1994_Raytheon_Databook 1994 Raytheon Databook

User Manual: 1994_Raytheon_Databook

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Raytheon Semiconductor

IIayIbeon

1994

Data,Book
AS£P
• Video
• ATE & Instrumentation
• Avionics Communication
• High Speed Communication
Standard Products
• Data Conversion
• Digital Signal Processing
• Linear
• PROMs
ASIC Arrays & Standard Cells
• Analog
• Mixed Analog-Digital

Raytheon Semiconductor

RayIIIaD-

1994
Data Book
ASSP
• Video
• ATE & Instrumentation
• Avionics Communication
• High Speed Communication
Standard Products
• Data Conversion
• Digital Signal Processing
• Linear
• PROMs
ASIC Arrays &Standard Cells
• Analog
• Mixed Analog-Digital

Advance Infonnatlon describes products that are not available at the time of printing. Specifications may change in any
manner without notice. Contact Raytheon for current information.
Preliminary Infonnallon describes products that are not in full production at the time of printing. Specifications are
based on design goals and limited characterization. They may change without notice. Contact Raytheon for current
information.
The information contained in this data bookhas been carefully compiled; however, it shall not by implication or otherwise
become part of the terms and conditions of any subsequent sale. Raytheon's liability shall be determined solely by its
standard terms and conditions of sale. No representation as to application or use or that the circuits are either licensed
or free from patent infringement is intended or implied. Raytheon reserves the right to change the circuitry and other
data at any time without notice and assumes no liability for inadvertent errors.

life Support Policy
Raytheon Semiconductor Division products are not designed for use in life support applications, wherein a failure or
malfunction of the component can reasonable be expected to result in personal injury. The user of Raytheon
components in life support applications assumes all risk of such use and indemnifies Raytheon Company against all
damages.

©Raytheon Company Semiconductor Division 1993.
All rights reserved.

In September 1992, Raytheon Semiconductor Division completed the acquisition of TRW LSI Products. Inc. in
La Jolla, California. The TRW products complement Raytheon's growing fine of signal processing and
multimedia components. The La Jolla operation will continue to develop and introduce leading-edge products
for the imaging, graphics, data acquisition and digital signal processing markets.

Contents
Section 1 - Product Innovations ...................................................................................................1-1
Multimedia •....•.........•...................................•....•..............•........................................•.................1-2
ATE & Instrumentation ................................................................................................................1-4
ASICs .........................................................................................................................................1-6
Section 2 - Application Specific Standard Products (ASSP) ...................................................... 2-1
MultimedialVideo/lmaging .........................................................................................•....••...•.......2-2
ATE & Instrumentation ..................................•...................•....•.........••....•.....••..•..•......•....•.•..•..2-247
Signal Synthesis ...............•..........•..•.........•....•.....••...•.....•..........•..••....•....•..........•....•....•...••....2-313
Avionics Communication ...................................•....................................................•..•....•........2-333
High Speed Communication ...................................................................................................2-371
Section 3 - Standard Products .....................................................................................................3-1
AID Converters .................................................................•.............................................•.........••.3-2
D/A Converters .....................................................................................................•..............•...3-137
Transform Products ........................................................................................................•.....•.•3-251
Vector Processing ...................................................................................................................3-333
Correlators ..............................................................................................................................3-353
Fixed-Point Arithmetic ...........•......................................................•.....•....•....•..........•................3-387
Memory/Storage ...............................................................................................••....•....•....•....•.3-429
Linear ..................................•........•...................•......................................................................3-441
PROMs .............................................................................•........................•.................•..•.......3-903
Small Signal Transistors ..........................•......................................................................•........3-925
Section 4- Analog/Mlxed-8lgnal Application Specific Integrated Circuits (ASIC) ..................... 4-1
Process Technologies ..................................................................................................•............•.4-1
Design Methodologies ..............................................•..................•..........•..........•...•................•....4-2
32 Volt Linear Arrays ...................................................................................................................4-4
Precision Complementary Arrays ...............•....................•...•.......................................................4-5
Precision Complementary Standard Cell Family ...•.........................•..........•.................................4-6
Test and Packaging ................................................................................................•.....••.......•....•4-8
Section 5 - Cross References .......................................................................................................5-1
Industry Type ..............................................................................................................................5-1
General .......................................................................................................................................5-2
Military Bipolar PROM .................................................................................................................5-5
Standardized Military Drawings ...................................................................................................5-6
MIL-M-38510 Products ................................................................................................................5-7
Section 6 - Quality & Reliability ....................................................................................................6-1
Section 7 - Application Notes .......................................................................................................7-1

Alphanumeric Index
Section 8 - Glossary .....................................................................................................................8-1
Section 9-Packaglng and Ordering Information .........................................................................9-1
Alphanumeric Index ..........................................................................................................................111

ii

Alphanumeric Index

Alphanumeric Index

Title

Page Number

DAC-08, 8-Bit High Speed Multiplying D/A Converter ...................................................................3-139
LH2111, Voltage Comparator .......................................................................................................3-697
LM101A1LH2101A, General Purpose Operational Amplifier .•.•.•.•...•••..•..••.•.•.••.•...••...••...••..•••....•.. 3-449
LM1 08A1LH21 08A, Precision Operational Amplifiers ..•...•.•...•••.•.•.••••.•.•.•••.•••••..••..••..•••.••.•..•...••.•.• 3-457
LM124/324, Single-Supply Quad Operational Amplifiers ...•....••.....•.......••.....•....•.....•.•.•.•..•••..•....•. 3-463
LM139/139A, 339/339A, Single-Supply Quad Comparators •.•..••.•.••••.••.•....••......•••...••.........•........ 3-673
LM148/348, Low Power Quad 741 Operational Amplifier •••...•.•••.••••.•...••..•.••...••...••..••.•....•........... 3-471
LM1851, Ground Fault Interrupter ...............................................................................................3-843
OP-07 Series, Instrumentation Grade Operational Amplifier •....••...•....•.•...•...•.•••••.•.•.••.••...••••.•.••.•. 3-483
OP-27, Low Noise Operational Amplifier .....................•....••....•.....•...•..............•.....•...................•..3-495
OP-37, Low Noise Operational Amplifier ........•.......•.......•...•.....•...••...•.•.....•...••.....••.••..•••.•.•.•.•.••.•.3-511
OP-77 Series, Precision Operational Amplifiers .•.....•...•.....•.........•....•...••....•...............•••.•.••••.••...•3-525

R29621/A, 512 x 8 Bipolar PROM ..........•........•.........•.....•........•.•...•...•••...•...•..•.•...•...•...•.••.••..••••..3-908
R29623/A, 512 x 8 Bipolar SPROM .............................................................................................3-909
R29631/A, 1024 x 8 Bipolar PROM ................•........••....•....•....•........................................•....•....•.3-910
R29633/A, 1024 x 8 Bipolar SPROM ...•........................•...•.....•...................................•....••...•....•.3-911
R29651/A, 2048 x 4 Bipolar PROM ..............................................................................................3-912
R29653/A, 2048 x 4 Bipolar SPROM ....................•.•.•......•..••..•.•.•...••...•.•.•.•...•.•..•••....•.............•...3-913
R29681/A, 2048 x 8 Bipolar PROM ..............................................................................................3-914
R29683/A, 2048 x 8 Bipolar SPROM ...........................................................................................3-915
R29771 , 4096 x 8 Bipolar PROM .................................................................................................3-916
R29773, 4096 x 8 Bipolar SPROM ................•.:..•.•...•........••.••...••.•....•....•....•.•..•...•....••....•...•....••..3-917
R29791 , 8192 x 8 Bipolar PROM .................................................................................................3-918
R29793, 8192 x 8 Bipolar SPROM ...............................................................................................3-919
RC3403A, Ground Sensing Quad Operational Amplifier ..............................................................3-535
RC4136, General Performance Quad 741 Operational Amplifier .....................................:..•••...••.• 3-547
RC4152, Voltage-to-Frequency Converter ...................................................................................3-799
RC4153, Voltage-to-Frequency Converter ...................................................................................3-809
RC4156/4157, High Performance Quad Operational Amplifier •........•..•..•..•.•...•....••...•..............•... 3-563
RC4190, MicropowerSwitching Regulators .................•.....•.•.•.........•...•.•.•..•..•••..•.•....•.....•.•..•....•. 3-723
RC4191/419214193, Micropower Switching Regulators .....................................•....•....••...•••.••.••.•.3-749
RC4194, Dual Tracking Voltage Regulators ....•....•.....•...•.........•.•.•.•.•.•.•.•.•..••••..•.•..•.••.•••..••••••.••.•. 3-757
RC4195, Fixed ±15V Dual Tracking Voltage Regulator ••...•••.••••.•.•.•.•••••.•.••••...•.•••.••..•.•.••.•••••..••••. 3-769
RC4200, Analog Multiplier ...........................................................................................................3-871
RC4207, Precision Monolithic Dual Operational Amplifier .••....•..•.•...•...•.•...•...•..•.•.•....•.•.•....••...•.•.3-595
RC4277, Dual Precision Operational Amplifiers ....•...•.•..••...•.•..••...•.....•.•.•....••.••.••..•••..•••..•••.•••••.•.3-603
RC4391 , Inverting and Step-Down Switching Regulator ...............................................................3-779
RC4444, 4 x 4 x 2 Balance Switching Cross Point Array ..............................................................3-893
RC4558, High-Gain Dual Operational Amplifier •..••...•...•.•..•..••..........•.....••..•.•.•.•.....•...•••...•••...••...•3-575
RC4559, High-Gain Dual Operational Amplifier ............................................................................3-585
RC4741 , General Purpose Operational Amplifier .•.•.•.•...•...•.•••••.•...•••.•.•••••.•.•.••••.••••.•.•.••••.•.••..•••.• 3-629
iii

Alphanumeric Index

Title

Page Number

RC5532/5532A, High Performance Dual Low Noise Operational Amplifier ................................... 3-637
RC5534/5534A, High Performance Low Noise Operational Amplifier ........................................... 3-645
RC7310, High Speed Driver .........................................................................................................2-249
RC7311, 250 MHz ATE Pin Electronics Driver .............................................................................2-257
RC731517315T, Three-State ATE Pin Electronics Driver .............................................................. 2-265
RC7316, Three-State ATE Pin Electronics Driver ......................................................................... 2-273
RC733117332, Active Load ..........................................................................................................2-281
RC734117342, High Speed Dual Comparator ...............................................................................2-287
RC7351, Parametric Measurement Unit .......................................................................................2-293
RC73687, High Speed Dual Comparator .....................................................................................2-303
RCC700, ATMIESCON IFibre ChannellSSA Transceiver ............................................................. 2-373
RCC521, STS-3/STM-1 Synchronizer and Framer ......................................................................2-387
REF-01, +10V Precision Voltage References ...............................................................................3-705
REF-02, +5V Precision Voltage References .................................................................................3-713
RM2207, Voltage-Controlled Oscillator ........................................................................................3-853
RM2211, FSK Demodulator/Tone Decoder ..................................................................................3-861
RM3182, ARINC 429 Differential Line Driver ................................................................................2-335
RM3182A, ARINC 429 Differential Line Driver ............................................................................. 2-343
RM3183, Dual ARINC 429 Line Receiver .....................................................................................2-351
RM3283, Dual ARINC 429 Line Receiver .....................................................................................2-361
RM741 , General Purpose Operational Amplifier ...........................................................................3-653
RM747, General Purpose Operational Amplifier ...........................................................................3-661
RV4140, Low Power Two-Wire Ground Fault Interrupter Controller .............................................. 3-823
RV4141, Low Power Ground Fault Interrupter ..............................................................................3-829
RV4145, Low Power Ground Fault Interrupter ..............................................................................3-835
TDC1012, Monolithic D/A Converter, 12-Bit, 20 Msps .................................................................. 3-153
TDC1016, Video Speed D/A Converter, 10-Bit, 20 Msps .............................................................. 3-173
TDC1018, D/A Converter, 8-Bit, 200 Msps ...................................................................................3-183
TDC1020, High-Speed Monolithic AID Converter, 10-Bit, 20 Msps .................................................. 3-5
TDC1035, Monolithic Peak Digitizer, 8-Bit, 20 ns Full Response Peak Width ................................:3-17
TDC1038, Monolithic Video AID Converter, 8-Bit, 20 Msps, Low Power ......................................... 3-25
TDC1041 , Monolithic D/A Converter, 10-Bit, 20 Msps, 12 ns Settling Time .................................. 3-195
TDC1044, Monolithic Video AID Converter, 4-Bit, 25 Msps ............................................................ 3-35
TDC1046, Monolithic Video AID Converter, 6-Bit. 25 Msps ............................................................ 3-45
TDC1047, Monolithic Video AID Converter, 7-Bit, 20 Msps ............................................................3-53
TDC1048, Monolithic Video AID Converter, 8-Bit. 20 Msps ............................................................ 3-63
TDC1049, High Speed AID Converter ............................................................................................3-73
TDC1058, Monolithic Video AID Converter, 8-Bit, 20 Msps, Low Power ......................................... 3-83
TDC1112, Monolithic D/A Converter, 12-Bit, 50 Msps, 12 ns Settling Time to 0.1% ..................... 3-207
TDC1141, Monolithic D/A Converter, 10-Bit, 50 Msps, 12 ns Settling Time .................................. 3-225
TDC1147, Monolithic Video AID Converter, 7-Bit, 15 Msps ............................................................ 3-95
TDC331 0, Video D/A Convertre, 1O-Bit, 40 Msps ......................................................................... 3-239
TMC1173, Low voltage CMOS AID Converter ............................................................................. 3-105
TMC1175, Monolithic CMOS AID Converter, 8-Bit, 30 Msps ........................................................ 3-121
TMC2011, Programmable Digital Delay, 3-18 x 8 Bit, 40 MHz ...................................................... 3-431
TMC2023, Correlator, 65 x 1 Bit, 30 MHz .....................................................................................3-355
TMC208K, Multiplier, 8 x 8 Bit, 45 ns, Two's Complement ...........................................................3-389
TMC2111, Programmable Digital Delay,1-16x 8 Bit, 40 MHz3-431 ............................................. 3-431
iv

Alphanumeric Index

Title

Page Number

TMC2208, Multiplier-Accumulator, 8 x 8 Bit, 40 ns .......................................................................3-399
TMC22071, Genlocking Video Digitizer ............................................................................................2-5
TMC22X9X, Digital Video Encoders/Layering Engine ••••••••.••••••••••••••••••••••••••••••.••••••••••..•••••••••••••••• 2-27
TMC2210, Multiplier-Accumulator, 16 x 16 Bit, 65 ns ••••••••••.•••••.••••••••••••••••••.••••.•••••••••••.••••••••.••••• 3-409
TMC2220, Correlator, 32 x 4 Bit, 20 MHz .....................................................................................3-369
TMC2221, Correlator, 128 x 1 Bit, 20 MHz ...................................................................................3-369
TMC2242, Half-Band Filter, 12116-Blt, 40 MHz ...............................................................................2-95
TMC2243, Video Filter,10 x 10 BIt, 3 Tap, 20 MHz ......................................................................3-109
TMC2246, Image Filter, 10 x 11 Bit, 30 MHz ................................................................................3-123
TMC2250, Matrix MultiplierlFlR Filter,12 x 10 BIt, 9 Element, 40 MHz ••••••••••••••••••••••••••.•••••••••••••• 3-335
TMC2255, Convolver, 2D, 5 x 5, 8-Bit, 30 MHz ............................................................................2-149
TMC2272, Color Space Converter, 36-Bit, 40 MHz ••••••••••••••.•••.•••••..•••••••••••••.•••••••••••••••.••.••..••••••• 2-169
TMC2301, Image Resampling Sequencer, 18 MHz .....................................................................2-187
TMC2302, Image Manipulation Sequencer, 40 MHz ....................................................................2-213
TMC2310, FFT Controller, Arithmetic Unit, 1K Point, 20 MHz ...................................................... 3-253
TMC2311, Fast Cosine Transformer, 12-bit, 15 MHz ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••. 3-301
TMC2330, Coordinate Transformer, 16 x 16 Bit, 25 MOPS ..•••.•••••••••••.••••••••••••.••.•••.••••..••.••••••••••• 3-319
TMC2340, Digital Synthesizer, Dual 16-Blt, 20 MOPS •••••.••••••••••••••••.••.•....•••••.••••••.•••...••.•••••••••••• 2-315
TMC28KU, Multiplier, 8 x 8 Bit, 45ns, Unsigned-Magnitude .........................................................3-389
TMC3211, Integer Divider, 32 x 16 Bit, 20 MOPS ........................................................................3-421

1IaVIII8.

v

Alphanumeric Index

vi

Section 1 - Product Innovations

Section 1
Product Innovations

We have accelerated the development of new products
at Raytheon Semiconductor, to provide complete, costeffective solutions to complex problems. We have
developed highly integrated solutions for the Multimedia!
Imaging and Automatic Test Equipment markets.

When you have the need for custom mixed-signalICs,
our family of Complementary Bipolar Tile Arrays,
CBiCMOS and Standard Cells offer attractive solutions,
which are also highlighted.

We have highlighted some of the leading products in
these areas on the following pages.

Contents
Multimedia
Digital Video Encoder ..........................................................................................................,................... 1-2
Genlocking Video Digitizer .......................................................................................................................1-3
3V/5V Video ND Converter .....................................................................................................................1-3
Automatic Test Equipment Pin Electronics
Pin Drivers ...............................................................................................................................................1-4
Fast Comparators ....................................................................................................................................1-5
Parametric Measurement Unit .................................................................................................................1-5
Communications
ATMIESCONTM/Fibre ChannellSSATM Transceiver ................................................................................. 1-6
STS-3/STM-1 Synchronizer and Framer .................................................................................................. 1-6
ASICs
CBiCMOS Linear Tile Arrays ...................................................................................................................1-7
CBiCMOS Standard Cells ........................................................................................................................1-8

For More Information calI1..aOO-722-7074.

Raytheon Semiconductor

1-1

Section 1 - Product Innovations

TMC22090/22190ITMC22190/22191 Digital Video Encoder and Layering Engine
Features
•
•
•
•

•
•
•

All digital video encoding
NTSC-M. PAL-B. G. H. I. M. N formats
Internal digital oscillators. no crystals required
Multiple input formats supported:
- 24-bit and 15-bit GBRlRGB
- YCSCR 4:2:214:4:4
- Color indexed
30 overlay colors (TMC22190rrMC22191)
Fully programmable timing
Supports pixel rate of 10 to 15 Mpps
256 x 8 x 3 color look-up tables (bypassable on
TMC2219X)
8-bit mask register

•
•
•
•
•

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•
•
•
•
•
•
•
•
•
•
•

8-bit composite digital video input
Hardware and 24-bit data keying
Synchronizes with TMC22071 Genlocking Video
Digitizer
8:8:8 video reconstruction
SMPTE 170M NTSC or CCIR report 624 PAL
compatible
PAUM
Simultaneous S-Video (VIC) NTSc/PAL output
10-bit D/A conversion (three channels)
Controlled edge rates
Power-down mode
Built-in color bars and modulated ramp test signals
JTAG (IEEE Std 1149.1-1990) test interface
Single +5V power supply
B4lead PLCC package

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Raytheon Semiconductor

For More Information call 1-800-722-7074.

Section 1 - Product Innovations

TMC22071 Genlocking Video Digitizer
Features
•

•
•

•
•
•
•

Fully integrated acquisition
3-Channel video input multiplexer
Two-stage video clamp
Automatic gain adjustment
Sync detection and separation
Genlock to NTSC or PAL inputs
Clock generation
8-bit video AID converter
Microprocessor interface
Line-locked pixel rates
12.27 MHz NTSC
MICROPiIOCESSOft
MEfFACi
- 13.5 MHz NTSC or PAL
- 14.75 MHz and 1.50 MHz PAL
Direct interface to TMC22090fTMC22190 encoders
Built-in circuitry for crystal oscillator
No tuning or external voltage reference required
68 lead PLCC package

ANALOG
MEfFACE

TMC1173 2.7 to 3.6 Volt 8-Bit 10 Msps Converter
Features

•••
••
••
•••

8-bit resolution
5 and 10 Msps conversion rate
Integral track/hold
Differential linearity error <::1:0.5 LSB
Single +2.7 to +3.6 volt power supply
<90 mW power diSSipation at 3.6 volts
Differential phase <0.5°
Differential gain <1 %
Three-state 3V
compatible outputs
Very low cost

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1-3

Section 1 - Product Innovations

RC7311 250 MHz ATE Pin Electronics Driver
Features

High output slew rate (2 V/ns minimum)
•• Wide
output voltage range (-3.0V to i8V). and up to
10 Vp-p swings
MHz minimum operation for ECl swings
•• 2S0
Wide input common mode range for ease of
interface to ECl as well as m and CMOS
short-circuit protection with current limiter
• Output
and thermal shutdown

••
••

•

100 rnA dynamic switching current drive
Absolute slew rate control
Available in 28-pin PlCC
low output voltage offset (30 mV) and output offset
drift (0.1 mVI"C typ.)
low input bias current (1 pA typ.) and current drift
(40 nAI"C) for output level program allows direct
coupling to a DAC output

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Features
•
•
•
•
•
•
•
•
•
•
•
•
•

1-4

High output slew rate (1.8 V/ns typ.)
Wide output voltage range (-2.SV to +7V). and up to
9.S Vp-p swings
Three-statelhigh impedance output
High repetition rate (250 MHz for ECl swings)
low output offset (20 mV typ.) and output offset drift
(0.1 mVI"C typ.)
Low leakage (10 nA typ.) and low output capacitance
(3 pF typ.) in high impedance inhibit mode
RC731STEl is pin-for-pin compatible with AD1322
High speed differential inputs with wide common
mode range for ease of interface to ECl as well as
m and CMOS levels
Output short circuit protection (safe operating area
protection with current limiting and thermal shutdown)
100 mA typo dynamic current drive capability
Absolute slew rate control
Available in 28-pin PlCC or 16-pin gullwing lead
package
Packaged parts available unterminated (RC731S) or
son series terminated (RC7315T) configurations

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SecUon 1 - Product Innovations
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RC7341/RC7342 High Speed Dual Comparator
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Features
•
•
•
•
•
•
•
•
•
•
•
•

12V max differential input voltage
Low propagation delays: 2.0 ns maximum
Low delay dispersion (:1:50 ps typ.) and drift (4 ps/"C max.)
:1:5 mV maximum input offset and 10 J.1VfCmax. drift
2 JlA typical bias current; :1:50 pA typo In disable mode
Common mode rejection ;::70 dB
Input disable mode
2 pF maximum input capacitance (RC7341)
Optional latch function
Available with common threshold input VlAB for lowest
Input capacitance (RC7341) or two independent
comparators (RC7342)
RC7342 is pln-for-pin compatible with 9687 comparators
Available in 16-pin SOIC, 20-pin PLCC or 16-pin PDIP

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'"'"

~>

mZ
,,>

CLKOUT
LDV
PXCK
EXT PXCK
PXCKSEL

DDS OUT
CB'I1'
PFDIN

"~

~:!!
m"
"pl
)10

~g

"

243808

Figure 1. Logic Symbol
For More Information call 1-800-722-7074

Raytheon Semiconductor

2-5

TMC22071
Figure 2. Functional Block Diagram

CVBS.,.

GVSYNCI

GHSYNCI

PXCK
LOV
VALID

MICROPROCESSOR
INTERFACE

ANALOG

INTERFACE

DOS I PIXEL CLOCK INTERFACE

243818

General Description
The TMC22071 is a fully-integrated genlocking
video AID converter which digitizes NTSC or PAL
baseband composite video under program control.
It accepts video on three selectable input channels,
adjusts gain, clamps to the back porch, and
digitizes the video at a multiple of the horizontal
line frequency. It extracts horizontal and vertical
sync, measures the subcarrier frequency and
phase (relative to the sampling clock), and provides
this data along with digital composite video data
over an a-bit digital video port. Two sync outputs
(GHSYNC\ and GVSYNC\) are also provided. It
generates 1x (LDV) and 2x (PXCK) pixel clocks
(PXCK) for data transfer. PXCK also serves as a
master clock for the companion TMC22x9x
Encoders.
Operating parameters are set up via a standard
microprocessor port. Provisions have been made
for internal or external voltage reference operation.

2-6

Timing
The TMC22071 operates from an internallysynthesized clock, PXCK, which runs at twice the
pixel data rate. The nominal pixel rates may be set
to 12.27 Mpps for NTSC, 13.5 Mpps for NTSC and
PAL, and 14.75 Mpps or 15.0 Mpps for PAL
operation.
Video Input
Three high-impedance video inputs are selected by
an internal multiplexer under host processor
control. The device accepts industry-standard
video levels of 1.23 Volts (sync tip to peak color).
Good channel-to-channel isolation allows active
video on all three inputs simultaneously. Antialiasing filtering (if used) and line termination
resistors must be provided externally. The input
selection is controlled by two bits in the Control
Register.

Raytheon semiconductor

For More Information calI1-80Q-722-7074.

TMC22071
Analog Clamp
The front-end analog clamp ensures that the input
video falls within the active range of the AID
converter. The digitized composite video output is
clamped to the back porch by a secondary digital
clamp.

The reference voltages to the AID converter are set
up by internal D/A converters under automatic
control during genlock acquisition. These voltages
determine the gain and offset of the AID converter
with respect to the video level presented at its
input.
Low-pass Filter

Automatic Gain Adjustment
Since video signals may vary substantially from
nominal levels, the TMC22071 performs an
automatic level setting routine to establish correct
signal amplitudes for digitizing.
The TMC22071 relies upon the presence of the
sync tip-to-back porch voltage to determine the
gain required for the input video signal.
Sync tip compression or clipping is often affected
by APl (Average Picture level) variation. Rather
than tracking minor variations in sync tip amplitude
and constantly adjusting video gain, the TMC22071
establishes proper signal amplitudes during initial
genlock acquisition, and then (optionally) holds the
gain constant. This results in a stable picture
under variable Signal conditions.
Improper termination of video cables (usually
double termination) is handled in the TMC22071 by
a selectable gain of +1.0 or +1.5. The higher gain
is used to amplify a doubly-terminated signal which
is reduced in amplitude by 2/3.
If the input signal levels are well controlled, the
automatic gain adjustment can be disabled and the
gain held at its nominal value (+ 1.0 or + 1.5).
Analog-to-Dlgital Converter
The TMC22071 contains a high-performance 8-bit
AID converter. Its gain and offset are automatically
set as a part of the automatic gain adjustment
process during initial signal acquisition, and require
no user attention.

For More Information call 1-800·722·7074.

The digitized composite video stream is digitally
lOw-pass filtered to remove chrominance
components from the sync separator. Filtering
provides robust operation by optimizing the signalto-noise ratio of the synchronizinglblanking portion
of the video, improving the accuracy of the back
porch blanking level detector.
A digital sync separator provides the output sync
signals, GHSYNC\ and GVSYNC\, and times
internal operations.
Horizontal Phase-Locked Loop
A phase-locked loop generates PXCK, at twice the
pixel rate. The reference signal for the horizontal
phase-locked loop is generated by the Direct
Digital Synthesizer (DDS). The DDS output is
constructed with an internal D/A converter and is
output from the TMC22071 via the DDS OUT pin.
This signal is passed through an external lC filter
and input to the horizontal phase-locked loop.
The phase of the DDS output is proportional to the
phase difference between PXCK and the horizontal
sync of the incoming signal.
A 20 MHz clock is required to drive the DDS. This
may be input to the TMC22071 via CMOS levels on
the ClK IN pin. Alternately, a 20 MHz crystal may
be directly connected between ClK IN and ClK\
OUT with tuning capacitors to activate the internal
crystal oscillator circuitry.

Raytheon Semiconductor

2·7

TMC22071
Subcarrler Phase-Locked Loop

Pin Functions

A fully-digital phase-locked loop is used to extract
the phase and frequency of the incoming color
burst. These frequency and phase values are
output over the CVBS bus during the horizontal
sync period.

Video Input
VIN1 -3

Video inputs, 1.25 Volts peak-to-peak,
sync tip to peak color.

Clocks
Back Porch Digital Clamp
CLK IN

20 MHz CMOS clock input to DDS.
This pin may also be used along with
CLK\ OUT for c!irectly connecting
crystals.

CLK\ OUT

Inverted DDS clock output. This pin
may also be used along with CLK IN for
directly connecting a crystal.

LDV

Delayed pixel clock output. LDV runs
at 1/2 the rate of PXCK and its rising
edge is useful for transferring CVBS
digital video from the TMC22071 to the
TMC22x9x Digital Video Encoders.

PXCK

2x oversampled line-locked clock
output.

A digital back-porch clamp is employed to ensure a
constant blanking level. It digitally offsets the data
from the AID converter to set the back porch level
to precisely 40 h for PAL and3Ch for NTSC.
Digitized Video Output
The digitized 8-bit video output is provided over an
8-bit wide CVBS data port, synchronous with PXCK
and LDV. Subcarrier frequency, and subcarrier
phase data are transmitted over CVBS7 _0 during
the horizontal sync tip period.
Microprocessor Interface
Since microprocessor buses are notoriously "noisy·
from a wide-band analog point of view, the
microprocessor interface bus is only one bit wide,
rather than the more customary eight. The
operation of this bus is similar to other buscontrolled devices except that the TMC22071
internal Control Register is accessed one bit at a
time.
A sequence of 47 bits is written to or read from the
LSB of a standard microprocessor port. Writing to
or reading from the secondary address results in
the transfer of data to or from the internal shift
register.
The RESEn input, when LOW, sets all internal
state machines to their initialized conditions.
Returning the RESEn pin HIGH starts the signal
acquisition sequence which lasts until locking with
the gain-adjusted and clamped video signal is
achieved.

2-8

EXT PXCK Input for external PXCK clock source.
PXCK SEL Select input for internal or external
PXCK. When HIGH, the internally
generated line-locked PXCK is
selected. When LOW, the external
PXCK source is enabled.
VAll 0

This output; when HIGH indicates that
incoming horizontal sync has been
detected and is within the +/-16 pixel
window in time established by previous
sync pulses. When LOW, it indicates
that incoming horizontal sync has not
bee found within the expected time
frame.

INn

This output is LOW if the internal
horizontal phase lock loop is unlocked
with respect to incoming video for 128
or more lines per field. After lock is
established, INn goes HIGH.

Raytheon Semiconductor

For MOre Information call 1-800-722-7074.

TMC22071
R/w\

Digital Video Interface
GHSYNC\

When the TMC22071 is locked to
incoming video, the GHSYNC\ pin
provides a negative-going pulse after
the falling edge of the horizontal sync
pulse. There is a fixed number of
PXCK clock cycles between adjacent
falling edges of GHSYNC\.

GVSYNC\

When the TMC22071 is locked to
incoming video, the GVSYNC\ pin
provides a negative-going edge after
the start of a vertical sync pulse.

CVBS7 _0

8-bit composite video data is output on
this bus at 1/2 the PXCK rate. During
the horizontal blanking interval, field ID,
subcarrier frequency, and subcarrier
phase are available on this bus.

Analog Interface
V REF

+1.23 Volt reference. When the
internal voltage reference is used, this
pin should be decoupled to Ac3ND with
a 0.1 J,LF capacitor. An external +1.2
Volt reference may be connected here,
overriding the internal reference
source.

COMP

Compensation for DDS D/A converter
circuitry. This pin should be decoupled
to V DDA with a 0.1 J,LF capacitor.
Decoupling points for AID converter
voltage references. These pins should
be decoupled to AGND with a 0.1 J,LF
capacitor.

Microprocessor Interface
Microprocessor data port. All control
parameters are loaded into and read
back from the Control Register over this
1-bit bus.

CS\

RESET\

When R/w\ and Ao are LOW, the
microprocessor can write to the Control
Register over Do. When R/W\ is HIGH
and Ao is LOW, the contents of the
Control Register are read over Do.

Loop Filter Interface
DDS OUT

Analog output from the internal Direct
Digital SyntheSizer D/A converter.

Microprocessor address bus. A LOW
on this input loads the I/O Port Shift
Register with data from Do and CS\. A
HIGH transfers the I/O Port Shift
Register contents into the Control
Register on the last falling edge of CS\.

PFD IN

Analog input to the Phase/Frequency
Detector of the horizontal phase-locked
loop

C ByP

When CS\ is HIGH, Do is in a highimpedance state and ignored. When
CS\ is LOW, the microprocessor can
read or write Do data into the Control
Register.

Decoupling point for the internal
comparator reference of the
Phase/Frequency Detector. This pin
should be decoupled to AGND with a
0.1 J,LF capacitor.

Power Supply

Bringing RESET\ liOW forces the
internal state machines to their starting
states, loads the Control Register with
default values, and disables outputs.
Bringing RESET\ HIGH restarts the
TMC22071.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

Positive power supply to analog
section.
Positive power supply to digital section.
Ground for analog section.
Ground for digital section.

2-9

TMC22071
Table 1. Package Interconnections
Signal Type Name

Function

Video Input

V1N1 -3

Composite Video Input

Clocks

CLKIN
CLK\OUT
PXCK
LDV
EXTPXCK
PXCKSEL

20 MHz DDS clock input
Inverted clock output
2x Pixel clock output
Pixel clock output
External PXCK input
PXCK source select

CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

51
53
19
17
54
46

Digital Video GHSYNC\
GVSYNC\
CVBS7 _0

Horizontal sync output
Vertical sync output
Composite output bus

CMOS
CMOS
CMOS

12
13
11-9,6-2

IlP I/O

Do
Ao
CS\
RESEn
RrM
INn
VALID

Data I/O port
IlP port control
Chip select
Master reset input
Bus readlwrite control
Interrupt output
HSYNC locked flag

TIL
TIL
TIL
TIL
TIL
TIL
TIL

Analog

VREF
COMP
Rr,Rs

VREF input/output
Compensation capacitor
AID Vref decoupling

PLL Filter

DDS OUT
PFDIN
C syp

Internal DDS output
HQrizontal PLL input
Comparator bypass

0.1 IlF

Power

VDDA
VDD

Analog power supply
Digital power supply

+5V
+5V

23,25,26,30,33,40,47
1,7,18,22,52,
58,59,63

Ground

AGND

Analog ground

O.OV

DGND

Digital ground

O.OV

24,27,32,35,37,39,
41,44,49,
8,15,16,20,21,50,
55-57, 65, 68

2-10

Value
1.23Vp-p

+1.23 V
0.11lF
0.1 IlF

Raytheon Semiconductor

Package Pin
34,31,29

66
60
62
64
61
67
14
38
48
36,28
45
43
42

For More Inionnalion call 1-800-722-7074.

TMC22071
Control Register Bit Functions
Bit

Mnemonic Function

0

SRESET

1-3

FORMAT

Bit

Software reset. When LOW,
resets and holds internal
state machines, resets
Control Register with
previously written values,
and disables output drivers.
When HIGH, SRESET starts
and runs state machines,
PXCK, and enables outputs.

Mnemonic Function
LDV cycles. Bit 24 is the
MSB.

25

AGC

AGC operation control.
After initial H and V sync
acquisition, AGC operation
is continuous for two fields
and then held when this bit
is LOW. When HIGH, AGC
is triggered for two fields
and then held.

26

FRERUN

When HIGH, a free-running
PXCK is generated,
independent of incoming
video. When LOW, PXCK is
locked to incoming video.

TEST

Factory test control bits.
These should be set LOW.

30

BLOCK

Block sync enable. When
HIGH, block sync is
accepted and sync tip
clamping during the vertical
Interval is disabled.

31

CVBSEN

CVBS bus enable. When
LOW, the CVBS 7_0 ,
GHSYNC\, and GVSYNC\
outputs are in a highimpedance state. When
HIGH, they are enables.

32

TEST

Factory test control bit. This
should be set LOW.

33

BPFOUT\

Burst phase / frequency
output control. When HIGH,
GRS is disabled. When
LOW, burst phase and
frequency information is
output on CVBS3_0 .

Input signal format select.
000
001
010
011
1xx

NTSC at 12.27 Mpps.
NTSC at 13.5 Mpps.
PALA at 14.75 MPPS.
PALs at 15.0 Mpps.
PAL at 13.5 Mpps.

4-6

TEST

Factory test control bits.
These should be set LOW.

7,8

SOURCE

Video source select.
00
01
1x

27-29

V1N1 ;
V 1N2,
V 1N3

9

VGAIN

Video gain. When LOW,
gain is set to + 1.0. When
HIGH, gain is set to +1.5.

10-16

TEST

Factory test control bits.
These should be set LOW.

17-24

LEADLAG

This control word allows the
HSYNC to be time-shifted
-122 to + 132 LDV cycles.
When LEAD LAG is 7B h ,
HSYNC and incoming video
are in alignment. A value of
83 h delays HSYNC eight
LDV cycles. A value of 73 h
advances HSYNC eight

For More Infonnation call 1-800-722·7074.

Raytheon Semiconductor

2-11

TMC22071
Bit

Mnemonic Function

34

DCLAMP

Bit

Digital clamp enable. The
digital clamp is enabled
when DCLAMP is HIGH and
disabled when LOW.

35-39

TEST

Factory test control bits.
These should be set LOW.

40-43

STVAL

Sync tip value. When
DCLAMP is HIGH and
STVAL is set to its default
value 3 h,the output sync
level is 3 h for NTSC and 7h
for PAL. Bit 43 is the MSB.

44-45

46

TEST

Mnemonic Function

Factory test control bits.
These should be set LOW.

GRSONLY When the horizontal phase
lock loop is unlocked and
this Control Bit is LOW, all
CVBS data is forced LOW
except the GRS signals.

The presence of GRS also
depends upon bit 33.
Status Bits (read only)
47

COLOR

Burst present status bit.
This bit is LOW when no
burst is present on the input
video. It is HIGH when
burst is present.

48-55

BLKAMP

Blanking amplitude status
bits. These eight bits report
the actual blanking level.

56

LOCK

Genlocked status bit. When
LOW, the TMC22071 is not
locked to an input signal.
When HIGH, lock has been
achieved.

57-58

TEST

These are read-only bits for
testing purposes only.

Figure 3. Control Register Map

2-12

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22071
Control and Status Registers
The TMC22071 is controlled by a single 47-bit
long Control Register. Access to the Control
Register is via the I/O Port Shift Register
arranged as shown in Figure 4. The Control
Register can be read and written, pennitting
software modification and examination of its
contents. The 12-bit Status Register is read-only
and accessed through the same I/O Port Shift
Register. Reading the Status Register yields
information about blanking level, subcarrier
presence, and whether or not PXCK is locked or
unlocked with respect to the line rate.
The host processor writes data into the
TMC22071 using only one bit of the
microprocessor's data and address bus. Once
the shift register has input and positioned the 47
bits of desired data (bit 46 first, bit 0 last), a HIGH
on Ao and a LOW on RIW\ when CS\ falls
transfers the I/O Port Shift Register contents to
the Control Register. The I/O Port Shift Register,
Control Register and Status Register are
governed by CS\ , RIW\ , and Ao. RIW\ and Ao
are latched by the TMC22071 on the falling edge
of CS\ and data input Do is latched on the rising
edge of CS\. Data read from Do is enabled by the
falling edge of CS\ and disabled by the rising
edge ofCS\.
The full sequence of 47 bits of Control Register
data must be written each time a change in that
data is desired. All or a few of the Control and
Status Register bits may be read, but the
sequence always begins with bit 58 of the Status
Register.

Table 2. MIcroprocessor Port Control

Ao

RJW\

0

0

0

1

1

0

1

1

ActIon
Write data from Do into 1/0
Port Shift Register
Read Do data from last stage
of I/O Port Shift Register
Transfer I/O Port Shift
Register contents to Control
Register
Enables continuous update of
status bits in I/O Port Shift
Register

Figure 5. Data Write Sequence

CS\

Ao _ _ _ _+--J

Figure 6. Data Read Sequence

cS\

Figure 4. Control and Shift Register Structure

D.

Ao

------fIo-...J

Control Register

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-13

TMC22071
Horizontal Timing

Programming the TMC22071

Horizontal line r.ate is selectable, and is determined
by the FORMAT control bits (12.27 Mpps for NTSC,
13.5 Mpps for NTSC and PAL, and either 14.75 or
15.0 Mpps for PAL). Figure 7 illustrates the
horizontal blanking intervai. Figure 8 completes the
definition of timing parameters with vertical blanking
interval detail.

Upon power-up after bringing RESEl\ LOW, the
TMC22071 Control Register is set to default values
as shown in the top entry oITable 4. These default
values do not necessarily render the TMC22071
operational in any specific application. Before the
TMC22071 is expected to acquire input video, its
Control Register must be loaded with data that is
specific to its use.

Figure 7. Horizontal Sync Timing

Figure 9. Output Data vs. Input Video Level
Peak Chromlnance~
Peak Luminance ~

00"00,,
27035A

Figure 8. Vertical Sync Timing

Video In

GHSYNC\
(Odd Field)

GHSYNC\~

(Even Field)

2-14

u

u-

2500SA

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22071
Table 3. TMC22071 Timing Options

Standard

Field
Rate
(Hz)

Line
Rate
(kHz)

Pixel
Rate
(Mpps)

PXCK
Frequency
(MHz)

Pixels
Per
Line

NTSC
NTSC-601

59.94
59.94

15.734264
15.734264

12.2727+
13.50

24.54+
27.0

780
858

PALA
PALs
PAL-601

50.00
50.00
50.00

15.625
15.625
15.625

14.75
15.00
13.50

29.5
30.0
27.0

944
960
864

Table 4. Control Register Example Data
Standard

Control Register Data (Bit 56 ................ Bit O)
46
42
38
34
26
14
30
18
22

10

6

2

DEFAULT 0000 0110 0000 1001 0000 0010 0000 0000 0000 0000 0000 001
NTSC
0000 0110 0000 1001 0000 0010 0000 0000 0000 OOxx 0000 000
NTSC-601 0000 0110 0000 1001 0000 0010 0000 0000 0000 OOxx 0000 010
PALA
PALs
PAL-601

0000 0110 0000 1001 0000 0010 0000 0000 0000 OOxx 0000 100
0000 0110 0000 1001 0000 0010 0000 0000 0000 OOxx 0000 110
0000 0110 0000 1001 0000 0010 0000 0000 0000 OOxx 0001 000

For More Information call 1-800-722-7074.

. Raytheon Semiconductor

2-15

TMC22071
eVBS Bus Data Formats
The CVBS bus outputs a Genlock Reference Signal
(GRS) along with the 8-bit digital composite video
data. The range of output data versus versus video
input voltage is illustrated in Figure 9 where sync tip
and blanking levels are controlled by the digital backporch clamp of the TMC22071. During horizontal
sync, the TMC22071 outputs field identification,
subcarrier frequency, and subcarrier phase
information on the CVBS bus.
Field identification is output on CVBS2 _0 . The LSB,
CVBSo• will be LOW during odd fields and HIGH for
even fields. When NTSC operation is selected,
CVBS 1_0 count 00,01,10,11 for fields 1 through 4

respectively. When PAL operation is selected,
CVBS2 _0 count 000,001,010, etc. to 111 for fields 1
through 8, respectively.
Subcarrier frequency is sent out in a 24-bit binary
representation in six 4-bit nibbles on CVBSa-o.
Subcarrier frequency data, f23-0 , is identical to the
pre-programmed BSEED value used in the
TMC22071 to lock the subcarrier phase-locked loop
to the incoming subcarrier frequency.
Subcarrier phase, <1»23-0' is also sent out in a 24-bit
binary representation in six 4-bit nibbles on CVBS3 -o.
Bit <1»23 is the MSB.

Figure 10. Genlock Reference Signal (GRS) Format.

PXCK

GHSYNC\

I.. ~I"

FIELD

FREQUENCY--+l+---

IDE~TIFICATION

24383A

Figure 11. eVBS Bus Video Data Format
PXCK

GHSYNC\

LOV

CVB~:o

PIXEL 1

24382B

2-16

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

TMC22071
Figure 12. Microprocessor Port - Write Timing

CS\
R/W\

24377A

Figure 13. Microprocessor Port - Read Timing

CS\
R/W\

Do----------4-~"'-lo:....ll-__J

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-17

TMC22071
Figure 14. Equivalent PFD IN Circuit

Figure 16. Equivalent DDS OUT Circuit

Voo

Voo

PFD IN 0---.---+--+-1 ...----+-.....

CB~ ~jt-~-r--r====t===~

. . - - - - . - . DDS OUT

+2.4 V

27032A
27033A

Figure 15. Equivalent Digital Input Circuit

Figure 17. Equivalent Digital Output Circuit
Voo

t-----+--o Output

Input

-=

27011A

27014A

Figure 18. Transition Levels for Three-State Measurements

CS\

I
~

tHOM
..---..

tooz
~ 0.5 V

I

Hi-Z

iO.5 V

2.0V

....

0.8 V
27034A

2-18

Raytheon Semiconductor

For More Infonnalion calI1.aoo·722·7074.

TMC22071
Absolute maximum ratings (beyond which the device may be damaged) 1
Power Supply Voltage ...............................................................................................................-0.5 to +7.0V
Input Voltage ........................................................................................................................-0.5 to V oo +0.5V
Digital Outputs
Applied VOltage2 ......................................................................................................... -0.5 to Voo+0.5V
Forced Current3 .4 ............................................................................................................ -6.0 to 6.0 mA
Short Circuit Duration
(Single output in HIGH state to GND) ..................................................................................... l second
Temperature
Operating, case ................................................................................................................-60 to +130°C
Operating, Junction ....................................................................................................................+ 150°C
Lead, soldering (1 0 seconds) ....................................................................................................+300°C
Vapor phase soldering (1 minute) ..............................................................................................+220°C
Storage .............................................................................................................................-65 to +150°C

Notes:

1.

2.
3.
4.

Absolute maximum ratings are limiting values applied individually while all other parameters
are within specified operating conditions. Functional operation under any of these
conditions is NOT implied.
Applied voltage must be current limited to specified range, and measured with respect to
GND.
Forcing voltage must be limited to specified range.
Current is specified as conventional current, flowing into the device.

For More Information caJI1-800-722·7074.

Raytheon Semiconductor

2-19

TMC22071
Operating conditions
Temperature Range
Standard
Parameter
Voo

Power Supply Voltage

V 1H

Input Voltage, Logic HIGH
TTL Inputs
CMOS Inputs
Input Voltage, Logic LOW
TTL Inputs
CMOS Inputs

V 1L

Min

Nom

Max

Units

4.75

5.0

5.25

V

Voo
Voo

V
V

0.8
1/3 Voc

V
V

-2.0
4.0

mA
mA

2.0
2/3 Voo
DGNO
DGNO

IOH
IOL

Output Current, Logic HIGH
Output Current, Logic LOW

V 1N

Video Input Signal Level
Sync Tip to Peak White

1.0

V

V REF

External Reference Voltage

1.235

V

TA

Ambient Temperature, Still Air

0

70

°C

Microprocessor Interface
tpWLCS
tpWHCS

CS\ Pulse Width, LOW
CS\ Pulse Width, HIGH

35
35

ns
ns

tSA
tHA

Address Setup Time
Address Hold Time

4
25

ns
ns

tso
tHO

Data Setup Time
Data Hold Time

80
2

ns
ns

Note: 1. Timing reference points are at the 50% level.

2-20

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22071
Electrical Characteristics
Temperature Range
Standard
Parameter
100

Power Supply Current1

IREF Reference Input Current
IIH
III

Input Current. Logic HIGH
Input Current. Logic LOW

VOH Output Voltage. Logic HIGH
VOL Output Voltage. Logic LOW

Typ

Max

Units

TBD

TBD

mA

V REF = +1.235V

100

j1A

Voo = Max. V IN = 4.0V
Voo = Max. V IN = 0.4V

±10
±10

j1A
j1A

0.4

V
V

±10
±10

j1A
j1A

15

pF
pF

15

pF
k.Q

Conditions

Min

Total Current
Voo=Max.fpXCK=30MHz

IOH =-2.0 mA
IOl =4.0mA

2.4

IOZH Hi-Z Output Leakage current. HIGH Voo=Max. VIN=V OO
IOZl Hi-Z Output Leakage current. LOW Voo=Max. VIN=GND
CI
Co

Digital Input Capacitance
Digital Output Capacitance

T A = 25°C. f = 1MHz
T A = 25°C. f = 1 MHz

Cv
Rv

Input Capacitance. V IN1 -3
Input Resistance. V IN1 -3

T A = 25°C. f = 3.58 MHz

4
10

50

Note 1. Typical 100 with Voo=+5.0 Volts and T A=250 C. Maximum 100 with V oo=+5.25 Volts and T A=OoC.

For Mora InfonnaIIan call 1-800-722-7074.

Raytheon Semiconductor

2-21

TMC22071
Switching Characteristics
Temperature Range
Standard
Parameter
too
tHO

Output Delay Time
Output Hold Time

fPCK
f pXCK

Pixel Rate
Master Clock Rate

Conditions

Min

CLOAO =35 pF

tpWLPX PXCK Pulse Width, LOW
tpWHPX PXCK Pulse Width, HIGH

Typ

Max

Units

2
3

15
8

ns
ns

12
24

15.3
30.6

MHz
MHz

12
12

ns
ns

tOH
tvo

Horizontal Sync to GHSYNC\
Vertical Sync to GVSYNC\

4.5
4.5

tXL
txv

PXCK LOW to LDV HIGH
PXCK LOW to LDV LOW

ns
ns

tOOM
tHOM
tooz

Do enable time
Do disable time
CS\ LOW to Do output driven

ns
ns
ns

pixels
pixels

System Performance Characteristics
Temperature Range
Standard
Parameter

Conditions

Min

Typ

Max

Units

ESCH

Sync time-base variation 1

±30

ns

Escp

Subcarrier Phase Error1

±5

degrees

tAL

Line-lock Acquisition Time

2

frames

VXT

Channel-to-Channel Crosstalk @3.58 MHz

-35

dB

Notes 1. NTSC/PAL compliant black burst at nominal input level ±1 0%, frequencies nominal ± 10 ppm.

2-22

Raytheon Semicondu.ctor

For Mora Information call 1-800-722-7074.

TMC22071
Rgure 19. Typical Interface Circuit
+5V
6.8pf

JpF

390

DoNo
10111'

Video A

VideoC

3.31<0

VAEF

V,N•

EXTPXCK

20 MHz. TTL

+5V

PFOIN
COMP

V,..
10111'

ODSOllT

V,N•

10111'

Video B

AoND

Voo VOOA

0.01111'

ClKIN
CLK\OUT
PXCKSEl

TMC22071

0.1111'

GENLOCKING
VIDEO DIGITIZER
Iii

0

~d'<~~

~~

FIr
R"
CVBs.:.
GHSYNCI
GVSYNCI
PXCK
lOV

MICROPROCESSOR
INTERFACE

24384B

Application Notes
The TMC22071 is a complex mixed-signal VLSI
circuit. It produces CMOS digital signals at clock
rates of up to 15 MHz while processing analog video
inputs with a resolution of less than a few millivolts.
To maximize performance it is important to provide
an electrically quiet operating environment. The
circuit shown in Figure 19 provides an optional
external1.2V reference to the VREF input of the
TMC22071. The internal VREF source is adequate
for most applications.

with -3dB bandwidth of 6.7MHz and a group delay of
140 nanoseconds at 5MHz. The filter of Figure 21
has been equalized for group delay in the video
signal band. Its -3dB passband is 5.5MHz while the
group delay is constant at 220 nanoseconds through
the DC to 5MHz frequency band.

Figure 20. Simple Anti-aliasing Filter

Filtering

2.2uH

Inexpensive low-pass anti-aliasing filters are shown
in Figures 20 and 20. These filters would normally
be inserted in the video signal path just before the
750 terminating resistor and AC-coupling capacitor
for each of the three video inputs, V1N1 -3 • The filter
of Figure 20 exhibits a 5th-order Chebyshev
response

For More Information call 1-800-722·7074.

2.2uH

o

Raytheon Semiconductor

2-23

TMC22071
Figure 21. Group Delay Equalized Filter
3.3 uH

3.3uH

4.7uH

Grounding

4.7uH

25008A

Using a 20 MHz Crystal
In systems where a 20 MHz clock is not available, a
crystal may be used to generate the clock to the
TMC22071. The crystal must be a 20 MHz
"fundamental" type, not overtone." Specific crystal
characteristics are listed in Table 5 and the
connections are shown in Figure 22.

The TMC22071 has separate analog and digital
circuits. To minimize digital crosstalk into the analog
signals, the power supplies and ground connections
a~e. provided over separate pins (Voo and VOOA are
digital and analog power supply pins; DGNO and
~NO are digital and analog ground pins). In
general, the best results are obtained by tying all
grounds to a solid, low-impedance ground plane.
Power supply pins should be individually decoupled
at the pin. Power supply noise isolation may be
provided between analog and digital supplies via a
ferrite bead inductor. Ultimately all +5 Volt power to
the TMC22071 should come from the same power
source.
Another approach calls for separating analog and
digital ground. While some systems may benefit
from this strategy, analog and digital grounds must
be kept within 0.1 V of each other at all times.
Interface to the TMC22x9x Encoder

Table 5. Crystal Parameters
Parameter

Value

Fundamental frequency
Tolerance
Stability
Load Capacitance
Shunt Capacitance
ESR

20 MHz
±30 ppm @ 25°C
±50 ppm, OOC to 70°C
20pF
7 pF Max.
500, Max.

Figure 22. Direct Crystal Connections

The TMC22x9x Digital Video Encoders have been
designed to directly interface to the TMC22071
Digital Video Genlock. The TMC22071 is the source
for TMC22x9x input signals CVBS7_0, GHSYNC\,
GVSYNC\, LDV, and PXCK as shown in Figure 23.
These signals directly connect to the TMC22x9x.
The microprocessor interface for TMC22x9x and
TMC22071 are identical. All W/R\, RESET\, data
and address bus signals from the host
microprocessor are shared by the TMC22x9x and
TMC22071. Only CS\, VALID, and INT\ signals are
separate from the microprocessor bus.

TMC22071

27030B

2-24

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22071
Figure 23. TMC22x9x Interface Circuit
CVBl>,,,
GHSYNC\
GVSYNC\

TMC22071

8

CVBS7"
GHSYNC\
GVSYNC\

PXCK

PXCK

LOV

GENlOCKING VIDEO DIGITIZER
f'=

~~

TMC22x9x

LOV

DIGITAL VIDEO ENCODER
f'=

w

-~
O'.{ ~

~Jl~~

liit

tt

tt

2
8

I~
MICROPROCESSOR
INTERFACE

27009B

Printed Circuit Board layout
Designing with high-performance mixed-signal
circuits demands printed circuits with ground planes.
Wire-wrap is not an option. Overall system
performance is strongly influenced by the board
layout. Capacitive coupling from digital to analog
circuits may result in poor picture quality. Consider
the following suggestions when doing the layout:
1.

2.

3.

Keep the critical analog traces (CaMP, VREF'
RT, Rs ' DDS OUT, PFD IN, C Syp , and V IN1 -3)
as short as possible and as far as possible from
all digital signals. The TMC22071 should be
located near the board edge, close to the analog
output connectors.
The power plane for the TMC22071 should be
separate from that which supplies the rest of the
digital circuitry. A single power plane should be
used for all of the Voo pins. If the power supply
for the TMC22071 is the same as that of the
system's digital circuitry, power to the
TMC22071 should be decoupled with ferrite
beads and 0.1 J.l.F capaCitors to reduce noise.
the ground plane should be solid, not cross-

For More Information call 1-800-722-7074.

hatched. Connections to the ground plane
should have very short leads.
4.

Decoupling capacitors should be applied
liberally to Voo pins. Remember that not all
power supply pins are created equal. They
typically supply adjacent circuitry on the device,
which generate varying amounts of noise. For
best results, use 0.1 J.l.F capacitors in parallel
with 0.Q1 J.l.F capacitors. lead lengths should be
minimized. Ceramic chip capaCitors are the
best choice.

5.

If the digital power supply has a dedicated
power plane layer, it should not overlap the
TMC22071, the voltage reference or the analog
outputs. Capacitive coupling of digital power
supply noise from this layer to the TMC22071
and its related analog circuitry can have an
adverse effect on performance.

6.

ClK should be handled carefully. Jitter and
noise on this clock or its ground reference may
degrade performance. Terminate the clock line
carefully to eliminate overshoot and ringing.

Raytheon Semiconductor

2-25

TMC22071
Pin Assignments
Pin

Name

Pin

Name

Pin

Name

Pin

Name

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

Voo
CVBSo
CVBS1
CVBS2
CVBS3
CVBS4
VOO
DGNO
CVBS5
CVBSs
CVBS7
GHSYNC\
GVSYNC\
VALID
DGNO
DGNO
lDV

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

Voo
PXCK
DGNO
DGNO
VOO
VOOA

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

~NO

52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

VOO
ClK\OUT
EXTPXCK
DGNO
DGNO
DGNO
VOO
VOO

~NO

VOOA
VOOA

~NO

RB
V1N3
VOOA
V1N2

~NO

VOOA
V1N1

RT

~NO

VREF

~NO

VOOA
AGNO
CBYP
PFDIN
~NO

DDS OUT
PXCKSEl
VOOA
COMP

~NO

DGNO
ClKIN

Ao

R/w\
CS\
Voo
RESEn
DGNO
Do
INn
DGNO

44

60

43

61

68
1

27

9

26

10

27023A

Ordering Information
Product
Number

Temperature
Range

Screening

Package

Package
Marking

TMC22071 R1 C

TA= O°C to 70°C

Commercial

68-lead PlCC

22071R1C

40G07281 Rev E IV93

2-26

Raytheon Semiconductor

For Mora Information call 1-800-722-7074.

TMC22X9X
TMC22090/22091
TMC22190/22191
Digital Video Encoders / Layering Engine
The TMC22X9X digital video encoders convert digital
computer image or graphics data (in RGB, VCeCR, or
color indexed format or a CCIR-601 signal into a standard
analog baseband television (NTSC or PAL) signal with a
modulated color subcarrier. PAL-M and NTSC without
pedestal are also available from the TMC22091/191.
Both composite (single lead) and S-VIDEO (separate
chroma and luma) formats are active simultaneously at the
three analog output pins, each of which generates a
standard video-level signal into doubly-terminated 750
load.
The TMC22X9X accepts digitized video from the
companion TMC22070 Genlocking Video Digitizer. Soft
switching between video sources is done under either
hardware or programmable data level control.
The TMC22190/191 offers a 4-layer keying capability,
bypassable CLUTs, and 30 overlay colors.
The TMC22X9X is fabricated in a submicron CMOS
process and packaged in 84-lead PLCCs. Performance Is
guaranteed from oae to 70ae.

Features
•
•
•

•
•
•
•
•
•
•
•
•
•
•

po".

•
•
•
•
•
•
•
•

..

ot...
poc

All digital video encoding
Internal digital oscillators, no crystals required
Multiple input formats supported
Input formats supported
- 24-bit and is-bit GBRlRGB
- VCeCR422 or 444
- Color indexed
30 overlay colors (TMC22190/191)
Fully programmable timing
Supports input pixel rates of 10 to 15 Mpps
256 x 8 x 3 color look-up tables (bypassable on
TMC22190/191)
•
8-bit mask register
8-blt composite digital video input
Hardware and 24-bit data keying
Synchronizes with TMC22070 genlocking video
digitizer
8:8:8 video reconstruction
SMPTE 170M NTSC or CCIR report 624 PAL
compatible
TMC22091/191 also supports PAL-M and NTSC
without pedestal
Simultaneous S-VIDEO (VIC) NTSc/PAL output
10-bit D/A conversion (three channels)
Controlled edge rates
3 power-down modes
Built-in color bars and modulated ramp test signals
JTAG (IEEE Std 1149.1-1990) test interface
Single +5V power supply
84-lead PLCC package

VHSYNC\
VVSVNC\

KEY
BYPASS'

~i
~~

cves,.
GHSYNC\
GVSYNC'

TOI
TMS

a:

~~

RESEl\

~~

CSI
AIW\

~~
~

TCK
TOO

0,.

A,.
LOY
PXCK
evpA$S\.nd a...., on TMC22UICVf81 only.

§
i:i
27OO8A

Logic Symbol
For More Information call 1-800-722-7074

Raytheon Semiconductor

2-27

TMC22X9X
Contents
General Description
22X9X Part Comparison Table .................................. 27
Pixel Data Input Formats ..•..•.........•...••..•..•...•.•••••.•..... 30
Pin Functions .............................................................31
Package Interconnection Table .................................. 33
Control Registers ....................................................... 36
A1-O Functions ...........................................................37
Control Register Map ................................................. 37
Control Register Defintions ................................... 38-39
Color Look-up Tables ...........................................40-48
TCBCR422 Pixel Data Sequence .......................... 49-50
Gamma Correction ....................................................51
Video Timing Parameters ........................................... 51
Horizontal Programming ............................................52
Vertical Programming· ................................................52
NTSC FieldlLine Sequence ........................................ 53
PAL FieldILlne Sequence ........................................... 54
PAL-M FieldlLine Sequence ...................................... 56
Timing Parameters Table ...........................................58
VITS Signal Insertion ................................................. 60
Subcarrier Programming ............................................ 61
SCH Phase Error Correction ...................................... 62
Video Test Signals ..................................................... 62
Microprocessor Interface ............................................ 63
Operational Timing ..................................................... 64
Reset Timing .............................................................. 65
Pixel Data Input Timing .............................................. 65

2-28

Master Mode .............................................................. 66
Slave Mode ................................................................ 66
Genlock Mode ........................................................... 67
Internal and External PDC ......................................... 67
Layering ................................................................69-72
Layering Priority Table ............................................... 72
Hardware and Data Keying ........................................ 72
Table 0, E, F.............................................................. 73
Genlock Interface ....................................................... 73
Intemal Filters ............................................................ 75
JTAG Test Interface ................................................... 76
Equivalent Input/Output Circuits ................................. 78
Three-state Levels and Timing ................................... 78
Absolute Maximum Ratings ....................................... 79
Operating Conditions ............................................80-81
Electrical Characteristics ............................................ 82
Switching Characterisitics .......................................... 83
System Performance Characheristics ........................ 84
Typical performance Waveforms .......................... 85-87
Application Notes ....................................................... 88
External Analog Filters ...............................................88
Grounding sTrategy ...................................................89
PC Board Layout ....................................................... 90
ReadlWrite Sequences ......................................... 90-91
Pin Assignments ........................................................92
Package Drawing .......................................................92
Ordering Information ..................................................93

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Functional Block Diagram
w

~
0:

Ol...

BYPASS\ and OL,..o on TMC2219X Only

BYPASSI

W

~
0:

CHROMA

P023:o

~

w
""-

iil

w

::;

~

LUMA

KEY
POC
WSYNC\
VHSYNC\

a
5l
o
;;
o

l!l

8z
w

GHSYNC\

"'w
0 0 GVSYNC\

COMPOSITE

01E

-'0:

Zw
wI-

"';g
CVBB,.

VIE,
COMP

>'"
00
-'X
Q.

CLOCKS

c

~

R"EF

!ii5:E

luoc(0i:t

f30:

MICROPROCESSOR
INTERFACE

JTAGTEST
INTERFACE

27006A

General Description
The TMC220901091/190/191 are totally-integrated
fully-programmable digital video encoders with
simultaneous composite and VIC (S-VIDEO)
outputs. The TMC22x9x video outputs are
compatible with SMPTE 170M NTSC, CCIR Report
624 PAL, PAL-M, and NTSC without pedestal
television standards. No external component
selection or tuning is required.
The encoders accept digital image data at the PD
port in one of several formats, which are matrixed
into luminance and chrominance components. The
chrominance signals are modulated onto a digitally
synthesized subcarrier. The luminance and
chrominance signals are separately interpolated to
twice the pixel rate, and converted to analog levels
by 10-bit D/A converters. They are also digitally
combined and the resulting composite signal is
output by a third 10-bit DIA converter. This
composite signal may be keyed (pixel rate
switching) with a second composite digital video
signal presented to the encoder.

For More Information call 1-800-722-7074.

The output video frames may be internally timed by
the TMC22x9x, synchronized with the external
frame buffer, or slaved to the companion
Genlocking Video Digitizer (TMC22070). All
operational parameters are fully programmable
over a standard microprocessor port.
Table 1 shows the key features that distinguish the
members of the TMC22x9x family. All of the
information presented in this data sheet applies to
all of the TMC22x9x unless otherwise noted.
Statements, paragraphs, tables, and figures that
apply to only one or two of the encoders will have
notation specifying the applicable part number.

Timing
The encoder operates from a single clock at twice
the system pixel rate. This frequency may be set
between 20 MHz and 30 MHz (pixel rates of 10
Mpps to 15 Mpps). Within this range are included
CCiR-601, D2 NTSC, and square-pixel formats, as

Raytheon Semiconductor

2-29

TMC22X9X
Table 1. Comparing the TMC22x9x Encoders
22090

22091

22190

22191

OL4_0 pixel inputs for 30 overlay colors
Number of video layers supported
BYPASS\ input for bypassing CLUTs
Composite digital video from D7-0
Luminance data from D7-0

No
2
No
Yes
No

No
2
No
Yes
Yes

Yes
4
Yes
Yes
No

Yes
4
Yes
Yes
Yes

Luminance I/O processing
Extended EH and SL intervals
User-controllable SETUP
Individual D/A power-down mode
NTSC without SETUP
PAL-M

No
No
No
No
No
No

Yes
Yes
Yes
Yes
Yes
Yes

No
No
No
No
No
No

Yes
Yes
Yes
Yes
Yes
Yes

Feature

well as a variety of computer-specific pixel rates.
An array of programmable timing registers allows
the software selection of all pertinent signal
parameters to produce NTSC (with or without 7.5
IRE pedestal) and PAL, and PAL-M outputs.
Input Formatting
The input section accepts a variety of video and
graphics formats, including 24-bit GBR and RGB,
15-bit GBR and RGB, YC SCR422, YC SCR444, and
8-bit color-indexed data (Figure 1a and 1b).
The input section of the TMC22x9x includes a key
comparator which monitors the pixel data port with
three independent 8-bit comparators, and invokes
a video key when the selected registers match the
incoming data.

Color Lookup Table
The Color Lookup Table (CLUT) is a 256 x 8 x 3
random-access memory, and provides means for
offset, gain, gamma, and color correction in RGB
and YCSC R operating modes. It provides a full 24bit color lookup function for color-index mode and
can be loaded in the same manner, with the same
data, as a standard VGA RAMDAC.
ColorS pace Conversion Matrix and Interpolator
The matrix converts RGB data (whether from RGB
inputs or color-indexed CLUT data) into Y, B-Y, RY format for encoding. In input configurations
where the pixel input is already in Y, B-Y, R-Y
format, the matrix is bypassed. When pixel data is
input in YC SCR422 format, the interpolation filters
produce YC SC R444 for encoding.

Mask Register
Sync Generator
A Mask Register is provided which is logically
ANDed with incoming color-index data to facilitate
pixel animation and other special graphics effects.
The Mask Register is ahead of the Data Key
comparators and is enabled only when color-index
input is selected. Mask Register programming and
operation are similar to that of the 171/176 family of
graphics RAMDACS.

2-30

The TMC22x9x can operate in Master, Genlock, or
Slave modes. In Master and Genlock modes, the
encoder internally generates all timing and sync
signals, and provides Horizontal Sync, Vertical
Sync, and Pixel Data Control (PDC) to the external
frame buffer circuitry. PDC is independently
selectable to function as an input or an output. In
Genlock mode, the TMC22x9x timing is controlled
by the TMC22070 Genlocking Video Digitizer over
the CVBS 7_0 bus, GVSYNC\, and GHSYNC\. The

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Figure 1a. Pixel Data Format
MSB

MODE

Format Control Register
MSB

GBR444

LSB

00011000

RGB444

00010000
00011100
00011101

COLOR INDEX :

0001X011

GBR15

00011010

RGB15

00010010
24300A

Figure 1b. Pixel Data Format (TMC22190/191 when CLUTs are Bypassed)
MSB
23

MODE

IiGo;Br!
I
1615

I

!

GBR444

IGrl

!

RGB444

IRrl I

I ~I I IRoIGrl

YCBC R444

Ivr!

YCBC R422

Ivrl
:

 Sequence for YCBCR422
Format Control Register Bit 6 = HIGH
MSB
23

Format Control Register Bit 6 = LOW
l.SB

1815

8

7

0

MSB

lSB

~~ I!!!I!!I!!Ii! !!I !I! !!i

Pixel 1
Plxel2 I=l=**=#i*~**=l=si~*
Pixel 3
Pixel4~**~y~~F***~~~mmlDlmllm

~~I: ::Hl: :I:::~t:

Pixel n 1I I I t"1 I I 1I I IqaJ I
Pixel "+11 I I I NIl I I I I IqRJ I

!

I

I

I

::I::@t: ::I

I

I

I
27OO3A

Note that the pixel input sequence begins on the first LOV pulse after POC goes HIGH.

Gamma Correction
Gamma is built into broadcast television systems
as a correction factor for nonlinearity in the signal
path. These nonlinearities occur in image
acquisition (nonlinear conversion of light into
current in a vidicon) and at the display (nonlinear
conversion of voltage into beam current in a CRT
and phosphor nonlinearity in converting current into
light). To minimize the number of nonlinear
amplifiers needed, these factors were combined

For McII8lnlonnalion call 1-800-722-7074.

into a single term, Gamma, which is applied to the
signal at the camera (there are fewer-cameras than
receivers).
Gamma is employed in television production to
give a particular "feel" to a picture, hence it Is not a
fixed value, even within a given television system.

Raytheon Semiconductor

2-51

TMC22X9X
A Gamma corrector transfer function takes the form
of
Output = k ( Input) 11y
where a typical Gamma is 2.2 for NTSC, 2.Bfor
PAL.
Computer systems usually ignore Gamma in
driving a display monitor. Each R, G, and B
channel is treated as linear. When encoding a
computer display output to video, the user must
decide whether to apply a gamma correction factor
and, if so, what value. It is a good assumption that,
since the digital video input over the CVBS bus is
in composite form, it has been Gamma corrected.

Video Timing
The TMC22x9x can be programmed to
accommodate a wide range of system timing
requirements. With· a line locked pixel rate of 10 to
15 Mpps, the digitally synthesized horizontal
waveforms and subcarrier frequency and phase
are determined from 24 registers that are loaded by
a controller.
Horizontal Programming

Gamma correction is applied in the RGB domain.
When operating in YCBC R , for example when
encoding a CCIR-601 signal, Gamma should have
already been applied. Gamma correction is readily
added to the RGB transfer equations shown in
Table 5.

Horizontal interval timing is fully programmable,
and is established by loading the timing registers
with the durations of each horizontal element, the
duration expressed in PCK clock cycles. In this
way, any pixel clock rate between 10 MHz and 15
MHz can be accommodated, and any desired
standard or non-standard horizontal video timing
may be produced. Figure 4 illustrates the
horizontal blanking interval with timing register
identification.

Figure 3. Typical Gamma Curve for NTSC.

Horizontal timing parameters can be calculated as
follows:

1.0

t

=N

x (PCK period)

= N x (2 x PXCK period)

0.8

where N is the value loaded into the appropriate
timing register, and PCK is the pixel clock period.

~0.6
Il..
I-

Gamma = 2.2

:::>

00.4

o

OUT = (IN) 1/2.2

O~~~~~--~~~~~

0.2

0.4

0.6

INPUT

2-52

Horizontal timing resolution is two PXCK periods.
PXCK must be chosen such that it is an even
integer multiple of the horizontal line frequency.
This ensures that the horizontal line period, H,
contains an integer number of pixels. The
horizontal line comprises the sum of appropriate
elements.

0.8

1.0

24222A

H = FP + SY + BR + BU + CBP + VA
When programming horizontal timing, subtract 5
PCK periods from the calculated values of CBP
and add 5 PCK periods to the calculated value for
VA.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Figure 4. Horizontal Blanking Interval Timing

The Vertical Interval comprises several different
line types based upon H, the Horizontal line time.
H = (2 x SL) + (2 x SH) [Vertical sync pulses]
= (2 x EL) + (2 x EH) [Equalization pulses]
The VB and VC lines are added to produce the
half-lines needed in the vertical interval at the
beginning and end of some fields. These must
properly mate with components of the normal lines.
VB = CBP + VA - XBP = H/2 - CBP
VC = VA -( EL + EH) = VA - HI2

Table 8. Horizontal Timing SpecHlcations
Parameter

FP
SY
BR
BU
CBP
VA
H

NTSC-M

PAL-I

PAL-M

(~)

~}

(~)

1.5
4.7
0.6
2.5
1.6
52.6556
63.5556

1.65
4.7
0.9
2.25
2.55
51.95
64.0

1.9
4.95
0.9
2.25
1.8
51.692
63.492

where Equalization HIGH and LOW pulses (EL +
EH) = H/2 and the Extended Color Back Porch,
XBP = VA + CBP - VB. XBP begins after the
end of burst, BU, taking the place of CBP in vertical
interval UBV lines.

Figure 5. Vertical Sync and Equalization Pulse
Detail

H/2

EH-~

Vertical Programming
Vertical interval timing is also fully programmable,
and is established by loading the timing registers
with the durations of each vertical timing element,
the duration expressed in PCK clock cycles. In this
way as with horizontal programming, any pixel rate
between 10 and 15 Mpps can be accommodated,
and any desired standard or non-standard vertical
video timing may be produced.
Like horizontal timing parameters, vertical timing
parameters are calculated as follows:
t

=N
=N

x (PCK period)
x (2 x PXCK period)

---.I

__-SL

EL

SH
24319A

Table 9. Vertical Timing Specifications
Parameter

H
EH
EL
SH
SL

NTSC-M

PAL-I

PAL-M

(~)

~)

~}

63.5556
29.4778
2.3
4.7
27.1

64
29.65
2.35
4.7
27.3

63.492
29.45
2.3
4.65
27.1

where N is the value loaded into the appropriate
timing register, and PCK is the pixel clock period.

For More Information call 1-800-722·7074.

Raytheon Semiconductor

2-53

TMC22X9X
Figure 6. NTSC Vertical Interval
FIELDS 1 AND 3
~--------------VERTICALB~G--------------.

VERTICAL SYNC
:------~----

POST-EQUAUZATION

H-----4------3H---~

VHSYNC\

VVSYNc\

~------------~----~\'~\------------------------

COMPOSITE

SYNC

VHSYNC\

VVSYNc\

~----------------------~\~~,----------------------

COMPOSITE

SYNC

27000A

2-54

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Table 10. NTSC Field I Line Sequence and Identification
Field 1
FIELD ID xOO

Field 2
FIELD ID x01

=

Field 3
FIELD ID x10

Field 4
FIELD ID x11

=

=

=

Line

ID

LTVPE

Line

ID

LTVPE

Line

ID

LTVPE

Line

ID

LTVPE

1
2
3
4
5
6
7
8
9
10

EE
EE
EE
SS
SS
SS
EE
EE
EE
UBB

00
00
00
03
03
03
00
00
00
00

264
265
266
267
268
269
270
271
272
273

EE
EE
ES
SS
SS
SE
EE
EE
EB
UBB

00
00
01
03
03
02
00
00
10
00

EE
EE
EE
SS
SS
SS
EE
EE
EE
UBB

00
00
00
03

EE
EE
ES
SS
SS
SE
EE
EE
EB
UBB

00
00
01
03
03
02
00
00
10
00

...

...

264
265
266
267
268
269
270
271
272
273

...

...

1
2
3
4
5
6
7
8
9
10

20
21

00

UBB
UBV
UVV

UBB
UVV
UVV

OF
OF

282
283
284

UBB
UBV
UVV

00

OE
OF

20
21
22

00

OF
OF

282
283
284

00

22

UBB
UVV
UVV

262
263

UVV
UVE

OF
OC

524
525

UVV
UVV

OF.
OF

262
263

UVV
UVE

OF
OC

524
525

UVV
UVV

OF
OF

...

...

...

...

...

...

...

...

...

...

...

...

03
03

00
00
00
00

...

...

...
...

...

...

...

OE
OF

...

EEEqualization pulse
SEHalf-line vertical sync pulse. half-line equalization pulse
SSVerticai sync pulse
ESHalf-line equalization pulse. half-line vertical sync pulse
EBEqualization broad pulse
UBB Black burst
UW Active video
UVEHalf-line video. half-line equalization pulse
UBVhalf-line black. half-line video

Master and Genlock mode details of VHSYNC\, VVSYNC\. and composite VVSYNC\ (SOUT = HIGH)
outputs are shown in Figures 6 and 7. When VHSYNC\ and VVSYNC\ are used as inputs (Slave mode).
their falling edges mark the beginning of the sync interval and the width of the input pulse is specified under
Operating Conditions.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-55

TMC22X9X
Figure 7. PAL Vertical Interval

V\lSYNC\
VVSYNc\
COMPOSrrB
SYNC

V\lSYNC\
VVSYNc\
COMPOSrrB
SYNC

V\lSYNc\
VVSYNC\
COMPOSrrB
SYNC

V\lSYNC\
VVSYNc\
COMPOSrrB

SYNC

27001 A

2-56

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Table 11. PAL Field I LIne Sequence and Identification
Field 1 and 5
FIELD ID = 000, 100

Field 2and 6
FIELD ID = 001, 101

Field 3and7
FIELD ID = 010,110

Field 4and8
FIELD ID 011,111

=

LIne

ID

LTYPE

LIre

ID

LTYPE

Line

ID

LTYPE

LIne

ID

LTYPE

1
2
3
4
5
6
7
8

SS
55
SE
EE
EE
-BB
UBB
UBB

03
03
02
00
00
05
00
00

313
314
315
316
317
318
319
320

ES
55
55
EE
EE
EB
UBB
UBB

01
03
03
00
00
10
00
00

55
55
5E
EE
EE
UBB
UBB
UBB

...

...

...

...

...

...

...

03
03
02
00
00
00
00
00

938
939
940
941
942
943
944
945

E5
55
55
EE
EE
EB
-BB
UBB

...

626
627
628
629
630
631
632
633

01
03
03
00
00
10
05
00

...

...

22
23
24

UBB
UBV
UVV

00

UBB
UVV
UVV

00

00

00

...

...

...

...

960
961
962

UBB
UVV
UVV

...

647
648
649

UBB
UBV
UVV

...

335
336
337

308
309
310
311
312

UVV
UVV
-VV
EE
EE

621
622
623
624
625

UVV
-VV
-VE
EE
EE

933
934
935
936
937

UVV
UVV
UVV
EE
EE

1246
1247
1248
1249
1250

UVV
UVV
-VE
EE
EE

DE

OF
...
OF
OF
07
00
00

OF
OF
...
OF
07
04
00
00

...

DE

OF
...
OF
OF
OF
00
00

...
...

...

OF.
OF

...

OF
OF
04
00
00

EEEqualization pulse
5EHalf-line vertical sync pulse, half-line equalization pulse
55Vertical sync pulse
E5Half-line equalization pulse, half-line vertical sync pulse
EBEqualization broad pulse
UBB Black burst
-BBBlack burst with color burst suppressed
UVV Active video
-VVActive video with color burst suppressed
UVEHalf-line video, half-line equalization pulse
-VEHalf-line video, half-line equalization pulse, color burst suppressed.
UBVhalf-line black, half-line video

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-57

TMC22X9X
Figure 8. PAL·M Vertical Interval

t.fj
8-

17

IlBB

UVV

VVSYNc\

COMPOSITE

SYNC

VHSYNC\
VVSYNc\

COMPOSITE

,YNC

t.fj
8-

17

IlBB

UVV

VVSYNc\

COMPOSITE

SYNC

COMPOSITE

,YNC

27082A

2-58

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Table 12. PAL-M Field I Line Sequence and Identification
Field 1 and 5
FIELD ID 000, 100

=

Field 2 and 6
FIELD ID 001, 101

=

Field 3and7
FIELD ID 010, 110

=

Field 4and8
FIELD ID 011, 111

=

Line

ID

LTYPE

Line

ID

LTYPE

Line

ID

LTYPE

Line

ID

LTYPE

1
2
3
4
5
6
7
8
9

SS
SS
SS
EE
EE
EE
-BB
-BB
UBB

03
03
03
00
00
00
05
05
00

263
264
265
266
267
268
269
270
271

ES
SS
SS
SE
EE
EE
EB
-BB
UBB

01
03
03
02
00
00
10
05

1
2
3
4
5
6
7
8

SS
SS
SS
EE
EE
EE
-BB
UBB

10

...

03
03
03
00
00
00
05
05

...

.. .

263
264
265
266
267
268
269
270
271

ES
SS
SS
SE
EE
EE
EB
-BB
UBB

01
03
03
02
00
00
10
05
10

UBB
UVV

00.

00

17
18

...

...

...

258
259
260
261
262

UVV
-VV
eVE
EE
EE

OF

279
280
281
...
521
522
523
524
525

UBB
UBV
UVV

...

...

...

17
18
...
259
260
261
262

UBB
UVV

00

...

...

UVV
eVE
EE
EE

OF

OF

04
00
00

...

279
280
281
...
521
522
523
524
525

...
UBB
UBV
UVV

...

OE.
OF

...

..

UVV
-VV
EE
EE
EE

OF

07
00.
00
00

OF

07
04
00
00

...

...

.. .

00
DE .
OF

...

..

UVV
UVV
EE
EE
EE

OF
OF

00
00
00

EEEqualization pulse
SEHalf-line vertical sync pulse, half-line equalization pulse
SSVertical sync pulse
ESHalf-line equalization pulse, half-line vertical sync pulse
EBEqualization broad pulse
UBB Black burst
-BBBlack burst with color burst suppressed
UW Active video
-VVActive video with color burst suppressed
UVEHalf-line video, half-line equalization pulse
-VEHalf-line video, half-line equalization pulse, color burst suppressed.
UBVhalf-line black, half-line video

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-59

TMC22X9X
Table 13. Standard Timing Parameters

Standard

Field Horizontal Pixel PXCK
Freq.
Rate Freq.
Rate
(Mppa) (MHz)
(Hz)
(kHz)

NTSC sqr. pixel
NTSC CCIR-601
NTSC4x Fsc

59.94 15.734266 12.27
59.94 15.734266 13.50
59.94 15.734266 14.32

PAL sqr. pixel
PAL CCIR-601
PAL 15 Mpps
PAL-M sqr.pixel
PAL-M CCIR-60
PAL-M4x Fse

Note:

1.
2.

3.

SY
10

BR
11

24.64
27.00
28.64

3A

07

40

08
09

50.00 15.625000 14.75
50.00 15.625000 13.50
50.00 15.625000 15.00

29.50
27.00
30.00

45

60.00 15.750000 12.50
60.00 15,750000 13.50
60.00 15,750000 14.30

25.01
27.00
28.60

3E

43
40
46

44
47

Timing Register (hex)
BU CBP XBP VA VC VB Note 1 FP
12
13
14
15
16
17
18
19
IF
22
24

OF
11
12

23
3F
64

8B
CB
F7

05

n

IE
30

90

00
OC
00

21
IE

21
10
21

60
40
73

03
C3
11

2B
13
31

B7

OB
OC
00

lC
IE

13
13
15

26
26
4C

86
Bf
E8

FE
12
22

8B
99
AC

22

20

B5

93
BF

EL
1A

EH2 SL2
1B 1C

SH CBl
1D 1E

40
6E
84

3A

65
65
65

12
14
15

lC
IF
21

SA

75
65
75

19
16
19

23

B5
90

93

20
23

BO

9A

45
3F
47

61

18
lA
lB

10
IF
21

70
8E
A5

53

3A

6E
84

3F
42

65
65

8E
A6

71

3F
43

52
59
5F
61

68
62
52
57
50

XBP, VA, VC, and VB are 10-bit values. The 2 MSBs for these four variables are in Timing Register
18. See Table 4.
EH and SL are 9-bit values. A most significant "1" is forced by the TMC22x9x since EH and SL must
range from 256 to 511. Extending the range of EH and SL to 767 is possible in the TMC22091/191.
Only the eight LSBs are stored in Timing Registers 1Band 1C.
Every calculated timing parameter has a minimum value of 5 except EH and SL which have minimum
values of 256.

VITS Signal Insertion

Subcarrler Programming

In both NTSC and PAL, the TMC22x9x can be set
up to allow VITS signals in the vertical interval in
place of normal black burst lines (UBB). This is
controlled by the Interface Control Register bit 7. If
this bit is LOW, UBB lines are black burst and are
independent of TMC22x9x input data. If the bit is
HIGH, all vertical interval UBB lines become UVV.
UVV lines are active video and depend upon data
input to the TMC22x9x. VITS lines may be used
for inserting special test signals or for passing
captioning data through the encoder.

The color subcarrier is produced by an internal 32bit digital frequency synthesizer which is completely
programmable in frequency and phase. Separate
registers are provided for phase adjustment of the
color burst and of the active video, permitting
external delay compensation, color adjustment, etc.

Edge Control
SMPTE 170M NTSC and Report 624 PAL video
standards call for specific rise and fall times on
critical portions of the video waveform. The
TMC22x9x does this automatically, requiring no
user intervention. The TMC22x9x digitally defines
slopes compatible with SMPTE 170M NTSC or
CCIR Report 624 PAL on all vital edges:
1.
2.
3.

2-60

H and V Sync leading and trailing edges.
Burst envelope.
Active video leading and trailing edges.

In Master or Slave mode, the subcarrier is internally
synchronized to establish and maintain a specified
relationship between the leading edge of horizontal
sync and color burst phase (SCH). In NTSC and
PAL, SCH synchronization is performed every eight
fields, on field 1 of the eight-field sequence. Proper
subcarrier phase is maintained through the entire
eight fields, including the 25 Hz offset in PAL
systems. See the description of 8FSUBR under
Test Control Register bit 1 for the subcarrier reset
function.
In Genlock mode, the phase and relative frequency
of the incoming video is transmitted by the
TMC22070 Genlocking Video Digitizer over the
CVBS bus at the beginning of each line, which
synchronizes the digital subcarrier synthesizer.
When control register bit BUKEN is HIGH and
digitized burst from the TMC22070 is passed

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
through to the reconstruction D/A converter, the
reference subcarrier for the chrominance modulator
is still synthesized within the encoder.

This value must be converted to binary and split
into two 8-bit registers, BURPHM and BURPHL.
PAL Subcarrler

NTSC Subcarrler
The PAL relationship is more complex, repeating
only once in 8 fields (the well-known 25 Hz offset):

For NTSC encoding, the subcarrier synthesizer
frequency has a simple relationship to the pixel
clock period, repeating over 2 lines: The decimal
value is:

x 232

FREQ = (1135 14>+ ( 1 1625)
(pixels I line)

FREQ = (455 I 2) X 232
( pixels I line )

This value must be converted to binary and split as
described previously for NTSC. The number of
pixels I line is found as in NTSC.

This value must be converted to binary and split
into four 8-bit registers, FREQM, FREQ2, FREQ3,
and FREQL. The number of pixels I line is:

For PAL, the decimal value for SYSPH is found
from:

Pixels I line = ( 2 I PXCK frequency )( H period)

SYSPH = FREQ I 217

SYSPH establishes the appropriate phase
relationship between the internal synthesizer and
the chroma modulator. The nominal value for
SYSPH is zero.

This value must be converted to binary and split
into two 8-bit registers, SYSPHM and SYSPHL.
Burst Phase in PAL is identical to SYSPH.
Therefore, the same values for SYSPHM and
SYSPHL must be used for BURPHM and BURPHL.

Other values for SYSPH must be converted to
binary and split into two 8-bit registers, SYSPHM
and SYSPHL.

PAL-M Subcarrler
FREQ = (909 I 4) X 232
( pixels I line)

Burst Phase (BURPH) sets up the correct relative
NTSC modulation angle. The value for BURPH is:

SYSPH = FREQ I 217 = BURPH
BURPH = SYSPH + 8,192 = SYSPH + 1tI4
Table 14. Standard Subcarrler Parameters

Standard

Field Horizontal Pixel PXCK Subcarrler
Subcarrier Reglater (hex)
Rate
Freq.
Ratft Freq.
Freq.
BURPHM BURPHL SYSPHM SYSPHL FREQIII FREQ2 FREQ3 FREQl
(Hz)
(kHz)
(MHz) (MHz)
(MHz)
27
26
25
24
23
22
21
20

NTSC sqr. pixel 59.94 15.734266 12.27
NTSC CCIR-601 59.94 15.734266 13.50
NTSC 4x Fsc
59.94 15.734266 14.32

24.54 3.57954500
27.00 3.57954500
28.64 3.57954500

20
20

00
00
00

00
00
00

00
00
00

4A
43

AA
EO

F8

20

40

00

00

PAL sqr. pixel
PAL CCIR-601
PAL 15 Mpps

14.75
13.50
15.00

29.50 4.4336187~
27.00 4.4336187~
30.00 4.43361875

00
00
00

00
00
00

00
00
00

00
00
00

4C
54
48

F3
13

AA

18
15
C6

12.50
13.50
14.30

25.01 3.57561149
27.00 3.57561149
28.60 3.57561149

00
00
00

00
00

00

00

00

49
43

00

00

00
00

45
OF
10

3F
66

PAL-M sqr.pixel
PAL-M CCIR-60
PAL-M 4x Fsc

50.00 15.625000
50.00 15.625000
50.00 15.625000

60
60

60

15.750
15,750
15,750

For More Information call 1-800-722·7074.

Raytheon Semiconductor

40

AA

00

C7
3E
00
19

96
AI
51
07
F5

2-61

TMC22X9X
SCH Phase Error Correction
SCH refers to the timing relationship between the
50% point of the leading edge of horizontal sync
and the positive or negative zero-crossing of the
color burst subcarrier reference. SCH error is
usually expressed in degrees of subcarrier phase.
In PAL, SCH is defined for line 1 of field 1, but
since there is no color burst on line ·i , SCH is
usually measured at line 7 of field 1. The need to
specify SCH relative to a particular line in PAL is
due to the 25 Hz offset of PAL subcarrier
frequency. Since NTSC has no such 25 Hz offset,
SCH applies to all lines.
The SCH relationship is only important in the
TMC22x9x when two video sources are being
combined or if the composite video output is
extemallycombinedwithanothervideosource.ln
these cases, improper SCH phasing will result in a
noticeable horizontal jump of one image with
respect to another and/or a change in hue
proportional to the SCH error between the two
sources.
SCH phasing can be adjusted by mqdifying
BURPH and SYSPH values by equal amounts.
SCH is advanced/delayed by one degree by
increasing/decreasing the value of BURPH and
SYSPH by approximately B6 h. An SCH error of
150 is corrected with SYSPH and BURPH offsets of
AAAh•

Video Test Signals
The TMC22x9x has two standard video test
waveforms available for evaluating video signal
integrity. These are selected and controlled by the
Format Control Register.
Setting the Format Control Register bits 0, 4, and 5
LOW generates standard color bars at the
COMPOSITE output (Figure 9), the I.uminance

2-62

component stair-step signal at the LUMA output,
and the chrominance component on the CHROMA
output. The six colors are 100% saturated PAL
and 75% saturated for NTSC. The exact location
of each color vector (subcarrier amplitude,
subcarrier phase) can be measured using industrystandard instrumentation (vectorscope).
The percentage color saturation is selectable via
Control Register OE, bit 0 in the TMC22091/191.
The color bar test pattern produced comprises
eight equal-width bars during VA, the active video
period. The Timing Register value for CBL is found
from:
CBL = { ( VA + 7 ) /8 }
If CBL is larger than this, the color bars are
truncated at the end of VA. If CBL is smaller than
VA / 8, the color bar sequence will repeat, starting
with another white bar. From left to right color bars
1 to 8 should be white, yellow, cyan, green,
magenta, red, blue, and black. See Figures 35, 36,
41,42,47,48.
The modulated ramp waveform is enabled by
setting the Format Control Register to 30h• It
comprises constant-amplitude and constant-phase
subcarrier modulation superimposed on a linear
ramp which slews from black to white during the
active video portion of each horizontal line interval
(Figure 10). This waveform is useful in making
differential gain and differential phase
measurements on the video signal. Differential
gain is a measure of the variation in saturation of a
color as the luminance component is varied from
black to white. Differential phase is a measure of
the variation in hue of a color as the luminance
component is varied from black to white.
Differential gain and differential phase are
measured with a vectorscope. See Figures 39, 40,
45,46.

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TMC22X9X
Figure 9. 100% Color Bars With 100% and 75% Chromlnance Saturation

2

2

3

3

718 I

24387A

Microprocessor Interface

Figure 10. Modulated Ramp Waveform

The microprocessor interface employs a 13-line
interface, with an a-bit data bus and two address
bits: four addresses are required for device
programming and CLUT/register management.
Address bit 0 selects between control registers and
CLUT memory. Address bit 1 selects between
reading/writing the register addresses and
reading/writing register or CLUT data.
When writing, the address is presented along with
a LOW on the R/W\ pin during the falling edge of
24388A CS\. Eight bits of data are presented on 07-0
during the subsequent rising edge of CS\. One
additional falling edge of CS\ is needed to move
input data to its assigned working registers.
Figure 11. Microprocessor Port - Write Timing

24323A

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-63

TMC22X9X
Figure 12. Microprocessor Port - Read Timing

In read mode. the address is accompanied by a
HIGH on the RIW\ pin during a falling edge of CS\.
The data output pins go to a low-impedance state
tOOl ns after CS\ falls. Valid data is present on
0 7-0 tOOM after the falling edge of CS\. Because
this port operates asynchronously with the pixel
timing. there is an uncertainty in this data valid
output delay of one PXCK period. This uncertainty
does not apply to tool'

The TMC22091/191 has an additional feature that
allows luminance pixel data to be read from the
0 7-0 , In this case the eight MSBs of luminance
found just prior to the Sync and Blank Insert block
are routed to the microprocessor port. When the
Control Register pointer is loaded with SOh' the
0 7-0 port will begin outputting 8-bit luminance
pixels synchronous with respect to PXCK. To halt
the pixel flow from 0 7-0 , simply bring CS\ HIGH.

The RESET\ pin restores the TMC22x9x to field 1
line 1 and places the encoder in a power-down
state (if HRESET is LOW). Bit 4 of the Global
Control Register (SRESET\) is set LOW. All other
control words and CLUT contents are left
unchanged. Returning RESET\ HIGH
synchronizes the internal clock with PXCK and
restores power to the device outputs.

Operational Timing
The TMC22x9x operates in three distinct modes:
1.

Master mode. The encoder independently
produces all internal timing and provides digital
sync to the host controller.

2.

Slave mode. The encoder accepts horizontal
and vertical sync from the controller and
synthesizes the video output accordingly.

3.

Genlock mode. The encoder accepts
horizontal and vertical sync from the
companion TMC22070 Genlocking Video
Digitizer. synchronizes itself to the incoming
video. and provides appropriate H Sync and V
Sync to the host. It synchronizes Pixel Data
input in two ways:

Reading Pixel Data from the D7-G Port
The microprocessor port of the TMC22x9x may be
used to extract digital video pixels. The eight
MSBs of the up-sampled and interpolated pixel
data that go to the COMPOSITE O/A converter can
also be sent to the 0 7-0 port and read for
subsequent processing. When the Test Control
Register is loaded with 28 h and the Control
Register pOinter is loaded with 40 h• the 0 7-0 port
will begin outputting 8-bit composite pixels
synchronous with respect to PXCK. To halt the
pixel flow from 0 7-0, simply bring CS\ HIGH.

2-64

a. Intemal POC. The encoder internally
generates the Pixel Data Control (POC)

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Figure 13. Reset Timing - PCK Synchronization

PXCK~1
2

~

RESEn_______________

signal which calls for data input from the
extemal pixel source.
b. External PDC. The encoder receives a
PDC signal from the host and accepts Pixel
Data based on that input.

---------2-4-33-0A

be shown with numbered rising edges. A
designation of 2N clocks refers to an even number
of PXCK rising edges
from device reset. If RESEn is not shown and
clock numbering does not refer to 2N, timing is
relative to signals shown in the diagram only.

Reset Timing
Pixel Data Input Timing
The TMC22x9x operates from a master clock
(PXCK) at twice the pixel rate. Some internal
circuitry employs a clock at the pixel rate, PXCK /
2. In Master mode, the PCK to PXCK timing
relationship is set on the rising edge of RESEn. In
Figure 13, PCK is denoted by odd PXCK counts.
When RESEn is taken LOW with sufficient setup
time (tSR) before a rising edge of PXCK, the
internal state machines are reset and the device is
put into a mode as dictated by the Global Control
Register bits 0 and 4. In Master mode, when the
RESEn pin is taken HIGH, the internal clock timing
is established. In Slave and Genlock mode, this
timing is established by VHSYNC\ and GHSYNC\
respectively. The first PXCK following this RESEn
rising edge is designated as PXCK 1. Where it is
significant, reference PXCK timing will

PXCK is internally divided by 2 to generate an
internal pixel clock, PCK which is not accessible
from the pins of the TMC22x9x. To ensure the
correct relationship between PCK and pixel data,
PCK is locked to VHSYNC\ or GHSYNC\ (Slave or
Genlock mode, respectively). In Master mode,
VHSYNC\ is produced on the rising edge of PCK
allowing external circuitry to synchronize the
generation of pixel data and LDV which also
operates at 1/2 the rate of PXCK.
The rising edge of LDV clocks the 24-bit pixel data
into three 8-bit registers while PCK clocks that data
through the pixel data path within the TMC22x9x.
It is therefore necessary to meet the set-up and
hold timing between pixel data and LDV as well as
LDVand PCK.

Figure 14. Slave Mode PO Pqrt Interface Timing (Genlock Mode)
PXCK
VHSYNC\
(GHSYNC\)

PCK

24340A

For Mora Information callt-800-722-7074.

Raytheon Semiconductor

2-65

TMC22X9X
Figure 15. Master Mode Timing

PXCK
RESEn

VHSYNC\o
COMPOSITE
OUTPUT
24353A

Master Mode

Slave Mode

In Master mode, initial timing is determined from
the RESEn input, and subsequent cycles result
from programmed values in the Timing Control
Registers. The Horizontal Sync output, VHSYNC\,
goes LOW 18 PXCK clock cycles after the device
is reset. The 50% point of the falling edge of sync
LOW on line 4 of field 1 (NTSC) or line 1 of field 1
(PAL) occurs at the COMPOSITE and LUMA
outputs 56 clocks after reset, or 38 clocks after
VHSYNC\.

In Slave mode, the 50% point of the falling edge of
sync occurs 46 PXCK clocks after the falling edge
of VHSYNC\, which is an input signal to the
TMC22x9x. This must be provided by the host to
begin every line. If it is early, the line will be started
early, maintaining the 52 clock delay to output. If it
comes late, the front porch portion of the output
waveform will be extended as necessary.

Figure 16. Slave Mode Timing

PXCK
VHSYNC\,
VVSYNC\,
for field 1
COMPOSITE
OUTPUT

2-66

50% Sync Amplitude ~

Raytheon semiconductor

24355A

For More Information caJI1-800·722·7074.

TMC22X9X
Figure 17. Genlocked Mode Timing

PXCK
GHSYNC\I
VHSYNC\o

COMPOSITE
OUTPUT

Genlocked Mode
In Genlocked mode, the encoder receives sync
signals over the GHSYNC\ and GVSYNC\ inputs,
and provides VHSYNC\ and VVSYNC\ to the host.
The 500k sync amplitude point occurs 50 PXCK
clocks after GHSYNC\ goes LOW, while VHSYNC\
is produced at clock 13. If GHSYNC\ is late, the
front porch is lengthened, if is is early, front porch is
shortened.
Pixel Data Control
The Pixel Data Control (POC) signal determines

the active picture area. It may be an input or an
output, as determined by the Interface Control
Register bit 1.
The position (number of PCK cycles) of the rising
edge of POC relative to the falling edge of
VHSYNC\ can be found by summing SY, BU, BR,
and CBP.
External Pixel Data Control
When used as an input, POC goes HIGH four
PXCK cycles before the first valid pixel of a line is
presented to the PO input port. If this signal is late

Figure 18. External Pixel Data Control

PXCK
POC1

COMPOSITE
OUTPUT
POST-FILTER
OUTPUT
24358A

For Mora Information call 1-800-722·7074.

Raytheon Semiconductor

2-67

TMC22X9X
(with respect to the horizontal blanking interval
programmed in the timing control registers), the
Color Back Porch (CBP) wi" be extended. If it is
early, incoming pixel data will be ignored until the
end of the CBP.

Internal Pixel Data Control
When programmed as an output, POC goes HIGH
four PXCK periods prior to the end of CBP (as
programmed in the horizontal timing registers)
which is also four PXCK cycles prior to required

input of the first pixel of a line.
Pixels produced by the encoder appear at the
analog outputs (COMPOSITE, LUMA, CHROMA)
40 clocks after they are registered into the PO port.
Note that the pixels enter at one-half the PXCK
rate. The encoded Signal passes through
interpolation filters which generate intermediate
output values, improving the output frequency
response and greatly simplifying the external
reconstruction filter. The interpolated pixels are
designated PI in the diagram.

Figure 19. Internal Pixel Data Control

PXCK
PDCo

COMPOSITE
OUTPUT
POST-FILTEA
OUTPUT
24357A

2-68

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TMC22X9X
Layering with the TMC22190/191
The "layering" capabilities of the TMC22190/191
are powerful and flexible. Layering is a video
production concept where various images or
patterns are superimposed (keyed) over each other
to form a final image that is the layered composite
of the input images. Four layers with the following
priority are defined for the TMC22190/191:

4-layer composite image is a very powerful tool in
the production of computerllive video. The
TMC22190/191 performs layering operations
entirely in the digital domain, enabling precise
digital control.

1.

For this layering example, a BACKGROUND image
(Figure 20) is generated. This image comprises
shaded matte levels varying from black at the top
of the screen to white at the bottom. This could
just as well be a color image which will be seen
wherever no other image appears through the
layering process.

2.

3.

4.

The DOWNSTREAM KEY layer keys over all
other layers.
The FOREGROUND layer keys over
MIDGROUND and BACKGROUND, but not
over DOWNSTREAM KEY.
The MIDGROUND layer keys over
BACKGROUND, but not over FOREGROUND
or DOWNSTREAM KEY.
The BACKGROUND layer never keys over any
other layer.

It is important not to confuse layers with sources.
The TMC22190/191 can be programmed to assign
any of its input sources (RGB, YCRC B, CVBS bus,
Overlay bits) to any of the four layers.

A 4-Layer Example

The MIDGROUND image comprises a happy face
superimposed over a white rectangle. Only the
happy face and the white rectangle are of interest
for this image and therefore, the portion of the
image outside that area will be replaced by the
BACKGROUND image when MIDGROUND is
keyed over BACKGROUND. A key signal is
generated on a pixel-by-pixel basis. It indicates

The ability to combine various video sources into a

Figure 20. 2-Layer Image Construction
BACKGROUND

2-LAYER COMPOSITE

MIDGROUND

27036A

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-69

TMC22X9X
which image is active. The key signal for keying
MIDGROUND over BACKGROUND is shown to
the right of the MIDGROUND image. This
represents a single bit signal mapped over the
image. When the signal is black (logic LOW), the
MIDGROUND image is active, when it is white
(logic HIGH), the BACKGROUND is active.
The results of layering MIDGROUND over
BACKGROUND images are shown in the 2-layer
composite image Figure 20.
A FOREGROUND image comprises a shaded
matte rectangle with "HI KIDS !" alpha characters
in its center. This is to be superimposed over the
previous 2-layer composite image. The key signal
needed for superimposing FOREGROUND over
other images is shown to the right of the
FOREGROUND image. This represents a single
bit signal mapped over the image. When the signal
is black (logic LOW), the FOREGROUND image is
active, when it is white (logic HIGH), the composite
image is active.
A new 3-layer composite image, FOREGROUND
over MIDGROUND over BACKGROUND, is shown

in Figure 21.
A DOWNSTREAM KEY image comprises the white
alpha characters "HAPPY FACE", and black alpha
characters "Time". This is to be superimposed
over the previous 3-layer composite image. The
key signal needed for superimposing
DOWNSTREAM KEY image over the other
composite images is shown to the right. This
represents a single bit signal mapped over the
image. When the signal is black (logic LOW), the
DOWNSTREAM KEY image is active, when it is
white (logic HIGH), the previous composite image
is active.
The final 4-layer composite image,
DOWNSTREAM KEY over FOREGROUND over
MIDGROUND over BACKGROUND, is shown in
Figure 22.
In this illustration, all four source images are static
(not moving). The images input to the
TMC22190/191 can just as well be "live" (from
video camera or VCR sources) as long as:
1. Data from those sources is in an input format
that the TMC22x9x can accept, and

Figure 21. Adding a 3rd Layer
2-LAYER COMPOSITE

KEY

3-LAYER COMPOSITE

1m KIDS !I
FOREGROUND

27037A

2-70

Raytheon Semiconductor

For More Information call1.aoO-722-7074.

TMC22X9X
Figure 22. Adding a 4th Layer

3-LAYER COMPOSITE

KEY

4-LAYER COMPOSITE

DOWNSTREAM KEY

27038A

2. The sources either synchronize the TMc22x9x
(Genlock mode) or are synchronized by the
TMC22x9x (Master or Slave mode).
Key signals may be generated external to the
TMC22x9x (Hardware Keying) and use the KEY
input pin for control. Key signals may also be
generated within the TMC22x9x (Data Keying) by
the comparison of input color data with color data
stored in the TMC22x9x.
2-Layer Keying with the TMC220901091
The TMC22090/091 facilitates the keying of PO
port input data over the CVBS ~us input data.
Keying is controlled on a pixel-by-pixel basis by
either the KEY input pin of the internal Data Key
function. The first two layers in the previous 4Layer Example apply to the TMC22090/091. The
result

For Mora Information call 1-800·722·7074.

of keying is an effect where a MIDGROUND source
image (i.e. Happy Face from PO data) is
superimposed over a BACKGROUND source
image (I.e. variable matte color from CVBS data).
Assigning Video Sources to Layers with the
TMC22190/191
Digital video inputs to the TMC22190/191 (PO,
CVBS, Overlay) are assigned to the four layers by
choOSing one of 16 modes of the Layering Control
Register. OVERLAY is always keyed (switched on
a pixel-by-pixel basis from active to transparent) by
the OL4 -O inputs. OVERLAY can not be
programmed to the BACKGROUND layer. The
CVBS digital video bus can be assigned to any of
the four layers and is keyed by the KEY input
signal or internal Data Key comparators. In modes
o thru 7, the CLUTs are not bypassed and the
BYPASS\ input is ignored.

Raytheon Semiconductor

2·71

TMC22X9X
Table 15. Layer Assignments, Image Sources, and Keying Controls (22190/191)
LCROC

BACKGROUND

LAnlODE

Image Sou,.,.

Image Sou,.,.

Keying CcnroI

0
1
2
3

PD(YCaCR, AGB, C~
PD(YCaCR, AGB, C~
PD(YCaCR, AGB, C~
PD(YCaCR, AGB, CQ

CVBS
CVBS
CVBS
CVBS

KEY or Data Key
KEY or Data Key
KEY

4
5

CVBS
OVERLAY
CVBS
PD(YCaCR' AGB, C~
CVBS
PD(YCaCR' AGB, C~
CVBS
PD(YCaCR' AGB, CQ

6
7

MlDGROUND

FOREGROUND
Keying Control:

OVERLAY
PD(YCaCR, AGB, CQ
PD(yCaCR, AGB, CQ

~
DataKey\
Dala Key
KEY or Data Key

KEY

PD(YCaCR, AGB, CQ
OVERLAY
OVERLAY
OVERLAY

CVBS
PD(YCBCR, C~
OVERLAY

KEY or Dala Key
BVPASSI

OVERLAY
PD(YCaCR, CQ
PD(RGB)
CVBS

~
BVPASSI

KEY
~
KEY or Data Key
KEY

8
9
A
B

PD(YCaCR, CI)
PD(RGB)
PD(RGB)
PD(RGB)

CVBS
PD(yCBCR, C~
CVBS
CVBS

KEY or Data Key
BVPASSI
KEY or Data Key
KEY or Data Key

C
0
E

PD(RGB)
CVBS
CVBS
PD(RGB)

PD(yCBCR, C~
PD(RGB)
OVERLAY
OVERLAY

BVPASSI
KEY

F
Nollls:

1.
2.
3.

~
~

Image SounMI:

Keying CcnroI

OVERLAY
OVERLAY

~
~

PD(YCa~, AGB, CQ
PD(YCaCR' AGB, CQ

DataKey\
DaIaKey

OVERLAY
OVERLAY
PD(yCBCR, CQ

~-o
~-o
BVPASSI
KEY or Data Key

KEY

CVBS
OVERLAY
PD(yCBCR, CQ

KEY or Dala Key

PD(YCB~,CQ

.

~
~
~

.

.

~

~
BVPASSI
BVPASSI

For LAYMODE = 0 to 7, Pixel Data always passes through the CLUTs. FORMAT, INMOOE, and the BYPAss\ pin selects
the input format for PD23-0 aocorcing to Table 7.
For LAYMODE = 8 to F and BYPAss\ = HIGH, Data Key is disabled.
Asserting the signallisllld under ·Keying Control:" enables the oolTllSponding "Signal Souroa:". Signals with ..." are asserted
by a logic LOW.

Hardware Keying

The KEY input switches the COMPOSITE D/A
converter input from the luminance and
chrominance combiner output to the CVBS data
bus on a pixel-by-pixel basis. This is a "soft"
switch, executed over four PXCK periods to
minimize out-of-band transients. Keying is
accomplished in the digital composite video
domain. The video signal from the CVBS bus is
only present on the COMPOSITE output. The
CHROMA and LUMA outputs continue to present
encoded PD port data when CVBS is active.
Hardware keying is enabled by the Key Control
Register bit 6. Normally, keying is only effective
during the Active Video portion of the waveform (as
determined by the VA registers 15 and 18. That is,
the Horizontal Blanking interval is generated by the
encoder state machine even if the KEY signal is
held HIGH through Horizontal Blanking. However,
it is possible to allow digital Horizontai Blanking to

2-72

DOWNSTREAM KEY

Image Sou,.,.:

be passed through from the CVBS bus to the
COMPOSITE output by setting Key Control
Register bit 5 HIGH. In this mode, KEY is always
active, and may be exercised at will.
The KEY input is registered into the encoder just
like Pixel Data is clocked into the PD port. It may
be considered a 25th Pixel Data bit. It is internally
pipelined, so the midpoint of the key transition
occurs at the output of the pixel that was input at
the same time as the KEY signal.
Data Keying

Data Keying internally generates a Key signal that
acts exactly as the external KEY signal. There are
three Key Value Registers 05, 06, and 07 that are
matched against the input data to the three CLUTs.
These tables are designated D, E, and F, because
they contain different information depending on the
input mode selected:

Raytheon semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Figure 23. Hardware Keying
PXCK
CVBS
KEY

PO
COMPOSITE
OUTPUT

*

KEY is advanced five PXCK cycles when
Control Register OE bit 4 is HIGH (22091/191).

J
24359A

The key registers may be individually enabled
using bits 3,2,1 of the Key Control Register. Bit 4
of the same register enables/disables data Keying
in its entirety. Data Keying and Hardware Keying
are logically ORed: when both are enabled, either
one will result in a key switch to the CVBS channel.
The key comparison is based on the input data to
the CLUTs. When operating in color-index mode,
all three CLUTs receive the same input value, so
anyone of the three registers is sufficient to identify
a key value. The outputs of all enabled key
registers are ANDed to produce the KEY signal. If
more than one key register are enabled and their
key values are not identical, no key will be
generated.
Table 16. Table D, E, F Contents
Mode

TableD

Table E

TableF

RGB
GBR
YCBCR
CI

Red
Green
Y
CI

Green
Blue
CB
CI

Blue
Red
CR
CI

For More Information call 1-800-722-7074.

Genlock Interface
The TMC22x9x can bring digital composite video
into its CVBS port, accompanied by separate
horizontal and vertical sync signals. It has been
designed to couple tightly with the companion
TMC22070 Genlocking Video Digitizer, but other
sources may use this port as well.
Digital composite video is in standard S-bit binary
format at a PXCK / 2 rate. Synchronization with
the internal PXCK / 2 is established by the phasing
of the GHSYNC\ input.
Subcarrier frequency and phase data are received
by the encoder over the CVBS bus as 4-bit nibbles
on CVBS3-o during the horizontal sync period.
Field identification is also required for the
TMC22x9x intemal sync generator. The 14th
nibble of the sequence contains no relevant data.
The TMC22070 provides these data - the Genlock
Reference Signal (GRS).

Raytheon Semiconductor

,

2-73

TMC22X9X
Figure 24. Data Keying

PXCK
CVBS

PO
COMPOSITE
OUTPUT

J
24360A

Figure 25. Genlock Interface Timing

PXCK

GHSYNC\
CVBS7:0
24341 A

Figure 26. Frequency/Phase Data Transfer

PXCK

GHSYNC\

cves7 :o

I~ ~Ic

FIELD

2-74

FREQUENCY----.oK---

IDE~TIFICATION

Raytheon Semiconductor

24383A

For More Information call 1-800-722-7074.

TMC22X9X
Filtering
The TMC22x9x incorporates internal digital filters
to establish appropriate bandwidths and simplify
external analog filter deSigns.

Since these are fixed-coefficient digital filters, their
filter characteristics depend upon clock rate.
Figures 25 and 26 show the frequency response
for two pixel rates, 12.27 MHz and 14.75 MHz.

Color-Difference Low-Pass Filters
Figure 28. Chroma Modulator and Luminance
Interpolation Filter Full Spectrum Response

The chrominance portion of a composite video
signal must be sufficiently bandlimited to avoid
cross-color and cross-luminance distortion, and to
preclude exceeding the allowable bandwidth of a
video channel.
The color-difference low-pass filters on the
TMC22x9x establish chrominance bandwidths
which meet the specifications outlined in CCIR
Report 624-3, Table II, Item 2.6, for system lover a
range of pixel rates from 12.27 Mpps to 14.75
Mpps. Equal bandwidth is established for both
color-difference channels.

o

3

6

9

12

15

Frequency (MHz)

Figure 29. Chroma Modulator and Luminance
Interpolation Filter Passband Detail

Figure 27. Color-Difference Low-Pass Filter
Response
o
·10
~·20

CD

:E. ·30

5 -40
~.50
c:
Ql

~

·60

·70

Frequency (MHz)

·80
2

6

8

Frequency (MHz)

Interpolation Filters
The Chroma Modulator output and the luminance
data path are digitally filtered with sharp-cutoff lowpass interpolation filters. These filters ensure that
aliased subcarrier, chrominance, and luminance
frequencies are suffiCiently suppressed in the
frequency band above base-band video and below
the pixel frequency (fs/4 to 3fs/4, where fs is the
PXCK frequency).

For More Information call 1-800·722·7074.

Virtually all digital-to-analog reconstruction systems
exhibit a high frequency roll-off as a result of the
zero-order hold characteristic of classic D/A
converters. This response is commonly referred to
as a sin(x)/x response. It is a function of the
sampling rate of the output D/A.
The TMC22x9x's digital interpolation filters convert
the data stream to a sample rate of twice the pixel
rate. This results in much less high frequency
sin(x)/x rolloff and the output spectrum between
fs/4 and 3fs/4 contains very little energy. Since
there is so little signal energy in this frequency
band, the demands placed on the output
reconstruction filter are greatly reduced. The

Raytheon Semiconductor

2-75

TMC22X9X
output filter needs to be flat to fs/4 and have good
rejection at 3fs/4. The relaxed requirements
greatly simplify the design of a filter with good
phase response and low group delay distortion. A
small amount of peaking may be used to
compensate residual sin(x)/x roll off.
Figure 30. Sln(x)/x Response At 1x Pixel-Rate
Conversion

.~ ........1 ..:::::::;::::::::::[····::···T:::::::=1::::::::=[::::::r::::::]
iii

:

!

·········+·········i··········.·········+·· '-i'

_

·2

~

·5 ........

.f.14.~Mpps

i

···.··········.·········i

~ : ::::::::i:::::::::l::::.~.:i~:~.~±. ::::::j:::...:::+··...::::~::···::::i
J.........j..........l.........i .........J..........l....... L.......~

+. . . .+. . . +. . . .+. . . +. . . +. . . .

j :: ::::::::i:::::::::j::::::::::/:::::::::i:::::::::j::::::::::l::::::::::t::..:::-l
+.·······1

JTAG Test Interface
The JTAG test port accesses registers at every
digital 1/0 pin except the JTAG test port pins.
Table 17 shows the sequence of the test registers.
The register number (Reg) indicates the order in
which the register data is loaded and read (Reg 1
is loaded and read first, therefore it is at the end of
the serial path). The scan path is 59 registers long.
The six TEST pins of the TMC220901091 function
as JTAG registers .
The JTAG port is a 4-line interface, following IEEE
Std. 1149.1-1990 specifications. The Test Data
Input (TOI) and Test Mode Select (TMS) inputs are
referred to the rising edge of the Test ClocK (TCK)
input. The Test Data Output (TOO) is referred to
the falling edge of TCK.

·8 .•••...

.9D~~--~2--~3---4~~5~~6--~7--~8

......

Frequency (MHz)

Figure 31. Sln(x)/x Response At 2X Pixel-Rate
Conversion
D

'-r...· ·...····¥=···;;;;····;.:::···L:········T······T·······r······T········1
I

,i:

I

·········+·········i··········.·········+··· ..+..

i

til

i

:

!

!

i

i

····.·········+········i

t. . . . .l. . .~.:r~.~T--. . . .l..........i.. ...~..... j
! . . . . .t. . . . .l. . . . . t.
~

f= 12.27 Mpp.

·1 ••••••.•.

~

i!

i

i

t.........

I

!

I

:

3

4

l..........~.........~.........~....··.·.·i··········f·········~
!
!
1
!
1
!
!

·2 .•.•.•.•.~ ••.•.•••.

D

:

f.14.75Mpps

f._29.5DMsps

2

5

Frequency (MHz)

2-76

6

7

8

......

Raytheon Semiconductor

For More Information calI1..aoo-722-7074.

TMC22X9X
Table 17. JTAG Interface Connections
Reg

Pin

Signal

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

28
29

BYPASS\ (TEST)
Ol4 (TEST)
CVBS 7
CVBS6
CVBSs
CVBS 4
Ol3 (TEST)
Ol2 (TEST)
Oll (TEST)
Olo (TEST)
P0 23
P0 22
P0 21
P0 20
P0 19
POlS
P0 17
P0 16
POlS
P0 14

44

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61

Reg

Pin

Signal

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

62
63
66
67
68
69
70
71
72
73
74
75
76

P0 13
PD 12
POll
P0 10
P0 9
POe
P0 7
P0 6
PO s
P0 4
P03
P0 2
POl
POo
lDV
PXCK
GVSYNC\
GHSYNC\
CVBS3
CVBS2

77

78
79
82
83
84
1

Reg

Pin

Signal

41
42

2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
21

CVBS 1
CVBS o
KEY
RESET\
CS\
R/w\
Al
Ao
POC
VHSYNC\
VVSYNC\

43
44

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

°7
06
Os
°4
03
°2
°1
00

Figure 32. JTAG Test Port Timing

TCK
TDI
TMS
TDO
24333A

For More Information call 1-800-722-7074_

Raytheon Semiconductor

2-77

TMC22X9X
Figure 34. Equivalent Analog Output Circuit

Figure 33. Equivalent Analog Input Circuit
Voo

RREF o---+--+--t---1
COMPOSITE
LUMA
CHROMA

VREFo----r~r--~F====E==~~

27013A

27012A

Figure 35. Equivalent Digital Input Circuit

Figure 36. Equivalent Digital Output Circuit
Voo

Input

0--+-----;
.---~~o

Output

Figure 37. Transition Levels for Three-State Measurements

CS\

1/

~

tHOM

tooz
~ 0.5 V

~~---~j:~----~:~-~--- K
iO.5 V

0.8 V
27029A

2-78

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TMC22X9X
Absolute Maximum Ratings (beyond which the device may be damaged)
Power Supply Voltage .............................................................................................................-0.5 to +7.0V
Digital Inputs
Applied VOltage 2 ...................................................................................................... -0.5 to Voo+0.5V
Forced Currents· 4 ...................................................................................................... -20.0 to 20.0 rnA
Digital Outputs
Applied VOltage2 ...................................................................................................... -0.5 to Voo+0.5V
Forced Current3 .4 ....................................................................................................... -20.0 to 20.0mA
Short Circuit Duration (Single output in HIGH state to GND) ............................................... l second
Analog Output Short Circuit Duration (Single output to GND) ...........................................................infinite
Temperature
Operating, case .............................................................................................................-60 to + 130°C
Operating, Junction, Plastic package ......................................................................................+ 150°C
Lead, soldering (1 0 seconds) ..................................................................................................+3OO°C
Vapor phase soldering (1 minute) ...........................................................................................+220°C
Storage ..........................................................................................................................-65 to + 150°C

Notes:

1.

2.
3.
4.

Absolute maximum ratings are limiting values applied individually while all other parameters
are within specified operating conditions. Functional operation under any of these
conditions is NOT implied.
Applied voltage r:lust be current limited to specified range, and measured with respect to
GND.
Forcing voltage must be limited to specified range.
Current is specified as conventional current, flowing into the device.

For More Information call HlOO-722-7074.

Raytheon Semiconductor

2-79

TMC22X9X
Operating Conditions
Temperature Range
Standard
Parameter
Voo

Power Supply Voltage

V IH

Input Voltage, Logic HIGH
TTL Compatible Inputs, all but PXCK
TTL Compatible Input PXCK
CMOS Compatible Inputs

V IL

Input Voltage, Logic LOW
TTL Compatible Inputs
CMOS Compatible Inputs

IOH
IOL

Output Current, Logic HIGH
Output Current, Logic LOW

V REF
IREF

RREF

External Reference Voltage
D/A Converter Reference Current
(IREF = V REF I RREF' flowing
out of the RREF pin)
Reference Resistor, VREF = Nom.

ROUT

Total Output Load Resistance

TA

Ambient Temperature, Still Air

Min

Nom

Max

Units

4.75

5.0

5.25

V

2.0
2.5
(2/3)Voo

Voo
Voo
Voo

V
V
V

GND
GND

0.8
(1/3)Voo

V
V

-2.0
4.0

mA
mA

2.1

1.235
3.15

4.4

V
mA

281

392

588

Q

37.5

Q

0

70

°C

12.27
24.54

15
30

Mpps
MHz

Pixel Interface
fpXL
f pXCK

Pixel Rate
Master Clock Rate, 2x pixel rate

tpWHPX
tpWLPX

PXCK Pulse Width, HIGH
PXCK Pulse Width, LOW

10
10

ns
ns

tsp
tHP
tHP

For PD,VVSYNC\,VHSYNC\,PDC,KEY
Setup Time
Hold Time, PD and KEY
Hold Time, PDC, VHSYNC\, VVSYNC\

12
0
5

ns
ns
ns

10
15
10

ns
ns
ns

Delay Time, LDV
tXL
tpWHLDV LDV Pulse Width, HIGH
tpWLLDV LDV Pulse Width, LOW

2-80

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Operating Conditions
Temperature Range
Standard
Parameter

Min

Nom

Max

Units
PXCK
periods
H

tpWLVH

VHSYNC\ Pulse Width, LOW

6

15

tpWHVV

VVSYNC\ Pulse Width, LOW

0.5

3

Genlock Interface
tSGI
tHGI

Setup Time, GHSYNC\,GVSYNC\,CVBS
Hold Time, GHSYNC\, GVSYNC\,CVBS

10
0

ns
ns

Microprocessor Interface
tpWLCS
tpWLCS
tpWHCS

CS\ Pulse Width, LOW, wI KEY Reg.
CS\ Pulse Width, LOW, wlo KEY Reg.
CS\ Pulse Width, HIGH

95
55
30

ns
ns
ns

tSA
tHA

Address Setup Time
Address Hold Time

10
0

ns
ns

tso
tHo

Data Setup Time (write)
Data Hold Time (write)

15
0

ns
ns

tSR
tHR

Reset Setup Time
Reset Hold Time

24
2

ns
ns

JTAG Interface
f TCK

Test Clock (TCK) Rate

20

MHz

tpWLTCK TCK Pulse Width, LOW
tpWHTCK TCK Pulse Width, HIGH

25
10

ns
ns

t STP
t HTP

10
3

ns
ns

Test Port Setup Time, TDI, TMS
Test Port Hold Time, TDI, TMS

Note: 1. Timing reference pOints are at the 50% level.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-81

TMC22X9X
Electrical Characteristics
Temperature Range
Standard
Parameter
100
IOOQ

VRO

Power Supply Current 1
Power Supply Current 1
(D/A disabled)

Conditions
V oo=Max,f pXC t<=30MHz
Voo=Max,fpXCK=30MHz

0.988

'BR

Voltage Reference Output
Input Bias Current, VREF

VREF = Nom

'IH
'll

Input Current, Logic HIGH
Input Current, Logic LOW

Voo = Max, VIN = 4.0V
Voo = Max, VIN = O.4V

VOH
Val

Output Voltage, Logic HIGH
Output Voltage, Logic LOW

IOH = Max
'Ol = Max

IOZH
IOZl

Hi-Z Leakage current, HIGH
Hi-Z Leakage current, LOW

Voo = Max, VIN = Voo
Voo = Max, VIN = GND

CI

Digital Input Capacitance
Digital Output Capacitance

TA = 25°C, f = 1MHz
T A = 25°C, f = 1MHz

Co

Min

VOC Video Output Compliance Voltage
ROUT Video Output Resistance
COUT Video Output Capacitance
lOUT = 0 mA, f = 1 MHz

Typ

Max

Units

300

350
90

mA
mA

1.235
100

1.482

10
-10

J.lA
J.lA

0.4

V
V

10
-10

J.lA
J.lA

10

pF
pF

2.0

V
kn
pF

2.4

4
10
-0.3
15
15

V

J.lA

25

Note 1. Typical 100 with Voo=+5.0 Volts and T A=250C, Maximum 100 with V oo=+5.25 Volts and T A=OoC.

2-82

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Switching Characteristics
Temperature Range
Standard
Parameter

Conditions

Min

Typ

Max

PIPES Pipeline Delay3

PD to Analog Out

44

44

44

PXCK
periods

23
125
100

ns
ns
ns
ns

30

ns

tool
tOOM
tOOM
t HOM

Output Delay, CS\ to Icw-Z
Output Delay, CS\ to Data Valid4 with KEY Register
Output Delay, CS\ to Data Valid4 without KEY Register
Output Hold Time, CS\ to hi-Z

tOOTP Output Delay, TCK to TDO Valid
tHOTP Output Hold Time, TCK to TDO Valid
toos

Output Delay

PXCK to VHSYNC\,
VVSYNC\, PDC

tR
tF

D/A Output Current Risetime
D/A Output Current Falltime

10% to 90% of full-scale
90% to 10% of full-scale

toov

Analog Output Delay

Notes:

1.
2.
3.
4.

8
10

Units

m

5
25

ns

2
2

ns
ns

20

ns

Timing reference, pOints are at the 50% level.
Analog C LOAO <10 pF, D7-0 load <40 pF.
Pipeline delay, with respect to PXCK, is a function of the phase relationship between the
internally generated PCK (PXCKl2) and PXCK, as established by the hardware reset).
tOOM (without KEY Register) = 1 PXCK + 54 ns = 100 ns worst-case at PXCK=24.54 MHz.

For More Information caJI1-800-722-7074.

Raytheon Semiconductor

2-83

TMC22X9X
System Performance Characteristics
Temperature Range
Standard
Parameter

Conditions

Min

Typ

Max

10

10

10

RES

D/A Converter Resolution

ELI
ELO

Integral Linearity Error
Differential Linearity Error

0.25
0.15

EG

Gain Error

±5

dp
dg

Differential Phase PXCK = 24.54 MHz,40 IRE Ramp 3
PXCK = 24.54 MHz,40 IRE Ramp3
Differential Gain

0.5
0.9

SKEW CHROMA to LUMA Output Skew

0

PSRR Power Supply Rejection Ratio

0.5

Notes

2-84

1.
2.
3.

CCOMP=0.1 I1F, f=1kHz

Units
Bits
%
0/0
%FS
degree
%

1

ns
%I%~VDD

TTL input levels are 0.0 and 3.0 Volts, 10%-90% rise and fall times <3 ns.
Analog C LOAD <10 pF, D7-0 load <40 pF.
NTSC

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Figure 38. NTSC Vectors

Figure 39. NTSC Color Bars Waveform

Figure 40. NTSC Horizontal Blanking Interval

Figure 41. NTSC Vertical Blanking Interval

Figure 42. NTSC Differential Gain

Figure 43. NTSC Differential Phase

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-85

TMC22X9X
Figure 44. PAL Vectors

Figure 45. PAL Color Bars Waveform

Figure 46. PAL Horizontal Blanking Interval

Figure 47. PAL Vertical Blanking Interval

Figure 48. PAL Differential Gain

Figure 49. PAL Differential Phase

2-86

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Figure 50. Color Bar Luminance

Figure 51. Color Bar Chromlnance

Figure 52. Short Time Distortion

Figure 53. K Factor

Figure 54. NTSC Multlburst

Figure 55. PAL Multiburst

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-87

TMC22X9X
Figure 56. Recommended Interface Circuit

=

r------------------------~

E!t,

+5V

I

+5V

BYPASSI and 040
on TMC221901191 only.
VODA
CHROMA
]

TMC22x9x

COMPOSITE VIDEO
OUTPUT

COMPOSITE

DIGITAL VIDEO
ENCODER

O.1(1F Voo
COMP
3.3KO

z>
ri1S;
:Dr

VR£F
LM185-1.2

~8

RR£F
3920

MICROPROCESSOR
INTERFACE

S-VIDEO OUTPUT

LUMA

JTAG TEST
INTERFACE

O.1(1F

m

27007A

Application Notes
The TMC22x9x is a complex mixed-signal VLSI
circuit. It handles TTL digital signals at clock rates
of up to 30 MHz while producing analog outputs
with a resolution of less than a millivolt. To
maximize performance it is important to provide the
product with a quiet operating environment.

the video outputs. The reference bandwidth is
limited by the 0.1 JlF capacitor on the COMP pin,
but low frequency signals (eg 60 Hz, 20 KHz power
supply noise) will be passed through to the outputs.

References

An inexpensive low-pass output filter is shown in
Figure 57. This filter is located in the video Signal
path just after the COMPOSITE, LUMA, and
CHROMA outputs of the TMC22x9x. The
TMC22x9x has been designed to output adequate
video levels to overcome the insertion loss of
output filters. VREF and RREF may be varied to
make up for filter loss. Since S-VIDEO comprises
separate and simultaneous luminance and
chrominance, it is important that the filters used on
CHROMA and LUMA have identical group delay.

The circuit shown provides a stable external
1.235V voltage reference to the TMC22x9x. To
use the internal voltage reference source, simply
leave the VREF pin unconnected except for the 0.1
JlF capacitor to ground. The accuracy the internal
voltage reference is approximately ±20%. This
variation can be overcome by varying the RREF
resistor to get desired video output levels. It is
recommended that a simple voltage divider from
the power supply NOT be used, as any variations
in power supply voltage would appear directly on

2-88

Filtering

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
TMC22070 Genlocking Video Digitizer. The
TMC22070 is the source for TMC22070 input
signals CVBS7_0 , GHSYNC\, GVSYNC\, and PXCK
as shown in Figure 59. These signals directly
connect to the TMC22190/191. The
microprocessor interface for TMC22x9x and
TMC22070 are identical. All W/R\, RESET\, data
and address bus Signals from the host
microprocessor are shared by the TMC22x9x and
TMC22070. Only CS\ and INT\ signals are
separately driven from the microprocessor bus.

Figure 57. Recommended Output
Reconstruction Filter

-=' O-p__--p__JVV'''''-~"'"""'''C'l.:::::::lf--p__--o
I1H

Encoder

1.8

=

27pF

27025A

Grounding Strategy

Figure 58. Response of Recommended Output
Filter

The TMC22x9x has distinctly separate analog and
digital circuits. To minimize digital crosstalk into
the analog signals, the power supplies and grounds
are provided over separate pins (VDD and DGND
are digital power supply pins; VDDA and ~ND are
analog supplies). In general. the best results are
obtained by tying all grounds to a solid, lowimpedance ground plane. Power supply pins
should be individually decoupled at the pin. Power
supply noise isolation may be provided between
analog and digital supplies via a series inductor.

i~i~II~~f
~

o

: : : : 300

15

20

25

Frequency (MHz)

Another approach calls for separating analog and
digital ground. While some systems may benefit
from this strategy, keep in mind that the analog and
digital grounds must be kept within O.5V of each
other at all times.

Interface to the TMC22070 Genlocklng Video
Digitizer
The TMC22x9x Digital Video Encoder has been
designed to directly interface to the

Figure 59. TMC22x9x-to-TMC22070 Interface Circuit
eV8s,~

TMC22070

8

GHSYNC\
GVSYNC\
PXCK
LOV

eves...
GHSYNCI
GVSYNC\
PXCK
LOV

GENLOCKING VIDEO DIGITIZER

Iii
~ &~!1 ~

i rT

TMC22x9x

DIGITAL VIDEO ENCODER

Iii

~ ceo
II !! iii ~

TTTT

T

I~I
MICROPROCESSOR
INTERFACE

For More Information call 1-800-722-7074.

Raytheon Semiconductor

27OO9A

2-89

TMC22X9X
Printed Circuit Board Layout

Microprocessor 1/0 Operations

Designing with high-performance mixed-signal
circuits demands printed circuits with ground
planes. Wire-wrap is not an option. Overall
system performance is strongly influenced by the
board layout. Capacitive. coupling from digital to
analog circuits may result in poor picture quality.
Consider the following suggestions when doing the
layout:

Various CLUT Read/Write operations are shown in
Table 18. Each step in the table requires a CS\
pulse (falling edge followed by a rising edge) to
execute.

1.

Keep analog traces (COMP, VREF' RREF'
CHROMA, LUMA, COMPOSITE) as short and
far from all digital signals as possible. The
TMC22x9x should be located near the board
edge, close to the analog output connectors.

2.

The power plane for the TMC22x9x should be
separate from that which supplies other digital
circuitry. A single power plane should be used
for all of the VDD pins. If the power supply for
the TMC22x9x is the same for the system's
digital circuitry, power to the TMC22x9x should
be filtered with ferrite beads and 0.1 J.LF
capaCitors to reduce noise.

3.

The ground plane should be solid, not crosshatched. Connections to the ground plane
should be very short.

4.

Decoupling capacitors should be applied
liberally to VDD pins. For best results, use
0.1J.1F capacitors in parallel with'0.01J.1F
capacitors. Lead lengths should be minimized.
Ceramic chip capacitors are the best choice.

5.

If there is dedicated digital power plane, it
should not overlap the TMC22x9x footprint, the
voltage reference, or the analog outputs.
Capacitive coupling of digital power supply
noise from this layer to the TMC22x9x and its
related analog circuitry can have an adverse
effect on performance.

For Write operations, R/W\ and A1-0 must conform
to setup and hold timing with respect to the falling
edge of CS\. 0 7-0 must meet setup and hold timing
with respect to the rising edge of CS\. These
timing relationships are illustrated in Figure 11.
When writing data into an internal register (i.e.
CLUT Address Register) an extra CS\ falling edge
is required to transfer the input data to that register.
This requirement is usually accomplished by
executing the next step in the sequence. If there is
no planned next step in the sequence, executing a
Control Register Read step will meet the
requirement and terminate the sequence.
For Read operations, R/W\ and A1-o must conform
to setup and hold timing with respect to the falling
edge of CS\. Read data on 0 7 -0 is initiated by the
falling edge of CS\ and terminated by the rising
edge of CS\ as shown in Figure 12. When reading
Control Registers, valid data appears tooM after
the falling edge of CS\. When reading CLUT
locations, an extra CLUT Read step is needed to
set up the CLUT Read sequence. This is
accomplished in the table by executing an extra
CLUT Read step just before the CLUT Read
sequence which returns successive d, e, and f
data. CLUT Read sequences must be terminated
an extra CS\ falling edge. This requirement is
usually accomplished by executing the next VO
step. If there is no planned next step in the
sequence, executing a Control Register Read step
will meet the requirement and terminate the
sequence.

6. The PXCK should be handled carefully. Jitter
-and noise on this clock or its ground reference
will translate to noise on the video outputs.
Terminate the clock line carefully to eliminate
overshoot and ringing.

2-90

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22X9X
Table 18. CLUT ReadIWrlte Sequences
Step RJW\ A1.() D7.()

Function

Step RJW\ A 1.()

Write Entire CLUT
Starting at Address 00
1

0

2

0

3

0

4

0

..
767

0

768

0

769

0

770

1

01

Write 00 into CLUT
Address Register.
11
d1
d1 written into 0, CLUT
address 00.
11
e1
e1 written into E, CLUT
address 00.
f1 written into F, CLUT
11
f1
address 00.
.. repeat steps 3,4,5 until
CLUT is full.
11 d256 d256 written into 0, CLUT
address FF.
11 e256 e256 ",!ritten into E, CLUT
addres.s FF.
11 f256 f256 written into F, CLUT
address FF.
00
xx Sequence termination.
00

..

0

01

2

0

11

3

0

11

4

0

11

5

1

00

addr Write addr into the CLUT
Address Register.
d1 . d1 written into 0, CLUT
address addr.
e1
e1 written into E, CLUT
address addr.
f1
f1 written into F, CLUT
address addr.
xx Sequence termination.
Read (:LUT Location
addr

1

0

01

2

1

11

3

1

11

4

1

11

5

1

11

6

1

00

addr Write addr into the CLUT
Address Register.
xx Set up for CLUT Read
sequence.
d1
d1 read from 0, CLUT
address addr.
e1
e1 read from E, CLUT
address addr.
f1
f1 read from F, CLUT
address addr.
xx Sequence termination.

For More Infonnation call 1-800·722·7074.

Function
Read CLUT Address
Register Then Write

1

1

01

2

0

11

3

0

11

4

0

11

5

1

01

6

0

11

7

0

11

8

0

11

9

1

00

Write CLUT Location
addr
1

Dr.()

addr Read CLUT Address
Register.
d1
d1 written into 0, CLUT
address addr.
e1
e1 written into E, CLUT
address addr.
f1
f1 written into F, CLUT
address addr.
addr+1 Read CLUT Address
Register. (terminates
Write sequence)
d2 d2 written into 0, CLUT
address addr+1.
e2 e2 written into E, CLUT
address addr+1.
f2
f2 written into F, CLUT
address addH 1.
xx Sequence termination.
Read/ModlfylWrlte CLUl
Location addr

1

0

01

2
3

1
1

11
11

4

1

11

5

1

11

..
6

0

01

7

0

11

8

0

11

9

0

11

10

1

00

Raytheon Semiconductor

addr Write addr into the CLUT
Address Register.
xx Set up for CLUT Read.
d1
d1 read from 0, CLUT
address addr.
e1
e1 read from E, CLUT
address addr.
f1
f1 read from F, CLUT
address addr.
.. System Modifies d1, e1,
f1 to d1', e1', f1'.
addr Write addr into the CLUT
Address Register.
(terminates Read
sequence)
d1' d1' written into 0, CLUT
address addr.
e1' e1' written into E, CLUT
address addr.
f1' f1' written into F, CLUT
address addr.
xx Sequence termination.

2·91

TMC22X9X
Table 19. Pin Assignments for 84-lead PLCC Package {RO}
Pin

Name

Pin

Name

Pin

Name

Pin

Name

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

CVBS2
CVBS 1
CVBSo
KEY
RESEn
CS\
RIW\
Al

22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

TOO
TCK
TMS
TOI

43

VDDA
CVBS7
CVBSs
CVBSs
CVBS4
OL3{TEST)
04(TEST)
OL1(TEST)
OLo(TEST)
P023
P0 22
P0 21
P0 20
P0 19
POlS
P0 17
POlS
POlS
P0 14
P0 13
P0 12

64

V DD

65
66
67
68
69
70
71
72
73
74
75
76

°GND
P0 11
POlO
P0 9
PO s
P07
PO s
POs
P04
P03
P02
POl
PO o
LOV
PXCK

Note:

Ao
°GND
POC
VHSYNC\
VVSYNC\
07
Os
Os
04
03
O2
01
Do

°GND
V DD
BYPASS\(TEST)
OL4(TEST)
V REF
RREF

~ND

44

45
46
47

48
49
50
51
52
53

COMPOSITE

54

~ND

55
56
57
58
59
60
61
62

LUMA
AGND
CHROMA

~ND

COMP
V DDA
V DDA
V DDA

63

77
78
79
80
81
82
83

84

°GND
VDD
GVSYNC\
GHSYNC\
CVBS3

Pin names in parentheses apply to TMC22090/091
54

74

53

75

12

32
27024A

2-92

Raytheon Semiconductor

For Mora Information call 1-800-722-7074.

TMC22X9X
Ordering Information
Product
Number

Temperature
Range

Screening

Package

Package
Marking

TMC22090ROC
TMC22091 ROC
TMC22190ROC
TMC22191 ROC

TA = O°C to 70°C
TA = O°C to 70°C
TA = O°C to 70°C
TA = O°C to 70°C

Commercial
Commercial
Commercial
Commercial

84-Lead
84-Lead
84-Lead
84-Lead

22090 ROC
22091 ROC
22190ROC
22191 ROC

PLCC
PLCC
PLCC
PLCC

40007228 Rev D 8/93

For More Information call 1-800·722·7074.

,Raytheon Semiconductor

2·93

TMC22X9X

2-94

Raytheon SemIconductor

For More Information call 1-800-722-7074.

TMC2242
TMC2242
Half-Band InterpolatingIDecimating Digital Wter
12 Bits, 40 MHz

Description
The TMC2242 is a fixed-coefficient, Iinear-phase halfband (Iow-pass) digital filter VLSI circuit which can also
be used to halve or double a digital signal's sample rate.
When used as a decimating post-filter wnh a doublespeed oversampling video AID converter, it greatly
reduces the cost and complexity of the associated
analog antialias pre-filter, such as that required for
broadcast video chrominance bandwidth limiting. When
used as an interpolating pre-filter, such as that required
for broadcast video chrominance bandwidth limiting.
When used as an interpolating pre-filter with a doublespeed oversampling DlA converter, the TMC2242 can
simplify the corresponding analog reconstruction postfilter. The only user ·programming" required is selection
of mode (interpolate, decimate, or neither) and rounding.
The TMC2242 accepts 12-bit two's complement data at
up to 40 million samples per second and outputs
saturated, two's complement or inverted offset binary
data, rounded to 9 to 16 bits. Within the 40 MHz 1/0
limit, the TMC2242's output sample rate can be 112, 1,
or 2 times its input sample rate.
The filter is flat within iD.02 dB from 0 to 0.22 FS, with
stopband attenuation of greater than 59.4 dB from 0.28
FS to the Nyquist frequency. The response is 6 dB down
at 0.25 FS. Symmetric-coefficient FIR filters such as the

TMC2242 have linear phase response. Although most
users will be pleased with the results obtained with one
TMC2242 in the system, full compliance with the
SMPTE 601 standard of -12 dB at 0.25 FS requires two
devices cascaded serially.
Fabricated using a one-micron CMOS process, the
TMC2242 operates at a guaranteed clock rate of 40
MHz over the standard temperature and supply voltage
ranges and is available in a 44-lead plastic chip carrier.

Features
•
•
•
•
•
•
•
•
•
•

40 MHz guaranteed maximum clock rate
User-selectable 2:1 deCimation, 1:2 interpolation
Frequency response iD.02 dB in passband
Stopband (0.28 to 0.5 x FS) rejection 59.4 dB
Two-device cascade meets celn recommendation
601 low-pass filter requirements
Dedicated 12-bit two's complement input data port
and 16-bit output data port with user-selectable
rounding to 9 through 16 bits
Two's complement or inverted offset binary output
format
Built-in limiter prevents overflow
Single +5V power supply
Compact 44-lead plastic chip carrier package

Logic Symbol

so, 5-0

TIMING
CONTROLS

{::~ >---~

SYNC ) - -. .

DE } ~~:~~~
1+---< TCO

TMC2242

CONTROLS

14--.J,;3:........( RNO 2-0

CLK)--"

L...._ _ _ _ _

For More Information call 1-800-722-7074.

DATA
OUT

~

Raytheon Semiconductor

21565A

2-95

TMC2242
Applications
• low-Cost, Industry-Standard Video Chrominance
Bandwidth limiting (Anti- Aliasing)
• Simple, High-Performance Video Reconstruction
Post-Filtering
• General Digital-Domain High-Performance low-Pass
Filtering, Requiring:
- Passband Below (0.22) x FS
- Stopband Above (0.28) x FS
• General Digital-Domain Waveform Reconstruction
Post-Filtering
• Telecommunications Systems
• Digitally Synthesized Radio
• Radar

Functional Description
The TMC2242 implements a fixed-coefficient linear-phase
Finite Impulse Response (FIR) filter of 55 effective taps,
with special rate-matching input and output structures to
facilitate 1:2 decimation and 2:1 interpolation. In the
straight-through mode (equal input and output clock rates),

the filter and input and output registers will operate at the
guaranteed maximum clock rate of 40MHz. The total
internal pipeline latency from the input of an impulse to
the corresponding output peak is 33 cycles; the 55-value
output response begins after 6 clock cycles and ends after
60 cycles.
To perform interpolation, the chip slows the effective input
register clock rate to half the internal and output rates. The
TMC2242 internally inserts zeroes between the incoming
data samples to "pad" the input data rate to match the
output rate.
To perform decimation, the chip sets the output register
clock rate to half of the input and internal rates. One output
is then obtained for every two inputs.
In interpolation or decimation mode, the SYNC control is
first held HIGH, then brought lOW with the first data input
value. SYNC is held lOW until resynchronization is desired.
For interpolation, input values should be presented at the
first rising edge of ClK for which SYNC=O and at every
alternate ClK rising edge thereafter.

Figure 1. Functional Block Diagram

SI I1 -0

L---_--<
DEC

INTERPOLATE: 0-1-0-1
ELSE 1-1-1-1

TCO
RND2_0

INT
SYNC

CLK/2IF DECIMATING: ElSE CLK

CLK ~ TO ALL REGISTERS

2-96

OE

21566A

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2242
Figure 2A. Transfer Function of TMC2242 Half-Band
FIR Filter
o

\

-10

-20

Figure 2B. Passband Detail of TMC2242 Transfer
Function
0.03

\

0.112

-30

!i!I

0.01

-1iII
-10

0.00

II~ IIVVl rlA . M

-70

11111 III lOll

.....
o

-0.01

,5OOIs
Frequency

Frequency

21567A

The input data word format is always two's complement.
The output data format is two's complement when TCO is
HIGH and inverted offset binary when TCO is lOW. The
output data can thus be processed further or routed
directed to a Digital-to-Analog converter for reconstruction.
The user can tailor the output data word width to his
system requirements using the Rounding control. As shown
in Table 1, the output is half-lSB rounded to the resolution
selected by the value of RND2-0. The bits below the lSB
are then zero-filled. The asynchronous three-state output
enable control simplifies interfacing to a bus.

Inputs
SI11-0

ClK

S015-0

Note:

SYNC

The TMC2242 operates from a single master
Clock. All internal registers (except output
register in decimate mode) are strobed on
the rising edge of Clock, and all timing
specifications are referenced to the rising
edge of Clock.
The user synchronizes the incoming data
with the TMC2242 by holding SYNC HIGH on
Clock N, and then lOW on Clock N+1, when
the first data word is presented to the input
Slll-0. If DEC=INT (passthrough mode),
SYNC is inactive. SYNC may be held lOW
until resynchronization is desired, or it may
be toggled at 1/2 the clock rate.

For More Information call 101100-722-7074.

Data presented to the registered 12-bit two's
complement data input port Slll-0 will be
latched internally on the current Clock. or on
every other Clock if in INTERPOLATE mode.
SI11 is the MSB.

Outputs

Signal Definitions
Clock

21568A

The current result is available at the
registered 16-bit output port S015-0, halflSB rounded as determined by the rounding
control word RND2-0. S015 is the MSB.

TMC2242's limiter ensures that an internal overflow will generate a valid full·
scale I7FFF positive or 8000 negativel output. The chip's D.C. gain is
1.0015=O.0126dB; 0.5007 =-3.004d8 in INTERPOLATE mode.

Controls
TCO

When the Two's Complement format Control
TCO is HIGH, all output data are presented in
signed two's complement format. When
LOW, the output is inverted offset binary,
obtained inside the chip by inverting bits
S014 through SOO, leaving S015 unchanged.

INT

When the input interpolation controllNT is
lOW, the input register is driven at full clock
speed and the chip inserts zeroes between
samples, "padding" the input to match the
output rate and effectively halving the input
data rate and the output amplitude. The
TMC2242 then interpolates between these

Raytheon Semiconductor

2-97

TMC2242
alternate input data points to achieve a full
output data rate.
DEC

When the decimation output control DEC is
LOW, the output register is driven at half
clock speed, decimating the output data
stream.

Note:

When INT=DEC. both the input and output registers run at the full clock rate.

The output data port S115-0 is in the highimpedance state when the asynchronous
output enable is HIGH. When OE is LOW, the
port is enabled.

Power
VDD, GND

These three pins set the position of the
effective least significant bit of the output
port by adding a rounding bit to the next
lower internal bit and zeroing all outputs
below the rounding bit. See Table 1.

RND2-0

Note:

OE

The TMC2242 operates from a single +5V
supply. All power and ground pins must be
connected.

The above controls. TCO, DEC. INT, and RND2.0 determine the device function.
numeric format. and rounding of the data. The user must exercise caution when
changing them. since they will impact work in progress in the chip's 60 clock
internal pipeline.

Table 1. Input and Output Data Formats and Bit Weighting. TeO=1 1
Bit Weight - Output Port During Interpolation Only2

I

-21

I

20

I

2-1

2-6

2-7

2-8

2-9

2- 10

2- 11

2- 12

2- 13

2- 14

Bit Weight - All other I/O
Rounding
RND2-0

Input
SI11

SI10

Sig

S015

S014

S015

S014

S015

•••

SI4

SI3

SI2

SI1

SID

S013

S08

S07

S06

S05

S04

S03

S02

SOl

SOor

S013

S08

S07

S06

S05

S04

S03

S02

0

001

S014

S013

S08

S07

S06

S05

S04

S03

S02r

SOl'
0

0

010

S015

S014

S013

S08

S07

S06

S05

S04

S03 r

0

0

S015

S014

S013

S08

S07

S06

S05

0

0

S015

S014

S013

S08

S07

S06

S015

S014

S013

S08

S07

S015

S014

S013

S08

S07r

S06r
0

S05r
0

S04r
0

Output

Note:

2-98

0

0
0

000

0

011

0

100

0

0

101

0

0

110

0

111

1. When TCO=O, most significant bit of output is positive instead of negative.
2. During interpolation. device DC gain is approximately 0.5
3. Where "r" indicates the half-LSB-rounded bit. 0 the zeroed LSBs. and a minus sign a sign bit.

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TMC2242
Table 2. Hexadecimal Impulse Response and
Decimal Equivalents of Coefficients
Inpulse
Out 1

Decimal
Equivalent

FFF2
0000
0017
0000
FFOB
0000
0039
0000
FFA8
0000
0070
0000
FF51
0000
00F3
0000
FEB5
0000
01CA
0000
F079
0000
03CO
0000
F95E
0000
145B
2010

-.000875473
.0
.001390457
.0
-.002265930
.0
.003501892

Note: 1.

Table 3. Input Transition Response
INPUT
INT=DEC
TCO=O

coel #1,55
coel #2, 54=0

OUTPUT
INT=O
INT=DEC
DEC=1
TCO=1
TCO=1

INT=1
DEC=O
TCO=1

400
400

XX
XX

XX
XX

xx
xx

XX

xx

400
400
000

3FEl
3FEl

4018
4018

2008
2010

4018
4018

DC gain 1

000

3B90

446F

245F

446F

Max
ringing

000
000
000
000

3B90
4FEB
6FFB
846F

446F
3014
1004
FBA9

2010
1004
0000
FBA9

446F
1004
1004
FBA9

000

lFFF

0000

0000

0000

>55 cycles

-.005355835
.007621765
-.01071167
.01483154

Min
ringing

-.02018738
.02796364
-.03949928

Steady
state

Note: 1. In interpolation. steady-state output will oscillate approximately 0.1%, as
here between 2008 and 2010 .

.05937767
-.1036148
.3180542
.5009766

coel#27,29
coel #28 (center)

~t=0.0.400.0.0.

INT=DEC=l
TCO=l

Table 4. Steady-State Output Values and Limiter Triggers ILl versus Input Data
Input
7FF
400
001
000
FFF
COO
800

INl\ = 1 or DEc\ = 0
TCO=O
TCO =1
0000 (L)
7FFF (U
3FE7
4018
7FEF
0010
7FFF
0000
800F
FFFO
C017
BFE8
FFFF (L)
8000 (U

For More Information call 1-800-722-7074.

INl\ = 0 and DEc\ = 1
TCO =0
TCO=l
3FF7/3FE7
4008/4018
5FF7/5FEF
2008/2010
7FF7
0008
7FFF
0000
8007
FFF8
A007/ AOOF
DFF8/ DFFO
COOF /COIF
BFFI/ BFEO

Raytheon Semiconductor

Interpretation

+ ful~scale
+ 1/2 scale
+ 1 LSB
Zero
-1 LSB
-1/2 scale
- Ful~ale

2-99

TMC2242
Package Interconnections
Signal
Tvpe

Name

Function

R2 Package

Timing Controls

INT
DEC
SYNC
ClK

Interpolate
Decimate
Synchronization
System Clock

44
1
43
42

Data Inputs

Slll-0

Input Data Port

Data Outputs

S015-0

Output Data Port

DE

Output Enable

40,37,36,35,34,33,
32,31,30,27,26,25
4,5,6,7,8,910,11,
14,15,16,17,18,19,
20,21
3

Output Controls

RN02-0

Rounding

22,23,24

Power

VDD
GND

Supply Voltage
Ground

13,29,38
12,28,39,41

Figure 3. Timing Diagram - Equal Rate Mode INT=DEC

ClK

SI11-0)(»(

33

35

I

SYNC

SO 15-0

Note:

2-100

XXX»< XXX»<
36

37

XX}

I

XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX X
X

--] '. r- --]"[

X

2

3

Values at S015-0 are impulse response centers Ipeaks) corresponding to inputs bearing
the same numbers. Thus, the input-to-center latency is 33 registers Iclock cycles).

Raytheon Semiconductor

X

X
21569A

For More Information call 1-800-722-7074.

TMC2242
Figure 4. Timing Diagram - Decimination INT=1, DEC=O

CLK

51"·0

3

XXX»< XXX»< XXX
4

5

ClK

5o15-o_---'xt..Jt.. _______---.l.~

3____

.Ll._ _ _ _ __

____

21570A

Figure 5. Timing Diagram - Interpolation INT=0, DEC=11

CLK

.,,~
o..z-..5!'_COJ:-"!:p_
(!)i>CJ)cncncncnwcnC/»

Pin Assignments - 44 Lead Plastic Chip Carrier - R2 Package
Pin

Name

Pin

Name

Pin

Name

Pin

Name

1
2
3
4

DEC
TCD
OE

12
13
14
15
16
17
18
19
20
21
22

GND
VDD
S07
S06
S05
S04
S03
S02
SOl
SOo
RND2

23
24
25
26
27
28
29
30
31
32
33

RNDI
RNDO

34
35
36
37
38
39

SI7
SI8
SI9
SilO
VDD
GND

40

SI11
GND
ClK
SYNC
INT

5
6
7
8
9
10
11

S015
80 14
S013
S012
SOl1
SOlO
S09
S08

Slo
Sil
SI2
GND
VDD
SI3
SI4
SI5
SI6

41
42
43
44

0

0

~~:;;~~g~~M~~

5111
GND
ClK
SYNC

40
41
42
43

iNT44
DEC 1
TCO
OE
S015 4
S014 5
S013 6

28
27
26
25
24
23
22
21
20
19
18

0

GND
51 2
51 1
Sio
RNDO
RND1
RND2
SOO
S01
502
S03

..... CIOm~~~~~~~~
N

.....

0,

en coo

C

r- u:a an -:r

~~~~g~~~gg~

21578A

Ordering Information
Product
Number
TMC2242R2C
TMC2242R2Cl

Temperature Range

Screening

Package

Package
Marking

STD-TA=O°C to 70°C
STD-TA=O°C to 70°C

Commercial
Commercial

44 lead Plastic Chip Carrier
44 lead Plastic Chip Carrier

2242R2C
2242R2Cl

4OG06433 Rev B 8193

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-107

TMC2242

2-108

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2243
TMC2243
CMOS FIR Filter
10 x 10 Bit, 20 MHz

Description
The TMC2243 is a video speed three stage 10 x 10 bit
FIR (Finite Impulse Response) filter integrated circuit
composed of three registered multiplier-adders
concatenated into a one-----+C

Raytheon Semiconductor

For More Information call HIOO-722-7074.

TMC2243
Figure 4. Typical Adaptive Filter Operation Sequence
Cycle

SI

DI

CI

CWE

0
1
2
3
4
5
6
7
8
9

SIO
Sil
SI2
SI3
SI4
SI5
SI6
SI 7
SiS
SI9
SIlO
Sill
SI12
SI13

010
011
012
013
014
015
016
017
OIS
019
01 10
01 11
01 12
01 13

Al
A2
A3
Bl
B2
B3
Cl
C2
C3

01
10
11
01
10
11

0
0
0
0
0
0

01

SI2
SI3
SI4
SI5
SI6
SI7
SiS
Sig

10

11
12
13

with FTl

~

LOW and FT2,3

~

10
11
00
00

00
IJO
00

SO

+
+
+
+
+
+
+
+

A1D11 +
A1012 +
A1013 +
B1014 +
B1015 +
Bl 016 +
Cl017 +
C10iS +

A2012 + A3013
A2013 + A3014
A2014 + A3015
B2015 + B3016
B2016 + 83017
B2017 + B301S
C20lS + C301g
C2019 + C30110

HIGH lone zero stagel

CI

eWE

DI

so

SI

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-117

TMC2243
Figure 5: Equivalent Input Circuit

Figure 6. Equivalent Output Circuit
VDD
n SUBSTRATE

n SUBSTRATE

Dl

Dl
p+

.....

CONTROL ~~W\r---4I~'"
INPUT
lKn

DUTPUT

n+

D2

D2

D3

P+

-~_-o

P WELl

P WElL
"::' GND

.,.. GNO

Figure 7. Test Load

Figure 8. Transition Levels For Three - State Measurements

TO

500n

OUTPUT PIN ~ VLDAD

J

GND

40PF
THREE-STATE
OUTPUTS

HIGH IMPEDANCE
0.5V

Note:

1. Assumes

2-118

Raytheon Semiconductor

DE

has gone LOW, within the Input Setup requirements.

For More Information call 1-800-722-7074.

TMC2243
Absolute maximum ratings Ibeyond which the device may be damaged I 1
Supply Voltage ...................................................................................................................................................................................................................................... -0.5 to + 7.0V
Input Voltage .............................................................................................................................................................................................................................. -0.5 to IV on +0.5VI
Output

Applied voltage 1 .............................................................................................................................................................................................. - 0.5 to IVOO +0.5VI
Forced current 3,4 ........................................................................................................................................................................................................ -1.0 to 5.0mA
Short - circuit duration Isingle output in HIGH state to groundl ......................................................................................................................................... 1 sec
Temperature
Operating, case .......................................................................................................................................................................................................... -50 to +130°C
junction ....................................................................................................................................................................................................................... 175°C
Lead, soldering 110 secondsl ..................................................................................................................................................................................................... 300°C
Storage ........................................................................................................................................................................................................................ -65 to +150°C
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3. Forcing voltage must be limited to specified range.

4. Current

IS

specified as conventional current flowing into the device.

Operating conditions
Temperature Range
Parameter

Min

Standard
Nom

Von

Supply Voltage

4.75

5.0

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

2.0

IOL
IOH

Output Current, Logic LOW
Output Current, Logic HIGH

TA
TC

Ambient Temperature, Still Air
Case Temperature

For More Infonnation call 1-800-722-7074.

0

Max
5.25

Min
4.5

Extended
Nom
5.0

Max

Units

5.5

V

0.8

0.8

V
V

4.0
-2.0

4.0
-2.0

mA
mA

125

°C
°C

2.0

70
-55

Raytheon Semiconductor

2-119

TMC2243
DC characieristics within specified operating conditions 1

Parameter

Test Conditions

1000 Supply Current, Quiescent
100U Supply Current. Unloaded

Voo
VOO

=

f
f

=

=

=

=

Max. VIN = av, !IE - HIGH
Max. OE = HIGH
20MHz
lDMHz

III
IIH

Input Current, logic lOW
Input Current. logic HIGH

VOO
VOO

VOL
VOH

Output Voltage, logic LOW
Output Voltage, logic HIGH

VOO = Min, 10l = Max
VOO - Min, 10H - Max

IOZl
10ZH
lOS

Hi-Z Output leakage Current, Output lOW VOO - Max, VIN Hi-Z Output leakage Current, Output HIGH VOO = Max, VIN =
Short - Circuit Output Current
VOO = Max, Output
one second duration

CI
Co

Input Capacitance
Output Capacitance

TA
TA

=
=

=

Temperature Range
Extended
Standard
Min
Max
Min
Max

Max, VIN - OV
Max, VIN = VOO

25°C, f
25°C, f

=
=

OV
VOO
HIGH, one pin to ground,
max

15
90

48
-75
-75

75
75

-75
-75

0.4

15

mA

90
48

mA
mA

75
75

f.lA
f.lA

0.4
2.4

2.4
-40
-40

40
40
-150

-40
-40

V
V

40
40
-150

f.lA
f.lA
mA

10
10

pF
pF

10
10

lMHz
lMHz

Units

Note:
1. Actual test conditions may vary from those shown, but guarantee operation as specified.

AC characteristics within specified operating conditions
Temperatll'8 Range
Extended
Min
Max
Min
Max
Standard

Tast Conditions

Parameter

/

Urits

ICY

Cycle Time

VOO - Min

50

50

ns

tPWl
tPWH

Clock Pulse Width LOW
Clock Pulse Width HIGH

VOO - Min
VOO = Min

20
20

20

ns
ns

ts
tSISI)

Input Setup Time
Input Setup Time, S121-& FT1 = HIGH
FTI = lOW

tH
tHISI)

Input Hold Time
Input Hold TIlDe, S121- 6

to
toc
tHO

Output Delay
Output Delay, Cascaded
Output Hold Time

VOO = Min, CLOAO - 40pF
VOO - Min, ClOAO = 10pF
VOO = Max, CLOAO = 40pF

lENA
tOiS

Three-State Output, Enable ~elay 1
Three-State Output, Disable Delay 1

VOO - Min, CLOAO = 40pF
VOO - Min, CLOAO - 40pF

20

ns
ns

15

20

25

18

28
20

2
5

3

ns

5

ns

ns

3D

3D

2D

2D

5

ns

5

2D
15

ns
ns

25
20

ns
ns

Note:
1. All transitions are measured at a 1.5V level except for tOIS and tENA-

2-120

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2243
Application Discussion
loading and Updating of Coefficients

Table 1. Impulse Response

Because of the TMC2243's internal architecture, its impulse
response is C3, C2, Cl, where C3 is the rightmost coefficient
and Cl is the leftmost. However, for glitchless performance,
coefficients must be updated from left to right: Cl then C2
then C3For example, consider an adaptive filter whose first set of
coefficients is Ai, second set is Bi and third set is Ci IFigure
41. First, the TMC2243 is initialized with Ai. If these are loaded
in numerical lIeft to rightl sequence, two of the first three
data points can be loaded with them, as shown in Figure 4.
Immediately after the third coefficient is loaded, the first
coefficient of the next set can be loaded, if desired, along with
the third data point.

Response
000
001
010
011
100
101
110
111

C2
C2
C2
C2
0

C3
C3
C3

~
C3
C3
C3
C3

C2
C2
C2
C2

Cl
Cl
Cl
Cl
0

Cl
Cl

Cl
Cl
0

Notes:
1. C3 is the rightmost coefficient, Cl is the leftmost.
2. FT 1 is relevant only if SUM IN is used. When multiple chips are
cascaded, FT 1 = LOW places a zero stage between their concatenated
impulse responses.

Building longer Filters
To build a filter of more than three non -zero stages, merely
concatenate a series of TMC2243s. The coefficient inputs may
be connected to the data bus, a separate common coefficient
bus, or separate buses, depending on system architecture,
memory and bus resources, and coefficient updating
requirements. The data inputs are connected to a common bus.
If the first feedthrough register is used land a zero stage is
not desired therel, an external register should be inserted in
the data input path for proper timing IFigure 91.
The 16-bit Sum-Out port of each TMC2243 is connected to
the Sum -In port of the next TMC2243 in the chain; the filter
output is the Sum -Out port of the last TMC2243. Since the
6 LSBs of each TMC2243's accumulation pipeline are not

output, each TMC2243 incorporates a r.ounding increment of 1
into the sixth bit, to minimize bias.
When TMC2243s are cascaded in this fashion, the minimum
permissible clock period is the sum of the output delay and
the Sum-In port's input setup time. When the Input Registers
are enabled Ithat is, FT 1 ~ LOWI, full 20MHz performance can
be obtained.
All data and coefficient inputs and outputs are two's
complement representation, whose relative scaling is presented
in the Data Formats table, Figure 1. Although the data values
are shown in fractional format, the user can arbitrarily rescale
them, as long as consistency is maintained.

Figure 9. Basic Diagram for Stacking the TMC2243 for High-Speed Operation
(no zero tap desired between each TMC2243. all FT 1 = lOW)
,..-

,'"
FROM
SYSTEM
BUS

CI

TMC2243

>------

SI

fCI

"+01

ClK

~

~

"

"'"

-

r--

TMC2243

CI

.... 01

/\

so

SI

TMC2243

TO
ADOITIONAl
STAGES

"+ 01
/\

so

SI

/\

SO

TO All REGISTERS

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-121

TMC2243
Ordering Information
Product
Number

Temperature Range

Screening

Package

Package
Marking

TMC2243G8C
TMC2243G8V

STD-TA=O°C to 70°C
EXT-TC= -55°C to 125°C

Commercial
Mll-STD-883

68 Pin Grid Array
68 Pin Grid Array

2243G8C
2243G8V

TMC2243H8C

STD-TA=O°C to 70°C

Commercial

69 Pin Plastic Pin Grid Array

2243H8C

40002174 Rev 0 8193

2-122

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2246
TMC2246
CMOS Image Filter
11 x 10 Bit, 40 MHz

Description
The TMC2246 is a video speed The TMC2246 is a video
speed convolutional array composed of four 11 x 10 bit
registered multipliers followed by a summer and an
accumulator. All eight multiplier inputs are accessible to
the user and may be updated every clock cycle with
integer or fractional two's complement data. A pipelined
architecture, fully registered input and output ports, and
asynchronous three-state output enable control simplify
the design of complex systems.
The data or coefficient inputs to the multipliers may be
held over multiple clock cycles, providing storage for
mixing and filtering coefficients. The 25-bit accumulator
path of the TMC2246 allows two bits of cumulative word
growth which may be internally rounded to 16 bits.
Output data are updated very 25 ns clock cycle, and
may be held under user control. All data inputs, outputs,
and controls are TIL compatible and are registered on
the rising edge of clock, except the three-state output
enable.
The TMC2246 is uniquely suited to performing pixel
interpolation in image manipulation and filtering
applications. As a companion to the Raytheon
Semiconductor TMC2301 Image Resampling
Sequencer, the TMC2246 Image Filter can execute a
bilinear interpolation of an image (4-pixel kernels) at
real-time video rates. Larger kernels or other more
complex functions can be realized with no loss in
performance by utilizing multiple devices.
With unrestricted access to all data and coefficient input
ports, the TMC2246 offers considerable flexibility in
applications performing digital filtering, adaptive FIR
filters, mixers, and other similar systems requiring highspeed processing.

For More Information call 1-800-722-7074.

Fabricated USing Raytheon Semiconductor's proprietary
OMICRON-CTM one-micron CMOS process, the
TMC2246 operates at a guaranteed clock rate of 40
MHz over the full temperature and supply voltage
ranges, and is available in a 120-pin plastic pin grid
array.

Features
•
•
•
•
•
•
•
•
•
•

40 MHz data and coefficient input and computation
rate
Four 11 x 10 bit multipliers with individual data and
coefficient inputs and 25-bit accumulator
User-selectable fractional or integer two's
complement data formats
Input and output data latches, with userconfigurable enables
User-selectable 16-bit rounded output
Internal 1/2 LSB rounding
Fully registered, pipelined architecture
Low power consumption CMOS process
Single +5V supply
Available in 120-pin plastic grid array

Applications
•
•
•
•
•
•

Fast pixel interpolation
Fast image manipulation
Image mixing and keying
High-performance FIR filters
Adaptive digital filters
One and two dimensional image processing

Raytheon Semiconductor

2-123

TMC2246
Functional Block Diagram
01 0_9
ENSEL

C10-l0

ENBI

020-9

030_9

C20-10 ENBZ

Clo-l0 ENB3

040-9

C40-1O ENB4

>---\------_

DEN >-------------~

Functional Description

Signal Definitions

General Information

Power

The TMC2246 Image Filter is a flexible multipliersummer array which computes the accumulated sum of
four 11 x 10 bit products, allowing word growth up to 25
bits. The inputs are user-configurable, allowing latching of
either the 10 or 11-bit input data. The data format is
user-selectable between integer or fractional two's
complement arithmetic. Total latency from input registers
to output data port is five clocks. The output data path
is 16 bits wide, providing the lower 16 bits of the
accumulator when in integer format or the upper 16 bits
of the 25-bit accumulator path when fractional two's
complement notation is selected. One-time rounding to
16 bits is performed when accumulating fractional data,
which is disabled when operating in integer format to
maintain the integrity of the least-significant bits.

VOO, GNO

2-124

The TMC2246 operates from a single + 5V
supply. All pins must be connected.

Clock
ClK

The TMC2246 operates from a single
master clock input. The rising edge of clock
strobes all enabled registers. All timing
specifications are referenced to the rising
edge of clock.

Inputs
01 9-004 9-0

01 through 04 are the 1O-bit data input
ports. The lSB is OxO. See Figure 1.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2246
Inputs (cont.)

Figure 2. Input Register Control

C11O-0C41O-0

ENB1- 4

C1 through C4 are the 11-bit coefficient
input ports. The LSB is CxO. See Figure 1.

ENSEL
1

a

Outputs
S15-0

The current 16-bit result is available at the
Sum output. The LSB is SO. See Figure 1.

Controls
FSEL

ENSEL

ENB1ENB4

Data input during the current clock is
assumed to be in fractional two's complement format, rounding to 16 bits is performed as determined by the accumulator control ACC, and the upper 16 bits of
the accumulator are output when the
registered Format Select input is LOW.
When FSEL is HIGH, two's complement
integer format is assumed, and the lower
16 bits of the accumulator are presented at
the output. No rounding is performed when
operating in integer mode. See Figure 1
and the Applications Discussion.
The registered Enable Select determines
whether the data or the coefficient input
registers may be held on the next rising
edge of clock, in conjunction with the
individual input enables ENB1- ENB4. See
Figure 2.
When ENBi (i = 1, 2, 3, or 41 is LOW,
registers Ci and Di are both strobed by the
next rising edge of CLK. When ENBi is
HIGH and ENSEL is LOW, Di is strobed, but
Ci is held. When ENBi and ENSEL are both
HIGH, Di is held and Ci is strobed. See
Figure 2. Thus, either or both input
registers to each multiplier are updated on
each clock cycle.

For More Information call 1-800-722-7074.

x

Input Register Held
Data i
Coefficient i
None

Where X denotes a "Don't Care" condition. Any register
not explicitly held is updated on the next rising edge of
clock.
ACC

When the registered Accumulator control is
LOW, no internal accumulation will be
performed on the data input during the
current clock, effectively clearing the prior
accumulated sum. If operating in fractional
two's complement format (FSEL= LOW!,
one-half LSB rounding to 16 bits is
performed on the result. This allows the
user to perform summations without
propagating roundoff errors. When ACC is
HIGH, the internal accumulator adds the
emerging product to the sum of previous
products, without performing additional
rounding.

OCEN

The output of the accumulator is latched
into the output register on the next clock
when the registered Clock Enable is LOW.
When OCEN is HIGH the contents of the
output register remain unchanged, however
accumulation will continue internally if ACC
remains HIGH.

OEN

Data currently in the output registers is
available at the output bus S15-0 when
the asynchronous Output Enable is LOW.
When OEN is HIGH, the outputs are in the
high-impedance state.

Raytheon Semiconductor

2-125

TMC2246
Figure 1. Data Formats
Fractional Two's Complement Format (FSEL =LOW)
10

115 114 113 112 111

1_26 1 25

6

5

4

3

2

1

_2° .2- 1 2-2

2-3

2- 4

2-5

2-6

2-7

2- 8

°
2-9

2- 3

2-4

2-5

2-6

2- 7

2- 8

2-9

COEFFICIENT (C1-4)

2- 3

2-4

2-5

2- 6

2- 7

2- 8

2-9

SUM

27

26

25

24

23

22

21

2°

DATA (01-4)

2°

COEFFICIENT (C1-4)

2°

SUM

8

9

7

_21

2°

.2-1 2-2

21

2°

.2-1 2-2

I 24 I 23 I 22

BIT
DATA (01-4)

Integer Two's Complement Format (FSEL = HIGH)
_29 28
_210 29

28

27

26

25

24

23

22

21

210

28

27

26

25

24

23

22

21

1_2151214121312121211
Note:

29

A minus sign indicates the sign bit.

Package Interconnections
Signal
Type

Signal
Name

Power

VOO
GNO

Supply Voltage
Ground

F3. H3. L7. CB
E3. G3. J3. L6. H11. C7

13. 21. 50. 112
9. 17. 25, 46, 79, 116

Clock

CLK

System Clock

C3

2

Inputs

01 9-0

01 Input

02 9_0

02 Input

03 9_0

03 Input

049_0

04 Input

CllO_0

Cl Input

C21O-0

C2 Input

C31O-0

C3 Input

C41O-0

C4 Input

Ml, K3, L2. Nl, L3.
M2, N2, l4, M3, N3
J12, K13, Jll, K12, 113,
112, Kll, M13, M12, 111
J13, H12, H13, G12, GIl,
G13, F13, F12, Fll, E13
B4, C5, A4, B5, A5,
C6, B6, A6, A7, B7
M4, L5, N4, M5, N5, M6,
N6. M7, N7, N8, M8
N13, Mll, llO, N12, Nll,
Ml0, L9, Nl0, M9, N9, L8
E12, 013, Ell, 012, C13. B13,
011, C12, A13, Cl1, B12
A8, B8, A9, B9, A10, C9,
Bl0, All, Bll, Cl0. A12

28, 29, 30, 31, 35,
36, 37, 38, 39, 40
77, 76, 75, 74, 73,
72, 71, 70, 69, 68
78, 80, 81, 82, 83,
84, 85, 86, 87, 88
125, 124, 123, 122, 121,
120, 119, 118, 117, 115
41, 42, 43, 44, 45, 47,
48, 49, 51, 52, 53
64, 63, 62, 61, 60, 59,
58, 57, 56, 55, 54
89, 90, 91, 92, 93, 94,
95, 96, 97, 101, 102
114, 113, 111, 110, 109, 108,
107, 106, 105, 104, 103

Outputs

S15-0

Sum Output

Cl, 02, 01, E2, El, F2, Fl, G2,
Gl, HI, H2. Jl, J2, Kl, K2, II

7, 8, 10, 11, 12, 14, 15, 16, 18,
19, 20, 22, 23, 24, 26, 27

Controls

FSEL
ENSEL
ENB1-ENB4
ACC
OCEN
DEN

Format Select
Enable Select
Input Enables
Accumulate
Output Register Enable
Output Enable

B2
Al
C4, A2, A3, B3
Bl
03
C2

3
130
128, 127, 126, 129
4
5
6

Not Connected

04 (Index Pin)

1. 32, 33, 34, 65, 66, 67,
98, 99, 100, 131, 132

No Connect

2-126

Function

H5 Package Pins

Raytheon Semiconductor

L5 Package Pins

For More Infonnaticn call 1-800-722-7074.

TMC2246
Figure 3. Timing Diagram

ClK

0Ig_0-04g_0

I
--l

XX
---1

C1l0-0- C41O-0

XX

OA

~IH

XXXXX

XX

XX

CB

)¢(

f----IS
CA

XXXXX

II I

CONTROLS 1

DB

XXXXX

--l=
=:J<

)¢(

1\ I
S15_0 1

I
Notes:

1.

Except OEN.

2.

Assumes OEN ~ LOW.

Figure 4. Equivalent Input Circuit

~t
SA

I

I

~
I

Figure 5. Equivalent Output Circuit
VOO
n SUBSTRATE

01

CONTROl~~WI,;-~~"

INPUT

",-~~-o

~

OUTPUT

02
p WELL

':" GNO

':" GNO

Figure 6. Threshold levels for Three-State Measurement

lOIS

0.5V

THREE-STATE
OUTPUTS

HIGH IMPEDANCE
0.5V

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-127

TMC2246
Absolute maximum ratings (beyond which the device may be damagedl 1
Supply Voltage ........................................................................................................................................................................................ - 0.5 to + 7.0V
Input Voltage ................................................................................................................................................................................. - 0.5 to (VOO + 0.5)V
Output

Applied voltage Z ................................................................................................................................................... - 0.5 to (VOO + 0.5)V
Forced current 3.4 ............................................................................................................................................................ - 6.0 to 6.0mA
Short-circuit duration (single output in HIGH state to ground) ......................................................................................... 1 Second
Temperature

Operating, case .............................................................................................................................................................. -60 to + 130°C
junction ........................................................................................................................................................................... 175°C
Lead, soldering (10 seconds) ......................................................................................................................................................... 300°C
Storage ............................................................................................................................................................................ - 65 to + 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range. and measured with respect to GNO.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

Operating conditions
Temperature Range
Parameter

Min

VOD

Supply Voltage

4.75

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

2.0

IOL
IOH

Output Current, Logic LOW
Output Current, Logic HIGH

tCY

Cycle Time

tpWL

2-128

Test Conditions

Clock Pulse Width, LOW

tpWH

Clock Pulse Width, HIGH

ts

Input Setup Time

tH

Input Hold Time

TA
TC

Ambient Temperature, Still Air
Case Temperature

Standard
Nom
5.0

Max

Min

5.25

4.5

0.8

VOO=Min
TMC2246
TMC2246-1
VOO=Min
TMC2246
TMC2246-1

5.0

Units

5.5

V

0.8

V
V

2.0
4.0
-2.0

VOO=Min
TMC2246
TMC2246-1

Extended
Nom
Max

4.0
-2.0

rnA
rnA

33
25

ns
ns

15
10
10

ns
ns
ns

10
8
2

ns
ns
ns

0

70
-55

Raytheon Semiconductor

125

°c
°c

For Morelnfonnation call 1-800-722-7074.

TMC2246
Electrical characteristics within specified operating conditions

1

Temperature Range
Parameter
100Q Supply Current, Quiescent
100U Supply Current, Unloaded
Input Current, Logic LOW

VOO=Max, VIN=OV

Input Current, Logic HIGH

VOO=Max, VIN=VOO

VOL
VOH

Output Voltage, Logic LOW
Output Voltage, Logic HIGH

VOO=Min, IOL =Max
VOO = Min, IOH = Max

IOZL Hi-Z Output Leakage Current, Output LOW
IOZH Hi-Z Output Leakage Current, Output HIGH
Short-Circuit Output
lOS

Note:

Input Capacitance
Output Capacitance

Extended
Min
Max

6
100

Voo=Max, VIN=OV
Voo=Max, OEN=5V, f=30MHz

IlL
IIH

CI
Co

Standard
Min
Max

Test Conditions

-10

mA
mA
-10

10

10

0.4
2.4

0.4
2.4

-40

VOO=Max, VIN=OV

Units

-40

flA
flA
V
V

VOO=Max, VIN=VOO
VOO = Max, Output HIGH, one pin to
ground, one second duration max.

40
60

40
60

flA
flA
mA

TA=25°C, f=lMHz
TA=25°C, f=lMHz

10
10

10
10

pF
pF

1. Actual test conditions may vary from those shown. but operation is guaranteed as specified.

Switching characteristics within specified operating conditions
Temperature Range
Parameter
to

Test Conditions

Output Oelay

Standard
Min
Max

VOO = Min, CLOAO = 25pF
TMC2246

15

TMC2246-1
tHO

Output Hold Time

tENA
tDiS

Three-State Output Enable Delay

Notes:

Three-State Output Oisable Delay

VOO=Max, CLOAO=25pF
1
1

VOO=Min, CLOAO=25pF
VOO=Min, CLOAO=25pF

13
5
15
20

Extended 2
Min
Max

Units
ns
ns
ns
ns
ns

1. All transitions are measured at a 1.5V level except for tOIS and tENA2. Consult factory for extended temperature specifications.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-129

TMC2246
Applications Discussion
Demonstration of Operation
The versatile input clock enables and unrestricted data
and coefficient inputs provided on the TMC2246 allow
considerable flexibility in numerous image and signal
processing architectures. Figure 7 shows a typical
sequence of operations which clarifies the inherent clock
latencies of the device and illustrates fixed coefficient

storage, product accumulation, and device reconfiguration prior to beginning a new accumulation. This
assumes that the device is set to fractional two's
complement mode IFSEL = LOW!. with OCEN = LOW,
OEN = LOW, and the input registers configured to hold
coefficients only IENSEL= LOW). X= "don't care:'

Figure 7. Typical TMC2246 Operation Sequence
ClK

01

C1 ENB1 02

C2 ENB2 03

0

-

-

0

-

1

Dll1)

Cl(1)

1

0211) C211)

2

0112)
01(3)

X

0

Cl(3)

0

0212) X
02(3) C2(3)

0

3

0

0312)
03(3)

4

01(4)

Cl(4)

-

02(4) C2(41

-

03(4) C3(4)

-

0
1

-

C3 ENB3 04
-

0311) C311)

X
X

-

C4 ENB4 ACC
-

0
1

04(1) C411)

1

0412)

0

04131 X
0414) C4(4)

-

x

Sum

0

-

-

1

0
1

-

1
0

1

-

0

5

S(5) = 01(1)Cll1) + 0211)C2(1)

6

S(6) = S(5) + 01 (2)Cl (1) + 02(2)C2(1 1

7

S(7) = S(6) + 01(3)Cl(3) + 02(3)C2(3)

8

S(8) = 01 (4)Cl (4) + 02(4)C2(4)

+ 03(1 )C3(1) + 04(1 IC4(1) + 2-10
+ 03(2)C3(1) + 04(2)C4(1)
+ 03(3)C3(1) + 04(3)C4(1 1
+ 03(4)C3(4) + 0414)C414) + 2- 10

Notice in this example, operating in fractional two's
complement mode, that rounding is imposed on the first

cycle only of an accumulation. This avoids the propagation of accumulated roundoff errors.

Using the TMC2246 for Pixel Interpolation
As a companion product to the TMC2301 Image
Resampling Sequencer, the TMC2246 offers an excellent
tool for performing high-speed pixel interpolation and
image filtering. Any pixel resampling operation with
multiple-pixel kernels must utilize some parallelprocessing technique, such as memory banding, in order
to maintain high-speed image throughput rates. Memory
Banding utilizes adders to generate parallel offset
addresses, allowing the user to access multiple pixel

2-130

locations simultaneously. Using such techniques, one
TMC2246 can perform bilinear interpolation (four-pixel
kernel) with no loss in system performance. Larger
kernels can be realized in similar systems with additional
TMC2246s. See TRW Application Brief AB-4,
"Performing Bilinear Interpolation Using the
TMC2301". Figure 8 illustrates a basic pixel interpolation application.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2246
Figure 8. Bilinear Interpolation Using the TMC2246

TMC2301

TMC2301

-

CAX

CAY

U

X

v

Y

\.

~

-0

ADDR
BANDED
SOURCE
IMAGE
RAM

KY

X. Y
DDUT

t

t

ADDR

ADDR

x+

t t t t

X. Y + 1

1. Y

ADDR
X + 1,
Y+ 1
DDUT

DOUT

DDUT

ADDRESS
OFFSET
ADDERS

BANDED
INTERPOLATION
COEFFICIENT
ROM

I

~
01 Cl

02 C2
03 C3
TMC2246

I

t
04 C4

S15-0
INTERPOLATED PIXEL DATA

TMC2011
PIPELINE
DELAY
REGISTER

>
>
t>
I>

r>

DIN
TARGET
IMAGE
RAM

I

U, V ADDRESS
ADDR
DDUT

t

TO DISPLAY

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-131

TMC2246
TMC2246 Applications in Digital Filtering
Unrestricted access to all input ports of the TMC2246
allows the user considerable flexiblity in realizing
numerous digital filter architectures. Figure 9 illustrates
how the device may be utilized as a flexible high-speed
FIR Filter with the ability to modify all of the filter
coefficients dynamically or to store a fixed set if desired.

Longer filters, with more taps, are realized by including
an external adder (such as the common 74381 typel to
cascade multiple TMC2246s. Alternatively, two additional
taps and a cascading adder are available in the TRW
TMC2249 Digital Mixer.

Figure 9. Utilization of the TMC2246 for FIR Filtering
DAn~~----~----~-----'~--~~----~----~-----1~----

CDEFF

--tr--......+--.......-+--~-+---1......-jr---<~+---.......-+--.....-+-----1~

SELECT

-lh_+-+-.....+-+-....-+--+-1--f-lI--4..-f-+-.....+-+....-+-+-1......-j1--

TMC2246
S15-0

TMC2246
S15-0

FIlTER OUTPUT

Pin Assignments - 120 Pin Plastic Pin Grid Array, H5 Package
Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

C3
B2
Bl
03
C2
Cl
02
E3
01
E2
El
F3
F2
Fl
G2

CLK
FSEL
ACC
OCEN
DEN

G3
Gl
HI
H2
H3
Jl
J2
Kl

GNO

L3
M2
N2
L4
M3
N3
M4

01 5
01 4

L7
N7

02 0
02 1
02 2
02 3
02 4

03 5
03 4
03 3
03 2
03 1

Cll

C31
C30
C40
C41

C7

GNO

N8
M8
L8

111
M12
M13
Kll
112

GIl

01 3
01 2
011

VOO
C12
Cl 1

A7
A6
B6

04 1
04 2
04 3
04 4

01 0
C1w
C19
C18
C17

N9
M9
Nl0
L9
M1D
Nll
N12
l10
Mll
N13

l13
K12

02 5
02 6

Jll
K13
J12

02 7
02 8
02 9
D39
GNO
03 8

E13
E12
013
Ell
012
C13
B13
011
C12
A13

2-132

S15
S14
GNO
S13
S12
Sll
VOO
SlO
S9
S8

J3
K2
11
Ml
K3
L2
Nl

S7
S6
S5
VOO
S4
S3
S2
GNO
Sl

L5
N4
M5

So
01 9
01 8
01 7
01 6

N5
L6
M6
N6
M7

C16
GNO
C15
C14
C13

C10
C20
C2 1
C22
C23
C24
C25
C26
C27
C28
C29
C210

J13
Hll
H12
H13
G12

03 7
03 6

Raytheon Semiconductor

G13
F13
F12
Fl1

03 0
C3 10
C39
C38
C3 7
C36
C35
C34
C33
C32

B12
A12
Cl0
Bl1
All
Bl0
C9
Al0
B9
A9
CS
B8
A8
B7

C42
C43
C44
C45
C46
C47
C4S
VOO
C49
C410
04 0

C6
A5
B5

A4
C5
B4
A3
A2
C4
B3
Al

04 5
04 6
04 7
D48
04 9
ENB3
ENB2
ENBI
ENB4
ENSEL

For More Information call 1-800-722-7074.

TMC2246
Pin Assignments - 132 Leaded CERQUAD, L5 Package
Name

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Pin

Name

Pin

Name

Pin

Name

Pin

Name

NC

23
24

S3
S2
GND

45
46
47
48
49

C16
GND

67
68
69
70
71

NC

ClK
FSEl
ACC
DCENB
DENB

89
90
91
92

50
51
52

VDD
C12
Cll
Cl0

C310
C39
C38
C37
C36
C35
C34
C33
C32
NC
NC
NC

S15
S14
GND
S13
S12
Sl1
VDD
SlO
S9
S8
GND

15
16

17
18
19
20
21
22

25
26
27
28
29
30
31
32
33
34
35

S6
S5

36
37
38
39
40
41
42

VDD
S4

43
44

S7

Sl
So
D19
D18
D17
D16
NC
NC
NC
D15
D14

53
54
55

C20
C21
C22

56
57

Dlo

58
59
60
61
62

CllO
C19
C18
C17

63
64
65
66

D13
D12
01 1

C15
C14
C13

C23
C24
C25
C26
C27
C28
C29
C210
NC
NC

72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88

D20
02 1
D22
D23
D24
D25
D26
D27

93
94
95
96
97
98
99
100
101
102

D28
D29
D39
GND
D38
D37
D36
D35
D34
03 3
D32
03 1
D30

C31

103
104
105
106
107
108

C30
C40
C41
C42
C43
C44
C45

109
110

C46
C47

Pin

Name

111

C48

112

VDD
C49
C410
D40
GND

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132

D41
D42
D43
D44
D45
D46
04 7
D48
D49
EN3B
EN2B
EN1B
EN4B
ENSEl
NC
NC

100

© © © © © © © © © © © © ©
© © © © © © © © © © © © ©
© © © © © © © © © © © © ©
10 © © ©
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~
© © ©
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TOP VIEW
© © ©
CAVITY UP
© © ©
©©©
©©©
13
12
11

© © © ~Key
./ © © ©
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©©©
©©©©©©©©©©©©©
©©©©©©©©©©©©©
©©©©©©©©©©©©©

33

ABCDEFGHJKLMN
21041A

120 Pin Plastic Pin Grid Array - H5 Package

For More Information call 1-800-722-7074.

34

66

21062A

132 Leaded CERQUAD - L5 Package

Raytheon Semiconductor

2-133

TMC2246
Ordering Information
Product
Number

Temperature Range

Screening

Package

Package
Marking

TMC2246H5C
TMC2246H5Cl

STD-TA =O°C to 70°C
STD-TA=O°C to 70°C

Commercial
Commercial

120 Pin Plastic Pin Grid Array
120 Pin Plastic Pin Grid Array

2246H5C
2246H5Cl

TMC2246L5V
TMC2246L5Vl

EXT-TC= -55°C to 125°C
EXT-TC= -55°C to 125°C

MIL-STD-883
MIL-STD-883

132 Leaded CEROUAD
132 Leaded CEROUAD

2246L5V
2246L5Vl

40G06126 RevE 8/93

2-134

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2249
TMC2249
CMOS Digital Mixer
12 x 12 Bit, 30 MHz

Description
The TMC2249 is a high-speed digital arithmetic circuit
consisting of two 12-bit multipliers, an adder and a
cascadeable accumulator. All four multiplier inputs are
accessible to the user, and each includes a userprogrammable pipeline delay of up to 16 clocks in
length. The 24-bit adder/subtractor is followed by an
accumulator and 16-bit input port which allows the user
to cascade multiple TMC2249s. A new 16-bit
accumulated output is available every clock, up to the
maximum rate of 30 MHz. All inputs and outputs are
registered except the three-state output enable, and all
are TTL compatible.
The TMC2249 utilizes a pipe lined, bus-oriented structure
offering Significant flexibility. Input register clock enables
and programmable input data pipeline delays on each
port offer an adaptable input structure for high-speed
digital systems. Following the multipliers, the user may
perform addition or subtraction of either product,
arithmetic rounding to 16-bits, and accumulation and
summation of products with a cascading input. The
output port allows access to all 24 bits of the internal
accumulator by switching between overlapping least and
most-significant 16-bit words, and a three-state output
enable simplifies a connection to an external system
bus.
All programmable features are utilized on a clock-byclock basis, with internal data and control pipeline
registers provided to maintain synchronous operation
between incoming data and all available functions within
the device.
The TMC2249 has numerous applications in digital
processing algorithms, from executing simple image
mixing and switching, to performing complex arithmetic

For More Information caJI1-800-722-7074.

functions and complex waveform synthesis. FIR filters,
digital quadrature mixers and modulators, and vector
arithmetic functions may also be implemented with this
device.
Fabricated using a one-micron CMOS process, the
TMC2249 operates at a guaranteed clock rate of 30
MHz over the standard commercial temperature and
supply voltage ranges, and is available in a low-cost 120
pin plastic pin grid array.

Features
•
•
•
•
•
•
•
•
•
•

30 MHz input and computation rate
Two 12-bit multipliers with spearate data and
coefficient inputs
Independent, user-selectable pipleline delays of 1 to
16 clocks on all inputs ports
Separate 16-bit input port allows cascading or
addition of a constant
User-selectable rounded output
Internal 1/2 LSB rounding og products
Fully registered, pipelined architecture
Low power consumption CMOS process
Single +5V power supply
Available in 120-pin plastiC grid array

Applications
•
•
•
•
•
•

Video switching
Image mixing
Digital signal modulation
Complex frequency synthesis
Digital filtering
Complex arithmetic functions

Raytheon Semiconductor

2-135

TMC2249
Functional Block Diagram

8, ...

···
·
·····

D~~~--~:------------------------~~:-----------~

···
···
·
···

~---~

~'9

-----------------------------------------------~

2-136

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2249
Functional Description

accumulator by swapping overlapping registers. The
output bus has an asynchronous high-impedance enable,
to simplify interfacing to complex systems.

General Information
The TMC2249 performs the summation of products
described by the formula:
SIN + 61 = AIN - ADELl- BIN - BDELI-I-l NEG 11NII
+ CIN - COELI- DIN - DDELI-I-l NEG 21NII + CASIN + 3-FTI

where ADEl through DDEl range from 1 to 16 pipe
delays. All inputs and controls utilize pipeline delay
registers to maintain synchronicity with the data input
during that clock, except when the Cascade data input is
routed directly to the accumulator by use of the
Feedthrough control. One-half lSB rounding to 16 bits
may be performed on the sum of products while
summing with the cascade input data. The user may
access either the upper or lower 16 bits of the 24-bit

For More Information call 1-800-722-7074.

Signal Definitions
Power
VOD, GNO

The TMC2249 operates from a single + 5V
supply. All power and ground pins must be
connected.

Clock
ClK

The TMC2249 operates from a single
master clock input. The rising edge of clock
strobes all enabled registers. All timing
specifications are referenced to the rising
edge of clock.

Raytheon Semiconductor

2-137

TMC2249
Inputs

A11-o011-0

CAS15-o

A through 0 are the four 12-bit registered data input ports. AD-DO are the LSBs.
See Table 1. Data presented to the input
ports is clocked in to the top of the
16-stage delay pipeline on the next clock
when enabled, "pushing" data down the
register stack.

RND

When the rounding control is HIGH, the
sum of products resulting from data input
during that clock is rounded to 16 bits.
Rounding is performed only during the
first cycle of each accumulation sequence,
to avoid the accumulation of roundoff
errors.

FT

When the Feedthrough control is HIGH, the
pipeline delay through the cascade data
path is minimized to simplify the cascading
of multiple devices. When FT is LOW and
ADEL through DDEL are all set to 0, the
data inputs are aligned, such that
Sin + 6) = CASln) + Aln)Bln) + Cln)Dln).
See Table 2.

CAS is the 16-bit Cascade data input port.
CASo is the LSB. See Table 1.

Outputs

S15-o

indicate the operation to be performed on
data input during the current clock, when
the length controls ADEL - DDEL are set to
zero.

The current 16-bit result is available at the
Sum output. The LSB is SO. The output
may be the most or least significant 16 bits
of the current accumulator output, as
determined by SWAP. So is the LSB. See
Table 1.

Controls

ENA-END

Input data presented to port i11-o Ii = A, B,
C, or D) are latched into delay pipeline i,
and data already in pipeline i advance by
one register position, on each rising edge
of CLK for which ENi is LOW. When ENi is
HIGH, the data in pipeline i do not move
and the value at the input port i will be
lost before it reaches the multiplier.
ADEL through DDEL are the four-bit
registered input data pipe delay select word
inputs. Data to be presented to the multipliers is selected from one of sixteen stages
in the input data delay pipe registers, as
indicated by the delay select word
presented to the respective input port
during that clock. The minimum delay is
one clock Iselect word = 0000), and the
maximum delay is 16 clocks Iselect
word = 1111). Following powerup these
values are indeterminate and must be
initialized by the user.

NEG1, NEG2 The products of the multipliers are negated,
causing a subtraction to be performed
during the internal summation of products,
when the Negate controls are HIGH. NEG1
negates the product A x B, while NEG2 acts
on the output of the multiplier which
generates the product Cx D. These controls
2-138

Data presented at the cascade data input
port are latched and accumulated internally
when the input enable CASEN dUring that
clock is Law. When CASEN is HIGH, the
cascade input port is ignored.
ACC

When the registered Accumulator control
is LOW, no internal accumulation will be
performed on the data input during the
current clock, effectively clearing the prior
accumulated sum. When ACC is HIGH,
the internal accumulator adds the emerging
product to the sum of previous products.
The user may access both the most and
least-significant 16 bits of the 24-bit
accumulator by utilizing SWAP. Normal
operation of the device, with SWAP = HIGH,
outputs the most significant word. Setting
SWAP = LOW puts a double-register
structure into "toggle" mode, allowing the
user to examine the LSW on alternate
clocks. New output data will not be clocked
into the output registers until SWAP returns
HIGH.
Data currently in the output registers is
available at the output bus S15-0 when the
asynchronous Output Enable is Law. When
OE is HIGH, the outputs are in the highimpedance state.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2249
Table 1. Data Formats and Bit Weighting

l- 22~

222

10

9

8

7

_211 210

29

28

219

217

216

11

115 114 113 112

J

221 1220

218

6

5

27

26

25

215

214

213

3

2

1

0

BIT

24

23

22

21

20

DATA INPUT (All-0-Dll-01

212

211

210

29

28

CASCADE INPUT (CAS15_01

4

SUM (S15-01

r--r__r--r__r--r__r--r--'--'--'--.--'--.--'--.--,
215

214

213

LSW

- 223 222

221

MSW

~~--r-~--r--+--r--+--+--+--+--+--+--+--+--+--~
~~

Note:

__

~~

__

~-L

__

~-L

__

~~

__

~~

__

~~

__

~~

__

~

1. A minus sign indicates the sign bit

Package Interconnections

•

Signal
Type

Signal
Name

Power

VOO
GNO

Supply Voltage
Ground

F3, H3, L7, C8
E3, G3, J3, L6, H11, C7

13,21, 50, 112
9, 17, 25, 46, 79, 116

Clock

CLK

System Clock

C3

2

Inputs

A11-0

A Input

B11-0

B Input

C11 -0

C Input

0 11 -0

o Input

AOEL3_0
BOEL3_0
COEL3_0
00EL 3_0
CAS ,5 _0

A Oelay
B Oelay
C Oelay
o Oelay
Cascade Input

N8, M8, L8, N9, M9, Nl0,
L9, Ml0, N", N12, L10, Mll
N7, M7, N6, M6, N5, M5,
N4, L5, M4, N3, M3, L4
A9, B9, AlO, C9, Bl0, A11,
B", ClO, A12, B12, C11, A13
B8, A8, B7, A7, A6, B6,
C6, A5, B5, A4, C5, B4
L11, M12, M13, Kll
M2, L3, Nl, L2
0", B13, C13, 012
A2, C4, B3, Al
L13, K12, J11, K13, J12, J13,
H12, H13, G12, G", G13, F13,
F12, F11, E13, E12

52, 53, 54, 55, 56, 57,
58, 59, 60, 61, 62, 63
51, 49, 48, 47, 45, 44,
43, 42, 41, 40, 39, 38
111, 110, 109, 108, 107, 106,
105, 104, 103, 102, 101, 100
113, 114, 115, 117, 118, 119,
120, 121, 122, 123, 124, 125
68, 69, 70, 71
36, 35, 31, 30
95, 94, 93, 92
127, 128, 129, 130
73, 74, 75, 76, 77, 78, 80, 81,
82, 83, 84, 85, 86, 87, 88, 89

Outputs

S,5-0

Sum Output

Cl, 02, 01, E2, El, F2, Fl, G2,
Gl, Hl, H2, Jl, J2, Kl, K2, L1

7,8, 10, 11, 12, 14, 15, 16,
18, 19, 20, 22, 23, 24, 26, 27

Controls

ENA-ENO
NEG1, NEG2
RNO
FT
CASEN
ACC
SWAP
DE

Input Enables
Negate
Round
Feedthrough
Cascade Enable
Accumulate
Swap Output Words
Output Enable

N13, N2, C12, A3
Bl,03
C2
Ell
013
B2
K3
Ml

64, 37, 96, 126
4, 5
6
91
90
3
29
28

No Connect

NC

None

L12

" 32, 33, 34, 65, 66, 67,
72, 98, 99, 100, 131, 132

Index Pin

04

For More Information call 1-800-722-7074.

Function

H5 Package Pins

Raytheon Semiconductor

L5 Package Pins

2-139

TMC2249
Figure 1. Timing Diagram

I
-H'H-XX XXX)(

ClK

AI1-0-011-0

I

OA

OB

I I I

CONTROLS 1

S15-0

XX

2----j'S

Notes:

r

XXX><

XX'
XX
=f=-SA-";""'"

11----

1. Except DE.
Z. Assumes DE = lOW, and ADEl- DDEl set to O.

Figure 2. Equivalent Input Circuit

Figure 3. Equivalent Output Circuit

n SUBSTRATE

n SUBSTRATE

01

p

p+

p+

CONTROL c>-4I--'WII---4I,........
INPUT

t--~~-o

lKQ

D3

01

OUTPUT

n+

02

02

pWElL

p WEll

Figure 4. Threshold Levels for Three-State Measurement

DE

'DIS

0.. 5V

THREE-STATE
OUTPUTS

HIGH IMPEDANCE
O.5V

2-140

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2249
Absolute maximum ratings Ibeyond which the device may be damaged) 1
Supply Voltage ........................................................................................................................................................................................ - 0.5 to + 7.0V
Input Voltage ................................................................................................................................................................................. - 0.5 to (Voo + 0.51V
Output
Applied voltage 2 ................................................................................................................................................... - 0.5 to (VOO + 0.51V
Forced current 3.4 ............................................................................................................................................................ - 6.0 to 6.0mA
Short-circuit duration (single output in HIGH state to groundl ......................................................................................... 1 Second

Temperature
Operating, case .............................................................................................................................................................. - 60 to + 130°C
junction ........................................................................................................................................................................... 175°C
Lead, soldering (10 secondsl ......................................................................................................................................................... 300°C
Storage ............................................................................................................................................................................ - 65 to + 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range. and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

Operating conditions
Temperature Range
Min

Standard
Nom

Voo

Supply Voltage

4.75

5.0

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

2.0

IOL
IOH

Output Current, Logic LOW
Output Current, Logic HIGH

tCY

Cycle Time

Parameter

Test Conditions

5.25

Min
4.5

0.8

Extended 1
Nom
Max
5.0

Units

5.5

V

0.8

V
V

2.0
4.0
-2.0

4.0
-2.0

mA
mA

VOO=Min
TMC2249
TMC2249-1

40
33

ns
ns

VOO=Min
VOO=Min

15
10

ns
ns
ns
ns

tpWL
tpWH

Clock Pulse Width, LOW
Clock Pulse Width, HIGH

ts
tH

Input Setup Time
Input Hold Time

8
4

TA
TC

Ambient Temperature, Still Air
Case Temperature

0

Note:

1. Consult factory for extended temperature specifications.

For More Information call 1-800-722-7074.

Max

70
-55

Raytheon Semiconductor

125

°c
°C

2-141

TMC2249
DC characteristics within specified operating conditions

1

Temperature Range
Test Conditions

Parameter
IDOQ Supply Current, Quiescent
IDOU Supply Current. Unloaded

VDD=Max, DEN = 5V, f=25MHz

Input Current, Logic LOW
Input Current, Logic HIGH

VDO=Max, VIN=OV
VDO= Max, VIN=VDD

VOL
VOH

Output Voltage, Logic LOW
Output Voltage, logic HIGH

VDD=Min, IOL =Max

Co
Note:

-10

Input Capacitance
Output Capacitance

-10
10

0.4

-40

VDD=Max, VIN=OV

0.4
2.4

2.4

Units
mA
mA

10

VDD = Min, 10H = Max

10Zl Hi-Z Output leakage Current, Output LOW
IOZH Hi-Z Output leakage Current, Output HIGH
Short-Circuit Output
lOS

Extended
Min
Max

6
100

VDo=Max, VIN=OV

IlL
IIH

CI

Standard
Min
Max

-40

I"A
I"A
V
V
I"A

VDD=Max, VIN=VDD
VDD= Max, Output HIGH, one pin to
ground, one second duration max.

40
60

40
60

~

TA =25°C, f=lMHz
TA=25°C, f=lMHz

10
10

10
10

pF
pF

mA

1. Actual test conditions may vary from those shown. but operation is guaranteed as specified,

AC characteristics within specified operating conditions
Temperature Range
Parameter
tD

2-142

Test Conditions

Output Delay

Standard
Max
Min

VDD = Min, CLOAD = 25pF
TMC2249
TMC2249-1

tHO

Output Hold Time

VDD=Max, CLOAD=25pF

lENA
tDiS

Three-State Output Enable Delay 1
Three-State Output Disable Delay 1

VD D= Min, CLOAD = 25pF
VD D= Min, ClOAD = 25pF

Note:

1. All transitions are measured at a 1.5V level except for tOIS and tENA'

Raytheon Semiconductor

Extended
Min
Max

Units

17
15

ns
ns
ns

15
20

ns
ns

5

For More Information call 1-800-722-7074.

TMC2249
Applications Discussion
Basic Operation
The TMC2249 is a flexible signal and image processing
building block with numerous user -selectable functions
which expand it's usefulness. Table 2 clarifies the

operation of the device, demonstrating the various
features available to the user and the timing delays
incurred.

Table 2. TMC2249 Operation Sequence
ClK ADEL A11-0 BDEL B11-0 CDEl C11-0 DDEl D11-0 NEG1 NEG2 CA515_0 FT ACC RND SWAP
1
2
3
4

5
6
7
8
9
10
11
12
13
14

0
0
0
0
0
0
0
0
0

All}
AI2}
AI3}
AI4}
AI5}
AI6}
A(7)
A(8}
A(9)

0
0
0
0
0
0
0
0
0

Bll}
BI2}
B13)
B14)
B15)
B16)
B(7}
B(8}
BI9}

0
0
0
0
0
0
0
0
0

Cll}
Cl2}
CI3}
Cl4}
Cl5}
Cl6}
C(7}
C(8}
C(9}

0
0
0
0
0
0
0
0
0

Oil}
DI2}
013)
DI4}
015)
DI6}
0(7)
0(8)
0(9)

L
L
H
L
L
L
L
L
L

L
H
L
L
L
L
L
L
L

CASI4)

CASI8}

-

L
L

L
L

L
L
L
L

L
L
L
L

L
L
L
L
L
H

L
H
L

H
L
L

H
L
L

H
H
H
H
H
H
H
L
H

515-0

IAI1}.B(l)+C(l).D(l))ms
IA(2)·B(2} - C(2}. D(2)}ms
1- A(3)· B(3) + C(3}· D(3))ms
(A(4)· B(4) + C(4)' D(4} + CAS(4))ms
(A(5).BI5}+C(5}.D(5)+CAS(8))ms
(A(6)· B(6) + CI6). 0(6) + 27}ms
(A(7}.B(7) +C(7)·D(7}+ S(ll))ms
(S(12))ls
(AI9}·B(8) + C(7}·D(6))ms

Where H= HIGH, L= LOW. "ms" indicates most
significant output word (bits 23 - S), "Is" indicates least
significant word (bits 15 - 01. The appropriates enables
for the indicated data are assumed, otherwise '-'

indicates that port not enabled. Note that the output
data summation including A(SI- D(SI is lost, since the
output on cycle 13 is swapped to the LSW of S(121 on
cycle S.

Digital Filtering
The input structure of the TMC2249 demonstrates great
versatility when all four multiplier inputs and the programmable delay registers are utilized. Tables 3 and 4
demonstrate how a direct-form symmetric FIR filter of
up to 32 taps can be implemented. By utilizing the four
input delay registers as pipelined storage banks, the user
can store up to 32 coefficient-data word pairs, split into
alternate "even" and "odd" halves. Two taps of the
filter are calculated on each clock, and the user then
increments/decrements the delay words (ADEL - DOELl.
The sums of products are successively added to the
global sum in the internal accumulator. Once all of the

For More Information caJI1-800-722-7074.

products of the desired taps have been summed, the
resultant is available at the output. The user then
"pushes" a new time-data sample on to the appropriate
even or odd data register "stack" and reiterates the
summation. Note that the coefficient bank "pointers",
the BDEL and DDEL delay words, are alternately
incremented and decremented on successive filter passes
to maintain alignment between the incoming data
samples and their respective coefficients. The effective
filter speed is calculated by dividing the clock rate by
one-half the number of taps implemented.

Raytheon Semiconductor

2-143

TMC2249
Table 3. Using the TMC2249 to Perform FIR Filtering - Initial Data Loading
Even Data

Odd Data

Coefficient

Storage

Register Position (Hex)

A

C

B

0

0

x(31)

h(l)

x(29)

x(30)
x(28)

h(O)

1

h(2)

h(3)

2

x(27)

x(26)

h(4)

h(5)

3
4

x(25)
x(23)

x(24)
x(22)

h(6)
h(8)

h(7)
h(9)

5

x(21)

x(20)

6

x(19)

x(18)

hll0)
h(12)

hill)
h(13)

7

x(17)

x(16)

h(14)

h(15)

8

x(15)

x(14)

h(15)

h(14)

9
A
B
C
D
E
F

x(13)
x(ll)

x(12)

h(13)

h(12)

x(9)

xll0)
x(8)

hill)
h(9)

hll0)
h(8)

x(7)

x(6)

h(7)

h(6)

x(5)

x(4)

h(5)

h(4)

x(3)

x(2)

h(3)

h(2)

xll)

xlO)

h(lI

hlO)

Table 4. FIR Filtering - Operation Sequence
Cycle

Push
A

B

C

0

Push
AOEL COEL BOEL OOEL ACC ENA ENC ENB END

1

-

-

-

-

0

0

-

-

-

1

1

1

3
4

-

-

2

2

2

2

-

-

-

0
1

0

2

-

-

-

-

-

3
4

3
4

3

5
6

4

3
4

-

-

5

5

5

5

-

-

-

6

6

8

-

9

-

-

-

-

7

-

-

12
13
14

10
11

-

7

6
7

7

6
7

-

8

8

8

8

-

-

9

9

9

9

-

-

-

-

-

-

A
B

A
B

-

-

-

A
B

-

c

c

c

-

-

-

-

-

x(32)

-

-

-

-

-

-

-

-

-

-

D
E
F
0
1
2
3
4

D
E
F
0
1
2
3
4

D
E
F
F
E
D
C
B

A
B
C
D
E
F
F
E
D
C
B

15
16

-

17

-

18

-

19

-

20
21

2-144

-

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

Raytheon Semiconductor

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

Convolution Sum

Resultant
Output

x(31)· hlO) + x(30). hll)
+ x(29)· h(2) + x(28)· h(3)
+ x(27)· h(4) + x(26). h(5)
+ x(25)·h(6) + x(24).hI7)
+ x(23)· h(8) + (22). h(9)
+ x(21 Hll 0) + x(20).h(11)
+x(19)·h(12)+x(18).(13)
+x(17)·h(14)+x(16).h(15)
+x(15)·h(15)+ (14).h(14)
+x(13)·h(13) +x(12)·h(12)
+xlll)·h(ll)+x(l O).h(l 0)
+ X(9)·h(9) + x(8). h(8)
+ x(7).h(7) + x(6)·h(6)
+ x(5). h(5) + x(4)· h(4)
+ x(3)· h(3) + x(2). h(2)
+ xll). h(l) + x(O)·h(OI
x(31). h(l) + x(32).h(0)
+ x(29)·h(3) + x(30).h(2)
+ x(27). h(5) + x(281' h(4)
+ x(25)· h(7) + x(26)·hI6)
+ x(23)· h(9) + x(24).hI8)

31
S=l: hlk)xln-k)
k=O

For More Information call 1-1100-722-7074.

TMC2249
Digital Filtering (cont.)
Alternatively, non-symmetric FIR Filters can be
implemented using the TMC2249 in a similar fashion.
Here, a shift register is used to delay the incoming data
fed to the A input by an amount equal to one-half the
length of the filter (the length of the A delay registerl.
As shown in Figure 5, the data is then sent to the C
input, thus "stacking" the A and C delay registers to
create a single N-tap FIR filter. The incremented delay
words (AOEL - DOELl for all four inputs are identical.
Again, the filter throughput is equal to the clock speed
divided by one-half the number of taps implemented.

Figure 5. Non-Symmetric 32-Tap FIR Filtering
Using the TMC2249

x(m)

>-

A

1---.

B
11(0)

x(m + 15)

11(15)

Taking advantage of the complex multiply which we
implemented above using the TMC2249, we can expand
slightly to calculate a Radix-2 Butterfly, the core of the
Fast Fourier Transform algorithm. To review, the Butterfly
is calculated as shown in Figure 6.

A-----------~~----~-----------X

~

x(m + 0)

Calculating a Butterfly

Figure 6. Signal Flow Diagram of Radix-2 Butterfly

TMC2011
rlI6-STAGE
V
SHIFT REGISTER

Thus we can perform a complex multiplication in two
clock cycles. Notice that the user must switch the two
components of the second input vector between the B
and 0 inputs to obtain the second complex summation.

4

C

0

x(m + 16)

11(16)

x(m + 31)

11(31)

B---t):-'-+--t~~-Y
Where

TMC2249

>

S15-0

and WN r is the complex phase coefficient, or "twiddle
factor" for the N-point transform, which is:
WN r = e-jl27r/NI

t

FILTER
OUTPUT

= cosl27r/NI + j(sin(21r/NIl
= Re(WI + jlm(WI.

Complex Arithmetic Functions
The TMC2249 can also be used to perform complex
arithmetic functions. The basic function performed by the
device, ignoring the delay controls,
SUM

= I±A.BI + I±C.OI.

can realize in two steps the familiar summation:
(P+jRIIS+jTi

=

X=A+BIWNq
Y = A-B(WNrl.

IPS-RTI + jiPT+SRI

111

121

by loading the TMC2249 as follows:

with Re and 1m indicating the real and imaginary parts
of the vector.
Expanding the complex vectors A and B to calculate X
and Y. we get:

X = IRelAI + jlmlAl1 + IReIBIReIWI-lm(BllmIWI + jiRelBllmlWI + ImlBIRelWl1
= IRelAI + ReIBIReIWI-lmIB\lmIWIl + jilmlA\ + ReIB\lmIW\ + ImIB\ReIWIl
= ReIX\+jlmIX\
and,

Y = IReIA\ + jlmIAII-IReIB\ReIWI-lmIBllmIW\ + jiRelB\lmlWI + ImIB\ReIWIl

TMC2249 Inputs
Step

A

B

C

0

NEG1

NEG2

Resultant Output

1
2

P
P

S
T

R
R

T
S

L
L

H
L

(PS-RTI
(PT +SRI

= IReIA\- ReIB\ReIW\ + ImIB\lmIWIl + j(lmIA\- ReIB\lmIWI-lmIB\ReIW\\

= ReIY\+jlmIY\

whp.rp. H ,mel L indicate a 10Dic HIGH and LOW.
For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-145

TMC2249
Calculating a Butterfly (cont.I

Quadrature Modulation

The butterfly is then neatly implemented in four clocks,
as follows:

The TMC2249 can also be used to advantage as a
digital-domain complex frequency synthesizer, as
demonstrated in Figure 7. Here, orthogonal sinusoidal
waveforms are generated digitally by sequentially
addressing Sine and Cosine ROMS. These quadrature
phase coefficients can then be multiplied with two input
signals, such as digitized analog data. The TMC2249
then adds these products, which could be output directly
to a high-speed digital-to-analog converter such as the
TRW TOC1012 for direct waveform synthesis. This 12-bit,
20MHz DAC is ideally s~ited to waveform generation,
featuring extremely low glitch energy for low spurious
harmonics.

TMC2249 Inputs
Step
1
2
3
4

A
Re(B)
Re(B)
Re(B)
Re(B)

B

0

C

CAS
Resultant
Input NEG1 NEG2 Output

Re(W) Im(B) Im(W) Re(A)
Re(W) Im(B) Im(W) Re(A)
Im(W) Im(B) Re(W) Im(A)
Im(W) Im(B) Re(W) Im(A)

L
H
L
H

Re(X)
Re(Y)
Im(X)
Im(Y)

H
L
L
H

Notice again that the components of the second vector
must be switched by the user on the second half of the
computation, as well as the parts of the vector
presented to the cascade input.

Figure 7. Direct Quadrature Waveform Synthesizer Using the TMC2249
B = SIGNAL 1

A=MIXER
,,"====16t:::::.~ R RPT
AMPLITUDE .L.

OE

12M

xl==1:===::::t

OUTPUT = A x(8 xCOS(FT) + CxSIN (FT))

12M

32

F = MIXER
FREQUENCY

01

C= SIGNAL 2

Pin Assignments - 120 Pin Plastic Pin Grid Array, H5 Package
Pin

Name

C3
B2
Bl

CLK
ACC
NEGl
NEG2
RND

D3
C2
Cl
D2
E3
Dl
E2
El
F3
F2
Fl
G2

2-146

S15
S14
GNO
S13
S12
Sll
VDD
SlO
Sg
S8

Pin
G3
Gl
. Hl
H2
H3
Jl
J2
Kl
J3
K2
L1
Ml
K3
L2
Nl

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

GND

L3
M2
N2
L4

BDEL2
BOEL 3
ENB

L7
N7

VDD
Bll

Lll
M12

ADEL3
AOEL 2

Gll
G13

CAS 6
CAS 5

Cll
B12

M3
N3
M4
L5
N4
M5
N5
L6
M6
N6
M7

Bl
B2
B3
B4

N8
M8
L8
N9
M9
N10

All
AlO
Ag

M13
Kll
L12
L13
K12
Jll
K13
J12
J13
Hll
H12
H13
G12

ADELl
ADELa
NC

F13
F12
Fll
E13
E12
D13
Ell
D12
C13
B13
011
C12
A13

CAS 4
CAS 3
CAS 2
CAS l
CAS o
CASEN
FT

A12
ClO
Bll
All
BlO
C9
AlO
B9
A9

S7
S6
S5
VDD
S4
S3
S2
GND
Sl
So
OE
SWAP
BDELO
BDELl

BO

B5
B6
B7
GND
B8
Bg
BlO

L9
M10
Nll
N12
LlO
Mll
N13

A8
A7
A6
A5
A4
A3
A2
Al
AO
ENA

CAS15
CAS14
CAS 13
CAS 12
CAS 11
CAS lO
GND
CASg
CAS 8
CAS 7

Raytheon Semiconductor

CDELo
CDELl
CDEL2
CDEL3
ENC
Co

C8
B8
A8
B7

Name

Pin

Name

Cl
C2
C3
C4
C5
C6
C7
C8
Cg

C7
A7
A6
B6
C6
A5
B5

GND

ClO
Cll
VDD
Dll
°lO
Og

A4
C5
B4

08
• D7
D6
D5
D4
D3
D2
Dl
DO
END

A3
A2
C4
B3

DDEL3
ODEL2
DDELl

Al

DDELO

For More Information call 1-800-722-7074.

TMC2249
Pin Assignments - 132 Leaded CEROUAD, L5 Package
Pin

Name

Pin

Name

Pin

Name

Pin

1
2
3

NC
CLK
ACC
NEGl
NEG2
RND

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

83
82
GND

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66

B7
GND

67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88

4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

815
814
GND
813
812
Sl1
VDD
810
89
88
GND
87
86
85
VDD
84

Sl
80
DE
SWAP
BDELO
BDELl
NC
NC
NC
BDEL2
BDEL3
ENB
Bo
B,
B2
B3
B4
B5
B6

B8
B9
BlO
VDD
B11
All
AlO
A9
A8
A7
A6
A5
A4
A3
A2
Al
AO
ENA
NC
NC

Name

Pin

Name

Pin

Name

NC

89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110

CASo
CASEN

111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132

Cl l
VDD
0 11
010
09
GND

ADEL3
ADEL2
ADELl
ADELO
NC
CAS15
CAS 14
CA8 13
CAS 12
CA8 11
CAS 10
GND
CAS 9
CA88
CA87
CAS6
CAS 5
CAS4
CA83
CA82
CAS 1
132

13
12
11
10

9
8
7
6
5
4
3
2

©©©©©©©©©©©©©
©©©©©©©©©©©©©
©©©©© © ©©©© ©©©
©©©
©©©
©©©
©©©
©©©
©©©
TOP VIEW
©©©
©©©
CAVITY UP
©©©
©©©
©©© ~Key
©©©
©©©
©©©
©©©©©©©©©©©©©
©©©©©©©©©©©©©
©©©©©©©©©©©©©

/

FT
CDELo
CDEL l
CDEL2
CDEL3
ENC
Co
NC
NC
NC
Cl
C2
C3
C4
C5
C6
C7
C8
C9
ClO

08
07
D6
05
04
D3
02
01
DO
END
DDEL3
DDEL2
DOELl
DDELO
NC
NC
100

99

\

/

67

33

ABCDEFGHJKLMN
21041A
21062A

120 Pin Plastic Pin Grid Array - H5 Package

For More Information call 1-800·722·7074.

132 Leaded CEROUAD - L5 Package

Raytheon Semiconductor

2·147

TMC2249
Ordering Information
Product
Number

Temperature Range

Screening

Package

Package
Marking

TMC2249H5C
TMC2249H5Cl

STD-TA =O°C to 70°C
STD-TA =O°C to 70°C

Commercial
Commercial

120 Pin Plastic Pin Grid Array
120 Pin Plastic Pin Grid Array

2249H5C
2249H5Cl

TMC2249L5V
TMC2249L5Vl

EXT - TC= -55°C to 125°C
EXT-TC= -55°C to 125°C

MIL-STD-883
MIL -STD-883

132 Leaded CERGUAD
132 Leaded CERGUAD

2249L5V
2249L5Vl

40G06125 Rev 0 8193

2-148

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2255
TMC2255
CMOS 3 x 3,5 x 5 Image Convolver
8 x 8 Bits, 12 MHz Data Rate

Description
Uke the faster TMC2250, the low cost TMC2255 can
perform a triple 3x1 matrix-vector multiplication or a 3x3
convolution. It can also perform a 5x5 convolution with
bidimensionally symmetrical coefficients. The on-chip
coefficient memory stores four sets of nine 8-bit two's
complement coefficients. Two of the TMC2255's five 8bit coefficients, which can be updated during operation.
The device accepts the unsigned and/or two's
complement data at 1/3 of the applied clock rate.
The 3 (3x1) matrix multiply mode supports various 3space numerical operations, such as video standards
conversion (e.g. VIQ to RGB) or three-dimensional
perspective transformation. Three input ports accept the
8-bit two's complement and/or unsigned magnitude data.
The two remaining input ports can be loaded with
coefficients and/or device control parameters ·on-thefly." In this mode, an output is generated on every clock
cycle.
The 3x3 and 5x5 pixel image convolver modes support
numerous functions, including static filtering and edge

detection. On every third clock cycle, the TMC2255
accepts three (3x3 mode) or five (5x5 mode) data
inputs. In the 5x5 mode, the coefficient kernel must be
symmetric both horizontally and vertically. Outputs from
the device are generated on every third clock cycle,
matching the input pixel data rate, and can be limited
(·clipped") 10 8, 9 or 12 bits.
Fabricated in Raytheon Semiconductor's OMICRONCTM one-micron CMOS process, the TMC2255 will
operate at clock rates of 0 10 30 MHz over the full
commercial temperature (OOC to 70OC) and supply
voltage ranges.

Features
•
•
•
•
•
•
•

8-bit data and coefficient input precision
Triple 3x1 matrix-vector multiplication mode
3x3 and 5x5 two dimensional convolution modes
m-compatible VO with three-state output bus
Offered in 68-contact plastic chip carrier (PLCC)
Built-in 8-, 9-, or 12-bit arithmetic limiter
Two's complement, unsigned, or mixed data
formats

Logic Symbol
A7_0
8 7•0
DATA
INPUTS

C7-0
D7•0
E7-0

CDNTRDl
INPUTS

ClE
CRA 1-0

ClK

For More Information call HlOO-722-7074.

Raytheon Semiconductor

2-149

TMC2255
Applications
•
•
•
•
•
•

RGB To/From YUV/YIQ Color Space Conversion
3x3 Or 5x5 Two Dimensional FIR Filtering
Edge Enhancement And General Image Processing
Robotics And Image Recognition
Electronic Darkroom
Desktop Publishing

Associated Products
• TMC2011 Variable Length Shift Register
• TMC2302 Image Manipulation Sequencer

Functional Description
The TMC2255 contains an array of multipliers and adders,
four 9x8-bit coefficient "pages" and a global control block,
all of which ca~e initialized or reconfigured through ports
D and Ewhen CLE is LOW. Device parameters include
matrix coefficients, internal device configuration (mode).
rounding precision, and input/output data formats (two's
complement, unsigned, or mixed). After the control
parameters have been loaded, device operation
commences with the next clock rising edge on which CLE
returns HIGH. Depending on the mode selected, three or

five data are input in parallel and proceed through a
sequence of operations: Input. Preaddition, MultiplyAccumulation, Rounding, Limiting and Output (Figures 1-4).

Input Stage
Inputs are supplied to ports A through Cin all operating
modes on every third clock cycle, beginnin.9JIYith the clock
rising edge that contains the most recent CLE LOW to HIGH
transition. Control and/or coefficient parameters can be
input through ports D and Eduring any of the three master
clock cycles that make up each data cycle. In the 5x5
convolution mode data enter the device through ports A-E.
Control and/or coefficients may be updated through ports D
and Eon the remaining two cycles of each clock triplet.
Input data formats may be unsigned and/or two's
complement. as identified in the mode select field of
port E.

Preaddition
In and only in 5x5 convolution, the horizontal and vertical
symmetry of the coefficients permits nine multipliers to do
the work of 25. To facilitate this, the data input to ports A
and Eare pre-added before multiplication, as are the Band
D inputs (Figure 4, the 5x5 Block Diagram).

Figure 1. Structural Block Diagram
INPUT

PREAODITION

MULTIPLICATIONI
ACCUMULATION

ROUNDING

LIMITING

OUTPUT

1....-_ _

fiE

RND

MPY-ACC

4x9xB

o

CLE
CRA1_0
CLK

2-150

COEFFICIENT
RAM

CONTROL
21423A

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC22SS
Coefficient Memory

least significant bit; E6= 1: add .100000 and use Z1 as least
significant bit, ignoring ZOo

The TMC2255 contains enough memory to store four
"pages~f nine 8-bit two's complement coefficients each.
When CLE is LOW, a new coefficient is written through
port Eto the page and location address identified on port
O. On every third clock cycle, the coefficient page to be
read and used in the immediate 3-cycle computation set is
selected by CRAO and CRA1. Of the nine coefficients per
page, Kl, i (i= 1 to 3) process the port A (and E) data; K2, i,
the port B (and 0) data; and K3, i, the port C data.

The device provides programmable output limiting in
unsigned (UN) and/or two's complement (TC) format and
for 8, 9, or 12 bits of output precision (including ZO). In
3(3xl) mode, for an RGB to YIO transformation, the device
can limit Zl (Y) to 9 bits unsigned while limiting Z3 (I) and
Z3 (0) to 9 bits two's complement.

Multiplication and Accumulation

Outputs

The device computes nine products during every three
clock cycles, accumulating them internally to full precision.

Output is through the 12-bit Z port, which provides 1/2 or 1
LSB precision, relative to the input format. In the 3(3xl)
mode three outputs will appear consecutively at the Z port
during each triple clock cycle; for data input on clock rising
edge 0, these results will emerge too after clock rising
edges 7,8, and 9. In both convolution modes the results
are output at 1/3 the device master clock rate, with the
first point of the impulse respoose emerging after clock
rising edge 9. To facilitate connection to a bus, the output
buffers are enabled and disabled (placed inj}ighimpedance state) by asynchronous control OE.

Rounding
Accumulated sums of products are rounded before the last
5 or 6 bits are truncated. Rounding is performed by adding
"010000" or "100000" to the emerging data stream,
accordiillLto the desired precision of the output results.
When CLE=O and O=OXXXllll, pin E6 sets the chip's
rounding position, viz: E6=0: add .010000 and use Zo as

For More Information call 1-800-722·7074.

Output Limiting

Raytheon Semiconductor

2·151

TMC2255
Figure 2. Functional Block Diagram, 3(3x1) Mode

...-----+ClK
ClK ) - - - +.....

ClKf,!

4x9x8
COEFFICIENT

RAM

eRA 1-0 >4[J---.L.R_A_ _ _ _ _ _......
Z11_ 0

2-152

Raytheon Semiconductor

21424A

For More Information call 1-800-722-7074.

TMC2255
Figure 3. Functional Block Diagram. 3x3 Mode

.-----+ClK
ClK }---4-+I

ClK/3

ClE

4x9x8

COEFFICIENT
RAM

CRA 1_0

~

...R_A_ _ _ _ _ _--II
Zl1-0

For More Information call 1-800·722·7074.

Raytheon Semiconductor

21425A

2·153

TMC2255
Figure 4. Functional Block Diagram, 5x5 Mode

CLK
CLK

ClM

ClE

°7_.0
4x9x8

COEFFICIENT
RAM
E7-O

2-154

Raytheon Semiconductor

For Mora Information call 1-800-722-7074.

TMC2255
Signal Definitions

cycles to avoid corrupting 3x3 or 3x(3x1)
work in progress. CRA should not be
updated during a 5x5 operation whose
result is needed.

Inputs
CLK

DATA INPUTS

CLE

CRAO,CRA1

Master chip clock, 0 to 30M Hz. All
operations are referenced to the rising
edges of CLK.
Of the device's five S-bit data input ports,
A, B, and Care used exclusively as data
inputs, whereas 0 and Eare also used to
program the device (see description of
CLE pin). For 5x5 convolution, all five
ports accept incoming data. In the other
modes, only Ports A-C accept incoming
data, leaving 0 and Ededicated to
control and coefficient values, which may
be updated at any time. In all modes,
data are loaded on every third rising
edge of CLOCK, beginrili!g on a clock
rising edge for which CLE makes a O-to-1
transition. Bits A7, B7, ... are the two's
complement sign bits or most significant
unsigned bits; bits AO, BO, ... are the
least significant bits (LSBs)
Active-LOW coefficient and control load
enable. When CLE is LOW, Ebecomes
the input port for the coefficients, and 0
becomes the coefficient write address
and control port. When CLE is HIGH, all
coefficients are held unchanged. A LOW
to HIGH transition at CLE also
synchronizes the TMC2255, ushering in a
new data input.

When updating coefficients on-the-fly
the user should not set CRA1-0 and 05:4
to the same page, but should read from
one page while writing to another.
OE

Asynchronous,~tive-LOW

output
enable. When OE is LOW, the output
drivers are enabled. When OE is HIGH
they are disabled (high-impedance). '

Outputs
DATA OUTPUTS Outputs available on the Z Port are
enabled by OE. Z11 is the unsigned
MSB or two's complement MSB/sign
bit; Z1 is the integer LSB (" ones' digit").
Zo is the 1/2 (fractional) digit. In the
3(3x1) mode (E=XXXXXOXX), a new valid
result will emerge too after every rising
edge of CLOCK. In the other modes
(E=XXXXX1XX), a result emerges after
every third rising edge of CLOCK. When
9-bit limiting is used, bits Z11 through Zs
will be identical.
Operation and Timing
Before operation, the TMC2255 must be initialized, i.e.
loaded with coefficients and set to the desired operating
mode, data format. and rounding precision. The chip is
programmed via ports 0 and E, which double as data input
ports in 5X5 mode.

Coefficient read address. The chip can
hold four "pages" of nine coefficients
each. These two pins determine which of
the four coefficient sets is to be used
with the data entering during that cycle.

Initialization

The timing of coefficient selection by
CRA is mode dependent. In the 3(3x1)
mode, CRA influences all coefficients
simultaneously. In the 3x3 and 5x5
convolution modes, however, CRA
selects the coefficients for each
multiplier column individually, i.e., three
per clock cycle from left to right (Block
Diagram - 3x3 Mode). CRA should be
changed only on "data input" clock

This control is accessed through bit 7 of port O. When CLE
is LOW, 07 must be LOW to allow the coefficient/control
information to be updated. If 07 is HIGH when CLE is
forced LOW, the device will not allow the coefficient or
control information to be updated, and device execution
will begin or continue~commanded on the previous LOW
to HIGH transition of CLE. Holding 07 HIGH (at least when
CLE is LOW) permits the system to resynchronize the chip
without changing any coefficients or configuration
parameters.

For More In'onnation call 1-800-722-7074.

Chip Select

Raytheon Semiconductor

2-155

TMC2255
Coefficient Loading

Mode Selection

When CLE and 07 are LOW, the coefficient values
presented to port 6 are loaded into the coefficient position
and page registers selected by port 0, as shown below.

When CLE=O and D=OXXX1111, pins E2-0 select the chip's
operating MODE and input data formats, viz:

When
D7-0=

Update From E7-0:
Coef

OXYVOOOO
OXYVOOOI
OXVVOO10
OXYV0100
OXVV010l
OXVV011O
OXVV1000
OXVV1001
OXVV101O
OXXXOX11
OXXXXOll
OXXX110X
OXXXllXO
OXXXllll
lXXXXXX

1,1
1,2
1,3
2,1
2,2
2,3
3,1
3,2
3,3
Hold all Coefficients
Hold all Coefficients
Hold all Coefficients
Hold all Coefficients
Control Information
Hold all Coefficients

Page
VV
VV
YV
VV
VV
YV
VV
VV
VV

When
E7-0=

Mode =

Data Formats=

OXXXXOOO
OXXXXOOI
OXXXX010
OXXXXOll

3(3xl )mat mpy
TCTC TC
3(3xl )mat mpy
UN TCTC

3(3xl )mat mpy
UN UN UN

ZI = A*Kl,1 + B*K2,1 + C*K3,1
Z2 = A*Kl,2 + B*K2,2 + C*K3,2
Z3 = A*Kl,3 + B*K2,3 + C*K3,3
OXXXX100
OXXXX10l

AB C

first of 3 results
last of 3 results

3x3 convolution
3x3 convolution

TCTC TC
UN UN UN

Z =Al*Kl,1 + Bl*K2,1 + Cl*K3,1
+ A2*Kl ,2 + B2*K2,2 + C2*K3,2
+ A3*Kl,3 + B3*K2,3 + C3*K3,3
OXXXXll0
OXXXX111

X = Don't Care

Each of the four "pages" YY comprises a full set of nine
coefficients (one per filter tap).

5x5 convolution
5x5 convolution

TC TCTC
UN UN UN

Z = Al*Kl,3 + Bl*K2,3 + Cl*K3,3 + Dl*K2,3 + El*Kl,3
+ A2*Kl,2 + B2*K2,2 + C2*K3,2 + D2*K2,2 + E2*Kl,2
+A3*Kl,1 + B3*K2,1 + C3*K3,1 + D3*K2,1 + E3*Kl,1
+ A4*Kl,2 + B4*K2,2 + C4*K3,2 + D4*K2,2 + E4*Kl,2
+ A5*Kl,3 + B5*K2,3 + C5*K3,3 + D5*K2,3 + E5*Kl,3
lXXXXXXX
[Unchanged from previous setting]
[Coefficients are always 8-bit two's complement.]

2-156

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2255
Timing

Rounding

All computuations are rounded internally following the
final accumulation of products. Rounding position depends
on the output format. If the user desires outputs with
1/2 LSB precision (relative to the inputs) then rounding is
performed into Z-1, just to the right of the LSB of the
output port, ZOo For 1 LSB precision, rounding is into ZO,
and the output is on pins Zll-l only.
Rounded at:

When E7-0 =

Outputs are,

OOXXXXXX
OIXXXXXX
IXXXXXXX

Zl1-Z0 (12 bits)
Zl1-Z1 (II bits)
Unchanged from previous setting

Result Latency

Device operating mode affects when valid results will be
available at the output port Zll :0. The three results of a
3xl triple dot product whose inputs enter on clock rising
edge 0 will be available too after clock rising edges
7,8, and 9. In a 3 x 3 and 5 x 5 convolution, the first
three impulse response points will emerge after clock
rising edges 9, 12, and 15. The last two points of a
5-point response (5x5 mode) will follow after rising edges
18 and 21.
Instructions, Inputs, and Synchronization

Output Limiting

When CLE=O and O=OXXXllll, pins E5-3 tell the chip to
which numerical format(s) to limit the emerging results.
Unsigned (UN), two's complement (TC), and mixed data
formats of 8, 9, or 12 bits (including ZO) are supported, as
follows. Limit ''Z'' applies to 3x3 and 5x5 convolutional
modes; limits Zl, Z2, Z3 apply to 3(3xl) mode.
Limit Z2

E7-0=

Limit Z1 or Z

Limit Z3

OXOOOXXX
OXOOIXXX
OXOIOXXX
OXOll XXX
OXIOOXXX
OXI01XXX
OXIIOXXX
OXlllXXX
IXXXXXX


UN9
UN9
UN9
TC12
TCI2
TCI2
UNI2
UNI2
UNI2
TC9
TC9
TC9
TC9
UN9
TC9

UN8
UN8
UN8
Unchanged from previous setting

Range
(RND=II)
0,255.5
-1024, I 023.5
0,2047.5
-128,127.5
(mixed)
0,127.5

Each rising edge of CLK which bears a CLE LOW to HIGH
transistion resynchronizes the device. If CLE goes from
LOW to HIGH on clock rising edge N, then the chip will
resynchronize, starting a new 3-cycle sequence on that
edge. It will look for incoming data at clock rising edges
N+3i, where i ':...L 2, ... (Timing Diagrams, Figures 5
through 11). If CLE is brought LOW while an operation is
already in progress (e.g., to update coefficients!, it should
be brought HIGH only on a regular data input clock cycle
(N+3i), to avoid corrupting pending results.
If CLE is LOW, control and/or coefficient information
entering on a rising edge of CLK will affect all subsequent
data inputs until the control parameters are again updated.
Internal pipelining of the controls ensures that "in
progress" operations on data previo~ input to the device
will continue unaffected, as long as CLE is brought HIGH
only on data input clock edges.
System Timing

Prior to output, the limiter (if enabled) tests the leading bits
of the emerging result. In the unsigned limit modes, if the
MSB=l, denoting a negative value, the output is forced to
0; if the MSB=O but any other bit above the 8, 9 or 12 bit
output field = 1, the output is forced to 11111111111.1 In
the TC9 limit mode, values above 127.5 (00001111111.1)
are forced to 00001111111.1 and values below -128
become 11110000000.0. In the TC12 limit mode,
values above 1023.5 (01111111111.1) are forced to
01111111111.1, and values below -1024 become
10000000000.0. If full LSB rounding (E6= 1) is used, output
bit Zo is ignored, each data format is correspondingly 1 bit
narrower than shown in the table, and the .5 fractions
disappear from the range limits.

For More Information call 1-800-722-7074.

Because the TMC2255's data throughput rate is 1/3 of its
incoming clock rate, the user must synchronize the data
inputs with the chip's control inputs and internal operation.
Figures 5through 8 illustrate four ways to use rising
edges of CLE to align data inputs in the 3(3xl) and 3x3
modes, whereas Figures 9 through 11 show how to use
CLE in the 5x5 mode.

Raytheon Semiconductor

2-157

TMC2255
In Figure 5, thecIt 0 to 1 transition on ClK rising edge
3("t =3") initializes the chip. The final configuration and
coefficient values are loaded through ports 0 and Eat t =2
and the first incoming data enter ports A, B, and Con rising
edge 6. In 3(3x1) mode, the three results from the t =6
input data emerge after t =13, 14, and 15. In 3x3 mode, the
first result from the edge 6 input data appears after edge
15 and remains until t = 18, when the second result using

t =6 inputs (which is the first result using t =9 inputs)
emerges. After t = 18, the convolution of the t =6, t =9,
and t = 12 inputs, the last output involving the t = 6 input,
appears. The part operates continuousy, with inputs read
on every third rising clock edge and a new output available
too after each rising clock edge (3(3x1) mode) or every
third rising edge (3x3 mode).

Figure 5. 3(3x1), 3x3 Timing Diagram, Single CLE Rising Edge
9

12

15

18

ClK

ClE _ _ _ _.....I

I

I

I

I

I

I

I

I

I

I

I

I

~«XXXXXXXXXXXXlXXXXXMXXXXXNXXXXXpXXXXXOXXX)
c7_0

~«XXXXlXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX)
EM

I

I

I

I

I

I

I

I

I

I

I

I

«XXXXlXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX)
I
I
I
I
I
-__--+-=-:-::--1

GNO

pWELL

211208

21121A

Figure 16. Transition Levels for Three-State Measurements

lOIS
THREE·STATE
OUTPUTS

O.SV

-----J\-.

HIGH IMPEDANCE

O.SV

21265A

Package Interconnections
Signal
Type

Signal
Name

Rt Package

Function

Power

VOO
GNO

Supply Voltage (+5)
Ground

Clock

ClK

System Clock

8

Control

ClE
DE
CRA1-0

Coefficient load Enable
Output Enable
Coefficient Read Address

6
7
62,63

Inputs

A7-0
B7-0
C7-0
07-0
E7-0

Data Input Port A
Data B
Data C
Control/Data 0
Coefficient/Data E

64,65,66,67,68,3,4, 5
54,55,56,57,58,59,60,61
44,45,46,47,48,49,50,51
36,37,38,39,40,41,42,43
27,28,29,30,31,32,33,34

Outputs

Zl1-0

Data Dutp uts

11,12,14,15,16,19,20,21,22,23,24,25

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2,10,17,53
1,9,18,26,35,52

2-167

TMC22S5
Pin Assignments - 68-Lead Plastic Chip Carrier - Rl Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

Name

GNO
VOO
A2
Al
AO
ClE
DE
ClK

GNO
VOO
ZII
ZIO

GNO
Z9
Z8
Z7

VOO

Pin
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

Name

GNO
Z6
Z5
Z4
Z3
Z2
ZI

Zo
GNO
E7
E6
E5
E4
E3
E2
El
EO

Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

Name

GNO
07
06
05
04
03
02
01
00
C7
C6
C5
C4
C3
C2
Cl
Co

Pin
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

Name

GNO
VOO
B7
B6
B5
B4
B3
B2
Bl
BO
CRAI
CRAO
A7
A6
A5
A4
A3

..,...

C'\I

(I')

oo:r

W)

U)

cC

r-- CZ

0

_

C'I

C")

oo:r 10

U)

.....

mmmmmmm>OQOUOUOOU

mm~~~~~~~~~~~~~~3

80
CRA1
CRAO
A7

61
62
63
64

'

43
42
41
40
39
38
37
36
35
34
33
32
31
30

A6 65
AS 66
A4 67
A3 68
GNO 1
VOO 2
A2 3

A1

0

4

Ao

ClE

DO
01
02
03
04
05
06
07
GNO

EO
E1
E2
E3
E4

OE

29 ES

ClK

2B E6
27 E7

GNO

9

Ordering Information
Product
Number

Data
Rate MHz

Temperature Range

Screening

Package

Package
Marking

TMC2255R1C
TMC2255R1Cl

10
12.5

STD-TA =O°C to 70 0 C
STD-TA =O°C to 70 0 C

Commercial
Commercial

68 Pin PlCC
68 Pin PlCC

2255Rl C
2255R1Cl

40006713 Rev B 8193

2-168

Raytheon Semiconductor

For More Information call 1-800-722-7074_

TMC2272
TMC2272
Digital Colorspace Converter/Corrector
36-Bit Color (12 Bits x 3 Components) 40 MHz

Description

A complete set of three 12-bit samples is processed on
every clock cycle, with a five-cycle pipeline latency. Full
23-bit (for each of three components) internal precision
is provided with 10-bit user-defined coefficients. The
coefficients may be varied dynamically, with three new
coefficients loaded every clock cycle. (The full set of
nine can be replaced in three clock cycles.) Rounding to
12 bits per component is performed only at the final
output. This allows full accuracy with correct rounding
and overflow headroom for applications that require less
than 12 bits per component. All inputs and outputs are
registered on the rising edges of the clock.

A 40 MHz, three-channel, 36 bit (three 12-bit
components) colorspace converter and color corrector,
the TMC2272 uses 9 parallel multipliers to process highresolution imagery in real time.
The TMC2272 also operates at any slower clock rate
and with any smaller data path width, allowing it to
handle all broadcast and consumer camera, framegrabber, encoder/decoder, recorder and monitor
applications as well as most electronic imaging
applications.

The TMC2272 is fabricated in a one-micron CMOS
process and has fully guaranteed performance over the
full commercial temperature range of 0 to 70ce, and all
other operational conditions specified in the Operating
Conditions table. The TMC2272 is available in a 121pin plastiC pin-grid array (PPGA) package in three speed
grades.

The TMC2272's processing ability allows colorspaces to
be optimized for every input or output device; camera,
monitor, transmission or storage medium in real time,
regardless of the Signal format required by each stage in
a system. For instance, a frame buffer may be operated
in any desired colorspace in an otherwise RGB system
with the use of two TMC2272s for translation to and from
the desired frame-buffer colorspace.
Logic Symbol

CLOCK

,

V

/

12
A(11-O) L
DATA {
INPUTS

12
B(11 ·0) L
C(11.0)

COEFFICIENT
INPUTS AND
WRITE
SELECT

1

>

~

1

' 12l.
I

KA(9-0)

L

L

KB(9.0)

>

I

10 "
10

~

®®®
®®®
®®®

,.12 "

(lH)}

x
12 "
I

12
I

~

"

Y(11 ·0)

DATA
OUTPUT

Z(11-O)

TMC2272
1oj:,

KC(9-0)

}

CSEL~.OI

,

For More Information call 1-800-722-7074.

I
2 •
24042A

Raytheon Semiconductor

2-169

TMC2272
Features

Associated Products

•
•

•
•
•
•
•
•

•
•
•
•
•
•
•
•

40 MHz (25 ns) pipelined throughput
3 Simultaneous 12-bit input and output channels
(64 Giga (236) colors)
Two's complement inputs and outputs
Overflow headroom available in lower resolution
1D-bit user-defined coefficients
TTL-compatible input and output signals
Full precision internal calculation
Output rounding
On-board coefficient memory
OMICRON-C™ 1J,1CMOS process

TDC1058 ND Converter
TDC1049 ND Converter
TMC2242 Interpolator!Decimator
TMC2230 Rectangular/Polar Converter
TMC22X9X Digital Video Encoder
TMC22071 Genlocking Video Digitizer

Applications
•
•
•
•
•
•
•
•

Translation between component color standards
(RGB, YIQ, YW, etc.)
Broadcast composite color encoding and decoding
(all standards)
Broadcast composite color standards conversion
and transcoding
Camera tube and monitor phosphor colorimetry
correction
White balancing and color-temperature conversion
Image capture, processing and storage
Color matching between systems, cameras and
monitors
Three-dimensional perspective translation

2-170

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2272
Figure 1. Functional Block Diagram
1>,;::::J:=========~;;;~-::-:-;-;;--------ICWSEl1,O =11
ENABLE K_Z

CWSEl1,O=Ol
ENABLE K_X

ClK

>-------.
Zll·0

For More Information call 1-800-722-7074.

Raytheon Semiconductor

24043A

2-171

TMC2272
Functional Description
General Information
The TMG2272 is a nine-multiplier array with the
internal bus structure and summing adders needed to
implement a 3 x 3 matrix multiplier (triple dot product).
With a 40MHz guaranteed maximum clock rate. this device
offers video and imaging system designers a single-chip
solution to numerous common image and signal-processing
problems.

Applications Discussion regarding encoded video
standard conversion matrices.
X(5) = A(l )KAX(l) + B(l )KBX(l) + G(l )KGX(l)
Y(5) =A(l )KAY(1) + B(l )KBY(1) + G(l )KGY(l)
Z(5) = A(l )KAZ(l) + B(l )KBZ(l) + G(l )KGZ(l)
Pin Definitions
Power
VOO. GNO

The three data input ports (All-0. Bll-0. Gll-0) accept
12-bit two's complement integer data. which is also the
format for the output ports (X 11-0. Y11-0. and Z11-0).
Other format and path width options are discussed in the
numeric format and overflow section. The coefficient input
ports (KA. KB. KG) are always 10-bit two's complement
fractional. Table 2details the bit weighting.

GWSEll-0

Full precision is maintained throughout the TMG2272.
Each output is accurately rounded to 12 bits from the
23 bits entering the final adder.

Clock

Signal Definitions
A(n). B(n). G(n)

Indicates the data word presented to
that input port during the specified
clock rising edge (n). Applies to input
ports All-0. Bll-0. and Gll-0·

KAX(n) thru KGZ(n) Indicates coefficient value stored in
the specified one of the nine onboard
coefficient registers KAX through KGZ.
input during or before the specified
clock rising edge (n).
X(n). YIn). Z(n)

Indicates data available at that output
port too after the specified clock rising
edge (n). Applies to output ports X11-0.
Y11-0. and Zl1-0·

The TMG2272 operates from a single
+5V supply. All pins must be connected.

Control

GlK

This input selects which three of the 9
coefficient registers. if any. will be updated
on the next clock cycle from the KAg-O. KBg-O
and KGg-O inputs. See Table 4 and the
Functional Block Diagram.

The TMG2272 operates from a single system
clock input. All timing specifications are
referenced to the rising edge of clock.

Data and Coefficient Inputs
All-0. Bll-0. Gll-0 These are the three 12-bit wide data
input ports.
KAg-O. KBg-O. KGg-O These are the 1O-bit wide coefficient
input ports. The value at each of
these three inputs will update one
coefficient register as selected
by the coefficient write select
(GWSEll-0) on the next clock.
See Table 1and the Functional
Block Diagram.

The TMG2272 utilizes six input and output ports to realize a Outputs
"triple dot product." in which each output is the sum of all
X11-0. Y11-0. Z11-0
three input words in multiplied by the appropriate stored
coefficients. The three corresponding sums of products are
available at the outputs five clock cycles after the input
data are latched. and three new data words rounded to
12-bits are then available every clock cycle. See the

2-172

Raytheon Semiconductor

These are the data outputs. Data
are available at the 12-bit registered
Output Ports X. Y. and Z too after
every clock rising edge.

For More Information calI1..aoo·722·7074.

TMC2272
Table 1. Coefficient Loading
CWSELl,O
00

01

10

11

Load
KAX

Load
KAY

Load
KAZ

Input

KAS-O

Hold
All

Input

KBS-O

Hold
All

Load
KBX

Load
KBY

Load
KBZ

Input

KCS-O

Hold
All

Load
KCX

Load
KCY

Load
KCZ

Package Interconnections
Signal
Type

Signal
Name

Power

VDD
GND

Supply Voltage
Ground

F3, H3, L7, C8, C4
E3, G3,J3, L4, L6, Hll, C7, C5,A4, B5

Clock

CLK

System Clock

Dll

Controls

CWSEL1,0

Coefficient Write Select

J12, J13

Inputs

All-0

Data Input A

Bll-0

Data Input B

Cll-0

Data Input C

KAS-O

Coefficient Input KAX, KAY,
orKAZ
(See Pin Definitions and
Table 1)
Coefficient Input KBX, KBY,
orKBZ
(See Pin Definitions and
Table 1)
Coefficient Input KCX, KCY,
or KCZ
(See Pin Definitions and
Table 1)

Ell, D13, E12, E13, Fl1, F12,
F13, G13, Gll, G12, H13, H12
Bl0, All, Bll, Cl0, A12, B12,
Cll, A13, C12, B13, C13, D12
A5, C6, B6, A6, A7, B7,
A8, B8, A9, BS, A10, CS
K13, Jll, K12, L13, L12, Kl1,
M13, M12, L11, N13

KB9-0

KCS-O

Outputs

Xll-0

Output X

Yll-0

Output Y

Zl1-0

Output Z

For More Information call 1-800-722-7074.

H5 Package

Function

Raytheon Semiconductor

Mll, Ll0, N12, Nll, MlO, L9,
Nl0, MS, N9, L8

M8, N8, N7, M7, N6, M6,
N5, M5, N4, L5

B4, A3, A2, B3, A1, C3,
B2, Bl, D3, C2, Cl, D2
D1, E2, El, F2, Fl, G2, Gl,
Hl, Kl, J2, Jl, H2
M4, N3, M3, N2, M2, L3
Nl, L2, K3, Ml, Ll, K2

2-173

TMC2272
Figure 2. Impulse Response

ClK

CWSEl1,0
KA, KB, KC

X
X

01

(0)

XX
XX

10

(K_Y)

XX
XX

11

(K_Z)

A
X

00

DATA IN A, B, C
KAX + KBX + KCX

A
A
A

XOUT

X
X

KAY + KBY + KCY

YOUT

KAZ + KBZ + KCZ

ZOUT

X

21509A

Figure 3. Input/Output Timing Diagram

ClK

CWSEl1, 0
KA,KB, KC
X, V,Z

ri
III

-4tSltH~

_

LI

PREVIOUS

tHO-----l

2-174

l--tPWL

21510A

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2272
Numeric Format and Overflow
Table 2 shows the binary weightings of the input and
output ports of the TMC2272. Although the internal sums
of products could grow to 23-bits, the outputs X, Y, and Z
are rounded to yield 12-bit integer words. Thus the output
format is identical to the input data format. Bit weighting
is easily adjusted by applying the same scaling correction
factor to both input and output data words.
As shown in Table 2, the TMC2272's matched input
and output data formats accommodate OdB (unity) gain.
Therefore the user must be aware of input conditions
that could lead to numeric overflow. Maximum input data
and coefficient word sizes must be taken into account with
the specific translation performed to ensure that no
overflow occurs.

The most apparent mode of operation is to left justify
the incoming data and to ground the unused input LSBs.
However, the outputs will still be rounded to the least
significant bit of the TMC2272, having little if any effect
on the top 8 bits actually used. Because the TMC2272
carries out all calculations to full precision, the preferred
mode of operation is to right justify and sign extend the
data as shown in Figure 4. Since all the LSBs are used,
the desired output will be rounded correctly, and overflow
will be accommodated by bits 7 through 10.
The TMC2272 may also be used in unsigned binary 8-bit
systems as shown in Figure 5. Bits 11 through 8 will
handle overflow.
In all applications, a digital zero (ground) should be
connected to all unused inputs.

Use with Fewer Than 12 Bits
The TMC2272 can be configured to provide several format
and overflow options when used in systems with fewer
than 12-bits of resolution. An 8-bit system will be used as
an example, however these concepts apply to any other
word width.

Table 2. Bit Weightings for Input and Output Data Words
Bit Weights

211 210 29

28

27

26

25

24

23

22

21

-111

IS

17

16

15

14

13

12

11

20

2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9

INPUTS
All Modes
Data A, B, C

110

19

Coefficients
KA,KB,KC
Internal Sum

10
-K9 .

-X20 X19 X18 X17

X16 X15 X14 X13

X12 Xll

XlO X9

07

03

01

KS

K7

K6

K5

K4

K3

K2

Kl

KO

XS

X7

X6

X5

X4

X3

X2

Xl

Xo

OUTPUTS
X,V,Z
Note:

-011 010 09

Os

06

05

04

02

00

A minus sign indicates a two's complement sign bit.

For More Information call 1-800-722·7074.

Raytheon Semiconductor

2·175

TMC2272
Figure 4. Two's Complement 8-Bit Application
INPUTS
(A11 • 0, Bll·00RCll·0)

SIGN
EXTENSION

OUTPUTS
(X11 • 0' Yll.00RZll. 0)

TMC2272
BIT WEIGHTINGS

-

-

MSB(7)

MSB(ll)
(10)

Figure 5. Binary 8-Bit Application
INPUTS
(A11 • 0, B11 • 0 OR Cl1• 0)

MSB (7)

~J

(9)

I-

(8)

I-

(7)

1--

NCt
OVERFLOW
(WILL
ACCUMUL ATE
OVERFLOW)

OUTPUTS
(X11 • 0' Y11.0 0RZ11·0)

TMC2272
BIT WEIGHTINGS

GND -

MSB(ll)

GND -

(10)

=J~~

GND -

(9)

-

GND -

(8)

--

OW
(WILL ACCU MULATE
OVERFLOW TO
4,09510

MSB(7)

(7)

MSB(7)

(6)

(6)

(6)

(6)

(6)

(6)

(5)

(5)

(5)

(5)

(5)

(5)
(4)

(4)

(4)

(4)

(4)

(4)

(3)

(3)

(3)

(3)

(3)

(3)

(2)

(2)

(2)

(2)

(1)

(1)

(1)

(1)

LSB(O)

LSB(O)

(2)

(2)

(1)

(1)

LSB(O)

LSB(O)

LSB(O)
24044A

LSB(O)
24045A

Absolute maximum ratings (beyond which the device may be damaged)1
Supply Voltage ...............................................................................................................................................................................................-0.5 to +7.0V
Input Voltage .....................................................................................................................................................................................-0.5 to (VDD + 0.5)V
Output
Applied voltage ....................................................................................................................................................................-0.5 to (VDD + 0.5)V2
Forced current ...............................................................................................................................................................................-6.0 to 6.0mA3,4
Short-circuit duration
(single output in HIGH state to ground) .................................................................................................................................................. 1 sec
Temperature
Operating case ..................................................................................................................................................................................-60 to +130°C
junction .................................................................................................................................................................................................175°C
lead soldering (10 seconds) .........................................................................................................................................................................300°c
Storage .............................................................................................................................................................................................................-65 to 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional
operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range. and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

2-176

Raytheon Semiconductor

For More Information call 1-800·722-7074.

TMC2272
Operating conditions
Temperature Range
Parameter

Min

VDD
VIL
VIH

Supply Voltage
Input Voltage,Logic LOW
Input Voltage.Logic HIGH

IOL
IOH

Output Current,Logic LOW
Output Current,Logic HIGH

tCY

Cycle Time
TMC2272
TMC2272-1
TMC2272-2

4.75

Standard
Nom
5.0

Max
5.25
0.8

2.0
4.0
-2.0

33

Units
V
V
V
mA
mA

27.7
25

ns
ns
ns

Clock Pulse Width,LOW
TMC2272
TMC2272-1
TMC2272-2

15
12
10

ns
ns
ns

tpWH

Clock Pulse Width,HIGH

10

ns

ts

Input Setup Time
TMC2272
TMC2272-1
TMC2272-2

8
7
6

ns
ns
ns

Input Hold Time
TMC2272
TMC2272-1
TMC2272-2

3
3

ns
ns
ns

AmbientTemperature, Still Air

0

tpWL

tH

TA

For More Information call 1-800-722·7074.

2

Raytheon Semiconductor

70

oC

2·177

TMC2272
Electrical characteristics within specified operating conditions 1

Parameter

Test Conditions

Temperature Range
Standard
Max
Min

Units

IOOQ
IOOU

Supply Current, Quiescent
Supply Current, Unloaded

Voo=Max, VIN=OV
Voo=Max, f=20MHz

12
160

rnA
rnA

III
IIH
IOZl

Input Current,logic lOW2
Input Current,Logic HIGH2
Leakage Current, Logic LOW!

±10

uA
uA
uA
uA

IOZH

Leakage Current, Logic HIGH3

Voo=Max, VIN=OV
Voo=Max, VIN=VOO
Voo=Max, VIN=OV
Voo=Max, VIN=VOO

VOL
VOH

Output Voltage,Logic lOW
Output Voltage,Logic HIGH

Voo=Min,IOl=4mA
Voo=Min,IOH=-2mA

lOS

Short-Circuit Output
Current

Voo=Max, Output HIGH,
One Pin to Ground,
One Second Duration Max.

CI
Co

Input Capacitance
Output Capacitance

TA=25 0 C, f=lMHz
TA=25 0 C, f=lMHz

Notes:

±10
±40
±40
0.4
2.4
-20

V
V

-80

rnA

10
10

pF
pF

1. Actual test conditions may vary from those shown, but guarantee operation as specified.
2. Except pins X11·Q, Y11-Q
3. Pins X11-Q. Y11.8 only.

Switching characteristics within specified operating conditions

Parameter

2-178

Test Conditions

Output Oelay
TMC2272
TMC2272-1
TMC2272-2

Voo=Min, CLOAO=25pF

tHO Output Hold Time
TMC2272
TMC2272-1
TMC2272-2

Voo=Max, CLOAO=25pF

to

Temperature Range
Standard
Max
Min
18
17
16

3
3
3

Raytheon Semiconductor

Units
ns
ns
ns

ns
ns
ns

For More Information call 1-800-722·7074.

TMC2272
Figure 7. Equivalent Output Circuit

Figure 6. Equivalent Input Circuit

nSUBSTRATE
01

p

p+

CONTROL
INPUT
0--+---+

02

)-------1"-----1 P WELL
':' GNO

21499A
21121A

Applications Discussion
The TMC2272 can convert between any two threecoordinate colorspaces with the selection of the proper
coefficients. Sets of coefficients for some popular
colorspace conversions are presented below.
By concatenating coefficient matrices of single
transformations, the user can program the TMC2272 to
perform compound transforms efficiently. For example,
given an RGB input, correction of the relative values of R
and B, for color temperature, conversion to YIQ,

modification of contrast by changing Y, and conversion
back to RGB can be performed as quickly and easily as any
simple transformation. To calculate the final set of
coefficients from the coefficients of the individual
transformations, the procedure in Figure 8(concatenation)
is used. If more than two matrices are to be combined, the
result from the concatenation of the first two matrices is
concatenated with the third. If more matrices must be
incorporated in the final function, the last step is repeated.

Figure 8. Concatenation

ABC

J K L

E F

M N 0

o

G H I

P Q R

=

AJ + BM + CP AK + BN + CQ AL+ BO+ CR
OJ + EM + FP OK + EN + FQ OL + EO + FR
GJ + HM + IP GK + HN + IQ GL + HO + IR
24046A

For Mora Information calI1-80D-722-7074.

Raytheon Semiconductor

2·179

TMC2272
Converting From GSR to YCSCR
With the right coefficients, two external NOT gates,
and an external 4-bit half-addder, the TMC2272
can convert video data from 8-bit full-scale (e.g.,
VGA) GBR components to 1O-bit YCBCR
components.
Table 1. 10-bit component formats
inclusive ranges.
Color Space Term
Data
Range
64-940
Luminance
Y
Y - 64
0-876
Y'
Color difference,
64-960
CB
Blue
U'
+/-448
CB - 512
Color difference,
64-960
CR
Red
V'
CR - 512
+/-448
GBR Green, Blue, Red 0-255
components

and
Format
magnitude
maqnitud
magnitude
2's comp
magnitude
2s comp
magnitude,
8-bits

The analog defining equations for 1 Volt luminance
and +/-0.5 Volt color difference components are:
Y = 0.5870 (G)
B - Y = -0.3313 (G)
R-Y= -0.4187 (G)

+ 0.1140 (B)
+ 0.5000 (B)
-0.0813 (B)

+ 0.2990 (R)
- 0.1687 (R)
+ 0.5000 (R)

To translate these equations into the digital
domain, note that the ranges of R, G, and Bare 0
to 255 instead of 0 to 1, the range of Y is 64 to 940
instead of 0 to 1, and the ranges of U and V are 64
to 960, instead of +/- 0.5:
Y

= (876/255)(0.S87(G)+0.114(B)+0.299(R))+64
= 2.01652 (G) +0.39162 (B) + 1.02715 (R) + 64

Let Y' = Y - 64, U' =C8 - 512, and V' = CR - 512.
The TMC2272 will compute Y', U', and V'. Adding
64 (040h) externally to Y' will then yield Y, whereas
inverting the most significant bits of U' and V', U'9
and V'9, will yield CB and CR, respectively.
Multiplying the equations immediately above by
128 and rounding each coefficient to the nearest
integer yields the recommended set of coefficients
for G8R to YUV conversion.
128 (Y') = 258 (G) +50 (B) +131 (R)
102
032
083
128 (U') = -149 (G) +225 (B) -76 (R)
OEl
3B4
36B
128 (V') = -188 (G) -37 (B) +225 (R)
344
3DB
OEl

dec.
hex
dec.
hex
dec.
hex

If the TMC2272 input data alignment for 8-bit GBR
is:
o 0 G7 G6 G5 G4 G3 G2 G1 GO 0 0
o 0 87 86 85 B4 B3 82 81 80 0 0
o 0 R7 R6 R5 R4 R3 R2 Rl RO 0 0
then the
o 0
U9 U9
V9 V9

output data alignment
Y9 Y8 Y7 Y6 YS
U9 U8 U7 U6 US
V9 V8 V7 V6 V5

for 10-bit Y'U'V' is:
Y4 Y3 Y2 Yl YO
U4 U3 U2 Ul UO
V4 V3 V2 Vl VO

where the tripled U9 and V9 sign bits denote two's
complement sign extensions. The factors of 4 in
the input data format and 128 in the equations are
absorbed by the internal 9-bit (factor of 512)
right-shifting of the emerging results.
At the output of the TMC2272, invert the most
significant bits, U9 and V9, of the chrominance
components, and add 1 at Y6 of the luminance to
obtain the true CCIR Rec. 601 values.

CB = (896/255)(-0.3313(G)+0.5(B)-0.1687(R))+512
= -1.16397(G) +1.75686(B) -0.59289(R) + 512

Converting from G8R to 8-bit Full-Scale YUV

CR = (896/255)(-0.4187(G)-0.0813(B)+0.5(R))+512
= -1.47115(G) -0.28571 (8) + 1. 75686(8)) + 512

With the right coefficients and two external NOT
gates, the TMC2272 can convert video data from
8-bit full-scale (e.g., VGA) GBR components to
8-bit ful/-scale YUV components.

2-180

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2272
Table 2. 8-bit component formats and inclusive
ranges:
Range
Color Space Term
Format
0-255
Y
Luminance
mCillnitude
128 to
2's comp
Color difference,
U
-127
Blue
0-255 magnitude
U'
U + 128
2s comp
V
Color difference,
128 to
-127
Red
0-255
magnitude
V'
V + 128
magnitude
G,B,R Green, Blue, Red 0-255
com..Qonents
As in the previous RGB to YCBCR case, begin
with the defining equations, but without the range
compensation factors of 255 / 876 and 255 / 896:
Y = 0.5870 (G) +0.1140 (B) +0.2990 (R)
U = -0.3313 (G) +0.5000 (B) -0.1687 (R)
V = -0.4187 (G) -0.0813 (B) +0.5000 (R)
The TMC2272 will compute Y, U, and V directly,
whereas inverting the most significant bits of U and
V (U7 and V7 will yield U' and V', respectively.
Multiplying the equations immediately above by
512 and rounding each coefficient to the nearest
integer yields the recommended set of coefficients
for GBR to YUV conversion.
512 (Y) = 301 (G) +58 (B) + 153 (R)
12D
03A
099
512 (U) = -170 (G) +256 (B) -86 (R)
100
3AA
356
512 (V) = -214 (G) -42 (B) +256 (R)
100
32A
3D6

dec.
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dec.
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dec.
hex

If the TMC2272 input data alignment for 8-bit GBR
is:
0 0 0 o G7 G6 G5 G4 G3 G2 G1 GO
0 0 0 o B7 B6 B5 B4 B3 B2 B1 BO
0 0 0 o R7 R6 R5 R4 R3 R2 R1 RO
then the
o 0
U7 U7
V7 V7

output data alignment
0 0 y7 Y6 Y5
U7 U7 U7 U6 U5
V7 V7 V7 V6 V5

for 8-bit
Y4 Y3
U4 U3
V4 V3

YUV is:
Y2 Y1 YO
U2 U1 UO
V2 V1 VO

where the quintupled U9 and V9 sign bits denote
two's complement sign extensions. The factor of
512 in the equations above is absorbed by the
internal 9-bit right shift of each emerging result.
For More Information call 1-800-722-7074.

At the output of the TMC2272, invert the most
significant bits, U7 and V7, of the chrominance
components, to obtain the 8-bit offset format.
Converting From YCBCR to GBR
Following the notation employed earlier, the
TMC2272 will be used to convert data in Y'U'V'
format into GBR format.
Since Y' = 876, U' = V' = 0, and G = B = R = 255
for saturated white output, every "Y'" coefficient
be 255 / 876 = 0.29110. The full analog matrix for
Y'U'V' to GBR conversion is:
G = 0.29110 (Y') -0.09794 (U') -0.20324 (V')
B = 0.29110 (Y') +0.50431 (U')
R = 0.29110 (Y') +0.39901 (V')
Since the largest element is just over 0.5 and the
largest permissible coefficient is 511, multiply all
elements of the matrix by 512 to obtain the values
to load into the TMC2272:
G = 149 (Y') -50 (U') -04 (V')
095
3CE 398
B = 149 (Y') +258 (U')
095
100
R = 149 (Y') +204 (V')
095
OCC

dec.
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dec.
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dec.
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Decrease the incoming luminance at the input to
the TMc2272 by 64 by adding 1's at positions Y9,
Y8, Y7, and Y6. Invert U9 and V9 and their sign
extensions, to accommodate CCIR Rec. 601 data.
Instead of reducing Y by 64, an alternate is to
reduce each of the G. B. and R outputs by
(255) (64/ 876) = 19.
For the Y'U'V' to RGB conversion, the TMC2272
input data alignment for 10-bit Y'U'V' is:

o 0 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO
U9 U9 U9 U8 U7 U6 U5 U4 U3 U2 U1 UO
V9 V9 V9 V8 V7 V6 V5 V4 V3 V2 V1 VO
where the tripled U9 and V9 sign bits denote two's
complement sign extensions. The TMC2272
output data alignment for 8-bit GBR is then:

Raytheon Semiconductor

2-181

TMC2272
o
o

0
0

0
0

000

o
o
o

G7 G6 G5 G4 G3 G2 Gl GO
87 86 85 84 83 82 81 80
R7 R6 R5 R4 R3 R2 Rl RO

Converting From 8-bit Full Scale YUV to GBR
Following the notation employed earlier, the
TMC2272 will be used to convert data in 8-bit YUV
format into 8-bit G8R format.

G

256 (Y') -88 (U') -83 (V')
100
3A8
349
8 = 256 (Y') +454 (U')
100
lC6
R = 256 (Y') +359 (V')
100
167
=

dec.
hex
dec.
hex
dec.
hex

For the YUV to RG8 conversion, the TMC2272
input data alignment for 1O-bit Y'U'V' is:

o Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Yl YO
U9 U9 U8 U7 U6 U5 U4 U3 U2 Ul UO
V9 V9 V8 V7 V6 V5 V4 V3 V2 Vl VO

Since Y = 256, U = V = 0, and G = 8 = R = 255 for
saturated white output, every "Y" coefficient will be
255/255=1.0. The full matrix for YUV to G8R
conversion is:

where the doubled U9 and V9 sign bits denote
two's complement sign extensions. The TMC2272
output data alignment for 8-bit G8R is then:

G = 1.0 (Y) -0.3443 (U) -0.7142 (V)
8 = 1.0 (Y) + 1. 7727 (U)
R = 1.0 (Y) + 1.3965 (V)

o o
o o
o o

Since the largest element is over 1.0 and the
largest permissible coefficient is 511, multiply all
elements of the matrix by 256 to obtain the values
to load into the TMC2272:

0
0
0

o
o
o

G7 G6 G5 G4 G3 G2 Gl GO
87 86 85 84 83 82 81 80
R7 R6 R5 R4 R3 R2 Rl RO

Note that the inputs have to be doubled because
the coefficient gain is 256, whereas the internal
gain is 1 1512, for a net gain of 1/2.

Ta bl e3. S ummaryof Colorspace Conversion Coefficients
Conversion
KAX KAY KAl
K8X K8Y K8l

KCX KCY KCl

RG8 to YUV

099 3AA 100

120 356 32A

03A 100 306

RGBto YC8CR

083 3B4 OEl

102 36B 344

032 OEl 30B

YUV to RGB

100 100 100

000 3A8 lC6

167 349 000

YCBCR to RGB

149 149 149

000 3CE 102

acc

.
Ta bl e 4. ConverSlon Port A sSlgnments
an dA'hgnments
Port
AIN
BIN
CIN

398 000

XOUT

YOUT

lOUT

RGB to YUV

R7-0

G7-0

B7-0

Y7-0

U7-0 (e)

V7-0 (e)

RGBto YCBCR

R7-0

G7-0

B7-0

Y9-0

U9-0 (e)

V9-0 (e)

YUV to RGB

Y8-1 (e)

U8-1 (e)

V8-1 (e)

R7-0

G7-0

87-0

YCBCRto RG8

Y9-0

CB9-0 (e)

CR9-0 (e)

R7-0

G7-0

B7-0

where Xy-O denotes right-justified, (e) denotes sign extension, and XY-l denotes shifted orne bit leftward
from right-justified position.

2-182

0
0
0

Raytheon semiconductor

For More Information call H300·722·7074.

TMC2272
HSV (HSI) Format Conversions

One may use two 64Kx8 ROM look-up-tables to calculate
Hue and Saturation from R-Y and B-Y in an 8-bit system.
However, the finite size of this LUT may limit performance,
especially if the TMC2272's full precision is used. The
TMC2330, developed to translate betwe~n rectangular
and polar coordinates, can perform the trigonometric
transformations to 16 bit precision at 25M Hz. These
calculations are the the same as required in HSV
calculations. A 4 Giga-byte x 32 bit LUT can achieve the
same accuracy and precision as the TMC2330, if it is
programmed correctly.

HSV (or HSI) refers to Hue (color) Saturation (vividness) and
Value (intensity or brightness). quantities which are directly
related to the human perception of light and color. The V
(or I) levels are simply the Y (or luminance) levels. Hue and
Saturation are derived from the R-Y and B-Y color
difference values of a signal.
HSV Calculations:
Value (V) =Intensity (I) =Y
Hue (H) =Arctan (B-Y/R-Y)
Saturation (S) =-V(R-y)2 + (B-y)2
R-Y = S * cos(H)
B-Y = S * sin(H)

To convert between Y, R-Y, B-Y and HSV, the the TMC2272
isn't needed at all; simply use the TMC2330. To convert
between HSV and any other format, use the TMC2330 to
translate between HSV and Y, R-Y, B-Y, and use the
TMC2272 to translate between Y, R-Y, B-Y and the other
format. See Figures 9 and 10.

Figure 9. Conversion to HSV
Xll • 0 (Y)

ANY DESIRED {:((1111: 00))
COLORSPACE

>

/

)

/

,12 "
Yll _0 (R.V)

12~
TMC2272
12

C(11-O)

"
...

12

...

XRINI5_0 "
/
'12

~

/
12

RXOUT15 10·0

NOTE 1 ...

L
'12

NOTE 1

"

v

"...

S

"

TMC2330
Zll_0(8.V)

YPOUTI510·0

YPINI5 • 0 "
'12

Notes:

EQUALIZING PIPELINE
DELAY, 22 CYCLES
3XTMC2011

NOTE 1

NOTE 1 "

.L

/
'12

-"
"

H
24047A

1. Connect TMC2272 MSBs (Bits 11) to TMC 2330 MSBs (Bits 15) and also to TMC2330 Bits 14-11. Connect TMC2272 LSBs (Bits 10-0) to TMC2330 LSBs (Bits 10-0).
TMC2330 output bits 14-11 are overflow.
2. TMC2272 Y11-0 outputs should not be confused with the designation "Y" used to signify the intensity components. The assignment of components to TMC2272 inputs
and outputs may be altered through the selection of appropriate coefficients.

Figure 10. Conversion from HSV

v)
12
XRINI5 ·0

S

>

NOTE 1

/
12

"...

I

EQUALIZING PIPELINE
DELAY, 22 CYCLES
3XTMC2011

xll •0

All •0 "

...

'12
RXOUTI5, 10·0

"

(Y)

(R· V)

12

811 • 0 ...

Yll •0
TMC2272

NOTE 1

y

/
12

y

12

I

,,-

>

"
...
...

ANY
>COLORSPACE

TMC2330
YPINI5 • 0

"

H

NOTE 1
Notes:

12

RXOUTI5, 10·0

(8· V)

Cll • 0

Zll·0
I

NOTE 1

12

12

">
"-

24048A

1. Connect input MSBs (Bits 11) to TMC2330 MSBs (Bits 15( and also to TMC2330 Bits 14-11. Connect input LSBs (Bits 10-0) to TMC2330 LSBs (Bits 10-0).
2. TMC2272 Y11-0 outputs should not be confused with the designation 'Y' used for an intensity component. Component assignment depends on the coefficients used.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-183

TMC2272
Input Interpolation/Output Decimation and Filtering
In some applications the two color-difference signals
(R-Y/B-Y or Gr/Gb, for example,) are transmitted at one-half
the rate of the luminance (Y) signal. These two colordifference signals are often multiplexed to one signa!
which is at the same sample rate as the luminance signal.
In many applications, if the color difference signals are
already band-limited, it is satisfactory to use the same
color difference sample for each two luminance sa~ples.
Little improvement is obtained with a sim~le averagl~g
([A+Bl!2) interpolation filter. If the color difference signal
is not band-limited, either of these two methods may Yield
unsatisfactory results due to aliasing. In this case, a TRW
TMG2242 digital low-pass ("half-band") interpolating filte.r
will correctly band-limit each color difference signal as It IS
interpolated. See Figure 11.

The same methods are used to decimate the color
difference outputs. Simple decimation by removing every
other sample of color information may yield unsatisfactory
results due to aliasing. This is a problem because the color
difference signals have now been transformed with the
higher-bandwidth luminance signals and therefore have
higher bandwidths than they had before the trans.form.
The best performance is obtained by uSing a precise lowpass ("half-band") decimation filter such as the .
TDG2242 to remove aliasing components. See Figure 12.
The TMC2242 is a bi-directional, selectable rate filterl
interpolatorIdecimator

Figure 11. Input Interpolation and Filtering
....

LUMINANCE ')
(Y)INPUT

12 '"
Cr

NOTE I,

/
Cr+Cb
xMSPS

7

v-

NOTE 1 ,

....

Cb

/
xl2MSPS
CL
Notes:

TMC2242 LOW PASS
FILTERIINTEPOLATOR,
1:2 MODE

A11 ·0
xMSPS

v-

'12

811 • 0 t...

Cr

TMC2272
xMSPS

12

DE·MUX

v-

'12

12

xl2 MSPS

NOTE 1 t...

)

..I\,

EQUALIZING PIPELINE
DELAY, 60 CYCLES OR
TMC2242 IN 1:1 MODE

12 0-y

TMC2242 LOW PASS
FILTERIINTEPOLATOR,
1:2 MODE

Cb

, C11 • 0 t...

/
xMSPS

v-

'12

K> xMSPS

24049A

1. Width of input paths will vary with source.
2. See TMC2242 Datasheet for further information.

Figure 12. Output Decimation and Filtering
X11 • 0

(Y)

t...

12
V11 • 0

(Cr)

/

TMC2272
xMSPS

12

'"

....
..

EQUALIZING PIPELINE
DELAY, 60 CYCLES OR
TMC2242 IN 1:1 MODE

TMC2242 LOW PASS
FILTERIINTEPOLATOR,
1:2 MODE

xMSPS

,

t...

12

v

(Cr)

7
xl2MSPS

LUMINANCE
(V) OUTPUT

12

xMSPS It...
DE·MUX

Z11·0

(Cb)

/

1\

xMSPS

12

t...

TMC2242 LOW PASS
FILTERIINTEPOLATOR,
1:2 MODE

...

(Cb)
xl2MSPS

12

12

Cr + Cb OUTPUT

) (MULTIFLEXED COLOR
DIFFERENCE)

v

A

eLK
xMSPS

2-184

24050A

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2272
Pin Assignments -121-Pin Plastic Pin Grid Array H5 Package
Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Al
A2
A3

X7
X9
XlO
GNO
Cll
Cs
C7
C5
C3
Cl
Bl0
B7
B4
X4
X5
Xs
Xli

B5
B6
B7
BS
B9
Bl0
Bll
B12
B13
Cl
C2
C3
C4
C5
C6
C7
CS

GNO
C9
C6
C4
C2
Bll
B9
B6
B2
Xl
X2
X6
VOO
GNO
ClO
GNO
VOO

C9
Cl0
Cll
C12
C13
01
02
03
011
012
013
El
E2
E3
Ell
E12
E13

Co
BS
B5
B3
Bl
Yll
Xo
X3
ClK
Bo
Al0
Y9
YIO
GNO
All
A9
AS

Fl
F2
F3
Fll
F12
F13
Gl
G2
G3
GIl
G12
G13
HI
H2
H3
Hll
H12

Y7
Ys
VOO
A7
A6
A5
Y5
Y6
GNO
A3
A2
A4
Y4
YO
VOO
GNO
AO

H13
Jl
J2
J3
Jll
J12
J13
Kl
K2
K3
Kll
K12
K13
Ll
l2
l3
l4

Al
Yl
Y2
GNO
KAS
CWSEll
CWSELo
Y3
Zo
Z3
KA4
KA7
KA9
Zl
Z4
Z6
GNO

l5
l6
l7
lS
19
LlO
Lll
Ll2
Ll3
Ml
M2
M3
M4
M5
M6
M7
MS

KCo
GNO
VOO
KBo
KB4
KBS
KAI
KA5
KA6
Z2
Z7
Z9
Zll
KC2
KC4
KC6
KC9

M9
Ml0
MIl
M12
M13
Nl
N2
N3
N4
N5
N6
N7
NS
N9
Nl0
NIl
N12
N13

KB2
KB5
KB9
KA2
KA3
Z5
Zs
ZIO
KCl
KC3
KC5
KC7
KCs
KBI
KB3
KB6
KB7
KAO

A4

A5
A6
A7
AS
A9
Al0
All
A12
A13
Bl
B2
B3
B4
Note:

Pin 04 has no electrical connection. It is a mechanical orientation pin.

© © © © © © © © © © © © ©
© © © © © © © © © © © © ©
11
© © © © © © © © © © © © ©
10 © © ©
© © ©
©©©
©©©
7 © © ©
6 © © ©
5 © © ©
4 ©©©
©©©
3 ©©©©©©©©©©©©©
2 ©©©©©©©©©©©©©
1 ©©©©©©©©©©©©©

13

12

ABC 0 E F G H

J

K L M N
21041A

For More Information call 1-800·722·7074.

Raytheon Semiconductor

2·185

TMC2272
Ordering Information
Product
Number
TMC2272H5C
TMC2272H5C-l
TMC2272H5C-2

Speed
MHz

Temperature Range

Screening

Package

Package
Marking

30
36
40

STD-TA = O°C to 70°C
STD-TA = O°C to 70°C
STD-TA = O°C to 70°C

Commercial
Commercial
Commercial

121 Pin Plastic PGA
121 Pin Plastic PGA
121 Pin Plastic PGA

2272H5C
2272H5C-l
2272H5C-2

40006753 Rev B 8193

2-186

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2301
TMC2301
CMOS Image Resampling Sequencer
15,18 MHz

Description

Features

The TMC2301 is a VLSI circuit which supports image
resampling, rotation, rescaling and filtering by generating
input bit plane, interpolation coefficient lookup table, and
output bit plane memory addresses along with external
multiplier-accumulator control signals. The TMC2301
can process data fields of up to 4096 x 4096 multibit
words at a clock rate of up to 18 MHz. An IRS-based
system can nearest-neighbor resample a 512 x 512
image in 15 milliseconds, translating, zooming, rotating,
or warping it, depending on the transform parameter set
loaded. A complete bilinear interpolation of the same
image can be completed in 60 milliseconds. Image
resampling speed is independent of the angle of
rotation, degree of warp, or amount of zoom specified.

•

A high performance, TMC2301-based system can
execute bilinear and cubic convolution algorithms that
rotate images accurately and in real time. Keystone or
other perspective correction, image plane distortion, and
numerous other second order polynomial
transformations can be programmed and executed
under direct user control. Direct access to the
interpolation coefficient lookup table allows dynamic
modification of the algorithm.
Following an initialization with the transform parameters
and control bits defining the operation to be executed,
the IRS assumes control of the input and output data
fields and executes unattended. Data word size is user
selectable. All inputs except INTER and all outputs are
registered on the rising edge of clock. All outputs are
three-state controlled except ACC, CZERO, END, and
DONE.
Fabricated in a 1 micron CMOS process, the
TMC2301 operates at clock rates of up to 18 MHz
over the full commercial (0 to 70°C) temnperature at
15 MHz over the extended (-55 to +125OC)
temperature and supply voltage ranges. All signals
are TTL compatible.

For More Information call 1-800-722-7074

Rotation, warping, panning, zooming, and
compression of images in real time
18 MHz clock rate
4096 x 4096 image field addressing capability
User-selectable nearest-neighbor, bilinear
interpolation, and cubic convolution resampling
algorithms
Static convolutional filtering of up to 16 x 16 pixel
windows
Single-pass or two-pass convolution operations
Low power consumption CMOS process
Single 5V power supply
Available in a SS-pin grid array and low-cost plastic
leaded chip carrier (J-bend)

•
•
•
•
•
•
•
•

Applications
•
•
•
•

Video special-effects generators
Image recognition systems, robotics
Artificial intelligence
High-precision image registration (LANDSAT
processing)
High-speed data encoding/decoding
General purpose image processing
Image data compression

•
•
•

Logic Symbol
lOR

"

WEN

'"

12

::r

8

/

4

.....

12

.....

83• 0

P11 ·0

>

ClK

'~"

INIT

~

./
12 .....

.I

U11 • 0

END

UWRI

/

ACC

INTER
NOOP

.....

,

Raytheon Semiconductor

DONE

t
2-187

TMC2301
Table 3. Parameter Registers Binary Format (Row or Column Sequencer)
Addr.

Format

0000·

MSB
211 210 29

28

27

26

25

24

23

22

21

LSB
20

0001·

211 210 29

28

27

26

25

24

23

22

21

20

0010

26

23

22

21

20

2-1

2-2

2-3

2-4 2-5

0011
(ControO
0100

ALR AIN PIPE RIC Ml MO

0101
0101·
(TM. FOY)
0110
0111
0111·
(Kernel)
1000

25

24

212 211

210 29

2-7 2-8

2-9

2-10 2-11 2-12

28

2-3

2-4 2-5 2-6
-27 26

25

24

23

22

TM 22

21

20

2-1

2-2

2-3

2-4 2-5 2-6

2-7

2-8

2-9

2-10 2-1 1 2-12

_27 26

25

24

23

22

23

22

21

20

21

128-2-12 007F.FFF
-128
FF80.0oo

OX/DUo

128-2-12 oo7F.FFF
-128
FF80.oo0

OX/DVO

XMIN
XMAX

Xc

20

20
Kernel

2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-10

1001
1010

-23
2-9

22 21
20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8
2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-10

1011
1100

-23
2-9

22 21
2-10 2-11

1101
1110*

-23 22
211 210

21
29

20
28

2-1 2-2
27 26

2-3
25

2-4
24

2-5
23

2-6
22

2-7
21

2-8
20

1111*

211

29

28

27

25

24

23

22

21

20

210

Name

27

2-1 2-2

21

Umits
Dec
Hex
4095
FFF
000
0
4095
FFF
000
0
4096-2-5 OFFF.F8
-4096
FOOO.OO

20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8
2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20

26

8-2-20
-8

0007.FFFFF 02X/DU2V

8-2-20
-8

0007.FFFFF
FFF8.0oo00

02X/DU2

8-2-20
-8

0007.FFFFF
FFF8.00000

02X/DV2

4095
0
4095
0

FFF
000
FFF
000

UMIN
UMAX

* unsigned binary notation
A "-" indicates MSB is sign bit
Intarnal Bit Mapping 1MC2301 (For parametric inputs integers in table are bits of P the input point)
212 211

XoUT[11:0] 11
l'ADNlt:4,
i\MAiI. }\MIN 11
5 4
X(J
llll(UU, llll(U\

~~~~v'

210

29

29

27

26

25

24

23

20

9

8

7

6

5

4

3

22
2

21

10

1

0

IV

9

~

~

~

4

~

l

1

U

~

l

1

I
U

11

10

~

~

7

~

5

4

7

~

5

4

3
11

l
10

9

U
B

7

2-1 2-2 2-3
I

6
~

1 lU
6

5
l

2-4 2-5

2-6

2-7

2-8

2-9

4
v

3

2-10 2-11

2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20

4
1
8

U

~

7

~

~

5

4

i3

Z

1

11

Iv

1
"

B

7

6

5

4
1

3

2

1

f)2X/DV2

2-188

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

0

TMC2301
Functional Block Diagram
XO, .c.'s

INTEGER 1---4_+1
SOURCE
ADDRESS
GENERATOR

WRITE'
ENABLE

FRACTIDNHHI-+I

REGISTER
ADDRESS

4

PARAMETER
DATA IN

12

SOURCE
AOORESS
INTERPOLATION
COEFFICIENT
ADDRESS

WALK COUNT
CONTROL WORO
AND TRANSFORM
PARAMETER
STORAGE REGISTER

XMIN
I--f"'X:::M:.,::AX"+I LIMITS

UMIN
I--If."U",MA""X'+!LlMITS

INPUT IMAGE
BOUNDARY
COMPARATOR

1------+-- ~~~~:

TARGET
ADDRESS
COUNTER

TARGET
AODRESS

14'-----------+---+--- ~:/~LUMN

ClK
INITIALIZE

TARGET
WRITE ENABLE

CONTROL
INTERCONNECT:
NEXT ROW/COLUMN
NOOP

t------------+---+---+ ACCUMULATE
L _____.J----==--------if-----:::::±=-.~~~~SFORM

TARGET
OUT ENABLE

Pin Assignments - 68 Pin Grid Array, G8 or H8 Package
K J H G FED C B A
Pin

Name

Pin

Name

Pin

Name

Pin

Name

B2
Bl
C2
Cl
02
01
E2
El
F2
Fl
62
61
H2
Hl
J2
Jl
Kl

INIT
OETA
INTER
END
DONE

K2
12
K3
L3
K4
L4
K5
l5
KS
lS
K7
l7
KO
LO
K9
19
110

Ul0
Ull
UWRI
ACC
CZERO

Kl0
Kll
Jl0
Jll
Hl0
Hll
610
611
FlO
Fll
El0
Ell
010
011
Cl0
Cll
Bll

Xl
X2
X3
X4

Bl0
Al0
B9
A9
BO
AO
B7
A7
BS
AS
B5
A5

Ps
P5
P4
P3
P2
Pl
Po
ClK
6No

B4

BO
Bl
B2
B3
WEN

Uo
Ul
U2
6ND
U3
U4
U5
Us
U7
Uo
U9
6ND

CAo
CAl
VDD
6ND
CA2
CA3
CA4
CA5
CAs
CA7
Xo
6ND

For More Information call 1-800-722-7074.

Xs
Xs
X7
Xo
6ND
X9
XlO
Xll
Pll
Plo
P9
Po
P7

A4
B3
A3
A2

3
4

~~) ~~~:
,"'~\

f"~\

'- ... ' ' ... ../

c:; ()

5
6 ~~~~ (~)
7 ~:~) ()

Top View
Cavity Up

8 C) C;I
9

~:) ~:~~ L -_ _ _ _ _ _-'

VoD
NooP
LOR

Raytheon Semiconductor

2-189

TMC2301
Pin Assignments

43
42
41
40
39
38
37
36
35
34
33
32

UlO 61

Un 62
UWRI 63

ACC64
ClERO 65
CAO 66
CA, 67

Von 68
GNO
CA2
CA3
CA4
CA5
CAB

I

5
6

CA7

7

Xo
GND

8
9

WEN
83
82
8,
80
LOR
NOOP
VOD
GND
eLK
Po
P,

31 P1
30
29
2B
17

I'

J

P3
P4
P5
P6

~~~~TITITInTInnIT~

68 Leaded IJ Bendl Plastic Chip Carrier - L1 or R1 Package

Functional Description
General Information
The IRS is a versatile self-sequencing address generator
designed primarily to filter a two - dimensional image or
to remap and resample it from one set of Cartesian
coordinates lx, yl into a new, transformed set lu, vi.
Most applications use two identical devices in tandem,
one generating the row coordinates IX and UI, the other
generating the column coordinates IY and VI. The
algorithm performed by the TMC2301 consists of two
steps: a coordinate system transformation, followed by
pixel interpolation. Interpolation is necessary when the
transformed pixel positions IU, VI do not coincide with
the original pixel positions IX, YI. The new pixel intensity
values are obtained by interpolating the original pixels in
the neighborhood of the transformed pixel positions. See
Figure 1.
The IRS executes a general second order coordinate
transformation of the form:
Xlu, vl=Au 2 +Bu+ Cuv+Dv2+Ev+F
Ylu, vi =Gu 2 + Hu + Kuv+Lv2 + Mv+ N
where A through N are user - defined parameters. It
steps sequentially through the pixels of a user - defined
rectangle in the new set of coordinates, computing the
"old" address IX, YI corresponding to each "new"
location IU, VI.
2-190

The TMC2301 uses the external multiplier - accumulator,
connected to the system clock, to calculate the interpolated pixel value by summing the products of the
original pixel values stored in the source buffer RAM and
the appropriate weights from the polynomial transform
lookup table. The new interpolated image value is then
stored in the corresponding IU, VI memory location.
Finally, the new image address is incremented by one
pixel in the "U" direction or reset to the start of the
next line Iwith "V" incremented!. proceeding
line - by -line through the entire destination image.
The TMC2301 can support any nearest neighbor, bilinear,
or cubic resampling, according to the user's requirements.
The bilinear and cubic kernels require a coefficient
lookup table and multiplier - accumulator. Both one - pass
and two - pass algorithms are supported. Sophisticated
"walkaround" algorithms implementing static filters are
also easily realized, utilizing convolutional kernels of up to
16 x 16 pixels. Both one and two - pass algorithms are
supported. For each output point in a typical static
single - pass filter, the IRS will generate a series of
addresses, "walking" around that point in two
dimensions. At the end of each walk, it will advance one
pixel along the output scan line, then begin the walk for
the next pixel.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2301

u_

Figure 1. Image Resamp6ng Geometry Showing Image Rotation and Expansion
x_ _

ORIGINAL (SOURCE) IMAGE

.....

10.01.

... --.r
--

(0.0)

:;.~.-.- -

~
./

~

NEW ITARGEn IMAGE

v

.~.:

::.

.
I
/
?
·
fA .........·
.

.

/NEWPIXEL

/"

NOTE 1 , . , . /
~.

+ @t
-- - -:--;:----.(UO'Voi"~-/ .
. -......... ..........
NOTE 2
• •

.

. .
.

/J --: -:-. .................

.. .. . . . . .t . .. .. .. .. ..

Notes:

..........

.

........

.

1. Coordinate transformation
U. V pixel mapped into
X. Y coordinates.
2. Pixel interpolation walk
new U. V pixel intensity
calculated from surrounding
X. Y pixel neighborhood.

' -. . .

,.
'.

. . ' . "....

A basic TMC2301-based system is shown in Figure 2. In this
typical system, two Image Resampling Sequencers process the
image. The only other external parts needed are a

multiplier - accumulator, external interpolation coefficient lookup
table RAM, and the user-specified Source and Destination
Image Memory.

Figure 2. Basic 2-D Image Convolver Using TMC2301 Image Resampling Sequencer Utilizing Typical 8-Bit Data Path
IMAGE DATA IN

12
INITIALIZATION
OATA

L L

~

IRS
RDW
(X)

~

CDNTRDL l............., ,-

-----+

INTER

/

1-/

ACC

r-- END /\ CA7-0

SOURCE
IMAGE
BUFFER
RAM

SDURCE
ADDRESS

UWRI
Ull-0

~

,24~

12L
Xll-0

r-----,

r---

4K x 4K WORDS
MAXIMUM
IMAGE SIZE

~

I ~DDRESS

X

ACC
CLK- ~X. V. P

~

INTERPDLATION
COEFFICIENT
BUFFER RAM

r-- -v'

I

8

...
v

TMC2208
8x8
MAC

V

DOUT
8UADDRESS

--+
'-

~

INTER
END

~:LUMN

v

,

Yll-0

(V)

/\
CLOCK "-

CA7-0

I

Vll-0

r--r---

1/
12

UWRI

'--

r-----"
24

~
/DESTINAlION~
ADDRESS

tl

DESTINAliON
IMAGE
BUFFER
RAM

4Kx4KWORDS
MAXIMUM
IMAGE SIZE

~

IMAGE DATA OUT

For More Infonnation call 1-600-722-7074.

,Raytheon Semiconductor

2-191

TMC2301
Signal Definitions

WEN

The registered Write Enable input allows the
transformation parameters to be written into the
preload register indicated by the address at the
B input port when lOW. See Figure 4.

lOR

The data held in all transformation parameter
preload registers is latched into the storage
registers when the registered input lOR is
HIGH. When lOR is lOW, the parameters
remain unchanged. See Figure 4.

ACC

The accumulation register of the external
multiplier-accumulator is initialized b~ the
registered ACC output. ACC goes lOW for one
cycle at the start of each interpolation "walk,"
effectively clearing the storage register by
loading in only the new first product. See
Figure 9.

Power
VOO, GNO

The TMC2301 operates from a single +5V
supply. All pins must be connected.

Clock
ClK

The TMC2301 has a single clock input. The
rising edge of ClK strobes all enabled registers.
All timing specifications are referenced to the
rising edge of ClK.

Inputs
Pll-0

The coordinate transformation parameters are
loaded through the registered 12-bit P input
port. Pll is the Most Significant Bit.

B3-0

The write addresses for the individual coordinate
transform parameters are presented at the
registered 4-bit B input port. B3 is the Most
Significant Bit.

UWRI

After the end of each interpolation "walk," the
Target Memory IU or VI Write Enable goes lOW
for one clock cycle. See Figure 9. This
registered output is forced to the high
impedance state when OETA is HIGH.

Xll-0

The current X lor YI source pixel address of the
image being resampled is indicated by the
registered 12-bit Xll-0 output bus. This output
is forced to the high impedance state when
NDDP is lOW. X11 is the Most Significant Bit.

INTER

CAl-O

The current interpolation kernel coefficient
lookup table address is indicated by the
registered 8-bit CAl -0 output bus. This output
is forced to the high impedance state when
NOOP is lOW. CAl is the Most Significant Bit.

In the common two -device system
configuration, the Interconnect inputs are
connected to the END flag outputs. The END
flag from the row IXI sequencer thus indicates
an "end of line" to the column IYI device, while
the column sequencer in turn sends a "bottom
of frame" signal to the row device, forcing a
reset of the address counter.

NOOP

The Clock is ave ridden when the registered
input NOOP is LOW, holding all address
generators in their current state. Also, the
output buffers for the address busses X11-0
and CAl -0 are forced to the high impedance
state. This allows the user access to all external
memory. When NOOP goes HIGH, normal
operation resumes on the next clock cycle.

oETA

The target memory outputs UWRI and address
bus U11-0 are in the high-impedance state
when the registered Output Enable input is
HIGH. When OETA is LOW, they are enabled on
the next clock cycle.

Outputs

Ull-0

The U lor VI target address of the image being
generated is indicated by the registered 12 - bit
U11-0 output bus. This output is forced to the
high impedance state when OETA is HIGH. U11
is the Most Significant Bit.

Controls
INIT

2-192

The control logic is cleared and initialized for
the start of a new image transformation when
the registered INIT input is HIGH for a minimum
of two clock cycles. Normal operation begins
after INIT goes lOW.

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TMC2301
Flags
The registered CZERO flag of a horizontal
dimension TMC2301 goes HIGH if X< 0,
XMIN~X~XMAX, or X;;;;'4096 (1000
hex). It goes LOW if O~X< XMIN or
XMAX < X< 4096. The logical AND of the
CZERO flags of a two-dimensional pair of
TMC2301s will go LOW when the source
address falls outside a rectangle with
vertices (XMIN, YMINL (XMAX, YMINL
(XMIN, YMAXL and (XMAX, YMAXL
denoting an invalid address. The external
data path can be wired to substitute a
selected background value whenever this
AND=o.

CZERO

END

The registered END flag goes HIGH during
the last pixel of the last walk m a row In
the case of the row chip, and the last pixel
of the last walk in a column in the column
chip, in the two - device architecture. This
output is used as the end - of -Ime and
end - of - frame indicator in conjunction
with the INTER inputs of both TMC2301s.

DONE

In the standard two-device system, a row
sequencer DONE flag HIGH after the last
walk at the end of the last row of an
image (during UWRI LOW) indicates the
end of the transform. This registered output
is usually ignored on the column device.
See the Transformation Control Parameters,
AUTOINIT.

Package Interconnections
Signal
Type

Signal
Name

Power

VOO
GNO

Supply Voltage
Ground

L5, A6
F2, Kl, K6, Ll0, FlO, 86

36,68
1,9, 18,35, 52, 60

Clock

CLK

System Clock

A7

34

Inputs

Pll - 0

Parameter Register Oata

010,011, Cl0, Cll, 811, 810,
A10, 89, A9, 88, A8, 87

Parameter Register Address

A3, 83, A4, 84

22, 23, 24, 25, 26, 27
28, 29, 30, 31, 32, 33
42,41,40,39

Source Address

Ell, El0, Fll, Gll, Gl0, Hll
Hl0, Jll, Jl0, Kll, Kl0, L9
K9, L8, K8, L7, K7, L6, K5, L4
L2, K2, Jl, J2, Hl, H2,

83

Outputs

°
Xl l -O
CA 7

°

Ull - 0

Function

Coefficient Address
Target Address

G8, H8 Package Pins

Gl, G2, Fl, El, E2, 01
Controls

INIT
NOOP
WEN
LOR
ACC
OETA
UWRI
INTER

Flags

CZERO
ENO
OONE

For More Information call 1-800-722-7074.

Initialize
No Operation
Parameter Write Enable
Lead Parameter Oata Registers
Accumulate
Target Memory Output Enable
Target Memory Write Enable
Interconnect
Coefficient Zero
End of Row/Page
End of Transform

82
85
A2
A5
L3
81
K3
C2
K4
Cl
02

Raytheon Semiconductor

L1, R1 Package Pins

21, 20, 19, 17, 16, 15,
14,13,12,11,10,8·
7,6, 5,4,3, 2, 67, 66
62,61, 59, 58, 57, 56,
55, 54, 53, 51, 50, 49
44
37
43
38
64
45
63
46
65
47
48

2-193

TMC2301
Transformation Control Parameters
The TMC2301 is a self -sequencing device which requires no
cycle - to - cycle intervention from the host system. To program
the device, the user loads the 16 operating parameters, which
define the transformation to be performed, which sections of
the original and resampled image spaces are to be utilized, and
various control words. Filtering operations are further defined
by thB values the user loads into the external coefficient
memory. The transform parameters are described below. See
also Tables 1 through 3.

dX/dUO

Is the initial horizontal partial first derivative
indicating the displacement along the X axis
which corresponds to each one -pixel movement
along the U axis. Usually, 0 < dX/dUO < 1
corresponds to magnification, whereas
dX/dUO > 1 represents reduction and
dX/dUO < 0 denotes reflection about a vertical
axis. The first derivatives are expressed in 8-bit
integer, 12-bit fraction two's complement
notation.

XMIN, XMAX, These four parameters outline the "source"
YMIN, YMAX rectangular region of the original image.
Whenever the IRS pair generates an IX, Y)
address within this boundary the CZERO flags
will denote a valid memory read. In the most
common case, XMIN < XMAX, YMIN < YMAX,
OOOh < X< FFFh <, and OOOh < Y< FFFh. In
this case, addresses out - of - bounds cause one
or both CZEROs to go LOW. Refer to Application Note TP - 38 for further information on
other boundary violation cases. Each parameter
is expressed in 12 - bit unsigned binary integer
notation. See Figure 12.

dX/dVO

Is the initial horizontal-vertical partial first
derivative. It indicates the displacement along
the X axis corresponding to each one-pixel
movement along the V axis. The coefficients
dX/dVO and dY/dUO define image rotation and
shear.

dY/dUO

Is the initial vertical- horizontal partial first
derivative. It indicates the displacement along
the Y axis corresponding to each one - pixel
movement along the U axis.

dY/dVO

Is the initial vertical partial first derivative. It
indicates the displacement along the Y axis
corresponding to each one - pixel step along the
V axis. Since dX/dUO and dY/dVO are separate
parameters, vertical magnification and reflection
need not match their horizontal counterparts.

UM IN, UMAX, These four parameters outline the "target"
VMIN, VMAX region of the lu, vi plane, into which the
resampled image will be written. The IRS will
generate, line by line, a scan that fills only this
portion of the plane, permitting the user to
assemble a mosaic of multiple rectangular
sub images. Care must be taken to ensure that
UMAX > UMIN and VMAX > VMIN. Each
parameter is expressed in 12-bit unsigned
binary integer notation. See Figure 12.

IXo, YO)

2-194

These are the coordinates of the first pixel to
be read from the original image. In many
applications, this point will be one of the four
corners of the original image to be resampled.
The pixels near IXO, YO) in the original image
will be used to compute the upper left pixel of
the transformed image. In non -inverting,
non-reversing applications IXO, YOI will be the
upper left corner of the original subimage. Each
coordinate is expressed in 13-bit integer plus
5-bit fraction, two's complement notation.

NOTE: For each incremental move along the U axis, the
starting point of the new "walk around spiral" is indexed to
the ENDING point of the previous walk around spiral, rather
than to its center. Therefore, the terms dX/dUO and dY/dUO
must be adjusted accordingly. Since each new line is
referenced back to the previous line's initial spiral starting
point, no similar dXldVO or dY/dVO correction is needed.
Is the second order horizontal derivative. It
indicates the rate of change of the horizontalhorizontal first derivative with each step along a
line in the output image space. All six
second -order derivatives are 4-bit integer,
20-bit fractional two's complement parameters.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2301
Is the second order horizontal-vertical-vertical
derivative. It indicates the rate of change of the
horizontal-vertical first derivative with each step
down a column in the output image space.
Is the second order vertical-horizontalhorizontal derivative. It indicates the rate of
change of the the vertical- horizontal first
derivative with each step along a line of the
output image space.
Is the second order vertical derivative. It
indicates the rate of change of the verticalvertical first derivative with each step down a
column of the output image space.

element kernel in one direction, then for a Ik + 11 element
kernel in the other direction. For kernel sizes exceeding 2 x 2,
the two - pass algorithm is obviously beneficial, requiring 2n
samples per output point instead of n x n. In this case, the
intermediate image data stored in the destination image
memory following the first pass is used as the source image
data on the second pass. The user may design his system to
switch source and destination memory bank addresses in place,
or could utilize a second TMC2301 pair in a pipelined
architecture. This would require a third image buffer for the
final destination image. Both devices of a system pair are
usually set to the same mode.
Kernel

Is the mixed second order derivative indicating
the rate of change of the first order horizontal
derivative as one proceeds downwards through
the output image space. This is also the rate of
change of the first order horizontal-vertical
derivative during horizontal sweeps in the output
image space.
Is the mixed second order derivative indicating
the rate of change of the first order vertical
derivative as one moves horizontally across the
output space, or, equivalently, the rate of
change of the first order vertical- horizontal
derivative as one moves vertically in the output
image space.
Row/Column
Select

Sets the mode to either Row 101 or Column 111
operation.

Mode

This 2-bit control word defines three unique
instructions:

Code

Instruction

00, 01
10

single - pass operation

11

pass 2 of two - pass operation

Field of View As the device walks through its kernel
IFDVI
coefficients, each corresponding step in lx, yl
space is normally one pixel length or height;
this is a field of view of 1. However, the user
can subsample the original space before filtering
or resampling, by applying the coefficient kernel
over a view field of up to 7 units. At a field of
view of F, the pixels selected for each kernel
operation are F pixels apart. This is useful in
oversampled pictures, whose intensity changes
only slowly from pixel to pixel.
Autoload
IALRI

When set to 1 IHIGHI, the LOR control is
automatically asserted when INIT is strobed,
loading the coefficient set currently stored in the
preload registers.

Autoinit
IAINI

At the end of an image, if the AIN bit is 1
IHIGHI the DONE flag goes HIGH for one clock
cycle and a new transform begins. If 0 ILOWI,
UWRI and the DONE flag remain HIGH during
the sequence until the user strobes the INIT
control to begin a new image transformation.

pass 1 of two - pass operation

In single -pass operation, the device walks through the entire
Ik + 11 x Ik + 11 kernel for each output pixel, where k is the
value written into the Kernel section Isee belowl of the
parameter register. Two - pass operation, which requires a
dimensionally separable kernel, is executed first for a Ik + 11

For More Information call HlOO-722-7074.

The effective kernel width Iheightl exceeds this
4-bit unsigned number by 1, thereby providing
kernels of 1 x 1 to 16 x 16 source pixels per
output, for either resampling or filtering. Simple
static filters can be implemented with kernels of
up to 16 x 16 pixels IKernel ~ 151, while
resampling interpolation kernels are limited to
4 x 4 pixels IKernel ~ 31, due to the four bits
of fractional X lor YI address generated by the
TMC2301. See the Applications Discussion,
below. Again, both devices in a pair are
generally initialized with equal Kernel values.

Raytheon Semiconductor

2-195

TMC2301
Pipe
IPIPEI

Adjusts the timing of the target memory write
controls, to compensate for buffered source
image RAM. If the PIPE bit is 1 IHIGHI, outputs
ACC and UWRI will be delayed one clock cycle
relative to the generation of the target address
IU or VI. See Figure 9.

Test Mode
ITMI

This mode is available for user inspection of the
coefficient data. The source image and
coefficient addresses are calculated by an
internal 28 - bit accumulator. When TM is
1 IHIGHI, the sign bit, normally discarded, and
the lower 11 bits of internal data are
substituted for the upper 12 bits appearing at
the source address port IXI during a standard
transform cycle. This allows user verification of
algorithm mathematics during debug. Since the
TM bit is registered and cannot be changed
during a single clock cycle, two distinct clock
cycles are required to access both the MSW
and LSW of the internal accumulator.
See Figure 3.

Table 1. Parameter Registers - Row Sequencer
Address

0000
0001
0010
0011
0011
0100
0101
0101
0110
0111
0111
1000
1001
1010
1011
1100
1101
1110
1111

Name

Description

XMIN

left side of Source Window

XMAX

Right side of Source Window

Xu (LSW)

Source starting point - X coordinate

Xo (MSW)

Source starting point - X coordinate

Controls

Mode Select Bits

dX/dUO (LSw)

Row/Row first differential

dX/dU O(MSW)

Row/Row fllst differential

TM, FOV

Test Mode, Field of View

dX/dVO (LSW)

Row/Column first differential

dX/dVO (MSW)
Kernel
d2X/dUdV (LSWI
d2X/dUdV (MSW)

Row/Column first differential
Resampling/Filtering Kernel

~X/dU2 (LSW)
d2X/dU2 (MSWI
d2X/dV2 (LSWI
d2X/dV2 (MSWI

Row second differential

UMIN

Left edge of Final Image

UMAX

Right edge of Final Image

Mixed second differential
Mixed second differential
Row second differential
Row/Column second differential
Row/Column second differential

Figure 3. Test Mode Data Routing
Table 2. Parameter Registers - Column Sequencer

SIGN

Address

Name

Description

12

11

INTERNAL
ACCUMULATOR

CA7_4

WALK COUNTER ~--I----'''''''---f-'''''~ CA3-0

8

2-196

4

0000
0001
0010
0011
0011
0100
0101
0101
0110
0111
0111
1000
1001
1010
1011
1100
1101
1110
1111

YMIN

Top of Source Window

YMAX

Bottom of Source Window

YO (lSWI
YO (MSw)

Source starting point - Y coordinate

Controls

Mode Select Bits

Source starting point - Y coordinate

dY/dUO (LSWI

Column/Row first differential

dY/dUo (MSWI
TM, FOV

Column/Row first differential

dY/dVO (lSWI

Column/Column first differential

Test Mode, Field of View

dY/dVO (MSW)

Column/Column first differential

Kernel
d2Y/dUdV (lSw)
d2Y/dUdV (MSw)

Resampling/Filtering Kernel Size
Mixed second differential
Mixed second differential

d2Y/dU2 (lSW)
d2Y/dU2 (MSW)
d2Y/dV2 (lSWI

Column/Row second differential

d2Y/dV2 (MSW)

Column second differential

Column/Row second differential
Column second differential

VMIN

Top edge of Final Image

VMAX

Bottom edge of Final Image

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2301
Table 3. Parameter Registers Binary Format (Row Or Column Sequencer)
Addr

Format

Limits

MSB

LSB

Dec

Hex

0000'

211

210

29

28

27

26

25

24

23

22

21

20

4095
0

FFF
000

0001'

211

210

29

28

27

26

25

24

23

22

21

20

4095
0

FFF
000

0010

26

25

24

23

22

21

20

2- 1

2-2

2- 3

2- 4

2- 5

4096-2- 5
-4096

OFFF.F8
FOOO.OO

128-2- 12
-128

007F.FFF
FF80.000

128-2- 12
-128

007F.FFF
FF80.000

8-2- 20
-8

0007.FFFFF
FFFB.OOOOO

8-2- 20

0007.FFFFF
FFFB.OOOOO

0011
0011

_212

211

210

29

28

27

ALR

AIN

PIPE

RIC

M1

MO

2- 1

2-2

2- 3

2- 4

2- 5

2- 6

2- 7

2- 8

2- 9

2- 10

2- 11

2- 12

-27

26

25

24

23

22

21

20

2- 5

2-6

2- 7

2- 8

2-9

2-10

2- 11

2-12

-27

26

25

24

23

22

21

20

(Control)

0100
0101
0101'
(TM, FDV)

TM

22

21

20

0110

2- 1

2-2

2-3

2-4

0111
23

22

21

20

1000

2- 9

2- 10

2- 11

2- 12

2- 13

2- 14

2- 15

2- 16

2- 17

2- 18

2- 19

2-20

1001

-2 3

22

21

20

2- 1

2-2

2- 3

2-4

2- 5

2- 6

2- 7

2-8

1010

2- 9

2- 10

2- 11

2- 12

2- 13

2- 14

2- 15

2- 16

2- 17

2- 18

2- 19

2-20

0111'
(Kernel)

-8
1011

-2 3

22

1100

2- 9

Z-10

21

20

Z-1

2- 2

2-3

2-4

2- 5

2- 6

2- 7

2- 8

Z-11

2- 12

2- 13

2- 14

2- 15

2- 16

2- 17

2- 18

2- 19

2-20

1101

-2 3

22

21

20

Z-1

Z-2

Z-3

2-4

2- 5

2- 6

2- 7

2- 8

1110'

211

210

29

28

27

26

25

24

23

22

21

20

1111'

211

210

29

28

27

26

25

24

23

22

21

20

8-2- 20
-8

0007.FFFFF
FFFB.OOOOO

4095
0

000

4095
0

FFF
000

FFF

• unsigned binary notation
A "-" indicates MSB is sign bit

For More Information call 1-800·722·7074.

,Raytheon Semiconductor

2·197

TMC2301
Operation of the Transformation Parameter
Registers
Numerous applications require the ability to update the
coordinate transformation parameters "on the fly: ,
Because the parameters are double - buffered, the user
can load any or all of them into the preload registers
without upsetting the operation in progress. Then LOR
(load data registersl will update all transform parameters
to the new values simultaneously. This feature is
particularly valuable for "pin cushion" and "fish eye"
transformations, or polar - to - rectangular conversions,
which cannot be performed with constant second
derivatives. The Autoload function updates the preload
registers at the beginning of a new image automatically.
See the Transformation Control Parameters section. Note
also that data can be loaded in to the registers while
NOOP is active (LOWI.

Figure 4. Operation of LOR Control for Parameter
Update

ClK")---+----------'

Figure 5. Timing Diagram

b:~~
"," t=,.::i. t;;= \ 1"""'-----"\------JI
INPUTS

@XXXXXXXXXXXXXX. . .__XX
b=tS-ltH(I)~
00i<
mx>®K

rtD(EI--j
_ _ _----J{

--1tHD~

VALID

)OO(------VA-L-IO---XX

---l rtHO(E)
I ~'-----

Noles
1 IS and 10iEI are guaranleed !O allow full speed operation In Ihe standard two-device architeclUre. See text.
2. All outpulS except END. See lexl

2-198

Raytheon Semiconductor

For More Information call 1-800-722·7074.

TMC2301
Figure 6. Equivalent Input Circuit

Figure 7. Equivalent Output Circuit

Voo

voo
n SUBSTRATE

01

01

"""'V--.........

CONTROL <>----....
INPUT

. . . . - -....-0

OUTPUT

02

03
P WELL

P WELL

.,.. GNO

.,.. GNO

Figure 8. Transition Level for Three-State Measurement

ClK
THREE-STATE
OUTPUTS 1

W

Note:

f:Y\ ______-'

1. All outputs except CZERO, ACC, END and DONE.

Absolute maximum ratings Ibeyond which the device may be damagedl 1
Supply Voltage ........................................................................................................................................................................................................................................ - 0.5 to +7.OV
Input Voltage ................................................................................................................................................................................................................................ -0.5 to (YOO +0.5)V
Output
Applied voltage 2 .............................................................................................................................................................................................. -0.5 to (VOO +0.5)V
Forced current 3,4 ..................................................................................................................................................................................................... -1.0 to +6.0mA
Short-circuit duration (single output in HIGH state to ground) ......................................................................................................................................... 1 sec
Temperature
Operating, case .......................................................................................................................................................................................................... -60 to + 130°C
junction ....................................................................................................................................................................................................................... 175°C
Lead, soldering 110 secondsl .....................................................................................................................................................................................•...........•...

moe

Storage ........................................................................................................................................................................................................................ -65 to + 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3.

Forcing voltage must be limited to specified range.

4. Current

IS

speCified as conventional current flowing Into the device.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-199

TMC2301
Operating conditions
Temperature Range
Parameter

Min

Standard
Nom
5.0

Voo

Supply Voltage

4.75

Vll
VIH

Input Voltage, logic LOW
Input Voltage, Logic HIGH

2.0

10l
10H

Output Current, Logic LOW
Output Current, Logic HIGH

TA
TC

Ambient Temperature, Still Air
Case Temperature

Max

Extended
Nom

Min

5.25

4.5

Max

5.0

0.8

Units

5.5

V

O.B

V
V

B.O
-4.0

rnA
rnA

125

°c
°C

2.0
B.O
-4.0

0

70
-55

DC characteristics within specified operating conditions 1

Test Conditions

Parameter
1000
100U

Supply Current, Quiescent
Supply Current, Unloaded

VOO
VOO

~

IlL
IIH

Input Current, Logic LOW
Input Current, Logic HIGH

VOO
VOO

~

VOL
VOH

Output Voltage, Logic LOW
Output Voltage, Logic HIGH

Voo
VOO

~

lOll
10ZH
lOS

Hi - l Output Leakage Current, Output LOW
Hi-l Output Leakage Current, Output HIGH
Short - Circu~ Output Current 1

VOO ~ Min, VIN ~ OV
VOO ~ Min, VIN ~ VOO
VOO ~ Max, Output HIGH, one pin to ground,
one second duration max.

CI
Co

Input Capacitance
Output Capac~ance

TA
TA

~
~

~

~

~

Temperature Range
Standard
Extended
Max
Min
Max
Min
5
75

Max, VIN ~ OV
Max, f ~ 15MHz
Max, VIN
Min, VIN

~

OV

~ VO~

Min, 10l ~ Max
Min, 10H ' Max

25°C, f
25°C, f

~
~

lMHz
lMHz

-10
-10

+10
+10

-75
-75

0.4
2.4
-40
-40

5
75

rnA
rnA

+75
+75

/l A

0.4
2.4

+40
+40
-100

10
10

-40
-40

Units

+ 40
+ 40
-100

10
10

/l A

V
V
/l A
/l A

rnA

pF
pF

Notes:
1. Actual test conditions may vary from those shown, but guarantee operation as specified.
2. Guaranteed but not tested.

2-200

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2301
AC characteristics within specified operating conditions
Temperature Range
Standard

Extended

-1

Parameter

Test Conditions

Min

Max

Min

Max

Min

Max

Units

tCY

Cycle Time

VOO ~ Min

55

66

66

ns

tpWL

Clock Pulse Width LOW

VOO ~ Min

25

30

30

ns

tpWH

Clock Pulse Width HIGH

VOO ~ Min

25

30

30

ns

IS

Input Setup Time 1

18

20

20

ns

tH

Input Hold Time

2

2

2

ns

tHIll

Input Hold Time, INTER

10

10

10

ns

to

Output Delay 2

VOO ~ Min, CLOAO ~ 40pF

27

35

35

ns

tOlE)

Output Oelay, END 1

VOO ~ Min, CLOAO ~ 10pF

37

45

45

ns

tHO

Output Hold Time 2

VOO ~ Max, CLOAO ~ 40pF

5

5

5

ns

tHOlE)

Output Hold Time, END

VOO ~ Max, CLOAO ~ 10pF

10

10

10

ns

tOiS

Three - State Oisable Delay

VOO ~ Min, CLOAO ~ 40pF

tENA

Three - State Enable Delay

VOO • Min, CLOAO ~ 40pF

18
27

20
35

20
35

ns
ns

Notes:
1. ts

+

tOlE) • tCY max.

2. Excluding output pin END.

Applications Discussion
Basic Operation

Each TM C2301 pair contains address controllers which execute
patterns much like the following FORTRAN 3-level nested DO
loop:
1. The inner loop is a clockwise outgoing spiral "walk" through
the N-element coefficient kernel.
2. The middle loop is a left - to - right "scan" along each row
of the output image space.
3. Finally, the outer loop is a top - to -bottom "scan" down
each column of the output image space.
A typical one - pass image transformation proceeds as follows:
1. The device pair outputs the addresses IXO, YOI, which is the
first point in the source image, and ICAX, CAYI, the
interpolation lookup table address for the first pixel in the
kernel. The output ACC goes LOW, causing the external
accumulator to IQad the first product without summation,

For More Information call 1-800-722-7074.

clearing the accumulator.
2. For the next N cycles, the IRS walks through an outward
clockwise spiral in lx, yl space, accumulating
pixel-interpolation coefficient products. The spiral sequence
is depicted in Figure 9.
3. After the completion of the first spiral walk, the IRS outputs
the target address of the first pixel, IUMIN, VMINI and the
control UWRI, along with the initial IX, YI values of the next
spiral walk. ACC and UWRI can be delayed by one clock
cycle by setting the control bit PIPE to 1 IHIGHI, simplifying
the task of interfacing the TMC2301 to buffered source
image memory.
4. After the last cycle of the next spiral, UWRI again goes
LOW for one clock, and the target address outputs are
updated, pointing to the location of the pixel calculation just
completed, IUMIN + 1, VMINJ.

Raytheon Semiconductor

2-201

TMC2301
after (UMAX + 1, VMINI will be (UMIN, VMIN
followed by (UMIN + 1, VMIN + 11, etc.

5. The third spiral walk begins with ACC going LOW, and ends
with (UMIN + 2, VMINI output and UWRI going LOW.
6. he procedure continues until (UMAX + 1, VMINI is reached,
at which point the device resets to U (position within rowl
and increments V (number of rowl. Thus, the next (U, VI set

+

11,

7. Upon completion of the walk corresponding to
(UMAX + 1, VMAX + 11, the TMC2301 will generate a
DONE flag with the final UWRI, and begin a new sequence.

Figure 9. liming Diagram and Pixel Map Showing Outward Clockwise Spiral Walk Generated by TMC2301
(2 x 2 Kernel Shown)

•

•

•

_.

•

.

@

•
•

~

•

.-.

•

•

•
•

•

ClK

X. Yll-0

==x

==x
I

CA7_0

X
X

X
X

X
X

==::xI
I
1\

U, Vll-0

{ NXT'

PIPE = 0

PIPE = 1

\

,~ I

\

{
_

/

I

UWRI

I
I
\

UWRI

X
X

I-

X
X

>C
>C

I
I
\

I

NEW U, V

I

I

X
X

NEXT WAlK-"

I

I
\

\

Notes:
1. Assumes that OETA is LOW and NOOP is HIGH.
2. Timing Parameters are not shown on this diagram.

2-202

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2301
On any given clock cycle, the actual IX, Yl and IU, VI
outputs of the IRS are given by the following equations:
x=xo + dX/dUo*m +dX/dVO *n + dZX/dUdV*m*n
+dzX/dUz*lm z - ml/Z +dzX/dVz*ln z - nl/Z o
+ FOV*CAXlw! + FOV*m*CAXIKerl
y =Yo + dY/dUo *m + dX/dVo *n + dZY/dUdV*m*n
+dzY/dUz*lm z - ml/Z + dZY/dVz*ln z - nl/Z o
+ FOV*CAYlwl + FOV*m*CAYIKerl
u=UMIN+m
v=VMIN+n

where FOV is the 4 - bit field of view parameter,
normally set to 1 so that the spiral walk proceeds in
single - pixel steps. Setting FOV to 4 would expand the
spiral walk, allowing the user to trade two bits of image
size for two bits of additional interpixel positioning
resolution. CAXlwl and CAYlwl are the current value of
the coefficient address outputs, and CAXIKERI and
CAYIKERI are the terminal values of each pixel walk. The
CAIKERI terms arise because the IRS computes each
new walk's starting point from the previous spiral walk's
end point, rather than its starting point.

Interpolation Coefficient Lookup Table Addressing
The external coefficient lookup table RAM stores the
interpolation values used to calculate the value of the
new pixel. These values are selected by the user,
allowing maximum filtering flexibility. In simple filtering
applications, all 8 bits of coefficient address are available
to access up to 256 interpolation coefficients, for kernels
of 16 x 16 pixels. This address is generated by the
internal walk counter of the TMC2301. In most
applications, the same Kernel parameter value is selected
in both IRS devices; thus, the Coefficent Address outputs
CA7 _ 0 for the X and Y devices are identical, and the
user needs only one of the 8 - bit buses for memory
access.
Applications executing a coordinate transformation,
however, will almost always generate non - integer
source pixel addresses; that is, the U lor VI locations will
not map to the X lor Yl addresses exactly, and fractional
address components are generated. The user then must
account for this spatial offset in both dimensions by
storing the appropriate corrected interpolation kernel
values in the lookup table. The 8 - bit address bus is
broken up into two parts: the fractional portion lupper 4
bitsl, and the walk counter 1I0wer 4 bitsl. Thus, in

For More Information call 1-800-722-7074.

resampling applications, the maximum kernel size is 4 x 4
pixels, or 16 locations. As in the filtering example,
assuming that the user has selected the same kernel size
for both IRS devices, the 4 bits of least - significant
address generated by both devices wil! be identical, and
redundant. The four most significant address bits,
however, will reflect the current fractional offsets of the
resampled pixel from the nearest X IYI location, to a
spatial resolution of 4 bits, in the X lor Yl directions.
Utilization of the 12 bits Itotal! of lookup table address is
left to the user, to be arranged as desired for memory
access. See Figure 3.

Application Examples
One of the more common applications for the TMC2301
is simple static filtering. In this case the source and
target memories locations are identical and no coordinate
transformation is performed. The IX, Yl and IU, VI
outputs listed in Table 4 show the address sequencing
generated by the TMC2301 to execute the walk of a
5 x 5 pixel interpolation kernel. The normalized
coefficients shown implement a first - order Butterworth
Low Pass Filter with cutoff radius of 1/.J2. Note that the
IU, VI output address is updated following the completion
of the walk for that location.

Figure 10. Pixel Map Showing Walk Sequence for
5 x 5 Static Filter

.

10.0)

21

22

23

24

2°f-·-~-:-:

19f 6f-:-:-1
1°f
17t

5t,--lJ1~F--i
:-;---2

r.

• . - - • .....-- • 4 - - e + - - .

16

'Raytheon Semiconductor

15

14

13

12

2-203

TMC2301
Table 4. IRS Outputs for Static Filter Illustrated in
Figure 10
Cycle

X

V

Index (CA)

Coefficient

U

V

1
2
3
4
5
6
1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

3
4
4
3
2
2
2
3
4
5
5
5
5
4
3
2
1
1
1
1
1
2
3

4
4
5
5
5
4
3
3
3
3
4
5
6
6
6
6
6
5
4
3
2
2
2
2
2
4

0
1
2
3
4

0.2176
0.0725
0.0435
0.0725
0.0435
0.0725
0.0435
0.0725
0.0435
0.0198
0.0212
0.0198
0.0128
0.0198
0.0212
0.0198
0.0128
0.0198
0.0212
0.0198
0.0128
0.0198
0.0272
0.0198
0.0128
0.2115

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

4

5
4

5
6
1
8
9
10
11
12
13
14
15
16
11
18
19
20
21
22
23
24
0

However, we have included a linear compression factor of 5:1,
and must accommodate the fact that each time u is
incremented, the start of the new walk is referenced to the
END of the previous walk. Given these corractions, the rotation
matrix becomes:

dX/dUO = 5cos(al = 3
dX/dVO = -5sin(al = -4
Kernel = 1

dY/dUO = 5sin(aHDV
dY/dVO = 5cos(al = 3

=

3

Figure 11. Pixel Map Showing Parameters for 63° Rotation
and 5:1 Compression Listed in Table 5
(0, Ol.

.

UO, OJ

{20,DI

4

4
4
4
4
4
4
4
4
4
4

\

Figure 11 illustrates the sequence for a bilinear resampling of a
63° rotation. The starting point is translated + 1 in the
Y-direction. A common rotation matrix might be:

dXldUO = cos (al = .6
dX/dVO = ~sin (al = -.8

2·204

dY/dUO = sin (al = .8
dY/dVO = cos (al = .6

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2301
Table 5. IRS Outputs for Operation Illustrated in Figure 11
Cycle
1
2

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

X

y

Index

U

V

5
6
6
5
8
9
9
8
11
12
12
11
14
15
15
14
1
2
2
1
4
5
5
4
7
8
8
7
10
11
11
10
0

5
5
6
6
9
9
10
10
13
13
14
14
17
17
18
18
8
8
9
9
12
12
13
13
16
16
17
17
20
20
21
21
15

0
1
2
3
0
1
Z
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0

4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
5
5
5
5
6

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6

6
6
6
7
7
7
7
8

right corner of the transformed image is located at
IUMAX + 1, VMAX + 11; the location of the corresponding
corner of the original image depends on the values of the
derivatives. Not to be confused with IXO, YOI, the points
IXMIN, YMINI and IXMAX, YMAXI define the "usable"
rectangular portion of the original image; points IX, YI lying
outside this region are ignored in most resampling and filtering
applications. This feature permits one to construct a mosaic of
several abutting subimages in the lx, yl plane, without danger
of edge effect interference between adjacent subimages. Note
in the figure that the upper left and lower left corners of the
original image lie outside the admissible region; in practice, the
values fetched at these locations will not be included in the
convolutional sums.

Figure 12. Pixel Maps Demonstrating Source and
Destination Image Boundaries and Image Clipping
(Note Shaded Areal

'-

ClERO

lOW

..

IXMIN. YMINI

IXMIN, YMAX) •

"-

,

IXMAX. YMAXI

v

!

(UMIN. VMIN)

Figure 12 may help clarify the relationships among IXO, YOI,
IXMIN, YMINI, IXMAX, YMAXI, IUMIN, VMINI, and
iUMAX, VMAXI. With positive first derivatives, IXO, YOI and
IUMIN, VMINI represent the upper left corners of the original
image and the new destination field, respectively. The lower

IUMAX. VMAXI

Note:

For More Information call 1-800-722-7074.

=

Assume OOOh < X< FFFh
OOOh < Y< FFFh

Raytheon Semiconductor

2-205

TMC2301
Example B. PIPE =1

Application Note
Nearest Neighbor Operation - Additional
Timing Details
Example A, PIPE =0
Inspecting Figure 201 :
PIPE =0, KER =0 (near neighbor), AUTOIN =1 (on),
UMN =0, UMX =5, VMN =0, VMX =5,
DXlDU =1, DYIDV =1, XO =0
First rising edge of elK after IN IT falling edge is #C.
Rabie entries are events after listed clock rising edge.
END, DONE flags =0, except where shown as 1.
UWRI goes low and remains low with elK #2.
elK

x u v ~~

DON Comments

R C

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
35
36
37
38
39
40
41

0
1 0 0
2 1 0
3 2 0
4 3 0
5 4 0
6 5 0
0 6 0
1 0 1
2 1 1
3 2 1
4 3 1
5 4 1
6 5 1
0 6 1
5 4 4
6 5 4
0 6 4
1 0 5
2 1 5
3 2 5
435

42
43
44
45
46
47

5
6
0
1
2
3

2-206

4
5
6
0
1
2

5
5
5
0
0
0

0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1

o

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

0
0
0
0
0
1

0 1
0
0
0
0
0

first clock after IN IT falling edge
first valid X addresses = XO
second X; first valid U, V =UMN, VMN

Now, referring to Figure 202:
PIPE = 1, KER - 0 (near neighborl, AUTOIN = 1 (on),
UMN =0, UMX =5, VMN =0, VMX =5,
DX/DU =1, DY/DV -1, XO =0
First rising edge of ClK after INIT falling edge is #C.
Table entries are events after listed clock rising edges.
END, DONE, flags =0, except where shown as 1.
UWRI goes low with ClK #3, stays low. Otherwise, the
timing is the same as Figure 201, i.e., pipeline delays UWRI
and ACC by one clock cycle.

Bilinear Interpolation

=

Example C. PIPE 0
From Figure 203, we can see the following:
PIPE = 0, KER - 1 (bilinear), AUTOIN = 1 (on),
UMN =0, UMX =5, VMN = 0, VMX =5,
DX/DU = 1, DY/DV = 1. YO =0, XO =0
First rising edge of ClK after INIT falling edge is #0.
Table entries are events after listed clock rising edges.
END, DONE flags = 0, except where shown as 1.

END ROW flag 3 cycles before last X

END
CL~

last X of first row
last U, V or first row; first X of 2nd row
First U, V of second row
END ROW flag 4 cycles before last U, V

last X of second row
last U V of second row U =UMX + 1
END COL goes high before last X
last X of V =VMX • 1row
first X of Last (V = VMX) row
first U, V =UMN, VMX of last row
last END ROW flag of frame
END COL goes low when DONE goes
high
DONE immediately before last X
last X of frame
last U, V =UMX + 1, VMX
first U, V =UMN, VMN of new frame
first END ROW flag of new frame

0

X U V ROW UWF ACC
1 0

1
2

0

0
1

0
0

3
4
5

1
1
0

0
1
1

1
1
1

6

100

1

0

7
8
9
10
11
12
13
14
15
16
17
160
161
162
163

200
200
100
210
310
3 1 0
2 1 0
3 2 0
4 2 0
4 2 0
3 2 0
5 3 5
4 3 5
5 4 5
6 5 4

0
1
1
1
0
1
1
1
0
1
1
1
1
1
0

1
1
1
0
1
1
1
0
1
1
1
1
1
0
1

Raytheon Semiconductor

1
1
1
1

DON

Comments
1st ClK after INIT falling
edge
151 valid X address. XO:
start 1st ACCum

end 1st 2x2 kemel; end 1st
ACCum
1st valid u, v • UMN, VMN;
2nd ACCum start

2nd valid u, v = UMN + 1. VMN

3rd valid u, v. UMN + 2, VMN

end 4th 2x2 kemel

begin next-to-Iast x-walk

For More Information call 1-800-722·7074.

TMC2301
CU
164
165
166
167
168
169
170
171
172
173
174
175
176

m

END
U V ROW UWR ACC DON Comments
654
1
1
545
1
1
655
1
0
begin last x-walk
755
0
1
755
1
1
1
655
1
last x of frame
1
065
1
0
165
0
1
165
1
1
065
1
1
lastu, v = UMX + 1, VMX
100
1
0
first u, v of new frame
200
1
0
200
1
1
100
1
1

x

Performing larger Interpolation Kernels
With PIPE = 0, AUTOINIT = 1, and the following
definitions:
Txdone = Clock cycle of final X address of a transform.
Txend = Clock cycle of final X address along a row.
KER =(K + 1)(K + 1), where K is the value in the "kernel
size" parameter register.

Examples:
D. KER =0 (nearest neighbor), UMIN =0, UMAX =3,
UMIN 0, VMAX 2

=

=

If first CLOCK edge after INIT goes low is 0, then:
First x, y out (= XO, YO) appears after CLOCK edge 2.
First u, v out (= 0,0) appears after CLOCK edge 3.
END is high after CLOCK edge 13 only.
DONE is high after CLOCK edge 16.
Last x out appears after CLOCK edge 16.
Last u, v out (= 4, 2) appears after CLOCK edge 17.
E. KER =1, (1 pass bilinear), UMIN =0, UMAX =4,
VMIN 1, VMAX 3

=

=

If first CLOCK edge after INIT goes low is 0, then:
First x, y out (= XO, YO) appears after CLOCK edge 2.
First u, v out (= 0, 1) appears after CLOCK edge 6 and
remains through edges 7, 8 and 9.
END is high after CLOCK edge 92, goes low after 96.
DONE is high after CLOCK edge 100 only.
Last x out appears CLOCK edge 101.
Last u, v out (= 5, 3) appears after CLOCK edge 102
and remains through edges 103, 104 and 105.

The following relationships hold true:
First X address - valid 3 rising clock edges after INIT's
failing edge.
END FLAG - goes HIGH for KER cycles at clock cycle
Txend -1-2*KER. Otherwise stated, END
is active for one walkaround starting two
walkarounds and one cycle prior to the
final source address of a row.
DONE FLAG -goes HIGH for one cycle at clock cycle
Txdone -1. Otherwise stated, DONE is
active for one clock cycle one cycle prior
to the last source address of the final
walkaround.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-207

TMC2301
figure 201
VOO3

--

VII02
VIllI
VIIOO

UII03

uooz

- - --

- - - - -- ---

-_

..

- - - - - - - - - -. - - - - - - ---LL

----,~----------------------------------::...ri_-=-.::-:...:-=-i""!:.._-=-__-r;;;-;;...;-;;..;;;-1"-;;;-;;...;-;;..-;;;..:£...:

---- --- - - -- -- ------_ ..

-----------------

UOOI
- , - , - . - -2- - . -

uooo

5-'1 - 2' -;- - - - - -

________________________

ENDR

______________
Jr-1 -- -- - --________
----- ----_

/NIT

~--------------------

DONE

~~

________

J~~

__________

--J~~

~~L

________

__________

~r_

1II00P

ActR
UWRI

-------- -- ---- - --------

CLOK

LORC

Y003

YOO2

-

---,~------------------------------------

YOOI
YOOO
XOO3

XOO2

-- - - - - - - - - - - - - - - ---

____________________________________~r____

--T-----------,--

----------D--------~

---------- -----------

------------------

XOOI
XOOO
__________________________-J~~________

DONE
______________

~~~

________

_J~~

_ _ _ _ _ _ _ ___

________

-J~~

__________

__1rJ~

__________

.J~

ENDR
/NIT

~~------------~-------------------------

~~------------------------------------------

1II00P

ActR
UWRI

----------- ----------

CLOK

LORC

KER - 0
PIPE - 0

2-208

UMIN * 0
UMAX * 5

YMIN = 0
VMAX·5

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2301
figure 202
VII03
VOO2
IIIJOI

woo

=:::.:....:---_--.:._--:_:...::=-=-:_:...::::i·-=-=--:_:.r-;._..:-=_-=:.._r,=_-=:....:i:...:_:...:_:.._c._-=~_J--=-==.=-=-..:;..:..::..:=:.t·~:.:_:.:..:_;...:_:...;_=-~_r_=-_=-;:_:..:_:..::_Ji"C_-=-_:":-:

UII03
UOO2

------ -- - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _.

UIIOI
UGQO

- -- - - - - - - - -

DONE

----------------------------------------------------~~~-----------_ _ _ _ _--'r-,
.....
.....
...,
,.-,
M
r-"'\. _ _ _ __

£NOR

INIT
lOOP

:I

,

---

l

-

1

1

l

- - -- -

.....

1

-

--- - - - - - - - - -J

S'

1

1

II

1

- -

1

- ---

------------------------------------------------ - -- - - - - - -- -- - - - - - - - - -- - - -- - - - - - - - -- - -- - - - - - - -------------------------------------- ----------

:..,:;-

lCCR
UWRl
CLOK
LDRC

--------- -- - - --- - - - - - - - - - - - - - - - - - - - -- - - - - - - - - -

YOO3
YOO2

YOOI
YOOO

XOO3
XOO2

XOOI
XOOO
DONE

- - - - -- - - - - - - - - - - - - - -----1-----------.-.

- --

-- - - ---

-

- - -- -

~1..

-

- - - --

_ _ _ _ __

ENDR

-----------------------------------------------,.....,,.....,

INIT

~-------------------------

r-t.

,.....,

,...,

,.....,

,.....,~----

lOOP

ACCR
UWRI
CLOK
lORC

---------------------------------------------KER - 0
PIPE - 1

UMIN·O
UMAX • 5

For More Information call 1-800-722-7074.

YMIN • 0
YMAX·5

Raytheon Semiconductor

2-209

TMC2301
Figure 203
VIm
VIIIIZ
WIll
VIIIIII

IE

..
UIIII1

---------

--.i...:~=_=_~~~...:..._.__

- -- -- -- - -- - - -- -- -- i -- -- 2·-;:'

-.- -• -- -,-- .. -..=

---

-------------'~~----------------

DONE

ENDR

.rr

lOOP

ICCR
UWRI

--------~~-----

~~--------------------------------

------------------,

CLOK

YIIII3

YIIII1

I

,

,

I

,

,

,

,

,

,

,

,

,

,

,

,

,

• • • • • • • • • • 77777777

II' Z 7T 117'-'-"-1-3451.·

LORe

YIIII2

-- - - ---

-

_F~~~~~~~----

II1IIIZ

____________________________________-"r-------------------------- -- - -- - -- - -- ---

------______________

~r___~

______________

---------------

----------------~__________________'r___

Y1IIJO
XU03
XlI02

---------------------------~

X1IIII

----------------------

X1IIIII

----'~-:r~T~~---------

------------------------------

- -________________________________
- - - - - - - - - - -- - - - --__

--------------"~~----------------

UWRI

- - - - - -. - -

- - ---- - -

CLOK

__ ! J. !.

DONE

.rr

ENDR

~L

lOOP

ICCR

- - --

!. !.. 1_1_7.J .!

IL IL12..!3

- - - - - - ---

.!!. !!.,.11_p..!'

LORe
~--------KER - 1
PIPE - 0

2-210

UMIN -0
UMAX·5

¥MIN ••
¥MAX - 5

Raytheon Semiconductor

For Mora Infarmallcn call 1-800-722-7074.

TMC2301
Ordering Information
Product
Number

Temperature Range

Screening

TMC2301G8C2
TMC2301G8V
TMC2301G8Vl

STD-TA=O°C to 70°C
EXT- TC = - 55°C to 125°C
EXT- TC = - 55°C to 125°C

Commercial
MIL-STD-883
MIL-STD-883

68 Pin Grid Array
68 Pin Grid Array
68 Pin Grid Array

2301G8C2
2301G8V
2301G8Vl

TMC2301H8C
TMC2301H8Cl

STD-TA =O°C to 70°C
STD-TA =O°C to 70°C

Commercial
Commercial

68 Pin Grid Array
68 Pin Grid Array

2301H8C
2301H8Cl

TMC2301L1V
TMC2301 L1Vl

EXT-TC= -55°C to 125°C
EXT-TC= -55°C to 125°C

MIL-STD-883
MIL-STD-883

68 Leaded Hermetic Ceramic Chip Carrier
68 Leaded Hermetic Ceramic Chip Carrier

2301L1V
2301L1Vl

TMC2301R1C
TMC2301R1Cl
TMC2301R1C2

STD-TA=O°C to 70°C
STO-TA =O°C to 70°C
STO-TA =O°C to 70°C

Commercial
Commercial
Commercial

68 Lead Plastic J-Leaded Chip Carrier
68 Lead Plastic J-Leaded Chip Carrier
68 Lead Plastic J-Leaded Chip Carrier

2301R1C
2301R1Cl
2301R1C2

Package

Package
Marking

40005061 Rev G 8193

For More Information call 1-800-722-7074_

:Raytheon Semiconductor

2-211

TMC2301

2-212

Raytheon Semiconductor

TMC2302
TMC2302
Image Manipulation Sequencer
40 MHz

Description
The TMC2302 is a high-speed self~uencing VLSI
circuit address generator which supports image
resampling, rotation, rescaling, warping, and filtering. It
generates input bit plane, interpolation coeffICient lookup
table, and output bit plane memory addresses along with
pixel interpolator control signals.
Similar in architecture to the TMC2301 Image
Resampling Sequencer, the TMC2302 features
numerous enhancements. In addition to an increase in
the maximum clock rate to 40 MHz, the device offers
three-dimensional address generation and implements
two-dimensional image transformation polynomials of up
to third order.

The TMC2302 can process image data fields with up to
24 bits of binary resolution (224 pixels) per dimension,
with 0 to 16-bit subpixel resolution.
A system based on two TMC2302s can nearestneighbor resample a two-dimensional 512 x 512 pixel
image in 6.5 milliseconds, translating, rotating, or
warping it, depending on the user-selected
transformation parameters. A complete bilinear
interpolation of the sample image can be completed in
26 milliseconds, while a nearest-neighbor resampling of
a 3D image 128 pixels on a side takes only 53
milliseconds with three TMC2302s. Image resampling
speed is independent of angle of rotation, degree of
warp, or amount of zoom specified.

Simplified Block Diagram

DATl5-0 )ASYNCHRONOUS {
HOST INTERFACE

IADR 6-0
ICS
IWR

'"
"
'"

"

"

v

CONTROl
PARAMETER
REGISTERS

SOURCE
ADDRESS
GENERATOR

r-<
"
v

OES

}

SADR 23-0

SOURCE MEMORY
INTERFACE

SVAL

t

t

WALK
COUNTER

./

"

OEK
}
KADR
ACC 7·0

CONVOWTIONAL
CONTROL

TWR
NOO p"

ASYNCHRONOUS {
HOST INTERFACE

INIT

'"

CLK

'"

"

~

CONTROl

A

I

TARGET
ADDRESS
GENERATOR

I

I

./

"

T::ll~}
TVAl
END

}

TARGET
MEMORY
INTERFACE

SYNC FLAGS

DONE
65-6420

For More Information ca/11-800-722-7074.

Raytheon Semiconductor

2-213

TMC2302
Features
• Asynchronous Loading Of Control Parameters
• Rapid (25ns Per Pixel) Rotation, Warping, Panning,
And Scaling Of Images
• Three-Dimensional Image Addressing Capability
• General Third-Order Polynomial Transformations In
Two Dimensions Implemented On-Chip; ThreeDimensional Transformation Of Up To Order 1.5 Also
Supported
• Flexible, User-Configurable Pixel Datapath Timing
Structure
• Static Convolutional Filtering Of Up To 16 x 16 Pixel
(One-Pass), 256 x 256 Pixel (Two-Pass) Or
256 x 256 x 256 Pixel (Three-Pass) Windows

• User-Selectable Source Image Subpixel Resolution of
2- 8 to 2- 16
• 24-Bit (Optional 36-Bit) Positioning Precision Within
The Source Image Space, 4S-Bit Internal Precision

• Low Power CMOS Process
• Available In A 120 Pin Plastic Pin Grid Array

Applications
•
•
•
•

High-Performance Video Special-Effects Generators
Guidance Systems
Image Recognition, Robotics
High-Precision Image Registration (LANDSAT
Processing)

Functional Block Diagram
ASYNCHRONOUS
HOST INTERFACE

SADR 23.0

~

.-----.

SOURCE
ADDRESS
GENERATOR

OES
SVAL

ACC

SYNCHRONOUS
HOST INTERFACE

~
NOOP

_ ...-

INIT

TWR
.......
INTERNAL

TADR 11.0

CLOCK

OET

ClK

PROGRAMMABLE
DELAY
OTO 7CLOCKS

2

3x (12·0)

TVAL

TARGET
ADDRESS
GENERATOR

3 x 13·81TS

~----------------------------~"

t----~

END

r---~

DONE
21243A

2-214

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TMC2302
Pin Assignments - 120 Pin Plastic Pin Grid Array, H5 Package
13

12
11

10
9
7

6
5
4

3

©©©©©©©©©©©©©
©©©©©©©©©©©©©
©©©©©©©©©©©©©
© © ©
© ©©
©© ©
©©©
©© ©
©©©
TOP VIEW
©© ©
©©©
CAVITY UP
©© ©
©©©
©© ©
©©©
Key
©© © \6
©©©
© © ©© © ©© ©©©©©©
© © ©© © © © ©©©© © ©
© © ©© © © ©©©©©©©

II

'\

k

/

ABCDEFGHJKLMN
21041A

Pin
C3
B2
Bl
03
C2
Cl
02
E3
01
E2
El
F3
F2
Fl
G2

Name

Pin

VOO
SAOR15
SADR 14
GNO

G3
Gl
Hl
H2
H3
Jl
J2
Kl
J3
K2
Ll
Ml
K3
L2
Nl

VOO
SADR13
SAOR 12
GND
SAOR11
SAOR lO
SAOR 9
VDD
SADRS
SADR7
GNO

Name

Pin

Name

Pin

VOO
SADRS
SADR 5

L3
M2
N2
L4
M3
N3
M4
L5
N4
M5
N5
LS
MS
N6
M7

NC
OEK

L7
N7
NS
MS
LS
N9
M9
Nl0
L9
MlO
Nll
N12
L10
Mll
N13

SADR4
GND
SADR3
SADR2
SAORl
VDD
SADRO
SVAL
ACC
GND
VOD
GND

KAOR7
VDO
KAOR s
KAOR 5
KADR4
GND
KADR3
KADR2
KADRl
KAORO
OET
TWR
TAORO

Name

Pin

VOO
TADRl
TADR2
TADR3
TADR4
TADR5
TADRS
TAOR 7
TAORS
TAOR9
TAORlO
TAOR n
DONE
GND
ENDO

L11
M12
M13
K11
L12
L13
K12
J11
K13
J12
J13
Hll
H12
H13
G12

Name

Pin

Name

Pin

Name

Pin

Name

VOO
GND
TVAL

G11
G13
F13
F12
Fl1
E13
E12
013
Ell
012
C13
813
011
C12
A13

GNO

Cll
B12
A12
Cl0
Bl1
All
Bl0
C9
Al0
B9
A9
CS
8S
AS
87

GNO
10ATS

C7
A7
AS
BS
CS
A5
B5

IAOR 5

VDD
GND
NDOP
INIT
VOD
GND
CLK
IWR
GND
VOO
SYNC
VOO

IDATa
lDATl
GND
VDD
IDAT2
IDAT3
IOAT 4
GNO
IOAT 5
10ATs
lDAT7
VDD
GND
VDO

IDAT9
lDATlO
lDAT11
IDAT12
IDAT 13
lDAT14
IDAT 15
ICS
1ADRo
IADRl
IADR2
IAOR3
IAOR 4

A4
C5
B4
A3
A2
C4
B3
Al

IADRs
DES
SADR23
SADR 22
SADR 21
SADR 20
VDD
SADR 19
SADR1S
SAOR 17
SAOR 1S
GND
VDD
GND

Functional Description
General Information
The TMC2302 is a versatile, high-performance address
generator which can control, under user direction,
filtering or remapping of two or three-dimensional
images by resampling them from one set of Cartesian
coordinates lx, y, z) into a new, transformed set lu, v, wI.
Most applications utilize two identical devices for twodimensional, or three devices for three-dimensional,
image processing. The host CPU initializes the system by
loading the input image buffer RAM with the source
For More Information call 1-800-722-7074.

image pixel data and the TMC2302s with the image
transformation and system configuration control
parameters. These parameters are loaded by a separate,
asynchronous input clock. The IMS-based system then
executes the entire transformation as programmed,
generating a DONE flag upon completion of the
transform. The user can program the chip to repeat the
transform continuously or to halt at the end.

Raytheon Semiconductor

2-215

TMC2302
General Information (cont.)
The IMSs continuously compute the target bit plane
lu, v) or bit space addresses lu, v, w) in typical line-byline, raster-scan serial sequence. For each output pixel
address, they compute the corresponding remapped
source image coordinates, each of whose upper 24 bits
become the source bit plane addresses lx, y). An
additional lower twelve bits are available through the
target address port in the optional extended address
mode. Source image addresses may be generated at up
to 40MHz, with the corresponding target image
addresses then appearing at up to 140/k)MHz, where "k"
is the size of the interpolation kernel implemented. In
the two-device system, one TMC2302 computes the
horizontal coordinates x and u while the other generates
the y and v Ivertical) addresses. In a three-dimensional
system, one additional device would provide the z and w
(depth or time) coordinates.
To support a wide range of image transformations, the
"row" or x/u device implements a 16-term polynomial of
the form:
x = a + bu + cu 2 + du 3 + ev + fvu + gvu 2 + hvu 3 + iv 2
+ jv 2u + kv 2u2 + Iv2u3 + mv 3 + nv 3u + ov 3u2 + pv 3u3

where a through p are the user-defined image transformation parameters. The TMC2302 steps sequentially
through the pixels within a user-defined rectangle in the
target image space, computing the "old" source image
address lx, y, z) corresponding to each "new" target
image pixel lu, v, wI. User-programmable flags are
available to indicate when the source and target image
addresses have fallen outside of a defined rectangular
area, simplifying the generation of complex images or
image windows.
In the three-dimensional mode, the x/u transformation
equation is:
x = a + bu +

BV

+ kw + fuv + ivw + luw + juvw

See "The Image Transformation Polynomial" section of
the Applications Discussion .

2-216

The TMC2302 utilizes an external multiplieraccumulator or interpolator, connected to the system
clock, to calculate the interpolated pixel value for each
color. The products of the original source image pixel
values surrounding the remapped pixel location !interpolation kernel) and the appropriate weights stored in the
coefficient lookup table are summed. The resulting new
interpolated image pixel value is then stored in the
corresponding IU, V, W) memory location in the target
image memory buffer. Next, the target image address is
incremented by one in the "u" direction until UMAX is
reached lend of line). when U is reset to UMIN, and the
V counter is incremented to give the first pixel location
in the next line. The process is repeated, proceeding
line-by-line through the image, until VMAX is reached. In
the case of three-dimensional images, the IMS system
also steps through each page in the image, incrementing
in the "w" direction with the completion of each image
plane until WMAX is reached, and the transformation is
complete.
The Image Manipulation Sequencer can support any
nearest-neighbor, bilinear interpolation, or cubic
convolution resampling, according to the user's requirements. Interpolation kernels of more than one pixel
require an external interpolation coefficient lookup table
and multiplier-accumulator. One, two, and three-pass
algorithms are supported. For each output point in a
typical two-dimensional single-pass static image filter, the
TMC2302 implements a spiralling pixel resampling
algorithm, "walking" around the resampling neighborhood
in two dimensions and generating the appropriate coefficient table addresses to sum up the interpolated pixel
value in the external pixel interpolator. At the end of
each walk, the TMC2302 will advance one pixel along
the output scan line and then execute the walk for that
next pixel. When performing multiple-pass interpolation,
the TMC2302 system proceeds along only one dimension
per pass, which requires dimensionally separable, preferably orthogonal, coefficients.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2302

x_ . . . . . .

u_

Figure 1. Image Resampling Geometry Showing Two-Dimensional Image Rotation and Expansion
(XMIN, YMIN)

(UMIN" VMI~)

ORIGINAL (SOURCE) IMAGE

y•

~:

~'

,

,

,
(UMAX, VMAX)

(XMAX, YMAX)

NOTES: 1. Coordinate transformation U, V pixel mapped into X, Ycoordinates.

2. Bilinear pixel interpolation walk. New U, Vpixel intensity calculated from surrounding X, Ypixel neighborhood.

A basic, two-dimensiQnal TMC2302-based system is
shown in Figure 2. In this typical arrangement, two
Image Manipulation Sequencers process the image. The
only other components needed beyond the source and
target image buffer memories are a multiplier-

For More Information call 1-800·722·7074.

'" NEW PIXEL

21244A

accumulator or pixel interpolator such as the TRW
TMC2246 Image Mixer or TMC2250 Matrix Multiplier,
and the Interpolation Coefficient Lookup Table RAM or
ROM.

Raytheon Semiconductor

2·217

TMC23.02
Figure 2. Basic Two-Dimensional Image Convolver Using TMC2302 IMS with Typical 8-Bit Data Path
IMAGE DATA IN

INITIALIZATION
DATA

16

>

/

"
io/

:J.8

IDAT15•0
TMC2302
IDAR 6.() ROW (X)

CONTROL

1\

.---

16

{to

....

/

SOURCE """
ADDRESS .,,/

SOURCE
IMAGE
BUFFER
RAM

...

-TWR

===:-

0

-W
X

L...-

ADDRESS

~

2x 16

SADR 2
ACC

TADR ll •0
KADR7•0, SADR 7•0

I

t--

16

ACC
CLOCK

INTERPOLATION
DATA COEFFICIENT DATA
IN
BUFFER RAM OUT

8

X, Y, P
Y

TMC2246,
TMC22S0
OR SIMILAR

ADDRESS

811

~

SADR 7•0
SADR23•
IDAT1S,()

8

TMC2302
ROW(Y)

lfs

=7:

WR

DESTINATION
ADDRESS

2x24
IDAR 6•0

1\

I

TADR 11 •0

4;8

I

CLOCK

DESTINATION
IMAGE
BUFFER
RAM

21245A

IMAGE DATA OUT

Signal Definitions
Power
VDD, GND The TMC2302 operates from a single +5V
supply. All pins must be connected.

the rising edge of the Input parameter Write
clock IWR. The last parameter must be
loaded twice on two consecutive rising
edges of IWR \.

Clock

ClK

IWR

2-218

The pixel clock of the TMC2302 strobes all
internal registers except the control
parameter preload registers. All timing
specifications except those are referenced
to the rising edge of ClK.
The internal image transformation and
configuration control parameter registers
are double buffered to simplify interfacing
with system controllers. ~ending on the
state of the chip selects ICS. control words
input to IDAT1S-0 and the corresponding
addresses presented to IADRa-o are
strobed into the outer preload registers on

Inputs
IADRS-O

The input parameter preload register
currently indicated by the Input parameter
register Address IADRa-o is loaded with the
data presented to input port IDAT on the
rising edge of IWR, as demonstrated in
Figure 3.

IDAT1S-0

Configuration and transformation parameter
Input Data is presented, along with the
appropriate input register address word
IADR6-0. to the parameter Input Data port.

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For More Information call1-lI00-722-7074.

TMC2302
Inputs (cont.)
IOAT 15-0
Icontl

delayed up to seven clock cycles after the
nominal sequence shown in Table 1 by
utilization of the pipeline delay parameter
PIPTAO. For systems requiring greater
spatial resolution in the source image than
that offered by the SAOR23-0 alone, the
Target Address Port can be reconfigured to
output 12 additional LSBs of the source
address by placing the device into the
Extended mode, in which case the pipeline
delay parameter must be set to 0 to
maintain alignment with the current source
address port output. See the Device
Configuration and Control Parameters
section.

IOAT 15-0 and is latched into the preload
registers on the next rising edge of IWR.
Preload register updates are disabled by
the chip select control ICS. See Figure 3.

Figure 3. Image Transformation and Configuration
Control Parameters Register Structure
TCM2302
IDATu;.o
PRELOAD
REGISTER
IWR

TO
REST
OF
CHIP

EN

Controls

IADR~

ICS

ICS
PIXEL
CLOCK

CLK

!

Outputs
SAORno

KADR7-0

TADR11-0

The 24-bit address of one dimension IX, y.
Z) of the source image pixel value currently
being resampled is output through the
Source Address port SAOR23-0. This port
can be forced to the high-impedance state
by the enable control OES.
The integer address steps for each
dimension of the spiral interpolation walk
performed by the TMC2302, as determined
by the transform parameter KERNEL are
generated by the internal walk counter and
output at the Coefficient Address output
port KAOR7_0. This port can be forced to
the high-impedance state by the enable
control OEK.
The 12-bit address of one dimension IU, V.
W) of the target image pixel value just
resampled is output through the Target
Address Port TADR 11-0. This port is forced
into the high-impedance state by the
enable control OET. TADRll_0 can be

For More Information call 1-800-722-7074.

The input parameter preload register write
clock IWR, and thus the preloading of all
configuration and transformation parameters, is disabled on the next clock when
the registered Input parameter Chip Select
input is HIGH. When ICS returns LOW,
they are enabled on the next clock. See
Figure 3.

INIT

The TMC2302 control logic is cleared and
initialized for the start of a new image
transformation, and the internal working
registers are updated with the contents of
the current control parameter preload
registers when the registered control input
INIT is HIGH. The image transformation
then commences with the first source
image pixel address nine clocks later.

SYNC

The user can select between continuous or
one-frame operation with the registered
input control SYNC. Assuming that INIT
remains LOW and NOOP remains HIGH, if
SYNC remains HIGH at the end of a
transform the TMC2302 will begin the next
image transformation without interruption.
This assumes either that the user is not
changing the parameter set, or that a new
set of parameters has already been loaded
into the preload registers midframe, prior to
the beginning of the last line in the
transform.

Raytheon Semiconductor

2-219

TMC2302
Controls (cont.)
SYNC
(cont.I

ACC

If SYNC is LOW during the last clock cycle
of a transform, the device will complete the
image, having loaded the new transform
parameter set during the first clock of the
final line of the transform, and halt in the
state set on the first clock cycle of the
next transform. These outputs are held until
SYNC is again brought HIGH, and operation
resumes on the next clock. See Figure 5.
The external pixel interpolator or multiplieraccumlator is initialized for a new accumulation of products by the registered Accumulator Control output ACC. On the first
cycle of each interpolation walk, this output
goes LOW for one cycle, effectively clearing
the register by loading in only the first new
resampled pixel value. When performing
nearest-neighbor resampling, this control
will remain LOW throughout the entire
transform. This output can be delayed up
to seven clock cycles after the nominal
sequence shown in Table 1 by the pipeline
delay parameter PIPACC. See the Device
Configuration and Control Parameters
section.
On the last cycle of each interpolation
walk, the Target Write Enable goes LOW
for one clock cycle, returning HIGH for all
but the last cycle of the next walk. When
performing nearest-neighbor resampling,
this control will remain LOW throughout
the entire transform. This output can be
forced to the high-impedance state by the
enable control OEl and can be delayed up
to seven clock cycles after the nominal
sequence shown in Table 1 by the pipeline delay parameter PIPTWR. See the
Device Configuration and Control
Parameters section.
Assuming that INIT remains LOW, the
internal system clock of the TMC2302 will
be disabled on the next clock, halting the
current transform, when the registered
control input NOOP goes LOW. When
NOOP returns HIGH, normal operation

2-220

resumes on the next clock. This control
does not affect the loading of the configuration and transformation parameter preload
registers.
OES

The source address port SAOR23-0 is
enabled when the asynchronous output
enable OES is LOW. When OES is HIGH,
the port is in the high-impedance state.

OEK

The interpolation coefficient address port
KADR7-0 is enabled when the asynchronous output enable OEK is LOW. When
OEK is HIGH, the port is in the highimpedance state.
The target address port TADR 11-0 and
target write enable TWR are enabled when
the asynchronous Target Output Enable OET
is LOW. When OET is HIGH, these outputs
are in the high-impedance state. This
control functions in both the normal and
extended addressing modes.

Flags
SVAL

When the current source image address
component output is within the working
space defined by the parameters XMIN and
XMAX (or YMIN, YMAX for the column
(YIVI device or ZMIN, ZMAX for the page
(Z/WI device!. the Source Address Valid
flag SVAL for that device is LOW. This flag
will go HIGH on the clock in which the
corresponding component address falls
outside the defined region. In a typical
system, the SVAL outputs of all IMS
devices are OR'ed together to generate a
global boundary violation flag. The user
might then insert zeroes into the pixel
interpolator to ignore that portion of the
image outside the defined space, or insert
a background color or image. This output
can be delayed up to seven clock cycles
after the nominal sequence shown in Table
1 by the pipeline delay parameter PIPSVA.
See the Device Configuration
and Control Parameters section.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2302
Flags (cont.I
TVAL

ENDD

When the current target image addresses
are within the working space defined by
the parameters UMINI and UMAXI, and
VMINI and VMAXI land WMINI and
WMAXI for systems processing threedimensional images), the Target Address
Valid flag TVAL for that device is LOW. This
flag will go HIGH on the clock in which
the current target address outputs fall
outside the defined region, Since each
TMC2302 device is programmed with
distinct MINI/MAXI parameters and
generates a separate TVAL flag, the user
may define separate two or threedimensional target space windows for each
device, TVAL can be delayed up to seven
clock cycles after the nominal sequence
shown in Table 1 by the pipeline delay
parameter PIPTVA, See the Device
Configuration and Control Parameters
section,
During the last pixel interpolation walk of a
row IX/U device), the last row in a page
IY/V device), or the last page in a three-

For More Infonnation call 1-800-722-7074.

dimensional transform IZ/W device). the
flag ENDD goes HIGH for the entire walk,
indicating End of the transform in that
dimension, It remains LOW otherwise, This
output can be delayed up to seven clock
cycles after the nominal sequence shown in
Table 1 by the pipeline delay parameter
PIPEND, See the Device Configuration
and Control Parameters section,
DONE

On the last clock cycle of the current
image transform, the DONE flags on all
TMC2302s go HIGH for one clock cycle
On the next clock cycle, all devices output
the first addresses and control signals for
the next image transform, If SYNC is LOW,
the IMS system halts, If SYNC is HIGH,
operation continues without interruption,
See "SYNC," in the Controls section, This
flag can be delayed up to seven clock
cycles after the nominal sequence shown in
Table 1 by the pipeline delay parameter
PIPDON, Also see "PFLS;' in the Device
Configuration and Control Parameters
section,

Raytheon Semiconductor

2-221

TMC2302
Package Interconnections

2-222

Signal
Type

Signal
Name

Power

VDD

Supply Voltage

GND

Ground

Clocks

CLK
IWR

System Clock
Input Parameter Write Clock

J12
J13

Inputs

IDAT 15 _0

Input Parameter Data

IADR6_0

Input Parameter Address

Al0. C9. Bl0. All. Bll. Cl0. A12. B12.
Bll Cll Dlt Dll Elt Ell Fll G13
A7. C7. B7. AB. BB. CB. A9

Outputs

SADR23_0

Source Address

KADR7_0
TADRll_0

Coefficient Address
Target Address

Controls

INIT
SYNC
ICS
ACC
TWR
NOOP
DES
OEK
OET

Initialize
Run/Halt
Input Parameter Chip Select
Accumulate
Target Memory Write Enable
No Operation
Source Address Output Enable
Coefficient Address Output Enable
Target Address Output Enable

K12
H13
B9
Ml
N6
L13
A6
M2
M6

Flags

SVAL
TVAL
ENDD
DONE

Source Address Valid
Target Address Valid
End of Dimension
Done

Ll
M13
N13
Ll0

No Connects

NC

No Connect
Index Pin

L3
D4

H5 Package Pins

Function

Raytheon Semiconductor

C3. C2. F3. G3. J3. L2. L4. L7. L11. Kll.
Jll. H12. G12. Fll. Dll. A13. A4. B3
D3. E3. G2. H3. K3. Nl. L5. Mll. M12. L12.
K13. Hll. Gll. F12. Ell. C12. Cll. C4. Al

B6. C6. A5. B5. C5. B4. A3. A2.
B2. Bl. Cl. D2. Dl. E2. El. F2.
Fl. Gl. Hl. H2. Jl. J2. Kl. K2
N2. M3. N3. M4. N4. M5. N5. L6
N12. Nll. Ml0. L9. Nl0. M9.
N9. LB. MB. NB. N7. M7

For More Information call 1-800·722·7074.

TMC2302
Table 1. Nominal Output Signal Timing
SADRZ3_0 1

ACC

-

TADR11_0

TWR

END

DONE

X'-l,J,O

0

UL-l,M

1

X'-l,J,l

1

UL-l,M

1

0

X'-1,J,2

1

UL-l,M

1

0
0
0

X'-l,J,K

1

UL-l,M

0

1

X',J,O

0

UL,M

1

1

··
·

0
0

X',J,l

1

UL,M

1

1

X',J;2

1

UL,M

1

1

0
0
0
0

X',J,K

1

UL,M

0

1

1

·•
·

Note:

1. KADR7 -0 timing identical.

The nominal sequence of address and control signals of
a two-dimensional, single-pass-programmed TMC2302
system, with all PIPE parameters set to 0, is shown in
Table 1. Here, the values of the last two new target
image pixels UL-l M and UL M are being calculated, and
the beginning and end of the interpolation walks of
length K which sample source image pixels in the
neighborhod of locations (XI-l,J, XI J) can be seen.
Utilizing the arrival of the source image address
(SADR31-0) as a reference point, the other signals

shown can be delayed up to seven clock cycles from the
nominal timing shown here, allowing the user to
configure these outputs to match the timing latencies of
his pixel data path structure. Considerable speed and
timing variations in image buffer memory, data register,
and pixel interpolator structure can thus be accomodated,
with minimal corresponding support hardware. Also see
"PFLS;' in the Device Configuration and Control
Parameters section.

Transformation Coefficient and Configuration and
Control Parameters
The TMC2302 is intended to act as a co-processor,
requiring only that the user program the device to
perform the image transformation desired by loading in
the appropriate device configuration and transformation
control parameters discussed in this section. The user
then issues an "Init" command, allowing his system to
run unattended until the completion of the image when
a "Done" flag is generated to inform the host system.
The capabilities and flexibility of the TMC2302 Image
Manipulation Sequencer are apparent when reviewing
the following tables which define the transformation
coefficient and configuration and control parameters.
These tables are broken up into two separate groups.
The first parameters discussed are the control words
which select the dimension calculated, the functional
configuration of each device, the working space in which
they will operate, the size of the interpolation kernel
For More Infonnation call 1-800-722-7074.

desired, and the timing of the various address and
control signals involved in handling the pixel data
pipeline. The second parameters are the polynomial
transform coefficients used in performing image
manipulation. The TMC2302 utilizes three levels of
internal 48-bit accumulators to calculate these values by
forward difference accumulation, generating no significant
cumulative spatial error for most applications. The user
must be aware that all internal parameter and coefficient
registers must be set by the user, including resetting
after powerup any unused control words or coefficients.
A major difference between the TMC2302 and the
TMCZ301 is that elimination of the device interconnects.
Instead, the user programs all X, U, V, and W boundaries
into all TMC2302 devices. The system's progress through
the image is monitored by each device independently
and in parallel.

Raytheon Semiconductor

2-223

TMC2302
Transformation Coefficient and Configuration and
Control Parameters (cont.)
The boundary values are usually identical in all devices in
order to maintain synchronous operation.
As mentioned above, the TMC2302 also features userprogrammable image data pipeline configuration controls.
All output signals except the source and coefficient
address outputs can be individually delayed by the user
up to seven clocks after the nominal system timing
illustrated in Table 1. This allows the user to softwareconfigure the TMC2302s in his system to match his pixel
interpolator, image buffer, and interpolation coefficient
RAM structure timing.
The user can also program the device to continue into
the next image for a set number of clock cycles after
the Done flag has appeared. First, this "flushes" the final
resampled pixel data word through the interpolation
pipeline, all the way to the target image RAM. Also,
valid pixel data will then appear on the first clock of the
next transform independent of the length of the pixel
pipeline, incurring no lost clock cycles.

dimensional operation, pass between the periods in
which these two target address values are generated.
Thus in 20 nearest neighbor operation UMAX must be
5 greater than UMIN. In 20 bilinear interpolation mode
(4-pixel two-dimensional kernel!. the distance must be
two pixels in the target image (actually enforcing a
spacing of 8 system clocksl.
UMINI,
VMINI,
WMINI

The target image addresses corresponding
to those of the top, left side, and front
page of the 2 or 3 dimensional region
indicated by the valid target address flag
TVAL are UMINI, VMINI. and WMINI,
respectively. Thus, to define a valid region
beginning at "m;' the MINI parameter
value is "m:' These parameters are
assumed to be in 12-bit unsigned binary
integer format.

UMAXI,
VMAXI.
WMAXI

The target image addresses one more than
those of the right side, bottom and back
page of the region indicated by the valid
target address flag TVAL are UMAXI,
VMAXI. and WMAXI. respectively. Thus, to
define a valid region ending at "n;' the
MAXI parameter value is "n + 1". These
parameters are assumed to be in 12-bit
unsigned integer format.

XMIN,
XMAX

The source image boundaries are defined
for each device by the parameters XMIN
and XMAX, in the case of the row device.
The column device then contains YMIN
and YMAX, and the page device (in systems performing three-dimensional operationsl ZMIN and ZMAX. The value of
XMAX should be greater than XMIN if the
boundary violation flag SVAL is to operate
correctly. These values are assumed to be
in 32-bit unsigned binary integer format.

PFLS

The user can set the number of clock
cycles that the TMC2302 continues in to
the next image following the DONE flag,
allowing his system to Flush all control and
data pipeline paths and halt after a maximum of seven cycles. The numeric format
assumed is three-bit unsigned binary
integer.

Device Configuration and Control Parameters
UMIN,
VMIN,
WMIN

UMAX,
VMAX,
WMAX

The memory addresses of the target image
boundaries corresponding to the top, left
side, and front page of the new image
being generated are defined in all devices
of the user's system by the parameters
UMIN, VMIN, and WMIN, respectively. At
the beginning of the transformation, the
initial source image coordinate (XO, YO, Zol
will be mapped to this coordinate set. The
numeric format assumed is 12-bit unsigned
binary integer.
The memory addresses of the target image
boundaries corresponding to the bottom,
right side, and last page of the image
being generated are defined in all devices
by the parameters UMAX, VMAX, and
WMAX, respectively. These values should
be greater than the UMINIVMIN/WMIN
values defined above. Numeric format
assumed is unsigned 12-bit binary integer.

Note: The parameter UMAX must exceed UMIN so as to
ensure that a minimum of 5 system clock cycles in twodimensional operation, or 15 clock cycles in three-

2-224

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TMC2302
Device Configuration and Control Parameters (cont.)
PTAD,
PDON,
PEND,
PTVA.
PSVA,
PTWR,
PACC

As mentioned above, the control signals
and target image pixel addresses generated
by the TMC2302 can be delayed up to
seven clock cycles after the nominal timing
shown in Table 1 by setting the appropriate Pipeline delay word. The numeric
format assumed for all delay words is
three-bit unsigned binary integer.

XTND

When the user sets the control bit XTND
to 1, the TMC2302 operates in an
extended-resolution source address bus
configuration. Assuming that the user has
his own raster scan generator available
elsewhere to manage the flow of output
pixels from the TMC2302 system, the
target address output bus TADR 11-0 is
reconfigured internally into an extension of
the source address bus, as SADR11-0· The
original source address bus SADR23-0 is
then SADR35-12- providing 36 bits of
spatial resolution in the source address
space. An XTND of 0 puts the device in
the standard 24-bit source, 12-bit target
address configuration.

E3D

Setting this control bit to 0 indicates a
two-dimensional image transform is to be
performed. When the E3D is set to 1, a
three-dimensional image is assumed, using
three TMC2302 devices.

DIM

The user sets each TMC2302 to operate in
a specific dimension as follows:

MODE

DIM1.O

Dimension

00
01
10
11

X/U (Rowl Device
VIV (Columnl Device
Z/W (Pagel Device
No Dperation

In systems performing the standard twodimensional spiral interpolation walk, MODE
is set to 11, indicating single-pass operation. When performing mUltiple-pass
resampling, the user must set this two-bit
control word pass-by-pass in all IMSs, to

For More Information call 1-800-722-7074.

implement each pass direction. For instance,
setting MODE to 00 causes the TMC2302
system to increment only in the X-direction,
holding the Y (and Z) addresses constant
until the end of that pixel walk. On the
next pass through the image, the user sets
MODE = 01, with the kernel increment in Y
only. In 3D, the IMS system then proceeds
again through the (U, V) target image
space, walking kernels only along the Z
direction.
MODE1.O
00
01

10
11

Resampling Performed
X-Pass
V-Pass
Z-Pass
Two-Dimension Spiral Walk

KERNEL

This parameter determines the size of the
interpolation walk performed. To implement
a convolutional sum of K+ 1 pixels, the
parameter KERNEL is set to K, up to a
maximum of 255. In single-pass operation,
this value must be identical in all devices,
giving a square interpolation kernel. In
mUltiple-pass operation, however, nonsquare kernels may be implemented, with
different K values in each dimension. Or,
the user could utilize a banded memory
architecture in two-pass mode to access an
entire row or column of a kernel in one
clock, completing the entire sum in a single
pass through the other dimension of the
kernel. Numeric format is 8-bit unsigned
integer.

FOV

The user determines the size of each step
in an interpolation walk, in terms of the
number of source image pixels, by setting
the Field Of View control. The binary
weighting of the image transformation
parameters and source address must be
taken into account when determining this
value. See Table 6 and the Applications
Discussion section. The numeric format
assumed is unsigned 16-bit integer.

Raytheon Semiconductor

2-225

TMC2302
Table 2. Control Parameter Registers Binary Format (Row, Column or Page Device)
Addr

Format

Limits

Name

Hex MSB

LSB

UMIN

30

UMAX

31

4095

UMINI

32

4095

UMAXI

33

211

210 29

28

27

26

25

24

23

22

21

VMIN

34

211

210 29

28

27

26

25

24

23

22

21

VMAX

35

211

210 29

28

27

26

25

24

23

22

21

VMINI

36

VMAXI

37

WMIN

38

WMAX

39

WMINI

3A

WMAXI

38

4095

o

o

o

4095

o

4095

o
20

o

211

210 29

28

27

26

25

24

23

22

21

20

PTAD

40

PDON

40

PEND

40

PTVA

40

PSVA

41

PTWR

41

4095

o

4095

o

211

210 29

28

27

26

25

24

23

22

21

4095

o

4095

o
20
25

24

23

22

21

4095

o

20

20

40

4095

o

4095

26

PFLS

Dec

o

7

o
7

o
7

o
7

o
7

o

Hex
FFF
000
FFF
000
FFF
000
FFF
000
FFF
000
FFF
000
FFF
000
FFF
000
FFF
000
FFF
000
FFF
000
FFF
000
00000000

00000000

7

o
7

o
7

o
7

o
7

o
7

o

7

o

7

o

Note: Table 1 continues on the following page.

2-226

Raytheon Semiconductor

For More Information call 1-800-722·7074.

TMC2302
Table 2. Control Parameter Registers Binary Format (cont.)

Name

Addr
Hex MSB

PACC

41

XTND

41

E3D

41

DIM

41

MODE

41

KERNEL

42

FOV

43

Format
LSB

Limits
Dec Hex
7

7

o

o

XTND
E3D
DlMl

D1Mo
MODEl MODE o
255

FF
00
216 _1 FFFF
o
0000

o

Transformation Parameter Registers
The Transformation Parameter Word storage register
addresses for the X/U device are listed in Table 3, along
with the differential terms for each polynomial coefficient
for both two and three-dimensional transforms. The
polynomial terms for the other IMS devicelsl are found
by replacing every "X" in the table with a Y lor Zl. A
TMC2302-based system can perform image manipulations of up to third order in two dimensions, and threedimensional transforms of up to order 1.5 I"first-and-ahalf order"!. Also, see "The Image Transformation

Polynomial': in the Applications Discussion section.
The notation used to define each polynomial coefficient
term in Table 3 is easily interpreted. Each differential is
of course defined by a differential in X, followed by the
corresponding dependent U, V. or W terms. Thus,
DXUV is equivalent to d2X/dUdV
and
DXUUUV to d4X/dU 3dV.

Table 3. Transformation Polynomial Coefficient Register Addresses
Parameter

Coefficient Word Addresses (hex)

Name

2D Term

3D Term

A
B
C
D
E
F
G

Xo
DXU
DXUU
DXUUU
DXV
DXUV
DXUUV
DXUUUV
DXVV
DXUVV
DXUUVV
DXUUUVV
DXVVV
DXUVVV
DXUUVVV
DXUUUVVV

Xo
DXU

H
I

J
K
l
M
N
0
P
Note:

DXV
DXUV
Xo
DXU
DXVW
DXUVW
DXW
DXUW

MSW

CSW

LSW

00
03
06
09
OC
OF
12
15
18
1B
lE
21
24
27
2A
2D

01
04
07
OA
OD
10
13
16
19
lC
IF

02
05
08
OB
OE
11
14
17
1A
lD
20
23
26
29
2C
2F

22
25
28
2B
2E

The Xo and DXU terms must each be loaded into two different registers when performing 30 transforms. Table 3 shows the binary weighting of all
of the Transformation Parameter words. which are 4S-bit signed fractional binary.

For More Information call 1-800·722·7074.

Raytheon Semiconductor

2·227

TMC2302
Table 4. Integer Binary Weighting of Transformation Parameters
Format

Limits
LSB . Dec
Hex

MSB
_247

MSW

246

245

244

243 242

241

240

239

238 237

236

235

234

233 232

228

227 226

225

224

223

222 221

220

219

218

217 216

212

211 210

29

28

27

26

24

23

22

21

CSW

231

230

229

LSW

215

214

213

Note:

A minus sign indicates a sign bit

Figure 4a. Timing Diagram, Pixel Clock, Control, and
Outputs

25

20

248 _1

FFFFFFFFFFW

0

000000000000

Figure 4b. Timing Diagram, Preload Parameters
is

~7Y~

~

ClK

INPUTS!

6s.6462

OUTPUW

Value "OAT 1" is loaded InlD address "ADR 1" on lite second rising edge of
IWR. since JCS =0, having been acquired by lite input register on Ihe first
edge.

21247A

Figure 6. Equivalent Output Circuit

Figure 5. Equivalent Input Circuit
n SUBSTRATE

01

01

p

p+

CONTROL 0 - - 6 - - - - - - + - - +
INPUT
n+
1KO

02

n+
n

pWELL
-.t~~G:::':N-:::O:-----6--~

02

r----::t:-:-:-:=-----'
21119A

pWELL
21121A

Figure 7. Threshold Levels for Three-State Measurements
OES, OEK, OET

-i--------'-\lteNA~

I""-Iol-S
O.5V

THREE·STATE
OUTPUTS

2.0V
HIGH IMPEDANCE
21249A

2-228

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2302
Absolute maximum ratings (beyond which the device may be damaged) 1
Supply Voltage ........................................................................................................................................................................................ - 0.5 to + 7.0V
Input Voltage ................................................................................................................................................................................. -0.5 to IV OO +0.5)V
Output
Applied voltage 2 ................................................................................................................................................... - 0.5 to 1VOO + 0.5)V
Short-circuit duration Isingle output in HIGH state to ground) ......................................................................................... 1 Second

Temperature
Operating, case .............................................................................................................................................................. - 60 to + 130°C
junction ........................................................................................................................................................................... 175°C
Lead, soldering 110 seconds) ......................................................................................................................................................... 300°C
Storage ............................................................................................................................................................................ - 65 to + 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.

Operating conditions
Temperature Range
Standard
Parameter

Test Conditions

Min

Nom

4.75

5.0

Max

-1
Nom

4.75

5.0

Max

Units

Voo

Supply Voltage

VIL
VIH

Input Voltage, Logic LOW

IOL
IOH

Output Current, Logic LOW
Output Current, Logic HIGH

tCY

Cycle Time

VOO=Min

33

25

ns

tpWL
tpWH

Clock Pulse Width, LOW

VOO=Min
VOO=Min

15
15

12.5

Clock Pulse Width, HIGH

ns
ns

ts
tH

Input Setup Time
Input Hold Time

10
2

8
2

TA

Ambient Temperature, Still Air

0.8

Input Voltage, Logic HIGH

For More Information call 1-800-722-7074.

5.25

Min

8.0
-4.0

Raytheon Semiconductor

V
V
V

2.0

2.0

0

5.25
0.8

8.0
-4.0

10

70

0

mA
mA

ns
ns
70

°c

2-229

TMC2302
Electrical characteristics within specified operating conditions 1
Temperature Range
Standard
Parameter
Supply Current, Quiescent
Supply Current, Unloaded

VOO=Max, VIN=OV
VOO=Max, f=20MHz,
OES= OEK=OET = 5V

Input Current, Logic LOW
Input Current, Logic HIGH

VOO = Max, VIN=OV

VOH

Output Voltage, Logic LOW
Output Voltage, Logic HIGH

VOO=Min, 10L =Max
VOO = Min, 10H = Max

lOlL
10lH
lOS

Hi-Z Output Leakage Current, Output LOW
Hi-l Output Leakage Current, Output HIGH
Short-Circuit Output Current

VOO=Max, VIN=OV

el
Co

Input Capacitance
Output Capacitance

100Q
100U

IlL
IIH
VOl

Note:

Min

Test Conditions

-1
Min Max

Max
10
70

10

-10

70

mA
mA

10

",A
",A

-10
10

VOO=Max, VIN=VOO

0.4

0.4

2.4

2.4

-40

VOO=Max, VIN=VOO
VOO = Max, Output HIGH, one pin
to ground, one second duration max.

-20

-20

40
-70

10
10

TA=25°C, f=lMHz
TA=25°C, f=lMHz

V
V
~

-40
40
-70

Units

10
10

~
mA

pF
pF

1. Actual test conditions may vary from those shown, but guarantee operation as specified.

Switching characteristics within specified operating conditions
Temperature Range
Standard
-1
Parameter

Test Conditions

too

Output Oelay

tHO

Output Hold Time

VOO = Max, CLOAO = 25pF

tENA
tOIS

Three-State Output Enable Oelay 1
Three-State Output Oisable Oelay 1

VOO = Min, CLOAO = 25pF
VOO=Min, CLOAO=25pF

Note:

Min

Max

Min

15

VOO=Min, CLOAO=25pF

Max
12

12
15

ns
ns

4

4

Units

12
15

ns
ns

1. Ail transitions are measured at a 1.5V level except for tOIS and tENA

Applications Discussion
The Image Transformation Polynomial
On any given clock cycle, when performing a twodimensional geometric transformation the addresses
output by the row IX/Uj TMC2302 are generated by
forward difference accumulation according to the
following third-order polynomial:

The polynomial utilized for three-dimensional transforms
is:

xlu,v) = a + bu + cu 2 + du 3 + ev + Ivu + gvu 2 + hvu 3
+ iv 2 + jv 2u + kv 2u2 + Iv2u3 + mv3 + nv3u + ov 3u2
+ pv 3u3 + FOV • CAXlca)

where UMIN~u~UMAX, VMIN~v~VMAX,
WMIN ~ w ~WMAX, and the polynomials for the
column or page devices are obtained by replacing the
x by a y or z, as appropriate.

2-230

xlu,v,w) = a + bu + ev + kw + luv + ivw + luw + juvw
+ FOV • CAXlca)

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2302
The Image Transformation Polynomial (cont.I
FOV is the 16-bit field-of-view parameter, normally set so
that the spiral walk proceeds in single-pixel steps. FOV
can be increased to expand the step size and thus the
spiral walk, subsampling the image. See Table 2 and
Table 6. Also, CAX/ca) is the current value of the
coefficient address, and CAX/Ker) is the terminal value of
each pixel walk in that dimension. See the Interpolation
Coefficient Lookup Table Addressing. The CAX/Ker)
term arises because the IRS computes each new walk's
starting point from the previous spiral walk's end point,
rather than its starting point.

We can reform the two-dimensional polynomial as:
xlu,v) = la + ev + iv 2 + mv 3) + Ib + Iv + jv 2 + nv 31u
+ Ie + gv + kv 2 + ov 3)u 2 + Id + hv + Iv 2 + pv 3)u 3,
and retain the simpler three-dimensional form:
xlu,v,w) = a + bu + ev + kw + fuv + ivw + luw + juvw

and define each of the polynomial coefficients in
arithmetic terms, as shown in Table 5.

Table 5. Transformation Polynomial Coefficients
Parameter
Name
A

Term

Two-Dimensional
Coefficient

a
b+c+d
2c+6d
6d
e+i+m
f+ 9 + h + j + k+ I + n+o+p
2(g + k+ 0)+ 6(h+ I +p)
6(h+l+p)
2i+6m
2(j + k+ I) + 6(n + 0 + p)
4k+121+120+36p
121+36p
6m
6(n+o+p)
120+36p
36p

Xo
DXU
DXUU
DXUUU
DXV
DXUV
DXUUV
DXUUUV
DXVV
DXUVV
DXUUVV
DXUUUVV
DXVVV
DXUVVV
DXUUVVV
DXUUUVVV

B
C

D
E
F

G
H
I

J
K
L
M

N
0
P

Understanding The Polynomial Coefficients
An Overview

As the formulae indicate, the source address is a
polynomial function of the two (or three) dimensions
of the target address. Each of the 16 terms of the
equation is of the form:
dm+n+fv
dumdvn P,

w

and may be treated approximately as a mixed partial
difference of order m, n, and p.

For More Information call 1-800-722-7074.

Three-Dimensional
Term
Coefficient

Xo
DXU
DXV
DXUV
Xo
DXU
DXVW
DXUVW
DXW
DXUW
-

-

a
b
0
0
e
f

a
b
i
j
k
I

0
0
0
0

The simplest term, ><0, is a zeroeth (non-) function of
the target addresses; it specifies the source address
point corresponding to the upper left point in the
target space. Xo generates image translation or "pan."
The next-simplest terms, dX/dU and dY/rN, govern the
relative scales of the source and target images, i.e.,
how large a step in source space corresponds to a unit
step in the corresponding direction in the target space.
As long as the cross-terms, dX/rN and dY/dU, are zero,
this is a straight scale ("zoom") operation, without
rotation or shear.

Raytheon Semiconductor

2-231

TMC2302
Understanding The Polynomial Coefficients (cont.)

Internal and External Data Formats

The first-6rder cross terms, d'X/dV and dY/dU, generate
source space displacements perpendicular to unit
displacements in the target space, thereby causing
shearing of the image. In conjunction with the parallel
source terms described above, they govern rotation,
shear, and scaling of the image.

The source address value output by the TMC2302 is a
24-bit two's complement number, with binary point
assignable by the user anywhere in the 16 lower bits.
The Extended mode appends 12 additional fractional bits
for greater output precision. All internal computations.
include these 24 plus 12 bits, plus an additional 12 lower
bits, for 48-bit precision. See Table 6.

Although the actions of the higher-order terms become
progressively difficult to describe, all terms behave
essentially as partial differences of various orders, and a
little thought and common sense will generally lead the
user to the proper conclusions. For example, the term
dXUU (using the notation of Table 3) is a horizontal scale
factor which increases as one progresses across each
row, causing a quadratic horizontal warp. In fact all
terms of the form dm'X/dUm or dnY/dVn cause only
stretching of the image, never rotation.

Internally, each TMC2302's source address (X, Y, or Z)
generator computes a 48-bit address through a modespecific accumulation of the sixteen 48-bit user-specified
resampling parameters. The 24 most significant bits of
the final accumulation emerge via the source address
port, whereas the "extend" mode makes the 12 nextmost-significant bits available at the target address port.
The 12 least significant bits are truncated internally.

Interpolation Coefficient Lookup Table Addressing

Source Address Bit Weighting and Setting the Binary
Point

The external coefficient lookup table RAM stores the
interpolation coefficient values used to calculate the
value of the new pixel. These values are selected by the
user, allowing maximum filtering flexibility. In simple
filtering applications, the source and target pixel
addresses map one-to-one, and only one interpolation
coefficient set is required. These integer addresses are
generated for each dimension by the internal walk
counters of each TMC2302.

When performing nearest-neighbor resampling, the user
may arbitrarily trade source image size against subpixel
resolution merely by adhering to a single binary point
position for all resampling parameters. For example, if
the binary point follows the 16 most significant bits in
each resampling parameter, then it will appear following
the source address' 16 most significant bits, leaving 8
(20 in extended mode) bits of subpixel resolution on
SADRn·

However, applications performing a coordinate
transformation will almost always generate non-integer
source pixel addresses; that is, the U (or V) locations will
not map to the X (or Y) addresses exactly, and a
fractional source address components are generated.
The user must then expand the interpolation coefficient
lookup table to include spatially-corrected values, as
determined by the subpixel resolution of the system.

Since the TMC2302 has no internal limiter, the user
should select the source address weighting
appropriately. Moving the source address connections to
the right and reducing the resampling parameters
accordingly, reduces the chance or arithmetic overflow
while increasing arithmetic round-off error.

The TMC2301 Image Resampling Sequencer allows the
user to trade subpixel resolution against interpolation
step size by obtaining the interpolation coefficient
addresses directly from the fractional part of the source
address. The TMC2302 gives the user 16 different
interpolation bit weighting positions. The complete
Interpolation Coefficient Address for that dimension then
consists of both the 8-bit interpolation walk address
KADR7-Q, weighted to match the source address binary
point by the parameter FOV, and the fractional portion of
the source pixel address SADR23-{), to the desired
subpixel resolution. See Table 6.

2-232

In any filtering or resampling operation performing an
interpolation walk, the user should set the Field or View
(FOV) parameter according to the desired binary point
position determined above, as follows. To provide 224
integral pixel positions per dimension, with no subpixel
resolution, set FOV =001 (hex). For 223 pOSitions with 1bit (0,5) subpixel resolution, FOV = 0010 (hex). Similarly,
for 29 positions and 15-bit subpixel resolution. FOV =
8000 (hex). As shown in Table 6. using the parameter
FOV the user effectively "shifts" the bit weight of the
coefficient address word KADR7-Q to match the
established location of his source address binary point. In
each case, the EXTEND mode provides 12 additional bits
of subpixel resolution but eliminates the separate target
or raster address, which must then be generated
elsewhere in the user's system.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2302
Table 6. Relative Bit Weighting - Source Address
Word

Weight

247

246 . .. 240

239

232

231 . .. 225

224

223 .. . 216

215 ... 212 ... 28

27 ... 20

Transform
Parameters

-47

46

0

Internal Source
Address Generator

-47

46

0

Source Address
Output SAOR 23 _0

-23

22 ... 16

15

8

7 ... 1

0

Extended Mode Only
TADRll_0

11 ... 4

KADR7_0
FOV=OOOI
FOV=0002

··
·

FOV=8000
Note:

27

27 ... 2'

3 ... 0

27 ... . .. 20
26 ... 20

20

A minus sign indicates a sign bit.

Utilization of the Image Boundary Flags SVAL and
TVAL
As mentioned above, the TMC2302 provides two
programmable valid address, or boundary flags. The
source valid flag SVAL is asserted when the current
source image address output for that device's source
image dimension is within the space defined by the
configuration parameters XMIN and XMAX, or YMIN
and YMAX, or ZMIN and ZMAX, as appropriate. Also,
the target valid flag TVAL is available to indicate when
the current target image address values fall within the
space defined by the configuration parameters UMINI,
UMAXI, VMINI. VMAXI, and also WMINI and WMAXI
in three-dimensional systems. Note that all of these
parameters are each programmed into each individual
TMC2302. Thus, the user could define two (or three I
different working spaces, one indicated by each IMS
device.
Figure 8 may help clarify the relationships among (XO,
YO, Zol. (UMIN, VMIN, WMINI. and (UMAX, VMAX,
WMAXI. for the two-dimensional case. With positive
first derivatives, (XO, Yol and (UMIN, VMINI represent
the upper left corners of the original image and the new
destination field, respectively. The lower right corner of
the new transformed image is located at (UMAX,
VMAXI; the location of the corresponding corner of the
original image depends on the values of the derivatives.

For More Information call 1-800-722-7074.

Not to be confused with (XO, Yol. the points (XMIN,
YMINI and (XMAX, YMAXI define the "usable" rectangular portion of the original image which is indicated
by the valid address flag SVAL; points (X, Yllying
outside this region are ignored in most resampling and
filtering applications. Specifically, the point (XO, Yol is
the location from which the TMC2302 system begins
the image resampling sequence. Every step beyond that
point in the source image space is defined by the
address generators implementing the image transformation polynomials.
The valid source address flag feature permits one to
construct a mosaic of several abutting subimages in the
(X, YI plane, without danger of edge effect interference
between adjacent subimages. Note in the figure that the
upper right corner of the resampled source image lies
outside the admissible region; in practice, the values
fetched at these locations will not be included in the
convolutional sums. One might. for instance, program
these boundary values to alert the system that an edge
is being approached and to modify the interpolation
coefficients appropriately, or simply to ignore pixel values
outside the defined space.

Raytheon Semiconductor

2-233

TMC2302
Utilization of the Image BoundarY Flags SVAL
and TVAL (con'!.)
The flag lVAL hov.teVer is utilized somewhat differently.
Working in unison with the target address working space
defined by UMINJUMAX. etc., the target address valid flag
could be programmed to delineate image areas other than
the immediate working space, and the flag of each

TMC2302 to indicate the unique regions anywhere withiO
the target image. With this flexibility, the user can generl;lte
windows, ·picture-in-picture composite multiple images, or
simply switch to a background image or border color.
n

Figure 8. Pixel Maps Demonstrating Source and Destination Image Boundaries, Violation Flags, and Image
Clipping (Note Shaded Areas)
~

!

~

~~UMI~VMI~

/(XMIN, YMIN)

,

f""I
I

I

l

- --

I

-,
I

(UMAX, VMAX)

I
I

L _
SVAL·l

SVAL·O
-

-

.

-.::J,

~MAX~YMA;/

L~AL~
TVAL = 1

SOURCE IMAGE SPACE

TARGET IMAGE SPACE

21250A

Ordering Information
Product
Number
TMC2302H5C 1
TMC2302H5Cl 1

Temperature Range

Screening

Package

Package
Marking

STD-TA=O°C to 70°C
STD-TA=O°C to 70°C

Commercial, 30M Hz
Commercial, 40MHz

120 Pin Plastic PGA
120 Pin Plastic PGA

2302H5C
2302H5Cl

40G06360 Rev C 8193

2-234

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2302
Real·Time Bilinear Interpolation Using
the TMC2302 or TMC2301
Image transfonnations and translations in bit mapped
systems are done by taking an original (source) image,
performing coordinate remapping and interpolation, then
restoring the image into a new (destination) image space.
The coordinates are remapped according to a
transformation polynomial. The polynomial, evaluated at
destination pixel addresses, maps the transfonned pixel
addresses (U,V) to pixel addresses in the original image
(X,V), i.e., (X,V) is a polynomial function of (U,V).

ORIGINAL (SOURCE) IMAGE

x_

(0,0)
y

t

(UMIN,VMAX)
Notes:
1.
2

65-6433

Coordinate transfonnation: Each pixel in (U.V) space is mapped to a location In (X.V) space.
Interpolation: Unless the pixel in (U. V) space coincides with one in (X,V) space, its amplitude must be estimated as a
weighted average of these of the surrounding pixels In (X.V) space. If the interpolation is done serially, throughput suffers in proportion
to the size of the interpolation kemel. However. the interpolation can also be perfonned in parallel to preserve throughput, as discussed
here.

For More Infonnation call 1-800-722-7074.

Raytheon Semiconductor

2-235

TMC2302
The TMC2302 Image Manipulation
Sequencer
The TMC2302 is a controller/address generator, around
which an image filtering and resampling system can be
built. Under limited supervision from an external
controller, the TMC2302 will generate the sequence of
memory read and write addresses to transform,
resample, and/or filter an image. In all cases, it fetches
data from one image buffer, governs its convolution with
a user-specified kernel of coefficients, and directs the
results to another image memory space. With 24-bit
source address buses the device and operate from a
source frame size of, for example, 64K X 64K pixels with
spatial resolution of 11256th pixel. A simplified block
diagram of the TMC2302 is shown in Figure 2.
Although the 24 source addresses bits of each TMC2302
can be designed arbitrarily with the source image
address bus, assume for the current discussion that bits
SADR (19:8) will correspond to the source image
address and that SADR (7:4) therefore denote subpixel
positioning to 1/16 pixel resolution.

The basic 2-D system, shown in Figure 3, consists of
data source and destination memories, coefficient lookup
table, multiplier-accumulator. TMC2302 parameters to
define the transform and starts the operation. It may also
control the loading of the source image into RAM and
provide the screen refresh, if needed.

/'

_Jo..

DAT1S-G
ASYNCHRONOUS {
HOST INTERFACE

)

v

IADR 6-0
ICS
....
/

iWR

,,

CONTROL
PARAMETER
REGISTERS

SOURCE
ADDRESS
GENERATOR

"

OES

;

SADR 23-G

"-

}

SOURCE MEMORY
INTERFACE

SVAL

+

t

/'

"

WALK
COUNTER

OEK
}
KADR
ACC 7-G

CONVOLUTIONAL
CONmOL

TWR
NOOp)
ASYNCHRONOUS {
HOST INTERFACE

,
INIT ,

CLK

,,

~

CONTROL

A

I

--<

TARGET
ADDRESS
GENERATOR

I

I

OET
TADR l1-G}
TVAl

TARGET
MEMORY
INTERFACE

END
}

SYNC FLAGS

DONE
65-&120

Figure 2. TMC2302 Block Diagram

2-236

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2302
DATA IN

2302 ROW
(X)

12
TADR (11 :o)!-=-;~----T-J

DATA

SOURCE
IMAGE
A BUFFER
RAM

CONTROL ' I r " - - - ;

ClK

H~"""""Y
8

)(,Y,P
8x8

MAC

HERE
4X4KWORDs
IMAGE SIZE
ONE SET
PER COLOR
COMPONENT

ONE SET
PER COLOR
COMPONENT

Dour

ONE SET
PER COLOR
COMPONENT

SADR(19:8)
TADR (11 :8)t---.:d'-----.f--1

CLOCK

>-~~

8

__...J

DATA OUT

65-6434

Figure 3. Basic 2-D Image Transformation Systems

Inexact Transformations
In many cases, evaluation of the transformation
polynomial results in a non-integer result (non-integer
address in the X, Y image space), In such cases, the
mapping from original image to transformed image will
be inexact, When this occurs, the user has the option of
accepting the pixel "nearesf' to the address generated,
or performing interpolation, a weighted average of
nearby pixel values. Using the pixel nearest the address
generated is the fastest method since one transformed
pixel can be generated on every cycle. The resulting
image will include jagged biasing artifacts, however.
Performing several transformations on the same image
will further degrade the resulting image.

For More Information caJI1-80o-722-7074.

Raytheon Semiconductor

2-237

TMC2302
One Cycle Bilinear Interpolation
A better image can be obtained by finding the four pixels
nearest the address generated and performing a
weighted averaging to determine the new pixel value.
This is known as bilinear interpolation. The TMC 2302
eases the control logic required for such a function by
performing a "walk" around the four closest pixels in the
source image space. Essentially, the TMC2302
generates the addresses of the four walk cycles, and the
current source pixel is multiplied by a weighting factor
and accumulated by the external multiplier accumulator.
At the end of the walk, the accumulated result from the
four nearest pixels is written into the destination image
RAM and the TMC2302 proceeds to the next group. The
obvious disadvantage to using bilinear interpolation is
that one new destination pixel is generated only on every
fourth cycle, reducing the output bandwidth by a factor of
four.
One method of "real-time" bilinear interpolation consists
of using four memories, each containing the entire
source image. The storage arrangement of the pixels
within each bank is staggered so that a single address
fed to the memories will result in the access of the proper
four pixel group. The TMC2302 is programmed to
generate the nearest neighbor address and the four
nearest pixels are accessed simultaneously and input to
the four independent multipliers of a TMC2246 quad
multiplier chip. The four pixels are multiplied by their
associated weighting factors and added to determine the
destination pixel sum. The major drawback of this
method is the prohibitive cost for additional memory
required to store four copies of the entire source image.
For large images, the memory cost and additional board
space makes this method unattractive.
A more efficient method is to divide the original source
image into a "four-color checker board" and to store it
into four separate pixel memory banks, each containing
14th of the source image. Since the image is separated
into four memories rather than duplicated, no additional
image memory is required. The goal is to separate the
image so that any square of four adjacent pixel locations

2-238

can be accessed simultaneously. Thus, the user must
organize the memory such that the four pixels of any
cluster will reside in separate memory banks. With this
method, only one set of address generators (TMC2302s)
is necessary, and only a slight address modification is
necessary to guarantee that the correct group of pixels is
accessed and output to the multipliers. Since all pixels
are accessed simultaneously, no "walk" is performed,
and the TMC2302 system is able to generate one
destination pixel on each clock cycle. For example, a
1024 X 768 image can be generated every 20ms for a
frame refresh rate of 50Hz. This method which will be
described below.

Using "Banded" Pixel Memory
The TMC2302 should be programmed to do "nearestneighbor" transformations (Kernel, K = 0 and the Xo and
Yo start boundaries programmed without 1/2-LSB
truncation debiasing to force address truncation when
evaluating the transformation polynomial for the nearestpixel address). The biased Xo and Yo guarantee that
when the exact pixel address falls within the region of
four pixels, the upper leftmost pixel will always be
selected as "nearest-neighbor."
The key to performing real-time bilinear interpolation is to
arrange the pixels in memory so that the four pixels of
every grouping will be stored in separate memories. The
four nearest pixels will form a square. Figure four shows
a sample 512 X 512 pixel image and the arrangement
into four separate memory banks designated A, B, C,
and D. It can be seen from the figure that any (square)
grouping of four pixels will have one pixel located in each
bank. Thus, one memory sector will hold even row-even
column pixels, another,even-row-add column pixels, etc.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2302
Ao.o
(0.0)

80.0
(1.0)

A1.0
(2.0)

81.0
(3.0)

A2.0
(4.0)

82.0
(5.0)

A3.0 .......... A255.0
(6.0) ......... (51 0.0)

8255,0
(511.0)

CO.O
(0.1)

00.0
(1.1 )

C1.0
(2.1)

01.0
(3.1)

C2.0
(4.1)

02.0
(5.1 )

C3.0 .......... C255.0
(6.1) ......... (51 0.1)

0255.0
(511.1)

Ao.1
(0.2)

80.1
(1.1 )

A1.1
(2.1)

81.1
(3.2)

A2.1
(4.2)

82.1
(5.2)

A3.1 .......... A255.1
(6.2) ......... (51 0.2)

8255.1
(511.2)

CO.1
(0.3)

00.1
(1.3)

C1.1
(2.3)

01.1
(3.3)

C2.1
(4.3)

02.1
(5.3)

C3.1 .......... C255.1
(6.3) ......... (51 0.3)

0255.1
(511,3)

Ao.2
(0.4)

80.2
(1,4)

A1.2
(2.4)

81.2
(3.4)

A2.2
(4,4)

82.2
(5,4)

A3.2 .......... A255.2
(6,4) ......... (51 0.4)

8255.2
(511,4)

CO.2
(0.5)

00.2
(1.5)

C1.2
(2.5)

01.2
(3,5)

C2.2
(4.5)

02.2
(5.5)

Cs.2 .......... C255.2
(6.5) ......... (51 0.5)

D255.2
(511.5)

AOO.255 80.255
(0.510) (1.510)

A1.255
(2.510)

81.255
(3.510)

A2.255
(4.510)

82.255
(5.510)

A3.255 ...... A255.2 55
(6.510) ..... (51 0.51 0)

8255.255
(511,510)

CO.255 00.255
(0.511) (1.511)

C1.255
(2.511 )

01.255
(3.511 )

C2.255
(4.511)

02,255
(5,511)

C3,255 ...... C255,255
(6.511) ..... (510.511)

0255.255
(511.511)

Figure 4. Source Image Pixel Arrangement
Subscripts i,i for A. 8. C. and 0 denote relative addresses in memory respectively.
The ordered pairs (a. b) denote the physical (X.V) pixel locations and the TMC2302
SAPR(X) and SADR(V) address outputs.
The pixels of the original image should be stored in the source RAM banks as shown in Figure 5. The original source
image can be loaded by decoding the TMC2302 least significant address bits (SAORx(8). SADRy(8) to determine the
memory bank for the pixel while the most-significant address bits (SADRx(19:9). SADRy (19:9)) are used as common
address lines to aU four memory banks.
In the following discussion, the TMC2302 address outputs SADRx and SADRy will be designated as:

XAo
~

VAo
V~

For More Information call 1-800-722-7074.

Horizontal Source
Least-Significant Horizontal Source X-Address 8it SADRx (8)
Upper Horizontal Source Address 8its SADRx (19:9)
Least-Significant Vertical Source V-Address 8it SADRx(8)
Upper Vertical-Source Address 8its SADRy (19:9)

Raytheon Semiconductor

2-239

TMC2302
TMC2302 Address
~ Y~
o 0
o 1

o

2

1
1
1
255
255

255
0
1
2
254
255

o

Bank A
XAoYAo=OO
Ao,o
Ao,1
Ao,2
Ao,255
A1,O
A11

A1'2
A255:254
A255,254

BankB

BankO

BankC
XAoYAQ=10
Co,O
CO,1
CO,2
CO,255
C1,O
C1,1
C1,2
C255,254
C255,254

XAoYAo=01
Bo,O
BO,1
BO,2
BO,255
B1,O
B1,1
B1,2
B255,254
B255,254

XAoYAo=11
00,0
00,1
00,2
00,255
01,0
01,1
01,2
0255,254
0255,254

Figure 5. Memory-Pixel Arrangement

Interpolation Kemal

• - actual
Pixel

Figure 6. TMC2302 Serial Walk Sequence
In real time bilinear resampling, this is executed in parallel.

When the transformation polynomial is evaluated and the
resulting pixel address falls within a group of four nearby
pixels (non-integer result), the TMC2302 will always
choose the upper leftmost pixel (PH) as the nearest
neighbor (due to the fractional address truncation in the
X and Y directions). Since the four pixels will reside in
independent banks, the upper leftmost pixel might be
located in any of the four memory banks (A,B,C, or 0).
The bank which contains the nearest neighbor must be
known, since in each case, different memory address
modification is required to select the correct pixel from
each bank.

-- B'--AI ---- B---AI ---- B'--A--B-'
I
I
I
I
I
:

!

I

I

: *-1 : *-2 :
I

I

I

I

I

I

I

I

I

:

I

I

,

:

:

I

I

I

I

I

I

--D---- C----D----C----D---- C---'D-'
i i i

:

i

ii-

: *-3 : *-4 : :

:

I

I

I

i

I

I

I

I

I

I

I

I

-- B'--- A ----B----A---- B'--- A--- B-'
I
I
I

I

I

I

I

I
I

I

-- D'--- C ---,D----C---- D'---C'--- D-'
65-6437A

Figure 7. Possible Selections for Nearest Neighbor

2-240

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2302
Memory Address Modification
Using the address LSBs (XAo, YAo) from each
TMC2302 external logic can determine which bank
contains the nearest neighbor. (This same decoding is
used when loading the original image into the source
image RAMs.)
Case·
1

XAo

YAo

1

o

1

1

o
o

2

3
4

o
1

Nearest Neighbor (Upper Leftmost) Pixel
A Memory Bank contains Nearest Neighbor
B Memory Bank contains Nearest Neighbor
C Memory Bank contains Nearest Neighbor
o Memory Bank contains Nearest Neighbor

'from Figure 7 above

Addressing for each memory bank (A, B, C, 0) is done using the uppermost address bits (X~ of the TMC2302s. The
LSB of each TMC2302 is used to determine both the upper leftmost pixel and the address modification required. In the
following paragraphs, the lower case subscripts (i,i) denote the address of a pixel within a given memory bank (A, B, C, or
0), and XA, YA are used to denote physical address outputs of the TMC2302 pairs.
Pixel address modification use to access the correct four pixel group is determined as follows:
Case A: Ai,i is nearest upperleft neighbor,
(No address modifications)
(XAo =YAo =0)

A"1.1

Case B: Bi,i Is upperleft neighbor,
(Modify X component of A &C memory addresses)
(XAo = 1, YAo =0)

B"1.1

B"
I,)
Figure 8. Pixel Memory Mapping
for A=Upper Leftmost

Figure 9. Pixel Memory Pattern
for B =Upper Leftmost

0"
I,)
Memory Addressing Becomes:
A address = ~ YAp.
B address =X~ YAt,t
C address =X~ YAt,t
o address = ~ YAt,t
i.e., no modification is required.

For More Information call 1-800-722-7074.

Ai+1,i

Ci+1.i

Memory Addressing Becomes:
A address = (XAt,t + 1, Y~
B address = (X~ Y~
C address = (XAp. + 1, Y~
o address = (~ Y~

Raytheon Semiconductor

2-241

TMC2302
(Modify Y component of A & B memory addresses)
(XAo = 0, YAo =1)

Case 0: Oi,i is nearest neighbor,
(Modify A, B & C addresses, X and Y components)
(XAo =1, YAo =1)

Ci,j

Oi,j

Case c: Ci,j is upperleft neighbor,

Figure 11. Pixel Pattern

Figure 10. Pixel Pattern

for 0 =Upper Leftmost

for C =Upper Leftmost

Ai,;+1

Bi,i+ 1

Bi,i+1

Ai+1,i+1

Memory Addressing Becomes:
A address =XA,J. + 1, YAv. + 1
B address = ~ YAv. + 1
C address = XAv. + 111, YAv.
oaddress = XAv., YAv.

Memory Addressing Becomes:
A address = X~ YAv. + 1
B address =X~ YAv. + 1
C address = XAv., YAv.
o address = ~ YAv.

Taking a close look at the address modifications required
for each case above, a simple pattern can be seen. This
pattern leads to a set of address modification ·rules·
based on the values of the least-significant address bits
from the TMC2301s (XAo and YAol. These rules are:
When YAo = 0, (Case A & B)
No modification to the Y address component (YA~ is
necessary.
When YAo = 1, (Case C & 0)
The Y component (Y~ of addresses to the A &B
memory banks must be incremented by 1.
When XAo = 0, (Case A & C)
No modification to the X address component (XA~ is
necessary.
When XAo = 1, (Case B & 0)
The X compOnent (X~ of addresses to the A & C
memory banks must be incremented by 1.

2-242

Ci+1,i

A system can easily be designed to modify the pixel
memory addresses according to the above criteria, to
select the correct four pixels to be interpolated. Rather
than actually performing a ·conditional" address
increment as discussed above, it requires less logic
simply to add the LSB address bit to the memory bank
addresses (~ Y~. Figure 12 shows the logic to
perform the required address modifications. The addition
(XAv. + XAo, YAv. +YAo) can be done using half-adders
with the XAo (YAo) address output of the TMC2302
connected to the carry-in of each adder. It can also be
done using high-speed programmable logic.
Note: Only modifications to the source image memory
are necessary. The destination image memory may be
arranged in a linear or other type array as required by
the refresh circuitry.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2302

12

u

TO
DEST.
MEMaRY

TMC2302
(COLUMN)

TMC2302
(ROW)
U

TADR (11:0)

TADR(11:0)

V
12

SADR (19:9)

SADR (19:9)

SADR(S)

1XA~ I XAo

I

"\t[
Yn .1
ADDRESS IN

lYAo

~

11

X11•1

YA~

SADR(S)

11

Xn .!

Yn .1

X11 •1

Yn .1

1

Xn .1

Y11 •1

BANK A

BANKC

BANKB

BANKD

OUT

OUT

OUT

OUT

t

S"

TO MPYA

t

s

TO MPYC

t

s

TOMPYB

t

s

TO MPYD

·Number of bits of intensity per pixel. per column component. typically 8 to 12.

65-8435A

Figure 12. Memory Address Modification

For More Information call 1-800·722·7074.

Raytheon Semiconductor

2·243

TMC2302
Coefficient Memory
Typically, the 4 highest fractional source address bits
from each TMC2302 (SADR (7:4) in the example) are
used to reflect the offset from the nearest XA (YA) pixel
location. With spatial resolution of 4 bits in both the X
and Y directions, there can be as many as 256 unique
coefficient values. This requires a coefficient memory of
at least 256 bytes. However, as shown below, each of the
four different cases requires its own set of 256
coefficients.
16 STEPS

I"
Pi,i

:

:

:

:

:

:

::

I

I

I

I

I

Pi,j+1

I
I
I
r
I
I
I
I
I
I
I
I
I
I
I
-----.,---I---r--r--r--r--r--T---r---r--,--..,--.,---I---r-----I
I
I
I
I
I
I
I
I __ 4I __ -II __ ....,I __ -II___I1___ I'- __ - - - -----~---1---1---~--1---'---4----I--_4-

I

I

I

I

I

I

I

I

I

I

-----+-+-+--f---f---J---J---f--t--t--i--+-+-+-+-----r----------+--1--+
l------I
I
I
-----~---r--r
I
I
I
I

I

I

I

I

I

1-------

----- .... ---I---r
I __ IL
_____ I___L
~

IL _____ _

I

I

I

I

I

I

I

I

-----.,---,---,...

r-------

_____ J___L__ L.

256 Discrete

L_____ _

: : :
-----.---r--r
I
I
I

Coefficient Values

:r------

___ L __

I _____ _
L

~

_____

~

16 STEPS

I
I
I
I
I
I
-----.,---I---r
I

I

I
I
r------

I

I

-----~---~--~
I
I
I

~------

I

------l--+-+
I
I
I

f------I

-----~---~--~

I

Pi +l,j

I

~------

I

I

iii

i

Pi +l,j+1
65·6436

Figure 13. Interpixel Resoultion

One-cycle bilinear interpolation requires four
independent coefficient memories, so that a parallel
multiplication can be performed with the four pixel
values.
Similar to determining the correct four pixel group, the
coefficients must take into account the memory bank (A,
B, C or D) that contains the upper leftmost pixel, and
adjust the coefficients accordingly. These adjustments
are necessary since the fractional address outputs
(SADRx (7:4), SADRy (7,4) from the TMC2302s reflect
the spatial distance only from the upper leftmost pixel
within the pixel group. Assuming that the fractional
addresses

2-244

SADRX (7:4) and SADRy (7:4) plus the integer LSBs
SADRX (8) and SADRy (8) are to be used directly to
address the 1024-byte coefficient memory, the loading of
the coefficients is shown on the next page with FX =
SADRx (7:4) and Fy '" SADRy (7:4) Case A through D
are the same as discussed previously for the pixel
address modifications.

Raytheon Semiconductor

For More Information call HIOO-722-7074.

TMC2302
Incorporating the concepts ouHined in this discussion,
the final system for one-cycle bilinear interpolation is
shown in figure 14. This figure shows a smail increase in
logic over the basic 2-D system shown in figure 3. The
additional logic required includes: TMC2246 (rather than
a single multiply/accumulate), and three additional
coefficient memories. Some additional decoding logic is
required to load the four pixel memory banks as well as
some data and address pipelining (registering) to meet
timing requirements. The solution, however, provides an
increased pixel bandwidth, by a factor of four, and only a
small increase in part count.

Case A: A is nearest neighbor (XAo = 0, YA{J = 0)
Coeff A = (1- fx) * (1 - fy)
Coeff 8 = ( fx) * (1-fy)
Coeff C = (1 -fx) * (fy)
Coeff D = fx * fy
Case B: B is nearest neighbor (XA{J = 0, YA{J = 1)
Coeff A = fx * (1- fy)
Coeff 8 = (1- fx) * (1- fy)
Coeff C = fx * fy
Coeff D = (1-fx)fy
case C: C is nearest neighbor (XAO = 1, YA{J = 0)
Coeff A = (1- fx) fy
Coeff B = fx fy
Coeff C = (1- fx) (1- fy)
Coeff D = fx * (1-fy)
Case 0: D is nearest neighbor (XAO=1,YA{J=1)
Coeff A = fx fy
Coeff B = (1 - fx) fy
Coeff C = fX * (1- fy)
Coeff D = (1- fx)(1 - fy)

10

IC
SAOR (19:9)
TMC2301
(ROW)

SAOR(B~

~

TOAR
SAOR(S:4)

IB

A

SOURCE
IMAGE
RAM

-is

15
I

I

10
10
10
10

0

C

B

I

A
COEFF.
RAM
1KxB f-

-

-

5

oj

S S B

TMC2246

~

~

0:

0

~

§:
0:
0

300 Hpm

DC Electrical Characteristics
Vcc = 10V :1:3%, VEE = -5.2V f5%, TA = 25°C (still air), no load, unless otherwise specified

Svmbol

Parameters
Differential Inputs: VIN+, VINAboolute
Input Voltage
V'N+' V,N_
V,D
Differential Input Range
Bias Current
I'N+' ',NAbsolute SLR Control, SRCA
VSRCA
Corrpliance Voltage Range
ISRCA
Control Current Range
%SLRMax "IoSLR Absolute Change
%SLRMax %SLR Aboolute Change
Matching slR Control, SRCM
CorrpJiance
Voltage Range
VSRCM
ISReM
Control Current Range
Max % SLR Ma1l::hing Change
%SLR
Voltage Program Inputs VH,L
VH
VH Range

VL

VLRange

VA
IH
IL
TCIH

IVOH-vod
Bias Current@ VH
Bias Current@ VL
Max Temperature Drift in IH

TCll

Max Temperature Drift in Il

LYBDC

Variation in IHo IL with Power
Supply and DC Voltage at VH or VL
VHlBW

VHlBW
2-252

Test CondHIons

IV,N+ -V'NJ
-2VS, V,N± s,..sV
VH = +5V, VL = OV

Min
-2.0
0.4

-2.3
-1.0

Max

UnHs

ECl
-100

..s.0
5.0
-250

V
V
J,1A

-0.9
+1.0

V
rnA
%
%

0.9
+0.5

V
rnA
%

..s.0
+10.0
..s.0
+5.5
+7.5
+3.5
10
-5.0
-5.0
40

V
V
V
V
V
V
V
J,1A
J,1A
nNOC

40

nNOC

+2.0

J,1A

-1.6
-20
-40/+25

V(X)m= -2.0
V(X)m=-2.4
VH = +5V, VL =-oV

l'vD

0.4
-0.5

0.6
30

Vce= 10V, VEE=-52V
Vee = 12V, VEE =-32V
Vee = 8V, VEE=-72V
Vee = 10V, VEE = -5.2V
Vee = 12V, VEE =-32V
Vee = 8V, VEE=-72V
Output Voltage ArrpIitude
-1.0V S,VHs,..sV; VL= -3.0V
-3V S, VLS, +5.5V; VH = ..s.OV
VH = 7.0V; 250C gA S, 70OC;
(0u1pUt not switching)
Vl =-2.0; 250CgC S,70OC
(oulput not switching)
V~ -1.0V to..sV
VL= -3V to +5.5V
-3 dB point from VH.LBW to VOUT

Raytheon Semiconductor

-1.0
+1.0
-3;0
-3.0
-1.0
-5.0
0.40
-1.0
-1.0

-2.0

50

kHz

For More Information, calI1-BOO-722-7074.

RC7310
DC Electrical Characteristics (continued)

VOH

Parameters
Signal Output Va. VOTERM
Range for High Level Voltage

Va...

Range for Low Level Voltage

oVOH

Offset to Output High Level

OVa...

Offset to Output Low Level

VTC

ro

Output Voltage Drift
Gain Error

fL

Unearity Error

Symbol

Zoor
lAC
loe
Va...
leL
TS
ICC

'EE
PSRVo
PSRVSL
TA

Test Conditions

Output Impedance
AC Current Drive
DC Current Drive
'Thermal Shutdoml 0IJII1Jt (TS)
Output Low Level
DC Current Umit
Shuldown Die Temperature
Other
Positive Supply Current
Negative Supply Current
Output Level to Power Supply
Rejection Ratio
Output Slew Rate to Power Supply
Rejection Ratio
Operating Temperature
Range

For More Information, call 1-800-722·7074.

Min

-1.0
Vee = 10V, VEE = -52V
+1.0
Vee = 12V, VEE =-3·2V
-3.0
Vee =8V, VEE=-72V
Vee =10V, VEE =-52V
-3.0
+1.0
Vee = 12V, VEE = -32V
-5.0
Vee =8V, VEE=-72V
OVOH= IVH - VOHl, VH= Ov, VL=-3\
-1.0V S VHS iSV; VL= -2V
OVa... = IVL- VOlI, VH=8V, VL= OV
-3VSVLS+5.5V; VH=+7V
-3V SVLS+5.5V, -1.0V SVHSiSV
-1.0
-3.0V S VL S+5.5V, V~ iSV
-1.0VSVHS+7.5V, VL=-3V
-0.3
OVSVLS+5V, V~iSV
OVSVHS+5V,YL=-3V
-0.5
-3.0V S VLS +5.5V, V~ iSV
-1.0VsN~+7.5V, VL=-3V
VO(RC7310)
70
50

1YP

Max

Units

30

is.O
+10.0
+6.0
+5.5
+7.5
+3.5
100

V
V
V
V
V
V
mV

30

100

mV

0.1

0.5
+1.0

mVfC
%VSET

+0.3

%VSET

+0.5

%VSET

Ia... =4rnA
70
115

n

12.6
100

110
130

rnA
rnA
0.5
130
160

rnA

60
60
Vee; t.Vee =:l:2.5%
VEE; t.VEE = :l:2.5%
Vee; t.Vee =:l:200 mV
VEE; t.VEE = ;1:200 mV
StillN.r
N.r Flow> 300 Ifpm

Raytheon Semiconductor

rnA

dB
dB

40
40

0
0

V

rnA
"C

25
25

4
4
50
70

%
%
"C

"C

2-253

RC7310
AC Electrical Characteristics

vee = 10V ±30,'0, VEE = -5.2V :15%, TA = 25°C (still air) and the load is a 50ntransmission line with 2.0 ns one-way delay,
unless otherwise specified. The transmission line should be back-terminated in 50n (±10,'0) using an external resistor. The
measurement probe is a high impedance FET probe with capacitance no greater than 6 pF and resistance no smaller
than 10 kn.

Symbol

Parameters

SLR

Slew Rate
(SRCM and SRCA
Adjusted)

SLR

Slew Rate
(No SRCM and SRCA
Adjustmen~

tR
tF

Rise lime and
Fall lime
(SRCM and SRCA
Adjusted)

tR
tF

Rise lime and
Fall lime
(No SRCM and SRCA
Adjustrnen~

f

Toggle Rate

tpLH
tpHL
Mp
tpTC
tPWM1N

Propagation Delay
Low to High
High to Low
Ma1ching Itpl 1-1 - tpi-li I
Temperature CoeffICient
Minimum Pulse Width

Test Conditions
VH"VL = 5V; measured between
20% and 80"10 poinlS.
With probe only as load
With probe and transmission line
VH-VL = 5V; measured between
20"10 and 80"10 poinlS.
With probe only as load
With probe and transmission line
Load is Probe Only
ArrpIitude = 0.8V (20% to 80%)
3V (10"10 to 90"10)
5V (10"10 to 90%)
9V (10"10 to 90%)
Load Is Probe Only
ArrpIitude = 0.8V (20"10 to 80%)
3V (10"10 to 90"10)
5V (10"10 to 90"10)
9V (10"10 to 90"10)
Amplitude = OPN
Arrplitude = 5.0V

PS

Propagation Delay
Variation with Pulse Width
Preshoot

OS

{),tershoot

0.5V < IVOIiVOL.1 < 5V

ts

0u1put Settling lime

IVOH-VOL.I = 5V;
To Within 3"10 of IVOIiVOL.1
To Within 1"10 of IVa-rVod

2-254

1YP

12
1.1

1.6
1.5

V/ns
V/ns

1.0
1.0

1.4
1.4

V/ns
V/ns

250
105

f = 10 MHz; VOH = +<>.4V; VOL. = -o.4V

VH - VL = 2.0V; Pulse Width atwhich
amplitude drops by 50 mV,
measured between 50% points
2ns< PW <98 ns;f= 10 MHz;
VOH = +<>.4V; Va.. = -o.4V
0.5V < IVOIiVOL.1 < 5V

MpPW

Min

Raytheon Semiconductor

Max

Units

0.6
1.7
2.4
4.0

0.8
2.0
2.9
4.8

ns
ns
ns
ns

0.7
2.0
2.8
4.8
270
110

1.0
2.4
3.6

ns
ns
ns

1.6
1.6
150
2

2.0
2.0
175

ns
ns
ps
psI"C
ns

+75

ps

ns
MHz
MHz

2.0

-75
15mV+
3% of VA
5OmV+
4% of VA
5
10

mV
mV
ns
ns

For More Information. caJI1-800-722-7074.

RC7310
Block Diagram

Vee

VEE

~~~~~t;~~==~~r~---------r--~OF
j-----,
VHC

I

0--+---,

0---1---1
VII~.. 0--1---1

VIN+

VLC 0--+---1
VL

Gnd

I

-I---wr--tI
I

I
I
I
I
I

IRC7311TI

Vo (RC7311)
(RC7311T)

--~
VOTERM

L_~®'_J

'-------+---0 VEEO

r-------------------

r-------------------------+--oTS

TST
65 ..5235

For More Information, call 1-800-722..7074.

Raytheon Semiconductor

2..255

RC7310

2-256

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC7311
RC7311
250 MHz ATE Pin Electronics Driver
General Product Description

Features
• High output slew rate (1.8 V/ns typical)
• Wide output voltage range (-3.0V to +8V), and up to
10 Vp-p swings
• 250 MHz minimum operation for ECl swings
• Wide input common mode range for ease of interface
to ECl as well as TTL and CMOS
• Output short-circuit protection with current limiter and
thermal shutdown
• 100 rnA dynamic switching current drive
• Absolute slew rate control
• Available in 28-pin PlCC
• low output voltage offset (30 mV) and output offset
drift (0.1 mV/oC typ.)
• Low input bias current (1 pA typical) and current drift
(40 nAl°C) for output level program allows direct
coupling to a DAC output.

Applications
•
•
•
•
•
•
•
•

ATE pin electronics driver
Precision waveform generator
Level translator
Differential line receiver
General purpose driver
Switch driver
Laser driver
CRT preamplifier

The RC7311 Pin Electronics Driver is an economical
alternative to standard pin electronics drivers in
applications that do not require three state capability in
the driver. An example of such an application would be
the large number of input address pins found in memory
testers.
The driver output levels are programmable between 3.0V and +8V to drive ECl, TTL and CMOS logic
families. The peak to peak output swing can vary from
values lower than 300 mV to values as high as 1OV. With
toggle rates greater than 250 MHz for ECl signals and
typical slew rates of 2 V/ns for 5 Vp-p signal amplitudes,
the RC7311 is compatible with the requirements of stateof-the-art testers. The high and low limits of the output
swing are set through the program pins VH and Vl ,
respectively. The transfer characteristic from the program
pins to the output pin is unity gain with low offset (30mV)
and offset drift (0.1 mVrC typical). The VH and Vl inputs
have been buffered to operate with low bias currents (1.0
pA typical) allowing direct coupling to the output of a
DAC.
The RC7311 is provided with high speed differential ECl
inputs for ease of interface with the differential ECl
outputs of a timing generator. The inputs have a wide
voltage range, -2V to +6V, so that if required, an input
may be driven by TTL or CMOS devices provided that
the other input is tied to the appropriate threshold value.
The RC7311 is specified at nominal power supply values
of 10V and -S.2V, and commensurate output voltage
swing limits of -3.0V and +8V. The supply rails may be
raised by 2V to achieve an output high level (VOH) of
+1 OV, or lowered by 2V to achieve an output low level
(VOL) of -SV. At all times there must be at least a 2V
margin between the positive supply and the maximum
value of VOH ' and between the negative supply and the
minimum value of VOL'
The RC7311 is implemented using Raytheon's high
performance precision complementary bipolar process.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

2-257

RC7311
Pin Definitions
Name Function
VCC

VEE

Quiet positive supply. The nominal value is 1OV f301o.
For oulput high voltage levels {V00 greater than the
nominal value of -H3V, VCC should be raised 2V
above the maximum VOl-! value. Whenever VEE is
lowered to provide margin at the 0U1put low level,
Vee should also be lowered by the same amount
Vcc should be bypassed to the ground plane with a
10,000 pF chip capacitor placed as dose to the pin
as possible.
Quiet negative supply. The nominal value is -52V to
:t5%. For ou1ptrt low voltage levels {VOlJ less than 3V, VEE should be lowered 2V below the minimum
VOL value. Whenever Vee is raised to provide
margin at the ou1ptrt high level, VEE should be raised
by the same amount. VEE should be bypassed to
ground with a 10,000 pF chip capacitor placed as
close to the pins as possible.

Veea Positive supply for the ou1ptrt stage. This supply is
brought out separately to minimize the supply noise
generated when the ou1ptrt switches. Vceo should
be bypassed to the ground plane with a 10,000 pF
chip capacitor placed as close to the pin as possible
and then immediately connected to Vee.
VEEO

Negative supply for the ou1ptrt stage. This supply is
brought out separately to minimize the supply noise
generated when the oulput switches. VEEO should
be bypassed to the ground plane with a 10,000 pF
chip capacitor placed as close to the pin as possible
and then immediately connected to VEE'

GND

Chip ground. These pins should be connected to the
printed circuit board's ground plane at the pins.

TST

Pin used for factory testing the thermal characteristics
of the device. The pin should be left unconnected or
tied to GND.

VH

Analog program input that sem the ou1ptrt high level
(VOH)' The transfer characteristic from VHto VOH is
nominally unity gain.

VL

AnaJog program input that sem the output low level
(VOL)' The transfer characteristic from VL to VOL is
nominally unity gain.

VHC

Bypass for analog program inp.Jt high, VH. VHC
should be bypassed to the ground plane with a 1000
pF chip capacitor placed as dose to the pin as
possible.

2-258

Name FunctIon
Bypass for analog program inp.Jt low, VL· VLC
VLC
should be bypassed to the ground plane with a
1000 pF chip capacitor placed as close to the pin as
possible.
V,N+
V,N-

Differential digital inputs. The oulput will toggle
between the two levels dictated by VH and VL as
the differential signal is swifched. Although these
inputs will normally be driven by ECL signals. they
have a wide enough common roode range that any
one of the inputs may be driven by a m or CMOS
signal provided that the other input is tied to the
appropriate threshold voltage.

Va

Driver oulput of RC7311. The ou1ptrt impedance is
12.Sn±1.5il The ou1put is usually back-terminated
in the characteristic impedance of the driven
transmission line. For a 50n line, a 37.40±1% or
better resistor should be placed extemaJly as close
to the oulput pin as possible to minimize reflections
and ringing. The resistor should also be able to
dissipate o.an to sustain the short-circutt current of
the output.

OF

On chip filter to improve ou1ptrt waveform (optional).
This pin connection is optional and should be left
unconnected Wnot used. When used OF pin
should be tied to the termination node that is direcUy
connected to the OUT.

SRCA Absolute slew rate control. By applying current at
this pin, sma/I changes in slew rate can be
programmed with an extemal DAC. This control pin
affects both positive and negative edge rates. If this
slew rate control is not desired this pin should be left
open.
CIM1
CIM2

Optional: A 10,000 pF chip capacitor could be
placed between CIM1 and CIM2 to ifllll'ove
impedance ma1ching across different voltage
swings. With this capacitor, oulput impedance stays
rrore constant with changes in voltage swings. W
not used, leave pins CIM1 and CIM2 open.

SRCM Slew rate control matching. By applying current at
this pin, sma/I changes in slew rate can be
programmed with an extemal DAC. This control pin
adjusts the ma1ch between positive and negative
edges. If this slew rate control is not desired this
pin should be left open.

Raytheon Semiconductor

For More Information, calI1-BOO-722-7074.

RC7311
Connection Information

Pin Definitions (continued)
Name Function
TS

28-pin PLCC Package
(Top View)

Active low ou1put notifies thermal shutdown has
occurred. In the event of a short-<:ircu~ or other fautt
that causes the die terrperature to rise between
1i5"C and i60"C, the thermal shutdown will
activate. If the fault persisls, the device will toggle
back and forth bemeen shutdown and normal
operation at a frequency in the tens of Hertz. TS is
an open collector ou1put capable of driving me
standard
loads. The TS pins of several drivers
may be wired together and input to a latch to
indicate an alarm condition.

4 3 2 1 282726

..::::

m

NC

25
24
23
22
21

5
6
7
8
9
10
11

20

19
12131415161718
65-5741

No connection.
Pin
1
2
3
4

Absolute Maximum Ratings (1)
Positive power supply, Vee ...................................... 13V
Negative power supply, VEE .................................. -B.2V
Difference between Vee and VEE .....•..........•........... i6V
Input voltage at V1N+' VIN- ............................... Vee -12V
VEE+i2V
Input voltage at VH' L .......•...•..........•..........•.... Vee -13V
VEE+13V
Differential input voltage, IVIN+ - VIN_I ........................ 6V
Difference between VH & VL, (lVH - Vd) .........•........ 13V
Driver output voltage ....................................... Vee -i3V
VEE+i3V
Output voltage at TS .................................................. 7V
Duration of short-<:ircuit to ground .................... Indefinite
Operating temperature range ....................... OOC to 70"C
Storage temperature range ................... -65"C to +i25"C
Lead temperature range
(Soldering 10 seconds) .................................. 300°C
Notes:
1. •Absolute Maximum Ratings· are those beyond which the safety
of the device cannot be guaranteed. They are not meant to
imply that the device should be operated at these limits. If the
device is subjected to the limits in the absolute maximum ratings
for extended periods, its reliability may be impaired. The tables
of Electrical Characteristics provide conditions for actual device
operation.

For More Information, call 1-800-722-7074.

5
6
7
8
9
10
11
12
13
14

Function
Vo
OF
CIM1
CIM2
TST
NC
Veeo
Vee
VHe
VLe
SRCM
SRCA
NC
VIN-

Pin
15
16
17
18
19
20
21

Function
VIN+
GND
NC
VH
VL
NC
NC
22 VEE
23
~EO
24
25 TS
26 NC
27 NC
28 GND

Ordering Information
Part Number
RC73110A

Package

Operating
Temperature
Range

OA

OOC to +70"C

Notes:
QA - 2S-pin PLCC

Raytheon Semiconductor

2-259

RC7311
Recommended Operating Conditions
Symbol
Te
Vee
VEE
Vee-VEE
VOH,VOL
IVoH-Vod
RT

Parameters
Case operating temperature\ l }
Positive supply voltage
Negative supply voltage
Difference between positive and negative supply
Range for output high level and output low level
Output amplitude
Output back-termination resistor for RC7311

Typ

Min
0
9.7
-5.45

10.0
-5.2
15.2

VEE+2V
0.4

Max
70
10.3
-4.95
15.8
Vee- 2V
10.0

Units
°C
V
V
V
V
V

n

37.4

Notes
1. With air flow >300 Jfpm

DC Electrical Characteristics
vcc = 10V:fBOIo, VEE = -5.2V:J:5% TA =25"C (still air), no load, unless otherwise specified

Symbol

Parameters
Differential Inputs
VJN+o V~
VIN+' VIN- Absolute Input Voltage
VID
Differential Input Range
Bias Current
IIN+,IINAbsolute SLR Control, SRCA
Co"",iance Voltage Range
VSRCA
Control Current Range
'SRCA
%SLRMax o/oSLR Absolute Change
%SLRMax o/oSLR Absolute Change
Matchk'lg SLR Control, SRCM
Co"",iance Voltage Range
VSRCM
Control Current Range
ISRCM
Max % SL.R Malching Change
%SLR
Voltage Program Inputs VH,L
VH Range
VH

VL

VLRange

VA
IH
IL
TCIH

IVOH-Vod
Bias Current @ VH
Bias Current@ VL
Max Temperature Drift in IH

TCIL

Max Temperature Drift in IL

2-260

Test CondItions

IVIN+ -VINJ
-2V5'. VIN± 5'. +6V
VH=+5V, VL=OV

Min

-2.0
0.4

-2.3
-1.5

Max

Units

ECl
-100

+6.0
5.0
-250

V
V

JlA

-0.9
+1.5

rnA

-1.6

-20

Voom=-2.0
Vcnm=-2.4
VH= +5V, VL=-OV

1VP

%
%

-40/+25
0.3
-0.5

0.6

0.9
+0.5

Raytheon Semiconductor

-1.0
+1.0
-3.0
-3.0
-1.0
-5.0
0.30
-1.0
-1.0

V

rnA
%

30
VCc= 10V, VEE=-5.2V
Vce = 12V, VEE = -3.2V
VCC= 8V, VEE=-72V
VCC=10V, VEE =-52V
VCC=12V, VEE=-32V
VCC= 8V, VEE =-72V
0u1put Voltage ArJ'l)Iitude
-1.0V 5'.VH5'...aV; VL= -3.0V
-3V 5'. VL5'. +5.5V; VH= ..a.OV
VH = 7.0V; 25"C5'.TA5'.70"C;
(oulput not switching)
VL= -2.0; 25"C 5'. TC 5'.70"C
(oulput not switching)

V

..a.0
+10.0
+6.0
+5.5
+7.5
+3.5
10
-5.0
-5.0
40

V
V
V
V
V
V
V

nN"C

40

nN"C

JlA
JlA

For More Information, call 1-800-722-7074.

RC7311
DC Electrical Characteristics (continued)
Symbol

VH,lBW

Parameters
Variation in IH' It.. with Power
Supply and DC Voltage at VHor Vl
VH,lFm

VOH

signal output V()J VOTERM
RarQe for High Level Voltage

VOL

Range for Low Level Voltage

~BDC

8VOH

Offset ID Ou!put High Level

8VOL

Offset to 0uIput Low Level

VTC

Ou!put Voltage Oift

Fa

Gain Error

fL

Unearity Error

loUT
lAC
loc
VOL
ICl
TS
IcC
IFF
PSRVo
PSRVSl
TA

Vt-j= -1.0V to -taV
Vl= ~V ID +5.5V
~ dB point from VH,LBW to VOUT
Vee=10V, VEE =-5.2V
Vee = 12V, VEE=~.2V
Vee = 8V, VEE=-72V
Vee = 10V, VEE =-5.2V
Vee=l2V, VEE=~.2V
Vee = Sv, VEE=-72V
8VOH = IVH - VOHI,VH= OV, VL= ~V
-1.0V S VHS-taV; Vl =-2V
8VOL =IVL -VOlI, VH=8V, VL=OV
~V S Vl S+5.5V; VH = +7V

Min
-1.8

-1.0VSVHS-taV
~.OV S VL S +5.5V, VH= -taV
-1.0VSVH S+7.5V, VL=~V
OVSVHS+5V, Vt-j=-taV
OVSVHS+5V, VL=~V
~.OV S VH S +5.5V, VH= -taV
-1.0VSVHS+7.5V, Vl=~V
Vo (RC7311)

'JW)

Max
+1.8

50
-1.0
+1.0

kHz

30

V
V
V
V
V
V
mV

30

50

mV

0.1

0.5

mVt'C

~.O

+1.0
-5.0

-1.0

+1.0 %VSET

-0.3

+0.3 %VSET

-0.5

+0.5 %VSET

70
50

70
115

n

12.S
100

lot.. = 4mA
110
130

mA
mA

mA
"C

4
4
50
70

mA
dB
dB
%
%
°C
°C

mA

Raytheon Semiconductor

40
40

0
0

25
25

V

0.5
130
160

SO
SO
VCC;L\VCC =±2.5%
VEE; L\VEE = ±2.5%
VCC;·WCC=±200mV
Vj:;j:;; L\Vj:;j:; = ±200 mV
Stili Air
Air Flow> 300 Ifpm

Units
pA

-ta.0
+10.0
+6.0
+5.5
+7.5
+3.5
50

~.O

~VSVLS+5.5V

Output Impedance
AC Current Drive
DC Current Drive
ThennaI Shutdown Output (TS)
Output Low Level
DC Current Umit
Shutdown Die Temperature
Other
Positive Supply Current
Negative Supply Current
Output Level to Power Supply
Rejection Ratio
Output Slew Rate to Power Supply
Rejection Ratio
Operating Temperature
Range

For More Information, call 1-800-722-7074.

Test CondItions

2-261

RC7311
AC Electrical Characteristics

vee = 1OV :1:3"10, VEE = -52V :1:5%, TA = 25"C (still air) and the load Is a son transmission line with 2.0 ns one-way
delay, unless otherwise specified. The transmission line should be back-terminated In son (±1"10) using an external
resistor (RC7311). The measurement probe Is a high Impedance FET probe with capacitance no greater than 6 pF and
resistance no smaller than 10 kn.
Symbol
SLR

SLR

Parameters
Slew Rate
(Adjust both SRCM &
SRCA)
Slew Rate
(No SRCM &
SRCA Adjustment)

tR
tF

Rise lime and
Fall lime
(SRCM&
SRCA Adjusted)

tR
tF

Rise lime and
Fall lime
(NoSRCM&
SRCA Adjustment)

f

Toggle Rate

tpLH
tpHL
Mp
tpTC
tPWM1N

Propagation Delay
Low to High
High to Low
Matching ItpLH - tpHd
Temperature Coefficient
Minimum Pulse Width

Test CondHlons
VH"VL = SV; measured between
20% and 80% points.
With probe only as load
With orobe and transmission line
VH-VL = SV; measured between
20% and 80% points.
With probe only as load
With probe and transmission line
Load Is Probe Only
Amplitude = 0.8V (20% to 80%)
3V (10% to 90%)
5V (10% to 90%)
9V (10% to 90%\
Load Is Probe Only
Amplitude = 0.8V (20% to 80%)
3V (10% to 90%)
5V (10"k to 90%)
9V 110"k to 90%1
Amplitude = 0.8V
Amolitude = 5.0V

OS

Overshoot

0.5V < IVOH-VOLI < 5V

ts

Output Settling lime

IVOH-VOLI = SV;
To Within 3% of IVOH-Vod
To Within 1% of IVOH"VOLI

2=262

1.6
1.S

1.8
1.7

V/ns
V/ns

1.4
1.35

1.6
1.5

V/ns
V/ns

2S0
105

1.6

PS

MpPW

Typ

f = 10 MHz; VOH = +0.4V; VOL = -O.4V

VH - VL = 2.0V; pulse Width at which
amplitude drops by 50 mV,
measured between 50"k paints
Propagation Delay
2 ns < PW<98 ns;f= 10 MHz;
Variation with Pulse Widtl V~ = +O.4V· Vf'II = -O.4V
Preshoot
O.SV < IVOH-Vod < SV

Raytheon Semiconductor

Max

Min

Units

0.60
1.7
2.4
4.0

0.5
1.9
2.8
4.5

ns
ns
ns
ns

0.7
1.8
2.6
4.5
270
110

0.9
2.2
3.2
S.2

ns
ns
ns
ns
MHz
MHz

1.6
1.9
150
2

1.9
ns

ns

ps
psI"C

2.0

ns

-75

+75
15mV+
3% of VA
SOmV+
4% of VA
5
10

ps

mV
mV
ns
.ns

For More Infonnation, call 1-800-722-7074.

RC7311
Block Diagram

V HC

OF

VH

CIM1
Vo

VIN+
V1N-

CIM2
VEEO

VL
VLC

Gnd

TS

TST
65-5235A

For More Information, caJI1-800-722-7074.

Raytheon Semiconductor

2-263

RC7311

2-264

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC731srr
RC73lSlRC731ST
Three-StateATE Pin Electronics Driver
Features

General Product Description

• High output slew rate (1.8 V/ns typical)
• Wide output voltage range (-2.5V to +7V), and up to
9.5 Vp-p swings
• Three-stale/high impedance output
• High repetition rate (250 MHz for ECl swings)
• Low output offset (20 mV typ.) and output offset drift
(0.1 mV/oCtyp.).
• Low leakage (10 nA typ.) and low output
capacitance (3 pF typ.) in high impedance inhibit
mode
• RC7315TEl is pin-for-pin compatible with AD1322
• High speed differential inputs with wide common
mode range for ease of interface to ECl as well as
m and CMOS levels
• Output short circuit protection (Safe Operating Area
protection with current limiting and thermal
shutdown)
• 100 mA typo dynamic current drive capability
• Absolute slew rate control
• Available in 28-pin PlCC, or is-pin gullwing lead
package
• Packaged parts available in unterminated (RC7315)
or 50n series terminated (RC7315T) configurations

The RC7315 Pin Electronics Driver is designed for use
in all high speed ATE systems which require pin drivers
with three state capability and high slew rates. The
RC7315 has the ability to drive a 50n transmission line
of up to 2 feet in length with a slew rate of 1.8 V/ns and
repetition rate of over 250 MHz for ECl output levels.
These features, combined with a maximum output
swing of 9.5 Vp-p over the range of -2.5V to +7V,
provide this circuit with the ability to test TTL, CMOS,
ECl and GaAs devices. The high and low limits of the
output swing are set through the program pins VH and
VL, respectively. The transfer characteristic from the
program pins to the output pin is unity gain with very low
offset drift. The VH and VL inputs have been buffered to
operate with low bias currents (1 ~ typical) allowing
direct coupling to the output of a DAC.

Applications
•
•
•
•
•
•
•

ATE Pin electronics driver
Precision waveform generator
level translator
Differential line receiver
General purpose driver
Laser driver
CRT preamplifier

When the RC7315 is used on an VO pin, it may be
forced into the high impedance state through the INH+
and INH- differential inputs. In the high impedance
state, excellent isolation is provided between the output
of the disabled driver and the pin by virtue of low driver
output capacitance (3 pF typical) and low output
leakage (10 nA typical).
The RC7315 is provided with high speed differential
ECl inputs for ease of interface with the differential ECl
outputs of a timing generator. The inputs have a voltage
range of -2V to +6V, so that if required, an input may be
driven by m or CMOS devices provided that the other
input is tied to the appropriate threshold value. The pin
driver is available in unterminated RC7315 or 50n
series terminated RC7315T configurations. The
RC7315TEl is pin-for-pin compatible with the Analog
Devices AD1322 driver.
The RC7315 is implemented using Raytheon's high
frequency complementary bipolar process.

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

2-265

RC731srr
Pin Definitions
Name
Vee

Function
Quiet positive supply. The nominal value is
1OV ±3%. For output high voltage levels (VOH )
greater than the nominal value of +7V, Vee
should be raised 3V above the maximum value
of VOH' Whenever VEE is lowered to provide
margin at the output low level, Vee should
also be lowered by the same amount. Vee
should be bypassed to ground with a 10,000
pF chip capacitor placed as close to the pins
as possible.

VEE

Quiet negative supply. The nominal value is
-5.2V ±5%. For output low voltage levels (VOL)
less than the nominal value of -2.2V, VEE
should be lowered 3V below the minimum
value of VOL' Whenever Vee is raised to
provide margin at the output high level, VEE
should also be raised by the same amount.
VEE should be bypassed to ground with a
10,000 pF chip capacitor placed as close to
the pins as possible.

Veeo

Positive supply for the RC7315 output stage.
This supply is brought out separately to
minimize the supply noise generated when the
output switches. Veeo should be bypassed to
the ground plane with a 10,000 pF chip
capacitor placed as close to the pin as possible and then immediately connected to Vee.

VEEO

Negative supply for the RC7315 output stage.
This supply is brought out separately to
minimize the supply noise generated when the
output switches. VEEO should be bypassed to
the ground plane with a 10,000 pF chip
capacitor placed as close to the pin as possible and then immediately connected to VEE'

CI+

Output stage positive supply decouple for
TC7315TEL only. CI+ should be bypassed to
the ground plane with a 1,000 pF chip capacitor placed as close to the pin as possible.

CI+

Output stage negative supply decouple for
TC7315TEL only. CI_should be bypassed to
the ground plane with a 1,000 pF chip capacitor placed as close to the pin as possible.

GND

2·266

Chip ground. Should be connected to the
printed circuit board's ground plane at the pin.

Name
VH

Function
Analog program input that sets the output high
level (VOH)' The transfer characteristic from
VH to VOH is nominally unity gain.

VL

Analog program input that sets the output low
level (VOL)' The transfer characteristic from VL
to VOL is nominally unity gain.

CVOL
CVOH

Bypass capacitor for VOH and VOL respectively. Pins CVOL and CVOH should be bypassed to the ground plane with a 1,000 pF
chip capacitor placed as close to the pin as
possible.

VIN+
V,N_

Differential digital inputs. The output will
toggle between the two levels dictated by VH
and VL as the differential signal is switched.
Although these inputs are normally driven by
ECL signals, they have a wide enough common mode range that anyone of the inputs
may be driven by a TTL or CMOS signal
provided that the other input is tied to the
appropriate threshold voltage.

Vo

Driver output on RC7315. The output impedance is Sn:fQU The output is usually back
terminated in the characteristic impedance of
the transmission line it drives. For a 50n line, a
40n ±1 % resistor should be placed externally
as close to the output pin as possible to
minimize reflections and ringing. The resistor
should also be able to dissipate o.sn to
sustain the short circuit current of the output.

VOTERM Driver output on RC7315T. This version is
packaged with an internal back termination
resistor. The output impedance Is 50n:fQ.5U
INH+
INH-

Differential digital inputs. When INH is true
(i.e. IHN+ > INH-), the driver is forced into the
high impedance state. Although these inputs
are normally driven by ECL signals, they have
a wide enough common mode range that any
one of the inputs may be driven by a TTL or
CMOS signal provided that the other input is
tied to the appropriate threshold voltage.

SRCA

Slew rate control for both edges. Slew rate of
both rising and falling edges decreases as the
control current is changed from 0 mA to -0.5
mA. SRC can be programmed with a current
DAC or set to a fixed value using a resistor.

Raytheon Semiconductor

For More Information, call 1-800·722·7074.

RC7315!f
Pin Definitions (continued)

Ordering Information

Name
SRCM

Function
Increases the speed of the falling edge to match
the rising edge

Part Number

Package

Operating
Temperature
Range

TS

Active low oulput notifies thermal shutdown has
occurred. In the event of a short circuit or other
fault that causes the die temperature to become
excessively large, the thermal shutdown will
kick in at a die temperature between 115°C and
160°C. If the fault persists, the device will toggle
back and forth between shutdown and norm~
operation at a frequency in the tens of Hertz. TS
is an open collector oulput c~ble of driving
two standard m loads. The TS pins of several
drivers may be wire-ORed together and input to
a latch to indicate an alarm condition.

RC73150A
RC7315TEL
RC7315TAEL

OA
EL
EL

OOC to +70°C
O°Cto +70°C
OOC to +70OC

NC

Notes:
QA • 28-pin PLCC
TEL .. 16-pin Gullwlng, 50ntermination (AD1322 pinout)
TAEL. 16-pin Gullwing, 50Q termination

No connection.

Connection Information
28-pin PLCC
(Top View)
4 3 2 1 282726

16-pin Ceramic Leaded Chip Carrier
with Gullwing Leads
(Top View)

'-"

5
6
7
8
9
10
11

1
2
3
4
5
6

25
24
23
22
21
20
19

RC7315T

7
8

12131415161718
65-5741
Pin Function
1
GND
2 Vee
3 SRCM
4 VEE
5 VEE
6 VOUT
7 SRCA
8 NC
9 Veeo
10 VEEO
11 VEE
12 VEE
13 VL
14 NC

Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Function
TS
VH
CVOL
VEE
VEE
CVOH
VIN _
VIN+
INHINH+
VEE
VEE
NC
NC

For More Information, call 1-800-722-7074.

16
15
14
13
12
11
10
9
65-5313

RC7315TEL
Pin
Function
1
GND
2
NC
3
VOTERM
4
NC
5
CI+
CI_
6
VL
7
DNC·
8
GND
9
10
VH
VIN _
11
12
VIN+
13
INH14
INH+
15
VEE
16
Vee
"DNC = Do Not Connect

Raytheon Semiconductor

RC7315TAEL
Pin
Function
1
GND
2
SRCM
3
VOTERM
4
SRCA
DNC·
5
DNC·
6
7
VL
TS
8
9
GND
10
VH
VIN _
11
12
VIN+
13
INH14
INH+
15
VEE
16
VCC

2-267

RC7315/r
Absolute Maximum Ratings (1)
Positive power supply, Vee ...................................... 13V
Negative power supply, VEE .................................. -8.2V
Difference between Vee and VEE ............................ 17V
Input voltage at VIN+' VIN_' INH+, INH- ........... Vee -12V,
VEE +12V
Input Voltage at VH, VL .................................. Vee -13V,
VEE +13V
Differential input voltage, IVIN+ - VINJ, IVINH+ - VINHJ ..... 6V
Difference between VH &VL (IVH - VLI) ................... 11V
Input voltage at SRCA ....................................... -3V1+7V
Slew rate control current .................................... -2.0 rnA
Driver Output Voltage ..................................... Vee -13V,
VEE +13V
Output voltage at TS .............•.................•....•.........•...5V
Duration of short-circuit to ground ..•••...•....••.•..• Indefinite
Operating temperature range •...••....•...••....• OOC to +70OC
Storage temperature range ................... -65OC to +1250C
Lead temperature range
(Soldering 10 seconds) .................................. 300OC

Notes:
I. •Absolute maximum ratings· are those beyond which the safety
of the device cannot be guaranteed. They are not meant to
imply that the device should be operated at these limits. If the
device is subjected to the limits in the absolute maximum
ratings for extended periods, its rerlability may be impaired. The
tables of Bectrical Characteristics provide conditions for actual
device operation.

Recommended Operating Conditions
Symbol
Te
Vee
VEE
Vee-VEE
VOH,VOL
VOWVOL
RT

2-268

Parameters
Case operating temperature
Positive supply voltage
Negative supply voltage
Difference between positive and negative supply
Range for output high level and output low level
Output amplitude
Output back-termination resistor (RC7315 only)

RSy1heon Semiconductor

Min

9.7
-5.45
-2
0.3
38

Typ
25
10.0
-5.2
15.2

41

Max

10.3
-4.95
15.8
7.0
10.0
42

UnHs
°C
°C
V
V
V
V

n

For More Information. call 1-800-722-7074.

RC731srr
DC Electrical Characteristics
vcc =10V :I:B%. VEE =-S.2V 15%. TA =2SoC (still air) and the load is a SO n transmission line with 2.0 ns one-way

delay. unless otherwise specified. The transmission line is back-terminated in son (15%) using either the internal
termination resistor (RC7315T) or an external resistor (RC731S).
Parameters
Test Conditions
Differential Inputs
VIN. , VIN., VINJoI. , VIN....
VIM.• VIM_ Absolute Voltage@ Data Inputs
Absolute Voltage @ Inhibit
"'NH+'
Inputs INH+. INHVIMI-!_
Differential Input Ranoe
IV,M - VI~,J
VJn
Differential Inhibit Input Range
VOINH
IV INH... - V'NH-I
Input
Bias
Current
@
Data
'IN+.IIN.
Inputs
-2V S VIN+' VIN_ S +6V
Input
Bias Current @ Inhibit
IINH+' IINHInputs
-2V S VINH+' VINH- S; +SV
Absolute Slew Rate Control Input SRCA
VSRCA
Compliance Voltage Range
Control Current Range
'SRCA
Matching Slew Rate Control Input SRCM
VSRCM
Compliance Voltage Range
Control Current Range
'SRCM
Voltage Program Inputs
VH,VL
VH
VH Range
VCC =10V; VEE =-S.2V
VCC =12V; VEE =-3.2V
VCC =BV; VEE =-7.2V
VL
VL Range
Vr.r. =10V; VFF =-S.2V
Vee =12V; VEE =-3.2V
V(,;(,; =BV; Vr:r: =-7.2V
Bias Current@ VI-!
-W S VI-! S; +7V; VI =-2.0V
IH
Bias Current@ VL
-2V S; VL S; +SV; VH =6.0V
IL
TCI H
Temperature Drift in IH
VH =7.0V; 25°C S; TC S; 70°C
output not SWitching
TCIL
Temperature Drift in IL
VL =-2.0V; 25°C S; TC S; 70°C
outout not switch ina
L\lBDC
-WS;VHS;+7V
Variation in IH• IL with
DC voltage at VHor VL
-2V S; VL S; +6V
Symbol

VH,LBW

-3 dB bandwidth from VH
or VL to the output

For More Information, call 1-800·722·7074.

-1VS;VH S;+7V;
-2V S;VLS;+6V; VH-VL =2.0V

Raytheon Semiconductor

Min

Max

Units

-2.0

+6.0

V

-2.0
0.4
0.4

+6.0
S.O
S.O

V
V
V

Typ

ECl
ECl
-100

~

-100

~

-2.0
-0.5

+2.0
+O.S

V
mA

-2.0
-O.S

+2.0
+O.S

V
mA

-2.0
0
-4.0
-2.5
-O.S
-4.5
-S
-S

+7.0
+9.0
+S.O
+6.0
+B.O
+4.0

V
V
V
V
V
V

-1

~

-1
-1

~

0.1

J,tAI°C

0.1

J,tAI°C

1

~

SO

kHz

2·269

RC731srr
DC Electrical Characteristics (confd)
Symbol

Vo

Parameters
Signal OUtput
V() V01BlM
Output Voltage Range

avOH

Amplitude
Offset to Oulput High Level

avOL

Offset to Output Low Level

VTC

Output Voltage Drift

fa

Gain Error

VA

Test CondHIons

MIn

Vee = 10V;VEE=-52V
Vee = 12V; VEE = -32V
Vee = 8V; VEE =-72V
IVarVod
VwO. no load; VL= -2V
WOH = IVH- VOHI
VwO. no load; VH= +7V
WOL = IVL - VOLI

-2.5
.(l.5
4.5
0.3

-1V~VOH~+7V;

Max

Units

+7.0
+9.0
+5.0
9.5

40

V
V
V
V
mV

20

mV

0.1

mVt'C

lYP

-2V~VOL~+6V
-1V~VOH~+7V;

tt

Unearity Error

Zour

Output IflllEldance

Izr..

Output Leakage Current in

loe
lAC
ICL
VTS

Trs
VSMAX
Vee
VEE
ICC
lEE
PSRVO
PSRVSL

TA

2-270

I 'our 5OmA

Inhibit Mode
DC Current Drive
AC Current Drive
Thennal Shutdown Output (lS)
Short Circuit Current Umit
TS Rag Oulput Level
Shutdown Die Temperature
Other
Maximum Rail to Rail
Supply Voltage
Positive Supply
Negative Supply
Positive Supply Current
Negative ~uppIy .(;urrent
Output Level Power Supply
Rejection Ratio
Output Slew Rate Power Supply
Rejection Ratio @ Vee
@VEE
Operating Temperature
Range

1

-2V ~VOL ~+6V
o~VOUTPUT ~ +5V
-2V ~ VOUTPUT ~ +7V
Vo (RC73150nly)
VOTERM (RC7315T only)
-1.0V ~VO~+5V

0.5
1.0
8
47.5

+5.0V~Vo~+7V

0.5

2

%VSET
%VSET
Q
Q

10
1

50
70

100

0.5
145

+8.0
-7.2

+12.0
-3.2

Raytheon Semiconductor

V
V
V
rnA

dB
dB

40
40
4
4
0
0

V

rnA

9U

Vee; IlVee =:fQ.5%
VEE;IlVE =:fQ.5%
VW 5V
and
IlVee=:fQOOmV
VL=OV IlVEE =:fQOO mV
StilfNr
Nr Row> 300 "r>m

f,IA
rnA
rnA

"C

17
+10.0
-5.2
85

nA

rnA

145
IOL =4rnA

Vce-VEE

%VSET

25
25

%
%

40
70

"C
"C

For More Infonnation, call 1-800-722-7074.

RC731Str
AC Electrical Characteristics

vee = 10V :!B%, VEE = -5.2V :15%, TA = 25°C (still air) and the load is a 50n transmission line with 2.0 ns one-way delay,
unless otherwise specified. The transmission line is back-terminated in 50n (:15%) using either the internal termination resistor
(RC7315T) or an external resistor (RC7315). The measurement probe is a high impedance FET probe with capacitance no
greater than 6 pF and resistance no smaller than 10 kn.
SYmbol Parameters
Slew Rate
SLR
(Slew rate not adjusted)

tR'
tF

Rise Time, and
Fall Time
(Slew rate not adjusted)

f

Toggle Rate

tpLH

Low to High Propagation Delay

tpHL

High to Low Propagation Delay

Test Conditions
VH - VL = SV; Measured

tos

Overshoot

O.SV < VA < 5.0V

ts

Output Settling Time

VA=SV;
To within 3% 01 VA
To within 1% of VA
VOH = 1V; VOL = -1V
Load = 100n 1115pF;

tpHZ
tpLZ
tpZH
tpZL
C7

Propagation Delay from Logic
Hiah to Inhibit Mode
Propagation Delay from Logic
Low to Inhibit Mode
Propagation Delay from Inhibit
Mode to logic High
Propagation Delay from Inhibit
Mode to Logic Low
Output capacitance in Inhibft Mode

For More Information, call 1-800-722-7074.

TYD

1.6

1.8

V/ns

1.S

1.7

V/ns

300
1S0

0.6
1.2
1.6
2.S
350
17S

ns
ns
ns
ns
MHz
MHz

1.6

ns

1.4
200

ns
ps

Max

Units

between 20% lmd 1'10% noint~.

With probe only as load
With probe and transmission
line
Load is Probe Only:
VA=1V (20% to 80%)
VA = 2V(10% to 90%}
V11 = 3V (10% to 90%)
VA=SV (10% to 90%)
Amolitude = 0.8V
Amplitude = 5.0V
1= 10 MHz; VOH = +O.4V;
V.O l = -O.4V
f = 10 MHz; VOH = +O.4V;
VOl = -D.4V
ItplH -tpHd

Propagation Delay Match
Propagation Delay Temperature
Coefficient
tPWmin Minimum Pulse Width
VH - VL = 2.0V; pulse Width at
which amplitude drops by
50 mV, measured between
SO%points.
t.tpPW Propagation Delay Variation
2 ns < PW < 98 ns;
with Pulse Width
f = 10 MHz; VOH = +0.4V;
VOL =-0.4V
Preshoot
0.5V < VA < 5.0V
tps
t.tp
tpTC

Min

Propagation delay is
measured to the point
at which voltage has
changed by 200 mY.

Raytheon Semiconductor

2
2.0

psl°C
ns

ps

±75
1SmV+
3% of VA
SOmV+
4% of VA

8
10
2.9

ns
ns
ns

2.9

ns

2.9

ns

2.9

ns

3

pF
2-271

RC731srr
Block Diagram

--------------------------------,L--o

I RC7315

I

I
I
I

GND

I-r----+----+--<==:J

+v.... (RC7315)
-v....

INH+
INH- C::>--r-------t_~~-.J

2-272

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC7316
RC7316
Three-StateATE Pin Electroni~ Driver
Features

General Product Description

• High output slew rate (3.2 V/ns) typical driving coax
• Wide output voltage range (-3.0V to +7V), and up to
9.5 Vp-p swings
• Three-statelhigh impedance output
• High repetition rate (550 MHz for ECl swings)
• low output offset (20 mV typ.) and output offset drift
(0.1 mV/"C typ.).
• Low leakage (10 nA typ.) and low output capacitance
(3.0 pF typ.) in high impedance inhibit mode
• 100 mA typo dynamic current drive capability
• High speed differential inputs with wide common mode
range for ease of interface to ECl as well as TIL and
CMOS levels
• Output short circuit protection (Safe Operating Area
protection with current limiting and thermal shutdown)
• Independently adjustable slew rate control available
on RC7316QA and RC7316TAEl package versions
• Available in 28-pin PlCC and 16-pin gullwing
packages
• RC7316TEl is pin-for-pin compatible with AD1321,
AD1322, and AD1324

The RC7316 Pin Electronics Driver is designed for use in
ultra high speed ATE systems which require pin drivers
with three state capability and high slew rates. The
RC7316 has the ability to drive a 500 transmission line of
up to 2 feet in length with a slew rate of 3.2 V/ns and
repetition rate of over 550 MHz for ECl output levels.
These features, combined with a maximum output swing
of 9.5 Vp-p over the range of -3.0V to +7V, provide this
circuit with the ability to test Th, CMOS, ECl and GaAs
devices. The high and low limits of the output swing are
set through the program pins VH and VL, respectively.
The transfer characteristic from the program pins to the
output pin is unity gain with very low offset drift. The VH
and VL inputs have been buffered to operate with low bias
currents (1 J.IA typical) allowing direct coupling to the
output of a DAC.

Applications
•
•
•
•
•
•
•

ATE pin electronics driver
Precision waveform generator
level translator
Differential line receiver
General purpose driver
Laser driver
CRT preamplifier

When the RC7316 is used on an 1/0 pin, it may be forced
into the high impedance state through the INH+ and INHdifferential inputs. In the high impedance state, excellent
isolation is provided between the output of the disabled
driver and the pin by virtue of low driver output
capacitance (3.0 pF typical) and low output leakage (10
nA typical).
The RC7316 is provided with high speed differential ECl
inputs for ease of interface with the differential ECl
outputs of a timing generator. The inputs have a voltage
range of -2V to +6V, so that if required, an input may be
driven by m or CMOS devices provided that the other
input is tied to the appropriate threshold value.
The pin driver is available in unterminated RC7316QA, or
500 series terminated RC7316 (TAEl or TEL)
configurations. The RC7316TEl is pin-for-pin compatible
with Analog Devices' AD1321, AD1322 and AD1324
drivers.
Independent control of the positive and negative slew
rates by an external voltage, current or resistors available
on RC7316QA and RC7316TAEl package versions. The
RC7316QA is packaged in a thermal enhanced 28 PlCC.
The RC7316 is implemented using Raytheon's high
frequency SiCMOS process.

For More Information, caJI1-800-722·7074.

Raytheon Semiconductor

2-273

RC7316
Pin Description
Name Function
Vee

VEE

Name Function

Quiet positive supply. The nominal value is 10V
:iG"1o. For ou1put high vottage levels (V011) greater
than the nominal value of +7V, Vee should be
raised 3V above the maximum value of V011'
Whenever VEE is towered to provide margin at the
oulput tow level, Vee should also be towered by the
same amount Vee should be bypassed to ground
with a 10,000 pF chip capacitor placed as dose to
the pins as possible.
Quiet negative supply. The nominal value is -52V
:l:5%. For oulput low vottage levels (VorJ less than
the nominal value of -2.SV, VEE should be lowered
3Vbelow the minimum value of VOL' Whenever
Vee is raised to provide margin at the ou1put high
level, VEE should also be raised by the sarne
amount VEE should be bypassed to ground with a
10,000 pF chip capacitor placed as close to the pins
as possible.

Veeo Positive supply for the RC7316 output stage. This
supply is brought out separately to minimize the
supply noise generated when the output switches.
Vceo should be bypassed to the ground plane with
a 10,000 pF chip capacitor placed as close to the pin
as possible and then immediately connected to
Vee·
VEEO Negative supply for the RC7316 output stage. This
supply is brought out separately to minimize the
supply noise generated when the output switches.
VEEO should be bypassed to the ground plane with
a 10,000 pF chip capacitor placed as close to the pin
as possible and then immediately connected to VEE'
GND

Chip ground. Should be connected to the printed
circutt board's ground plane at the pin.

VH

Analog program input that sels the output high level
(VOH)' The transfer characteristic from VHto V011 is
nominally untty gain.

VL

Analog program input that sels the output low level
(VOL)' The transfer characteristic from VL to VOL is
nominally unity gain.

V1N+
V1N-

Differential digital inpu1s. The ou1put will toggle
between the tNo levels dictated by VH and VL as
the differential signal is switched. Although these
inputs are normally driven by ECl signals, they
have a wide enough common mode range that any
one of the inputs may be driven by a TIl or CMOS
signal provided that the other input is tied to the
appropriate threshold vottage.

Vo

Driver ou1put on RC7316. The ou1put impedance is
1OO:i2n The ou1put is usually back terminated in
the characteristic impedance of the transmission
tine tt drives. For a 500 line, a 400±1 % resistor
should be placed extemally as close to the output
pin as possible to minimize reflections and ringing.
The resistor should also be able to dissipate 0.80
to sustain the short circutt current of the output.

INH+
INH-

Differential digital inputs. When INH is true (i.e.
IHN+ > INH-), the driver is forced into the high
impedance state. Although these inputs are
normally driven by ECl signals, they have a wide
enough common mode range that any one of the
inputs may be driven by a TIl or CMOS signal
provided that the other input is tied to the
appropriate threshold vottage.

+SRC Slew rate control for the positive edge. Slew rate of
the positive edge changes as the control voltage is
changed from -2.0V to +2.0V. +SRC can also be
programmed with a current DAC or set to a fixed
value using a resistor.
-SRC

Slew Rate Control for the negative edge. Slew rate
of the negative edge changes as the control voltage
is changed from -2.0V to +2.0V. -SRC can also be
programmed with a current DAC or set to a fixed
value using a resistor.

TS

flctNe low ou1put notifies thermal shutdown has
occurred. In the event of a short circutt or other fautt
that causes the die temperature to become
excessively large, the thermal shuldown will kick in
at a die terJl)erature between 115"C and 160"C. If
the fautt persisls, the device will toggle back and
forth between shutdown and normal operation at a
frequency in the tens of Hertz. TS is an open
collector ou1put capable of driving tNo standard TIl
loads. The TS pins of several drivers may be wireORed together and input to a latch to indicate an
alarm condition.

NC

No connection.

CvOL Bypass capacitor for V011 and VOL respectively.
CvOH Pins CVOL and CVOH should be bypassed to the
ground plane with a 1,000 pF chip capacitor placed
as close to the pin as possible.

2-274

Raytheon Semiconductor

For More Infonnation, caill-BOO·722-7074.

RC7316
Ordering Information
Part Number

Package

Operating
Temperature
Range

RC7316QA
RC7316TEL
RC7316TAEL

QA
EL
EL

O°Cto+70°C
O°C to +70°C
OOCto +70°C

Notes:
QA =28-pin PLCC, unterminated
TEL - 16-pin Gullwing, son termination (AD1322 pinout)
TAEL - 16-pin Gullwing, son termination

Connection Information
28-pin PLCC
(Top View)

16-pin Ceramic Leaded Chip Carrier
with Gullwing Leads
(Top View)

4 3 2 1 282726
'--'

5

25

6

24
23
22
21
20
19

7
8
9

10
11

----

16
15
14
13
12
11
10
9

12131415161718
65-5741

Pin Function
1
2

3
4

5
6
7
8
9

10
11
12
13
14

GNO
Vee
-SRC
VEE
VEE
VOUT
+SRC
NC
Veeo
V EEO
VEE
VEE

Vl

NC

65-5313

RC7315TEL

RC7315TAEL

Pin

Function

Pin

Function

Pin

Function

15
16
17
18

TS

1

1

2
3
4
5
6

GNO
NC
VOTERM
NC
C1+
CI_

2
3
4
5
6

GNO
-SRC
VOTERM
+SRC
ONC·
ONC·

7

VL

7

Vl

19
20
21
22
23
24
25
26
27
28

For More Information, call 1-800-722-7074.

VH
CVOl
VEE
VEE
CVOH
VIN_
VIN+
INHINH+
VEE
VEE
NC
NC

8

ONC·
9
GNO
10
VH
11
VIN_
12
VIN+
13
INH14
INH+
15
VEE
Vce
16
"ONC = 00 Not Connect

Raytheon Semiconductor

8
9

TS
GNO
10
VH
11
V IN _
12
VIN+
13
INH14
INH+
15
VEE
16
Vee
NC= No Connection

2-275

RC7316
Absolute Maximum Ratings (1)
Positive power supply, Vee ......................................... 13V
Negative power supply, VEE .....................................AI2V
Difference between Vee and VEE ............................... 16V
Input voltage at VIN+' VIN_' INH+,INH- ................ Vee -12V,
VEE +12V
Input Voltage at VH' VL ...................................... Vee -13V,
VEE +13V
Differential inputvottage, IVIN+ - VIN.!' IVINH+ - VINH-I ..... 6V
Difference between VH & VL (IVH - VLI) ....................... 11V
Input voltage at +SRC,-SRC ................................. -3V/+7V
Slew rate control current ........................................ -2.0 rnA
Driver Output Voltage ........................................ Vee -13V,
VEE +13V
Output voltage at TS ..................................................... 5V
Duration of short-<:ircuit to ground ......................... Indefinile
Operating terrperature range ......................... OOC 10 +70"C
Storage terrperature range ....................... -65"C to +125"C
Lead lemperature range
(Soldering 10 seconds) ..................................... 300"C

Notes:
1. "Absolute maximum ratings" are those beyond which the safety of
the device cannot be guaranteed. They are not meant 10 imply that
the device should be operated at these limits. If the device is
subjected 10 the limits in the absolute maximum ratings lor
extended periods. its reDability may be impaired. The tables of
Electrical Characteristics provide conditions for actual device
operation.

Recommended Operating Conditions
Symbol
Te
Vee
VEE
Vee-VEE
VOH,VOL
VOWVOL
RT

2-276

Parameters
Case operating temperature
.Positive supply voltage
Negative supply voltage
Difference between positive and negative supply
Range for output high level and output low level
Output amplitude
Output back-termination resistor (RC7316 only)

Raytheon Semiconductor

MIn
0
9.7
-5.45

Typ
25
10.0
-5.2
15.2

-3.0
0.1
41

Max
+70
10.3
-4.95
15.8
7.0
9.5

UnIts

°C
°C
V
V
V
V

I

For More Information. call 1-800-722-7074.

RC7316
DC Electrical Characteristics
Vee =10V :i!3%, VEE =-52V f5%, TA =25"C (still air) and the load is a 50n transmission line with 2.0 ns one-way
delay, unless otherwise specified. The transmission line is back-terminated in son (f5%) using an external resistor
(RC7316).
Symbol

VIN+, VIN"'JNH+,
"'JNHV10
V01NH

Test Conditions

Parameters
Differential Inputs
VIN+' VIN-' VINH+' VINHAbsolute Voltage@Data Inpuls
Absolute Voltage @ Inhibit
Inpuls INH+. INHDifferential Input Range

Max

Units

-2.0

+6.0

V

-2.0
0.4

+5.0
5.0

V

Min

lYP

ECl
V
IV1N+ - VIN-I
Differential Inhibit Input Range
0.4
ECl
V
5.0
IVINH~ - VINH-I
Input
Bias
Current
@
Data
Inpuls
-100
-3S
IIN+,IIN-2V ~ VIN+' VIN- ~ +6V
~
-SO
-1S0
~
IINH+' IINH- Input Bias Current @ Inhibit Inpuls -2V ~ VI~' VINH~ iOV
Positive Edge Slew Rate Control Input +SRC (Available on RC7316QA and RC7316TAEl only)
Compliance Voltage Range
-2.0V
V
+2.0
V..sRC
Negative Edge Slew Rate Control Input -SRC (Available on RC7316QA and RC7316TAEL only)
Compliance Voltage Range
-2.0
V
+2.0
V-SRC
Voltage Program Inputs VH, VL
VH
-3.0
V
VHRange
+7.0
Vee = 10V; VEE = -S2V
-1.0
V
+9.0
Vee = 12V; VEE = -32V
-S.O
V
Vcc =BV;VEE =-72V
+S.O
VL
-3.0
+6.0
V
VCC=10V;VEE =-S2V
VLRange
-1.0
+B.O
V
Vee = 12V; VEE = -32V
-5.0
+4.0
V
Vee = BV; VEE = -72V
Bias Current@VH
1.0
S.O
-1 V ~ VH ~+7V; VL = -3.0V
IH
~
Bias Current @ VL
-1.0
-S.O
-3V ~ VL~ +SV; VH = 6.0V
IL
~
TCIH
Temperature Drift in IH
VH = 7.0V; 2SOC ~ Tc ~ 70°C
0.1
J.JN'C
oulput not switching
TCIL
Temperature Drift in IL
0.1
VL = -3.0V; 2SoC ~ TC ~ 70°C
J.JN'C
oulput not switching
~IBDC
Variation in IH• IL with power
-1
1
-1VSVHS+7V
~
supply and DC voltage at VHor VL -2V~VL~+6V
-3 dB bandwidth from VH
kHz
50
-1V~VH~+7V;
VH,LBW
or VL to the oulput
-2V~VL~+6V;VK"VL =2.0V

For More Information. call 1-800·722·7074.

Raytheon Semiconductor

2·277

RC7316
DC Electrical Characteristics (confd)
Symbol

Parameters

Vo

Signal Output VOJ VOTERM
Output Voltage Range

VA
WOH

Amplitude
Offset to OJlput High Level

Wa..

Offset to OJlput Low Level

VTC

Output Voltage Drift
Gain Error
Unearity Error

£0
£t.

Units

20

+7.0
+9.0
+5.0
9.5
40

V
V
V
V
mV

20

40

mV

-1.0
-0.5
-1.0
B.O
-10

0.1
±O.5
±O.2
±O.S
10
±1.0

+1.0
+0.5
+1.0
12
+10

50
70

100

70

110

115

135

+B.O
-72

+10.0
-52

70
75
40
40

95
95

Vee = 10V; VEE =-52V
Vee = 12V;VEE =-32V
Vee = BV; VEE = -72V

-3.0
-1.0
-5.0
0.1

IVowVaJ
-1VsVHs+6V;VL =-2V
WOH=IVwVOHI
-2Vs VLs +6V; VH = +7V
Wa.. = IVL - Va..l
-1V sVOH s+7V;
-2VsVa..s+7V
OV s VOUTPUT s +5V
-2V s VOUTPUT s +7V

Output Impedance
Output Leakage Current in
Inhibit Mode
DC Current Drive
loe
AC Current Drive
lAC
Thermal Shutdown Output (TI3
DC Current Umit
leL
Output Low Level
Va..
Shutdown Die Temperature
TTS
Other
Rail to Rail Supply Voltage
Vs
Positive Supply
Vee
Negative
Supply
VEE
Positive Supply Current
ICC
Negative
Supply Current
lEE
PSRVO Oulput Level Power Supply
Rejection Ratio
PSRVSL Output Slew Rate Power Supply
Rejection Ratio @ Vee
@VEE
Operating Temperature
TA
Range

2-278

Max

Min

Zour
IZI..

1YP

Test Conditions

-2.0V s Vo s +6.5V

mVf'C
%VSET
%VSET
%VSET

I
nA

rnA
rnA

(Open Collector OutpUt)
Ia.. =4 rnA

Vee-VEE

Vee; IN ee = ±2.5%
VEE;~VEE =±2.5%
VH =5V I
and
I~Vee =±200 mV
VL =OV I~VEE=±200mV
Still Air
Air Flow> 300 Ifpm

Raytheon Semiconductor

0
0

130
0.5
160

rnA
V

17
+12.0
-32
rnA
rnA

V
V
V

"C

dB
dB

25

25

4
4
50
75

%
%
"C

"C

For More Information, call 1-800-722·7074.

RC7316
AC Electrical Characteristics
Vee = 10V ±B%, VEE = -5.2V ±50,'0, TA = 25°C (still air) and the load is a 500 transmission line with 2.0 ns one-way
delay, unless otherwise specified. The transmission line is back-terminated in 500 (±50,'0) using both internal and external
termination resistance. The measurement probe is a high impedance FET probe with capacitance no greater than 3 pF
and resistance no smaller than 10 k.Q.
Symbol Parameters
Slew Rate
SLR

V+SRC

V-SRC

tR'
tF

Positive SLR Control + SRC
Control Voltage Range
Slew Rate Change
Negative SLR Control -SRC
Control Voltage Range
Slew Rate Change
Rise Time, and
Fall Time

f

Toggle Rate
(Probe only)

tpHL

High to Low Propagation Delay

Atp
tpTC

Propagation Delay Match
Propagation Delay Temperature
Coefficient
Minimum Pulse Width

Test Conditions
VH - VL .. 5V; Measured
between 20% and 80% points.
With probe only as load
With probe and transmission
line
RC73160A & RC7316TAEL
VH = +5V, VL .. OV
RC73160A & RC7316TAEL
VH = +5V, VL= OV
CL =5.0 pF
VA=0.8V (20% to 80%)
VA=3V (10% to 90%)
VA = 5.V (10% to 90%)
Amplitude = 0.8 Vp-p
Amplitude = 3.0 Vp-p
Amplitude = 5.0 Vp-p
1 = 10 MHz; VOH = +0.4V;
VOL" -O.4V
ItpLH -tpHd

AtpPW

Propagation Delay Variation
with Pulse Width

tps

Preshoot

tos

Overshoot

0.5V < VA < 5.0V

ts

Output Settling Time

VA =5V;
To within 3% of VA
To within 1% 01 VA

For More Information, call 1-800-722-7074.

Typ

3.2

3.5

V/ns

3.0

3.2

V/ns

Max

Raytheon Semiconductor

Units

-2.0
0.5

+2.0
+3.5

V
V/ns

-2.0
0.5

+2.0
+3.5

V
V/ns

0.5
0.95
1.4
550
300
220

0.6
1.1
1.6

ns
ns
ns
MHz
MHz
MHz

1.8
70

20
100

ns
ps

500
275
200

ps/oC

2
VH - VL = 2.0V; pulse Width at
which amplitude drops by
50 mV, measured between
50% points.
CL =5.0 pF
2 ns < PW < 98 ns;
1 = 10 MHz; VOH" +0.4V;
VOL =-0.4V
0.5V < VA < 5.0V

tPWmin

Min

1.1

1.2

ns

70

100
15mV+
3% of VA
50mV+
4% of VA

ps

5.0
10.0

7.0
12.0

ns
ns

2-279

RC7316
AC Electrical Characteristics (continued)

vee = 10V ::f:3Ok, VEE = -S2V ±5%, TA = 25"C (still air) and the load is a soa transmission line with 2.0 ns one-way
delay, unless otherwise specified. The transmission line is back-terminated in soa (±5%) using both internal and external
termination resistance. The measurement probe is a high impedance FET probe with capacitance no greater than 3 pF
and resistance no smaller than 10 k.Q.
Symbol Parameters
Propagation Delay from Logic
tpHZ
High to Inhibit Mode
Propagation Delay from Logic
tpLZ
Low to Inhibit Mode
Propagation Delay from Inhibit
tpZH
Mode from Logic High
Propagation Delay from Inhibit
tpZL
Mode to Logic Low
Cz
Output capacitance in Inhibit Mode

Test Conditions
VOH = 1V; VOL =-1V
Load .. 100n
to 2.5V; Propagation
delay is measured
to the point at which
voHage has changed by
200 mV.

Min

Typ
1.5

Max
2.0

Units
ns

2.0

2.S

ns

2.0

2.S

ns

2.0

2.S

ns

2.5

3.0

pF

Block Diagram

-------------------------------,
RC7316

I

Ir--o

GND

I
>--!----I Offset Control h l - - - i

and
Switching

Slew Rate
Control i--E::----I------i'--<

j------, II

........_ - - 1
Buffer

1

+VSRC RC73160A &
-VSRCS RC7316TAEL
Only

>-....
--JIIVIr-t-r----t:=> VOTERJ RC7316TEL &
I 1 RC7316T: I
J RC7316TAEL

I I

I I

II
I

Only

II

Only

-------I---c::::>vo} RC73160A
: 1---------1--0 Vcoo
1-------1

I

1---------,--0 VEEO

_-_

........

INH-17-t-------I

Only
TS

....
65-52848

2-280

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC7331132
RC7331132
Active Load
General Product Description
The RC7331132 Active load IC's are designed for use in
high speed ATE systems. Both are fully monolithic
devices capable of loading the device under test with independently programmable sink and source currents.
Independent sink (ISINK) and source (lSOURCE) currents
are set by the voltage applied to control inputs VISINK
and VISOURCE• respectively. The control voltage inputs
(VISINK and VISOURCE) to output current conversion is
10 mA per volt with RSR and RSK equal to 1 k.U
This voltage to current conversion is performed within the
RC7331/32 Active Loads and the low bias current required (5.0 J.IA typ.) allows for the setting of output current
levels using a standard voltage output D/A Converter.
The RC7331 and RC7332 ActIve loads feature typical
linearity error of fD.1 % linearity errors. The tranSition between the output sink (lSINK) and source (ISOURCE)
current is controlled by a wide input range commutation
voltage (VCOM) (-3.0V to +7.0V). Switching occurs when
the device under test output VDUT slews above or below
the programmed VCOM'
When the RC7331/32 are used on an ATE pin, they may
be forced into a high impedance state through the high
speed differentiallNH+ and INH- inputs. In the high impedance state, excellent isolation is provided between
the output of the disabled driver and the pin of the OUT,
by virtue of the low output capacitance (2 pF typ.) and
low output leakage current (100 nA typ.).
The INH+ and INH- differential inputs are normally driven
by ECl Signals. However they have a wide common
mode voltage range of -2V to +6V, so that if required, an
input may be driven by TIL or CMOS input levels provided that the other input is tied to the appropriate threshold
value. The switching speed between IOH' IOL and the
inhibit mode is 1.5 ns typo enabling the RC7331/32 to be
compatible with Raytheon's 250 MHz RC7311 and
RC7315 Pin Drivers.

For More Information. call 1-800-722-7074.

The RC7331 El is pin-for-pin compatible with the Analog
Devices' AD1315 Active Load. The RC7331 QA comes
in a thermally enhanced 28 PlCC package.
The RC7332 ActIve load is a lower cost version and
provides the capability to set maximum ISINK and
ISOURCE current with two extemal resistors, RSR and
RSK.

Features
+ ±so mA voltage programmable current (RC7331)
+ Independent programmable control of sink and
source current values
+ fD.1 % Output current resolution, ±1.5% typical gain
error, and fD.1% typical linearity error
+ 2 pF typical output capacitance
+ Low current leakage in inhibit mode (100 nA)
+ Low output current temperature drift 2.0 J,LAI"C
+ Wide commutation voltage range (-3.0V to +7V)
+ Fully monolithic device (including Schottky diodes)
+ 1.5 ns typical propagation delay
+ Operates on -5.2V and +1 OV supplies
+ Inhibit control digital inputs have wide voltage range
for ECl, m or CMOS compatibility
+ RC7331 is available in 16-pin Gullwing. pin-for-pin
compatible with Analog Devices' AD1315
+ RC7332 is available in 2B-pin PlCC thermal
enhanced package
+ Fast settling time of 12 ns typical at ±SO rnA.

Applications
+ ATE pin measurement electronics
+ Instrumentation

Raytheon Semiconductor

2-281

RC7331/32
Pin Definitions
Name

FunctIon

Name

Function

VCC

Quiet positive supply. The nominal value is 10V
±5%. V+ should be bypassed to ground with a
10,000 pF chip capacitor placed 9S close to the
pins 9S possible.

ISINK

VEE

Quiet negative supply. The nominal value is 5.2V ±5%. V_ should be bypassed to ground with
a 10,000 pF chip capacitor placed 9S close to the
pins 9S possible.

In the inhibit mode programmed sink current is
steered to this pin. ISINK may be connected to
any potential voltage between .!JV and +7V. tt is
typically connected to the VCOM programming
voltage point A connection to GND is possible
although not recommended in order to keep
ground transient currents to a minimum.

'our

This pin is connected to the DUT.

RSR

This pin is used to connect an external resistor
which establishes the ISOURCE maximum
current range. It is recommended to use 0.1% or
better maximum tolerance resistors to achieve
:1:2.5% or better accuracy. The other end of this
resistor is tied to ground.

RSK_
RSK+

This pin is used to connect an external resistor
which establishes the ISINK maximum current
range. It is recommended to use 0.1% or better
maximum tolerance resistors to achieve :1:2.5%
or better accuracy.

NC

No connect

GND

Device ground. This pin should be connected to
the printed circuH board's ground plane at the
pins.

VI SINK

Analog DC voltage input which sets the sink
current value. VISINK control voltage to output
current conversion is ~ 0 NV ( e.g., VISINK =
5V,Iour = -50 rnA, RSr= 11q.

VISOURCE Analog DC voltage input which sets the source
current limit VISOURCE control voltage to output
. .IS R
10 NV( e.g.,
current conversIOn
VISOURCE
SK
= 5V, lOUT = 50 rnA, RSR = 1Iq.
VCOM

Commutation analog DC voltage input which sets
the transition point voltage where switching
between forced sink or source current occurs.

INH+
INH-

Differential digHaJ inputs. lNhen INH+ is true (i.e.
INH+ > INH-), VDUT input is forced into a high
impedance state. Although these inputs are
normally driven by ECl signals, they have a wide
enough common mode range that anyone of the
inputs may be driven by a TIL or CMOS signal
provided that the other input is tied to the
appropriate threshold voltage.

'SOURCE In the inhibit mode the programmed source
current is steered to this pin. ISOURCE may be
connected to any potential vottage between .!JV
and +7V.1t is typically connected to the VCOM
programming voltage point A connection to GND
is possible although not recommended in order to
keep ground transient currents to a minimum.

2-282

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC7331132
Ordering Information
Part Number

Package

RC73320A
RC7331EL

Operating
Temperature
Range

OA
EL

Notes:
QA • 28-pin PLCC

EL • 16-pin Gullwing

Connection Information
28-pin PLCC
(Top View)

16-pin Ceramic Leaded Chip Carrier
with Gullwing Leads
(Top View)

4 3 2 1282726

1
2
3
4
5
6
7
8

~

5

25
24
23

6
7
8
9
10
11

22

21
20
19
12131415161718

16
15
14
13
12
11
10
9

85-5741"
65-5313

RC7332QA1
PlnFunction
1 GND
2
VCC
-SRC
3
4
VEE
5
VEE
6 VOUT
7
+SRC
8
NC
9
Vcce
10 V EEO
11 VEE
12 VEE
13 VL
14 NC

Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Function
TS
VH
CVOL
VEE
VEE
CVOH
V IN _
VIN+
INHINH+
VEE
VEE
NC
NC

RC7331EL
Pin

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Function
ISOURCE
VCOM
lOUT
VEE
ISINK
VISOURCE
GND2
GND
VI SINK
NC
NC
NC
VCC
INH+
INHNC

Notes:
1. On RC73320A package, VIS1NK input is tied to the other end of the limiting resistor tied to RSI---.-,-0 ISINK

VI SINK D---t---l

-"J--;r--r'
'---'VV'u
65-5591

Notes:
1. RSR and RSK are required only for the RC7332.
2. The RSR, RSK·, and RSK+ pins are not provided on the RC7331. RSR and RSK
are 1 K and provided internally.

2·286

Raytheon Semiconductor

For More Information, call 1-800·722·7074.

RC7341142
RC7341/RC7342
High Speed Dual Comparator
2.0 ns Propagation Delay
Description

Features

111e RC7341/42 is a very high speed dual comparator with
Ia1ched input option and ECL compatible outpuls capable of
drMng 500 terminated Ones. 1he RC7341 is configured as a
windows COJ'Tl)arafor whereas the RC7342 is configured as
lY.O independent comparators and is pin for pin corrpatibIe
with the industry standard 9687 corrparalors. 1he RC73411
42's low ~ation delay (2.0 ns maxirrum), wide input
common range (4Vto-+8V) and low bias current (±10 JJA
maximum) makes it ideal to for monitoring ou1puls from TTl,
CMos. ECl and even GaAs devices In ATE applications.

• 12 V max differential input voltage
• Low propagation delays: 2.0 ns maxirrum
• Low delay dispersion (±1oo ps lypicaI) and drift (4 psfC
typicaij
• :i5 mV maximum input offset and 10 IlVfC max. drift
• ±2 JJA typical bias current; ±SO pA typ. in disable mode
• Common mode rejection ~ 60 dB
• Input dISable mode (transparent to user)
• 2 pF maximum Input capacitance (RC7341)
• Latch function
• Available with common threshold input VIAtB window
compara1or (RC7341) or lY.O independent COJ'Tl)arafors
(RC7342)
• RC7342 is pin for pin compatible with 9687 comparators
• Available In 16-pin SOIC, 2O-pin PlCC or 16-pin P-DIP

111e propagation delay dISpersion is only ±1 00 ps (lypicaI).
111e RC7341/42 features a high impedance input mode (10'
that reduces the bias current to ±SO pA (lypicaI), effectively
removing the DC electrical load of the comparalor inputs.
1he RC7341/42 also has a latch function to sample the input
waveforms. Latches A and B are controOed by differential
latch enable (LEA and LEB) ECL signals.
111e RC7341/42 is fabricated using Raytheon's high
performance corTlJIernentary bipolar process.

For More Information, call 1-800-722-7074.

Applications
• ATE Pin Electronics
• 1hreshoIdIPeak Voltage Detector
• Level Une Receiver
• Umitlng AmpOfier

Raytheon Semiconductor

2-287

RC7341142
Ordering Information
Part Number

Package

Operating
Temperature
Range

RC7341PN
RC7341QC
RC7341QCA
RC7341KM

PN
QC
QCA
KM

O°C to +70OC
O°C to +70OC
O°C to +70OC
O°Cto +70OC

RC7342PN
RC7342QC
RC7342KM

PN
QC
KM

OOC to +70OC
OOC to +70°C
OOC to +70OC

Notes:
/8838 suffix denotes MIL-5TD-883, Level 8 processing
PN .. 16-lead SOIC
OC .. 20-lead PLCC
OCA =28-fead PLCC
KM = 16-lead PDIP

Connection Information for PLCC

Connection Information for DIP and SO

RC7341

RC7342

Notes:
1_ Input disable mode not available on RC7342 SOIC
and P-DIP package_
2_ RC7341QCA is pin-for-pin compatible with 8T681
except for· pins_
2-288

Raytheon Semiconductor

li--/---~{J

For More Information, call 1-800·722·7074.

Raytheon Semiconductor

v..

2-301

RC7351

2-302

Raytheon Semiconductor

For More Infonnalion, caJI1-800-722-7074.

RC73687
RC73687
High Speed Dual Comparator
2.2 ns Propagation Delay
Product Description

Features

The RC73687 is a very high speed dual comparalor with
latched input option and ECL compatible outpuls capable of
driving son terminated lines. The RC73687 is configured as
i'Ml independent comparators and is pin for pin corrpatible
with the industry standard 9687 comparators. The RC73687
low propagation delay (2.2 ns maximum), wide input
common range (-4V to i8V) and low bias current (151JA
maximum) makes it ideal to for monitortng outpu1s from m,
CMOS, ECl and even GaAs devices in ATE applications.
The propagation delay dispersion is only fBO ps (typical).

• 12 V max differential input voltage
(forVCc=+10V, VE~-5.2V)
• Low propagation delays: - 1.8 ns typical
• Low delay dispersion (±65 ps typical) and drift (4 pst'C
typical)
• 15 mV maximum input offset and 10 I!VfC max. drift
• f31JA typical bias current; 50 pA typo in disable mode
• Commonmoder~~on~70dB
• Input disable mode (transparent to user)
• Latch function
• RC73687 is pin for pin compatible with 9687
comparators
• Available in 16-pin SOIC, 20-pin PlCC or 16-pin P-DIP

The RC73687 features a high irrpeclance input mode (10)
that reduces the bias current to 150 pA (typical), effectively
removing the DC electrtcalload of the comparalor inputs.
The RC73687 also has a latch function to sample the input
waveforms. Latches A and B are controlled by differential
latch enable (lEA and lEB) ECl signals.
The RC73687 is designed to operate with VCC supply
voltages of +5.0V to +1 OV.

Applications
•
•
•
•

ATE Pin Electronics
Threshold/Peak Voltage Detector
Level Une Receiver
Umiting Amplifier

Operation at +1 OV will provide a wider input common mode
voltage range, (-4V to i8V) versus (-4V to +3V). It also
provides a lower input capacitance (1.0 pF) versus (1.5 pF)
The RC73687 is fabricated using Raytheon's high
performance corrplementary bipolar process.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

2-303

RC73687
Absolute Maximum Ratings(1)
Positive power supply. Vee ............................... +12V
Negative power supply. VEE ................................ -7V
Difference between Vee and VEE ....................... 19V
Input voltage at V'A+' V,B+ .......................... Vee +0.7V
Input voltage at V'A_' V,S- ............................. VEE -C.7V
Differential input voltageIV,A+ - V,A_I' IV,B+ - V,S_I' 16V
input voltage at LEA, LEB ................................... Vee
Input voltage at LEA. [EB ................................... VEE
Input voltage at '0+' ' 0_.................................. Vee. VEE
Differen~al input voltage .................... ILEA - LEAl. 7V
ILEB - LEBI. 7V

110 - V'OTHI. 7V
Operating temperature range .......... '" -40°C to +85°C
Storage temperature range .............. -65OC to +125°C
Lead temperature range (solder 10 sec.) ......... 260OC

Notes:
1. 'Absolute maximum ratings' are those beyond which the safety
of the device cannot be guaranteed. They are not meant to
imply that the device should be operated at these limits. If the
device is subjected to the limits in the absolute maximum ratings
for extended periods. its re6abi6ty may be impaired. The tables
of Electrical Characteristics provide conditions for actual device
operation.

Ordering Information
Part Number

Package

OperatIng
Temperature
Range

RC73687PN
RC736870C
RC73687KM

PN
QC
KM

O°C to +70OC
OOC to +70OC
O°C to +70°C

Notes:
PN - 16-lead sOle
ae - 20-lead PLee
KM - 16~ead PDIP

Connection Information
PLCC

GND

SO and P-DIP
(300 mil wIde)

GND
LEB

RC73687

CiA
GND

RC73687
V 10TH

IEB

vee

Note: Input disable mode not available on RC73687
SOIC package.

2-304

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC73687
Pin Definitions
Pin No.

Function

Vee

Quiet positive supply. The nominal voltage is 1OV ±3%. Vee should be bypassed to ground with a 0.01
chip ceramic capacitor placed as close to the pins as possible.

J.lF

Quiet negative supply. The nominal voltage is -5.2 :1:5%. VEE should be bypassed to ground with a 0.01
chip capacitor placed as close to the pins as possible

J.lF

GND

Chip ground. This pin should be connected to the printed circuit board's ground plane at the pin.
Differential non-inverting inputs

Differential inverting inputs

LEA,LEB
LEA,LEB

Differential digital enable inputs for latches A and B. Although these inputs will be normally driven
by ECL signals, they have a wide enough common and that they may be driven by a TTL or CMOS Signal
provided the other input is tied to the appropriate threshold. If LEA or LEB inputs are tied to a logic high,
then latches A and B are transparent and output A or B, will track changes to comparator A or B
respectively. A logic low on LEA or LEB will disable the latch, and the oulputs will reflect the input state just
prior to the latch disable command.
10 is the differential non-inverting input and V10TH is the Inverting input for enabling/disabling the
comparator. Although the inputs will normally be driven by ECL signals, they have a wide enough common
mode range that they may be driven by a TTL or CMOS signal provided the other input is tied to the
appropriate threshold. When 10 and V10TH pins are left open they remain internally biased a +2.5 volt and 1.3 volts respectively and the circuit defaults to a comparator input enable state. A differential voltage of
400 mV must be exceeded to disable the comparator input. The disabled inputs will have a typical bias
current of :1:50 pA.

OA,OA

Differential oulputs for comparator A.

OB,OB

Differential oulputs for comparator B. Each comparator can drive 50Q terminated lines to 2 Vn .

For More Information, call 1-800·722·7074.

Raytheon Semiconductor

2-305

RC73687
Recommended Operating Conditions
Symbol
Te
Vee
VEE
Vee-VEE
RT
Vrr
VH

Parameters
Case operating temperature
Positive supply voltage
Negative supply voltage
Difference between positive and negative supply
Output termination load resistance
load termination supply voltage
latch input threshold voltage

MIn
0
4.75
-5.45
45
-3.0
-1.25

Typ

Max
70
5.25
-4.95
15.8
100
-2.0
-1.35

5.0
-5.2
15.2
50
-2.0
-1.3

UnHs

°c
V
V
V

n
V
V

DC Electrical Characteristics (Normal Operating Conditions)
Vee =+5V ±3%. VEE =-S.2V ±5%. TA =25OC.
Symbol

VIA+' VIA_
V'B+' V,B_
V,AO' V,BO
Vo
TCVo
flX+. flX_

Parameters
Differential Analog Inputs
V'A+' V,A_. VIB+' VIB_
Absolute Input Voltage
(Input Common Mode Range)
Differential Input Range
Input Voltage Offset
Input Voltage Offset Drift
Input Bias Current

Test Conditions

Min

Typ

-4.0

,x

IV + - V,X-l
±2
Enabled Mode

±5.0

Disabled Mode
Enabled Mode

±50
1.0
1.0

Max

UnHs

+3.0

V

±7.0
V
±S
mV
10 JlVrC
±10
JlA

JlA
'OIB
'BOFFSET
VIA+' VIA_
VIB+' VIB _
ZI
CMRR

VIM. VIA_
VIO
'0
VOH
VOL
lee
'EE
PSRR

2-306

Input Bias Current
Input Bias Current Offset
Analog Input Capacitance

Input Impedance
Common Mode Rejection Ratio -2Vto +2V
DIgItal Inputs
(Latch & DIsable)
Absolute Input Voltage
Differential Range
IV10+ - V10-'
Digital Input Current
DigItal Outputs
Output Voltage High
Output Voltage low
Power Supply
Positive Supply Current
Negative Supply Current
Power Supply Rejection Ratio
Vee ±2.S%. VEE ± 2.S%

Raytheon Semiconductor

70

SOO
80

-2.0
0.4

ECl

pA

JlA
2.0

Kn
dB

60

V
V

+5.0
+5.0
20

JlA

-1.6

V
V

-1.0

24
40
70

pF

mA
mA
dB

For More Information. call 1-800-722-7074.

RC73687
AC Electrical Characteristics
vee =+5.0V ±3%, VEE =-5.2V :1:5%, TA =25°C.
Symbol
tpo
ts
to

Parameters
Propagation Delay
HtolandLtoH
Delay Slew Between
A and B Sides
Delay Dispersion

t.tpOTC
t.tpOTC

Prop. Delay Temp. Drift
Delta Prop. Delay with
Duty Cycle

tPWMIN

Minimum Pulse Width

ts

Data to latch enable
set uptime
latch enable to data in
hold time
latch enable to output
high or low
Active to Inhibit
Inhibit to Active

tH
tlPO
tiD
tiE

For More Information, call 1-800-722-7074.

Test Conditions

Min

(0.2 V/ns So Input slew rate So 2.0 V/ns)
ECl: VTH =-1V, +O.2Voverdrive;
VTl =-1.6V, -O.2V underdrive
rising and falling edges
TIL: VTH = +2.SV, +0.5V overdrive;
VTL =O.SV; -O.SV underdrive
rising and falling edges
0.01% and 99.99% duty cycle
SO kHz, Vlp_p =SV, VTH =2.5V
(10 ns between measurements)
o ~ Vs ~ 3V; VTHA =2.8V, VTHB =0.2V
tiS =2.S V/ns, IVoH - VoLI ~ 600 mVo_o

Typ
1.8

Max Units
2.2
ns

100

200

±150

ps

±1S0

ps

4
50

ps/°C
ps

1.0

1.0

ns

ns

TBD
1.S
5.0
10.0

Raytheon Semiconductor

ps

2.0

ns
ns
ns
ns

2-307

RC73687
Block Diagram

RC73687

LEA

LEA

Latch
A

t----L-o

OA

t----;'-()

OA

Latch

t---t-{)

OB

t---t-o

OB

B

__ J
Vee GND VEE LEB LEB

2-308

Raytheon Semiconductor

65-5266

For More Infonnation, call 1-800-722-7074.

RC73687
Addendum
DC Electrical Characteristics (High Supply Voltage Conditions)
Vee =+1 OV ±3%. VEE =-5.2V :1:5%. TA =25"C
Symbol

VIA+' VIA_
VIB+, VISV1AO• VIBO
Vo
TCVO
IIX+·IIX101B
ISOFFSET

VIM' VIA_
VIB+' VISZI
CMRR

VIA+' VIA_
VIO
'0

VOH
VOl
lee
lEE
PSRR

Parameters
Differential Analog Inputs
VIA+, VIA·, VIB+, VIB·
Absolute Input Voltage
(Input Common Mode Range)
Differential Input Range
Input Voltage Offset
Input Voltage Offset Drift
Input Bias Current
Input Bias Current
Input Bias Current Offset
Analog Input Capacitance

Test Conditions

Typ

-4.0
IVlx+ - Vlx.I
±3.0
Enabled Mode
Disabled Mode
Enabled Mode

Input Impedance
Common Mode Rejection Ratio -2Vto +2V
Digital Inputs
(Latch & Disable)
Absolute Input Voltage
Differential Range
IVID+ - VID-I
Digital Input Current
Digital Outputs
Output Voltage High
Output Voltage Low
Power Supply
Positive Supply Current
Negative Supply Current
Power Supply Rejection Ratio Vee :1:2.5%. VEE :1:2.5%

For More Information, call 1-800·722·7074.

Min

Raytheon Semiconductor

±7.0
:1:50
1.0
1.0

70

500
80

-2.0
0.4

ECl

Max

Units

+8.0

V

12
±10
10
±15

V
mV

40

60

70

~

pA
~

2.0

pF
K
dB

+5.0
+5.0
20

~

1.6

V
V

-1.0

24

~VI"C

V
V

rnA
rnA
dB

2·309

RC73687

2-310

Raytheon Semiconductor

For More Information, call 1-800·722·7074.

Section 2 -

Application Specific Standard Products

Instrumentation Products

Amplifier

AID Converter

Signal Processing

~~·~"4
Modern instrumentation calls for a wide variety of highperformance signal conditioning, acquisition, processing,
and synthesis components. Raytheon offers a wide
variety of standard products in all of these categories.
Moreover, the ASIC RPA160 tile arrays and RSC4000
Standard Cells enable you to tailor ICs to your system
specific requirements. Here are a few highlights from our
broad line of products.
In signal conditioning our amplifiers and amplifier cells
cover the spectrum up to 800 MHz, with very low noise
options as well. For acquisition, we have both highspeed NO converters and blazing fast comparators. If
low-power or battery operation is important, look at the
TMC1173 3V 10 Msps NO converter. It's perfect for

For Applications Information. call (619) 457-1000.
For Technical Uterature. call 1-800-722-7074.

4-,

D/A Converter

Amplifier
65-6231

handheld applications such as digital scopes. Our
Parametric Measurement Unit makes it easy to
assemble a low-oost DC measure.
Once the signal is acquired, we have the DSP functions
to analyze it, from Fast Fourier Transforms (FFTs) to
complex digital filters and mixers. If your instrument
needs to generate Signals, either for output or for
demodulation of acquired signals, the TMC2340 is a
great digital quadrature oscillator. For analog signal
generation, use our Signal Synthesis DACs, followed
again by high-performance amplifiers. For digital Signal
generation, use our high-speed, high current Pin Drivers
to drive ECl, Positive shifted ECl, TIL or CMOS levels.

Raytheon Semiconductor

2-311

Section 2 - Application Specific Standard Products

Instrumentation Products
convf
Rate
(Msps)

RMS/R~S

Product
TDC1035

ResoluUon
Bits
8

TDC1038

8

20

45

TDC1048
TDC1058

8
8

20
20

45
45

TMCl173·10
-05
TMCl175·20

8
8
8

10
5
20

45
45
45

-30
-40

8
8
9

30
40
30

45
45
48

TDC1049

SNR
(dB)

Package
B7,R3

Grade2
C,V

86, NS, R3,
C3, E1
BS,NS,C3,El
B6,NS, R3,
El
N2, M7, R3
M7,N2, R3
B2, N2,C3,
M7,R3
M7,N2, R3
M7, N2, R3, El
JO, J3, Cl, L1,
G8,El
Jl, GO, El

C,V
C, V,SMD
C
C
C
C,V
C,V
C,V
C, V,SMD

Notes
Peak digitizer. Digitizes peat( value of pulses as
narrow as 12 ns.
low power version of TDC1048.
Industry standard video AID.
New industry standard video AID. Single +5V
power supply. TDC1048 performance equivalent
Low power CMOS video AID with integral Track!
Hold. +2.7V to +3.3V power supply.
low power CMOS video AID with integral Track!
Hold. Includes D/A

ECl interface

Monolithic video AID, TTL interface. ±2V input range.
TDC1020
10
20
55
C,V
Notes:
1. Guaranteed. See product specifications for test cond~ions.
2. A = High refiability, Te = -55"C to 125"C. C = Commercial, TA = O"C to 70"C. V= MIL-STO.a83 Compliant, Te = -55"C to 125"C.
SMD = Available per Standardized MiI~ary Drawing, Tc = -55"C to 125"C.
3. A = High reliabil~y, Te = -20"C to 95"C.
Clock
Rate 1
Product
(MHz)
Digital Frequency Synlheslzers
TMC2340-1
25
20

Pin Drivers
RC7310
RC7311
RC7315
RC731S

Comparators

Frequency
Resolution
(Hz)

SFDR
(dB)

Output

Package

Grade

Noles

O.OOS
0.006

106
106

Dual 16 Bft
Dual 16 Bft

Gl,H5, L5
Gl,H5,L5

C,V
C,V

AM, FM, PM i~uts.
Quadrature outputs.

Slew Rate
1.2 V/ns
2V/ns

Voltage Range
-3.0 to +8V
-3.0 10 +8.0V

Output Swing
(p-p)
10 Vp-p
10V

1.8 V/ns
3.2 V/ns

·2.5107.5V
-3.0 10 7.0V

9.5V
9.5V

Output
Three Slate
No
No
Yes
Yes

PropagaUon Delay

Voltage Range

Input Bias Current

Input Capacitance

RC7341 (Window)
RC7342 (Dual)

2.0 ns
2.0ns

-4VI0+8V
-4VI0+8V

10).IA (over -4 to +8V)
10).IA (over -410 +8V)

2pF
1.25 pF

RC73687 (Dual)

2.2ns

-4Vlo +8V

5).IA

2pF

Force Voltage
Range
-5V to +15V

Force Current
Ranges
(4 Ranges)
:1500 nA to ±20 ).IA
±2 ).IA to ±200 ).IA
±10 J.tA 10 ±1 rnA
:1500 J.tA 10 ±40 rnA

Force Current
Resolution
:W.05%

Precision
Measurement Unit
RC7351

Accuracy
12 bits, 0.5%
gain error

Package
28PlCC
28 PlCC, lS LOCC
28 EPlCC
28 EPlCC, lS lDCC

Package

All are
available in

Package
28 PlCC

Notes:
1. Both the RC7342 and the RC73687 are pin-Ior-pin compatible with 9687 standard comparators.

3-312

Raytheon semiconductor

For Applications Information, call (619) 457·1000.
For Technical Ulerature, call 1-800-722-7074.

Section 2 - Application Specific Standard Products

Signal Synthesis

DDS

Q

Direct Digital Frequency Synthesis (DDFS) offers signal
flexibility and stability that is unattainable with analog
techniques. DDFS is the process whereby the digital
samples representing a desired analog signal are
computed. These samples are then fed to a D/A
converter for the construction of the analog signal. The
TMC2340 produces data representing baseband signals
up to 12.5 MHz (higher with aliasing or multiplexing
techniques) with a 0.006 Hz frequency resolution and
can change frequencies cleanly in 25 ns. It produces a
pair of 16-bit quadrature outputs.

For Applications Information, call (619) 457-1000.
For Technical Uterature, call 1-1100-722-7074.

V

The synthesizer can produce frequency modulation (FM)
or phase modulation (PM) simultaneously with amplitude
modulation (AM). It is carefully designed to drive the
TDC1012 signal syntheSis D/A converter, creating the
lowest-distortion digital synthesizer subsystem available
today.
Raytheon's new TMC22X9X Digital Video Encoders are
complete programmable video waveform synthesizers.
Incorporating DDFS to digitally generate a subcarrier, with
fully programmable horizontal timing, and three high·
precision output D/A converters on board, these encoders
are outstanding integrated test Signal generators. Built·in
colorbars and a modulated ramp are also included.

Raytheon Semiconductor

2-313

Section 2 - Application Specific Standard Products

Signal Synthesis Products
Clock
Frequency
Rate 1
Resolution
(MHz)
(Hz)
Product
Digital Frequency SynUlesizers
TMC234D-1
25
0.006
20
0.006

Product
Associated
TDC1041-1

ResoluUon
(bits)
D/A Converters
10
10
10
10
10
12
12
12

SFDR
(dB)

Output

Package

Grade

Notes

106
106

Dual 16 Bit
Dual 16 Bit

G1, H5, LS
G1, H5, LS

C,V
C,V

AM, FM, PM Inputs.
Quadrature outputs.

Dlff. Un
Error1
(±%)

COnv.
Rate1
(Msps)

Rise
Time1
(ns)

Package

Grade (2)

Notes

20
20

R3
R3

C

Low cost 10-bit video DIA m interface.

20
20
20
50

4
4
10
4
4
4
4
4
4
4

N6,R6
R3
R3
J7, N7, R3
J7, N7, R3
J7, N7, R3
J7,N7,R3
N7,R3

C
C, V,SMD
C, V,SMD
C,V
C

50
50
50

4
4
4

J7,N7,R3
J7, N7, R3
J7, N7, R3

C, V,SMD
C, V,SMD
C,V

TDC1112-3

12

0.048
0.096
0,.096
0.048
0.096
0.012
0.024
0.048
0.048
0.012

-2
-1

12
12
12

0.024
0.048
0.048

TDC331 0
TDC1141-1
TDC1012-3
-2
-1

12

40
50
50

20

CIOC~

Description
Product
Digital Video Generatora
TMC22X9X Digital Video Encoder

Size

Rate
(MHz)

lObi

30

Power1
(WaHs) Package
1.1

RO

C
C
C

C

Grade2
C

Single +5V power supply.
low cost 1D-bil video D/A
ECl interface.
Signal synthesis DlA.
70 dBc SFDR. Very low glitch.
Drives 25.Q direcUy.
TIL interface.
Signal synthesis D/A.. 70 dBc SFDR. Very
low glitch.
Drives 25QdirecUy. ECl interface.

Notes
AI-Digital Encoder. RGBlYCflCR'Coior Index I~.
NTSCIPAL ComposHe and 8-Video 0utp14.

Notes:
1. Guaranteed. See product specifications for test conditions.
2. c. Commercial, TA. 000 to 7000. V. MIL-5TD-883 cornpnant, TC. -5500 to 12500.
SMD • Available per Standardized Military Drawing, TC. -5500 to 12500

2-314

Raytheon Semiconductor

For Applications Iniormation. call (619) 457·1000.
For Technical Uterature, call 1-800·722-7074.

TMC2340
TMC2340
Digital Synthesizer
Dual 16-Bit, 25 MOPS

Description
The TMC2340 performs waveform synthesis, modulation,
and demodulation. When presented with a TTL clock
signal and user-selected 15-bit amplitude and 32-bit
phase increment values, the TMC2340 automatically
generates quadrature-matched pairs of 1S-bit sine and
cosine waves in DAC-compatible 1S-bit offset binary
format. If desired, these waveforms are easily phase or
frequency-modulated on-chip, and the amplitude input
facilitates gain adjustment or amplitude modulation.
Digital output frequencies are restricted only by the
Nyquist limit of clock rateJ2, with frequency resolution of
O.OOS Hz at the guaranteed maximum 25 MHz clock rate.
A new data word pair is available at the output every
clock cycle. All input and output data ports are registered,
with a user-configurable phase accumulator structure and
input clock enables to simplify interfacing. The phase data
range over a full 2TI radians. All signals are TTL
compatible.
Fabricated in Raytheon Semiconductor's OMICRON-CTM
one-micron CMOS process, the TMC2340 operates at
the 25 MHz maximum clock rate over the full commercial
temperature (0 to 70"C) and supply (4.75 to 5.25V)
voltage ranges, and is available in a low-cost 120 pin
plastic pin grid array. The MIL-STD-883 version, the
TMC2340L5V, is housed in a ceramic chip carrier and is
specified over the full extended (-55°C to 125°C) case
temperature range.

Features
•
•

•
•
•
•
•

Guaranteed 25 Msps pipelined data throughput rate
15-bit magnitude, 32-bit phase data input precision
1S-bit offset binary or 15-btt unsigned magnitude
output data format
Input register clock enables simplify interfacing
Low power consumption CMOS process
Single -+fJV power supply
Available in a 120-pin plastic pin grid array package
Compliant with MIL-STD-8838 in a 132-leaded
CERQUAD

Applications
•
•

Digital waveform synthesis, including quadrature
functions
Digital modulation and demodulation

TMC2340 Logic Symbol

ENA
AM(14_0)
ENP (1,0)

TMC2340
DATA OUTPUTS

DEI

PH (31-0)

FM

User-configurable phase accumulator for waveform
synthesis, frequency modulation or phase modulation
Amplitude input for gain adjustment and amplitude
modulation

For More Information call 1-800-722-7074.

•
•
•

PM

0810
eLK

Raytheon Semiconductor

21271A

2-315

TMC2340
Functional Block Diagram
AM 14-0)

ENA

FM

PM

15

AM

15

OBIQ)--..r~------~-'

0Eir---~

I (IS-D)

21272A

Functional Description
General Information
The TMC2340 converts Polar (Phase and Magnitude)
data into Rectangular (Cartesian) format. The first
transformed result is available at the outputs 22 clock
cycles after startup, with new output data available every
40ns. All input and output data ports are registered, with
input clock enables to simplify system bus connections.
The input ports accept 15-bit amplitude and 32-bit
phase data, and the output ports produce 16-bit
Rectangular data words in either 16-bit offset binary or
15-bit unsigned magnitude format. The 32-bit phase
accumulator handles high-accuracy (O.006Hz at the
maximum clock rate) phase increment values with
minimal accumulation error. The flexible input phase
accumulator structure supports frequency or phase
2-316

modulation, as determined by the input register clock
enable ENYP1, 0 and accumulator controls FM and PM.
The 16 MSBs (Most Significant Bits) of phase data are
used in the transformation itself.

Signal Definitions
Power
VOO, GNO

The TMC2340 operates from a single + 5V
supply. All power and ground pins must be
connected.

Clock
ClK

The TMC2340 operates from a single clock.
All enabled registers are strobed on the
rising edge of ClK, which is the reference
for all timing specifications.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2340
Inputs/Outputs
AM14-0

AM 14-0 is the registered peak amplitude
15-bit input data port. AM 14 is the MSB.

PH31-0

PH31-0 is the registered Phase angle
increment 32-bit input data port. The input
phase accumulators are fed through this
port in conjunction with the input enable
select ENP1, O. PH31 is the MSB.

115-0

015-0

115-0 is the registered X-coordinate 16-bit
output data port. This output is forced into
the high-impedance state when OEI = HIGH.
10 is the LSB. 115 will be "stuck at" logic
HIGH if OBIO=O.

where C is the Carrier register and M is
the Modulation register, and 0 = LOW,
1= HIGH. See the Functional Block
Diagram.
FM, PM

The user determines the internal phase
Accumulator structure implemented on the
next clock by setting the accumulator
control word FM, PM, as shown below:

FM, PM

Instruction

00
01
10
11

015-0 is the registered Cartesian
Y-coordinate 16-bit output data port. This
output is forced to the high-impedance
state when OEQ=HIGH. 00 is the LSB.
015 will remain at logic HIGH if OBIO=O.

where 0 = LOW, 1= HIGH. See the
Functional Block Diagram.
The accumulator will roll over correctly
when full-scale is exceeded, allowing the
user to perform continuous phase accumulation through 27r radians, or 360 degrees.

Controls
ENA

ENP1,0

ENP1,O
00
01
10
11

Data presented to the input port AM are
latched into the input registers on the
current clock when ENA is HIGH. When
ENA is LOW, the data stored in the register
remains unchanged.
The value presented to the PH input port is
latched into the phase accumulator input
registers on the current clock, as determined by the control inputs ENP 1 0, as
shown below:
'
Instruction

No accumulation performed
PM accumulator path enabled
FM accumulator path enabled
INonsensical} logical OR of PM and FM

OBIO

The format select control sets the numeric
format of the Rectangular data: offset
binary format when HIGH, and unsigned
when LOW. This is a static input. See the
Timing Diagram.

OEI,OEO

Data in the output registers are available at
the outputs of the device when the respective asynchronous Output Enables are LOW.
When OEX or OEY is HIGH, the respective
output port is in the high-impedance state.

No registers enabled, current data held
M register input enabled, C data held
C register input enabled, M data held
M register set to 0, C register input enabled

For More Information cafI1-800-722-7074.

Raytheon Semiconductor

2-317

TMC2340
Package Interconnections
Signal
Tvpe

Signal
Name

Power

Function

H5 Package Pins

L5 Package Pins
1,9,21,37,45, 53, 67, 87, 91,
99, 112, 120
5, 11, 12, 14, 17, 29, 33, 49, 75,
83, 86, 89, 95, 104, 108, 115, 116,
124, 129

VDD

Supply Voltage

GND

Ground

C3, E3, H3, L4, L6, L8, 111, Fll, Ell,
Cll, C8, C6
D3, E2, El, F2, G3, K3, L3, L7, Kll, Jll,
GIl, F12, E12, Dll, Cl0, C9, B7, C7, C5,
C4

Clock

CLK

System Clock

F3

13

Inputs

AM14-0

Radius Data

PH 31 -0

Phase Data

F13, G13, G12, H13, H12, Hll, J13, J12,
K13, K12, 113, 112, M13, M12, N13
110, N12, NIl, Ml0, L9, Nl0, M9, N9,
M8, N8, N7, M7, N6, M6, N5, M5, N4,
L5, M4, N3, M3, N2, M2, Nl, L2, Ml,
Ll, K2, J3, Kl, J2, Jl

85, 84, 82, 81, 80, 79, 78, 77, 76,
74, 73, 71, 69, 68, 66
61, 60, 59, 58, 57, 56, 55, 54, 52,
51,50,48,47,46,44,43,42,41,
40, 39, 38, 36, 34, 31, 30, 28, 27,
26, 25, 24, 23, 22

115-0

I Data

D13, D12, C13, B13, C12, A13, B12, A12,
Bll, All, BIO, AIO, B9, A9, B8, A8

Q15-0

Q Data

A7, A6, B6, A5, B5, A4, B4, A3, A2, B3,
AI, B2, Bl, C2, Cl, D2

90, 92, 93, 94, 96, 97, 100, 102,
105, 106, 107, 109, 110, 111, 113,
114
117,118,119,121,122,123,125,
126, 127, 130, 132,3,4, 6, 7, 8

ENR
ENP1,0
FM, PM
081Q
OEI
OEG

Radius In Enable
Phase In Enable
Modulation
Cartesian Data Format
lOut Enable
Q Out Enable

MIl
Gl, G2
H2, HI
Fl
E13
Dl

NC

No Connect Pins

-

2, 32, 35, 62, 64, 65, 72, 98, 101,
103, 128, 131

Index Pin

D4

-

Outputs

Controls

No Connect

63
18, 16
20,19

15
88
10

Static Control Input
081Q determines the numeric format of the output data:
offset binary if HIGH and unsigned magnitude if LOW.
This control acts with 2-cycle latency on the chip's

2-318

22-cycle data path and is normally hardwired to a
system-specific state.

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TMC2340
Table 1. Data Input/Output Formats - Integer Format
BitU
Port

OBIQ

AM

X
X

PH

31

30

29

16

15

2- 1

2-2

2-15

2-16
215

Q

215

Q

Notes:

1.

i20 denotes two's complement sign or highest magnitude

bit· since phase angles are module 27t and phase
accumulalor is module 232, this bit may be regarded as
:I7t.

2.
3.
4.
5.

All phase angles are in terms of 7t radians, hence notation
'xx'
A sign-and-magnitude '0' output is obtained by
appending the input bit PH31 as a sign bit 10 the
corresponding (i.e., delayed 22 cycles) 014-0.
A sign-and-magnitude '1" output is obtained by appending
the exclusive OR of PH31 and PH30 as a sign bit 10 the
corresponding 114-0.
When 0810=0, outputs 115 and 015 become 'do not
connects' and will stay logic HIGH. (They may be wired 10
VOO, left open, or connected 10 any logic input without
damage 10 the part or excessive power consumption.)

6.

14

0

214
2-17
214
214
214
214

20.
2- 31

Format

2°.
20.
20.

U
TIU
U
B
U

2°.

B

Ix...)

Formats:
T/U~ Two's

Complement/Unsigned Magnitude 32 Bits
U~ Unsigned Magnitude
15 Bits
B~ Offset Binary
16 Bits

PH

AM. I. Q

HEX

U

T

B

U

-7[ Z-15

7[(2_2- 151

8001

_7[(1_2- 15)

7[(1 +2- 15)

8000

-7[
7[(1_2- 15)

7[(1-2- 15)
7[.2- 15

32767

FFFF

7FFF

-1

32767

0001

-32767

7[.2- 15

0000

-32768

0

0

"Hex" column contains the 16 MSBs of the 32-bit phase input
(16 LSBs are 01. the 15 bits of the amplitude input or the 16 bits
of the offset binary output.

Figure 1. Timing Diagram. Operating Conditions

I

I

23

22

1

24

elK

OBIQ~=====
I
FM, PM

ENA, ENP (1,0)

AM (14.0)' PH (31· 0)

XXXXX

A

I I

XXX)( )
I

xx

XX

I(B)
I I

Nole: 1. DEI. 6Eii -lOW

For More Information call 1-800·722·7074.

~
f(A)

Raytheon Semiconductor

21273A

2·319

TMC2340
Figure 2. Timing Diagram. Phase Modulation
22

FM

PM

ENA

23

24

25

-uuuu

ClK

I>.. I>.. I>.. I>.. I>.. I>..
"'f.XIY.XA J.X XX XX XX XXI XX
'lJ '0. I>.. I>.. I>.. I>.. I>.. I>..

AM

ENP(I,O)

PH

01>..

XX XXXXXXXXXXXXXXX
XX XX XX XX XX XX XX XX
XX XX XX XX XX XX XX XX
A

10

01

01

01

01

K

C

01

01

M

N

1,0
Notes: 1.
2.
3.
4.
5.

OEI, OEQ = Law.
Carrier C and peak amplilude Aloaded on CLK O.
Modulation values I. J, K, L, ... loaded on eLK 1, CLK 2, etc.
Output corresponding to modulati~n loaded at elK i emerged too after eLK i + 21.
To modulate amplitude, vary AM with ENA:. 1.

Figure 3. Equivalent Input Circuit

21274A

Figure 4. Equivalent Output Circuit

voo
n SUBSTRATE

n SUBSTRA:tT
01

01

p

p+

p+

CONTROL
INPUT
1KO

n+

n+

02

n

02

pWELL

pWELL
>-------~~~~

GNO
21120A

21121A

Figure 5. Transition Levels for Three-State Measurements
lENA
OEI,OEO

0.5Y
THREE·STATE
OUTPUTS

____+----.

HIGH IMPEDANCE

0.5Y

2-320

21275A

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2340
Absolute maximum ratings (beyond which the device may be damaged) 1
Supply Voltage ........................................................................................................................................................................................ - 0.5 to + 7.0V
Input Voltage ................................................................................................................................................................................. - 0.5 to IVOO + 0.5jV
Output Voltage
Applied voltage ................................................................................................................................................... - 0.5 to IVOO + 0.5jV 2
Forced current ............................................................................................................................................................ - 6.0 to 6.0mA 3.4
Short-circuit duration Isingle output in HIGH state to groundj ......................................................................................... 1 Second
Temperature
Operating, case .............................................................................................................................................................. - 60 to + 130°C
junction ........................................................................................................................................................................... 175°C
Lead, soldering 110 secondsj ......................................................................................................................................................... 300°C
Storage ............................................................................................................................................................................ - 65 to + 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range. and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

Operating conditions

Parameter
VOO
VIL
VIH
IOL
IOH
tev

Supply Voltage
Input Voltage, Logic LOW
Input Voltage, Logic HIGH
Output Current, Logic LOW
Output Current, Logic HIGH
Cycle Time

tPWL

Clock Pulse Width, LOW

tPWH

Clock Pulse Width, HIGH

ts

Input Setup Time

tH

Input Hold Time

TA
Te

Ambient Temperature, Still Air
Case Temperature

Test Conditions

Temperatura Range
Standard
Extended
Min
Max
Min
Max
4.75
2.0

VOo=Min
TMC2340-1
Voo=Min
TMC2340-1
Voo=Min
TMC2340-1
TMC2340-1
TMC2340-1

For More Information call 1-800-722-7074.

5.25
0.8

4.5

10
8
8

V
V
V

8.0
-4.0
55
45

rnA
rnA

11
8
8

6

6

12
10
1
1
0

13
11
2
2
70
-55

Raytheon Semiconductor

5.5
0.8

2.0
8.0
-4.0
50
40

Units

125

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

DC
DC

2-321

TMC23.40
Electrical characteristics within specified operating conditions

1

Temperature Range

looa Supply Current, Quiescent
IOOU Supply Current. Unloaded

10

mA

160

160

mA

-10

-10
10

pA

VOO=Max, VIN=OV

VOL

Output Voltage, Logic LOW

VOH

Output Voltage, Logic HIGH

VOO=Min, IOL =Max
VOO=Min,IOH=Max

IOZL
IOZH
lOS

Hi-Z Output Leakage Current, Output LOW
Hi-Z Output Leakage Current, Output HIGH
Short-Circuit Output Current

VOO=Max, VIN=OV

CI

Input Capacitance
Output Capacitance

TA=25°C, f=lMHz
TA=25°C, f=lMHz

Note:

Unfts

10

Input Current, Logic LOW
Input Current, Logic HIGH

Co

Extended
Min
Max

VOO=Max, VIN=OV
VOO=Max, f=20MHz
DEI and OEQ=VOO

IIH

IlL

Standard
Min
Max

Test Conditions

Parameter

10

VOO=Max, VIN=VOO

0.4
2.4

VOO"" Max, VIN=VOO
VOO = Max, Output HIGH, one pin to
ground, one second duration max.

1. Actual test conditIOns may vary from those shown, but specified operation

-20

0.4
2.4

-40
40
-100

V
V

-20

-40
40
-100

/LA
/LA
/LA

10
10

pF
pF

10
10
IS

/LA

guaranteed.

Switching characteristics within specified operating conditions
Temperature Range
Parameter

Extended
Min
Max

Units

10

Output Delay

VOO=Min, CLOAO=40pF
TMC2340-1

22
20

25
23

ns
ns

tHO

Output Hold Time

VOO=Max, CLOAO=40pF
TMC2340-1

4
4

4
4

ns
ns

tENA

Output Enable Delay

VOO=Min, CLOAO=40pF
TMC2340-1

13
12
14

17

ns
ns

lOIS

2-322

Test Conditions

Standard
Min
Max

Output Disable Delay

VOO= Min, CLOAO=40pF
TMC2340-1

Raytheon Semiconductor

13

15
14
13

ns
ns

For More Information call 1-800-722-7074.

TMC2340
Phase/ Amplitude to Sine/Cosine Conversion
Geometry
Polar-To-Rectangular Conversion Geometry
The TMC2340 performs a coordinate-space transformation according to the familiar trigonometic
relationships shown in Figure 6.

With constant amplitude and phase increment values and
either FM or PM HIGH, the TMC2340 will output a
series of complex number pairs representing the
horizontal and vertical projections of a vector rotating
about the origin, i.e., a cosine wave and a sine wave.

Figure 6. Input to Output Relationship for Sinusoid Generation
YOUT (n) =AM(n) StN (PH • n)

Y
AM

AM/2

f:------+-''-----~-_. t =n/fclK

At point "a" n =2ll/PIN
X
XOUT (n) =AM(n) cos (PH • n)
AM

AM/2

.---4t------4t------._+ t=n/fclK

21276A

For More Information call 1-800·722·7074.

Raytheon Semiconductor

2·323

TMC2340
Digital Waveform Synthesis
Waveform Generation and Modulation

7. the output valid during clock rising edge

Utilizing the internal phase accumlators in a TMC2340,
users can easily generate high-accuracy digital quadrature
sinusoidal waveforms with minimal support. The 32-bit
data path ensures negligible cumulative error in most
applications, and the accuracy of the transform is limited
only by the truncation of the result to 16 bits prior to
the Transform Processor and the ± 1 lSB maximum error
of the transform algorithm. Amplitude Modulation is of
course performed simply by varying the amplitude input.
Either Frequency (phase angle shifted by the cumulative
sum of the modulation inputl or Phase (phase angle
shifted by the instantaneous modulation inputl
Modulation can be realized by configuring the TMC2340
as shown in Figures 7 and 8.

where PH m and AMm are the chip inputs at rising edge
m, PC is the (constantl carrier phase increment. PM 1= 0,
PM2, ... m=1, and FM1-m=0.

Figure 7, Performing Phase Modulation

Figure 8, Performing Frequency Modulation

AM(14:0)

PH(31 : 0)

In Figure
m+22 is:

1m + 22 =AMmcos(PH m+ mPCI
Om +22=AM msin(PH m+ mPCI

Expressed in terms of time instead of clock cycles,
I((m + 221 Ifcl k=AMm/fclkCOS(PHm/fclkl
where fclk is the frequency of the square wave applied
to ClK.

PH(31 : 0)

AM(14: 0)

15

15

15

16MSB

CORE

1(15: 0)

0(15: 0)

1(15: 0)
21277A

2-324

Raytheon Semiconductor

0(15: 0)
21278A

For More Infonnation call 1-800-722-7074.

TMC2340
In Figure 8, the output valid during clock rising edge
n+22 is:

n
Im+22=AMm cos (I: PHm+nPCI
m=l

Expressed in terms of time instead of clock cycles,
n
I(n + 221/fclk=AM m/fclk cos (I: PHm/fclk+ PC· m/fclkl
m-1

Digital Synthesizer with TDC1012 D/A Converter

n
Qn+22=AMm sin (I: PHm+nPCI
m=l

where PH m and AMm are the chip inputs at rising edge
AM, PC is the (constantl carrier phase increment.
FM1 =0, FM2 ... n=1, and PM=O.

Connection of the TMC2340 to the TDC1012 O/A
converter is straightforward. As shown in Figure 9, the
TOC1012 data lines are connected to either the I or Q
outputs. Both outputs may be used, with two TOC1012's
for quadrature synthesis.

Figure 9. Frequency Synthesizer

HOST INTERFACE:
ENA

AMPLITUDE
DATA
15
FREQUENCY
AND/OR
PHASE DATA

115

AM 14.0

114
113

ENP 1.0

112
113

PH 31 • 0

TMC2340
MODULATION
CONTROL

FM, PM

02
03
04

't1P

05

110

Os

19

07

IS

Os

17

09

elk{

r--*--:M""-:INI.....J.

TI4·1A

IS
OEI

""

15
14
ClK

+5V >------+--~-t------'

·S.2V

21279A

Note: To use two TDCl 012's in quadrature, connect second TDC1012 to 015 (MSB) to 04 and ground OEO.

For More Information call 1-800·722-7074.

Raytheon Semiconductor

2-325

TMC23.40
Control Qf the TMC2340
The TMC2340 needs to be initialized to tell it what
frequency and amplitude sinusoid to generate. To initialize
amplitude. apply the desired full-scale amplitude to the
AM input port of the TMC2340 (AM 14 through AMOI
and pull ENA HIGH for one clock cycle. This will load
the amplitude. If ENA is held HIGH, then the amplitude
will follow the inputs on the AM port. If the user
assumes an implied binary point before the MSB of the
AM port, the input range will be 0 to just under 1, and
the outputs will fall between 0 and 2, with binary points
after 115 and Q15·
To set the frequency, the C register must be loaded with
a value which is the phase increment per clock cycle. If
the binary point is considered to be just left of the MSB
(input range is 0 to almost 11 then the output frequency
is the TMC2340 clock frequency multiplied by the
number loaded into C. Since C is 32 bits wide, with a
20MHz clock, one LSB represents a frequency increment
of 0.005Hz.
To load the C register, set ENYP1 = 1 and ENYPO = 0;
the data presented at the PH port will be loaded on the
next clock rising edge.
At this point the TMC2340 has been initialized and can
be put into one of three modes depending upon the
states of FM and PM:
Mode 0

FM =0, PM =0
In this mode the chip is in standby. The
unchanging output corresponds to AM
cos(PMI on the I outputs with PM being
the phase increment.

Mode 1

FM=1, PM=O
Frequency Modulation Mode. The chip
generates an output signal of peak amplitude AM and frequency determined by
accumulating the sum of the phase

2-326

increment values in the C and M registers
(more about the M register in a later
sectionl.
Mode 2

FM=O, PM=1
Phase Modulation Mode. The TMC2340
generates a sinusoid of the frequency
represented in the C register and the peak
amplitude in the AM register. On each
clock cycle, the phase of the signal is offset
by the value in the M register.

Modulation
The output of the TMC2340 can be phase (Mode 21 or
frequency (Mode 11 modulated. An un modulated sinusoid
results if the contents of registers C and M are held
constant. Its frequency is set by C (Mode 21 or C+ M
(Mode 11. Since the state of the M register is not
defined at power up, the M register should be loaded or
cleared to begin operation.
If the signal is to be frequency modulated then the
modulation signal is loaded into the M register. The
format for the frequency is the same as that for the C
register. If ENYP 1 0 = 0, 1 then the data that is
presented at the PH port is automatically loaded on each
clock rising edge.
For phase modulation, the phase deviation is loaded
into the M register (same manner as for frequency
modulationl. The units of the phase offset are cycles and
full-scale is just under one output cycle per TMC2340
clock cycle. The MSB represents a phase of 180°, and
the LSB a phase of about 8x10- 8 degrees (eight onehundred-millionths of a degree!, or 71-/231 radians.
To synchronize two TMC2340s, first load them with their
respective data in mode 0, then switch them simultaneously to either Mode 1 or Mode 2.

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TMC2340
Calculating Frequency, Amplitude, and Phase
Input Values for the TMC2340
This Application Brief discusses equations which
simplify the calculation of register values which
control the TMC2340. These values allow the
generation of output carrier frequency, frequency or
phase modulation, and output amplitude.
The results of the equations are converted to
binary register values and should be rounded to the
resolution of the applicable register (32 or 15-bits).
For negative values of phase or frequency
modulation, use these equations for positive values
and see Table 1 of the TMC2340 data sheet to
convert them to negative values.
The TMC2340 operates by continuously
incrementing a register (phase accumulator) that
rolls over when it becomes full. For example. if the
next increment to the phase accumulator causes it
to overflow by 47 LSBs, the phase accumulator
retains the value 47. The value present in the
carrier register (C) is the amount by which the
phase accumulator is incremented each system
clock cycle. As the value of the carrier register is
increased, the value with which the the phase
accumulator is incremented each clock cycle is
increased, resulting in an increased carrier
frequency.

The magnitude of the carrier is determined or
modulated by the value loaded in the AM register.
Phase modulation is accomplished by adding the
value of the phase accumulator to the value of the
modulation (M) register. This adds an offset to the
phase of the carrier. This does not affect the
increment value of the phase accumulator and
therefore only effects the phase of the carrier,
leaving the frequency constant.
Adding the value of the modulation register to the
phase accumulator along with the value of the
carrier register on each clock cycle results in a shift
in frequency. This is because the phase
accumulator is incremented by a different amount
each clock cycle.
Frequency or phase modulation is selected with the
FM and PM input pins which configure the
TMC2340. The equations presented herein are
useful for s.etting carrier frequency and phase,
output amplitude, and frequency and phase
modulation. To modulate the carrier with an
external Signal, the signal must be digitized and
those values loaded into the modulation inputs of
the TMC2340.
The carrier and modulation registers are loaded
through the PH 31 -0 inputs. The ENP 1,0 inputs
select the desired register. The amplitude register
is loaded through the AM14_0 inputs.

CARRIER FREQUENCY:
Desired Carrier Frequency
Carrier Register (C) Value =
Clock Frequency

AMPLITUDE AND AMPLITUDE MODULATION:
Desired Output Amplitude
AM Register Value
Full-Scale Output Amplitude

FREQUENCY MODULATION:
Desired Change in Carrier Frequency
Modulation Register (M) Value =
Clock Frequency

For More Infonnation call 1-800-722-7074.

Raytheon Semiconductor

2-327

TMC2340
PHASE·MODULATION:
Desired Change in Phase in radians (degrees)
Modulation Register (M) Value = - - - - - - - - - - - - - - - -

EXAMPLE 1: Set carrier frequency to 3.579545 MHz with a system clock of 20MHz.

Carrier Register (C) Value =

Desired Carrier Frequency
3.579545 X 106
32
--------- X 2
= - - - - - - - X 232
Clock Frequency
20 X 106

C = 0.17897725 X 4,294,967,296 = 768,701,436 = 2DD1 73FBh
= 00101101110100010111 001111111011 = PH 3 1-O
EXAMPLE 2: Set output amplitude to be 12.2% of full-scale.
Desired Output Amplitude
AM Register Value =

0.122

- - - - - - - - - X (2 15_1) = - - - X 32767
Full-Scale Output Amplitude

1.000

AM = 3,998 = OF9Eh = 0001 1111 0011 1100 = AM 14-0
EXAMPLE 3: Change carrier frequency by 10kHz with a system clock of 3 MHz.
Desired Change in Carrier Frequency
Modulation Register (M) Value = - - - - - - - - - - - - Clock Frequency
10 X 103

X 232

M=

=

14,316,558

= OODA 740Eh

3 X 106
M

= 00000000110110100111010000001110 = PH 31 -0

EXAMPLE 4: Shift the phase of any carrier frequency by 12°.
Desired Change in Phase
Modulation Register (M) Value = - - - - - - - - 360°

12
360

M = 0.033333 X 232 = 143,165,577 = 0888 8889h
= 00001000100010001000100010001001 = PH 31 -0

2-328

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2340
Pin Assignments -121-Pin Plastic Pin Grid Nray, H5 Package; 12O-Pin Ceramic PGA. G1 Package
Pin

Name

Pin

Name

Pin

Al
A2
A3
A4
A5
A6
A7
AS
A9
Al0
All
A12
A13
Bl
B2

Q5
Q7

B3
B4
B5
B6
B7
BS
B9
BlO
Bll
B12
B13
Cl
C2
C3
C4

Q6
Q9
Qll

C5
C6
C7
CS
C9
Cl0
Cll
C12
C13
01
02
03
011
012
013

13
12
11
10
9
8
7
6

Qs
QlO
Q12
Q14
Q15
10
12
14
16
Is
110
Q3
Q4

Q13
GNO
11
13
15
17
19
112
Q1
Q2
VOO
GNO

Name

Pin

Name

Pin

GNO

El
E2
E3
Ell
E12
E13
Fl
F2
F3
Fll
F12
F13
Gl
G2
G3

GNO
GNO

Gll
G12
G13
Hl
H2
H3
Hll
H12
H13
Jl
J2
J3
Jll
J12
J13

VOO
GNO
VOO
GNO
GNO
VOO
111
113
OEQ
Qo
GNO
GNO
114
115

VOO
VOO
GNO

1ID
OBIQ
GNO
ClK
VOO
GNO
AM14
ENP 1
EN Po
GNO

Name

Pin

Name

Pin

Name

Pin

Name

GNO

Kl
K2
K3
Kll
K12
K13
L1
l2
l3
l4
l5
l6
l7
lS
19

PH 2
PH4
GNO
GNO
AM5
AM6
PH5
PH7
GNO

L10
L11
L12
L13
Ml
M2
M3
M4
M5
M6
M7
MS
M9
Ml0
Mll

PH 31
VOO
AM3
AM4
PH 6
PH 9
PH 11
PH 13
PH 16
PH 1S
PH 20
PH 23
PH 25
PH2S
ENA

M12
M13
Nl
N2
N3
N4
N5
N6
N7
NS
N9
Nl0
Nll
N12
N13

AMl
AM2
PHS
PHlO
PH12
PH 15
PH 17
PH 19
PH 21
PH22
PH 24
PH 26
PH 29
PH30
AMo

AM12
AM13
PM
FM
VOO
AM9
AM 10
AM 11
PHo
PHl
PH3
GNO
AM7
AMs

VOO
PH 14
VOO
GNO
VOO
PH27

©©©©©©©©©©©©©
©©©©©©©©©©©©©
©©©©©©©©©©©©©
©©©
©©©
©©©
©©© (
©©©
©©©
TOP VIEW
©©©
©©©
CAVITY UP
©©©
©©©
©©©
Key
© © ©
©©©II.
©©©
©©©©©©©©©©©©©
©©©©©©©©©©©©©
©©©©©©©©©©©©©

'\

k

L

ABCDEFGHJKlMN
21041A

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-329

TMC2340
Pin Assignments - 132 Leaded CERQUAD, L5 Package
Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

1
2
3
4
5

VOO
NC

23
24
25
26
27

PH l

45
46
47
48

VOO
PH 18
PH 19
PH20
GNO

67
68

VOO
AMl
AM2
GNO

89
90
91
92

GNO

12
VOO

6
7
8
9

°2
°1

AM3
NC

93
94
95

111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132

Pin

10
11
12
13
14
15
16
17
18
19
20
21
22

°4
°3
GNO

28
29
30

°0
VOD
OEO
GND
GND
CLK
GND

31
32
33
34
35
36
37

0810

38
39
40
41

ENPO
GND
ENP 1

PM
FM

42
43
44

VOD
PHo

132

34

2-330

PH2
PH 3
PH 4
PH 5
PH 6
GNO
PH 7
PH 8
NC
GNO
PH 9
NC
PH lO
VOD
PH 11
PH 12
PH 13
PH 14
PH 15
PH 16
PH 17

49
50
51

PH21
PH 22
PH 23

52
53
54
55
56
57

65
66

AM4
AM5
GNO

78
79

AM6
AM7
AM8
AM9

80
81

AMlO
AM 11

96
97
98
99
100
101
102
103

PH30
PH 3l
NC
ENA
NC
NC

82
83
84
85
86
87

AM12
GNO

104
105

AM13

106
107

AMO

88

DEI

VOO
PH24
PH25
PH 26
PH27
PH28
PH29

58
59
60
61
62
63
64

69
70
71
72
73
74
75
76

77

AM14
GNO
VOO

108
109
110

115
VOO
114
113
112
GNO
111
110
NC
VOD
19
NC
18
NC
GNO
17
16
15
GNO
14
13

11
10
GNO
GND
°15
°14
°13
VOO
°12
Qll
QlO
GND
Q9
Q8
°7
NC
GND
Q6
NC
°5

100

21062A

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2340
Ordering Information
Product
Number

Temperature Range

Screening

Package

Pakcage
Marking

TMC2340H5C1
TMC2340H5C
TMC2340L5V1
TMC2340L5V
TMC2340G1V1
TMC2340G1V

STD: TA =0 to 70°C
STD: TA =0 to 70"C
EXT: TC =-55°C to 125°C
EXT: TC =-55"C to 125"C
EXT: TC =-55"C to 125"C
EXT: TC =-55°C to 125°C

Commercial
Commercial
MIL-STD-883B
MIL-STD-883B
MIL-STD-883B
MIL-STD-883B

121-Pin Plastic Pin Grid Array
121-Pin Plastic Pin Grid Array
132-Leaded CEROUAD
132-Leaded CEROUAD
120-Pin Ceramic PGA
120-Pin Ceramic PGA

2340H5C1
2340H5C
2340L5V1
2340L5V
2340G1V1
2340G1V

40006720 Rev B 6/93

For More Information call 1-800-722-7074.

Raytheon Semiconductor

2-331

TMC2340

2-332

Raytheon Semiconductor

For More Information call 1-800-722-7074.

Section 2 - Application Specific Standard Products

ARINC Products
+15V

":'

Inputs

vss
ARINC
Channel

o

In 1A

0ut1A

HO

In 1B

Out1B

LO

RU3283
ARINC
Channel
1

In2A

Out2A

H1

In2B

Out2B

L1

VR VI Sync CIk +V.
RM3182
RU3182A A"",

Mode

N1

Oala(A)

NO

Oala(B)
-VB

EF4442

":'

IRQ

+V. GNO -V.

2

In 1A

Out1A

H2

FVW

In 1B

01ll1B

L2

Clock

RU3283
ARINC
Channel

3

}

01ll2A

H3

In2B

OUl2B

L3

-15V

pF

,-

Microprocessor

Microprocessor

DO-DB

In2A

":' 75 Y75
P

Reset

+15V

ARINC
Channel

ARINC
line Out

B"",

Data Bus

AD
A1

CS
To+5V

ARINC429 defines an air transport industry standard for
the transfer of digital data between avionic system
elements. It specifies the basic system configuration and
communication protocols. Any avionics element, having
information to transmit, will do so from a designated
output port over a single twisted and shielded pair of
wires to all other elements that have a need for such

Dual Receiver

information. The information flow is uni-directional. The
typical ARINC429 system consists of a Controller, which
oversees the gathering and time multiplexing of data in
accordance with the protocol, a Une Driver, capable of
driving the twisted pair, and one or more Receivers,
which process the data transmitting over the twisted pair.

line Drivers

Features

Features

•
•
•

•
•
•
•

•
•
•

Converts ARINC429 levels to serial data
Two separate analog receiving channels
Built in m compatible test inputs
m and CMOS compatible inputs
Short-circuit protected
3183 and 3283 are pin compatible

For More Information. call 1-800-722-7074.

•
•
•

Adjustable rise and fall times
Adjustable output voltage swing
Short circuit protection
Output over-voltage protected
m and CMOS compatible inputs
Drives 4000' 130 nF loads
MIL-STD-883S screening available

Raytheon Semiconductor

2-333

Section 2 - ApplicatIon Specific Standard Products

ARINC Receivers
Bandgap
References
No

Hysteresis
No

Matched
Prop. Delays
No

MlL-STD-883
No

VoHages
+15, -15, +5V

RM31831883B

No

No

No

Yes

+15, -15, +5V

RM3283

Yes

Yes

Yes

No

+15, -15, +5V

RM3283/883B

Yes

Yes

Yes

No

+15, -15, +5V

RM3183

Packages
20 pin CDiP
20padLCC
20 pin CDiP
20 pad LCC
20 pin COIP
20 pin SOL
20padLCC
20 pin CDiP
20 pad LCC

ARINC Line Drivers
DlgHailySeI
Transmission Rate
RM3182

No

Ou1put Impedance
7S0Nominai 750 Controlled

Yes

No

20
No

MIL-sTD-883 VoHages
No

+15,-15,+5V

Packages
20pinCOIP
20 pad LCC

RM3182/883B

No

Yes

No

No

Yes

+15, -15, +5V

RM3182A

Yes

No

Yes

Yes

No

+15, -15, +5V

20 pin COIP
20 pad LCC
20 pin COIP
20 pin SOL
20padLCC

RM3182N883B

Yes

No

Yes

Yes

Yes

+15,-15,+5V

20 pin CDiP
20padLCC

2-334

Raytheon Semiconductor

For More Information, caD 1-800-722-7074.

RM3182
RM3182
ARINC 429 Differential Line Driver
Description

Features

The RM3182 consists of a bus interface line driver
circuit plus auxiliary gating and synchronization
circuitry. Designed to address the ARINC 429
standard. the RM3182 has output rise and fall
times adjustable by the selection of two external
capacitor values. and the output voltage swing
range can be adjusted through an externally
applied VREF signal. The logic inputs as well as
the sync control inputs are TTUCMOS compatible.
The device is constructed on a monolithic IC using
a junction-isolated bipolar process. Sputtered SiCr
resistors are used in the internal bias circuitry.
providing stable internal bias currents. The
RM3182 is available in 16-lead ceramic DIP and
28-pad LCC. and can be ordered with MIL-STD8838 high reliability screening.

•
•
•
•
•
•
•
•

Adjustable rise and fall times
Adjustable output voltage swing
Short circuit protected
Output overvoltage protected
Sync and clock enable inputs
TTL and CMOS compatible inputs
MIL-STD-8838 types available
100 Kbitslsecond data rate

Functional Block Diagram

~1"

N_:
1. RLand CL ore 8lI1emaL Full load ........ ore: RL- 400 Cl,ec- 0.03 IIf.
2. Pin IXImbara ore'''' 16-1ood DIP.

For More Information. call 1-800·722·7074.

Raytheon Semiconductor

2·335

RM3182
Ordering Information

Absolute Maximum Ratings
Supply Voltage (+Vs to -Vs) ..................................... 36V
V1 Voltage •................•.................•........................... +7V
VREF Voltage ........................................................... +6V
Logic Input Voltage ........................... -0.3V to +VS +0.3V
Output Short Circuit Duration ........................ See Note 1
Output Overvoltage ...............................................±B.5V
Storage Temperature Range ................ -65°C to +150OC
Operating Temperature Range ............. -55°C to +125°C
See Note 2
Lead Soldering Temperature (60 sec.) ............... +300°C

Part Number
RM3182S
RM3182S18838
RM3182L
RM3182U8838

Package

Operating
Temperature
Range

S
S
L
L

-SS'C to +12S'C
-SS'C to +12S'C
-SS'C to +12S'C
-SS'C to +12S'C

Notes:
1883B suffix denotes MIL-STD-883, Level B processing
S = 16-lead sidebraze ceramic DIP
L - 28-pad lead less chip carrier

Notes:
1. Heatsinking may be required for output short circuit at +125"C.
2. Heatsinking may be required depending on load and signal
frequencies

Thermal Characteristics
(Still air, soldered into PC board)

Max. Junction Temp.
Max. Po TA < 50°C
Therm. Res. 9JC
Therm. Res. 9JA
For TA > 50°C Derate at

2-336

16-Lead
Sidebrazecl
DIP
+175°C
1470 mW
25°CIW
85°CIW
11.7mWfOC

28-Pad
LCC
+175OC
1040mW
25°CIW
120°C/W
8.3 mW/oC

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RM3182
Connection Information
16-Lead Sidebraze DIP (Top View)

1

@)

6!Hl4192

28-Pad LCC (Top View)

4 3 2

282726

5
6
7
8
9
10
11

25
24
23
22
21
20
19
12131415161718

65-4193

For More Information. call 1-800-722-7074.

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Function
VREF
Pwr Enable
Sync
Data (A)
CA
AoUT
-VS
GND
+VS
NC
VOUT
CB
Data (8)
Clock
NC
V1

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Function
VREF
NC
Pwer Enable
Sync
NC
Data (A)
NC
NC
CA
NC
NC
NC
AoUT
-VS

Raytheon Semiconductor

Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Function
GND
+VS
BoUT
NC
NC
NC
NC
CB
Data(8)
NC
Clock
NC
NC
V1

2-337

RM3182
Electrical Characteristics
(Vs = ±15V. VREF = V1 = +5V. Pwr Enable = OV. Rl = open circuit. -55"C S TA S +125"C)
Min

Parameters

Test Conditions

Positive Supply Current

Data Rate = 0 to 100 Kbits/sec

Negative Supply Current

Data Rate = 0 to 100 Kbitslsec

V1 Supply Current

Data Rate = 0 to 100 Kbits/sec

VREF Supply Current

Data Rate = 0 to 100 Kbits/sec

Input Logic Level High

Typ

Max

Units

11

16

rnA

-16

-10
200

975

J.LA

-1.0

-0.4

-0.15

rnA

rnA

2.0

V

Input Logic Level Low

0.5

V

Output Voltage High
Output Voltage Low

With Respect to Ground

4.75

With Respect to Ground

-5.25

5.0
-5.0

5.25
-4.75

V
V

Output Voltage Null

Both Data Input = Logic 0

-250

0

+250

rnV

1

10

-20

-1

J.LA
J.LA

Input Current High

V1N =2.0V

Input Current Low

V1N =0.5V

Output Short Circuit Current

Output in High State. to Gnd

Output Short Circuit Current

Output in Low State. to Gnd

Positive Supply Current

Output High and Shorted to Gnd

Negative Supply Current

Output Low and Shorted to Gnd

-133
80

Input Capacitance·

-80

rnA

133

rnA
150

-150

rnA
rnA

5

15

pF

'Guaranteed by design.

Typical Power Dissipation Characteristics
(Vs = ±15V. V1 = VREF = +5V. Pwr Enable = OV. TA = +25"C)
Data Rate
(Kbltslsec)

load

Positive
Supply
Current

Negative
Supply
Current

PlnV1
Supply
Current

Internal
Power
Dissipation

load
Power
Dissipation

oto 100
12.5 to 14
100

Open Circuit
Full load'·
Full load'·

11 mA
24mA
46mA

-10 mA
-24mA
-46mA

200 J.1A
200 (.LA
200 (.LA

325mW
660mW
1000 mW

0
60mW
325mW

··RL= 4000. CL = 0.03 JlF (see Functional Block Diagram).

2-338

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RM3182
Principles of Operation
Each device consists of one differential driver and
associated gating circuitry. The gating circuitry
consists of clock and sync signal inputs which are
ANDed with the two data inputs. See the block
diagram and truth table. Three power supplies
are required to operate the RM3182 in a typical
ARINC 429 bus application: +15V, -15V, and
+5V. The +SV supply, in addition to powering the
internal bus current regulator, provides a reference voltage that determines the output voltage
swing. The differential output swing will equal 2
VREF • If a value of VREF other than +SV is used,
then a separate +SV supply is required for pin V1.
Figure 1 depicts connections for the ARINC 429
application. The driver output impedance is
nominally 7S0. With the Data(A) input at a logic
high and Data (B) input at a logic low, AOUT will

swing to +VREF and BOUT will swing to -VREF
(constituting a logic high state). Reversing the
data Input states will cause Aoor to swing to
-VREF and Bour to +VREF- With both data Input
signals at a logiC low state, the outputs will both
swing to OV (output In null state).
The slew rate of the outputs, and consequently
rise and fall times, can be adjusted through the
selection of two external capacitor values. Typical
values are CA = CB = 75 pF for high-speed operation (100 Kbits/sec) and CA =C =SOO pF for
low-speed operation (12.S to 11KbitslSeC).
The device can be powered down by applying a
logic high signal to the Power Enable pin. If the
power down feature is not used, then the Power
Enable pin should be tied directly to ground.

+15V

+5V

Data (A)

Inputs

l

,---,

RM3182

To Bus

Power
Enable
Data (B) Gnd
Cs

Note: Pin numbers are for
the 16-lead DIP.

-15V
65-4187A

Figure 1. ARINC 429 Bus Application

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

2-339

RM3182

Data A
I

DataB

~Ov~~~11

rl~

_____

Adjust By CB or Rate Seled
OutAor
Amp A
Adjust By CA or Rate Seled
OutB
orAmpB

Differential
Output

Out A-Out B
or
Amp Out AAmpOutB

Note: Outputs unloaded
65-4188

Figure 1. SwHching Waveforms

Truth Table
Sync

2-340

X
L

Clock
L
X

H
H
H
H

H
H
H
H

Data (A) Data (B)
X
X
X
X
L
L
L
H
H
L
H

H

AOUT

BOUT

OV
OV
OV
-VREF
+VREF
OV

OV
OV
OV
+VREF
-VREF
OV

Raytheon Semiconductor

Comments
Null
Null
Null
Low
High

Null

For More Information, call 1-800-722-7074.

;r

CJ)

~

(")

iii

:;0'

~

~.

(16)

~

0(5)

+V.
rL

f~1

(9)
40K

~

~
~

c..

VI

~I ~
~198K

Data (A)

0(4)

::s"

Power Enable

C'D

r~

3

20K

2OK~

a
n"

~20K~80K

c

~.

1#

.....

"

QJ

3

r1

Clock
281(

(14)

i

s~
(3)

CD

o

::s

W

~
,~ I·~oj~
~ I 1,m
w.
:

3

n
o

5.
c
~
...

~~~~
I U--L

10K

I

10K

(13)

I

I I ,

I~;r

10Kh

I I I I!

1

T

4K

II

Aour
(6)

.,.

!!auT

10K

5K

5K

2.5K

r" r
....,

5K

·Va

m
Note: Pin numbers are for the 16-1ead DIP.

0(1)

V"""

r;J

I

~

r

0(12)

r.

85-41111

I~
CM

1-06

00
N

~
Avionics

RM3182

2·342

Raytheon Semiconductor

For More Information, call 1-800·722·7074.

RM3182A
RM3182A
ARINC 429 Differential Line Driver

available in 16-lead ceramic side-brazed DIP, 28-pad
LCC and can be ordered with MIL-STD-8838 high
reliability screening.

Description
The RM3182A is a complete differential line driver IC.
When Data A =Data 8 or Sync or Clock Signal is low,
the driver forces the output to a Voltage Null level (OV ±
250 mV). Designed to address the ARINC 429 standard,
the RM3182A has output rise and fall times that can be
adjusted by the selection of an extemal capacitor (CA or
CB) and an output voltage range adjustable through an
extemallyappliedVREFsignal.A1lloglc inputs and sync
control inputs are nuCMOS compatible. The device is
constructed on a monolithic IC using a junction-isolated
bipolar process. Sputtered SiCr resistors in the intemal
bias circuitry provide for stable bias currents and a
tighter tolerance of output impedance. The RM3182 is

Features
•
•
•
•
•
•
•

•
•
•

Adjustable rise and fall times
Low supply current
Capable of driving 30 nF II 400n
Digitally selectable 12.5 or 100 kbitlsec data rate
Adjustable output voltage swing
Output overvoltage protected
Short circuit protected
m and CMOS compatible inputs
MIL-5TD-8838 screening available
Available in 16-lead ceramic side-brazed DIP
and 28-pad LCC

Functional Block Diagram
Cap (A)

r ________

Vee

5 _ _ _~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~

1

1

3pF

I

Amp A

Charge Pumps
Da1a (A) ~;---l Da1a (A)

14

Sync

3

I

1 10

41

Clock

1

10K

Clock Cap (A) ~f-4--I
Sync

Ia.. (A)

1J-'-f---1 v".,
Da1a (B) 0=13_--1 Ca.. B

V".,

V~

V~

:::

1
Rate
Select

21
D-t---1

1

Rate
Select

1a..(8)I-+---+--4--------'

1
L _______ _

+-JWIr--+--...----'-1-[] AmpB
15

3pF

12

VEE

1

-86---~------------~

CapB

GND

V.

Note: Pin numbers are for the DIP jIlCkage.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

2-343

RM3182A
Absolute Maximum Ratings

Connection Information
Top View

Supply Voltage (Vcc to VEE) .............................. +36V
VLOGIC Threshold Voltage .................................... +7V
VREF Voltage ..................................................... +VCC
Logic Input Voltage .................. -0.3V to VLOGIC +O.3V
Temperature Range
Storage ....................................... -65"C to +150"C
Operating .................................... -55"C to +125"C
Junction Temperature ....................... -55"C to +175°C
Lead Soldering Temperature
(60 sec) ..................................................... +300°C

65-04192

Thermal Characteristics
(Still air, soldered on a PC board)

Parameter
Max. Junction Temp.
Therm. Res. 6JA
Therm. Res. BJC
For TA > 50°C Derate at

16-Lead
Side-brazed
DIP

28-Pad
LCC

+175°C

+175"C

70"CNI
28"CNI(1)
14.3 mWI"C

60°CNI
25°CNI
13.3 mWI"C

Pin

Pin DeflnHlon 16·lead DIP
Function
Pin
Function

1
2
3
4
5
6
7
8

VAEF
Rate Select
Sync
Data A
CA
Out A
Vee
GND

9
10
11
12
13
14
15
16

Top View
4 3 2

282726

5
6

25
24

7

RM3182AS
RM3182AL

Package

S
L

Operating
Temperature
Range
-55°C to +125°C
-55°C to +125°C

Notes:
S = 16-lead ceramic DIP
L = 28-pad ceramic lead less chip carrier

2-344

23

8
9
10
11

Ordering Information
Part
Number

Vee
Amp A
OutS
CB
DataS
Clock
AmpS
VLOGIC

22
21
20
19
12131415161718
65·4193

Pin
1

2
3
4
5
6
7

Pin Definition 28·termlnal LCe
Function
Pin
Function

VREF
NC
Rate Select
Sync
NC
Data A
NC
NC

8
9

CA

10
11
12
13
14

NC
NC
NC
Out A
Vee

Raytheon Semiconductor

15
16
17
18
19
20
21
22
23
24
25
26
27
28

GND
Vee
Out S
NC
NC
Amp A
NC
CB

Data S
NC
Clock
AmpS
NC
VLOGIC

For More Information, CBII1-800-722-7074.

RM3182A
Electrical Characteristics
(VCC = +15V, VEE = -15V, VREF = +5V, VLOGIC = +5V, Rate Select = OV, RL = Open Circuit, CL = 0 pF, -55°C < TA < +125°C)

Parameters
Positive Supply Current
Negative Supply Current
VLOGIC Supply Current
VREF ~uppJy UJrrent
Input Logic Level High
Input Logic Level Low
Output Voltage High
uutput vOltage lOW
Output Voltage Null
Input current High
Input Current Low
Input Capacitance
Output Short Circutt Current

Symbol

Test CondlUons

Min

Icc
lEE
ILOGIC
IREF
VIH
VIL
VOH
VOL
VNULL
IIH
IlL

Dati Rate = 0 10 100 kb's
Dati Rate = 0 10 100 kb's
Dati Rate = 0 10 100 kb's
Data Hate = 0 10 100 kb'S
Dependent on VLOGIC

4.0
4.0
150
-500
2.0

With Respect 10 Ground
With Respect 10 Ground
Both Data InpulS = Logic 0

4.75
-5.25
-250

5.0
-5.0
0

VIN =2.0V
VIN=OfN

-645

-161

VEE Short Circuit Current

-294

(j1\1)

ISC

Aour and/or BouT shorted line 10

Iscvcc

Aour and/or BouT shorted line 10

ISCVEE

line or 10 GND
Aour and/or BouT shorted line to
line or to GND

line or to GND
VCC Short Circuit Current

1'yp
5.7
4.9
214

100

Max
6.9
6.9
300
-100
VIogic
0.5
5.25

Units
rnA
rnA

-4.75

+250
1
-SO
15

J.IA
J.IA
V
V
V
V
mV

J.IA
nA

p'"

133

156

rnA

140

165

rnA

140

165

rnA

Note: 1. Guaranteed by design

Typical Power Dissipation Characteristics
(VCC =+15V, VEE=-15V, VREF= +5V, TA= +25°C, CA= Cs =56 pF)
Data Rate
(Kblts/sec)
0-100
12.5-14
100

Load

Rate
Select

Positive
Supply
Current

Negative
Supply
Current

PlnVLOGIC
Supply
Current

Total
Power
Dissipation

Open Circuit
Full Load"
Full Load"

Logic 1,0
Logic 1
Logic 0

5.7 rnA
19.6 rnA
39.1 rnA

4.9 rnA
22.7 rnA
38.4 rnA

214 J.IA
200 J.IA
200 J.IA

160mW
655mW
1165 mW

"RL = 4000, CL = 0.03 J.LF (See Functional Block Diagram)

For More Information, call 1-800·722-7074.

Raytheon Semiconductor

2-345

RM3182A

IREF , ILOGIC vs. Temperature

Supply Current VS. Temperature
(CL =0 pF, f\ =Open Circuit)
500

-

lEE

400

~300

Icc

~

200

B
o

-55

!

25

I REF

I LOGIC

100

25

-55

Slew Rate vs. CA, CB

AmpA, AmpB Output Impedance Typical
4.0

2.5

3.5 I'-...

.."

2.0

."./'

'fj' 1.5

E

2r-f

1.0

-

V"

~

~

.! 2.0

&!

50

"-

:J.

~ 2.5

o
12.5

~

fij' 3.0

."./'

0.5

100

!

150

~

"- ..........Rate Select - 0 _

1.5

......

1.0
0.5 ~ ~seleL-jV

o

o

I--

I'-....

r.....

~

50 100 150 200250 300350400450 500
External eapacHor (pF)

Frequency (Hz)

2-346

125

Temperature (Oe)

Temperature (Oe)

.c

~

o

125

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RM3182A
Principles of Operation
The device contains three main functional blocks. 111e first block is a digital section used to decode the ARINC Clock,
Synchronization, and Data inputs as shown in Functional Block Diagram. This block takes these inputs and channels the
data to the charge pump circuits. The logical relationship for these pins is presented below.

I/O Truth Table
Sync

Clock

X
L
H
H
H
H

L
X
H
H
H
H

Data A
X
X
L
L
H
H

DataB
X
X
L
H
L
H

Out A

OutB

OV
OV
OV
-VREF
+VREF
OV

OV
OV
OV
+VREF
-VREF
OV

Comments
Null
Null
Null
Low
High
Null

The second functional block is a charge pump circuit that is used to control the output waveform and its timing
characteristics. 111is is achieved through charging and discharging a capacitor with a known current. The capacitor is user
selectable, and is connected between CA or Cs pins and ground. A Rate Select pin (digital input) enables to set the rise
and fall time. If this pin is tied to ground, the device functions in the high rate. This mode is recommended if the user does
not have an application requiring data rate switching. In the table below, recommended capacitor values are given for
each possible data combination.

Rate Select Pin Truth Table
Rate Select
Logic 0
Logic 1
Logic 0
Logic 1

CA
Ca
(pF)

10%t090%
Rise/Fail Time
{j.Is)

Data Rate
(Kblts/sec)

Comments

56
56

1.5

100
12-14.5
12-14.5
NlA

High Rate
Low Rate
Low Rate
Not Used

390
390

10
10
NlA

The last functional block of the device consists of a voltage follower and a high power output differential amplifier. 111e
voltage follower buffers the signals presented at the charge caps and presents the mirrored signal to the difference
amplifier to drive the ARINC line. Two different outputs are available from the differential amplifiers: Amp A, Amp B, and
Out A , Out B. The outputs Amp A and Amp B are the direct outputs of the power amplifier. The outputs Out A and Out B
include 37.50 series resistors added to minimize bus reflections by matching the power amplifier's output impedance to
the cable's impedance of 750. Amp A and Amp B may be used to customize the output impedance of the device. These
outputs can also be used to enhance the device's drive capability. For example, driving the standard 30 nF II 4000 load
defined in the ARINC specifications (see output drive capability and capacitive loads for more details). All outputs are
protected from voltage spikes with diodes connected between the output pins and the supply lines.

For More Information, call 1-800-722·7074.

Raytheon Semiconductor

2·347

RM3182A
A New Option: Amp AlAmp B

Output Drive Capability and
Capacitive Loads
The Traditional Approach
The RM3182A is capable of driving a high capacitive/
resistive load. If complete ARINC compliance is required
then Out A and Out B pins are recommended to maintain
the output impedance. In this configuration, driving the
full ARINC load of 30 nF II 4000 the output characteristic
takes on the transfer function of a low pass filter due to
the internal 37.50 resistor, the line resistance and the
capacitance associated with the cable. This will result in
a lower rise/fall time of the device. Equation 1.1 relates
the output voltage at Out A and Out B to the voltage at
the power amplifier's output. Output A is taken for this
example:
1.1

Applications
Out A = ____Am...,-:-PA-Z~L=-I2(ZLI2) + RoUT

Heat Sinking lAir Flow and Short Circuit
Protection

Where: ROUT =37.50 and ZL =RL II CL
The output as a function of frequency is given by
equation 1.2.

~TIfm)

= """

A(fm{ ~+2Poor

i,

+j Test inputs = OV
lEE (-VS>

Test inputs = OV

(+VL)

Test inputs = OV

100

Specifications
Typ
Max
10
13
-10
-13
0
+2.5
±5

30
19
19
Filter caps disconnected
Filter caps disconnected
Filter caps disconnected

V1H =2.7V
V1L =O.OV

V(A) = OV
V(B) =OV

CL= 50 pF, TA = 25°C
CL= 50 pF TA = 25°C
CL= 50 pF, f 0= 400 kHz
Filter caps = 39 pF
TA= 25°C
±Vs = 15V, TA = 15°C
±Vs = 12V, TA = 15°C
±Vs = 15V, TA = 15°C
±Vs = 12V, TA = 15°C
±Vs = 15V, TA = 15°C
±Vs = 12V, TA = 15°C

4.0
3.5

10
10
10

5
0.5

0.0
15
1.0

4.3
4.0
0.02
0.3
40
30

O.OS
O.S
70
70

800
320
3.7
3.0
S.7
7.4
9.0

8.6

Units
V
V
V
V

kn
kn
kn

SO
25
25
3
3
3

2.7

TA= 25°C
Full temp. range
TA=25°C
Full temp. range

Vex.

Min
6.5
-6.S
-2.S

pF
pF
pF
V
V
~
~

V
V
V
V
ns
ns
ns
ns

7.0
6.0
15.0
14.0
20.0
1S.0

rnA
rnA
rnA
rnA
rnA
rnA

Notes:
1. With noise filter capacitors disconnected.
2. Guaranteed by design.
For More Information, call 1-800-722·7074.

Raytheon Semiconductor

2-353

RM3183
Truth Table
ARINCnputs
V(A)- V(S)
Null

Test Inputs
TESTA
TESTS
0
0
0
0
0
0
1
0
1
0

low
High
YeA) =OV, V(B) =OV
V(A) =OV, V(S) =OV
V(A) =OV, V(S) =OV

Outputs
OUTA
0
0

OUTS
0

0

1

0

0
0

1
0

Functional Block Diagram
+Vs

+Vl

r--J~-In 1A
In 1B
Cap 1A

______1___ ,
115

18 1
Input
Protection
& Level
Shift

16
191

Out 1B

Cap1B

17

TestA

21

Test B

20

1

I
I
I
I

Test
Interface

I
In2A

6

4

Cap2A

71

3

8

1

In2B

Cap2B

Out2A

I
I

Input
Protection
& Level
Shift

5

Out2B

1

---r---------g:r---I
-Vs

2-354

Out1A

Gnd

Raytheon Semiconductor

65-4708

For More Information, call 1-800-722·7074.

RM3183
Typical Performance Characteristics
Propagation Delay vs. Temperature
CL =50 pF, CFlLliR =39 pF

iii'
S.

}'

g

Q.

f
c.

1000
900
800
700
600
500
400
300
200
100

Supply Current VS. Temperature
12

-- -

- -

-

11

...... '"
---:r
TrLH -

C

.§.
C
~

B

-

T pHL

....

-So

-35

-10

15

65

40

90

115

Vs

7 I-- VL
6

::J

~

o

8

5

II)

-Vs (lee l

9

~

Q.
Q.

Vdloo)

10

+Vs(lccl

4
3
-SO

140

= :l:15V
= +5V

-35

-10

15

40

65

co

90

115

~

140

Temperature (Oc)

Temperatura (Oe)

Output Voltage High vs. Output Current

Output Voltage Low vs. Output Current

0.75 I - - - + - - - I - - - t -

f...
~

0.50

~-~--+--+-~-r

-;;P

0.25 t---+---::01""'--=""""''---+-~'-::~--1

.

°0~-0~.5~--1~~----1~.5----2~.0--~2.~5---3~.0~
lodmA)

Propagation Delay VS. Filter Capac~ance
TA = 25°C

TR and TF vs. Temperature
70

3.0

T~ ".,

iii'
S. 50
E 40

•

1=

.a:~

30
20

10

o

-SO

.1

.L

60

:::::

----

-35

,,/'

.---- --, V

-10

15

i[

",,/'"

.....

2.0

g

S

1.5

Q.

1.0

65

90

115

~

140

~

-:::-

'/

/" ~

.----

TpHL

0.5

o
o

Temperature (Oc)

For More Information, call 1-800-722-7074.

~

./

--~~

:0-

TF

2
c.
40

I

-'-

2.5 -T.=+25°C

50

100

150

200

250

300 350

~

400

Filter Capacitance (pF)

Raytheon Semiconductor

2-355

RM3183
Rise/Fall Times

Propagation Delay
+10V

ARINC In
(Differential) OV

L.J
I

I
1
1
Logic Out
(A Output)

r-

rI

---11

I
I
1

Logic
Out

mL

I
TpLH--+'1

I I
;+"1

I

I I
I I

I
1

-+I~

I I

1 I

+!

~-

TF

TPHL

AC Test Waveforms

+15V

VIN1

0.1 J.IF ~

-15V

0.01 J.IF ~

0.01 J.IF ~

11

VOLIn

18
';:"

V0UT2
16

RM3183
8 I - - -.....--i~) Voor3
';:"

14 51---+~~ Voor4
~~--T---r-~~~~
';:"

Notes:
';:"
1. VIN =400 kHz square wave. -3.5V to +3.5V.
2. Set VREF = +3.5 Vto test Voun and VOUT3.
Set VREF = -3.5 V to test VOUT2 and VOUT4.
3. 50 pF load capacitance includes probe and wiring
capacitance.
AC Test Schematic Diagram

2-356

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RM3183
Circuit Description
The RM3183 contains two discrete ARINC 429 receiver
channels. Each channel contains three main sections: a
resistor-diode input network, a window comparator, and
a logic output buffer stage. The first stage provides
overvoltage protection and biases the signal using
voltage dividers and current sources which are internally
connected to the +VL logic supply. This configuration
provides excellent input common mode rejection and a
stable reference voltage for the window comparators.
Because the threshold for switching is determined by
this circuitry, ±5% tolerance is recommended for the +VL
supply. The test inputs will set the outputs to a
predetermined state for built-in test capability. The
ARINC inputs must be forced to OV when using the test
inputs. If the test inputs are not used, they should be
grounded.
The window comparator stage generates two serial data
streams, one having logic 1 states corresponding to
ARINC "high" states (OUTA), and the other having logic
1 states corresponding to ARINC "low" states (OUTB).
An ARINC "null" state at the inputs forces both outputs
to logic O. thus, the ARINC clock signal is recovered by
applying a NOR function to OUTA and OUTB.
The output stage generates a m compatible logic
output capable of driving several gate inputs.

Applications Information
The standard connections for the RM3183 are shown in
Figure 1. Dual supplies from ±12 to ±15 VDC are
recommended for the ±VS supplies. Decoupling of all
supplies should be done near the IC to avoid
propagation of noise spikes due to SWitching transients.
The ground connections should be sturdy and isolated
from large switching currents to provide as quiet a
ground reference as possible.

For More Information, call 1-800-722-7074.

The noise filter capacitors are optional and are added to
provide extra noise immunity by limiting the noise
bandwidth of the input signal before it reaches the
comparator. Two capacitors are required for each
channel and they must all be the same value. The
suggested capaCitor value for 100 KHz operation is 39
pF, which will give a noise bandwidth of approximately
800 KHz. For lower data rates, larger values of
capacitance may be used to yield better noise
performance. To get optimum performance, the
following equation should be used to calculate capaCitor
value for a specific data rate:
C=

3.95 x 10-6
FO

FO =Data rate, bits/sec
The RM3183 can be used with the Raytheon RM3182
Une Driver to provide a complete analog ARINC 429
interface. A simple application which can be used for
systems requiring a repeater-type circuit for long
transmissions or test interfaces is given in Figure 2.
More RM3182 drivers may be added to test multiple
ARINC channels, as shown.
An all digital Ie is available which forms a complete
receiver system when combined with the RM3183. The
Thomson EF4442 is a four channel ARINC 429 receiver
IC which contains all the digital circuitry required to
interface with an 8-bit processor. Each channel consists
of a 32-bit register, an 8-bit status word comparator, and
a 24-bit latch. A multiplexer and 8-bit data bus buffer
form the interface to the system microprocessor. Rgure
3 shows a typical ARINC application having both
transmit and receive functions using four ICs: the
RF4442, plus the RM3182 driver and two RM3183 dual
receivers. Fore more information on the EF4442,
contact Thomson Military Semiconductors at (714) 9576018.

Raytheon Semiconductor

2-357

RM3183
Typical Applications
+5V

+15V

RM3183

18
ARINC
Channel

16

1

~PF

InlA
15

In lB

19 CaplA

12

A }Channell
Data Out
B To logic

17 CaplB
fl9PF
6

ARINC
Channel

4

2

39pF

7

rf

jj3
_
39pF

logic
Test
Inputs

{

2
20

In2A

8

In2B
5

Cap2A

A } Channel 2
Data Out
To logic
B

Cap2B

TestA
Test B

-15V

65-4710

Figure 1. ARINC Receiver Standard Connections

ARINC
Test
Channel
Input

A)

B

Test
Channel

1

A) Test
Channel
I

B

2

I

I

I

+ +

To Addnional
Channels

65-4711

Figure 2. Repeater Circun

2-358

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RM3183
Inputs
Mode

Vas

RM3182
ARINC
Channel

o

In lA

OutlA

HO

In lB

OutlB

LO

RM3183
ARINC
Channel
1

In2A

Out2A

H1

In2B

0ut2B

Ll

Nl

Dala(A)

NO

Dala(B)
-Va

EF4442

-::'

+Va GND -Va
In lA OutlA

H2

iRa
!Wi

OutlB

l2

Clock

InlB

2

RM31B3
In2A

ARINC
Channel
3

In2B

}

0ut2B

F~

Microprocessor

Micraprocessor

00-08

DeBus

H3

0ut2A

-15V

-::' 75 PF[l'T75 pF

Reset

ARINC
Channel

ARINC
UneOut

AO

La

From
Address
Decoder

Al

CS

_.....

To +5'1

Figure 3_ Four-Channel ARINC Receiver Circu~
-15V
10n

1/2W
+15V

lB

4
':'

10K

5
10K

16

RM3183

6

10K
15

10K

8

':'

14

9

11

12
':'

':'

10K

10n

1/2W
+5V

10n
112W

+15V

Burn-In Circun
For More Information, call 1-800-722-7074_

Raytheon Semiconductor

2-359

I\)

en

l;,

en

(')

o

::r

CD

>

I BlAS1

D. n.

~pK

.

l~K

20K

!- 10K ~
10K:

,0-

Co

10K;~

2S0K

<~

I

>

~~Kv
t-.....

K

L

1.2~!<

20K

'"

~;"'"

1

L

n.

+ I BlAS2

::s

0'
0

::s

a.
c

.

a0

.....

G

n.

Test

...

ct.

J

..... 1~~SK

'"

Co

i

12SK

2.SK

v

2.SK

,,,,,.

~

"
To Section 2

...

..... 1••~K

V

~

'"
2.~!<

-Vs .....

20K

1.25K

........

L

1'>0.

-0
Out 1B

r-..
f5.47t1

V

2.SK

TestB

,.,..,..

.

-0:-- ......

1.2SK V

~.
.' ~
." 10K.,,10K

2.SK

' ...

~

~

..o

20K

I

a
f

f

,.

10K

D-

Cap

'~

10K

2S0K

K

20K

In

Out 1A

~SK

:;SK

0

3

c
cS"

~:

CD

fC

]

'Y

::a

~
:::J'

SK~
.~

SK.;

3

ac=r

1:~~K

.,)
~

~.!>K

r

~

iiJ
3

~

~

RM3283
RM3283
Dual ARINC 429 Line Receiver

Description

Features

The RM3283 consists of two analog ARINC 429
receivers which take differentially encoded ARINC level
data and convert it to serial m level data. The RM3283
provides two complete analog ARINC receivers and no
external components are required.

•
•
•

Input level shifting thin film resistors and bipolar
technology allow ARINC input voltage transients up to
±1 OOV without damage to the RM3283.
Each channel is identical, featuring symmetrical
propagation delays for better high speed performance.
Input common mode rejection is excellent and threshold
voltage is stable, independent of supply voltage. Data
outpuls are TTL and CMOS compatible.

•
•
•
•
•
•

Two separate analog receiver channels
Converts ARINC 429 levels to serial data
Built-in m compatible complete channel test Inputs
m and CMOS compatible outputs
Low power dissipation
Internal bandgap
Short circuit protected
MIL-STO-883B screening available for ceramic
packages
Available in 20-lead ceramic DIP, 20-pad
LCC, and 20-lead SOL

Two TTL compatible test inpuls used to test the ARINC
channels are available. They can be used to override the
ARINC input data and set the channel outputs to a known
state.
The Raytheon RM31821RM3182A line driver is the
companion chip to the RM3283 line receiver. Together
they provide the analog functions needed for the ARINC
429 interface. Digital data processing involving serial-toparallel conversion and clock recovery can be
accomplished using one of the ARINC Interface IC's
available or by an equivalent gate array implementation.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

2-361

RM3283
Absolute Maximum Ratings

Ordering Information

Supply Voltage (Vcc to VEe) .............................. +36V
VLOGIC Voltage ....................................................+7V
Logic Input Voltage .................. -o.3V to VLOGIC +0.3V
Temperature Range
Storage ... ~ ................................... -65OC to +150OC
Operating .................................... -55OC to +1250C
Junction Temperature ....................... -55OC to +175°C
Lead Soldering Temperature
(60 sec., DIP, LCC) ................................... +300°C
(10 sec., SOL) ........................................... +260°C

Part Number

Operating
Temperature
Range

Package
M

RV3283M
RM3283D
RM3283L

o
L

-40°C to + 85°C
-55°C to +125°C
-55°C to +125°C

Notes:
D - 20-lead ceramic DIP
L - 20-pad Lee
M _ 20-lead SOL (Wide Body SOle)

Thermal Characteristics (Stili air, soldered on a PC board)
Parameter
Max Junction Temp.
Therm. Res. 9JA
Therm. Res. 9JC

20-Pad
LCC

20-Lead
COIP

1750C
85°CIW
20°CIW(1)

175°C
70°CIW
28OCIW(1)

20-Lead

SOL

Notes:
1. MIL-STD·1835

Connection Information
Top View

Top View

Pin
1

Top View

2
3
4
5
6
7
8

9
10
11
12
13

14

86-0558

2-362

Raytheon Semiconductor

15
16
17
18
19
20

Function
-Vs
TestA
Cap2B
In2B
Out2B
In2A
Cap2A
Out2A
+VL
NC
+Vs
Out1B
NC
Gnd
Out1A
In1B
Cap1B
In1A
C1A
TestB

For More Information. call 1-800·722·7074.

RM3283
DC Electrical Characteristics
TA = -Ssoc to +12SOC, ±12V SVs S±1SV, VL = +SV, unless otherwise noted
Symbol

icc (+VS>
lEE (-VS>
IL (VL)
V (2)
TL

VTHI~/

VIN
V1C(3/

Parameter

Conditions

Test inputs = OV
Test inputs = OV
Test inputs = SV
V(A)-V(B)
V(A)-V(B)
V(A)-V(B)
V(A)andV(B)-GND

Low threshold
High threshold
OUTA and OUTB = 0
Max common moae
frequency = SO kHz

Input resistance, Input A to Input B
Input resistance, Input A to Gnd
Input resistance, B to Gnd
C(I.4)
Input capacitance, A to B
I
C (1.4)
Input capacitance, A to Gnd
H
C (1.4)
Input capacitance B to Gnd
G
Test Inputs (Test A, Test B)
VIH(5)
Logic 1 input voltage
V (5)
Logic 0 input voltage
IL
Logic 1 input current
IIH
Logic
0 input voltage
IlL
Outputs
IOH = 100 J.lA
VOH
IOH=2.S rnA
Ia. = 100 J.lA
Va.
Ia. =2.0 rnA
Tr6)
Rise lime
Tf(6)
Fall Time
Propagation delay
TPlH
Output low to high
Output
high to low
TPHL
R,
RH
RG

Filter caps disconnected

!: Declflcallons
Typ
Max
4.3
6.0
10.1
12.0
14.0
17.S
4.7
5.0
5.3
5.7
6.0
6.3
-2.5
2.S
0

Min

±5
35
20
20

50
25
25

2.7
0
120
15

V,H =5V
VIL =O.SV
TA = 25°C
Full temp. range
TA =25°C
Full temp. range
CL= 50 pF @ 25°C
CL= 50 pF @ 25°C
CL= 50 pF, f= 400 kHz
Filter caps = 0 pF
TA =25°C

kO
kO
kO

10
10
10

Filter caps disconnected
Filter caps disconnected

4.0
3.5

4.3
4.0
0.02
0
SO
40
700
700

Units
rnA
rnA
rnA
V
V
V
V

pF
pF
pF
V
V

O.S
300
40

J.lA
J.lA

0.1
O.S
70
70

V
V
V
V
ns
ns
ns
ns

Notes
1. As stated in ARINC429
2. Vr refers to the !hreshold voltage at which !he channels output switches from low to high or from high to low
3. Common mode voltage present at bo!h ARINC inputs
4. Guaranteed by design
5. Test inputs should be connected to ground if not used
6. Sample tested

For More Information, call 1-800·722·7074.

Raytheon Semiconductor

2·363

RM3283
Typical Performance Curves
Propagation Delay vs. Temperature
CL =50 pF, CALTER =0 pF

Supply Current vs. Temperature
20

~Or-------------r-----------~

800 1--_______-+__T::;;po;Hl"",---O::::;-'-==--I

t;;;;;~~===:f~~::::::=::.::-:::::~P~LHC-=l

..... 700

~ 600 F"
;
~

C

.§.

500r-------------r------------4
400r-------------r------------4

C

J 300r-------------r-----------~

I!!
...
::J

~ 200r-------------r-----------~

!

10~

-55

25

U

18
16
14
12
10
8
6
4
2

IL
1=
Icc

-55

25

Temperature (Oc)

Output Voltage High vs. Output Current
4.5 ,----,-----r----:r------,-----r---,

r----r-----r---,r------r----,---~

4.3 i-=---\---=""-l::-----1r----\----I-----i

0.75 r----\----l-----\--

Gi'

!:= 0.50 r----/----+----t-",c..+
...

::P
0.25

__

o

~

0.5

__

~

____

1.0

~

__

1.5

~

__

2.0

~

__

2.5

i

4.1 ~~~~-I----,~~~---I-----i

~:z:

3.9 1 - - - - 1 - - - 1 - -

~

1----/----::.I-~"""""~::...-+::___4--_l

O~

125

Temperature (Oc)

Output Voltage Low vs. Output Current
1.00

!

o

125

3.7 I----/----+---If---+----+---''''''d

~

3.5 0~--~--~-----''----~--~--~3.0
0.5
1.0
1.5
2.0
2.5

~

3.0

IOH(mA)

100(mA)

Propagation Delay vs. Filter Capacitance
TA =25"C
70
60

fi)

S- 50
eD

E 40

j::

;f

=

a:

~

~

-~ ---

3.0

~>-

TA

as

30

~

20

e

Co

10

o

-55

25

I

!

125

2.0

I

~

1.5
1.0

Q.

.;'

~
~~

::.V

--

.....

~

./

./
~

I--"":T

pHl

0.5

o

o

Temperature (OC)

2-364

I

2.5 -TA=+25°C

50

100

150

200

250

300 350

~

400

F!!ter Capac!tance (pF)

Raytheon Semiconductor

For More Information, caJI1-8oo-722-7074.

RM3283
Rise/Fall Times

Propagation Delay
+10V
ARINC In
(Differential) OV

L..J
I

I
I
I

Logic Out
(A Output)

r-

r-l

---.JI

I
I
I

Logic
Out

JflL
r-

I
TpLH~1

I

I

I
I
I

I
I
I

-+--! :-

65-4709A

T pHL

AC Test Waveforms

+1SV

1n1A

O.111F ~

-ISV

O.1I1F ~

+5V

O.1"F ~

"

OUl1A

1a

121-~P-@ OUl1B

1n2A @---f6
RM3283

ai----'t-@ OUl2A
14 Si---.......@

L.....:i=---T---T--T---T-' 5OpF~

OUl2B

.,..

Notes:
....
1. Y'N =400 kHz square wave, -3.5V to +3.5V.
2. Set VREF = +3.5 V to test VOUT! and V0UT3 •
Set VREF = -3.5 V to test V0UT2 and V0UT4.
3. 50 pF load capacitance includes probe and wiring
capacitance.

AC Test Schematic Diagram

For More Information, call 1-1100-722-7074.

Raytheon Semiconductor

2-365

RM3283
RM3283 Test Input Truth Table
ARINC Inputs
VeAl-VeB)
Null
Low
High

Test Inputs
TESTA
TESTB
0
0
0
0
0
0
1
0
1
0
1
1

X
X
X

OUTA
0
0
1
0
1
0

Outputs
OUTB
0

Output
State
Null
Low
High
Low
High
Null

1
0
1
0
0

Functional Block Diagram
+Va

+Vl

1--jL-----------1---~
RM3283

In lA

,... lBI

In 18

161

-

CaplA

Cap 18

r.

""
y

y

19!
17i

TestA ,... 21

-

Test 8
Cap2A

Cap 28

-

r.

In 28

r.

Channel
Test
Circuitry

201

I

3

i

4

i

'Y

A

•• y

!lS "
!

112

I
I
I
I
I
I
I
I

-

Bit Detection r-and Level
Shifting f-Hysteresis

"""

-Va

2·366

Bandgap Voltage
Reference
Threshold
Generator

Output
Driver

71

61

In2A

Bit
Detection f-and Level
Shifting
Hysteresis t -

""

~yyy

18

Output
Driver

is

!
Gnd

Raytheon Semiconductor

-

Out lA
Out 18

Out2A
Out2B

65-5925

For More Information, call 1-800·722·7074.

RM3283
Circuit Description
The RM3283 contains two discrete ARINC 429 receiver
channels. Each channel contains three main sections: a
resistor input network, a window comparator, and a logic
output buffer stage. The first stage provides overvoltage
protection and biases the signal using voltage dividers
and current sources, providing excellent input common
mode rejection. The test inputs are provided to set the
outputs to a predetermined state for built-in channel test
capability. If the test inputs are not used, they should be
grounded.
The window comparator section detects data from the
resistor input network. A Logic 1 corresponds to ARINC
"high" state (OUTA) and a Logic 0, to ARINC "low" state
(OUTB). An ARINC "null" state at the inputs forces both
outputs to Logic O. Threshold and hysteresis voltages are
generated by a bandgap voltage reference to maintain
stable switching characteristics over temperature and
power supply variations.

CFILTER = 3,95 x 106
Fo
Where:
CFILTER is the capaCitor value in pF
Fa is the input frequency 10kHz SFa S 150 kHz.
The RM3283 can be used with the Raytheon
RM31821RM3182A line driver to provide a complete
analog ARINC 429 interface. A simple application
which can be used for systems requiring a repeatertype circuit for long transmissions is given in Figure 2.
More RM3182 drivers may be added to test multiple
ARINC channels, as shown.

The output stage generates a TTL compatible logic
output capable of driving 3 mA of load.

Applications Information
The standard connections for the RM3283 are shown in
Figure 1. Dual supplies from ±12 to ±15 VDC are
recommended for the ±Vs supplies. Decoupling of all
supplies should be done near the IC to avoid propagation
of noise spikes due to switching transients. The ground
connection should be sturdy and isolated from large
switching currents to provide as quiet a ground reference
as possible.
The noise filter capacitors are optional and are added to
provide extra noise immunity by limiting bandwidth of the
input signal before it reaches the window comparator
stage. Two capacitors are required for each channel and
they must all be the same value. The suggested
capacitor value for 100 kHz operation is 39 pF. For lower
data rates, larger values of capacitance may be used to
yield better noise performance. To get optimum
performance, the follOWing equation can be used to
calculate capacitor value for a specific date rate:

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

2-367

RM3283
+5V

Typical Applications

+15V

RM3283
18
ARINC
Channel

16

1

In 1A
15

In 1B

39 pF 19

E

Cap1A

12

A }Channel1
Data Out
B To logic

17 Cap1B

fl9PF
6
ARINC
Channel

4

2

39pF

E

2

{

8

In2B

7 Cap2A

jj3
39pF
_
logic
Test
Inputs

In2A

20

5

A } Channel 2
Data Out
To logic
B

Cap2B

TestA
TestB

·15V

65-471OA

Figure 1. ARINC Receiver Standard Connection

ARINC
Test
Channel
Input

A}

B

A}
I
I

I
I
I

B

Test
Channel

1

Test
Channel

2

• +
To Additional
Channels

65-4711A

Figure 2. Repeater Circuft

2-368

Raytheon Semiconductor

For More Information. call 1-800·722·7074.

RM3283
+5V

Input.
Mode

V..

ARINC
Channel

0

InlA

CUllA

HO

InlB

CUllB

LO

RM3283
ARINC
Channel
1

In2A

CluI2A

Hl

In2B

CluI2B

Ll

Nl

DaIa(A)

NO

Oala(B)

ARINC
UneCUI

-V.

-15V

EF4442

lI8sii
IRQ

+V. GNO -V.

ARINC
Channel

2

InlA

CUllA

H2

RiW

In lB

CUllB

L2

Clock

RM3283

ARINC
Channel

3

rT

Oul2A

H3

In 2B

CUI 2B

l3

'-l....L--I

Microprocessor

00-08

,-,ln2A

OalaBUB

AO
Al

Cs
To+5V

65-4536A

Figure 3. Four-Channel ARINC Receiver Circuit

-15V

loa
112W
+15V

18

r----i4
10K

5

RM3283

t-----t---i 6
10K

8

16
10K
15 1-4-.1\1\,..,....-,

14

9

11

loa

112W

loa

112W
+15V

65-4707A

Burn-In Schematic Diagram

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

2-369

RM3283

2-3iO

Raytheon Semiconductor

For More Information, call 1-800·722·7074.

Section 2 - Application Specific Standard Products

Communications

LAN Server

The RCC700 is a high speed transmitter, receiver
(transceiver) for serial fiber optic or copper communications. It can operate at data rates of 194.40, 200.00,
265.625 Mbaud. this device together with circuitry
driving a coax or a fiber optic line, forms the complete
physical layer of a communication system and as such
is fully compliant with the Fiber Channel Physical Layer
Standard (FC-PH), Enterprise Systems Connection
Architecture (ESCON) and Serial Storage Architecture
(SSA). The device can also be used as the physical
transport for an Asynchronous Transport Mode LAN,
operating at 194.4 Mbaud. The RCC700 integrates a
complete phase-locked loop clock recovery and data
retiminglgeneration subsystem, a phase-locked loop
clock synthesizer, a 10:1 MUX and a 1:10 DeMUX, and
an 88/1 OB encoder/decoder. The device is implemented
in a submicron CMOS process which offers the possibility of back integrating the protocol circuitry for the
network as well.

For More Information, call 1-800-722-7074.

85-6464

The RCC521 is a Synchronizer/Framer that will find its
applications primarily in a Synchronous Optical Network
(SONET) and ATM 155.52 Mbls physical transport.
SONET is an international, digital standard for fiber optiC
communications and is expected to become the transport backbone of the broadband network of the future. It
defines a multiplexing hierarchy that starts with a data
rate of 51.84 Mbls (OC1) and goes to 2488.2 Mb/s
(0C48) in multiples of OC1. The RCC521 provides the
frame recognition and synchronization functions required of a SONET line interface at 155.52 Mb/s (OC3).
The device has on chip phase-locked loops for clock
generation and clock and data recovery. It provides
frame recognition, byte alignment, scrambling/
descrambling, bit interleaved parity generatiOn/checking
and alarm generation in accordance with CCITT and
ANSI standards. The device also satisfies the requirements in Bellcore TR-NWT-000253.

Raytheon Semiconductor

2-371

Section 2 - Application Specific Standard Products

2·372

Raytheon Semiconductor

For More Information. call 1-800·722·7074.

RCC700
RCC700
ATM/ESCONTM/Fibre ChanneI/SSA Transceiver
TM

200 or 265.625 Megabaud
Description

Features

The RCC700 is a monolithic transmitter/receiver IC
integrating a complete phase-locked loop clock recovery
and data retiming/regeneration subsystem, a phase
locked loop clock synthesizer, a 10:1 Mux, a 1:10
Demux, an 8M Ob Encoder and a 10bl8b Decoder. It
operates with a single +5V power supply. The RCC700
provides a complete physical interface in compliance
with the Fibre Channel Physical layer Standard (FCPH), Enterprise Systems Connection Architecture
(ESCON) and Serial Storage Architecture (SSA)
specifications. It can also be used for the transport of
Asynchronous Transfer Mode (ATM) LAN operating at
194.4 Mbaud (155.52 Mbls OC-3 data rate with 8b/10b
overhead).

•
•
•
•
•
•
•
•
•
•

The RCC operates at 194.41200 Megabaud when FS is
at a level high and at 265.625 Megabaud when FS is
low (i.e. Gnd).

Applications

For More Information, call 1-800-722-7074.

•

•
•

•
•
•
•
•
•

200 or 265.625 Megabaud data rates
Compliant with the Fibre Channel and ESCON
standards
PLL clock and data recovery
Clock synthesizer
On-chip lock detect circuitry
8b110b Encode/Decode
Parity generate/check
Low power dissipation: 600 mW (typ) @ 200 Mbaud
Byte sync on K28:1, K28.5 or K28.7
Single power supply: +5V
m compatible parallel data inputs/outputs
PECl compatible serial data inputs/outputs
Available in 68-pin PlCC and 54-pin PQFP

Fibre Channel, ESCON, and SSA transceiver
ATM transceiver
High-speed fiber optics or coax links
High-resolution graphic display terminal
High-speed test equipment
Video data transmission

Raytheon Semiconductor

2-373

RCC700
Absolute Maximum Ratings1

Ordering Information
Part Number

Package

Operating
Temperature
Range

RCC700 Pl
RCC700PO

Pl
PO

O°C to +70°C
O°C to +70°C

Notes:
PL =68-Pln PLCC package
PQ =64-Pln PQFP package

Operating Temperature Range ................... O°C to 700C
Storage Temperature Range ............... ·S5°C to +150°C
Junction Temperature Range ..........••.. -55°C to +1500C
lead Temperature Range (Soldering 10 sec.) ..... 300OC
Positive Power Supply, Vee .................................. 0 to SV
Voltage Applied to Any TIL Inputs ................... -1 to SV
Voltage Applied to Any PECl Inputs ................. -1 to SV
Voltage Applied to Any CMOS Outputs ............ -1 to SV
Voltage Applied to Any PECl Outputs .............. -1 to SV
Current from Any CMOS Outputs ............. -50 to 50 mA
Current from Any PECl Outputs ............... -50 to 50 mA
Voltage Applied to VREF Output Voltage ........ -1 to +SV
Notes:
1. "Absolute Maximum Ratings" are those beyond which the
safety of the device cannot be guaranteed. They are not meant
to imply that the device should be operated at these limits. If
the device is subjected to the limits in the absolute maximum
ratings for extended periods, its reliability may be impaired.
The tables of Electrical Characteristics provide conditions for
actual device operation.

Recommended Operating Conditions
Svmbol

TA
Vee
R

Parameters
Ambient operating temperature
Positive supply voltage (OVCC and AVeC)
PECl differential load resistance (2)

Min
0
4.75
80

TVD

5.0
100

Max
70
5.25
150

UnHs
"C
V

n

Notes
2. Differential load resistance 01 loon equals connection olSOn to AC ground on each of DOUT, DOUT.

2-374

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RCC700
Connection Information
Pin
1
2
3

64-Pln PQFP Package
(Top View)

4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
~wmO~NM~~w~romo~N
~~~NNNNNNNNNNMMM

Note: Contact factory for 64-pin PQFP dimensions

Pin
1
2
3
4

68-Pln PlCC Package
(Top View)
mw~w~~~N~ffi~~~~~~~
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

•

60
59
58
57
56
55
54

53
52
51
50
49
48
47
46
45
44
~re~gM~~~~~~~~~~~~

For More Information. call 1-800·722·7074.

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

5

6
7
8
9
10
11
12
13
14
15
16
17

18
19
20
21
22
23

Function
002
001
000
OVCC
OVCC
DGND
OGND
POUT
KOUT
EF
RBe
PE
NC
PIN
PIN
En<
DI7
DI6
DIS
DI4
DI3
012

Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

Function
Dl1
010
NC
TBC
DVCC
DOL
DGND
DVCC
DOL
DGND
OOUT
DOUT
LSEL
AVGND
AVeC
AVCC
AGND
AGND
Avec
Avec
43 AGND
44 SDOUT

Pin
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

Function
SOIN
SDIN
FI
FIN
FS
LD
SYNCEN
BSYNC
DveC
ovee
Dvec
DGND
DGND
DGND
D07
006
DOS
D04
D03
DGND

Function
DGND
DGND
DGND
D07
D06
DOS
D04
D03
NC
NC
002
DOl
DOO
DVCC
DVCC
DGND
DGND
POUT
KOUT
EF
RBC
PE
Ne

Pin
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

Pin
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

Function
LSEL
AGND
AVCC
AVCC
AGND
AGND
AVCC
AVec
AGND
SDOUT
SDiN
SDIN
DIN
DIN
NC
FS
LD
SYNCEN
BSYNC
DVeC
DVCC
DVCC

Raytheon semiconductor

Function
PIN
KIN
En<
NC
DI7
DI6
DIS
DI4
DI3
Dl2
Dll
DIO
GND
TBC
DVCC
RST
DGND
DVCC
DOL
43 NC
44 DOUT
45 DOUT
46 VREF

2·375

RCC700
section (DOUT/DOUT). When lESl is low,
Le., tied to GND, the receiver accepts the
incoming input data (DIN/DIN). Connect to
GND or leave open when not used.

Pin Definitions
Name
DVCC

Function
Positive supply for digital circuitry. The nominal
value is 5V :1:5%. VCC should be bypassed to
the ground plane with a 10,000 pF chip
capaCitor placed as close to the pin as possible.

AVCC

Positive supply for analog circuitry. The
nominal value is 5V :1:5%. VCC should be
bypassed to the ground plane with a 10.000
pF chip capaCitor placed as close to the pin as
possible.

OGND

Chip ground for digital circuitry. DGND should
be connected to the printed circuit board's
ground plane at the pins.

AGND

Chip ground for analog circuitry. AGND pins
should be connected to the printed circuit
board's ground plane at the pins.

DIN/DIN Receiver differential input data (PECl levels).
SYNC EN Byte Synchronization Enable (ffi levels).
When SYNC EN is high, the RCC700 will
automatically resynchronize the demultiplexer
to byte align with the received K28.1 , K28.5 or
K28.7 for both negative and positive running
disparities (RD- and RD+). Connect to GND or
leave open when not used.
BSYNC

Byte Synchronized output flag (CMOS levels).
BYSNC goes to a HIGH level for one byte
clock when SYNCEN is high and the RCC700
detects and resynchronizes on K28.1, K28.5
or K28.7.

SDIN,
SDIN

PECl input of the PECl to CMOS converter
for the signal detect flag of the fiber optics
receiver module. leave open when not used.

SDOUT

CMOS output of the PECl to CMOS converter
for the Signal detect flag of the fiber optics
receiver module.

D10-D17

Transmitter input data (ffi levels).

TBC

Transmit Byte Clock (TTL levels). Input
reference frequency for the internal high speed
clock generator: 20 MHz or 26.5625 MHz.

KIN

K character indicator input (TTL levels).

000 ...7

Receiver output data (CMOS levels).

PIN

Odd parity input (TTl levels).

KOUT

K character indicator output (CMOS level).

PE

Parity Error indicator output (ffi levels). PE
will stay low when the on-chip calculated odd
parity matches the incoming parity PIN. If
there is a parity error, the PE flag is raised to a
level high.

POUT

Odd parity output (CMOS level). POUT is high
when the parity of the 000/007 byte is odd.

RBC

Receive Byte Clock (CMOS levels): 20 MHz or
26.5625 MHz.

lD

lock Detect output flag (CMOS levels). It is
HIGH on powerup. It goes lOW on loss of
lock. It remains lOW for 50 ~ and cycles
HIGHILOW for every 50 ~ until lock is
established. In the locked state, lD remains
HIGH.

EF

Error Flat output (CMOS levels). EF goes high
to flag running disparity and coding violations
detected during the 108/8B decoding.

FS

Frequency Select (CMOS levels). The
RCC700 operates at 200 Mbls when FS is at a
level high and at 265.625 Mbls when FS is low
(Le., GND).

DOUI
DOUT

DOL

Transmitter differential output data (PECl
levels). The output is a current mode driver
with a nominal current driver of 12 rnA. To
generate a 1.2~, use a 1000 resistor
across DOUT, DOUT.
Data Output low controls inputs (TTl levels).
When high, it forces the outpuUo a logic low
state (DOUT = lOW and DOUT = HIGH) to
protect the fiber optic source. Connect to GND
or leave open when not used.

VREF

Data output threshold reference to provide
ease of interfacing to a single-ended input.

LSEL

(TTL levels) Internal differentialloopback for
"on-board" diagnostic of the device. When
loop select (lSEl) is high, the receiver
accepts the output data from the transmitter

2-376

RST

Raytheon Semiconductor

Asynchronous Chip reset input. Chip is reset
when RST is brought to a level high (CMOS
levels).

For More Information, call 1-800-722-7074.

RCC700
DC Electrical Characteristics
Vee = 5V ±5%, GND = OV unless otherswise indicated)
Svmbol Parameters
Transmitter Section
Vih
m Input Voltage High
Vii
m Input Voltage low
m Input Current
lin
Ci
Input Capacitance
Vohp
PECl Output Voltage High
Volp
PECl Output Voltage low
10
PECl Output Current
VREF Output Threshold Reference
IREF
VREF Output Current
Receiver Section
Vih
m Input Voltag High
Vii
m Input Voltage low
lin
m Input Current
Vcm
Com. Mode Range (DIN, DIN)
Vdiff
Diff. Input Voltge (DIN, DIN)
lip
PECl Input Current

Test Conditions

Min
2.0
0
-1

Rdiff= 1000
Rdiff = 1000

4.1
2.9

TVD

iD.1
3
4.3
3.1
12

Max

Units

+5.5
0.8
1
10
4.5
3.3

V
V

.45 (Vohp +Volp)
1

.55 (Vhp +volp)

2.0
0
-1
2
0.2
-100

+5.5
0.8
1
5
5.5

3.5
0
1

VCC
0.5

~

pF
V
V
mA
V
mA
V
V
~

V
1

~

Vohc
Volc
lolc
ICC
PO

CMOS Output Voltge High
CMOS Output Voltage Low
Output Current
Supply Current
(200 Mb)
(265 Mb)
Power Dissipation (200 Mb)
(265 Mb)

Note 3

120
140
600
700

V
V
mA
mA
mA
mW
mW

Notes:
3. Under both transmit and receive output switching conditions.

For More Information, call 1-800·722·7074.

Raytheon Semiconductor

2·377

RCC700
AC Electrical Characteristics
(Vee = 5V ±5%, GND = OV unless otherwise indicated)
Svmbol Parameters
Transmitter Section
Fref
Input Clock reference frequency

Test Conditions

tacq
tids
tidh
Fout

Acquisition time
DINO ..7, KIN, PIN valid to TBC t setup
TBC ho DINO ..7, KIN invalid hold
Output data rate

tr,tf
trj
tdj

DOUT, DOUT rise and fall times
DOUT, DOUT pk-pk random jitter
DOUT, DOUT pk-pk deterministic jitter
Receiver Section
Input data rate variation
Input data transition density to
acquire and maintain lock
Loop acquisition time for 1OE-12 BER
Loop~ture range
DIN, DIN input rise and fall time
DIN DIN input peak to peak jitter
RBC pulse width high
RBC pulse width low
LD assert delay
LD pulse width
RBCt to 000 ..7, KOUT, POUT delay
200 Mbaud
265.5625 Mbaud
RBC period

--

fcc

0
tacq
fc
tri, tfi

ti
tH
tL
tld1
tld2
tod

T
f

Min

FS=O (GND)
FS= 1
Note 2

Tm

Max

Units

1

MHz
MHz
ms

26.5625
20

ns

4

ns
Mbls
Mbls

4

FS=O (GND)
FS= 1
20% to 80% points
Note 3
Note 4

265.625
200
500
300
100

ps
ps
ps

±1000

ppm

2500

bits
ppm

1

ns

0.07T
O.55T
O.55T

ns
ns
ns

0.2

±1000
20% to 80% points
NoteS
O.45T
O.45T

0.5T
0.5T
60
50

35

20
13.8
FS=O
ES-1

J.IS
J.IS

37.7

ns
ns
ns

_SO.O

~

23.8

Notes:
1. Test conditions (unless otherwise indicated): PECLinput rise and fall times S2 ns, RLOAD • 1OOil across DOUT, DOUT VBB - 3.7V; TTL
input rise and fall times $15 ns. Receiver input data rate =200 or 256.625 Mbls±I000 ppm; transition density ~.25.
2. Acqusition time is the time to establish lock once the device is pwoered up to the operating VCC range.
3. Input test patter K28.7. Jitter measured at 50% amplitude, for a BER of 10E-12.
4. Input test pattern K28.5. Jitter measured at 50% amplitude.
5. Guaranteed by design.

2-378

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RCC700
The RCC700 features a Data Output Low function
(DOL) that can force the data output (DOUT) to LOW for
protection of the fiber optic module transmitter diode.
DOL is controlled by the Protocol IC or the fiber optic
transmitter module. The RCC700 also incorporates an
Error Transmit input (ETX). The RCC700 sends a
violating code when ETX is brought to a logic HIGH. If
ETX stays HIGH for more than one word clock cycle, the
transmitter will send error bytes of alternate running
disparities in order to maintain the DC balance of the
line (100111 1011 or 011000 0100).

Transmitter Section
The RCC700 transmitter section includes a phaselocked loop synthesizer, an 88110B encoder, an input
parity checker and a 10:1 multiplexer. The RCC700
accepts a CMOS data byte (010-017) along with the K
character indicator (KIN) and parity bit (PIN).
The Parity Check circuitry calculates the odd parity of
the input data byte and compares it with PIN. If the
calculated parity differs from PIN, the transmitter flags
the error by bringing the parity error bit, PE, to a HIGH
level. For example, for 010-017 =00000101, PIN should
be 1. If PIN is not equal to 1, PE = 1.

The 200 or 265.625 MHz clock used for the serial
stream is generated using a PLL clock generator which
multiplies the input frequency, 20 or 26.5625 MHz, by a
factor of 10. A Frequency Select pin (FS) is used to set
the VCO center frequency. The VCO is set for 200 MHz
operation when FS is at a CMOS logic HIGH and
2675.625 MHz when FS is at a CMOS logic lOW. The
input clock reference for the PLl clock generator,
Transmit Byte Clock (TBC), typically comes from a
crystal oscillator or from the system.

The RCC700 transmitter section encodes the CMOS
input data byte 010 to 017) into a 1O-bit word using IBM's
8811 OB coding (see Table 1) The encoded word is then
converted to a serial high speed data stream (DOUTI
DOUT) at 200 or 265.625 Mbauds via a 10:1-UmeDivision Mux. The serial data stream (DOUT/DOUT) is
transmitted at PECl levels (positive shifted ECl levels,
Vth = +3.7V). in 68-pin PlCC package, a data output
threshold reference, VREF, is provided for ease of
interfacing to single-ended inputs. However, differential
connections are recommended.

FS~+===========~~~L~_r======~----~
_~ -=::=J High Speed Ie-

TBC

--1-----------1

',Clock Generator

I

EU~-+-------------------------'I~+10r~__~

rg-W
g

KIN --I--;.........,...----:'-----:~ -

-6

DID-DI?
PIN

_~...-------~;

--I--'--...;.;,..---------toi~.

t-

m

r-~

,..-+.1.-'----'---,

8B/l0B ~ Time
1.0:1
Encoder!-" Division
MUX

~arity

~
5

VREF
DOUT
~~
a 1-+-1-+-_ DOUT

l

5

.~

Check

PE.-~~-~------~~=~~---~
DOL
LSEL
LD

I. \ , , ' :

A

.,..

C~&

<

·"i

RBC

Disparity/
Code . .
Violation
Check

RST>-EF

L"
0'

KOUT ---+1'-1.5

r--

"'.

S L..,;,r",

DOD-DO? • •- g'
POUT
I·'· ~
BSYNC
SYNCEN

~

.....

r-

Parity L.....;..
Gen.
8B/l0B ~
'--Decoder I --

r-

.--L-~
N
l......- :...

Data
r---;;::
c
Recovery
Data Clk
x

~_+--_ DIN
__

DIN

'--

I-

1:10

Byte

Time I,
Alignment
Division tCircuit
DEMUX

I

Ir;:;-;PE~C::-;-L-::tO:-;C::;:M;;:O:;cS:-l+rt--< SDIN

~=t;;·~;;;;;;;;;;~~~~;;;;;;;;;;;~~~~=c=on~v=ert=e=r
=~:J--< SDIN
!
.!.
!!
•
)0

AVCC

For More Information, call1-800-?22-?074.

AGND

DVCC DGND

Raytheon Semiconductor

SDOUT

2-379

RCC700
Receiver Section
The RCC700 receiver section includes a complete
phase-locked loop clock recovery and data retimingl
regeneration subsystem, a byte alignment circuit, a 1:10
demultiplexer, an 8B110B decoder, a disparity/code
violation checker and a parity generator. The RCC700
accepts a differential PECl (positive shifted ECl levels,
VH = 3.7V) data stream (DIN/DIN) at 200 Mbauds or
265.625 Mbauds, recovers the clock and regenerates
the encoded serial data. The recovered encoded data is
then converted to 10 parallel data lines via 1:10 time
division demultiplexer and decoded into an -bit byte via
the 8B110B decoder. K Command characters are also
detected and indicated by bringing the KOUT pin to a
HIGH level. The odd parity of the output 8-bit byte (000007) is calculated and available at pin POUT. For
example, for 000-007 = 00000101, POUT should be 1.
The RCC700 also generates a Receive 8yte Clock
(RBC) for driving the CMOS protocol layer IC. All the
outputs to the protocol layer IC are at CMOS levels.
Running disparity and coding is checked during the 1OBI
B8 decoding and violations are flagged by bringing the
Error Flag (EF) to a HIGH level. If consecutive bytes
have more 1s or more Os, or if running disparity is
different from expected for the received code, or the
transmission character s not part of Table 1, EF goes
HIGH. If 100111 1011 or 011000 0100 is received,
EF=1, KOUT=1, 000·007=00000000.
The RCC700 contains a byte synchronization circuitry.
When enabled (SYNC EN high), the RCC700 will
automatically resynchronize the demultiplexer to align
with the leading seven bits (00111 11 or 11000 00) of
the transmission character, corresponding to reception
of K2B.1, K2B.5 or K2B.7).
SYNC EN pin gives the protocol layer IC the flexibility to
request the RCC700 to align only when required, e.g. at
power up or after loss of word synchronization.
The RCC700 also incorporates a lock Detect (lD)
output to alert the protocol layer circuit when the incoming data is phase-locked to the VCO frequency. The lD
output is normally HIGH on powerup. In the event of
loss of lock, the lock detect (lD) flag changes to a lOW
state and stays lOW for about 50 IJS. It then cycles
HIGH and LOW approximately every 50 IJS until the
Clock and Data Recover circuit is phase-locked to the
incoming data. In the locked state, lD remains HIGH.
The RCC700 also incorporates a PECl to CMOS
converter to translate the PECL.o.utput signal from an

optical receiver module SDIN/SDIN to a CMOS output
signal. This allows for direct interfacing with the CMOS
protocol layer circuit. SDIN is active high. Therefore,
SDOUT will be at a CMOS level high when an optical
Signal is present at the input of the fiber optics receiver
module.

loopback Test Mode
The RCC700 features an intemal differentialloopback
for ·on-board" diagnostic of the device. WhenJoop
select (lSEl) is high, the receiver accepts the output
data from the transmitter se.ction (DOUT/DOUT). When
lSEl is low, i.e., tied to GND, the receiver accepts the
incoming input data (DIN/DIN).

Use of Table 1 for Encoding/Decoding
The following information describes how Table 1 can be
used for generating valid transmission characters
(encoding) and checking the validity of received
transmission characters (decoding).
The transmission character s labelled "abckefghj." The
transmission order is a,b,c, ...j in that order. HGFEDCBA
corresponds to the data inputs 017... 010 in that order. In
the table, each valid data byte and special code byte
has two columns representing two transmission characters. The two columns correspond to the current value of
the running disparity (CURRENT RD- or CURRENT
RD+). Running disparity is a binary parameter with
either the value + or -.
The transmitter calculates the new running disparity
based on the contents of the transmitted character.
Similarly, the receiver calculates the new running
disparity based on the contents of the received character.
The first 6 bits of the character, "abcdei,· form one subblock and "fghj" form another sub-block for computing
running disparity. Running disparity (CURRENT RD+ or
CURRENT RD-) at the beginning of the six-bit sub-block
is the running disparity at the end of the last transmission character. Running disparity at the beginning of the
four-bit sub-block is the running disparity at the end of
the six-bit sub-block. Running disparity at the end of the
transmission character is the running disparity at the
end of the four-bit sub-block.
Running disparity at the end of sub-block is positive, if it
contains more 1s than Os. It is also positive if it is 00111
for the six-bit sub-block and 0011 for the four-bit subblock. Otherwise, the running disparity is the same as at
the beginning of the sub-block.
CURRENT RD is used to select the transmission

2-380

Raytheon Semiconductor

For More Information, calil-BOO-722-7074.

RCC700
character for the data byte or special code.

disparity.

While decoding the received character, the column
corresponding to the current value of the receiver's
running disparity shall be searched for the received
transmission character. If the received transmission
character is found in the proper column, the transmission character is considered valid and the associated
data or special code byte decoded. Otherwise, the
character is considered invalid and EF pin is held HIGH
for that byte. Independent of the transmission
character's validity, the received transmission character
shall be used to calculate a new value of running

Oetection of a code violation (EF=HIGH), does not
necessarily indicate that the transmission character In
which the code violation was detected is in error. Code
violation may occur due to the prior error which altered
the running disparity of the bit stream, but it did not
result in a detectable error at the transmission character
in which it occurred. An example of an error scenario
where the error is flagged after it happens is shown in
the figure below.

RO Character

-

Transmitted character stream
Transmitted bit stream
Bit stream after error
Oecoded character stream

021.1
1010101001
1010101011
021.0

RD Character

+
+

010.2
010101 0101
010101 0101
010.2

RD Character

+
+

023.5
1110101010
1110101010

Error

RD
+
+
+
+

Block Diagram
DOL
ETX

VREF

TBC
DOUT
KIN
010-017
PIN
PE
LSEL
LO
RBC
RST
EF
KOUT
DOO-D07
POUT
BSYNC
SYNC EN

DOUT

DIN
DIN
SDIN
SDIN

GND

For More Information. call Hloo-722-7074.

Raytheon Semiconductor

2-381

RCC700
Table 1. 88/108 Encoding
OATA3
BYTE
NAME

00.0
01.0
02.0
03.0
04.0
05.0
06.0
07.0
08.0
09.0
010.0
011.0
012.0
013.0
014.0
015.0
016.0
017.0
018.0
019.0
020.0
021.0
022.0
023.0
024.0
025.0
026.0
027.0
028.0
029.0
030.0
031.0
00.1
01.1
02.1
03.1
04.1
05.1
OS.l

07.1
08.1
09.1
010.1
011.1
012.1
013.1
014.1
015.1

2-382

HGF

EOCBA1

abcdei

fghj2

abcdei

fghj2

OATA3
BYTE
NAME

000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111

100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111

0100
0100
0100
1011
0100
1011
1011
1011
0100
1011
1011
1011
1011
1011
1011
0100
0100
1011
1011
1011
1011
1011
1011
0100
0100
1011
1011
0100
1011
0100
0100
0100
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001

011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000

1011
1011
1011
0100
1011
0100
0100
0100
1011
0100
0100
0100
0100
0100
0100
1011
1011
0100
0100
0100
0100
0100
0100
1011
1011
0100
0100
1011
0100
1011
1011
1011
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001

016.1
017.1
018.1
019.1
020.1
021.1
022.1
023.1
024.1
025.1
026.1
027.1
028.1
029.1
030.1
031.1
00.2
01.2
02.2
03.2
04.2
05.2
06.2
07.2
08.2
09.2
010.2
011.2
012.2
013.2
014.2
015.2
016.2
017.2
018.2
019.2
020.2
021.2
022.2
023.2
024.2
025.2
026.2
027.2
028.2
029.2
030.2
031.3

BITS

CURRENTRO-

CURRENTRO+

BITS

CURRENT RD-

HGF

EOCBA1 abcdei

001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
001
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010
010

10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11.101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

Raytheon Semiconductor

011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011

CURRENT RO+

Ighj2

abcdei

fghj2

1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101

100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100

1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101

For More Information. call 1-800-722-7074.

RCC700
Table 1. 88/108 Encoding (continued)
pATA'

BITS

~YTE

NAME
00.3
01.3
02.3
03.3
04.3
05.3
06.3
07.3
08.3
09.3
010.3
011.3
012.3
013.3
014.3
015.3
016.3
017.3
018.3
019.3
020.3
021.3
022.3
023.3
024.3
025.3
026.3
027.3
028.3
029.3
030.3
031.3
00.4
01.4
02.4
03.4
04.4
05.4
06.5
07.5
08.5
09.5
010.4
011.4
012.4
013.4
014.4
1015.4

HGF

011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
011
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100

EOCBA1
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111

CURRENT RD-

CURRENT RO+

abcdai

fghj2

abcdai

fghj2

100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111

0011
0011
0011
1100
0011
1100
1100
1100
0011
1100
1100
1100
1100
1100
1100
0011
0011
1100
1100
1100
1100
1100
1100
0011
0011
1100
1100
0011
1100
0011
0011
0011
0010
0010
0010
1101
0010
1101
1101
1101
0010
1101
1101
1101
1101
1101
1101
0010

011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000

1100
1100
1100
0011
1100
0011
0011
0011
1100
0011
0011
0011
0011
0011
0011
1100
1100
0011
0011
0011
0011
0011
0011
1100
1100
0011
0011
1100
0011
1100
1100
1100
1101
1101
1101
0010
1101
0010
0010
0010
1101
0010
0010
0010
0010
0010
0010
1101

For Mora Information, call 1-800·722·7074.

OATA'
BYTE
NAME
016.4
017.4
018.4
019.4
020.4
021.4
022.4
023.4
024.4
025.4
026.4
027.4
028.4
029.4
030.4
031.4
00.5
01.5
02.5
03.5
04.5
05.5
06.5
07.5
08.5
09.5
010.5
011.5
012.5
013.5
014.5
015.5
016.5
017.5
018.5
019.5
020.5
021.5
022.5
023.5
024.5
025.5
026.5
027.5
028.5
029.5
030.5
031.5

BITS
HGF

100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101
101

EOCBA1
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

Raytheon Semiconductor

CURRENT RD-

CURRENT RO+

abcdai

fghi 2

abcdai

fghi 2

011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011

0010
1101
1101
1101
1101
1101
1101
0010
0010
1101
1101
0010
1101
0010
0010
0010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010

100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100

1101
0010
0010
0010
0010
0010
0010
1101
1101
0010
0010
1101
0010
1101
1101
1101
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010

2·383

RCC700
Table 1. 88/108 Encoding (continued)
OATA3
BYTE

BITS

00.6
01.6
02.6
03.6
04.6
05.6
06.6
07.6
OS.6
09.6
010.6
011.6
012.6
013.6
014.6
015.6
016.6
017.6
018.6
019.6
020.6
021.6
022.6
023.6
024.6
025.6
026.6
027.6
02S.6
029.6
030.6
031.6

110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110

SPECIAL'
COOE
NAME
K2S.0
K2S.1
K2S.2
K2S.3
K2S.4
K2S.5
K2S.6
K2S.7
K23.7
K27.7
K29.7
K30.7
Notes:

CURRENT RO-

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

BITS

abcdei

fghj2

abcdei

fghj2

100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011

0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110

011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100

0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110

CURRENT RO-

HGF

EOCBA'

abcdei

fghi2

000
001
010

11100
11100
11100
11100
11100
11100
11100
11100
10111
11011
11101
11110

001111
001111
001111
001111
001111
001111
001111
001111
111010
110110
101110
011110

0100
1001
0101
0011
0010
1010
0110
1000
1000
1000
1000
1000

all
100
101
110
111
111
111
111
111

CURRENT RO+

OATA3
BYTE
NAME
00.7
01.7
02.7
03.7
04.7
05.7
06.7
07.7
OS.7
09.7
010.7
011.7
012.7
013.7
014.7
015.7
016.7
017.7
01S.7
019.7
020.7
021.7
022.7
023.7
024.7
025.7
026.7
027.7
02S.7
029.7
030.7
031.7

BITS
HGF
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111
111

EOCBA'
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

CURRENT ROabcdei
100111
011101
101101
110001
110101
101001
011001
111000
111001
100101
010101
110100
001101
101100
011100
010111
011011
100011
010011
110010
001011
101010
011010
111010
110011
100110
010110
110110
001110
101110
011110
101011

fQhj2
0001
0001
0001
1110
0001
1110
1110
1110
0001
1110
1110
1110
1110
1110
1110
0001
0001
0111
0111
1110
0111
1110
1110
0001
0001
1110
1110
0001
1110
0001
0001
0001

CURRENT RO+
abcdei
011000
100010
010010
110001
001010
101001
011001
000111
000110
100101
010101
110100
001101
101100
011100
101000
100100
100011
010011
110010
001011
101010
011010
000101
001100
100110
010110
001001
001110
010001
100001
010100

fQhj2
1110
1110
1110
0001
1110
0001
0001
0001
1110
0001
0001
1000
0001
1000
1000
1110
1110
0001
0001
0001
0001
0001
0001
1110
1110
0001
0001
1110
0001
1110
1110
1110

CURRENTRO+
abcdei

fghi2

110000
110000
110000
110000
110000
110000
110000
110000
000101
001001
010001
100001

1011
0110
1010
1100
1101
0101
1001
0111
0111
0111
0111
0111

1. "HGF EOC BA" corresponds to 017 ... 0 in that order
2. a is to be transmitted first, followed by
b, c, d ... .i in that order

2-384

3.

Kin~O

4.

Kin~1

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RCC700
TRANSMITTER TIMING
TBC

DINO ..7, KIN, PIN

""

I ...
1

/

1

I

tidh

-I'"

-I

X

>K

:x

DOUT, DOUT

tids

.... tf ....

'"

- 80%

- -l{-

20%

~tr~

~
~
...... .....

DOUT, DOUT

trj. tdj

RECEIVER TIMING

:x
.... .... - -l{-

DIN,I5iN

tfi

-

80%
20%

~ .~
tn

~
~
...... .....

DIN, DIN

tj

I'"
I ...
RBC

T
tL

~

1

Y
I ...

DOUTO .. 7, KOUT,POUT

For More Information, call 1-800-722-7074.

X
Raytheon Semiconductor

.. I
.. I

tH

tod

I

~

-I

X
2-385

RCC700
5
10
11
12
13
14
15
16
17
18
19
20
21
22

6

2

60

ST

Siemens
Fiber
Optic
Xcvr

RCC700
68 PIN PLCC Package

....-_ _........_ _ _ _ _ _ _...;8::..j V23806A7-C2

23
24

ST

7

25
26

Interconnection of RCC70D to a Fiber Optic Transceiver

2-386

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RCC521
RCC521
STS-3/STM-l Synchronizer and Framer
General Description

Features

The RCC521 STS-31STM-1 Synchronizer and Framer
provides all the frame recognition and synchronization
functions required of a SONET/SOH line interface at the
155.52 Mbls data rate. On-chip phase-locked loops
facilitate clock generation and clock and data recovery.
The chip provides frame recognition. byte alignment.
scramblingldescrambling. bit interleaved parity (BIP-8)
generation/checking. and alarm generation according to
the applicable CCITI and ANSI standards. The chip
also satisfies the requirements in Sellcore TR-NWT000253.

•

The high speed serial line signals are provided with
positive-shifted ECl (PECl) interfaces. operating off a
single +5V supply. to interface directly with standard
fiber-<>ptic modules.
The RCC521 is implemented using Raytheon's high
performance CMOS-O process.
In a typical SONET OC-3/S0H-1 link. the RCC521 will
interface with standard fiber optic modules on the line
side and with CMOS Circuitry on the terminal side. The
differential PECl VO on the RCC521 permits a direct
interface to standard fiber optic modules without recourse to interv,ening level translators. In most applications. the only high speed board traces will be two pairs
of short stubs carrying serial data differentially: one from
the transmit section of the RCC521 to the fiber optic
transmitter module. the other from the fiber optic receiver module to the receive section of the RCC521. A
list of SONET/SOH compliant fiber optic modules that
are compatible with the RCC521 are given in the
Application Information section.

For More Information. call 1-800-722-7074.

•
•
•
•
•
•
•
•
•
•
•
•
•
•

Transmits/Receives at the STS-31STM-1 serial data
rate of 155.52 Mbls
Single supply (+5V) operation
On-chip clock synthesis and clock and data recovery
PECl VO for direct interface to fiber-<>ptic modules
Oetects framing sequence in serial data from network
and provides deserialized byte data and 19.44 MHz
byte clock to terminal
Receives 19.44 MHz byte clock and byte data from
terminal and provides serial data to network
Transmit clock may be directly coupled in at 155.52
MHz or synthesized from external 19.44 MHz source
Receive Pll retains lock even in the absence of
transitions in 70 consecutive bit poSitions
Scramblingldescrambling and BIP-8 calculation!
checking with optional bypass mode
Generates lOS(loss of signal). OOF(out of frame).
lOF(loss of frame). and RFE(receive frame error)
alarms
Loopback capability at both network and terminal ends
Test mode allows chip to be tested using an abbreviated frame
1.0 W maximum power dissipation
Fabricated in Raytheon's High Performance CMOS
process
Conforms to ANSI T1.105-1991.CCITI G.70B and
Sellcore TR-NWT-000253

Applications
•
•
•
•

SONET STS-3 or SOH STM-1 line interface
OC-31S0H-1 Regenerators. Add/Orop Multiplexers
ATM using SONET transport
SONET/SOH Test Equipment

Raytheon Semiconductor

2-387

RCC521
Pin No. Signal Name
1
TBD5
2
TBD6
TBD7
3
4
DVDD3
TRFPN
5
TEST
6
7
TRBC
EPA
8
CFSEl
9
10
AREFO
11
AREFI
12
ARE
13
DVDD2
14
REFClK
15
SCKINT
16
SCKINC
17
DGND2
AGND2
18
19
TlF2
TlF1
20
21
AVDD2
22
CSSEl
23
PVDD2
24
SDOC
25
PGND
26
SOOT
27
PVDD1
28
PVDD3
29
SCKOC
SCKOT
30
31
PGND3
32
lLB
lDN
33
34
ENRCK
35
SD
DVDD1
36
37
SOC
38
SDT
39
DGND1
IGND
40
41
SDINC
42
IVDD

Type
mlnput
mlnput
mlnput
Digital Power
mOutput
mlnpul
mOutput
mlnput
mlnput
Analog Output
Analog Input
mlnput
Digital Power
mlnput
PECl Input
PECl Input
Digital Ground
Analog Ground
Analog Current OIP
Analog Current OIP
Analog Power
mlnput
Digital Power
PEClOutput
PEClGround
PEClOutput
PECl Power
PECl Power
PEClOutput
PEClOutput
PEClGround
mlnput
mOutput
TIl Input
mOutput
Digital Power
PECl Input
PECl Input
Digital Ground
PEClGround
PECl Input
PECl Power

Pin No. Signal Name
SDINT
43
44
IGND
45
AVDD1
RlF1
46
47
RlF2
AGND1
48
OOFN
49
DVDD3
50
RFE
51
OOF
52
lOF
53
54
LOS
FFRM
55
DGND3
56
57
BIPERR
TlB
58
FM
59
DVDD3
60
RBDO
61
RBD1
62
RBD2
63
RBD3
64
DGND3
65
RBCLK
66
DGND3
67
RBD4
68
RBD5
69
RBD6
70
71
RBD7
72
DVDD3
73
ENSCP
74
RESETN
TFPN
75
DVDD3
76
77
TBDO
78
TBD1
TBD2
79
TBD3
80
81
DGND3
82
TBClK
DGND3
83
84
TBD4

Type
PECl Input
PEClGround
Analog Power
Analog Curent OIP
Analog Current OIP
Analog Ground
mlnput
Digital Power
mOutput
mOutput
mOutput
mOutput
mlnput
Digital Ground
mOutput
TIl Input
mOutput
Digital Power
mOutput
mOutput
mOutput
mOutput
Digital Ground
TIl Output
Digital Ground
TIl Output
TIl Output
TIl Output
TIl Output
Digital Power
TIl Input
TIl Input
TIl Input
Digital Power
TIl Input
TIl Input
TIl Input
TIl Input
Digital Ground
TIl Intput
Digital Ground
TIl Input

Ordering Information
Part Number

Package

Operating
Temperature

Range
RCC521XX
RCC521YV

2-388

xx

O°C 10 70°C

YV

O°CIO 70°C

Raytheon Semiconductor

Package

Order Number

84 Pin PLCC

RCC521xx

84 Pin CLDCC

RCC521yy

For More Information, call 1-800-722-7074.

RCC521
Pinout

ARE
DVDD2
REFCLK
SCKINT
SCKINC
DGND2
AGND2
TLF2
TLFl
AVO 02
CSSEL
PVDD2
SDOC
PGND
SOOT
PVDD1
PVDD3
SCKOC
SCKOT
PGND3
LLB

838281807978777675
74
73
72
71
70
69
68
67

13
14
15
16

66

65
64
63
62
61

60
59
58
57

32

RESETN
ENSCP
DVDD3
RBD7
RBDS
RBD5
RBD4
DGND3
RBCLK
DGND3
RBD3
RBD2
RBDl
RBDO
DVDD3

FM

56

TLB
BIPERR
DGND3

55

FFRM

54

LOS

~M~$D~~~~~~«~~Q~~OO~~~

65-6461

Absolute Maximum Ratings (1)
Supply voltage, AVDD,DVDD,IVDD,PVDD ................. 7V
Voltage at any input.. .................................................. 6V
Ambient operating temperature range ........ -40°Cto 85°C
Power dissipation ................................................... 1.2W
Storage temperature range ................... -65°C to +150°C
lead temperature range
(Soldering 10 seconds) .................................. 300°C

Notes:
1. "Absolute maximum ratings· are those beyond which
the safety of the device cannot be guaranteed. They
are not meant to imply that the device should be
operated at these limits. If the device is subjected to
the limits in the absolute maximum ratings for
extended periods, its reliability may be impaired. The
tables of Electrical Characteristics provide conditions
for actual device operation.

Recommended Operating Conditions
Symbol

Parameters

Min

TC

Case Oerating Temprature
Positive Supply Voltage
Power Dissipation

-40

Voo
Po

For More Information, call 1-800-722-7074.

4.75

Raytheon Semiconductor

Typ
5.0

Max
85
5.25
1.0

Units
V

W

2-389

RCC521
Network (lIne) Side

Transmit byte
Ref. clock
Alarms
Control
Rece ive byteclock and framing
Receive byte

--!~~!!!!!!!!1!4~!!~~P!!!!!:!!!!.

Transmit serial

1»11---+ bit stream

::I!IIIIIIIIIIIIII,II

Receive serial
"'11+-_ clock-embedded
bit stream

...!-IIZb::~;:;;Z;i2;~~;;EE::2.
Rgure 1. Simplified Block Diagram

Detailed Description
The simple block diagram of Figure 1 is shown in more
detail in Figure 3. The transmit section is expanded into a
Clock Generation block, a Transmit State Machine block
and a Parallel-to-Serial Conversion block. The receive
section consists of a Clock and Data Recovery block. a
Framer block and a Receive State Machine block.
The RCC521 can operate in two modes: a "Full Framing
mode" (FFRM=O) and a "Recognition Only mode"
(FFRM=1).ln the Full Framing mode, the RCC521
recognizes the STS-3/STM-1 framing sequence in the bit
stream received from the line and then anticipates and
tracks subsequent occurrences of the framing sequence in
conformance with the CCITI and ANSI standards. Most
applications will use the chip in this mode. In the Recognition Only mode, the RCC521 will look for the framing
sequence, output a Frame Mark (FM) pulse at every
occurrence of the framing sequence, and provide byte
alignment based on the detected framing. It will not

Terminal +-Side

--+Line
Side

execute the tracking algorithm required of the ANSI and
CCITI standards. This mode will only be used in when
the tracking is done by a separate upstream device.

Clock Generation
The Clock Generation block generates and distributes
the 155.52 MHz clock used for serial transmission. This
clock may be derived in one of two ways, determined by
Clock Frequency Select (CFSEL) : it may be synthesized from a reference at the byte frequency of 19.44
MHz using an on-chip phase-locked loop, or it may be
coupled in externally at 155.52 MHz. If CFSEL is 1, the
Clock Generation block expects a 19.44 MHz clock that
conforms to the ANSUCCITI standards to be presented
at the Reference Clock (REFCLK) input pin. The on-chip
PLL will synthesize the transmit clock using this reference. If CFSEL is 0, the Clock Generation block expects
to receive an ANSI/CCITI compliant 155.52 MHz clock
at the SCKINT (Serial Clock In True) and SCKINC
(Serial Clock In Complement) pins. In this case, the on-

line+-Side

--+ Terminal
Side

FOTM • Abe, Optic Transmltte, Module
FORM· Abe, Optic Receiver Mcdule

Figure 2. The RCC521 in a Typical Link
2-390

Raytheon Semiconductor

For More Information, call 1-800·722·7074.

RCC521
Z

II.

8
FM
RFE
OOF LOF LOS
BIPERR
RBOQ-7
RBCLK

1
RECEIVE
STATE
MACHINE

DATA

r-~--.~~--~-L1.
1-

__________~SO~T~
SOC

FRAMER

ell<
FRAMING

<

!cc

TFPN

TRANSMIT
STATE
MACHINE

Figure 3. Detailed Block Diagram

chip Pll is bypassed and the external clock is buffered
and distributed within the device. SCKINT and SCKINC
are differential PECl (positive-shifted ECl) inputs.
The Clock Generation block also generates two timing
reference signals, TRBC and TRFPN, based on REFClK,
which may be used by the terminal to frame and clock out
the byte-wide data to the RCC521 from the transmit FIFO
in the terminal. TRFPN (Transmit Reference Frame Pulse
Negative) has width equal to one byte and occurs at the
frame rate of 8 kHz. TRBC (Transmit Reference Byte
Clock) is a symmetrical clock signal at 19.44 MHz.
The Clock Generation block also has an alternate reference circuit. The alternate reference may be used to
insert a secondary timing reference, or provide a stable
clock for start-up in the event the primary reference
cannot be relied upon. The alternate reference may be
generated in one of two ways: the first, by connecting the
output from a 19.44 MHz external crystal oscillator/clock
source to AREFI (Alternate Reference In), the second, by
connecting a 19.44 MHz fundamental mode crystal
between pins AREFI and AREFO (Alternate Reference
Out). If the Alternate Reference Enable (ARE) input pin is
asserted, the Clock Generation block synthesizes the
serial transmit clock from the alternate reference instead
For More Information, call 1-800-722-7074.

of synthesizing it from REFCLK or using SCKINT/
SCKINC. The ANSVCCITT standards require Network
Equipment (NEs) to provide a secondary clock source in
case the primary source becomes unsuitable. The
secondary clock source may be connected to AREFI
and switched in using ARE. It is unlikely that an alternate reference generated using the on~hip crystal
oscillator will be suitable as the secondary clock source
in NEs, unless each device is individually tuned, because the frequency cannot be guaranteed to be within
f20 ppm from device to device owing to variations in
semiconductor process and parasitic capacitance.
However, the crystal will have to be provided, to ensure
proper initialization, in Line, Loop and Through timing
applications where the principal clock is derived from the
SONET/SDH input to the device and a guaranteed
standby clock is unavailable. The crystal provides a
permanent, free-running, clock source that assures
proper start-up on Power Up and Reset. This is explained below in the description of the Clock and Data
Recovery block. Note, in all applications where the
transmit reference is not related to the received clock, a
crystal or an alternate external reference is not necessary for proper operation of the RCC521.

Raytheon Semiconductor

2-391

RCC521
More information on clock generation, which includes
Raytheon's solutions for clock synthesis from other
reference frequencies (1.544, 2.048 and 51.84 MHz), is
available in the Application Information section

Transmit State Machine
The Transmit State Machine provides the timing marks for
the scrambler and the B1 parity generation circuitry. It
receives the Transmit Byte Clock (TBClK), the Transmit
Frame Pulse Negative (TFPN) and the Transmit Byte
Data (TBDO-7) from the terminal. TBClK is the 19.44
MHz byte clock with which the data byte TBDO-7 is
clocked into the RCC521 for subsequent serialization and
transmission. TFPN provides the framing reference for the
transmit section of the RCC521; it should be a pulse
synchronous with the third P:2. byte of the framing sequence. The terminal may derive TBClK and TFPN from
TRBC and TRFPN, respectively.

Parallel to Serial Conversion
This block serializes the TBOO-7 data byte, scrambles it,
and transmits it at 155.52 Mbls using the serial transmit
clock from the Clock Generation block. Although the serial
transmit clock will be exactly eight times the frequency of
TBClK, thereby obviating the need for an on-chip FIFO,
the phase relationship between the two clock signals will
be arbitrary. This can lead to setup and hold problems
when the data byte is loaded into the Parallel to Serial
Conversion block for serialization. A phase alignment
circuit is used to establish adequate phase separation
between TBClK and the internal load clock which loads
the data byte into the Parallel to Serial Conversion block.
Once the phase relationship is established, the circuit will
operate properly even if the active edge of TBClK shifts
is ns relative to its initial reference position. If the Enable
Phase Adjustment (EPA) pin is logic "1", the phase
alignment circuit will re-establish the load clock if the
active edge of TBClK shifts outside the permitted window. If EPA is "0", the intemalload clock, once established, remains fixed until a Reset is applied, no matter
what TBClK does subsequently.
Note, if EPA="1", clock wander will not cause phase
realignment because TBCLK and the internal bit clock
track the reference clock. A phase realignment will be
necessary only if there is extreme variation in the propagation delay of TRBC through the terminal electronics to
TBClK, or if protection switching is activated. The
operation of the phase alignment circuit is discussed fully
in the Application Information section.
The Serial Data Output to the line side is differential
(SOOT and SDOC). The output has PECl voltage levels
allowing the RCC521 to drive standard opto-electronic
2-392

transmitters directly.
The Enable Scrambling and Parity (ENSCP) control pin
determines whether the data bytes should be scrambled
and the B1 parity byte calculated and inserted, or
whether the data bytes should simply be relayed through
without scrambling or B1 insertion. If ENSCP="1", the
scrambler is enabled three octets after the trailing edge of
TFPN (I.e., after the third C1 byte). The Bit Interleaved
Parity (BIP-8) is also calculated, to give even parity, for
all octets in the current frame after scrambling. When the
bytes of the next frame are clocked into the RCC521
from the terminal, the first B1 byte in the new frame is
replaced by the BIP-8 value that was last calculated
(note, BIP-8 is inserted before scrambling but calculated
after scrambling). The scrambler is disabled after 2421
bytes have been transmitted. The TFPN pulse should,
therefore, be synchronous with the last P:2. byte of the
framing pattern. This ensures that the first nine bytes of
the frame (the framing pattern and the C1 bytes) are not
scrambled.
If ENSCP="O", TBDO-7 is simply serialized and transmitted without scrambling or parity insertion.
The behavior of the Transmit Section immediately after
Reset and Power Up are explained in detail in the
Application Information section.

Clock and Data Recovery
The Clock and Data Recovery block extracts the serial bit
clock from the input bit stream. This clock is the basis for
all timing in the Receive Section. The Clock and Data
Recovery block receives the high speed serial bit stream
from the opto-electronic receiver on differential PECl
inputs - Serial Data In True and Serial Data In Complement (SDINT & SOINC). It also receives the differential
inputs, Signal Detect True and Signal Detect Complement (SOT and SOC), from the opto-electronic receiver.
Signal Detect is a low speed PECl signal which is
asserted by the opto-electronic receiver when it receives
optical power above a specified threshold value.
The Clock and Data Recovery block consists of a lowjitter phase-locked loop which extracts the clock information and the data from the serial input on pins SDINT and
SDINC. This phase-locked loop, which will be referred to
as the Receive PlL, is separate from the phase-locked
loop in the Clock Generation block. The latter, which will
be referred to as the Transmit Pll, is well isolated from
the Receive Pll to minimize jitter from any crosscoupling between the two and to avoid false lock. Upon
power up or Reset, the Receive Pll aligns itself to the
Transmit Pll using a phase-frequency comparison

Raytheon Semiconductor

For More Information, call1.s00-722-7074.

RCC521
scheme which allows the Receive PLL to pull-in and
achieve lock even if the initial frequency discrepancy is
relatively large. After the Receive PLL is locked to the
transmit frequency, it will immediately re-align itself to the
incoming data stream if and when Signal Oetect is TRUE
and transitions are detected at the SOINT and SOINC
inputs. When the Receive PLL locks onto the serial input,
it employs a phase-only comparison scheme along with a
proprietary pulse discrimination technique to minimize
jitter generation and improve jitter tolerance. By initially
aligning the Receive PLL to the transmit frequency, the
Receive PLL is tuned very close to the input frequency.
This permits the Receive PLL to maintain a low bandwidth
for jitter performance, and yet, reliably lock onto the serial
input data.
The recovered 155.52 MHz Receive clock is output on
differential PECL outputs SCKOT and SCKOC (Serial
Clock Out True and Complement) where it may be
buffered out to other devices in Line, Loop, and Through
timing applications. Because the PECL buffers dissipate a
fair amount of power and inject some noise into the
substrate of the integrated circuit, the Enable Receive
Clock (ENRCK) control pin may be de-asserted to disable
the PECL buffers if the Serial Receive Clock output is not
needed. If the board designer prefers not to route high
speed clocks on the board, the Receive Byte Clock may
be connected externally to other devices and the serial
clock synthesized from the byte clock. In this case,
however, the jitter will be the composite jitter from two
phase-locked loops. The Receive PLL also generates a
Lock Detect Negative (LON) output which is asserted
when the Receive PLL is locked to the serial input.
Because the Receive PLL needs the Transmit PLL for
initialization, a circularity problem may arise in timing
applications where the serial transmit clock is derived
from the clock recovered on the same chip. On Power Up
or Rese~ the Receive PLL will look to the Transmit PLl to
provide initial frequency alignment. But, the Transmit PLL
cannot provide a stable clock because it derives its
reference from the clock recovered by the Receive PLl.
Even if the transmit reference is derived from a SONET!
SOH input received on a different chip, failure of that
source would again prevent initialization of the Receive
PLl. To overcome this problem, the Clock Source Select
(CSSEL) input is provided. If CSSEL is 0, the Serial
Transmit Clock is derived in the usual manner: it is
synthesized from REFCLK or derived from SCKINT!C as
determined by CFSEl. If CSSEL is 1, the Serial Transmit
Clock is synthesized from AREFI. If a SONET compliant
clock source is not provided to AREFI as the secondary
clock, a crystal will have to be provided. A clock source
For More Information, call 1-800-722-7074.

accurate to :1200 ppm is adequate for initialization. If
LON is connected to CSSEL, the transmitter will initialize
using the secondary reference and then switch to the
primary reference after the Receive PLl has successfully locked to the input bit stream. The Application
Information section provides details on how the RCC521
should be hooked up in various timing configurations.

Framer
The Framer block identifies the frame boundaries and
correctly demarcates the incoming serial bit stream into
octets. The Receive Section of the RCC521 will enter
the Seek Framing (SF) condition whenever RESETN or
Out Of Frame Negative (OOFN) is asserted. More
details on the operation of the RCC521 after RESETN
or OOFN is asserted is given below in the Reset and
Receive State Machine sections, respectively. Once in
the Seek Framing condition, if FFRM="1", the Framer
block will initiate the ANSI!CCID procedure to acquire
frame alignment. It will begin a serial search for the
STS-3 framing pattern: three A1 (hex FS) octets followed by three A2 (hex 28) octets. When the framing
pattern is recognized, the RCC521 sets the timing mark
for the byte boundary and begins counting octets. If the
framing pattern is accurately repeated exactly one frame
later, the RCC521 enters the In Frame (IF) condition.
Otherwise, the circuit resumes the search for two
framing patterns which are exactly one frame interval
apart. A new frame search may be initiated at an
arbitrary point within the incoming data stream by simply
asserting OOFN. As soon as the RCC521 enters the In
Frame condition, it outputs a Frame Mark (FM) pulse
and enables the byte aligned data onto RBOO-7. This is
explained further in the Receive State Machine section.
In the Recognition Only Mode (FFRM="O"), when the
Framer block is in the Seek Framing condition, it will
search for the framing pattern and determine the frame
and byte boundaries from the first framing pattern
detected. The circuit will not attempt to verify framing or
modify the established frame and byte boundaries
based on subsequent occurrences of the framing
pattern. A new search for the framing pattern must be
initiated by the terminal electronics by re-asserting
OOFN.
If ENSCP="1·, the BIP-8 is generated for each frame of the
received data before the data is descrambled. The value
obtained for one frame is compared for errors with the first
B1 byte of the descrambled data of the next frame. If
ENSCP="O", the received data is deserialized and passed
through to the terminal without descrambling.

Raytheon Semiconductor

2-393

RCC521
Receive State Machine

asserted.

The Receive State Machine provides the timing marks for
the descrambler, the parity checker, and the other circuits
in the Receive Section. It also generates the alarm Signals
according to the ANSI/CCITT standards and outputs the
status of the B1 parity check.

The Receive State Machine also generates the following
alarm signals: Receive Frame Error (RFE), Out Of Frame
(OOF), Loss Of Frame (LOF), and Loss Of Signal (LOS).
The RFE and LOS alarms are generated In both the Full
Frame and the Recognition Only modes. The OOF and
LOF alarms are generated only if FFRM="1".

The Receive State Machine divides down the recovered bit
clock to generate the Receive Byte Clock (RBCLK) and
synchronizes the Received Byte Data (RBDO-7) to RBCLK.
The terminal clocks in the deserialized data using RBCLK.
When the RCC521 enters the In Frame condition, the
Receive State Machine outputs a Frame Mark (FM) pulse.
This pulse is one byte wide and in phase with the third ft.2.
byte of the framing pattern relayed on RBD0-7.lf FFRM."1",
the first FM pulse is output with the third ft.2. byte In the
second of the two consecutive frames needed to take the
RCC521Into the In Frame condition. If FFRM="O", the FM
pulse is output with the third ft.2. byte of the very first frame
pattern recognized.
In the Full Framing Mode, once the RCC521 Is in the In
Frame condition, the Receive State Machine will output FM
pulses regularly, every 2430 bytes, until RESETN or
OOFN is asserted. The occurrence of a spurious framing
pattern within the frame will not cause re-framing or the
output of an FM pulse. If the RCC521 goes Out of Frame
(OOF) from an In Frame condition (OOF is described
below), the Receive State Machine retains the current
frame boundary until OOFN is asserted. It retains the
current byte boundary until asubsequent frame acquisition
is successful. Therefore, on detecting an Out of Frame
condition, the OOF alarm is set, but the FM pulses, RBDO7 and RBCLK continue based on the existing timing. As
soon as OOFN is asserted to initiate a new frame search,
the FM pulses stop until the new frame acquisition is
successful, whereupon they resume based on the newly
established frame boundary. RBDO-7 and RBCLK will
continue to be output based on the old byte boundaries
while the frame search is in progress, although the data
may well be invalid. After frame acquisition, RBDO-7 and
RBCLK will reflect the new byte boundaries when the first
FM pulse corresponding to the new frame boundary is
output Apulse stretching circuit is employed to ensure that
no runt pulse is output on RBCLK when it changes alignment as a result of reframing.
In the Recognition Only Mode, once the RCC521 is in the
In Frame condition, the Receive State Machine will output
an FM pulse every time a framing pattern is recognized.
The occurrence of framing patterns will not cause realignment of byte and frame boundaries unless OOFN is

2-394

RFE: Once the RCC521 is in the In Frame condition, the
Receive State Machine expects the Framer to identify the
six byte framing pattern beginning 2424 bytes after the last
Frame Mark. If the Framer does not recognize a correct
framing pattern, a one byte wide RFE pulse is generated.
RFE is output in phase with the FM pulse.
OOF: The Receive State Machine asserts the OOF alarm
output as long as the RCC521 is in the OOF condition. The
RCC521 will be in the OOF condition on power up, Reset,
and when OOFN is asserted. It Is also possible to enter the
OOF condition from the In Frame condition if the incoming
data is corrupt In the Full Frame mode, the RCC521 will
autonomously enter the OOF condition from the In Frame
condition if erroneous framing patterns are detected in four
consecutive frames. The RCC521 will re-enter the In
Frame condition when two successive error free framing
patterns are detected. In the Recognition Only mode, the
RCC521 cannot autonomously enter the OOF condition
from the In Frame condition. It can only do so If OOFN Is
explicitly asserted. In this case, the RCC521 enters the In
Frame condition as soon as the first framing pattern Is
encountered.
LOF: If the OOF condition persists for 3 ms (24 frames), the
LOF alarm Is asserted. The LOF is de-asserted when eight
consecutive error free framing patterns are received (i.e.,
the circuit has remained In Frame for 1 ms).
LOS: The Receive State Machine asserts the LOS alarm
if Signal Detect is de-asserted or if an uninterrupted series
of all ones or all zeros is received for an Interval exceeding
25±5j.1S. The LOS is de-asserted when two consecutive
error free framing patterns are detected.
If FFRM="1", the Receive State Machine will output the
results of the B1 parity check on the BIP Error (BIPERR)
output pin. The B1 byte that was generated for the prior
frame Is exclusive OR-ed with the B1 byte in the present
frame to yield an error byte which has a logic 1 at every bit
position that is in error. The error byte is clocked out in bytewide pulses in phase with RBD0-7. The first pulse will be
In phase with the B1 byte on RBDO-7.

Loopback
The RCC521 has loopback capability at both the terminal

Raytheon Semiconductor

For More Information, caD 1-800-722-7074.

RCC521
and the network ends. If Terminal loopback (TlB) is
asserted, TBDO-7 is serialized as usual. However, the
Clock and Data Recovery block will internally select the
serial transmit data instead of the serial receive data on
SDINT and SDINC. Consequently, RBDO-7 will output a
delayed replication of TBDO-7. If Une loopback (llB) is
asserted, the serial input data on SDINT and SDINC is
deserialized and presented to RBDO-7. The data is also
multiplexed internally, along with the receive clock, into the
Transmit State Machine. The Signal on SOOT and SDOC
will therefore be a delayed replication of SDINT and
SDINC.

positive supply reaches 4V(±O.5V) and then released. This
assures glitch free operation on power up. A Reset is
issued internally when the positive supply reaches the
release voltage. The ensuing operation is identical to that
described above in the Reset section.

Test Mode
The Test Mode is used to factory-test the chip expeditiously. If TEST is asserted, the RCC521 operates with a
short frame of 16 bytes. The first six bytes constitute the
framing pattern. The first nine bytes are not scrambled. The
13th byte is treated as the B1 byte. The remaining six bytes
may be packed with arbitrary data. In the Test mode, the
serial transmit clock is output on SCKOT/SCKOC instead
of the recovered clock.

Reset
A general reset is performed by asserting RESETN (Reset
Negative) for at least two byte periods. The RCC521 will
automatically perform a Reset on power up. On Reset, the
Transmit Pll and the Receive Pll will enter the out of lock
condition and begin a new acquisition cycle. The byte
counter and the scrambler in the Transmit Section will reset
themselves and await TBClK and the next TFPN pulse.
Once the Transmit Pll has achieved lock, TRBC and
TRFPN will be issued. The serial output will be all zeroes
until transitions are present on TBClK. The first negative
going transition on TBClK will trigger the phase alignment
circuit and establish the position of the internal load clock
which loads the parallel to serial converter. If ENSCP="O",
valid data is presented to the serial output with the very first
byte. If ENSCP="1", valid data is presented at the serial
output from the beginning of the next frame ( the B1 byte
in the very first frame will be incorrect).
On Reset, The Receive Section will enter the Out Of Frame
condition and follow the standard procedure to go In
Frame. All preset alarms will be cleared. As soon as the
Receive Pll commences the lock-in procedure to acquire
the serial receive input, a timer is set. An OOF condition is
declared when this timer expires if framing is not achieved
prior to expiry. New alarms will be generated depending on
how long the OOF condition persists.

Power Up
On power up, all CMOS outputs are held low until the
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

2-395

RCC521
Pin Definitions
Power and Ground
Power and ground feeds to the various functional blocks on the chip are kept separate to prevent switching noise
from one block from affecting another. Many of the functional blocks have distinct power and ground pins which, at a
minimum, have to be interconnected on the power and ground planes, respectively, on the printed circuit board. The
Application Information section has guidelines on how optimal power distribution and supply decoupling should be
done.
Symbol Pin Signal Name I Function
AVDD1
AGND1
DVDD1
DGND1
IVDD
IGND

AVDD2
AGND2
DVDD2
DGND2
PVDD1
PVDD2
PVDD3
PGND
PGND3
DVDD3

DGND3

45
48
36
39
42

Analog VDD and GND for the Clock and Data Recovery block. For optimal supply decoupling, an RF
quality 0.Q1 j.lF capaCitor should be connected between the pins as close as possible to the pins.
Digital VDD and GND for the Clock and Data Recovery block. For optimal supply decoupling, an RF
quality 0.Q1 j.lF capaCitor should be connected between the pins as close as possible to the pins.
VDD and GND for the PECl Inputs. For optimal supply decoupling, an RF quality 0.01 j.lF capacitor
40,44 should be connected between the pins as close as possible to the pins. Good isolation from supply
noise should be provided on the printed circuit board. Otherwise, the jitter tolerance of the Clock and
Data Recovery block will be impaired.
21
Analog VDD and GND for the Clock Generation block. For optimal supply decoupling, an RF quality
18 0.01 j.lF capacitor should be connected between the pins as close as possible to the pins.
13 Digital VDD and GND for the Clock Generation block. For optimal supply decoupling, an RF quality
17 0.01 j.lF capacitor should be connected between the pins as close as possible to the pins.
27 VDD and GND for the PECl Outputs. For optimal supply decoupling, an RF quality 0.01 j.lF capacitor
23 should be connected between PVDD1 and PGND as close as possible to the pins. Another should be
28 connected, likewise, between PVDD2 and PGND. PVDD3 should be decoupled to PGND3.
25
31
4,50 VDD for the Digital logic. If there is no VDD plane, each pin should be decoupled to the ground plane
60,72 on the printed circuit board using RF quality 0.01 J.lF capacitors.
76
56,65 Ground for the Digital logic. These pins should be connected to the ground plane of the printed circuit
67,81 board.
83

line (Network) Side I/O
Symbol

Pin

Signal Name I Function

SDINT
SDINC
SDT
SDC

43
41
38
37

Serial Data In True and Complement. These differential PECl inputs receive the serial bit stream at
155.52 Mbls from the line side.
Signal Detect True and Complement. This low speed differential Signal is received from the fiber optic
receiver module. If the Signal is TRUE, it indicates optical power is received by the module. If the signal
is FALSE, the Clock and Data Recovery unit will not attempt to extract the timing information from the
input bit stream. It will, instead, synchronize its voltage controlled oscillator (VCO) to the serial transmit
frequency. If 'Signal Detecr is issued as a single-ended output by the fiber optic module, this output
should be connected to SDT and the appropriate threshold should be provided to SDC (see Application
Information). Note, if the user does not wish to engage the Signal Detect function, the RCC521 will
operate properly if SDT and SDC are hardwired to a TRUE state. However, the standard implementation, which employs the Signal Detect, is more robust in that it offers greater immunity to false lock.

SDOT
SDOC

26
24

2-396

Serial Data Out True and Complement. These differential PECL outputs transmit the serial bit stream
at 155.52 Mb/s to the fiber optic transmitter module.

Raytheon Semiconductor

For More Information. caJI1..s00-722-7074.

RCC521
Pin Definitions (continued)
Line (Network) Side I/O (continued)
Symbol

Pin

Signal Name I Function

SCKOT
SCKOC

30
29

Serial Clock Out True and Complement. In normal operation, these differential PECL outputs provide
the serial receive clock recovered from SOINT and SDINC. In the TEST mode, these outputs provide
the serial transmit clock corresponding to SOOT and SOOC. SCKOT and SCKOC should be disabled
by deasserting ENRCK if the serial clock is not required for off-chip timing.

Terminal Side I/O
Symbol

Pin

Signal Name I Function

RBDO
RBD1
RBD2
RB03
RBD4
RBD5
RBD6
RBD7
RBCLK

61

Receive Byte Data 0-7. The deserialized data from the line is output to the terminal on this bus. RBD7
is the MSB. It is received first.

62

63
64
68
69
70
71

66

FM

59

TBDO
TBD1
TBD2
TBD3
TBD4
TBD5
TBD6
TBD7
TBCLK

77
78
79
80
84
1
2
3
82

TFPN

75

Receive Byte Clock. This is a 19.44 MHz clock Signal corresponding to RBOO-7. It is used by the
terminal electronics to clock in RBDO-7. RBDO-7 is clocked in by the falling edge of RBCLK.
Frame Mark. This is a byte-wide pulse output at the frame frequency (8 KHz) of the received signal.
The pulse is active high. It lasts for the duration of the third A2 byte of the framing pattem transmitted
on RBOO-7.
TransmH Byte Data 0-7.The octets meant for serialization are input to the RCC521 from the terminal
on this bus.Transmission is big-endian, i.e., TB07, which is the MSB, is transmitted first.

Transmit Byte Clock. This is a 19.44 MHz clock signal corresponding to TBOO-7. The RCC521 clocks
in TBDO-7 on the falling edge of TBCLK.
TransmH Frame Pulse Negative. This active low signal should be one byte wide and repeat at the
transmit frame frequency. The RCC521 derives framing information from this signal. TFPN must be
in phase with the third A2 byte of the framing pattern on TBDO-7.

Timing
Symbol
REFCLK

Pin
14

SCKINT
SCKINC

15
16

Signal Name I Function
Reference Clock. A reference clock at 19.44 MHz should be provided on this pin. This clock should
conform to the ANSI/CCITT requirements for clocks because the Clock Generation block uses
REFCLK to synthesize the serial transmit clock. In external timing applications, REFCLK will normally
be a derivative of the BITS clock. In Line, Loop and Through timing applications, where the transmit
clock must be extracted from the received bit stream, RBCLK may be connected externally to REFCLK.
Serial Clock In True and Complement. If a compliant serial clock is available and the on-chip
synthesizer is not desired, the 155.52 MHz transmit clock can be directly provided through these PECL
inputs. The CFSEL control input should specify whether REFCLK or SCKINT/SCKINC is used.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

2-397

RCC521
Pin Definitions (continued)
TIming (contlnyecf)
Symbol

Pin Signal Name I Function

TRBC

7

Transmit Reference Byte Clock. The serial transmit clock is divided down to provide a clock output

at 19.44 MHz. The terminal may derive TBCLK from this output
TRFPN

5

AREFI
AREFO

11
10

Transmit Reference Frame Pulse Negative. An Inverted pulse one byte wide Is output at the frame
frequency by dividing down the serial transmit clock. This signal may be used by the terminal to derive
TFPN.
Alternate Reference In and Out. In External timing applications, an optional 19.44 MHz timing
reference that is an alternate to REFCLK may be applied to AREFI and switched In using the ARE
control pin. In timing applications where REFCLK or SCKINT/SCKINC Is derived from the received data
stream, an alternate reference is compulsory because the primary reference will be invalid until the
Receive PLL establishes lock. If a reliable source is unavailable for AREFI, afundamental mode crystal
that will provide a 19.44 MHz ±200ppm frequency must be connected between AREFI and AREFO and
the CSSEL control input must be set to a logic "1". The LON control pin may be used to determine if
the Receive PLL has established lock and then switch over to the primary reference.

Alarm SIgnals
Symbol
OOFN

RFE

Pin Signal Name I Function
49 Out Of Frame Negative. This positive edge triggered signal is asserted by holding OOFN low for at
least two byte periods (105 ns). The RCC521 acts on the riSing edge of OOFN after It has been low
for the requisite two byte periods. OOFN resels the Receive Section with the exception of the Clock
and Data Recovery block. When OOFN is asserted, the RCC521 initiates a new frame search. Until
the RCC521 gets back in frame, RBDO-7 and RBCLK will continue to be output based on the previous
demarcation of byte boundaries.
51 Receive Frame Error. this is aone byte wide pulse output in phase with the third A2 byte of the framing
pattem on RBD0-7. RFE is output only if a framing pattern is not detected where one is expected.

OOF

52

LOF

53

LOS

54

BIPERR

57

2-398

Out Of Frame. This active high output is asserted for as long as the RCC521 is in the Out Of Frame
condition. The RCC521 will enter the OOF condition from the In Frame condition if four consecutive
frames have framing pattern errors. To re-enter the In Frame condition, two consecutive error-free
framing patterns must be detected. OOF is disabled if FFRM="O".
Loss Of Frame. This active high output is asserted if OOF is high for 24 frames (3 rns). OOF Is deasserted when eight consecutive error free framing patterns are detected. LOF is disabled if FFRM="O".
Loss Of Signal. This active high output is asserted if the serial input bit stream is stuck high or stuck
low for more than 25;1;5 J,LS. It is de-asserted when two consecutive error-free framing patterns are
detected.
Bit Interleaved Parity Error. If ENSCP="1", the result of the B1 parity check is output on this pin as
a series of byte wide pulses in phase with RBCLK. The first BIPERR pulse denotes an error in the Bit7 positon. This pulse is output synchronously with the B1 byte on RBDO-7. BIPERR pulses that occur
In any of the subsequent seven byte intervals indicate errors In the corresponding B1 bit positions.

Raytheon Semiconductor

For More Information. caD 1-800·722-7074.

RCC521
Pin Definitions (continued)
Control Signals
Symbol

Pin

Signal Name I Function

FFRM

55

TLB

58

LLB

32

ENSCP

73

ARE

12

TEST

6

RESETN

74

ENRCK

34

LON

33

Full Framing Mode. This input is active high. When FFRM is "1", the Framer block executes the full
ANSI/CCITI procedure to establish framing and enter the In Frame condition. If FFRM="O", the part
operates in the Recognition Only mode. In the latter case, the RCC521 establishes byte boundaries
based on the first framing pattern recognized. The part then enters the In Frame condition and ceases
verification of frame boundaries until OOFN is asserted.
Terminal Loopback. This input is active high. When TLB is asserted, the serial transmit data is passed
through to SOOT and SOOC and also looped back internally into the Clock and Oata Recovery block.
The result is identical to what would be achieved if SOOT and SOOC were tied externally to SOINT and
SOINC, respectively.
Line Loopback. This input is active high. When LLB is asserted, the received byte data is passed
through to RBOO-7 and also looped back internally into the Transmit Section. The recovered clock is
passed through and TBCLK is ignored. The result is identical to that achieved if RBOO-7 were
connected externally to TBOO-7 and the receive timing substituted for the transmit timing.
Enable Scrambling and ParHy . This input is active high. If ENSCP="1", the scramblers and the parity
circuits are enabled in the Transmit and the Receive sections. On the transmit side, the BIP-8 byte that
was generated for the previous frame is substituted into the B1 position of the present frame. The data
is scrambled and then transmitted serially. On the receive side, the serial input data is descrambled
and the B1 byte is checked against the BIP-8 byte generated from the previous frame. Any errors are
reported on BIPERR. If ENSCP="O", the transmit data is serialized and passed through without
scrambling and B1 substitution. The receive data is simply deserialized without descrambling. The BIP8 cirCUitry is disabled and no errors are reported on BIPERR.
Alternate Reference Enable. This input IS active high. If ARE="1", the Clock Generation block will
internally switch its reference from REFCLK to AREFI.
Test Mode. This input is active high. If the TEST input is held high for at least one byte interval, the
RCC521 will enter the TEST mode. The Test mode is incorporated in the RCC521 to ease chip test
in the factory. In the Test mode, the part operates assuming an implied frame length of 16 bytes. As
in normal operation, the first six bytes comprise the framing pattern and the first nine bytes are not
scrambled. However, the thirteenth byte is the implied B1 byte. The other six bytes may carry random
data. In the Test mode, the serial transmit clock implied by SOOT/SOOC is output on SCKOT/SCKOC
instead of the clock recovered from SOINT/SOINC.
Reset Negative. This input is positive edge triggered. RESETN must be held low for at least two byte
intervals to be recognized. After this interval, the RCC521 executes a general reset on the ensuing
rising edge of RESETN. On Reset, the Transmit PLL and the Receive PLL re-synchronize themselves.
The Framer block enters the Seek Framing condition after giving the PLLs enough time to lock. All
alarms are cleared. The transmit reference clocks are generated after the transmit PLL achieves lock.
The transmit byte counter is reset and transmission resumes based on the first trailing edge of TBCLK
received after the Transmit PLL has locked.
Enable Receive Clock. This is an active high output. When it is asserted, the serial receive clock is
output on SCKOT/SCKOC in normal operation, and the serial transmit clock is output on the same pins
in the Test mode. In normal operation, if the recovered serial clock is not needed for off-chip timing,
ENRCK should remain deasserted to conserve power and reduce switching noise.
lock Detect Negative. This is an active low output. LON goes low when the Receive PLL locks onto
the input bit stream on SOINT and SOINC. LON is not asserted when the Receive PLL locks onto the
transmit frequency during initial frequency alignment.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

2-399

RCC521
Pin Definitions (continued)
Control Signals (continued)
Symbol

Pin

Signal Name I Function

EPA

8

CFSEL

9

CSSEL

22

Enable Phase Alignment. This input is active high. The phase alignment circuit maintains the
necessary interval between TBCLK and the internal clock which loads the parallel to serial converter
in the Transmit section. If EPA=H1", the phase alignment circuit will re-align the internal load clock
should TSCLK drift by more than ±6ns with respect to the initial reference timing. If EPA="O", the phase
alignment is established just once.
Clock Frequency Select. This input specifies which of two primary references are used to generate
the serial transmit clock. If CFSEL="1 H,the Clock Generation block expects a 19.44 MHz reference on
REFCLK. If CFSEL="O", the Clock Generation block expects a 155.52 MHz differential clock on
SCKINT and SCKINC.
Clock Source Select. If CSSEL="O·, the serial transmit clock is derived from the primary reference:
either REFCLK or SCKINT/SCKINC. If CSSEl="1", the serial transmit clock is synthesized from
AREFI.

~

Symbol

Pin

Signal Name I Function

SO

35

TLF1
TLF2

20
19

RLF1
RLF2

46

Signal Detect. This is an active high output. The signal received on the differential PECL inputs SOT
and SOC is translated to TTL levels and output on this pin.
TransmH Loop Filter 1 and 2. The passive components that comprise the loop filter for the Transmit
PLL are connected to these pins. See the Application Information section for component values and
their effect on loop performance.
Receive Loop FIHer 1 and 2. The passive components that comprise the loop filter for the Receive
PLL are connected to these pins. See the Application Information section for component values and
their effect on loop performance.

2-400

47

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RCC521
DC Electrical Characteristics
Symbol

Parameters

VII
VII..
III..
C1

TTL Inputs
High level Input voltage
Low level Input voltage
Input leakage current
Input capacitance
Positive·shifted ECl Inputs
High level Input voltage
low level Input voltage
Input leakage current
Input capacitance

VOlt
VOl.
IOL
10it

TTL Outputs
High level output voltage
low level output voltage
High level output current
Low level output current

VOlt
VOL
VOD
IOL
10it

Positive-shifted ECl Outputs
High level output voltage
Low level output voltage
Differential output voltage
High level output current
Low level output current

VII
VII..
III..
C1

For More Information, call 1-800-722·7074.

Test Conditions

Min

DVDD=4.75V
DVDD=5.25V
DVDD=5.25V

2.0

IVDD=5.0V
IVDD=5.0V
IVDD=5.25V

Max

0.8
10
3.0
4.0
3.3
1.0
8

3.7
3.0

DVDD=4. 75V,10It=·2mA
DVDD=5.25V,loL=4mA

4.25

PVDD=5.0V,RD,FF=50n
PVDD=5.0V ,RD,~50n
PVoo=5.0V,RoIFF"50n
PVDD=5.0V,RDIFF"50n
PVoD=5.0V,Ro,FF=50n

3.7
2.7
0.6
13
13

Raytheon Semiconductor

Typ

4.1
3.3
0.8
16
16

Units
V
V
~

pF
V
V
~

pF

0.4
4.0
-2.0

V
V
mA
mA

4.4
3.8
1.0
19
19

V
V
V
mA
mA

2-401

RCC521
AC Electrical Characteristics
Max

UnHs

8.0
8.0

ns
ns

PVDD=5.0V,RDwrSOQ,CL=20pF
PVDD=5.0V,RDwr50Q,CL=20pF

1.1
1.1

ns
ns

f=155.52MHz,(215·1) PRBS!3I
RDI~SOQ,CL=20pF
REFClK=19.44 MHzl4l

45

ps

22

ps

0.1

dB
dB/dec

0.1

dB
dB/dec

Symbol

Parameters

Test CondHlons

Min

t RISE

moutputs
Rise time
Fall time

OVoo=5.0V,CL=15pF
OVDD=5.0V,CL=15pF

1.0
1.0

PosUive-shifted ECl Outputs(2)
Rise time
Fall time

tFALL
tRISE
tFALL
JCEN

JTRANSF

JTOI.

Clock Jitter (r.m.s.)
Jitter Generation:
Total jitter In the differential
output (SOOT-500C)
Random jHter In TRBC
JHter Transfer:
Serial Receive Input to Serial
Receive Clock (SOINT·
SOINC) to(SCKOT·SCKOC)
Jitter Gain
JHter Gain Rolloff
REFClKlAREFI to TRBC
JHterGaln
JHter Gain Rolloff
JHter Tolerance:
Serial Receive Input (SOINTSOINC) amplitude penalty

Typ

(Fig. 4), Serial Up Is freq. modu·
lated with sinusoid that genera·
tes jitter to the mask In Flg.5
10Hzs;f~30kHz

f>130kHz

·20

10Hz s; f S;80 kHz
f> 80 kHz

·20

Input jHter conforms to the
mask In Figure 5. BER=11t1O

dB

Notes:
2. The PECl outputs are current mode outputs with a nominal current drive of 16 rnA. The outputs are designed to give a nominal
swing of 800 mV when used in conjunction with a differential
load of 50n.
3. Jitter number includes data dependent and random jitter. Data
dependent jitter is measured by inserting a 215..1 pseudo-random bit sequence in byte-organized fashion at T8D0-7 with the
chip in the bypass mode.
4. Random jitter on TR8C is measured by applying a low·jitter «10
ps rms) square wave to REFCLK, measuring the random jitter in
TR8C on a high speed digital sampling oscilloscope, and subtracting out the trigger jitter in rms fashion.

2-402

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RCC521
Jitter Transfer Characteristic from the Serial Receive Input to
the Serial Receive Clock
dB

0.1

Jitter Gain

Acceptable Range

Hz

130K
Frequency

65-6197M

Figure 4

Jitter Tolerance Mask for the Serial Receive Input
UI
15

Slope = -20 dB/decade

UI- 6.43 ns
Sinusoidal 1.5
Input
Jitter
Amplitude
(p-p)
0.1

10

30

300 6.5K

65K

Frequency

Hz
65-6198

Figure 5

For More Information, call1-800-7~-7074.

Raytheon Semiconductor

2-403

RCC521
Timing Relationships
Symbol
T1
T~

T3

T4
T5
T6
T7

T8

T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T~

T21
T22
T23
T24
T25
T26
T27
T28
T29

2-404

Parameter Description
TBoo·7 setUD time to falllna edae of TBCLK
TBDO.7 hold tlma attar falllnll adaa of TBCLK
TFPN setuD time to falllna edae of TBCLK
TFPN holtl tlma Aftar fAlllnn AtlnA of TBCLK
TBCLK ~Iock narlod
TBCLK Dulsewldth hlah
TBCLK Dulsewldth low
RBoo·7 outDUt delay after the falllna edae of RBCLK
FM output delay after falllna edae of RBCLK
RBCLK clock Derlod
RBCLK Dulsewldth hlah
RBCLK
low
FM pulsewldth
Offset of rising edge of Serial Clock Out (SCKOT·SCKOC) from
~ntra of bit CAli of Sl!rlal Data Out (SDOT.SDOC\ In TIIM Modll
(SCKOT·SCKOCI nulse nerlod
(SCKOT·SCKOCI Dulsewldth low
(SCKOT.SCKOC\
hlah
Delay from failing edge of TBCLK to centre of bit cell of MSB of
byte OUtDut on (SOOT-BDOCI
Delay from failing edge of LSB on (SDINT·SDlNC) to failing
I byte
edae of RBCLK for the
TRFPN falllna edae outDut delay after rlslna edae of TRBC
TRFPN Dulsewldth
TRBCDerlod
TRBC nulsewldth hklh
TRBC Dulsewldth low
RESETN Dulsewldth
Delay from rlslna edae of RESETN to rlslna edae of yalld TRBC
Delay from first valid rising edge of TRBC to first valid failing
IIdae of TRFPN
Delay from rising edge of RESETN to leading edge of valid
(SCKOT·SCKOC) when serlallnDut Is Dresent
Delay from failing edge of RBCLK to leading edge of BIPERR
output bit

Raytheon Semiconductor

Min
5.0
5.0
5.0

Typ

Max

·20DDm
3.0

6.43
3.215

+~DDm

:to

3.~15

Units
os
ns
ns
5_0
n!l
·~O nnm 51.4403 I+~nnm
ns
18
ns
18
ns
10
ns
0
10
ns
0
·20 DDm 151.4403 '+20DDm ns
22
ns
22
ns
51.44
47
56
ns
ns
-0.5
0.5

40

ns
ns
ns
ns

40

ns

0
10
47
51.44
56
·20 ppm 51.4403 +20 ppm
22
22
105
500
10
0

0

ns
ns
ns
ns
ns
ns
us
ns

1.2

ms

10

ns

For More Information, caD 1-800-722-7074.

RCC521
T5

TBCLK

,

TBD~7 ?II

I~F1I
-------------~~r------t

I

A2

L-_ _.....

A2

01

L _ _- - '

,

I

TFPN

\

!

65-6196

Figure 6

T10

T12
RBCLK

,
,

I

I
I

:T8
RBDO-7

~

!~

A2

~,

A2

!~

A2

lTg,

I

T13

IE ~

f

FM

~,

C1

\
65-6195

Figure 7

Bit Cell

,~'~I
, ,
,
,
I

Serial Transmit Output
(SDOT-SDOC)

Serial Transmit Clock
(SCKOT-SCKOC)

I

,T14
,, ,,
:

TBDO-7

L:YIB#NJ IByte#N+l
,

~

-----..,iI--T-1-8--~)I'
TBCLK

I

f·r-----

T21

65-6202

Figure 10

T25

, 1 f~

If

RESETN

:

TRBC

!
I
I

Serial Receive Clock
(SCKOT - SCKOC)

T26)1

~T27 \,------,r
I

TRFPN

II

- - --

1 r
I

I

___________- J

I~

I

T28

~
Figure 11

2-406

I

Raytheon Semiconductor

65-6203M

For More Information, call 1-800-722-7074_

RCC521
RBCLK
I
I

I

I
I

RBDO-7

---IX

.L..~

BIPERR

I

r----T'~'r_----~
Byte

#2rOy:< B1 Byte
:129):

X'--_.....JX'--_.....JX

: :r---"""'\.
I
I

~

Bit OK
B1 Parity Bit 4
65-6200M

Figure 12

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

2-407

2-408

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

Section 3 - Standard Products

Section 3
Standard Products

Raytheon Semiconductor offers a comprehensive line of
standard products serving a wide variety of applications
in diverse commercial, industrial and military markets.
Applications that include video proceSSing, medical
imaging, data acquisition, instrumentation, guidance
control systems, radar and many others.

Standard Linear products have provided solutions for
designers since the early 1960s. Products such as
precision op amps, comparators, voltage references,
DACs and regulators are manufactured using the
company's own bipolar junction isolated process, and
can be screened to JAN Class B.

Addressing video signal synthesis and graphics
applications, to name a few, are Raytheon's AID and D/A
converters, ranging from 4-bits at 200 Msps up to 12-bits
at 50 Msps.

Raytheon's PROMs include standard and powerswitched versions in many different speeds and
packages and have high immunity to total dose radiation,
making these products especially suitable for military
applications.

Signal processing functions are performed by our
Transform and Vector Processing, Correlator, FixedPoint Arithmetic and Memory/Storage products.

Small signal transistors round out Raytheon's Standard
Products offering. Both sole source and industrystandard types are available, and support many existing
commercial and military applications.

Contents
AID Converters ............................................................................................................................................3-2
D/A Converters ........................................................................................................................................3-137
Transform Products .................................................................................................................................3-251
Vector Processing ...................................................................................................................................3-333
Correlators ..............................................................................................................................................3-353
Fixed-Point Arithmetic .............................................................................................................................3-387
Memory Storage ......................................................................................................................................3-429
Linear ......................................................................................................................................................3-441
PROMs ...................................................................................................................................................3-903
Small Signal Transistors ..........................................................................................................................3-925

Raytheon Semiconductor

3-1

I

Section 3 - Standard Products

AID Converters
,., TDC1020

10

TDC1049

0

'0'
....
in
""
c

0
;:

TDC1038

TMCll73

"TDC100l
v

8

TM Pll75

oTDC1047

6

..., TDC1046

4

" TDC1044

.2
0

1/1
CD

a:

2

2

5

10

20

50

100

Conversion Rate (Mega Samples per Second)
65-6227

Raytheon Semiconductor offers a line of high performance
NO converters that addresses applications requiring
conversion rates from less than 1 Msps to 40 Msps. We
pioneered the monolithic video NO converter in 1977, and
in 1989 received an Emmy Award for our contributions to
the field of video conversion. The current offerings are the
fourth generation products of Raytheon Semiconductor's
commitment to quality video conversion.

New to the family of video converters is the TMC22070
Genlocking Video Digitizer. This fully-integrated
acquisition system includes everything needed to convert
analog NTSC or PAL video into a composite digital video
signal. The digitizers generate a line-locked sampling
clock, adjust the gain and offset of the incoming video,
digitize it, and measure the phase and frequency of the
color burst for further processing.

For standard video bandwidth conversion, you can' beat
the TMCl175 8-bit 40 Msps CMOS AID, which is available
in a 24 lead SOIC package, and consumes less than 150
mW. For low voltage applications, the new TMCl173
operates at 10 Msps with a supply voltage of 2.7 to 3.3V
and only requires 90 mW.

The TDC1035 is an innovative new product that digitizes
the peak value of a pulse (as narrow as 12 ns) that
occurs any time during a user-defined "window". It is
ideal for high-energy physics experiments, electronic
warfare and general purpose instrumentation.

3-2

Raytheon Semiconductor

For More Information call 1-800-722-7074.

Section 3 - Standard Products

Conv.
Resolution Rate 1
Product
BHs
(Msps)
4
25
TOC1044
TOC104S
25
6
TOC1047
7
20
TOC1147
7
15

RMSIRMS
SNRI
(dB)
Package
89,N9
33
88
87
39
3S
87

TOC1035

8

TMC22071

8

15

TOC1038

8

20

45

TOC1048

8

20

45

TOC1058

8

20

45

TMC1173-10

8

10

45

-05
TMC1175-20

8
8

5
20

45
45

-30
-40

8
8

30
40

45

9

30

48

TDC1049

45

Grade2
C, V,SMD
C, V,SMD
C,V
C, V

87

C,V

R1

C

8S,NS,R3
E1
8S,NS
C3,E1
8S, NS, R3,
E1
M7,N2, R3

C,V

No pipeline delay. Well suited to subranging
converter applications.
Peak digitizer. Digitizes peak value of pulses as
narrow as 12 ns.
Genlocking digitizer with input MUX, clamp, sync
separator, clock generator, subcarrier Pll
low power version of TOC1 048.

C, V,SMD

Industry standard video AID.

C

New industry standard video AID. Single +5V
power supply. TDC1048 performance equivalent.
low power CMOS video AID with integral TracklHold.
+2.7V to +3.3V power supply.

M7, N2, R3
82, N2, C3,
M7,R3
M7,N2,R3
M7,N2,R3
E1
JO, J3, C1,
L1, G8, E1
J1,GO, E1

C
C,V

low power CMOS video AID with integral TracklHold.

C, V
C, V
C
C, V,SMD

Includes TOC331 0 D/A
ECl interface

C

TOC1020
10
20
C, V
55
Notes:
1. Guaranteed. See product specifications for test conditions.
2. A =High reliability, Tc. -5500 to 12500.
B =Industrial, Tc =-2500 to 8500
C =Commercial, TA =000 to 7000.
F =Extended Temperature Range, Tc • -5500 to 12500
V - MIL·STD-883 Compliant, Tc • -55·C to 12500.
SMD =Available per Standardized Military Drawing, Tc =-5500 to 12500.
3. A =High reliability, Tc =-20·C to 9500.

For More Information call 1-800-722-7074.

Notes

Monolithic video AID, TIL interface. ±2.V input range.

Raytheon Semiconductor

3-3

Section 3 - Standard Products

3-4

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI020
TDCI020
ffigh-Speed Monolithic AID Converter
10-Bit, 20 Msps

Description

Features

The TDC1020 is a 20 Msps (Megasample per second)
full-parallel (flash) analog-to-digital converter, capable of
converting a video signal into a stream of 1O-bit digital
words.

•
•
•
•

All outputs of the device are TIL compatible, and will
provide the conversion in unsigned magnitude, or two's
complement format, and either inverted or non inverted.
An output signal indicating overflow condition is also
provided for added flexibility. All digital inputs to the
device are TIL compatible.

Functional Block Diagram
"
"

"
"

'"

'"
'"

"
"
"

'"
'"
"
For More Information call 1-800-722-7074.

.

"

"

• m
•

Applications
•
•
•
•
•

Medical imaging systems
Video data conversion
Radar data conversion
High-speed data acquisition
Process control

1
--

~
,~~

."

~

~
'"

'.'

~

·..

~

·

'~~

---';--.
1024T010
ENCODER

===:;

REGISTER

OVF,iWF

=+,;:>

'"

~

fhk>:=~
"'

~,

."
"

~

·
·

,~

."
"

'"

."
."

10-bit resolution
20 Msps conversion rate
Overflow flag
Sample-and-hold circuit not required
digital interface
Selectable output format

~

·
.'

~

"--

f~~
,.,
OlFFERINTIAl
COMPARATORS

'---

(0124)

"

Raytheon Semiconductor

3-5

I

TDCI020
Functional Description

Reference

General Information

The bias voltages for the comparator array are provided
by use of a serial chain of 1024 equal-valued resistors
across which the reference voltage is applied. Seven
equally separated'mid-point adjustment taps are provided
to allow the user to optimize the integral linearity of the
device. In addition, there are sense leads on the top and
bottom of the resistor chain which allow the user to
minimize the offset and gain errors of the device. It is
recommended that the user drive RM2, RM4 and RM6
in order to obtain optimal device performance. One
method for driving the references is shown in the
Typical Interface Circuit. The reference top and
reference bottom sources must be able to source or sink
the reference current and since noise on these leads will
lead to inaccurate conversions, they should be bypassed
with a capacitor to AGNO. There are in addition 4 more
reference taps, the use of which is not required to obtain
0.1 % integral linearity. It is recommended that these pins
be left open Ino connectionl.

The TOC1020 is a flash analog-to-digital IAIDI converter
in which each of the 1024 comparators has one input
biased at one of the transition points of the transfer
function and all of the other comparator inputs are
connected to the analog input signal. The output of the
comparator array is sometimes referred to as a
"thermometer" code as all of comparators biased at
voltages more positive than the input voltage will be off
and the rest will be on. The thermometer code from the
comparator array is encoded into an ll-bit code 110 data
bits plus an overflow bitl. The format of the code that is
encoded is determined by the format controls NMINV
and NLiNV so that the data presented to the output
latches is in binary, two's complement or inverted data
format.

Power and Thermal Management
The TOC1020 operates from two supply voltages, + 5.0V
and - 5.2V. The bulk of the current drawn by the
positive supply is returned through the negative supply,
however, the positive supply should be referenced to
digital ground 10GNOl and the negative supply to analog
ground IAGNOI. All power and ground pins must be
connected. The maximum power is drawn at the lower
limit of the operating temperature range. When the
device is being operated at elevated temperatures, the
power dissipation drops, however, thermal management
will then be a consideration. The TOC1020 is rated for
operation in a 70°C ambient temperature in still air.
The power dissipation decreases with increasing
temperature. TRW specifies the absolute maximum lEE
and ICC specifications in the Electrical Characteristics
Table. The worst case conditions are VCC = 5.25V,
VEE = - 5.5V and the case temperature equal to DoC.
The case temperature of DoC is, however, a transient
condition since the device immediately warms up and
decreases its power dissipation, upon power up. For
typical steady state power dissipation as a function of
ambient temperature, please see Figure 7.
It is possible to relax the temperature requirements of
the device by providing adequate heat sinking.

3-6

Format Control
There are two inputs provided on the TOC1020 which
control the output format of the device. When NMINV is
connected to a logic LOW, the MSB is inverted. When
NLiNV is connected to a logic LOW 02 through 010 will
be inverted. By using various combinations of these
commands the user can select any of the following
output data formats: binary, inverted binary, two's
complement inverted two's complement. The Output
Coding Table shows the output formats generated for
each of the control states.

Convert
The analog input to the TOC1020 is sampled at a time
tSTO after the rising edge of the CONV signal. The
output data from the 1024 comparators is encoded into
the proper format and the final result is transferred to
the output latches on the next rising edge. This timing is
shown in the Timing Diagram (Figure 1). Note that
there are minimum LOW and HIGH requirements of the
CONV signal ItpWH, tpwLI which must be met for
proper device operation. In addition, the performance is
generally improved if the CONV signal is LOW for as
long as possible. A circuit which provides an optimized
waveshape CONV signal to the TOC1020 is shown on
the Typical Interface Circuit.

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

TDCI020
Analog Input
The analog input to the TDC1020 has an equivalent
circuit shown in Figure 2. It should be noted that the
major component of the input impedance is capacitance,
and the input range is 4Vp-p. A low-impedance driving
circuit is recommended for the TOC1020 to obtain good
dynamic performance. All analog inputs to the TDC1020
must be connected to insure proper operation of the AID
converter.
Outputs

TTL (54174 LS) unit loads. The outputs hold the previous
data a minimum time tHO after the rising edge of the
CONV signal. New data becomes valid after a maximum
delay time. to.
No Connects
There are several pins labelled No Connect (NC) which
have no electrical connection to the chip. These pins
should be connected to AGNO for best noise
performance.

The data and overflow outputs of the TOC1020 are TTL
compatible. capable of driving four low power Schottky
TDC1020 Package Interconnections
Signal
Type

Signal
Name

Power

VCC
VEE
DGND
AGND

Reference

RT
ROFS
RTS
RMl
RM2
RM3
RM4
RM5
RM6
RM7
RB
RBS

Format Control

NMINV

Function
Positive Supply Voltage
Negative Supply Voltage
Digital Ground
Analog Ground
Reference Resistor. Top
Dverflow Sense
Reference
Reference
Reference
Reference
Reference
Reference
Reference

Resistor.
Resistor.
Resistor.
Resistor.
Resistor.
Resistor.
Resistor.

Top Sense
1/8 Tap
2/8 Tap
3/8 Tap
4/8 Tap
5/8 Tap
6/8 Tap

Reference Resistor. 718 Tap
Reference Resistor. Bottom
Reference Resistor. Bottom Sense

Value

J1 Package Pins

GO Package Pins

5.0V
-5.2V
O.OV
O.OV

13. 14. 19. 20. 40. 58
12.15.16.17.18.21
10. 11.22. 23
43. 55

K4. K5. L7. K8. Cll. Bl
L3. L5. K6. L6. K7. L8
L2. K3. L10. Kl0
Al0. A3

2.0V
2.0V
2.0V
1.5V 1

59
57
60
54

C2
B2
Cl
B3

1.0V 1
0.5V 1
O.OV 1

53
51
49
47
45

A4

-2.0V
-2.0V

44
39
41

B9
Cl0
Bll

-0.5V 1
-1.0V 1
-1.5V 1

A5
B6
A8
A9

NLiNV

Not MSB Invert
Not LSB Invert

TTL
TTL

63
28

E2
Jll

Convert

CONY

Convert

TTL

36

Dll

Analog Input

VIN

Analog Signal Input

Outputs

OVF
OVF

Overflow
Overflow Complement
Most Significant Bit

Dl MSB
D2
D3
D4
D5
D6
Note:

+2 to -2V
TTL
TTL
TTL

46. 48. 50. 52

B8. B7. B5. B4

1
2

El
F2
Fl

TTL
TTL
TTL

3
4
5
29

TTL
TTL

30
31

G2
Gl
Hl0
Hll
Gll

1. Measured values.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-7

I

TDCI020
TDC1020 Package Interconnections (cont.)
Signal
Type

Signal
Name

Outputs

No Connects

Function

Value

J1 Package Pins

GO Package Pins

D7
DS
D9
DIO LSB

Least Significant Bit

TTL
TTL
TTL
TTL

32
33
34
35

FlO
Fll
Ell
Dl0

NC

No Connection

Open

6, 7, S, 9, 24, 25, 26, 27,
37, 3S, 42, 56, 61, 62, 64

H2, HI, J2, Jl, Kl, K2, L4,
K9, L9, Kll, Jl0, Gl0, El0,
Bl0, A7, A6, A2, D2, Dl

Output Coding Table
Binary
True

True

Inverted

Input

NMINV=1
NLlNV=1

NMINV=O
NLlNV=O

NMINV=O
NLlNV=1

NMINV=1
NLlNV=O

>2.000V
2.000V
1.996V

MSB - LSB 10VFI
0000000000111
0000000000101
0000000001101

1111111111111
1111111111101
1111111110101

1000000000111
1000000000(01
1000000001101

0111111111111
0111111111101
0111111110(01

··•

··•

··•

0.004V
O.OOOV
-0.004V

•
•

·

-1.996V
-2.000V
Note:

3-8

Offset Two's Complement
Inverted

··
·

·
··

0111111111(01
1000000000101
1000000001101

1000000000101
0111111111101
0111111110(01

1111111111101
0000000000101
0000000001101

0000000000101
1111111111(01
1111111110(01

1111111110101
1111111111101

0000000001 (01
0000000000101

0111111110101
0111111111101

1000000001101
1000000000101

··
·

··
·

··
·

·•
·

Input voltages are at code centers.

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TDCI020
Figure 1. Timing Diagram

I. .

F~

~I""

--'l

CONV ..1f""SN-AM-P-LE---\"---_ _

-

'1

IpWH~ IPWL-,

SAMPLE
N+1

\.

I'

r

\

If""S-AM-PL-E-""'\
/
2
\..... _ - - - - J .

'1

------~

ANALOG INPUT

--.j
DIGITAL OUTPUT

DATA
N+1

1

-~+I--~~--~~~~~~--~--~~~--~~--~~
21162A

Figure 2. Simplified Analog Input Equivalent Circuits

I

I

CIN IS A NONLINEAR JUNCTION CAPACITANCE
VRB ISA VOLTAGE EQUAL TO THE VOLTAGE ON PIN RB

REFERENCE
RESISTOR
CHAIN

Figure 3. Equivalent Input Circuits
Convert, NMINV, and NLiNV
VCC

Figure 4. Output Circuits

0---..,...-.--.--

~p----<> vCC

L.-~>--o()

DVREF

DGND

OUTPUT

0------1
0------4---

For More Infonnation call 1-800-722-7074.

21378A

+VCC

8100
TO
OUTPUT
PINo-t-'--+
1N3062

21379A

Raytheon Semiconductor

OUTPUT
EQUIVALENT
CIRCUIT

LOAD 1
TEST LOAD FOR
":'
DELAY MEASUREMENTS 21380A

3-9

I

TDCI020
Absolute maximum ratings (beyond which the device may be damaged) 1
Supply Voltages
VCC (measured to DGNDI .............................................................................................................................................. - 0.5 to + 6.0V

VEE (measured to AGNDI .............................................................................................................................................. + 5.0 to - 6.0V
AGND (measured to DGNDI ........................................................................................................................................... -1.0 to + 1·.0V
Input Voltages
CONY, NMINV, NLINV (measured to DGNDI ............................................................................................................. - 0.5 to + 5.5V
VIN (measured to AGNDI ................................................................................................................................................... VCC to VEEV
Any reference (measured to AGNDI ................................................................................................................................ VCC to VEEV
VRT (measured to VRBI ................................................................................................................................................. -1.0 to + 4.4V
Output

Applied voltage measured to DGND 2 ......•..•.•...•.......•........•..••.....•...............•..•......••...•..•...••.•.•.......•.••.•..•...........•..•...• - 0.5 to + 5.5V
Applied current, externally forced 3.4 ....................................................................................................................... -1.0 to + 6.0mA
Short-circuit duration (single output in HIGH state to groundl ......................................................................................... 1 Second
Sense lead current .......................................................................................................................................................... -1.0 to 1.0mA
Temperature

Operating, ambient .......................................................................................................................................................... - 55 to + 90°C
junction ....................................................................................................................................................................... + 175°C
Lead, soldering (10 secondsl ..................................................................................................................................................... +300°C
Storage ............................................................................................................................................................................ - 65 to + 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

Operating conditions
Temperature Range
Commercial
Max
Min
Nom

Parameter

3-10

4.75
-4.9
-0.1

VCC
VEE

Positive Supply Voltage
Negative Power Supply Voltage

VAGND

Analog Ground Voltage (measured to DGNDI

tpWL
tpWH

CONY Pulse Width, LOW
CONY Pulse Width, HIGH

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

IOL
IOH

Output Current, Logic LOW
Output Current, Logic HIGH

VRM2
VRM4
VRM6

Reference Tap, 1/4-Scale
Reference Tap, 1/2-Scale
Reference Tap, 3/4-Scale

0.8
-0.2
-0.8

1.0
0.0
-1.0

0.2
-1.2

0.8
-0.2
-0.8

VRT
VRB
VRT-VRB

Most Positive Reference Voltage
Most Negative Reference Voltage
Reference Voltage Differential

1.8
-1.8
3.6

2.0
-2.0

2.2
-2.2

1.8
-1.8

4.0

4.4

3.6

5.0
-5.2
0.0

5.25
-5.5
0.1

Min

22
18

4.75
-4.9
-0.1

Extended
Nom
5.0
-5.2
0.0

Max

Units

5.25
-5.5
0.1

V
V
V

22
20

ns
ns

0.8

0.8
2.0

2.0
4.0
-400

Raytheon Semiconductor

1.2

4.0
-400
1.0
0.0
-1.0
2.0
-2.0
4.0·

V
V
rnA
p.A

1.2
0.2
-1.2

V

2.2
-2.2

V
V

4.4

V

V
V

For More Information call 1-800-722-7074.

TDCI020
Operating conditions (cont.)
Temperature Range
Commercial
Min
Nom
Max

Parameter
VIN

Input Voltage Range

TA
TC

Ambient Temperature, C-Grade
Case Temperature, V-Grade

VRB

±2.0

0

VRT

Min

Extended
Nom

VRB

±2.0

Max

Units

VRT

V

125

°c
°c

70
-55

Electrical characteristics within specified operating conditions
Temperature Range
Parameter

Test Conditions

ICC
lEE

Total Positive Supply Current
Total Negative Supply Current

VCC=VEE=Max
VEE=Max

IREF
RREF

Reference Current
Reference Chain Resistance

VRT' VRB = Nom
VRT' VRB=Nom

RIN
CIN

Analog Input Resistance
Analog Input Capacitance

VRT' VRB=Nom, VIN=VRB
VRT' VRB = Nom, VIN = VRB

ICB

Input Constant Bias

VEE=Max

IlL
IIH
II

Input Current, Logic LOW
Input Current, Logic HIGH
Input Current, Maximum

VCC=Max, VI=0.5V
VCC=Max, VI=2.4V
VCC=Max, VI=5.25V

VOL
VOH

Output Voltage, Logic LOW
Output Voltage, Logic HIGH

VCC=Min,IOL=Max
VCC=Min, IOL =Max

lOS

Short-Circuit Output Current

VCC=Max, output HIGH, one pin to
ground, one second duration max.

CI

Digital Input Capacitance

TA =25°C, f=lMHz

Commercial
Min
Max

Extended
Min
Max

850
-500

850
-500

50

50

80

80

3000

2000

Units
mA
mA
mA
Ohms
Ohms
pF

300

300

2

3

mA

50
100
100

50
100
100

/LA
/LA
/LA

0.5

0.5

2.4

2.4
-35

-35

15

15

V
V
mA

pF

Switching characteristics within specified operating conditions
Temperature Range
Parameter

Test Conditions

Commercial
Min
Max

Maximum Conversion Rate

VEE=Min, VCC=Min

20

tSTO

Sampling Time Offset

VEE=Max, VCC=Max

3

tD

Output Delay
Output Hold Time

FS

tHO

For More Information call 1-800-722-7074.

VEE=Max, VCC=Max
VEE=Max, VCC=Max

Extended
Min
Max
20

17

3

37
5

Raytheon Semiconductor

5

Units
Msps

17

ns

43

ns
ns

3-11

I

TDCI020
System performance characteristics within specified operating conditions
Temperature Range
Parameter
ELI
ELI
ELD

Linearity Error, Integral
Linearity Error, Integral
Linearity Error, Oifferential

Test Conditions

Typ

Reference Taps Open
Reference Taps Adjusted

±0.1
±0.05
±0.05

Reference Taps Open

Extended
Min
Max

±0.2
±0.1
±0.1

±0.2
±0.1
±0.1

5

225

CS

Code Size

EOT
EOB
TCO

Offset Error, Top
Offset Error, Bottom

25
-30

30
-35

Offset Error Tempco

± 10

±20

tTR

Transient Response

Full-Scale Input Step,
Settling to ± 32 LSBs

20

30

30

BW

Full-Power Bandwidth

Full-Scale Input

10

5

SNR

Signal-to-Noise Ratio

Note 1
60
59
56
54
52

58
56
52
47
43

59
58
54
48
43

55
52
48
41

-66
-64
-58
-50
-44

-58

-53

-56
-52
-43
-41

-53
-46

1.0MHz

70

FIN~2.0MHz

68
63
55
48

53
54
48

53
54
48

FIN~

1.0MHz

FIN~2.0MHz
FIN~5.0MHz
FIN~8.0MHz

SINAO

Signal-to-Noise And Distortion

FIN ~ 10.0MHz
Note 1
FIN~

1.0MHz

FIN~2.0MHz
FIN~5.0MHz
FIN~8.0MHz

THD

Total Harmonic Distortion

FIN ~ 10.0MHz
Note 1
FIN~ 1.0MHz
FIN~2.0MHz
FIN~5.0MHz
FIN~8.0MHz

FIN ~ 10.0MHz
SFDR

Spurious-Free Dynamic Range

FIN~5.0MHz
FIN~8.0MHz

FIN ~ 10.0MHz
EAP

Aperture Error

DP

Differential Phase

DG

Differential Gain

Note:

5

225

Units
%
%
%
% Nominal
mV
mV
",A/oC
ns

MHz

58
56
52

dB
dB
dB
dB
dB

52

dB

52
45

dB
dB
dB
dB

39

dBc
dBc
dBc
dBc
dBc

Note 1
FIN~

3-12

Commercial
Min
Max

40
35

dB
dB

50
FS ~ 4 x NTSC Subcarrier,
Reference Taps Adjusted
FS ~ 4 x NTSC Subcarrier,
Reference Taps Adjusted

1. FS ~ 20Msps. Reference Taps Adjusted.

VCC~ VEE~ Nom,

dB
dB
dB

50

ps

0.3

0.5

Degree

0.8

1.0

%

TA ~ 25°C.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI020
Typical Performance Curves
A. Typical SNR vs. Input Frequency
~

i!

il

~
S!li

Ii:;
",!Q
~:
;iz

B. Typical Supply Current vs. Temperature

6OF~~~:I
50

600

500

-

ICC

400
40

300

30

I (mAl

ZOO

Zo

100

52~
::~ 10

0

:E=
==

......

-100

OL-____~____~______~____~____~
3ZK

10M

INPUT FREOUENCY (Hzl

For More Information call 1-800·722-7074.

-ZOO

10

ZO

30

40

50

60

70

AMBIENT TEMPERATURE
lEE

-300

Raytheon Semiconductor

3-13

I

TDCI020
Calibration
Calibration of the TOC1020 consists of adjusting the
reference taps so that the converters integral linearity,
gain and offset errors are minimized. To minimize the
offset errors the sense leads must be used properly. The
sense leads are not designed to carry very much current
1< 1mAl and should therefore be used in a feedback
loop to a high-impedance input such as that shown in
the Typical Interface Circuit. When a circuit similar to
that in the Typical Interface Circuit is used for
generating the reference voltages, calibration can be
achieved with the following procedure:
1. Apply an input to the input amplifier which is
1/2 LSB less than full-scale lAID input = 1.998VI and
adjust the gain so that the output of the AID is
toggling between full-scale and one LSB below fullscale 11111111111 and 1111111110 for binary
conversionsl·
2. Apply an input to the input amplifier which is
1/2 LSB greater than zero-scale lAID input =
-1.998VI and adjust VRB via the VRB pot so that
the output of the AID is toggling between 0 and 1
10000000000 and 0000000001 for binary
conversionsl.
The AID converter will now be calibrated to provide
accurate conversions throughout its input range. To
optimize the integral linearity of the device set up the
"Subtractive Ramp Test" described on page 6 of the
TRW Applications Note TP-30, "Understanding Flash
AID Converter Terminology," then adjust the mid-point
taps to minimize the bow in the error curve.
Typical Interface
A Typical Interface Circuit is shown of the TOC1020. The
analog input amplifier, a THC4231, is used to directly

3-14

drive the AID converter. This amplifier is set up to have
a gain of four and will provide the recommended + 2 to
-2V input signal to the TOC1020 when it has a 1Vp-p
input signal. All four analog input pins are connected in
parallel to decrease the parasitic inductance. An LM313
is used to provide a stable reference voltage which is
buffered by a dual op-amp, generating VRT and VRB.
Both op-amps have their outputs buffered by an emitter
follower to decrease the output impedance seen by the
reference resistor chain. To minimize noise coupling into
the reference resistor chain, bypass capacitors have been
added, bypassing the reference taps to ground.
Since capacitive coupling from the digital signals to the
analog input will adversely affect the converter performance, careful attention to board layout is recommended.
As is true with most bipolar integrated circuits, the
substrate of the TOC1020 IVEEI must be the most
negative potential applied. This rule applies for all
conditions of temperature, signal level and power supply
sequencing. In many systems, the voltage reference
generators and input driving amplifier are powered from
voltages greater than the + 5 and - 5.2V of the
TOC1020. Whenever this situation occurs, it is always
possible for the VEE inputs of the TOC1020 to be
positive with respect to the VIN or VRB inputs when
power supplies are cycled ON and OFF.
To protect the TOC1020 from latch-up due to substrate
bias, TRW recommends the use of a 1N5818 Schottky
diode connected between VEE and VIN and another
between VEE and VRB with the anode of each diode
connected to VEE. The diodes prevent VIN and VRT from
going more than O.4V more negative than VEE. This
protection circuit is shown in Figure 5.

Raytheon Semiconductor

For More InfonnatiOIl call 1-800·722-7074.

TDCI020
Figure 5. Typical Interface Circuit
VCC +5V >-~--------------:::-;'t:-(VV"'-"'t;:;;::F-"""'-r---'

;r:, ;r:,

O.I~F

;r:,

O.I~F

VCC

VCC
46
48
50
ANALOG ~
INPUT ~'---r---"i

40,58

19,20

13,14

10,11,
22,23

VCC DGND
16

VIN
VIN

OVF

lD

10

VIN

OVF

2D

20

VIN

(MSS)D 1

3D

43
AGND
~'VV''''-

GND

52

1Vp.p

.15V '>-_ _

8

VCC

D2

AGND

_ _-'

11
13

D3

RTS

D4

29

14

30
74LS174

4D

40

5D

50

6D

60

CLK
RT

10
12
15

CLR

TDC1020

O.1~1
16
ROFS
RM2

D5
D6

~

RM4

D8
D9
RM6

(LSS) DlO

31

3D

33

11

34

13

35

14

CONV
VEE
12,15

VEE
16,17

20
74LS174

30

4D

40

5D

50

6D
CLK

Rs

ANALOG
GROUND

2D

32

RSS

VEE ·5V )----,...----.-'''''''''------+----......

Vec GND
lD
10

30

60

10
12
15

CLR

1

CLOCK
INPUT

VEE
18,21

,~.I~F ~.I~F ~.I~F
Rl, R2 2Kn 10· TURN POTENIOMETER
INDUCTORS: FAIR·RITE #2743 001112

>------,

V

DIGITAL ~
GROUND·

m

For More Infonnation call 1-800-722-7074.

21377A

Raytheon Semiconductor

3-15

I

TDCI020
Ordering . Information
Temperature Range

Screening

TDC1020J1C
TDC1020J1V

STD-TA=O°C to 70°C
EXT - TC= -55°C to 125°C

Commercial
Military

64 Pin Hermetic Ceramic DIP
64 Pin Hermetic Ceramic DIP

lO20J1C
1020J1V

TDC1020GOC
TDClO20GOV

STD-TA=O°C to 70°C
EXT-TC= -55°C to 125°C

Commercial
Military

68 Pin PGA
68 Pin PGA

1020GOC
1020GOV

Product
Number

Package

Package
Marking

Pin Assignments
68 Pin Grid Array - GO Package
Pin

Name

Pin

Name

Pin

Name

Pin

Name

A2

NC

A3

RMl
NC

A5
A6
A7

AGND
RM2
RM3
NC
NC

BS
Bl0
Bll
Cl
C2
Cl0

RBS
RTS
RT
RB

D7
D8
D3
D2
NC

RM5
RM6
AGND
VCC
ROFS
RMl
VIN
VIN
RM4
VIN
VIN

Cll
Dl
D2
DlO
Dll
El
E2
ElO

VCC
NC
NC
DlO LSB
CONV
OVF
NMINV
NC

Ell
Fl
F2

DS
Dl MSB
OVF

K4
K5
K6
K7
K8
KS
KlO
Kll
L2
L3
L4
L5
L6
L7
L8
LS
L10

VCC
VCC
VEE
VEE
VCC
NC

A8
A9
Al0
Bl
B2
B3
B4
B5
B6
B7
B8

FlO
Fll
Gl
G2
Gl0
Gll
Hl
H2
Hl0
Hll
Jl
J2
Jl0
Jll
Kl
K2
K3

A4

11
10

9
8
7

6
5

/'

...

D6
NC
NC
D4
D5
NC
NC
NC
NLiNV
NC
NC
DGND

1

OVF

2

D1 (MSa

3

D2

4

D3
NC
NC
NC
NC 9

DGNO
NC
DGND
VEE
NC

DGND 10
DGND 11
VEE 12
VCC 13
VCC 14
VEE 15

VEE
VEE
VCC
VEE
NC

VEE 16
VEE 17

DGND

44 RM7

\.

'......" ......'
, ....\ i·.. ··"
',.......,,"\,..........',

\

TOP

VIEW

41 Ras

37 NC
36 CONV

' .....J' ...... ,

,....., ,.....,
'..../ \.../

'...../ '...... '

43 AGND
42 NC
40 VCC
39 Ra
38 NC

' ......''-.....,1
\. I

50 VIN
49 RM4
48 VIN

VEE 21

,...., ,....,
,

53 RM2
52 VIN
51 RM3

VCC 20
DGND 22
DGND 23
NC 24

,,,.....,,.....\

55 AGND
54 RMI

47 RM5
46 VIN
45 RM6

VEE 18
VCC 19

....."i .....
' \..../
,...., ',::=-:,
... ··\ , .... \
J ';':;;' , .......' \ .... '
,,.....
....\ , .....,
'...../ ' ..../
,....." ......,
,'......
....,' \,......./
',......../\.,' .....
.......',
,'......
....,",......../,

OVF

35 D10 (LSB)
34 D9
33 D8

A

a C D E F G H

J

K L

21385A

64 Pin Hermetic Ceramic DIP - Jl Package

40G05371 Rev 0 8193

3·16

Raytheon Semiconductor

For More Information caJI1-800·722·7074.

TDCI035

TDCI035
Monolithic Peak Digitizer
a-Bit, 30 ns Full Response Peak Width

Description

Features

The TDC1035 is a unique variant of the full-paraJlel
("flash") analog-tcKIigital converter, capable of capturing
the maximum peak amplitude of one or more pulses
applied to its input between asynchronous reset pulses.
Multiple "peak read" operations can be performed
between resets. Peaks are detected digitally, so
operation is stable and predictable. Packaged in a
24-pin CERDIP, the TDC1035 features lower power
consumption and smaller size than an analog peak
detector/ADC combination. All digital inputs and outputs
are m compatible, and all outputs are registered and
three-state.

•
•
•
•
•
•
•
•
•
•
•
•
•

8-bit resolution
Full DC linearity for pulses - 30 ns wide
Does not require analog peak-hold circuit
Continuous peak capture between resets
Multiple read operations between resets
1/2 LSB linearity
Narrow ambiguity region around reset
Detects pulses as small as 12 ns wide
Guaranteed monotonic
Selectable data format
Available in 24-pin CERDIP and 28-lead
PLCC packages
1.0W power consumption
Three-state registered outputs

Applications
•
•
•
•

Functional Block Diagram

Radar pulse classification
Electronic countermeasures
Radiation measurement
Instrumentation

R/2
V,N

>-t---i
R

R/2
RESET

For More Information call 1-800-722-7074.

Raytheon Semiconductor

eLK

TSO

3-17

I

TDCI035
Pin Assignments
0 1 (MSS)
O2
03
04
OGND
VEE

24
23
22
21
20
19

MINV
OE
Rs
AGND
I\1ID
V1N
18 AQND
17 RT
16 RESET
15 Os (LSB)
14 ~
13 0 6

1

2
3
4
5

6

ClK 7
Vee
VEE
0GND
LlNV
Os

8
9
10
11
12

65-6365

24 Pin CERDIP - 87 Package

Rs 26
OB 27
MINv\ 28
0 1 (MSB) 1
~ 2
03 3
D4 4

~:n::n:;~~

18
17
16
15
14
13
12

RESET
Os

07
06
Os
LlNv\
OGND

LOCOr-..COQ)!=::
0(.)

w:.::

0(.)

ifl

i'5z~5::i1z>

c

65-6366

28 Lead PLCC - R3 Package

Functional Description
General InfDrmatiDn
The TDC1035 peak detector operates on groundreferenced negative-going signals. Within tRP
nanoseconds after the rising edge of the clock signal
ClK, it outputs the most negative value reached since
the previous RESET pulse. The active-HIGH RESET control
is independent of ClK, but may be connected to ClK to
provide a single-control peak detector. Multiple output
cycles are permitted between reset operations.
The TDC1035 contains parallel array of comparators, an
array of latches, and an encoder which outputs the
location of the highest -valued latch which is set. The
TDC1035's response characteristics are determined by its
comparator array. A comparator's response time is
determined by the degree of overdrive. since the output
changes only when the area above threshold reaches a
characteristic value. Therefore, the digitization accuracy of
a pulse's peak value depends on the shape of the pulse.
To permit accurate, repeatable characterization, the
TDC1035 is tested with a slew-rate limited "square"
pulse. It will digitize Ito its DC accuracy! the peak value
of a square pulse having a minimum duration of 30ns.
The accuracy degrades gracefully as the duration
decreases from 30 down to 12ns, where it understates
the applied amplitude by 15% IFigure
Production
characterization of the TDC1035 uses "square" pulses
with controlled rise and fall times of Bns.

n

3-18

Performance of the TDC1035 with other pulse shapes
Isuch as Gaussian or bandwidth-limited square pulse! can
be estimated by applying an energy above threshold
model, with area of 120 picoVolt -seconds.
The operation of all asynchronous sequential logic circuits
involves some temporal ambiguity. The most common
form of this ambiguity, metastability, occurs in data synchronizers. In a peak digitizer such as the TDC1035, this
ambiguity comes in the form of periods during which the
accuracy of the measurement of a pulse may be
affected, or the pulse may not even be detected. There
is a 10ns ItRP! ambiguity period after the falling edge of
the RESET signal, during which detection or accuracy of
detection of any pulse is not guaranteed. There is also a
region of 40ns Itpc! before the rising edge of the
loutput! clock IClK! where a pulse may be missed or
detected inaccurately. These regions are shown in the
timing diagrams, Figures 1 and 2. During the latter
period, if the input signal increases to a new peak larger
than the previously-latched value, the value loaded into
the output register may be incorrect land will most likely
be zero!; nonetheless, the peak detection latches will
hold the Icorrect! new peak value.
As shown in Figure 3, the TDC1035's comparator inputs
have emitter-follower buffers, which limit the permissible
input signal slew rate to 250VI f1S. This corresponds to a
full-scale transition time of Bns.

Raytheon Semiconductor

For More Information caiI1-800-722-7074.

TDCI035
Power
The TDC1035 operates from two supply voltages: + 5.0V
and - 5.2V The current return for the positive supply is
0GNO, and the return for the negative lanalog) supply is
AGNO. All power and ground pins MUST be connected.

Reference
The reference for the TOC1035 is a negative voltage
applied across a chain of 255 resistors. The top of this
chain is connected to the RT pin, and the voltage
applied to the RT pin IVRT) should be within 0.1V of the
analog ground. Note that the difference between the
voltage applied to the pin and the voltage at the
reference chain is the offset specification IEOT and EOS).
The bottom of the reference resistor chain is connected
to the RS pin, and the voltage applied to the RS pin
IVRS) should be between 1.8 and 2.2V negative with
respect to the RT pin for full-specification operation.
Reduced reference voltage operation is possible at
reduced accuracy Ifor example, for generating a nonlinear transfer function). The RT- RS reference source
should be able to deliver at least 45mA.
Due to the variation in the reference currents with clock
and input signals, RT and RS should be connected to
circuit nodes with a low impedance to ground. For
circuits in which the reference is not varied at a high
rate, a bypass capacitor to ground is recommended. If
the reference inputs are exercised dynamically le.g., for
AGC or nonlinear operation), a low-impedance reference
source is required. The reference voltages may be varied
dynamically; contact the factory for information on
limitations when the device is used in this mode. The
performance of the TOC1035 is specified with DC
references of VRT = O.OV and VRS = - 2.0V

Control
Two function control pins, MINV and LlNV, are provided.
These names stand for active-lOW Most significant bit
INVert and active-lOW least significant bits INVert,
respectively. These controls are for DC li.e., steadystate), not dynamic, use. They permit the output coding
to be either straight binary or offset two's complement.
in either true or inverted sense, according to the Output
Coding Table. A single output state control pin, OE, is
provided. The three-state outputs may be placed in a
high-impedance state by applying a logic HIGH to the OE
control pin, and enabled by driving OE lOW.

For More Information call 1-800-722-7074.

The function control pins may be tied to VCC for a logic
HIGH, and 0GNO for a logic lOW; however, a 2.2 kOhm
pull-up resistor is preferred over direct connection to
VCC. If a pull-up resistor is not used, the absolute
maximum voltage rating for the part becomes that of the
TTL input, 5.5V, rather than the higher value for the VCC
terminal.

Command
Two pins, RESET and ClK, control the TDC1035. When
brought HIGH, the level-sensitive RESET control resets
the peak-storing latches. The edge-sensitive ClK control
causes the peak value to be loaded into the output
register when a rising-edge IlOW-to-HIGH) signal is
applied. As noted above, there is a data ambiguity period
associated with the operation of each of these inputs.

Analog Input
Although the TDC1035's 255 comparators have emitterfollower isolated inputs, the input impedance can vary up
to 25 percent with the signal level, as comparator input
transistors switch on or off. As a result, for optimal
performance, the source impedance of the driving device
must be less than 25 Ohms. The input signal will not
damage the TOC1035 if it remains in the range
VEE-0.5V to VAGNO+0.5V If the input signal stays
between the VRT and VRS reference voltages, the 8-bit
digital equivalent of the most negative voltage reached
will be latched into the array of latches, subject to the
dynamic effects mentioned above. A transient more
negative than VRS will cause a full-scale output too
after the ClK line rises.

Outputs
The outputs of the TDC1035 are TTL compatible, capable
of driving four low-power Schottky TTL 154lS174lS) unit
loads or the equivalent. The outputs hold the previous
data a minimum time tHO after the rising edge of the
ClK input, and are guaranteed to have the new output
value after a maximum time toO. Under light DC load
conditions Isuch as driving CMOS loads or base-input
low-power Schottky such as the 74l5374) 2.2k pull-up
resistors to + 5.0V are recommended.

Raytheon Semiconductor

3-19

I

TDCI035
Package Interconnections
Value

B7 Package Pins

+5.OV
-5.2V
O.OV
O.OV
O.OV
-1.0V
-2.0V
TTL (Active LOW)
TTL (Active LOW)
TTL (Active LOW)
TTL (Active HIGH)
TTL (Rising Edge)
. O.OV to -2.0V
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

8
6,9
5,10
18,21
17
20
22
24
11
23
16
7
19
1
2
3
4
12
13
14
15

Function

Name

Positive Supply Voltage
Negative Supply Voltage
Digital Ground
Analog Ground
Reference Resistor, Top
Reference Resistor, Middle
Reference Resistor, Bottom
MSB Invert
LSB Invert
Output Enable
Resets Peak Value to Zero
Loads Output Register
Analog Input Signal
MSB Output

Vee
VEE
DGND
AGND
RT
RMD
RB
MINV
LlNV
OE
RESET
eLK
Y,N
Dl
D2
D3
D4
DS
DS
D7
DS

i

LSB Output

Figure 1. Timing with Separate RESET and ClK
I

~~t\OG
RESET

DATA

i
I

Figure 2, Timing with Common RESET and ClK

FIPWHR

8ns~

r-

FULL SCALE

I
1

n

I

-----~
IPWHC--J \1'-----PEAKN·1

I

~

----1--..:...-IIHHCO ~I

~ 100 --..I

3-20

I

9
7, 11
5,12
20,25
19
24
26
28
13
27
18
8
21
1
2
3
4
14
15
16
17

"'1

"" tRP ..,1 "" IMIN..,I "" IpC
i~ - -

J-{ ~ns

4
CLK

I

R3 Package Pins

21222A

Raytheon Semiconductor

For More Information call 1-800-722·7074.

TDCI035I
Figure 3. Simplified Analog Input Equivalent Circuits

'.O~EJ~ ~t ~
VEEA

VRB

CIN IS ANONLINEAR JUNCTION CAPACITANCE
VRB IS AVOLTAGE EQUAL TO THE VOLTAGE ON PIN RB

REFERENCE
RESISTOR
CHAIN

Figure 4. Digital Input Equivalent Circuit

VEE
21191A

Figure 5. Output Circuits

--_-0 Vee

VeeO---~--------~--

8100
1600
TO
OUTPUT
PIN

INPUT

0--_*-+
ALL
DIODES
lN3062

---+--o OUTPUT
21188A

LOAD 1
21189A

Figure 7. Variation of Accuracy as a Function
of Width. "Square" Input Pulse

Figure 6. Recommended Input Circuit
TDC1035

VIN
VIDEO
OPERATIONAL
AMPLFIER

~

'5
21224A

~

7 ~--+--~---+------i

!!i~6

i
15

20

25

PULSE WIDTH ( ns at 50"10)

For More Information call HIOO-722-7074.

Raytheon semiconductor

30
21225A

3-21

TDCI035
Output Coding
Binary
Range

Offset Two's Complement

Step

-2.0000V FS
7.8431mV Step

-2.0480V FS
8.000mV Step

True
MINV = 1
LlNV = 1

000
001

O.OOOOV
-0.0078V

O.OOOOV
-0.0080V

00000000
00000001

11111111
11111110

10000000
10000001

01111111
01111110

-0.9922V
-1.0000V
-1.0078V

-1.0160V
-1.0240V
-1.0320V

01111111
10000000
10000001

10000000
01111111
01111110

11111111
00000000
00000001

00000000
11111111
11111110

•
•
•

•
•
•

•
•
•

•
•
•

•
•

-2.0240V
-2.0320V

11111110
11111111

00000001
00000000

01111110
01111111

··•

•
•
•
127
128
129

·••

··•

254
255

-1.9844V
-1.9922V

·••

·••

Inverted
0
0

True
0
1

Inverted
1
0

··
·

··
·

·••

·

10000001
10000000

Absolute maximum ratings (beyond which the device may be damagedl 1
Supply Voltages

Vee (measured to 0GNO) .............................................................................................................................................. -0.5 to + 7.0V
VEE (measured to 0GNO) .............................................................................................................................................. -7.0 to +0.5V
AGNO (measured to 0GNO) ........................................................................................................................................... -0.5 to +0.5V
Input Voltages

RESET. eLK. DE, MINV, lINV (measured to AGNO) ................................................................................................ - 0.5 to + 5.5V
VIN, VRT' VRS (measured to AGNO) ............................................................................................................... (VEE - 0.5) to + 0.5V
VRT (measured to VRS) ................................................................................................................................................. - 2.2 to + 2.2V
Outputs

Applied voltage (measured to 0GNO) ....................................................................................................................... -0.5 to +0.5V 2
Applied current (externally forced) .......................................................................................................................... -1.0 to 6.0mA 3.4
Short-circuit duration (single output HIGH to shorted to ground) .................................................................................... 1 Second
Temperature

Operating, ambient ........................................................................................................................................................ - 55 to
junction ......................................................................................................................................................................
Lead, soldering (10 seconds) .....................................................................................................................................................
Storage ............................................................................................................................................................................ - 65 to
Notes:

+ 125°C
+ 175°C
+ 300°C
+ 150·C

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating condjtions.
Functional operation under any of these conditions is NOT implied. Device performance is guaranteed only if specified operating conditions
are met.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as positive current flowing into the device.

3-22

Raytheon Semiconductor '

For More Information caJI1-800·722·7074.

TDCI035
Operating conditions
Temperature Range
Parameter

Min
4.75
-4.90
-0.1

Positive Supply Voltage
Negative Supply Voltage
Analog Ground Voltage

VCC
VEE
VAGND

tpWlC
tpWHC

Reset Minimum Pulse Width, HIGH
ClK Minimum Pulse Width, lOW
ClK Minimum Pulse Width, HIGH

SR

Input Signal Slew Rate

Vil
VIH

Input Voltage, logic lOW
Input Voltage, logic HIGH

10l
10H

Output Current, logic lOW
Output Current, logic HIGH

VRT
VRB
VRT-VRB

Reference Voltage, Top
Reference Voltage, Bottom

VIN

Input Voltage Range

TA
TC

Case Temperature

tpWHR

Standard
Nom

Max

Min

Extended
Nom

5.25
-5.5

4.50
-4.90
-0.1

5.0
-5.2
0.0

5.0
-5.2
0.0

0.1

20
20

Max

20

ns
ns

0.8
2.0

4.0
-400

4.0
-400

-0.1
-1.8

0.0
-2.0

0.1
-2.2

-0.1
-1.8

1.8

2.0

2.2

1.8

VRB

VRT

Ambient Temperature, Still Air

Vlp.S

250

0.8
2.0

0.1
-2.2
2.2

0.0
-2.0
2.0

VRT
-55

V
V
rnA
p.A
V
V
V

VRB

V

+125

°c
°c

70

0

V
V
V
ns

20
20
20
250

Reference Voltage Span

Units

5.5
-5.5
0.1

Electrical characteristics within specified operating conditions
Temperature Range
Test Conditions

Parameter

Standard
Min
Max

Extended
Min
Max

ICC
lEE

Positive Supply Current
Negative Supply Current

VCC = Max, Static
VEE = Max, Static

35
-160

35
-160

IREF
RREF

Reference Current
Reference Resistance

VRT-VRB=Nom
Total, RT to RB

35

35

RIN
CIN
ICB

Input Equivalent Resistance (DC)

VRT' VRB=Nom, VIN=VRB
VRT' VRB=Nom, VIN=VRB
VEE=Max

III
IIH

Input Current logic lOW
Input Current logic HIGH

11M

Input Current, VIN = Max

10Zl

Hi-Z Output leakage Current, Output lOW
Hi-Z Output leakage Current, Output HIGH
Short-Circuit Output 1

VCC=Max, VO=OV
VCC=Max, VO=5V
VCC= Max, Output HIGH, one
output tied to DGND for 1 second.

VOH

Output Voltage, logic lOW
Output Voltage, logic HIGH

VCC=Max, 10l =Max
VCC=Min,IOH=Max

CIN

Input Capacitance, Digital

10ZH
lOS

VOL

Note:

Input Capacitance, Analog
Input Constant Bias Current

57

57

50

VCC=Max, Vil =O.4V
VCC = Max, VIH = 2.4V
VCC=Max, VIH=5.5V
-30
-30

Units
rnA
rnA
rnA
Ohms
kOhms

50
50
250

50
350

pF
p.A

-500
50
1

-500
50
1

p.A
p.A
rnA

30
30
-50

p.A

30
30
-50

-30
-30

0.5
2.4

0.5
2.4

10

10

p.A
rnA

V
V
pF

1. Worst case. all digital inputs and outputs LOW.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-23

I

TDCI035
Switching characteristics within specified operating conditions
Temperature Range
Parameter

Standard
Min
Max

Test Conditions

Extended
Min
Max

Units

tpc

ClK Setup Time

VCC~Min, VEE~Min,

load 1

30

30

ns

tRP
tDO

RESET Delay
Output Delay

VCC~Min, VEE~Min,

load 1
load 1

5
35

5
35

ns
ns

tHO
lOIS

Output Hold Time
Output Disable Time
Output Enable Time

VCC~Min, VEE~Min,

tENA
Note:

VCC~Min, VEE~Min,

load 1
load 1
VCC~Min, VEE~Min, load 1

5

ns

5

VCC~Min, VEE~Min,

20
70

20
90

ns
ns

1. tRP and tpc are the guaranteed maximum lengths of the ambiguity periods.

System performance characteristics within specified operating conditions
Temperature Range
Test Conditions

Parameter

Standard
Min
Max

Extended
Min
Max

0.2

0.2
0.2

VRT' VRB ~ Nom
VRT' VRB~Nom

ELI
ELO

Linearity Error, Integral, Independent
Linearity Error, Differential

CS

Code Size

VRT' VRB~Nom

30

Analog Input Pulse Width

Square Pulse,
15% Accuracy
DC Accuracy

12

12

30

30

tMIN

EOT
EOB
TCO

Offset Error, Top
Offset Error, Bottom
Offset Error, Temperature Coellicenl

VIN~VRT
VIN~VRB

VRT, VRB , VCC' VEE~Nom

0.2
170

±8
±15
±20

30

170

Units
%FS
%FS
% Nominal

ns
ns
±8
±15
±20

mV
mV
ItV/oC

Applications Discussion

Under certain conditions, the real component of the
input impedance may go negative at frequencies near
100MHz. To prevent oscillation at the input signal port,
TRW recommends connecting the input signal to the
TOC1035 via a series-connected resistor of at least

10 Ohms located close to the device. Further, if the
signal bandwidth is not already limited so that the input
slew rate limit is not exceeded, external circuitry is also
recommended. The circuit shown in Figure 6
accomplishes both goals.

Ordering Information
Product
Number
TDC1035B7C
TDC1035B7V
TDC1035R3C

Temperature Range

Screening

Package

STD - TA =OOC to 700C
EXT - Te =-55OC to 1250C
TA =OOC to 700C

Commercial
MIL-STD-883
Commercial

24-Pin CERDIP
24-Pin CERDIP
28-Lead PLCC

Package
Marking
1035B7C
1035B7V
1035R3C

-

40G06460 Rev B 8/93

3-24

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI038
TDCI038
Monolithic Video AID Converter
8-Bit, 20 Msps, Low Power

Description
The TDC1038 is a flash analog-to-digital converter
capable of converting a video-speed signal into a stream
of 8-bit digital words at 20 Msps (MegaSampies Per
Second). It is pin-for-pin compatible with the industry
standard TDC1048 but uses half the power. Since the
TDC1038 is a flash converter, a sample-and-hold circuit
is not required.
The TDC1038 consists of 255 clocked latching
comparators, combining logic, and an output register. A
single convert clock controls the conversion operation.
The unit can be configured to give either true or inverted
outputs, in binary or offset two's complement coding. All
digital 1/0 is TIL compatible.

Features
•
•
•
•
•

8-bit resolution
DC to 20 Msps conversion rate
7 MHz full-power bandwidth
30 MHz small signal -3 dB bandwidth
112 LSB linearity

Pin Assignments

700 mW power dissipation
+5V, -5V (or -5.2V) supply operation
Low cost
Drop-in replacement for TDC1048
Sample-and-hold circuit not required
Analog input range 0 to -2V
Differential phase 0.30
Differential gain 0.7%
Selectable data format
Available in plastic DIP, CERDIP, and PLCC

Applications
•
•
•
•
•
•
•

Digital television
Electronic warfare
Low power upgrade for TDC1 048
Video digitizing
Medical imaging
High energy physics
Low cost, low power, high-speed data conversion

c

°

1(MSB)
02
03
04
0GNO
VCC
VEE
VEE
VEE
VCC
0GNO
NLiNV
05
06

•
•
•
•
•
•
•
•
•
•

1

6
7
8

9
10
11
12
13
14

~

28
27
26
25
24
23
22
21
20
19
18
1 17
] 16
] 15
'--------'

t§u ~u ~u

tnoo::t"MN..-OO>
NNNNNC'I..~

18
17
16
15
14
13
12

For More Information call 1-800-722-7074.

RT
CONY
08(LSB)

Dr
06
05
NLiNV

cowwwoo

zowwWoz

0>

c

1038.B6.28PIN
1038.N6.28PIN

" 86 Package
28 Pin CEROI~28 Pin Plastic~DIP - N6 Package

c

t5

cl:z:>z>zoet

NMINV
RM
R8
AGNO
NC
VIN
NC
VIN
NC
AGNO
RT
CONY
08(LSB)
07

> > > >

C)

c

1038.R3.28PIN

28 Lead Plastic J-Leaded Chip Carrier - R3 Package

Raytheon Semiconductor

3-25

I

TDCI038
Functional Block Diagram
NMINV
NLiNV
CONY
VIN
RT

)>---------------------,

>--------------------,1

>--------,-----,-1--+1--+------,1
r----------,

6

~+-------~,

V
V

R~~+---t--I---+--t...;'
R~
R~

't

v,~

.

i'Jo....~
1,27'>----t-t--.t

R ;;-

...

255 TO 8
ENCODER

f---->..

~

REGISTER

~

~ 0,. 8

~>---f--fl----+t

+----I--+-+--t.....
v

'~
R

--""

'~

.~

1254'>_--f--f1----+t

t--t---t--t-l/

R~,?-t---t---t---t
~>_--4-~
........
R2

~

'----:D':'::IFF::::E':':RE~NT~IA~L--.....

RM>-t===~-I

,

COMPARATORS
(255)

Functional Description

Power

General Information

The TOC1038 operates from two supply voltages: +5.0V
and -5.0V. -5.2V may be used with a slight increase in
power dissipation. The return path for ICC. the current
from the +5.0V supply is 0GND. The return for path lEE,
the current from the -5.0V supply, is AGND. All power
and ground pins must be connected.

The TDC1038 has three functional sections: a
comparator array, encoding logic, and output
registers. The comparator array compares the
input signal with 255 reference voltages to
produce an N-of-255 code (or thermometer
code, since all the comparators whose reference
is more negative than the input signal will be on,
and all those whose reference is more positive
will be off). The encoding logic converts the
N-of-255 code into the user's choice of coding.
The output register holds the output constant
between updates.

3-26

1038.Fsn

Reference
The TOC1038 converts analog signals in the range
VRB::;\!IN::;\!RT into digital form. The specifications of the
TOC1038 are guaranteed with VRT, (the voltage applied
to the top of the reference resistor chain) at 0.0±0.1V
and VRB (the voltage applied to the bottom of the
reference resistor chain) at -2.0±0.lV.

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

TDCI038
Linearity is guaranteed with no adjustment; however, a
midpoint tap, RM, allows trimming of converter integral
linearity as well as the creation of a nonlinear transfer
function. This is explained in the Application Note TP-19
"Non-Unear AID Conversion." The circuit shown in
Figure 6 will provide approximately a 1(2 LSB adjustment of the linearity at midscale. The characteristic
impedance seen at this node is approximately 200 ohms
and should be driven from a low-impedance source.
Note that any load applied to this node will affect
linearity, and any noise introduced at this point will
degrade the overall quantization SNR. Due to the slight
variation in the reference current with clock and input
signals, Rr and RB should be low-impedance-to-ground
points. For circuits in which the reference is not varied, a
bypass capacitor (0.0 to 0.1 pF) to ground is recommended. If the reference inputs are exercised dynamically (as in an automatic gain control circuit) a lowimpedance reference source is required. The reference
vottages may be varied dynamically up to 5 MHz;
however, device performance is specified with fixed
reference voltages as defined in the Operating Conditions Table.

Convert
The TDC1038 requires extemal convert (CONV) signal.
Because the TDC1038 is a flash converter it does not
require a track-and-hold circuit. A sample is taken (the
outputs of the comparators are latched) within tSTO
(Sampling Time Offset) after a rising edge on the CONV
pin. The resutt is encoded and then transferred to the
output registers on the next rising edge. The digital
output for sample N becomes valid tD after the rising
edge of clock N+ 1 and remains valid until tHO after the
rising edge of clock N+2. (See Figure 1, Timing Diagram.)

Output Format Control
Two output format control pins, NMINV and NLlNV, are
provided. These controls are for DC (i.e., steady state)
uses. They permit the output coding to be either straight
binary or offset two's complement, in either true or
inverted sense, according to the Output Coding Table.
These active LOW pins may be tied to Vee (through a
4.7 kOhm resistor) for a logic 1 or DGND for a logic O.

Outputs

Analog Input
For precise quantization, the TDC1038 uses latching
comparators. For optimum overall system performance
the source impedance of the driving circuit must be less
than 25 ohms. If the input signal is between the VRT and
VRB references, the output will be a binary number from
to 255. When a signal outside the recommended input
voltage range (0 to -2V) is applied, the output will remain
at either full-scale value. The input signal will not damage
the TDC1 038 if it remains within the range specified in
the Absolute Maximum Ratings Table. Both analog
input pins are connected together intemally and therefore either one or both may be used.

o

For Mora Information call 1-800-722-7074.

The outputs of the TDC1 038 are TIL compatible, capable
of driving four low-power Schottky TIL (54/74 LS) loads
or equivalent. The outputs hold the previous data for a
minimum of tHO after the rising edge of the CONVert
signal.

Not Connected
There are several pins that have no intemal connection to
the chip. They should be left open.

Raytheon Semiconductor

3-27

I

TDCI038
Package Interconnections
Signal
Type

Signal
Name

Value

86, N6, R3 Package Pins

Power

VCC
VEE
AGNO
OGNO

~igital

Supply Voltage
Analog Supply Voltate
Analog Ground
~igital Ground

+5.0V
-5.0V
O.OV
O.OV

6,10
7,8,9
19,25
5, 11

Reference

RT
RM
RB

Reference Resistor (Top)
Reference Resistor (Middle)
Reference Resistor (Bottom)

O.OV
-1.0V
-2.0V

18
27
26

Function

Analog Input

VIN

Analog Signal Input

Convert

CONV

Convert

OVto-2V
TTL

17

Format Control

NMINV
NLiNV

Not Most Signficant Bit Invert
Not Least Significant Bit Invert

TTL
TTL

28
12

Data Output

01
02
03
04
05
06
07
08

Most Significant Bit Output

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

1
2
3
4
13
14
15
16

Not Connected

NC

Not Connected

Least Significant Bit Output

21,23

Open

20,22,24

Figure 1. Timing Diagram

1
0(

CONV

F~

Y'g-NA-MP-L-E~\

-Ii

.

---··;...1-T
1
tpWH
SAMPLE

'1

N+l

tPWL

--1

\.

I'

l~-SA-MP-L-E---..\

1 N+2

/

\

'---_---J

ANALOG INPUT

3-28

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI038
Figure 2. Simplified Input Circuits

V'":"U·8~Nt
VEEA

VRS

V1
VEE

CIN IS A NONLINEAR JUNCTION CAPACITANCE
VRS IS A VOLTAGE EQUAL TO THE VOLTAGE ON PIN RS

REFERENCE
RESISTOR
CHAIN

VEE
1038.2

Figure 4. Output Circuit

Figure 3. Convert Input Equivalent Circuit

Vcc

_---1--~--O VCC

Vcc~~--------~--------~--

~

__--+--t__+-.:o0UTPUT

8l0n
TO
OUTPUT
PIN "'"""1r----Mt---i

INPUT ~+--+-----,..--'

lN3062

40pF
LOAD 1
TEST LOAD
FOR DELAY
MEASUREMENTS

OUTPUT EQUIVALENT
CIRCUIT

1038.3

1038.4

Output Coding Table
Binary

Offset Two's Complement
True
Inverted

True

Inverted

Input
Voltage

NMINV=HIGH
NLlNV=HIGH

NMINV=LOW
NLlNV=LOW

NMINV=LOW
NLlNV=HIGH

NMINV:HIGH
NLlNV=LOW

O.OOOOV
..(J.0078V

0000 0000
0000 0001

1111 1111
1111 1110

10000000
10000001

0111 1111
01111110

·

·

..(J.9922V
-1.0000V
-1.0078V

01111111
1000 0000
1000 0001

·
·
-1.9844V

·
·
1111 1110

-1.9922V

1111 1111

··

Notes:

.
10000000
0111 1111
0111 1110

.

0000 0001
0000 0000

·
·
·
1111 1111
0000 0000
0000 0001

.

0000 0000
11111111
11111110

·
01111110
0111 1111

1000 0001
1000 0000

1.

NMINV and NLiNV are to be oonsidered DC oontrols. They may be tied to +5V for a logic 1 or tied to ground for a logic O.

2.

Voltages are oode midpoints.

For More Information call 1-800-722-7074.

Raytheon semiconductor

3-29

I

TDCI038
Absolute maximum ratings (beyond which the device may be damaged) 1
Supply Voltag..
vee (measured to DGNO) ......................................................................................................................-C.5 to +7JN
VEE (measured to AGNO) .............:......................................................................................................... +0.5 to -7JN
AGNO (measured to DGNO) .................................................................................................................... -C.5 to +0.5V
Input VoItag.. 2
CONV, NMINV, NLiNV .................................................................................................................. -C.5 to lVcc+0.5V)
VIN, VRT, VRB (measured to AGNol ...................................................................................................••.•VEE to +0.5V
VRT (measured to VRB) ..........................................................................................................................-2.2 to +2.'lII
Input CUrrants 3
CONV, NMINV, NLiNV ........................................................................................................................-50 to +50 rnA
VIN, VRT, VRB ................................................................................................................................................-100 to +100 rnA

Output
Applied voltage (measured to DGNO) ..........................................................................................-C.5 to lVee+o.5V)2
Applied current, extemally forced .....................................................................................................-20 to +20 rnA 3
Short-circuit duration (single output in HIGH state to ground)

Temperatur.
Operating, ambient (all packages except N6 and R3 ............................................................................ -55 to +1250(;
(N6 and R3 packages only) .....................................................................................................-20 to +900c
junction (all packages) .................................................................................................................... +1750(;
Lead, soldering. all packages (10 seconds) .................................................................................................... +3000(;
Storage, all packages ...........................................................................................................................-65 to +1500(;

Notes:

3-30

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified
operating conditions. Functional operation under any of these conditions is NOT implied. A condition applied individually that exceeds the Operating Conditions specification but is less than the Absolute Meximum Ratings will not
cause immediate device failure.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI038
Operating Conditions
Temperature Range
Standard
Extended
Min Nom
Max
Min Nom

Parameter

Max

Units

5.50
-5.50
0.1

V
V
V
ns
ns
V
V
mA

Vee
VEE
VAGNO
tPWL
tPWH
VIL
VIH
IOL
IOH
VRT
VRB
VRT-VRB
VIN
TA

Digital Supply Voltage
Analog Supply Voltage
Analog Ground Voltage (Measured to DGNO)
CONVert Pulse Width, LOW
CONVert Pulse Width, HIGH
Input Voltage, Logic LOW
Input Voltage, Logic HIGH
Output Current, Logic LOW
Output Current, Logic HIGH
Most Positive Reference Input 1
Most Negative Reference Input 1
Voltage Reference Differential
Input Voltage
Ambient Temperature, Still Air

Note:

1. VRT must be more positive than VRB, and voltage reference differential must be within specified range.

4.75
-4.9
-0.1
18
22

5.0
-5.0
0.0

5.25
-5.50
0.1

4.50
-4.9
-0.1
18
22

5.0
-5.2
0.0

0.8
2.0

-0.1
-1.9
1.8
VRB
0

0.8
2.0

0.0
-2.0
2.0

4.0
-400
0.1
-2.1
2.2
VRT
70

-0.1
-1.9
1.8
VRB
-55

0.0
-2.0
2.0

4.0
-400
0.1
-2.1
2.2
VRT
125

J.IA
V
V
V
V

"C

Thermal characteristics (approximate)
Parameter
Bja

Thermal Resistance, Junction to Ambient

Nom

Max

Min

B6

50
45
65

"CIW
"CIW

"CIW

12
17
14

"CIW
"CIW

N6

R3

8jc

Thermal Resistance, Junction to Case

B6
N6

R3

For More Information call 1-800-722-7074.

Raytheon Semiconductor

"CIW

3-31

I

TDCI038
Electrical characteristics within specified operating conditions
Temperabn Range
Standard

Test Conditions

Parameter

ICC
lEE
IREF
RREF
RIN
CIN
ICB
IlL
IIH
II
VOL
VOH
lOS

Positive Supply Current
Negative Supply Current
Reference Current
Total Reference Resistance
Input Equivalent Resistance
Input Capacitance
Input Constant Bias Current
Input Current Logic LOW
Input Current. Logic HIGH
Input Current. Max Input Voltage
Output Voltage. Logic LOW
Output Voltage. Logic HIGH
Short-Circuit Output Current

CI

Digital Input Capacitance

Note:

Min

Vcc=Max1
VEE=Max 1
VRT. VRB=Nom

Max

Extended

Min

35
-170
30

67
80
VRT. VRB=Nom. VIN=VRB
VRT. VRB-Nom. VIN-VRB
VCCA=Max
VCC=Max. VI=0.4V
-200
VCC=Max. VI-2.4V
VCC-Min. 10L=Max
VCC=Min. 10L=Max
2.4
Vcc=Min. 10H-Max
VCC=Max. Output HIGH. one pin to
ground. one second duration max
TA=25"C. F=l MHz

Max
35
-170
50

40

40
50

50
500
-{l.6

250
-{l.6

50

-400

50

1.0
0.5

1.0
0.5

Units
rnA
rnA
rnA
Ohms
kOhms
pF
~

rnA
~

-40

-40

rnA
V
V
rnA

15

15

pF

2.4

1. Worst case. all digital inputs and outputs LOW.

Switching characteristics within specified operating conditions
Temperature Range
Standard
Parameter

FS

Test Conditions

Maximum Conversion Rate

20
-2

tsTo Sampling Time Offset

to
tHO

3-32

Output Delay
Output Hold Time

Min

Vcc=Min. Load 1. Figure 4
Vcc=Min. Load 1. Figure 4

Raytheon Semiconductor

5

Max
10
30

Extended

Min
20
-2
5

Max

Units

10
35

Msps
ns
ns
ns

For More Information caJI1-800-722-7074.

TDCI038
System performance characteristics within specified operating conditions

Parameter

Test Conditions

Linearity Error Integral, Independent
ELI
ELD Linearity Error Differential
Code Size
Cs
EaT Offset Error, Top
EOB Offset Error, Bottom
TCO Offset Error, Temperature Coefficient
BW Bandwidth, Full-Scale Input
BWSS -3 dB Bandwidth, Small Signal
tTR Transient Response, Full Scale
SNR Signal-to-Noise Ratio

VRT, VRB=Nom

Peak SignaVRMS Noise
RMS Signal/RMS Noise
Aperture Error
Differential Phase Error
Differential Gain Error

EAP
DP
DG

Temperature Range
Standard
Extended
Min
Max
Min
Max

25
VIN=VRT
VIN=VRB
No Spurious or Missing Codes
-20 dBFS Input
10 MHz Bandwidth,
20 Msps Conversion Rate
1.248 MHz Input
2.438 MHz Input
1.248 MHz Input
2.438 MHz Input

0.2
0.2
175
+15
-15
±20

0.2
0.2
175
+15
-15
±20

25

7
30
40

7
30
40

54

53

53

52

45

44

44

43

60
1.0
2.0

FS=4x NTSC
FS=4x NTSC

60
1.0
2.0

Units
0/0
0/0
0/0 Nom
mV
mV
JlVrC
Mhz
MHz
ns

dB
dB
dB
dB
ps
Degree
0/0

Figure 5. Typical Interface Circuit
+5V
CONY
INPUT

0.1~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-,

~

~

10

2.2K
+5V

2K
O2
03

1K
75Q
17
VIDEO@,...-.._----.JV1I1\r--+---'-f:"%O
INPUT
81
>---_+_---J\IV'It--_....=f VIN

04
05

VIN
TDC1038

18
27
26

06

AGND

Dr

AGND

08 (LSS)

Rr

DGNO

RM

DGi"lD

4

13
14
15
26

RS

0.1
24K

(0.1
2N2907

·5V

1 i

·5V

For More Information caJI1-800-722-7074.

·5V

Raytheon Semiconductor

21390A

3-33

I

TDCI038
Figure 6. Optional Midscale Linearity Adjust

Figure 7. Typical SINAD IfS. k,p,'t Frequency

-----

50

45
R
>--.......:M""

.

III

'C

TDC1038

40

Q

c(

z

iii

-......... .......

..........

r--....

~

CLOCK RATE = 20MSPS
INPUT SIGNAL = -O.ldB FU LSCAL

35

RB

-2V --~--------.:::=..J
1038.6

30
2345678
INPUT FREQUENCY - MHz

Typical Interface Circuit
The Typical Interface Circuit (Figure 5) shows a wideband operational amplifier driving the AID converter
directly. Bipolar inputs to the op amp can be accommodated by adjusting the offset control. Raytheon
Semiconductor's TDC4611 provides a stable reference
for the offset and gain controls. All VIN pins are connected close to the device package and the input
amplifier's feedback loop should be closed at that point.

1038.7

The buffer has an inverting gain of two, increasing a lVpp video input signal to the recommended 2Vp-p input for
the TDCl 038. Proper decoupling is recommended for all
systems.
The bottom reference voltage (VRB) is supplied by an
inverting amplifier or the TDC4611, buffered with a PNP
transistor. The transistor provides a low-impedance
source and is necessary to sink the current flowing
through the reference resistor chain.

Ordering Information

40G06121

3-34

Product
Number

Temperature Range

Screening

TDC1038B6C
TDC1038B6V
TDC1038N6C
TDC1038R3C

STD - TA =OOC to 700C
EXT - TC =-55OC to 1250C
STD - TA =OOC to 700C
STD - TA =OOC to 700C

Commercial
MIL-STD-883
Commercial
Commercial

Package
28-Pin CERDIP
28-Pin CERDIP
28-Pin Plastic DIP
28-Lead Plastic J-Leaded Chip Carrier

Package
Marking
1038B6C
1038B6V
1038N6C
1038R3C

Rev 0 8/93

Raytheon Semiconductor

For Mora Information call 1-800-722-7074.

TDCI044
TDCI044
Monolithic Video AID Converter
4-Bit, 25 Msps

Description

Features

The TDC1044 is a 25 Msps (Megasample per second)
full-parallel analog-to-digital converter, capable of
converting an analog signal with fUll-power frequency
components up to 12.5 MHz into 4-bit digital words. Use
of a sample-and-hold circuit is not necessary for
operation of the TDC1044. All digital inputs and outputs
are TIL compatible.

•
•
•
•
•
•

The TDC1044 consists of 15 latching comparators,
encoding logic, and an output register. A single convert
signal controls the conversion operation. The unit can
be connected to give either true or inverted outputs in
binary or offset two's complement coding.

Applications
•
•
•
•

4-bit resolution
1/4 LSB non-linearity
Sample-and-hold circuit not required
25 Msps conversion rate
Selectable output format
Available in a 1S-pin DIP and a 20-lead PLCC

Video special effects
Radar data conversion
Medical imaging
Medical processing

Functional Block Diagram
NMINV
NUNV

I

CONY

RT

;---

~
.
~

R,

R

R

R

R
,~

R

R

liz

I

I I I

•
•

•

•
•
•

••
•

~

:
•

':\

~
~

r--'--

•
•
•

15 TO'
ENCODER

•
•

•

~

~

LATCH

~

'----

DIFfERENTIAL
COMPARATORS 1151

RS

'----REFERENCE
RESISTOR
CHAIN

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-35

I

TDCI044
Pin Assignments

= t:::

Reference

< <

~ ~ ~

NC l U E J 1 3 Vee
CONV 20
12 NMiNV

Ao.o

1

11 RM

VII

2

10 NUNV

NC3

UNC

Ji"lElEa!'JI

..-

20 Lead PLCC - R4 Package
AGNO 1

>7

VII 2

NC 3

Rr

4
RB 5
VEE 8
NLiNV 7
R,. 8

24 CONY
23 D.(LSB)

22

Os

21
20
19
18
17

D2
Dl(MSB)

i>GHo
Vee
NMINV

16 Pin DIP - B9 Packaga
16 Pin Plastic DIP - N9 Package

......7

Functional Description
General Information
The TOC1044 has three functional sections: a comparator
array, encoding logic, and an output register. The
comparator array compares the input signal with 15
reference voltages to produce an N-of-15 code
(sometimes referred to as a "thermometer" code, as all
the comparators referred to voltages more positive than
the input signal will be off, and those referred to
voltages more negative than the input signal will be onl.
The encoding logic converts the N-of-15 code into binary
or two's complement coding, and can invert either
output code. This coding function is controlled by DC
signals on pins NMINV and NLiNV The output register
holds the output constant between updates.

Power
The TOC1044 operates from two power supply voltages,
+ 5.0V and - 5.2V. The return for ICC (the current
drawn from the + 5.0V supplYI is DGND. The return for
lEE (the current drawn from the -5.2V supplYI is AGND.
All power and ground pins must be connected.

3-36

The TOC1044 converts analog signals in the range
VRB VIN VRB into digital form. VRB (the voltage
applied to RB at the bottom of the reference resistor
chainl and VRT (the voltage applied to RT at the top of
the reference resistor chainl should be between + 0.1V
and. -1.1 V VRT should be more positive than VRB
within that range. The voltage applied across the
reference resistor chain (VRT-VRBI must be between
OAV and 1.3V The nominal voltages are VRT=O.oOV
and VRB = -1.00V These voltages may be varied
dynamically up to 10MHz. Due to slight variation in the
reference currents with clock and input signals, RT and
RB should be low-impedance points. For circuits in which
the reference is not varied, a bypass capacitor to ground
is recommended. If the reference inputs are varied
dynamically (as in an Automatic Gain Control circuit!. a
low-impedance reference source is required. A reference
middle, RM, is also provided; this may be used as an
input to adjust the mid-scale point in order to improve
integral linearity. This point may also be used as a tap to
supply a mid-scale voltage to offset the analog input. If
VRM is used as an output, it must be connected to a
high input impedance device which has small input
current. Noise at this point may adversely affect the
performance of the device.

Controls
Two function control pins, NMINV and NLiNV are
provided. These controls are for DC (i.e., steady statel
use. They permit the output coding to be either straight
binary or offset two's complement. in either true or
inverted sense, according to the Output Coding Table.
These pins are active LOW as signified by the prefix "N"
in the signal name. They may be tied to VCC for a logic
"1" and DGND for a logic ''0:'

Convert
The TOC1044 requires a CONVert (CONVI signal. A
sample is taken (the comparators are latchedl within
tSTO after a rising edge of CONV. The coded result is
translated to the output latches on the next rising edge.
The outputs hold the previous data a minimum time
(tHol after the rising edge of the CONV signal. New
data becomes valid after a maximum delay time, to.

Raytheon Semiconductor

For Mora Information call 1-800-722-7074.

TDCI044

Outputs

Analog Input
The TOC1044 uses latching comparators which cause
the input impedance to vary slightly with the signal level.
For optimal performance, the source impedance of the
driving circuit must be less than 25 Ohms. The input
signal will not damage the device if it remains within
the range of VEE to + 0.5V. If the input signal is at a
voltage between VRT and VRB, the output will be a
binary code between 0 and 15 inclusive. A signal
outside this range will indicate either full-scale positive
or full-scale negative, depending on whether the signal
is off-scale in the positive or negative direction.

The outputs of the TOC1044 are TTL compatible, and
capable of driving four low-power Schottky TTL (54174
LS) unit loads. The outputs hold the previous data a
minimum time (tHO) after the rising edge of the CONV
signal. Data becomes valid after a maximum delay time
(to) after the rising edge of CONV. For optimum performance' 2.2 kOhm pull-up resistors are recommended.
No Connects

Pin 3 of the TOC1044 is labeled No Connect (NC), and
has no connection to the chip. Connect this pin to AGNO
for best noise performance.

Package Interconnections
Signal
Type
Power

Reference

Controls
Convert
Analog Input
Outputs

No Connects

Signal
Name
Vee
VEE
DGND
AGND
RT
RM
RB
NMINV
NLiNV
CONV
VIN

0,
02
03
04
NC

For More Information call 1-800-722-7074.

Function
Positive Supply Voltage
Negative Supply Voltage
Digital Ground
Analog Ground
Reference Resistor, Top
Reference Resistor, Middle
Reference Resistor, Bottom
Not MSB Invert
Not LSB Invert
Convert
Analog Input Signal
MSB Output

LSB Output
No Connect

Value
+5.OV

-5.'N
O.OV
O.OV
O.OV

.fJ.fN
-LOV
TIL

m
TIL
OVto-1V
TIL
TIL
TIL

m
AGND

Raytheon Semiconductor

89, N9 Package
Pins
10
6
11
1
4
8
5
9
7
16
2
12
13
14
15
3

R4 Package
Pins
13
8
14
1
4
11
7
12
10
20
2
15
16
17
18
3,5,6,9,19

3-37

I_

TDCI044
Figure 1. Timing Diagram

DIGITAL OUTPUT

Figure 2. Simplified Analog Input Equivalent Circuit

---+------+------.

VIN 0-.....

1-0F-15
COMPARATORS

I
REFERENCE
RESISTOR
CHAIN

Figure 3. Digital Input Equivalent Circuit

Figure 4. Output Circuits
+VCC

VCC o---~~----~~-

-.-_-..()VCC

20K

S10n

15K

TO
OUTPUT 0-"""'1~-M-"
PIN

INPUT

......-4~-(l OUTPUT

OUTPUT EQUIVALENT
CIRCUIT

3-38

Raytheon Semiconductor

lN3062

LOAO 1
'::'
TEST LOAO FOR DELAY
MEASUREMENTS

For More Information call 1-800-722-7074.

TDCI044
Absolute maximum ratings (beyond which the device may be damagedl 1
Supply Voltages
VCC (measured to 0GNO) .......................................................................................................................................................................................... -0.5 to +l.OV
VEE (measured to AGNO) ........................................................................................................................................................................................... +0.5 to -l.OV
AGNO (measured to 0GNO) ...................................................................................................................................................................................... -0.5 to +0.5V

Input Voltages
CONY, NMINV, NLiNV (measured to 0GNO) ......................................................................................................................................................... -0.5 to +5.5V
VIN, VRT, VRB (measured to AGNO) ........................................................................................................................................................................ +0.5 to VEEV
VRT (measured to VRB) ............................................................................................................................................................................................. -2.2 to +2.2V
Output
Applied voltage (measured to 0GNO) ................................................................................................................................................................... -0.5 to +5.5V 2
Applied current. externally forced .................................................................................................................................................................... -1.0 to +6.0mA3,4
Short circuit duration (single output in high state to ground) ............................................................................................................................................ 1 sec
Temperature
Operating, ambient .................................................................................................................................................................................................... -55 to +125'C
junction .................................................................................................................................................................................................................... +150'C
Lead, soldering (10 seconds) .................................................................................................................................................................................................. +300'C
Storage ................................................................................................

............................................................................................ -65 to + 150'C

Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as positive when flowing into the device.

Operating conditions
Temperature Range
Parameter

Min

Standard
Nom

Max

Min

Extended
Nom

Max

Units

VCC

Positive Supply Voltage (Measured to 0GNO)

4.75

5.0

5.25

4.5

5.0

5.5

V

VEE

Negative Supply Voltage (Measured to AGNO)

-4.9

-5.2

-5.5

-4.9

-5.2

-5.5

V

VAGNO

Analog Ground Voltage (Measured to 0GNO)

-0.1

0.0

0.1

-0.1

0.0

0.1

V

tpWL

CONY Pulse Width, LOW

tpWH

CONY Pulse Width, HIGH

VIL

Input Voltage, Logic LOW

VIH

Input Voltage, Logic HIGH

17

17

ns

17

17

ns

0.8

0.8

V
V

2.0

2.0

Output Current, Logic LOW
Output Current, Logic HIGH

VRT

Most Positive Reference

-1.9

0.0

0.1

-1.9

0.0

0.1

V

VRB

Most Negative Reference

-2.1

-1.0

-0.1

-2.1

-1.0

-0.1

V

VRrVRB

Reference Oifferential

0.2

1.0

2.0

0.2

1.0

2.0

V

VIN

Input Voltage

TA

Ambient Temperature, Still Air

TC

Case Temperature

For More Information call 1-800-722-7074.

4.0

2.0

rnA

IOL
IOH

-400

VRB
0

Raytheon Semiconductor

VRT

-400

f.lA

VRB

VRT

V

-55

125

'c
'c

70

3-39

I

TDCI044
Electrical characteristics within specified operating conditions

Parameter

Test Conditions
Posnive Supply Current
Negative Supply Current

ICC
lEE

Temperature Range
Standard
Extended
Min
Max
Min
Max
15

VCC - MAX, static 1
VEE ~ MAX, static 1
TA ~ O°C to lO°C
TA ~ lO°C
TC ~ -55°C to 125°C
TC ~ -125°C

IREF
RREF

Reference Current
Total Reference Resistance

VRT' VRB ~ NOM

RIN
CIN

Input Equivalent Resistance
Input Capacitance

VRT' VRB ~ NOM, VIN ~ VRB

ICB
III

Input Constant Bias Current
Input Current, logic lOW

VEE
VCC

IIH
II

Input Current, logic HIGH
Input Current, Max Input Voltage

VCC - MAX, VI - 2.4V
VCC ~ MAX, VI ~ 5.5V

VOl
VOH

Output Voltage, logic lOW
Output Voltage, logic HIGH

VCC - MIN, 10l - MAX
VCC = MIN, 10H = MAX

lOS

Short Circuit Output Current

VCC = MAX, One pin to ground, one second
duration, Output HIGH.

CI

Oigital Input Capacnance

TA = 25°e, F ~ lMHz

~
~

20

rnA

-65
-35

rnA
rnA
rnA
rnA

-50
-40

2

2

500

500

300

100

MAX
MAX, VI - 0.5V CONV
NMINV, NliNV

Units

rnA
Ohms
kOhms
pF

25

25

25
-0.4
-0.6
50
1.0

50
-0.6
-0.8
50
1.0

flA
rnA
rnA

0.5

V
V

0.5
2.4

2.4

flA
rnA

-30

-30

rnA

15

15

pF

Note:
1. Worst case: all digital inputs and outputs lOW

Switching characteristics within specified operating conditions

Parameter
FS
tSTO
to
tHO

3-40

Maximum Conversion Rate
Sampling Time Offset
Digital Output Delay
Digital Output Hold Time

Test Conditions
Vce
VCC
VCC
VCC

-

MIN, VEE =
MIN, VEE MIN, VEE =
MAX, VEE -

MIN
MIN
MIN, load 1
MAX, load 1

Raytheon Semiconductor

Temperature Range
Standard
Extended
Min
Max
Min
Max
25

25
15
35

10
30

5

5

Units
MSPS
ns
ns
ns

For More Information caJI1-800-722-7074.

TDCI044
System performance characteristics within specified operating conditions

Parameter

Temperature Range
Extended
Standard
Min
Max
Min
Max

Test Conditions
VRB

CS

Code Size

VRT, VRB

EOT
EOB
TCO

Offset Error Top
Offset Error Bonom
Offset Error Temperature Coefficient

BW

Bandwidth, Full Power Input

tTA

Transient Response, Full Scale

10

10

ns

EAP

Aperture Error

30

30

ps

ELI
ELO

~

NOM

Units

linearity Error Integral, Independent
linearity Error Oifferential

~

1.6
1.6
NOM

75

125

1.6
1.6
75

+30
+40
±20

VIN - VRT
VIN ~ VRB
12.5

%
%

125

% Nominal

+30
+40
±20

mV
mV

12.5

/lV/'C
MHz

Output Coding Table 1
Binary

Offset Two's
Complement
True
Inverted

Range

True

Inverted

-1.00V FS

NMINV ~ 1
NLiNV ~ 1

0
0

0
1

1
0

O.OOOV
-0.067V
-0.133V
-0.200V
-0.267V
-0.333V
-O.40OV
-0.467V
-0.533V
-0.600V
-0.667V
-0.733V
-O.BOOV
-0.B67V
-0.933V
-1.000V

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000

1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111

0111
0110
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000

Note:
1. Input voltages are at code centers.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-41

I

TDCI044
Calibration
To calibrate the TDC1044, adjust VRT and VRB to set
the 1st and 15th thresholds to the desired voltages.
Assuming a OV to -lV desired range, continuously
strobe the converter with - 0.0033V (1/2 LSB from
O.OOOV) on the analog input, and adjust VRT for output
toggling between codes 0000 and 0001. Then apply
- 0.967V (1/2 LSB from -1.000V) and adjust VRB for
toggling between codes 1110 and 1111. Instead of
adjusting VRT, RT can be connected to analog ground
and the OV end of the range calibrated with an amplifier
offset control. RB is a convenient point for gain
adjustment that is not in the analog signal path.

gain factor of -1. A small value resistor, R12, serves to
isolate the small input capacitance of the AID converter
from the amplifier output and insure frequency stability.
The pulse and frequency response of the amplifier are
optimized by variable capacitor C12. The reference
voltage for the TDC1044 is generated by amplifier U3.
System gain is adjusted by varying R9 which controls the
reference voltage level to the AID converter.
Input voltage range and input impedance for the circuit
are determined by resistors Rl and R2. Formulas for
calculating values for these input resistors are:

Typical Interface Circuit

Rl

The TDC1044 does not require a special input buffer
amplifier to drive the analog input because of its low
input capacitance. A terminated low-impedance
transmission line « 100 Ohms) connected to the VIN
terminal of the device is sufficient if the input voltage
levels match those of the AID converter.
However, many driver circuits lack sufficient offset
control, drive current, or gain stability. The Typical
Interface Circuit in Figure 5 shows a simple amplifier
and voltage reference circuit that may be used with the
device. U2 is a wide-band operational amplifier with a

3-42

=

(~~~)

1060

and
1000 Rl )
R2 = liN - ( 1000+Rl
where VR is the input voltage range of the circuit, liN is
the input impedance of the circuit, and the constant
1000 comes from the value of R3. As shown, the circuit
is set up for lVp-p 75 Ohm video input.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

IDCI044
Figure 5. Typical Interface Circuit
+5V

R13
21K
01 (MSBI
VIDEO INPUT
IV p-p

ct

12

Rl
37.4

R14
2.2K
~

R2
39.2

13
R15
21K

R7
lK

R9
2K
10-TURN
"GAIN"

.1

C7
0.1 ~
50V

CLK
-5.2V

RB
2K
10-TURN
"OFFSET"

R6
2K

'J

14

CB

0.1
50V

RIO
10K

Rll
10K

)--------------+--------+--------'

>-------------.....- - - - - -.....------------~..........,

Ordering Information
Product

Temperature Range

Screening

Package

Package
Marking

STD - TA = O"C to 7O"C
00 - Tc = -55"C to l25"C
STD - TA - O"C to 70"C
STD - TA = O"C to 70"C

Commercial
MIL-STD-883
Commercial
Commercial

l6-Pin DIP
l6-Pin DIP
l6-Pin Plastic DIP
20-Lead PLCC

1044B9C
1044B9V
1044N9C
1044R4C

Number
TDC1044B9C
TDC1044B9V
TDC1044N9C
TDC1044R4C

40001899 Rev E 8/93

For More Information call 1-800-722-7074_

Raytheon Semiconductor

3-43

I

TDCI044

3-44

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI046
TDCI046
Monolithic Video AID Converter
6-Bit, 25 Msps

Description

Features

The TDC1046 is a 25 Msps (Megasample per second)
full-parallel (flash) analog-to-digital converter, capable of
converting an analog signal with full-power frequency
components up to 12.5 MHz into 6-bit digital words. Use
of a sample-and-hold circuit is not necessary for
operation of the TDC1 046. All digital inputs and outputs
are m compatible.

•
•
•

•
•
•
•
•
•
•

The TDC1046 consists of 63 clocked latching
comparators, encoding logic, and an output buffer
register. A single convert signal controls the conversion
operation. The unit can be connected to give either true
or inverted outputs in binary or offset two's complement
coding.

6-bit resolution
1/4 LSB linearity
Sample-and-hold circuit not required
m compatible
25 Msps conversion rate
Selectable output format
Available in an 18-pin CERDIP
Low cost
Low analog inut capacitance
Available per Standard Military Drawing

Applications
•
•
•
•
•
•

Low-{X)st video digitizing
Medical imaging
Data acquisition
TV special effects
Video simulators
Radar data conversion

Functional Block Diagram
NMINV } - - - - - - - - - - - - - - - - - - - ,
NLiNV
CONY >-------------1~--_.-t_l;_-___,

>------------------,

>-=::::j::=;=~-r=r----1h

VIN
RT ).

R

R

••
•

63 TO 6
ENCODER

LATCH

R

R

DIFFERENTIAL
COMPARATORS
(63)

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-45

I

TDCI046
Pin Assignments
VIN
Rr
0GNO
NMINV
(MSBIOI
02
03
Vee
VEE

1
2
3
4
5
6
7
8
9

18
17
16
15
14
13
12
11
10

RB
AGNO
°GNO
eONV
06 (LSBI
05
04
NLINV
Vee

within that range. The voltage applied across the
reference resistor chain (VRT - VRBI must be between
0.8V and 1.2V The nominal voltages are VRT= O.OOV and
VRB = -1.00V These voltages may be varied dynamically
up to 12.5MHz. Due to variation in the reference
currents with clock and input signals, RT and RB should
be low-impedance-to-ground points. For circuits in which
the reference is not varied, a bypass capacitor to ground
is recommended. If the reference inputs are exercised
dynamically (as in an Automatic Gain Control circuit), a
low-impedance reference source is required.

Controls
18 Pin CERolP - B8 Package

Functional Description
General Information
The TDC1046 has three functional sections: a comparator
array, encoding logic, and output latches. The comparator
array compares the input signal with 63 reference
voltages to produce an N-of-63 code (sometimes referred
to as a "thermometer" code, as all the comparators
referred to voltages more positive than the input signal
will be off, and those referred to voltages more negative
than the input signal will be onl. The encoding logic
converts the N-of-63 code into binary or offset two's
complement coding, and can invert either output code.
This coding function is controlled by DC signals on pins
NMINV and NLiNV The output latch holds the output
constant between updates.

Power
The TDC1046 operates from two supply voltages, + 5.0V
and - 5.2V The return for ICC, the current drawn from
the + 5.0V supply, is oGNo. The return for lEE, the
current drawn from the -5.2V supply, is AGND. All
power and ground pins must be connected.

Reference
The TDC1046 converts analog signals in the range
VRB ";;;VIN ";;;VRT into digital form. VRB (the voltage
applied to RB at the bottom of the reference resistor
chainl and VRT (the voltage applied to RT at the top of
the reference resistor chainl should be between + O.lV
and -1.1 V. VRT should be more positive than VRB

3-46

Two function control pins, NMINV and NLiNV are
provided. These controls are for DC (i.e., steady statel
use. They permit the output coding to be either straight
binary or offset two's complement in either true or
inverted sense, according to the Output Coding Table.
These pins are active LOW as signified by the prefix "N"
in the signal name. They may be tied to VCC for a logic
"1" and DGND for a logic "0:'

Convert
The TDC1046 requires a CONVert (CONVI signal. A
sample is taken (the comparators are latchedl within 5ns
(tsTOI after a rising edge on the CONV pin. This time is
tSTO, Sampling Time Offset. The 63 to 6 encoding is
performed on the falling edge of the CONV signal. The
coded result is transferred to the output latches on the
next rising edge. The outputs hold the previous data a
minimum time (tHol after the rising edge of the CONV
signal.

Analog Input
The TDC1046 uses strobed latching comparators which
cause the input impedance to vary with the signal level,
as comparator input transistors are cut-off or become
active. For optimal performance, the source impedance of
the driving circuit must be less than 50 Ohms. The input
signal will not damage the TDC1046 if it remains within
the range of VEE to + 0.5V If the input signal is at a
voltage between VRT and VRB, the output will be a
binary number between 0 and 63 inclusive. A signal
outside this range will indicate either full-scale positive
or full-scale negative, depending on whether the signal is
off-scale in the positive or negative direction.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI046I
Outputs
The outputs of the TOC1046 are TTL compatible, and
capable of driving four low-power Schottky TTL 154174
LS) unit loads or the equivalent. The outputs hold the
previous data a minimum time ItHO) after the rising edge

of the CONV signal. Data IS guaranteed to be valid
after a maximum delay time Ito) after the rising edge of
CONV. For optimum performance, 2.2 kOhm pull-up
resistors are recommended.

Package Interconnections
Signal
Type

Signal
Name

Power

vCC
VEE

Function

Value

88 Package Pins

+5.0V
-5.2V

°GNO
AGNO

Positive Supply Voltage
Negative Supply Voltage
Digital Ground
Analog Ground

8, 10
9
3, 16
17

Reference

VRT
VRB

Reference Resistor (Topl
Reference Resistor (Bottoml

O.OV
-1.0V

2
18

Controls

NMINV

Not Most Significant Bit INVert

NLiNV

Not Least Significant Bit INVert

TTL
TTL

4
11

Convert

CONV

Convert

TTL

15

Analog Input

VIN

Analog Signal Input

°1
O2

MSB Output

Outputs

°3
°4
°5
°6

LSB Output

O.OV
O.OV

OV to -lV

1

TTL
TTL
TTL
TTL
TTL
TTL

5
6
7
12
13
14

Output Coding Table 1
Binary
Range

Two's Complement

True

Inverted

True

Inverted

NMINV;l

0
1

0

100000
100001

011111
011110

15.8730mV Step

NLlNV;l

0
0

O.OOOOV
-0.0159V

000000
000001

111111
111110

-0.4921V
-0.5079V

011111
100000
100001

··
·

100000

111111

011111
011110

000000
000001

000000
111111
111110

111110
111111

000001
000000

011110
011111

100001
100000

··
·

-0.5238V

··•

-0.9841V
-1.0000V
Note:

··
·

···

··
·

··
·

··
·

1

··
·
···

1. Voltages are code midpoints when calibrated Isee Calibration sectionl.

For More Infonnation call 1-800·722-7074.

Raytheon Semiconductor

3-47

TDCI046
Figure 1. Timing Diagram

"I- tpwH~tpwLI
I
\,-------,11
'I ~AMPLE \'---_-'ll

Ir==~

~I'I SAMPLE'-

CONV

\.1

SAMPLE
N+l

N+2-

ANALOGINP~U:T-1~N~::::::~~~~~------------~~~

-+__

____________

-l
OIGITAL OUTPUT

I

1

--~~~~~~~~~~~~~~----~~~~~~~--~&

Figure 2. Simpfified Analog Input Equivalent Circuit

VIN

0 -....- - -....- - - - -....- - - . . . . . ,

1-0F-63
COMPARATORS

REFERENCE
RESISTOR
CHAIN

CIN IS A NONLINEAR JUNCTION CAPACITANCE
VR8 IS A VOLTAGE EQUAL TO THE VOLTAGE ON PIN R8

Figure 3. Digital Input Equivalent Circlit

Figure 4. Output Circuits
+VCC

VCC 0-......;..-_....- - - - -....-

-

...-

....-oVCC

22K

810n

15K
TO
OUTPUT 0 -_ _......INPUT

'--.-._-<>

OUTPUT

OUTPUT EQUIVALENT
CIRCUIT

3-48

..

PIN

Raytheon Semiconductor

1N3062

LOAD 1
TEST LOAD FOR DELAY
MEASUREMENTS

For More Information call 1-800·722·7074.

TDCI046
Absolute maximum ratings Ibeyond which the device will be damagedl 1
Supply vohages
vcc Imeasured to 0GNOI .......................................................................................................................................................................................... -0.5 to +7.0V
VEE Imeasured to AGNOI ........................................................................................................................................................................................... +0.5 to -7.0V
AGNO Imeasured to 0GNOI ...................................................................................................................................................................................... -0.5 to +0.5V
Input vohagas
CONY, NMINV, NliNV Imeasured to 0GNOI ......................................................................................................................................................... -0.5 to +5.5V
VIN, VRT' VRB Imeasured to AGNOI ........................................................................................................................................................................... +0.5 to VEE
VRT Imeasured to VRBI ............................................................................................................................................................................................. +1.2 to -1.2V

Output
Applied vo~age Imeasured to 0GNOI ...................................................................................................................................................................... -0.5 to 5.5V2
Applied current, externally forced ....................................................................................................................................................................... -1.0 to 6.0mA3,4
Short circu~ duration Isingle output in high state to groundl ............................................................................................................................................ 1 sec
Temperature
Operating, case .......................................................................................................................................................................................................... -55 to
junction ....................................................................................................................................................................................................................
Lead, soldering 110 secondsl ..................................................................................................................................................................................................
Storage ........................................................................................................................................................................................................................ -65 to

+125°C
+175°C
+300°C
+150°C

Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as positive when flowing into the device.

Operating conditions
Temperature Range
Parameter

Extended

Min

Standard
Nom

Max

5.0
-5.2
0.0

5.25
-5.5
0.1

VCC
VEE
VAGNO

Positive Supply Voltage Imeasured to 0GNOI
Negative Supply Voltage Imeasured to AGNOI
Analog Ground Voltage Imeasured to 0GNOI

4.75
-4.9
-0.1

tPWL
tpWH

CONY Pulse Width ILOWI
CONY Pulse Width IHIGHI

15
17

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

10L
10H

Output Current, Logic LOW
Output Current, Logic HIGH

VRT
VRB
VRr-VRB

Most Positive Reference Input 1
Most Negative Reference Input 1
Voltage Reference Oifferential

VIN

Input Voltage

VRB

VRT

TA
TC

Ambient Temperature, Still Air
Case Temperature

0

70

Min
4.5
-4.9
-0.1

Nom

Max

5.0
-5.2
0.0

5.5
-5.5
0.1

15
17
0.8

V
V

2.0
-0.4

rnA
rnA

0.1
-1.1
1.2

V
V
V

VRB

VRT

V

-55

125

°c

2.0
4.0
-0.4

-0.1
-0.9
0.8

0.0
-1.0

0.1
-1.1
1.2

V
V
V
ns
ns

0.8
2.0

Units

-0.1
-0.9
0.8

0.0
-1.0

Note:
1. VRT must be more positive than VRB' and voltage reference differential must be within specified range.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-49

I

TDCI046
Electrical characteristics within specified operating conditions

Parameter

Test Conditions

ICC

Positive Supply Current

Vcc ~ MAX, static 1

lEE

Negative Supply Current

VEE ~ MAX, static 1
TA

=

Temperature Range
Standard
Extended
Min
Min
Max
Max

-95

O°C to 70°C

~

Reference Current

RREF

Total Reference Resistance

RIN
CIN

Input Equivalent Resistance
Input Capacitance

VRT, VRB ~ NOM, VIN ~ VRB

ICB
IlL

Input Constant Bias Current

VEE - MAX
VCC - MAX, VI ~ 0.5V CONV
NMINV, NLiNV

IIH
II

Input Current, Logic HIGH

VOL

Output Voltage, Logic LOW

VOH

Output Voltage, Logic HIGH

lOS

Short Circuit Output Current

VCC - MAX, One pin to ground,
one second duration, output HIGH

CI

Digital Input Capacitance

TA - 25'C, F - lMHz

Input Current, Logic LOW

Input Current, Max Input Voltage

-150
-75

125'C

IREF

VRT' VRB - NOM
VRT - VRB - MAX

10
100

VCC - MAX, VI - 2.4V
VCC ~ MAX, VI - 5.5V
VCC - MIN, 10L - 2 rnA
VCC ~ MIN, 10H - MAX

15
66

rnA

rnA
rnA
rnA
rnA
Ohms
kOhms

40

40

Units

rnA

-75

TA - 70°C
TC ~ -55'C to 125'C
TC

25

20

30

30

pF

105
-0.4

180
-0.6

pA
rnA

-0.6

-0.8

rnA

50
1.0

50
1.0

pA

0.5

V

0.5
2.4

2.4

rnA

V

-30

-30

15

15

rnA

pF

Note:
1. Worst case, all digital inputs and outputs LOW.

Switching characteristics within specified operating conditions

Parameter

3-50

Test Conditions

FS

Maximum Conversion Rate

Vee ~ MIN, VEE - MIN

tSTO
to

Sampling Time Offset
Output Delay

Vce - MIN, VEE - MIN
Vee - MIN, VEE - MIN, Load 1

tHO

Output Hold Time

Vce - MAX, VEE ~ MAX, Load 1

Raytheon Semiconductor

Temperature Range
Standard
Extended
Min
Max
Min
Max
25

25
5
30

5

5

Units
MSPS

10

ns

35

ns
ns

For More information cail1-800-722-7074.

I

TDCI0461
System performance characteristics within specified operating conditions
Temperature Range
Parameter

Test Conditions
VRT' VRB~Nom

ELI
ELO

Linearity Error Integral, Independent

CS

Code Size

VRT' VRB~Nom

EDT
EOB

Offset Error, Top

VIN~VRT

Offset Error, Bottom

VIN~VRB

TCO

Temperature Coefficient IOffset Voltagel

BW

Bandwidth, Full Power Input

tTR

Transient Response, Full-Scale
Signal-to-Noise Ratio

Extended
Max

Min

0.4
0.4

Linearity Error Differential

SNR

50

150

0.4
0.4
50

+50
-30
±20
12.5

12.5MHz Bandwidth,
25Msps Conversion Rate
1MHz Input
12.5MHz Input
1MHz Input
12.5MHz Input

RMS Signal/RMS Noise

Aperture Error

150

42
40
33
31

%
%
% Nominal
mV

±20

",V/oC

mV

MHz
10

36
32
33
29
30

Units

+50
-30

12.5
10

Peak Signal/RMS Noise

EAP

Standard
Min
Max

ns

dB
dB
dB
dB
30

ps

Calibration
To calibrate the TOCl046, adjust VRT and VRB to set
the 1st and 63rd thresholds to the desired Voltages. In
the Functional Block Diagram, note that Rl is greater
than R, ensuring calibration with a positive voltage on
RT. Assuming a oV to -1V desired range, continuously
strobe the converter with - 0.0079V on the analog
input. and adjust VRT for output toggling between codes
00 and 01. Then apply -0.9921V and adjust VRB for
toggling between codes 62 and 63. Instead of adjusting
VRT, RT can be connected to analog ground and the OV
end of the range calibrated with a buffer offset control.
RB is a convenient point for gain adjust that is not in
the analog signal path. These techniques are employed
in Figure 5.

Interface Circuit (Figure 5) shows a simple buffer
amplifier and voltage reference circuit that may be used
with the TOClo46. U2 is a wide-band operational
amplifier with a gain factor of - 2. A small value
resistor, R12, serves to help isolate the input capacitance
of the AID converter from the amplifier output and
insure frequency stability. The pulse and frequency
response of the buffer amplifier are optimized by variable
capacitor C12.
The reference voltage for the TOCl046 is generated by
amplifier U3 and PNP transistor Ql which supplies the
reference current. System gain is adjusted by varying R9
which controls the reference voltage level to the AID
converter.

Typical Interface Circuit
The TOC1046 does not require a special input buffer
amplifier to drive the analog input because of its low
analog input capacitance. A terminated low-impedance
transmission line «100 Ohms) connected to the VIN
terminals of the TOCl046 is sufficient if the input
voltage levels match those of the AID converter.

Input voltage range and input impedance for the circuit
are determined by resistors Rl and R2. Formulas for
calculating values for these input resistors are:
Rl=

_1_
( 2VR) _
1000
liN

However, many driver circuits lack sufficient offset
control, drive current. or gain control. The Typical
For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-51

TDCI046
Typical Interface Circuit (cont.)

where VR is the input voltage range of the circuit, liN is
the input impedance of the circuit, and the constant
1000 comes from the value of R3. As shown, the circuit
is set up for lVp-p 75 Ohm video input.

and

R2=lIN - (1000 Rl )
1000+Rl
Figure 5. Typical Interface Circuit

+5V>-------------------~~--------~-----------~~------~----------,
L1
FERRITE BEAD
INDUCTOR
e12

05
220

013
2.2K

1-6p'

VIUEOINPUT

@
~

0--1V

O.

03
1K

01
37.4

20

R2

39.2

R7

H6

lK

2K

r------'IIItv-....

eLK

)---------------------f--------t---+----------'

-5.2V >----------------------------<10--......----------------------1

Standard Military Drawing

the sale controlling document defining the SMD product.

These devices are also available as products manufactured, tested, and screened in compliance with Standard
Military Drawings (SMDsl. The nearest vendor equivalent
product is shown below; however, the applicable SMD is

Standard Military
Drawing
5962-87786-01VA

Nearest Equivalent
TRW Product No.

Package

TDC1046B8V

18 Pin CERDIP

Ordering Information
Product
Number

Temperature Range

Screening

Package

Package
Marking

TOC1046BBC
TOC1046BBV

STD-TA=O°C to 70°C
EXT-TC= -55°C to 125°C

Commercial
MIL-STD-BB3

lB Pin CERDIP
lB Pin CERDIP

1046BBC
1046BBV

5962-B7786 OlVA

EXT-TC= -55°C to 125°C

Per Standard Military Drawing

1B Pin CEROIP

5962-B7786 01VA

40001719 Rev F 8/93

3-52

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI0471
TDCI047
Monolithic Video AID Converter
7-Bit, 20 Msps

Description

Features

The TDC1 047 is a 20 Msps (Megasample per second)
full-parallel (flash) analog-tcHiigital converter, capable of
converting an analog signal with full-power frequency
components up to 7 MHz into 7-bit digital words. A
sample-and-hold circuit is not necessary. All digital
inputs and outputs are m compatible.

•
•
•
•
•
•

The TDC1047 consists of 127 clocked latching
comparators, combining logic, and an output buffer
register. A single convert signal controls the conversion
operation. The unit can be connected to give either true
or inverted outputs in binary or offset two's complement
coding.

7-bit resolution
112 LSB linearity
Sample-and-hold circuit not required
20 Msps conversion rate
Selectable output format
Available in 24-pin CERDIP

Applications
•
•
•
•
•

The TDC1 047 is pin and function compatible with
Raytheon Semiconductor La Jolla's TDC1027, and
offers increased performance with lower power
dissipation.

Low-cost video digitizing
Medical imaging
TV special effects
Video simulators
Radar data conversion

Functional Block Diagram
NMINY
NLiNY
CONY
VIN

Ry

I

), I I

....--RI

H;<

R

~

,~

•
•
•

R

R

R

R2

'---

For More Infonnation call 1-800-722-7074.

,~

k<

••
•
IZ7 TO 7
ENCODER

••
•

.
~
:

':l-

~

~

LATCH

~

~

~

R

':l-

:

••
•

'--

DIFFERENTIAl
COMPARATORS
IIZ7I

Raytheon Semiconductor

3-53

TDCI047
Pin Assignments
VIN
Rr
AGNO
°GNO
NMINV
(MSB) 01

1

2
3
4

5
6
7

02
03 8
04 9
Vee 10
VEE 11
AGNO 12

24
23
22
21
20
19
18
17
16
15
14
13

VIN
RB
AGNO
0GNO
eONV
07 (LSB)
06
05
Vee
NLINV
VEE
AGNO

24 Pin CERDIP - B7 Package

Functional Description
General Information
The TDC1 047 has three functional sections: a comparator
array, encoding logic, and output latches. The comparator
array compares the input signal with 127 reference voltages to produce an N-of-127 code (sometimes referred
to as a "thermometer" code, as all the comparators
referred to voltages more positive than the input signal
will be off, and those referred to voltages more negative
than the input signal will be onl. The encoding logic
converts the N-of-127 code into binary or offset two's
complement coding, and can invert either output code.
This coding function is controlled by DC signals on pins
NMINV and NLiNV The output latch holds the output
constant between updates.

Power
The TDC1 047 operates from two supply voltages, + 5.0V
and - 5.2V The return for ICC, the current drawn from
the + 5.0V supply, is DGND. The return for lEE, the
current drawn from the - 5.2V supply, is AGND. All
power and ground pins must be connected.

Reference
The TDC1047 converts analog signals in the range
VRB~VIN~VRT into digital form. VRB (the voltage.
applied to the pin at the bottom of the reference resistor
chainl and VRT (the voltage applied to the pin at the top
of the reference resistor chain I should be between
+ 0.1V and -1.1V VRT should be more positive than
VRB within that range. The voltage applied across the
reference resistor chain (VRT-VRBI must be between 0.8V
3-54

and 1.2V The nominal voltages are VRT= O.OOV and
VRB = -1.00V These voltages may be varied dynamically
up to 7MHz. Due to variation in the reference currents
with clock and input signals, RT and RB should be lowimpedance-to-ground points. For circuits in which the
reference is not varied, a bypass capacitor to ground is
recommended. If the reference inputs are exercised
dynamically as in an Automatic Gain Control (AGCI
circuit. a low-impedance reference source is
recommended.

Controls
Two function control pins, NMINV and NLiNV are
provided. These controls are for DC (i.e., steady statel
use. They permit the output coding to be either straight
binary or offset two's complement. in either true or
inverted sense, according to the Output Coding Table.
These pins are active LOW as signified by the prefix "N"
in the signal name. They may be tied to VCC for a logic
"1" and DGND for a logic "0:'

Convert
The TDC1 047 requires a CONVert (CONVI signal. A
sample is taken (the comparators are latchedl within the
Sampling Time Offset (tsTOI of a rising edge on the
CONV pin. The 127 to 7 encoding is performed on the
falling edge of the CONV signal. The coded result is
transferred to the output latches on the next rising edge.
The outputs hold the previous data a minimum time
(tHol after the rising edge of the CONV signal. This
permits the previous conversion result to be acquired by
external circuitry at that rising edge, i.e., data for sample
N is acquired by the external circuitry while the
TDC1047 is taking input sample N+ 2.

Analog Input
The TDC1 047 uses strobed latching comparators which
cause the input impedance to vary with the signal level,
as comparator input transistors are cut-off or become
active. For optimal performance, both VIN pins must be
used and the source impedance of the driving circuit
must be less than 30 Ohms. The input signal will not
damage the TDC1 047 if it remains within the range of
VEE to + 0.5V If the input signal is between the VRT
and VRB references, the output will be a binary number
between 0 and 127 inclusive. A signal outside this range
will indicate either full-scale positive or full-scale
,
negative, depending on whether the signal is off-scale in
the positive or negative direction.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI047
Outputs
The outputs of the TOC1 047 are TTL compatible, and
capable of driving four low-power Schottky TTL (54174
LSI unit loads or the equivalent. The outputs hold the

previous data a minimum time (tHaI after the rising edge
of the CONV signal.

Package Interconnections
Signal
Type
Power

Signal
Name

Function
Positive Supply Voltage

Value

87 Package Pins
10, 16
11, 14
4,21
3, 12, 13, 22

°GNO
AGNO

Analog Ground

+5.0V
-5.2V
O.OV
O.OV

Reference

RT
RB

Reference Resistor (Top)
Reference Resistor (Bottom)

O.OOV
-1.00V

2
23

Controls

NMINV
NLiNV

Not Most Significant Bit INVert
Not Least Significant Bit INVert

TTL
TTL

5
15

Convert

eONV

Convert

TTL

20

Analog Input

VIN

Analog Signal Input

OV to -lV

1,24

°1
°2
°3
°4

MSB Output

Outputs

Vce
VEE

°5
°6
°7

For More Infonmation caJI1-800-722-7074.

Negative Supply Voltage
Oigital Ground

LSB Output

Raytheon Semiconductor

TTL

6

TTL
TTL
TTL
TTL

7

TTL
TTL

8
9
17
18
19

3-55

I

TDCI047
Figure 1. TIming Diagram

DIGITAL OUTPUT

I

--~--~~~~~~~~~~~~~~--~~~~~~~~~

Figure 2. Simplified Analog Input Equivalent Circuit
VIN 0-....- - - _ - - - - - _ - - - - .

Ica

VEEA
CIN IS A NONLINEAR JUNCTION CAPACITANCE
VRa IS A VOLTAGE EQUAL TO THE VOLTAGE ON PIN Ra

Figure 3. Digital Input Equivalent Circuit
VCC

Figure 4. Output Circuits

0---4~-----.._---

+VCC

22K
15K

Blon
TO
OUTPUT o-_ _-W-...
PIN

INPUT 0 - - L-.....--oO OUTPUT

lN3062

OUTPUT EQUIVALENT
CIRCUIT

3-56

Raytheon Semiconductor

LOAD 1
.,..
TEST LOAD FOR DELAY
MEASUREMENTS

For More Infonnation calI1..aoo·722-7074.

TDCI047
Absolute maximum ratings Ibeyond which the device will be damagedJ1
$uptIIy VaItages

VCC (measured to 0GNIY .......................................................................................................................................................................................... -0.5 to +7.0V
Vee (measured to AtiNIY ..............................................................................................................................................•.........................•.......•.......... +0.5 to -7.DV
AtiNO (measured to 0GNIY ....................................................................................................................................................................................... -0.5 to +0.5V
Input VaItages

CONY, NMINV, NliNV (measured to 0GNIY .......................................................................................................................................................... -0.5 to +5.5V
VIN- VRT' VRB (measured to AGNIY ........................................................................................................................................................................... +0.5 to Vee
VRT (measured to VRW .............................................................................................................................................................................................. +21 to -2.2V
Output

Applied voltage (measured to 0GNIY ..................................................................•..................................................................................................... -0.5 to 5.5V2
Applied current externally forced ..........................•.•......................•.........•................•......................................................................................... -1.0 to 6.0mA3,4
Short circu~ duration (single output in high state to ground! ............................................................................................................................................ 1 sec
TtIRIJIIIIlII1I:e

Operating, case ......................................................................................................................................................................................................... -55 to + 125°C
junction ...............................................•......................................................•.......•..................................................................................................... +175°C
lead, soldering (10 seconds! ................................................................................................................................................................................................... +300°C
Storage ...................................•.•.........................•..........•...............•..........•................................•.................................................................................. -65 to + 150°C
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing vohage must be limited to specified range.
4. Current is specified as positive when flowing into the device.

Operating conditions
Temperature Range
Test Conditions

Parameter

Min

Standard
Nom

Max

5.0
-5.2
0.0

5.25
-5.5
0.1

VCC
Vee
VAGNO

Pos~ive

Supply Voltage (measured to 0GNOi
Negative Supply Voltage (measured to AGNOi
Analog Ground Voltage (measured to 0GNOi

4.75
-4.9
-0.1

'PwL
tPWH

CONY Pulse Width, LOW
CONY Pulse Width, HIGH

14
16

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

IOL
IOH

Output Current Logic LOW
Output Current, Logic HIGH

VRT
VRB
VRy-VRB
Vlr~

Most Positive Reference Input 1
Most Negative Reference Input 1
Voltage Reference Oifferential
Input Voltage

TA
TC

Ambient Temperature, Still Air
Case Temperature

Min
4.5
-4.9
-0.1

Extended
Nom

Max

Units

5.0
-5.2
0.0

5.5
-5.5
0.1

V
V
V

14
16

ns
ns

0.8
2.0
4.0
-0.4
-0.1
-0.9
0.8

0.8

V
V

2.0
-0.4

mA
mA

0.1
-1.1
1.2

2.0

0.1
-1.1
1.2

-0.1
-0.9
0.8

VRB

VRT

VRB

VRT

V
V
V
V

0

70
-55

125

°c
°C

0.0
-1.0
1.0

0.0
-1.0
1.0

Note:
1. VRT must be more positive than VRS, and voltage reference differential must be within specified range.

For More Information call HIOO·722·7074.

Raytheon Semiconductor

3·57

TDCI047
Electrical characteristics within specified operating conditions

Parameter

Test Conditions

ICC

Positive Supply Current

VCC ~ Max, static 1

lEE

Negative Supply Current

VEE ~ Max, static 1

Temperature Range
Extended
Standard
Min
Max
Min
Max
25

e

fA

~

DoC to 700

TA

~

10°C

Te

~

-55°C to 125°C

30

-170

VRT, VRS ~ Nom

Reference Current

RREf

Total Reference Resistance

mA

RIN

Input Equivalent Resistance

GIN

Input Capacitance

ICB

Input Constant Bias Current

VEE ~ Max

III

Input Current, logic lOW

VCC

35

28
VRT, VRS ~ Nom, VIN ~ VRS

~

-

Max, VI

n.sv CONY

~

IIH

Input Current, logic HIGH

Vce

~

Max, VI

~

2.4V

II

Input Current, Max Input Voltage

VCC

~

Max, VI

~

5.5V

VOL

Output Voltage, logic LOW

VCC ~ Min, 10l ~ Max

VOH

Output Voltage, logic HIGH

VCC

lOS

Short Circuit Output Current

Vee •

~

Min, IOH

~

50

mA
Ohms
kOhms

60

pf

150

300

Il A

-0.4

-0.6
-O.B
50
1.0

mA

0.5

Max, one pin to ground,

mA

40

2.4

Max

mA

-130

60

-0.6
50
1.0

NMINV, NliNV

-220

20

100

mA
mA

-135

TC ~ 125°C
IREf

Units

0.5
2.4

mA
Il A
mA
V

V

-30

-30

15

15

mA

one second duration.

el

Digital Input Capacitance

TA • 25°e, F • IMHz

pF

Note:
:. Worst case, all digital inputs and outputs LOW.

Switching characteristics within specified operating conditions

Parameter

3·58

Test Conditions

FS

Maximum Conversion Rate

VCC ~ Min, VEE ~ Min

tSTO

Sampling Time Offset

Vee - Min, VEE ~ Min

to

Output Delay

Vec ~ Min, VEE ~ Min, load 1

tHO

Output Hold Time

Vee' Max, VEE' Max, load 1

Temperature Range
Standard
Extended
Min
Max
Min
Max

Raytheon Semiconductor

20

20

30

5

MSPS

10
35

I

5

Units

ns
ns
ns

For More Information call 1-800·722·7074.

TDCI047
System performance characteristics within specified operating conditions

Parameter

Temperature Range
Standard
Extended
Max
Min
Max
Min

Test Conditions

ELI
ELO

Linearity Error Integral. Independent
Linearity Error Differential

VRT' VRB ~ Nom

CS

Code Size

VRT, VRB

VDT
VDB

Offset Voltage Top
Offset Voltage Bottom

TCO

Temperature Coefficient

BW

Bandwidth, Full Power Input

~

30

Nom

tTR

Transient Response, Full Scale
Signal-to - Noise Ratio
Peak SignaliRMS Noise
RMS SignaliRMS Noise

EAP

Aperture Error

OP
OG

Differential Phase Error 1
Differential Gain Error 1

170

% Nominal

mV
mV

±2U

±20

/-I Vlo C

30

MHz

7
10

48
46
39
37

10

50

50
1.5
2.5

1.5
2.5

FS~4xNTSC

ns

dB
dB
dB
dB

46
44
37
35

FS~4xNTSC

%

+50
-30

7

7MHz Bandwidth,
20MSPS Conversion Rate
lMHz Input
7MHz Input
lMHz Input
7MHz Input

%

+50
-30

170

VIN ~ VRT
VIN ~ VRB

SNR

0.4
0.4

0.4
0.4

Units

ps
Degree
%

Note:
1. In excess of quantization.

Output Coding
Binary
Step

Offset Two's
Complement
True
Inverted

Range

True

Inverted

-1.0000V FS
7.B74mV STEP

NMINV ~ 1
NLiNV ~ 1

0
0

0
1

1
0

O.OOOOV
-0.007BV

0000000
0000001

1111111
1111110

1000000
1000001

0111111
0111110

063
064

-0.4960V
-0.5039V

0111111
1000000

1000000
0111111

1111111
0000000

0000000 .

126
127

-1.9921V
-1.0000V

1111110
1111111

0000001
0000000

0111110
0111111

1000001
1000000

000
001

•

··
·•
·

··
·
·•
·

··
·
···

···
··
·

···
·•
·

··
·
·•
·

1111111

Note:
1. Voltages are code midpoints when calibrated Isee Calibration Section!'

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-59

I

TDCI047
Calibration
codes 00 and 01. Then apply -0.9961V and adjust VRB for
toggling between codes 126 and 127. Instead of adjusting VRT,
RT can be connected 10 analog ground and the OV end of the
range calibrated with a buffer offset control. RB is a
convenient point for gain adjust that is not in the analog signal
path. These techniques are employed in Figure 5.

To calibrate the TDC1047, adjust VRT and VRB to set the 1st
and 127th thresholds to the desired voltages in the block
diagram. Note that Rl is greater than R, ensuring calibration
with a positive voltage on RT- Assuming a OV to -lV desired
range, continuously strobe the converter with -0.0039V on the
analog input, and adjust VRT for output toggling between

Figure 5. Tvpical Interface Circuit
+SV
RS
2200

VIDEO
INPUT

1 t
U4
E
LM313
REFERENCE

~
C7

OI~F
sov

:b
~

~

"GAIN"
R9
MULTlTURN POT
2KO

'¢'

CI2
1- 6pF.,!ARIABLE

C9
O.I.uF
SOV
R6
2KO
14 ' "

*ca

~

RID
10KO

I

0]

8

I

RI2
270

~

2~ 7

~ O.I~F
6

01

2N2907

3

,r-;-~H~

-S.2V

,

VIN

R16
2.2K

VIN

O.I/i F
SOV

"

9

I
RI1
2.2K

F

RT

SOV

2SV

SOV

U3
/lA741C
OP-AMP

1

AGND

O.I~F

~.uF

~I-CS

8

],12,
13,22

~3

I~

1
RIS
2.2K

04

FAIR-RITE
L2
27430011111

7

TDC1047

~~

U2
HA-2S39-S
OP-AMP

1
R14
2.2K

D2

"OFFSET"
R8
MULTITURN POT
2KO

6

R4
2KO

Rll
10KO

,

RI]
2.2K

VCC
DIIMSOI

f-jh

CLK

110,16

J,;CI
;J;
10.uF
2SV

/I'

R]
IKO

R2 3
39.20

R7
IKO

C3
IO/lF +
2SV

.&

RI2
37.40

~

IfI!

LI
FAIR-RITE
274300111111

*
+

23

b

DS

R18
2.2K
06 18

1
R19
2.2K

°GNO
~

(LSOI

NMINV
20

1

RO

C11
~O.I/lF
SOV

;;

17

NLiNV

CONY

19

1

~
~

VEE

111,14 +

"
Notes:
1. Unless otherwise specified, all resistors are 1/4W, 2%.

1000 R2 )
2. Rl" liN - (- - 1000 + R2

3. R2 "(2V

Range ) _0.001

VREF liN

3-60

Raytheon Semiconductor

For More Information call 1-800-722-7074,

IDCI0471
Ordering Information
Product
Number
TDC104787C
TOC104787V

Temperature Range

Screening

Package

Package
Marking

STO-TA=O·C to 70°C
EXT - TC= - 55°C to 125°C

Commercial
MIL-STO-883

24 Pin CEROIP
24 Pin CERDIP

104787C
104787V

40001393 Rev F 8193

For More Information calI1-800-722-70R

Raytheon Semiconductor

3-61

TDCI047

3-62

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI048
TDCI048
Monolithic Video AID Converter
a-Bit, 20 Msps

Description

Features

The TDC1048 is a 20 Msps (Megasample per second)
full-parallel (flash) analog-to-digital converter, capable of
converting an analog signal with full-power frequency
components up to 7 MHz into 8-bit digital words. A
sample-and-hold circuit is not necessary. Low power
consumption eases thermal considerations, and board
space is minimized with a 28-pin package. All digital
inputs and outputs are TTL compatible.

•
•
•
•
•
•
•
•
•
•
•
•

The TDC1048 consists of 255 clocked latching
comparators, combining logic, and an output buffer
register. A single convert signal controls the conversion
operation. The unit can be connected to give either true
or inverted outputs in binary or offset two's complement
coding.

8-bit resolution
20 Msps conversion rate
Sample-and-hold circuit not required
Differential phase 1 degree
Differential gain 2.0%
112 LSB linearity
Guaranteed monotonic
TTL compatible outputs
Selected data format
Available in 28-pin plastic DIP, CERDIP, or LCC
MiI-5td-883 compliant screening available
Available per standard military drawing

Applications
•
•
•
•

Functional Block Diagram
NMIN v

Low-cost video digitizing
Radar data conversion
Data acquisition
Medical imaging

I

NUN v

CONv

,

v'N
T

"
,
,
,
'12

,>-- ~
'12

,
H

,
,

"
" >- t::=....
For More Information call 1-800-722-7074.

r;<'
:/

P-J-

k

;/

·· , ·. ··
~
....
~~

255 TO

a

ENCODER

~

-,/

'""'"

LATCH

-p

·· ·•• , ·••
~
~

DIFFERENTIAL
COMPARATORS
(2551

-

---

Raytheon Semiconductor

3-63

TDCI048
Pin Assignments

Q

01 (MS8)
°2
°3
°4
°GNO
Vee
VEE
VEE
VEE
Vee
0GNO
NLiNV
05
06

3

6

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

NMINV
RM
R8
AGNO
VIN
VIN
VIN
VIN
VIN
AGNO
RT
eONV
08 (LS8)
07

Q

~ off >~.ff J

R8
RM
NMINV
01 (MS8)

26
27
28
1

18
17
16
15
14
13
~ 12

°2
°3
04 4

U')ca

.....

RT
eONV
08 (LS8)
07
06
05
NLiNV

c:oc:n~;:

cowwW(')c

~~::-r>w~>(,,) ~
Q

28 Pin CERDIP - B6 Package
28 Pin Plastic DIP - N6 Package

Functional Description
General Information
The TOC1048 has three functional sections: a comparator
array, encoding logic, and output latches. The comparator
array compares the input signal with 255 reference
voltages to produce an N-of-255 code (sometimes
referred to as a "thermometer" code, as all the comparators below the signal will be on, and all those above
the signal will be offl. The encoding logic converts the
N-of-255 code into binary or offset two's complement
coding, and can invert either output code. This coding
function is controlled by DC signals on pins NMINV and
NLI NV. The output latch holds the output constant
between updates.
Power
The TOC1048 operates from two supply voltages, + 5.DV
and - 5.2V. The return for ICC, the current drawn from
the + 5.0V supply, is DGND. The return for lEE, the
current drawn from the - 5.2V supply, is AGND. All
power and ground pins must be connected.
Reference
The TOC1048 converts analog signals in the range
VRBoIt---i
The bottom reference voltage, VRB, is supplied by an
inverting amplifier on the LM611 ,buffered with a PNP
transistor. The transistor provides a low-impedance source
and is necessary to sink the current flowing through the
reference resistor chain. The bottom reference voltage

10K

-2V

Figure 6. Typical Interface Circuit
+5V

+5V

~~~~

@

2.2K

2.2K
+5V

NMINV
12

17
20
21
23
24
18
27
26

NLiNV

O2

CONY

°3

VIN

°4

VIN

°5

VIN
VIN
AGNO

For More Information call 1-800·722·7074.

°6

14
15

°7
08 (LSB)

RT

°GNO

RM

°GNO

RB

P·l
·5V

TOC1048

13

·5V

·5V

Raytheon Semiconductor

3-71

I

TDCI048
Ordering Information
Product
Number
5962-8760001 XA
TDC1048C3C
TDC1048C3V
5962-87600013A
TDC104886C
TDC104886V
TDC1048C3C

Temperature Range
EXT - Tc = -55·C to 125·C
STD - TA - O·C to 70·C
EXT - TC = -55·C to 125·C
EXT - Tc = -55·C to 125·C
STD - TA = O·C to 70·C
EXT - Tc = -55·C to 125·C
STD - TA - O·C to 70·C

Screening
Per Standard Mil Drawing
Commercial
MIL-8TD-883
Per Standard Mil Drawing
Commercial
MIL-8TD-883
Commercial

Package
28-Pin Ceramic DIP
28-Contact LCC
28-Contact LCC
28-Contact LCC
28-Pin CERDIP
28-Contact LCC
28-Contact LCC

Package
Marking
5962-8760001 XA
1048C3C
1048C3V
5962-87600013A
104886C
104886V
1048C3C

40G01216 Rev 18193

3-72

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI0491
TDCI049
High-Speed AID Converter
9-Bit, 30 Msps

Description

Features

The TDC1049 is a flash (full-parallel) analog-to-digital
converter capable of converting analog signals with fullpower frequency components up to 15 MHz into 9-bit
words at rates up to 30 Msps (Megasamples Per
Second). A sample-and-hold circuit is not required. All
digital inputs and outputs are differential ECL.

•
•
•
•
•
•
•
•
•

The TDC1049 consists of 512 latching comparators,
encoding logic and an output register. A differential
convert signal controls the conversion operation. The
outputs can be connected to give either true or inverted
binary or offset two's complement formats.

Video data conversion
Radar data conversion
High-speed data acquisition

..

CONV
CONV

Applications
•
•
•

Functional Block Diagram

30 Msps conversion rate, 15 MHz analog bandwidth
9-Bit resolution and linearity
Sample-and-hold circuit not required
Differential phase 0.5 degrees
Differential gain 1.0%
Overflow flag
Single -5.2V power supply
Differential ECl outputs
Available in a 64-pin DIP, 68-c0ntact lCC and
68-pin ceramic pin grid array

(

"IN

R,

RT
DFS
R,

RI1

i<
V

R,

RI1

R~

R

R

RMID

R

R.

For More Infonnation call 1-800-722-7074.

,--'--

rl<

~
....
... :~

1'~

1

r----+-

OVF.

OVF

'8

512 TO 9
ENCODER

I )

LATCH

~

Al1

RI1

...,

~

RI1

... ~

,"'"
1v:

.....
----,,«,

'---

,

DIFFERENTIAL
COMPARATORS
I"~

Raytheon Semiconductor

3-73

TDCI049
Pin Assignments
"

D7

..

~

(gJ

1
f

Di

" ''
os" ''

Di

64
63 .,ILSB)

Og(lSB)

82 .,llSB)

.,ILSB)

61 DGND
60 CONY
59 CONY

DGND
CONV

58

DGND

.....," ,'

g57.,.

NO •
NOlO

OFS

~58

"

NO"

"

Ne 13

..

RTS
OFS
RT 10
Ne 11

V~

V,N 12

0

VEEA, 14

NO"
Ne 16

VEEA 17

NO"
¥EEA 19

NO,.
Ne 21

b" ....,
51

AoND

so

V,N

VEfll 22[
Ne 23
Ne 24

.....,,,

V,N

46

"oND

45
44

"GND
NC

61

" 0,

58 "
57 AGND
"

54 Veeo
Ne

52 NC

P51

AoND 14

50

V,N 15
V,N
RM
V,N
AGND
AGND

NC

55 Ne
53

VeEA
Ne

49 Ne

16
17
18
19
20

48 VEEA
47 Ne

Ne 21

46 VEEA
45 Ne
44 NC

43 v~
42 NC
41 RS

VIN 22

43 Veeo

40 Res

RSS 25

NC "
RS

24~

42

Ne

41

Ne

39 DGND
38 DGND
37 OVF

'GNO 26[
DGND 27

39 NC

OVF "

".,30"

360VF

0vF29

37
36 04

35

0, (MSB)

0,"

34

D1 (MSB)

01 (MSB) 30
D1 (MSBj 31

3S
34 D3

iii"

33 0,

64 Pin DIP

3B

!!!!: i::lEu i:

~ ~u

liEu o::a

~~~~~~~~~~~~:~~~3

OFS 61

43 RSS

RTS 6Z

"

CIDiV 63

Ne

CONY 64

41 DGND
.. OVF

DONO 65

29M
38 Dl {MSBI

.,ILS" 66

31

09 (LSB) 67

DB

68
D, 1
OJ 2

34 "

330,
32 D,

D,

.,
4

31 fi4
30NC
29 Ne

D,

0,; 7

NC

AOND

,

0, (MSB)

"0,
35 02

. ,,,
~

28 Ne

'E1 AOND

S~~~~~~~~~~N~~~~~

~~~~~~~~~~~~~~~~~

Nt

D4

68 Contact LCC

-

C1 Package

D3

3302

0,"

JO Package

~ ~CI ~

z~>«z>z=

40 "'NO

NO"
NO"

0428

co +-

0,

"0,

AGND 13

49 V,N
48 RM
47

07

63
82 ..,

4

CONY

DGNO

Q54 NC

VEED "

64 0,

,
,
,
,
,
,

64 Pin DIP

J3 Package

Pin Assignments
68 Pin Ceramic Pin Grid Array, G8 Package
Pin

Name

Pin

Name

Pin

Name

Pin

Name

A2
A3
A4
A5
A6
A7
-A8
AS
AID
Bl
82
B3
B4
B5
86
B7
B8

NC

BS
BIO
Bll
Cl
C2
ClO
Cll
01
02
010
011
El
E2
El0
Ell
Fl
F2

VEEA
NC

FlO
Fll
Gl
G2
GIO
GIl
HI
H2
HID
Hll
Jl
J2
J1D
Jll
Kl
K2
K3

Os
07
01

K4
K5
K6
K7
KS
KS
KJO
Kll
l2
l3
l4
l5
l6
l7
lS
lS

AGNO
VIN
VIN
NC

1I0

OFS

3-74

VEEO
NC
NC
NC
NC
NC
NC
VEEO
NC
AGNO
VEEA

NC
VEEA
VEEA
VEEA
NC

AGNO
NC
NC
05
NC
04
04
06
°5
03
03
°7
06
02
O2

OJ
Os
Os
OVF
OVF
°GNO

Dg

NC
°GNO
CONV
°GNO
RBS
RB
VIN

AGNO
VIN
RTS
CONV
NC
NC
AGNO
RM
NC

000000000
0@0000000@0
00
00
00
00
00 BOTTOM VIEW
00
00
00
o0
~I~ENTATION
00
00
~. 00
00
~00
0@0000000@0
000000000{1
K J

H G FED

11
10

C B A

V1N
AGNO
RT

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI049
Functional Description
General Information
The TOC1049 has three functional sections: a comparator
array, encoding logic and output register. The comparator
array compares the input signal with 512 reference
voltages to produce an N-of-512 code or "thermometer"
code. The comparators referenced to voltages less than
the input signal will be on and those referenced to
voltages greater than the input signal will be off. The
encoding logic converts the N-of-512 code into 9-bit
binary data. The output register holds the output
between updates.

Power
For optimum performance, separate analog and digital
power, VEEA and VEED should be supplied to the
TOC1049. Separate analog and digital power supplies or
a common supply with separate analog and digital paths
and high-frequency decoupling can be used. The return
path for the current drawn from VEEA and VEED is
AGNO and 0GNO, respectively. The returns AGNO and
0GNO should also be kept separate and connected
together at the power supply terminals. It is recommended that provisions be made on the printed circuit
board for shorting jumpers between analog and digital
ground as close to the AID converter as possible. The
installation of the jumpers depends upon the printed
circuit board layout and overall system performance once
the system is in operation. The voltage difference
between VEEA and VEED must be less than ±O.lV The
same voltage difference limit applies to the difference
between AGNO and 0GNO. All power and ground inputs
to the converter must be connected.

Reference
The TOC1049 converts analog signals in the range
VRB----.-------,
D
~-----4__o

0

CDNV
5K

51(

VEED C>----~-----..J
DUTPUT EOUIVALENT CIRCUIT
TD
OUTPUT

,.

!. "

o-----<:tt-----.

~1

LDAD 1
TEST LOAD FDR DELAY
MEASUREMENTS

-2.0V

Figure 5. CONVert. CONVert Switching Levels
o.OV
~---,,----------

VICM MIN

""

"" """
-------,-," " -- - - - - -

"" "",-----,

VICM MAX -

3-78

-

-

-

-

~'"

Raytheon Semiconductor

-1.3V
CDNV

x'-____

For More Information call HIOO-722-7074.

TDCI049
Absolute maximum ratings (beyond which the device may be damaged) 1
Supply Voltages
VEED (measured to DGND) ................................................................................................................" .......................... + 0.5 to - 7.0V
VEEA (measured to AGND) ........................................................................................................................................... +0.5 to -7.0V

AGND (measured to DGND) ........................................................................................................................................... + 1.0 to -1.0V
VEEA (measured to VEED) ............................................................................................................................................ +0.5 to -0.5V
Input Voltages 2

CONY, CONY (measured to DGND) ................................................................................................................................... + 0.5 to VEE
VIN, VRT, VRB (measured to AGND) ............................................................................................................................... + 0.5 to VEE
VRT (measured to VRB) ................................................................................................................................................. + 2.5 to - 2.5V
Output

Short-circuit duration (single output in HIGH state to ground) .............................................................................................. Infinite
Temperature

Operating, case .............................................................................................................................................................. - 60 to
junction ......................................................................................................................................................................
Lead, soldering (10 seconds) .....................................................................................................................................................
Storage ............................................................................................................................................................................ - 65 to
Notes:

+ 140°C
+ 175°C
+ 300°C
+ 150°C

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.

Operating conditions
Temperature Range
Parameter

Min

Standard
Nom

Max

Min

Extended
Nom

Max

Units

-4.9
-4.9
-0.1
-0.1

-5.2
-5.2
0.0
0.0

-5.5
-5.5
+0.1
+0.1

-4.9
-4.9
-0.1
-0.1

-5.2
-5.2
0.0
0.0

-5.5
-5.5
+0.1
+0.1

V
V
V
V

VEED
VEEA
VAGND
VEEA-VEED

Digital Supply Voltage (measured to DGND)
Analog Supply Voltage (measured to AGND)
Analog Ground Voltage (measured to DGND)
Supply Voltage Differential

tpWL
tpWH

CONY Pulse Width, LOW
CONY Pulse Width, HIGH

VICM
VIDF
VIN

Input Voltage, Common Mode
Input Voltage, Differential
Input Voltage Range

-0.5
0.3

VRT
VRB
VRr-VRB

Most Positive Reference Input 1
Most Negative Reference Input 1
Voltage Reference Differential

-0.1
-1.9
1.8

TA
Te

Ambient Temperature, Still Air
Case Temperature

Note:

12
15

ns
ns

12
15
-2.5
1.2

VRB
0.0
-2.0
2.0

0

-0.5
0.3

VRT

VRB

0.1
-2.1
2.2

-0.1
-1.9
1.8

-2.5
1.2

0.0
-2.0
2.0

VRT

V
V
V

+0.1
-2.1
2.2

V
V
V

125

°C
°C

70
-55

1. VRT Must be more positive than VRB . and voltage reference differential must be within specified range.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-79

TDCI049
Electrical characteristics within specified operating conditions
Temperature Range
Test Conditions

Parameter
lEE

Supply Current

Standard
Min
Max

VEEO. VEEA=Max
TA=O°C to 70°C
TA= 70°C
TC= -55°C to 125°C

Extended
Min
Max

-950
-750
-1090
-750

TC=125°C
VRT. VRB = Nom

RREF

Reference Current
Total Reference Resistance

10
56

RIN
CIN

Input Equivalent Resistance
Analog Input Capacitance

VRT. VRB=Nom. VIN=VRB
VRT. VRB=Nom. VIN=VRB

16

ICB
II

Input Constant Bias Current
Input Current. CONY. CONY

VEEA=Max. VIN=OV
VEEO=Max. VI= -0.7V

VOL
VOH

Output Voltage. Logic LOW 1
Output Voltage. Logic HIGH 1

VEED=Nom
VEED=Nom

CI

Digital Input Capacitance

TA=25°C. f=lMHz

Note:

1. Test Load=5000 to -2V on each output.

IREF

10
56

Units
rnA
rnA
rnA
rnA

36
200

mA
Ohms

160

160

kOhms
pF

500
150

750
180

p.A
p.A

-1.5

V
V

20

pF

36
200

16

-1.6
-0.95

-1.1
20

Switching characteristics within specified operating conditions
Temperature Range
Parameter
FS

Maximum Conversion Rate

VEEO. VEEA = Min

30

tSTO

Sampling Time Offset

VEEO. VEEA=Min

-2

to
tHO

Output Oelay 1
Output Hold Time

VEED. VEEA = Min
VEED. VEEA = Min

3

Note:

3-80

Test Conditions

Standard
Min
Max

1

Extended
Min
Max

Msps

30
6

-2

27

3

Units

6

ns

27

ns
ns

1. Test Load = 5000 to - 2V on each output. CLOAD = 20pF.

Raytheon Semiconductor

For More Information call HlOO-722-7074.

TDCI0491
System performance characteristics within specified operating conditions
Temperature Range
Parameter

Test Conditions

Standard
Min
Max

Extended
Min
Max

ELI

Linearity Error Integral. Independent

ELD

Linearity Error Differential

VRT. VRB=Nom
VRT. VRB=Nom. VRM Adjusted
VRT. VRB=Nom

Q

Code Size

VRT. VRB=Nom

EDTS
EOT
EOBS
EOB
TCO

Offset
Offset
Offset
Offset
Offset

tTR

Transient Response. Full-Scale

BW

Bandwidth. Full Power Input

± 0.9dB Frequency Response

15

15

MHz

SNR

Signal-to-Noise Ratio

30Msps Conversion Rate.
10MHz Bandwidth
1.25MHz Input
5.0MHz Input
1.25MHz Input
5.0MHz Input

57
53
48
44

57
53
48
44

dB
dB
dB
dB

Error.
Error.
Error.
Error.
Error.

Top
Top
Bottom
Bottom
Temperature Coefficient

Peak Signal/RMS Noise
RMS Signal/RMS Noise

EAP

Aperture Error

DP
DG

Differential Phase Error
Differential Gain Error

0.15
0.10
0.1

Units

15

185

VIN=VRB

15

%
%
%

185

% Nominal

±4
30

±4
30

±4
-30
20

±4
-30
20

mV
mV
mV
mV
/lV/oC

20

20

VIN = VRT. RTS Connected
VIN=VRT
VIN = VRB' RBS Connected

0.20
0.10
0.1

50

50

ps

0.5
1.5

0.5
1.5

FS=4 x NTSC
FS=4 x NTSC

ns

Degree
%

Typical Performance Curves
B. SNR vs. Analog Input Frequency

A. Power Supply Current vs. Temperature

60
-450

~ -500

iii 50

:s

!i -550

~-----~

II:

5l
'"
sa
i!

'" -600
B
II:

> -650
~
~-700

40
30

~

~-800

~
'"iii

-850

~

Eli -750

20

'" 10

-55°

-25°

0°

25°

50°

75°

100°

125° \

1.248 2.438 3.58

For More Inlormation call 1-800-722-7074.

7

9

10

11

12

13

14

15

ANALOG INPUT FREOUENCY (MHz)

CASE TEMPERATURE (OC)

Raytheon Semiconductor

3-81

TDCI049
Standard Military Drawing
These devices are also available as products manufactured, tested, and screened in compliance with Standard
Military Drawings ISMDsl. The nearest vendor equivalent
product is shown below; however, the applicable SMD is
the sale controlling document defining the SMD product.
Ordering Information
Product
Number

Temperature Range

Screening

Commercial
TDC1049JOC
STD - TA = O·C to 700C
MIL-STD-883
TDC1049J0V
EXT - TC = -55·C to 125°C
5962-8853201 XA EXT - Tc =-55°C to 125°C Per Standard Mil Drawing
Commercial
TDC1049C1C
STD - TA =OOC to 70°C
MIL-5TD-883
TDC1049C1V
EXT - TC =-55°C to 125°C
5962-8853201 ZA EXT - Tc =-55°C to 125°C Per Standard Mil Drawing
TDC1049G8C
Commercial
STD - TA =OOC to 70°C
TDC1049GSV
EXT - Tc =-55°C to 125°C
MIL-5TD-883

Standard Mirrtary
Drawing

Nearest Equivalent

Package

Package
Marking

64-Pin Ceramic DIP
64-Pin Ceramic DIP
64-Pin Ceramic DIP
68-Contact Ceramic LCC
68-Contact Ceramic LCC
68-Contact Ceramic LCC
68-Pin Ceramic PGA
68-Pin Ceramic PGA

049JOC
l049JOV
5962-8853201XA
1049C1C
1049C1V
5962-8853201 ZA
1049G8C
1049G8V

Package

Raytheon Product No.

5962.m53201XA

TDC1049JOV

64-Pin Ceramic DIP

5962-8853201YA

TDC1049J3V

64-Pin Ceramic DIP

5962-8853201ZA

TDC1049C1V

68-Contact Chip Carrier

5962-8853201 UA

TDC1049L1V

68-Contact Chip Carrier

4OG03657 Rev E 8193

3-82

Raytheon Semiconductor

For More Infonnation call1.aoO-722-7074.

TDCI058
TDCI058
Monolithic Video AID Converter
a-Bit, 20 Msps, Low Power

Description
The TDC1058 is a flash analog-to-digital converter
capable of converting a video-speed signal into a stream
of a-bit digital words at 20 Msps (MegaSampies Per
Second). Since the TDC1058 is a flash converter, a
sample-and-hold circuit is not required.
The TDC1058 consists of 255 clocked latching
comparators, combining logic, and an output register. A
single convert clock controls the conversion operation.
The unit can be configured to give either true or inverted
outputs in binary or offset two's complement coding. All
digitail/Os are m compatible.

Features
•
•
•
•
•

a-bit resolution
DC to 20 Msps conversion rate
7 MHz full-power bandwidth
60 MHz small signal -3 dB bandwidth
112 LSB linearity

•
•
•
•
•
•
•
•
•
•

600 mW power diSSipation
+5V single supply operation
Lowest cost
Pin compatible with CXA1096P, AOC-304
Sample-and-hold circuit not required
Analog input range +3V to +5V
Differential phase 0.50
Differential gain 1%
Selectable data format
Available in plastic DIP, CERDIP, and PLCC

Applications
•
•
•
•
•
•

Digital television
PC-based data acquisition
Video digitizing
Medical imaging
High energy physics
Low cost, low power, high-speed data conversion

Pin Assignments

.

.

D1 (MSB) 1
02 2
03 3
°4
°GNO
VCCO
AGNO
AGNO
AGNO
VCCO
0GNO
NLiNV
05
06

6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22

~o 350 :i5u g
>z>z>z>

NMINV
RM
RB
VCCA
NC
VIN
NC

..n_C":»C"oI
N
_
C' .:t .:t .:t.;> r!i'

21209A

For More Information call 1-800-722-7074.

C'\I

RB 26
RM 27
NMINV 28
0 1 (MSB)

21 VIN
20 NC
19
18
17
16
15

......

.-.~

21210A

28 Leaded Plastic Chip Carrier - R3 Package

Raytheon Semiconductor

3-83

I

TDCIOS8
Functional Block Diagram
NMINV
NliNV

"

"
CONV

I

VIN
RT

'""

~
~
.....

Rl~
?R~

R~

~

~

R:?-

··

~

>

~~D
'yy

R:?-

~

·

~~

~
~

I

··
255T08
ENCODER

~

R{

'~

$

R{

'~

R~
'~

R2~

··

··

~~

~
~

8

"-

"

,/

REGISTER

/

t...

"

·

~

DIFFERENTIAL
COMPARATORS
(255)

2121 1A

Functional Description
General Information

Power

The TOC1058 has three functional sections: a comparator array, encoding logic, and output registers. The
comparator array compares the input signal with 255
reference voltages to produce an N-of-255 code (or
thermometer code, since all the comparators whose
reference is more negative than the input signal will be
on, and all those whose reference is more positive will
be off). The encoding logic converts the N-of-255 code
into the user's choice of coding. The output register
holds the output constant between updates.

The TOC1058 operates from a single supply voltage:
+ 5.oV. All power and ground pins must be connected.

3-84

Reference
The TOC1058 converts analog signals in the range
VRS ~ VIN ~ VRT into digital form. Nominally, VRS is
set to 3V and VRT is set to 5V. However, the specifications of the TOC1058 are guaranteed as long as the
following three reference operating conditions are met:
1.) the voltage applied across the reference resistor

Raytheon Semiconductor

For More Information call HI00-722·7074.

TDCI058
Reference (cont.)
chain (VRT-VRBI is within the range of 1.8 to 2.2V. 2.1
VRT ~ (VCCA + O.1Vl and 3·1 VRB ;;;;. 2.65V. Therefore. if
the supply voltage is expected to drop below 4.9y' the
reference voltages should be lowered accordingly. For
instance. if the system design allows the supply voltage
to drop to the minimum recommended value of 4.75V.
VRT should be set to 4.65V and VRB should be set to
2.65V. These reference voltages will allow the TOC1058
to give fully guaranteed performance over the full supply
voltage range. See the Operating Conditions Table for
further information.
Linearity is guaranteed with no adjustment; however. a
midpoint tap. RM. allows for the optional trimming of
converter integral linearity as well as the creation of a
nonlinear transfer function. This is explained in the
Application Note TP-19 "Non-Linear AID Conversion:'
The circuit shown in Figure 7 will provide approximately
a 1/2 LSB adjustment of the linearity at midscale. The
characteristic impedance seen at this node is approximately 220 Ohms and should be driven from a lowimpedance source. Note that any load applied to this
node will affect linearity and any noise introduced at this
point will degrade the overall SNR. Due to the slight
variation in the reference current with clock and input
signals. RT and RB should be low-impedance-toground points. For circuits in which the reference is not
varied. a bypass capacitor (0.01 to 0.1 p,Fl to ground is
recommended. If the reference inputs are exercised
dynamically (as in an automatic gain control circuitl a
low-impedance reference source is required. The
reference voltages may be varied dynamically at up to
5MHz; however. device performance is specified with
fixed reference voltages as defined in the Operating
Conditions Table.

Analog Input
For precise quantization. the TOC1058 uses latching
comparators. The source impedance of the driving circuit
must be less than 25 Ohms. for optimum overall system
performance. If the input signal is between the VRT and
VRB references. the output will be a binary number from
o to 255. When a signal outside the recommended input
voltage range (VRB to VRTI is applied. the output will
remain at either full-scale value. The input signal will not

For More Information call 1-800-722-7074.

damage the TOC1058 if it remains within the range
specified in the Absolute Maximum Ratings Table.
Both analog input pins are connected together internally
and therefore either one or both may be used.

Convert
The TDC1058 requires an external convert (CONVI signal.
Because the TOC1058 is a flash converter it does not
require a track-and-hold circuit. A sample is taken (the
outputs of the comparators are latchedl within tSTO
(Sampling Time Offsetl after a rising edge on the CONY
pin. The result is encoded on the falling edge. and then
transferred to the output registers on the next rising
edge. The output becomes valid to (Output Delay Timel
after the rising edge of CONVert and remains valid for at
least tHO (Output Hold Timel after the rising edge of
CONVert. Therefore. the value of sample N becomes
valid to after the rising edge of clock N + 1 and remains
valid until tHO after the rising edge of clock N + 2. (See
Figure 1, Timing Diagram. I

Output Format Control
Two output format control pins. NMINV and NLiNV. are
provided. These controls are for DC (i.e .. steady statel
use. They permit the output coding to be either straight
binary or offset two's complement. in either true or
inverted sense. according to the Output Coding Table.
These pins are active LOW. as signified by the N prefix
in the signal name. They may be tied to VCC (through a
4.7 kOhm resistorl for a logic HIGH or DGND for a logic
LOW.

Outputs
The outputs of the TOC1058 are TTL compatible and
capable of driving four low-power Schottky TTL (54174
LSI loads or the equivalent. The outputs hold the previous data for a minimum of tHO after the rising edge of
the CONVert signal.

Not Connected
There are several pins that have no internal connection
to the chip. They should be left open.

Raytheon Semiconductor

3-85

I

TDCI058
Package Interconnections
Signal
Type

Signal
Name

Power

VCCD
VCCA
AGND
DGND

Digital Supply Voltage
Analog Supply Voltage
Analog Ground
Digital Ground

Reference

RT
RM
RB

Reference Resistor (Top)
Reference Resistor (Middle)
Reference Resistor (Bottom)

Function

86, N6, R3
Package Pins

Value
+5.0V
+5.0V
O.OV
O.OV

6, 10
19.25
7. 8. 9
5. 11

5.0V
4.0V
3.0V

18
27
26

Analog Input

VIN

Analog Signal Input

Convert

CDNV

Convert

TTL

17

Format Control

NMINV
NLiNV

Not Most Significant Bit Invert
Not Least Significant Bit Invert

TTL
TTL

28
12

Data Output

01
02
03
04
05
06
07
08

Most Significant Bit Output

Least Significant Bit Output

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

1
2
3
4
13
14
15
16

NC

Not Connected

Open

20. 22. 24

Not Connected

Figure 1. Timing Diagram
CONY

ANALOG INPUT

JI'-~AMPLE

--

~
DIGITAL OUTPUT

~

\

1

~tSTO

I

'-1'-

1
FS

1I

See Text

tpWH~tpWL-'

SAMPLE
N+1

DATA
N ·1

tHO ~

1I

\.

--{:~

XXXX

21. 23

I

XXX'%..

SAMPLE
N+2

\

~
XXXX

DATA
N

I

I

\

--'"
DATA
N+1

XXXX
21190A

pr

Figure 2. Simplified Analog Input Equivalent Circuit

vw:~t)'c.
AGND

"Nf

VCCA

Y,N

0-+-+--1

VRB AGND

C 'N IS A NONLINEAR JUNCTION CAPACITANCE
VRB IS A VOLTAGE EQUAL TO THE VOLTAGE ON PIN RB

3-86

Raytheon Semiconductor

REFERENCE
RESISTOR
AGND
CHAIN

21196A

For More Information caJI1-800-722-7074.

Figure 3. Convert Input Equivalent Circuit

Figure 4. Output Circuit

VCCDo---~------~----------~--

8100

.--..._~~+--+__o0UTPUT TO

OUTPUT
PIN

INPuTo-+--I----_.J

1N3062

40pF

-=

DGND
OUTPUT EQUIVALENT
CIRCUIT

21197A

LOAD 1
...
TEST LOAD
DGND
FOR DELAY
MEASUREMENTS
21198A

Output Coding Table
Binary

Offset Two's Complement

True

Inverted

True

Inverted

Voltage

NMINV=HIGH
NLlNV=HIGH

NMINV=LOW
NLlNV=LOW

NMINV = LOW
NLlNV=HIGH

NMINV=HIGH
NLlNV=LOW

5.0000V
4.9922V

0000 0000
0000 0001

11111111
11111110

1000 0000
1000 0001

0111 1111
0111 1110

Input

··
·

4.0078V
4.0000V
3.9922V

··
·

3.0156V
3.0078V
Notes:

·•
·

0111 1111
1000 0000
1000 0001

·•
·

1111 1110
11111111

·
·•

1000 0000
0111 1111
0111 1110

·•
·

0000 0001
0000 0000

·
·•

•
•

·

11111111
0000 0000
0000 0001

0000 0000
11111111
1111 1110

•
•

•
•

·

0111 1110
0111 1111

·

1000 0001
1000 0000

1. NMINV and NliNV are to be considered DC controls. They may be tied to +5V through a 4.7 kOhm resistor for a logic HIGH or tied to
ground for a logic LOW.
2. Voltages are code midpoints.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-87

TDCI058
Absolute maximum ratings (beyond which the device may be damaged) 1
Power Supply Voltages
VCCA (measured to AGND) .....................................................................................-0.5 to +7.0V
VCCD (measured to DGND) .................................................................................... -0.5 to +7.OV
AGND (measured to DGNol .................................................................................... -0.5 to +0.5V
Input Voltages
CONV. NLiNV. NMINV ....................................................................................-0.5 to VCC+O.5V
VIN. VRT. VRB (measured to AGNol .......... ·... ·.... ·..... ·.. ····.····.·· .. ·.... ·........................ -0.5 to +5.5V
VRT (measured to VRBl ..........................................................................................-2.2 to +2.2V
Input Currents
CONV. NLiNV. NMINV ........................................................................................-50to +50 rnA
VIN. VRT. VRB .............................................................................................................-100 to +100 rnA

Digital Outputs
Applied voltage2 .........................................................................................................-0.5 to VCC+O.5V
Applied current3.4 ..........................................................................................................-50 to +50 mA
Short-circuit duration (single output in HIGH state to GND) .......................................... 1 second.
Temperature
Operating. ambient (all packages except N6 and R3) ............................................ -55 to +1250C
(N6 and R3 packages only) .......................................................................... -20 to 900C
junction (all packages) ....................................................................................... +1750C
Lead. soldering. all packages (10 seconds) ..................................................................... +3OOOC
Storage ...............................................................................................................-65 to +1500C

Notes:

3-88

1. Absolute maximum ratings are limiting values applied individually while all other parameters are
within specified
operating conditions. Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range. and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

Raytheon Semiconductor

For More Information call 1.000-722-7074.

TDCI058
Operating Conditions
Temperature Range
Standard

Min

Parameter

4.75
4.75
'{).1
19
27

Nom

Extended

Max

5.0
5.0
0.0

5.25
5.25
0

Min

Nom

Max

4.50
4.50
+0.1
18
22

5.0
5.0
0

5.50
5.50
0.1

Units

VCCA
VCCO
VAGNO
trwL
trwH
VIL
VIH
IOL
IOH
VRT
VRB
VRT-VRB
VIN
TA
TA

Analog Supply Voltage
Digital Supply Voltage
Analog Ground Voltage (Measured to DGNO)
CONV Pulse Width. LOW
CONY Pulse Width. HIGH
Input Voltage. Logic LOW
Input Voltage. Logic HIGH
Output Current. Logic LOW
Output Current. Logic HIGH
Most Positive Reference Input 1
Most Negative Reference Input 1
Voltage Reference Differential
Input Voltage
Ambient Temperature. Still Ajr
Case Temperature

Note:

1. VRT must be more positive than VRB. and voltage reference differential must be within specified range.

0.8
2.0

2.. 65
1.8
VRB
0

V
V
V
ns
ns
V
V
rnA

0.8
2.0

5.0
3.0
2.0

4.0
-400
VCCA =0.1
2.2
VRT
70

4.9
2.9
1.8
VRB

5.0
3.0
2.0

-55

4.0
-400
5.1
3.1
2.2
VRT

V
V
V
V

125

"C
"C

JlA

Thermal characteristics (approximatel
Package

Typical

Units

8ja

Thermal Resistance, Junction to Ambient

N6
R3

45
65
50

°C/W
°C/W
°C/W

8jc

Thermal Resistance, Junction to Case

N6

17
14

°C/W
°C/W
°C/W

Parameter

B6

R3
B6

For More Information call 1-800-722-7074.

Raytheon Semiconductor

TBD

3-89

I

TDCI058
Electrical characteristics within specified operating conditions

Parameter
ICCA+ ICCD
IREF
RREF
RIN
CIN
ICB
IlL
IIH
II
VOL
VOH
lOS
CI
Note:

Test eoncfrtions

Temperature Range
Standard
Extended
Min
Max
Min
Max

Total Supply Current
Vcc=Maxl
Reference Current
VRT, VRB=Nom
Total Reference Resistance
67
Input Equivalent Resistance
80
VRT, VRB=Nom, VIN-VRB
Input Capacitance
VRT, VRB=Nom, VIN=VRB
Input Constant Bias Current
VCCA=Max
Input Current Logic LOW
VCc=Max, VI=0.4V
Input Current Logic HIGH
-200
Vcc=Max, VI=2.4V
Input Current, Max Input Voltage VCC=Min, 10L=Max
Output Voltage, Logic LOW
Vcc=Min, 10L=Max
Output Voltage, Logic HIGH
2.4
Vcc=Min, 10H=Max
Short-Circuit Output Current
Vcc-Max, Output HIGH, one pin to
ground, one second duration max
Digital Input Capacitance
TA=25"C, F=l MHz

160

160
50

30
40
40
50
250
-0.6
50
1.0
0.5

-400

50
500
-0.6
50
1.0
0.5

Units
rnA
mA
Ohms
kOhms
pF
~

rnA
~

-40

-40

mA
V
V
rnA

15

15

pF

2.4

1. Worst case, all digital inputs and outputs LOW.

Switching characteristics within specified operating conditions

Parameter
FS

Maximum Conversion Rate

tsTO Sampling Time Offset
Output Delay
to
tHo Output Hold Time

3-90

Test Conditions

Temperature Range
Standard
Extended
Min
Max
Min
Max
20
-2

Vcc=Min, Load 1, Figure 4
Vcc=Min, Load 1, Figure 4

Raytheon Semiconductor

5

10
35

20
-2
5

10
35

Units
Msps
ns
ns
ns

For More Infonnation caJI1-800-722-7074.

TDCI058
System performance characteristics within specified operating conditions

Parameter

Test Conditions

ELI Linearity Error Integral. Independent
ELD Linearity Error Differential
Code Size
Cs
EaT Offset Error. Top
EOB Offset Error. Bottom
Teo Offset Error. Temperature Coefficient
BW Bandwidth. Full-Scale Input
BWSS -3 dB Bandwidth. Small Signal
tTR Transient Response. Full Scale
SNR Signai-to-Noise Ratio

VRT. VRB=Nom

Peak SignallRMS Noise
RMS SignaVRMS Noise
EAP

Aperture Error

DG

Differential Gain Error

VIN=VRT
VIN=VRB
No Spurious or Missing Codes
-20 dBFS Input
10 MHz Bandwidth.
20 Msps Conversion Rate
1.248 MHz Input
2.438 MHz Input
1,248 MHz Input
2.438 MHz Input

Temperature Range
Standard
Extended
Min
Max
Min
Max

25
-10
-20
7
60
70

0.2
0.2
175
+10
-15
±20

25

±0.2
±0.2
175
+15
-15
±20

7

60
70

54
53
45
44

53
52
44

43
60

60

2.0

FS=4x NTSC

Figure 5. Typical Interface Circuit
'5V )>----------------------.-----__.----,

2.0

Units
0/0
0/0
0/0 Nom
mV
mV
JJ.VfC
Mhz
MHz
ns

dB
dB
dB
dB
ps
%

~

'15V)-,---------'111/1""'"""-----,

D1 IMSB)
D2
D3
D4
DS

13
14

D6
D7
DsllSB)
TOel0Ss

NC

NMINV

15
16
20,22,24

2S

NliNV 12
ANAlOG~

INPUT

f

lK
50

lK

~0.1

lK

"OFFSET"

CLOCK>-----------------.!!..JL-:..~~:-..-~::,..,,-..J
ALL CAPACITORS 0.1 MF CERAMIC UI~LESS OTHERWISE NOTED

For More Information call 1-800-722-7074.

Raytheon Semiconductor

21497A

3-91

I

TDCI058
Figure 7. Optional Midscale Linearity Adjust

Figure 6. Inexpensive Interface Circuit
+5V

RT

+5V --~~--------~-------'-I
FERRITE
BEAD

10K

~~~----------~VCCA,VCCD

2K:>-ot----t

~--~~------~~RT

0.1~FPO~F

2000

R
>-----f--,M"'I

TDC1058

10K
TDC1058
RB

1MF
INPUTo-j

+3V--~~--------------~

V,N
+0.1~F

2000

21195A

RM

RB

0.1~FPO~F
-=
CONY
NOTE: 1. Optional, see text

21213A

Typical Interface Circuit
The Typical Interface Circuit (Figure 5) shows an
example of a high-performance application circuit for the
TDC1058. The wideband analog input amplifier drives the
AID converter directly. Bipolar inputs to the amplifier can
be accommodated by adjusting the offset control. TRW's
TDC4614 provides a stable reference for both the offset
and gain control. All VIN pins are con-nected close to
the device package and the input ampli-fier's feedback
loop should be closed at that point. The buffer has an
inverting gain of two, increasing a 1Vp-p video input
signal to the recommended 2Vp-p input for the
TDC1058. Proper decoupling is recommended for all
systems.
The bottom reference voltage (VRBI is supplied by an
inverting amplifier or the TDC46l4, buffered with a PNP
transistor! The transistor provides a low-impedance source

3-92

and is necessary to sink the current flowing through the
reference resistor chain.
The Inexpensive Interface Circuit shown in Figure 6
offers considerable parts reduction for cost-sensitive
applications where DC response is not required and loss
of some power supply rejection is tolerable. The 200
Ohm resistors bias the input to + 4V and provide the
current to the zener diode to provide the reference
bottom Voltage. The l/tF capacitor decouples the input
signal from the DC voltage present at the input of the
TDC1058. The 10/tF and O.l/tF capacitors, as well as the
ferrite bead, provide power supply decoupling. The
1N57ll Schottky diodes are for protection against
overvoltages at the input and are not required if these
precautions are taken elsewhere in the circuit.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI058I
Typical Performance Curves
A. Typical Differential Phase and Gain
DIFFERENTIAL
GAIN

. :;.:;.. ,.

;.:.:t"--_~

DG

=

B. Typical SINAD (SNR + Distortion) vs. Input
Frequency

2%

50

--.... ............

0

~.............................

0.99%

45

-2
DIFFERENTIAL PHASE

,0 .......................................................... .

..,

............

III

~ 40

z

CLOCK RATE· 20MS
INPUT SIGNAL = FULL SCALE ·0.1 dE

iii

""-

,

"

35

30

Convert Frequency = 14.3181800MHz
Analog Input = 3.57954550MHz

2
3
45678
Input Frequency - MHz
21215A

21214A

Ordering Information
Product
Number

Temperature Range

Screening

TDC1058B6C
TDC1058B6V
TDC1058N6C
TDC1058R3C

STD - TA = OOC to 700c
EXT - TC = -55OC to 1250C
STD - TA = OOC to 700C
STD - TA = OOC to 700C

Commercial
MIL-STD-883
Commercial
Commercial

Package
2IWin CERDIP
28-Pin CERDIP
28-Pin Plastic DIP
28-Lead Plastic J-Leaded Chip Carrier

Package
Marking
1058B6C
lD58B6V
lD58N6C
lD58R3C

40G05738 Rev E 8/93

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-93

TDCI058

3·94

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TDC1l47

TDCl147
Monolithic Video AID Converter
7-Bit, 15 Msps

Description

Features

The TDCl147 is a 7-bit "flash" analog-to-digital
converter which has no pipeline delay between sampling
and valid data. The output data register normally found
on flash AID converters has been bypassed, allowing
data to transfer directly to output drivers from the
encoding logic section of the circuit. The converter
requires only one clock pulse to perform the complete
conversion operation. The conversion time is
guaranteed to be less than 60 nanoseconds.

•
•
•
•
•
•
•
•

20 Msps conversion rate
No digital pipeline delay
7-bit resolution
112 LSB linearity
Sample-and-hold circuit not required
TTL compatible
Selectable output format
Available in 24 pin CERDIP

Applications

The TDCl147 is function and pin-(X)mpatible with
Raytheon Semiconductor La Jolla's TDC1047 7-bit flash
AID converter which has an output data register. The
TDC1147 will operate accurately at sampling rates up to
15 Msps and has an analog bandwidth of 7 MHz.
Unearity errors are guaranteed to be less than 0.4%
over the operating temperature range.

•
•
•
•
•
•

Low-(X)st video digitizing
Medical imaging
Data acquisition
High resolution AID converters
Telecommunications systems
Radar data conversion

Functional Block Diagram
NMINV
NIiNV
CONY
VIN
RT

I I

=-

~
~

RI

R

•
•
•

:\
R

R

••

,~

•

R

:• '"

~

~
: ':\
':\

.

~

••
•
1Z1 TO 7
fNCOD£R
7

/

••
•

~

R

RZ

DIffERENTIAL

'---

For More Information call 1-800-722-7074.

COMPARATORS
Illli

Raytheon Semiconductor

3-95

I

TDCl147
Pin Assignments

!! '--'

VIN

1

NMINV

5

(MSD) 01

6

I

04

9

L_____ ___J

[RT
RT
Rr 1 LSB

11111111
11111111
11111110

•
•

•
•

(RT + Rs)/2 + 1 LSB
(RT + Rs)/2

5000

•

•

•

•

Rs + 1 LSB
Rs
-----1I~

~'o>__---tl~
AGBD

-

--.

For More Information call 1-800-722-7074.

27051A

27052A

Raytheon Semiconductor

3-109

I

TMCl173
Absolute Maximum Ratings (beyond which the device may be damaged) 1
Supply Voltages
VOOA (measured to AGNO) .......................................................................................-0.5
VOOO (measured to DGNO) ......................................................................................-0.5
VOOA (measured to Vooo) .......................................................................................-0.5
DGNO (measured to AGNO )......................................................................................-0.5

to
to
to
to

+7.0V
+7.0V
+0.5V
+0.5V

Inputs
Applied voltage 2 CONY, OE\ ..............................................................................-0.5 to VOOO V
Applied voltage 2 RT , RB, VIN .............................................................................A GNO to VOOA V
Outputs
Applied VOltage 2 ............................................................................................ -0.5 to (Voo+0.5) V
Forced Current3 .4 ................................................................................................... -6.0 to 6.0 rnA
Short Circuit Duration
(Single output in HIGH state to GND) ........................................................................... 1 second
Temperature
Operating. ambient. ..................................................................................................-20 to +90°C
Junction .............................................................................................................................+ 140°C
Lead, soldering (1 0 seconds) ...........................................................................................+300°C
Vapor phase soldering (1 minute) ....................................................................................+220°C
Storage ...................................................................................................................-65 to + 150°C
Notes:

1.

2.
3.
4.

3-110

Absolute maximum ratings are limiting values applied individually while all other parameters
are within specified operating conditions. Functional operation under any of these
conditions is NOT implied.
Applied voltage must be current limited to specified range, and measured with respect to
GND.
Forcing voltage must be limited to specified range.
Current is specified as conventional current, flowing into the device.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC1173
Operating conditions
Standard Temperature Range
Parameter
V OOA
VOOO
AGNO

Analog Supply Voltage
Digital Supply Voltage
Analog Ground Voltage
(Measured to DGNO )

Min

Nom

Max

Units

2.7
2.7
-0.1

3.0
3.0
0

3.6
3.6
0.1

V
V
V

Conversion Rate
TMC1173-5
TMC1173-10

5
10

Msps
Msps

CONY pulse width, HIGH
TMC1173-5
TMC1173-10

20
20

ns
ns

CON V pulse width, LOW
TMC1173-5
TMC1173-10

20
20

ns
ns

RT
Rs
RT - Rs

Reference, Top
Reference, Bottom
Reference Voltage Differential

0
0
1.2

V DO
1.3
3.3

V
V
V

VIN

Analog Input Range

Rs

RT

V

V IH
V IL

Input Voltage, Logic HIGH
Input Voltage, Logic LOW

0.2

x VOO
x VOO

IOH
IOL

Output Current, Logic HIGH
Output Current, Logic LOW

-1.0
2.0

mA
mA

TA

Ambient Temperature, Still Air

70

°C

fs

tpWH

tpWL

For More Information call 1-800·722·7074.

0.85

0

Raytheon Sem/conductor

3·111

I

TMCl173
Electrical characteristics
Standard Temperature Range
Parameter
100

Total Power Supply
Current

Conditions
VOOA=VOOO= 3.6V,
C LOAO = 35pF
TMC1173-5, fs = 5 Msps
TMC1173-10, fS = 10 Msps

IOOQ

Quiescent Power Supply VOOA=Vooo=Max,CONV=LOW
Current
VOOA=VOoo=Max,CONV=HIGH

Po

Total Power Dissipation

V OOA = VOOO =3.6V
CLOAO = 35pF
TMC1173-5, fs = 5 Msps
TMC1173-10, fs = 10 Msps

CONV=HIGH

R'N
ICB

Input Capacitance
Input Resistance
Analog Input Current

IREF
RREF

Reference Current
Reference Resistance

RT = 1.2 V, RB = 0.0 V

C 'N

VRT
Ref. Voltage, Top
VRB
Ref. Voltage, Bottom
VRrV RB Ref.Voltage Ditt.

Min

Typ

Max

Units

17
21

25
30

mA
mA

15
20

mA
mA

61
76

mW
mW

16

18

pF
kQ

±10

J.tA

100

400
RB = V R_, RT = VR+
RB = V R_, RT = VR+
RB = V R_, RT = VR+

2.4
500

mA
Q

1.6
0.4
1.2

V
V
V

I'H
I,l

Input Current, HIGH
Input Current, LOW

VOO = Max, V ,N = VOO
VOO = Max, V ,N = 0 V

±10
±10

J.tA
J.tA

'OZH
10Zl

leakage Current, HIGH
Leakage Current, LOW

OE\ = HIGH, VOUT = VOO
OE\ = HIGH, VOUT = DGNO

±10
±10

J.tA
J.tA

lOS

Short-Circuit Current

30

mA

VOH
VOL

Output Voltage, HIGH
Output Voltage, LOW

0.3

V
V

Note:

3·112

0 0 -7, 10H = Max
0 0 -7 , 10H = Max

2.2

Values shown in Typ column are typical for VOO = +3.0 V and TA = 25°C.

Raytheon Semiconductor

For More Infonnalion call 1-800·722·7074.

TMCl173
Switching Characteristics
Standard Temperature Range
Parameter

Conditions

tSTO

Sampling Time Offset

too

Output Delay Time

C LOAD = 15pF

tHO

Output Hold Time

C LOAD = 15pF

tENA
tOiS

Output Enable Time
Output Disable Time

For More Information call 1-800·722·7074.

Min

Typ

Max

Units

0

3

10

ns

44

ns
ns

5
65
65

Raytheon Semiconductor

ns
ns

3·113

I

TMC1173
System Performance Characteristics
Standard Temperature Range
Parameter

Conditions

Min

Typ

Max

UnitS

ELI

Integral Linearity Error

Rs
RS
Rs
RS

= VR_, RT = VR+
= AGNO ' RT = +1.2 V
= AGNO ' RT = +2.7 V
= AGNO' RT = VDDA

±0.3
±0.3
±0.3
±0.3

±O.S
±O.S
±O.S
±O.S

LSB
LSB
LSB
LSB

ELO

Differential Linearity
Error

Rs
Rs
RB
Rs

= VR_, RT = VR+
= AGND , RT = +1.2 V
= AGND , RT = +2.7 V
= A GND , RT = VDDA

±0.3
±0.3
±0.3
±0.3

±O.S
±0.5
±0.5
±0.5

LSB
LSB
LSB
LSB

CS

Code Size

19S

%nom

BW

Bandwidth

5

MHz

Eap

Aperture Error

EOT

Offset Voltage, Top

RT - V IN for most positive
code transition

±75

mV

Eos

Offset Voltage, Bottom

Rs - V IN for most negative
code transition

±40

mV

DG

Differential Gain

fs = 14.3 Msps,
NTSC 40 IRE ramp,
for Rs = V R_, RT = VR+ and
Rs = AGND , RT = +1.2 V
V DD = +3.0 V, TA = 25°C

2

0/0

DP

Differential Phase

fs = 14.3 Msps,
NTSC 40 IRE ramp,

1

a

5

30

ps

for Rs = V R_, RT = VR+ and
Rs = AGND , RT = +1.2 V
V DD = +3.0 V, TA = 2SoC
Note: Values shown in Typ column are typical for VDD = +3.0 V and T A = 2SoC. Bandwidth is the frequency band
in which a full-scale sinewave can be digitized without spurious codes.

3-114

Raytheon Semiconductor

For Mol'll Information call 1-800-722-7074.

TMC1l73
System Performance Characteristics
Standard Temperature Range
Parameter

Conditions

SNR

TMC1173-5, fs = 5 Msps,
fiN = 1.24 MHz
fiN = 2.48 MHz
TMC1173-10, fs = 10 Msps,
fiN = 1.24 MHz
fiN = 2.48 MHz
fiN = 4.96 MHz

SFDR

Signal-to-Noise Ratio

Spurious Free
Dynamic Range

TMC1173-5, fs = 5 Msps,
fiN = 1.24 MHz
fiN = 2.48 MHz
TMC1173-10, fs = 10 Msps,
fiN = 1.24 MHz
fiN = 2.48 MHz
fiN = 4.96 MHz

Min

Typ

43
42

46
45

dB
dB

43
42
40

45
44
42

dB
dB
dB

37
32

43
40

dB
dB

37
31
26

43
40
32

dB
dB
dB

Max

Units

Note: SNR values do not include the harmonics of the fundamental frequency.
SFDR is the ratio in dB of fundamental amplitude to the harmonic with highest amplitude.
Values shown in Typ column are typical for VDD = +3.0 V and T A = 25°C.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-115

I

TMCll73
Figure 9. Typical Interface Circuit
+3Vo-----.--------.----------~--_.

LM185-1.2

1kQ

O.1IlF ~

Video
Input

CONY .---------------------------------~
OE\

.-----------------------------------~

27056A

Application Notes
The circuit in Figure 9 uses a band-gap reference
to generate a variable RT reference voltages for the
TMC1173 as well as a bias voltage to offset the
wideband input amplifier to mid-range. An "offset
adjust" is also shown for varying the mid-range
voltage level. The operational amplifier in the
reference circuitry is a standard general-purpose
741-type.
The voltage reference is variable from 0.0 to 2.4
volts on RT while Rs is grounded. Note the diode
clamps on the wideband op-amp output. These
prevent the NO input from being driven beyond the
power supply. Diode protection is advised as good
practice to prevent analog input signals from being
driven beyond the power supply.

3-116

The circuit in Figure 1Oa shows the self-bias of RT
and Rs by connection to VR+ and VR_. This sets up
a 0.4 to 1.5 Volt input range for VIN' The input
range is susceptible to power supply variation since
the voltages on RT and Rs are directly derived from
VDDA- The video input is AC-coupled and biased
at a variable midpoint of the AID input range. This
circuit offers the advantage of minimum support
circuitry for the most cost-sensitive applications.
In Figure 10b. an external band-gap reference sets
RT to + 1.2 Volts while Rs is grounded. The internal
pull-up resistor. R+. provides the bias current for
the band-gap diode. The input impedance of the
Rf input is approximately 500 and the NO
converter input is biased at the mid-point of the
input range.

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TMC1l73
Figure 10. Typical Interface Circuits

(a)

0.1 I1F

~~dp~~

rp

75Q

CONY

OE\

0.1I1F~

10 I1 F
f-_ -*-___-----'---I

VIN

OE\

CONY
1N4148

AGND

DGND

~----------------~

~----------------~

(b)

, - - - - - 1 VR+

;=-:-.-+----1 RT

TMC1173

I~~t ~10

1kQ
F
f-11_-*-_ _-.-_ _ _-i

56Q

VIN

OE\

CONY

1kQ
AGND

DGND

1N4148

CONY

OE\

~----------------~

~----------------~

27057A

For More Information caJI1-800-722-7074.

Raytheon Semiconductor

3-117

I

TMCl173
Grounding

The TMC1 '173 has separate analog and digital
circuits. To keep digital system noise from the AID
converter, it is recommended that power supply
voltages (V DOD and V DDA) come from the same
source and ground connections (DGND and AGND)
be made to the analog ground plane. Power
supply pins should be individually decoupled at the
pin.
The digital circuitry that gets its input from the
TMC1173 should be referred on the system digital
ground plane.

should be used for all of the V DD pins. If the
power supply for the TMC1173 is the same as
that of the system's digital circuitry, power to
the TMC1173 should be decoupled with ferrite
beads and 0.1 J.lF capacitors to reduce noise.
3.

the ground plane should be solid, not crosshatched. Connections to the ground plane
should have very short leads.

4.

Decoupling capacitors should be applied
liberally to V DD pins. Remember that not all
power supply pins are created equal. They
typically supply adjacent circuitry on the
device, which generate varying amounts of
noise. For best results, use 0.1 J.lF ceramic
capacitors. Lead lengths should be minimized.
Ceramic chip capacitors are the best choice.

5.

If the digital power supply has a dedicated
power plane layer, it should not overlap the
TMC1173, the voltage reference or the analog
inputs. Capacitive coupling of digital power
supply noise from this layer to the TMC1173
and its related analog circuitry can have an
adverse effect on performance.

6.

CONY should be handled carefully. Jitter and
noise on this clock may degrade performance.
Terminate the clock line carefully to eliminate
overshoot and ringing.

Printed Circuit Board Layout

Designing with high-performance mixed-signal
circuits demands printed circuits with ground
planes. Wire-wrap is not an option ... even for
breadboarding. Overall system performance is
strongly influenced by the board layout. Capacitive
coupling from digital to analog circuits may result in
poor ND conversion. Consider the following
suggestions when dOing the layout:

1.

2.

3-118

Keep the critical analog traces (V IN , RT, Rs '
VR+' VRJ as short as possible and as far as
possible from all digital signals. The TMC1173
should be located near the board edge, close
to the analog output connectors.
The power plane for the TMC1173 should be
separate from that which supplies the rest of
the digital circuitry. A single power plane

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC1l73
Typical Performance Curves

A.

IDD VS.

B.

VDD at 25°C

18

IDD (mA)

12

10

j

12

VRB = 0.4 V
VRT = 1.6 V
TA = 25°C
fiN = 2 MHz
fs = 10 Msps -

I-

11

3.6

3.0
3.3
V DD (Volts)

I

I

I

I

... .....

48
46
44

SNR (dB)
42 I--

6

r--. r-... r-.....

-

40 I-38

c-,

36

2

3
fiN (MHz)

4

fiN

I

VDD=3.0V
VRB = 0.4 V
VRT = 1.6 V
TA = 25°C
fs = 10 Msps -

1""-0 r--.

75

50

-25

D. SNR vs.

fiN

9

5

V DD = 3.0 V
VRB = 0.4 V
V RT = 1.6 V
fiN = 2 MHz
Is = 10 Msps

IDD (mA)

-

•

10

8
Effective
Bits
7

I-

/

/
LI

2.7

C. EFB vs.

/

TA

13

1/

14

at fs

= 10 Msps

vs.

/

/

16

IDD

5

V DD = 3.0 V
V RB = 0.4 V
VRT = 1.6 V
TA = 25°C
Is = 10 Msps

, , ,

I

234

5

fiN (MHz)

27058A

For More Infonnation call 1-800-722-7074.

Raytheon Semiconductor

3-119

I

TMCl173
Ordering Information
Product
Number

Conversion
Rate (Msps)

Temperature
Range

Screening

Package

Package
Marking

TMC1173M7C5
TMC1173M7C10

5
10

T A: O°C to 70°C
TA: O°C to 70°C

Commercial
Commercial

24-Lead SOIC
24-Lead SOIC

1173M7C5
1173M7C10

TMC1173N2C5
TMC1173N2C10

5
10

TA: O°C to 70°C
T A: O°C to 70°C

Commercial
Commercial

24-Pin Plastic DIP
24-Pin Plastic DIP

1173N2C5
1173N2C10

TMC1173R3C5
TMC1173R3C10

5
10

TA: O°C to 70°C
TA: O°C to 70°C

Commercial
Commercial

28-Lead Plastic PLCC
28-Lead Plastic PLCC

1173R3C5
1173R3C10

TMC1175E1C

30

TA: OO°C to 70°C

Commercial

Eurocard PC Board

TMC1175E1C

4OG07280 Rev B 8/93

3-120

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC1l75

TMCl175
CMOS 8-Bit Video AID Converter
Description
The TMC1175 analog-tcKIigital (AID) converter employs
a two-step architecture with integral track/hold. The
device converts analog signals into 8-bit digital words at
rates up to 40 Msps (Megasamples per second). The
architecture and CMOS technology reduce typical power
dissipation to less than 150 mW.
The TMC1175 operates from a Single +5 Volt power
supply and has internal voltage reference resistors
which allow self-bias operation. The input capacitance is
very low, simplifying the design of, or eliminating, the
need for video driving amplifiers. All digital inputs and
three-state outputs are ffi-compatible.
The TMC1175 is available in 24-pin plastic DIP, 24-Lead
plastic SOIC, and 28-lead J-Iead PLCC packages. Miltemperature versions are available in CERDIP or
ceramic LCC packages. Performance specifications are
guaranteed over the -20 to 75°C and -55 to 1250C
temperature ranges.

8-bit resolution
10,20, and 40 Msps conversion rate
Integral track/hold

Differential linearity error - "
]]:!~ >CI:
>

Do 3

D, 4

2
Do 3
D, 4
D, 5
D3 6
D, 7
Ds 8
D, 9
D,10
Vooo 11
CONV 12
DGND

0, 5
D3 6

19 V,N

0, 7

18 Voo•

Ds 8

D. 9

24
23
22
21
20
19
18
17

It).q-MC\J

DGNO

..... OQ)

NC\lC\JC\JC\JC\I

V R•
AGNO

AGNO
V,N
Voo•

RT

16 V R•
15 Voo•
14 Voo•
13 Vooo

V R• 26
R. 27

18 Voo•

DGNO 28
N/C
1

16 Vooo

OEI
DGNO

2
3

Do

4

17 Voo•
15 N/C
14 CON V
13 Vooo
12 D,
lOf.Of'-..COo)O

~

OOO~

15 Voo•
Vooo 11

14 Voo•

CONV12

13 Vooo

z

N2 Package
24-pin Plastic DIP

.....

R.

M7 Package
24-Lead SOIC

.....
~

0·0'0

R3 Package
28-lead J-Iead PLCC
27049A

General Description
The TMC1175 is an 8-bit AID converter which uses
a two-step architecture to perform analog-to-digital
conversion at rates up to 40 Msps. The input
signal is held in an integral track/hold stage during
the conversion process. Pipelined operation is
achieved with one input sample taken and one
output word provided for each convert cycle. The
first step in the conversion process is a coarse 4-bit
conversion. The coarse 4-bit result determines the
range of the subsequent fine 4-bit AID conversion
step. To eliminate spurious codes, the fine 4-bit
AID converter output is gray-coded and converted
to binary before combining with the coarse result to
form the complete 8-bit result.

Analog Input and Voltage References
The TMC1175 converts analog signals in the range
RT $; VIN $; Rs into digital data. The AID converter
input range is very flexible and extends from the +5
Volt power supply to ground. Normally, external

3-122

voltage reference sources are connected to the RT
and Rs pins or Rs is grounded.
Two reference pull-up and pull-down resistors
connected to VR+ and VR_, are provided for
operation without external voltage reference
circuitry. These voltages applied to RT and Rs may
be generated externally, or are self-generated by
connecting VR+ to RT and VR_to Rs. In the latter
case the power supply voltage is divided by on-chip
resistors to bias the RT and Rs points.
The self-bias reference voltages are useful in
applications where overall circuit cost is important
and absolute accuracy and stability of the AID
converter gain is not critical.
The V IN input range is from Rs to RT. The device
will not be damaged by signals within the range
AGND to V DD ·

Raytheon Semiconductor

For More Information call 1-800·722-7074.

TMC1l75
Figure 3. Reference Resistors
Table 1. Output Coding Table

V DDA +3.0V
----j

Input
Voltage

Output Code
MSB
LSB

RT

-----"
AGND

27010A

01111111
10000000

•
•

11111110
11111111
11111111

Note: 1 LSB = (RT - RB)/255
Digital Inputs and Outputs
The sampling of the applied input signal takes
place on the falling edge of the CONY signal. The
output word is available after the rising edge of
CONY, delayed by 2 1/2 CONY cycles. The output
remains valid for tHO (Output Hold Time) and new
data becomes valid to (Output Delay Time) after
the rising edge of CONY.

Pin Functions
The input voltage conversion range
extends from the voltage applied to the
RT and RB pins.
The top and bottom inputs to the
reference resistor ladder. DC voltages
applied to RT and RB define the VIN
conversion range.

The outputs of the TMC1175 are TTL-compatible
and are capable of driving four low-power Schottky
TTL (54/74LS) loads. An output enable control,
OE\, places the outputs in a high-impedance state
when HIGH. The outputs are enabled when OE\ is
LOW.
Power and Ground
The TMC1175 operates from a Single +5 Volt
power supply. For optimum performance, it is
recommended that AGNO and 0GNO pins of the
TMC1175 be connected to the system analog
ground plane.

For More Information call 1-800·722-7074.

Internal pull-up and pull-down
reference resistors used in self-bias
operation.
CONY

AID converter clock input. VIN is
sampled on the falling edge of CONY.

OE\

Output Enable. When LOW, 0 0-0 7 are
enabled. When HIGH, 0 0-0 7 are in a
high-impedance state.

DO-07

Eight-bit TTL-compatible digital
outputs. Valid data is output on the
rising edge of CONY.

Raytheon Semiconductor

3-123

I

TMCl175
VOOA'VOOO +5 Volt power inputs. These should
come from the same power source and
be decoupled to AGNO '

AGNO,DGNO Ground inputs should be connected to
the system analog ground plane.

Table 2. Package Interconnections
Signal Type

Name

Function

Value

N2, M7 Pin

R3, C3 Pin

Inputs

V 1N
RT
Rs
VR+
VR.
OE\
CON V

Analog Input
Reference Voltage Top Input
Reference Voltage Bottom Input
Reference Voltage Top Source
Reference Voltage Bottom Source
Output enable
Convert (Clock) input

Rs-RT
2.6V
0.6V
2.6V
0.6V
TTL
TTL

19
17
23
16
22
1
12

23
20
27
19
26
2
14

Outputs

Do

Least Significant Bit

3
4
5
6
7
8
9
10

4
5
6
7

14,15,18
11, 13
20,21
2,24

17,18,21
13,16
24,25
3,28

01
O2
03
04
05
06
07

Most Significant Bit

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

Power

V OOA
Vooo
AGNO
DGNO

Analog Supply Voltage
Digital Supply Voltage
Analog Ground
Digital Ground

+5V
+5V
O.OV
O.OV

No Connect

N/C

Not Connected

open

3-124

Raytheon Semiconductor

9
10
11
12

1,8,15,22

For More Information caJI1-800-722-7074.

TMC1l75
Figure 4. Timing Diagram

Sample
N+1

Sample
N+3

-++0...--- 1/fs
r-----~I

CONV

r-----~I

__Hj:.Z__

Data N-1

Data N

OE\
27050A

Figure 5. Equivalent Digital Input Circuit

Figure 7. Equivalent Digital Output Circuit

Voo

Voo

n Substrate

Input

Output

n

-=

Figure 6. Equivalent Analog Input Circuit

~'o~----jl~
VIN

27011A

27014A

Figure 8. Transition Levels for Three-State
Measurements

OE\

o--+-----..------+$

Video
Input

TMC1175

2kn
"Offset
Adjust"

OE\
0

l-..-..J\N50°C Derate at 8.38 mWfC

Connection Information
16-Lead
Dual-In-Une
(Top View)

135°C/W

7.41 mWfC

~177

Pin
1
2
3
4
5
S
7
8

3-140

Function
VLC Threshold Control
lOUT
-Vs
lOUT
81 (MSB)
82
B3
B4

Raytheon Semiconductor

Pin
9
10
11
12
13
14
15
16

Function

B5
8S
87
B8 (LSB)
+Vs
VREF (+)
VREF (-)
Compensation

For More Information call HIOO-722-7074.

DAC08
Functional Block Diagram
+v.

VLC

MSB
Bl

B2

B3

B4

B5

I!II

B7

I!II

(4)

(2)

lK

I

lour

lour

lK

-Va
(3)

For More Information call 1-800-722-7074.

500

500

500

500

Raytheon Semiconductor

500

500

500

6IH)178

3-141

DAC08
Electrical Characteristics
(Vs = ±15V,IREF = 2.0 rnA, TA = -55OC to +125OC for DAC-QS and DAC-08A; TA = OOC to +70OC for DAC-OSC and
DAC-OSE unless otherwise specified. Output characteristics refer to both lOUT and louT')

Min

DAC-Q8A
Typ

Max

Min

DAc-DS
Typ

Max

Units

Resolution

8

8

8

8

8

8

Bits

Monotonicity
Nonlinearity

8

8

8

8

8
+0.19

Bits

Full Temperature Range

8
+0.1

%FS

Settling Time

To +112LSB. All Bits
Switched ON or OFF

Parameters

Test Conditions

85

135

85

150

ns

35
35
±10

60

35
35
±10

60
60
±SO

ns
ppmlOC

+18

V

1.99

2.04

mA

±1.0
0.2

±S.O

JJA

TA =+25°C1
Propagation Delay
Each Bit
All Bits Switched
Full Scale Tempco
Output Vottage Compliance

TA=+25OC1

Full Scale Current
Change < 112 LSB

-10

60
±SO
+18

-10

1.992

2.000

1.94

±D.5
0.1

±4.0
1.0

RoUT> 20 MO Typical

Full Scale Current

VREF = 10.000V
R14• R15 = 5.000kO

1.984

TA = +25OC
Full Scale Symmetry
Zero Scale Current

IFS-IFS

Output Current Range

VREF =+15V. -Vs = -10V

2.1

2.1

R14' R15 = 5.000kO
Logic Input Levels

VREF = +25V. -Vs = 12V

4.2

4.2

Logic "0"
Logic "1"
Logic Input Current

2.0

Logic "0"
Logic "1"
Logic Input Swing

VLC=OV
VIN = -10V to +0.8V
VIN = 2.0V to 18V
-Vs =-15V

-10

Logic Threshold Range l

Vs =±15V

-10

Reference Bias Current
Reference Input Slew Rate1

mA

0.8

VLC=OV

0.8

V

-2.0

-10

JJA

0.002

10
+18

V

2.0
-2.0
0.002

4.0

2.0

-1.0
8.0

-10
10
+18
+13.5
-3.0

-10
-10
4.0

-1.0
8.0

+13.5
-3.0

JJA
mA/J.IS

Note:
1. Guaranteed by design. but not tested.

3-142

Raytheon Semiconductor

For More Information call HIOO-722-7074.

DAC08
Electrical Characteristics (continued)
Parameters

Test CondHlons

Power Supply Sensitivity

+Vs =4.5Vto 18V,
-Vs = -4.5V to -18V,

Positive
Negative
Power Supply Current
Positive
Negative
Positive
Negative
Positive
Negative

Power Consumption

Min

DA(}()8A
Typ
Max

Min

DAC-08
Typ

Max

UnHs
o/oLY=S

:10.0003 :to.01
:to.002 :to.01

IREF = 1.0 mA
Vs ·-J5·0V,
IREF = 1.0 mA
Vs = +5.0V, -15V,
IREF =2.0 mA
Vs =±15V
IREF =2.0 mA
Vs=-J5·0V
IREF" 1.0 mA
Vs = +5.0V, -15V,
IREF =2.0 mA
Vs =±15V

:to.OOD3 :to.01
:to.OO2 :to.01

o/~V

%1%

2.3
-4.3

3.8
-5.8

mA
mA

3.8

2.4

-7.8
3.8
-7.8

-6.4
2.5
-6.5

3.8
-7.8
3.8
-7.8

mA
mA
mA

48

33

48

108

136

108

136

135

174

135

174

2.3
-4.3

3.8
-5.8

2.4
-6.4
2.5
-6.5
33

I

--

mA

mW

IREF=2.0 mA

Parameters

Test CondHlons

Resolution
MonotoniCity

Min
8
8

Nonlinearity

Full Temperature Range

Settling Time

To +112LSB, All Bits
Switched ON or OFF

DAC-08E
Typ
Max
8
8

8
8

Min
8
8

DAC-Qac
Typ
Max

8
8

+0.19

8

UnHs
Bits
Bits

8
+0.39

%FS

85

150

85

150

ns

35
35
±10

60
60
±SO

35
35
±10

60
60

ns

±BO

ppml"C

+18

V

1.99

2.04

mA

:12.0

±16.0

~

TA =+25°C1
Propagation Delay
Each Bit
All Bits Switched

TA =+25oc1

Full Scale Tempco
Full Scale Current
Output Vonage Compliance

Change < 112 LSB

-10

+18

-10

1.99

2.04

1.94

±1.0

±B.O

RoUT> 20 MO Typical
Full Scale Current

VREF = 10.000V
R14, R15 = 5.00Okn
TA=+25OC

Full Scale Symmetry

IFS4-IFS2

For More Information call 1-800-722-7074.

1.94

Raytheon Semiconductor

3-143

DAC08
Electrical Characteristics (continued)
DAC-OSC

DAC-08E
Parameters

Test Conditions

Min

Zero Scale Current
Output Current Range

VREF. +lSV,

Typ

Max

0.2

2.0

Min

Typ

Max

0.2

4.0

Units
~

2.1

2.1

mA

4.2

4.2

mA

-Vs = -10V
R14, R15 = S,OOOkn

VREF=+25V,
-Vs = -12V

Logic Input Levels
Logic "0"

0.8

VLC=OV

Logic "1"
Logic Input Current

2.0

VIN = -10V to +0.8V

Logic "1"

VIN = 2.0V to 18V

Logic Input Swing

-VS =-lSV

-10

Logic Threshold Range l

VS=±lSV

-10

Reference Bias Current

Negative
Power Supply Current
PosHive

~

2.0

-2.0

-10

-2.0

-10

0.002

10

0.002

10

-1.0

Reference Input Slew Rate 1

PosHive

V

VLC .. OV

Logic "0"

Power Supply SensHivity

0.8

4.0

+18

-10

+13.S

-10

-3.0

8.0

-1.0
4.0

+18

V

+13.S

V

-3.0

8.0

~

mA/J,ls

+Vs = 4.SVto 18V
-Vs = -4.SVto -18V

±O.OOO3 ±D.Ol

±D.0003 ±D.01

IREF= 1.0 mA

±D.002 ±D.Ol

±O.OO2 ±D.01

o/eNS

-%/N
-

Vs=±5·0V,

2.3

3.8

2.3

3.8

Negative

IREF = 1.0 mA

-4.3

-S.8

-4.3

-S.8

PosHive

Vs = +S.OV, -lSV,

2.4

3.8

2.4

3.8

Negative

IREF=2.0 mA

-6.4

-7.8

-6.4

-7.8

PosHive

VS=±lSV

2.S

3.8

2.S

3.8

IREF=2.0 rnA

-6.S

-7.8

-6.S

-7.8

Vs =±5·0V

33

48

33

48

mW

103

136

108

136

mW

135

174

135

174

mW

Negative

mA

mA

mA

IREF -1.0 mA
Power Consumption

Vs = +S.OV, -lSV,
IREF =2.0 mA
VS=±lSV
IREF=2.0 mA

3-144

Raytheon Semiconductor

For More Information call 1-800·722·7074.

DAC08
Typical Performance Characteristics

-

OmA

~

AI bits swltdted ON

I

r-....

,... -

........

- *:
-

1.0mA I-

~-

~

~

2.0mA

........

I

" , 10"'"

lL

- r.I

r- -

I

lOUT
f!

I
50 naJDlvlalon
IFS -2mA

(11111111)

True and Complementary Output Operation

Full Scale Settling Time

I:

Input O.4V

loUT

1\-1110
112 LSB - 4JIA

:

BitS 2.4V
logic

I

!

II

0.4V

;

I

IREF =2 mA

(00000000)

Loglo
Input

OUtput -112 LSB
0
SeIling +112 LSB

-I-

r-.... 1'00.

I

lOUT

2.4V

OV
BJ,lA

;-

0

I
- .- - -,-I
y

-;-

I

2.5V

\I:
I

0.5V
.Q.5A

50 nslDlvlslon
lOUT

LSB Switching
5
TA=TMINtoTMAX
All bits "HIGH"

4

o

/'
o

./

--

:. -=- !\.- - -,-'

-2.SmA

1\
\

/'

J-

~

I

200 nS/Dlvlslon
REO (Input) = 2000
1\= 100n

CcaO
RIN"SK
+VIN .. 10V

"- Umltfor
·Vs=-SV

2

--Z - ~

I

Limit for -Vs = -15V

/'

!
I

Fast Pulsed Reference Operation
4

3

IREF(mA)

Full Scale Output Current vs. Reference Current
10

iii

:!.

8

RI4=RI5=1 lin

6

RL~5000

2

VRI5 =OV

4 All Bits "ON"

1 0
c5 -2

_~

;i-

-4
-6

Cc =1 15 ~F.IV~N ~I~

'-

'\

.\.

Centered at +IV large signal
-10 Cc " 15 pF. VIN = 50 mVp•p
-12 Centered at +200 mV small signal"
-14
0.1
1

.a

1LS~::61fi"l

1\

'-

p.p

SB = 7.8jIA

1L

'"

0.01

;

0.1

10

IFS(mA)

18

LSB Propagation Delay vs. Full Scale Output Current

10

F(MHz)
llof",,,nN> Inn.ot i=r""""nt'V RA~l'V)nSe

For More Information call 1-600-722-7074.

Raytheon Semiconductor

3-145

DAC08
reference applications, see section entitled "Reference
Amplifier Compensation for Multiplying Applications."

Applications Information
Reference Amplifier Set-up
The DAC-08 is a multiplying D/A converter in which the
output current is the product of a digital number and the
input reference current. The reference current may be fixed
or vary from nearly zero to +4.0 rnA. The full scale output
current is a linear function of the reference current and is
given by:
IFS = ~~

X IREF where IREF =114

In positive reference applications, an external positive
reference voltage forces current through R14 into the
VREF(+) terminal (pin 14) of the reference amplifier.
A1tematively, a negative reference may be applied 10 VREF(-) at
pin 15; reference current flows from ground through R14
into VREF(+l as in the positive reference case. This
negative reference connection has the advantage of a very
high impedance presented at pin 15. The voltage at pin 14
is equal to and tracks the voltage at pin 15 due to the high
gain of the internal reference amplifier. R15 (normally equal
to R14) is used to cancel bias current errors; R15 may be
eliminated with only a minor increase in error.
Bipolar references may be accommodated by offsetting
VREF or pin 15. The negative common mode range of the
reference amplifier is given by: VCM- = -Vs plus (IREF x 1
kQ) plus 2.5V. The poSitive common mode range is +Vs
less 1.5V.
When a DC reference is used, a reference bypass
capacitor is recommended. A 5.0V TIL logic supply is not
recommended as a reference. If a regulated power supply
is used as a reference, R14 should be split into two
resistors with the junction bypassed to ground with a 0.1 (.IF
capacitor.
For most applications, the tight relationship between IREF
and IFS will eliminate the need for trimming IREF. If
required, full scale trimming may be accomplished by
adjusting the value of R14, or by using a potentiometer for
R14. An improved method of full scale trimming which
eliminates potentiometer T.C. effects is shown in the
recommended full scale adjustment circuit.
Using lower values of reference current reduces negative
power supply current and increases reference amplifier
negative common mode range. The recommended range
for operation with a DC reference current is +0.2 rnA to
+4.0 mA.
The reference amplifier must be compensated by using a
capacitor from pin 16 to -VS. For fixed reference operation,
a 0.Q1 (.IF capacitor is recommended. For variable
3-146

MuHlplylng Operation
The DAC-08 provides excellent multiplying performance
with an extremely linear relationship between IFS and
IREF over a range of 4.0 ~ to 4.0 rnA. Monotonic
operation is maintained over a typical range of IREF from
100 ~ to 4.0 rnA.

Reference Amplifier Compensation for MuHlplylng
Applications
AC reference applications will require the reference
amplifier to be compensated using a capacitor from pin
16 to -VS' The value of this capaCitor depends on the
impedance presented to pin 14; for R14 values of 1.0,
2.5, and 5.0 kn, minimum values of Cc are 15, 37, and
75 pF. Larger values of R14 require proportionately
increased values of Cc for proper phase margin.
For fastest response to a pulse, low values of R14
enabling small Cc values should be used. If pin 14 is
driven by a high impedance such as a transistor current
source, none of the above values will suffice and the
amplifier must be heavily compensated which will
decrease overall bandwidth and slew rate. For R14 =1.0
kn and Cc = 15 pF, the reference amplifier slews at 4.0
mAl~ enabling a transition from IREF = 0 to IREF = 2.0
mAin 500 ns.
Operation with pulse inputs to the reference amplifier
may be accommodated by an alternate compensation
scheme. This technique provides lowest full scale
transition times. An internal clamp allows quick recovery
of the reference amplifier from a cutoff (I REF = 0)
condition. Full scale transition (0 to 2.0 mAl occurs in
120 ns when the equivalent impedance at pin 14 is 200n
and Cc = O. This yields a reference slew rate of 16 mAl
~ which is relatively independent of RIN and VIN values.

Logic Inputs
The DAC-08 design incorporates a unique logic input
circuit which enables direct interface to all popular logic
families and provides maximum noise immunity. This
feature is made possible by the large input swing
capability, 2.0 ~ logic input current and completely
adjustable logic threshold voltage. For -VS =-15V, the
logic Inputs may swing between -10V and +18V. This
enables direct interface with +5V CMOS logic, even
when the DAC-08 is powered from a +5V supply.
Minimum input logic swing and minimum logic threshold
voltage are given by: -VS plus (IREF x 1.0 kQ) plus 2.5V.
The logic threshold may be adjlJsted over a wide range

Raytheon Semiconductor

For More Information call 1-1300-722-7074.

DAC08
by placing an appropriate voltage at the logic threshold
control pin (pin 1, VLC)' VTH is nominally 1.4V above
VLc. For m and OTl interface, simply ground pin 1.
When interfacing ECl an IREF =1.0 mA is
recommended. For general setup of the logic control
circuit, it should be noted that pin 1 will source or sink
100 J,1A typical; external circuitry should be designed to
accommodate this current.

compliance, reference amplifier negative common mode
range, negative logic Input range, and negative logic
threshold range; consult the various figures for guidance.
For example, operation at -4.5V with IREF = 2 mA Is not
recommended because negative output compliance
would be reduced to near zero. Operation from lower
supplies is possible. However, at least 8V total must be
applied to insure turn-on of the internal bias network.

Fastest settling times are obtained when pin 1 sees a low
impedance. If pin 1 is connected to a 1.0 kn divider, for
example, it should be bypassed to ground by a 0.01 !tF
capacitor.
Analog Output Currents

Symmetrical supplies are not required, as the OAC-08 is
quite insensitive to variations in supply voltage. Battery
operation is feasible as no ground connection is
required. However, an artificial ground may be used to
insure logic swings, etc. remain between acceptable
limits.

Both true and complemented output sink currents are
provided where lOUT + lOUT =IFS ' Current appears at
the "true" output when a "1" is applied to each logic input.
As the binary count increases, the sink current at pin 4
increases proportionally, in the fashion of a "positive
logic' O/A converter. When a "0" is applied to any input
bit, that current is turned off at pin 4 and turned on at pin
2. A decreasing logic count increases lOUT as in a
negative or inverted logic O/A converter. Both outputs
may be used Simultaneously. If one of the outputs is not
required it must still be connected to ground or to a point
capable of sourcing IFS; do not leave an unused output
pin open.
Both outputs have an extremely wide voltage compliance
enabling fast direct current-to-voltage conversion through
a resistor tied to ground or other voltage source. Positive
compliance is 36V above -Vs and is independent of the
positive supply. Negative compliance is given by -Vs
plus (I REF x 1.0 kn) plus 2.5V.
The dual outputs enable double the usual peak-to-peak
load swing when driving loads in quasi-differential
fashion. This feature is especially useful in cable driving,
CRT deflection, and other balanced applications such as
driving center-tapping coils and transformers.

Power consumption may be calculated as follows:
Pd = (1+) (+Vs) + (1-) (-Vs) + (2I REF) (-Vs). A useful
feature of the OAC-08 design is that supply current is
constant and independent of input logic states; this is
useful in cryptographic applications and further serves to
reduce the size of the power bypass capacitors.

Temperature Performance
The nonlinearity and monotonicity specifications of the
OAC-08 are guaranteed to apply over the entire rated
operating temperature range. Full scale output current
drift is typically ±1 0 ppl'Tll"C, with zero scale output
current and drift essentially negligible compared to 1/2
lSB.
The temperature coefficient of the reference resistor R14
should match and track that of the output resistor for
minimum overall full scale drift. Settling times of the
OAC-08 decrease approximately 10% at -55°C; at
+1250C an increase of about 15% is typical.

Power Supplies
The OAC-08 operates over a wide range of power supply
voltages from a total supply of 9V to 36V. When
operating at supplies of :i5.0V or less, IREF ~ 1.0 mA is
recommended. low reference current operation
decreases power consumption and increases negative

For More Information call HlOO-722-7074.

Raytheon Semiconductor

3-147

I
:

DAC08
Typical Applications

LSB

MSB

For fixed reference TTL operation,
typical values are:

VLC
+VREF

255

RREF

256

V REF = +10.000V
RREF = 5.000K
R15 = RREF
Cc = 0.01 (JF

VLC =OV (Ground)

IFs = - - x - lOUT + lOUT

= IFS for all logic states

&!HI186

Figure 1. Basic Posttive Reference Operation

-

LowT.C.

liN

4.SK

O-.JVI.fIr-*-I +YREF
RIN (14)
(15)

39K

DAc-oa

'YREF

10K>_.._----o-,.,.",.r
Pot

IREF Peak Negative Swing 01 liN

::: 1V

v

(15) - REF
86-0188

DAC-08

High Input
Impedance

-

R15

-YREF
(15)L-_ _ _ _ _ _J

(Optional)

Figure 3. Recommended Full Scale Adjustment Clrcutt

+YREF Must be above Peak Positive Swing 01 YIN
65-0187

Figure 2. Accommodating Bipolar References

3-148

Raytheon Semiconductor

For More Infonnation call HIOO-722-7074.

DAC08
Typical Applications (Continued)

IWF

14 +VREF

loUT

loUT

lOUT

IOiiT

DAC-08

'::'

-v_

'Fa- +V_
-V!!EF
IWF Sels

R15

15 -YREF

'FS : R151a far bias current canceUaIlon.

..

....

B1 B2B3B4BS B5
Scale
1 1 1 1 1 1
Full Scale
Half Scale +l.SB 1 o 0 o 0 0
1 o 0 o 0 0
Half Scale
Half Scale ·LSB 0 1 1 1 1 1
Zero Scale +I.SB 0 0 0 0 0 0
o 0 0 0 0 0
Zero Scale

B7B8 lou.,mA IourmA
1 1 1.992 0.008
o 1 1.008 0.984
o 0 1.000 0.992
1 1 0.992 1.000
0 1 0.008 1.984
0 0 0.000 1.992

Eour

Eour

-9.660
-5.040
·S.oOO
....960
.0.040
0.000

.0.000
....920
... .960
-5.000
-9.920
-9.960
1&00.10

FIgure 4. Basic Negative Reference Operation

Figure 5. Basic Unipolar Negative Operation

+10.000v
B1 B2
Poe Ful Scale
1 1
Poe Ful Scale - LSB 1 1
Zeto Scale + LSB
1 0
Scale

10.0001<

,__ 2mA

-

ZeIDScaie
1
Zero Scale - LSB
0
Neg Full Scale + LSB 0

Neg Fun Scale

0

0
1
0
0

B3 B4 BSB6 B7 B8
1 1 1 1 1 1
1 1 1 1 1 0
0 0 0 0 0 1
o 0 o 0 0 0
1 1 1 1 1 1
0 0 0 0 0 1
0 0 o 0 0 0

Eour

Eour

-9.920
-9.840
.0.080
0.000
+0.080
+9.920
+10.000

+10.000
+9.920
+0.160
+0.080
0.000
-9.840
-9.920

Figure 6. Basic Bipolar Output Operation

10K
+1SV

MSB

2
VoUT -+10V

5.000K

LSB
B1 B2 B3 B4 B5
Scala
1 1 1 1 1
Pos Fun Scale
1 0 0 o 0
Zero Scala
Neg Full Scala + 1 LSB 0 0 0 o 0
o 0 o 0 0
Neg Full Scale

5.000K
6

5.000K

B6
1
0
0
0

B7
1
0
0
0

B8
1
0
1
0

EOUT
+4.960
0.000
-4.960
-5.000

+15V -15V

Figure 7. Offset Binary Operation

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-149

I

DAC08
Typical Applications (Continued)
>-+--o EouT

DAC-08

For complementary output (operation as a negative logic (OAC)
connect Inverting Input of op amp to I~ (pIn 2) ; connect loUT
(pin 4) to ground.

85-0183

Figure 8. Posttive Low Impedance Output Operation

EoUT

DAC-08

o to +IFS· Rl
IFs =

For complementary output (operation as a negative logic (DAC)
connect inverting input of op amp to lOUT (pin 2) ; connect lOUT
(pin 4) to ground.

255

'2s6

109 IRF

65-0194

Figure 9. Negative Low Impedance Output Operation

ECl

CMOS, PMOS/NMOS
+Vs

To Pin 1

t--OV lC
6.2K

To Pin 1
VlC
I R3
' 400 IlA

-5.2V

Temperature Compensating VlC Circuits

65-0195

Figure 10. Interfacing Wtth Various Logic Families

3-150

Raytheon Semiconductor

For More Information call 1-800-722-7074.

DAC08
Settling TIme
The DAC-08 is capable of extremely fast settling times,
typically 85 ns at IREF =2.0 mAo Judicious circuit design
and careful board layout must be employed to obtain full
performance potential during testing and application. The
logic switch design enables propagation delays of only 35
ns for each of the 8 bits. Settling time to within 1/2 LSB
is therefore 35 ns, with each progressively larger bit
taking successively longer. The MSB settles in 85 ns,
thus determining the overall settling time of 85 ns.
Settling to 6-bit accuracy requires about 65 to 70 ns. The
output capacitance of the DAC-08 including the package
is approximately 15 pF; therefore the output RC time
constant dominates settling time if RL > 500n.
Settling time and propagation delay are relatively
insensitive to logic input amplitude and rise and fall times,
due to the high gain of the logic switches. Settling time
also remains essentially constant for IREF values down to
1.0 m~, ~ith gradual increas~s for lower IREF values.
The principal advantage of higher IREF values lies in the
ability to attain a given output level with lower load
resistors, thus reducing the output Ftc time constant.

Measurement of settling time requires the ability to
accurately resolve ±4.0 ~, therefore a 1.0 k.Q load is
needed to provide adequate drive for most oscilloscopes.
The settling time fixture uses a cascade design to permit
driving a 1.0 k.Q load with less than 5.0 pF of parasitic
capacitance at the measurement node. At IREF values of
less than 1.0 mA, excessive RC damping of the output is
difficult to prevent while maintaining adequate sensitivity.
However, the major carry from 01111111 to 10000000
provides an accurate indicator of settling time. This code
change does not require the normal 6.2 time constants to
settle to within :W.20/0 of the final value, and thus settling
times may be observed at lower values of IREF"
DAC-08 switching transients or "glitches· are very low
and may be further reduced by small capacitive loads at
the output at a minor sacrifice in settling time.
Fastest operation can be obtained by using short leads,
minimizing output capacitance and load resistor values,
and by adequate bypassing at the supply, reference and
VLC terminals. Supplies do not require large electrolytic
bypass capacitors as the supply current drain is
independent of input logic state: 0.1 pF capaCitors at the
supply pins provide full transient protection.

For Turn-0n, VL = 2.7V
For Turn-0ff, VL = 0.7V

Minimum
Capacitance
+0.4V - ,

VCL

0.7V o--.....-

___- - l
1K

OV

ov

2K

RREF
+VREF

-=

L-

-O.4V....r-

n--.l\M>.---l

15
.--1t,N\,.--l

-vREF

R15

+Vs
13

-15V

to D.U.T.

0.1 IJF ;I:_

I_ 0.1 IJF
+15V

-15V

Figure 11. Settling Time Test Fixture
For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-151

I
.-

DAC08

3-152

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI012
TDCI012
Monolithic Digital-to-Analog Converter

I

12-Bit, 20 Msps

Description

Features

The TDC1012 is a ffi compatible, 12-bit monolithic
D/A converter capable of converting digital data into an
analog current or voltage at data rates in excess of 20
Megasamples per second (Msps).

•
•
•
•

The analog performance has been optimized for
dynamic performance, with very low glitch energy. The
dual outputs are able to drive 50n load with 1 Vo~
output levels while keeping a spurious-free-
Q'"

3-154

16 CONV

06
05 10

15 VCC

D4 11

14 01 (MSB)

03 12

13 O2

24075A

28 Contact Chip Carrier-C3 Package
28 Leaded Plastic Chip Carrier-R3 Package

17 FT

0GNO 8

24076A

24 Pin Hermetic Ceramic DIP-J7 Package
24 Pin Plastic DIP-N7 Package

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TDCI012
Functional Description

Reference

General Information
The TOCl 012 consists of five major circuit sections: the
LSB data register, the MSB decode block, the decoded
MSB register, the current switch array, and the reference
amplifier. All data bits are registered just before the
current switches to minimize the temporal skew that would
generate glitches.

The TOCl 012 has two reference inputs: REF+ and REF-.
These are the inverting and non inverting inputs of the
Internal reference amplifier. An externally generated
reference voltage is applied to the REF- pin. Current flows
into the REF+ pin through an external current setting
resistor (RREF). This current is the reference current (IREF)
which serves as an Internal reference for the current
source array. The output current for an input code N from
OUT+ is related to IREF through the following relationship:

Th~re

are three major OfA architectures: segmentated,
weighted current sources, and R-2R. In segmentated
converters there is one current source for each possible
output level. The current sources are equally weighted
and for an input code of N, N current sources are turned
on. An N bit segmented OfA has 2N-l current sources.
A weighted current source OfA has one current source for
each input bit, and a binary weighting for the current
sources. In ~n R-2R 0/A. there is one current source per
bit and a resistor network which scales the current sources
to have a binary weighting. When transitioning from a
code of 011111111111 to 100000000000, both the
R-2R OfA and Binary weighted O/A are turning some
current sources on while turning others off. If the timing is
not perfect, there is a moment where too many current
sources are either on or off, resulting in a glitch. In a
segmented architecture, 2047 of the current sources
remain on, and one more is turned on to increment the
output - no possibility of a glitch.
The TOCl 012 uses an architecture with the 6 MSBs
segmented and the 6 LSBs form a R-2R network. The
result is a O/A converter which has very low-glitch energy,
and a moderate die size.

Power. Grounds
The TOCl 012 requires a -5.2V power supply and a +5.0V
power supply. The analog (VEEA) and digital (VEED) supply
voltages should be decoupled from each other, as shown
in the Typical Interface Circuits. The VCC pin should be
consi~ered a digital power supply. The O.llJF decoupling
capacitors should be placed as close as possible to the
power pins. The inductors are simple ferrite beads and are
neither critical in value nor always required.

For More Information call 1-800-722-7074.

lOUT =N x IREF
64
Where N is the value of the input code
This means that with an IREF that is nominally 625~, the
full scale output is 40mA, which will drive a 50Q load in
parallel with a 50Q transmission line (25Q total load) with
a lV peak to peak signal. The impedance seen by the REFand REF+ PinS should be approximately equal so the effect
of amplifier input bias current is minimized. The TOC1012
has been optimized to operate with a reference current of
625J.IA. Significantly increasing or decreasing this current
may degrade the performance of the device.
~he

minimum and maximum values for VREF and IREF are
listed In the table of Operating conditions. The internal
reference amplifier is externally compensated to assure
stability. To compensate this amplifier, a O.llJF capacitor
should be connected between the CaMP pin and VEEA.
The amplifier has been optimized to minimize the settling
time, and as a result should be considered a DC amplifier.
Performance of the TOCl 012 operating in a multiplying OfA
mode IS not guaranteed.
Stable, adjustable reference circuits are shown in the
Typical Interface Circuits, 5, 6and 7.

Digital Inputs
The data inputs are TTL compatible. The TOCl 012 is
specified with two sets of setup and hold times. One of
these pairs of specifications guarantees the performance
of the TOCl 012 to specifications listed in the Minimum
and Maximum columns of the System performance
characteristics table.

Raytheon Semiconductor

3-155

I

TDCI012
The second more rigid specification is recommended for
applications where lowest possible glitch and highest
SFDR are desired. The more stringent ts and tH ensure
that the data will not be slewing during times critical to the
TOC1 012, and will minimize the effects of capacitively
coupled data feedthrough and optimize SFDR performance.
Another method for reducing the effect of capacitive
coupling is to slow down the slew rates of the digital
inputs. This has been done in the circuit shown in the
Typical Interface Circuitsby the addition of 50Q series
resistors to the data lines.

Clock and Feedthrough Control
The TOC1 012 requires a TTL clock signal (CONV) Data is
synchronously entered on the rising edge of CONV. The
CONV input is ignored in the Feedthrough (FT = HIGH)
mode. The Feedthrough (FT) pin is normally held LOW.
where the TDC1 012 operates in a clocked mode (the output
changes only after a clock rising edge). An internal pulldown resistor is provided,and this pin may be left open for
clocked operation.
For certain applications, such as high-precision successive
approximation AID converters, throughput delay may be
more important then glitch performance. In these cases,
the FT pin may be brought HIGH, which makes the input
registers transparent. This allows the analog output to
change immediately and asynchronously in response to the
digital inputs.

3-156

Since skew in the bits of the input word will result in
glitches, and will affect settling time, it is recommended
that the TOC1 012 be operated in clocked mode for most
applications.

Analog Outputs
Two simultaneous and complementary analog outputs are
provided. Both of these outputs are full-power current
sources. By driving the current source outputs into a
resistive load, they may be used as voltage outputs. OUT+
provides a 0 to -40mA output current (0 to -1 V when
terminated in 25Q) as the input code varies from
0000 0000 0000 to 1111 1111 1111. OUT-varies in a
complementary manner from -40 to OmA (-1 to OV when
terminated with 25Q) over the same code range. (See the
Input Coding Table.)
The output current is proportional to the reference current
and the input code. The recommended output termination
is 25Q. This can be provided by placing a 50Q source
resistor between the output pin and ground, then driving a
terminated 50Q transmission line. With this load, the
output voltage range of the converter is 0 to -1.0V.
If a load is capacitively coupled to the TOC1 012, it is
recommended that a 25Q load at DC, as seen by the
TOC1 012, continue to be maintained. The output voltage
should be kept within the output compliance voltage range,
VOC, as specified in the Electrical characteristics
table, or the accuracy may be impaired.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI012
Package Interconnections
Signal Type

Signal
Name

Function

Power

VCC
AGND
DGND
VEEA
VEED

Digital Supply Voltage
Analog Ground
Digital Ground
Analog Supply Voltage
Digital Supply Voltage

Reference

REFREF+
COMP

Value

J7&N7
Package Pins

C3&R3
Package Pins

+5.0V
O.OV
O.OV
-5.2V
-5.2V

15
5
8
18
22

26
13
17
1
5

Reference Voltage Input
Reference Current Input
Compensation Capacitor

-1.0V
625!lA
0.1j.lf, see text

19
20
21

2
3
4

14
13
12
11
10
9
23
24
1
2
3
4

24
23
22
21
20
19
6
7
8
9
10
11

17

28

-~

Data Inputs

Feedthrough

01 (MSB)

Most Significant Bit

02
03
04
05
06
07
08
09
010
011
012 (LSB)

Least Significant Bit

TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL

FT

Feedthrough Mode Control

TIL

Convert

CONV

Convert (Clock) Input

TIL

16

27

Analog Output

OUT+
OUT-

Analog Output
Analog Output

Ot040mA
40 to OmA

6
7

14
15

Input Coding Table l
Input Data
MSB
LSB

OUT+(mA)

VOUT+(mV)

OUT-(mA)

VOUT-(mV)
-1000.00
-999.75
-999.52

0000 0000 0000
0000 0000 0001
0000 0000 0010

0.000
0.009
0.019

0.00
-n.24
-n.49

40.000
39.990
39.980

011111111111
1000 0000 0000

19.995
20.005

-499.88
-500.12

20.005
19.995

111111111101
111111111110
111111111111

39.980
39.990
40.000

-999.52
-999.75
-1000.00

0.019
0.009
0.000

Note:

···
·
···

···
·
···

···
·

··
·

···
·
···

-500.12
-499.88

-n.49
-n.24
0.0

1. IREF = 6251JA. RLOAO = 25(1

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-157

I

TDCI012
Figure 1. Timing Diagram

CONY

~--r-~------------+-~----------------JI
DY

OUT-

-IV
tSET

±1/2LSB
24077A

Figure 2. Equivalent Input Circuits
-----------~--_--------- AGND

CONYERT, ~ & DATA (0 1•12)
yCC------.----1----~~---

REF -

0-----------1---1

REF + 0---._----1

-1.3Y

INPUT 0---....1\1\1\.................

REFERENCE
SEGMENT
SWITCH

I BIAS

----+-----~~-----+------~YE~

DYREF

-------------f.---------

~ED

3-158

21139A

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

TDCI012
Figure 4. Output Test Load

Figure 3. Equivalent Reference and Output Circuits

TEST LOAD:
r-----~~+---~----~--~O~+

...----<""""'''-'>__-+--_--0----0 OUT·

REF+

o---+_--iH-,

REF·

o----i---f

OUT +
OUT·

D-_------....--.. OTO·l VOLT

21346A

I
I
I

I

~~--------~------------~~----------VE~

L•••
COMP

21345A

Absolute maximum ratings (beyond which the device may be damaged)1
Supply Voltages
VCC
VEEA
VEEA
VEED
AGND

(Measured to DGND) ..............................................................................................................................................--{J.5 to +7.0V
(Measured to AGND) ..............................................................................................................................................-7.0 to +0.5V
(Measured to VEED) ...............................................................................................................................................-50 to +50mV
(Measured to DGND) ..............................................................................................................................................-7.0 to +0.5V
(Measured to DGND) ..............................................................................................................................................--{J.5 to +0.5V

Inputs
CDNV, FT, D1-12 (Measured to DGND)2 ................................................................................................................... VCC +0.5 to -0.5V
CONV, FT, DI-12 Current, Externally Forced3 ..............................................................................................................................±3mA
REF+, REF-, Applied Voltage (Measured to AGND)3 ........................................................................................................ VEEA to +OV
REF+, REF-, Current, Externally Forced 3 .......................................................................................................................................±3mA

Outputs
OUT+, OUT-, Applied Voltage (Measured to AGND)2 ......................................................................................................-2.0 to +2.0V
OUT+, OUT-, Current, Externally Forced3 .................................................................................................................................... +50mA
Short·Circuit Duration (Single Output to GND) ........................................................................................................................ unlimited

Temperature
Operating, Ambient
(Plastic Package) ....................................................................................................................................................................-20 to +90°C
(Ceramic Package) ...............................................................................................................................................................-60t0 +150°C
Junction
(Plastic Package) .............................................................................................................................................................................. +140°C
(Ceramic Package) ...........................................................................................................................................................................+200°C
Lead, soldering (10 seconds) ..........................................................................................................................................................+300°C
Storage ...................................................................................................................................................................................-65 to +150°C
Note:

1. Absolute maximum ratings are limited values applied individually while other parameters are within specified operating conditions. Functional operation
under any of these conditions is NOT implied. Device performance and reliability are guaranteed only if the Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range. Current is specified as conventional current flowing into the device.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-159

TDCI012
Operating conditions
Temperature Range
Parameter

Min

Standard
Nom
Max

Min

Extended
Max
Nom

Units

VCC
VEED
VEEA
VAGND
VEEA

Positive Supply Voltage (Measured to DGND)
Negative Supply Voltage (Measured to DGND)
Negative Supply Voltage (Measured to AGND)
Analog Ground Voltage (Measured to DGND)
Negative Supply Voltage (Measured to VEED)

tpWL
tpWL

CONV Pulse Width LOW (to Meet Specification)
CONV Pulse Width LOW (to Optimize SFDR)

20
20

20
20

ns
ns

tpWH
tpWH

CONV Pulse Width HIGH (to Meet Specifications)
CONV Pulse Width HIGH (to Optimize SFDR)

20
20

20
20

ns
ns

ts
ts

Setup Time, Data to CONV (to Meet Specification)
Setup Time, Data to CONV (to Optimize SFDR)

25
32

25
36

ns
ns

tH
tH

Hold Time (to Meet Specifications)
Hold Time (to Optimize SFDR)

1
4

1
6

ns
ns

tSF
tHF

Setup Time, Data to FT
Hold Time, Data to FT

5
28

7
32

ns
ns

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

2.0

VREF
IREF

Reference Voltage (REF-)
Reference Current (REF+)

-0.7
550

Cc

Compensation Capacitor

0.01

TA
TC

Ambient Temperature, Still Air
Case Temperature

0

4.75
-4.9
-4.9
-0.1
-20

5.0
-5.2
-5.2
0.0
0

5.25
-5.5
-5.5
0.1
20

4.5
-4.9
-4.9
-0.1
-20

5.0
-5.2
-5.2
0.0
0

0.8

5.5
-5.5
-5.5
0.1
20

0.8

V
V

-1.3
675

V

2.0
-1.0
625

-1.3
700

0.1

-0.7
575

-1.0
625

0.01

0.1

!lA
~

70
-55

V
V
V
V
mV

125

°c
°C

Notes: 1. A common power supply isolated with ferrite bead inductors is recommended for VEEA and VEED. This is shown in the Typical Interface Circuits.

3-160

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI012
Electrical characteristics within specified operating conditions
Temperature Range
Standard
Min
Max

Test Conditions

Parameter

VEEA=VEED=Max,static
TA=Oto 70°C
TA=70°C
TC=-55 to 125°C
TC=125°C
Vcc=Max, Static
TA=Oto 70°C
TA=70°C
TC=-55 to 125°C
TC=125°C

IEEA+IEED

ICC

Extended
Min
Max

-180
-150
-200
-150
25

Reference Input Capacitance
Digital Input Capacitance

15
15

VDC
RO

Compliance Voltage
Output Resistance

Co
10

Output Capacitance
Full Scale Output Current

IREF=Nominal

IlL
IIH

Input Current, Logic LOW
Input Current, Logic HIGH

VCC, VEE=Max, VI=0.4V
VCC, VEE=Max, VI=2.4V

-10
-10

50
100

-10
-10

11M
VTH

Input Current, Max Input Voltage
Logic InputThreshold Voltage,Typical

VCC, VEE=Max, VI=VCC Max
VCC, VEE=Nom, TA=25°C

-10
1.25

100
1.55

-10
1.25

-1.2
12

1.2

-1.2
12

45

rnA
rnA
rnA

15
15

pF
pF

1.2

V
kQ

45

pF
rnA

50
100

IlA
IlA

100
1.55

~
V

40

40

rnA
rnA
rnA
rnA
rnA

35
24

20

CREF
CI

Units

Switching characteristics
Temperature Range
Parameter
FD
tDC
tDD
tDF
tR
tF
tSET

Maximum Data Rate
Clock to Output Delay
Data to Output Delay
FTto Output Delay
Risetime
Falltime
Settling Time, Voltage

For More Information caJI1-800-722-7074.

Test Conditions
VEEA, VEED, VCC = Min
VEEA, VEED, VCC = Min, FT =LOW
VEEA, VEED, VCC = Min, FT = HIGH
VEEA, VEED, VCC = Min
90% to 10% of FSR, FT = LOW
10% to 90% of FSR, FT = LOW
FT = LOW, Full-Scale Voltage
Transition on 10UPo ±O.0188%
FSR

Standard
Min
Typ
Max
20

Raytheon Semiconductor

25

20

Min
20

17
35
35
4
4
30

Extended
Typ
Max
23
20
40

40

20

4
4
35

Units
MHz
ns
ns
ns
ns
ns
ns

3-161

I

TDCI012
System performance characteristics
Temperature Range
Parameter
ELO

Differential Linearity Error

Test Conditions

Standard
Min
Typ Max

VEEA, VEED, Vcc, IREF= Nom 1
TDC1012XXY3
TDC1012XXY2
TDC1012XXYl

ELI

VEEA, VEED, Vcc, IREF= Nom 1
TDC1012XXY3
TDC1012XXY2
TDC1012XXYl
-10

VDS
IB

REF+ to REF- Offset Voltage
REF-Input Bias Current

EG
10F

Absolute Gain Error
Output Offset Current

VEEA, VEED, VCC, IREF= Nom
VEEA, VEED, VCC= Min,
DH2=lOW

PSRR
PSS

Power Supply Rejection Ratio
Power Supply Sensitivity

VEEA. VEED, Vcc, IREF= Nom 2
VCC, VEEA, VEED=4%, IREF=Nom

GA

Peak Glitch Area

SFDR

Spurious Free Dynamic Range

Notes:

3-162

Integral Linearity Error

-5
-5

Extended
Typ Max

60

±O.012

%

±O.024
±O.048
±O.024

±O.024
±O.048
±O.024

%
%
%

±O.048
±O.048

±O.048
±O.048

%
%

+10
10

f.IA

5

%

+5

f.IA

-48
-140

dB

+10
5

-10

5

-5

+5

-5

25

45
60

70
75
78

Units

±O.012

-50
-140
25

IREF=Nom,20Msps,
10MHz bandwidth
Fou t=6MHz
Fou t=5MHz
Fout=2MHz
Fout=lMHz

Min

45

mV

f.IA/V
pV-sec
dBc

dBc
dBc
dBc

1. OUT-connected to AGND, OUT+driving virtual ground.
2. 120 Hz, 600 mV p-p ripple on VEE and Vee.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI012
Typical Performance Curves (Typical Settling Time Characteristics)
A. Full-Scale Output Transition, Rising Edge
-.0007

B. Settling Time, Full-Scale Output, Rising Edge

rn-rrn""""__- __- __- ___

0.000

Conditions
Output Load: RL = 25Q
CL < 5pF
Temp: Ambient
Supply Voltages: Nominal

1~

Conditions
Output Load: RL = 25Q
CL < 5pF
Temp: Ambient
Supply Voltages: Nominal

I--tSET

± 1/2 LSB



.

0

+,

to.l

..-

C

E

Z

ct

 CLK

'>-+--+---1 10

1 0 J - - - - - - - - ,... 0 1 (MSB)

")--l---..1f----l 20

)--l---..1f----l 30

U3

'>-+--+---1 40

",,)-1---4---450

20

.. O2

30

.. 0 3

40

.. 0 4

50

.. 0 5

)-1---4---460

60

.. 0 6

)-1---4---470

70

.. 0 7

)-1---4---480

80

.. 0 8

74lS374

REF+ f--REF-I--------.J

TDC1012

+---46
+-+---It> ClK
'>-+-+---110

10 I - - - - - - - I..~ 0 9

'>-+-+---120

20 I - - - - - - - I..~ 010

'>-+--+---130
'>-+-+---140

40 I - - - - - - - -......
I~ 0 12 (LSB)

-50

50 -

-60

60 -

-10

70-

-80

801--

~-F

OUT + 1--=....
1=4-70-1 rr--,4_ A

..... CONY

r--+

FT

q

MINI-CIRCUITS

I~ 011
30 I - - - - - - - -......
U4

OUT-

."

VEEO VEEA 0GNO AGND

74lS374

24088A

3-166

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI012
Figure 6. Typical Interface Circuit with Differential Amplifier Output
c;> Vee

...~>-

~~~
yy,

-"~~
y"

lK:':

I

~A~

1

Y
2K :Y-L.

bJ
Ul

LM611

~

Vee

±

':"

+

jj

~
~

10

lQ

0 1 (MSB)

20

2Q

O2

3Q

03

4Q

04

30
U3

40

"-

~

~
,~

.. >

:.:~1.5K

VCC

ClK

"-

.. >-~

1.5K ::

50

5Q

05

60

6Q

06

70

7Q

07

SO

SQ

Os

REF+

r--

REF-

COMP

74LS374

~f--oVEE

TOC1012

jj
ClK

"

~
~
~,

,"-

10

lQ

09

20

2Q

0 10

30

3Q

011

40

U4

4Q

-

60

6Q -

-

70

7Q

-

-

SO

SQ

-

5Q

50

74LS374

,..

0 12 (lSB)
CONY

=:r=
VEE

For More Information call 1-800-722-7074.

~~'

V EEO V EEA 0GNO AGNO

---1

Raytheon Semiconductor

r....

i,.'A'A'

OUT

FT

...

J,~~.

OUT +

~25
~

>

:.::~25

-c;

l -"NY
100

~loo
24089A

3-167

TDCI012
Figure 7. Typical Interface Circuit with Resistive Load Output

vee
9

lK~

Ul

~~

yyy

Ul~+----------------------------i
~
vee

LM611 -+____
+
__________

~

r--4G
r-II----{> CLK
~>-+--+-----Il D

1 0 1 - - - - - - - -...... 0 1 (MSB)

~>-+--+-----I2D

20

O2

30

03

40

04

~>-+--+-----I30

U3

~>-+--+-----I40

~>-+--+-----160
~>-+--+-----170

50

05

60

06

7Q

07

'>-+--+-----180

80

08

'>-+--+-----150

74LS374

REF+ REF-I---...J

COMP

------;1---0 - 5V

TDC1012

+--+----[> CLK
'>-+--1-----110

,

10 I------------I~ 0 9

>---if---ii-----I20

20

>---if---ii-----I 30

30

011

40

0 12 (LSB)

'>-1--1-----140

U4

0 10

-50

50 f - -

-60

60 f - -

-

70

70f--

-

80

80 I---

CONY
~ FT

OUT + 1------....-----0)

~25
OUT -1----4----....J

74LS374

24D9DA

3-168

Raytheon Semiconductor

For More Information call 1-/100-722-7074.

TDCI012
Using the TDC1 012 and TDC1112 In Sinusoidal
Synthesis Applications
In the past, most waveform synthesis was
performed using analog oscillators, with their
problems of drift, limited versatility, and design
complexity. However, as the cost of highperformance digital circuits and digital-to-analog
converters continues to fall, digital waveform
synthesis is becoming increasingly popular. Direct
digital synthesis (DDS) offers unprecedented levels
of signal stability. Potential signal complexity for
numerous applications including communications,
instrumentation, radar, and medical imaging is also
enhanced by DDS. This application note describes
how exceptional spectral purity can be achieved
with the TDC1 012 and TDC1112 in sinewave
synthesis applications. Board design techniques
which optimize the performance of these D/A
converters is also discussed.
In most applications, the performance of a digital
synthesizer is limited by the digital-to-analog
converter (D/A) employed. Specifications of
interest include maximum allowable sampling
(digital clock) rate, signal-to- [random] noise ratiO,
total harmonic distortion, and spurious-free
dynamic range (SFDR).
With their high linearity and low glitch energy, the
TRW TDC1012 and TDC1112 12-bit and TDC1018
8-bit D/A converters are particularly well suited to
DDS applications. When used with the TRW
TMC2340 Direct Digital Frequency Synthesizer, the
TDC1012 becomes the output stage of a highperformance, low part count digital frequency
synthesizer. The TDC1 012 offers a 20MSPS clock
rate and is TIL-compatible. The TDC1112
operates at up to 50MSPS and is ECl-compatible.
Both parts offer 70dB SFDR for 8 MHz signals
sampled at 20MSPS.
The circuit in Figure 10 can perform with spurs as
low as -70dBc. To maintain a clean clock Signal, a
buffer should drive the clock to the direct digital
synthesis circuitry. The clock oscillator should be
powered from the same decoupled Vee as the D/A
converter.

For More Information call 1-800-722-7074.

Grounding is extremely important. A solid copper
ground plane should be used and connected to
digital ground at only one point to prevent the
formation of ground loops. This minimizes the flow
of digital switching current across the D/A ground
plane.
The use of a balun across the D/A outputs
significantly improves spectral purity, since it
effectively cancels distortion due to the Early
voltage and data feedthrough characteristics of the
D/A converter. In some applications, a 470
picofarad capacitor connected between pin 6 and
pin 7 as close to those pins as possible will be
effective in reducing spurs.
The primary sources of 2nd-harmonic distortion are
insufficient input setup and hold times (ts and tH)
and data feedthrough. Minimum setup and hold
times for the SFDR specification are shown in the
"System Performance Characteristics· section of
the data sheets for the TDC1 012 and TDC1112.
Figure 10 shows a 74AlS374 8-bit register with a
2ns R-C delay (200 Ohm, 10 pF in the clock input
line) that is designed to help meet setup and hold
times for the TDC1012 (when it is operated at
20MSPS) while reducing output slew rates. For
military applications, a 54F374 with a 3ns R-C
delay will meet the extended temperature range
setup and hold time specifications while
maintaining reasonable output slew rates. Note
that the military versions of the TDC1012 and
TDC1112 are available in a 24-pin side brazed
ceramic dual-in-line package which has been
specifically designed to minimize data feedthrough.
For optimum performance, the D/A converter
should be soldered directly to the board. If a
socket must be used, a low profile gold-insert
socket such as Robinson-Nugent part number ICT246-S-TG is recommended.
The primary source of 3rd-harmonic distortion is
the small non-linear component of output
capacitance of the D/A. This can be minimized by
reducing the amplitude of the output voltage swing,
e.g. with the 1:4 impedance ratio balun as shown in
Figure 10. The center tap of the balun can be tied
to a positive voltage generated by two diodes in
series to ground. This will improve the 3rd-

Raytheon Semiconductor

3-169

I

TDCI012
harmonic distortion by around 2dB at the expense
of the power dissipated by the diode biasing circuit.
The D/A output voltage excursions should be
limited to less than +1.2V.
The true harmonic distortion of these circuits can
be masked by the spectrum analyzer under certain
conditions. In particular, the circuit of Figure 10
generates a relatively high output power which can
cause distortion in the internal circuitry of some

spectrum analyzers. This can be avoided by
setting the input attenuation to a higher level,
typically 40dB.
The TDC1012 and TDC1112 D/A converters and
TMC2340 Direct Digital Frequency Synthesizer
make high-performance digital frequency synthesis
cost-effective in applications requiring stability,
spectral purity, and versatility.

Figure 8. The TDC1 012 In a DDS Application

r> ~

5

r - - - - - - - - - - - " ' ' ' ' - JI

----+i

:~ (-~

TT4-IA

DVe

----DVe -

rTr7
I

Mlnl-Circuil,.

UII

Al,\o

'2.5dBM

.t 611Hz

shown

VEE Arl6",---.,o~-.-<
FTI7
CONVI6
VCCI'-I.:;.5_t-_ _~...,
01 14

FerrlLe beads are
F.lr-", te ph. 19141895-2855
PIN 2743881112 or sl"llar

02 13

Oscillotor Is

eTp%KnJk)~:'Hf5n. 18151786-8411
Plelronlcs pn. 12061523-9395
PIN PIIOO-He or slMII.r

I1S8 0 I

Ferrlle
bead

DOS eLKCI---<

vee

3-170

Raytheon Semiconductor

VEE

For More Information call 1-800-722·7074.

TDCI012
Ordering Information
Product
Number

Temperature Range

Screening

Package

Package
Marking

TA=O°C to 70°C
TA=O°C to 70°C
TC=-55°C to 125°C
TA=O°C to 70°C
TC-55°C to 125°C

Commercial
Commercial
MIL-STD-883
Commercial
MIL-STD-883

Plastic DIP
Ceramic DIP
Ceramic DIP
Plastic Chip Carrier
Ceramic Chip Carrier

1012N7C-X
1012J7C-X
1012J7V-X
1012R3C-X
1012C3V-X

TDC1012N7CX
TDC1012J7CX
TDC1012J7VX
TDC1012R3CX
TDC1012C3VX

Linearity Grade (X)
ELD
ELI

Linearity Error, Differential
Linearity Error, Integral

None

1

2

3

±O.096% (4 LSB)
±O.096% (4 LSB)

±O.048% (2 LSB)
±O.048% (2 LSB)

±O.024% (1 LSB)
±O.048% (2 LSB)

±O.OI2% (1/2 LSB)
±O.024% (1 LSB)

40G02291 Rev E 8193

For Mora Information call 1-800-722-7074.

Raytheon Semiconductor

3-171

I

TDCI012

3-172

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI012
TDCI016
Video Speed D/A Converter

I

10-Bit, 20 Msps

Description

Features

The TDC1 016 is a bipolar monolithic digital-to-analog
converter which can convert digital data into an analog
voltage at rates up to 20 Msps (Megasamples Per
Second). The device includes an input data register and
operates without an external deglitcher or amplifier.

•
•
•
•
•
•
•
•

Operating the TDC1 016 from a single -5.2V power
supply will bias the digital inputs for Eel levels, while
operating from a dual fiN power supply will bias the
digital inputs for TTL levels.

•
•

All version of the TDC1 016 are 1O-bit digital-to-analog
converters, but are available with linearity specifications
of either 8. 9, or 10 bits. The TDC1 016 is patented
under U.S. patent number 3283120 with other patents
pending.

20 Msps conversion rate
8, 9, or 10-bit linearity
Voltage output, no amplifier required
Single supply operation (-5.2V, ECl compatible)
Dual supply operation (±5.0V, m compatible)
Internal 10-bit latched data register
Low glitch energy
Disabling controls, forcing full-scale, zero, and
inverting input data
Binary or two's complement input data formats
Differential gain = 1.5%, differential phase = 1.00

Applications
•
•
•

Construction of video signals from digital data 3x or
4x NTSC or PAL color subcarrier frequency
CRT graphics displays, RGB, Raster, Vector
Waveform synthesis

Functional Block Diagram
10 TIL INPUTS
(20 ECL INPUTS)
CLK

TIllECL
DIGITAL
INPUT
BUFFERS

DATA
LATCHES
10

CURRENT
SWITCHES
10

R-2R
RESISTOR
NETWORK

AOUT

10

NDiS
(NDlS)

CLK

VREF

NFL
NFH
N2C
VREF
COMP

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-173

TDCI016
Pin Assignments
NC
VEE
COMP

2

VREF
AGNO
AGNO
AOUT
AGNO
VCC
0GNO
NOIS
ClK
ClK
NOIS
(MSB)
(MSB) 01
N2C

4

Di

3

5
6
7
8
9
10

11
12
13
14
15
16
17

D2

18
02 19
NFH 20

40
39
38
37
36
35

NC
NC
NC
010 (lSB)
DIG (lSB)
09

34Ug
33 08
32
31
30
29
28
27
26
25
24
23

DB

VREF
AGNO
AGNO
AOUT
AGNO
VCC

07

ii7

1
2
3

4
5
6
°GNO 7
NOIS 8
ClK 9

06
Dii
05

Os
04

D4

(MSB) 01 10
N2C 11
02 12

03

2203
21 NFL

40 Pin Ceramic J5 Package

24 COMP
23
22
21
20
19
18
17
16
15
14
13

VEE
010 (lSB)
09
08
07
06
05
04
03
NFL
NFH

24 Pin Ceramic J7 Package

Functional Description

Power

General Information

The TDC1016 can be operated from a single -5.2V
power supply or from a dual ± 5.0V power supply. For
single power supply operation, VCC is connected to
DGND and all inputs to the device become ECl
compatible. When VCC is tied to + 5.0V, the inputs are
TTL compatible:

TTL/ECl buffers are used for all digital inputs to the
TDC1016. logic family compatibility depends upon the
connection of power supplies. When single power supply
(- 5.2VI operation is employed, all data, clock, and
disable inputs are compatible with differential ECl logic
levels. All digital inputs become compatible with TTL
levels when dual power supply (± 5.0VI operation is
used.
The internal 10-bit register latches data on the rising
edge of the clock (ClKI pulse. Currents from the current
sources are switched accordingly and combined in the
resistor network to give an analog output voltage. The
magnitude of the output voltage is directly proportional
to the magnitude of the digital input word.
The NFL and NFH inputs can be used to simplify system
calibration by forcing the analog output voltage to either
its zero-scale or full-scale value. The TDC1016 can be
operated in binary, inverse binary, two's complement. or
inverse two's complement input data formats.

3-174

The return path for the output from the 10 current
sources is AGND. The current return path for the digital
section is DGND. DGND and AGND should be returned
to system power supply ground by way of separate
conductive paths to prevent digital ground noise from
disturbing the analog circuitry of the TDC1016. All AGND
pins must be connected to system analog ground.

Reference
The reference input is normally set to -1.0V with
respect to AGND. Adjusting this voltage is equivalent to
adjusting system gain. The temperature stability of the
TDC1016 analog output (AOUTI depends primarily upon
the temperature stability of the applied reference voltage.

Raytheon Semiconductor

For More Information call 1-800-722·7074.

TDCI016
Reference (cont.)
The internal operational amplifier of the TDC1016 is
frequency stabilized by an external 1 microfarad tantalum
capacitor connected between the COMP pin and VEE. A
minimum of 1 microfarad is adequate for most applications. but 10 microfarads or more is recommended for
optimum performance. The negative side of this capacitor
should be connected to VEE.
Controls
The NDIS inputs are used to disable the TDC1016 by
forcing its output to the zero-scale value Icurrent sources
offl. The NDIS inputs are asynchronous. active without
regard to the ClK inputs. The other digital control inputs
are synchronous. latched on the rising edge of the ClK
pulse.
The rising edge of the ClK pulse transfers data from the
input lines to the internal 10-bit register. In TIL mode.
the inverted inputs for ClK. DATA. and NOIS are inactive
and should be left open.

and NFL are both activated with a logic "0;' the input
data to the 10-bit register is inverted.
Data Inputs
Data inputs are ECl compatible when single power
supply operation is employed. The J5 and C2 packages
allow for differential ECl inputs while the J7 and B7
packages have only single-ended inputs. When
differential ECl data is used. any data input can be
inverted simply by reversing the connections to the true
and inverted data input pins. All inverted input pins
should be left open if single-ended ECl or TIL modes
are used. All data inputs have an internal 40 kOhm pullup resistor to VCC.
Analog Output
The analog output voltage is negative with respect to
AGND and varies proportionally with the magnitude of
the input data word. The output resistance at this point
is 80 Ohms. nominally.
No Connects

The Input Coding Table illustrates the function of the
digital control inputs. A two's complement mode is
created by activating N2C with a logic "0:' When NFH

There are several pins labeled no connect INCI on the
TDC1016 J5 and C2 packages. which have no
connections to the chip. These pins should be left open.

Package Interconnections
Signal
Type

Signal
Name

Function

Value

85 Package Pins

87 Package Pins

Power

VCC
VEE
AGNO
DGND

Positive Supply Voltage
Negative Supply Voltage
Analog Ground
Digital Ground

+5.0V
-5.0V
O.OV
O.OV

9
2
5. 6. 8
10

6
23
2.3.5
7

VREF
COMP

Reference Voltage In
Compensation

-1.0V

4
3

1
24

NDIS
NDiS
ClK
ClK
N2C
NFH
NFL

Not Disable
Not Disable (Inv)
Clock
Clock (lnv)
Not Two's Complement
Not Force HIGH
Not Force lOW

11
14
12
13
17
20
21

8

Reference

Controls

For More Information call 1-800-722-7074.

I/LF
TTL/ECl
ECl
TTl/ECl
ECl
TTL/ECl
TTL/ECl
TTL/ECl

Raytheon Semiconductor

9

11
13
14

3-175

I

TDCI016
Package Interconnections (cont.)
Signal
Tvpe
Oata Inputs

Signal
Name

Function

Value

85 Package Pins

87 Package Pins

16
15
19
18
23
22
25
24
27
26
29
28
31
30
33
32
35
34
37
36

10

01
01
02
02
03
03
04
04
05
05
06
06
07
07
08
08
09
09
010
010

Oata Bit 1 (MSB)
Oata Bit 1 (MSB Inv)

Oata Bit 10 (lSB)
Oata Bit 10 (lSB Inv)

TILJECl
ECl
TTL/ECl
ECl
TIL/ECl
ECl
TIL/ECl
ECl
TTL/ECl
ECl
TTL/ECl
ECl
TIL/ECl
ECl
TTL/ECl
ECl
TTL/ECl
ECl
TIL/ECl
ECl

Analog Output

AOUT

Analog Output Voltage

OVto -IV

7

4

No Connects

NC

No Connect

Open

1,38,39,40

--

Figure 1. Timing Diagram

12
15
16
17

18
19
20
21
22

Figure 2. Analog Output Equivalent Circuit.
TTL and ECl Mode
AGND

DATA,
CONTROLS
CLOCK

AOUT
lCLDCK
INPUT DATA DEPENDENT CURRENT SINK
OUTPUT ------t--~
NOle: 1. Differential Eel mode only

3-176

lOS

Note: 1. 75n requires outside trim

Raytheon Semiconductor

For More Inlormation call 1-800-722-7074.

TDCI016
Figure 3. Digital Input Equivalent Circuit, TTL Mode

Figure 4. Digital Input Equivalent Circuit, ECl Mode

vcc

vee

(+5.0v)

(O.OV)

I

40K
40K

50K

35K

DGNDo----.----+---~r_~~-----

13K

DATA

DATA 0----+----._--1
DATA 0---41-------+-------'
37K

VEE 0-----*-----------*-----

Absolute maximum ratings (beyond which the device will be damagedl'
Supply Voltages
..................................................................................................................................................... -0.5 to +7.0V

Vee (measured To DGND)

VEE (measured To AGND) ........................................................

.......................................................................................... +0.5 to -7.0V

AGND (measured To DGND)

................................................................................... +0.5 to -0.5V

Digital (measured To DGND)

............................................................................................................................................................................ +7.0 to -7.0V

Input Voltages
Reference (measured To AGND) ............................................................................................................................................................................. -1.5 to +0.5V
Output
Applied voltage (measured To AGND) .

................................................................................................................................. +2.0 to -2.0V2

Short-circuit duration .................................. .

................................................................................................................................................. indefinite

Temperature
Operating ambient

............................................................................................ + 125°C

junction .......... .

............................................................................................ + 175°C

................................................................................................................................................ +300o e

Lead, soldering (10 seconds)
Storage ..................................................

....................................................................................................................................................... -65 to +150°C

Notes
Absolute maximum ralings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
Applied voltage must be current limited to specified range.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-177

TDCI016
Operating conditions
Temperature Range
Parameter

Min

Standard
Nom

Max

Min

Extended
Nom

Max

Units

5.0
0.0
-5.0
0.0

5.25
0.25
-5.5
0.1

4.50
-0.25
-4.5
-0.1

5.0
0.0
-5.0
0.0

5.50
0.25
-5.5
0.1

V
V
V
V

VCC

Positive Supply Voltage

VEE
VAGND

Negative Supply Voltage
Analog Ground Voltage (Measured to DGNDI

4.75
-0.25
-4.5
-0.1

tpWl
tpWH

ClK Pulse Width, LOW
ClK Pulse Width, HIGH

15
15

20
20

ns
ns

ts

Input Register Set-up Time

TTL Mode
ECl Mode

20
25
2

22
27
2

ns
ns
ns

TTL
ECl
TTL
ECl

DGND

0.8
-1.67

DGND

0.8
-1.67

2.0
-1.0

VCC

2.0 1
-1.0

VCC

tH

Input Register Hold Time

Vil

logic "0"

VIH

logic "1"

VREF
CCOMP

Reference Voltage
Compensation Capacitor

TA
TC

Ambient Temperature
Case Temperature

TTL Mode
ECl Mode

Mode
Mode
Mode
Mode

-0.8
1.0

-1.0

0

-1.2

-0.8
1.0

-1.0

-1.2

V
V
V
V
V
flF

°c
°c

70
-55

125

Note

Electrical characteristics within specified operating conditions

Parameter

Test Conditions

ICC
lEE
IREF

Power Supply Current
Power Supply Current
Reference Input Current

TTL Mode, VCC ~ Max, VEE
TTL Mode, VCC ~ Max, VEE
VEE ~ Max, VRH ~ -1.0V

III

logic "0" Input Current

TTL
ECl
TTL
ECl

IIH

logic "1" Input Current

COUT Output Capacitance
Digital Input Capacitance
CIN
ROUT Output Resistance

Temperature Range
Standard
Extended
Min
Max
Min
Max

Mode,
Mode,
Mode,
Mode,

VCC
VCC
VCC
VCC

~

~
~

~

~
~

Max
Max

Max, VEE ~ Max
0.0, VEE ~ Max
Max, VEE ~ Max
0.0, VEE ~ Max

AOUT to AGND (Figure 2)
Any Digital Input to DGND
AOUT to AGND (Figure 2)

70

Units

20
-130

20
-150

mA
mA

10

10

flA

-1.0
-300
75
350

-1.0
-300
75
350

flA
flA
flA

10
35
95

35
95

10

70

mA

pF
pF
Ohms

1. Retufil current from VEE flows through AGND'

3-178

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TDCI016
Switching characteristics within specified operating conditions

Parameter
FC

Maximum Data Rate

tDS

Data Turn - on Delay

tSET

Settling Time

Test Conditions

Temperature Range
Standard
Extended
Min
Max
Min
Max

TTL Mode Full-Scale Output Step

20

20

MSPS

ECl Mode Full-Scale Output Step

17.B

17.B

MSPS

Rl

75 Ohms

30

30

ns

TDC101B-B to 0.2%

30
35
40

30
35

ns

40

ns

~

TDC101B-9 to 0.1%
TDC101B-l0 to .05%
tRV

Output 10% to 90% Risetime

Units

VEE

~

Nom, Rl

~

75 Ohms, Full-Scale Step

5.5

ns

5.5

ns

System performance characteristics within specified operating conditions

Parameter
RES

Resolution

ELI, ElD linearity Error Integral and Differential

Independent Based
VOFS
VOZS

Test Conditions

Temperature Range
Standard
Extended
Min
Max
Min
Max

All TDC101B Devices

10

TOC101B-B

10

Units
Bits

0.2

0.2

% FS

TDC1016-9

0.1

0.1

% FS

TDC1016-10

0.075

Full-Scale Output Voltage

VEE

Zero-Scale Output Voltage

VREF ~ -1.000V
VEE ~ Nom, Rl ;, 10 kOhms

~

Nom, Rl ;, 10 kOhms

-0.95

-1.05
± 15

% FS
-0.95

-1.05
± 15

V
mV

VREF = -1.000V
DP

Differential Phase

DG

Differential Gain

NTSC 4x subcarrier 1
NTSC 4x subcarrier 1

GE

Glitch "Energy" IAreal

Rl = 50 Ohms, Midscale

125

125

pV-sec

GV

Glitch Voltage

Rl = 50 Ohms, Midscale

35

35

mV

Note

1.0
1.5

1.0
1.5

Degree
%

1. In excess of theoretICal DP and DG due to quantizing error

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-179

I

TDCI016
Input Coding Table

NDiS

N2C

NFH

NFL

Data

a

x

x

x

xxxxxxxxxx

0.0

1
1

1
1

1
1

1
1

1111111111
0000000000

0.0
-1.0

Binary (Default State for TTL
Mode Control) Inputs Open

1
1

1
1

a

a
0

1111111111
0000000000

-1.0
0.0

Inverse Binary

0

1
1

0
0

1
1

1
1

0111111111
1000000000

0.0
-1.0

Two's Complement

1
1

0

0

0111111111
1000000000

-1.0
0.0

1
1

x
x

a
a

0
0

Inverse Two's Complement

a

1
0

xxxxxxxxxx
xxxxxxxxxx

0.0
-1.0

Force HIGH
Force LOW

Notes:

1

Output

Description
Output Disabled

1. For TIL. 0.0 < Vll < +0.8V is logic "0"
2. For TIL. +2.0 < VIH < +5.oV is logic "1"
3. For ECl. -1.85 < Vll < -1.B7V is logic "0':
4. For ECl. -1.0 < VIH < - 0.8V is logic '''''.
5. x="don't care"

Calibration
The TOC1016 is calibrated by adjusting the voltage
reference to give the desired full-scale output voltage.
The current switches can be turned on either by loading
the data register with full-scale data or by bringing the
NFH input to a logic zero. Note that all 10 current
switches are activated by the NFH input and the
resulting full-scale output voltage will be greater than if
the system used only eight or nine bits for full-scale
data.

The TOC1016 output and currents from the SYNC and
BLANKING inputs are summed and amplified by the
HA2539 wide-band operational amplifier. Note the
careful power supply decoupling at the power input pins
of the amplifier. The output of the circuit is a composite
video signal with SYNC and BLANKING levels coming
from external sources. This technique allows the
TOC1016 to use its entire dynamic range for the video
information while pulses are added by other means.

Typical Application

The reference for the TOC1016 is generated by dividing
the output voltage from a two-terminal band-gap voltage
reference. System gain is calibrated by adjusting variable
resistor R1. Analog and digital grounds should be routed
back to system power supply ground by separate paths.

The Typical Interface Circuit (Figure 5) shows the
TOC1016 in a typical application, reconstructing video
signals from digital data. Television timing signals, SYNC
and BLANKING, are added by injecting current from the
Wilson current source into a resistor divider circuit at the
output of the TOC1016.

3-180

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI016
Figure 5. Typical Interface Circuit
+12V
+5V

+ R14

~J

R15

Rl&

R22

ClOCK

D2
D3
D4

nL DATA
INPIIlS

~4~4·'="

+5V

Ul

05

mc

D&

H21

101&

D7
DB

R4

+12V

09
R5

lIB

Rl1
RID

HI 'GAlN"

COMPOSITE
VIDEO
OUT

R2

·OFFSET"
H3
-5V

R12

H9
-12V

Parts List
Resistors
Rl
R2

R3
R4
R5

R6

R7
R8,R9
RlO
Rll,R12
R13
R14,R15
R16,R22
R17,R18
R19
R2D,R21

Capacitors
51(

.u
'"
lK

43
33
330
750
10
75
10K
220
100
390
2K
lK
lK

For More Information call 1-800·722·7074.

1/4W
1/4W

i,.4W
1I4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W

10-lum
lO-lUm
5%
5%
5%
5%
5%
5%

2%
5%
5%

5%
5%
10-lUm
5%
5%

Cl
C2
C3

C4
C5
C6
C7
C8
C9
ClO

Diodes

O.OlJ.LF
1.0J.LF
1.0J.LF
2.2iJ.F
0.1J.LF
2-5pF
O.lJ.LF
0.1J.LF
O.lJ.LF
O.lJ.LF

50V
10V
10V
25V
5DV
5DV
5DV
5DV
5DV
5DV

CRI

lN4001

Transistors
Q1

02
Q3
Q4
OS

2N2907
2N2907
2N2907
2N6660
2N6660

Integrated Circuits
RF Chokes
l1,l2

Ferrite beads

Raytheon Semiconductor

Ul
U2
U3
U4

TRW TDC1016
lMl13
HA2539
SN74D4

3·181

I

TDCI016
Ordering Information
Product
Number

Temperature Range

Screening

TDC1 01 6J5CX
TDC1016J5AX
TDC1016J7CX
TDC1016J7AX

STD - TA = O·C to 70·C
EXT - TC =-55·C to 125·C
STD - TA =O·C to 70·C
EXT - Tc =-55·C to 125·C

Commercial
High Reliability
Commercial
High Reliability

Package

Package
Marking

40 Pin Ceramic
40 Pin Ceramic
24 Pin Ceramic
24 Pin Ceramic

1016J5CX
1016J5AX
1016J7CX
1016J7AX

4OGOO28O Rev H 8193

3-182

Raytheon Semiconductor

For More Information call HIOO-722-7074.

TDCI018
TDCI018
Digital-to-Analog Converter
a-Bit, 200 MHz

Description
The TDC1018 is an 8-bit digital-to-analog converter,
designed for 200 MHz operation and capable of directly
driving a 75 Ohm load to standard video levels. Most
applications require no extra registering, buffering, or
deglitching. Four special level controls make the device
ideal for video applications. All data and control inputs
are ECl compatible.
The TDC1018 is built with Raytheon Semiconductor's
OMICRON-BTM 1-micron bipolar process. On-chip data
registers and precise matching of propagation delays
make the TDC1 018 inherently low-glitching. The
TDC1018 offers high performance, low power
consumption, and video compatibility in a 24-pin DIP or
a 28-contact chip carrier.

Features
•
•
•
•

Monolithic "Graphics-Ready"
125 MHz digital update rate, TDC1018
200 MHz digital update rate, TDC1018-1
8-bit resolution

•
•
•
•
•
•
•
•
•
•

1/2 lSB linearity
Registered data and video controls
Complementary current outputs
Video controls: SYNC, BLANK, BRighT, force high
Inherently low glitch energy
ECl compatible inputs
Multiplying mode capability
Can be operated in m systems
Available in a 24-pin DIP and 28-contact
chip carrier
Single -5.2V power supply

Applications
•
•
•
•
•
•

RGB graphics
High resolution video
Raster graphic displays
Digital synthesizers
Automated test equipment
Digital transmitters/modulators

Functional Block Diagram r------------------""""!
CONTROL

-=:t::-=t:::::>1 LOGIC

FH. BLANK
BRT.
...
SYNC

r:=:::::-I---I-~

OUT +

L..:=;=...J---r-'-

OUT-

4

CONY. CONY
FT

REF+ REF-

For Mora Information call 1-800-722·7074.

Raytheon Semiconductor

COMP
3-183

I

TDCI018
Pin Assignments
Q'U :l5 + I CIa..
Z ... 1- I- Zi!!j
>55:'u

lElCl!i::3I::1;::;25!!
05 1
06 2
0] 3
Da 4
VEEO 5
CDNV 6
CDNV 7
FT 8
°GNO 9
FH 10
BLANK 11
BRT 12

IQJ

24
23
22
21
20
19
18
17
16
15
14
13

03
04
05
06
0]

Da

General Information
The TDC1018 develops complementary analog output
currents proportional to the product of the digital input
data and analog reference current. All data and control
inputs are compatible with standard ECl logic levels.
FeedThrough control 1FT) determines whether data and
control inputs are synchronous or asynchronous. If FT is
lOW, each rising edge of the CONVert clock ICONV)
latches decoded data and control values into an internal
D-type register. The registered values are then converted
into the appropriate analog output by switched current
sinks. When FT is HIGH, data and control inputs are not
registered, and the analog output asynchronously tracks
the input values. FT is the only asynchronous input, and
is normally used as a DC control.
The TDC1018 uses a segmented approach in which the
four MSBs of the input data are decoded into a parallel
"Thermometer" code, which drives fifteen identical
current sinks to produce sixteen coarse output levels.
The lSBs of the input drive four binary-weighted current
switches, with a total contribution of one-sixteenth of
full-scale. The lSB and MSB currents are summed to
provide 256 analog output levels.

3-184

1I
2B

1
2
3
4
IoaCD

.....

NC
IREf+
IREfSYNC
BRIGHT
BLANK
FH

cam=;:

CI>
...
Z I>
Z
U ... CI CI
Z>UU

24 Pin CERDIP - B7 Package

Functional Description

18
17
16
15
14
13
12

Dz26

04
03
02
01
VEEA
DUT+
DUTAGND
CDMP
REF+
REFSYNC

t:

CI
Z
ClIU
ClZ

28 Contact Chip Carrier - C3 Package
Special control inputs, SYNC, BLANK, Force High IFH)
and BRighT IBRT), drive appropriately· weighted current
sinks which add to the output current to produce specific
output levels especially useful in video applications.

Power
To provide highest noise immunity, the TDC1018 operates
from separate analog and digital power supplies, VEEA
and VEED, respectively. Since the required voltage for
both VEEA and VEED is - 5.2V, these may ultimately be
connected to the same power source, but individual
high-frequency decoupling for each supply is recommended. A typical decoupling network is shown in
Figure 7. The return for IEED, the current drawn from
the VEED supply, is DGND. The return for IEEA is AGND·
All power and ground pins MUST be connected.
Although the TDC1D18 is specified for a nominal supply
of - 5.2V, operation from a + 5.0V supply is possible
provided that the relative polarities of all voltages are
maintained.
For additional information concerning the use of ECl D/A
converters in a + 5V system, refer to TRW Application
Note TP-33 "Using the TDC1018 and TDC1034 in a
TTL Environment."

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TDCI018
Reference
The TOC1018 has two reference inputs: REF + and
REF -, which are noninverting and inverting inputs of an
internal reference buffer amplifier. The output of this
operational amplifier serves as a reference for the
current sinks. The feedback loop is internally connected
around one of the current sinks to achieve high accuracy
(see Figure 41.
The analog output currents are proportional to the digital
data and reference current, IREF. The full-scale output
value may be adjusted over a limited range by varying
the reference current. Accordingly, the stability of the
analog output depends primarily upon the stability of the
reference. A method of achieving a stable reference is
shown in Figure 7.
The reference current is fed into the REF + input, while
REF - is typically connected to a negative reference
voltage through a resistor chosen to minimize input offset
bias current effects.
A COMPensation input (COMP), is provided for external
compensation of the TOC1018's reference amplifier. A
capacitor (CCI should be connected between COMP and
the VEEA supply, keeping lead lengths as short as
possible. The value of the compensation capacitor determines the effective bandwidth of the amplifier. In
general, decreasing Cc increases bandwidth and
decreases amplifier stability. For applications in which the
reference is constant, Cc should be large, while smaller
values of Cc may be chosen if dynamic modulation of
the reference is required.

Propagation delay from input change (control or datal to
analog output is minimized in the asynchronous mode of
operation.
In the synchronous mode, the video control inputs are
registered by the rising edge of the CONV clock in a
manner similar to the data inputs. The controls, like data,
must be present at the inputs for a setup time of ts (nsl
before, and a hold time of tH (nsl after the rising edge
of CONV in order to be registered. In the asynchronous
mode, the setup and hold times are irrelevant and
minimum pulse widths HIGH and lOW become the
limiting factor.
Asserting the video controls produces various output
levels which are used for frame synchronization,
horizontal blanking, etc., as described in video system
standards such as RS-170 and RS-343A. The effect of
the video controls on the analog outputs is shown in
Table 1. Special internal logic governs the interaction of
these controls to simplify their use in video applications.
BlAN K, SYNC, and Force High override the data inputs.
SYNC overrides all other inputs, and produces full
negative video output. Force High drives the internal
digital data to full-scale, giving a reference white video
level output. The BRT control creates a "whiter than
white" level by adding 10% of the full-scale value to the
present output level, and is especially useful in graphics
displays for highlighting cursors, warning messages, or
menus. For non-video applications, the special controls
can be left unconnected.

Data Inputs
Controls
The TOC1018 has four special video control inputs:
SYNC, BLANK, Force High (FH), and BRighT (BRT), in
addition to a clock FeedThrough control (FTI. All controls
are standard ECl level compatible, and include internal
pulldown resistors to force unused controls to a logic
lOW (inactivel state.
Typically the TOC1018 is operated in the synchronous
mode, which assures the highest conversion rate and
lowest spurious output noise. By asserting FT, the input
registers are disabled, allowing data and control changes
to asynchronously feed-through to the analog output.

For More Information call 1-800-722-7074.

Data inputs to the TOC1018 are standard single-ended
ECl level compatible. Internal pulldown resistors force
unconnected data inputs to logic lOW. Input registers are
provided for synchronous data entry and lowest
differential data propagation delay (skew), which
minimizes glitching.
In the registered mode, valid data must be present at
the input a setup time ts (nsl before, and a hold time tH
(nsl after the rising edge of CONV. When FT is HIGH,
data input is asynchronous and the input registers are
disabled. In this case the analog output changes
asynchronously in direct response to the input data.

Raytheon Semiconductor

3-185

I

TDCI018
Convert

Analog Outputs

CONVert ICONVI is a differential ECl compatible clock
input whose rising edge synchronizes data and control
entry into the TOC1018. Within the constraints shown in
Figure 2, the actual switching threshold of CONV is
determined by CONV. CONV may be driven single-ended
by connecting CONV to a suitable bias voltage IVBBI.
The bias voltage chosen will determine the switching
threshold of CONV. However, for best performance,
CONV must be driven differentially. This will minimize
clock noise and power supply/output intermodulation.
Both clock inputs must normally be connected, with
CONV being the complement of CONV.

The two analog outputs of the TOC1018 are highimpedance complementary current sinks which vary in
proportion to the input data, controls, and reference
current values. The outputs are capable of directly driving
a dual 75 Ohm load to standard video levels. The output
voltage will be the product of the output current and
effective load impedance, and will usually be between
OV and -1.07V in the standard configuration Isee Figure
51. In this case, the OUT-output gives a OC shifted
video output with "sync down." The corresponding
output from OUT + is also DC shifted and inverted, or
"sync up:'

Package Interconnections
Signal
Type
Power

Reference

Controls

Data Inputs

Signal
Name

Function

Value

87 Package Pins

C3 Package Pins

VEEA

Analog Supply Voltage

-5.2V

20

23

VEED

Digital Supply Voltage

-5.2V

5

AGND

Analog Ground

O.OV

17

6
20

DGND

Digital Ground

O.OV

9

10

REF-

Reference Current- Input

REF+

Reference Current+ Input

Op-Amp Virtual Ground
Op-Amp Virtual Ground

14
15

17

COMP

COMPensation Input

Cc

16

19

FT

Register FeedThrough Control

ECl

8

9

FH

Data Force High Control

ECl

10

12

BLANK
BRT

Video BLANK Input
Video BRighT Input

ECl
ECl

11
12

13
14

SYNC

Video SYNC Input

ECl

13

15

D1

Data Bit 1 (MSB)

ECl

21

25

D2

ECl

22

26

D3
D4

ECl
ECl

23
24

27
28

D5

ECl

1

1

D6

ECl

2

2
3

ECl

3

D8

Data Bit 8 (lSB)

ECl

4

4

CONV

CONVert Clock Input

ECl

6

7

CONV

CONVert Clock Input. Complement

ECl

7

8

OUT -

Output Current-

Current Sink

18

21

OUT +

Output Current +

Current Sink

19

22

D7
Convert

Analog Outputs

3-186

16

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI018
Figure 1. Timing Diagram

I

OV

-1.3V
CONY

Figure 2. CONVert. CONVert Switching Levels

.,----,,- '~---,

,,

O.OV

-

-

-

-

- --

VICM MIN

,

", , ,
-------,-,, ,
" ,,-----,
~'"
X'-____

-1.3V
CONY

VICM MAX -

____

Figure 3. Equivalent Input Circuits

- -......- - -.....-

.....- - AGNO
DATA.
CONTROLS

10011

40KII

IBIAS

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-187

TDCI018
Figura 4. Equivalent Output Circuit

r-------~~--~------~__o ooT+

...----+"......---+--~--__+___c

REF+

OUT-

0--+-.------+-11-.....

REF- 0--1---1

~r-----~--------------'---------V~
COMP

Figura 5. StandII'd Load Configuration

VIDEO
MONITOR

,

---..,I

OUT-

RS

15!"!

I
I

I
I
IL ___ .....JI

TDC1018

7m

E~
RS

COAX

7m

q~c

o INVERSE
VIDEO

TEST LDAD:
OUT+
OUT-

RL

VIDEO OUT
-1 VOLT

oTO

37.5!"!

3-188

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI018
Absolute maximum ratings Ibeyond which the device may be damagedl 1
Supply Voltages
VEEO Imeasured to 0GNOI ........................................................................................................................................................................................... -7.0 to 0.5V
VEEA Imeasured to AGNOI ........................................................................................................................................................................................... -7.0 to 0.5V
AGNO Imeasured to 0GNOI .......................................................................................................................................................................................... -0.5 to O.5V
Input Voltages
CONY, Oata, and Controls Imeasured to 0GNOI ..................................................................................................................................................... VEEO to O.5V
Reference input, applied vo~age Imeasured to AGNOl 2
REF+ ......................................................................................................................................................................................................................... VEEA to 0.5V
REF- ......................................................................................................................................................................................................................... VEEA to 0.5V
Reference input, applied current, externally forced 3,4
REF+ ...................................................................................................................................................................................................................................... 6.0mA
REF- ...................................................................................................................................................................................................................................... 0.5mA

Output
Analog output, applied vo~age Imeasured to AGNOI
OUT + ...................................................................................................................................................................................................................... - 2.0 to +2.0V
OUT - ...................................................................................................................................................................................................................... -2.0 to +2.0V
Analog output, applied current, externally forced 3,4
OUT + ...................................................................................................................................................................................................................................... 50mA
OUT - ...................................................................................................................................................................................................................................... 50mA
Short circuit duration .................................................................................................................................................................................................... Unlimited sec
Temperature
Operating, ambient .................................................................................................................................................................................................... -60 to + 140°C
junction .................................................................................................................................................................................................................... + 175°C
lead, soldering 110 secondsl .................................................................................................................................................................................................. +300°C
Storage ........................................................................................................................................................................................................................ -60 to + 150°C
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the device.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-189

I

TDCI018
Operating .conditions
Temperature Range
Standard
Min
Nom
Max

Units

Digital Supply Vokage Imeasured to DGNDI

-4.9

-5.2

-5.5

V

Analog Supply Vokage Imeasured to AGNoi

-4.9

-5.2

-5.5

V

Analog Ground Voltage Imeasured to DGNDI
VAGND
VEEA-VEED Supply Voltage Differential

-0.1

0.0

+0.1

V

-0.1

0.0

+0.1

V

Parameter
VEED
VEEA

VICM

CDNV Input Voltage. Common Mode Range IFigure 21

-0.5

-2.5

V

VIDF

CDNV Input Voltage, Differential IFigure 21

0.4

1.2

V

tpWL

CDNV Pulse Width, LOW

4

ns

tpWH

CDNV Pulse Width, HIGH

4

ns

ts

Setup Time, Data and Controls

3.5

ns

tH

Hold TIme, Data and Controls

0

VIL

Input Voltage, Logic LOW

VIH

Input Voltage, Logic HIGH

IREF

Reference Current

Cc

Compensation Capacitor

TA

Ambient Temperature, Still Air

ns
-1.49

V
V

-1.045
Video standard output levels 1

1.059

8-bit linearity

1.0
2000

1.115

1.171

mA

1.3

mA
pF

3900

0

70

°C

Note:
1. Minimum and Maximum values allowed by ±5% variation given in RS343A and RS170 after initial gain correction of device.

Electrical characteristics within specified operating conditions

Test Conditions

Parameter
IEEA+IEED

Temperature Range
Standard
Min
Max

Supply Current

Units

VEEA = VEED = MAX, static 1
TA = O°C to 70°C

170

mA

TA = 70°C

130

mA

CREF

Equivalent Input Capacitance, REF+, REF-

5

pF

CI

Input Capacitance, Data and Controls

5

pF

VDCP

Compliance Voltage, + Output

-1.2

+1.5

V

VDCN

Compliance Voltage, - Output

-1.2

+ 1.5

V

RD

Equivalent Output Resistance

20

CD

Equivalent Output Capacitance

KOhms
20

pF

lOp

Max Current, + Output

VEEA = NOM, SYNC = BLANK = 0, FH = BRT = 1

30

mA

ION

Max Current, - Output

VEEA = NOM, SYNC = 1

30

mA

IlL

Input Current, Logic lOW, Data and Controls

VEED = MAX, VI = -1.49V

200

IIH

Input Current, Logic HIGH, Data and Controls

VEED = MAX, VI = -1.045V

200

/1 A
/1 A

IIC

Input Current, Convert

VEED = MAX, -1.49V < VI< -1.045V

50

/1 A

Note:
1. Worst case over all data and control states

3-190

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI018
Switching characteristics within specified operating conditions

Parameter
FS

Temperature Range
Standard
Min
Max

Test Conditions
VEEA' VEED ~ MIN
TDC1018

Maximum Data Rate

TDC1018-1

Units

125

MSPS

200

MSPS

tDSC

Clock to Output Delay, Clocked Mode

VEEA, VEED

~

MIN, FT

~

0

8

ns

tDST

Data to Output Delay, Transparent Mode

VEEA, VEED

~

MIN, FT

~

1

13

ns

tSI

Current Settling Time, Clocked Mode

VEEA, VEED

~

MIN, FT

~

0

0.2%

10

ns

0.8%

8

ns

3.2%

5

ns

1.7

ns

tRI

Risetime, Current

10% to 90% of Gray Scale

System performance characteristics within specified operating conditions

Parameter

Test Conditions

Temperature Range
Standard
Min
Max

Units

Ell

Linearity Error Integral. Terminal Based

VEEA, VEED, IREF ~ NOM

0.2

% of Gray Scale

ELO

Linearity Error Differential

VEEA, VEED, IREF ~ NOM

0.2

% of Gray Scale

IOF

Output Offset Current

VEEA' VEED ~ MAX, SYNC ~ BLANK ~ 0, FH ~ BRT ~ 1

10

J.lA

VEEA, VEED ~ MIN, IREF ~ NOM

±5

% of Gray Scale

±0.024

% of Gray Scale/DC

EG

Absolute Gain Error

TCG

Gain Error Tempco

BWR

Reference Bandwidth, - 3dB

Cc ~ MIN, ~ VREF ~ lmV p-p

DP

Differential Phase

4 x NTSC

1.0

Degrees

DG

Differential Gain

4 x NTSC

2.0

%

PSRR

Power Supply Rejection Ratio

VEEA , VEED, IREF ~ NOM I
VEEA' VEED' IREF ~ NOM 2

1

MHz

45

dB

55

dB

PSS

Power Supply Sensitivity

VEEA' VEED, IREF ~ NOM

120

J.lAIV

GC

Peak Glitch Charge

Registered Mode 3,4

800

fCoulomb

GI

Peak Glitch Current

Registered Mode

GE

Peak Glitch "Energy" IAreal

Registered Mode 4

30

FTC

Feedthrough Clock

Data ~ Constant 5

-50

dB

FTD

Feedthrough Data

Clock ~ Constant 5

-50

dB

1.2

mA
pV-Sec

Noles:
20KHz, ±O.3V ripple superimposed on VEEA , VEED: dB relative to full gray scale.
260Hz, ±O.3V ripple superimposed on VEEA- VEED: dB relative to full gray scale.

3. fCoulombs

~

mlcroamps x nanoseconds

4. 37.5n load. Because glitches tend to be symmetric, average glitch area approaches zero.
5. dB relative to full gray scale, 250M Hz bandwidth limit

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-191

I

TDCI018
Table 1 Video Control Truth Table
Sync

Blank

Force High

Bright

Data Input

Out- (mA)l

Dut- (V)2

Out- (lRE)3

1
0
0
0
0
0
0
0

X
1
0
0
0
0
0
0

X
X
1
1
0
0
0
0

X
X
1
0
0
0
1
1

X
X
X
X
000 ...
111...
000 ...
111...

28.57
20.83
0.00
1.95
19.40
1.95
17.44
0.00

-1.071
-0.781
0.00
-0.073
-0.728
-0.073
-0.654
0.00

-40
0
110
100
7.5
100
17.5
110

Description 4
Sync level
Blank level
Enhanced High level
Normal High level
Normal low level
Normal High level
Enhanced low level
Enhanced High level

Notes:
1.
2.
3.
4.

Out + is complementary to Out-. Current is specified as conventional current when flowing into the device.
Voltage produced when driving the standard load configuration 137.5 Ohmsl. See Figure 5.
140 IRE units - 1.00V.
RS-343-A tolerance on all control values is assumed.

Figure 6. Video Output Waveforms for Out- and Out+ with Standard Load Configuration
BRIGHT
D.D

-1-----------NORMAL WHITE LEVEL

-73

256 "GRAY-SCALE" LEVELS

-728

____________ l ___ ~M~B~~L

-181

-

-

-

-

-

-

-IIDI

-

-

-

-

-

-

DB

-

_______________

VOUT-(mVI
Rl"" 37.5 Ohms

-290

-J4J
VOUT+lmVl

-

-

-

-

-

-

-

-

-

-

-

__

-'-----,

-

-

-

-

_'-----'=_-L-

,---'.c.:.:;.._-,-

------------T---------

-

-

-

-

-

-

-

-

-

-

-

.,.-""=--..J

NORMAL BLACK LEVEL

RL '" 37.5 Ohms
256 "GRAY-SCALF' LEVRS

-998

,-_____J_l ___ ...".o~...'!H~~

___ _

BRIGHT
-1071

3-192

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TDCI018
Figure 7. Typical Interface Circuit

Parts List
Integrated Circuits

MS'

-{

Ul

DATA
fEel)

I

TDC1018 D/A Converter

Voltage References
~fV'I"'"'-_-<

lS'

-S.2V

1V,DEo----,
I MONITOR

-S.2V

I

I

J"

~~~~~======~~=====jl~q:¥
:

Rt

75Q

I

CONVert

VRl LM113 or LM313 Bandgap Reference

:I

I Inductors

-Ll---F-er-ri-te-B-e-a-d-S-h-ie-Id-I-nd-u-c-to-r--------Fair-Rite PIN 2743001112 or Similar

I

L____ J-----------------------Resistors

CONVert

T = ECL TERMINATION

-{
CONTROLS
fEet)

Rl
R2
R3
R4

lKD
1.00KD
2.00KD
1.00KD

Pot
1I8W
1I8W
1I8W

10 Turn
1% Metal Film
1% Metal Film
1% Metal Film

-5.2V

Capacitors
Cl-C3
Cc

O.l/LF
O.Ol/LF

50V
50V

Ceramic Disc
Ceramic Disc

Ordering Information
Product
Number

Temperature Range

Screening

Package

Package
Marking

TDC1018B7C
TDC1018B7Cl

STD-TA=O°C to 70°C
STD-TA=O°C to 70°C

Commercial
Commercial

24 Pin CERDIP
24 Pin CERDIP

1018B7C
1018B7Cl

TDC1018C3C
TDC1018C3Cl

STD-TA = O°C to 70°C
STD-TA =O°C to 70°C

Commercial
Commercial

28 Contact Chip Carrier
28 Contact Chip Carrier

1018C3C
1018C3Cl

40G01211 Rev H 8193

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-193

TDCI018

3-194

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI041
mCI041
Monolithic DigitaI-to-AnaIog Converter

I

10-Bit, 20 Msps, 12 ns Settling lime

Description

Features

The TDC1041 is a TIL compatible, 10-bit monolithic
D/A converter capable of converting digital data into an
analog current or voltage at data rates in excess of 20
Megasamples-per second (Msps).

•
•
•
•
•

The analog circuitry has been optimized for dynamic
performance, with very low glitch energy. The output is
able to drive a 500 load with a 1 Volt output level while
maintaining low harmonic distortion.
Data registers are incorporated on the TDC1 041. This
eliminates data skew encountered with external
registers and latches and minimizes the glitches that
can adversely affect many applications.

10-bit resolution
20 Msps data rate
TTL inputs
Very Iowillitch with no track and hold circuit needed
Dual +4 dBm (1V into 50~ outputs make output
amplifiers unnecessary in many application

Applications
•
•
•
•

Test signal generation
Arbitrary waveform synthesis
Broadcast and studio video
High-resolution AID converters

Interface Diagram

01 (MSB)

O2

Da
04
05

TDC1D41

06

~
08
09
010 (LSB)

24078A

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-195

TDCI041
Functional Block Diagram
REF. } - - - - -.........- - - - - - - ,
REFERENCE
AMPLIFIER
REF·
COMP

.----+-------""

01 (MSB)

63 UNIFORMLY WEIGHTED
MSB CURRENT SWITCHES

O2

03

MSB DECODE
REGISTER

04
05
06
CONV

OUT.
CURRENT
SWITCH ARRAY
OUT·

FT

LSB DATA
REGISTER

6 BINARY WEIGHTED
....._ _ _ _ _ _ _ _ _... LSB CURRENT SWITCHES

Pin Assignments

211378

Functional Description
General Description

VCC
CONY
FT
VEEA
REF·
REF.
COMP

18 NC

26
27
28
1
2
3
4

17DGND
16 NC
15 OUT·
14 OUT.

13 AGND
12 NC

or-co

ttlc

0)

.0 Q

0(..)

CZ

(.)

Z

>
24080A

28 Leaded Plastic Chip Carrier - R3 Package

3-196

The TOC1 041 consists of five major circuit sections: the
LSB data register, the MSB decode block, the decoded
MSB register, the current switch array, and the reference
amplifier. All data bits are registered just before the
current switches to minimize the temporal skew that would
generate glitches.
Power. Grounds
The TDC1041 requires a -5.2V power supply and a +5.0V
power supply. The analog (VEEA) and digital (VEED) supply
voltages should be decoupled from each other, as shown in
the Typical Interface Circuit. The VCC pin should be
considered a digital power supply. The 0.11JF decoupling
capacitors should be placed as close as possible to the
power pins. The inductors are simple ferrite beads and are
neither critical in value nor always required.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI041
Reference and Compensation

Clock and Feedthrough Control

The TOC1041 has two reference inputs: REF+ and REF-.
These are the inverting and noninverting inputs of the
internal reference amplifier. An externally generated
reference voltage is applied to the REF- pin. Current flows
into the REF+ pin through an external current setting
resistor (RREF). This current is the reference current (lREF)
which serves as an internal reference for the current
source array. The output current for an input code N from
OUT+ is related to IREF through the following relationship:

The TOC1 041 requires a TTL clock signal (CONV). Data is
synchronously entered on the rising edge of CONV. The
CONV input is ignored in the Feedthrough (FT = HIGH)
mode. The Feedthrough (FT) pin is normally held LOW,
where the TOC1041 operates in a clocked mode (the output
changes only after a clock rising edge). An internal pulldown resistor is provided, and this pin may be left open for
clocked operation.

IREF
IOUT=Nx 16
Where N is the value of the input code.
This means that with an IREF that is nominally 6251JA, the
full-scale output is 40mA, which will drive a 50Q load in
parallel with a 50Q transmission line (25Q total load) with
a 1V peak to peak signal. The impedance seen by the REFand REF+ pins should be approximately equal so that the
effect of amplifier input bias current is minimized. When
driving a 75Q load, the reference current must be reduced.
This can be done by increasing the value of the resistor
from REF+ to ground.
The internal reference amplifier is externally compensated
to ensure stability. A 0.11JF capacitor should be connected
between the CaMP pin and VEEA

Digital Inputs
The data inputs are TTL compatible. One of the effects that
leads to degradation of the dynamic performance of the
device is the capacitive feedthrough from the digital inputs
to the analog output of the device. One method of reducing
the effect of capacitive coupling is to slow down the slew
rates of the digital inputs. This can be done in many ways,
starting with the selection of a logic family that is no faster
than what is needed, and can include the addition of 50Q
series resistors to the data lines.

For More Information call HIOO-722-7074.

For certain applications, such as high-precision successive
approximation AID converters, throughput delay may be
more important than glitch performance. In these cases,
the FT pin may be brought HIGH, which makes the input
registers transparent. This allows the analog output to
change immediately and asynchronously in response to the
digital inputs.
Since skew in the bits of the input word will result in
glitches, and will affect settling time, it is recommended
that the TOC1 041 be operated in clocked mode for most
applications.

Analog Outputs
Two simultaneous and complementary analog outputs are
provided. Both of these outputs are full-power current
sources. By loading the current source outputs with a
resistive load, they may be used as voltage outputs. OUT+
provides a 0 to -40mA output current (0 to -1V when
terminated in 25Q) as the input code varies from
00 0000 0000 to 11 1111 1111. OUT-varies in a
complementary manner from -40 to OmA (-1 to OV when
terminated with 25Q) over the same code range. (See the
Input Coding Table.) The output current is proportional to
the reference current and the input code.

No Connect
These pins have no internal connection and should be left
open for optimal performance.

Raytheon Semiconductor

3-197

I
."

TDCI041
Package Interconnections
Signal
Type

Signal
Name

Power

AGND
DGND
VeEA
VeED
VEED

Analog Ground
Digital Ground
Analog Supply Voltage
Digital Supply Voltage
Digital Supply Voltage

O.OV
O.OV
-5.2V
-5.2V
-5.2V

13
17
1
5
26

Reference

REFREF+
COMP

Reference Voltage Input
Reference Current Input
Compensation Capacitor

-1.0V
625!lA
0.11J/', see text

2
3
4

Data Inputs

Dl (MSBI
D2
D3
D4
D5
D6
D7
D8
D9
DIO (LSBI

Most Significant Bit

Least Significant Bit

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

24
23
22
21
20
19
6
7
8
9

FT

Feedthrough Mode Control

TTL

28

Feedthrough

Function

Value

R3Package
Pins

Convert

CONV

Convert (Clockllnput

TTL

27

Analog Output

OUT+
OUT-

Analog Output
Analog Output

Oto 40mA
40 to OmA

14
15

No Connect

NC

No Internal Connection

Open

10,11,12,16,18,25

Input Coding Table 1
Input Data
MSB LSB

VOUT+lmVI

OUT-lmAI

VOUT-lmVI

0000000000
0000000001
00 0000 0010

0.000
0.039
0.078

0.00
-0.97
-1.95

40.000
39.961
39.922

-1000.00
-998.05
-998.05

0111111111
1000000000

19.961
20.000

-499.03
-500.00

20.000
19.961

-500.00
-499.03

1111111101
1111111110
11111111 l1

39.922
39.961
40.000

-998.05
-999.03
-1000.00

0.078
0.039
0.000

···

···

Note:

3-198

OUT+lmAI

···
··
·

···
···

···

··
·

···

···

-1.95
-0.97
0.0

1. IREF =6251lA, RLOAD =250

Raytheon Semiconductor

for More Infcnnation call 1-800-722-7074.

TDCI041
Figure 1. Timing Diagram

I

INPUT
(0
, -,2 ) _ _ _ _J

CONY

'PWH

'pWL

IT-~----------------~--------------------'I
OV

OUT-

-IV
±1/2 LSB

I SET

I SET

240778

Figure 2. Equivalent Reference and Output Circuits

IT

CONVERT, & DATA (0, -10)
VCC - - - - - - . . . - . - -

AGNO
REF-

INPUT

O---'V'\I\r-__---1

REF+

-1.3V

0VREF

------t---

REFERENCE
SEGMENT
SWITCH
VEEA
21139A

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-199

TDCI041
Figure 3. Simplified Reference and Output Circuits

Figure 4. Output Test Load

CURRENT
SINK#N
.----hlL!---.----+--o OUT +
0-_.".-+--+-...,....-0----0 OUT·

TEST LOAD:
OUT +
OUT·

D-_---.....-+ 0 TO·l VOLT
CL
<5pF

I
I
I

21346A

.......----- VEEA

I
L
__ _

===:T----~-----

COMP

21345A

Absolute maximum ratings (beyond which the device may be damaged)l
Supply Voltages

VCC
VEEA
VEEA
VEED
AGND

(measured to DGND) .....................................................................................................................................................-0.5 to +7.0V
(measured to AGND) .....................................................................................................................................................-7.0to +0.5V
(measured to VEED) .....................................................................................................................................................-50 to +50mV
(measured to DGND) .....................................................................................................................................................-7.0 to +0.5V
(measured to DGND) .....................................................................................................................................................-0.5 to +0.5V

Inputs

CONY, FT, Dl·l0 (measured to DGND)2 ................................................................................................................................VCC +0.5 to -O.5V
CONY, FT, Dl-l0 Current, externallyforced 3 ............................................................................................................................................±3mA
REF+, REF-,applied voltage
(measured to AGND)3 ...............................................................................................................................................VEEA to +0.5V
REF+, REF-, current, externally forced3 .....................................................................................................................................................±3mA
Oulputs

OUT+, OUT-, applied voltage
(measured to AGND)2 ..................................................................................................................................................-2.0 to +2.0V
OUT +, OUT-, current, externally forced 3 .................................................................................................................................................+50mA
Short-circuit duration (single output to GND) ...................................................................................................................................... unlimited
Temperature
Operating, ambient

(Plastic Package) ...........................................................................................................................................................-20 to +90°C
(Ceramic Package) ......................................................................................................................................................-60 to +150°C
Junction
(Plastic Package) .....................................................................................................................................................................+140°C
(Ceramic Package) ..................................................................................................................................................................+200°C
Lead, soldering (10 seconds) ......................................................................................................................................................................+300°C
Storage
........................................................................................................................................................................................-65 to +150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while other parameters are within specified operating conditions. Functional
operation under any of these conditions is NOT implied. Device performance and reliability are guaranteed only if the Operating Conditions are not
exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range. Current is specified as conventional current flowing into the device.

3-200

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TDCI041
Operating conditions
Temperature Range
Parameter

Min

5.0
-5.2
-5.2
0.0
0

Max

Units

5.25
-5.5
-5.5
0.1
20

V
V
V
V
mV

VCC
VEED
VEEA
VAGND
VEEA

Positive Supply Voltage (Measured to DGND)
Negative Supply Voltage (Measured to DGND)
Negative Supply Voltage (measured to AGND)
Analog Ground Voltage (Measured to DGND)
Negative Supply Voltage (Measured to VEED)l

tpWL
tPWH

CONV Pulse Width LOW (to Meet Specification)
CONV Pulse Width HIGH (to Meet Specifications)

20
20

ns
ns

ts
tH

Setup Time, Data to CONV (to Meet Specification)
Hold Time (to Meet Specifications)

25
1

ns
ns

tSF
tHF

Setup Time, Data to FT
Hold Time, Data to FT

5
28

ns
ns

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

2.0

VREF
IREF

Reference Voltage (REF-)
Reference Current (REF+)

-n.7
400

Cc

Compensation Capacitor

0.01

TA

Ambient Temperature, Still Air

0

Note:

4.75
-4.9
-4.9
-n.l
-20

Standard
Nom

0.8
-1.0
625

-1.3
700

0.1

I

V
V
V

J.lA
jlf

70

°c

1. A common power supply isolated with ferrite bead inductors is recommended for VEEA and VEED. This is shown in the Typical Interface Circuit.

Electrical characteristics within specified operating conditions
Temperature Range
Parameter

Test Conditions

IEEA+IEED

VEEA=VEED=Max, static
TA=Oto 70°C
TA=70°C

ICC

Vcc=Max, Static
TA=Oto 70°C
TA=70°C

CREF
CI

Reference Input Capacitance
Digital Input Capacitance

VOC

Compliance Voltage

RO
Co
10

Output Resistance
Output Capacitance
Full-Scale Output Current

IREF=Nominal

IlL
IIH

Input Current, Logic LOW
Input Current, Logic HIGH

VCC,VEE=Max, VI=0.4V
VCC,VEE=Max, VI=2.4V

11M
VTH

Input Current, Max Input Voltage
Logic InputThreshold Voltage,Typical

VCC,VEE=Max, VI=VCC Max
VCC,VEE=Nom, TA=25°C

For More Infonnation call 1-800-722-7074.

Min

-1.2

Standard
Max
-180

mA

-150

mA

25

mA

20

mA

15
15

pF
pF

1.2

12

Raytheon Semiconductor

Units

V

45

kn
pF
mA

-10
-10

50
100

J.lA
J.lA

-10
1.25

100
1.55

J.lA

40

V

3-201

TDCI041
Switching characteristics
Temperature Range
Parameter

Test Conditions

Maximum Data Rate
Clock to Output Delay
Data to Output Delay
FT to Output Delay
Risetime
Falltime
Settling Time. Voltage

FD
tDC
too
tDF
tR
tF
tSET

VEEA. VEED. Vcc=Min
VEEA. VEED. Vcc=Min. FT=LDW
VEEA. VEED. Vcc=Min. FT=HIGH
VEEA. VEED. Vcc=Min
90% to 10% of FSR. FT=LDW
10% to 90% of FSR. FT=LDW
FT=LDW. Full-Scale Voltage
transition on IOUTto ±O.0188%FSR

Min

Standard
Typ

Max

Units

17
35
35
4
4
30

MHz
ns
ns
ns
ns
ns
ns

25

20

20

System performance characteristics
Temperature Range
Parameter
ELD

ELI

VOS
IB
EG
IOF
PSRR
PSS
GA
SFDR

Test Conditions

3·202

Standard
Typ

VEEA. VEEO.IREF = Nom 1
TDC1041
TDC1041-1
VEEA. VEED.IREF = Nom 1
TDC1041
TDC1041-1

Differential linearity Error

Integral linearity Error

REF+ to REF- Offset Voltage
REF- Input Bias Current
Absolute Gain Error
Output Offset Current
Power Supply Rejection Ratio
Power Supply Sensitivity
Peak Glitch Area
Spurious Free Dynamic Range

-10
VEEA. VEED. Vcc. IREF= Nom
VEEA. VEED. VCC= Min. 01-10=LOW
VEEA. VEED. VCC.IREF= Nom 2
VCC. VEEA. VEED=4%.IREF= Nom

-5

IREF=Nom. 20 Msps.
10MHz bandwidth

60

25

Fout=6MHz
Fou t=5MHz
Fout=2MHz
Fout=1 MHz
Notes:

Min

1.

OUT-connected to AGND. OUT+driving virtual ground.

2

120 Hz. 0.6VPi' ripple on VEEA and VEED. dB relative to 0.6VJ>i) ripple input.

Raytheon Semiconductor

70
75
78

Max

Units

±O.l
±0.05

%
%

±0.1
±O.05
+10
5
5
±40
-50
-140
45

%
%
mV

!lA
%
).IA
dB

!lAJV
pV-sec
dBc

dBc
dBc
dBc

For More Infonnation call 1-800·722·7074.

TDCI041
Applications Information
There are three major 0/A architectures: segmented,
weighted current sources, and R-2R. In segmented there
is one current source for each possible output level. The
current sources are equally weighted and for an input code
of N, N current sources are turned on. An N bit segmented
0/A has 2N current sources. A weighted current source
O/A has one current source for each bit of input with a binary
weighting for the current sources. In an R-2R 0/A, there is
one current source per bit, and a resistor network which
scales the current sources to have a binary weighting.
When transitioning from a code of 0111111111 to
100000000000, both the R-2R 0/A and Binary weighted
O/A are turning some current sources on while turning
others off. If the timing is not perfect, there is a moment
where all current sources are either on or off, resulting in
a glitch. In a segmented architecture, 511 of the current
sources remain on, and one more is turned on to increment
the output no possibility of a glitch.
The TOCl 041 uses a hybrid architecture with the 6 MSBs
segmented, and the 4 LSBs from a R-2R network. The result
is a converter which has very low-glitch energy, and a
moderate die size.

Layout. Power and Grounding
The layout of grounds in any system is an important
design consideration. Separate analog and digital grounds
are provided at the TOC1041. All ground pins should be
connected to a common low-noise, low-impedance
groundplane. This groundplane should be common for the
TOC1041 and all of its immediate interface circuitry, which
includes all of the reference circuitry, the output load
circuitry, and all of the power supply decoupling
components.
The digital driving logic should use a separate system
ground, and this ground should be connected (typically
through a ferrite bead inductor) to the analog groundplane
in only one place. The analog and digital grounds may be
connected in other ways if required by the user's system
grounding plan, however, the voltage differential between
the AGNO and OGNO pins must be held to within iD.l
Volts.

Direct Digital Synthesis Applications
There are many factors that can influence the system
performance of a direct digital synthesizer. The following

For More Information call 1-800-722-7074.

comments are directed at getting the best possible
performance from the TOCl 041, as measured by Spurrious
Free Dynamic Range (SFDR).
The termination of the output pins has an effect on OAC
performance. For most synthesis applications, optimum
signal purity is obtained with the use of a balun (a simple
RF transformer made by wrapping a few turns of wire
around a ferrite core). This configuration has the benefit
of cancelling common mode distortion.
Harmonic distortion may improve even further with reduced
AC termination impedance values, at the expense of
lowered output voltage.
An output amplifier is not recommended because any
amplifier will add extra distortion of its own, which is
likely to be much greater than that present from the direct
outputs of the TOCl 041.
One detrimental effect in OAC performance is capacitive
coupling of the digital data into the output terminal. The
actual digital-data waveform which represents a sine wave
contains strong harmonics of that sine wave. This can be
seen by connecting a digital data line to the input of an
analog spectrum analyzer. Therefore data feedthrough to
the analog output of a system due to improper board
layout or system shielding and grounding will appear as
additional harmonic distortion, adversely affecting SFDR.
The strict adherence to at least the minimum input data
setup and hold times is important for the realization of the
optimal performance. Spur levels may decrease as setup
and hold times are increased. It is possible to achieve even
higher performance in some instances by carefully "tuning"
the input data setup and hold times (slightly delaying or
advancing the CONV signal in relation to the data) fed to
the TOCl 041. The Operating conditions table has two
sets of data for ts and tH, one which guarantees
performance of the device in most applications, and one,
more conservative specification which has been found to
be optimal for DDS applications
The purity of the output of the TOCl 041 is greater than that
which can be measured by many spectrum analyzers. The
spectral plots shown in this data sheet were generated
with an HP8568B, which has a noise floor barely below
that of the TOC1 041, once the TOCl 041 performance has
been optimized. When making spectral measurements it is
important to remember that the TOCl 041 output power is
+4dBm, which is greater power than many analyzers are

Raytheon Semiconductor

3-203

I

TDCI041
equipped to handle without adding distortion of their own.
Accordingly, it may be necessary to introduce an attenuator
to the input of the spectrum analyzer to see the true DAC
performance.

Output Termination
The recommended output termination is 250. This can be
provided by placing a 500 source resistor between the
output pin and ground, then driving a 500 transmission
line. With this load, the output voltage range of the
converter is 0 to -1.0V. If a load is capacitively coupled to
the TOC1 041, it is recommended that a 250 load at DC,
as seen by the TOC1 041, continue to be maintained. The
output voltage should be kept within the output compliance
voltage range, VOG. as specified in the Electrical
Characteristics table, or the accuracy may be impaired~
Optimum DC linearity is obtained by using a differential
output either with a balun, or an operational amplifier in
the differential mode. If it is desired that the TOC1 041 be
operated in a single ended fashion, the unused output

3-204

should be connected directly to ground as is shown in
Figure 5. The CONV signal provided to the TOC1 041
must be as free from clock jitter as possible. Clock jitter
is the random cycle-to- cycle variation in clock period.
CONV clock jitter will effectively appear at the output as
phase noise. A value of lOps or less for clock jitter is
recommended for the highest performance applications.
Ordinary crystal oscillators are satisfactory. Highperformance synthesizers, such as the HP8662, used to
trigger a precision pulse generator, are also satisfactory,
although not as jitter free as a crystal oscillator.

Driving a 750 Transmission line
The TOC1041 has been optimized to operate with a
reference current of 625~. Significantly increasing or
decreasing this current may degrade the performance of
the device. If it is desired that the device drive a 37.50
load (750 source termination driving 750 transmission
line) rather than the 250 suggested load, then VREF should
be held at 1V and IREF reduced to 417~. This will result in
a 1V p-p voltage being generated at the DAC output.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCI041
Figure 5. Typical Interface Circuit
Vee
(

lq. ~>-

.J.~~
,,,

1

I

~AIN
2J('

[' -!-

~

LM611

Ul

.1~~

-yy,

~

Vee

-'

+

i

":'

,~
1.5Kj;

G
10

10

0 1(MSB)

20

20

O2

30
U3

40
"-

?-

;: 1.5K

VCC

ClK

'-

.:.

30

03

40

04

~
,~

50

50

05

60

60

06

10

10

01

,"-

SO

SO

Os

74lS314

REF+

-

REF-

COMP

r-----;I--<> -sv

TOC1041

G
ClK

'"

~,

10

10

09

20

20

010 (LSB)

30

30
U4

40

-

50

60
10
SO

74lS314

,

OUT+

40

r-60 r-10 r-So r--

50

,.

CONY

FT

OUT

VEEO VEEA 0GNO AGNO

=rf=F
-sv

~

~25::
~...?"-'
- ...~25
"..

t-

~

24091A

GNO

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-205

TDCI041
Ordering Information
Product Number

TDC1041 R3C
TDC1041R3Cl

Temperature Range

TA=O°C to 70°C
TA=O°C to 70°C

Screening

Commercial
Commercial

Package

Package Marking

Plastic Chip Carrier
Plastic Chip Carrier

1041R3C
1041R3Cl

40G06718 Rave 9193

3-206

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCll12
TDCll12
Monolithic Digital-to-Analog Converter

I

12-Bit, 50 Msps, 12 ns Settling lime to 0.1 %, 70 dB SFDR

Description

Features

The TDC1112 is a ECl compatible, 12-bit monolithic
D/A converter capable of converting digital data into an
analog current at data rates in excess of 50
Megasamples-per second (Msps).

•
•
•
•
•

The analog circuitry has been optimized for dynamic
performance, with very low glitch energy. The output is
able to drive a 500 load with 1 Volt outpuls while
keeping a spurious-free-dynamic range greater than 70
dB.
Data registers are incorporated on the chip. This
eliminates the temporal data skew encountered with
external registers and latches and minimizes the
glitches that can adversely affect many applications.

•
•

12-bit resolution
50 Msps data rate
ECl inpuls
Very Iow-glitch with no track and hold circuit needed
Dual;4 dBm (1V into 50q outpuls make output
amplifiers unnecessary in many applications
70 dB typical spurious-free-dynamic-range
Available compliant to Mll-STD-883C

Applications
•
•
•
•
•

Direct digital RF Signal generation
Test signal generation
Arbitrary waveform synthesis
Broadcast and studio video
High-resolution AID converters

Interface Diagram

21338A

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-207

TDCl112
Functional Block Diagram
REF+

>-----_--------,

REFERENCE
, ___A:M:PL~IF~IE:R_~~~--1
REF· ;
COMP
.........J

>-_____

63 UNIFORMLY WEIGHTED
MSB CURRENT SWITCHES

Dl (MSB)
D2
D3

MSBDECODE
REGISTER

D4
D5
D6
CONY

OUT+
CURRENT
SWITCH ARRAY

CONY

OUT·

FT

D7
D8
D9

LSBDATA
REGISTER

DlO
D11
D12 (LSB)

6 BINARY WEIGHTED
....._ _ _ _ _ _ _ _ _...... LSB CURRENT SWITCHES

21339A

Pin Assignments
D91

24D8

D10 2

23 D7

D11

3

22 VEED

D12 (LSB)

4

21 COMP

AGND

5

20 REF +

OUT + 6

19 REF·

OUT·

7

18 VEEA

DGND

8

17 FT

D6

9

16 CONY

D5 10

15 CONY

D4 11

14 Dl (MSB)

D3 12

--....._ _ _.....r

NC
DGND
NC
OUT·
OUT +
AGND
NC

It)U),,,,"Q)cn~;::

lHoccooCJ) J!cf~

13 D2

>
21340A

24 Pin Hermetic Ceramic DIP - J7 Package
24 Pin Plastic DIP - N7 Package
3·208

~ 18
~ 17
~ 16
~ 15
14
13
12

CONY 26
CONY 27
FT 28
VEEA
REF·
REF +
COMP 4

Q'"

21341A

28 Contact Chip Carrier - C3 Package
28 Leaded Plastic Chip Carrier - R3 Package

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDCll12
Functional Description
General Information
The TDCll12 consists of five major circuit sections: the
LSB data register, the MSB decode block, the decoded
MSB register, the current switch array, and the reference
amplifier. All data bits are registered just before the
current switches to minimize the temporal skew that
would generate glitches.

digital signals contain high-frequency harmonics of the
clock, as well as the signal that is being provided to the
DAC, the result of data feedthrough often looks like
harmonic distortion which degrades the Spurious-FreeDynamic-Range (SFDR) performance of the D/A.

The layout of grounds in any system is an important
There are three major D/A architectures: thermometer
design consideration. Separate analog and digital grounds
code segmentation, weighted current sources, and
are provided at the TDCll12. All ground pins should be
R- 2R. In thermometer code segmentation there is one
connected to a common low-noise, low-impedance
current source for each possible output level. The current groundplane. This groundplane should be common for the
TDCll12 and all of its immediate interface circuitry,
sources are equally weighted and for an input code of
N, N current sources are turned on. An N bit segmented which includes all of the reference circuitry, the output
D/A has 2N current sources. A weighted current source
load circuitry, and all of the power supply decoupling
D/A has one current source for each bit of input with a components.
binary weighting for the current sources. In an R- 2R
The digital driving logic should use a separate system
D/A, there is one current source per bit, and a resistor
network which scales the current sources to have a
ground, and this ground should be connected (typically
binary weighting.
through a ferrite bead inductor) to the analog groundplane in only one place. The analog and digital grounds
When transitioning from a code of 011111111111 to
may be connected in other ways if required by the user's
system grounding plan, however, the voltage differential
100000000000, both the R- 2R D/A and binary
weighted D/A are turning some current sources on while between the AGND and DGND pins must be held to
turning others off. If the timing is not perfect, there is a within ± 0.1V.
moment where all current sources are either on or off,
resulting in a glitch. In a segmented architecture, 2047
Reference
of the current sources remain on, and one more is
The TDCll12 has two reference inputs: REF + and
turned on to increment the output-no possibility of a
REF -. These are the inverting and noninverting inputs of
glitch.
the internal reference amplifier. An externally generated
reference voltage is applied to the REF - pin. Current
The TDCll12 uses a hybrid architecture with the 6
flows into the REF + pin through an external current
MSBs segmented, and the 6 LSBs from a R- 2R
setting resistor (RREF). This current is the reference
network. The result is a converter which has very low
current (lREF) which serves as an internal reference for
glitch energy, and a moderate die size.
the current source array. The output current for an input
code N from OUT+ is related to IREF through the
Power, Grounds, and layout
following relationship:
The TDCll12 requires a single - 5.2V power supply. The
IREF
analog (VEEA) and digital (VEED) supply voltages should
lOUT (Input Code N) = N x 64
be decoupled from each other, as shown in the Typical
Interface Circuits, to provide the highest noise immunity.
This means that with an IREF that is nominally 625p.A,
The 0.1 p.F decoupling capacitors should be placed as
the full scale output is 40mA, which will drive a 500
close as possible to the power pins. The inductors are
load in parallel with a 500 transmission line (250 load
simple ferrite beads and are neither critical in value nor
total) with a 1V peak-to-peak signal. The impedance
always required.
seen by the REF- and REF+ pins should be approximately equal so that the effect of amplifier input bias
The high slew-rates of digital data make capacitive
current is minimized.
coupling with the D/A output a real problem. Since the
For More Information call 1-800-722·7074.

Raytheon Semiconductor

3·209

I

TDCll12
Reference (cont.)
The TDCll12 has been optimized to operate with a
reference current of 625JtA. Significantly increasing or
decreasing this current may degrade the performance of
the device. The minimum and maximum values for VREF
and IREF are listed in the Operating Conditions Table.
The internal reference amplifier is externally compensated
to assure stability. To compensate this amplifier, a 0.1 p,F
capacitor should be connected between the COMP pin
and VEEA The amplifier has been optimized to minimize
the TDCll12 settling time, and as a result should be
considered a DC amplifier. Performance of the TDCll12
operating in a multiplying OIA mode is not guaranteed.
A typical interface circuit that includes a stable,
adjustable reference circuit is shown in Figures 9a-c.

output changes only after a clock rising edge). An
internal pull-down resistor is provided, and this pin may
be left open for clocked operation. For certain applications, such as high-precision successive approximation
AID converters, speed may be more important then
glitch performance. In these cases, the FT pin may be
brought HIGH, which makes the input registers transparent. This allows the analog output to change
immediately and asynchronous in response to the digital
input, without the need for a clock.
Since skew in the bits of the input word will result in
glitches, and may affect settling time, it is recommended
that the TOCll12 be operated in clocked mode for most
applications.

Analog Outputs
Digital Inputs
The data inputs are single-ended ECl compatible. The
TDCll12 is specified with two sets of setup and hold
times. One of these pairs of specifications guarantees the
performance of the TDCll12 to specifications listed in
the minimum and maximum columns of the System
Performance Characteristics Table. The second more
rigid specification is recommended for applications where
lowest possible glitch and highest SFDR are desired. The
more stringent ts and tH insure that the data will not be
slewing during times critical to the TDCll12, and will
hence minimize the effects of capacitively coupled data
feedthrough and optimize SFDR performance. Another
method reducing the effect of capacitive coupling is to
slow down the slew rates of the digital inputs. This has
been done in the circuit shown in Figures 9a-c by the
addition of 50n series resistors to the data lines.

Clock and Feedthrough Control
The TDCll12 requires an ECl clock signal (CONVert and
CONVert). Even though complementary operation is
preferred, a single-ended signal may be used if either
unused CONV input is biased at a DC voltage midway
between the active input's VIH and Vil levels.
Data is synchronously entered on the rising edge of
CONV (the falling edge of CONV). The CONV input is
ignored in the Feedthrough (FT= HIGH) mode.
The Feedthrough (FT) pin is normally held lOW, in which
case the TOCll12 operates in a clocked mode (the

3-210

Two simultaneous and complementary analog outputs are
provided. Both of these outputs are full-power current
sources. By loading the current source outputs with a
resistive load, they may be used as voltage outputs.
OUT + provides a 0 to - 40mA output current (0 to
-lV when terminated in 25n) as the input code varies
from 0000 0000 0000 to 1111 1111 1111. OUT-varies
in a complementary manner from - 40 to OmA (-1 to
OV when terminated with 25n) over the same code
range. (See the Output Coding Table.) The output
current is proportional to the reference current and the
input code.
The recommended output termination is 25n. This can
be provided by placing a 50n source resistor between
the output pin and ground, then driving a 50n transmission line. With this load, the output voltage range of
the converter is 0 to -1.0V If a load is capacitively
coupled to the TOCll12, it is recommended that a 25n
load at DC, as seen by the TDCll12, continue to be
maintained. The output voltage should be kept within the
output compliance voltage range, VOC, as specified in
the Electrical Characteristics Table, or the accuracy
may be impaired.
See Figure 9b for a suggested circuit for achieving a
bipolar output voltage range. Optimum DC linearity is
obtained by using a differential output either with a
balun, or an operational amplifier in the differential
mode. If it is desired that the TDCll12 be operated in a
single ended fashion, the unused output should be
connected directly to ground as is shown in Figure 9c.

Raytheon Semiconductor

For More Information call 1-1100-722-7074.

TDCll12
Package Interconnections
Signal
Type
Power

Reference

Data Input

Signal
Name

C3, R3 Package Pins

Value

J7, N7 Package Pins

-5.2V
-5.2V

18

1

22

AGND
DGND

Analog Supply Voltage
Digital Supply Voltage
Analog Ground
Digital Ground

O.OV
O.OV

5
8

5
13

REF-

Reference Voltage Input

REF+
COMP

Reference Current Dutput
Compensation Capacitor

-1.0V
0.625mA
O.I/LF. See Text

Dl (MSB)

Most Significant Bit Input

ECl

VEEA
VEED

Function

D2
D3
D4
D5
D6
D7
D8

17

19

2

20
21

3
4

14
13
12
11
10
9

24

ECl
ECl
ECl
ECl
ECl
ECl
ECl
ECl
ECl

23
24
1
2

23

22
21
20
19
6
7

D9
DIO
Dll
D12 (lSB)

least Significant Bit Input

ECl
ECl

3
4

8
9
10
11

Feedthrough

FT

Feedthrough Mode Control

ECl

17

28

Convert (Clock)

CONV
CONV

Convert (Clock) Input
Convert (Clock) Input

ECl
ECl

16
15

27
26

Analog Output

OUT+
OUT-

Analog Output

-40mA
-40 to OmA

6
7

14

For More Information call 1-800-722-7074.

Analog Output

o to

Raytheon Semiconductor

15

3-211

I

TDCll12
Output Coding Table 1
Input Data
MSB
0000
0000
0000

0000
0000
0000

D1-12
LSB

OUT+ (rnA)

VOUT + (mV)

OUT- (rnA)

0000
0001
0010

0.000
0.009
0.019

0.00
-0.24
-0.49

40.000
39.990
39.980

1111
1111
1111

-1000.00
-999.75
-999.52

0

0

0

0

0

0

0

0

0

0

0

0111
1000

VOUT- (mV)

1111
0000

1111
0000

0

0

0

19.995
20.005

-499.88
-500.12

20.005
19.995

0

-500.12
-499.88

0

0

0

0

0

0

0

0

0

o·

0

0

0

0

1111
1111
1111

1101
1110
1111

-999.52
-999.75
-1000.00

39.980
39.990
40.000

0

-0.49
-0.24
0.00

0.019
0.009
0.000

Figure 1. Timing Diagram

's

'SF

'H

'HF

INPUT DATA
(01-121

CONV
(PIN 161
FT
(PIN 17)

OV

OUT(PIN 71

-IV

'SET

3-212

±% LSB

'SET

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TDCll12
Figure 2a. Equivalent Input Circuit (Data and H)

Figure 2b. Equivalent Input Circuit (CONV and
CONY)

INPUT o--t---"WI.--t--....,..---I

I

CONY o-l---+--i-'\rvIr-+---1

100
CONY o-t-J1.J\A,--f---+---+---+---'

40K

21344A

21343A

Figure 3. Equivalent Reference and Output Circuits
CURRENT
SINK#N
r----!-V'"~-....,..--___!~--o

OUT +

...--.....,.1'-_-+-....,..--+----0 OUT·
REFERENCE
AMPLIFIER

REF+
REF·

REFERENCE
CURRENT

r------, r-----'
I
I

o--_1_--i
I
I

I
I

L__ _

L-----r-----+--------+------

COMP

Figure 4. Standard Test Load
TESTLOAD:

VEEA

21345A

Figure 5. CONY and CONY Switching levels

- - - - - - - - - - - - - - - - - - - - - - o.ov

21346A

,,
.'-----, '
, '
, '" ' '----V-

.,----,-

OUT+ o-..,..--_-.orO.1V
OUT·

_

-

-

_

-

-

--- ---- ---- -

_'" -

~_ -

V
-----------,
ICMMAX

For More Information call 1-800-722-7074.

Raytheon Semiconductor

-- -

-

-

-

-

vlCMMIN

·1.3V
CONY

~CONV
21347A

3-213

TDCll12
Absolute maximum ratings (beyond which the device may be damaged) 1
Supply Voltages
VEEA (measured to AGNOI .
................................................................................................................... -7.0 to +0.5V
VEEA (measured to VEEDI ........................................................................................................................................... - 50 to + 50mV
VEEO (measured to 0GNOI ............................................................................................................................................ - 7.0 to + 0.5V
AGNO (measured to DGNOI ........................................................................................................................................... - 0.5 to + 0.5V
Inputs
Applied voltage
CONY, CONY, FT, 0 1- 12 (measured to 0GNOl z ............................................................................................... VEEO to +O.OV
REF+, REF- (measured to AGNOl2 ................................................................................................................... VEEAto +O.OV
Applied current
REF +, REF -, externally forced (measured to AGNDI 3.4 ............................................................................................... ± 3mA
Digital inputs ................................................................................................................................................................................... ± 3mA
Outputs
Applied voltage
OUT +, OUT - (measured to AGNOI Z ••••••••••••••••.•••••••..•••••••.•••••••••..••••••••..•••••••..•••••••.•.•••••..•..••••..•.•••••.....••••......• - 2.0 to + 2.0V
Applied current
OUT +, OUT -, externally forced (measured to AGNOI 3.4 ........................................................................................... + 50mA
Short-circuit duration (single output to GNDI ....................................................................................................................... Unlimited
Temperature
Operating, ambient (plastic packagel ........................................................................................................................... - 20 to + 90°C
(ceramic packagel ...................................................................................................................... - 60 to + 150°C
junction (plastic packagel ........................................................................................................................................ + 140°C
(ceramic packagel ..................................................................................................................................... + 200°C
Lead, soldering (10 secondsl ..................................................................................................................................................... + 300°C
Storage ............................................................................................................................................................................ -65 to + 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions IS NOT implied. Device performance and reliability are guaranteed only if the Operating
Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

3-214

Raytheon Semiconductor

For More Infonnation caJI1-800-722-7074.

TDCll12
Operating conditions
Temperature Range
Commercial
Min
Nom

Parameter
FS

Clock Frequency

VEEA
VEEA
VAGND

Analog Supply Voltage (measured to AGNDI
Analog Supply Voltage (measured to VEEDII
Digital Supply Voltage (measured to DGNDI
Analog Ground Voltage (measured to DGNDI

VREF

Reference Voltage, REF-

IREF

Reference Current, REF +

Cc

Compensation Capacitor

VIL
VIH

Digital Input Voltage, Logic LOW
Digital Input Voltage, Logic HIGH

ts
ts
tH
tH

Input
Input
Input
Input

tSF
tHF

Setup Time, Data to FT
Hold Time, Data to FT

VICM
VIDF

CONV Input Voltage, Common Mode Range 3
CONV Input Voltage, Differential 3

tpWL

CONV Pulse Width LOW
;;;. 40Msps

VEED

tpWL
tpWH

Data
Data
Data
Data

50

0
-4.9
-20
-4.9
-0.1

Max

-5.2
0.0
-5.2

-5.5
+20
-5.5

0.0

0.1

-0.7
0.550

-1.0
0.625

-1.3
0.700

0.01

0.1

Min
0

Setup Time
Setup Time 2
Hold Time
Hold Time 2

CONV Pulse Width HIGH
;;;'40Msps

MHz
V
mV
V
V

-5.2

-5.5

0.0
-5.2

+20
-5.5
0.1

-0.7

-1.0

0.0

0.575

0.625

0.01

0.1

-1.3
0.675

18
24
0

-0.5
0.4

V
V
ns
ns
ns

4

-2.0
1.2

V
mA
I'F

-1.60

7
24

< 40Msps
CONV Pulse Width LOW 2

Units

50

-1.00

17
24
0
4

-0.5
0.4

Max

-4.9
-20
-4.9
-0.1

-1.55
-1.05

Military
Nom

ns
7
24

ns
ns

-2.0
1.2

V
V

10.5
11
18

10.5
11
18

ns
ns
ns

8.0
9.0
11

8.5
9.0
11

ns
ns
ns

tpWH

<40Msps
CONV Pulse Width HIGH 2

TA
TC

Ambient Temperature, Still Air
Case Temperature

Notes:

1. A common power supply, isolated simply with femte bead inductors. is recommended for VEEA and VEED .
See the TYPical Interface Circuits, Figures 9a-c.

0

70
-55

125

°c
°c

2. SFDR senSitive applications.
3. See Figure 5., CDNV. CONV Switching levels.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-215

I

TDCll12
Electrical characteristics within specified operating conditions 1
Temperature Range
Parameter
lEE

Supply Current (lEEA + IEED)2

Commercial
Min
Max

Military
Min
Max

VE EA =Max 3

-180

-195

TA=70 °c
TC= 125°C

-150

Test Conditions

-145

CREF
CI

Reference Input Capacitance
Digital Input Capacitance

IlL

Digital Input Current, Logic LOW
Digital Input Current, Logic HIGH
CONV Input Current

VEED= Max, VI= -1.85V
VEED = Max, VI = - 0.8V

Output Resistance

VOC

Output Capacitance
Output Compliance Voltage

OUT +, OUTOUT +, OUTOUT +, OUT-

-1.2

10

Full-Scale Output Current

OUT +, OUT-

40

IIH
IIC
RO
Co

Notes:

REF+, REF-

15
15

Dl-12' FT, CONV, CONV
-10

15
15
-10

200
200

-10

250
250

-10

50

VEED=Max, -1.85V-----_-------.
REFERENCE
AMPLIFIER

REF·
COMP

r----+--------,

01 (MSB)

63 UNIFORMLY WEIGHTED
MSB CURRENT SWITCHES

O2

03

MSBDECODE
REGISTER

04
05
06
CONY

OUT.
CURRENT
SWITCH ARRAY

CONY

OUT·

FT

LSBDATA
REGISTER

6 BINARY WEIGHTED
...._ _ _ _ _ _ _ _ _..... LSBCURRENTSWITCHES

Pin Assignments

21591A

Functional Description
General Description

CONY
CONY
FT
VEEA
REF·
REF.
COMP

18 NC

26
27
28
1
2
3

17
16
15
14

DGND
NC
OUT·
OUT.

13 ~ND
12 NC

4

0
..... co 0> 0 0 0
ttl0 C 0 c Z : Z :

>

iii"
~

21592A

28 Leaded Plastic Chip Carrier - R3

3·226

The TDC1141 consists of five major circuit sections: the
LSB data register, the MSB decode block, the decoded
MSB register, the current switch array, and the reference
amplifier. All data bits are registered just before the
current switches to minimize the temporal skew that would
generate glitches.

Power and Grounds
The TDC1141 requires a single -5.2V power supply. This
supply is divided into analog (VEEA) and digital (VEED)
supply pins which should be decoupled from each other.
An example of this decoupling is shown in the Typical
Interface Circuit. The 0.1!1F decoupling capacitors should
be placed as close as possible to the power pins. The

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TDCl141
inductors are simple ferrite beads and are neither critical in
value nor always required.

Data is synchronously entered on the ri.sing edge of CO~V
(the falling edge of CQliJiJ). The CONV Input IS Ignored In
the Feedthrough (FT = HIGH) mode.

Reference and Compensation
The TDCl141 has two reference inputs: REF+ and REF-.
These are the inverting and noninverting inputs of the
internal reference amplifier. An externally generated
reference voltage is applied to the REF- pin. Current flows
into the REF+ pin through an external current setting
resistor (RREF). This current is the reference current (IREF)
which serves as an internal reference for the current
source array. The output current for an input code N from
OUT+ is related to IREF through the following relationship:
lOUT =N x IREF
16
Where N is the input code to the OJA converter

The Feedthrough (FT) pin is normally held lOW, in which
case the TDCl141 operates in a clocked mode (the output
changes only after a clock rising edge). An internal pulldown resistor is provided, and this pin may be left op~n for
clocked operation. For certain applications, such as hlghprecision successive approximation AID converters, output
delay may be more important than glitch perform~nce. In
these cases, the FT pin may be brought HIGH, which makes
the input registers transparent. This allows the analog
output to change immediately and asynchronously In
response to the digital input, without the need for a clock.

Analog Outputs

The internal reference amplifier is externally compensated
to ensure stability. A 0.1j.lF capacitor should be connected
between the COMP pin and VEEA

Two simultaneous and complementary analog outputs are
provided. Both of these outputs are full-power cu.rrent
sources. By loading the current source outputs With a
resistive load, they may be used as voltage outputs.
OUT+ provides a 0 to -40mA output current (0 to -1 V
when terminated in 250) as the input code varies from
00 0000 0000 to 11 1111 1111. OUT-varies in a
complementary manner from -40 to OmA (-1 to OV when
terminated with 250) over the same code range. (See the
Input Coding Table.) The output current is proportional to
the reference current and the input code.

Digital Inputs

No Connect

This means that with an IREF that is nominally 625f.lA, the
full-scale output is 40mA, which will drive a 500 load in.
parallel with a 500 transmission line (250 load total) with
a 1V peak to peak signal. The impedance seen by the REFand REF+ pins should be approximately equal so that the
effect of amplifier input bias current is minimized.

All digital inputs including the FT, CONV and Data Inputs
are compatible with ECl logic. Input registers arepro~lded
on the data input lines to minimize the effect of glltchlng
caused by data skew.

These pins have no internal connection and should be left
open for optimal performance.

Clock and Feedthrough Control
The TDCl141 reguires a differential ECl clock signal
(CONVert and CONVert). Even though complementary
operation is preferred, a single-ended signal may be used
if either unused CONV input is biased at a DC voltage
midway between the active input's VIH and Vil levels.

For More Information caJI1-800-722-7074.

Raytheon Semiconductor

3-227

I

TDCl141
Package Interconnections
Signal
Type

Signal
Name

Power

AGND
DGND
VEEA
VEED

Analog Ground
Digital Ground
Analog Supply Voltage
Digital Supply Voltage

O.OV
O.OV
-5.2V
-5.2V

13
17
1
5

Reference

REFREF+
COMP

Reference Voltage Input
Reference Current Input
Compensation Capacitor

-1.0V
625tJA
0.1 tH', see text

2
3
4

Data Inputs

Dl (MSB)
D2
D3
D4
D5
D6
D7
D8
D9
D10 (lSB)

Most Significant Bit

least Significant Bit

ECl
ECl
ECl
ECl
ECl
ECl
ECl
ECl
ECl
ECl

24
23
22
21
20
19
6
7
8
9

Feedthrough

FT

Feedthrough Mode control

ECl

28

Convert

CONY
CONY

Convert (Clock) Input
Convert Complement

ECl
ECl

27
26

Analog Output

OUT+
OUT-

Analog Output
Analog Output

Oto 40mA
40 to OmA

14
15

No Connect

NC

No Internal Connection

Open

10,11,12,16,18,25

Function

Value

R3 Package
Pins

Input Coding Table 1
Input Data
MSB LSB

VOUT+(mV)

OUT-(mA)

VOUT-(mV)

0000000000
0000000001
0000000010

0.000
0.039
0.078

0.00
-0.97
-1.95

40.000
39.961
39.922

0111111111
1000000000

19.961
20.000

-499.03
-500.00

20.000
19.961

-500.00
-499.03

1111 1111 01
1111111110
1111111111

39.922
39.961
40.000

-998.05
-999.03
-1000.00

0.078
0.039
0.000

-1.95
-0.97
0.0

···

···

Note:

3·228

OUT+(mA)

··
·
··
·

···
··
·

··
·
··
·

-1000.00
-998.05
-998.05

··
·
··
·

1. IREF =625iJA, RLOAO =250

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TDCl141
Figure 1. Timing Diagram

I

INPUT
(D
- ) _ _ _ _oJ
I 12

CONV

~--~------------~--------------------'I
DV

OUT-

-IV

±1/2 LSB
'SET

24D77A

Figure 2. Equivalent Input Circuit (Data and FT)

INPUT

Figure 3. Equivalent Input Circuit (CONV and CONV)

o-+---'Wlr--+-_---I

CONY o-+-----'I__-~\fV1"'"""I__-I

100
CONY o-+--"IM.,.....-1I---+----1I----+--...J

40K

21343A

21344A

Figure 4. Equivalent Reference and Output Circuits
CURRENT
SINK#N

.--_ _-+--./I......L_ _>----...L--o OUT +
,...--.....,.f\--+---+-__1>----II----o OUTREFERENCE
CURRENT

1"-----,

REF +

I
I

REF -

o----i---I
I
I
I
I __ _
L

. . . .-------......------ VEEA

~__o-----

COMP

For More Information caJI1-800-722-7074.

21345A

Raytheon Semiconductor

3-229

TDCl141
Figure 5. Standard Test Load
TEST LOAD:
OUT +
OUT·

Figure 6. CONY and CONY Switching Levels
- - - - - - - - - - - - - - - - - - - - - - O.OV

D-_----...---1~

,,
'''-----, , ' '
, '" ' '----V'~----, -

0 TO-IV

-

-

21346A

VICMMAX -

-

-

-

-

-

-

-

-

-

-

-

-~

-

-

-

-

-

..lIo., _ _ _ _ _ _ _ _ _ ·1.3V

-

-

-

-

-

,

-

-

-

-

-

-

-

VICMMlN

CONY

~ CONY

21347A

Absolute maximum ratings (beyond which the device may be damaged)1
Supply Voltages
VEEA
VEEA
VEED
AGND

(Measured to
(Measured to
(Measured to
(Measured to

AGND) ....................................................................................................................................................-7.0 to +0.5V
VEED) .....................................................................................................................................................-50 to +50mV
DGND) ....................................................................................................................................................-7.0 to +0.5V
DGND) ....................................................................................................................................................-0.5 to +0.5V

Inputs
CONV, CONY, FT, Dl-12 (Measured to DGND)2 ....................................................................................................................... VEED to +0.5V
REF+, REF-, Applied Voltage
(Measured to AGND)2..
. ........ VEEA to +0.5V
REF+, REF-, Current, Externally Forced 3,4 .................................................................................................................................................. ±3mA
Outputs
OUT+, OUT-, Applied Voltage
.. .. -2.0 to +2.0V
(Measured to AGND)2 .....
OUT t, OUT-, Current, Externally Forced3.4 ..
.. ..................................... +50mA
Short-Circuit Duration (Single Output to GND) .................................................................................................................................... unlimited
Temperature
Operating, ambient
(Plastic Package) ...........................................................................................................................................................-20 to +90°C
(Ceramic Package) ......................................................................................................................................................--fjOto +l50°C
Junction
(Plastic Package) .....................................................................................................................................................................+140°C
(Ceramic Package) ..................................................................................................................................................................+200°C
Lead, Soldering (10 Seconds) ..........................................................................................................................................,.......................... +300°C
Storage
........................................................................................................................................................................................--fj5to+l50°C
Notes:

3-230

1. Absolute maximum ratings are limiting values applied individually while other parameters are within specified operating conditions. Functional
operation under any of these conditions is NOT implied. Device performance and reliability are guaranteed only if the Operating Conditions are
not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

Raytheon Semiconductor

For More Infcrmation call 1-800-722-7074.

TDCl141
Operating conditions
Temperature Range
Parameter

Min

FS

Clock Frequency

VEED
VEEA
VAGND
VEEA

Negative Supply Voltage (Measured to DGND)
Negative Supply Voltage (Measured to AGND)
Analog Ground Voltage (Measured to DGND)
Negative Supply Voltage (Measured to VEED)1

tpWL

CONY
CONY
CONY
CONY

tpWH

Pulse Width
Pulse Width
Pulse Width
Pulse Width

Standard
Nom

0

LOW (FS>40 Msps)
LOW (FS<40 Msps)
HIGH (FS>40 Msps)
HIGH (FS<40 Msps)

-4.9
-4.9
-0.1
-20

-5.2
-5.2
0.0
0

Max
50

Msps

-5.5
-5.5
0.1
20

V
V
V
mV

10.5
11
8
9

ns
ns
ns
ns

ts
tH

Setup Time, Data to CONY
Hold Time

17
0

ns
ns

tSF
tHF

Setup Time, Data to FT
Hold Time, Data to FT

7
24

ns
ns

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

-1.05

VREF
IREF

Reference Voltage (REF-)
Reference Current (REF+)

-1.55

-0.7
400

Cc

Compensation Capacitor

0,01

TA

Ambient Temperature, Still Air

0

Note:

-1.0
625

-1.3
700

0.1

I

Units

V
V
V
~

!If
70

°C

1. A common power supply isolated with ferrite bead inductors is recommended for VEEA and VEED. This is shown in the Typical Interface Circuits.

Electrical characteristics within specified operating conditions
Temperature Range
Parameter

Test Conditions

IEEA+IIEED

VEEA=VEED=Max,static TA=O to 70°C
TA=70°C

CREF
CI

Reference Input Capacitance
Digital Input Capacitance

VOC
RO

Compliance Voltage
Output Resistance

Co
10

Output Capacitance
Full-Scale Output Current

IREF=625~

IlL
IIH

Input Current, Logic LOW
Input Current, Logic HIGH

VEE=Max, VI=O.4V
VEE=Max, VI=2.4V

For More Infonnation call 1-800-722-7074.

Min

Standard
Max
-180
-150
15
15

-1.2
12

1.2

45

Raytheon Semiconductor

40
-10
-10

200
200

Units
rnA
rnA
pF
pF
V
kQ
pF
rnA
~

WA

3-231

TDCl141
Switching characteristics
Temperature Range
Parameter

Test Conditions

tDC
too
tDF
tR

Clock to Output Delay
Data to Output Delay
FT to Output Delay
Risetime 1

tF

Falltime 1

tSET

Settling Time, Voltage

Note:

Min

Standard
Typ

Max

2

20
25
30
4

ns
ns
ns
ns

2

4

ns

12

20

ns

VEEA, VEED=Min, FT=lOW
VEEA, VEED=Min, FT=HIGH
VEEA, VEED=Min
90% to 10% of FSR,
FT=LOW
10% to 90% of FSR,
FT=lDW
FT=LOW, Full-Scale
Voltage transition
on IDUPO 0.1 % FSR

Units

1. Clocked Mode

System performance characteristics
Temperature Range
Parameter
ELO

Ell

VDS
IB
EG
IOF
PSRR
PSS
GA
Notes:

3-232

Test Conditions

Differential linearity Error

Integral linearity Error

REF+ to REF- Offset Voltage
REF- Input Bias Current
Absolute Gain Error
Output Offset Current
Power Supply Rejection Ratio
Power Supply Sensitivity
Peak Glitch Area
1.

Min

Standard
Typ

VEEA, VEED, IREF= Nom 1
TDC1141
TDC1141-1
VEEA, VEED, IREF = Nom 1
TDC1141
TDC1141-1
-10
5
VEEA, VEED, IREF = Nom
VEEA, VEED= Max, 01-12 = LOW
VEEA, VEED, IREF = Nom 2
VEEA, VEED = ±4%, IREF = Nom

-5

Max

Units

±O.1
±O.05

%
%

±O.1
±O.05
+10

%
%
mV

IlA
5

%

±40

IlA

-50
-140
40

dB

IJNV
pV-sec

OUT-connected to AGND, OUT-+drilling llirtual ground.
120 Hz, 600 mVp-p ripple on VEE and Vee.

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

TDCl141
Typical Performance Curves (Typical Settling Time Charactersitics)
B. Full-Scale Output Transition, Falling Edge

A. Full-Scale Output Transition, Rising Edge
- .0007

[T'T'"Tl_""'''''''-''I'''''''''''''-''''''-''-''''-''I''"''''''!I

M'T'I'TT'' ' ' ' rT'nr'TT'1' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 'T]

- .0004 ___

Conditions
Output Load: RL = 25Q
CL < 5pF
Temp: Ambient
Supply Voltages: Nominal

Conditions
Output Load: RL = 25Q
CL<5pF
Temp: Ambient
Supply Voltages: Nominal

-1.0060 _ ...........J..J...L.......l..J..J...u..L......L..i.J...L..I...L.Ju..wu...LJ...L..i.J..L.u..u.J...L..i.J"U
Ons
200ns
TIME (ns)

TIME (ns)

21596A

21597A

D. Typical Supply Current vs. Temperature

C. Typical Settling Time vs. Settling Accuracy

·160.---------------------,

no

..

~

Conditions

to.5

Output Load: RL = 25Q
CL< 5pF
Temp: Ambient
Supply Voltages: Nominal

0

en

--'

--'

·140

~

u..
0
;f!.

+.

.

..

to.l

C

Z

<'1-1'_1111_" 09
-

......~\I\.I\_--

TT4·1A

D10 (LSB)

.,.

CLK

·S.2V

For More Information call 1-1100·722·7074.

Raytheon Semiconductor

21593A

3·235

TDC1l41
Figure 8. Typical Interface Circuit with Bipolar. Differential Mode Operational Amplifier Output
LEGEND
SYMBOL

CIRCUIT

*Tu

,....----+--< ·S.2V

·S.2V

12x500HM

10H176

I----M...J\,/\I\r-..... 02
I---~...J\,/\I\r-..... 03
I----M...J\,/\I\r-..... 04
I----M...J\,/\I\r-..... 05
I----M...J\,/\I\r-..... 06

~~~

TOCl141

~

~~~~~iJr-~4J~~M~
r-~i-J\J\Ar-____ 09
r--~.J\I\IIr-"'" 010 (LSB)

ClK

·S.2V

3-236

Raytheon Semiconductor

21594A

For More Information call 1-800-722-7074.

TDCl141
Figure 9. Typical Interface Circuit with Resistive Load Output
LEGEND
SYMBOL

I

CIRCUIT

To

,...-------<'-{ ·S.2V

·S.2V

°2
°3

ANALOG OUT

°4
Os
°6

o.r

25

TOCl141

°8
°9
010 (lSB)

ClK

21595A

·S.2V

Ordering Information
Product Number

Temperature Range

TDC1141R3C
TDCl141 R3Cl

TA=O°C to 70°C
TA=O°C to 70°C

Screening
Commercial
Commercial

Package
Plastic Chip Carrier
Plastic Chip Carrier

Package Marking
1141R3C
1141R3C·l

40006718 Rev B 8193

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-237

TDCl141

3-238

Raytheon Semiconductor

For Mora Information call 1-800-722-7074.

TDC3310

TDC3310
Video D/A Converter 10-Bit, 40 Msps
Description

Features

The TDC331 0 is a very high-speed 10-bit D/A
converter especially suited for low-cost video
applications. The TDC3310 offers 10-bit resolution, TTL-compatible inputs, and requires only a
single +5 volt power supply. It has a single-ended
voltage output, SYNC and BLANKing control
inputs and an INVERT input that reverses video
levels without altering either SYNC or BLANKing.

•
•
•
•
•
•
•
•
•
•

Operating at data rates up to 40 Msps, the
TDC3310 is ideal for reconstructing composite
NTSC, PAL and RS-343A video waveforms. Data
is decoded and registered ahead of the current
switch array, resulting in outstanding low-glitch
characteristics.
The TDC331 0 is available in a 32-lead plasticJLeaded PLCC and 28-pin plastic packages and is
guaranteed from O°C to 70°C.

I

10-Bit resolution
Single +5 volt power supply operation
DC to 40 Msps, guaranteed
±1.0 LSB linearity error
TTL-compatible inputs
1 Vp-p video output
Sync and Blank controls
Video invert control
Very low glitch energy
Very low cost

Applications
•
•
•
•
•
•
•

Reconstruction of com posite video
High-resolution video
Low-cost video systems
Set-top RF converter boxes
Satellite receivers
Direct digital synthesis
Multimedia

CURRENT SWITCH ARRAY 1231

.""
.. ¥OUT

r-I--+--I-~-~I""",,""'"

LSBDATA

>-~+-I REGISTER

D9H~+-I

Dl0LSBE~~
SYNC

REGISTER

BLANK

REGISTER

331D.FBD

Figure 1. Block Diagram

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-239

TDC3310
Connection Information

i

NC

1

28 D'0 (LSBI

NC

2

V

~

G'~rI'~QMQNQ8 ~

BLANK

3

26 D8

1a=~Ie~~~~N

SYNC

4

25 D7

INVERT

5

24 D6

VREF
COMP

6
7

23 D5
22 D4

VOUT

8

21 D3

AGND

9

20 D2

VCCA 10

19 D, (MSBI

NC 11

18 CONY

DGND 12

17 VCCD

NC 13
NC 14

~I~

D8 30
D931
D,0 32

20 VCCD

1

17 DGND

2

16 NC
15 NC
14 NC

DGND
BLANK
SYNC
NC

3
4
&n co ..... co cnC_Nr")

t: It 0.

16 NC

'1!::=:::=::::::=::::!.t' 15

III

..

....

:IE ::>

ca -c:;
::; -caZ
CJZ Z

Z

> > co
co........
i!E
u>
c>

DGND

28-Pin Plastic DIP - N6 Package

19 DGND
18 NC

'"

Q

3310.A6.32P1N

32-Lead Plastic J-Leaded Chip Carrier - R6 Package

Ordering Information
Product
Number

Linearity Error
(LSB)

Temperature
Range

Screening

Package

Package
Marking

TDC331N6C
TDC3310R6C

±1.0
±1.0

TA = O°C to 70°C
TA = O°C to 70°C

Commercial
Commercial

28-pin Plastic DIP
32-Lead J-Lead PLCC

3310N6C
3310R6C

TMC1175E1C

30

TA = O°C to 70°C

Commercial

Eurocard PC Board

TMC1175E1C

mance D/A converter.

Functional Description
The TDC331 0 consists offive major circuit sections: the data and control registers, the MSB
decode block, the MSB current switch array, the
binary weighted LSB array and the reference
amplifier. All inputs are registered just before the
current switch array to minimize the temporal
skew that generates glitches.
The TDC331 0 uses an architectures that combines
segmentation and binary weighted techniques.
With the four MSBs segmented into 15 equal-value
current switches, and the six LSBs using binary
weighting, an optimal trade-off between glitch
performance and die size (cost to the user) is
made. The result is a very low cost, high perfor-

3-240

Power and Ground
The TDC3310 requires a single +5.0 volt power
supply. The analog (VCCA) and digital (VCCD)
power supply voltages should be separately
decoupled, as shown in the Typical Interface
Circuits, to reduce power supply induced noise.
0.1 /!F decoupling capacitors should be placed as
close as possible to the TDC3310 power pins.
Ferrite beads are neither critical in value nor
always required.
The high slew rate of digital data make capacitive
coupling to the outputs of any D/A converter a
potential problem. Since the digital signals contain high frequency harmonics of the CONv\

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDC3310
signal, as well as the video output signal, the
result of data feedthrough often looks like harmonic distortion or reduced signal-to-noise
performance Separate analog and digital grounds
are provided on the TDC3310, but all ground pins
should be connected to a common solid ground
plane for best performance.

VREF
The TDC3310 is designed to operate with a voltage reference referred to VCCA (a 1V difference
between VREF and VCCA). The TDC3310 uses this
voltage differential to generate an internal reference current for the current switch array. Since
the DC voltage provided to VREF must be referred
to VCCA (and not AGNO), the output voltage of the
D/A converter is referred to VCCA (and not to
AGNO). This allows the gain of the TDC3310 to be
immune from variations of VCCA. VREF should be
decoupled to VCCA.
The internal reference amplifier has a highimpedance input and is externally frequencycompensated to ensure stability. A 0.1 J.LF capacitor should be connected between the COMP pin
and AGNO. The Typical Interface Circuits include
an adjustable reference circuit.

Data Inputs 0,.,0
The data inputs are TTL-compatible. For applications involving fewer than 10 bits, connectthe
unused LSBs to DGNO.

CONv\
The TDC331 0 requires a TTL-compatible clock
signal, CONV\. All inputs are registered on and the
analog output changes teo after the falling edge
of CON V\.

SYNC and BLANK

of the TDC3310 during CRT retrace intervals.
When BLANK is HIGH, data to D1-10 is ignored
and VOUT is forced to a fixed blanking level,
nominally 81 mV below the video "black" level.
When SYNC is HIGH, data to D1-10 and BLANK
are ignored and VOUT is forced to a fixed sync
level, nominally 433 mV below the level corresponding to BLANK. SYNC and BLANK are registered within the TDC3310 on the falling edge of
CONV\.

INVERT
INVERT controls the polarity of D1-10 without
affecting the SYNC or BLANK inputs. This input
functions as a system data format selector, allowing the reversal of black and white in a video
image. See the Input Coding Table. INVERT is
registered within the TDC3310 on the falling edge
of CON V\.

VotJr
The voltage output of the TDC3310 is referred to
VCCA and varies from VCCA to VCCA - VREF- The
VOUT terminal of the TDC3310 has an internal
90a resistor to provide a voltage output from the
current switch array. The close thermal coupling
and matched temperature coefficients of the
internal reference current generator and this
VOUT load resistor provide an output that is stable
over temperature. Operation with an external load
resistor will reduce output voltage range as well
as temperature stability. Current may be driven
into or out of the VOUT terminal as long as the
output compliance voltage limit of the TDC3310 is
not violated.

Not Connected
There are several pins with no internal connection
to the TDC3310. They should be left open.

SYNC and BLANK inputs control the output level

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-241

TDC3310
Table 1. Package Interconnections
Signal Type

Name

Function

Value

N6Pin

Power

VCCA
VCCD

Ground

Data Input

AGND
DGND
VREF
COMP
D, (MSB)

Analog supply voltage
Digital supply voltage
Analog ground
Digital ground
Reference voltage input
Compensation capacitor
Most Significant Bit Input

Clock
Output
Not Used

D2
D3
D4
D5
D6
D7
Ds
D9
D,o (LSB)
INVERT
SYNC
BLANK
CONv\
VnlIT
NC

Least Significant Bit Input
Invert D1-D10
SYNC input
BLANK input
Clock input
Analog output
Not connected

5.0V
5.0V
O.OV
O.OV
VccA-1
0.1 IlF
TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL
TIL
+4 to +5
Open

10
17
9
12,15
6
7
19
20
21
22
23
24
25
26
27
28
5
4
3
18
8
1,2, 11
13, 14, 16

Reference

I

f--------WHITE

Vec+-----------""\ VOLTS

~I~E:

R6Pin
10
20
9
1, 13, 17, 19
6
7
23
24
25
26
27
28
29
30
31
32
5
3
2
22
8
4, 11, 12, 14
I 15, 16, 18,21

-

1024 "GRAY - SCALE" lEVELS

1_____ .!LA~K

__ _
BLANK

Vee -1.0
vee -1.081

-- -

Vee -1.514

- - - - - - - - - - - - - - - - _'--_ _ _.1-

-

- - - -- -

- - -'-----...

3310.1

Figure 3. Video Output Waveforms

3-242

Raytheon Semiconductor

For More Information call 1-800-722·7074.

TDC3310
Table 2. Input Coding Table

=

=

w/r~ND

INVERT HIGH
V OUT
w/rVCCA

w/r~ND

0.000
-0.001
-0.002

5.000
4.999
4.998

-1.000
-0.999
-0.998

4.000
4.001
4.002

0
0

-0.500
-0.501

4.500
4.499

-0.501
-0.500

4.499
4.500

0
0
0

0
0
0

-0.998
-0.999
-1.000

4.002
4.001
4.000

-0.002
-0.001
0.000

4.998
4.999
5.000

1

0

,

-1.081
-1.514

3.919
3.486

-1.081
-1.514

3.919
3.486

SYNC

INVERT LOW
V OUT
w/rVCCA

0
0
0

0
0
0

1000000000
0111111111

0
0

0000000010
0000000001
0000000000

xxxxxx xxxx
xxxxxx xxxx

x

D1 ......... D10
(MSB LSB)

BLANK

1111111111
1111111110
1111111101

V OUT

V OUT

Note: VREF = VCCA - 1.000 volts, VCCA = 5.0 volts, no external

t
t
±1/2lSB

10%

i
t

VOUT ------~-..:::;('----~

teo

3310.2

Figure 4. Timing Diagram

For More Information call HIOO-722·7074.

Raytheon Semiconductor

3·243

TDC3310
r------4-_-...;..;...:.-+-o VOUT

3310.3

Figure 5. Equivalent Reference and Output Circuit

----1-.

VOUT a-.....

39 F

vee TO vee -1 VOLT

VECTORSCOPE

r

- - - ;"sv;;'i

I
L.

I
I
_ _ _ _ _ ... 3310.5

~:.=rFf
ps
0.1

3310.4

Figure 6. Output Test Load

3-244

Figure 7. Output Load for DP and DG

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDC3310
Absolute Maximum Ratings 1
Supply Voltages
VCCA (measured to AGNO) .............................................................................................. -0.5 to +7.0V
VCCO (measured to DGNO) .............................................................................................. -0.5 to +7.0V
VCCA (measured to VCCO) ............................................................................................... -0.5 to +0.5V
AGNO (measured to DGNO) .............................................................................................. -0.5 to +0.5V
Inputs
CONV\ D1-10, SYNC, BLANK, INVERT .................................................................................................
Applied voltage measured to DGN0 2 ........................................................................ -0.5 to +7.0V
Externally forced current 3 ................................................................................................ ±10 mA

VREF
Applied voltage (measured to AGNO) 2 ............................................................ -0.5 to (VCCA +2)V
Externally forced current 3 ................................................................................................ ±10 mA
Output
VOUT
Applied voltage (measured to AGNO) 2 .................................................................... +3.0 to +7.0V
Externally forced current 3 ................................................................................................±20 mA
Temperature
R6 Package
Operating, ambient ..................................................................................................... -25 to +90°C
Junction ..............................................................................................................................+140°C
B6 Package
Operating, ambient ................................................................................................... -60 to + 150°C
Junction ..............................................................................................................................+200°C
Lead, soldering (10 sec.) ...........................................................................................................+300°C
Storage ...........................................................................................................................-65 to + 150°C
Notes:
1. Absolute maximum ratings are limiting values applied to individually while all other parameters are within specified
operating conditions. Functional operation under any ofthese conditions is NOT implied. Oevice performance and reliability are guaranteed only if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.

For More Infonnation call 1-800-722-7074.

Raytheon Semiconductor

3-245

I

TDC3310
Operating Conditions
Parameter

Description

Standard Temperature Range
Max
Nom
Min

VCCA
VDDC

Analog Power Supply Voltage

4.75

5.00

5.25

V

Digital Power Supply Voltage

4.75

5.00

5.25

V

VCCA-VCCD

Power Supply Voltage Differential
Ground Voltage Differential

-0.1
-0.1

0.0
0.0

0.1

V

0.1

V

VCCA -1.5
0.01

VCCA -1.0
0.1

VCCA -0.5

V

0.8

IlF
V
V

AGND-DGND
VREF

Reference Voltage

Units

Cc
VIL

Compensation Capacitor

VIH

Input Voltage, Logic HIGH

2.0

ts

Input Data Setup lime

20

ns

tH

Input Data Hold lime

2

ns
ns

Input Voltage, Logic LOW

tPWL

CONv\ Pulse Width, LOW

10

tPWH

CONv\ Pulse Width, HIGH

10

TA

Temperature Range, Still Air

0

ns
70

°C

Electrical Characteristics
Parameter
Supply current
ICC

Conditions

CIN

Input Capacitance

VCCD = VCCA = Max
CONY\, D1-10, SYNC,

IlL

Input Current, Logic LOW

IIH

Standard Temperature Range
Typ
Max
Min
70
115

Units
mA

5

10

pF

VCCD = Max. VI = OAV

-200

-400

Input Current. Logic HIGH

VDDC = Max, VI= 2.4V

10

100

RO

Output Resistance

VOUT to VCCA. TA =+25°C

90

100

r.tA
r.tA
n

Co

Output Capacitance

VOUT Terminal

20

pF

VOC

Output Compliance

Referred to VCCA

-1.5

0

+004

VFS

Full-Scale Output

Referred to VCCA. VREF = Nom

-0.95

-1.0

-1.05

Vl
V

VBLANK

Blank Output Voltage

Referred to VFS. VREF = Nom

-71

-81

-91

mV

VSYNC

Sync Output Voltage

Referred to VBLANK. VREF = Nom

-380

-433

-480

mV

BLANK. INVERT, VREF

3-246

Raytheon Semiconductor

80

For More Information call 1-800-722-7074.

TDC3310
Switching Characteristics
Parameter

Conditions

Maximum Clock Rate
Clock to Output Delay1, 2
Output Risetime 1, 2

VCCA' Vcco = Min
V CCA' V DOC = Min
90% to 10% of Full Scale

tF

Output Falltime 1,2

10 to 90% of Full Scale

tSET

Output Settling lime 1, 2 , ;;l

fS
tco
tR

GA

Standard Temperature Ran ~e
Typ
Max
Min
Units
MHz

40
15

8

ns

5

10

ns

10

ns

to 1%

5
10

18

ns

to±1LSB

25

40

Peak Glitch Area 2, 3

ns
pV-see

50

Notes:
1. See Timing Diagram.
2. Standard Test Load, Figure 4.
3. Worst-case transition.

System Performance Characteristics
Standard Temperature Range
Typ

Max

Units

ELO

Differential Linearity Error

V CCA' VCCD' VREF = Nom

±0.5

±1.0

LSB

ELI

Integral Linearity Error

VCCA' Vcco, VREF = Nom

±0.5

±1.0

LSB

EG

Absolute Gain Error

VC CD' VCCA' V REF = Nom

±1

±5

V CCD' VCCA' VREF = Nom
V CCA' VCCD = Max, D 1-10 = HI pH
VCCA' Vcco, = Max, D1-10 = H GH

±30

Parameter

TCEG Gain Error Tempeo
V OF
Output Offset Voltage
TCO F Offset Tempeo
IREF
Dp

V REF Input Bias Current

DG

Differential Gain

Differential Phase

For More Information call 1-800-722-7074.

Conditions

Min

-10

= 4 x NTSC Subcarrier
fS = 4 x NTSC Subearrier
fS

Raytheon Semiconductor

-25

-50
1

%
ppm/"C
mV
IlV/"C

5

I!A

0.2

Degrees

0.3

%

3-247

I

TDC3310
+w>---------------~--~

D.1

D.1

3.9IC

IK

>-_-+IYP-P
VIDEO our
01_10

0 1 _ 10

SYNC

SYNC

BlANK

BlANK

fliNY

CONY
3310.&

Application Notes

Printed Circuit Board Layout

Since the internal reference and output circuits of
the TDC331 0 are referred to the power supply, Vee,
the external voltage reference shown in the Typical
Interface Circuit is also referred to Vee. A simple 1.2
volt Bandgap reference diode is voltage-divided to
provide 1.0 volts between the VREF and Vee inputs. The output of the TDC3310 is AC coupled into
a 75n resistor which divides the output video level
by a factor of two. The video amplifier gain is +2,
restoring the 1 Vp-p video level and referring the
video signal to AGNO. It is important to ensure the
power supply for the TDC331 0 is well-regulated
and free of high-frequency noise. Careful power
supply decoupling will ensure the highest quality
video signals at the output of the circuit.

Designing with high-performance mixed-signal
circuits demands printed circuits with ground
planes. Wire-wrap is not an option - even for
breadboarding. Overall system performance is
strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may
result in poor NO conversion. Consider the following suggestions when doing the layout:

Grounding
The TDC3310 has separate analog and digital
circuits. To keep digital system noise from the D/A
converter, it is recommended that power supply
voltages (VOOO and VOOA) come from the same
source and ground connections (DGND and AGNO)
be made to the analog ground plane. Power supply
pins should be individually decoupled at the pin.

1. Keep the critical analog traces (VIN, RT, RB,
VR ... VR-) as short as possible and as far as
possible away from all digital signals. The
TMC1173 should be located near the board
edge, close to the analog output connectors.
2. The power plane for the TMC1173 should be
separate from that which supplies the rest of
the digital circuitry. A single power plane
should be used for all of the VOO pins. If the
power supply for the TMC1173 is the same as
that of the system's digital circuitry, power to
the TMC1173 should be decoupled with ferrite
beads and 0.1 ~F capacitors to reduce noise.
3. The ground plane should be solid, not crosshatched. Connections to the ground plane
should have very short leads.

The digital circuitry that gets its input from the
TMC1173 should be referred on the system digital
ground plane.

3-248

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TDC3310
4. Decoupling capacitors should be applied
liberally to Voo pins. Remember that not all
power supply pins are created equal. They
typically supply adjacent circuitry on the
device, which generate varying amounts of
noise. For best results, use O.1I1F ceramic
capacitors. lead lengths should be minimized.
Ceramic chip capacitors are the best choice.

5. If the digital power supply has a dedicated
power plane layer, it should not overlap the
TMC1173, the voltage reference or the analog
inputs. Capacitive coupling of digital power
supply noise from this layer to the TMC1173
and its related analog circuitry can have an
adverse effect on performance.
6. CONY should be handled carefully. Jitter and
noise on this clock may degrade performance.
Terminate the clock line carefully to eliminate
overshoot and ringing.

Typical Performance Curves
80

105
100

70

95

'CC(mAI

ICC (mAl 90

60

85

80

75

50
'-:=----::-=-----:-:!::-7.=:::--' 33lO.A

'-:=--~:-=-----:-:!::-7.=:::--' 3310.8

Power Supply Current vs. Temperature

ROUT

vs. Temperature

4OG06946 Rev 0 &'93

For More Information call 1-800·722·7074.

Raytheon Semiconductor

3·249

TDC3310

3-250

Raytheon Semiconductor

For More Information call 1-800-722-7074.

Section 3 - Standard Products

Transform Products

65-6225

Transform products perform complex conversions from
one signal space to another. The high level of integration
in Raytheon products yields very efficient, cost-effective
implementations of the basic signal processing function.

The Fast Cosine Transform is the key functional element
in image compression. The TMC2311 operates on 12 bit
data at a 15 Mega PixeVs rate.
The TMC2330 is tailored to convert data in polar
coordinate space to rectangular space, or vice-versa, at
rates of 25 million operations per second.

The Fast Fourier Transform is a basic tool in time!
frequency domain processing. The TMC2310 executes a
1K point, 16 bit FFT in 514 J.lS (16 points in 4 J.1S).

Product
TMC2310-1

TMC2311-2
-1
TMC2330-1

Clock
Rate1
Description
(MHz)
Size
Fast Fourier Transform
16-Bit
20
20
15
Fast Cosine Transform
12-Bit
17.8
14.5
17.8
Coordinate Transform 16x16 Bit 25
20

Power1
(Watts)
0.75
0.75
0.75
0.7
0.7
0.7
0.7
0.7

Package
G5, L4, L6
H7
G5, L4, L6
R1
R1
Rl
H5, L5
H5, L5

Grade
V
V
C
C
C
V,C
V,C

Notes
1024 point complex FFT in 514 ~ with 1S-bit
internal precision and block floating-point
rescaling.
Data compression processor.
Meets cClrr specifications
8x8, 2-<1imension.
Cartesian H polar converter.

Notes:
1. Guaranteed. See product specifications for test conditions.
2. A = High Reliability, Te .. -55"C to 125"C.
C .. Commercial, TA - O"C to 70"C.
V .. MIL-5TD-883 compliant, Te .. -55"C to 125"C.
SMD .. Available per Standardized Military Drawing. Te .. -55"C to 125"C
For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-251

TMC2310

3-252

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2310
TMC2310
FFT Processor
16119-Bit, 20 MHz

Description

Features

The TMC231 0 is an advanced integrated circuit which
can execute co~lex Fast Fourier Transforms (FR),
forward or inverse, of up to 1024 points, with or without
data windowing. The device operates with either
unconditional or conditional overflow block floating-point
rescaling. Adaptive and static Finite Impulse Response
filtering, real and co~lex multiplication or multiplyaccumulation, and magnitude squared operations are
also supported. Sinusoidal coefficients ('Roots of Unity')
for Fourier Transforms are provided in a CoeffICient
Look-Up Table in on-chip ROM. At the maximum clock
rate of 20 MHz, the device will execute radix-2 butterflies
in 100 ns, and 1024-point complex transforms (5120
butterflies) in 514 ~ec.

•

The TMC231 0 provides the arithmetic, control,
coeffICient memory and address generation logic for a
variety of signal processing and vector algorithms.
External memory is used for storage of complex data
and window or filter coefficients. Each data port is
bidirectional and the device can be used with one or two
banks or memory for either in-place or bank switched
memory configurations, allowing the user to overlap VO
operations with arithmetic execution. All functions utilize
the same basic system architecture, ensuring maximum
flexibility.
The control structure has been designed to simplify its
use as a high-speed arithmetic accelerator. The device
is programmed by initializing two internal configuration
registers to set device parameters such as function,
transform length, data addressing modes, single or bank
switching memory architecture, and other options. Once
initialized, the device generates data addresses and
control for extemal memory, transfers data, executes the
algorithm, and provides a DONE flag to indicate
completion.

•
•
•
•
•
•
•
•
•

Stand alone execution of forward or inverse
complex Fast Fourier Transforms, adaptive and
non-adaptive FIR filtering, multiplication or
multiplication-accumulation (real or complex)
magnitude squared
Fast 100 ns per butterfly yields a 2 MHz to 4 MHz
sampling rate in single-device systems (16-point
FFT in 4 ~ec, 1024-point in 514~)
Pipelined addressing mode and internal data
storage to reduce memory bandwidth
Multiple-transform array mode to increase
throughput
On-chip ROM coefficient look-Up table for FFT
coefficients ("Twiddle Factors")
16-bit fixed-point data format with 19-bit
intermediate and final results for improved precision
Conditional overflow rescaling or manual scaling
(block floating-point) for high signal-to-noise
performance
Scaler (block exponent) output
User-programmable window functions
Complete on-chip address generation and control
for off-chip data and window/(FIR) coefficient
memory

Logic Symbol

HOST
INTERFACE

SCEN

vO

_

1,11111.1

CMD 1·0)-"::';--'"
DONE

Built with Raytheon Semiconductor's OMICRON-CTM
CMOS process, the TMC231 0 is available in 89-pin
plastic and 88-pin ceramic pin grid arrays and a 100
leaded ceramic chip carrier.

For More Information call 1-800-722-7074.

)--_.. 0 0

ClK

Raytheon Semiconductor

IRAMSEl

ADg• O

v
MEMORY CONTROL INTERFACE

3-253

TMC2310
Applications
•
•
•
•
•
•
•

•
•
•
•
•
•

Radar
Sonar
Digital Communications
High - Speed Modems
Image Processing, Graphics
Test Instrumentation
Medical Electronics

Spectral Decomposition/Analysis
Frequency- Multiplex Demodulation
Adaptive Filtering And Equalization
Pulse And Image Compression
Frequency And Time Domain Digital Filtering
High - Speed Complex Multiplication

Functional Block Diagram
WINDOWIFllTER
COEFFICIENT
PORT 1WI6-0)

Voo

)>------••

GNO

)>------+.

REAL
110 PORT
IREI8_0)

'-------
The W-Bus is used to input the 17-bit
window and FIR Filter coefficients. W5-0 is
also used as an output to access the block
exponent and last pass overflow.

For More Information call 1-800-722-7074.

TMC2310
Data Buses (cont.)
W16-0

The scaler exponent (W3-0) indicates the
number of shifts performed on the data for
multiple pass transforms while WS-4
indicates the overflow (in bits) that occurred
during the previous pass. WS-4 indicates
how many, if any, of the three MSBs (RE1816, 1M 18-16) of the final results contain
significant data (i.e. bits which are not an
extension of the sign). If the largest
magnitude result mantissa of a pass falls
between -32,768 and +32,767, inclusive,
W5-4 following that pass will be O. If,
instead, it falls between -65,536 and 32,769, inclusive, or between +32,768 and
+65,535, inclusive, WS-4 will be a 1,
denoting 1 bit of net word growth to be
compensated at the start of the next pass
by a rig ht shift.

Control Inputs
CMD1-0

The manifold functions of the TMC231 0
FFT processor are selected by the
Information loaded into its Configuration
Registers, CR1 and CR2. The loading of
these registers is controlled by the CMD1-0
input pins and the clock. The TMC231 0
must be RESET and both Command
Registers loaded before the first operation
(FFT or other transformation) begins. The
TMC2310 RESETs automatically after each
complete transform, and then CR1 and/or
CR2 may be updated for a different
operation. If neither CR1 nor CR2 is
updated, the previous operation will be
repeated on the next data set.
Each register value may be loaded in a
separate LOAD sequence, or both values
may be loaded sequentially in the same
LOAD sequence. CR1 and CR2 may be
loaded in any order because bit 15 is an
identification bit. The values for CR1 and
CR2 may be presented to pins RE1S-3 from
any source. A clever source for one of
these values is memory location 0, which is
called by the TMC231 0 during the LOAD
operation.

For More Information call

1-800-722-7074.

The LOAD command is given by the first
clock rising edge at least Is after setting
CMD1-0 ",01. The Command Register value
is read by the TMC2310 at its RE15-3 pins
on the third (and fourth, for sequential
loading) rising clock edge after the LOAD
command. CMD1-0 must be held at 01
during the entire LOAD sequence. As long
as CMD1-0 is held at 01, the TMC231 0
command registers track the RE1S-3 inputs.
See the timing diagram 7 and 8 for further
information.
Here are the step-by-step instructions:
For the first operation after applying power,
the TMC231 0 must be RESET. (This step
is not required for subsequent operations.)
1. Set CM 01-0",00 for at least 4 clock
rising edges. (DONE, WR\and
RAMSEL will go HIGH.)
Load the Configuration Registers by
entering a LOAD command and presenting
the values for CR1 and/or CR2 to the
TMC2310.
2. Set CMD1-O",01 at least Is before a
clock rising edge, which we'll label ·0."
3. Present the data for CR1 or CR2 to the
RE1S-3 pins at least Is before clock
rising edge 3.
4. To load the selected operation, set
CMD1-0 ",11 to enter the CONTINUE
mode, during which the TMC231 0 waits
for a start command. The START
command is given by setting
CMD1-0 ",10 at least Is before a clock
rising edge. For proper operation
CMD1-0 must be set to 11
(CONTINUE) within 4 clock cycles after
to START command. The selected
operation is performed to completion.
The registered CoMmanD input is used to
RESET the device, LOAD configuration
registers, and START an operation.
Commands are issued by placing a valid
command on the input for one (or more)
clock cycle(s) then returning to the CONT
command. The input should normally
remain in the inactive (CONT) state. The
operation of each command is as follows:

Raytheon Semiconductor

3-259

I

TMC2310
CMD1.Q
00

Command ·Operallon
RESET
If RESET Is held for alleast 4 clock cycles,
the DONE llag, WR, RAMSEL are set
HIGH. The address bus (AD9-0), data
buses RE1s-o.1Mul.o and W16-0 are set to
hlgh-impedance stale, and the RD output is
LOW. A RESET command held for only
one cycle does not reset the chip, but
causes the last pass scaler (W5-4) to be
added to the current scaler exponent (W~
0). The sum then appears on Ws-n until
cleared. RESET held for more than one
cycle will clear the scaler exponent field
(Ws-n).

01

LOAD

AD9-0 is activated and a read is performed
with the address set to zero. If LOAD is
foDowed by a CONT then the device wiD be
put into a RESET state.

10

START

START causes the device to begin an
operation. The START command must be
valid for at least one clock cycle, but not
longer than 4 clock cycles. After two startup cycles, the DONE flag is set LOW and
the data and addresses buses become
active. Upon completion of the operation,
WR, and DONE are HIGH, RD is LOW,
AD9-0, RE18-0 and IM1S-o are In highImpedance, and execution suspended until
the next command. The state of the
RAMSEL pin depends on the mode
determined in Configuration Register 2.
The START command clears the current
contents of the scaler exponent (W~).

11

SCEN

3-260

CONT

CONTInue is the inactive state for the
command Input It has no Internal effect
After a command has been issued, the
CMD Input should be set to this state.
following a start, the CMD input must be
set to CONT for the operation to complete
properly. If the previous command was a
RESET or LOAD then the device remains
In RESET.

(rescaled) intemally by a common powerof-two scale factor. By bringing SCEN
HIGH, the user can read the base-2
logarithm of this scale factor, "A; over
W3-o. The unsigned binary value "A" tells
how much rescaling, i.e., how many onebinary-place right shifts, occurred
cumulatively during all but the first radix-4
pass of the transform.
In general, the largest output word will have
grown past the nominal 16-bit input format
(the LSBs of the data VO ports), into bits
018, 017, and 016. While reading "An over
W3-0, the user can also read ·C,· which
tells how much word growth occurred
during the final pass, on W5-4. If C=-.. . .______________________
I

RAMSEL 10
RAMSEL II

c:=x:::x:=x:=::

I

I

<>-.. . _______________________

I

RIi

I

WR
SCALER EN

Complex Multiply Control and Address Timing Diagram
ADO _ 9

ADA-.

ADA-.

I

I

REO-IS
WBUSO_16
DONE

I

~,-----------------------------------------

I

I

I

I

RAMSELOO C-.. . ._______________________

RAMSEL 10

-.. . ._____________--.J

RAMSEL 11

I

jffil

I

u

WR

u

SCALER EN

FIR Dual Real Control and Address Timing Diagram
ADO _ 9
REO_IS

ADA-.
CA1

ADA-.
CA2

I

I

I

WBUSO_16

-----------:-1------:---<

DONE
RAMSEL XO

-~

I
I

RDl

I

~,-------------------------------------------I

_____________________

I

u

WR

u

SCALER EN

3-282

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2310

I

----------~---~

L -_ _ _ _ _ _ _ _ _ _~r___

LL-

__________~~~rl~-------AOR"'N-1

~
~

I
I

=>CYXXXXXXXXXXXXXX>~---------RE (N-2)

RE (N-1)

~--------------~------------

----------------------~-----~

~~------------------L-J
J

u

~~------------~-----------U

____________________________~~rl~-------ADA=N-1

I

~~----RE (N·2)

SUM (0)

I

~~--------------~------------

L-J

J

u
For More Information call 1-800·722·7074.

----~~~----------------~------------­
~--------------~-----------U

Raytheon Semiconductor

3·283

TMC2310
Figure 12. TMC2310 Overall Timing Diagram

Pipelined Addressing Relative Clock and CMD(O-l) Timing Diagram

CLOCK
CMOo
CMOI

!=xxxxxx=x=

FFT/IFFT Control and Address Timing Diagram
AD O_ 9
~
RE O- 18

--------~

I

c:>c:::::>c:::)

WBUSO_16
DONE

!~-----------------------------------------

I

RAMSEL 00

CXXJCX7'<~~~XX~7'C<~~X..,..X'""'yr------------------------------------------

RAMSEL 01

CC-----'i----~("5('X'~O).>(,x..~~X:-'AA",m;;DR~,/'",/'V,.'ADR~2

ADD _ 9
RED -18

CR'

CR2

WBUSO_16
DONE

I

RE 11

I

WI(4J

I

~I- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

RAMSEL 00

C--------------RE (N-2)

RE (N-1)

~

~~--------~------------

~

--------------------~------c=J_

~~------------------~
~
~L____________~-----------

-----u

U

________________________

~--~rl~----

I

ADR=N-1

~>-----------

~

~~
~~
I
~----------~----------

~

L-J

____~r--lL__________________~-------------~L__ _ _ _ _ _ _ _ _ _ _ _~----------

-----u
For More Information call 1-800-722-7074.

u

Raytheon Semiconductor

3-285

I

TMC2310
Figure 13. Equivalent Input Circuit

Figure 14. Equivalent Output Circuit

voo

voo
n SUBSTRATE

n SUBSTRATE

01

01
p+

p+

CONTROL o---'Wv-~~"
INPUT
lKO

....-~~-o OUTPUT
n+

02

02
P WELL

P WELL
.,. GNO

Absolute maximum ratings (beyond which the device may be damaged) 1
. ... -0.5 to + 7.0V

Supply Voltage ............ .

- 0.5 to IVoo + 0.5)V

Input Voltage
Output

- 0.5 to IVoo + O.5)V
. . . . . . . . . . .. - 3.0 to 6.0mA

Applied voltage 2 ................ . .......... .
Forced current 3,4 .....
. ........... .

1 sec

Short - circuit duration Isingle output in HIGH state to ground)
Temperature

- 60 to + 130°C
+ 175°C
..... 300°C
- 65 to + 150°C

Operating, case ..
junction
Lead, soldering
Storage .

110

seconds)

Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.

3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

3-286

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TMC2310
Operating conditions
Temperature Range
Standard
Parameter

Min

Nom

4.75

5.0

Extended
Max

Min

-1
Nom

Max

Min

Nom

Max

Units

VOO

Supply Voltage

tCY

Clock Cycle Time

50

50

66

ns

tpWH Clock Pulse Width HIGH
tpWL Clock Pulse Width LOW

25
20

25
20

30
25

ns
ns

7
1

9
2

11

ns
ns

ts
tH

Input Setup Time
Input Hold Time

VIL
VIH
VIHC

Input Voltage, Logic LOW
Input Voltage, Logic HIGH
Input Voltage, Clock HIGH

IOL
IOH

Output Current, Logic LOW
Output Current, Logic HIGH

TA
TC

Ambient Temperature, Still Air
Case Temperature

4.5

5.25

5.0

5.5

2

0.8

0.8

2.0

2.0
2.3

2.2
4.0
-2.0
0

4.0
-2.0

70
-55

V

V
V
V
rnA
rnA
°c
°C

125

DC characteristics within specified operating conditions 1
Temperature Range
Parameter

Test Conditions

IOOQ Supply Current, Quiescent
IOOU Supply Current, Unloaded
IlL

Input Current, Logic LOW

VOO=Max, VIN=OV

Input Current. Logic HIGH

VOO=Max, VIN=VOO

VOL
VOH

Output Voltage, Logic LOW
Output Voltage, Logic HIGH

VOO=Min, IOL =4mA
VOO=Min,IOH=-2mA

IOZL Hi-Z Output Leakage Current, Output LOW
IOZH Hi-Z Output Leakage Current, Output HIGH
lOS Short-Circuit Output Current
IOSW Short-Circuit Output Current for WR

Note:

Input Capacitance
Output Capacitance

VOO=Max, VIN=OV
VOO=Max, VIN=VOO
VOO = Max, Output HIGH, one pin
to ground, one second duration max.
VOO=Max, Output HIGH, one pin
to ground, one second duration max.
TA=25°C, f=lMHz
TA=25°C, f=lMHz

Extended
Min Max

5
150

VOO=Max, VIN=OV, OONE=HIGH
VOO = Max, f=20MHz

IIH

CI
Co

Standard
Min Max

-10
10

10
160

rnA
rnA

-10

/LA
/LA

10

0.4
2.4

Units

0.4
2.4

V
V

-20
20
-180

20
-180

/LA
/LA
rnA

-180

-180

rnA

10

10
10

10

-20

pF
pF

1. Actual test conditions may vary from those shown. but guarantee operation as speCified.

For Mora Information call 1-800-722-7074.

Raytheon Semiconductor

3-287

I

TMC2310
Switching characteristics within specified operating conditions 1
Temperature Range
Standard
Parameter
to

Delay Clock to Output

Test Conditions

Min

Scaler (W5-0)
Output Hold Time

19
18
15
32

20
18
16
38

25
20
18
40

Units
ns
ns
ns
ns

VDD = Min. Load = 25pF
RE18-0. IM18-0
AD9-0. RAMSEL
RD. DONE
Scaler (W5-0)

4
4
2
5

2
2
2
5

ns
ns
ns
ns

Setup Time AD9-0 to WR LOW
Hold Time AD9-0 to WR HIGH
Setup Time Data to WR HIGH
(Data Valid to end of WR)
Hold Time Data to WR HIGH
(Data Hold from end of WR)

VOD = Min. Load = 25pF
VDO = Min. Load = 25pF
VDD = Min. Load = 25pF

0
10
24

0
5
22

ns
ns
ns

VDD = Min. Load = 25pF

10

10

ns

tPWR

WR Pulse Width LOW

VDO = Min. Load = 25pF

15

14

ns

tOWL
tOWH

Oelay. Clock HIGH to WR LOW
Delay. Clock LOW to WR HIGH

VDD = Min. Load = 25pF
VDD = Min. Load = 25pF

11

tENA
tOIS

Three-State Enable Oelay
Three-State Disable Delay

VOD = Min. Load = 25pF
VDD = Min. Load = 25pF

tSA
tHA
tso
tHD

Note:

3-288

Max

Voo=Min. Load=25pF
RE18-0. IM18-0
AD9-0. RAMSEL
RD. DDNE

tHO

Max

Extended
-1
Min Max
Min

7

25
18
20
14

10

28
22

ns
ns

21
16

ns
ns

1. All transitions are measured at a 1.5V level except for tOIS and tENA

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2310
Table 7. Performance Benchmarks
Number Execution 1 Execution Cycles
Execution
Execution Time (20MHz)
(Multiple Transform Mode) Time (20MHz) (Multiple Transform)
of Points Cycles

Operation
FFTlIFFT
(Real Window/No Windowi

641T ransform + 23

4.35,"S

3.2 ,"SlTransform + 1.25 ,"S

11.15,"S
20.75,"S
53.15,"S
104.35,"S

9.6 ,"SIT ransform + 1.55 ,"S
19.2 ,"SlTransform + 1.55 ,"S
51.2 ,"SIT ransform + 1.95 ,"S
102.4 ,"SlTransform + 1.95 ,"S

5120/T ransform + 47
N/A

258.35,"S
514.35,"S

256.0 ,"SIT ransform + 2.35 ,"S
N/A

415
1063
2087
5167
10,287

16
32
64
128

132

96/T ransform + 36

300
556
1332

256/T ransform + 44
512/T ransform + 44
1280/Transform + 52

FFT/IFFT
(w/Complex Multiplyi

87
223

192ITransform + 31
384ITransform + 31
1024/T ransform + 39
2048/T ransform + 39

16
32
64
128
256
512
1024

6.6,"S
15.0,"S
27.8,"S
66.6,"S

4.8 ,"SlTransform + 1.8 ,"S
12.8 ,"SlTransform + 2.2 ,"S
25.6 ,"SlTransform + 2.2 ,"S
64.0 ,"S/Transform + 2.6 ,"S

FIR Filtering

-

2 Cycles/Poinl+ 9

1OOns/Point + 450ns

Multiplication
Multiply - Accumulate
Magnitude Squared

-

2 Cycles/Poinl+ 15

1OOns/Poinl+ 750ns

Note:

1. Execution times are valid for all ffT addressing and scaling modes.
Execution time is defined as the number of clocks from CMO~START until OONE~HIGH Isee belowl.
The number of clock cycles is obtained in the following manner:
Clock Cycles ~ INum. of Passes) • 12. Total Num. of Points) + INum. of Passes) • 8+ 7
~ 12. Total Num of Butterflies) + IProcessing Overhead).

Figure 15. Execution Cycle Time

r--

ClK

CMO

EXECUTION TIME

~JLJLr
L/~

DONE

Note:

-I

1. for multiple transforms. the total time can be obtained by multiplying the value in the table by the number of concurrent transforms.
Example: 15 transforms of length 54 - points:
from Table 7.: 384 clocks per transform + 31 cycles overhead.
Therefore. the total number of cycles is:
Total

~

1384/transform)·115 transforms) + 31

For More Information call 1-800-722-7074.

~

6175 cycles.

Raytheon Semiconductor

3-289

I

TMC23.10
Applications
Data Formats

utilize manual scaling. During multiple pass
transforms, shifting can also be performed
automatically (except for the first pass) by selecting
the auto scale feature. If an operation may cause an
overflow, sufficient memory width must be provided
or data shifting performed to prevent loss of
significant data. However, certain operation never
cause overflow. For example, multiplication of two
inputs which are both less than 1.0 will produce a
result of less than 1.0. Since the MSBs of the output
will always be a sign extension of the result, they
can be ignored. This can simplify the memory
arrangement by allowing the use of 16-bit memory
systems (see Interfacing to Memory).

The input and output data formats are shown in
Figure 16. Data are output on the RE and 1M buses
using the two's complement 19-bit data format.
Input data must conform to the specified 16-bit data
format detailed in Figure 16. During the first pass of
any operation data input on the RE and 1M buses
may require scaling in order to be processed
correctly by the device's arithmetic elements. Data
input scaling parameters are specified according to
the manual scale control set in CRl or the input
scaler select set in CR2. Only the sixteen Least
Significant Bits (LSBs) or "shifted" LSBs can be
used safely in the arithmetic elements. If no data
shift is performed, bits RE15 and IM15 must be sign
extended into the three Most Significant bits (REl81& IMl8-1el to conform to the internal two's
complement data buses. To perform FFTs the
device supports an 18 x 17-bit multiply. However,
inputs exceeding the 16-bit formats shown above
may produce an intermediate overflow within the
device's arithmetic elements.

The W-Bus data maybe reduced to 16-bit format to
simplify memory interfacing. To maintain maximum
accuracy, this can be accomplished in one of two
ways. If using only positive window or filter
coefficients, the MSB (W1 el may be connected to
GND through a pull-down resistor (see Interfacing to
1~it Memory Systems). If both positive and
negative coefficients are used, the LSB (WO) can be
connected to GND through a pull-down resistor.

The user is responsible for monitoring and
accommodating data overflow for single pass
instructions and for multiple pass transforms which

Figure 16. Data Bus Formats
19-BIT Fractional Output Data Farmat IRE. IMl

18

17

16

15

14

13

12

11

10

I -~ I ~ I I t' I I I 2~ I r I I •••
2'

2-'

2"2

1

0

W,

Wo

2-5

16-Bit Fractional Input Data Format {RE, 1M) with 3-Bit Sign Extension
18
17
16
15
14
13
12
11
10

65-&155

3-290

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

TMC2310
FIR Filter Operation
The TMC2310 performs both adaptive and non-adaptive
coefficient Finite Inpulse Response (FIRI filters by performing a linear convolution between filter coefficients
and input data. External data memory is used to store
data samples and coefficients. For an N-tap filter, the
data (RE, IMI memory retains the N most recent data
samples and the window/coefficient memory stores the
N filter coefficients.
The output of an N-tap, FIR filter is given by the convolution equation:
N-l
vln-N+ll = E hlklxln-kl

k=D

The convolution is accomplished by multiplying data in
the RE and 1M memories with filter coefficients stored in
external RAM or ROM and input on the W-Bus. During
the multiplication/accumulation, the RE and 1M data are
shifted down in memory by one address in preparation
for the next pass.
At the start of a pass, the N-most recent data samples
(x(nll are stored in memory addresses from 0 through
N-1 in ascending order (oldest sample in address 01.

The filter coefficients are stored in window/coefficient
memory in corresponding addresses but in reversed
order. After the START command, the coefficients and
data are multiplied and accumulated term-by-term, while
each value in RE and 1M memory is shifted down by
one memory location (with RAMSEL= HIGHI. Upon completion of the pass, the RE and 1M data have been
shifted by one location, and the final accumulated result
(y(nll is output to address=N-1 with RAMSEL=LOW.
In preparation for the next pass, the result at memory
address N -1 is read by the host system. Execution stops
at the end of each pass to allow time to read this result
and to load the next data sample. To produce the next
convolution output, this new data input is stored in
location N -1, and a START command is re-issued. This
operation is repeated for each output point y(nl.
A diagram of the ordering of data samples and filter
coefficients before and after successive passes is shown
in Figure 17. An examination of the arrangement of
coefficients (h(kll and data samples (x(nll shows that the
FIR filter equation is calculated by summing the product
of filter coefficients and data points in corresponding
addresses.

Figure 17. FIR Filter Operation
MEMORY
ADDRESS

RE,IM
MEMORY

W·MEMORY

N·1

x(N·1)

h(O)

N·2

x(N·2)

h(1)

RE,IM
MEMORY

W·MEMORY

y(1)

h(O)

h(1)

x(N)

h(1)

·
·
·

·
·
·

·
·
·

h(N ·4)

x(4)

h(N·4)

x(5)

h(N·4)

x(2)

h(N·3)

x(3)

h(N ·3)

x(4)

h(N·3)

x(1)

h(N ·2)

x(2)

h(N·2)

x(3)

h(N·2)

x(O)

h(N·1)

x(1)

h(N·1)

x(2)

h(N·1)

x(3)

x(N)

RE,IM
MEMORY

W·MEMORY

4

y(O)

h(O)

x(N·1)

x(N+ 1)

MEMORY AT END OF PREVIOUS PASS
OUTPUT OF NEXT PASS = y(1)

'4

.
.

MEMORY AT END OF PREVIOUS PASS
OUTPUT OF NEXT PASS = y(2)

y(O) OUTPUT TO
ADDRESSN·1

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-291

I

TMC2310
FIR Filter Operation (cont.)
The filter order (tap length) is set by the
form length" and "number of transform"
CR1 and CR2 respectively. The allowable
16 to 1024 taps, in multiples of 16. The
is two clock cycles per tap, per channel.

"single transparameters in
filter sizes are
throughput rate

Adaptive filters produce an error term for each filter
output:
[Actual Filter Output] - [Desired Filter Output] = Error

or,
y(n)-y(n)' =()' (n)
The error term is used to update the filter coefficients
for the next data pass. The memory arrangement for
adaptive filtering uses the RE memory for data storage
and 1M memory for existing and modified filter coefficients. During the pass, the data (x(n)) are shifted· down
one address in memory while the product of data and
coefficients is being accumulated (with RAMSEL== HIGH).
Concurrent with the determination of the convolution
sum and the data shifting in the RE data memory, the
filter coefficients are modified by the function:

Both the 2-Real and Real/Imaginary FIR filtering are
performed as described above. The "FIR 2-Real"
(CR1[14:11J==1001) instruction utilizes one set of filter
coefficients for both the RE18-0 and 1M 18-0 data. The
FIR Real-Imaginary instruction allows the use of separate
filter coefficients for RE and 1M data. This allows
simultaneous filtering of two independent Real data sets
with different filter functions. Coefficients for each set
are input on alternate clock cycles through the W-Bus
with the use of the RD option available in
CR2[4J.

h'(n) = [1- ()' (nllh(n)

Adaptive FIR Filtering

Where the h' are the filter coefficients used for the next
pass.

Adaptive FIR filtering modifies the filter coefficients
concunrently with the convolution. Adaptive filtering
operates differently from non-adaptive FIR filtering.
As indicated before. the output y(n), can be obtained
by convolving input data with filter coefficients:

The update value a is input on the W-Bus on every read
cycle and the modified filter coefficients are stored in 1M
memory. The operation is shown in Figure 18.

y(nl

=

N-1
E h'(klx(n - kl
k=D

Figure 18. Adaptive Filtering
MEMORY
ADDRESS

RE,IM
MEMORY

W·MEMORY

N·l

x(N·l)

h(O)

N·2

x(N ·2)

h(l)

x(N)

4

RE,IM
MEMORY

W·MEMORY

x(N+l)

'L.

RE,IM
MEMORY

W·MEMORY

y(O)

h'(O)

y(l)

h"(O)

x(N·l)

h'(l)

x(N)

h"(l)

·
·
·

·
·
·

·
·
·

·
·
·

x(3)

h(N· 4)

x(4)

h'(N·4)

x(5)

h"(N·4)

x(2)

h(N· 3)

x(3)

h'(N ·3)

x(4)

h"(N·3)

x(l)

h(N ·2)

x(2)

h'(N·2)

x(3)

h"(N·2)

x(l)

h'(N ·1)

x(2)

h"(N·l)

x(O)

MEMORY AT END OF PASS

MEMORY AT END OF NEXT PASS
Note:

1. W-8us input

=

a Inl

h'lkl = hlkll1- a Inll
h"lkl = h'lkIl1- a 'Inll
y(O) OUTPUT TO
ADDRESS N·1

3-292

Raytheon Semiconductor

For More Information call HIOO-722·7074.

TMC2310
Interfacing to Memory
Using the TMC2310 with lower Resolution Data
The TMC2310 allows data inputs of up to 16 bits for all
operations without the risk of an internal overflow. When
using data values that are smaller than 16 bits it is
recommended that they be placed in the upper MSBs of
the RE and 1M data ports. For instance, when using
12 - bit initial inputs for an FFT operation the real and
imaginary data should be placed on both RE 18 _ 7 and
1M 18 _ 7, respectively. Using the upper MSBs of each
19 - bit data port allows the device to operate in either
the AUTO or MANUAL scale mode. Configuration
Register 1, CRl [4:3]. must be set to perform a right shift
of 3 bits on the data input during the first pass. Results
from the first pass have the potential of growing up to
19 bits, therefore, to maintain maximum precision the
outputs should be contained in 19 - bit wide memory.

external memory in order to increase arithmetic precision
and minimize roundoff error. To obtain the best results,
the memory system should support all 19 data bits. In
order to reduce the number of memory devices, the
system can be configured with 16 - bit wide data
memories. While this configuration may reduce system
size and cost, there will be a decrease in accuracy due
to truncation of the output data. In a 16 - bit memory
system, data should be left - justified (connected to the
16 MSBsl with the 3 LSBs connected to pull- up (or
pull- downl resistors. Configuration Register 1 is
programmed to perform auto or manual data scaling with
a right shift of 3 bits performed on the data during the
first pass (CR[4:3]=111. The 16 MSBs of the output are
stored into memory, truncating the three LSBs.

Initial data inputs can be connected to the 12 LSBs,
however, since the device uses a two's complement data
format each input must be sign extended into RE 18 and
1M 18, the MSBs. For operations that require multiple
passes (i.e., FFTIIFFTI intermediate results will carry less
precision. This will result in a reduction in the overall
accuracy of the transform operation.

In systems utilizing data windowing, the user may
connect either the LSB or the MSB of the W - Bus to
ground through a pull- down resistor of 5 kOhms. If
both positive and negative window values are to be
used, the MSB is required (two's complement formatl
and the LSB may be grounded. For positive magnitude
window functions, the MSB will always be zero, and can
therefore be connected to ground through a 5 kOhm
resistor.

Interfacing to 16 - Bit Memory Systems
The TMC2310 outputs 19 bits of significant data to
Figure 19. Interfacing to 16 - Bit Memories

TMC2310

ClK

-< ~~:~~:

>----t>

For More Information call 1-800-722-7074.

SCEN , . .- - - -.......

Raytheon Semiconductor

3-293

I

TMC2310
Pipelined vs. Non ~ Pipelined Addressing
Operation of the TMC2310 at its maximum clock rate
requires the use of high - speed data memory. By
including a special addressing mode, slower memory can
be used by the addition of high - speed external address
registers. The TMC2310 has been designed to allow the
user to make system tradeoffs between memory cost and
device count.
Normally, a memory address is output and the data
strobed into or out of memory within a single clock
cycle. Therefore, the following relationship must be met:
tCY [tOD(TMC2310 Addr. Dutl + tAcc(memoryl + tS(TMC231 0 Data Inl]

or equivalently, the memory access time must meet the
requirement:
tAcclmemorYI

[tCY- tolTMC23101 - tS(TMC23101]

Use of the "Pipelined Addressing" mode alters the above
relationship. In pipelined mode, the address and controls
IRD and RAMSEL) appear one cycle earlier. For a read
operation, the data will be input to the TMC2310 on the
following cycle. For a write operation, the output data
and the WR strobe will occur one cycle after the
address and controls. For proper synchronization, the
address, RD and RAMSEL outputs must be externally
registered. The requirement for external memory speed
becomes:

tAcclmemorYI

[tCY - tolexternal registerl - tSITMC231 01]

By substitution of the appropriate parameters into the
above equation, it can be seen that the use of an
external high-speed register l'AS374, F374, etc.) results
in a substantial reduction of memory speed laccess time)
requirements.

Typical System Configuration
Figure 20 shows a typical system configuration utilizing
many of the described techniques. The system includes
"pipe lined addressing", evident by the use of external
registers on the TMC2310 memory address and controls.
The system also includes a banked IBank A and Bank B)
memory system ,which may consists of single port or
multi - port memory. IExternal host interface to memories
is not shown.)
Finally, the diagram shows a system utilizing two window
memories Ifor dual real and complex operations). If only
one window memory is required IReal Windows) then
the Imaginary memory, WI21. and associated output
register and inverter may be deleted. For a single
window memory, the chip select of W11) can be
connected to a LOW and the output enable connected to
the DONE flag to disable the memory when the device
is idle.

Figure 20. Typical System Configuration

CMD1_D

ClK

3-294

>---r-'£..--------~:.J

Raytheon Semiconductor

W5-D
(SCALER)

For More Information call 1-800-722-7074.

TMC2310
Applications Infonnation

Rescaling

System Memory Options

After the memory configuration scheme has been
defined the user can now tackle the issue of memory
resolution. Although the device achieves maximum
Signal-to-Noise performance using 19-bit wide memories
excellent performance can still be attained using
narrower memory. A common application is to use 16-bit
memories interfaced to the upper 16 MSBs of each 19bit data port. Independent of the memory width,
rescaling of the data during the computation is necessary
to prevent overflow. Signal-to-noise is maximized when
the auto scale feature is activated, however, the user
must then extract the scaler information from the W-Bus
so that the proper order of magnitude of the data can be
determined. Per definition of the FFT, a shift (or rescale)
of 2 bits performed following every second radix-2
butterfly is sufficient to maintain accuracy without the
threat of overflow. The TMC231 0 supports this mode of
operation with the manual scale option. For example.
when using 12·bit inputs the initial data should be loaded
into the memory with MSB at RE17/IM1]. RE18 and
IM18 are just sign extensions of RE17 and IM17, while
RSt.() and IM4'() should be set to zero. The initial shift
performed at the beginning of the first pass will then
have no effect on the data. Subsequent passes will each
be rescaled by 2 bits following the butterfly operations.
Use the following settings: CR1ISJ:1, CR1[4:3J:10.

Single-port memories for both real and imaginary data
can be used with the TMC2310.lf single port memories
are used, system performance will depend not only on
the time required to perform the operation but also the
time required to load and unload the memory. Systems
requiring continuous operation are better supported with
dual-port memories. This approach allows data to be
loaded into, for example, the upper 1K portion of a 2K
deep memory while the TMC231 0 is operating on data in
the lower 1K addresses. This technique eliminates the
need for arbitration logic available in some dual-port
memory. It is recommended that the device be used in
the Pipelined Addressing mode to eliminate bus
contention between the TMC2310 and the local real and
imaginary data memory.

Memory Interface
When determining system memory requirements, the
user must also take into account the Bit Reversion
necessary to perform the FFT. Either the data must be
stored in bit-reversed memory locations prior to
performing the FFT, orthe TMC2310 must perform the
bit-reversal of the addresses when accessing the real
and imaginary data on the first pass of the FFT. If data
are loaded into memory in bit-reversed locations, the
system can be operated using only 1 bank of memory.
By supporting an additional bank of real and imaginary
memory, the user has the option of allowing the bit
reversal of the addresses to be performed by the
TMC2310. This is a more efficient approach since it
allows the host to load the inputs into one bank and
unload the results from the other bank. Enabling and
disabling of the memory banks is controlled by the
RAMSEL flag provided by the TMC2310.
The operation of the RAMSEL flag is determined in
conjunction with the bit reverse option. The user can
determine the bank where the final results will be
written with the Sourceffarget Memory Select option in
Configuration Register 2. If bit-reversal is performed by
the TMC2310, the RAMSEL flag will toggle in such a
way as to move the intermediate and/or final results into
the second bank of the memory. If the data are loaded
into bit-reversed locations of the memory initially, then
the RAMSEL flag can be used as a signal to indicate
when the final results are being written. CR1[7:6J=10,
CR2[6:5J=1X. (In this configuration the results will be
written to bit-reversed locations).
For More Information call 1·800·722·7074.

Using the TMC231 0 with 17·bit Inputs
For non-FFT applications the device can support 17-bit
wide inputs while returning valid results. For convolution
operation (i.e., MPY-ACC and FIR modes) the user must
be careful not to exceed the accumulator width of the
device. Input data can be placed into RE16'() and IM16.Q
of the two data ports. RE18-17 are sign extensions of
RE16 and IM16.Q of the two data ports. RE18-17 and
IM18-17 are sign extensions of RE16 and IM16 of the
initial inputs. The data in the real and imaginary memory
can also be interfaced to allow an initial shift of the inputs
within the device prior to performing the desired
operation. If the real and imaginary data are stored with
the MSBs at RE17 and IMp. sign extension will be
supported internally in the device following the 2-bit shift,
CR1[4:3J:10.

Raytheon Semiconductor

3·295

I
",

TMC2310
Generating a Write Pulse

generate this write strobe since the ROt signal is
normally LOW and goes HIGH only during write cycles.
The ROlSignal should be gated with the system clock to
create an active LOW write (enable) strobe. If the device
is to be used to implement Unwindowed or Real
Windowed FFTs exclusively. then this method should
achieve better system timing and performance.

The high-speed operation of the TMC2310 requires the
use of fast random access memory. The TMC2310
provides a write enable pin for use with the local real and
imaginary data memories. In some circumstances. it is
necessary for the user to generate this write strobe to
increase the pulse width to meet system requirements.
As an alternative. the user can use the ROt output to

J

~

.... cs
cs

~

....

ClK ,,;

~D
~~
-::!:-

r--~

~

AS374
(2)

<

It-

-

AS32

r

..J

cs

10i'-

r-<: OE

WR

-<

r

BANKB

10-

WE4

~

-

BANKA

CS

OE BANKB

WE4

1.~

1::0-

BANKA

REl8-0

CS

W(1)
(REAL)

OE

~

~

IMl 8-0

AD
RAMSEl
ADg.o
DONE

Iii
Wl6-0
SCEN
CMD 1-O

I?

~1t

I+¥-

WS-O
(SCALER)

65-&156

Figure 1. Memory Interface for FFT Systems

3-296

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2310
Generating a Write Pulse (continued)
More general applications. particularly those that require
(2) window coefficient memories (i.e.• Complex MPV.
RE/IM MPV-ACC etc.). require an alternative circuit for
Write strobe generation. The TMC2310 contains an
option in CR2 that changes the operation of the RD!
signal. Under normal operations CR2[41=O the RD! signal
will not be activated until the first valid result appears at
the real and imaginary data ports. after which RD! will
toggle on successive cycles. If activated. the RD! signal
will toggle following application of the START command

so that WR and WI inputs can be synchronized with the
falling and rising edge of the RD!. respectively. If it is
necessary for the write strobe to be generated for these
modes (including FFT/IFFT with Complex Mpy) then an
alternate circuit must be used. Specifically. if CR2[41=1
RD! will toggle every cycle and if the write strobe is
created by gating RD! with elK then the device will
incorrectly generate (4) write pulses during the first four
read cycles writing over unprocessed data. The following
circuit eliminates this situation by setting CR2[41=O:

.....

CLK ~--I--I I-++-~.r-

WR

RE1e.o

AD
RAMSEL
IV---~-I ADg.o

TMC231 0

1 4 - - - 1 - - - 1 DONE

65-6457

Figure 2. Memory Interface for General Systems

For More Infonnation call 1-800-722-7074.

Raytheon Semiconductor

3-297

I

TMC2310
Bit-Reverse Addressing Details

The radix - 2, Decimation -In -Time (DIT) FFTIIFFT
algorithm performed by the TMC2310 requires data
scrambling during the first butterfly pass (Refs. [2],[3]).
The scrambling amounts to a bitwise reversal of the
address index during the first pass of the FFT. A flow
diagram for a genera!, radix - 2, 16 - point FFT is shown
in Figure 21. By a close examination of the figure, it can
be seen that the first butterfly is performed on data
points Xlo) and XIS) with results stored in X(O) and X(l).
It is apparent that results must be written to a
secondary memory to prevent the loss of the unused
data point X(l).
The TMC2310 allows several addressing options for
transforms. While these modes have no effect on speed
or processing time, they do affect system memory
requirements. If the input data samples are stored in
memory in sequential order, then the TMC2310 must
perform the bit-reversed addressing (CR1[7:6)==01)
during the first butterfly pass. To accomodate the data
scrambling and prevent overwriting of unused data, the
user must provide additional "scratch pad" memory for

intermediate storage during this pass. The RAMSEL
output is used to toggle between the two banks during
reads and writes of the first pass. RAMSEL must be
connected either to the "chip enables" of separate
memories or to an additional address line (for a paged
memory system). At the completion of the transform,
data will be in memory in sequential (frequency or time)
order.
A transform can be done without the scratch pad
memory by initially storing the data in scrambled order.
This is accomplished by a simple reverse ordering of the
address lines between the host system address generator
(counters, etc.) and the data memory (Figure 22). The
transform is then performed "in - place" (no bit - reverse,
CRl [7:6) == ~O). Since the input data has been
"pre - scrambled", the TMC23lo will read and write data
to memory addresses in a sequence that requires no
additional memory. Final results will be available in
sequential, frequency bin order. In either case, if
windowing is performed, the user must store the
window function either in sequential or scrambled order
to match that of the input data.

Figure 21. 16 - Point FFT
MEMORY LOCATION
CR1I7:6]

00

-=

CRII7:6]

=

OUTPUT MEMORY
LOCATION

01

--)(10]

Xo

"

Xi

XU)

X.

XI~

X"

X(3)

X,

XI~

"

X"

Xl5I

X,

XI"

14

X14

XOI

"
"

"
3-298

X,

XI"

X,

Xl9]

10

X,

"
"

X,

10

"

X"

XI'.

"

X"

XUlI

"

14

X,

X(14)

14

"

X"

x(15)

"

Raytheon Semiconductor

12

For More Information call 1-800-722-7074.

TMC2310
Figure 22. Bit-Reversed Input Data for 1024-Point Transform
lO-BIT

COUNTER
CIRCUIT

DUAL - PORT RAM

I

Au

ADO

Al

Al

ADI

Q7

A2

A2

AD2

Q&

A3

A3

AD3

lis

~

~

AD4

Q4

A5

A5

AD5

Q3

As

A&

AD&

Q2

A7

A7

AD7

Ql

Aa

Aa

ADa

Ag

Ag

ADg

Ilg

Au

Oa

Do

DATA
RE.IM~ DATA

DATA

3a

DATA

I

'19
'19

I

TMC231 0

REla-o
IM18_0

Alternate Method For Write Strobe Generation
The high-speed operation of the TMC2310 requires the
use of fast random addess memory. In some instances.
the pUlse-width and timing of the TMC231 D's WR may
not meet the system requirements. As an alternative, the
user can use the RD output used to generate a write
strobe for memory. Since RD is normally LOW and goes
HIGH only during write cycles, the user can gate RD
with the system clock to create an active LOW write
(enable) strobe. Implementing the write strobe in this

method may give better system timing and performance.
The strobe will be the LOW portion of the system clock.
Figure 23, part (a) shows external generation of a write
strobe in non-pipelined addressing systems, and part (b)
for pipelined systems utilizing the external address
registers. The external register (74AS821) is clocked by
a delayed system clock (through the AS32) to guarantee
a valid memory address until WE goes HIGH.

Figure 23. Generating a Write Strobe
RAMSEL
TMC2310

ClK

>-_-D

ADg_O _ _ .... ,
TMC2310

TO WE
OF RAM
(a)

ClK>-..--I:>

TO WE
OF RAM

For More Information call 1-800·722·7074.

Raytheon Semiconductor

3·299

TMC2310
Scale Factor (W3-0)

In the inverse FFl the final exponent read at this port
will be the true binary exponent for the emerging real
and imaginary data, In the forward FFl this value will
exceed the true exponent by N, where the total number
of transform points is 2N The format for this exponent
is 4-bit unsigned integer.
References

[1] Harris, F.J., "On the Use of Windows for
Harmonic Analysis with the Discrete Fourier

Transform;' Proceedings of the IEEE, Vol. 66,
No, 1, January, 1978, pp 51-83.
[2] Oppenheim, AV, Schafer, RW, "Digital Signal
Processing," Prentice-Hall, Inc" 1975,
[3] Rabiner, LR" Gold, B" "Theory and Applications
of Digital Signal Processing," Prentice-Hall, Inc"
Copyright-Bell Laboratories,

Ordering Information
Product
Number

Temperature Range

Screening

TMC231OG5V
TMC2310G5Vl

EXT - TC= - 55°C to 125°C
EXT-TC= -55°C to 125°C

MIL-STD-883, 15MHz
MIL-STD-883, 20MHz

88 Pin Ceramic Pin Grid Array
88 Pin Ceramic Pin Grid Array

231OG5V
231OG5Vl

TMC2310H7C

STD-TA=O°C to 70°C

Commercial, 20MHz

89 Pin Plastic Pin Grid Array

231OH7C

TMC231OL4V
TMC2310L4Vl

EXT-TC= -55°C to 125°C
EXT - TC= -55°C to 125°C

MIL-STD-883, 15MHz

100 Leaded Ceramic Chip Carrier
100 Leaded Ceramic Chip Carrier

231OL4V

MIL-STD-883, 20M Hz

TMC2310L6V
TMC231OL6Vl

EXT - TC= -55°C to 125°C
EXT-TC= -55°C to 125°C

MIL-STD-883, 15MHz
MIL-STD-883, 20MHz

132 Leaded CEROUAD
132 Leaded CEROUAD

2310L6V
231OL6V1

Package

Package
Marking

2310L4Vl

40005263 Rev E 8193

3-300

Raytheon Semiconductor

For More Information caJI1-800·722·7074.

TMC2311
TMC2311
CMOS Fast Cosine Transform Processor
12 Bits, 15 Million Pixels Per Second

Description

Features

The TMC2311, a high-speed algorithm specific
processor, computes the one or two dimensional forward
discrete cosine transform (DCl) of an 8 or 8x8 point array
of contiguous 9-bit data or the inverse OCT of 12-bit data.
Output precision in all cases in 12 bilS. It complies with
the CCITT Specialists' Group on Visual Telephony (SG
XV) accuracy specification for inverse OCT. With ilS
internal coefficient TOM, data transpose RAM, address
generators, and sequencer, the TMC2311 acceplS high
level instructions from a host processor and raw 8x8
blocked data from an external memory and returns
transformed data to a second external memory. The
TMC2311 also includes a defeatable adder-subtractor for
linear predictive coding and differential pulse code
modulation. The p1pelined TMC2311 can transform
continuous 8x8 pixel data blocks at a rate of one per
4.48 J.IS.

•

Operating under a system clock of up to 30 MHz, the
TMC2311 accepts each incoming data block in row-major
("line-by-Iine") format at two clock cycles per pixel. Output
data are written in column-major format, Le., down the
left-most column of the block, then down the next column
to the right, etc., also at two clock cycles per pixel. In the
inverse OCT mode, the chip acceplS column-major data
and returns row-major data. Thus, a pair of TMC2311
chips can transform an image and return it to ilS original
spatial domain, with or without any intervening operation,
such as compression, transmission and re-expansion.
Built with a one-micron double level metal OMICRONCTM low-power CMOS process, the TMC2311 is
available in a 68-lead plastic chip carrier.

•
•
•
•
•
•
•
•
•

Stand alone execution of 8-point forward or inverse
cosine transform
Continuous 8x8-point 2-D OCTs every 4.48 J.IS
including memory transpose and data loading!
unloading
On-chip cosine coefficient ROM
On-chip data transpose memory with direct transpose
mode
Auxiliary adder with optional clipped outputs for linear
predictive coding and differential pulse code
modulation
Two's complement 12-bit data VO format
Two's complement 9-bit add/subtract input
Full CCITT SGXV compatibility
All inpulS and outputs m compatible
68 pin Plastic Chip Carrier

Logic Symbol
12
DlN I1 _0

DOUTI1-O

DATA
INPUTS

liE

DXB-O

I

ISEL
DSEL

CTRL7_0

CONTROL
IN/OUT

l'fff

BOT

OUTPUTS
ANO
ENABLES

EOB

TMC2311

iiii

FE

WR
INIT

1
For More Information call 1-800-722-7074.

NOOP
CLK

Raytheon Semiconductor

24026A

3-301

I

TMC2311
Applications

Associated Products

•
•
•
•
•
•
•

• TMC2220 - 4x32 Correlator
• TMC2250 - 2-D 3x3 FIR Filter
• TMC2272 - Colorspace Converter

Image Processing, Graphics
Pulse And Image Compression
Video Teleconferencing
Linear Predictive Coding
Differential Pulse Code Modulation
Electronic Publishing
Medical Imaging And Archiving

Figure 1. Functional Block Diagram

DXIJ..O

ISEl

OSEL

CTRL3

.or

iii

w,r-----'
NOOPr---------L_ _ _ _ _---.J

Functional Description
The TMC2311 comprises five internal blocks: a controller,
two arithmetic elements, a data transpose memory and
an auxiliary adder circuit (Figure 1). Each arithmetic
element (AE) can compute an 8-point 1-dimensional OCT
in 16 clock cycles. When the device is configured to
perform 2-dimensional transforms, the first AE computes
the OCT of each consecutive row of 8 pixels. The results
of each 8x1 OCT are written into the intermediate memory.
After eight 1-dimensional transforms are computed, the
device computes the OCT of each consecutive 8-pixel
column, while (if so instructed) computing the DCTs of
the rows of the next block of data. The auxiliary adder/
subtractor can be used with a forward and inverse
transform in linear predictive coding applications. The

3-302

'OT

adder can also be used alone to perform differential pulse
code modulation without the cosine transform. In all modes
and configurations the device operates on continuous data
at a rate of up to 15 Megapels/second and can perform a
complete 8x8 OCT every 128 clock cycles.

Control
The control block includes the chip's preprogrammed
controller, sequencer, and microcode generator. The host
system needs only to load a single 8-bit control word on
C7-0 and then strobe the INIT pin. The chip will proceed
automatically through the chosen operation without further
supervision.

Raytheon Semiconductor

For More Information call HlOO-722-7074.

TMC2311
Arithmetic Element #1

Figure 2. 2-D Transform (With Transpose)

Comprising a multiplier and two adder/subtractors,
bypassable processor AE1 performs a series of onedimensional8-point forward or inverse OCTs on the
incoming data, writing its 8-point transform results into
the transpose memory.

DDUTl1_0

DlNl1_0

Data Transpose Memory

TMC2311

This two-port 64-word RAM collects each group of eight
consecutive 8-point transformed data sets from AE1 and
then passes them to AE2 while collecting the next group,
thereby acting as a large pipeline buffer. When enabled,
the OTM accepts each 64-point data block in row-major
sequence and returns the same data in column-major
order, effecting a "corner turn." Bypassing this block
leaves the data sequence unchanged.

24032A

The device can also perform one-dimensional OCTs (lOCTs)
with or without memory transpose.
When CTRL2-0 =010, the chip will transform eight 8-point
rows of incoming data, then transpose the results without
transforming the columns (Figure 3).

Figure 3.1-0 Transform With 8x8 Transpose

Arithmetic Element #2
I~entical to AE1, bypassable data processor AE2 performs
eight 8- point one-dimensional transforms on each 64-point
block of data. Each transform pulls one data point from
each of the eight transforms done by AE1, completing the
8x8 two-dimensional transform. For one-dimensional
transforms, either AE can be bypassed.

DIN 11 _0

I -........- T " " " " l......./ DOUT11 _0

TMC2311

24033A

Auxiliary Adder
T~e

remaining circuitry in Figure 1can be employed as
either a presubtractor or a post-adder. (See Applications
Discussions of Linear Predictive Coding, Differential
Pulse Code Modulation, and Interframe Coding.) As
instructed by CTRL3 (INVERT), CTRL7 (XSEL), ISEL. and
OSEL. this .adder combines the 9-bit two's complement
data entering on port OX8-0 with either the incoming or
emerging data stream.

When CTRL2-0 =011, the device accepts eight 8-point
rows of data and transposes them before AE2 performs
one-dimensional OCTs (IOCTs) of the columns (Figure 4).

Figure 4. 8x8 Transpose With 1-0 Transform

DOUT11 _0

Operating Modes
The TMC2311 's five operating modes are selected by
control PinS CTRL2 -0. The device can be configured in the
following ways:
The device will perform a two-dimensional transform if
CTRL2-0 =000 or 001. AE1 performs a one-dimensional
OCT (lOCT if CTRL3 =1) on each of eight 8-pixel rows of
data supplied row-by-row to OIN11-0. Results from each
block of eight transforms are fed via the Transpose
Memory to AE2, which performs a one-dimensional OCT
(I~CT) on each of the eight 8-pixel columns of data, in turn
(Figure 2).

For More Information call 1-800·722·7074.

TMC2311

24034A

The device can also perform one-dimensional transforms
without transposes. When CTRL2-0 =100 or 101, AE1
performs a one-dimensional OCT or IOCT on each incoming
8-polnt row of data (Figure 5).

Raytheon Semiconductor

3·303

I

TMC2311
Figure 6. Memory Transpose (Without Transform)

Figure 5. 1-D Transform (Without Transpose)

DlNI1_0

I---r---Y--Y-v DDUTI1 _0

TMC2311

TMC2311

24035A

Finally, the device wiil perform the memory transpose with
no OCT when CTRL2-0 = 110 or 111 (Figure 6).

24036A

Table 1summarizes the operation of controls CTRL7,
CTRL3, ISEL and OSEL which "fine tune" the mode
selection by programming the presubtractor/postadder and
the transform direction. (Where a full two- dimensional FCT
or IFCT is needed, CTRL2-0 must be set to 011. CTRL7=1
then enables presubtraction and OSEL= 1 enables
postaddition, as desired by the user.)

Table 1. Operating Mode Configurations
Device Configuration
CTRLJ

ISEL

OSEL

0
0
1

0
1

X
X

0
0

0
1

0
0

0
1

0
1
0
1

0
0
0

0
1
1

0
1
1

1

1

0

1

0

Function

20 OCT
20 IDCT
Interframe Compress
Interframe Decompress

20 FCT
2DIFCT
20 FCT, Presubtract
20 IFCT, Post Add

LPC
ILPC
LPC Directly Out
ILPC Directly Out

20 FCT, Presubtract
20 IFCT, Post Add
DOUT~DIN-DX

0
1
0
1

DOUT~DIN+DX

1

DPCM Directly Out
IDPCM Directly Out

DOUT(k)~DIN(k)-DIN(k-l )

1

DOUT(k)~DIN(kl+DIN(k-l )

1

DPCM w/Transpose
IDPCM w/Transpose

DOUT(k)~DIN(k)-DIN(k-l )

1

DOUT(k)~DIN(k)+DIN(k-l )

1

Notes:

3-304

CTRL7

Application

LPC/ILPC
DPCM/IDPCM

0
1
0
1

1
1

Linear Predictive Coding IForward/lnverse)
Differential Pulse Code Modulation IForward/lnverse)

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2311
Signal Definitions

CTRL4

Automatic Reinitialization (AUTOINIT). AI=O
allows continuous operation of device. When
AI= 1, the device will halt at the end of the
specified transform.

CTRL5

Arithmetic Limit (CLIP). CLlP=1 saturates data
outputs to 9 bits. CLIP is useful when
presubtraction or postaddition is used with
the OCT or IDCT.

CTRL6

Flag Control (FC). FC determines when the
output flags, BOT and EOB, appear. When
FC=O, both flags are output with the
corresponding data result. When FC= 1, the
flags appear two clock cycles earlier.

CTRL7

Auxiliary Adder Select (XSEL). XSEL controls
two multiplexers within the auxiliary adder
circuitry. The first mux feeds the non-inverted
input to the adder either the DIN port
(XSEL= 1) or outputs from the core of the
device (XSEL=O). The second mux selects the
data entering the core of the device from
either the input port (XSEL=O) or adder output
(XSEL= 1). See Applications, Operating
Mode Configurations.

ISEL

Input Data Select. ISEL=O connects the
inverted (optional) input of the auxiliary adder
to the OX port. When ISEL=1, the DIN port is
connected, via a one data cycle delay. Output
from this mux to the adder is inverted when
INV=O. See Applications, Operating Mode
Configurations.

OSEL

Output Data Select. When OSEL=O, data
results from the device core pass to the final
output register. When OSEL= 1, results from
the adder pass to the final output register.
See Applications, Operating Mode
Configurations.

OE

Asynchronous active LOW OUTPUT ENABLE
for data output port, DOUT 11-0. When OE= 1,
every output is forced into a high-impedance
state.

FE

Active LOW asynchronous output FLAG
ENABLE. When FE= 1, BOT and EOB are forced
into a high-impedance state.

Control
INIT

Single pass "start" command. INIT=O resets
the internal logic and output flags and
updates the CTRL7-0 parameters. INIT is
registered and must be LOW for at least 3
clock cycles. INIT returning HIGH starts the
transform. The first data point is loaded two
cycles later.

NOOP

Input clock disable. NOOP= 1 freezes
operation of the device on the next CLK rising
edge. Operation commences from where it
stopped one cycle after NOOP returns LOW.

WR

Control word preload command. WR=O loads
CTRL7-0 parameters into the device's preload
register. The next INIT rising edge transfers
the preloaded parameters into the chip's
working registers.

RD

Control word (READ) command. RD=O allows
the preloaded parameters CTRL7-0 to be
read.

CTRL2-0

MODE Control. Defines the internal
configuration (mode) of the device, selecting
either 2-dimensional or 1-dimensional
transforms and/or the access to the internal
Transpose Memory (Figures 2through 6.)

CTRL3

CTRL2--O

Operation

000
001
010

2-0 Transform

011
100
101

2-0 Transform
1-0 Transform, Transpose
Transpose, 1-0 Transform
1-0 Transform
1-0 Transform

110
111

Transpose
Transpose

Inverse Transform Enable (lNV). INV=O
selects a forward OCT. If INV= 1, the device
will compute the Inverse OCT. INV also
inverts the data to one side of the auxiliary
adder. When and only when INV=O, data
from the multiplexer which selects the OX
port or delayed DIN port will be inverted.

For More Information call 1-800-722-7074.

Raytheon semiconductor

3-305

I

TMC23.11
Data Inputs
DINll-0

DXs-o

Data INput Port (12-bit two's complement
format). DIN is the input port for both
FORWARD and INVERSE transforms. DIN11 is
the MSB. For two dimensional forward
transforms, data precision is limited to 9 bits,
DINS-O, and must be sign-extended into the
remaining MSBs. Data exceeding the lower 9bit range may cause an internal overflow. For
INVERSE transforms, the entire 12-bit input
port may used without risk of overflow.
Auxiliary Data Input Port (9-bit two's
complement format). Feeds one side of
auxiliary adder. DXS is the MSB. Auxiliary
inputs can be provided to the device for linear
predictive coding (lPC) where pixel
differences are transformed. In the FORWARD
direction, inputs supplied to the OX port (and
selected via ISEl) will be subtracted from
pixel values input simultaneously on the DIN
port. In the INVERSE direction, OX inputs will
be added to outputs following the desired
tranform operation. The OX inputs must be
delayed so that they appear at the adder
simultaneously with the corresponding pixel
outputs.

Data Outputs
DOUT 11-0

3-306

are clipped to 9 bits, DOUTS-O, with sign
extension into the remaining MSBs. DOUT is
forced into a high-impedance state when
OE=l.

Output Flags
BOT

Beginning Of Transform. Toggles lOW to
denote the first result of each onedimensional S-point transform or the first
result of each S-point row or column of a twodimensional transform. When FC=O, BOT will
appear simultaneously with the corresponding
result. When FC= 1, BOT will appear one data
I/O cycle earlier.

EOB

End Of Block. Toggles lOW to signal the last
result of the entire (S or 64 point) transform
field. When FC=O, EOB appears
simultaneously with the last data result.
When FC= 1, EOB appears two cycles earlier.

Clock
ClK

Data Path Clock. The device operates with a
clock of 0 to 30M Hz. All internal operations
are referenced to the rising edges of ClK; I/O
operations except CTRl7-0 read and write, to
alternate rising edges of ClK.

Power

Data OUTput Port (12-bit, two's complement
format). DOUT is the output port for both
FORWARD and INVERSE transforms. DOUT11
is the MSB. When CLlP=l, all data outputs

VDD, GND

The TMC2311 operates from a single +5 Volt
supply. All VDD and GND pins must be
connected.

Raytheon Semiconductor

For Morelnfonnation call 1-800·722·7074.

TMC2311
Table 2. Data Formats and Bit Weighting

I

4

10

11

o

3

Input Data Format- Forward Transforms
DIN

S

S

S

28

27

26

23

22

23
23

22

21

24

22

21

zO
zO

24

23

22

21

20

23

22

21

zO

23

22

21

25

20

Input Data Format -Inverse Transforms

ox:

I
I

-211
-211

I
I

210
210

I
I

29

z9

28

27

26

-28

27

28

27

z6
z6

24

25
25
25

I·

Output Data Format- Forward Transforms
DOUT:I

-211

210

29

28

27

I

26

I

25

I

24

I

Output Data Format-Inverse Transforms
S

Notes:

S

S

-zS

27

26

25

24

zOl

S=Sign Extension.
In forward transforms, system should feed two's complement sign bit to OINll-8 for 9-bit data size.
In inverse transforms, chip will output two's complement sign bit into pins DOUT 11-8.

Figure 7. Control Preload Timing

Operation and Timing
Initialization
Control Word Preload Timing
The self-sequencing TMC2311 requires no cycle-to-cy~
supervision by the host system. On the rising edge of WR,
the user loads an 8-bit control word (CTRL7-0) which sets 5
device parameters: mode and direction of the transform,
continuous (or non-continuous) device operation, format of
output data and timing of the output flags, The control
parameters preloaded via CTRL7-0 are registered internally
and updated by the INIT signal. Control load timing is
displayed in Figure l

CTRL 7_0

RXXXX XXXXXXXXXXX)
C(Nl

I

~X

PRELOAD
REGISTER _ _ _
C_(N_-1_1_ _ _..L.l'--_ _ _C_(_Nl_ _ __

INIT

~

WORKING
REGISTER _ _ _ _ _ _
C_(N_-1_l_ _ _ _ _..........._C_(N_l_
24028A

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-307

TMC2311
Figure 8. Control Read Timing

Control Word Read Timing
The TMC2311 also permits the user to read the preloaded
control word value back through CTRL7-0, a bidirectional
port. When RD=O, the CTRL7-0 port outputs the control
information stored in the device (Figure 8).

Rill - - - !
!-I

tDO~ ~tHO~

CTRl 7_0

KXXXX

XXXXXXXXXX)
24029A

Data Input Timing

Data Output Timing

After the TMC2311 is initialized, data are input to DIN 11-0
and DXS-O on alternate rising edges of the device system
clock. When the device is set for forward DCTs with
transpose, data inputs are accepted in row-major format
i.e., line-by-line through the SxS transform window. When
the device performs inverse DCTs, inputs are accepted in
column-major format. Following the rising edge of INIT
command, data inputs can be continuously loaded into the
device on alternate rising edges of the system clock
(Figure 9).

Results are output at half the system clock rate. The initial
result latency and the number of results depends on the
device operation specified by CTRL2-0. Once the first result
reaches the output port remaining results will appear
continuously. When the TMC2311 is set to perform forward
DCTs with transpose, output data are written in columnmajor format. In the inverse direction, data results are
returned row-by-row (Figure 10).

Figure 9. Data Input Timing

Figure 10. Data Output Timing
ClK
I

DEI

ClK

1

I

L
----~,------,~,

1
---I!-- I DO 1---1
---I lEN I-- i'HO--j H-

I

I

tSI--

~
I EDG ES OF ClK ---I I-- t H
~23RISING

INIT

1

ts+3tCy+tH

I i
1

r

I DIS

1

~ts~

DOUT 11-0

(XXXX XX XX XX
24031A

tHf.li--

~H (XXXXXXXXXX~~X
I

DX 8_0

I

(XXXXXXXXXX~o·~X
24030A

3-308

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2311
Overall Timing
The TMC2311 will expect data in groups of Sor 64 points
at regular intervals based on the mode of operation defined
by CTRL2-0. Results will be returned ~y th~ T~C2311 In
similar groups following a predetermined initial latency.
For applications that use the auxiliary adder ahead of the
core of the device, corresponding OX and DIN inputs should
be presented simultaneously to the device. Applications
that use the adder after the OCT/memory core must
account for the device's internal latency (Table 3). Each
OX port input must be timed to appear at the adder one
data cycle ahead of its corresponding output.
Table 3. Data Output latency
CTRLZ-O

Operation

Latency*

000
001

2-0 Transform

232 clocks
232

2-0 Transform
1-0 Transform, Transpose
Transpose, 1-0 Transform
1-0 Transform
1-0 Transform

010
all
100
101
110
Transpose
111
Transpose
'cycles after INIT goes high

For More Information call 1-800·722·7074.

200
200
56
56
168

If AUTOINIT (CTRL4)=O, the device will operate
continuously with no interruption between transforms.
Otherwise the device will halt after the specified number
of data points have been processed. When AUTO!Nll=1,
device operation will resume with the next INIT signal.
The TMC2311 also provides two output flags to
differentiate between the rows/columns of the transform
window and between individual transform blocks. The
Beginning Of Transform (BOT) flag goes LOW with the first
data result of each Sx1 transform row or column. A second
flag, End Of Block, EOB, delineates transform blocks. EOB
will go LOW when the last data point of each Sx1 (one
dimensional mode) or SxS (two dimensional mode)
transform is output. The user can program these flags to
appear with their respective data (FC=O) or o.ne. data cycle
earlier (FC= 1). Figure 11 shows the overall timing of a
forward 2-D OCT with pre-subtraction and FC=O. Figure 12
shows the overall timing of an inverse 2-D OCT with post
addition and FC=1, demonstrating the timing for inputs to
auxiliary port OXS-O and the shift in flag timing.

168

Raytheon Semiconductor

3-309

I

TMC2311
Figure 11. Overall Timing - Forward Transform (Flag Control=O)
CLOCK

INIT 1 . . __--'
(0. 01
(0, 11
(X, XI
(X, xI
D1N,,_O "7'r"'J(X"l"'7'rXX.. . .,X.......
XX'"""'X,;..;...;X
........X'ft"'7X~~ ~ XXX XXX ~
(0.01
(0, 11
(X, XI
(X, XI
DXS-O.. . . ,(X......
XX......,X......
XX'"""'X,;..;...;X,.......X.,....;.X~~ ~ XXX XXX ~

»

S~XXXX

DOUTS_O (XXXXXXXX

x<)

)

BOT

"»

EOB

"»

10,01

Notes: 1. DlNll-0 (i,j) aligned with OXS-O lUI, but alignment with OOUTll-0 is mode-dependent
2. OOUTll-0 (0,0) is valid on elK rising edge 116 in two-dimensional transfer modes only.

Figure 12. Overall Timing - Inverse Transform (Flag Control=1)
CLOCK

INIT 1 . . __--'
(0. 0)

(1.D~ ~

XI

(X, XI

(X, X)

(X, x~

(0 0)

(0,1)

(0,2)

(0,3)<-

(X,

DINtH (XXXXXXX XXX A9 ). XXX

XXX XXX XXX
DXs_o (XXXXXXXXXXXX;\g ) XXX' XXX XXX XXX
<- ~

I

~~

BOT

"»

EOB

)"

(0,1)

X

~

t:9
)

)

2. DOUTll-0 10.01 is valid on elK rising edge 116 in two-dimensional transform modes only.

Raytheon Semiconductor

A9

(

Notes: 1. OXs-o (i.j) precedes OOUT11-0 (i,j) by two elK cycles, but alignment with OINl1-0 is mode-dependent.

3-310

A9

For More Information call 1-1300-722-7074.

TMC2311
117

228

232

244

240

236

JL,
~

~~---------------------------------------------

~

~

~
~

~

~
~

(

r

~

(

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

(X, XI

I

)

~ SX
(

(X, XI

XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX X)
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX X)
(7,61

(0,71

(1,71

(2,71

X X X

(3,71

(4,71

(5,71

(6,71

X X

X

(7,71

X

X

)

(0,01

X

X

I

)

24032A

~

~

~

~

---',

(

~
~

~
---',

---',

(X, XI

(X, XI

(X, X~ ~

(X, XI

(X, XI

(X, X~ ~

XXX XXX XXX
XXX XXX XXX

(X,XI

(X,XI

(X,XI

(X, XI

(X,XI

(X,XI

(

(6,61

(6,71

X

(7,01

X

,)
(

(X,XI

,»

)

SX

(X,XI

XXX XXX XXX XXX ID
XXX XXX XXX XXX X)

)

XSSX
CC

»

(7,51

(7,61

X

(7,11

X

(0,01

X

X

I

C(

»

24033A

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-311

TMC2311
Absolute maximum ratings (beyond which the device may be damaged)l
Supply Voltage ...............................................................................................................................................................................................-0.5 to +7.0V
Input VoltageZ ...................................................................................................................................................................................-0.5 to (VDD + 0.5)V
Output

Applied Voltage 2 .......................................................................................................................................................-0.5 to (VDD + 0.5V)
Forced Current,3.4 ..............................................................................................................................................................-3.0 to +6.0mA
Short Circuit Duration
(single output in HIGH state to ground) ............................................................................................................................... 1 second
Temperature

Operating, Case ....................................................................................................................................................................-6Oto +130°C
Junction .......................................................................................................................................................................................+175°C
Lead, Soldering (10 seconds) .........................................................................................................................................................+300°C
Storage ...................................................................................................................................................................................-65 to +150°C
Notes: 1. Absolute maximum ratings are limiting values applied individually while a" other parameter are within specified operating conditions. Functional operation
under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range. and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

Operating conditions
Temperature Range
Parameter

3-312

Min

VOD

Supply Voltage

tCY

Cycle Time
TMC2311
TMC2311-1
TMC2311-2

4.75

tpWL
tpWH

Clock Pulse Width, LOW
Clock Pulse Width, HIGH

ts
tH

Input Setup Time
Input Hold Time

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

IOL
IOH

Output Current, Logic LOW
Output Current, Logic HIGH

TA
TC

Ambient Temperature, Still Air
Case Temperature

Standard
Nom

Max

5.0

5.25

Units
V

37
34.5
28

ns
ns
ns

8
8

ns
ns

11

ns
ns

0

0.8
2.0

0

Raytheon Semiconductor

V
V

4.0
-2.0

mA
mA

70

°c
°C

For More Information caJI1-800-722-7074.

TMC2311
Electrical characteristics within specified operating conditions 1
Temperature Range
Standard
Parameter

Test Conditions

Min

Max

Units

IOOG
IOOU

Supply Current, Guiescent2
Supply Current, Unloaded

Voo=Max, VIN=OV, TS=5V
Voo=Max, f=30MHz, TS=5V

30
130

rnA
rnA

III
IIH

Input Current, logic lOW
Input Current, logic HIGH

VOO=Max, VIN=OV
Voo=Max, VIN=VOO

-10
+10

~

VOL
VOH

Output Voltage, logic lOW
Output Voltage, logic HIGH

Voo=Min,IOl=Max
Voo=Min,IOH=Max

IOZl
IOZH

Hi-Z Output leakage Current,
Hi-Z Output leakage Current,

lOS

Short Circuit Output Current

Voo=Max, VIN=OV Output LOW
Voo=Max, VIN=OV
Output HIGH
Voo=Max, Output
HIGH one pin to
ground one second
duration max.

CI
Co

Input Capacitance
Output Capacitance

TA=25°C, f=lMHz
TA=25°C, f=lMHz

Note:

0.4
2.4

~

I

V
V

-40
+40

rnA
rnA

-45

rnA

10
10

pF
pF

1. Actual test conditions may vary from those shown above. but guarantee operation as specified.
2. Following power-on. the TMC2311 must be clocked for at least 10 clock cycles before the clock is disabled.

Switching characteristics within specified operating conditions 1
Temperature Range
Standard
Parameter
too

tHO
tENA

tOiS
Note:

Test Conditions

Output Delay
TMC2311
TMC2311-1
TMC2311-2
Output Hold Time
Three-State Output Enable Delay
TMC2311
TMC2311-1
TMC2311-2
Three-State Output Disable Delay

Min

Voo=Min, Cloa d=40pF

Voo=Max, Cl oa d=40pF
Voo=Min, Cloa d=40pF

Voo=Min, Cloa d=40pF

Max

Units

16
16
16
12

ns

4
16
16
16
12
22

ns
ns

ns

1. All transitions except for tOiS and tENA are measured at a 1.5V level.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-313

TMC2311
Figure 13. Equivalent Input Circuit

Figure 14. Equivalent Output Circuit
VOO
n SUBSTRATE

nSUBSTRATl
01

01

p+

CONTROL
INPUT

p+

0----1--'\/ / \ r - _ - - - - .
n+
1KO

02

03
pWELL

n

pWELL

02
pWELL
>---~t--:::-:=---'

.,. GNO

21122A

Applications Discussions

21121A

Figure 15. Basic System

Frequency Domain Coding - Basic System
Frequency domain coding entails partitioning an image into
(for example) 8x8 pixel blocks, then determining the twodimensional spatial frequency spectrum of each block. In
image compression, each component is then quantized by a
frequency-specific factor, which tends to be smaller (more
precise) for the dominant lower- frequency components
and larger (coarser) for the less crucial higher-frequency
components. Quantization effects compression by reducing
the number of bits per frequency bin and by zeroing out
high-frequency, low-energy bins. Following the quantizer,
the scaled frequency data are then (arithmetic or Huffman)
coded into a format that will allow them to be transmitted
(or archived) even more economically. In particular, the
JPEG modified Huffman coding represents each string of
"zeroed out" bins with a compact code.

r - - - - - - COMPRESSOR - - - - - - - - ,

CTRl3-l) =0000, 2D FORWARO

~CT

n= QUANTIZER
CODER =HUFfMAN OR ARITHMnlC ENTROPY CODER

24034A

r------DECOMPRESSOR - - - - - - ,

The transmitted images are reconstructed by reversing
these operations. Coded information is received and
restored to frequency information through a decoder. The
received (or retrieved) data then pass through an inverse
quantizer that restores the most important frequency
components, albeit at somewhat grainier than original
levels. Finally, the image is reconstructed by the inverse
OCT. In practice, compression ratios of up to 20:1 can
provide visually acceptable results with still images.

CTRl3.0 = 1000, 2D INVERSE DCT

24035A

The basic compression circuit (Figure 15) shows a sample
implementation of an intraframe compressor. The system
contains an encoder comprising the TMC2311 OCT chip, a
quantizer and a coder. Images are reconstructed in a
complementary system with a decoder, a dequantizer, and
a TMC2311 (inverse) OCT chip.

3-314

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2311
Figure 16. Interframe Compression System

r- OECOMPRESSOR ----,

, . . - - - - - - - - COMPRESSOR--------,

I
2403JA
24036A

Interframe Compression

Linear Predictive Coding System

Figure 16 shows a moving picture extension of frequency
domain coding, which processes differences between the
corresponding pixels of successive image frames.
Interframe compression describes areas of change within a
moving image by comparing each new frame against
earlier frames. Prior to the OCT. a block from the new
frame is subtracted from the corresponding block of the
previous frame. The resulting differences are transformed,
quantized, coded, and transmitted. The compressed data
are then reconstructed by reversing the processing steps:
decode, dequantize, inverse OCT. then accumulate
differences from frame to frame. Transforming only these
differences increases the achievable compression.

Many critical biomedical and defense applications require
that images be compressed and then restored "Iosslessly,"
i.e., without degradation. One technique, referred to as
Linear Predictive Coding (LPCl. has been very effective in
speech compression. For image compression, LPC entails
coding the differences between the current and previous
pixel blocks of the same frame. This technique of
intraframe compression can be used with or without the
OCT. Much of the Figure 16 interframe compression
architecture can also be applied here, although the delay
block now corresponds to delay within a single frame.

For More Information call 1-800-722-7074.

To obtain lossless compression, the user may code the
differences between pixel blocks directly, without the OCT.
This variety of intraframe compression, demonstrated in
Figure 17, uses just the auxiliary adder of the TMC2311. In
the forward direction, the differences are computed and
transferred to the quantizer and coder circuitry where they
are readied for transmission. In the inverse direction, the
reconstruction process involves inverse coding and
quantization, followed by cumulative addition of the image
differences by the TMC2311 's auxiliary adder.

Raytheon Semiconductor

3-315

TMC2311
Figure 17. linear Predictive Coding System (No Cosine Transform)

r-

, . . . - - - - - - - COMPRESSOR--------,

DECOMPRESS OR

~

24039A
2403BA

Differential Pulse Code Modulation
Another linear prediction algorithm, differential pulse code
modulation, (DPCM) uses the differences between
individual pixels on each line of the image. These
differences are quantized, coded and transmitted (or
archived). This technique is also used where lossless
compression is required. The system shown in Figure 18
illustrates the use of the auxiliary adder circuit of the
TMC2311. The device incorporates a special input delay
path that allows a previous pixel value to be added or
subtracted from the current input pixel value. The results
are then either fed into the device core to perform a
transpose function or output directly from the adder. In the
forward direction the pixel differences are fed to the
quantizer and coder blocks of the system and transmitted.
In the inverse direction the coded information is
reconstructed by inverse coding followed by inverse
quantization and finally the accumulation of pixel
differences in the TMC2311.

3-316

Figure 18. Differential Pulse Code Modulation
System (No Cosine Transform)
, - - - - - - - COMPRESSOR - - - - - - - ,

, . . . - - - - - - DECOMPRESSOR - - - - - - ,

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2311
Package Interconnections
Signal
Type

Signal
Name

Power

VDD
GND

Clock

Function

R1 Package Pin

Value

Supply Voltage
Ground

+5.0V
O.OV

21017335368
149131826355267

CLK

System Clock

TTL

65

Inputs

DINll-0
DX8-0

Data Inputs
Aux Adder In

TTL
TTL

444546474849505154555657
343637383940414243

Outputs

DOUTll-0
BOT
EOB

Data Outputs
Begin Transform
End Of Block

TTL
TTL
TTL

56781112141516192021
22
23

Control

INIT
NOOP
WR
RD
ISEL
OSEL
OE
FE

Initialize
No Operation
Control Preload
Read Control
Input Data Select
Output Select
Output Enable
Flag Enable
Control Params
Test Pin

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

60
61
66
64
59
58
3
62
3231 302928272524
63

CTRL7-0
DNR

-

I

Do Not Connect

Ordering Information
Product
Number
TMC2311R1C
TMC2311 R1 C1
TMC2311R1C2

Data
Rate MHz

Temperature Range

Screening

Package

Package
Marking

13.5
14.5
17.8

STD-TA = OOC to 700C
STD-TA = OOC to 700C
STD-TA = OOC to 700C

Commercial
Commercial
Commercial

68 Pin PLCC
68 Pin PLCC
68 Pin PLCC

2311R1C
2311R1C1
2311R1C2

40G06753 Rev B 8193

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-317

TMC2311

3-318

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TMC2330
TMC2330
CMOS Coordinate Transformer
16 x 16 Bit, 25 MOPS

Description

•

The TMC2330 VLSI circuit converts bidirectionally
between Cartesian (real and imaginary) and Polar
(magnitude and phase) coordinates at up to 25 MOPS
(Million Operations Per Second).

•
•

1S-bit user-selectable two's complement or sign-andmagnitude rectangular data formats
Input register clock enables and asynchronous output
enables simplify interfacing
User-configurable phase accumulator for waveform
synthesis and amplitude, frequency, or phase
modulation
Magnitude output data overflow flag (in Polar-toRectangular mode)
Low power consumption CMOS process
Single +5V power supply
Available in a 120-pin plastic pin grid array package
Available in a 132-leaded CERQUAD

In its Rectangular-to-Polar mode, the TMC2330 can
extract phase and magnitude information or backward
"map" from a rectangular raster display to a radial (e.g.,
range-and-azimuth) data set.

•

The Polar-to-Rectangular mode executes direct digital
waveform synthesiS and modulation. With its 32-bit phase
accumulator, the chip can generate and frequency or
phase-modulate quadrature sinusoidal waveforms with a
frequency resolution of O.OOS Hz at a 25 MHz clock rate.
The TMC2330 greatly simplifies real-time image-space
conversion between the radially-generated image scan
data found in radar, sonar, and medical imaging systems,
and raster-oriented display formats.

Applications

All input and output data ports are registered, and a new
transformed data word pair is available at the output
every 40 ns. The user-configurable phase accumulator
structure, input clock enables, and asynchronous threestate output bus enables simplify interfacing. All signals
are TIL compatible.
Fabricated in Raytheon Semiconductor's OMICRON-CTM
one-micron CMOS process, the TMC2330 operates at up
to the 25 MHz maximum clock rate over the full
commercial (0 to 70"C) temperature and supply voltage
ranges, and is available in a low-cost 120-pin plastic pin
grid array package. The MIL-STO-883C version, the
TMC2330L5V, is housed in a ceramic chip carrier and is
specified over the full extended (-55 to 125°C) case
temperature range.

Features
•
•

•
•
•
•
•
•

Scan conversion (phased array to raster)
Vector magnitude estimation
Range and bearing derivation
Spectral analysis
Digital waveform synthesis, including quadrature
functions
Digital modulation and demodulation

TMC2330 Logic Symbol
ENXR
XRIN (15-0)
ENVP (1,0)

TMC2330
DATA OUTPUTS
OERX

VPIN{3H)

RXOUT (15. 0)

ACC{1,0)

PVOUT (15. 0)

TCXV

Rectangular-to-Polar or Polar-to-Rectangular
conversion at guaranteed 25 MOPS pipelined
throughput rate
Polar data: 16-bit magnitude, 32-bit inputl1S-bit
output phase

For More Information calI1.aoo-722-7074.

•
•
•
•

OVF
RTP

21261A

ClK

Raytheon Semiconductor

3-319

I
•
.

TMC2330
Functional Block Diagram
ENXR

TCXY

~--..

RTP>--.....

OERX>---a.
RXOUT (15.0)

OVF

PYOUT (15.0)

Functional Description
General Information
The TMC2330 converts between Rectangular (Cartesianl
and Polar (Phase and Magnitudel coordinate data word
pairs. The user selects the numeric format and transformation to be performed (Rectangular -To-Polar or PolarTo-Rectangular!. and the operation is performed on the
data presented to the inputs on the next clock. The
transformed result is then available at the outputs 22
clock cycles later, with new output data available every
40ns. All input and output data ports are registered, with
input clock enables and asynchronous high-impedance
output enables to simplify connections to system buses.
When executing a Rectangular-To-Polar conversion, the
input ports accept 16-bit Rectangular coordinate words,
and the output ports generate 16-bit magnitude and
3-320

21262A

16-bit phase data. The user selects either two's complement or sign-and-magnitude Cartesian data format. Polar
magnitude data are always in magnitude format only.
Since the phase angle word is modulo 27l", It may be
regarded as either unsigned or two's complement format
(Tables 1 and 21.
In Polar-To-Rectangular mode, the input ports accept
16-bit Polar magnitude and 32-bit phase data, and the
output ports produce 16-bit Rectangular data words.
Again, the user selects between two's complement or
sign-and-magnitude Cartesian data format. The dual.
32-bit phase accumulator input registers are useful In
signal synthesis applications, storing high-accuracy
(O.o06Hz at the maximum clock ratel phase Increment
values with minimal accumulation error. This allows the
TMC2330 to generate precision quadrature waveforms
unattended, once the accumulator has been enabled.
The flexible input phase accumulator structure supports

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2330
General Information (cont.)
frequency or phase modulation, as determined by the
input register clock enable ENYP1 0 and accumulator
control word ACC1 o. The 16 MSBs (Most Significant
Bits) of phase data' are used in the transformation itself.

current clock when ENXR is HIGH. When
ENXR is lOW, the value stored in the
register remains unchanged.
ENYP1,0

Signal Definitions
Power
VOO, GND

The TMC2330 operates from a single + 5V
supply. All power and ground pins must be
connected.

Clock
ClK

XRIN 15-0

XRIN 15-0 is the registered Cartesian
X-coordinate or Polar Magnitude (Radius)
16-bit input data port. XRIN 15 is the MSB.

YPIN31-0

YPIN31-0 is the registered Cartesian
V-coordinate or Polar Phase angle 32-bit
input data port. The input phase accumulators are fed through this port in conjunction with the input enable select ENYP1 o.
When RTP is HIGH (Rectangular-To-Polar!,
the input accumulators are normally not
used. The 16 MSBs of YPIN are the input
port, and the lower 16 bits become "don't
cares" if ACC=OO. YPIN31 is the MSB.

RXOUT 15-0 RXOUT 15-0 is the registered Polar Magnitude (Radius) or X-coordinate 16-bit output
data port. This output is forced into the
high-impedance state when OERX = HIGH.
RXOUT 15 is the MSB.
PYOUT15-0 PYOUT 15-0 is the registered Polar Phase
angle or Cartesian V-coordinate 16-bit
output data port. This output is forced
to the high-impedance state when
OEPY=HIGH. PYOUT15 is the MSB.

Controls
ENXR

ENVP1.O

Instruction

00
01
10
11

No registers enabled, current data held
M register input enabled, C data held
C register input enabled, M data held
M register set to 0, C register input enabled

The TMC2330 operates from a single clock.
All enabled registers are strobed on the
rising edge of ClK, which is the reference
for all timing specifications.

InputslOutputs

The value presented to the input port XRIN
is latched into the input registers on the

For More Information calI1-S00-722-7074.

The value presented to the YPIN input port
is latched into the phase accumulator input
registers on the current clock, as determined by the control inputs ENYP 1 0, as
shown below:
'

I

where C is the Carrier register and M is
the Modulation register, and 0 = lOW,
1= HIGH. See the Functional Block
Diagram.
RTP

This registered input selects the current
transformation mode of the device. When
RTP is HIGH, the TMC2330 executes a
Rectangular -To-Polar conversion. When RTP
is lOW, a Polar -To-Rectangular conversion
will be performed. The input and output
ports are then configured to handle data in
the appropriate coordinate system. This is a
static input. See the Timing Diagram.

ACC1,0

In applications utilizing the TMC2330 to
perform waveform synthesis and modulation
in the Polar -To-Rectangular mode (RTP =
lOW), the user determines the internal
phase Accumulator structure implemented
on the next clock by setting the accumulator control word ACC1,0, as shown below:
Configuration

ACC1,O

No accumulation performed
PM accumulator path enabled

00
01
10

FM accumulator path enabled
INonsensical) logical OR of PM and FM

11

where 0 = lOW, 1= HIGH. See the
Functional Block Diagram.
The accumulator will roll over correctly
when full-scale is exceeded, allowing the
user to perform continuous phase accumulation through 27r radians, or 360 degrees.

Raytheon Semiconductor

3-321

TMC2330
Controls (cont.)

OVF

ACC1 0
(cont.!

Note that the accumulators will also function when RTP = HIGH (Rectangular -ToPolarj, which is useful when performing
backward mapping from Cartesian to polar
coordinates. However, most applications will
require that ACC1 0 be set to 00 to avoid
accumulating the tartesian Y input data.

TCXY

The format select control sets the numeric
format of the Rectangular data, whether
input (RTP = HIGHj or output (RTP = LOWj.
This control indicates two's complement
format when TCXY = HIGH, and sign-andmagnitude when LOW. This is a static
input. See the Timing Diagram.

When RTP = LOW 1P0Iar-To-RectangularL the
Overflow Flag will go HIGH on the clock
that the magnitude of either of the current
Cartesian coordinate outputs exceeds the
maximum range. It will return LOW on the
clock that the Cartesian out -put value(sj
return to full-scale or less. See the
Applications Discussion section. Overflow
is not possible in Rectangular-To-Polar mode
(RTP=HIGHj.

OERX, OEPY Data in the output registers are available
at the outputs of the device when the
respective asynchronous Output Enables are
LOW. When OERX or OEPY is HIGH, the
respective output port(sj is in the highimpedance state.

Package Interconnections
Signal
Type

Signal
Name

Power

VOO

Supply Voltage

GNO

Ground

Clock

ClK

Inputs

Outputs

Function

L5 Package Pins

C3, E3, H3, l4, l6, l8, Lll, Fll, Ell,
Cll, C8, C6
03, E2, F2, G3, K3, l3, l7, Kll, Jll,
GIl, E12, 011, Cl0, C9, C7, C5, C4

1, 9, 21, 37, 45, 53, 67, 87, 91, 99,
112,120
5, 11, 14, 17, 29, 33, 49, 75, 83, 89,
95, 104, 108, 116, 124, 129

System Clock

F3

13

XRIN 15_0

X or Radius Data

YPIN31-0

Y or Phase Data

F12, F13, G13, G12, H13, H12, Hl1, J13,
J12, K13, K12, Ll3, Ll2, M13, M12, N13
LlO, N12, NIl, Ml0, 19, Nl0, M9, N9,
M8, N8, N7, M7, N6, M6, N5, M5, N4,
l5, M4, N3, M3, N2, M2, Nl, l2, Ml,
ll, K2, J3, Kl, J2, Jl

86, 85, 84, 82, 81, 80, 79, 78, 77, 76,
74, 73, 71, 69, 68, 66
61, 60, 59, 58, 57, 56, 55, 54, 52, 51,
50,48,47,46,44,43,42,41,40,39,
38,36,34,31,30,28,27,26,25,24,
23, 22

013,012, C13, 813, C12, A13, 812, A12,
811, All, 810, Al0, 89, A9, 88, A8
A7, A6, 86, A5, 85, A4, 84, A3, A2, 83,
AI, 82, 81, C2, Cl, 02

90,92, 93, 94, 96, 97, 100, 102, 105,
106,107,109,110,111,113,114
117,118,119,121,122,123,125,
126, 127, 130, 132, 3, 4, 6, 7, 8
63
18, 16
12
20, 19
15
88
10

RXOUT 15 _0 Radius or X Data
PYOUT 15 _0 Phase or Y Data

~-322

H5 Package Pins

Controls

ENXR
ENYP1,0
RTP
ACC1,0
TCXY
OERX
OEPY

X or Radius In Enable
Y or Phase In Enable
Conversion Select
Accumulate Control
Cartesian Data Format
Radius or X Out Enable
Phase or Y Out Enable

MIl
Gl, G2
El
H2, HI
Fl
E13
01

Flags

OVF

Overflow Flag

87

115

No Connect

NC

No Connect Pins

-

Index Pin

04

2, 32, 35, 62, 64, 65, 72, 98, 101,
103, 128, 131
-

Raytheon Semiconductor

For More Infonnation caJll-800-722-7074.

TMC2330
Static Control Inputs
The controls RTP and TCXY determine the transformation
mode and the assumed numeric format of the Rectangular data. The user must exercise caution when
changing either of these controls, as the new trans-

Table 1. Data Input/Output Formats
Port

RTP

TCXY

XRIN
XRIN
XRIN

X

YPIN
YPIN
YPIN

X

RXOUT
RXOUT
RXOUT

a

formed results will not be seen the at the outputs until
the entire internal pipe (22 clocks) has been flushed.
Thus, these controls are considered static.

Integer Format

31

30

29

16

a
rl
214
214

±20.
NS
_2 15

r2

14

0

215
NS
_2 15

214
214
214

20.
20.
20.

2-16

2-17

2-31

Format
U
S
T
(x7r)T/U

213
213

S
T
NS
_2 15

1
X

215

a
a

PYOUT
PYOUT
PYOUT

Bit#
15

NS
_2 15

±20.

X

214
214
214

20.
20.
20.

S
T
U

214
214
2-1

20.
20.
2-15 (x7r)T/U

S
T

Table 2. Data Input/Output Formats - Fractional Format
Port

RTP

TCXY

XRIN
XRIN
XRIN

a

X

YPIN
YPIN
YPIN

X

RXOUT
RXOUT
RXOUT

31

30

29

16

2-1
2-1
2-1

±20.
NS.
_20

2-2
2-2
r 2

a
a

Notes:

2-1
2-1
2- 1

r
r

2- 16

r 17

r 31

S

2-15

T
(x7r)T/U

rl
rl
2- 1

2-15
2-15
2-15

NS.
_20.

2-1
rl
2- 1

2-15
2-15
2-15 (x7r)T/U

1.
2.

NS denotes negative sign, i.e., '1' negates the number.

1=Two's Complement

3.

± 20 denotes two's complement sign or. highest magni-

S= Signed Magnitude
U=Unsigned

6.

S
T
U

S
T

Formats:

r.adians, hence

5. If ACC = 00, YPIN 115-01 ar.e "don't cares:'

HEX

U

FFFF
--

65535

8001
8000
7FFF

32769
32768
32767

- 32767
-32768
32767

0
32767

--

--

--

--

0001
0000

For More Information call 1-800-722-7074.

U

15

NS.
-20.
20.

+20.

"II"

15

S

- 215 denotes two's complement sign bit.

4. All phase angles ar.e in ter.ms of
notation "X7r:'

Format

0

T

1
X

tude bit ~ since phase angles are modulo 21r and
phase accumulator. is modulo 232 , this bit may be
regarded as + 7r or - 7r.

14

NS.
-20.

20.

1
X

PYOUT
PYOUT
PYOUT

Bit#
15

Raytheon Semiconductor

T

--

1
0

S

-1
- -

1

0

- 32767
--1

1
0

3-323

I

TMC2330
Figure 1. Timing Diagram - No Accumulation

ClK

I

--Itsf.-

RTP, TCXV t'XXXXXX'7nIM'l:"Jt'"ri-.:..----'--

I I

I

- - - - - -

------

XXXXXXX}.. @.. @..
00

ACC(l,O)

00

--Itsl tH f.ENXR, ENVP (1,0)

XRIN (15.0)' VPIN (31 .0)

xx

RXOUT (15,0),1 PVOUT (15-0)

~tHO

I(A)

XX

1(8)

I I
Note: 1. OERX, OEPY -LOW

21263A

Figure 2. Timing Diagram - Phase Modulation
22

RTp,TCXV

23

24

25

LS1.Jl..JLS

ClK

XX

~-------------------------ACC (1,0)

XXX)()(}", 00 tl. 01

XX 01 XX 01 XX 01 XX 01 XX

XRINXX~
ENVP(l,O) XX 10 XX 01 XX 01 XX 01 XX 01 XX 01 XX 01 XX

PXOUT,
PVOUT
Notes: 1.
2.
3.
4.
5.

OERX, OEPY - LOW.
Carrier C and amplitude Rloaded on elK O.
Modulation values I, J, K, L, ... loaded on eLK 1, eLK 2, etc.
Output corresponding to modulation loaded at eLK i emerged too after eLK i + 21.
To modulate amplnude, varyXRIN with ENXR '1.

21264A

3-324

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2330
Figure 3. Equivalent Input Circuit

Figure 4. Equivalent Output Circuit

n SUBSTRATE

nsuBsTRA1T

01

01

p+

p+

CONTROL
INPUT
1KO

n+

n+

I

02
02
pWELL

pWELL
GNO
21120A

21121A

Figure 5. Transition Levels for Three-State Measurements
r---~----------~I

lENA

o.sv
THREE·STATE
OUTPUTS

____+-...--

HIGH IMPEDANCE

O.SV

21265A

Absolute maximum ratings (beyond which the device may be damaged) 1
Supply Voltage ......................................................................................................................................................................................... - 0.5 to + 7.0V
Input Voltage .................................................................................................................................................................................. - 0.5 to (VOO + 0.51V
Output Voltage
Applied voltage .................................................................................................................................................... - 0.5 to (VOO + 0.51V 2
Forced current .............................................................................................................................................................. - 6.0 to 6.0mA 3.4
Short-circuit duration (single output in HIGH state to groundl ......................................................................................... 1 Second
Temperature
Operating, case ........................................................................................................................
-60 to + 130°C
junction ........................................................................................................................................................................... 175°C
Lead, soldering (10 secondsl .......................................................................................................................................................... 300°C
Storage ............................................................................................................................................................................ - 65 to + 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-325

TMC2330
Operating conditions
Temperature Range
Parameter
VDD

Supply Voltage

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

10L
IOH

Output Current. Logic LOW
Output Current. Logic HIGH

tCY

Cycle Time

tpWL

Test Conditions

4.75

2.0

VOO~Min

ts

Input Setup Time
Input Hold Time

TA
TC

Ambient Temperature, Still Air
Case Temperature

5.5

V

0.8

V
V

8.0
-4.0

mA
mA

TMC2330-1

50
40

55
45

ns
ns

VOD~Min

10

11

ns
ns
ns
ns

8
8
6

8
8
6

TMC2330-1

12
10
1

13
11
2

TMC2330-1

1

VOO~Min

TMC2330-1

tH

Units

2.0
8.0
-4.0

TMC2330-1
Clock Pulse Width, HIGH

4.5

5.25
0.8

Clock Pulse Width, LOW

tpWH

Extended
Min
Max

Standard
Min
Max

0

ns
ns
ns
ns

2
70
-55

°c
°c

125

Electrical characteristics within specified operating conditions 1
Temperature Range
Parameter
IODO Supply Current, Ouiescent
IODU Supply Current, Unloaded

VDO~Max, VIN~OV

IlL
IIH

Input Current. Logic LOW
Input Current, Logic HIGH

VOO~Max, VIN~OV

VOL
VOH

Output Voltage, Logic LOW
Output Voltage, Logic HIGH

VOO ~ Min, 10L ~ Max
VOO ~ Min, 10H ~ Max

IOZL
IOZH
lOS

Hi-Z Output Leakage Current, Output LOW
Hi-Z Output Leakage Current. Output HIGH
Short-Circuit Output Current

VOD~Max, VIN~OV

CI
Co

Input Capacitance
Output Capacitance

TA~25°C, f~lMHz
TA~25°C, f~lMHz

Note:

3-326

Test Conditions

Standard
Min
Max

Extended
Min
Max

10

10

VOO ~ Max, f~ 20MHz
OERX and OEPY ~ VOO

VOO~Max, VIN~VOO

VOO~Max,

Output HIGH, one pin to
ground, one second duration max.

160

160

mA

-10
10

p.A
p.A

0.4

-20

mA

-10
10
2.4

VOO~Max, VIN~VOO

Units

0.4
2.4

-40
40
-100

V
V

-40
40
-100

p.A
p.A
p.A

10

10

pF

10

10

pF

-20

1. Actual test conditions may vary from those shown, but specified operation is guaranteed.

Raytheon Semiconductor

For More Information call 1-800-722·7074.

TMC2330
Switching characteristics within specified operating conditions
Temperature Range
Parameter

Standard
Min
Max

Test Conditions

Extended
Max
Min

Units

VDD = Min, CLOAD = 40pF
TMC2330-1

22
20

25
23

ns
ns

Output Hold Time

VDD = Max, CLOAD = 40pF
TMC2330-1

4
4

4
4

ns
ns

tENA

Output Enable Delay

lOIS

Output Disable Delay

VDD = Min, CLOAD = 40pF
TMC2330-1
VDD = Min, CLOAD = 40pF
TMC2330-1

13
12
14
13

17
15
14
13

ns
ns
ns
ns

tD

Dutput Delay

tHO

Applications Discussion
Numeric Overflow
Because the TMC2330 accommodates 16-bit unsigned
radii and 16-bit signed Cartesian coordinates, Polar -ToRectangular conversions can overflow for incoming radii
greater than 32767 = 7FFFh and will overflow for all
incoming radii greater than 46341 = B505h. lin signed
magnitude mode, a radius of 46340 = B504h will also
overflow at all angles.) The regions of overflow and of
correct conversion are illustrated in Figure 6.

In two's complement mode, the number system's asymmetry complicates the overflow conditions slightly. An
input vector with an X component of - 32768 = 8000h
will not overflow, whereas one with an X component of
+ 32768 will. Table 3 summarizes several simple cases
of overflow and near-overflow.

Numeric Underflow

In signed magnitude mode, overflows are circularly
symmetrical - if a given radius overflows at an angle
P, it will also overflow at the angles 1l" - P, 1l" + P, and
- P. This is because - X will overflow if and only if X
overflows, and - Y will overflow if and only if Y
overflows.

In RTP=l IRectangular-To-Polar model. if XRIN=YPIN=
0, the angle is undefined. Under these conditions, the
TMC2330 will output the expected radius of 0 IRXOUT=
0000) and an angle of 1.744 radians IPYOUT=4707).
This angle is an artifact of the CORDie algorithm and is
not flagged as an error, since the angle of any 0 length
vector is arbitrary.

Table 3a. X-Dimensional Marginal Overflows

Table 3b. Maximal Overflow (Radius In =65535)

TC YPIN

TC YPIN

0000=0
8000=11"
1 0000=0
1 8000=11"

OV RXOUT

CORRECT X

1 0000= +0
1 8000= -0
8000 = - 32768
8000 = - 32768

+32768
-32768
+32768
-32768

In all cases, RTP = DIPolar-To-Rectangular mode) and
XRIN = 8000 lincoming radius = 32768).

For More Information call 1-800·722·7074.

0
0
1
1

0000=0
8000=11"
0000=0
8000=11"

OV RXOUT
1
1
1
1

7FFF = + 32767
FFFF = - 32767
FFFF= -1
0001= +1

CORRECT X
+65535
-65535
+65535
- 65535

In all cases, RTP = DIPolar -To-Rectangular mode) and
XRIN = 7FFF !incoming radius = 65535, which will always
overflow).

Raytheon Semiconductor

3·327

I

TMC2330
Figure 6. First Quadrant Coordinate Relationships
7r

/2

65535-r---

X' R(cos e)
Y'R(sin e)

32767-+-=:::::-------,

and
R. ~X2+ y2
e·tan· t (Y/X)

1
y

If R<32768, overtlow will not occur (region A).
If R> 32767, overflow will occur (region C) nIXI > 32767 or IYI > 32767.
If R>32767, overtlow will not occur (region B) if IXI <32768 and IYI < 32768.

x---+.

65535

32767

21266A

Performing Scan Conversion with the TMC2330
Medical Imaging Systems such as Ultrasound, MRI. and
PET, and phased array Radar and Sonar systems generate radial-format coordinates (range or distance, and
bearing) which must be converted into raster-scan format
for further processing and display. Utilizing the TRW

TMC2301 Image Resampling Sequencer, a minimum
chipcount Scan Converter can be implemented which
utilizes the trigonometric translation performed by the
TMC2330 to backwards-map from a Cartesian coordinate
set into the Polar source image buffer address space.

Figure 7. Block Diagram of Scan Converter Circuit Utilizing TMC2330 and TMC2301 Image Resampling
Sequencer

I SADR

I

x
Y

SADR

TMC2330
COORDINATE
TRANSFORMER

e.
e

SOURCE
IMAGE
BUFFER

R

DATA OUT

II

~

(2) TMC230t OR
(2) TMC2302 fMAGE
RESAMPLING SEQUENCERS

TADR

U
TADR

~

V

(4) TMC2011
DELAY
REGISTER

v.

~

1\

TWR

TMC2208 MULTIPlIER·ACCUMULATOR
OR
TMC2246 PIXEL INTERPOLATOR

II

DATAfN
TARGET
IMAGE
BUFFER

21267A

3-328

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2330
As shown in Figure 7, the TMC2330 transforms the
Cartesian source image addresses from the TMC2301
directly to vector distance and angle coordinates, while
the TMC2301 writes the resulting resampled pixel values
into the target memory in raster fashion. Note that the
ability to perform this spatial transformation in either
direction gives the user the freedom to process images
in either coordinate space, with little restriction. Image
manipulation such as zooms or tilts can easily be
included in the transformation by programming the
desired image manipulation into the TMC2301 's
transformation parameter registers.
Statistical Evaluation of Double Conversion

In this empirical test, 10,000 random Cartesian vectors
were converted to and from polar format by the
TMC2330. The resulting Cartesian pairs were then
compared against the original ones. The unrestricted data
base represents uniform sampling over a square bounded
by -32769

KB (9· 0)

>

10

10~
10

KC(9·0)

f

A(11-O)

DATA
INPUTS

">
">

B(11 ·0)

>

C(11· 0)

>

7
7

~
v

12

4

,12

~

".-

DATA
CASCADE
OUTPUT INTERFACE

~~

XC (11·0) =X(11·0)1 CASIN (15·4)

YC (11·8) =Y(11· 8) 1CASIN (3·0)

4
Y(7·4)

= Y(7·4)

4
YC (3 • 0) = Y(3-0) 1CASOUT (3·0)
12

,12 "

12

For More Information call 1-800-722-7074.

~

@@@
@@@
@@@

A

"
v

ZC (11· 0) = Z(11·0) 1CASOUT (15·4)

9· MULTIPLIER ARRAY

~
21280A

V

Raytheon Semiconductor

3-335

I

TMC2250
Features
• Four User-Selectable Filtering And Transformation
Functions:
Triple Dot Product (3 x 31 Matrix Multiply
Cascadeable 9-Tap Systolic FI R Filter
Cascadeable 3 x 3-Pixel Image Convolver
Cascadeable 4 x 2-Pixel Image Convolver

and 111. the cascade ports assume 12-bit integer, 4-bit
fractional two's complement data on both input and
output. The coefficient input ports (KA, KB, KCl are
always 1O-bit two's complement fractional. Table 1
details the bit weighting of the input and output data in
all configurations.

• 40MHz (25nsl Pipelined Throughput
• 12 -Bit Input And Output Data, 1O-Bit Coefficients
• 16-Bit Cascade Input And Output Ports In All Filter
Modes
• Onboard Coefficient Storage, With Three-Cycle
Updating Of All Nine Coefficients

Operating Modes

Applications
•
•
•
•
•
•
•

Image Filtering And Manipulation
Video Effects Generation
Video Standards Conversion And Encoding/Decoding
Three-Dimensional Image Manipulation
Medical Image Processing
Edge Detection For Object Recognition
FIR Filtering For Communications Systems

Functional Description
General Information
The TMC2250 is a nine-multiplier array with the internal
bus structure and summing adders needed to implement
a 3 x 3 matrix multiplier (triple dot productl or cascadeable 9-tap FIR filter, 3 x 3-pixel convolver, or 4 x 2-pixel
convolver, all in one monolithic circuit. With a 30MHz
guaranteed maximum clock rate, this device offers video
and imaging system designers a single-chip solution to
numerous common image and signal-processing problems.
The three data input ports (A, B, Cl accept 12-bit two's
complement integer data, which is also the format for
the output ports (X, y. Zl in the matrix multiply mode
(Mode 001. In the filter configurations (Modes 01, 10,

3-336

The TMC2250 can implement four different digital filter
architectures. Upon selection of the desired function by
the user (MODE1-oL the device reconfigures its internal
data paths and input and output buses appropriately. The
output ports (XC, YC, and ZCl are configured in all filter
modes as 16-bit Cascade In and Cascade Out ports so
that multiple devices can be connected to build larger
filters. These modes are described individually below. The
110 pin-function configurations for all four modes are
shown in Table 1.

Definitions
The calculations performed by the TMC2250 in each
mode are also shown below, utilizing the following
notation:
A(1L B(5L
C(2L
CASIN(3j

Indicates the data word presented to that
input port during the specified clock rising
edge (xl. Applies to all input ports A11-0,
B11-0, C11-0, and CASIN15-0·

KA1(1L
KB3(41

Indicates coefficient data stored in the
specified one of the nine onboard coefficient registers KA 1 through KC3, as shown
in the block diagram for that mode, input
during or before the specified clock rising
edge (xl.

X(11, Y(4L
Z(61,
CASOUT(61

Indicates data available at that output port
too after the specified clock rising edge
(xl. Applies to all output ports X11-0,
Y11-0, Z11-0, and CASOUT 15-0·

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TMC2250
Table 1. Data Port Formatting by Mode
Inputs
Mode

Al1-0

B11-0

Inputs/Outputs

Cl1 _0

KAg_O

KBg_O

KCg_O

KBg_O

XC 11 _0

Outputs

YC 11 -8

YC 3-0

Y7-4

ZC 11_0

00

A11-0

B11-0

C11-0

KAg_O

KCg_O

X11-0

Y7-4

Y3-0

Z11-0

01

A11-0

All-0

NC

KAg_O

KBg_O

KCg_O

CASIN 15 _4

CASIN 3_0

NC

CASOUT 3_0

CASOUT 15 _4

10

A11-0

B11-0

C11-0

KAg_O

KBg_O

KCg_O

CASIN15_4

CASIN 3_0

NC

CASOUT 3_0

CASOUT 15 _4

11

A11-0

B11-0

NC

KAg_O

KBg_O

KCg_O

CASIN 15 _4

CASIN3_0

NC

CASOUT3_0

CASOUT 15 _4

Y11-S

Numeric Format

Data Overflow

Table 2 shows the binary weightings of the input and
output ports of the TMC2250. Although the internal
sums of products could grow to 23 bits, in the matrix
multiply mode (Mode 00) the outputs X, Y, and Z are
truncated to yield 12 -bit integer words. Thus the output
format is identical to the input data format. In the filter
configurations (Modes 01, 10, and 11) the cascade
output is always half-lSB rounded to 16 bits, specifically
12 integer bits and 4 fractional guard bits, with no
overflow "headroom:' The user is of course free to halflSB round the output word to any size less than 16 bits
by forcing a 1 into the bit position of the cascade input
immediately below the desired lSB. In all modes, bit
weighting is easily adjusted if desired by applying the
same scaling correction factor to both input and output
data words. If the coefficients are rescaled, the relative
weightings of the CASIN and CASOUT ports will differ
accordingly.

As shown in Table 2, the TMC2250's matched input and
output data formats accommodate 0 dB (unity) gain.
Therefore, the user must be aware of input conditions
that could lead to numeric overflow. Maximum input
data and coefficient word sizes must be taken into
account with the specific algorithm performed to ensure
that no overflow occurs.

Signal Definitions
Power
VOO, GNO

The TMC2250 operates from a single + 5V
supply. All pins must be connected.

Clock
ClK

The TMC2250 operates from a single
system clock input. All timing specifications
are referenced to the rising edge of clock.

Table 2. Bit Weightings For Input and Output Data Words
Bit Weights

211 210

29

28

27

26

25

24

23

22

21

20

Ig

IS

17

16

15

14

13

12

11

10

2-1 2-2 2-3 2-4 2-5 2-6 2-7 2- 8 2-9

Inputs
All Modes
Data A, B, C

-111

110

Coefficients
KA,KB,KC
Modes 01,10,11
CASIN
Internal Sum

-Kg

KS

K7

K6

K5

CI6

CI5

CI 4

CI 3

CI2

CI,

CIO

X20 X,g X,S X17 X'6 X'5 X14 X,3 X,2 X'l

X1Q

Xg

Xs

X7

X6

X5

0,

00

-CI'5 CI'4 CI'3 CI'2 CI11 CI1Q

Cig

CiS

CI7

K4

K3

K2

Kl

KO

X4

X3

X2

X,

Xo

Outputs
Mode 00
X, V,Z

-0"

010

Og

Os

07

06

05

04

03

02

Modes 01,10, l'
CASOUT
-CO'5 CO'4 CO,3 CO'2 CO" COlO COg COS C07 C06 C05 C0 4
Note:

C03 C02 CO, COO

1. A minus sign indicates a two's complement sign bit.

For More Information call 1-800-722-7074,

Raytheon Semiconductor

3-337

I

TMC2250
3 x 3 Matrix Multiplier (Mode 00)
outputs five clock cycles after the input data are
latched, and three new data words half-LSB rounded
to 12 bits are then available every clock cycle.

This mode utilizes all six input and output ports in
the basic configuration to realize a "triple dot
product," in which each output is the sum of all
three input words in that column multiplied by the
appropriate stored coefficients. The three
corresponding sums of products are available at the

X(5) =A(l )KA 1(1) + B(1)KB1(1) + C(l)KCl (1)
Y(5) =A(1)KA2(1) + B(1)KB2(1) + C(1)KC2(1)
Z(5) =A(1)KA3(1) + B(1)KB3(1) + C(1)KC3(1)

Figure 1. 3 x 3 Matrix Multiplier Impulse Response (Mode 00)

ClK

CWE

KA, KB, KC

DATAINA,B,C

MODE CONTROL

X XX
X XX
01

10

KJ

K_2

0

&
XX

0

XX
XX

11

\.

K_3

X

AX X\
1.0

00

0

00

xx

XOUT

YOUT

KA3 + KB3 + KC3

/.

ZOUT

3-338

Raytheon Semiconductor

X

21282A

For More Information call 1-800-722-7074.

TMC2250
Figure 2. 3 x 3 Matrix Multiplier Configuration (Mode 00)

A

KA

I

B

KB

C

KC

x

For More Information call 1-800-722-7074.

y

Raytheon Semiconductor

21281A

3-339

TMC2250
9-Tap FIR Filter (Mode 01)

The architecture for this configuration is shown in Figure
4. The user loads the desired coefficient set, presents
input data to ports A and B simultaneously (most applications will wire the A and B inputs together). and
receives the resulting 9-sample response, half-LSB
rounded to 16 bits, 5 to 13 clock cycles later. A new
output data word is available every clock cycle. The
figure shows that the input data are automatically rightshifted one location through the row of multiplier input

registers on every clock in anticipation of a new input
data word.
CASOUT(13) =A(9)KA3(9) + A(8)KA218) + AI7)KA 1(7)
+ B(6)KB3(9) + B(5)KB2(8) + BI4)KBlI7)
+ B(3)KC3(9) + B(2)KC2(8) + B(1)KC1 (7)
+CASIN(10)
Latency: Impulse in to center of 9-tap response =9
registers. Cascade In to Cascade Out = 4 registers.

Figure 3. 9-Tap FIR Filter Impulse Response (Mode 01)
11

12

13

14

15

16

17

CLK

CWE

X01Xl0XllX

KA,KB,KC

X

KJX K_2 XK_3 X

NO'A

DATA IN A, B

MODE CONTROL

X

01

X

CASIN

CASOUT

X KA3 X KA2 X KAI X KB3 X KB2 X KBI X KC3 X KC2 X KC1 X

Q13 X
21284A

3-340

Raytheon Semiconductor

For More Information call 1-800-722·7074.

TMC2250
Figure 4. 9-Tap FIR Filter Configuration (Mode 01)

I

Z=CASOUT
(0 -15)
212B3A

For More Infonnation call 1-800-722-7074.

Raytheon Semiconductor

3-341

TMC2250
3 x 3-Pixel Convolver (Mode 10)
This filter configuration accepts a 3-pixel-square neighborhood, side-loaded three pixels at a time through input
ports A. B, and C, and multiplies the 9 most recent pixel
values by the coefficient set currently stored in the
registers. These products are summed with the data
presented to the cascade input, and a new 3-cycle
impulse response, rounded to 16 bits, is available at the
output port 5-7 clocks later, with a new output available
on every clock cycle. The input pixel data are automatically shifted one location to the right through the three
rows of multiplier input registers on every clock in

anticipation of three new input data words, effectively
sliding the convolutional window over one column in an
image plane.
CASOUT(71 =A(3IKA3(31 +A(2IKA2(21 + A(1IKA 1(11
+ B(3IKB3(31 + B(2IKB2(21 + B(1IKB1 (11
+ C(3IKC3(31 + C(2IKC2(21 + C(1IKC1 (11
+CASIN(41
Latency: Impulse in to center of 3-tap response=6
registers. Cascade In to Cascade Out = 4 registers.

Figure 5. 3 x 3-Pixel Convolver Impulse Response (Mode 10)

ClK

CWE

KA, KB, KC

X X X X
X X X X
01

10

11

KJ

K_2

K_3

DATA IN

A,B,C
MODE 10

)0(

X

01

CASIN

CASOUT

IK j =KA j + KBj + KC j

3-342

Raytheon Semiconductor

21286A

For More Information call 1-800-722-7074.

TMC2250
Figure 6. 3 x 3-Pixel Convolver Configuration (Mode 10)

Z= CASOUT
(0·15)
21285A

For More Information call 1-800-722·7074.

Raytheon Semiconductor

3-343

TMC2250
4 x 2-Pixel Cascadeable Convolver (Mode 11)
Similar to Mode 10, the 4 x 2-pixel convolver allows the
user to perform full-speed cubic convolution with only
two TMC2250 devices and the TMC2111 Pipeline Delay
Register to synchronize the cascade ports (see the
Applications Discussion sectionl. Pixel data are sideloaded into ports A and B, multiplied by the onboard
coefficients, summed with the cascade input and halfLSB rounded to 16 bits. The four-cycle impulse response
emerges at the cascade output port 5 to 8 clock cycles
later. A new output word is available on every clock
cycle. Note that Multiplier KC2 is not used in this mode

and that its stored coefficient is ignored. As shown
below, the column of input pixel data is automatically
shifted one location to the right through the two rows of
multiplier input registers on every clock in anticipation of
two new input data words, effectively sliding the
convolutional window over one column in an image
plane.
CASDUT(81 =A(41KA3(41 + A(31KA2(31 + A(21KA 1(21
+ A(11KB3(41 + B(41KB3(41 + B(31KB2(31
+ B(21KBl (21 + B(11KCl (21 + CASIN(51

Figure 7. 4 x 2-Pixel Convolver Impulse Response (Mode 11)
10

11

ClK

CWE

KA, KB, KC

00

X XX XX X
KJ

K_2

~

DATA IN A, B

MODE

K_3

XX

XX

11

CASIN

CASOUT

3-344

X X X X

Raytheon Semiconductor

21288A

For More Information call HIOO-722-7074.

TMC2250
Figure 8. 4 x 2-Pixel Convolver Configuration (Mode 11)

I

Z=CASOUT
(0-15)
21287A

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-345

TMC2250
Signal Definitions (cont.)
Inputs And Outputs

Controls
MODE1, 0

The TMC2250 will switch to the configuration selected by the user (as shown in
Table 31 on the next clock. This registered
control is usually static; however, should the
user wish to switch between modes, the
internal pipeline latencies of the device
must be taken into account. Valid data will
not be available at the outputs in the new
configuration until enough clocks in the
new mode have passed to flush the internal
registers.

A11-0,
B11-o,
C11-o

Data presented to the 1o-bit registered
data input ports A B, and C are latched
into the multiplier input registers for the
currently selected configuration (Table 31.
In all modes except Mode 00, new data
are internally right -shifted to the next filter
tap on each rising edge of ClK.

KAg_o,
KBg_o,
KC9-D

Data presented to the 10-bit registered
coefficient input ports KA, KB, and KC are
latched three at a time into the internal
coefficient storage register set indicated by
the Coefficient Write Enable CWE 1 0 on
the next clock, as shown in Table 4.

CASIN15-o

In all modes except Mode 00, the x port
and four bits of the Y output port are
reconfigured as the 16-bit registered
Cascade Input port CASIN 15-0. Data
presented to this input will be added to
the weighted sums of the data words
which were presented to the input ports
(A, B, and CI.

X11-0,
Y11-0,
Z11-o

In the matrix multiply mode, data are
available at the 12-bit registered output
ports X, Y. and Z too after every clock.
These ports are reconfigured in the
filtering modes as 16-bit Cascade Input
and Output ports.

Table 3. Configuration Mode Word
MODE1,O

Configuration Mode

00
01

3 x 3 Matrix Multiply
9-Tap One-Dimensional FIR
3 x 3-Pixel Convolver
4 x 2-Pixel Convolver

10
11

Data presented to the coefficient input
ports (KA KB, and KCI will update three of
the internal coefficient storage registers, as
indicated by the simultaneous Coefficient
Write Enable select, on the next clock.
See Table 4 and the Functional Block
Diagram.

Table 4. Coefficient Write Enable Word
Coefficient Set Selected
00
01
10
11

Hold all registers
Update KA1, KB1, KC1
Update KA2, KB2, KC2
Update KA3, KB3, KC3

Table 5. Coefficient Input Ports

3-346

Input Port

Registers Available

KA
KB
KC

KA1, KA2, KA3
KBl, KB2, KB3
KC1, KC2, KC3

NOTE: The output ports X, Y, Z and CASOUT, and the
input port CASIN are internally reconfigured by the
device as required for each mode of the device. The
multiple-function pins have names which are combinations of these titles, as appropriate.
CASOUT 15-0 In all modes except Mode 00, the Z port
and four bits of the Y output port are
reconfigured as the 16-bit registered
Cascade Output port CASOUT 15-0.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2250
Package Interconnections
Signal
Type

Signal
Name

Power

VOO
GNO

Supply Voltage
Ground

F3, H3, L7, C8, C4
E3, G3, J3, L4, L6, Hll, C7, C5

Clock

CLK

System Clock

011

Controls

MOOEl,O
CWE1,0

Mode Control
Coefficient Write Enable

85, A4
J12, J13

Input/Output

A11-0
811-0
C11 -0
KA9_0
K8 9_0
KC9_0
XC11_O
YC l1 -8
Y7-4
YC3-0
ZC 11 _0

Data Input A
Data Input 8
Data Input C
Coefficient Input A1, A2, A3
Coefficient Input 81, 82, 83
Coefficient Input Cl, C2, C3
CASIN 15 _4/Output X
CASIN3_0/0utput Y11-0
Output Y7-4 Only
CASOUT3_0/0utput Y3-0
CASOUT 15_4/Output Zl1-0

Ell, 013, E12, E13, Fll, F12, F13, G13, Gll, G12, H13, H12
810, All, 811, Cl0, A12, 812, Cll, A13, C12, 813, C13, 012
A5, C6, 86, A6, A7, 87, A8, 88, A9, 89, A10, C9
K13, Jll, K12, Ll3, L12, Kll, M13, M12, Lll, N13
Mll, Ll0, N12, N11, Ml0, L9, Nl0, M9, N9, L8
M8, N8, N7, M7, N6, M6, N5, M5, N4, L5
84, A3, A2, 83, Al, C3, 82, 81, 03, C2, Cl, 02
01, E2, El, F2
Fl, G2, Gl, Hl
Kl, J2, Jl, H2
M4, N3, M3, N2, M2, L3, Nl, L2, K3, Ml, Ll, K2

Function

H5 Package Pins

Figure 9. Input/Output Timing Diagram

~
1

I

I 2

I

ClK

CWE

KA, KB, KC
X,V,Z
CASOUT
21289A

Figure 10. Equivalent Input Circuit

Figure 11. Equivalent Output Circuit

voo
n SUBSTRATE

nsuBsTRA1T

01

p

p+

01
p+

CONTROLo__~__JV

INPUT

1KO

n+

n+

03
pWELL

02

02

pWELL

)-______-+-==---1
-=

GNO

For More Information call 1-800-722-7074.

21122A

Raytheon Semiconductor

P WELL
21121A

3-347

I

TMC2250
Absolute maximum ratings Ibeyond which the device may be damagedl 1
Supply Voltage ........................................................................................................................................................................................ - 0.5 to + 7.0V
Input Voltage ................................................................................................................................................................................. - 0.5 to (Voo + 5.0)V
Output
Applied voltage ................................................................................................................................................... - 0.5 to 1Voo + 5.0)V 2
Forced current ............................................................................................................................................................ - 6.0 to 6.0mA 3.4
Short-circuit duration (single output in HIGH state to ground) ......................................................................................... 1 Second

Temperature
Operating, case .............................................................................................................................................................. - 60 to + 130°C
junction ........................................................................................................................................................................... 175°C
lead, soldering (10 seconds) ......................................................................................................................................................... 300°C
Storage ................................................................................................................................................................................ - 65 to 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range. and measured with respect to GND.
3. forcing voltage must be limited to speCified range.
4. Current is specified as conventional current flowing into the device.

Operating conditions
Temperature Range
Parameter
Von

Supply Voltage

VIL

Input Voltage, logic lOW

VIH

ClK Only
Input Voltage, logic HIGH

IOL
IOH
tCY

Cycle Time
TMC2250
TMC2250-1
TMC2250-2

TMC2250-2
tpWH Clock Pulse Width, HIGH

tH

Input Setup Time
TMC2250
TMC2250-1
TMC2250-2
Input Hold Time
TMC2250
TMC2250-1
TMC2250-2

TA
TC

3-348

4.75

5.0

Ambient Temperature, Still Air

Max
5.25

Min
4.5

0.8
0.8
2.0

Output Current, logic lOW
Output Current, logic HIGH

tpWL Clock Pulse Width, lOW
TMC2250
TMC2250-1

ts

Min

Standard
Nom

Extended
Nom

Max

5.0

5.5

V

0.8
0.6

V
V
V

2.0
4.0
-2.0

33
27.7

4.0
-2.0

Units

rnA
rnA

33
27.7

ns
ns
ns

15
12
10

15
12

ns
ns

10

10

ns
ns

8
7
6

8
7

ns
ns

3
3
2

3
3

25

0

ns
ns
ns
ns
70

Case Temperature

-55

Raytheon Semiconductor

125

°c
°c

For More Information call 1-800-722-7074.

TMC2250
Electrical characteristics within specified operating conditions 1
Temperature Range
Parameter

Test Conditions

Supply Current, Quiescent
Supply Current, Unloaded

VOO~Max, VIN~OV

IIH
lOlL
IDiH

Input
Input
Input
Input

VOL
VO H

Output Voltage, Logic LOW
Output Voltage, Logic HIGH

VOO~Min, IOL ~4mA

lOS

Short-Circuit Output Current

VOO ~ Max, Output HIGH, one pin to
to ground, one second duration max.

CI
Co

Input Capacitance
Output Capacitance

TA~25°C, f~lMHz

IOOQ
IOOU
IlL

Notes:

Standard
Min
Max

Current,
Current.
Current,
Current.

Logic
Logic
Logic
Logic

LOW 2
HIGH 2
LOW 3
HIGH 3

Extended
Min
Max

Units

12
160

12
160

rnA
rnA

VOO~Max, VIN~OV

-10

VOO~Max, VIN~VOO

10
-40

-10
10
-40
40

/LA
/LA

VOO~Max, f~20MHz

VOO~Max, VIN~OV
VOO~Max, VIN~VOO

VOO~Min, 10H~

40

0.4

0.4
2.4

2.4

-2mA

-20

-80

-20

10

10
10

TA~25°C, f~lMHz

-80

10

/LA
/LA
V
V
rnA

pF
pF

1. Actual test conditions may vary from those shown. but guarantee operation as specified.
2. Except pins XCll-0, YCll-S.
3. Pins XCll-0. YCll-8 only.

Switching characteristics within specified operating conditions
Temperature Range
Parameter
to

tHO

Output Delay
TMC2250
TMC2250-1
TMC2250-2
Output Hold Time
TMC2250
TMC2250-1
TMC2250-2

For More Information call 1-800-722-7074.

Test Conditions

Standard
Min
Max

Extended
Max
Min

Units

VOO ~ Min, CLOAO ~ 25pF
18
17

20
18

16

ns
ns
ns

VOO~Max, CLOAO~25pF

3

3

ns

3
3

3
3

ns
ns

Raytheon Semiconductor

3-349

I

TMC2250
Performing Large-Kernel Pixel Interpolation
The Cascade Input and Output Ports of the TMC2250
allow the user to stack multiple devices to perform larger
interpolation kernels with no decrease in pixel throughput. Figure 12 illustrates a basic application utilizing
Mode 11 to realize a 4 x 4-pixel kernel, also called Cubic
Convolution. This example utilizes the TMC2011 VariableLength Shift Register to compensate for the internal
latency of each TMC2250. Alternatively, some applications may utilize RAM, FlFOs, or other methods to
store multiple-line pixel data. In these cases the user
may compensate for latency by simply offsetting the
access sequencing of the storage devices.

Figure 12. Performing Cubic Convolution with Two
TMC2250s
A >-+1c::2 - - - - - - -.. A
4X2TMC2250
B >+1c::2 - - - - - - -. . B

CASOUT

OUTPUT

21290A

Pin Assignments - 121 Pin Plastic IH51 or Ceramic IG11 Pin Grid Array
Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Al
A2
A3
A4
A5
A6
A7
AS
AS
Al0
All
A12
A13
Bl
B2

XC7
XCg
XC 10
MOOE O

B3
B4
B5
B6
B7
BS
BS
Bl0
Bll
B12
B13
Cl
C2
C3
C4

XCs
XC 11
MOOE 1
Cg
Cs

C5
C6
C7
CS
Cg
ClO
Cll
C12
C13
01
02
03
011
012
013

GNO

El
E2
E3
Ell
E12
E13
Fl
F2
F3
Fll
F12
F13
Gl
G2
G3

YCs
YClO
GNO

Gll
G12
G13
Hl
H2
H3
Hll
H12
H13
Jl
J2
J3
Jll
J12
J13

A3
A2
A4
Y4
YCo
VOO
GNO

Kl
K2
K3
Kll
K12
K13
L1
l2
l3
l4
l5
l6
l7
lS
lS

YC3
ZCo
ZC3
KA4
KA7
KAg
ZCl
ZC4
ZC 6
GNO
KCo
GNO

LlO
Lll
Ll2
L13
Ml
M2
M3
M4
M5
M6
M7
MS
MS
Ml0
Mll

KBS
KAl
KA5
KAS
ZC2
ZC7
ZCs
ZCll
KC2
KC4
KC6
KCs
KB2
KB5
KBs

M12
M13
Nl
N2
N3
N4
N5
N6
N7
NS
NS
NlO
Nll
N12
N13

KA2
KA3
ZC5
ZCs
ZClO
KC 1
KC3
KC5
KC7
KCs
KBl
KB3
KB6
KB7
KAo

Cll
Cs
C7
C5
C3
Cl
BlO
B7
B4
XC4
XC5

C4
C2
Bll
BS
B6
B2
XC 1
XC2
XC6
VOO

ClO
GNO
VOO
Co
B8
B5
B3
Bl
YCll
XCo
XC3
ClK
Bo
AlO

All
Ag
AS
Y7
YC s
VOO
A7
A6
A5
Y5
Y6
GNO

Ao
Al
YCl
YC2
GNO
KAs
CWE 1
CWEo

VOO
KBO
KB4

04 Index Pin (Unconnected)
13
12
11

10
9
8

7
6
4

©©©©©©©©©©©©©
©©©©©©©©©©©©©
©©©©©©©©©©©©©
©©©
©©©
©©©
©©©
©©©
©©©
TOP VIEW
©©©
©©©
CAVITY UP
©©©
©©©
©©©
Key
© © ©
©©©
©©©""
©©©©©©©©©©©©©
©©©©©©©©©©©©©
©©©©©©©©©©©©©

/

'\

k

/

ABCOEFGHJKlMN
21041A

3-350

Raytheon Semiconductor

For Mora Information call 1-800-722-7074.

TMC2250
Ordering Information
Product
Number

Speed
(MHz)

Temperature Range

Screening

Package

Package
Marking

TMC2250H5C
TMC2250H5C 1
TMC2250H5C 2

30
36
40

STD-TA=O°C to 70°C
STD-TA =O°C to 70°C
STD-TA=O°C to 70°C

Commercial
Commercial
Commercial

121 Pin Plastic Pin Grid Array
121 Pin Plastic Pin Grid Array
121 Pin Plastic Pin Grid Array

2250H5C
2250H5C 1
2250H5C 2

TMC2250G1V
TMC2250G1V1

30
36

MIL-TC= -55°C to 125°C
MIL-TC= -55°C to 125°C

MIL-STD-883
MIL-STD-883

121 Pin Ceramic Pin Grid Array
121 Pin Ceramic Pin Grid Array

2250G1V
2250G1V1

40G06391 Rev B 8193

For More Infonnation call HIOO-722-7074.

Raytheon Semiconductor

3-351

TMC2250

3-352

Raytheon Semiconductor

For More Information call 1-800·722·7074.

Section 3 - Standard Products

Correlators
INPUT SHIFT REGISTER
INPUT
SIGNAL

CORRELATOR
OUTPUT
STORED
REFERENCE

similarity between two digital signal streams. which is key
to pattern recognition and data synchronization
applications. All Raytheon correlators are m compatible.

Raytheon is the industry leader in correlators for high
performance communications. signal. radar and image
processing applications. Correlators measure the

Product
Description
TMC2023-1 Correlator

Size
64x1

TMC2220-1 Correlator

4x32

Clock
Rate'
(MHz)
50
35
25
20

17
TMC2221-1 Correlator

1x12B

20

17

Power'
(Watts)
0.4
0.4
0.4
0.3
0.3
0.3
0.3

Package
B2, B7, C3
B2,B7,C3
B2,B7

GB,HB
GB,HB
B6
B6

Grade
C, V,SMD
C, V,SMD
C. V,SMD
C,V
C,V
C,V
C,V

Notes
Pin compatible wilh TDC1023.
Threshold nag.
Programmable.
Optionall&Q modes.
Programmable.

Notes:
1. Guaranteed. See product specifications for test conditions.
2. C • Commercial, TA • 0"C to 70"C.
V = MIL-STD-8S3 Compliant, Tc =-55"C to 125"C.
SMD .. Available per Standardized Military Drawing, Tc = -55"C to 125"C.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-353

Section 3 - Standard Products

3-354

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2023
TMC2023
CMOS Digital Output Correlator
64-Bit, 25, 30, 35, and 50 MHz

Description

Features

The TMC2023 is a monolithic 64-bit correlator with a 7bit three-state buffered digital oulput. This device
consists of three 64-bit independently clocked shift
registers, one 64-bit reference holding latch, and a 64bit independenUy clocked digital summing network. The
device is available in versions capable of 25,30,35, and
50 MHz parallel correlation rates.

•
•
•
•
•
•
•

The 7-bit threshold register allows the user to preload a
binary number from 0 to 64. Whenever the correlation is
equal to or greater than the number in the threshold
register, the threshold flag goes HIGH.
The 64-bit shift mask register (M register) allows the
user to mask or selectively choose "no compare" bit
positions enabling total word length flexibility.
The reference word is serially shifted into the B register.
Bringing LOR HIGH parallel loads the data into the R
reference latch. This allows the user to serially preload a
new reference word into the B register while correlation
is taking place between the A register and the R latch.
The two words are continually compared bn-by-bit by
exclusive-OR circuns. Each exclusive-OR provides one
bit to the dignal summer. The output is a 7-bn word
representing the number of positions which agree at any
one time between the A register and R latch. A control
provides either true or inverted binary output formats.
Built with Raytheon Semiconductor La Jolla's onemicron double level metal OMICRONCTM low power
CMOS process, the TMC2023 is available in a 24-pin
CERDIP package and 28-contact chip carrier. The
CMOS TMC2023 is pin co/ll>8tible with the bipolar
TDC1023.

For Mora Infonnation call 1-800-722-7074.

•
•
•
•
•

25, 30, 35, and 50 MHz correlation rates
All inputs and outputs m compatible
Serial data Input, parallel correlation output
Programmable word length
IndependenUy clocked registers
Programmable threshold detection and flag output
Available in 24-pin CERDIP and 28-contact chip
carrier
Available to Standard Military Drawing (SMD)
Pin-Compatible with TDC1023
Output format flexibility
Three-state outputs
Low-power CMOS

Applications
•
•
•
•
•
•
•
•
•
•
•

Check sorting equipment
High densny recording
Bar code identification
Radar signature recognition
Video frame synchronization
Electro-optical navigation
Pattem and character recognition
Cross-oorrelation control systems
Error correction coding
Asynchronous communication
Matched filtering

Raytheon Semiconductor

3-355

TMC2023
Functional Block Diagram
eLKS

INV

AIN ----'~r----.....- - -...
AOUT

CLKA

PIPELINEO
DIGITAL
SUMMER
(3 STAGES)

lOR

ClKB
BIN --.......---I-L----.j.J
MIN ---'~...---'_r_---J...,
ClKM
1°0-6

Pin Assignments

....

.... ....
...lQ ...::E= ...c= '"= '".r.... '"z '"z
!:I !::i

a:
Q

Q

Q

Q

co

~

Q

N

N

N

VOO

1

24 ClK B

MIN

2

23 ClK M

AIN

3

22 CLKA

ClKA 26

18 NC

BIN
CLKT

4

21 lOR

ClKM 27

171°0

5

20 MO UT

CLKS

6

19 AOUT

INV

7

TS

8

18 BOUT
17 TFlG

1°6 9
105 10

16 GNO

104 11

14 101

103 12

13 102

15 100

CLKB 28

16101

VOO

1

151°2

VOO

2

141°3

MIN

3

13104

AIN

4

12105

82,8724PIN

...'"z

24 Pin CEROIP - B2. B7 Package

3-356

Q

...
z

rE'

.....

....

......'"

.
........
en

...

:2

::

>
!!

I!!

51

...
r:~.?RPIN

28 Contact Chip Carrier - C3 Package

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

TMC2023
Functional Description
General Information
The TMC2023 consists of an input section and an output
section. The input section contains the A. B, and M
registers, an R latch, XOR/AND logic and a pipelined
summer network. The output section consists of threshold,
inversion and three-state logic.

Continuous Correlation
The TMC2023 contains three 1 x 64 serial shift registers
(A, B, and M). The operation of these registers is identical
and each has its own input, output, and clock. As shown in
the Timing Diagrams, valid data is loaded into register A
(B, M) on the rising edge of ClK A (ClK B, ClK M). Data is
valid if present at the input for a setup time of at least tSSR
before and a hold time of tH after the rising clock edge.
The summing process is initiated when the comparison
result between the A register and R latch is clocked into
the summing network by a rising edge of ClK S. Typically,
ClK A and ClK S are tied together so that a new
correlation score is computed for each new alignment of
the A register and R latch. When lOR goes HIGH, the
contents of register B are copied into the R latch. With lOR
lOW, a new template may be entered serially into register
B, while parallel correlation takes place between register A
and the R latch. In the case of continuous correlation, lOR
is held HIGH so that the R latch contents continuously track
those of the B register.
The summing network consists of three pipelined stages.
Therefore, the total correlation score for a given set of
A and B register contents appears at the summer output
three elK S cycles later. Data on the output pins 100-6 is
available after an additional propagation delay, denoted
tDCOR on the Timing Diagrams.
The correlation result is compared with the contents of the
threshold register. TFlG goes HIGH if the correlation equals
or exceeds the threshold value. TFlG is valid after a delay
of tDF from the third ClK S rising edge.

Cross-Correlation
When lOR goes HIGH, the B register contents are copied
into the reference latch (R latch). This useful feature allows
correlation to take place between data in the R latch and
the A register while a new reference is being serially
clocked into the B register. If the new reference is n bits
long, it requires n rising edges of ClK to load this data into
For More Informallon call 1-800-722-7074.

the B register. For the timing diagram, n =64. lOR is set
HIGH during the final (nth) elK B cycle, so that the new
reference word is copied into the R latch. The minimum
lOW and HIGH level pulse widths for lOR are shown as
tpWl and tpWH, respectively.
After the new reference is loaded, the data to be correlated
is clocked through the A register. Typically, ClK A and ClK
S can be tied together. This allows a new correlation score
to be computed for each shift of the A register data relative
to the fixed reference word in the R latch. The digital
summer is internally partitioned into three pipelined stages.
Therefore, a correlation score for a particular alignment of
the A register data and the R latch reference appears at
the summer output three ClK S cycles later. After an
additional output delay of tDCOR, the correlation data is
valid at the output pins (100-6). If this correlation result is
equal to or exceeds the value in the threshold register,
then TFlG goes HIGH. TFlG is valid tDF after the third
rising edge of elK S.

Threshold Register Load
The timing sequence for loading the threshold (T) register
is shown in the Timing Diagrams. The T register holds the
7-bit threshold value to be compared with each correlation
result. The rising edge of elK T loads the data present on
the 100-6 pins into the T register. T flag logic is pipelined 3
stages, with the summer. The new value loaded into the
threshold register will affect the TFlG on the third ClK S
(plus an output delay tDF) following the T register load.
The output buffers must be ina high-impedance state
(disabled) when the T register is programmed from an
external source. After a delay of tDIS from the time TS
goes HIGH, the output buffers are disabled. The data pins
100-6 may then be driven externally with the new threshold
data. The data must be present for a setup time of tSCOR
before and tH after the rising edge of ClK T for correct
operation. The minimum lOW and HIGH level pulse widths
for ClK T are shown below as tpWl and tpWH,
respectively.
After TS is set lOW, there is an enable delay of tENA before
the internal correlation data is available at pins 100-6.

Invert Control Timing
Most applications will tie the INVert control HIGH or lOW
depending on system requirements. In the few situations in
which the control is used dynamically, the user must
observe special timing constraints.

Raytheon Semiconductor

3-357

I

TMC2023
Because INVERT governs logic located between the master
and slave latches of the data output register, its setup and
hold requirements differ from those of the data and other
controls. The device will respond to changes on INV
whenever CLOCK is HIGH and will ignore it when CLOCK
is lOW. To minimize the data output delay and to avoid
inducing errors, the user should observe the following
timing constraints:
1. Set INVERT to the desired state for the next output on or
before the rising edge of CLOCK. If INVERT is asserted a
few nanoseconds after the rising edge, the data output
may be similarly delayed.
2. More importantly, keep INVERT in the desired state until
after the falling edge of CLOCK, to avoid corrupting the
output data. If INVERT is changed several nanoseconds
before the falling edge of CLOCK, the data will likewise
change. If it is changed just before the falling edge, an
indeterminate output may result.

This result is complemented at the input of the AND gates
and ANDed with the mask bit (Mil resulting in:

The last step, performed in the digital summer, is to sum
the above result over all bit positions simultaneously for a
correlation at time n:

n
C(n+3l = L. [ (Ai XNOR Bj) AND Mi 1
i =n - 63
where i = 1, 2, 3. .. and n = correlation word length

Signal Definitions
Power
VDD, GND

Mask Register
In addition to the A and B shift references, the TMC2023
has another independently clocked register: the M, or mask
Control
register. The M register functions identically to the A and B
register, except that its parallel outputs are ANDed with
INV
the exclusive-ORed outputs from the A register and R latch.
Many uses of the TMC2023 digital correlator require
disabling the correlation between certain bit positions
(Ai and Rj) of input words A and R. While correlation data
is being clocked into the A and/or B register, a mask word
may be entered into the M register. Where no comparison
is to be made, zeroes are entered in those M register
positions. The exclusive-OR result between each bit
position is ANDed with a bit from the M register. Thus,
if a particular mask bit (Mil is zero, the output correlation
between A and B for that bit position will be disabled.
Consequently, a zero correlation is presented to the digital
summer for each masked bit position.
The Mask register is useful for changing correlation word
length and location within the registers. Where a word is
undefined or no correlation is to take place, the M register
should contain zeroes.
The M register is useful for building logic functions. Note
that for each bit Ai and Ri, the correlation logic is:
Ai + Ri

3-358

Ai Ri + Ai Ri (Ai exclusive-OR Rj)

The TMC2023 operates from a single +5V
supply. All VDD and GND pins must be
connected.

Control that inverts the 7-bit digital output.
When a HIGH level is applied to this pin, the
outputs 100-6 are logically inverted. See the
Timing Diagrams for setup and hold
requirements.

TS

The three-state control enables and disables
the output buffers. A HIGH level applied to
this pin forces outputs into the highimpedance state. This control also allows
loading of the internal threshold register.

LDR

Control that allows parallel data to be loaded
from the B register into the reference latch
for correlation. If LDR is held HIGH, the R
latch is transparent.

Clocks
ClKA
ClK M,
ClK B

Input clocks. Clock input pins for the A M,
and B registers, respectively. Each register
may be independently clocked.

ClK T

Threshold register clock. Clock input used to
load the T register.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2023
serve as parallel inputs to load the threshold
register. Data present one setup time before
ClK T goes HIGH will be latched into the
threshold register.

Digital summer clock. Clock input that allows
independent clocking of the pipelined
summer network.

ClK S

Data Inputs
MIN

Mask register input. Allows the user to
choose "no-compare" bit positions. A "0" in
any bit location will result in a no-compare
state for that location (bit position masked).
Shift register inputs to the A and B 54-bit
serial registers.

TFlG

The TFlG output goes HIGH whenever the
correlation score is equal to or greater than
the number loaded into the T register (0 to 54).

BOUT

Shift register outputs of the three 54-bit shift
register:

AOUT

B, A, and M, respectively. These outputs may
be used to

MOUT

For cascading multiple devices.

Data Outputs
100-5

Bi-directional data pins. When outputs are
enabled (TS lOW), data is a 7-bit binary
representation of the correlation between the
unmasked portions of the R latch and the A
register. 105 is the MSB. These pins also

No Connect
NC

These pins should be left unconnected.

I

Package Interconnections
Signal

Signal

Type

Name

Power

GND

Function

82, 87 Package

C3 Package

VDD

Ground
Supply Voltage

16
1

19,20
1,2

Control

INV
TS
lDR

Inverter Output
Three-State Enable
load Reference

7
8
21

9
10
25

Clocks

ClKA
ClKM
ClK B
ClKT
ClK S

A Register Clock
M Register Clock
B Register Clock
Threshold Register
Digital Summer Clock

22
23
24
5
6

26
27
28
7
8

Inputs

MIN
AIN
BIN

Mask Register
Shift Register
Shift Register

2
3
4

3
4
6

Outputs

10 6-0

Correlation Score

TFLG
BOUT
AOUT
MDUT

Threshold Flag
Shift Register B
Shift Register A
Shift Register M

9,10,11,12,
13,14,15
17
18
19
20

11,12,13,14,
15,16,17
21
22
23
24

NC

No Connect

None

5,18

No Connect

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-359

TMC2023
Figure 1. Continuous Correlation
tpWl

lOR = HIGH
TS = lOW
BIN = REFERENCE
T REGISTER PRELOAOEO

tpWH

ClKA
ClKS

10 0 - 6

-----+---'1

TFlG
FIG 1

Figure 2. Cross-Correlation

FIG 2

3-360

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2023
Figure 3. Threshold Register Loading
_1/fCLK-CLKA
CLKS
AIN

XXXX

XXXX

AN

AN+l

4NA~

TS
1=,OIS-'
100-6
OUT

XXXX

SN-4

SN-2

100-6
IN

SN

SN-l

SN+l

THRESHOLD DATA
-'SCOR_ ~'H~

.-----------------~ ~'PWL__: *-'PWH~
CLKT

-

'OF

~

X FN+l

TFlG XXXXXXXXXXXXXXXXXXXXXXXX,--_FN-_'---,X,--_FN- . J
BIN = REFERENCE

'/
NEW THRESHOLD

LOR = HIGH

Figure 4. Invert Control Timing

1

,~\
'"

Figure 5. Equivalent Input Circuit

1
-6

XXXXXXXx*..-----VA-UD

vDD
SUBSTRATE

p
CONTROL
INPUT 0 - - 4 - - 1
n

2023.5

Figure 6. Equivalent Output Circuit

Figure 7. Threshold Levels for Three-State
Measurements

voo
SUBSTRATE

TS

+---+---0 OUTPUT

'OIS

O.5V

THREE-STATE----.l--.1
OUTPUTS

HIGH IMPEDANCE

~

O.5V

20217

2023.6

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-361

I

TMC2023
Absolute maximum ratings (beyond which the device may be damaged)1
Power Supply Voltage.. .

.................................................................................................. -0.5 to +7.0V

Input Voltage ....

......................................... -0.5 to (VDD+0.5) V

Outputs
Applied Voltage 2 ..
......... -0.5 to (VDD+0.5) V
Forced Current3,4 .................................................................................................................................................................................. -3.0 to 6.0 rnA
Short Circuit Duration
(Single output in HIGH state to GND) ........................................................................................................................................ 1 second

Temperature
Operating, case .....................................................................................................................................................................-60 to +130°C
Operating, Junction ..........................................................................................................................................................................+175°C
Lead, soldering (10 seconds) ..........................................................................................................................................................+300°C
Storage ...................................................................................................................................................................................-65 to +150°C
Notes:

3-362

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current. flowing into the device.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2023
Operating conditions
Temperature Range
Standard
Parameter

Voo
tfWL

tPWH

tscOR

tSSR

tH

fCLK

VIH
VIHC
VIL
IOH
IOL
TA
TC

Power Supply Voltage
Clock Pulse Width, lOW
TMC2023
TMC2023-1, -2
TMC202J.3
Clock Pulse Width, HIGH
TMC2023
TMC2023-1, -2
TMC2023-3
Data Setup Time, Correia tor
TMC2023
TMC2023-1, -2
TMC202J.3
Data Setup Time,
Shift Register (AIN, BIN, MIN)
TMC2023
TMC2023-1, -2
TMC2023-3
Data Input Hold Time,
Correlator and Shift Register
All grades
ClK Frequency, Correlator,
Shift Register and Flag Sections
TMC2023
TMC2023-1
TMC2023-2
TMC202J.3
Input Voltage, logic HIGH
Input Voltage, logic HIGH, A,B,M,S ClKS
Input Voltage, logic LOW
Output Current, logic HIGH
Output Current, logic lOW
Ambient Temperature, Still Air
Case Temperature

For More Information call 1-800-722-7074.

Min

Nom

Max

Min

4.75

5.0

5.25

4.5

Extended
Nom
5.0

Max

Unita

5.5

Volts

15
12
8

15
14
10

ns
ns
ns

15
12
8

15
14
8

ns
ns
ns

12
10
9

14
10
10

ns
ns
ns

12
8
7

13
10
9

ns
ns
ns

0

0

ns

25
30
35
50
2.0
2.0

0

25
30
35
50
2.0
2.4

0.8
-2.0
4.0
70

Raytheon Semiconductor

-55

I

MHz
MHz
MHz
MHz
V
V

0.8
-2.0
4.0

mA
mA

125

"C
"C

V

3-363

TMC2023
Electrical Characteristics
Temperature Range

Conditions

Parameter
1000

IOOU

Power Supply Current, Quiescent
Power Supply Current, Unloaded

IIH
IlL
VOH
VOL
IOZH
IOZl
los

Input Current, Logic HIGH
Input Current, Logic LOW
Output Voltage, Logic HIGH
Output Voltage, Logic LOW
Output Leakage Current, HIGHt
Output Leakage Current, LOW1
Short Circuit Output Current

CI
Co

Input Capacitance
Output Capacitance

Note:

1.

3-364

VOO =Max, VIN =LON, TS =HIGH
VOO =Max, TS =HIGH
TMC2023, fCLK =25 MHz
TMC2023-1, fCLK =30 MHz
TMC2023-2. fCLK =35 MHz
TMC2023-3, fCLK =50 MHz
VOO =Max, VIN =VOO
Voo =Max. VIN =eN
VOO =Min, IOH =Max
VOO =Min, IOL =Max
VOO =Max, VIN =VOO
VOO =Max, VIN =GND
VOO =Max, Output HIGH, one pin
to ground, one second duration
TA =25OC, f =1 MHz
TA =25OC, f =1 MHz

Standard
Min
Max

Extended
Min
Max

Units

5

10

rnA

55
75
75
100
+10
-10

55
75
75
100
+10
-10

rnA
rnA
mA
rnA

2.4

2.4

IIA
IIA
V
V

0.4
+40
-40
-100

0.4
+40
-40
-100

IIA
IIA

10
10

10
10

pF
pF

rnA

These values are the III and IIH for the T Register.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2023
Switching Characteristics

Parameter

Temperature Range
Standard
Extended
Min
Max
Min
Max

Conditions

Output Delay. Correlator
TMC2023
TMC2023-1. -2
TMC2023-3

VDD = Min. CLOAD = 40 pF

Output Delay. shift Register
TMC2023
TMC2023-1.-2
TMC2023-3

VDD = Min. CLOAD = 40 pF

Output Delay. Flags
TMC2023
TMC2023-1. -2
TMC2023-3

VDD = Min. CLOAD = 40 pF

tHO

Output Hold Time
All grades

VDD = Min. CLOAD = 40 pF

tENA

Three-State Output Enable Delay
TMC2023
TM C2023- 1. -2
TMC2023-3
Three-State Output Disable Delay
TMC2023

VDD = Min. CLOAD = 40 pF

tDCOR

tDSR

tDF

tDIS

Units

22
19
17

22
20
18

ns
ns
ns

22
20
18

25
22
20

ns
ns
ns

20
17
15

22
19
17

ns
ns
ns

4

4

ns

20
16
15

25
20
18

ns
ns
ns

20
16
14

24
18
16

ns
ns
ns

VDD = Min. CLOAD = 40 pF

TMC2023- 1. -2
TMC2023-3

Application Notes
The TMC2023 can be cascaded to implement correlations
of more than 64 bits. Typically. all clocks are tied together
and the A. B. and M outputs of preceding stages are
connected to the respective inputs of subsequent stages.
An external summer is required to generate the composite
correlation score. Use of the T register and TFLG require
additional hardware for this configuration. The TMC2221
correlator provides 12B taps.

For More Information caJI1-800-722-7074.

When comparing a multi-bit word to a single-bit reference.
the outputs from the individual correlators must be
appropriately weighted. This weighting reflects the relative
importance of the different bit positions. Normally simple
shifts (division by 2. 4. B•... ) provide the required weighting.
The TMC2220 correlator provides 32-tap 4x1 correlation.

Raytheon Semiconductor

3-365

I

TMC2023
Figure 8. Cascading for Extended-Length Correlation
C~A-----------r------------------~------------------~

C~B---------r-i------------------~~----------------~
C~M------ll~r-t-------------~~~+--------------­

c~s ---.r.H:--±-,-----HI:f---.t--l------~+
-t AJN

~:T': -t BIN TM~
-t MIN

100 6

1 ,

AguT~_ _ _JiAJi;;;N:-'-...L.....L..~Ag;;;;!UT1---I--j;Ai;IN..L...L...l....l.....,

TM~ BOUTr----l1\\\---..BIN TMC2023
[M::::IN=---!10~;P!6~,:M~OU!!TI--J.,),:L
.......-t. M_IN_-.;.;~#N;;:.._--I
. 100_6

BOUTr-------.. BIN
MOUT

[1

~

7

I

,y; ... .lJ~~==~II
7

SUMMER

1

ttl.iIl N+7
Figure 9. Multi-Bit x 1-Bit Correlation

REGISTER

SUMMER

~~:~NCE

3-366

+-__

_____________

CORRElATION

OUTPUJ

~

Raytheon Semiconductor

For More Information call 101100·722·7074.

TMC2023
Standard Military Drawing
These devices are also available as products
manufactured, tested, and screened in compliance with
Standard Military Drawings (SMD). The nearest vendor

SMD
5962-89711
5962-89711
5962-89711
5962-89711
5962-89711
5962-89711

01JA
02JA
01LA
02LA
013A
023A

equivalent product is shown in the table; however, the
applicable SMD is the sole controlling document defining
the SMD product.

TRW Product

Speed

Package

TMC2023B7V
TMC2023B7Vl
TMC2023B2V
TMC2023B2Vl
TMC2023C3V
TMC2023C3Vl

25MHz
30MHz
25MHz
30MHz
25MHz
30M Hz

24 Pin CERDIP 0.6- Wide
24 Pin CERDIP 0.6" Wide
24 Pin CERDIP 0.6' Wide
24 Pin CERDIP 0.6' Wide
28 Contact Chip Carrier
28 Contact Chip Carrier

Ordering Information
Product
Number
TMC2023B2C
TMC2023B2Cl
TMC2023B2C2
TMC2023B2C3
TMC2023B2V
TMC2023B2Vl
TMC2023B2V2
TMC2023B2V3
TMC2023B7C
TMC2023B7Cl
TMC2023B7C2
TMC2023B7C3
TMC2023B7V
TMC2023B7Vl
TMC2023B7V2
TMC2023B7V3
TMC2023C3C
TMC2023C3Cl
TMC2023C3C2
TMC2023C3C3
TMC2023C3V
TMC2023C3Vl
TMC2023C3V2
TMC2023C3V3

fCLJ(

Package

Temperature

Screening

Package
Marking

STD: TA =0 to 70"C
STD: TA =0 to 70"C
STD: TA =0 to 70"C
STD: TA =0 to 70"C

Commercial
Commercial
Commercial
Commercial

24-pin CERDIP,
24-pin CERDIP,
24-pin CERDIP,
24-pin CERDIP,

0.3" Wide
0.3" Wide
0.3" Wide
0.3" Wide

2023B2C
2023B2Cl
2023B2C2
2023B2C3

EXT: Te =-55 to 125"C
EXT: Tc =-55 to 125"C
EXT: Te =-55 to 125"C
EXT: Te =-55 to 125"C

MIL-STD-883
MIL-STD-883
MIL-STD-883
MIL-STD-883

24-pin CERDIP,
24-pin CERDIP,
24-pin CERDIP,
24-pin CERDIP,

0.3" Wide
0.3" Wide
0.3" Wide
0.3" Wide

2023B2V
2023B2Vl
2023B2V2
2023B2V3

STD: TA =0 to 7O"C
STD: TA =0 to 70"C
STD: TA =0 to 70"C
STD: TA =0 to 70"C

Commercial
Commercial
Commercial
Commercial

24-pin CERDIP, 0.6" Wide
24-pin CERDIP, 0.6" Wide
24-pin CERDIP, 0.6" Wide
24-pin CERDIP, 0.6" Wide

2023B7C
2023B7Cl
2023B7C2
2023B7C3

EXT: Te =-55 to 125"C
EXT: Te =-55 to 125"C
EXT: Tc =-55 to 125"C
EXT: Tc =-55 to 125"C

MIL-STD-883
MIL-STD-883
MIL-STD-883
MIL-STD-883

24-pin CERDIP,
24-pin CERDIP,
24-pin CERDIP,
24-pin CERDIP,

2023B7V
2023B7Vl
2023B7V2
2023B7V3

STD: TA =0 to 70"C
STD: TA =0 to 70"C
STD: TA =0 to 70"C
STD: TA =0 to 70"C

Commercial
Commercial
Commercial
Commercial

28-Contact Hermetic Ceramic
28-Contact Hermetic Ceramic
28-Contact Hermetic Ceramic
28-Contact Hermetic Ceramic

Chip Carrier
Chip Carrier
Chip Carrier
Chip Carrier

2023C3C
2023C3Cl
2023C3C2
2023C3C3

EXT: Te =-55 to 125"C
EXT: Te =-55 to 125"C
EXT: Tc =-55 to 125"C
EXT: Te =-55 to 125"C

MIL-STD-883
MIL-STD-883
MIL-STD-883
MIL-STD-883

28-Contact Hermetic Ceramic Chip Carrier
28-Contact Hermetic Ceramic Chip Carrier
28-Contact Hermetic Ceramic Chip Carrier
28-Contact Hermetic Ceramic Chip Carrier

2023C3V
2023C3Vl
2023C3V2
2023C3V3

(MHz)
25
30

35
50
25
30

35
50
25
30

35
50
25
30

35
50
25
30

35
50
25
30

35
50

0.6"
0.6"
0.6"
0.6"

Wide
Wide
Wide
Wide

40000283 Rev I 8/93

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-367

I

TMC2023

3-368

Raytheon Semiconductor

For More Infonnation call 1-800·722·7074.

TMC222O/TMC2221
TMC2220rrMC2221
CMOS Programmable Digital Output Correlators
4 x 32 Bit, 20 MHz; 1 x 128 Bit 20 MHz

Description
The TMC2220 20 MHz, TTL compatible CMOS
correlator is composed of four separate 1 x 32 correlator
modules. The correlation scores of the four modules are
weighted, combined and output on two separate parallel,
three-state ports.
Each module contains a 32-bit serial data register, a 32bit serial reference preload register, a 32-bit parallel
reference latch and a 32-bit parallel mask latch.
Correlation is performed by 32 exclusive-NOR (XNOR)
gates. Each XNOR gate compares one (single bit)
reference word. While correlation is being performed
between the data and the present reference, the next
reference pattern may be preloaded through one of two
multiplexed input ports. Shorter sampling windows and
bipolar correlation are also supported. Each module
outputs a 6-bit binary correlation score. Either an
unsigned (range 0 through 32) or bipolar (range -16
through +16) representation may be selected. The
outputs of each pair of correlator modules is added, with
user-selected weighting factors, producing intermediate
correlation scores which can be combined or output
directly to the main or auxiliary output ports.
Since the four modules can be cascaded serially or in
parallel, the TMC2220 supports numerous single and
dual channel applications involving 1, 2 or 4-bit wide
data and window lengths up to 32, 64, 96 or 128 bits.
Multiple devices can be combined to support large
correlation operations.
The TMC2221 combines the four 32-bit modules in
series for a fixed channel configuration of 1-bit by 128.
The reduced complexity and package size of the
TMC2221 is ideal for applications requiring less
versatility than the lMC2220. By making use of the
mask function, any size single channel length of up to
128 bits is possible.

For More Information call 1-800-722-7074.

With the TMC2221 , the reference word is serially loaded
through the single two-input multiplexed reference port of
the first correlator module. Although the configuration is
fixed, the reference loading process and basic operation
for each module is similar to that of the TMC2220. The
outputs are summed with equal weighting, and the result is
output through the single 8-bit output port. Unsigned
magnitude or two's complement (bipolar) output score may
be selected.

Features
•
•
•
•
•
•
•
•
•
•
•

20 MHz continuous correlation rate
Fully programmable masking
Two's complement or unsigned magnitude correlation
score
User-programmable reference load multiplexing
Channel weighting and output formatting (lMC2220)
Multi-bit, dual-channel or non-coherent (quadrature)
correlation (TMC2220)
Single +5V power supply
Low power CMOS construction
Three-state m compatible outputs
TMC2220 available in 68-pin grid array and 69-pin
plastic PGA packages
TMC2221 available in a 28-pin CERDIP

Applications
•
•
•
•
•
•
•
•

Signal detection
Radar signature recognition
Secure communications
Robotics/automated assembly
Automatic test equipment
Electro-optical navigation
Pattern and character recognition
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Raytheon Semiconductor

3-369

I

TMC2220/TMC2221
TMC2220 Functional Block Diagram
.1

1-0)

2

II

J

WEIGHTING
DECODER

{ilili}

TC

~

",

.,

elK

MOOULEl

,

'l;'I¥.I··

~

",

~·'Oy ~
~-

l.

~

•

.,

RE,

REFEflEMCE MUX
ANIlENA8l.E
DECOOER

.-

PARALLEL

•

PlPE1.1NE

T

',1"1,,
f

"
-,"

MZ

r~[:>-4 :,~~

{J

1M

..P....F "'" ~ ~~
.,

f

"

+~I

+

:1 .., nl~I:d-· ~~,

"',

HJI -

MODUlE 2

E,
"

I+-

~~

f-.

,
"

,'

~
IADz

BY

,

BO,

1-0

ddd'

",, ''
,

rcoM'11N11ll1i

COMBINING
MATRIX DECODER

MOOULE3

f-.

k&.
f£

f-.
~

,

MOOOLE4

~

lD'"

", ~
BY,

Lo

Raytheon Semiconductor

""
5

,,-.

D

•

AUXILIARY
OUlPUTPORT

I

~

f-.

OOTPU.
POfl'

•

"

BY,

3-370

iiiil

I+I-

",

..

....

6

5

lDR

A~

DMs_.

10

MATRIX

lilA

...
...

For More Information call 1-800-722-7074.

TMC2220rrMC2221
Functional Block Diagram
AE >------I----I>\J\.H
AD

MODULE 2

MODULE 1

MODULE 4

LM>------I~---I>\
LDR

>------+.....

" >------If---I-r~-+---I..
BY >--;::::==::::;-I-;:::~-r

BD

rc>------t
3 STAGE
DELAY

D~_D

OEM

TMC2220 Pin Assignments

TMC2221 Pin Assignments

l K J H G FED C B A

68 Pin Grid Array - G8 Package
69 Pin Plastic Pin Grid Array - H8 Package 1
Pin

Nam.

Pin

Name

Pin

Name

Pin

Name

B2
BI
C2
CI
02
01

OA I

K2
L2
K3
L3
K4
L4
KS
LS
KS
LS
K7
L7
K8
L8
KS

GNO

KlO
Kll
JIO
Jll
HID
Hll
GlO
Gll
FlO
Fll
EIO
Ell
010
011
CIO
Cll
Bll

RE2
AI2
BY2
BX2
All
BYI
BXI
GNO
CLK
GNO

BID
AlO
BS
AS
BB
AB
B7
A7
BS
AS
BS
AS

LOR4
AE4
lOR3
AE3

E2
EI
F2
FI
G2
GI
H2
HI
J2
JI
KI

0110
OMo
OM I
OM2
OM3
OM4
OMs
VOO
OMS
OM7
OM8
OMg
BOI
AOI
B02
A02

"L9

LID

VOO
GNO
OEM
W2
WI
Wo
CI
Co
TC
LM
LORI
AEI
lOR2
AE2
RED
REI

BY3
BX3
AI3
BY4
BX4
AI4
VOO

B4

AI
B3
A3
A2

iiEA
VOO
A04
B04
A03
B03
OA7
OAt;
OAS
0",
OA3
OA2
GNO

000000000
00000000000

~~/
00

11
10

\~~:
TOP VIEW
CAVITY UP

00

5

lOR
AE
REI
GNO
RE2
AI
GNO
elK
BY
BX
VOO
AD
BO
NC

10
11
12
13
14

Z8 lM
27 TC
2& OEM
25 GNO
24 GNO
23 OM7
22 VOO
21 OM6
2tJ OM5
19 OM4
18 OM3
17 OM2
16 OMI
15 OMO

28 Pin CERDIP - 86 Package

OO~
./00.
o 0 ~KEY
00 3
00000000000 2
000000000
ABCDEFGHJKL

Note:

1. Pin 04 is a mechanical orientation pin on the HB package at

21044A

manufacturer's option.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-371

I

TMC2220/TMC2221
Functional Description
General Information
The TMC2220 consists of four independent 1 x 32 correlator
channels with weighted correlation scores which are combined
and output on the two output ports Imain and auxiliary!. By
taking advantage of the instruction set and 110 structure, the
TMC2220 can be adapted to a wide variety of applications.
The TMC2221 consists of the four 1 x 32 correlator modules
cascaded internally for a single 1 x 128 correlator. The outputs
of each module are given a unity weighting, summed and
placed on the output port.

Correlator Channel Modules
Each of the four modules Ii ~ 1 to 41 contains two 32 - bit
serial synchronous shift registers, Ai Idatal and Bi Ireference
preloadl; two 32-bit parallel latches, Ri Ireferencel and Mi
Irnaskl; 32 exclusive-NOR gates; 32 AND gates; a 32-bit
parallel binary counter with a 6- bit unsigned output and a
defeatable half-scale 1-161 subtractor with a 7-bit two's
complement output.
Whenever a given Ai or Bi register is enabled, the next rising
edge of the clock loads the value at the corresponding Ai or
BXi/BYi input port into the first cell of the register, and shifts
the contents of each cell to the next, overwriting the contents
of the last cell. These serial-in, parallel-tapped registers form
the first of six registers which account for the six internal
delays. After an output buffer delay to, the new contents of
the last cell of Ai and Bi become available at the outputs Aoi
and Boi respectively. These outputs are used for cascading
multiple devices. In addition, the Bi input multiplexer selects
which of two input ports, BXi or BYi, is to be used on that
cycle.
The reference latch Ri tracks the contents of Bi when control
LORi was HIGH on the previous cycle and holds when LORi
was LOW. A HIGH on LORi transfers the contents of Bi in
parallel into Ri on the next clock cycle where correlation takes
place. When LORi is held HIGH, Rj is transparent, enabling
direct correlation between Ai and Bi.
Each of the 32 outputs of Ri is correlated against the
corresponding tap of Ai by an XNoR gate whose output is
connected to both the masking AND gate and the masking
latch Mi.
Each Mi tracks if LM was HIGH on the previous cycle and
holds if LM was LOW. When LM is held HIGH, all Mi latches
are transparent and the output of each XNoR gate is sent to

3-372

both inputs of the corresponding AND gate to prevent masking
or disabling from occurring. A LOW on LM loads the next
unmasked correlation pattern Ifrom the XNoR gatesl into each
Mi. Wherever the latch holds a logic one, normal correlation is
enabled; wherever it is a logic zero, correlation is masked by
the AND gate.
A 32 - bit parallel counter encodes the number of logic ones
emerging from the AND gates as a 6-bit binary number
between 0 and 32 1100000!. The clock drives the two pipeline
registers in the counter Ithe second and third registers in the
six register pipeline!.
The 6-bit unsigned binary output of each parallel counter then
enters a half -scale subtractor where it passes unchanged if
the pipelined control TC is LOW and is reduced by 16 if TC is
HIGH. If TC is HIGH, the range of correlation scores becomes
-16 through + 16 where + 16 denotes a perfect match
between the contents of Ai and those of Ri with no masking.
A score of -16 denotes that no unmasked data bit matches
the corresponding reference bit lanti - correlation!. The TC
control is pipelined by 3 registers, such that it is aligned with
new data entering the Ai or Bi register.

Weighting and Merging Circuitry
On the TMC2220, the 7-bit two's complement output of each
correlator module 101, 02, 13, 141 is multiplied by a factor of 0,
1, 2, 3, 4 or 5 according to controls W2-0. The outputs of
each pair of multipliers is then added and the results 0 and I
are loaded into the fourth pipeline register.
Following two additional pipeline delays from the fifth and
sixth registers, correlation sum I is available on the TMC2220
at the 8-bit auxiliary output port, OA7 -0, if the buffer is
enabled IDEA ~ LoWI.
Under controls C1-0, the TMC2220 combiner blends Q and I
into a single final correlation score which is sent to the 10 - bit
main output port, OMg-O, if OEM is LOW. The combiner
pipeline register stage 5 and the main output register stage 6
are balanced by the auxiliary port double output register. In the
simplest mode, the combiner outputs correlation sum Q
permitting the TMC2220 to be used in two separate correlator
channels. In this application, the combined results from
modules 1 and 2 emerge through OMg-O while the results
from modules 3 and 4 emerge through OA7 -0. In the three
remaining modes, the output at the main port will reflect the
correlations of all four modules.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2220trMC2221
In the second mode, the combiner outputs the unweighted
sum, 0 + I. In the third mode, it outputs the weighted sum,
+ 1/2, for single channel binary applications. In the fourth
mode, the combiner extracts the absolute values of 0 and I
and adds the greater magnitude value to one half of the lesser
value. This final mode is an approximation of the Pythagorean
vector magnitude formula:

o

M

=

IX2 + y211/2

The TMC2220 contains a tatal of five pipeline registers plus
the data and reference preload shift registers making the tatal
delay six clock cycles. Instructions and data paths are pipelined
so the instructions presented on a given clock cycle apply to
the value entering registers Ai and Bi. Instructions RE, LM,
LOR and AE, all of which enable registers or latches, must be
set one cycle early Isee timing diagraml.

For the TMC2221, the correlation score of each module is
passed unchanged ITC = LoWI or reduced by sixteen
ITC = HIGHI. Each module score is given a unity weighting
then sent ta the combining matrix where the four scores are
added and output on the 8- bit data bus if OEM is LOW.
In magnitude mode ITC = LoWI and masking disabled, a
perfect match between the data and reference will produce a
correlation score of 128 110000000BI and correlation score of 0
shall indicate no matches lanti - correlationl. In two's
complement mode ITC = HIGHI, perfect correlation will
produce a score of 64 101000000BI and anti - correlation shall
have an output of -64 111000000BI. A total of five register
delays plus the input register cause the result to be available
on the sixth clock cycle after the loading of the input data.

Signal Definitions
Power

VOO,
GNO

The TMC2220 lO-bit output format is:
The TMC2220/TMC2221 operate from a single
+5V power supply. All power and ground pins
must be connected.

I I,71 ,61 ,51 ,.1 ,31"1 " I ,0 I. ,-, I
I-,sl ,71 ,61 ,q ,41 ,31,'1 ,'I ,0 I. ,-'I
,8

Inputs
A11-4

The main, BXi, and alternate, BYi, reference
preload inputs to the Bi register of each
correlator module are selected by controls
RE2-0·

Where each term is either unsigned magnitude
or magnitude minus 16 depending on the TC
control. The TMC2221 8-bit output format is:

Outputs

OM7

Aol-4

Bol-4

Each cascade reference preload output is a
single - bit serial output from the Bi register of
each correlatar module.

OM9-0

The lO-bit main correlation output ITMC2220
onlyl is a combination of the four module
output scores, 01, 02, 13, 14, which are
dependent on the W2 _0 weighted adder and
C1-0 combining matrix controls. The main
output port is enabled by OEM.

For More Infcnnalion, call 1-800-722-7074.

if TC is HIGH

The TMC2221 has an 8-bit correlation output
OM7 -0 which always outputs the sum:

Each data input is a single -bit serial input ta
the Ai register of each correlatar module.

Each cascade data output is a single-bit serial
output from the Ai register of each correlator
module.

if TC is LOW

°Mo

I,7 H ,51 ,.1 ~ I"I" I,a I if TC is LOW
kl ,.1 ,5 H ~ I,' I" I,a I if TC is HIGH
OA7-0

ITMC2220 onlyl The 8-bit auxiliary correlation
output is the sum of two module output scores,
13 and 14, which are dependent on the W2 - 0
weighted adder controls. The auxiliary output
port is enabled by oEA.
The 8-bit binary output format is:

I ,71,.1,51 ,41 ~ I"I " I ,0 I
1-,71,&1,s I ,.1,31" 1,,1,01

Raytheon Semiconductor

if TC is LOW
if TC is HIGH

3-373

I

TMC2220ffMC2221
Clocks
ClK

The clock for Ai data and Bi reference preload
registers can be toggled at up to 20M Hz. All
registers are strobed on the rising edge of ClK
and dependent on the registered enable controls,
AEi. for the Ai registers, and RE2 _0 for the Bi
registers. The plpelme delay registers for the
controls, W2-0, Cl-0 (TMC2220 onlyl and TC
are also strobed on the rising edge of ClK.

Controls
AEl-4

The clock enable for the four Ai data registers
IS a registered, a?tive HIGH control. When AEi is
lOW on the prevIous cycle, no shifting of data
occurs on Ai. AEi is read on the rising edge of
ClK, thus the shifting of data in Ai will occur
on the next rising edge of ClK.

Cl-0

(TMC2220 onlyl These pipelined instructions
select the function to be executed by the
combining matrix and output through the main
output port, OMg-O.

LDRl-4

The load Reference control copies the contents
of register Bi into latch Ri for correlation. If
LORi was lOW on the previous clock cycle, the
present contents of the latch remain in Ri. If
LORi was HIGH, Ri is transparent and the Bi
are values used in the current correlation.

lM

The load Mask control allows the user to mask
or select "no compare" bit positions in each
channel: Inputs shifted into Ai and Bi produce a
correlatIOn pattern as the desired mask. Control
lM must be HIGH on the previous cycle to
track and lOW to store the pattern in the mask

3-374

latches Mi. If no masking is required, lM is
kept HIGH, making Mi transparent.
OEA

ITMC2220 onlyl The asynchronous output enable
for the auxiliary output por!J!A7 -0, is an
active lOW control. When OEA is HIGH, the
output is in a high -impedance state.

OEM

The asynchronous output enable for the main
output p~rt, OMg-O (OM7 -0 on ~ TMC2221l,
IS an active lOW control. When OEM is HIGH,
the output is in a high -impedance state.

RE2-0

The encoded clock enable and load selector
controls determine the various combinations of
BXi and BYi reference inputs that may be
selected for the four reference preload registers
Bi. The Bi register clocks may also be
selectively enabled. Like lOR, lM and AEi, this
control is delayed by one clock cycle. IRE2-1
used on the TMC2221 to select BX or BY.! See
Table 1.

TC

The Two's Complement control forces the
outputs of the four correlator modules to be
unipolar (0 to 321 or bipolar (-16 to + 16). When
TC is lOW, the outputs of the correlator
~od~les are passed unchanged to the weighting
circUitry. When TC is HIGH, 16 is subtracted
from each correlator output which is then
interpreted as a two's complement value.

W2-0

(TMC2220 onlyl The weighted adder controls
determine the relative weightings of the four
correlation module scores.

Raytheon Semiconductor

For More Information call 1-800-722·7074.

TMC2220trMC2221
TMC2220 Package Interconnections
Signal
Type
Power
Inputs

Signal
Name

Function

GB. H8 Package Pins

Voo
GNo

Supply Voltage
Ground

F2, L2, Bll, AB
K2, K3, Gll, Fll, A2

A11-4
BXl_4

Data Input

Main Reference Preload
Alternate Reference Preload

Hlo, Kll, 010, Cll
GlO, Jl1, Ell, Clo
Hll, Jlo, Elo, 011

BOl-4
oM9-0
oA7_o

Data Output
Reference Preload Output
Main Port
Auxiliary Port

J2,
HI,
H2,
85,

Clock

CLK

Master Clock

FlO

Controls

AEH
C1-o
LDRl-4
LM
OEA
OEM

Register Clock Enable
Combining Matrix
Reference Load
Mask Load
Auxiliary Port Output Enable
Main Port Output Enable
Reference Load Select
Two's Complement
Module Weighting Factor

KB, K9, A9, AID
L5, K6
L7, LB, B9, BID
K7
BB

BYl-4
Outputs

AOl_4

RE2-o
TC
W2-o

Kl, B6, B7
Jl, A6, A7
Gl, G2, Fl, EI, E2, 01, 02, CI, C2
A5, B4, A4, B3, A3, B2, Bl

I

L3

KlO, L1o, L9
L6
K4, L4, K5

TMC2221 Package Interconnections
Signal
Type
Power

Signal
Name

Function

86 Package

Voo
GNo

Supply Voltage
Ground

11, 22,
4, 7, 24, 25

Inputs

AI
BX
BY

Data Input
Main Reference Preload
Alternate Reference Preload

6
10
9

Outputs

AO
BO
oM7_o

Data Output
Reference Preload Output
Main Port

12
13
23, 21, 20, 19, lB, 17, 16, 15

Clock

CLK

Master Clock

8

Controls

AE
LOR
LM
OEM

Register Clock Enable
Reference Load
Mask Load
Port Output Enable
Reference Load Select
Two's Complement

2
1
28
26
5, 3
27

RE2-1
TC
No Connection

For More Infonnalion. call 1-800-722-7074.

NC

14

Raytheon Semiconductor

3-375

TMC2220/TMC2221
Table 1. Reference Preload Register Input and Enable
Operation
Selected Reference
Port (TMC2220)

REi
Controls

Selected Reference
Port (TMC2221)

RE2-0
000

1
Dis

2
Dis

3
Dis

4
Dis

001
010

Dis
Dis

Dis

Dis

BX4

Dis

BY3

BX4

011

Dis

Dis

BY3

BY4

100

BXl

BX2

BX3

BX4

101

BYI

BX2

BX3

BX4

110

BYI

111

BYI

BX2
BY2

BY3
BY3

BX4
BY4

Dis
BY
BX
BY

Notes:

1. Dis

~

Bi register disabled Ihold model.

2. LSB IREOI not used on the TMC2221.

Table 2. Module Weighting Factor Operation
(TMC2220 Only)
Wi Controls

Internal Channel Configuration

W2-0

n

000
001

01 + 02
301 + 02

13 + 14
313 + 14

010

401 + 02

413 + 14

011
100

°2

'4

'3

°1
301 + 202

101
110

313 + 214
413 + 214
513 + 214

4Ql + 202

111

501 + 202

Sliding Correlation Timing
The TMC2220 and TMC2221 have a six register pipeline. There
are registers for the input data and reference, parallel counter,
weighting circuitry, combining matrix, and output. CLK is used
to load all Ai, Bi and instruction pipeline registers. With the
register controls enabled, a data or reference word is loaded
into its respective Ai or Bi register on every rising edge of
elK. Data AN enters register Ai on the rising edge of clock
CN. The reference latch is static if the previous LORi was
LOW or tracks Bi if LORi was HIGH. If reference preload is
not desired, holding control LORi HIGH makes latch Ri
transparent and direct correlation between Ai and Bi occurs.
Data is valid if present at the input for a setup time ts before
and a hold time tH after the rising clock edge. Setup and hold
time requirements also apply to instructions and controls,
however, AE, LOR, LM and RE must be valid one cycle before
taking effect.
Because of the six internal pipeline delays, the correlation
score for a given set of Ai and Bi register contents appears at
the output ports six clock cycles plus an output delay to later.
When the main and auxiliary ITM C2220 only) output ports are
enabled IDEM ~ LOW and oEA ~ LOW), the correlation score
ON of data window AN-31 through AN is output after rising
clock edge CN+5 IAN-127 through AN on the TMC22211.
Instructions TC, Wand C are registered and pipelined so that
the instructions will be aligned with the data. The instructions
IN Isee timing diagram) which are loaded on rising clock edge
CN apply to a correlation between data and reference words
N-31 IN-127) through N. Masking is assumed to be preset
Iprevious LM ~ LOW) or unused Iprevious LM ~ HIGHI. The
same timing applies if the reference is shifting and data is
fixed.

Table 3. Combining Matrix Operation (TMC2220 Only)
Ci Controls
Cl-0
00
01
10
11

Main Output Port Function
DMg_O

°°

1i2

Max

1101, 1111

+

0+ I
+ 1/2 Min

1101, 111)1

Notes:

1. The larger magnitude value of ° or I plus one-half of the smaller
magnitude value.
2. The TMC2221 always outputs the sum 01 + 02 + '3 + '4·

3-376

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2220rrMC2221
Figure 1. S6ding Correlation Timing

eLK

..

REGISTER CLOCK

....

--+--,.....,.-'1

_'.DA7_'----------------------------~ ~

~.ID-------------------------~t=~:j~ .~--

Reference Register Load Timing
The HIGH on LDRi transfers the contents of Bi in parallel into
Ri in the next clock period. Ri tracks Bi when control LORi is
HIGH and holds when LDRi is lOW. N rising edges of ClK are
reqUired to load N reference words into the reference preload
register Bi. The rising edge of clock CN loads reference word
BN so that Bi contains words BN-31 through BN.
Figure 2 illustrates the LORi instruction timing to transfer
reference window BN -31 through BN into the reference latch.
With this timing, correlation against the' old reference pattern is
preserved during the "lOR" clock cycle and that correlation
against the new reference pattern BN -31 to BN should
commence immediately after the "lOR" clock cycle. The user
must meet the normal input setup and hold time requirements
and setup the instruction one clock cycle before the desired
transfer.

A completely new reference can be loaded into latch R on
every 32nd clock cycle. With the output ports enabled, the
correlation score ON Icorrelation between data AN -31 through
AN and reference BN-31 through BNI is available an output
delay to after the rising edge of clock CN + 5 because of the
six register pipeline.
Operation of the TMC2221 is similar to the operation described
for the TMC2220 except the length of the reference word is
128 bits rather than 32. The reference register will therefore
contain the pattern BN -127 through BN, and correlation occurs
between this reference and data AN-127 through AN. A new
reference word therefore requires 128 clock cycles to
completely load the new value. With the output ports enabled,
the correlation score ON Icorrelation between data AN-127
through AN and reference BN -127 through BNI is available an
output delay to after the rising edge of clock CN + 5·

Figure 2. Reference Latch Load Timing

For More Infoonation. calI1.aoo-722·7074.

Raytheon Semiconductor

3-377

I

TMC2220/TMC2221
Mask Register Loading
Control LM latches a mask pattern into Mi which selectively
disables word positions in each correlator module. Masking
latch Mi tracks the XNOR output if, on the the previous clock
cycle, LM was HIGH and holds if LM was LOW. Figure 3
illustrates the TMC2220 LM timing to latch a mask generated
by the exclusive NOR of AN -31 through AN with RN -31
through RN. LM must be set HIGH ts before the rising edge
of clock CN-1 to load the mask for AN-31 thru AN. LM
must be set LOW before the next rising edge of CN to ensure
words N-31 to N remain latched as the mask pattern. A
completely new mask may be loaded on every 32nd clock
cycle. However, to permit time for data and reference loading,

mask loading is generally limited to every 64th clock cycle. The
first correlation score which reflects mask N is output to after
the rising edge of clock cycle CN + 6.
Operation of the TMC2221 is similar that of the TMC2220 but
requires 128 clock cycles to completely load a new mask
pattern. To permit time to load new data and a new reference
pattern once the mask is loaded, an additional 128 clock cycles
is required. Therefore, mask loading is generally limited to
every 256 clock cycles in the TMC2221. The mask pattern
loaded will be the exclusive-NOR of AN-127 through AN with
RN-127 through RN·

Figure 3. Masking Latch Load Timing

M,

MASK N-l

XXX
X

3-378

MASK N IXNOR N- 31 TO Nt

X

X

X

Raytheon Semiconductor

X

o·bi

0.

~

For More Information call 1-800·722·7074.

TMC2220rrMC2221
Applications Discussion

Figure 4. Dual 64 x 1 Configuration

The TMC222D architecture provides the flexibility for a number
of configurations. The cascade outputs and the internal
weighting and adder logic allow a single TMC222D to be
configured as four independent 32 - bit correlators, independent
96-bit and 32-bit correlators, two independent 64-bit
correlators, or as a single 128 x 1 correlator. The TMC222D
may also be cascaded serially or in parallel to increase the
length or width of correlation.
To increase the correlation length in a single TMC222D system,
the cascade outputs of a module 1ADi, BOil can be connected
to the inputs of the next module IAli + 1, Bli + 11. When using
this configuration, the input enables and load controls should
be connected together. Figure 4 shows the configuration for a
dual 64 x 1 correlation. In this application, the outputs of
module 1 are connected to the inputs of module 2 and the
outputs of module 3 are connected to the inputs of module 4.
The weighting logic is set for 1:1 weighting and the combining
logic is set to output 01 + 02 on the main output DMg-O,
and 13 + 14 on the auxiliary output DA7 -0.

r------j
A',

-1-+''-+1 OX,

I

AD,
MODULE'

00,

I
I

I

A'.

-1-+-'-+1 ox.

I

MODULE.

Figure 5. Cascading the TMC222D for Extended-Length Correlation
Figure 5 shows an example of multi - bit correlation with
extended length. This example shows 4-bit correlation with a
length of 64-bits. The outputs of the two TMC222Ds must be
externally added to obtain the 64-bit correlation score. The
weighting and combining of the module correlation scores
should be set as required by the application.

---+

All
BXI/BYI
AI2
BX2/BY2
AI3
BX3/BY3
AI4

Q

For More Infamation, call 1-800-722·7074.

Raytheon Semiconductor

3-379

TMC2220/TMC2221
Figure 6. 8-Bit Correlation with the TMC2220
Figure 6 shows an example of 8-bit, two's complement
correlation. Two TMC2220s are used in parallel and externally
summed to obtain the properly weighted correlation score. To
obtain a properly weighted correlation score, each bit of the
output must be multiplied by an appropriate binary scaling
factor. The 8-bit data input and reference are connected as
shown. The weighting control of each TMC2220 is set for 4:1
weighting IW2-0 ~ OlDl. This multiplies the upper two bits of
each TMC2220 by a factor of 4 101, 131. The next step is to
multiply the 2nd and 4th bits 102, 141 by a factor of 2. An
equivalent operation is to divide the 1st and 3rd bits by 2. This
operation is accomplished by setting the combining logic to
output the sum 0 + 1/2 IC1-0 ~ 011. The final output of each
TMC2220 will be equivalent to:
DMg-O ~ 14 x 011

+

12 x 131

+

11 x 021

+

Setting the weighting and combining controls as described will
produce a correlation score with each bit properly weighted
based on its 4-bit binary position. The final step is to multiply
the correlation output of the most -significant TMC2220 Ibits
7- 41 by a factor of 16 then combine thOe outputs of the two
TMC2220s. This is done using external adder circuitry.
Multiplication is performed by simply shifting the output lines
of the upper TMC2220 by four places at the input to the
adder logic. The output of the summer, therefore, shall give
the binary weighted correlation score of a quantized 8-bit
input. The same circuit can be used with unsigned data if the
inverter on the most-significant-bit of the reference input is
omitted.

11/2 x 141

10

4
L ________________________________ ~
TMC2220

15

SUMMER

RESULT

B9-0
R3
4

10

o
R2

I 40' +21 3+°2+14/2
I
I

Rl

I

II
RO

I

I
L __________________________ ~

I

TMC2220

l

REFERENCE

3-380

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2220rrMC2221
Figure 7. Full Complex Correlation with the TMC2220
Figure 7 is an example of full complex correlation. In this
example, separate real and imaginary terms are multiplied and
summed internally to provide a real and imaginary result. This
method preserves the phase information of the input. Inputs
are connected as shown in the figure. The imaginary term in
ImlDl x ImlRI is negated linvertedl for proper sign in the
summation. The TMC2220 is set for 1:1 1Q1 + Q2, 13 + 141
weighting, two's complement mode, and the combining control
is set to output Q on the main output and I on the auxiliary
output. All 32 internal taps are used.
A simple example would be to find a sine wave in a
demodulated data stream. The references would be set to:

~-----------------,

RE(oI

>---i-..r----,

REiRI

>----t+L--...J
10

IMiDI
IMiRI

>----t+L__....J

REiDI

>---4...r---,

IMiRI

>----r+L--...J

IMiDI

>---i-..r----,

REiRI

>--;-+L__...J

RelRI ~ Cos I wtl and ImlRI ~ Sin I wtl

TMC2220

w-----------------~
= 1:1

where, w is the modulation frequency. Each term is set to:

TC

=

1

1 for positive and 0 for negative

I

The data inputs are set to:
RelDI ~ datain x Coslltl and ImlDI ~ data in x Sin Iftl
where, f is the mixer or carrier frequency.

Figure 8. Complex Correlation with Magnitude Resuh
Figure 8 is similar to full complex correlation, however, in this
example the output is magnitude only. This application is used
when the phase relationship is not required. The inputs are
connected as in the previous example, however, rather than a
full complex output, the outputs are combined internally to:
Max ilQI, 1111

+

1/2 Min IIQI, IIII

IC1-D ~ 111 to obtain the approximate magnitude output.
MUltiplying the output by 15/16 will reduce the error in the
magnitude approximation.

r------------------------------,

REiDI

>---+-..r---,

REiRI >---t-'~-_..J
IMiDI
IMiRI >---t-'~-_..J
DMg_D
REiDI

>--+..r--,

MAGNITUDE

IMiRI >--T~--..J
IMiDI

>---l-H---'

REiRI >---t-'~--J

~----------------------------

For More Information. call 1-1100·722·7074.

Raytheon Semiconductor

3-381

TMC2220/TMC2221
Figure 9. Cascading the TMC2221 for Extended - Length Correlation
The TMC2221 can be cascaded to implement correlations of
more than 128-bits. Typically all clocks, reference inputs and
enables are connected together and the A and B outputs of

preceding stages are connected to the respective inputs of
subsequent stages. An external summer is required to generate
the composite correlation score.

TC

LOR
LM

AE
RE2_1
ClK

,
~
)-+

I

I

I i2
A'Y

TMC2221

AO

#1

>---+

8X

-

80 _

!lMg_O

I i2
AY

.....

AO

TMC2221

.....

#2
8X

( : 10

V

./

V

I

80

DMg_O

10

12
TMC2221

#N
8X

DMg_O

tjl0

"

U
SUMMER

I
AY

J

ILOG2 NI + 10

Figure 10. Multi-Bit x 1 Bit Correlation
The TMC2221 may also be used to compare multi-bit words
with a single-bit reference. When this is done, the output of
each TMC2221 must be appropriately weighted to the adder

circuitry. The weighting reflects the relative importance of the
different bit positions. Weighting can normally be accomplished
by simple bit shifts at the input to the summer.

MSB

INPUT
DATA
WORD

REGISTER

r---r-..... SUMMER
CORRELATION
OUTPUT

-+__.....

REFERENCE _ _ _ _ _ _
CODE

3-382

Raytheon Semiconductor

For More Information call HIOO·722·7074.

TMC2220trMC2221
Figure 11. Equivalent Input Circuit

Figure 12. Equivalent Output Circuit

voo
n SUBSTRATE

n SUBSTRATE
01

01
p+

CONTROL
INPUT

0-"''''''''''''-'''''''
lKQ

....---41-00 OUTPUT

n+

03

02

p WELL

02

p WELL

pWELL

:' GNO

:' GNO

Figure 13. Threshold Levels for Three-State Measurements

tOiS

I

0.5V

THREE-STATE
OUTPUTS

HIGH IMPEDANCE
0.5V

Absolute maximum ratings Ibeyond which the device may be damagedl 1
Supply Voltage ........................................................................................................................................................................................................................................ -0.5 to +7.0V

Input Vohage ................................................................................................................................................................................................................................ -0.5 to IVOO +0.5V)
Output
Applied vokage 2 .............................................................................................................................................................................................. -0.5 to IVOO +0.5V)
Forced current 3.4 ..................................................................................................................................................................................................... -1.0 to +6.0mA
Short-circuit duration Isingle output in HIGH state to ground) ......................................................................................................................................... 1 sec
Temperature
Operating, case .......................................................................................................................................................................................................... -60 to +1300 e
junction ....................................................................................................................................................................................................................... 175°e
Lead, soldering 110 seconds) ..................................................................................................................................................................................................... 3000 e
Storage ........................................................................................................................................................................................................................ - 65 to +1500 e
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

For More Information, call1-8~~>.}>.;>~

Pin Assignments

!1l III s; !II III <=!

~ !lj

10

:;j

&l

P,,(MSB) 40

P'4 41

P"
P"

42
43

26 CLKY
25 CLKX

P11 44

P,o
P,
P,
CLKP

1
2
3
4

23 X,

P2 12
P, 13

22 X,

(LSB) Po 14

21 X.

(LSB) Xo 15

24 X,(MSB)

~

20 XI
19 X,

TRIM
NC

18 X,
,...coo~::~~:!~~~

~~~~~r:C~~fEfE~
t-

6&637.

TMC208KU Pinout

For More Information call 1-800-722-7074.

~40

Pl1
39 P 2
'
38 P'3

37
36
35
34

P'4
P'5 (MSB)
V7 (MSB)
Va

~

X

32 GNO
31 V4

30 Voo
29 V3
28
27
26
25
24
23
22

V2
V,
V0 (LSB)
RND
CLKV
CLKX
X7 (MSB)

X2 17
X3 18
X. 19
Xs 20 '--_ _ _-' 21 X6

65-8369

~~

ct:>1:

X, 16

-

Raytheon Semiconductor

40 Pin CERDIP - 65 Package
40 Pin Plastic DIP - N5 Package

3-389

TMC208K/TMC28KU
TMCZ08K Functional Block Diagram
TRIM

elK x > - _ - - - - - 1

RND>-+-_....

elK Y

>-+.-----.

elK P

TRll

TMC28KU Functional Block Diagram
XIN

IXrol L---I-8~--"''''''
CLK X

>-------4
~-+-'''" MSPDUT

(P15-sI
RND

>-----+1

elK Y > - - - - - -

eLK P

3-390

R~ytheon

Semiconductor

TRll

For Mora Information call 1-800-722·7074.

T~C208KJT~C28EJJ
Functional Description
General Information
The TMC208K and TMC28KU have three functional sections:
input registers, an asynchronous multiplier array and output
registers. The input registers store the two 8-bit numbers
which are to be multiplied and the instruction which controls
output rounding. The rounding control is used when a
single -word output is desired. Each input operand is stored
independently, simplifying multiplication by a constant. The

asynchronous multiplier array is a network of AND gates and
adders designed to handle two's complement numbers in the
TMC208K or unsigned magnitude numbers in the TMC28KU.
The output registers hold the product as two 8- bit words, the
Most Significant Product (MSPI and the least Significant
Product (lSPI. Three-state output drivers allow the multipliers
to be used on a bus, or allow the MSP and lSP to be
multiplexed over the same 8-bit output lines.

Signal Definitions
handling the case (-11 x (-11 must be made.
The TMC208K outputs a -1 in this case. As a
result, external error handling provisions may be
required.

Power
VDD, GND

The TMC208K and TMC28KU operate from a
single +5 Volt supply. All power and ground
lines must be connected.

Clocks

Data Inputs
X7-0,Y7-0

The TMC208K has two 8-bit two's complement
data inputs labeled X and Y. The TMC28KU has
two 8-bit unsigned magnitude data inputs
labeled X and Y. The Most Significant Bits
(MSBsl, X7 and Y7, carry the sign information
for the two's complement notation in the
TMC208K. The remaining bits are X6-0 and
YS-O with Xo and YO the lSBs. The input and
output formats for fractional and integer two's
complement, and fractional and integer unsigned
magnitude notations are shown in Figures 1
through 4.

Data Outputs
P15-0

The TMC208K has a 16-bit two's complement
output which is the product of the two input X
and Y values. The TM C28KU has a 16 - bit
unsigned magnitude output which is the product
of the two input X and Y values. This output is
divided into two 8-bit output words, the MSP
and LSP. The MSB of both the MSP and the
lSP is the sign bit in the TMC208K. The input
and output formats for hactional and integer
two's complement, and fractional and integer
unsigned magnitude notations are shown in
Figures 1 through 4. Note that since +1 cannot
be exactly represented in fractional two's
complement notation, some provision for

For More Information call 1-800-722-7074.

ClK X, ClK Y The TMC208K and TMC28KU have three clock
ClK P
lines, one for each input register (ClK X and
ClK YI and one for the product register (ClK PI.
Data present at the inputs of these registers are
loaded into the registers on the rising edge of
the appropriate clock. In the TMC208K, the RND
input is registered and clocked in on the rising
edge of the logical OR of both ClK X and ClK
Y. Special attention to the clock signals is
required if normally HIGH clock signals are used.
Problems with loading this control signal can be
avoided by the use of normally lOW clocks. In
the TMC28KU, the RND input is registered and
clocked in on the rising edge of ClK X.

Controls
TRIM, TRll

TRIM and TRll are the three -state enable lines
for the MSP and the lSP. The output driver is
in the high-impedance state when TRIM or
TRll is HIGH, and enabled when lOW. TRIM
and TRll are not registered.

RND

When RND !Round I is HIGH, a one is added to
the MSB of the LSP. A one will be added to
the P6 bit in the 208K or to the P7 bit in the
28KU. Note that rounding always occurs in the
positive direction. In some applications this may
introduce a systematic bias. The RND input is
registered and used when a rounded 8-bit
product is desired.

Raytheon Semiconductor

3-391

I

TMC208K1TMC28KU
Package Interconnections
Signal
Type

Signal
Name

Power

VOO
GNO

Supply Voltage
Ground

30
32

Data Inputs

X7-0
Y7-0

X Input Word
Y Input Word

22-15
35-33, 31, 29-26

Data Outputs

P15-8
P7-0

MSP Output
lSP Output

36-40, 1-3
7-14

Clocks

ClK X
ClK Y
ClK P

X Register Clock
Y Register Clock
Product Register Clock

23
24
4

Controls

TRIM
TRll
RNO

MSP Three - State
LSP Three-State
Round

5
6
25

Function

85, N5 Package

Figure 1. Fractional Two's Complement Notation (TMC20BK)
BINARY POINT

SIGNAL
L-~~~

__-L__

~

__

~

__

L-~

__

~

DIGIT VALUE

~1-~~-7~~7+~~1-7+~~~~~~~~~

L----1I-~---L_::::-f-~..L....:--L....:.---L--=-+-=-~::.....L.:~L...:.::_::_L-=-..L..::......t....:=--J...:.---'

SIGNAL
DIGIT VALUE

Figure 2. Integer Two's Complement Notation (TMC20BK)
BINARY POINT

3-392

Raytheon Semiconductor

Xo

SIGNAL

Zo

DIGIT VALUE

Yo

SIGNAL

Zo

DIGIT VALUE

Po

SIGNAL

zO

DIGIT VALUE

For More Information call 1-800-722-7074.

~C208RJr~C28EJU
Figure 3. Fractional Unsigned Magnitude Notation (TMC28KU)
BINARY POINT

I-X_7+-+--+--+-''-I-'-I-:...J.-=-l SIGNAL
2-1

r-~~~~~~~

DIGITAL VALUE

SIGNAL
DIGIT VALUE

Figure 4. Integer Unsigned Magnitude Notation (TMC28KU)
BINARY POINT

Xu

SIGNAL

'zIl

DIGIT VALUE

Yo

SIGNAL

20

DIGIT VALUE

Po

SIGNAL

20

DIGIT VALUE

X

I

Figure 5. Timing Diagram

INPUT
INPUT
CLOCK
OUTPUT
CLOCK

tpWH

~------tMPY-----....-I

THREE-STATE
CONTROL

OUTPUT

FtOis

OUTPUT

For More Information call 1-800-722·7074.

HIGH IMPEOANCE

Raytheon Semiconductor

3-393

TMC2o.8K1TMC28KU
Figure 6. Equivalent Input Circuit

Figure 7. Equivalent Output Circuit
voo
n SUBSTRATE

n SUBSTRATE
P

CONTROL <>---'W'v-~p-",
INPUT
IKQ

01

...-~.....-o OUTPUT

n+

02

02

p WELL

p WELL
':" GNO

':" GNO

Figure 8. Threshold Levels For Three-State Measurements
TRIM. TRIL

lOIS

O.5V

THREE-STATE
OUTPUTS

HIGH IMPEDANCE
O.5V

Application Discussion
Multiplication By A Constant
Multiplication by a constant requires that the constant be
loaded into the desired input register and that the register not
be loaded again until a new constant is desired. The multiply

cycle then consists of loading new data and strobing the
output register.

Selection Of Numeric Format
Essentially, the difference between integer, mixed and fractional
notation in system design is only conceptual. For example, the
TMC20SK and TMC2SKU do not differentiate between this
operation:

6 x 2 = 12
and this operation:
16/S1 x 12/S1

=

12/64

The difference lies in constant scale factors lin this case, a
factor of S in the multiplier and multiplicand and a factor of

3·394

64 in the product!. However, these scale factors do have
implications for hardware design. Because common design
practice assigns a fixed value to any given line land input and
output signals often share the same linel, the scale factors
determine the connection of the output pins of any multiplier
in a system. As a result, only two choices are normally made:
integer or fractional notation. If integer notation is used, the
LSBs of the multiplier, multiplicand and product all have the
same value. If fractional notation is used, the MSBs of the
multiplier, multiplicand and product all have the same value.

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TMC208K!fMC28KU
DC characteristics within specified operating conditions 1

Parameter

Temperature Range
Standard
Extended
Min
Max
Min
Max

Test Conditions

100Q

Supply Current, Quiescent

100U

Supply Current, Unloaded

flA
flA

Output Voltage, Logic LOW
Output Voltage, Logic HIGH

Voo = Min, 10L = Max

10ZL

Hi-Z Output Leakage

=

Max, VIN = OV

0.4

Voo

=

0.4

2.4

Voo = Min, IOH = Max

Hi-Z Output Leakage Current, Output HIGH

mA
mA

10

VOL
VOH

Short-Circuit Output Current

50
100
-10

Voo = Max, VIN = Voo

lOS

50
100

10

Voo

Input Current, Logic HIGH

10ZH

mA

-10

Input Current, Logic LOW

IIH

Output LOW

Units

5

Voo = Max, TRIM, TRIL = 5V, I = 22MHz
IlL

Curren~

5

Voo = Max, VIN = OV
Voo = Max, TRIM, TRIL = 5V, I = 10MHz

Max, VIN = OV

Voo = Max, VIN = Voo
Voo = Max, Output HIGH, one pin to
ground,

2.4

V
V

-40

-40

flA

40

40

flA

-100

-100

mA

one second duration max.
CI

Input Capacitance

TA = 25°C, I = lMHz

10

10

pF

Co

Output Capacitance

TA = 25°C, I = lMHz

10

10

pF

Note:

1.

Actual test conditions may vary from those shown, but guarantee operation as specilied.

2.

2f = 20 MHz for ETR.

AC characteristics within specified operating conditions

Parameter
tMPY

Multiply Time

Test Conditions

Temperature Range
Standard
Extended
Min
Max
Min
Max

Voo = Min
TMC20BK, TMC2BKU
TMC20BK-l, TMC2BKU-l

tpWH

Clock Pulse Width, LOW
Clock Pulse Width, HIGH

ts

Input Setup Time

tpWL

tH

Input Hold Time

to

Output Delay

tENA

tOiS

Three-State Output Enable Delay 1

Three-State Output Disable Delay 1

Voo - Min
Voo - Min
TMC20BK, TMC28KU
TMC20BK-l, TMC2BKU-l

Voo - Min, CLoAo = 40pF
TMC20BK, TMC2BKU

65

70

ns

45

50

ns

15
15

15

ns

15

ns

25

30

ns

20

25

ns

0

0

ns

40

45

ns

TMC20BK-l, TMC2BKU-l

25

30

ns

Voo = Min, CLOAo = 40pF
TMC20BK, TMC28KU
TMC20BK-l, TMC28KU-l

40
20

45

ns

25

ns

Voo = Min, CLOAD = 40pF
TMC20BK TMC2BKU

40

45

ns

20

25

ns

TMC20BK-l, TMC2BKU-1
Note:

Units

1. All transitions are measured at a 1.5V level except lor tOiS and tENA'

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-395

I

~C208RJT~C28EJU
Absolute maximum ratings Ibeyond which the device may be damaged I1
Supply Voltage ........................................................................................................................................................................................................................................ -0.5 to +7.0V
Input Voltage .............................................................................................................................................................................................................................. -0.5 to {Von +' 0.51V
Output
Applied voltage 2 ..................................................................................................................................................................... ,.. ,................... -0.5 to {Von + 0.51V
Forced current 3,4 ........................................................................................................................................................................................................ -1.0 to 6.0mA
Short-circuit duration {single output in HIGH State to groundl ......................................................................................................................................... 1 sec
Temperature
Operating, case .......................................................................................................................................................................................................... -60 to +130°C
junction ....................................................................................................................................................................................................................... 175°C
Lead, soldering {10 secondsl ..................................................................................................................................................................................................... JOO°C
Storage ........................................................................................................................................................................................................................ ·-65 to +150°C
Notes:
1. Absolute maximum ratings are limiting values applied individually While all other parameters are within specilied operating conditions.
Functional operation under any 01 these conditions is NOT implied.
2. Applied voltage must be current limited to specilied range and measured with respect to GND.
3. Forcing voltage must be limited to specilied range.
4. Current is specified as conventional current flowing into the device.

Operating conditions
Temperature Range
Min

Standard
Nom

Von

Supply Voltage

4.75

5.0

V,L
V,H

Input Vokage, Logic LOW
Input Voltage, Logic HIGH

2.0

IOL
IOH

Output Current, logic lOW
Output Current, Logic HIGH

TA
TC

Ambient Temperature, Still Air
Case Temperature

Parameter

3-396

Max

Min

5.25

4.5

O.B

5.0

Max

V

O.B

V
V

4.0
-2.0

mA
mA

125

°c
°c

70
-55

Raytheon Semiconductor

Units

5.5

2.0
4.0
-2.0

0

Extended
Nom

For More Information call 1-800-722-7074.

T~C208RJT~C28~
Ordering Information
Package

Package
Marking

Product
Number

Temperature

Screening

TMC208KB5C
TMC208KB5C1
TMC208KB5V
TMC208KB5V

STD - TA = 0 to 70"C
STD - TA = 0 to 70"C
EXT - Te =-55 to 125"C
EXT - Te =-55 to 125"C

Commercial
Commercial
MIL-STD-883
MIL-STD-883

4O-pin
4O-pin
4O-pin
4O-pin

TMC208KN5C
TMC208KN5C1

STD- TA = 0 to 70"C
STD- TA = 0 to 70"C

Commercial
Commercial

4O-pin Plastic DIP
4().pin Plastic DIP

208KN5C
208KN5C1

TMC28KUB5C
TMC28KUB5C1
TMC28KUB5V
TMC28KUB5V1

STD - TA = 0 to 70"C
STD- TA = 0 to 70"C
EXT - Te = -55 to 125"C
EXT - Te = -55 to 125"C

Commercial
Commercial
MIL-STD-883
MIL-STD-883

4O-pin CERDIP
4O-pin CERDIP
4O-pin CERDIP
4O-pin CERDIP

28KUB5C
28KUB5C1
28KUB5V
28KUB5V1

TMC28KUN5C
TMC28KUN5C1

STD - TA = 0 to 70"C
STD- TA = 0 to 70"C

Commercial
Commercial

4O-pin Plastic DIP
4O-pin Plastic DIP

28KUN5C
28KUN5C1

TMC208KR2C
TMC208KR2C1

STD - TA = 0 to 70"C
STD- TA = Oto 70"C

Commercial
Commercial

44 J-Lead PLCC
44 J-Lead PLCC

208KR2C
208KR2C1

TMC28KUR2C
TMC28KUR2C1

STD- TA = 0 to 7O"C
STD- TA = 0 to 70"C

Commercial
Commercial

44 J-Lead PLCC
44 J-Lead PLCC

28KUR2C1

CERDIP
CERDIP
CERDIP
CERDIP

208KB5C
208KB5C1
208KB5V
208KB5V1

28KUR2C

I

40005076 Rev 0 8193

ForMore Information call 1-800-722-7074_

Raytheon Semiconductor

3-397

TMC208K!TMC28KU

3-398

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2208
TMC2208
CMOS Multiplier-Accumulator
8x8Bit,40ns

Description

Features

The TMC2208 is a high-speed 8 x8 bit parallel
multiplier-accumulator which opera1es at a 40 ns cycle
time (25 MHz multiply-accumulate rate). The input data
may be specified as two's corrplement or unsigned
magnitude, yielding a full-precision 16-bit product.
Products may be accumulated to a 19-bit result

•

Individually clocked input and ou1put registers are used
to provide maximum sys1em throughput and simplify bus
interfacing. These registers are positive-edge-triggered
D-type flip-flops. The result is dMded into a 3-bit
eXTended Product (XTP), an 8-bit Most Significant
Product (MSP). Individual three-state output ports are
provided for the XTP, MSP, and LSP. The output
register can be preloaded directly via the output ports.

The TMC2208 is pin and function compatible with the
TDC1008 in the 48-pin DIP. Built with Raytheon
Semiconductor La Jolla's OMICRON-cc™ one micron
CMOS process, power consumption is greatly reduced.

Functional Block Diagram

•
•
•
•
•
•
•
•
•

Function compatible with the TDC1008 (pin
compatible in 48-pin DIP package)
40 ns multiply-accumulate time (worst case
commercial)
8 x 8 parallel multiplication with accumulation to
19-bit result
Selectable accumulation, SUbtraction, rounding,
and accumulator preload
All inputs and outputs are registered and m
compatible
Three-sta1e outputs
Two's complement or unsigned magnitude
operation
Single +fJV power supply
Low power CMOS construction
Available in 48-pin ceramic or plastic DIP and PLCC

Applications
•
•
•
•
•
•

Array processors
Video processors
Radar Signal processors
FFT processors
General purpose digital signal processors
Micro/mini-computer
PREL

RX
III

TSX

LSPOUT

1"'-01
CLKy

>-_-----'

For More Information call 1-800-722-7074.

CLKP

Raytheon Semiconductor

TSL

3-399

I

TMC2208
Pin Assignments
P12
Pll
Pl0
P9

1
2

3
4

P8 5

TSM 6
ClK P 7
PREl 8
P7 9

P6 10
P5 11
GND 12
P4 13
P3 14
P2 15
Pl 16
Po 17
TSl 18
SUB 19
ACC 20
RND 21

Xo

22

Xl 23
X2 24

~ - 1 r - - - - - '

ACC, SUB, ~~t==:)
RND,TC ~

ClK Y> - 4 - - - - ,

YINllSPOUT
(Y15 ·iYP15-0)

TSl

For More Inlonnation call 1-800-722-7074.

Raytheon Semiconductor

ClK P

TSM

2210.FBD

3-409

TMC2210
Pin Assignments
~
X5
X4
X3

~
Xl

Xo

000000000
0@0000000@0
00
00
00
00
00
00 BOTTOM VIEW
00
00
00
~mENTATION
00

64 X7

63 Xa
3

62

Xg

61 Xl0
60 XII
59 X12
58 X13
57 X14
5& XIS
55 TSI.
54 RND
53 SUB
52 ACC
51 ClKX
50 ClKV
49 VD D
48 TC
47 TSX
48 PREl
45 TSM
44 CLKP
43 P34
42 P33
41 P32
40 P31
39 P30
38 P29
37 P28
38 P27
35 P26
34 P25
33 P24

6
7
a
9

Po· Yo
Pl' Yl
P2' Y2 10
P3. Y3 11
P4•Y4 12
P5• Y5 13
P6•Y6 14
Pl' V7 15
GND 16
Pa' Ya 17
Pg. V9 la
Pl0•Yl0 19
P11 ,Vll 20
P12•Y12 21
P13•Y13 22
P14•V14 23
PIS' VIS 24
P16 25
P17 26
PIa 27
P19 28
P20 29
P21 30
P22 31
P23 32

~~

64 Pin Hermetic Ceramic DIP - JO. NO Package

43 P17
42
41

p,.
p,.

Xo63

X, 64
X, 65
X. 66
X. 67

Xs68
1
"0
x, 2
X. 3
X. 4

x,.

xl1
x12

x,.

x,.

7

J

H

G

FED

C

B

2

A

G8.69PIN/HB.69PIN

68 Pin Ceramic (G8) or Plastic (H8) Pin Grid Array

JO.64PIN

V,.P, 61
V•.P. 62

K

9

~~~

0@0000000@0
000000000
L

11

10

Pin

Name

Pin

Name

Pin

Name

Pin

Name

A2
A3
A4
A5
A6
A7
AS
A9
Al0
Bl
B2
B3
B4
B5
B6
B7
BS

NC

B9
Bl0
Bll
Cl
C2
Cl0
Cll
01
02
010
011
El
E2
ElO
Ell
Fl
F2

X12
X14
NC

FlO
Fll
Gl
G2
GIO
Gil
HI
H2
HIO
Hll
Jl
J2
Jl0
Jll
Kl
K2
K3

VOO
ClK Y

K4
K5
K6
K7
K8
K9
Kl0
Kll
l2
l3
l4
l5
l6
L7
lS
L9
L10

P20
P22
P24
P26

Po· Yo
Xl
X3
X5
X7
X9
Xli
X13
P2• Y2
Pl· Y1
Xo
X2
X4
X6
Xs
XIO

P4• Y4
P3• Y3
TSl
X15
P6• Y6
P5• Y5
SUB
RNO
GNO
P7• Y7
ClK X
ACC
Pg. Y9
Ps• Ys

Pll· Yll
PIO· YIO
TSX
TC
P13· Y13
P12· Y12
TSM
PREl
P15• Y15
P14• Y14
P34
ClK P
NC
P16
PIS

P28
P30
P32
P33
P17
P19
P21
P23
P25
P27
P29
P31
NC

40 P,.
39 P21
39 P"

37 P,.
36 p..

0

35 P,.
34 p..

33 P"

32 P,.
31 P,.
30 p..

5
6
7
8

p.,

29
29 P32

9

~~~~~~
~~~~~
~~~~~N~~~~~
~~~~~

27 P33

~~~~~g~~~~~
d
a...l-d
65-637'

S8-Lead Plastic J-Leaded chip Carrier - Rl Package
3-410

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2210
the least Significant Bitsl. Data present at
the X and Y inputs are clocked into the
input registers on the rising edge of the
appropriate clock.

Functional Description
General Information

The TMC2210 consists of four functional sections: input
registers, an asynchronous multiplier array, an adder and
Data Outputs
output registers. The input registers store the two 16-bit
There is a 35-bit two's complement or
numbers which are to be multiplied and the control lines P34-0
unsigned magnitude result that is the sum
which control the input numerical format Itwo's
of
the products of the two input data
complement or unsigned magnitude\, output rounding,
values and the previous products which
accumulation and subtraction. The round control is used
have been accumulated. The output is
when a single-word output is desired. Each number is
divided into two 16-bit output words, the
independently stored, simplifying multiplication by a
MSP and lSP, and one 3-bit output word,
constant. The output registers can be preloaded with a
the XTP. The MSB of the XTP is the sign
constant to provide the sum of products plus a constant.
bit if two's complement notation is used.
The asynchronous multiplier array uses a modified
Booth's algorithm and has been designed to handle two's
complement or unsigned magnitude numbers. The output Clocks
registers hold the product as two 16-bit words and one
ClK X
ClK X is the clock input for the X15-0 data
3-bit word: the MSP, the lSP and the XTP. Three-state
ClK Y
register. ClK Y is the clock input for the
output drivers permit the TMC2210 to be used on a bus ClK P
Y15-0 data register. ClK P is the clock
or allow the outputs to be multiplexed over the same
input for the product register.
16-bit output lines. The lSP is multiplexed with the Y
input.
Controls
The TMC2210 has three clock lines, one for each of the
input registers and one for the product register. Data
present at the inputs of these registers are loaded into
the registers on the rising edge of the appropriate clock.
The Round IRND\, Two's Complement ITCI, Accumulate
IACCI and Subtract ISUBI inputs are registered and all
four bits are clocked in on the rising edge of the logical
OR of both ClK X and ClK Y. Problems with the loading
of these four control signals can be avoided by the use
of normally lOW clocks.

TSX,
TSM, TSl

TSX, TSM and TSl are three-state enable
lines for the XTP, the MSP and the lSP,
respectively. The output driver is in the
high-impedance state when TSX, TSM or
TSl is HIGH and enabled when the
appropriate control is lOW.

PREl

PREl IPreloadl is an active HIGH control
which has several effects when active. First.
all output buffers are forced into the highimpedance state. Second, when any or all
of TSX, TSM and TSl are also HIGH,
external data present at the output pins
will be preloaded into the corresponding
section of the output register on the rising
edge of ClK P. Normal data setup and hold
times apply both to the logical AND of
PREl and the relevant three-state control
ITSX, TSM, TSll and to the data being
preloaded. These setup and hold times are
with respect to the risi ng edge of ClK P.

RND

RND IRoundl controls the addition of a one
to the MSB of the lSP for rounding. When
RND is HIGH, a one is added to the MSB
of the lSP for rounding the product in the
MSP and XTP lif appropriatel rather than
truncating.

Signal Definitions
Power
VDD, GND

The TMC2210 operates from a single + 5V
supply. All power and ground lines must be
connected.

Data Inputs
X15-0,
Y15-0

There are two 16-bit two's complement or
unsigned magnitude data inputs, labeled X
and Y. The Most Significant Bits IMSBs\,
denoted X15 and Y15, carry the sign
information when two's complement
notation is used. The remaining bits are
denoted X14-0 and Y14-0 Iwith Xo and YO

For More Information call 1-800·722·7074.

Raytheon Semiconductor

3-411

I

TMC2210
Controls (cont.)
TC

TC ITwo's Complementl controls how the
device interprets data on the X and Y
inputs. When TC is HIGH, both inputs are
two's complement inputs. When TC is lOW,
both inputs are unsigned magnitude only
inputs. The necessary sign extension for
negative two's complement numbers is
provided internally.

ACC

When ACC IAccumulatel is HIGH, the
content of the output register is added to
or subtracted from the next product
generated, and the result is stored back
into the output registers on the next rising
edge of ClK P. When ACC is lOW, multiplication without accumulation is performed,
and the next product generated will be
stored into the output registers directly. This
operation is used for the first term in a
summation to eliminate the need for a
separate "clear" operation.

SUB

The SUB ISubtractl control is used in
conjunction with the ACC control. When
both the ACC and SUB controls are HIGH,
the content of the output register is
subtracted from the next product generated,
and the difference is stored back into the
output register. When ACt is HIGH and
SUB is lOW, the content of the output
register is added to the next product
generated and the sum is stored back into
the output register. Note that the previous
output is subtracted from the product, not
the product from the previous output.

No Connects
NC

The pin grid array version of the TMCZZlO
has four pins which are not connected
internally.

Package Interconnections
Signal
Type

Signal
Name

Power

VOO
GNO

Supply Voltage
Ground

FlO
El

49
16

17, 18, 19, 20
53, 54

Data Inputs

X15-0

X Input Word

56-64, 1-7

1-10, 63-68

Y15-0

Y Input Word

Cll, Bl0, AlO, B9, A9, B8, A8, B7,
A7, B6, A6, B5, A5, B4, A4, B3
Jl, J2, Hl, H2, Gl, G2, Fl, F2,
E2, 01, 02, Cl, C2, Bl, B2, A3

24-17, 15-8

45-52, 55-62

Data Outputs

P34 -0

Product Output

JlO, Kll, KlO, 19, K9, l8, K8, l7, K7,
l6, K6, l5, K5, l4, K4, l3, K3, l2,
K2, Jl, J2, Hl, H2, Gl, G2, Fl, F2,
E2, 01, 02, Cl, C2, Bl, B2, A3

43-17, 15-8

26-52, 55-62

Clocks

ClK X
ClK Y
ClK P

X Register Clock
Y Register Clock
P Regsiter Clock

El0
Fll
Jll

51
50
44

15
16
25

Controls

TSX
TSM
TSl
PREl
RNO
TC
ACC
SUB

XTP Three-State
MSP Three-State
lSP Three-State
Preload
Round
Two's Complement
Accumulate
Subtract

Gl0
HlO
ClO
Hll
011
Gll
Ell
010

47
45
55
46
54
48
52
53

22
24

NC

No Connection

Kl, L10, Bll, A2

-

-

No Connects

3-412

Function

G8, H8 Package Pins

Raytheon Semiconductor

JO, NO Package Pins

Rl Package Pins

11
23
12
21
14
13

For More Infonnalion call 1-800-722-7074.

TMC2210
Figure 1. Fractional Two's Complement Notation
BINARY POINT
x" X14 X13 x" x" x" x,

,.' ,.' ,.'

V'5 v14 V13 Y12 Y11 v,o

,,0

X
,,0

,.' ," ,"

P34 P33 P32 Pat P30 P"

,,' " " "
XTP

,4

,,5

,0

p,.

,4

,,5

x,

X6

,-6

'" ,'.

29

V,

v.

,-6

,..
'"

x.

V,

V6

,4

,.5

,.6

'"

MSP

x,

x,

x,

x,

Xo

2"10 211 212 2 13 214

i 1S

v,

Vo

V5

V,

V,

V,

29 flO 2"11 2"12 2 13 2"14 2"15

P" P'6 P'5 P" P" P" P"

,.' ,.' ,.'

X5

". ,.'

P20 P"

p,.

P" P'6 P'5

2,10 ill 2"12 213 214 2 15

SIGNAL

DIGIT VALUE

SIGNAL

DIGIT VALUE

P14Ip13lp12Ip11lplOIPglpslp7

f16If1712'1~Jfl~Jf21f21If221 2 23

P6
224

P5

P,

2 25 2 26

P,
2"27

P,

P,

Po

2 28 229 i 30

SIGNAL
DIGIT
VALUE
2210,1

LSP

Figure 2. Fractional Unsigned Magnitude Notation
BINARY POINT
x'5 x14 x13 X12

," ,"

,.'

,-4

x11

XlO x,

,.' ,.' ,'.
,-6

V" Y14 Y13 Y12 Y11 VlO

X

P341 P331 P32

,"
Pat

,.' ,.'

,"

x.

,.'

,-6

x,

X6

x,

,-4

,,5

XTP

x,

x,

x,

Xo

DIGIT VALUE

SIGNAL

V,

v.

V,

,"

,..

i9 i 10 ill i12 i 13 214 i 15 i 16

,.6 ,"

,-8

SIGNAL

i9 i 10 ill i 12 i 13 214 i15 i 16

V6

V5

Pao P29 P28 P27 P26 P25 P24 P23 P22 P21

,'1,,',0 ,.' ,.' ,-3

x,

V,

V,

V,

v,

Vo

P20 P19 Pta P17 P16

,.' ,.10 ,." "" ,,13 ,.14 ,'"

DIGIT VALUE

Plsl P141 Pta P121 Pl1 Pto I psi psi P71 P61 psi P4 1Pal P21 P, I Po I SIGNAL

,"6 ""1,.'.1,.,, ,.20 1,," ,,"1,."1,,"1,.25 1,,'61,."1,.'.1,.29 1,,30 1,-3'1,.321el~IJE

MSP

LSP

2210,2

Figure 3. Integer Two's Complement Notation
BINARY POINT
X15 x14 X13 x" x"
_2 15 ,14

X

,,34

,33
XTP

,32

,3' ,"

,29

p,.

P" P26 P25 P24 P" P" P" P20 P"

". ,"

,'6 ,25 ,24

," ,"

MSP

For More Information call 1-800-722-7074.

,21

,20

p,.

," ,"

x,

X6

X5

x,

Xo

SIGNAL

,10

,. "

,6

,5

" " " "

,0

DIGIT VALUE

V,

V6

V5

V,

v,

Vo

SIGNAL

"

,6

" " " " "

,0

DIGIT VALUE

P,

P6

P5

P,

Po

SIGNAL

"

,6

,5

" " " "

"

," ," ," ," "

P" P'6 P" P14 P" P" P" P" P,

," ,'. ,"

216 215 ,14

X,

x.

V" V14 Y13 V12 V" V" V,
_2 15 ,14

P34 P33 P32 P3t P30 P"

,13

xlO x,

," ," ," ," "

Raytheon Semiconductor

v.

,.
p.

,.

LSP

x,

x,

V,

P,

V,

P,

P,

,0 DIGIT VALUE
2210,3

3-413

I

TMC2210
Figure 4. Integer Unsigned Magnitude Notation
BINARY POINT

x"

X14

X13

X12

X11

X'O

X9

X8

x,

X6

X5

x,

X3

x, x, '0 SIGNAL

,'5

214

213

212

211

,10

,9

,8

"

,6

,5

"

,3

" "

,0

DIGIT VALUE

Y15

Y14

Y13 Y12 Yt1

Yl0

V9

V8

V,

V6

V5

V,

V3

V,

Vo

SIGNAL

,'5

214

213

212

211

,'0

,9

,8

"

,6

,5

"

,3

" "

,0

DIGIT VALUE

P20 P19 "8 P17 P16 "5 P14 Pt3 P12 P11

'10

'9

'8

'5

SIGNAL

,6

,5

" "
" "

'0

,8

"
"

'3

,9

"
"
LSP

'6

,10

,0

DIGIT VALUE

X

P341 P331 P32
23412331232

P3t

II
p30

i" 1,30 1,'9

228 227

'24

P22

'"

,'6 ,:>5 224 223 222

221

P28 P27 P26 P25

P29

XTP

P23

219

220

218 217

216 215

214

213

212

211

MSP

,3

V,

2210.4

Figure 5. Timing Diagram
NON·MULTIPLEXED INPUTS
(X 1N, CCNTROLS)

INPUT CLOCKS
(CLKX, CLKY)

•••

XXX
_

XXX ...
_

[~tS-1AtHII~
----!..-[--;ppwl~~ -----I

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

tMA

OUTPUT CLOCK

".~.,.~ J

I

COO"",

MULTIPLEXEDLEADS~ltDlSr-

n
1\' - - - ::-:Itpwl-'-------.......
t1 " r- I

tENA--I

(YIN' LSPO UT)

INPUT DATA

NON·MULTIPLEXED
OUTPUTS (XTP, MSP)

INPUT DATA

I

t:= 1,~___~_:....r_tDiS
~_D_AT_A_OU_T_..... I
DATA OUT

1 \1'-----

I::=tS

I

tH~
iI

PRELOAD IN DATA

PRELOAD IN DATA

~I
I I

PREVIOUS
CYCLE OUTPUT
PREL

3-414

/

------------------------~

Raytheon Semiconductor

~

~~---2210.5

For More Infonnation caJI1-800-722-7074.

TMC2210
Figure 7. Equivalent Output Circuit

Figure 6. Equivalent Input Circuit

SUBSTRATE

SUBSTRATE

+---+--0 OUTPUT

CONTROL 0---4"----+
INPUT

2210.7
2210.6

Figure 8. Threshold Levels for Three-State Measurements
TRIM, TRll,

I,---~----------,I

'ENA

TSL

o.sV
THREEoSTATE
OUTPUTS

J

----i==

-r

I

2210.8

D.SV

Preload Truth Table
PREL1,2

TSX1

TSM1

TSL1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Notes:

XTP
Register - Output
Register - Output
Register - Output
Register - Output
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z Preload
Hi-Z Preload
Hi-Z Preload
Hi-Z Preload

MSP
Pin
Pin
Pin
Pin

Register - Output
Register - Output
Hi-Z
Hi-Z
Register - Output
Register - Output
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z Preload
Hi-Z Preload
Hi-Z
Hi-Z
Hi-Z Preload
Hi-Z Preload

LSP
Pin
Pin

Pin
Pin

Register - Output
Hi-Z
Register - Output
Hi-Z
Register - Output
Hi-Z
Register - Output
Hi-Z
Hi-Z
Hi-Z Preload
Hi-Z
Hi-Z Preload
Hi-Z
Hi-Z Preload
Hi-Z
Hi-Z Preload

Pin
Pin
Pin
Pin

1. PREL, TSX, TSM, and TSl are not registered.
2. When PREL is HIGH, any change of output register Ifor those outputs in which the three-state control is lOWI is inhibited.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-415

TMC2210
Absolute maximum ratings (beyond which the device may be damagedl 1
Supply Voltage ......................................................................................................................................................................................... - 0.5 to + 7.0V
Input Voltage .................................................................................................................................................................................. - 0.5 to IVDD + o.5)V
Outputs
Applied voltage .................................................................................................................................................... - 0.5 to IVDD + 0.5)V 2
Forced cu rrent .......... ....... ..... ........................ .......... ................... ................. ............. ............................ ............... .......... - 1.0 to 6.0mA 3.4
Short-circuit duration Isingle output in HIGH state to ground) ......................................................................................... 1 Second
Temperature
Operating, case .............................................................................................................................................................. - 60 to + 130°C
junction ........................................................................................................................................................................... 175°C
Lead, soldering 11 0 seconds) .......................................................................................................................................................... 300°C
Storage ............................................................................................................................................................................ - 65 to + 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT Implied.
2. Applied voltage must be current limited to specified range.
3.

Forcing voltage must be limited to specified range.

4. Current is specified as conventional current flowing into the device.

Operating conditions
Temperature Range
Parameter

3-416

Min

VDD

Supply Voltage

4.75

VIL
VIH

Input Voltage, Logic LOW
Input Voltage, Logic HIGH

2.0

IDL
IOH

Output Current, Logic LOW
Output Current, Logic HIGH

TA
TC

Ambient Temperature, Still Air
Case Temperature

Commercial
Nom
5.0

Max
5.25

Min
4.5

0.8

5.0

Max

V

0.8

V
V

4.0
-2.0

rnA
rnA

125

°c
°c

70
-55

Raytheon Semiconductor

Units

5.5

2.0
4.0
-2.0

0

Military
Nom

For More Information call 14100-722-7074.

TMC2210
DC characteristics within specified operating conditions

Parameter
100Q

1000

Conditions

Supply Current, Quiescent

VOO=Max, VIN=OV
All Except
TMC2210-45, -55, Outputs Open
VOO=Max, TSl, TSM, TSX=5V
f=15MHz
f=10MHz
f=6.2MHz

Supply Current, Unloaded 1

Input Current, Logic lOW

III

P15-0' Y15-0
VOO=Max, VIN=VOO
X15-0' Controls, Clocks
P15-0' Y15-0

VOL
VOH

Output Voltage, logic lOW
Output Voltage, logic HIGH

VOO = Min, 10l = + 4.0rnA
VOO=Min, 10H= -400pA

10Zl
IOZH

Hi-Z Output leakage Current, Output lOW
Hi-Z Output leakage Current, Output HIGH

VOO=Max, VIN=OV
VOO=Max, VIN=VOO

CI
Co
ClIO

Input Capacitance
Output Capacitance
Ito Capacitance

f=1.0MHz, TA=25°C
f=I.DMHz, TA=25°C
f=I.DMHz, TA=25°C

Note:

1. Supply current is proportional to fCLK. typically 5mA per MHz.

Units

10
0.5

rnA
rnA

75
50
30

75
50
30

rnA
rnA
rnA

-10
-40

-10
-40

rnA
rnA

10
40

.10
40

rnA
rnA

5
0.5

VOO-Max, VIN=OV
X15-0' Controls, Clocks

Input Current, logic HIGH

IIH

Temperature Range
Military
Commercial
Min
Min
Max
Max

0.4

D.4

2.6

2.6

V
V

-40
-40

-40
-40

pA
pA

10
10
15

10

10
15

pF
pF
pF

AC characteristics within specified operating conditions 1
Temperabn Range

Parameter

tMA

Notes:

Multiply-AccutnJlate lime

Conditions

Commercial
Min
Max

TMC2210-95
TMC2211HlO
TMC221!H35

Military
Min
Max
95
80
65

95

80
65
15
15

tPvVL Oock Pulse Width, LON

TMC2210-95
TMC2211HlO
TMC2210-65

15
15
15

25

tPtNH CIcok PUlse Width. HIGH

TMC2210-95
TMC2211HlO
TMC221!H35

15
15
15

15
15
25

1.
2.

Units

ns
ns
ns
ns
ns
ns
ns
ns
ns

AI 1ransitions ara measured at a 1.5V lew! except lENA and tolS which are measured as shown in Rgura 8.
Voo = Min.

For More Infomialion call 1-800-722·7074.

Raytheon Semiconductor

3-417

I

TMC2210
AC characteristics within specified operating conditions 1(cont.)

Parameter
Input Setup TIme

15

Conditions

Input Hold TIme

Output Delay

to

tENA

tolS

Notes:

1.

2.

3-418

Three-5tate Output
Enable Delay

Three-5~te

Output
Disable Delay

Units

20
20
15

20
20
25

ns
ns
ns

30
30

30

30
30
25

ns
ns
ns

0
0
0

0
0
3

ns
ns
ns

3
3
3

3
3
3

ns
ns
ns

Da~,ACC,SUB,RND,TC

TMC221(}95
TMC221 0-80
TMC221 0-65
PREL TSL, TSM. TSX
TMC221(}95
TMC2210-80
TMC221 0-85

tH

Temperatln Range
Mirrtary
Commercial
Min
Max
Min
Max

Da~,ACC,SUB,RND,TC

TMC221(}95
TMC221 0-80
TMC2210-65
PREL TSL, TSM, TSX
TMC221(}95
TMC221 0-80
TMC221 0-85
VDD =Min, CLOAD =40 pf
TMC221 0-95
TMC221 0-80
TMC221 0-85
VDD =Min, CLOAD =40 pf
TMC221 0-95
TMC221 0-80
TMC221 0-85
VDD =Min, CLOAD =40 pf
TMC221 0-95
TMC221 0-80
TMC221 0-85

40
35

35

40

35

35

ns
ns
ns

40
30

40
35
302

ns
ns
ns

35
30
302

ns
ns
ns

30
35
30

30

AlI1ransitions are measured at a 1.5V lew! exospt tENA and tOIS which are measured as shown in Figure 8.
Voo =Min.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2210
Application Discussion

and this operation:

16/8) x 12/8) = 12/64

Multiplication by a Constant
Multiplication by a constant requires that the constant be
loaded into the desired input register and that the
register not be loaded again until a new constant is
desired. The multiply cycle then consists of loading new
data and strobing the output register.
Selection of Numeric Format
Essentially, the difference between integer, mixed and
fractional notation in system design is only conceptual.
For example, there is no difference between this
operation:

6x2=12

The difference lies only in constant scale factors lin this
case, a factor of 8 in the multiplier and multiplicand and
a factor of 64 in the product). However, these scale
factors do have implications for hardware design.
Because common good design practice assigns a fixed
value to any given line land input and output signals
often share the same line), the scale factors determine
the connection of the output pins of any multiplier in a
system. As a result, only two choices are normally made:
integer and fractional notation. If integer notation is
used, the LSBs of the multiplier, multiplicand and product
all have the same value. If fractional notation is used,
the MSBs of the multiplier, multiplicand and product all
have the same value.

Ordering Information
Multiplyl
Product
Number

Accumulate
Time Ins)

Temperature

Package

Screening

Package
Marking

TMC2210G8C65
TMC2210G8C80
TMC2210G8V65
TMC2210G8V80
TMC2210G8V95

65
80
65
80
95

STD: TA =0 to 700(;
STD: TA =0 to 700(;
EXT: Te =-55 to 1250(;
EXT: Te =-55 to 1250(;
EXT: Te =-55 to 1250(;

Commercial
Commercial
MIL-STD-883C
MIL-STD-883C
MIL-STD-883C

68-pin Ceramic Pin Grid Array
68-pin Ceramic Pin Grid Array
68-pin Ceramic Pin Grid Array
68-pin Ceramic Pin Grid Array
68-pin Ceramic Pin Grid Array

2210G8C65
221OG8C80
2210G8V65
221OG8V80
2210G8V95

TMC2210H8C65
TMC2210H8C80

65
80

STD: TA =0 to 700(;
STD: TA =0 to 700(;

Commercial
Commercial

68-pin Plastic Pin Grid Array
68-pin Plastic Pin Grid Array

2210H8C65
2210H8C80

TMC2210JOV80
TMC2210JOV95

80
95

EXT: Te =-55 to 1250(;
EXT: Te =-55 to 1250(;

MIL-STD-883C
MIL-STD-883C

64-pin Hermetic Ceramic DIP
64-pin Hermetic Ceramic DIP

221OJOV80
221OJOV95

TMC2210NOC65
TMC2210NOC80
TMC2210NOC95

65
80
95

STD: TA =0 to 700(;
STD: TA =0 to 700(;
STD: TA =0 to 700(;

Commercial
Commercial
Commercial

64-pin Plastic DIP
64-pin Plastic DIP
64-pin Plastic DIP

2210NOC65
2210NOC80
2210NOC95

TMC2210R1C65
TMC2210R1C80

65
80

STD: TA =0 to 700(;
STD: TA =0 to 700(;

Commercial
Commercial

68-Lead Plastic J..Leaded Chip Carrier
68-Lead Plastic J..Leaded Chip Carrier

2210R1C65
2210R1C65

40G02412.Rev E 8193

For More Information call 1-800-722·7074.

Raytheon Semiconductor

3-419

I

TMC2210

3-420

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TMC3211
TMC3211
Integer Divider
32-Bit; 20 MOPS

Description

Applications

The TMC3211 is a fast monolithic two's complement
integer divider which can divide a 32-bit dividend by a
16-bit divisor to produce a 32-bit quotient, with a
maximum pipelined throughput of 20 MOPS (Million
Operations Per Second). Data is input on separate
busses, and quotients are available on a 32-bit output
bus with synchronous three-state enable. All data inputs
and outputs are registered and TTL compatible. All input
and output signal timing is referenced to the rising edge
of Clock.

•
•
•
•
•

The TMC3211 has a single system clock and separate
load enable controls for the dividend and divisor
registers. This allows the device to be used in
applications requiring division by a constant. Underflow
automatically produces the expected zero quotient, and
dividing by zero sets a divide-by-zero output flag.

Functional Block Diagram

The internal architecture of the TMC3211 allows all 32bit two's complement integer dividends and nonzero 16bit two's complement integer divisors, without
prenormalization. The output quotient format is 32-bit
integer.

Graphics and image processors
Matrix operations and geometric transforms
Perspective extraction
Radar signal proceSSing
Range scaling

ENX >---cr~-,

r~--'b------< ENY

elK )--I-;";::~"",...J

The TMC3211 makes a full-preciSion, full-speed divide
function available to designers of workstations, image
processors, and radar systems who need to perform
perspective extractions, matrix operations, range
scaling, and other complex functions.

Features
•
•
•
•
•
•

32-bit by 16-bit fixed-point integer division with
32-bit quotient
20 MHz clock rate and pipelined throughput rate
Three-bus VO architecture allows unrestricted
throughput
Easy system interfacing
Status flags for divide-by-zero and inexact result
All inputs and outputs TTL compatible

For More Information call 1-800-722-7074.

20
OE >------.,~

Raytheon Semiconductor

DZERO,INX

3-421

I

TMC3211
Pin Assignments

Functional Description

120-Pin Plastic Pin Grid Array - H5 Package

General Information

Pin

Name

Pin

C3
82
81
03
C2
Cl
02
E3
01
E2
El
F3

VOO
Y15
YEN
GNO

13
M2
N2
L4
M3
N3
M4
L5
N4
M5
N5

F2

Fl
G2
G3
Gl
HI
H2
H3
Jl
J2
Kl
J3
K2
L1
Ml
K3
12
Nl

VOO
Y16
Y17
GNO
Y1B
Y19
Y20
VOO
Y21
Y22
GNO

Y26
Y27
Y2B
VOO
Y29
. Y30
Y31
GNO
VOO
GNO

Pin

Name

Pin

GNO

L11
M12
M13

VOO
GNO

Cll
812
A12
Cl0
811
All
810
C9
Al0
89
A9
CB
8B
AS
87
C7
A7
A6

Xu
Xl
VOO
X2
X3
X4
GNO

Kll

L12
L13
K12

Jll

X5

K13

Xs

J12
J13
Hll
H12
H13
G12
GIl
G13
F13
F12
Fll
El3
E12
013
Ell
012
C13
813
011
C12
A13

X7

16
M6
N6
M7
L7
N7
NB
MB
LB
N9
M9
Nl0
L9
MlO
Nll
N12
L10
MIl
N13

VOO
Y23
Y24
Y25
GND

Name

Xa
Xg
Xl0
Xll
VOO
X12
Xu
X14
X15
XEN
CLK
OEO
°31
°30
°29
°28
°27
GNO
°26

°25
VOO
GNO
°24
°23
VOO
°22
°21
°20
GNO
°19
°lB
VOO
°17
°16
°15
°14
VOO
°13
°12
°Il
GNO
°lO

Og
°B
VOO
GNO
VOO

B6

C6
A5
85
A4
C5
B4

Name
GNO
°7

Os
~
~
03
°2
°1

00
OZ
REM
YO
Yl
Y2
Y3
Y4
Y5
Y6
Y7
YB
Y9
YlO

The TMC3211 consists of input registers, a pipelined array
divider, and output Iquotient! registers. The 16-bit divisor and
32 -bit dividend input registers can each be loaded independent
y using the two synchronous load enable controls. The
divider is a 16 -stage pipelined non -restoring array which
produces a 32 -bit quotient and condition flags which indicate
an attempted division by zero, or operations which yield a
non-zero remainder or inexact result. The 32-bit parallel
quotient output register includes three -state output drivers
with synchronous enable control, which permits multiple
TMC3211s to be operated in parallel or connected directly to a
system bus.
The TMC3211 requires a total of 19 clock cycles to generate a
full 32 - bit quotient result. Once the internal pipeline is full, a
new quotient is available at the output every clock cycle.

Signal .Definitions
Power
VDD, GND

VO~

Clock
ClK

C4

Yll
Y12
Y13
Y14
GNO

83
Al

VOO
GNO

A3
A2

@ @ @ @ @ @ @ @ @ @ @

4:

@ @

to

@ @

to

© @ @

@ @

(1)

Ii) @ @

5:
6:

Y31-0

3-422

The 16-bit Divisor is presented through the
registered X input port. X15 is the sign bit. The
lSB is XO.

@@to©Ii)©©©©©©@@

r;-======~~~© ©@@

Top View

Cavity Up

4)

©

The 32 -bit Dividend is presented through the
registered Y input port. Y31 is the sign bit. The
lSB is YO.

@ @

@@@@@@@@@@@@@

71 @ @ to
8 @ @ to
9 @ @ (1)
10 @ @ ©
11 @ @ to
12 @ @ @
13 @ @ @

The TMC3211 has a single Clock input. All input
and output signal timing is referenced to the
rising edge of Clock.

Inputs

NMLKJHGFEDCBA

I!
2
3

The TMC3211 operates on a single +5V supply.
All power and ground lines must be connected.

@ @

Ii) @ @

©

@ @

@

@ @

Outputs

031-0

The current Ouotient is available on the
registered 0 output bus. 031 is the sign bit.
The lSB is 00.

© @ @ © © ©> © @ @

@ @ @ @ @ @ @ @
@ @

@ @

@ @ @ @ @ @ @ @

Raytheon Semiconductor

For More Information caJI1-800·722·7074.

TMC3211
Controls

Flags

YEN

Data present at the Dividend input Y31-0 is
latched into the input registers on the rising
edge of clock when the enable control YEN is
LOW.

DZ

Whenever a zero divisor is input, the resulting
invalid output quotient will be accompanied by a
registered Divide-By-Zero Flag HIGH.

REM

Whenever a division operation leaves a nonzero
remainder, the resulting quotient is accompanied
by a registered nonzero Remainder Flag HIGH.

Data present at the Divisor input X15 - 0 is
latched into the input registers on the rising
edge of clock when the enable control XEN is
LOW.
OEQ

The quotient output bus 031- 0 and flags DZ
and REM arB in the high -impedance state
when the registered Output Enable OEQ is HIGH.
When OEQ is LOW, they are enabled on the
next clock cycle.

Package Interconnections
Signal
Type
Power

Signal
Name

Function

H5 Package

VDD

Supply Voltage

GND

Ground

CLK

System Clock

M9

Y31-O

Dividend Data

X15-0

Divisor Data

Ml, L1, K2, Kl, J2, Jl, H2, HI,
Gl, Fl, F2, El, E2, 01, D2, Cl,
B2, A2, A3, 84, C5, B5, A5, C6,
86, A6, A7, C7, B7, A8, B8, CD
LB, M8, N8, N7, M7, N6, M6, 16,
N5, M5, N4, M4, N3, M3, N2, M2

Outputs

031-0

Ouotient Data

19, M10, NIl, NI2, L10, N13, M13, L13,
K12, Kl3, J12, J13, H12, H13, GIl, G13,
F13, F12, E13, E12, 013, Dl2, C13, B13,
B12, A12, C1O, B11, All, B10, eg, A10

Controls

YEN
XEN
OEO

Dividend Write Enable
Divisor Wr~e Enable
Ouotient Dutput Enable

Bl
N9
NIO

Flags

DZ
REM

Divide- By Zero Rag
Inexact Remainder Flag

B9
A9

Index Pin

04

Clock
Inputs

No Connect

For More Information call1-BOO-722-7074.

Raytheon Semiconductor

B3, A4, A13, Dll, Fll, G12, J11, K11,
L11, L7, L4, L2, J3, G3, F3, C2, C3
AI, C4, Cll, C12, Ell, Hll, L12, M12,
M11, L5, 13, Nl, K3, H3, G2, E3, D3

3-423

I

TMC3211
Applications Discussion
Division Using A Constant
By utilizing the separate input data register load enable
controls, the TMC3211 can perform division by a

constant. The data currently held remain in the input
registers until updated by the user.

Data Formats
The TMC3211 supports fixed-point two's complement
data formats. By keeping track of the binary points of
the input data, the user can then interpret the resulting

quotient properly. Two possible binary weightings of the
input and output bits are as follows:

Figure 1. Integer Data Format
Pin
V
X
Q

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 Dll DID
_231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 2 15 214 213 212 211 2 10
_2 15 214 213 212 211 2 10
_231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210

D9

D8

D7

D6

D5

D4

D3

D2

D1

DO

29

28

27

26

25

24

23

22

21

20

29

28

27

26

25

24

23

22

21

20

29

28

27

26

25

24

23

22

21

20

Figure 2. Fractional Data Format
V

_20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31
_20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15

X
Q

_2 15 .2 14 213 212 211 210 29

28

27

26

25

24

23

22

21

20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16

where a leading minus sign indicates a sign bit.
Care must be taken when adopting fractional data
formats. By observing the binary weighting applied to
the input data in the dividend and divisor, the binary
point of the quotient can then be correctly established.
The difference lies only in constant scale factors, which
must be considered in order to maintain a data format
which is compatible with the bit weighting of the
hardware system. The two most common choices are
fractional and integer notation. If integer notation is
used, the LSBs of the dividend, divisor, and quotient all
have the same value. With fractional notation the MSBs
are all of equal weight.

Divide by Zero

Negative Full-Scale Overflow
Due to a finite data word width, a two's complement
overflow error occurs under the following unique
condition:
Divisor Y= 80000000H 1- Full-Scalel
Dividend X= FFFFH 1-11
Result:

The flag DZ indicates that the divisor input for the
current calculation was a zero, independent of the
dividend. Dividing by zero is an undefined operation
yielding a meaningless quotient. Thus, this flag must be
monitored to guard against possible errors.

3-424

Inexact Results
The flag REM is provided to indicate that the current
quotient left a nonzero remainder and was truncated
toward zero.

Ouotient 0 = 80000000H 1- Full-Scalel
As stated above, this is due to a limitation in the number
of bits available to indicate a positive full-scale quotient.
and data overflows into the MSB position to indicate an
incorrect sign.

Raytheon Semiconductor

For More Infonnadon call 1-800-722-7074.

TMC3211
Figure 3. Timing Diagram
19

~tCV--1

XXX)¢(

VI

X15-0

0000

NOTE 1
Xl

XXXXXXXXXXXX>
QX'IY

'0000

tlltA

£5000

I

to

Notes:
1. Demonstrates division by a constant, 02

om

~

~

1;=

f;=

=f

031-0' OZ. REM'

2. Assumes

21

20

Do

>K

tHO
°1

I

X

°2

x=

Y2/X 1.

LOW.

Figure 4. Equivalent Input Circuit

I

Figure 5. Equivalent Output Circuit

voo
n SUBSTRATE

01

01

...--4_-0 OUTPUT

CONTROL o-...;",Vv-......- .
INPUT

02
p WELL
~

.". GNO

GNO

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-425

TMC3211
Absolute maximum ratings Ibeyond which the device may be damaged) 1
Supply Voltage ........................................................................................................................................................................................................................................ - 0.5 to + 7.0V
Input Voltage .............................................................................................................................................................................................................................. -0.5 to (VOO + 0.5)V
Olllput
Applied voltage 2 ............................................................................................................................................................................................ -0.5 to (VOO + 0.5)V
Forced current 3.4 ........................................................................................................................................................................................................ -3.0 to 6.0mA
Short-circuit duration (single output in HIGH state to ground) ......................................................................................................................................... 1 sec
Temperature
Operating, case .......................................................................................................................................................................................................... - 60 to + 130°C
iunction ....................................................................................................................................................................................................................... 175°C
lead, soldering (10 seconds) ..................................................................................................................................................................................................... 300°C
Storage ........................................................................................................................................................................................................................ - 65 to + 15(JOC
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to GND.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

Operating conditions
Temperature Range

Standard
Parameter

3-426

Test Conditions

Min

Nom

Max

5.0

5.25

V

O.B

V
V

4.0
-2.0

rnA
rnA

50

ns

VOO

Supply Voltage

4.75

Vll
VIH

Input Voltage, logic lOW
Input Voltage, logic HIGH

2.0

IOl
IOH

Output Current, logiC lOW
Output Current, logic HIGH

tCY

Cycle Time

VOO

tpWl
tpWH

Clock Pulse Width, LOW
Clock Pulse Width, HIGH

VOO - Min
VOO = Min

ts
tH

Input Setup Time
Input Hold Time

TA

Ambient Temperature, Still Air

=

Min

Units

15
15

ns
ns

12
6

ns
ns

0

Raytheon Semiconductor

70

°c

For More Information call HIOO·722·7074.

TMC3211
DC characteristics within specified operating conditions

1

Temperature Range
Parameter

Standard
Min
Max

Test Conditions

100Q

Supply Current, Quiescent

100U

Supply Current, Unloaded

IlL
IIH

Input Current, Logic LOW
Input Current, Logic HIGH

VOO = Max, VIN = OV

VOL
VOH

Output Voltage, Logic LOW
Output Voltage, Logic HIGH

VOO = Min, 10L = Max
VOO=Min,IOH=Max

10ZL
10ZH
lOS

Hi-Z Output Leakage Current. Output LOW
Hi-Z Output Leakage Current, Output HIGH
Short-Circuit Output Current

VOO=Max, VIN=OV

CI
Co

Input Capacitance
Output Capacitance

TA=25°C, f=lMHz
TA=25°C, f=lMHz

Note:

1. Actual test conditions may vary from those shown. but guarantee operation as specified.

Units
rnA

5
150

Voo=Max, VIN=OV
VOO=Max, OEQ=5V, f=20MHz

rnA

-10

/LA
/LA

10

VOO=Max, VIN=VOO

0.4

V
V

2.4
-40
40
-150

VOO=Max, VIN=VOO
VOO=Max, Output HIGH, one pin to
ground, one second duration max.

/LA
/LA
rnA

10
10

pF
pF

AC characteristics within specified operating conditions
Temperature Range
Standard
Parameter

Test Conditions

to

Output Oelay 1

tHO

Output Hold Time

Note:

VOO=Min, CLOAO=25pF
VOO = Max, CLOAO = 25pF

Min

Max
35

5

Units
ns
ns

1. Equivalent to tOIS and tENA of the three-state outputs.

Ordering Information
Product
Number

Temperature Range

Screening

Package

Package
Marking

TMC3211H5C

STO- TA = O°C to 70°C

Commercial

120 Pin Plastic Pin Grid Array

3211 H5C

40005579 Rev 0 8193

For Mora Information call 1-800-722-7074.

Raytheon Semiconductor

3-427

I

TMC3211

3-428

Raytheon Semiconductor

For More Information call 1-800-722-7074.

Section 3 - Standard Products

~e~ory/Storage
8
01 7-0,"-'"_ _ _ _-.1'1

8

La-OL.--+---l

Signal processing puts extraordinary demands on
memory and storage elements. The highly pipelined
architectures require a variety of short, wide, variable
delays to compensate unequal data paths. At times, long
delays are needed.

Product
TMC2011-1
TMC2111-1

CloCk
Rate1
Description
Size
(MHz)
Programmable Digilal Delay 3-18x8 bil
40
30
Programmable Digilal Delay 1-16x8 bit 40
30

Raytheon provides solutions to all of those problems with
special-purpose memory and storage elements. The
TDC1005 and TDC1 006 shift registers are basic long,
fast serial storage elements. For delay equalization
problems, the TMC2011/2111 provides an easy solution,
with a byte-wide architecture and fully programmable
lengths up to 18 words.

Power1
(Walls)
0.1
0.1
0.1
0.1

Package
B2.R3
B2,C3
B2,R3
B2,C3

Grade

C

Notes
Also 21-36x4 split mode.

C. V,SMD

C
C, V,SMD

Notes
1. Guaranteed. See product specifications for test conditions.
2. A =High Reliability, Tc - -55"C to 125"C.
C - Commercial, TA - O"C to 70"C.
V" MIL-5TO-883 compliant, Tc - -55"C to 125"C.
SMD =Available per Standardized Military Drawing, Tc =-55"C to 125"C.

For More Information caiI1-800-722-7074.

Raytheon Semiconductor

3-429

I

Section 3 -

3-430

Standard Products

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC201VTMC2111
TMC201VTMC2111
CMOS, Variable-Length Shift Register
8-Bit, 40 MHz

Description

Features

The TMC2011 and TMC2111 are high-speed, byte-wide
shift registers with programmable delay lengths.

•
•

The TMC2011 can be programmed to any length
between 3 and 18 stages. If offers a special split-word
mode which allows for mixed delay lengths. The
TMC2011, constructed in low-power CMOS, is pin and
function compatible with the bipolar TDC1 011.
The TMC2111 is a byte-wide shift register that can be
programmed to lengths of 1 to 16 stages.
The TMC2011 and TMC2111 are fully synchronous,
with all operations controlled by a single master clock.
Input and oulput registers are positive-edge triggered Dtype flip-flops. The length and mode controls are also
registered. Both devices operate with a maximum clock
rate of 40 MHz.
Built with Raytheon Semiconductor's OMICRON-CTM
one micron CMOS process, the TMC2011 and
TMC2111 are ffi-compatible, low-power replacements
for the popular TDC1 011, used in applications ranging
from video to bit-slice processors.

•
•
•
•
•
•

Low power CMOS
Pin compatible replacement for the TDC1011
(TMC2011)
Inputs and oulputs are TTL-compatible
DC - 40 MHz clock rate
Selectable delay lengths (TMC2011 : 3 to 18 stages,
TMC2111: 1 to 16 stages)
Special 4-bit wide mixed-delay mode (TMC2011)
Available in 24-pin CERDIP and 28-contact plastic
or ceramic chip carrier
Commercial and MIL-STD-883C grades

Applications
•
•
•
•
•
•

Video filtering
High speed data acquisition
Local storage registers
Digital delay lines
Television special effects
Pipeline register

I

Simplified Block Diagrams
TMC2011

TMC2111

OUTPUT 003 _0

"=-=t=-:=::

OUTPUT 007 _0

LENGTH
SELECTOR La _...

LENGTH
SELECTOR L3 _0

2111.S60

OUTPUT 007 _4
MODE
2011.S60

For More Information call 1-800-722-7074.

Raytheon Semiconductor

3-431

TMC2011/TMC2111
TMC2011 Functional Block Diagram

MC>-----

ClK

TMC2011 Pin Assignments
010 1

24 000

01 1 2
01 2 3

23 001

013 4

21 003

lO 5

20 l2

l1 6

19 l3

22 002

VOO 7
ClK 8

18 GNO

014 9

16 004

015 10

15 005

016 11

14 006

017 12

13 007

17 MC

2011.B2,24

003
002
001
000
01 0
011
012

26
27
28
1

4

TMC2011
(TOP VIEW)

18
17
16
lS
14

004
DOs
006
007
017
13 016
12 Dis

2011,C3,R3,28

28 Contact Chip Carrier - C3 Package
28 Lead Plastic J-Leaded Chip Carrier - R3 Package

24 Pin CERDIP - 82 Package

3-432

Raytheon Semiconductor

For More iniormation cali 1-800-722-7074.

TMC2011/TMC2111
TMC2111 Functional Block Diagram

elK >>-----~ TO All STAGES

2111.FBD

TMC2111 Pin Assignments
01 0 1
011 2

24 000

012 3
01 3 4

22 002

lO 5

20 l2

II 6

19 l3

23 001
21 003

VOO 7
ClK 8

18 GNO

014 9

16 004

015 10

15 005

016 11

14 006

017 12

13 007

17 GNO

003
002
001
000
010
011
012

26
27
28
1
2
3
4

18
17
16
15
14
13
12

TMC2111
(TOP VIEW)

s ... s
o

>gd

004
005
006
007
017
016
015

i5~~
2111.C3.R3.28

2111.B2.24

24 Pin CERDIP - B2 Package

For More Information call 1-800-722-7074.

28 Contact Chip Carrier - C3 Package
28 Lead Plastic J-Leaded Chip Carrier - R3 Package

Raytheon Semiconductor

3-433

I

TMC2011/TMC2111
Functional Description

Data Outputs

General Information

000-7

The TMC2011 consists of two 4-bit wide, programmable
length shift registers. The TMC2111 consists of a single
8-bit wide, programmable length shift register. The internal registers of each device share control signals and a
common clock.

The outputs of the shift register are delayed
relative to the input signals. The amount of
the delay is programmable Isee Table 11.
The outputs remain valid for a minimum
of tHO nanoseconds after the leading edge
of ClK. This allows the data to be latched
into circuits with non-zero hold time
requirements.

Signal Definitions
Controls
Power
VOO, GNO

Data Inputs
01 0-7

3-434

ClK

All inputs and outputs are synchronous and
operate from a single master clock. All
operations occur on the rising edge of the
master clock.

lO-3

The length select input is used to determine the register delay of the TMC2011
and TMC2111. This input is registered and
affects the output too after the clock edge
after it is input to the device Isee Timing
Diagram I. Delay lengths are specified in
Table 1.

MC

The Mode Control ITMC2011 Onlyl is used
to select the special 4-bit wide split mode
on the TMC2011. When HIGH the delay on
007-4 is fixed at 18 stages, while 003-0
have the delay specified by the length
select. When MC is lOW. all eight bits
have equal delays as specified by the
length select.

The TMC2011 and TMC2111 operate from
a single + 5V supply. All power and ground
lines must be connected.

Eight inputs are provided for the data,
which pass through the shift register
unchanged. The eight inputs on the
TMC2011 are divided into two groups of
four bits to allow mixed delay operation.
The lengths of these two groups are
different when the Mode Control IMCI is
HIGH Isee Table 11. When MC is lOW
both groups have equal delays. The
TMC2111 consists of a single group of
eight bits with all data bits having equal
delays

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TMC2011/TMC2111
Figure 1. Timing Diagram (Preset Length Controls)

\,------,1

Note:

1.

2011/2111.1

Lis 007-4 Length from Table f.

Figure 2. Length Control Operation

TMC2011
00 7 _0

X

-

DATA
5

x

DATA
6

x

DATA
7

x

DATA
8

x

DATA
8

x

TMC2111

DATA
9
DATA
11

007 _0

2011/2111.2

Figure 3. Equivalent Input Circuit

I

Figure 4. Equivalent Output Circuit

SUBSTRATE

~~~~ROL 0--_ _+-_--;

GND

For More Information call 1-800-722-7074.

2011/2111.3

Raytheon Semiconductor

GND

2011/2111.4

3-435

TMC2011/TMC2111
Figure 1. Timing Diagram (Preset Length Controlsl

\~---,I

'tlIXllI.

I

~3C~~

ts

~~Tt -1

'tlIXllI.

ItH~

0 -LX-l,I_C_O_NT_R...,Ol_S---LIX-l-_ _ _ _ _ _ _ _ _ •••

X

X

J

DATA N + l 1

...

'tlIXllI.
to

.

DATA
N+l+1

~

tHO~

IXI

~ATA

xxxxxx

~~T~

X

007-0 ____L-~____________~~____~__~--~,~~,----~~----~~----Note:

1_

Lis 007 _4 Length from Tebl. 1.

2011/2111.1

Figure 2. Length Control Operation
ClK

MC,
l3_ 0

TMC2011
0°7_0

xxxxx
X

0010

DATA

5

XXXXX

X

0010

DATA
6

XXXXX
X

0011

DATA
7

XXXXX

X

0011

DATA

8

XXXXX

X

0011

DATA

8

XXXXX
X

DATA
9

TMC2111

DATA
11

0°7_0

2011/2111.2

Figure 3, Equivalent Input Circuit

Figure 4. Equivalent Output Circuit

SUBSTRATE

CONTROL

INPUT

o---t---+

GND

3-436

2011/2111.3

Raytheon Semiconductor

GND

2011/2111.4

For More Information call 1-800-722-7074.

TMC2011/TMC2111
Absolute maximum ratings (beyond which the device may be damaged) 1
Supply Voltage ........................................................................................................................................................................................ - 0.5 to + 7.0V
Input Voltage ................................................................................................................................................................................. - 0.5 to (VOO + 0.5)V
Output
Applied voltage 2 ................................................................................................................................................... - 0.5 to (VOO + 0.5)V
Forced current 3.4 ........................................................................................................................................................ - 3.0 to + 6.0mA
Short-circuit duration Isingle output in HIGH state to ground) ......................................................................................... 1 Second

Temperature
Operating. case .............................................................................................................................................................. - 60 to + 130°C
case Iplastic package (R3) only) ................................................................................................................ - 20 to + 90°C
junction ........................................................................................................................................................................... 175°C
Lead. soldering (10 seconds) ......................................................................................................................................................... 300°C
Storage ............................................................................................................................................................................ - 65 to + 150°C
Notes:

1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range. and measured with respect to GNO.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.

Operating conditions
Temperature Range
Min

Standard
Nom

VOO

Supply Voltage

4.75

5.0

tpWL
tpWH

Clock Pulse Width. LOW
Clock Pulse Width. HIGH

12
12

12
12

ns
ns

ts

10
8
10
8
1.0

10

tH

Input Setup Time
TMC2011
TMC2011-1
TMC2111
TMC2111-1
Input Hold Time

ns
ns
ns
ns
ns

V,L
V,H

Input Voltage. Logic LOW
Input Voltage. Logic HIGH

Parameter

01 7-0, L3-0' MC
CLK
IOL
IOH

Output Current. Logic LOW
Output Current. Logic HIGH

TA
TC

Ambient Temperature. Still Air
Case Temperature

For More Information call 1-800-722-7074.

Max
5.25

Min
4.5

5.0

Max
5.5

12
3.0
0.8

2.0
2.4

0.8
2.0
2.4

4.0
-2.0
0

Extended
Nom

Raytheon Semiconductor

V
V
V

4.0
-2.0

mA
mA

125

°c
°c

70
-55

Units
V

3-437

TMC2011/TMC2111
DC characteristics within specified operating conditions 1
Temperature Range
Parameter

Test Conditions

Standard
Min
Max

Supply Current, Quiescent
Supply Current, Unloaded
TMC2011
TMC2111

VOO ~ Max, VIN ~ OV

IlL
IIH

Input Current, Logic LOW
Input Current, Logic HIGH

VDD~Max, VIN~OV

VOL

VOD'~

VOH

Output Voltage, Logic LOW
Output Voltage, Logic HIGH

Min, 10L ~ Max
VDD ~ Min, 10H ~ Max

lOS

Short-Circuit Output Current

VDD ~ Max, Output HIGH, one pin to
ground, one second duration max.

CI

Input Capacitance
Output Capacitance

TA~25°C, f~lMHz

Co
Note:

1. Actual test conditions may vary from those shown, but guarantee operation as specified.

IOOQ
IOOU

Extended
Min
Max

5

Units

5

mA

40

40

40

40

mA
mA

VDD~Max, f~20MHz

-10

VDD~Max, VIN~VDD

-10
+ 10
0.4

2.4

TA~25°C, f~lMHz

p.A
+10
0.5

2.4

p.A
V
V

-50

-50

10
10

10
10

mA

pF
pF

Switching characteristics within specified operating conditions 1
Temperature Range
Parameter
fCLK

tD

Test Conditions

Maximum Clock Rate
TMC2011, TMC2111
TMC2011-1, TMC2111-1

VDD~

Output Oelay
TMC2011, TMC2111

VDD ~ Min, CLOAD ~ 40pF

Standard
Min
Max
30
40

30

20
17
VOO~Max, CLOAD~40pF

tHO

Output Hold Time

Note:

1. All transitions are measured at a 1.5V level.

Units

Min

TMC2011-1, TMC2111-1

3-438

Extended
Min
Max

Raytheon Semiconductor

5

MHz
MHz

25

5

ns
ns
ns

For More Information call 1-800·722·7074.

TMC2011/TMC2111
Standard Military Drawing
These devices are also available as products manufactured, tested, and screened in compliance with
Standard Military Drawings ISMDs\. The nearest vendor
equivalent product is shown below; however, the
applicable SMD is the sole controlling document defining
the SMD product.

Standard Military

Nearest Equivalent

Drawing

Raytheon Prod. No. Package

5962~944601 LA

TMC2011B2V
TMC2011C3J
TMC2111B2V
TMC2111C3J

5962~6013A

5962-8944602LA
5962~9446023A

24 Pin CERDIP
24 Contact Chip Carrier
24 Pin CERDIP
24 Contact Chip Carrier

Ordering Information
Product
Number

Temperature Range

TMC2011B2C
TMC2011 B2Cl
TMC2011B2V

STD-TA _O°C to 70°C
STD-TA _O°C to 70°C

TMC2011C3V

Screening

Package

Package
Marking

EXT - TC- - 55°C to 125°C

Commercial
Commercial
MIL-STD-883

24 Pin 0.3" CERDIP
24 Pin 0.3" CERDIP
24 Pin 0.3" CERDIP

2011B2C
2011B2Cl
2011B2V

EXT-TC- -55°C to 125°C

MIL-STD-883

28 Contact Hermetic Chip Carrier

2011C3V

TMC2011R3C
TMC2011 R3Cl

STD-TA-O°C to 70°C
STD-TA-O°C to 70°C

Commercial
Commercial

28 Lead Plastic J-Leaded Chip Carrier
28 Lead Plastic J-Leaded Chip Carrier

2011R3C
2011R3Cl

TMC2111B2C
TMC2111B2V

STD-TA _O°C to 70°C
EXT - TC- - 55°C to 125°C

Commercial
MIL-STD-883

24 Pin 0.3" CERDIP
24 Pin 0.3" CERDIP

2111B2C
2111B2V

TMC2111C3V

EXT - TC- -55°C to 125°C

MIL-STD-883

28 Contact Hermetic Chip Carrier

2111C3V

TMC2111R3C
TMC2111R3Cl

STD-TA _O°C to 70°C
STD-TA-O°C to 70°C

Commercial
Commercial

28 Lead Plastic J-Leaded Chip Carrier
28 Lead Plastic J-Leaded Chip Carrier

2011R3C
2011R3Cl

40006086 Rev 0 eI93

For More Information caJI1-800·722·7074.

Raytheon Semiconductor

3-439

TMC2011/TMC2111

3-440

Raytheon Semiconductor

For Mora Information call 1-800-722-7074.

Linear
Standard Linear Products
I Operational Amplifiers I
I

I

I

Low Power

General Purpose

High Gain

High Performance

• LMl481348

• RM741
• RC747

• RC4558
• RC4559
• RC4560

•
•
•
•

I
Precision
•
•
•
•
•
•

RC4207
RC4227
LH210SlA
RC4277
LM10SlA
LT1001/A

.OP-07
.OP-27
.OP-37
.OP-77

Comparators
LH2111
LM111
LMl39/A
LM339
RM4805lA

.RC3403A
•
•
•
•
•

RC4136
RC4741
LH2101A
LM101A
LM1241324

VoHage References

Voltage Regulators

REF01 +1 OV Voltage Reference
REF02 +5V Voltage Reference

Ground Fault Interrupters
RC4152
RC4153

RC4156
RC4157
RC55321A
RC55341A

RC4190 Mlcropower Switching Regulator
RC4191 1213 Mlcropower Switching Regulator
RC4391 Inverting Switch Mode Regulator
RC4194 Dual Tracking Regulator
RC4195 Fixed Dual Tracking Regulator

Specialty Functions
RC4200/A Multiplier
RC4444 Balanced Cross Point Array
RM2207 Voltage Controlled Oscillator
RC2211 FSK Demodulator Tone Decoder

LM1851
RV4140
RV4141
RV4145

65-8152

At Raytheon Semiconductor we're committed to analog
technology. Our growing line of standard linear products
have provided circuit solutions for thousands of
designers over the years. These products are based on
our investment in people and technology, total quality
control, just-in-time manufacturing, along with three
decades of providing analog solutions to many design
problems.
A variety of low noise precision operational amplifiers,
instrumentation amps, comparators, D!A multiplier!
dividers, preCision voltage references, voltage-tofrequency converters, low power switching regulators
and voltage regulators and specialty circuits comprise
this product line.
The products are fabricated on a bipolar-based junction
isolated process. The process provides precision, low
noise, low offset input stages, current sources and
For More Information, call 1-800-722-7074.

moderate power stages when needed.
Precision instrumentation grade op amps are achieved
with the addition of temperature stable silicon chromium
thin film resistors, Zener zap trimming, low noise epitaxial
growth process, and our patented Vas digital offset
nulling technique. This technique provides commercial
grade products with ±1 0 ~V offset, with a worst-case
voltage drift of 0.1 ~VloC.
Screening Options Available:
• JANClassB
• Standard Military Drawings (SMD)
• MIL-STD-883, Class B
• Source Control Drawing (SCD)
• Environmental Stress Screening
• Military Temperature Range
• Industrial Temperature Range
• Commercial Temperature Range

Raytheon Semiconductor

3-441

I
"

Linear
Precision Operational Amplifiers
Type
RC4207F
RC4207G
RC4227F
RC4227G
RM4227B
RC4277F
RV4277F
LH210SA
LH210S
lMl0SA
LM108
OP-07A
OP-07
OP-07E
OP'()7C
OP'()7D
OP-27A
OP-27B
OP-27C
OP-27E
OP-27F
OP-27G
OP-37A
OP-37B
OP-37C
OP-37E
OP-37F
OP-37G
OP-77A
OP-77B
OP-77E
OP-77F
Op-nG

3-442

Descripllon
Dual low Noise
Dual low Noise

Dual low Noise

low Vas

Ultra Low Noi se

Decompensated
(AC stable with
AVCL?!S)
Ultra Low Noise

LowVos

Vos
(lLV)
75
150
75
150
75
75
75
500
2000
500
2000
25
75
75
150
150
25
60
100
25
60
100
25
60
100
25
60
100
25
60
25
60
100

Electrical Characteristics (minimax except')
TCVos
CMRR
los
I.
(dB)
(lLVJ"C)
(nA)
(nA)
1.3
0.7*
1.3
0.4'
1.3
1.0
1.0
5.0
15
5.0
15
0.6
1.3
1.3
1.S
2.5
0.6
1.3
1.8
0.6
1.3
I.S
0.6
1.3
1.8
0.6
1.3
1.8

5
10
10
15
10
5.0
5.0
0.2
0.2
0.2
0.2
2.0
2.8
3.8
6.0
6.0
35
50
75
35
50
75
35
50
75
35
50
75

0.3
0.6
0.3
0.6
1.2

1.5
2.S
1.5
2.S
2.S

±S
±10
±15
±25
±15
±S.O
±S.O
±2.0
±2.0
±2.0
±2.0
±2.0
:1:;3.0
±4.0
±7.0
±12.0
±40
±S5
:!BO
±40
±S5
:!BO
±40
±S5
:!BO
±40
±55
:!BO
±2.0
±2.8
±2.0
±2.S
±2.8

Raytheon Semiconductor

100
94
104
100
104
110
110
96
S5
96
85
110
110
106
100
94
114
106
100
114
106
100
114
106
100
114
106
100
120
116
120
116
116

Gain
(VIII-V)
0.4
0.25
0.5
0.4
0.5
2.0
2.0
.04
.025
.04
.025
0.3
0.2
0.2
0.12
0.12
1.0
1.0
0.7
1.0
1.0
0.7
1.0
1.0
0.7
1.0
1.0
0.7
5.0
2.0
5.0
2.0
2.0

I••
(mA)

6.67
S.O
6.67
S.O
6.67
5.5
5.5
0.4
0.4
0.4
0.4
4.0
4.0
4.0
5.0
5.0
4.67
4.67
5.67
4.67
4.67
5.67
4.67
4.67
5.67
4.67
4.67
5.67
2.0
2.0
2.0
2.0
2.0

For Morelnlormation. calil-B00-722-7074.

Linear
Slew
(V/J.1S)

GBW(MHz)

1 kHz
Nols,"
(nV/..JHz)

0.3
0.3
2.7
2.7
2.7
0.3
0.3
.05
.05
.05
.05

1.5
1.5
8.0
8.0
8.0
1.5
1.5
1.0
1.0
1.0
1.0

10.3"
10.3"
3.8"
3.8"
3.8"
10.3*
10.3"
30
30
30
30

0.3
0.3
0.3
0.3
0.3
2.8
2.8
2.8
2.8
2.8
2.8
17
17
17
17
17
17
0.3
0.3
0.3
0.3
0.3
""10 Hz

0.5
0.5
0.5
0.5
0.5
8.0
8.0
8.0
8.0
8.0
8.0
63
63
63
63
63
63
0.6
0.6
0.6
0.5
0.6

18
18
18
20
20
5.5
5.5
8.0
5.5
5.5
8.0
5.5
5.5
8.0
5.5
5.5
8.0
18
18
18
20
20

M
SOIC

D
CDIP

X
X
X

Packages
T
N
PDIP T0-99

L
LCC

Temperature Range
0"C to
-55"C to
·2S"C to
+12S"C
+85"C
+70"C
X
X
X
X

X
X
X
X
X
X

X
X

X
X

X
X

X
X

X
X
X
X

X
X
X
X

X
X

X
X
X
X
X

X
X
X
X
X
X

X
X
X

X
X
X

X
X
X

X
X
X

X
X
X

X
X
X

X
X
X

X
X
X
X
X

X
X
X
X
X
X

X
X
X
X
X
X

X
X
X

X
X
X

X
X
X
X
X

X
X
X

MIL-8TD
883/B
Availability

X
X
X
X
X
X

X
X
X
X
X

X
X

X
X
X
X
X

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-443

Linear
Precision Operational Amplifiers
Input Offset Voltage Selection Table by Package Type (+25OC limits, in microvolts)
Part
Type
RC4207*
RC4227*
RC4277*
OP-07
OP·27
OP·37
OP·77
lMl08/A
lH2108/A"
"Dual

Plastic
DIP (N)
±75
±75
±30
±75
±25
±25
±25

SOIC(M)

±75
·±25
±25
:1£0

Leadless
Chip
Carrier (l)

Ceramic
DIP (D)
±75
±75
±30
±25
±25
±25
±25

Metal
Can
TO·99 (T)

±25
±25
±25
±25
±25

±Soo
±SOO

±SOO
±SOO

±Soo
±SOO

Audio and General Purpose Operational Amplifiers
Single Operational Amplifiers

Type
lMl01A

Description
General Purpose with 1m·
proved Input Characteristics
General Purpose, Internal Comp
High Performance, low Noise

Maximum Input
Specifications @25"C
Offset
Offset
Bias
VOI~e Currant Current
(m
(nA)
(nA)
2.0
10
75

Typ.'
Unity
Gain
BW
(MHz)
1.0

Typ.
Slaw
Rate
(V/!!S)
0.5

Available Packages
Temp·
Range
M

D
X

L

M

N

T
X

X
RM741
0.5
M
X
5.0
200
500
1.0
RC5534
X
4.0
300
1500
10
13
C
X
RM5534
M
X
2.0
200
800
10
13
RC5534A3
4.0
300
1500
10
13
X
C
RM5534A3
X
X
M
13
2.0
200
800
10
Notes:
1. Gain bandwidth product for 55341Aseries and closed loop bandwidth for OP series. 2. Operating Temperature Range: M =·55"C to +125"C; C=O"C to
+70"C. 3. RMlRC5534A guarantees maximum illlut noise specification.

Dual Operational Amplifiers
Maximum Input
Specifications @25"C
Offset
Offset
Bias
VOlt~e Current Current
(m
(nA)
(nA)
2
10
75
5
200
500
6
500
200
5
200
500
6
100
250
5
100
250
7
300
800
4
150
800
2
100
400
4
150
800
100
400
2

Typ.'
Unity
Gain
BW
(MHz)

Typ.
Slew
Rate
(v/!!s)
0.5
0.5
1
1
2 (1,5)
2 (1,5)
4
8
8
8
8

Available Packages
Temp·
Range

Type
Description
0
L
M N T
lH2101A High Performance
X
RM747
Dual 741
X
M
X
RC4558
Wideband 741
3
X X
C
RM4558
3
M
X
X
RC4559
High Performance
4 (3)
C
X
X X
RM4559
4 (3)
M
X
X
RC4560
Wide Bandwidth
10
C
X X
RC5532
High Performance,
10
C
X
X
RM5532
Low Noise
X
10
M
X
RC5532A3
X
10
C
X
RM5532A3
10
M
X
X
Notes:
1. Gain bandwidth product for 5532A series. 2. Operating Temperature Range: M=-55"C to +125"C; C =O"C to +70"C. 3. RMlRC5532A guarantees maximum
illlut noise specification. () Denotes guaranteed specifications.

3-444

Raytheon Semiconductor

For More Information. cali 1-800·722·7074.

Linear
Quad Operational Amplifiers
Maxlmumln~

Type

DescrIption

RM4741
RC4741
LM124
LM148
lM324
RC3403A
RC4136
RM4136
RC4156

741 General Purpose
Single Supply
LaN Pa.ver 741
Single Supply
Ground Sensing
741 General Purpose
High Performance

RM4156
RC4157
RM4157

High Speed, Decompensated

Speclflcallona
Offset
Offset
Voltage CUrrent
(mY)
(nA)
3
5
5
5
7
6
6
4
5

5'C
Blaa
Current
(nA)

30

200
300

50

30

150
50

150
100
250
500
500
400
300

3

30

200

5
3

50

30

300
200

25
50
50

200

TKftt
UntY
Gain

BW
(MHz)
3.5
3.5
1
1
1
1
3
3
3.5
(2.8)
3.5
(2.8)
19 (15)
19(15)

Typ.
Slaw
Rate
(V1¢3)
1.6
1.6
0.5
1.2
1
1.5
1.6
(1.3)
1.6
(1.3)
8(6.5)
8 (6.5)

Available Packages
Tampt
Range

D

M

X

L

II

X
X
X X
X
X X

C
C
C
M

T

X

C
M
M

N

X

C

X X
M

X
X X

C
M

X

Nates:
1. Opelllling Temperatura Range: M. -$'C to +125'C; C. O'C 10 +7O"C.
Denotes guaIII1Ieed specIIIc:atlon.

(I

Comparators
lIaxlmumln~

Type

DescrIption

LH2111
LMll1
LM139
LM139A
LM339
RM4805
RM4805A

Dual Precision Voltage
Low Input Current
Quad Single Supply
Quad Single Supply
Quad Single Supply
Precision High Speed

SpeclDcaUons
Offeat
BIas
Voltage Current
(nA)
(mV)
3.0
3.0
5.0
~.O

5.0
0.6
0.25

100
100
100
100
250
1800
1200

Voltage
5'C
Offeet Gain
lIu
CUrrent (VImV
Sat.
lyp) Voltage
(nA)
10
10
25
25
50
150
80

200
200
200

200
200
20
20

& 12V
& 12V
0.40
0.40
0.40
0.40
0.40

Output
Leakage
CUrrent
(nA typ)
0.2
0.2
0.1
0.1
0.1

Available Packages

D

L

II

N

X
X
X
X

T

X
X X

X
X

I

Package Codes:
D • Ceramic DIP

L • Leadless Chip CarrIer

For More Infarmation, can 1-800·722·7074.

M • Plastic SOIC

N • Plastic DIP

Raytheon Semiconductor

T. Metal can (T0-99)

3-445

Linear
Voltage References

Device
REF-01
REF-01C
REF-01D
REF-02
REF-02C
REF-02D

Nominal
Voltage
Out
10.00
10.00
10.00
5.00
5.00
5.00

Typical
Tempco
(ppmFC)
10.0
20.0
70.00
10.00
20.00
70.00

Temp.
Range
Mil
Comm
Comm'
Mil
Comm
Comm

Typical
t:N
overremp.
(%)
.18
.14
.49
.18
.14
.49

Typical
line Reg.
(%Nolt)

.006
.009
.012
.006
.009
.012

Typical
Load Reg.
(%/mA)
.006
.006
.009
.006
.006
.009

Typical
Load
Current
(mA)
15
15
15
15
15
15

Input
Voltage
Range
(Voltage)
12 to 40
12 to 40
12 to 40
7t040
7t040
7to 40

Voltage Regulators
Product
RC4190
RC4191/213
RC4194
RC4195
RC4391

Regulator
Type
Low Power Switcher
Low Power Switcher
Adj. Dual Tracker
Fixed Dual Tracker
Inverting Switcher

Operating
Range
1.3 to 30V
2.2 to 30V
±45V
±30V
4t030V

Typ. Regulation
Efficiency
line
Load
85%
.04% Vo
0.2% Vo
85%
.04% Vo
0.2% Vo
nla
0.04% Vout
0.002%vout
2.0mV
5.0mV
nla
70% 1.0 to 1.5% Vo .07 to 0.2% Vo

Typ. Supply
Current
235 J.IA
225J.IA
+0.8 and -1.8 mA
±1.5mA
300 J.IA

VOltage-to-Frequency Converters
Product
RC4152
RC4153

3-446

Description
VFCor FVC
VFC

High
Accuracy
0.05% Max
0.01% Max

Bandwidth
DC to 100 kHz
DC to 250 kHz

Raytheon Semiconductor

Tempco
50 ppmf'C

For More Information, call 1-800·722·7074.

Linear
Ground Fault Circuit Interrupters (GFCI)
Raytheon Semiconductor has been involved with GFCVALCI markets since 1973. Keeping pace with mandated UL
regulations surrounding GFCVALCI type safety devices in homes has created a very high demand for low cost, easy to
assemble, reliable ICs. Raytheon Semiconductor has met this challenge by providing the following standard GFCVALCI
products.

Features
GFCI Applications
ALCI Application
IQUIESCENT
Ext. parts for GFCI
Ext. parts for ALCI
110V1220V Operation
Built-in Rectifier
Packaging
8-S01C
8-DIP
Dice

LM1851
Yes
No
2.5mA
20
18
No
No

RV4140
No
Yes
375 JlA
n/a
10
Yes
Yes

RV4141
Yes
Yes
500 JlA
13
10
Yes
Yes

Yes
Yes
Yes

Yes
Yes
Yes

Yes
Yes
Yes

RC4447 Quad PIN Diode Switch Driver
•
•
•
•

Drives PIN Diodes or MOSFETs
50 ns response time (lOW to high)
10 MHz pulse rate
Quad Driver, die or packaged units

RC2211 FSK Demodulatorrrone
Decoder
•
•
•

Excellent tempco - 20 ppml"C
Wide frequency range - 0.Q1 Hz to 300 KHz
FSK demodulation with carrier-detector

RM2207 Voltage Controlled Oscillator
•
•
•
•

RV4145
Yes
Yes
450JlA
21
12
Yes
No

Yes
Yes
Yes

RC4444 4 X 4 X 2 Balanced Switching
Crosspoint Array
•
•
•
•
•
•

Low bidirectional RON
High Am:
Low capacitance
High rate firing
Predictable holding current
Superior gate matching

RC42001A Multiplier
•
•
•
•
•

Non-linearity - 0.1 % max.
Tempco - 0.005%
Wide bandwidth - 4 MHz
Signal-ta-noise ratio - 94 dB
Multiply, divide square, square roo~ RMS-to-DC
conversion, AGC, modulate/demodulate

20 ppm/"C tempco
Adjustable duty cycle - 0.1 % to 99.9%
Wide frequency range - 0.Q1 Hz to 1 MHz
Two or four FSK capability

For More Information, call HI00·722·7074.

Raytheon Semiconductor

3-447

I

Linear

3-448

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

LMIOIAILH2101A
LMIOIAILH2101A
General Purpose Operational Amplifier
Features

Description
The LM1 01MH21 01A Is a general purpose high
performance operational amplifier fabricated
monolithically on a silicon chip by an advanced
epitaxial process. The LH21 01 A consists of two
LM1 01 A ICs in one 16-1ead DIP. The units may be
fully compensated with the addition of a 30 pF
capacitor stabilizing the circuit for all feedback
configurations including capacitive loads.

•
•
•
•
•

Input offset voltage 0.7 mV
Input bias current 30 nA
Input offset current 1.5 nA
Full frequency compensation 30pF
Supply voltage ±5.0V to f!2.0V

The device may be operated as a comparator with a
differential input as high as 30V. Used as a
comparator the output can be clamped at any desired
level to make it compatible with logic circuits.
The LM101A and LH2101A operate over the full
military temperature range from -55"C to +125"C.

For Mora Inlonnation, call 1-800-722-7074.

Raytheon Semiconductor

3449

LMIOIAILH2101A
Connection Information

Ordering Information
Part Number

B-Lead

TO-99 Metal Can
(Top View)

Pin
1

2
3
4

5
6

7
8

Package

B-Lead

Dual In-Una Package
(Top View)

Function
ComplVos Trim
-Input
+Input
-VS
Vos Trim
Output
+Vs
Comp

-

LM101AD
LM101AD/883B
LM101AT
LM101ATm83B
LH2101AD
LH2101AD1883B

0
0
T
T

0
0

Operating
Temperature
Range

-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C

NolIIS:
18838 suffix denolllS Mil-std-883. Level 8 processing
D = 8-lead ceramic DIP (LM10l types)
D 16-1ead ceramic DIP (LH2101 types)
T • 8-1ead metal can (TO-99)
Contact a Raytheon sales office or representative for
ordering in!onnaticn on special peckagellemperature
range combinations.

=

Absolute Maximum Ratings

16-Lead Dual In-Line Package

Supply Voltage ...........................................±2.2V
Differential Input Voltage .............................. 30V
Input Voltage' ........................._................................_.±15V
Output Short-Circuit Duration2 .................. Indefinite
Storage Temperature
Range ................................. -65°C to +150°C
Operating Temperature Range
LM101A, LH2101A ............. -55°C to +125°C
Lead Soldering Temperature
(60 sec) ............................................ +300°C

(Top View)

Notes:
1. For supply voltages less than ±15V.the absolute maximum
input voltage is equal to the supply voltage.
2. Observe package !hennal charecteristics.

Pin
Pin
Function
Function
9 +Vs(8)
1 +Vs (A)
10 Comp (8)
2 Comp (A)
3 ComplVosTrim (A) 11 CompNos Trim (8)
12 -Input (8)
4 -Input (A)
13 +Input (8)
5 +lnput(A)
14 Vos Trim (A)
6 -Vs
15 NO
7 Vos Trim (8)
16 Output(A)
8 Output (8)

3-450

Raytheon Semiconductor

For Mora Information, call 1-800-722·7074.

LMIOIAILH2101A
Thermal Characteristics
16-Lead
Ceramic

DIP

8-Lead
To-99
Metal can

Max. Junction Temp.

+175°C

+175°C

+175°C

Max. Po TA <50°C

833mW

658mW

1042mW

Therm.Res9JC

45°C/W

50°C/W

60°C/W

Therm. Res. 9JA

150°CrN

190°CrN

120°CrN

8.33mWf'C

5.26mWf'C

8.33mWf'C

8-Lead
Ceramic

For TA >50°C Derate at

DIP

I
For More Infonnation, calI1-8O().722·7074.

Raytheon Semiconductor

3-451

LMIOIAILH2101A
Electrical Characteristics

(C • 30 pF; fFJ.ov !NS S:l2OV; -55'C S TA S +125'C unless otherwise specified)
Parameters

Test Conditions

LM1 01 AlLH21 01 A
Typ Max
Min

Units

2.0

mV

Input Offset Voltage

TA = +25°C, Rs S 50 kn

0.7

Input Offset Current

1.5

10

nA

Input Bias Current

TA = +25°C
TA = +25°C

30

75

nA

Input Resistance

TA = +25°C

1.5

Supply Current

TA = +25°C Vs = ±20V

Large Signal Voltage Gain

TA = +25°C, Vs = ±15V
VOUT =±10V, RL~2 kn
RsS50kn

Input Offset Voltage
Average Input Offset Voltage Drift

4.0
1.8

50

Input Offset Current
Average Input Offset Current Drift

3.0

mV

15

IlVfOC

20

nA

+25°C STAS +125°C

0.01

0.1

-55°C S TAS +25°C

0.02

02

Input Bias Current
Supply Current

1.2

Large Signal Voltage Gain

TA = +125°C, Vs =±20V
Vs =±15V
VOUT = ±10V, RL ~ 2 kn

25

Output Voltage Swing

Vs=±15V

RL =10kn

±12

±14

RL=2kn

±10

±13

mA
V/mV

160

3.0

RSS50kn

Mn
3.0

nArC

100

nA

2.5

rnA
VlmV
V

Input Voltage Range

Vs=±20V

±15

Common Mode Rejection Ratio

RS S50kn
RSS50kn

80

96

dB

80

96

dB

Power Supply Rejection Ratio

3-452

Raytheon Semiconductor

V

For More Infonnation, call1..aoo-722-7074.

LMIOIAILH2101A
Typical Performance Characteristics
Supply Current vs. Supply VoHage
2.5

120

I
T =-SS°C

-------

2.0

C 1.5

.s.
Ji

VoHage Gain vs. Supply VoHage

1.0
0.5

110
T A- t2SOC

iii'
~

.c

T A= +l25"C

o

±5

±10

90

!

±15

100

-- f

t.-5S 0

~

:;;;.-

---

±20

:1:10

15
Vs = :t1SV

TA=~S"C

300
~

TA= -5S"C

100

I

o

±10

is

€

10

I-

5

±15

"'

±20

5

o

500

Vs = ±lSV

....

"-

Is

"

r-- -....

-75 -50

.....

-25

los

o

30

-

+25 +50 +75 +100 +125

I
I

M~taIdan

..... "
.........
DIP
......

o

I-

" ....

100
+25

I

I
I

1""...

200

...........

I
I

~

§. 300
~

r-....

......
i' ...

i" 400

"

I

25

Maximum Power Dissipation vs. Temperature
600

400

100

20

lOUT (mA)

Input Bias, Offset Current vs. Temperature

~

15

10

:l:VsM

200

""

TA - +25°C

TA = +l25°C

!

T A= -55"C

~

±20

Current Limiting
Output VoHage vs. Output Current

400

cc

!

:1:15
:l:Va (V)

Input Bias Current vs. Supply VoHage

300

T = +2SOC

2S "C

T A-

:!:Vs(V)

b

+45

+105

~

!

+125

TA (Oc)

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-453

LMIOIAILH2101A
Typical Performance Characteristics (Continued)
Output Voltage Swing vs. Frequency

Open Loop Gain vs. Frequency
120

-

100

Vs =±15V

" t'--... b-.. l'-..Cl

12~~~~++~~~~~-+~~

~

iii" 60
~

~

40
20

Cl = 30 IF,"""

l

o
-20

vs= ±15V
14 ~=t=itmlt=***I-l.Jl!--J-.jf-.l-Hj T A= +25"C

-

T A= +25"C

80

J

16~~Tm~~Tmm-~~~~~~

_!

.1

1

> 10~~~~++~~~~~-+~~
=3pF

100

lK

10K

8 1-++tt1~-t-t+tttl~l-:H:!+I;!!I--+HitHH

~

6H:+i-ttHItT++tttI~:-HI-ttltttt--++tiHtltl

!'...

~~

lOOK

1M

1\

1\

(5

Cl =3 F

4r+Hffi~~~~~~\~~+ffi~

!

~

10

t;

I"

"

~r I~m~r~·~*~-r~*~-+H*~!

10M

10K

lK

F (Hz)

lOOK

1M

10M

F (Hz)

Follower Large Signal Pulse Response
Output Voltage vs. Time
10
8
6

€

J

4
2

Vs = ±15V _
TA = +25"C

r-\

-~
-4
-6

~

I~put

,
1\

~

~

~-

1/oJtput ~

II

f--

-8

-10

o

10 20 30 40 50 60 70 80
Tima(IlS)

3-454

Raytheon Semiconductor

For More Infonnation, call 1-800-722-7074.

L~101AJL1I2101A
Typical Applications
R1
R2
Input o--IVV\,_----''I/V'\r----,

~6_50'C Derate at

DIP

I
For Mora Information, call 1-800-722-7074.

Raytheon Semiconductor

3-459

LMI08A1LH2108A
Electrical Characteristics

v

(±5V S S S ~V and TA S +25'C unless otherwise noted)
Parameters

Test COnditions

LM1 OSAlLH21 08A LM108ILH2108
Min
Typ
Max
Typ Max Min

Units

Input Offset Voltage

0.3

0.5

0.7

2.0

mV

Input Offset Current

0.05

0.2

0.05

0.2

nA

O.S

2.0

0.8

2.0

Input Bias Current
Input Resistance1
Large Signal Voltage Gain

VS=±15V.
VOUT=±10V.
RL=---0

VOJT

6

R3

Cs

R6
6-.ltNi..-...

(")

:::T

N

<'I

~y=

1"0>'1

i

~

~

=
00

~

3=
IN

l.

~

=
00
>

~:::r
~

R11

90

:l

fC

R12

3

n'
o

&
c

90
-I n (2) 0----.-1::".'

..~

+1" (3) 0 - - - - - - - - + - - - - - - '

Q'
§=
iil

~
3

g.

p

~

-

I
~

OuIpul

+--+--<0 (6)

-V.(4)0f-------.-...-----~-_~--------_l_----__J---....l.-....l.-J---.-l
65-2649

Notes:
1. 01,02,013,014,015,016 are superbeta devices.
2. Pin numbers shown are for a-lead packages.

LMl24/324
LMl24/324

Single-Supply Quad Operational Amplifier
Features

Description
Each of the devices in this series consists of four
independent high-gain operational amplifiers that are
designed for single-supply operation. Operation from
split power supplies is also possible and the low
power supply drain is independent of the magnitude of
the power supply voltage.
Used with a dual supply, the circuit will operate over a
wide range of supply voltages. However, a large
amount of crossover distortion may occur with loads
to ground. An extemal current-sinking resistor to -VS
will reduce crossover distortion. There is no crossover
distortion problem in single-supply operation if the
load is direct-coupled to ground.

•
•
•
•
•
•

Large DC voltage gain - 100 dB
Compatible with all forms of logic
Temperature compensated
Unity Gain Bandwidth - 1 MHz
Large output voltage swing - OV to (+VS
-1.SV)
Input common mode voltage range includes
ground

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-463

LMl24/324
Connection Information

Ordering Information

14-Lead Dual In-Line Package
(Top View)

Package

Operating
Temperature
Range

LM324M
LM324N

M
N

O°C to +70°C
O°C to +70°C

LM124D
LM124D/8838

D

0

-55°C to +125°C
-55°C to +125°C

Part Number

...-----, ...-----,

Notes:
883B suffix denotes Mil-8td-883, level B processing
N =14-1ead plastic DIP
D = 14-lead ceramic DIP
M = 14-lead plastic SOIC

65-0418

Pin
Function
1 Output (A)
2 -Input (A)
3 +Input (A)
4 +VS
5 +Input (8)
6 -Input (8)
7 Output (8)

Pin
Function
8 Output (C)
9 -Input (C)
10 +lnput(C)
11 Ground
12 +Input (0)
13 -Input (0)
14 Output(O)

Absolute Maximum Ratings
Supply Voltage ........•.•..•.............. +32V or ±16V
Differential Input Voltage ............................ 32V
Input Voltage ............................... -O.3V to +32V
Output Short Circuit to Ground(l)
(One Amplifier) + Vs S 15V and
TA = +25°C ................................ Continuous
Input Current (V IN < -O.3V)(2) ................................ 50 mA
Operating Temperature Range
LM124 ............................... -55°C to +125°C
LM324 .................................... O°C to +70°C
See Notes on next page.

Thermal Characteristics
14-Lead

14-Lead

Small Outline

14-Lead
Plastic

Ceramic

Max. Junction Temp.

+125°C

DIP
+125°C

DIP
+175°C

Max. Po TA <50°C
Therm. Res 9JC

300mW

468mW

1042 mW

Therm. Res. 9JA
For TA >50°C Derate at

3-464

-

-

60°CIW

200°CIW
5.0mWfOC

160°CIW
6.25 mWfOC

120°CIW
8.38 mW/oC

Raytheon Semiconductor

For More Infonnalion, caJI1-800·722·7074.

LMl24/324
Electrical Characteristics
(+v s = +5.0V(3) and TA= +25°C, unless otherwise noted)
LM324

LM124
Parameters

Test Conditions

Min

Input Offset Voltage 3
Input Bias Current 4
Input Offset Current

Typ

Max

±2.0

45
±3.0

Input Voltage Range S

+Vs -+30V

Supply Current

RL _ .., +VS - 30V

0

(Over Temperature)

RL - .. on allop amps

Large Signal Voltage Gain

+Vs ·15V
(for large VOUT swing)

50

Typ

Max

Units

±5.0

±2.0

±7.0

mV

150

45

250

nA

Min

±5.0

±30
+VS
-1.5

1.5

3.0

0.7

1.2

100

±50

nA

+VS
-1.5

V

1.5

3.0

mA

0.7

1.2

0

25

mA
VlmV

100

RL
.§.

400

~

350

,....

~

-

450

1

-

\

300
0

au
250

o

2

~v.

IV

Input

\.

I

3

4

5

5

6

7

1K

543 -

€

J

2

1
0.001

II
VI

-"~'
'":'

I-

+Vs=
+Vs = +3OV

+V~

lOUT

~UACE

0.1

+

":'

~

Independent of +V.
T A -+25·C

V

111111111 111111 I
0.01

7.

+Vs = +5V

+vs

VOIlT

+

!

1M

Output Voltage VS. Output Sink Current

IIIIII! IIIIII111 I

_ +V.J2 _

2K

100K

10K

10

6

+

F(Hz}

Output Voltage VS. Output Source Current

7

~

+7V

'\

o

8

,

Time (I1S)

8

~'

v..

1\

~

~ ...,

puN

.00

15

V'N_ + 50pFT

-

'001<

TA= +25'C
_+Vs =+3OV_

0.1

II

10

0.01

TA=+25'C

[/

o

0.01

0.1

10

+
-4-

VOIlT

~

!

100

ISiNK (rnA)

100

+ISOURCE (rnA)

Current Limning
OUtput Current VS. Temperature
90
80

I

70

C('

.§.

60
50

8 40

'+

30

- -r-- -

20

I

~

--

I

111_

-

~

-

r-

10

o
-55 -35 -15

For More Information, calI1-80D-722-7074.

+5 +25 +45 +65 +85 +105+125

Raytheon Semiconductor

3-467

LMl24/324
Typical Performance Characteristics (Continued)
Input Voltage vs. Supply Voltage

Input Bias Current vs. Temperature
90
80
70
60

i

50
40
30
20
10

~

~------~--------~------~

5

!

I

-----

o
-ss

15

10

1 I I

3 I-I-I--

I

-

.....

+Vs =+lSV

I

I

+Vs -+SV

I

I

-35 -15

!

I

I I

I

+5 +25 +45+65

+85+105+125

TA ("e)

Open loop Voltage Gain vs. Supply Voltage

Supply Current vs. Supply Voltage
I--

Veil = OV

I

+Vs = +30V 1

±Vs(V)

4

I

160

.~

}?

~ 80

J

TA=O"O to +125"0

I

I

Rl =20kn R l ='2kn' -

r---...

,-1"'""

iii'

I--

40

~

T A= -5S·0

10

I

120

20

o

30

o

5

10

15

20

25

30

35

!

40

+Vs(V)

Open Loop Voltage Gain vs Frequency

Follower Large Pulse Response Signal vs. Time
4

140~--~--~--~~~~mr~--~

120 I----/----/---

€

3

J

J2
o

€

r\
\

/

I

Rl~2kn

I

Vs =+15V'-

I--

<~

~

3

.: 2

r--

o

0

5

10

15

20

25

30

35

!

40

Time (liS)

3-468

Raytheon Semiconductor

For Mare Information, call 1-800-722-7074.

LMl24/324
Schematic Diagram

(4)

Output

L..--...---+-----4:J
+ Input

VOUT

(1,7,8,14)

(3,5,10,12)

Ground

'---.....---~-.....- - - -___--4--.-.--~---+--o(11)
6!Hl417

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-469

LMl24/324

3-470

Raytheon Semiconductor

For More Infonnation. call HIOO·722·7074.

LM148
LM148
Low Power Quad 741 Operational Amplifier
Description

Features

The LM 148 is a true quad 741. It consists of four
independent high-gain, internally compensated, lowpower operational amplifiers which have been
designed to provide functional characteristics identical
to those of the familiar 741 operational amplifier. In
addition, the total supply current for all four amplifiers
is comparable to the supply current of a single 741
type op amp. Other features include input offset
currents and input bias currents which are much less
than those of a standard 741. Also, excellent isolation
between amplifiers has been achieved by
independently biasing each amplifier and using layout
techniques which minimize thermal coupling.

•
•
•
•
•
•
•
•
•
•

741 op amp operating characteristics
Low supply current drain - 0.6 mNamplifier
Class AB output stage - no crossover
distortion
Pin compatible with the LM124
Low input offset voltage - 1.0 mV
Low input offset current - 4.0 nA
Low input bias current - 30 nA
Unity gain bandwidth - 1.0 MHz
Channel Separation - 120 dB
Input and output overload protection

The LM148 can be used anywhere multiple 741 type
amplifiers are being used and in applications where
amplifier matching or high packing density is required.

I
For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-471

LM148
Connection Information

Ordering Information

14-Lead Dual In-Line Package

(Top View)

Part Number

Package

Operating
Temperature
Range

o

LM148D
LM148D/8838*

o

Notes:
·/883B suffix denotes Mil-8td-883, Level B processing
D = 14-lead ceramic DIP

Pin
Function

1 Output (A)
2 -Input (A)
3 +Input (A)
4

+VS

5 +Input (8)
6 -Input (8)
7 Output (8)

~5-04'8

Pin

Function
8 Output (C)
9 -Input (C)
10 +Input (C)
11 Ground
12 +Input (0)
13 -Input (0)
14 Output (0)

Thermal Characteristics
14-Lead
Ceramic
DIP

Absolute Maximum Ratings
Supply Voltage •.......•.•......•.•....•....•.•.•....•.... ±22V
Oifferentiallnput Voltage ........•.........•.•......••. 44V
Input Voltage' ..............................................................................±22V
Output Short Circuit Ouration 2 ....................... Indefinite
Storage Temperature
Range ..........•...•.•.•..••..•.•..... -65°C to +150°C
Operating Temperature Range
LM148 .......•....•..•....•..........• -55°C to +125°C
Lead Soldering Temperature
(GO sec) ......•.•.......•......•....•........•..•.•. +300°C

Max. Junc. Temp.

+175·C

Therm. Res. 9.l e

1042 mW
GO·CIW

Therm. Res. 9.IA
ForTA > 50·C
Derate at

8.33mW
per·C

Max. Po TA < 50·C

120·CIW

Notes:
1. For supply voltages less than ±15V, the absolute maximum
input voltage is equal to the supply voltage.
2. Short circuit to ground on one amplifier only.

3-472

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

LM148
Electrical Characteristics
(Vs = ±15V and TA = 25°C, unless otherwise noted)
Parameters
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance 1
(Differential Mode)
Supply Current
All Amplifiers
Large Signal Voltage Gain
Channel Separation
Unity Gain Bandwidth
Phase Margin
Slew Rate
Short Circuit Current

Test Conditions
RS ::;101<0

Output Voltage Swing
Input Vottage Range
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio

Typ
1.0
4.0
30

Max
5.0
25
100

Units
mV
nA
nA

0.8

2.5
2.4

3.6

MQ
rnA

Vs =±15V
Vs =±15V
VOUT = ±10V, RL ~2kQ
F =1 Hz to 20 kHz

50

160

V/mV

120
1.0

dB
MHz
Degrees
V/iJS
rnA

60
0.5
25

The following specifications apply for V~

Input Offset Voltage
Input Offset Current
Input Bias Current
Large Signal Voltage Gain

Min

=±15V ·55°C < Til < + 125°C.

RR::;101<0

6.0
75
325

mV
nA
nA
V/mV

Vs = ±15V, VOUT = 10V25
RI <21<0
Vs =±15V, RL = 10 kQ
RI =21<0
Vr::. =±15V
RSS10 kQ

±12
±10
±12
70

±13
±12
90

V
V
V
dB

Rs::;101<0

77

96

dB

Note:
1. Guarameed by design but not tested.

I
For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-473

LMl48
Typical Performance Characteristics
Input Bias Currert vs. Temperature

Supply Currert vs. Supply Voltage
6~--r---~--~---r---r---'

5 I------lf-

41----If--

i

90
80
70
/'
60
/' /'
50
c
~ r--... L L L
,.g 40 ['"'-..
~~~
30
¥
20
10

e-

-

31----1--

=
~~~~~--4---~---+--~;

O~~~~
__~~~~~~~~
o
±5
±10
±15
±20
±25
±30

;;.c:::

-

r- r-.

_~

I

v.=:I:2ov- r-V.=:t:15V_ r-V.-:t:10V- r-V.-:t:5V _

r--

~

~

c:-

o
-55 -35 ·15 +5 +25 +45 +65 +85 +105+125

iV.(V)

Positive Current Limit
Output Voltage vs. Output Source Current

Output Voltage SWing vs. Supply Voltage
50

I

40 f--

T"

15

I

~+25OC

/'

~30
~

/'

o
o

:.ss"C
V
+25°C
+125°C

±10

:t5

o
o

±20

±15

10

·15

)

o
o

+125°C

5

30

100

10

"

15

~

S

J

+25 OC -55"C

20

10

!

~

25

i

30

0.1
100

ISlNK(mA)

3-474

1 25

v. _:t:15V

,

-5

11

Output Impedance vs. Frequency

'\: -........;::: r--.....

~

~\

1K

c-....

·10

15

~

20
+1 SOURCE (mA)

5

iVa

Negative Currert Limit
Output Voltage vs. Output Sink Currert

v. = i15V

~"

./

10

,

,

V

V

)20

~--

10

Raytheon Semiconductor

~

1K

10K
F(Hz)

100K

1M

For More Infonnation, call 1-800-722·7074.

LM148
Typical Performance Characteristics (Continued)
Open Loop Gain VS. Frequency

CMRR vs. Frequency
110

120
100
80
60
40
20

.1.

v.

'" "'"

o

10

100

=±15V
T.=+25·C -

VS -±15V _
T. =+25'C _

90 ........
......

70

"

lK

I'..

iD

LM148

"

:l:!.. 50

,,;

10

'"

lOOK

F(Hz)

~

1M

~

-10
10

10M

100

........-::

r:::::

5

iD

o

±15V i
T. = +25'C

III

.f!>

\ ...........

\

"' -15
-20
-25

I'..

\.

1M

10M

10K

e.
090

20
10
0
-10

1

0.1

lOOK

F (Hz)

30

r\..

'- I\.

-30

-35

10K

Gain, Phase Test Circuit

Av

-5
:; -10

lK

100
90
80
70
60
50 til
40

IV! =

i'..

~

.......

o

Gain, Phase vs. Frequency
120
15
10

..........

........

I""

10K

30

~M148

~

~

10

F(MHz)

Small Signal Pulse Response
Input, Output VoHage VS. Time
100

t
}

0

V. = ±15V _
T.=+25·C
Av=l
-

.....
I

I

\

-10 0
<>

0

~

}
"-

-

:> 100

Sz

Large Signal Pulse Response
Output Voltage VS. Time

V

0
-1 0

/

I\..

L

'\

"-...

<::-

VB • ±15V
T •• +25'C

~1 0

0

a!

Av ·l

0

R L Z2K

> -1 0

:>-100

o

2

3

4

I

o

40

80

120

160

~
200

Time (1lS)

Time (1lS)

For Mora Information, call 1-800-722-7074.

I

:"-

/

Raytheon Semiconductor

3-475

LM148
Typical Performance Characteristics (Continued)
Gain Bandwidth Product vs. Temperature

Unclistorted Output Voltage Swing vs. Frequency
32
Vs = ±15V

2S

TA =+25°0-

24

Ay = 1
RL=2K
-8......-0 VOUT

RI2

Vour=2

(!~

+ 1) • (-Vs -3V )

~ VINCY ~(+VS-3V)

Vs - ±15V
R = R2. trim R2 to boost CMRR

65-1140

Figure 3. Low Cost Instrumentation Amplifier

Adjust R for minium drift
03 low leakage diode
01 added to improve speed
Vs .±15V

I

6501159

Figure 4. Low Voltage Peak Detector With Bias Current Compensation

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-479

LM148
Typical Applications

R5

(Continued)

lOOK

RS

C2
O.OOlJ1F

10K

Rl
R2

7
RO

Tune Q through RO
for predictable results: Fo Q S 4 xl 0"
Use bandpass output to tune for Q
VIs)
VIN(S) =

N(s)
D(s)

Scno

D(s) = S2 +

Q

.

+

0lg2

NHP(S) - S2 HOHP' NBP(S)" .5Olg HOBP
Q

Fo:

...!.- IRs
2lt

{1

v' Rs v' i1t2

,

t1 = R1Cl Q= (1 + R41 R3+R41 RO\
,
1+RSIR5
/

FNOTCH = ..!...
(~)112 , HOHP:
2lt
F\. tl t2
HOlP ",

(~
R5

tt21

SI2
J

1+R6IR5
H
1+R4IR3+R4IRO
1+R3IRO+R3IR4' OSP"' 1+R3IRO+R3IR4

1+R5IRS
1+R3IRO+R31R4

65-1160

Figure 5. Universal State-Space Filter
100K

150K _ _~
VIN O-..J\jVlr
~+-UVOUT1

4.556K
:

~_ _ _ _ _ _ _ _ _ _~~l00VK~_ _ _ _ _~

39.4K

65-1161

Use general equations, and tune each section separately.
01s1 Section 0.541, 02nd Section 1.306.
The response should have 0 dB peaking.

=

=

Figure 6. 1 kHz 4-Pole Butterworth Filter

3-480

Raytheon Semiconductor

For More Information, caJI1-800-722-7074.

LM148
Typical Applications

(Continued)

R7

R8

R1

C2

Cl
R3
R6
R4

0--+-----------......-----------'

VIN(S)

Q
=

IRs (

V R7

R1Cl
) F
1 {fVJ (
1
) F
1 L
R6
VR3C2R2C1 ' 0 = 2ff:{ FfT
o/R2R3C1C2' NOTCH • 2xVR3R5R7C1C2

Necessary condition for notch :

1

R6

=

Rl
R4R7

Examples: FNOTCH = 3 kHz, Q =5, Rl =270K, R2 =R3 =20K. R4 =27K. R5 =2OK, R6 = R8 = 10K, R7 = lOOK.
Cl = C2 = 0.001 1If.
Better noise perfonnance than the state-space approach.

65-1162

Figure 7. 3 Amplifier Bi-Quad Notch Filter
R5
lOOK

Gain VB Frequency

'1~1II

_·20

V,N

III

R3

·30

~-IO

o-..JVVIr_-.!:.I

·50
·60
·70

RO

100

1K

10K

100K

F(Hz)

R"O

I

Fe . l kHz, Fs =2 kHz, Fp= 0.543. Fz • 2.14, Q. 0.841, pp. 0.987, Pz -4.92.

a • 4.403 normalized to ripple BW.
Fp.

+xn

G-).Fz

-~~(+1,Q· 1+~':;~41RO x!Ws

,a.

'i/Pi6i5

1 + R"41R"0

x:l -+-::R':::61=R='S'-'+"'=R:::'6/R=-p

Use the B'P outputs to tune Q, a, tune the 2 sections seperately.

Rl.R2_92.6K, R3.R4. RS. lOOK, R6_10K, RO.l07.8K,Ro. .100K,Rti • 155.1K,
R"1 • R'2. SO.9K, R"4 - R"S = lOOK, R'6 • 10K, R'O - 5.78K, R"L • lOOK, Ril .24B.12K, R'F .10OK.

65-1163

All capacitors are 0.001 flF.

Figure 8. 4th Order 1 kHz Elliptic Filter (4 Poles, 4 Zeros)

For More Infonnation, call 1-800-722-7074.

Raytheon Semiconductor

3-481

LMl48
Schematic Diagram

(1/4 Shown)

r-------.....,------------t--o

(4)

-Vs

R8

25
Output

(1.7.8.14)

R9

22

R6
1K

L-.--~-+--_+---_+_-_+-___4~----_+_--_6____O (11)

-Va
65-1136

3-482

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

OP-07
OP-07
Precision Operational Amplifier
Description

Features

The OP-07 operational amplifier is designed for
precision low-level signal conditioning where ultra low
Vos and TeVos are required along with very low
bias currents. Internal compensation eliminates the
need for external components. Novel circuit design
and tight process controls are used to obtain very low
values of Vos which is further reduced by computer
controlled digital nulling techniques at test. Low
frequency noise is minimized. Internal biasing
techniques reduce external bias and offset currents to
values on the order of ±1 nA over the military
temperature range. The OP-07 is a direct
replacement for the 10BA. The OP-07 can also
replace chopper stabilized amplifiers in many
applications.

•
•
•
•
•
•
•
•
•

Low noise - 0.35 INp~p (0.1 Hz to 10Hz)
Ultra low Vos -10 ~v
Ultra low Vas drift - 0.2 ~vre
Long term stability - 0.2 ~V/Mo
Low Input bias current - ±1 nA
High CMRR -120 dB min
Wide input voltage range - ±14V
Wide supply voltage range - f!JV to ±22V
Fits 10BA and 741 sockets

I
For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-483

OP-07
Ordering Information
Part Number

Package

Connection Information
Operating
Temperature
Range

OP-07CN
OP-07DN
OP-07EN
OP-07CM
OP-07DM
OP-07EM

N
N
N
M
M
M

O'Cto+70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C

OP-07T
OP-07T/8838
OP-07AT
OP-07AT/8838
OP-07D
OP-07D/8838
OP-07AD
OP-07AD/8838

T
T
T
T
0
0
0
0

-55'C to +125'C
-55'C to +125'C
-55'C to +125'C
-SS'C to +12S'C
-55'C to +125'C
-55'C to +125'C
-55'C to +125'C
-55'C to +125'C

8-Lead

8-Lead

T0-99 Metal can
(Top View)

Dualln-Une Package
(Top View)

85-032C6

a-Lead Plastic
Dual In-Line S()..8

(Top View)

I883B suffix denotes Mil-Std-883, Level B prooessing

N =8-Jeacl plastic DIP
T = 8-lead metal can (T0-99)
M = 8-lead plastic SOIC

3-484

6S-02666

Raytheon Semiconductor

Function

1
2

Ves Trim
-Input
+Input
-Vs (Case)
NC
Output
+VS
VOS Trim

3

NOles:

-

Pin

4
5
6
7
8

For More Infonnation, call 1-800-722-7074.

OP-07
Absolute Maximum Ratings
Supply Voltage .............................................±2.2V
Input Voltage 1 .................................................... ±2.2V
Differential Input Voltage ................................ 30V
Internal Power Dissipation 2 ........................ SOO mW
Output Short Circuit Duration .................. Indefinite
Storage Temperature
Range ................................... -6S·C to +1S0'C
Operating Temperature Range
OP-07A ................................. -SS·C to +12S'C
OP-07E1C/D ............................ -2S'C to t8S'C
Lead Soldering Temperature
SO-8 (10 sec) ..................................... +260·C
T0-99, DIP (60 sec) ........................... +300·C
Notes:
1. For supply voltages less than ¥.22V. the absolute maximum

ill'ut voltage is equal to the suWly vokage.
2. Observe package thermal characteristics.

Thermal Characteristics
a-Lead
Ceramic DIP

a-Lead
TO-99
Metal Can

a-Lead
Plastic

SO

8-Lead
Plastic DIP

Max. Junction Temp.

+175'C

+175'C

+125'C

+125'C

Max. Po T A <50'C

833mW

658mW

300mW

468mW

Therm. Res 9JC

45'C/W

50'C/W

-

-

Therm. Res. 9JA

150'C/W

190'C/W

240'C/W

160'CIW

8.33mWrC

5.26 mW/,C

4.17 mwrc

6.25 mW/,C

For TA >50'C Derate at

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

I
3-485

OP-07
Electrical Characteristics
(Vs = ±1SV and TA = +2S'C unless otherwise noted)
Parameters
Input Offset VoHage 1
Long Term Ves Stability3.4
Input Offset Current
Input Bias Current
Input Noise VoHage2
Input Noise VoHage OensHy2
Input Noise Current~
Input Noise Current OensHy2
Input Resistance (Oiff. Mode)"
Input Resistance (Com. Mode)
Input VoHage Range
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal VoHage Gain

Test Conditions

Min

0.1 Hz to 10 Hz
Fo = 10 Hz
Fo=100Hz
Fo= 1000 Hz
0.1 Hz 10 10 Hz

30

RL~2kD,

Max

OP-07
Typ

10
0.2
0.3
fD.7

Max

Units

25
1.0
2.0
±2.0

30
0.2
0.4
±1.0

75
1.0
2.8
±3.0

/lV
/lVlMo
nA
nA

0.35
10.3
10

0.6
18
13

0.35

/lVo-o

9.6
14

11
30
0.80

9.6
14

0.6
18
13
11
35
0.80

pAO-D

0.23
0.17

~

0.32

Fo = 10 Hz
Fa=100Hz
FO = 1000 Hz

VCM=±13V
Vs =±3Vto±18V

OP-07A
Typ

±13
110
100
300

0.14
0.12
80
200
±14

Min

10.3
10

0.32

0.23
0.17
20
±13

126
110
500

110
100
200

150

500

±12.5

±13

0.14
0.12
60
200
±14
126

Output VoHage Swing

RL ~ 500 kD, VOUT
.. ±O.5V, Vs=±3V
RL ~10 kD,
RL~2

kD,

Rl ~1 kD,
Slew Rate
UnHy Gain Bandwidth

RL~2

kD,

AVOL =+1.0

Open Loop Output Resistance
Power Consumption

VOUT = 0, lOUT = 0
Vs =±15V
Vs =±3V

Offset Adjustment Range

RTRIM =20kO

.JHz

.JHi
MO

Gn
V
dB

110
500

dB

150

500

VlmV

±12.5

±13

VlmV

VOUT= ±10V
Large Signal VoHage Gain3

nV

±12

±12.8

±12

±12.8

±10.5

±12

±12

0.1

0.3
0.8

±10.5
0.1

60
75
4.0
±4.0

120
6.0

V

VI(lS
MHz

0.3
0.8
60
75
4.0
±4.0

n
120

mW

6.0
mV

NOles:
1. Input Offset Voltage measurements are performed by automated test equpment approximately 0.5 seconds after appUcation 01 power. OP~7A is tested
fully warmed up.
2. This parameter is tested on a sample basis only.
3. Guaranteed but not tested.
4. Long Term Input Offset Voltage Stability refers to the average trend Hne of Vos vs. Time over extended periods after the first 30 days of ql8ration.
Excluding the initial hour of ql8ration. changes in Vos during the first 30 ql8rating days are typically 2.54 /JoV.

3-486

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

OP-07
Electrical Characteristics

=

=

(VS ±15V and TA +25·C unless otherwise noted)
Parameters
Input Offset VoHage 1
Long Term Input
Offset VoHage Stability3.4
Input Offset Current
Input Bias Current
Input Noise VoHage~
Input Noise VoHage
Density2
Input Noise Current2
Input Noise Current
Density2
Input Resistance 3
(Differential Mode)
Input Resistance
(Common Mode)
Input VoHage Range
Common Mode
Rejection Ratio

Test CandHlons

Min

0.1 Hz to 10 Hz
Fo = 10 Hz
Fo = 100 Hz
Fo = 1000 Hz
0.1 Hz to 10 Hz
Fo=10Hz
Fo =100 Hz
FO = 1000 Hz
15

OP-07C
OP-07D
OP-07E
Typ IMax Min Typ Max Min Typ Max
75
60 150
30
60 150
0.3 1.5
0.4 2.0
0.5 3.0
0.5 3.8
±1.2 ±4.0
0.35 0.6
10.3 18
10
13
9.6
11
14
30
0.32 0.8
0.14 0.23
0.12 0.17
50

8.0

160

0.8
±1.8
0.38
10.5
10.2
9.8
15
0.35
0.15
0.13
335

6.0
±7.0
0.65
20
13.5
11.5
35
0.9
0.27
0.18
7.0

120

0.8
::12.0
0.38
10.5
10.2
9.8
15
0.35
0.15
0.13
31

6.0
±12
0.65
20
13.5
11.5
35
0.9
0.27
0.18

UnHs
IlV
IlV/Mo
nA
nA
IlVo-o
nV

¥Z
pAp_p
pA
Vliz
Mil

120

Gil

VCM=±13V

±13
106

±14
123

±13
100

±14
120

±13
94

±14
110

V
dB

powerSU~IY

Vs =±3Vto±18V

94

107

90

104

90

104

dB

Large Signal VoHage Gain

RL~2kO,

200

500

1200 400

120

400

VlmV

Rejection atio

VOUT =±10V
Large Signal Voltage Gain;s RL ~ 500 kO, VOUT
=±0.5V, Vs =±3V
RL~2k.Q

150 500
±12.5 ±13
±12 ±12.8

R

~1

+10.5 +12

RJ

~2k.Q

0.1
0.8

RL~10k.Q

Output VoHage Swing

Slew Rate

kil

100 400
±12 ±13
±11.5 ±12.8

400
±12 ±13
±11.5 ±12.8

V/mV
V

+12

0.3

0.1

0.3

0.1

0.3

V/f.l.S

Unity Gain Bandwidth

AVCL =+1.0

Open Loop Output
Resistance

VOUT'; 0, lOUT = 0

60

Power Consumption

Vs = ±15V, RL = 00

75

120

80

150

80

150

VS=±3V, RL =00

4.0

6.0

4.0

8.0

4.0

8.0

RTRIM = 20 k.Q

±4.0

Offset Adjustment Range

For More Information, call 1-800-722-7074.

0.8

0.8
60

Raytheon Semiconductor

±4.0

I

MHz
il

60

±4.0

mW
mV

3-487

OP-07.
Electrical Characteristics (Vs = ±15V, -55"C s; TA g 125"C unless otherwise noted)
Parameters

Test Conditions

Min

Input Offset VoHage
Average Input Offset VOHape
Drift without External Trim
With External Trim3

OP-07A
Typ

Max

25
0.2

SO
O.S

0.2
0.8

OP-07B
Typ

Max

Units

SO
0.3

200

JlV

O.S
4.0
25

0.3
1.2
8.0

1.3
5.6

M.O

:12.0
13

:1:6.0

nA

50

pA/"C

Min

1.3
JlVJOC

RTRIM =201<0

Input Offset Current
Average Input Offset
Current Drift2

5.0

Input Bias Current

±1.0
8.0

Average Input Bias
Current Drift2
Input Voltage Range
Common Mode Rejection Ratio
Power Supply Rejection Ratio

VCM =±13V
Vs ±3Vto ±18V

±13
106
94

Large Signal VoHage Gain

RL~2

kO,
Vour=±10V

Output Voltage

RL~2kO,

0:

25

50

nA
pA/"C

±13
106

±13.5
123

200

±13.5
123
106
400

94
150

106
400

V
dB
dB
V/mV

±12

±12.S

±12

±12.S

V

Electrical Characteristics (Vs = ±15V, OOC S; TAS; +70OC unless otherwise noted)
Parameters

Test Conditions

Min

OP-07C
OP-07D
OP-07E
Typ Max Min Typ Max Min Typ Max

Input Offset VoHage 1

45

130

85

250

85

250

Average Input Offset Voltage
Drift without External Trim
With External Trim3

0.3

1.3

0.5

1.8

0.7

2.5

0.3

1.3

0.4

1.S

0.7

2.5

Units
JlV
JlVJOC

RTRIM =201<0

Input Offset Current

0.9

5.3

1.S

8.0

1.S

8.0

nA

Average inPut unset
Current Drift2

8.0

35

12

50

12

50

pN"C

Input Bias Current

±1.5 :1:5.5

Average Input Bias
Current Drift2

13

±2.2 ±9.0
18

35

±3.0 ±14
18

50

50

nA
pA/"C

Input Voltage Range

±13 ±13.5

±13 ±13.5

±13 ±13.5

V

Common Mode Rejection
Ratio

VCM~±13V

103

123

97

120

94

106

dB

Power Supply Rejection
Ratio

Vs =±3Vto ±18V

90

104

86

100

86

100

dB

Large Signal Voltage Gain

RL~2 kO,
VOUT =±10V

180

450

100

400

100

400

VlmV

Output VoHage Swing

RL~21,,6_-<>--0 VOIJr

+15V

10K

+15V
01

±IOV

Reference

Junction

-15V
02

R4

Rl

·15V

R2

ra='R4

·15V

R2
10K

Nole: Pin numbers shown are for 8·lead packages.

65-3217

65-3216

High Stability Thermocouple Amplffier
3-492

Precision Absolute Value Circuit

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

OP-07
Schematic Diagram
(7)

+~O-----~------~~---------'------1------'----~----~----~~~~--~
R2B(1)

8K

C1
75pF

R1B
42K

(3)

Output

FI3
500

(6)

D27

+Input

C3
300pF

R5
021

D22

D26

3K

D25

(2)
·~t

R4
500

(4)

·Vs
Notes:

1. R2A and R2B are electronically adjusted during factory test for mlnlum Vos.
2. Pin numbers shown are for a·lead packages.

I
For More Information. caD 1-800-722·7074.

Raytheon Semiconductor

3-493

OP-07

3-494

Raytheon Semiconductor

For More Information, caJI1-800-722-7074.

OP-27
OP-27

Low Noise Operational Amplifier
Description
The OP-27 is designed for instrumentation grade
signal conditioning where low noise (both spectral
density and burst), wide bandwidth, and high slew rate
are required along with low input offset voltage, low
input offset temperature coefficient and low input bias
currents. These features are all available in a device
which Is internally compensated for excellent phase
margin (70') in a unity gain configuration.

The OP-27 is available in SO-8 (small-outline), TO-99
can, plastic mini-DIP and ceramic mini-DIP packages,
and can be ordered with Mil-Std-883 Level B
processing.

Digital nulling techniques performed at wafer sort
make it feasible to guarantee temperature stable input
offset voltages as low as 25 j.LV. Input bias current
cancellation techniques are used to obtain 10 nA input
bias currents.

Features

The OP-27 design uniquely addresses the needs of
the Instrumentation designer. Power supply rejection
and common mode rejection are both in excess of 120
dB. A phase margin of 70' at unity gain guards
against peaking (and ringing) in low gain feedback
circuits. Stable operation can be obtained with
capacitive loads up to 2000 pP. Input offset voltage
can be externally trimmed without affecting input offset
voltage drift with temperature or time. The drift
performance is, in fact, so good that the system
designer must be cautioned that stray thermoelectric
voltages generated by dissimilar metal at the contacts
to the input terminals are enough to degrade its
performance. For this reason it is also important to
keep both input terminals at the same relative
temperature.

For More Information, caJI1-800-722-7074.

"By decoupling the load capacitance with a series resistor of 50n
or more, load capacitances larger than 2000 pF can be
accommodated.

• Very low noise
Spectral noise density - 3.0 nV/~Hz
1/F noise corner frequency - 2.7 Hz
• Very low Vos drift
0.2 j.LV/Mo
0.2j.LVrC
• High gain - 1800 VlmV
• High output drive capability - ±12V into
600nload
• High slew rate -2.8 V/j.LS
• Wide gain bandwidth product - 8 MHz
• Good CMRR - 126 dB
• LowVos-10j.LV
• Low noise - 0.08 j.LV pop (0.1 Hz to 10Hz)
• Low input bias current-±10 nA

Raytheon Semiconductor

I
3-495

OP-27
Connection Information
8-Lead
T0-99 Metal Can

Ordering Information

8-Lead Plastic
Dual In-LIne 50-8

(Top View)

Package

Operating
Temperature
Range

OP-27EN
OP-27FN
OP-27GN
OP-27EM
OP-27FM
OP-27GM

N
N
N
M
M
M

O'C to +70'C
O'C to +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'C to +70'C

OP-27AD
OP-27AD/B83
OP-27BD
OP-27BD/883
OP-27CD
OP-27CD/883
OP-27AT
OP-27AT/883
OP-27BT
OP-27BT/883
OP-27CT
OP-27CT/883

D
D
0
0
D
D
T
T
T
T
T
T

-55'C to +125'C
-SS'C to +125'C
-55'C to +125'C
-S5'C to +125'C
-55'C to +125'C
-55'C to +12S'C
-55'C to +125'C
-55'C to +125'C
-55'C to +125'C
-55'C to +125'C
-55'C to +125'C
-55'C to +125'C

Part Number

{]
65-02666
65-03205

8-Lead
Dual In-LIne Package
(Top View)

Pin
1
2
3
4

5
6
7
8
6lHl3206A

Function
Vas Trim
-Input
+Input
-VS
NC
Output
+VS
Vas Trim

Notes:
18838 suffix denotes Mil-5td-883, Level 8 prooessing
N = S-Iead plastic OIP
= 8-lead ceramic OIP
T =S-Iead metal can (T0-99)
M =8-lead plastic sOle

o

3-496

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

OP-27
Absolute Maximum Ratings
Supply Voltage .............................................f2.2V
Input Voltage 1 .................................................... i2.2V
Differential Input Voltage ............................... 0.7V
Internal Power Dissipation2 ........................ 658 mW
Output Short Circuit Duration ................. .lndefinite
Storage Temperature
Range ........................................ -65·C to +150'C
Operating Temperature Range
OP-27AlBIC ............................... -55'C to +125'C
OP-27E1F/G .................................... O'C to +70'C
Lead Soldering Temperature
(SO-8, 10 sec) ......................................... +260·C
(DIP,TO-99; 60 sec) ................................ +300·C
N~es:

1. For s~ voltages less than ~2V. the absolute maximum
irpl.l voltage is equal \0 the supply vokage.
2. Observe package thermal characterislics.

Thermal Characteristics
8-Lead
Small
Outline

8-Lead
Ceramic
DIP

8-Lead
TO-99
Metal Can

8-Lead
Plastic
DIP

Max. Junction Temp.

+125'C

+175'C

+175'C

+125'C

Max. Po TA <50'C

300mW

833mW

658mW

468mW

Therm. Res BJC

-

45'C/W

50'C/W

-

Therm. Res. BJA

240'C/W

150'C/W

190'C/W

160'C/W

4.17 mW/,C

8.33mWtC

5.26 mW/,C

6.25mWtC

For TA >50'C Derate at

I
For More Infonnation, call 1-800-722-7074.

Raytheon Semiconductor

3-497

OP-27
Electrical Characteristics

=

=

(Vs ±15V and TA +25'C unless otherwise noted)

Test Conditions

Min

01).27C/(

OP.27B/I

OP·27A11

Parameters

TYD Max Min

Typ Max Min

Input Offset VoHage 5

10

25

20

60

Long Term Input Offset
VoHage Stability 1. 4

0.2

1.0

0.3

1.5

Typ

Units

30

Max
100

0.4

2.0

JlV/Mo

JlV

Input Offset Current

7.0

35

9:0

50

12

75

nA

Input Bias Current

±10

±40

±12

:1:55

±15

±SO

nA

Input Noise VoHage2

0.1 Hz to 10 Hz

O.OS 0.1S

O.OS p.1S

0.09 0.25

Fo=10Hz

3.5

3.5

3.S

S.O

Input Noise VoHage

Fo=30Hz

3.1

4.5

3.1

4.5

3.3

5.6

Oensity2

Fo= 1000 Hz

3.0

3.S

3.0

3.S

3.2

4.5

Fa= 10 Hz

1.7

4.0

1.7

4.0

1.7

5.5

5.5

Input Noise Current

Fa =30 Hz

1.0

2.3

1.0

2.3

1.0

Oensity2

Fa = 1000 Hz

0.4

0.6

0.4

0.6

0.4

1.5

Input Resistance
(Oiff. Mode)4
Input Resistance
(Com. Mode)

1.2

6.0
3.0

0.8

5.0
2.5

JlVp.p
nV

v'Ri
~

0.6

-1Hz

4.0

Mn

2.0

GO

Input von age Range3

±11 ±12.3

±11 ±12.3

±11

12.3

V

Common Mode
Rejection Ratio

VCM =±11V

114

126

106

123

100

120

dB

Power Supply
Rejection Ratio

Vs ±4Vto±18V

100

120

100

120

94

118

dB

RL~2kO,

Large Signal VoHage Gain

Output VoHage Swing
Slew Rate4

RL~ 1 kO,

VOUr=±10V 1000 1800
VauT =±10V 800 1500

1500

700

200

250

RL~2kO,

±12 ±13.S

RL~600o.

±11

±12

±11

±12

±11

±12

V

RL~2kO,

1.7

2.8

1.7

2.8

1.7

2.8

V/jJS

5.0

B.O

5.0

B.O

5.0

S.O

MHz

70

n

VOUT = O.IOUT = 0

70
90

RTRIM = 10kn

250

V/mV

±12 i±13.S

Power Consumption
Offset Adjustment Range

700 1500

SOO 1500

VOUT = ±1V. Vs=±4V

Gain Bandwidth Product4
Open Loop Output
Resistance

700

1000 1S00

70
140

±4.0

90
±4.0

500

±11.5 13.5

140

100

170
±4.0

mW
mV

Notes:
1. Long Term Input OIIset Voltage Stability refers to the average trend fine of Vos vs. Time over extended periods after the first 30 days of operalion.
Excluding the innial hour of operation, changes in Ves during the first 30 operating days are typically 2.5IlV.
2. This parameter is tested on a sample basis only.
3. Caution: The Common Mode Input Range is a function 01 s~1y voltage. See Typical Performance Curves. Also, the input proledion diodes do not aHow
the device to be removed or inserted into the circun w~hout first removing power.
4. Parameter is guaranteed but not tested.
5. Input OIIset Vokage measurements are performed by automated test equipment approximalely 0.5 seconds after application of power.

3-498

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

OP-27
Electrical Characteristics
(Vs = ±1SV. -SS'C $oTA So +125'C unless otherwise noted)
Parameters

Test Conditions

Min

OP-27A
Typ Max

Input Offset Voltage 1

30

60

Average Input Offset
Voltage DrHt2

0.2

0.6

Input Offset Current
Input Bias Current

OP·27B
Typ Max

Min

OP·27C
Typ Max

Units

50

200

70

300

0.3

1.3

0.4

1.8

30

135

nA

±35 ±150

nA

15

50

22

85

±20

±60

±28

±95

±10.3 ±11.5

Input Voltage Range

Min

±10.3 ±11.5

I1V
I1

vrc

±10.2 ±11.5

V

Common Mode
Rejection Ratio

VCM -±10V

108

122

100

119

94

116

dB

Power Supply
Rejection Ratio

VS - ±4.5Vto ±18V

96

116

94

114

86

110

dB

Large Signal Voltage Gain

RL~2

500

1000

300

800

VlmV

Output Voltage Swing

RL~kn

1<0, VOUT -±1 V600 1200
±11.5 ±13.5

±10.5 ±13

±11 ±13.2

V

Electrical Characteristics
(Vs = ±1SV. O'C S TAs +70'C for plastic package unless otherwise noted)
Test Conditions

Parameters

Min

OP·27E
Typ Max

Min

OP·27F
Typ Max

Min

OP·27G
Typ Max

Units

Input Offset Voltage 1

20

50

40

140

55

220

Average Input Offset
Voltage Drnt2

0.2

0.6

0.3

1.3

0.4

1.8

20

135

nA

±25 ±150

nA

Input Offset Current
Input !:lIas vurrent
Input voltage Range

10

50

14

85

±14

±60

±18

±95

t±10.5 ±11.8

±10.5 ±11.8

±10.5 ±11.8

I1V
I1

vrc

v

Common Mode
Rejection Ratio

VCM -±10V

110

124

102

121

96

118

dB

Power Supply
Rejection Ratio

Vs - ±4.5V to ±18V

97

118

96

116

90

114

dB

Large Signal Voltage Gain RL~2kn. VOUT -±10V 750

1500

700

1300

450

1000

VlmV

f-t:11.4 ±13.5

±11

±13.3

V

Output Voltage Swing

RL~I

"-

5

o
-5
-10
1

TA - +25°C

1""..

.70°

~

1

100

F (MHz)

3-500

1\
r\

70

~

100

120

160

'"

10

80

140

\

\

r--

I......

10

100

lK

10K lOOK

1M

!

I'"

10M 100M

Slew Rate, Gain Bandwidth Product,
Phase Margin vs. Temperature

t 1±1~) I

l"-

"- r-...

~

F(Hz)

$

",Av
16

'" I......

-10

Gain, Phase Shift vs. Frequency

~

['0"

10

F(Hz)

25

'"

30

III

1.0

......

90

iii
:2-

30

i""""""""o.

180

Ci

e

~

10

ti::

60

I

t-

Vs - +15V

9

GBW

r--....

50

--

r-- f-

4

::E

e

200
220

100

3

a:
rn

,~

SL

1:::

2
-75

-50

65-0006

Raytheon Semiconductor

~

-25

6
0

25

50

75

100

125
65-0007

For More Infonnation, call 1-800-722-7074.

OP-27
Typical Performance Characteristics (Continued)
Maximum Output Swing VS. Load Resistance

Supply Current vs. Total Supply Voltage
18

10

-

8

-

~

T~ K+25°;"- ~

I.---

r- l-~i-55OCI

4

2

b

T" =1+12so

~

...r-

6

15

5

-VS

--

~

~

I.
1
+VOUT

L

10

/'

.,-

~

~

~

-VOUT

//

6

V

2

!

!

-2

45

35

25

2:1:15~

14 -TA=+25"C

0.1

10

1.0

+Vs to .Vs (V)

RL(kn)

Open loop Gain VS. Supply Voltage

Short Circun Current vs. Time
2.5

60

I
T,,-+25°C

50

C

.s
.J

40

2.0
~

..... r--....

~

30

Vs=~5V

-

Isc(+)

TA=+25°C

.....
r-- .....

-

>

-

~

1.5

£

1.0

oJ

Isc (-)

~V

o

o

2

3

4

o

5

:1:5

:1:10

Gain, Phase Shift vs. Frequency

16r------r------~----~--~~

T,,-+25°C

8

16

~

12

>

2:

i!

8

o

1K

10K

100K

4
0

-4
-8

~

4

I

12

Vs-~5V

\

20

1M

!

10M

ij

-12

IS

-16
0

!5

!10

!15

!20

±Vs (V)

F (Hz)

For More Information, caJI1-800-722-7074.

:t20

Common Mode Input Range vs. Supply Voltage

11111111 I

24

:t15

±Vs (Volts)

28

}

RL -1kO

,/

Time (MIn)

~

::::-

0.5

20

10

I,

RL-2~

Raytheon Semiconductor

3-501

OP-27
Typical Performance Characteristics (Continued)
Op Amp Comparison
Input Noise Vonage Density vs. Frequency

Input Noise Vonage Density vs. Frequency
10

100

Vs -115V
TA _+25°C

5

", i"r,

t

:>

.sc
CD

1

il'

-

~~

Lj
10

:>

s.

~

C
til

~rmilir
1

741

~

'"~

Low Noise
Audio
OpAmp

O~-2171_ -'lIF Comer

......

II

!

Instrumentation Range to DC Audio Range to 20 kHz

1
1

'"
1000

100

~

1~111F Corner 2.7 Hz

of>

10

~~-lllir

100

10

1000

F(Hz)

F (Hz)

Input Noise Current Density vs. Frequency

Input Noise Vonage Density vs. Supply Vonage
S

10·°ma=~11

I

I10 Hz

-

4

TA=+2SoC

at

-

at

1.0 kHz

2

1

10K

1K

100

o

±10

±S

±Vs (V)

F(Hz)

Input Noise Vonage Density vs. Temperature

Input Offset Vonage Drift of Representative Units
60

Vs = t1SV

4

±20

±1S

r---+---~---+--~~--+-~~~~

~

20

>"

a:

0

!--

.} -20

1~~--~~--~~--~~!
-25
o +25 +50 +75 +100 +125

-60

-80

[-

OP-27B
~ I"P-27A

r-.. OP-27A
r-r---... ......... r- OP-J7B
Trimming With 10K
i'....
I
Pot Does Not
..........

-40
2~--4---~---4----r---+---~--~

-~

I.:::::::::

OP-27C

V ~ OP-27B
I
V V OP-27A

- -...-r

:----.. -~-27C

~

~

~~
" ~ ~prB

10

c(

:--r--

§

OP-27A

o
-75 -50

-25

0

25

:8

50

75

100 125

2.4
r - I 1 IIII~II
2.2
T A= +2S-v
2.0 r - vs=tlSV
1.8
/
1.6
1.4
1.2
1.0
0.8
II
0.6
0.4
0.1
1.0

TA (Oc)

I-"

70 I - 60

aI

-vs

~
+vs "

~

~

......

50
40

~
"~

"~

1

10

10'

10' 10' 10' 10'

!

10' 10'

"

100

VCM=~OV

II

I'

80

"

60
40
10'

10'

10'

10'

!

10'

F(Hz)

F (Hz)

For More Information. call 1-800-722-7074.

I

TA=+2S0C

~

~

II~~=UJI

I'

120

-...~

aI 100
~
a: 80 I - a:

100

CMRR vs. Frequency

TA=+2SoC

120 1 -

!

10

140

160
140

100 125 1S0

RL(k)

PSRR vs. Frequency

If

75

Open Loop Gain vs. Load Resistance

VSI=±liv

40

20

50

TA (Oc)

50

]

!

i

o

Time (Min)

30

I
OP-27A

o
o

1

OP-27B

Raytheon Semiconductor

3-503

OP-27
Typical Performance Characteristics (Continued)
Small Signal Overshoot vs. Capactlive Load
100

_t
I

80

b--'""

....... 60

C

~ 40

/

V

~ci:~ion

/

A

.,

. ..... 11

lll. IA .A

r\. lI\A l.,I..

-

Vs = ±15V
VIN =l00mV_

20

I
o II
o

0.1 Hz to 10 Hz Peak-Io-Peak Noise vs. Time

Av= +1.0

1
500

1000

1500

I
2000

~

o

2500

30

15

45

Time (Sec)

CL (pF)

+20V

65-0028

Input Offset Trimming CircuH

Burn-In Circutt

J .~
"

v=
.>--11_4

2.SVlJl.S

When R F ~ 100n and the input is driven
with a fast, large signal pulse ( ~ 1.0V).
the output waveform will appear as shown.
Note: Pin numbers shown are for 8-lead packages.

65-0030

Large Signal Transient Response

3-504

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

OP-27
Typical Applications
RIAA Phono PreamplHier (Figure 1)
The new moving coil magnetic phono cartridges have
sensitivities that are an order of magnitude lower than
the sensitivity of a typical moving magnet cartridge (0.1
mV per CMlS versus 1.0 mV per CMlS). This places a
greater burden on the preamplifier to achieve more
gain and less noise. The OP-27 is ideally suited for
this task. The object in designing an RIM phono
preamp is to achieve the RIM gain-frequency
response curve while contributing as little noise as
possible to avoid masking the very small signal
generated by the cartridge. The circuit shown is
adjusted to match a 40 dB RIM curve as shown in
Figure 2. Note that by convention the RIM gain is
specified at 1 kHz. With the "break points" of the
curves specified at 50,500 and 2.1 kHz, respectively,
the entire curve is fixed by the specified gain at 1kHz.
The circuit is designed to operate with a 3140000
step-up transformer to present the optimum source
impedance to the amplifier for best noise figure. The
optimum source impedance is obtained as the ratiO of

the spectral noise voltage en to the spectral noise
current IN (when en has dimensions of nV/...JHz and IN
has dimensions of pAl...JHz and the ratio has
dimensions of k,OJ. The circuit is deSigned to be
tested and adjusted independent of the transformer.
For testing, introduce a very low level signal of 1 mV at
test point TP-1. The first stage is a wideband stage
which provides a small amount of gain (1 + R4/R5)
approximately equal to 10 dB. Low value feedback
resistors must be used to prevent additional noise due
to the spectral current noise or excessive Johnson
noise. The gain of the first stage reduces the noise
contribution of the second stage. The RIM transfer
curve poles and zeros are due entirely to the feedback
network of the second stage.
The poles and zeros of the RIM feedback network
are sufficiently separated in frequency that they may
be estimated with the following equations:
F1(50 Hz) ~

27tR7C3
1

F2(500 Hz) ~

27tR~C3
27tR8C2

F3(2100 Hz)

~

C4A
330

C4B2700
RBB33K
RBA
138K
Ferrite

TP-1

Beads

l3.0040000
3.00 Moving
Coil Cartridge
65-0031

Noles:
1. To lest, disconnect transformer and inject signal aITP·1.
2. Pin numbers shown are lor S-Iead packages.

Figure 1. RIM Phono Preamplifier

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-505

OP-27
I I
I I

......

I
I
I
I

I
I
I
I
I

-,,--I
I
I
I

value and the source impedance at the output of this
transformer, approximately 15 kn, still provides near
optimum noise performance. (A high quality audio
transformer with a step-up ratio of 6.7 to one is not
available.) The voltage gain of the amplifier, not
including the transformer step-up, is unity up to about
1.5 Hz. It may be desirable to reduce the size of this
capacitor to minimize burst noise even though the
OP-27 has a 1/F noise corner below 3 Hz. C2 rolls off
the high frequency response at 90 kHz giving a noise
power bandwidth of 140 kHz.

F2
Frequency _

Instrumentation

Fa - Low end rolloff frequency (user selected)
Fl·50Hz
F2=500 Hz
F3 - 2.1 kHz

65-0032

Figure 2. RIAA Phono Playback
Equalication Curve
These equations are only approximations. Final tuning
is performed with the adjustable capacitors and
potentiometers. The following sequence can be used to
adjust for the RIM response after injecting a low level
signal into TP-1 (transformer disconnected).
1. At 100 Hz adjust C3A for an output level 6 dB lower
than the low frequency output.
2. At 1000 Hz adjust R8A for an output level 20 dB
lower than the low frequency output.
3. At 21 kHz adjust C4A for an output 40 dB less than
the low frequency output.

Low Impedance Microphone Preamp (Figure 3)
In this preamp the transformer converts the low
microphone impedance up to a value that is close to the
optimum source impedance required by the OP-27 for
best noise performance. The optimum source
impedance can be calculated as the ratio of erllN' which
for the OP-27 is approximately 7000U Fortunately the
noise performance does not degrade appreciably until
the source impedance is four or five times this optimum

3-506

The OP-27 is particularly adaptable to instrumentation
applications. When wired into a single op amp
difference amplifier configuration, the OP-27 exhibits
outstanding common mode rejection ratio. The spot
voltage noise is so low that it is dominated almost
entirely by the resistor Johnson noise. (Figures 4
through 7).
The three op amp instrumentation amplifier of Figure
8 avoids the low input impedance characteristics of
difference amplifiers at the expense of two more
operational amplifiers and a slight degradation in .
noise performance. The noise increases because two
amplifiers are contributing to the input voltage spectral
noise instead of one. Thus the noise contribution,
exclusive of resistor Johnson noise, increases by
slightly more than..J2. The spectral noise voltage
increases from approximately 3 nV/VHz to
approximately 4.9 nV/VHz, with the third amplifier
contributing about 10% of the noise. The gain of the
input amplifier is set at 25 and the second stage at 40
for an overall gain of 1000. R7 is trimmed to optimize
the common mode rejection ratio (CMRR) with
frequency. With balanced source resistors a CMRR
of 100 dB is achieved. With a 1 kQ source
impedance imbalance CMRR is degraded to 80 dB at
5 kHz due to the finHe (3 Gq input impedance.

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

OP-27
Rl
150K

1:10
Jensen Transformer
JE·115K·E

Miaophone
(1500)

R3

loon

I

Cl
l00011F

65-0033

Figure 3. Low Impedance Microphone Preamplnier

R2A
lOOK

100
TA = +25°C
Vs = ±15V

6

VOUT

VOUT= 1000 (~VIN)
=~VIN (R2AlRl)

~

:s.c

R2

+

As • Rl + R2

~

10

til

at 10 Hz

1
65-0034

~

~

100

i-"" i-'"

jerillioise OilY

1K

~

I

10K

RsO

Note:
Pin numbers shown are for 8-1ead packages.

Figure 4. Difference Amplnier

Figure 5. Difference Amplifier
Input Vottage Noise Density vs. Source Resistance

I
For More Information, call 1-800-722·7074.

Raytheon Semiconductor

3·507

OP-27
100K

140
120
VOUT

.... 100

......

ID

:2- 80
IX:
IX:

::E
0

AYCL -1000

60
40
20

65-0036

o
10'

10'

10

10'

10'

F(Hz)

Figure 7. Difference Amplifier
CMRR YS. Frequency

Figure 6. CMRR Test CircuH

R8
20K (0.1%)

>---4t-----lJ Your

R9
19.8K

R10

500

=

Trim R2 for A VCl 1000
Trim Rl0 for DC CMMR
Trim R7 for minimum VOUT at VCM

=20 Vpp, 10 kHz

Note: Pin numbers shown are for 8-lead packages.

Figure 8. Three Op Amp Instrumentation Amplnier

3-508

Raytheon Semiconductor

For More Information, caJI1-800-722-7074.

~

(J)

n
::r

~

~

iiJ

~
3

a0"

Vos
Trim

g.

(8)

o

;>

!L
~

Vos
Trim

I

-...
~

Input
(2)

3

g
&.
c

125

a:! a:;

"

~5.(

R2B
960

R7

. . rf
.Vs

~

R2A
18K

1# 029YQ30

E~

01
2X

...v.

~'~

~

_:F (ok

+Input

(3)

02 ....

800

800

*o1

%J

2X 101

R291
200

n

..... 4X

R25
20

r-

.v.

as

R23
.. 360

&

40K

~1;'026

20pF
OO2

M033

-ht17 Y04 %J

or

Q3"'-.t

':l

018v

ad

~~}
00

eoo

R10
780

I---

R11
580

09.......,
n 010

-

OUIJM
(6)

R26
20

Y::

~ t-

~ r--

t-K

•. C3
80pF
C2
120pF

039

ff

~

""

~~Q41

120

021

Q20

-""Q6

!l

"

II

......

R22

Y07
1"'0;

C1
150pF

r-..

028

~~1.

R8

R32
160

500

~

027

01!

R31

R30
200

eooK

·Vs

R9
3CK

R1A
18K

R28
700

R17
51<

~c:
5K

~~

~R20
50

~

r--

1-K04O

~~
100

-,
o

(4)

c.>

4
04f

4.51<

R1~i
125

R1C
125

5...

r-..

R2C

YZ2
~R10
J: y

ok

ffl

......

*R1E
250

:E

::J

0~00 o~

Z4

r~TZ3

ok

~

i8

R1G
4.51<

(1)

ii"
~

Vs
(7)

NoIe: Pin "umbels shown ate for 8-Iead packages.

~

~

~

co

_1 .. i*1

OP-27

3-510

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

OP-37
OP-37
Low Noise Operational Amplifier
Description

Features

The OP-37 is designed for instrumentation grade
signal conditioning where low noise (both spectral
density and burst). wide bandwidth. and high slew rate
are required along with low input offset voltage. low
input offset temperature coefficient and low input bias
currents. The OP-37 is a decompensated version of
the OP-27 and is AC stable in gain configurations
equal to five and higher.

•

Digital nulling techniques performed at wafer sort
make it feasible to guarantee temperature stable input
offset voltages as low as 251lV. Input bias current
cancellation techniques are used to obtain 10 nA input
bias currents.
The OP-37 design uniquely addresses the needs of
the instrumentation designer. Power supply rejection
and common mode rejection are both in excess of 120
dB. Input offset voltage can be externally trimmed
without affecting input offset voltage drift with
temperature or time. The drift performance is. in fact
so good that the system designer must be cautioned
that stray thermoelectric voltages generated by
dissimilar metal at the contacts to the input terminals
are enough to degrade its performance. For this
reason it is also important to keep both input terminals
at the sa,me relative temperature.

•
•
•
•
•
•
•
•
•
•

Very low noise
Spectral noise density - 3.0 nVlVRz
1/F noise corner frequency - 2.7 Hz
Very low Vas drift
0.21lV/Mo
0.21lVrC
High gain - 1800 V/mV
High output drive capability - ±12V into 6000
load
High slew rate -17 VI~
High gain bandwidth product - 63 MHz
Good CMRR -126 dB
low Vas -10 IlV
low noise - 0.08 IlVpop (0.1 Hz to 10Hz)
low input bias current - ±1 0 nA
Compensated for AC stability with AVCL ~ 5

The OP-37 is available in. SO-8 (small-outfine). TO-99
can. plastic mini-DIP and ceramic mini-DIP packages.
and can be ordered with Mil-Std-883 level B
processing.

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

I
3-511

OP-37
Ordering Information

Connection Information
B-Lead
Metal Can
(Top View)

TO-99

8-Lead Plastic
Dual In-Line SO-8
(Top View)

65-03206A

3-512

Operating
Temperature
Range

OP-37EN
OP-37FN
OP-37GN
OP-37EM
OP-37FM
OP-37GM

N
N
N
M
M
M

O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C

OP-37AD
OP-37AD/883
OP-37BD
OP-37BD/883
OP-37CD
OP-37CD/883
OP-37AT
Op·37AT/883
OP-37BT
OP·37BT/883
OP-37CT
OP-37CT/883

0
0
0
0
0
0
T
T
T
T
T
T

-SS'C to +12S'C
-SS'C to +12S'C
-SS'C to +12S'C
-SS'C to +12S'C
-SS'C to +12S'C
-SS'C to +12S'C
·SS'C to +12S'C
·SS'C to +12S'C
-SS'C to +12S'C
·SS'C to +12S'C
-SS'C to +12S'C
·SS'C to +12S'C

65-02666

66_

a·Lead
Dualln·Llne Package
(Top View)

Part Number Package

Pin
1
2
3
4
S
6
7
8

Function
Ves Trim
-Input
+Input
·VS
NC
Output
+VS
Ves Trim

Notes:
I883B suffix denotes Mi~Sld-883, Level B processing
N = 8-lead plastic DIP
D= Slead ceramic DIP
T = 8-lead metal can (T0-99)
M= 8-lead plastic sole

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

OP-37
Absolute Maximum Ratings
Supply Voltage .............................................:f!2.2V
Input Voltage 1 .................................................... :f!2.2V
Differential Input Voltage ............................... 0.7V
Internal Power Dissipation2........................ 658 mW
Output Short Circuit Duration .................. Indefinite
Storage Temperature
Range ........................................ -6S·C to +1S0'C
Operating Temperature Range
OP-27A18/C ............................... -SS·C to +12S'C
OP-27E1F/G ................................. -2S'C to +8S'C
OP-27E1F/G .................................... O'C to +70'C
Lead Soldering Temperature
(SO-8, 10 sec) ......................................... +260·C
(DIP, T0-99; 60 sec) ............................... +300·C
Notes:
1. For s4JPIy voltages less than :¥22V. the absolute maximum input
vohage is equal to the s4JPIy voltage.
2. Observe package thermal characteristics.

Thermal Characteristics
8-Lead
Small
Outline

8-Lead
Ceramic
DIP

8-Lead
TO-99
Metal Can

8-Lead
Plastic
DIP

Max. Junction Temp.

+12S'C

+17S'C

+17S'C

+12S'C

Max. PD TA <50'C

300mW

833mW

6S8mW

468mW

-

45'C/W

50'C/W

-

Therm. Res 8JC
Therm. Res. 8JA
For TA >SO'C Derate at

240'C/W

1S0'C/W

190'C/W

160'C/W

4.17 mWrC

8.33 mWrC

S.26mWrC

6.2SmWrC

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-513

OP-37
Electrical Characteristics

(VS =±15V and TA =+25'C unless otherwise noted)
Parameters

Test CondHlons

Op·37A1E
OP·37C/G
OP·37B/F
Min Typ Max Min Typ Max Min Typ Max

UnHs

Input Offset Voltage:>

10

25

20

60

30

100

J,1V

Long Term Input Offset
Voltage Stability1, 2

0.2

1.0

0.3

1.5

0.4

2.0

J,1VlMo

Input Offset Current

7.0

35

9.0

50

12

75

Input Bias Current

±10 ±40

±12 ±55

±15 ±80

nA
nA

0.1 Hz to 10 Hz

0.08 0.18

0.08 0.18

0.09 0.25

J,1Vp _p

Fn =10Hz

3.5

3.5

3.8

8.0

Input NOise Voltage

Fa=30 Hz

3.1

4.5

3.1

4.5

3.3

5.6

nV

Oensity2

Fo= 1000 Hz

3.0

3.8

3.0

3.8

3.2

4.5

"Hz

Input Noise Voltage2

5.5

5.5

Fo=10Hz

1.7

4.0

1.7

4.0

1.7

Input Noise Current

Fo =30Hz

1.0

2.3

1.0

2.3

1.0

Oensity2

Fa= 1000 Hz

0.4

0.6

0.4

0.6

0.4

Input Resistance
(Oiff. Mode)4

1.5

Input Resistance
(Com. Mode)

6.0

1.2

0.8

2.5

3.0

Input Voltage Range3

5.0

pA
0.6

4.0

"Hz
MO

2.0

GO

±11 ±12.3

±11 ±12.3

±11 ±12.3

V

Common Mode
Rejection Ratio

VCM =±11V

114

126

106

123

100

120

dB

Power Supply
Rejection Ratio

Vs = ±4V to ±18V

100

120

100

120

94

118

dB

RL~2kn, Vour=±1 V10001800

Large Signal Voltage Gain RL~ 1 kn, VOUT=±1 V8001500
VOUT= ±1V, Vs =±4 f,1250 700
Output Voltage Swing
Slew Rate 4

800 1500
250

200

500

±12 ±13.8

±12 ±13.8

Rl~6000,

±11

±12

±11

±12

±11

±12

RL~2IP-37A
Typ Max MIn Typ Max MIn Typ Max

UnHs

Input Offset Voltage 1

30

60

50

200

70

300

IlV

Average Inpu1 Offset
Voltage Drift2

0.2

0.6

0.3

1.3

0.4

1.8

Ilvrc

Input Offset Currem

15

50

22

85

30

135

nA

±20

±flO

:±28

195

±35 ±150

nA

Input Bias Current
Inpu1 Voltage Range

±10.3 ±11.5

±10.~

±11.5

±10.2 ±11.5

V

Common Mode
Rejection Ratio

VCM=±10V

108

122

100

119

94

116

dB

Power Supply
Rejection Ratio

Vs = ±4.5V to ±18V

96

116

94

114

86

110

dB

Large Signal Voltage Gain

RL~2

500 1000

300

800

VlmV

Ou1pu1 Voltage Swing

kn, VOUT =±10V 600 1200
±11.5 ±13.5
RL~kn

±11 ±13.2

±10.5 ±13

V

Electrical Characteristics
(Vs = ±15V,O'C s.. TA s.. +70'C for plastic packages unless otherwise noted)
Parameters

Test CondItions

MIn

JP-37E
Tvo Max

Min

( P-37F
JP-37G
Tvo Max Min Tvo Max

UnIts

Input Offset Voltage 1

20

50

40

140

55

220

Average Inpu1 Offset
Voltage Drift2

0.2

0.6

0.3

1.3

0.4

1.8

IlV
Ilvrc

20

135

nA

:±25 ±150

nA

Input Offset Currem

10

50

14

85

Input Bias Current

±14

±flO

±18

195

Input Voltage Range

±10.5 ±11.8

±10.5 11.8

±10.5 ±11.8

V

Common Mode
Rejection Ratio

VCM =±10V

110

124

102

121

96

118

dB

Power Supply
Rejection Ratio

Vs = ±4.5V to ±18V

97

118

96

116

90

114

dB

Large Signal Voltage Gain RL~2 kn, VOUT =±10V 750 1500
Ou1pu1 Voltage Swing

RL~kn

±11.7 ±13.6

700 1300

450 1000

VlmV

±11.4 13.5

±11 ±13.3

V

I

Notes:
1. Input Offset Voftage measurements are pertormed by automated test equipment approximately 0.5 seconds after application of power.
2. TcVos pertormance is guaranteed untrimmed or when trimmed with RmlM

For More Information. call 1-800-722-7074.

=8.0 kn to 20 kn.

Raytheon Semiconductor

3-515

OP-37
Typical Performance Characteristics
5100

0.1

JIF

lOOK

F

2K

6

22jIF

Scope
xl
RIN-1MO

110K

-

__

No~:

1. Peak-ID-peak noise measured in a 10 second interval
2. The device under test should be warmed up for 3 minutes and shielded from air current
3. Voltage gain =SO.OOO.
4. All capacitor values are lor non-poIariZed capacitors only.
S. Pin numbers shown sare for &-lead package.

0.1 Hz to 10Hz Noise Test Circuit
0.1 Hz to 10Hz Noise Test Circuit
Gain vs. Frequency
100

.-

90

70

.l

60

~

100

iii

Test Time of 10 Sec Further
SO - UmilS Low Frequency (<0.1 Hz)
Gain
40

30

0.1

1.0

~

80

J

60

"-.....

!

0
1

100

10

'"
10

10 2

10'

10 7

10'

4.0

-40

TA - +125"C

40 H-ttltllll-+H Ay

-120

'"
"

T4oM=

.~ 70°C

::::::::::::::!:IIAy,=~:~::~s_-t-fL-lu.·HJ.llJI_2oo
0

10K

lOOK

1M

10M

-----

C

-80

~

~eo

.§.

Ji

TA -+25"C -

3.0

--V

-160

100M

!

.......

p
.....

~

t::::=-

1.0

5

15

~

~ I..-

~~

, I---""'"TA _ -S5"C

2.0

F(Hz)

3-516

"'"

0

60

0

10'

Supply Current vs. Total Supply Voltage

80

20

10 5

S.O

100

C

10'

I

r--...

F(Hz)

Gain. Phase Shift vs. Frequency

..

I

TA _+2S"CVs - tlSV
RL~2kO
-

20

F(Hz)

iii'

I

40

IIIIIIII IIIIIIII III

0.01

,"'" r"...

120

1\1\

~~

80

iii

Open Loop Gain vs. Frequency
140

25

35

i

45

+V. to .V. (V)

Raytheon Semiconductor

For More Information. calI1-80D-722-7074.

OP-37
Typical Performance Characteristics (Continued)
Short Circuit Current vs. Time

Maximum Output Swing vs. Load Resistance
60

18
16
14

+S~

12
~

8

>

...-1"..

10
,/

8
6

'I'--.,

~Voor

/

/
if

4

,

50

:;;;---

............

2

r--

20

I I II

-2

10

10

0.1

--

r-r--

lse (·)

Vs -115V
T,,-+25°C

o

Vs-t15V
T,,- +25°C

l se (+)

o

2

5

4

3

Time (Min)

Open Loop Gain vs. Supply Voltage
2.5

I
T A-+25°C

2.0
I,

RL-2~

~

1.5

J

1.0

~....

/

/

Maximum Undistorted Output vs. Frequency
28

--

~

/ RL -lkQ

'V

0.5

II

24

~

16

J

12

T~-!2~}d

\

20

\

Vs-115V

~

8

'-

4

o
o

±5

±10

±15

±2O

o

±25

'r--- ...

104

:tVs (V)

F{Hz)

Input Noise Voltage Density VS. Frequency

Common Mode Input Range vs. Supply Voltage
16r------r------r------r-----,

10

I

12
8

€

J

4

t¥:>

0

s.c

-4

III

-8
f!
0

-12

~

-16
0

!5

!10

!15

!20

5

,

r--.

"

"'.r
/

LIfF

-

Comer = 2.7 Hz

I I 1111111

±Vs{V)

For More Information, call 1-800·722·7074.

TA= +25°C
Vs = 115V

10

100

1000

F (Hz)

Raytheon Semiconductor

3·517

OP-37
Typical Performance Characteristics (Continued)
Op Amp Comparison
Input Noise Voltage Density vs. Frequency
100

741

.:.c

""'"

I .... ".

L:""oo.

GI

J

l/FCorner

~i41~11

Hi

llF I orner2.7~
Instrumentation Range 10

11

"

~
i

low Noise
Audio
9PAmp

10

'"

•

~
...

I ~~'born~
ill III

~ 1'000

~:>

Input Noise Current Density vs. Frequency
10.0

1M X 100

f--

oq Audio Range 1020 kHz

10

100

eno

•

In _ [eno'- (130 "V)'I'-

.3-

-I-L-t-I+
1 W

•

500K

...

I,
1.0

llF Corner 140 Hz

10

1000

I I

I I " 1111

0.1

10K

lK

100

F(Hz)

F(Hz)

Input Noise Voltage Density vs. Total Supply Voltage

Input Noise Voltage Density vs. Temperature
5

5

I

I

-

4

Va: t15V

=

TA +25°C

4

~--+---~--~--~---+

___~~~

all0 Hz

-

at 1.0 kHz
2r---+---;----r---r---+--~--_;

2

1

o

±15

±10

±5

±20

1~~--~~--~~--~--!
-50
-25
o +25 +50 +75 +100 +125

±Vs(V)
Input Offset Voltage Drift of
Representative Units
60

40

.,.......

20

:>

0

J

-20

a

fo-'"

--

po<"""

k V
fo-"'"

.....................

-40 --60

- ...-

-

Trimming with 10K
Pot does not
ihangj TC, os

-80

-75 -SO -25

o

I

V

......

Input Offset Voltage vs. Time
(Warm-up Drift)

,.

OP-37C
OP-37B
OP-37A
~
OP-37B
OP-37A

V

10

TA- +25"C -/-----+-----t-----1

Vs- 115V

OP-37CIG

~

--..

,- --

OP-37BIF
OP-37A
OP-37B

........ OP-37C

OP-37AIE

!

+25 +50 +75 +100 +125 +150 +175

2

3

4

5

Time (Min)

3-518

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

OP-37
Typical Performance Characteristics (Continued)

Input Offset Current vs. Temperature

Input Bias Current vs. Temperature
so

50

Vs=t15V
40

<"

20

10

<"

~

OP-37B

.J
J

-so

-25

0

"~P-37C

20

.~ ~ ~P-37B

10

OP-37A
-75

30

S.

I""
~ 1::I"""
~

o

1

+25 +SO +75 +100 +125+1SO

OP-37A

-75

J

TA- +25·C

120 I -

"'"

iii'

100

a:
a:
U)

SO

~
0..

1.0

0.4
0.1

~

-Vs

'~

t-

+Vs ......

70 t - -

!

Ii
1.0

100

10

........

50

iii'

a:
a:
~

40

1

10

10'

10'

I"r--.

10'

10'

~

10' 10'

TA=+25·C
Vet/. = t10V
,,~

"
lOOK

1M

i

10M

o

F (Hz)

For More Information, call 1-800-722-7074.

lao. ..A. .AJ

oJ.,,"

"
10K

10'

0.1 Hz to 10Hz Peak-to-Peak Noise vs. Time

60

40
lK

~

'~

II~~=UJII

100

SO

~
'~

F (Hz)

CMRR vs. Frequency
140

~

~

60

Rdk)

120

+75 +100 +125

160

1.2

0.6

+50

PSRR vs. Frequency

1.4

O.S

+25

140

L

1.6

o

-25

-50

Open Loop Gain vs. Load Resistance

1.S

!

~t-

o

2.4
2.2 IT ~=I :~~~16
2.0 :---- Vs = t15V

>~

I

" OP!37C
30

S.

..!P

I

Vs=:II5V _

40

15

30

"" :\.0 r,."N'

45

Tlma (Sac)

Raytheon Semiconductor

3-519

I

OP-37
Typical Performance Characteristics (Continued)
Slew Rate vs_ Supply Vonage

Slew Rate vs. Load Resistance

20

19
L

15

Iii

~
a::

#

10

~~
:;......-

~

18

Fall

Js~I~~WI

-

TA-+25OC
Av-~

Vo -2OVp-p

V '"

TA - +25 OC
+10

III

AVCL -

5

o

:t3

±6

:1:9

:t12

±15

±18

!

±21

16

15
0.1

100

10

1.0

+2OV

>-.........--o+Vs

>---="0

VOUT

-Vs
-2OV

65-0351

Note: Pin numbers shown are for a-lead packages.

Bum-In Circun

3-520

Input Offset Trimming Circuit

Raytheon Semiconductor

For More Informatkln, call 1-800-722-7074.

OP·37
Typical Applications
Low Impedance Microphone Preamp
(Figure 1)
In this preamp. the transformer converts the low
microphone impedance up to a value that is close to
the optimum source impedance required by the OP37 for best noise performance. The optimum source
impedance can be calculated as the ratio of erilN
which for the OP-37 is approximately 7000n.
Fortunately. the noise performance does not degrade
appreciably until the source impedance is four or five
times this optimum value. The source impedance at
the output of this transformer of 15 kn still provides
near optimum noise performance. (A high quality
audio transformer with a step-up ratio of 6.7 to one is
not available.) C1 rolls off the high frequency
response at 90 kHz giving a noise power bandwidth of
140 kHz.

Instrumentation
The OP-37 is particularly adaptable to instrumentation
applications. When wired into a single op amp
difference amplifier configuration. the OP-37 exhibits

outstanding common mode rejection ratio. The spot
voltage noise is so low that is dominated almost
entirely by the resistor Johnson noise (Figures 2
through 5).
The three op amp instrumentation amplifier of Figure
5 OP-370P-37 avoids the input impedance
characteristics of difference amplifiers at the expense
of two more operational amplifiers and a slight
degradation in noise performance. The noise
increases because two amplifiers are contributing to
the input voltage spectral noise instead of one. Thus.
the noise contribution. exclusive of resistor Johnson
noise. increases by slightly more than --12. The
spectral noise voltage increases from approximately 3
nV/VHz to approximately 4.9 nV/VHz. with the third
amplifier contributing about 10% of the noise. The
gain of the input amplifier is set at 25 and the second
stage at 40 for an overall gain of 1000. R7 is trimmed
to optimize the common mode rejection ratio (CMRR)
with frequency. With balanced source resistors. a
CMRR of 100 dB is achieved. With a 1 kn source
impedance imbalance CMRR is degraded to 80 dB at
5 kHz due to the finite (3 G~ input impedance.

~Q=T{)II
Microphone
(1500)

>-......- - + - - - - ( )

VOUT

1:10
Jensen Transformer
JE·115K·E

I

65-0321

Figure 1. Low Impedance Microphone Preamplifier

For More Information, call 1-800-722·7074.

Raytheon Semiconductor

3·521

OP-37
R2A

lOOK

100
TA. +25°0
VS. %15V

6V 1N

~>

Voor

{

.s.
i

±t>-o
R2

+

R• • R1 +R2

10

i-'"

at 10 Hz

~ ""~iaiiii,lKjise 'jly I

1
100

!

10K

RS (0)

Figure 2. Difference Amplifier
lOOK

Figure 3. Difference Amplifier
Input Noise Vottage Density vs. Source Resistance

Note: Pin number shown are for 8-lead packages.

Figure 4. CMRR Test CircuH
R5

R8

5000(0.1%)

2OK(0.1%)

VOUT

R6
5000(0.1%)

R9
19.8K

Rl0

soon
Trim R2 for AvcL .1000
Trim RIO for dc eMMA
Trim R7for minimum VOUT at VCM - 20 Vp.p. 10 kHz

65-0355

Figure 5. Three Op Amp Instrumentation Amplifier

3-522

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

g'
~

(8)

~
3

'I"

CD

!!!.

is·
:;:>
0

-

RIG
4.5K Z4

Vos
Trim

!lb

1)

~
0

Z

~
.:...

Z

~

Z

'So

:3'
CD

Z

0

fC
2,

()

0

+Inpu

F~

Rl~
125

01
2X

,....

.~

R29

::J

_043

-vs

l

v;;!

I~K

'L

~!

~

DiD~

~

...

700

~ 17

12 pF

'"'1

03"

I~

Y04~
~'
024

RIO
7S0

'--

Rll
580

R25
20

08
R14

L.....
~Q~

1....1

=

200pF
-.II
II

R26
20

L035

~t-

~r--

S

R17

~

(6)

r--o

Quip ,ut

~Q32

Q9

I~

p39

C4

r-~33

~IC2

0

1-"041

800

II

Sl

3

R21
1.SK

Ff
-i

40l<

~Q26
~25htJ 4X

cc
~

R"~
r-.

c

m

A

800

~

a
n'
iii'

!AI 029.JAI030
t-...
~

021

"'-I

-0
(7)

R31 ~R32
500 ; 160

~S

.....07

200 ...I SOpF

C

RS

.~~

b~""
2X

.-

R9
30K

Cl, 150 pF

Q~

027

o~ ~s

tR2A
ISK

e~

Q.

0l!

R2B
960

R2B
960

:=t
(2)

r.., ~.

~Z5.!'"

RIC
~ 125

::J

~

R30
200

R7
t600K

042

::r:=
.y " " "if

RID
125

-Input

r-.,

~,Z2

Z

:a
II)

+vs

Z3

RIE
250

0

:::T

Trim

~ O~ 0;!l

R2C:
4.5K

y~

RIF
500

en
(')

t;;t
:

036
034
2X

5K

R19
2K

R20
50

t-

~Q40

rJ:;:Q37
2X

lR2100i

01SJ
019

~ 2X

(4)

~,~

300

65.Q0335

600

S
Note: Pin numbers shown are for 8-lead packages.

o~
I

Co>

~

(.H

....:a

_llMii

OP-37

3-524

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

OP-77
OP-77
Precision Operational Amplifier
Description

Features

Designed to upgrade OP-07 and other similar
precision op amps, the OP-77 offers ultra high
performance in applications requiring high gain,
superior gain-linearity, and extremely low TCVos.
The OP-77's outstanding gain-linearity, which
eliminates incorrectable system nonlinearities
common in previous precision op amps, is achieved
by an exceptional open-loop gain of more than 10
million maintained over ±1 OV output range. The
excellent TCVOS of 0.1 J!vrc, plus an extremely low
power consumption of 35 mW (which reduces warmup drift) significantly increases system accuracy over
temperature. These characteristics, along with low
VOS,low lOS, high CMRR, high PSRR, and low input
noise levels, combine to raise the performance level
of many high-resolution instrumentation and data
conversion systems.

•
•
•
•
•
•
•
•
•
•
•

Ultra high gain -12000 V/mV
Outstanding gain linearity
Ultra low VOS drift - 0.1 J!VI'C
Low Vos -10 J!V max
Low noise-0.3 J!Vp_p (0.1 Hz to 10 Hz)
Low power consumption - 35 mW
Low input offset current - 0.3 nA
High CMRR - 140 dB min
High PSRR -120 dB min
ReplacesOP-07,108,741 types
Wide range of package types

Advanced circuit design and wafer processing are
Raytheon Semiconductor's added advantages in
quality and reliability. A patented, proprietary VOS
trimming method after packaging significantly
enhances yield and availability of top grade (AlE)
devices.

I
For More Infonnation, call 1-800-722-7074.

Raytheon Semiconductor

3-525

OP-77
Ordering Information

Connection Information

Package

Operating
Temperature
Range

OP-77EN
OP-77FN
OP-77GN
OP-77EM
OP-77FM
OP-77GM

N
N
N
M
M
M

O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
OOC to +700C .
O'Cto +70'C
O'Cto+70'C

OP-77AT
OP-77AT/8838
OP-77BT
OP-77BT/883B
OP-77AD
OP-77AD/883B
OP-77BD
OP-77BD/883B

T
T
T
T
D
D
D
D

-55'C to +125'C
-55'C to +125'C
-SS'C to +125'C
-55'C to +125'C
-55'C to +125'C
-55'C to +125'C
-55'C to +125'C
-55'C to +125'C

Part Number

8-Lead
Dualln-Une Package

8-Lead
T0-99 Metal Can

(Top View)

(Top View)

116-03206

8-Lead Plastic
Dual In-Line SO-8

(Top View)

3-526

Raytheon Semiconductor

Pin

Function

1
2

Vos Trim
-Input
+Input
-VS
NC
Output
+VS
Vos Trim

3
4

5
6
65-02888

Notes:
I883B suffix denotes Mil-8td-883, Level B processing
N = 8-1ead plastic DIP
D =8 lead ceramic DIP
T =8-1ead metal can (T0-99)
M =8-lead plastic sale

86«I206A

7
8

For More Information, caJI1-800-722-7074.

OP-77
Absolute Maximum Ratings
Supply Voltage ............................................. f!2.2V
Input Voltage 1 ..................•....•.........................•.. f!2.2V
Differential Input Voltage ................................ 30V
Internal Power Dissipation 2 ...••......•............ 500 mW
Output Short Circuit Duration .................. Indefinite
Storage Temperature
Range ................................... -65'C to +150'C
Operating Temperature Range
OP77A,B .............................. -55·C to +125'C
OP77E,F,G ................................ O·C to +70'C
Lead Soldering Temperature
T0-99, DIP, (60 sec) .......................... +300·C
SO-8 (10 sec) ..................................... +260·C
NOles:
1. For supply vo~ages less than :l22V, lhe absolute maximum
input voltage is equal 10 lhe supply vohage.
2. Observe package thermal characteristics.

Thermal Characteristics
8-Lead
Ceramic DIP

8-Lead
TO-99
Metal Can

8-Lead
Small
Outline

8-Lead
Plastic DIP

Max. Junction Temp.

+175'C

+175'C

+125'C

+125'C

Max. PD TA <50'C

833mW

658mW

300mW

468mW

I nerm. Res 9JC

45T,/W

50-CIW

-

-

Therm. Res. 9JA
For TA >50'C Derate at

150'C/W

190'C/W

240'C/W

160'C/W

8.33mWrC

5.26mWrC

4.17 mwrc

6.25mWrC

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

I
3-527

OP-77
Electrical Characteristics
(Vs =±15V and TA =+25'C unless otherwise noted)
Parameters

Test CondHlons

Min

Input OffsetVoltage3
Long Term Vos Stability1
Input Offset Current
Input Bias Current
Input Noise Voltage!)
Input Noise Voltage DensityS
Input Noise CurrentS

±SO

JJ.V
JJ.V/Mo
nA

±1.5

:f20
0.2
±D.3

:f2.8

±1.2
0.35
10.3

:f2.8
0.65
18

10

13

10

13

nV

9.6
14

9.6
14

FO=100Hz

0.32
0.14

11
35
0.8
0.23

\lli

0.32
0.14

11
30
0.8
0.23

Fo" 1000 Hz

0.12

0.17

0.12

0.17

26

RL:2:2 k.O,
RL:2: 1 k.O,
RL:2:2 k.O,
AYCL = +1.0
VO UT " O.loUT " 0
Vs = ±15V. RL = 00
Vs = f!3V. RL = 00

Offset Adjustment Range

UnHs

Fo·100Hz
Fo = 1000 Hz
0.1 Hz to 10 Hz

Output Voltage Swing

Power Consumption

Max

0.35
10.3

VCM=±11V
Vs = ±3V to ±BV
RL ~2 k.O,
VOUT= ±10V
RL:2: 10 k.O,

Open Loop Output Resistance

:f25

op·nB
Typ

0.1 Hz to 10 Hz
FO ·10Hz

Common Mode Rejection Ratio
Power Supply Rejection Ratio
large Signal Voltage Gain

Slew Rate2

±10

Min

:f2.0
0.6
18

Input Resistance (Ditt. Mode)':
Input Resistance (Com. Mode)
Input Voltage Range4

Closed loop Bandwidthi!

Max

0.2
±D.3
±1.2

FO=10Hz
Input Noise Current DensityS

op·nA
Typ

RTRIM=20kn

nA
JJ.Vp_p

PAo-o
pA
~

18.5

±13
120

45
200
±14
140

±13
116

45
200
±14
140

110
5000

120
12000

110
2000

120
8000

±13
±12.5
±12
0.1

±13.5
±13
±12.5

±13
±12.5
±12

±13.5
±13
±12.5

V

0.2

0.1

0.2

V/(.IS

0.4

0.6

0.4

0.6

MHz

60

35
2.0
±3.5

MO

an
V
dB
dB
VlmV

n

60
60
4.5

35
2.0
:ta.5

60
4.5

mW
mV

Notes:
1. Long Term Input Offset Voltage Stability refers to the average trend Ine of Vos vs. Time over extended periods after the first 30 days of operation.
Excluding the inftial hour of operation, changes in Vos during the first 30 operating days are typically 2.5I1V.
2. Guaranteed by design.
3. Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application It power. The Op-nA
grade in T, 0, and L packages are tested fully warmed up.
4. The input protection diodes do not anow the device to be removed or inserted into the circuit wkhout first removing power.
5. Sample tested.

3-528

Raytheon Semiconductor

For More Information, caJI1-800--722-7074.

OP·77
Electrical Characteristics
(Vs

=±15V and TA =+25'C unless otherwise noted)

Parameters
Input Offset Voltage 3
Long Term Input
Offset VoHaoe Stabilitv 1
Input Offset Current
Input Bias Current
Input Noise Voltage5
Input Noise VoHage
Density5
Input Noise CurrentS
Input Noise Current
Oensity5

Test CondHlons

Min

0.1 Hz to 10 Hz
Fn = 10 Hz
Fn =100 Hz
Fn = 1000 Hz
0.1 Hz to 10 Hz
Fo=10Hz
Fn =100Hz
Fn =1000 Hz

lrput Resi~~nce
Oiff. Mode

26

put Resist3~nce
lrCom.
Mode
Inout Voltaae Ranae4
Common Mode
Rejection Ratio
Power Su~1y
Reiection alio
Large Signal Voltage Gain

Dp·77E
)P·77F
Op·77G
Tvo Max Min Tvo Max Min Tvo Max
±10 225
220 ±£i0
±SO ±100
0.3
0.4
0.4
±G.3
±1.2
0.35
10.3
10
9.6
14
0.32
0.14
0.12
45

±1.5
22.0
0.6
18
13
11
30
0.8
0.23
0.17

±G.3
±1.2
0.38
10.5
10.2
9.8
15
0.35
0.15
0.13
18.5 45

200

22.8
±2.8
0.65
20
13.5
11.5
35
0.9
0.27
0.18

±G.3
±1.2
0.38
10.5
10.2
9.8
15
0.35
0.15
0.13
18.5 45

200

±2.8
22.8
0.65
20
13.5
11.5
35
0.9
0.27
0.18

UnHs
uV
~VlMo

nA
nA
UVn.n

JJY....
..,1Hz
~~-D.

M...
-/Hz
Mil

200

Gil

VCM =±13V

+13
120

±14
140

±13
116

+14
140

±13
116

±14
140

V
dB

Vs = :l:3Vto ±18V

110

123

110

123

110

123

dB

RL~2kD.

5000 12000

2000 6000

2000 6000

VlmV

±13
±12.5
±12
0.1
0.4

±13
12.5
±12
0.1
0.4

±13 13.5
~12.5 ±13
±12 12.5

V

VOUT =±10V
RL~10k.Q

Output Voltage Swing

RL~2kn
RL~1kn

Slew Rate2
Closed-Loop Bandwidth2
Open Loop Output
Resistance
Power Consumption
Offset Adjustment Range

RI

~2kn

AVCL =+1.0
VoUT =O,louT=O
Vs =±15V, RL = co
Vs =:I:3V, ~ = co
RTRIM=20kn

±13.5
±13
±12.5
0.2
0.6
60
35
2.0
:1:3.5

±13.5
±13
±12.5
0.2
0.6
60

60
4.5

35
2.0
:1:3.5

0.1
0.4

60
4.5

0.2
0.6
60
35
2.0
:1:3.5

V/uS
MHz
il
60
4.5

I

mW
mV

Notes:
1. Long Term Input Offset Voltage Stability refers 10 the average trend line of Vos vs. Time over extended periods after the first 30 days of
operation. Excluding the initial hour of operation. changes in Vos during the first 30 operating days are typically 2.5 !lV.
2. Guaranteed by design.
3. Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
The op-nE grade on T, 0, and L packages are tested fully warmed up.
4. The input protection diodes do not allow the device 10 be removed or inserted into the circuit without first removing power.
5. Sample tested.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-529

OP-77
Electrical Characteristics
(VS = ±15V. -55'C S; TA S; +125'C unless otherwise noted)
OP-77A
Typ

op·na
Typ

Max

Units

±45
0.2

±120

0.1

:!:SO
0.3

0.6

uV
pVfC

Inout Offset Current
Average Input Offset
Current Drift2

±D.B
:is.0

:1:2.2
:1:25

±1.0
:is.0

±4.5
:iS0

_nA
pAf'C

Input Bias Current

:1:2.4

±4.0

:1:2.4

±6.0

nA

Average Input Bias
Current Drift2
Inout Voltaoe Ranoe
Common Mode Rejection Ratio

±B.O

:125

±15

±35

pAre

Parameters

Test Conditions

Min

Input Offset Voltage

:1:25

Average Input Offset
Voltaoe Driftl

Max

Min

VCM=±10V
Vs = ±3V to ±8V
RL ~2 ill,
Vour =±10V

±13
120

±13.5
140

±13
110

±13.5
140

110
2000

120
6000

106
1000

120
4000

dB
dB
VlmV

Maximum Output Voltage
Swing

RL~2ill,

±12

±13

±12

±13

V

Power Consumption

RL =

Power Supply Rejection Ratio
Large Signal Voltage Gain

40

00

75

V

75

40

mW

Electrical Characteristics
(Vs =±15V. O°C S;TA S; +70°C unless otherwise noted)

:>p-nl
Min _TVD

TI!~

Mn _Min

op·nl
TVD

OE'-nl
Max

Min

Tvn

MAY

IInltll

IlV
JJ,VfC

Input Offset Voltage

±10

±45

:120 ±100

±80 ±100

Average Input Offset
Voltage Drift

0.1

0.3

0.2

0.3

0.6

1.2

Input Offset Current

±D.5 :1:2.2

±D.5 ±4.5

±D.5 ±4.5

nA

Average Input Offset
Current Drift2

±1.5 ±40

±1.5 ±85

±1.5 ±85

pAre

Input Bias Current

:12.4 ±4.0

:1:2.4 :!:S.O

:1:2.4 :!:S.O

nA

±15

±15

Average Input Bias
Current Drift2

±8

Input Voltage Range

±40

±60

±60

pAre

±13 ±13.5

±13 ±13.5

±13 ±13.5

V

Common Mode Rejection
Ratio

VCM =±13V

120

140

110

140

110

140

dB

Power Supply Rejection
Ratio

Vs = ±3V to ±lBV

110

120

106

120

106

120

dB

Large Signal Voltage Gain

RL~2ill,

2000 6000

1000 4000

1000 4000

±12

±12

±12

VlmV

VoUT =±10V
Output Voltage Swing

RI~2ka

Power Consumption

RL =

Notes:

3-530

1.
2.

±13
40

00

75

±13
40

75

V

±13
40

75

mW

100% tested for Grade A and T packages.
Sample tested.

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

OP-77
Typical Performance Characteristics

op-n Improved Open-Loop Gain Linearity
Input vs. Output Voltage
I

..3I'V

I

1/

----

.10V _ _ _

f-- TA

f-

Typical Precision Op Amp Gain Linearity
Import vs. Output Voltage

- +25°0
R L -2kll
Vs _1:15V

-

r--

-3I'V

V
+10V

·10V

"

+15Jl.V

_\.

/~
~+10V

\/

--'i\

-,
I

-151'V

I

Vour
Ri

5OK"

R2
1000·

R3
SOK"

-

VOUT ~ 1000 Vas

• Resistors must have low
thermoelectric potential

-iSV

65-03821

Test Circuit for Input Offset Voltage and
Its Drift with Temperature

85-3822

Input Offset Voltage Adjustment

100K

I
Notes:
1. Peak-to-Peak noise measured in a iO-second interval.
2. The device under test should be warmed up lor 3 minutes and shielded Irom air currents.
3. Vohage Gain = 50,000
4. AD capacitor values are lor non-polarized capac~ors only.
S. Pin numbers shown are lor 8-lead packages.

6!Hl3823B

0.1 Hz to 10Hz Noise Test Circuit

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-531

OP-77
Typical Applications

lK

+15V

CI
30pF

O.II1F

~

01
IN4148

lK
+15V

O.lI1F

~

6 '::'

>=:""'--<1--0 VOUT

6

OOV

Full Scale of IV
1.1AN

AVCl = 1.6
65-4018

Positive Current Source
RI

This simple bootstrapped voltage reference provides a
precise 1OV virtually independent of changes in power
supply voltage, ambient temperature and output
loading. Correct zener operating current of exactly 2
mA is maintained by Rl, a selected 5 ppml'C resistor,
connected to the regulated output. Accuracy is
primarily determined by three factors: the 5 ppml'C
temperature coefficient of 01, 1 ppmrC ratio tracking
of R2 and R3, and operational amplifier Vos errors.
Vos errors, amplified by 1.6 (Avell, appear at the
output and can be significant with most monolithic
amplifiers. For example: an ordinary amplifier with
TCVos of 511VrC contributes 0.8 ppmrC of output
error while the OP-77, with TCVes of 0.3 Jl.VrC,
contributes but 0.05 ppmfC of output error, thus
effectively eliminating TCVes as an error consideration.

lOUT

-Vs

VIN 

~

8",[f1.

OP-77

3-534

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC3403A
RC3403A
Ground Sensing Quad Operational Amplifier
Description

Features

The RC3403A is a high performance ground sensing
quad operational amplifier featuring improved dc
specifications equal to or better than the standard 741
type general purpose op amp. The ground sensing
differential input stage of this op amp provides
increased slew rate compared to 741 types.

•
•
•
•
•
•
•
•

Class AS output stage - no crossover distortion
Output voltage swings to ground in single supply
operation
High slew rate - 1.2 V/jJS
Single or split supply operation
Wide supply operation - +2.5V to +36V or
±1.25V to ±18V
Pin compatible with LM324 and MC3403
Low power consumption - 0.8 mA/amplifier
Common mode range includes ground

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-535

RC3403A
Connection Information

Ordering Information
Pan Number Package

14-Lead Dual In-Line Package

(Top View)
RC3403AN

Operating
Temperature
Range

N

Notes:
N. 14-lead plastic DIP.

Absolute Maximum Ratings (1)
Pin

Function

1

Output (A)
-Input (A)
+Input (A)

2
3

4
5
6
7

8
9
10
11
12
13

Supply Voltage ......................... +36V or ±18V
Input Voltage •.•...•.•.•....•••.•...•.•.•••. -Q.3 to +36V
Differential Input Voltage .......................... 36V
Storage Temperature
Range ................................ -65OC to +1500C
Operating Temperature Range .. O°C to +70°C
Lead Soldering Temperature
(60 sec) •....•..........•......•...................... +300°C

+Vs

+Input (8)
-Input (8)
Output (8)
Output (C)
-Input (C)
+Input (C)
-Vs (Gnd)
+Input (0)
-Input (0)

Notes:
1. •Absolute maximum ratings' are those beyond which the
safety of the device cannot be guaranteed. They are not
meant to imply that the device should be operated at these
limits. If the device is subjected to the limits in the absolute
maximum ratings for extended periods, its reliability may be
impaired. The tables of Electrical Characteristics provide
conditions for actual device operation.

Thermal Characteristics
14-Leaa
Plastic DIP

Max. Junction Temp.
468mW
Therm. Res 9J C
Therm. Res. 9J A
For TA >50°C Derate at

3-536

6.25 mWFC

Raytheon Semiconductor

For More Infonnation, call 1-800-722-7074.

RC3403A
Low Voltage Electrical Characteristics
(+vs =+5V, -vs =GND, and TA =+25° C)
RC3403A

Parameters

Test Conditions

Input Offset VoHage
Input Bias Current
Input Offset Current
Supply Current
Large Signal Voltage Gain
Output VoHage Swing 1

RL =00 All Amplifiers
RL ~-OVOUT

>-.....-0

VOUT

(0)

vOUT -- ~
= +Vs
R2+ R1
2

R3
1M

VOUT

65-1l646

Ground Referencing a
Differential Input Signal

=~
2

(As shown)

65-0645

Voltage Reference

O.05J.1F

>7....._ 0 Output 1

10K

IV\

L -_ _ _ _ _ _ _ _ _

51K

~~

Output2

10K
Note: Wide control voltage ranges:
OV :S Vc :S 2 (+Vs -1.5V)

65-0647

VoHage Controlled Oscillator

3-542

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC3403A
Typical Applications (Continued)

f_

Rl

R2

Rl
100K

AV=I+ R2

1M

C IN

Av= 11 (As shown)

VIN ~

Co

~rVOUT
R

R2

-

lOOK

+Vs n--I\I'V\r-t
+

L

Cl

1

10

Av = RF

-VS

Rl

R5

Av = 10 (As shown)

lOOK
':'

':'

f\/\

J.LF

f\J\
V

T
2Vp.p
l

65-0649

T

0 _...L--+-+-'-_ 2Vp.p

V

.l
65-0648

AC Coupled Non-Inverting Amplifier

AC Coupled Inverting Amplifier

Design Example:

Fo ACenter Frequency
BW A Bandwidth
R inkG
C in I'F

~ J-.IVIV\,--4...=-1
Cl

C2

Given: Q = 5, Fo = 1 kHz
LaIRl =R2=10kG
Then R3 =9 (5)2 -10
R3= 215 kG

~<10

Rl

Q=

lK

BW
Cl =C2=

Q

C= !.= 1.6nF
3

"3

} Use scaling faclors in these expressions.

65-0650

If source impedance is high or varies, filter may be preceeded
with vollaQe follower buffer to stabilize filter parameters.

Multiple Feedback Bandpass Filter

R2

V~OOtOUT:~

>-----0
VIN 0-------"-1

VINI..

Rl ~1 R2

'laNH _

Rl
Rl +R2

I

VOL

I

VINI.

: VINH

H. RI ~IR2

I

(VOL - V REF) + VREF
(VOW VREF) + VREF
(VOW VOL)

I

VREF
65-0653

Comparator With Hysteresis

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-543

RC3403A
Typical Applications (Continued)
SOK

.-----\iVIr--.....-o Vour

A6

VI

10K

V.
R3

o-_-A.J......-+=-!

Vour= (; (1 + &+ b),(V2 - VI)

R4

A2

A6

Fi5=ii7

AS

lor bast CMRR

C

Al_R4

V2

A7

R

R2_R5
Gain-

!!!
R2

(1

+~)
R3

F. - 2Kk: lor Fa _1kHz
.C(1+&+b)

R_16kQ

C_o.o!""

65-0652

Wein Bridge Oscillator

High Impedance Differential Amplifier

R
0- .§.

R

Where~w

C

TBP • Center Frequency Gain

TN - Banttlass Notch Gain

Cl

Y'N ~f--""""''lNIr-~

F __
,_

o 2ltRC
R1- OR

AI

R2 _

R2

TaP

C1

(--0

.!!!..

Notch Output

R3-T NR2
C1 -ICC

Exampte:

Fo -1000 Hz
BW-100 Hz
TaP -1
TN - l

R-160kO
Rl-1.6MO
R2-1_6MO
R3-1.6MO
C -0.001 j1F

Bi-Quad Filter

3-544

Raytheon Semiconductor

For More Information, calI1-80Q-722-7074_

RC3403A
Schematic Diagram (1/4 Shown)
+Vs
(4)o-~------------~--------------~~----~----~--~--------~---,

+--4__.---+<>

Output
(t,7,8,14)

-VS orGND

(11) o---'--------'-----------~-------4--+-_lr___+------+------4----i_--+-----'
65-0635

I
For More Information, call 1-800-722-7074_

Raytheon Semiconductor

3-545

RC3403A

3·546

Raytheon Semiconductor

For Morllinformation, call 1-800·722-7074.

RC4136
RC4136
General Performance Quad 741 Operational Amplifier
Description

Features

The 4136 is made up of four 741 type independent
high gain operational amplifiers internally
compensated and constructed on a single Silicon Chip
using the planar epitaxial process.

•
•
•
•
•

This amplifier meets or exceeds all specifications for
741 type amplifiers. Excellent channel separation
allows the use of the 4136 quad amplifier in all 741
operational amplifier applications providing the
highest possible packaging density.

•
•
•

Unity gain bandwidth - 3 MHz
Short circuit protection
No frequency compensation required
No latch-up
Large common mode and differential voltage ranges
Low power consumption
Parameter tracking over temperature range
Gain and phase match between amplifiers

The specially designed low noise input transistors
allow the 4136 to be used in low noise signal
processing applications such as audio preamplifiers
and signal conditioners.

I
For More Information, caJI1-800-722-7074.

Raytheon Semiconductor

3-547

RC4136
Connection Information
14-Lead Dual-In-Llne
Package
(Top View)

Thermal Characteristics
Pin
1
2
3
4
5
6

7
8
9
10
11
12

Function
-Input (A)
+Input (A)
Output (A)
Output (8)
+Input (8)
-Input (8)
-VS
-Input (C)
+Input (C)
Output (C)
+VS
Output (0)
+Input (0)
-Input (0)

14-lead
Small
Outline

14-lead 14-Lead
Plastic Ceramic
DIP
DIP

Max. Junction Temp.

+1250C

+1250C

+1750C

Max. Po TA <50OC

300mW 468mW 1042mW

Therm. Res 0JC

ao°clW

Therm. Res. 0JA

2000CIW 1600CIW 1200ClW

For TA >50OC Derate 5.0mW
per'C
at

a.25mW 8.38mW
per'C
per'C

Ordering Information

Absolute Maximum Ratings
Supply Voltage
RM4136 ...............•..............................±22V
RC4136 ...........................••...•.............±18V
Input Voltage' ...........................................................................±30V
Differential Input Voltage •........................... 30V
Output Short Circuit Duration2 ..................... lndefinite
Storage Temperature
Range •....•........•...•...•.....•.. -65°C to +150°C
Operating Temperature Range
RM4136 ............................ -55°C to +125°C
RC4136 .........•.......•................ 0°C to +70°C
Lead Soldering Temperature
(DIP, 60 sec) ................................... +300°C
(SO-14, 10 sec) •..................•........... +260-C

Package

Operating
Temperature
Range

RC4136N
RC4136M

N
M

O°C to +70°C
O°C to +70°C

RM41360
RM413601883B

0
0

-55°C to +125°C
-55°C to +125°C

Part Number

Notes:
883B suffix denotes Mil-Std-883. Level B processing
N - 14-1ead plastic DIP
D =14-lead ceramic DIP
M = 14-Jead plastic SOIC

Notes:
1. For supply voHages less than ±15V, the absolu1e
maximum input voltage is equal to the supply voltage.
2. Short circuit may be to ground, typically 45 mAo

3-548

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4136
Electrical Characteristics

(Vs =±15V and TA =+25'C, unless otherwise noted)

Parameters

Test CondHlons

Input Offset VoHage

RgS1Dkn

Min

RM4136
Typ

Max

Min

RC4136
Typ Max

UnHs

0.5

5.0

0.5

6.0

mV

Input Offset Current

5.0

200

5.0

200

Input Bias Current

40

500

40

500

nA
nA

0.3

5.0

0.3

5.0

Mil

50

300

20

300

VImV

RL~10k.Q

±12

±14

±12

±14

V

RL~2kn

±10

±13

±12
70

±14
100

±10
±12

±13
±14

V

70

100

dB

76

100

76

100

dB

Input Resistance
Large Signal VoHage Gain

RL~2kO,

Output VoHage Swing

VOUT =±10V

Input VoHage Range
Common Mode Rejection Ratio RsS10k.Q
Power Supply Rejection Ratio RgS10k.Q
RL =00, All Outputs

210

Rise Time

VIN =20mV, RL =2kn

0.13

0.13

~

Overshoot

CLS100pF

5.0

5.0

%

Unity Gain Bandwidth
Slew Rate

3.0

MHz

RLi?!2kn

3.0
1.5

1.0

Channel Separation

F - 1.OkHz, Rs=1k.Q

90

90

V4JS
dB

Power Consumption

210

340

340

mW

Transient Response

=

=

=

=

The following specifications apply for RM -SS"C s TAS 125° RC O"C STAS 70°, VS

Input Offset VoHage

=±15V

6.0

7.5

Input Offset CUrrent

500

300

nA

Input Bias Current

1500

800

nA

RgS1Dkn

Large Signal VoHage Gain

RL~2kD,

Output VoHage Swing

RL~2k.Q

Power Consumption

For More Information, caD 1-800-722-7074.

VOUT=±10V

25
±10
240

Raytheon Semiconductor

400

mV

15

V/mV

±10

V
240

400

mW

3-549

I

RC4136
Electrical Characteristics Comparison
(VS = ±1SV and TA +2S'C unless otherwise noted)

Parameter
Input Offset Voftage
Inout Offset Current
Inout Bias Current
Inout Resistance
Large Signal Voftage Gain (RL = 2~
Output Voftage Swing (RL=~
Input Voftage Range

RC4136(Typ)
0.5
5.0
40
5.0
300
±13V

RC741(Typ)
2.0
10
BO
2.0
200
±13V

±14V

±13V

LM324(Typ)
2.0
5.0
55
100
I+Vs ,1.2VI
to-Vs
I+Vs -1.5VI

Units
mV
nA
nA
Me
VimV
V
V

to-V~

Common Mode Rejection Ratio
Power Supply Rejection Ratio
Transient Response
Rise Time
Overshoot
Unity Gain Bandwidth
Slew Rate
Input Noise Voftage Density (F= 1kHz)
Short Circuit Current

3-550

100
100

90
90

0.13
5.0
3.0
1.0
10
±45

0.3
5.0
O.B
0.5
22.5
~5

Raytheon Semiconductor

85
100

dB
dB

uS
O.B
0.5

%
MHz
VIuS
nVM-Iz
mA

For More Information, call 1-800-722-7074.

RC4136
Typical Performance Characteristics
Input Offset Current VS. Temperature

Input Bias Current VS. of Temperature
25

100
80
~

60

~

40

.s

r--

I I

20 -

vs= ±15V

vs= ±15V

15

-

10

'--.r--

5

20
+10

+20

+30

+40

+50

+60

~

o

+70

o

+10

+20

'"
+30

+40

+50

+60

~

+70

TA (GC)

TA (GC)

Input Common Mode Voltage Range vs.
Supply Voltage

Output Voltage vs. Supply Voltage

10
51-=......::;F7':~i'7'5~&-S...;..1:,..s.."'71,....::,..o;,..

s.
G~

10

~

~

o

10

100

1K

~

10K

0.1

100K

10

1

100

F (Hz)

22

~ 20
~

J

18
16
14
12
10
8

0.1

~

100K

Quiescent Current vs.
Supply Voltage

..-

10

I--!-

I

TA = +25°C

8

I'

II
I

10K

F (Hz)

Output Voltage Swing vs. Load Resistance
28
26 '-Vs ~ ±l~vl
24 f-- TA =+25°C

1K

~

6

I

4
2

/
10

±3

±6

±9

±12

±15

!

±18

+VsI-Vs (V)

3-552

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4136
Typical Performance Characteristics (Continued)
Transient Response
Output Voltage vs. Time

Follower Large Signal
Pulse Response

E

J

10
8
6
4
2
0
-2
-4
-6
-8
-10

28

I

I

I

I

I

I

I

I

Vs = :t15V
TA= +25·C-

Output

I
I

J
I
1

~

o

10

I

I

24
20

t

I

I 1\
I
I
I
\
I
I I
IlnPjt 1_
I
I

J

--

16
12

90",(, .,F-

/

8

Vs = :t15V
TA =+25 0 C RL=2kn _
CL-100pF

/

4

if- 10% Rise Time

o

20
30
TIme (lIS)

-

o

40

0.25

0.50

Channel Separation VS. Frequency

~ 0.4

fj

60

~ 0.3

40

0.2

~

20 I- Vs = ±15V
TA =+~~~C

o

100

1K

Vs =±30V

0.5

80

10

V~~ ~I~I~RMSI

0.6

iii'
::2-

~

1.25

Total Harmonic Distortion vs. Frequency

r--.

100

1.00

Time (lIS)

140
120

0.75

10K

\

\
L

0.1

o

10

100K

100

F (Hz)

lK

10K

~

100K

F(Hz)

Total Harmonic Distortion vs. Output Voltage

-

0.6
0.5

~

Q

i!:

0.4

I

I

I

0.3
0.2

,. /

0.1

o

123

For More Information, call 1-800-722-7074.

I

I

- Vs = ±15V
RL=2K
- Ay=40dB
_F=lkHz
Rs = lkn

4

5

6

7

8

Raytheon Semiconductor

9

i

10

3-553

RC4136
4136 Versus 324
Although the 324 is an excellent device for singlesupply applications where ground sensing is
important. it is a poor substitute for four 741 s in split
supply circuits. The simplified input circuit of the 4136

4136

exhibits much lower noise than that of the 324 and
exhibits no crossover distortion as compared with the
324 (see illustration). The 324 shows significant
crossover distortion and pulse delay in attempting to
handle a large signal input pulse.

Comparative Crossover Distortion

324

F =50 kHz ____
VOUT =8 Vp•p

Rl =2kn
Av=1
Vs =f:5V
65-0539

Output Voltage Swing vs. Frequency

Open Loop Gain vs. Frequency
120
100

r--

80

iii' 60
:E.

J

~

~~
~K

K

40
20

4136
741

r-.....
~ 1'-..

f": 1'-..
f'

o
-20 1

10

100

1K

10K 100K

1M

o

~

10M

F(Hz)

3-554

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC4136
Follower Large Signal Pulse Response
Output Voltage vs. Time
+8
+6
+4

~

J

I
I

I- 4136 "

+2

0
-2
-4

~

-8

14

RL -2kO

12

1---

o

30

40
TIme (lIS)

16

I

Vs. ±10V-

I /
I l/ Oytputs \\
.1
1/ Input
\ I~
V
\ \

-6

Input Common Mode Voltage Range vs.
Supply Voltage

60

I324

~

10

J

8

+

~

80

6
4
2

-

'ooe -TA~+70oe

L

,.

./ /"

./ ./
-741
./ ~
,......",

L
/

o

±5

V/ "

V

:1:10

--

-4136

:1:15
+VS/-VS(V)

!

:1:20

I
For More Information. caD 1-800-722-7074.

Raytheon Semiconductor

3-555

RC4136
Typical Applications (Continued)
Power Amplifier

lamp Driver

+Vs
910K

65-0523

VoHage Follower

Comparator with Hysteresis

10K

3

>--+--0

>3~_O

VOUT

Vour

65-0522

65-0519

DC Coupled 1 kHz lowpass Active Filter

Squarewave Oscillator
+Vs

0.01 fLF
o-..AJ",,"~r----II----.--o

lOOK
VOUT

O.OlfLF ~

65-0521

3-556

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC4136
Typical Applications (Continued)
1 kHz Bandpass Active Filter

620K

65-0528

AC Coupled Inverting Amplifier

AC Coupled Non-Inverting Amplifier
1M

0.1

lOOK

JLF

-=

65-0525

65-0524

Voltage Control Oscillator (VCO)
lOOK
R

I

lOOK
51K

3

JLrL
OUlpUt 1

/VV
Output 2
10K
• Wide control voltage range: OV < Vc < 2(+Vs-l.SV)

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

65-0526

3-557

RC4136
Typical Applications (Continued)
Full-Wave Rectifier and Averaging Filter
20K

1%

20K

2.5K

1%

Cal

r-------~~----------~~~~~roDC

Output

4.7 !If

AC ,,_TI
Input \ . r j

H

20K

20K

1-!+~J\j11\i%~~_ _--I"'---0

Input

Output

Trim R, such that

R1
R3
R2 = 2R4

65-0529

Notch Frequency vs. C1
10K

~ 741
lK

.o 100

10
0.0001

"' ....

0.001

0.001

0.01

!

1.0

Center Frequency (Hz)

3-558

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4136
Typical Applications (Continued)
Multiple Aperture Window Discriminator

3
V4

4
V3

10

V2--+--0

VOUT

R1 =R4
R2=R5

Inputs

R6~R7

1

(+)

" Matching detennines CMRR

A

v

R5"
10K

0.1%

=

RS ( 1 + 18!..)

R2

R3

R7*
100K

0.1%
65-0533

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-559

RC4136
Typical Applications (Continued)

Analog Multiplier/Divider
,.------11--0 +15V

·Matched Transistors

3-560

Raytheon Semiconductor

65-0534

For More Infonnation, call 1-800-722-7074.

RC4136
Typical AppllcaUons (Continued)

Spot Noise Measurement Test Circuit

~

______49.9K ______
~~

3.3M
~~~~

I

__

DC-1HzN
----~O~

0.082
IIF

3

60 dB Wideband
Amplifier

78.7K

10llF 1 Hz
I

111F

t-o

0.111F

I
I
I

t-olI

0.0111F

r - - - - - 1........>-i~Hzl
3.16K

10K
31.6K
100K

1mV

=1nVliHi
RMS

I

3.16K 1 Hz

10 IIF, Hzl

I
I
I
I
I
I

4990

1 kHz 1 1 k H zI Selectable Frequency

Stepped 10 dB
Atlenuator

I

L______

I

:=: _____ J

Constant a Filler

65-0535

For Mora Information, caD 1-800-722-7074.

Raytheon Semiconductor

3-561

I

RC4136
Schematic Diagram

+~o---------~--------------~--------~----~----~----~
(11)

-Input

Output
(3.4.10.12)

+Input 0 - - - + - - - - - - 1 - - '
01

(2.5.9.13)

15 pF

Z1
5.5V

R2
5K

-~O---~~--~---(7)

R3
5K

__--------~--------__----__----1-----1-----~
65-0495

3-562

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC4156/RC4157
RC4156/RC4157
High Performance Quad Operational Amplifiers
Description

Features

The 4156 and 4157 are monolithic integrated circuits,
consisting of four independent high performance
operational amplifiers constructed with an advanced
epitaxial process.

•
•
•
•
•
•
•

These amplifiers feature guaranteed AC performance
which far exceeds that of the 741 type amplifiers.
Also featured are excellent input characteristics and
guaranteed low noise, making this device the optimum
choice for audio, active filter and instrumentation
applications. The 4157 is a decompensated version
of the 4156 and is AC stable in gain configurations of 5 or greater.

Unity gain bandwidth for 4156 - 3.5 MHz
Unity gain bandwidth for 4157 - 19 MHz
High slew rate for 4156 -1.6 V/J,JS
High slew rate for 4157 - 8.0V/J,JS
Low noise voltage -1.4 J,NRMS
Indefinite short circuit protection
No crossover distortion

I
For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-563

RC4156/RC4157
Ordering Information

Connection Information

Package

Operating
Temperature
Range

RC4156N
RC4156M
RC4156D
RC4157N
RC4157M

N
M
D
N
M

O°Cto +70°C
O°C to +70°C
O°C to +70°C
O°C to +70°C
O°Cto +70°C

RM4156D
RM4156D/8838

D
D

-55°C to +125°C
-55°C to +125°C

Part Number
14-Lead
Dual In-LIne Package
(Top View)

Pin Function
1
2
3
4
5
6
7

Output (A)
-Input (A)
+Input (A)
+VS
+Input (8)
-Input (8)
Output (8)
8 Output (C)
9 -Input (C)
10 +Input (C)
11 -VS
12 +lnput(O)
13 -Input (0)
14 Output (0)

NOIIIS:

/8838 suffix denotes MU-Std-883. Level 8 processing
N = 14-lead plastic DIP
D = 14-leadceramic DIP
M _ 14-1ead plastic SOIC

85-0736

Absolute Maximum Ratings
Supply Voltage ...........................................±20V
Differential Input Voltage .............................. 30V
Input Voltage1 ...._••••••___..........._.............._ •••__ ................. __•• ±15V
Output Short Circuit Duration2 ........... _........_.lndefinlte
Storage Temperature
Range ................................. -65°C to +150°C
Operating Temperature Range
RM4156/4157 ..................... -55°C to +125°C
RC4156/4157 .......................... O°C to +70°C
Lead Soldering Temperature
(DIP; 60 sec) ....................................+300°C
(S0-14; 10 sec) ................................ +260°C
Notes:
1. For supply voltages less than ±15V. the absolule maximum
Input voltage is equal to the supply voltage.
2. Short circuit to ground on one amplifier only.

3-564

Raytheon Semiconductor

For More Infonnation. call H!OD-722-7074.

RC4156/RC4157
Thermal Characteristics
14-Lead
Plastic 50-14

14 Lead
Plastic DIP

14 Lead
Ceramic DIP

Max. Junction Temp.

+125°C

+125°C

+175°C

Max. Po TA <50°C

300mW

468mW

1042mW

-

-

60°C/W

Therm. Res 9J C
Therm. Res. 9JA
For TA >50°C Derate at

200°C/W

160°C/W

120°C/W

5.0 mW/oC

6.25mWrC

8.38 mW/oC

Electrical Characteristics
(Vs =±15V, RM = -55OC STAS+125OC, RC = O°C STAS+70°C)
RM4156/4157
Min lYP MaX

RC4156/4157
Min lYP Max

5.0

6.5

mV

Input Offset Current

75

100

nA

Input Bias Current

320

400

nA

Parameters

Test Conditions

Input Offset Voltage

Rs S10 kn

Large Signal Voltage Gain
Output Voltage Swing

UnHs

RL2:2 kn,VOUT ±10V

25

15

V/rnV

RL 2:2 kn

±10

±10

V

Supply Current

10

10

rnA

Average Input Offset Voltage Drift

5.0

5.0

Jl'v/°C

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-565

I

RC4156/RC4157
Electrical Characteristics
(VS = ±15V and TA = +25OC unless otherwise noted)
RM4156/4157

Typ

Max

0.5
15

Input Bias Current

60

200

Input Resistance

0.5

Parameters

Test Conditions

Input Offset Voltage

Rs s; 10 k.Q

Min

Input Offset Current

RC4156/4157

Typ

Max Units

3.0

1.0

5.0

mV

30

30

50

nA

60

300

Min

nA

0.5

MO

Large Signal Vottage Gain

RL ~2 k.O. Vour±10V

50

100

25

100

V/mV

Output Vottage Swing

RL ~10 k.Q

±12
±10

±14
±13

±12
±10

±14
±13

V
V

±12

±14

±12

RL~2kO

±14

V

Output Resistance

Input Vottage Range

230

230

0

Short Circun Current

25

25

mA

Common Mode Rejection Ratio

Rs S;10kO

80

80

Power Supply Rejection Ratio

Rs S10kO
RL =00

80

80

Supply Current (All Amplifiers)

4.5

dB
dB
5.0

5.0

7.0

mA

Transient Response (4156)
Rise Time

25

%

1.3

1.6

1.3

1.6

V~

2.8

3.5

2.8

Overshoot

25

Slew Rate
UnHy Gain Bandwidth (4156)

nS

60

60

3.5

MHz

50

50

%

Rise Time

50

50

nS

Overshoot

25

25

%

Phase Margin (4156)

RL = 2 k.O. Ct. = 50 pF

Transient Response (4157)

Av = J!j

Slew Rate
UnHy Gain Bandwidth (4157)
Phase Margin (4157)

Av=-5

6.5

8.0

6.5

8.0

V/jJS

15

19

15

19

MHz

50

%

50

Av=-5RL=2k.O.
CL =50pF

Power Bandwidth
Input Noise Vottage

Your = 20Vp•p
F= 20 Hz to 20 kHz

Input Noise Current

F=20Hzt020kHz

Channel Separation

3-566

20

20

25
1.4

2.0

25
1.4

15

15

108

108

Raytheon Semiconductor

kHz
2.0

!lVRM~

pARMS
dB

For More Information, call 1-800-722-7074.

RC4156/RC4157
Typical Performance Characteristics
Open Loop Gain, Phase vs. Frequency
110
100
90
80
iii 70
:2- 60
50
40

J

11~~~::::l
.~J~I

Im~~~I~~ III
CL=55pF

4>

20
10

o
1

10

100

o
45
90

30

-10

PSRR vs. Temperature
140

1K 10K lOOK 1M
F (Hz)

iii

120

I-.

100

r-

~

:2- 80

&

II)

II:
II:

+Vs

-

-Vs ---

"'"

-

60

a..

135

40

180

20

o

10M

-100 -75 -50 -25

o

+25 +50 +75+100+125+150
TA (Oc)

Channel Separation vs. Frequency
lOOK

-140
-120

r-

-100

i
II)

()

-80

C.s. = 20 log ( VOUT2 )
100 VOUT1

lOOK

-60
-40
-20

o

10

100

1K

10K

100K
65-0739

F(Hz)

Input Noise Voltage, Current Density
vs. Frequency

Transient Response vs. Temperature
1.3

35

1.4

ap- 1.2

30

1.2

S
~
0..+

25

:s

~1
5=
-al

1.1
1.0

~l -

I-""""

t--

0.9

~
>
.s

.r

i E 0.8

,

15
10

.. 0

I-~ 0.7

5

0.6
-100 -75 -50 -25 0 +25 +50 +75+10Or125+150

0.8

~ .......

"-

0.6
en

0.4

IN

0.2

o
10

100

1K

10K

0
100K

~
--4--oV4
Triangle
Wave
Output

L-------~vr--------~

.-----------+

Integrator
5K

+15V Q--'VV\r---.

V3

• Optional - asymmetric ramp slopes
-15V

n--J\""'---'

~750

5K

Figure 1. Triangle and Square Wave Generator

65-2051

Figure 2. Triangle Generator - Symmetrical Output Option

Active Filters
The introduction of low-cost quad op amps has had a
strong impact on active filter design. The complex
multiple-feedback, single op amp filter circuits have
been rendered obsolete for most applications. Statevariable active-filter circuits using three to four op
amps per section offer many advantages over the
single op amp circuits. They are relatively insensitive
to the passive-component tolerances and variations.
The Q. gain. and natural frequency can be
independently adjusted. Hybrid construction is very
practical because resistor and capacitor values are
relatively low and the filter parameters are determined
by resistance ratios rather than by single resistors. A

3-570

generalized circuit diagram of the 2-pole state-variable
active filter is shown in Figure 3. The particular input
connections and component-values can be calculated
for specific applications. An important feature of the
. state-variable filter is that it can be inverting or noninverting and can simultaneously provide three
outputs: Iowpass. bandpass. and highpass. A notch
fi~er can be realized by adding one summing op amp.
The 4156 was designed and characterized for use in
active filter circuits. Frequency response is fully
specified with minimum values for unity-gain
bandwidth. slew-rate. and full-power response.
Maximum noise is specified.

Raytheon Semiconductor

For Mora Information. call 1-800-722-7074.

RC4156/RC4157
R5
100K

R4
V1

C2

C1
1000 pF

10K

1000 pF

R3·

O--"",tV--.

VLP
Lowpass
Output
VHP
Highpass

OUput

VBP
Bandpass
Output

• Input connections are chosen for inverting or non-inverting response. Values of
R3.R7.RS determine gain and Q.
•• Values of Rl and R2 determine natural frequency.

65-0751

Figure 3. 2 - Pole State-Variable Active Filter
Output swing is excellent with no distortion or clipping.
The 4156 provides full, undistorted response up to 20
kHz and is ideal for use in high-performance audio
and telecommunication equipment.

The input configuration determines the polarity
(inverting or non-inverting), and the output selection
determines the type of filter response (Iowpass,
bandpass, or highpass).

In the state-variable filter circuit, one amplifier
performs a summing function and the other two act as
integrators. The choice of passive component values
is arbitrary. but must be consistent with the amplifier
operating range and input signal characteristics. The
values shown for C1, C2, R4, RS and R6 are arbitrary.
Pre-selecting their values will simplify the filter tuning
procedures, but other values can be used if
necessary.

Notch and all-pass configurations can be implemented
by adding another summing amplifier.

The generalized transfer function for the state-variable
active filter is:

Design Example - Bandpass Filter

T (s) _a~2 + a1 s +

ao

s2+b1s+bO

Bandpass filters are of particular importance in audio
and telecommunication equipment. A design
approach to bandpass filters will be shown as an
example of the state-variable configuration.

For the bandpass active filter (Rgure 4) the input
Signal is applied through R3 to the inverting input of
the summing amplifier and the output is taken from
the first integrator (Vsp). The summing amplifier will
maintain equal voltage at the inverting and noninverting inputs (see equation on next page).

Filter response is conventionally described in terms of
a natural frequency roo in radians/sec, and Q, the
quality of the complex pole pair. The filter parameters
roo and Q relate to the coefficients in T(s) as:

roo = ~Do

and Q = roO
bO

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-571

I

RC4156/RC4157
Set Center Frequency

RS
100K

65-0752

Figure 4. Bandpass Active FiRer
R3RS

R3R4

R4RS

R3 + RS
VHP (S) +
R3 + R4
VLP (S) + R4 + RS
R3R4
R4RS
R4
R3RS
RS+ R3+R4
R3+ R4+RS
+ R3+RS

V1N (S) + RSR+7R7 Vsp (s)

These equations can be combined to obtain the transfer function:

1
Vsp (s) = - R1 C1 S VHP (s) and VLP (s) =

1
- R2C2S Vsp (s)

R4
R3

VSP (s)
VIN (s) =

Defining 1/R1C1 as Cl)I, 1/R2C2 as Cl>z, and
substituting in the assigned values for R4, RS,
and RS, then the transfer function simplifies to:

104

v;(S)

CI)

R3

VSP (s)

This is now in a convenient form to look at
the center-frequency roo and filter O.

roo = '10.1 Cl)lfD2

1

=

104 ]
1.1 + R
S2 + [
1~
1
0
+ R7

3-572

s

1
R1C1 S

roo = 10-9 '10.1
Cl)1 S

andO=
R1R2

[1

+

1.1 +

~;] COo
4

~3

+ _1_
Cl)lfD2

The frequency response for various values of 0
are shown in Figure S.

Raytheon Semiconductor

For More Infonnation, call 1-800-722-7074.

RC4156/RC4157
o
-10

ar

",

V

-20 ".,.. . /

./

.....

:2. -30

V
-40 V
../

-50
-60

.\\.~

,,'\\, ....

~

~

'"

",

......

1. The passive component values should be chosen
such that all op amps are operating within their linear
region for the anticipated range of input signals. Slew
rate, output current rating, and common-mode input
range must be considered. For the integrators, the
current through the feedback capacitor (I = C dV/dt)
should be included in the output current computations.

~"' .......... o=o.~,
\\.

:......

" :--.......

~""-

1/

'- r--...

1/

"

0= 1.0
0=2.0
0=5.0
0= 10
0=20
0=50 '
0= 100

~'"

Vr -(~oJJ (i- ~o)2

2. From the equation for 0, it should seem that
infinite 0 could be obtained by making R7 zero. But
as R7 is made small, the 0 becomes limited by the op
amp gain at the frequency of interest. The effective
closed-loop gain is being increased direcUy as R7 is
made smaller, and the ratio of open-loop gain to
closed-loop gain is becoming less. The gain and
phase error of the filter at high 0 is very dependent on
the op amp open-loop gain at COo.

Figure 5. Bandpass Transfer
Characteristics Normalized for
Unity Gain and Frequency

3. The attenuation at extremes of frequency is
limited by the op amp gain and unity-gain bandwidth.
For integrators, the finite open-loop op amp gain limits
the accuracy at the low-end. The open-loop roll-off of
gain limits the filter attenuation at high frequency.

~

V

l,...o-""

0.1

" 10

1.0

ro

roo
ro

V;

1

roo a

Vep
=

+

These equations suggest a tuning sequence where ro
is first trimmed via R1 or R2, then 0 is trimmed by
varying R7 and/or R3. An important advantage of the
state-variable bandpass filter is that 0 can be varied
without affecting center frequency COo.
This analysiS has assumed ideal op amps operating
within their linear range, which is a valid design
approach for a reasonable range of roo and O. At
extremes of COo and at high values of 0, the op amp
parameters become Significant. A rigorous analysis is
very complex, but some factors are particularly
important in designing active filters.

The 4156 quad operational amplifier has much better
frequency response than a conventional 741 circuit
and is ideal for active filter use. Natural frequencies of
up to 10kHz are readily achieved and up to 20 kHz is
practical for some configurations. 0 can range up to
50 with very good accuracy and up to 500 with
reasonable response. The extra gain of the 4156 at
high frequencies gives the quad op amp an extra
margin of performance in active-filter circuits.

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-573

RC4156/RC4157
Schematic Diagram

(1/4 Shown)

r

--_---1P""-..---------.......--.----_--o(4)
+V.
~------;---~----------------_+~~Q1

(2,6,9,13)

-Input

(1,7,8,14)
Outputs

+ Input
(3,5,10,12)

R6
20 RS

150

To

Next
Amplifier

R7

20

R2
10K

01

'--_-+-_+-_-+-_ _ _---50·C Derate at

Matching Characteristics
(Vs = ±15V. TA = +25OC unless otherwise specified)
Test
Conditions

RMlRC4558

Typ

Units

Voltage Gain

RL~2kn

±1.0

dB

Input Bias Current

RL~2kn

±15

nA

Input Offset Current

RL~2kn

±7.5

nA

Parameter

I
For More Information, caD HlOO-722-7074.

Raytheon Semiconductor

3-577

RC4558
Electrical Characteristics
(Vs = ±15V and TA = +25OC unless otherwise specified)

Parameters
Input Offset Vottage

Test CondHlons

MIn

RM4558
Typ

Max

1.0

RsS10kO

Min

RC4558
Typ

5.0

2.0

Max UnHs
6.0

mV
nA

Input Offset Current

5.0

200

5.0

200

Input Bias Current

40

500

40

500

Input Resistance

0.3

Large Signal Vottage Gain

RL~2kn,

Output VoKage Swing

RL~10kO

RI

Vour =±10V

~2kn

Input VoKage Range
Common Mode Rejection Ratio
Power Supply Rejedion Ratio

Rs S10kO
Rs SI0kO

Power Consumption

RL=

Transient Response

1.0

0.3

nA

1.0

MO

50

300

20

300

VImV

±12

±14

±12

±14

V

±10

±13

±10

±13

V

±12

±13

±12

±13

V
dB

70

100

70

100

76

100

76

100

100

00

170

100

dB
170

mW

VIN= 20mV
RL =21<0
CLS100pF

0.3

0.3

~

35

35

%

Slew Rate

RL~2kn

0.8

0.8

Channel Separation

F = 10kHz, As .. lkO

90

90

VIIJS
dB

3.0

MHz

Rise Time
Overshoot

Unity Gain Bandwidth (Gain .. 1)

2.5

3.0

2.0

The following specificatIons apply for RM =-55"C S TA S +125"C, RC =00 S TA S +70"C

Input Offset VoKage

6.0

7.5

mV

500

300

nA

RSSI0kO

Input Offset Current
RC4558
Input bias Current
RC4558

1500

Large Signal Vottage Gain

RL~2kD, Vour=±10

Output Vottage Swing

RL~2kO

Power Consumption

RL=oo

3-578

800

nA

25

15

VlmV

±to

±10

V
mW

120

200

Raytheon Semiconductor

120

200

For More Information, caD 1-800-722·7074.

RC4558
Typical Performance Characteristics
Input Offset Current vs. Temperature

Input Bias Current vs. Temperature
25

100

80

c;

SO

..!f

40

.s

r--

I

-

J

20 r- Vs = ±15V

Vs = ±15V

15
~

10

r-- t----

5

20
+10

+20

+30

+40

+50

+SO

~

o

+70

o

+10

+20

+30

TA (OC)

i

+60

+70

Open Loop VoHage Gain VS. Frequency
120

r-

100

10

...........

80

5~~~77~~~~~~~~~~
0

+50

TA (OC)

Input Common Mode VoHage Range vs. Supply VoHage

J€

+40

"- i"'o..

iii' SO

" r-..

~

~~~77~~~~~~~~~~

j

-5~~~~~~~~~~~~~~

40

20

......... i'..
.........

o
-15

±L4---±~S---±8~~~--~~~~~~

-20

10

1

100

1K

10K 100K

i"'o.. ...

1M

~

10M

F{Hz)

Open Loop VoHage Gain VS. Temperature
800
I--

SOO

f

~

J ±1~V

t- Vs

= ±15V

--.r--

120

.§. 100

400

~

L=2k~

r--

g

I

140

s=

:;-

...J

<

Power Consumption vs. Temperature

80

200
It)

o
o

~
+10

+20

+30

+40

+50

+60

+70

60

o

+10

+20

+30

+40

+50

+60

+70

TA (OC)

TA ("C)

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-579

RC4SS8
Typical Performance Characteristics

(Continued)

Output VoHage Swing vs. Supply Voltage

OUtput VoHage Swing vs. Load Resistance
28
26
24

€

~

J
-10
±6

±8

±10

±12

±14

±16

~vs~ ±l~VI

22
20
18

II

16
14
12
10

I

I

/

8

±18

b---" I-

...-

~ TA-+2S"C

10

0.1

+Vsf-Vs(V)

Output VoHage Swing vs. Frequency
40
36
32
28
24
~ 20
16
> 12

1111

Quiescent Current vs. Supply Voltage
5

I III

l~s=~lWI

\

€

4

TA = +2S·C
RL =2kO

~

3

1
!} 2

8

8
4
100

1K

10K

'"

'"

o

TA=+2S"C

lOOK

1M

~

o

o

±3

±6

F(Hz)

28

20

I-

12

So

::>

~

8
4
0

90%

I

"l

o

'--""

10% Rise Time

0.25

O.SO

€

Vs = :l:1SV
TA=+2SoC R L =2kO _
C L = 100pF

/

V-

0.75

1.00

I-

J

!

1.25

10
8
6
4
2
0
I
-2
II
-4
-6 I - -8
-10

- II

o

Time ( J.1S)

3-580

!

±15

±18

Follower Large Signal Pulse Response
Output VoHage vs. Time

24

16

±12

+V,/-Vs(V)

Transient Response
Output VoHage vs. Time

>

±9

Raytheon Semiconductor

I

I

I

I
Output

I
I
I Input

I
I
10

I

Vs = :l:1SV
TA = +2S"C-

I'
I\.
i .'\
1
1_

--

20
30
Time (lIS)

40

For More Information. caJI1-800-722-7074.

RC4558
Typical Performance Characteristics

(Continued)
Input Noise Voltage Density vs. Frequency

Input Noise Current Density vs. Frequency
1000

100
Vs = ±15V
TA - +25 OC
Rs=50n
Ay =60dB

\

Li

Vs - ±15V _
TA = +25°C
Rs=50 n
Ay =60dB ;:

\

100

:>

s.

........

J'

~

0.1

1

10

100

lK

10

o

10

100

lOOK

10K

Total Harmonic Distortion vs. Output VoHage

Channel Separation vs. Frequency
140

,

II

120

r--....

100

m 80

g

~

Q

60

j:

40
20

lK
F (Hz)

F (Hz)

fj

~

1

lOOK

10K

0.6 I - - r- Vs = ±15V
RL=2K
0.5 t - - r- Ay=40dB
0.4 I - - r- F =1kHz
Rs = 1kn
0.3

I

'I

0.2

r-

o
10

Vs = ±15V
TA = +25°C

~

1111

100

lK

10K

.... /

0.1

o

lOOK

1

2

3

4

F (Hz)

5

6

Vour (VRMS

7

8

~~
9

10

)

Distortion vs. Frequency

0.5

g
Q

j:

0.4
0.3

I

V~u~ ~ljl~RMSI

0.6

Vs =±30V

\
\

0.2

/

0.1

o

10

100

lK

10K

!

lOOK

F(Hz)

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-581

RC4558
Typical Applications
Lamp Driver

Voltage Follower

+Vs

>-......-oVour

65-0229

Power Amplifier

Comparator With Hysteresis

910K
-VIN

+Vs

0----=-1
10K

>-_0 Vour

lOOK
65-0231

Squarewave Oscillator
lOOK

lOOK
lOOK
65-0232

3-582

Raytheon Semiconductor

For More Information, call1-80D-722-7074.

RC4558
Typical Applications

(Continued)

DC Coupled 1kHz Low-Pass Active Filter
VIN

AC Coupled Non-Inverting Amplifier
1M

16K
O.OlI1F
D--Mfv-+---It---.......- { ) V OUT

...-----'\M...-----..-O VOUT

VIN 0--+--11-........-"'''-1

lOOK

lOOK
0.1

!1F

lOOK
65-0233
65-0234

1kHz Bandpass Active Filter
V"

AC Coupled Inverting Amplifier
lOOK

3901<

>----+_{) VOUT
620K

65-0236

Voltage Controlled Oscillator (VCO)
0.05 \IF

lOOK
51K

I

7

VOUT2
10K

• Wide control voltage range: OV < V < 2(+Vs -1.5Vs )
65'()237

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-583

RC4558
Schematic Diagram

+vso-________
~--------_.--------~----~~----~--~
(8)

Output

(1,7)
+Input

0----+----------+---1
(3,5)

R2

5K

-~o-~~~---4----~------~----~---+---4--~
65-0208

3-584

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4559
RC4559
High-Gain Dual Operational Amplifier
Description

Features

The 4559 Integrated circuit is a high performance dual
operational amplifier internally compensated and
constructed on a single silicon chip using an
advanced epitaxial process.

•
•
•
•

These amplifiers feature guaranteed AC performance
which far exceeds that of the 741-type amplifiers. The
specially designed low-noise input transistors ailow
the 4559 to be used in low-noise signal processing
applications such as audio preamplifiers and signai
conditioners.

•
•
•

The 4559 also has more output drive capability than
741-type amplifiers and can be used to drive a 600n
load.

•
•
•

Unity gain bandwidth - 4.0 MHz
Slew rate - 2.0 V/¢3
Low noise voltage -1.4I!VRMS
Supply voltage - :¥2.2.V for RM4559 and
±18V for RC/RV4559
No frequency compensation required
No latch up
Large common mode and differentiai voltage
ranges
Low power consumption
Parameter tracking over temperature range
Gain and phase match between amplifiers

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-585

RC4559
Connection Information
B-lead
TO-99 Metal Can
(Top View)

Ordering Information

a-lead
Dual In-line Package
(Top View)

65-0210

B-lead Plastic
Dual In-line SO-8
(Top View)

Pin
1
2
3
4
5
6
7
8

Function
Output (A)
-Input (A)
+Input (A)
-VS
+Input (8)
-Input (8)
Output (8)
+VS

Part Number

Package

RC4559M
RC4559N
RC4559D

M
N
D

RM4559D
RM4559D/8838
RM4559T
RM4559T/8838

D
D
T
T

Operating
Temperature
Range
O·C to +70·C
O·C to +70·C
O°C to +70°C
-55·C to +125·C
-55·C to +125·C
-55·C to +125·C
-55·C to +125·C

Notes:
18838 suffix denotes Mil-Std-883, Level 8 processing
N = 8-lead plastic DIP
D = 8 lead ceramic DIP
T =8-lead metal can (T0-99)
M = B-Iead plastic sOle

Absolute Maximum Ratings
Supply Voltage
RM4559 ...............................................±22V
RC4559 ...............................................±18V
Input Voltage 1 ............................................................................ ±15V
Differential Input Voltage ............................. 30V
Output Short Circuit Duration2 ...................... Indefinite
Operating Temperature Range
RM4559 ............................. -55·C to +125·C
RC4559 ................................... O·C to +70·C
Lead Soldering Temperature
(SO-8; 10 sec) .................................. +260·C
Lead Soldering Temperature
(DIP. TO-99; 60 sec) ....................... +300·C
Notes:
1. For supply voltages less than ±15V, the absolute maximum
input voltage is equal to the supply voltage.
2. Short circuit may be to ground on one op amp only. Rating
applies to +75' C ambient temperature.

3-586

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4559
Thermal Characteristics
8-Lead
Small Outline

8-Lead
Plastic
DIP

8·Lead
Ceramic
DIP

8-Lead
TO-99
Metal Can

Max. Junction Temp.

+125°C

+125°C

+175°C

+175°C

Max. Po T A<50'C

300mW

468mW

833mW

658mW

45°CIW

50°CIW

Therm. Res 9JC
Therm. Res. 9JA
For TA >50'C Derate at

-

-

240°CIW

160°CIW

150°CIW

190°CIW

4.17 mW/oC

6.25 mW/oC

8.33 mW/oC

5.26 mW/oC

Matching Characteristics
(Vs = ±15V, TA = +25OC unless otherwise specified)
Test
Conditions

RMlRC4559
Typ

RL2:2 kQ

±1.0

dB

Input Bias Current

±15

nA

Input Offset Current

±7.5

nA

Parameter
Voltage Gain

Units

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-587

RC4559
Electrical Characteristics
(VS = ±15V and TA = +25°C unless otherwise specified)
RM4559
Parameters

Test CondHlons

Input Offset VoHage

Rs :S:l0kn

Min

Typ

Max

Max

UnHs

1.0

5.0

2.0

6.0

mV

5.0

100

5.0

100

nA

40
1.0

250
0.3

40
1.0

250

0.3

nA
Mil

50

300

20

300

V/mV

RL ~ 10kn

±12

±14

±12

±14

V

RL~2kn

±10

±13

±10

±13

V

RL~600il

:±9.5

±10

:±9.5

±10

V

±12

±13

±12

±13

V

80

100

80

100

dB

82

100

82

100

Inout Offset Current
Input Bias Current
Input Resistance (Differential Mode)
large Signal Voltage Gain

IRC4559
Typ
Min

RL~2kn

VOUT= ±10V
Output Voltage Swing
Input Voltage Range
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Supply Current
Transient Response

Rs :S:l0kn
Rs :S:10kn
RL=oo
VIN =20mV

3.3

3.3

5.6

dB
5.6

mA

Rise Time

RL=2kn

80

80

nS

Overshoot

CL:S: 100pF

35

35

%

Slew Rate

1.5

2.0

1.5

2.0

Unity Gain Bandwidth

3.0

4.0

3.0

4.0

24

32
1.4

24

32
1.4

Input Noise Voltage

Your = 20VIrD
F= 20Hz to 20kHz

Input Noise Current

F= 20Hz to 20kHz

25

25

V/J,lS
MHz
kHz
J,lVRMS
pARMS

Channel Separation

Gain = 100, F= 10kHz

90

90

dB

Power Bandwidth

2.0

2.0

Rs = lkn
The following specifications apply for RM =·55OC :S:TA:S:+ 125"C, RC =OOC :S:TA :S:+70"C RM4559/RC4559
Input Offset Voltage

6.0

7.5

mV

Input Offset Current

300

200

nA

Input Bias Current

500

500

large Signal Voltage Galn

Rs :S:10kn

RL~kn

nA

25

15

V/mV

±10

±10

V

Vour=±10V
Output Voltage Swing

RL~2kn

Supply Current

RL =00

3-588

4.0

6.6

Raytheon Semiconductor

4.0

6.6

mA

For More Information. caJI1-800-722.-7074.

RC4559
Typical Performance Characteristics
Input Offset Current vs. Temperature

Input Bias Current vs. Temperature
25

100

80 C(

so

-

S.
..!!'

C(

15

Jl

10

.s

i--

40

I I

20 I-- vs. ±15V

vs= ±15V

1-- '--

5

20
+ 10

+20

+30

+40

+50

+SO

~

o

+70

'"

~

o

+10

+20

+30

+50

+70'"

+60

TA (DC)

TA (DC)

Open Loop VoHage Gain vs. Frequency

Input Common Mode VoHage Range vs. Supply
VoHage

--

120
100

10

80

5~~~~~~~~77~~~~~

iD so

~ 0~~77%~~:?7~71'~~~
~

+40

"""""

:2-

J

~~~~~~~~~7?~~~~71

"

~

40

"-

20

-10 1----1I---Ir-~I"'ooE6f7?~~~~71

o

-15 ':---J~~:---:-!':-~-=-~-:=~~~

·20

" "- r-...

"- ~

...

"'
10

1

100

lK

10K lOOK

1M

~

10M

F (Hz)

Power Consumption vs. Temperature

Open Loop VoHage Gain vs. Temperature

800

II
-

C-

J

>.§.

--

~ 400
200

o

o

+10

L=2kQ

+20

+30

+40

100

80

+50

+SO

~

+70

'"

so

o

~
+10

+20

+30

+40

+50

+SO

+70

TA (DC)

TA (DC)

For More Information, caJI1-800-722·7074.

Vs = ±15V

--- -

120

SOO

~

I

140

Vs= ±15V

Raytheon Semiconductor

3·589

RC4559
Typical Performance Characteristics

(Continued)

Output Voltage Swing vs. Supply Voltage

Output Voltage Swing vs. Load Resistance

15

28
26 I-- Vs ~ ±l~V I
24 I-- TA=+2S"C

10
5

.

€

J

22

€

20
18

..~
J

0
-5

II

16
14
12
10

-10

I
I
/

8
±6

±8

±10

±12

±14

±16

1.0

0.1

±18

Quiescent Current vs. Supply Voltage

Output Voltage Swing vs. Frequency
40

5

III

1111

36
32

l~s=~1W

3

lSJ

8 16

>

12

8

o
100

1K

10K

100K

2

TA=+2S"C

'"

I'..

4

-

4

TA = +2S·C
RL = 2 kG

1\

€

1M

~

o

o

±3

±6

28

10

24

8

J

12

8
4

o

I

90% .,{. "-'"

/
if- 10% Rise Time
0.50

€..

Vs = :!:lSV
TA = +2SoC RL=2kG _
C L = 100pF

/

0.25

±15

~

±18

I

0.75

1.00

J

~

1.25

2
0
-2
-4
-6

Output

II
I

-

I

I

I

Vs= :!:lSV
TA = +2S·C-

~-

4

o

I

I

I

I'
I
I

Input :_

\.

\

--

-8
-10

o

Time (J.lS)

3-590

I

6

20

§.

±12

Follower Large Signal Pulse Response
Output Voltage vs. Time

Transient Response
Output Voltage vs. Time

16

±9

+Vsf-Vs (V)

F (Hz)

>"

10

RL (kn)

+Vsf-Vs (V)

28
24
~ 20

-

...-

Raytheon Semiconductor

10

20
30
Time (1lS)

40

For More Information, caJI1-800-722-7074.

RC4559
Typical Performance Characteristics

(Continued)

Input Noise Current Density vs. Frequency

Input Noise Voltage Density vs. Frequency

100
Vs = ±15V
TA=+25 D C
Rs=50n
Av=60dB

1\

~ml~II~11

1000

III I
lUll

III~

0.1

1

1K

100

10

III I
10K

~

100K

o

F(Hz)

F{Hz)

Channel Separation vs. Frequency

Total Harmonie Distortion vs. Output Voltage

140
120

........

100

iii 80

'i
.....

~
~ 60

0

j:

40

0.6

-

0.5

-

0.4

TA = t,~~~C

o

100

10

1K

10K

!

100K

I=VOllT p.p
VOllT p.p

-

== VOllT p.p

2BV

-

lBV
-

BV

o

1

2

3

0.1

Vs - ±15

0.6

Vs - ±10V

0.5

Vs - ±5V

~ 0.4

~ 0.3

100

1K

I 111111
10K

100K

!

6

7

8

V~~ ~I~I~RMSI _
Vs =±30V

\

~

9

10

I

I

\

1M

L

0.1

o

10

F(Hz)

For More Informatbn, caJI1-800-722-7074.

5

0.2

RL-Open
CL-50pF

11111111

4

Total Harmonic Distortion vs. Frequency

~ \J~J!~~ F~II~~elrlll
~

-==

-

L

0.1

Your (VRMS )

Output Voltage Swing vs. Frequency

10

IL

0.3

F (Hz)

:E

1

0.2

20 I- Vs = ±15V

30

1

- Vsl= ±llv
RL=2K
- A v =40dB
_F=lkHz
Rs = lkn

100

1K

10K

~

100K

F{Hz)

Raytheon Semiconductor

3-591

RC4559
Typical Applications
400Hz Lowpass Butterworth Active Filter

10K

620Q

Input

Output

o--+-II-........JV,V\r_----'V\JI\r----_--'V\J'\r--~p____o

13.2K

65'()240

Stereo Tone Control

5K

SOK

SOK
0.068 !1F

0.068!1F

5K

0.068 !1F
O.0681'F

0.068 !1F

O.068!1F

1.67K

3-592

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4559
Typical Applications

(Continued)

RIM PreamplHier

VINA

V INB

Vs =± 15V

f""
12K1"0027.F

750pF
"-'\/VV-

65-0242

Triangular-Wave Generator
Integrator
C1
0.111 F

Threshold
Detector

>!...-.....O

8.2K

VOUT

65-0243

Low Frequency Sine Wave Generator with Quadrature Output

I

Sine
Output

0.0211F

Cosine

1----.-0 Output

50K

22M
Fo _1 Hz

6.3V
6.3V
6S'()244

For Mare Information, call 1-800-722-7074.

Raytheon Semiconductor

3-593

RC4559
Schematic Diagram
+Vso-________
~--------_.--------_1----~~----~----~
(8)

Output
(1.7)

+Input o----i----------i--J
(3.5)

R2
5K

~SO--_1~_1~--_1------+_--------~----_+---__~--_1--~
(4)

3-594

Raytheon Semiconductor

For More Infonnatlon. call 1-800-722-7074.

RC4207
RC4207
Precision Dual Operational Amplifier
Description

Features

Designed for low level signal conditioning. and
instrumentation applications, the 4207 is a precision dual
amplifier combining excellent DC input specifications with
low input noise characteristics. Ultra low input offset
voltage, low drift, high CMRR, and low input bias currents
serve to reduce input related errors to less than 0.01% in a
typical high gain instrumentation amplifier system (Av =
1000). The 4207 contains two separate amplifiers with a
high degree of isolation between them; each is complete
requiring no external compensation capacitors or offset
nulling potentiometers. The inherent VOS is typically less
than 150 J.1V, resulting in superior temperature drift, and
this low initial offset is further reduced by "Zener-zap·
nulling when the wafers are tested.

•
•
•
•
•
•
•
•
•

Low Noise - 0.35 J.1Vp-p (0.1 Hz to 10Hz)
Ultra-low Vos -75 J.1V
Ultra-low Vos drift-1.3 J.1VrC
Long term Vos stability - 0.2 J.1V/Mo
Low input bias and offset currents - ±5 nA
High gain - 400 V/mV
Fits 4558 socket
Industry standard pinout
8-lead mini-DIP

Advanced thin film and nitride dielectric processing allows
the 4207 to achieve its high performance and small size
(the 4207 is offered in a-lead DIPs). The 4207 fits the
industry standard 8-lead op amp pin-out.

I
For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-595

RC4207
Ordering Information
Part Number
RC4207FN
RC4207GN

Thermal Characteristics

Package

Operating
Temperature
Range

N
N

O°Cto +70°C
O°C to +70°C

Notes:

8·Lead
Plastic
DIP
Max. Junction Temp.
468mW
Therm. Res. eJC
Therm. Tes. eJA
For TA > SOOC derate at

18838 suffix denotes Mi~Std-883, Level 8 processing
N = 8-lead plastic DIP

1600ClW
6.2SmWIOC

Absolute Maximum Ratings
Supply Voltage .. ,........................................±18V
Input Voltage 1 .................................................±18V
Differential Input Voltage ..................•....•.•.••. 30V
Internal Power Dissipation2 ..................... 500 mW
Output Short Circuit Duration ............... Indefinite
Storage Temperature
Range ....................•.............. -65·C to +150'C
Operating Temperature Range
RC4207F/G ................................ O·C to +70'C
Lead Soldering Temperature
(60 sec) ............................................... +300·C

Connection Information
8-Lead

Dual In·Line Package
(Top View)

Notes:
1. For supply voltages less than ±18V, the absolute maximum
input voltage is equal to the supply voltage.
2. Observe package thermal characteristics.

Pin
1
2
3

3·596

Raytheon Semiconductor

Function
Output A
-Input A
+lnputA

4

-VS

5
6
7

+Input 8
-Input 8
Output 8

8

+VS

65-01782

For More Information, calI1-80D-722-7074.

RC4207
Electrical Characteristics
(Vs = ±15V. OOC S TAS +70'C unless otherwise noted)
4207G

4207F

Typ

Max

Input Offset Voltage
Average Input Offset Voltage Drift2

45
0.3

Parameters

Test CondHlons

Min

Input Offset Current

±2.0

Average Input Offset Current Drift

8.0

Input Bias Current

±2.0

Average Input Bias Current Drift

Typ

Max

UnHs

150
1.3

85
0.7

250

~V
~VlOC

±10

±1.S

±15

Min

12
±10

±3.0

13

nA
pAre

±15

nA
pAlO(;

18

±10

±13.5

±10

±13.5

V

Common Mode Rejection Ratio

VCM =±10V

94

120

92

10S

dB

Power Supply Rejection Ratio

Vs = ±4.0V to ±1S.5V

94

115

92

100

dB

large Signal Voltage Gain

Rl>2.0kD.
VOUT =±10V

200

450

75

400

VlmV

RL >2.0k!l

±11

±12.S

±11

±12.S

Input Voltage Range

Maximum Output Voltage Swing
Power Consumption

RL =00

150

240

150

V
240

mW

I
For More Information, calI1-80D-722-7074.

Raytheon Semiconductor

3-597

RC4207
Electrical Characteristics
(Vs =±15V. and TA =+25OC unless otherwise noted)
Parameters

Test Conditions

Min

4207B/F
Typ
MaX

Input Offset Voltage3

30

Long Term Vos Stability 1

0.2

Min

75

4207G
Typ

Max

Units

60

150

I1V

0.5

I1VlMo

Input Offset Current

±D.5

±5

±2

±10

nA

Input Bias Current

±0.5

±5

±2

±10

nA

Input noise Voltage

Input Noise Voltage Density

Input Noise Current

Input Noise Current Density

0.1 Hz to 10Hz

0.35

0.35

FO ·10Hz

10.3

10.3

FO .100 Hz

10

10

FO .1000 Hz

9.6

9.6

¥Z

0.1 Hzto10Hz

14

14

pAp-p

FO ·10Hz

0.32

0.32

Fo .l00 Hz

0.14

0.14

pA

Fo ·1000Hz

0.12

0.12

1HZ

60

31

MO

120

GO

Input Resistance (Ditt. Mode)
Input Resistance (Com. Mode)

200

Input Voltage Range4

I1VP-P
nV

±11

±14

±11

±14

V

100

126

94

110

dB

Common Mode Rejection Ratio

VCM -±11V

Power Supply Rejection Ratio

Vs .. ±4.0V to ±16.5V

100

110

94

104

dB

Large Signal Voltage Gain

RL ~ 2kn. VOUT " ±10V

400

600

250

400

V/mV

VOUT .±1.0V, RL .1Kn 200

400

100

200

±12.5

±13

±12.5

±13

RL~2kn

±12

±12.8

±12

±12.8

Vs ·±4.0V
RL ~ 10kn
Output Voltage Swing

V

RL ~ 1kn

±11

±12

±11

±12

Slew Rate

RL~2kn

0.1

0.3

0.1

0.3

VlI1s

Closed Loop Bandwidth

AvOL " +1.0

1.5

1.5

MHz

VOUT • O,louT - 0
VS -±15V, ~.oo

60

60

Open Loop Output Resistance
Power Consumption

VS" ±4.0V, RL _ ..
Crosstalk

126

150

200

35

50

155

126

0

160

240

48

64

155

mW

dB

Notes:

1.

2.
3.
4.

Long Term Input OIfset Voltage Stabiflly refers to the averaged trend fine 01 Vos vs. Time over extended periods after the
first 30 days 01 operation. Excluding the initial hour 01 operation, changes in Vos during the lirst 30 operating days are
typically 2.5I1V.
Guaranteed by design.
Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after
application 01 power.
The input protedion diodes do nel alow the device to be removed or inserted into the circuh whhout first removing power.

3-598

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4207
Typical Performance Characteristics
Input Offset Voltage vs. Temperature
85

_~S=±15V
R= 1000

75

~

50

.........

J
25

"""- -

o

o

-50

./

V
+100

+50

Input Bias Current vs. Differential Input Voltage
+120

I

+80 I-- At

Ci"

I I I I I I
IV DIFFI !tJ.5V ~ B I~3nA

E
.......

V
---'

0

./

ID

"+

V

-40
-80

""

i..,.;'

+40

-80

Vs= ±15V
TA= +25 0 C

I
-20

+20

Vs =±15V

6

-40

Ci" Ci"
o S. .s
+40

./

-120
-30

Input Bias Current vs. Temperature
-120

-!

4

~

2
+80
+120
+30

o

-50

+50

+100

65-0368

Input Offset Current vs. Temperature
2.5
2.0

.1

CMRR vs. Frequency
130

I

120

Vs=±15V

Ci"

.s

.J

1.5
1.0
0.5
0

-50

"

o

I

~

110

iii"
:2a:
a:

100

~

90

::E

0

80

I
70

60
+50

For More Information, call 1-800-722-7074.

+100

1.0

10

lK

100

"

10K

iii
~
lOOK

F(Hz)

Raytheon Semiconductor

3-599

RC4207
Typical Performance Characteristics
PSRR vs. Frequency
120

Open Loop Gain vs. Supply Voltage
1000

111111111 II

TA=+25°C -

TA = +25°C

110

800
100

iii"
~
a:
a:
fIl

I......
90

r-.

~

80

D.

~

J

I...... r-,

70

...

600

..........

'"

400
200

60
......

50
0.1

10

1.0

100

o

10K

lK

o

±S

Closed Loop Response for
Various Gain Configurations

Open loop Gain vs. Frequency

80

'"'"

100
Vs=±15V
T A= +25OC

iii"

..........

~

J

[\

100

lK

!

Vs=i15V TA= +25·C

'"

60

:!:!.... 40

-40
10

I

80

I"I'-..

o
0.1

20

f'..

-20

10K lOOK 1M 10M

o

lK

100

I I 1111

f--r-

1

20
16

~

12

.]

t;

8

'" --

10

100

!

10M

.!

10

p

1

+VOUT

....:: i-'r-

I
-Your

5

.....

1

1M

1

i--""Ii

4

o
lK

0.1

F(kHz)

3-600

_I

t-vs =±15V
T A = +25"C
15 t- VIN =±10mV

Vs =t15V
TA=+2B'C

~

o

""

lOOK

I'

Output Voltage vs. Load Resistance to Ground
20

~

J

10K

F(Hz)

Maximum Undistorted Output vs. Frequency
24

~

0

F (Hz)

28

±20

:tVs (V)

F(Hz)

120 f - -

!

±lS

±10

1.0

~

10

RL (kn)

Raytheon Semiconductor

For More Information, caJI1-800-722-7074.

RC4207
Typical Performance Characteristics
Output Short Circutt Current vs. lime

Power Consumption VS. Total Supply Vottage
60

1000

I--

TAm

-

+25"C

" """

o

..........

20

30

!

I

I

I

I

"'-.1

r-.....

2

I--Vs d:15V
+25"C
20

50

40

I

1. V IN (Pin 3) =-10mV. VOUT=+I5v2. VIN (Pin 3) = +10mV. VoUT =-15V

~

1/

10

1

50

i--'-

100

I

T,. -

o

3

2

4

TIme (Min)

Typical Applications

R4

Rl

10K

10K

Vlo-~VV~--'-----~~-----'

R2

+15V

10K

V2

0---'lN"'----"
R3

10K

>-~--.() "oUT

-15V
Rl =R2=R3=R4
65-0381

Adjustment-Free Precision Summing AmplHier
R4
10K

R3
10K

R3

Rl
Sensing
Junction

+15V

VIN

R1
10K

R5
10K

+15V

+ISV

01

±10V

I

6

Your

Reference
Junction

R2

02
-15V
R4

-15V

Rl = R2
R3

R2

R4
65-0382

10K

High Stability Thermocouple Amplifier

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

65-0383

Precision Absolute Value Circun

3-601

en
CO)

Co>

~

:::r

CD

3

OUlput A

<\Is

OutputB

(1)

(8)

(7)

a
n"

AmpllfierB 2
--,
Q)
rAmpjifiTrA-------------------------- i l l
~

II

~R2B

-R!I

Z2 I
1RIE0- 0- -r
"'-'~
Z4
136.61( RID 0- - r - RIC RIB
11 15.7K
5.31<
5K

I

I
ffl
3

(2)

g"
Co

.

g
~
§=
iil

I

.~

-i~
~

Cl
:;;!

+1(;fA

~
.75 .25

034

r

11
I..,
1 053

R21

188

033

~

~J'F

.

450

~I032r 035

~3
750
750

R24

01

I

R25

1

200

R4

as

200

D2

al

02 ..,

2X

2Xf'

I..,
, .... as

7~fF

lOOK

11

047

04

~...

R22~ ~;

2X'1"
Rl: [Rl..1

32K,!

84

I"

360

....

'-

I .. .
01~
015

R17
20

r-~
RIB

010"

~ as

011-t:013

019>F-::

1 Q38~7
=1- '1
.33 .6
1
a51
1
' 5000 derate at

Ordering Information
Package

Operating
Temperature

RC4227FN
RC4227GN

N
N

000 to +7000
000 to +7000

RM4227BD
RM4227BD1883B

0
0*

-5500 to +12500
-5500 to +12500

Part Number

8-Lead

Ceramic
Plastic
DIP
DIP
+17500
+12500
833mW
468mW
45OC/W
150"CIW
1600c/w
8.33mWIOC 6.25mWIOC

Bange

NOles:
/8838 suffIX denotes MiJ.Std-883. Level 8 processing
D • IHead ceramic DIP
N =IHead plastic DIP

3-604

Raytheon Semiconductor

For More Information. calI1-8O().722-7074.

RC4227
Electrical Characteristics

(Vs = ±15V, and TA:;; +25"C unless otherwise noted)
4227B/F

4227G

TYP

MaX

Input Offset Voltage3

20

75

Long Term Vos Stability 1

0.3

Parameters

Test Conditions

Min

Input Offset Current
Input Bias Current
Input noise Voltage

Input Noise Voltage Density

Input Noise Current Density

Min

TYP

MaX

30

150

0.4
±10

±5

±15

±5

±15

±7.5

±25

O.OS

O.OS

Fo -l0Hz

3.S

3.8

Fo -30Hz

3.3

3.3

Fo -l000 Hz

3.2

3.2

Fo -l0Hz

1.7

1.7

I1V
I1VlMo

±2.5

0.1 Hzlol0Hz

UnHs

nA
nA
I1VP-P

nV

--

"I'IZ

Fo- 30 Hz

1.0

1.0

Fo ·l000Hz

0.4

0.4

Input Resistance (Dill. Mode)

5.0

4.0

"Iir

Input Resistance (Com. Mode)

2.5

2.0

GO

pA

MO

Input Voltage Range2, 4

±11

±12.3

±11

±12.3

V

Common Mode Rejection Ratio VCM -±IIV

104

123

100

120

dB

Power Supply Rejection Ratio

Vs - ±4.0Vlo±16.5V

104

120

100

lIS

dB

large Signal Voltage Gain

RL~2kn,

500

1000

400

800

VlmV

400

800

300

600

RL~ 1.0kn

250

500

200

400

VOUT -±10V

VOUT - ±10V, RL -11«1,
VOUT -±1.0V, VS. ±4.0V
Output Voltage Swing
Slew Rate 2

RL~2.0kn

±12

±13.S

±12

±13.S

RL ~ lkn

±11

±12

±11

±12

RL~2.0kn

1.5

2.7

0.1

0.3

V/l1s

5.0

8.0

5.0

8.0

MHz

70

0

Gain Bandwidth Product
Open Loop Output Resistance

VOUT - 0, lOUT - 0

Power Consumption

RL--

Crosstalk

70
160
126

200

155

180
126

V

240

155

I

mW
dB

Notes:
1. Long Term Input Offset Voltage Stability refers to the averaged trend fine of Vos vs. Time over extended periods after the
first 30 days of operation. Excluding the initial hour of operation, changes in Vos during the first 30 operaling days are
typically 2.5 IlV.
2. Guaranteed by design.
3. Input Offset Voltage measurements are per10rmed by automated test equipment approximately 0.5 seconds after
appHcation of power.
4. The input protection diodes do not allow the device to be removed or inserted into the circuit without !irst removing power.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-605

RC4227
Electrical Characteristics
(VS =±15V. -55'C S TAS +125'C unless otherwise noted)
42278
Typ

Max

Units

Input Offset VoHage 1
Average Input Offset VoHage Drift;!

50
0.3

200
1.3

(.lV
(.lVrC

Input Offset Current

±10

::1:35

nA

Input Bias Current

±15

±45

nA

Parameters

Test COnditions

Min

Input VoHage Range

±10

±11.5

V

Common Mode Rejection Ratio

VCM =±10V

100

119

dB

Power Supply Rejection Ratio

VS • ±4.0V 10 ±16.5V

100

114

dB

Large Signal VoHage Gain

RL ;?;2 kD, VOUT =±10V

350

650

VlmV

Output VoHage Swing

RL;?;2.0kn

±11

±13.2

V

Power Consumption

RL =00

200

280

mW

NOles:
1. Input offset voltage measurements are performed by automated tes! equpment approximately 0.5 seconds after
appDcation of power.
2. This parameter is tested on a sample basis only.

Electrical Characteristics
(Vs = ±15V. O°C S TAS +70'C unless otherwise noted)
4227G
Typ

Max

UnHs

85

250

(.lV

4227F
Typ

Max

Input Offset VoHage

45

150

Average Input Offset VoHage Drift2

0.3

1.3

0.4

Input Offset Current

±B

±15

±10

::1:35

nA

Input Bias Current

±10

±30

±15

±45

nA

Parameters

Test COndHlons

Input Voltage Range

Min

±10

Min

JlVfOC

±11.8

±10

±11.8

V

Common Mode Rejection Ratio

VCM=±10V

100

121

92

118

dB

Power Supply Rejection Ratio

Vs = ±4.0V 10 ±16.5V

100

116

92

114

dB

Large Signal VoHage Gain

RL>2.0kD,
VOUT=±10V

350

700

250

500

V/mV

Output VoHage Swing

Rl>2.0kn

±11

±13.5

±11

±13.5

V

Power Consumption

RL =00

200

280

mW

3-606

180

240

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC4227
Typical Performance Characteristics
0.11'F
100K

22fl'F

~pe

RIN -1M

110K

-=

Notes:
1. Peak-to-peak no/se measured In a 10-second InteNal
2. The device under test should be warmed up for 3 minutes and shielded from air currents •
3. Voltage gain - 50,000.

65-0003

0.1 Hz to 10Hz Noise Test Circuit (112 Shown)

0.1 Hz to 10Hz Noise Gain vs. Frequency
100
90

80

130

.-

110

"\\

~~

iii"

70

C

80

.c

~

Test Time 0110 Sec Further
50 r- UmilS Low Frequency (<0.1 Hz)
GaIn
40
30
0.01

1.0

70

""-........

50

........

I

-10

100

10

" f"..

10

1

10

100

1K

20
16

iii"

10

C

5

:g.

"'"

o
-5

-10

ts 1±1~J I

1

T,,-+25"C
II

"

\

-70° \

,

"

10

~

r\

10K lOOK

'" 1"'0..

1M

10M 100M

F(Hz)

Slew Rate, Gain Bandwidth Product,
Phase Margin vs. Temperature

Gain, Phase Shift vs. Frequency

~.
~Av

r-.....
........
f"..

F(Hz)

25

.......

30

IIIIIII IIIIIII II
0.1

""-........

90

iii'

:eo

-

Open Loop Gain vs. Frequency

80
100
120
1

!
I

~

a:

II)

220
100

60

9

50

i-SL

~

2
-75

-50

I

Vs _+15V

GB~

3

I

10
I

~

4

1
1

'Mr-

70

- --

;--

~

-25

0

25

50

75

6
100 125

F(MHz)

For More Information, caD 1-800-722-7074.

Raytheon Semiconductor

3-607

RC4227
Typical Performance Characteristics (Continued)
Maximum Output Swing vs. Load Resistance

Supply Current vs. Total Supply VoHage
10

18

8

....

--

,

,.~

.

L..--

14 I - -

TA _+125°C

I--

i.--

T~=+25';"" ~

4

16

.1

-

12

€

-..-

4

TArSSOC

~
, / I.....

10

J :V/

~ I--

+VCAJT

/

-Voor

,

Vs -:t15V
TA-+25"C

2

I I I I

o
-2

2

15

5

45

35

25

I

o

10

1.0

+V.to-V.M

RdkO)

Open-Loop Gain vs. Total Supply Voftage

Short Circuit Current vs. llme
60

2.5

50

2.0

I

TA-+25oC

-

1
.:J

40

"["-..

30

........

--

Vs-tl5V
TA-+25"C

'sc(+)

-

!i

1.5

J

1.0

~

VRL-1kO

0.5

20
10

;~
/

~

'sc(-)

--~

"
RL-2~

o

2

3

4

o

5

o

±10

TIm. (MIn)

±15

±2D

:tV. (V)

Common-Mode Input Range vs. Supply Voftage

Maximum Undistorted Output vs. Frequency

16~----~------~----~----~

12~----~------~~~~~--~
8~----~--~~~~-

€

J

4~----~~~--~----~----~

o~--~~------~----~----~
-4~----=::~~c:---~=

~~----~--~~~~--~----~

-12
:!
-16 L - - _ - - L . ._ _..1..-_--'-......::....;:...;;.....,J ~

o

15

110

:t15

120

:tV. (V)

3-608

Raytheon Semiconductor

For More Information, caD 1~o-722-7074.

RC4227
Typical Performance Characteristics (Continued)
Op Amp Comparison
Input Noise Voltage Density vs. Frequency

Input Noise Voltage Density vs. Frequency
100

10
Vs-!;1SV
TA-+2SoC

~

.....
......

741

~

I!SO

i',

:-::-.

[A:-

.s.

\

11', 1'-0.

~'!Io,~Corner

_

10

Uti

lciwNoise
Audio

OpAmp

ii=4277

z

II

11F Comer - 2.7Hz

r-..

,,

1IFComer

"' 1"0.
....

1/F Corner 2.7 Hz
,::.strumentatlon Range 10 DC Audio Range 10 20 kHz

1
1

1

10

100

1000

1

100

10

F(Hz)

1000

F (Hz)

Input Noise Current Density vs. Frequency
10.0

'01<".

~

I"
t--

I 'OQ~
.....

10

. ..... I eno"
In -

+

(130 nV)']'·

'"

~

I I
1K

100

ano

lMxl00

1/F Comer 140 Hz

I III WI

0.1

500K

10K

F (Hz)

I
For More Information. call 1-800·722·7074.

Raytheon Semiconductor

3·609

en
(')

Co)

~

::::J"

o

(I)

3

Qu1putA
(1)

+'Is

~
(')

Qu1put B
(7)

(8)

Amplifier B C

--,

r~plif~A--------------------------rt

J

I --R!l
I 0- ~
I
......
Rle
~

112.11<:

!
CD

o

:s

fC

3

ao

-Input"
(2)

5.
c

...g
a'

~

~
3
~
;>
~
~

~
~

C3

;i>!

+Input"
(3)

I
I
I
I
I
I
II

Rl0
5.5K

0-

.25K
Z4
~

R1C
5.3K

R1B
lK

~
025

R2A

~

....
029

30pF

R20
188

'-1033

'" 034

....

450

. '"

~1r-..Q35

r-..

n

R27
R29
2K

.. 05

R4

750

50

I' 08

Q2 .....

2Xr

",...~-t::::018

.....014
C2B

R15

20
R29

84

...

r-..

380

Q7

_

C3

R5
30K

75pF

*02

R18
1.5K
;

r-

",0_23
03......

04

010.....

IV

-r;-r

~7 ~21 ~

020.....

011...J:;:013

Rl"
10i('

R22
32K

R1J R13

Ir-

022

C¥l
fI

R23
10K

R8
200

R7
200

R8
2K

R9
50

Rl0
180

fir

Q42

R2B
lK

039

040
R30

I

800
R31

I

375

II

I
~--------------i--------------_J
(4)
-VB

I
I
I
I
I

I l.... l... I I ;,)

I L.;..J

2X~""
Rl1
161{

V"-ii-1-1

20

as

5KL~

I

I

II
R17
II
1--1R18
I

hkQ55

.!:'

I
I1

018
015

.
."- L " ' 0 1
.....7

012

I I

053'::!

019~ II I hlW

D3

~

f-

I
I

I
I

20

I I

1
R32
lOOK

II

~

..

12K

I
I
I
I
I

R21

Q6:!
·'L

r---

... 01

R19
250

024~
.75 .25

~Cl

Rl"
15.5K

*01

I
.)031

029 030

~Z3

""l2X

I
I
I
I
I
I
I
I

JJ
LJ.

R2B
lK

R2C

I

045

-K

~

041

~
Q43

Q44

I
I
I

iii"

I ~
I 3
I
I
I
I
I
I
I
I -I"""B

~

I
I~B
(5)

I
I
I
I
I
I
I
I
I

~_J

65-2662

~

§

RC4277
RC4277
Dual Precision Operational Amplifier
Description

Features

The RC4277 provides the highest precision available
in a dual bipolar operational amplifier. A monolithic
dual version of the RC4077. the RC4277 is designed
to replace OP-07 and OP-77 type amplifiers in
applications requiring high PC board layout density.
The RC4277 has a well-balanced. mutually supporting
set of input specifications. Low Vos. low lB' high
open-loop gain. and excellent matching characteristics
combine to raise the performance level of many
instrumentation. low-level Signal conditioning. and
data conversion applications. PSRR. CMRR. Vos
drift. and noise levels also support high precision
operation.

•
•
•
•
•
•
•
•
•

High DC preCision
VerylowVos-30~V

Very low VOS drift - 0.3 ~vrc
High open-loop gain - 5000 V/mV
High CMRR -120 dB
High PSRR -120 db
Low noise - 0.35 ~VPop (0.1 Hz to 10Hz)
Low input bias current - 3.0 nA
Low power consumption -140 mW

The high performance of the RC4277 results from two
innovative and unconventional manufacturing steps.
plus careful circuit layout and design. The key steps
are SiCr thin-film resistor deposition and post-package
trimming of the Input offset voltage characteristic. The
low 75 ~V max VOS specification is maintained in
high-volume production by way of the post-package
trim procedure. where internal resistors are trimmed
through the device input leads at the final test
operation. Devices retain this low offset through the
stability and accuracy of the trimmed thin-film
resistors.
The RC4277 is available in 8-lead plastic and ceramic
DIPs.

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-611

RC4277
Ordering Information

Thermal Characteristics

Package

OperatIng
Temperature
Range

RC4277FN

N

O'Cto +70'C

RV4277FD

D

-25'C to +85'C

Part Number

Notes:
/8838 suffix denotes Mil-Std-883, Level 8 processing
N - 8-lead plastic DIP
D _ 8 lead ceramic DIP

B-lead
CeramIc
DIP

B-lead
Plasllc
DIP

Max. Junction Temp.

+175'C

+125'C

Max. Po TA <50'C

833mW

468mW

Therm. Res 9JC

45'CIW

-

Therm. Res. 9JA

150'c/w

160'C/W

For TA >50'C Derate at 8.33mWrC 6.25mWrC

Connection Information

Absolute Maximum Ratings
Supply Voltage ....................................................:t!2.2V
Input Voltage1 .....................................................:t!2.2V
Differential Input Voltage .......................................30V
Internal Power Dissipation2 ............................ 500 mW
Output Short Circuit Duration ........................ Indefinite
Storage Temperature
Range ............................................-65·C to +150'C
Operating Temperature Range
RV4277 ............................................-25·C to +85'C
RC4277 .............................................. O·C to +70'C
lead Soldering Temperature
(60 sec) ....................................................... +300·C

B-Lead
Dual In-LIne Package
(Top View)

Notes:
1. For slWiy vohages less than jfl2V, tha absolute maximwn illlUl
voltage is equal to the slWlY voltage.
2. Observe package thermal characteristics.

3-612

Raytheon Semiconductor

Pin Function
1 Output A
2 -Input A
3 +lnputA
4

-Vs

5
6
7

+Input B
-Input B
OutputB

8

+Vs

65-01782

For More Information, call 1-800-722-7074.

RC4277
Electrical Characteristics
(Vs = ±15V and TA = +25'C unless otherwise noted)
Typ
30

Max
75

Input Offset Voltage Match

25

150

Long Term VOS Stabilityl

0.3

Parameters
Input Offset Voltage;'

Test CondHlons

Min

Input Offset Current
Input Bias Current
Input Noise Voltage

0.5

5.0

nA

±S.O

nA

0.1 Hz to 10 Hz

0.35

FO= 10 Hz

10.3

Fo= 100 Hz

10

Fo = 1000 Hz

9.6

Input Noise Current

0.1 Hz to 10Hz

14

Fo = 10 Hz

0.32

FO=100HZ

0.14

Fo= 1000 Hz

0.12

Input Voltage Range2 , 4
Common Mode Rejection Ratio

VCM =±11V

Power Supply Rejection Ratio

Vs = ±4V to ±16.5V

Large Signal Voltage Gain

RL~2kn,

Slew Rate

PAp-p
pAl...JRZ

±11

±14

V

110

132

dB

132

dB

3500

V/mV

±12.5

±13

HL~2 kll

±12

±12.8

1 k11

±11

±12

RL~2kn

0.1

VOUT =±10V

10kn

AVCL = +1.0

upen Loop Output Resistance VOUT - 0, lOUT - 0
Power Consumption
Vs =±15V, RL =00
Crosstalk

nV/...Jrrz

110

HL~

Closed Loop Bandwidth

J.1Vp-p

1300

RL~

Output Voltage Swing

J.1V
J.1VlMo

±0.5

Input Noise Voltage Density

Input Noise Current Density

UnHs
J.1V

0.3

V/J.1S

0.8

MHz

60

n

60
126

V

150

100

mW
dB

NOles:
1. Long Term Input Offset Voltage Stabirlly relers to the average trend line of Vos vs. lime over extended periods after the first 30 days of operation.
Excluding the ilttial hall' 01 operation, changes in Vos during the first 30 qJElrating days are typically 2.5 IlV.
.
2. Guaranteed by design.
3. Input Offset Voftage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
4. The input protection diodes do not anow the device to be removed or inserted into the circun wtthout lirst removing power.

For Mare Information, call 1-800-722-7074.

Raytheon Semiconductor

3-613

I

RC4277
Electrical Characteristics

(Vs = ±15V, O'C ::; TA::; +70'C for plastic packages unless otherwise noted)
Parameters

Test CondHlons

Input Offset VoHage

O'C S TA S +70'C
-25'C S TA S +85'C

Min

Typ

Max

UnHs

50
50

120
135

J,LV
J,LV

Average Input Offset
VoHage Drilt2

0.3

1.0

J,LVrC

Input Offset Current

1.5

5.0

nA

±1.5

±5.0

nA

Input Bias Current
Input VoHage Range

±10

±13.5

V

Common Mode Rejection
Ratio

VCM =±10V

110

124

dB

Power Supply Rejection
Ratio

Vs = ±4V to ±16.5V

110

124

dB

Large Signal Voltage Gain

RL > 2 1<0, VOUT = ±1 OV

1300

3000

VlmV

Maximum Output VoHage
Swing

RL >2 1<0

±11

±12.6

V

Power Consumption

RL =00

70

120

mW

NOles:
1. Input offset vottage measurements are performed by automated test equipment approximately 0.5 seconds after appRcation of power.
2. This parameter is tested on a sample basis only.

3-614

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4277
Typical Applications
R3

Rl
R4
10K

Rl
10K

Sensing
Junction

VI
+15V
V2

Reference
Junction

R3
10K

VOUT

V3

RS
2.5K

-15V

R3
-

65-4232

V 1N

Rl
10K

6S-4233

High Stability Thermocouple Amplifier

Adjustment-Free Precision Summing Amplifier

R3
10K

R4

R4
10K

R5
10K

+15V

±10V

7

Vour
OV to +10V

02

R2

10K

-15V

65-4334

I

Precision Absolute Value Circuit

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-615

(J)~

c.>

~

~(1
§~

OJ

Z2
+Vs

lJ~~

(8)

zkJR1E
900

r

I

R1H
2.2K

~C

Z2(1 7.2K
Z1

~F

--m-

Z3

~

5K

t~lA
15K

lX
R2C
3.5K

~~

010
2X

05:::!J
lX

Q42

R2G
5K R2F
30K

30K
R1J
20K

R2E
1.71<

"-4X

.......

~
Al ';OOpF
Cl

Z4

r

03~
I""

o

1 t~

::I

W
3

g'

031

&.

c

.

g,

o

g.
p
~

~

"
o

~

,0'1~:

028 027

A21

A (2)

~

~
3

032

~~ -

R18
1.5K

039

01~O12

Q40

1(6)

RSA

~

~Dl

3K

25p,:

-

JQ20

~'022

"

R98
3K

....

1

1#028
·"VPNP

1?
0102
4X

014
~4

2X

R19
700
1#'041

-r-.

,....

03"
R4
10K

Rl2A
5.75K

-r--

R22
500

A(l)

04"

....
R3
10K

(7)

Rl0l
500K

:::7

=~2B

33 pF

500

+Input
A(3) B (5)

~nput

;r

=~

~,~~l{
030

~;.

50pF

R28

3.3K

CD

CUI put

.--

"'06

l..
034!"'1

C2A

~

R16
30

~.2K

........

~

023

R2J
R2A
75K

2-....J
Q)

2~~~

019

Vas

~::r

018

n' -....J

J

I
A2H
2.2K

015

~

~8

R8
ReA
2.51<: 10K

V 017

r

R8B
10K

~~2B
815

R12C
1K

67
R102
140K

~3

230

~i

-Vs
(4)

65-4235

One Section of Two

103

RC4277
Typical Applications

RS

R2

SOK

SK

R3

SK

>---oVoor

R1

SOK

R4

SK

SK

SK

':'
(+)

R1 -RS.10 R2
R2 .. R3
R4.RS

..

Av·B!
RS
Note: This circuit can tolerate input voltages that
exceed the 4277's supply voltage rating as long as
the slew rate do not exceed the op amp's slew rate.

65-4427

High Voltage Differential Amplifier

R1
Aln

R

X

R3POT
Position

xR3
Vour ·2(2X-1)

65-3062

65-4428

Polarity Changing Gain Controlled Amplifier

For More Information, call 1-800-722-7074.

I

Gain Controlled Amplifier Transfer Function

Raytheon Semiconductor

3-617

RC4277
A3

Al

10K
10K
(+) O--Jl.fI/v-..----'Wr----'1

V IN

(-)

O!_/\Jl~VK\,- _Nl~V~\,_
___

......._ <

1---+----0 lour

A3-A4
Al-R2
A3
lOUT - -V IN (AlAS)
Al
Input Vo~age Aange = A3 (+Vs -l.SV)

65-4429

Differentia/Input Current Source

R2

VOUT
AG - Optional Gain Adjust

A2
Av --(m+ l )

-lSV
65-4430

High Input Impedance Subtractor

3-618

Raytheon Semiconductor

For More Information, calI1-80D-722-7074.

RC4277
R1A

R2A

Voor

R1B

Va -

~=~X=~)

R3

R2B

(V2 - V1)

Note: This circuit provides a linear relationship
between the R G potentiometer setting
and circuit gain.

Difference Amplifier with Linear Gain Control

R3A
R1
V1

R4A

20K

>--+--0 VOUT

RG
V2

20K
R2

R3B

R4B

I

Note: The driven shield will reduce the effects
of cable capacitance on ac CMRR.
65-4432

Three Op Amp Instrumentation Amplifier with Driven Shield

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-619

RC4277
RM42n SPICE Macro Model
This circuit models AC and DC characteristics including slew rate. bandwidth. Vos.ls.IOS' CMRR. output voltage range.
and gain. The circuit produces typical values for these parameters.

(5)

F.,...
V.IAS

Re,

RB,
(1)

RC2

8.SK

D.5

8.SK

(11)

500

F....,

D.
D.

V.IAS
0.5

Cl
(12)

Dp
D.

8pF
(6)

C2
20PF

VLN
OV

(7)

(8)

Ro,

(4)

80

(2)

R..
500

g~
F.

(21)

(0)

(40)

Roo
30

D.
D.

H...
-

VLN

1.0

(30)
(3)

85-4447

3-620

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC4560
RC4560
Wide-Bandwidth Dual Operational Amplifier
Features

Description
The 4560 integrated circuit is a high-gain. widebandwidth. dual operational amplifier capable of
driving 20V peak-to-peak into 4000 loads. The 4560
combines many of the features of the 4558 as well as
providing the capability of wider bandwidth. and higher
slew rate makes the 4560 ideal for active filters. data
and telecommunications. and many instrumentation
applications. The availability of the 4560 in the surface
mounted package allows the 4560 to be used in
critical applications requiring very high packing
densities.

•
•
•
•
•
•
•
•
•
•

Unity gain bandwidth (Av = 1) - 10MHz
Slew rate - 4.0 V/~
Noise voltage at 1kHz - 7.0nVNRi
Noise voltage current at 1kHz - O.4pMflz
±10V Output Into 4000 loads (f25mA)
Supply current per amplifier - 1.8mA
Input offset voltage - 2.0mV
Input offset current - 5.0nA
Unity gain frequency compensated
Output short circuit protected

I
For More Information, calI1.aoo-722-7074.

Raytheon Semiconductor

3-621

RC4560
Connection Information

Ordering Information

8-Lead
Dual In·Llne Package

(Top View)

Part Number

Package

Operating
Temperature
Range

RC4560M
RC4560NB

M
N

·20°C to +75°C
·20°C to +75°C

Notes:
N: 8..Jead plastic DIP
M - 8-lead plastic sole

Absolute Maximum Ratings

65-0.210

Pin
1
2
3
4

5

6
7

8

Supply Voltage ••••••••.•.•.••••••.•.••.••.••••••.••••••• ±18V
Input Voltage1 •••••••••••••••••••••••••••••••••••••••••••• ±15V
Differential Input Voltage ........................... +30V
Output Short Circuit Duration2 ••••••••••••• Indefinite
Operating Temperature
Range ............•.•...............•... ·20·C to +75'C
Lead Soldering Temperature (10 Sec)
RC4560NB ....................................... +300·C
RC4560M ••••••••••••••••••••••••••••••••.•••.••• +260°C

Function
A Output
A·lnput
A+lnput
+VS
B +Input
B ·Input
B Output
·VS

Notes:
1. For supply voltages less than ±15V, the absolute
maximum input voltage is equal 10 the supply
voltage.
2. Short circuit may be 10 ground on one amp only.
Rating applies 10 +7S"C ambient temperature.

Thermal Characteristics
Small
Outline
SO-8

8-Lead
Plastic
DIP

Max. Junction Temp.

+125°C

+125°C

Max. Po TA<50'C

300mW

468mW

Therm. Res OJC

-

-

Therm. Res. 0JA

240°C/W

For TA >50'C Derate at 4.17 mWI"C

3-622

160°C/W
6.25mW/oC

Raytheon Semiconductor

For More Information, calI1.aoo-722-7074.

RC4560
Matching Characteristics
(Vs =±15V. TA = +25"C)

Parameter

Conditions

Typ

Units

f\~2k.a

±1.0

dB

Input Bias Current

±15

nA

Input Offset Current

±7.5

nA

Voltage Gain

I
For More Infonnation. caD 1-800-722·7074.

Raytheon semiconductor

3·623

RC4560
Electrical Characteristics
(VS= ±15V and TA= +25OC unless otherwise specified)
Parameters

Test Conditions

Input Offset Voltage
Inout Offset Current
Input Bias Current
Input Resistance (Differential Mode)
Large Signal Voltage Gain

RS~10kn

Output VoHage Swing
Inpul vonage Hange
Common Mode Rejection Ratio
Power Supply Rejection Ratio
power consumption
Transient Response
Rise Time
Overshoot
Slew Rate
Channel Separation
Unity Gain Bandwidth

Rl:c:.
~

J

~
400K

200K

+10

+20

+30

+40

160

............
~

rf 140

fL=2k Q

I--.

I

V~.±15V

180

600K

+50

+60

II)

120

~

100

+70

o

+20

+30

+40

~

~
+50

+60

+70

TA(OC)

TA (OC)

For More Information, call 1-800-722-7074.

+10

--- -

Raytheon Semiconductor

3-625

RC4560
Typical Performance Characteristics

(Continued)

Typical Output Voltage as a Function
of Supply Voltage

Output Voltage Swing as a Function
of Load Resistance
28
26
24

~

~
t::

.]

~~--~--~--~--~~~~

±6

±8

±10

±12

±14

±16

~

±18

1.--i-'

22
~
20
/
18
V'
16
/
14
12 1
10
8
0.1

~

1.0

+VJ-Vs(V)

Quiescent Current as a Function
of Supply Voltage
100

II~~ _I±~~V

I I 11111

I~~~WJ

TA -+25°(

J

!

60

oS

40

~

r-:

100

1K

10K

~

o

o

6

3

F(Hz)

28

~

J

20

9011 f-

16

J

I

8

o

I- -

10
8
6
4

~

I

12
4

"" -

II \

Vs -±15V TA -+25°C _
RL -2kn
CL -'00pF-

~

I

10% Rise Time

~

~
o

100

200

300

15

400

500

to

2
0

.}

-2

-4
·6
·8
·10

V:-±~5V [ -

TA -+25°C [ -

I--

I

i

I I\,

1

-

j

1

1

~

&.. - - -

o

Tima (ns)

3-626

9
12
:!:Vs(V)

Voltage Follower Large Signal Pulse Response

Transient Response
24

I

~

20

!iI
1M

100K

I

TA -+25°C_

80

RL .. 400n

o

10

RL(kn)

Output Voltage Swing as a Function of Frequency
40
36
32
c:- 28
c:;. 24
~ 20
16
12
8
4

-

·V&. i±1s1L
T - 25 C

Raytheon Semiconductor

4

12
8
Tima(ns)

16

For More Information. caD 1-800-722-7074.

RC4560
Typical Performance Characteristics

(Continued)

Input noise Current as a Function of Frequency

Input Noise as a Function of Frequency

100~~II~II~~~~II~~1I
Is;

t!

100

1l

Ii 10

1
.3

~

.s

Vs - :t15V
f--3!.,-I-H-HIlI--H-1+III- TA - +25°C KtltHi+++H-IHI

10 _ _ __

0.1

---~
~

L.....I-.J..U.I.I.IIL...L...u.L.L.UJL..I...I..l..L..U.III................LIJJIL...........u..uw

o

10

100

1K

10K

100K

F(Hz)

Channel Separation

Total Harmonic Distortion vs. Output VoHage

140

r---..

100

iD

:2-

l

80

B 60

Q

j!:

o

10

- Av=40dB

0.4

-

_f.lkHz
Rs= lkn

I

_Vsl= :t11v
R L -2K

I

II

0.3
0.2

40
20 -

0.5

-

0.6

120

!

Vs = :l:15V

TA=+~~~C

100

1K
F(Hz)

10K

.... /

0.1

o

1

100K

2

3

4

5

6

7

8

9

~

10

Distortion vs. Frequency

I

V~~ ~I~I~RMSI

0.6

Vs - :t30V

0.5

lO.4
~ 0.3

1\
\

0.2

./

0.1

o

10

100

1K

10K

~

100K

F(Hz)

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-627

RC4560
Schematic Diagram
+vso-________
_+----------~--------~----_+------~--~
(8)

R6
27

Output
(1,7)

120
+Inputs
(3,5)

01

R7
27

Q7

02
R2
5K

R4

SOK

-~O--~~~~----~----~--------~~----~----~~--_4--~
(4)

3-628

Raytheon Semiconductor

For Mora Infonnation, calI1-80D-722-7074.

RC4741
RC4741
General Purpose Operational Amplifier
Description

Features

The RC4741 is a monolithic integrated circuit,
consisting of four independent operational amplifiers
constructed with the planar epitaxial process.

•
•
•
•
•
•
•
•
•

These amplifiers feature AC and DC performance
which exceed that of the 741 type amplifiers. Its
superior bandwidth, slew rate and noise
characteristics make it an excellent choice for active
filter or audio amplifier applications.
A wide range of supply voltages (:t2V to :t20V) can be
used to power the RC4741 , making it compatible with
almost any system including battery powered
equipment.

Unity gain bandwidth - 3.5 MHz
High slew rate - 1.6 VIpS
Low noise voltage - 9 nV/--MZ
Input offset voltage - 0.5 mV
Input bias current - 60 nA
Indefinite short circuit protection
No crossover distortion
Internal compensation
Wide power supply range - :t2V to :t20V

Applications
•
•
•

Universal active filters
Audio amplifiers
Battery powered equipment

I
For More Information, call1.soo-722-7074.

Raytheon Semiconductor

3-629

RC4741
Connection Information

Ordering Information

RC4741M
RC4741N

M
N

Operating
Temperature
Range
O·C to +70·C
O°C to +70°C

RM4741D
RM47410/883B

D
D

-55°C to +125°C
-55°C to + 125°C

Part Number
14-Lead Dual In-Line Package
(Top View)

Package

Notes:
IB83B suffix denollls Mil-Std-883. Level B processing
N -14-lead plestic DIP
D = 14-1eadceramic DIP

M • 14-1eed small oudine

Absolute Maximum Ratings
65-0418

Pin Function
1 Output (A)
2 -Input (A)
3 + Input (A)
4 +Vs
5 +Input (B)
6 -Input (B)
7 Output (B)
8 Output (C)
9 -Input (C)
10 +Input (C)
11 -Vs
12 +Input (0)
13 -Input (0)
14 Output (0)

3-630

Supply Voltage ...........................................±20V
Differential Input Voltage ..............................30V
Input Voltage1 ..............................................................................±15V
Output Short Circuit
Duration2 ............_.._ .... _ ........................................... Indefinite
Storage Temperature
Range ................................. -65°C to +150°C
Operating Temperature Range
RM4741 .............................. -55°C to +125°C
RC4741 ................................... O°C to +70°C
Lead Soldering Temperature
(60 Sec, DIP) ....................................+300°C
(10 Sec, SOIC) .................................+260·C
Notes:
1. For supply voltages less than ±15V, the absolute
maximum input voltage is equal to the supply voltage.
2. Short circuit to ground on one amplifier only.

Raytheon Semiconductor

For More Information, call HIOO-722-7074.

RC4741
Thermal Characteristics
14-Lead
Small Outline
Max. Junction Temo
Max. Pn TA,50OC
Therm. Res 6JC
Therm Res. 6.Jc
For TA > 500C Derate at

-

14-Lead
Ceramic
DIP
+175OC
1042mW
SO"CNI

1S0"CIW
S.25mWfOC

S.3SmWfOC

14-Lead
Plastic
DIP
+125OC
46SmW

+125OC
300mW

-

200"CNI
5.0mWfOC

120"CNI

Electrical Characteristics

(Vs = ±15V and TA = 250C unless otherwise specified)

RM4741
Parameters
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Large Signal
Voltage Gain
Input Voltage Range
Output Resistance
Output Current
Common Mode
Rejection Ratio
Supply Current
(All Amplifiers)
Transient Response
Rise Time
Overshoot
Slew Rate
Unity Gain Bandwidth
Power Bandwidth

RC4741

Test Conditions
RsS10kn

Min

Typ

Max
3.0
30
200

RL 2: 2kn
VOUT ±10V

50

0.5
15
SO
0.5
100

±12
VOUT±10V

:1:5

RSS10kn
!N =:1:5

SO

For More Information, call1-80Q-722-7074.

Typ

Max
5.0
50
300

25

1.0
30
SO
0.5
50

±12
300
±15

:1:5

5.0

dB
5.0

75
25
1.S
3.5
25

75
25
l.S
3.5
25

9.0
108

9.0
108

Raytheon Semiconductor

Units
mV
nA
nA
Mn
V/mV
V
n
mA

300
±15

SO
4.5

VOUT = 20Vp-p
RL =2k
Input Noise Voltaae Density F=1kHz
Channel Separation

Min

7.0

I

mA

nS

%
VluS
MHz
kHz
nV/VHz
dB

3-631

RC4741
EI~lcal Characteristics
(VS =±15V, RM =_55° CgAs+125° C, RC = OOCSTA + 70OC)
RM4741

Parameters

Test Conditions

Input Offset Voltage
Inout Offset Current
Inout Bias Current
large Signal
Voltage Gain
Output Voltage SwIng

R~S10kn

Min

Max
5.0

RC4741
Typ

Min

Max
6.5
100
400

5.0

75
325
RL~2kn

Un"s
mV
nA

nA
VlmV

15

25

VOUT ±10V
RL~10kn

±12
±10

RI ;::2kn
Supply Current
(All Amplifiers)
Average Input Offset
Voltage Drift
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio

Typ
4.0

±13.7
±12.5
10

±13.7
±12.5
10

±12
±10

rnA

5.0

5.0
RsS10kn
!:N±5.0V
RSS10kn
!:N±5.0V

V

74

74

JlVlOC
dB

80

80

dB

Typical Performance Characteristics
Open Loop Gain. Phase vs. Frequency

PSRR VS. Temperature

11 0 ~RrTrmmrTITITlII"TTnmrnmnll"TTl1rmII"'TT
90 HtlllIIHiftlllll80
-NtHiHttlHllH+

iD
~

140

~1HR~-Hf!IHH+HHlI-I-HIHlH+!lIHllH+

100

70

120
0

45

60

J:

90

30
20
10

135

o

1

180

I---

100

~e

i

iD

80

a:
a:

60

~

+vs -

f--

-v -

r--

~ 40
20

o

-100 -75

-so

-25

o

!

+25 +50 +75+100+125 +150

TA (OC)

3-632

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC4741
Typical Performance Characteristics (Continued)
Channel Separation vs. Frequency
lOOK

-140
-120
-100

.>-<~o

iii' -80
:!!.

v0UT1

CS=20log( V0UT2

100 VOUT1

-60

fJ

-40

)

lK

-20

>-7-6--0 VOU12

lK

0
10

100

1K

10K

100K

FCHz)

Input Noise Voltage VS. Frequency

Transient Response vs. Temperature
1.3

35

1.4

p- 1.2

30

1.2

8. ~0 1.1

25

1.0

I
•

~

j

I--

......

1.0

Ii"
~

20 \.

0.8

s..

15

0.6 {

>:

J! ii 0.9

ii .~ 0.8
~z

tI 10

~ I"-.....

en

5

r-....

INI

.... 0.7

0.6
-100 -75 -50 -25

'\ ~

10

100

1K

-11
a::.tI

en ii
~

~ 1.1

11

S 1.0

10

1~

...

+1

!

'"V "

.........

,/

9
8

-50

-25

i'..

o

+25

+50

!

+75 +100 +125

0.9

V

0.7

±15

±20

SR&BW

I

i/
o

TA COC)

For More Information, ca\11-800-722-7074.

-

~

~ 0.8

!Ji

BW

V

!

BW- ~ f-

SR

100K

Slew Rate, Bandwidth VS. Supply Voltage

12

+

;=0
m-

10K

F CHz)

Slew Rate, Bandwidth VS. Temperature

°It)
N

0.2

o

TA ("C)

u

0.4 ~

o
0 +25 +50 +75+100 +125 +150

@'

±2

±5

±10

I

+VsI-VsM

Raytheon Semiconductor

3-633

I

RC4741
Typical Performance Characteristics (Continued)
Small Signal Phase Margin, Unity Gain
Bandwidth VS. Load Capacitance
70
7
IIII
60 ~ c[>M

11111

1~~1~2~

6

50

e.
i 30
i40

N"

4

I"-

~

" ':I~II
'l'I+4.I
100

1K

;=

..

I.IUII

I

I

=t5V

1111111

I'

I

L = Open
=,CL =50pF

100K

0.1

!

J 11111111 I III

100

65-0786

CL (pF)

I

=R

o

10K

Vour p.p = 8V Vs
I

t- VOUTP.p = 2V Vs = ±2V

8
> 1.0 § I(JOIW~~I~oll~w~r!

III
==

2

:=

~

Vs -t15V

VOUT p.p = l8V Vs = tl0V

10

€

:E:

3

10
10

30 =VOUTP.p=28V

5

20

o

Output Voltage Swing vs. Frequency

1K

10K

100K

1M

F(Hz)

Input Bias, Offset Current vs. Temperature

140

140r--r-.--.--.-'--~-r~.-'--'

120

120 t=t=j:2f=:~~f=~~H

_100

1 80
.J
~

CMRR VS. Temperature

60

~

--!B

m

20

80r-~~--+-~~--+--r~r-~-i

~

60~~-+--+-~~--+--r~r-+-~

a:

40

-

lor

o

100r-~~--+-~~--+--r~r-~-i

~

40r-~~--+-~~--+--r~r-~-i

20r-~~--+-~~--+--r~r-~-im

/

o

·100 ·75 ·50 ·25

·100 ·75 ·50 ·25 0 +25 +50 +75+100+125+150

~

0 +25 +50 +75+100+125+150
TA (Oc)

TA eC)

Output Voltage Swing VS. Load Resistance

30
"...

25

€

V

20

~

15

J

10

5

o

V
I'

100

3·634

1K

10K

Raytheon Semiconductor

!

100K

For More Infonnation, call 1-800·722·7074.

RC4741
Schematic Diagram (1/4 Shown)
+Vs
(4)

~____~________~Q~3~____~r-

____

~~Q1

(2,6,9,13)

-Input

0-------+------,
(1,7.8,14)

Output
R8
20
R8
50

F1

To Next

Amplifier

R7
20

Q6

01

R2
10K

-Vs
(11)
65-0778

I
For Mora Information, caD 1-800-722-7074.

Raytheon Semiconductor

3-635

RC4741

3-636

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC5532/5532A
RC5532/5532A
High Performance Dual Low Noise Operational
Amplifier
Description

Features

The 5532 is a high performance, dual low noise
operational amplifier. Compared to standard
dual operational amplifiers, such as the RC747,
it shows better noise performance, improved
output drive capability, and considerably higher
small-signal and power bandwidths.

•
•
•
•
•
•
•
•

This makes the device especially suitable for
application in high quality and professional
audio equipment, instrumentation, control
circuits, and telephone channel amplifiers. The
op amp is intemally compensated for gains
equal to one. If very low noise is of prime
importance, it is recommended that the 5532A
version be used which has guaranteed noise
specifications.

For Mora Information. cal1~722-7074.

Small signal bandwidth -10 MHz
Output drive capability - 6000.. 10 VRMS
Input noise voltage - 5 nVNHz
DC voltage gain - 50,000
AC voltage gain - 2200 at 10kHz
Power bandwidth - 140 kHz
Slew rate - 8 VIpS
Large supply voltage range - .yJV to :fQOV

Raytheon Semiconductor

3-637

RC5532/5532A
Connection Information

Ordering Information

8-Lead TD-99 Metal Can

Package

Operating
Temperature
Range

RC5532D
RC5532N
RC5532AD
RC5532AN

D
N
D
N

O°Cto -70°C
O°C to +70°C
O°C to -70°C
O°Cto +70°C

RM5532D
RM5532D/883B
RM5532AD
RM5532AD/883B
RM5532T
RM5532T/883B
RM5532AT
RM5532AT/883B

D
D
D
D
T
T
T
T

-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C

Part Number

(Top View)

B-Lead
Dual In-LIne Package
(Top View)

Notes:
8838 suffix denotes Mil-Std-883, Level 8 processing
N z 8-lead plastic DIP
D - 8-lead ceramic DIP
T - 8-lead metal can T0-99

Absolute Maximum Ratings(1)

65-01782

Pin Function
1
Output (A)
2
-Input (A)
3
+Input (A)
4
-VS
5
+Input (8)
6
-Input (8)
7
Output (8)
8
+VS

3-638

Supply Voltage ........................................... ±22V
Input Voltage .................................................±vs
Differential Input Voltage ............................. 0.5V
Operating Temperature Range
RM5532/A .......................... -55°C to +125°C
RC5532/A ................................ 0°C to +70°C
Storage Temperature
Range ................................. -65°C to +150°C
Lead Soldering Temperature
(60 Sec) ............................................ +300°C
Notes:
1. "Absolute maximum ratings" are those beyond which the safety
of the device cannot be guaranteed. They are not meant to imply
that the device should be operated at these limits. If the device is
subjected to the limits in the absolute maximum ratings for
extended periods, its reliability may be impaired. The tables of
Electrical Characteristics provide conditions for actual device
operation.

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC5532/5532A
DC Electrical Characteristics
(Vs =±15V and TA =+25'C unless otherwise noted)
Parameters

Test Conditions

RM553215532A
Min
lYP Max

RC553215532A
Min
lYP Max

UnHs

0.5

0.5

Input Offset Voltage
Over Temperature

2.0
3.0

Input Offset Current

10

100
Over Temperature

200

Input Bias Current

200
Over Temperature

400

200

700

Supply Current

6.0
Over Temperature

11

6.0

13

4.0

mV

5.0

mV

150

nA

200

nA

800

nA

1000

nA

16

mA

22

mA

Input Voltage Range

±12

±13

±12

±13

V

Common Mode Rejection Ratio

80

100

70

100

dB

86

100

dB

Power Supply Rejection Ratio
Large Signal Voltage Gain

Output Voltage Swing

80

100

Rl ~2 k.O, VOUT =±10V

50

25

100

Over Temperature

25

15

50

Rl ~ 600n, VOUT =±10V

40

15

50

Over Temperature

20

10

Rl~600n

±12

±13

±12

±13

Rl =600n, Vs =±18V

±15

±16

±15

±16

Rl~2k!l

±12

VlmV

V

±13

Input Resistance (Dit!. Mode)

300

300

k!l

Short CircuH Current

38

38

mA

NOles:

1. Diodes protect the inputs against over-voltage. Therefore,lIlless current-limiting resistors are used,large currents will flow ~ the
differential inpIt voltage exceeds O.6V. Maximum input current should be Dmited to ±10mA.
2. Over Temperature: RM= 55 "C STA 125"C; RC = O"C STA S700c

I

Electrical Characteristics
(Vs = +15Vand TA = +25°C)
RC/RM5532
Typ Max
Min

RC/RM5532A
Typ
Min
Max

Fe =30 Hz
Fe = 1 kHz

8.0
5.0

8.0
5.0

Input Noise Current Density

Fo=30Hz
Fe -1 kHz

2.7
0.7

2.7
0.7

pANRZ

Channel Separation

F = 1 kHz, Rs = 5 kg

110

110

dB

Parameters

Test Conditions

Input Noise Voltage Density

For Mora Information, call 1-800-722-7074.

Raytheon Semiconductor

12
6.0

Units
nVNRZ

3-639

RC5532/5532A
AC Electrical Characteristics
(Vs =±15V and TA = +25°C)
RC/RM553215532A
Test Conditions

Output Resistance
Overshoot

Av = 30 dB Closed Loop, F = 10kHz, RL = 600n

0.3

UnHy Gain, VIN = 100 mVp.p

10

%

CL = 100 pF, RL = 600n
F= 10kHz

2.2

VlmV

Gain Bandwidth Product
Slew Rale

CL = 100 pF, RL = 600n

10

Power Bandwidth

VOUT =±10V
VOUT= ±14V, RL .. 6000, VS·±18V

8.0
140
100

MHz
V/).IS
kHz

Gain

Min

Typ

Parameters

Max

Units
n

kHz

Thermal Characteristics
8-Lead
Plastic DIP

8-Lead
Ceramic DIP

T0-99 MetailCan

Max. Junction Temp.

+125°C

+175OC

+175OC

Max. Po TA <50OC

468mW

833mW

658mW

Therm. Res 0JC

-

45'CIW

500clW

Therm. Res. 0JA

160°CIW

1500CIW

625mW/oc

8.33 mW/oc

190°CIW
5.26 mWfC

For TA >50°C Derate at

8-Lead

Test Circuits
Follower, Transient Response

Closed Loop Frequency Response

>-~--t--'"

VOUT

600n

>=---+--_ _

VOUT

600n

100 PF,J
65-1794

3·640

Raytheon Semiconductor

65-1795

For Mora Information, call 1-800-722-7074.

RC5532/5532A
Typical Performance Characteristics
Open Loop Gain vs. Frequency

Closed Loop Gain vs. Frequency
60

120

.......
80

t'-.....

iii'
:!:!. 40

J

........

Vs = ±15V
TA =+25"C Rs=10o _

-r
~ - 10 k

40

...........

I

"""

0-

100

1K

10K

100K

1M

1K

10K

100K

~

~
1M

10M

100M

1G

Output Voltage Swing vs. Frequency

Short Circuit Current VS. Temperature
80
Vs = ±15V

Vs = ±15V

20

60

"""---

\
\

10

100

f'

1
1
F(Hz)

~

o

'\

F(Hz)

30

J

'-

1
-20

40

'1.

I

1

~

10M

d\

~=lkoRe= OC>

o
~

a

I'\.

RF = 9 k ORE = 1 k

.............

40
10

I
RE • 100

I

Av·40dB

.......

a

10K

100K

F(Hz)

-

20

\
1K

-

"

1M

~

~

~
10M

0-55

100M

-25

o

+25

+75

~

+150

TA (OC)

Input Bias Current vs. Temperature

Supply Current VS. Supply Voltage
1.4

12

+50

I

11_

I

Vs =±15V

lOUT =0_

1.2

8

-' ~

4

~

:i"

L...--

::1.

0.8

ID

0.4

~

o

o

~
±10

±20

±30

I' r---.-

o

-55

o

+25

+50

+75

+150

TA (OC)

+VtI-Vs(v)

For More Information, call 1-800-722-7074.

-25

~

~

Raytheon Semiconductor

3-641

RC5532/5532A
Typical Performance Characteristics (Continued)

Common Mode Input Range vs. Supply VoHage

Output VoHage Swing vs. Supply Voltage

,

15
10

€

5

~

0

}

TA = +25"C
R =6000

.....

V-

/"'"

V-

/

15

5

€

I..... ......

-5

.............

-10

J
I'.....

............
±5

./

TA-+25°C
10

±10

~

('"~

0

L.....,
-5

~

-10

.............. .....

~

r-.....

±20

±15

./

±5

±10

+Vr/-Vs(V)

Transient Response
Output VoHage vs. Time

Follower Large Signal Pulse Response
Output Voltage vs. Time
10

I
I
I
Vs = ±15V
TA=+25"C

8

~

J

6
4
2
0
-2
-4
-6
-8
-10

./
/
~

o

I

Ou1put

140
-

120
100

I

I
! I I
Input

±15

+Vr/-VB(V)

!
J

\..

\.

-1--

-

ii!

I

80

40

/

Vs - ±15V_
TA - +25°C
RL =6000Av=+1
CL = 100 pF

/

./

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

"""\

I

60

20

~

I

o

I
50

100

150

i

~

~

200

Time (nS)

Time (I-IS)

Input Noise Voltage Density vs. Frequency

Dmgl~
100

lK

10K

lOOK

1M

F(Hz)

3-642

Raytheon Semiconductor

For More Infonnation, call 1-800-722-7074.

RC5532/5532A
Schematic Diagram (112 Shown for 5532)

~--~~~--------~----~-------+------~--------------.--o +~
(8)

-Input
(2,6)

o-~~_--1I---+--...

R14

02

14 Output
(1,7)

+Input o--~""'o[.
(3,5)

R15
14

~~~----~----~~_~~~_~~~"",~---+----~

__

~V·s
(4)

65-1780

I
For Mora Infonnation, caD 1-800-722-7074.

Raytheon Semiconductor

3-643

RC5532/5532A

3-644

Raytheon Semiconductor

For More 1nfonnaIIon, cal 1-800-722-7074.

RCS534/5534A
RC5534/5534A
High Performance Low Noise Operational Amplifier
Description

Features

The 5534 Is a high performance, low noise operational
amplifier. This amplifier features popular pin-out,
superior noise performance, and high output drive
capability.
This alTlllifier also features guaranteed noise
performance with substantially higher gain-bandwidth
product, power bandwidth, and slew rate which far
exceeds that of the 741 type amplifiers. The 5534 Is
internally compensated for a gain of three or higher and
may be externally compensated for optimizing specific
performance requirements of various applications such
as unity-gilln voltage followers, drivers for capacitive
loads or fast seWing.

•
•
•
•
•
•
•
•

Small signal bandwidth - 1Q...MHz
Output drive capability - 600n, 10 VRMS
atVS=±18V
Input noise voltage - 4 nVNHz
DC voltage gain - 100,000
AC voltage gain - 6000 at 10kHz
Power bandwidth - 200 kHz
Slew rate -13 VlJ,1S
Large supply voltage range - :t!3V to fQOV

The specially designed low noise input transistors allow
the 5534 to be used in very low noise Signal processing
applications such as audio preamplifiers and servo error
amplifiers.

I
For More Infonnation, call 1-800-722-7074.

Raytheon Semiconductor

3-645

RC5534/5534A
ord·
enng If
n ormation

Connection Information
8-Laad
TO·99 Metal can

(Top View)

85-03205

Pin
1
2
3

Package

Operating
Temperature
Range

RC5534N
RC5534AN

N
N

O°C 10 +70°C
O°Cto +70°C

RM55340
RM553401883B
RM5534AO
RM5534A0/883B
RM5534T
RM5534T1883B
RM5534AT
RM5534AT1883B

0
0
0
0
T
T
T
T

-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C 10 +125°C
-55°C to +125°C
-55°C to +125°C

Part Number

8-Lead
Dual In-Line Package
(Top View)

65-0103

Notes:
/8838 suffix denotes Mil-std-883. Level 8 processing
N = 8-lead plastic DIP
D = 8-1ead ceramic DIP
T =8-lead metal can (T0-99l

Function
Vas Trim
-Input
+Input

4

-Vs

5
6

Camp
Output

7

+Vs

8

Vas Trim/Camp

Absolute Maximum Ratings
Supply Voltage ....................;.................. ~V
Oifferenliallnpul Voltage ......................... O.5V
Input Voltage ...........................................±Vs
Storage Temperature
Range ............................ -65°C to +150OC
Operating Temperature
Range
RM55341A ..................... -55OC to +125OC
RC55341A ........................... OOC to +70OC
Lead Soldering Temperature
(60 sec) ....................................... +300OC
Output Short Circuit Duration1 ............. +300OC
Notes:

I.

Short circuit may be to gound only. Rating applies to

+1250C case temperature or +1750C junction temperature.

Thermal Characteristics
8-Lead
Plastic DIP

8-Lead
Ceramic DIP

8-Lead
TO-99 Metal Can

Max. Junction Temp.

+125°C

+175°C

+175°C

Max. Po TA <50°C

468mW

833mW

658mW

-

45·CIW

50°CIW

160°CIW

150°CIW

190°CIW

6.25mW/oC

8.33 mW/oC

5.26mWfOC

Therm. Res 0JC
Therm. Res. 9JA
For TA >50°C Derate at

3-646

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC5534/5534A
Electrical Characteristics
(Vs = ±15V and TA = +25·C unless otherwise noted)

Parameters

Test Conditions

Input Offset Voltage

RsS 1kn

RM5534/A
Typ Max
Min

RC5534/A
Min

Typ

Max

Units

0.5

2.0

0.5

4.0

mV

Input Offset Current

10

200

20

300

nA

Input Bias Current

400

800

500

1500

Input Resistance (Dill. Mode)

100

Large Signal Voltage Gain

RL ~ 600n. Your - ±10V

Output Voltage Swing

RL~600n

Input Voltage Range

nA

100

kn

50

100

25

100

V/mV

±12

±13

±12

±13

V

±12

±13

±12

±13

V

Common Mode Rejection Ratio

RSS 1kn

80

100

70

100

dB

Power Supply Rejection Ratio

RsS 1kn

86

100

86

100

dB

Supply Current

RL • ..

4.0

Transient Response
Rise Time

VIN - 50 mY. RL - 600n
CL • 100 pF. Cc • 22 pF

35

35

nS

17

17

%

Overshoot

6.5

4.0

8.0

mA

Slew Rate

Cc·O

13

13

VflJ.S

Gain Bandwidth Product

Cc • 22 pF. CL .100 pF

10

10

MHz

Power Bandwidth

Vour • 20Vp _p• Cc • 0

200

200

kHz

Input Noise Voltage

F.20Hzto20kHz

1.0

1.0

I1VRMS

Input Noise Current

F.20Hzto20kHz

25

25

pARMS

Channel Separation

F.1kHz.Rs =5kn

110

110

dB

5534A

5534

Input Noise Voltage Density

Input Noise Current Density

Broadband Noise Figure

Fo ·30Hz

5.5

7.0

7.0

Fo .1 kHz

3.5

4.5

4.0

"Hz

Fo. 30 Hz

1.5

2.5

~

Fo .1 kHz

0.4

0.6

~

F.10Hz-20kHz.
Rs ·5kn

0.9

-

nV

dB

I

The following specifications apply for RM; ·55°C S TA S +125°C =
RC = DOC s T'A'< + 7DoC, V'5_= ±15V
RM5534/A
Input Offset Voltage

R!,:s 1 kn

RC5534/A

3.0

5.0

mV

Input Offset Current

500

400

nA

Input Bias Current

1500

2000

nA

Large Signal Voltage Gain

RL ~ 600n. Your • ±1 OV

Output Voltage Swing

RI ~600n

Supply Current

Vs-±15V.~- ..

For More Information. calI1-80D-722-7D74.

25

15

±10

±10
9.0

Raytheon Semiconductor

V/mV
V
14

mA

3-647

RC5534/5534A
Typical Performance Characteristics
Slew Rate vs. Compensation Capacitor

Input Bias Current vs. Temperature

0.6

..............

...........

0.5

<::I.

0.4

"

0.3

-

14

0.7

---

12
Vs = ±15V

I~S =~I~J

"'i"-

10

TA =+25"C

"-

8
6

'~

4

0.2

~

0.1

~
+10

+20

+30

+40

+50

+60

~

2

~

o
o

+70

10

100

Cc (pF)

Common Mode Input Range

VS.

Supply Voltage

Open Loop Gain VS. Frequency

15r---r-~r-~---'--~~~~~

11111111 1111

100
10

Vs - ±15V
TA -+25·C

80

5

111111

iii'
~ 60

J

~~I~I~p~1

~

C =22pF

40

-15 '----''-----' __- '__- '__--&.......;::.......<.LL~ ~

±4

±6

±8

±10

±12

±14

±16

±18

l-

~

I-

I-

20
-1 0 1----1f-----1---=t'-'6~~~~~~M ~

lI-

'"

o
o

Ie
i"'o.

100

1K

10K lOOK

1M

~

10M 100M

F(Hz)

+VJ-Vs (V)

Open Loop Gain VS. Temperature

-

150

>-E 100

~

~

~
-<

Vs =±15V
R L =2kU

I-- --.. I--

-

50

~

~

o

o

+10

+20

+30

+40

+50

+60

+70

TA (OC)

3-648

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RCS534/5534A
Typical Performance Characteristics

(Continued)

Output VoHage Swing vs. Load Resistance

Output VoHage Swing vs. Supply Voltage

~

.
~

15~~~~--~--~--~~~~

30

mr

10

26

1111

22

5

~

J

:>

~ -5
+---,P"'0(6!'~~~s-1 ~

-10

±8

±10

±12

±14

±16

II

14
10

~

6

~~--~~--~--~~~~
±6

~

2

±18

lK

100

10

+Vr/-Vs (V)

36

Quiescent Current vs. Supply Voltage
5

Vs = ±15V
I--II-+-HttlH--l--!-+H+IH--+++1-H TA = +25"C
RL=2kn

Il.

~

/

~ 24
G-

~

Cc=27pF

12

6 1--I--11-++1-HH-++++HflH-

0
100

10K

lK

~ ~ ~~ 1F )

~

r11111111
lOOK

1M

~

~

~

o
o

±6

±3

50

I

_l

Cc =22pF

/. -y...
-h

r

CL = 500 pF
Cc =47pF

V

"-

J

30
20

10

o

I 11/

I)
IV

-

VS = ±15V
TA = +25"C
RL =600n
Ay=+l

.;;;; f-100%
o
50

I
100

I
150

r-r-r-- ~
~
200

10
8
6
4
~ 2
0
.} -2

-

..

-4
-6

-8

-10

---

I
II

o

I

T T T _

I

Vs = ±15V
TA = +25"0
~ Cc=OpF

I'I I\,

Oulput

I

I I

Input T

-

-

\.

---

1\

'\

~

~
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

nma (liS)

-Tlma(nS)

For More Infonnation, call 1-800-722-7074.

±18

Follower Large Signal Pulse Response
Output VoHage vs. Time

90%

l40

±15

+Vsf-Vs(V)

Transient Response
Output VoHage vs. Time

cL = 100 pF

±12

±9

F(Hz)

60

T

TA = +25"0

(

18

70

-

-,

4

30

..
.}

10K

RL (0)

Output VoHage Swing vs. Frequency
42

I I

Vs = t15V
F-1kHz
T.H.D.
10

6
+VIN

-Vs

3-650

VOUT

Raytheon Semiconductor

65-1n4

For More Information, caJI1-800-722-7074.

RC5534/5534A
Schematic Diagram
Compensation
(5)

VOSTriml
Compensation

Vas Trim
(1)

4-____~__~+Vs

~____~~________~~~~~______~______-1~________

(7)

Rl
13.3K

+Input
(3)

R2
13.3K

R9
5.9K

o-~p--_--I~-I----.

R16
570
R17
150

03

02
-Input
(2)

Output
(6)

R4

Rll
180

120

R12
3K

R13
180

R14
1.5K

R20
2K

-+____-+-"""__-+-__-+-__-+__-+__-4-__-4__-4______-+--o-Vs

L -__~____

(4)
65-1726

I
For More Information, caiI1-800-722-7074.

Raytheon Semiconductor

3-651

RC5534/5534A

3·652

Raytheon Semiconductor

For More Information. call 1-800-722·7074.

RM741
RM741
General Purpose Operational Amplifier
Description

Features

The RM741 integrated circuit is a high-performance,
high-gain, internally compensated monolithic
operational amplifier fabricated on a single silicon chip
using an advanced epitaxial process.

•

High common-mode voltage range and absence of
latch-up tendencies make the RM741 ideal for use as a
voltage follower. High gain and wide ranges of
operating voltages provide superior performance in
integrator, summing amplifier and general feedback
applications.

•
•
•
•
•
•

Supply voltage
RM741-±22V
Offset voltage null capability
Short-circuit protection
No frequency compensation required
No latch-up
Large common-mode and differential
voltage ranges
Low power consumption

The RM741 is pin compatible with the LM101A. The
RM741 operates over a temperature range from -55OC
to +125OC.

I
Fer More Infonnation, call 1-800-722-7074.

Raytheon Semiconductor

3-653

RM741
Ordering Information

Connection Information
8-Lead

&-Lead

T0-99 Metal Can
(Top View)

DUBlin-LIne Package

Part Number

(Top View)

RM741 0
RM741D/883B
RM741T
RM741T/883B

Package

o
o
T
T

Operating
Temperature
Range
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C

Notes: 883B suffix denotes MiI-Std-883, Lewl B proosssing
D • 8 lead ceramic DIP
T • 8-lead metal can TO-99
65-03205

Pin
1
2

3
4
5
6
7

8

B5-03206A

Function
Vos Trim
-Input
+ Input
-Vs
Vos Trim
Output
+VS
NC

Absolute Maximum Ratings
Supply Voltage
RM741 .................................. ±22V
Differential Input Voltage ..•..•. 30V
Input Voltage' .....__..... _...................._... ±15V
Output Short Circuit Duration •. Indefinite
Storage Temperature
Range ................................... -65°C to +150°C
Operating Temperature Range
RM741 .................................. -55°C to +125°C
Lead Soldering Temperature
(60 sec) .••..•...........................+300°C
Note:
1.
For supply voltages less than ±15V,the absolute maximum
input voltage is equal to the supply voltage.

3-654

Raytheon Semiconductor

For Mote Information, call 1-800-722-7074.

RM741
Thermal Characteristics
8-Lead

8-Lead

Ceramic

TO-99

DIP

Metal can

Max. Junction Temp.

+175°C

+175°C

Max. Po TA <50°C

833mW

658mW

Therm. Res 9JC

45°C/W

50°C/W

Therm. Res. 9JA

150°C/W

190°C/W

8.33mWrC

5.26mWrC

For TA >50°C Derate at

Electrical Characteristics
(Vs =±15V and TA =+25OC unless otherwise noted)
Parameters
Test ConditIons
Input Offset Voftage 1
R!'l~10kn
Input Offset Current
Input Bias Current
Input Resistance (Differential Mode)
Large Signal Voftage Gain
RL~2 kO, Vour=±10V
Output Voftage Swing
1].~10kn
RL~2kn

Input Voftage Range
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Power Consumption
Transient Response Rise Time
Overshoot
Slew Rate
N~e:

Rs~10kn
Rs~10kn

MIn

0.3
50
±12
±10
±12
70
76

VIN. 20 mV, RL .. 2kn
CL~100pF
RL~2kn

Typ
1.0
20
80
2.0
200
±14
±13
±13
90
90
50
0.3
5.0
0.5

Max
5.0
200
500

Units
mV
nA
nA

Mn
VlmV
V

85

V
dB
dB
mW
.~.

%

I

VlJlS

1. Offset voltage is oolled by connecting a 1Okn potentiometer across the Vas trim pins and connecting the Wller pin to ·VS'

For More Information, caD 1-800-722-7074.

Raytheon Semiconductor

3-655

RM741
Electrical Characteristics
(Vs = ±15V. -55°C S lAS +125°C)

Parameters"

Test Conditions

Input Offset Voltage
Input Offset Current
Input Bias Current
Large Signal Voftage Gain

RL~10kn

RL~2kO,

Vour-±10V

MIn

25

RL~10kn

Output Voltage Swing

RL~

Common Mode Rejection Ratio
Supply Voltage Rejection Ratio

Rs~10kn

Supply Current

+125"C
-55"C
+12S"C
-55"C

Power Consumption

3-656

Typ

2kn

Rs~10kn

Max

Units

6.0
200
SOO

mV

nA
nA
VImV

±12
±10

V

70
76

dB
dB
mA
mW

Raytheon Semiconductor

For Mol8lnformation. call HlOO-722-7014.

RM741
Typical Performance Characteristics
Transient Response
Test Circuit

Input Offset Voltage
Trim Circuit

>-......-+--- Vour

-Vs

Power Consumption vs. Supply Voltage
100

J .l

80 i - TA-+25·C

!

60

rl

40

./

./

20

~

V

Open Loop Gain Vs. Frequency

J

100

80

iD 60

V

:!!.

J

/

".,

-- """

120

40

29

±10

I

±15

o
-20 1

:t20

10

Vs - I :l:1SV ITA _+25"0

'" '"

100

+VJ-Vs(V)

-45

I
-

1.

~

-90
-135

-180 1

Vs

10

100

1M

10M

Input Offset Current vs. Supply Voltage
5

~ ± 15V

TA -+25·C

......

coS

~

3

I

TA-+25~C

4

'"

10K 100K

F(Hz)

Open Loop Phase vs. Frequency

o

1K

" '""'- , I

-

~

.J
2

1K

10K 100K 1M

I

10M

1±5

:1:15

I

:t20

+VJ-Vs(V)

F(Hz)

For More Infonnalion. caD 1-800-722-7074.

±10

Raytheon Semiconductor

3-657

RM741
Typical Performance Characteristics (Continued)
Input Resistance, Capacitance vs. Frequency

Output Resistancevs. Frequency

10M

500

100

1111111

r-

1M

s

10

Ii:'

9 300

J

r2

S::

eIN

z

rr: 100K

!;

200
i;'

100
1

10K
100

1K

10K

100

100K

F (Hz)

28
26
24

,...-

22

20
18
16
~ 14
> 12
10

/

Vs =±lSV
TA= +2S0C

I I I

V

0.1

11111111

1.0

I

r-..

o

10

100

1K

10K

100K

F(Hz)

Input Noise Voltage Density vs. Frequency

Input Noise Current Density vs. Frequency

1000

100
Vs - ±lSV
TA= +2S0C

Vs - ±tsv
TA-+25°C

~ 10

100

~

~

~

j1

,j 10

~

100

1K

10K

~

100K

~

0.1

10

100

1K

10K

~
100K

F (Hz)

F (Hz)

3-658

!

1\
\

RL (kil)

I!

1M

Vs -±lSV
TA=+2S"C
RL = l00kn

!

I

100K

F (Hz)

40
36
32
28
~ 24
20
,. 16
~ 12
8
4

~I-

I

8
6
4

o

-

I

8

10K

Output VoHage Swing vs. Frequency

/

~

1K

65-0945

Output VoHage Swing vs. Load Resistance

2

I I

Vs - :tlSV
TA-+2SoC

400

RIM

Raytheon Semiconductor

For More Information, caJI1-800-722-7074.

RM741
Typical Performance Characteristics (Continued)
Short Circuit Current VS. Temperature

Input Bias Current VS. Temperature
200

~S

35
..

I±1J- f--

30

150

i
60

I.......

25

r-.....

-r-. ........
-20

-50

+20
+60
TA(·C)

*

+100

4

~

2

o

...... -..

~
rf

-

iG

I

1.0
0.8

T
TT
vs" ±15V f--.

""-

;---

80

-..

-

i--.

60

r-.

-

TArC)

Frequency Characteristics VS. Temperature

Open Loop Gain VS. Supply Voltage

-20

+20

+60

+100

-60

+140

115

II.

Vsl -

•

+140

- -..

........

~

~

~

~ P'"

0.6
-60

±115V _

110

~~~~

I

CIO~~.~

C

t~~

+20
+60
TA(OC)

For Mol8lnformaticn, cal 1-800-722-7074.

+100

- TA~ +J5°"

.,,-

iii'100
:g.
~ 95

1- ~

-20

-20

105

SIewRate

*

+140

!

40

iii

1.4

~

!

+100

+20
+60
TA (·C)

-60

• 1.2
.3

+60

120
100

.....

+20

Power Consumption vs. Temperature

I J_

"

-20

TArC)

12

~

....... ~
~

10-60

+140

Vs. ±15V- I--

14

8

...... .....

15

i

16

.s.

~

r--.....

Input Offset Current vs. Temperature

10

'"

iii 20

o

C

......

"".

.....

+100

--' i-"

...-

I

1/

90

85
80

+140

o

Raytheon Semiconductor

:t4

:t8

:t12

:t16

!

:t20

+Y,j-Ys(V)

3-659

RM741
Typical Performance Characteristics (Continued)
Output Voltage Swing vs. Supply Voltage

Common Mode Input Range vs. Supply Voltage

40

.1-

36 32 -

28

£ 24
~ 20
8 16
4

o

16

.1

.., ,.,

/'

14

./

12

./
/'

>' 12

8

1

-55·CSTA~+125·C
RL~2kO

."

±5

./

~
t10

*

€

10

J

8
6

4
2

~ -55·CSTA~+125·C

./

./

:t20

t15

-VJ+V.M

, ./

./

l..---

L

""
t10

!

:t20

t15

+VJ-V.(V)

Schematic Diagram
·lnput
(2)

~~----~~----'-------~--~------------------1---O+~
(7)

50

Output
(6)

25

~---+----~--~--

__

~~----4---+---~----+-__~____4--o~8

Note: AD raslstanca and capacltanca yaJues are nominal.

3-660

Raytheon Semiconductor

(4)

85-0lI4O

Fer More Infonnation, cal 1-800-722-7074.

RM747
RM747
General Purpose Dual Operational Amplifier
Description

Features

The RM747 Integrated circuit Is a high gain,
operational amplifier Internally compensated and
constructed on a single silicon chip using an
advanced epitaxial process.

•
•
•
•

The RM747, operates over a
temperature range from -55"C to +125"C.

•

Combining the features of the 741 with the close
parameter matching and tracking of a dual device on
a monolithic chip results in unique performance
characteristics. Excellent channel separation allows
the use of the dual device in all single 741 operational
ampDfier applications providing high packaging
density. It Is especially well suited for applications In
differential-In, differential-out as well as in
potentiometric amplifiers and where gain and phase
matched channels are mandatory.

•
•

Short circuit protection
No frequency compensation required
No latch-up
Large common mode and differential
voltage ranges
Low power consumption
Parameter tracking over temperature range
Gain and phase match between
amplifiers

I
For M:Ire Information, call1~722-7074.

Raytheon Semiconductor

3-661

RM747
Ordering Information

Connection Information
1D-Lead rD-1oo Metal Can
(Top View)

Part Number Package
Pin
1

NC

2

3
4

65-0872

Function
Output A
-VsA
-Input A
+lnputA

5

-Va

6
7

8
9

+Input B
-Input B
+VsB
OutputB

10

NC

RM747D
RM7470m83B
RM747T
RM747iI883B

D
D
T
T

Operating
Temperature
Range
-5500 to +125"C
-5500 to +12500
.. -5500 to +12500
-5500 to +12500

Noles:

883B suffix denotes MD-S1d-883. Level B processing
D • 14-1ead ceramic DIP
T = 10-lead melsl can TO-100

Absolute Maximum Ratings
Supply Voltage
RM747 .................................................±2.2V
Differential Input Voltage .............................30V
Input Voltage! _.....___...___.___....____....__.____..._...__.....±15V
Output Short-Circuit Duration .............. Indefinite
Storage Temperature
Range ............................;... -65°C to +150°C
Operating Temperature Range
RM747 ............................... -55°C to +125°C
Lead Soldering Temperature
(60 sec) ............................................+300°C

14-Lead Oualln-Une Package
(Top View)

Notes:
1. For supply voltages less than ±15V. the absolute
maximum input voltage is equal to the supply voltage.
85-0873

3-662

Pin
1
2
3

Function
-lnputA
+ Input A
Vas Trim A

4

-Va

5
6
7
8
9
10

Vas TrimB
+Input B
-Input B
Vas TrimB
+VsB
Output B

11

NC

12
13
14

Output A
+VsA
Vas Trim A

Raytheon Semiconductor

ForMere Information, call 1-800-722-7074.

RM747
Thermal Characteristics
14-Lead Ceramic DIP

10-Lead TO-100 Metal Can

+175°C

+175°C

1042 mW

658mW

Max. Junction Temp.
Max. Po TA <50°C
Therm. Res 8JC

60°C/W

SO°C/W

Therm. Res. 8JA

120°C/W

190°C/W

8.33 mWI"C

S.26mW/oC

For TA >SO°C Derate at

Electrical Characteristics

(Vs =±15V and TA =+25°C unless otherwise noted)
Parameters

Test Conditions

Input Offset Voltage

RSS10kn

Typ

Max

Units

1.0

5.0

mV

Input Offset Current

20

200

nA

Input Bias Current

80

500

nA

Input Resistance (Diff. Mode)

Min

0.3

2.0

Mil

50

200

V/mV

Input Voltage Range

±12
±10
±12

±14
±13
±13

V

Common Mode Rejection Ratio Rs S 10kn

70

90

dB

Power Supply Rejection Ratio

76

90

dB

Large Signal Voltage Gain

RL:2: 2 kn, Your =±10V

Output Voltage Swing

RL:2:10kn
RL:2: 2kn

RsS 10kn

Power Consumption

100

V

170

mW

I

Transient Response
Rise Time

VIN = 20 mV, RL = 2 kn

0.3

J.lS

Overshoot

CL S 100 pF

5.0

%

Slew Rate

RL:2:2kn

0.5

V/J.lS

Channel Separation

F=1kHz

98

dB

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-663

RM747
Electrical Characteristics
(Vs =± 15V, -55°C S;TA S; +125°C)
Parameters

Test Conditions

Input Offset Voltage
Input Offset Current

RsS; 10kn
TA = +125°C,
TA .. +70°C
TA .. -55°C
TA=O°C
TA -+125°C,
TA=+70°C
IA=-55°v,
TA-O°C

Input Bias Current

Large Signal Voltage Gain

RL~2kn,

Output Voltage Swing

Vour-±10V
RL~ 10K
RL~2kn

Common Mode Rejection Ratio Rs:!:10kn
Power Supply Rejection Ratio RS S; 10 kn
Power Consumption
TA" +125°C
TA =-55°C
Input Voltage Range

Min

Typ

Max

Units

6.0
200

mV
nA

500

nA

500

nA

1500

nA

25

VlmV

±12
±10
70
76,

V
V
dB
dB
mW
mW
V

150
150
200

±12

Typical Performance Characteristics
Frequency Characteristics vs.·Supply Voltage
1.4

I

1.2

i&!

1.0 f- Slew Rate

O.S

~

~

TA=+25°C I
./Transient Response

-

•

~

-

<-..J..

-~

'-Closed Loop Bandwid1h

0.6
±5

±10
+Vs/-Vs(V}

3-664

Input Offset Voltage Trim Circuit

±15

!

±20

65-0899

Note: Pin numbers shown are for
14-lead packages

Raytt18onSemic()nductor

For More Information. caD 1-8O().~-7074.

RM747
Typical Performance Characteristics (Continued)

Open Loop Gain vs. Supply VoHage
115

40

110

36 r-- -SsoCsTAs ±12SoC
32 I - - At ~ 2 k.Cl

J

--

T A =+2S0C

105

~

Output VoHage Swing vs. Supply Voltage

100
/'

95

V

./ ~

~ I--

€

~

J

./

90

!

8S

I

I

I

28

24
20
16
~
12
./
8
r-'
4

o

±2 ±4 ±6 ±8 ±10 ±12 ±14 ±16 ±18±20

/'

±10

±S

II

14 I - -SsoCSTAS+12SoC
12
10

./

8
4

2

/'"

V

100

...->"

±10

60

.§.
~

./

±S

I I

80 I - - TA =+2S"O

V

o

I

±lS

o~

±20

;;

300

.s..

±10

/
~

±lS

±20

+Vr/-Vs CI)

Input Resistance vs. Temperature

I

10.0

I
I - - I- VsI =±1SV

I=vs ..

±lSV
~

'-

..!P 200

100

o

L

V

V

V

±5

Input Bias Current vs. Temperature

400

V

L

40
20

+Vr/-Vs (V)

SOO

±20

Power Consumption vs. Supply Voltage

./

6

!

±lS
+Vr/-VsM

Common Mode Input Range vs. Supply
VoHage

I

L-

V

+Vr/-Vs(V)

16

/'

L

-60

""

~

1.0

L

"",

L

z

.......

-20

r£

...... ........
+20

+60

For More Information, call 1-800-722-7074.

+100

!

+140

0.1 6

- 0

Raytheon Semiconductor

-20

+20

+60

+100

i

+140

3-665

RM747
Typical Performance Characteristics (Continued)

Input Offset Current vs_ Supply Voltage

Input Offset Current vs. Temperature

40

30

C

,5.20

.J
10

140
120

TA' +2S"C

--

Vi -~SV

I

100

-

C

80

-

60

c

.J

o

:1:5

:1:10

!

20

o

:t20

:1:15

" ,
...... 1'00..

40

-20

-60

+20

+VJ-V.M

26 - Vs :t1~vl
24 _ TA=+2S"C

70
I-- Vs - :t1SV

SO

.5.

50

-

........ ......

If
40

-20

+20

+60

~

20

~

18

Ii

16
14
12
10
8
0.1

>

30
-60

+100

!

+140

35

C

25

.J

20

.5.

--

;

II
I
1/

!

I
L

10

1.0

600

.......

500

..... 1'0.....

i"""--.

"""

i"""--.

.......

10
-60

i'

400

.5.

300

~

1"0...

"""-

1'00...

......

"""- .......

.

200

15

100
-20

+20

+60

+100

+140

o

+25

TA (DC)

3-666

+140

Absolute Maximum Power Dissipation
VS. Temperature

Short Circuit Current vs. Temperature

30

1

22

"""

+100

Output Voltage Swing vs. load Resistance
28

.....

+60

TA(DC)

Power Consumption vs. Temperature

60

-

+45

+65

+85

+105

+125

TA (DC)

Raytheon Semiconductor

For More Infonnation, call1-80o-~7074.

RM747
Typical Performance Characteristics (Continued)

Input Noise Voltage Density vs. Frequency

Input Noise Current Density vs. Frequency

IlllTIlf 11
100

r---r-.

l¥>

.s.

10

Vs = ±15V
TA z +25"0

-

,j

L-~.LUI.IIL-..J....I...L.LIIIIJL......L...L..J..1.LWL--L.J..J..I.1IIII!

0.1

1
10

100

10K

1K

10

100K

100

1K

F(Hz)

Broadband Noise Referred to Input vs. Source
Resistance
100

~ Vs. ±15V

t:: TA = +25"0
iii

~

60

~ 40

i-"'"

10-1 kH

~

I'...AVOl
'r--.... I'...
()

'" 20

10K

1K

!

-20

f'...

.=

1

10

1

100

1.0 1-+-I--:::::d~+Ea--+-~+-=+~

0.8 1'--1--4--1----'1-/
0.6 L--.l..-.l..-.l..-.l..-.l..-..I--..I--..I--..I.-....J!
-60
-20
+20
+60
+100
+140

~

-135

10K 100K 1M 10M

I

~

J

·111111 ±I III
Vs = 15V
TA =+25"0
RL =100KO

28

,

24
20

1\

16
12

1\

8
4

o

100

TA (Oc)

For More Information, call 1-800-722-7074.

1K

40
36
32

1-+-+-+-

'Iii

!

~e

Output Voltage Swing vs. Frequency

Frequency Characteristics vs. Temperature
...---.---r---.-..--.---"-"--'--""'---'

~

-90

F (Hz)

1.4
1.2

-45

I"

Rs(n)

II

...... l"-

~

o

100K

o

1

Vs =±15V TA = +25"0

'\ I'..

80

10-10 kHz

1

~

100
10-100 kHz

0.1
100

lOOK

Open Loop Gain, Phase vs. Frequency
120

10

10K

F(Hz)

1K

10K

'"

lOOK

1M

F(Hz)

Raytheon Semiconductor

3-667

RM747
Typical Performance Characteristics (Continued)
Input Resistance, Capacitance vs. Frequency
10M
RIN

10

.I

I

500 f-

.....

1M

g

Output Resistance vs. Frequency
600

100

400

~

C

J

100K

J~ 1!"~15~ I
TA-+25"C

g

J

300
200

i--"~

100
10K
100

1K

10K

0.1
1M

100K

I
i

o

100

10K

1K

CMRR vs. Frequency

o

"'-

Transient Response Output Voltage vs. Time

"'

10

100

1K

24
20

>"

.!

~

"~
1

28

Vs =I:l:15V I TA =+25"C -

"

1M

F(Hz)

F(Hz)

100
90
80
70
iii 60
:2- 50
a:
a: 40
~ 30
20
10

!

100K

10K 100K 1M

J

90%..,

16
12

I

8

I

4

o I - ~'rjme

I

10M

o

I
0.5

F(Hz)

1.0

1.5

2.0

!

2.5

11m. (115)

Follower Large Signal Pulse Response
Ouput Voltage vs. Time

Transient Response Test Circuit

Vour

€

Rl

J

10
8
6
4
2
0
·2
-4
-6

J

·10

~15V1

sTA=+25"C -

/
I Output

:1

-

i'
i ~
Input:
\.

:

'-

-8
Note: Pin numbers shown are
for 14·lead packages

Vs - :l:15V
TA,,+25"C
R l ,,2kO
Cl = 100pF
I

~O%

o

-

!

10 20 30 40 50 60 70 80 90

11ma(I1S)

3-668

Raytheon Semlcondu~or

For More Information, calI1-80D-722·7074.

RM747
Typical Applications

Sine

C2

C3

Output

820pF

820pF

1%

1%

+15V

01

R3

02

lOOK
1%

R2

10

180K

>--9-0

1%
-15V

R4

Output

Rl

lOOK

lOOK
1%

:-:-i~:::;:::::;==
2 p,fC2 R2 C3 R3

f-

Cosine

(R1Cl - R2C2)

I

Cl
820pF

1%
65-0901

Quadrature Oscillator
+15V
Amplifier

Currsnt Source

R13
1.5K

R14

lN963B

R2

25.8K*

,..---t--'

20K

1%

1%
Rl
20K

1%

10

VINA o--JV\I\r-e---t

>-~-O

VOUT

R5
5K
-15V
R3
20K

1%

R4

1%
-liN

15K
10/0

I

R17
100

• Matched to 0.1 %

-15V

Zero Adjust

Note: Pin numbers shown are for 14-lead packages

+15V
65-0902

Analog Multiplier

For More Information, calI1-80Q-722-7074.

Raytheon Semiconductor

3-669

RM747
Typical Applications (Continued)

-PoCompressor
Input

R5
lK

R
Rl
lK

Compressor
12

O~~~
Expander

10

Input
-15V

-

Compressor

-Fb-

Expander
Output

Expander

Maximum compressor expansion ratio .. RIIA (10 kn> R ~ 0)
Note: Diodes 01 through 04 are matched FD6666 or equivalent
Compressor/Expander Amplifiers

R4
12K
01
6.2V

R6
10K
R5
10K
7
12

Positlve
Regulated
OUtput
+12V

10
6

R7
5K

Positive Output = VOl x R1 + R2
R2
Negative Output = - Positive Output

x =~

Negative
Regulated
Output
-12V
IL s5mA
Source or Sink

65-0904

Note: Pin numbers shown are for 14-lead packages.

Tracking Positive and Negative Voltage
References

3-670

Raytheon Semiconductor

ForMare Information, call 1-800-722-7074.

RM747
Typical Applications (Continued)
R2
30K

Notch Frequency VS. Capacitor C1
10K

Vour

I"Trim R3 such IIlaI

~-:

"'==~"
10
0.0001

0.001

0.1

0.01

1.0

c, (I'F)
Notch Filter Using the 747 as a Gyrator
R2

>12~_OVour
12

>-+-OVOUT

R1 R2

Ri';"ii2
Oaln
RIN .4ooMO
CIN 1 pF

=

ROUTS10

BW .. 1 MHz

65.()9()8

10
100
1000

R2
R1
B.W.
RIt
9kO 100kHz 400MO
11<0
100kn 9.9kn 10kHz 280MO
1OOkO 99.9kn 1 kHz
SOMO
~7

Non-Inverting Amplifier

Unity Gain Voltage Follower

R2

12

>~-O

Gain
1
10
100
1000

B.W.
R1
R2
10kO 10kO 1 MHz
10kO 100 kHz
1kO
1kO 1OOkO 10kHz
100kO 1OOkO 1 kHz

Vour

RIN
10kO
1kO
1kO
1000

vlNA

R1

vlNB

R2

ViNe

I

R3
12

Vour

Note: Pin numbers shown are for 14-lead packages

Inverting Amplifier

For More Information, caD 1-800-722-7074.

RF

Weighted Averaging Amplifier

Raytheon Semiconductor

3-671

RM747
Schematic Diagram (1/2 Shown)
~r-----~--~----1----~r-------~r--O+Vs
(9.13)

(1.7)
-Input
Output
(10.12)

(8.14)
Ves Trim o--t---t----t-.,
Ves Trim
(3.5)

5K
~

__

~_~~

____________

~_~~_1-_~

__

~

_ _+---O-Vs
(4)

Note: Pin numbers shown are for 14-lead packages

3-672

Raytheon Semiconductor

65-0871

For More Information. call 1-800-722-7074.

LM139/139A, LM339
LM139/139A, LM339
Single Supply Quad Comparators
Description

Features

These devices offer higher frequency operation and
faster switching than can be had from internally
compensated quad op amps. Intended for single supply
applications. the Darlington PNP input stage allows
them to compare voltages that include ground. The twostage common-emitter output circuit provides gain and
output sink capacity of 3.2 mA at an ou1put level of 400
mY. The ou1put collector is left open. permitting the
designer to drive devices in the range of 2V to 36V.

•
•
•
•

Input common mode voltage range Includes ground
Wide single supply voltage range - 2V to 36V
Output compatible With m. DlL. ECl. MOS and
CMOS logic systems
Very low supply current drain (0.8 mA) Independent
of supply voltage

They are Intended for applications not needing response
time less than 1 JIS. but demanding excellent op amp
input parameters to offset voltage. current and bias
current, to ensure accurate comparison with a reference
voltage.

I
For Mora InbmatIan, call 1-800-722-7074.

Raytheon Semiconductor

3-673

LM139/139A, LM339
Absolute Maximum Ratings

Ordering Information

Supply Voltage .........................................+ 36V or ±18V
Differential Input Voltage ..........................................36V
Input Voltage Range ................................ -0.3 to +36V(2)
Output Short Circuit to Ground (1) ................... COntinuous
Input Current (VIN < -o.3V)(2) ................................... 50 rnA
Operating Temperature Range
LM139 ............................................... -55"C to +125"C
LM339 .................................................... O"C to +70"C
Storage Temperature Range ................ -65"C to +150"C
Lead Soldering Temperature
S0-14, 10 sec................................................. +260"C
DIP, 60 sec..................................................... +300"C

OperatJng
Part Number
LM339M
LM339N
LM139D
LM139D1883B
LM139AD
LM139AD1883B

Package

Temperature
Range

M
N
D
D
D
D

O"C to +70OC
OOC to +70OC
-55OC to +125OC
-55OC to +1250C
-55OC to +125OC
-55OC to +1250C

Notes:

/883B suffix denotes MIL-STD-883, Level Bprocessing
M • 14..Jead plastic sOle
N. 14..Jead ceramic DIP
D. 14..Jead ceramic DIP

See Notes.

Connection Information
Thermal Characteristics
14-Lead
Plastic

so

14-Lead
Plastic
DIP

14-Lead

Ceramic
DIP

Max. Junction Temp.

+1~

+1~

+175OC

Max. PD TA <.50·C

300mW

468mW

1042mW

200CCN1

16O"CN1

12QOCN1

S.OmWFC

6.25mWFC

8.38mWFC

6f1'CNI

Thenn. Res 0JC
Thenn. Res. OJA
For TA >5Q·C Derate at

3-674

Pin

Function

Pin

Function

1
2
3
4
5
6
7

Output B
Output A
+Vs
-Input A
+lnputA
-Input B
+Input B

8
9
10
11
12
13
14

-lnputC
+lnputC
-Input D
+lnputD
Ground
Output D
OutputC

Raytheon Semiconductor

For Mora InIcrmation. call 1-800-722-7074.

LM139/139A, LM339
Electrical Characteristics
(Vs =+5V, see note 3)
Parameters

Test CondHlons

Input Offset Voltage

TA = +25"C (8)

Input Bias Current

Min

Output In Linear Range

LM139A
Typ

Max

UnHs

±1.0

±2.0

mV

25

100

nA

±3.0

±25

nA

+Vs

V

TA = +250(4), VCM = OV
Input Offset Current

TA-+25"C, VCM=OV

Input Voltage Range

TA = +25"C(5), VS = 30V

0

-1.5
Supply Current

0.8

RL = 00 on all comparators,

2.5

rnA

TA. +25"C
Large Signal Voltage

RL •

Gain

RL ~ 15 k,Q, +Vs - +5V

00,

50

+Vs" 30V,

200

VlmV

300

ns

1.3

J.1S

16

rnA

(to support large Vour swing)

TA-+25"C
Large Signal Response

VIN = TTL logic Swing,

Time

VREF .. 1.4V, VRL .. 5V,
RL· 5.1

Response Time

k,Q,

TA • +25"C

VRL - 5V, RL" 5.1

k,Q,

TA = +25°C (6)
Output Sink Current

VIN_~1V, VIN+-O

6.0

VOUTS1.5V, TA-+25"C
Saturation Voltage

VIN_~1V, VIN+-O,

250

400

mV

ISINK S 4 rnA, TA = 25"C
Output Leakage Current

~

0.1

VIN+ ~ 1V, VIN_ = 0,
VOUT=5V, TA-+25"C

Input Offset Voltage

Note 8

±4.0

mV

Input Offset Current

VCM=OV

±100

nA

Input Bias Current

VCM=OV

Input Voltage Range

+Vs·30V

Saturation Voltage

VIN_ ~ 1V, VIN+ = 0,

Output Leakage Current

VIN+ ~ 1V, VIN _.. 0,

0

300

nA

+Vs
-2.0

V

700

mV

1.0

~

36

V

ISINK S4rnA
VOUT=30V
Differentiall/llUl Voltage (10) VINt~V, (or-Vs ,fused) (7)
See Notes.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-675

I

LM139/139A,LM339
Electrical Characteristics
(+vs = +5V, see note 3)
LM33~

LM139
Parameters

Test CondHlons

Input Offset Voltage

TA= +25OC (8)

Input Bias Current
Input Offset Current

Output in Unear Range
TA=+25OC(4), VCM=OV
TA = +25OC, VCM = OV

Input Voltage Range

TA = +25oc(5), +Vs=30V

Supply Current

RL = 00 on all comparators,
TA =+25OC

Large Signal Voltage
Gain

RL = 00, +Vs = 30V,
RL ~ 15 kO, +Vs = +5V
(to support large Vour
swing), TA= +25"C

Large Signal Response
TIme
Response TIme

Min

Typ

Max

:12.0

:15.0

25

100

:1:3.0

:125

0

+Vg
-1.
0.8

:150

nA

+Vg
-1.

V

2.5

rnA

0.8

300

ns

VRL=5V,R~=5.1

1.3

1.3

pS

16

rnA

kn.

250

Output Leakage Current

VIN+ ~ 1V, Vr. = 0,
Vour =5V, A=+25OC
Note 8

0.1

6.0

16

Input Offset Current

Differential Input
Voltage (10)

:15.0

300

m

VIN- ~ 1V, ~~= 0,
ISINK S 4 m , A= +25OC

Output Leakage Current

nA

VIN =
logic Swing,
VREF = 1.4V, VRL = 5V,
RL = 5.1 kn. TA= +25OC

Output Voltage, VOL

Output Voltage VOL

250

VlmV

VIN- ~ 1V, ~~ = 0,
Vour S1.5 ,IA=+25OC

Input Bias Current

mV

25

200

25

Output Sink Current

Input Voltage Range

Units

:12.0 :15.0

0

2.5

Max

200

TA=+25OC )

Input Offset Voltage

Min Typ

6.0
400

250
0.1

0

mV
pA

:f9.0

:f9.0

mV

±100

±150

nA
nA

300

VCM=OV
VCM =30V

400

+V8
-2.

400
0

+V8
-2.

V

VIN- ~ 1V~N+ = 0,
ISINK S4
VIN+ ~ 1V, VIN- = 0,
Vour= 30V

700

700

mV

1.0

1.0

pA

VIN~~OV
(or - s, if used) (7)

36

36

V

See Notes.

3-676

Raytheon Semiconductor

For More Infcnnation, call 1-800-722-7074.

LM139/139A, LM339
Electrical Characteristics

(Continued)

Notes:
1. Short circuits from the output to +Vs can cause excessive heating and eventual destruction. The maximum output
current is approximately 20 mA independent of the magnitude of +Vs.
2. This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector
base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In
addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action
can cause the output voltage of the comparators to go to the +Vs voltage level (or to ground for a large overdrive) for
the time duration that an input is driven negative. This is not destructive and normal output states will re-establish
when the input voltage, which was negative, again retums to a value greater than -0.3V.
3. These specifications apply for +VS =SV and -SsoC S TA S +12SoC, unless otherwise stated. The LM339 temperature
specifications are limited to O°C S TAS +70°C.
4. The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant,
independent of the state of the output so no loading change exists on the reference or input lines.
S. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than
0.3V. The upper end of the common mode voltage range is +Vs -1.SV, but either or both inputs can go to +30V
without damage.
6. The response time specified is for a 100 mV input step with S mV overdrive. For larger overdrive signals 300 ns can
be obtained. See Typical Performance Characteristics section.
7. Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within
the common mode range, the comparator will provide a proper output state. The low input voltage state must not be
less than -0.3V (or 0.3V below the magnitude of the negative power supply, if used).

8. At output switch point, Your = 1.4V, As = on with +Vs from SV to 30V; and over the full input common mode range
(Vourto +Vs -1.SV).
9. For input signals that exceed +Vs' only the overdriven comparator is affected. With a SV supply, VIN should be
limited to 2SV max, and a limiting resistor should be used on all inputs that might exceed the positive supply.
10. Guaranteed by design.

I
For More Information, call 1-800-722'7074.

Raytheon Semiconductor

3-677

LM139/139A, LM339
Typical Performance Characteristics

--

Supply Current vs. Supply Voltage
1.0
.... 1"'"

o.a
~

r
~

D.2

o

o

--

r--

"..

0.4

--

~ I""""

....
0.&

~

---

is

Input Current vs. Supply Voltage
80

TA,- -ts-c
...TA,-crc
1"""
I
TA,-+f5'C-

L
~ Ioe
TA,-+7O'C_

vI~(C~.~V

I- RIN(CM) - oooMO
80

TA--s'C

i

J

~.L-crc

40

TA,-+2!i'C
ITA,-+ 25"CL-

""

2D

:1:10

o

:1:15

:l:VsM

T~_+1~

o

:1:15

I

±211

Output Saturation Voltage vs. Sink Current

oulo!
SalUralion

1.0

~

:1:10

:l:VsM

10

>

is

"'

T~_+7O'C

~~

~~ V

0.1
TA,.+125·C.......

0.01

III

'II

~r

TA,.-55OC

./ ~~
. / ~ " " ' TA, • +25·C
~ I'

0.001
0.01

0.1

1.0

10

100

SINK

3-678

Raytheon Semiconductor

For Morelnbma1{Qn, call 1-000-722·7074.

LM139/139A, LM339
+5V
6.0
5.0

~

I-

::>
>0

1

4.0

1-

3.0

co- ,- 20 mV

2.0
1.0

>

.5.
z
:>

0
~7'
0
-50

Input Overdrive _ S.O mV

1 \

100mV r-

7'
TA =2S0 C

-100

65-0086

o

O.S

I.S

1.0

2.0

Time (l.Is)
Input Overdrive Response Time

+SV
6.0
5.0

"

4.0
I-

3.0

>5

2.0

I

.5.

J

J
20mV

I

I

I

I I

~

o
z
>-

'\. J

Y I

1.0

>

Input Overdrive .100 mV

I

I
SmV

I
~

(-;7
100
SO

TA

=2S oC

'1'

0

o

0.5

1

I.S

1.0

2.0

65-0687

Time (l.Is)

I

Input Overdrive Response Time

For More Information. call1-BOO-722-7074.

Raytheon Semiconductor

3-679

LM139/139A, LM339
Typical Applications - Single Supply (+Vs = +15V)

.
our

Drivingm

Driving CMOS

Comparator with Hysteresis

12V

ORing the Output

Limit Comparator

--

.Va

II

v..

tOOK

One-Shot Multivibrator with Input Lock Out
3-680

Raytheon Semiconductor

For Mole 1nbma1ion, calI1-800-'n2-7074.

LM139/139A, LM339
Typical Applications - Single Supply (Continued)

100K

1001<

2

5.1K

'>--11-+-0 vour
1N914

20M

I

10K

0.5 \IF

Low Frequency Op Amp

Zero Crossing Detector (Single Power Supply)

R•

• 11

AI

•

DI
'N\l14

10"

m

to MOS Logic Converter

Pulse Generator

-

I
For Mora tnramalion, call 1-800-722-7074.

Raytheon Semiconductor

3-681

LM139/139A, LM339

3·682

Raytheon Semiconductor

For More In!ormation, caa 1-800-722·7074.

RM4805
RM4805
Precision High Speed Latching Comparator
Description

Features

The RM4805 is an ideal comparator for high speed. high
precision applications. The input errors are factor
trimmed to less than 1/10 LSB of a 12-bit. 10V system.
The latch function allows the system designer additional
flexibility. When the latch input is a m low. the
comparator functions normally. When the input is raised
to a TIL high. the comparator oUlput is latched in its
current state.

•
•
•
•
•

22 ns propagation delay
Low offset voltage - 100 J.1V
Low offset current - 10 nA
m compatible latch
moulput

The RM4805 is ideal for ultra precise. very fast system
designs. Typical applications include successive
approximation NO converters of 12 or more bits. zero
crossing detectors. high speed sampling and window
detectors.
The RM4805 high speed comparator is functionally
equivalent to the popular comparators AM686. SE527.
CMP-05 and J,tA760. Propagation delay is 35 ns with a
112 LSB overdrive in a 12-bit. 10V system.

I
For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-683

RM4805
Ordering Information

Absolute Maximum Ratings
Supply Voltage ...........................................+5.5V1-16.5V
Differential Input Voltage ............................................ 1V
Internal Power Dissipation 1 ................................... 500 mW
Input Voltage ............................................................±4V
Storage Temperature Range .•......•...... -65°C to +150 °C
Operating Temperature Range
RM4805 ............................................ -55°C to +1250C
RC4805 ................................................. O°C to +70OC
Lead Soldering Temperature (60 sec.) ............... +300°C

Part Number

RM4805D1883B
RM4805A01883B

Package

Operating
Temperature
Range

D
D

-55OC TO +125°C
-55°C TO +125°C

Notes:

18838 suffix denotes MIL-5m-S83, Level 8 processing

o.. S-Iead ceramic DIP

Note:
1

See table of Thermal Characteristics for maximum
ambient temperature derating factor.

Thermal Characteristics
8-L.ead
Ceramic

DIP
Max. Junction Temp.

+175OC

Max. Po TA <50'C

833mW

Therm. Res eJC
Therm. Res. eJA

150"Cm

For TA >50'C Derate at

8.33 mWfC

Connection Information
8-Lead
Dualln-Une Package

(Top View)

Pin

Function

1
2
3

Ground
+ Input
-Input

4
5

-Vs
NC

6
7

Latch Enable
Output

8

+Vs

65-0506

3-684

Raytheon Semiconductor

For More Information, call HIOO-722-7074.

RM480S
Electrical Characteristics
(Vs = i!jV and TA = +25°C. Latch Enable = OV unless otherwise noted)
Parameters

Test Conditions

Input Offset Voltage

Rs s50n

Min

RM4805A
Typ
Max

Min

RM4805
Typ
Max

UnHs

100

250

250

600

J1V

Input Offset Current

10

80

25

1S0

nA

Input Bias Current

0.7

1.2

0.9

1.8

J1A

Large Signal Voltage Gain
Output Voltage SWing

15
VIN > 10 mV.lour = 200 (.IA

2.4

Input voltage Range

±2.2

Common Mode Rejection

RsS50n. VCM = Min

Ratio

Input Voltage Range

Power Supply Rejection

Rs S 50n. +Vs = +SV.

Ratio

-5.2SV S -Vs S -4.75V

2.7
0.3

VIN <-10 mV. ISINK=8 rnA

10

50

2.4

±2.0

V/mV

2.7
0.3

0.4

±2.7

40

V
0.4

±2.7

V
V

86

84

dB

86

84

dB

86

84

dB

and -Vs = -5V.
+4.75V S +VS S +5.25V
Rssson
+Vs .. +5V.
-SV S -Vs S -15V
Supply Current (Positive)

VOUTSO.4V

Supply Current (Negative)

VOUTSO.4V

Power Consumption

VOUTSO.4V

115

160

130

180

mW

100 mV Step. Voo = 5 mV

22

35

22

35

ns

100 mV Step. Voo = 1.2 m\

35

35

ns

Enable Time

Voo=SmV

16

16

ns

Disable Time

Voo=5mV

22

22

ns

Propagation Delay'

11
-16

16

-12

13
-18

18

-13

rnA
rnA

Latch

Latch
High Voltage

2.0

Low Voltage

2.0

V

0.8

0.8

V

Latch
High Current

VLH = 3.0V

40

75

(.IA

Low Current

VLL =0.8V

10

20

(.IA

'Minimize lead length by soldering the 4805 directly to PC board. The use of sockets may cause oscillations from stray capacitive coupling.

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-685

I

RM480S
Electrical Characteristics
(Vs = ffJV, RM = -55°C gA S+125°C; RC = O°C STA S+70°C, Latch Enable = OV unless otherwise noted)
RC4805/RM4805
Min Typ
Max

Units

0.80

0.50

1.5

MV

5.0

2.5

7.5

I1VI"C

RC4805E1RM4805A
Typ Max
Min

Parameters

Test Conditions

Input Offset Voltage

RsS50Q

0.25

Average Input Offset

(Note 1)

1.5

Voltage Drift
Input Offset Current

200

400

nA

Input Bias Current

2.5

3.8

~
V/mV

Large Signal Voltage Gain
Output Voltage Swing

15
V,N > 10mV, '0UT=200~

2.2

0.3

V,N < -10 mV, ISINK = 6.4 rnA
Input Voltage Range

10
2.2

2.5
0.45

0.3

0.45

V

±2.0

±2.0

V

Rs s50o. VCM = ±2V
Input Voltage Range

85

80

dB

Power Supply Rejection

Rs S50o. +Vs =+5V,

75

72

dB

Ratio

-5.25V S -Vs S-4.75V

Common Mode Rejection
Ratio

and -Vs = -5V,
+4.75V S +VS < +5.25V
Supply Current (Positive)
Supply Current (Negative)
Power Consumption
Propagation Delay 1

VOUT SO.4V
VOUT SO.4V

13
-20

18

15

15
-20

20

15

mA
mA

VOUT SO.4V
100 mV Step, VOD = 5 mV

140

190

150

200

mW

30

50

35

55

ns

100 mV Step, VOD = 1.2 mV

50

50

ns

Note:
1.

Guaranteed but not tested

3-686

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RM4805
Typical Performance Characteristics
VOUT(V)

I
1. 5.0 mV 0.0.
2. SmVO.D.
3. 1.2 mV 0.0.

3 ......

2 .....
1...,.

, ,

4

I

hDut

Outpl!r-

3

If'. LI' ,.r-. ~

\
2
1_V

1\

I

I

,

\

r\

3

,

. . 1\ ./ r\ ~

r\ IA

/

1. S.omVO.D

o

I-Input

I

Output

1\

3 ......
2. SmVO.D.
3. 1.2 mV 0.0.

5 nsiPar Division

2

1\

A

2 ......

7

VOUT (V)
4

\
o

5 nsiPar Division

Rising Edge Response Time

Falling Edge Response Time

Inlltmalto
Generator
50

f\J 100:1

Divider

50

Response Time Test Setup

I
Response to 50 MHz Sine Wave

Response to 25 MHz Sine Wave
For More Information, call 1-800·722-7074.

Raytheon Semiconductor

3-687

RM480S
Typical Performance Characteristics (continued)
1ZOO

1000

VS-~V

800

'"

!600
400
10~~~~~--~-4

8~~~~~~~~~!
-ss

+25

-55

+25

+125

TA (OC)

TA(:C)

Supply Current vs. Temperature

Input Bias Current vs. Temperature
36

80

"

70

VS .. ±5V
60

~

o

+125

90

~

--.... r--....

VS-':!:5V

32

r- Voo-5mv
L

50
24

40

~

V

V

10'

30

20
it

20

~

10

lOOK

1M

10M

100M

16
-55

+25

F(Hz)

Gain vs. Frequency

3-688

+125

TA (OC)

Propagation Delay vs. Temperature

Raytheon Semiconductor

For Mora Inlcnna1lon, call1~722-7074.

RM480S
Applications Information

Latch Enable

Optimal performance of the 4805 in high speed
applications circuits requires that careful layout and circuit
design techniques are used. The use of good power
supply bypass capacitors, minimum lead lengths and a
good ground plane are essential. Clamping diodes for the
inputs may also be required.

The effective gain at low levels of input overdrive can be
increased by applying a carefully timed positive going
step to the latch enable input. This technique is
especially useful in successive approximation AID
converters, where the exact time of comparison is well
defined. After the SAR changes the DAC output. a
delayed pulse applied to pin 6 will increase the effective
gain from about 5 VlmV to 20 VlmV. and therefore
speeds up the response time for low level input signals.
In a 12-bit ±10V AID system. the propagation delay for 1
LSB will decrease about 30%. Figure 1 shows the
waveforms for this technique, and Figure 2 shows a
one-shot time delay circuit using a m IC that can be
used to create the pulse.

Bypass CapaCitors
Tantalum electrolytics connected close to the power
supply leads are usually sufficient; sometimes a smaller
ceramic capacitor in parallel with the tantalum may
improve high frequency response even further. Typical
values would be 10 J.IF in parallel with 0.01 J.IF.

Minimize Lead Lengths
Short input leads are essential to eliminate stray
capacitance that might otherwise induce oscillations.
Avoid the use of sockets; solder the IC directly to the PC
board. When laying out a PC board, position the signal
source as close to the comparator inputs as is physically
possible. Avoid stray capaCitance from the inputs to
ground, and route the output away from the inputs. Best
response times will occur when the source impedance
driving the inputs is kept low «1 kDJ. Avoid driving heavy
capacitive loads with the output (example: coaxial cable,
which has a parasitic capacitance of 50 pF per foot).

"1"_

,g_____ _
Clock

"0.._ _ _ _....

"1"-

-0"_ _ _ _

w ____

---'n~=====

Latch (Pin 6)

Comparator

Input

T D(One-Shot)

Figure 1. Gain Boost Waveforms

Ground Plane
A ground plane reduces the parasitic inductance of PC
traces. Current flow through the PC trace is mirrored by a
return current flow that passes through the ground plane
adjacent to the PC trace. This sets up a magnetic field that
cancels the magnetic field in the PC trace. thus reducing
parasitic inductance.

DalayTime

Use the component side of the board for the ground pane.
Cover that side as completely as is practical. especially
under traces carrying high frequency Signals. Mount high
frequency components close to the board.

Adjust

Clamping Diodes
If the differential input voltage will be greater than 1V. the
inputs should be clamped with high speed low
capacitance diodes.

JL

......,
Figure 2. Delayed Pulse Circu~

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-689

I

RM480S
Typical Applications

4805 Response
DAC settling Time·
SAR Delay Time
Total-Cycle Time
Number Cycles + Reset
Total ConversIon TIme

ConversIon TIme
8-BHs
20ns
135 ns
50ns
205ns

x9

~ 1= 1/2 LBS
Samp~
2
and Hold J...-.JVV\r-...~---t
Amplifier

3

Clock

Digital
Out

'-------"7""'"IIOUT

OAC-08

'OuT
• Response will be affected by DAC's output
capacitance and equivalent resistance.

Figure 3. Successive Approximation ADC

3-690

Raytheon Semiconductor

For More Information, call HlOO-722-7074.

RM4805
Typical Applications (Continued)
2K
0.1%

10K
0.1%

-=
1K

A
B

C
1K

.sV
10K

10K

'Delay should equal the settling time spedflcation minus 30 ns minus appropriate guard band.

Figure 4. Op Amp Settling Time Test Circuit

The settling time test circuit uses the precision
latching window comparator to automate op amp
settling time testing. If the DUT is not settled by the
end of the time delay, the A output is latched low.

Latch 1
R1

7
>-------~--------o

A

A

o
o
B

B

o

c

o

o

o

*Both latches low

Vy _'VV\r---t

>----------------0 c

15-1171

Figure 5. Precision Latching Window Comparator

For More Infonnation. call 1-800-722-7074.

Raytheon Semiconductor

3-691

I

RM480S
Fast Latching Eel to TIL Line Translator,
Up to 50 MHz

type as a reference, a single-end ECl to m translator
can be made to track changes in logic levels. A typical
circuit is shown in Figure 9.

The high speed differential input and the latched m.
output makes the 4805 ideally suited for use as an ECl
to TTL translator. Existing logic supplies of -5.2V and
+5.0V are compatible with the 4805 power supply
requirements. With a m compatible latch input, the
4805 can be latched from the m subsystem or from
the ECl subsystem, by using another 4805 on the latch
signal.

In system design one subsystem may be in one
configuration, be driven with ECl line drivers, but in
another configuration the same subsystem may be
driven from a TTL gate.
High gain, low input bias current and ±2.0V common
mode range on the 4805 allow the easy design of an
adaptive ECl-m. to m. translator. The ECl interface
is the same as shown in Figure 6. By adding pull-up
resistors and a bypassed level shifting resistor to the
m. outputs (see Figure 9), the same subsystem line
receiver can interface with ECl or TTL with no hardware
change in the receiver.

In ECl systems, the termination resistors and pull---.TTLOut
MC10101
R2

R4
·1SV

.Vs (-S.2V)
65-1504

Figure 6. Eel to m Translator

3-692

Raytheon Semiconductor

For More Information. calI1.aoo-722·7074.

RM4805
Typical Examples (Continued)

-5.2V
10K

,

Tracking
......... logic
Threshold

-5.2V(.VS>

8S-1508

·5.2V (.VS>

Figure 7. Single·Ended ECl to m Translator wtth Tracking ECl Reference

+5.0V

Une
Termination
Resistor

ECl
Signal
Level.

I

TTlGnd

EClGround

-5.2V(.VS>

1_1"-11------ Gnd

-------i~

·Nolse+
8S-1505

Notes:
1. Common mode range of 4805 Is -B.ov to +2.0V.
2. The 4805 can stand -3.0V, +5.0V of ground noise from the ECl Gnd to the TTL Gnd.

Figure 8. ECl to TTL Translator with extended Common Mode Range

For More Information, call 1-800·722·7074.

Raytheon Semiconductor

3·693

RM4805
Typical Examples (Continued)

For 220WUne
-Vs--S.2V
VTHEV - -2.0V

Eel
Logic
Lovels

v--.

Rl - R3 - 179 (180)
R2 - R4 - 286 (270)
RS_R6_1K

~......

Cl-C2-SOpF

Twis1ed
Pair
+S.OV

-

~--~----~--1-~~1---~TTLorECl
TTL
Signal

l

-=-

+S.OV

Rl

R3

~----~----~~-4

R4

R2

-S.2V

-S.2V (-Vsl

Figure 9. Adaptive Eel -m to m Translator

3-694

Raytheon Semiconductor

65-1507

For More Infonnation, calI1-SOO-722-7074.

en

a'

(")

~

::r
C'D

igo
~

~7041

~
~
?J

f ~':!"
R!~ R1e
960 480

R1E
1920

~~S6

_?ZR

R1S
120

340

I

'S;

g,

7R24

S4

r

03

Q9

~VOl 01~ ....

Q1

f~

"'05

.

+Input 00-Input

01

044,N

.....c: ~
~
r.~~
~oeK

R12

......067

R27
30K

042'"

...."['

rU-

I,

~ ~

V

I

I

Q64~

r

AS
UK

R28
10K

~
061

~

'-.I

047

048,

R6
1.5K

~

~7034

?"...........

...
1i!.5

"'-I

V048

(ols (ok
(4)

·VI

I

022'"

......

~
R19
UK

I

025

~

,

OS1V

J043

I

I

3K

!'Ii;

J070

r

052 V

Gnd

Q1~

V013

r

a

a

031
4X'-l:LG

l
=
~

V 053 '-4071

I

\put

R29

028

......

~(

.. ,1!

A' L

-",

Q60l...,.

~'

300

R10 .."

f3C

H;::Q68

r--

R.....

R7
325

3K

Q23

~J.-I

024

R14
3K

~

/#'I

R11

~
~ ~
~ '~~
05!A-

iiJ
3

.....,021

S8~

a
o

i

3K

13)

066'-.1

c!"

Q38

UK

c

..

c

r-..,

017
650

~O4

02

Q58

1=

lKQ27

-"'j
..

2

06

""\:..

03*

=-J

VQ10

'-.I
~ ~S9

I

_~

L'l

~

n
o

R4J
650...

R2C
240

R2
340

"82

R3
650

n
.~~
03'J

::l

3

....
...

R2S
120

R23
2.6K

S~:-206t<:
>---

Z1

R1A

ffl

aC:;"

Latcll Enable

.?

"j>!

3

(6)

('

VQ49

'I

I

RM4805

3-696

Raytheon Semiconductor

For Moll! Infcrmation, call 1-800-722-7074.

LMII11LH2111
LMll1/LH2111
Voltage Comparators
Description

Features

These low input current voltage comparators are
designed to operate over a wide range of supply
voltages,lncluding ±15V and single +5V supplies. Their
outputs are compatible with DTl, RTl, TTL and MOS
devices, and can be connected in "wire-OR"
configuration. The LH2111 consists of two LM111 les
packaged in a 16-lead DIP. The LH2111 is available
with MIL-STO-883B screening.

•
•
•
•

Low input offset current - 4 nA
Low input bias current - 60 nA
Operates from a Single +5V supply
Response Time - 200 ns

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-697

LMlll/LH2111
Absolute Maximum Ratings

Connection Information

Supply Voltage .......................................................±18V
Output to -Vs............................................................ 50V
Ground to -VS' ..........................................................30V
Differential Input Voltage ..........................................30V
Input Voltage 1..............................................................±15V
Power Oissipation2 ................................................. 500 mW
Output Short Circuit Duration .............................. 10 sec.
Storage Temperature Range ................ -65°C to +150°C
Operating Temperature Range ............. -55OC to +125OC
Voltage at Strobe Pin ........................................ +VS -5V
Lead Soldering Temperature (60 sec.) ............... +300°C

8-Lead
TQ-99 Metal can

(Top View)

Pin

2
3

65-03205

Notes:
1. For supply voltages other than ±15V, the maximum input is equal
to the supply voltage.
2. Observe package thermal characteristics.

Function
Ground
+Input
-Input
-Vs
Balance
Balance/Strobe
Output
+Vs

1

8-Lead
4
Dual In-Line Package ~

7

(Top View)

8

Ordering Information
Part Number
LM111T1883B
LM1110/883B
LH2111D
LH21110/883B

Package

OperatIng
Temperature
Range

T
0
0
0

-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C

Pin
1
2
3
4
5
6

65-03206

Notes:
/8838 suffix denotes MIL-Sro-883, Level 8 processing
o ~ S-Iead ceramic DIP (LMlll)
0= 16-lead ceramic DIP (LH2111)
T = S·lead metal can (TO-99)

7

Thermal Characteristics
8-L.ead
TQ-99

Metal can

Ceramic

16-L.ead
CeramIc

DIP

DIP

8-L.ead

Max. Junction Temp.

+175"C

+175"C

+175"C

Max. Po TA<50'C

658mW

B33mW

1042mW

45"CN-1

60"CN-1

Therm. Res 9JC
Therm. Res. 9JA

5O"CNJ
190"CN-I

150"C1W

For TA>5O"C Derate at S.2BmWfC 8.33mWfC

3-698

65-02658

8
9
10
11
12
13
14
15
16

Function
+Vs (A)
Ground (A)
+ Input
-Input (A)
-Vs
Balance (8)
Bal/Strobe (B)
Output (B)
+Vs
Ground (8)
+Input (8)
-Input (B)
Balance (A)
Bal/Strobe (A)
Output (A)
NC

120"CN-I

8.38mWfC

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

LMlll/LH2111
Electrical Characteristics
(Vs = ±1SV1 and -55"C S; TAS; +12SoC unless otherwise noted)
Parameters
Input Offset Voltage 2
Input Offset Current2
Input Bias Current
Large Signal Voltage Gain
Response Time
Output Voltage Low (Vou
Output Leakage current
Input Offset Voltage"
Input Offset Current"
Input Bias Current
Input Voltage Range
Output Voltage Low (Vou
Output Leakage Current
Positive Supply Current
Negative Supply Current

Test Conditions
TA= +25"C. Rs S; SO kn
TA = +2SoC
TA = +2S"C
TA = +2SoC
TA= +25°C. 100 mV step. S mV overdrive
VIN SS mV.IL = SO mA, TA = +2S"C
VIN~S mV. Vour=35V.
TA = +2S"C. ISTROBE = 3 rnA
RgS;SOkn

Min

Pin 7 pull up may go to +5V
+Vs = 4.SV. -Vs = OV. VIN S -6 mV.lour = 8.0 mA
VIN~SmV. Vour=35V
TA= +25"C. each amplifier
TA= +2S"C. each amplifier

-14.S

40

Typ
0.7
4.0
60
200
200
3.0
0.2

Max

10

Units
mV
nA
nA
VlmV
ns
mA
nA

1.S
S.O
100

4.0
20
1S0
13.0
0.4
sOO
6.0
S.O

mV
nA
nA
V
V
nA
mA
mA

0.23
100
S.1
4.1

3.0
10
100

Notes:
1. Vos.los and 18 specifications apply forVs • +5V to Vs. ±15V.
2. Vos and los are maximum values required to drive the output to within 1V of either supply with a 1 mA load.
3. Do not short circuit the strobe pin to ground - drive it with a3 to 5 mA current instead.
4. If the strobe and balance pins are unused, short them together for maximum AC stability.

I
For More Infcnnalion, call HIOO..722..7074.

Raytheon Semiconductor

3..699

LMII11LH2111
Typical Performance Characteristics
400

,

I...

.......
300

........

.........

100

Raised (Short Pins :
5,6, and 8)*
_

........

-

.........

=
-

30

-

20

I

V!'_:t 15V

Nonnal

Va .. :t15V

--

" "" .......

1
~

=

Raised (Short
Pins 5, 6 &8)*

""-t.

I

-- -

10

........

........

..........

...

Normal
I

o

o

-55

-35

-IS

+25 +45 +65

+5

+85 +105 +125

-55

-35

-15

+5

TA CDC)
* Pin numbers are for 8-lead packages

+85

+85 +105 +125

Input Offset Current vs. Temperature

100

180

f-- T" - +25 "C

160
1..0'

JJ III

10

F=

g

+45

• Pin numbas are for B-Iead packages

Input Bias Current vs. Temperature

:;:-

+25

TA CDC)

·~.xlmum ~

~

-

>'8

i-"

~

c.s.
III~YPIC81

_tfJ

VOI-Vos+R,los

II""

10K

T,,_+25"C

120
100
80

I

"

1M

-

Il

60
40

11111

0.1

IV~_ ~5~

140
~

20

o

10M

-16

-12

-8

o

-4

+4

+8

+12

+16

VOIFFCv)

Input Bias Current vs. Differential Input Voltage

Equivalent Input Offset Voltage vs. Input Resistance

I
I

-D.5
-

I
I

60

I
I

'Refer:ed to ':tvs

-1.0

:;:-

..... -1.5

~

>

I

I

,

-

+0.2
·Vs

-55

-35

-15

+5

+25

+45 +85

+85 +105 +125

Emitter

I- Follower Output
IRL=800u
10
I

I

I

o-1

I

I

I

I

I

,-

I
I

l-

~

I

Va =30V TA=+25"C-

I

~

>-

+0.4

-D.5

"'-.~

,I"
o

"

'+0.5

!

+1

VDlFF{mV)

TA CDC)

Common Mode Limns vs. Temperature
3-700

I

50 r - - Normal OUtput
~
RL=1K
V++= SOV

Output Voltage vs. Differential Input Voltage

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

LMll1/LH2111
Typical Performance Characteristics (Continued)
6

6

5
~

4

!;

3
2
1

>0

/ V
20m

-

5m
2m

~
Z

>-

'-J III
/

.j

1:

- f--fSlOO - f--0

Vwj:

,~

IY

>

I
I

o

I
I

2 f-smv

~z

!

0.6

0.2

~

1-2mV -

\ 1\
\

,"

1'4

>"

~

IU

"-

..l,... ~

_

I
o

0.8

0.2

+

=
VOUT

2K

-

\\
")--f-+_\lj..:\.~-..piI-II-'~":..p.-....~
o
I I I ..

100

>

50
0

_
~

o

I

2

20mV ...,
5mV ..,.
V
2mV T

7

0.5

!;(

0.4

til

>

..

0.3

.'

..,

-SSoe:

.'

~

.J

!'lit'

... --

,:&,

.I

140

"

120

.-"l! ~

..

I

I

I

T

I

T

T
4

3

2

I

~

Po

,
,,,
7

100

.'IIP"

80

1/

,

40

~

0.7

,--

0.6

:::;;iii'\'"
",

0.5

T,,= +25"C

.........

~

ISC I - -

o
20

30

40

~

0.3

11-

C

0.1

o
o

10

0.4

0.2

/

20

T A -+25·C

-- --

""-

_~ &0

o

o

'K-

Input Overdrive vs. Response Times

I#'

0.1 t..I":

Vour

I

T

o

.A

0.2

-_

_

Time (liS)

T A= +125·C

TA=

T

+

I

I

T"uroe: ,

4

0.8

~

I

f-- I - V.=t15V

Input Overdrive vs. Response Times

0.6

T

-VI

Time (liS)

0.7

0.8

£1i., ";" =
_

~

IL

-

o

T

Vw

0

I

3

T
,/

f/ 7'

-1,ft

Vs =t15V _
T,,=+25"C

I

,

20
5
0
0
5
0

-10

!

I
0.6

0.4

Input Overdrive vs. Response Times

UJ~,,_-

-s

-

I

I
I

TA • +2S"C- f---

-100

I

5 ~ 5 mV
0 ~ 2 mV

'-'--

Tim_(II S)

~ ~: ~ 2Lv~~-\"-,....p~~f-+-YW~·V'
:::!

ll

I
-I

0

Time ()Js)

I-

. . ur

\

~

-so

Input Overdrive vs. Response Times

20

YW~OYour

\

1-'
3 1-20mV .,

f---

oY our-

,'9' LM 11

0

€

4

I:::I

.sv

IlY 1/
'fY

o

f---

.-

I

II

C_

T =:1:2

5

10

15

50

'OUT (mA)

Output Saturation VoHage vs. Output Current

For More Information, call 1-800-722-7074.

Short CircuH Current, Power Dissipation VS. Output Voltage

Raytheon Semiconductor

3-701

I

LMIIIILH2111
Typical Performance Characteristics (Continued)
10

6

V.=:l:15V _

TA=+25°C
5

1

4

_ti

3

C

.§.
>

~

2
1
00

-1

8

I"'-

4

+vs

~

r-

r
:l:Vs
2 r (Oltput1Igh)

!

:1:10

:tS

""" r--...

6

- -~

~tputLow)

I'-......
""'-

o

:1:15

.55

-35

-

·15

±VSM

+5

+25

+45

+65

- -~

+85

TA (0C)

Supply Current vs. Temperature

Supply Current vs. Supply VoHage

100
FV s =±15V

~

10

.s

I

~VOUT

~

""""'""

=50V

I ..........

il5
-='
.1

.01

I

I

i...oo""""

I .............

V1N=15V

I

r--"'"

I

I

I

I

25

45

65

85

105

125

leakage Current vs. Temperature

3·702

Raytheon Semiconductor

For More Information, call 1-800-722·7074.

LMII11LH2111
Schematic Diagram
Balance
(5)

r--+-~--~~~~--~---1---+--~--------------'----O(~ +Vs

Output
(7)

(3)

R13
4.0
Note: PIn numbera are for 8-lead packagea
(4)

.Vs

(1)
Ground
6!>4038

I
For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-703

LMll1/LH2111

3-704

Raytheon Semiconductor

For Molllinfonnation. call 1-800-722-7074.

REF-Ol

REF-01
+lOV Precision Voltage Reference

Description

Features

The REF-01 Precision Voltage Reference contains a
bandgap reference using thin-film resistors, a step-up
amplifier, short circuit protection, and a zener trim
network. The REF-01's +1 OV output shows excellent
stability for large changes of temperature, load
current, and input voltage. A trim pin is provided that
can change the output voltage by at least 3% with little
effect on temperature coefficient.

•
•
•
•
•
•
•
•

+1 OV output - fD.3%
Adjustable - ±G%
Excellent temperature stability - 3 ppmrC
Low noise - 20 J1.Vp-p
Wide input voltage range - +12V to +40V
No external components
Short circuit proof
Low power consumption - 15 mW

I
For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-705

REF·Ol
Connection Information

Ordering Information

8-Lead
Dual In·LIne Package
(Top View)

8-Lead T0-99
Metal can
(Top View)

65-0970

Part Number

Package

Operating
Temperature

0
0
N
N
0
D
T
T

O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
-55'C to +125'C
-55'C to +125'C
-55'C to +125'C
-55'C to +12S'C

"'.........
-v

Pin
1
2
3
4
5
6
7
8

Function
NC
+Vs
NC
Ground
Trim
Output
NC
NC

REF·01CO
REF·01DO
REF·01CN
REF·01DN
REF·010
REF·01018838
REF·OH
REF·01T/8838

Notes:
/8836 suffix denotes Mil-Std-883. Level 6 processing
D = 8-lead ceramic DIP
N = 8-lead plastic DIP
T =8-lead metal can (T0-99)

Absolute Maximum Ratings
Supply Voltage
REF·01 ................................................. +40V
REF-01 C, 0 .........................................+30V
Internal Power Dissipation .................... 500 mW
Output Short Circuit Duration ............... Indefinite
Storage Temperature
Range ................................. -65'C to +150'C
Operating Temperature Range
REF·01, .............................. -55'C to +125'C
REF·01 C,D .............................. O·C to +70'C
Lead Soldering Temperature
(60 Sec) ............................................ +300·C

Thermal Characteristics
Max. Junction Temp.
Max. Po TA <50'C
Therm. Res 9JC
Therm. Res. 9JA
For TA >50'C Derate at

3-706

8-Lead
PlastiC DIP
+125'C

8·Lead CeramIc
Metal Can
+175'C

8-Lead To-99
Metal Can
+175'C

468mW

833mW

658mW

-

45'Cm

50'Cm

160'CIW

150'Cm

190'Cm

6.25mWrC

8.33mWrC

5.26mWrC

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

REF-Ol
Electrical Characteristics
(V's = ±15V and T'A= +25"C unless otherwise noted)
Parameters
,
Output Voltage
Output Adjustment Range
Output Voltage Noise1
Supply Voltage
Une Regulation2
Load Regulation£!
Turn-on Setting Time
Supply Current
Load Current
Sink Current
Short Circuit Current

Test CondHlons
ILOAD= OmA
RTRIM = 10 kn
0.1 Hz to 10Hz

REF-01
Typ
10.00
:1:3.3
20

Min
9.95
:1:3.0

Max
10.05

UnHs
V
%
J.1Vp-p
V
%IV
%/rnA

30

12

40

Vs = +13V to +33V
ILOAD = OmA to 10rnA
To :ID.1%of Final Value
No Load

0.006
0.006
5.0
1.0
21
-0.5
30

10
-0.3
Vour= 0

0.010
0.010

J.L5
1.4

mA
mA
mA
rnA

I

Electrical Characteristics
(Vs = ±15V and -55"C~ TA~ +125"C unless otherwise noted)
Parameters
Output Voltage Change With
Temperature 3, 4
Output Voltage Temperature
CoefficienF
Change in VOUT Temperature
Coefficient With Output Adjustment
Une Regulation'=!
Load Regulation£!
Notes:

REF-01
Typ

Max

UnIt

Over Temp. Range

0.18

0.45

%

Over Temp. Range

10

25

ppml°C

RrRIM = 10kn
Vs = +13V to +33V
ILOAD = OmA to 8mA

0.7
0.009
0.007

0.015
0.012

ppm/%
%IV
%/mA

Test CondHlons

Min

I

1. Guaranteed by design.
2. Une and load regulation specifications include the eHects of sol heating.
3. Output voftage change with telJllOralure = VUAX"VU1N X 100"10

10V
4. Output voltage change with temperature specification applies untrimmed, or trimmed to +10V.
5. Output voltage temperature coefficient =Output voftage change wtth temperature X 1rP
(100%) (180"C)

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-707

REF·Ol
Electrical Characteristics

(Vs = ±15V and TA= +25°C unless otherwise noted)
Parameters
Output Voltage
Output Adjustment Range
Output Voltage Noise1
Supply Voltage
Line Regulation2
Load Regulation2

Turn-on Settina Time
Supply Current
Load Current
Sink Current
Short Circuit Current
Notes:

Test CondItions
ILOAD=OrnA
RrRIM= 10 kn
0.1 Hz to 10Hz
Vs = +13V to +33V
ILOAD = OmA to SmA
ILOAD = OmA to 4rnA

REF·01C
Typ
9.90 10.00
:¥2..7 ±a.3
25
12
0.009
0.006
0.006

MIn

To ±O.1 % of Final Value
No Load
S.O
-0.2
Vour=O

5.0
1.0
21
-0.5
30

Max
10.10

35
30
0.015
0.Q15
0.015

REF-01D
Typ
Max UnHs
10.00 10.150
V
9.S50
%
:¥2..0
±a.3
25
uVo~
12
V
30
0.04
%IV
0.012

Min

0.009

1.6
S.O
-0.2

5.0
1.0
21
-0.5
30

0.04

%/mA

uS
2.0

rnA
rnA
rnA
rnA

1. Guaranteed by design.
2. Une and load regulation specifications include the effects of sel heating.

3-708

Raytheon Semiconductor

For More Infoonalion. call 1-800-722·7074.

REF-Ol
Electrical Characteristics
(Vs = +15V, O°C S TAS +7000, and hIT = 0 unless otherwise noted)
Parameters
Output Voltage Change With
Temperature 3, 4
Output Voltage Temperature
CoefficienF
Change in VOUT Temperature
Coeffieclent With Output Adjustment
Une Regulation2
Load Regulation2
NOles:

Test Conditions

REF"()1C
Min Typ
Max

REF-01D
Min Typ
Max

Units

Over Temp. Range

0.14

0.45

0.49

1.7

%

Over Temp. Range

20

65

70

250

pprn/OC

0.7
0.020
0.020

0.025
0.025

pprrv%
%IV
%JmA

RmIM= 10kn
Vs = +13V to +30V
ILOAD = OmA to 8mA

0.7
0.011 0.018
0.008 0.018

1. Guaranteed by design.
2. Une and load regulation specifications include the effects 01 sal healing.
3, Output voltage change with telJll8rature = VMAx-VMIN X 100'1'0
10V

4. Output voltage change with temperature specification applies untrimmed, or trimmed to +10V.
S. Output voltage temperatura coefficient =Output voltage change wfth temperature X 10&
(100'1'0) (7O"C)

Typical Applications
Current Sink

Current Source
+15V

lour

2
V
Voltage Compliance:
+ s
-25V to +3V
Vour 6

REF-Ol

2

V
+ s

Voltage Compliance:

6 -3V to +25V

I

VOUT

REF-Ol

Trim

R

Trim

R

Gnd

IOUT=

VOUT

R

-15V

lOUT

For More Information, call 1-800-722-7074.

IOUT= VOUT +1 rnA

+1 rnA

Raytheon Semiconductor

R

3-709

REF-Ol
Typical Performance Characteristics
Maximum Load Current VS. Differential
Input Vottage

35
~

.s.

~

..!3
E
:J
E

i

r

30

Output Adjust
+15V

Short Circuit Protection

""-..l

25

2
+Vs
6
Vour

500 mW Maxim~m ~
Dissipation

20
15

I

10

REF-01

TA=+25°C

5

I

I

o

o

10

Output

20

RTRIM
10K

Trim 5

25

65-0552

Normalized Load Regulation
(DILOAD = 10 mAl VS. Temperature
1.4

E~

y

1.3
c + 1.2
0 ....

i j

L'

1.1

~~ 1.0
a::

i

i a::
...J!

0.9
0.8

:::i 0.7
0.6
-60

......

./

....

./

V

+Vs = +15V
-20

+20
+60
TA ("C)

+100

!

+140

The REF-01 trim terminal can be used to adjust the
output voltage over a 1OV :t'300mV range. This
feature allows the system designer to trim system
errors by setting the reference to a voltage other than
10V. Of course, the output can also be set to exactly
10.000V or to 10.240V for binary operation.
Adjustment of the output does not significantly affect
the temperature performance of the device. Typically
the temperature coefficient change Is 0.7 ppmlOC for
100mV of output adjustment.

Burn-In Circuit
+18V
R1
2K
±10%

Normalized Line Regulation VS. Temperature

_ P'

Ell)

1.4
1.3

... V

c c:t! 1.2
0 ....

i j

1.1

~~ 1.0
a:: i 0.9
CIIa:: 08

:5!::; 0.7.

0.6
-60

2W

io

--

....... V

V
REF-01

....... ~

-20

+20
+60
TA (OC)

2K

+100

!

+140

-18V

3-710

Raytheon Semiconductor

65-0553

For More Inlamation, call1-800-722-7074.

REF-Ol
Schematic Diagram
r-____~--~------~--------------~~+vs
(2)

021

.")-<~+---""",---o

Output
(6)

Rl
12K

Trim
t--'VI.I\r--o (5)

Tempco
(3)

Ground
(4)
6&0546

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-711

REF-Ol

3-712

Raytheon Semiconductor

For More Infcrmation, call HlOO..722..7074.

REF-02
REF·02
+5V Precision Voltage Reference
Description

Features

The REF-02 Precision Voltage Reference contains a
bandgap reference using thin-film resistors, a step-up
amplifier, short circuit protection, and a zener trim
network. The REF-02's +5V output shows excellent
stability for large changes of temperature, load
current, and input voltage. A trim pin is provided that
can change the output voltage by at least 3% with
little effect on temperature coefficient. A tempeo pin
also provides a voltage that varies linearly with
temperature, typically from +470 mV to +830 mV over
the military temperature range.

•
•
•
•
•
•
•
•

+5V output - ±D.3%
Adjustable - ±3%
Excellent temperature stability - 3 ppmfC
Low noise - 10 IlVp-p
Wide input voltage range - +7V to +40V
No external components
Short circuit proof
Low power consumption - 10 mW

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-713

REF-02
Connection Information
8-Lead
Dualln·L1ne Package
(Top View)

Ordering Information

8-Lead T0-99
Metal can
(Top View)

_70
Pin
1
2
3
4
5
6
7
8

~

Package

Operating
Temperature
Range

REF·02CD
REF·02DD
REF·02CN
REF·02DN

D
D
N
N

O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C

REF·02D
REF·02DI8838
REF·02T
REF·02T/8838

D
D
T
T

·SS·C to +12S'C
·SS·C to +12S'C
·SS·C to +12S'C
·SS·C to +12S'C

Part Number

Notes:
I883B suffix denotes MiI-8td-883. Level B processing
D • 8-lead ceramic DIP
N = 8-lead plastic DIP
T =8-lead metal can (TO-99)

Function
NC
+Vs
Tempco
Ground
Trim
Output
NC
NC

Absolute Maximum Ratings
Supply Voltage
REF-02 •..........•........•.......•.•...•..•....•..•.•. +40V
REF·02C,D .......................................... +30V
Internal Power Dissipation ..........•..•..•.•. 500 mW
Output Short Circuit Duration ............... Indefinite
Storage Temperature
Range ................................. -65·C to +150'C
Operating Temperature Range
REF·02 ..•....................•....... -55·C to +125'C
REF-02C,D ..................•..........• O·C to +70'C
Lead Soldering Temperature
(60 Sec) ...•...•...........•........•.•.•.•.•....•.. +300·C

Thermal Characteristics
8-Lead
Plastic
DIP

8-Lead
Ceramic
DIP

8-Lead
T0-99
Metal Can

Max. Junction Temp.

+125'C

+17S'C

+17S'C

Max. Po TA U-I.,;IW

loU-I.,;/W

ll:lU-I.,;/W

6.2SmWrC

8.33mWrC

S.26mWrC

Therm.ResOJC
I nerm. Hes. tlJA
For TA >SO'C Derate at

3-714

Raytheon Semiconductor

For More Information. call 1-800-722·7074.

REF·02
Electrical Characteristics
(Vs = +15V and TA = +25"C unless otherwise noted)

REF.()2JH
Parameters
Output Voltage
Output Adjustment Range
Output Voltage Noise1
SuPply Voltage
Une Regulation2
Load Regulation2
Tum-on Setting Time
Supply Current
Load Current
Sink Current
Short Circuit Current
TempeoVoltage OutputS

Test CondHlons
ILOAD =OmA
RmIM= 10kn
0.1 Hz to 10Hz

Min
4.975
:!B.O

Typ

5.000
±B.O
10
0.006
0.006
5.0
1.0
21
-0.5
30
630

10
-0.3
VOU1'= 0

UnHs
V

15
40
0.010
0.010

J,lVD-D
V
%lmA

1.4

mA

%

7
Vs =+8Vto+33V
Ii00n = OmA to 10mA
To :lD.1 % of Final Value
No Load

Max
5.025

%IV
~
rnA

mA
mA
mV

Electrical Characteristic
(Vs = +15V and -55"C S TA S +125"C unless otherwise noted)
Parameters
Oulput Voltage Change With
Temperature3,4
Outout Voltaae Temoorature
CoefficienF
Change in VOlJl" Temperature
Coefficient With Output Adjustment
Une RegulationZ
Load Regulation~
Output Voltage
Temperature Coefficients
NOles:

REF-02
Typ

Max

UnHs

Over Temp. Range

0.18

0.45

%

Over Temp. Range

10

25

ppmI"C

RmIM= 10kn
Vs = +8V to +33V
ILOAD = OmA to 8mA

0.7
0.009
0.007

0.015
0.012

Test CondHlons

Min

2.1

ppmtok

%IV
%/mA
mV/oc

1. Guaranteed bv design.

2. Una and load regulation specifications include !he effects 01 sel healing.
3. ~ VIllage change with temperature = (VMAX - VU1W X 100'YD'SV
4. 0uI!U wltage change with temperatll8 speciflCBlion lIRlIies IDrimmed, or trimmed 10 +5'1.
5. 0uI!U voltage temperatll8 coeffICient =(0uI!U voltage change with teql8l'Blure X 10ev[ (100%) (180'C)]
6. Uml current in or out 01 pin 3 10 50nA end Umi C8jl8c1ance on pin 310 3OpF.

For More InIamaIion, call 1-800-722-7074.

Raytheon Semiconductor

3-715

REF-02
Electrical Characteristics
(Vs = +15V and TA= +25"C unless otherwise noted)
Test CondHlons
Parameters
Output Voltage
ILOAD =OmA
Output Adjustment Range RrRIM = 10ka
Output Voltage Noise 1
0.1 Hz to 10Hz
Supply Voltage
Une Regulation2
Vs = +8V to +33V
Load Regulation2
Turn-on Setting Time
Supply Current
Load Current
Sink Current
Short Circuit Current
Tempco Voltage Output3

Min
4.950
f!2..7
7.0

ILOAD= OmA to 8mA
ILOAD = OmA to 4rnA
To±D.1% of Final Value
No Load
8.0
-0.2
Vour= 0

REF-02C
Typ
Max
5.000 5.050
is.O
12
18
30
0.009 0.015

REF-02D
Typ Max UnHs
Min
4.900 5.000 5.100
V
f!2..0 is.O
%
12
J.l.Vp-p
V
7.0
30
0.012 0.04 %/V

0.006 0.015

%/mA

5.0
1.0
21
-0.5
30
630

1.6
8.0
-0.2

0.009 0.04
5.0
1.0
2.0
21
-0.5
30
630

pS
rnA
mA
mA
mA
mV

NOles:
1. Guaranteed by design.
2. Une and load regulation specifications include the eHects of sal heating.
3. Umil current in or out of pin 3 to 50nA and limit capacilanoe on pin 3 to 3OpF.

3-716

Raytheon Semiconductor

For Mora Information. call HIOO-722-7074.

REF-02
Electrical Characteristics
(Vs = +15V, 0° and TA = OOC ~ TA ~ +70°C and lour = 0 unless otherwise noted)
REF-02C

Parameters
Output Voltage Change With
Temperature3,4
Output Voltage Temperature
Coefficients
Change in Vour Temperature
Coefficient With Output Adjustment
Une Regulatio~
Load Regulation2
Tempco Voltage output
Temperature Coefficients
Notes:

REF-02D

Typ

Max

Over Temp. Range

0.14

Over Temp. Range
RrRIM= 10kn
Vs = +8V to +33V
ILOAD = OmA to 5mA

Test ConclHlons

Min

Min

Typ

Max

UnHs

0.45

0.49

1.7

%

20

65

70

0.7
0.011
0.008

0.Q18
0.018

2.1

250 ppl'Tll"C

0.7
ppm/%
0.020 0.025 'YoN
0.020 0.025 'Yo/mA
2.1

mVfOC

I. Guaranteed by design.
2. Una and load regulation spec:ilications include the effects 01 sel heating.
3. Output voltage change with temperature =

(VMAX ' VMIt« lOOo/J5V

4. Outplt voltage change with temperature specification applies untrimmed. or trimmed to +5V.
5. OuIplt voltage temperature coefficient =(OUtput voltage change wfth temperature X 10Sl/[(IOO%)(70'C)]
6. Uml current in or out 01 pin 3 to 50nA and Om. capacitance on pin 3 to 3OpF.

I
For Mora Information, call 1-800·722·7074.

Raytheon Semiconductor

3·717

REF·02
Typical Performance Characteristics
Maximum Load Current vs.
Differential Voltage
35

<'
.5.

r

30

JE

"""-L

15

E

:!II

J--.......

+Vs
VOUT 6

I

10

';c

2

500 mW Maxim~m
Dissipation

20

:I

+15V

Short Circuit Protection

25

Q

Output Adjustment

REF-02

TA=+25°C

5

!

J

o

o

10

20

Output

Tempco

Trim

3

25

RlRI...
10K

5

Gnd

4

-

Normalized Load Regulation
(AllOAD = 10 mA) vs. Temperature

j::-g-

1.4
1.3

V

c~ 1.2
0--

i g 1.1
~~ 1.0
a:

Q

'8 a:•
..J~

.....

./

0.9

,,/'

0.8
0.7
O.S

'L

/
+Vs -+15V

".

-so

-20

+20

+so

+100

!

+140

65-0971

The REF-D2 trim terminal can be used to adjust the
output voltage over a 5V ±300mV range. This feature
allows the system designer to trim system errors by
setting the reference to a voltage other than 5V. Of
course, the output can also be set to exacUy 5.000V
or to 5.12V for binary operation. Adjustment of the
output does not significantly affect the temperature
performance of the device. Typically the temperature
coefficient change is O.7ppmI"C for 1OOmV of output
adjustment.

TA (OC)

Burn-In Circuit
+18V

Rl

....F='tQ?'

Normalized Line Regulation vs. Temperature
1.4
1.3

~.!.

1.2

i.§

1.1

i~ 1.0

a: :i' 0.9
! a: 0.8

:::;!
:::;

0.7
O.S

-so

v

--

~

-20

....... ~ ""

2K
:1:100/0
2W

VOUT

~

6

REF-02
2K

+100

I

+140

-18V

3-718

Raytheon Semiconductor

For More Infcnnation. call 1-1100-722-7074.

REF-02
Typical Applications
Figure 3 shows how the REF-02 can be connected
with an OP-07 to create an electronic thermometer.
The circuit uses the +5V reference oulput and the op
amp to level shift and amplify the 2.1 mVFC Tempco
oulput into a voltage signal dependent on the ambient
temperature. Different scaling can be obtained by
selecting appropriate resistors from the table in Agure
3, giving oulput slopes calibrated in degrees Celsius
or degrees Fahrenheit.
To calibrate, first measure the voltage on the Tempco
pin (VTEM PCO> and the ambient room temperature (TA
in °C). Put those values into the follOWing equation:
VTEMPCO (in millivolts)
(S) (TA + 273)

X=

Where S = Slope factor for your circuit selected from
the table in Rgure 3 (in millivolts per OC or oF).

Then tum the circuit power off, short VOUT 9 pin 6) of
the REF-02 to ground, and while applying exactly
100.00mV to the op amp oulput, adjust RB2 so that Vs
= (X) (100mV). Now remove the short and the 100mV
source, reapply circuit power and adjust RrRIM so that
the op amp oulput voltage equals (TN(S), The
system is now exactly calibrated.
For remote sensor applications a 1.50 resistor (Rs)
must be connected in series with the Tempco pin to
isolate it from cable capaCitances. Low temperature
coeffICient metal film resistors must be used for RA,
Rs and Re·
Better grades of REF-02 will provide greater accuracy
over a wider range of temperatures. To decrease op
amp input errors, use an OP-27 instead of an OP-07.
A system using a REF-02 and an OP-07 will provide a
typical accuracy of ::W.5% over the military
temperature range.

+15V

2

V
+ s

lour

2

Voltage Compliance:
-25V to +3V

Voltage Complianoe:
+Vs
-3V to +25V
Vour 6

VOUT 6
REF-02
Tampco

3

Trim

REF-02
R

Tampco

3

Trim

lour- Vour
+1 rnA

R

lour

R

lour -

V
..QY! +1 rnA

-15V

R

65-0074

65-0973

Figure 1. Current Source
Figure 2. Current Sink

For More Information, oaII1-800-722-7074.

Raytheon Semiconductor

3-719

REF·02
+15V
2
Vs

Rc

VOUT 1-'6"--_+-1--+ VREF
RF-02
Trim 1-'5"---+-I-+<

Note: OP-07 pin numbers shown
are for 8-lead packages.
·Up to 10 feet of shelded 4-conductor cable.

Ac

TCVOUT - (2 .1 mVI"C) ( 1 + RA IIRB )

Ac

Your - (H RA IIRB ) VTEMPCO -

Where RB • RBI +R82

Ac

RA) (Vour)

(

RBSlstor VaiuBS
TevOUT Slope(s)
Temperature Range

1OmVI"C
-5S"C to +12S"C

100mVI"C
-55"C to +12S"C

1OmVfOF

Output Voltage Range

-o.ssV to +1.2SV

-S.SV to 12.5V

-.67V to +2.S7V

OValO"C

OValO"C

OValO°F

RA (±1 % Resistor)

9.09Kn

1SKn

8.2SKn

RB1 (±1% Resistor)

1.SKn

1.82Kn

1.0Kn

R82 (Potentiometer)

200n

soon

200n

S.11Kn

84.SKn

7.SKn

Zero Scale

Rc (±1% Resistor)

Figure 3. Precision Electronic Thermometer

3-720

Raytheon Semiconductor

For Mora Infonnation, call 1-800-722-7074.

REF-02
Schematic Diagram
r-----~--~----~--------------~-o~s
(2)

Q21

.......-----o

~--+------

Output
(6)

R1
12K

Trim
t--"WI..--oO (5)

Tempco
(3)

L..-------+---------__--+-____I-----oGround
(4)

I
For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-721

REF·02

3-722

Raytheon Semiconductor

For Mora Information. call 1-800-722-7074.

RC4190
RC4190
Micropower Switching Regulators
Description
The RC4190 monolithic IC is a low power switch
mode regulator intended for miniature power supply
applications. This DC-to-DC converter IC provides all
of the active components needed to create supplies
for micropower circuits (load power up to 400 mW, or
up to 1OW with an external power transistor). Contained internally are an oscillator, switch, reference,
comparator, and logic, plus a discharged battery
detection circuit.
Application areas include on-card circuits where a
non-standard voltage supply is needed, or in battery
operated instruments where a 4190 can be used to
extend battery lifetime.
These regulators can achieve up to 85% efficiency in
most applications while operating over a wide supply
voltage range, 2.2V to 30V, at a very low quiescent
current drain of 215 JlA.
The standard application circuit requires just seven
external components for step-up operation: an
inductor, a steering diode, three resistors, a low value
timing capacitor, and an electrolytic filter capacitor.
The combination of simple application circuit, low
supply current, and small package make the 4190
adaptable to a wide range of miniature power supply
applications.
The 4190 is most suited for single ended step-up
(Vour > VIN) circuits because the NPN internal switch
transistor is referenced to ground. It is complemented
by another Raytheon micropower switching regulator,
the 4391, which is dedicated to step-down (Vour < VIN)
and inverting Vour = -VIN) applications. Between the
two devices the ability to create all three basic switch-

For More InfcnnaIion. call 1-800-722-7074.

ing regulator configurations is assured. Refer to the
4391 data sheet for step-down and inverting applications.
With some optional external components the application circuit can be designed to signal a display when
the battery has decayed below a predetermined level,
or designed to Signal a display at one level and then
shut itself off after the battery decays to a second
level. See the applications section for these and other
unique circuits.
The 4190 micropower switching regulator series
consists of three devices, each with slightly different
specifications. The RM4190 has a 1.5% maximum
output VOltage tolerance, O.2"k maximum line regulation, and operation to 30V. The RC4190 has a 5.0%
maximum output voltage tolerance, 0.5% maximum
line regulation, and operation to 24V (RC4190) and
30V (RC4190A). Other specifications are identical.
Each type is available in plastic and ceramic DIPs, or
SO-8 packages.

Features
•
•
•
•
•
•
•
•
•
•

High efficiency - 85% typical
Low quiescent current - 215 ~
Adjustable output - 1.3V to 30V
High switch current - 200 rnA
Bandgap reference -1.31V
Accurate oscillator frequency - ±1 0%
Remote shutdown capability
Low battery detection circuitry
Low component count
8-lead packages including small outline
(S0-8)

Raytheon Semiconductor

I
3-723

RC4190
Ordering Information

Connection Information
B-Lead

DIP
(Top View)

Small Outline

Part Number

SO-S

Package

Operating
Temperature
Range

M
M
N

OOCto +70OC
OOCto +70OC
OOCto +70OC

D
D

-55OC to +1250C
-55OC to +1250C

(Top View)
. RC4190M
RC4190AM
RC4190N

10

RM4190D
RM4190D/8838

Notes:
/8838 suffix denotes Mi~Std-883. level 8 processing

Pin
1

2
3
4
5
6
7
8

Function
Low Battery (Set) Resistor (LBR)
Timing Capacttor (Cx)
Ground
Extemallnductor (Lx)
+Supply VoHage (+VJ
Reference Set Current (Iel
Feedback VoHage (V.,J
Low Battery Detector Output (LBO)

N ~ 8-lead plastic DIP
D =8 lead ceramic DIP
M =8-lead plastic sole

Absolute Maximum Ratings(1)
Supply Voltage (Without External Transistor)
RM4190, RC4190A ................................. +30V
RC4190 ................................................... +24V
Storage Temperature
Range .................................... -65'C to +150'C
Operating Temperature Range
RM4190 .................................. -55·C to +125'C
RC4190, RC4190A ...................... O·C to +70'C
Switch Current .................................. 375 rnA Peak
Note:
1. •Absolute maximum ratings' are those beyond which the
safety of the device cannot be guaranteed. They are not
meant to imply that the device should be operated at
these limits. If the device is subjected to the limits in the
absolute maximum ratings for extended periods. its
reliability may be impaired. The tables of Electrical
Characteristics provide conditions for actual device
operation.

Thermal Characteristics

Max. Junction Temp.
Max. Po TA <50'C
Therm. Res aJC
Therm. Res. aJA
For TA >50'C Derate at
3-724

8-Lead
Plastic
DIP
+125OC
468mW

160OC/w
6.25mWfOC

8-Lead
CeramiC
DIP
+175OC
833 mW
45°C/W
150°C/W
8.33mWfOC

Small
Outline
SO-8
+125°C
300mW

240°C/W
4.17mWfOC

Raytheon Semiconductor

For More Information. call HIOQ-722·7074.

RC4190
Functional Block Diagram
4190

65-2686

Electrical Characteristics
Ie =5.0 J.IA over the full operating temperature range unless otherwise noted.)

(+vs =+6.ov,

Parameters
Supply VoHaae
Reference VoHage
(Intemal)
Supply Current

SymbOl

CondHlons

+V
VREf

Isv

RM4190/RC4190A
Min
Typ
Max

RC41901RC4190A
Min
Typ
Max

2.6
1.25

2.6
1.20

Measure at Pin 5

UnHs

1.31

24130
1.42

V
V

1.31

30
1.37

235

350

235

350

JJA

0.2
0.5

0.5
1.0

0.5
0.5

1.0
1.0

%Vo
%Vo

5.0

50

5.0

14=0
Line Regulation
Load Regulation
Reference Set Current
Switch Leakage Current

L.
Ie
lco

0.5 VOUT < Vs < VOUT
Vs = 0.5 VOUT
P = 150mW
1.0

30

50
30

JJA
JJA

30

30

JJA

Supply Current
(Disabled)

Iso

Ve:!>200 mV

Low Battery

IUlD

Va -= O.4V,
V1 = 1.1V

Output Current
OSCillator Frequency
Temperature Drift

For More Information, call 1-800-722-7074.

1.0

V4 = 24V (RC4190)
30V (RM4190,
RC4190A)

500

1200
±200

Raytheon Semiconductor

500

1200

JJA

±200

ppmfOC

3-725

RC4190
Electrical Characteristics
(+vs= +6.0V, Ie = 5.0 IJA, and TA = +25°C unless otherwise noted.)

Parameters
Supply Vottage
Reference vonage
(Intemal)
Swttch Current
Supply Current

Symbol

Conditions

+Vs
VREF
Isw
ISY

V. =400 mV
Measure at Pin 5

RM4190llRV419OJ
RC4190A
Min
Typ
Max

RC4190/RV419OJ
RC4190A
Min
Typ
Max

2.2
1.29

2.2
1.24

100

1.31

30
1.33

200
215

300

100

Units

1.31

24/30
1.38

V
V

200
215

300

~

rnA

I. = 0
Efficiency
Line Regulation
Load Regulation

ef

Operating Frequency

Fo

Range
Reference Set Current
Switch Leakage Current

lco

V. = 24V (RC4190)
30V (RM4190,
RC4190A)

'so
II

Supply Current
(Disabled)
Low Battery
Bias Current
Capacttor Charging
Current
Oscillator Frequency
Tolerance
Capacitor Threshold
VoHage +
Capacttor Threshold
VoHage Feedback Input
Current
Low Battery
Output Current

3-726

85
0.04
0.2

0.5

0.1

25

75

1.0

5.0
0.01

50
5.0

Ve:>200 mV

0.1

5.0

VI = 1.2V

0.7

0.7

~

8.6

B.6

~

±10

±10

%

+Vrnx

104

1.4

V

-VTHX

0.5

0.5

V

0.1

0.1

~

1500

~

0.5 Vour < Vs < VOUT

L.

Vs = +0.5 Vour
PL = 150mW

Ie

lex

'FS
'LBO

V7 = 1.3V
Va = OAV,

500

1500

85
0.04
0.2

0.5

%Vo

0.5

%Vo

0.1

25

75

kHz

1.0

5.0
0.01

50
5.0

~

0.1

5.0

~

0.2

500

%

~

VI = 1.lV

Raytheon Semiconductor

For Mora Information, call 1-800-722-7074.

RC4190
Typical Performance Characteristics
Minimum Supply Voftage
vs. Temperature

Quiescent Current vs. Temperature

4.0

300
250

3.0

I

I

1-2~0

I

I

I
I

215

€

::

2.0

I""--

.ov

i

1.8V

150

~

-

195

200
2.4V "'"""'-

100

1.0

o
-75

-50

-25

o

50

!

Vs -+6V-

o

-75

+25 +50 +75 +100 +125

-50

-25

I

o

TA("C)

Reference Voltage vs. Temperature
+2.0
+1.5

1.32

./

./

v

l

~

+1.0
:g +0.5
~
0

/'"

~

z...... -0.5
-1.0

/

.E

I

~

128
-75

~

OSCillator Frequency vs. Temperature

1.33

1.29

I

+25 +50 +75 +100 +125
TA (OC)

-50

-25

0

..... ..........

---

-50

-25

TA (OC)

o

~

...-

!

-1.5
-2.0
-75

+25 +50 +75 +100 +125

.....

~

-'

+25 +50 +75 +100 +125
TA("C)

Minimum Supply Voltage
vs. Temperature
+2

\

\

~

"-2

o

5

10

15

20

25

!

30

+Vs(V)

For More Information, call 1-800-722·7074.

Raytheon Semiconductor

3-727

RC4190
Principles of Operation
Simple Step-Up Converter
The most common application, the step-up regulator,
Is derived from a simple step-up (VOUT > VBAT) DC-toEC Converter (Figure 1).

rr~ IR:}~
(-)

8lH648

Figure 1. Simple Set-Up

When swHch S Is closed, the battery voltage is applied
across the inductor L Charging current flows through
the inductor, building up a magnetic field, increasing
as the switch is held closed. While the switch is
closed, the diode 0 is reverse biased (open circuit)
and current is supplied to the load by the capacitor C.
Until the switch is opened, the inductor current will
increase linearly to a maximum value determined by
the battery voltage, inductor value, and the amount of
time the swHch Is held closed (1MAl( =VuJL x Too)'
When the swHch Is opened, the magnetic field collapses, and the energy stored in the magnetic field is
converted into a discharge current which flows
through the inductor in the same direction as the
charging current. Because there Is no path for current
to flow through the switch, the current must flow
through the switch, the current must flow through the
diode to supply the load and charge the output
capacitor.
If the switch is opened and closed repeatedly, at a rate
much greater than the time constant of the output RC,
then a constant de voltage will be produced at the
output.
An output voltage higher than the input voltage is
possible because of the high voltage produced by a
rapid change of current in the inductor. When the
switch Is opened, the inductor voltage will instantly
rise high enough to forward bias the diode, to VOUT +
Vo'

3-728

In the complete 4190 regulator, a feedback control
system adjusts the on time of the switch, controlling
the level of inductor current, so that the average
inductor discharge current equals the load current,
thus regulating the output voltage.

Complete Step-Up Regulator
A complete schematic of the minimum step-up
application is shown in figure 2. The Ideal switch In the
DC-to-DC Converter diagram is replaced by an open
collector NPN transistor Q1. CF functions as the output
filter capacitor, and 01 and Lx replace 0 and L
When power is first applied, the current in R1 supplies
bias current to pin 6 (Ie)' This current is stabilized by a
unity gain current source amplifier and then used as
bias current for the 1.31 V bandgap reference. A very
stable bias current generated by the bandgap is
mirrored and used to bias the remainder of the chip. At
the same time the 4190 Is starting up, current will flow
through the inductor and the diode to charge the
output capacitor to VBAT - Vo'
At this point, the feedback (pin 7) senses that the
output voltage is too low, by comparing a division of
the output voltage (set by the ratio of R2 to R3) to the
+1.31 V reference. If the output voltage Is too low then
the comparator output changes to a logical zero. The
NOR gate then effectively ANDs the oscillator square
wave with the comparator signal; if the comparator
output is zero AND the oscillator output is low, then
the NOR gate output is high and the switch transistor
will be forced on. When the oscillator goes high again,
the NOR gate output goes low and the switch transistor will turn off. This turning on and off of the switch
transistor performs the same function that opening
and closing the switch in the simple DC-to-DC Converter does; i.e., it stores energy in the inductor during
the on time and releases Hinto the capacitor during
the off time.
The comparator will continue to allow the oscillator to
turn the switch on and off until enough charge has
been delivered to the capaCitor to raise the feedback
voltage above 1.31V.

Raytheon Semiconductor

For More Information. cafl HIOO-722-7074.

RC4190
Thereafter. this feedback system will vary the duration
of the on time In response to changes In load current
or battery voltage (see Figure 3). If the load current
increases (waveform C). then the transistor will remain
on (waveform D) for a longer portion of the oscillator

cycle (waveform B). thus allowing the inductor current
(waveform E) to build up to a higher peak value. The
duty cycle of the switch transistor varies in response
to changes In load and time.

(+)

R1

+

-

01
4
r- 4<-----4190-------1

6 Ie

@

5 +Vs
VBAl

1
1
1
1
1

REF

OSC

+C

1
1
1
1

RL

0- ---Xls J
Cx

Gnd

3--

LBR LBO

R2

17

F

@
~ILOAD

R2 1)

VOUT = VREF (R3 +

R3

2

NC

NC

(-)

Figure 2. Complete Step-Up Regulator
_1.4V

®

®

_O.5V
(Internal)

r - _IL(Max)

@ _ _ _--.r-----I-

Cx

OSC

I LOAD

_OmA

®

_O.72V

(Internal)

I

VBEOI

_OV
_IMAX

®

CD
@)

_OmA
_IMAX

_OmA

10

_
VOUT + Vo VLX
_VMAX
_
0.3V (01 SAT)
85-2674

Figure 3. Step-Up Regulator Waveforms

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-729

RC4190
to meet the load current drain and the output voltage
will collapse. If the inductor value is too low or the
oscillator frequency too low, then the inductor current
will build up too high, causing excessive output
voltage ripple, or over stressing of the switch transistor, or possibly saturating the inductor.

The inductor value and oscillator frequency must be
carefully tailored to the battery voltage, output current,
and ripple requirements of the application (refer to the
Design Equations Section). If the inductor value is too
high or the oscillator frequency is too high, then the
inductor current will never reach a value high enough

R1
1M

Cr-

R4
5

+

Ie

111Fr
7

VFB

4190

+Vs

Lx

GND
R3

3

SOVs

R5=

- May not be Required

I MAX

65-2675

R4=10R5

Figure 4. High Power Step-Up Regulator
(With the addnion of a power transistor (TIP73) and a few components,
the 4190 can accommodate load power up to lOW)
Simple Step-Down Converter
Figure 5 shows a step-clown DC-to-DC Converter
(VOUT ~ VBAT) with no feedback control.

65-1644

When S is closed, the battery voltage minus the
output voltage is applied across the inductor. All of the
inductor current will flow into the load until the inductor
current exceeds the load current. The excess current
will then charge the capacitor and the output voltage
will rise. When S is opened, the voltage applied
across the inductor will discharge into the load. As in
the step-up case, the average inductor current equals
the load current. The maximum inductor current IMAX
will equal (VBAT - VOUT)/L times the maximum on time of
the switch transistor (TON)' Current flows to the load
during both half cycles of the oscillator.

Figure 5. Simple Step-Down Converter

3-730

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4190
replaces S of Figure 5, and R6 and R7 are added to
provide the base drive to the 2N2907 in the correct
polarity to operate the circuit properly.

Complete Step-Down Regulator
Most step-down applications are better served by the
4391 step-down and inverting switching regulator
(refer to the 4391 data sheet). However, there is a
range of load power for which the 4190 has an
advantage over the 4391 in step-down applications.
From approximately 500 mW to 2W of load power, the
4190 step-down circuit of Figure 6 offers a lower
component count and simpler circuit than the comparable 4391 circuit, particularly when stepping down a
voltage greater than 30V.

Greater Than 30V Step-Down Regulator
Adding a zener diode in series with the base of the
2N2907 allows the battery voltage to increase by the
value of the zener, with only a slight decrease in
efficiency. As an example, if a 24V zener is used, the
maximum battery voltage can go to 48V* when using
a 4190. Refer to Figure 7.

Since the switch transistor in the 4190 is in parallel
with the load, a method must be used to convert it to a
series connection for step-down applications. The
circuit of Figure 6 accomplishes this. The 2N2907

Note: The addition of the zener diode will not alter the
maximum change of supply. With a 24V zener, the
circuit will stop operating when the battery voltage
drops below 24V + 2.2V = 26.2V.
Maximum battery voltage is 54V when using RM4190 (30V + 24V).

R8

Rl
V...

B

Lx

01
lN914

D1
lND14

41110

V,.

7

LBR

At

R3

GNO

VIA.

R5

41110
LBR
GND

R4

'::'

R4. V.-1.31V
511A
'::'

VOUT

Lx

+V.

Ie

R4

Lx

R5.

260K

R6

=J2.
I.

R7

=~

For More Information, call1-800-722-7074.

R3
':'

85-2678
':'

Figure 6. Complete Step-Down Regulator

V,.

R4. V,-1.31V
511A

R6

=.!!!!.
I.

AS. 260K

R7

=~

-I

Figure 7. Step-Down Regulator Greater Than 30V

Raytheon Semiconductor

3-731

RC4190
Design Equations
The inductor value and timing capacitor (C,J value
must be carefully tailored to the input voltage, input
voltage range, output voltage, and load current
requirements of the application. The key to the
problem is to select the correct inductor value for a
given oscillator frequency, such that the inductor
current rises to a high enough peak value (I MAX) to
meet the average load current drain. The selection of
this inductor value must take into account the variation of oscillator frequency from unit to unit and the
drift of frequency over temperature. Use ±20% as a
maximum change from the nominal oscillator frequency.
The worst-case conditions for calculating ability to
supply load current are found at the minimum supply
voltage; use +Vs (min) to calculate the inductor value.
Worst-case conditions for ripple are at +Vs (max).
The value of the timing capacitor is set according to
the following equation:
2.4 x 1()6
o z - Cx(pF)

f (H)

The squarewave output of the oscillator is intemal and
cannot be directly measured, but is equal in frequency
to the triangle waveform measurable at pin 4. The
switch transistor is normally on when the triangle
waveform is ramping up and off when ramping down.
Capacitor selection depends on the application; higher
operating frequencies will reduce the output voltage
ripple and will allow the use of an inductor with a
physically smaller inductor core, but excessively high
frequencies will reduce load driving capability and
efficiency.
Find a value for the start-up resistor R1:

Where IA is the feedback divider current (recommended
value is between 50 ~ and 100 ~).
Step-Up DeSign Procedure
1. Select an operating frequency and timing
capacitor as shown above (10kHz to
40kHz is typical).
2. Find the maximum on time (add 5 J,1S for the
turn-off base recombination delay of 01):

TON =

1

"'2F+5 ps
o

3. Calculate the peak inductor current IMAX (if
this value is greater than 375 rnA, then an
external power transistor must be used in
place of 01):

where:
Vs = supply voltage
V0 = diode forward voltage
IL = dc load current
Vsw = saturation voltage of 01 (typ O.5V)
4. Find an inductance value for Lx:

Lx (Henries) =

(

Vs-Vsw )TON
1MAl(

The inductor chosen must exhibit approximately this value at a current level equal to IMAX
5. Calculate a value for the output filter
capacitor:
VI
CF (J.LF) =

TON

(

SMAX+I)

-v;;V

L

R

R1 = Vs -1.2V
5~

where VR = ripple voltage (peak)

Find a value for the feedback resistors R2 and R3:
R2 =Vour -1.31V
IA

1.31V

3-732

Step-Down Design Procedure
1. Select an operating frequency.
2. Determine the maximum on time (TON) as in
the step-up design procedure.

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4190
3. Calculate IMAX :

5. If the efficiency is poor, go back to (1) and start
over. If the ripple is excessive, then Increase the
output filter capacitor value or start over.

'!lAX -

Compensation

5. Calculate a value for the output filter capacitor:

CF~)=

(TON) (

evs - VOUT) 'MAX

+'L )

VOUT
VR

AHemate Design Procedure
The design equations above will not work for the
certain input/output voltage ratios, and for these
circuits another method of defining component values
must be used. If the slope of the current discharge
waveform is much less than the slope of the current
charging waveform, then the inductor current will
become continuous (never discharging completely),
and the equations will become extremely complex.
So, if the voltage applied across the inductor during
the charge time is greater than during the discharge
time, used the design procedure below. For example,
a step-down circuit with 20V input and 5V output will
have approximately 15V across the inductor when
charging, and approximately 5V when discharging. So
in this example, the inductor current will be continuous
and the alternate procedure will be necessary.
1. Select an operating frequency (a value between
10kHz and 40 kHz is typical).
2. Build the circuit and apply the worst case conditions to it, Le., the lowest battery voltage and the
highest load current at the desired output voltage.
3. Adjust the inductor value down until the desired
output voltage is achieved, then go a little lower
(approximately 20%) to cover manufacturing
tolerances.
4. Check the output voltage with an oscilloscope for
ripply, at high supply voltages, at voltages as high
as are expected. Also check for efficiency by
monitoring supply and output voltages and currents [eft =(VQIT) (IQIT)/(+Vsl(lsv) x 100%$].
For More Infcnnation, call 1-800-722-7074.

When large values ( >50 ~ are used for the voltage
setting resistors, R2 and R3 of Figure 2, stray capacitance at the VFB input can add a lag to the feedback
response, destabilizing the regulator, increasing low
frequency ripple, and lowering efficiency. This can
often be avoided by minimizing the stray capaCitance
at the VFB node. It can also be remedied by adding a
lead compensation capacitor of 100 pF to 10 nF In
parallel with R2 in Figure 2.

Inductors
Efficiency and load regulation will improve if a quality
high 0 inductor is used. A ferrite pot core is recommended; the wind-yourself type with an air gap
adjustable by washers or spacers is very useful for
breadboarding prototypes. Care must be taken to
choose a permeable enough core to handle the
magnetic flux produced at IMAX ; if the core saturates,
then efficiency and output current capability are
severely degraded and excessive current will flow
though the switch tranSistor. A pot core inductor
design section is provided later in this datasheet

An isolated AC current probe for an oscillOSCOpe
(example: Tektronix P6042) is an excellent tool for
saturation problems; with it the inductor current can be
monitored for nonlinearity at the peaks (a sign of
saturation).
Low Battery Detector

An open collector signal transistor 02 with comparator
C2 provides the designer with a method of signaling a
display or computer whenever the battery voltage falls
below a programmed level (see Figure 8). This level is
determined by the +1.3V reference level and by the
selection of two external resistors according to the
equation:
Where VTH =Threshold Voltage for Detection

Raytheon Semiconductor

3-733

RC4190
VTH = VR£F( ~: +1)
When the battery voltage drops below this threshold
Q2 will turn on and sink over 1500 pA typically. The
low battery detector circuitry may also be used for
other,less conventional applications (see Rgures 14
and 15).
Automatic Shutdown
The bias control current for the reference is externally
set by a resistor from the Ie pin to the battery. This
current can vary from 1.0 pA to 50 pA without affecting the operation of the IC. Interrupting this current
will disable the entire circuit, causing the output
voltage to go to OV for step-down applications, and
reducing the supply current to less than 1.0 pA.
Automatic shutdown of the 4190 can be achieved
using the circuit of Figure 9.
+vs

R4

-

I LllO

RS

65-1651

Figure 8. Low Battery Detector

+
vBAT -=-

Rl

4190

R9
65·2678

Figure 9. Automatic Shutdown

3-734

A resistor is placed from the Ie pin to ground, creating
a voltage divider. When the voltage at the Ie pin is
less than 1.2V, the 4190 will begin to turn off. This
scheme should only be used in limited temperature
range applications since the "turn off' voltage at the Ie
pin has a temperature coefficient of -4.0 mVf'C. At
25°C, typically 250 nA is the minimum current required by the Ie pin to sustain operation. A 5.0 pA
voltage divider works well taking into account the
sustaining current of 250 nA and a threshold voltage
of 0.4V at turn off. As an example, if 3.0V is to be the
turn off voltage, then R9 = 1.1/4.75 pA and R1 = (3.01.1) 5.0 pA or about 240 kn and 390 kn respectively.
The tempco at the top of the divider will be -4.0 mV
(R1 + R9)/R9 or -10.5 mV/oC, an acceptable number
for many applications.
Another method of automatic shutdown without
temperature limitations is the use of a zener diode in
series with the Ie pin and set resistor. When the
battery voltage falls below Vz + 12V the circuit will
start to shut down. With this connection and the low
battery detector, the application can be designed to
signal a display when the battery voltage has dropped
to the first programmed level, then shut itself off as
the battery reaches the zener threshold.
The set current can also be tumed off by forcing the Ie
pin to 0.2V or less using an external transistor or
mechanical switch. An example of this is shown in
Figure 10.
In this circuit an external control voltage is used to
determine the operating state of the 4190. If the
control voltage Vc is a logic 1 at the input of the 4025
(CMOS Triple NOR Gate), the voltage at the Ie pin will
be less than 0.5V forcing the 4190 off «0.1 pA leel.
Both the 2N3904 and 2N2907 will be off insuring long
shelf for the battery Since less than 1.0 pA is drawn
by the circuit.
When Ve goes to a logic 0,2.0 pA is forced into the Ie
pin through the 2.2 MO resistor and the NOR gate,
and at the same time the 2N3904 and 2N2907 turn
on, connecting the battery to the load.

As long as Vc remains low the circuit will regulate the

Raytheon Semiconductor

For More Infonnalicn, call HlOO·722·7074.

RC4190
output to 5.0V. This type of circuit Is used to back up
the main supply voltage when line interruptions occur,
a particularly useful feature when using volatile
memory systems.

until the battery voltage decays below 7.5V, at which
time It will start to switch and regulate the output at
7.0V until the battery falls below 2.2V.
If this circuit operates at its typical efficiency of 80%,
with an output current of 10 mA, at 5.0V battery
voltage, then the average input current will be IN =
(Vour x IJ +(Vwx eJ or fl.OV x 10 mA) + (5.0Vx 0.8
mA) = 17.5 mAo

9.0V Battery Ufe Extender

Figure 11 shows a common application: a circuit to
extend the lifetime of a 9.0V battery. The regulator
remains In ils quiescent state (drawing only 215 JIA)

Lx

,...-.....--_<> VOUT - 5V

2.2M

r--- ---I

1

1/34025

1

1
1

Figure 10. Battery Back-Up Circuit
65·2679

Lx

9VID2.2V

+

VBAT

-=-

-~

1N914

To7V
R1
1M

+

C1:

150~

1 LBR
GND
3
RS"
260K

R4"
910K

-

-

4190
R3
25K

Cx
2
Cx

150

PF

65-2680

"Optional

FlQure 11. 9.0V Battery Life Extender

For MonIlnfamation, call HIOO-722-7074.

Raytheon Semiconductor

3-735

RC4190
Bootstrapped Operation (Step-Up)

In steJHJP applications, power to the 4190 can be
derived from the output voltage by connecting the +Vs
pin and the top of R1 to the output voltage (Figure 12).
One requirement for this circuit is that the battery
voltage must be greater than 3.0V when it is energized or else there will not be enough voltage at pin 5
to start up the IC. The big advantage of this circuit Is
the ability to operate down to a discharged battery
voltage of 1.0V.

Ie

SYlOW

Ya.u+..::..

-l

v"",.w

lN014

l.omH

R1

5

1M

following circuit eliminates this disadvantage, aDowing
a battery voltage above the programmed output
voltage to decay to well below the output voltage (see
Figure 13).
The circuit operation Is similar to the steJHJp circuit
operation, except that both terminal of the Inductor are
connected to switch transistors. This switching method
allows the inductor to be disconnected from the
battery during the time the inductor is being discharged. A new discharge path is provided by 01,
allowing the inductor to be referenced to ground and
independent of the battery voltage. The efficiency of
this circuit will be reduced to 55-600/0 by losses In the
extra switch transistor and diode. Efficiency can be
IlTl>roved by choosing transistors with low saturation
voltages and by using power Schottky diodes such as
Motorola's MBR030.

• I.+Ya
4110

1M'
1110

R5'
2801(

':'

':'

':'

'0pIi0nII

Figure 12. Bootstrapped Operation (Step-Up)

--

R4

2.21<
R2

Buck-Boost Circuit (Step-UplDown)

A disadvantage of the standard step-up and stepdown circuits is the limitation of the Input voltage
range; for a step-up circuit, the battery voltage must
always be less than the programmed output voltage,
and for a step-down circuit, the battery voltage must
always be greater than the output voltage. The

1\3

Figure 13. Buck Boost Circuit (Step-UpIDown)

3-736

Raytheon Semiconductor

For Mora InfDnnation, call 1-800-722-7074.

RC4190
Step-Up Voltage Dependent Oscillator

pin 8, effectively putting C2 in parallel with Cx' This
added capacitance will reduce the oscillator frequency
according to the following equation:

The 4190's ability to supply load current at low battery
voltages depends on the inductor value and the
oscillator frequency. Low values of inductance or a low
oscillator frequency will cause a higher peak inductor
current and therefore increase the load current
capability. A large inductor current is not necessarily
best, however, because the large amount of energy
delivered with each cycle will cause a large voltage
ripple at the output, especially at high input voltages.
This trade-off between load current capability and
output ripple can be improved with the circuit connection shown in Figure 14. This circuit uses the low
battery detector to sense for a low battery voltage
condition and will decrease the oscillator frequency
after a pre-programmed threshold is reached.

F ~ 2.4 x 1008
o Cx +C2
Where C is in pF and F0 is in Hz.
Component values for a typical application might be
R2 = 330 kn. R5 = 150 kn. Cx= 100 pF, and C2 =
100 pF. These values would set the threshold voltage
at 4.1 V and change the operating frequency from 48
kHz to 24 kHz. Note that this technique may be used
for step-up, step-down, or inverting applications.
Step-Down Regulator With Protection
One disadvantage of the simple application circuits is
their lack of short circuit protection, especially for the
step-up circuit, which has a very low resistance path
for current flow from the input to the output. A current
limiting circuit which senses the output voltage and
shuts down the 4190 if the output voltage drops too
low can be built using the low battery detector circuitry. The low battery detector is connected to sense
the output voltage and will shut off the oscillator by
forcing pin 2 low if the output voltage drops. Figure 15
shows a schematic of a step-down regulator with this
connection.

The threshold is programmed exacijy as the noram
low battery detector connection:
VTH = VFEF

(

=:

+1 )

When the battery voltage reaches this threshold, the
comparator will turn on the open collector transistor at

Lx

lN914

-I

+
5

Ie

4

+Vs

I

OF

Lx

LBR
LBO

R2

VFB

4190

Ox

7

Gnd

R3

3

2
'::"

'::"

61;-2683

Figure 14. Step-Up VoHage-Dependent Oscillator

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-737

RC4190
R2 and R3 set the output voltage, as in the circuit of
Figure 2. Choose resistor values so RS = R3 and R4 =
R2, and make R8 25 to 35 times higher than R3.
When the output is shorted, the open collector transistor at pin 8 will force pin 2 low and shut off the oscillator and therefore shut off the external switch transistor.
The regulator will then remain in a low current off
condition until power is removed and reapplied. C2
provides momentary current to ensure proper start-up.
This scheme will not work with the simple step-up
regulator, but will work with the boost-buck converter,
providing short circuit protection in both step-up and
step-down modes.

4190/4391 ± Power Supply
A positive and negative dual tracking power supply
using a step-up 4190 and an inverting 4391 is shown
in Figure 16. The inductor and capacitor values were
chosen to achieve the highest practical output currents from a +12V battery, as it decays, while keeping
the output voltage ripple under 100 mVp-p at ±15V
output.

The circuit may be adapted to other voltages and
currents, but note that the 4190 is step-up, so Voor
must be greater than VBAT
The output voltages may both be trimmed by adjusting
a single resistor value (R3 or R4), because the
reference for the negative output is derived from
+Voor This connection also allows the output voltages
to track each other with changes in temperature and
line voltage.
The timing capacitors are set up exactly as in the
voltage dependent oscillator application of Figure 14.
The values of R2, RS, C6, and C4 that are given were
chosen to optimize for the +12V battery conditions,
setting the threshold for oscillator frequency change at
VBAl = +B.5V.

As given, this power supply is capable of delivering
+45 rnA and -15 rnA with regulation, until the battery
decays below 5.0V.
For information on adjusting the 4391 to meet a
specific application refer to the Raytheon 4391 data
sheet.

VSAT
R6
R1
1M

loOK

6

4190

R8

~R~--~--+---~

LBO
8

Gnd 3
2

R3 R5

R8=35(R3)

R2
VOUT =1.31 (Fi3+ 1)
65-2684

Figure 15. Step-Down Regulator With Protection

3-738

Raytheon Semiconductor

For Mora Information, call 1-800-722-7074.

RC4190
·l our -·15mA

+VSAT
(12V Normal)
01

.vOIJT

+l our -45mA

lN914

L-~~~~--~----~-o+~1JT

LBR

R7
lOOK

R3

11K

To+Vour

+Vour - VAEF (;+1)

~VolJTl- +Vour ( =~)

85·2885

Figure 16. 4190/4391 Power Supply (±15V)

Negative Step-Up Regulator

-

R1
1M

In the circuit of Figure 17, a bootstrap arrangement of
supply and ground pins helps generate an output
voltage more negative than the input voltage. On
power-up, the output filter capacitor (CFl will charge
through 02 and Lx' When the voltage goes below 2.4V, the 4190 begins switching and charging Cp The
output will regulate at a value equal to the reference
voltage (1.31 V) plus the zener voltage of 01. RZ sets
the value of zener current, stabilized at 1.31 V/R2.

7

6

5

Ie

+vs

4190
Cx

2

C

XT

GncI
3

Lx
4

-Vour

"J:

CF

Figure 17. Negative Step-Up Regulator

For More Information. call 1-800·722·7074.

Raytheon Semiconductor

·v ..
65-4131

3-739

en
(")

(.0)

i!

::r

0

CD

3

+Vs
(5~

Lx

VFB

(4)

(7)

Ox
(~

a
(;'
c

~'

D1

3

::a
I»

os:::J'
CD
0
:::J

ffl
3

Ie
(6)

n
0
:::J

Q,

C

a0
...
Ql

~

f

f

.,g.
;>

~
;b
8

~

;;;!

raf~J

~

R6

34.4K

Rl
147K

(8)

LBO

(1)
LBR

(3)
Gnd

~

Q
joooo.l.

~

RC4190
Troubleshooting Chart
Symptom

Possible Problem

Draws excessive supply current on start-up

Battery not ·stiff' - inadequate supply bypass
capacitor.
Inductance value too low.
Operating frequency (FJ too low.

Output voltage is low.

Inductance value too high for F0 or core saturating.

Inductor ·sings· with audible hum.

Not potted well or bolted loosely.

Lx in appears noisy -

Normal operating condition.

scope will not synchronize.

Inductor is saturating:
1. Core too small.
2. Core too hot
3. Operating frequency too low.

h~A-'~,
Time
Inductor current shows nonlinear waveform.

Waveform has resistive component:
1. Wire size too small.
2. Power transistor lacks base drive.
3. Components not rated high enough.
4. Battery has high series resistance.

h~U-'~,
Time
Inductor current shows nonlinear waveform.

~
Ill(

External transistor lacks base drive or beta is too low.

,LJ-,-,,

Time
61>-6348
Inductor current is linear until high current is reached.
Poor efficiency.

Core saturating.
Diode or transistor:
1. Not fast enough.
2. Not rated for current level (high VeE SAT).
High series resistance.
Operating frequency too high.

Motorboating (erratic current pulses).

Loop stability problem - needs feedback capacitor
from Voor to VFB (pin 7),100 to 1000 pF.

For Mora Information. call 1-1100-722-7074.

Raytheon Semiconductor

3-741

RC4190
Background Information
During the past several years there have been various
switching regulator ICs introduced by many manufacturers, all of which attended to the same market,
namely controllers for use In power supplies delivering
greater than 10W of DC power. Raytheon felt there
was another area which could use a switching regulator to even more advance the area of battery powered
equipment. Battery powered systems have problems
peculiar unto themselves: changes in supply voltage,
space considerations, battery life and usually cost.
The 4190 was designed with each of these in mind.
The 4190 was partitioned to work in an eight pin
package, making it smaller than other controllers
which go into 14 and 16 pin packages.

Battery powered applications require the load as seen
by the battery to be as small as possible to extend
battery life. To this end, the quiescent current of the
4190 is 15 to 100 times less than controllers designed
for nonbattery applications. At the same time, the
switch transistor can sink 200 mA at 0.4V., comparable to or better than higher powered controllers. As
an example, the 4190 configured in the step-up mode
can supply 5.0V at 40 rnA output with an input of 3.0V.
Cost is usually a primary consideration in battery
powered systems. The 4190, guaranteed to work
down to 2.2V, can save the designer and end user
money as well because battery costs decrease as the
number of cells needed goes down.

Soft Start

6
Ie
RC4190
65-2076

Figure 18: Soft Start Circuit
The delay introduced by the RC time constant at
start-up allows the output filter capacitor to charge up,
reducing the instantaneous supply current. A typical
value for C is in the 0.1 J,If range.

3-742

Raytheon Semiconductor

For More Information. caJI1-800·722-7074.

RC4190
Bootstrapped Low Voltage Start-Up
Figure 19 shows the bootstrapped application can be
"kicked on" using an extra capacitor and triple pole
double throw switch (3P01). This connection allows
the circuit to start up using a single Ni-Cad cell of 1.2V
to 1.6V. When power is first applied the 1.2V battery
does not provide enough voltage to meet the minimum 2.2V supply voltage requirement. The 22~
capacitor, when switched, temporarily doubles the
battery voltage to bias up the 4190.
When the switch is the down position, the capacitor
charges up to the battery voltage. The, when the

switch Is changed to the up position, the capacitor is
put in series connection with the battery, and the
doubled voltage is applied directly to the positive
power supply lead of the 4190. This voltage is
enough to bias the junctions internal to the 4190 and
gets it started. Then, when the stepped up output
voltage reaches a high enough value, diode 01 is
forward biased and the output voltage takes over
supplying power to the 4190. The circuit is shown with
component values for +5V output, but the circuit can
be set up for other voltages.

1N914
01

Lx

Motorola
4 MBR140P

Lx
6

Ie

VOUT = +5V. 10 rnA

02

4190

+
R2

c.=

I22 PF

33K

VFB 7
R3
13K

65-2078

Figure 19: Bootstrapped Low Voltage Start-up

I
For More Information. call HIOO-722-7074.

Raytheon Semiconductor

3-743

RC4190
Magnetic Circuft

Electrical Circutt

North

65-1720

65-1721

Figure 20. Electricity Versus Magnetism

Electricity Versus Magnetism

Question: What happens if too small a core is used?

Electrically the inductor must meet just one requirement. but that requirement can be hard to satisfy. The
inductor must exhibit the correct value of inductance
(L. in Henrys) as the inductor current rises to its
highest operating value (I MAX). This requirement can
be met most simply by choosing a very large core and
winding it until it reaches the correct inductance value.
but that brute force technique wastes size. weight and
money. A more efficient design technique must be
used.

First. one must understand how the inductor's magnetic field works. The magnetic circuit in the inductor
is very similar to a simple resistive electrical circuit
(see Figure 20). There is a magnetizing force (H. in
oersteds). a flow of magnetism. or flux density (B. in
Gauss). and resistance to the flux. called permeability
(U. in Gauss per oersted). H is equivalent to voltage in
the electrical model. flux density is like current flow.
and permeability is like resistance (except for two
important differences discussed on the fOllowing
page).

3-744

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC4190
First Difference: Permeability, instead of being
analogous to resistance, is actually more like conductance (1IR). As permeability increases, flux increases.
Second Difference: Resistance is a linear function.
As voltage increases, current increases proportionally,
and the resistance value stays the same. In a magnetic circuit the value of permeability varies as the
applied magnetic force varies. This nonlinear characteristic is usually shown in graph form in ferrite core
manufacturer's data sheets. See Figure 21.
6000

----

5000

:I

4000

iI 3000
CJ
m 2000
1000 H

o I

+2S0C

":8soc_

.

,..

/ /
'Aft.

Of-

+1jS

r Stackpole Ceramag 248
J. I
j'- Hysteresis Loop vs. Temperature
I

I

-0.5 0 0.5 1

I

I

I

I

-I

I

22.53579
H Oersteds

Figure 21: Typical Manufacturer's Curve Showing
Saturation Effects

As the applied magnetizing force increases, at some
point the permeability will start decreasing, and
therefore the amount of magnetic flux will not increase
any further, even as the magnetizing force increases.
The physical reality is that, at the point where the
permeability decreases, the magnetic field has
realigned all of the magnetic domains in the core
material. Once all of the domains have been aligned
the core will then carry no more flux than just air; it
becomes as if there were no core at all. This phenomenon is called saturation. Because the inductance
value, L, is dependent on the amount of flux, core
saturation will cause the value of L to decrease
dramatically, in turn causing excessive and possibly
destructive inductor current.

For More Information. call 1-800·722·7074.

Pot Cores for 4190
Pot core inductors are best suited for the 4190
micropower switching regulator for several reasons:
1. They are available In a wide range of sizes.
4190 applications are usually low power with
relatively low peak currents (less than 500mA). A
small inexpensive pot core can be chosen to meet
the circuit requirements.
2. Pot cores are easily mounted. They can be
bolted directly to the PC card adjacent to the
regulator IC.
3. Pot cores can be easily air-gapped. The length
of the gap is simply adjusted using different
washer thicknesses. Cores are also available
with predetermined air gaps.
4. Electromagnetic Interference (EMI) Is kept to a
minimum. The completely enclosed design of pot
core reduces stray electromagnetic radiationan important consideration of the regulator circuit
is built on a PC card with other circuitry.
Core Size
Question: Is core size selected according to load
power?
Not quite. Core size is dependent on the amount of
energy stored, not on load power. Raising the operating frequency allows smaller cores and windings.
Reduction of the size of the magnetics is the main
reason switching regulator design tends toward higher
operating frequency. Designs with the 4190 should
use 75kHz as a maximum running frequency, because
the turn off delay of the power transistor and stray
capacitive coupling begin to interfere. Most applications are in the 10 to 50kHz range, for efficiency and
EMI reasons.
The peak inductor current (IMAX) must reach a high
enough value to meet the load current drain. If the
operating frequency is increased, and simultaneously
the inductor value is decreased, then the core can be
made smaller. For a given core size and winding, an
increase in air gap spacing (an air gap is a break in
the material in the magnetic path, like a section
broken off a doughnut) will cause the inductance to

Raytheon Semiconductor

3-745

I
:

RC4190
#1

#2

#3

#4

8

8
8
8

22X
130m
24 Gauge
70 Tums

3A

DCn.O.Sn
18X
11 mm

i

26 Gauge
70 Tums

2A

E

DCn.0.7n

~

14X
8mm

j

lA

28 Gauge
60 Turns

Dcn.o.sn
llX
7mm

0
2mH

30 Gauge

3mH

~

Inductor Value (Henries)

50 Turns

Dcn.ln

"Includes safety margin (25%) to ensure nonsaturation

Figure 22: Inductor Design Aid
calculation must be done to find the adjusted
saturalion) to Increase.
number of turns. Find AL (inductance index)
for a specific air gap.
The curves shown in Figure 21 are typical of the ferrite
L (indicated)
.
manufacturer's power HF material, such as Siemens
Turns2
= \ (In Henrys/turn2)
N27 or Stackpole 24B, which are usually offered in
Then divide the required inductance value by ~ to
standard millimeter sizes including the sizes shown.
give the actual turns squared, and take the square
Use of the Design Aid Graph (Figure 22)
root to find the actual turns needed.
1. From the application requirement, determine the
Actual Turns =
l (required)
A..
inductor value (L) and the required peak current
If the actual number of turns is significantly less
(IMAX)'
than the number from the table then the wire size
2. Observe the curves of the design aid graph and
can be increased to use up the left-over winding
determine the smallest core that meets both the
area and reduce resistive losses.
L and I requirements.
6. Wind and gap the core as per calculations,
3. Note the approximate air gap at IMAX for the
and measure the value with an inductance
selected core, and order the core with the gap. (If
meter. Some adjustment of the number of
the gapping is done by the user, remember that a
turns may be necessary.
washer spacer results in an air gap of twice the
The saturation characteristics may be checked
washer thickness, because two gaps will be
with the inductor wired into the switching regulator
created, one at the center post and one at the
application circuit. To do so, build and power up
rim, like taking two bites from a doughnut.)
the circuit. Then (recommend Tektronix P6042 or
4. If the required inductance is equal to the indicated
equivalent) around the inductor lead and monitor
value on the graph, then wind the core with the
the current in the inductor. Draw the maximum
number of turns shown in table of sizes. The
load current from the application circuit so that the
turns given are the maximum number for that
regulator is running at close to full duty cycle.
gauge of wire that can be easily wound in the
Compare the waveform you see to those pictured
cores winding area.
in Figure 23.
5. If the required inductance is less than the
Check for saturation at the highest expected
value indicated on the graph, a simple
ambient temperature.
decrea~e and .IMAX (the usable peak current before

3-746

Raytheon Semiconductor

For More Information, call

1-800-722·7074.

RC4190
Improper Operation
(Waveform is Nonlinear, Inductor Is
Saturating)

Proper Operation
(Waveform is Fairly Linear)

65-1723

65-1723

Figure 23: Inductor Current Waveforms

7. After the operation in circuit has been checked,
reassemble and pot the core using a potting
compound recommended by the manufacturer.
If the core material differs greatly in magnetic
characteristics from the standard power material
shown in Figure 22, then the following general
equation can be used to help in winding and
gapping. This equation can be used for any core
geometry, such as an E-E core.

Lx=

(1.26)(N2)(Ae)(108)
g = (Ie/ue)

Where: N = number of turns
Ae = core area from data sheet (in cm2)
Ie = magnetic path length from data
sheet (in cm)
ue =permeability of core from
manufacturer's graph
g = center post air gap (in cm)

For More Information, caJI1-800·722·7074.

Manufacturers
Below is a list of several pot core manufacturers:
Ferroxcube Company
5083 Kings Highway
Saugerties, NY 12477
Indiana General Electronics
Keasley, NJ 08832
Siemens Company
186 Wood Avenue South
Iselin, NJ 08830
Stackpole Company
201 Stackpole Street
St. Mary, PA 15857
TDK Electronics
13-1-Chome
Nihonbaski, Chuo-ku, Tokyo

Raytheon semiconductor

I
3-747

RC4190

3-748

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4191/4192/4193
RC4191/4192/4193
Micropower Switching Regulators
Description
The RC4191/419214193 series of monolithic ICs are
low power switch mode regulators intended for
miniature power supply applications. These DC-to-DC
converter ICs provide all of the active components
needed to create supplies for micropower circuits.
Contained internally are an oscillator, switch, reference, comparator, and logic, plus a discharged battery
detection circuit.
These regulators can achieve up to 85% efficiency in
most applications while operating over a wide supply
voltage range, 2.2V to 30V, at a very low quiescent
current drain of 215 J.IA.
The standard application circuit requires just seven
external components for step-up operation: an
inductor, a steering diode, three resistors, a low value
timing capacitor, and an electrolytic filter capacitor.
The combination of simple application circuit, low
supply current, and small package make the 4193
adaptable to a wide range of miniature power supply
applications.
The 4193 is most suited for single ended step-up
(Voor > VIN) circuits because the NPN internal switch
transistor is referenced to ground. It is complemented
by Raytheon's micropower switching regulator, the
4391 , which is dedicated to step-down (Voor < VIN)
and inverting Voor = -V1N ) applications. Between the
two devices the ability to create all three basic switching regulator configurations is assured. Refer to the
4391 data sheet for step-down and inverting applications.

For More Information, call HlOO-722-7074.

The 4191/92/93 series of micropower switching
regulators consists of three devices, each with slightly
different specifications. The RM4191 has a 1.5%
maximum output voltage tolerance, 0.2% maximum
line regulation, and operation to 30V. The RC4192
has a 3.0% maximum output voltage tolerance, 0.5%
maximum line regulation, and operation to 30V. The
4193 has a 5.0% maximum output voltage tolerance,
0.5% maximum line regulation, and operation to 24V.
Other specifications are identical for the 4191 , 4192
and 4193. Each type is available in commercial,
industrial, and military temperature ranges, and in
plastic and ceramic DIPs and 80-8 packages.

Features
•
•
•
•
•
•
•
•
•
•

High efficiency - 85% typical
Low quiescent current - 215 J.IA
Adjustable output - 1.3V to 30V
High switch current - 200 rnA
Bandgap reference -1.31 V
Accurate oscillator frequency - ±1 0%
Remote shutdown capability
Low battery detection circuitry
Low component count
8-lead packages

Raytheon Semiconductor

I
3-749

RC4191/4192/4193
Functional Block Diagram

Connection Information
8·Lead DIP
(Top View)

LBR

o

Pin
1
2
3
4

5
6

7
8

41911213

LBO

65-0070

Function
Low Battery (Set) Resistor (LBR)
Timing Capacitor (Cx)
External Inductor (Lx)
Ground
+ Supply Voltage (+Vs)
Reference Set Current (Ie>
Feedback Voltage (VFB)
Low Battery Detector Output (LBO)

65-1640

Ordering Information
Package

Operating
Temperature
Range

RC4191M
RC4192M
RC4193M
RC4191N
RC4192N
RC4193N

M
M
M
N
N
N

O°C to +70°C
O°C to +70°C
O°C to +70°C
O°C to +70°C
O°C to +70°C
O°C to +70°C

RV4191N
RV4192N
RV4193N

N
N
N

·25°C to +85°C
·25°C to +85°C
·25°C to +85°C

RM4191D
RM4192D
RM4193D
RM4191D/883B

0
0
0
0

·55°C to +125°C
·55°C to +125°C
·55°C to +125°C
·55°C to +125°C

Part Number

Absolute Maximum Ratings(1)
Supply Voltage (Without External Transistor)
4191,4192 ........................................+30V
4193 .................................................. +24V
Storage Temperature
Range ............................... ·65°C to +150°C
Operating Temperature Range
RM41911213 ...................... ·55°C to +125°C
RV4191/2I3 ........................ -25°C to +85°C
RC4191/2I3 ........................... O°C to +70°C
Switch Current .................................... 375 mA Peak
Note:
1. •Absolute maximum ratings' are those beyond which the
safety 01 the device cannot be guaranteed. They are not
meant to imply that the device should be operated at these
limits. II the device is subjected to the limits in the absolute
maximum ratings for extended periods, its reliability may be
impaired. The tables of Electrical Characteristics provide
conditions for actual device operation.

Notes:
/8838 suffix denotes Mi~Std-883.Level 8 processing
N =8-lead plastic DIP

D=8 lead ceramic DIP

M =a-lead plastic SOIC

3·750

Raytheon Semiconductor

For More Information. call 1-800·722·7074.

RC4191/4192/4193
Thermal Characteristics
a-Lead
Plastic
DIP
+125°C
468mW

Max. Junction Temp.
Max. Po TA <50°C
Therm. Res 9JC
Therm. Res. 9JA
For TA >50'C Derate at

a-Lead
Ceramic
DIP
+175°C
833 mW
45°C/W
150°C/W
8.33mWI"C

160°C/W
6.25 mWI"C

Small
Outline
SO-8
+125°C
300mW

240°C/W
4.17 mWI"C

Electrical Characteristics
(Vs = +6.0V, Ie = 5.0 IJA, and TA = +25OC unless otherwise noted)

Parameters
Supply Voltage
Reference Voltage
(Internal)
Switch Current
Supply Current
Efficiency
Une Regulation
Load Regulation
Operating Frequency
Range'
Reference Set Current
Switch Leakage
Current
Supply Current
(Disabled)
Low Battery
Bias Current
Capacitor Charging
Current
Oscillator Frequency
Tolerance

Symbol Conditions
+Vs
VREF
Isw
Isv

V3 =400mV
Measure at Pin 5
13=0

ef
LI

0.5 Vo VBAT) DC-toDC Converter (Figure 1).

tt~ tR:}~~
(-)

85-1646

Figure 1. Simple Step-Up Converter

When switch S is closed, the battery voltage is applied
across the inductor L. Charging current flows through
the inductor, building up a magnetic field, increasing
as the switch is held closed. While the switch is
closed, the diode D is reverse biased (open circuit)
and current is supplied to the load by the capaCitor C.
Until the switch is opened, the inductor current will
increase linearly to a maximum value determined by
the battery voltage, inductor value, and the amount of
time the switch is held closed (IMAX =VBAIL x TON)'
When the switch is opened, the magnetic field collapses, and the energy stored in the magnetic field is
converted into a discharge current which flows
through the inductor in the same direction as the
charging current. Because there is no path for current
to flow through the SWitch, the current must flow
through the diode to supply the load and charge the
output capacitor.
If the switch is opened and closed repeatedly, at a rate
much greater than the time constant of the output RC,
then a constant DC voltage will be produced at the
output.
An output voltage higher than the input voltage is
possible because of the high voltage produced by a
rapid change of current in the inductor. When the
switch is opened, the inductor voltage will instantly
rise high enough to forward bias the diode, to Vour +
VO'

3-754

In the complete 4193 regulator, a feedback control
system adjusts the on-time of the switch, controlling
the level of inductor current, so that the average
inductor discharge current equals the load current,
thus regulating the output voltage.

Complete Step-Up Regulator
A complete schematic of the minimum step-up
application is shown in figure 2. The ideal switch in the
DC-to-DC Converter diagram is replaced by an open
collector NPN transistor 01. CF functions as the output
filter capacitor, and D1 and Lx replace D and L.
When power is first applied, the current in R1 supplies
bias current to pin 6 (Ie)' This current is stabilized by a
unity gain current source amplifier and then used as
bias current for the 1.31 V bandgap reference. A very
stable bias current generated by the bandgap is
mirrored and used to bias the remainder of the chip. At
the same time the 4193 is starting up, current will flow
through the inductor and the diode to charge the
output capacitor to VBAT - VO'
At this point, the feedback (pin 7) senses that the
output voltage is too low, by comparing a division of
the output voltage (set by the ratio of R2 to R3) to the
+1.31 V reference. If the output voltage is too low then
the comparator output changes to a logical zero. The
NOR gate then effectively ANDs the oscillator square
wave with the comparator signal; if the comparator
output is zero AND the oscillator output is low, then
the NOR gate output is high and the switch transistor
will be forced on. When the oscillator goes high again,
the NOR gate output goes low and the switch transistor will turn off. This turning on and off of the switch
transistor performs the same function that opening
and closing the switch in the simple DC-to-DC Converter does; Le., it stores energy in the inductor during
the on-time and releases it into the capaCitor during
the off-time.
The comparator will continue to allow the oscillator to
turn the switch on and off until enough charge has
been delivered to the capaCitor to raise the feedback
voltage above 1.31V.

Raytheon Semiconductor

For More Information, call HlOO-722-7074.

RC4191/4192/4193
Thereafter, this feedback system will vary the duration
of the on-time in response to changes in load current
or battery voltage (see Figure 3). If the load current
increases (waveform C), then the transistor will remain
on (waveform 0) for a longer portion of the oscillator
cycle (waveform B), thus allowing the inductor current

(waveform E) to build up to a higher peak value. The
duty cycle of the switch transistor varies in response
to changes in load and time.

®
(+)
4

01

'-1<---- 4190i92i93------1

Rl

@

R2

I7
R2

VOUT - VREF (R3 + 1)

R3

(-)

Figure 2. Complete Step-Up Regulator
.-1.4V

o

. - o.sv
(Internal)

®

. - . - IL(Max)

@ _ _ _.r-------'
______________________ •

®

®
®

®

. - OmA
.-O.72V
(Internal)

OSC
I LOAD

I

VBEQ1

.-ov
ILX

.-OmA
.-IMAX
10

.-OmA
. - VOUT+VO
. - VBAT
VLX
. - O.3V (Ql SAT)

Figure 3. Step-Up Regulator Waveforms
For More Information, call 1-800-722-7074.

Cx

Raytheon Semiconductor

65-1642

3-755

~

(J)
()

::s-

0)

CD

3

a0"
+Vs
(5)

Lx

VFB

ex

(4)

(1)

(2)

C

c!"
D1
3

~
.a::.
~

\C

~
~

\C

~
.a;;.
~

I

!

t..

.J

1

~10

I

I~

~~

~\W ~Q28I,

~

::r

CD

0

::s

fII

~

()

0

::s

a.
C
g,

Ie
(6)

..

0

ir
it

Q1

iI

f

t

~

~

~
;ro!

(8)

(1)

LBO

LBR

(3)
Gnd

,I~

I?~

~

~

I

RC4194
RC4194
Dual1hlcking Voltage Regulators
Description

Features

The RC/RM4194 are dual polarity tracking regulators
designed to provide balanced or unbalanced positive
and negative output voltages at currents to 200 mAo A
single external resistor adjustment can be used to
change both outputs between the limits of :±SO mV
and±42V.

•

These devices are designed for local 'on-card"
regulation, eliminating distribution problems
associated with single-point regulation. To simplify
application the regulators require a minimum number
of external parts.
The device is available in three package types to
accommodate various power requirements. The K
(T0-66) power package can dissipate up to 3W at TA
=+25°C. The 0 14-pin dual in-line will dissipate up to
1W and the N 14-pin dual in-line will dissipate up to
625mW.

•
•
•
•

Simultaneously adjustable outputs with one
resistor to ±42V
Load current - :lQ00 mA with 0.04% load
regulation
Internal thermal shutdown at TJ =+175°C
External balance for ±VOUT unbalancing
3W power dissipations

Connection Information
9-Lead

T0-66 Package
(Top View)

+VOUT

GND

Comp+

RSET

Functional Block Diagram
BaI
Compo

4194
65-0199

14-Lead
NC
Comp+

NC
GND

Plastic &Ceramic DIP
(Top View)

I

a

Bal

CompNC

-Vs

NC

-VOUT

65-0207

For More Information, call HlOO-722-7074.

Raytheon Semiconductor

3-757

RC4194
Absolute Maximum Ratings(1)

Ordering Information
Package

Operating
Temperature
Ranae

RC4194N
RC4194D
RC4194K

N
D
K

O°Cto +70°C
OOC to +70OC
O°Cto +70°C

RM4194D
RM4194D/8838
RM4194K

D
D
K

-55°C to +125°C
-55°C to +1250C
-55°C to +125°C

Part Number

Notes:
I883B suffix denotes Mil-Std-883, Level B processing
N = 14-lead plastic DIP
D. 14·lead ceramic DIP
K • 9·lead T0-66

Supply Voltage
RC4194 ...............................................±35V
RM4194 ...............................................±45V
Supply Input to Output Voltage Differential
RC4194 ...............................................±35V
RM4194 ...............................................±45V
Load Current
N Package ....................................... 100 mA
D Package ...................................... 150 mA
K Package ...................................... 250 mA
Operating Temperature Range
RC4194 .................................. O°C to +70°C
RM4194 ............................. -55°C to +125°C
Storage Temperature
Range ...................................... -65°C to +150°C
Lead Soldering Temperature
( 60 sec) ........................................... +300°C
Note:
1. •Absolute maximum ratings' are those beyond which the
safety of the device cannot be guaranteed. They are not
meant to imply that the device should be operated at these
Omits. If the device is subjected to the limits in the absolute
maximum ratings for extended periods, its reliabifity may be
impaired. The tables of Electrical Characteristics provide
conditions for actual device operation.

Thermal Characteristics
14-Lead
Plastic DIP

14-Lead
Ceramic DIP

9-Lead TO-66
Metal Can

Max. Junction Temp.

+125°C

+175°C

+150°C

Max. Po TA <50°C

468mW

1042mW

2381mW

-

60°CIW

7°CIW

160°CIW

120°CIW

42°CIW

6.25mW/oC

8.38 mWfOC

23.81 mW/oC

Therm. Res 8JC
Therm. Res. 8JA
For TA >50°C Derate at

3-758

Raytheon Semiconductor

For More Information, call 1-800·722·7074.

RC4194
Electrical Characteristics
(±5 ~voor ~VMAX; -V~~-8V; IL = ±1mA; RM4194: -55°C ~TA~+125°C; RC4194: O°C ~TA~+70°C unless otherwise
specified)
Parameters

Test Conditions

Line Regulation
Load Regulation'

ll.Vs = 0.1 VIII
4194K: IL < 200 mA
41940: IL < 100 mA
±Vs =±(Voor + 5)V

Output Voltage Drift With
Temperature 2
Positive Output
Negative Output
Supply Current3 (Positive)
Supply Current! (Negative)

Voor =±5V
Voor =±5V
Vs = ±VMAX ' Voor = OV.IL = 0 mA
Vs = ±VMAX ' Voor = OV.IL = 0 mA
RM4194

Min

Typ

Max

UnHs

0.04

0.1

%VOOT

0.002 0.004

:19.5

0.002 0.015
0•• 003 0.015
+0.8 +2.5
-1.8
-4.0
±45

Supply Voltage

%Voor"L
(mA)

%?C

%IOC
mA
mA
V

Output Voltage Scale Factor

RC4194
RSET = 71.5 kQ, TA= +25°C. Vs =±VMAX
RM4194: Rser = 71.5 kQ, IL = 25 mA

:19.5
2.38
0.05

RC4194: RSET = 71.5 kQ, IL = 25 mA

0.05

2.5

±35
2.62
±42

Output Voltage Range

kDJV
V

Output Voltage Tracking
Ripple Rejection
Input-Output Voltage Differential
Short Circuit Current
Output Noise Voltage

F = 120 Hz. TA = +25°C
IL = 50 mA, TA= +25°C
Vs = ±30V. TA = +25°C
CL= 4.7 pF. VOUT = ±15V
F =10 Hz to 100 kHz

± 0.04
~
c 0.03

6

~

90

l

70

ia:

.2

Vour -±15V

1-

50

i-"'"'

r--

!

30
10

o

'Iii

0.02

I

0.01

"5

100

1K

10K

~

0
.0.01

100K

TA = ;'"12::,g.... ~

V V

V
-'
o

=1+25°~

ij
3

~

~

~

~

1001~1~1~1~200

Output Vottage Tracking vs. Temperature

>
~ 0.6

~ 0.4

~aI 0.2
0

J
'0 -0.2

i

ITA

IL(mA)

1 0 .8

•

K

I

F(Hz)

~

-

>

-0.4

~

~~

-

.P "'-'-

t::-:::: -:7'
::/'
.....
~

/ '~

".

-!

c

0-0.6
-60 -40 -20

0

+20 +40 +60 +80+100+120+140
TA (Oc)

A - % Tracking of Vour
B - T.C. for Positive Regulator
C - T.C. for Negative Regulator

3-760

Raytheon Semiconductor

For More Information, call HlOO·722-7074.

RC4194
Typical Applications
Unbalanced Output Voltage - Comparator Application
+VOUT

0.01 IlF

+

J

+Vs

To Additional
Compmaro~

~ 4.7IlF··
+VS

Comp+

+VOUT

RM4194

RA

>---0

Bal

(Typically 15 RC4805s)

-Vs
-Vs
RseT Comp- Gnd

Ro

-VOUT

Rs

-VOUT ;-5V

.------iD To Additional

71.5K

Compmarors
Ro
-

"i-=

-=

O.OlIlF

4.71lF
Ro(kn); 2.5 (-V OUT)
Adjust Ro for -VOUT ; -5V (12.5 Idl)
RFl = RF2 = 20 kO (See Schematic)

65-0205

Rs= oowhen 4VOUT IS:I-VOUTI
For +VOUT = 5 when -VOUT = -5V

RA =00

Rs=

00

High Output Application
2N4905 or equiv.

r---------~

r~------------------------~~~__,

t---0+VOUT

+

-r

4194

470

-Vs

Comp-

Ro -VOUT

I

601lp·

.--_-_--0

-VOUT

0.1/IF
Ro
2N2297 or equiv.

r--+----~--------------~

Load regulation
10mV@2.5A

Rsc·
2 N 9 1 4 o r ' - e q u - i v - . - - - - - - - - - - - - - - - - - - - l Ro (kil); 2.51Vol
·Rsc=

.ilL
Isc

··Optional usage - Not as critical as -Vo bypass capacito~.
Note: Compensation and bypass capaciror connections should be close as posibe ro the 4194

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

65-0206

3-761

RC4194
Typical Applications

(Continued)
Balanced Output Voltage - Op Amp Application

+

0.0Q1

+Voor -+15V
To AddtIonal
OpAmps

~4.7JlP.

4194

> - - - 0 (Typically 180 741 s)

-V,II--_--I -Va

o

RseT Comp-

Gnd

Ro

-Voor

71.5K

-VOUT--15V
To Additional

t-----o

OpAmpa

0.001 JlF
Ro(kn) - 2.5 VOUT

Dignally Controlled Dual 200 mA VoHage Regulator

r---------------------~--O +Vs-+25V
2
In

0.01JlF

OUt

B

1

REF-II2

Gnd
4

-

R2

250

±VOUT = 4 loR1
5

-Va
+Vo B
13
..........;;.-._ _ _-~2 Ro

RC4194K

+V oor (Oto+19.92V)

I,::,

10JlF

-yo ...1'-+-_0 -VOUT (0 to -19.92V)

-

110JlF
Binmy InpulS

-Va _-25V
Adjust R2 for -19.92V at -Voor with all "15" at binary Inputs,
then optionally adjust R3 for +19.92V at +VOUT

Optional Tracking
Adjustment

+Vo rB~_-..-o
R3
RC4194K

BaJ a 100K

100K

-Yo 1-=---......-0
65-1725

3-762

Raytheon Semiconductor

For Mora 1nIcnnaIion, call 1-800-722-7074.

RC4194
4194 Switchable Power Supply

then flows into 013's collector. Since 013's collector
is tied to the R pin, the 100 J.IA current will develop a
ground-refere;ced voltage drop proportional to the
value of Ro, which is then amplified by the internal
error amplifier. When the analog switch in Figure 1
turns on, it effectively shorts out Ro and causes OV to
be applied to the error amplifier. The output voltage in
the off state will be approximately:l:20 mY. If a higher
value (50 to 100 mV) is acceptable, then the DG201
analog switch can be replaced with a low-cost small
signal transistor, as shown in the alternate switch
configuration.

The outputs of the 4194 can be simultaneously
switched on or off under logic control as shown in
Figure 1. In the 'off' state, the outputs will be forced
to a minimum voltage, or about:l:20 mV, rather than
becoming open-circuit. The turn-on time, with the
outputs programmed to ±12V, is approximately 200
J,I5. This circuit works by forcing the Ro pin to ground
with an analog switch.
Refer to the 4194 internal schematic diagram. A
reference voltage that regulates with respect to -Vs is
generated at the RSET pin by the zener diode 012 and
the buffer circuit of 011 and 013. When the external
71.5k AsET resistor is connected between the RSET pin
and -VS' a precision current of 100 J.IA is generated
which

Comp+

+VS O-~P------t +Vs

+Vour

Compo.oOl~

...-_ _ _-t-vs

J
I

4194
-Your

-vs o--II-+-..JVV'v-"1 RSET
RSET

Ro
30K

'Quad SPST CMOS Analog Switch

4.7W
-12V

4.7W

* AHernate Switch Configuration
-------,I
I
4194

I
I
I

Logic

+12V

+

:r

Gnd

71.5K

C

O.OOl~

I
I
0
I
'- _ _ _ _ _ _ _ _ ...1I

I

47K

-: -:

65-4083

Figure 1. ±12V SwHchable Power Supply

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-763

I

RC4194
Compensation
For most applications, the following compensation
technique is sufficient. The positive regulator section
of the 4194 is compensated by a 0.001 J.lF ceramic
disc capacitor from the Comp+ terminal to ground.
The negative regulator requires compensation at two
points. The first is the Comp- pin, which should have
0.001 J.lF to the -VI pin, or case. A ceramic disc is
ideal here. The second compensation point for the
negative side is the -Voor terminal, which ideally
should be a 4.7 J.lF solid tantalum capacitor with
enough reserve voltage capacity to avoid the
momentary shorting and reforming which can occur
with tantalum caps. For systems where the cost of a
solid tantalum capacitor cannot be justified, it is
usually sufficient to use an aluminum capacitor with a
0.03 J.lF ceramic disc in parallel to bypass high
frequencies. In addition, if the rectifier filter capacitors
have poor high frequency characteristics (like
aluminum electrolytics) or if any Impedance is in
series with the +VI and -VI terminals, it is necessary to
bypass these two points with 0.Q1 J.lF ceramic disc
capaCitors. Just as with monolithic op amps, some
applications may not require these bypass caps, but if
In doubt, be sure to include them.

O.OOI IlF n

O.OI#~

4184

,va 0--""""-;

1--..--0 'VOUT

IO.OlIlF

-=

Note:
All Capacitors are Ceramic Disc
Except·

=Solid Tantalum

116·4201

Figure 2. 4194 Recommended
Compensation

All compensation and bypass caps should have short
leads, solid grounds, and be located as close to the
4194 as possible. Refer to Rgure 2 for recommended
compensation circuitry.

capable of handling large current surges. Figure '3
shows all six of the possible protection diodes. The
diodes at the inputs and outputs prevent voltages at
those points from becoming reversed. Diodes from
outputs to inputs prevent the output voltage from
exceeding the input voltage. Chances are that the
system under consideration will not require all six
diodes, but if in doubt, be sure to include them.

Protection

Brownout Protection

In systems using monolithic voltage regulators, a
number of conditions can exist which, left uncorrected,
will destroy the regulator. Fortunately, regulators can
easily be protected against these potentially
destructive conditions. Monolithic regulators can be
destroyed by any reversal of input or output voltage
polarity, or if the input voltage drops below the output
voltage in magnitude. These conditions can be
caused by inductive loads at the inputs or outputs of
the regulator. Other problems are caused by heavy
loads at the unregulated inputs to the regulator, which
might cause the input voltage to drop below the output
voltage at tum-off. If any of the preceding problem
conditions are present in your system, it is
recommended that you protect the regulator using
diodes. These diodes should be high speed types

The 4194 is one of the most easily applied and
trouble-free monolithic ICs available. When used
within the data sheet ratings (package power
dissipation, maximum output current, minimum and
maximum input voltages) it provides the most costeffective source of regulated ±15V for powering linear
ICs.

3-764

Sometimes occasions arise in which the 4194 ratings
must be exceeded. One example is the "brownouf.
During a brownout, line voltages may be reduced to
as low as 75 VRMS' causing the input voltage to the
4194 to drop below the minimum dropout voltage.
When this happens, the negative output voltage can
go to positive. The maximum amount of current
available is approximately 5 mAo

Raytheon Semiconductor

For More Information, call 1-1100·722·7074.

RC4194
O.OOllJF

n

Comp+

4194

-VOUTI--_-..--o -Voo-r
Comp-

4.71JF·

~

To

-VOUT

I

O.01 J.1F

Note:
All Capacitors are Ceramic Disc
Except' - Solid Tantalum

Figure 3. 4194 Regulator Showing All Protective Diodes
In general this is not enough current to damage most
ICs which the 4194 might be supplying, but it is a
potentially destructive condition. Fortunately, it is
easy to protect against. As shown in the typical
application circuit in Figure 4, a diode, D, can be
connected to the negative output.
If a small signal silicon diode is used, it will clamp the
negative output voltage at about +O.55V. A Schottky
barrier or germanium device would clamp the voltage
at about +O.3V. Another cure which will keep the
negative output negative at all times is the 1 ma
resistor connected between the +15V output and the
Comp- terminal. This resistor will then supply drive to
the negative output transistor, causing it to saturate to
-1 V during the brownout.

regulation approximately 2°C below 175"C. To avoid
shutdown, some form of heatsinking should be used
or one of the above operating conditions would need
to be derated:
Balanced Output (VOUT - ±15V)

lMO

+18VTo+30V

...---=-..1.-_-..,

+15Vat 100 mA

+
4194
-18VTo-30V

o - - - - l .Va

Heatsinking

Gnd

:r

10jIF

-=

-15Vat l00mA
-VOUTt--1t--_.--.

o

Voltage Regulators are power devices which are used
in a wide range of applications.
When operating these devices near their extremes of
load current, ambient temperature and input-output
differential, consideration of package dissipation
becomes important to avoid thermal shutdown at
175"C. The 4194 has this feature to prevent damage
to the device. It typically starts affecting load

Figure 4. 4194 Typical Application Circuft

'In allowing for process deviations, the user should work with a maximum
allowable function temperature of 150"C.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-765

I

RC4194
The following is the basic equation for junction
temperature:

TJ- TA
OJ-A =

PD
TJ - TA

PD =

where
TJ = junction temperature (OC)
TA =ambient air temperature (0G)
Po = power dissipated by device (W)
0J.A = thermal resistance from junction to
ambient air ("CIW)

=(VIN-VOUT)xlo+VINXlo

Solve for 10'
TJ - TA

VINX 10

OJ-A (VIN - VOUT)

(VIN - VOUT)

10=
The power dissipated by the voltage regulator can be
detailed as follows:
10=
where
VIN = input voltage
Voor = regulated output voltage
10 = load current
10 = quiescent current drain

= 60 mA - 13 rnA

Let's look at an application where a user is trying to
determine whether the 4194 in a high temperature
environment will need a heatsink.
Given:

TA = 125°C

=41.6°C/W, K (T0-66) pkg.

47 rnA

If this supply current does not provide at least a 10%
margin under worst case load conditions, heatsinking
should be employed. If reliability is of prime
importance, the multiple regulator approach should be
considered.
In equation 1, OJ'" can be broken into the following
components:

In the above example, let's say that the user's load
current is 200 rnA and he wants to calculate the
combined 0e-s and 9S-A he needs:

VIN = 40V
Voor

~

40 x 3.25 X 10-3
10

OM = 0J-C + 0e-s + 0S-A
where
0J-C = junction-Io-case thermal resistance
9c;.s = case-to-heatsink thermal resistance
9s-A= heatsink-to-ambient thermal resistance

TJat thermal shutdown =150°C

OJ'"

150°C - 125°C
41.6°CIW x 10V

= 30V

Given: 10 = 200 rnA,

10 = 1 mA + 75 J.1A'Voor x 30V
=3.25 mA •

10V x 200 mA + 40 x 3.25 x 10-3
• The current drain will increase by 50ILANOUT on positive side
and 1OOILANOUTon negative side.

3-766

Raytheon Semiconductor

For More Information. call HlOO·722·7074.

RC4194
When using heatsink compound with a metal-to-metal
interface, a typical 0e-s = 0.5°C/W for the K package.
The remaining 0s-A of approximately 4°CfW is a large
enough thermal resistance to be easily provided by a
number of heatsinks currently available. Table 1 is a
brief selection guide to heatsink manufacturers.

Given IlJ-C = 7.15°CfW for the 4194 in the
K package,
0e-s + 0s-A = 11.75°CfW - 7.15°CfW
= 4.6°CfW

Table 1. Commercial Heatsink Selection Guide
No attempt has been made to provide a complete list of all heatsink manufacturers. This list is only representative.
Manufacturer/Series or Part Number

9S,A·eCIW)

TO-66 Package
0.31-1.0

Thermalloy - 6441, 6443, 6450, 6470, 6560, 6590, 6660, 6690

1.0 - 3.0

Wakefield - 641
Thermalloy- 6123,6135,6169,6306,6401,6403,6421,6423,6427,6442, 6463, 6500

3.0 - 5.0

Wakefield - 621, 623
Thermalloy- 6606,6129,6141,6303
IERC-HP
Staver - V3-3-2

5.0 -7.0

Wakefield - 690
Thermalloy - 6002, 6003, 6004, 6005, 6052, 6053, 6054, 6176, 6301
IERC-LB
Staver- V3-5-2

7.0 -10.0

Wakefield - 672
Thermalloy - 6001, 6016, 6051, 6105, 6601
IERC-LA,uP
Staver- V1-3, V1-5, V3-3, V3-5, V3-7

10.0-25.0

Thermalloy - 6-13, 6014, 6015, 6103, 6104, 6105, 6117

20
30
32
34

Thermalloy - 6007
Thermalloy - 6010
Thermalloy - 6011
Thermalloy - 6012
IERC-U
Wakefield - 650, 651

Dual In-line Package

45
60

I

Staver Co., Inc.: 41-51 N Saxon Ave., Bay Shore, NY 11706
IERC: 135 W Magnolia Blvd., Burbank, CA 91502
Thermalloy: P.O. Box 34829,2021 W Valley View Ln., Dallas, TX
Wakefield Engin Ind: Wakefield, MA 01880
• All values are typical as given by manufacturer or as determined from characteristic curves supplied by manufacturer.

For More Information, calI1-S00-722-7074.

Raytheon Semiconductor

3-767

cp

en

Comp+
(7)

'"

~

(")

:::r

(J)

3

+Vs

a(;'
c

~'

DJ
3

R21
1.1

-Your
(6)

R23
20K

RFl (8)

:IJ
I»

Bal

'S.
::T
(I)

o

RF2
047

:l

(4)
Gnd

ffl
3

n'
o
:l
Co
C

g,
o

...

(1)

-voor

~

f

f

R15

~

1.10

~

I
f;!

•
Note: Pin numbers are for K package.

(3)

(2)

-Vs

(9)

RSET

Ro

To Case

Comp-

65-0198

£
~

RC4195
RC4195
Fixed + 15V Dual Tracking Voltage Regulator
Features

Description

•

The RM/RC4195 is a dual polarity tracking regulator
designed to provide balanced positive and negative
15V output voltages at currents up to 100mA. This
device is designed for local "on-card" regulation,
eliminating distribution problems associated with
single point regulation. The regulator is intended for
ease of application. Only two external components are
required for operation (two 10 ~ bypass capacitors).

•
•
•
•

±15Voperational amplifier power at reduced
cost and component density
thermal shutdown at Tj = +175°C in addition to
short circuit protection
Output currents to 100 mA
May be used as Single output regulator with up to
+50Voutput
Available in TO-66, T0-99 and 8-lead mini-DIP

The device is available in four package types to
accommodate various applications requiring
economy, high power, dissipation, and reduced
component density.

Connection Information
TO-66 Metal Can
(Top View)

T0-99 Metal can
(Top View)

-v. (Case)

+v.

NC

NC

Comp+

GND
Comp-

8-Lead DIP
(Top View)

+v.

+1SVour
Bal

-15Vour
-v.
65-0091

For More Information. call 1-800-722-7074_

85-0092

Raytheon Semiconductor

65-0093

3-769

I

RC4195
Ordering Information

Absolute Maximum Ratings

Package

Operating
Temperature
Ranae

RC4195N
RC4195T
RC4195K

N
T
K

000 to +7000
O°C to +70°C
000 to +70°C

RM4195T
RM4195T/8838
RM4195K

T
T
K

-5500 to +12500
-5500 to +12500
-55°C to +12500

Pan Number

Supply Voltage(±Vs> to Ground .................±30V
Load Current
K Package ................. _..................... 150 mA
T and N Package ............................. 100 mA
Storage Temperature
Range ..........................._.... -65°C to +150°C
Operating Temperature Range
RC4195 .. _.. ___ .. ___ .. __ ......... __ ...... O°C to +70°C
RM4195 ............................. _55°C to +125°C
Lead Soldering Temperature
(60 sec) ............................................ +300°C

Notes:
18836 suffix denotes Mil-5td-883. Level 6 processing
N • 8.Jead plastic DIP
T. 8-lead metal can TO-99
K. 9-lead metal can T0-66

Functional Block Diagram
4195;--_ _ _...---,

Comp+

1

Comp-

3

1-+--'"

Pinout for dual-in-line package shown.

3-no

Raytheon Semiconductor

65-0089

For More Information. call 1-800-722-7074.

RC4195
Thermal Characteristics
8-Lead
Plastic DIP

8-Lead TO-99
Metal Can

9-Lead TO-66
Metal can

Max. Junction Temp.

+125°C

+175°C

+150°C

Max. PDTA<50°C

468mW

658mW

2381mW

-

50°C/W

7°C/W

160°C/W

190°C/W

42°C/W

6.25 mW/oC

5.26 mW/oC

23.81 mW/oC

Therm. Res OJC
Therm. Res. 0JA
For TA >50°C Derate at

Electrical Characteristics
(IL = ±1mA; Vs = ±20V, CL= 10pF; RM4195: -55°C ~TA~+125OC; RC4195: OOC ~TA~+70OC unless otherwise
specified)!
RC/RM4195
Parameters

Test CondItions

MIn

Une Regulation
Load Regulation
Output Voltage Drift With
Temperature
Supply Current
Supply Voltage
Output Voltage
Output Voltage Tracking
Ripple Rejection
Input-Output Voltage Differential
Short Circuit Current

F = 120 Hz, TA = +25°C
IL =50 rnA
TA= +25°C

Output Noise Voltage

TA = +25°C, F = 100Hz to 120kHz

Internal Thermal Shutdown

..

Vs = ±18V to :t30V
IL =1mA to 100rnA

Vs = :t30V, IL = 0 mA
±18
14.5

TA = +25°C

Typ

Max

Units

2
5

20
30

mV
mV

0.005 0.015
±1.5 ±4.0
:t30
15.0 15.5
:1:50 :t300
75

3.0
220

..

%IOC
mA
V
V
mV
dB
V
mA
J,LVRMS

60
175

°C

lThe specificationS above apply for the given Jundlon temperatures Since pulse lest cond~lOns are used.

For More Infoonation, call 1-800-722-7074.

Raytheon Semiconductor

3-771

I

RC4195
Typical Performance Characteristics
Standby Current Drain

Output Load Regulation
·2

-...:

2
GI>

WE

4

~ 15

6

5=
~.!!!

8

8!

--

Lr-RM4195: -5500 to +ISOOC

0

:= ......

2.5

r-. -...:

RC4195: OOC to +12500

r-

"";r-. '-

~

./

......

10

"'..
.§..

o

c

1.0

>.a
c

m
40

20

80

60

+25·C
+ 25°C

1.5

.
a
!

-a

Vs = ±laV
TJ =TA

12
14

RC4195:0·C
2.0 I " - RM4195: ·55·C

100

0.5

o
18

16

20

22

'L(mA)

2.5

I

.s-::::,
:::I as
g ~2.0
!
~GI
5!!:

TA= RC4195:00C
TA = RM4195: -55°C-

1 Positive Regulator

L..-

TA = +25°C

~

k-

:::I

o

Q

1.0

E

.2
c
~

0

I--'"'

RM4195:-550Cto +150"C
20

.- ~

I

~

I

2.0

i'
-;
1!

i

~

~ ~

f""o.....

N

1.0

"'

;g 120

a
~

" ""'"-

N ~
80 I - - Package

iii 40

~

o

r-....
........

o

2.0

4.0

6.0

8.0

10

---

12

o

o

+25 +50 +75 +100 +125

14

~

·20

c -30

I L • 0 m}

!c

!

a:

·70
·80

1/
./

Raytheon Semiconductor

I

II

I

Positive Re! ulatol

./

"

·90

·100
100

I

L,...-4

·50
-60

I

Negative Regulator

oS! -40

8:
16

·10

Input/Output Voltage Differential (V)

3·772

,~
~

o

CD

r- l"'""-

I - - - - N o Heat Sink
- - __ Infinite Heat Sink

r-.,.......

Ripple Rejection

T 1'\ f - ~ ......:
\\
K~I
\ ~ackage~ ,~ackage"
.\ \.
1\."\
"
I'..

.§.. 160
1:

I'

0.5

·75 ·50 ·25

100

"'

I"-..

1.5

Maximum Current Capability
200

32

"-

T

o

I

80

60

40

30

1000

til

T A= +25°C
i.- ~ I-- ~t--.
""" Regulator
J .1
~RC4195: 000 to +125°C Nega~

o

28

K

AVOUT =20mV

~
5 >3.0

26

Power Dissipation

Regulator Dropout Voltage
4.0

GI

24

VIN (V)

1.0K

10K

lOOK

~

1M

F(Hz)

For Mors Information, call

1-800-722-7074.

RC4195
Typical Applications
+15Vat 100 rnA

+18Vto +30V

+VOUT

+Vs
4195

-18V to -30V
-Vs

GND

+
-:;I;

-15Vat 100 mA

-VOUT

+~

-=

10l1F

10l1F

65-0100

Balanced Output (Vour =± 15V)

VOUT = +50Vat 100 mA

+53V to +6IJV

+VOUT t - -.....-

+

.....--o

-,J 10l1F
-Vs

Rl
R2
15K
VOUT =+15V(1 +Fi1) '--_ _ _ _ _....
R2
35K

(VOUT + 3V) < +Vs < 60V

65-0101

Positive Single Supply (+15V < Vour < +50V)

'Rse

2N4905 or Equiv.

~------~

r~--------------~r-~~--;

I

+VOUT=+15V
47
+Vs

+Vs
4195
47

-Vs

-VOUT t-.....- - t - - Q -VOUT = -15V

-Vs
Comp-

Load Regulation
10mA@2.5A
'Rsc

2N4914 or Equiv.

'R

-~

se - Isc

High Output Current

For More Information, caJll-800-722-7074.

Raytheon Semiconductor

65-0102

3-773

RC4195
Brownout Protection
The 4195 is one of the most easily applied and
trouble-free monolithic ICs available. When used
within the data sheet ratings (package power
dissipation, maximum output current, minimum and
maximum input voltages) it provides the most costeffective source of regulated ±15V for powering linear
ICs.
Sometimes occasions arise in which the 4195 ratings
must be exceeded. One example is the "brownour.
During a brownout, line voltages may be reduced to
as low as 75 VRMS' causing the input voltage to the
4195 to drop below the minimum dropout voltage.
When this happens, the negative output voltage can
go to positive. The maximum amount of current
available is approximately 5 mA.
In general this is not enough current to damage most
ICs which the 4195 might be supplying, but it is a
potentially destructive condition. foretunately, it is easy
to protect against. As shown in the typical application
circuit, a diode, 0, can be connected to the negative
output.
If a small signal silicon diode is used, it will clamp the
negative output voltage at about +O.55V. A Schottky
barrier or germanium device would clamp the voltage
at about +O.3V. Another cure which will keep the
Balanced Output (VOUT

= ±15V)

negative output negative all times is the 1 mil resistor
connected between the +15V output and the comp terminal. this resistor will then supply drive to the
negative output transistor, causing it to saturate to -1 V
during the brownout

Heatsinking
When operating these devices near their extremes of
load current, ambient temperature and input-output
differential, consideration of package dissipation
becomes important to avoid thermal shutdown at
175"C. The 4195 has this feature to prevent damage
to the device. It typically starts affecting load
regulation approximately 2"C below 175°C. To avoid
shutdown, some form of heatsinking should be used
or one of the above operating conditions would need
to be derated:
The following is the basic equation for junction
temperature:
(1)

where
TJ = junction temperature ("C)
TA = ambient air temperature (0C)
PD = power dissipated by device (W)
OJ-A = thermal resistance from junction to
ambient air ('C/W)

lMn

+15Vat 100mA

+18VTo+30V
+vs

+VOUT

-18VTo-30V
-Vs

+

:c

4195
-VOUT

-=

1011f
-15Vat 100 mA

Gnd

o

Typical Application CircuH
• In allowing for process deviations. the user should work with a
maximum allowable fundion temperature of l50'C

3-774

Raytheon Semiconductor

For More Information, call 1-800·722·7074.

RC4195
The power dissipated by the voltage regulator can be
detailed as follows:

should be employed. If reliability is of prime
importance, the multiple regulator approach should be
considered.
In equation 1, OM can be broken into the following
components:

where
VIN = input voltage
Vem= regulated output voltage
10 = load current
IQ = quiescent current drain

0J-A = 9J.C + 9c.s + 9s.A

Let's look at an application where a user is trying to
determine whether the 4195 in a high temperature
environment will need a heatsink.
Given:
TJ at thermal shutdown = 150°C
TA = 125°C
9J-A = 41.6°CIW, K (T0-66) pkg.
V1N =40V
VWT = 30V
10 = 1 rnA + 75 J.lAIVem x 30V
=3.25 rnA·

where
9J-C = junction-to-case thermal resistance
9c.s = case-to-heatsink thermal resistance
9s-A= heatsink-to-ambient thermal resistance
In the above example, let's say that the user's load
current is 200 rnA and he wants to calculate the
combined 9c.s and 0s.A he needs:
Given: 10 = 200 rnA,

(VIN - Vem) x 10 + VIN X 10
50°C -125°C

OJ-A

10V x 200 rnA + 40 x 3.25 x 10-3

=---

Given 0J-C = 7.15°CIW for the 4195 in the
K package,
8c.s + 8s.A = 11.75°CIW - 7.15OCIW

Solve for 10 ,

= 4.6OCIW

150°C - 125°C
41.6°C/W x 10V
=

40 x 3.25 X 10-3
10

When using heatsink compound with a metal-to metal
interface, a typical 9c.s = 0.5°CIW for the K package.
The remaining 8s.A of approximately 4°CIW is a large
enough thermal resistance to be easily provided by a
number of heatsinks currently available. Table 1 is a
brief selection guide to heatsink manufacturers.

50 rnA - 13 rnA - 47 rnA

If this supply current does not provide at least a 10%
margin under worst case load conditions, heatsinking

• The current drain will increase by 501lANour on pos~ive side and
100llANour on negative side.

For More Information, call 1-800·722·7074.

Raytheon Semiconductor

3-775

I

RC4195
Table 1. Commercial Heatsink Selection Guide

No attempt has been made to provide a complete list of all heatsink manufacturers. This list is only representative.

9u ·COCIW)

Manufacturer/Series or Part Number
TO-66 Package

0.31-1.0

Thermalloy - 6441, 6443, 6450, 6470, 6560, 6590, 6660, 6690

1.0 - 3.0

Wakefield - 641
Thermalloy- 6123,6135,6169,6306,6401,6403,6421,6423,6427,6442,6463,6500

3.0 - 5.0

Wakefield - 621, 623
Thermalloy-6606,6129,6141,6303
JERC-HP
Staver - V3-3-2

5.0-7.0

Wakefield - 690
Thermalloy-6002, 6003,6004, 6005, 6052,6053,6054, 6176,6301
JERC-LB
Staver- V3-5-2

7.0 -10.0

Wakefield - 672
Thermalloy-6001, 6016, 6051, 6105,6601
JERC-LA,uP
Staver - V1-3, V1-5, V3-3, V3-5, V3-7

10.0-25.0

Thermalloy - 6-13, 6014, 6015, 6103, 6104, 6105, 6117
T0-99 Package

12.0 -20.0

Wakefield - 260
Thermalloy -11 01, 1103
Staver - V3A-5

20.0 - 30.0

Wakefield - 209
Thermalloy-1116,1121,1123,1130, 1131,1132,2227,3005
IERC-LP
Staver - F5-5

3.0 -50.0

Wakefield - 207
Thermalloy - 2212, 2215, 225, 2228, 2259, 2263, 2264

20
30
32
34
45
60

Thermalloy Thermalloy Thermalloy Thermalloy IERC-LJ
Wakefield -

Dual In-line Package
6007
6010
6011
6012
650, 651

• All values are typical as given by manufacturer or as determined from characteristic curves supplied by manufacturer.

Staver Co., Inc.: 41-51 N Saxon Ave., Bay Shore, NY 11706
IERC: 135 W Magnolia Blvd., Burbank, CA 91502
Thermalloy: P.O. Box 34829, 2021 W Valley View Ln., Dallas, TX
Wakefield Engin Ind: Wakefield, MA 01880
3-776
Raytheon Semiconductor

For More Information, call H!OO-722-7074.

RC4195
Schematic Diagram
+Vs
(8)

R1
10K

r--------i---;---o

Comp+
(1).

Ground
R7

(2)

3

+15V

t - - O Output
(7)

Comp(3)

BaJance
(6)

-15V

Output
(5)

-VS
(4)

·Pin numbers are for 8-pin packages.

65-0090

I
For More Information, call 1-800-722-7074.

Raytheon semiconductor

3-n7

RC4195

3-ns

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4391
RC4391
Inverting and Step-Down Switching Regulator
Description

Features

Raytheon's RC4391 is a monolithic switch mode
power supply controller for micropower circuits. The
4391 integrates all the active functions needed for low
power switching supplies, including OSCillator, switch,
reference and logic, into a small package. Also, the
quiescent supply current drawn by the 4391 is
extremely low; this combination of low supply current,
function, and small package make it adaptable to a
variety of miniature power supply applications.

•

The 4391 complements another Raytheon switching
regulator IC, the RC4190. The 4190 is dedicated to
step-up (Voor > Vtl) applications, while the 4391 was
designed for inverting (Voor = -VIN) and step-clown
(Voor < Vtl) applications. Between the two devices
the ability to create all three basic switching regulator
configurations is assured. Refer to the 4190 data
sheet for information on step-up applications.

•
•
•
•

VersatileInverting function (+ to-)
Step-down function
Adjustable output voltage
Regulates supply changes
MicropowerLow quiescent current - 170 (.IA
Wide supply range - 4V to 30V
High performance High switch current -375 mA
High efficiency - 70% typically
Low battery detection capability
8-lead mini-DIP or S.O. package

The functions provided are:
• Squarewave oscillator (adjustable externally)
• Bandgap voltage reference
• High current PNP switch transistor
• Feedback comparator
• Logic for gating the comparator
• Circuitry for detecting a discharged
battery condition (in battery powered systems)

I

Few external components are required to build
a complete DC-to-DC converter:
• Inductor
• Low value capacitor to set the oscillator
frequency
• Electrolytic filter capacitor
• Steering diode
• Two resistors

For More Information, call 1-800·722-7074.

Raytheon Semiconductor

3-779

RC4391
Absolute Maximum Ratings

Connection Information

Internal Power Dissipation ............................. SOO mW
Supply Voltage1
(Pin 6 to Pin 4 or
Pin 6 to Pin S) ...............................................+30V
Storage Temperature
Range ......................................... -6S·C to +1S0'C
Operating Temperature Range
RM4391 ....................................... -SS·C to +12S'C
RV4391 ......................................... -2S·C to +8S'C
RC4391 ............................................ O·C to +70'C
Switch Current (IMAX) .............................. 375 rnA peak

Small Outline

8·Lead DIP
(Top View)

50·8
(Top View)

65-02666

Pin
1
2
3
4
S
6
7
8

Function
Low Battery Resistor (LBR)
Low Battery Detector (LBO)
Timing Capacitor (Cx)
Ground
External Inductor (Lx)
+Supply Voltage (+Vs)
+1.2SV Reference Voltage (VREF)
Feedback Voltage (VFB)

Note:
1. The maximum allowable supply voltage (+Vs) in inverting
applications will be reduced by the value of the negative
output voltage, unless an external power transistor is used
in place of Q1.

Functional Block Diagram

Ordering Information

RC4391N
RC4391M

N
M

Operating
Temperature
Range
O·C to +70°C
O·C to +70°C

RV4391N

N

-2So C to +85°C

RM43910

0

-5S'C to +12SoC

Part Number

Package

65-1610

Notes:
I883B suffix denotes Mil-Sld-883. Level B processing
N =8-lead plastic DIP
D = 8-lead ceramic DIP
M =8-lead plastic sOle

3-780

Raytheon Semiconductor

For More Infonnation, call 1-800-722-7074.

RC4391
Thermal Characteristics
8-Lead
Plastic DIP

8-Lead
Ceramic DIP

Small Outline
SO-8

Max. Junction Temp.

+125°C

+175°C

125°C

Max. Po TA<50·C
Therm. Res 9JC

468mW

833mW

300mW

-

45°C/W

Therm. Res. 9JA

160°C/W

150°C/W

240°C/W

6.25mW/oC

8.33 mW/oC

4.17 mW;oC

For TA >50·C Derate at

-

Electrical Characteristics

(Vs = +6.ov, over the full operating temperature range unless otherwise noted)
Parameters
Supply Voltage
Supply Current
Reference Voltage

Output Voltage

Symbol
+Vs
ISY

Condition
(Note 1)
Vs=+2SV

VREF
VOOT

VOOToom = -S.OV
VOOTnom = -1SV

Min
4.0
1.13

300
1.25

Max
30
SOO
1.36

-S.S
-16.S

-S.O
-1S.0

-4.S
-13.S

2.0

4.0

VOOToom = -S.OV,
C x =1S0pF
Vs = +S.8V to +1SV
Line Regulation

Load Regulation

Switch Leakage Current

Typ

V

OfoVOOT

L1.
VOOToom = -1SV,
Cx = 1S0pF
Vs = +S.8V to +1S

1.S

3.0

VOOToom = -S.OV,
Cx = 3S0pF, Vs = +4.SV,
PLOAD = OmW to 7SmW

0.2

O.S
OfoVOOT

LO.

leo

Units
V
pA
V

VOOToom = -1SV,
Cx = 3S0pF, Vs = +4.SV,
PLOAD = OmW to 7SmW

0.2

0.3

Pin 5 = -20V

0.1

30

pA

NOIe 1. The maximum allowable supply voltage (+VS) in inverting applications wiU be reduced by the value of the negative output vohage. unless an external
power transistor is used.

For More Information, call HIOO-722·7074.

Raytheon Semiconductor

3·781

I

RC4391
Electrical Characteristics
(Vs = +6.0V, TA = +25°C unless otherwise noted)
Parameters

Supply Voltage

Symbol

Condition
Vs=+4·0V,
No External Loads

Max
250

300

500

-5.35

-5.0

-4.65

-15.85

-15.0

-14.15

1.5

3.0

1.0

2.0

0.2

0.4

VOOT

V

LI,

%VOOT
Vooroom =-15V,
Cx = 150pF
Vs = +5.8V to +15V
Voor oom = -5.0V,
Cx = 350pF, Vs = +4.5V,
PLOAD = OmW to 75mW

Load Regulation

%VWT

LO,
Voor rom = -15V,
Cx = 350pF, VS = +4.5V,
PLOAD = OmW to 75mW

Reference Voltage
Switch Current
Switch Leakage Current
Cap. Charging Current
LBD Leakage Current
LBD On Current
LBR Bias Current

3-782

VREF
Isw

lco
lex
ILBOL
ILSIlO
ILBRB

Units

J.lA

Voor rom = -15V
Voor rom = -5.0V,
CX= 150pF,
Vs = +5.8V to +15V
Line Regulation

TYJt
170

ISY

Vs=+25V
No External Loads
Voorrom = -5.0V
Output Voltage

Min

Pin5=5.5V
Pin 5 = -24V
Pin3 =OV
Pin 1 = 1.5V, Pin 2 = 6.0V
Pin 1 = 1.W, Pin 2 = O.4V
Pin 1 = 1.5V

1.18
75
6.0
210

Raytheon Semiconductor

0.07

0.14

1.25
100
0.01
10
0.01
600
0.7

1.32

V
mA

5.0
14
5.0

J.lA
J.lA
J.lA
J.lA
J.lA

For More Information, calI1-8()()"722·7074.

RC4391
Typical Performance Characteristics
Oscillator Frequency VS. Supply Vottage

OSCillator Frequency vs. Temperature

6.5
,/

6.0
5.5

~

5.0

~

4.5

~

8

./

7

L
V

6
5

V

4

tL

4.0

o

5

---

3

10

15

2

~

3.5
3.0

V

20

o

25

-55

Reference Vottage VS. Temperature

o

70

125

1.260

1.255

}

k-"':"

Reference Vottage VS. Supply Vottage

1.260

€

V

L

~

L

1.250
1.245

V

/

1.255

~~

€III

..

V

I..--"'"

1.250

,,/

>

1.245

'"
\8'"
~

1.240

o

-55

25

70

125

1.240

4

6

TA (OC)

20

30

+Vs(V)

Collector Current VS. 01 Saturation VoHage

Minimum Supply Vottage vs. Temperature
4

600
500
L

400

4"
.§. 300
200
100
20
10

10

I
o

/

lL

~

v

..-

3

€

-::+

~

2

..............

----

0

1:;

:z
 50 ~ are used for the voltage
setting resistors (R1 and R2 of Figure 2) stray
capacitance at the VFB input can add lag to the feedback
response, destabilizing the regulator, increasing low
frequency ripple, and lowering efficiency. This can often
be avoided by minimizing the stray capacitance at the
VFB node. It can also be remedied by adding a lead
compensation capacitor of 100 pF to 10 nF. In inverting
applications, the capacitor connects between -Voor and
VFB; for step-down circuits it connects between ground
and VFB• Most applications do not require this capacitor.

The entire device may be shut down to an extremely low
current non-operating condition by disconnecting the
ground (pin 4). This can be easily done by putting an
NPN transistor in series with ground pin and switching it
with an external signal. This switch will not affect the
efficiency of operation, but will add to and increase the
reference voltage by an amount equal to the saturation
voltage of the transistor used. A mechanical switch can
also be used in series between circuit ground and pin 4,
without introducing any reference offset

Inductors

The most important consideration in selecting an
external power transistor is the saturation voltage at Ie =
IMAX• The lower the saturation voltage Is, the better the
efficiency will be. Also, a higher beta transistor requires
less base drive and therefore less power will be.
Also, a higher beta transistor requires less base drive
and therefore less power will be consumed in driving it,
improving efficiency losses In the interface. The part
numbers given in the following applications are
recommended, but other types may be more appropriate
depending on voltage and power levels.

Efficiency and load regulation will improve if a quality
high 0 inductor is used. A ferrite pot core is
recommended; the wind-yourself type with an air gap
adjustable by washers or spacers is very useful for
bread-boarding prototypes. Care must be taken to
choose a core with enough permeability to handle the
magnetic flux produced at IMAX• If the core saturates,
then efficiency and output current capability are severely
degraded and excessive current will flow through the
switch transistor. A pot core inductor design section is
provided later in this datasheet.

Power Transistor Interfaces

An isolated AC current probe for an oscilloscope
(example: Tektronix P6042) is an excellent tool for
saturation problems; with it the inductor current can be
monitored for nonlinearity at the peaks (a sign of
saturation).

R4

-

Low Battery Detector

An open collector signal transistor 02 with comparator
C2 provides the designer with a method of signaling a
display or computer whenever the battery voltage falls
below a programmed level (see Figure 7). This level is
determined by the +1.25V reference level and by the
selection of two external resistors according to the
equation:

I Lllo

R5

I

65-1651A

Figure 7. Low Battery Detector

VTH = VRE.F (R4 +1 )
R5
When the battery drops below this threshold 02 will turn
on and sink typically 600~. The low battery detection
circuit can also be used for other less conventional
applications such as the voltage dependent oscillator
circuit of Figure 12.

For More Information, call 1-800·722·7074.

Raytheon Semiconductor

3·789

RC4391
When troubleshooting external power transistor circuits,
ensure that clean, sharp-edged waveforms are driving
the interface and power transistors. Monitor these
waveforms with an oscilloscope - disconnect the
inductor, and tie the VFB input (pin 8) high through a 10K
resistor. This will cause the regulator to pulse at
maximum duty cycle without drawing excessive inductor
currents. Check for expected on time and off time, and
look for slow rise times that might cause the power
transistor to enter its linear operating region.
The following external power transistor circuits may
demand some adjustment to resistor values to satisfy
various power levels and input/output voltages. Cx and
Lx values must be selected according to the design
equations (pages 9 and 10).

Inverting Medium Power Application
Figure 8 is a schematic of an inverting medium power
supply (250mW to 1W) using an external PNP switch
transistor. Supply voltage is applied to the IC via R3:
when the internal switch transistor is turned on current
through R4 is also drawn through R3; creating a voltage
drop from base to emitter of the external switch
transistor. This drop turns on the external transistor.

Voltage pulses on the supply lead (pin 6) do not affect
circuit operation because the internal reference and bias
circuitry have good supply rejection capabilities. A power
Schottky diode is used for higher efficiency.

Inverting High Power Application
For higher power applications (500mW to 5W), refer to
Figure 9. This circuit uses an extra external transistor to
provide well controlled drive current in the correct phase
to the power switch transistor. The value of R3 sets the
drive current to the switch by making the interface
transistor act as a current source. R4 and R5 must be
selected such that the RC time constant of R4 and the
base capacitance of Q2 do not slow the response time
(and affect duty cycle), but not so low in value that
excess power is consumed and efficiency suffers. The
resistor values chosen should be proportional to the
supply voltage (values shown are for +5V).

+5V

C1

O.11l'i

R3
lkO

R2
62kO

5
7
6
VFB VREF +vs
4391

5
Lx

R4
500

R1
1.2MO

6S-2476

Figure 8. Inverting Medium Power Application

3-790

Raytheon Semiconductor

For More Information, call 1-000-722-7074.

RC4391

C1

O.lll~

R2

4391

65-2478

Figure 9. Inverting High Power Application

Ste!>,Down Power Applications
Figures 10 and 11 show medium and high power
interfaces modified to perform step-down functioning.
The design equations and suggestions for the circuits of
Figures 8 and 9 also apply to these circuits. For a
certain range of load power, the RC4193 can be used
for ste!>,sown applications. A load range from 400mW to
2W can be sustained with fewer components (especially
when stepping down greater than 30V) than the
comparable 4391 circuit. Refer to Raytheon's RC4191!
419214193 data sheet for a schematic of this medium
power step-down application.

The threshold is programmed exactly as the normal low
battery detector connection:

When the battery voltage reaches this threshold the
comparator will turn on the open collector transistor at
pin 2, effectively pulling Cy in parallel with CX' This
added capacitance will reduce the oscillator frequency,
according to the following equation:

VoHage Dependent Oscillator
The 4391's ability to supply load current at low battery
voltages depends on the inductor value and the
oscillator frequency. Low values of inductance or a low
oscillator frequency will cause a higher peak inductor
current and therefore increase the load current
capability. A large inductor current is not necessarily
best, however, because the large amount of energy
delivered with each cycle will cause a large voltage
ripple at the output, especially at high input voltages.
This trade-off between load current capability and output
ripple can be improved with the circuit connection shown
in Figure 12. This circuit uses the low battery detector to
sense for a low battery voltage condition and will
decrease the oscillator frequency after a preprogrammed threshold is reached.

For More Information, calI1-8CJO..722-7074.

Current Limiting
The oscillator (Cx) pin can be used to add short circuit
protection and to protect against over current at start-up
(when using large values for the output filter capacitor greater than 100 ~). A transistor VBE is used as a
current sensing comparator which resets the oscillator
upon sensing an over current condition, thus providing
cycle-by-cycle current limiting. Figure 13 shows how this
is applied.

Raytheon Semiconductor

3-791

I

RC4391
CI

O.I~F~

RI

~----~----~----~--~---o~ruT

Note: A minlum load ::t I mA must be connected.

Figure 10. Step-Down Medium Power Application
MBRI40P
I
I
I

5000

1__ -

6

+I O
·3_V__..-__7, v AEF

-=-+ V

+vs
4391

BAT

5

LXH--r

8

RI
51(

(+)
VOllT

(+5ValIA
as shown)

(-)
Note: A minium load ::tlmA must be connected.
·Optional - Extends supply voHage range.

65·2077

Figure 11. Step-Down High Power Application

4391

2N3906
or Equivalent
R4

3

ex

4391

65-2159

R5
65-2053

Figure 12. Voltage Dependent Oscillator

3-792

Raytheon Semiconductor

Figure 13. Current Limiting

For More Information. call 1-800-722-7074.

~

W
:::T

f

(I)

f
J'

3

+Vs

LBR

LBO

(6)

(1)

ex

(2)

(3)

~

~

I~

I~

Q

ij

~

~ Rl

JOl

~

J02

I "":l.

~540K

~Q4

0.6

0.3

~:::r

Q3AJ
O'S r-....

l~C
1 Q6

2;~F ~Q9

:J

ffl

~
4X~ ~

R2
3K

3

.~

~

c

ao
;~

6~~

0.1

I"

01SL 019
0.1

~~

01S~Z

H«

rt:~OS
7016
R6
20K

I

~022
I.....

012

023

£;;-

~

014~

1::;044

~

~~

i

l~gK~

o

r-.... 0.9 r-.... 0.9 '" 0.9

J,
'"

034
.1

DJ
3

k015
016
'" 2X
L

07

~~OS

R7

~~ Q39~
029
SOX

~

~10K

040>-

R3
S.2K

~:S~

jQ3 j03J032J033

l:l-,

,"1~~

0.1

I'

lOX

N

~04S
Q46

...

c

~'

~
~35 036~")IJ-t---+---1'
027;/1

~011

07"'-l

g'

O.S ...

1~~'

! ..

CD

J01H

03BJ

" Q4B 010
'"
r..:

°b j

o

.

IJ

'"

a(;'

026
40X

....

~2S

~

~024

013

'*~

"i2 013

Q4~
010Y

..
042....
2X".

yQ43
'" 2X

01~7

";2

0

J

(]

(7)

(S)

(4)

VREF

VFB

(S)
Lx

014

GNO
65-6364

~

Co)

~
~

\C
......

RC4391
Troubleshooting Chart
Symptom
Draws excessive supply current on star-up.

circuit (Figure 13).
Output voltage is low.
Inductor "sings" with audible hum.
scope will not synchronize.

Lx pin appears noisy -

Possible Problems
Inductance value too low.
Output frequency (Fol too low.
Combination of low resistance inductor and high
value filter capacitor - needs current limiting
Inductance value too high for F0 or core
saturating.
Not potted well or bolted loosely.
Normal operating condition.
Inductor is saturating:
1. Core too small.
2. Core too hot.
3. Operating frequency too low.

Time
Inductor current shows nonlinear waveform.
Waveform has resistive component:
1. Wire size too small.
2. Power transistor lacks base drive.
3. Components not rated high enough.
4. Battery has high series resistance.
Inductor current shows nonlinear waveform.

~
ILXC

-1MAl(

External transistor lacks base drive or beta is
too low.

,/\, ,

Time
fi5-6349
Inductor current is linear until high current is reacheo.
Poor efficiency.
Core saturating.
Diode or transistor:
1. Not fast enough.
2. Not rated for current level (high VceSAT).
High series resistance.
Operating frequency too high.
Motorboating (erratic current pulses).

3-794

Loop stability problem - needs feedback capacitor
from Voor to VFB (pin 8). 100pF to 1000pF.

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4391
Pot Core Inductor Design
Electrical CircuH

Magnetic CircuH

I

EORE-"R

North

65-1720
Flux

65-1721

Figure 14. ElectricHy vs. Magnetism

Electricity Versus Magnetism
Electrically the inductor must meet just one requirement,
but that requirement can be hard to satisfy. The inductor
must exhibit the correct value of inductance (L, in
Henrys) as the inductor current rises to its highest
operating value (I MAX). This requirement can be met
most simply by choosing a very large core and winding it
until it reaches the correct inductance value, but that
brute force technique wastes size, weight and money. A
more efficient design technique must be used.

Question: What happens if too small a core is used?
First, one must understand how the inductor's magnetic
field works. The magnetic circuit in the inductor is very
similar to a simple resistive electrical circuit. There is a
magnetizing force (H, in oersteds), a flow of magnetism,
or flux density (B, in Gauss), and a resistance to the flux,
called permeability (U, in Gauss per oersted). H is
equivalent to voltage in the electrical model, flux density
is like current flow, and permeability is like resistance
(except for two important differences discussed to the
right).

First Difference: Permeability instead of being
analogous to resistance, is actually more like
conductance (1/R). As permeability increases, flux
increases.
Second Difference: Resistance is a linear function. As
voltage increases, current increases proportionally, and
the resistance value stays the same. In a magnetic
circuit the value of permeability varies as the applied
magnetic force varies. This nonlinear characteristic is
usually shown in graph form in ferrite core
manufacturer's data sheets .
6000

+25°C

5000

:I

1 ~

~ 3000
CD

o

L.-

~

.

+1rf-

~ ~

2000
1000

I

'- ~ ":;:a5°C_

4000

J

I
Stackpole Ceramag 24B
r- Hysteresis Loop vs. Temperature
I
I
I
I
I
II
I

1n

-D.5 0 0.5 1

22.53579
H Oersteds

Figure 15. Typical Manufacturer's Curve Showing
Saturation Effects

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-795

RC4391
As the applied magnetizing force increases, at some
point the permeability will start decreasing, and therefore
the amount of magnetic flux will not increase any further,
even as the magnetizing force increases. The physical
reality is that, at the point where the permeability
decreases, the magnetic field has realigned all of the
magnetic domains in the core material. Once all of the
domains have been aligned the core will then carry no
more flux than just air, it becomes as if there were no
core at all. This phenomenon is called saturation.
Because the inductance value, L, is dependent on the
amount of flux, core saturation will cause the value of L
to decrease dramatically, in tum causing excessive and
possibly destructive inductor current
Pot Cores for RC4391

Pot core inductors are best suited for the RC4391
switching regulator for several reasons:
1. They are available In a wide range of sizes.
RC4391 applications are usually /ow power with
relatiVely low peak currents (less than 500mA). A
small inexpensive pot core can be chosen to meet
the circuit requirements.

2. Pot cores are easily mounted. They can be bolted
directly to the PC card adjacent to the regulator IC.

3. Pot cores can be easily air-gapped. The length of
the gap Is simply adjusted using different washer
thicknesses. cores are also available with
predetermined air gaps.
4. Electromagnetic Interference (EMI) Is kept to a

minimum. the completely enclosed design of a pot

3-796

core reduces stray electromagnetic radiation - an
important consideration if the regulator circuit is built
on a PC card with other circuitry.
Core Size
Question: Is core size selected according to load
power?
Not quite. Core size Is dependent on the amount of
energy stored, not on load power. Raising the operating
frequency allows smaller cores and windings. Reduction
of the size of the magnetics Is the main reason switching
regulator design tends toward higher operating
frequency. Designs with the RC4391 should use 75 kHz
as a maximum running frequency, because the tum off
delay of the power transistor and stray capacitive
coupling begin to interfere. Most applications are in the
10 to 50 kHz range, for efficiency and EMI reasons.
The peak induclor current (IMAX) must reach a high
enough value 10 meet the load current and
simultaneously the Inductor value Is decreased, then the
core can be made smaller. For a given core size and
winding, an increase in air gap spacing (an air gap Is a
break in the material in the magnetic path, like a section
broken off a doughnut) will cause the inductance to
decrease and 'MAX (the usable peak current before
saturation )to increase.
The curves shown are typical of the ferrite
manufacturer's power HF material, such as Siemens
N27 or Stackpole 248, which are usually offered in
standard millimeter sizes including the sizes shown.
Use of the Design Aid Graph
1. From the application requirement. determine the
inductor value (L) and the required peak
current (IMAX).

Raytheon Semiconductor

For More InfcrmaIion, call 1-800-722·7074.

RC4391
#1

#2

#3

#4

22X
13mm

8

Air Gap - 0.02"
24 Gauge
70 Tums
Dcn.o.5O

3A

..

....
•I!a.

1SX
11 mm

8

2SGauge
70 Tums
DCn.0.7n

2A

!
j

14X
Smm

8

Air Gap - 0.012"

lA

2SGauge
SO Tums
Dcn-o.en

;::
~

11X
7mm

8

0

30 Gauge
50 Tums
Dcn.1n

1 mH

3mH

\Il

Inductor Value (Henries)
"Includes safety margin (25%) to ensure nonsaturation
Figure 16. Inductor Design Aid

2. Observe the curves of the design aid graph and
determine the smallest core that meets both the L
and I requirements.
3. Note the approximate air gap at IMAX for the
selected core, and order the core with the gap. (If
the gapping is done by the user, remember that a
washer Ispacer results in an air gap of twice the
washer thickness, because two gaps will be
created, one at the center post and one at the
rim, like taking two bites from a doughnut.)
4. If the required inductance is equal to the indicated
value on the graph, then wind the core with the
number of turns shown in the table of sizes. The
turns given are the maximum number for that gauge
of wire that can be easily wound in cores winding
area.
5. If the required inductance is less than the value
indicated on the graph, a simple calculation must be
done to find the adjusted number of turns. Find \
(inductance index) for a specific air gap.
L (indicated)
Turns2

=A

(in HenriesfTurn2)

"I.

Then divide the required inductance value by AL to
give the actual turns squared, and take the square
root to find the actual turns needed.
Actual Turns =

L (required)

\

If the actual number of turns is significantly less than
the number from the table then the wire size can be
increased to use up the leftover winding area and
reduce resistive losses.
6. Wind and gap the core as per calculations, and
measure the value with an inductance meter. Some
adjustment of the number of turns may be
necessary.
The saturation characteristics may be checked with
the inductor wired into the switching regulator
application circuit. To do so, build and power up the
circuit. Then clamp an oscilloscope current probe
(recommend Tektronix P6042 or equivalent) around
the inductor lead and monitor the current in the
inductor. Draw the maximum load current from the
application circuit so that the regulator is running at
close to full duty cycle. Compare the waveform you
see to those pictured.
Check for saturation at the highest expected
ambient temperature.

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-797

I

RC4391
Proper Operation
(Waveform Is Fairly Linear)

Improper Operation
(Waveform is Nonlinear, Inductor is Saturating)

65-1723
115-1722

Figure 17. Inductor Current Waveforms

7. After the operation in circuit has been checked,
reassemble and pot the core using a potting
compound recommended by the manufacturer.
If the core material differs greatly in magnetic

characteristics from the standard power material
shown in Figure 16, then the following general
equation can be used to help in winding and
gapping. This equation can be used for any core
geometry, such as an E-E core.

Lx =

Where:

3-798

(1.26) (N2)(Ae)(1OS)
g = (Iefue)

Manufacturers
Below is a list of several pot core manufacturers:
Ferroxcube Company
5083 Kings Highway
Saugerties, NY 12477
Indiana General Bectronics
Keasley, NJ 08832
Siemens Col'll>any
186 Wood Avenue South
Iselin, NJ 08830
Stackpole Company
201 Stackpole Street
St. Mary, PA 15857

N =number of turns
Ae = core area from data sheet (in cm2)
Ie = magnetic path length from data
sheet (in cm)
ue = permeability of core from
manufacturer's graph
g = center post air gap (in cm)

TDK Electronics
13-1, 1-Chrome
Nihonbaski, Chuo-ku, Tokyo

Raytheon Semiconductor

For Moralnfcnnation, call 1-800-722-7074.

RC4152
RC4152
Voltage-to-Frequency Converters

Description

Features

The 4152 is a monolithic circuit containing all of the
active components needed to build a complete voltageto-frequency converter. Circuits that convert a DC
voltage to a pulse train can be built by adding a few
resistors and capacitors to the internal comparator, oneshot, voltage reference, and switched current source.
Frequency-to-voltage converters (FVCs) and may other
signal conditioning circuits are also easily created using
these converters.

••
•••
•••
••
•

Raytheon was the first company to introduce a
monolithic VFC. The 4151 offers guaranteed
temperature and accuracy specifications. The converter
is available in a standard a-pin plastic DIP.

Applications

••
••
••
•

Functional Block Diagram
4152
Sw~ched

Current
Source Output
S~ched

Reference
Output

Comparator
) Inputs

Open Collector
Output

One Shot

Timing

65-1517

For More Information. calI1-8()()'722-7074.

Single supply operation
Pulse output DTIJTTlJCMOS compatible
Programmable scale factor (K)
High noise rejection
Inherent monotonicity
Easily transmittable output
Simple full scale trim
Single-ended input, referenced to ground
V-F or F-V conversion
Voltage or current input
Wide dynamic range

•
•
••

Precision voltage-to-frequency converters
Pulse-width modulators
Programmable pulse generators
Frequency-to-voltage converters
Integrating analog-to-digital converters
Long-term analog integrators
Signal conversion:
- Current-to-Frequency
- Temperature-to-Frequency
- Pressure-to-Frequency
- Capacitance-to-Frequency
- Frequency-to-Current
Signal isolation:
- VFG-<>pto-isolation-FVC
- ADC with opto-isolation
Signal encoding:
- FSK modulation/demodulation
- Pulse-width modulation
Frequency scaling
DC motor speed control

Raytheon Semiconductor

I
3-799

RC4152
Absolute Maximum Ratings

Ordering Information

Supply Voltage ...................................................... + 22V
Internal Power Dissipation ................................. 500 mW
Input Voltage .....•.•.•...........•..•..••.•......•...•..•• -O.2V to +VS
Output Sink Current
(Frequency Output) ......••...............••.•••..••.......•.. 20 mA
Output Short Circuit to Ground ...................... Continuous
Storage Temperature Range ................ -65°C to +150OC
Operating Temperature Range
RC4152 ................................................. O°C to +70OC
RV4152N ............................................ -25°C to -H35OC
Note:
1. "Absolute maximum ratings' are those beyond which the safety
of the device cannot be guaranteed. They are not meant to
imply that the device should be operated at these limits. If the
device is subjected to the limits in the absolute maximum
ratings for extended periods. its reliability may be impaired.
The tables of electrical Characteristics provide conditions for
actual device operatiolL

Part Number
RC4152N
RC4152M
RV4152N

Package
N
M
N

Operating
Temperature
Range
OOC to +70OC

Notes:
N • 8-lead plastic DIP
M • 8.Jead plastic SOIC

Connection Information

Pin
1
2

3
4
5
6
7

8

65-1529

Function
Switched Current Source Output (lOUT)
Switched Voltage Reference (RS)
Logic Output (Open Collector) (Four)
Ground (GND)
One-Shot R. C Timing (Co)
Threshold (VTH)
Input Voltage (VIN)
+VS

Thermal Characteristics
8-Lead
Plastic
DIP

Small
Outline
SO-8

Max. Junction Temp.

+125"C

+125"C

Max. Po TA c::50'C

468mW

300mW

160"CNI

240"C/W

6.25mWfC

4.17mWfC

Thenn. Res 9JC
Thenn. Res. 9JA

For TA >SO'C Derate at

3-800

Raytheon Semiconductor

For More Information. call 1-800-722·7074.

RC4152
Electrical Characteristics
(Vs == +15V, and TA == +25°C unless otherwise noted)
Parameters

Test Conditions

Max

Units

2.5

6.0

mA

+15

+18

V
mV

Min

Typ

+7.0

Power Supply Requirements (Pin 8)
Supply Current

Vs=+15V

Supply Voltage
Input Comparator (Pins 6 and 7)
Vas
Input Bias Current

±2.0

±10

-50

-300

nA

Input Offset Current

±SO

±100

nA

0

VS-2

Vs-3

V

0.65

0.67

0.69

V

·50

-500

nA

0.1

0.5

V

±30

±50

ppmFC

Input Voltage Range
One Shot (Pin 5)
Threshold Voltage
Input Bias Current
Saturation Voltage

1=2.2 mA

Drift 01 Timing vs.

T=75J.1S

Temperature 2

over specified temperature range

Timing Drift vs. Supply Voltage

±100

ppmN

Switched Current Source (pin 1) 1
Output Current

Rs = 16.7K, over

+138

Drift vs. Temperalure2

specified temperature range

±50

Drift vs. Supply Voltage

J.IA
±100

%N

0.10

Leakage Current

Off State

Compliance

Pin 1 = OV to +1 OV

1.0

ppm/OC

50

nA

1.0

2.5

2.0

2.25

2.5

±50

±100

V
ppm/oC

ISINK=3 mA

0.1

0.5

V

ISINK = 10 mA

0.8

Off State

0.1

1.0

J.IA

0.007

0.05

%

±75

±150

ppm/OC

J.IA

Reference Voltage (Pin 2)
VREF
Drift vs. Temperature 2
Logic Output (Pin 3)
Saturation Voltage
Leakage Current

over specified temperature range

Nonlinearity Error
(Voltage Sourced Circuit of Figure 3)

1.0 Hz to 10 kHz

Temperature Drift Voltage2

FOUT = 10kHz, over

(Voltage Sourced Circuit of Figure 3)

over specified temperature range

Noles:
1. Temperature coefficient of output CUlTent source (pin 1 output) exclusive of reference vohage drift.

2. Guaranteed but nol tested.

For More Information, call 1-800·722·7074.

Raytheon Semiconductor

3·801

I

RC4152
Typical Performance Characteristics
100 KHz Current-Sourced VFC

10KHz Current-Sourced VFC

Nonlineartty VS. Input VoHage

Nonlineartty VS. Input VoHage
+0.01

+0.06

+0.005

+0.03

I

0

""" .......... r-...

~

::; -0.005

- 'V

!

V

0 ...........

~

-0.03

z

Z

-0.01

~

o

1

2

3

4

5

6

7

8

9

~

=

'7

/

-0.06

~

-0.015

I'--

~

-0.09

10

~

o

2

3

4

VIN (V)

5

6

7

8

9

10

VIN(V)

100 KHz VoHage-Sourced VFC

10KHz VoHage-Sourced VFC

Nonlineartty VS. Input VoHage

Nonlineartty VS. Input VoHage

+0.10

+0.005

+0.05

"C"

"C"

g

0

w

.........

~

::;-0.005

i'- I'-..

Z

.,/'

.... .,/'

r--.

--"

0

~

-0.05

ill

-0.10

'"

-0.15

:b

o

2

3

4

5

6

..........

-

.........

Z

-0.01
-0.015

g

w

7

8

9

10

~

o

2

3

4

-

~

V V

+0.08

.... 1'--

g
~

~

-0.01

z
~

o

~
2

3

4

5

6

7

8

+0.04

w

Z

-0.015

9

10

0

./

V

v

V"

8

9

10

r-.... r--....
r"-..

-0.04
-0.08

o

FIN (kHz)

3-802

7

+0.12

+0.005

~

6

100 KHz Precision VFC
Nonlineartty vs. Input Frequency

+0.01

:;-0.005

5
VIN(V)

10KHz Precision VFC
Nonlineartty VS. Input Frequency

0

7
~

VIN(Y)

-~

/'

10 20 30 40 50 60 70

'"

ill
~

80 90 100

FIN (kHz)

Raytheon Semiconductor

For More Information, calI1.aoo-722-7074.

RC4152
Principles of Operation
The 4152 contains the following components: an open
loop comparator, a precision one-shot timer, a switched
voltage reference, a switched current source, and an
open collector logic output transistor. These functional
blocks are internally interconnected in a special way. By
adding some external resistors and capacitors, a
designer can create a complete voltage-to-frequency
converter.
The comparator's output controls the one-shot
(monostable timer). The one-shot in turn controls The
switched voltage reference, the switched current source
and the open collector output transistor. The functional
block diagram shows the components and their
interconnection.
To detail, if the voltage at pin 7 is greater than the
voltage at pin 6, the comparator switches and triggers
the one-shot. When the one-shot is triggered, two things
happen. First, the one-shot begins its timing period.
Second, the one-shot's output turns on the switched
voltage reference, the switched current source and the
open collector output transistor.
The one-shot creates its timing period much like the
popular 555 timer does, by charging a capacitor from a

reSistor tied to +Vs. The one-shot senses the voltage on
the capacitor (pin 5) and ends the timing period when
the voltage reaches 213 of the supply voltage. At the end
of the timing period, the capacitor is discharged by a
transistor similar to the open collector output transistor.
Meanwhile, during the timing period of the one-shot, the
switched current source, the switched voltage reference,
and the open collector output transistor all will be
switched on. The switched current source (pin 1) will
deliver a current proportional to both the reference and
an external resistor, Rs. The switched reference (pin 2)
will supply an output voltage equal to the internal
reference voltage (2.25V). The open collector output
transistor will be turned on, forcing the logic output (pin
3) to a low state. At the end of the timing period all of
these outputs will turn off. The switched voltage
reference has produced an off-on-off voltage pulse, the
switched current source has emitted a quanta of charge,
and the open collector output has transmitted a logic
pulse.
To summarize, the purpose of the circuit is to produce a
current pulse, well-defined in amplitude and duration,
and to simultaneously produce an output pulse which is
compatible with most logic families. The circuit's outputs
show a pulse waveform in response to a voltage
difference between the comparators inputs.

Integrator

I

+Vs

VIN

oto +10V
Current Setting Resistor
Rs = 16.7K

R'}

RLOAD

JLJL..

FOUT

r

Open Collector Output

One Shot
Timing

Co
65-1518

Figure 1. Single Supply VFC
For More Information, call H!00-722-7074.

Raytheon Semiconductor

3-803

I

RC4152
Applications

VINIRB. To operate correctly, the input voltage must be
negative, so that when the circuit is balanced, the two
currents cancel.

Single Supply VFC
The stand-alone voltage-to-frequency converter is one of
the simplest applications for the 4152. This application
uses only passive external components to create the
least expensive VFC circuit (see Figure 1).
The positive input voltage VIN is applied to the input
comparator through a low pass filter. The one-shot will
fire repetitively and the switched current source will pump
out current pulses of amplitude VREPRS and duration
1.1 ReCo into the integrator. Because the integrator is
tied back to the inverting comparator input, a feedback
loop is created. The pulse repetition rate will increase
until the average voltage on the integrator is equal to the
DC input voltage at pin 7. The average voltage at pin 6 is
proportional to the output frequency because the amount
of charge in each current pulse is precisely controlled.
Because the one-shot firing frequency is the same as the
open collector output frequency, the output frequency is
directly proportional to VIN.
The external passive components set the scale factor.
For best linearity, RS should be limited to a range of 12
knto20 kU
The reference voltage is nominally 1.9V for the 4151 and
2.25V for the 4152. Recommended values for different
operating frequencies are shown in the table below.
Operating Range
DC to 1.0 kHz
OCto 10kHz
OCto 100 kHz

Ro

Co

RB

CB

6.8kn 0.1 J.IF 100kn 10 J.IF
6.8kn 0.01 J.IF 100kn 10 J.IF
6.8kn 0.001 J.IF 100kn 10 J.IF

The single supply FVC is recommended for uses where
dynamic range of the input is limited, and the input does
not reach OV. With 10kHz values, nonlinearity will be
less than 1.0"10 for a 10 mV to 10V input range, and
response time will be about 135 ms.

Precision Current Sourced VFC
This circuit operates similarly to the single supply VFC,
except that the passive R-C integrator has been replaced
by an active op amp integrator. This increases the
dynamic range down to OV, improves the response time,
and eliminates the nonlinearity error introduced by the
limited compliance of the switched current source output.
The integrator algebraically sums the positive current
pulses from the switched current source with the current
3-804

T
-1- Four

-n

IVINI
{TPl
RB = lou

where TP = 1.1

RaCe

lOUT = V~~F

By rearranging and substituting,

FOUT=~.1 ~~RJ

["+ ]

Recommended component values for different operating
frequencies are shown in the table below.
Range
Input YIN
oto-lOY
oto-lOY
Oto-l0Y

Scale
Output Fo Factor
Ro
Co
CI
RB
Oto 1.0 kHz 0.1 KHzN 6.Skn 0.1 JJF 0.05 JJF 100 kn
Otol0 kHz 1.0 kHz 6.Skn 0.01 JJF 0.005 JJF 100 kn
Oto 100 kHz 10kHzN 6.Skn 0.001 uF 500 of 100 kn

The graphs shown under Typical Performance
Characteristics show nonlinearity versus input voltage
for the preciSion current sourced VFC. The best linearity
is achieved by using an op amp having greater than 1.0
V/J,lS slew rate, but any op amp can be used.

Precision Voltage Sourced VFC
This circuit is identical to the current sourced VFC,
except that the current pulses into the integrator are
derived directly from the switched voltage reference.
This improves temperature drift at the expense of high
frequency linearity.
The switched current source (pin 1) output has been tied
to ground, and RS has been put in series between the
switched voltage reference (pin 2) and the summing
node of the op amp. This eliminates temperature drift
associated with the switched current source. The graphs
under the Typical Performance Characteristics show
that the nonlinearity error is worse at high frequency,
when compared with the current sourced circuit.

Single Supply FVC
A frequency-to-voltage converter performs the exact

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4152
C,
0.005 JIF
lN914

Rs
Y,N

lOOK

oto -10V o--JV\/Ir-t

As =16.7K
I

At.

5.1K

FOUT 0--4-----=-1

RS
lOUT +Vs 8
4152
4 Gnd C VFC V
V'NI~7:....-_ _ _ _ _....I
o
TH
10kO

OUlplj Frequency
o S:FoS: 10kHz

6,t---~~JV\1Ir~-'

5

65-151;

Figure 2. Precision Current Sourced VFC

c,

0.0051'1'

Ra
lOOK

Y,N

o to -10V

R•• ,.,,,

1000

I

I

RL

5.1K
F;

2

3

IaurR.

OUT o--<~FOUT

Output Frequency
O~FOUT S:10kHz

4152

4 Gnd Co VFC V

TH

8

Y,N 1"'7'-_ _ _ _ _--J

6t-_ _ _-1~lVDVkO~~_,

5

Co
0.011'1'

+V.

5kO

ll1F

Ro

B.SkO
65-1521

Figure 3. Precision Voltage Sourced VFC

For More Information, call HlOO-722-7074.

Raytheon Semiconductor

3-805

RC4152
Output ripple can be minimized by increasing Ca, but this
will limit the response time. Recommended values for
various operating ranges are shown In the following table.

opposHe of the VFCs function; it converts an input pulse
train into an average output voltage. Incoming pulses
trigger the Input comparator and fire the one-shot. The
one-shot then dumps a charge into the output integrator.
The voltage on the integrator becomes a varying DC
voltage proportional to the frequency of the input signal.
Figure 4 shows a complete single supply FVC.

Input
Operating
Range
RO
Re
CIM
Ce
Co
010 1.0 kHz 0.02~ ~.8 k.Q 0.1~ 100 k.Q loo~
010 10kHz 0.002~ ~.8 k.Q 0.01 ~ 100 k.Q 10 JJF
010 100 kHz 200pF 6.8 k.Q 0.001 JJF 100 k.Q 1.0 JJF

The input waveform must have fast slewing edges, and
the differentiated input signal must be less than the
timing period of the one-shot, 1.1 ROCO. Adifferentiator
and divider are used to shape and bias the trigger input;
a negative going pulse at pin 6 will cause the
comparator to fire the one-shot. The input pulse
amplitude must be large enough to trip the comparator,
but not so large as to exceed the ICs input voltage
ratings.

Precision FVC
Unearity, offset and response time can be improved by
adding one or more op amps to torm an active Iowpass
filter at the output. Acircuit using a single pole active
integrator is shown in Figure 5.

The output voltage is directly proportional to the input
frequency:

VOUT = [ 1.1 •IlCIlV
'0 ;~ 'B REF

Ripple
loOmV
loOmV
1.0mV

The positive output current pulses are averaged by the
inverting integrator, causing the output voltage to be
negative. Response time can be further improved by
adding a double pole filter to replace the single pole filter.
Refer to the graphs under Typical Performance
Characteristics that show nonlinearity error versus input
frequency tor the precision FVC circuit.

J

FIN (Hz)

+15V o---....--I\M,.---...-----.

Ro
6.aka

10kO

Co
O.o1ILF

10 kO

FIN

7
C IN
V
0.022ILF
IN
1-_-.-=6=-1 VTH

o--f

Frequency
Input

5
Co Gnd 4
4152

VFC

FOUT 3

Rs

lOUT

2

-

o ~ FIN ~ 10kHz
10kn

+lSV

VOUT

} R. - 16.71<

Rs
lOOK
65-1521

Figure 4. Single Supply FVC

3-806

Raytheon Semiconductor

For More Information, call 1-800-722-7074_

RC4152
Ro
6.BkG

+15V

0-----+--''111\,.--.----,
10 kG
10kn

7

FIN

5

Co
0.011!F

~ '::"
VIN
Co Gnd 4
0.02211F
6
4152 VFC
1 - - - - - 1 VTH

o---J

Frequency Input
o ~Fo ~ 10kHz
5.0 Vp.p
Squarewave

L-_+~V~S~~~~~

5kG

B

10kn

RB

+15V

100kn

loon
~~-J\M-~-oVOUT

Voltage Output

RB
100 kG

Offset
Adjust

-10V~Vo~0

65-1522

Figure 5. Precision FVC

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-807

Co

en

CD

:::T

(.)

(')

0

(I)

1

3

sa.
(:r
c

(3t
(8)

+Vs 0

,

,

,

FOUT ,

, ,

•

,

iii"

ce

a3

~::r

043

CD

o

::l

ffl

3
0'
o

(2)

Rs 0

,

r::s
':'

S.
c
g,

-Vs

o

~

~

~
iii

ig.

10K
(4)
Gnd

.?

~

§
~
N

2:J

~

000

65-1516

~

Cl
~
~

01

N

RC4153
RC4153
Voltage-to-Frequency Converter

Description

Features

The 4153 sets a new standard for ease of application
and high frequency performance in monolithic voltageto-frequency converters. This voltage-to-frequency
converter requires only four passive external
components for precision operation, making it ideal for
many low cost applications such as AID conversion,
frequency-to-voltage conversion, and serial data
transmission. The improved linearity at high frequency
makes it comparable to many dual slop AID converters
both in conversion time and accuracy, while retaining
the benefits of voltage-to-frequency conversion, Le.,
serial output, cost and size. The speed accuracy and
temperature performance of the 4153 is achieved by
incorporating high speed ECl logic, a high gain, wide
bandwidth op amp, and a buried Zener reference on a
single monolithic chip.

•
•
•
•

0.1 Hz to 250 kHz dynamic range
0.01% F.S. maximum nonlinearity error - 0.1Hz to
10kHz
50 ppml"C maximum gain temperature coefficient
(external reference)
Few external components required

Applications
•
•
•
•
•
•
•
•
•
•

Precision voltage-to-frequency converters
Serial transmission of analog information
Pulse width modulators
Frequency-to-voltage converters
AID converters and long term integrators
Signal isolation
FSK modulation/demodulation
Frequency scaling
Motor speed controls
Phase lock loop stabilization

I
For More Information, call 1-800-722·7074.

Raytheon Semiconductor

3-809

RC4153
Absolute Maximum Ratings(1)
Supply Voltage .......................................................±18V
Intemal Power Dissipation ................................. 500 mW
Input Voltage ................................................. -VS to +VS
Output Sink Current
(Frequency Output) ........................................... 20 mA
Storage Temperature Range ................ -65"C to +150°C
Operating Temperature Range
RM4153 ............................................ -55°C to +125"C
RC4153 .................................................. 0°C to +70"C
Note:
1. ·Absolute maximum ratings· are those beyond which the
safety of the device cannot be guaranteed. They are not meant
to imply that the device should be operated at these limits. "
the device is subjected to the limits in the absolute maximum
ratings for extended periods, its reliability may be impaired.
The lables of Electrical Characteristics provide conditions for
actual device operation.

Ordering Information
Part Number

Package

RC4153D
RM4153D

D
D

Operating
Temperature
Range
-55"C to +125"C

Notes:
0= 14-lead ceramic DIP

Connection Information

Thermal Characteristics
14-Lead
Ceramic
DIP
Max. Junction Temp.

+175OC

Max. Po TA <50'C

1042mW

Thenn. Res 9JC

600 C/W

Thenn. Res. 9JA

1200CNI

For TA >50'C Derate at

115-1823

8.33 mWf'C

Pin
1
2
3
4
5
6
7

3-810

Function
-VS
REFGnd
VREFOUtput
VOUT (Op Amp)
l,N (REF Input)
Co (Pulse Width)
Trigger Input

Raytheon Semiconductor

Pin Function
8 Circutt Gnd
9 Frequency Output
(Open Collector)
10 +VS
11 (+) Op Amp Input
12 (-) Op Amp Input
13 VOS Trim
14 VOSTrim

For More Information, call 1-800-722-7074.

RC4153
Electrical Characteristics
(Vs = ±15V and TA = +25"C unless otherwise noted)
Parameters
Power Supply Requirements
Supply Voltage
Supply Current (+VS. touT = 0)
(-VS. lOUT =0)
Full Scale Frequency
Transfer Characteristics
Nonlinearity Error Voltage-ro-Frequency1
0.1 Hz ~ FOUT S 10 kHz
1.0 Hz ~ FOUT S 100 kHz
5.0 Hz ~ FOUT S 250 kHz
Nonlinearity Error Frequency-to-Voltage1
0.1 Hz ~ FIN ~ 10 kHz
1.0 Hz ~ FIN ~ 100 kHz
5.0 Hz ~ FIN ~ 250 kHz
Scale Factor Tolerance. F = 10 kHz
K=

Min

Typ

Max

Units

±12

±15
+4.2
-7
500

±18
+7.5
-10

V
rnA

0.002
0.025
O.OS

0.01
0.05
0.1

%FS
%FS
%FS

0.002
0.05
0.07

0.01
0.1
0.12

%FS
%FS
%FS

250

1
2VREFRIN CO

Change of Scale Factor with Supply
Reference Voltage (VREF)
Temperature Stability (O°C to 70"C) 1.2, 3
Scale Factor 10KHz Nominal
Reference Voltage
Scale Factor (External Ref) 10 KHz FS
Scale Factor (External Ref) 100 KHz FS
Scale Factor (External Ref) 250 KHz FS

kHz

:to.5

%

0.008
7.3

%/V
V

±75
:1:50
f25
:1:50
±100

±150
±100
:1:50
±100
±150

ppm/"C
ppm/DC
ppmf'C
ppm/DC
ppm/DC

Notes:
1. Guaranteed but not tested.
2. VREF Range: S.SV ~ VREF ~ a.ov.
3. Over the specified operating temperature range.

For More Infonnation. call 1-800-722-7074.

Raytheon Semiconductor

3-811

I

RC4153
Electrical Characteristics (Continued)
Parameters
OpAmp
Open Loop Output Resistance
Short Circuit Current
Gain Bandwidth Product 1
Slew Rate
Output Voltage Swing (RL ~ 21<)
Input Bias Current
Input Offset Voltage (Adjustable to 0)
Input Offset Current
Input Resistance (Differential Mode)
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Switched Current Source
Reference Current (External Reference)
Digital Input (Frequency-to-Voltage, Pin 7)
Logic ·0"
Logic "1"
Trigger Current
Logic Output (Open Collector)
Saturation Voltage (Pin 9)
ISINK =4 rnA
ISINK =10 rnA
ILEAK (Off State)

Min

2.5
0.5
Oto+10

75
70
25

Typ

230
25
3.0
2.0
-0.5 to +14.3
70
0.5
30
1.0
100
106
350

Max

400
5.0
60

1.0

n
rnA
MHz
VljJS
V
nA
mV
nA
Mn
dB
dB
VlmV

rnA

0.5
2.0
-50

0.15
0.4
150

Units

V
V
~

0.4
1.0

V
V
nA

Notes:
1. Guaranteed but not tested.

3-812

Raytheon Semiconductor

For More Information, call HIOO-722-7074.

RC41 53
Typical Performance Characteristics
10kHz Full Scale Drift
Output Frequency vs. Temperalure

250 kHz Full Scale Drift
Output Frequency vs. Temperature

10.06

250.S

- -- --

10.03
'N'

!.

10

~

9.97

~

~

....-

~
~

25D.4

f--

.,

'N' 250.0

!.

V
./

~

~ 249.6

./

249.2

9.94

-

........

,/

10

~

9.91
.sO -40 -20

0

248.S
.sO -40 -20

+20 +40 +60 +SO +1 00+120

0

"

+20 +40 +60 +80 +1 00+ 120

T.dOC)

360 kHz Voltage-Io-Frequency
Nonlinearity vs. Input Voltage

'C'

g

250 kHz Voltage-Io-Frequency
Nonlinearity vs. Input Vollage

O.OS

0.09

0.04

0.06

gw

0

w
~ -0.04
...I

z

'" "'-

'/
r.......

V

~

-0.03

-0.12

-0.06

2

3

4

6

5

"-

~

Z

-O.OS

o

'~ r-....

/

0

...I

.-'

/

0.03

......

/' "

7

S

9

10

~

o

~
25

50 75 100 125 150 175 200225 250

VIN (V)

FIN

(kHz)

I

250 KHz Full Scale Peak
Nonlinearily VS. Scale Factor
0.10
'C'

e

w
~

~

a
D

O.OS

I

0.06

/

0.04

~

...I

z

V

~

0.02
0

o

-

~

30

'{/

60

V

0

I

F-IO-~ "........

.;'

v -'

i'

k~
V-Io-F

-

120 150 1S0 210 240 270
K (kHz)

For More Information. call HIOQ-722-7074.

Raytheon Semiconductor

3-813

RC4153
Typical Performance Characteristics (Continued)
10KHz Vonage-to-Frequency
Nonlinearny vs. Input Vonage

10KHz Vonage-to-Frequency
Nonlinearny vs. Input Frequency
0.004

0.004
0.002

0.002
'C'

0

'C'

e

.........

~
~..(l.002

g

w
~

-

,,- ~ r-

........ r-.

..I

z

3

4

5

6

7

8

9

-0.006

10

on

;;;

~

o

2

3

4

VIN (V)

0.008

0.05

0.004

..... V

'C'
............

~-0.005

6

7

8

9

10

50 KHz Vonage-to-Frequency
Nonlinearny vs. Input Frequency

0.01

0

5

FIN (kHz)

50 KHz Vonage-to-Frequency
Nonlinearity vs. Input Voltage

Iw

.........

-0.004

~
2

r- i"--

~

z -0.002

~

o

v

..I

-0.004
-0.006

f......-

0

r---.. ........

l,.....--" V

~

V

0

V

-

./

.........

'" ~ ......

~..(l004
•

..I

..I

z

Z

-0.01

on

..(l.008

-0.015

~

-0.012

Ii!

o

2

3

4

5

6

7

8

9

10

~

~

o

5

10 15 20

25
FIN

0.04

0.04

0.02

g

0.02
'C'

0

............
w
~ -0.02

r---..

..I

z

/
,,-- .....

r-

e

V

~

~
2

3

4

5

6

7

8

0

L

V

..-

r--.....

I-'

i'-.

"-

~

9

10

-0.04
-0.06

o

VIN (V)

3-814

/'

~ -0.02
z

~

o

(kHz)

..I

-0.04
..(l.06

40 45 50

100 KHz Voltage-to-Frequency
Nonlineartty vs. Input Frequency

100 KHz Vonage-to-Frequency
Nonlinearity vs. Input Vonage

'C'

30 35

10

20 30

40 50
FIN

Raytheon Semiconductor

60 70

80 90 100

(kHz)

For More Infonnation. call H!()()-722-7074.

RC4153
Typical Application Circuits
RIN

VINcr~~V-~~--~----------------------------------------'

Full Scale
10kHz
50kHz
100 kHz
250 kHz

4153

1000 pF

130 pF

20K
20K
20K
20K

2
VREF
7.3V

___ J

One
Shot

7

F OUT= 2V REF R IN Co

T =
•• For Bipolar Input

(V REF= 7.3V)

t

F

VIN RREF + VREF RIN
OUT= 2RINRsVREFCO

• ±V smust be thoroughly decoupled.
.. For bipolar input.
Resistance in Ohms unless otherwise specified.

FOUT

=1.5xl0·Co

5x 10·'
Co:!:: Four{Max)
65-1825

Figure 1. Voltage-to-Frequency Converter Minimum Circuit
Full Scale Adjust

Voflago
Oulput

Full Scale

Co

10kHz

50kHz
100 kHz
250 kHz
VRIPPlE

=

Co

Co

II'F

3300 pF
3lOpF
150pF

0.2lf'

60pF

10 ""
21'F

R.
20K
40K
43K
39K

I

2VflEFCO(1 ·1.5 x 1Q4CoF,d

Co
T rt;COVERY. 1.36 x 10 4CI CoRa UIN

+Vs·
~:::""'----lo-o F"","

Rl
10K

(O.l~NkHz) o-!I-+---=-..,.....
eN

o.o02pF

R2
S.lK
Vour .2VREF RB Co FIN

C

~~
o
FIN (Max)

• ±V s mllSt be 1horoughly decoupled.
•• Optional.
Resistance in Ohms unless otherwise specified.

65-1826

Figure 2. Frequency-to-Voltage Converter
For More Information, call H!OO-722-7074.

Raytheon Semiconductor

3-815

RC4153
Typical Application Circuits

(Continued)

Full Scale
Adjust

v.,
~ml0~ O-~~~~~------------------------------------------~
Full Scale

I

10kHz
50kHz
100kHz
250 kHz

RIN

CI

-Va

CI
O.lfLF
0.02 F

oF
1000pF

Co
3300 F
680 F
330
130pF

RIN
20K
20K
20K
20K

0.011'F
(Mylar)

1f

Co

Frequency
OUlpu!

VIN
FOUT • 2VREF RIN Co
CO:S;;

5x 10"
FOUT(Max)

• ±Vs must be lhoroughly decoupled.
Resistance in Ohms unless otherwise specified.

65-1828

Figure 3. VoHage-to-Frequency Converter with Offset and Gain Adjusts

3-816

Raytheon Semiconductor

For More Information, caJI1-800-722-7074.

RC4153
Principles of Operation

because the amount of charge in each lOUT pulse is
carefully defined, both in magnitude and duration. The
duration of the pulse is set by the timing capacitor Co
(point 0). This feedback system is called a chargebalanced loop.

The 4153 consists of several functional blocks which
provide either voltage-to-frequency or frequency-tovoltage conversion, depending on how they are
connected. The operation is best understood by
examining the block diagram as it is powered in a
voltage-to-frequency mode (Figure 4).

The scale factor K (the number of pulses per second for
a specified VIN), is adjusted by changing either RIN and
therefore liN, or by changing the amount of charge In
each lOUT pulse. Since the magnitude of lOUT Is fixed at
1 milliamp, the way to change the amount of charge is
by adjusting the one-shot duration set by
(lOUT may
be adjusted by changing VREF.) The accuracy of the
relationship between VIN and FOUT Is affected by three
major sources of error: temperature drift, nonlinearity
and offset

When power is first applied, all capacitors are
discharged. The input current, VINIRIN, causes CI to
charge, and point C will try to ramp down. The trigger
threshold of the one-shot is approximately +1.3V, and if
the integrator output is less than +1.3V, the one-shot will
fire and pulse the open collector output E and the
switched current source A (see Figures 4 and 5).
Because the point C is less than +1.3V, the one-shot
fires, and the switched current source delivers a
negative current pulse to the integrator. This causes CIN
to charge in the opposite direction, and point C will ramp
up until the end of the one-shot pulse. At that time, the
positive current VINIRIN will again make point Cramp
down until the trigger threshold is reached.
When power is applied, the one-shot will continuously
fire until the integrator output exceeds the trigger
threshold. Once this is reached, the one-shot will fire as
needed to keep the integrator output above the trigger
threshold. If VIN is increased, the slope of the downward
ramp increases, and the one-shot will fire more often in
order to keep the integrator output high. Since the oneshot firing frequency is the same as the open collector
output frequency, any increase in VIN will cause an
increase in FOUT. This relationship is very linear
Integrator

fr----------~I----------~,

eo.

The total temperature drift is the sum of the individual
drift of the components that make up the system. The
greatest source of drift in a typical application is In the
timing capacitor, Co. Low temperature coefficient
capacitors, such as silver mica and polystyrene, should
be measured for drift, using a capacitance meter.
Experimentation has shown that the lowest tempco's are
achieved by wiring a parallel capacitor composed of
70% silver mica and 30% polystyrene.

I

Y,N
+5V _ _ _.......

.I~ lnnJU1Ilfl
B

...----1 t------t--{) C

c
VIN o---'Wv--1---t

o to 10V
o
Voltage
Reference
7.3V

Switched

Current
Source
L -_ _ _..I

E

B
Co
(Timing)

,......... ,.........
I '-J ",-/VVV,
A

A

A.

..

IT'N'rr

·1.0mA
SWitched Current Source
Logic (Internal)

Integrator OUtput
VTRlGGER=+l.3V

..o.65V
One Shot Timing (Co)
T _1.5 x 10'Co
-4.1V

Inn nnnn :~OUtput

u u uuUUI =

O.2V

Fo=

r

---.l!..!!L.-

2VREFR,N C O

65-1818

Figure 4. Vottage-to-Frequency Block Diagram
For More Information. call 1-800-722-7074.

rLILJlflJlJlJ

SWitched current
Source OUtput

65-1817

Figure 5. Vofiage-to-Frequency Timing Waveforms

Raytheon Semiconductor

3-817

I

RC4153
The reference on the chip can be replaced by an
external reference with much tighter drift specifications,
such as an LM199. The 199'5 6.9V output is close to the
4153's 7.3Voutput, and has less than 10 ppl'l'lfOC drift.
Nonlinearity is primarily caused by changes in the
precise amount of charge in each lOUT pulse. As
frequency increases, internal stray capacitances and
switching problems change the width and amplitude of
the lOUT pulses, causing a nonlinear relationship
between VIN and FOUT. For this reason, the scale factor
you choose should be below 1 KHzIV or as low as the
acquisition time of your system will allow.
Nonlinearity is also affected by the ratiO of CI to CO.
Less error can be achieved by increasing the value of
CI, but this affects response time and temperature drift.
Optimum values for CI and Co are shown in the tables
in Figures 1, 2, and 3. These values represent the best
compromise of nonlinearity and temperature drift.
Polypropylene, mylar or polystyrene capacitors should
be used for CI.
The accuracy at low input voltages is limited by the
offset and Vas drift of the op amp. To improve this
condition, an offset adjust is provided.
Once your system is running, it may be calibrated as
follows: apply a measured full scale input voltage and
adjust RIN until the scale factor is correct. For precise
applications, trimming by soldering metal film resistors in
parallel is recommended instead of trimpots, which have
bad tempcos and are easily taken out of adjustment by
mechanical shock. After the scale factor is calibrated,
apply a known small input voltage (approximately 10
mV) and adjust the op amp offset until the output
frequency equals the input multiplied by the scale factor.
The output E consists of a series of negative going
pulses with a pulse width equal to the one-shot time.
The open collector pull-up resistor may be connected to

3-818

a different supply (such as 5V for ffi) as long as it
does not exceed the value of +Vs applied to pin 10.
The load current should be kept below 10 mA in order
to minimize strain on the device. Pins 2 and 8 must be
grounded in all applications, even if the open collector
transistor is not used.
Figure 6 shows the complete circuit for a preciSion
frequency-to-voltage converter. This circuit converts an
input frequency to a proportional voltage by integrating
the switched current source output. As the input
frequency increases, the number of lOUT pulses
delivered to the integrator increases, thus increasing
the average output voltage. Depending on the time
constant of the integrator, there will be some ripple on
the output. The output may be further filtered, but this
will reduce the response time. A second order filter will
decrease ripple and improve response time.
The input waveform must meet three conditions for
proper frequency-to-voltage operation. First, it must
have sufficient amplitude and offset to swing above and
below the 1.3V trigger threshold (See Figure 6 for an
example of AC coupling and offset bias.) Second, it
must be a fast slewing waveform having a quick rise
time. A comparator may be used to square it up.
Finally, the input pulse width must not exceed the oneshot time, in order to avoid retriggering the one-shot
(AC couple the input).
Capacitive coupling between the trigger input and the
timing capacitor pin may occur if the input waveform is
a squarewave or the input has a short period. This can
cause gross nonlinearity due to changes in the oneshot timing waveform (See Figure 7). This problem can
be avoided by keeping the value of Co small, and
thereby keeping the timing period less than the input
waveform period.

Raytheon Semiconductor

For More Infoonation, calI1.aoo-722-7074.

RC4153
-15V

-Vs

+15V

+Vs

VOS2

VOUT+

4

VOUT

RI
Vos1

4153

-In

Trig
VREF

CI

12

+In

11

liN

RI

Comparator with

Hysteresis

Input
Coupling

65-1814

Figure 6. Frequency-lo-Voltage Precision Converter

Proper
Operation

Timing

1

Waveform
on

Co

Input
Frequency

Input
Frequency

I

Improper
Operation
Timing
Waveform
On Co
Gitch
65-1812

Figure 7. Frequency-lo-Voltage Timing Waveforms

For More Information, call HIOO-722-7074.

Raytheon Semiconductor

3-819

RC4153
Detailed Circuit Operation
The circuit consists of a buried zener reference
(breakdown occurs below the surface of the die,
reducing noise and contamination), a high speed oneshot, a high speed switched precision voltage-to-current
converter and an open-collector output transistor.
Figure 8 shows a block diagram of the high speed oneshot and Figure 9 shows the monolithic implementation.
A trigger pulse sets the R-S latch, which lets Co charge
from IT. When the voltage on Co exceeds VTH, the
comparator resets the latch and discharges Co. looking
at the detailed schematic, a positive trigger voltage turns
on 05, turns off 04, and turns on 03. 03 provides more
drive to
keeping it on and latching the base of 011
low. This turns on the switched current source and turns
off 01, allowing Co to charge in a negative direction.
When the voltage on Co exceeds VTH, 013's collector
pulls 03's base down, resetting the latch, turning off the
switched current source and discharging Co through
01. Note that all of the transistors in the signal path are
NPNs, and that the voltage swings are minimized ECl
fashion to reduce delays. Minimum delay means
minimum drift of the resultant VFC scale factor at high
frequency.

To Switched
Current Source

C

o.-o-;.--tc::;)1

Trig

Reset

as

R-S Latch

Comparator
6!,.,819

Figure 8. One-Shot Block Diagram

Trigger

..---oC

~-----~---+-4-~-~~---1~-~~---+---~----O~s

Ramp Generator

Comparator

R-S Latch
65-1827

Figure 9. One-Shot (Detail)
3-820

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4153
The switched current source is shown as a block
diagram in Figure 10 and detailed in Figure 11. The
summing node (+ input of the op amp) is held at OV by
the amplifier feedback. causing VREF to be applied
across R60. This current (VREPR60). minus the small
amplifier bias current. flows through 035. 035 develops
a VBE dependent on that current. This VBE is developed
across 036. Since 035 and 036 are equal in area. their
currents are equal. This mirrored current is switched by
the one-shot output.
The detail schematic shows the amplifier and load (021
through 034). the mirror transistors (035. 036) and the
differential switching transistors (07. 08). The amplifier
uses a complementary paraphase input composed of
021 through 026 with a current mirror formed by 027
through 030. which converts from differential to singleended output. Level-shift diodes 032 and 034 and
emitter follower 031 bootstrap the emitters of the mirror
devices 029 and 030 to increase gain and lower input
offsets. which would otherwise be caused by
unbalanced collector voltages on 023 and 026.
Matching emitter currents in 035 and 036 are assured
by degeneration resistors R3 and R4. The differential
switch allows the current source to remain active

continuously. shunting to ground in the off state. This
helps stabilize the output and again. NPNs reduce
switching time. timing errors. and most important. drift of
timing errors over temperature.
V REF

+7.3V

RGO

I
A

Switched
Current

Source
Output

From
----- B One Shot

vs

L..------4I------+----Q-

65-1822

Figure 10. SwHched Current Source Block Diagram
VREF

To
Collector

01011

ToBias
Network

Rl
3.47kn

R43
56.2kn

R3

3.92 kn

~so-----~~----~----------~------~--~~--~

R4

3.92 kn

65·1824

Figure 11. Switched Current Source (Detail)
For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-821

I

(,)

ch

I\)
I\)

+v. 0.-,.--,

Ves,

VCIt

{Olfael
Ad;IsI

Vorr-r-f-Trig.J c.-io -In

Co~

Forr1.J1j

1\

PulseOulput

~:r
g
~

fC

3

g'
~

Q,

c

.

g,

o

~

~

ig.
?

~

i~
~

~

-VIC

III

I I

Notes: All resistor values are in KG
~=Aluminum

Trig

65-6268

RV4140
RV4140
Low Power 1\vo-Wire Ground Fault Interrupter Controller
Description

Features

The RV4140 is a low power controller for AC outlet
appliance leakage circuit interrupters. These devices
detect hazardous current paths to ground such as an
appliance falling into water. The interrupter then open
circuits the fine before a harmful or lethal shock occurs.

•
•
•
•
•
•
•
•
•
•

Intemally. the RV4140 has a diode bridge rectifier. zener
shunt regulator. op amp. current reference. time delay
circuit. latch and SCR driver.
An external sense transformer. SCR. relay. two resistors
and three capacitors complete the design of the circuit
interrupter. The simple layout and minimum component
count ensure ease of application and long term
reliability.

Powered from the AC line
Built-in bridge rectifier
Direct interface to SCR
350 J.IA quiescent current
Adjustable trip current
Adjustable time delay
Minimum extemal components
Meets UL 943 requirements
Specifically for two-wire systems
For use with 11 OV or 220V systems

I
For More Informalion, call H1ClO-722-7074.

Raytheon Semiconductor

3-823

RV4140
Absolute Maximum Ratings
Supply Current .............................................. 7 mA
Internal Power Dissipation ....................... 500 mW
Storage Temperature Range ....... -65°C to +150°C
Operating Temperature Range ..... -35°C to +80°C
Lead Soldering Temperature
(DIP, 60 sec.) .........................................+300°C
(SO, 10 sec.) .........................................+260°C

Thermal Characteristics
8 Lead

8 Lead
I

Max. PD TA <50°C

300mW

468mW

240°CIW

160°C/W

Therm. Res 9JO
Therm. Res. 9JA

For TA >50°C Derate at 4.1 mWI"C

6.25mWI"C

Ordering Information

Connection Information
B-Lead Plastic
Dual In-LIne So-a
(Top View)

Part Number
RV4140N
RV4140M

Package
N
M

Operating
Temperature
Range
-35°C to +80°C
-35°C to +80°C

Notes:
N • 8-lead plastic DIP
M - 8-lead plastic sale

8-Lead Plastic
Dlalln-Une Package
(Top View)

o

8II-GOII3

Pin Function

1

RsEl

2

VFB

3

Common (+2.5V)
Ground

4
5

6
7
8
3-824

Una

Neutral
SCR Trigger
C Delay

Raytheon Semiconductor

For MonIlnbmatiDn. call 1-800-722-7074.

RV4140
Electrical Characteristics
I line = 1.2 mA, TA = 25"C, RSET = 290 kn
Min

Typ

Max

Un"s

I line .. 700 ~, 12-3 - 9 ~

6.8
6.8

7.2
7.2

7.6
7.6

Volts
Volts

Design Value

-3.0

0
2.0
30

3.0
100

mV
MHz
nA

0
1.4
300

4.7
0.1
2.0
420

5.4
10
2.6
600

mV
Volts

2.6

2.9

3.2

Volts

-

2.0
29

-

ms

35

~

Parameters
Shunt Regulator (pins 5 to 6)
Regulated Voltage
Regulated Voltage
Sense Amplifier (pins 2 to 3)

Test Conditions

Offset Voltage
Gain Bandwidth
Input Bias Current
SCR Trigger (pins 7 to 6)
Output Resistance
Output Voltage
Output Voltage
Output Current
Reference VoHage (Pins 3 to 4)
Reference Voltage
Delay Timer (pins 8 to 4)
Delay Time (1)
Delay Current

12-3 .. 11

~

Design Value
Design Value
V5-6 = open, 12-3 = 0 ~
12-3 = 9 ~
12-3= 11 ~
V7-6 = OV,12-3 = 11
Iline=700~

C8-4=20 nF
12-3= 11

~

~

4.0

23

k.Q

~

Notes:
1. Delay time is defined as starting when the instantaneous sense current (12-3) exceeds 2.9VIRsET and ending when the SCR Trigger voltage
V7-6 goes high.

Functional Block Diagram

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-825

RV4140
Principles of Operation

Supply Current Requirements

(Refer to Block Diagram and Rgure 1)
The shunt regulator generated by a 6.5V zener diode is
built into the internal bridge rectifier. It is divided to
create an internal reference voltage of 2.9V connected
to pin 3. The secondary of the sense transformer is AC
coupled to the inverting input of the sense amplifier at
pin 2; the non-inverting input is referenced to pin 3. A
current feedback loop around the sense amplifier
ensures a virtual ground will be presented to the
secondary of the sense transformer. In this manner it
acts as a current transformer instead of a voltage
transformer. In this mode, the transformer's
characteristics are very predictable and circuit
adjustments are not necessary in production.
The sense transformer has a toroidal core made of
laminated steel rings or solid ferrite material. The
secondary of the transformer is 500 to 1000 turns of #40
wire wound through the toroid. The primary is one turn
made by passing the AC hot and neutral wires through
the center of the toroid. When a ground fault exists, a
difference exists between the current flowing in hot and
neutral wires. The difference primary current, divided by
the number of secondary turns, flows through the
secondary wire of the transformer.
The AC coupled transformer secondary current then
flows through the sense amplifier's feedback loop,
creating a full wave rectified version of the secondary
fault current. This current passes through RSET at pin 1,
generating a voltage equal to RSET times the peak fault
current divided by the sense transformer turns ratio.
This voltage is compared with the reference voltage at
pin 3.
If the voltage at pin 1 is greater than pin 3, a comparator
will charge C2 through a 29 !lA current source at pin 8. If
the voltage at pin 1 exceeds pin 3 for longer than the
delay time, a 400 !lA current will pulse between pins 7
and 6 which will trigger the gate of the SCR.
If the voltage at pin 1 exceeds pin 3 for less than the
delay time, the SCR will not trigger.
The fault current at which the controller triggers the SCR
is dependent on the value of RSET and the time delay
determined by C2.
UL 943 requires the circuit interrupter trip when the
ground fault exceeds 6 mA and not trip when the fault
current is less than 4 mA.

3-826

The RV4140 has a built-in diode bridge rectifier that
provides power to the chip independent of the polarity of
the AC line. This eliminates the external rectifier required
for previous GFCI controllers.
RUNE limits the shunt regulator current to 2 mA. The
recommended value is 47K to 91 K for 11 OV systems and
91 K to 150K for 220V systems. The recommended
maximum peak line current through RUNE is 7 mAo
DO NOT connect a filter capacitor between pins 5 and 6 in
an attempt to filter the supply voltage at the RV4140.
Proper operation of the RV4140 requires the internal
supply voltage to be unfiltered.

SCR Driver
The SCR must have a high dV/dt rating to ensure that line
noise (generated by electrically noisy appliances) does not
falsely trigger the SCR. Also, the SCR must have a gate
drive requirement less than 200 !lAo C3 is a noise filter that
prevents high frequency line pulses from triggering the
SCR.
The relay solenoid used should have a 3 ms or less
response time to meet the UL 943 timing requirement.

Supplier of Sense Transformers and
Cores
Magnetic Metals Corporation, Camden, NJ 08101, (609)
964-7842, supplies a full line of ring cores and
transformers designed specifically for GFCI and related
applications.

Determining the Values of RSET and
C2
Determine the ground fault trip current requirement. This
will be typically 5 mA in North America (117 VAC) and 10
mA in the UK and Europe.
Determine the minimum amount of time delay required to
prevent nuisance tripping. This will typically be 1 to 2 ms.
The value of C2 required to provide the desired delay time
is:
C2=10xT
where:

Raytheon Semiconductor

For More Information, call1.aoo-722-7074.

RV4140
C2 is in nF

IFAULT is the desired ground fault trip current in mA
RMS
N is the number of sense transformer secondary turns.

T Is the desired delay time In ms.
The value of RSET to meet nominal ground fault trip
current specification is: 2.05 x N
IFAULTX COS 180 (TIP)

This formula assumes an ideal sense transformer is
used. The calculated value of RSET may have to be
changed up to 30% when using a non-ideal transformer.

RSET=

Where:
RsET is in kn
T is the time delay In ms
P is the period of the line frequency in ms

Mov
Una

Sensa Transformer
1:500 Turns Rallo
3 Ring Staal Cora

RTEST

Press to Test

15K

...J::::l-

o-----------------~
Normally

Closed

latching

Contacts

O~~~_1~~~--~H~m~-----------------------;~~:::f:::::::::::g~~
Nautral
C2
O.02I1F

Sollnold 0-----....____-,

C1
10l1F

RUNE
91K

Figure 1. Appliance Leakage Detector Circuit Application

For Mor8 InfcrmatiOn, calI1.aoo-722-7074.

Raytheon Semiconductor

3-827

~

§~

~

e
g.~
~
2

c!

~

-!i

v.. 0

,

j

t'C

una

(2)

(5)

N.-.

o

:J

ffl :::'0.(' J 1
3

I

Vee

I

l..~.

Il

~

I t(Q24 I t(Q26 IK032 I K I~

) (8)

RIO

4.71<

SCR
(7)

g

Cap
(8)

:J

a.
c

§

AS
23K

G('4)ndO

I -1 1 I I

r

I

1

I

RaeroO---_~

~

f

f
~.

~

~

i

~

?:f

~

(1)

1 I

11 1 1 1 1 1
Sub

11 I
.......

RV4141

RV4141
Low Power Ground Fault Interrupter
Description

Features

The RV4141 is a low power controller for AC receptacle
ground fault circuit interrupters. These devices detect
hazardous current paths to ground and ground to
neutral faults. The circuit interrupter then disconnects
the load from the line before a harmful or lethal shock
occurs.

•
•
•
•
•
•
•
•
•
•

Intemally, the RV4141 contains a diode rectifier, shunt
regulator, precision sense amplifier, current reference,
time delay circuit, and SCR driver.

Powered from the AC line
Built-in rectifier
Direct interface to SCR
500 J.LA quiescent current
Precision sense amplifier
Adjustable time delay
Minimum external components
Meets UL 943 requirements
For use with 110V or 220V systems
Available in 8 pin DIP or SOIC package

Two sense transformers, SCR, solenoid, three resistors
and four capacitors complete the design of the basic
circuit interrupter. The simple layout and minimum
component count insure ease of application and long
term reliability.
Features not found in other GFCI controllers include a
low offset voltage sense amplifier eliminating the need
for a coupling capaCitor between the sense transformer
and sense amplifier, and an internal rectifier to eliminate
high voltage rectifying diodes.
The RV4141 is powered only during the positive half
period of the line voltage, but can sense current faults
independent of its phase relative to the line voltage. The
gate of the SCR is driven only during the positive half
cycle of the line voltage.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-829

RV4141
Absolute Maximum Ratings

Ordering Information

Supply Current ......................................... 10 rnA
Internal Power Dissipation •..•.•..•.•.•.•..•.• 500 mW
Storage Temperature
Range ................................. -65°C to +150°C
Operating Temperature
Range ................................... -35°C to +80°C
Lead Soldering Temperature
(60 Sec.• DIP) ...•.....•......•......•........... +300°C
(10 Sec.• SO) ..•............••........•.•....•.•. +260°C

Connection Information

Pan Number

Package

Operating
Temperature
Range

N
M

-35°Cto+80°C
·35°Cto +80°C

RV4141N
RV4141M
Notes:
N - 8-lead plastic DIP
M _ 8-lead plastic SOlO

Thermal Characteristics

Max. Junction Temp.

8-Lead
Plastic
SOIC
+125°C

S·Lead
Plastic
DIP
+125°C

Max. PDTA<50°C

300mW

468mW

Therm. Res. 9JA

240°C/W

160°C/W

ForTA >50°C
Derate at

4.1 mW
peroC

6.25mW
peroC

S-Lead Plastic
Dual In-Line SO-S
(Top View)

Therm. Res 9JC
65-02666

8·Lead Plastic
Dlalln·Llne Package
(Top View)
0

3-830

Pin

Function

1

Amp Out

2

VFB

3

VREF (+13V)

4

5

Ground
Line

6

+Vs

7
8

SCR Trigger
Delay Cap

Raytheon Semiconductor

For More Information, call HlOO-722-7074.

RV4141
r-----------~--~~--------I

I
I
I
I

~
15K

~
Test

Grounded Neutral
1:200

Normally Closed
Latching Contacts

Phase

I
I
I
I

Uneo---,~~_ _-t\:---J '/-----:N-:-e-ut-ral-:----\t~::j ~--r-----~-o-i..:;:---t-t---,4Load

I
I
I
I

Solenoid

1000 pF

I ...

IIRN
11 0•4

II

I
T~~
III
I
RSET
X01 03DA
~~It II
I
C3
1W II
I
6
10 nF
II
I
5 1JlF35V
II
I~F~ _ _ _ _ _ _ _
4
1N4004
Il_______________ J
Note:
Ponions of this schematic are subject to
U.S. patents 3,878,435 and Re. 30,678

I
I
I
t-~-' I
I
RG
I
Rs
20K

1.6

Fault
Resistance
Not Pall of

I
I
I
I
I

~~c~i~J

65-5109

Figure 1. GFI Application Circuit

I
For More Information, call 1-000-722·7074.

Raytheon Semiconductor

3·831

RV4141
Electrical Characteristics
(IUNE = 1.5 mA and TA = +25°C. RSET = 650 kn)
Parameters
Shunt Regulator (Pins 5 to 4)
Regulated Voltage
Regulated Voltage
Quiescent Current
Sense Amplifier (Pins 2 to 3)
Offset Voltage
Gain Bandwidth
Input Bias Current
SCR Trigger (Pins 7 to 4)
Output Resistance
Output Voltage
Output Voltage
Output Current
Reference Voltage (Pins 3 to 4)
Reference Voltage
Delay Timer (Pins 8 to 4)
Delay Time (Note 1)
Delay Current

Test Conditions

Min

Typ

Max

Units

12-3 = 11 JJA

25.0
25.0

27.0
27.0
500

29.0
29.0

Volts
Volts

-

JJA

0
1.5
30

200

-

J.l.V
MHz

100

nA

IUNE =750 JJA. 12-3 = 9 JJA
V5-4 = 24V

200

(Design Value)
(Design Value)

-

V7~ = Open. 12-3 = 0 JJA
12-3 = 9 JJA
12-3 = 11 JJA
V7~ = OV. 12-3 = 11 JJA

4.0
0
2.4
400

4.7
0.1
3.0
600

5.4
10
3.6
800

kn
mV
Volts

IUNE = 750 JJA

12.0

13.0

14.0

Volts

C8 -4 = 12 nF

-

ms

30

2.0
40

-

~-3=11JJA

50

JJA

JJA

Note:
1. Delay time Is defined as starting when the instantaneous sense current (Ia-J exceeds 6.5 VIRSET and ending when the seR
trigger voltage V74 goes high.

Functional Block Diagram
Amp 1
Out

1------.....,

RV4141

86-6108

3-832

Raytheon Semiconductor

For Mont 1nfoonaIion. c3I HIOO·722·7074.

RV4141
Circuit Operation

Supply CUrrent Requirements

(Refer to Block Diagram and Figure 1)

The RV4141 Is powered directly from the line through a
series limiting resistor called RLlNE, its value Is between
24 kn and 91 kn The controller IC has a built-in diode
rectifier eliminating the need for extemal power diodes.

The precision op amp connected to Pins 1 through 3
senses the fault current flowing In the secondary of the
sense transformer, converting it to a voltage at Pin 1.
The ratio of secondary current to output voltage is
directly proportional to feedback resistor, RSET.
RsET converts the sense transformer secondary current
to a voltage at Pin 1. Due to the virtual ground created
at the sense amplifier Input by its negative feedback
loop, the sense transformer's burden Is equal to the
value of RIN. From the transformer's point of view, the
ideal value for RIN Is on This will cause it to operate as
a true current transformer with minimal error. However,
making RIN equal to zero creates a large offset voltage
at Pin 1 due to the sense amplifier's very high DC gain.
RIN should be selected as high as possible consistent
with preserving the transformer's operation as a true
current mode transformer. A typical value for RIN is
between 200 and 1000n

As seen by the equation below, maximizing RIN
minimizes the DC offset error at the sense amplifiers
output The DC offset voltage at Pin 1 contributes
directly to the trip current error. The offset voltage at Pin
1 is:
Ves x RsETI(RIN + RSEC)
Where:
Ves = Input offset voltage of sense amplifier
RSET = Feedback resistor
RIN = Input resistor
RSEC= Transformer secondary winding resistance
The sense amplifier has a specified maximum offset
voltage of 200 J1V to minimize trip current errors.
Two comparators connected to the sense amplifier
output are configured as a window detector, whose
references are -6.5 volts and +6.5 volts referred to Pin 3.
When the sense transformer secondary RMS current
exceeds 4.6/RSET the output of the window detector
starts the delay circuit If the secondary current exceeds
the predetermined trip current for longer than the delay
time a current pulse appears at Pin 7, triggering the
SCR.
The SCR anode Is directly connected to a solenoid or
relay coil. The SCR can be tripped only when its anode
is more positive than its cathode.

For More Inbmation, call 1-800-722-7074.

The recommended value for RLiNE Is 24 kn to 47 kn for
110V systems and 47 kn to 91 kn for 220V systems.
When RLiNE Is 47 kn the shunt regulator current Is
limited to 3.6 mAo The recommended maximum peak
line current through RLiNE is 10 mA.

GFCI Application
(Refer to Figure 1)
The GFCI detects a ground fault by sensing a difference
current in the line and neutral wires. The difference
current Is assumed to be a fault current creating a
potentially hazardous path from line to ground. Since the
line and neutral wires pass through the center of the
sense transformer, only the differential primary current Is
transferred to the secondary. Assuming the turns ratio Is
1:1 000 the secondary current is 1/1000th the fault
current The RV4141's sense amplifier converts the
secondary current to a voltage which Is compared with
either of the two window detector reference voltages. If
the fault current exceeds the design value for the
duration of the programmed time delay, the RV4141 will
send a current pulse to the gate of the SCR.
Detecting ground to neutral faults is more diffICult. Rs
represents a normal ground fault resistance, RN is the
wire resistance of the electrical circuit between loadl
neutral and earth ground. AG represents the ground to
neutral fault condition. According to UL 943, the GFCI
must trip when RN = 0.40., Ra = 1.60 and the normal
ground fault is 6 rnA.
Assuming the ground fault to be 5 mA, 1 rnA and 4 mA
will go through AG and RN, respectively. caUSing an
effective 1 mA fault current This current Is detected by
the sense transformer and amplified by the sense
amplifier. The ground/neutral and sense transformers
are now mutually coupled by AG, RN and the neutral
wire ground loop. producing a positive feedback loop
around the sense amplifier. The newly created feedback
loop causes the sense amplifier to oscillate at a
frequency determined by groundlneutral transformer
secondary Inductance and C4. Typically it occurs at 8
KHz.

Raytheon Semiconductor

3-833

RV4141
C2 is used to program the time required for the fault to
be present before the SCR is triggered. Refer to the
equation below for calculating the value of C2. Its typical
value is 12 nF for a 2 ms delay.
RSET is used to set the fault current at which the GFCI
trips. When used with a 1:1000 sense
transformer, its typical value is 1 MO for a GFCI
designed to trip at 5 rnA.
RIN should be the highest value possible which insures
a predictable secondary current from the sense
transformer. If RIN is set too high, normal production
variations in the transformer permeability will cause unit
to unit variations in the secondary current. If it is too low,
a large offset voltage error at Pin 1 will be present This
error voltage in tum creates a trip current error
proportional to the input offset voltage of the sense
amplifier. As an example, if RIN is 500n, RSET is 1 Mn,
RSEC is 450 and the Vos of the sense amplifier is its
maximum of 200 J.LV, the trip current error is :±5.6%.
The SCR anode is directly connected to a solenoid or
relay coil. It can be tripped only when its anode is more
positive than its cathode. It must have a high dV/dt
rating to ensure that line noise (generated by electrically
noisy appliances) does not falsely trigger it. Also the
SCR must have a gate drive requirement less than 200
JIA. C3 is a noise filter that prevents high frequency line
pulses from triggering the SCR.
The relay solenoid used should have a response time of
3 ms or less to meet the UL 943 timing requirement.

Sense Transformers and Cores
The sense and ground/neutral transformer cores are
usually fabricated using high permeability laminated
steel rings. Their single turn primary is created by
passing the line and neutral wires through the center of
its core. The secondary is usually from 200 to 1500
turns.

Calculating The Values of RSET and C2.
Determine the nominal ground fault trip current
requirement This will be typically 5 rnA in North America
(117V AC) and 22 rnA in the UK and Europe (220V AC).
Determine the minimum delay time required to prevent
nuisance tripping. This will typically be 1 to 2 ms.
The value of C2 required to provide the desired delay
time Is:
C2=6xT
where:
C2isinnF
T is the desired delay time in ms.
The value of RsET to meet the nominal ground fault trip
current specification is:
4.6xN
RsET=-------'FAULT x COS 180(T/P)
Where:
RSETisin kn
T is the time delay in ms
P Is the period of the line frequency in ms
IFAULT Is the desired ground fault trip current
in rnA RMS
N is the number of sense transformer
secondary turns.
this formula assumes an ideal sense transformer is
used. The calculated value of RSET may have to be
changed up to 30% to when using a non-ideal
transformer.

Magnetic Metals Corporation, Camden, NJ 08101 , (609)
964-7842 and Magnetics, 900 E. Butler Road, P.O. Box
391, Butler, PA 16003, (412) 282-8282 are full-line
suppliers of ring cores and transformers designed
specifically for GFCI and related applications.

3-834

Raytheon Semiconductor

For Mole Infcnnation, call1-800-n2-7074.

RV4145

RV4145
Low Power Ground Fault Interrupter
Description

Features

The RV4145Is a low power controller for AC
outlet ground fault interrupters. These devices
detect hazardous grounding conditions, such as
equipment (connected to opposite phases of the
AC line) in contact with a pool of water and open
circuits the line before a harmful or lethal shock
occurs.

•
•
•

Contained Internally are a 26V zener shunt
regulator, an op amp, and an SCR driver. With
the addition of two sense transformers, a bridge
rectifier, an SCR, a relay, .and a few additional
components, the 4145 will detect and protect
against both hot wire to ground and neutral wire
to ground faults. The simple layout and conventional design ensure ease of application and long
term reliability.

For MoI8Infcrma11on, call 1-800-7'l2-7074.

•
•
•
•
•

No potentiometer required
Direct Interface to SCR
Supply voltage derived from AC line 26Vshunt
Adjustable sensitivity
Grounded neutral fault detection
Meets U.L. 943 standards
450 p.A quiescent current
Ideal for 120V or 220V systems

Raytheon Semiconductor

3-835

RV4145
Thermal Characteristics

Absolute Maximum Ratings
Supply Ourrent ......................................... 18 rnA
Internal Power Dissipation .................... 500 mW
Storage Temperature
Range ................................. -65°0 to +150°0
Operating Temperature
Range ................................... -35°0 to +85°0
Lead Soldering Temperature
(60 Sec, DIP) ....................................+300°0
(10 Sec, SOlO) .................................+260°0

Connection Information
8-Lead Plastic
Dualln-Une S0-8
(Top View)

8-Lead

8-Lead

Plastic
SOIC

Plastic
DIP

Max. Junction Temp.

+125°C

+125°C

Max. PD TA <50°C

300mW

468mW

Therm. Res 901C
Therm. Res. 9JA
For TA >SO°C Derate at

240°CIW

160°CIW

4.1 mWrC

6.25mWf'C

Ordering Information
Pan Number
RV4145N
RV4145M

Package
N
M

Operating
Temperature
Range
-35°C to +85°C
-35°C to +85°C

Notes:
N • a·lead plastic DIP
M • a-lead plastic sOle

B-Lead Plastic
Dualln-Une Package
(Top View)

Pin
1
2
3
4
5
6
7
8
3-836

Function
VFB
+Input
VREF (+13V)
GND
SCR Trigger
+Vs(+26V)
Op Amp Output
NC

Raytheon Semiconductor

For Mora Information; calI1-800-'7l2-7074.

RV4145
Electrical Characteristics
(Is = 1.5 mA and TA = +25°C)
Parameters
Shunt Regulator
Zener Voltage (+VS>
Reference Voltage (VREF)
Quiescent Current (IS>
Operational Amplifier
Offset Voltage
+Outout Voltaee Swine
-Outout Voltaee Swine
+Outout Source Current
-Outout Sink Current
Gain Bandwidth Product
Detector Reference Voltage
Resistors
R1
R2
R3
SCR Trigger Voltage
Detector On
Detector Off

Test Conditions

Min

TvD

Max

Units

Pin 6 to Pin 4
Pin 3 to Pin 4
+Vs =24V

25
12.5

26
13
450

29.2
14.6
750

V
V
pA

Pin 2to Pin 3
Pin 7to Pin 3
Pin 7to Pin 3
Pin 7to Pin 3
Pin 7 to Pin 3
F=50kHz
Pin 7to Pin 3
Is=OmA
Pin 1 to Pin 3
Pin 2to Pin 3
Pin 5 to Pin 4
Pin 5to Pin 4

-3.0
6.8
-9.5

0.5
7.2
-11.2
650

+3.0
8.1
-13.5

mV
V
V
IIA
rnA

1.0

1.0
6.8

1.8
7.2

8.1

MHz
±V

4.0

10
10
4.7

5.4

kn
kn
kn

1.5
0

2.8
1

fa

mv

Test Conditions

Min

Typ

Max

Units

Pin 6to Pin 4
Pin3to Pin 4
+Vs=23V

24
12

26
13
500

30
15

V
V
pA

Pin 2to Pin 3
Pin 7to Pin 3
Pin 7to Pin 3
F=50kHz
Pin 7to Pin 3
Is=OmA
Pin 1 to Pin 3
Pin 2 to Pin 3
Pin 5 to Pin 4
Pin 5to Pin 4

-5.0
6.5
-9

+5.0
8.3
-14

6.5

0.5
7.2
-11.2
1.8
7.2

8.3

mV
V
V
MHz
±V

3.8

10
10
4.7

5.6

kn
kn
kn

2.8
3

!'in

rnV

V

Electrical Characteristics
(Is = 1.5 mA and -35°C S TAS +85°C)
Parameters
Shunt Regulator
zener Voltage (+VS>
Reference Voltage (VRFF)
Quiescent Current (IS>
Operational Amplifier
Offset Voltage
+Output Voltage Swing
-Output Voltage Swing
Gain Bandwidth Product
Detector Reference Voltage
Resistors
R1

R2
R3
SCR Trigger Voltage
Detector On
....
rOff
For Men 1nIcrmaIion, call 1-800-722-7074.

1.3
0

Raytheon Semiconductor

V
3-837

RV4145
Functional Block Diagram

+Input

OpAmp
Output

VREF
(+13V)

+Vs
(+26V)

seR
Trigger
65·1748

3-838

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RV4145
Principles of Operation
The 26V shunt regulator voltage generated by the string
of zener diodes is divided into three reference voltages: 31
4 VS, 1/2 VS, and 1/4 VS. VREF is at 112 Vs and is used
as a reference to create an artificial ground of +13V at the
op amp non-inverting input.
Figure 1 shows a three-wire 120V AC outlet GFI
application using a 4145. Fault signals from the sense
transformer are AC coupled into the input and are
amplified according to the following equation:
V7 = RSENSE x ISENSE/N

The sensitivity to grounded neutral faults is adjusted by
changing the frequency of oscillation. Increasing the
frequency reduces the sensitivity by reducing the loop
gain of the positive feedback circuit. As frequency
increases, the signal becomes attenuated and the loop
gain decreases. With the values shown the circuit will
detect a grounded neutral fault having resistance of 2Q
or less.
The inputs to the op amp are protected from overvoltage
by back-to-back diodes.

seR Driver

Where V7 is the RMS voltage at pin 7 relative to pin 3,
RSENSE is the value of the feedback resistor connected
from pin 7 to pin 1, ISENSE is the fault current in amps
RMS and N is the turns ratio of the sense transformer.
When V7 exceeds plus or minus 7.2V relative to pin 3 the
SCR Trigger output will go high and fire the external SCR.

The SCR used must have a high dV/dt rating to ensure
that line noise (generated by noisy appliances such as a
drill motor) does not falsely trigger the SCR. Also, the
SCR must have a gate drive requirement of less than
200 J,lA. CF is a noise filter capacitor that prevents
narrow pulses from firing the SCR.

The formula for V7 is approximate because it does not
include the sense transformer characteristics.

The relay solenoid used should have a 3 ms or less
response time in order to meet the UL 943 timing
requirement.

Grounded neutral fault detection is accomplished when a
short or fault closes a magnetic path between the sense
transformer and the grounded neutral transformer. The
resultant AC coupling closes a positive feedback path
around the op amp, and therefore the op amp oscillates.
When the peaks of the oscillation voltage exceed the
SCR trigger comparator thresholds, the SCR output will
go high.

Shunt Regulator

Sense Transformers and Cores
The sense and grounded neutral transformer cores are
usually fabricated using high permeability laminated
steel rings. Their Single turn primary is created by
passing the line and neutral wires through the center of
its core. The secondary is usually from 200 to 1500
turns.

RUNE limits the current into the shunt regulator; 220V
applications will require substituting a 47 kn2W resistor.
In addition to supplying power to the IC, the shunt
regulator creates internal reference voltages (see above).

Magnetic Metals Corporation, Camden, NJ 08101, (609)
964-7842 and Magnetics, 900 E. Butler Road, P.O. Box
391, Butler, PA 16003, (412) 282-8282 are full line
suppliers of ring cores and transformers designed
specifically for GFI applications.

Operational Amplifier

Two-Wire Application Circuit

RSENSE is a feedback resistor that sets gain and
therefore sensitivity to normal faults. To adjust RSENSE
follow this procedure: apply the desired fault current (a
difference in current of 5 mA is the UL 943 standard).
Adjust RSENSE upward until the SCR activates. A fixed
resistor can be used for RSENSE, since the resultant
±15% variation in sensitivity will meet UL's 4-6 mA
specification window.

Figure 2 shows the diagram of a 2-wire 120V AC outlet
GFI circuit using a 4145. This circuit is not designed to
detect grounded neutral faults. Thus, the grounded
neutral transformer and capacitors C3 and C4 of Figure
1 are not used.

The roll-off frequency is greater than the grounded neutral
fault oscillation frequency, in order to preserve loop gain
for oscillation (which is determined by the inductance of
the 200:1 transformer and C4).
For More Information, call HlOO-722-7074.

Raytheon Semiconductor

3-839

~

(0)

00

""

o

~

~

~

Press

~

RreST

~~---------------~

0

o~----------------------------------------~

15K

Ground Neutral
Transformer

Latching
Contac1s

Kl

Hot

tine

"

cO'
c:
@

:D

;-"

'S
'::J'

G>

CD

CD
0

Neutral
RSENSE
1M'

RV4145

~

::s

"2-

3

:::J

n'

::s
a.
c:

a0

...

' O.OI.ILF

NC

o·

fC g.

0

' Solenoid

C3

:!l

OpAmp
Output

J..

Q

C4

TO

0c:

""
;J
@

+Vs

CD

~

(+26V)

0

SCR
Trigger

o03 F

IL

RliNE
24K

~.

s.

g

01 Tag
X0103DA

sr

C2

~

CF
2.2 JLF

iii

i.,

O.OIJLF

15-

;:>

~

~
~

;r;!

65-4113
• Value depends on transformer characteristics.

a'

f

p-

f

To Test

RTEST
~
15K

g.

;>

~

~

..lli!!......
Line o

~

"

{

\{

)
I

Neullal
RaENSE

;;;:!

1M"

..y.,

iTS
c

SolenoId

RV4145

a

NC

f\)

:::a G)
m
"T1
OS -

OpAmp
Output

::J':8=
CD

2 a·
~

-

ffl
_
3
a·c~
()

RuNE
+Vs

~j

01 Tag

SCR
Trigger

c <:
~ :5i
o a
..

24K

(+26V)

""

X0103DA

0

i

c,.

C2
O.01p.F

2.2p.F

_lISA

" Value depsnds on tJansfonnar chaIactarIstIcs

;

-"

i

:II

~
:::J'

3;::J
fIl
3

g'

ii
c

~
~

f

I
~
~

§

.~
.N

~

;i>!

(5)
SCRTrigger
65-4114

LM1851
Ground Fault Interrupter
Description

Features

The LM1851 is a controller for AC outlet ground fault
interrupters. These devices detect hazardous grounding
conditions (example: a pool of water and electrical
equipment connected to opposite phases of the AC line)
in consumer and industrial environments. The output of
the IC triggers an extemal SCR, which in turn opens a
relay circuit breaker to prevent a harmful or lethal shock.

•
•
•
•
•
•
•
•

Full advantage of the U.S. UL943 timing specification is
taken to ensure maximum immunity to false triggering
due to line noise. A special feature is found in circuitry
that rapidly resets the integrating timing capaCitor in the
event that noise pulses introduce unwanted charging
currents. Also, flip-flop is included that ensures firing of
even a slow circuit breaker relay on either half- cycle of
the line voltage when extemal full wave rectification is
used.

No potentiometer required
Direct interface to SCR
Supply voltage derived from AC line - 26V shunt
Adjustable sensitivity
Grounded neutral fault detection
Meets UL943 standards
450 J.IA quiescent current
Ideal for 120V or 220V systems

The application circuit can be configured to detect both
normal faults (hot wire to ground) and grounded neutral
faults.

I
For More Information, calI1-8OQ.722-7074.

Raytheon Semiconductor

3-843

LM1851
Thermal Characteristics

Absolute Maximum Ratings
Supply Current ......................................... 19 mA
Power Dissipation •.•.•....•.•..•....•••.•...•..... 570 mW
Operating Temperature
Range ................................... -40°C to +70°C
Operating Temperature
Range ................................. -65°C to +150°C
Lead Soldering Temperature
(SO-8, 10 sec) .................................. +260°C
Lead Soldering Temperature
(DIP, 60 sec) .....................................+300°C

Max. Junction Temp.

8-Lead
Plastic
DIP
+125°C

8-Lead
Small
Outline
+125°C

Max. PDTA<50°C

468mW

300mW

Therm. Res. 9JA

160°CIW

240°CIW

ForT" >50°C
Derate at

6.25mWI

4.17mWI

°C

°C

Therm. Res 9JC

Ordering Information
Part Number

Package

LM1851N
RV4145M

N

M

Operating
Temperature
Range
-40°C to +70°C
-40°C to+70°C

Notes:
N • a·lead plastic DIP
M =a·lead plastic sOle

Connection Information
8-Lead
Dual In-LIne Package
(Top View)

8-Lead Plastic
Dual In-Line 50-8
(Top View)

Pin
1

2
3
4
5
6
7
8

3-844

Function
SCR Trigger

• Input

65-02666

+ input
Ground
AmpOut
RsET
CT
+VS

Raytheon Semiconductor

For More Information, call HI()()"722·7074.

LMl8S1
Definition of Terms
Normal FauH: An unintentional electrical path, RB,
between the load terminal of the hot line and the ground,
as shown by the dashed lines.

Normal FauH Plus Grounded Neutral FauH: The
combination of the normal fault and the grounded
neutral fault, as shown by the dashed lines.

Hot

Hot

---lRB

GFI

Hot

Hot

~. {N._

GFI

F\OAD

---~ RB

U" { N.",.

I

I
I

I
I

~

____~

II
I

Neutral

Ra

RN

Ro

I

I

----~-------

----~-----------~I

II
I
I

----.
-=I

65-3906

'=E
65-3904

Functional Block Diagram
Trimlng
+V.

Capachor

8

Grounded Neutral FauH: An unintentional electrical
path between the load terminal of the neutral line and
the ground, as shown by the dashed lines.

7

SensltMly
Sal RasISlor

6

Sense Amplifier
Outpul

6

D3

Hot
GFI

Line {
Neutral

Neutral ~
L-____---J

Ra

~ RIN
I

----~---------~I

-=-

SAC

Invanlng

Trigger

Input

Non-Inverting
Input

Ground

65-3905

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-845

LM1851
DC Electrical Characteristics
(TA = +2SoC, ISHUNT =SmA)
Parameters
Power Supply Shunt
Regulator Voltage
Latch Trigger Voltage
Sensitivity Set Voltage
Output Drive Current
Output Saturation Voltage
Output Saturation Resistance
Output External Current
Sinking Capability
Noise Integration Sink
Sink Current Ratio

Test Conditions

Min

Typ

Max

Units

22

26

30

V

Pin7
15
Pin 8to Pin 6
6
Pin 1 With Fault
O.S
Pin 1 Without Fault
Pin 1 Without Fault
Pin 1 Without Fault,
2
VPlN1 Held to 0.3\1'
Pin 7, Ratio of Discharge
Currents Between No Fault 2.0
Fault and Fault Conditions

17.5
7
1
100
100

20
8.2
2.4
240

V
V
mA
mV
n

2.8

3.6

Conditions
l:)ee rlgure 1 iC
soon Fault (see Fig. 2) 1
soon Normal Fault,
2n Neutral (see Fig. 2) 1

Min

Typ

Max

~

t)

I

Pin 8, Average Value

S

mA
~J.LA

AC Electrical Characteristics
(TA =+2Soc, ISHUNT =SmA)

Parameters
Normal raul[ l,;urrent l:)ensltlvlty
Normal Fault Trip Time
Normal Fault With Grounded
Neutral Fault Trip Time

18

Units
mA
mS

18

mS

Notes:
1. Average of 10 trials.
2. Required Ul sensitivity tolerance is such that external trimming of lM1851 sensitivity will be necessary.
3. This externall applied current is in addition to the internal "output drive current" source.

3-846

Raytheon Semiconductor

Fer Mont Infamation, call 1-800-722-7074.

LMl8S1
Typical Performance Characteristics
(TA = +25"C)

Normal Fauft Current Threshold vs. J\e,.

Average Trip Time vs. Fauft Current
1000

1
§

~~C:!of

u

i

:UI,9

'00

10

11 III

0.01

II

~

:I

10

1
100K

If

Trip Time (Seconds)

IL

~

Ia

~

io

10

~

~

...

J

100 I-----l'---+--I--+_

10

0

~

!
:

I-----l--+--I--+_

L-----'-----'-----'---....L...--....."---'-----'

0

5

10

15

20

25

30

35

!

...

f

m~~f~v

",

:{j

1~~!IL

-lmA

0.1

~?

0.01
0.1

Output Voltage @ VPlN1M

For Mora InfcrmaIion, call 1-800-722·7074.

10M

Pin 1 Saturation Voftage vs. External Load Current. 'L

C 1000 ...---.r----r--,.--...--..---..---,
.E

1M
RSET(n)

Output Drive Current vs. Output Voftage

a

!

:=

I I II

0.1

Sense Transformer 1000:1

10

-~ ai

~
I

r--..

Ii

.........

III

o

7V

Raa - '" (rms). x (0.91)

I.......

J
...

ormal

.c.

100

:::::I

10

100

External Load Current (mA)

Raytheon Semiconductor

3·847

LM18S1
LM1851

7
TImkIg
Cap
r----+-----~ SCR

100K
0.047I1F
-In F2......."V\r-....
+In

Trigger

Or

0.002

ISHUNT

800Hz

RsEr 8

5 Op Amp
Output

GND 1-'4-1-_ _ _...

r-_...-8'-1 +V.

+

300mV _

1.5M

Figure 1. Normal Faull Sensitivity Test Circuit
Sense

GndlNeulral
CoD

Hot

CoD
Una

High II Coil

+

LM1851
7

Timing
Cap

Or SOR

+In

0.015 Trigger
OpA/np
5 0u1put

IIsET

,---+--+-..,...8, +V.
0.01/400V

t:--+---'
200pF

GND 4

0.01

+

10llF
Tant

RSEl"

•Adjust RaET for desired sensitivity.

85-31112

figure 2. 120 Hz Neutral Transformer Application

3·848

Raytheon Semiconductor

For More Information, c:a111.eoo·722·7074.

LM1851
Principles of Operation
(Refer to Functional block Diagram)
The voltage at the supply pin is clamped to +26V by the
internal shunt regulator 03. This shunt regulator also
generates an artifICial ground voltage for the
noninverting Input of A1 (shown as a +1 OV source). A1,
01, and Q2 act as a current mirror for fault current
signals (which are derived from an external
transformer). When a fault signal is present, the
mirrored current charges the extemal timing capacitor
until its voltage exceeds the latch trigger threshold
(typically 17.5V). When then this threshold is exceeded,
the latch engages and 03 turns off, allowing 12 to drive
the SCR connected to pin 1.
Extra Circuitry in the feedback path of A1 works with the
switched current source 11 to remove any charge on CT
induced by noise in the transformer. If no fault current is
present, then 11 discharges CT with a current equal to 3
ITH, where ITH is the value of current set by the external
RSET resistor. If fault signals are present at the input of
AI (which is held at virtual ground, +1 OV), one of the two
current mirrors in the feedback path of A1 (04 and 05)
will become active, depending on which half-cycle the
fault occurs in. This action will raise the voltage at Vs,
switching 11 to a value equal to ITH, and reducing the
discharge rate of CT to better allow fault currents to
charge it.
Notice that ITH discharges CT during both half-cycles of
the line, while IF only charges CT during the half-cycle in
which IF exits pin 2 (since 01 will only carry fault current
in one direction). Thus, during one half-cycle, IF-ITH
charges CT, while during the other half-cycle ITH
discharges it.

Application Circuit
A typical ground fault interrupter circuit is shown in
Figure 2. It is designed to operate on 120 VAC line
voltage with 5 mA normal fault sensitivity.
A full-wave rectifier bridge and a 15k12W resistor are
used to supply the dc power required by the IC. A 1~
capaCitor at pin 8 used to filter the ripple of the supply
voltage and is also connected across the SCR to allow
firing of the SCR on either half-cycle. When a fault
causes the SCR to trigger, the circuit breaker is
energized and line voltage is removed from the load.

For More Information. call 1-800·722·7074.

At this time no fault current flows and the CT discharge
current increases from ITH to 31TH (see Block Diagram).
this quickly resets both the timing capacitor and the
output latch. The circuit breaker can be reset and the
line voltage again supplied to the load, assuming the
fault has been removed. A 1000:1 sense transformer is
used to detect the normal fault The fault current, which
is basically the differerlCe current between the got and
neutral lines, Is stepped down by 1000 and fed Into the
input pins of the operational amplifier through a 10 ~
capacitor. The 0.0033 ~ capacitor between pin 2 and
pin 3 and the 200 pF between pins 3 and 4 are added to
obtain better noise immunity. The normal fault sensitivity
Is determined by the timing capacitor discharging
current, ITH. ITH can be calculated by:
ITH= ~ -+- 2
RSET

(1 )

At the decision point, the average fault current just
equals the threshold current, ITH.

ITH = IF (rms) x

0.91

2

(2)

Where IF(rms) is the rrns input fault current to the
operational amplifier and the factor of 2 is due to the fact
that IF charges the timing capacitor only during one halfcycle, while ITH discharges the capaCitor continuously.
The factor 0.91 converts the rrns value to an average
value. Combining equations (1) and (2) we have:

7V
RsET = IF (rrns) x 0.91

(3)

For example, to obtain 5 rnA(rrns) sensitivity for the
circuit in Figure 2 we have:

7V
RSET = 5 rnA x 0.91
1000
= 1.5 Mn

Raytheon Semiconductor

(4)

3-849

LM1851
The .correct value for RSET can also be determined
from the characteristic curve that plots equation (3).
Note that this Is an approximate calculation; the exact
value of RSET depends on the specific sense
transformer used and LM1851 tolerances. Inasmuch as
UL943 specifies a sensitivity "Window" of 4 mA to 6mA,
provision should be made to adjust RsEl with a
potentiometer.
Independent of setting sensitivity, the desired integration
time can be obtained through proper selection of the
timing capacitor, CT. Due to the large number of
variables Involved, proper selection of CT Is best done
empirically. The following design example should only
be used as a guideline.
Assume the goal Is to meet UL943 timing requirements.
Also assume that worst case timing occurs during GFI
start-up (S1 closure) with both a heavy normal fault and
a 20 grounded neutral fault present this situation Is
shown diagrammatically below.

•

Subtract 4 rns time required to open a sluggish
circuit breaker.

•

This gives a total s 10 rns maximum Integration time
that could be allowed.

•

To generate 8 ms value of integration time that
accommodates component tolerances and other
variables:
(5)
Or= 1xT
V

where T = integration time
V = threshold voltage
I = average fault current Into CT
1=

,

,

(O.S)lt

As

500

-

(0.2)1

~
0.4

As
500

~I
65-3913

,

w

,

,

current
division of
Input sense
transformer

Start with a S 25 rns specification. Subtract 3 rns
GFI tum-on time (15k and 1 ~. Subtract 8 rns
potential loss of one half-cycle due to fault current
sense of half-cycles only;

x (0.91)
'W'

"

'W'

(6)

,

CT charging
rms to
on half-cycles average
only
conversion

UL943 specifies S 25 ms average trip time under these therefore:
conditions. Calculation of CT based upon charging
currents due to normal fault only Is as follows:
CT = [( ~~~ )x (1.60~40.4)x

3-850

)

GFI
Neutral

•

RN
RG+RN
portion of
fault current
shunted
around GFI

heavy fault
current generated
(swamps ITH)

Hot
Line

(

(10~0)x

G

)X(0.91) ]x O.OOS

17.5
CT = 0.01

Raytheon Semiconductor

JIF

(7)

For Mora InIcrmaIion, caD 1.aoo-722·7074.

IM1851
In practice. the actual value of CT will have to be
modified to include the effects of the neutral loop upon
the net charging current. The effect of neutral loop
induced currents is difficult to quantize. but typically they
sum with normal fault currents. thus allowing a larger
value of CT.

The larger capacitor can be accommodated because RN
and Ra are not present. allowing the full fault current, I.
to enter the GFI.

For UL943 requirements. 0.015 JlF has been found to
be the best compromise between timing and noise.

In Figure 2. grounded neutral detection is accomplished
by feeding the neutral coil with 120 Hz energy
continuously and allowing some of the energy to couple
into the sense transformer during conditions of neutral
fault.

For those GFI standards not requiring grounded neutral
detection. a still larger value capacitor can be used and
better noise immunity obtained.

Transformers may be obtained from Magnetic Metals.
Inc.• 21st Street and Hayes Street, Camden. NJ 08101
- (609) 964-7842.

For More Information. call 1-800·722·7074.

Raytheon Semiconductor

3·851

LM1851
Schematic Diagram

(8)

(3)
(8)

(I)

(4)

(7)
l1li-3914

3-852

Raytheon Semlcondu~or

For Men Infcrmation. call 1-800-722-7074.

RM2207
RM2207
Voltage Controlled Oscillator

Description

Features

The RM2207 is a monolithic voltag~ontrolled oscillator
(VCO) integrated circuit featuring excellent frequency
stability and a wide tuning range. The circuit provides
simultaneous triangle and squarewave outputs over a
frequency range of 0.Q1 Hz to 1 MHz. It is ideally suited
for FM, FSK and sweep or tone generation as well as
for phase-locked loop applications.

•
•
•
•
•
•
•
•
•
•

As shown In the Block Diagram, the circuit is comprised
of four functional blocks: a variable-frequency oscillator
which generates the basic periodic waveforms; four
current switches actuated by binary keying inputs; and
buffer amplifiers for both the triangle and squarewave
outputs. The intemal switches transfer the oscillator
current to any of four external timing resistors to
produce four discrete frequencies which are selected
according to the binary logic levels at the keying
terminals (pins 8 and 9).
The RM2207 has a typical drift specification of 20 ppm!
"C. The oscillator frequency can be linearly swept over a
1000:1 range with an external control voltage; and the
duty cycle of both the triangle and the squarewave
outputs can be varied from 0.1 % to 99.9% to generate
stable pulse and sawtooth waveforms.

Excellent temperature stability - 20 ppml"C
Linear frequency sweep
Adjustable duty cycle - 0.1% to 99.9%
Two or four level FSK capability
Wide sweep range -1 000:1 min.
Logic compatible input and output levels
Wide supply voltage range - ±4V to ±13V
Low supply sensitivity ± 0.15%/V
Wide frequency range - 0.Q1 Hz to 1 MHz
Simultaneous triangle and squarewave outputs

Applications
•
•
•
•
•

FSK generation
Voltage and current-to-frequency conversion
Stable phase-locked loop
Waveform generation triangle, sawtooth, pulse,
squarewave
FM and sweep generation

I
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-853

RM2207
Absolute Maximum Ratings

Thermal Characteristics

Supply Voltage .................................................... +26V
Storage Temperture Range .....•..•••...• -65"C to +150°C
Operating Temperature Range .......... -55"C to +125"C
Lead Soldering Temperature ........................... +300"C
(60 sec)

Ordering Information
Part Number
RM2207D
RM2207D1883B

Package

14-Lead
Ceramic DIP
+175"C
1042mW
60"CIW

Max. Junction Temp.
Max. Po TA < 50"C
Therm. Res OJC
Therm. Res. OJA
For TA > 50"C Derate at

8.33mWI"C

Connection Information
Operating
Temperature
Range

Top View
Trianglewave
Output

D

-55"C to +125°C

Notes:
/883B suffix denotes MIL-STD-883, Level B processing
D -14-Lead Ceramic DIP
Current

Sw~ches 1----19 }

L_j--18

Binary
Keying
Inputs
65-0623

3-854

Raytheon Semiconductor

For More Informalion, call 1-800-722-7074.

RM2207
Electrical Characteristics
(Test Circuit of Figure 1, Vs =:H3V, TA" +2SOC, C. SOOO pF, R1 .. R2 .. R3 .. R4 .. 20 1<0, RL" 4.71<0, binary inputs grounded, 81
and 82 closed unless otherwise specified)
Parameters
General Characteristics

I

Supply Voltage
Single Supply
Split Supplies
Supply Current
Single Supply
Split Supplies
Positive
Negative

Test Conditions

See Typical Performance
Characteristics

Min

Typ

Max

UnHs

+8.0
±4

+12
±6

+26
±13

V
V

5.0

7.0

rnA

5.0
4.0

7.0
6.0

rnA
rnA

2.2

2.8

V

Measured at pin 1,
S1 open (See Fig. 2)
Measured at pin 1,
S1 open (See Fig. 1)
Measured at pin 12,
S1, S20pen

Binary Keying Inputs

Switching Threshold

Measured at pins 8 and 9.
Refer to pin 10.

1.4

Input Resistance

5.0

kn

1.0
0.01
±1.0
0.5

MHz
Hz
%offo
%offo

Oscillator Section - Frequency Characteristics

Upper Frequency Limit
Lower Practical Frequency
Frequency Accuracy
Frequency Matching
Frequency Stability
vs. Temperature (Note 1)
vs. Supply Voltage
Sweep Range
Sweep Linearity
10:1 Sweep
1000:1 Sweep
FM Distortion
Recommended Range of
Timing Resistors
Impedance at Timing Pins
DC Level at Timing Terminals

C=500pF,R3=2kn
C =50J.l.F, R3 .. 2kn

0.5

OOC < TA < +7SoC
R3 = 1.S knforfH
R3 = 2 Mn for fL
C -5000pF
fH" 10 kHz, fL - 1 kHz
fH = 100 kHz, fL = 100 Hz
±10% FM Deviation
See Characteristic
Curves
Measured at pins 4, 5, 6, or 7

1000:1

±3.0

20
0.15
3000:1

50

ppmf"C
%N
fHlfL

1.0
5.0
0.1

2.0

%
%
%
kn

1.5

2000
75
10

n
mV

4

6
10
+100
0.1

Vp_p
n
mV
%

11

12
0.2
200
20

Output Characteristics

Triangle Output
Amprrtude
Impedance
DC Level
Linearity
Squarewave Output
Amplitude
Saturation Voltage
Rise Time
Fall Time

Measured at pin 14

Referenced to pin 10
from 10% to 90% of swing
Measured at pin 13,
S2Closed
Referenced to pin 12
CLS10pF
CLS10pF

0.4

Vp_p
V
ns
ns

Note: 1: Guaranteed by design.
For More Inbmation, call 1-1100-722-7074.

Raytheon Semiconductor

3-855

RM2207
Typical Performance Characteristics
Typical Operating Range for Splft Supply Voltage
+~~----~----~------~----~

i

Frequency h;c)Jracy vs. llming Resistance

7

It !

+20

~

+10

~

I

f
j

I---~;.r;

+51---~~=---+-~1
00

-0
-10
-15
Negative Supply (Volts)

..

I

~
-~

./

./

Ii "

....

./

./

/.

100K
1M
10K
Timing Resistance (n)

1K

~--"T""--""T"-__r---r--r_~

R r -2Mn

E

TA = +25°C

C 1.02

f

1M

10M

Normalized Frequency Drift vs. Supply Voftage

1.04

1.00

I

0.98

'I

0.96

10K

i..

!

./

.....

-2

1
a: 100K
l

!

L

Vs -+6V
C_5000pF

-7

-20

Recommended llmlng Resistor Value vs. Power Supply Voftage*
10M ~----~----__r-------r-----....,

§:

~

3

';;: +15 1------f7l7L..c.,..£",<<;..oQl'X:-----t------i

Irn

/
-

~

!

1K
0

4
8
12
Spilt Supply Voltage (V)
I

0.94

:!

0.92

16

2

I

I

I

0

8
16
24
Single Supply Voltage (V)

I

I

4

32

4

,
8

8
10
6
Spilt Supply Voltage (V)
I

,

I

12

14

,

20
12
14
18
Single Supply Voltage (V)

22

Normalized Frequency Drift vs. Temperature

Pulse and Sawtooth Outputs

l

+2~__r---r--_r__,r___r--~--r_....,

~

+1

...

-1

J

-2

I'
;

J
°RT • Parallel combination of activated timing resislDrs

3-856

I

-3 L-.&.....,-.L.....-.L.....-'-L....---!----'----'
-75 -00 "-~ 0 +~ +50 +75 +100 +1~
Temperature (OC)

Raytheon Semlconduct()r

For More InfamaIion, call 1-800-722-7074.

RM2207
Description of Circuit Controls
Timing Capacitor (pins 2 and 3)
The oscillator frequency is inversely proportional to the
timing capacitor, C. The minimum capacitance value is
limited by stray capacitances and the maximum value by
physical size and leakage current considerations.
Recommended values range from 100 pF to 100 J.LF.
The capacitor should be non-polarized.
Timing Resistors (pins 4, 5, 6 and 7)
The timing resistors determine the total timing current,
IT, available to charge the timing capacitor. Values for
timing resistors can range from 1.5 kn to 2 MQ;
however, for optimum temperature and power supply
stability, recommended values are 4 kn to 200 kn To
avoid parasitic pick up, timing resistor leads should be
kept as short as possible. For noise environments,
unused or deactivated timing terminals should be
bypassed to ground through 0.1 J.LF capacitors.
Otherwise, they may be left open.
Supply Voltage (pins 1 and 12)
The RM2207 is designed to operate over a power
supply range of ±4V to ±13V for split supplies, or 8V to
26V for single supplies. At high supply voltages, the
frequency sweep range is reduced. Performance is
optimum for ffN, or 12V single supply operation.
Binary Keying Inputs (pins 8 and 9)
The internal impedance at these pins is approximately 5
kn.. Keying levels are <1.4V for "zero" and> 3V for
"one" logic levels referenced to the DC voltage at pin 10.
Bias for Single Supply (pin 11)
For single supply operations, pin 11 should be externally
biased to a potential between +Vf:J3 and +Vf:J2 (see
Figure 2). The bias current at pin 11 is nominally 5% of
the total oscillation timing current IT.
Ground (pin 10)
For split supply operation, this pin serves as circuit
ground. For single supply operation, pin 10 should be
AC grounded through a 1 J.LF bypass capacitor. During
split supply operation, a ground current of 2 IT flows out
of this terminal, where IT is the total timing current.
Squarewave OUtput (pin 13)
The squarewave output at pin 13 is an "open-rollector"
stage capable of sinking up to 20 mA of load current. RL
serves as a pull-up load resistor for this output.
Recommended values for RL range from 1 k.Q to 10 kn.
For More Information, call 1-800·722·7074.

Trlanglewave Output (pin 14)
The output at pin 14 is a trianglewave with a peak swing of
approximately one-half of the total supply voltage. Pin 14
has a very low output impedance of 1on and is internally
protected against short circuits.
Note: Triangle waveform linearity is sensitive to parasitic coupling
between the square and the trianglewave outputs (pins 13 and
14). In board layout or circuit wiring, care should be taken to
minimize stray wiring capacitance between these pins.

Operating Instructions
Precautions
The following precautions should be observed when
operating the RM2207 family of integrated circuits:
1. Pulling excessive current from the timing terminals will
adversely affect the temperature stability of the circuit.
To minimize this disturbance, it is recommended that
the total current drawn from pins 4, 5, 6 and 7 be
limited to <6 mA. In addition, permanent damage to
the device may occur if the total timing current
exceeds 10 mAo
2. Terminals 2,3,4,5,6 and 7 have very low internal
impedance and should, therefore, be protected from
accidental shorting to ground or the supply voltages.
3. The keying logic pulse amplitude should not exceed
the supply voltage.

Split Supply Operation
Figure 1 is the recommended circuit connection for split
supply operation. The frequency of operation is determined
by the timing capacitor, C, and the activated timing
resistors (R1 through R4). The timing resistors are
activated by the logic Signals at the binary keying inputs
(pins 8 and 9), as shown in Table 1. If a single timing
resistor activated, the frequency is 1/RC.
Table 1. Logic Table for Binary Keying Controls
Logic Selected
Timing
Pins
0 6
fl
0 1
6&7
1 0
5
14 &5 f2+f~

~vel

sr-s-

Frequency Definitions
fl = 1/R3C, ~1 = 1/R4C
f2 = 1/R2C, ~f2 = lIR1C
fl +Ml
f2
Logic levels: 0 = Ground
Logic levels 1 =?3V

Note: For single supply operation, logic levels are referenced to
voltage at pin 10.

Raytheon Semiconductor

3·857

RM2207
S2

10 r-.:..L..-:"L..-..:...L.....::.I-...::.L--'13

Squarewave

RM2207
Device

Output

.----()-'.-I

11

Under Test

14

Trianglewave

.......,I'IIT"-rI-"fT'"~-r--""I!"T.......

OUlput

R2

-Vs

o-+-4:r.:-.()-+----.....

Note: This circuit is for Bench Tests only. DC testing is normally performed
with automated test equipment using an equivalent circuit.

Figure 1. Test Circuft for Splft Supply Operation

Otherwise, the frequency Is either1/(R111R2)C or
1/(R111R4)C.
The squarewave output Is obtained at pin 13 and has a
peak-to-peak voltage swing equal to the supply voltages.
This output is an ·open-collector" type and requires an
external pull-up load resistor (nominally 5 kq to the
positive supply. The triangle waveform obtained at pin 14
is centered about ground and has a peak amplitude of
+VsJ2.
The circuit operates with supply voltages ranging from
fAV to ±13V. Minimum drift occurs with fIN supplies.

Single Supply Operation
The circuit should be interconnected as shown In FlQure
2 for single supply operation. Pin 12 should be
grounded, and pin 11 biased from +VS through a
resistive divider to a value of bias voltage between +Vg13
and +VsJ2. Pin 10 is bypassed to ground through a 0.1
J.IF capaCitor.
For single supply operation, the DC voltage at pin 10 aOO
the timing terminals (pins 4 through 7) are equal and
approximately 0.6V above Ve, the bias voltage at pin 11.
The logic levels at the binary keying terminals are
referenced to the voltage at pin 10.
On-Off Keying
The RM2207 can be keyed on and off by simply
activating an open circuited timing pin. Under certain
conditions, the circuit may exhibit very low frequency

3-858

«1 Hz) residual oscillation in the ·olr state due to internal
bias current. If this effect is undesirable, it can be
eliminated by connecting a 10 MO resistor from pin
3to+VS·
Frequency Control (Sweep and FM)
The frequency of operation is controlled by varying the
total timing current, IT, drawn from the activated timing
pins 4, 5, 6 or 7. The timing current can be modulated by
applying a control voltage, Vc, to the activated timing pin
through a series resistor Rc as shown in Figure 3.
For split supply operation, a negative control voltags, Vc,
applied to the circuit of Figure 3 causes the total timing
current, IT, and the frequency, to increase.
As an example, in the circuit of Figure 3, the binary keying
Inputs are grounded. Therefore, only timing pin 6 is
activated.

The frequency of operation is determined by:
f•

1
R3CB

[' -

VcR3 ] Hz
(Rc)(-Vsl

Pulse and SaWtooth Operation
The duty cycle of the output waveforms can be controll~
by frequency shift keying at the eOO of every half cycle of
oscillator output. This is accomplished by connecting one
or both of the binary keying inputs (pins 8 or 9) to the
squarewave output at pin 13. The output waveforms can
then be converted to positive or negative pulses aOO
sawtooth waveforms.

Raytheon Semiconductor

ForMorelnformalion, calI1-8O().722-7074.

RM2207

r

O.lI1F

S2

c

Squarewave
Output

13

RM2207
3.9K

Device

11

Under Test

Trianglewave
Output

14

'--~~6-r-""'7:;"T""--:4-r--::-Ir--'
R3

R4

R2

Rl

Fgure 2. Test Circutt for Single Supply Operation

Figure 4 is the recommended circuit connection for duty
cycle control. Pin 8 is shorted to pin 13 so that the circuit
switches between the "0,0· and the "1,0" logic states
given in Table 1. Timing pin 5 is activated when the
output is "high", and pin 6 is activated when the
squarewave output goes to a "low" state.
The duty cycle of the output waveforms is given as:

- Ie

rVe

IT

Rc

RM2207

~Io

R3

-Vs

CB

65-0632

Figure 3. Frequency Sweep Operation

R2
Duty Cycle = R2 + R3
and can be varied from 0.1 % to 99.9% by proper choice
of timing resistors. The frequency of oscillation, f, is
given as:

9

f=+ [R2:R3]

RM2207

The frequency can be modulated or swept without
changing the duty cycle by connecting R2 and R3 to a
common control voltage Vc instead of to -VS. The
sawtooth and the pulse output waveforms are shown in
the Typical Performance Characteristics Graphs.

5

6

R2

R3

-vs o--4----t----'
~CB

8

13

14

Sawtooth
Output
4.7K
Pulse
Output

+Vs
65.0633

Figure 4. Pulse and Sawtooth Generation

For More Information, calI1.aoo-722-7074.

Raytheon Semiconductor

3-859

RM2207
Schematic Diagram
r-~------~r---~~----~~----~--~~------~----O+V8
(1)

~----~------~--~--~~-O~.
(12)
65-0622

3-860

Raytheon Semiconductor

For More Information. call 1-800-722·7074.

RC2211
RC2211
FSK Demodulatorrrone Decoder

Description
The RC2211 is a monolithic phase-locked loop (Pll)
system especially designed for data communications. It
is particularly well-suited for FSK modem applications,
and operates over a wide frequency range of 0.01 Hz to
300 kHz. It can accommodate analog signals between 2
mV and 3V, and can interface with conventional DTL,
m and ECl logic families. The circuit consists of a
basic PLL for tracking an input signal frequency within
the passband, a quadrature phase detector which
provides carrier detection, and an FSK voltage
comparator which provides FSK demodulation. External
components are used to independently set carrier
frequency, bandwidth and output delay.

Features
+ Wide frequency range - 0.01 Hz to 300 kHz
+ Wide supply voltage range - 4.5V to 20V
+ DTIJTTlJECl logic compatibility
+ FSK demodulation with carrier-detector
+ Wide dynamic range - 2 mV to 3 VRMS
+ Adjustable tracking range - ±1 % to ±80%
+ Excellent temperature stability - 20 ppmf"C typical
Applications
+ FSK demodulation
+ Data synchronization
+ Tone decoding
+ FM detection
+ Carrier detection

Functional Block Diagram

FSK
DaIa
Output

I

FSK

Input

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-861

RC2211
Absolute Maximum Ratings

Thermal Characteristics

Supply Voltage ....................................................:t!2.0V
Input Signal Level ........................................... 3 VRMS
Storage Temperature Range ............. -65"C to +150"C
Operating Temperature Range
RM2211 D ................................... -55°C to +1250C
RV2211 N ...................................... -25°C to +85"C
RC2211N ......................................... OOC to +70°C
Lead Soldering Temperatuare (SO sec.) .......... +300"C

Max. Junction Temp.
Max. Po TA < SO"C
Therm. Res OJC
Therm. Res. OJA
For TA > SO°C Derate at

Connection Information

Ordering Information

Top View
+Vs

Part Number
14

~

Timing
Capacitor

~
Lock
Detector
Filter

Timing
Resistor
Loop
...Detector
OUtput
Reference
Voltage
Output
Reference
Bypass

3

GND

Lo~

Detector
Outputs

19
FSK
Data
OUtput

6
FSK Comparator

RC2211N
RV2211N
RM2211D
RM2211 D/8838

14-Lead
Plastic DIP
+12S"C
468mW
1S0°C!W
S.5mWfC

14-Lead
Ceramic DIP
+17S"C
1042mW
SO°C/W
120°C/W
8.33mWfC

Package

Operating
Temperature
Range

N
N
D
D

O"C to +70"C
-2SoC to +85°C
-S5°C to +125°C
-55°C to +125OC

Notes:
/8838 suffix denotes MIL-STD-883. Level 8 processing
N • 14-Lead Plastic DIP
D • 14·Lead Ceramic DIP

FSK

8 Comparator
Input

65-0657

3·862

Raytheon Semiconductor

For More Information. calI1.aoo·722·7074.

RC2211
Electrical Characteristics
Parameters
General
Supply Voltage2
Supply Current

Units

Test Conditions

v
rnA

RO

fiL

~

~
~

(4)

GND
lI'V11AVV """"IUWIIVY _ 1 _ _ _

-......,111_..,..... __ •

r"""R VVlllt'lUGM.II

6S-0658

o

~

~

RC4200
RC4200
Analog Multiplier
Description
The RC4200 analog multiplier has complete
compensation for nonlinearity, the primary source of
error and distortion. This multiplier also has three onboard operational amplifiers designed specifically for
use in multiplier logging circuits. These amplifiers are
frequency compensated for optimum AC response in a
logging circuit, the heart of a multiplier, and can
therefore provide superior AC response.

Features
•
•
•
•

High accuracy
Nonlinearity - 0.1 %
Temperature coefficient - 0.005°/JoC
Multiple functions
Multiply, divide, square, square root, RMS-to-DC
conversion, AGC and modulate/demodulate
Wide bandwidth - 4 MHz
Signal-to-noise ratio - 94 dB

The RC4200 can be used in a wide variety of
applications without sacrificing accuracy. Four-quadrant
multiplication, two-quadrant division, square rooting,
squaring and RMS conversion can all be easily
implemented with predictable accuracy. The nonlinearity
compensation is not just trimmed at a single
temperature, it is designed to provide compensation
over the full temperature range. This nonlinearity
compensation combined with the low gain and offset
drift inherent in a well-designed monolithic chip provides
avery high accuracy and a low temperature coefficient.
The excellent linearity and versatility were achieved
through circuit design rather than special grading or
trimming, and therefore, unit cost is very low.
The RC4200 is ideal for use in low distortion audio
modulation circuits, voltage-controlled active filters, and
precision oscillators.

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-871

RC4200
Ordering Information

Absolute Maximum Ratings
Supply Voltage1 ............................................................-22.V
Intemal Power DIssipatlon2.................................... 500 mV
Input Current .........................................................-5 rnA
Storage Temperature Range
RM4200/4200A .............................. -65"C to +150"C
RC4200/4200A .............................. -55"C to +125"C
Operating Temperature Range
RM4200/4200A .............................. -55"C to +125"C
RC4200/4200A .................................... D"C to +70"C
Notes:

1.
2.

Part Number

Operating
Temperature
Range

Pa~ge

RC4200N
RC4200AN
RM4200D
RM4200AD
RM4200AD1883B

N
N
0

O°Cto +70°C
0°Cto+70°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C

0
0

Notes:
/8838 suffix denotes MIL-STD-883. Level 8 processing
N • 8-lead plastic DIP
D • a·lead ceramic DIP

For a supply voltage greater than -2211. the absolute maximum
input voltage is equal to the supply voltage.
Observe package thermal characteristics.

Connection Information

Thermal Characteristics
(Stili air, soldered into PC board)

Top View

Pin
1
2
3
4

85-0070

3-872

5
6
7
8

Function
12
VOS2
-VS
13 (Output)
14
GND

VOS1
11

Max. Junction Temp.
Max. Po TA < 50"C
Therm. Res. 8~Q
Therm. Res. 8JA
For TA > 50"C Derate at

Raytheon Seml.conductor

8-Lead

8-Lead

Plastic
DIP
+125"C
468mW

Ceramic
DIP
+175"C
833mW
45"CIW
150"CIW
8.33 mW/"C

160"CIW
6.25 mW/"C

For More Information, calI1-800-n2-7074.

RC4200
Electrical Characteristics
(Over operating temperature range, Vs = -1SV unless otherwise noted)

Parameters
Total Error as Multiplier
Untrimmed
With External Trim
Versus Temperature
Versus Supply (-9 to -18V)
Nonlinearity
Input Current Range (11, 12 and 14
Input Offset Voltage
Input Bias Current
Average Input Offset
Voltage Drift
Output Current Range (13)
Frequency Response, -3dB point
Supply Voltage
Supply Current

Test Conditions
TA= +25"C
Note 1

Min

4200A
Typ Max

Min

±2.0

50 J.IA Si1,2,4 S 250 J.IA,
TA = +25°C (Note 2)

±D.2
±D.005
±D.1
±D.1
1000
:1:5.0

1.0
11 = 12= 14= 150 J.IA
TA=+25°C
11 = 12 = 14 = 150 J.IA
TA= +25°C

1.0

300

:1:50
1000

1.0
-18

4.0
-15

/1 = 12 = 14 = 150 J.IA
TA= +25°C

Max Units
:1:3.0

±D.2
±D.OOS
±D.1

11 = 12 = 14 = 150 J.IA
Note 3

4200
Typ

-9.0
4.0

1.0
-18

4.0
-15

%
%

%/"C
o/JV
±D.3
1000
±10

mV

500

nA

%

J.IA

±100 I·NrC
1000
J.IA
MHz
-9.0
V
4.0
mA

NOles:
1. Refer to Figure 6 for example.
2. The illlut circuits tend to become unstable aliI. 12. ~ < 50 !lA and linearity decreases when 11. 12. ~ > 250 !lA (sq. @ 11 =12 =500 !lA. nonfinearity error •
0.5%).
3. These specifICations apply w~h output (13) oonnected to an op amp summing junction. ff desired. the output (13) at pin (4) can be used to drive a resistive load
directly. The resistive load should be less than 7000 and must be pulled up to a pos~ive supply such that the voltage on pin (4) stays w~hin a range 01 0 to +5V.

I
For More Information. call HlOO-722·7074.

Raytheon Semiconductor

3·873

RC4200
Functional Description
The RC4200 multiplier is designed to multiply two input
currents (11 and 12) and to divide by a third input current
(14). The output is also in the form of a current (13). A
simplified circuit diagram is shown in Figure 1. The
nominal relationship between the three inputs and the
output is:
(1 )

The three input currents must be positive and restricted
to a range of 1 IJA to 1 mAo These currents go into the
multiplier chip at op amp summing junctions which are
nominally at zero volts. Therefore. an input voltage can
be easily converted to an input current by a series
resistor. Any number of currents may be summed at the
inputs. Depending on the application. the output current
can be converted to a voltage by an external op amp or
used directly. This capability of combining input currents
and voltages in various combinations provides great
versatility in application.
Inside the multiplier chip. the three op amps make the
collector currents of transistors 01. Q2 and Q4 equal to
their respective input currents (11. 12. and 14). These op
amps are designed with current-source outputs and are
phase-compensated for optimum frequency response

as a multiplier. Power drain of the op amps was
minimized to prevent the introduction of undesired
thermal gradients on the chip. The three op amps
operate on a single supply voltage (nominally -15V) and
total quiescent current drain is less than 4 rnA. These
special op amps provide significantly improved
performance In comparison to 741-type op amps.
The actual multiplication is done within the log-antilog
configuration of the 01-Q4 transistor array. These four
transistors. with associated proprietary circuitry. were
specially designed to precisely implement the
relationship
kT
ICN
(2)
VSEN =0 In ISN
Previous multiplier designs have suffered from an
additional undesired linear term in the above equation;
the collector current times the emitter resistance. The
lerE term introduces a parabolic nonlinearity even with
matched transistors. Raytheon has developed a unique
and proprietary means of inherently compensating for
this undesired ICrE term. Furthermore. this Raytheondeveloped circuit technique compensates linearity error
over temperature changes. The nonlinearity versus
temperature is significantly improved over earlier
designs.
From equation (2) and by assuming equal transistor
junction temperatures. summing base-to-emitter voltage
drops around the transistor array yields:
(3)
This equation reduces to:

I2

4200 Multlpiler

11

1112
1314

IS11S2
1S31S4

-=--

(4)

The ratio of reverse saturation currents. ISlI82/1831S4.
depends on the transistor matching. In a monolithic
multiplier this matching is easily achieved and the ratio
is very close to unity. typically 1.0 ±1%. The final result
is the desired relationship:
1112
13 =-14-

65-1885

(5)

The inherent linearity and gain stability combined with
low cost and versatility makes this new circuit ideal for a
wide range of nonlinear functions.

Figure 1_ Functional Diagram

3-874

Raytheon Semiconductor

For More Information. call 1-800-722-7074_

RC4200
Basic Circuits
Vx

8

Current Multiplier/Divider

13 =~

7

(6)

Vx

~

V
11 = -L

14

-..
12

-=V

4
13

-

+
-=-

.1

14 = .!t.
~

~

2

12=~

+Vz
V

RC4200
Multiplier

-=

+

~

..-

7

R1

R2

Vy

11

RS

-

~Cs

RC4200
JlIltlpller

12

4

2

Ca~ -=

-Va

-----

Figure 3

"

65-1883

85-1SS2

Amplifier A1 is used to convert the 13 current to an
output voltage.
Multiplier: Vz = constant ¢ 0
Divider: Vy = constant ¢ 0

Ammeter

'~1::-

Vo

13

Rs-10kOhms
Cs - 0.005 !1F

R1

8

+

-=
Vy

14
The current-product-balance equation restates this as:

R1

+Vz

11

The basic design criteria for all circuit configurations
using the 4200 multiplier is contained in equation (1):
i.e.•

F4

....

R1

Voltage MultiplierlDivider

-

R1
Vx O-....IV\I\r--;8=-1
11

Figure 2

7

RC4200
Multiplier

Dynamic Range and Stability
The precision dynamic range for the 4200 is from +50
IJA to +250 IJA inputs for 11.12 and 14. Stability and
accuracy degrade if this range is exceeded.
To improve the stability for input currents less than 50
IJA. filter circuits (RSCS) are added to each input (see
Figure 3).

I

65-1884

Solving for Vo = VXVy RoA4
Vz
R1R2
For a multiplier circuit Vz = VR =constant
Therefore: Va = VXVyK where K = RoA4
VR R1R2
For a divider circuit Vy = VR = constant
Therefore: Va = Vx K where K = VR ROR4
Vz
R1R2
Figure 4

For More Information. calI1-BOO-722-7074.

Raytheon Semiconductor

3-875

RC4200
Extended Range

Cross-Product Cancellation

The input and output voltage ranges can be extended to
include 0 and negative voltage signals by adding bias
currents. The RSCS filter circuits are eliminated when
the input and biasing resistors are selected to limit the
respective currents to 50 ~ min. and 250 ~ max.

Cross-products are a result of the VXVR and VyVR
terms. To the extend that: R1 Rb = RexRd and R2Ra =
Rey~, cross-product cancellation will occur.

Extended Range Multiplier

The offset caused by the VREF2 term will cancel to the
extent that: RaRb = ReRd, and the result is:

Arithmetic Offset Cancellation

+VREF

R.,

Ra

...

R.t

VyVX VOVREF

5

Vx

(Input)

Rl

-- -

Vy

4

Rc.

RoRd

Vo

Ro

(OutpuQ

Resistor Values

~

"::"

or Vo - VXVyK

VREF R1R2

...

2

RoRd

Where K =

RC4200
Muhlpllar

(InpuQ

--

R1R2

~

+Vs

Inputs:

.Vs

Vx(min.) S Vx S Vx(max.)
Rex

AVx = Vx(max.) - Vx(min.)

Figure 5

Vy(min.) S Vy S Vy(max.)
Resistors Ra and Rb extend the range of the Vx and Vy
inputs by picking values such that:
11(min.) =

Vx(min.) +VREF = 50~,
R1
Ra

and 11 (max.) = Vx(max.) +VREF = 250 ~;
R1
Ra
also 12(min.) = Vy(min.) +VREF = 50 ~,
R2
Rb
Vy(max.) VREF 2 0,,/1
d
I
(
)
an 2 max. =
R
+= 5 ~.
2
Rb

AVy = Vy(max.) = Vy(min.)
VREF = Constant (+7V to +18V)
K=

VXVy

AVXVREF
Ra = -2---'50-!lM-:-:V-'-x---=20~0=~"-:-,,-V:-x(:-m-ax--:-.)
AVyVREF
Rb = -2-50-!lM-V-y--....:...20~0=~"--V-y(-m-ax-.)
Re=

R~b, Rex = R~b ,Rev =R~a
R
0-

3-876

(Design Requirement)

AVx
AVy
VREF
R1 = 200 ~ , R2 = 200 ~ , ~ = 250 ~

Resistor Re supplies bias current for 13 which allows the
output to go negative.
Resistors Rex and Rey permit equation (6) to balance,
ie.:

~

Raytheon Semiconductor

AVXAVyK
160~

For More Information, call HlOO-722-7074.

RC4200
10K S RS = RS = R16 S50K
R7 = R11 = R14 = 1000
As = R10 = 1000 (VslO.05)
R1S = 1000 (VslO.10)
R8= R111 Ra
R12= R211 Rb
R13 = Ro II RC II Rcx II Rcv

Multiplying Circuit Offset
Adjust

...---...------...,.........- - - 0 +VREF

+Vs
100 RD

.

R19

...

.JVI,.,..,....-..."""~

R20 Z os

-Vs

RC4200

o-+-~--~~----~~

Rl rR20 can be used 10 help cancel
crossproduct errors caused by reslSlOr
product mis·match (See Appendix 1).

Multiplier

RD

~4==-1---J\Afv----,...-oVo (OtpUI)

65-1880

Procedure:
1. Set all trimmer pots to OV on the wiper.
2. Connect Vx input to ground. Put in a full scale square wave on Vv input. Adjust XoS(RS) for no square wave on Vo
output (adjust for 0 feedthrough).

3. Connect Vv input to ground. Put in a full scale square wave on Vx input. Adjust YOS(Rg) for no square wave on Vo
output (adjust for 0 feedthrough).

4. Connect Vx and Vv to ground. Adjust Vos(R16) for OV on Vo output.
Figure 6

For Mora Information, call 1-800-722-7074.

Raytheon Semiconductor

3-877

I

RC4200
Note: it is necessary to match the above resistor crossproducts to within the amount of error tolerable in the
output offset, I.e., with a 10V F.S. output, 0.1% resistor
cross-product match will give 0.1 % x 1OV =10 mV
untrimmable output offset voltage.

Extended Range Divider
+VREF
+VREF

Ra
R
Vx
(Input)

Raz

...

lie

--

8

Ret
~

Vz
(Output)

Resistor Values

~

11

7

Inputs:
Vx(min.) ~ Vx ~ Vx(max.)
tNx =Vx(max.) =Vx(min.)
VZ(min.) ~ Vz ~ Vz(max.)
tNz = Vz(max.) = Vz(min.)
VREF = Constant (+7V to +18V)

Vo
(Output)

Outputs:
Vo(min.) ~Vo ~VO(max.)
fNo =Vo(max.) =Vo(min.)

66-1879

Figure 7
K=

As with the extended range multiplier, resistors Raz and
Rao are added to cancel the cross-product error caused
by the biasing resistors, i.e.,

v~~z

(Design Requirement)

~Vo
VREF
Ro = 750 J.1A ,Rb = 250 J.1A

~Vz

,A4 = 200 J.1A

~= _______~~V~OV~R~E~F_____

750 pMVo - 700 J.1A Vo(max.)
~= _______~~V~ZV~R~E~F_____

250 pMVz - 200 J.1A Vz(max.)
Ra=
To cancel cross-product and arithmetic offset:

~~ ,Raz= ~A4
Rb

Rb
~V~VZ

R1 = 600 J.1AK
and the result is:
VXVREF
VOVz
R1Rb = ROR4
where K =

3-878

VREFROR4
R1 Rb

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4200
Divider Circuit with Offset Adjustment

Ra

Xes

~~: ~19

----------

R20

As

-VS
'::'

R18-R21 can be used in place of AS 10 help
cancel gain error due 10 resistor product
mis-match (See Appendix 1).

General
10KSRs= R13= R17S50K
R7 + Rs'" R111RailRazilRao
Rs ... R7 (VslO.05)
R9=Rb
R10 ... 100x A4
R11 = 20K
R12 = 100K
R14 +R15'" RollRc
R1S'" R15 (VslO.10)

Example: Two-Quad Divider
Vo = K (VxNz), K = k, VREF = +Vs = +15V
-10 S Vx S +10, therefore !:NX = 20
OSVZS+10, therefore L\Vz = 10
-10 SVo S+10, therefore L\Vo = 20
Ro = 26.7K
R1 = 333K
Rb = SOK
Rs, R13, R17 = 10K
A4 =50K
R7, R15 =1K
Rc =37.5K
Rs, R11 =20K
ReI = 300K
Rs, R9, R1S = 300K
Ra = 187.5K
R10 = 4.7M
Raz= 31.25K
R12=100K
Rao = 133K

I

Figure 8

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-879

RC4200
Divider Circuit Offset Adjustment
Procedure

Square Root Circuit Vo = N Wx

1. Set each trimmer pot to OV on the wiper.
2. Connect Vx (Input) to ground. Put a DC voltage of
approximately 1/2 Vz(max.) DC on the Vz (input)
with an AC (squarewave is easiest) voltage of 1/2
Vz (max.) peak-to-peak superimposed on it. Adjust
Xes (Rs) for zero feedthrough. (No AC at Yo)

Vx o-'IN\r+--t~
(lnpul)

Vz(Max.) ------------------

112 Vz (Max.)

OV

Vo
(Output)

-..FtRm-.

1/2;Z(Max.)

__________________ .

3. Connect Vx (input) to Vz (input) and put in the
1/2VZ(max.) DC with an AC of approximately 20 mV less
than Vz(max.).

8501877

Adjust Zos(RI3) for zero feedthrough.

Vz (Max.)

Hfffi-- .

1/2 Vz (Max.) - -- - -- -

OV

If RaRb = ReRd and RaoRbROAd + RaoRbReA4 =
ReAd RoA4

--

--

-

--

-

..i.

Then

~= VXVREForv02=vxKwheraK ..
RoA4

Rl Rb

VREFROA4
Rl Rb

and Vo = NVVx where N.. VI<

T

o s: Vx s: Vx(max.) and Vo(max.) =NVVx(max)

::10mV

65·1868

N=

:v~

Vo(max)2
74pA N2

4. Return Vx (input) to ground and connect Vz(max.)
DC on Vz(input). Adjust output Vos(R17) for
VO=OVO
S. Connect Vx (input) to Vz (input) and put in Vz
(max.) DC. (The output will equal K.) Decrease the
input slowly until the output (Vo = K) deviates
beyond the desired accuracy. Adjust los to bring it
back into tolerance and return to Step 4. Continue
Steps 4 and Suntil Vz reduces to the lowest value
desired.
Note: As the input to Vx and Vz gets closer to zero (an
illegal state) the system noise will predominate so much
that an integrating voltmeter will be very helpful.

(Design Requirement)

Ra = ReI = VREF

SOpA
VREF
Rb = Rc = 1S0pA
Rt=
Rao=
Ro=

VO(max)
SOpA
Vo(max)
125pA
Vo(max)
225pA

Figure 9

3-880

Raytheon Semiconductor

For More Infonnation, call1.soo-722-7074.

RC4200
Square Root Circuit Offset Adjust

+VREF

Ra
RI

Vx

+Vs

(Input)

Xes
+Vs

~~I~

~t

...

ReI

....
4

Ro

13

+Vs

5

8

~

I"

As
RC4200

R7

- s

----------

-

O.1IlF

Multiplier

12

2

fig

RI6

-Vs

Vo
(Output)

-Vs

-=
Rao

Rl ,,-R17 can be used in place of fig to help
reduce linearity error due to resistor product
mis-match (See Appendix 1).

10KS:RS= R13S:50K

65-1876

R7 = 1000
Vs
R6=R7 0.05
RS = Rl11 Rail Rao

Rl0 = RollRc

I

R11 = 1000
R12 = R11

Vs
0.1

Procedure
1. Set both trimmer pots to OV on the wiper.
2. Put in a full scale (0 to Vx(max.) squarewave on Vx input. Adjust Xos(Rs) for proper peak-to-peak amplitude on Va
output (Scaling adjust)

3. Connect Vx input to ground. Adjust VOS(R13) for OV on Va output.
Figure 10
For More Information; call 1-800-722-7074.

Raytheon Semiconductor

3-S81

RC4200
Squaring Circuits Vo = K Vx2

+VREF

Rc

R

-

8
.....
11

~o--.~~-+--r-~~

(Input)

14

7
RC4200
Multiplier

-

-

~

12

-

4

2

Ro

Vo
(Output)

13

+Vs

-Vs

Rex

4
R1

-VS
65-1875

+2VXVREF+ VREF2 =VOVREF + VREF2 +VXVREF
R1 Ra
Rl
RORd
ReRd
ReRd
If Ra2 =ReRd and R1 Ra =2RexRd
then

VOVREF

vi

R""R = - R
2 or Vo =KVX2 where K
od
1

Vx(min.)~Vx ~ VX(max.)

K=

R1

W

lJ.VX =VX(max.) - VX(min.)

V

(Design Requirement)

lJ.VX
200IJA

=

R _
lJ.VXVREF
a - 250IJA lJ.VX - 200IJA VX(max.)
V

Rd - .:B.EE- 250IJA
R2
R - ...:..:5Le- Rd

R

-~
2Rd

cx-

lJ.ViK
RO = 160lJA
Figure 11

3-882

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4200
Squaring Circuits Offset Adjust

~o-~--~~--4--;--~

(Input)

-Va
RC4200
Multiplier

--

RrR10 can be used ID cancel all
linearity errors caused by Input
oIfsel8 and realatar product
nil-malch (See Appendix 1).

12

-Va

Rex

VM~'!

R14

R18

R15

-Va

-

10.

11' F
a!>-1874

10KSR10. R11 S50K
Ra. R15 = 100n

Vs

Rg. R14= 1oon 0:1

I

RS. RS = R111Ra
R1S = RollRcllRcx

Procedure
1. Set both trimmer pots to OV on the wiper.
2. Put in a full scale (±Vx) squarewave on Vx input Adjust Zos(R10) for uniform output

3. Connect Vx input to ground. Adjust VOS(R11) for OVon Vo output.
Figure 12
For Mora Infcrmation. caD 1-800-722·7074.

Raytheon Semiconductor

3-883

RC4200
Errors Caused by Input Offsets

Appendix 1 - System Errors
There are four types of accuracy errors which affect
overall system performance. They are:

vo-~

1. Nonlinearity - Incremental deviation from absolute
accuracy. (1)
2. Scaling Error - Unear deviation from absolute
accuracy.
3. Output Offset - Constant deviation from absolute
accuracy.
4. Feedthrough(2) - Cross-product errors caused by
input offsets and external circuit limitations.
The nonlinearity error in the transfer function of the 4200
is fD.1 % max. (fD.03% max. for 4200A).
I.e.• 13 =

1;~2

...

F4

5

8

..-

II

T

'z

Vx Feedthrough--------'

OulputO/fselError - - - - - - - - - - - - '

System errors can be greatly reduced by extemally
trimming the input offset voltages of the 4200. (:f!3.0%
F.S. for 4200 and fD.1 % for 4200A.)

Vx

~i'

R2
Vy

...

F4

8

Vz
+Vs

RI

7

Vy

I

R2

-Vs

R2

4

Ro

-Va

';"

RC4200
Multiplier

65-1870

..-

Vo

13

-Vs

if; Xes =XoSX. YOS =YOSy. los =-VOSz•

flo

4

2

Vo

2

-Vs

14

12

!~

l00F4
RC4200
Multiplier

7

-

_

Scaling E r r o r - - - - - - - - - - '

-Va

vz

T-1--)

±_I- VVVOSX±VXVOSV±VOVOSZ±VOSXVOSV]

R,

I.e.• Vo = VXVy RoA4 :f!3.0% F.S,(3)(4)
Vz
R1R2

Vx

v,:":

fD.1% F.S.(4)

The other system errors are caused by voltage offsets
on the inputs of the 4200 and can be as high as :f!3.0%
(±2.0% for 4200A).

RI

F

+Vs

-

VXVy
then Vo Vz

RoA4
R1 R2

0
S (3)
fD.3 Yo F. .

Figure 14. 4200 with Input Offset Adjustment

Figure 13

65-1871

Notes:
1. The input circuits tend to become unstable at 11. 12. 14 < 50 IIA
and linearity decreases when 11. 12. 14 > 250 IIA (e.g.• @ 11 •
12 • 500 IIA nonlinearity error .. 0.5%).
2. This section will not deal with feedthrough which is proportional
to frequency of operation and caused by stray capacitance
and/or bandwidth limitations. (refer to Figure 21.)
3. Not including resistor tolerance or output offset on the op amp.
4. For 50 IIA S 11.12.14 S 250 IIA.

3-884

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

RC4200
Extended Range Circuit Errors

Method #2

The extended range configurations have a disadvantage
in that additional accuracy errors may be introduced by
resistor product mismatching.

Notice that the ratios of R1 Rb : RexRd and R2Ra :
ReYAd are both dependent of Ad, also that R1, R2, Ra
and Rb are all functions of the maximum input
requirements. By designing a multiplier for the same
input ranges on both Vx and Vy then R1 = R2, Rex =
Rey and Ra = Rb. (Note: It is acceptable to design a
four quadrant multiplier and use only two quadrants of
it.)

Multiplier (Figure 6)
An error in resistor product matching will cause an
equivalent feedthrough or output offset error:
1. R1 Rb = RexAd fa, Vx feedthrough (Vy = 0) =
faVx

2. R2Ra =ReyAd:$, Vy feedthrough (Vx =0) =:$Vy
3. RaRb = ReAd ±y, Vo offset (Vx = Vy =0) = ±WREF*
'Output offset errors can always be trimmed out with the output op
amp offset adjust. Vos (Rl61.

Reducing Mismatch Errors (Figure 6)
You need not use .01% resistors to reduce resistor
product mismatch errors. Here are a couple of ways to
squeeze maximum accuracy out of the extended range
multiplier (see Figure 6) using 1% resistors.

Method #1
Vx feedthrough, for example, occurs when Vy = 0 and
VOSY O. This Vx feedthrough will equal ±VXVOSY.
Also, if Vosz 0, there is a Vx feedthrough equal to
±VxVosz. A resistor-product error of a will cause a Vx
feedthrough of faVx. Likewise, Vy feedthrough errors
are: ±VyVOSX, ±VyVOSZ and ± ~Vy.

*

*

Total feedthrough:
~XVOSY ±VyVOsxfaVx:$Vy±l•.vx +Vy) Vosz
By carefully adjusting XoS(R5), YOS(Rg) and Zos(R20)
this equation can be made to very nearly equal zero and
the feedthrough error will practically disappear.

Select Ad to be 1% or 2% below (or above) the
calculated value. This will cause a and ~ to both be
positive (or negative) by nearly the same amount. Now
the effective value of Ad can be trimmed with an offset
adjustment ZoS(R20) on pin 5.
This technique will cause: 1) a slight gain error which
can be compensated for with the Ro value, and 2) an
output offset error that can be trimmed out with
VOS(R1S) on the output op amp.

Extended Range Divider (Figure 8)
The only cross-product error of interest is the Vz
feedthrough (Vx = 0 and Vosx 0) which is easily
adjusted with Xos(R5).

*

Resistor product mismatch will cause scaling errors
(gain) that could be a problem for very low values of Vz.
Adjustments to YOS(R18) can be made to improve the
high gain accuracy.

Square Root and Squaring (Figures 10
and 12)
These circuits are functions of single variables so
feedthrough, as such, is not a consideration. Cross
product errors will effect incremental accuracy that can
be corrected with Yos(R14) or Zos(R10).

A residual offset will probably remain which can be
trimmed out with VOS(R1S) at the output of amp.

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

..

3-885

I

RC4200
therefore, the rms value of AsinCilt becomes:

Appendix 2 - Applications

A

Design Considerations for RMS-to-DC
Circuits

Vrms~

Average Value

RMS Value for Rectified Sine Wave

Consider Vin = Asinrot. By definition,

Consider Vin = IA sin CIltl, a rectified wave. To solve,
integrate of each half cycle.

~ fo~

VAG =

VINdt

i.e.

=Period

Where T
(J)

~

=

27tf
27t
=
T

~A

"
I
I

\

, ...

I
\

I

I
\1

o

T

"

\

\

f Sot
~T

Virf dt =

A2sin 2cot dt +

This is the same as

\

+faT

Ii

(-ASinCllt)2dt ]

A2sin2rot dt

so, IAsinClltlrms = AsinClltrms

T

""2

VAG =

[Io~

+JoT

65-1873

Asincot dt

[-.!.co cos rot ] f

Practical Consideration: IAsinCiltl has high-order
harmonics; AsinCilt does not. Therefore, non-ideal
integrators may cause different errors for two
approaches.

0

= ~ [-cos (It) + cos(O))

2lI:

Average Value of Asinrot is

v..

~
A
It

(a)

RMSValue
Again, consider VIN = Asincot

Vrms = VVAVG· =

vlN

{.1.1
T 0

T

[VIN12dt
(b)

Vrms for Asincot dt:
Vrms =

Vrms

{..!. rr A2sin2cot dt

[1 1cos 2 cos 2 cot]dt
0 2 2

=IA21T
- -T

I A2[ T
Vrms = V- 2

Vrms = {
Vrms

3-886

Avg

TJo

2

- -1

4co

sin2mt

[V~:2]

65-1872

= Vo

Implies Vo = y'-A-vg-(-IV-IN"""21-)
Vo =

VAvg VIN2

]T
0

~2 [~ ]

Figure 15

=~
2
Raytheon Semiconductor

For More Information, caJI1-800-722-7074.

RC4200

VIN

lOOK

300K

300K

167K

lOOK

200K

5
13.3K

RC4200A
Multiplier

RC4200A
Multiplier

Xl

Vx

50K

250K'

4
2

60K

~-.........

-vs
83.3K

80K

1_5K-,3'1 10~Kr---~+fl0K

..

100

!

-Vs

'Determines sacle lactor (K) lor X2 lunction.
"Determines sacIe lactor (K) lor {X lunction.
65·1869

+11. - +VREF - +15V
-Vs - -15V

Figure 16. RMS to DC Converter VOUT
Amplitude Modulator wHh A.G.C, (Figure 17)

In many AC modulator applications, unwanted output
modulation is caused by variations in carrier input
amplitude. The versatility of the RC4200 multiplier can
be utilized to eliminate this undesired fluctuation. The
extended range multiplier circuit (Figure 5) shows an
output amplitude inversely proportional to the reference
voltage VREF.

By making VREF proportional to Vy (where Vy is the
carrier input) such that:
VREF = VH =I(lVyll,
Then the denominator becomes a variable value that
automatically provides constant gain, such that the
modulating input (Vx) modulates the carrier (Vy) with a
fixed scale factor even though the carrier varies in
amplitude.

For More Information, call 1-800-722-7074.

==JIVT

If VH is made proportional to the average value of Asinrot
(i.e., 2Aht) and scaled by a value of 7tl2 then:
VH=A
and if: Vx = Modulating input (VM)
and: Vy = Carrier input (Asinrot)
Then: Va = K VM sin rot where K = ::~
The resistor scaling is determined by the dynamic range
of the carrier variation and modulating input.
The resistor values are solved, as with the other
extended range circuits, in terms of the input voltages.
Input voltages:
Modulation voltage (VM): 0 ~ VM ~ Vx(max.)
Carrier (Vy): Vy = Asinrot
Carrier amplitude fluctuation (M):
A(min.) sint ~ Vy ~ A(max.) sinnot
Dynamic Range (N): A(max.)/A(min.),
A(max.) = VH(max.) and (A(min.) = VH(min.)

Raytheon Semiconductor

3-887

I

RC4200
R"
R1

+'4.

At,
8

30K

7

10K
RC4200

-V.

RO

+-¥A,-------,

Il.IttlpU.r
R2

v. _

C>-1>--+--.Jv\i~--4----=-I
Aswmt
+V.

30K

4

10K

r ..........-o

VoV.. slnm1

·V.

·V.

'::"

R1
R2
R3
30K

C1

470

+

R3
30K

VH - iAVGIASlnm11-A

85-1866

Figure 17. Amplitude Modulator with AG.C.
The maximum and minimum values for 11 and 12 lead to:

Example #1

11 (max.) = VX(max.) +VH(max.) = 250 j.tA
R1
Ra

Vy =Asincot 2.5V SA S 1OV, therefore N =4
OV SVM S 10V, therefore Vx(max.) = 10V
K = 1, therefore Vo = VM sincot

.
VH(min.)
11(mln) =
Ra
= 50 j.tA VM(min.) = 0
12(max) = A(max.)
R2
12(min.) =

VH~in.)

+VH(max.)
Ra

=250 j.tA

= 50 j.tA

R - Vx(max.) - ~ = 200K
1 - 50j.tA
- 50j.tA
A(max.)
R1 = 50j.tA

= 50j.tA

10V

R A(min.)
a = 50j.tA

= 50j.tA

= 200K

2.5V
= 50K

For a dynamic range of N, where
A(max.)
N= A( min.
.)

<5,

Ro -K
-

R1R2
Ra

-1
-

200K x 200K
= BOOK
50K

These equations combine to yield:
Vx(max.)
A(max.)
R1 = (5 -N)50j.tA' R2 (5 -N)50j.tA'
R _ A(min.)
a - 50j.tA

3·888

Example #2
Vy = Asincot 3 S A S 6, therefore N = 2
OV S VM S BV, therefore Vx(max.) = BV
K =.2, therefore Vo =.2 VM sincot
so:
R1 = 53.3K, R2 = 40K
Ra = 60K and Ro = 7.11K

Raytheon Semiconductor

For More Information, call 1-800·722·7074.

RC4200
Inputs
Vz

-

A1

Vx

-

11

As

14

7
RC4200
Multiplier
-Vs
Vy

~

g.1

-

-

I C

-Vs

':'

~

As

Cs ~ 0.111F

+Vs

100~

Ao

F

!

A4

5

Cs ~ O.1I1F

+Vs

+Vs

V0S4ADJ

8

VOS2

4

Output
>-~-{)

2

Vo

Io.1I1F -Vs

As = 10K, Cs = 0.00511F
-Vs
65-1867

Figure 18. First Quadrant MultiplierlDivider

Limited Range, First Quadrant Applications

The following circuit has the advantage that crossproduct errors are due only to input offsets and
nonlinearity error is slightly less for lower input currents.
The circuit also has no standby current to add to the
Mise content, although the signal-to-noise ratio worsens
at very low input currents (1-5 pAl due to the noise
current of the input stages.
The RSCS filter circuits are added to each input to
improve the stability for input currents below 50 pA.
caution

The bandpass drops off significantly for
lower currents «50 pAl and nonsymmetrical rise and fall times can cause
second harmonic distortion.

For More Information, call 1-800-722-7074.

Thermal Symmetry

Thermal
Symmetry
Line

-Vs

Gnd

Output 13
65-2775

The scale factor is sensitive to temperature gradients
across the chip in the lateral direction. Where possible,
the package should be oriented such that sources
generating temperature gradients are located phYSically
on the line of thermal symmetry. This will minimize
scale-factor error due to thermal gradients.

Raytheon Semiconductor

3-889

I

RC4200

-

5 250

+3
dc

Vz

+1

1'1

m
:Eo ·1

..S.

·3

:s
0 ·5
Vo

~

·7

~

;!
• Peak to Peak

·9
·11
10

102

10'
Frequency (Hz)

Vx

250 IlAdc B

-

5 250

de

Vz

_

+1

III

:Eo ·1
'5

1\

~ -3

Vy
Vo

o

.5

i

·7

~

8!
• Peak to Peak

·9

·11

':'

10

Vx

250 IIA de B

102

10'

10'
10·
Frequency (Hz)

10'

10 7

+3
ac·
-167 IIA de

5 83.4

Vz

+1

m

..

1\

:Eo ·1
:s
~ ·3
o .5

Vy

~

Vo

-

~

'iii

·7

a: ·9

• Peak to Peak

I/)

l8

~

·11

':'

10

102

10'
10'
10'
Frequency (Hz)

10'

10 7

Figure 19

3-890

Raytheon Semiconductor

For More Infonnation. call 1-800-722-7074.

RC4200

250 ,..---r-r----'7-..---"""7'T----".

~

150

1--~'--+7"---?"'f-_7"<;...-....,p.C-_r_-I

.;t

100

1:11

~

i

~

250

Figure 20a. Output Noise Current (I) vs. Input Currents (I•• I,l
for ~ = 250 IlA

Figure 20a. Output Noise Current (IJ vs. Input Currents (I,. IJ
for I•• 250 IlA

.c

200

1, ( 1lA)

12 ( 1lA)

i

150

250

,..--~-_._--..--__r-__r----,

200
150 t---+-100
50

I--"I"""'~

I---I--of-"::::::=+-

~

O'---....L---'-_-J..._--'-_--'_---'~
1.0

10

100

1K

10K

100K

1M

I

Frequency (Hz)
Figure 21. AC Feedthrough vs. Frequency

For More Infonnation. calI1-8OQ..722·7074.

Raytheon Semiconductor

3·891

~
IS

en
(")

r

'"

(5)

11

S

Gnd

(6)0 ,

~101

(7)01

VOS1

0103 ....... , 1#'0104

010~

:::r

CD

r

)

,1

Rl~

0.1

.....

"'vo..Jvl

~H2
0.1

I
I

;6

3
a0"

~02
C3:::::

........ J~.ft.

C

O4ONJ
l ...

Dr

co
iiJ

~JnA"tJ

3

:D

CD

'S
::T
CD

0

II

:l

ffl
3

0'

(2)

:l
Q.
C

VOS!

0

1

~

i Hv ,J _L l~1

t

II ~:t

0

a0

...

;r

f

ig.
?

~

i

~

i:l

:;:!

R206
511
(3)

-Va

85-1848
(1)

~

~

Ci

~

RC4444
RC4444
4 x 4 x 2 Balanced Switching Crosspoint Array

Description

Features

The RC4444 is a monolithic dielectrically isolated
crosspoint array arranged into a 4 x 4 x 2 matrix. The
primary application is for balanced switching of 600n
transmission lines. The ring and tip are selected by
selective biasing of the P+ and P- gate.

•
•
•
•
•
•

Designed to replace reed relays in telephone
switchboards. it does not require a constant gate drive
to keep the SCR in the "ON" condition. It is several
orders faster. with no bouncing. and has a much longer
operating life than its mechanical counterpart.

Low bl-directional RoN
High RoFF
Excellent matching of gates
Low capacitance
High rate firing
Predictable holding current

The 16 SCR pairs with the gating system are packaged
in a 24-pin dual in-line package.

Block Diagram

(21)

-

A2
p+

"
~

A1

p+

( ~)

~

~

~

~

~

~

~

~

~

-~

~

~

(20)

I

!.?)
~

p+

02

~

(6)

C2(

C1

~

~

(1)

82

81

~

(!)

~

~

~

~

r~

~

~

(18)
(~)

p+ "
(
01
(16)

!J

Df. .~

(

(4) (3) (9)
Z2 p- Z1

For More Information, call 1-800·722·7074.

>f:

~

~

r~

(

(2) (10)(11)
Y2 P- Y1

>f:

~

(

(24)(23)(13)
X2 P- X1

Raytheon Semiconductor

(22)(14)(15)
W2 P- W1

65-2413

3-893

RC4444
Absolute Maximum Ratings

Thermal Characteristics

Operating Voltage ...............................................+25V
Operating Current per Crosspoint ................... 100 rnA
Storage Temperature Range ............. -65°C to +150OC
Operating Temperature Range ............... O°C to +70°C
Lead Soldering Temperature •........................•• +300°C
(60 sec)

24-Lead
Plastic DIP
+125°C
555mW

Notes: 1. Maximum voHage from anode to cathode.

Max. Junction Temp.
Max. Po TA < 50°C
Therm. Res 8JC
Therm. Res. 8JA
For TA > 50°C Derate at

Connection Information

Ordering Information

135°CIW
7.41 mW/oC

Package

Operating
Temperature
Range

N
D

O°Cto +70°C
O°C to +70°C

24-Lead

Dualln·Line Package
(Top View)

Part Number
RC4444N
RC4444D

24-Lead
Ceramic DIP
+175°C
1042mW
60°C/W
120OC/w
8.33mW/oC

Notes:
N - 24-lead 600 wide plastic DIP
D " 24-Lead 600 wide Ceramic DIP

65-0695

Pin

Function

Pin

Function

1
2
3
4
5
6

Anode Al
Cathode Y2
RowSelectZ
Cathode Z
Column Select A
Column Select 8
Column Select C
Column Select D
Cathode Zl
Row Select Y
Cathode Y1
Anode D2

13
14
15
16

Cathode Xl
RowSelectW
CathodeWl
Anode Dl
Anode C2
Anode Cl
Anode 82
Anode 81
AnodeA2
CathodeW2
Row Select X
Cathode X2

7

8
9
10
11
12

3-894

17

18
19
20
21
22
23
24

Raytheon Semiconductor

For More Information, call 1-800-722·7074.

RC4444
Electrical Characteristics
(oae s TA S +70ae unless otherwise specified)

Parameters
Anode-Cathode Breakdown Voltage
Cathode-Anode Breakdown Voltage
Base-Cathode Breakdown Voltage
Cathode-Base Breakdown Voltage
Base-Emitter Breakdown Voltage
Emitter-Cathode Breakdown Voltage
OFF State Resistance
Dynamic ON Resistance
Holding Current
Enable Current
Anode-Cathode ON Voltage
Gate Sharing Current
Ratio at Cathodes
Inhibit Voltage
Inhibit Current
OFF State Capacftance
Tum-ON Time
Minimum Voltage Ramp

Test COndItIons
IAK=25~
IAK=25~
IBK-25~
IKB=25~
IBE=25~
IEK=25~

VAK= 10V
Center Current = 10 rnA
Center Current = 20 rnA
VBE = 1.5V (Fig. 2)
IAK= 10mA
IAK=20mA
Under Select Conditions
with Anodes Open (fig. 1)
VB = 3.0V (Fig. 3)
VB = 3.0V (Fig. 3)
VAK=OV
(Fig. 5)
Which Could Fire the SCR
Under Transient Condftions
(Figure 5)

MIn
25
25
25
25
25
25
100
4.0
2.0
0.9
4.0

0.8
0.8

RC4444
Typ

Max

12
10
3.8
1.0
1.1
1.25
1.25
0.3
0.1
2.0
1.0

800

UnIts
V
V
V
V
V
V

Mn
n

rnA
rnA
V
rnA/rnA
rnA/rnA
V
rnA

pF
J.1S
V/J.1S

I
For More Information, call 1-800-722·7074.

Raytheon Semiconductor

3·895

RC4444
Typical Performance Characteristics
Anode-Cathode on VoHage VS.
Current and Temperature

Holding Current VS. Ambient Temperature

2.0

1

1.6

1:

~ 1.2

:::J

- r-

1.1

>"
......

r-..

"0
0

~

oQ 0.8

0.9

'i

"0
0

V

9CD 0.8

c
:§ 0.4

m

~

CD

~

o

c

<

~

0.7

o

-10 0 10 20 30 40 50 60 70 80 90

~

...... TA=O°C

" ~ '- TA = +25°C

Y=r
o

Ambient Temperature (OC)

2

4

70

0.9

as 0.7

&

...........

Q.

o
024

~ 0.3

~
:g

6 8 10 12 14 16 18 20

en

==

o

0.2
0.1

0
0.1 0.2 0.5 1.0 2

Anode-Cathode Current (rnA)

CD

u

Eas
So
0

6
4

g
1'-

roo-

-

2

.....

~

6 8 10 12 14 16 18 20
Anode-Cathode Current (rnA)

3-896

10

~

8

i
=
u
'j§

6

c

1'-0..

50100

Dynamic on Resistance vs. Ambient Temperature

"-

"

5 10 20

Anode-Cathode Voltage (V)

Dynamic on Resistance vs.
Anode-Cathode Current

"'

i'"

lj 0.4

--

±20

IX:

~

6 8 10 12 14 16 18 20

g 0.6
0.5

S ±40

~
c 10
as
li1/1 8

m

g 0.8

>
.5. ±60

12

-

iL 1.0

.s

±80

....... 14

r

-

Off-sHe CapacHance VS. Anode-Cathode VoHage

±100

9-

-

Anode-Cathode Current (rnA)

Difference In Anode-Cathode on VoHage
(Between Associate Pairs of SCRs)
VS. Anode-Cathode Current

~

-

,.......:: ~ ~

...
,V

.c

-- --~ K--

1.0

CD

-....-

-

I

I

I

..d---t"':
TAK =10mA
r"

I

TAK =20

-

I

I

~

I-

-

IX:

4

~

2

~

o

9

~

:g

-10 0 10 20 30 40 50 60 70 80 90
Ambient Temperature (OC)

Raytheon Semiconductor

For More Infonnation, call HIOO-722-7074.

RC4444
Typical Performance Characteristics (Continued)
Crosstalk vs. Signal Frequency

Feedback VS. Signal Frequency
-60

-60

-70

iii'
~

~

~

a

V

e -100

~

-110

V

~

,

-120

-130
0.1

5

0.5 1.0

II

-90

l/

...e
-110
~ -120
.c -100

i,.;'~

J

-80

.c
CI
::s

I-'

-90

::J

-70

iii'

-80

:il

50100

10

V

-130
0.1

0.5 1.0

5

!

10

50100

Signal Frequency (kHz)

Signal Frequency (kHz)

Test Circuits
4.SmA

=<

11

GHS=

12

~=

65-2415

Figure 1. Test Circuit for Gate Sharing Current Ratio

Figure 2. Enable Current (Both SCRs Must Turn On)

+10V +3.3V V1NH

0--0

R

R

I

Inputs

65-2416

Figure 3. Inhibit VoHage and Inhibit Current (Both
SCRs Must Remain Off)

< +8.SV
<+2.5V

-

Vc & V~

IoN<1I1S
(at 50% Amplitude

Point)

dv/dt Test SRC Must
Tirne < 25 liS Remain Off
dv/dt < SOD/liS 65-2417

Figure 4. Test Waveforms for dv/dt and tan

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-897

RC4444
Test Circuits (Continued)
Clock

0-_...------------.

~-_t_-_...--_.-_t_--

_ __o -10V

Each 1/4 7400

1.2K

1K

L-_ _ _ _ _

o~~

-=-3V

Figure 5. Test Circun for dv/dt and ~

~

65-2418

TA .. +2SoC. VI = 12 dBm, Crosspoints Off
Feedthrough .. 20 Log,o 01oNl)
65-2049

Figure 6. Test Circutt for Feedthrough vs.
Frequency

TA - +2S oC, VI - 12 dBm, Crosspoinst On
Feedthrough - 20 Log 10 (Vrr;.N01)
65-2050

Figure 7. Test Circun for Crosstalk vs.
Frequency
3-898

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4444
Typical Applications
The RC4444 crosspoint switch is designed to provide a
low-loss analog switching element for telephony signals.
It can be addressed and controlled from standard binary
decoders and is CMOS compatible. With proper system
organization, the RC4444 can significantly reduce the
size and cost of existing crosspoint matrices.
SIgnal Path ConsIderations

The RC4444 is a balanced 4 x 4 2-wire crosspoint array.
It is ideal for balanced transmission systems, but may
be applied effectively in a number of single ended
applications. Multiple chips may be interconnected to
form larger crosspoint arrays. The major design
constraint in using SCR crosspoints is that a forward DC
current must be maintained through the SCR to retain
an AC signal path. This requires that each subscriberinput to the array be capable of sourcing DC current as
well as its AC signal. With each subscriber acting as a
DC source, each trunk output then acts as a current
sink. The instrument-to-trunk connection in Figure 8
shows this configuration. However, with each subscriber
acting as a DC source, some method of interconnecting
them without a trunk must be provided. Such a local or
intercom termination is shown in Figure 9. Here both
subscribers source DC current and exchange AC
Signals. The central current sink accepts current from
both subscribers while the high output impedance of the
current sink does not disturb the system.
These configurations are system compatible. The DC
current restriction is not a restriction in the design of an
efficient crosspoint array. Because of the current sink
terminations, a signal path may use differing numbers of
crosspoints in any connection or in two sides of the
same connection further relaxing restrictions in array
design.

For More Infcrmation, call 101100-722-7074.

Figure 10 demonstrates circuit operation. S1, S2 and S3
are open. The Crosspoint SCRs are off as they have not
gate drive or DC current path through S1. By closing S2
and S3, gate drive is provided, but the SCRs still remain
off as there is no DC current path to hold them on. Close
S1 and the circuit is enabled, but with S2 and S3 off
there is still no signal path. Closing S2 and S3 with S1
closed - current is injected into both gates and they
switch on. DC current through RL splits around the
center-tapped winding and flows through each SCR,
back through the lower winding and through S1 to
ground. If S2 and S3 are opened, that current path still
remains and the SCRs remain on. If an AC signal is
injected at either G1 or G2, it will be transmitted to the
other signal port with negligible loss in the SCRs. To
disconnect the AC Signal path, the SCRs must be
commutated off. By opening 81 the DC current path is
interrupted and the SCRs switch off. The AC signal path
is disconnected. With S1 closed, the circuit is enabled
and may be addressed again from S2 and S3. This
circuit demonstrates a balanced transmission
configuration. The transmission characteristics of the
SCRs simulate a relay contact in that the AC signal
does not incur a contact voltage drop across the
crosspoint The memory characteristics of the crosspoint
are demonstrated by the selective application of S1, S2,
and S3.
The selection of RL is governed by the power supply
voltage and the desired DC current If 10 mA is to flow
through each SCR then RL must pass 20 mA. Thus,
(+VS - VAK)/RL = 20 mA. The selection of Rp is
governed by the characteristics for crosspoint turn on.
Adequate enable current must be injected into the
column select and Rp should drop at least 1.5V. The
PNP transistor has a typical gain of one. Thus, Rp
should pass at least 2 mA to provide 4 mA column
select current

Raytheon Semiconductor

3-899

I

RC4444
Addressing Considerations
The RC4444 crosspoint switch is addressed by
selecting and turning on the PNP transistor that controls
the SCR pair desired. The drive requirements of the
RC4444 can be met with standard CMOS outputs. A
particular crosspoint is addressed by putting a logical "1"
on the emitter and a logical "0" on the base of the
appropriate transistor. A resistor in the base circuit of the
transistor is required to limit the current and must also
drop 1.5V to assure forward bias of the two diodes In the
collector circuits.
The gate current required for SCR turn on is 1 rnA
typically. CMOS one-of-n decoders are available that
provide both active high and active low outputs and are
we" suited for standard addressing organizations. The
major design constraint in organizing the addressing

structure Is that any signal path which is to be
addressed must create a DC path from a source to a
sink. If that path requires two crosspoints, they must be
addressed simultaneously. Of course, once the path is
selected, the addressing hardware is free to initiate
other signal paths. To meet the DC path requirement,
crosspoint arrays should be deSigned in block such that
any give DC path required only one crosspoint per
block. A signal path, however, may still use two
crosspolnts in the same block by sequentially
addressing two DC paths to the same terminator. For
example, the left or right pairs of crosspolnts In Figure 9
must be addressed simultaneously but the left pair may
be addressed In sequence after addressing the right
pair. This is not a difficult constraint to meet and it does
not require unnecessary addressing hardware.

Emitter selects
CMOS outputs
+15V

Instrument
500
' - - - - - 0 ·15V

All CMOS operated from
+15V power supply

65-2410

CMOS ouputs base selects

Figure 8. Instrument-to-Trunk Connection

3-900

Raytheon semiconductor

For More Information. caIJ 1-800-722·7074.

RC4444
.-----------~~~~~~~~~~~~----------------~~-----o+15V

Emitter Selects Are Actiw High CMOS Outputs

500

Instrument

CMOS
Buffer

All CMOS logic operated
from +15V power supply

L-_-__-o_15V

65-2420

Figure 9. Typicallnstrument-to-Instrument Connection

51

52

53

Line Condition

On

X
Off

Off

Enabled, Not Connected

On

On

On

X

X

Off

X

X

On
On

W1

W2

G~r~

X

Enabled, Not Connected

I

Addressed and Connected

G1 Connected to G2
Disconnected

X- Don' Care

65-2421

Figure 10. Crosspoint Operation Demonstration Circun

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-901

i

(J)
-"

3

"2..
::;:
iii"

e.
Anode
A1

Anode Anode
A2
B1

Anode Anode
B2
C1

Anode Anode
C2
01

(J)

Anode
02

(')

::s3

CD

1
RowSelee!

a5"

W

0
~"

Cathode

W1

~=r

Cathode
W2

RowSelee!
X

CD

o

::s

fU
3

n
o

a
c
ao

...

Cathode
X1

Cathode

X2

RowSelee!

Y
Cathode
Y1

Cathode
Y2

Row Select

Z

g'

f

I

~
~

~
~

fo!

Cathode
Cathode

Z1

Z2
Column
Select

Column
Select

A

B

Column
Selee!
C

Column
Select

o

65-2412

DJ
3

PROMs
PROMs
Ao-A12

_ - - - - - - - - - - - - - - 3.0V

_ . _ - - - - - - - - - - - - - - - - 1~V

' - - - - - - - - - - - _ _ _ _ OV

3.0V

-+------~I'_"""T--~r_"""T- 1.5V

° -0.
0

--"**"*+If---:~*---_ttttt-

OV
VOH

1.5V

VOL

Keys to Timing Diagram
Waveforms

Inputs
Must be

Will be

Steady

Steady

Don't Care.
Any Change
Permitted

Changing State
Unknown

DoeaNot
Apply

Center Une la
High Impedance
OffStste

Raytheon Semiconductor bipolar PROMs feature full
Schottky clamping and three-state outputs. The devices
are available in four- and eight-bit wide JEDEC standard
configurations. The PROMs employ nichrome fuse links,
which store a logical HIGH and are programmed to a
LOWstate. Chip select inputs provide logic flexibility and
ease of memory expansion decoding. The devices
contain an internal test row and column, which are
accessed and programmed during wafer sort test. These
fuses ensure a high programming yield and guarantee
AC performance and DC parameters.
Raytheon Semiconductor's PROM series includes
standard performance and power-switched versions.
The devices are available in different speed and
package options.

Outputs

Raytheon Semiconductor's memory products have a
high immunity, or resistance, to total dose, neutron
fluence and dose rate radiation. Our memory products
are well-suited for military and aerospace applications.
Screening Options Available:
• Level S
• JAN Class B
• Standardized Military Drawing (SMD)
• Class B
• Source Control Drawing (SCD)
• Military Temperature Range
• Commercial Temperature Range
Raytheon offers JAN and Standardized Military Drawing
product as off-the-shelf devices, on a direct OEM basis
or through distributors.

I
For More Information, call 1-800·722-7074.

Raytheon Semiconductor

3-903

PROMs
PROM Selection Guide

Product
Size
R29621/1A 4K
R29623I3A 4K
R29631/1A 8K

Organization Enable (1)
512X8
CS
512X8
PS
CSt, CS2
1024X8
CS3, CS4

R2963313A

1024X8

8K

Outputs
TS
TS
TS

PS',~

TS

PS3, PS4

R29651/1A 8K
R2965313A
8K
R29681/1N 16K

2048X4
2048X4
2048X8

CS

TS
TS
TS

PsCS'
CS2, CS3

R2968313A2 16K

2048X8

PSt
fiS2, PS3

TS

R29771

32K

4096X8

CSt, CS2

TS

R29773

32K

4096X8

PSt, PS2

TS

R29791

64K

8192X8

TS

R29793

64K

8192X8

TS

Raytheon
Package MIL-STD-1835
9,IC
Designator case Outline "CIW
0
0-8
<11
0-8
0
<11
0
0-3
<11
L
c-4
<10
F-6
F
<10
0-3
0
<11
L
C-4
<10
F
F-6
<10
0-6
0
<11
0-6
0
<11
0-9
S
<11
0-3
0
<11
C-4
L
<10
0-9
S
<11
0
0-3
<11
L
C-4
<10
0-9
S
<11
0
0-3
<11
C-4
L
<10
F
F-6A
<10
0-9
S
<11
0-3
0
<11
L
C-4
<10
F
F-6A
<10
0-9
S
<11
0-3
0
<11
F
F-64A
<10
0-9
S
<11
0-3
0
<11
F-6A
F
<10

Max ICC
Power
Supply
Current
155mA

MaxICCD
Power Down
Supply
Current
45mA

170mA

45mA

170mA
45mA
180mA

50mA

190mA

55 mA

190mA

50mA

Notes:
1. CS/CS = Chip Select for PROM
PSIPS = Chip Select for SPROM
2. Contact Factory regarding flat pack package.

JAN Ordering Information
MIL-M-385l0 Slash Sheet Part Number
Raytheon Part Number
MIL-M-385l0/20902BVA .................................................................JR29651DQ (2K X 4, l8-pin ceramic DIP)
MIL-M-385l 0I20904BJA ...•..•....•..••.••..•..•....•....•.••.•.•....•..•••.••.•..•.•••. JR29631 DR (1 K X 8, 24-pin ceramic DIP)
MILOM-3851 0/21 002BJA .................................................................JR29681 DR (2K X 8, 24-pin ceramic DIP)
Raytheon Semiconductor CAGE Code - 07933
3-904

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

R296XX1R297XX
R296XX1R297XX

Standard PROMs and Power-Switched SPROMs

Description

Features

Raytheon Semiconductor's Bipolar Reid Programmable
Read-Only Memories include both standard and powerswitched versions. Cs/PS inputs provide logic flexibility
and ease of memory expansion decoding. SPROM
power-switch circuitry is activated by the PS input.

•

Raytheon PROMs and SPROMs are manufactured with
nichrome fuses and low power Schottky technology. The
devices are shipped with all bits in the HIGH (logical
ONE) state. To achieve a LOW state in a given bit
location the nichrome link is fused open by passing a
Short, high current pulse through the link. All devices are
programmed using the same programming technique.
Standard PROMs are enabled by a single active LOW
CS or by both active LOW CS and high CS inputs.
Power-switched PROMs (SPROMs) are enabled by a
Single active LOW PS or by both active LOW PS and
HIGH PS inputs. See the individual block diagrams for
the enable scheme.

•
•
•
•
•
•
•
•
•

Applications
•
•
•
•
•
•
•
•

For More Information. call 1-800·722·7074.

Devices are available in military (-55°C to +125°C)
temperature range
Standard PROMs are offered in power-switched
SPROM versions
Typically, 75% power savings achieved by
deselected SPROMs
Reliable nichrome fuses
Three-state outputs
Devices programmed on standard PROM
programmers
High immunity or resistance to high levels of
constant or burst radiation
Device pinouts comply with JEDEC standards
Available in surface mount and through-hole
packaging
PROMs and SPROMs are offered in 24-pin, 0.3"
wide DIPs

Microprogram control store
Microprocessor program store
Programmable logic
Custom look-up tables
Security encoding/decoding
Code converter
Character generator
Use in redundant systems

Raytheon Semiconductor

I
3·905

R296XX1R297XX
Absolute Maximum Ratings
(above which the useful life may be impaired)
Supply Voltage to Ground Potential (continuous), Vre ......................................................................................................................................... -C.5V to +7.0V
DC Input Current .................................................................................................................................-30 rnA to +5.0 rnA
DC Input Voltage (address inputs) .............................................................................................................-C.5V to +5.5V
DC Input Voltage (chip/power select input pin)
R296XX ................................................................................................................................................-0.5V to +33V
R297XX ................................................................................................................................................-0.5V to +28V
DC Voltage Applied to Outputs (except during programming) ............................................................. -0.5V to +Vre max.
Output Current into Outputs During Programming ................................................................................................240 rnA
DC Voltage Applied to Outputs During Programming
R296XX ...............................................................................................................................................................26V
R297XX ...............................................................................................................................................................24V
Junction Temperature ...........................................................................................................................................+175°C
Storage Temperature ...............................................................................................................................,65°C to +150°C
Programming Temperature ..................................................................................................................................25 :f;5°C
Lead Temperature (soldering, 10 seconds) .............................................................................................................30000
Current Density (metallization) ...................................................................................................................< 5 x 1OSA/cm2
Thermal Resistance, Junction-to-Case 0JC
Dual-In-Une ................................................................................................................................................s 11°Cm
Leadless Chip Carrier .................................................................................................................................s 10°Cm
Flat Pack ......................................................................................................................................................S1 o°cm

Operating Conditions
Military
Parameter

Description

Min.

Max.

Unit

Vee

Supply Voltage
Case Operating Temperature

5.5
+125
0.8

V

Te
V1L1 l

4.5
-55

V1H l

DC/Functional High Level Input Voltage

V1L

AC Low Level Input Voltage

V1H

AC High Level Input Voltage

DC/Functional Low Level Input Voltage

2.0

V
V

0

3.0

°C

V
V

Note:
1. Functional tests shall be conducted at input test conditions as follows: V1H =V,H(min) +20%, -0%; V1L =V1L(max)
+0%, -50%. Devices may be tested using any input voltage within this input voltage range but shall be guaranteed
to V,H(min) and V1L(max). CAUTION: To avoid test correlation problems, the test system noise (e.g., testers,
handlers, etc.) should be verified to assure that V,H(min) and V1L(max) requirements are not violated at the device
terminals.

3-906

Raytheon Semiconductor

For More Information. call 1-800·722·7074.

R296XX!R297XX
Electrical Characteristics
Over Operating Range
Devices conform to MIL-STD-883, Group A, Subgroups 1, 2 and 3
Parameter

Description

Test Conditions

Min

VOH

Output High Voltage

Vee = Min, 10H = -2 mA
VIN = VIH or VIL

2.4

V (1)
OL

Output Low Voltage

Vee = Min,

IOL =8 mA

0.4

VIN = VIH or VIL

10L = 16 mA

0.5

R296XX

-250

R297XX

-100

IL

Input Low Current

I'H

Input High Current

Vee;; Max, VIN ;; O.4V

Max

V

Vcc = Max, VIN = 2.7V

10

Vee = Max, VIN = 5.5V

40

I (2)
os

Output Short Circuit
Current

Vee = Max, VOUT = 0.2V(3)

VIC
IcEX

Input Clamp Voltage

Vee = Min, liN = -18 mA

Output Leakage Current

Vee = Max,
Chip Disabled

-15

Units

V

~
~

-85

mA

-1.2

V

VouT =.5.5V

+40
-40

~

VOUT= 0.4V

Notes:
1. This characteristic cannot be tested prior to programming; it is guaranteed by factory testing.
2. Not more than one output should be shorted at a time. Duration of the short circuit should not exceed 1 second.
3. Voor = O.OV for R297911R29793
4. Typical CIN =5 pF

Pin Names
Symbol

Description

AD-A"

Address Inputs

CS

Chip Select Active Low (PROM)

CS

Chip Select Active High (PROM)

PS

Chip Select Active Low (SPROM)

PS
01_0n

Chip Select Active High (SPROM)

I

Data Outputs

For More Information. caJll-8()()·722·7074.

Raytheon Semiconductor

3-907

R296XX1R297XX
512 x 8 PROM - R29621/R29621 A
Power and AC Characteristics Over Operating Range
ICC conforms to MIL-STD-883, Group A, Subgroups 1, 2 and 3
AC parameters conform to MIL-STD-883, Group A, Subgroups 9,10 and 11
Maximum LImits
Parameter Description

Test Conditions

Units

29621 AM

R29621M

155

155

rnA

CL = 30 pP,

60

80

ns

Enable Access Time

R1 = 300n to Vee

40

40

ns

Enable Recovery Time

R2 = 600n to GND, 16 rnA Load

lee

Power Supply Current

Vee = Max

tM

Address Access Time

tEA
tER
PD

All Inputs GND

Power Dissipation

40

40

ns

853

853

mW

·See AC Test Load Circuit and Switching Waveforms

Block Diagram

Ordering Information
Part Type

Package

R29621DM
R29621 DM/883B
R29621DMS
R29621 ADM
R29621 ADMl8838
R29621ADMS

Operating Temperature
Range

D
D
D
D
D
D

-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +12500
-55°C to +125°C
-5500 to +125°C

Notes:
/883B suffix denotes MIL-8TD-883, Level B processing
S suffix denotes Level S processing
O. 20-/ead ceramic DIP

2

17

10164
Decoder

A2--------------~
Aa ______________4:%..1
A ______________......
5
4

cs ___1.:..;;50[>

Pin-Out Information

1018
Multiplexers
(8)

Output
Drivers (8)

Dual In-LIne Package
P'NfIt

.........

00000000

BS-0112

Pin 15 is also the programming pin (pp)
65-1314

3-908

Raytheon Semiconductor

For More InJonnalion, caJI1-800·722·7074.

R296XX1R297XX
512 x 8 SPROM - R29623/R29623A
Power and AC Characteristics Over Operating Range
ICC conforms to MIL-STO-883, Group A, Subgroups 1, 2 and 3
AC parameters conform to MIL-STO-883, Group A, Subgroups 9, 10 and 11
Maximum Limits
Parameter Description
Power Down, Supply
leeo
Current (disabled)

Test Conditions

R29623AM

R29623M

UnHs

Vee = Max
PS = V1H , All other
inputs=GND

45

45

rnA

Icc

Supply Current
(enabled)

Vee = Max
All inputs = Gnd

155

155

mA

tM

Address Access Time

CL = 30 pF·

60

85

ns

tEA

Enable Access Time

R1 = 300n to Vee

65

85

ns

tEA

Enable Recovery Time

R2 = 600n to GND, 16 rnA Load

40

40

ns

Po

Power Dissipation
(Disabled)

248

248

mW

Po

Power Dissipation
(Enabled)

853

853

mW

·See AC Test Load Circuit and Switching Waveforms

Ordering Information
Part Type

Package

R29623DM
R29623DMl883B
R29623DMS
R29623ADM
R29623ADMl883B
R29623ADMS

Block Diagram

Operating Temperature
Range

D

D
D
D
D
D

-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55OC to +125°C

Ao

Al

2

As
A.

16 1 of 64
17 Decoder

A7

18

A.

19

......._ . . 1

Az ______________~3,

Noles:

/8838 suffix denotes MIL-STD-883. Level 8 processing
S suffix denotes level S processing
D - 20-lead ceramic DIP

A3 ______________

~4~

A4 ______________

~5,

1018

Multiplexers
(8)

Pin Out Information
Dual In-Line Package
Output

ps _ _ _-'1'-'i5:l1

Drivers (8)

_

N

.......

CD'"

•

00000000
85-0113

Pin 15 is also the programming pin (pp)

For More Infoonalion. call 1-800-722-7074_

65-1316

Raytheon Semiconductor

3-909

R296XX1R297XX
1024 x 8 PROM - R29631/R29631 A
Power and AC Characteristics Over Operating Range
ICC conforms to MIL-STO-883, Group A, Subgroups 1, 2 and 3
AC parameters conform to MIL-STO-883, Group A, Subgroups 9, 10 and 11
Maximum limits
Parameter Description
Power Supply Current
lee

Test Conditions
Vee = Max
All inputs = Gnd

R29631AM

R29631M

170

170

Units
mA

CL =30 pF*

60

90

ns

tM

Address Access Time

tEA

Enable Access Time

R1 = 300n to Vee

40

40

ns

tER

Enable Recovery Time

R2 = 600n to GND, 16 rnA Load

40

40

ns

Po

Power Dissipation

935

935

mW

·See AC Test Load Circuit and Switching Waveforms

Ordering Information
Part Type

OperatIng Temperature
Range

Package

R29631DM
R29631 DMl883B
R29631DMS
R29631FM
R29631 FM/883B
R29631FMS
R29631 ADM
R29631ADM/883B
R29631AFMS
R29631 ADM
R29631AFMl883B
R29631AFMS

Block Diagram

D
D
D
F
F
F
D
D
D
F
F
F

-55°C to +125°C
-5500 to +125°C
-5500 to +125°C
-55°C to +125°C
-55°C to +125°C
-5500 to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C

A4

As
As
A7
As
As

4
3
2

10164
Decoder

23
22

Ao
AI
A2
A:J

Notes:
I883B suffix denotes MIL-5TD-883, Level B processing
S suffix denotes Level S processing
D - 24-lead .600 wide ceramic DIP
F - 24-lead ceramic flat pack (cerpak)

6
5

10116
Multiplexers
(8)

Output
Drivers (8)

... C\lC'J ..

It)"' ....

co

00000000

Pin Out Information

65-0116

Dual-ln-Line/Flat Pack Package

vee

A.

1

2

A7 A.

3

4

A.

A. A. A.

5

S

7

S

9

10

11

A,

Ao

0,

O.

O. Gnd

Pin 20 Is also the programming pin (pp)

3-910

12

86-4069

Raytheon Semiconductor

For More Infonnation. call 1-800-722-7074.

R296XX1R297XX
1024 x 8 SPROM - R29633/R29633A
Power and AC Characteristics Over Operating Range
ICC conforms to MIL-STO-883, Group A, Subgroups 1, 2 and 3
AC parameters conform to MIL-STO-883, Group A, Subgroups 9,10 and 11
Maximum LImits
Parameter Description
Power Down, Supply
Icco
Current (Disabled)
Supply Current
Icc
(Enabled)
t
Address Access Time
Enable Access Time
t.,
Enable Recovery Time
t.R
Power Dissipation
Po
(Disabled)
Power Dissipation
Po
Enabled

Test Conditions
Vcc = Max, PS = VIH ,
All other Inputs = GND
Vcc = Max
All inputs = GND
CL=30pP
R1 - 3000 to Vcc
R2 - 6000 to GND, 16 rnA Load

R29633AM

R29633M

45

45

Units
mA

170

170

rnA

70

90

ns

70
40
248

115
40
248

ns
ns
mW

935

935

mW

• See AC Test Load Circuit and Switching Waveforms

Ordering Information
Part Type

Package

R29633DM
R29633DMl8838
R29633DMS
R29633FM
R29633FMl8838
R29633FMS
R29633ADM
R29633ADM/8838
R29633ADMS
R29633AFM
R29633AFMl8838
R29633AFMS

Operating Temperature
Range

o

o
o
F

F
F
D
D

o
F

F

F

-55°C to +1250C
-55OC to +1250C
-55°C to +125°C
-55°C to +125°C
-55OC to +125OC
-55°C to +125°C
-55°C to +125°C
-55°C to +1250C
-55°C to +125°C
-55OC to +125°C
-55°C to +1250C
-55°C to +125°C

Block Diagram
4,------,
3

2 10164
1 Decoder

Ao,-------~

A1 _ _ _ _ _ _ _-':7..,
A2 _ _ _ _ _ _-'6....,
5

10116
Multiplexers
(8)

~----------~L-~~~

Notes:
J883B suffix denotes MIL-5TD-883, Level B processing
S suffix denotes Level S processing
o = 24-lead _600 wide ceramic DIP
F • 24 lead ceramic flat pack (cerpak)

Pin Out Information

Output
Drivers (8)

910111314151617
-NC').",.o,....

00000000
Dualln-UneJFlat Pack Package

Pin 20 Is also !he programming pin (pp)

For More Information, call 1-800-722-7074_

65-0117

6!>4071

Raytheon Semiconductor

3-911

I

R296XXIR297XX
2048 x 4 PROM - R29651/R29651 A
Power and AC Characteristics Over Operating Range
ICC conforms to MIL-STO-883, Group A, Subgroups 1,2 and 3
AC parameters conform to MIL-STO-883, Group A, Subgroups 9, 10 and 11
Maximum Limits
Parameter Description
Power Supply Current
Icc
tM

Address Access Time

Test CondHlons
Vee =Max
All inputs =Gnd

R29651AM

R29651M

170

170

Units
rnA

70

90

ns

CL =30 pF·

=300n to Vee

tEA

Enable Access Time

R1

tEA
PD

Enable Recovery Time

R2 =600n to GND, 16 rnA Load

Power Dissipation

45

50

ns

45

45

ns

935

935

mW

·See AC Test Load Circuit and Switching Waveforms

Ordering Information
Part Type

Package

R29651DM
R29651 DM/SS38
R29651DMS
R29651 ADM
R29651 ADM/8838
R29651ADMS

Operating Temperature
Range

D
D
D
D

D
D

-55"C to +125°C
-55°C to +125°C
-55"C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C

Notes:
J8838 suffix denotes MIL-STD-883, Level 8 processing
S suffix denotes Level S processing
D • IS·lead wide ceramic DIP

Block Diagram
As
As

2
1

A7

17
16

As
As
AIO

10164

Decoder

15

AO--__________~r---~--~
A_
l -_
--_
- -_
-' '--'7~
'-I
A2
_
_

Pin Out Information

A3 _ _ _ _ _ _ _ _~4~

Dual In-Line Package

A4------~~

Os ____-'1;..;..0Q

Pin 10 is also the programming pin (pp)

3·912

10132
Multiplexers
(4)

_ _~_~

Output
Drivers (4)

6!i-1324

Raytheon semiconductor

For More Information, call 1-800-722·7074.

R296XX1R297XX
2048 x 4 SPROM -- R29653/R29653A
Power and AC Characteristics Over Operating Range
ICC conforms to MIL-STD-883, Group A, Subgroups 1, 2 and 3
AC parameters conform to MIL-STD-883, Group A, Subgroups 9,10 and 11
Maximum L1mhs
Description

Test Condhlons

R29653AM

R29653M

leeo

Power Down, Supply
Current (disabled)

Vee = Max
PS = V1H, All other
inputs = GND

45

45

Unhs
mA

Icc

Supply Current
(enabled)

V =Max
Aifinputs = Gnd

170

170

rnA

tM

Address Access Time

CL = 30 pF"

75

90

ns

tEA

Enable Access Time

R1 = 300n to Vee

80

95

ns

tEA

Enable Recovery Time

R2 = 600n to GND, 16 rnA Load

45

45

ns

Po

Power Dissipation
(Disabled)

248

248

mW

Po

Power Dissipation
(Enabled)

935

935

mW

Parameter

"See AC Test Load Circuit and Switching Waveforms

Ordering Information
Part Type

Package

R29653DM
R29653DMl8838
R29653DMS
R29653ADM
R29653ADMl8838
R29653ADMS

Block Diagram

Operating Temperature
Range

D
D
D
D
D
D

-55°C to +125°C
-55°C to +1250C
-55OC to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C

A7

17

10164

Aa
Ag

16
15
8

Decoder

A,o

AO------------~--~~--I

Al------~;
A2
______
~;

Notes:
/B83B suffix denotes MIL-STD-883, Level B processing
S suffix denotes Level S processing
D • IS-lead wide ceramic DIP

A3------~;

A4------~~__-r~__~

Pin Out Information
Ps ____"""'1:.::.001

Dual In-Line Package
Vee A7

10132

Muttlplexers
(4)

Output

Drivers (4)

As Au

Pin 10 is also the programming pin (pp)
65-1326

For More Information, call HlOO-722-7074.

Raytheon Semiconductor

3-913

R296XXIR297XX
2048 x 8 PROM - R29681/R29681 A
Power and AC Characteristics Over Operating Range
ICC conforms to MIL-STO-883, Group A, Subgroups 1, 2 and 3
AC parameters conform to MIL-ST0-883, Group A, Subgroups 9, 10 and 11
Parameter

Maximum Limits

Icc

Description
Power Supply Current

Test Conditions
Vee = Max
All inputs = Gnd

tM

Address Access Time

R29681AM

R29681M

Units

180

180

rnA

CL =30pF·

70

100

ns

tEA

Enable Access Time

R1 = 300.0 to Vee

45

50

ns

tOR

Enable Recovery Time

R2 = 600.0 to GND, 16 rnA Load

35

45

ns

Po

Power Dissipation

990

990

mW

·See AC Test Load Circuit and Switching Waveforms

Pin Out Information

Loadl... Chip Clrrler (28oT"mI..~

A. At ArNCVcoA. '"

~:D···'"'''' ::&

Ordering Information
Part Type

Package

R29681DM
R29681DM/883B
R29681 OMS
R29681LM
R29681 LM/883B
R29681LMS
R29681SM
R29681SM/883B
R29681SMS
R29681 ADM
R29681ADMl883B
R29681ADMS
R29681ALM
R29681ALM/883B
R29681 ALMS
R29681ASM
R29681 ASM/883B
R29681 ASMS

o
o
o
L

L
L

S
S
S

o
o
o
L
L
L

S
S
S

Operating Temperature
Range
-55°C to +1250C
-55°C to +1250C
-55OC to +1250C
-55°C to +1250C
-55°C to +125°C
-55°C to +1250C
-55°C to +125°C
-55°C to +1250C
-55°C to +125°C
-55°C to +125°C
-55OC to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C

Notes:
I883B suffix denotes MIL-STD-883, Level B processing
S suffix denotes Level S processing
D • 24-lead .600 wide ceramic DIP
L - 28-terminal ceramic leadless chip carrier
S • 24-lead .,300 wide side-brazed ceramic DIP
Contact factory regarding flat pack package

ca.

At .,

:III

AI •

21 CI:I
ZI NC
II a.
0,

At ,

NO 1.

1.

0. tt
tzg1 ... I117 "

....... _

q, q, .... NOo.o,o,

... _ _ plnll>Pl
_I~..U ..

Annable In 0.:1" InII o.r WIde Pooklgn
\tc AI At AtO el1 CS12 C83 OJ 01 Oa 01 04
,.

t

'4 "

•

11

"

"

. . . . . . . . At .. otOZOZ ....
... 20 .. " ..... _ _ plnll>Pl

Block Diagram
A.
As

A.

4.-----,
3

2 101128

A7

1

Aa

23

A.

22

At.

21

Decoder

A. __________~~--~~-,
At __________--1..
7-1
A. __________--"S-t
5

lollS
Multiplexers

A.----------~1-

(8)

__~~~

OUtpul

DrIvers (8)

... fIII . . . . . . . . . . .

00000000
85.0128

3-914

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

R296XX1R297XX
2048 x 8 SPROM - R29683/R29683A
Power and AC Characteristics Over Operating Range
ICC conforms to MIL-STD-883, Group A, Subgroups 1, 2 and 3.
AC parameters conform to MIL-STD-883, Group A, Subgroups 9, 10 and 11.
Paramo
eter
Icco

Maximum Limits
R29683AM
R29683M
50
50

1M

Description
Power Down, Supply
Current (disabled)
Supply Current
(enabled)
Address Access Time

Test Conditions
":!..a:.. =Max
PS =Yttt. All other i~uts =GND
Vcc =Max
All inputs =Gnd
CL =30pF*

tEA

Enable Access Time

R1

tER

Enable Recovery Time

R2 = 600n to GND, 16 mA Load

Po

Power Dissipation
(Disabled)
Power Dissipation
(Enabled)

Icc

Po

=300n to Vee

'See AC Test Load Circuit and Switching Waveforms

Units
mA

180

180

mA

70

105

ns

85

105

ns

45

50

ns

275

275

mW

990

990

mW

Pin Out Information
L1adloa Chip CarrlOr (28-TOnnlnaQ

Ordering Information
Part Type

Package

A. •

:-:-:-:,:';,",:...

D~'

A. •

Operating Temperature
Range

24

D
D
D
L
L
L

5
S
S
D
D
D
L
L
L

S
5
S

-55°C to +125°C
-55°C to +125°C
-55OC to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125OC
-55OC to +125°C
-55OC to +1250C
-55°C to +125°C
-55OC to +125OC
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55OC to +1250C
-55°C to +125°C

Notes:
/8838 suffix denotes MIL-STD-883, level 8 processing
5 suffix denotes level S processing
D .. 24.Jead .600 wide ceramic DIP
L =28-terminal ceramic leadless chip carrier
S • 24-lead, .300 wide side-brazed ceramic DIP
Contact factory regarding flat pack package

Pit

23 Ps.

At'

DPs.

A, II

21 He
20 0-

He 10

R29681DM
R29681 DM/883B
R29683DMS
R29683LM
R29683LMl883B
R29683LMS
R29683SM
R29683SMl883B
R29683SMS
R29683ADM
R29683ADM/883B
R29683ADMS
R29683ALM
R29683ALMl883B
R29683ALMS
R29683ASM
R29683ASM/883B
R29683ASMS

A..

A, 7

O! 11

UJ 0,
1'13

,,,'51117"

q,q.QndNCO.o.o.
Pin 24 Is llso .... P'QSJamming pin (pp)

Du"-In-Lln.
Available In or and 0.... Wid. Pack_g ..
A, At
P$rPSI 0. Or o. 0. 04

Vec

"""Ps,

An 20 Is also the prowammlng pin fAIt

65-4074

Block Diagram
A.

4

A.
A.
A7

3
128.128

A.
A.
A,.-"l..-_...J
A.
8
A, _ _ _ _ _-'7'-1
A.
A.

10116
Muttplexe..
(8)

OUiput
Orivers (8)

00000000
65-0128

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

3-915

R296XX1R297XX
4096 x 8 PROM - R29771
Power and AC Characteristics Over Operating Range
Icc conforms to Mll-STO-883, Group A, Subgroups 1,2 and 3. AC parameters conform to Mll-STO-883, Group A,
SubaroUDS 9 10 and 11
Maximum LImits
Parameter

Description

Test CondHlons

Icc

Power Supply Current

t~

tEA

Address Access Time
Enable Access Time
Enable Recovery Time

Vee" Max
All Inputs GND
CL =30pF*
R1 = 300a to Vee
R2 = 600a to GND
16 mA load

Po

Power Dissipation

tEA

·See AC Test Load Circuit and Switching Waveforms

R29771M
190

UnHs
rnA

65
35
35

ns
ns
ns

1.04

W

Pin·Out Information
Lod_ Chip carrier (280T.rmlna~
At;

Part Type
R29771DM
R29771 DMI8838
R29771DMS
R29771FM
R29771 FMI8838
R29771FMS
R29771lM
R29771lMl8838
R29771lMS
R29771SM
R29771 SMI8838
R29771SMS

Package
D
D
D
F
F
F
l
l
L

S
S
S

Operating Temperature
Range

-55"C to +125"C
-55"C to +125"C
-55"C to +125"C
-55"C to +125°C
-55°C to +125"C
-55°C to +125"C
-55°C to +125"C
-55"C to +125"C
-55"C to +125"C
-55"C to +125"C
-55"C to +125°C
-55°C to +125°C

Notes:
/883B suffix denotes MIL-STD-883, Level B processing
S suffix denotes Level S processing
D • 24-lead .600 wide ceramic DIP
F • 24-lead ceramic bottom·brazed flat pack
L • 28-terminal ceramic leadless chip carrier
S • 24-lead, .300 wide side-brazed ceramic DIP

A. A, NCVco A,A.

~:D:5

Ordering Information

22 ca,
IINC

A, •

At'

He 10
0, 11

ZO

t.

0.

0,

12 t3 t4t11117t.
O. O.Ond NCO.O.o.

PO>.41o_ ..............".pIn(w)
Du.~ln·U.. Package

Available In Q,3' and a.r Wide PackagH
'loa A. A. A. Ci An
M

..

cs.

0. 0,

o.

O. 0.

altI01.,.,71I"413

PO> 20 10 01..... provromrrIng pin (w)

Block Diagram
A.--'.....----,

A.
A7
A.
A.
A••
A,,-"L-_---'

A.,-=====~~
10132

. -=====+1

A._

~ ...

Mubiplexerl

cs.---~
cs.
___-1

Driworl (8)

(8)

A41------------------~____~~~

Output

00000000

.......

3-916

Raytheon Semiconductor

For Mora Information, cell 1-800·722-7074.

R296XX1R297XX
4096 x 8 SPROM - R29n3
Power and AC Characteristics Over Operating Range
Icc conforms to MIL-STO-883, Group A, Subgroups 1, 2 and 3.
AC parameters conform to MIL-510-883, Group A, Subgroups 9, 10 and 11
Parameter

DescrIptIon

Test Conditions

~

Power Down, Supply
Current (disabled)
Supply Current (enabled)
Address Access Time
Enable Access Time

Vcc =Max, PS =VIH ,
All other inputs =GND
Vcc = Max, All inputs =Gnd
CL =30 pF*
R1 =300n to Vcc

I.R

Enable Recovery Time

R2 =600n to GND, 16 rnA Load

PEL
Po

Power Dissipation (Disabled)
Power Dissipation (Enabled)

lceo
Icc
1M

·See AC Test Load Circuit and Switching Waveforms

R29773DM
R29773DM/883B
R29773DMS
R29773FM
R29773FMl883B
R29773FMS
R29773LM
R29773LM1883B
R29773LMS
R29773SM
R29773SM/883B
R29773SMS

Package

S
S
S

55

rnA

190
65
115

rnA
ns
ns

35

ns

303
1.04

mW
W

A. A,A,NCYclIA.A,

:::0'"
,. ",. :~

Operating Temperature
Range

D
D
D
F
F
F
L
L
L

Units

Pin Out Information

Ordering Information
Part Type

MaxImum Limits
R29n3M

-55°C to +125°C
-55°C to +125°C
-55OC to +125°C
-55°C to +1250C
-55°C to +125°C
-55°C to +1250C
-55OC to +1250C
-55OC to +1250C
-55OC to +125°C
-55°C to +1250C
-55°C to +1250C
-55°C to +125°C

Notes:
/8838 suffix denotes MIL-5TD-883, Level 8 processing
S suffix denotes Level S processing
D = 24·lead .600 wide ceramic DIP
F = 24-lead ceramic bottom-brazed flat pack
L = 28-terminal ceramic leadless chip carrier
S =24-lead, .300 wide side-brazed ceramic DIP
Contact factory regarding flat pack package

Atl

.~

A. •

Z1 He

NC 10

20

0-

0. n

"

0,

121S14151,,71,

0. o,Ond NCa.Q.o.

Pin 24 I, alto the programming pin Q:Jp)
Du...ln-LlneIFla' Pack P.ckIIg.
Aw.llab..... or and 0 .... Wid. Pack. . .
'loa'"

A,

",. . . "liPS 0 , 0 , 0 . 0 . 0 .

"

_

~

N

:II

4

I

1

n

I!

A, A_

t. "
•

A, A. At A.

7

17

'I •

14 "

•

•

it

A, A, 0,

10

12

o. 0.

Pin 20 ia also the programrring pin (w)

Gnd
~

Block Diagram
As
A.

3r----,

A7
A.

101128
Decoder

A.

Alo
A , , -...._ - - - '

AO======t~~
10132

AI

A':=====~5~
MulllplexelS
(8)
A.------------~4i___~r_~

A.

ps .----"20"<1

OUtput

pS._---'1.;;.,8-i

DrivelS (8)

00000000
15-01%1

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

3-917

R296XX1R297XX
8196 x 8 PROM - R29791
Power and AC Characteristics Over Operating Range
lee conforms to MIL-5TD-883, Group A, Subgroups 1, 2 and 3.
AC parameters conform to MIL-STD-883, Group A, Subgroups 9, 10 and 11

Parameter Description
Power Supply Current
lee

Test Conditions
Vee = Max, All Inputs GND

Maximum L1mHs
R29791M
190

UnHs
mA

tM

Address Access Time

CL =30 pFl

75

ns

tEA

Enable Access Time

=300n to Vee
R2 =600n to GND, 16 rnA Load

30

ns

30

ns

1.04

W

R1

tER

Enable Recovery Time

Po

Power Dissipation

Note:
1.See AC Test Load Circuit and Switching Waveforms

Ordering Information
Part Type

Operating Temperature
Range

Package

o

R29791DM
R297910M/BB38
R29791DMS
R29791FM

-55°C to +125°C
-55OC to +125°C
-55°C to +125°C
-55OC to +1250C
-55OC to +1250C
-55OC to +1250C
-55OC to +1250C
-55OC to +1250C
-55°C to +125OC

o
o
F
F
F

R29791FMlBB38
R29791FMS
R29791SM
R29791 SMI8838
R29791SMS

Block Diagram

S
S
S

A.
A.
A7

A.
A.

101256
Oecoder

A,.

21
A11
A'2_'-_--'

A.-------!-r-.....::........--,

'.======::tI

A2
6
A
A_------'H

10132
Multiplexers

A.------.::.4-L_~(;=:6),.._--1

Notes:
J883B suffix denotes MIL-STD-883, Level B processing
S suffix denotes Level S processing
D • 24-lead .600 wide ceramic DIP
F • 24-lead ceramic bottom-brazed flat pack
S .. 24-lead, .300 wide side-brazed ceramic DIP

Output
Drivers (8)

00000000
65-0'26A

Pin-Out Information
Dual-In-Llne/Flat Pack Package
Available In 0.3" and O.S" Wide Packages
vee A.

A.

A,.

cs

An A'2 O. 0 7 O. O. O.

24

22

21

20

19

23

18

17

16

15

14

13

7

8

9

10

11

12

Pin 20 is also the programming pin (pp)
65-4062A

3-91B

Raytheon Semiconductor

For Mora Information, call 1-800-722-7074.

R296XX1R297XX
8192 x 8 SPROM - R29793
Power and AC Characteristics Over Operating Range
Icc conforms to MIL-STO-883, Group A, Subgroups 1, 2 and 3.
AC parameters conform to MIL-STO-883, Group A, Subgroups 9, 10 and 11
Parameter

Description

Test Conditions

tEA

Power Down, Supply
Current (disabled)
Supply Current (enabled)
Address Access Time
Enable Access Time

Vcc = Max, PS = V,H ,
All other inputs = GND
~ = Max, All inputs = Gnd
CL =30pF*
R1 = 300n to Vee

tER

Enable Recovery Time

R2 = 600n to GND, 16 mA Load

Pn
PD

Power Dissipation (Disabled)
Power Dissipation (Enabled)

IccD
lee
t

Maximum Limits
R29793M

Units

50

mA

190
75
125

mA
ns
ns

30

ns

275
1.04

mW
W

·See AC Test Load Circuit and Switching Waveforms

Ordering Information
Part Type

Block Diagram

Operating Temperature
Range

Package

o

R29793DM
R29793DM/8838
R29793DMS
R29793FM
R29793FM/8838
R29793FMS
R29793SM
R29793SMl8838
R29793SMS

-55OC to +125°C
-55OC to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55OC to +1250C

D
D
F
F

F
S
S
S

Noles:
J883B suffix denoles MIL-STD-883, Level B processing
S suffix denoles Level S processing
D = 24-lead .600 wide ceramic DIP
F = 24-lead ceramic bollom-brazed flal pack
S - 24-lead, .300 wide side-brazed ceramic DIP

A.

A.
A7

A.
A.
A,.

A"
A,.--"L-_---'

~::::::::::~~--l~O~f~~~

A. -----------'!5'-1
A.-----------c~

lIuftlplex...
(8)

A.--------~4i___~r_~

Pi ___20~

OUtput
Drlv... (8)

00800000
16-0127'\

Pin Out Information
Dual-ln-Line/Flat Pack Package
Available In 0.3" and O.S" Wide Packages
vee A.

A.

AlO

ps

Au A12 O. 07

O. 0, O.

24

22

21

20

19

15

23

18

17

16

14

13

123456

Pin 20 is also the programming pin (pp)
For More Information, call 1-800-722-7074.

6S-4072A

Raytheon Semiconductor

3-919

R296XX1R297XX
AC Test Load Circuit
Vee

0-------0--<::>---...,
51

Rl

300n
Output

0-----..-----.
R2

soon

65-4059

Notes:
1. tM is tested with switch S, closed and CL • 30 pF.
2. tEA is tested with CL • 30 pF; S, is open for high impedance to "1" test and closed for high impedance to ·0" test.
3.

~

Is tested with CL - 5 pF; S, is open for "1" to high impedance test and measured at V011 -0.5V output level and is closed
for "0" to high impedance test and measured at Vat. +0.5V output level.

Switching Waveforms
_ - - - - - - - - - - - - - - 3.0V
1.5V

OV
3.0V
1.5V

OV

VOH

0,- On

--"''*"*'+If---'**....- - - f f f f + - 1.5V
VOl

Keys to Timing Diagram
Waveforms

3-920

Inputs

Outputs

Must be
Steady

Will be
Steady

Don't Care.
Any Change
Permitted
Does Not
Apply

Changing State
Unknown
Center Line is
High Impedance
Off State

Raytheon Semiconductor

65-4811

For More Information, call HlOO-722-7074.

R296XX1R297XX
Dynamic Burn·ln

Dynamic Life Test/Burn·ln Circuits
In accordance with MIL-STD-883, Methods
100511015, Condition D

TA =125+!O °C minimum
Vco =5.25 ±O.25V
Square Wave Pulses on AD to An are:
50% ±1 0% duty cycle
Frequency of each address is to be
1/2 of each preceding input,
with AD beginning at 100 kHz
(e.g., AD =100 kHz ±10%,
A1 =50 kHz ±1 0%,
A2 =25 kHz ±10%,
An =112 An-1 ±10%, etc.)
Resistors are optional on input pins
(R =3000 ±1 0%)

Dynamic Burn..n

R296311631A
R296331633A
R29681 1681 A
R296831683A
R29771
R29773
R29791
R29793

For Men Information, call 1-800-722·7074.

Dynamic Bum·1n

65-4064

6~63

Raytheon Semiconductor

3·921

R296XX1R297XX
Static Life Test/Burn-In Circuits
Static Burn..n

In accordance with MIL-STD-883, Methods
1005/1015, Condition C
TA =125+!O °C minimum
Vee =5.25V ±O.25V
Resistors are optional on input pins
(R =3000 ±1 0%)

Static Burn-In

Vee

R29651/651 A
R29653/653A

Static Burn-In

65-4067

Vee

R29631J631A
R29633J633A
R29681J681A
R29683J683A
R29771
R29773
R29791
R29793

65-4068

3-922

Raytheon Semiconductor

For More Informalfon, call 1-800-722-7074.

R296XX1R297XX
Programming Characteristics
Address

TTLHigh

X
--~--~-----------

TTLUM

VOUT
TTLUM
S.SV

Strobe

TTL High
TTL Low

R296XX Series

R297XX Series

TR = O.34V/JJS Min. - 1.25V/JJS Max.
Tpp =80 liS Min. -1101lS Max.
T p= 1 liS Min. -40 liS Max.
T01 = 70 liS Min. - 90 liS Max.
TD2= 100 nS Min.
Vpp - 27V Min. - 33V Max.
VOUT = 20V Min. - 26V Max.

TR - O.34V/JJS M"III. - 1.25V/JJS Max.
Tpp -70 liS Mn. -120 liS Max.
Tp = 20 liS Min. - 40 liS Max.
T01·60IlSMn.-100IlSMax.
T02- 100 nS Min.
Vpp • 26V Mn. - 28V Max.
VOUT = 22V Min. - 24V Max.

Noms:
Output Load = 0.2 mA During 6.0V Check
Output Load = 12 rnA During 4.2V Check

~10

Programming Timing

Device Programming Inputs
If you would like to have Raytheon program your devices, please submit one of the following:
• Two masters and truth table
• Two masters and checksum
In either case, we require customer approval prior to programming the devices.
If you need blank devices in order to supply programming masters, please do not hesitate to contact Raytheon for
unprogrammed samples.

For Mole Information, call 1-800·722·7074.

Raytheon Semiconductor

3·923

R296XX!R297XX
Commercial Programmers (subject to
change)
Equipment must be calibrated at regular intervals. Each
time a new board or a new programming module is
inserted, the whole system should be checked. Both
timing and voltages must meet published specifications
for the device.
Please contact the following manufacturers for
equipment information:
Data VO Corp.
10525 Willows Road, N.E.
P.O. Box 97046
Redmond, WA 98073-9746
(800) 247-5700

Commercial Surface Mount Socket
Adapter Manufacturer (subject to
change)
Please contact the following manufacturer for equipment
information:
Emulation Technology, Inc.
2344 Walsh Avenue, Bldg. F
Santa Clara, CA 95051
(408) 982-0660
The companies listed above are not intended to be a
complete guide of manufacturers of programmers or
adapters, nor does Raytheon endorse any specific
company.

Stag Microsystems Inc. (R296XX Series)
1600 Wyatt Drive, Suite 3
Santa Clara, CA 95054
(408) 988-1118

3-924

Raytheon Semiconductor

For More Information, call 1-800-722·7074.

Small Signal Transistors
Small Signal Transistors (Hermetic Seal)
Raytheon Semiconductor offers a wide variety of industry
standard and sole source high reliability (JAN, JANTX,

JANTXV) Small Signal Transistors. lhese transistors are
available In a variety of hermetic seal packages (T018,
T039, T046, T072, TOn, T078, TOS6).

Product
Description
NPN General Purpose Amplifier
2N0657**
2N0697**
NPN General Purpose Amplifier
2N0706**
NPN Ultra High Speed Switch
2N0718A
NPN General Purpose Amplifier
2N0720A**
NPN General Purpose Amplifier
2N091 0**
NPN General Purpose Amplifier
NPN UHF Amplifier
2N0918
2N0930
NPN Low Noise, High Gain Amplifier
2N1131**
PNP General Purpose Amplifier
2N1132**
PNP General Purpose Amplifier
2N1613**
NPN Medium Current General Purpose Amplifier
2N1711**
NPN General Purpose Amplifier
2N1890**
NPN General Purpose Amplifier
2N1893**
NPN General Purpose Amplifier
2N2060
NPN Differential Amplifier
2N2219A
NPN Medium Current General Purpose Amplifier
2N2222A
NPN Medium Current General Purpose Amplifier
2N2369A
NPN Ultra High Speed Switch
2N2484
NPN Low Level Low Noise High Gain Amplifier
2N2605
PNP Low Level Low Noise High Gain Amplifier
2N2905A
PNP Medium Current General Purpose Amplifier
2N2907A
PNP Medium Current General Purpose Amplifier
2N2919**
NPN Low Noise High Gain Differential Amplifier
2N2920
NPN Low Noise High Gain Differential Amplifier
2N2945A**
PNP Chopper
2N2946A**
PNP Chopper
2N3019
NPN General Purpose Amplifier
2N3057A**
NPN General Purpose Amplifier
2N3250A**
PNP Low Level Gen Purpose Amp & Switch
2N3251 A
PNP Low Level Gen Purpose Amp & Switch
2N3467
PNP Core Driver
2N3485A**
PNP Med Current Gen Purpose Amplifier
2N3486A
PNP Med Current Gen Purpose Amplifier
2N3498**
PNP High Voltage Gen Purpose Amplifier
2N3499**
NPN High Voltage Gen Purpose Amplifier
** Designates Sole Source

For Mora Infcrmation, call 1-800·722-7074.

Package
T039
T039
T018
T018
T018
T018
T072
T018
T039
T039
T039
T039
T039
T039
TOn
T039
T018
T018
T018
T046
T039
T018
TOn
TOn
T046
T046
T039
T046
T018
T018
T039
T046
T046
T039
T039

Raytheon Semiconductor

JAN
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X

JANTX

JANTXV

X
X

X

X
X

X

X
X
X

X

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

3-925

I

Small Si2nal Transistors
Product
2N3500··
2N3501
2N3634
2N3635
2N3636
2N3637
2N3700
2N3735
2N3737
2N3762··
2N3763··
2N381 0
2N3811
2N3866
2N3866A·
2N4029
2N4033
2N4449
2N4854
2N51 09
2NS794
2N5795
2N5796
2N6987
2N6988
2N6989
2N6990
SP2219AF
SP2219AQF
SP2484F
SP2484QD
SP2484QF
SP2605F
SP260SQF
SP290SAF
SP290SAQD
SP2905AQF
SP3019QF
SP3467F
SP3467QD
SP3467QF
SP3724F
SP3724QD
SP3724QF
SP372SF
SP372SQD
SP3725QF

Description
NPN High Voltage Gen Purpose Amplifier
NPN High Voltage Gen Purpose Amplifier
PNP High Voltage Gen Purpose Amplifier
PNP High Voltage Gen Purpose Amplifier
PNP High Voltage Gen Purpose Amplifier
PNP High Voltage Gen Purpose Amplifier
NPN General Purpose Amplifier
NPN High Current High Speed Switch Core Driver
NPN High Current High Speed Switch Core Driver
PNP High Current High Speed Switch Core Driver
PNP High Current High Speed Switch Core Driver
PNP Low Noise High Gain Differential Amplifier
NPN Low Noise High Gain Differential Amplifier
NPN RF Amplifier
NPN RF Amplifier
PNP General Purpose Amplifier
PNP General Purpose Amplifier
NPN Ultra High Speed Switch
NPN/PNP Complementary Dual
NPN RF Amplifier
Dual NPN Med Current General Purpose Amp
Dual NPN Med Current General Purpose Amp
Dual NPN Med Current General Purpose Amp
Quad PNP Med Current General Purpose Amp
Quad PNP Med Current General Purpose Amp
Quad NPN Med Current General Purpose Amp
Quad NPN Med Current General Purpose Amp
Dual NPN Med Current General Purpose Amp
Quad NPN Med Current General Purpose Amp
Dual NPN Low Noise, High Gain Amp
Quad NPN Low Noise, High Gain Amp
Quad NPN Low Noise, High Gain Amp
Dual PNP Low Noise, High Gain Amp
Quad PNP Low Noise, High Gain Amp
Dual PNP Med Current General Purpose Amp
Quad PNP Med Current General Purpose Amp
Quad PNP Med Current General Purpose Amp
Quad NPN General Purpose Amp
Dual PNP High Current, High Speed Switch
Quad PNP High Current, High Speed Switch
Quad PNP High Current, High Speed Switch
Dual NPN High Current, High Speed Switch
Quad NPN High Current, High Speed Switch
Quad NPN High Current, High Speed Switch
Dual NPN High Current, High Speed Switch
Quad NPN High Current, High Speed Switch
Quad NPN High Current, High Speed Switch

Package
T039
T039
T039
T039
T039
T039
T018
T039
T039
T039
T039
T078
T078
T039
T039
T039
T039
T046
T078
T039
T078
T078
T078
T0116
T086
T0116
T086
T089
T086
T089
T0116
T086
T089
T086
T089
T0116
T086

JAN

JANTX

JANTXV

X
X

X
X

X
X
X
X
X
X

X
X
X
X
X
X

X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X

X
X
X
X
X

X
X
X
X
X
X

TOB6
T089
T0116
T086
T089
T0116
T086
T089
T0116
T086

•• Designates Sole Source
3-926

Raytheon Semiconductor

For More Infonnation. call 1-800-722-7074.

ASIC
Section 4
AnaloglMixed-Signal Application Specific
Integrated Circuits
Raytheon Semiconductor is a major supplier of high
accuracy and high performance analog and mixed-signal
ASICs with High Speed Bipolar and CBiCMOS processes.
These high performance products are available for
customer specific products for both commercial and
military applications such as:
•
•
•
•
•
•

ATE Pin drive and sense electronics
Video/multimedia products
Data acquisition products
RFIIF communications products
High speed data communications (FOOl, ESCON,
Fiber Channel, ATM)
Power management circuitry

When converting your discrete design into an ASIC,
Raytheon's design engineers will use existing analog or
digital (mixed-signal) cells from standard cell libraries.

Under the VRSA-Tile (Versatile Raytheon Smart ASICs)
concept, Raytheon supports full custom transistor level
deSign, tile array design and standard cell design. These
ASIC products are based on both complementary bipolar
and CBiCMOS process technologies and are available in a
variety of commercial/military DIP or surface mount packages.
A comprehensive, proven CAD system forms an integral
part of Raytheon Semiconductor's VRSA-Tile design
methodology. Front end design such as Schematic Capture
and Circuit Simulation are linked in software to Layout,
Design Verification and Testing, sharing a common database for error-free designs. The resulting prototypes, as well
as production parts, are manufactured and assembled at
Raytheon facilities with particular emphasis on timely
delivery of quality products.

ASIC Process Technologies
Features
BVCEO
NPN (fT)
Minimum Geometries
NMOS (Drawn)
PNP (9 Vertical
Minimum Geometries
PMOS (Drawn)
CMOS 1X (Inverter Gate Delay)
P-Channel JFET
SiCr Resistors
Matching
Tempco
Applied VoHage
Tolerance
Zener lap CapabilHy
Schottky Diodes (AISi)
Schottky Diodes (PISi)
Schottky Diodes <1 ns Response Time

For More Infoonation, call 1-800·722-7074.

HI6h Voltage
32 olt Bipolar
32
0.5
(18 x 23)

(18 x 23)

Yes
Yes
1.5
200
200
±10
Yes
Yes
No
No

CBICMOS
12
4.0
(2x 3)
2.5
1.5
(2 x3)
2.5
1.0
Yes
<1.0
50
200
±10
Yes
No
Yes
Yes

Raytheon Semiconductor

CBIP
12
4.0
(2 x 3)
1.5
(2 x 3)
1.0
Yes
<1.0
50
200
±10
Yes
No
Yes
Yes

Units
Volts
GHz

fJll1
fJll1
GHz
fJll1
fJll1
ns

% max-match
ppm/OC
Volts
Percent

4-1

ASIC
ASIC Product Offering
Products

Process

RLA32V
Bipolar Array
Family

32 Volt
Bipolar Process

I
I

RFA120
I 12-Tile FET Array

-------

RLDASO
S-Tile
IMixed-Signal Array
I

CBIP
Complementary
Bipolar Process

RPA160
16-Tile
Complementary
Bipolar Array
I
I
I
I

CBiMOS
Complementary
Bipolar + CMOS
Process

----

RPA90
9-Tile Array

RSC4000
CBiP or CBiCMOS
Standard CelliCs
65-5992

Available Design Methodologies
Array
32V & 12V CBiP

Standard cell
32V, 12V CBiP & CBiCMOS

Full Custom
32V, 12V CBiP & CBiCMOS

DeSign review to prototypes:
6-10 weeks

DeSign review to prototypes:
14-16 weeks

Design review to prototypes:
18-24 weeks

Improved Circuit Performance
Pre-designed standard cell
Smallest die for function (die,
package)
Optimized layout
Better performance
Low power for small die
Optimized thermal gradients

••
•
••
•

First Silicon Success
Pre-designed macrocelilibrary
Array foundation
Low risk, high confidence

•
•

•
••

•
•

4-2

Fast circuit update, 2-4 weeks
80% (max) array utilization
Low development cost
Yearly volumes >SOK units/yr_

•
•
•
•
•
•
•
•
•
•

Optimized Circuit Performance
Custom designed cells
lowest thermal gradients
Optimized layout for function
Smallest die for function
Lowest power for die size
Lowest unit price for function

Circuit changes 6-8 weeks
Efficient utilization of all silicon

•
•

Circuit changes 12-14 weeks
Optimized utilization of silicon

Higher NRE than array
Yearly volumes >100K units/yr_

••

Highest NRE
Yearly volumes >100K units/yr_

Raytheon Semiconductor

For More Information, call 1-800-722-7074_

ASIC
ASIC CAD System
Depending on circuit complexity and the number of digital
gates required, PC based or workstation based tools may be
used. In the PC environment, orCAD is used for schematic
capture and circuit simulations can be executed in PSpice or
HSPICE. However. only a limited amount of digital logic can
be handled in this manner before simulation run-times
become excessive.
The workstation tools are Cadence based, and either the
Edge or the Mist package can be used for schematic
capture. The Verilog tool is offered for mixed-signal
applications requiring extensive digital circuitry. Mixed-mode
simulations using Verilog employ HSPICE for analog
simulations. Since circuit simulations are repeated by
Raytheon to verify a customer's results, the same CAD
environment is used wherever possible.

Once the simulation resuRs have been mutually accepted, the
design moves to the Layout phase. Here, Cadence's Cell
Ensemble tool is used. This layout tool extracts layout
parasitics that are inserted in the simulation models and
simulations can be re-run, using this additional information.
When simulation results are acceptable, Design Rule
Checking (DRC. ERC) and Layout Verification (LVS) software
is run prior to the start of mask making. Hsimulation results
are not satisfactory, changes may have to be made to the
layout In order to address observed problems and the cycle is
repeated until the post-layout simulation results are
acceptable. Only then will the design move on to mask
making. Final simulations are used to generate the test
program for the design.

Design Flow
P.C. Customer's

W.S. Customer's

Schematic Capture
OrCAD

Schematic Capture
Cadence Edge or Artist

P.C. Customer's

W.S. Customer's

Circuit Simulation
PSpice, HSPICE

MixedMocIe

Circuit Simulation

Raytheon's
Schematic Capture,
PC'sOrCAD,
Cadence
or Artisl

Raytheon's
Parasitic Extraction
Caclence

Raytheon's
Circuit Satistics

65-4559A

For More Infcnnation, call 1-800-722-7074.

Raytheon Semiconductor

ASIC
32 Volt Linear Arrays (RLA Family)
Bipolar junction isolated wafer fabrication is the basis for the
linear macrocells listed below. This process employes
projection-based photolithographic imaging, thin film etch
definttion and a two-layer interconnect technology. A
dielectrically isolated SiCr resistor fabrication technique is
used along with a conventional, low cost single layer
personalization mask step.

The basic untt of our linear arrays is the programmable
differential gain block - the op amp or comparator. This
allows custom tailoring of high level functions at a single
macrocelliocation. Addttional functions can be buiH by
combining macrocells with the onboard transistors and
resistors.

BVcEO

Description

Ft (min)

RLA40

RLA80

RLA120

RLA160

32V

Type GS Macrocells

500 MHz

4

8

4

32V

Type NGS Macrocell

500 MHz

0

0

8

No

No

32V

MVREF V-Reference
NPNS Transistors

500 MHz
500 MHz

37

32V

NPNM Transistors

500 MHz

4

32V

NPNL Transistors

500 MHz

PNPS Transistors

4MHz

32V

32V

RFA120

RLDA80

7

8

8

8

4

0

No

Yes

No

Yes

46

39

43

71

24

0

0

4

4

0

3

4

0
4

0

0

17

19

16

10

27

12

Digital Macros

0

0

0

0

0

18

Small Digttal Macro

0

0

0

0

0

19

D-Latch Cell

0

0

0

0

0

16

Digital 110 Cell

0

0

0

0

0

10

Extra Current Source

0

0

0

0

0

0

MNIMO

3

4

4

4

4

4

SiCr Resistors (Total)
Total ReSistance
Bonding Pads

66

93

196

240

262

128

106M

2.7M

4.SM

S.7M

6.2M

3.1M

24

24

24

44

32

46

Analog Macrocells Available

OpAmps

Dig Hal Macrocells Available for RLDA80

MOPAI
MOPA2
MOPA3
MCMPI
MCMP2
SW
UNIREF
DVREG

Vos=±1 mVtyp.
los =4 nA typo
Slew rates 0.7 V/J.lS
Gain bandwidth = 10 MHz

AND2
NOR2
XNOR2
DLP
DLN
DITC
DOTC

4-4

BasicOpAmp
Ground Sensing Op Amp
Class AB Op Amp
Ground Sensing Comparator
Open Emitter Comparator
SPDT Analog Swttch
Bandgap Reference
Vonage Regulator

COmparators
Vos=±1 mVtyp.
los = 20 nA typo
Response time 1 J.lS

Raytheon Semiconductor

2 Input AND gate
2 Input NOR
2 Input exclusive NOR gate
Positive gate D-Iatch
Negative gate D-Iatch
nuCMOS input cell
nuCMOS output cell

For More Infonnation. call 1-800·722-7074.

ASIC
Precision Complementary Arrays (RPA Family)
The RPA90 and RPA160 are a family of high speed analog
customer specific ASICs. These arrays are fabricated on a
precision high speed analog process (CBiP) with thin film
resistors. The RPA90 has a fixed tile foundation in a 3 x 3 grid
pattern, the RPA160 has a 4 x 4 pattern. Each tile has Hs own

axis of symmetry to minimize parasitic and thermal gradients
as shown below. By using the tile array's pre-designed and
characterized analog macrocells, the risk associated with
analog design is reduced. A listing of the available macrocells
is located on the following page.

Description
QN1S NPN Transistor wHh Schottky Clamp (1 X)
QN5S NPN Transistor with Schottky Clamp (5X)

fy(mln)
4GHz
4GHz

QN25S NPN Transistor wfth Schottky Clamp (25X)

4GHz

QP1 PNP Transistor (1 X)

1.5GHz

13 Volts
15 Volts

QP5 PNP Transistor (5X)

1.5GHz

15 Volts

QP25 PNP Transistor (25X)
DS1 Schottky Diode

1.5GHz

15 Volts

Quantltyl
Tile
15

BVcm
13 Volts
13 Volts

3
6
10
2
6
2

MOS CapacHor, largest definable value of 1 pF
RTF1 SiCr Resistor (2.5K max. definable value)
RTF2 SiCr Resistor (15K max. definable value)
RTF1 SiCr Resistor (38K max. definable value)

QN25

RlF3 RTF3
QNIS QNIS QNIS QNIS ONIS ON5S

QN25

**** **RBI(~~;

DSI

OP26

QPI OPI OPI OPI OPI QPS

-K

-K-K-K-K-K-K

-K
-K

OP25

-K
RTF2

-K-K-K-K-K-K
**$RBI(~

-K -K

QPl OPI OPI QPl OPI OPS

* * * ~~

OP25

DSI

OP25

OP25

-K -K -K -K -K -K -K -K

ONIS ONIS ONIS QNIS ONIS ON6S

For More Information, call 1-800-722-7074.

ON25

ON26

Raytheon Semiconductor

32

96
64

ON25

RlF3RTF3

54

6
4

OP25

--I200 MHz Wide Power Bandwidth Product, Low Power Buffer
COmparators
CMP01
30 ns TTUCMOS General Purpose Comparator
CMP02
25 ns TTUCMOS Single Supply Comparator
CMP03
40 ns, Low Offset Precision Comparator
CMP04
3 ns High Speed ECL-Output Comparator
CMP05
6.5 ns, Low Power High Speed TTL Comparator
VREF
REF01
80 ppmf'C, 2% Accurate, 2.5V Bandgap Reference
REF02
30 ppml"C, 0.5% Accurate, 2.5V Bandgap Reference
Signal COnditioning
MLT01B
12 MHz, Low Noise, High Accuracy, Analog MuHiplierlDivider
MXA01B
50 MHz, 8 Channel MuHiplexed Video Amplifier
DEM01B
30 MHz, 100 ns, Synchronous ModulatorlDemodulator
QMD04B
250 MHz, Quadrature Modulator or Demodulator
TAH01B
38 MHz, Low Droop 0.5 mV/JJS, Precision Track and Hold
MIX01B
800 MHz RRn, 400 MHz IF, Wide Bandwidth Mixer/Amplifier
PU Signal Synthesis &Data Recovery
VC001B
200 MHz High Speed VoHage Controlled Oscillator (VCO)
PLL01
150 MHz, 50 ppmf'C High Speed Phase Lock Loop
PLL03
200 MHz, 12 ps RMS (typ.) JHter, Phase Lock Loop
4-6

Raytheon Semiconductor

Std. Cell
RSC4000

Macrocells
RPA90 RPA160

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes

Yes
Yes
Yes

Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes

Yes
Yes

Yes
Yes

Yes
Yes

Yes
Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes
No

Yes
Yes
Yes
Yes
Yes
No

Yes
Yes
Yes

Yes
Yes
No

Yes
Yes

For More Information, caJI1-800-722-7074.

ASIC
RSC4000 Digital Functions
Digital Bipolar Standard Cells
{Only available on RSC4000}

Digital CMOS Cells

Gates, Inverters and Buffers
1N11HI
Inverter
NI11 HI
Buffer
AN21 HI
2-lnput AND
ND21HI
2-lnput ANDINAND
NR21 HI
2-lnput NOR
0R22CI
2-lnput ORINOR
X022CI
2-lnput EX{)RlNOR
ON41 HI
4-lnput ORINAND
OA42CI
4-lnput OR-ANDINAND

Inverters and Buffers
IN 11 LC
Inverter (1 X)
IN112C
Inverter (2X)
IN 113C
Inverter (3X)

Flip-Flops, Latches
DFNC11
D Flip-Flop
LANCHI
D Latch
Input/Output Translators
RPNElI
m-ECL Input Translator
RPNETP
m-PECL Input Translator
DTNEIT
ECL-m Output Translator
DTNEPT
PECL-TTL Output Translator
Miscellaneous Functions
MX41EI
4:1 MuHiplexer wHh Enable
MX21EI
2:1 MuHiplexer wHh Enable
DC24EI
1:4 DemuHiplexer
DC24EI
2:4 Decoder wHh Enable
REF03B
ECL Bandgap Reference
REF04B
ECL VoHage Reference
REF05B
Input VoHage Reference

Data Conversion Cells
•
•
•
•
•

1Q-Bft, 40 MHz ADC
8-Bft, 30 MHz Low Power ADC
6-Bft, 70 MHz ADC
8-Bft, 50 MHz DAC
8-Bft, 15 ns Track and Hold

Gates
ND21LC
AN21LC
NR21LC
0R21LC
XN21LC
X021LC
ND31LC
AN31LC
NR31LC
OR31LC
ND41LC
AN41LC
NR41LC
OR41LC
AR41LC

2-lnput NAND Gate
2-lnput AND Gate
2-lnput NOR Gate
2-lnput OR Gate
2-lnput XNOR Gate
2-lnput XOR Gate
3-lnput NAND Gate
3-lnput AND Gate
3-lnput NOR Gate
3-lnput OR Gate
4-lnput NAND Gate
4-lnput AND Gate
4-lnput NOR Gate
4-lnput OR Gate
4-lnput AND-NOR Gate

Latches and Flip-Flops
LANCHC
D Latch
DFNCRC
D Flip-Flop
DFBCRC
D Flip-Flop wfth Preset, Clear
and Buffered Outputs
Input and Output Buffers
RPIECC
CMOS Input Inverter wIPad, Pullup and ESD
RPIElC
m Input Inverter wIPad, Pullup and ESD
DPIECC
CMOS Driver/Inverter wIPad and ESD
DPNECT
BiCMOS TTL Driver wIPad and ESD
DTNECT
BiCMOS m Three-State Driver wIPad
and ESD
TTNECT
BiCMOS Transceiver Three-State Driver
wIPad and ESD
LRINCC
CMOS Inverting Line Receiver (no pad)
LRNNCC
CMOS Line Receiver (no pad)
LRINTC
m Inverting Une Receiver (no pad)
LRNNTC
m Une Receiver (no pad)
Miscellaneous cells
ASW01C
Transmission Gate (1X)
DM241C
2:4 Decoder/1:4 DemuHiplexer
MX21IC
2:1 MuHiplexer
MX411C
4:1 MuHiplexer
MX811C
8:1 MuHiplexer

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

4-7

ASIC
Analog/Digital Test Capability
Once developed and in production, VRSA-Tile is supported through a variety of high pin count and surface mount plastic and hermetic
packages, fully tested on LTX, Teradyne or HP mixed-signal testers.

Analog Test Capability (LTX-80/HP9491)

Digital Test Capability (HP9491)

Parameter
Settling/AcquisHion Time
Bandwidth
Aperture Time
Harmonic Distortion
ADC Conversion Rates
Differential Gain/Phase
Slew Rate
Pattern Generation

Parameter
Maximum Pin Count
Maximum Test Pattern Rate
Timing Edge Placement Range
Timing Resolution
Timing Accuracy
Edge and Compare Output CapabilHy

Range
0.4% in 20 ns
200 MHz
100 ps
-B6dB
128 MHz
2.0lDegree
500 V/IJS at 1V
128 MHz

Performance
80
128 MHz
Oto 2 Periods
±100 ps
±SSO ps
SinglelWindowl
Double

ASIC Packaging Options
The following table lists the packages that are currently available for Raytheon Semiconductor ASIC products.
Package
Description
Ceramic 24 Lead Flat Pack (0.40" wide)
Ceramic 44 Lead Quad Flat Pack (0.65" sq.)
Ceramic 64 Lead Chip Carrier (0.90" sq.)
Ceramic 20 Pad LCC (0.35" sq.)
Ceramic 28 Pad LCC (0.45" sq.)
Ceramic 44 Pad LCC (0.65" sq.)
Plastic 28 Lead Chip Carrier (0.45" sq.)
Plastic 44 Lead Chip Carrier (0.65" sq.)
Plastic 68 Lead Chip Carrier (0.95" sq.)
Plastic 14 Lead DIP (0.30" wide)
Plastic 16 Lead DIP (0.30" wide)
Plastic 24 Lead DIP (0.30" wide)
Plastic 40 Lead DIP (0.60" wide)
Plastic 8 Lead sOle (0.15" wide)
Plastic 14 Lead SOIC (0.15" wide)
Plastic 16 Lead SOIC (0.15" wide)
Plastic 20 Lead SOIC (0.30" wide)
Plastic 24 Lead SOIC (0.30" wide)

4-8

TyplcalOJA
Value (CIW)
65
50
44
85
75
65
65
55
45
70
65
50
45
155
110
105
80
75

Raytheon Semiconductor

For More Infonnation. calI1-8Q().722·7074.

Cross References

Section 5
Cross References

Industry Type Cross References
Industry
Type

Raytheon Semiconductor
Nearest
Equivalent

AD647
AD708

RC4207
RC4277

HA5127
HA5137
HA-5147

OP-27
OP-37
OP-47

LH21 08

LH21 08

LM108

LM108

Industry
Type

Raytheon Semiconductor
Nearest
Equivalent

LT-1002

RC4227

MAX9686

LM111

MC1741

RC741

NE51 05

RC4805

NE5532
NE5534

RC5532
RC5534

OP-227

RC4227

Contents
Industry Type ..............................................................................................................................................5-1
General .......................................................................................................................................................5-2
Military Bipolar PROM .................................................................................................................................5-5
Standardized Military Drawings ...................................................................................................................5-6
QPL Approval Status Per M3851 0-90 .........................................................................................................5-7

For More Infoonalion, call HIOO-722-7074.

Raytheon Semiconductor

5-1

Cross References
Analog Devices
ADOP-07A
AD OP-07A1883
ADOP-07C
ADOP-07D
ADOP-07E
ADOP-07
AD OP-071883
ADOP-07
ADOP-27A
AD OP-27A1883
ADOP-27B
AD OP-27B/883
ADOP-27C
AD OP-27C/883
ADOP-27E
ADOP-27F
ADOP-27G
ADOP-37A
AD OP-37A1883
ADOP-37B
AD OP-37B/883
ADOP-37C
AD OP-37C/883
AD OP-37E
ADOP-37F
ADOP-37G
OP77A
OP77A1883
OP77A
OP77B
OP77B/883
OP77E
OP77F
OP77G
ADVF32
ADVF32
AD539
ADREF-01
ADREF-01C
REF-02
REF-02C
REF-02D

Burr Brown
VFC032BP
VFG-32PB
OPA27A1883
OPA27B/883
OPA27C/883B
OPA27A
OPA27B

5-2

Raytheon Semiconductor
Nearest Equivalent
OP-07A
OP-07A1BB3B
OP-07C
OP-07D
OP-07E
OP-07
OP-071883B
OP-07
OP-27A
OP-27A18838
OP-27B
OP-27B/883B
OP-27C
OP-27C/883B
OP-27E
OP-27F
OP-27G
OP-37A
OP-37A18838
OP-37B
OP-37B1883B
OP-37C
OP-37C/883B
OP-37E
OP-37F
OP-37G
OP-77A
OP-77N883B
OP-77A
OP-77B
OP-77B/883B
OP-77E
OP-77F
OP-77G
RC4152
RC4153
RC4200/A
REF-01
REF-01C
REF-Q2
REF-02C
REF-02D

Raytheon Semiconductor
Nearest Equivalent
RC4152
RC4153
OP-27A18838
OP-278/883B
OP-27C/883B
OP-27A
OP-27B

Burr Brown
OPA27C
OPA27E
OPA27F
OPA27G
OPA37A
OPA37A1883
OPA37B
OPA37B/883
OPA37C
OPA37C1883
OPA37E
OPA37F
OPA37G

Exar
XR2207
XR2211
XR4136
XR4151
XR5532
XR5532A
XR5534
XR5534A

Goldstar
GL71 07

Harris
CA124
CA139
CA324
CA339
CA5403A
RA4741
HA3-5101
HA3-5102
HA3-5102
HS3182
HS3182
ICL8013

Hitachi
[M1851

Raytheon Semiconductor

Raytheon Semiconductor
Nearest Equivalent
OP-27C
OP-27E
OP-27F
OP-27G
OP-37A
OP-37A18838
OP-37B
OP-37B/883B
OP-37C
OP-37C/883B
OP-37E
OP-37F
OP-37G

Raytheon Semiconductor
Nearest Equivalent
RM2207
RC2211
RC34Q3A
RC4152
RC5532
RC5532A
RC5534
RC5534A

Raytheon Semiconductor
Nearest Equivalent
RV4145

Rarrheon Semiconductor
Ne rest Equivalent
[M124
LM139
LM324
LM339
RC3403A
RC4741
RC5534
RC5532
RC5532A
RM3182
RM3182A
RC4200/A

Raytheon Semiconductor
Nearest Equivalent
RV4145

For More Information. call 1-800-722-7074.

Cross References
Hoh

Raytheon semiconductor
Nearest Equivalent

Maxim

HI8382
HI8382
H18482
H18482

RM3l82
RM3l82A
RM3l83
RM3283

Raytheon semiconductor
Nearest Equivalent

REf-01
REF-01C
REF-01D
REF-02
REF-02C
REF-02D
MAC630C
MAX630C
MAC630C
MAX4l93C
MAC4391C

REf-01
REF-01C
REF-01D
REF-02
REF-02C
REF-02D
RC4l90
RC4l9l
RC4l93
RC4l93
RC4391

Motorola

Raytheon semiconductor
Nearest Equivalent

[Ml01A
[Mlll
[M124
[M139
[M324
[M339
[M348
LM348
[M4l36
MCl42100
MC1504Ul0
MC1504Ul0
MC1504Ul0
MC1404U5
MC1404U5
MCl404U5
MC1468
MC1468
MC174l
MC3403
MC4558
MC4558
MC4741

[Ml01A
[Mlll
[M124
[M139
[M324
U.il339
RC4l56
RC4l57
RC4l36
RC4444
REF-01
REF-01C
REf-OlD
REF-02
REF-02C
REF-02D
RC4194
RC4l59
RC741
RC3403A
RC4558
RC4559
RC4741

Linear Technology Raytheon Semiconductor
Nearest Equivalent
Qp:01A

OP:01AT

OP~7A1883B
OP~7AJJ883B
OP~7C
OP~7E
OP~7
OP~71883B

OP~7A1883B
OP~7A1883B
OP~7C
OP~7E
OP~7
OP~71883B

OP-27A
OP-27A
OP-27A1883B
OP-27A1883B
OP-27C
OP-27C
OP-27C/883B
OP-27C/883B
OP-27E
OP-27E
OP-27G
OP-27G
OP037A
OP-37A
OP-37A1883B
OP-37A1883B
OP-37C
OP-37C
OP-37C/883B
OP-37C/883B
OP-37E
OP-37E
OP-37G
OP-37G
lMl08A
lM1QSA
LM108A1883B
LM108A1883B
LM108
LM10ST
LM10S1883B
LM10S1883B
OP-227EN
RC4227FN
OP-227GN
*RC4227GN
OP-227AJ
*RM4227BD
OP-227AJ/883B
*RM4227BD/883B
REF-Ol
REF-Ol
REF-01C
REF-01C
REF-02
REF-02
REF-02C
REF-02C
REF-02D
REF-02D
NOTE: LTC OP-227 contains two die in a 14-pin package.
Raytheon's 4227 is a monolithic IC in an 8-pin package.

For More Information, call1-S00-722-7074.

Raytheon Semiconductor

5-3

Cross References
National

n':M1A
[~111

L~124
L~139

LM148
[~168
[~169

[M185l
L~324
[~3251326

[M33l
LM339
LM3403
LM348
LM348
[~368

LM368
LM369
LM369
[M4l36

SG5-Thompson

Raytheon Semiconductor
Nearest Eqlvalent
DiilHllA
[~1l1
L~124
[~139

LM148
REF-02
REF-Ol
RV4l45
Ltvi324
RC4l94
RC4l52
LM339
RC3403A
RC4l56
RC4l57
REF-02C
REF-02D
REF-01C
REF-01D
RC4136

[~124

[~124

[M139
[M148

LM139
LM148
[M324
LM339
RC4558

Samsung

KA2a03

5-4

LM324

[M324

LMlll
LM124

[~339

[~339

NE5532
NE5532A
NE5534
SE4558
J.lA74l
J.lA747

RC5532
RC5532A
RC5534A
RC4558
RC741

Texas Instruments

Raytheon Semiconductor
Nearest Equivalent
LM101A
[Mlll

LM101A

[Ml01A
[Mlll

[~324

L~139

Raytheon Semiconductor
Nearest Equivalent
LM11l
LM124
LM139

L~lll
[~124

Raytheon Semiconductor
Nearest Equivalent
LM101A
LMlll

LM339
MC4558

Signetics

R~747

L~124

[M139

[M139

[~148

[~148

[M324
[M339
LM348
LM348
~C3403

RC4136
TL4941617

L~324
[~339

RC4l56
RC4l57
RC3403A
RC4l36
RC4l90

Raytheon Semiconductor
Nearest Equivalent
RV4145

Raytheon Semiconductor

For More Infonnation, call 1-1100-722-7074.

Cross References
Military Bipolar PROMs
Except 6617/178

HM76321
N/A
HM76641
N/A

Raytheon Semiconductor
Nearest Equivalent
Difference
R29621
tEAJICC
R29621 A
tEAIle/ICC
R29623
R29623A
R29631
tEAIIER
R29631 A
tM
R29633
~IIE~CCD
R29653A
R29681
R29681A
tMIIER
R29681A
tAr
~M&IDC/ACI
R29683
ICCSB/ICCOPI
Pinout
R29683A
CMOS/DC/ACI
ICCSB/ICCOPI
Pinout
R29771
tMIlEAIIEB
R29773
R29791
R29793

Signetics
Part Type
82S147
82S147A
N/A
N/A
82S181
82S181A
N/A
N/A
82S185
82S185A
N/A
N/A
82S191
82S191A
R29683
R29683A
82HS32A
82HS321B
N/A
82HS641A
82HS641B
N/A

Raytheon semiconductor
Nearest Equivalent
Difference
R29621
R29621 A
R29623
R29623A
R29631
~IIEJICC
R29631A
ICC
R29633
R29633A
R29651
tM/lCC
R29651A
tMIlEAIIEB
R29653
R29653A
R2981
R29681A
tMIIEB
N/A
N/A
R29771A
tM
N/A
R29773
R29791
tAA
N/A
R29793

Harris
Part Type
HM7649
HM7649A
N/A
N/A
HM7681
HM7681A
HM7681P
N/A
N/A
HM7616
HM76161
HM6617
HM6617B

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

5-5

Cross References
Standardized Military Drawings
To stem the proliferation of contractor-generated Source
Control Drawings (SCDs), the U.S. Government has
established a program to create a single governmentcontrolled SCD for each part in the military inventory.
This document is called a Standardized Military Drawing
(SMD) and is available for use by any contractor. By
greatly reducing the number of part numbers thus
generated, it is much more practical to maintain an
inventory of these products, reducing acquisition time,
cost and overhead.
Raytheon Semiconductor is a strong supporter of this
program. We have a number of products currently in the
system and the list is growing rapidly. Identified below
are the products in the inventory at the time of
publication of this data book, along with the "nearest
generic equivalenf' Raytheon part number. Since the

SMD
5962-87600
5962-87786
5962·88532

5962088739

5962-89446

5962·89711

5-6

Defense Electronics Supply Center (DESC) in Dayton,
Ohio controls the detailed spec, we manufacture and test
the product strictly in accordance with that spec. If it
varies in any way from the standard speCification, the
SMD is the controlling document. It is important to verify
from DESC that you are working from the latest revision
of the SMD.
These products are not only available from the
government supply channels and from the Raytheon
Semiconductor factory. Many are handled through the
normal commercial distribution channels, providing ready
access to full-spec military products. They are all fully
compliant with the latest release of MIL-STD-883.
If you need a product not listed here, contact the factory.
It may be in progress; if not, we will be delighted to work
with you to add it to the program.

Suffix

Raytheon Part No.

Description

olXA
l03A
OlVA-01XA*'
01VA-01ZA-·
01UN·
01QA
02QA
03QA
04QA
01XA
02XA
03XA
04XA
01LA
013A
02LA··
023A-·
01JA
02JA
03JA
04JA
013A
023A
033A
043A
01LA
02LA
03LA
04LA

TDC1048B6V
TDC1048C3V
TDC104688V
TDC1049JoV
TDC1049J3V
TDCl049ClV
TDC1049LlV
TMC208KB5V
TMC208KB5Vl
TMC28KUB5V
TMC28KUB5Vl
TMC208KC2V
TMC208KC2Vl
TMC28KUC2V
TMC28KUC2Vl
TMC2011B2V
TMC2011C3V
TMC2111B2V
TMC2111C3V
TMC2023B7V
TMC2023B7Vl
TMC2023B7V2
TMC2023B7V3
TMC2023C3V
TMC2023C3Vl
TMC2023C3V2
TMC2023C3V3
TMC2023B2V
TMC2023B2Vl
TMC2023B2V2
TMC2023B2V3

8Blt 20 Msps AID
6Bit 20 Msps AID
9 Bit 30 Msps AID
9 Bit 30 Msps AID

aX8 Bit Multiplier

3-l8xB Shift Register

64 Bit COrrelator

Raytheon Semiconductor

For More Infonnation. calI1-8QO-722-7074.

Cross References
SMD
5962"89715

5962"89!l2!l
5962-90596

5962-90708
5962-90996

5962-91652

5962-86879
5962-!l958
5962-87738

5962-87739
5962-88537

Suffix
01XC"
02XC"
01YA**
02VA**
OlEA"
olJA
013A**
02JA
023A'*
01XCA**
01MYA
01MXA
01MZA
01MJC
01M3A
02MJC
02M3A
01EX
013A
102GA
102PA
OlGA
01PA
02GA
02PA
olCA
olGA
01PA
02GA
02PA
03GA
03PA

Raytheon Part No.
TMC2301G8V
TMC2301G8Vl
TMC2301L1V
TMC2301L1Vl
TOC1044B9V
TOC1012J7Vl
TDC1012C3Vl
TDC1012J7V2
TDC1012C3V2
TMC220BJ4V
TMC2009C1V
TMC2009J3V
TMC2009L1V
TOCl112J7V1
TDCll12C3Vl
TDC1112J7V2
TDCll12C3V2
RM3182S/883B
RM3182U883B
REF01Tl883B
REF010/883B
OP77BT/883B
OP77BD1883B
OP77AT/883B
OP77A01883B
LM139AD/883B
OP37AT/883B
OP37AO/883B
OP37BT/883B
OP37B01883B
OP37CT/883B
OP37C01883B
lM139D/883B
RC2211 D/883B
RM4194D/883B
LM124D/883B
R29771 lM/883B

Description
Image Rotation seq.

Single Supply Quaa Comparator
FSK DemoauclatorlTone Decoaer
Dual Tracking voffage Regulator
Single Supply Quaa Operational Amphfler
4096 x 8 Bipolar PROM

4 Bit 25 Msps AiD
12 Bit ECL OAC

BxB BicMAC
12x12 Bit MAC

12 Bit ECl OAc

ARINc 429 Olfferenllalline Driver
+10V PrecIsion Voffage Reference
PrecIsion Operational Amphfler

Single Supply Quaa Amphfler
Low NOise Operational Ampiffler

7700801CA
7705001CA"
7705401CA u
7704301CA
82008013A
8200801JA
8200801 LC*82008043A
8200804JA
8200804LC**
8200901LC"
8200901JA
8200901 XC
8203601GA
8203601PA
8203602GA

R29791SM/883B

8192 x 8 Bipolar PROM

OP07AT/883B
OP07A01883B
OP07T1883B

Precision Operational Amplifier

8203602PA

OP07D/883B

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

5-7

Cross References
MIL-M-38510 Products
M38510 Part No.
10101BCA
10101BGA
10101BPA
10102BAA**
10102BCA
10102BDA
10102BIA
10103BCA
10103BGA
10103BHA
10103BPA
10104BGA
10104BPA
10104B2A**
10105BEA
10106BEA

Raytheon Part No.
MM0741 DCA
MM0741 TEA
MM0741 DEA
MM0747CJA
MM0747 DCA
MM0747CAA
MM0747TFA
MM0101ADCA
MM0101ATEA
MM0101ACQA
MM0101ADEA
MM0108ATEA
MM0108ADEA
MM0108ALSA
MM2101ADMA
MM2108ADMA

10304BCA
10304BGA
10304BHA
10304BPA
10304B2A**
10305BEA
11001BCA
11003BCA**
11003BDA**
11004BCA
11005BCA
11201BCA
11201BDA
11201B2A**
11301BEA
11302BEA
13101BGA**
13101 BPA**
13102BPA**
13501BPA
13501BGA
13501B2A**
13502BPA
13502BGA
13502B2A**
20902BVA
20904BJA
21002BJA

MM0111 DFA
MM0111 TEA
MM0111CQA
MM0111 DEA
MM0111LSA
MM2111 DMA
MM0148 DCA
MM4156 DCA
MM4156CAA
MM4136 DCA
MM0124 DCA
MM0139 DCA
MM0139CAA
MM0139LSA
MM4818DMA
MM4818ADMA
MM5534ATEA
MM5534ADEA
MM5532ADHA
MM4807ADEA
MM4807ATEA
MM4807ALSA
MM4807DEA
MM4807TEA
MM4807LSA
JR29651DQ
JR29631DR
JR29681DR

Description
General Purpose Operational Amplifier

General Purpose Dual Operational Amplifier

General Purpose Operational Amplifier

Precision Operational Amplifier

General Purpose Dual Operational Amplifier
Precision Dual Operational Amplifier
Voltage Comparator

Low Power Quad Operational Amplifier
High Performance Quad Operational Amplifier
General Performance Quad Operational Amplifier
Single·Supply Quad Operational Amplifier
Single-Supply Quad Comparator

8·Bit Multiplying D/A Converter
Low Noise Operational Amplifier
Low Noise Dual Operational Amplifier
Precision Operational Amplifier

2048 x 4 Bipolar PROM
1024 x 8 Bipolar PROM
2048 x 8 Bipolar PROM

"Indicates sole source

5-8

Raytheon Semiconductor

For More Inbmation, call 1-800-722·7074.

Section 6 - Quality & Reliability

Section 6
Quality & Reliability

Raytheon's Commitment to
Customers

failure rate is controlled by wear-out mechanisms
inherent in the device construction.

Raytheon Semiconductor is dedicated providing
innovative high performance mixed-signal semiconductor
products.

,,

:
Infant MonaJlty:

The company has embraced the Total Quality
Management (TQM) concept for continuously improving
its products and services.

Random Failures

Raytheon Semiconductor maintains relationships which
are based upon integrity, open communication and
commitment to mutually beneficial, long term business
partnerships with its customers and suppliers.
Our definition of quality is meeting customer requirements
100% of the time. The responsibility for this quality is
shared by all employees.
With these commitments in mind, the Division has
developed a comprehensive Quality/Reliability Policy
Manual. Raytheon welcomes the opportunity to discuss
these poliCies with its customers and suppliers, and
solicits their questions, comments and/or
recommendations for improvement.

Reliability Concepts
Reliability is defined as the probability that product will
perform its' intended function for a specified period of
time. The reliability model generally assumed for
Integrated Circuits is that the failure rate over time follows
a "bathtub" curve.
This model predicts an early "infant mortality" period
where the failure rate is controlled by extrinsic defects.
After these initial failures occur, the failure rate is
essentially random and depicts the useful life of the
product. In this region of the curve a prediction of the
Failure rate In Time can be made, expressed as FITs
(assuming a constant failure rate). The "bathtub" curve
also predicts a final period in the product life where the
For More Information, call 1-1100-722-7074.

Wearout
Failure.

Operating Time

~"'7

Figure 1. Failure Rate vs. Time
Integrated circuits have demonstrated characteristically
long product lifetimes. In order to estimate the reliability
of these products, it is necessary to understand extrinsic
and intrinsic failure mechanisms and to accelerate
possible "useful life" failures. Physical and
environmental testing allows an understanding of
potential defects contributing to early failures. For
extended life prediction, the Arrhenius Model is used to
extrapolate from accelerated testing of the product to
useful field life.
The Arrhenius Model was originally developed to
describe temperature accelerated chemical reaction
rates, and is used to predict time/temperature
relationship of Integrated Circuit failure rates. Increased
temperature operation is one method of accelerating
failure. The Arrhenius Model predicts an exponential
relationship of temperature and intrinsic failure rate.
Using failure statistics obtained from high temperature
operation, the failure rate of the process can be
estimated and extrapolated to a specified operating
temperature range for the product family. An "activation
energy" for the expected failure mechanism is used for
this estimate of the expected failure rate under use
conditions.

Raytheon Semiconductor

6-1

Section 6 - Quality & Reliability

II

~":;""'

L.._ _

__
SO%....J:L..C_L_ _---,I=-_IL..90_%CL

I

x Failure Rate

Figure 2. Frequency vs. Failure Rate

The infant mortality and random failures periods can be
described through a series of probability calculations.
The probability of having a failure at a specific point in
time can be expressed by the equation:

where:
R = reaction rate as a function of time and
temperature
Ro = constant related to temperature
T = Kelvin temperature
E = activation energy (electron volts)
When this equation is plotted, as shown in Figures 3 and
4, it can be used to determine the failure rate at temperatures other than the test temperature of the device.

12_

Po =e-xt
where:
x = the failure rate (failures per unit time)
t=time
The failure rate "'1.." is usually expressed in % failures per
1000 hours and is sometimes expressed as a mean
time between failures (MTBF) through the expression:
1

MTBF =

Failure Rate

Since the data for the failure rate calculations is derived
from a sample of devices from a production lot, a
confidence level number is usually stated for the failure
rate estimation. A 60% confidence level (Cl) is used for
the purposes of these calculations.
The failure rate "x· is calculated by using a Chi square
(X2) distribution through the equation:
where:

c=

500400 300

200
100
50
Temperature (OC) t2

Figure 3. Normalized Time-Temperature Regressions for
Various Activation Energy Values (1000rK)

x2(x.2r+2)
2nt

100

x = 100-%CU100

1218

20

242.89.2

9.8

M
10

r = number of rejects
n = total number of devices
t=time

~
::>

0

::t:

The number of failures over a period of time (x) is critical
in determining an accurate failure rate number. If only
device failures at room or operating temperatures were
counted, it would take a large number of failures over a
long period of time to gather sufficient data. Therefore,
accelerated test methods using elevated temperatures
are used. Temperature is used to accelerate failures in
a device and the increase can be expressed in a form of
the Arrhenius equation which states that the reaction
rate increases exponentially with temperature.

1.0

§
>:::

0.1

OJ

0.01

.

~

II:

1.2

I!

.a

;,t

~

0.001

...!

0.0001

I

0.00001

150 I
14501350 250
500400 300 200
100

R=ROe ~
kT

65

25

50

Temperature I"C)

Figure 4. Failure Rate (1000rK)
6-2

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

Section 6 - QualHy & RellabllHy

Table I. Group A Electrical Tests for Class B Oevices(1)
SubgroupS(2)
QualHy/Accept No. =116/0 (3)(4)
Subgroup 1
Static tests at 25°C
Subgroup 2
Static tests at maximum rated operating temperature
Subgroup 3
Static tests at minimum rated operating temperature
Subgroup 4
Dynamic tests at 25°C
Subgroup 5
Dynamic tests at maximum rated operating temperature
Subgroup 6
Dynamic tests at minimum rated operating temperature
Subgroup 7
Functional tests at 25°C
Subgroup 8A
Functional tests at maximum rated operating temperatures
Subgroup 88
Functional tests at minimum rated operating temperatures
Subgroup 9
Switching tests at 25°C
Subgroup 10
Switching tests at maximum rated operating temperature
Subgroup 11
Switching tests at minimum rated operating temperature

1. The specific parameters to be included for tests in each subgroup shall be as specified in the applicable acquisition document
Where no parameters have been identified in a particular subgroup or test within a subgroup. no group A testing is required for
that subgroup or test to satisfy group A requirements.
2. The applicable tests required for group A testing (see 11) may be conducted individually or combined into sets of tests, subgroups (as defined in Table I.), or sets of subgroups.
3. The sample plan (quantity and accept number) for each test shall be 116/0.
4. If any device in the sample fails any parameter in the test, subgroup, or set of tests/subgroups being sampled, each and every
additional device in the (sub}lot represented by the sample shall be tested on the same test set-up for all parameters in that
test, subgroup, or set of tests/subgroups for which the sample was selected, and all failed devices shall be removed from the
(sub}lot for final acceptance of that test, subgroup, or set of tests/subgroups, as applicable.

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

6-3

section 6 - Quality Be Reliability

Table 2 Group B Tests for Class B (1)(2)
MIL·STD-883

Quantity/

(Accept No.)

Test
Method
Subgroup 2(3)
a. Resistance to solvents
Subgroup 3
a. Solderability(4)

Condition

orLTPD

2015
2022

3(Ql
Soldering temperature of 245 f50C

10

or

2003
SubgroupS
a. Bond strength(5)
1. Therrnocompression
2. Ultrasonic or wedge
3. Flip-chip
4.8eamLead

2011
1. Test condition C or D

2. Test condition C or D
3. Test condition F
4. Test condition H

Notes:
1. Post burn-in eledrical rejed devices from the same inspedion lot may be used for all subgroups when end-point measurements
are not required.

2.

Subgroups 1, 4, 6, 7, and 8 have been deleted from this table. For convenience, the remaining subgroups will not be renumbered.

3.

Resistance to solvents testing required only on devices using inks or paints as the marking or contrast medium.

4.

All devices submitted for solderability test shall be in the lead finish that will be on the shipped produd and which has been
through the temperaturellime exposure of burn-in except for devices which have been hot solder dipped or undergone tin fusing
after burn-in. The LTPD for solderability test applies to the number of leads inspeded except in no case shall less than 3
devices be used to provide the number of leads required.

5.

Unless otherwise specified, the LTPD sample size for condition Cor 0 is the number of bond pulls seleded from a minimum
number of 4 devices, and for condition For H is the number of dice (not bonds) (see Method 2011).

Table 3. Group C (Die-Related Tests - For Class B only)
MIL-8TD-883

Quantity/

Test
Subgroup 1
a. Steady-state life test
b. End-point electrical
parameters

6-4

(Accept No.)
Method

Condition

orLTPD

1005

Test condition to be specified
(1,000 hours at 1250C or equivalent In
accordance with Table 1.)

5

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

Section 6 - Quality & Reliability

Table 4" Group 0 (Package Related Tests)
Mll-STD-883
Test
Method
Subgroup 1 (1)
a. Phvsical dimensions
Subgroup 2 (1)
a. Lead integrity (2)
b. Seal (3)
1. Rne
2. Gross
Subgroup 3 (4)
a. Thermal shock
b. Temperature cycling
c. Moisture resistance (5)
d. Seal
1. Fine
2. Gross
e. Visual examination
f. End-point electrical parameters (6)
Subgroup 4 (4)
a. Mechanical shock
b. Vibration, variable frequency
c. Constant acceleration
d. Seal
1. Rne
2. Gross
e. Visual examination(7)
1. End-point electrical parameters
Subgroup 5 (1)
a. San atmosphere (5)
b. Seal
1. Rne
2. Gross
c. Visual examination
Subgroup 6 (1)
a. Internal water-vapor content(S)
Subgroup 7 (1)
a. Adhesion of lead finish (9,10)
Subgroup 8
a. Lid torque (1)

CondHlon

Quantltyl
(Accept No.)
or lTPD
15

2016
2004

Test condnion 82 (lead fatigue)

1014

As applicable

1011

Test condttion 8 as a minimum, 15 cycles minimum

1010
1004
1014

Test condttion C, 100 cycles minimum

5

15

As applicable
In accordance wtth visual criteria of Method 1004 &1010
As specified in the applicable device specification

2002
2007
2001
1014

Test condttion 8 minimum
Test condttion A minimum
Test condttion E minimum (see 3). VI orientation only
As applicable

15

As specified in the applicable device specification
1009
1014

Test condttion A minimum
As applicable

15

In accordance with visual criteria of Method 1009
1018

5,000 ppm maximum water content at 100'C

3(0) or 5(1)

2025

15

2024

5(0)

Notes:
1. Electrical reject devices from that same inspection lot may be used for samples.
2. For leadless chip carrier packaged only, use test condition D. For leaded chip carrier packages, use condition Bl. For pin grid array and
other rigid leads use Method 2038.
3. Seal test (subgroup 2b) need be performed only on packages having leads exiting through a glass seal.
4. Devices used in subgroup 3, "Thermal and Moisture Resistance- may be used in subgroup 4, "Mechanical".
5. Lead bend stress initial conditioning is not required for leadless chip carrier packages.
6. End-point electrical parameters are performed after moisture resistance and prior to seal test
7. Visual examination shall be in accordance with Method 1010 or 1011.
8. Test three devices; if one fails, test two additional devices with no failures. At the manufacturers option, if the initial test sample (i.e., 3 or
5 devices) fails a second complete sample may be tested at an alternate laboratory that has been issued suitability by the qualifying
activity. If this sample passes the lot shall be accepted provided the devices and data from both submissions is submitted to the qualifying
activity along with 5 additional devices from the same lot
9. The adhesion of lead finish test shall not apply to leadless chip carrier packages.
10. LTPD based on number of leads.
For More Information, calil-BOO-722-7074.

Raytheon Semiconductor

6-5

Section 6 - Quality & RellabllHy

Table 5. Typical Qualification Plan for Hermetic Packaged Devices (1)(2)(3)
Test
Group B
Subgroup 3
Solderability
SubgroupS
Bond Strength
Group C
Subgroup 1
Operational Ufe
(168,250,500,
1000,2000)
Electrical Test
25°C DC)
(2 date codes,
77 samples each)
Group 0
Subgroup 2
Lead Integrity
F&G Leak
UdTorque
Subgroup 4
Mechanical Shock
Vibration
Constant Acceleration
F&G Leak
Visual Examination
Electrical Test 25°C

Conditions Per MIL-STD-883

Quantity

Accept No.

15

0

15

0

77

1

25

1

25

1

2455°C
Condition C and record bond pull strength

16B-hour point will be used to screen out
the infant mortality failure. The sample size
after the 16B-hour point will be 77.

Condition B2

Condition B
Condition A
Condition B Min.

Notes:
1.

The above group B, C, D are run completely, if the product (package and die) has no history.

2.

Hthe package is pre-qualified, then only Group C, Subgroups 1 and 2, and Group D, Subgroup 4 are conducted.

3.

Hthe product is not JAN or 883 compliant, then 168-hour pre-burn in is not performed to screen out infant mortality prior to
Group CTest.

6-6

Raytheon Semiconductor

For More Information, call 1-800-722·7074.

Section 6 - Quality & Reliability

.
• I QuaIT
. Package oeVlces
1iable 6. 11iypica
Ilcation PI an for PIastlc
Sample
Size
45

Accept
No.
0

Test
Operating
Life

Test Conditions
Temperature 125°C
lime 1000 hrs.
Electrical Test at 168 hrs.,
500 hrs., 1000 hrs., 250 hrs.
Bias - per spec requirements

Purpose of Test
Accelerated Life

Autoclave

Pressure 15 PSiG
Temperature 121°C, >95° RH
Electrical Test at 96 hrs.,
(no metal deterioration),
144 hrs., 250 hrs., 500 hrs.

Package integrity and
moisture resistance

45

0

85°C/85% RH

Temperature 85°C
Humidity 85%
lime 1000 hrs.
(no metal deterioration)
Electrical Test at 168 hrs.,
250 hrs., 500 hrs., 1000 hrs.,

Accelerated life corrosion
resistance

45

0

Storage Life

Temperature 1500C
Determine the effect of high
Bias-None
temperature storage
Electrical Test at 144 hrs., 250 hrs.,
500 hrs.

45

0

Temperature
Cycle

Temperature -65°C to +1500C
No. Cycles 100
Electrical Test 25°C

Determine the resistance to
high and low temperatures

45

0

Thermal
Shock

Per 883 Method 1011

Determine resistance to rapid
temperature change.

45

0

Moisture
(10 Day)

Temperature -10OC to +65°C
Humidify 90% RH
lime 240 hrs.
Electrical Test at 240 hrs.
Visual Inspection of Leads

Package integrity to moisture,
lead corrOSion, etc.

45

0

Solderability

Per 883, Method 2003

To determine the solderability
of the lead finish

3

0

Lead Fatigue

Per 883, Method 2004
Condition B

To determine the physical
resistance to lead bending
fatigue

3

0

External Visual

10-30X Magnification

To evaluate physical construction and processing resultS
to package and lead frame

45

0

'2 date codes of 50 each

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

6-7

Section 6 - QualHy & Reliability

Reliability Program

Table 7. Typical Plastic Process Monitor Tests

The quality and reliability activity at Raytheon is a
thorough and continuous activity. It starts with initial
design concepts and processes, and carries through to
the finished product.

Test

Purpose of Test

Autoclave
(steam
pressure)

To evaluate the resistance of moisture
penetration of the package and the
effects of moisture on the chip under
accelerated conditions of 15 pounds of
steam pressure at 120°C.

Biased

To evaluate the operational life and
resistance to moisture penetration of the
chip and the plastic package under the
accelerated conditions of 85°C and 85%
relative humidity.

Reliability Engineering, working with Design and Product
Engineering, monitors the new device design or process
through all stages of development and remains the full
and final authority over the qualification status of all products.
Raytheon's established RA Qualification plans are used
to approve new devices, processes or manufacturing
facilities. Two examples are shown in Tables 5 and 6 for
hermetic package devices and plastic package devices.
The Reliability Department continually monitors all
product lines through product sampling, routine requalification and QCI testing of JAN and other Hi-Rei
products to evaluate failure modes and failure rates. The
results from these tests are reviewed with Product and
Production Engineering and any necessary corrective
actions are taken.

Lab Facilities
Raytheon maintains a fully equipped laboratory to
conduct its reliability, failure analysis, and environmental
testing. The typical types of tests that are performed by
this facility include:
• QCI Groups A, B, C and 0 environmental
requirements
• Destructive Physical Analysis
• SEM AnalysiS
• Microprobe Analysis/Laser Cutler
• X-ray Dispersion Analysis
• Biased 85/85 and Steam Pressure Pot (PCT)
• Highly Accelerated Stress Testing (HAST)
• Electromigration Characterization
• TDDB Testing of MOS Gate Oxide
• Hot Carrier Degradation
• ESDTesting
• PIND Testing

85°C/85%
RH

Operating
Life

To evaluate the operational field life of
the device under accelerated conditions
of 125°C.

Resistance
to Solvents

To determine that the brand markings
will not become illegible on the package
parts when subjected to the solvents and
test per MIL-STD-883C, Method 2015.

Solderability

Per Method 2004 of MIL-STD-883.

External
Visual

To determine the physical construction
and processing results to the package
and lead frame at 30X magnification.

Lead
Fatigue

To determine the physical resistance to
lead bending fatigue per Condition B,
Method 2004, of MIL-STD-883.

Thermal
Shock

To determine that the device can survive
exposure to rapid changes in temperature
from -55°C to +125°C per Condition B of
Method 1011 of MIL-STD-883.

In addition to quality control check point inspection at
every assembly step, reliability process monitoring (see
Table 7) is performed.

Plastic Package Device Monitor

The autoclave (steam pressure) test determines the
package's moisture resistance in the shortest possible
time, allowing immediate corrective action where
necessary, thus ensuring the long-term reliability of the
products.

Raytheon is a major supplier of standard and ASIC
products in plastic packages. Products are available in a
variety of plastic packages such as DIPs, SOICs, and
LCCs. Significant investments have been made in both
the technology and manufacture of high-reliability, lowstress plastiC encapsulated packages.

All products are 100% electrically tested and visually
screened followed by sample testing for electrical, visual
and mechanical defects to determine the outgoing PPM
defect rate. With a quality goal of 100 ppm or less,
Raytheon's devices have failure rates well below the
industry standards.

6-8

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

Section 6 - Quality & Reliability

Major Programs

,
,
,

Raytheon Semiconductor is involved in major programs
which require and support a high level of quality and
reliability expertise in the design, manufacture and
control of our products.

Assembly

The commercial programs address such market
segments as computers and automotive. These markets
are a driving force within Raytheon's commercial
product quality and reliability controls.

25°C DC

The most significant military program is JAN 38510
which requires a Defense Electronics Supply Center
(DESC) certification of our fabrication and
manufacturing lines. The JAN military specifications and
MIL-145208 form the foundation of our QA system,
thereby benefiting all products - JAN, 883 compliant,
DESC Standard Military Drawings (SMD), Source
Control Drawings (SCD), and commercial.

PCT Monitor

100°C Functional

An extensive statistical process control program has
been initiated which includes wafer fabrication
processing, quality assurance monitors, assembly
monitors, environmental screening and electrical testing.

t

Plastic Process
Monitor

Internal Audit Program

+

Raytheon Semiconductor maintains an internal audit
program which requires the auditing of all product
processing and control systems. This audit verifies
conformance to manufacturing and quality procedures
identifying areas needing improvement and
enhancement.

PPM QAGate
Electrical
Visual/Mechanical

+

Process Monitors

Pack

Extensive process monitors in fab, assembly and
electrical test are a critical part of Raytheon's quality
program. These enable early detection of process
problems as well as characterization of process
improvements.

+
Ship

Reliability Monitor
65-4198

Figure 5. Linear Plastic Flow Chart

For More Information, call 1-800-722-7074.

The Reliability Monitor Program monitors, on a
continuing basis, the reliability of all IC products in
hermetic and plastic packages. This program requires
that periodically several different part types from each
microcircuit technology group as detailed in Appendix E
of MIL-M-38510 be evaluated to the MIL-STO-883 Test
Method 5005 Groups A, B, C and D test requirements.
The data generated from this program provide a basic
library of reliability information on many product types

Raytheon Semiconductor

6-9

Section 6 - Quality & Reliability
and is used to provide Quality Conformance Inspection
(QCI) data to meet customer-specific group test data
requirements.

I

38510
JANClassB
USA Buih
Asssembly

f

Military Programs

Internal
Visual
M2010CondB

JAN·MIL·M-38510

f

Raytheon's foremost commitment is to the JAN MIL-M38510 program which is administered by the Defense
Electronics Supply Center (DESC) and the Defense
Logistics Agency (DLA) of the Department of Defense.
We maintain DESC certified wafer fabrication, assembly
and test facilities which allow us to provide an extensive
number of JAN QPL device types.
The JAN 38510 program is designed to provide a
consistently high reliability hermetic product
manufactured to a standard process flow and quality!
reliability program as defined in MIL-M-38510, MIL-STD976 and MIL-STD-883 and the resulting baselines.
A JAN device is identified and branded with a unique
part number as shown in Figure 7 and Table 8. The
device is also branded with our manufacturers'
designating symbol (CORP or RP), logo (RAVor R), the
sealing cycle date code, country of origin, a two-digit fab
quarter code (indicating year and quarter in which die
fabrication was completed, and the applicable
electrostatic discharge sensitivity identifier.
A current listing of Raytheon's JAN 38510 QPL devices
may be obtained by contacting the nearest Raytheon
Field Sales Office.

883 Compliant
The 883 compliant program offers hermetic products
assembled and tested to the requirements of paragraph
1.2.1 of MIL-STD-883 for Class B devices. With
Raytheon as the qualifying activity and offshore
assembly permiSSible, these devices are as close as
one can get to JAN 38510 reliability using a standard
process flow (See Figure 6).

STABake
M1008CondC
24-Hrs + 150'C

.

Temp Cycle
M1010CondC
10 Cycles
-65'C to -l50'C

J

I
I

Constant
Acceleration
M2001 Y Axis Only
PerPkg Reg

.

External Visual

.
I

Pre Burn-In
Elec Parameters
Per Device Spec

883
ClassB

Assembly

,

Bum-in
M1015

.

Post-Bum
Elec Parameters
Per APP Device

Series
.@25'C+PDA

f
Final Electrical
+25'C, -55'C,
+125'C

.

Fine Leak
M1014AorB
Gross Leak
M1014C

..

External visual
M2009

t
OCISample

Figure 6. Screening for JAN and 883 Compliant Devices

Lead Finish
Raytheon offers two lead finished - solder dipped and
matte tin plate (non-JAN only). The preferred and
recommended lead finish is solder which is tin plated
prior to dipping.
Raytheon offers a solder lead finish that will meet the
solderability requirements of MIL-M-38510.

Raytheon's 883 compliant program is complemented by
our active participation in DESC's Standard Military
Drawing program.
A current listing of our 883 compliant devices which
includes those DESC SMDs for which Raytheon is an
approved source of supply may be obtained by
contacting the nearest Raytheon Semiconductor Field
Sales Office.
6-10

Raytheon Semiconductor

For More Information. call H300-722-7074.

Section 6 - Quality & Reliability

JM 38510 I XX XXX y y y
_ _ _ _T--' -.--- - -~ - JAN prefix (which may be applied
only to a fully conformant device per
paragraph 3.6.2.1 and 3.6.7 of MIL-M-38510
MIL-M-38510 - - - - - - - - - - - - - '
Hor/---------------~

1= no radiation hardness assurance
M, D, Rand H = levels of hardness
Slash Sheet Number-----------------'
Device Number on Slash Sheet - - - - - - - - - - - - '
Screening Level S, B - - - - - - - - - - - - - - - - - - '
Package Outline Letter/Number _ _ _ _ _ _ _ _ _ _ _ _ _---'
(see Table 8)
Lead F i n i s h - - - - - - - - - - - - - - - - - - - - - '
A =Solder Dipped
Figure 7. MIL-M-38510 Part Marking

Table 8. JAN Package Codes
38510 Outline
Letter/Number

38510 Type
Designation

A
B
C
D
E

F-1
F-3
D-1
F-2
D-2
F-5
A-1
F-4
A-2
D-3
F-6
D-9
D-4
D-5
D-8
F-9
D-6
C-2
C-4

F

G
H

I
J
K
L
P
Q

R

S
V

2
3

For More Information, call 1-IlOO·722-7074.

Description
14-lead, 1/4 x 1/4 Cerpak
14-lead, 3/16 x 1/4 Cerpak
14-lead. 1/4 x 3/4 Cerdip
14-lead, 1/4 x 3/8 Cerpak
16-lead, 1/4 x 7/8 Cerdip
16-lead, 1/4 x 7/8 Cerpak
8-lead, TO-99 can
10-lead, 1/4 x 1/4 Cerpak
1O-Iead, T0-1 00 can
24-lead, 1/2 x 1-1/4 Cerdip
24-lead, 3/8 x5/8 Flatpak
24-lead, 1/4 x 1-1/4 Cerdip
8-lead, 1/4 x 3/8 Cerdip
40-lead, 2 x 5/8 DIP
20-lead, 1/4 x 1-1/16 Sidebraze DIP
20-lead, 1/4 x 1/2 Cerpak
18-lead, 1/4 x 5/16 Cerdip
20-terminal. 3/8 x 3/8 Chip Carrier
28-terminal, 1/2 x 1/2 Chip Carrier

Raytheon Semiconductor

6-11

Section 6 - QualHy & RellabllHy

6-12

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

Section 7 - Application Notes

Section 7
Application Notes

Contents
AN-25
TP-6A
TP-17B
TP-31
TP-33
TP-40
TP-47B
TP-49B
TP-50A
TP-51A
TP-52A

RC4151/52153 Voltage-to-Frequency Converters .....................................................................7-3
An Introduction to the Z Transform and its Derivation ............................................................. 7-33
Correlation ... A Powerful Technique for Digital Signal Processing ......................................... 7-57
An Introduction to Two Different Finite Impulse Response Structures ..................................... 7-81
Using the TDC1034, TDC1018, TDC1141 and TDC1112 in a TIL Environment .................... 7-89
Non-Linear Operations with the TMC2301 Image Resampling Sequencer ............................. 7-93
The TMC2302P5C Demonstration Board .............................................................................7-105
TMC2242 Topics: Operation with 8-Bit VO, Comparing with Analog Anti-Aliasing Filters,
3 dB Better SNR Through Oversampling .............................................................................. 7-137
The Evaluation Board for the TMC11751TDC331 0 ............................................................... 7-149
A Demonstration Board for the TMC22090 Digital Video Encoder ........................................ 7-163
Bilinear Interpolation in Polar Coordinates ............................................................................7-185
RC419314391 Switching Regulators .....................................................................................7-192

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

7-1

Section 7 - Application Notes

7-2

Raytheon Semiconductor

For More Information, caJI1-800-722-7074.

AN-25

RC4151152/53

Voltage-to-Frequency Converters

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

7-3

AN-25
Contents
Page
INTRODUCTION ............................ 3
BASIC OPERATION ......................... 3
Comparison of the 4151
and 4152 to the 4153 ..................... 4
Frequency-to-Voltage Conversion ........... 6
INTEGRATORS AND AID's
Long Term Integrators ..................... 8
Design Example-Sun Power Integrator ..... 8
Low Level AID Converter ................... 8
Process Trend Indicator .................... 9
Ratio Computers .......................... 11
OSI Microprocessor DVM ................. 12
DATA TRANSMISSION
VFC Isolation .............................
Fiberoptic Transmitter .................... ,
4153 FSK Modulator ......................
4151/2 FSK Modulator ....................
Digital Frequency Encoding ...............
Bipolar Telemetry Scheme ................
Two-Wire Transmitter .....................
Tape Recording ...........................

15
16
17
17
18
18
21
21

MOTOR SPEED CONTROLS ................
Pulse Width Modulation Speed Control ....
Open Loop Switching Control .............
Series-Pass Summing Control .............
Phase Locked Loop Speed Control ........

22
22
23
23
24

MISCELLANEOUS APPLICATIONS ..........
Titrator ...................................
VCO Stabilization .........................
Staircase Generator .......................

26
26
26
27

APPENDIX Signal Conditioning ..............
Transducer Bridge ........................
Absolute Value Circuit ....................
FVC Signal Conditioning ..................
Other Application Ideas ...................

29
29
29
30
31

Figure

1
2
3
4

5
6
7
8

9
10

11
12
13
14

7-4

Title

Page

VFC Block Diagram .................. 4
4153 Timing Waveforms .............. 4
4151/4152 Timing Waveforms ........ 5
Scale Factor vs.
Typical Peak Nonlinearity .......... 6
10kHz Full Scale Temperature Drift .. , 6
100kHz Full Scale Temperature Drift .. 6
10kHz V-to-F Nonlinearity ........ " .. 6
50kHz v-to-F Nonlinearity ........... 6
100kHz V-to-F Nonlinearity ........... 6
Frequency-to-Voltage Conversion .... 7
Second Order Active Filter ........... 7
Simple Integrating AID Converter .... 9
Sun Power Integrator ................ 9
Low Level Pulse Width
AID Converter .................... 10

Figure
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53

Title

Page

High Resolution Pulsel
Period AID Converter ............. 10
Process Trend Indicator ............ 10
Amplitude Ratio Computer .......... 11
Precision VFC Ratio Circuit ......... 11
Block Diagram for OSI
Microprocessor DVM ............. 12
Complete Microprocessor DVM ..... 13
OSI Program Listing ................ 14
VFC-FVC Transmission ............. 15
VFC Isolation ....................... 15
VFC Optoisolator ................... 15
Fiberoptic Transmission ............ 16
4153 FSK Modulator ................ 16
4153 FSK Component
Values for 300 Baud Bell .......... 17
FSK Modulator Using 4151/2 ........ 17
4151/2 FSK Component Values
for 300 Baud 103 Standard ........ 17
Digitally Controlled
Frequency Generator ............. 18
BCD Input Clock Generator ......... 18
Bipolar Telemetry Scheme .......... 19
Bipolar Telemetry Receiver .......... 19
Bipolar Telemetry Transmitter ....... 19
Bipolar Telemetry Waveforms ....... 20
Two Wire Transmission System ..... 20
Tape Recorder Interface ............ 21
FVC Provides Error Signal .......... 22
FVC Provides Ramp for PWM ....... 22
Pulse Width Modulation Waveforms . 23
VFC Provides Open Loop
Switching Control ................ 23
Series Pass Summing Controller .... 24
Phase Locked Loop Speed Control .. 24
Phase Locked Loop PWM Waveforms 25
Phase Comparator Relationships .... 25
Chloride Titrator .................... 25
Voltage Controlled Oscillator ........ 26
Staircase Generator ................ 27
Staircase Generator Waveforms ..... 28
Transducer Bridge .................. 29
Absolute Value Circuit .............. 30
FVC Input Conditioning ............. 30
FVC Timing Waveforms ............. 30

Raytheon Semiconductor

For More Information call 1-800-722-7074.

AN-25
RC4151/52/53
Voltage-to-Frequency Converters
Application Notes
Prepared by

Bruce Moore

INTRODUCTION
A Voltage-to-Frequency Converter (VFC) acts
just as the name suggests: it converts a DC
input voltage into a pulse output frequency. As
the magnitude of the input voltage increases,
the output frequency increases. This is a linear
relationship, and high linearity means
accuracy in conversion. By connecting the
frequency output to a digital counter, and
counting for a precise interval, a binary number
is stored directly proportional to the input
voltage. This creates a voltmeter, or integrating
AID converter.
The conversion is accomplished with a charge
balanced feedback loop. This analog method
of conversion and its inherent linearity assure
that over the entire range of input voltages,
there will consistently be a proportional binary
code from the counter. This means that the
system is inherently monotonic. Specifically, a
converter with .01 percent nonlinearity has
accuracy and monotonicity equivalent to a 12
bit parallel AID converter.
When compared to the other methods of NO
conversion, the VFC's disadvantage is longer
conversion time, equal to the sample period.
This disadvantage can be a positive design
feature for measurements in a noisy
environment, because the longer sampling
period averages out noise. The conversion time
may be reduced by using a VFC which is
accurate at higher frequency. Raytheon's 4153
VFC can give 3-1/2 digit conversion in less than
5mS. Successive approximation techniques
are fast, but very sensitive to noise. In
comparable systems, the three different
methods of conversion are equivalent in
resolution, temperature sensitivity, and
nonlinearity. Dual slope conversion is a
compromise betweeen successive
approximation and V-to-F conversion, because
it has good noise rejection and a moderate
conversion time.
For More Information call 1-800-722-7074.

Modern integrated circuit technology made the
VFC a cost effective alternative to these other
NO systems. A few years ago the VFC was a
black box; bulky and expensive. Then hybrid
and modular versions were introduced,
bringing efficiency and priced under one
hundred dollars. In 1976 Raytheon introduced
the world's first monolithic VFC, the 4151.
Since then the 4152 and 4153 have been
designed, for increased performance and with
fewer external components. Raytheon's
monolithic converters offer competitive
performance when compared with modular
versions, while providing increased flexibility
in modifying design parameters, and costing
much less.
The future will see increased use of VFC's in
places where other methods of conversion are
presently employed in addition to a variety of
newer non-conventional applications. The
advantages of VFC's are in their size, cost, and
serial output, which allow them to be located
near the source of analog data. VFC's can
provide the inverse function, frequency-tovoltage conversion. Raytheon converters can
be connected in a number of configurations to
fill most needs. The applications described in
this publication include microprocessor
interfacing, motor speed controls, phase lock
loops, and other unique circuits.

BASIC OPERATION
The output of a VFC consists of a series of
negative going pulses. The pulse width remains
constant (one shot period determined by
external components) while the duty cycle
varies in response to the input voltage. Thus it
is an AID converter with a serial output. Figure
1 and 2 show the prinCiples of a positive input
precision mode VFC using a 4153.

Raytheon Semiconductor

7-5

AN-25
Integrator
CIN

VIN

E
Open Collector
Output

Fig. 1 VFC Block Diagram

...1,,-----

VIM

____
+5V

o
A

lflfl1ml

-10

B

+fOV.

.

Switched Currenl
Source Output
-1.0mA

~

S.C.S. logic [lnlBrnall

C

o

f1l\f\IT
lflfl1ml

-O.65V

One Shot Timing (COl
-4.1V T =1.5 x fO'CO

+Vcc

Logic Output
~O.2V

VIN
fO = 2VREFRINCO

Fig.2 4153 Timing Waveforms

The heart of a VFC is the switched current
source, which can deliver discrete amounts of
charge precisely controlled in amplitude and
duration.
7-6

The integrator algebraically sums the positive
current, VINlRIN,with the negative current
pulses from the switched current source. This
integrated sum (waveform C of Figure 2) is
applied to the trigger input of the one shot. If
that voltage becomes less than the trigger
threshold, the one shot fires, pulsing the
switched current source and the logic output
(waveform E). The lOUT pulse from the current
source causes the integrator output to ramp up
for the period of the one shot, and then ramp
back down to the trigger voltage. The slope of
this downward ramp is proportional to the input
voltage. The system acts as a charge balanced
loop, with the interval between one shot firings
determining the duty cycle, proportional to the
input voltage. To summarize; the one shot
works continually, by increasing the frequency
of lOUT pulses, to keep the output of the
integrator above the trigger threshold. If the
positive input increases the frequency of
negative lOUT pulses will increase to keep the
integrator output high.

Comparison of the 4151 and 4152
to the 4153
The 4151 and 4152 operate much like the 4153,
except for differences in polarity and voltage as
Figure 3 illustrates. For the precision circuit,
the input voltage must be negative, because the
switched current source output is positive.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

AN-25
VIN _ _ _ _~

5V

Y

------lOV

A

B

fUJLillU1JliUlJ

+135"A

0 Switched Current Source Output

u-tlTIJlJ1illUl

Internal One Shot Output

A A A 11 II A II t1 11 2/3 Vee
(UU U UUUUUL One Shot Timing (CO)

o

V;~F

T = 1.lRoCo

0

~

T=l.lROCo
+Vee

E

Inn
n nnnnnn Logic Output fo = O.395~
(VIN)
U U U UUUUUUI OV
RBRoCo
T =...L
fo

Fig.3

4151/4152 Timing Waveforms

Consequently the integrator ramps up to the
one shot threshold instead of down. The one
shot comparator threshold is set externally,
and the one shot waveform is inverted. The
equations for one shot time and output
frequency also differ. These differences are
attributable to the philosophy with which the
4153 was designed. The 4153 was intended to
be connected in the precision configuration,
and contains an internal op amp. The current
output was made negative so that the input
voltage would always be positive. This function
meets more user needs than the requirement of
a negative input and allows the use of high
performance NPN transistors in the switched
current source.
The 4151 was the first monolithic VFC,
providing the basic function at low cost (less
than one dollar in quantity). The 4151 was
followed by the 4152 as a pin compatible
replacement offering improved specifications,
especially temperatu re drift. The 4153
combines the basic components with an on
board op amp to minimize the number of
external components required for precise
applications, giving the user additional
convenience and improved specifications for
temperature drift and linearity, especially at
frequencies over 10 kHz.
For More Information call HI00·722-7074.

The graphs in Figures 4 through 9 show the
differences in performance of the three
Raytheon VFC·s. The curves for the 4151 and
4152 were derived with the VFC in the currentsourced precision circuit from the 4151/4152
Data Sheet. The voltage-sourced circuit is
slightly different, it has pin 1 (10) connected to
ground rather than to the summing mode of the
op amp. When compared to the currentsourced circuit, the voltage-sourced circuit
optimizes temperature performance at the
expense of linearity.
Figure 4 depicts how linearity is degraded with
increasing full scale frequency. Degradation
occurs because of switching problems in the
one shot affecting the total amount of charge in
each 10 pulse. Variations from the precise
charge cause deviations in the integrator
output, affect the intervals between triggering,
and change the output frequency from its ideal.
Notice that the 4153, with its high speed ECl
logic, has improved high frequency linearity.
Temperature drift is affected by increasing
frequency as illustrated in Figures 5 and 6 at 10
kHz and 100 kHz. The 4153, with its buried
zener reference, outperforms the 4151 and
4152. The reference, the switched current
source, the resistor and capacitor temperature
coefficients all contribute to temperature drift.

laytheon Semiconductor

7-7

AN-25

!

0.18

=E

0.12

.s

i

0.15

0.09

~

0.06

/

.~

0.03

. /,../

= 30~60~90

....-

II

~

120

10.00

~
>-

---

150

180

S 9.95

4153

9.90

210

-

10.05
f-----

/

// /

:z

I-

/~152

4151/

.~
g

10.10

L

/

- -V
/'

20

-20

'-

I

-

101

;... .

' ...
"""" . ~

.......

,.,

99

~ ~ .....

>-

:~

':.~2

'" ,

"

-0.005

r".

c

~ -001

4f ,.,-V
'4f
I

.........

I

41t\
20

-20

40

60

80

100

9

120

Fig. 7 10KHz V-to-F Nonlinearity

+0.02

+0.06
+0.03

+0.01

~

E

......
-0.02

10

Input Voltage

Fig.6 100KHz Full Scale Temperature Orift

z:

120

.... :/V

4153

r--..

Ambient Temperature ro CI

-0.01

100

+0.005

I

~
"

97
-60 -40

..::;:

80

4)53

98

~

60

+0.01

'-,

.~
g

40

Fig. 510KHz Full Scale Temperature Orift

102

c

\

Ambient Temperature [' CI

Fig. 4 Scale Factor vs. Typical Peak Nonlinearity

~
>~

'''\ 4152
4151

Full Scale Frequency [scale lactorl

~ 100

-- -

/'

9.85
-60 -40

240 KHz

-

4153

1- ..... .....
_,-r'" ===
-::' ..... t--_

-- r--., --

~

"-.

'1 -1/~
4153

2 .-

~

:.

'7

:~

I~ ~
"
-0.03

z:

4T

~~"

g

V

9

e:.>-0.06

4153

"-.

41~

-

~~

.... -:>

r--

../

.1 . /

4T

9

10

10

Input Voltage

Input Voltage
Fill. 850KHz V-to-F Nonlinearity

Fig. 9 100KHz V-to-F Nonlinearity

For absolute best performance use a
temperature stabilized external reference, such
as an LM199, heat the 4153 with an external
heater, measure, then select resistor and
capacitor temperature coefficients.

the frequency of the pulses (see Figure 10). The
higher the frequency is, the higher the DC
output voltage becomes. This mode has one
inherent problem - the DC output contains a
ripple component equal in frequency to the
input pulses. The proper use of filtering can
reduce this ripple, but will also decrease the
response time. A trade off must be made
between response time and ripple. Generally
the filtering should be as large as the

Frequency-to-Voltage Conversion
A VFC can also work backward. With a change
in configuration the VFC will convert an input
pulse train into a DC Voltage proportional to
7-8

Raytheon Semiconductor

For More Information call HlOO-722·7074.

AN-25
RB

+Vee

CB
10K
Trig

fiN

o-ft--.--..,
0.002

VOUT

5K

Fig. 10 Frequency-Io-Vollage Conversion

RI
10

>-....-oVOUT

Fig. 11 Second Order Active Filler

acceptable response time will allow. The width
of the pulses from the incoming frequency
must be less than the period of the one shot
(see appendix, FVC Signal Conditioning).
The input triggers the one shot, switching the
current source, thereby delivering a well
defined amount of charge to the op amp
integrator. This produces an average voltage at
the output proportional to the repetition rate Df
the incoming pulses. Replacing the single pole
integrator with a second order (double pole)
filter improves response time and output ripple
(see Figure 11).
The ratio of the time constants R1 C1 and R2 C2
determines the response to a step change in
input frequency. The response will be critically
For More Information call 1-800-722-7074.

damped if R1 C1 = 4(R2C2). Optimal results are
obtained when R1 C1 = R2C2, which provides a
damping factor of one half. Choose capacitors
C1 and C2and the oneshot timing capacitor for
minimum ripple over the desired range of
operation. Empirical tests show that the peak to
peak ripple is less than 100 mV (10 Hzto 10 kHz)
when R1 = 100K and C1 = 0.1 microfarad.
Frequency-to-voltage converters are useful in
analog transmission systems where a VFC
transmits a pulse train over a twisted pair to be
received by a FVC. The FVC converts this back
into a voltage for analog signal processing or
chart recorder output. Other uses include
motor speed controls, phase lock loops,
frequency scaling, and FSK demodulation.

Raytheon Semiconductor

7-9

AN-25
INTEGRATORS AND AID'S
Long Term Integrators
Accurate analog integrators which operate
over a wide dynamic range or which integrate
over extended periods are difficult to build.
Expensive, low drift, low leakage op amps and
capacitors can be replaced by a voltage-tofrequency converter and a counter. The signal
to be integrated is converted to a frequency and
counted over a known sample period,
providing a total count equal to the time
integral of the signal (See Figure 12).
jVT = K jFdt = KJ dNT

dt
~ = KN

An integrator is an AID converter with a long
sampling period. With many AID conversions,
such as a DVM, the task is not to get integration
over long periods but rather to get accurate
resolution in a short period. VFC's are scaled to
give many pulses in this short period, in order
to achieve a high binary count (increasing
resol ution).
For fast conversion, the 4153 offers the best
linearity and temperature accuracy at high
frequency. 3-1/2 digit accuracy may be
obtained in 5 mS. This is comparable to many
dual slope converters, at a lower cost, while
retaining the transmission advantages of a VFC
converter.

where N = Total count
and K = VFC Scaling Constant

Design Example - Sun Power Integrator
Digital
} Output

Fig. 12 Simple Integrating AID Converter

In addition to their ability to integrate over long
periods of time, VFC AID converters have the
following advantages:
1. Wide dynamic input range due to inherent
VFC linearity (10,000 to 1).
2. The process can be interrupted without
affecting the integrated value (no droop
due to RC time constants).
3. The output may be directly interfaced to a
digital information processing system, used
for a seven segment display or converted
back to analog with a low cost DIA
converter.
4. The. digital counter may be preset to any
desired value before integrating up
(or down).
5. The resolution and conversion speed are
totally controlled by the system designer.
6. VFC AID's have high monotonicity due to
their inherent linearity.
7. High noise rejection when integrating with
a sample period longer than the period
of the noise.
7-10

The following example is a system that
integrates the amount of sunlight on a photo
cell over a 12 hour period. The maximum
output of the cell is 5 volts, and the visual
display must be accurate to 3 digits. Since it is
easy to convert a binary count to decimal
display with a binary to seven segment
counter-driver, such as an ICM 7225, we need
to select a VFC scale factor which will give us a
count divisible by 10 after our 12 hoursampling
period. The minimum scale factor is 1 Hz per
volt, so the output must be equal to or greater
than 10Hz full scale. There are 43,200 seconds
in twelve hours, so 43,200 is the minimum
binary count per volt. The components used for
1 Hz per volt are somewhat unwieldy, therefore
a larger scale factor must be used. If we use a
maximum binary count of 5 million for 5V input,
a 1 million binary count will equal one volt over
12 hours. One million pulses per 43,200
seconds equals a scale factor of 23.15 Hz per
volt. This allows more reasonable values of
resistors and capacitors (see data sheet for the
specific VFC being used). The seven segment
counter driver automatically decodes binaryto-decimal, however with insufficient binary
counting stages internally, a pre-counter must
be added. By moving the decimal place six
places the display reads directly in volts.
The time base can be made from a 555 timer
operating at low frequency. The 555's output
can be divided further by feeding it into the
clock input of a counter, giving extremely long
sample periods from the MSB output.

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

AN-25

} Digital
Output

Fig. 13 Sun Power Integrator
Fig. 14 Low Level Pulse Width A/D Converter

Low Level AID Converter
A disadvantage of conventional VFC AID
converters is that the resolution of small signals
is not as good as for large signals. Small
voltages give a total count much less than the
capacity of the counter, reducing accuracy,
even though the output of the VFC is highly
accurate. The normal solution is to add a
preamplifier for small signals. However, this
causes errors and must be switched out to
measure large signals. When small signals
must be processed, measure the period, rather
than the frequency of the VFC output, by
counting a high frequency reference oscillator
during the interval between VFC pulses.
The leading edge of the first VFC pulse toggles
the flip flop high, enabling the counter to begin
counting the 1 MHz oscillator frequency. The
leading edge of the second VFC pulse toggles
the flip flop again, disabling the counter. The
counter now holds a binary count inversely

proportional to the voltage input. In this
system, the smaller the signal, the greater the
resolution. Note that the input must be large
enough to provide at leasttwo output pulses, so
the interval between them may be measured.
The input may have a small DC bias applied to
it, placing it on the threshold of producing an
output, to provide resolution in microvolts. This
technique is very useful for measuring low level
transducer outputs, such as a thermocouple.
The circuit of Figure 14 has the opposite
problem of the conventional VFC AID
approach. Large signals applied to the VFC
cause a small period, and therefore lower the
resolution, because fewer oscillator pulses will
be counted. The problem is solved when we
combine both techniques. The next circuit
measures both the period and the frequency of
the VFC output.

VFC
Pulse Count. N

VIN

~
/

Clock

Period
Counter

Digital
Outputs

Fi rst to Last
Pulse Time, T

1

Fig. 15 High Resolution Pulse/Period AID Converter

For Morelnlonnation call 1-800-722-7074.

Raytheon Semiconductor

7-11

AN-25
Process Trend Indicator
With the conventional technique of VFC
integration (Figure 12), the digital count is a
true representation of the integration only after
the sampling period is completed. To get an
integration after some intermediate time, more
counters with different sampling periods would
be required. The following system is another
long term integrator, but has the advantage of
continuously updating the digital output with a
short sampling period.

which now supplies the new output. The output
of the latches can be used as the digital
integrated output. The time derivative of the
integration (the degree of smoothing) is
determined by the scaling of the inputs to the
differential amplifier and by the scaling of the
input to the VFC. The change of the output
between samplings is proportional to the
difference between the present output and the
new input.

The differential amplifier at the input subtracts
the present VouTfrom the input. This difference
signal is put through an absolute value circuit
and a scaling pot, which applies a positive
voltage proportional to the magnitude of the
differential input to the input of the VFC. During
the sample period, the up/down counter counts
the output frequency of the VFC. The counter
counts up ordown depending on the sign of the
output of the differential amplifier. If the
present output is greater than the input, it
counts down. If the input is greater, it counts
up. At the end of the sampling period the count
is latched into the input of the D/A converter,

The two counters are controlled by aD-type
positive edge triggered flip flop. The lower one
stores a count proportional to the time between
the first pulse and the last pulse in the sample
period. The upper one is clocked by the VFC
output pulses and stores the total number of
VFC pulses in the sample period. Deriving the
period between pulses and the input voltage is
simple arithmetic since we know the total time
for a number of pulses. Now we have a flexible
system that will measure a wide range of input
voltages with high resolution without the use of
expensive components.

Pick Up/Down
Differential
Amplifier
VIN

VOUT

Digital
} Output
Analog
Output

Fig. 16 Process Trend Indicator

7-12

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

AN-25
Ratio Computers
Sometimes a need arises for a circuit that
provides an output proportional to the ratio of
two input signals. Examples include power
measurement and transfer function
determination. The circuit shown in Figure 17
uses two VFC's and some digital processing to
produce a binary number proportional to the
ratio of two input signals. This digital output
may be used directly or converted back to a
voltage with a D/A converter. VIN2 is converted
to a square wave by the flip flop. This square
wave (divided by 2) is used to gate the output of
VFC 1. Thus, the number of pulses from output
one per pulse of output two is counted. Note:
The frequency from VFC 1, and therefore the
input to VFC 1, must be more than or equal to
that of VFC 2.
VI
Count Out = K '/,V2

System timing must be tailored to individual
applications. Many modifications to this design
are possible. For example, over/under range
alarms, channel steering for ratios less then
unity, or dB or other non-linear conversions by
the use of ROM's in decoding.
Another economical method for achieving ratio
measurements that can be accomplished easily
with a VFC is measuring resistance ratio. This
could be done with the previous circuit by
using a bridge and differentially amplifying the
output, and then measuring the ratio between
the supply voltage and the differential amplifier
output. This application will achieve highly
accurate results, but there is another method
that uses only one VFC in the precision mode
(see Figure 18). The equation for output
frequency of the 4152 is:
fo

=

L

.486 ~~
\ RoCo /\ Rs 7 VIN

The output frequency is directly dependent on
the ratio
Rs
Rs

VIN 1

VIN2

The resistor to be trimmed is connected to the
Rs position. The reference resistor is
connected to the Rs position. VIN is adjusted to
-9.67 volts. When the ratio is unity the output
frequency will be 10 kHz. The output could be
compared to a reference frequency or read on a
frequency counter. Note: this application will
not work with a 4153 because the Rs resistor is
internal and cannot be adjusted.

D Flip-Flop
Digital Output

Fig. 17 Amplitude Ratio Computer

VIN

+Vee

RB

CI
10K

5.1K

RO

100n

A similar application is measuring capacitance.
By using the same precision mode circuit, we
can derive the value of the Co by making Rs, Rs,
Ro and VIN constant. The output frequency is
proportional to
Co

Co

-=
Fig. 18 Precision VFC Ratio Circuil

For More Information call 1-800·722·7074.

and the period is directly proportional to the
capacitor-under-test Co. If the need is to
compare a capacitor with a reference
capacitor, or the measure a single capacitor
value in high volume, then the output can be
compared to a reference frequency. The
difference, or beat, frequency may be
monitored as an audio signal as well as read
with a counter.

Raytheon Semiconductor

7·13

AN-25

VIN

Fig. 19 Block Diagram ior Microprocessor DVM

,

I
OSI Microprocessor DVM
VFC integrators and AID converters are very
useful in microprocessor controlled systems.
Several similar sources of analog data may be
multiplexed and then converted with one VFC
and counter, or several individually tailored
converters may be digitally multiplexed. The
sampling period can be derived from the
system clock and modified with software to
compensate for different scale factors. Offset
drift and gain errors can be automatically
compensated with an auto-zero approach.
The greatest source of error in VFC converters
is scale factor drift. The temperature coefficient
of the 4153 is guaranteed at 50ppm/o C with an
external reference. Using resistor and
capacitor temperature coefficients of 50ppm,
the worst case temperature coefficient would
be about 150ppm/o C. This would lead to a
±.15% error over a 10°C range. This can be
corrected by a careful selection of
components, but there is a better approach. By
applying a known reference voltage to the VFC,
a correction term can be generated to
automatically eliminate gain error and offset
drift. The correction term can be applied within
7-14

the program or through a D/A convertor to the
VFC. Thermal changes occur slowly in most
systems, so the scale factor updating cycle is
typically run at a small fraction of the signal
conversion rate. In systems requiring very low
data rates, program a calibration cycle
immediately ahead of the signal conversion
cycle.
Figures 19 and 20 show in detail a DVM using a
4153 and an Ohio Scientific C1P
microcomputer. The 6502 microprocessor in
the C1 P controls the counters, and puts the
data in memory for display on a CRT.
A 4153 connected for 1 kHz full scale operation
clocks two four bit counters, which in turn are
buffered into the microprocessor data bus.
Control of the buffers and counters is derived
from the microprocessor address bus via hardwired logic and an eight bit latch. Figure 19
shows the block diagram and Figure 20 shows
the complete schematic.
The program first clears the display, takes 10
sample readings and averages them, then
displays the result. We will look at the program
step by step and follow the operation in the
diagrams.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

g
;::
iii

0

SO'

3II>

5V

d'.

0

:>

~

-

Irom
Computer

~

0

3 20 2
4
5
7
6
8 373 9
12
13
14
15
17
16
18
.19

Do
D1
D2
D3
D4
D5
D6
D7

~
CJ
~

III

DOo
D1
D02
D03
D04
D05
D06
D07

8·Bit Latch

5V

-15V 15V

10
9
'16

5.1K I

A~

Au

I
CD

o

::J

fC

3
0'
o

2 161 5
14
01
13
12

Am
AA

~~

CompuMr

~~6
lpo
,
A2 A5
A3
A1

7
3

120K

~

5V

13

A11
3 4
Ao o>--~------_-.J

Do
D1
D2
D3

g,
c

a
...o

,,,-'pl
I m"
i,·'

1111

-=

J.

-=

N

IIII

15
F7FE

7 10
111---...J
t-~D~1~5--------------------J114
3
D16
13 161 4
017
.12
5
11
6
_

To
Computer

D4
D5
D6
D7

A1 RC725, RC4807 or equivalent
0

-=

5V

-=

Tri·State
8uffers

Fig. 20 Complete 051 Microprocessor DVM

4·8it
Counters

~•

~

~

U1

Application Notes

AN-25
REM = Remark
10 X=236
20 S=10
30 FOR Y=1 TO 5:PRINT:NEXT
40 A1=0
50 FOR V=1 TO 5
60 POKE 63487,0:REM Clear Counters
70 POKE 63487,255:REM Start to Count
80 FOR T=O TO X:NEXT
90 POKE 63487,253:REM Stop Count
100 A=PEEK(63486)
110 A=10.004* A/253
120 PRINT A
130 A1=A1+A
140 NEXT V
150 A1=A1/S
160 A1=.01 *INT(100* A1)
170 PRINT"READING";A 1;"VOLTS"
180 PRINT
190 GOTO 30
Figure 21. OSI Program Listing

The first four lines initialize the program, clear
the output variables, and erase the display. Line
50 sets up the iterative loop for the averaging
routine. Lines 60 through 100 actually take the
measurement. The addresses that the hardwired logic was designed for were selected by
checking the memory map for unused
locations. Line 60 addresses location F7FF,
which latches in the binary number 0 from the
data bus. The latch output resets the two binary
counters to zero, and keeps them from
counting until the next program line. Line 70
again addresses the latch, and the data bus
word enables the count to begin. The next two
lines are an iterative loop which sets the sample
period, which ends when the latch is again
addressed. The counters now contain a binary
number proportional to the VFC output
frequency. Note that there are 6 unused latch
outputs which may be used for other purposes.
The program now addresses F7FF, which
selects the tri-state buffers and loads the
counter outputs onto the data bus. The
measured count is converted to an equivalent
voltage reading by finding ratio of that count to
the full scale count and multiplying it by what
has been defined as the full scale input voltage.
7-16

VIN =

N
NFS

(VFs)

Where N = present count, NFS = full scale
count, and VFS = VIN for full scale count.
In this application 10.004 volts was applied to
the VFC, and the sampling period was adjusted
until the counters had counted without going
overflow (in this case 253, due to non ideal
timing increments).

Example
When 3 volts is applied to the VFC, the counter
will count to three tenths of the full scale, or 76.
Accuracy to within three digits is obtained by
dividing 76 by 253, which equals .30039.
Multipling the result by 10.004 will yield an
answer of 3.005 volts. When this is combined
with the averaging techniques, it will provide
three digits of accuracy consistently. This
allows for scale factors other than those
divisible by ten.
Line 110 provides this computation, and lines
120 through 150 are part of the 10 reading
averaging technique. Line 160 truncates the
unneeded digits, as the accuracy is limited by
the 8-bit data capacity. The last lines display
the final averaged result and loop back to the
beginning of the program. The value of S set in
line 20 determines the number of samples
averaged. Line 120 prints the individual voltage
readings, and may be deleted after debugging
is completed.
Our system was constructed using two
separate P.C. boards; one for the interface, the
other for the 4153 and counters. The interface
can then be used for other purposes. All the
IC's in the interface are 54174 Series TTL, so the
interface may be used with any microprocessor
with a compatible bus, providing the two
address codes are in unused locations.
The 4153 is set up for approximately 1 kHz F.S.
operation, but the user can and should
experiment with results. The 4153 input is
buffered by a voltage follower in order to
minimize circuit loading. In order to minimize
temperature drift and nonlinearity, good
grounding practices, well bypassed supplies,
and low temperature coefficient components
should be used.

Raytheon Semiconductor

For More Information call 1-800·722·7074.

AN-25
Analog
Input

~OUT
VFC

J'J'

Fig. 22 VFC -

DATA TRANSMISSION
Telemetry (remote monitoring) is an
application that is well suited for converters.
Analog information can be transmitted through
environments of high electrical noise (such as a
manufacturing facility) or over long distances
while retaining a high degree of accuracy.
While this application could work with
conventional AID and 01 A converters
transmitting parallel data, or through a parallel
to serial converter, a simpler cost effective
solution exists. A VFC converts the analog
signal directly to serial form, where it is
transmitted to a FVC for reconstruction of the
analog signal, or is converted directly to digital
via a counter and latch.
The open collector output of the VFC can be
used directly for twisted pair lengths of several
hundred feet. For distances of several
thousand feet a line driver and receiver can be
used. Longer distances will require radio or
telephone FSK transmission.

Output

VIN

~IN Reconstructed
FVC

Analog
Output

FVC Transmission

The VFC is powered by a floating power supply
and transmits a pulse train to the medium. The
medium is usually an optoisolator (LED and
photo transistor in one package), but it could
be a transformer or even a speaker and
microphone. The medium can also serve as the
transmission line, i.e., an optical fiber, infrared, or radio transmitter. The pulses from the
medium can be reconverted with an F to V
converter or used for direct digital output.
Figure 24 shows a circuit which uses an LED
and a phototransistor to provide electrical
isolation between the transducer and the rest of
the system. This is generally used to protect
microcomputers from transient voltages and
grounding problems, or where a transducer
has a high voltage on it.
The optoisolator is pulsed directly by the VFC
at the relatively low level of 10mA, conserving
power. One stage of gain is added to the
receiving side. the light emitted by the LED
provides base current to turn on the
phototransistor, turning off the output
transistor and giving a logic High out. This
circuit has a wide bandwidth and will drive at
least 6 standard TTL loads.

+5V (Local)
+15V (Isolated)

Fig. 23 VFC Isolalion
Logic
Output

VFC Isolation (figure :!3)
Some applications require that the transmitter
be electrically isolated from the receiver due to
high voltages existing between them. The
classical solution is to use an isolation amplifier
and an AID converter. For high accuracy (12
bit) the cost of these becomes prohibitive when
compared to VFC isolation schemes.
For More Information call 1-800·722·7074.

VIN

Raytheon Semiconductor

Fig. 24 VFC Oploisolalor

7·17

AN-25
light received by the photodiode is converted
into a small current. This current is amplified by
A1 and applied to the comparator, A2. This
hysteresis comparator has an adjustable
reference to set the threshold for the logic
output. The circuit as shown has a bandwidth
sufficient to handle 20 kHz signals.

Fiberoptic Transmitter
Figure 25 shows a typical scheme for isolation
and transmission using a precision VFC and
fiberoptics.
Most fiberoptic transmitters require currents in
excess of the output drive capability of
Raytheon VFC's. Since the current must be a
pulse of short duration and the VFC supplies
negative going output pulses, the output is
inverted with a PNP transistor, 01. This
transistor must be selected for a current
capability equal to the requirements of the
transmitter. Pulses of light are sent through the
fiber to be received by the photodiode. The

A common requirement of communications is
the transmission and decoding of binary data
as two or more discrete frequencies. This
frequency shift keying function is easily
implemented using a VFC, 2 transistors, and a
flip flop. Two circuits are shown, one using a
4153, and the other a 4151 or 4152.
Receiver

Transmitter

+5V (Local)

+15V (Isolated)
100n

100K

+5V

Fiber Optic
light Pipe

limiting
Resisitor

A1
A2

=

=

50K

200pF
Photodiode

ffo:::/ 0

2K
100K

RC301
RC311

-5V (Local)

Fig. 25 Fiberoplic Transmission

VREF = 7.3V
+5V

RIN2

-15V +15V
5.1K
FSK
....--'\III'v-_-o Output

+2
R'IN

Lowpass
Filter

01 = 2N2222 or equivalent
02 = 2N2906 or equivalent

Fig. 26 4153 FSK Modulator

7-18

Raytheon Semiconductor

For More Information call 1-800-722-7074.

AN-25
4153 FSK Modulator (Figure 26)
When the logic input goes High, 01 is turned
on, which turns 02 on. The input current is
VREF- .2V
RIN1
The one shot frequency will increase to
balance this input current. If the logic input
goes Low, 02 turns off. The integrator input
current is
VREF
RIN1 + RIN2
so the one shot frequency, and therefore the
logic output frequency decreases to balance
the loop. The output pulsefreguency isapplied
to the toggle, which divides by two, and
provides an output square wave of half the
frequency of the VFC. This is applied to a
lowpass filter to round the edges for
transmission over public telephone lines.
Figure 27 is a table of component values forthe
two ranges of the Bell 103 standard.

4151/2 FSK Modulator
Figure 28 shows a simple FSK modulator using
a 4152. When the logic input goes high, 01
turns on and shorts out RS2, thus changing the
scale factor. Overall frequency trim may be
changed by trimming RIN or RB, and relative
trim by adjusting RS2. Fo is equal to
(Rs) (Vee)
2.53 RoCoRB
An inverter on the input may be necessary to
keep your system's logie polarity correct, as the
output frequency decreases with a logic High
input. Components for the filter must be
selected with the bandwidth and response time
limitations of the medium in mind.

Mark
Space
Ro
Co
RB
CB
RS1
RS2

1070Hz
1270Hz
= 6.8K

Mark
Space
RO
Co
RB
CB
RS1
RS2

=
=

= 0025~F
= lOOK
= 4.7~F
= 12.3K
= 2.3K

= 2025Hz
= 2225Hz
= 6.8K
= O.025~F
= lOOK
= 4.7j.1F
=
=

23.2K
2.3K

I

Mark
Space
RIN1
RIN2
Co
CIN

1070Hk
1270Hz
28.3K
= 6.0K

Mark = 2025Hz
Space = 2225Hz
RIN1 = 16.1K
RIN2 = 1.6K
Co = O.0068~F
CIN = O.l~F

=
=
=

= O.0068~F

= 01~F

Fig. 29 4151/2 FSK Component Values lor
300 Baud Bell 103 Standard

Fig. 27 4153 FSK Component Values lor
300 Baud Bell 103 Standard
+15V

RB
FSK
Output
Logic
Input
+2

Q1

Lowpass
Filter

=2N2222 or equivalent

Fig. 28 FSK Modulator Using 4151/2

For More Infonnation call 1-800·722·7074.

Raytheon Semiconductor

7·19

AN-25
Digital Frequency Encoding
Generation of more complex encoding, such as
an encoder providing 10 linearly separated
frequencies, is easy with an extension of the
previous circuits or with the help of a D/A
converter.
Figure 30 shows how a D/A can be connected
to a VFC. The binary input code is converted to
a voltage by the D/A converter, and then
applied to the VFC. The VFC's output is then
divided by two by the toggle in order to get a
square wave output. Figure 21 shows a digitally
programmable clock generator using a 4153.

Encoded
Output

Digital {
Input

Fig. 30 Digitally Controlled Frequency Generator

This circuit provides a 100 Hz to 9.9 kHz square
wave output programmed by thumbwheel
switches or by an 8-bit BCD coded binary input
word. The output changes in 100 Hz steps -one
step for each least significant digit change. The
DAC-20 is a 2 digit BCD D/A converter which
provides a 0 to 1rnA current output. The
reference voltage for the DI A is provided by the

4153. A 1 converts the DIA's current output to a
o to 9.9V signal applied to the 4153 VFC. Scale
factor for the VFC is 2 kHz/volt, which is then
divided by two by the 7474 latch (connected as
a toggle). This gives a square wave output of
100 Hz to 9.9 kHz. Scale factor of the VFC may
be adjusted to give the desired range, up to a
100 kHz square wave output. To calibrate, set
the D/A inputs to maximum (1001 1001), and
trim the 5K pot until output is 9.9 kHz. Then set
the inputs to minimum (00000001) and adjust
the offset (10K pot) until the output reads 100
Hz. The 4153's linearity ensures that all other
settings are in calibration. Other types of D/A
converters may be used, as well as different
frequency scalings and output signal
conditioning.

Bipolar Telemetry Scheme
Figure 32 shows a complete transceiver for
serial transmission of bipolar analog signals
over a twisted pair (or any other form of
transmission). It overcomes the usual
limitations on bipolar serial transmission by
encoding the pulse output. Negative input
voltages are transmitted as a negative going
pulse train and positive voltages as a positive
going pulse train. This information is decoded
into a frequency output proportional to the
magnitude of the input, and a sign output
dependent on the polarity of the input.
+15V -15V

10K

-15V
+15V -15V
lOUT

Ai = RC4131 or equivalent

Fig. 31 BCD Input Clock Generator

7-20

Raytheon Semiconductor

For More Information call 1-800-722-7074.

AN-25
VIN

1--.......-0 fOUT

1--_--0 Polarity

Polarity

Fig. 32 Bipolar Telemetry Scheme

+5V
Frequency
Input

r-------~

__-+--O

from twisted pair

Polarity
Output

10K

Clock

O.OO5I'F
Frequency 0 - - - - - - - - '
Output

15

8

Fig. 33 Bipolar Telemetry Receiver

+15V
91K

+5V
10K±O.I%
VIN o----'W\r-...--""I\r-~

+10V to -10V

5.1K

680pF
-15V

A1.2 ; RC4558 or equivalent
01 = 2N2222 or equivalent

+15V -15V

Fig. 34 Bipolar Telemetry Transmitter

For More Infonnation call

1-1100-722-7074.

Raytheon Semiconductor

7-21

AN-25
The absolute value circuit applies a voltage
proportional to the magnitude of the input to
the VFC. The frequency output of the VFC is
encoded with the polarity output of the
comparator, giving a coded signal which is
transmitted to the decoder.
VIN - - - - - - - -

The absolute value circuit provides a positive
voltage equal to the magnitude of the input
voltage. This buffered output is applied to the
VFC. The VFC generates 10 J..LS wide negative
going pulses with a scale factor of 1 kHz/volt.
Full scale input is therefore 20 volts peak to
peak. The transistor provides a logic output
dependent on the polarity of VIN (See the
absolute value circuit in the appendix on signal
conditioning). This polarity signal is used to
encode the frequency output of the VFC in a
TTL exclusive OR gate. Positive going pulses
are generated from positive inputs, and
negative going pulses for negative inputs.

Transducer Bias
ISlAS 0; 5mA

t-------

1~S
Coded
Signal
Decoded
Magnitude

OV

~~

Pi n n n n n n

I
J U U U U U U U

+5V
0

ULJLJUUUL

+5V
0

Decoded
Polaritv

+5V

Fig. 35 Bipolar Telemetry Waveforms

to twisted pair

D1

Transmitter

-

+10V

~-------------.------~--.---~~.-~~

Co

A 1,2 = RC4558
D1,2 = 1N4001
D3,4 = 1N914
Q1 = 2N2900

1K

415112

100K

17K

"'>-_--0

+15V

TTL

Output
o to 5V

5K
D3

D4

-15V
from
twisted pair ---a~---~-----'\Nv--"'"
RF
RxCx ~ RoCo
3,3K
20

+15V

4.7K
12K
Receiver

65-01D9BA

CF ~ RoCo
4RF

Fig. 36 Two Wire Transmission System

7·22

Raytheon semiconductor

For More Information call 1-800·722·7074.

AN·25
The coded pulse information is transmitted and
applied to the 0 input of the 7474 latch, and to
the two trigger inputs of the dual-edge
retriggerable one shot (8853). For the
components shown, the one shot generates a
25 ,."S wide negative going pulse for each 1O,."S
input pulse. It will trigger for negative going
pulses or positive going pulses on the last edge
encountered, thus producing a 25,."S wide
pulse train equal in frequency to the data (See
Figure 35). The rising edge of these pulses
clock the O-Iatch, and the information on the 0
input will be latched in. If the pulses are
negative going, the clock will rise when the 0
input is High, latching the Q output Low. If the
pulses are positive going, the clock will rise
when the 0 input is Low, latching the Q output
High. The latch output now corresponds to the
polarity of the information transmitted. The
values given are not absolutes, and timing and
scale factor may be adjusted to your needs.

Two-Wire Transmitter
Figure 36 shows a complete true two-wire
transmission system. The same wires that carry
the data signal also supply power to the VFC,
eliminating batteries or isolated power supplies
at the transducer. The circuit as shown uses the
4151 single supply configuration, delivering '"
1% accuracy. Greater accuracy may be
obtained by adding a single supply op amp for
precision mode. The components shown giveO
to 10 kHz operation.
The output of the 4151/2 pulls current pulses
from the transmission line, which are detected
and output as a TTL signal by the receiver. The
blocking diode 01 and 1O,."F capacitor filter the
supply to the VFC and absorb line relections of
the transmitted data. Bias voltage for the
transducer can be provided by the transmitter
supply if the current requirement is less than 5
mA.
Transistor Q1 provides two functions: it acts as
a series pass transistor to regulate the
transmitter supply, and it acts as a commonbase amplifier for the data pulses. The current
pulses create a voltage drop across the 1200
resistor, which is capacitively coupled into a
filter and comparator. The comparator is
connected so that the output swings from OV to
+5V (TTL logic). CFRF and CxRx provide noise
filtering to reject electromagnetic interference
from motors and power lines. CFRF controls the
For More Information call 1-800-722-7074.

response time of the power regulator (A 1 and
Q1), and CxRx provide a lowpass filter for the
output amplifier. 02 protects Q1 from transient
voltages on the transmission line. Typical
values for a 75,."S pulse width are:
CF = .005,."F
Rx= 1KO
Cx= .001!-1F

Tape Recording
Transducer data may be stored on magnetic
tape with a VFC. An application of this might be
the taking of data at a remote site with only
battery operated equipment available, or file
storage for later reference. The data may be
retrieved for use in digital format, or
reconverted to analog for chart recorder
display.
Some signal conditioning and restrictions must
be observed when recording data. The
frequency response of the deck will limit the
dynamic range of the analog data. Most
recorders will not accept pulse trains of sharp
square waves because of NAB compensation.
Accuracy of the system will be limited by motor
speed variations (wow and flutter) of the deck.
Good battery operated cassette recorders will
introduce about 1% to 3% inaccuracy. If battery
operation is necessary, be sure the batteries
are well charged, or the tape speed may vary as
they discharge. Many cassette decks have a
200-300 Hz AC component in the motor speed.
This is a function of the motor poles and belt
ratios. If higher accuracy is needed, there are a
few expensive high quality portable recorders
on the market that will give 0.5 percent error.
Figure 37 shows a system for recording the
data on tape. The VFC's pulse output is fed to a
toggle flip flop, giving a square wave of half the
frequency out. This signal is applied to a
lowpass filter to round the square wave,

to Tape
Recorder

Inalog
Input

Raytheon Semiconductor

5K

Input

Fig. 37 Tape Recorder Interlace

7-23

AN-25
because sharp rise-times will cause the NAB
compensation to overload the tape. Both high
and low frequency response limit the dynamic
range of the input, so it may be necessary to
add a DC offset to the transducer to achieve a
frequency offset. Excellent results in most
applications will be obtained by limiting the
recorded signal to a 1 to 5 kHz bandwidth.
The signal may be retrieved from the tape by
capacitive coupling of the output to a ground
referenced comparator. This will give a square
wave output which may be processed digitally
or applied to an FVC for analog reconstruction.
Remember that the FVC must have twice the
scale factor of the VFC for 1-to-1 reproduction.

pulse width modulation, and switching
transistor providing pulsed DC power to a DC
motor. This concept will work with all types of
AC tachometers if certain design rules are met.
The error amplifier might conceivably be a
power op amp with the output driving the motor
directly. The power regulator might be a series
pass transistor, a switching transistor, a triac,
or relay, etc. The reference input to the error
amplifier can be used to vary the motor speed
or act as a trim for precise applications.
+Vcc

MOTOR SPEED CONTROLS
Raytheon converters are extremely versatile in
motor speed control circuits. There are two
general forms for this application; one using an
FVC providing an error signal dependent on
variations in motor speed, and the form which
uses a VFC to provide a pulse frequency to gate
a power regulator. Figure 38 shows the FVC
feedback system.

RB
ntegrator

Fig. 39 FVC Provides Ramp for PWM

Pulse Width Modulation Speed Control
Figure 39 uses the general form of Figure 38 to
implement a pulse width modulation scheme
for switching control of a DC motor. This circuit
gives excellent rejection of variations in load,
power supply voltage, and temperature. The
tachometer sends a pulse train to the FVC,
which produces a ramp signal whose DC level
is proportional to motor speed. This ramp is
compared to a control inputto generate a pulse
width modulated signal to drive the transistor
switch.

Fig. 38 FVC Provides Error Signal

In this form, tachometer pulses are converted
into a voltage dependent on motor speed. This
signal is amplified with respect to some
reference voltage, to provide a control signal
which regulates the power supplied to the load.
If the motor slows down, the DC voltage from
the FVC decreases, which causes the control
signal to increase, which makes the regulator
deliver more power, causing the motorto speed
up. This general form can be used with varied
types of motor, tach, amplifier, and regulator
systems. We will discuss a system which uses
an optical tachometer, a comparator providing
7·24

The values of the components used are highly
dependent on the tachometer, the motor, and
its application. For smooth operation, the tach
frequency must be much greater than the
motor RPM's (approximately 10 times) to
ensure that the load friction/inertia product
does not slow the motor between tach pulses. If
necessary, a frequency multiplier may be used
to make the apparent ratio of tach frequency to
motor revolutions higher. The tach pulses must
be within the input voltage constraints for the
FVC circuit (See appendix on FVC Signal
Conditioning).

Raytheon Semiconductor

For More Information call 1-800·722·7074.

AN-25
Tachometer --,
Output

for positive switching and must be able to drive
the output transistor into saturation. For larger
motors, add more output transistors (in
parallel) to accommodate motor requirements.

n n n n r

UUUUU

..J1fl.J1.f1JL

FVC to

Integrator

Output

_A_AA---.L\.... A
TV V V V

~

PWM

- -

VCONTROL

Transistor Switch

Fig. 40 Pulse Width Modulation Waveforms

The FVC output current pulses of amplitude 10
and width Tp are integrated by the parallel RC
circuit RsCs. The time constant RsCs is chosen
such that the input to the comparator is a
triangle wave. This triangle must have a peakto-peak amplitude large enough to provide
good pulse width modulation, but also have a
long enough time constant to provide an
average voltage proportional to motor speed.
The peak-to-peak voltage is given
approximately as:

10

CS

Open Loop Switching Control
The preceding application uses an FVC to
provide an error signal dependent on motor
speed to provide feedback for precise speed
control. Perhaps your application does not
require precise control, but needs a switching
drive to increase efficiency. This brings us to
the second type of converter motor speed
application, using a VFC to provide a pulse
frequency to gate power regulator (See Figure
41).
The VFC provides a pulse train whose
frequency is dependent on the speed control
voltage. This pulse train is used to switch a
power transistor, providing pulsed DC power to
drive the motor. This increases the motor's
efficiency and allows smoother operation at
lower RPM's than a steady DC supply would.
This AC supply has a problem of heating the
motor if used for extended periods.

(Tp\

Tp 1- \TJ
= Vhigh - Vlow ""
where: Tp = One Shot Time (1.1 RaCo)
Vpeak-peak

+VCC

1
and: T = Tach Frequency
The average voltage is given as
VCOMP (Avg.) = Rslo

Speed
Control

~~1

Some experimenting will be necessary to
optimize your motor - tachometer
combination.
The speed control input (Vcontrol) is
compared to the filtered FVC output, which
contains a triangular ripple component and a
DC component proportional to motor speed.
Variations in motor demands or supply or a
change in the control input will cause the
output of the comparator to vary in duty cycle
(Pulse width modulation). A speeding up of the
motor will result in less on time of the power
transistor, delivering less energy per unit time,
thus slowing the motor back down. Component
values are generally chosen for approximately
30 to 50 percent duty cycle under normal
loading. The comparator must have high gain
For More Infonnation call 1-800-722-7074.

Fig~

41 VFC Provides Open Loop
Switching Control

Series - Pass Summing Controller
Figure 42 combines the low speed smoothness
of Figure 41 with the advantages of DC power
(low heating). The summing amplifier output
contains an AC component produced by the
VFC, and a DC component proportional to the
speed control voltage. This voltage, minus the
base-emitter voltage of the pass transistor,
appears across the motor. The inputs to the
summing amplifier are scaled such that the
pulse train is eliminated when the speed
control voltage reaches approximately 50

Raytheon Semiconductor

7-25

AN-25
percent of the full scale value. The summing
amplifier must be in a non-inverting
configuration.
+Vee
Speed
~ontrol

Fig. 42 Serles Pass Summing Controller

Phase Locked Loop Speed Control
Figure 43 shows another pulse width
modulation scheme which has the advantages
of increased gain at high RPM's, and that the
tach frequency equals the VFC output
frequency.
The VFC provides two functions in the circuit; it
converts the speed control voltage into a
reference frequency with which to compare the
tachometer frequency, and it also provides a
triangle waveform from the integrator to be
used to pulse width modulate the output.
The output frequency of the VFC is compared
to the tachometer frequency in a digital
exclusive-OR phase comparator. For proper
phase comparison to take place, the VFC
output and the tachometer output must both
have 50 percent duty cycle when locked. The
output ofthe phase comparator is fed into a
lowpass filter to give a varying DC voltage error
signal.
+vee

This error signal is sent to a comparator which
functions much like the comparator in the
circuit of Figure 39. It provides pulse width
modulation at the output, because the other
input is the triangle waveform from the
integrator of the VFC. The lowpass filter must
have a longer time constant than the integrator
of the VFC in order to provide good pulse width
modulation.
Since the triangle waveform is equal in
frequency to the VFC output, the VFC
frequency is not only the same as the tach
frequency, but also the drive pulse rate.
Therefore, to ensure smooth operation, the
tach frequency must be much greater than the
motor RPM rate.
The inputs to the phase comparator will vary in
angle from a degrees to 180 degrees. At a
degrees, the lowpass filter output will be avolts.
At 180 degrees, theoutputwill be maximum. To
provide a proper error signal, the PWM must be
scaled such that the system will balance when
the phase angle is 90 degrees.
This type of phase comparator may lock onto
harmonics of the tach output. The range of
frequencies over which it will lock greatly
depends on the relationship of the lowpass
filter and time constants of the motor drive.
Experimentation with the lowpass filter
characteristics, the tach pulse to motor RPM
ratio, and scaling of the PWM inputs will be
necessary to optimize your system.
In the locked condition, if the motor sees a
greater load and slows, the filter output voltage
increases and provides more on time to the
output transistor to speed it back up. The peak
amplitude of the triangle waveform decreases

Phase Detector (exclusive or)

Speed
Control
Integrator Output
pin I, 6
Low Pass
Filter

.J.

Motor

Fig. 43 Phase Locked Loop Speed Control

7·26

Raytheon Semiconductor

For More Information call 1-800·722·7074.

AN-25
as the VFC frequency increases. For a 50-to-1
frequency change the peak-to-peak triangle
voltage is 3.8 times smaller. This reduction of
input voltage to the comparator acts as an
increase in loop gain at high frequencies. This
11.6 dB effective gain increase at the high end
compensates for the gain reduction at high
motor speeds inherent in pulse width
modulated DC motor drives.

example of this is seen in Figure 46, where the
precise charge dis--pensing characteristics of a
4152 VFC are used to control a chemical
reaction.

+vcc

RL

Switched
Current
Source I--_~
10

Error Signal
from Phase
Comparator / Ramp from VFC

J

One
Shot

Logic
Outp'

-Ac----,,,",,---..J'....

Fig. 44 Phase Locked Loop PWM Waveforms

Typical Waveforms
in locked Condition

lectrolyte
Solution

VFC
Output
Fig. 46 Chloride Titrator

II II II
---1 L.-l L.-l L-

Tach
Output
Phase
Comparator
Output
Filter
Output

I

~

Vee

1f2VcC

!

~
0°

90°

180°

Input Phase Angle

Fig. 45 Phase Comparator Relationships

MISCELLANEOUS APPLICATIONS
Converters are not limited to the standard uses
of AID conversion and telemetry. The 4153, for
example, has an op amp, a voltage reference, a
comparator and switched current source, and
an open collector output, all contained
internally. These functions can be combined to
create circuits other than just converters. An
For More Information call 1-800-722-7074.

Titrator
The VFC's current pulses generate Ag+ ions,
which precipitate CI-ions from the electrolyte
solution. If there are CI-ions in the soultion, the
Ag electrode is polarized positive. This
switches the ground referenced comparator,
which fires the one shot, switches the logic
output, and dumps a charge from the Ag
electrode into the solution. The charge causes
CI-ions to be absorbed by the Ag electrode, so
the one shot keeps firing until all CHons are
gone. When that happens, the Ag electrode is
polarized negative, below the comparator
threshold, and the one shot stops firing. The
number of charges dispensed, which equals
the number of logic output pulses, is a measure
of how may CI-ions were in the solution.

~gCI-

(N) (10) (1.1 RoCo) (35.3~g/~Mole)
.96487 X 10-6 Coulombs/~Mole

Where N = the number of charges dispensed
and .96487 X 10-6coulombs equal the charge
dispensed with each pulse. Q = (I) (T) I in amps
T in seconds. Titration of a standard solution of
CI- will be necessary to calibrate the
measurements.

Raytheon Semiconductor

7-27

AN-2S
veo Stabilization

The veo output is a high frequency sine wave.
This is squared in a comparator and the
frequency is digitally divided down to a
frequency usable by the FVe. Some signal
conditioning will be necessary at the FVe input
(see appendix). The FVe gives an error signal
which is applied to a summing integrator. The
FVe output is balanced with the V control
signal to produce the voltage control input to
the veo. Thus, if the veo drifts, the FVe
output voltage changes, which causes the
integrator output to give an error signal
correcting the veo. Low temperature
coeffiecient components should be used in the
FVe and integrator, such as a low drift op amp
and polystyrene capacitors.

Low cost veo's do not have good temperature
characteristics or linearity. By adding a low
cost F-to-V converter in a feedback loop
around the veo its performance is greatly
enhanced, giving linearity of .01 percent and
low temperature coefficient, without resorting
to heating elements or expensive digital
synthesis.

RIN1

CIN

-VCONTROL o--...I\N......- - - j

RIN?
Sine Wave
Output

Fig. 47 Voltage Controlled Oscillator Stabilization

+Vcc

I
Rx

Ro

8

Co

-.eif-<~
C

~

-==-

2 7

RA

Threshold

415112
le·l

1
10K

6

Rv

~

-:;:-

~

415112
IC·2

RB

~
3
-:::-

Ro

8

~

Threshold

1

3

7 2

Rs
10K

i-=-

CO

A

Staircase
Output

~
"

~

5K

Rl

,Dl...

.~

D2

.j~

5K

D3

...

Rs

*

1"-'
fCl

Fig. 48 StaIrcase Generator

7-28

Raytheon Semiconductor

For More Information call 1-800-722-7074.

AN-25
the logic output (pin 3) goes High, allowing C1
to charge again. The cycle repeats itself until
enough charges have been delivered to C2 to
bring the voltage on C2 above the comparator
threshold of IC-1. This threshold is set by Rx
and Rv; when it has been exceeded, IC-1 's one
shot fires, bringing its logic output Low, and
discharging both C1 and C2 through 01 and
02. After the one shot period of IC-1, its logic
output goes High, C1 again begins charging
through R1, and a greater cycle repeats itself.
The basic timing function is provided by the
charge and discharge of C1. This timing sets
the interval between chargings of C2. C2, not
having a discharge path, increases its voltage
in steps until the threshold is reached. A low
input current buffer on the output may be
necessary before utilizing the circuit.

Staircase Generator
Figure 48 illustrates the VFC's versatility, as it
uses the functional building blocks to create a
circuit not related to conversion. It uses the one
shot and comparator of IC-1 to provide a timing
function similar to a 555, and the switched
current source of IC-2 to charge a capacitor.
To understand the circuit, consider what
happens when power is first applied. Both C1
and C2 are discharged, and C1 begins to
charge through R1. The voltage on C1
increases until it reaches IC-1 's threshold, set
by RAand RB. When the threshold is exceeded,
the one shot fires, bringing pin 3 Low and
delivering a discrete amount of charge to C2.
C2's voltage rises by an amount proportional to
the charge, and the logic output discharges C1
through 03. After the one shot period of IC1,

VTHRESHOLD2 =

+vee(~)
\Ra + Rb

- - - - - - - - --

) t:.V

VTHRESHOLD1 =

+vee~)
\Rx + Rv

- - -- - - - - T1

l~

T2

____~Il~____~~
T3

VTH -

0.7)

T1

= R1C11n ( 1- ----vee

T2
T3

=
=

where VTH

RB

= Vee RA + RB

1.1ROCo of IC-1
1.1 RoCo of IC-2

t:. V =

(I01)(1.1RoCo)
C2

see 4151/2 Data Sheet
for Design Equations

Fig. 49 Staircase Generator Waveforms

For More Information call 1-800-722-7074.

Raytheon Semiconductor

7-29

AN-25
Appendix
Signal Conditioning
Transducer Bridge
Low level transducer signals may be integrated
and converted directly by the period
measurement technique (see Figure 14).
Another technique is to amplify the signal with
a low drift instrumentation amplifier before
conversion. Transducers with bridge outputs
lend themselves to this, with a differential
output, allowing amplification with high noise
rejection. Bridges require a reference
(excitation) voltage to generate the differential
output, readily supplied by the 7.3 volt
reference output of the 4153. Figure 50 shows a
typical transducer interface circuit using a
4153. A 1 and 01 buffer the reference output of
the 4153 to supply a well regulated excitation
voltage to te bridge. Changes in the value of the
transducer (x) cause changes in the differential
output voltage.
VREF
R
VOIFF = - 2 - - X + R (VREF)
This differential output is amplified by the
instrumentation amplifier A2 and applied to the

input of the VFC. Thus the VFC output
frequency is proportional to the value of the
transducer resistance. This circuit is only an
illustrative example, as bridge configurations
could be unipolar or bipolar, linear or
nonlinear.

Absolute Value Circuit
Figure 51 is a schematic for an absolute value
circuit for bipolar inputs.
When VIN is positive the op amp is effectively
out of the circuit; when its output goes Low the
1 N914 turns off, and the signal passes without
attenation to the VFC input. When VIN is
negative, the op amp inverts the signal (the
1 N914 is biased through the zener), and the
VFC receives a positive input. The zener diode
ensures that the polarity indicating transistor is
turned on. The polarity output may be used to
drive the sign bit of the interface or display.

+Vee

13

+Vee

4153

5.1K
Logic
Output

CO
A1 = RC741
A2 = RC725

-=:Fig. 50 Transducer Bridge

7·30

Raytheon Semiconductor

For More Information call 1-800·722·7074.

AN-25
Matched

,---''-----"
20K

+Vcc

20K

VIN o----'\NIr-tI--~VI/'.--____1t_--O VOUT

01 2V

02

10K

-::-

A1
Q1
01
02

+VCC

Polarity
Output

2K

=
=

RC725
2N2222

= 1N5228
=

1N914

Fig. 51 Absolute Value Circuit

-15V +15V

+Vcc
VOUT

RA
14

CI

RI

4153
12
11

RB

Comparator wilh
Hysleresis

52 8 9

Input
Coupling

-::-

6

RI

-::-

FVC

Fig. 52 FVC Inpul Conditioning

FVC Signal Conditioning
Frequency-to-voltage converters require the
input waveform to have a sharp edge, and that
the signal actually reaching the trigger input
have less pulse width than the period of the one
shot. This is to prevent the one shot from being
retriggered, which would cause an erratic,
nonlinear output. If the input is a sine wave, for
instance, a Schmitt trigger or comparator
should be used to square up the waveform
before AC coupling to the FVC (see Figure 52).
The time constant CA(RAl/Rs) should be kept
less than 151-'S in most applications. For
applications with a square wave input, the one
shot time should be kept less thatthe minimum
period of the square wave. This prevents the
input from interfering with the timing waveform
and affecting linearity. By keeping Co small
this problem can be avoided (see Figure 53).
For More Information caJI1-800-722-7074.

-,L-JIILJIIL

r

Proper
Operation

1

l L-JIILJIIL

Input
Frequency

Timing
Waveform
on Co

Input
Frequency

Improper
Operation

~

Raytheon Semiconductor

Timing
Waveform
on Co

Glitch

Fig. 53 FVC Timing Waveforms

7-31

AN-25
Other Application Ideas
Here are some more application ideas:
• Audio Logic Level Indicator
• Automotive Cruise Control
• Frequency-to-Voltage -Gain- Voltage-toFrequency
• Pulse Width Modulators
• Pulse Frequency Modulated Audio
Transmission
• FSK Demodulators
• Signal Conversion
Current-to-frequency
Temperature-to-frequency
Pressure-to-frequency
Frequency-to-current
Capacitance-to-frequency
Light-to-frequency
• Variometers
• Discriminators
• Tacho.meters and Flow Meters
• Multimeters and Panel Meters
• Linear Potentiometer Positioners

7-32

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TP-6A

An Introduction to the Z Transform
and its Derivation

For More Information, calI1-80Q-722-7074.

Raytheon Semiconductor

7-33

TP-6A
INTRODUCTION TO THE Z TRANSFORM AND ITS DERIVATION

1.

INTRODUCTION

Recent advances in the field of electronic
computing machinery are due largely to the
great strides made in IC technology. Specifically, improved speed and higher IC density
have made practkal the efficient digitization
and subsequent processing of real world data.
More complex processing with more accurate
results can be performed with digital than with
present analog data equipment. With scientific
advancement in fields such as medicine and geophysics the need for complicated processing
algorithms and large data storage capability
points most singularly in favor of the digital
approach.
The recognized potential of the digital
computer as a signal processing tool has spawned
rebirth in the field of discrete mathematics.
The Z transform has proven itself to be a useful
constituent in this field, and it is the intent
of this paper to introduce the Z transform as a
means of analysis and synthesis of purely discrete time and mixed (analog-digital) systems.
Hopefully, those familiar with Z transform
theory will find the presentation unique and
clear; and newcomers to the field of DSP,
especially those of an analog persuasion, will
be spared the frustration of breaking into this
new field which usually bears little resemblance
to its analog counterpart. This is not to be an
exhaustive treatise on digital processing mathematics but more of an introduction to the subject. It is designed especially to clarify or
define some of the crucial points which the
author finds are omitted from most introductory
treatments of the subject. This attitude will
hopefully give the reader a good intuitive foundation on which to build.
2.

MOTIVATION FOR LAPLACE TRANSFORM

One frustrating aspect of an engineering
education is that often the student is expected
to accept a formula or concept at face value,
use it, and build on it without knowing its origin. Some may reply, "Who cares?" and rejoice
at the prospect of having to learn less material.
On the other hand, the more inspired find it
maddening to open to page 1 of their digital
systems text and find the opening statement: "It
is intuitively obvious to the casual observer
that:
00

1:
n=O

h 2
n

1
2rrj

Clearly, this sort of thing may propagate
and cause great confusion or misuse of the
theory. For our purpose (that is, understanding
discrete time systems) it is important that the
fundamental theorems which apply to any linear
system are well understood. A good place to
start is with a derivation of the LaPlace transform and the motivation behind it. This will
lay the groundwork for the Z transform discussion which follows:
All continuous realizable linear time
invariant systems can be described in most
general terms by the nth order differential
equati on 1.

(1)
m

b ~ + '"
m dtm

bl du + b u
dt
0

x(t)

u and yare both functions of time and the
a's and b's are constant for the time invariant
case. From a system standpoint, y is the system output and the u's are the input terms. To
simplify matters let x equal the sum of all the
input terms are shown in equation 1.
X(t) ____ 1 SYSHW1 i - y ( t )

For any given input x(t), a unique system
output y(t) will result. Generally the output
will be a complicated sum of individual time
functions (not necessarily resembling input x).
We arrive at the response via the tedious time
domain solution of the differential equation for
the given input x(t).
One input function to a linear system yields
a conceptually trivial solution to the differential equation and hence simplifies the system
description. The complex exponential time function est (where s = iJ + jw) may be di fferentiated
any number of times without destroying its original functional form.

H(Z) H(t) Z-l dZ "
IZi=l

7-34

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TP-6A
That is,

X(S)-~-V(s)

Successive differentiations yield the original time function est multiplied by a complex
constant (e.g. sn). For the present we will not
be concerned with the meaning of est in a practical sense but note that is has a remarkable
property particularly suited to differentiation.
Returning to equation (1), we might logically
question, "with the output of a system being est
what must the input have been?"
Letting y(t) = est (the output), differentiating and accumulating all the terms one
finds:

Hence, function est will pass through a
linear invariant system unaltered in functional
form and merely modified by a constant, H(s).
est are called the eigenfunctions of the system, and H(s) are the eigen-va1ues or the transfer function. In general, any functions which
undergo the linear operations of a iven s stem
and maintain their functional form but are
simply modified in amplitude or weight) are
called eigenfunctions. Similar definitions
relate to vectors which undergo linear transformation. The terms eigenvector and eigenvalue apply in these cases. The reader is
reminded that H(s) is a function of the value
of 5 alone and takes on unique values according
to the value selected for 5 for the input.
Expandi ng bri ef1y will soli di fy thi s poi nt
and also relate the practicality of the transfer
function. First note that est = eot[coswt +
jsinwt]; est has no time bound on it, and extends
from t = minus to plus infinity. For 0 = 0,
s = jw and est = coswot + jsinwot.
As an example, choose

The input function is shown to be the same
function as the output function (est) but simply
multiplied by the constant ansn + .•. al s + ao
which we will term IjH(s) from this point on.
Conversely for an input x(t)
put will be

=

H1(s)

For X(s)

est the out-

=s

a
+ a

=~
X(s)

(4)

ejwo t , s = jw o

est H(s)
V(s)
2.1

Eigenfunctions and Transfer Functions

Our starting point is the differential equation which is accepted as an accurate description of all linear invariant and continuous phenomena. For an input x = est (where s may take
on any complex value) the output function will
also be est but multiplied by a constant H(s),
that is y = H(s)·x.

X(jw)

To denote that x and yare of identical
functional form est, a more formal expression
using capital letters for X and V is adopted.
V(s) = H(s)

XTsT

(3)

Also the time variable t is omitted for brevity.

For More Information call 1-800-722-7074.

The complex eigenvalue is a complex multiplier. That is, it has the capability of scaling ~m~litude and also effecting a phase shift
on eJw. From H(jw) the complex frequency
response is found.

Raytheon Semiconductor

7-35

TP-6A
In the laboratory real sinusoids are
generated. These can be described mathematically
by combining complex exponentials through
Euler's identities as follows:

This method of system characterization has
not attracted much interest probably because at
t = _00, e -at is infinitely large. However,
conceptually speaking, if one applies e- at to
H1(S), H(-cr} e- crt is the output response.
2.2

ejwo t _ e-jwo t
2j
The real sinusoid frequency response of the system described by HI(s} is found ~onceptually by
fo~cing HI(S} separately with e+J wot/2 and with
e-J wot/2 and then adding the responses.
Y(jw} + Y(-jw}

LaPlace Transform as a Convolution

The system transfer function can be found
directly from its impulse or natural response
by LaPlace transformation. The impulse response of a continuous system can be obtained
by applying a unit impulse to the input of H.
The impulse has the property of having unit
area (i.e., volt-sec) while having infinitely
high amplitude. It can be defined as a rectangular pulse whose width T approaches zero and
whose amplitude l/T approaches infinity (Figure I).

51t)
CONSTANT
AREA = 1 VOLT-SEC

It can be shown that the steady state response
can be found directly from the transfer function. That is, for real sinusoid inputs
x = cos(wt + 8}, the output y is
Fi gure 1.
where 8 is the input reference phase and $0 is
the phase imparted by the network transfer function. Details of this discussion can be found
in The Analysis of Linear Circuits by C. Close.
Real exponentials and damped sinusoids are
also special cases of the eigenfunction est
For w = 0, est = eat. The transfer function is
very general in that it gives the response for
any input eigenfunction for any specified value
of s.
For x(t} = e- crt , a = -cr and w = O. The
output will be of the form e-crt but will have
a coefficient H(a}.
a e at
y(t} =a+a

[_a]
\
a-a

e-at

Eigenvalue coefficient

7-36

Generation of a Unit Impulse
or Dirac Delta Function oCt)
(Area is a constant 1 voltsec, and width and amplitude
vary inversely)

Figure 2 shows the canonical representation for H. The application of an impulse
imparts an initial value of 1 volt on the first
integrator. The response which follows is the
impulse response or natural response of the filter. It is equivalent to the homogeneous solution of the differential equation (I) (i.e.,
the solution for x = OJ.
It is not possible for an ideal impulse to
be generated in real life, but the theoretical
effect of its application may be duplicated
perfectly by placing an initial value on the
system at t = 0, through any available means.
The reader is advised to consult any book on
circuit theory for an in-depth discussion on
system impulse response and the homogeneous differential equation.

Raytheon Semiconductor

For More Information call H!OO-722-7074.

TP-6A
For T+O the summation becomes an integral.
T (the normalizing factor which maintains fairly
constant energy for all values of T) becomes the
differential increment dt, and nT becomes a continuous time variable T. The integral

j[
~

x(t)

x(t) ott - T) dt

lim T x(nT) (6)
T+O

may be verified as correct.
Good insight is gained into the system
behavior by applyin9 one of the impulses from
Figure 3, say x(-3T) ott + 3T),ana observing
the system response to it. For an impulse of
unit weight applied at t = 0, a hypothetical
impulse response is established (Figure 4).

'0

Figure 2.

General Canonical Form

As a preliminary to the actual LaPlace
integral derivation, an input function x(t) is
approximated by a sequence of impulses weighted
by T . x(t) (Figure 3).
x{tl ENVE lOPE \

/

-- --

/

~~

"'''~

__

,

"

/

Figure 4.

Impulse Response h(t)

The system is casual or nonantic-ipatory in that
the response does not precede the input.
-T

Figure 3.

T

2T

3T

4T

Discrete Time Approximation of x(t)

Figure 5 shows the response for the system
with x(-3T) ott + 3T) applied.

Hypothetical function x(t) shown approximated
by impulses weighted by T . x(t) at T spacing;
all impulses are actually infinitely high but
have various weights.
x(-3T) hIt + 3T)

The approximation is written in equation
form:*
function envelope (weight)

~~' ,'fft,d fo tfm,
x(t)

T ~ x(t) ott - nT)

x(nT)

by

oT
(5)

n

T

Figure 5.

2T

System Response to x(-3T)

The system output to the complete x(nT)
string is found by accumulating all the individual impulse responses (Figure 6).

*The approximation for x(t) should include an
integral, because in the strictest mathematical
sense the shifting property of a dirac delta
function is defined only under integration. The
abbreviated form has been generally accepted in
the engineering field., probably because it is
more clear.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

7-37

TP-6A
It follows that da = -dT
Original Integral

New Integral

Variable of
Integration Limit
T

7~

T

-T

T

2T

3T

4T

t

yet) =
For example, if x(t) began at t = -3T and
were zero previously, then the output at t = -3T
would be T • x(-3T) • h(O) = y(-3T). The output
at t = -2T has contributions from x(t) at -2T,
namely T • x(-2T) • h(O) and the tail of h(t+3T),
i.e., T • x(-3T) • h(-T + 2T). The outputs for
various discrete times are listed below.
y( -3T)

T x_3 h(O)

y(-2T)

T[x_ 2 ho + x_3 hl ]

y(-T)

T[x_ l ho + x_2 hl + x_3 h2]

y(nT)

T[xn ho + xn_l hl + xn_2 h2 + .••

t-(-~)=~

a

t-t=O

i

x(t-a) h(a)da

Recalling that the transfer function H(s)
relates the amount of est that will pass
through the system for a given $1 l~t x(t) =
Xes) = est, then x(t - a) = e-S(.-a). It follows that

j

es(t-a) h(a)da
(10)

o

The exponential is separable yielding

yet) =

estf" h(a)e-sada = X(Sif h(a)e-sada
o

n

T ~

x(mT) h(t-mT)

m=-3

For a continuous input, mT and nT become
continuous variables T and t, respectively, and
for the most general case where x(t) begins at
t = -~, the summation in equation (7) becomes
the continuous convolution integral.

1

0

The integral can be rearranged slightly to
suit our purposes by making the following change
of variables:

=t -

T

(11)

For x(t) = est it was shown (starting with
equation (1» that yes) = H(s) Xes). Allowing
H(s) Xes) to step in for yes) yields the well
known laPlace transform integral.
Xes) H(s) = xes)

j

e-sa h(a)da

o

(12)

and
co

X(T) h(t-T)dT = lim y(nT) (8)
T...o

a

(9)

~

In closed form

7-38

a

o

yet)

x_ 3hn+3]

y(nT)

Limit

The convolution is equivalently stated

Figure 6. Superposition Sum of Individual
Impulse Responses

yet) =

Variable of
Integration

H(S)

=/
o

"0

h(t).e- st dt

=/
o

(13)

2.3 Summary
linear time invariant continuous systems
are described by nth order differential equations.

Raytheon Semiconductor

For More Information caJI1-800-722-7074.

TP-6A
In general, obtaining an expression for the output y(t) requires the time domain solution of
the differential equation. The involved process
may be tedious and yield unwieldy results forst
most inputs. For inputs of the form x(t) = e
the output is always of the same functional form
and modified only by a coefficient. That is,
y(t) = H(s)e st . H(s) is called the transfer
function of the system and it results from passing est through the differential equation. To
denote that the input is specifically the eigenfunction* est, the input and output functions
are more formally denoted by capital letters X(s)
and Y(s). The time dependence of est is understood and the t is dropped for brevity. The
H(s)'s corresponding to each X(s) are the eigenvalues. There are infinitely many eigenvalues
since s may take on infinitely many values.
As implied, dealing with the differential
equation and its solution can be a tiresome and
often unrewarding experience. The transfer
function is very useful for computing frequency
response, assessing system stability, and doing
complicated filter and system designs. It can
also be used indirectly to compute the time
response of a filter to inputs other than est
without resorting to the differential equation.
When the impulse response of a system is
given and the transfer function H(s) is desired,
the LaPlace transform may be used. As illustrated in the derivation, the LaPlace transform
is the convolutional solution of a system or
differential equation whose input is the system
eigenfunction. The convolution (or superposition) integral is employed to find the output
for any input, but it yields a rather simplistic
result when the eigenfunction is used as the
input and the transfer function is implicitly
described:
X(s) H(s)

Y(s)

The eigenfunctions are found to have
practical significance, in that appropriate
pairs yield physically realizable and usable
waveforms. Specifically, allowing w = 0 yields
est = eat, and for a = 0,

coswt

*As a rule, functions which pass through a linear
system unaltered in functional form are termed
eigenfunctions. The associated multipliers are
called eigenvalues. This description is consistent with operations in linear vector spaces
where a vector x undergoes a linear algebraic
transformation A resulting in vector AX, where
A is a constant. X is commonly known as an
eigenvector. The multiplier A is an eigenvalue.

For More Information call 1-800-722-7074.

is formed, or more generally
eat cOswt
The transfer function representations of
systems are classically termed as frequency
domain descriptions, where differential equation
solutions deal with the time or spatial domain.
The variable s is the complex frequency variable
which has real and imaginary parts, a and jw,
respectively. Technically, the response of a
system to real frequency relates to its behavior
in passing eat. The response to imaginary frequency relates to "real world" sine or cosine
waveforms.
3.

Z TRANSFORM

The LaPlace and Z transforms belong to a
class of linear time invariant transformations
loosely termed as convolutional transforms.
Their derivations stem from the superposition
determination of a system output given that it
is forced with the eigenfunction input.
The Z transform, which is the widely
accepted tool to describe and design purely discrete time and mixed systems, provides similar
information stability and frequency response as
does the LaPlace transform for continuous systems. The Z transform and discrete transfer
function relate to the frequency domain in a
discrete time system.
The Z transform may be derived in the same
manner as is the LaPlace transform, with the
exception that the time variable is discrete.
Before proceeding with the derivation, some
opening remarks concerning discrete time or sampled data functions are in order.
As pointed out earlier, continuous functions are special cases of discrete time functions. Figure 3 and equation (6) indicate that
decreasing sampling time T adds more and more
samples 'on the waveform. As T~ the sampled
waveform becomes continuous.
One would expect that the continuous frequency domain could be interpreted as a special,
or more specifically, limiting, case of the discrete frequency domain, just as continuous time
functions are special cases of discrete time
functions (i.e., T = 0). A mathematical description to this end would soften the absolute distinction which is usually made between sampled
and continuous worlds. Alternating between the
two without having to resort to separate timeto-frequency transforms is sometimes beneficial
in a practical sense as well as a tutorial sense.
However, the Z transform is not designed to
do this in its basic form; and consequently the

Raytheon Semiconductor

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TP-6A
notion of the discrete frequency domain is
usually held quite separate from that of the
continuous frequency domain, and its related s
plane. The next section briefly describes the
effects of applying signals at arbitrary sampling rates to continuous elements. A smooth
transition between the sampled and continuous
frequency domains is thus provided. The following development ultimately leads to the Z
transform.
3.1

The difference operation is reminiscent of
basic calculus, where the first derivative or
slope of the function is approximated by the
same. For sampled functions, derivatives are
meaningless; and at least in this case* they
are approximated by first differences.
Equation (16) in its discrete form is
given.

Effects of Sampled Data on Continuous
Elements

I

+ •.. a1

Figure 7 shows a continuous filter with
impulse response h(t), subjected to an input
waveform x(t), which is sampled by an impulse
train. The train is normalized by T, the sampling interval.
OUTPUT

INPUT

SAMPLER

SAMPLER
hit)

xlt)

y(nTI

Variables x and yare now discrete and denoted
by x(nT) or xn' etc.
The discrete version of est is the eigenfunction to equation (16). We can confirm this
by observing its behavior under successive differencing. Maintaining the shortened notation:
esT _ 1
--T-

T

Figure 7. Continuous Filter with Sampled Input

(17)

Note that esnT (the discrete eigenfunction) is
preserved and is multiplied by a constant
(eST - 1)/1.
The second difference yields:

~ [~ esnT] = [eS\_ 1] ~ esT = ~eS\_ If esnT
(18)

n

y(nT) = T L x(mT) h(nT-mT)
m=-oo

(14)

Similarly,

It can be shown that when a continuous system is subjected to a sampled input the differential equation becomes a forward difference
equation. The differentials are replaced with
forward differences and the coefficients take
on modified values.
The first forward difference denoted
approximates dy/dt. It is defined below:
y(nT+T) - y(nT) and lim ~T
T

+
(16)

yn+1 - Yn

The immediate output y(t) is jagged waveform depicted in Figure 6. Equation (7)
describes the waveform at this point exactly for
the sampled input denoted Tx(nT). If we are concerned with y(t) at the sample points, a fictitious sampler (synchronized with T6T) may be
added. The final output is then denoted y(nT).
The discrete convolution sum describing y(nT) is
given in equation (14).

~n

T

T..o

(~fYn/T)

s!.t
dt

*The field of numerical analysis deals with the

approximation of derivatives and integrals by
more sophisticated operations on discrete signals. The processes involved lead to various
other discrete frequency domain variables such
as the w or bilateral transform variable. The
interested reader may find material on these
subjects from many sources.

(15)

7-40

Raytheon Semiconductor

For Mora Information calI1~.722.7074.

TP-6A
Letting i = n - m, a summation over i results
with the modified limits as indicated.

Recalling that for the continuous case
dN
dt

-Ne

st

=s

N st

(19)

e

The reader should delight in knowing that
the multiplying factor {esT - 1)/T is exactly
analogous to s. More specifically, it is the
discrete version of s; esT can be expanded:
fesT -

t

T

T

y(nT)

IJ = 1{[1
+ sT + {sT)2 + {sT)3 +
.. .J-l}
T
2!
3!

L

es(n-i)T h(iT)

The reader may check the substitution of variables and subsequent limit modifications using
the LaPlace derivation as a guide.
es(n-i)T separates, and using the frequency domain notation, equation (24) results.

(20)

Y(S)

and it follows directly that
lim (eST - 1) =

T->O

T

s

T

.

L

h(iT)Z-i

i=o

f

i=o

h(iT) e- siT

(24a)

or

00

T ~ h(iT)[T13 + lri
1=0

H(13)

Mathematically,

i~

= T· esnT

= H{S) X(S)

H(Z)

Moreover, the resulting discrete transfer function H{[e sT - 1]/T) becomes H{s) as T->O.

(23)

i=o

(24b)

where Z = T13 + 1.
H (ZTl) = H{s)

Because i3 and Z are related algebraically, H(p)
may be denoted H(Z).

where Z = est
For convenience we assign the Greek letter S =
(Z - 1)/T for future use.
Following the same direction as with the
LaPlace derivation, for x{nT) = esnT the same
signals are denoted with capital letters and
the time variable is dropped. Hence,

Equation (24a) with the normalizing T
omitted is the accepted form of the Z transform.
The effects of sampling on a continuous system
are best illustrated through the normalized Z
transform, and for the present the T will be
included. In Section 4 the Z transform is used
in the direct computer implementation of digital
filters and the T is omitted.
3.2 Sampling Effects on First Order Systems

x{nT) = X{S)} f
(T) e snT
y(nT) = Y(S)
or x n =

(21)

The two are related by the transfer function:

To illustrate the effects of sampling, a
first order filter with h(t) = e- at is selected
for the system in Figure 7.
The LaPlace transform of h(t) is:

Y{s) = H{S) X(S)

H(s)

Given that a system has a given impulse
response h(t), its discrete transfer function
is found directly through the convolution sum
of equation (14) with x(nT) = esnT .
The operation is trivial and leads ultimately to the Z transform.
n

y(nT) = T

L

esmT h{nT-mT)

m=-oo

For More Information call 1-800-722-7074.

(22)

=

_I_
s + a

(25)

The poles and zeros for a general H(s) are typically denoted in the complex s plane. The s
plane may be used as an analytical tool for
graphically computing frequency response or
root locus plots. It symbolically describes
the system relative performance and stability.
That is, real poles plotted in the left half
plane represent converging exponential impulse
responses. Complex poles represent damped sinusoid components and right half plane poles represent an unstable system.

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TP-6A
INTEGRATOR
1M S

S-PLANE

HIS)= _ a _
s +a

From equation (27) it is seen that sampling
produces a pole of B = -(1 - e-aT)/T and a zero
at II = -liT. As the sampling rate increases,
the circle radius approaches infinity, and
, rrect
-(1 - e-aT)/T approaches -a which is the cQ
pole location for h(t) = e-at • -(1 - e-aT}IT is
therefore the sampled system view of a continuous system singularity at -a. One may verify
that taking the limit as T goes to zero yields
-a, and lim [ Te + 1 ] _
1
T-+O
1
-aT - S'""'+'a
(27)

a+

--~---4------~ REALS

-a

Figure 8.

s Plane Showing Pole
for H(s) at s = -a

The real axis is a direct but not a linear
mapping of the real s axis. -liT in the sampled
plane corresponds to negative infinity in the
s plane. Hence, the effect of sampling on a
continuous system is not just to bend the jw
axis but also to modify the numerical value
of the real pole positions by an exponential
warping factor. This is illustrated by computing the normalized Z transform for e- anT .
H(Z) = T I:e- anT Z-n = T[l+e- aT Z-l + e- 2aT Z-2
n=O
+ ••• ]

This converging infinite series can be
expressed in closed form:

= 1-e-ai

-1
Z

= Z-eT~aT

(26)

Substituting Z = TS + 1
H(S) =

TIl+l
I -aT
II + -e

---r-

7-42

T

By expanding e- aT into a power series this result
is obtained:
-aT
(aT)Z
(aT)3
e
= 1 - aT + 2
- 3!
......

Sampling x(t) bends the jw axis of the
s plane into a circle of radius liT centered
at -liT as shown in Figure 9a. This can be
ve~ified by plotting e for s = jw. The term
(eJwT - l)/T maps out a circle whose arc length
is the input signal frequency w. The circle
becomes infinitely large as T approaches zero,
and the circle perimeter becomes the jw axis
of the s plane. Equivalently, the jw axis may
be considered a circle of infinite radius;
corresponding to the fact that a continuous
waveform is'a sampled waveform with infinite
sampling rate. The area outside the circle
corresponds to the right half s plane. Poles
in this region result in instability.

H(Z)

- e

(27a)

Figure 9b shows the pole zero plot in the S
plane for three sampling intervals T1' T2 and T3.
In Figure 10 three implementations for the first
order discrete filter are given. .Each filter
gives a sampled output with a continuous input,
although theoretically the inputs may be sampled
and synchronized with the input samplers. The
frequency responses for all three will be identical at the sampling instants.
Figure 10b,c show purely discrete versions
of the configuration. In b the accumulator or
discrete integrator is shown within the enclosed
area. It is mathematically equivalent to an analog integrator driven with a sampled input. The
delay elements are intrinsic to implementation
of any discrete function and may be formed with
purely continuous elements (L-C distributed delay
lines), or with discrete elements (digital registers or charge coupled devices) according to the
nature of the signal inputs. For demonstrative
reasons we have elected to simulate systems
which apply to real continuous phenomena (such as
integration, etc.). Even if this is the intent
of the design, the system can always be
described more simply with delays rather than
with discrete integrators as the basic element.
This is shown by example in Figure 10. The
transfer functions for all three are shown to be
equivalent with some algebraic shuffling of terms.
For purely digital filters where the data is
sampled and quantized by an AID converter, all
the arithmetic operations are done digitally.
The delays are implemented with memory (or shift
registers), the summing points are realized with
digital adders, and digital multipliers are
employed to give the correct filter coefficients.
Some useful digital filters are designed by
directly substituting a discrete frequency variable for s in the analog transfer function. The
res~lting t:ansfer function ca~ be expressed
ult1mately 1n terms of Z or Z- , regardless of
the discrete variable form. The configuration
can always use delays directly rather than discrete integrators (whose functional elements are
delays) •

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For Mora Infcrmation calI1~722.7074.

TP-6A
jw

T

, PLANE

w

,

(
-0.11

-r

TOOT

°T

Imj!
II PLANE

a)

Sampled Analog Configuration

__~,~WT~___~~._.+-~~-+~~---"~

-Y

T

r--------- -----,
I
I

I
I

I
I

I
I

I

I

a) sand

e Plane

II

Correspondence

DISCRETE
INTEGRATOR

I~=.-!...
I 1 _ Z-1
P

Im'I· ...

I
I

I
I

~--------------~

T'O

H(SI"S~.5

b)

Discrete Integrator Configuration

-----------=====~.~~RE=G:'ON~R..
}

Figure 19.

sand w Planes Showing Correspondence of Frequencies

Raytheon Semiconductor

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TP·6A
It is evident from Figure 19 that a frequency of fs/2 (i.e., w = ~/2, one-half the
sampling frequency) maps into j infinity in
the w plane. Hence, traversing a relatively
small span of frequencies close to the Nyquist
frequency (fs/2) results in a relatively large
variation on the imaginary w axis. This fact
provides advantage in the digital world for
filters with sharp transitions. The following
example illustrates this point.
Figure 20 shows the pole plot in the s
plane for a fifth order* Butterworth filter
whose cutoff frequency is at w = ~/2T or
f = fs/4 (1/4 the sampling frequency fs). To
get the same cutoff pOint for the digital filter
the circular pole pattern has its radius widened
according to 2/T tan wT/2. The pole pattern in
both planes is exact other than normalization,
because w is a direct substitution for s in the
analog transfer function for the Butterworth
filter.
The frequency response for the filter can
be found graphically by drawing vectors from
the imaginary frequency axes to the pole locations. The response at any point is the
reciprocal of the product of the vector lengths.
In the w plane a frequency of 3/B fs produces
vectors which are proportionately longer on the
1m w axis than on the jw axis (Figure 19). The
cutoff rate for the digital filter is therefore
greater and provides a sharper filter than the
corresponding analog filter.

The transfer function for the fifth order
Butterworth is given in equation (39).
2

n

H(s)
i

=1
(39)

The poles are situated in a circular contour at a radius of nc (cutoff frequency) in
the s plane. There are four complex conjugate
poles and one real pole. The corresponding
discrete domain cutoff frequency is wc. To
show how the discrete transfer function is
developed take one of the second order factors
in equation (39) and replace s with 2/T •
(Z - l/Z + 1)

(40)

Simplification yields a Z transfer
function of the form
2
A (1 + Z-l)

1 + BZ- 1 + CZ- 2

. 3
laWs

which can be implemented directly with delay
elements (Figure 21).

S PLANE

It is not necessary to implement the
integrator terms T/2 (1 + Z-l)/(l - Z-l)
because clearing equation (40) leaves just the
delay terms with their corresponding modifiers.
The complete filter is implemented by cascading
the individual second order sections with the
first order section.

\x
"-x
Figure 20.

Pole Plots for Fifth Order
Butterworth Filter Using
Transform

The first order section transfer f.unction
is found and easily implemented (Figure 21).

*Th;-~~~d~~-~~~ consult a book on filter

theory for the actual details on the parameters for the Butterworth and elliptic filters.

7·50

Raytheon Semiconductor

-+

£ (Z -1)
T Z +1

+

w

(41a)

c

For More Information call 1-800·722·7074.

TP-6A
simple and obvious features of analog designs
(such as direct pole zero mappings into the Z
plane).* As a result methods like the bilinear
transform emerged as effective design techniques.

-c

Figure 21.

Canonical Form for Butterworth
Second Order Section

0--

-,

~

-0 ------L...0--'----'.---I

Figure 22.

First Order Section

+
wT

H(Z)

4.2

(Z +1)

Z_ (1 _w~ T)

(41b)

Introduction to FIR Structures

The previous section described in IIR
digital filter using a discrete approximation
to the analog frequency variable s. This
technique follows naturally the Z transform
development presented in the first section
because the normalized Z transform was shown
to result from the application of a sampled
waveform (analog) to a continuous network.
This effect resulted in replacing the derivatives
of the differential equation with forward
differences. The w (or bilinear) transform
method uses a more complicated expression to
approximate the derivative, and good filters
result. This method is considered an indirect
implementation because it is a mapping of an
analog transfer whose form is based directly on
some frequency response criteria.
Early digital filter work was based on contemporary analog theory. The realization came
very early that poorly performing filters
resulted when digital designs were based on

For More Information call 1-800·722-7074.

Finite impulse response digital filters
are characterized by their time limited impulse
responses. These filters may be implemented
in the analog world through the use of LC type
tapped delay lines or charge coupled delay
lines. However, they are still discrete time
filters in spite of their analog or semi-analog
implementation. From a mathematical standpoint
they have no real analog counterpart in that
no expressed or implied attempt is made to
simulate integrating or differentiating operators which are the elements of a true analog
fi lter.
Practically speaking, the advantages of
FIR filters cannot be truly realized because
the time delay cannot be simulated in an
analog fashion without some objectionable side
effects. In a charge coupled device (CCO)
amplitude errors accumulate as the signal propagates down the line. Noise is a problem,
and limited dynamic range is attainable with
currently available devices. LC delay lines
(which only approximate time delay) are limited
to medium frequency applications due to the
large inductor capacitor sizes necessary for low
frequency work. Both techniques have high frequency rolloff characteristics which make precision filter designs difficult. Time delays
can be implemented in the digital machine to
the accuracy of a crystal oscillator. There is
no insertion loss problem, and dynamic range is
dependent only on the word length of the computer
(i.e., 12, 14, 16 bits).
In general IIR filters are more efficient
than FIR filters. For a given order no FIR
filter can achieve as sharp a transition as the
best IIR filter with the same ripple error
constraint. A typical FIR filter may take twice
as much memory as an IIR filter with the same
specification requirements.
In contrast, FIR filters are generally much
easier to implement than IIR types and generally
less susceptible to roundoff noise. The main
feature of a FIR filter is its capability to

*Such techniques as the impulse invariant and
matched Z transform methods are generally
frowned upon in serious filter design applications. The reader is referred to Rabiner and
Gold, "Theory and Application to Digital
Signal Processing," for an in-depth discussion
of these methods as well as the method of
approximation by forward and backward
differences.

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TP-6A
achieve an exact linear phase response if
desired. IIR filters are typified by the wild
phase excursions through the transition regions
which can cause severe distortion problems in
image, radar, and speech processing systems.
Optimization techniques which are applied
to analog and digital recursive filters can be
applied successfully to nonrecursive structures
to achieve very accurate approximations to a
desired or ideal frequency response. Specifically, the Chebyshev criterion which minimizes
the maximum error over a band of frequencies
can be applied to FIR design to yield equiripple
filters with the added attraction of linear .
phase.
To describe all the virtues and mathematical
techniques behind the design of FIR filters is
beyond the intent of this paper. The reader
is directed to the sources named in the
bibliography for the detailed research on the
various design techniques. The signal flow
graph for a general FIR filter is given in
Fi gure 23.

Equation (42) is just the convolution sum for
a finite duration impulse response with input
xn . The Z transform of hn which relates X(z)
and Y(z) is found by letting xn = esnT as in
Section 1. (esnT)(e-smT) = xn-m and the Z transform is given in Equation (43a) and (43b).

~m
H( Z)

N-l
= H(Z)

L

n=O

h Z-n
n

(43a)

hO + hl Z-l + h2 Z-2 + • . •
(43b)
hN_l Z-(N-l)

4.3 Constraints on hn for Linear Phase
True linear phase filters have a phase
function of the form

The constraints on hn can be indicated by
examining the function in Figure 24 which is
symmetric about the point t = O. It is shown
as a finite duration continuous function but
may be piecewise linear or purely discrete.

X n-IN-1)

L----yn

Figure 23.

FIR Signal Flow Graph
(z-l terms represent data
delays of one clock time T)

Figure 24.

Symmetric Time Function

The function in Figure 25 is h(t) shifted by to
and therefore symmetric about to'

The filter output consists of input xn and
past samples xn-1, xn-Z, ... xn-N of various
weights. The weights (h o - hN-1) define the
impulse response of the filter directly. Output Yn at any instant in time nT is given by
equations (42a) and (42b).
hN_1 xn-(N-1)
(42a)

y

7·52

n

=

Figure 25.

Shifted Symmetric Time Function

(42b)

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TP-6A
Without regard to realizability assume that
h(t-t o ) is the impulse response to some filter.
We desire the frequency response or the network
function of the filter. The Fourier transform
may be used.

H(s)

I S=JW. = H(jw)

Letting T
limits gives

i

=

1:

t +t l
0

. t

2itl h(,) cos
o

.f tl

0

J

tl

(44)

-tl

h(,) is symmetric about, = 0 and theref~re
h(,) = h(-,). Equation (44) can be rewrltten.
H(jw) =[e-jwtoj.
(45)

h(-rl sin WT dT

-tl

t-t o and with the appropriate

H(jw) =

d,

is in general different for each w but it is
always a real number,and hence imparts no phase
shift. Negation of the imaginary term

H(t - t ) e- Jw dt

t -t
o 1

w,

keeps the integral portion of the eigenvalue
real and therefore ensures the phaseless
transfer of eigenfunction eJwt .
Before tabulating the purely discrete
network characteristics based on these findings,
the case of an antisymmetric impulse response
is analyzed.
Figure 26 is a transfer function which
exhibits anti symmetric behavior about t = to.
Proceeding as before one finds that the
real integral disappears leaving.

H(jw)
Letting

a

=-, in the first integral gives

With e±je described as cos e ±j sin

H(j"} •

,.j"',

[2

~"

e

hh} '" "' "

_ j j t l h(-r) sin WT dT+j j t l h(-r) sin WT dT
o

0

Figure 26.

The second and third integrals cancel each
other. The first integral and a phase term
e-jwto are left. Recall that in ganeral H(jw)
is a complex eigenvalue which modifies amplitude
and imparts a pahse shift. e-jwto has amplitude
unity and phase shift t(w) = wto. It is linear
with wand simply represents a constant throughput time delay of to seconds. The integral

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Antisymmetric Function

The integral is imaginary, implying an additional -90 degree phase delay added to the
linear phase term.
These filters are usually considered
linear phase, although strictly speaking

Raytheon Semiconductor

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TP-6A
~(w) = -wt o - n/2 is not a linear function of
w. More accurately they are termed constant
group delay filters since d$/dw = -to = constant.
Purely linear phase filters have constant group
delay and constant phase delay.* These filters
are used for differentiators and Hilbert transformers where a constant 90 degree pahse shift
is needed.

4.4 Linear Phase Configurations for Discrete
Filters

'"---_-"--~-~~-

Four structures for the Nth order linear
phase digital filters (Figure 23) are:
1)

N odd, hn symmetric

2)

N even, hn symmetric

3)

N odd, hn antisymmetric

4)

N even, hn anti symmetric

A case 1 configuration is shown in Figure 27.
Because N is odd, hn is symmetric about (N-1)/2;
N is arbitrarily 7. If each mode were processed
separately, N-1 multiplications would have to be
performed. Because the impulse response is
symmetric, the delay line outputs may be taken
in groups of two, added together, and multiplied by the apppropriate co-efficient. Only
half as many multiplications are necessary. As
multiplication is usually the most time consuming
operation, a significant savings in machine
time can be realized.

Figure 27.

FIR Structure for N Odd,
Symmetri c Case

*Group delay is defined as the derivative of
the phase function with respect to frequency
(D = d$(w)/dw). Phase delay is defined as
2rr $(w)/w.

7-54

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TP-6A
5.0 SUMMARY

BIBLIOGRAPHY

The Z transform was introduced as the
convolutional solution to a discrete time system
whose input is the system eigenfunction. The
derivation which was modeled after the LaPlace
Transform in section one, provides an easy
transition into the theory of discrete time
signals. It was indicated that with the proper
normalization, the Z transform becomes the
LaPlace transform as the sampling rate approaches
infinity. This presentation is useful in sample
data control system work where it is essential
to understand the effects of sampling on continuous elements.
In modeling digital filters after analog
prototypes, this view point is also helpful.
Such is the case with the w transform whose
complex frequency variable arises from a trapezoidal approximation to continuous integration.

1.

L. R. Rabiner and B. Gold, Theory and
Application of Digital Signal Processing,
Prentice-Hall, Inc., Englewood Cliffs,
New Jersey, 1975.

2.

B.Gold and C. M. Radar, Digital Processing
of Signals, McGraw-Hill Book Co.,
New York, 1969.

3.

J. R. Ragazzini and G. F. Franklin, SampledData Control Systems, McGraw-Hill Book Co.,
New York, 1958.

4.

A. V. Oppenheim and R. W. Schafer, Digital
Signal Processing, Prentice-Hall, Inc.,
Englewood Cliffs, New Jersey, 1975.

As signal processing tasks·become progressively more challenging, the mathematical tools
required to meet their demands become more
powerful and complex. It is necessary for the
engineer and scientist to develop a good intuitive feeling for these tools. A firm mathematical basis is therefore essential.

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7-56

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TP-17B

Correlation ... A Powerful Technique for Digital
Signal Processing

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TP-17B

TABLE OF CONTENTS
1.0

CORRELATION THEORy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
1.2
1.3
1.4
1.5

2.0

Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . . . . . . . . . . . . . .
Correlation................................................................
Convolution...............................................................
Digital Correlation and Convolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Digital Correlator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1
1
2
2
2

BASIC CORRELATOR APPLICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4

Applications Using Unexpanded Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Expanded Code Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4
8

2.1
2.2
3.0

SyNCHRONiZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
3.2
3.3

4.0

MULTIPLE COR RELATOR APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
4.2

5.0

Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Word Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bit Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Serial Connections for Sequences Over 64·bits Long. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Parallel Connectiqn for Analog or Multi·Bit Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

CONVOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
5.2
5.3
5.4
5.5

"Exclusive-Nor" Versus "And" Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . .
Higher-Precision Convolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Precision Convolution with Negative Quantities . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . .
Longer-Sample Convolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Convol~tion of Analog Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20
20
21
21
22

BIBLIOGRAPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7-58

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TP-17B
1.0 CORRELATION THEORY
(1 )

1.1 BACKGROUND

Correlation techniques are used widely in communica·
tions, instrumentation, computers, telemetry, sonar,
radar, medical and other signal processing systems. Corre·
lation has several desirable properties, including:
• The ability to detect a desired signal in the presence
of noise or other signals.
• The ability to recognize specific patterns within
analog or digital signals.

Here, R 12 (T) refers to the correlation between two sig·
nals, vl and v2' It is determined by multiplying one sig·
nal, v1 t). by the other signal shifted in time, v2(t + T ),
and then taking the integral of the product. Thus, correlation involves multiplication, time shifting (or delay)
and integration.
If the functions are periodic, the expression simplifies to:

• The ability to measure time delays through various
media, such as materials, the human body, RF
paths, electronic circuits, etc.
As these properties indicate, correlation is essentially
a comparison process. In fact, we use correlation daily
when we compare sounds, images, or other sensations
relative to other sounds, images or sensations stored in
our brain. The key function of the human comparison
process is to measure mentally the degree of similarity
between two or more parameters. Th is comparison is
generally made with good discrimination against extrane·
ous forms of information and noise. The comparison can
be made in real time, or we can mentally store the data
until some later time.
The mental correlation process is fine where the
decision·making process is not Iimited by time constraints.
However, in electronic systemswe do not usually have the
luxury of performing correlation at our leisure. Correia·
tion must be performed in real time, requiring the use of
electronic circuits that are compatible with the system in
question.

(2)

where To is the period of the functions.
The effects of multiplication, time shifting and integration
can be visualized graphically in Figure 1. This particular
example shows two waveforms that have similar shapes
and equal periodicity. The picture shows one particular
time shift, TO' between v1 (t) and v2(t + TO)' In this
example, 70 was chosen to yield a very low correlation
between the two functions.
A value of TO selected to maximize the degree of overlap between the two functions would yield maximal
correlation. As this example illustrates, the correlation of
two functions is very sensitive to their relative phasing.

Electronic systems that perform correlation have been
around for years, but they have been bulky and ineffi·
cient. The development of VLSI has changed this; now
correlation can be performed efficiently with a minimum
number of components. Before we look at some of
these VLSI components,let's look at the theory behind
correlation.
1.2 CORRELATION

The correlation between two functions is a measure
of their similarity; loosely termed, it is a. comparison
process. This comparison can be expressed mathemat·
ically as the correlation between two functions v 1(t)
and v2(t):

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Figure 1. Two Related Waveforms. The timing is such
that the product v1 (t) v2(t) = 0 for the value
of TO shown.

Raytheon Semiconductor

7·59

TP-17B
The correlation of a function with a time-delayed
replica of itself is called autocorrelation. Thus v 1(t) ;
v2(t), and R 12( T ) becomes R ( T) and is given by:

and

R(n);
(3)

1.3 CONVOLUTION
Closely related to correlation is the convolution of two
functions, v1(t) and v2 (t), which is defined as:

(4)

Inspection of the arguments of functions v 1 and v2 shows
that correlation handles two functions "forward" in time,
while convolution treats one forward and the other back·
ward. Both procedures involve multiplying two functions
together in some fashion, and then integrating the result·
ing product over the range of the common independent
variable, "t". Mathematically, filtering involves the con·
volution of an input function, v(t) with the system's
impulse response, h(t), yielding:
+~

C(T) ;

where C(

T )

f_ ~

v(t) h(

T -

(5)

t) dt

is the functional output of the filter.

1.4 DIGITAL CORRELATION AND CONVOLUTION
Whereas all the functions discussed so far are continuous analog representations of physical variables, digital
signal processing requires functions to be represented in
discrete form, where the time scale and amplitude are
quantized into discrete steps. The above integrals are
changed into sums and the functions take on a finite num·
ber of discrete values. The convolution and correlation
equations in discrete form become:

y(n) =

L

x(k) h(n - k)

L

v1(k) v2(n + k)

(6)

k;-~

respectively. Here, the indices "k" and "n" measure out
the variables denoted by "t" and "T" in the earlier discussion. In practice, the summations will cover finite
ranges of values of "k", rather than the infinite range
shown here. The ranges selected will depend on the
durations of the two functions and of their sampled portions, and on their periodicities (if any).
A digital correlator circuit can perform both correia·
tion and convolution, operating according to the discrete
summation equations. The remainder of th is chapter
describes a monolithic digital correlator that can perform
digital correlation and convolution at a 20·MHz rate.
Correlation and convolution will be discussed further in
the other chapters, which discuss several applications of
the monolithic correlator.
1.5 DIGITAL CORRELATOR
The major functions of an all·digital correlator are
shown in Figure 2. A reference shift register stores the
reference word, and the input word is applied to the input
shift register. Both shift registers are n bits long, where
"n" is any whole number. The respective bits of the two
shift registers are connected to individual exciusive·NOR
gates, whose outputs are applied to a summing network.
In operation, the correlator output is obtained by
al igning the input word (in the sh ift register) relative to
the reference word. The respective bits in the two shift
registers are compared by the exclusive-NOR gates, whose
outputs are summed. The shift registers, the exclusiveNOR gates, and the summer fulfill the three functions of
correlation: time delay, multiplication, and integration,
respectively.

INPUT
SIGNAL

STORED
REFERENCE

ANALOG OR
DIGITAL

k=-~

SUMMER

Figure 2. Basic Correlator

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For More Information call 1-800-722-7074.

TP-17B
A new and first-of-its-kind monolithic digital correlator from TRW LSI Products is the 24-pin TDC1023J,
which can perform 64-bit parallel correlation at 20 MHz_
Its block diagram is shown in Figure 3_

output of the digital summer is a 7 -bit word representing,
in binary, the number of bit positions in the A register
and R latch that are in agreement at any instant of time.

To perform correlation with the TDC1023J, the input
signal is serially shifted into the independently-clocked
A-register and the reference word is serially-shifted into
the independently-clocked B register_ A +1 logic value
at "clock R" copies the reference word from the B register into the "R latch. The user can then serially load a
new reference word into the B register while correlation
takes place between the A register and the R latch_

The M register is a 64-bit, independently-clocked mask
register that permits the user to select bit positions where
no comparisons are desired. This is accomplished by
inserting a 64-bit serial word into the M register, with
logical "O's" in the "no comparison" bit positions. Since
the outputs from the M register are appl ied to the AN D
gates that also contain the outputs from the exclusiveNOR gates, masked bits are prevented from reaching the
digital summer_

Data in the A register and R latch are continually compared bit-for-bit by the exclusive-NOR gates, whose outputs are applied to the digital summer via AND gates_ The

Either true or inverted binary outputs can be obtained
from the TDC1023J through use of the INV control line,
which operates on the outputs of the digital summer. The

DATA REGISTER

••••••••••••••••••••

AoUT
CLKS

•
•
•

PIPE LINED
DIGITAL
SUMMER

64
7
INV

THRESHOLD
FLAG
LDR

REFERENCE LATCH

3-STATE

•••••••••••••••••

THRESHOLD
REGISTER

.................
REFERENCE
REGISTER

MASK REGISTER

••••••••••••••••••••
--oVCC
---"OGND

CLKT

MOUT
7-81T PARALLEL
DIGITAL OUTPUT

Figure 3_ TDC1023J Digital Output Correlator

For More Information call 1-800-722-7074_

Raytheon Semiconductor

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TP-17B
inverters' exclusive-OR gate outputs feed seven, 3-state
output buffers controlled by signal TS_ (Logical "1" on
the TS disables the buffered outputs by placing them in a
high impedance state_) When INV is a logical "1", the
seven 0 0-0 6 outputs are inverted; when INV is a logical
"0", they are true.
The TDC1023J also has a 7-bit, independently-clocked
T register, which is used to establish a correlation threshold. Exceeding the threshold causes a logical "1" on
Flag T, the threshold flag. The threshold is set by first
disabling the output buffers using the TS control line,
then using outputs 0 0 -0 6 to parallel-load the desired
threshold number into the T register. Flag T is activated
when the binary number from the digital summer equals
or exceeds the threshold stored in the T register.

2.0 BASIC CORRELATOR APPLICATIONS
A binary correlator compares, bit-by-bit, one sequence
of binary digits against another. If these two binary
sequences are derived from different sources, such as the
phase patterns of a transmitted CW radar signal and its
reflected return, the operation is cross-correlation. In
contrast, auto correlation is the comparison of a single
binary sequence against a time-shifted copy of itself.
Cross-correlation applications include:
• Detection of differences (e.g., errors) between two
data sequences;

• Direct autocorrelation or cross-correlation of nonredundant non-expanded data;
• Comparisons of expanded-code data sequences, in
which extra bits have been added for error-rejecting
redundancy or for other uses, such as multiplex
addressing; and
• Synchronization of a receiver/analysis system with
an incoming signal.
2.1 APPLICATIONS USING UNEXPANDED DATA
Many correlator applications involve comparing a given
data sequence or pattern against a standard ("correct")
sequence. As shown in Figure 4, when presented with
two sequences of up to 64 bits each, the correlator counts
the number of bits in one sequence th~t match the corresponding bits in the other sequence. The difference (E)
between the total number of bits under comparison (N)
and the correlator's output (R, the number of coincident
bits) is the number of deviations (presumably errors)
between the two sequences,{e., E = N - R.
CORRELATOR REGISTER A:

crEST DATAl

COR RELATOR REGISTER B:

(STANDARD OF COMPARISON)
OUTPUT:

• Determination of the time delay between two similar signals, such as a radar transmission and its
returning reflection;
• Correction of errors in expanded-code (redundant)
data streams;
• Multiplexing of data among several users;
• Recognition of specified patterns within a data
stream; and
• Synchronization of a decoding process or analyzer
(such as a TV. receiver's scanning circuits) with an
incoming data stream.
Autocorrelation is often employed to identify periodicities within a data stream, as a time-domain alternative to
spectral analysis and the associated time domain - frequency domain transformations. Similarly, it can
"extract" a periodic signal from its random noise background, since the signal will yield high autocorrelation
levels, while the random interface will not.
The TDC1023J fits three broad classes of correlator
applications:

7-62

LI_'....L._°.....LI_'.......1_°......r.I_'.....LI_'_IL-'......r.I_'...J
1+1+0+0+1+1+0+1-'

In this example, N = 8, R = 5, and E = 8 - 5 = 3. The
correia tar's registers are filled serially with the two binary
sequences shown; the corre/atar's output of "5" indicates
that in 5 of the positions, the two sequences coincide.
Figure 4. Correlation of a Data Sequence Against a
Standard
2.1.1 Logic Analyzer
In principle, the TDC1023J correlator could be used
in the automated testing of digital circuits. This trivial
application is included as a tutorial example ...to illustrate
the correlator's function, rather than as a suggestion for
a cost-effective, practical device. The other applications
discussed in this paper use the correlator's unique capabilities far more efficiently. In this application the data
values (logic levels) of a specified group of test points
are entered serially into one of the correlator's registers.
The remaining register is filled with the corresponding
"correct" pattern for that device, test point(s), and test.
The difference between the number of bits under comparison and the number of agreements is the number of
errors detected.

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For More Infonnation call 1-800-722-7074.

TP-17B
Although this type of operation does not identify the
exact location of a given error, it flags and counts errors
rapidly and automatically. In the automatic testing of a
complex device, the correlator can count agreements as
they arise during a long test cycle. The resulting total
number of agreements (correlation score) can be regarded
as a figure of merit for the device under test. A maximum
possible score throughout the test procedure indicates
error-free performance. This application is suitable for
assembly line testing, where parts exhibiting no errors
are passed, those exhibiting one or more errors are rejected,
and there is generally no need to describe or locate each
error precisely.
A complication in this application is that the correlator
can be loaded only with serial streams of data, whereas
most test situations involve the simultaneous examination
of data values at several parallel test points. Therefore,
parallel-to-serial conversion of the data is often required.
This requirement is a constraint primarily in high-speed
multipoint testing, where the correlator's input must be
rapidly multiplexed among several inputs (test points).
Where higher speeds are required, two or more correlators
may be employed in parallel, with each correlator monitoring a group of test points.
Since a typical TDC 1023J correlator can accommodate
a 20 MHz bit rate, the number of correlators required is at
least N x R/20, where "N" is the number of test points to
be examined and "R" is the rate at which they must be
checked (in MHz).
Figure 5 is a simplified bllJck diagram of a multiplecorrelator system designed to perform high-speed error
analysis of several test points simultaneously. For simplicity, a separate correlator is wired to each test point in
the circuit. During the test;the sequence of data values
appearing at each test point is clocked serially into the
corresponding correlator's A register. At the end of the
test, each correlator's output score is read.

SYSTEM UNDERGOING
EVALUATION
TEST POINTS

1.2345678
00000

OUT

Figure 5. Multiple-Correlator Test Fixture Block Diagram

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In this example, the test fixture includes a separate
TDC1023J correlator for each test point. During testing,
the values appearing at these test points are fed serially
into the respective A register inputs. Each correlator's B
register holds the "correct" pattern for its test point.
When a full test sequence is stored in each A register,
the correlator outputs are summed.
The TDC1023J 64-bit digital output correlator has
three features that simplify actual implementation of the
system in Figure 5. First, if fewer than 64 bits are required
in a test sequence, the masking register can be used to
select only the desired A register contents, ignoring all
others. Second, the digital summer outputs and the
register input and output ports facilitate serial connection of n correlators, allowing test sequences longer than
64 bits. Th ird, when set to the appropriate "pass" level,
the threshold register will automatically activate a flag
to distinguish between parts passing and failing the test
sequence.
The correlator's input registers must be appropriately
clocked, to ensure that they read the desired test data
values, without omissions or duplications. This is particularly critical where parallel-to-serial conversion
(multiplex switching) is employed to enable each correlator to evaluate several parts or test points. Furthermore, since its inputs feed directly into one-bit-wide serial
shift registers, the correlator is limited to verifying high
(logic "1") and low (logic "0") levels, rather than indeterminate, high-impedance, or rapidly oscillating levels.
When properly timed, the correlator can process brief
impulses, as long as its maximum shift rate of 20 MHz is
not exceeded. Since the input register set up time is
25 nsec, each input signal must remain valid for at least
this long, to ensure proper data handling. The minimum
correlation clock time of 50 ns also limits the TDC1023J's
real-time correlation rate to 20 MHz.
Two sign'als can be loaded into and across the A and B
registers at a bit rate of 20 MHz for pre-correlation alignment. They can also be clocked at 20 MHz during realtime correlation, in which a correlation score is computed
for e~ch new alignment. Although the data can be realigned and correlated continuously at 20 MHz, the three
steps of internal pipelining in the digital summation network imply that the "Nth" correlation score will be available while the "N + 3rd" alignment is being clocked into
the A and B registers. The user's timing and control logic
must allow for this pipelining latency period.
2.1.2 Time Delay Measurement
A simple correlator-based system can determine the
time delay between two similar patterns of bits, such as a
transmitted radar or sonar signal and its reflected return.
In this example, the two signals appear similar in shape
or bit pattern, but will exhibit a relative time shift of
2 D/C, where D is the antenna-target separation and C is

Raytheon Semiconductor

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TP-17B
the speed of light (or the speed of sound, in sonar and
ultrasound systemsl. Theoretically, this time delay will
cause a low correlation between the two signals, even
though without the delay, the two signals would corre·
late well. As shown in Figure 6, correlator·based time
delay measurement entails gradually "el iminating" the
time delay by shifting one signal with respect to the other.
The highest correlation is obtained when the total shift
just compensates for the original time delay between two
signals. The transmitted signal can be a burst of energy
which contains a particular phase or amplitude pattern,
or it can be a continuous signal comprising periodic repe·
titions of a pattern.

~ CORRELATOR REGISTERS--i REG COR

TIt)

TRANSMISSION

T
~

REAL-TIME

Rltl

ONE-BIT DELAY

Rlt+H

TWO-BIT DELAY

R(t-+21

THREE_BIT DELAY

R It+3)

1 000

8

0 [710001 .. 1.

~"

~

1

100[7]oooD otd al
A

4

- - - SIGNAl. TIME DIRECTION

I

I
I--TD--I

I
I

(EARLIER)

TIME

__

(LATER)

Signal"T" is the original transmission; "R" is the reflected
return. In real time, Rand T are separated by the time
delay TO, which causes them to correlate poorly, Shift·
ing R to eliminate the relative time delay will yield a high
correlation. The time behaviors of both signals determine
the correlation pattern. In this figure, earlier values are
to the left of later ones.
Figure 6. Data Shifting for Time Delay Measurement
For time delay measurements, the TDC1023J's B regis'
ter is fed the "original" signal, such as a transmitted radar
(or sonar) pattern, while the A register is simultaneously
filled with the (delayed) "return" signal. The two regis'
ters are clocked together, so that the time delay between
the signals appears as a displacement in their relative regis'
ter positions, as shown in Figure 7. After loading both
registers, the system monitors the correlator output while
continuing to clock the A register only. This loads pro·
gressively later return signal bits, wh ile sh ifting the de·
layed pattern across the original pattern as in Figure 7.
The number of bit shifts required for an acceptable cor·
relation, times the signal's bit time (inverse of frequency)
is the total time delay between the two signals.
For time delay measurement the transmitted code
must be long and complex enough to avoid false or ambiguous alignments. For example, a code such as 101010101
would clearly be unsuitable for time delay measurement,
since all shifts of 2N bits (where N = 1, 2, 3, ... ) would
yield high correlations, causing ambiguous results. In
contrast, a code which repeats only once every 500 characters is much more likely to provide an unambiguous

7-64

First, the original transmission and delayed reflection are
loaded simultaneously into the B and~A registers, respectively. Next, the B register clock is stopped, while the A
register clock continues to read in the return signal and
shift it across the register. The highest correlation occurs
when the" A register only" clock cycles have just compensated for the original delay between the signals.
Figure 7. Time Delay Measurement with a Correlator
measure of any time delay of less than 500 bit times,
although even this code would be unsuitable in some
applications involving longer time delays.
When a nonrecurring code, such as a single burst of
information, is employed in time delay measurement, the
length and pattern of the transmitted code are still constrained. Under ideal circumstances where the only objective is to measure distance to a target, a simple isolated
pulse, e.g., a single positive bit surrounded by negatives
or zeroes, can be transmitted, as shown in Figure 8. The
returning reflection of this signal contains a similar isolated pulse, delayed by the round-trip travel time between
the antenna and the target. However, this is an insensitive
• I

SHIFT REGISTER t64-8ITS)

CORR

10

0

0

0

0

0

0

0\'''\ 0

0

0

0

0

•

0

0

0

0

oEJ· oIso

10

0

0

0

0

0

0

oHo

0111 •

0

0

0

0

0

0

0

0

10

0

0

0

0

0

0

01.. ·/0

0

0

0

0

0

0

0

0

0

•

0

0

0

0

01 . .

moo IA

..

10 64

As in Figure 7, the original signal is loaded into the B
register. The return is clocked across the A register until
a correlation of 64 is obtained. Note that the total correlation score is relatively insensitive to the imposed time
delay, reaching 64 for perfect alignment, but 62 at all
other times.
Figure 8. Single-Pulse Time-Delay Measurement

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TP-17B
alignment test, with a total correlation score of 62/64
when the transmitted and received pulses are mis-aligned,
versus 64/64 for perfect alignment.
In the presence of noise or interference, the return signal could contain one or more false positives, which could
reduce the perfect·alignment correlation and generate
other equally high correlations.
Longer codes are used to improve the accuracy and
sensitivity of the time delay measurement, as shown in
Figure 9. Here, a seven-bit "Barker code" is chosen for
its low correlation with random noise and with timeshifted versions of itself. Although the longer pulse code
cannot improve the 64/64 correlation score for perfect
time alignment, in the presence of noise it will greatly
reduce the chance of a burst of random noise causing a
high correlation. For a given level of interference and
concommitant bit errors, increasing the Barker code
length tends to reduce the frequency and magnitude of
false correlations, thereby enhancing the accuracy of the
range measurement system. The interested reader can
refer to the literature on Barker codes, which offer the
lowest. achievable error rates and highest sensitivity for
these appl ications.
A caveat in time delay measurement is that the bit
rate of the code must be high enough to permit precise
measurement of the time delay, since the correlator can
measure time delay only to within ±'1 bit time. A higher
bit rate permits a more precise determination of delay
time, but increases the amount of data to be handled.

2.1.3 Identification of Periodicities in a Data Stream
This autocorrelation application involves comparing a
single data stream against a time-delayed replica of itself,
in order to identify periodicities or patterns. First, as
shown in Figure 10, the signal is loaded simultaneously
into the A and B registers. Then, when the registers are
full, the B register pattern is held stationary, while the
incoming signal continues to be clocked sequentially
through the A register, to simulate a steadily increasing
time shift. Periodicities in the data paqern generate high
correlations, which appear periodically as the A register
contents slide past the B register. These correlation peaks
are separated by low correlations, and the number of bits
between sequential high correlations corresponds to the
period of the repeating pattern. For example, the data
sequence 100100100100 exhibits a high autocorrelation
for every delay of 3N bit times, where N = 1, 2, 3, ....
Random noise can make a periodic signal harder to
detect, by reducing the contrast between the periodic cor·
relation peaks and the low "residual" correlations between
them. However, a correlator can still identify signal
periodicities, in the presence of surprisingly high levels of
random noise. If SImI and S(m + n) are the original and
time-shifted versions of the pure signals, and N(m) and
N(m + n) are the corresponding additive noise values, then
the correlator performs the following sum:
63

R(n) =

L:

[SImI + N(m)l [S(m + n) + N(m + nIl

(7)

m=O
7-81T REGISTERS

CORRELATION

o

~

1

1

1

1

1

1

1

1

1

1

1

1

1

o
0

1

o

1

1

0

o

no
D

~

0

o

o

0

1

I

1

1

1

1

B

0

0

0

0

As

0

0

0

0

A,

0

0

0

A2

0

0

A3

0

A,

1

1

AS

1

1

Asl

1

A, 1

0

o

J7l

0

1

1

1

1

o

0

0

oJ"7Lo

0

0

0

o

1

I

~

o
0

1

J

0

SImI
N(m)
SImI
N(m)

~

In this example, alignment within one bit time generates
a significantly higher score than any other degree of
relative timing between the two signals.
Figure 9. Time·Delay Measurement with a Seven·Bit
Barker Code

For More Information calI1~-722-7074.

where m and n are indices representing discrete steps in
time. (In this example, the sum runs arbitrarily over 64
values only because this is the length of the TDC1023
correlator.) The function being summed comprises four
terms:
S(m+n)
N(m+n)
N(m+n)
S(m+n)

Truly random noise does not correlate significantly with
either S or with its time-shifted self; therefore only the
term SImI . S(m + n) contributes significantly to R, the
overall sum. However, according to statistical theory,
the noise products do not necessarily vanish if the summation is over a data set too short to constitute a statistically representative sample. When a short sample is
considered, the noise can interfere significantly, masking
the pattern of periodic high and low correlations. To
handle a data sample longer than 64 bits, the user can
increase the length of the summation by cascading two or
more correlators in series.

Raytheon Semiconductor

7-65

TP-17B
I·

-I

20 BlT FfEfA:)r£Iff;\

I
I

----.0
I

n

E

I

I

I
I

n

E

I

I
I

I

I
I

I

I

E

I

I
I

E

I

I
I

I

I

Cl I I I
Cl I I I
I Cl I I

r

n

I

I
I

I

I

I
E

r

I

1

I

1

I
I

I

I
I

A

fA]

I

CORR

20
10

A,

Table 1. Code Expansion for Redundancy

A2

I

I
I

I 'a
I "0

A

I
I

I

I
I

I
E

I

I

1

~_CJ

I

I
I

I

E

I
I

I

I

I
I

I

n

I

":l

'0

A,

20

As

10

A6

I I I
LI I I

(such as addressing) in the data stream. Tables 1 and 2
present examples of these two types of code expansion.
In Table 1, each of the four original 2·bit codes is reo
placed by one of four 6-bit codes, strictly to add redun·

A,

10

As

20

In this example, a'single bit error in the original code will
alter its meaning. In contrast, a single·bit error in the
expanded code will no t change its meaning, if the system
can recognize the intended pattern from the five unaltered
bits.
ORIGINAL CODE

00

The original signal is fed, in duplicate, into the A and, B
registers, generating a perfect correlation. The A register
copy is sequentially shifted, while the B register copy is
held static. Periodicities in the data then cause periodic
peaks in the correlation score.
The letters "An and "E" tag specific pulses of the signal,
for the reader's convenience.
Figure 10. Autocorrelation and Signal Periodicities
2.2 EXPANDED CODE APPLICATIONS

EXPANDED CODE

o1
o

o0
o1

0 1 0 1

-1 0

0 1 0

0 0 0 0

1 1 1 1 1 1

dancy for error protection. In Table 2, each code now
bears a third bit, which assign,S the coded information to
one of two potential users. There is no redundancy in
Table 2; every bit bears essential data or address
information.
Table 2. Code. Expansion for Addressing

The unexpanded data applications described in Sec·
tion 2.1 involve direct use of data or data streams, without added redundancy or other expansion of the original
code (pattern of bits). The following applications involve
the comparison of expanded-code data streams against
one another. Despite its increased length, which slows the
transmission of useful information, expanded code is used
for several purposes, including:
• Correction or flagging of errors;

In this sample format, the first two bits bear the message,
while the third identifies the intended receiver.
ORIGINAL
MESSAGE

INTENDED

RECEIVER

~

o0
o,

000
o, 0

o0
o,

1 0
, 1

1 00

1 0 1
111

1 1 0

,

FORMAT:

1

MESSAGE

ADDRESS

X X

X

• MUltiplexing of code (when address information is
included within the data stream); and
• Automatic recognition systems, which also involve
incorporating address information within the data
stream.
An "expanded code" is one which contains extra data
bits, beyond those absolutely required to convey the information it contains. For example, since there are four
possible 2·bit combinations: 00,01, 10, and 11, up to
four possible data values can be unambiguously represented by assigning each to one of these 2·bit combinations ("minimal codes"). In an expanded-code application, each of the four data values is assigned to one or
more "expanded" codes longer than two bits, i.e., the
original four values would be mapped into a space containing a larger number of possible values. The extra bits
of an expanded code can be used either to add redun·
dancy (for error detection) or to convey new information

7-66

2.2.1 Error Correction
Error correction systems can operate only on expanded
code, since it is data redundancy that enables them to de·
tect and identify incorrect values. A maximum-efficiency
code, such as ordinary binary numbers, can tolerate no
errors. For example, if 1110 (14) is intended.. but 0110
(6) is sent, there is no way to determine whether the 0110
is actually a true "6" or an intended "14" or other value,
with one or more erroneous bits.
However, by expanding the 16 possible 4·bit binary
values into seven bits, a 7-bit "code alphabet" can be
developed. A system using this expanded code can cor·
rect single errors and detect up to two simultaneous
errors. With the ordinary (unexpanded) binary system,
each code is separated by only one bit from its neighbor-

Raytheon Semiconductor

For More Information caiI1-800-722-7074.

TP-17B
ing codes, such that a single l-bit error transforms one
allowable code into another, unintended code. In coding
terminology, the "distance between codes" is 1 bit and
the number of "tolerable simultaneous errors" is zero.
Expanding from four bits to seven increases the total
number of possible combinations of bits from 24 = 16
to 27 = 128, a factor of eight. Only 16 of these 128
codes are regarded as valid, whereas the remaining 7 x
16 = 112 codes each represent a one-bit deviation from
one of the correct codes (Table 3). Since each true code
is chosen to differ in at least three bits from all other
correct codes, the "distance between codes" is now three
bits, and each single-error code can be unambiguously
associated with a particular correct code. Thus, each
of the N = 16 original true values has been mapped into
eight expanded codes, one representing the nominally
correct expansion, the others each containing a single
error in one of the seven bit positions of the expanded.
code. In this case, since the distance between adjacent
codes is three bits, the system can positively identify and
correct l·bit errors. The system can detect 2-bit errors,
but cannot distinguish between these and other single·bit
errors.
Table 3. Seven-Bit Expansion of a 4-Bit Code

Note that the last four bits of each expanded code are
merely the original four-bit code. Furthermore, if fourbit code" A" is the inverse of four-bit code "6," then
their seven-bit expansions will exhibit the same inverse
relationship.

ORIGINAL

EXPANDED

000 0

0000000

000 1

o1

001 0

1100010

001 1

101

o 1 00
o1o1
o1 1 0
o1 1 1
1 000

1 000 1

o0

1 1

1 1 1 0 1 00
1 000 1 0 1
00101 1 0

o 1 001 1 1
1 o 1 1 000

1 001

1 1 0 1 001

101 0

o1

1

o1

1 1 0 1 0

1

000 1 0 1 1

1 1 00

010 1 100

1 1

o1

001 1 1

o

1

1 1 1 0

1 001 1 1 0

1 1 1 1

1 1 1 1 1 1 1

Correlator-Based Error Correction System
An error·correction system can be designed with the
TDC1023J correlator (Figure 11). In the 7-bit expanded
code example, the correlator is set to compare seven consecutive bits of incoming signal sequentially against the
16 "correct" 7-bit codes. This is accomplished by reading
seven signal bits into the correlator's B register, and then
clocking in the first trial 7-bit "correct" code from a
memory. If a low correlation is obtained, i.e., if fewer
than six of the signal bits agree with their "paradigm"
counterparts, then the next code is loaded into the
register. If the second pattern also fails to produce a
correlation score of 6/7 or 7/7, then the third pattern is
loaded in, and the process continues until a correlation of
7 or 6 is obtained, presumably corresponding to a match
(or near-match) between the correct code and the signal.
When this high correlation is obtained, the correct code
value (from the memory) is sent to the system output. If
the correlation score is a perfect 7, the output will equal
the input, with no change. In contrast, if the correlation
score is 6, the output will be the error-free intended code,
even though the input contained a l-bit error. In this
example, the correlator's output th reshold level is set to
6, to flag only perfect and near-perfect correlations.
The threshold flag can also be used to restart the B
register clock, if desired. This system can operate at a
fixed rate, clocking in a new data word after each full
cycle through all ROM combinations, or a new data word
can be clocked in as soon as a high correlation is reached,
effectively "short-cycl ing" the system. The TDC 1023's
unique architecture, with the serial A and B registers,
plus the R latch, accommodates high-speed operation,
by permitting the user to load each new data sample into
the B register wh ile the previous sample (in the R Latch)
is compared sequentially against the paradigms being
shifted across the A register.
This system must be modified for high-error rate applications_ As described, it yields the wrong output when
fed a code containing two errors, since any two-error
versior'i of a code is indistinguishable from a one-€rror
version of another code. Thus, given correct codes of
A = 1100110 and B = 0010110, a two-error version of

ROM

I---H

AIN

AOUT
CORRELATOR
TDC1023J

INCOMING SIGNAL

CORRECTED OUTPUT

SIGNAL

BIN

L -_ _---'-::.:::....---I

The incoming signal is loaded into the B register, while
the first paradigm code is loaded into the A register.
If the resulting correlation is high, the threshold flag
opens the output (AND) gate, sending out the correct
code from AOUT' If the correlation is too low, the next
code is loaded in, etc_, until a high correlation results.
Figure 11. Correlator-Based Error Correction System

For More Information call 1-800-722-7074.

Raytheon Semiconductor

7-67

TP-17B
code A, e.g., 0000110, is indistinguishable from one single'
error version of B, 00QOll0. The correlator mistakenly
identifies the two-error A code as a one-error B code, and
put out a false B code as its interpretation of the true data
value. If a relatively high error rate is anticipated, then
an even longer code expansion must be employed to
increase the system's error tolerance. Using a carefully designed enhanced code, double, triple, or higher order
errors can be accurately corrected. The maximum number of simultaneous errors that can be corrected is always
less than half of the distance (number of bit changes)
between codes. Sin\:& longer codes imply slower transmission of useful information, there is an obvious tradeoff
between a code's efficiency and its error tolerance.
One disadvantage of correlator-based error correction
is that the correlator must run through numerous comparisons for each segment of incoming signal code. With a
16-combination, 7-bit code, the correlator must compare
the incoming data stream against each of 16 stored
combinations.
Since each pattern is seven bits long, up to 7 x 16 =
112 clock cycles are required to test each 7-bit segment of
incoming code. Thus, in this example the maximum
permissible bit rate for incoming information is 1/16 of
the correlator's maximum bit shift rate. If higher data
handling speed is required, the incoming data stream can
be fed into two or more correlators simultaneously (Fig·
ure 12). If two correlators are used, each correlates the
incoming data segment against only half of the possible
true values from the memory. When one correlator
"finds" an acceptable high level of correlation between
the data stream and one of its stored' paradigm patterns,
it then feeds the contents of its comparison register
serially into the output.
INCOMING SIGNAL

CORRECTED
StGNAL
OU11'--.....---H~-...,
R6
R7 330
DATA &
560
:>O-'\N'V-_-f ClOCK
INPUTS

DIGITAL
GROUND

U2
lM313

R4
IK
+
CaMP

REF+ REF-

UI

TDCIDI8

0.01

RI
J9

"
F

>-_ _ . _ - - - - - -...

VOUT

Figure 1.

For More Infonnation call 1-800·722·7074.

75

Raytheon Semiconductor

7·91

TP-33
/31

x Rl
/31 + 1
where /31 is the forward current gain of transistor Q1.

VOUT

WHITE

IEOl

=

x

The current in Q1 as a function of O/A converter output
current can be shown by:

=r

U2 +

IV~~2 -

BlACK

IEOl

SYNC

where VU2 is the forward voltage drop across band-gap
reference device 11.22 Volts nominallyl and lOlA is the O/A
output current flowing into the OUT-terminal of the O/A
converter.

Figure 2

1-\-2pOmil3
. .i ....•.•..•..
WHITE

BlACK

r-I-r II....
II
rJ
-

~

~

E;s

1,

,

...

..

I

.11

lOlA

1M
I
~

III

~
I

II ·· .

."m

II

II

121

The transfer function of the TOC1018 O/A converter in its
linear range is given by:
= [(

M

1+

VBElj_ lOlA

inpu~5:ata) x IREF x Kl}

+ IBLK

131

where IREF is the reference current flowing into the REF+
terminal of the O/A converter, Kl is a constant derived from
the datasheet, and IBLK is the nominal O/A output current
when the O/A converter outputs "black."
IREF, IBLK, and ISYNC output current levels can be determined
from the Operating Conditions Table and the Video Control
Truth Table found on the datasheet for the TOC1018.

Figure 3

Analysis Of The Current "Turn - Around" Circuit
A set of equations is helpful in tailoring this circuit for a
specific application. Equations ·1, 2, and 3 show the derivation
of the transfer function of the circuit Equations 4, 5, and 6
come from information presented on the TOC1018 Datasheet
The relationship between the output voltage of the circuit to
the current in Q1 is given by:

IREF

=

(

IBLK

=

19.4 mA nominally

Kl

=

VU2
)
R3A + R3B

=

1.115 mA nominally

141
151

ISYNC output current

28.57 mA

IREF

1.115 mA

25.6

161

Conclusion
The circuit described is a true single power supply voltage
output O/A converter. The techniques discussed in this
application note should help clarify the operation of TRW's
high-speed eight and four-bit O/A converters in a TTL
environment

7·92

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TP-40

Non-Linear Operations with the TMC2301
Image Resampling Sequencer
John Eldon and John Watson

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

7-93

TP-40

7-94

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

TP-40

Non - Linear
Op~rations with the
TMC2301 Image
Resampling
Sequencer

Figure 1
(0.0)

(0.0)

.

..
(x. y)

DXVO> 0

Figure 2
(0.0)

(0.0)

John Eldon. TRW lSI Products Inc.
John Watson. U.C.S.D.
The TMC2301 Image Resampling Sequencer is used in an
image filtering and resampling system both to map input
address sequences to output address sequences la geometric
transformationl and to provide a set of local addresses (a
"walk"l with which to calculate each output point's intensity by
interpolation of a selected number of input points' intensities.
Both these functions and the associated control signals are
described in TP-36 and TP-37. Here we will consider the use
of pure and mixed second -order terms to achieve nonlinear
geometric mappings. A general technique for approaching
nonlinear transforms and two simple examples are included.
Finally, a series of parameter sets is given to demonstrate the
effect of second - order coefficients on a rectangular test
image.

Review of Zero and First Order Terms
The TMC2301 implements the following "backward" mapping
from (u, vi, the output address,to (x, yl, the input address
(with the kernel ~ 0, i.e., with no pixel walk, since we are
not yet concerned with interpolation herel:
X~ XO +u*DXUO +lu L ull2'DXUU +u*v*DXUV +v*DXVO clv2 -vI12*OXVV
Y~ YO +u*DYUO +lu 2- ull2*DYUU +u*v*DYUV +v*DYVO +lv 2-vI12*DYVV

.

..
(x. Y)

(u. v)

DXVO 1 AND DYUO < 1
respectively.
DYVO shears the image in the vertical direction, as shown in
Figures 3 and 4:

Figure 3
(0.0)

(0.0)

..

Here we use the notation DXUO ~ dX/dUO,
DXUU ~ d2X/dU, DXUV ~ d2 X/dUdV, etc. As described in
TP-36 and TP-37, the lower-order coefficients operate as
follows:

(x. y)

.

DYUO> 0

XO and YO translate the (u, vi image by shifting its origin.
DXUO copies, expands or ·compresses the (u, vi image
horizontally, for the cases DXUO ~ 1, DXUO> 1, and
o< DXUO < 1 respectively. DXUO < 0 constitutes a reflection
(copied, compressed or expandedl about the vertical axis.

Figure 4
(0.0)

DXVO shears the curve in the horizontal direction, as shown in
Figures 1 and 2:
(x, y)

For More Information call 1-800-722-7074.

Raytheon Semiconductor

DYUO< 0

7-95

TP-40
Meaning of Nonlinear Terms

Figure 7

There are two useful ways to look at the DXUU, DXUV, DYUU,
DYW, and DYUV expressions. On the one hand, they are the
coefficients of U2, U*V and V2 for the separate X and Y
equations Iwith a minor adjustment; see the next section!. On
the other hand, they can be thought of as second derivatives
lor, more correctly, second -order finite differences!. Thus, for
example, the positive half of the parabola y = 2*U2 has a
positive second derivative d2Y/dU = 4 and, indeed, setting
DYUU = 4 and DXUO = 1 transforms the line U = 0 to
Y = 2*U2 lagain, with the necessary coefficient adjustments!.
Likewise, d2X/dUV = ella constantl has the continuous
solution X = c,.*U*V + Iterms in U and V alonel, and with
the TMC2301, setting DXUV = c1 results in a cl*U*V term in
the solution for X Isee above!.

(0,01

With either interpretation, the second -order inputs perform the
following operations lagain, we consider the "backward"
mapping from the rectangular lu, vi ouput to the lx, yl inputi:
DXUU: Just as DXUO expands or compresses an image in the
horizontal direction linearly, so DXUU expands or
compresses it nonlinearly Iwith U2!. For example lagain
ignoring adjustments, i.e., in this example, DXUU is
presumed to directly multiply U21:
Figure 5
(0,01

(0, 01

(0,01

+
(x.

yl

Figure 8
(0,01

(0,01

+
(x.

yl

..
(u,vl

DXVV 0

yl

(U,

vI

DXUU> 0

(x,

Figwe 6

DXUV> 0

(0,01

(0,01

+
(x,

yl

Figure 10
(0,01

(0,01

..

•
DXUU 0

DYUU: This produces a nonlinear warp in the vertical direction,
as in Figures 11 and 12:

Raytheon Semiconductor

For More Infonnalion call HlOO-722-7074,

TP-40
Figure 11

DYUV: This warps the curve in the vertical direction, in which
the lower righthand corner undergoes the maximum
vertical shift, as in Figures 15 and 16:

+

Figure 15

+

Ix. Vi

Figure 12

Ix, yl

DYUV> 0

Figure 16

+
Ix. Vi

+

DYUU> 0

Ix, yl

DYVV: This expands or compresses in the vertical direction
non-linearly, as in Figures 13 and 14:
Figure 13

Iu,vl

DYUV> 0

Compensating the Coefficients
(Not Applicable to DXUV. DYUV)
The "pure" second-order terms are implemented by the
TMC2301 with a double accumulation which results in the
form le.g.l Y ~ DYUU*IU2 - U1/2. Thus, when we wish to
implement a formula of the form Y ~ cl *U2 + c2*U, we
need the following coefficient transformation:

+

DYUU

~

2*cl; DYUO

~

cl

+

c2

The same ianalogousl transformation holds for DXUU, DXW,
DYVV, DXUO, DXVO and DYVO. For examples, see below.
DXUV and DYUV require no adjustment.

Ix. vi

DYVV> 0

(u.vl

Technique

Figure 14

+
Ix. vI

.....-.

I-~ I
(II.vl

Each nonlinear situation requires a different treatment, mainly
because the functional forms can be hard to identify, and
nonlinear matrices cannot be cascaded as the linear operations
such as translation, rotation and scaling can be (see TP-361. A
possible generalized approach is as follows:
8.

DYVV>O

Superimpose the input and output images with the output
(u, vi image aligned with an axis, if possible, so that the U
and V functional forms are dimensionally separable in terms
of the axes.

b. Estimate a functional form of the input lx, Vi image. If
necessary, define a new set of axes to help with this step.
For More Information caJI1-800-722·7074.

Raytheon Semiconductor

7-97

TP-40
c. Working from the image backwards, map the image into
the intermediary axis set lif anyl, rotate the intermediary
axes to the u, v axes lor the u', v' axes setl, then express
the desired U and V functional forms.
d. Remember to adjust the coefficient on any pure first and
second-order terms IDXUU, DXW, DYUU, DYVV, DXUD,
DXVO, DYUO, DYVOI.

The shear IDXDVI affects the mapping of the lu, vi rectangle,
as in Figure 20:
Then, the warp IDXUVI brings the right edge back, as in Figure
21:
Figure 20
(0, 20)

(120.20)

Examples
I. Keystoning

Say that the image lin the x, y plane I is of the form illustrated
in Figure 17, with "keystoning" distortion and horizontal
curvature, and it is desired to correct the perspective and
restore the picture to its rectangular form IFigure 181. IThe
keystoning is rather extensive, to make the example easy to
follow.!
F"lglI"e 17

120 ....~_ _ _&..I
Ix. y) IMAGE

vi

120

(0. 20)

(0.20)

1120.20)

(120.20)

or - - - - - - - - w

120 ......_ _ _ _--'
(DESIRED) (u. v) IMAGE

(u. v)

(u. v)

(INTERMEDIARY)
(120. 20)

r-,-,~-

~

,,

\
,

V

__... "
~

Taking as our functional form, then:
X = U + cl*V + c2*U*V;

"',

,,
,
.,' ... --...." ,,

Step c: Since the shear begins at V = 20 and is linear
thereaher, we translate the starting point:
X = U + cl*IV - 201 + c2*U*IV - 201

'I

(0. 120)
(120. 120)
SUPERPOSITION OF ~x, Y)
AND (u, v) IMAGES

Step a, the superposition, is illustrated in Figure 19. Since the
X and Y components are easily separable Ithe sides are a
function of v, and the top and bottom are a function of ul, no
rotation is necessary.
Step b: To get the functional forms, consider the sides first.
To map the vertical lines U = 0 and U = 120 into the x, y
image, we need a horizontal shear to the right IDXVO > 01 for
the U = 0 line and, then, a horizontal warp to the leh
IDXUV < 01 to correct the righthand side. Since both operations
work as functions· of the original u, v space, the horizontal
warp will not affect the leh edge.
7-98

(0,

(INTERMEDIARY)

Figure 19
(0.0)

(120.120)

Ix. Y)

Figure 21

Figure 18
120

(0. 120)

Since the lehhand side is not affected by c2 and needs a
slope of 115, we know cl = 0.2. Then, plugging in points, e.g.,
X1120. 1201 = 100. we get c2 = -0.0333. Expanding:
X = 1.0667U + 0.2*V - 0.00333*V*U - 4; this can be
checked by substituting in other test points, e.g., IU, VI = /0,
201, 160. 201, 1120, 601, etc.
So DXUO

=

1.0667, DXVO

Raytheon Semiconductor

=

0.2, DXUV

=

0.00333, XO

=

-

4

For More Information call 1-800-722-7074.

TP-40
II. Correcting the Horizontal Cwvature

Turning to the top and bottom, one must choose a functional
form. Unfortunately, one is limited to polynominal forms; a
circle is not available, since Y will equal the square root of
some polynominal function in U. However, an arc can be
closely approximated by a parabolic form, and that is the
obvious choice here. Since Y is positive going downwards, and
the vertex of the parabola is translated along the u-axis by
SO, we suppose a form:

second -order terms available, however, something like the
above approach is usually easiest.!
III. A Tutorial Example

We will now consider a more complex example Iwith little
practical significancel to illustrate the general technique. Say
you were given the following input image Ibottom curve of
Figure 231 and desired output image Itop curve of Figure 231:
Figure 23

Y = A*U2 + S*U + C + V

o

The point IU, VI = 10, 201 maps to Y = 20, and the points
IU, VI = lBO, 01 and 1120, 201 mapping to Y = 0 and Y = 20
respectively. Substituting this yields:
Y = 1111801*U2 - 12/31*U + V
Sut here the OYUU term requires coefficient transformation, as
above. Since cl = 1111801 and c2 = 1-2/31,
OYUU = 2*cl = 0.01111 and OYUO = cl + c2 = -0.6S111.
The "V" term requires OYVO = 1.
Inputting these 7 coefficients Iwith others equal to 01 will
transform the x, y image to the rectangular boundary of
U = 0 to 120, V = 20 to 120. Of course, if the original image
weren't precisely parabolic, there would be some error. In this
case, if the top and bottom were actually circular, we could
easily calculate from Figure 22:

10

5

15

25

20

30

5
10
15

20

25
30

(x. y)

IMAGE

35

Step a, to superimpose the images with the U and V
functional forms aligned with an axis, is already done. Step b
is to estimate a functional form of the input image. To help
do this, we introduce intermediate axes Zx and Zy, extend the
input image to be symmetrical, and measure distances from
the new axes to some known image points IFigure 241:

Figure 22
(60,0)

Figure 24
10

15

20

25

30

35

,.'
- - - - - Iv.

R = ILf212 + IR - abslbll 2
R = ILf212 + b21 I 2*abslbl

=

v)

IMAGE

100, and thus

IBO - XI2 + 11100 - YI2 = 10000. Comparing these values
with the parabolic ones, one can determine the accuracy of
the approximation. If you wish to make it even closer, you can
use a least-squares curve fitting technique by taking more
points from the "ideal" circle.

,

...............

INOTE: To get the functional form desired, of course, the user
may employ any standard technique for translating a series of
points into an explicit functional description. With only first and
For More Information call 1-800-722-7074.

Raytheon Semiconductor

7-99

TP-40
Clearly, we can again estimate a parabolic form for the x, y
image in terms of Zx and ly:
ly = A*(Zx. - 201 2 + B*(Zx - 201 + C
c. Using some points, e.g., (Zx, lyl = (10, 101, (20, 301 and
(30, 101, yields:
ly = (1/51Zx2 + 8*Zx - 50, Zx = 10 to 25.
Now, this axis (from 10 to 251 must be mapped to the
eventual U axis, which can be done by the standard
rotation matrix:.
IX'I
Icos 120° - sin 120°1
IY'I = 1 [Z, l, 11 Isin 120° cos 120°1
Substituting for ly, we get
X' = 0.173*Zx2 + B.4287*Zx - 43.3
Y' = - .1*Zx2 + 4.8BB*Zx - 25
Now, sweeping X' through 10 to 25 is the same as
sweeping Zx through 10 to 25, so we have the x, y image
as a function of the U- axis, U = 10 to 25. But we want
to sweep U from 0 to 15, so we shift:
X = -0.173*(u + 1012 + B.428*(u + 101 - 43.3
Y = O.l*(U + 1012 + 4.8BBB*(U + 101 - 25
Now, we have the original (x, yl curve by tracking along
the U- axis from 0 to 15. But we want to generate it by
sweeping through the output curve, i.e.,
V= -(1/301*U2+(2/31*U. So that this translates into the
desired (x, yl image, we need to add 1 to Yfor each
increment of V (a Y = Vterm, i.e., OYVO = 1, as is
normal in a copy; see abovel and, then, subtract the
expression for V above from each Y point. (See Figure 251:

Inputting these coefficients will indeed transform the given
(x, yl input image to the given (u, vI output image.

Test Images
The above examples all take an "irregular" input (x, yl image
and map it to a rectangular output (u, vI image. For the
purposes of testing (or for intentional distortion of an image!,
the reverse process is useful: taking a rectangular (x, yl input
and producing an "irregular" (u, vI output. Below are 12
examples (assuming a full-scale screen of 512x512 pixelsl of
using 1 coefficient at a time to transform a rectangular input.
The pure second-order coefficients have been compensated, as
described above (e.g., in the first example below, we achieve
X = 1/512 U2 by setting OXUU = 2*Cl = 1/25B and
OXUO = Cl + C2 = 1/5121.
Figure 26
10.01

1512.01

10. 512)

(284, 01

10.01

1512,5121

10.5121
DXUU> 0

lx, yl

(284. 512)
10. vi

DXUU = 0.D0694444
10.0000 0001 1100 0111 00011
DXUO = 0.00341222
10.0000 0000 1110 0011 01011
DYVD = 1

Figure 11

Figure 25

10

The other coefficients map directly: OYVO - 1, XO = 3.B8;
YO = 13.BB.

10,0)

1512,01

10. 01

256

AMOUNT Of
SUBTRACTION

15

This yields (expanding I Y = V - p.OBBB*U2 + 2.2*U + 13.BB.
The U values along the curve will be the sam.e as those along
the axis. Finally, we need to compensate for the OXUU and
OYUU coefficients:
OXUU = 2*Cl = 2*(-0.1731= -0.34B;
OXUO = Cl + C2 = 2.9B8 - 0.173 = 2.795;
OYUU = 2*(-0.OBBBI = -01333;
OYUO = 2.2 + (-0.06661 = 2.1333;
7-100

10. 512)

IMAGE
lx, yl

10.512)
DXUU < 0

1512. 512)
10. v)

DXUU = 11512 = -2- 9
I. .. 111.1111 1111 1000)
DXUO = 1 - 1/1024 = 1023/1024
10.1111 1111 1100 0000)
DYVD = 1

Raytheon Semiconductor

For Mora h,formation calI1.aoD-722-7074.

TP-40
Figure 28
DXW > 0 (WITH

Figure 31
oxuv< 0

DFFSET)

(D, D)

(0,

D) (64, D)

(512, 680)

--.,,

(256, D)

(0, D)

(0, D)

I
I
I
I

I

I
I

I
I

I

I

I
I

I

I

I

I

I

I

I

I

I

{x, V)

(512,512)

(0,512)

(x, y) (256, 512)

(u, v)

(512,512)

(u, v)

DXW = 112048.?' 2-11
(O.OOOO 0000 0010)
DXUD = 409714096
(I.OOOO _
0001 0000)
XD = -64
(. .. 111000000.00 ... )

OXUV = 2- 10
(. .. 111.1111 1111 1100)
OXUO = 1
DVVO = 1

Figure 29

Figure 32

DXW 0
(512,0)

(O,OI

(O, D)

(x, y)

OXUV = 2.7902 10- 4
(0.00000000000100100100)
OXUO = 1
OVVO = 1

For More Information call 1-800-722-7074.

(u, v)

(512, 448)
(u, v)

(0,0)

(512,64)

(448,512)

(512, 512)

(512,512)

(x.

yl

(512, 512)
(u, v)

(512, 576)

OYUU = _2- 11
( ... 111.1111111111100000)
DYUO = _2- 12
(... 111.1111111111110000)
DYVO = 1
DXUO = 1

Raytheon Semiconductor

7-101

TP-40
Figure 34

Figure 37

DYW>O
(0......
01_ _ _ _ _--.

DYUV 0
(512.01

vi

(u,

vi

512. 5121

DYUU = _2- 10
(111.1111 1111 11001
DYUO = 2-2 _ 2- 11
(0.0011 1111 111000001
DYVO = 1
DXUO = 1

Figure 36
(0. 01

(512. 5121

(0.01

We can assume a parabolic form:

Y = Au 2
(512.4481
(0. 5121

(x.

Vi

(512. 5121

DYUV = 312.7902X10- 4
(0.000000000001001001
DYVO = 1
DXYO = 1

7-102

(u,

vi

+

Bu

+

V+ C

Substituting points. e.g.:
Y=
Y=
Y=
Y=

32, IU, VI = 10, 321
32, IU, VI = 1256, 01
512, IU, VI = 1512, 5121
512, IU, VI = 1256, 4801

One arrives at Y = 1/2048 U2 + 114 U + V. which leads to
the parameter assignment listed on Figure 38
IDYUU = 2*1-1120481; DYUO = -112048 + 114.

Raytheon Semiconductor

For More Information call HIOO-722-7074.

TP-40
Test Image for Keystoning
Producing a keystoning effect from an input rectangle requires
some approximation. When we mapped from a lu. vI rectangle
to an lx, yl keystoned image, the sides u = 0 and u = 120
were constants and, thus, the equation
X = a*U + b*U*V + c'V + d became a linear function in V.
If, however, we try to achieve the following transformation in
Figure 39:

Figure 39
(512, O)

(O,O)

(0, 512}

(64, 512)

(512,512)

(x, y)

(512,O)

10, O}

(u, v)

(448, 512)

If one wishes for more linear sides at the cost of some error
at the corner points, one can use a balanced mapping as
follows:
X121.333, 170.6661 = 0
X142.666, 341.3331 = 0
X1490.666, 170.6661 = 512
X1469.333, 341.3331 = 512
The degree of curvature error improves for cases of milder
keystoning and worsens for cases of more extreme keystoning.
For example, in the transformation in Figure 41, a mapping of
the four corners results in X = U - 1130*V + 1/7680*U*V.
Here the maximum curvature lagain halfway down the output
imagel is only 0.26 pixels off from the ideal lIinearl result. By
contrast, if the keystoning extends to X = 128 and X = 384
on the bottom of the output, the maximum error Iwith corner
mapping 1 can be as high as 20 pixels. For cases such as this,
it is certainly advisable to use a balanced mapping, choosing
points 1/3 and 213 of the way down both sides, in order to
reduce the curvature.

we find that the X = a constant = a*U + b*U*V + c*V does Figure 41
not allow U or V to be expressed as a linear function of the
(0, 5121
other. Nevertheless, we can perform a 4-point mapping to
(O,O)
achieve a good approximation, as follows:
,.-------....,

(0, 512}

(O,O)

I

Mapping Points:
X 10, OJ = 0
X 1512, OJ = 512
X 164, 5121 = 0
X 1448, 5121 = 512

I
(0, 512}

Solving four simultaneous equations by substituting these points
into X = AU + BV +CUV + 0, we arrive at:
A = DXUD = 1; B = DXVO = 116; C - DXUV - 1/1536; 0 = XO

=

0

The result is a mapping with ideal lexactl values at the test
points Icornersl but a slight curvature along the vertical sides
of the output image. This curvature amounts to a maximum of
4.6 pixels halfway between the top and bottom Isee Figure 40!.

Figure 40
(512,O)

(O,O)

(512, 5121

(16,512)

(u, v)

(496. 512)

The TMC2301's nonlinear terms can be put to use in a wide
variety of application -specific ways. One can, e.g., flatten out
curved surfaces by simply applying a pure second order term
Iwith rotation, if necessary!. The magnitude of the
second -urder coefficient can be calculated by mapping points
estimated from the size and location of the original image on
the screen, as above. Similarly, one could flatten out an object,
which is tilted away from the camera by mapping the four
corner points. In cases like these, the coefficients have to be
estimated and adjusted according to the particulars of camera
angle and image location.

(475.4, 256)

(36.6, 256)

(64, 512)

(x. y)

(u, v)

(448, 512)

For More Information call 1-800-722-7074,

Raytheon Semiconductor

7-103

TP·40

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For More Information, call 1-800-722-7074.

TP-47B

TMC2302P5C Demonstration Board

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

7-105

TP-47B

7-106

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For Mora Information, call 1-800-722-7074.

TP-47B
The TMC2302P5C Demonstration Board
Introduction
The Raytheon TMC2302P5C Demonstration Board is designed to demonstrate some of the image
manipulations possible with the TMC2302 Image Manipulation Sequencer. The Demonstration Board
stores a source image up t0512 x 512 eight-bit pixels. The TMC2302 addresses the source image
elements in a manner determined by the type of manipulation being performed. Each addressed pixel
proceeds through a color look-up table (TMC0171) prior to display. The TMC0171 Color Palette maps
each of the 256 possible color values to the 262,144 displayable pixel locations.
The TMC2302 can perform up to a third-order warp on the source image. The software for the
Demonstration Board allows the user to individually edit the coefficients controlling the warp. The
software can also generate coefficients based on mouse-driven parameters or pseudo-random
sequences.
The Demonstration Board performs a few of the large number of image manipulations possible with
the TMC2302. The Demonstration Board performs only nearest neighbor resampling on twodimensional images. When used with a multiplier-accumulator (Raytheon's TMC2208 and TMC221 0)
or a multiplier-array (Raytheon's TMC2246, TMC2249 or TMC2250) the TMC2302 is capable of
convolutions and bi-linear and bi-cubic interpolations. These interpolations produce much smoother
images (fewer aliased artifacts, jagged edges) than the nearest neighbor resampling performed by the
Demonstration Board.

Configurations
the Demonstration Board and its software are designed to run on an IBM-compatible PC, XT, AT, 386
or 486 personal computer. It will run in a PC bus-compatible slot, or from an IBM PC type parallel port.
If a math coprocessor (8087, 80287, 80387 or the coprocessor section of an 80486) is present in the
host computer, the supplied software will use it. If a math coprocessor is not found, the floating-point
operations will be done by the host processor. This may cause the system to run more slowly than ti
would if a math coprocessor was present.

For More Information call 1-800-722·7074.

Raytheon Semiconductor

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TP-47B
Some of the demonstration software requires a three button mouse with MSmouse driver
installed on the host computer. If the software can't find the driver or the mouse, it will indicate
so and prevent those routines from executing.
The amount of main system memory required for the demonstration program is about 150K
bytes.
There are two independent options for installation. The first option determines how the host PC
communicates with the Demonstration Board. The second option determines how the monitor(s)
are connected to the Demonstration Board and the host PC.

Host Connection
The Demonstration Board can be installed in a PC-compatible slot in the host computer, or
run from a parallel port. The PC slot installation can be more convenient for long-term
installations in one host computer. The parallel port installation does not require the PC
case to be removed, but an additional cable and external power supply are required.
A Demonstration Board installed in the host computer will use I/O ports 300-307h and
310-317h. If any other devices in the system respond to these addresses, the board will
not operate properly and system damage could result. Check the address ranges used by
network or interface boards to ensure that there will be no conflict.
If the Demonstration Board is to be operated from the parallel port of the host computer,
then an adapter cable is needed to connect the parallel port to the dual-row header on the
Demonstration Board. This adapter cable is not supplied with the board, but is readily
available from computer supply companies. An external power supply (+5 Volts at 2
Amperes) with a disk drive style power connector will be needed. The cable pin functions
are shown in Section 4.
The board may respond faster when installed on the host computer AT bus, but this may
not be apparent in a 12 MHz AT or 386 system.

Monitor Configurations
A single VGA monitor may be shared between host computer display (text) and
Demonstration Board display (image). A separate monitor (VGA or an RS-170 block sync
monitor) can be used for the Demonstration Board display.
If a single monitor is used, the VGA output from the host computer is routed through the
Demonstration Board to th9 monitor. The Demonstration Board switches the monitor over
to its output under software control.
If separate monitors are used for the Demonstration Board output, the VGA pass-through
cable is not used. The monitor for the Demonstration Board can be either a VGA type

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For More Information call 1-800·722-7074.

TP-47B
multi sync monitor or an RS-170 compatible color or monochrome monitor. The RS-170
monitor must handle block sync, since no serration pulses are provided.
Cables for connecting monitor(s) are not supplied with the Demonstration Board. For the
RS-170 block-sync option the green video output should be used (connector pin function
information is provided in Section 4).
Board Instal/ation
If the board is installed in an internal slot in the host computer, the Demonstration Board edgeconnector provides all the signal and power required. The board can be installed in any free PC
or AT bus slot. Plug the board in and tighten the bracket mount screw ensuring that the board is
properly supported and that it cannot touch adjacent boards. The 26-pin parallel port header
(marked "J3") and the four-pin power connector (marked "J4") must be disconnected while the
Demonstration Board is installed in the host computer.
If the board is operated outside of the host computer, the 26-pin dual-row connector on the
Demonstration Board should be connected to a parallel port with an appropriate adapter cable.
The dual-row header end of the cable connects to J3 with pin 1 closest to the "J3" marking. The
other end of the adapter cable connects to a standard parallel 1/0 port. A 5 Volt D.C. regulated
power supply capable of supplying 2 Amperes should be connected to J4. The pin functions for
both cable connections are shown in Section 4.
Monitor Instal/ation
If a single monitor is used, then the 15-pin hi-density end (three rows of pins) of the VGA input
cable should be connected to the output connector on the host computer VGA card. The is-pin
Sub-D end (two rows of pins) is then connected to the Demonstration Board.
If a VGA monitor is used (whether as a single monitor shared with the host or as an additional
monitor to the host computer display), the monitor cable should connect to the 1S-pin hi-density
D connector on the Demonstration Board. For RS-170 operation. the monitor connects to the 15pin hi-density D connector.
Batch Demonstration Operation
A simple batch program is provided that will run with any of the installation configurations. The
disk marked "TRWDEMO" contains all the software needed to run the batch demonstration.
Insert this disk in drive A: and type: A:DEMO to start the program, which will load an image and
manipulate it. See Section 2.4 or Section 6.0 if the program does not execute. If the program is
to run from a hard disk, use MKDIR to make a directory and copy the files to the hard disk
directory.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

7-109

TP-47B
Problems
The demonstration program will display diagnostic messages when it starts. If the message
"Demonstration Board not found" is displayed, the program was unable to locate the board on the
PC bus or on a parallel port. If the Demonstration Board is installed in the PC bus, this error may
be caused by another board at the same bus 1/0 addresses as the Demonstration Board. Some
network and interface boards use the same addresses. Conflicting boards should be removed
from the system. If the Demonstration Board is connected to a parallel port and is not found by
the software, check the board power by observing the lit LED. If the LED is not illuminated,
check the power supply voltage. Additionally, it may be necessary to check the adapter cable
connections.
Software
The Demonstration Board is supplied with programs to manipulate images and perform
diagnostic tests. The following programs are included:
a.
b.
c.
d.
e.
f.

TRWDEMO.EXE - the main demonstration program
TRWDIAG.EXE - the diagnostic program
TRWOFF.EXE - a program to return the display to the VGA card
TRWSRC.C - a sample C program to run the Demonstration Board
DEMO.BAT - a batch file to run a short demo
TRWSCRPT.TXT - the script that is piped to TRWDEMO by DEMO.BAT

TRWDEMO
This program executes the various demonstrations. When initialized, it searches for the
Demonstration Board on the parallel ports starting at the highest addressed parallel port.
After checking the parallel ports, the PC bus is examined for the presence of the
Demonstration Board. The test of a parallel port will disrupt any current print job on that
port. The automatic port search can be overridden, if necessary, with the command line
option Ip:# which causes the parallel port at base address # to be used (Le.
"trwdemo/p:378" uses the parallel port that starts at address 378h). The command line
option Ii causes the program to only look for a Demonst~ation Board installed on the host
computer bus.
All other configuration options are automatically sensed. Configuration and debugging
messages are displayed as the program starts to help isolate problems.
There are four command line options. The Ip and Ii options were discussed above. The Is
command line options causes the program to not wait for a key to be struck to stop the
current sequence. This is useful for batch files, since the key wait routine will not see
characters in the batch file. The If option causes the program to use an optimized math
coprocessor routine for some calculations. This results in faster execution, but requires
the presence of a math coprocessor. This may be beneficial on slower machines that
have a coprocessor installed such as an 80287 on a 286 system or an 8087 on an 8088

7-110

Raytheon Semiconductor

For Morelnfonnation call 1-800-722-7074.

TP-47B
system. If the If option is not specified, the program will automatically use the
coprocessor, if present. If no coprocessor is found and the If option is not specified, the
host processor will do all computations. If the If option is specified and no coprocessor is
present, program operation is unpredictable.
After the program has determined the configuration and location of the Demonstration
Board, a list of available commands is displayed. A command is invoked by entering the
command number followed by [cr]. The commands are:

o • Terminate
This command causes the program to terminate and returns to C:>.
1 • Load Image
This command loads an image into the Demonstration Board source image
memory. The program will ask for the file name of the image to load. The main
demonstration program can load images into the Demonstration Board from
several image formats. The extent on the image file name is used to determine
the type of image being loaded. The following are supported:
a.

.GIF

b.

.PIC

c.

.MAP

d.

.RGB

e.

.BW

'Graphics Interchange Format' is a trademark of CompuServe,
Inc.
Mouse Systems PC Paint Picture File Format is limited to 4- and
8-bit version 2.00 images.
768 bytes of lookup table information followed by a 512 x 512
image. The format may change.
512 x 512 image data uses a lookup table that maps the top 3 bits
to red, the next 3 bits to green, and the bottom two bits to blue.
512 x 512 image data uses a lookup table that maps the values to
a grey scale.

2 • Edit Coefficients
This command allows individual coefficients to be edited. More than one
coefficient can be specified on a line. The [cr] key will switch the monitor back to
allow editing of more coefficients. If no coefficients are entered, the [cr] key will
return to the main menu. The values entered are floating point. Note that the
higher order coefficients have dramatic effect and should be kept quite small.
Also note that the target (screen) origin is at the beginning of the back porch
(during blanking). For a Demonstration Board with 20 MHz clock displaying VGA,
this means that pixels less than U = 40 or V = 33 will be blanked. A good starting
command is "aO -100 bO -50 a1 1 b4 1" which sets Xo(Ao) = -100, Yo(Bo) = -50,
dX/dU(A1 ) = 1, and dY/dV(B4 ) = 1.
3· Rotate
This command rotates the image 360 degrees in one degree increments.

For More Information call 1-800·722·7074.

Raytheon Semiconductor

7-111

TP-47B
4 - Warped Rotate
This command executes a combined warped rotation.
5,6,11,12, and 14 - Various Random Warps
These command selections cause the image to be warped under control of the
host computer. Typing a key on the keyboard stops the warp at the end of the
current pass.
7 - Other
This allows changing of options that affect the way the image wraps around at its
edges. The submenu allows you to select one of the following:

o
1
2
3
4

Clips to the image border. This is the default mode.
Wraps the image around in all directions.
Wraps the image around in quadrant 4, relative to the source image.
Clear coefficients between commands. This is a default mode._
Do not clear coefficients between commands. This allows editing of
coefficients created during other transformations.

8 - Mouse Corner Warp
The mouse is used for this control point warp that uses the four corners of the
image as the control points. When no mouse buttons are depressed, the upper
left corner of the source image is moved by moving the mouse. The left, middle
and right buttons control the remaining three corners of the image. Pressing the
left and right mouse buttons simultaneously returns to the main menu.
9 - Mouse Rotate and Zoom
The mouse controls rotation and scaling of the image. Moving the mouse while
holding no buttons, one button or two buttons changes rotation and scaling
parameters. Simultaneously pressing the left and right buttons returns to the main
menu.
10 - MONG
A paddle game. This uses vertical mouse motion to move the paddle up and
down.
13 - Spin Down
This selection spins the source image while expanding it from a reduced size.
The the image is reduced in size by clipping without minifying.
TRWDlAG - Diagnostic Software
TRWDIAG allows the Color Palette and image memory to be tested. This program has a
menu similar to the one in TRWDEMO. Selecting the number for an option causes that
test to be run. The image memory tests take quite a bit longer over the parallel port then

7-112

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For More Information call 1-800-722-7074.

TP-47B
they do with the Demonstration Board installed on the host computer bus. The options
are:
0- Quit
This section terminates the program.
1 - Parameter Select
This allows changes to the parameters used by the tests. The check parameter
allows only the writing of the pattern to memory, only checking a pattern that is
already in memory, or both writing the pattern and checking the pattern. The
pattern parameter controls the pattern used to check the memory. The triple
pattern is good for address testing. The random pattern uses a polynomial based
pseudo-random number generator. The H ramp and V ramp patterns produce an
incrementing pattern across or down the source memory. The seed is used as a
starting value for all tests. A value of zero should not be used with the random
pattern. The offset controls the starting phase of the triple pattem.The count
controls the number of times the test is run. A count greater than one causes the
seed to be changed for each pass of a test.
2 - Image RAM Test
This selection tests the source image memory.
3 - DACTest
This selection tests the image Color Palette memory in the TMC0171. The mask
is determined by initial testing when the program starts. If the DAC is determined
to only be 6 bits, then only the lower six bits are checked.
4 - DAC Mask Test
This selection tests the mask register in the TMC0171. It tests 256 patterns for
each count. If there are no errors encountered, the mask is restored to its initial
value.
5 - DAC Mask Set
This selection shows the current value of the mask and allows a new value to be
entered. If the mask is set to FFh and the Combo Test (selection 8) is run, the
DAC RAM array will be tested for sensitivity to asynchronous pixel inputs.
6 - Print RAM Region
This selection allows a region of the image RAM to be displayed as hexadecimal
numbers.
7 - Print DAC Region
This selection allows a region of the DAC Color Palette RAM to be displayed as
hexadecimal numbers.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

7-113

TP-47B
8 - Combo Test
This option puts a triple pattern in the image RAM and a random pattern in the
DAC and checks them. A triple pattern is then loaded in the DAC and a random
pattern in the image RAM. These patterns are then checked and the mask is
checked.

9 - Clock
This option makes a rough measurement of the frequency of the oscillator on the
Demonstration Board.

10 - Border Image
This option writes a test image to image RAM and sets the TMC0171. Use
TRWDEMO to view the image. The left edge is red, the right edge is green, the
top is blue, and the bottom edge is yellow. Inside this bounding box are some
color check blocks. Since the box border is a single pixel wide, the aliasing in the
nearest-neighbor sampling may cause a border not to appear when the image is
minified.
TRWOFF
This program switches the system to the VGA display if it is chained through the
Demonstration Board. This can be a useful program to run from the system
AUTOEXEC.BAT file to ensure that the computer does not boot with the display switched
to the Demonstration Board output. This program searches for a bus-installed card first. If
it does not find the Demonstration Board on the bus, then the parallel ports are checked.
To go directly to a Demonstration Board on a specific parallel port, the /p:# command line
option can be given (similar to the TRWDEMO/p option).
The Demonstration Board Hardware
Memory Map
The following table describes the memory locations for the registers that are used to
control the Demonstration Board. These addresses arecfor a bus installed Demonstration
Board. Other sections describe the translation used for addressing these registers from
the parallel port.

7·114

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TP-47B
Memory Map for 2302 Demonstration Board

Address

Type

Function

Bits

300

RD

Status Register

0- VFLAG
1 - Monitor Select 0
2 - Monitor Select 1
3 - Monitor Select 2
4 - VGA feedthrough
5 - Relay
6 - Collision
7 - Control bit 7

WR

TMC2302 data lower byte

RD
WR

TMC2302 data higher byte

302

RD
WR

Vertical Clear
TMC2302 Address

303

RD
WR

Control Register

304

RD
WR

RAM data
RAM data

305

RD
WR

RAM address YA<9 .. 6>

RD
WR

RAM address XA<7 .. 0>

RD
WR

RAM address YA<5 .. 0>,XA9,CA8

301

306
307

For More Information call 1-1100-722-7074.

Raytheon Semiconductor

0- 23021nit
1 - Download
2 - Download Write
3 - Wrap Source
4 - Reserved
5 - Relay
6 - Overlay Enable
7 - Reserved

7-115

TP-47B
TMC0171 Color Palette Addresses
Address

Function

310
311
312
313
314
315
316
317

Write Mode Address Register
Palette Data
Mask
Read Mode Address Register
Write Mode Overlay Address*
Overlay Data*
Reserved
Read Mode Overlay Address*

* the Overlay function is not present for TMC0171 Color Palette

Control Register Functions
The control register (Address 303h) sets the base mode for the Demonstration Board.
23021NIT
DOWNLOAD
DOWNLOAD WRITE
WRAP SOURCE
RELAY

OVERLAY ENABLE

Setting and then clearing the 2302 INIT bit will initialize
the TMC2302s.
Setting the Download bit allows the image memory to be
read.
Setting both the Download and the Download Write bits
allows the image memory to be written.
The Wrap Source bit causes the source image space to
wrap around in both dimensions.
When the Relay bit is cleared, the VGA input is passed
through. When the Relay bit is set, the Demonstration
Board image is passed through to the output connector.
The Overlay Enable bit enables a special mode that is
used for MONG. In this mode the TMC2302 TVAL
signals are used to set an overlay, instead of controlling
the blanking region at the edge of the screen.

The TMC2302 control registers are set by writing the desired address in the TMC2302
Address register. Next, the lower byte of the TMC2302 data is written to the TMC2302
Data Low Byte register. Finally, the higher byte is written to the TMC2302 Data High Byte
register. Writing the high byte causes the data to be written to the selected TMC2302. Bit
7 of the TMC2302 Address register selects the X-coordinate TMC2302 when LOW, and
the Y-coordinate TMC2302 when HIGH. The TMC2302 addresses are use coefficient bit
32 as the bottom bit of the X and Y image address. The sub-pixel bits below bit 32 are
ignored and the bits above bit 40 (for a 512 squared source space) are also ignored.
The image RAM is written by setting the Download and Download Write bits in the control
register, the desired address is set in the three RAM address registers, and the data is

7·116

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TP-47B
written to the RAM Data register. To read the image RAM, set the Download bit in the
control register. Then, set the desired address in the three RAM address registers.
Finally, read the data from the RAM Data register. The TMC0171 Color Palette mask
should be cleared prior to setting the Download bit. The mask should only be set back to
3Fh after the Download bit cleared.
Status Register Functions
The status register (Address 300h) reads back status from the Demonstration Board.
V FLAG

MONITOR SELECTS
VGA FEEDTHROUGH

RELAY
COLLISION

VFLAG is active if a vertical blanking interval has come
along since the last time VFLAG was cleared. VFLAG
is cleared by reading the Vert Clear location.
The Monitor Select bits (0, 1, 2) reflect the state of the
Monitor Select bits coming back from the VGA monitor.
The VGA Feedthrough bit is LOW if the VGA chaining
cable is connected from the Demonstration Board to a
VGA card. Otherwise this bit is HIGH.
The Relay bit reflects the status of the elay bit in the
Control register.
The Collision bit indicates that the image and the
overlay were coincident when in Overlay Enable mode.
This bit is cleared by reading the Vert Clear location.
Status bit 7 reflects the state of bit 7 in the Control
register.

Parallel Port Access
To access a Demonstration Board on a parallel port, bit 2 of the parallel port control
register must be set LOW. The parallel port uses an additional register on the
Demonstration Board. This register is loaded by outputting the data on the parallel port
data register and taking bit 3 of the parallel port control register HIGH and then LOW. The
bottom five'bits of this additional Demonstration Board register are the same as the bottom
five address bits when the board is installed in the system bus. Bit 5 should be left LOW.
If bit 6 is taken from a LOW to a HIGH, the read back shift register is loaded.
The parallel port control bit 0 is taken HIGH for a read to the Demonstration Board. The
readback data is read one bit at a time on bit 7 of the parallel port status register. The
readback data starts with the last significant bit, and is advanced to the next bit by taking
bit 3 of the parallel port control register HIGH and then LOW. Since this will also load the
additional register described above, bit 6 on the parallel port output data should be kept
HIGH to keep from reloading the readback shift register. The parallel port inverts the
readback data. The parallel port control bit 1 is taken HIGH for a write to the
Demonstration Board.

For More Information call 1-800·722·7074.

Raytheon Semiconductor

7-117

TP-47B
Connector Pin Functions
This section gives the pin functions for the VGA output connector, the VGA chaining input
connector, the PC slot edge connector, the parallel port connector, the auxiliary power
connector, and the two signal probe headers.
Hi-Density VGA Output Connector (J1) Pinout

7·118

Pin Signal

Pin Signal

1
2
3
4
5

7
8
9

Red
Green
Blue
Monitor Select 2
Ground

6

10

Ground
Ground
Ground
SP1
Ground

Raytheon Semiconductor

Pin

Signal

11
12
13
14
15

Monitor Select 0
Monitor Select 1
Horizontal Sync
Vertical Sync
SP2

For More Information call 1-800·722·7074.

TP-47B
VGA Chaining Input Connector (J2)
Pin

Signal

Pin

Signal

1
2
3
4
5
6
7
8

Red
Green
Blue
Monitor Select 2
Ground
Ground
Ground
Ground

9
10
11
12
13
14
15

SP1
VGA Sense
Monitor Select 0
Monitor Select 1
Horizontal Sync
Vertical Sync
SP2

PC Slot Connector
Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

NC
0(7)
0(6)
0(5)
0(4)
0(3)
0(2)
0(1)
0(0)
NC
AEN
NC
NC
NC
NC

A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31

NC
NC
NC
NC
NC
NC
A(9)
A(8)
A(7)
A(6)
A(5)
A(4)
A(3)
A(2)
A(1)
A(O)

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15

Ground
Reset
+5 Volts
NC
NC
IR02
NC
NC
NC
Ground
NC
NC
lOW
lOR
NC

B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31

NC
NC
NC
NC
NC
NC
NC
IR05
IR04
IR03
NC
NC
NC
+5 Volts
NC
Ground

For More Information call 1-800-722-7074.

Raytheon Semiconductor

7-119

Tp·47B
Parallel Port Adapter Cable

7-120

J3 Pin

Parallel
Port Pin

Signal

Use

PC Port

1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

Strobe
0(0)
0(1)
0(2)
0(3)
0(4)
0(5)
0(6)
0(7)
Ack
Busy
P.End
Select
Auto Feed
Error
Init Prt
Select In
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground

lOR
0(0)
0(1 )
0(2)
0(3)
0(4)
0(5)
0(6)
0(7)
VGA Sense
Readback Data
VFLAG

Control Bit 0
Data
Data
Data
Data
Data
Data
Data
Data
Status Bit 6
Status Bit 7
Status Bit 5
Status Bit 4
Control Bit 1
Status Bit 3
Control Bit 2
Status Bit 3

lOW
Enable
Control Strobe
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TP-47B
Auxiliary Power Connector (J4)
Pin

Signal

1
2
3
4

No Connect
Ground
Ground
+5 Volts

X Probe Connector (X-coordinate TMC2302 Signals)
Pin

Signal

Pin

Signal

1
3
5
7
9
11
13
15
17
19

Ground
TVAl
TADR(3)
TADR(O)
KADR(O)
TWR
KADR(2)
SADR(2)
SADR(3)
ACC

2
4
6
8
10
12
14
16
18
20

Ground
ENDD
DONE
TADR(2)
TADR(1)
KADR(1)
KADR(3)
SADR(O)
SADR(1)
SVAl

V Probe Connector (V-coordinate TMC2302 Signals)

For More Information call 1-800-722-7074.

Pin

Signal

Pin

Signal

1
3
5
7
9
11
13
15

SVNC (pulled up)
NOOP (pulled up)
TVAl
TADR(3)
TADR(O)
SADR(2)
SADR(3)
Ground

2
4
6
8
10
12
14
16

Ground
ClK
ENDD
TADR(2)
TADR(1)
SADR(O)
SADR(1)
SVAl

Raytheon Semiconductor

7-121

TP-47B
Jumpers
The table below shows the jumper positions for a 512 x 512 source space. The board should be
positioned so that the bracket is towards the right. The jumper on W1 is vertical (up means
connect the middle and top pins with the jumper plug). The remaining jumpers are horizontal (up
means connect the top two pins together with a jumper plug).

Jumper Positions
Jumper

Position

Jumper

Position

W1
W3
W5
W7
W9
W11

Up
Middle
Up
Up
Down
Left

W2
W4
W6
W8
W10

Middle
Up
Up
Down
None

Hardware Description
The TMC2302 integrated circuits are designed to provide the capability to rapidly manipulate
images. The TMC2302P5C Demonstration Board allows the user to become familiar with the
types of manipulations possible with the TMC2302. It also provides test points for examining the
timing and control sequencing of the TMC2302.
The board has three major blocks. The first of these is the warp address generator, which
consists of two TMC2302s (identified in the block diagram as the X TMC2302 and Y TMC2302).
The TMC2302s operate at video rate and generate the address sequences for the manipulation
being performed. The second major block is the Image RAM where the source image is stored.
The TMC0171 Color Palette is the third major block. It converts the digital pixel values from the
Image RAM into red, green,and blue signal levels for display on a video monitor.
The warp address generator provides X and Y addresses to the Image RAM. The TMC2302
generate these addresses at video rate, and generate most of the video timing information as
well. The Target Valid (TVAL*) signals from the X and Y TMC2302s are used for video sync and
blanking, respectively. The TMC2302s operate continuously and the target windows are set up
to provide the appropriate Target Valid timing. The X and Y addresses index the appropriate
pixel for the location currently being refreshed on the video display.
The Image RAM provides the appropriate pixel value for the address being indexed. This RAM is
static and operates at the video pixel rate. The TMC0171 Color Palette uses the pixel data to
address it's on-chip RAM (color look-up table or color palette). The color palette provides the
red, green, and blue values for the pixel being refreshed. These levels are sent to the video
monitor.

7·122

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For More Infonnation call 1-800·722·7074.

TP-47B
Hardware Interface
The Demonstration Board supports operation in a personal computer card slot or from a PCcompatible parallel port. When the board is operated from a parallel port, the port signals are
converted to the same signals that would be generated from an internal PC card slot. The
parallel port decode register holds the value that is used to simulate the lower bits of the address
that would normally come from the PC bus. The ENABLE signal is HIGH to enable PC bus
operation, and LOW for parallel port operation. When using the parallel port, ENABLE tells the
decode logic to ignore the upper address bits. Reading back from the parallel port involves
loading the Readback Shift Register with a data byte and then shifting the data to a parallel port
status line, one bit at a time.
The Video Out signals come from either the TMC0171 Color Palette or the VGA Video In
connector. If a single display is shared between the Demonstration Board and a VGA display
board, then the Video Source Relays switch the two sources to the monitor.

Downloading
Each of the major functional blocks contains data that must be downloaded. These are the
coefficients for the address generators, the source image for the Image RAM, and the color
palette RAM data for the TMC0171. The TMC2302s and TMC0171 can be loaded at any time.
The Image RAM must be switched into a special download mode. The TMC2302s do not allow
read back of coefficients. The Image RAM and TMC0171 both allow their data to be read. The
download mode (with one variation) is used to upload the Image RAM. When downloading (or
uploading) the decode logic converts the PC bus address into a strobe for the section of board
being addressed. These strobes are used to load data into RAMs or registers, or to enable data
out of RAM or the Status Buffer. The Data Bus Transceiver isolates the heavy loading of the
local data bus from the PC data bus.
When downloading, the TMC2302 Address Register and TMC2302 Low Data Register must be
loaded before sending the high byte data. Writing the high byte causes the transfer of the high
and low data to the address contained in the TMC2302 Address Register.
Downloading (or uploading) to (or from) the Image RAM is more complex. The Control Register
download bit (bit 1: referred to as "Download" in the Demonstration Board instructions but named
"DNLOAD" on the schematic drawings)s) must be set. This control bit changes the source of the
Image RAM X and Y address from the TMC2302s to the RAM Address Registers. To enable
write data to the Image RAM and to disable the Image RAM output buffers, another Control
Register bit ("Download Write" in the instructions and "DNWR" in the schematic drawings) must
be set. After these control bits have been set, the desired X and Y Image RAM address must be
written to the RAM Address Registers. Then the image data byte can be read or written.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

7-123

TP-47B
Programmable Array Logic
There are two Programmable Array Logic (PAL) devices on the TMC2302P5C Demonstration
Board. One is used exclusively for decoding the addresses used to access the board. The other
handles a potpourri of video functions.
The Decode Logic consists of the decode PAL and a decoder IC. The decode PAL generates all
the read strobes and just the write strobes for the decoder IC and the TMC0171. The decoder IC
decodes the individual write strobes for the registers and the Image RAM. All of the decode
signals are asynchronous. The decode PAL uses different equations for PC bus and parallel port
operation. The ENABLE signal (abbreviated ENAB in the PAL code) is HIGH for bus operation
and LOW for parallel port operation. It changes the decode from using PC bus address lines A9AO to using the Parallel Port Decode Register lines A4, A2, A1 and AO. PWR and PRD are the
TMC0171 write and read strobes. MORE is the enable to the decode IC to further decode a
write operation. RAMDAT is a decode for either reads or writes to the Image RAM. For an
Image RAM write operation, both RAMDATand MORE will be active. STATUS is a read decode
to the Status Buffer. DEN enables the Data Bus Transceiver, and is active for PC bus reads to
any of the Demonstration Board, for PC bus writes, for parallel port writes, or for cases where the
bus is quiescent (to keep the local data bus quiet by preventing it from floating for long periods).
The Video Timing PAL generates some of the video monitor control signals and two status flags.
BLANK is the blanking signal to the monitor. The equations define the inactive state of BLANK,
which means they define the active video display region (BLANK is the compliment of active
display for each individual dot clock interval). For operation without either overlays or source
image wrapping (normal mode), the pixels of the warped image are displayed if the source X and
Y pixels were valid and the Y TMC2302 target region is valid. The Target Valid (TVAL) signal
from the Y TMC2302 defines the normal active display region for the monitor. When source
image wrapping is enabled, the SVAL X and Y signals are not used to clip the displayed area to
the source image bounds. This causes the source image to wrap around to fill the entire
displayable area of the screen. In overlay mode (used for MONG), the source image is always
assumed to be in a displayable screen area. SVAl X and Y determine the displayable area for
the source image. TVAL Y (abbreviated TVY in the PAL source) determines the overlay region
independently from the source image region. The OlO signal is activated for overlay region (not
supported by the
TMC0171.)
For VGA display operation, VCNT1, VCNT2, and VSYNC generate a two line sync interval.
Horizontal sync comes from the TVAl X signal. For RS-170 block sync, the TVAL X region is
programmed to generate composite sync.
The Video Timing PAL also generates two flags that are available through the status buffer.
VFLG is set when the X TMC2302 is done with the video display refresh sequence. Both
TMC2302s continue refreshing the screen using the coefficients in their respective control
parameter preload buffers. VFLG indicates to software that there is a vertical interval available to
change the contents of the control parameter preload buffers before the new coefficient set is
used. VFLG is cleared by writing to the decode location that generates the VClR strobe. The
7-124

Raytheon Semiconductor

For More Information calI1-80D-722-7074.

TP-47B
COll flag is used only in overlay mode (for MONG). It indicates that the source image region
(defined by SVAl X and Y) and the overlay region (defined by TVY) are at least partially
coincident on the screen. This is used by MONG to determine when the image hits the paddle.
Seasoned MONG players will note that it is possible for the image to take a quantum jump
through the paddle without a hit being detected. COll is cleared the same way VFlG is cleared.
Each TMC2302 generates an independent target region valid signal (TVAl). Sync generally is
the compliment of the TVAl signal from the X TMC2302, while blank generally comes from the
compliment of the TV Al signal from the Y TMC2302. Blank is also used to blank the screen
beyond the edge of the source image.

For More Information call 1-800-722-7074.

Raytheon Semiconductor

7-125

TP-47B
Listing for Decode PAL
MODULEtrw2
TITLE 'TRW TMC2302P5C Decode PAL, B-bit version'
trwu1 device 'P20LB';
A9,AB,A7,A6,A5,A4,A3,A2,A 1,AO
AEN,1I0W,1I0R
pin 14,2,1;
ENAB
pin 20;
DNWR
pin 23;
!MORE,!PWR,!PRD,!RAMDAT pin 16,22,15,21;
!DEN,!VCLR,!STATUS
pin 19,1B,17;
HADDR =[A9,AB,A7,A6,A5,A4,A3,.x.,.x.,.x.];
ADDR = [A9,AB,A7,A6,A5,A4,A3,A2,A1,AOJ;
PADDR ~[A4,.x.,A2,A1,A01;
@radix 16;

pin 13,11,1 O,9,B,7,6,5,4,3;
"PC bus control lines
"high for PC bus, low for parallel port
operation
"status bit, active for image download writes
"decode outputs
" more decode outputs
"PC bus high address
"PC bus address
"Parallel port address

EQUATIONS
PWR =
(HADDR == 310) & !AEN & lOW & ENAB
"310 - 317 Write
# A4 & !AEN & lOW & !ENAB;
"parallel port Write
PRO =
(HAD DR == 310) & !AEN & lOR & ENAB
"310 - 317 Read
# A4 & !AEN & lOR & !ENAB;
"parallel port Read
MORE = (HADDR == 300) & !AEN & lOW & ENAB
"300 - 307 Write to 2nd decode
# !A4 & !AEN & lOW & !ENAB;
"parallel port Write
RAMDAT =(ADDR == 304) & lOR & !DNWR & !AEN & ENAB "Image RAM Read
# (ADDR == 304)& lOW & DNWR & !AEN & ENAl3lmage RAM Write
# (PADDR == 4) & lOR & !DNWR & !AEN & !ENAB'paraliel port Read
# (PADDR == 4) & lOW & DNWR & !AEN & !ENAB'parallel port Write
VCLR =
(ADDR == 302) & lOR & !AEN & ENAB
"Read to 302 clears the Vert Flag
# (PADDR'== 2) & lOR & !AEN & !ENAB;
"parallel port Read
STATUS =(ADDR == 300) & lOR & !AEN & ENAB
"Read to 300 returns status
# (PADDR == 0) & lOR & !AEN & !ENAB;
"parallel port Read
DEN =
(HADDR == 300) & lOR & !AEN & ENAB
"Enable data to PC bus
# (HADDR == 310) & lOR & !AEN & ENAB
"Enable RAMDAC data to PC bus
# lOW & !IOR
"lOR inactive term to prevent
parallel port fight
# AEN & liaR;
"default - enable bus to prevent
float
END trw2

7-126

Raytheon Semiconductor

For More Information call HI00·722·7074.

TP-47B
Listing for Sync PAL

MODULE trw1 FLAG '-r2'
TITLE 'TRW TMC2302P5C Sync PAL'
trw2 device 'P20R6';
ClK
IOE
ISVAlX
ISVAlY
ITVY

pin
pin
pin
pin
pin

1;
13;
2;
3;
4;

WRAPSRC
XDONE
INIT
ENDDX
ENDDY
IVClR
OVlMODE
IBLANK
VFlG
IVCNT2
IVCNT1
INITD
COll
VSYNC
OlO

pin 5;
pin 6;
pin 7;
pin 8;
pin 9;
pin 10;
pin 11;
pin 15;
pin 16;
pin 17;
pin 18;
pin 19;
pin 20;
pin 21;
pin 22;

"Video dot clock
"Output enable
"Source Image Address Valid in X dimension
"Source Image Address Valid in Y dimension
"Target Address Valid from Y 2302 (indicates active" video screen
region [versus blanking region])
"Wrap the source image by ignoring SVAlX and SVAlY
"Done from X 2302 - sets VFlG
"Init from control register
"ENDD from X 2302, pulses during H-sync
"ENDD from Y 2302, active for last line
"Vertical Flag Clear
"Overlay Mode bit from Control Register
"Video Blanking signal
"Vertical Flag to status register
"Counter bit 2 for VGA vertical sync
"Counter bit 1 for VGA vertical sync
"Resynchronized Init to 2302's
"Collision Flag to status reister (for Overlay Mode)
"VGA Vertical Sync
"Overlay bit 0 to DAC

EQUATIONS
IBLANK = SVAlX & SVAlY & TVY
"don't blank when source valid (& on screen)
# WRAPSRC & TVY
"don't blank when Wrap Source mode set
# OVlMODE & SVAlX & SVAlY "don't blank source when in overlay mode
# OVlMODE & TVY;
"don't blank for overlay region
VCNT1 := ENDDY
"start VGA Vertical sync
# VCNT1 & IENDDX;
"and hold for next horizontal line
VCNT2:= VCNT1 & ENDDX;
"hold Vertical sync for all of second line
OlO =
TVY & OVlMODE;
"in overlay mode, TVY indicates the overlay region
COll:= TVY & SVAlX & SV AlY
"set overlay mode collision - image & overlay hit
# COll & IVClR;
"hold collision until Vertical Clear command
INITD:= INIT;
"synchronize INIT into 2302's
IV SYNC :=VCNT1 # VCNT2;
"VGA Vertical sync
VFlG:= XDONE & IVClR
"set Vertical Flag - end of 2302 screen refresh
sequence
# VFlG & IVClR;
"hold Vertical Flag until Vertical Clear command
END trw1;

For More Information call 1-800-722-7074.

Raytheon Semiconductor

7-127

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1'100
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9
10

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18
17
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15
13
12

11

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CY7C185
07
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05
04
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02
01
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19
18
17

3
12
11

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1'103
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1'10
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YA
YA0

07
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05
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1'100

19
18

17
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1
13
12
11

6 A4

7
8
9
10

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1'12
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1'10
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MEMS-3A

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7
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MSEL4

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07
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05
04
03
02
01
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U17
CY7C185

VAS

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CY7C185

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XA5
XA4
XA3
XA2
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1'101
1'100

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All
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1'19
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A7
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A3
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21
20
19
18
17
15
14
13

2
23
21
24
25

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05
04
03
02
01
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lAOR1
IAOR0
07
06
05

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C7
87
A8
8S
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lA6 TMC2302SA23 86
lAS U21
SA22 C6
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SA21 AS
lA3
SA20 85
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SA17 A3
SA16 A2
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107
106
105
10'"
103
102
101
100

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SA6
SA5
SA'"
SA3
SA2
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SA0

F2
Fl
Gl
Hl
H2
Jl
J2
Kl
K2

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UP1~

INlT
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KA7
KA6
KAS
KM
KA3
KA2
KAl
KA0

N2
M3
N3
M4
N4
M5
N5
L6

1013

SA 13

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1010

SA 10

UP2~ NOOP

CLOCK~

CLK

01

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lAOR~

lAOR3
lAOR2
lAORl
lAOR0

XA9
XAS
XA7
XA6
XA5
XM
XA3
XA2
XAl
XA0

07
06
05
04
03
02
01
00
107
106
105
104
103
102
101
100

XSA3
XSA2
XSAl
XSA0

lAOR7

U10
74HCT04
5
6

XKA3
XKA2
XKA1
XKA0

A10
C9
810
All
811
C10
A12
812
813
C13
12
013
E12
E13
F13
G13

1015
1014

X CHIP

c

120 PIN
PLASTIC
PGA
NUMERIC

PIN .'5

TA10
TA9
TAS
TA7
TA6
TA5
TM
TA3
TA2
TAl
TA0

N11
M10
L9
N10
M9
N9
LS
MS
NS
N7
M7

ig~~

~:~~
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SA10
SA9
SAS
SA?
SA6
SAS

ig!

IWR
89 lCS

INITO~
UP1~
UP2~

NOOP

CLOCK~

CLK

INlT
SYNC

ACC Ml
ENOO N 13

XACC
ENOOX

OONE

XOONE

~~0

~I~lrW
PGA

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~SUALX* TUX*11 ~
H6

ONLOAO--.--J

Y CHIP

XTA3
XTA2
XTAI
XTA0

XTRW*

SYNC*

SA15 ~~
SAH Cl

1011
1010
IDS
lOS
IO?
ID6
105
104
103
102

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XPROBE

XPRQ8E

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lAS U22
SA22 C6
lA~
SA21 AS
lA3
SA20 85
lA2
SA19 C5
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SA1S 8~
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SA17 A3
SA16 A2

TAll N12

c.

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811
C10
A12
812
813
C13
012
013
E12
E13
F13
G13

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03
02
01
00
107
106
105
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103
102
101
ID0

3

g

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C7
87
A8
8S
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A9

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lAOR5

02

g~

El
F2
F1
Gl
H1
H2
SA~ J1
SA3 J2
SA2 K1

~~!

K2

KA7
KA6
KA5
KM
KA3
KA2
KAl
KA0

N2
M3
N3
M4
N4
M5
N5
L6

TAll
TA10
TA9
TAS
TA7
TA6
TAS
TM
TA3
TA2
TAl
TA0
Ace

NUMER I C

ENDO

PIN . ' 5

OONE
SUAL
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TP-47B
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For More Infonnation caJI1-800-722-7074.

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lVll~IO G

Raytheon Semiconductor

7-133

TP-47B
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7-134

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Raytheon Semiconductor

For Moralnfonnation call 1-800-722-7074.

TP-47B

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Raytheon Semiconductor

7-135

TP-47B
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7-136

•
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°e

•
•

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

TP-49B

TMC2242 Topics: Operation with 8-bit I/O,
Comparing with Analog Anti-Aliasing Filters and 3 dB
Better SNR Through Oversampling

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

7-137

TP-49B
TMC2242 Topics:
I.
Operation with a-bit I/O
II. Comparing with analog anti-aliasing
filters
III. 3dB Better SNR Through
Oversampling
The TMC2242 is a video-speed half-band antialiasing digital filter. It accepts 12-bit parallel input
data and delivers 16 bits of parallel data. Its
decimation mode is particularly useful for filtering
data from analog-to-digital (AID) converters, while
its interpolation mode filters data prior to digital-toanalog (O/A) conversion. The TMC2242 greatly

simplifies analog pre- or post-filters. In decimation
mode, the output data rate is 112 the input data
rate. In interpolation mode, the output data rate is
twice the input data rate. The TMC2242's third
mode, 1:1 filtering, is used for general purpose
fixed-coefficient digital filtering.

Figure 1. Connecting the TMC2242 for 8-blt 2's complement format.

7-138

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TP-49B
There are many possible connection methods (bit
weight assignments) for applications where fewer
than the full 12 input bits are used. Recommended
connections for 8-bit applications are shown in
Figures 1 through 12. For higher resolution inputs,
expand data input and output connections in the
direction of the LSBs, keeping MSB connections as
shown.
Internal Limiting
The TMC2242's limiter restricts its output
magnitude to 7FFFh (most positive) and 8000h
(most negative) in two's complement output format
(TCO = HIGH). In unsigned magnitude output
format (TCO = LOW), the output magnitude is
limited to OOOOh (most positive) and FFFFh (most
negative). This limiting is not performed in the
interpolation mode where the "gain" of the
TMC2242 is approximately 0.5. In low input
resolution applications «12 bits), the full output
range of the TMC2242 is not used and the on-chip
limiting may not be effective.
Prevention of Overflow and Underflow
Sharp-cutoff analog and digital filters may exhibit

minor overshoot and undershoot when driven with
sharp step inputs. The output excursions of these
filters will be greater than the peak-to-peak input
signal excursion for full-scale input step transitions.
Whereas analog filters usually have ample signal
headroom for overshoot and undershoot transients,
digital filters have a limited and well-defined output
range and may clip when asked to filter full-scale
input transients. The TMC2242 provides the extra
output word width (16 bits) required to
accommodate this potential signal growth.
If sharp, full-scale input transitions are anticipated,
and the system cannot accommodate the extra
dynamic range provided by the TMC2242 (as
applied in an 8-bit system, for instance) then the
input range should be limited slightly to prevent
undesired overflow and underflow.
Tables 2 suggests input value limits for this kind of
application. It applies for all input and output
formats, however attention must be paid to the
difference between the bit assignments of the
TMC2242 and bit weighting of the system. The
actual limiting values required in any particular
application will vary according to the nature of
expected signals and system configuration.

Table 1. Effect of on-chlp IImltlng,ln 8-blt applications

Mode

Output
Format

Is on-chip
limiting
effective?

comp
comp
comp
comp

decimate
1:1 filter
interpolate
interpolate

2's
2's
2's
inv

comp
comp
comp
2's comp

yes
yes
no
no

2's comp
2's comp
2's comp

decimate
1:1 filter
interpolate

inv uns mag
inv uns mag
inv uns mag

yes
yes
no

9

uns mag
uns mag
uns mag

decimate
1:1 filter
interpolate

uns mag
uns mag
uns mag

no
no
no

10
11
12

uns mag
uns mag
uns mag

decimate
1:1 filter
interpolate

inv uns mag
inv uns mag
inv uns mag

no
no
no

Figure

Input
Format

1
2
3
3a

2's
2's
2's
2's

4

5
6
7
8

For More Information calI1.aoo-722-7074.

Raytheon Semiconductor

7-139

TP-49B
Table 2. Suggested limits for 12-blt formats

Mode

S1 11 -0 limit values
for unsigned magnitude
Min
Max

S1 11 -0 limit values
for 2's complement
Min
Max

decimate
1:1 filter
interpolate
If less than 12 bits of input data are used in
applications involving fast full-scale transitions, the
input value must remain within these values. Table
3 suggests limiting values for 8-bit input data
connected to Sl ll -4 for two's complement format
(Figures 1 through 6) and connected to S1 10-3 for
unsigned magnitude format (Figures 7 through 12).
Unless shown otherwise, unused input pins are

connected to ground. Note that the connection of
system data to S1 11 -0 depends upon the
application, mode, and particular data format used.
In Figures 3, 3a, 7, 8, 9,10,11 and 12, the unused
MSBs of the TMC2242 (S015 and, in some cases,
S014) may be used to indicate out-of-range
conditions.

Table 3. Suggested Input limits for 8-blt applications having sharp step Inputs

Mode

Output
Format

Limit values
for 8-bit data
Min
Max

2'scomp
2's comp
2's comp
2's comp

decimate
1:1 filter
interpolate
interpolate

2's comp
2's comp
2's comp
inv 2's comp

8Fh
8Fh
9Bh
9Bh

70h
70h
64 h
64h

6

2',s comp
2's comp
2's comp

decimate
1:1 filter
interpolate

inv uns mag
inv uns mag
inv uns mag

8Fh
8Fh
9Bh

70 h
70 h
64h

7
8
9

uns mag
uns mag
uns mag

decimate
1:1 filter
interpolate

uns mag
uns mag
uns mag-

10h
10h
1Bh

EFh
EFh
E4h

10
11
12

uns mag
uns mag
uns mag

decimate
1:1 filter
interpolate

inv uns mag
inv uns mag
Inv uns mag

10h
10h
1Bh

EFh
EFh
E4h

Figure

Input
Format

1
2
3
3a
4

5

7-140

Raytheon Semiconductor

For More Information, calI1-80Q-722-7074.

TP-49B
Full-Scale Sinewave Inputs
Filter coefficients were chosen to give an optimum
filter shape, but yield a gain slightly above unity for
1:1 filtering and decimation, and 0.5 for
interpolation. This extra gain is less than 0.03dB
worst case. If pure full-scale sinewaves are
expected, the input level will need to be reduced
slightly. A gain of 0.03dB corresponds to three
additional LSB-weights referred to full-scale in a
12-bit system, less than one LSB in a 10-bit
system, and less than 1/4 LSB in an 8-bit system.
In 8-bit applications the 0.03dB gain is therefore
usually ignored. This additional gain contributes no
linearity error or distortion, and the full input range
may be used without fear of undershoot or
overshoot.
Rounding
The TMC2242 has internal rounding circuitry which
allows the output to be rounded to any of eight

selectable precisions. Rounding is accomplished
by adding an offset of 1/2 LSB to the digital result
and then truncating. The RND 2-O inputs select
which of SOO.7 is the system LSB. Setting RND 2-O
= 111 selects S07' and RND 2_0 = 000 selects SOo.
If SOx is the system LSB, then set RND2 -O = x.
These selections apply to Figures 3, 3a, 6, 7, 8, 9,
10,11 and 12.
Figures 1, 2, 4, and 5 use SOs as the LSB.
Additional offset is required for correct rounding in
applications where one of S015-S is the LSB. in
this case, an input is tied HIGH to add the
additional offset that, when combined with the
selected rounding bits of the TMC2242, results in a
total offset of 1/2 LSB. In Figures 1,2,3, and 5,
the internal rounding adds 1/4 LSB and input SI 2 is
tied HIGH to add another 1/4 LSB for a total of 112
LSB, all referred to SOs. It is less correct to set
input bit SI3 HIGH to provide all of the required 1/2
LSB because setting RND 2-O = 000 selects SOo as
the LSB which will add an additional undesired
1/512 LSB offset.
Figure 3.

5°15
5°14
5°13
5°12
5°11
5°10
TMC2242 509
508
5°7
506
505

8·BIT
INPUT
FROM
SYSTEM
+5V
11<.0

2 TCO

5°4
503
5°2
5°1
500

4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21

8-BIT
OUTPUT
TO
SYSTEM
LSB
NC
NC
NC
Ne
NC
NC
NC

2242.3a.APP

Note: 1. Sign extension, .. MSB/SIGN during overflow or underflow.

For More Information call

1-800·722·7074.

Raytheon Semiconductor

7·141

TP·49B
Figure 4.

Figure 3a.

8·BIT
INPUT
FROM
SYSTEM
+5V

lk!l

40
5111
37
51,0
36
519
35
51
34 8
517
33
51 6
32
515 TMC2242
31
51
30 4
513
27
512
26 51,
25
510
1
DEC
44
INT
2
TCO

5°'5
5°'4
5°'3
5°'2
5°11
5°'0
509
508
S~
506
505
5°4
503
5°2
5o,
500

4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21

8·BIT
OUTPUT
TO
SYSTEM

5°'5
5°'4
5°'3
5°'2
5°11
5°'0
TMC2242 509
508
5°7
506
505

8·BIT
INPUT
FROM
SYSTEM
+5V

LSB

lk!l

NC
NC
NC
NC
NC
NC
NC

5°4
503
5°2
5o,
500

2 TCO

4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21

8·BIT
OUTPUT
TO
SYSTEM
LSB
NC
NC
NC
NC
NC
NC
NC
NC

RND2 RND, RNDO

RND2 RND, RNDo

22

22

2242.4.APP

2242.3b.APP

Note: 1. Sign extension - MSB/SIGN during overflow or underflow.

Figure 6.

Figure 5.

8·BIT
INPUT
FROM
SYSTEM
+5V

lk!l

40
51"
37
51 ,0
36
Sig
35
51
34 8
517
33
516
32
515 TMC2242
31
514
30
513
27
512
26 51,
25
510
1
DEC
44
INT
2 TCO

5°'5
5°'4
5°'3
5°'2
5°11
5°'0
509
508
S~
506
5°5
5°4
503
5°2
5o,
50 0

4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21

8·BIT
OUTPUT
TO
SYSTEM

8·BIT
INPUT
FROM
SYSTEM
+5V

NC
NC
NC
NC
NC
NC
NC
NC

lk!l

2 TCO

5°4
503
5°2
5o,
500

4
MSB/51GN
5 NC
6
8-BIT
7
OOTPUT
8
TO
SYSTEM
9
10
11
14
15 NC
16 NC
17
NC
18 NC
19
Ne
20
NC
21 NC

RND2 RND, RNDO

RND2 RND, RNDO

22

22
2242.5.APP

7·142

5°'5
5°'4
5°'3
5°'2
5°11
5°'0
TMC2242 509
508
5~
506
505

Raytheon Semiconductor

2242.S.APP

For More Information call 1-800·722·7074.

TP-49B
Figure 8.

Figure 7.
40
37
36
3
34
33
32
31
30

S-BIT
INPUT
FROM
SYSTEM
+5V

27

1k.O

26
25
1

51
"
51 ,0
519
SiS
517
SI6
TMC2242
515
SI4
SI3
SI2
SI,
510
DEC

5015
5°'4
50,3
5°12
5°11
5°'0
S09
SOs

44

INT
2 Teo

S~

S06
S05
S04
S03
S02
SO,
SOO

4
5
6
7
S
9
10
11
14
15
16
17
1S
19
20
21

40

S·BIT
OUTPUT
TO
SYSTEM

S·BIT
INPUT
FROM
SYSTEM
+5V

NC
NC
NC
NC
NC
NC
NC

1k.O

51,1

5°'5
5°'4
37
51 ,0
5013
36
519
5°'2
35
Sis
5°11
34
5~
5°'0
33
Sis TMC2242 S09
32
SiS
SOs
31
SI4
5~
30
513
S06
27
SI2
SOS
26 51,
S04
25
Sio
S03
1
DEC
S02
44
INT
SO,
SOO
2 TCO

RND2 RND, RNDO

4
5
6
7
S
9
10
11
14
15
16
17
1S
19
20
21

22
2242.7.APP

1. HIGH

during overflow or underflow.

2242.8.APP

Note: 1.

HIGH

during overflow or underflow.

Figure 10.

Figure 9.
40

M5B/51GN
S-BIT
INPUT
FROM
SYSTEM
+5V
LSB
1k.O

SO,5
SO,4
37
51 ,0
5°13
36
519
5°'2
3
Sis
5°11
34
51
50 ,0
33 7
51 6 TMC2242 50
9
32
515
50S
31
SI4
S~
30
SI3
S06
27
SI2
SOS
26
SI,
S04
25
SIO
5°3
1
DEC
S02
44
INT
SO,
51,1

2 TCO

500

4
5
6
7
S
9
10
11
14
15
16
17
18
19
20
21

40

NC1
NC2
M5B/SIGN
S·BIT
OUTPUT
TO
SYSTEM

S-BIT
INPUT
FROM
SYSTEM
+5V
1k.O

NC
NC
NC
NC
NC.

1. HIGH during
2. HIG H during

22
underflow.
overflow or underflow.

For More Information call 1-800-722·7074.

SO,5
SO,4
37
SI'0
SO,3
36
519
S012
35
SiS
5o"
34
S~
5010
33
51 6 TMC2242 S09
32
515
S08
31
SI4
S~
30
SI3
S06
27
SI2
S05
26
SI,
S04
25
Sio
S03
1
DEC
S02
44
INT
S01
2
TCO
SOO
SI'1

4
5
6
7
S
9
10
11
14
15
16
17
18
19
20
21

8-BIT
OUTPUT
TO
SYSTEM

NC
NC
NC
NC
NC
NC

RND2 RND1 RNDO

RND2 RND1 RNDO
Note:

NC
NC
NC
NC
NC

RND2 RND, RNDO

22
Note:

S-BIT
OUTPUT
TO
SYSTEM

22
2242.9.APP

2242.1 a.A?p

Note:

1. HIGH

Raytheon Semiconductor

during overflow or underflow.

7·143

TP-49B
Figure 11.

Figure 12.

S015
S014
S013
S012
S011
S010

8-BIT
INPUT
FROM
SYSTEM

TMC2242

+5V

1kO

S09
S08
S~
S06
S05
S04
S03
S02
S01
SOo

4
5
6
7

40 SI11

a-BIT
OUTPUT
TO
SYSTEM

a
9

~~

14
15
16
17
18
19
20
21

8-BIT
INPUT
FROM
SYSTEM

S015
S014
S013
S012
S011
S010
TMC2242 S09
SOa

S~

+5V
NC
NC
NC
NC
NC
NC
NC

S06
S05
S04
S03
S02
S01
SOo

1kO

4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21

NC1
NC2
MSB(SIGN
8-BIT
OUTPUT
TO
SYSTEM

NC
NC
NC
NC
NC
NC

RND2 RND1 RNDo

22
2242.11.APP

2242.12.APP

Note: 1. HIGH during underflow.
2. HIGH during overflow or underflow.

Note: 1. HIGH during overflow or underflow.

Table 4. Summary of connections shown In Figures 1 through 12.
Input
Figure Format

Mode

Output
Format

Input
Pins

SI 2
Pin

Output
Pins

DEC\ INn

TCO

RNDo

1
2
3
3a

2'scomp
2's comp
2's comp
2'scomp

decimate
1:1 filter
interpolate
interpolate

2's comp
2's comp
2's comp
inv 2's comp

S1 11 -4
S1 11 -4
S1 11 -4
S1 11 -4

HIGH
HIGH
LOW
LOW

SOlS-8
SOlS-8
S014-7
S014-7

LOW
LOW
HIGH
HIGH

HIGH
HIGH
HIGH
LOW

HIGH
HIGH
HIGH
HIGH

4
5
6

2's comp decimate
2's comp 1:1 filter
2's comp interpolate

inv uns mag
inv uns mag
inv uns mag

S1 11 -4
S1 11 -4
S1 11 -4

7

9

uns mag
uns mag
uns mag

decimate
1:1 filter
interpolate

uns mag
uns mag
uns mag

S1 1O-3
S1 1O-3
S1 1O-3

HIGH SOl 5-8 LOW
HIGH SOlS-8 LOW
LOW SOlS-7' HIGH
S014=NC
LOW S014-7 LOW
LOW S014-7 LOW
LOW S013-6 HIGH

10
11
12

uns mag
uns mag
uns mag

decimate
1:1 filter
interpolate

inv uns mag
inv uns mag
inv uns mag

S1 1O -3
S1 1O-3
S1 1O-3

LOW S014-7
LOW S014-7
LOW S013-6

8

HIGH
LOW
LOW
LOW

HIGH LOW HIGH
LOW LOW HIGH
LOW LOW HIGH
HIGH HIGH HIGH
LOW HIGH HIGH
LOW HIGH LOW

LOW HIGH LOW HIGH
LOW LOW LOW HIGH
HIGH LOW LOW LOW

Notes: 1. For unsigned magnitude input format, SI 11 =LOW
2. In all cases, RNDl and RND2 = LOW.

7-144

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TP-49B
II.

Comparing with analog anti-aliasing
filters

When a signal is sampled periodically. the
frequency spectrum of that signal is "folded" in
such a way as to superimpose frequencies in the
primary band of DC to 1/2 the sampling rate with
frequencies outside of that band. This effect is
commonly called aliasing. To avoid having this
effect destroy (by superimposing high frequency
noise on the lower frequency signal) information of
interest. an anti-aliasing filter must be used to
remove the energy above fJ2 from the Signal
before it is sampled.
Due to aliasing. the sampling rate must be at least
twice the signal bandwidth. To account for real
world filters. there must be ample headroom for the
"skirts" of the anti-aliasing filter. When sampling a
signal such as a video signal, the sampling rate
chosen (often 4x the NTSC color subcarrier
frequency) and the signal bandwidth define the
anti-aliasing filter required. If. for example, the
signal band is DC to 6 MHz. then the filter must
pass DC to 6 MHz and attenuate 7.16 MHz (1/4
octave transition band) by 48 dB. Since realization
of such a filter is very difficult. compromises are
sometimes made in the Signal bandwidth. or the
amount of attenuation. or both.
An alternative is to increase the sample rate. If the
sample rate is increased to 8x the NTSC color
subcarrier frequency, then the stopband need not
commence until 14.32 MHz. allowing 1.25 Octaves
for the filter to transition from passband to
stopband. The disadvantage of this is that the
amount of data being generated has doubled. even
though the information content has stayed the
same.
A solution is to sample at a high rate with a simple
anti-aliaSing filter in front oft the NO converter.
Then digitally low-pass filter and decimate the data.
This avoids the need to store or process more data
than the information content of the signal would
warrant. This is the purpose of the TMC2242 halfband filter.
The TMC2242 is a digital low-pass filter which
For More Information call 1-800-722-7074.

passes frequencies from DC to 1/4 the sampling
rate. As a result of aliasing, only the frequency
spectrum from DC to 1/2 the sampling rate is
unique. Since the TMC2242 passes 1/2 of the
spectrum available to it, it is called a "half-band
filter." The signal is then decimated so that the
output data rate becomes 1/2 the input data rate.
The result is that the complexity of the anti-aliasing
filter has been significantly reduced at the expense
of having to sample the signal at twice the rate
needed, plus the addition of a digital
filter/decimator. It is reasonable to ask if this is a
good tradeoff.
One performance advantage of the TMC2242 over
the complex analog filter is that of group delay.
Group delay is a measure of the differential
propagation time of two sinewaves, of differing
frequencies, through a circuit. The result of poor
group delay is poor pulse response. The group
delay of the digital filter is ZERO.
The use of the FIR filter structure in the TMC2242
guarantees stability, and insensitivity to component
selection. The equivalent analog filter would
require several high precision components (L and
C), all matched precisely to achieve desired
performance. This matching must be maintained
over the operating temperature range for the
circuit. The result is usually an analog filter design
that requires hand tuning to achieve desired
performance, making the filter expensive to
manufacture. All TMC2242s have exactly the
same characteristics. over the entire guaranteed
temperature range, and the characteristics will not
change with age.
The reliability of systems employing the TMC2242
should be greatly improved since there will be a
greatly reduced component count.
The following pages show plots of the TMC2242,
the vertical axis is in dB and the horizontal axis is
frequency normalized so that the sampling rate is

1000.

Raytheon Semiconductor

7·145

TP-49B
Figure 13. TMC2242 Frequency Response Curves

G
A
I
N

d

B

10
0
-10
-2.0
-30
-40
-50
-60
-70
-80

.1-

'\

.1.1-

~

J

-I-I-

.1-

'1 "

.1-'-

o

I

•

I

I

I

100

200

In""

""

•

400

300

A

\n

~f1

~

500

Frequency (500=Nyquist)

0.1 - , . . - - - - - - - - - - - - - - - - - - - ,

G

A
I
N

0.0 + - - - - - - - - - - - - - - - - - - ; r - - - - - 1

d

B

-0.1 4-f-4-t-+-lr-++-H--i--H-f--HH-+--t-+-t--t-t-'-t--+-I
250
o
100
150
200
50

Frequency (500=Nyquist)

7-146

Raytheon Semiconductor

For More Information calIHIOO-722-7074.

TP-49B
III.

3dB Better SNR Through
Oversampling

By operating an NO converter at rates above the
minimum required to meet the Nyquist criterion, it is
possible to reduce quantization noise. Filtering and
decimation return the original data bandwidth, but
with improved SNR.

The TMC2242 is a half-band deCimating filter. The
input signal is low pass filtered, passing only the
OC to fs/4 band. The output is decimated so that
the output data rate is 112 the input data rate. The
primary reason for using the TMC2242 is to simplify
the requirements imposed upon anti-aliasing filters
which are normally placed just ahead of ND
converters. One beneficial side effect of using the
TMC2242 is that by oversampling, the signal-toquantizing noise ratio is increased by 3dB for each
octave of oversampling. The result of using a
TMC2242 after a 9-bit NO converter (Le.
TOC1049) sampling at 8x the NTSC color
subcarrier frequency is an equivalent 4x subcarrier
sampling rate where the resolution of the output
signal is 9.5 bits.
To explain where the additional 1/2 bit comes from,
the digitizing process must be modeled. If the input
to the NO converter is a signal, f(t), and the
digitized output of the signal is fd(t), then the
digitization can be thought of as simply adding
quantization noise of fd(t)-f(t). This difference

For More Information call 1-800-722-7074.

signal is called £(t). Therefore fd(t)=f(t)+£(t). £(t) is
the noise that is not wanted since it represents the
error in the sample.
The probability density function of £(t) is close to
that of white noise for most real Signals. Its value
is equally likely to fall between +1/20 and -1/20
where 0 is a quantization step. If sampling is done
at twice the required rate, followed by decimation,
the noise in the decimated signal will be the sum of
the two £(t)s. The expected value of the sum of
two variables equally distributed over a range of
± 1120 is ±"2/2 0, hence the noise has increased by
a factor of "2. In the mean time, the signal, having
been sampled twice, has increased in value by a
factor of 2. Since the signal strength grows more
rapidly than the noise, there is an improvement in
SNR by a factor of 21"2 (3dB) for each octave of
oversampling.
Another way of looking at the process is in the
frequency domain. The spectrum of £(t) is white
and therefore its energy is equally distributed
across the frequency band for DC to f5/2. The halfband filter acts equally on the noise and the signal.
Since the signal falls entirely within the passband, it
is entirely passed. The noise, being evenly
distributed, is cut in half, increasing the signal-tonoise ratio by 3dB.

Raytheon Semiconductor

7-147

TP-49B

7-148

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

TP-SOA

The Evaluation Board for the TMCl17SffnC3310

For More Information, calI1-80D-722-7074.

Raytheon Semiconductor

7-149

TP-SOA

7-150

Raytheon Semiconductor

For Mora Information, calI1-SQO-722-7074.

TP-50A

Application Note TP-50A
The Evaluation Board for the
TMC1175ITDC3310
The TMC1175E1 C Evaluation Board brings all of the circuitry together for evaluating Raytheon's
TMC1175 CMOS NO converter and the TDC3310 10-bit D/A converter. The NO and D/A signal
paths are independent but easily configurable at the edge connector for reconstruction of NO
converter data with the D/A converter. Data is registered after the NO and before the D/A
converters. A common clock signal will drive both NO and D/A converters. NO and D/A
converters may also be clocked independantly via the edge connector.
The TMC1175E1 C is a simple two-layer printed circuit board with 100 x 160 millimeter Eurocard
dimensions. The component side of the board comprises mostly ground plane with only a few
interconnections. A double row 64-pin DIN male connector gives access to all power and digital
signals. Analog input and output signals are available from SMA connectors.
Variable voltage references are provided for the TMC1175 and TDC3310. Configurable input
and output wideband video amplifiers are provided for signal conditioning. Signal path offsets
may be adjusted at the input and output amplifiers.

Figure 1. Evaluation Board Block Diagram

NO OUT

27022A

For More Information call 1-800·722-7074.

Raytheon Semiconductor

7-151

TP-50A
Power Supply and Clock Input Requirements
Both the TMC1175 and TOC3310 require only +5 Volts for operation. The NO converter voltage
reference circuits and wideband amplifiers may be operated from voltages of ±5 to ±18 Volts.
A Clock Buffer circuit has been included on the board with a 500 terminated SMA input. The
.clock buffer circuit provides separate CONV signals to the NO and O/A converters and their
registers. Pull-up resistors on edge-connector ClK inputs enable the clock buffer when a
common clock is used. If separate clocks are desired, edge-connector pins B2 and B24 may be
used for the NO and O/A converters, respectively. The TOC331 0 clock input may be monitored
on test point TP1.

TMC1175 AID Converter Circuitry
The circuitry included on this evaluation board is not intended to represent the minimum design
for Nd operation. It is designed with maximum flexibility for evaluating the TMC1175 in various
configurations.
The input amplifier, U6, may be configured for inverting or non-inverting operation, with and
without variable offset voltage. R39 is the potentiometer used for varying the offset of the signal
applied to the NO converter. The output of the input amplifier is monitored at SMA A IN2· AIN2
may also be used as a signal input when AC-coupling to the NO converter is used. The 750
input termination resistor and voltage gain of this amplifier are jumper selectable. Fixed amplifier
gains of -4, -1, +2, and +5 are available.
AC- or DC-coupling directly to the TMC1175, is accomplished via input connector A IN2 . A "poor
man's" diode clamp limits the negative going AC-coupled signal to the NO converter to the
voltage applied to RT. The diode clamp and coupling method are jumper selectable. Silicon
diodes are included on the board to prevent voltage excursions on the input to the NO converter
from going beyond the power supply range.
Two variable voltage reference circuits are provided on the board for driving the RT and RB
inputs of the TMC1175. The NO reference voltage inputs may be jumper configured for the
internal reference divider of the TMC1175 using VR+ and VR_. Other jumper options connect RT
to Vee and RB to GNO. The reference inputs to the NO converter may be monitored on test
pOints TP5 and TP6.
Table 1 summarizes the function of each jumper and Table 2 indicates which jumpers are to be
installed and removed for amplifier configurations.

7-152

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TP-50A
Table 1. AID Converter Jumpers
J14
J15
J16
J17

Connects OFFSET control to inverting input of amplifier.
Grounds inverting input of amplifier for non-inverting operation.
Connects AIN1 to inverting amplifier input.
Enables 750 termination resistor on A IN1 .

J18
J19
J20
J21

Connects AIN1 to non-inverting amplifier input.
Connects OFFSET control to non-inverting input of amplifier.
Decreases feedback resistor of amplifier from 4.99kQ to 1.0kO.
Connects amplifier output to ND input.

J22
J23
J24
J25

D.C. couples amplifier output to ND input.
Enables 750 termination resistor on AIN2 .
Enables diode clamp.
Connects ND RT to VR+ pin.

J26
J27
J28
J29
J30

Connects ND
Connects ND
Connects ND
Connects ND
Connects ND

RT to Vcc.
RT to variable voltage reference.
RB to ground.
RB to V R_pin.
RB to variable voltage reference.

Table 2. Jumpers for AID Input Configurations

1

2
3
4

5

Configuration

Installed

Removed

Non-inverting, with offset control
Inverting, with offset control
Non-inverting, without offset control

J14
J16
J15

J18
J19
J18

J15
J14
J14

J16
J15
J16

AC-coupled direct input on AIN2
(with termination and clamp)
DC-coupled direct input on A ln2
(without termination and clamp)

J23

J24

j21

j22

J21

J23

For More Information caJI1-800-722-7074.

J22

Raytheon Semiconductor

J19
J18
J19

J24

7-153

TP-50A
TDC3310 D/A Converter Circuitry
The D/A converter circuitry included on the Evaluation Board is not intended to represent the
minimum design for D/A operation. It is designed with maximum flexibility for evaluating the
TDC3310 in configurations that work for various applications and implementations. Since the
TDC3310 is a 10-bit D/A converter, its two LSBs are jumpered to ground, enabling 8-bit
operation, matching the resolution of the TMC1175 ND converter. The INVERT input to the
TDC3310 is grounded by jumper J4.
A simple band-gap voltage reference and potentiometer R7 provide a variable reference to the
TDC3310. Varying R7 will change the "gain" of the TDC331 0 D/A converter. The reference is
set to -1.0 Volts with respect to the +5 Volt power supply as part of the factory test procedure.
The adjustment ranges from -0.4 to -1.2 Volts with respect to the +5 Volt power supply. The
TDC3310 reference voltage may be monitored on test point TP2.
AC- or DC-coupling directly from the TDC331 0 to the output amplifier is accomplished via jumper
J6. SMA connector AoUT1 can be used as a monitor point for the input to the output amplifier or
as an un-amplified D/A converter output. A "poor man's" diode clamp limits the negative going
AC-coupled signal from the D/A converter to GND. The diode clamp is jumper selectable.
The wideband video output amplifier, U5, may be configured for inverting (Av = -2) or noninverting (Av = +2) operation with variable offset voltage from R16. The amplifier has an output
series resistor of 75Q to ensure 1 Volt pk-pk video levels into 75Q terminated cables.
Since the output voltage frorTl the TDC3310 D/A converter if referred to the +5 Volt power supply,
the output amplifier may be configured as a differential amplifier with one input referred to the +5
Volt power supply. This configuration reduces the effect of common-mode noise from the power
supply at the input to the amplifier.
Table 3 summarizes the function of each jumper and Table 4 indicates which jumpers are to be
installed and removed for output amplifier configurations.

7-154

Raytheon Semiconductor

For More Information call 1-800-722-7074.

TP-50A
Table 3. D/A Converter Jumpers
J1
J2
J3
J4
J5

Enables 51 Q termination resistor on D/A CLK.
Grounds LSB of D/A converter for 8-bit operation.
Grounds 2nd LSB of D/A converter for 8-bit operation.
Grounds INVERT input to O/A.

J8

Enables 75Q termination resistor on AOUT1 connector.
D.C. couples output of D/A converter.
Enables diode clamp.
Connects inverting input of amplifier to Vee'

J9
J10
J11
J12
J13

Connects AC-coupled output of D/A to amplifier.
Grounds inverting input of amplifier.
Connects non-inverting input of amplifier to Vee'
Connects non-inverting input of amplifier to D/A output.
Connects non-inverting input of amplifier to ground.

J6
J7

Table 4. Jumpers for D/A Output Amplifier Configurations
Removed

Configuration Coupling Referred

Installed

3
4

Non-inverting
Inverting
Non-inverting
Inverting

AC
AC
DC
DC

GND
GND
GND
GND

J10
J9
J6
J6

J12
J13
J10 J12
J9 J13

J6
J6
J8
J8

J8
J8
J9
J10

J9
J10
J11
J11

J11 J13
J11 J12
J13
J12

5
6
7
8

Non-inverting
Inverting
Non-inverting
Inverting

AC
AC
DC
DC

Vee
Vee
Vee
Vee

J8
J9
J6
J6

J12
J11
J8 .J12
J9 J11

J6
J6
J9
J8

J9
J8
J10
J10

J10
J10
J11
J12

J11 J13
J12 J13
J13
J13

1
2

For More Information .caII1-800-722-7074.

Raytheon Semiconductor

7-155

TP-50A
The Edge Connector
The edge connector has been arranged to easily configure the board for reconstructing AID data
with the TDC331 0 D/A converter. A.lD data outputs are located exactly adjacent to D/A data
inputs on the edge connector. Simply shorting these edge connector pins together will enable
the direct transfer of data from one signal path to the other.

Table 5. Edge-connector Pin Assignments
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1

7-156

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D/A D1 MSB
D/A D2
D/A D3
GND
D/A D4
D/A D5
D/A D6
D/A D7
D/A D8
D/A D9
D/A D10 LSB
N/C
N/C
N/C
N/C
N/C
N/C
GND
GND
GND
GND

B32
B31
B30
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1

V- (-15V)
V+(+15V)
N/C
N/C
N/C
N/C
N/C
N/C
D/A CONY Input
N/C
N/C
AID D1 MSB
AID D2
AID D3
Vee (+5V)
AID D4
AID D5
AID D6
AID D7
AID D8 LSB
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
AID CONY Input
VEE' (-5.2V)

Raytheon Semiconductor

For More Information call 1-800-722-7074.

-n

g
;;:
0
iil
SO"

"T1

to'
e:
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818

3t»

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~

~
~

~

CONY 12

111

10

8

9

13

°7 MS8
CIS
l00PF~

8
7

:D

CD

:::s

fC

R39,2KAJD
OFFSET AOJ

.~

°4

U9

03

Dl
DOlS8

g'
c

TMC1175

D2

3

g,

821
12

°6
Os

io

(')

0

ClK

6
5

14
7 74AlS374
Ul0
4
17

IS
6

16

4

18

19

3

3

2

820

::s
<

(I)

....
"'I

(I)

"'I

819

en

817

:T

816

3

(')

(I)

S»

815
814
813

::t.

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C

OJ'

(C

"'I

S»

3

R2B
lK

09
lN4148

1175.EBD

~
~

832)>-----..---1

•

til

~

'71

m
Application Notes

";'I

."

en

cC'
e
Cil

Q>

~

~

~

•

01

c ~
»
0
U9

lH

PIN 12,
UI8
PIN II

CIJ(

~AA.J\.

!

::r

8:::I
fe
3

n'
o

ac
...~

824)

1

1P1

~
-

,

A21'

e.

I
~

19 D, MS8
22

3

,

A20'
"

~

~
CD
~

en
(')
::I'
CD

3
D)

19

DDs

TDC3310

II

24 D&

U3

8

17

Z5 D7

9

1&

..!!

IS

11

14

&
7

A13'

¢ ¢
J21

74A1.S121
UI

D)

cc
~

22 D,

AI&'

g

B31

D)

1P3

COMP 7

Z1 ~

5

A17'
,

All

10 Dz

10

"

"

'REf &

Z1

A19'

f

f

I l1~I ~: lll~~ I
IflPI ~ I

::s

( ;'

AI4

g'

1J4

J,

AI5

~

I

0

3

I
'OUT

+

Aourz

~

1.1&

,o:T 1 :T
11

JIZ ,J11 , , ,

2& D8

27 119
ZI D'OLSB

1J3

Yr

U8.PlNI~U7,PlN3

R16,2K
DIA OffSET ADJ
3310,E80

TP-50A
Table 6. Parts List
Item Qty

PartNalue

Ref. Designator

Mfg. PIN

C1-C7, C9-C12, C14,
C16-C18, C21-C33
C8, C13, C1S, C19

MD01SC104KAB, AVX

1

29

Ceramic capacitor, 0.1 JlF

2

4

Tantalum capacitor, 100 JlF

3
4
S
6

2
1
4
17

Resistor, 200
Resistor, SUO
Resistor,7S0
Resistor, 1.0kO

7
8
9
10
11
12
13

1
2
1
1
4
1
4

Resistor, 1.33kO
Resistor, 2.0kO
Resistor, 3.0kQ
Resistor, 4.0kO
Resistor,4.7kO
Potintiometer, 2kO
Potentiometer, 2kO

R13,R22
R1
R9, R17,R18,R23
R6, R10, R12, R14
R19, R24-R31,
R33-R36
R20
R11, R1S
R8
R21
R2-RS
R7
R16,R26,R32, R39

14

10

Silicon Diode

D1-D10

1N4148

15
16
17

1
1
1

10-bit register
Quad 2-input NAND gate
10-bit D/A Converter

U1
U2
U3

18
19
20

1
2
2

1.2 Volt bandgap diode
Wide band op-amp
Voltage reference, op-amp

U40
U5,U6
U7,U8

21

1

8-bit ND Converter

U9

22

1

8-bit register

U10

74ALS821
74LS132
TDC3310N6C, Raytheon
Semiconductor
LM38S-1.2
EL2041 , Elantec
LM611, National
Semiconductor
TMC1175N2C30, Raytheon
Semiconductor
74ALS374

For More Information call 1-800-722-7074.

Raytheon Semiconductor

TAP107K03SSCS,AVX
RNSOC20ROF
RNSOCS1ROF
RNSOC7SROF
RNSOC1001F

RNSOC1331F
RNSOC2001F
RNSOC3001F
RNSOC4001F
RNSOD4701F

7-159

TP-SOA
Figure 4. PC Board Circuit-Side Layout

Figure 5. PC Board Component-Side Layout

o

-

•
•• 0 0 • ••.
••• •••
••
•
••
••
•
•
•• •••••
•• •••
••
•
••
•• ••
.000000
••
• ••
••
•
•
•
.000000
••
0 o·
••
::
0
:
:
•
•
••
•
•
•
0
:.0
000
o
:~ 0 . 0 :
:
•• 0
0 0
• • 0•• • ••o0 • ••• •••
•
.~ " - 0 0 .
•
.0. •
•
•
• 00.
•• •• • • • • o o
oo • •• _ .•
Y
••••
•••••••••• •
•
o 0
000
•
000
•
••
••
o 0 00 • • • ··1.~
00
••••
•• •• ••
•• ••
• • •• 00• • • 00.
•
•
••
••
••
•
•
00
••
••
•• •• ••
•
••
•
000 •
•
••
••
•• •• ••
•• •••
• • • 00 • • • • •
•
•
••
00
•
••
•
••
00
••
•• •• ••
••
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••
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00 • • • • • •
.
•
00
•• ••••
• 0..
00.
•
•o
o o. •• • ••

o

7-160

Raytheon Semiconductor

o

• • •• •
• • •• •
•••
• • •• •
•• • •
•
• • •• •

o

For More Infonnation call 1-800-722-7074.

TP-50A
Figure 6. PC Board Silkscreen Layout

o

'!:lID

TMCl175/TDC3310E1C

DIA CONVERTER
OHO aD§o,r-'--'

~ 'i3: DPOOT2 1''1••
o ~ -[!jfr~"""-"

UI

~~

.~~~!
TP6

'"

~

~

OHO~ rnu
AID CONVERTER

For More Information call 1-800·722·7074.

OAIN2

TP6

OAINI

~

"~l!:! _

.-

~

...

BOARD "11'1)(1'16971'1 REU.B

Raytheon Semiconductor

D~~~'
~ ..........
~~
~

A/Ro9~~fET

!~.... r;l Jm{: aID
[j {Il} RT ADJUST
~ OHO
cm:> C=::::B2E==~
ASSEMBLV "11'1)(1'16973 REU.

c::::J

7·161

TP-50A

7-162

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

TP-SIA

A Demonstration Board for the TMC22090 Digital
Video Encoder

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

7-163

TP-SIA

7-164

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

TP-51A

A Demonstration Board for the
TMC22090 Digital Video Encoder
Dean Raby
The TMC22061 P7C encoder demonstration board converts 8-bit digital component video, ( CCIR
rec 656 or SMPTE rp 125, a.k.a. "601") into analog composite video using the TMC22090 digital
video encoder. The board is dual standard and will operate in both PAL and NTSC television
standards.
A 27 MHz crystal oscillator is prqvided for cases where a CCIR-601 source is not available. In
such a case only the intemally generated color bars and modulated ramp can be produced.

Figure 1. Block diagram

+flV
ov
-5V

~

TJ
MHZ
XTAL

HEX SWITCH FOR
PATTERN SELECTION
HORIZONTAL AND
VERTICAL TIMING
GENERATION

TMC22090
PROGRAMMER

PAUNTSC SELECT
SOFTWARE RESET
S-VIDEO OUTPUT

TMC22090
DIGITAL
INPUT

601
INTERFACE

DIGITAL
VIDEO
ENCODER

CHROMINANCE OUTPUT
LUMINANCE OUTPUT
COM POSITE OUTPUT

28017"

For Mont Information call 1-800-722·7074.

Raytheon Semiconductor

7·165

TP-51A
CCIR-601lnterface
The CCIR-601 data stream is terminated into differential ECL-to,TIL converters. The translated data is latched
through U23 at a 27 MHz rate and then to a YC demultiplexer~' Here; the luminance and chrominance data words are
separated into two data streams termed Y and C, respectively. This YC data goes directly into the TMC22090 which
separates the color difference signals from the C data and interpolates the color difference signals to the same sample
rate as Y data. This interpolation improves the horizontal color transitions.
The TRS decoder decodes the field (F), vertical blanking (V), and horizontal blanking (H) information for use in the
timing signal generation on'the board. The TRS decoder also produces the pixel counter reset and the LDV signal for
latching the YC data into the TMC22090.

Horizontal and Vertical Timing
The pixel counter (U4, U5, and U1) is decoded to produce the VHSYNC\ and PDC signals required by the TMC22090
for horizontal synchronization. A 2x line rate clock, H/2_CLK, used in the VVSYNC\ generation, is also produced
along with P_CLOCK and DATA_EN. P_CLOCK is used to clock the program counters and the DATA_EN signal used
in the YC demultiplexing circuit.
A 4-bit counter embedded in U9 is started whenever V goes HIGH, which occurs at the beginning of each vertical
blanking interval. This counter is clocked by H/2_CLK which enables the VVSYNC\ pulse to be produced at the same
time as the first vertical sync pulse in each field. The PGM output signal ensures that the software reset signal,
RES_OUT, goes HIGH 15 half-line periods before the program counter starts.

Software Reset
A software reset occurs whenever the pushbutton switch, S3, is depressed. The software reset is latched through U9
to ensure a known relationship between the internal pixel clock of the TMC22090 and the externally generated LDV,
PDC, VHSYNC\, and VVSYNC\ signals. When S3 is depressed the internal state machines of the TMC22090 are
reset and the outputs are disabled. When S3 is released the program counter is started at the beginning of the next
vertical blanking period. Software Reset is required after power-up and after each functional change.

Programming the TMC22090
A 12-bit counter (U6, U7, and US) is used to produce the addresses used in programming the TMC22090. U11
produces the required R/W\, A1:o, and CS\ signals, while U12 contains 16 different pages of setup data for NTSC and
another 16 pages, for PAL (selected via switch S2). An additional 32 pages are unprogrammed, and available for user
setups. They are accessed by addressing the Upper Memory Blocks (UMB) via selector E7. To ensure that the
outputs of the programmable logic are correctly timed to transitions on the microprocessors data bus, they are
addressed at four times the rate that U12 is addressed. The 16 pages of setup data are selected by the rotary switch
S1, as shown in the table below.

7-166

Raytheon Semiconductor,

For More Information call 1-800-722-7074.

TP-51A
Table 1. Board Operational Setups.
Rotary
Switch
Position

o

Board Function

1
2
3

Color bars test signal (8-bars).
Color bars test signal (9-bars).
Modulated ramp test signal.
Encodes CCIR-601 input data (normal operation)

4
S
6
7

Subcarrier data limited to 28-bit resolution.
Subcarrier data limited to 24-bit resolution.
Luminance data limited to 6-bit resolution.
Chrominance data limited to 6-bit resolution.

8
9
A
B

Luminance and chrominance data limited to 6-bit resolution.
Inverted luminance data.
Inverted luminance data and 1800 phase shift to chrominance.
Chrominance data set to constant value in UV CLUTs.

C

Color burst phase advanced 10 degrees.
Color burst phase retarded 10 degrees.
Reduced active video line length.
Black burst (NTSC includes pedestal).

e

E
F

For More Infarmalion call 1-800-722-7~74.

Raytheon Semiconductor

7-167

TP-51A
Output Reconstruction Filters
The 2x oversampling of internal digital data before the output D/A converters of the TMC22090 not only reduces the
Sin(x)/x high-frequency roll-off but eliminates complicated reconstruction filters. This is particularly important as the
frequency response of digital filters is dependent upon the sample rate while the frequency of the aliased subcarrier
component is fixed. The filters are terminated on the board. If termination on the board is not required, simply remove
the appropriate link behind the BNC connector (E4, E5, E6).

Operation Without a CCIR-601 Source
Only rotary switch positions 0, 1, and 2 are useful without a CCIR-601 digital video source available. These switch
positions produce color bars and a modulated ramp These test patterns are inserted into the pixel data path after the
ClUTs in RGB format and demonstrate 90% of the circuitry of the TMC22090. To provide a PXCK in the absence of a
CCIR-601 source, switch E2 to internal.

Power Supply Requirements
The TMC22061 P7C board requires 1.25 Amps from the +5 Volt power supply and 0.25 Amps from the -5 Volt power
supply. The -5 Volt power supply powers ECl logic devices which have relatively good noise immunity. The +5 Volt
power supply not only drives TIL logic devices but it also provides the power to the TMC22090. Therefore, it is
recommended that a bench power supply is used with the cable lengths kept to a minimum. When operating in standalone mode, only +5 Volts is required.

On-Board Read-Only Memory
The table on the next page shows the content format of the EPROM which hold the 64 pages of setup data.

7-168

Raytheon Semiconductor

For Mora Information call 10800-722-7014.

TP-51A
Table 2. EPROM Address Map
Address

Contents

o
CLUT address pointer set to OOh
2

Start of CLUT data

Vn-1
Vn
Vn+1

769

End of CLUT data

770

Control Register pointer set to OOh

771

Start of Control Register data

851

End of Control Register data

852

Unused locations set to OOh

1023

Unused locations set to OOh

For More Infonnalion call 1-800-722-7074.

Raytheon Semiconductor

7-169

TP-51A
APPENDIX A. TMC22061 Parts List

Item Qty

Part/Value

Ref. Designator

PIN, Mfg. No.

1
2
2

2
3
3

Ferrite Beads
Inductors, 1.BIlH
Inductors, 1.01lH

L1, L2
L3,L5, L7
L4, L6,LB

2743001112, FAIR-RITE Prod. Corp.
IMS-2 1.BIlH +/- 5%, Dale
IMS-2 1.01lH +1- 5%, Dale

3

33

Ceramic capacitor, 0.1 IlF

MD015C104KAB, AVX

4
5
7
7

4
3
3
6

Ceramic capacitor, 0.01 IlF
Ceramic capacitor, 47 pF
Ceram ic capacitor, 100 pF
Ceramic capacitor, 330 pF

B
9

2
2

Tantalum capacitor, 0.471lF
Tantalum capacitor, 221lF

C3-C5, C9-C14, C43
C17-C20,C22-C39,C41
C1, C16, C40, C42
C57, C59, C61
C45,C49,C53
C44, C47, C4B, C51,
C52,C55
C2,C15
C7, CB

10
11
12
13
14
15
16
16A

9
9
1
1
1
1
1
1

Resistor, 75Q
Resistor, 120Q
Resistor, 412Q
Resistor, 3.3kQ
Resistor,4.7kQ
Resistor, 47kQ
SIP resistor, 3.3kQ
SIP resistor, 3.3kQ

R15-R20, R22-R24
R3, R5-R12
R14
R1, R13, R21
R2
R4
RN1
RN2

RN50C75ROF
RN50D1200F
RN50C4120F
RN50C3301F
RN50D4701F
RN50D4702F
430BR-1 01-332, Bourns
431 OR-1 01-332, Bourns

17
1B
1BA

1
1
2

1N414B Silicon Diode
LT1 004 Bandgap Reference
1N4004 Silicon Diode

CR1
CR2
CR3, CR4

1N414B
LT1 004-1.2, Linear Technology
1N4004, Motorola

19
20
21
22
23
24

1
2
2
1
3
1

TMC22090 Encoder
16RB PAL
20RB PAL
27512 Eprom
10125 ECL-TIL Translator
74F08 Quad 2-input AND

U1B
U9, U20
U10, U11
U12
U16,U19,U22
U13

TMC22090ROC, Raytheon Semiconductor.
TIBPAL16RB-15CN, Texas Inst.
TIBPAL20RB-15CNT, Texas Inst.
TMS27C512-120JL, Texas Insl.
MC10125P, Motorola
MC74F08N, Motorola or equiv.

7-170

Raytheon Semiconductor

MD015C103KAB, AVX
SR151A470JAA, AVX
SR151A101JAA, AVX
SR133A561JAA, AVX
TAP474K035SCS, AVX
TAP226K035SCS, AVX

For More Infonnation call 1-800-722-7074.

TP-51A
APPENDIX A. TMC22061 Parts List (continued)

Item Qty

Part/Value

Ref. Designator

PIN, Mfg. No.

25
26
27
28
29
30
31

1
3
3
1
2
1
2

74LS74 Dual D-type FF
74F163 4-bit counter
74LS163 4-bit counter
74F174 Hex D-type FF
74F374 Octal D-type FF
74HCT374 Octal D-type
74F377 Octal D-type FF

U14
U1,U5,U4
U6,U7,U8
U2
U17,U23
U15
U21, U24

MC74LS74AN, Motorola or equiv.
MC74F163AN, Motorola or equiv.
MC74LS163AN, Motorola or equiv.
MC74F174AN, Motorola or equiv.
MC74F374N, Motorola or equiv.
MC74HCT374N. Motorola or equiv.
MC74F377N, Motorola or equiv.

32

1

Crystal oscillator

Y1

MXO-55GA-2C-27MHz, CTS-Kyight
F11 00H-27M Hz, Fxo

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

15
4
4
1
3
1
1
2
1
1
1
1
1
2
2
1
1
4
1

Test points
Shorting block
Jumpers
Power Connector
BNC connectors
S-VIDEO Connector
25-pin D-connector
SPDTswitch
SPDTswitch
SPDTswitch
HEX rotary switch
PLCC socket
Oscillator socket
20-pin DIP socket
24-pin DIP socket
28-pin DIP socket
Universal transistor mount
Standoff
Bare PC Board

TP1-TP15

ME151-203-100, Mouser
ME151-8000, Mouser
NSH-36SB-S1-TR, Robinson-Nugent
ELM0331 00, PCD
31-5431, Amphenol
749263-1 , Amphenol
617B025SAJ220, Amphenol
090320102, Secma Inc.
ATIDG-RA-1, Alco Switch
TP11 FG-RA-O, Alco Switch
350134GSV, EECO
PLCCB-84-PS-T, Robinson-Nugent
ICA-143-SCO-TG30, Robinson-Nugent
ICA-203-S-TG30, Robinson-Nugent
ICA-243-S-TG30, Robinson-Nugent
ICA-286-S-TG30, Robinson-Nugent
111-080, BIVAR
1902F, Keystone
40X07140 Rev. B, Raytheon Semi.

For More Information call 1-800-722-7074.

E1,E4, E5,E6
J1
J2,J3,J4
J5
P1
E2,E7
S2
S3
S1

Raytheon Semiconductor

7-171

TP-51A
APPENDIX 8 PAL Functions Listings
This appendix contains the programmable array logic listings of the devices used on the TMC22061 P7C evaluation
board. These listings are shown as ABEL_HDL source files. The following brief tutorial is provided and refers only to
terms used for programming logic used on this board,.
Sets
A set is a collection of signals and constants that are operated on as one unit. Any operation applied to a set is
applied to each element in the set. For example in U9,
count

=

[c3,c2,cl,cO]

Valid operations used on the TMC22061 P7C are:

Operator

Example

:=

A .= [1,0,1]
!A
A & B
A # B
A == B
A != B
A < B
A <= B
A > B
A >= B

&

#

!=
<
<=
>
>=

Description
registered assignment
NOT: ones complement
AND
OR
equal
not equal
less than
less than or equal
greater than
greater than or equal

The basic elements of a source file
Module
Title
Declarations
Equations
End

7·172

The module statement names the module and indicates the presence of any dummy variables used.
The title statement can be used to give a title or description for the module.
Declarations associate names with devices, pins, nodes, constants, macros, and sets.
It is possible to use equations, state diagrams, or truth tables to describe logic designs. All
programmable devices in appendix A use equations.
The end statement terminates the module. Comments begin with double quotation marks, " ", and
end with either another double quotation mark or the end of line, whichever comes first.

Raytheon Semiconductor

For Mora Infannallcn call 1-800-722·7074.

TP-51A
Board Reference Designator U9
bdl u9
Module
'VVSYNC generation and reset control logic'
Title
Declarations
bdl u9 device "P16R8';
"inputs"
pin 1,2,3,4;
clk,v,pn,f
pin 7;
s reset
"outputs"
pin 19,18,17,16;
cO,cl,c2,c3
pin 15,14,13,12;
fb,vvsync,pgmfb,pgm
"notation"
count = [c3,c2,cl,cO];
t = (s_reset & !pgmfb) # pgm # (v & s reset & !pgm &
pgmfb) ;
Equations
!cO
:= cO & t & (count != 15 )
# !t;
!cl
:= !cO & !cl & t & (count != 15 )
# cO & cl & t (count != 15)
# !t;
!c2
:= !c2 & !cO & t & (count != 15)
# !c2 & !cl & t & (count != 15)
# c2 & cl & cO & t & (count != 15)
t;
#
:= c3 & !cO & t & (count != 15)
!c3
c3 & !cl & t & (count != 15)
#
c3 & !c2 & t & (count != 15)
#
t;
#
!vvsync := fb & pn & ( (count >= 3) & (count <= 5) )
# fb & ( (count >= 4) & (count <= 5) )
# !fb & !pn & (count -- 5)
# ( (count >= 6) & (count <= 7) ) ;
!fb
:= (! fb & v) # (f & ! v) ;
.= s reset;
pgmfb
!pgm
:= (count -- IS)
# s reset & pgmfb & !pgm
# !s- reset;
End
bdl u9

For MorelnfannaJIon call 1-800-722-7074.

Raytheon Semiconductor

7-173

TP·SIA
Board Reference Designator U10
Module
bd1 u10
Title
'VHSYNC generation and data control logic'
Declarations
bd1_u10 device "P20R8';
"inputs"
aO,a1,a2,a3,a4,a5,a6
pin 2,3,4,5,6,7,8
a7,a8,a9,aO
pin 9,10,11,14;
pin 1,23;
clk,pn
"outputs"
vhsync,pdc,hclk
pin 22,21,20;
h2clk,den,pclk
pin 19,18,17;
fb
pin 16;
"notation"
addr
[a10 .. aO);
Equations
!vhsync := «addr >= 16) & (addr <= 256»;
!hclk
:= «addr >= 1712) & (addr <= 16»;
h2clk
:= «addr >= 15) & (addr < 256»

# ! fbi
!den
!pclk
!fb

:= aO;
:= ! aO;
:= «addr >=766)

&

(addr < 1015);

End

Raytheon Semiconductor

For Mont Infannallan call1.aoo-722-7074.

TP-51A
Board Reference Designator U11
Module
bd1 ull
Title
'TMC22090 programming control'
Declarations
bd1 u11 device "P20R8';
"inputs"
clk
pin 1;
aO,a1,a2,a3,a4,a5,a6
pin 2,3,4,5,6,7,8;
a7,a8,a9,a10,a11
pin 9,10,11,14,23;
"outputs"
offset,zero,countclr
pin 22,21,20;
dck,rw,cs,aa1,aaO
pin 19,18,17,16,15;
"notation"
addr = [all .. aO);
Equations
!offset
:= ((addr >= 3081) & (addr < 3265));
!zero
. - (addr == 0)
#
((addr >= 3264) & (addr <= 3327));
countclr
.= (addr >= 3265);
!dck
:= !a1 & zero;
!rw
:= zero & (addr <= 3261);
!cs
.- (a1 & aO)
#
(!a1 & !aO)
#
(addr >= 3263)
#
! zero;
!aa1
: = (addr <= 9)
# ((addr >= 3082) & (addr <= 3085))
#
!zero;
!aaO
.= !offset
# (addr >= 3264)
#
! zero;
End
bd1 u9

For More Information call HI00-722·7074.

Raytheon Semiconductor

7·175

TP-51A
Board Reference Designator U20
Module
bdl u20
Title
'TRS decode'
Declarations
bdl_u20 device "P16R8';
"inputs"
dO,dl,d2,d3,d4,d5,d6,d7
pin 2,3,4,5,6,7,8,9;
"outputs"
pl,p2,p3,f,v,h
pin 19,18,17,16,15,14;
p reset,ldv
pin 13,12;
"notation"
data = [d7 .. dO];
Equations
!pl
"hFF) ;
.- (data
!p2
"hOO) & !p1;
.- (data
.= (data
!p3
"hOO) & !p2;
!h
.- ( !h & p3) # ( !d4 & !p3) ;
.= (!v & p3) # (! d5 & !p3 & !d4)
!v
# ( !v & !p3 & d4) ;
!f
.- ( ! f & p3) # ( !d6 & !p3 & !d4)
# (! f & !p3 & d4) ;
!p_reset
.- !p3 & d4;
!ldv
.- !p- reset # ldv;
End
bd1 u9

7-176

Raytheon Semiconductor

For More Information call 1-800-722-7074.

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TP-51A
Additional Information
A schematic database is available in OrCADtm format, along with PAL and EPROM Maps. Contact the factory.
The TMC22061 Demonstration Board, design documentation, and software are provided as a design example for the
customers of Raytheonr. Raytheon makes no warranties, express, statutory, or implied regarding merchantability or
fitness for a particular purpose.
Raytheon reserves the right to change products and specifications without notice.

7-184

Raytheon Semiconductor

For More Information caJI1-800-722·7074.

TP-52A

Bilinear Interpolation in Polar Coordinates

For More Information, caJI1-800-722-7074.

Raytheon Semiconductor

7-185

TP-52A

7-186

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

TP·52A

Bilinear Interpolation in Polar Coordinates
Dr. John A. Eldon
In many radar and medical scanner applications, data are collected in polar format at discrete
range/azimuth positions, but displayed on a rectangular raster. To create a raster display or to
prepare the data for manipulation, the user typically wants to locate, for every picture element (
pixel) "p" with integer "target" Cartesian coordinates, the corresponding set of polar coordinates
in the "source" data space.
In polar space, unless the transformed point p happens to coincide with one of the positions
whose signal value is known, its value must be estimated from those of the surrounding points.
As in conventional rectilinear resampling, one can interpolate the transformed point's value from
those of the nearest one, four, or sixteen data points. This application brief provides some
guidance for dealing with the geometric distortions inherent in polar-to-rectangular resampling.
Although this application brief deals specifically with the problem of bilinear ( four-point)
resampling, the reader may extend it to other resampling kernel sizes.

Figure 1. Backmap from Raster to Polar
.A

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from those of R, then the terms Involving ( up - Uc ) and/or ( vp - Vc ) need to be rescaled to make
all length-dimension variables consistent in the above equations. In Figure 1, one unit of R
corresponds to one unit of u, but 1.25 units of v. The polar coordinate origin lines at
(uo + 6.7 , Vo + 8.7). The Pythagorean Theorem yields:

f)

Rp = ((uo + 4 - Uo - 6.7)2 + 0.82 (vo + 4 - Vo - 8.7)2)1/2 = 4.34,
or Ro = 4 and fR = 0.34, separating the integer and fractional parts for later computational
convenience. Since p is to the left of the polar center,
Ap = 1t + arctan(0.8(vo+8.7-vo-4) / (uo+4-uo-6.7)) = 2.19 radians.
Since the angular step in Figure 1's polar coordinates is 21t/16 radians, Ap
5.6, or Ao = 5 and fA = 0.6.

= 2.19 / ( 21t116 ) =

In the example shown, the polar coordinates of the point "p," which lies at ( Uo + 4 , Vo + 4 ) in the
display raster grid, are ( Ro + fR ' Ao + fA ) = ( 4.34,5.6). Since the signal value at this precise
location is not known, it is estimated from the values of the four nearest known data points, which
define the dotted trapezoid surrounding p.
Figure 2 is an expanded and rotated view of transformed data point "p," whose coordinates in
polar space are ( Ro + fR ' Ao + fA). The four surrounding known data values are "ul"
( upper left) at ( Ro ' Ao ), "II" at ( Ro + 1 ,AO)' "urn at
( RO ' AO + 1 ), and "Ir" at ( Ro + 1 ,Ao + 1 ). Blindly and naively estimating the value at p from
those at the four reference points according to the standard bilinear interpolation formula, would
yield:

For noncritical applications, this will produce acceptable results, particularly if the number of
azimuthal bins is large and the number of range bins is small. However, many applications will
demand at least some of the geometric corrections described below.
Since bilinear interpolation is a Cartesian procedure, an artificial rectangular grid, ( x,y ), is
constructed with an origin coinciding with that of the polar data source space and with y-axis
oriented at the angle Ao + 0.5, halfway between p's four nearest neighboring data pOints. [Note
that our point-specific local coordinates x and y, contrived strictly for convenience in the
discussion which follows, are not generally aligned with the desired rectilinear display space.] If
N represents the number of azimuthal rays per full circle, and A and F are defined as 1tIN and
A (2fA - 1 ), respectively, then the rectangular coordinates of the transform point and its four
surrounding data points are as listed in Table 1.
7·188

Raytheon Semiconductor

For More Information call 1-800·722·7074.

TP-52A
Figure 2. Bilinear Resampling with Polar Data

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ur, II, and Ir, the polar coordinate system has been rotated and local Cartesian coordinates x and
y ( not to be confused with display coordinates u and v ) have been defined for convenience.
Table 1. Polar and Local Rectangular Coordinates

Point

Polar

Rectangular

p

( Ro + fR ' Ao + fA )
( Ro ,Ao)
( Ro ' Ao + 1 )
(Ro+1,Ao)
( Ro + 1 , Ao + 1 )

( ( Ro + fR ) sin ( F ) , ( Ro + fR ) cos ( F ) )
( -Ro sin ( A ) , Ro cos ( A ) )
( Ro sin ( A ) , Ro cos ( A ) )
( -( Ro + 1 ) sin ( A ). ( Ro + 1 ) cos ( A ) )
( ( Ro + 1 ) sin ( A ) , ( Ro + 1 ) cos ( A ) )

ul
ur
II
Ir

Having established the positions of the four reference pOints and the transform point in the new
rectangular space, proceed with the bilinear interpolation, noting any distortions arising from the
polar format of the data.
First, consider the y dimension. Each reference point's y coordinate is scaled by a factor of cos
(A ), whereas the y coordinate of p is scaled by cos (F), which can vary in value from 1 to

For More Infonnalion call 1-800·722·7074.

Raytheon Semiconductor

7·189

TP~52A
cos ( A). The maximum distortion of p's y position occurs when p lies on the y axis, i.e., when fA
= 0.5. In this case, the positional distortion and thus the interpolation accuracy will be a function
of radial position ( range) and azimuthal step size, i.e., the number of data scan directions. For
example, if there are 64 range bins and 128 sca.n angles spread over a full circle, then the
maximum distortion will be 64 * ( 1 - cos ( 7tl128 ) ) =0.02 range bins. This implies that if Ro =64
and fA = 0.5, the point p will lie 0.02 range bin lower ( farther from the origin) than indicated by
fRo To correct for this effect, the user would increase fR by 0.02 before interpolating radially.
Without this correction term, proceed with the first dimension of a conventional bilinear
interpolation,multiplying the values at ul and ur by ( 1 - fR ) and the values at II and Ir by fRo To
apply the correction, replace fR with fR" where:
fR'

=fR + ( Ro + fR ) ( cos ( n: ( 1 - 2fA ) IN) - cos ( 7tlN ) )

The correction term vanishes as the transformed point approaches one of the source data
azimuthal axes, i.e, as fA approaches 0 or 1.0. Furthermore, the error grows linearly with range.
Perhaps the simplest way to handle this is to increase the size of the coefficient table, so that it
can be addressed jointly by fR' Ro' and fA' instead of only fR and fA.
Using similar logic, examine distortion in the x direction, to compute the appropriate adjustment
for fA. The x coordinates of points ul and ur are - Ro sin (7tlN ) and Ro sin (7tlN ), respectively,
whereas the x coordinate of p is ( Ro + fR ) sin ( n:( 1 - 2fA ) IN), and the x coordinates of the two
lower reference points are -( Ro + 1 ) sin ( 7tlN ) and ( Ro + 1 ) sin ( 7tlN). With no geometric
correction, one would execute the second dimension of the bilinear interpolation by multiplying ul
and II by ( 1 - fA ) and ur and Ir by fATo apply a geometric correction to the second dimension of the bilinear interpolation, note first
that the distance between the two lower reference points is L = 2 ( Ro + 1 ) sin ( 7tlN ), whereas
the x coordinate of p is ( Ro + fR ) sin ( n:( 1 - 2fA ) IN). The horizontal projections of the
distances from II to p and from p to Ir are M = ( Ro + 1 ) sin ( 7tlN ) - ( Ro + fR ) sin ( n:( 1 - 2fA ) IN )
and N =( Ro + 1 ) sin ( 7tlN ) + ( Ro + fR ) sin (n:( 1 - 2fA ) IN ), respectively. Instead. of multiplying
II by ( 1 - fA)' multiply it by NIL. Similarly, to apply the geometric correction to Ir, multiply it by
MIL instead of fA.
Finally, the problem of horizontal interpolation between the two upper reference pOints, ul and ur,
is addressed. With no geometric correction, ul is multiplied by ( 1 - fA) and ur by fA- If p's x
coordinate falls between -Ro sin ( 7tlN ) and +Ro sin ( 7tlN ), then define I, m, and n following the
development of L, M, and N in the previous paragraph, viz:
I =2 (Ro) sin (7tlN), m = Ro sin (7tlN) - (Ro + fR) sin (n:(1 - 2fA) IN), and
n = Ro sin ( n:IN ) + ( Ro + fR ) sin (n:( 1- 2 fA ) IN ).
Then, multiplying ul by nil and ur by mil will yield a geometrically corrected result.
The problem with this approach is that it doesn't satisfactorily address p's which fall near one of
the azimuthal axes, such that x ( p) is between x ( ul ) and x ( II ) or between x ( ur) and x ( Ir),
as in the shaded regions of Figure 2. The denser our set of data - bearing azimuthal scanlines,
7~190

Raytheon Sem!conductor

For Mora Information call 1-800-722-7074.

TP-52A
the less significant this problem is. One fairly clean way to handle the problem is to reduce the
bilinear interpolation to a one - dimensional linear interpolation in such cases, taking advantage
of the proximity of p to two known data points. Thus, as fA approaches 0, compute the value of p
as:

v ( p ) = ul ( 1 - fR ) + II ( fR )
As fA approaches 1.0, one would use a similar one - dimensional interpolation, substituting ur for
ul and Ir for II".
To decide if and when to employ a geometric correction in polar data resampling, the user should
run a series of test simulations with simple geometrical shapes as source data and watch for
distortions and other artifacts during resampling. If present, artifacts will generally be most
noticeable at the largest radii. Alternatively, the user can employ the geometric correction
equations presented in this paper to calculate the worst - case spatial distortion and then judge
whether this would be visually objectionable.

For More Infonnation call 1-800-722-7074.

Raytheon Semiconductor

7-191

TP52A

7-192

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4193/4391

RC4193/4391 Switching Regulators

For More Information, call 1·800-722·7074.

Raytheon semiconductor

7·193

RC4193/4391
Table of Contents
Page

Introduction .............................................................................. 3
Application Suitability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3
Oscillator ................................................................................
Internal Design .........................................................................
Frequency Accuracy ....................................................................
Synchronized Oscillator .................................................................
Duty Cycle .............................................................................
Soft Start ..............................................................................
Delayed Start ...........................................................................
Current Limiting ........................................................................

4
4
5
5
5
6
6
6

4391 Step Down .......................................................................... 6
4193 Low Voltage Start Up ................................................................. 9
±12V Transformer Coupled Application ...................................................... 9
Capacitor Coupled ±15V Power Supply ..................................................... 12
Pot Core Inductor Design .................................................................
Electricity Versus Magnetism ............................................................
Pot Cores for 4193/4391 ................................................................
Core Size .............................................................................
Use of the Design Aid Graph ............................................................
Manufacturers .........................................................................
Design Examples ......................................................................

14
14
15
15
15
17
17

Appendix: Troubleshooting Chart ......................................................... 21

7·194

Raytheon Semiconductor

For Mora Information, call 1·800-722·7074.

RC4193/4391
Introduction
The RC4193 and RC4391 are low power switching regulator control ICs, complete with all the
active components needed to build small power
supplies. The 4193 is dedicated to step up applications (VIN < VOUT) and uses an internal NPN
power transistor, while the 4391 is set up for step
down (VIN > VOUT) and inverting (positive input,
negative output) applications, and includes a
PNP power transistor. More detailed information, such as pin out, specifications, and basic
usage are contained in the RC4191/4192J4193
Data Sheet and the RC4391 Data Sheet. This
application note is intended to supplement the
data sheets; it provides extra application circuits
plus additional design and troubleshooting aids.
First is a brief section with guidelines for determining whether these micropower regulators
meet your application requirements. Next is a
discussion of the internal oscillator. Limitations
and characteristics of the oscillator are provided,
along with some circuits that use the oscillator
(Cx) pin for other purposes. After the oscillator
section is a very basic 4391 application (step
down) which was not included in the RC4391
Data Sheet. Following this step down application are some specifically tailored 4193 application circuits, with specifications and PC card
layouts. These dual op amp supply applications
give the reader good examples of the size,
simplicity, and performance made practical by
the RC4193 and RC4391.
Near the end of this application note is a section
on designing a pot core inductor to fill the requirement for an external inductor. This inductor
design guide was intended for engineers without
a strong background in magnetics; it shows how
to select a core and wind it properly without an
excess of equations or complex calculations
that confuse many first time switching regulator
users. Included are design examples that start
with the application requirements and end up
with a finished pot core design.
Last is a troubleshooting chart listing common
prototype breadboarding problems and possible
causes and cures.

1. Small Size
The Raytheon circuits are packaged in an
8-lead mini-DIp, and this combined with the
low external component count reduces the
amount of PC board area needed to about 1
inch 2 • Also, they work well up to 75kHz,
reducing the size of the inductor core required. Therefore on card power supplies
where the regulator is built on the same PC
board with other circuitry are practical and
cost effective. Competitive manufacturers'
controllers usually come in 14 or 16 lead
packages and require more external
components.
2. Efficiency

The efficiency depends on two major factors:
The ratio of controller power consumption to
load power, and the saturation voltage of the
power switch transistor. First, 4193 and 4391
feature very low supply current, so the
power consumed will be very low compared
to the load power. If the load power is high
then this feature loses importance, and controllers with milliamps of supply current
become acceptable. Second, the saturation
voltage of the power switch transistor will
reduce efficiency at high switch currents.
External switch transistors can help here, but
add to circuit complexity and cost. Below
are some general guidelines for efficiency
and load power, showing the range of power
that Raytheon'S circuits are practical for.
Efficiency
Load Power

4193

Selecting the best switching regulator controller
for a given application means reviewing the
strengths and weaknesses of the controllers
available and deciding which fits in your niche.
The main strengths of Raytheon's 4193 and 4391

4391

Comments

Oto 150mW 70 to BO% 60 to 70% Ideal range
150 to 400mW 60 to 7rJ'/o 50 to 60% Somewhat
reduced efficiency
400mW to
10W

50 to BrJ'/o 60 to 80% External power
transistor

>10W

Application Suitability

For More Information, call 1-800-722-7074.

are their small size, low quiescent current, and
versatility; the weaknesses are relatively low
power transistor current rating (375mA), imprecise oscillator frequency, higher EMI (electromagnetic interference), and single ended output.

Impractical for 4193/4391 due to
imprecise oscillator frequency

3. Versatility
Between the 4193 and the 4391 all the standard switcher configurations can be built
using a minimum of external components.

Raytheon Semiconductor

7-195

RC4193/4391
The 4193 is dedicated to step up applications
and the 4391 covers inverting and step down
applications. Also, a variety of other features
are possible using the remote shutdown
capability and low battery detection circuitry
(see the applications in the 4191/4192/4193
Data Sheet and later in this publication for
examples).
4. Oscillator Tolerance
Because the oscillator is constructed with
diffused resistors the initial accuracy and
drift with temperature of the oscillator frequency is poor. Therefore, the application
circuit must be overdesigned so that units
with a higher than nominal frequency will
meet the output load current drain, and units
with a lower than nominal frequency do not
overcurrent or overheat the power transistor
or overcurrent and saturate the inductor. At
high load power (> 10W) this variation
becomes impractical, since an increase in
component specifications tolerable at lower
power becomes expensive and bulky at high
power. See the section titled "Oscillator" for
more information.

5. EMI (Electromagnetic Interference)
The 4193 and 4391 use a variable duty cycle
method of feedback control rather than
pulse width modulation (PWM) control.
Under reduced load current or no load conditions the duty cycle will be greatly reduced
and the short pulses produced will cause
greater RF radiation, due to the increased
high frequency components of the voltage
switching waveform at the switch transistor.
This problem of somewhat greater EMI at
low loads is offset by the benefit of variable
duty cycle control having no minimum load
required. PWM circuits usually require some
minimum load current to maintain regulation.

Oscillator
Internal Design
The oscillator creates its square wave like the
popular RC555 timer does: by the charge and
discharge of a capacitor, controlled by two voltage level detectors and a current steering flipflop. See Figure 1.

+Vs

r--------------I

I
I

Cx

I

A/"V

-1.78V
-{J.67V

I

I
I
Cx

I
D

I-IJIL
Lx (4193) C[J

JtLJ
1

.,

I

Lx (4391)

I

-Off

-On
~On

NPH
PHP

-Off

'--v-'

Maximum
On Time

I
I

,I

~---------------"::" GND

65-02155A

Figure 1. Oscillator Block Diagram and Waveforms
7-196

Raytheon Semiconductor

For More Information, call 1·800-722·7074.

RC4193/4391
When power is first applied, the timing capacitor
Cx charges up from a constant current source I,
integrating the current into a linear voltage
ramp. The voltage ramps up until it reaches the
upper comparator threshold, at which time a
current sink 21 which subtracts from I is
switched in; the resultant negative current discharges Cx. The voltage on Cx then ramps
downward, until it hits a lower threshold voltage,
switching 21 out, and the voltage again ramps
upward. This cycle repeats itself endlessly and
the resultant triangular waveform can be observed at the Cx pin. The square wave output is
internal and cannot be directly observed. Note
also that the 10pF capacitance of a 10X scope
probe will change the frequency of oscillation.
The internal power transistor switches at the
peaks of the triangle wave. The two Raytheon
parts switch at opposite phases of the triangle;
when the power transistor of the 4193 is on and
the triangle wave on Cx is ramping down, the
4391 's transistor is off. This means that when
power is first applied, the 4193's transistor is on,
a hard start condition that can cause latch up
and excess supply current (the 4391 starts up
with its transistor off). This hard start condition
is easily cured with the addition of one capacitor
(see the section "Soft Start" for details),

TTL or
CMOS

n

-.-J

I

U

I 4193/4391

:

I

I

I

I

I

I

I

Input

Cx

I

~ ___ .J

r

~7~'

Figure 2. Synchronized Oscillator Interface

.

ex

VFB

Lx (4193)

Lx (4391)

High
High
Low
Low

High
Low
High
Low

Off
On
Off
Off

Off
Off
On
Off

·"High" = tied to supply through 100K
"Low" = tied to ground through 100K
"Low" = tied to negative voltage through 100K
(4391 only)
Figure 3. Truth Table for Cx and VFB
(Static Conditions)

Frequency Accuracy
The oscillator was designed to be simple and
operate down at low supply voltages, and as a
result the initial frequency accuracy and drift
with temperature are poor. All application designs must take this variation into account. Use
±30% tolerance in figuring worst case component values and ratings, ensuring that the
inductor value is low enough for those units with
a high oscillator frequency, and that the inductor
and power transistor have a high enough peak
current rating to cover those units whose oscillator frequency is lower than nominal. This
±30% tolerance is most important to high power
applications, especially when selecting external
power transistors and inductor cores.

Synchronized Oscillator
If a TTL or CMOS square wave is available the
internal oscillator may be slaved to the external
signal. Figure 2 shows the one resistor interface.
In addition to its use in easing component tolerance problems this interface can help in troubleshooting switching problems on prototype
breadboards. The truth table (Figure 3) shows
For More Information, call 1-800-722-7074.

what state the internal power transistor will be in
for combinations of Cx pin and VFB pin
conditions.

Duty Cycle
There is a SMS turn off delay of the 4193 power
transistor (3MS for the 4391). When on, the transistor saturates and remains on SMS after the
oscillator (Cx) transition, This causes the maximum duty cycle to be greater than SO%, and
increases with increasing oscillator frequency.
For this reason application designs should be
limited to 7SkHz maximum operating frequency.
The duty cycle can be varied somewhat by connecting a high value resistor between the Cx pin
and either ground or +Vs. Note the difference in
polarity between the 4193 and 4391; a pull up
resistor decreases the 4391 duty cycle and increases the 4193 duty cycle. Limit the current in
this resistor to O,SMA (2M'o from Cx to ground).
The variable duty cycle method of feedback
control used (as opposed to PWM) turns on the
switch transistor only when the load demands
current. This feedback system responds to a
wide range of load currents, and regulates
tightly from no load to full load where other systems require a minimum load. However, this on

Raytheon Semiconductor

7-197

RC4193/4391
demand system can make the oscillator appear
"noisy," as its voltage waveform may not be in
synchronization with the oscillator waveform.
This is a normal operating condition, but may
cause extra EMI (electromagnetic interference)
under reduced output loading conditions.
Soft Start
At the moment power is applied the 4193 is fully
on, and the resultant current spike can cause
the supply voltage to sag or the inductor to
saturate and complicate startup. Many of these
problems can easily be cured by adding a capacitor to the startup circuit as shown in Figure 4.
+Vs
1M

In this case the open. collector LBO (Low Battery
Detector) output clamps the oscillator pin (Cx)
low and forces the power transistor off. Slowly
the capacitor C will charge up to the LBR threshold. When the +1.3V threshold is reached, the
LBO comparator will reverse its state and unclamp the oscillator, allowing it to run freely and
toggle the power transistor. This can be used for
much longer delays than the soft start circuit.
Current Limiting
The oscillator (Cx) pin can also be used to add
short circuit protection in a method similar to
the external sync interface. A transistor VBE is
used as a current sensing comparator which
resets the oscillator upon sensing an overcurrent condition, thus providing cycle-by-cycle
current limiting. Figure 6 shows how this is
applied to the 4391 in an inverting application.
+Vs

Ie

111

RC4193
4391

Figure 4. Soft Start Circuit
The delay introduced by the RC time constant at
startup allows the output filter capacitor to
charge up before the power transistor switches
on, reducing the instantaneous supply current.
A typical value for C is in the O.1jlF to 1.0jlF
range.
Delayed Start
A more sophisticated delay start feature may be
added by use of the low battery detector. See
Figure 5 for a schematic.

7.5M

+Vs
I
I

RC4193

CT

LBO I

47K

18

I
I

I

r L_______ _
I

I
I
1

+1.3V

2

J

65-021S8A

Figure 5. Delayed Startup Circuit

7-198

This idea is not as easy to implement with the
4193, because its Cx pin must be clamped low
instead of high to force the output transistor off.
The emitter of the output transistor is internally
connected to ground, so putting a resistor in
series is not possible. This idea will work for
external transistors though, and a schematic is
shown in Figure 7.

4391 Step Down

I

I

I

100K

Figure 6. 4391 Short Circuit Current Limit

I
I

I LBR
I
I
I

65-021S9A

The next section describes a new 4391 application, using the 4391 to provide the step down
or "buck" configuration instead of using a 4193
plus external transistor. This application is
important because it eliminates the external
transistor in low power step down applications
(saving PC real estate and parts costs) and also
extends the input voltage range.
Figures 8 and 9 show block diagrams of how
this trick is done. In Figure 8 the ground pin of
the device is connected to circuit ground, and
the circuit regulates to a lower output voltage.

Raytheon Semiconductor

For More Information, call1-BOo-722-7074.

RC4193/4391

1M

Ie
GND
":"

VaUl

+Vs
4193

Lx

VFB

Cx

":"

47K

Q3
":"

Cx

O.311

Ql = 2N2222
Q2 = TIP112
Q3 = 2N39D4
6S-Q2160A

Figure 7. Typical High Power Interface With Current Limit (4193)

- - - - _ - - - - - - 0 + Positive
Input

I

+VS
Out I-Entire Voltage
Across Device

Gnd

I

~GrOUnd

- - - - - - - - - 4 - - 0 Negative
Output
65-02109A

Figure 8. Normal 4391 Inverting Circuit

+ Positive
Input

J
+Vs
Minimum Voltage
Across Device

1

out~
Gnd

1

Positive
Output
IGround
65-02110A

Figure 9. New 4391 Step-Down Circuit
For More Information, call 1-800·722-7074.

Regulating to a voltage lower than ground provides the normal (positive input, negative output) inverting circuit. Figure 9 shows the ground
pin of the device connected to a positive output
voltage instead of circuit ground. This connection increases the supply voltage range, increases efficiency, and renders the 4193 stepdown circuits obsolete.
The standard step-down application for the 4193
regulator requires the use of an extra external
PNP transistor. The reason for this is that the
power switch transistor internal to the 4193 is an
open collector NPN with its emitter tied to
ground, and the step-down mode needs a PNP
with its emitter wired to the positive supply. The
4391 application shown in Figure 10 eliminates
the extra transistor in step-down circuits.
The 4391, ordinarily an inverting regulator (positive in, negative out), requires that the output
voltage sensed by the feedback resistor to be a
negative voltage with respect to the ground pin
of the device. In this step-down circuit the 4391
is tricked into believing that the output is negative by wiring its ground pin to the output filter
capacitor and its feedback resistor to the negative terminal of the battery.
When power is first applied, the 4391 senses that
the feedback point is not negative enough with
respect to its ground. Therefore, the transistor

Raytheon Semiconductor

7-199

RC4193/4391
01

VREF +Vs

+

VBAT

-=-

Lx
Lx

R1

4391

R2

'--+--"T"-'
+

VOUT

1..---+-----1,...--......- - - 0 (5V as shown)

65-o2095A

IMPORTANT NOTE: This circuit must have a minimum load current:::: 1mA always connected.
Figure 10. Low Power Step-Down Supply
switches, and pumps charge into the filter capacitor, raising the ground pin with respect to the
negative battery terlT1inal until it starts to regulate. Thereafter the feedback system will maintain a programmed voltage across the capacitor
[VOUT = (1.3V)(R2/R1)].

across the 4391 is less than the battery voltage
(applied voltage = VSAT - VOUT). This means
that less power is consumed by the regulator
and so it subtracts less from the efficiency.
Figure 11 shows how the supply voltage range
can be extended using a zener diode connected
in parallel with the device. This zener protects
the 4391 from start up transients. When power is

A side benefit of this arrangement is increased
efficiency, because the supply voltage applied

01

-::-

+1.3V
+
VBAT _

VREF
50K

R1

2.8M

R2

+Vs

4391

Lx

50n
Lx B50I'H
30V

75V

+
VOUT
1..---4--..0-.,.-----<1>-----<> (5OV as shown)

65..(}2111A

Figure 11. High Voltage Step-Down Supply

7·200

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

RC4193/4391
first applied the output filter capacitor is discharged, so the entire supply voltage is momentarily applied across the 4391. The zener diode
provides a shunt path around the device so that
the spike of current required to charge the output capacitor up to its regulated voltage does
not flow through the 4391 and possibly damage
it. Using this zener shunt gives the circuit capability to handle very high input voltages, provided the difference between input and output is
within the 30V rating of the 4391. For example, a
75V supply could be safely regulated to 50V
output, and could regulate to an even lower
output voltage if a series zener (like the optional
zener in Figure 12) is added.

4193 Low Voltage Start-Up
Figure 13 shows how the bootstrapped application can be "kicked on" using an extra capacitor
and triple pole double throw switch. This connection allows the circuit to start up using a
single Ni-Cad cell of 1.6 to 1.2V. When power is
first applied the 1.2V battery does not provide
enough voltage to meet the minimum 2.4V supply voltage requirement. The 22J.lF capacitor,
when switched, temporarily doubles the battery
voltage to bias up the 4193.
When the switch is in the down position, the
capacitor charges up to the battery voltage.

Then, when the switch is changed to the up
position, the capacitor is put in series connection with the battery, and the doubled voltage is
applied directly to the positive power supply
lead of the 4193. This voltage is enough to bias
the junctions internal to the 4193 and gets it
started. Then, when the stepped up output voltage reaches a high enough value, diode 01 is
forward biased and the output voltage takes
over supplying power to the 4193. The circuit is
shown with component values for +5V output,
but the circuit can be set up for other voltages.

+12V Transformer Coupled
Application
Transformer switching regulators have one great
advantage over the standard single winding inductor applications: multiple windings can be
taken from the secondary to produce multiple
DC output voltages. Two output voltages are
generated by the example below, the first being
a well regulated +12V and the second being an
unregulated -12V. The circuit could be built
using two switching regulators (4391 and 4193)
to provide two well regulated output voltages,
but that approach requires two ICs, two inductor
cores, and twice as much board space. The
transformer coupled circuit eliminates much of
this hardware at some expense of load and line
regulation and winding complexity.

MBR 140P

+13V

+

VBAT

.=.

5K
20K

L---+--.....- ....---+-_-o

'Optional -

Extends supply voltage range

VOUT

(+5V at 1A
as shown)

6S-Q2077A

Figure 12. High Power Step-Down Supply
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

7-201

RC4193/4391
01

+5V
Output (10mA)

~,cit
W"'

r1~

l00~H

02

I

+

5 +Vs

4193

1M

33K

Lx

22~F

VFB
13K

10pF

01 = 1N914 or equivalent
02 = Motorola MBR140P (power Schottky) or equivalent

65-02078A

Figure 13. Low Voltage Start-Up (Bootstrapped Operation)
Transformer coupled 4193 circuits are necessarily single ended (as opposed to push-pull)
because only one output transistor is included
within the IC. This single ended output exaggerates one major disadvantage of transformer
applications, the size of the core needed. Pushpull circuits utilize 100% of the flux capability of
a given core, while single ended circuits utilize
only 50%. Thus in single ended applications the

a) Simple Step-Up

core must be larger to meet the same output
power requirement. So single ended transformer
applications should be limited to lower load
power applications (less than 10W). In this
example a combination of step-up and transformer coupling is used in order to simplify the
winding arrangement (only two windings
needed). See Figure 14.

b) Simple Transformer

c) Transformer Plus Step-Up

Figure 14. Circuit Topology

7·202

Raytheon Semiconductor

For More Information, call 1·800-722·7074.

RC4193/4391
01
20:35EJ1N914 -l2V

II

R1
1M

+

T1

1~~~PUI

02
1N914 ":"

I-'--Dt---t"-_-"t--o

C4

+l2V

Output

20pF

R3
10K
65-02164A

T1 = 14mm X 8mm power pot core with .012 inch air gap (use 28 gauge magnet wire)
NOTE: +VOUT must have a minimum load for proper operation (see Figure 16)

Figure 15. ±12V Transformer Coupled Power Supply
The power supply converts +5V TTL supply
voltage into ±12V output voltages. Load and line
regulation are traded away for simplicity and
low cost; the negative output has no line regulation, and poor (but acceptable for many purposes) load regulation. In return this supply
needs only a minimum of expensive components: a single 4193 and one inductor core
constitute the majority of cost.
The positive output voltage exhibits the good
regulation of other 4193 applications, because
the feedback control is derived from the positive
output, and changes in input voltage or load
current are compensated for by adjusted duty
cycle.
Line regulation at the negative output is OdS;
any change in input voltage is seen at the negative output. This is because of transformer coupling. The input/output relationship of a transformer is given by:
Vp _ Np
Vs - Ns

As the supply voltage VIN is increased, Vs and,
therefore, -VOUT will decrease in direct proportion. This means that a preregulated voltage
supply, such as a +5V TTL supply, must be used
(rather than a battery which will decay).
Load regulation at the negative output is a function of the current drawn from both outputs.
Though obviously not a precision output, this
negative voltage is good enough for many op
amp type applications, and if necessary can be
post regulated with a three terminal series voltage regulator. See Figure 16 for a graph of negative load regulation.
14

2:

13

J

12

~

11

iz

10

:s:;;
~

where: Vp = Primary DC Voltage
Vs = Secondary DC Voltage
N = Number of turns

Positive Load Resistor [+RLl

In this case the DC voltage at the primary is the
voltage applied when the switch transistor is off.

Figure 16. Negative Output Load Regulation

Vp = +VOUT + VD - VIN
For More Information, call 1-800-722-7074.

Raytheon Semiconductor

7-203

RC4193/4391
±12V Transformer Coupled Power Supply
Specifications

simple off the shelf two terminal inductor is the
only magnetic component required.

Output Voltage .................... ±12 Volts
Input Voltage ....................... +5 Volts
Output Current ................ ±12 Milliamps
Efficiency ............................. 60%
Ripple ........................... 100mVp_p

There is a tradeoff, however, resulting from
using this capacitor coupled inverting circuit
instead of an extra winding. Unbalanced output
voltages result where the value of the negative
output voltage is always a diode drop less than
the positive. Therefore, a Raytheon 4195 seriespass dual tracking regulator IC is added after
the 4193 in order to produce balanced outputs.
Use of a linear series pass regulator reduces the
efficiency greatly, so therefore the tradeoff for
using the capacitor coupled circuitry is a loss of
efficiency (reduced to about 35-40%). Because
of this lowered efficiency battery applications
are less suitable, but the circuits strong points
(small size and low cost) make it useful for a
range of on-card applications.

Secondary
R3

e e [====:J·e

0

(;)Cl

e ec=Je
C3
eoe
02
e ec=Je

(;)C2

Drill Out

R3

:::~~.

0

<

~

R2

~

\ll

+12VoUT

A side benefit from the 4195 linear regulator is
reduced ripple and noise at the output. Also,
both the positive and negative outputs are
tightly regulated.

-12VoUT

Figure 17. ±12V Power Supply Component
Placement Diagram

+18.5V
(Regulated)
4193

A
} Regulated
±15V Output

4195

-0

-=-

65-02167A

Figure 19. Capacitor Coupled Supply
(Block Diagram)
Figure 20 shows a complete schematic of the
capacitor coupled supply including the 4195
linear regulator.
Figure 18. Transformer Coupled Supply 1X PC
Board Layout (Component Side View)

Capacitor Coupled ±15V Power
Supply
This application circuit is similar to the transformer coupled ±12V power supply in that it
uses just a single 4193 IC and one inductor core,
but in this case the negative output is created by
a capacitor-diode inverting circuit tapping the Lx
pin. So, the extra winding needed in the transformer coupled circuit is eliminated, and a
7-204

The switching regulator portion of the circuit
steps up and charges its positive output (Point
A) normally through the flyback connection of
01. (NOTE: If the 4195 is removed point A can
be used as a Single +15V supply with an output
current capability of 20mA at an efficiency of
60%.) The voltage at point A is regulated via a
feedback signal set by R2 and R3 [VA = (R2/R3
+ 1) VREFJ. This +18.5V at point A is then
stepped down to +15V by the 4195.
The negative voltage at point B is developed
through the 10jlF coupling capacitor and 02,
03. When the inductor is discharging into point
A the Lx terminal rises to one diode drop above

Raytheon Semiconductor

For Mora Information. call1-80D-722-7074.

RC4193/4391

+5V
Input

Rl
1M
Ie

+Vs
4193

220I'H
•
Dl

Lx ......................-Dlf--1--....-.--4 A

R2
110K

C3

C4+

O.OlI'F l00l'~

+15V
+Vs
-15V Output

+ C2

-Vs

~i--_-o

65-G2168A

• = 11 mm X 7mm power pot core with 70 turns and .02 inch C.P. air gap
D1, 2, 3 =1N914

Figure 20. ±15V Capacitor Coupled Supply

the voltage at point A. During this discharge
time the coupling capacitor charges through D3,
which is forward-biased. Then, when the next
oscillator cycle starts the Lx terminal is forced
nearly to ground by the internal power transistor, and the more positively charged side of
the capacitor is held at close to ground potential.
So D3 is then reverse-biased, D2 is forwardbiased, and the capacitor discharges into pOint
B. Thus point B is charged to a negative voltage
(~lV less than the magnitude of pOint A) with
each oscillator cycle. This negative voltage is
then stepped down to -15V by the 4195.

For More Information, call 1-800-722-7074.

Specifications for ±15V Capacitor Coupled
Power Supply
Output Voltage .•................• +15V ±.5V
-15V ±.5V
Output Current ....•.................. ±8mA
Input Voltage Range .......... +4.5V to +8.0V
Output Voltage Ripple .............. < 5mVpp
Load Regulation ,.................... < 5mV
(no load to full load)
Operating Temperature
Range ......•............. -35 0 C to +85 0 C

Raytheon Semiconductor

7·205

RC4193/4391
+15V Output

•

G
0

C6

+

+0 • ~

~

C7
-15V Output

Ground

Figure 21. ±15V Power Supply 2X Component
Placement Diagram (Component

Side View)

Figure 22. ±15V Power Supply 1X PC Card
Layout (Component Side View)

Pot Core Inductor Design
Magnetic Circuit

Electrical Circuit

E= I • R

65-01720A

Figure 23. Electricity Versus Magnetism

Question: What happens if too small a core is

Electricity Versus Magnetism

used?
Electrically the inductor must meet just one
requirement, but that requirement can be hard
to satisfy. The inductor must exhibit the correct
value of inductance (L, in Henrys) as the inductor current rises to its highest operating
value (IMAX). This requirement can be met most
simply by choosing a very large core and winding it until it reaches the correct inductance
value, but that brute force technique wastes size,
weight and money. A more efficient design
technique must be used.

7-206

First, one must understand how the inductor's
magnetic field works. The magnetic circuit in
the inductor is very similar to a Simple resistive
electrical circuit (see Figure 23). There is a
magnetizing force (H, in oersteds), a flow of
magnetism, or flux density (8, in Gauss), and a
resistance to the flux, called permeability (U, in
Gauss per oersted). H is equivalent to voltage in
the electrical model, flux density is like current
flow, and permeability is like resistance (except
for two important differences discussed below).

Raytheon Semiconductor

For More Information. call 1·800-722-7074.

RC4193/4391
First Difference: Permeability, instead of being

analogous to resistance, is actually more like
conductance (1/R). As permeability increases,
flux increases.
Second Difference: Resistance is a linear function. As voltage increases, current increases
proportionally, and the resistance value stays the
same. In a magnetic circuit the value of permeability varies as the applied magnetic force
varies. This nonlinear characteristic is usually
shown in graph form in ferrite core manufacturer's data sheets. See Figure 24.

6000

+25°C

5000

.' r-;"85;C I-

4000

..,I

//1,

2000

~

~

1000

I
II
.5

I
I
I- f--

Stackpole Ceramag 24B
Hysteresis Loops vs. Temperature-

I
.5

Core Size

+115°C

t::;;

3000

~

.

t-

Ll

1.0

2.5 3.0

f--

L

LJJ
2.0

5.0

7.0

9.0

HOersteds

Figure 24. Typical Manufacturer's Curve
Showing Saturation Effects

As the applied magnetizing force increases, at
some point the permeability will start decreasing, and therefore the amount of magnetic flux
will not increase any further, even as the magnetizing force increases. The physical reality is
that, at the point where the permeability decreases, the magnetic field has realigned all of
the magnetic domains in the core material.
Once all of the domains have been aligned the
core will then carry no more flux than just air, it
becomes as if there were no core at all. This
phenomenon is called saturation. Because the
inductance value, L, is dependent on the
amount of flux, core saturation will cause the
value of L to decrease dramatically, in turn causing excessive and possibly destructive inductor
current.

Pot Cores for 4193/4391
Pot core inductors are best suited for Raytheon's
micropower switching regulators for several
reasons:

1. They are available in a wide range of sizes.
4193/4391 applications are usually low power

For More Information, call 1·800·722·7074.

with relatively low peak currents (less than
500mA). A small inexpensive pot core can be
chosen to meet the circuit requirements.
2. Pot cores are easily mounted. They can be
bolted directly to the PC card adjacent to the
regulator IC.
3. Pot cores can be easily air-gapped. The
length of the gap is simply adjusted using
different washer thicknesses. Cores are also
available with predetermined air gaps.
4. Electromagnetic interference is kept to a
minimum. The completely enclosed design
of a pot core reduces stray electromagnetic
radiation - an important consideration if the
regulator circuit is built on a PC card with
other circuitry.

Question: Is core size selected according to
load power?
Not quite. Core size is dependent on the amount
of energy stored, not on load power. Raising the
operating frequency allows smaller cores and
windings. Reduction of the size of the magnetics
is the main reason switching regulator design
tends toward higher operating frequency. Designs with the 4193/4391 should use 75kHz as a
maximum running frequency, because the turn
off delay of the power transistor and stray capacitive coupling begin to interfere. Most applications are in the 10 to 50kHz range, for efficiency
and EMI reasons.
The peak inductor current (lMAX) must reach a
high enough value to meet the load current
drain. If the operating frequency is increased,
and simultaneously the inductor value is decreased, then the core can be made smaller. For
a given core size and winding, an increase in air
gap spacing (an air gap is a break in the
material in the magnetic path, like a section
broken off a doughnut) will cause the inductance to decrease and IMAX (the usable peak
current before saturation) to increase.
The curves shown in Figure 25 are typical of the
ferrite manufacturer's power HF material, such
as Siemens N27 or Stackpole 24B, which are
usually offered in standard millimeter sizes including the sizes shown.

Use of the Design Aid Graph (Figure 25)
1.

From the application requirement, determine
the inductor value (L) and the required peak
cu rrent (I MAX)'

Raytheon Semiconductor

7·207

RC4193/4391
22X
13mm
24 Gauge
70 Turns
Den = 0.5n

18X
11mm
26 Gauge
75 Turns
Den = O.7n

14X
8mm
28 Gauge
60 Turns
DC!! = 0.6n
11X
7mm

Inductor Value (Henrys)

30 Gauge
50 Turns
Den = 1n

'Includes safety margin (25%) to ensure nonsaturation.

Figure 25. Inductor Design Aid
2. Observe the curves of the design aid graph
and determine the smallest core that meets
both the L and I requirements.
3. Note the approximate air gap at IMAX for the
selected core, and order the core with the
gap. (If the gapping is done by the user, remember that a washer spacer results in an
air gap of twice the washer thickness, because two gaps will be created, one at the
center post and one at the rim, like taking
two bites from a doughnut.)
4. If the required inductance is equal to the
indicated value on the graph, then wind the
core with the number of turns shown in the
table of sizes. The turns given are the maximum number for that gauge of wire that can
be easily wound in the cores winding area.
5. If the required inductance is less than the
value indicated on the graph, a simplecalculation must be done to find the adjusted
number of turns. Find AL (inductance index)
for a specific air gap.

L (indicated) = AL (in Henrys/turn2)
Turns 2
Then divide the required inductance value
by AL to give the actual turns squared, and

7-208

take the square root to find the actual turns
needed.
L (required)
AL
Actual Turns =
If the actual number of turns is significantly
less than the number from the table then the
wire size can be increased to use up the leftover winding area and reduce resistive
losses.
6. Wind and gap the core as per calculations,
and measure the value with an inductance
meter. Some adjustment of the number of
turns may be necessary.
The saturation characteristics may be
checked with the inductor wired into the
switching regulator application circuit. To do
so, build and power up the circuit. Then
clamp an oscilloscope current probe
(recommend Tektronix P6042 or equivalent)
around the inductor lead and monitor the
current in the inductor. Draw the maximum
load current from the application circuit so
that the regulator is running at close to full
duty cycle. Compare the waveform you see
to those pictured in Figure 26.
Check for saturation at the highest expected
ambient temperature.

Raytheon Semiconductor

For More Information. call1-BOO-722-7074.

RC4193/4391

65-01723A

Proper Operation
(Waveform is Fairly linear)

Improper Operation
(Waveform is Nonlinear, Inductor is Saturating)

Figure 26. Inductor Current Waveforms

7. After the operation in circuit has been
checked, reassemble and pot the core using
a potting compound recommended by the
manufacturer.
If the core material differs greatly in magnetic
characteristics from the standard power material
shown in Figure 25, then the following general
equation can be used to help in winding and
gapping. This equation can be used for any core
geometry, such as an E-E core.
L - (1.26)(N2)(Ae)(10 8)
Xg _ (Ie/ue)
Where:

N = number of turns
Ae = core area from data sheet (in cm2)
Ie = magnetic path length from data
sheet (in cm)
ue = permeability of core from manufacturer's graph
g = center post air gap (in cm)

TDK Electronics
13-1, 1-Chome
Nihonbaski, Chuo-ku, Tokyo
Tohoku Metal Ind.
13-7,6-Chome
Ginza, Chuo-ku, Tokyo

Design Examples
Design Example One: 25kHz 4391 Inverter
Application requirements:
-VOUT = 11.3V
+Vs = 6V
ILOAD = 50mA

Inductor Approximation (See Figure 27)
1.

Find TON:

2.

Find TI:

Manufacturers
Below is a list of several pot core manufacturers:
Ferroxcube Company
5083 Kings Highway
Saugerties, NY 12477
Indiana General Electronics
Keasley, NJ 08832
Siemens Company
186 Wood Avenue South
Iselin, NJ 08830
Stackpole Company
201 Stackpole Street
SI. Mary, PA 15857

For More Information, call 1-800-722-7074.

(

1~~;:S )(2)(50mA) = 348mA

Raytheon Semiconductor

7-209

RC4193/4391
IMAX-

Charge
Slope =

Discharge
Slope =

+Vs

-(VOUT

+ Vol

---ex-

LX

Inductor
Current

0----"

T1

=

(Lx) (lMAX)
VOUT

+ Vo

ILOAD -- (IMAX)(
-Z TON +T1TOFF )

Switching
Waveform

T1
TON =

T1

=

~
VOUT + Vo

Vs- vsw) TON
( l7QiJi+l7D

65-{l2172A

Idealized Schematic
Figure 27. 23kHz 4391 Inverting Design Example

4. Find Lx:

Design Example Two: 10kHz Step-Up

Lx =(VOY~A: Vd) (TI) =(s';:~A) (11.5JLS) =396JLH

Regulator

5. Look up 400 },LH and 350mA in Figure 25 the point lies inside the #4 core area, so the
smallest size core can be used. Estimate the
air gap - at the 400},LH 350mA point the air
gap required is about .009". At .009" air gap,
the inductance value is approximately 500},LH
with a full (50 turn) winding.

L
_ 500},LH _
2
AL = Turn 2 - 5Q2 - .2},LH/Turn
The needed value of inductance is 400},LH, so
the actual number of turns =

~

Inductor Approximation (See Figure 28)
1. Find TON:

1

1

2. Find TI:
TI

=(VOUT +VsVd - Vs)

(TON)

=(1S.7VSV- Sv)\SSILS) =26ILS

3. Find IMAX:
IMAX

= 44.7 Turns
Round up to the next highest number - use
45 turns.
7-210

+VOUT = 15V
+Vs = 5V
ILOAD = 100mA

TON == 2fo + 5},LS = (2)(10K) + 5},LS = 55},LS

So

Turns (Actual) =

Application requirements:

=( TON ~ITOFF) (21Ll =

(~~:;) (2)(100mA) = nOmA

Raytheon Semiconductor

For More Information. calI1-BOo-722-7074.

RC4193/4391
Discharge
Slope =
- (VOUT + VD - VS)
Lx

IMAX- Charge
Slope =
I Vs

Inductor
Current

LX

--

0-

r-

T1

Switching
Waveform

J

I..

TON

I..

~I

T1

=

ILOAD

=

~X)(IMAX)

VOUT + VD - Vs
( IMAX ) (

-2-

T1
)
TON + TOFF

TOFF-4

T1 _
TON -

T1

Vs - VSW
VOUT + VD Vs
(

=

Vs - VSW
)
VOUT + VD Vs TON

VOUT

Idealized Schematic
Figure 28. 10kHz 4391 Step-Up Design Example

4. Find Lx:

Turns (Actual) =

Lx = (VOUT + Vd IMAX

vs)

(TI) =

= 51

J(LXALxL
AL =

j

360tLH
.138tLH/N2

Turns

This leaves some extra winding space which
could be filled by using the next larger wire
size; in this case 26 gauge would work well.
5. Look up 360tLH and 770mA in Figure 25 the paint lies between th~ #4 curve and the
#3 curve, so the #3 core must be used. Estimate the air gap - by Figure 25 it is approximately .012". At .012", the inductance value
with a full winding (60 turns) of 28 gauge
wire is about 500tLH.
So

Design Example Three: 20kHz Step-Down
(4193)
Application requirements:
+VOUT =20V
+VS = 32V
ILOAD = 200mA

Inductor Approximation (See Figure 29)
A

L

= 500tLH
= •138tL H/N2
602

1.

Find TON:

The needed value of inductance is 360tLH, so

For More Information, call1-80Q-722-7074.

Raytheon Semiconductor

7-211

RC4193/4391
Discharge
Slope
VOUT - Vo
0

----rxInductor
Current
NOTE: Inductor current flows to load
during TON and T1

0-

Switching
Waveform

J

.. I..

\.---TON

r-

T1

(Lx) (lMAX)

0

~

I
-(I
)(_T_1_
LOAO - MAX TON + TOFF

TOFF"~

+~)
TON + TOFF

..I!.. _ Vs - Vsw - VOUT
TON -

~
-=-

VOUT- Vo

T1 - (Vs - Vsw - VOUT ) T
VOUT - Vo
ON

+
Lx

VOUT

+Vs

65-02174A

Idealized Schematic
Figure 29. 20kHz Step-Down Design Example

2.

Find TI:

_ (32V - 20V)
_
_ (VS - VOUT)
TI - VOUT _ Vd (TON) - 20V _ .7V 30tLS - 18.6tLS

#3 core must be used. Estimate the air gap
- by Figure 25 it is approximately .005". At
.005", the inductance value with a full winding (60 turns) is about 1,000tLH.
So

IMAX = fo(TI

21L
+ TON)

(2)(200mA)
= 389mA
20K(18.6tLS + 30tLS)
4.

Find Lx:

Turns (Actual) =
Lx =(VOUT - Vd) (TI) =
IMAX

/LX
J"AL

=

j

923 tL H
.277 tLH/N2

= 57.6 Turns
Use 58 turns.

19.3V )
( 389mA
(18.6tL S) = 923tLH
5.

The needed value of inductance is 923tLH, so

Look up 923tLH and 389mA in Figure 25 the point lies between #3 and #4 cores so the

7-212

Raytheon Semiconductor

For More Information, call1-BOO-722-7074.

RC4193/4391
Appendix: Troubleshooting Chart
Symptom

Possible Problems

Draws excessive supply current on
start-up.

Battery not "stiff" - inadequate supply
bypass capacitor.
Inductance value too low.
Operating frequency too low.
Hard start condition - see "soft start".

Output voltage is low.

Inductance value too high for Fop or core
saturating.

Inductor "sings" with audible hum.

Not potted well or bolted loosely.

Lx pin appears noisy - scope will not
synchronize.

Normal operating condition.

~~~

Inductor is saturating:
1. Core too small.
2. Core too hot.
3. Operating frequency too low.

-IMAX

I

I

I

0

Time
Inductor current shows nonlinear
waveform.

~~Lj

-IMAX
I

I

-0

Waveform has resistive component:
1. Wire size too small.
2. Power transistor lacks base drive.
3. Components not rated high enough.
4. Battery has high series resistance.

Time
Inductor current shows nonlinear
waveform.
Poor efficiency.

Core saturating.
Diode or transistor:
1. Not fast enough.
2. Not rated for current level (high SAT).
High series resistance.
Operating frequency too high.

Motorboating (erratic current pulses).

Loop stability problem - needs feedback
capacitor.

For More Information, call1-80Q-722-7074.

Raytheon Semiconductor

7-213

RC4193/4391

7-214

Raytheon Semiconductor

For Mora Information. call 1-800-722-7074.

Section 8 - Glossary

Section 8
Glossary
Ambient Temperature (TAl
Standard temperature range devices have their
temperature range specified in terms of the ambient
temperature (still air) surrounding the converter.
Analog Ground Voltage (VAGND)
Potential of the analog ground terminal with respect to
the digital ground terminal.
Analog Input Impedance (RIN)
Although the input impedance of a flash NO converter is
largely capacitive. it does have a resistive component
which is approximated with RIN. the input resistance. RIN
varies with the input voltage.
Aperture Error (EAP)
Because there is an aperture of non-zero duration during
which the NO looks at a signal before conversion. there
are errors introduced in the conversion. These errors are
the effect of: aperture time (the amount of time during
which the input signal is considered before conversion).
aperture time uncertainty (the variation in aperture time)
and aperture jitter which is the uncertainty in the starting
instant of the aperture time. All of these effects are
combined in a single parameter. Aperture Error (EAP).
Aperture Errors cause a degradation of the SNR of the
NO converter with higher analog input frequencies and
are estimated based upon this SNR degradation.
Average Input Bias Current Drift (TCIB)
The ratio of change in input bias current to a change in
ambient temperature. expressed in nanoamps per OC
(nNoe).

TC _ IB@T(1)-IB@T(2)
IB T(1) - T(2)

Where T(1) and T(2) are the upper and lower limits of the
specified temperature range.
Average Input Offset CUrrent Orlft (TCIOS)
The ratio of change in input offset voltage to a change in
ambient temperature. expressed in microvolts per
degree C (pVJOC).

For More Information. call1-BOO-722-7074.

TC

_los @ T(1) -los @ T(2)
lOS T(1) - T(2)

Where T(1) and T(2) are the upper and lower limits of the
specified temperature range.
Average Input Offset Voltage Drift (TCvos)
The ratio of change in input offset voltage to a change in
ambient temperature. expressed in microvolts per
degree C (JNI°C).
Ves @ T(1) - VOS @ T(2)
TCVOS =
T(1) - T(2)

Where T(1) and T(2) are the upper and lower limits of the
specified temperature range.
Bandwidth, reference (BWR)
BWR specifies the maximum frequency at which the
reference (VREF) may be exercised. It is a small signal
parameter since in most cases the reference is only
varied by a small portion of its full-scale value. Exceeding
the BWR specification may result in the same types of
coding errors encountered when the BW speCification is
violated.
Case Temperature (Tc)
For extended temperature range devices. the
temperature range is specified in terms of the case
temperature.
Channel Separation (CS)
The ratio of output voltage of an afTl)lifler to the output
voltage of an adjacent amplifier whose gain is 100. and
whose inputs are grounded. expressed in decibels (dB).
Channel separation is measured at the outputs of
adjacent amplifiers:

100VOC1l)
Channel Separation = 20LOG10 ( VO(2)
Where VO(1) and VO(2) are the independent and
dependent amplifier output voltages.

Raytheon Semiconductor

8-1

Section 8 - Glossary
Code Size (Q, CS)

Code size Is the size of the IndMduai codes, from code
transition to code transition. It is often expressed as a
percentage of the Ideal code size. The Ideal code size Is
given by:
Input Voltage Range
2N

Differential NonllnearHy (DNL)

Where N is the number of bits of resolution of the NO
converter.

a is also defined as the total nurrt>er of quantizing levels
or codes output by a converter (2N).
Common Mode Rejection Ratio (CMRR)

The ratio of change of input common mode voltage (both
inputs swing together over a specified voltage range) to a
change In Input offset vo~age, expressed In decibels (dB).
CMRR = 20LOG10 (

VIN(1) - VIN(g)
)
Vas @ VIN(1) - Vas @ - VIN(2)

Where VIN(1) and VIN(2) are the upper and lower limits of
the input common mode voltage range.
Compliance

The measure of the output impedance of a switch current
source, given as a maximum current for a specified voltage
change, in microamps(J.IA).
Differential Gain (DG)

Differential gain is defined as "The difference between (1)
the ratio of the output amplitudes of a small high-frequency
sine wave signal at two stated levels of a low frequency
signal on which it is superimposed and (2) unity" [1].
Distortion-free processing of a color television signal
demands that the amplitude of the chrominance signal not
be affected by the luminance function. This is a relevant
speCification for the video industry since the saturation of
the color being shown is represented by the amplitude of a
small signal superimposed upon another signal which
determines the brightness of the color. The standard
method for measuring the differential gain of a device is by
using a standardized test signal, known as a modulated
ramp (refer to Agure 2). The output of the NO Is then
reconstructed by a reference D/A and low pass filter; the
resultant signal Is displayed on a vectorscOpe which is
defined in reference [2]. During DG measurements the
~torscope display will be fuzzy due to quantizing errors
In the NO and D/A. The measurement requires
interpretation of the peak-to-peak curvature of the center of
the waveform. There are theoretical bounds on differential
gain performance described in [3]. The number specified
8-2

on an NO converter data sheet Is the difference between
the actual differential gain of the device and the
theoretical performance. Agure 3 shows the typical test
set-up that might be used In Differential Gain testing,
which is described in more detail in reference [2].
The Incremental error from an ideal 1 LSB analog output
change when the input Is changed 1 LSB; guaranteed
monotoniclty requires the differential nonlinearity error to
be less than 1 LSB. Differential nonlinearity is expressed
as a percentage of the full scale output
Differential Phase (DP)
Differential Phase is defined a "the difference in output
phase of a small, high-frequency, sine wave signal at the
two state levels of a low frequency signal on which it Is
superimposed" [1]. Distortion-free processing of a color
television signal demands that the phase of the
chrominance signal not be affected by the luminance
function.
Differential phase errors appear on the T.V. screen as
changes in the hue of the colors (tint) as the brightness
changes. Differential phase testing is very similar to
differential gain testing. The equipment shown In Agure
3 Is identical for both tests. The results are analyzed in
the same manner as Differential Gain. Reference [2]
also Includes differential phase testing of NO converters.
Digital Input Capacitance (CI)
The amount of capacitive loading present at a digital
Input. Digital Input capacitance is measured with a
capacitance bridge, applying a 1 MHz signal to the input

Distortion (THO)
,
The large signal harmonic distortion between input and
output under closed loop conditions, expressed, in
percent at a specified frequency.
Full Power Bandwidth (BW)

Bandwidth specified for a Flash Analog-to7Digitai (NO)
converter Is different from the bandwidth specification
given for a purely analog device. Before attenuation
becomes a significant factor in the performance of the
converter, other problems may arise, leading to .
degraded performance. Spurious and miSSing codes
might be encountered when the analog input frequency
exceeds the bandwidth specification. Bandwidth for an
NO converter is the maximum frequency full-scale input
sinewave that can be accurately quantized by the NO
converter without spurious or missing codes. A spurious

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Section 8 - Glossary
code is a code which is grossly inaccurate, such as when
the input signal is near mid-scale and an output code
which is a full-scale output is generated. When the signal
is reconstructed with a O/A converter, this spurious code
looks like a glitch, and is therefore sometimes referred to
as a glitch. Bandwidth is measured with worst case power
supply conditions and sampling at the maximum sampling
rate. (FS).
The test used to determine the bandwidth of an NO
converter is the "Beat Frequency Test." The principle
behind this test is to use "aliasing" to convert a highfrequency input signal to a lOW-frequency output signal
which is easier to analyze. This is done by providing the
NO converter with a high-frequency sine wave input, and
then sampling the input at a rate offset by a small delta in
frequency from an integral (N) multiple of the input
frequency. A O/A converter is given every Nth NO output;
this produces an output Signal of the NO which is an
aliased version of the input. In a typical set-up, the analog
reconstruction (O/A output) is examined on an
oscilloscope for spurious and miSSing codes. Figure 1
shows a typical test set-up. A spurious code is defined as
a non-continuous change in the output of the NO which is
not affected in the input signal.

Where T(1) and T(2) are the upper and lower limits of the
specified temperature range.
Integral LlnearHy Error (Eu)
Integral linearity is a measure of how the ideal and actual
transfer functions of the NO compare. The integral
linearity error is the maximum difference between the
actual and ideal quantization levels (the midpoint
between adjacent threshold levels).

Full Scale Frequency
A voltage-ta-frequency converter can operate up to the
guaranteed full scale frequency without violating any of
the performance specs for this frequency range. Full
scale frequency is expressed in Hertz (Hz).

There are several methods for measuring integral
linearity. A typical NO transfer function showing different
types of linearity errors is shown in Figure 6. Zero-based
linearity is used mainly in bipolar systems with
adjustments that allow the user to null any errors at the
origin (the center of the transfer function). To measure
zero-based integral linearity, a "straight line of best fit" is
drawn through the origin. Then the maximum deviation of
the actual transfer function from this line is determined.
Terminal-based linearity measurements are similar to the
zero-based; however, the line is drawn between the two
end points of the transfer function. The same difference
signal is generated, and the same method is used for
interpreting the results. The other method for measuring
independent integral linearity involves drawing the
"straight line of best fit" through the transfer function,
independent of the mid or end points, then calculating
the error. A common method for measuring integral
linearity is the subtractive ramp test. A low-frequency
ramp is digitized by the NO converter, then the signal is
reconstructed with a O/A converter. The reconstructed
signal is now subtracted from the original ramp with a
differential amplifier and the difference (error signal) is
displayed on an oscillOSCOpe. The sawtooth wave
displayed on the oscilloscope can be examined for
integral non-linearities. Figure 7 shows the test set-up for
the subtractive ramp test.

Full Scale Symmetry
The difference between the full scale output values of the
two outputs of a complementary output O/A, expressed in
microamps (1lA).

Input Bias Current (IB)
The average of the two input currents with the output
voltage at the center of its swing with no load, expressed
in nanoamps (nA).

Gain Bandwidth Product (GBW)
The frequency at which the open loop gain equals unity,
expressed in Hertz (Hz).

Input Current, Constant Bias 1 (ICB)
The current drawn by the input of the NO converter is
dependent upon frequency and voltage level of the
analog input. The current is sometimes also dependent
upon the phase of the convert signal. This dependence
is explained under 19B, synchronous bias current;
however, neglecting all of these second order effects, the
current drawn by the input of the NO is leB. This can be
thought of as the sum of the converter input bias currents
which is dependent upon the input voltage level.

Full Scale Current (IFS)
The maximum current that can be obtained from the
output for a specified reference current, measured in
milliamps (mA). A typical binary O/A produces its full scale
output with all ones applied at the input.

Gain Temperature Coefficient
The variation of full scale current measured over a
specified temperature range, expressed in parts per
million per degree C (ppm/QC).
.
_(IFS@T(1)-IFS@T(2»)
Gain TC T(1) - T(2)
For More Information, call Hloo-722·7074.

(~)
IFS

Raytheon Semiconductor

8-3

Section 8 - Glossary
Input Current, logic Hlgh1 (IIH)
IIH is the current drawn by a digital input to the device
when the potential of the terminal is in the logic low state.
Input Current, logic Low1 (IlL>
IlL is the current drawn by a digital input to the device
when the potential of the terminal is in the logic low state.
Input Current, Synchronous Blas1 (ISB)
In some flash converters, the current flowing into the
analog input varies slightly depending upon the state of
the CONY input varies slightly depending upon the state of
the CONY signal. If the comparators are in the track mode
(CONV low), then the input current is greater, and the
amount of this current change is ISB, synchronous bias
current
Input Equivalent CapacHance (CIN)
CIN is an approximation of the largely capacitive input
impedance of a flash AID converter. The input capacitance
is slightly dependent upon the DC level of the analog input
voltage and the input frequency. The input equivalent
capacitance must be taken into account when designing a
buffer to drive a flash AID.

Input Offset Current (los)
The difference between the two input currents with the
output voltage at the center of its swing with no load,
expressed in nanoamps (nA).
Input Offset VoHage (VOS)
The voltage that must be applied between the two inputs to
obtain an output voltage in the center of the output swing
range, expressed In millivolts or microvolts (mV or J.LV).
Input Resistance (Common Mode)
The ratio of input voltage change to the resulting change in
Input bias current, expressed in megaohms or gigaohms
(MQorG~.

V(1) - V(2)
Common Mode RIN - IB @ V(1)- IB @ V(2)

Where V(1) and V(2) are the upper and lower limits of the
Input voltage range.
Input Resistance (Differential Mode)
The ratio of small signal change in input offset voltage to a
change in input current at either input terminal with the
other grounded, expressed in megaohms (M~.

The method used to test input capacitance involves
sending a high-frequency signal through a transmission
line to the analog input, and determining the input
impedance by analysis of the reflected wave. This type of
test is performed by an R.F. Impedance analyzer.

Input VoHage Range
The range of voltages at the inputs over which an amplifier
or comparator operates within its common mode rejection
ratio specification, expressed in volts (V).

Input Noise Current (INp-p)
The peak-to-peak noise current within a specified
frequency band, expressed in nanoamps or picoamps (nA
or pAl.

Large Signal Voltage Gain (AvOL>
The ratio of a specified output voltage change to the
change in Input offset voltage required to effect the change
under open loop conditions, expressed in volts per millivolt
(V/mV) or decibels (dB).

Input Noise Current DensHy (IN)
The RMS noise current in a 1 Hertz band centered on a
specified frequency, expressed in picoamps per root Hertz
(pAl~).

Input Noise VoHage (enp-p)
The peak-to-peak noise voltage within a specified
frequency band, expressed in nanovolts or microvolts (nV
or J.LV).
Input Noise VoHage DensHy (en)
The RMS noise voltage in a 1 Hertz band centered on a
specified frequency, expressed in nanovolts per root Hertz
(nV/~z).

8-4

AVOL

=( VOUT(1)
- VOUT(2) )
VOS(1) - VOS(2)

Where VOUT(1) and VOUT(2) are the specified upper and
lower voltage limits for the change at the output
Leakage Current (ILEAJ()
The current that flows into the open collector output
transistor when the logic output transistor is in the ·olr
state, as a result of the application of the maximum supply
voltage to the output. Leakage current is measured in
microamps (~).
Least Significant Bit (LSB)
The digital input line which has the smallest effect on the
analog output. LSB can also refer to the measure of the

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Section 8 - Glossary
analog output change when the input code is incremented;
in that case, the ideal value of 1 LSB is calculated as:
1LSB =(~

) (Full Scale Range) in V or MA

where N is the resolution of the converter.
Line Regulation
The ratio of change in output voltage to the change in
supply (line) voltage affecting it, expressed as a
percentage of the output voltage per volt change in supply
voltage (%N).
L1nearHy Error, Differential (ELD)
Differential non-linearity is a measure of the uniformity of
the code midpoint spacing. Differential linearity is defined
as the maximum of the difference between adjacent code
midpoints and the width of one Least Significant Bit
(LSBs). If there is a missing code, the center of that code
is considered to be the transition which skips that code. A
differential non-linearity calculation is shown if Figure 4.
Another method that can be used to determine differential
non-linearity is a subtractive ramp test which examines the
difference between adjacent quantization levels (see ELI).
This method is shown in Figure 5. Differential non-linearity
is sometimes measured with a statistical (histogram) test.
In the histogram test the AiD converter is provided a fullscale sinusoidal analog input, and a large number of
output samples is collected. The probability of obtaining
each code is then calculated and the ratio of the actual
number of samples at that code to the total number of
samples represents the differential linearity error. An
increase in code width results in a corresponding increase
in the number of occurrences of that particular code.
Load Regulation
The ratio of change in output voltage to the change in load
(output) current affecting it. measured in percent of output
voltage per mlliamp change in load current (%/mA).
Logic Input Current
The input current into the logic SWitch at specified applied
voltage. expressed in microamps (pA).

Maximum Sampling Rate (Fs)
Fs is a sampling rate (samples per second) at which the
converter is guaranteed to operate. Most flash AiD
converter will operate reliably at any rate up to the
maximum sampling rate, which is measured with worst
case supply, worst case duty cycle conditions. and
maximum full-power input frequency.
Monotonlclty
For anyone LSB increase in input code the D/A output
either increases or remains constant.
Noise Power Ratio (NPR)
"NPR is the decibel ratio of the noise level in a
measuring channel with the baseband fully noise
loaded ...to ...the level in that channel with all of the
baseband noise loaded except the measuring channel"
[4]. To test NPR, the input of the AiD converter is
presented with white noise having a frequency spectrum
from low frequencies up to 1/2 the sampling rate. The
power of the input noise is adjusted so that the converter
is fully loaded. but not Clipping excessively. The output of
the AiD converter is then converted back into an analog
signal with a 01A. The 01A output is passed through a
very narrow band pass filter. and the output power of the
signal is measured. The process is now repeated. but
with a notch filter at the input of the AiD converter. The
ratio of the two measured powers is the Noise Power
Ratio, and is often expressed in dB:
NPR = 10 10910 (ratio)
NPR is often used to determine how much noise will
"bleed" into one channel from other channels in a
broadband. frequency domain multiplexed system.
NonlinearHy
The difference between the actual analog output and an
imaginary straight line drawn between the measured
zero scale and full scale readings, for any code
combination. Nonlinearity is expressed as a percentage
of the full scale output.

LogiC Input Levels
The range of voltages within which the logic trip level is
guaranteed, expressed in volts (V).

NonllnearHy Error (NL,)
On a plot of input voltage versus output frequency, a
straight line is drawn from the origin to the full scale point
which is defined by the intersection of the maximum
input voltage and maximum output frequency.

Long Term Input Offset VoHage Stability
The averaged trend line of Vos vs. time over extended
periods after the first 30 days of operation expressed in
microvolts per month (INIMo).

The actual plot of input versus output frequency should
not deviate from this straight line by more than increment
M=O(MAX). Nonlinearity is defined here as (M=oIM=s) x
100% where FS is the maximum frequency for the range
in question. For instance, when specifying nonlinearity

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Raytheon Semiconductor

8-5

Section 8 - Glossary

error for the 0.1 Hz to 10kHz range, then Fs = 10kHz.
When specifying nonlinearity error for a frequency-tovoltage converter, nonlinearity error is defined as (t:NI
VFS) x 100%.
Offset Adjustment Range
The change in VOS that can be produced using the
specified external offset adjustment circuit, expressed in
millivolts (mV).
Offset Errors, Sense Connected EOBS, EOTS
To minimize the effect of offset errors, some NO
converters have sense outputs. These allow the use of a
sense pin, which carries minimal current to close a
feedback path around the reference input, resulting in
lower offset errors. Figure 9 shows a block diagram for
an NO converter which has sense connections. Figure
10 shows how a feedback path is closed around an
operational amplifier to make use of the offset sense
point. Eess and EOTS are the residual offset errors
when the sense leads are used.
Offset Voltage Bottom, Offset VoHage Top (EOB,
EOT)
Figure 8 shows the block diagram for a typical G-bit flash
NO converter. There is a parasitic (Rp) resistance
between the RT lead and the first resistor. The voltage
drop across this resistor is an offset voltage between the
first code quantization level and the voltage applied to
RT. This offset is referred to as EeT. The similar offset
voltage at the bottom of the resistor chain is EOB. EeT
and EeB are measured by applying a known voltage to
RT and Rs and measuring the difference between these
voltages and the voltages of the first and last code
transitions of the NO converter. In an ideal NO, the first
transition occurs at a point 1/2 LSB more negative than
the top of the range. Therefore, if the input voltage to the
device is set 112 LSB closer to RB than zero, and VRT is
adjusted to get toggling between codes 0 and 1, then the
voltage on RT will be EeT.
Open Loop Output Resistance (ROUT)
The resistance seen looking into the output with the
output at the center of its swing, under small signal
conditions, expressed in ohms (q
Output capacitance
The value of the internal parasitic capacitances,
modelled as a single capacitor from the output to ground,
expressed in picofarads (pF).
Output Current, logic High 1 (IOH)
IOH is the minimum current that is available (this is a
8-6

negative value, there current flow is out of the device) to
force an output terminal to the high state, while potential
at the terminal is at the VOH minimum specification.
Output Current, Logic Low1 (IOU
IOL is the minimum current that is available to force
output terminal to the low state, while the potential at the
terminal is at the VOL maximum specification.
Output Delay (to)
to is the time between the rising edge of the CONV
signal and the time at which the output data from the NO
is guaranteed to be stable. On many m flash NO
converters, this delay can be reduced by the addition of
pullup resistors from the data outputs of the device to the
Vee supply. This output delay is measured with the test
load specified in the corresponding data sheet
Output High VoHage (VOH)
The potential at an output terminal in the high state with
respect to digital ground, when loaded with the test load
defined in the data sheet. VOH is measured with Vee at
a minimum.
Output Hold Time (tHO)
The time from the rising edge of the convert signal to the
time when the output data lines begin to change.
Output Short ClrcuH Current1 (lOS)
The current flowing from an output when the output is
short circuited to ground while in the logic high state.
This specification is indicated only on m compatible
devices.
Output Leakage Current (ILEAJ()
For open collector output types; the collector to emitter
leakage current of the output transistor with the output in
an off condition and a specified voltage applied,
expressed in microamps (J.lA).
Output Low Voltage (Vou
The potential at an output terminal in the low state with
respect to digital ground, when loaded with the test load
defined in the data sheet. VOL is measured with Vee set
to the maximum value.
Output Sink Current (ISINJ()
The current flowing into the output for a specified set of
input and output conditions, measured in milliamps (rnA).
Output Source Current (ISOURCE)
The current flowing out of the output for a specified set of
input and output conditions, measured in milliamps (rnA).

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Section 8 - Glossary
Output Voltage Compliance
The range of voltages over which the output can be
driven while maintaining nonlinearity specifications,
measured in volts (V).
Output Voltage Noise
Output voltage noise is the broadband noise over a
specified range of frequencies, measured in microvolts
peak-to-peak (JJ.Vp-p).
Output Voltage Swing (VOUT)
The peak output change, referred to ground, that can be
obtained for a specified load resistance, expressed in
volts (V).
Overshoot (OS)
The positive or negative going excursion that exceeds
the final settled condition at the output of a closed loop
unity gain amplifier, expressed as a percentage of the
output step.

Pulse Width High (tPWtU
tPWH minimum is the minimum width high CONV pulse
with which the AID will accurately operate if all other
specifications are met. tpWH is measured from the 1.3 Volt
level of the rising edge of the CONY signal to the 1.3 Volt
level of the falling edge of the CONY signal on m
compatible devices. If the CONV Signal has a low portion
of tpWH, and a high portion of tpWH, the device may be
exceeding FS in which case it may not operate properly.
Pulse Width Low (tpwu
tPWL is the low CONY pulse width with which the AID will
accurately operate if all other specs are met. tPWL is
measured from the 1.3 Volt level of the falling edge of the
CONY signal to the 1.3 Volt level of the rising edge of the
CONY signal on m compatible devices.
Reference Bias Current
The input current to the reference amplifier which subtracts
from the reference current, expressed in microamps (J,1A).

Phase Margin (PM)
The difference between the amplifier phase shift and
1800 at the frequency where the open loop gain equals
unity, expressed in degrees.

Reference Bottom Voltage (VRS)
The potential of the RB terminal with respect to analog
ground.

Phase Margin = 1800

Where e equals the input-output phase shift at Av =1.

Reference Current (IREF)
The current flowing through the reference resistor chain (in
through RT)'

Power Bandwidth
The maximum frequency at which a specified peak
voltage sine wave may be obtained, measured in Hertz
(Hz).

Reference Input Slew Rate
The average rate of change of the output current for a step
change at the reference input, expressed in milliamps per
microsecond (mAlJ.lS).

Power Supply Rejection Ratio (PSRR)
The ratio of change of supply voltage to a change in
input offset voltage, expressed in decibels (dB).

Reference Middle Voltage (VRM)
The potential of the RM terminal with respect to analog
ground.

PSRR _ 20LOG (
VS(l) - VS(2)
}
10 Ves @ VS(l) - Ves @ VS(2)

Reference Top Voltage (VRT)
The potential of the RT terminal with respect to analog
ground.

-0

Where VS(l) and VS(2) are the upper and lower limits of
the specified change of supply voltage.
Power Supply Sensitivity
The ratio of change in the full scale output to a change in
supply voltage, measured in percent of full scale per
percent change in supply voltage (o/oM=s/%AV).

Reference Resistance (RREF)
RREF is the total resistance of the entire reference resistor
chain, including parasitics. It can be measured directly
between RT and RB. Another method of testing RREF is to
calculate it from IREF and (VRT - VAB).

Propagation Delay
The time delay between a step input to all inputs and a
change in the output, from the 5% point of m input
swing to the 50% point of the final output value.
Propagation delay is expressed in nanoseconds (ns).

Resolution
The number of inputs or bits. The number of discrete steps
or states at the output is equal to 2N, where N is the
resolution of the converter.

For More Information, call 1-800-722.7074.

Raytheon Semiconductor

8-7

Section 8 - Glossary
Rise Time
The time required for an output voltage step to change
from 10% to 90% of its final value, expressed in
nanoseconds (ns).

Sink Current (ISINKl
The amount of current that can be forced into the output
with the reference still within :±a% regulation, expressed
in milliamps (mA).

Sampling Time Offset (tSl0)
Sampling time offset is the time interval between the
rising edge of the CONV signal and the actual instant at
which the NO samples the input signal.

Supply Current1 (ICC)
ICC is the current drawn by the device from the VCC
supply. ICC is a positive valued parameter. ICC
decreases with increasing temperatures in most NO
converters and is measured with VCC at the maximum
rated value.

Scale Factor (K)
Scale factor K is the ratio of FoNIN.
Settling Time
The time delay between a 50% of m level change at all
logic inputs to the point where the output settles within a
speCified error band of its final value, for either full scale
to zero scale or zero scale to full scale changes. Settling
time is measured in nanoseconds or microseconds (ns
or J.IS).
Short Circuit Current (Isc)
The maximum output current available from a device
with the output shorted to ground, expressed in milliamps
(mA).
Signal·ta-Noise Ratio (SNR)
The signal·to·noise ratio is the ratio of the value of the
Signal to that of the noise. The values of the signal and of
the noise are usually expressed as RMS, but for some
signals such as video, it is defined as peak· to-peak
signal vs. RMS noise, because it is difficult to determine
the RMS value of a video signal, and the meaning of
peak-to-peak noise is not a useful parameter. The signal·
to-noise ratio of an NO converter provides a good figure
of merit for the dynamiC accuracy of the device. To test
SNR, the NO converter is given a high purity sine wave
input. This is sampled at a non-harmonic sampling rate
and the output of the NO converter is stored in memory.
The data from the NO are then transformed into the
frequency domain with a Fast Fourier Transform (FFT)
and analyzed to determine the SNR. When analyzing the
data, most of the "noise" will be located at the harmonic
frequencies; therefore the SNR is a good estimate of
total harmonic distortion. The analysis method takes the
RMS or peak-to-peak voltage of the signal, and divides it
by the RMS value of the noise. SNR is usually expressed
in dB with the formula below:
SNRRMS = 20 10910 SignalRMs
NoiseRMS
SNRpeak.RMS=2010g10 Sig~alRMs +9.0
NOlseRMS
8-8

Supply Current1 (lEE)
lEE is the current drawn by the device from the VEE
supply. Since lEE is referenced to a negative supply, it is
a negative valued parameter (current flows out of the
device). In Raytheon Semiconductor's bipolar converters,
lEE decreases with increasing temperature and is
measured with the maximum (most negative) rated VEE.
Supply Current (ISY)
The current required from the power supply to operate a
device under quiescent no-load conditions, expressed In
milliamps (mA).
Supply Voltage (Vs)
The range of power supply voltages over which a device
will operate, expressed in volts (V).
Supply VoHage (VEEA. VEED. VEE)
VEE is the negative supply voltage. On converters with
both digital and analog negative supplies, the analog
supply is denoted VEEA, and the digital supply is,VEEA.
Temperature Coefficient (TC)
The change in the output voltage over specified
temperature range in parts per million per °C (ppm/"C).
Temperature Coefficient (TCO)
TCO is the factor which linearly approximates the
variation with temperature of offset errors (EoT, Eos).
This is a first order approximation and the actual
temperature coefficient is a function of temperature
which may exceed the maximum of TCO in some
temperature ranges.
Transient Response (tm)
trR is the amount of time required for the converter to
recover from a full-scale input transition, before valid
data can be produced. The comparators in a flash NO
converter have a finite slew rate and a finite settling time.
If a device is presented with a full-scale input change

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For More Information, call 1-800-722-7074.

Section 8 - Glossary
(which exceeds that slew rate). it takes trR for the input
circuit to recover and provide accurate data.
Unity Closed

Loop Bandwidth (BW)

The frequency at which the small signal voltage gain is 3
dB below unity when operated as a closed loop unity
gain follower. expressed in Hertz (Hz).

Zero Scale Current
The leakage current flowing into the DIA converter output
with all logic inputs off and the output at a specified
voltage range. expressed in microamps (IJA).

References
[1] IEEE Standard Dictionary of Electrical and Electronic
Terms. IEEE Std 100-1977. p. 177.
[2] IEEE Standard Definitions of Terms Relating to
Television. IEEE Std 201-1979.
(3) F.A. Williams and R.K. Olsen. "Quantization Effects
on Differential Phase and Gain Measurements:
SMTE Journal. November 1982.
(4) The White Noise Book, M.J. Kent.

Bibliography
Gray, P.R., and R.G. Meyers. Analysis and Design of
Analog ICs. New York: Wiley. 1977.
Kester. Walter. "Characterizing and Testing AID and DIA
Converters for Color Video Applications." IEEE
Transactions on Circuits and Systems: July 1978.
p.539.
Liao. Samuel Y. Microwave Devices and Circuits. New
Jersey: Prentice-Hall 1980.
Pratt, William J. "Don't Lean on AID Converter Specs."
Electronic Design: April 1974. p. 80.
Smith. Bryan F. "Understanding High Speed AID
Converter Specifications." Computer Labs
Application Note. 1974.
Tewksbury. SK.K. et aI. "Terminology Related to the
Performance of SIH. AID and DIA Circuits." IEEE
Transactions on Circuits and Systems: July 1978.
p.419.
IEEE Broadcast Technology Society ·Proposed
Standard for Performance Measurements of ND and
DIA Converters for PCM Television Video Circuits.
Project No. 746."

For More Information, call 1-800·722·7074.

Raytheon Semiconductor

B·9

Section 8 -

Glossary
SYNlllESIZER

PULSE
GENERATOR

SYNTHESIZER

REFERENCE
REFERENCE
f- IN
SIGNAl
OUT
OUT

-

0

TRIGGER
IN

OSCILLOSCOPE

OUT

SIGNAl OUT

VIN

I
I
.;.N

I
CONY
INPUT
AID CONVERTER

C~

i

LOW PASS
FlTER

DlACONVERTER

Figure 1. Beat Frequency Test Set Up

A----

120IRE
UNITS
100
80

RAMP IS NOT
DEFINED IN

THIS PERIOD

o

Figure 2. Modulated Ramp Test Signal

4.2 MHz LOWPASS FILTER
TEST SIGNAL
GENERATOR

....

r-. CONVERTER .;.. CONVERTER
"'v
0(.,

AID

t

D/A

...

4.2 MHz LOWPASS FILTER

0(.,

"'v

t

FS (IF REQUIRED)

...

VECTORSCOPE

65-6425

Figure 3. Differential Gain and Phase, Test Set Up

8-10

Raytheon Semiconductor

For More Information, caD 1-800-722-7074.

Section 8 - Glossary
CENTER OF CODE

Differential Unearity Errror Test Method
Find maximum value of:
I(Slap size- LSB width) I
Divide above by LSB widlh
Nola: Step size is not !he same as
1he code size defined as Q.

' - SECTION OF AID TRANSFER FUNCTION

Figure 4. Differential Linearity Error

65-6427

Figure 5. Differential Non-Linearity Measurement

12
11

TERMINAL BASED ~
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Figure 6. AID Converter Transfer Function

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

8-11

Section 8 - Glossary

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8-12

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

Section 8 - Glossary

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Figure 10. Driving a Reference with the Sense Connection

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

8-13

Section 8 - Glossary

Video Terminology
AGC
Automatic Gain Control in a video system is a
circuit or subsystem that senses video amplitude
and automatically adjusts amplifier gain to
increase or decrease the video signal to the
desired level.
ALPHA-channel
a is a digital value (usually 8- or 10-bits,
normalized, and ranging from 0 to 1) that is
associated with the mixing of two video sources.
The value of a scales the magnitudes of input
video in the following mixer equation:
Mixed video = ( a )(Video #1) + ( 1-a )(Video #2)

a values are also associated with each RGB

Anti-aliasing Filter
A low-pass analog filter preceding an AID
converter. The purpose of this kind of filter is to
sufficiently attenuate frequency components
above the signal band of interest. If not
sufficiently attenuated, unwanted noise and high
frequency components will alias (mix)
themselves back into the critical frequency band,
and degrade AID conversion results. Since the
unwanted frequencies become mixed with the
wanted frequency band, it then becomes
impossible to separate the two later in the
system.
Aperture Delay, Error, Jitter, Uncertainty
Aperture is an analog-to-digital converter concept
referring to the window of time when the AID
converter is sampling and its input signal.

color pixel in graphics and imaging systems. a is
used to scale the intensity an image on a pixelby-pixel basis.

Aperture delay is the absolute time between the
clock edge that initiates the conversion cycle and
the time when the input signal is actually
sampled.

AM
Amplitude Modulation refers to adding low
frequency information to a high-frequency signal
by changing its amplitude in proportion to the low
frequency information. Amplitude modulation of
the color subcarrier frequency in video results in
the variation of color intensity (saturation).
Amplitude modulation of a carrier frequency is
the way the video portion of a television signal is
transmitted over an rf channel and is the basis of
AM radio.

Aperture Error, Jitter, and Uncertainty are
different terms for essentially the same thing.
They refer to the changes in Aperture Delay
exhibited on a sample-to-sample basis.
Excessive Aperture Error, Jitter, and Uncertainty
degrade AID converter dynamic performance
parameters such as SNR (signal-to-noise ratio).

APL
Average Picture Level is a video term that refers
to the variation in active video levels as the TV
picture changes from very dark to very light
scene content. Under normal operating
conditions, APL can vary widely and quickly,
burdening circuit elements such as AGC, clamps,
and DC-restore.

8-14

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For More Information, call 1-800-722-7074.

Section 8 - Glossary
Artifact
A video artifact is an unwanted characteristic of a
television picture due to noise, improper image
filtering, or timing errors.
Aspect Ratio
The ratio of picture width to picture height. For
NTSC and PAL, the aspect ratio is 4:3. The
aspect ratio for HDTV will be set at 16:9.

T

3 HIGH

B-Y
One of the "color-difference" signals derived from
matrix multiplying RGB values by various
constants. The other color-difference signal, (RY), is derived in conjunction with (B-Y).
B-Y = -0.299 R - 0.587 G + 0.866 B
Back Porch
The portion of the horizontal interval of a video
line beginning with the rising edge of Horizontal
Sync and ending with the beginning of active
video.
Back porch includes Breezeway, Color Burst,
and Color Back Porch.

Bandwidth
A range of frequencies over which a circuit or
system works without degrading. The bandwidth
ofNTSC video is approximately 4.2 MHz and 5.5
MHz for PAL, meaning that frequency
components from near-DC to the bandwidth limit
are normally expected to be present. For an ND
converter, bandwidth refers to the range of input

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frequencies over which the ND converter is to
accurately work without degrading the result.
Bandwidth Flatness
The flatness of a frequency band is the measure
of the variation of the amplitude of all frequencies
in the band of interest. In the NTSC video band
of 4.2 MHz, a flatness of +/-1 dB is considered to
be acceptable.
Baseband
Composite video normally occupies a frequency
span from near-DC to 4.2 MHz for NTSC and 5.5
MHz for PAL. When video is applied to an rf
modulator for transmission on a television
channel, the resulting AM modulated rf is no
longer baseband.
BetaCam
A combination VCR and color TV camera, carried
on one shoulder, used for recording local news
events or other video productions. BetaCam
offers much higher video quality than S-Video or
VHS .... but at a considerably higher price.
Black Balance
A color TV camera operation that examines the
red, green, and blue analog signal values from
the image sensor elements and adjust them so
that a true black signal (no Chrominance) results
when the camera is focused on a black object.
Black Burst
A compos~e video signal that carries with ~ all
Horizontal and Vertical Sync, Color Burst, and
Set-up (Pedestal) if applicable to the television
standard in effect. No active video is allowed in
Black Burst. See Black Level for waveform.
Black Level
Black level is the active video amplitude of a
black picture. In the NTSC television standard
used in the U.S., the black level is defined to be
7.5 IRE units above that of the blanking level.
The NTSC used in Japan and in PAL, the black
level is defined to be exactly the same as
blanking. The elevated black level is also known
as "setup" or "pedestal."

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U.S. NTSC "black"

8-15

Section 8 -

Glossary

Blanking
The video signal level of the Front Porch,
Breezeway, and Color Back Porch. The term
blanking refers to the shutting off of the red,
green, and blue CRT electron beams at the end
of each line and field allowing the sweep circuitry
to retrace and set up for the next line or field.
Blooming
A TV camera term where one or more of the red,
green, and blue image sensors overloads due to
excess light and causes the image to clip at its
maximum brightness. This was common before
the use of solid-state CCD image sensors.
Breezeway
That portion of a video horizontal interval
between the rising edge of Horizontal Sync and
the beginning of Color Burst.

subcarrier. Chrominance carries with it no
information about Sync or Luminance.
Chroma Bandwidth
Chrominance (the color component of video)
comprises a phase and amplitude modulated
subcarrier frequency. The span of frequencies
generated by phase and amplitude modulation of
the color subcarrier frequency is the chrominance
bandwidth. The NTSC chrominance bandwidth
is approximately 1.3 MHz on a 3.58 MHz
subcarrier.
Chroma Demodulator
Chrominance comprises a phase and amplitude
modulated subcarrier frequency that carrier with
it all color information for a video Signal. In video
processing, it is often necessary to extract color
information signals. A Chroma Demodulator
circuit provides color difference signals from
chrominance.

Breezeway
Chroma Key
Chroma key is a video special effect that allows
one image to be superimposed over another. A
foreground image is keyed over (switched in
place of) a background image wherever there is
a specific color (usually blue or green) found on
the foreground image.
Broad Pulse
Another term used for the Vertical Sync pulses
(between the strings of Equalizing Pulses) in the
Vertical Sync interval.
Burst Gate
A video system Signal that indicates the timing of
the Color Burst in the Horizontal Blanking
Interval.
CCD
Charge Coupled Devices are used for almost all
TV camera image sensing applications. A single
CCD is used in consumer quality CamCorders,
sensing the three primary colors, red, green, and
blue. In more expensive TV cameras, including
studio cameras, three separate CCDs sensitive
to red, green, and blue light capture the image.
CCIR
Comite Consultatif Intemational des Radiocommunications. The United Nations regulatory
body covering all forms of radio communications.
Chrominance
That component of a composite video signal that
contains only amplitude- and phase-modulated

8-16

Chroma Trap
A band rejection filter specifically designed to
reject the color subcarrier portion of a composite
video signal without altering the luminance
portion of the video.
Clamp
A circuit element in a video system that forces
the Front and Back Porch blanking level of
composite video to a specific desired voltage.
Normal composite video requires that the Back
Porch level be 0.0 Volts. Video transmission
lines are usually AC-coupled, causing the DC
reference to be lost. AID Converters may require
the Back Porch level to be at some other voltage.
Clamp circuits force composite video to the
prescribed levels.
Clipping
Under certain light conditions the "white" level of
composite video may exceed the maximum
allowable for transmission or processing.
Clipping circuits prevent video from exceeding
these limits.

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Section 8 - GlOSsary
Closed Captioning
Closed Captioning data is inserted and
transmitted on one of the Black Burst lines at the
top of each field. A Closed Captioning decoder
extracts that data, converts it to text, and
superimposes that text over the video program.
CLUT
A Color Look-Up Table is found on digital video
encoders, mixers, and RAMDACs. The CLUT is
a small block of high-speed RAM that maps pixel
input data to a specific color. The CLUT of a
typical VGA RAMDAC maps the 8-bit pixel data
into 256 different colors made up of 18-bits each
(6-bit red, 6-bit green, 6-bit blue).
Coaxial cable
The most common method of transporting
composite or serial digital video around a system
or studio is over a cable comprising a center
conductor and a surrounding grounded shield.
Low cost coaxial cables offer low loss, wide
bandwidth, and low noise video performance.
Color Back Porch
That portion of the Horizontal Sync interval
between the end of Color Burst and the
beginning of active video

Color Burst

Color Bars
A video test signal that displays eight vertical
bars of six fully-saturated colors plus black and
white. The six colors are the three primary colors
(red, green, and blue) and their three
complements (cyan, magenta, yellow).

W Y C G M R B Bk

For More Information, call 1-800-722-7074.

Color Burst
That portion of the Horizontal Sync interval after
Breezeway and before Color Back Porch. From
eight to eleven full cycles of color subcarrier
frequency define the Color Burst. The Color
Burst envelope has a specific shape, controlling
the growth and decay of the color subcarrier
waveform. Color Burst provides a subcarrier
reference for color demodulation.
Color Decoder and Color Demodulator
See Chroma Demodulator
Color Difference
Components of color based upon a matrix
multiplication operation on RGB values. (R-Y)
and (B-Y) color difference components can also
be visualized by mapping color vectors onto the
00 and 90 0 polar coordinate axes.
Color Encoder
The circuit element that outputs chrominance
from the two color difference Signals. This is the
opposite function of the color decoder.
Color Framing
A color frame in NTSC consists of four sequential
fields comprising all possible combinations of
Color Burst phase and vertical sequences. PAL
color framing is an 8-field sequence.
Color Killer
When incoming video in a video system does not
contain color information (monochrome, without
chrominance) there is no need to separate color
difference components from chrominance. the
color killer circuit detects the missing color burst
and disables the color decoder accordingly,
eliminating any color artifacts.
Color Purity
Color Purity is a measure of how close a specific
color comes to its target saturation and hue.
When displaying color bars on a vectorscope,
each of the six color vectors should be centered
in the graticule box that corresponds to its
saturation (chrominance amplitude) and hue
(chrominance phase angle with respect to color
burst).
On a television screen, color purity is a subjective
test. Color purity is best determined by painting
the entire screen with fully-saturated red.
Variations in the displayed color indicate misaligned electron guns or a magnetized shadow
mask in the picture tube.

Raytheon Semiconductor

8·17

Section 8 - Glossary

Color Space
The Chrominance component of composite video
is usually divided further into components of
color. The most common color components, or
color spaces, are (B-Y)(R-Y), CBCR, 10, UV, and
HS.
Colour
With all due respects to the Oueen, this word is
simply misspelled. It should be 'color', and
everybody knows what color is. Except, of
course, those who are blind or color-blind, and
then it really doesn't matter much, does it?
Comb Filter
A special filter used for separating chrominance
from composite baseband video. A comb filter is
a far better filter than a chrominance trap
because it can pick out chrominance components
that overlap into the luminance frequency band.
When plotted, the frequency response of this
kind of filter looks like the teeth of a comb.
Component
Composite video can be separated into
components. Horizontal and Vertical Sync
pulses, Luminance, and Chrominance
information combine to make composite video.
Chrominance can be further separated into color
difference signals such as (B-Y)(R-Y), CBCR, 10,
UV, etc.

Luminance of that pixel is represented by Y and
the color components of that same location are
CBCR. Therefore, it takes a complete set of
YCBCR data to completely define one pixel.
Cross-Color Distortion
Luminance information that is inadvertently
decoded as part of the Chrominance signal. For
example, vertical stripes on a coat can be
interpreted as subcarrier due to their relative
spacing when compared to the period of the
subcarrier frequency.
Cross-Luma Distortion
Chrominance information that is inadvertently
decoded as Luminance.
Crosspoint Switch
A switching or networking element in a video
system that interconnects any of x inputs to any
of y outputs. The Crosspoint switch is a key
element in a video production mixer or video
routing system. A 4x4 crosspoint switch array is
shown below.
Inputs

,

Contrast
The separation between the whitest white and
blackest black of an image. Low contrast images
look like they have a lot of gray in them.

,

,

Outpu ts

.

Composite Video
Composite video is the signal formed by
combining Horizontal and Vertical Sync, Color
Burst, Luminance, and Chrominance.
Contouring
An image artifact from limited gray-scale or color
resolution. Instead of gradual changes in color
shading, the image will have lines that resemble
the isobars on a weather map. Contouring is
usually not noticeable with 7 -bit or greater grayscale resolution.

rT

Crosstalk
The unwanted noise or distortion on a signal that
has been injected by other signals near the signal
being measured.
CVBS
An abbreviation for Composite Video Blank and
Sync. The CVBS bus is a high-speed data path
between video processors over which digital
composite video data is sent. Sync pulses and
blanking levels are later extracted from this data.

0-1
Co-site Sampling
When video is digitized, decoded, and then
transmitted in component form, pixels are
decoded into a set of components corresponding
to a single location on the displayed image. The

8-18

A digital video standard for YCBCR4:2:2
components sampled at 13.5 MHz. Digital video
is transmitted serially at 270 Mbit per second or
in 10-bit parallel format at 27 Mword per second.
D1 is also known as CCIR-601.

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Section 8 - Glossary
0-2
A worldwide standard for digital composite video
sampled at 4 x fSC (14.318 Msps for NTSC and
17.732 Msps for PAL).
Data Key
Digital Video Encoders like the TMC22190 offer a
feature that allows keying (pixel switching) by
matching input RGB color combinations with preprogrammed colors stored in the data key
register. When the input color does not match
the stored color, RGB input data is encoded.
Whenever the input color matches the stored
color, the encoder outputs video corresponding
to the data found on the CVBS bus.
DC-Restore
During video processing, the DC voltage level of
blanking, 0.0 Volts, may have been modified. DC
Restore circuits bring the blanking level back to
0.0 Volts for transmission. See also Clamp.
Decimating Filter
A digital filter that not only outputs data at a rate
lower that data in input (1/2 the rate for 2:1
decimation) but also attenuates unwanted image
artifacts caused by the decimation process.
Decoder
The process of extracting Luminance and color
difference components such as (R-Y)(B-Y) or
CSCR from composite video is the function of a
decoder. Various filtering techniques are also
employed in a decoder to accurately separate
Chrominance information from Luminance and
thereby improve picture quality.
Differential Gain
A video parameter that quantifies color accuracy
over the black-to-white Luminance range. Dg is
measured by superimposing a constant
amplitude subcarrier on a linear ramp or stairstep Luminance signal. The variation in the
amplitude of the subcarrier, dg, corresponds to
variations in color saturation.
Differential Phase
A video parameter that quantifies color accuracy
over the black-to-white luminance range. Dp is
measured by superimposing a constant phase
subcarrier on a linear ramp or stair-step
Luminance signal. The variation in the phase of
the subcarrier, dp, corresponds to variations in
color hue.

For More Information, call 1-I!00-722-7074.

Digitizer
Another term for Analog-to-Digital Converter
(AID) except that a digitizer will have circuit
functions like clamps, amplifiers, and other
elements necessary to complete the process of
converting composite video to digital data.
Dissolve
A controlled transition between two video
images. In a dissolve, the original image
decreases in amplitude at the same time as the
second image increases. The second image is
gradually superimposed over the original until it
dominates and there is no original image at all.
Doubly-Terminated
1. When terminating resistors are located at both
source and destination ends of coaxial cable.
2. When too many terminating resistors are
connected to a coaxial cable, attenuating the
video Signal.
Downstream Key
The last key source in a multilayer keyed
composite image. The Downstream Key places
the top-most image on the composite image.
Edge Rate
The rise and fall slopes of Horizontal and Vertical
Sync pulses, Color Burst envelope, and the
beginning and end of active video must be limited
and controlled to keep high-frequency
components from exceeding the channel
bandwidth.
Encoder
Encoders assemble composite video from its
components. For example, the inputs to an
encoder are Horizontal and Vertical Sync, RGB
or YCBCR component video, or color-index
values. The output is complete baseband
composite video including all H and V Sync
timing.
Equalization Pulse
A series of pulses in the Vertical Sync interval
just preceding and following the series of Vertical
Sync pulses.

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Equalization Pulses

8-19

Sect/on 8 - Glossary
Even Field
One of the two fields that make up each frame of
an interlaced video signal. Video "half-lines
appear at the end of each even field. See Field,
Odd Field
Fader
A video processing element that fades or
dissolves a video image to black (or from black).
Many consumer CamCorders have automatic
faders that operate at the touch of a button.
Field
In an interlace video system such as NTSC and
PAL, each frame of 525 lines (625 for PAL) is
made up of two fields of 262.5 line apiece (312.5
for PAL). In NTSC there are 59.94 fields per
second while PAL produces 50. But PAL
flickers, yes it does.
Field Sequence
The combination of Equalization Pulses, Vertical
Sync pulses, video half-lines, and Black Burst
lines (including VITS, SMPTE Time Code,
Closed Captioning, etc.) found between the last
active video line of one field and the first active
video line of the next field.
Field Tilt
A video parameter that indicates the drift or
change in blanking level from the beginning of a
field to the end of that field. Field tilt is usually
caused by inadequate back porch clamping of
the blanking level to 0.0 Volts.
Flat Field
A video test signal for measuring field and line
tilt. The flat field is either a full field of Black
Burst or a full field of constant gray or white (no
Chrominance).
FM
Frequency Modulation refers to adding lowfrequency information to a high-frequency signal
by changing its frequency in proportion to the low
frequency information. Modulation of the color
subcarrier frequency in SECAM video systems
results in changing the color intensity or
saturation. Frequency modulation of a carrier
frequency is the principle behind the transmission
of the audio portion of television programs over
an rf channel, and FM radio.

8-20

Frame
In an interlaced video system such as NTSC or
PAL, a frame is made up of two interlaced fields.
The frame rate for NTSC is 29.97 and 25.0 for
PAL, exactly 1/2 of the field rate.
Frame Store
A digital Video system that captures by digitizing
and writes into RAM all of the pixels comprising a
frame of video.
Front Porch
That portion of the Horizontal Sync interval after
the end of active video and before the falling
edge of Horizontal Sync.

Front Porch

Gamma
A mathematical correction factor, y, used to
compensate video systems for non-linearity such
as that found in optical image sensors and CRTs.
In the transfer function: Output = K (Input) 1fyy
introduces a non-linearity the compensates for
non-linearity associated with the input. Typical
values for yin NTSC and PAL are 2.2 and 2.8,
respectively.
Generations
When recording video on tape, each subsequent
copy of a copy of a copy is a generation. Digital
recording techniques and equipment permit many
more generation to be produced without
significantly degrading picture quality.
Genlocking
The video process of extracting Horizontal and
Vertical Sync from composite video for the

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For More Information, call 1-800·722·7074.

Section 8 - Glossary
purpose of synchronizing video cameras,
recorders, and other video processing systems.
Group Delay
A video parameter that compares the relative
propagation delay of different frequencies in the
video band. If, for example, low frequencies
such as 100 kHz have a significantly different
delay through a video filter or amplifier than the
color subcarrier frequency, 3.58 MHz (NTSC),
Luminance features of a picture will not align
themselves with the color of that feature. That
will look bad.
GRS
The Genlock Reference Signal includes
subcarrier frequency, subcarrier phase, and field
identification digital data. It is transmitted from
the TMC22070 Genlocking Video Digitizer to the
TMC22090 and 22190 Digital Video Encoders
over the CVBS bus during Horizontal Sync.
HDTV
High Definition TeleVision is a video technology
of the future which promises to dramatically
improve image quality by increasing signal
bandwidth as well as line and frame rates. HDTV
will require high-speed AJD and D/A converters
as well as very high speed digital video
processors. Also know as "Advanced
Television."
Horizontal Interval
The Horizontal Sync interval is the series of
signals between the end of active video of one
line and the start of video for the next line. It
includes the Front Porch, Horizontal Sync,
Breezeway, Color Burst, and Color Back Porch
(all of Back Porch).
Horizontal Sync
A negative-going pulse at the end of every line.
This pulse triggers CRT retrace and the
beginning of the next line.

HSI
Hue, Saturation, and Intensity color components.
These correspond closely to the controls found
on most TV sets: tint (hue), color (saturation),
brightness and contrast (intensity).
Hue

.
That characteristic of color that differentiates
Rosy Red from Vida Blue from Mellow Yellow. in
a polar coordinate vector display, hue
corresponds to the angle of the vector with
respect to the Color Bu rst.

Hum Bars
Noise induced from AC power line voltages may
appear as horizontal lines scrolling vertically in
the displayed image in NTSC. In PAL, hum bars
due to 50 Hz power will be stationary.

A serial 3-wire interface between integrated
circuits used to set-up and control those circuits.
Interlace
In NTSC and PAL video systems, an image is
scanned in two passes. The scanned lines of the
first pass (field) are interlaced with the lines of
the second pass. The interlaced lines do not
overlap each other, but rather fill in the space
between lines of the next pass.
Interpolation Filter
A digital filter that doubles the sampling rate of
the input data by calculating (interpolating) a new
data pOint on the basis of two or more sequential
input points. The new data point is inserted
between the input data points used for its
calculation.
IRE Units
The Institute for Radio Engineers developed a
scale for measuring video signal amplitudes.
Sync pulses are to be 40 IRE units in amplitude
and active video is limited to 100 IRE units. The
entire range of 140 IRE units was defined to be 1
Volt peak-to-peak. NTSC waveform monitors
usually have a graticule showing IRE units.
Jitter
See Aperture Jitter
JTAG
An integrated circuit test interface which allows
board level testing of all interconnections to a
large integrated circuit without testing the actual

For More Information. call 1-800-722-7074.

Raytheon Semiconductor

8-21

Section 8 - Glossary
function of the integrated circuit. See TMC22190
data sheet.
K-Iactor
A video parameter that is a measure of impulse
response of a video system.

Line Tilt
A video parameter that indicates the drift or
change in blanking or gray video level from the
beginning of a line to the end of that line. Line tilt
is usually caused by inadequate Back Porch
clamping of the blanking level to 0.0 Volts or to
short AC-coupling time constants.

Key

A video processing method for superimposing
one image over another. A key signal in the
shape of the image to be superimposed is used
to switch that image on in place of the
background image. The newsreader is "keyed"
over the city scene in the example below.

Linear Key
Similar to digital keying except that the transition
from background image to foreground image is a
ramp, over which the foreground image gradually
overwrites the background image. Same as "solt
keying".
Linear Phase
A characteristic of a video filter or amplifier that
ensures good group delay.

Lap Dissolve
Same as Dissolve. A controlled transition
between images when one gradually overwrites
(overlaps) the other.
Layer
When multiple key signals are used to build a
multiple level composite image by keys, wipes,
and dissolves, each component image is a layer.
Layering Engine
A circuit or system that accomplishes the
layering (keying) of several images to lorm a
single composite image. See TMC22190 data
sheet.
Line
Video images are scanned by optical sensors
from left to right, forming a line, repeating, one
line at a time to build a complete two-dimensional
image. Active video, Front Porch, Horizontal
Sync, Color Back Porch, and Color Burst
comprise each video line.
Line Rate
The number of video line scanned or displayed
per second. In NTSC there are 15,734 lines per
second, and 15,750 in PAL.

8-22

Linearity
A common system parameter that rellects the
system's ability to closely follow and process
input signals without adding errors and degrading
results. In video, linearity sometimes relates to
differential phase and differential gain
performance.
Luminance
The black-and-white components of a video
signal. When combined with Chrominance, the
result is composite video.
Make-belore-break
A term to describe the action of crosspoint
switches. When a switch transition is made from
one video source to another, it is important that
there be no period of time during which the
neither source is connected to the output.
"Make-belore-break" means that the new video
source connection is made to the output just
before the old video source disconnects.
Modulated Pulse
A video test waveform used in the testing of
Group Delay and YC gain matching. A
modulated pulse is a short period of subcarrier
that grows and decays according to a specific
pulse envelope.
Modulated Ramp
The video test waveform that is used in testing
differential phase and differential gain.

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Section 8 - Glossary

Modulation
Adding information to a signal. For example,
phase and amplitude modulation of the color
subcarrier to make Chrominance. Adding
Chrominance to Luminance is a Luminance
modulation process. TV transmitters are AM
modulated for video and FM modulated for audio.

Monitor
A television screen that accepts baseband
composite video and displays the image. A
monitor may be a subset of a TV receiver which
can also detect and demodulate the rf signal from
a television channel and display the image and
amplify the sound.

Multiburst
A video test waveform that includes short bursts
of several frequencies (1.0, 2.0 MHz etc.)
spanning the video band. When displayed on a
waveform monitor, Multiburst offers a quick look
at system frequency response by observing the
relative amplitude of each frequency burst with
respect to the others.

Multipulse
A video test waveform that includes series of
short modulated envelope pulses of varying
amplitudes, duration, and subcarrier frequency.
When displayed on a waveform monitor,
Multipulse offers a quick look at system pulse
response and group delay.

For More Information, caD 1-800-722·7074.

Noise
Any part of a video signal that is not desirable
and degrades the quality of the picture. Hum
bars, speckles, ghosts, zits, etc. combine to
reduce picture quality.
NTSC
A color television system developed by the
National Television Standards Committee that is
used in North America, Japan, and other parts 01
the world. NTSC is an interlaces system,
characterized by 59.94 fields and 29.97 frames
per second and 525 line per frame.

Odd Field
One of the two fields that make up each frame of
an interlaced video signal. See Field, Even Field
Overlay
A computer graphics operation where colored
text or patterns are written on top of a displayed
image without modifying that image. Most
RAMDACs and digital video encoders have
additional overlay color RAM annexed to the
CLUT for this purpose. Overlay is enabled on a
pixel-by-pixel basis and the color of the overlay
depends only upon the overlay RAM location
addressed and the color value stored in that
address.
Oversampling
Whenever a Digitizer of AID Converter is clocked
at a rate that is far in excess of the Nyquist
criteria (>2x required bandwidth) the system is
said to be oversampled. Oversampling in video
systems relaxes the anti-alias filter cut-off
requirements and reduces system cost. An
oversarnpling AID converter may be followed by
a decimation filter to minimize the data
bandwidth.
PAL
A color television system (Phase Alternate Line)
used in Europe and other parts of the world.
PAL is an interlaces system, characterized by 50
fields and 25 frames per second and 625 line per
frame.

Raytheon Semiconductor

8·23

Section 8

Glossary
PM
Phase Modulation refers to adding low frequency
information to a high-frequency signal by
changing its relative phase in proportion to .the
low frequency information. Phase modulation of
the color subcarrier frequency in video results in
changing the color hue.

Pedestal
In NTSC systems, the blanking level of
composite video is 0.0 Volts while the "black"
color level is defined at +7.5 IRE units (+53 mV).
This small difference between blanking and black
is intended to completely cut off the CRT beam in
the TV during retrace. PAL systems do not
employ Pedestal (same as Setup).
Phase
The offset in time between two sinewaves of
exactly the same frequency. Phase is usually
expressed in degrees with 360 degrees of phase
between sine peaks.

Pulse Bar
A video test waveform that includes short pulses
and black-to-white transitions.

Phase-Lock Loop
In general, a phase-lock loop is a frequency
synthesizer whose output is continuously
compared to and varied according to some
incoming reference frequency.
In video applications, phase-lock loops are used
to generate a stable subcarrier frequency using
incoming color burst as the phase and frequency
reference signal. They are also used to generate
AJD converter clock frequencies using the line
scan frequency as the reference.
Pipeline Latency
In a digital system or processor, there is a period
of time between the entering of data into the
system and the emerging of processed data
corresponding to that data. This time inteNal is
usually divided into discrete time elements or
clock periods which control the processing
operations. Latency is the number of clock
cycles between the input and the result based
upon the inputs.
Pixel
The most basic element of an image. When
digitized, each video line is divided into discrete
elements, pixels, which are characterized only by
position and color. Images are a collection of a
number of pixels per line and lines per frame.

8-24

QAM
In video processing, Quadrature Amplitude
Modulation is the process of applying the color
component signals (U and V) to amplitude and
phase modulate the color subcarrier, producing
Chrominance.
Raster
A term used to describe the horizontal and
vertical scanning of the electron beams in a TV
or other CRT display.
R-Y
One of the "color-difference" signals derived from
matrix multiplying RGB values by various
constants. The other color-difference Signal, (BY), is derived in conjunction with (R-Y).
R-Y = 0.701 R - 0.587 G - 0.114 B
Reconstruction Filter
An analog filter used to smooth the transitions
between discrete analog voltages produced by a
Digital-to-Analog converter (D/A) when
reconstructing wideband signals such as video.
The filter must have good group delay
characteristics as well as adequate attenuation of
frequencies beyond the video band.
RGB
The most base components of color, the primary
colors Red, Green, and Blue. Combining all
possible intensities of red, green, and blue light
sources produces an infinite number of visible
colors.

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Section 8 - Glossary
Routing
The interconnection and distribution of video
signals throughout a video system such as a
production studio or television station. Video
sources and destinations are usually routed
through the use of crosspoint switches.
RS-170A
A Television Standard specification that defines
and describes the signal characteristics of NTSC.
See SMPTE 170M.
S-Vldeo
A baseband video standard that keeps
Luminance
separate from Chrominance. S-Video
connectors and cables carry two video signals,
one for Luminance and the other for
Chrominance.
Sample-and-Hold
A circuit element that acquires an analog signal
by sampling that signal and then holds the DC
level of that signal at the time it was sampled. A
sample-and-hold is usually found at the front end
or internal to NO converters. They hold the ND
input steady while the digital equivalent to the
held DC level is determined.
Saturation
The characteristic of color that differentiates
Navy Blue from Baby Blue, Blood Red from Pink,
and Kelly Green from Mint Green.
SCH Phase
SCH is the SubCarrier phase relationship
between the falling edge of Horizontal Sync and
the phase angle of the Color Burst. Whenever
video signals are mixed, it is very important that
the SCH characteristics of the two video signals
be matched. If SCH errors are present, the
mixed video will suffer from incorrect colors and
horizontal spatial shifts.

SECAM
A television system primarily used in France,
China, Soviet Union (R.I.P.), and the middle

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East. SECAM is similar to PAL except that the
color subcarrier is frequency modulated instead
of phase modulated for varying color hue. This
renders SECAM completely incompatible with
PAL and NTSC.
Serial Digital
A digital communication standard that sends
digitized video (and audio) through 75 Ohm
cables at 270 Mbits per second conforming to
CCIR-601 specifications. Serial Digital is
becoming the studio interconnection standard.
Serration
The series of Equalization and Vertical Sync
pulses found between fields in the vertical
interval.
Setup
In NTSC systems, the blanking level of
composite video is 0.0 Volts while the "black"
color level is defined at +7.5 IRE units (+53 mV).
This small difference between blanking and black
is intended to completely cut off the CRT beam in
the TV during retrace. PAL systems do not
employ Setup (same as Pedestal).
Short time Distortion
SO is a video parameter that describes the
character of fast changing Luminance in video.
Rise time, fall time, overshoot, undershoot,
ringing, and damping of fast edges are compared
to ideal transitions for the measurement.
Sine-Squared Pulses
A pulse and fast edge video test signal that is
band limited within the limits of the baseband
composite video. In NTSC systems, rise and fall
times of Sine-squared pulses are limited to 125
nanoseconds. The limits are 100 nanoseconds
in PAL.
Skew
The actual difference in time of two or more
events that are ideally supposed to be
simultaneous. For example, the data sent out
from an NO converter are ideally supposed to
change simuttaneously, but may not. Luminance
and Chrominance outputs of encoders and RGB
outputs of RAM DACs are ideally supposed to be
simuttaneous. There may be, however, a small
skew between these signals.
SMPTE
SOCiety for Motion Picture and Television
Engineers.

Raytheon Semiconductor

8-25

Section 8 - Glossary
SMPTE-170M
An NTSC video standard developed by SMPTE
that replaces RS-170A.
SMPTE Time Code
A digitally coded set of data usually found in
vertical interval line 19 that indicates the hour,
minute, second, and frame number of video.
SMPTE Time Code is extensively used in
videotape editing and in record keeping. It may
also be encoded on the audio track of videotape
(linear time code).
SNR
Signal-to-Noise Ratio is the ratio in decibels (dB)
of the wanted signal amplitude to the unwanted
noise in a video signal.
Soft Key
A key transition between a foreground image and
a background image during which there is a
controlled gradual transition instead of a switched
instantaneous transition. See also Key, Layer
Square Pixel
When a video line is digitized and divided into
discrete picture elements that have equal
horizontal and vertical dimension with respect to
the displayed image, the pixels are "square." A
circle displayed 100 pixels high and 100 pixels
wide will be round, not egg shaped.
Stair Step
A video test signal that ramps Luminance from
black to white using 5 or 10 discrete DC levels
(steps). Stairstep waveforms with constant
amplitude and phase subcarrier added are
sometimes used in differential gain and
differential phase measurements.
Subcarrier
A high-frequency signal, added to the Luminance
component of video that carries with it all color
information. In NTSC, the subcarrier frequency
is 3.579545 MHz and in PAL the frequency is
4.433618 MHz. Amplitude modulation (AM) of
the subcarrier results in changes in color
saturation while phase modulation (PM) of the
subcarrier results in changes in hue.
Subcarrier Phase
The phase of subcarrier with respect to a
reference subcarrier (i.e. color burst).

SVGA
Super VGA is a computer CRT display standard
that employs 600 or more horizontal lines and
800 or more pixels per line. It is contrasted with
VGA which employs 480 lines and 640 pixels per
line. SVGA offers higher CRT resolution than
VGA. The common SVGA resolutions are:
600 x 800, 768 x 1024, and 1024 x 1280.
SVHS
Super VHS is a VCR recording standard that
separates the Luminance (V) from Chrominance
(C) and records both of these Signals on tape.
SVHS cassettes are similar to VHS cassettes but
SVHS will not playback on regular VHS VCRs.
Sweep
A term used to describe the horizontal and
vertical scanning of the electron beams in a TV
or other CRT display. Sweep can also refer to
the change or span of frequency in a video test
signal.
Sync
An abbreviation that refers to the set of horizontal
and vertical synchronizing pulses that indicate
beginning of image lines and fields.
Sync Separator
A video processor that detects composite sync
pulses and outputs separate horizontal and
vertical sync pu Ises.
Sync Tear
An undesirable effect when a monitor input is
switched between two asynchronous video
sources. Sync tear occurs when video sources
that are not genlocked are mixed or switched.
Sync Tip
The most negative voltage level of the video
signal during the Horizontal and Vertical Sync
pulses.
Termination
The resistive load placed at the source and/or
destination end of a coaxial cable to ensure
maximum signal integrity, proper impedance
matching, and amplitude.
Tilt
See Field Tilt and Line Tilt
Time-Base Corrector
A video processing system that corrects
variations in line and field timing due to video

8-26

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Section 8 - Glossary
tape recorder head speed variations. These
systems are also known as TBCs.
Tint

Vertical Sync
A series of negative-going pulses at the end of
every field. These pulses trigger CRT vertical
retrace and the beginning of the next field.

Same as Hue. That characteristic of color that
differentiates Rosy Red from Ira Blue from
Mellow Yellow. In a polar coordinate vector
display, hue corresponds to the angle of the
vector with respect to the Color Burst.
Vector
A vector is a quantity that has both magnitude
and direction. In video, colors are represented
by vectors in polar coordinates. Magnitude
corresponds with the level of saturation and the
direction of the vector corresponds to hue.

Vectorscope
A video test instrument that analyzes color
subcarrier characteristics by displaying them on a
polar coordinate scale as vectors. A
Vectorscope can also display color components
such as (R-Y) (B-Y), YIQ, RGB etc.

VGA
A common computer video display characterized
by 480 line per frame and 640 pixels per line,
non-interlaced.
VITS
Vertical Interval Test Signals may have many
purposes, primarily in-service studio and
transmitter testing and automatic receiver
adjustment. VITS information is inserted in place
of the Black Burst lines at the top of each frame.
VM700
A video measurement test instrument made by
Tektronix. This instrument is the industrystandard for measuring video parameters.
Waveform monitor
A video test instrument that displays the line and
field waveforms of video signal.
White
The on-screen color resulting from the red,
green, and blue color components being active
and at their full-scale value. White is the
brightest value of Luminance.

Vertical Interval
The combination of Equalization pulses, Vertical
Sync pulses, video half-lines, and Black Burst
lines (including VITS, SMPTE Time Code,
Closed Captioning, etc.) found between the last
active video line of one field and the first active
video line of the next field.

For More Information, call 1-800-722-7074.

White Balance
A color TV camera operation that examines the
red, green, and blue analog signal values from
the image sensor elements and adjust them so
that a true white signal (no Chrominance) results
when the camera is focused on a white object.
Wipe
A wipe is a video production term that refers to
the transition from one video source to another.
During a wipe operation, the screen is split in
various patterns, uncovering the new video
source while covering the old source. In the
example below, the golfer shares a split-screen
wipe with a desert scene.

Raytheon SemIconductor

8-27

Section 8 - Glossary
25 Hz Offset
In most PAL standards, the subcarrier frequency,
fsc and the horizontal line frequency, fH, are
related by:
fSC = ( ( 1135 1 4 ) + ( 1 1 625 ) ) fH
The factor (1/625) adds 25 Hz the PAL subcarrier
frequency. This offset masks the residual
subcarrier dot pattern (sometimes seen on blackand-white displays) by causing the dot pattern to
move, making it less visible ..

v
The Luminance component of video. For
example, the Y in YCBCR, YIQ, YUV all refer to
the Luminance or black-and-white component of
the color video signal. Y is calculated from red,
green, and blue values by:

Y = 0.299 R + 0.587 G + 0.114 B
YC
A video component set which separates
Luminance (Y) from Chrominance (C). S-Video
is based on YC components. The Luminance
signal is all that is displayed on a black-and-white
TV or monitor.
YCBCR
A common color component set derived from
Y(B-Y)(R-Y) components which, in turn, are
derived from RGB values. YCBCR is the
component set used in CCIR-601 and 0-1 video
standards.

via
Another color component set similar to YCBCR
except rotated through a different vector
baseline. YIQ is most commonly associated with
NTSC.

VUV
A modified video component set, similar to
YCBCR. In YUV, UV are scaled in order to
prevent overmodulation of the subcarrier
modulator in an encoder.

2:1 :1
Similar to 4:2:2 except at 1/2 the data rate. 2:1:1
is used in teleconferencing where video is sent
over telephone lines.

8-28

4-field sequence
A complete field sequence for NTSC which
includes all Color Burst phase and vertical
interval sequences consists of 4 fields.
4x subcarrier sampling
Digitizing composite video at a rate (frequency)
equal to exactly four time the color subcarrier
frequency (14.318181 MHz for NTSC and
17.734472 MHz for PAL).
4:1 :1
This suffix, when added to YCBCR
(YCBCR4:1:1) indicates that for every 4 samples
of Luminance data (Y) there is only one sample
of CB and CR data available.

4:2:2
This suffix, when added to YCBCR
(YCBCR4:2:2) indicates that for every 4 samples
of Luminance data (Y) there are 2 samples of CB
and 2 samples of CR data interleaved.
4:4:4
This suffix, when added to YCBCR or RGB
(YCBCR4:4:4, RGB4:4:4) indicates that for every
4 samples of Luminance data (Y) or R there are
4 samples of CB or G and 4 samples of CR or B
data.

601
Refers to the CCIR Recommendation 601-1,
which describes and defines "Encoding
Parameters of Digital Television for Studios."

a-field sequence
A complete field sequence for PAL which
includes all Color Burst phase and vertical
interval sequences consists of 8 fields.

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

SectIon 8 - Glossary
For further reading and study on VIDEO:
•

CCIR 601-1 "Encoding Parameters of Digital Television for Studios"

•

CCIR 624-3 "Television Systems"

•

Craig, Margaret, "Television Measurements - NTSC Systems", Tektronix 1780R instrument literature

•

Craig, Margaret, "Television Measurements - PAL Systems", Tektronix 1781 R instrument literature

•

Hutson, G.H., Shepherd, P.J., Brice, W.S., "Colour Television", McGraw-Hili Berkshire, England (1990)

•

IEEE Standard Dictionary of Electrical and Electronic terms", John Wiley & Sons, New York (1972)

•

Jack, Keith, "Video Demystified", High Text Publications, Solano Beach, California (1993)

•

Roberts, R.S., "Television Engineering - Broadcast, Cable, and Satellite Part 1: Fundamentals", Pentech Press,
London (1985)

•

Roberts, R.S., "Television Engineering - Broadcast, Cable, and Satellite Part 2: Applications", Pentech Press,
London (1985)

•

SM PTE 170M Proposed SM PTE Standard for television - Composite analog video signal - NTSC for studio
applications.

•

Stafford, R.H., "Digital Television", John Wiley & Sons, New York (1980)

•

Watkinson, John, "The Art of Digital Television", Focal Press, Oxford (1990)

For More Information, cal 1-800-722-7074.

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8-29

SectIon 8 - Glossary

8-30

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For More Information. call 1-800·722·7074.

Section 9 - Ordering Information" Packaging

Section 9
Ordering Information
& Packages
Contents
Product Ordering Information .....................•.•......................•........•...••..................•...........................................2
Packaging Information .........................................•............•..............•......•.....•....•.............................................9
68-Contact Hermetic Ceramic Chip Carrier ......•.•..............................................................................9
A1
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B4
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BS
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B9
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G5
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GS
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H5
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H7
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JO
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J5
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J6
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J7
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JS
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For More Information, can 1-800·722·7074.

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Section 9 - Ordering Information" Packaging
24-Lead Plastic Dualln-Une Package .300" ...................................................................................47
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40-Lead Plastic Dualln-Une Package ............................................................................................49
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20-Lead Ceramic Dualln-Une Package ..........................................................................................63
D-24
24-Lead Ceramic Dualln-Une Package (0.3" Wide) .......................................................................64
D-24W 24-Lead Ceramic Dualln-Une Package (0.6" Wide) .......................................................................65
F-16
16-Lead Ceramic Gull Wing Flat Pack ............................................................................................66
F-24
24-Lead Ceramic Flat Pack (Cerpak) Package ...............................................................................67
F-24B 24-Lead Ceramic Bottom-Brazed Flat Pack Package .....................................................................68
L-20
20-Pad Leadless Chip Carrier .........................................................................................................69
L-28
28-Terminal Ceramic Leadless Chip Carrier ...................................................................................70
M-8
8-Lead Plastic Small Outline Dual In-Line Package .........................................................................71
M-14
14-Lead Plastic Small Outilne Dualln-Une Package .......................................................................72
M-16
16-Lead Plastic Small Outiine Dualln-Une Package .......................................................................73
24-Lead Plastic Small Outiine Dualln-Une Package .......................................................................74
M-24
N-8
8-Lead Plastic Dualln-Une Package ..............................................................................................75
N-14
14-Lead Plastic Dualln-Une Package ............................................................................................76
N-16
16-Lead Plastic Dual In-Une Package ............................................................................................77
N-20
20-Lead Plastic Dual In-Une Package ............................................................................................78
N-20W 20-Lead Plastic Dualln-Une Package (0.6" Wide) ••••••••••••••.••.••.••••••••••••••••••••••••••••••••••••••••••••••••••.•• 79
N-24N 24-Lead Plastic Dual In-Line Package (0.3" Wide) ..........................................................................80
S-16
16-Lead Ceramic Sidebraze Dualln-Une Package ......................................................................... 81
20-Lead Ceramic Sidebraze Dual In-Line Package ......................................................................... 82
S-20
S-24
24-Lead Ceramic Sidebraze Dualln-Une Package (0.3" Wide) ....................................................... 83
T-8
8-Lead TQ-99 Metal Can ................................................................................................................84
9-Lead TQ-66 Metal Can ................................................................................................................85
T-9
T-10
10-Lead TQ-100 Metal Can ............................................................................................................86
N2
N4
N5
N6
N7
N8
N9

9-2

Raytheon Semiconductor

For More Information, call 1-800-722·7074.

Section 9 - Ordering Information & Packaging

Product Ordering Information

Dual & Quad
Transistors
Dual or Quad

Prefix
SP

T

6-Pin
Dual Flatpak (TO-89)

QF

14-Pin
Quad Flatpak (T0-86)

QD

14-Pin
Quad, DIP, (TO-116)

Suffix
QD

1

Device Type

F

Device
2484

~97

TDCITMC/MPY

8M..

T

TMC

2210

Nn*

C

1

Device Family - - - - - - - - - '
TDC/TMC/MPY

Device Number - - - - - - - - - - - - - '
Package - - - - - - - - - - - - - - -.......
Temperature Range & Screening - - - - - - - - - - - - '
A =High Reliability. TC =-55°C to +125°C
B =Industrial. TC =-25°C to +85°C
C - Commercial. TA. O°C to +70°C
F - Extended Temp. Range. TC =-55OC to +125°C
V = MIL-STD=883. Level B. TC =-55°C to +125°C

Electrical Variation - - - - - - - - - - - - - - - - - - - - '
(OptionaQ
On - Refer to product listing for second digit

For More Information. caD 1-800·722-7074.

Raytheon Semiconductor

66-6398

9-3

Section 9 - Ordering Information & Packagtng

L

R29681ADMS
Prefix

I

_ _ _ _ _ _ _.....1

Bipolar PROM Family
6 =Bipolar PROMs
7 =Enhanced Bipolar PROMs

Screening

/883B =MIL-STD-S83, Class B
S = MIL-8TD-883, Level S

Temperature Code

M - Military Temp Product
(-55°C to +125°C)

Memory Size
2 - 512 x S (4K»
3 = 1024 x S (SK)
5 2048 x 4 (SK)
7 4096 x S (32K)
S .. 2048 x S (16K)

=
=

*Package Type

9 =S192 x S (64K)
Product Type
1 =Standard PROM

3

Performance

A = Speed Option

=Power-Switched PROM

JAN Linear
Prefix: LH/LT
Device Type

Blank .. Standard Speed

MM

T

0741

DC

A

T

Package Code
Lead Finish
65-6399

94

Raytheon Semiconductor

For More Information, caD 1-800-722-7074.

Section 9 - Ordering Information & Packaging

JAN PROM

JR

Prefix _ _ _ _ _ _T...J
Device type

29631

DR·

J

PackageCode-------------------...J
*All devices supplied with solder dip lead finish
65-6400

RC/RMJRV Series
Temperature Range

RM

4558

A

Dn

1883B

T

RC = Commercial, O°C to +70°C
RM = Military, -55°C to +125°C
RV - Industrial, -25°C to +85°C

Basic Part Type - - - - - - - - - - - - - '
Four digits max
Electrical Grade -----------------------------'
See data sheet

Package Type· ------------------------------------'
High Reliability Processing - - - - - - - - - - - - - - - - '
(Optional)
·Second digit is optional. Refer to product listing.
65-6401

For Mora Information, call HIOO·722·7074.

Raytheon Semiconductor

9·5

Section 9 - Ordering Infonnatlon & Packaging

LMILP Series

LM

Prefix: LMILP

T

124

T

D

A

/883B

~

Basic Part Type &
Temperature Range

First digit denotes temperature range·
1 = Military, -55°C to +125°C
3 - Commercial, O°C to +70°C

Electrical Grade - - - - - - - - - - - - '
See data sheet

Package Type - - - - - - - - - - - - - '
High Reliability Processing ---------~
(Optional)
·Except LM1851 operational temperature range .. -40°C to +70°C

LT·

1001

T-'

J.

LHILT Series
Prefix: LHILT ____

A

D

65-6402

1883B

Basic Part Type _ _ _ _ _ _
Four digits max

Electrical Grade - - - - - - - - - - '
See data sheet

Package T y p e - - - - - - - - - - - - - - '
High Reliability Processing - - - - - - - - - - - - '
(Optional)
65-6403

9-6

Raytheon Semiconductor

For More Information, call 1-800·722·7074.

Section 9 - Ordering Information &Packaging

TT
REF

REF Series

Prefix

01

x

o

1883B

Basic Part Type - - - - - -.....

Electrical Grade - - - - - - - - - - '
See data sheet

Package T y p e - - - - - - - - - - - - - - '
High Reliability Processing - - - - - - - - - - - - '
(Optional)
65-6404

07

OP-

OPSerles

T-I

~

Prefix _ _ _ _ _ _
Basic Part Type _ _

A

o

1883B

T
..

___

Electrical Grade - - - - - - - - - - '
See data sheet

Package Type _ _ _ _ _ _ _ _ _ _ _----J
High Reliability Processing

-------------1

(Optional)
65-6405

For More Information, cal 1-800·722·7074.

Raytheon Semiconductor

9·7

Section 9 - Ordering Information Be Packaging

DACSeries

DAC-

Prefix _ _ _ _ _ _T.....I
Basic Part Type

T
08

x

D

1883B

------.....1

Four digits max

Electrical Grade _ _ _ _ _ _ _ _ _..J
See data sheet

Package Type _ _ _ _ _ _ _ _ _ _ _---...l
High Reliability Processing

----------.....1

(Optional)
65-6406

9-8

Raytheon Semiconductor

For More Information, caD 1-800-722-7074.

Section 9 - Ordering Information & Packaging

A1

S8-Lead Hermetic Ceramic Chip Carrier
JEDEC Type A
Dimensions
Sym
A
AI
81

0
0,
02
03
e
h

Min
.075
.050
.033
.940

(1.90)
(1.27)
(0.84)
(23.88)

Inches (Millimeters)
Max
.110
.070
.039
.960

(2.79)
(1.78)
(0.99)
(24.38)
.075
.800
.400
.050
.050
.040

i
L
N

Notes

.040 (1.02)

Note 3
(1.90) Ref.
(20.32) Basic
(10.16) Ref.
(1.27) Basic
(1.27) Ref.
(1.02) Ref.

.055 (1.40)
68, Note 4
17, Note 5

NO
Ref. 90X00181
Notes:

1. A pin one identifier shall be located adjacent to pin one and within the
shaded area shown.
Dimension e: each pin centerline shall be located within .007 inch
(O.lBmml of its true longitudinal position.

3. Dimension 0: exclusive of package anomalies (lid misalignment,
ceramic particles, etc.l. Such anomalies shall not exceed .0lD inch
(0.25mml
4. Dimension N: number of terminals.
5. Dimension NO: number of terminals per package edge.
6. Controlling dimension: inch.

PIN , IDENTIFIER

,-- - - - - - --- -

---,

Top View
Cavity Down

,------------

For More Information call 1-800-722-7074.

Raytheon Semiconductor

9-9

Section 9 - Ordering Information & Packaging

24-Lead Ceramic Dual In-Line Package

82

Dimensions

Notes:

A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2

Dimension e: each pin centerline shall be located within .010 inch
(0.25mml of its true longitudinal position relative to pins' and N
(N =lead countl

3. Dimensions E, and eA: measured with leads perpendicular to the base
plane.
4. Dimensions E" eB and ee: measured to outside edge of lead.
5. Dimension eA: measured to lead center.
6.

Dimensions D and E: inclusive of package anomalies (lid misalignment,
ceramic particles, etcl Such anomalies shall not exceed .0'0 inch
(0 25mml

Dimension N: number of leads.
Controlling dimension: Inch.

~::::::::: lJ
PIN 1 IDENTIFIER

Inches (Millimeters)
Max

A
b

,150 13,811
,014 10.361

.200 15,081
,023 10.581

b,
b2
c
0

.050 11.271

.070 11.781

E
E,

.015
1.280
.305
.320

10.381
132.511
17.751
18.131
.100 12.541 Basic
.300 17.621 Basic

.400 110.161
.125 13.171

.200 15.081
.060 11.521

Q,

.015 10381
.070 11.781

8
8,

.005 10,131

Q

1-

Notes

.040 11.021 Nominal
.008 10.201
1.235 131.371
.28017.111
.300 17.621

eA
eB
eC
L
N

9. Standard lead finish is tin plate for all grades.
, O.

Min

e

7. Dimensions b, b, and c: increase maximum limits by .003 inch
(O.OBmml when solder finish applied.
B.

Sym

24, Note 8

.098 12.491

Ref.90X00181

I-------~D------_I

20102A

9-10

Raytheon Semiconductor

For More Information call 1-800-722-7074.

SecUon 9 - Ordering InfonnaUon &Packaging

83

20-Lead Ceramic Dual In-Line Package
Dimensions

Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .010 inch
10.25mml of its true longitudinal position relative to pins 1 and N
IN ~ lead countl.
3. Dimensions El and eA: measured with leads perpendicular to the base
plane.
4. Dimensions E1• eB and eC: measured to outside edge of lead.
5. Dimension eA: measured to lead center.
6. Dimensions D and E: inclusive of package anomalies lIid misalignment.
ceramic particles. etc.l. Such anomalies shall not exceed .010 inch
10.25mml.
7. Dimensions b. b1 and c: increase maximum limits by .003 inch
10.OSmml when solder finish applied.
S. Dimension N: number of leads.
9. Standard lead finish is tin plate for all grades.
10. Controlling dimension: inch.

~;~;:~)I

Sym

Min

Inches (Millimeters)
Max

.150 (3.81)
.015 (0.38)
.050 (1.27)

.200 (5.08)
.021 (0.53)
.060 (1.52)

.008 (0.201
.220 (5.591
.'90 (7.37)
.090 (2.291

.012
.985
.310
.320
.110

IB

.310 (7.781

.410 (10.411

ee
L
N

.125 (3.171

.200 (5.081

Q

.020 (0.511

.060 (1.521

A
b
b1
b2

c
0
E
E1

e

Notes

.040 (1.02) Nominal
(0.31)
(25.021
(7.871
(8.13)
(2.791
.300 (7.621 Basic

eA

20, Note 8

Q1

s
S1

.060 (1.521
.005 (0.131

Ref. 90X00181

~-------D--------~'I
\r-:~~======~H~~n~NGU~~E~

Qt

_____~II~~~~

ec-~::=j

For Mont Infarmalion call 1-800-722-7074.

Raytheon Semiconductor

20103A

9-11

Section 9 - Ordering Information & Packaging

a-Lead Dual In-Line Package

84

Dimensions

Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .010 inch
(0.Z5mm) of its true longitudinal position relative to pins 1 and N
(N=lead count).
3. Dimensions El and eA: measured with leads perpendicular to the base
plane.
4. Dimensions E1, e8 and ee: measured to outside edge of lead.
5. DimenSion eA: measured to lead center.
6. Dimensions 0 and E: inclusive of package anomalies [lid misalignment,
ceramic particles, etc.). Such anomalies shall not exceed .010 inch
(0.25mm).

7. DimenSions b, b1 and c: increase maximum limits by .003 inch
(O.OSmm) when solder finish applied.
S.

Dimension N: number of leads.

9. Standard lead finish is tin plate for all grades.
10. Controlling dimension: inch.

Sym
A
b
b,
b2
c

Min

Inches (Millimeters)
Max

.150 (3.81)

.200 (5.08)

.015 (0.38)
.030 (0.76)

.021 (0.53)
.070 (1.78)

.008 (0.20)

.012 (0.31)

.040 (1.02) Nominal

D
E
E,

.220 (5.56)
.290 (7.37)

.291 (7.39)
.320 (8.13)

e

.090 (2.29)

.110 (2.79)

eA
eB
eC
l
N
Q

Notes

.400 (10.16)

.300 (7.62) Basic
.310 (7.78)
.125 (3.17)

.200 (5.08)

.020 (0.51)

.060 (1.52)

.410 (10.41)

8, Note 8

Q,

s
S,

.055 (1.40)
.015 (0.38)

Ref. 90X00181

9-12

Raytheon Semiconductor

For More Information call 1-800-722-7074.

SecUon 9 - Ordering Information 8& Packaging

85

4O-Lead Ceramic Dual In-Line Package
Dimensions

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .010 inch
10.25mml of its true longitudinal position relative to pins 1 and N
IN =lead countl.
3. Dimensions El and eA measured with leads perpendicular to the base
plane.
4. Dimensions E1. eB and ee: measured to outside edge of lead.
5. Dimension eA: measured to lead center.
6. Dimensions D and E: inclusive of package anomalies lIid misalignment.
ceramic particles. etc.l. Such anomalies shall not exceed .010 inch
10.25mml.
7. Dimensions b. b1 and c: increase maximum limits by .003 inch
10.08mml when solder finish applied.

Notes:

8. Dimension N: number of leads.
9. Standard lead finish is tin plate for all grades.
10. Controlling dimension: inch.

Sym
A
b

b,
b2
c
D

E
E,
e

Inches (Millimeters)
Max

Min
.150 (3.81)
.014 (0.36)
.050 (1.27)

Notes

.225 (5.72)
.023 (0.58)
.065 11.65)
.040 (1.02) Nominal

.008 (0.20)
2.030 (51.56)
.510 (12.95)
.590 (14.99)

.015
2.096
.600
.620

(0.38)
(53.24)
(15.24)
(15.75)
.100 (2.54) Basic
.600 (15.24) Basic

eA
eB

.700 (17.78)

Be
L

.125 (3.17)

.200 15.08)
.060 11.52)

Q,

.015 (0.38)
.070 (1.18)

5
5,

.00510.13)

40, Note 8

N
Q

.098 12.49)

Ref. 90XOOl al
40

21

T
E

20

1

PIN 1 IDENTIFIER

20105A

For More Information call 1-4100·722·7074.

Raytheon Semiconductor

9-13

Section 9 - Ordering Information & Packaging

28-Lead Ceramic Dual In-Line Package

86

Dimensions

Notes:

1.

A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.

2. Dimension e: each pin centerline shall be located within .010 inch
10.25mmi of its true longitudinal position relative to pins 1 and N
IN=lead counti.

Sym
A
b

3. Dimensions El and eA: measured with leads perpendicular to the base
plane.

b,
b2

4.

c

Dimensions E1, eS and eC: measured to outside edge of lead.
5. Dimension eA: measured to lead center.
6. Dimensions 0 and E: inclusive of package anomalies [lid misalignment,
ceramic particles, ete.i. Such anomalies shall not exceed .010 inch
10 25mmi
7. Dimensions b, b1 and c: increase maximum limits by .003 inch
10.08mmi when solder finish applied.
8.

Dimension N: number of leads.

9. Standard lead finish is tin plate for all grades.
10. Controlling dimension: inch.

15

28

0
E
E,
e

Min
.150 13,811
,014 10,361
,050 11.271

Inches (Millimeters)
Max

,040 11,021 Nominal
.008
1.435
,500
,590

10,201
136.451
112,701
114,991

,015
1.480
,600
,620

10,381
137,591
115,241
115.751
,1 00 12,541 Basic
,600 115,241 Basic

eA
eB
eC

.700 117.781

L
N

,125 13,171

,200 15,081

Q

.015 10,381
,07011.781

,060 11.521

Q,

28, Note 8

,098 12.491

S

S,

Notes

,200 15.081
,023 10,581
,07011.781

,005 10.131

PIN 1 IDENTIFIER

20106A

9-14

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

SectIon 9 - Ordering Information &PackagIng

87

24-Lead Ceramic Cualln·L1ne Package
Dimensions

Notes:

,. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .010 inch
10.25mml of its true longitudinal position relative to pins 1 and N
IN = lead countl.
3. Dimensions E, and eA: measured with leads perpendicular to the base
plane.
4. Dimensions E,. eS and eC: measured to outside edge of lead.
5. Dimension eA: measured to lead center.
6. Dimensions D and E: inclusive of package anomalies Ilid misalignment.
ceramic particles. etc.l. Such anomalies shall not exceed .010 inch
10.25mml.
7. Dimensions b. b1 and c: increase maximum limits by .003 inch
10.OBmml when solder finish applied.
B. Dimension N: number of leads.
9. Standard lead finish is tin plate for all grades.
10. Controlling dimension: inch.

Sym
A
b

bl
bZ
c
D

E

E,

Min
.150 (3.811
.014 (0.36)
.050 (1.27)

Inches (Millimeters)
Max

Notes

.200 (5.08)
.023 (0.58)
.070 (1.78)
.040 (1.02) Nominal

.008
1.235
.510
.590

(0.20)
(31.40)
(12.95)
(14.99)

.015
1.280
.610
.620

(0.38)
(32.51)
(15.49)
(15.75)
.100 (2.54) Basic
.600 (15.24) Basic

e
eA
eB

.700 (17.78)

ee
L
N
0

0,
S
S,

.125 (3.17)

.200 (5.08)

.015 (0.38)
.070 (1.78)

.060 (1.52)

24. Note 8

.098 (2.49)
.005 (0.13)

Ref. 90XOO 181

PIN 1IDENTIFIER

20107A

For McII8lnformalion calI1.a1().722-7074.

Raytheon SemIconductor

9-15

SecUon 9 - Ordering Information & Packaging

B8

18-Lead Ceramic Dual In-Line Package
Dimensions

Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .010 inch
10.25mml of its true longitudinal position relative to pins 1 and N
IN=lead countl.
3. Dimensions El and eA: measured with leads perpendicular to the base
plane.

A

b
b1
b2

4. Dimensions E1, eB and eC: measured to outside edge of lead.
5. Dimension eA: measured to lead center.
6. Dimensions D and E: inclusive of package anomalies [lid misalignment.
ceramic particles, etc.l. Such anomalies shall not exceed .010 inch
10.25mml.

c

7. Dimensions b, b1 and c: increase maximum limits by .003 inch
10.oSmml when solder finish applied.
S. Dimension N: number of leads.

e

9. Standard lead finish is tin plate for all grades.
10. Controlling dimension: inch.

18

10

~::::::lII
--II--

PIN

Sym

11~ENTIFIER

0

E
E1

Min

Inches (Millimeters)
Max

.150 (3.811
.014 (0.36)
.050 (1.27)

.200 (5.08)
.023 (0.58)
.065 (1.65)

.008
.875
.280
.290

.015
.920
.305
.320

,040 (1.02) Nominal
(0.20)
(22.22)
(7.11)
(7.37)

(0.38)
(23.37)
(7.75)
(8.13)
.100 (2.54) Basic
.300 (7.62) Basic

eA
eB
ee

.400 (10.16)

L
N

.125 (3.17)

.200 (5.08)

0

.015 (0.38)
.070 (1.78)

.060 (1.52)

01

18, Note 8

.098 (2.49)

S
S1

Notes

.005 (0.13)

Ref. 90XOO 181

b1 9

~----------D----------~

9-16

Raytheon Semiconductor

For More Information call 1-800-722-7074.

SecUon 9 - Ordering Information &Packaging

89

16-Lead Ceramic Dual In-Line Package
Dimensions

Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .010 inch
10.25mml of its true longitudinal position relative to pins 1 and N
IN = lead countl.
3. Dimensions El and eA: measured with leads perpendicular to the base
plane.
4. Dimensions E1• eS and eC: measured to outside edge of lead.
5. Dimension eA: measured to lead center.
B. Dimensions D and E: inclusive of package anomalies Ilid misalignment.
ceramic particles. etc.l. Such anomalies shall not exceed .010 inch
10.25mmJ.

7. Dimensions b. b1 and c: increase maximum limits by .003 inch
10.OBmmJ when solder finish applied.
B. Dimension N: number of leads.
9. Standard lead finish is tin plate for all grades.
10. Controlling dimension: inch.
16

Sym
A
b

b,
b2
c
D

E
E,
e
eA
eS
ee
L
N

0
0,

Min
.150 (3.81)
.014 (0.36)
.050 (1.27)

.200 (5.08)
.023 (0.58)
.065 (1.65)

.008
.750
.240
.290

.015
.820
.305
.320

Notes

.040 (1.02) Nominal
(0.20)
(19.05)
(7.11)
(7.37)

(0.38)
(20.83)
(7.75)
(5.13)
.100 (2.54) Basic
.300 (7.62) Basic

.400 (10.16)
.125 (3.17)

.200 (5.08)

.015 (0.38)

.060 (1.52)

24, Note 8
.070 (1.78)
.080 (2.03)

$
$,

Inches (Millimeters)
Max

.005 (0.13)

Ref. 90X00181

For More Information calI1-80D-722-7074.

Raytheon Semiconductor

9-17

Section 9 - Ordering Information & Packaging

C1

68-Contact Hermetic Ceramic Chip Carrier
Dimensions
Sym

Min

Inches (Millimeters)
Max

Notes

PIN 1 IDENTIFIER

A
Bl
B3
D

Dl
D2
D3
D5
e
el
h
j
L

L4
L5

+

j

,-II HHMHHHHHHHHHHHAHHII
A

.

PIN 1 IDENTIFIER

9-18

.082
.022
.006
.938

(2.08)
(0.56)
(0.15)
(23.82)

.110 (2.79)
.028 (0.71)
.022 (0.56)
.962 (24.43)
.075
.800
.400
.850
.050

(1.90) Ref.
(20.32) Basic
(10.16) Basic
(21.59) Ref .
(1.27) Basic

.015 (0.38)
.040 (1.02) Ref.
.020 (0.51) Ref.
.045 (1.14)
.003 (0.08)
.075 (1.91)

.055 (1.40)
.015 (0.38)
.095 (2.41)

N

68, Note 4

ND

17, Note 5

Ref. 90X00181
Notes: 1. A pin one identifier shall be located adjacent to pin one and within the
shaded area shown.
2. Dimension e: each pin centerline shall be located within .007 inch
(0.18mml of its true longitudinal position.
3. Dimension 0: exclusive of package anomalies (lid misalignment,
ceramic particles, etc.l. Such anomalies shall not exceed .010 inch
(O.Z5mml.
4. Dimension N: number of terminals.
5. Dimension NO: number of terminals per package edge.
6. Controlling dimension: inch.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

Section 9 - Ordering Information & Packaging

C2

44·Contact Hermetic Ceramic Chip Carrier
Dimensions

Min

Sym

28

40

A

.064 (1.62)

.110 (2.79)

81
83

.022 (0.56)

.028 (0.71)

.006 (0.15)

.022 (0.56)

°°1

.640 (16.26)

.660 (16.76)

1

(

.250 (6.35) Basic
.550 (13.97) Ref.
.050 (1.27) Basic

~

t

18
17

j

.015 (0.38)
.040 (1.02) Ref.

i

(

L

.075 (1.90) Ref.

e

el
h

Notes

.500 (6.35) Basic

°2
°3
°5

44
0

Inches (Millimeters)
Max

.020 (0.51) Ref.

L

.045 (1.14)

.055 (1.40)

L4
L5

.003 (0.08)

.015 (0.38)

.075 (1.91)

.095 (2.41)

N

44, Note 4

NO

11, Note 5

Ref 90XOO 181
Notes:

A

I

II AHHHHHHHHHAII

1. A pin one identifier shall be located adlacent to pin one and within the
shaded area shown.
2. Dimension e: each pin centerline shall be located within .007 inch
(0.1Smml of its true longitudinal position.
3. Dimension 0: exclusive of package anomalies (lid misalignment,
ceramic particles, etc.l. Such anomalies shall not exceed .010 inch
(0.25mml.
4. Dimension N: number of terminals.
5. Dimension NO: number of terminals per package edge.
6. Controlling dimension: inch.

~I

For More Information call 1-800-722-7074.

Raytheon Semiconductor

9-19

Section 9 - Ordering Information & Packaging

C3

28·Contact Hermetic Ceramic Chip Carrier
5ym

~r-----------O----------

__~

~~----02------~

19

18

12

Min

Inches (Millimeters)
Max

A

.064 11.62)

.100 12.54)

81

.022 10.56)

.028 10.71)

83

.006 10.15)

0

.442 111.23)

.022 10.56)
.460 111.68)

Notes

01

.075 11.90) Ref.

D2

.300 17.62) Basic

03

.150 13.81) Basic

Os

.350 18.89) Ref .

e

.050 11.27) Basic

el
h
j
L

.01510.38)

.045 11.14)

.055 11.40)

L4
LS
N

.003 10.08)

.015 10.38)

.075 11.91)

.095 12.41)

.040 1102) Ref.
.020 10.51) Ref.

28, Note 4

NO

7, Note 5

Ref. 90XOO 181
Notes:

11

9-20

1. A pin one identifier shall be located adjacent to pin one and within the
shaded area shown.
2. Dimension e: each pin centerline shall be located within .007 inch
10.18mml of its true longitudinal position.
3. Dimension 0: exclusive of package anomalies [lid misalignment.
ceramic particles. etcl. Such anomalies shall not exceed .010 inch
(0 25mml
4. DimenSion N: number of terminals.
5. Dimension NO: number of terminals per package edge.
6. Controlling dimension: inch.

Raytheon Semiconductor

For More Information call 1-800-722-7074.

SecUon 9 - Ordering Information & Packaging

GO

68 Pin Grid Array
Cavity Down with Flat Heat Sink
Dimensions

Sym
Notes:

1.
2.
3.
4.
5.

Pin one identifier shall be within shaded area shown.
Dimension M: defines matrix size.
Dimension N: defines pin count.
Controlling dimension: inch.
Optional /TRW optionl index pin.

A
A,

A2
B
B,
B2
0

Min
.120 (3.051
.025 10.631
.150 (3.811
.017 10.431

Inches (Millimeters)
Max
.185 (4.701
.060 11.521
.240 16.101
.020 10.511
.080 12.031

.050 (1.271 Nominal
1.140128.961

1.180 129.971
1.000 125.401 Basic
.100 12.541 Basic

0,
e

L

Notes

.120 (3.051

.14013.561
11, Note 2
68, Note 3

M
N

Ref. 90X00181

-BNOTEt

GGGG0GGG0
0@GGG0GGG@G
GG
GG
GG
GG
GG
GG
GG
GG
GG
GG
GG
GG
GG
GG
G@GG00GGG@G
I GGGG0GG0G~
,
I I

~----D1----~

KEY (BOTTOM SIDEI FOR PIN ONE IDENTIFIER
20125A

For More Information call 1-800-722-7074.

Raytheon Semiconductor

9-21

SecUon 9 - Ordering Information 8& Packaging

G5

89 Pin Grid Array
Dimensions
Sym

Notes: .1.
2.
3.
4.
5.

Pin one identifier shall be within shaded area shown.
Dimension M: defines matrix size.
Dimension N: defines pin count.
Controlling dimension: inch.
Optional !TRW optionl index pin.

Min

Inches (Millimeters)
Max

.080 (2.03)
.040 (1.02)
.115 (2.92)
.017 (0.43)

A

A1
A2
<1>8

<1>81
<1>82

.125
.060
.190
.020
.080

Notes

(3.18)
(1.52)
(4.83)
(0.51)
(2.03)
.050 (1.27) Nominal

1.340 (34.04)

D

1.380 (35.05)
1.200 (30.48) Basic
.100 (2.54) Basic

D1
e
.120 (1051

L

M

.150 (3.81)
13, Note 2
88, Note 3

N

Ref. 90X00181

- - -6-0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
00
00
fill,
00
00
00
00
00
~=t=0 0
00
BOTTOM VIEW
00
00
00
00
00
00
00

e
-r----e-0 0

I

t

c

t

00

ORIENTATION PIN --....."". ~

-I!J00

0000000000000
- - -6-0 0 0 0 0 0 0 0 0 0 K::1I e
1IDENTIFIER

9-22

20130A

Raytheon Semiconductor

For More Information call 1-800-722-7074.

Section 9 - Ordering Information & Packaging

G8

68 Pin Grid Array
Dimensions
Inches (Millimeters)
Min

Sym
Notes:

1. Pin one identifier shall be within shaded area shown.
2. Dimension M: defines matrix size.
3. Dimension N: defines pin count.
4.

Controlling dimension: inch

5. Optional (TRW optionl index pin.

Max

A

.080 (2.031

.125 (3181

At

.040 (1.021

.060 (1.521

A2

.115 (2.921

.190 (4.831

.pB
.pB,
.pB2

.017 (0.431

.020 (0.511

0

.080 (2.031
.050 (1.271 Nominal
1.140 (28.961

1.180 (29.971
1.00 (25.41 Basic

0,

.100 (2.541 Basic

e
L

Notes

.120 (3.051

.150 (3.811

M

11, Note 2

N

68, Note 3

Ref. 90X00181

-B-

KEY (BOTTOM SIDEI FOR PIN ONE IDENTIFIER
20133A

For More Information call 1-800-722-7074.

Raytheon Semiconductor

9-23

SecUon 9 - Ordering Information 8& Packaging

121 Printed Circuit Board Pin Grid Array

H5

Cavity Up

Dimensions
Sym

Notes: 1. Pin one identifier shall be within shaded area shown.
2. Pin diameter excludes solder dip finish.
3.

Dimension M: defines matrix size.

4. Dimension N: defines the maximum possible number of pins. Orientation
pin is at supplier's option.
5. Controlling dimension: inch.

Inches (Millimeters)
Max

Min

A

.125 (3.17)

.215 (5.46)

A1

.080 (2.03)

.160 (4.06)

.pB
.pB2

.016 (0.41)

.020 (0.51)

D

Notes

Note 2
.050 (1.27) Nominal, Note 2

1.340 (34.04)

1.380 (35.05)

Square
1.200 (30.48) Basic

D1

e

.100 (2.54) Basic

L

.110 (2.79)

.145 (3.68)

L1

.170 (4.32)

.190 (4.83)

M

13, Note 3

N

120, Note 4

Q

.040 (1.02)

.060 (1.521

Ref.90X00181

I~<- - - 0 - - - - - . . . 1

0000000000000
0000000000000
0000000000000
000
000
000
000
000
000
000
000
000000000
0000000000
00000000000

- - -e--O 0 0 0 0 0 0 0 0 0 0 0

i---e--O 0 000 000 0 0 0 0
I
0000000000000
000
000
BOTTOM VIEW

000
000
o 0 0
ORIENTATION
0 0 0
000
PIN~ 000
000
0000
0000000000000
0000000000000
- - -e--O 0 0 0 0 0 0 0 0 000

PIN 1IDENTIFIER

9-24

000
000

/

20141A

Raytheon Semiconductor

For More Information call 1-800-722-7074.

Section 9 - Ordering Information & Packaging

89 Printed Circuit Board Pin Grid Array

H7

Cavity Up

Dimensions

Sym
Notes:

1.

Pin one identifier shall be within shaded area shown.

2

Pin diameter excludes solder dip finish.

3. Dimension M: defines matrix size.
4.

DimenSion N: defines the maximum possible number of pins. Orientation
pin is at supplier's option.

5. Controlling dimension: inch

Min

Inches (Millimeters)
Max
.215 15.461

A

.125 13.171

Al

.080 12.031

,160 14.061

B

.01610.411

.020 (0.511

B2
0

Notes

Note 2
.050 11.271 Nominal, Note 2

1.340 134.041

1.380 135.051

01

Square
1.200 130.481 Basic

e

.100 12.541 Basic

L

.110 12.791

.145 13.681

Ll

.170 14.321

.190 14.831

M

13, Note 3

N

88, Note 4

0

,040 11.021

.060 11.521

Ref, 90X00181

©©©©©©©©©©©©©
©©©©©©©©©©©©©
© ©
© ©
© ©
© ©
©©
© ©
©©
©©
© ©
©©
©©
© ©
©©
©©
©©
©©
© ©©
©©
©©
©©© ©©© © © © ©
© © ©©©©© © © © ©

--~©©©©©©©©©©©©

i:--- ~© © © © © © © © © © © ©
I

© ©
© ©
©©
©©
©©
©©
©©
©©
BonOMVIEW
©©
©©
©©
©©
©©
©©
©©
ORIENTATION PIN ________"" _ © ©
©©
~©©
©©©©©©©©©©©©©
- - ~© © © © © © © © © © © ©

PIN 1 IDENTIFIER

For More Information call 1-800-722-7074_

20143A

Raytheon Semiconductor

9-25

Section 9 - Ordering Information & Packaging

H8

69 Printed Circuit Board Pin Grid Array
Cavity Up
Dimensions

Sym
Notes:

1. Pin one identifier shall be within shaded area shown.
2. Pin diameter excludes solder dip finish.
3. Dimension M: defines matrix size.
4. Dimension N: defines the maximum possible number of pins. Orientation
pin is at supplier's option.
5. Controlling dimension: inch.

Inches (Millimeters)
Max

Min

A
A,

.125 (3.17)

.215 (5.46)

.080 (2.03)

.160 (4.06)

B
B2

.016 (0.41)

.020 (0.51)

0

Note 2
.050 (1.27) Nominal. Note 2

1.140 (28.96)

1.180 (29.97)

Square
1.000 (25.40) Basic

0,

e
L
L,

Notes

.100 (2.54) Basic
.110 (2.79)

.145 (3.68)

.170 (4.32)

.190 (4.83)

M

11. Note 3

N

68. Note 4

Q

.040 (1.02)

.060 (1.52)

Ref. 90XOO 181

©©©©©©©©©
©©©©©©©©©©©
©©
©©
©©
©©
©©
©©
©©
©©

-©©©©©oooo
--&-©OOO©©OOOO
00
©o
00

L
01

00
00
o 0

BOTTOM VIEW

00
00
00
00

ORIENTATION -........
_
0 0
PIN
.............,.. ,..

00
"" .... ""
00000000000
- - -00000000 0
~

PIN 110ENTIFIER

9-26

©©

20144A

Raytheon Semiconductor

For More Information call 1-800-722-7074.

Section 9 - Ordering Information & Packaging

64-Lead Hermetic Ceramic Dual In-Line Package

JO

Dimensions
Inches (Millimeters)
Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .010 inch
[0.25mml of its true longitudmal position relative to pins 1 and N
[N ~ leadcDuntl
3. Dimensions E1, E3 and eA: measured with leads perpendicular to the
base plane.
4. Dimensions E1, eB and ee: measured to outside edge of lead.
5. Dimensions E3 and eA measured to lead center.
6. Dimensions D and E: melusive of package anomalies [lid misalignment,
ceramic particles, etc.!. Such anomalies shall not exceed .010 inch
[0 25mml.
7. Dimension N: defines pin count
8. Controlling dimension: inch.

Sym
A
b
b1

c
D
E
E1

Min
.120
.015
.040
.008
3.170
.880
.890

13.051
10.381
11.021
10.201
180.521
122.351
122.611

Max

Notes

.175 14.441
.023 10.581
.065 11.651
.015 10.381
3.240 182.301
.910 123.111
.930 123.621
.100 12.541 Basic
.900 122.861 Basic

e

eA
eB
ee

1.000 125.401

L
N

.125 13.171

.175 14.441

0
S

.025 10.631

.065 [1.651
.100 12.541

S1
S2

.005 10.131
.005 10.131

64, Note 7

Ref. 90X00181

33

64

32
PIN 1 IDENTIFIER

For More Information call 1-800-722-7074.

Raytheon Semiconductor

9-27

Section 9 - Ordering Infonnatlon &Packaging

J1

64-Lead Hermetic Ceramic Dual In-Line Package
Bottombraze with Heat Sink
Dimensions
Sym

Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .010 inch
10.25mmJ of its true longitudinal position relative to pins , and N
IN = leadcountJ.
3. Dimensions E,. E3 and eA: measured with leads perpendicular to the
base plane.
4. Dimensions E,. eS and eC: measured to outside edge of lead.
5. Dimensions E3 and eA: measured to lead center.
6. Dimensions D and E: inclusive of package anomalies Ilid misalignment.
ceramic particles. etc.J. Such anomalies shall not exceed .010 inch
IO.25mmJ.
.
7. Controlling dimension: inch.
8. Dimension 0,: measured from lead braze/ceramic interface.
9. Dimension N: defines pin count.

A
b
b1

c
0

E
E,
E3
e

Min
.190 (4.831
.015 (0.38)
.040 (1.02)
.008 (0.201
3.170 (80.52)
.790 (20.07)
.880 (22.351
.025 (0.63)

Inches (Millimeters)
Max

.100 (2.54) Basic
.900 (22.861 Basic

eA

Ba
Be
L

1.050 (26.67)
.000 (0.00)
.125 (3.17)

.175 (4.44)
64. Note 9

N

0
BASE PLANE
SEATING PLANE

01

.050 (1.27)
.026 (0.66)

~

.100 (2.54)
.100 (2.54)

S
S1

Notes

.275 (6.99)
.023 (0.58)
.065 (1.65)
.015 (0.38)
3.240 (82.30)
.810 (20.57)
.930 (23.62)

.005 (0.131
.060 (1.52)

Ref. 90X00181

64

33

PIN 1 IDElmAER

9-28

Raytheon Semiconductor

For More Information call 1-800-722-7074.

Section 9 - Ordering Information & Packaging

J3

64-Lead Hermetic Ceramic Dual In-Line Package BOHombraze
Dimensions
Inches (Millimeters)
Min

Max

A

.125 (3.171

.200 (5,081

b
bl

.015 (0.381
.040 (1.021

.023 (0.581
,065 (1.651

Sym
Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .0lD Inch
10.Z5mml of its true longitudinal position relative to pins 1 and N
IN =leadcountl.
3. Dimensions E1, E3 and eA: measured with leads perpendicular to the
base plane.
4. Dimensions E1, eB and ee: measured to outside edge of lead.
5. Dimensions E3 and eA: measured to lead center.
6. Dimensions 0 and E: inclusive of package anomalies (lid misalignment,
ceramic particles, etc.1 Such anomalies shall not exceed .olD inch
10.Z5mml
7. Controlling dimension: inch.

°

1: measured from lead braze/ceramic interface.
9. Dimension N: defines pin count.
8. Dimension

BASE PlANE

----l-i

SEATING PLANE!
r
If!

4.I~e

eA

tL

10
=-j!

3
t,----E

·1

'~\ °1

Notes

c

.008 (0.201

.015 (0.381

D
E

3,170 (80.521

3.240 (82.301

.790 (20.071

.810 (20.571

El
E3
e

,880 (22.351

.930 (23.621

.025 (0,631
.100 (2.541 Basic
.900 (22.861 Basic

eA
eB
ee

1.050 (26,671

L
N

.125 (3.171

,175 (4.441

11

,050 (1.271

.100 (2,541

III
8

.026 (0,661

81
82

.005 (0.131

64, Note 9

.100 (2.541
,005 (0.131

Ref. 90X00181

11-------8B

33

PIN 1 IDENTIFIER

For More Information caJll-800-722-7074.

Raytheon Semiconductor

9-29

Section 9 - Ordering Information & Packaging

J4

48-Lead Hermetic Ceramic Dual In-Line Package
Dimensions
Inches (Millimeters)

Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .010 inch
10.25mml of its true longitudinal position relative to pins 1 and N
IN =leadcountl.
3. Dimensions El and eA: measured with leads perpendicular to the base
plane.

4. Dimensions E1, eS and ee: measured to outside edge of lead.
5. Dimension eA: measured to lead center.
6. Dimensions D and E: inclusive of package anomalies lIid misalignment,
ceramic particles, etc.l. Such anomalies shall not exceed .010 inch
10 25mml.
7. DimenSion N: defines pin count.
S. Controlling dimension: inch.

BASE PLANE
~==~~~~____________~I:~'

I

SEAliNG PLANE

~ .~:=

I
I

:=J

Min

Max

A

.120 (3.05)

.175 (4.44)

Sym
b

.014 (0.35)

.023 (0.58)

bl

.040 (1.02)

.065 (1.65)

c

.008 (0.20)

.015 (0.38)

0
E

2.370 (60.20)

2.435 (61.85)

.575 (14.60)

.610 (15.49)

El

.590 (14.99)

.620 (15.75)

Notes

e
eA
eB
eC
L
N
Q
S

SI
S2

.100 (2.54) Basic
.600 (15.24) Basic
.700 (17 .78)
.125 (3.17)

.200 (5.08)

.025 (0.63)

.060 (1.52)

48, Note 7
.100 (2.54)
.005 (0.13)
.005 (0.131

Ref. 90XOO 181

25

48

24

9-30

Raytheon Semiconductor

For More Information call HIOO-722-7074.

SectIon 9 - OrderIng InformaUon &PackagIng

40-Lead i-lermetic Ceramic Dual In-Line Package

J5

Dimensions
Inches (Millimeters)
Notes: 1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .010 inch
10.25mml of its true longitudinal position relative to pins 1 and N
IN = leadcountJ.
3. Dimensions El and eA: measured with leads perpendicular to the base
plane.
4. Dimensions E1• eB and ee: measured to outside edge of lead.
5. Dimension eA: measured to lead center.
6. Dimensions D and E: inclusive of package anomalies lIid misalignment.
ceramic particles. etc.l. Such anomalies shall not exceed .010 inch
10.25mml·
7. Dimension N: defines pin count.
8. Controlling dimension: inch.

Sym

Min

A
b

.120
.014
.040
.008
1.970
.575
.590

bl
c
0

E
El
e

(3.05)
(0.35)
(1.02)
(0.20)
(50.04)
(14.60)
(14.99)

Max
.175
.023
.065
.015
2.030
.610
.620

Notes

(4.44)
(0.58)
(1.65)
(0.38)
(51.56)
(15.49)
(15.75)
.100 (2.54) Basic
.600 (15.24) Basic

eA
eS

.700 (17.78)

Be
L

.125 (3.17)

.200 (5.08)

.025 (0.63)

.060 (1.52)
.098 (2.49)

40, Note 7

N
Q

8
.005 (0.13)
.005 (0.13)

81

~

Ref. 90XOO 181

40

21

20
1 IDENTifiER

71"

D

-:L.,
BASE PLANE
SEATING PLANE

•

For More Infonnalion call 1-800-722-7074.

Raytheon Semiconductor

9-31

SectIon 9 - Ordering Information &Packaging

J6

28-Lead Hermetic Ceramic Dual In-Line Package
Dimensions
Inches (Millimeters)
1. A notch or pin on~ identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .01 0 inch
{0.25mml of its true longitudinal position relative to pins 1 and N
IN = leadcountl.
3. Dimensions El and eA: measured with leads perpendicular to the base
plane.
4. Dimensions E1. eB and eC: measured to outside edge of lead.
5. Dimension eA: measured to lead center.
6. Dimensions D and E: inclusive of package anomalies {lid misalignment.
ceramic particles. etc.l. Such anomalies shall not exceed .010 inch
{0.25mml.
7. Dimension N: defines pin count.
8. Controlling dimension: inch.

Notes:

Sym
A
b

bl
c
D

E
El
e
eA
eB
ee
L
N
Q

Max

Min
.120
.014
.040
.008
1.380
.575
.590

(3.051
(0.351
(1.021
(0.201
(35.051
(14.601
(14.991

.175
.023
.065
.015
1.420
.610
.620

.100 (2.541 Basic
.600 (15.241 Basic
.700 (17.781
.125 (3.171

.200 (5.081

.025 (0.631

.060 (1.521
.098 (2.491

28, Note 7

5
51
52

Notes

(4.441
(0.581
(1.651
(0.381
(36.071
(15.491
(15.751

.005 (0.131
.005 (0.131

Ref. 90XOOI Bl
28

15

C~:-=~===-,
11_ee

r-

14

SA

--I

eB

1 IDENTIFIER

BASE PLANE

SEATING PLANE

9-32

Raytheon Semiconductor

For More Information call 1-800-722-7074.

Section 9 - Ordering Information & Packaging

24-Lead Hermetic Ceramic Dual In-Line Package

J7

Dimensions
Inches (Millimeters)
Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown

Sym

2.

A

Dimension e: each pin centerline shall be located within .010 Inch
(0 25mmi of ItS true longitudinal position relative to pins 1 and N
(N ~ leadcounti.

3. Dimensions El and eA: measured with leads perpendicular to the base
plane.
4. Dimensions E1, eS and ee: measured to outside edge of lead.
5. Dimension eA: measured to lead center.
6. Dimensions D and E: inclusive of package anomalies (lid misalignment
ceramic particles, etc.). Such anomalies shall not exceed .010 inch
(0 25mmi

7. Dimension N: defines pin count
8. Controlling dimension: inch.

13

24

Min

Max

b

.120 13.05)
.014 10,35)

.175 14.44)
,023 10.58)

b,

.040 11.02)

.065 11.65)

c
D

,008 10.20)

.015 10.38)

1.180 129.97)
.575 114.60)

1.220 130.99)

,590 114.99)

,620 115.75)

E
E,

e
eA
eO
ee

Notes

.610 115.49)
.100 12.54) Basic
.600 115.24) Basic
.700 117.78)

L
N

.125 13,17)

.200 15.08)

Q

.025 10.63)

,060 11,52)

S
S,
S2

,005 10.13)

24, Note 7
.098 12.49)
,005 10.13)

Ref. 90X00181

12

1 IDENTIFIER

20154A

For More Infonnation call 1-800-722-7074.

Raytheon Semiconductor

9-33

SecUon 9 - Ordering InformaUon &Packaging

18-Lead Hermetic Ceramic Dual In-Line Package

J8

Dimensions
Inches (Millimeters)
Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Dimension e: each pin centerline shall be located within .010 inch
IO.25mml of its true longitudinal position relative to pins 1 and N
IN = leadcountl.
3. Dimensions E1 and eA: measured with leads perpendicular to the base
plane.
4. Dimensions E1, eB and ee: measured to outside edge of lead.
5. Dimension eA measured to lead center.
6. Dimensions 0 and E: inclusive of package anomalies lIid misalignment,
ceramic particles, etc.l. Such anomalies shall not exceed .010 inch
(0.25mml.
7. Dimension N: defines pin count.
8. Controlling dimension: inch.

18

Sym
A
b

bl
c
D

E
El
e

Min

Max

.10012.54)
.014 10.35)
.040 11.02)
.008 10.20)
.885 122.48)
.285 17.24)
.290 17.37)

.17514,44)
.02310.58)
.06511.65)
.01510.38)
.915 123.24)
.305 17.75)
,32018.13)
.100 12.54) Basic
.300 17.62) Basic

eA
eB
ee

.400110.16)

L
N

.12513.17)

.20015.08)

Q

.01510.38)

.060 11.52)
.098 12.49)

18, Note 7

8
81
82

PIN 1 IDENTIFIER

Notes

.00510.13)
.005 10.13)

Ref. 90X00181

c-1~
BASE PlANE
SEATING PLANE
I

I

I \

Il--aA--j
ae

f--

aB

9-34

Raytheon Semiconductor

For Mont Information call 1-800-722·7074.

Section 9 - Ordering Information & Packaging

16-Lead Hermetic Ceramic Dual In-Line Package

J9

Dimensions
Inches (Millimeters)
Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.

Sym

2. Dimension e: each pin centerline shall be located within .010 inch
[0.25mml of its true longitudinal position relative to pins 1 and N
[N =leadcountl.

A
b
b1
c
D
E

3. Dimensions El and eA: measured with leads perpendicular to the base
plane.
4. Dimensions E1, eB and ee: measured to outside edge of lead.
5. Dimension 8A: measured to lead center.
6. Dimensions D and E: inclusive of package anomalies [lid misalignment,
ceramic particles, etc.l. Such anomalies shall not exceed .010 inch
[0 25mml.
7. Dimension N: defines pin count.
8. Controlling dimension: inch.

16

El

Min

.175 [4.44)

.040 (1.02)

.065 (1.65)

.008 (0.20)

.015 (0.38)

.790 (20.07)
.285 (7.24)

.810 (20.57)
.305 (7.75)

.290 (7.37)

.320 (8.13)

Notes

.023 (0.58)

.100 (2.54) Basic

e

.300 (7.62) Basic

eA
eB
ee

.400 (10.16)

L
N

.125 (3.17)

.200 (5.08)

n

.015 (0.38)

.060 (1.52)

16, Note 7

S

SI
S2
8

Max

.100 (2.541
.014 (0.35)

.080 (2.03)
.005 (0.13)
.005 (0.13)

Ref. 90X00181

PIN 1 IDENTIFIER

'-1~

I ' --:L"

'Fl'

j

-.----t---;;;:-;-;~BASE PLANE
_ _ _!i
SEATING PLANE
" I
" I
II

'7.

i l--1e 1-->

~

For More Information call 1-800-722-7074.

Raytheon Semiconductor

..

\\

II

I \\\\

I

"b··-!'

~~~-eB----__~

9-35

SectIon 9 - Ordering Information & Packaging

L1

68 Leaded Hermetic Ceramic Chip Carrier
Dimensions
Sym

DI-h=~1
D3------j
1601

I

A

I

144

I

I

Al
A2
b

PIN 1

·IDENTIRER
43

/

V

I

'D

II

9-36

.009 (0.23)
.935 (23.75)

.115
.100
.015
.022
.012

Notes

(2.92)
(2.54)
(0.38)
(0.56)
(0.30)

.970 (24.64)
.075
.800
.400
.050

.350 (8.98)

(1.91) Ref.
(20.32) Basic
(10.16) Basic
(1.27) Basic

.400 (10.16)

N

68, Note 4

ND

17, Note 5

Ref. 90X00181

"-

10

(2.03)
(1.78)
(0.13)
(0.41)

Dl
D2
D3
L

~
9

D

.080
.070
.005
.016

Inches (Millimeters)
Max

e

~

68

c

Min

I I

26

Notes: 1. A pin one identifier shall be located adjacent to pin one and within the
shaded area shown.
2. Dimension e: each pin centerline shall be located within .007 inch
10.18mml of its true longitudinal position.
3. Dimension Df exclusive of package anomalies lIid misalignment. ceramic
particles. etc.I. Such anomalies shall not exceed .010 inch 10.25mml.
4. Dimension N: number of terminals.
5. Dimension ND: number of terminals per package edge.
6. Controlling dimension: inch.

Raytheon Semiconductor

For More Information call 1-800·722·7074.

SecUon 9 - Ordering Information & Packaging

L3

84 Leaded Hermetic Ceramic Chip Carrier
Dimensions
Inches (Millimeters)

Notes:

1. A pin one Identifier shall be located adjacent to pin one and within the
shaded area shown.

Sym

2. Dimension 01' exclusive of package anomalies lIid misalignment, ceramic
particles, etc.l. Such anomalies shall not exceed .010 inch [0.25mml.
3. Dimension N: number of terminals.
4. Dimension NO: number of terminals per package edge.
5. Controlling dimenSion: inch.

A2
b
c
01

Notes

Min

Max

.060 11.521
.055 11.40)
,005 10,13)

.100 12.54)
.075 (1.91)
.025 10,64)

.008 10.20)
.005 10.13)
.640 116.25)

.012 10.30)
.009 10.23)
.660 116.76)
,250
.500
,025
,035

e
,350 18.98)

L

.445 111.30)
.016 10.41) Ref.
84, Note 3
21, Note 4
,015 10,38) M
,004 10,10) M

L2
N
63
e1

43

I

§4

T1

1

/

NO
T

I

I

16,35) Basic
(12.70) Basic
10.64) Basic
10,89) Ref.

Ref 9OX00181

~

D

I

42

PIN 1 IDENTIFIER LOCATED
ON THE BOTTOM

-$-

1

+

T C

A

CD I BCD I

T1 C

~~-

(TOP VIEW)

84

fill

~

~

1

22

..

21

01

For More Information call 1-800-722-7074.

~aytheon

Semiconductor

9-37

SectIon 9 - Ordering InformaUon &Packaging

L4

100 Leaded Hermetic Ceramic Chip Carrier
Dimensions

Notes: 1. A pin one identifier shall be located adjacent to pin one and within the
shaded area shown.
2. Dimension D( exclusive of package anomalies lIid misalignment. ceramic
particles, etc.I. Such anomahes shall not exceed .010 lOch 10.25mmJ.
3. Dimension N: number of terminals.
4. Dimension ND: number of terminals per package edge.
5. Controlling dimension: inch.

Sym

Min
,080
.075
,005
.008
.005
.740

A
Al
A2
b

c
01
02
03

Inches (Millimeters
Max

(2,031
(1.91)
(0,131
(0,201
(0,131
(18.801

.120
.095
,025
.012
.009
.760

Notes

(3,051
(2.411
(0,641
(0,301
(0,231
(19.301

8

81

e

.275 (6.981

L

,300
.600
.025
.025

(7,621 Basic
(15.241 Basic
(0.641 Basic
(0.641 Ref.

.016
100,
25,
.020
.005

(0.411 Ref.
Note 3
Note 4
(0.511 M
(0.131 M

.330 (8.381

L2
N

NO
T
Tl
Ref. 90XOO1Bl
50

PIN 1 IDENTIFIER LOCATED
ON THE BOnOM

I

+

T C

-$- T1

A®IB®I

C

(TOP VIEW)

100

26

A

9-38

Raytheon Semiconductor

For McII8lnfcrmalion call 1-800-722·7074.

SecHon 9 - Ordering InformaUon & Packaging

L5
Notes:

132 Leaded Cerquad

Dimensions

1. A pin one identifier shall be located adjacent to pin one and within the
shaded area shown.
2. Dimensions 0 and E : exclusive of package anomalies lIid misalignment,
1
ceramic partices, etc ..1 Such anomalies shall not exceed .010 mch

A
A,

10.25mmi.
3. Dimension N: number of terminals.
4. Dimension NO: number of terminals per package edge.
5. Controlling dimension: inch.

b

c
O. E
0,. E,
e

132

100

Inches (Millimeters)
Max

Min

Sym

.114
.055
.008
.005

.154
.075
.012
.009

(2.89)
(1.40)
(0.20)
(0.13)

(3.91)
(1.90)
(0.30)
(0.23)
1.415 (35,94) Ref.

.860 (21.83)

.900 (22.84)

.220 (5.58)

.320 (8.12)

.025 (0.64) Basic
132. Note 3
33, Note 4

N

NO

I
I

Notes

Ref. 90XOO 181

I

I~"",l.

1

--

~

T

I

e

TOP VIEW

--

E

---

+

--

-

--

I

I.

T
67

I

1~4

El

~

I
33 1

- G. -----c±J

b

66
°1

0

•
20162A

For More Information caJll-800-722-7074.

Raytheon Semiconductor

9-39

SecUon 9 - Ordering InforrnaUon It Packaging

L6

100 Leaded Cerquad
Dimensions

Notes: 1. A pin one identifier shall be located adjacent to pin one and within the
shaded area shown.
2. Dimensions 01 and E,: exclusive of package anomalies lIid misalignment,
ceramic particles, etc.!. Such anomalies shall not exceed .010 Inch

10.25mml.

Min

A
A,

3. Dimension N: number of terminals.
4. Dimension NO: number of terminals per package edge.
5. Controlling dimension: inch.

75

I

Inches (Millimeters)
Max

.114 (2.89)
.055 (1.40)
.008 (0.20)

c
D, E

.005 (0.13)

.154
.075
.012
.009

D" E,
e

.670 (17.02)

.760 (19.30)

L
N

.220 (5.58)

.320 (8.12)

b

100
j

Sym

(3.91)
(1.90)
(0.30)
(0.23)
1.300 (32.95) Ref.
.025 (0.64) Basic
100, Note 3
25, Note 4

ND

I

Notes

Ref. 90XOO 181

I

,

~

IDENTIFIER

-- -

E

I

--

I

~

I

-+-

-

--

I

1
E,

~

I

1~6

e

- '1. ----r:::±J

~

TOP VIEW
I
25

T

50

0,

D

OlE

t ,----L-:===D'
=
=:'
r
-Ll
I
1+ I
A

aaaaaaaaaaaaaaaaaaaaaaaaa

t

9-40

t

20163A

Raytheon Semiconductor

For More Infonnation call 1-800-722-7074.

SectIon 9 - OrderIng Information & PackagIng

M3

20·Lead Plastic SOle, .300"
Dimensions
Sym
A
b
b,
c
D
E

El
e

Min

Inches (Millimeters)
Max

.093 (2.36)
.014 (0.36)

.104 (2.64)
.019 (0.48)

.009
.496
.291
.394

.013
.512
.299
.419

(0.23)
(12.60)
(7.39)
(10.01)

Notes

(0.33)
(13.01)
(7.60)
(10.64)
.050 (1.27) Typ.

L
20

N
Q

.004 (0.10)

.012 (0.30)

Ref. 90X00181
10

SEATING PLANE

For Mora Information call 1-800-722·7074.

Raytheon Semiconductor

21579A

9-41

SecUon 9 - Ordering InformaUon &Packaging

M9

16·Lead Plastic SOle, .300"
Dimensions
Sym
A
b

Min

Inches (Millimeters)
Max

.093 (2.36)
.014 (0.36)

.104 (2.64)
.020 (0.51)

.009
.398
.291
.394

.013
.413
.299
.419

Notes

b1

c
0
E
E1

e
F
L
N
Q

(0.23)
(10.11)
(7.39)
(10.01)

(0.33)
(10.50)
(7.60)
(10.64)
.050 (1.27) TVp.

.089 (2.26)

.092 (2.34)

.004 (0.10)

.012 (0.30)

16

01

Ref. 90X00181

~~DiOiOOOOD~
~"""IlLI""""""""""IlLI"""
~e~b~~

9-42

SEATING PLANE
21581 A

Raytheon Semiconductor

For More Information call 1-800-722-7074.

SecUon 8 - Ordering Information &Packaging

ME

14-Lead Plastic SOle, .150"
Dimensions
Inches IMHlimetenl

Mill

Sym
A
b

bl
c
0
E
E1

•F

Max

.053 11.35)
.01410.36)

.069 11.75)
.020 10.51)

.OOB
.335
.150
.22B

10.20)
IB.51)
13.B1)
15.79)

.01010.25)
.344 IB.74)
.15713.99)
.244 16.20)

.049 11.25)

.059 11.50)

.00410.10)

.01010.25)

Notes

.050 11.27) Typ.

L

14

N
Q

a

Ref. 90XOO 181

SEATING PLANE
21583A

For Mont InfarmaJlan call 1-800-722·7074.

Raytheon Semiconductor

9-43

SectIon 9 - Ordering InformaUon &Packaging

MH

8-Lead Plastic SOle, .150"
Dimensions
Min

Sym
A
b

b1
c
D

E
E1
e
F
L
N
Q

Inche. (Millimeten)
Max

.053 (1.35)
.014 (0.36)

.069 (1.15)
.019 (0.48)

.007
.188
.150
.228

.010
.196
.158
.244

(0.18)
(4.78)
(3.81)
(5.79)

Notes

(0.25)
(4.98)
(4.01)
(6.20)
.050 (1.27) Typ.

.049 (1.25)

.059 (1.50)

.004 (0.10)

.010 (0.25)

8

0<

Ref.90X00181

~F

SEATING PLANE

t

21585A

Q

9-44

Raytheon Semleonductor

For Mont InbmaIIan C11111-«1O-722-7074.

SectIon 9 - OrderIng InformatIon & PackagIng

64-Lead Plastic Dual In-Line Package

NO

Dimensions

Notes: 1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Each pin centerline shall be located within .010 inch 10.25mml of its
true longitudinal position.

Sym

Min

A

Inches (Millimeters)
Max

Notes

.250 16.351

b

.014 10.351

.022 10.561

b,
C

.030 10.761

.070 11.781

.008 10.201

.015 10.381

0

3.05 177.471

3.245 182.421

0,

.005 10.131

E

.745 118.921

.840 121.341

E,
e

.900 122.861

.925 123.501

F
L

.125 13.181

.195 14.951

.115 12.921

.200 15.081

Q

.015 10.381

ex

0°

.100 12.541 Basic

15°

Ref. 90XOO 181

33

64

PIN , IDENTIFIER

SEATING PLANE

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

9-45

Section 9 - OrderIng InformatIon & PackagIng

20-Lead Plastic Dual In-Line Package

N1

Dimensions

Notes:

1. A notch or pin one identifier shall be located adlacent to pin one and
within the shaded area shown.
2. Each pin centerline shall be located within .010 inch 10.25mml of its
true longitudinal position.

Sym

Min

Inches (Millimeters)
Max

A

.145 (3.68)

.200 (5.08)

b

.015 (0.381

.021 (0.53)

e

.009 (0.23)

.015 (0.38)

0

1.013 (25.73)

1.040 (26.42)

0,

.005 (0.13)

E

.255 (6.48)

.265 (6.73)

E,

.310 (7.87)

e

.090 (2.29)

.363 (9.27)
.110 (2.79)

F

.125 (3.18)

.135 (3.43)

L

.125 (3.18)

.140 (3.56)

Q

.020 (0.51)

0'

0°

.060 (1.52) Typ.

b,

~:::::::111
PIN 1 IDENTIFIER

Notes

15°

Ref. 90XOO 181

9-46

Raytheon Semiconductor

For More Infonnation caJI1-800·722·7074.

Section 9 - Ordering Information & Packaging

24-Lead Plastic Dual In-Line Package, .300"

N2

Dimensions

Notes: 1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2.

Sym

Each pin centerline shall be located within .0lD inch [0.25mml of its

A

true longitudinal position.

b

bl
C
D
~

~

~:::::::]
1

PIN 1 IDENTIFIER

01

~L

D1

E

El
e
F
L
Q
a

Min
.130
.014
.045
.008
1.180
.005
.240

13.301
10.351
11.141
10.201
129.971
10.131
16.101

Inches (Millimeters)
Max
.230
.023
.070
.015
1.285

Notes

15.841
10.581
11.781
10.381
132.641

.310 17.871
.300 17.621 Basic
.100 12.541 Basic

.115 12.921
.115 12.921
.015 10.381
00

.195 14.951
.200 15.081
15 0

Ref. 90XOO 181

20168A

For More Information caJI1-800-722-7074.

Raytheon Semiconductor

9-47

SectIon 9 - OrderIng InformaUon & PackagIng

48-Lead Plastic Dual In-Line Package

N4

Dimensions
Inches (Millimeters)
Notes: 1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Each pin centerline shall be located within .010 inch (0.25mmJ of its
true longitudinal position.

8ym
A
b

b,
C
D

D,
E
E,
e
F
L
Q
01

Max

Min
.014
.030
.008
2.375
.005
.485
.600

.250
.022
.070
.015
2.490

(0.35)
(0.76)
(0.20)
(60.32)
(0.13)
(12.32)
(15.24)

Notes

(6.35)
(0.56)
(1.78)
(0.38)
(63.25)

.580 (14.73)
.625 (15.87)
.100 (2.54) Basic

.125 (3.18)
.115 (2.92)
.015 (0.38)
0°

.195 (4.95)
.200 (5.08)

15°

Ref. 90XOO 181

48

25

T

E

~~~~~~~JL
24

" " PIN 1 IDENTIFIER

SEATING PlANE

9-48

Raytheon Semiconductor

For More Information call 1-800·722·7074.

Section 9 - Ordering Information & Packaging

4O-Lead Plastic Dual In-Line Package

N5

Dimensions
Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.

Sym

2. Each pin centerline shall be located within .010 inch (0.25mml of its
true longitudinal position.

A

Min

Inches (Millimeters)
Max
.250 (6.35)

b

.014 (0.35)

b1
C

.030 (0.76)
.008 (0.20)

.015 (0.38)

0

1.980 (50.29)

2.095 (53.21)

01
E

.005 (0.13)

.022 (0.56)
.070 (1.78)

.485 (12.32)
.600 (15.24)

.580 (14.73)

F
L

.125 (3.18)

.195 (4.95)

.115 (2.92)

.200 (5.08)

Q

.015 (0.38)

Cl

0°

E1
e

Notes

.625 (15.87)
.100 (2.54) Basic

15°

Ref. 90XOO 181

21

40

IT
E

20
1 IDENTIFIER

___------------------------D------------------------~~

I~

~o

~ ~~

-lr-'

For More Information call 1-800·722·7074.

_+ ~

Raytheon Semiconductor

A

=--,---SEATING_PLANE

9-49

Section 9 - Orderln,g InformaUon 8& packaging

N6

28-Lead Plastic Dual In-Line Package
Dimensions

Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Each pin centerline shall be located within .010 inch 10.25mml of its
true longitudinal position.

Sym
A
b

.014
.030
.008
1.380
.005
.485
.600

b,
28

15

Min

C
D

D,
E
E,
e

(0.361
(0.761
(0.201
(35.051
(0.13)
(12.32)
(15.24)

Inches (Millimeters)
Max
.250
.022
.070
.015
1.565

Notes

(6.351
(0.561
(1.781
(0.381
(39.751

.580 (14.73)
.625 (15.88)
.100 (2.54) Basic

F

.115 (2.92)
.015 (0.38)
0°

L
Q

'"

.200 (5.08)
15°

Ref. 90X00181

I~'"-D~
A

20172A

9-50

Raytheon Semiconductor

For More Information calI1.alO·722·7074.

Section 9 - Ordering Information & packaging

N7

24-Lead Plastic Dual In-Line Package
Dimensions

Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Each pin centerline shall be located within .010 inch 10.25mml of its
true longitudinal position.

24

13

Sym

Min

A

b

b,
C
D

D,
E
E,

.014 10.351
.030 10.761
.008 10.201
1.150129.211
.005 (0.131
.485 (12.321
.600 (15.241

Inches (Millimeters)
Max
.250
.022
.070
.015
1.290

16.351
10.561
11.781
10.381
132.771

.580 (14.731
.625 (15.881
.100 (2.541 Basic

e
F
L
Q
01

Notes

.125 (3.181
.115 (2.921
.015 10.381
0°

.195 (4.951
.200 (5.081
15°

Ref. 90X00181

For More Information call 1-800-722-7074.

Raytheon Semiconductor

9-51

Section 9 - Ordering InformaUon & Packaging

N8

18-Lead Plastic Dual In-Line Package
Dimensions

Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Each pin centerline shall be located within .010 inch 10.25mml of its
true longitudinal position.

Sym
A
b

b,
C
0

0,
E

E,
e
F
PIN 1 IDENTIFIER

L
Q

'"

Min
.014
.045
.008
.845
.005
.240
.300

(0.36)
(1.14)
(0.20)
(21.46)
(0.13)
(6.10)
(7.62)

Inches (Millimeters)
Max
.210
.022
.070
.015
.925

Notes

(5.33)
(0.56)
(1.78)
(0.38)
(23.50)

.280 (7.11)
.325 (8.25)
.100 (2.54) Basic

.115 (2.92)
.115 (2.92)
.015 (0.38)
0°

.195 (4.95)
.160 (4.06)
15°

Ref. 90X00181

9-52

Raytheon Semiconductor

For Mora Information call 1-800-722-7074.

Section 9 - Ordering Information Be Packaging

N9

16-lead Plastic Dual In-Line Package
Dimensions

Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.
2. Each pin centerline shall be located within .0lD inch 10.25mml of its
true longitudinal position.

Sym
A
b
b1
C
D
D1

E
E1

e
F
L
Q

'"

Inches (Millimeters)
Max

Min
.014
.045
.008
.745
.005
.240
.300

.210
.022
.070
.015
.840

(0.35)
(1.14)
(0.20)
(18.92)
(0.13)
(6.10)
(7.62)

Notes

(5.33)
(0.56)
(1.78)
(0.38)
(21.34)

.280 (7.11)
.325 (8.25)
.100 (2.54) Basic
.195 (4.95)
.160 (4.06)

.115 (2.92)
.115 (2.92)
.015 (0.38)
0°

15°

Ref. 90X00181

I~-.-----.--

R

~=~==t.:=~BA~S~EPlA~N~E=-_~S~E~!!!!:rINt!ClGi1PlA~NE~-tnv

J[~~.~.~

For Mont Information call 1-800·722·7074.

.~j!

Raytheon Semiconductor

r

'.
20175A

9·53

Section 9 - Ordering Information & Packaging

NH

a-lead Plastic Dual In-line Package
Dimensions

Notes:

1. A notch or pin one identifier shall be located adjacent to pin one and
within the shaded area shown.

Sym

2. Each pin centerline shall be located within .010 inch (0.25mml of its
true longitudinal position.

A

b

Min

Inches (Millimeters)
Max

.145 (3.681
.015 (0.381

.200 (5.081
.021 (0.531

.009
.373
.005
.245
.310
.090
.125
.125
.020

.015 (0.381
.400 (10.161

.060 (1.521 Typ.

b1

e
0
01

E
E1

e
F
L
Q

Notes

Ci

(0.231
(9.471
(0.131
(6.221
(7.871
(2.291
(3.181
(3.181
(0.511
00

.255
.365
.110
.135
.140

(6.481
(9.271
(2.791
(3.431
(3.561
15 0

Ref. 90X00181

r-E--I
A
SEATING PLANE

l.:Jt."

9-54

'~~-

Raytheon Semiconductor

ro"M

For More Information call 1-800-722-7074.

SectIon 9 - Ordering Informadon &Packaging

RO

84-Lead Plastic J-Leaded Chip carrier
Dimensions

Notes: 1. All dimensions and tolerances conform to ANSI Y14.5M-19B2.
2. Datum plane (- H-I located at top of mold parting line and
coincident with top of lead. where lead exits plastic body.
3. Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .010 inch 10.25mml.
4. Details of pin 1 identifier are optional but must be located within the
zone indicated.
5. Dimension N: number of terminals.
6. Dimension NO: number of terminals per package edge.
7. Controlling dimension: inch.

Inches IMillimetersl
Max

Min

Sym

.16514.201
.09012.291
.013 10.331
.02610.661
1.185 130.101
1.150 129.211
1.185 130.101
1.150 129.211

A

A,
b

b,
D

D,
E

E,

.200 15.081
.13013.301
.021 10.531
.03210.81)
1.195 130.351
1.158129.41)
1.195 130.351
1.158129.411

N

ND

Notes

Note 3
Note 3
84, Note 5
21, Note 6

.020 10.51)

Q
Ref. 90X001B1
E

I.

E1

53

75

PIN 11DENllFER
(SEE NOlE 41

84

_1•
-1
01

0

12

20180A

For Mora InfannaIIon caJl1-800-722·7074.

Raytheon Semiconductor

SecUon 9 - Ordering InfonnBUon & Packaging

R1

68-Lead Plastic J-Leaded Chip carrier
Dimensions
Min

Sym

Notes: 1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
2. Datum plane (- H-I located at top of mold parting line and
coincident with top of lead, where lead exits plastic body.
3. Dimension 01 and E1 do not include mold protrusion. Allowable
protrusion is .010 inch IO.25mmJ.
4. Details of pin 1 identifier are optional but must be located within the
zone indicated.
5. Dimension N: number of terminals.
6. Dimension NO: number of terminals per package edge.
7. Controlling dimension: inch.

D

D,

~------- E -------~

.165
.090
.013
.026
.985
.950
.985
.950

Inches (Millimeters)
Max

(4.20)
(2.29)
(0.33)
(0.66)
(25.02)
(24.13)
(25.02)
(24.13)

.200
.130
.021
.032
.995
.958
.995
.958

•N
ND
Q

(5.08)
(3.30)
(0.53)
(0.81)
(25.27)
(24.33)
(25.27)
(24.33)

Notes

Note 3
Note 3
.050 (1.27) Basic
68, Note 5
17, Note 6

.020 (0.51)

Ref. 90X00181

61

66
D1

D

10

rn '. .'

+.

.

~

AI

~~b

"t

.

T

_""",Hi
SEATING PLANE

20181A

9-56

Raytheon Semiconductor

For More Information caD 1-8)(1-722-7074.

SecUon 9 - Ordering InforrnaUon & Packaging

R2

44-Lead Plastic J·Leaded Chip Carrier
Dimensions

Sym

Notes: 1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
2. Datum plane (- H-I located at top of mold parting line and
coincident with top of lead. where lead exits plastic body.
3. Dimension 01 and El do not include mold protrusion. Allowable
protrusion is .010 inch 10.25mml.
4. Details of pin 1 identifier are optional but must be located within the
zone indicated.
5. Dimension N: number of terminals.
6. Dimension NO: number of terminals per package edge.
7. Controlling dimension: inch.

A
A,
b
b,

0
0,
E
E,
e

Min
.165
.090
.013
.026
.685
.650
.685
.650

14.20)
(2.29)
10.33)
10.66)
117.40)
116.51)
117.40)
116.51)

N
NO
Q

Inches (Millimeters)
Max
.180
.120
.021
.032
.695
.656
.695
.656

14.57)
(3.04)
(0.53)
(0.81)
(17.65)
(16.66)
(17.65)
(16.66)

Notes

Note 3
Note 3
.050 (1.27) Basic
44, Note 5
11, Note 6

.020 (0.51)

Ref. 90X00181

39

40

PIN lIDEN11FIER
(SEE NOTE 4)

44

1_1

D

e

T-

6

~~bl

17

tI~"_-,~,---___
~

Al

~~b

For More Infonnalion call 1-800-722-7074.

1.

T

D_AT_UM_PlAN_E_(-_H-_)_
SEATING PLANE

Q

Raytheon Semiconductor

20182A

9-57

SecUon 9 - Ordering Information & Packaging

R3

28·Lead Plastic J·Leaded Chip Carrier
Dimensions

Notes:

1. All dimensions and tolerances conform to ANSI YI4.5M-1982.
2. Datum plane I-H-} located at top of mold parting line and coincident
with top of lead, where lead exits plastic body.
3. Dimension 01 and E1 do not include mold protrusion. Allowable
protrusion is .010 inch 1.245mml.
4. Details of pin 1 identifier are optional but must be located within the
zone indicated.
5. Dimension N: number of terminals.
6. Dimension NO: number of terminals per package edge.
. 7. Controlling dimension: inch.

Sym

Min

Inches (Millimeters)
Max

A

.165 (4.20)

.180 (4.57)

A,

.900 (2.29)

.120 (3.04)

b

.013 (0.33)

.021 (0.53)

b,

.026 (0.66)

.032 (0.81)

D

.485 (12.32)

.495 (12.57)

D,

.450 (11.43)

.456 (11.58)

E
E,
e

.485 (12.321

.495 (12.57)

.450 (11.43)

.456 (11.58)

Note 3
Note 3
.050 (1.27) Basic
28, Note 5

N

ND
Q

Notes

7, Note 6
.020 (0.51)

Ref. 90X00181

11

llf
:
~~bT
t

~

I

9-58

DATUM PLANE (-H-)

""..,,''''
20183A

Raytheon Semiconductor

For More Informadon caJI1-800-722-7074.

Section 9 - Ordering Information & Packaging

0-8

8-Lead Ceramic Oualln-Line Package

Inches

M""meters

Dimension

Max

Min

A
b1
b2
C1
0
E
E1

.014
.045
.OOB
.220
.290

e

Max

Min

5.08
.58
1.65
.38
10.29
7.87
8.13

.36
1.14
.20
5.59
7.37

.100 SSC

2.54SSC

.125
.140

.200

3.18
3.56

5.08

L1
Q

.015

.060
.055

.38

S
S1

1.52
1.35

.005

a

0°

L

81

.200
.023
.065
.015
.405
.310
.320

.13
15°

0°

15°

8

65-6373

For More Information, can 1-800-722-7074.

Raytheon Semiconductor

9-59

Section 9 - Ordering Information &Packaging

0-14

14-Lead Ceramic Oualln-Line Package
Inches

Millimeters

Dimension
Min

Max
.200
.023
.065
.015
.785
.310
.320

A

b1
b2
C1
D
E
E1

.014
.045
.OOS
.220
.290

e
L
L1
Q

S
S1

a

Min

.36
1.14
.20
5.59
7.37

.100 BSC
.125
.140
.015
.005
0°

Max
5.OS
.58
1.65
.38
19.94

7.87
8.13
2.54BSC

.200
.060
.098
15°

3.18
3.56
.38
.13
0°

5.OS
1.52
2.49
15°

t - - - - D -----+I

51-1

65-6379

9-60

Raytheon Semiconductor

For More Information. call1.aoo-722-7074.

Section 9 - Ordering Information & Packaging

0-16

16-Lead Ceramic Oualln-Line Package
Millimeters

Inches
Dimension
Min
A

b1
b2
C1
0
E
E1

.014
.045
.008
220
.290

Max
.200
.023
.065
.015
.840
.310
.320

Min

5.59
7.37

.200

3.18

.36
1.14
.20

.100 esc

e
L

.125

L1

.140

a

.015
.005
O·

.38
21.34
7.87
8.13
2.54 esc

.38

5.08

1.52

.098

a

1.65

3.56
.060

5
51

Max
5.08
.58

2.49
.13

15·

O·

15·

14--- 0---1

A
~.
S1~

.i..Aa

S

E

J:"T
L L1

E1

c.-\\-

For More Information, call 1-800-722-7074.

65-6382

Raytheon Semiconductor

9-61

Section 9 - Ordering Information & Packaging

0-18

18-Lead Ceramic Oualln-Line Package
Inches

M""meters

Dimension
Min
A

b1
b2

C1
0
E
E1

.014
.045
.008
.220
.290

.36
1.14
.20

.840
.310
.320

5.59
7.37

.100 esc

e
L
Ll

.125

a

.015

.200

.005

a

D·

1.65
.38
21.34
7.87
8.13

3.18

5.08

3.56
.060

.38

.098

51

5.08
.58

2.54 esc

.140

5

Max

Min

Max
.200
.023
.065
.015

1.52
2.49

.13
15·

D·

15·

14--- D ---./

51

5

bl

9-62

65-6384

Raytheon Semiconductor

For More Information. call 1-800-722-7074.

Section 9 - Ordering Information &Packaging

0-20

20-Lead Ceramic Dual In-Line Package
Inches

Millimeters

Dimension
Min

A
b1
b2
C1
0
E
E1

Max
.200
.023
.065
.015
1.060
.310
.320

.014
.045

.oos
.220
.290

e
.125

L1

.125

Q

.015

J~::::~::i
~

5.59
7.37
2.54 BSC

.200

3.18

.005

a

o·

5.08

3.56
.070

.38

.080

81

Max
5.08
.58
1.65
.38
26.92
7.87
8.13

.36
1.14
.20

.100 BSC

L

8

81

Min

1.78
2.03

.13
15·

o·

15·

8

6~386

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

9-63

Section 9 - Ordering Information &Packaging

0·24

24-Lead Ceramic Oualln·Line Package (0.3" Wide)
Inches

M""meters

Dimension
Min

Max

Min

Max
5.08

b1

.014

.200
.023

.36

.58

b2

.045

.065

1.14

1.65

C1

.008

.015

.20

A

D

.38

1.280

E

.220

E1

.290

e

32.51

.310

5.59

.320

7.37

.100 BSC

L

.125

L1

.140

Q

.015

5
.005

a

0

0

8.13
2.54 BSC

.200

3.18

5.08

3.56
.060

.38

.080

51

7.87

1.52
2.03

.13
15

0

00

150

1 + - - - - - 0 ----~

51

5

"PW
~

+l j.- b2

L L1

-. e

-1-1b1

9-64

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

Section 9 - Ordering Information & Packaging

D-24W 24-Lead Ceramic Dual In-Line Package (0.6" Wide)
Inches

Millimeters

Dimension
Min

A
b1
b2
Cl

Min

.014

Max
.225
.023

.36

.58

.045

.065

1.14

1.65

.008

.015

.20

.38

D

Max
5.72

1.290

32.77

E

.500

.610

12.70

15.47

El

.590

.620

14.99

15.75

e

.100 SSC

L

.120

l1

.135

a

.015

2.54 SSC
.200

3.05

.075

8

.38

.098

81

.005

a

O·

5.08

3.43
1.91
2.49
.13
15·

o·

15·

s.J~:::~:::::1s
65-6390

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

9-65

Section 9 - Ordering Information & Packaging

F-16

16-Lead Ceramic Gull Wing Flat Pack
Millimeters

Inches
Dimension

A
A1

Min
.090
.023

Max
.133
.033

Min
2.28

Max
3.38

0.58

0.84

b

.013

.017

0.33

C

JJ07

JJ10

0.178

D

.675

.685

17.15

D11E1

.442

.458

11.23

.065

1.27

e
L

0.25
17.40
11.63
1.27 BSC

.05B5O
.050

0.43

1.65

Index ""\.

+

f

j~

9-66

D

f
01

~

JIt= =lIl
E1

[A1

I
*

~

--':1---+1-=Jj-±so

Raytheon Semiconductor

For More Information, can HI00-722-7074.

Section 9 - Ordering Information & Packaging

F-24

24-Lead Ceramic Flat Pack (Cerpak) Package
Inches

MIllimeters

DImension
A
b

C
0
E

Min
.063
.015
.003
.584
.363

e

Min
1.6-0
.38
.08
14.83
9.22

.050B8C

Q

.250
.026

8
81

.005

L

Max
.090
.019
.006
.621
.377

Max
2.29
.48
.15
15.77
10.03

1.27B8C
.370
.040
.045

6.35
.66

9.40
1.02
1.14

.13

s

--.L

For More Information, call 1-1100-722-7074.

Raytheon Semiconductor

9-67

Section 9 - Ordering Information & Packaging

F·24B 24-Lead Ceramic BOHom-Brazed Flat Pack Package
Inches

Millimeters

Dimension
Min

Max

Min

A

.045

.115

1.14

b

.015

.019

.38

.48

C

.003

.006

0.08

0.15

D

Max
2.92

.640

16.26

E
El

.350

E2

.180

4.57

E3

.030

0.76

.420

9.14

10.67

.450

e

11.43

.050 BSC

1.27BSC

L

.250

.370

6.35

9.40

a

.026

.045

0.66

1.14

S
SI

.045
.005

1.14
0.13

A

9-68

Raytheon Semiconductor

For More Information. caIIl-BOO-722-7074.

Section 9 - Ordering Information & Packaging

L·20

20·Pad Leadless Chip Carrier
Inches

Millimeters

Dimension

A
A1
81
83
DIE

Min
0.064
0.054
0.022

Max
0.086
0.066
0.028

Min
1.63
1.37
0.56

Max
2.18
1.68
0.71

.006

.022

0.15

0.56

0.358

8.69

9.09

0.342

D1/E1

.200 BSC

D2lE2

.100 BSC

D31E3

9.09

.358

e

0.050BSC

h

0.040 REF

1.27 BSe
1.02 REF

J

0.020 REF

0.51 REF

L1

.045

.055

1.14

1.40

L2

.075

.095

1.91

2.41

L3

.003

.015

.008

NDINE

0.38
5

5

A1

-I 1-

I+---E---.!

T

Jx45°
65-6388

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

9-69

Section 9 - Ordering Information & Packaging

L-28

28-Terminal Ceramic Leadless Chip Carrier
Inches

Millimeters

Dimension
Min

Max

Min

Max

A
A1
81

.060
.050
.022

.100
.088
.028

1.52
1.27
0.56

2.54
2.24
0.71

B3

.006

.022

.015

.056

DIE

.442

.460

11.23

11.68

D11E1

.300 BSC

7.62 BSC

D2lE2

.1SOBSC

3.81 BSC
.460

D3lE3

10.21

11.68

8

.OSOBSC

h

.040 REF

1.27 BSC
1.02 REF

j

.020 REF

0.51 REF

L1

.045

.055

L2

.075

.095

1.91

2.41

L3

.003

.015

0.08

0.38

NDINE

7

1.14

1.40

7

L3

9-70

Raytheon Semiconductor

For More Information. can 1-800·722·7074.

Section 9 - Ordering Information & Packaging

M-8

a-Lead Plastic Small Outline Dual In-Line Package
Inches

MIllimeters

Dimension
A
A1
B
e
D
E

Min
.053
.004
.014
.007
.188
.150

e
H
L
IX

h

Max
.069
.009
.020
.010
.197
.158

Min
1.35
.10
.350
.19
4.S0
3.S0

1.27Bse

.050 Bse
.22S
.020
0°
.010

Max
1.75
.20
.450
.22
5.00
4.00

.244
.045
So
.020

5.S0
.50S
0°
.25

6.20
1.14
So
.50

65-6375

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

9-71

Section 9 - Ordering Information &Packaging

M-14

14-Lead Plastic Small Outline Dual In-Line Package
Inches

Millimeters

Dimension

A
A1
B
C
D
E

Min

Max

Min

Max

.053
.004
.014
.007
.336
.150

.069
.008
.019
.009
.344
.158

1.35
0.10
0.36
0.18
8.54
3.81

1.75
0.20
0.48
0.23
8.74
4.01

.244
.020
.045
80

5.79
0.25
0.51
00

e
H
h
L

OC

.050BSC
.228
.010
.020
00

1.27BSC
6.20
0.50
1.14
80

Dimensions conform to JEDEC Specification MS'()12·AB for SO packages.

L

0

A1

~ a:;::=P.1--~
65-6380

9·72

Raytheon Semiconductor

For More Information. call 1-800·722·7074.

Section 9 - Ordering Information &Packaging

M-16

16-Lead Plastic Small Outline Dual In-Line Package
Inches

MIllimeters

Dimension

A
A1
B

C
D
E

Max

Min
.0532
.0040
.013
.0075
.3859
.1497

.0688
.0098
.020
.0098
.3937
.157

1.75
0.25
0.51
0.25
10.00
4.00

0.10
0.33
0.19
9.80
3.80

.050 esc

e

Max

Min
1.35

1.27 BSC

H
h
L
LE
Y

.2284
.0099
.016
.030

.2440
.0196
.050

-

0

00

.004
80

-

5.80
0.25
.40
.76

6.20
0.50
1.27

-

0.10
80

00

-

Notes:
1. Refer \0 applicable &ymbollisl
2. Dimension '0' does not include mold ftash, protrusions of gate burrs. Mold ftash,
protrusions and gate burrs shall not exceed .006 In. (.15 mm) per side.
3. Dimension 'E' does not include interlead ftash or protrusions. Interlead ftash and
protrusions shaD not exceed .101 in. (.25 mm) per side.
4. The chamfer on Ihe body is optional. If it is not present, a visual index feature must
be located wilhin Ihe hatched area.
5. 'L' is Ihe lenglh of terminal for soldering to a substrate.
6. The lead width '8' as measured .014 in. (.36 mm) or greater abowlhe seating
plane, shall not exceed a maximum value of .024 in. (.61 mm).

B
65-6448

For More Information, caD 1-1100-722-7074.

Raytheon Semiconductor

9-73

Section 9 - Ordering Information & Packaging

M-24

24-Lead Plastic Small Outline Dual In-Line Package
Inches

Millimeters

Dimension

A
A1
B
C
0
E
e

H
L

S1
a
N

Min

Max

Min

Max

.092
.003
.014
.009
.598
.290

.105
.012
.020
.013
.614
299

2.34
0.08
0.35
0.23
15.19
7.37

2.67
0.30
0.51
0.32
16.70
7.60

.420
.050

9.98
0.38
0.13
0°

.050 BSC
.393
.015
.005
0°

1.27BSC

8°
24

10.67
1.27

-

8°
24

Notes:
1. Dimensions and toleranclng per ANSI Y14.5 - 1982
2. Contromng dimension: millimeter
3. Index area; a notch or a pin one identification marks hall be located adjacent to pin
one. The manufacturers' identification shall not be used as a pin one identification
mark.
4. The basic pin spacing is .050 (1.27 mm) between centerllnes. Each pin centerline
shall be located within.OO5 (0.13 mm) of its exact longitudinal position relative to pins
1 and 24.
5. AppUes to all four comers (leads number 1, 12, 13 and 24)
6. Twenty·two spaces.
7. All leads: increase maximum Umit by .003 (0.08 mm) measured at the center of the
flat, when lead finish "A" (hot solder dip) Is applied.
8. "0" and "E" are reference datums, and do not include mold flash.
9. Body material: plastic (epoxy).
10. "N" is the number of terminal positions.

65-6447

9-74

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

Section 9 - Ordering Information & Packaging

N-8

8-Lead Plastic Dual In-Line Package

Millimeters

Inches
Dimension
Min

A
B
B1
C
0
E1
E

.014
.030
.OOS
.330
.240
.300

e
L

A1
01
M

Max
.200
.023
.070
.013
.375
.260
.325

Min

Max

0.36
0.76
0.20
8.38
6.09
7.37

5.OS
0.58
1.78
0.30
9.40
6.60
7.87
2.54BSC

.100 SSC
.125
.015
.005
00

.200
.060
150

3.18
0.38
0.13
00

5.OS
1.52
150

81
65-6372

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

9-75

Section 9 - Ordering Infonnatlon & PaCkaging

N-14

14-Lead Plastic Dual In-Line Package
Inches

Millimeters

Dimension

A
B
B1
C
0
E1
E

Min

Max

Min

Max

.014
.030
.008
.740
.240
.300

.200
.023
.070
.013
.760
.262
.325

0.36
0.76
0.20
18.92
6.10
7.37

5.08
0.58
1.78
0.30
19.18
6.60
7.87

.200
.060
.005
150

3.18
0.38
.013
00

e
L

A1
01
M

2.54BSC

.100 BSC
.125
.015
00

5.08
1.52
150

o

65-6378

9-76

Raytheon Semiconductor

For More Information. cal 1-800-722-7074.

SectIon 9 - Ordering InformatIon & PackagIng

N-16

16-Lead Plastic Cualln-Llne Package
Inches

Millimeters

DImensIon

A
B
B1
C
D

E1
E

MIn

Max

MIn

.014
.030
.OOS
.740
.240
.300

.200
.023
.070
.013
.760
.262
.325

0.36
0.76
0.20
18.80
6.10
7.37

e
L

A1
01
M

.100 BSC
.125
.015
.005
00

Max
5.08
0.58
1.78
0.30
19.30
6.60
7.87
2.54BSC

.200
.060
150

3.18
0.38
0.13
00

5.OS
1.52
150

61
65-6381

For More Information, caD 1-800-722.7074.

Raytheon Semiconductor

9·77

Section 9 - Ordertng information & Packaging

N-20

2O-Lead Plastic Dual In-Line Package
Inches

Millimeters

Dimension

A
81
C
0
E1
E
L

Min

Max

Min

Max

.014
.008
.995
.245
.290
.115

.210
.023
.Q12
1.065
.310
.320
.150

.36
.211
5.27
6.22
7.37
2.92

5.33
.58
.30
27.05
7.87
8.13
3.81

e
A1
01
M

.1...1.

-I

0

~~Al
B

8

B1

2.548SC

.100 BSC
.015
.005
0°

15°

0.38
.13
0°

15°

~
Jt:-1-c
6S~5

9-78

Raytheon Semiconductor

For More Information, call 1-800·722-7074.

Section 9 - Ordering Information & Packaging

N-20W 20-Lead Plastic Dual In-Line Package (0.6" Wide)
Inches

Millimeters

Dimension
Min

A
B
B1
e
D
E1
E

.014
.030
.008
1.24
.530
.590

e
L

A1
D1
M

Max
.225
.023
.070
.012
1.26
.550
.620

0.36
0.76
0.20
31.5
13.46
14.99
2.54Bse

.100 Bse
.200
.075

.120
.015
.005
0°

Max
5.72
0.58
1.78
0.30
32.0
13.97
15.78

Min

15°

3.05
0.38
0.13
0°

5.08
1.91
15°

o

65-6389

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

9-79

Section 9 - Ordering Information & Packaging

N-24N 24-Lead Plastc Dual In-Line Package (0.3" Wide)
Notes
1. Controlling dimensions are in "inches"
2. Dimesioning and tolerancing per ANSI

Inches

Millimeters

Dimension

Y14.5M·1982.

Min

3.

Dimensions "A", "A 1" and "L" are measured
with the package seated in the Seating
Plane.
4. "0" an d "E1" dimensions for plastic
packages, do not include modi flash or
protrusions. Mold tlash or protursions shall
not exceed .010 inch (0.25 mm).
5. "E" and "eA" measured with the leads
constrained to be perpendicular to the base
plan.
6. "eS" and "eC" are measured at the lead tips
with the leads unconstrained. "eC" must be
zero or greater.
7. The basic pin spacing os .100 inch (2.54
mm) between centerlines. Each pin
centerline shall be located within ±010 inch
(0.25 mm) of its exact longitudinal position
relative to pins 1 and 24.
8. All leads: increase maximum Omit I7f .003
inch (0.08 mm) measured at the center of
the flat, when lead finish "A" (hot solder dip)
is applied.
9. "N" is the maximum number of lead
positions.
10. Eleven spaces.

A
A1
A2

B
B1
e
0
01
E
E1

Min

Max

5.33

.210
.015
.115
.014
.045
.008
1.125
.005
.300
.240

e

.195
.022
.070
.015
1275
0.13
.325
.280

0.38
2.92
0.36
1.14
0.20
28.58

4.95
0.56
1.78
0.38
32.39

7.62
6.1

8.26
7.11
2.54BSe
7.62BSC

.100 BSe
.300BSe

eA
eB
L
N

Max

.115

.430
.160
24

2.92

1Q.92
4.06
24

1+----0----+1
Sase
Plane
Seating
Plane

65-6446

9·80

Raytheon Semiconductor

For More Information, can 1-800·722·7074.

SectIon 9 - OrderIng InformatIon & PackagIng

8-16

16-Lead Ceramic Sidebraze Dual In-Line Package
Millimeters

Inches
DImensIon
MIn

Max

A

b1
b2

C1
0
E
E1
e
L
L1
Q

S
S1

52

14---

0

.014
.045
.008
.200
.290

.310

.200
.023
.065
.015
.840
5.59
.320

MIn

.36
1.14
.20

.005
.005

1.65
.38
21.33
7.87
8.13

7.37

.100 BSC
.125
.140
.015

Max

5.08
.58

2.54BSC
.200
.060
.098

3.18
3.57
.33

5.08
1.52
2.49

.13
.13

----.I

81-1
~

82

~

.

t ¥
f ~'
~t
b1

b2
65-6383

For Mora Information, call 1-800-722-7074.

Raytheon Semiconductor

9-81

Section 9 - Ordering Information & Packaging

S-20

20-Lead Ceramic Sidebraze Dual In-Line Package
Inches

Millimeters

Dimension
Min
A
b1
b2
C1
0
E
E1

e
L
L1

Max
.200
.023
.065
.015
1.060
.310
.320

.014
0.45
.008
.220
.290

Min

.36
1.14

5.59
7.37

.100 SSC

a

.125
1.40
.015

S
S1
S2

.005
.005

Max
5.08
.58
1.65
.38
26.92
7.87
8.13

2.54SSC
.200
.070
.080

3.18
3.57
.38

5.08
1.78
2.03

.13
.13

1 - - - - 0 _ _-1

82

65-6387

9-82

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

Section 9 - Ordering Information Be Packaging

S-24

24-Lead Ceramic Sidebraze Dual In-Line Package (0.3" Wide)
Inches

MIllimeters

Dimension

Max

Min
A

Max

Min

5.08

.225

.014

.023

.36

.58

b2

.045

.065

1.14

1.65

Cl

.008

.015

.20

b1

.38

1.280

D

E

.220

El

.290

e

32.51

.310

5.59

.20

7.37

.100SSC

L

.125

L1

.125

Q

.015

8

72.7
8.13
2.54 SSC

.200

3.18

5.08

3.56
.060

.38

1.52
2.03

.080

81

.005

.13

S2

.005

.13

! e - - - - 0 ---~

81-1

For More Information, call 1-800-722-7074.

Raytheon Semiconductor

9-83

SectIon 9 - Ordering InformatIon & PackagIng

T-8

8-Lead TO-99 Metal Can
Millimeters

Inches
DImensIon
A

b
b1
D
D1
102
e
e1

Max

MIn
.165
.016
.016
.335
.305
.110

.185
.019
.021
.375
.335
.160
.200BSO
.100 BSO

.027
.500

L2
Q

.250
.010

Max

4.70
.48
.53
9.53
8.51
4.06
5.08BSO
2.54BSO

.040
.034
.045
.750
.050

F

K
K1
L
L1

a

MIn
4.19
.41
.41
8.51
7.75
2.79

1.02
.86
1.14
19.05
1.27

.69
.69
12.7
6.35

.045
450BSC

1.14

.25

450BSO

Reference Plane

85-8374

9-84

Raytheon Semiconductor

For More Information, cal 1-800-722-7074.

Section 9 - Ordering Information & Packaging

T-9

9-Lead TO-66 Metal Can
Inches

Millimeters

Dimension

A

B
C

Min
.250
.028
.360

.620
.500

D
E

G
J
K
L
M

.300
.050
.142

~A

-

fr-

!Ll
....

1.90
3.86
3.68
12.26

12.11
36°Typ

.962
1.252
.700

24.33

24.43
31.80
17.80

C-'

r

D E

1.27
3.60

36°Typ
.958

15.748
12.70
5.84BSC

.075
.152
.145
.483

.477

Max
8.63
.863

7.62

.325BSC

N

P
R
S

Min
6.35
.71
9.14

Max
.340
.034

~

r
p

65-6376

For More Information, call 1-800·722·7074.

Raytheon Semiconductor

9·85

Section 9 - Ordering Information & Packaging

1-10

10-Lead 10-100 Metal Can
Inches

Millimeters

Dimension
A
b
b1
D
D1
02

e
e1
F
K
K1
l
l1
l2
Q
IX

Max

Min
.165
.016
.016
.335
.305
.110

.185
.019
.021
.375
.335
.160
.230Bse
.115 Bse

.250
.010

.045
36°Bse

4.70
.48
.53
9.53
8.51
4.06
5.84Bse
2.92Bse

.040
.034
.045
.750
.050

.027
.027
.500

Max

Min
4.19
.41
.41
8.51
7.75
2.79

1.02
.86
1.14
19.05
1.27

.69
.69
12.70
6.35
.25

1.14
36°Bse

Reference Plane
Base and Seating Plane

~b1

65-6377

9-86

Raytheon Semiconductor

For More Information, call 1-800-722-7074.

........

Semiconductor
350 Ellis St.
Mountain View, CA 94043
(415) 968-9211
From San Jose Airport:
Take 101 North to Ellis Street Exit.
Left on Ellis. Raytheon Semiconductor is on the right side of the street.
(350 Ellis Street, Mt. View.)

Raytheon Semiconductor - La Jolla

~

University of Ccllfomla

San Diego

Raytheon Semconductor - La JoDa
4243 Campus Point Court
San DIego. CA 92121

I

To Raytheon Semiconductor from Lindbergh Field (San Diego Airoort): &.it the ~ going TOWARD SAN DIEGO. Go North on
Interstate S (follow Harbor Drive - LEFT on Grape. LEFT on Albalross (under Freew!y)•.~ss Hawthorn and enter the free!'8Y). Exit
Interstate S at the Genesee Ave offramp~(13 miles north of San Diego) and tmn right \~). Proceed up the hill 10 Cam~ Pomt Drive
(second s1ODli2ht) and tmn left. Go 10 ~ampus Point Court (the firSt street) and tIim left. Rayt\leon Seiniconductor is on the left side of
tbe street Pail: in front of the building (first driveway) at the far end of the lot in visitors' paiting and enter the front lobby.
To Lindberg!! Field (San Diego Airp<>q) from Ravtheon Semiconductor: Proceed south on Interstate S from Genesee. Use the Sassafras
Street exit, which aciually puts you on Kettner Bfvd. Tum right on Laurel Street, and follow the signs 10 the aitpOO terminal or car
rental return.
24413A

Notes

Raytheon Semiconductor

Notes

Raytheon Semiconductor

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o
0
o

Signal Synthesis
Avionics Communication
Data Conversion
Other _ __

o
o
o
o
o

Digital Signal Processing
Linear
PROM
Small Signal Transistors
32 von Linear Arrays

o
o

Precision Complementary
Arrays Analog & Mixed
Signal (RPA Family)
Precision Complementary
BiCMOS Standard Cell
Family (RSC4000)

BUSINESS REPLY MAIL
FIRST CLASS

PERMIT NO. 4n

NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES

MOUNTAIN VIEW, CALIFORNIA

Postage Will Be Paid By Addressee:

Raytheon Company
SEMICONDUCTOR DIVISION
PO BOX 7016
MOUNTAIN VIEW, CA 94039-7016

1111111111111111111111111111111111111111111111111111
--~-----------------------~-----

BUSINESS REPLY MAIL
FIRST CLASS

PERMIT NO. 4n

MOUNTAIN VIEW, CALIFORNIA

Postage Will Be Paid By Addressee:

Raytheon Company
SEMICONDUCTOR DIVISION
PO BOX 7016
MOUNTAIN VIEW, CA 94039-7016

11111111111111111111111111111111111111111111111111 II

NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES

Raytheon Sem iconductor Headquarters
Raytheon Company
Semiconductor Division
350 Ellis Street
P.O. Box 7016
Mountain View, CA 94039-7016
Telephone: (415) 968-9211
Literature: (800) 722-7074
Cust. Svc.: (408) 522-7051
FAX: (415) 966-7742

Raytheon Company
Semiconductor - La Jolla
P.O. Box 2472
La Jolla, CA 92038-2472
Telephone: (619) 457-1000
(800) 879-5747
FAX: (619) 455-6314
Internet: applications @ Ij.sd.ray.com
sales @ Ij.sd.ray.com

Raytheon Semiconductor Regional Sales Offices
CALIFORNIA (Southwest)
Raytheon Semiconductor
10A Goodyear
Irvine, CA 92718
(909) 699-7194
FAX: 714-830-2607

FLORIDA
Raytheon Semiconductor
130 Ridgewood Drive
Longwood, FL 32779
(408) 682-6988
FAX: (407) 682-6404

MASSACHUSETIS
Raytheon Semiconductor
63 Second Avenue
Burlington, MA 01803
(617) 272-1313
FAX: 617-270-7965

CALIFORNIA (Northwest)
Raytheon Semiconductor
760 North Mary Ave.
Sunnyvale, CA 94086
(408) 522-7060
FAX: 408-522-7055

ILLINOIS
Raytheon Semiconductor
1430 Branding Lane #129
Downers Grove, IL 60515
(708) 810-1577
FAX: (708) 810-1683

NEW YORK
Raytheon Semiconductor
300 Vanderbilt Motor Parkway #200
Hauppauge, NY 11788
(516) 231-1090
FAX: (516) 231-1294

Raytheon Semiconductor International Sales Offices
UNITED KINGDOM
Raytheon Semiconductor
International Company
Elizabeth Way
The Pinnacles
Harlow, Essex CM19 5AZ
England
Telephone: 44-279-421510
FAX: 44-279-421316
Raytheon Semiconductor
International Company
Pelican House
83 New Street
Andover, Hants. SP10 1DR
England
Telephone: 44-264-334616
FAX: 44-264-334620

GERMANY
Raytheon Semiconductor
International Company
Kathi-Kobus-Str.24/11
D-80797 Munich
Germany
Telephone: 49-89-187053
FAX: 49-89-183758
FRANCE
Raytheon Semiconductor
International France
LaBoursidiere, A3 RN 186
F-92350 Plessis Robinson
Cedex, France
Telephone: 33-1-463-10676
FAX: 33-1-463-24608

JAPAN
Raytheon Semiconductor
International Company
Matsukaze Building 5/F
4-1-1 Kitashinagawa Shinagawa-Ku
Tokyo 140 Japan
Telephone: 81-3-3280-4776
FAX: 81-3-3280-4156

Raytheon Semiconductor

350 Ellis Street
Mountain View CA 94043 7016
8007227074
FAX 415 966 7742

iiayiileon
65-2217

B/93-B-50M

Raytheon Semiconductor

350 Ellis Street
Mountain View CA 94043 7016
8007227074
FAX 415 966 7742

65-2217

8/93-8-50M



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