1994_Silicon_Systems_Communications_Products 1994 Silicon Systems Communications Products
User Manual: 1994_Silicon_Systems_Communications_Products
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FIRST CLASS
CAR-RT SORT
COMMUNICATIONS
PRODUCTS
·
···...........•.••..................•.•. ,......
~
Silicon Systems' Santa Cruz facility,
site ofsix-inch wafer fabrication line.
Silicon Systems specializes in the design and manufacture of application-specific,
mixed-signal integrated drcuits (MSICs®). If offers a sophisticated line of custom and
standard ICs aimed primarily at the storage, communications and automotive products
marketp Iace.
The company, which is headquartered in California, 30 miles south of Los Angeles, was
founded in 1972 as a design center. It soon entered into manufacturing and today has
two fabrication sites in California and approximately 2,000 employees worldwide.
Additional operations include assembly and test facil·ities in California and Singapore
and design engineering centers in California as well as in Tokyo and Singapore.
Reliability and quality are built into Silicon Systems' products through the use of
statistical problem solving techniques, analytical controls, and other quantitative
methods. The company is committed to the goal of customer satisfaction through the
on-time del ivery of defect-free products that meet or exceed the customer's expectations and requirements. This statement reflects the corporate quality mission and
contains key elements instrumental in attaining true customer satisfaction. Listed in the
back of this publication is a worldwide network of sales representatives and distributors
ready to serve you.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
NOTICE
All products listed herein and subsequently sold by Silicon Systems, Inc. are covered by the
warranty, limitation of liability and patent indemnification provisions reflected in the Silicon
Systems Order Acknowledgement Form only. Silicon Systems, Inc. makes no warranty,
express or implied, statutory or by description regarding the information set forth herein and/
or freedom from patent infringement. Silicon Systems, Inc. reserves the right to discontinue
production, change speCifications and prices at any time and without notice.
Applications requiring mechanical and electrical parameters outside of the published
specifications are not recommended without additional review and acceptance by Silicon
Systems, Inc. Silicon Systems, Inc. further assumes no responsibility for the use of any
integrated circuit technology other than integrated circuit technology embodied in a Silicon
Systems, Inc. product. These products are not authorized for use as components in life
support devices or systems. No patents or licenses regarding the integrated circuit technology herein are implied unless otherwise stated.
© Copyright 1994 Silicon Systems, Inc. All rights reserved. Product and company names listed are trademarks of their
respective companies.
K-Series integrated circuits are protected by the following patents:
4,691,172/4,777,453/4,847,868/4,866,739/4,870,370 / 4,789,995
Contents
Target, Advanced and
Preliminary Information
In this data book the following conventions
are used in designating a data sheet
''Target,'' "Advanced" or "Preliminary":
Target SpecificationThe target specification is intended as an
initial disclosure of specification goals for
the product. Product is in first stages of
design cycle.
Advance InformationIndicates a product still in the design cycle,
undergoing testing processes, and any
specifications are based on design goals
only. Do not use for final design.
Preliminary DataIndicates a product not completely released to production. The specifications
are based on preliminary evaluations and
are not guaranteed. Small quantities are
available, and Silicon Systems should be
consulted for current information.
III
Index
Page #
Contents ................................................................................................................................................... 111
Index ........................................................................................................................................................ IV
Numerical Product Index ........................................................................................................................ VII
Discontinued Parts List ........................................................................................................................... VII
Product Selector Guide .........................................................................................................................VIII
Section 1.
CUSTOM SOLUTIONS ................................................................................................................ 1-0
Section 2.
QUALITY ASSURANCE AND RELIABILITY .............................................................................. 2-0
Section 3.
K-SERIES SINGLE-CHIP MODEM FAMILY
K-Series Modem Family Introduction ......................................................................................................................3-0
Bell 212A11 03 Single-Chip Modem ...........................................................................................3-1
73K212L
73K221 L
CCITT V.22, V.21 Single-Chip Modem ................................................................................... 3-21
73K222L
V.22, V.21, Bell 212A Single-Chip Modem ............................................................................. 3-43
73K222U
Single-Chip Modem with UART .............................................................................................. 3-65
73K224L
V.22bis Single-Chip Modem .................................................................................................3-105
73K302L
Bell 212A, 103, 202 Single-Chip Modem .............................................................................. 3-133
CCITT V.23, V.21 Single-Chip Modem ................................................................................. 3-157
73K312L
73K321 L
CCITT V.23, V.21 Single-Chip Modem ................................................................................. 3-177
CCITTV.23, V.22, V.21 Single-Chip Modem ........................................................................ 3-197
73K322L
73K324L
CCITTV.22bis, V.22, V.21, V.23 Single-Chip Modem .......................................................... 3-219
Section 4.
NEW
NEW
NEW
Section 5.
MODEM PROTOCOL & BUS INTERFACE PRODUCTS
73D246
73D2240
73D2247
73D2248/2348
73D2910
73D2950
73M550/1550/
2550
SPECIAL MODEM PRODUCTS
73M223
73M376
Section 6.
Microcontroller ..........................................................................................................................4-1
V.22bis 2400 Bitls Low Power Modem Device Set.. ...............................................................4-37
MNP5, V.42bis, Datacom Modem Device Set ..............................................................................•
MNP5 Datacom Modem Device Set .......................................................................................4-61
Microcontroller ......................................................................................................................... 4-71
Microcontroller ........................................................................................................................4-75
Universal Asynchronous ReceiverlTransmitter with FIFOs .................................................. 4-1 07
1200 Baud FSK Modem ............................................................................................................ 5-1
K-Series Integrated Line Interface Unit ..................................................................................... 5-7
ANALOG SIGNALLING & SWITCHING PRODUCTS
75T201
75T202l203
75T204
75T2089/90/91
75T980
78A093A1B
78A207
Integrated DTMF Receiver ....................................................................................................... 6-1
5V Low-Power DTMF Receiver ................................................................................................ 6-9
5V Low-Power Subscriber DTMF Receiver ............................................................................ 6-17
DTM F Transceivers ................................................................................................................ 6-25
Call Progress Tone Detector ................................................................................................... 6-33
12 x 8 x 1 Crosspoint Switch with Control Memory ...................................................................... .
MFR1 Receiver .......................................................................................................................6-39
* Data Sheet available upon request.
IV
Page #
Section 7.
PCM PRODUCTS
78P233A
78P234
78P236
78P2361
78P2362
78P300
78P304A
78P7200
Section 8.
NEW
Section 9.
NEW
Section 10.
DS-1 Une Interface ....................................................................................................................... *
2048 KBiVs PCM Interface Unit .................................................................................................... *
DS-3 Une Interface ................................................................................................................... 7-1
STS-1 Line Interface ............................................................................................................... 7-11
34.368 MbiVs Line Interface .................................................................................................... 7-21
T1/E1 Short-Haul Transceiver with Receive Jitter Attenuation ............................................... 7-31
Low-Power T1/E1 Integrated Short Haul Transceiver with Receive Jitter Attenuation ........... 7-47
DS-3 Line Interface with Receive Equalizer ............................................................................ 7-65
LAN PRODUCTS
78Q902
78Q903
78Q8330
78Q8360
78Q8370
78Q8373
Ethernet Twisted-Pair Media Attachment Unit .......................................................................... 8-1
1OBase-T Hub Transceiver ........................................................................................................... *
Ethernet Coaxial Transceiver ..................................................................................................8-15
Ethernet Controlier/ENDEC Combo ........................................................................................8-27
PCMCIA Ethernet Combo .......................................................................................................8-63
3V/5V PCMCIA Ethernet Combo .......................................................................................... 8-103
PROGRAMMABLE ELECTRONIC FILTERS
32F8001
32F8002l8003
32F8011/8012
32F8020/8022
32F8020Al8022A1
8021/8023
32F8030
32F81 01/81 021
8103/8104
32F8120
32F8130/8131
32F8144
Low-Power Programmable Electronic Filter .............................................................................. 9-1
Low-Power Programmable Electronic Filter ............................................................................ 9-13
Programmable Electronic Filter ...............................................................................................9-23
Programmable Electronic Filter .................................................................................................... *
Low-Power Programmable Electronic Filter ............................................................................ 9-35
Programmable Electronic Filter ...............................................................................................9-47
Low-Power Programmble Electronic Filter .............................................................................. 9-57
Low-Power Programmable Electronic Filter ............................................................................ 9-69
Low-Power Programmable Electronic Filter ............................................................................ 9-77
Programmable Electronic Filter ............................................................................................... 9-85
PACKAGING/ORDERING INFORMATION
Package Index
................................................................................................................................................ 10-1
Ordering Information ............................................................................................................................................. 10-2
Plastic DIP 8,14,16 and 18 Pins .......................................................................................................................... 10-3
Plastic DIP 20, 22,24 and 24S Pins ..................................................................................................................... 10-4
Plastic DIP 28, 32 and 40 Pins ..............................................................................................................................10-5
Cerdip 8, 14, 16 and 18 Pins ................................................................................................................................. 10-6
Cerdip 22, 24 and 28 Pins .....................................................................................................................................10-7
Quad (PLCC) 20 and 28 Leads ............................................................................................................................. 10-8
Quad (PLCC) 32 and 44 Leads ............................................................................................................................. 10-9
Quad (PLCC) 52 and 68 Leads ........................................................................................................................... 10-10
Quad Flatpack (QFP) 52, 100 Leads .................................................................................................................. 10-11
Quad Flatpack (QFP) 128 Leads ........................................................................................................................10-12
Thin Quad Flatpack (TQFP) 32, 48 Leads .......................................................................................................... 10-13
Thin Quad Flatpack (TQFP) 64 Leads ................................................................................................................ 10-14
Thin Quad Flatpack (TQFP) 100 Leads .............................................................................................................. 10-14
Thin Quad Flatpack (TQFP) 120 Leads .............................................................................................................. 10-15
Thin Quad Flatpack (TQFP) 128 Leads .............................................................................................................. 10-15
Very Thin Quad Flatpack (VTQFP) 48 and 64 Leads ......................................................................................... 10-16
Very Thin Quad Flatpack (VTQFP) 100 Leads ................................................................................................... 10-17
Very Thin Quad Flatpack (VTQFP) 120 Leads ..................................................................................................... 10-1
Ultra Thin Quad Flatpack (UVQFP) 64 and 100 Leads ....................................................................................... 10-19
(Continued)
* Data Sheet available upon request.
V
Section 10.
PACKAGING/ORDERING INFORMATION (continued)
Page #
SON 8, 14 and 16 Leads .....................................................................................................................................10-20
SOL 16, 18, 20, 24 and 28 Leads ....................................................................................................................... 10-21
SOL 34 Leads
.............................................................................................................................................. 10-22
SOW 32 Leads
..............................................................................................................................................10-22
SOM 36 Leads
..............................................................................................................................................10-22
.............................................................................................................................................. 10-23
SOM 44 Leads
VSOP 20, 24 Leads .............................................................................................................................................10-23
VTSOP 16, 20 Leads .......................................................................................................................................... 10-24
UTSOP 20, 36 Leads .......................................................................................................................................... 10-25
Small Form Factor Package Selector Guide ....................................................................................................... 10-26
Section 11.
SALES OFFICES/DISTRIBUTORS ............................................................................................ 11-1
Section 12.
APPLICATION NOTES AND GLOSSARY
K-Series Application Notes
NEW
NEW
NEW
K-Series General Application Notes ...................................................................................................................... 12-1
- Setting DTMF Levels for 1200 Bitls K-Series Modems ...................................................................................... 12-5
- SSI 73K212A High Speed Connect Sequence .................................................................................................. 12-6
- V.22 & V.22bis Connect Sequences .................................................................................................................. 12-7
- Remote Loop Handshake Sequence ................................................................................................................. 12-8
- SSI 73K224L Retrain at 2400 bitls ..................................................................................................................... 12-9
- SSI 73K212, 73K222 Originate & Answer Handshake Sequences ................................................................. 12-10
- SSI 73K224L Originate & Answer Handshake Sequences .............................................................................. 12-12
- Modem Performance Testing ........................................................................................................................... 12-14
- Troubleshooting the Modem Design ................................................................................................................ 12-20
73M376 Integrated Line Interface Application Note ............................................................................................ 12-23
78P236/2361/236217200 Demo Board Application Note ..................................................................................... 12-27
7808330 Demo Board Application Note ............................................................................................................. 12-37
7808360 Technical Reference Guide ......................................................................................................................... .
7808370 Technical Reference Guide ................................................................................................................. 12-41
DTMF Receiver Application Guide ...................................................................................................................... 12-85
7809001 UCJ - DAA Micromodule Design Guide ............................................................................................... 12-99
7809002 Superintendent DAA Micromodule DeSign Guide ............................................................................. 12-111
GLOSSARY ........................................................................................................................................_............. 12-123
Voiceband Modem Standards Reference Chart ................................................................................................ 12-135
* Data Sheet available upon request.
VI
Numerical Index
SSI Device Numbers
Page #
SSI Device Numbers
32F8001 .......................................•........................................ 9-1
32F8002l8003 ..................................................................... 9-13
32F8011/8012 ........................................................: ............ 9-23
·32F8020/8022 ....•......••.............................................................. *
32F8020Al8022A18021/8023 .............................................. 9-35
32F8030 ..........................................................................•... 9-47
32F81 01/81 02181 03/81 04 ................................................... 9-57
32F8120 .............................................................................. 9-69
32F8130/8131 ......................•.............................................. 9-77
32F8144 .............................................................................. 9-85
730246 .................................................................................. 4-1
7302240 .............................................................................. 4-37
7302247 .................................................................................... *
7302248/2348 ..................................................................... 4-61
730291 0 .............................................................................. 4-71
7302950 .............................................................................. 4-75
73K212L ................................................................................ 3-1
73K221 L .............................................................................. 3-21
73K222L .............................................................................. 3-43
73K222U ............................................................................. 3-65
73K224L ............................................................................ 3-105
73K302L ...........................••............................................... 3-133
73K312L ............................................................................ 3-157
73K321 L ............................................................................ 3-177
73K322L ............................................................................ 3-197
Page #
73K324L ............................................................................ 3-219
73M223 ....................................................•......•.•.................... 5-1
73M376 .........................................................................•........ 5-7
73M550/1550/2550 ........................................................... 4-107
75T201 .................................................................................. 6-1
75T202l203 ........................................................................... 6-9
75T204 ................................................................................ 6-17
75T2089/90/91 .................................................................... 6-25
75T980 ................................................................................ 6-33
78A093A1B ................................................................................ *
78A207 ................................................................................ 6-39
78P233A ................................................................................... *
78P234 ...................................................................................... *
78P236 .................................................................................. 7-1
78P2361 .............................................................................. 7-11
78P2362 .............................................................................. 7 -21
78P300 ................................................................................ 7-31
78P304A .............................................................................. 7-47
78P7200 .............................................................................. 7 -65
780902 .................................................................................. 8-1
780903 ..................................................................................... *
7808330 .......................................................................•...... 8-15
7808360 .............................................................................. 8-27
7808370 .............................................................................. 8-63
7808373 ............................................................................ 8-103
*Data Sheet available upon request.
Discontinued Parts List
The following parts are no longer supplied or supported by Silicon Systems.
Part #
73D2180
73D2404
73D2420/2421
73D2247F
73K212 (12V Version)
73K221 (12V Version)
73K222 (12V Version)
73M214
73M450U1450/2450
73M650/1650
75T957
75T981
75T982
78P8050
78P8060
VII
COMMUNICATION PRODUCTS REFERENCE
Device Number
8212
8103
1202
CCITT
V.21
CCITT
V.23
CCITT
V.22
CCITT
V.22bis
Description
PoW'er
Supply
Available
Packages
K-SERIES SINGLE CHIP MODEM FAMILY
SSI73K212L
~
Low Power 73K212
+5V
SSI73K212SL
~
73K212L with serial interface only
+5V
22 DIP
SSI73K221L
SSI 73K221 SL
~
~
Low Power 73K221
+5V
22, 28 DIP, 28 PLCC
~
~
73K221 L with serial interface only
+5V
22 DIP
SSI73K222L
~
~
~
Low Power 73K222
+5V
22, 28 DIP, 28 PLCC
SSI 73K222SL
~
~
~
73K222L with serial interface only
+5V
22 DIP
SSI73K222U
~
~
~
73K222L with 16C450 UART
+5V
40 DIP, 44 PLCC
SSI73K224L
~
~
~
~
Bell 212A/1 03, CCiTT V.22bis/V.22/V.21
+5V
SSI 73K224SL
~
~
~
~
73K224L with serial interface
+5V
28 DIP, 28, 32 PLCC,
52 QFP, 64 TQFP
22 DIP
SSI73K302L
~
~
Bell 212A/202/103
+5V
28 DIP, 28 PLCC
SSI 73K302SL
~
~
Bell 212A/202/1 03; serial interface only
+5V
22 DIP
B103
~
SSI73K312L
~
28 DIP, 28 PLCC
~
~
BELL 202/103; CCITT V.21 /V.23
+5V
SSI73K321L
~
~
CCiTT V.23/V.21
+5V
28 DIP, 28 PLCC,
52 QFP, 64 TQFP
28 DIP, 28 PLCC
SSI 73K321 SL
~
~
73K321 L with serial interface only
+5V
22 DIP
SSI73K322L
~
~
~
CCITT V.23/V.22/V.21
+5V
28 DIP, 28 PLCC
SSI 73K322SL
~
~
~
73K322L with serial interface only
+5V
22 DIP
~
~
~
CCiTT V.22bis/V.22/V.23/V.21
+5V
SSI73K324L
B212
~
28 DIP, 28, 32 PLCC,
52 QFP, 64 TQFP
MODEM PROTOCOL PRODUCTS! DEVICE SETS
SSI73D246
SSI73D2240
SSI73D2247
SSI 73D2248/2348
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
SSI73D2910
SSI 73D2950/2950T
~
+5V
+5V
+5V
+5V
Various QFP & TQFP
Various DIP & PLCC
Various DIP & PLCC
Various QFP & TQFP
Modem Controller Device
+3V/+5V
Various QFP & TQFP
FAX/Data Modem Device Set = W / AT, MNP485 V.42, V.42 bis
+3V/+5V
Various QFP & TQFP
Modem
Modem
Modem
Modem
Controller Device
Device Set w/ AT (73K224L based design)
Device Set w/ AT, MNP 4&5
Device Setw/ AT, MNP
EIA - 57F Class I, Industry Class II. Truespeech Voice Compression
Notes:
The SSI 73D2247 Device Set comes with a Configurable Command Interpreter.
- - -
- - -
- - -
----
- - -
Device Number
Circuit Function
Features
Power
Available Packages
SPECIAL MODEM PRODUCTS
551 73M223
1200 bit/ s Modem IC
Compact HDX V.23 modem
+5V
16 DIP, 16 SOL
551 73M376
Integrated Line Interface
The active components of a DAA in a chip used on 73M9001
+5V
28 PLCC, 24 VSOP
ANALOG SIGNALLING AND SWITCHING PRODUCTS
551 75T201
Integrated DTMF Receiver
Binary coded 2-of-8 output
+12V
22 DIP
551 75T202
Integrated DTMF Receiver
Low power, binary output
+5V
18 DIP
551 75T203
Integrated DTMF Receiver
Early detect, binary output
+5V
18 DIP
551 75T204
Integrated DTMF Receiver
Low power, binary output
+5V
14 DIP, 16 SO
551 75T2089
Integrated DTMF Transceiver
Generator & receiver, ~ interface
+5V
22 DIP
551 75T2090
Integrated DTMF Transceiver
Like 75T2089 w/ call progress detect
+5V
22 DIP
551 75T2091
Integrated DTMF Transceiver
Like 75T2090 w/ early detect
+5V
28 DIP, PLCC
551 75T980
Imprecise Call Progress Detector
Energy detect in 305-640 Hz band, Teltone
+5V
8 DIP
551 78A093A/B
12x8x 1 Crosspoint Switch
Low ON resistance, two versions
551 78A207
Integrated MF Receiver
Detects central office toll signals
551 78P236
DS-3 Line Interface
T3 clock & data recovery, transmit equalization
+5V
28 DIP
551 78P2361
STS-l Line Interface Transceiver
STS-l clock & data recovery, transmit equalization
+5V
28 DIP
551 78P2362
CEPT E-3 Line Interface Transceiver
E3 clock & data recovery, transmit equalization
+5V
28 DIP
551 78P300
Tl /E 1 Short Haul Transceiver
Receive jitter attenuation
+5V
28 DIP, PLCC
551 78P304A
Low-Power 38P300
Receive jitter attenuation
+5V
28 DIP, PLCC
551 78P7200
DS-3 Line Interface Transceiver
DS-3 Transceiver w/Receive equalization & higher transmitter drive
+5V
28 DIP
551780902
1OBase-T MAU Transceiver
Direct interface to twisted pair and AUI
+5V
28 DIP, PLCC
551780903
1OBase-T Hub Transceiver
Programmable squelch, detect/correct reverse polarity
+5V
24 DIP, 28 PLCC
+5, +12V
40 DIP, 44 PLCC
PCM PRODUCTS
x
LAN PRODUCTS
5517808330
802.3 Coax Transceiver
1OBase-2 applications
+9V
20 DIP, PLCC, 64 TQFP
5517808360
Ethernet Controller/ENDEC Combo
Fully integrated MAC ENDEC & AUI
+5V
100 QFP, TOFP
5517808370
1OBase-T/PCMClA for Ethernet
Single-chip Ethernet for PCMClA card
+5V
5517808373
3V/ 5V 1O-BaseT/PCMCIA for Ethernet
3V or 5V for PCMClA Ethernet
3Vor 5V
l000FP, 100 TOFP
1000FP, TQFP
BUS INTERFACE PRODUCTS
551 73M550
16C550 pin compatible UART
Receive and Transmit FIFOs
+5V
40 DIP, 44 PLCC, 48 GT
551 73M1550
28-pin version of 73M550
Full UART in 28-pin package
+5V
28 DIP, PLCC
551 73M2550
28-pin version of 73M550
Adds ~RST function
+5V
28 DIP, PLCC
Notes:
x
Section
1
CUSTOM
SOLUTIONS
I
1-0
CUSTOM SOLUTIONS
Faster to market for mixed-signal applications
SILICON SYSTEMS LEADS THE WA Y
DEVELOPING MIXED-SIGNAL CUSTOM
PRODUCTS.
Whatever your mixed-signal design application, Silicon
Systems gives you a competitive advantage. In communications, disk drives, other storage products, automotive control
systems, or other analog/digital signal processing applications,
you can depend on our technical know-how to do the job right
and turn your design around faster.
This is a story about leadership. Silicon Systems is dedicated to taking the point in the creation of high-performance,
application-specific custom, mixed-signal integrated circuits
(MSICs®).
CMOS. Bipolar. BiCMOS. Analog. Digital.
We've done it
Such dedication means we bring a lot to the party. Including truly innovative analog, digital, and mixed analog/digital
ICs. A full complement of mixed-signal CMOS, SiCMOS and
Bipolarwaferfabrication processes, state-of-the-art automated
design tools, production, assembly, test, and QA capability.
Our designers are an experienced bunch. They're uniquely
able to take a look at your specific application problem and
move quickly to the right IC solution.
Our team is particularly adept at identifying key issues
such as power, cost and performance trade-offs. So we can
gear our efforts toward delivering you an optimized solution,
manufactured with the appropriate fab process.
No one's more experienced
More than 20 years of successfullC design work makes us
the most experienced engineering team in the MSICs field. Add
it all up and you get a company that saves you time and money
while delivering you the most sophisticated mixed-signal custom ICs you can get.
CMOS Analog Processing
For analog continuous time, samples data
(switched-capacitor implementation), and
high-current power transistor applications.
low power, high density capability also
allows inclusion of ROMs, RAMs, and
other analog/digital subsystems.
•
•
•
•
BiCMOS Signal Processing
For high-performance, low noise,
wide band signal acqUisition and processing applications. Offers TTL and/or ECl
logic interfaces with high current drive.
•
•
•
•
•
•
•
Sub 1 nV/..JHz HDD RNI amplifiers
AGC, pulse detection amplifiers
High-speed data separators
Wideband transceivers
Plls (phase locked loops)
Optical signal processing
Digital cellular, PCS IF circuits
Digital CMOS
For ASIC controllers, digital signal
processors, sequencers and data path
applications with on-board ROM, RAM,
and PlA sub-systems. Offers standard
TTL and/or CMOS logic interfaces.
•
•
•
•
•
Digital communications lAN devices
Hard disk drive controllers
SCSI interface controllers
UARTs
Digital signal processors for hard
disk servo and telecommunications
1-1
Complete single-chip 2400 bitls modem
14.4 kbps modem chip set
Direct-broadcast satellite descrambler
Servo and spindle motor controllers with 1.0
Amp motor interfaces
• High-resolution analog data acquisition
• Cellular baseband processor
1
CUSTOM SOLUTIONS
The right mix of analog and digital
SOPHISTICA TED TOOLS FOR
STRUCTURED CUSTOM DESIGN
Providing total analog/digital systems on a chip allows you
to meet your cost and performance objectives whether you're
designing the next generation of communication, computer
peripheral, or industrial control systems.
At each of five design centers capable of worldwide service
- Tustin, San Jose and Nevada City, California; Tokyo and
Singapore - Silicon Systems employs PEGASYS, an internal
design automation system developed from carefully selected
vendor tools and our own proprietary software. Using Mentor
Graphics workstations for both electrical and physical design,
PEGASYS helps create complex designs while significantly
reducing schedules, costs and errors.
We've turned to CMOS to effectively implement lowpower, highly integrated systems solutions for everything from
modems and cellular phones to hard disk drive controllers and
digital signal processors.
We've gone the BiCMOS route to meet the high-performance needs of products like wideband transceivers, wireless
IF modems, RIW amplifiers, low-noise amplifiers, pulse detectors, high-speed data separators and high-performance, lowpower combo devices.
By integrating third-party tools and custom software, we're
better able to design and analyze mixed-signal integrated
circuits in all CMOS, Bipolar and BiCMOS technologies. It's an
approach that has given us the edge in mixed-signal design and
helped put Silicon Systems' customers in a favorable position
in the marketplace.
• Product and company
names are trademarks of
their respective companies
c:J1~
ATISIM'
lerules'
Lism'
Dracula'
PEGASYS Design System
1-2
CUSTOM SOLUTIONS
Specifically, PEGASYS brings the following to each design:
• Chip floor planning
• Fully integrated design environment
• Analog device generators
• Methodology for precision circuit design
• Schematic driven layout
• Integrated electrical and physical design
• On-line point-to-point routing
• Unique blend of full-custom and automated layout
techniques
• Compaction
• Automatic place and route
• Support of custom cells, standard cells, and compiled
blocks in any combination
• Complete layout verification
• Full mixed-signal parasitic extraction
Ourdesign automation staff integrates the third-party tools
and optimizes their use on the Mentor platform. This framework
can easily accommodate new tools when needed, and it
enables us to support a combination of analog and digital
design techniques in all CMOS, Bipolar and BiCMOS chip
designs. By mixing design methodologies, we can achieve
optimum systems performance, even when schedules are
tight.
• Design rule checking (drc)
• Layout-versus-schematic verification (Ivs)
• Parasitic extraction/back annotation
• Output in industry standard GDS format
In the first generation Pegasys system, Silicon Systems
pioneered a device-generator based approach to precision
analog layout. In partnership with Mentor Graphics, we have
enhanced this technique for our current system, based on
Mentor Graphics VB ICstation® tools. ICstation® provides tremendous flexibility, combined with ease of customization, to
fully support analog and mixed-signal designs. A variety of
layout styles and techniques are combined to meet each chip's
specific requirements. Rigorous verification checks ensure the
quality and accuracy of the layout, for both physical and electrical properties. Post-layout simulation uses true parasitic modeling to handle remaining problems before first silicon fabrication.
Electrical design
A single CAE (computer aided engineering) environment
provides for schematic capture, synthesis, simulation, and fault
grading. We support this software with extensive libraries of
pre-designed cells and components. Highly specialized cells or
components can be designed and enhanced where required.
We simulate each circuit to meet precise performance specifications using:
• Analog circuit simulation
STATE OF THE ART CMOS DIGITAL AND
ANALOG PROCESSES
• Digital logic simulation
• VHDL simulation
Silicon Systems offers four proven CMOS process technologies for creating cost effective, highly integrated systems solutions. These processes combine small geometry digital circuit
capability with high performance analog capability. Table 1 summarizes Silicon Systems' CMOS process capabilities.
Our newest CK process is designed to support high
breakdown, high current power FETs, bipolar structure for
specialized analog needs, poly capacitors and resistors, low
noise differential amplifiers and high performance AID and
D/A converters. It also includes highly optimized and silicon
area efficient digital cells including DSPs, microcontrollers,
sequencers, memory managers and data paths.
The CJ process provides high performance analog and
digital cells and includes the same analog and digital complex
devices in our CK process.
Our CG process supports high-performance analog circuitry with precision poly-poly capacitors. Complex analog
circuitry includes 1.25 Amp power FETs, 12-bit switched capacitor analog to digital converters and low distortion operational amplifiers and filters. Complex digital circuitry includes
DSPs, microcontrollers, sequencers, memory mangers and
data paths.
The CH process also provides high quality, low voltage
coefficient, precision poly-poly capacitors that support high
performance switched-capacitor filtering and data conversion
(AID and D/A ) circuits.
• Mixed-mode simUlation
• Switched-capacitor filter simulation
• Analog and mixed-mode behavioral simulation
Admittedly, simulation alone is not the key to perfecting
performance. That's why we work aggressively to refine our
understanding of models to make them work with simulation.
Inside our progressive device modeling and characterization
(DMC) laboratory, we develop accurate circuit simulation models and parameters. The DMC lab provides complete device
model data for our processes using capabilities such as AC
measurement, statistical analysis and worst-case modeling.
Accurate models are a cornerstone of our design-for-quality
approach.
To ensure high quality test vectors, production test vectors
are derived from simulation vectors using the TSSI tools early
in the design process. The industry-standard Zycad fault simulator is then used to determine fault coverage.
Physical design
Our PEGASYS layout system aids the mask designer
through all physical design phases, ensuring consistency
throughout the design cycle. This flexible, fully integrated
environment supports a broad range of layout techniques, from
full-custom to full-automation. Capabilities include:
1-3
•
CUSTOM SOLUTIONS
BICMOS process technologies
BIPOLAR & BICMOS PROCESS
TECHNOLOGIES
Our BiCMOS process portfolio is expanding to support the
evolving demands of the mixed-signal IC market. Now in
production is our BCA process which combines 13 GHz NPNs
with 1.01l CMOS features to support the design of efficient, high
performance, mixed-signal circuits. High bandwidth analog
circuits can be combined with dense digital logic to support the
development of 5V data channels with transfer rates into the
120+ MbiVs range, while maintaining low power consumption.
The BCA technology has also allowed our designers to develop
3V only circuits to address very low power applications.
Our bipolar MSICs take advantage of two high-performance Bipolar processes: BK (for 12V applications) and BN (for
5V applications). The BK analog/digital process achieves its
higher voltage operation and improves lateral PNP transistor
performance by using a lightly-doped epi layer.
In BK we provide deep N+ and P+ enhancement layers to
reduce both collector series and base resistance. Our use of
up-junction isolation gives us a major reduction in device area,
when compared with that of typical junction isolated processes.
Metal-poly capacitors with a nitride dielectric are used for
improving capacitor reliability.
Our second generation BiCMOS process, BCB, will provide the next step in performance with a parallel improvement
in circuit density. BCB advances our BiCMOS with 0.81l CMOS
feature sizes and improved interconnect capability resulting in
a significant performance step for CMOS logic. This will allow
implementation of mixed-signal circuits that support data transfer rates well beyond 200 MbiVs, while maintaining very low
power dissipation. The dense digital advantages of BCB will
also expand the possibilities for cost effective customization
and programmability in both 5V and 3V environments.
BN. Low-powerl 8 GHz Bipolar at 5 volts
A noteworthy feature of a minimum size BN process
transistor is that it's only about 1/5th the size of a minimum size
BK transistor. Because we employ full oxide isolation in BN, we
can fabricate very fast, very small transistors and reduce
sidewall capacitances. This supports not only high speed, but
low power.
For a summary of our BiCMOS processes see Table 2.
The BN process features high-performance NPN transistors to support mixing high-performance emitter coupled logic
(ECl) with analog circuitry. To provide for strict TTL I/Ocompatibility, we use superior PtSi Schottky diodes.
The resulting speed and packing density allows you to
effectively implement dense high-performance, low-power
Bipolar analog/digital capability into your system designs.
For a feature-by-feature comparison of Silicon Systems'
BK and BN Bipolar processes, see Table 3.
1-4
CUSTOM SOLUTIONS
CH
Si-Gate, single metal,
dual poly, PWell
12V
1SV
3.61!
5.SIl
6.411
n/a
o
o
o
o
o
o
CG
Si-Gate, dual metal,
dual poly, PWell
7V
5V
1.51!
3.01!
4.511
6.01!
o
o
o
CJ
Si-Gate, dual metal,
dual poly, NWell
5V
Si-Gate, dual metal,
dual poly, NWell
5V
7V
1. 01!
2.011
3.011
3.31!
o
o
o
CK
7V
O.SI!
1.611
2.011
2.41!
o
o
o
DDD SID structure
Poly-poly capacitors
Low-voltage coefficient
High n /Opoly resistors
Epi substrate option
Buried well-ring
DDD SID structure
Poly-poly capacitors
Shrinkable to 1
Ldd SID structure
Poly-poly capacitors
Shrinkable to O.SI!
Ldd SID structure
Poly-poly capacitors
Shrinkable to 0.51!
TABLE 1: CMOS Process Chart
BCA:
5V
10V
1.01!
2.61!
3.211 3.SI! 5.01!
SV
13GHz
1.01!
Bipolar:
High Performance NPNs
o Polysilicon emitters
o PtSi Schottky Diodes
o Poly resisters
o Gate Oxide Capacitors
o Poly Capacitors
• Sidewall Oxide Isolation
o Fuses
CMOS:
o Lightly Doped Drains
o
BCB:
5V
SV
O.SIl
1.61!
2.01! 2.01! 2.41!
8V
15GHz
O.SI!
TABLE 2: BiCMOS Process Chart
BK
Junction-isolated
12V
2GHz
2.51!
9.011
14.01!
BN
Oxide-isolated
6V
SGHz
2.01!
4.511
S.OI!
TABLE 3: Bipolar Process Chart
1-5
• Polysilicon emitters
• AI Schottky diodes
• Nitride capacitors
• Ion implanted resistors
o Up/down junction isolation
o Collector/base plugs
o High performance NPNs
• PtSi Schottky diodes
o Nitride capacitors
• Ion implanted resistors
o Sidewall oxide isolation
o Collectorlbase
•
CUSTOM SOLUTIONS
Quality that delivers
A SUPERIOR FINISH FOR CMOS, BIPOLAR
ANDBICMOS
With effective systems such as PROMIS and our designfor-quality approach in place, Silicon Systems is prepared to
deliver you finished products you can really depend on. On
time. And within budget.
You might say this isthepayoffwindow. The benefits of our
process technologies, design tools and our unique custom
approach all come together during wafer fabrication, test and
assembly.
For details on how you can take best advantage of Silicon
Systems' custom mixed-signal IC solutions, see your nearest
Silicon Systems representative, or contact us. Silicon Systems, Inc.
14351 Myford Road, Tustin, CA 92680-7022.714-573-6000.
FAX: (714) 573-6914.
Our two manufacturing centers, located in Tustin and
Santa Cruz, California, can offer specialized capabilities to
match your particular fabrication requirements. Both facilities
provide you with high resolution stepper photolithography technology, positive resist, dry plasma etch systems, high current
ion implantation and automatic sputtering.
Fabrication sites in both Tustin and Santa Cruz accommodate
4- and 6-inch wafer fabrication and Bipolar, CMOS and BiCMOS
processes.
The right package
Silicon Systems offers a wide range of packages to meet
the small footprint requirements of advanced storage and
communication products. We continue to be innovative in
surface mount technology by providing PLCC, SO, VSOP,
VTSOP, OFP, TOFP, VTOFP and UTOFP packages. At our
ISO 9002-certified Singapore assembly & test facility we have
the full capability to support high quality automated packaging
while also maintaining rapid cycle times.
Design Components
• Schematic Capture
• Simulation
• Netlisting
Rnal Design Review
Prom Is. Quality through CAM
Process and Management Information System (PROMIS)
underscores our commitment to computer-aided manufacturing (CAM). And to delivering you a superior quality product on
time.
• Automatic Placing
and Routing or
Hand-Packed Layout
• Automatic Circuit
Trace
We use PROMIS to facilitate the data required in our
manufacturing, monitoring and statistical process control (SPC)
systems.
With PROMIS we more effectively manage our inventory,
accurately track wafers in process, and closely monitor the
clean room environment.
Test Program Creation
Photomask
WaferFab
Prototype
(Assembly, Test, Ship)
PROMIS also assists our SPC efforts, as does ourcommitment to fully train all of our manufacturing personnel in SPC
basics.
We deslg n for qlliallty
Evaluate Prototype
It's our view that quality is nothing less than absolute
customer satisfaction. To achieve it, we begin far "upstream" in
the product development process. Our design-for-quality
approach scrutinizes the design itself with statistically based
models, comprehensive simulation tools and vigorous design
reviews.
The results of such an effort are IC products that boast
lower defect rates, higher parametric performance and far
fewer redesigns. Moreover, our persistence in improving quality keeps us focused on finding better and faster ways to satisfy
future customer demands.
Customer Interface for Full-Custom
and Cell-Based Designs
1-6
Section
2
RELIABILITY &
QUALITY ASSURANCE
2
I
CONTINUOUS IMPROVEMENT
MISSION &.. OBJECTIVE
STATEMENT
Mission
Be the supplier of choice by exceeding customer expectations
through continuous improvements in our products, systems
and services.
Objectives
Provide world class quality in our products and services
through focus on:
Customer Partnering
Cycle Time Improvement
Process and System Improvements
Develop a culture that ensures the consistent use of continuous
improvement tools and fact based dedsion methodology by:
Senior Management Leadership
Employee Empowerment
Aggressive Goal Setting and Performance Measurement
Communication and Celebration of Successes
Alan V. King
President. CEO
b
Cheryl A. Stock
Vice President. Corporate R&..QA
~~~~~ Ji~~DK~·
2-0
Reliability and
Quality Assurance
SECTION 1
1.1
Our Reliability and Quality Assurance organizations are
committed to working closely with our customers to provide
assistance and a continually improving levelof product quality.
INTRODUCTION
Silicon Systems is committed to the goal of customer satisfaction through the on-time delivery of defect free products
that meet the customer's expectations and requirements.
This section outlines Silicon Systems' ongoing activities for
the control and continual improvement of quality in every
aspect of our organization.
1.2
CON~NUOUSIMPROVEMENT
Continuous improvement is Silicon System's strategic thrust
for the 1990's. In order to ensure that all aspects of our
business are encompassed by this mandate, Corporate
Reliability & Quality Assurance has been chartered with the
responsibility for developing, educating and overseeing the
worldwide continuous improvement process. The continuous improvement initiative will lead to developing a new
organizational culture, changing attitudes and stronger ownership and accountability for total customer satisfaction.
Silicon Systems is diligently working to maintain and improve
its position as a world-class provider of mixed-signal integrated circuits (MSICs®).
We realize and practice the concept that quality and reliability
must be designed and built into our products. In addition,
Silicon Systems utilizes rigid inspections and data analysis to
evaluate the acceptability and variation existing in incoming
materials and performs stringent outgoing quality verification. The manufacturing process flow is encompassed by an
effective system of test/inspection checks and in-line monitors which focus on the control and reduction of process
variation. These gates and monitors ensure precise adherence to prescribed standards and procedures.
1.3
CHARACTERISTICS OF SILICON SYSTEMS'
CON~NUOUSIMPROVEMENTPROCESS
Executive Steering Committee leadership and direction - defines the right things to do and provides
guidance - the right way to do them.
Continuous improvement is measured everywhere and
by everyone. Metrics that reflect pride in accomplishment are celebrated.
Silicon Systems also incorporates the use of statistical process control techniques into company operations. The control and reduction of the process variation by the use of
statistical problem solving techniques, analytical controls
and other quantitative methods ensures that Silicon Systems'
products maintain the highest levels of quality and reliability.
H
SILICON SYSTEMS' QUALITY MANDATE:
Benchmarking is employed as a method to shorten
learning curves and ensure successful ventures.
Quality management and employee empowerment are
encouraged at all levels.
~ -I
CPD
PaA
Manae:
Singapore
F.A. Lab
FIGURE 1: Organizational Chart
2-1
I
Reliability and
Quality Assurance
•
It is the practice of Silicon Systems to have corporate quality
and reliability objectives encompass all of its activities. This
starts with a strong commitment of support from the corporate
level and continues with exceptional customer support long
after the product has been shipped.
Supplier partnership is a critical element of our quality
strategy.
This is the essence of Silicon Systems - a total quality
involved company - forward looking and immersed in the goal
of customer satisfaction and best-in-class business pursuits.
1.4
Silicon Systems emphasizes the belief that quality and reliability must be built into all of its products by ensuring that all
employees are educated in the quality philosophy of the
company. Some of the features built into Silicon Systems
quality culture include:
CORPORATE RELIABILITY AND
QUAUTY ASSURANCE
It is the objective of the Corporate Reliability and Quality
Assurance organization to ensure that proactive quality
systems are in place to ensure that Silicon Systems' products
will meet or exceed customer requirements and expectations. In addition, the Reliability and Quality Assurance
organization works to facilitate the timely implementation of
solutions and monitors the effectiveness of corrective actions. These organizational strategies support the continuing
enhancement of quality consciousness throughout Silicon
Systems.
1.5
1.
2.
ISO 9000 CERTIFICATION
Silicon Systems has determined that ISO 9000 certification
is an important strategy for achieving total customer satisfaction. Our Singapore assembly and test operations facility has
been ISO 9002 certified through SISIR and our domestic
facilities are currently in pursuit of this important industry
standard. We believe strongly that ISO 9000 certification
proves that Silicon Systems is doing the right things to do
things right.
Structured training programs directed at wafer fabrication, test, process control personnel and supporting
organizations.
- Team-based problem solving methodologies.
- Corporate-wide training of quality philosophy and
statistical methods.
Stringent in-process inspection, gates, and monitors.
3.
Rigorous evaluation of designs, materials, and processing procedures.
4.
Stringent electrical testing (100% and QC AQUSampie
testing).
5.
Ongoing reliability monitors and process verifications.
6.
Real-time use of statistical process control
methodology.
7.
Corporate level audits of manufacturing, subcontractors, and suppliers.
8.
Timely corrective action system.
9.
Control of non-conforming material.
These focused quality methods result in products which
deliver superior performance and reliability in the field.
SECTION 2: QUALITY ASSURANCE
2.1
2.2.1
QUALITY OBJECTIVES
INCOMING INSPECTIONS
Incoming inspection plays a key role in Silicon Systems'
quality efforts. Small variations in incoming material can
traverse the entire production cycle before being detected
much later in the process. By paying strict attention to the
monitoring of materials at the earliest possible stage, variation can be reduced, resulting in a stable uniform process.
While all Silicon Systems employees have direct responsibility
for quality in their functions, the Quality Assurance Organizations have the ultimate responsibility for the reliable performance of our products. This is accomplished through the
development, administration and assessment offormal quality systems which assure Silicon Systems' management, as
well as our customers, that products will fulfill the requirements of customer purchase orders and all other specifications related to design, raw material and in process through
completion of the finished product.
2.2.2 IN-PROCESS INSPECTIONS
Silicon Systems has established key inspection monitors in
such strategic areas as wafer fabrication, wafer probe, assembly, and final test. These quality monitoring tests are
performed in addition to the intermediate and final inspections
found in the manufacturing process.
Corporate Quality Assurance supports, coordinates and actively participates in the formal qualification of suppliers,
material, processes, and products, and the administration of
quality systems and production monitors to assure that our
products meet Silicon Systems quality standards. Producl
Quality Assurance provides the liaison between Silicon Systems and the customer for all product quality related concerns.
Quality control monitors have been integrated throughout the
manufacturing flow, so that data may be collected and analyzed to verify the results of intermediary manufacturing
steps. This data is used to document quality trends or long
term improvements in the quality of specific operations.
2-2
Reliability and
Quality Assurance
sign-related functions include ensuring that process specification revisions are translated into updated design parameters and the translation of manufacturing process capability
into design guidelines. This is accomplished through the
identification and monitoring of critical process and device
parameters. Wafer level test at the early stages of process
development also plays a critical role. These elements, included in Silicon Systems design for quality effort, support the
development of robust design rules which are as insensitive
as possible to inherent manufacturing variation. The result is
a product that delivers predictable and reliable long term
performance.
2.5
PPM REDUCTION PROGRAM
The primary purpose of a PPM reduction program is to
provide a formalized feedback system in which data from
nonconforming products can be used to improve future
product consistency and reliability. The action portion of this
program is accomplished in three stages:
FIGURE 2
Quality Assurance Relationships
Quality Steering Committee
1.
Identification of defects by failure mode.
2.
Identification of defect causes and initiation of corrective
action.
3.
Measurementof results and setting of improved goals.
The data summarized from the established PPM program is
compiled as a ratio of units rejectedltested. This ratio is then
expressed in terms of defective parts per million (PPM).
Founded on a statistically valid database of PPM data and an
established five-year strategic plan identifying PPM improvement goals, Silicon Systems has consistently achieved excellent quality standards and will continue to progressively
improve PPM standards.
Abnormality control is being used to enhance the effectiveness of this process. In process monitors such as oxide
integrity, electromigration immunity and other parameters
monitor long term reliability as well as circuit performance.
2.3 QUALITY STEERING COMMITTEE
The Corporate, Product and Manufacturing Quality Assurance organizations work closely together to provide leadership in the development, integration and assessment of
Silicon Systems' worldwide quality systems and procedures.
2.6
COMPUTER AIDED MANUFACTURING CONTROL
Computer Aided Manufacturing (CAM) is used throughout
Silicon Systems for the identification, control, collection and
dissemination of timely information for logistics control. Silicon Systems also uses this type of computerized system for
statistical process control and manufacturing monitoring.
PROMIS, (PROcess Management and Information System),
displays approved/controlled recipes, processes, and procedures; tracks work-in-process; reports accurate inventory
information; allows continuous recording of facilities data;
contains statistical analysis capabilities; and much more.
PROMIS allows for a paperless facility, a major element in
minimizing contamination of clean room areas.
This team approach ensures that policies and procedures are
standardized and facilitates rapid improvement in products,
processes and services.
2.4 DESIGN FOR QUALITY
Since the foundation of a reliable product is rooted in the
design process, the Reliability and Quality Assurance organizations actively participate in comprehensive cross-functional reviews of design stages priorto the product's transition
to production status. These review stages assure a predictable and effective development cycle. Other important de-
2-3
2
Reliability and
Quality Assurance
TEST
CONDITIONS
PURPOSE OF EVALUATION
Biased temperature/humidity
Highly accelerated stress test (HAST)
High temperature operating life (HTOL)
Early Failure Rate
Steampressure
Temperature cycling
Thermal shock
Salt atmosphe re
Constant acceleration
Mechanical shock
Solderability
Lead integrity
Vibration, variable frequency
Thermal resistance
Electrostatic damage
Latch-up
Seal fine and gross leak
8soC/8So %RH
JDEC A110
Mil 8830, Method 100S
Mil 8830, Method 100S
121°C/1SPSI
Mil 8830, Method 1010
Mil 8830, Method 1011
Mil 8830, Method 1009
Mil 8830, Method 2001
Mil 8830, Method 2002
Mil 8830, Method 2003
Mil 8830, Method 2004
Mil 8830, Method 2007
Silicon Systems Method
Mil 8830, Method 3015
Silicon Systems Method
Mil Std 8830, Method 1014
Resistance to high humidity with bias
Evaluates package integrity
Resistance to electrical and thermal stress
Detect infant mortality
Resistance to hiqh humidity
Resistance to thermal excursion (air)
Resistance to thermal excursion (liquid)
Resistance to corrosive environment
Resistance to constant acceleration
Resistance to mechanical shocks
Evaluates solderability of leads
Evaluates lead integrity before board assembly
Resistance to vibration
Evaluates thermal dissipation
Evaluates ESD susceptability
Evaluates latch-up susceptibility
Evaluates hermeticity of sealed packages
TABLE 1: Reliability Stress Tests
SECTION 3: RELIABILITY
3.3
3.1
This program has been established to randomly select a
statistically significant sample of production products for
SUbjection to maximum stress test levels in orderto evaluate
the useful life of the product in a field use environment.
RELIABILITY PROGRAM
Silicon Systems has defined various programs that will
characterize product reliability levels on a continuous basis.
These programs can be categorically described by:
PRODUCTION MONITORS
3.
Evaluations
4.
Failure analysis
S.
Wafer level reliability
Table 1 lists reliability test methods that are in use at Silicon
Systems. This analysis of production monitor at Silicon
Systems provides valuable information on possible design/
process changes which assure continued improved reliability.
The monitors are periodically reviewed for effectiveness and
im provem ents.
6.
Data collection and presentation for improvement
projects
3.4
1.
Qualifications
2.
Production monitors
3.2
EVALUATIONS
The evaluation program at Silicon Systems is an ongoing
effort that will continue defining standards which address the
reliability assessment of the circuit design, process parameters, and package of a new product. This program continuously analyzes updated performance characteristics of product as they undergo improvement efforts at Silicon Systems.
QUALIFICATIONS
Extensive qualification testing and data collection ensures
that all new product designs, processes, and packaging
configurations meet the absolute maximum ratings of design
and the worst case performance criteria for end users. A large
database generated by means of accelerated stress testing
results in a high degree of confidence in predicting final use
performance. The qualification criteria used are periodically
reviewed to be consistent with Silicon Systems' increasing
quality and reliability goals in support of our customers.
3.5
FAILURE ANALYSIS
The failure analysis function is an integral part of the Quality
and Reliability department at Silicon Systems. Silicon Systems has assembled a highly technical and sophisticated
failure analysis laboratory and staff. This laboratory provides
visual analysis, electrical reject mode analysis, and both
2-4
Reliability and
Quality Assurance
destructive and non-destructive data to aid the engineers in
developing corrective action for improvement. These test
analyses may include metallurgical, optical, chemical, electrical, SEM with X-ray dispersive analysis, and E-Beam noncontact analysis as needed.
3.8
RELIABILITY METHODS
The Reliability Program utilizes a number of stress tests that
are presently being used to define performance levels of our
products. Many of these stress tests are per MIL-STD-883D
as shown in Table 1.
These conclusive in-house testing and analysis techniques,
are complemented by outside support, such as scanning
acoustic microscopy, focused ion beam, and complete surface and material analysis. This allows Silicon Systems to
monitor all aspects of product manufacturing to ensure that
the product of highest quality is shipped to our customers.
3.9
RELIABILITY PREDICTION METHODOLOGY
At Silicon Systems, the Arrhenius model is used to relate a
failure rate at an accelerated temperature test condition to a
normal use temperature condition.
The model basically states FR = A exp(-EalKT)
3.6
WAFER LEVEL RELIABILITY PROGRAM
Where:
A primary objective at Silicon Systems is to improve the
reliability of our products through characterization of our
manufacturing operations. The identification of specificfailure
mechanisms occuring in the wafer fabrication and assembly
processes is a prerequisite to effective corrective action
aimed at reducing defects and improving quality and reliability.
The primary advantage of wafer level reliability testing is the
speed at which results can be derived, thereby providing
additional response time and an early warning of process
changes. This tool provides Silicon Systems with a very rapid
analysis tool which allows for the early identification of
possible problems and a determination of their origin.
Failure rate
Constant
Ea
Activation Energy (eV)
K
Boltzmann's constant 8.62 x 10-5 eV/ degree K
"T
Absolute temperature (degree K)
SECTION 4:
4.1
ELECTROSTATIC DISCHARGE
PROGRAM
ESD PREVENTION
Silicon Systems recognizes that the protection of Electrostatic Discharge (ESD) sensitive devices from damage by
electrical transients and static electricity is vital. ESD safe
procedures are incorporated throughout all operations which
come in contact with these devices. Continuous improvement in the ESD protection levels is being accomplished
through the incorporation of increasingly robust protection
devices du ring the circuit design process as well as work area
improvements.
The continuous improvement approach taken at Silicon
Systems uses the wafer level reliability tests as tools to
improve the process, identify potential problems, determine
the sources of any process weakness and eliminate problems upstream in the process. This results in a focus on
reliability improvement that goes well beyond merely determining the projected lifetime of a product to a detailed
characterization, measurement and control of the specific
parameters which actuailly determine product lifetime.
3.7
FR
A
Silicon Systems' quality activity incorporates several protection measures forthe control of ESD. Some of the preventive
measures include handling of parts at static safe-guarded
workstations, the wearing of wrist straps during all handling
operations, the use of conductive lab coats in all test areas
and all areas which handle parts and the packaging of
components in conductive or anti-static containers.
DATA COLLECTION AND PRESENTATlON FOR
IMPROVEMENT PROJECTS
Data collected from each element of the Reliability program
is summarized for scope and impact and distributed among
all engineering disciplines in the company. This data facilitates improvement and provides our customers an opportunity to review the performance of our product.
2-5
•
NOTES
2-6
Section
3
K-SERIES
MODEM FAMILY
I
3
Introduction
Silicon Systems' K-Series Family of One-Chip Modems
addition, an innovative bus structure makes a separate
controller unnecessary in dedicated integral designs.
All K-Series devices are available in low-power versions. This feature allows optimal performance with
single +5V supply operation and is unique to Silicon
Systems' products.
Silicon Systems is a leader in the design and manufacturing of CMOS VLSI modems. Currently, Silicon
Systems offers the most extensive line of one-chip
modem ICs available, with high-performance, costeffective designs suitable for a wide range of applications. Silicon Systems' fully compatible modem IC
family has redefined the modem IC as a universal
component which can be easily integrated into any
system. Designs can be upgraded to meet different
standards and speeds by simply substituting one KSeries IC for another. Using a K-Series family modem
IC in your application eliminates product obsolesence,
and minimizes development costs.
Silicon Systems' single-chip modem IC family is
designed to be the most effective solution for a wide
variety of modem applications. The products provide
for a full range of communications standards and
speeds up to 2400 bitls. Moreover, features can be
extended to include additional modes and higher
operating speeds without impacting existing designs.
Take advantage of these capabilities. Design for
tomorrow's needs today by using Silicon Systems'
K-Series modem IC family.
The Silicon Systems modem IC family consists of four
basic products:
1.
The SSI 73K222L, a multi-mode device which
combines both Bell 212A11 03 and V.22N.21 capability in one chip, with operating modes at 0 - 30,
600 and 1200 bitls.
2.
The SSI 73K222U which combines the functionality of the 73K222L with the industry standard
16C450 UART.
3.
The SSI 73K224L, a major technological breakthrough which provides 2400 bitls V.22bis operation in addition to V.22N.21 and Bell 212A1103
modes in a single IC.
K-Series Modem Design Manual
The Silicon Systems K-Series Modem Design Manual
contains a large body of application literature for the
K-Series family of single chip modem products. This
manual is intended as a tutorial for those users who
may be designing with modems for the first time, and
also as a helpful guide for more experienced modem
designers.
K·SERIES
MODEM
4.
DESIGN
The SSI 73K322L provides CCITI V.22N.21 plus
V.23 Videotex modes.
MANUAL
New additions to Silicon Systems' modem IC family
extend the available operating modes and provide
features which greatly simplify integral modem design.
The SSI 73K324L offers V.22bis, V.22N.21 and V.23
operating modes on one chip. These products dramatically reduce external circuitry required for dedicated integral modem designs.
Silicon Systems' one-chip modem IC products represent technical achievements unmatched in the industry. An advanced Digital Signal Processor resides on
the same chip with sophisticated analog circuitry in the
SSI 73K224L and SSI73K324L products. "U" versions
of the K-Series devices integrate an industry standard
UART with full modem capability on a single chip. In
The K-Series Modem Design Manual is available
through our worldwide network of representatives and
distributors.
3-0
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
January 1994
DESCRIPTION
FEATURES
The SSI 73K212L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a typical Bell 212A full-duplex modem.
Using an advanced CMOS process that integrates
analog, digital and switched-capacitor filter functions
on a single substrate, the SSI73K212L offers excellent
performance and a high level of functional integration
in a single 28-Lead PLCC, 28-or 22-pin 01 P configuration. The SSI 73K212L operates from a single +5V
supply.
One-chip Bell 212A and 103 standard compatible
modem data pump
Full-duplex operation at 0-300 bltls (FSK) or
1200 bitls (OPSK)
Pin and software compatible with other
SSI K-Series 1-chip modems
Interfaces directly with standard microprocessors
(8048,80C51 typical)
Serial or parallel microprocessor bus for control
Serial port for data transfer
The SSI 73K212L includes the OPSK and FSK modulator/demodulator functions, call progress and handshake tone monitor test modes and a OTMF dialer.
This device supports all Bell 212A modes of operation
allowing both synchronous and asychronous communications.
Both synchronous and asynchronous modes of
operation
Call progress, carrier, precise answer tone and
long loop detectors
OTMF generators
Test features such as analog loop. digital loop, and
remote digitalloopback are provided. Internal pattern
generators are also included for self-testing. The SSI
73K212L is designed to appear to the systems designer as a microprocessor peripheral, and will easily
interface with popular one-chip microprocessors
Test modes available: ALB, OL, ROL, Mark, Space,
Alternating bit patterns
Precise automatic gain control allows 45 dB
dynamic range
CMOS technology for low power consumption
using 30 mW @ 5V
Single +5V supply
(Continued)
BLOCK DIAGRAM
PIN DIAGRAM
CLK
AOO-AD7
1m
WFr
' -_ _..II
D--_~
~A
D--_~
ALE D---~
~ D---..-!
RESET
~A
D---..-!
SMART
GND
XTl1
RXA
XTL2
VREF
ADO
RESET
AD1
ISET
AD2
RXCLK
AD3
RXD
AD4
TXD
DIALING
AD5
&
FJ'~~S
~D O----------~
~D
n-----------~
1.4-_ _ _ _ _-1
AD6
EXCLK
AD7
ALE
WR
TXA
RD
VDD
CAUTION: Use handling procedures necessary
for a static sensitive component.
)194 - rev.
3-1
3
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
DESCRIPTION (Continued)
Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC rate converter. The SYNC/ASYNC
convertor will reinsert any deleted stop bits and transmit output data at an intra-character rate (bit-to-bit
timing) of no greaterthan 1219 bit/so An incoming break
signal (lOW through two characters) will be passed
through without incorrectly inserting a stop bit.
(80C51 typical) for control of modem functions through
its 8-bit multiplexed address/data bus or serial control
bus. An ALE control line simplifies address demultiplexing. Data communications occurs through a separate serial port only.
The SSI73K212L is ideal for use in either free standing
or integral system modem products where full-duplex
1200 bitls data communications over the 2-wire
switched telephone network is desired. Its high functionality, low power consumption and efficient packaging simplify design requirements and increase system
reliability. A complete modem requires only the addition of the phone line interface, a control microprocessor, and RS-232 level convertor for a typical system.
The SSI73K212L is part of SSi's K-Series family of pin
and function compatible single-chip modem products.
These devices allow systems to be configured for
higher speeds and Bell or CCITT operation with only a
single component change.
SYNCHRONOUS MODE
The Bell 212A standard defines synchronous operation only at 1200 biVs. Operation is similar to that of the
asynchronous mode exceptthat data must be synchronized to a provided clock and no variation in data
transfer rate is allowable. Serial input data appearing at
TXD must be valid on the rising edge of TXCLK.
TXCLK is an internally derived 1200 Hz signal in
internal mode and is connected internally to the
RXCLK pin in slave mode. Receive data at the RXD pin
is clocked out on the falling edge of RXCLK. The
ASYNCH/SYNCH converter is bypassed when synchronous mode is selected and data is transmitted out
at the same rate as it is input.
OPERATION
ASYNCHRONOUS MODE
DPSK MODULATOR/DEMODULATOR
Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous fashion. The SSI 73K212L includes ASYNC/SYNC and
SYNC/ASYNC converters which delete or insert stop
bits in order to transmit data within a 0.01 % rate. In
asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC converter. The
ASYNC/SYNC converter accepts the data provided on
the TXD pin which normally must be 1200 biVs +1.0%,
- 2.5%. The rate converter will then insert ordelete stop
bits in orderto output a signal which is 1200 biVs ± .01 %
(±.01 % is the required synchronous data rate
accuracy).
The SSI 73K212L modulates a serial bit stream into
dibit pairs that are represented by four possible phase
shifts as prescribed by the Bell 212A standard. The
baseband Signal is then filtered to reduce intersymbol
interference on the band limited 2-wire telephone line.
Transmission occurs using either a 1200 Hz (originate
mode) or 2400 Hz carrier (answer mode). Demodulation is the reverse of the modulation process, with the
incoming analog signal eventually decoded into di-bits
and converted back to a serial bit stream. The demodulator also recovers the clock which was encoded into
the analog signal during modulation. Demodulation
occurs using either a 1200 Hz carrier (answer mode or
ALB originate mode) or a 2400 Hz carrier (originate
mode or ALB answer mode). The SSI 73K212L uses a
phase locked loop coherent demodulation technique
for optimum receiver performance.
The serial data stream from the ASYNC/SYNC converter is passed through the data scrambler and onto
the analog modulator. The data scrambler can be
bypassed under processor control when unscrambled
data must be transmitted. The ASYNC/SYNC rate
converter and the data scrambler are bypassed in all
FSK modes. If serial input data contains a break signal
through one character (including start and stop bits) the
break will be extended to at least 2· N + 3 bits long
(where N is the number of transmitted bits/character).
FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. In the Bell 103, the standard
frequencies of 1270 and 1070 Hz (originate, mark and
3-2
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
space) or 2225 and 2025 Hz (answer, mark and space)
are used. V.21 mode uses980 and 1180 Hz (originate,
mark and space) or 1650 and 1850 Hz (answer, mark
and space). Demodulation involves detecting the received frequencies and decoding them into the
appropriate binary value. The rate converter and
scrambler/descrambler are bypassed in the 103 mode.
EXCLK. WR is then pulsed low and data transferred
into the selected register occurs on the rising edge of
WR.
SPECIAL DETECT CIRCUITRY
The special detect circuitry monitors the received
analog signal to determine status or presence of carrier, call-progress tones, answer tone and weak received signal, (long loop condition). An unscrambled
mark request signal is also detected when the received
data out of the DPSK demodulator before the descrambier has been high for 165.5 ms ± 6.5 ms minimum. The
appropriate detect register bit is set when one of these
conditions changes and an interrupt is generated for all
purposes except long loop. The interrupts are disabled
(masked) when the enable interrupt bit is set to O.
PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band signals in the
receive channel. Amplitude and phase equalization
are necessary to compensate for distortion of the
transmission line and to reduce intersymbol interference in the bandlimited receive signal. The transmit
signal filtering approximates a 75% square root of
raised Cosine frequency response characteristic.
DTMF GENERATOR
The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode
is selected using the tone register and the transmit
enable (CRO bit 01) is changed from 0 to 1.
AGC
The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
receiver dynamic range of >45 dB.
PARALLEL BUS INTERFACE
Four 8-bit registers are provided for control, option
select and status monitoring. These registers are addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appearto a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The status detect register is read
only and cannot be modified except by modem
response to monitored parameters.
SERIAL COMMAND INTERFACE
The serial command mode allows access to the
SSI 73K212L control and status registers via a serial
command port (22-pin version only). In this mode the
AO, A 1 and A2lines provide register addresses fordata
passed through the data pin under control of the RD
and WR lines. A read operation is initiated when the RD
line is taken low. The next eight cycles of EXCLK will
then transfer out eight bits of the selected address
location LSB first. A write takes place by shifting in eight
bits of data LSB first for eight consecutive cycles of
3-3
I
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
PIN DESCRIPTION
POWER
28-PIN
22-PIN
TYPE
DESCRIPTION
GND
28
1
I
System Ground.
VDD
15
11
I
Power supply input, 5V ± 10% (?3K212l). Bypass with .1
and 22 J..lF capacitors to ground.
VREF
26
21
0
An internally generated reference voltage. Bypass with
0.1 J..lF capacitor to GND.
ISET
24
19
I
Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 MQ resistor. ISET should be bypassed to GND with a
0.1 J..lF capacitor.
NAME
PARALLEL MICROPROCESSOR INTERFACE
12
-
I
Address latch enable. The falling edge of ALE latches the
address on ADO-AD2 and the chip select on CS.
4-11
-
I/O
Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
registers.
CS
20
-
I
Chip select. A low during the falling edge of ALE on this pin
allows a read cycle or a write cycle to occur. ADO-AD? will
not be driven and no registers will be written if CS (latched)
is not active. The state of CS is latched on the falling edge
of ALE.
ClK
1
2
0
Output clock. This pin is selectable under processor control
to be either the crystal frequency (for use as a processor
clock) or 16 x the data rate for use as a baud rate clock in
DPSK modes only. The pin defaults to the crystal frequency
on reset.
INT
1?
13
0
Interrupt. Thisopen drain output signal isusedto inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.
RD
14
-
I
Read. A low requests a read of the SSI ?3K212l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.
ALE
ADO-AD?
3-4
SSI73K212L
Bell 212A/103
Single-Chip Modem
PARALLEL MICROPROCESSOR INTERFACE
(Continued)
NAME
28-PIN
22-PIN
TYPE
DESCRIPTION
RESET
25
20
I
Reset. An active high signal on this pin will put the chip into
an inactive state. All control register bits (CRO, CR1, Tone)
will be reset. The output of the CLK pin will be set to the
crystal frequency. An internal pull down resistor permits
power on reset using a capacitor to VDD.
WR
13
-
I
Write. A low on this informs the SSI ?3K212L that data is
available on ADO-AD? for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low .
SERIAL MICROPROCESSOR INTERFACE
AO-A2
-
5-7
I
Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.
DATA
-
8
I/O
Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.
RD
-
10
I
Read. A low on this input informs the SSI ?3K212L that
data or status information is being read by the processor.
The falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.
WR
-
9
I
Write. A low on this input informs the SSI?3K212L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the rising edge
ofWR.
Note:
In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the
pins; AD, A 1 , A2, DATA, and an unconnected pin. Also, the R D and WR controls are used differently.
The Serial Control mode is provided in the parallel control versions by tying ALE high and CS low.
In this configuration AD? becomes DATA and ADO, AD1 and AD2 become AD, A1 and A2,
respectively.
3-5
•
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
DTE USER INTERFACE
NAME
28-PIN
22-PIN
TYPE
EXCLK
19
15
I
External Clock. This signal is used in synchronous transmission when the external timing option has been selected.
In the external timing mode the rising edge of EXCLK is
used to strobe synchronous DPSK transmit data applied to
the TXD pin. Also used for serial control interface.
RXCLK
23
18
0
Receive Clock. The falling edge of this clock output is
coincident with the transitions in the serial received data
output. The rising edge of RXCLK can be used to latch the
valid output data. RXCLK will be valid as long as a carrier
is present.
RXD
22
17
0
Received Data Output. Serial receive data is available on
this pin. The data is always valid on the rising edge of
RXCLK when in synchronous mode. RXD will output constant marks if no carrier is detected.
TXCLK
18
14
0
Transmit Clock. This signal is used in synchronous transmission to latch serial input data on the TXD pin. Data must
be provided so that valid data is available on the rising edge
of the TXCLK. The transmit clock is derived from different
sources depending upon the synchronization mode
selection. In Internal Mode the clock is generated internally.
In External Mode TXCLK is phase locked to the EXCLK pin.
In Slave Mode TXCLK is phase locked to the RXCLK pin.
TXCLK is always active.
TXD
21
16
I
Transmit Data Input. Serial data for transmission is applied
on this pin. In synchronous modes, the data must be valid
on the rising edge of the TXCLK clock. In asynchronous
modes (1200 bitls or 300 baud) no clocking is necessary.
DPSK data must be 1200 bitls +1%, -2.5%.
DESCRIPTION
ANALOG INTERFACE AND OSCILLATOR
RXA
27
22
I
Received modulated analog signal input from the telephone line interface.
TXA
16
12
0
Transmit analog output to the telephone line interface.
XTL1
XTL2
2
3
3
4
I
I
These pins are for the internal crystal oscillator requiring
a 11.0592 MHz parallel mode crystal and two load capacitors to Ground. Consult crystal manufacturer for proper
valves. XTL2 can also be driven from an external clock.
3-6
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
REGISTER DESCRIPTIONS
line. CR1 controls the interface between the microprocessor and the SSI 73K212L internal state. DR is a
detect register which provides an indication of monitored modem status conditions. TR, the tone control
register, controls the DTMF generator, answer and
guard tones and RXD output gate used in the modem
initial connect sequence. All registers are read/write
except for DR which is read only. Register control and
status bits are identified below:
Four 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AD, A 1 and
A2 address lines in serial mode, or the ADO, AD1 and
AD2 lines in parallel mode. In parallel mode the address lines are latched by ALE. Register CRO controls
the method by which data is transferred over the phone
REGISTER BIT SUMMARY
CRO
CONTROL
REGISTER
CRl
000
001
1
DETECT
REGISTER
DR
010
TONE
CONTROL
REGISTER
TR
011
CONTROL
REGISTER
2
CR2
100
CONTROL
REGISTER
3
CR3
101
10
110
10
REGISTER
NOTE:
ENABLE
DETECT
INTERRUPT
BYPASS
SCRAMBLER
RECEIVE
DATA
UNSCR.
MARKS
CARRIER
DETECT
TRANSMIT
DTMF
DTMF3
When a register containing reserved control
bits is written into, the reserved bits must be
programmed as D's.
3-7
CLK
CONTROL
TEST
MODE
TEST
MODE
1
0
ANSWER
TONE
CALL
PROGRESS
LONG
LOOP
DTMF2
DTMFl
DTMFO
RESET
•
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
REGISTER ADDRESS TABLE
OOOO=PWR DOWN
0001=INT SYNCH
0010=EXT SYNCH
0011.SLAVE SYNCH
0100=ASYNCH 8 BITs/cHAR
0101=ASYNCH 9 BITS/CHAR
0110=ASYNCH 10 BITSICHAR
0111=ASYNCH 11 BITS/CHAR
1100=FSK
O=XTAL
1=16XDATA
RATE OUTPUT
ATCLK PIN IN
DPSKMODE
ONLY
OOXX-73K212L, 322L, 321 L
01 XX=73K221 L, 302L
10XX=73K222L
1100=73K224L
1110=73K324L
1101 =73K312L
3-8
O=DISABLE
TXAOUTPUT
1=ENABLE
TXAOUTPUT
O=ANSWER
1=ORIGINATE
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 0
~D5
CRO
000
BIT NO.
DO
01
04
02
03
01
DO
TRANSM IT TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
MODE 3
MOOE2
MODE 1
ENABLE ORIGINATE
MOOEO
NAME
CONDITION
DESCRIPTION
Answer/
Originate
0
Selects answer mode (transmit in high band, receive
in low band).
1
Selects originate mode (transmit in low band,receive in
high band).
Transmit
0
Disables transmit output at TXA.
Enable
1
Enables transmit output at TXA.
Note: Answer tone and OTMF TX control require TX
enable.
05 04 03 02
05,04,03,
02
Transmit
Mode
0
0
0
0
Selects power down mode. All functions
disabled except digital interface.
0
0
0
1
Internal synchronous mode. In this mode TXCLK is an
internally derived 1200 Hz signal. Serial input data
appearing at TXO must be valid on the rising edge of
TXCLK. Receive data is clocked out of RXO on the
falling edge of RXCLK.
0
0
1
0
External synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 1200 Hz clock must be
supplied externally.
0
0
1
1
Slave synchronous mode. Same operation as other
synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.
0
1
0
0
Selects OPSK asynchronous mode - 8 bits/character
(1 start bit, 6 data bits, 1 stop bit).
0
1
0
1
Selects OPSK asynchronous mode - 9 bits/character
(1 start bit, 7 data bits, 1 stop bit).
0
1
1
0
Selects OPSK asynchronous mode - 10 bits/character
(1 start bit, 8 data bits, 1 stop bit).
0
1
1
1
Selects OPSK asynchronous mode - 11 bits/character
(1 start bit, 8 data bits, Parity and 1 stop or 2 stop bits).
1
1
0
0
Selects FSK peration.
"
3-9
•
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 1
CR1
001
D7
D6
D5
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTER.
BIT NO.
NAME
D1,00
Test Mode
CONDITION
D4
D3
BYPASS
ClK
SCRAMB CONTROL
D2
D1
DO
RESET
TEST
MODE
1
TEST
MODE
0
DESCRIPTION
D1 DO
D2
D3
D4
D5
Reset
ClK Control
(Clock Control)
Bypass
Scrambler
Enable Detect
Interrupt
0
0
Selects normal operating mode.
0
1
Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable bit must be low.
1
0
Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is ignored.
1
1
Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit data carrier at
the TXA pin.
0
Selects normal operation.
1
Resets modem to power down state. All control register bits (CRO, CR1, Tone) are reset to zero. The output
of the ClK pin will be set to the crystal frequency on
reset.
0
Selects 11.0592 MHz crystal echo output at ClK pin.
1
Selects 16 X the data rate, output at ClK pin in DPSK
modes only.
0
Selects normal operation. DPSK transmij data is passed
through scrambler.
1
Selects Scrambler Bypass. Bypass DPSK data is
routed around scrambler in the transmit path.
0
Disables interrupt at INT pin.
1
Enables INT output. An interrupts will be generated
with a change in status of DR bits D1-D4. The answer
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TX DTMF is activated. All interrupts will be
disabled if the device is in power down mode.
3-10
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 1
CR1
001
BIT NO.
(Continued)
07
06
05
TRANSMIT
PATIERN
1
TRANSMIT
PATIERN
0
ENABLE
DETECT
INTER.
NAME
CONDITION
04
02
01
DO
RESET
TEST
MODE
1
TEST
MODE
0
03
BYPASS
ClK
SCRAMB CONTROL
DESCRIPTION
07 06
07,06
Transmit
Pattern
0
0
Selects normal data transmission as controlled
by the state of the TXD pin.
0
1
Selects an alternating mark/space transmit pattern for
modem testing.
1
0
Selects a constant mark transmit pattern.
1
1
Selects a constant space transmit pattern.
DETECT REGISTER
BIT NO.
NAME
CONDITION
DO
lONG lOOP
0
D1
CAll
PROGRESS
DETECT
02
03
04
DESCRIPTION
Indicates normal received signal.
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in
the 350 to 620 Hz call progress band.
ANSWER
TONE
DETECT
0
CARRIER
DETECT
0
UNSCRAMBLED
MARK
0
No answer tone detected.
Indicates detection of 2225 Hz answer tone. The
device must be in originate mode for detection of
answer tone.
No carrier detected in the receive c
nel.
Indicated carrier has been detected in the received
channel.
No unscrambled mark.
Indicates detection of unscrambled marks in the
received data. A valid indication requires that
unscrambled marks be received for> 165.5 ± 6.5 ms.
3-11
•
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
DETECT REGISTER (Continued)
BIT NO.
NAME
D5
D5
D4
D3
D2
D1
DO
RECEIVE
DATA
UNSCR.
MARK
CARR.
DETECT
ANSWER
TONE
CALL
PROG.
LONG
LOOP
CONDITION
RECEIVE
DATA
DESCRIPTION
Continuously outputs the received data stream. This
data is the same as that output on the RXD pin, but it
is not disabled when RXD is tri-stated.
D6,D7
Not used.
TONE REGISTER
TR
011
BIT NO.
D7
D5
D4
D3
D2
D1
DO
RXD
OUTPUT
CONTR.
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF3
DTMF2
DTMF1
DTMFO
NAME
CONDITION
DESCRIPTION
D3 D2 D1 DO
D3, D2,
D1,DO
DTMF
o a
0
0-
1
1
Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTM F and TX enable bit (CRO, bit
D1) are set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT
DTMF CODE
D3 D2 D1 DO
TONES
LOW HIGH
D
a a a a
941
3-12
1633
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
TONE REGISTER
TR
011
(Continued)
D7
D5
D4
D3
D2
D1
RXD
OUTPUT
CONTR.
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF 3
DTMF 2
DTMF 1
BIT NO.
NAME
CONDITION
DESCRIPTION
TRANSMIT
DTMF
a
Disable DTMF.
TRANSMIT
ANSWER
TONE
a
RXD OUTPUT
CONTROL
a
D4
D5
D7
DO
DTMF
a
Activates DTMF. The selected DTMF tones are
transmitted continuously when this bit is high (with
Transmit Enable, CRO-D1). TX DTMF overrides all
other transmit functions.
r.
Disable
Enables answer tone generator. A 2225 Hz answer
tone will be transmitted continuously when the Transmit Enable bit is set in CRO. The device must be in
answer mode.
Enables RXD pin. Receive data will be output on
RXD.
Disables RXD pin. The RXD pin reverts to a high
impedance with internal, weak pull-up resistor.
10 REGISTER
ID
110
D7
D6
D5
D4
D3
ID
ID
ID
ID
ID
BIT NO.
NAME
D7,D6,D5
Dev~e
CONDITION
D7 D6 D5 D4
D4
a a x x
DESCRIPTION
Indicates Device:
SSI 73K212L, 73K321 Lor 73K322L or
Identification
Signature
3-13
L
•
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
VDD Supply Voltage
14 V
Storage Temperature
-65 to 150°C
Soldering Temperature (10 sec.)
260°C
Applied Voltage
-0.3 to VDD + 0.3 V
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
NOM
MAX
UNITS
VDD Supply Voltage
4.5
5
5.5
V
TA, Operating Free-Air
Temperature
-40
+85
°C
-0.01
+0.01
%
2.2
MQ
Clock Variation
CONDITIONS
(11.0592 MHz) Crystal or
external clock
External Components (Refer to Application section for placement.)
~F
VREF Bypass capacitor
(External to GND)
0.1
Bias setting resistor
and ISET pins)
(Placed between VDD
1.8
ISET Bypass capacitor
(ISET pin to GND)
0.1
IlF
VDD Bypass capacitor 1
(External to GND)
0.1
J.1F
VDD Bypass capacitor 2
(External to GND)
22
XTl1 load Capacitor
Depends on crystal characteristics;
40
XTl2 load Capacitor
from pin to GND
20
2
J.1F
pF
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)
PARAMETER
100, Supply Current
IDDA, Active
IDD1, Power-down
IDD2, Power-down
CONDITIONS
MIN
NOM
MAX
UNITS
8
12
rnA
4
rnA
3
rnA
ISET Resistor = 2 MQ
= 11.0592 MHz
ClK = 11.0592 MHz
ClK = 19.200 kHz
ClK
Digital Inputs
VIH, Input High Voltage
Reset, XTl1 , XTl2
3.0
VDD
V
All other inputs
2.0
VDD
V
3-14
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS (continued)
(TA = -40°C to 85°C, VDO = recommended range unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
Vll, Input low Voltage
NOM
0
IIH, Input High Current
VI = VIH Max
Ill, Input low Current
VI = Vil Min
-200
Reset Pull-down Current
Reset = VDO
1
Input Capacitance
All Digital Input Pins
MAX
UNITS
0.8
V
100
j.lA
j.lA
50
j.lA
10
pF
Digital Outputs
VOH, Output High Voltage
10H MIN = -0.4 rnA
VOL, Output low Voltage
10 MAX=1.6 mA
VOL, ClK Output
10=3.6mA
RXD Tri-State Pull-up Curr.
RXD = GNO
CMAX, ClK Output
Maximum Capacitive load
2.4
-1
VDD
V
0.4
V
0.6
V
-50
j.lA
15
pF
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to + 85°C, VDD = recommended range unless otherwise noted.)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
-10.0
-9
dBmO
PSK Modulator
Carrier Suppression
Measured at TXA
55
Output Amplitude
TX scrambled marks
-11
-0.35
dB
FSK Mod/Demod
+.35
%
-10.0
-9
dBmO
TH 0 in the alternate band
DPSK or FSK
-60
-50
dB
Output Bias Distortion
Transmit Dotting Pattern
InAlB@ RXD
±8
Total Output Jitter
Random Input in ALB @ RXD
Output Freq. Error
ClK = 11.0592 MHz
Transmit level
Transmit Dotting Pattern
Harmonic Distortion
in 700-2900 Hz band
-11
-15
%
+15
%
DTMF Generator
-.25
Freq. Accuracy
Output Amplitude
low-Band, DPSK Mode
-10
-9
+.25
%
-8
dBmO
Output Amplitude
High-Band, DPSK Mode
-8
-7
-6
dBmO
Twist
High-Band to low-Band,DPSK mode
1.0
2.0
3.0
dB
Long Loop Detect
OPSK or FSK
-38
-28
dBmO
Dynamic Range
Refer to Performance Curves
3-15
45
dB
•
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING
PARAMETERS
(Continued)
CONDITIONS
MIN
NOM
MAX
UNITS
Call Progress Detector
Detect Level
2-Tones in 350-600 Hz band
Reject Level
2-Tones in 350-600 Hz band
Delay Time
-70 dBmO to -30 dBmO STEP
27
Hold Time
-30 dBmO to -70 dBmO STEP
27
Hysteresis
-34
0
dBmO
-41
dBmO
80
ms
80
ms
2
dB
Carrier Detect
Threshold
DPSK or FSK receive data
-49
-42
dBmO
Delay Time
-70 dBmO to -30 dBmO STEP
15
45
ms
Hysteresis
Single tone detected
2
Hold Time
-30 dBmO to -70 dBmO STEP
10
24
ms
In FSK mode
-49
-42
dBmO
Delay Time
-70 dBmO to -30 dBmO STEP
20
45
ms
Hold Time
-30 dBmO to -70 dBmO STEP
10
30
ms
-2.5
+2.5
%
3
dB
Answer Tone Detector
Detect Level
Detect Freq. Range
Output Smoothing Filter
TXA pin Output Impedance
200
300
0
Output load
TXA pin; FSK Single
Tone out for THD = -50 db
in .3 to 3.4 KHz
50
pF
Spurious Freq. Compo
= 76.8 KHz
Frequency = 153.6 KHz
-39
dBmO
-45
dBmO
TXA pin; 76.8 KHz
1.0
mVms
+10
Hz
100
ms
+625
ppm
50
ms
Clock Noise
kO
10
Frequency
Carrier VCO
Capture Range
Originate or Answer
Capture Time
-10Hz to +10 Hz Carrier
Freq. Change Assum.
-10
40
Recovered Clock
Capture Range
% of frequency
center frequency
(center at 1200 Hz)
Data Delay Time
Analog data in at RXA pin to
receive data valid at RXD pin
3-16
-625
30
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
PARAMETERS
(Continued)
CONDITIONS
MIN
NOM
MAX
UNITS
Timing (Refer to Timing Diagrams)
TAL
CS/Addr. setup before ALE low
30
ns
TLA
CS/Addr. hold after ALE low
20
ns
TLC
ALE low to R D/WR low
40
ns
TCL
RD/WR Control to ALE high
10
TRD
Data out from RD low
0
TLL
ALE width
60
TRDF
Data float after RD high
0
ns
160
ns
80
ns
ns
TRW
RD width
200
25000
ns
TWW
WR width
140
25000*
ns
TDW
Data setup before WR high
150
ns
TWD
Data hold after WR high
20
ns
TCKD
Data out after EXCLK low
TCKW
WR after EXCLK low
150
ns
TDCK
Data setup before EXCLK low
150
ns
TAC
Address setup before control**
50
ns
TCA
Address hold after control**
50
ns
TWH
Data Hold after EXCLK
20
ns
*
Maximum time applies to parallel version only.
**
Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.
200
Note: Parameters expressed in dBmO refer to the following definition:
5V Version
o dB loss in the Transmit path to the line.
2 dB gain in the receive path from the line.
Refer to the Basic Box Modem deagram in the Applications section for the DAA design.
3-17
ns
•
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
ALE
~
~
~
TlC
AD
.I
TRW
1
TCl
J
,f-
-I;-
TlC
TLA
L
ADO-AD7
es
J
-+
WR
---K
-=i-
TAL
.I.!.i
>i----K
~
ADDRESS
TRD
TRDF
~
READ DATA
~D
.J-
TDW
>i----K
-~-
-4-
J
TWW
ADDRESS
>i----K
WRITE DATA}-
-4-
READ TIMING DIAGRAM (SERIAL VERSION)
EXClK
AO-A2
DATA
--+
WRITE TIMING DIAGRAM (SERIAL VERSION)
EXClK
-----+----------------------------------------r-~
TCKW
I,TAC.
AO-A2 ----+------------------------------------------+f-.
DATA
3-18
HTWW
I~
TCA
SSI73K212L
Bell 212A/1 03
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
ClK
GND
XTl1
RXA
XTL2
GND
RXA
VREF
XTL1
RESET
A1
AD
VDD
VREF
ADO
RESET
AD1
ISET
AD2
RXClK
ISET
AD3
RXD
RXCLK
AD4
TXD
RXD
AD5
cs
4
3
2
1
28 27 26
25
24
PLCC PINOUTS
ARE THE SAME AS
THE 28-PIN DIP
23
TXD
ADS
EXClK
EXCLK
AD7
TXClK
TXCLK
ALE
TNT
10
20
INT
WR
TXA
11
19
TXA
AD
VDD
400-Mil
22-Pin DIP
22
21
12 13 14 15 16 17 18
28-Pin
PLCC
600-Mil
28-Pin DIP
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
Plastic Dual-In-Line
73K212L -IP
73K212L-IP
Plastic Leaded Chip Carrier
73K212L-IH
73K212L - IH
28-pin
22-pin
Plastic Dual-In-Line
73K212SL -IP
73K212SL -IP
Ceramic Dual-In-Line
73K212SL -IC
73K212SL -IC
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
0194 - rev.
3-19
Protected by the following Patents (4,691,172) (4,777,453)
©1989 Silicon Systems, Inc.
•
Notes:
3-20
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
January 1994
DESCRIPTION
FEATURES
The SSI 73K221 L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a CCITT V.22 and V.21 compatible modem,
capable of 1200 or 0-300 bitls full-duplex operation
over dial-up lines. The SSI 73K221 L is an enhancement of the SSI 73K212L single-chip modem with
performance characteristics suitable for European and
Asian telephone systems. The SSI73K221 L produces
either 550 or 1800 Hz guard tone, recognizes and
generates a 21 00 Hz answer tone, and allows V.21 for
300 Hz FSK operation. The SSI 73K221 L integrates
analog, digital, and switched-capacitor array functions
on a single substrate, offering excellent performance
and a high level of functional integration in a single 28or 22-pin DIP configuration. The SSI 73K221 L, operates from a single +5 volt supply.
One-chip CCITT V.22 and V.21 standard compatible modem data pump
Full-duplex Operation at 0-300 bitls (FSK) or 600
and 1200 bitls (DPSK)
Pin and software compatible with other
S51 K-Series 1-chip modems
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Serial (22-pin DIP) or parallel (28-pin DIP or
PLCC) microprocessor bus for control
Serial port for data transfer
The SSI 73K221 L includes the DPSK and FSK modulator/demodulator functions, call progress and handshake tone monitor test modes, and a tone generator
capable of producing DTMF, answer and 550 or
1800 Hz guard tone. This device supports
V.22 (Except mode v) and V. 21 modes of operation,
Test modes available: ALB, DL, RDL, Mark,
Space, Alternating bit patterns
Precise automatic gain control allows 45 dB
dynamic range
Space efficient 22- or 28-pin DIP or 28 Pin PLCC
packages
CMOS technology for low power consumption
using 30 mW @ 5V
Single +5 volt supply
Both Synchronous and Asynchronous modes of
operation
Call progress, carrier, precise answer tone
(2100 Hz), and long loop detectors
DTMF, and 550 or 1800 Hz guard tone generators
(Continued)
BLOCK DIAGRAM
PIN DIAGRAM
ClK
GND
XTL1
RXA
ADO-AD7
XTL2
All
WR
ALE
cs
RESET
O------.!
0----..1
0----..1
0----..1
0----..1
iN!' D - - - - - j
TXA
RXA
SMART
DIALING
&
TXD
RXD
o-------~
F~i~~s J . + - - - - - . . . . l
0-------....,
VREF
ADO
RESET
AD1
ISET
AD2
RXClK
AD3
RXD
AD4
TXD
AD5
CS
AD6
EXClK
AD7
ALE
WR
TXA
RD
VDD
CAUTION: Use handling procedures necessary
for a static sensitive component.
)194 - rev.
3-21
I
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
DESCRIPTION (Continued)
FSK modes. If serial input data contains a break signal
through one character (including start and stop bits) the
break will be extended to at least 2· N + 3 bits long
(where N is the number of transmitted bits/character).
allowing both synchronous and asynchronous communications. The SSI 73K221 L is designed to appear
to the systems designer as a microprocessor peripheral, and will easily interface with popular one-chip
microprocessors (80C51 typical) for control of modem
functions through its 8-bit multiplexed address/data
bus or alternatively via the serial control bus. An ALE
control line simplifies address demultiplexing. Data
communications occurs through a separate serial port
only.
Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC rate converter. The SYNC/ASYNC
convertor will reinsert any deleted stop bits and transmit output data at an intra-character rate (bit-to-bit
timing) of no greaterthan 1219 bit/so An incoming break
signal (low through two characters) will be passed
through without incorrectly inserting a stop bit.
The SYNC/ASYNC converter also has an extended
Overspeed mode which allows selection of an output
range of either +1% or +2.3%. In the extended
Overspeed mode, stop bits are output at 7/8 the normal
width.
The SSI73K221 L is ideal for use in either free standing
or integral system modem products where full-duplex
1200 bit/s data communications over the 2-wire
switched telephone network is desired. Its high functionality, low power consumption and efficient packaging simplify design requirements and increase system
reliability. A complete modem requires only the addition of the phone line interface, a control microprocessor, and RS-232 level converter for a typical system.
The SSI73K221 L is part of Silicon Systems' K-Series
family of pin and function compatible single-chip modem products. These devices allow systems to be
configured for higher speeds and Bell or CCITT operation with only a single component change.
SYNCHRONOUS MODE
The CCITTV.22 standard defines synchronous operation at 600 and 1200 bit/so The Bell 212A standard
defines synchronous operation only at 1200 biVs.
Operation is similar to that of the Asynchronous mode
except that data must be synchronized to a provided
clock and no variation in data transfer rate is allowable.
Serial input data appearing at TXD must be valid on the
rising edge of TXCLK.
OPERATION
TXCLK is an internally derived signal in Internal mode
and is connected internally to the RXCLK pin in Slave
mode. Receive data at the RXD pin is clocked out on
the falling edge of RXCLK. The ASYNC/SYNC converter is bypassed when Synchronous mode is
selected and data is transmitted at the same rate as it
is input.
ASYNCHRONOUS MODE
Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous
fashion, The SSI 73K221 L includes ASYNC/SYNC
and SYNC/ASYNC converters which delete or insert
stop bits in order to transmit data at a regular rate. In
Asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC rate converter. The
ASYNC/SYNC rate converter accepts the data provided on the TXD pin which normally must be 1200 or
600 bit/s + 1.0%, - 2.5%. The rate converter will then
insert or delete stop bits in order to output a signal
which is 1200 or 600 bit/s ± 0.01 %.
DPSK MODULATOR/DEMODULATOR
The SSI 73K221 L modulates a serial bit stream into
dibit pairs that are represented by four possible phase
shifts as prescribed by the V.22 standard. The
baseband signal is then filtered to reduce intersymbol
interference on the bandlimited 2-wire telephone line.
Transmission occurs on either a 1200 Hz (Originate
mode) or 2400 Hz carrier (Answer mode). Demodulation is the reverse of the modulation process, with the
incoming analog signal eventually decoded into di-bits
and converted back to a serial bit stream. The demodulator also recovers the clock which was encoded into
the analog signal during modulation. Demodulation
The serial data stream from the ASYNC/SYNC converter is passed through the data scrambler and onto
the analog modulator. The data scrambler can be
bypassed under processor control when unscrambled
data must be transmitted. The ASYNC/SYNC rate
converter and the data scrambler are bypassed in all
3-22
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
occurs using either a 1200 Hz carrier (Answer mode or
ALB Originate mode) or a 2400 Hz carrier (Originate
mode or ALB Answer mode). The SSI73K221L uses
a phase locked loop coherent demodulation technique
for optimum performance.
FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. V.21 mode uses 980 and
1180 Hz (originate, mark and space) or 1650 and
1850 Hz (answer, mark and space). Demodulation
involves detecting the received frequencies and
decoding them into the appropriate binary value. The
rate converter and scrambler/descrambler are bypassed in the V.21 mode.
SERIAL COMMAND INTERFACE
The serial Command mode allows access to the
SSI 73K221 L control and status registers via a serial
command port (22-pin version only). In this mode the
AO ,A1 and A21ines provide register addresses for data
passed through the data pin under control of the RD
and WR lines. A read operation is initiated when the RD
line is taken low. The first bit is available after RD is
brought low and the next seven cycles of EXCLK will
then transfer out the remaining seven bits of the selected address LSB first. A write takes place by shifting
in eight bits of data LSB first for eight consecutive
cycles of EXCLK. WR is then pulsed low and data
transferred into the addressed register on the rising
edge of WR.
PASSBAND FILTERS AND EQUALIZERS
SPECIAL DETECT CIRCUITRY
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band signals in the receive channel. Amplitude and phase equalization are
necessary to compensate for distortion of the transmission line and to reduce intersymbol interference in the
band limited receive signal. The transmit signal filtering
approximates a 75% square root of raised Cosine
frequency response characteristic.
The special detect circuitry monitors the received
analog signal to determine status or presence of carrier, call-progress tones, answer tone and weak
received signal (long loop condition). An unscrambled
mark signal is also detected when the received data out
of the DPSK demodulator before the descrambler has
been mark for 165.5 ms ± 6.5 ms minimum. The
appropriate detect register bit is set when one of these
conditions changes and an interrupt is generated for all
conditions except long loop. The interrupts are disabled (masked) when the enable interrupt bit is setto O.
AGC
DTMF GENERATOR
The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
dynamic range of >45 dB.
The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode
is selected using the tone register and the transmit
enable (CRO bit 01) is changed from 0 to 1.
PARALLEL BUS INTERFACE
Four 8-bit registers are provided for control, optionselect and status monitoring. These registers are
addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The detect register is read only and
cannot be modified except by modem response to
monitored parameters.
3-23
I
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
PIN DESCRIPTION
POWER
28-PIN
22-PIN
TYPE
DESCRIPTION
GND
28
1
I
System Ground.
VDD
15
11
I
Power supply input, 5V ±1 0%. Bypass with 0.1 and 22 IlF
capacitors to ground.
VREF
26
21
0
An internally generated reference voltage. Bypass with
0.1 IlF capacitor to GND.
ISET
24
19
I
Chip current reference. Sets bias currentforop-amps. The
chip current is set by connecting this pin to VDD through a
2 MQ resistor. ISET should be bypassed to GND with a
0.1 IlF capacitor.
NAME
PARALLEL MICROPROCESSOR INTERFACE
12
-
I
Address latch enable. The falling edge of ALE latches the
address on ADO-AD2 and the chip select on CS.
4-11
-
I/O
Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
control registers.
CS
20
-
I
Chip select. A low on this pin during the falling edge of ALE
allows a read cycle or a write cycle to occur. ADO-AD7 will
not be driven and no registers will be written if CS (latched)
is not active. The state CS is a latched on the falling edge
of ALE.
ClK
1
2
0
Output clock. This pin is selectable under processor control
to be either the crystal frequency (for use as a processor
clock) or 16 x the data rate for use as a baud rate clock in
DPSK modes only. The pin defaults to the crystal frequency
on reset.
INT
17
13
0
Interrupt. This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.
RD
14
-
I
Read. A low requests a read of the SSI 73K221 l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.
RESET
25
20
I
Reset. An active high signal on this pin will put the chip into
an inactive state. All control register bits (CRO, CR1 , Tone)
will be reset. The output of the ClK pin will be set to the
crystal frequency. An internal pull down permits power on
reset using a capaCitor to VDD.
ALE
ADO-AD7
3-24
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
PIN DESCRIPTION
(Continued)
PARALLEL MICROPROCESSOR INTERFACE (Continued)
NAME
WR
28-PIN
22-PIN
TYPE
13
-
I
DESCRIPTION
Write. A low on this pin informs the SSI 73K221 L that data
is available on ADO-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.
SERIAL MICROPROCESSOR INTERFACE
AO-A2
-
5-7
I
Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.
DATA
-
8
I/O
Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.
RD
-
10
I
Read. A low on this input informs the SSI73K221 L that data
or status information is being read by the processor. The
falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.
WR
-
9
I
Write. A low on this input informs the SSI 73K221 L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the rising edge
of WR.
Note:
In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the
pins; AO, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.
The Serial Control mode is provided in the parallel control versions by tying ALE high and CS low.
In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2,
respectively.
3-25
I
SSI73K221L
CCITI V.22, V.21
Single-Chip Modem
PIN DESCRIPTION (Continued)
DTE USER INTERFACE
NAME
28-PIN
22-PIN
TYPE
EXCLK
19
15
I
External Clock. This signal is used in synchronous transmission when the external timing option has been selected.
In the External Timing mode the rising edge of EXCLK is
used to strobe synchronous DPSK transmit data applied to
the TXD pin. Alternately used for serial control interface.
RXCLK
23
18
0
Receive Clock. The falling edge of this clock output is
coincident with the transitions in the serial received data
output. The rising edge of RXCLK can be used to latch the
valid output data at RXD. RXCLK will be valid as long as a
carrier is present in DPSK synchronous modes.
RXD
22
17
0
Received Digital Data Output. Serial receive data is available on this pin. The data is always valid on the rising edge
of RXCLK when in Synchronous mode. RXD will output
constant marks if no carrier is detected.
TXCLK
18
14
0
Transmit Clock. This signal is used in DPSK synchronous
transmission to latch serial input data on the TXD pin. Data
must be provided so that valid data is available on the rising
edge of the TXCLK. The transmit clock is derived from
different sources depending upon the Synchronization
mode selection. In Internal Mode the clock is generated
internally. In External Mode TXCLK is phase locked to the
EXCLK pin. In Slave Mode TXCLK is phase locked to the
RXCLK pin. TXCLK is always active.
TXD
21
16
I
Transmit Data Input. Serial data for transmission is applied
to this pin. In Synchronous modes, the data must be valid
on the rising edge of the TXCLK. In Asynchronous modes
(1200/600 biVs or 300 baud) no clocking is necessary.
DPSK data must be 1200/600 bitls + 1%, -2.5% or +2.3%,
-2.5 % in extended Overspeed mode.
DESCRIPTION
ANALOG INTERFACE AND OSCILLATOR
RXA
27
22
I
TXA
16
12
0
Transmit analog output to the telephone line interface.
XTL1
XTL2
2
3
3
4
I
I
These pins are for the internal crystal oscillator requiring
an 11.0592 MHz Parallel mode crystal. Load capacitors
should be connected from XTL 1 and XTL2 to Ground. XTL2
can also be driven from an external clock.
Received modulated analog signal input from the telephone line interface.
3-26
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
REGISTER DESCRIPTIONS
Four a-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AD and A1
address lines in Serial mode, orthe ADO and AD1 lines
in Parallel mode. In Parallel mode ADO and AD1 lines
are latched by ALE. Register CRO controls the method
by which data is transferred over the phone line. CR1
controls the interface between the microprocessor and
the SSI 73K221 L internal state. DR is a detect register
which provides an indication of monitored modem
status conditions. TR, the tone control register, controls the DTM F generator, answer and guard tones and
RXD output driver used in the modem initial connect
sequence. All registers are read/write except for DR
which is read only. Register control and status bits are
identified below:
REGISTER BIT SUMMARY
I
CRO
CONTROL
REGISTER
1
DETECT
REGISTER
CRl
001
DR
010
TONE
CONTROL
REGISTER
m
011
CONTROL
REGISTER
2
CR2
100
CONTROL
REGISTER
3
CR3
101
10
REGISTER
10
110
NOTE:
ENABLE
DETECT
INTERRUPT
BYPASS
SCRAMBLER
RECEIVE
DATA
UNSCR.
MARKS
CARRIER
DETECT
ANSWER
TONE
TRANSMIT
DTMF
DTMF3
DTMF2
When a register containing reserved
control bits is written into, the reserved bits
must be programmed as D's.
3-27
CLK
CONTROL
RESET
TEST
MODE
1
TEST
MODE
CALL
PROGRESS
LONG
LOOP
DTMFlf
OVERSPEED
0
DTMFOf
GUARDf
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
REGISTER ADDRESS TABLE
0=1200 Bms DPSK
1-600 BITtS DPSK
OOOO.PWR DOWN
0001-INT SYNCH
DOl0.EXT SYNCH
0011-SLAVE SYNCH
0100.ASYNCH 8 BITSICHAR
0101.ASYNCH 9 BITSICHAR
0110=ASYNCH 10 BITSICHAR
0111.ASYNCH 11 BITSICHAR
1100=FSK
O-DISABLE
TXAOUTPUT
l-ENABLE
TXAOUTPUT
O-ANSWER
l=ORIGINATE
O=XTAL
1=16X DATA
RATE OUTPUT
ATCLK PIN IN
DPSKMODE
ONLY
0=1800 Hz G.T.
1-550 Hz G.T.
00XX-73K212L. 322L. 321 L
01 XX=73K221 L. 302L
10XX-73K222L
1100=73K224L
1110=73K324L
11 01 =73K312L
3-28
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
CONTROL REGISTER 0
07
CRO
000
..
MOOUL.
OPTION
BIT NO.
DO
01
05
02
03
04
01
TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT
MODE 3
MODE 2
MODE 1
MODE 0
ENABLE
DO
ANSWER/
ORIGINATE
NAME
CONDITION
Answer/
Originate
0
Selects Answer mode (transmit in high band, receive
in low band).
1
Selects Originate mode (transmit in low band, receive
in high band).
Transmit
0
'lIe:; ::mIPe:;
Enable
1
Enables transmit output at TXA.
Note: TX Enable must be set to 1 to allow Answer Tone
and OTMF transmission.
DESCRIPTION
transmit output at TXA
05 04 03
05,04,03,
02
Transmit
Mode
0
0
0
0
Selects Power Down mode. All functions disabled
except digital interface.
0
0
0
1
Internal Synchronous mode. In this mode TXCLK is an
internally derived 1200 Hz signal. Serial input data
appearing at TXO must be valid on the rising edge of
TXCLK. Receive data is clocked out of RXO on the
falling edge of RXCLK.
0
0
1
0
External Synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internallyto EXCLK pin, and a 1200 Hz ± 0.01 % clock must
be supplied externally.
0
0
1
1
Slave Synchronous mode. Same operation as other
Synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.
0
1
0
0
Selects OPSK Asynchronous mode - 8 bits/character
(1 start bit, 6 data bits, 1 stop bit).
0
1
0
1
Selects OPSK Asynchronous mode - 9 bits/character
(1 start bit, 7 data bits, 1 stop bit).
0
1
1
0
Selects OPSK Asynchronous mode - 10 bits/character
(1 start bit, 8 data bits, 1 stop bit).
0
1
1
1
Selects OPSK Asynchronous mode -11 bits/character
(1 start bit, 8 data bits, Parity and 1 stop bit).
II,
"
3-29
I
SSI73K221L
CClll V.22, V.21
Single-Chip Modem
CONTROL REGISTER 0
(Continued)
D5
D7
CRO
000
NAME
BIT NO.
D4
D3
D2
D1
DO
TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT
MODE 3
MODE 2
MODE 1
MODE 0
ENABLE
MODUL.
OPTION
CONDITION
ANSWER/
ORIGINATE
DESCRIPTION
Selects:
D7
DPSK mode at 1200 bit/so
Modulation
o
Option
X
DPSK mode at 600 bit/so
X = Don't care
CONTROL REGISTER 1
CR1
001
D7
D6
D5
D4
D3
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTER.
BYPASS
SCRAMB
ClK
CONTROL
BIT NO.
NAME
D1,DO
Test Mode
CONDITION
D2
D1
DO
RESET
TEST
MODE
1
TEST
MODE
0
DESCRIPTION
D1 DO
D2
D3
Reset
ClK Control
(Clock Control)
0
0
Selects normal Operating mode.
0
1
Analog loopback mode. Loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced
low.
1
0
Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is ignored.
1
1
Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit carrier from
TXA pin.
0
Selects normal operation.
1
Resets modem to power down state. All control
register bits (CRO, CR1, Tone) are reset to zero. The
output of the ClK pin will be set to the crystal
frequency.
0
Selects 11.0592 MHz crystal echo output at ClK
pin.
1
Selects 16 X the data rate, output at ClK pin in DPSK
modes only.
3-30
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
CONTROL REGISTER 1
CR1
001
BIT NO.
D4
D5
(Continued)
D7
D6
D5
D4
D3
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTER.
BYPASS
SCRAMB
ClK
CONTROL
D2
D1
DO
RESET
TEST
MODE
1
TEST
MODE
0
NAME
CONDITION
Bypass
Scrambler
0
Selects normal operation. DPSK data is passed
through scrambler.
1
Selects Scrambler Bypass. Bypass DPSK data is
routed around scrambler in the transmit path.
0
Disables interrupt at INT pin.
1
Enables INT output. An interrupts will be generated
with a change in status of DR bits D1-D4. The answer
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TX DTMF is activated. All interrupts will be
disabled if the device is in Power Down mode.
Enable Detect
Interrupt
DESCRIPTION
D7 D6
D7,D6
Transmit
Pattern
0
0
Selects normal data transmission as determined
by the state of the TXD pin.
0
1
Selects an alternating mark/space transmit pattern for
modem testing.
1
0
Selects a constant mark transmit pattern.
1
1
Selects a constant space transmit pattern.
DETECT REGISTER
DR
010
BIT NO.
DO
NAME
D5
D4
D3
D2
D1
DO
RECEIVE
DATA
UNSCR.
MARK
CARR.
DETECT
ANSWER
TONE
CAll
PROG.
lONG
lOOP
CONDITION
DESCRIPTION
long loop
Indicates low received signal level.
D1
Call Progress 1 - - - - - - - - + - - - - - - ' - - - = - - - - - - - - - - - - - - - - 1
Detect
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in
the 350 to 620 Hz call progress band.
3-31
I
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
DETECT REGISTER (Continued)
DR
010
BIT NO.
NAME
D2
Answer
Tone
Detect
D5
D4
D3
D2
D1
DO
RECEIVE
DATA
UNSCR.
MARK
CARR.
DETECT
ANSWER
TONE
CALL
PROG.
LONG
LOOP
CONDITION
Indicates detection of 2100 Hz answer tone. The
device must be in Originate mode for detection of
answer tone.
o
Carrier
Detect
D3
D4
No carrier detected in the receive channel.
Indicates carrier has been detected in the received
channel.
Unscrambled
Mark
Indicates detection of unscrambled marks in the
received data. This may be used in the V.22 connect
sequence orfor requesting a remote modem to configure itself for remote digitalloopback. A valid indication
means that unscrambled marks have been received
for> 165.5 ± 6.5 ms.
Receive
Data
D5
DESCRIPTION
Continuously outputs the received data stream. This
data is the same as that output on the RXD pin, but it
is not disabled when RXD is tri-stated.
TONE REGISTER
TR
011
D7
D6
D5
D4
D3
D2
D1
DO
RXD
OUTPUT
CONTR.
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF3
DTMF2
DTMF 11
OVERSPEED
DTMF 01
GUARD
BIT NO.
NAME
CONDITION
D6 D4 DO
DO
DTMF 01
Guard Tone
1
X
Transmit DTMF tones.
X
0
0
Transmits 1800 Hz guard tone.
0
1
Transmits 550 Hz guard tone.
D4 D1
DTMF 11
DO interacts with bits D6, D5, and D4 as shown.
X
X
D1
DESCRIPTION
D1 interacts with D4 as shown.
0
0
Asynchronous DPSK 1200 or 600 bitls +1.0% - 2.5%
0
1
Asynchronous DPSK 1200 or 600 bitls +2.3% -2.5%.
3-32
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
TONE REGISTER (Continued)
TR
011
07
06
05
04
RXD
OUTPUT
CONTR.
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
BIT NO.
NAME
03,02,
01, DO
DTMF 3,
2,1,0
CONDITION
03
DTMF3
02
01
DO
DTMF2
DTMF 11
OVERSPEED
DTMF 01
GUARD
DESCRIPTION
03 02 01 DO
0
1
0 01 1
0
1
Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTMF andTX enable bit (CRO, bit
01) is set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT
0
0
0
0
3
0
0
1
1
697
1477
4
0
1
0
0
770
1209
5
0
1
0
1
770
1336
6
0
1
1
0
770
1477
7
0
1
1
1
852
1209
8
1
0
0
0
852
1336
9
1
0
0
1
852
1477
0
1
0
1
0
941
1336
1
0
1
1
941
1209
1
1
0
0
941
1477
1
1
0
1
697
1633
1
#
A
B
C
0
05
Transmit
DTMF
Transmit
Answer
Tone
0
1
1
0
TONES
LOW HIGH
1
2
..
04
DTMF CODE
03 02 01 DO
697
697
1209
1336
1
1
0
770
1633
1
1
1
1
852
1633
0
0
0
0
941
1633
0
Disable DTMF.
1
Activates DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF
overrides all other transmit functions. Modem must be
in DPSK mode during DTMF transmission.
0
Disables answer tone generator.
1
Enables answer tone generator. A 2100 Hz answer
tone will be transmitted continuously when the
Transmit Enable bit is set in CRO. The device must be
in Answer mode.
3-33
I
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
TONE REGISTER (Continued)
TR
011
D7
D6
D5
D4
RXD
OUTPUT
CONTR.
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
D3
DTMF3 DTMF2
DTMF 01
GUARD
DESCRIPTION
0
Disables guard tone generator.
(Transmit
Guard Tone)
1
Enables guard tone generator (See DO for
selection of guard tones).
RXD Output
Control
0
Enables RXD pin. Receive data will be output on
RXD.
1
Disables RXD pin. The RXD pin becomes a high
impedance with internal weak pull-up resistor.
10 REGISTER
D7
D6
D5
D4
10
ID
ID
ID
110
NAME
CONDITION
D7 D6 D5 D4
D7, D6, D5
DTMF 11
OVERSPEED
CONDITION
D7
D4
DO
NAME
D6
BIT NO.
D1
TX Guard
BIT NO.
10
D2
DESCRIPTION
Indicates Device:
Device
Identification
Signature
3-34
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
V
-65 to 150
260
DC
DC
-0.3 to VDD+0.3
V
Storage Temperature
Soldering Temperature (10 sec.)
Applied Voltage
UNIT
14
VDD Supply Voltage
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
NOM
VDD Supply voltage
4.5
5
5.5
V
T A, Operating Free-Air
Temperature
-40
+85
DC
-0.01
+0.01
%
2.2
MQ
Clock Variation
CONDITIONS
(11.0592 MHz) Crystal or
external clock
MAX
UNITS
External Components (Refer to Application section for placement.)
VREF Bypass Capacitor
(External to GND)
0.1
Bias setting resistor
(Placed between VDD
and ISET pins)
1.8
JlF
2
ISET Bypass Capacitor
(ISET pin to GND)
0.1
VDD Bypass Capacitor 1
(External to GND)
0.1
JlF
VDD Bypass Capacitor 2
(External to GND)
22
JlF
XTL 1 Load Capacitor
Depends on crystal characteristics;
40
XTL2 Load Capacitor
from pin to GND
20
3-35
JlF
pF
I
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VOO = recommended range unless otherwise noted.)
PARAMETER
100, Supply Current
100A, Active
CONDITIONS
MIN
NOM
MAX
UNITS
8
12
rnA
ISET Resistor = 2 MQ
ClK = 11.0592 MHz
1001, Power-down
ClK = 11.0592 MHz
4
rnA
1002, Power-down
ClK = 19.200 KHz
3
rnA
Digital Inputs
VIH, Input High Voltage
Reset, XTl1, XTl2
3.0
VOO
V
All other inputs
2.0
VOO
V
0
0.8
V
100
~
Vll, Input low Voltage
IIH, Input High Current
VI = VIH Max
Ill, Input low Current
VI = Vil Min
-200
Reset Pull-down Current
Reset = VOO
1
Input Capacitance
All Digital Input Pins
~
50
~
10
pF
VOO
V
Digital Outputs
VOH, Output High Voltage
10H MIN = -0.4 rnA
2.4
VOL, Output low Voltage
10 MAX = 1.6 rnA
0.4
V
VOL, ClK Output
10=3.6 rnA
0.6
V
-50
~
15
pF
RXO Tri-State Pull-up Curro
RXO = GNO
CMAX, ClK Output
Maximum Capacitive load
-1
3-36
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VOD = recommended range unless otherwise noted.)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
PSK Modulator
Carrier Suppression
Measured at TXA
55
Output Amplitude
TX scrambled marks
-11
dB
-10
-9
dBmO
FSK Mod/Demod
Output Freq. Error
ClK
= 11.0592 MHz
-0.35
Transmit level
Transmit Dotting Pattern
-11
Harmonic Distortion
in 700-2900 Hz band
+ 0.35
%
-10
-9
dBmO
TH D in the alternate band
DPSK or FSK
-60
-50
dB
Output Bias Distortion
Transmit Dotting Pattern
InAlB@ RXD
±8
Total Output Jitter
Random Input in ALB @ RXD
-15
%
+15
%
+ 0.25
%
DTMF Generator (Modem must be in DPSK mode to meet specifications)
Freq. Accuracy
- 0.25
Output Amplitude
low Group, DPSK Mode
-10
-9
-8
dBmO
Output Amplitude
High Group, DPSK Mode
-8
-7
-6
dBmO
Twist
2.0
3.0
dB
-28
dBmO
High-Group to low-Group
1.0
Long Loop Detect
DPSK or FSK
-38
Dynamic Range
Refer to Performance Curves
45
dB
Call Progress Detector
Detect level
2-Tones in 350-600 Hz band
Reject level
2-Tones in 350-600 Hz band
Delay Time
-70 dBmO to -30 dBmO STEP
Hold Time
-30 dBmO to -70 dBmO STEP
-34
dBmO
dBmO
27
80
ms
27
80
ms
2
Hysteresis
Note:
0
-41
Parameters expressed in dBmO refer to the following definition:
5V Version
dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
o
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
3-37
dB
I
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
NOM
MAX
UNITS
-49
-42
dBmO
15
45
ms
CONDITIONS
MIN
Threshold
DPSK or FSK receive data
Delay Time
-70 dBmO to -30 dBmO STEP
Carrier Detect
3.0
Hysteresis
Single tone detected
2
Hold Time
-30 dBmO to -70 dBmO STEP
10
24
ms
-49.5
-42
dBmO
dB
Answer Tone Detector
Detect Level
Not in V.21 mode
Delay Time
-70 dBmO to -30 dBmO STEP
20
45
ms
Hold Time
-30 dBmO to -70 dBmO STEP
10
30
ms
-2.5
+2.5
%
Detect Freq. Range
Output Smoothing Filter
Output load
Spurious Freq. Compo
Output Impedance
Clock Noise
TXA pin; FSK Single
kQ
10
Tone out for THO = -50 db
in 0.3 to 3.4 KHz
50
pF
Frequency = 76.8 kHz
-39
dBmO
Frequency = 153.6 kHz
-45
dBmO
300
Q
1.0
mVms
TXA pin
200
TXA pin; 76.8 kHz
CarrierVCO
Capture Range
Capture Time
Originate or Answer
-10
40
-10Hz to +10 Hz Carrier
Frequency Change
+10
Hz
100
ms
+625
ppm
50
ms
Recovered Clock
-625
Capture Range
Data Delay Time
Analog data in at RXA pin to
receive data valid at RXD pin
3-38
30
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
Guard Tone Generator
Tone Accuracy
550 or 1800 Hz
-20
+20
Hz
Tone Level
550 Hz
-4.0
-3.0
-2.0
dB
(Below DPSK Output)
1800 Hz
-7.0
-6.0
-5.0
dB
Harmonic Distortion
550 Hz
-50
dB
700 to 2900 Hz
1800 Hz
-60
dB
Timing (Refer to Timing Diagrams)
TAL
..
*
CS/Addr. setup before ALE low
30
ns
TLA
CSIAddr. hold after ALE low
20
ns
TLC
ALE low to RD/WR low
40
ns
TCL
RD/WR Control to ALE high
10
TRD
Data out from RD low
0
ns
160
ns
TLL
ALE width
60
TRDF
Data float after RD high
0
TRW
RDwidth
200
25000
ns
TWW
WR width
140
25000·
ns
TOW
Data setup before WR high
150
ns
80
ns
ns
TWO
Data hold after WR high
TCKD
Data out after EXCLK low
TCKW
WR after EXCLK low
150
ns
TDCK
Data setup before EXCLK low
150
ns
20
ns
200
ns
TAC
Address setup before control··'
50
ns
TCA
Address hold after control··
50
ns
TWH
Data hold after EXCLK
150
ns
Maximum time applies to parallel version only.
Control for setup is the falling edge of RD or WR .
Control for hold is the falling edge of RD or the rising edge of WR.
3-39
I
SSI73K221L
CClll V.22, V.21
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
~
ALE
~_ _ _ _ _ _ _ _~_ _ _ _ _ _ _ __
TlC
TRW
-,-
TCl
J
...,1-
TlC
J
.I
TWW
+
L
ADO-AD?
--K
TAL
TlA
TRD
TRDF
~
~
~
ADDRESS
>I-----K
READ DATA
>I-----K
I
1111
ADDRESS
>I-----K
TOW
TWO
~'III ~.I
WRITE DATA)t--
READ TIMING DIAGRAM (SERIAL VERSION)
EXClK
AO-A2
DATA
--+
WRITE TIMING DIAGRAM (SERIAL VERSION)
EXClK
HTWW
-----+----------------------------------------~~i
TCKW
AO-A2.
II
TAC
-----+-------------------------------------------1*
DATA
3-40
I~
•
TeA
SSI73K221L
CCITT V.22, V.21
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
ClK
GND
RXA
ClK
VREF
XTl1
RESET
AO
GND
XTL1
RXA
XTL2
VREF
ADO
RESET
AD1
(SET
AD2
RXClK
(SET
AD3
RXD
4
3
2
1
28 27 26
25
RXCLK
AD4
TXD
A1
RXD
AD5
cs
A2
TXD
ADS
EXClK
DATA
EXCLK
AD7
TXClK
WR
TXCLK
ALE
1NT
10
20
(NT
WR
TXA
11
19
TXA
AD
VDD
AD
VDD
400-Mil
22-Pin DIP
600-Mil
28-Pin DIP
24
PLCC PINOUTS
ARE THE SAME AS
THE 28-PIN DIP
23
22
21
12 13 14 15 16 17 18
28-Pin
PLCC
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
SSI 73K221 L with Parallel Bus Interface
28-Pin DIP
73K221L-IP
73K221L -IP
28-Pin PLCC
73K221L-IH
73K221L -IH
SSI 73K212L with Serial Interface
22-Pin DIP
73K221 SL - IP
73K221 SL - IP
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
)194 - rev.
3-41
Protected by the following Patents {4,691 ,172) (4,777,453)
©1989 Silicon Systems, Inc.
I
Notes:
3-42
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
January 1994
DESCRIPTION
FEATURES
The SSI 73K222L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a CCITT V.22, V.21 and Bell 212A compatible modem, capable of 1200 bitls full-duplex operation over dial-up lines. The SSI 73K222L is an enhancement of the SSI 73K212L single-chip modem
which adds V.22 and V.21 modes to the Bell 212A and
103 operation of the SS173K212L. In Bell 212A mode,
the SSI 73K222L provides the normal Bell 212A and
103 functions and employs a 2225 Hz answer tone.
The SSI73K222L in V.22 mode produces either 550 or
1800 Hz guard tone, recognizes and generates a
2100 Hz answer tone, and allows 600 bitls V.22 or
0-300 bitls V.21 operation. The SSI 73K222L integrates analog, digital, and switched-capacitor array
functions on a single substrate, offering excellent performance and a high level of functional integration in a
single 28- or 22-pin DIP configuration. The
SSI 73K222L operates from a single +5V supply.
The SSI 73K222L includes the DPSK and FSK modulator/demodulator functions, call progress and handshake tone monitor and a tone generator capable of
One-chip CCITT V.22, V.21, Bell 212A and 103
standard compatible modem data pump
Full-duplex operation at 0-300 bitls (FSK) or 600 and
1200 bitls (DPSK)
Pin and software compatible with other
SSI K-Series 1-chip modems
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Serial or parallel microprocessor bus for control
Serial port for data transfer
Both synchronous and asynchronous modes of
operation including V.22 extended overspeed
Call progress, carrier, precise answer tone (2100 or
2225 Hz), and long loop detectors
DTMF, and 550 or 1800 Hz guard tone generators
Test modes available: ALB, DL, RDL, Mark, Space,
Alternating bit patterns
Precise automatic gain control allows 45 dB
dynamic range
CMOS technology for low power consumption using30mW@5V
Single +5 volt supply
(Continued)
BLOCK DIAGRAM
PIN DIAGRAM
ClK
ADO-AD7
11li 1"1.-_...-J
TXA
WIf
ALE
-os
RXA
RESET
TXD
o--------.!
RXD
D-------~
Xll'
RXA
Xll2
VREF
ADO
RESET
AD'
ISET
AD2
RXClK
AD3
RXD
AD4
TXD
ADS
CS
AD6
EXClK
AD7
ALE
WR
TXA
RD
VDD
CAUTION: Use handling procedures necessary
for a static sensitive component.
0194 - rev.
3-43
I
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
DESCRIPTION (Continued)
The serial data stream from the ASYNC/SYNC converter is passed through the data scrambler and onto
the analog modulator. The data scrambler can be
bypassed under processor control when unscrambled
data must be transmitted. The ASYNC/SYNC converter and the data scrambler are bypassed in all FSK
modes. If serial input data contains a break signal
through one character (including start and stop bits) the
break will be extended to at least 2 • N + 3 bits long
(where N is the number of transmitted bits/character).
tone required for European applications. This device
supports V.22 (except mode v) and V. 21 modes of
operation, allowing both synchronous and asynchronous communications. Test features such as analog
loop, digital loop, and remote digital loopback are
supported. Internal pattern generators are also
included for self-testing. The SSI73K222L is designed
to appear to the systems designer as a microprocessor
peripheral, and will easily interface with popular
one-chip microprocessors (80C51 typical) for control
of modem functions through its 8-bit multiplexed
address/data bus or serial control bus. An ALE control
line simplifies address demultiplexing. Data communications occurs through a separate serial port only.
Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC converter. The SYNC/ASYNC convertor will reinsert any deleted stop bits and transmit
output data at an intra-character rate (bit-to-bit timing)
of no greater than 1219 bitls. An incoming break signal
(low through two characters) will be passed through
without incorrectly inserting a stop bit.
The SSI73K222L is ideal for use in either free standing
or integral system modem products where full-duplex
1200 bitls data communications over the 2-wire
switched telephone network is desired. Its high functionality, low power consumption and efficient packaging simplify design requirements and increase system
reliability. A complete modem requires only the addition of the phone line interface, a control microprocessor, and RS-232 level converter for a typical system.
The SSI73K222L is part of Silicon Systems' K-Series
family of pin and function compatible single-chip
modem products. These devices allow systems to be
configured for higher speeds and Bell or CCITT operation with only a single component change.
The SYNC/ASYNC converter also has an extended
overspeed mode which allows selection of an
overspeed range of either +1% or +2.3%. In the extended overspeed mode, stop bits are output at 7/8 the
normal width.
SYNCHRONOUS MODE
The cCln V.22 standard defines synchronous operation at 600 and 1200 bit/so The Bell 212A standard
defines synchronous operation only at 1200 bit/so
Operation is similar to that of the asynchronous mode
except that data must be synchronized to a provided
clock and no variation in data transfer rate is allowable.
Serial input data appearing at TXD must be valid on the
rising edge of TXCLK.
OPERATION
ASYNCHRONOUS MODE
TXCLK is an internally derived signal in internal mode
and is connected internally to the RXCLK pin in slave
mode. Receive data at the RXD pin is clocked out on
the falling edge of RXCLK. The ASYNCH/SYNCH
converter is bypassed when synchronous mode is
selected and data is transmitted out at the same rate as
it is input.
Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous fashion. The SSI 73K222L includes ASYNC/SYNC and
SYNC/ASYNC converters which delete or insert stop
bits in order to transmit data within a ±0.01% rate. In
asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC converter. The
ASYNC/SYNC converter accepts the data provided on
the TXD pin which normally must be 1200 or 600 bitls
+ 1.0%, -2.5%. The converter will then insert or delete
stop bits in orderto output a signal which is 1200 or 600
bitls ± 0.01% (± 0.01% is required synchronous data
rate accuracy).
DPSK MODULATOR/DEMODULATOR
The SSI 73K222L modulates a serial bit stream into
di-bit pairs that are represented by four possible phase
shifts as prescribed by the Bell212A or V .22 standards.
The baseband signal is then filtered to reduce intersymbol interference on the band limited 2-wire
3-44
SSI73K222L
V.22, V.21, Bell 212A
Single-Chip Modem
PARALLEL BUS INTERFACE
telephone line. Transmission occurs using either a
1200 Hz (originate mode) or 2400 Hz carrier (answer
mode). Demodulation is the reverse of the modulation
process, with the incoming analog signal even~uall~
decoded into di-bits and converted back to a senal bit
stream. The demodulator also recovers the clock
which was encoded into the analog signal during
modulation. Demodulation occurs using either a
1200 Hz carrier (answer mode or ALB originate mode)
or a 2400 Hz carrier (originate mode or ALB answer
mode). The SSI 73K222L uses a phase locked loop
coherent demodulation technique for optimum
receiver performance.
Four 8-bit registers are provided for control, option
select and status monitoring. These registers are addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The detect register is read only and
cannot be modified except by modem response to
monitored parameters.
SERIAL COMMAND INTERFACE
The serial command interface allows access to the
SSI 73K222L control and status registers via a serial
command port (22-pin version only). In this mode the
AO, A 1 and A21ines provide register addresses fordata
passed through the data pin under control of the RD
and WR lines. A read operation is initiated when the RD
line is taken low. The first bit is available after RD is
brought low and the next seven cycles of EXCLK will
then transfer out seven bits of the selected address
LSB first. A write takes place by shifting in eight bits of
data LSB first for eight consecutive cycles of EXCLK.
WR is then pulsed low and data transferred into the
addressed register occurs on the rising edge of WR.
This interface mode is also supported in the 28-pin
packages. See serial control interface pin description.
FSK MODULATOR/DEMODULATOR
The FSK mod~lator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. In Bell 103, the standard
frequencies of 1270 and 1070 Hz (originate, mark and
space) or 2225 and 2025 Hz (answer, mark and space)
are used. V.21 mode uses 980 and 1180 Hz (originate,
mark and space), or 1650 and 1850Hz (answer, mark
and space). Demodulation involves detecting the received frequencies and decoding them into the
appropriate binary value. The rate converter and
scrambler/descrambler are bypassed in the 103 or
V.21 modes.
PASSBAND FILTERS AND EQUALIZERS
SPECIAL DETECT CIRCUITRY
High and low band filters are included to shape the
amplitude and phase response of the transmit an?
receive signals and provide compromise delay equalization and rejection of out-of-band signals in the
receive channel. Amplitude and phase equalization
are necessary to compensate for distortion of the
transmission line and to reduce intersymbol interference in the band limited receive signal. The transmit
signal filtering approximates a 75% square root of
raised Cosine frequency response characteristic.
The special detect circuitry monitors the received a~a
log signal to determine status or presence of carner,
call-progress tones, answer tone and weak received
signal (long loop condition). An unscrambled mark
request signal is also detected when the received data
out of the DPSK demodulator before the descrambler
has been high for 165.5 ms ± 6.5 ms minimum. The
appropriate detect register bit is set when one of these
conditions changes and an interrupt is generated for all
purposes except long loop. The interrupts are disabled
(masked) when the enable interrupt bit is set to O.
AGC
DTMF GENERATOR
The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
receiver dynamic range of >45 dB.
The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode
is selected using the tone register and the transmit
enable (CRO bit 01) is changed from 0 to 1.
3-45
3
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
PIN DESCRIPTION
POWER
NAME
28-PIN
22-PIN
TYPE
DESCRIPTION
GND
28
1
I
System Ground.
VDD
15
11
I
Power supply input. 5V ±10% (73K222l). Bypass with .1
and 22 ~F capacitors to GND.
VREF
26
21
0
An internally generated reference voltage. Bypass with
.1 JlF capacitor to ground.
ISET
24
19
I
Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 MQ resistor. ISET should be bypassed to GND with a
.1 JlF capacitor.
PARALLEL MICROPROCESSOR INTERFACE
12
-
I
Address latch enable. The falling edge of ALE latches the
address on ADO-AD2 and the chip select on CS.
4-11
-
I/O
Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
registers.
CS
20
-
I
Chip select. A low on this pin during the falling edge of ALE
allows a read cycle or a write cycle to occur. ADO-AD7 will
not be driven and no registers will be written if CS (latched)
is not active. The state of CS is latched on the falling edge
of ALE.
ClK
1
2
0
Output clock. This pin is selectable under processor control
to be either the crystal frequency (for use as a processor
clock) or 16 x the data rate for use as a baud rate clock in
DPSK modes only. The pin defaults to the crystal frequency
on reset.
INT
17
13
0
Interrupt. This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.
RD
14
-
I
Read. A low requests a read of the SSI 73K222l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.
RESET
25
20
I
Reset. An active high Signal on this pin will put the chip into
an inactive state. All control register bits (CRO. CR1. Tone)
will be reset. The output of the ClK pin will be set to the
crystal frequency. An internal pull down resistor permits
power on reset using a capacitor to VDD.
ALE
ADO-AD7
3-46
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
PIN DESCRIPTION
(Continued)
PARALLEL MICROPROCESSOR INTERFACE
NAME
WR
28-PIN
22-PIN
-
13
TYPE
I
(Continued)
DESCRIPTION
Write. A low on this informs the SSI73K222L that data is
available on ADO-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.
SERIAL MICROPROCESSOR INTERFACE
AO-A2
-
DATA
5-7
I
Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.
-
8
I/O
Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.
RD
-
10
I
Read. A low on this input informs the SSI 73K222L that
data or status information is being read by the processor.
The falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.
WR
-
9
I
Write. A low on this input informs the SSI73K222L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the riSing edge
ofWR.
Note:
In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the
pins; AO, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.
The serial control mode is provided in the parallel control versions by tying ALE high and CS low.
In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2,
respectively.
3-47
I
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
PIN DESCRIPTION (Continued)
DTE USER
NAME
28·PIN
22·PIN
TYPE
DESCRIPTION
EXCLK
19
15
I
External Clock. This signal is used in synchronous transmission when the external timing option has been selected.
In the external timing mode the rising edge of EXCLK is
used to strobe synchronous DPSK transmit data applied to
on the TXD pin. Also used for serial control interface.
RXCLK
23
18
0
Receive Clock. The falling edge of this clock output is
coincident with the transitions in the serial received data
output. The rising edge of RXCLK can be used to latch the
valid output data. RXCLK will be valid as long as a carrier
is present.
RXD
22
17
0
Received Data Output. Serial receive data is available on
this pin. The data is always valid on the rising edge of
RXCLK when in synchronous mode. RXD will output constant marks if no carrier is detected.
TXCLK
18
14
0
Transmit Clock. This signal is used in synchronous transmission to latch serial input data on the TXD pin. Data must
be provided so that valid data is available on the rising edge
of the TXCLK. The transmit clock is derived from different
sources depending upon the synchronization mode selection. In Internal Mode the clock is generated internally. In
External Mode TXCLK is phase locked to the EXCLK pin.
In Slave Mode TXCLK is phase locked to the RXCLK pin.
TXCLK is always active.
TXD
21
16
I
Transmit Data Input. Serial data fortransmission is applied
on this pin. In synchronous modes, the data must be valid
on the rising edge of the TXCLK clock. In asynchronous
modes (1200/600 bitls or 300 baud) no clocking is necessary. DPSK data must be 1200/600 biVs +1%, -2.5% or
+2.3%, -2.5 % in extended overspeed mode.
ANALOG INTERFACE AND OSCILLATOR
RXA
27
22
I
Received modulated analog signal input from the telephone line interface.
TXA
16
12
0
Transmit analog output to the telephone line interface.
XTL1
XTL2
2
3
3
4
I
These pins are for the internal crystal oscillator requiring
a 11.0592 MHz parallel mode crystal. Load capacitors
should be connected from XTL 1 and XTL2 to Ground.
XTL2 can also be driven from an external clock.
I
3-48
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
REGISTER DESCRIPTIONS
Four 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AD, A 1 and
A2 address lines in serial mode, or the ADO, AD1 and
AD2 lines in parallel mode. In parallel mode the address lines are latched by ALE. Register CRO controls
the method by which data is transferred over the phone
line. CR 1 controls the interface between the microprocessor and the SSI 73K222L internal state. DR is a
detect register which provides an indication of monitored modem status conditions. TR, the tone control
register, controls the DTMF generator, answer and
guard tones and RXD output gate used in the modem
initial connect sequence. All registers are read/write
except for DR which is read only. Register control and
status bits are identified below:
REGISTER BIT SUMMARY
I
CRO
CONTROL
REGISTER
CRl
001
1
DETECT
REGISTER
DR
010
TONE
CONTROL
REGISTER
TR
011
CONTROL
REGISTER
2
CR2
100
CONTROL
REGISTER
3
CR3
101
10
110
ENABLE
DETECT
INTERRUPT
BYPASS
SCRAMBLER
CLK
CONTROL
RESET
TEST
MODE
1
TEST
MODE
RECEIVE
DATA
UNSCR.
MARKS
CARRIER
DETECT
ANSWER
TONE
CALL
PROGRESS
LONG
LOOP
TRANSMIT
DTMF
DTMF3
DTMF2
10
REGISTER
NOTE:
When a register containing reseNed control
bits is written into, the reseNed bits must be
programmed as D's.
3-49
DTMF11
OVERSPEED
0
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
REGISTER ADDRESS TABLE
0=1200 BfTlS DPSK
1=600 BIT/S DPSK
O=BELL 103 FSK
1=V21 FSK
O-DISABLE
TXAOUTPUT
l=ENABLE
TXAOUTPUT
OOOO.PWR DOWN
0001.INT SYNCH
0010=EXT SYNCH
00ll=SLAVE SYNCH
0100=ASYNCH 8 BITSICHAR
01 01-ASYNCH 9 BITSICHAR
0110=ASYNCH 10 BITS/CHAR
0111 =ASYNCH 11 BITSICHAR
1100=FSK
O.DISABLE
l=ENABLE
O=NORMAL
O=XTAL
l=BYPASS
1=16 X DATA
SCRAMBLER RATE OUTPUT
ATCLK PIN IN
DPSKMODE
ONLY
O=ANSWER
1.ORIGINATE
O.NORMAL
l=RESET
0.2225 Hz A.T.
1800 Hz G.T.
1=2100 Hz A.T.
500 HzG.T.
00XX=73K212L, 322L, 321 L
01 XX=73K221L, 302L
10XX=73K222L
1100=73K224L
1110=73K324L
1101 =73K312L
3-50
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
~ONTROl
REGISTER 0
05
04
03
02
01
DO
TRANSM IT TRANSM IT TRANSM IT TRANSM IT ANSWER/
MODE 2
MODE 1
MODE 0
ENABLE ORIGINATE
DO
o
Answer/
Originate
Selects answer mode (transmit in high band, receive
in low band).
Selects originate mode (transmit in low band, receive
in high band).
01
05,04,03,
02
Transmit
Enable
Transmit
Mode
Enables transmit output at TXA.
Note: TX Enable must be set to 1 to allow AnswerTone
and OTMF Transmiission.
o
0
0
0
Internal synchronous mode. In this mode TXCLK is an
internally derived 1200 Hz signal. Serial input data
appearing at TXO must be valid on the rising edge of
TXCLK. Receive data is clocked out of RXO on the
falling edge of RXCLK.
000
001
o
0
0
External synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 1200 Hz ± 0.01 % clock must
be supplied externally.
Slave synchronous mode. Same operation as other
synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.
o
o
o
o
0
o
Selects PSK asynchronous mode - 8 bits/character
(1 start bit, 6 data bits, 1 stop bit).
Selects PSK asynchro
(1 start bit, 7 data bits, 1
o
o
06
Selects power down mode. All functions disabled
except digital interface.
mode - 9 bits/character
bit).
Selects PSK asynchronous mode - 10 bits/character
(1 start bit, 8 data bits, 1 stop bit).
Selects PSK asynchronous mode - 11 bits/character
(1 start bit, 8 data bits, Parity and 1 or 2 stop bits).
o
Not used; must be written as a "0."
3-51
I
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
CONTROL REGISTER 0
(Continued)
D5
D7
CRO
000
BIT NO.
D7
D4
D3
D2
D1
DO
TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
MODE 3
MODE 2
MODE 1
MODE 0
ENABLE ORIGINATE
MODUL.
OPTION
NAME
CONDITION
DESCRIPTION
Modulation
Option
x = Don't care
CONTROL REGISTER 1
CR1
001
D7
D6
D5
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTER.
BIT NO.
NAME
D1, DO
Test Mode
CONDITION
D4
D3
BYPASS
ClK
SCRAMB CONTROL
D2
D1
DO
RESET
TEST
MODE
1
TEST
MODE
0
DESCRIPTION
D1 DO
D2
D3
Reset
ClK Control
(Clock Control)
0
0
Selects normal operating mode.
0
1
Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced
low.
1
0
Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is ignored.
1
1
Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit carrier from
TXA pin.
0
Selects normal operation.
1
Resets modem to power down state. All control
register bits (CRO, CR1, Tone) are reset to zero. The
output of the ClK pin will be set to the crystal
frequency.
0
Selects 11.0592 MHz crystal echo output at ClK
pin.
1
Selects 16 X the data rate, output at ClK pin in DPSK
modes only.
3-52
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
CONTROL REGISTER 1 (Continued)
CR1
001
BIT NO.
D4
D5
D7
D6
D5
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTER.
D4
D3
BYPASS
ClK
SCRAMB CONTROL
D2
D1
DO
RESET
TEST
MODE
1
TEST
MODE
0
NAME
CONDITION
Bypass
Scrambler
0
Selects normal operation. DPSK data is passed
through scrambler.
1
Selects Scrambler Bypass. Bypass DPSK data is
routed around scrambler in the transmit path.
0
Disables interrupt at INT pin.
1
Enables INT output. An interrupts will be generated
with a change in status of DR bits D1-D4. The answer
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TX DTMF is activated. All interrupts will be
disabled if the device is in power down mode.
Enable Detect
DESCRIPTION
D7 D6
D7,D6
Transmit
Pattern
0
0
Selects normal data transmission as controlled by the
state of the TXD pin.
0
1
Selects an alternating mark/space transmit pattern for
modem testing.
1
0
Selects a constant mark transmit pattern.
1
1
Selects a constant space transmit pattern.
DETECT REGISTER
BIT NO.
NAME
DO
long loop
D1
Call
Progress
Detect
D5
D4
D3
D2
D1
DO
RECEIVE
DATA
UNSCR.
MARK
CARR.
DETECT
ANSWER
TONE
CAll
PROG.
lONG
lOOP
CONDITION
DESCRIPTION
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in
the 350 to 620 Hz call progress band.
3-53
I
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
DETECT REGISTER (Continued)
BIT NO.
NAME
02
Answer
Tone
Detect
05
04
03
02
01
DO
RECEIVE
DATA
UNSCR.
MARK
CARR.
DETECT
ANSWER
TONE
CALL
PROG.
LONG
LOOP
CONDITION
Indicates detection of 2225 Hz answer tone in Bell
mode or 21 00 Hz in CCITT mode. The device must be
in originate mode for detection of answer tone. For
CCITT answer tone detection, bit DO of the Tone
Register must be set to a 1.
Carrier
Detect
03
Indicates carrier has been detected in the receive
channel.
Unscrambled
Mark
Detect
04
Indicates detection of unscrambled marks in
the received data. A valid indication requires that
unscrambled marks be received for> 165.5 ± 6.5 ms.
Receive
Data
05
DESCRIPTION
Continuously outputs the received data stream. This
data is the same as that output on the RXD pin, but it
is not disabled when RXD is tri-stated.
TONE REGISTER
TR
011
07
06
RXD
OUTPUT
CONTR.
TRANSMIT
GUARD
TONE
BIT NO.
DO
NAME
DTMF 01
Answerl
Guard Tone
TRANSMIT TRANSMIT
ANSWER
DTMF
TONE
CONDITION
02
01
DO
DTMF3
DTMF2
DTMF 1/
OVERSPEED
DTMF 0/
ANSWER/
GUARD
DESCRIPTION
DO interacts with bits 06, OS, and 04 as shown.
X
X
1
X
Transmit DTMF tones.
X
0
0
0
Detects 2225 Hz in originate mode.
X
1
0
0
Transmits 2225 Hz in answer mode (Bell).
X
0
0
1
Detects 2100 Hz in originate mode.
X
1
0
1
Transmits 2100 Hz in answer mode (CCITT).
1
0
0
0
Select 1800 Hz guard tone.
0
1
Select 550 Hz guard tone.
0
D4 D1
DTMF 11
Overspeed
03
06 05 04 DO
1
01
04
05
D1 interacts with D4 as shown.
0
0
Asynchronous DPSK +1 .0% -2.5%.
0
1
Asynchronous DPSK +2.3% -2.5%.
3-54
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
TONE REGISTER
TR
011
07
06
RXD
OUTPUT
CONTR.
TRANSMIT
GUARD
TONE
BIT NO.
NAME
04
05
TRANSMIT TRANSMIT
ANSWER
DTMF
TONE
CONDITION
03
02
01
DO
DTMF3
DTMF2
DTMF 11
OVERSPEED
DTMF 01
ANSWERI
GUARD
DESCRIPTION
03 02 01 DO
03,02,
01,00
DTMF 3,
2,1,0
0
1
0
1
01
0
1
Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTM F and TX enable bit (CRO, bit
01) are set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT
04
Transmit
DTMF
Transmit
Answer
Tone
TONES
LOW HIGH
1
0
0
0
1
697
1209
2
0
0
1
0
697
1336
3
0
0
1
1
697
1477
4
0
1
0
0
770
1209
5
0
1
0
1
770
1336
6
0
1
1
0
770
1477
7
0
1
1
1
852
1209
8
1
0
0
0
852
1336
9
1
0
0
1
852
1477
0
1
0
1
0
941
1336
1209
*
1
0
1
1
941
#
1
1
0
0
941
1477
A
1
1
0
1
697
1633
B
1
1
1
0
770
1633
C
1
1
1
1
852
1633
0
0
0
0
0
941
1633
0
Disable DTMF.
1
Activates DTMF. The selected DTMF tones are
transmitted continuously when this bit is high. TX
DTMF overrides all other transmit functions.
05 04 DO
05
DTMFCODE
03 02 01 DO
05 interacts with bits 04 and DO as shown.
0
0
X
Disables answer tone generator.
1
0
0
Enables answer tone generator. A 2225 Hz answer
tone will be transmitted continuously when the Transmit Enable bit is set in CRO. The device must be in
answer mode.
1
0
1
Likewise a 2100 Hz answer tone will be transmitted.
3-55
I
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
TONE REGISTER (Continued)
TR
011
D7
D6
RXD
OUTPUT
CONTA.
TRANSMIT
GUARD
TONE
NAME
BIT NO.
D4
CONDITION
D3
DTMF3
D1
DO
DTMF2
DTMF 11
OVERSPEED
DTMF 01
ANSWERI
GUARD
DESCRIPTION
0
Disables guard tone generator.
1
Enables guard tone generator (See DO for selection
of guard tones).
RXD Output
Control
0
Enables RXD pin. Receive data will be output on
RXD.
1
Disables RXD pin. The RXD pin reverts to a high
impedance with internal weak pull-up resistor.
10 REGISTER
ID
D2
Transmit
Guard Tone
D6
D7
D5
TRANSMIT TRANSMIT
ANSWER
DTMF
TONE
D7
D6
D5
D4
ID
ID
ID
ID
110
SIT NO.
NAME
D7,D6
Device
CONDITION
D7 D6 D5 D4
DESCRIPTION
Indicates Device:
Identification
Signature
3-56
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
VDD Supply Voltage
14V
Storage Temperature
-65 to 150°C
Soldering Temperature (10 sec.)
260°C
Applied Voltage
-0.3 to VDD+0.3V
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
NOM
MAX
UNITS
VDD Supply voltage
4.5
5
5.5
V
TA, Operating Free-Air
Temperature
-40
+85
°c
-0.01
+0.01
%
Clock Variation
CONDITIONS
(11.0592 MHz) Crystal or
external clock
External Components (Refer to Application section for placement.)
VREF Bypass Capacitor
(External to GND)
0.1
Bias setting resistor
(Placed between VDD
and ISET pins)
1.8
J.lF
2
2.2
MQ
ISET Bypass Capacitor
(ISET pin to GND)
0.1
J.lF
VDD Bypass Capacitor 1
(External to GND)
0.1
J.lF
VDD Bypass Capacitor 2
(External to GND)
22
XTL 1 Load Capacitor
Depends on crystal characteristics;
40
XTL2 Load Capacitor
from pin to GND
20
3-57
J.lF
QF
•
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chi,p Modem
ELECTRICAL SPECIFICATIONS (Continued)
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)
PARAMETER
100, Supply Current
MIN
CONDITIONS
ISET Resistor
NOM
MAX
UNITS
8
12
rnA
4
rnA
3
rnA
= 2 Mil
IDDA, Active
CLK = 11.0592 MHz
1001, Power-down
ClK = 11.0592 MHz
1002, Power-down
ClK
= 19.200 KHz
Digital Inputs
VIH Input High Voltage
Reset, XTL1 , XTl2
3.0
VDD
V
All other inputs
2.0
VDD
V
0
0.8
V
100
llA
Vll, Input Low Voltage
IIH, Input High Current
VI = VIH Max
ilL, Input low Current
VI
Reset Pull-down Current
= Vil Min
Reset = VDD
Input Capacitance
All Digital Input Pins
~
-200
1
50
J.IA
10
pF
Digital Outputs
VOH, Output High Voltage
10H MIN = -0.4 rnA
VOL, Output Low Voltage
10 MAX = 1.6 rnA
VOL, ClK Output
10 = 3.6 rnA
RXD Tri-State Pull-up Curro
RXD=GND
CMAX, ClK Output
Maximum Capacitive load
2.4
-1
3-58
VDD
V
0.4
V
0.6
V
-50
J.IA
15
pF
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
ELECTRICAL SPECIFICATIONS
(Continued)
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
-10.0
-9
dBmO
+.35
%
PSK Modulator
Carrier Suppression
Measured at TXA
55
Output Amplitude
TX scrambled marks
-11
dB
FSK Mod/Demod
Output Freq. Error
ClK
= 11.0592 MHz
-0.35
Transmit level
Transmit Dotting Pattern
-11
-10.0
-9
dBmO
Harmonic Distortion
in 700-2900 Hz band
TH 0 in the alternate band
DPSK or FSK
-60
-50
dB
Output Bias Distortion
Transmit Dotting Pattern
in AlB@ RXD
±8
Total Output Jitter
Random Input in ALB @ RXD
-15
%
+15
%
DTMF Generator
Freq. Accuracy
-.25
Output Amplitude
low Band, DPSK Mode
-10
Output Amplitude
High Band, DPSK Mode
-8
Twist
High-Sand to Low-Band, DPSK Mode
1.0
long Loop Detect
DPSK or FSK
-38
Dynamic Range
Refer to Performance Curves
+.25
%
-8
dBmO
-7
-6
dBmO
2.0
3.0
dB
-28
dBmO
-9
dB
45
Call Progress Detector
Detect level
2-Tones in 350-600 Hz band
-34
0
dBmO
Reject level
2-Tones in 350-600 Hz band
-41
dBmO
Delay Time
-70 dBmO to -30 dBmO STEP
27
80
ms
Hold Time
-30 dBmO to -70 dBmO STEP
27
80
ms
Hysteresis
Note:
2
Parameters expressed in dBmO refer to the following definition:
odB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
3-59
dB
I
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
CONDITIONS
Carrier Detect
DPSK or FSK
MIN
NOM
MAX
UNITS
Threshold
receive data
-49
-42
dBmO
Delay Time
-70 dBmO to -30 dBmO STEP
15
45
ms
Hysteresis
Single tone detected
2
Hold Time
-30 dBmO to -70 dBmO STEP
10
24
ms
-49.5
-42
dBmO
20
45
ms
10
30
ms
-2.5
+2.5
%
dB
3.0
Answer Tone Detector
Detect Level
Not in V.21 mode
Delay Time
-70 dBmO to -30 dBmO STEP
Hold Time
-30 dBmO to -70 dBmO STEP
Detect Freq. Range
Output Smoothing Filter
Output load
Spurious Freq. Compo
TXA pin; FSK Single
Tone out for THO = -50 db
in .3 to 3.4 KHz
50
pF
Frequency = 76.8 kHz
-39
dBmO
Frequency = 153.6 kHz
-45
dBmO
300
Q
1.0
mVrms
TXA pin Output Impedance
Clock Noise
kQ
10
200
TXA pin; 76.8 KHz
Carrier VCO
Capture Range
Originate or Answer
Capture Time
-10Hz to +10 Hz Carrier
Freq. Change Assum.
-10
40
+10
Hz
100
ms
+625
ppm
50
ms
Recovered Clock
Capture Range
% of frequency
center frequency
(center at 1200 Hz)
Data Delay Time
Analog data in at RXA pin to
receive data valid at RXD pin
3-60
-625
30
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
ELECTRICAL SPECIFICATIONS (Continued)
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
Guard Tone Generator
Tone Accuracy
550 Hz
1800 Hz
-20
+20
Hz
Tone Level
550 Hz
-4.0
-3.0
-2.0
dB
(Below DPSK Output)
1800 Hz
-7.0
-6.0
-5.0
dB
Harmonic Distortion
550 Hz
-50
dB
700 to 2900 Hz
1800 Hz
-60
dB
Timing (Refer to Timing Diagrams)
.
TAL
CSI Addr. setup before ALE Low
30
ns
TLA
CS/Addr. hold after ALE Low
20
ns
TLC
ALE Low to RD/WR Low
40
ns
TCL
RD/WR Control to ALE High
10
TRD
Data out from RD Low
0
TLL
ALE width
60
TRDF
Data float after RD High
ns
140
ns
0
200
ns
ns
TRW
RD width
200
25000
ns
TWW
WR width
140
25000
ns
TDW
Data setup before WR High
150
20
ns
TWD
Data hold after WR High
TCKD
Data out after EXCLK Low
TCKW
WR after EXCLK Low
150
ns
TDCK
Data setup before EXCLK Low
150
ns
TAC
Address setup before control*
50
ns
TCA
Address hold after control*
50
ns
TWH
Data Hold after EXCLK
20
Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.
3-61
ns
200
ns
I
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
ALE
~
~
~
TLC
RD
.L
TRW
-k-
.L
TCl
+
TlC
TLA
L
ADO-AD7
cs
1
TWW
J
I~
~ ~ ·~I
-+
WR
--K
--=t-
TAL
'J
TRD
!.I
TRDF
i!.I
ITWD
TOW
ADDRESS >i----K READ DATA>i----K ADDRESS >i----KWRITE DAT*-
-i-
-~-
-~-
READ TIMING DIAGRAM (SERIAL VERSION)
EXClK
AO-A2
DATA
--+
WRITE TIMING DIAGRAM (SERIAL VERSION)
EXCLK
AO-A2 - - - + - - - - - - - - - - - - - - - - - - - - - \ + ,
DATA
3-62
SSI73K222L
V.22, V.21 , Bell 212A
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
ClK
GND
RXA
ClK
VREF
XTL1
RESET
XTL2
ISET
GND
XTL1
RXA
XTL2
VREF
ADO
RESET
AD1
ISET
AD2
RXCLK
AD3
RXD
TXD
4
3
2
1 28 27 26
AO
RXClK
AD4
A1
RXD
AD5
A2.
cs
TXD
AD6
EXClK
EXClK
AD7
TXClK
TXClK
ALE
INT
10
20
INT
WR
TXA
11
19
TXA
RD
VDD
RD
VDD
400-Mil
22-Pin DIP
600-Mil
28-Pin DIP
25
24
PLCC PINOUTS
ARE THE SAME AS
THE 28-PIN DIP
23
22
21
12 13 14 15 16 17 18
28-Pin
PLCC
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
SSI 73K222L with Parallel Bus Interface
28-Pin Dip
28-Pin PLCC
73K222L-IP
73K222L-IH
73K222L-IP
73K222L-IH
SSI 73K222L with Serial Interface
22-Pin Sip
73K222SL-IP
73K222SL-IC
73K222SL-IP
73K222SL-IC
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
0194 - rev.
3-63
Protected by the following Patents (4,691,172) (4,777,453)
©1989 Silicon Systems, Inc.
I
Notes:
3-64
SSI73K222U
Single-Chip Modem
with UART
December 1993
DESCRIPTION
FEATURES
The SSI 73K222U is a compact, high-performance
modem which includes a 8250Al16C450 compatible
UART with the 1200 bitls modem function on a single
chip. Based on the SSI 73K222L 5V low power CMOS
modem IC, the SSI 73K222U is the perfect modem/
UART component for integral modem applications. It is
ideal for applications such as portable terminals and
laptop computers. The SSI 73K222U is the first fully
featured modem IC which can function as an intelligent
modem in integral applications without requiring a
separate dedicated microcontroller. It provides for data
communication at 1200, 600, and 300 bitls in a multimode manner that allows operation compatible with
both Bell 212A1103 and CCITT V.22/v.21 standards.
The digital interface section contains a high speed
version of the industrystandard 8250Al16C450 UART,
commonly used in personal computer products. A
unique feature of the SSI 73K222U is that the UART
section can be used without the modem function,
providing an additional asynchronous port at no added
cost. The SSI 73K222U is designed in CMOS technology and operates from a single +5V supply. Available
packaging includes 40-pin DIP or 44-pin PLCC for
surface mount applications.
• Modem/UART combination optimized for integral bus
applications
• Includes features of SSI73K222L single-chip modem
• Fully compatible 16C450/8250 UART with 8250B or
8250A selectable interrupt emulation
• High speed UARTwill interface directly with high clock
rate bus with no wait states
• Single-port mode allows full modem and UARTcontrol
from CPU bus, with no dedicated microprocessor
required
• Dual-port mode suits conventional designs using local microprocessor for transparent modem operation
• Complete modem functions for 1200 bitls (Bell 212A,
V.22) and 0-300 bitls (Bell 103, V.21)
• Includes DTMF generator, carrier, call-progress and
precise answer-tone detectors for intelligent dialing
capability
• On chip 2-wire/4-wire hybrid driver and off-hook relay
buffer
• Speaker output with four-level software driven volume
control
• Low power CMOS (40 mW) with power down mode
(15 mW)
• Operates from single +5V supply
BLOCK DIAGRAM
TXD
XTL1
XTl2
PIN DIAGRAM
ClK
TXAI
UDO
UDI
TXA2
UD2
RXA
UD3
SPKR
UD4
(CTS)/MAO
UD5
UD6
UD7
(MR)/MAI
8250A I 16C450
UART
(UA3)/MA2
UAO
DATA/(DTR)
UAI
AD/(ADS)
UA2
WR/(N/C)
(DCD)/DClK
DOSTR
(RTS)/TNf
DISTR
OH
CS2
RELAY
DRIVER
INTRPT
1293 - rev.
(RI) ;U'RST
RESET
RXD
VDD VREF GND
Parentheses indicate single-port mode.
ISET STNDlN
3-65
CAUTION:
Use handling procedures necessary
for a static sensitive component.
3
SSI73K222U
Single-Chip Modem
with UART
FUNCTIONAL DESCRIPTION
interrupt operation. The UART used in the
8S1 73K222U can be used with faster bus read and
write cycles than a conventional 16C450 UART. This
allows it to interface directly with higher clock rate
microprocessors with no need for external circuitry to
generate wait states.
The 881 73K222U integrates an industry standard
8250/16C450 UART function with the modem capability provided by the 881 73K222l single chip modem IC.
The SSI 73K222U is designed specifically for integral
microprocessor bus intelligent modem products. These
designs typically require the standard 8250 or higher
speed 16450 UART to perform parallel-to-serial and
serial-to-parallel conversion process necessary to interface a parallel bus with the inherently serial modem
function. The 8S1 73K222U provides a highly integrated design which can eliminate multiple components in any integral bus modem application, and is
ideal for internal PC modem applications.
The primary function of the UART is to perform parallelto-serial conversion on data received from the CPU
and serial-to-parallel conversion on data received from
the internal modem or an external device. The UART
can program the numberof bits per character, parity bit
generation and checking, and the number of stop bits.
The UART also provides break generation and detection, detection of error conditions, and reporting of
status at any time. A prioritized maskable interrupt is
also provided.
The 881 73K222U includes two possible operating
modes. In the dual-port mode, the device is suitable for
conventional plug-in modem card designs which use a
separate local microprocessor for command interpretation and control of the modem function. In this mode,
a dedicated microcontroller communicates with the
SSI 73K222U using a separate serial command port.
In the Single-port mode the main CPU can control both
the UART and modem function using the parallel data
bus.This allows very efficient modem design with no
local microprocessor required for dedicated applications such as laptop PC's or specialized terminals.
The UART block has a progammable baud rate generator which divides an internal 1.8432 MHz clock to
generate a clock at 16 x the data rate. The data rate for
the transmit and receive sections must be the same.
For DP8K modulation, the data rate must be 1200 Hz
or 600 Hz. For F8K modulation, the data rate must be
300 Hz or less. The baud generator can create a clock
that supports digital transfer at up to 115.2 kHz. The
output of the baud generator can be made available at
the ClK pin under program control.
MODEM FUNCTION (SSI 73K222l)
To make designs more space efficient, the
8S1 73K222U includes the 2-wire to 4-wire hybrid
drivers, off-hook relay driver, and an audio monitor
output with software volume control for audible call
progress monitoring. As an added feature the UART
function can be used independent of the modem function, providing an added asynchronous port in a typical
PC application with no additional circuitry required.
The modem section of the 8S1 73K222U provides all
necessary analog functions required to create a single
Chip Bell 212N103 and CCITT V.22N.21 modem,
controlled by the system CPU or a local dedicated
microprocessor. Asynchronous 1200 bitls DP8K (Bell
212A and V.22) and 300 baud FSK (Bell 103 and V.21)
modes are supported.
The modem portion acts as a peripheral to the microprocessor. In both modes of operation, control information is stored in register memory at specific address
locations. Inthe single-port mode, the modem section
can be controlled through the 16C450 interface, with
no external microcontroller required. The primary analog blocks are the DPSK modulator/demodulator, the
FSK modulator/demodulator, the high and low band
filters, the AGC, the special detect circuitry, and the
DTMF tone generator. The analog functions are performed with switched capaCitor technology.
UART FUNCTION (16C450)
The UART section of the S81 73K222U is completely
compatible with the industry standard 16C450 and the
8250 UART devices. The bus interface is identical to
the 16450, except that only a single polarity for the
control signals is supported. The register contents and
addresses are also the same as the 16C450. To insure
compatibility with all existing releases of the 8250
UART deSign, external circuitry normally used in PC
applications to emulate 8250B or 8250A interrupt operation has been included on the 881 73K222U.
A select line is then provided to enable the desired
3-66
SSI73K222U
Single-Chip Modem
with UART
PSK MODULATOR / DEMODULATOR
SPECIAL DETECT CIRCUITRY
The SSI 73K222U modulates a serial bit stream into
dibit pairs that are represented by four possible phase
shifts as prescribed by tne Bell 212A or V.22 standard.
The baseband signal is then filtered to reduce intersymbol interference on the band limited 2-wire PSTN
line. Transmission occurs using either a 1200 Hz
(originate mode) or 2400 Hz carrier (answer mode).
Demodulation is the reverse of the modulation process, with the incoming analog signal eventually decoded into dibits and converted back to a serial bit
stream. The demodulator also recovers the clock which
was encoded into the analog signal during modulation.
The demodulator decodes either a 1200 Hz carrier
(originate carrier) or a 2400 Hz carrier (answer carrier).
The SSI73K222U uses a phase-locked-loop coherent
demodulation technique that offers inherently better
performance than typical DPSK demodulators used by
other manufacturers.
The special detect circuitry monitors the received analog signal to determine status or presence of carrier,
call-progress tones, answer tone, and weak received
signal (long loop condition). An unscrambled mark
signal is also detected when the received data out of
the DPSK demodulator before the descrambler has
been high for 165.5 mS ±13.5 mS. The appropriate
status bit is set when one of these conditions changes
and an interrupt is generated for all monitored conditions except long loop. The interrupts are disabled
(masked) when the enable interrupt bit is set to a O.
FSK MODULATOR/DEMODULATOR
The FSK modulator frequency modulates the analog
output signal using two discrete frequencies to represent the binary data. In Bell 1 03, the standard frequencies of 1270 Hz and 1070 Hz (originate mark and
space) and 2225Hz and 2025 Hz (answer mark and
space) are used. V.21 mode uses 980 Hz and 1180 Hz
(originate, mark and space) or 1650 Hz and 1850 Hz
(answer, mark and space). Demodulation involves
detecting the received frequencies and decoding them
into the appropriate binary value.
DTMF GENERATOR
The DTMF generator will output one of 16 standard
dual-tones determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode
is selected and the transmit enable (CRO bit 01) is
changed from a 0 to a 1.
TEST FEATURES
Test features such as analog loopback (ALB), remote
digital loopback, local digital loopback, and internal
pattern generators are also included.
LINE INTERFACE
The line interface of the SSI73K222U consists of atwoto-four wire hybrid, and an off-hook relay driver.
The two-to-four wire converter has a differential transmit output and requires only a line transformer and an
external impedance matching resistor. Four-wire
operation is also available by simply using either of the
transmit output signals.
PASSBAND FILTERS AND EQUALIZERS
A high and low band filter is included to shape the
amplitude and phase response of the transmit signal
and provide compromise delay equalization and rejection of out-of-band signals in the receive channel.
Amplitude and phase equalization is necessary to
compensate for distortion of the transmission line and
to reduce intersymbol interference in the band limited
receive signal. The transmit signal filtering approximates a 75% square root of raised Cosine frequency
response characteristic.
The relay driver output of the SSI 73K222U is an open
drain signal capable of sinking 20 mA, which can
control a line closure relay used to take the line off hook
and to perform pulse dialing.
AUDIO MONITOR
An audio monitor output is provided which has a
software programmable volume control. Its output is
the received signal. The audio monitor output can
directly drive a high impedance load, but an external
power amplifier is necessary to drive a low-impedance
AGC
The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping, and provides a total
dynamic range of >45 dB.
3-67
•
SSI73K222U
Single-Chip Modem
with UART
PIN DESCRIPTION
GENERAL
NAME
DIP
PLCC
TYPE
VDD
40
44
I
DESCRIPTION
+5V Supply ±1 0%, bypass with a .1 and a 22~F capacitor
to GND
GND
20
22
I
System Ground
VREF
19
21
0
VREF is an internally generated reference voltage which is
externally bypassed by a 0.1~F capacitor to the system
ground.
ISET
9
11
I
The analog current is set by connecting this pin to VDD
through a 2 Mil resistor. ISET should be bypassed to GND.
Alternatively, an internal bias can be selected by connecting ISET to GND, which will result in a larger worst-case
supply current due to the tolerance of on-chip resistors.
Bypass with .1 ~F capacitor if resistor is used.
XTL1
25
27
I
XTl2
24
26
I
These pins are connections for the internal crystal
oscillator requiring an 11.0592 MHz crystal (9216Hz x
1200). XTl2 can also be TTL driven from an external clock.
ClK
21
23
0
Output Clock. This pin is selectable under processor control to be either the crystal frequency (which might be used
as a processor clock) or the output of the baud generator.
RESET
10
12
I
Reset. An active signal (high) on this pin will put the Chip into
an inactive state. The control register bits (except the
Receiver Buffer, Transmitter Holding, and Divisor latches)
will be reset. The output of the ClK pin will be set to the
crystal frequency. An internal pull-down resistor permits
power-on reset using a 0.1 ~F capaCitor connected to the
5V supply.
STNDlN
15
17
I
Single-port mode select (active high). In a Single-port
system there is no local microprocessor and all the modem
control is done through the 16C450 parallel bus interface.
The local microprocessor interface is replaced with UART
control signals which allow the device to function as a digital
UART as well as modem.
3-68
SSI73K222U
Single-Chip Modem
with UART
PIN DESCRIPTION (continued)
UART INTERFACE
NAME
DIP
PLCC
TYPE
UAO-UA2
UA3
37-39
12
41-43
14
I
I
UART Address. These pins determine which of the UART
registers is being selected during a read or write on the
UART data bus. The contents of the DLAB bit in the
UART's Line Control Register also control which register is
referenced. In single-port mode, UAO-UA3 are latched
when ADS goes high. In dual-port, only UAO-UA2 are
used.
UDO-UD7
27-34
30-37
I/O
(3 state) UART Data. Data or control information to the
UART registers is carried over these lines.
DISTR
35
38
I
Data Input Strobe. A low on this pin requests a read of the
internal UART registers. Data is output on the 00-07 lines
if DISTR and CS2 are active.
DOSTR
36
39
I
Data Output Strobe. A low on this pin requests a write of the
internal UART registers. Data on the 00-07 lines are
latched on the rising edge of DOSTR. Data is only written
if both DOSTR and CS2 are active.
CS2
1
2
I
Chip Select. A low on this pin allows a read orwrite to the
UARTregisterstooccur. In single port mode,CS2 is latched
on ADS.
INTRPT
5
7
0
(3 state) UART Interrupt. This signal indicates that an
interrupt condition on the UART side has occurred. If the
Enable 8250A interrupt bit in the interrupt Enable Register
is 0 the interrupt is gated by the DISTR signal to provide
compatibility with the 8250B. The output can be put in a high
impedance state with the OUT2 register bit in the Modem
Control Register. In single-port mode, INTRPT also becomes valid when a modem interrupt signal is ge nerated by
the modem section's Detect Register.
RXD
6
8
I/O
Function is determined by STNDLN pin and bit 7, Tone
Control Register:
DESCRIPTION
STNDLN
07
0
0
RXD outputs data received by modem.
1
0
RXD is electrically an input but signal is
ignored.
X
1
RXD is a serial input to UART.
3-69
•
SSI73K222U
Single-Chip Modem
with UART
PIN DESCRIPTION (continued)
UART INTERFACE (continued)
TXO
7
9
0
Function is determined by STNOLN pin and bit 7, Tone
Control Register:
STNOLN
07
0
0
1
0
TXO is forced to a mark.
X
1
TXO is a serial output of UART.
TXO is a serial output of UART.
ANALOG / LINE INTERFACE
NAME
DIP
PLCC
TYPE
DESCRIPTION
TXA1
TXA2
3
4
4
5
0
0
(differential) Transmitted Analog. These pins provide the
analog output signals to be transmitted to the phone line.
The drivers will differentially drive the impedance of the line
transformer and the line matching resistor. An external
hybrid can also be built using TXA1 as a single ended
transmit signal.
RXA
16
18
I
Received Analog. This pin inputs analog information that is
being received by the two-to-four wire hybrid. This input
can also be taken directly from an external hybrid.
SPKR
17
19
0
Speaker Output. This pin outputs the received signal through
a programmable attenuator stage, which can be used for
volume control and disabling the speaker.
OH
18
20
0
Off-hook relay driver. This signal is an open drain output
capable of sinking 20mA and is used for controlling a relay.
The output is the complement of the OH register bit in CR3.
3-70
SSI73K222U
Single-Chip Modem
with UART
PIN DESCRIPTION (continued)
UART CONTROL INTERFACE (STNDLN
(See Figure 1: Single-port mode)
=1)
NAME
DIP
PLCC
TYPE
ADS
23
25
I
Address Strobe. ADS is used to latch address and chip
select to simplify interfacing to a multiplexed Address/Data
Bus. UAO-UA3 and CS2 are latched when the ADS signal
goes high.
UA3
12
14
I
UART Address Bit 3. UA3 is used in single-port mode to
address the modem registers from the 16C450 interface.
If UA3 is 0, the normal 16C450 registers are addressed by
UAO-UA2 and if UA3 is 1, the modem registers are addressed. UA3 is latched when ADS goes high.
DESCRIPTION
CTS
14
16
I
Clearto Send. This pin is the complement of CTS bit in the
Modem Status Register. The signal is used in modem
handshake control to signify that communications have
been established and that data can be transmitted.
DSR
13
15
I
Data Set ReadyThis pin is the complement of DSR bit in
the Modem Status RegisterThe signal is used in modem
handshake to signify that the modem is ready to establish
commu nications.
DCD
11
13
I
Data Carrier Detect. This pin is the complement of DCD bit
in the Modem Status Register. The signal is used in modem
control handshake to signify that the modem is receiving a
carrier.
DTR
22
24
0
Data Terminal Ready.The DTR output is programmed
through a bit in the Modem Control Register. The signal is
used in modem handshake to signify that the 16C450 is
available to communicate.
RTS
2
3
0
Request to Send. The RTS output is programmed through
a bit in the Modem Control Register. The signal is used in
modem handshake to signify that the 16C450 has data to
transmit.
RI
8
10
I
Ring Indicator. This Indicates that a telephone ringing
signal is being received. This pin is the complement of the
RI bit in the Modem Status Register.
3-71
I
SSI73K222U
Single-Chip Modem
with UART
PIN DESCRIPTION (continued)
MICROPROCESSOR INTERFACE (STNDLN
(See Figure 2: Dual-port mode)
NAME
=0)
DIP
PLCC
TYPE
12-14
14-16
I
Modem Address Control. These lines carry register
addresses for the modem registers and should be valid
throughout any read or write operation.
DATA
22
24
I/O
Serial Control Data. Serial control data to be read/written is
clocked in/out on the falling edge of the DCLK pin. The
direction of data transfer is controlled by the state of the RD
pin. If the RD pin is active (low) the DATA line is an output.
Conversely, if the RD pin is inactive (high) the DATA line is
an input.
RD
23
25
I
Read. A low on this input informs the SSI 73K222U that
control data or status information is being read by the
processor from a modem register.
WR
26
28
I
Write. A low on this input informs the SSI 73K222U that
control data or status information is available for writing into
a modem register. The procedure for writing is to shift in
data LSB first on the DATA pin for eight consecutive cycles
of DCLK and then to pulse WR low. Data is written on the
rising edge of WR.
DCLK
11
13
I
Data Clock. The falling edge of this clock is used to strobe
control data for the modem registers in or out on the DATA
pin. The normal procedure for a write is to shift in data LSB
first on the DATA pin for eight consecutive cycles of DCLK
and then to pulse WR low. Data is written on the rising edge
of WR. The falling edge of the RD signal must continue for
eight cycles of DCL~ in order to read all eight bits of the
reference register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.
INT
2
3
0
(with weak pull-up) Modem Interrupt. This output signal is
used to inform the modem processor that a change in a
modem detect flag has occurred. The processor must then
read the Modem Detect Registerto determine which detect
triggered the interrupt. INTwili stay active until the processor reads the Modem Detect Register or does a full reset.
JlPRST*
8
10
0
Microprocessor Reset. This output signal is used to provide a hardware reset to the microprocessor. This signal is
high if the RESET pin is high or the MCR bit 03 (OUT1) bit
is set.
MAO-MA2
DESCRIPTION
* NOTE: The JlPRST pin is an upgraded function which was not included in the initial definition of the
SSI 73K222U.
3-72
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FIGURE 1:
Single-Port Mode
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In the single-port mode, the SSI 73K222U is designed to be
accessed only by the main CPU using the same parallel bus utilized
for data transfer. This mode is enabled when the STNDLN pin is at
a logic "1". In the single port mode, internal registers are accessed
by the main CPU to configure both the UART section and the
modem function, eliminating the need for a separate microcontroller. In this mode, multiplexed pins provide the CTS, DSR, DTR,
OED and RI signals normally associated with the UARTfunction. A
separate pin, ADS, is used for bus control.
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FIGURE 2:
Dual-Port Mode
The dual-port mode allows use of a dedicated microprocessor for
control of the modem function, and is enabled when the STNDLN
pin = "0". This mode is useful for conventional plug-in card modem
designs where it is necessary to make the modem function transparent to the main CPU. In this mode, the SSI 73K222U's multiplexed pins form the serial command bus used to communicate with
the external microprocessor. The AT, CTS, DSR, DTR, and DCD
logic functions must then be implemented using ports from the
dedicated microprocessor.
The serial control interface allows access to the control and status
registers via a serial command port. In this mode the MAO, MA1,
and MA2 lines provide register addresses for data passed through
the DATA pin under control of the RD and WR lines. A read operation is initiated when the RD line is taken low. The next eight
cycles of DCLK will then transfer out eight bits of the selected
address location LSB first. A write takes place by shifting in eight
bits of data LSB first for eight consecutive cycles of DCLK. WR is
then pulsed low and data transfer into the selected register occurs
on the rising edge of WR.
SSI73K222U
Single-Chip Modem
with UART
UART CONTROL REGISTER OVERVIEW
DATA BIT NUMBER
UART
ADDRESS
UA3·UAO·
REGISTER
D7
D6
D5
D4
D3
D2
Dl
DO
RECEIVER
BUFFER
REGISTER
I (READ ONLY)
RBR
0000
DLAB=
a
BIT7
(MSB)
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BITO
(LSB)
TRANSMIT
HOLDING
REGISTER
l(WRITE ONL'r')
THR
0000
DLAB- 0
BIT7
(MSB)
BIT6
BIT 5
BIT4
BIT3
BIT2
BIT 1
BITO
(LSB)
INTERRUPT
ENABLE
REGISTER
ENABLE
IER
0001
DLAB= 0
a
a
0
ENABLE
MODEM
STATUS
INTERRUPT
ENABLE
REC. LINE
STATUS
INTERRUPT
ENABLE
THR
EMPTY
INTERRUPT
ENABLE
REC. DATA
AVAILABLE
INTERRUPT
INTERRUPT
ID
BITO
·0" IF
INTERRUPT
PENDING
8250N
16C450
INTERRUPT
INTERRUPT
ID
REGISTER
(READ ONLY)
IIR
0010
a
0
0
0
0
INTERRUPT
ID
BITl
LINE
CONTROL
REGISTER
LCR
0011
DIVISOR
LATCH
ACCESS
(DLAB)
SET
BREAK
STICK
PARITY
EVEN
PARITY
SELECT
(EPS)
PARITY
ENABLE
(PEN)
NUMBER
OF STOP
BITS
(STB)
WORD
LENGTH
SELECT 1
(WLS1)
WORD
LENGTH
SELECT 0
jWLSO)
MODEM
CONTROL
REGISTER
MCR
0100
0
0
0
LOOP
ENABLE
INTERRUPT
(OUT2
IN 16C450)
I1 PRST
(OUTlIN
16C450)
REQUEST
TO SEND
(RTS)
DATA
TERMINAL
READY
(DTR)
LINE
STATUS
REGISTER
LSR
0101
0
TRANSMIT
SHIFT REG.
EMPTY
(TSRE)
TRANSMIT
HOLDING
REGISTER
EMPTY(THRE)
BREAK
INTERRUPT
(BI)
FRAMING
ERROR
(FE)
PARITY
ERROR
(PE)
OVERRUN
ERROR
(OE)
DATA
READY
(DR)
MODEM
STATUS
REGISTER
(READ ONLY)
MSR
0110
DATA
CARRIER
DETECT
(DCD)
RING
INDICATOR
(RI)
DATA
SET READY
(DSR)
CLEAR
TO SEND
(CTS)
DELTA
DATA CARR.
DETECT
(DDCD)
TRAILING
EDGE RING
INDICATOR
(TERI)
DELTA
DATASET
READY
(DDSR)
DELTA
CLEAR
TO SEND
(DCTS)
SCRATCH
REGISTER
SCR
0111
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BITO
DIVISOR
LATCH
(LS)
DLL
0000
DLAB= 1
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BITO
DIVISOR
LATCH
(MS)
DLM
0001
DLAB= 1
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT10
BIT9
BIT8
• In single-port mode (STNDLN pin = 1), all four address lines UA3-UAO are used to address the UART Control Registers.
• In dual-port mode (STNDLN pin = 0), only three address lines UA2-UAO are used to address the UART Control Registers;
the UA3 pin becomes the MA2 pin in this mode.
3-75
I
SSI73K222U
Single-Chip Modem
with UART
MODEM CONTROL REGISTER OVERVIEW
ADDRESS
STNDLN
1
0
REGISTER
MA2MAO
UA3UAO
DATA BIT NUMBER
07
os
05
04
03
02
01
DO
CONTROL
REGISTER
0
CRO
000
1000
MODULATION
OPTION
0
MODULATION
MODE
POWER
ON
CHARACTER
SIZE 1
(READ ONLY)
CHARACTER
SIZE 0
(READ ONLY)
TRANSMIT
ENABLE
ORIGINATE!
ANSWER
CONTROL
REGISTER
1
CRl
001
1001
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTERRUPT
BYPASS
SCRAMBLER
CLK
CONTROL
RESET
TEST
MODE
1
TEST
MODE
0
DETECT
REGISTER
DR
010
1010
DEVICE
SIGNATURE
1
DEVICE
SIGNATURE
0
RECEIVE
DATA
UNSCR.
MARK
DETECT
CARRIER
DETECT
ANSWER
TONE
DETECT
CALL
PROGRESS
DETECT
LONG
LOOP
DETECT
TONE
CONTROL
REGISTER
TONE
011
1011
RXDfTXD
CONTROL
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF
3
DTMF
2
DTMF
1
DTMFO
GUARDIANS.
TONE
CONTROL
REGISTER
2
CR2
100
1100
CONTROL
REGISTER
3
CR3
101
1101
SPEAKER
VOLUME
1
SPEAKER
VOLUME
0
OFF-HOOK
X
X
X
X
X
SCRATCH
REGISTER
SCR
110
1110
BIT 7
BITS
BITS
BIT4
BIT3
BIT2
BIT 1
BITO
UART
CONTROL
REGISTER
UCR
111
1111
TXCLK
(READ ONLY)
X
RING
INDICATOR
(RI)
DATA
CARRIER
DETECT (DCD)
DATA
SET
READY
(DSR)
CLEAR
TO
SEND
(CTS)
RESERVED FOR FUTURE USE
REQUEST
DATA
TO SEND
TERM. READY
(RTS)
(DTR)
(READ ONLY) (READ ONLY)
3-76
SSI73K222U
Single-Chip Modem
with UART
UART REGISTER BIT DESCRIPTIONS
UART SECTION
RECEIVER BUFFER REGISTER (RBR) (READ ONLY)
STNDLN:
0
ADDRESS:
UA2 - UAO 000, DLAB = 0
=
1
UA3 - UAO
=0000, DLAB =0
This read only register contains the parallel received data with start, stop, and parity bits (if any) removed. The
high order bits for less than 8 data bits/character will be set to O.
TRANSMIT HOLDING REGISTER (THR) (WRITE ONLY)
STNDLN:
0
ADDRESS:
UA2 - UAO 000, DLAB = 0
UA3 - UAO
=
1
=0000, DLAB =0
This write only register contains the parallel data to be transmitted. The data is sent LSB first with start, stop,
and parity bits (if any) added to the serial bit stream as the data is transferred.
INTERRUPT ENABLE REGISTER (IER)
STNDLN:
0
ADDRESS:
UA2 - UAO 001, DLAB
=
1
=0
UA3 - UAO
=0001, DLAB = 0
This 8-bit register enables the four types of interrupts of the UART to separately activate the chip Interrupt
(INTRPT) output signal. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of the
Interrupt Enable Register. Similarly, by setting the appropriate bits of this register to a logic 1, selected
interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and the
active (high) INTRPT output from the chip. All other system functions operate in their normal manner, including
the setting of the Line Status and Modem Status Registers.
NAME
CONDITION
DO
Received Data
1
This bit enables the Received DataAvailable Interrupt when set to logic 1.
D1
Transmitter Holding
Register Empty
1
This bit enables the Transmitter Holding Register
Empty Interrupt, when set to logic 1.
D2
Receiver Line
Status Interrupt
1
This bit enables the Receiver Line Status Interrupt,
when set to logic 1.
D3
Modem Status
1
This bit enables the Modem Status Register Interrupt when set to interrupt logic 1.
D4
8250N16450
1/0
Set for compatibility with 8250Al16C450 UARTS.
Reset this bit to disable the gating of the INTRPT
interrupt line with the DISTR signal which is
needed for 8250B compatibility.
Not Used
0
BIT NO.
D5 - D7
DESCRIPTION
These three bits are always logic O.
3-77
I
SSI73K222U
Single-Chip Modem
with UART
INTERRUPT 10 REGISTER (ItR) (READ ONLY)
STNDLN:
0
1
ADDRESS:
UA2· UAO = 010
UA3· UAO = 0010
UART SECTION
The IIR register gives prioritized information as to the status of interrupt conditions. When accessed, the IIR
freezes the highest priority interrupt pending and no other interrupts are acknowledged until the particular
interrupt is serviced by the CPU.
BITND.
NAME
CONDITION
Interrupt Pending
0
D1, D2
Interrupt ID bits 0, 1
Table below
D3 - D7
Not Used
0
DO
DESCRIPTION
This bit can be used in either a hardwired priortized
or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic 0, an interrupt
is pending and the IIR contents may be used as a
pointerto the appropriate interrupt service routine.
When bit 0 is a logic 1 , no interrupt is pending.
1
These two bits of the ItR are used to identify the
highest priority interrupt pending as indicated in
the following table.
These five bits of the IIR are always logic O.
INTERRUPT PRIORITY TABLE
02
01
DO
PRIORITY
0
0
1
-
1
1
0
1
0
0
0
TYPE
SOURCE
RESET
-
None
None
Highest
Receiver Line Status
Overrun Error,
Parity Error,
Framing Error or
Break Interrupt
Reading the Line
Status Register
0
Second
Receive Data
Available
Receive Data
Available
Reading the Rcvr.
Buffer Register
1
0
Third
Transmit Holding
Register Empty
Transmit Holding
Register Empty
Reading ItR Register
(if source of interrupt)
or Writing to Transmit
Holding Register
0
0
Fourth
Modem Status
Clear to Send or
Data Set Ready or
Ring Indicator or
Data Carrier Det.
Reading the Modem
Status Register
3-78
SSI73K222U
Single-Chip Modem
with UART
LINE CONTROL REGISTER (LCR)
STNDLN:
0
ADDRESS:
UA2 - UAO 011
1
UA3 - UAO
=
UART SECTION
=0011
The user specifies the format of the asynchronous data communications exchange via the Line Control
Register. In addition to controlling the format, the user may retrieve the contents of the Line Control Register
for inspection. This feature simplifies system programming and eliminates the need for separate storage in
system memory of the line characteristics.
BIT NO.
NAME
DO
Word Length Select 0
01
Word Length Select 1
02
Number of Stop Bits
CONDITION
DESCRIPTION
Bits DO and 01 select the number of data bits per
character as shown:
01
DO
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
oor 1
Word Length
This bit specifies the number of stop bits in each
transmitted character. If bit 2 is a logic 0, one stop
bit is generated in the transmitted data. If bit 2 is a
logic 1 when a 5-bit word length is selected via bits
and 1 , one-and-a-half stop bits are generated. If
bit 2 is a logic 1 when either a 6, 7, or 8-bit word
length is selected, two stop bits are generated.
The receiver checks the first stop bit only, regardless of the number of stop bits selected.
o
03
Parity Enable
1
This bit is the Parity Enable bit. When bit 3 is a logic
1, a parity bit is generated (transmit data) or
checked (receive data) between the last data word
bit and stop bit of the serial data. (The parity bit is
used to produce an even or odd number of 1's
when the data word bits and the parity bit are
summed).
04
Even Parity Select
1 or 0
This bit is the Even Parity Select bit. When bit 3 is
a logic 1 and bit 4 is a logic 0, an odd number of
logic 1 's are transmitted or checked in the data
word bits and parity bit. When bit 3 is a logic 1 and
bit 4 is a logic 1, an even number of logic 1 's are
transmitted or checked.
3-79
I
SSI73K222U
Single-Chip Modem
with UART
LINE CONTROL REGISTER (LCR) (Continued)
BIT NO.
05
UART SECTION
NAME
CONDITION
Stick Parity
1 or 0
DESCRIPTION
This bit is the Stick Parity bit. When bit 3 is a logic
1 and bit 5 is a logic 1, the parity bit is transmitted
and checked by the receiver as a logic 0 if bit 4 is
a logic 1 or as a logic 1 if bit 4 is a logic O.
05
04
0
0
Parity
ODD Parity
0
1
EVEN Parity
1
0
MARK Parity
1
SPACE Parity
1
06
Set Break
1
Output of modem is set to a spacing state. When
the modem is transmitting DPSK data if the Set
Break bit is held for one full character (start, data,
parity, stop) the break will be extended to 2 N + 3
space bits (where N = # data bits + parity bit + 1
start + 1 stop). Any data bits generated during this
time will be ignored. See note below.
07
Divisor Latch Access
Bit (DLAB)
1
This bit is the Divisor Latch Access Bit (DLAB). It
must be set high (logic 1) to access the Divisor
Latches of the baud generator during a Read or
Write operation. It must be set low (logic 0) to
access the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register.
NOTE: This feature enables the CPU to alert a terminal in a computer communications system. If the
following sequence is followed, no erroneous or extraneous characters will be transmitted because of the break.
1.
Load an all O's pad character in response to THRE.
2.
Set break in response to the next THRE.
3.
Wait for the Transmitter to be idle. (TSRE = 1), and clear break when normal transmission has
to be restored.
During the break, the Transmitter can be used as a character timer to accurately establish the
break duration.
3-80
SSI73K222U
Single-Chip Modem
with UART
MODEM CONTROL REGISTER (MCR)
STNDLN:
0
UA2-UAO=100
ADDRESS:
UART SECTION
1
UA3 - UAO = 0100
The MCR register controls the interface with the modem. Bits 01 and DO are also available as read only bits
in the UART Control Register in the Modem Registers. In single-port mode, bits 01 and DO are available
inverted at the RTS and OTR pins.
NAME
CONDITION
DO
OTR
1
This bit controls the Data Terminal Ready (OTR)
output. When bit 0 is set to a logic 1, the OTR
output is forced to a logic O. When bit 0 is reset to
a logic 0, the OTR output is forced to a logic 1.
01
RTS
1
This bit controls the Request to Send (RTS) output.
When bit 1 is set to a logiC 1, the RTS output is forced
to a logic O. When bit 1 is reset to a logic 0, the RTS
output is forced to a logic 1.
02
IlPRST*
(OUT1 in 16C450)
1
In single-port mode inactive unless loop = 1,
then functions as below (04). In dual-port mode
the IlPRST pin is the logical OR of this bit and the
RESET pin.
03
Enable Interrupt
(OUT2 in 16C450)
0
Sets INTRPT
STNOLN = 1.
04
LOOP
BIT NO.
05 - 07
DESCRIPTION
pin
to
high
impedance
if
1
INTRPT output enabled.
1
This bit provides a localloopback feature for diagnostic testing of the UART portion of the
SSI 73K222U. When bit D4 is set to logiC 1, the
following occurs:
1.
TXO is forced to mark, RXO is ignored.
2.
The output of the Transmitter is looped to the
Receiver.
3.
The four modem control inputs to the UART
(CTS, OSR, OCO, andRl) are ignored and the
UART signals RTS, OTR, Enable Interrupt, and
IlPRST are forced inactive.
4.
The UART signals RTS, OTR, Enable Interrupt, and IlPRST are internally connected to
the four control signals CTS, OSR, OCO and
RI respectively. Note that the Modem Status
Register Interrupts are now controlled by the
lowerfourbits of the Modem Control Register.
The interrupts are still controlled by the Interrupt Enable Register.
These bits are permanently set to logic O.
0
• Note: The Il-PRST bit has an upgraded function which was not included in the initial definition of the SSI 73K222U.
3-81
I
SSI73K222U
Single-Chip Modem
with UART
LINE STATUS REGISTER (lSR)
STNDLN:
0
UA2·UAO=101
ADDRESS:
1
UA3· UAO = 0101
UART SECTION
This register provides status information to the CPU concerning the data transfer.
BIT NO.
NAME
CONDITION
DO
DR
1
The Data Ready (DR) bit is set to a 1 whenever a
complete incoming character has been received
and transferred into the Receiver Buffer Register.
Data Ready is reset to 0 by reading the data in the
Receiver Buffer Register or by writing a 0 into it
from the processor.
01
OE
1
The Overrun Error (OE) bit indicates that the data
in the Receiver Buffer Registerwas not read by the
CPU before the next characterwas transferred into
the Receiver Buffer Register, thereby destroying
the previous character. The OE indicator is reset
whenever the CPU reads the contents of the Line
Status Register.
02
PE
1
The Parity Error (PE) bit indicates that the received
character did not have the correct parity. The bit is
reset to 0 whenever the CPU reads the Line Status
Register.
03
FE
1
The Framing Error (FE) bit indicates that the received character did not have a valid stop bit. The
FE indicator is reset whenever the CPU reads the
contents of the Line Status Register. A framing
error will not occur in DPSK receive from the
modem due to the fact that missing stop bits are
reinserted.
04
BI
1
The Break Interrupt (BI) bit indicates that a break
has been received. A break occurs whenever the
received data is held to 0 for a full data word (start
+ data + stop) or for two full data words when
receiving in DPSK mode from the modem. The BI
bit is reset to 0 whenever the CPU reads the Line
Status Register.
05
THRE
1
The Transmit Holding Register Empty (THRE)
indicates that the Transmitter is ready to accept a
new character for transmission. The THRE bit is
reset when the CPU loads a character into the
Transmit Holding Register.
06
TSRE
1
The Transmit Shift Empty (TSRE) indicates that
both the Transmit Holding Register and the Transmit Shift Registers are empty.
07
-
0
Always zero.
3-82
DESCRIPTION
SSI73K222U
Single-Chip Modem
with UART
MODEM STATUS REGISTER (MSR) (READ ONLY)
STNDLN:
0
1
ADDRESS:
UA2 - UAO = 110
UA3 - UAO = 0110
UART SECTION
This register provides the current state of the control signals from the modem. In addition, four bits provide
change information. The CTS, DSR, DCD, and RI Signals come from the UART Control Register if
STNDLN = 0 and from the CTS, DSR, DCD and RI pins (inverted) if STNDLN = 1. This register is READ ONLY.
The delta bits indicate whether the inputs have changed since the last time the Modem Status Register has
been read. In Loop Mode CTS, DSR, RI and DCD are taken from RTS, DTR, IlPRST, and Enable Interrupt
in the Modem Control Register respectively.
BIT NO.
NAME
CONDITION
DO
DCTS
1
This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the CTS input to the chip
has changed state since the last time it was read by
the CPU.
D1
DDSR
1
This bit is the Delta Data Set Ready (DDSR)
indicator. Bit 1 indicates that the DSR input to the
chip has changed state since the last time it was
read by the CPU.
D2
TERI
1
This bit is the Trailing Edge of the Ring Indicator
(TERI) detector. Bit 2 indicates that the RI input to
the chip has changed state.
D3
DDCD
1
This bit is the Delta Data Carrier Detect (DDCD)
indicator. Bit 3 indicates that the DCD input to the
chip has changed state.
D4
CTS
1
This bit is the complement of the Clear To Send
(CTS) input. If STNDLN =0, this reflects the status
of the UART Control Register bit. If bit 4 (loop) of
the MCR is set to a 1, this bit is equivalent to RTS
in the MCR.
D5
DSR
1
This bit is the complement of the Data Set Ready
(DSR) input. If STNDLN =0, this reflects the status
of the UART Control Register bit. If bit 4 of the MCR
is set to a 1, this bit is the equivalent of DTR in the
MCR.
D6
RI
1
This bit is the complement of the Ring Indicator (RI)
input. If STN DLN = 0, this reflects the status of the
UART Control Register bit. If bit 4 of the MCR is set
to a 1, this bit is equivalent to IlPRST in the MCR.
D7
DCD
1
This bit is the complement of the Data Carrier
Detect (DCD) If STNDLN = 0, this reflects the
status of the UART Control Register bit. If bit 4 of
the MCR is setto a 1, this bit is equivalentto Enable
Interrupt in the MCR.
3-83
DESCRIPTION
I
SSI73K222U
Single-Chip Modem
with UART
SCRATCH REGISTER (SCR)
STNDLN:
0
ADDRESS:
UA2 • UAO
UART SECTION
1
UA3· UAO = 0111
=111
The Scratch Register is a dual port register which can be simultaneously accessed through both the UART
bus and the modem bus.This provides the possibility for the modem controller to communicate directly with
the central CPU. Note that if both processors write the Scratch Register, the data stored will be from whichever
processor last wrote the register.
DIVISOR LATCH (Least significant byte) (DLL)
STNDLN:
0
ADDRESS:
UA2· UAO = 000, DLAB = 1
UA3 • UAO
DIVISOR LATCH (Most significant byte) (DLM)
STNDLN:
0
ADDRESS:
UA2· UAO = 001, DLAB = 1
1
UA3 • UAO = 0001, DLAB
1
=0000, DLAB =1
=1
DIVISOR LATCH VALUE VS. DATA RATE
The Divisor Latch is two 8-bit write only registers which control the rate of the programmable baud generator.
The programmable baud generator generates an output clock by dividing an internal 1.8432 MHz clock by the
value stored in the divisor latch. This output clock has a value of 16X the data rate at which the modem will
operate. This output clock is available at pin 21 underthe control of bit 3 (D3) of the Modem Control Register 1.
Upon loading either of the Divisor Latches the 16-bit device counter is immediately loaded, preventing long
counts on initial load. The following table shows divisor values for common data rates.
DESIRED
DATA RATE
DIVISOR USED
FOR 16 x DATA
RATE CLOCK
% ERROR
GENERATED
DESIRED
DATA RATE
DIVISOR USED
FOR 16 x DATA
RATE CLOCK
50
1
2304
4800
24
75
1
1536
7200
16
1047
9600
12
19200
6
110
1
1
134.5
857
0.058
% ERROR
GENERATED
159
1
768
38400
3
300
1
384
56000
2
600
2
192
1.
Data Rate valid for FSK transmission.
96
2.
Data Rate valid for halfspeed DPSK transmission.
3.
Data Rate valid for normal 1200 BIT/S DPSK
transmission.
1200
3
1800
64
2000
58
2400
48
3600
32
0.69
3-84
2.86
SSI73K222U
Single-Chip Modem
with UART
MODEM REGISTER BIT DESCRIPTIONS
CONTROL REGISTER (CRO)
STNDLN:
0
ADDRESS:
MA2 - MAO = 000
BIT NO.
DO
D1
1
UA3 - UAO
MODEM SECTION
=1000
NAME
CONDITION
Answer/Originate
0
Selects Answer Mode (transmit in high band, receive in low band).
1
Selects Originate Mode (transmit in low band,
receive in high band).
0
Disables transmit output at TXA.
Transmit Enable
1
DESCRIPTION
Enables transmit output at TXA.
NOTE: Answer tone and DTM F TX control require
Transmit Enable. If Transmit Enable is on, call
progress and answer tone detector interrupts are
masked.
D2,D3
D4
D5
These bits are read only. These bits represent the
character size. The character size is determined
by the UART Line Control Register and includes
data, parity (if used), one start bit, and one stop bit.
Character Size 0, 1
D3
D2
0
0
8-bit character
0
1
9-bit character
1
0
1O-bit character
1
1
11-bit character
This bit controls the power down mode of the
SSI 73K222U, the analog, and most digital portions of the chip. The digital interface is active
during power down.
Power ON
Modulation Mode
Character length
0
Power down mode.
1
Normal operation.
0
DPSK
1
FSK
D6
Reserved
0
Must be written as zero.
D7
Modulation Option
0
DPSK: 1200 bitls
600 bitls
1
FSK:
0
1
103 mode
V.21 mode
3-85
I
SSI73K222U
Single-Chip Modem
with UART
CONTROL REGISTER (CR1)
STNDLN:
0
ADDRESS:
MA2 • MAO = 001
BIT NO.
DO,D1
D2
D3
D4
NAME
Test Mode
Reset
ClK Control
(Clock Control)
Bypass Scrambler
MODEM SECTION
1
UA3· UAO = 1001
CONDITION
DESCRIPTION
D1
DO
0
0
Selects normal operating mode.
0
1
Analog loopback Mode. loops the transmitted
analog signal back to the receiver, and causes the
receiver to use the same center frequency as the
Transmitter. To squelch the TXA pin, transmit
enable bit must be forced low.
1
0
Selects remote digitalloopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data in TXD is ignored.
1
1
Selects half-duplex. Internally performs a logical
AND of TXD and RXD to send to the UART
receiver. Both transmit and receive characters will
occur at the Receiver Buffer Register.
0
Selects normal operation.
1
Resets modem to power down state. All Control
Register bits (CRO, CR1 , TONE) are reset to zero.
The output of the clock pin will be set to the crystal
frequency.
0
ClK pin output is selected to be an 11.0592 MHz
crystal echo output.
1
ClK pin output is selected to be 16 x the Data Rate
set by the UART divisor latch.
0
Selects normal operation. DPSK data is passed
through scrambler.
1
Selects Scrambler Bypass. DPSK data is routed
around scrambler in the transmit path.
3-86
SSI73K222U
Single-Chip Modem
with UART
CONTROL REGISTER (CR1) (Continued)
BIT NO.
05
06,07
MODEM SECTION
NAME
CONDITION
Enable Detect
Interrupt
0
Disables interrupts generated by Detect Register
bits 01 - 04 at INT pin in dual-port mode, or at
INTRPT pin in single-port mode. All interrupts
normally disabled in power down modes.
1
Enables interrupts generated by Detect Register
bits 01 - 04 at INT pin in dual-port mode, or at
INTRPT pin in single-port mode. An interrupt will
be generated with a change in status of DR bits
01 - 04. The answer tone and call progress detect
interrupts are masked when the TX enable bit is
set. Carrier detect is masked when TX DTM F is
activated. All interrupts will be disabled if the
device is in power down mode. The interrupt is
reset when the DR register is read.
Transmit Pattern
DESCRIPTION
07
06
0
0
Selects normal data transmission as controlled by
the state of the TXD pin.
0
1
Selects an alternating mark/space transmit pattern
for modem testing.
1
0
Selects a constant mark transmit pattern.
1
1
Selects a constant space transmit pattern.
3-87
II
SSI73K222U
Single-Chip Modem
with UART
DETECT REGISTER (DR)
STNDLN:
0
MA2 - MAO = 010
ADDRESS:
BIT NO.
DO
D1
D2
D3
D4
D5
1
UA3 - UAO = 1010
MODEM SECTION
NAME
CONDITION
Long Loop
0
Indicates normal received signal.
1
Indicates low received signal level « -38 dBm).
0
No call progress tone detected.
1
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy
in the normal 350 to 620 Hz call progress bandwidth.
0
No answer tone detected.
1
Indicates detection of 2225 Hz answer tone in Bell
mode or21 00 Hz in CCITT mode. The device must
be in Originate Mode for detection of answer tone
for normal operation. For CCITT answer tone
detection, bit DO of the Tone Register must be set.
Call Progress Detect
Answer Tone Received
Carrier Detect
Unscrambled Marks
0
No carrier detected in the receive channel.
1
Carrier has been detected in the receive channel.
0
No unscrambled mark detected.
1
Indicates detection of unscrambled marks in the
received data. A valid indication requires that
unscrambled marks be received for > 165.5 ±
13.5 ms.
Continuously outputs the received data stream.
This data is the same as that output on the RXD
pin, but it is not disabled when RXD is tri-stated.
Receive Data
D6,D7
Device Signature 0, 1
DESCRIPTION
Product Identified
D7
D6
0
0
SSI 73K212U (special order only)
0
1
SSI 73K221 U (special order only)
1
0
SSI73K222U
3-88
SSI73K222U
Single-Chip Modem
with UART
TONE CONTROL REGISTER (TONE)
STNDLN:
0
ADDRESS:
MA2 - MAO = 011
MODEM SECTION
1
UA3 - UAO = 1011
The Tone Control Register contains information on the tones that are transmitted. Tones are transmitted only
if the Transmit Enable bit is set. The priority of the transmit tones are: 1) OTMF, 2) Answer, 3) FSK,
4) Guard.
BIT NO.
00
NAME
OTMF 0 / Answer/
Guard Tone
00,01,
02,03
OTMF
CONDITION
DESCRIPTION
06 05 04 00
00 interacts with bits 06, 05, and 04 as shown:
X
X
1
X
Transmit OTMF tones.
X
1
0
0
Select 2225 Hz answer tone (Bell).
X
1
0
1
Select 2100 Hz answer tone (CCITT).
1
0
0
0
Select 1800 Hz guard tone.
1
0
0
1
Select 550 Hz guard tone.
Table below
Programs 1 of 16 OTM F tone pairs that will be
transmitted when TX DTMF and TX enable bit
(CRO, bit 01) is set. Tone encoding is shown
below.
KEYBOARD
EQUIVALENT
3-89
I
DTMF CODE
03 02 01 DO
TONES
LOW
HIGH
1
0
0
0
1
697
1209
2
0
0
1
0
697
1336
3
0
0
1
1
697
1477
4
0
1
0
0
770
1209
5
0
1
0
1
770
1336
6
0
1
1
0
770
1477
7
0
1
1
1
852
1209
8
1
0
0
0
852
1336
9
1
0
0
1
852
1477
0
1
0
1
0
941
1336
*
1
0
1
1
941
1209
#
1
1
0
0
941
1477
A
1
1
0
1
697
1633
B
1
1
1
0
770
1633
C
1
1
1
1
852
1633
0
0
0
0
0
941
1633
SSI73K222U
Single-Chip Modem
with UART
TONE CONTROL REGISTER (TONE) (Continued)
D4
D5
D6
D7
TX DTMF
0
Disable DTMF.
(Transmit DTM F)
1
Activates DTMF. The selected DTMF tones are
transmitted continuously when this bit is high. TX
DTMF overrides all other transmit functions.
TXANS
D5
DO
D5 interacts with bit DO as shown.
(Transmit Answer Tone)
0
X
Disables answer tone generator.
1
0
Enables answer tone generator. A 2225 Hz answer tone will be transmitted continuously when
the transmit enable bit is set. The device must be
in answer mode.
1
1
Enables a 2100Hz answer tone generator, with
operation same as above.
TX Guard
0
Disables guard tone generator.
(Transmit Guard Tone)
1
Enables guard tone generator. (See DO for selection of guard tones).
RXD/TXD Control
CONTROL REGISTER (CR3)
STNDLN:
0
ADDRESS:
MA2· MAO
BIT NO.
NAME
DO - D4
Not Used
D5
Off Hook
06,07
MODEM SECTION
D7
Function is dependant on status of STNDLN pin.
0
0
RXD is output data received by modem, TXO is
serial output of UART.
1
0
RXD is electrically an input, but the signal is
ignored, TXD is forced to a mark.
X
1
RXD is serial input to UART, TXD is serial output
of UART.
STNDLN
1
UA3· UAO
=101
Speaker Volume 0, 1
CONDITION
=1101
DESCRIPTION
Not presently used.
0
Relay driver open.
1
Open drain driver pulling low.
D7
D6
0
0
Speaker volume control status.
Speaker off
0
1
-24 dB
1
0
-12 dB
1
1
OdB
3-90
SSI73K222U
Single-Chip Modem
with UART
SCRATCH REGISTER (SCR)
STNDLN:
0
ADDRESS:
MA2 - MAO
=110
1
UA3 - UAO
MODEM SECTION
=1110
The Scratch Register is a dual-port registerwhich can be accessed either through the UART bus orthe modem
bus. It can be used for a communication path outside the data stream.
UART CONTROL REGISTER (UCR)
STNDLN:
0
ADDRESS:
MA2 - MAO 111
=
1
UA3 - UAO
=1111
The UART Control Register contains the handshaking signals necessary for the microprocessor to communicate with the central CPU through the UART.
BIT NO.
NAME
CONDITION
DO
CTS
1
01
OSR
1
02
OCO
1
03
RI
1
04
OTR
1
05
RTS
1
06
Not Used
07
TXCLK
DESCRIPTION
In dual-port mode, CTS, DSR, OCO and RI are
writeable locations which can be read through the
16C450 port in the Modem Status Register.
In the single-port mode, DO - 03 are ignored and
the information for the Modem Status Register
comes directly from the external pins.
OTR and RTS are read only versions of the
same register bits in the Modem Contol Register.
Clock
TXCLK is the clock that the UART puts out with
TXO. The falling edge of TXCLK is coincident with
the transitions of data on TXO. TXCLK can also be
used for the microprocessor to send synchronous
data independent of the UART by forcing data
patterns using CR1 bits 6 and 7 before the rising
edge of TXCLK.
NOTE: Control Register 2 (CR2) is reserved for~future products and is disabled.
3-91
I
SSI73K222U
Single-Chip Modem
with UART
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
TA = -40°C to 85°C, VDD = 5V ± 10%, unless otherwise noted.
RATING
UNIT
VDD Supply Voltage
7
V
Storage Temperature
-65 to 150
°C
260
°C
-0.3 to VDD +0.3
V
PARAMETER
Soldering Temperature (10 sec.)
Applied Voltage
NOTE: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VDD, Supply Voltage
4.5
5
5.5
V
TA, Operating Free-Air
Temperature
-40
85
°C
PARAMETERS
CONDITIONS
External Component (Refer to application drawing for placement.)
VREF Bypass Capacitor 2
(VREF to GND)
0.1
Bias Setting Resistor 1
(Placed between VDD
and ISET pins)
1.8
ISET Bypass Capacitor 2
ISET pin to GND
0.1
VDD Bypass Capacitor
(VDD to GND)
0.1
XTL 1 Load Capacitor
XTL2 Load Capacitor
Input Clock Variation
2
IlF
2
MQ
IlF
IlF
From pin to GND
From pin to GND
(11.0592 MHz)
2.2
-0.01
40
pF
20
pF
+0.01
%
Hybrid Loading
R1
See Figure 3
600
R2
C
TXA Hybrid Loading
600
.Q
0.033
IlF
1. Optional for minimum worst case current consumption.
2. Minimum for optimized system layout; may require higher values for noisy environments.
3-92
.Q
SSI73K222U
Single-Chip Modem
with UART
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to +85 °c, VDD = 5V ± 10%, unless otherwise noted.
CONDITIONS
PARAMETERS
MIN
NOM
MAX
UNIT
8
12
rnA
100, Supply Current
IDDA, Active
= 2MO
ISET Resistor
= GND
IDDA, Active
ISET
8
15
rnA
1001, Power-Down
ClK = 11.0592MHz
3
4
rnA
1002, Power-Down
ClK = 19.200KHz
2
3
rnA
100
~
Digital Inputs
Input High Current
IIH
VI = VDD
Input low Current
III
VI =0
Input low Voltage
VIL
Input High Voltage
VIH
Except RESET & XTl1
2.0
VIH
RESET & XTl1
3.0
Input High Voltage
Pull Down Current
~
-200
0.8
V
V
5
RESET PIN
V
Input Capacitance
30
~
10
pF
VDD
V
Digital Outputs
Output High Voltage VOH
lOUT = -1 rnA
2.4
Val UDO-UD7 and INTRPT
lOUT = 3.2 rnA
0.4
V
Val other outputs
lOUT
= 1.6 rnA
0.4
V
ClK Output
Val
lOUT = 3.2 rnA
0.6
V
OH Output
Val
lOUT = 20 rnA
1.0
V
OH Output
Val
0.5
V
20
~
Offstate Current INTRPT pin
lOUT
= 10 rnA
-20
VO=OV
Capacitance
Inputs
Input Capacitance
10
pF
ClK
Maximum capacitive load to pin
15
pF
Analog Pins
200
RXA Input Resistance
kO
25
RXA Input Capacitance
3-93
pF
I
SSI73K222U
Single-Chip Modem
with UART
DYNAMIC CHARACTERISTICS AND TIMING
TA = -40°C to +85°C, VDD = 5V ± 10%, unless otherwise noted.
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNIT
DPSK Modulator
Carrier Suppression
Measured at TXA
55
Output Amplitude
ANS TONE 2225 or 2100 Hz
-11
-10.0
-9
DPSK TX Scrambled Marks
-11
-10.0
-9
dBmO
FSK Dotting Pattern
-11
-10.0
-9
dBmO
±5
Hz
FSK Tone Error
dB
Bell 103 or V.21
dBmO'
DTMF Generator
Freq. Accuracy
-.25
Output Amplitude
Low Band, not in V.21 mode
Output Amplitude
-10
-9
-7
High Band, not in V.21 mode
-8
Long Loop Detect
DPSK or FSK
-40
Demodulator
Dynamic Range
DPSK or FSK
.25
%
-8
dBmO
-6
dBmO
-32
dBmO
dB
45
Call Progress Detector
Detect Level
2-Tones in 350-600 Hz Band
Reject Level
2-Tones in 350-600 Hz Band
Delay Time
-70dBmO to -30 dBmO Step
Hold Time
-30dBmO to -70 dBmO Step
Hysteresis
Carrier Detect
-39
0
dBmO
-46
dBmO
27
80
ms
27
80
ms
2
dB
DPSK or FSK Receive
Threshold
Data
-49
-42
dBmO
Delay Time
-70 dBmO to -30 dBmO Step
15
45
ms
-30 dBmO to -70 dBmO Step
10
24
ms
-49.5
-42
dBmO
Hysteresis
Hold Time
2
dB
3.0
Answer Tone Detector
Detect Level Threshold
In FSK mode
Delay Time
-70 dBmO to -30 dBmO STEP
20
45
ms
Hold Time
-30 dBmO to -70 dBmO STEP
10
30
ms
-2.5
+2.5
%
Detect Frequency Range
1. All units in dBmO are measured at the line input to the transformer. The interface circuit inserts an 8 dB
loss in the transmit path (TXA1 - TXA2 to line), and a 3dB loss in the receive path (line to RXA).
3-94
SSI73K222U
Single-Chip Modem
with UART
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
CONDITIONS
MIN
10KI150 pF LOAD 5% THD
2.75
Capture Range
Originate or Answer
-10
Capture Time
-10Hz to +10 Hz Carrier
Frequency change assumed
PARAMETERS
NOM
MAX
UNIT
Speaker Output
-1
Gain Error
Output Swing SPKR
+1
dB
VP
Carrier VCO
40
10
Hz
100
ms
Recovered Clock
Capture Range
% of Center Frequency
Data Delay Time
Analog data in at RXA pin to
receive data valid at RXD pin.
+625
ppm
30
50
ms
-625
Guard Tone Generator
Tone Accuracy
550 or 1800 Hz
-20
+20
Hz
Tone Level
550 HZ
-4.0
-3.0
-2.0
dB
(Below DPSK Output)
1800 HZ
-7.0
-6.0
-5.0
dB
Harmonic Distortion
700 to 2900 HZ
-60
dB
MAX
UNIT
140
ns
200
ns
200
ns
10000
ns
SERIAL BUS INTERFACE (See Figure 4)
The following times are for CL = 100 pF.
MIN
PARAMETER
TRD
0
Data out from Read
TCKD
Data out after Clock
TRDF
Data Float after Read
0
TRCK
Clock High after Read
200
TWW
Write Width
140
NOM
ns
TDCK
Data Setup Before Clock
150
ns
TCKH
Data Hold after Clock
20
ns
TCKW
Write after Clock
150
ns
TACR
Address setup before Control'
50
ns
TCAR
Address Hold after Control'
50
ns
TACW
Address setup before Write
50
ns
TCAW
Address Hold after Write
50
ns
1. Control is later of falling edge of R D or DCLK.
3-95
I
SSI73K222U
Single-Chip Modem
with UART
PARALLEL BUS INTERFACE (See Figure 5) The following times are for CI
PARAMETER
MIN
MAX
Dual-Port Mode
RC
Read Cycle
= TAD -I- TRC
240
TDIW
DISTR Width
TODD
Delay DISTR to Data (read time)
THZ"
DISTR to Floating Data Delay
0
TRA
Address Hold after DISTR
20
TRCS
Chip select hold after DISTR
TAR*
DISTR Delay after Address
TCSR
DISTR Delay after Chip Select
WC
Write Cycle
TDOW
= 100 pF.
MIN
MAX
Single-Port Mode
340
80
ns
80
80
50
UNIT
0
ns
80
ns
50
ns
20
ns
20
20
ns
20
20
ns
20
20
ns
140
140
ns
DOSTR Width
80
80
ns
TDS
Data Setup
30
50
ns
TDH**
Data Hold
20
20
ns
TWA
Address Hold after DOSTR
20
20
ns
TWCS
Chip select hold after DOSTR
20
20
ns
= TAW + TDOW + TWC
TAW*
DOSTR delay after Address
20
20
ns
TCSW
DOSTR delay after Chip Select
20
20
ns
TAOS
Address Strobe Width
40
ns
TAS
Address Setup Time
30
ns
TAH
Address Hold Time
0
ns
TCS
Chip Select Setup Time
30
ns
TCH
Chip Select Hold Time
0
ns
TRC
Read Cycle Delay
40
40
ns
TWC
Write Cycle Delay
40
40
ns
TAD
Address to Read Data
200
300
ns
*
TAR and TAW are referenced from the falling edge of either CS2 or DISTR or DOSTR, which ever is later.
**
THZ and TDH are referenced from the rising edge of CS2 or DISTR or DOSTR, which ever is earlier.
3-96
SSI73K222U
Single-Chip Modem
with UART
TXA1
R1
RXA ..,;:....----1
c
110
1:1
TXA2
6000
R2
(Nominal Telephone
Line Impedance)
TA Hybrid Loading
Analog Interface Hybrid Loading
FIGURE 3: TXA Hybrid Loading Analog Interface Hybrid Loading
READ MODE
DCLK
1m
ADDRESS
TACR1
TRD
DO
DATA
WRITE MODE
DCLK
WR"
ADDRESS
DATA
FIGURE 4: Modem Serial Bus Timing
3-97
•
SSI73K222U
Single-Chip Modem
with UART
ADS
(STNDLN =1)
ADDRESS
UA2 (UA3)-UAO
TAR
DATA
UD7-UDO
FIGURE 5: UART Bus Timing
3-98
SSI73K222U
Single-Chip Modem
with UART
TYPICAL PERFORMANCE CHARACTERISTICS
The SSI 73K222U was designed using an integrated
analogldigital architecture that offers optimum performance over a wide range of line conditions. The
SSI 73K222U utilizes the circuit design proven in
SSI's 73K222L one-chip modem, with added enhancements which extend low signal level performance and increase immunity to spurious noise typically encountered in integral bus applications. The
SSI 73K222U provides excellent immunity to the types
of disturbances present with usage of the dial-up
telephone network. The following curves show representative Bit Error Rate performance under various
line conditions.
BER vs. SIN
This test measures the ability of the modem to function
with minimum errors when operating over noisy lines.
Since some noise is generated by even the best dialup lines, the modem must operate with as Iowa SIN
ratio as possible. Optimum performance is shown by
curves that are closest to the zero axis. A narrow
spread between curves for the four line conditions
indicates minimal variation in performance when operating over a range of line qualities and is typical of high
performance adaptive equalization receivers. High
band receive data is typically better than low band due
to the inherent design of PSK modems.
SSI73K222U
BERvsRECEWELEVEL
SSI73K222U
BER vs SIN
J
~
J
HIGH BAND RECEIVE
·40 dBm
DPSK OPERATION
\ ~ IS
J
\~ L~~ ~ rr I--
\ 1\\
!;t
a::
a::
0 10.4
a::
a::
\
UJ
CD
10.3
\
C2
l'! ~
UI
Cl or 3002
!;t
r--r-l
~~
!:::
'c2
r--
\' ~~
\
a::
a::
0 10-4
a::
a::
r'---'
1--1 FLflT
~
\
\~ KClor3002J I\'l\
UJ
!:::
Cl
,\\ tooo ~ '\\
1\\\
\ ,\
10.5
\
1\
\
SIN = 10.8 dB
\
10.5
~
\
'1\ \
,\
~\
\\1\
\ \
4
C2 LINE
BPS
600
UJ
I
-1
~
10.3
I HIGH
BAND RECEIVE ~
DPSK OPERATION
~
1\
i~
\ \
10
12
10
14
SIGNAL TO NOISE (dB)
SIN -15 dB
-1 0
·20
-30
RECEIVE LEVEL (dBm)
3-99
-40
·50
I
SSI73K222U
Single-Chip Modem
with UART
BER vs. Receive Level
SSI73K222U
BER vs CARRIER OFFSET
This measures the dynamic range of the modem. As
signal levels vary widely over dial-up lines, the widest
dynamic range possible is desirable. The minimum
Bell specification calls for 36dB of dynamic range.
SIN ratios were held constant at the indicated values
while receive level was lowered from very high to very
low signal levels. The ''width of the bowl" of these
curves taken at the 10· BER point is a measure of the
dynamic range.
I HIGH BAND RECEIVE
I DPSK OPERATION
I--
10-3
W
I-
oct
a:
a:
0
a:
a:
w
t::
co
BER vs. Carrier Offset
This parameter indicates howthe modem performance
is impacted by frequency shifts encountered in normal
PSTN operation. Flat curves show no performance
degradation from frequency offsets. The SSI K-Series
devices use a 2nd order carrier tracking phase-Iockedloop, which is insensitive to carrier offsets in excess of
10Hz. The Bell network specifications allow as much
as 7Hz offset, and the CCITT specifications require
modems to operate with 7Hz of offset.
10-4
J
I
10-5
C2 10.8 dB SIN
-12
I--
300211.5 dB SiN
\
I
r\. r-
I- P
4
\
.....-
--
f.-- v
f-'"'
f--
-4
-8
-12
SIGNAL TO NOISE (dB)
APPLICATION
The SSI73K222U includes additional circuitry to greatly
simplify integral modem designs in either of two different configurations. The Single-port mode represents
the most efficient implementation for an integral modem. Figure 9 shows a typical schematic using this
mode. In this configuration, the SSI 73K222U transfers data and commands through the Single parallel
port. All modem control is provided by the main CPU,
eliminating the need for an external microcontroller
and supporting components. The SSI 73K222U is
unique in that access to both the UART and modem
sections is possible through the UART port. Also
shown is a separate serial port, which can be used
independent of the modem function when the modem
section is inactive. Figure 10 shows a more conventional integral modem design, in which a local microprocessor handles modem supervision, allowing the
modem function to be transparent to the main processor. Inclusion of the hybrid drivers, audio volume
control, and off hook relay driver reduces component
count for a highly efficient design. In either mode of
operation, the SSI 73K222U's ability to operate from a
single +5 volt power supply eliminates the need for
additional supply voltages and keeps power usage to
a minimum.
(See Figure 9 & 10: Typical Integral Applications
Single and Dual-Port Modes.)
3-100
U2
.5
R6
PC BUS
3
VOO
C4
IRO
I
0.1
~
CI39pF 11'7~H~
T
C2 '8pF
AO A31
I
I
A2 A29 T
A3 A26 I
Al A30
XTLl
Xl
24
XTL2
UAO
neD
7
38
UAl
RXO
6
37
UA2
~
.E.:
UA3
graW!~.AL
Al5S'
SERIAL PORT
t5l:ll'11
U'~OI\
AS A26
A6 A25
15
39
T
I
.5
STNOALN
"¢'
.5
A4 A27
~F
I
"L-..-<
II
121
7
L--d
m
A7 A24
A8 A23
A9 A22
SSI
73K222U
~
ow
T.
-'"
R5W B13
36
lll%TA
lOF[B14
35
~
~
·
i= ~
-~
b
.,
1N4004
05
1N4004
mi
Jl
26
UOO
UOl
RXA
16
16
29
UD2
neAl
3
D3 A6
30
UD3
D4 AS
31
UD4
MOVl
OS A4
32
UDS
V250LA20A
06 A3
33
U06
07 A2
34
U07
08 A9
27
01 AS
02 A7
neA2
SPKA
.SV
R5
Rl 600n
Fus'!!ble
T
RUNE
Al
A
~
4
4 ...
~A
,C9
•
~F R3 5.1K
.5
...
~
~~
U5
LM386
Fuseable
10
Al
PHONE
en
:i"
(Q
o.N
mN
:e
-I3~
II
U2
PC BUS
IRoo
IR04
,oo~
J3
825
COM 2 INT
824
INTRPT ONO
ISET
C 1 39pF 11.0S92MHz
.5V
~
I
10,.1'
~8pF
25
OXI
37
A2A29
UAO
~~~
::;:':::l_
::::T (Q -.J
C8
'~~
1,.1'
c:1"
.... ON
8053
G
~
DATA
22
OQJ(
TXO
RXO
6
l'Sm
29
!J(
31
ALE
11
RXO
TXO
1
Pl.0
P3.4
61 U3
11
2
Pl.l
1'!ll 23
WIi 26
4
Pl.3
P3.6
5
PU
P3.7
MA2
12
8
Pl.7
MAl
13
7
Pl.6
MAO
14
t:t:R"
21
LS30
NIC
-"'::::TN
~ _. N
-Cc
3:
o
a.
(t)
3
PO
CS:!
A8 A23
A9 A22
I
UA2
A5 A26
A6 A25
9
STNDAUlI 15
231J;llS
A7 A24
.5
vool40
XTll
UAI
Al A30
A3 A28
Ul
C4
0.1,.1'
XTl2
39
AO A31
M A27
20
R7
3
COMIINT
B3
81 I
.5
6
WC
!NT
2
P2
Pl.5
19
Xl
18
X2
12
"1m>
R7
221<
SS/
73K222U
""RST I 8
05
1N4004
p .-
,
Jl
c:+--..-o .5V
R5
In
Fuseable
NO
~
LINE
Al
MOYI
V2SU.A2OA
I
.~..
:
-0 R
A
• T
~R
R6
Al
10
Fuseable
FIGURE 10: 73K22U Typical Integral Application Dual-Port Mode
PHONE
SSI73K222U
Single-Chip Modem
with UART
PACKAGE PIN DESIGNATIONS
CAUTION:
Use handling procedures necessary
for a static sensitive component.
(Top View)
CS2
VDD
(RTS) ITNT
UAO
TXAI
UAI
Parentheses indicate single-port mode.
UA2
DOSTR
INTRPT
RXD
"l5iSfR
TXD
UD7
6
5
4
3
2
INTRPT
1
44
43
42
41
40
0
RXD
8
TXD
9
39
DOSTR
38
DISTR
(Ai) I!I'RST
UD6
ISET
UDS
(Fi"j I~PRST
10
36
UD6
RESET
UD4
ISET
11
35
UD5
(UCD)/DClK
UD3
RESET
12
(UA3)/MA2
UD2
(DCD) I DCLK
13
33
(DSR)/MAI
UDI
(UA3) I MA2
14
32
UD2
(DSR)/MAI
15
31
UDI
(CTS) I MAO
16
30
UDO
STNDLN
17
29
N/C
(CTS)/MAO
UDO
STNDlN
UD7
UD4
UD3
WR/(N/C)
RXA
XTll
SPKR
XTl2
OR"
'AD I
VREF
19
<:
er:
x
er:
(ADS)
DATAl (DTR)
GND
18
~
CL
en
20
21
22
23
24
25
26
16
I~
0
~
I--
<:
<:
~
I--
Z
Cl
0
~
oc
I-Q.
I~
~
x
27
28
-'
I~
I--
x
ClK
44-Pin
PLCC
600-Mil
40-Pin DIP
ORDERING INFORMATION
ORDER NO.
PART DESCRIPTION
PKG.MARK
SSI73K222U
40-Pin Plastic Dual-In-Line
73K222U-IP
73K222U-IP
44-Pin Plastic Leaded Chip Carrier
73K222U-IH
73K222U-IH
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-6914
1293 - rev.
3-103
©1989 Silicon Systems, Inc.
•
Notes:
3-104
SSI73K224L
V.22bis/V.22/V.21 ,
Bell 212A/1 03
Single-Chip Modem
January 1994
DESCRIPTION
FEATURES
The SSI 73K224L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a V.22bis compatible modem, capable of
2400 biVs full-duplex operation over dial-up lines. The
SSI 73K224L offers excellent performance and a high
level of functional integration in a single 28-pin DIP.
This device supports V.22bis, V.22, V.21, Bell 212A
and 8ell103 modes of operation, allowing both synchronous and asynchronous communication.The
SSI 73K224L is designed to appear to the systems
designer as a microprocessor peripheral, and will easily interface with popular single-chip microprocessors
(80C51 typical) for control of modem functions through
its 8-bit multiplexed address/data bus orvia an optional
serial control bus. An ALE control line simplifies address demultiplexing. Data communications normally
occur through a separate serial port. The SSI 73K224L
is pin and software compatible with the SSI 73K212L
and SSI 73K222L single-chip modem ICs, allowing
system upgrades with a single component change.
One-chip multi-mode V.22bls/V.221V.21 and
Bell 212A11 03 compatible modem data pump
FSK (300 bit/s), OPSK (600,1200 bltls), or QAM
(2400 bitls) encoding
Pin and software compatible with other
SSI K-Series 1-chip modems
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Parallel microprocessor bus for control with a
wide range of package options
Selectable asynch/synch with Internal bufferl
de buffer and scrambler/descrambler functions
All synchronous and asynchronous operating
modes (internal, external, slave)
Adaptive equalization for optimum performance
over all lines
Programmable transmit attenuation (16 dB, 1 dB
steps), selectable receive boost (+18 dB)
Call progress, carrier, answer tone, unscrambled
mark, S1, and signal quality monitors
OTMF, answer and guard tone generators
The SSI 73K224L operates from a single +5 V supply
for low power consumption.
Test modes available: ALB, Ol, ROl, Mark, Space,
Alternating bit, S1 pattern
CMOS technology for low power consumption
(typically 100 mW @ 5V) with power-down mode
(15 mW@5V)
TTL and CMOS compatible inputs and outputs
The SSI73K224L is ideal foruse in either free-standing
or integral system modem products where full-duplex
(Continued)
BLOCK DIAGRAM
8-BlT
~p
BUS
UF
I
I
!: I
:AGC
:
L. ___________________________ -'
10-TOO-E-D......
ETE-CT-IQN-,'
0194 - rev.
3-105
GAIN BOOST
I
SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
DESCRIPTION (Continued)
2400 bitls data communications over the 2-wire
switched telephone network is desired. Its high functionality, low powerconsumption, and efficient packaging simplify design requirements and increase system
reliability.
The SSI73K224L is designed to be a complete V.22bis
compatible modem on a chip. The complete modem
requires only the addition of the phone line interface, a
control microprocessor, and RS-232 level converterfor
a typical system. Many functions were included to
simplify implementation of typical modem designs. In
addition to the basic 2400 bitls QAM, 600/1200 bitls
DPSK and 300 bitls FSK modulator/demodulator sections, the device also includes SYNCH/ASYNCH
converters, scrambler/descrambler, call progress tone
detect, DTMF tone generator capabilities and handshake pattern detectors. V.22bis, V.22, V.21 and Bell
212N103 modes are supported (synchronous and
asynchronous) and test modes are provided for diagnostics. Most functions are selectable as options and
logical defaults are provided.
Demodulation is the reverse of the modulation process, with the incoming analog signal eventually
decoded into di-bits and converted back to a serial bit
stream. The demodulator also recovers the clock
which was encoded into the analog signal during
modulation.Demodulation occurs using either a
1200 Hz carrier (answer mode or ALB originate mode)
or a 2400 Hz carrier (originate mode or ALB answer
mode). Adaptive equalization is also used in DPSK
modes for optimum operation with varying line
conditions.
FSK MODULATOR/DEMODULATOR
OPERATION
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. The Bell 103 standard frequencies of 1270 and 1070 Hz (originate mark and
space) and 2225 and 2025 Hz (answer mark and space)
are used when this mode is selected. V.21 mode uses
980 and 1180 Hz (originate, mark and space) or 1650
and 1850 Hz (answer, mark and space). Demodulation
involves detecting the received frequencies and decoding them into the appropriate binary value. The rate
converter and scrambler/descrambler are automatically
bypassed in the FSK modes.
QAM MODULATOR/DEMODULATOR
PASSBAND FILTERS AND EQUALIZERS
The SSI 73K224L encodes incoming data into quadbits represented by 16 possible signal points with
specific phase and amplitude levels. The baseband
signal is then filtered to reduce intersymbol interference on the band limited telephone network. The
modulator transmits this encoded data using either a
1200 Hz (originate mode) or 2400 Hz (answer mode)
carrier. The demodulator, although more complex,
essentially reverses this procedure while also recovering the data clock from the incoming signal. Adaptive
equalization corrects for varying line conditions by
automatically changing filter parameters to compensate for line characteristics.
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band signals. Amplitude
and phase equalization are necessary to compensate
for distortion of the transmission line and to reduce
intersymbol interference in the band limited receive
signal. The transmit signal filtering corresponds to a
75% square root of raised Cosine frequency response
characteristic.
DPSK MODULATOR/DEMODULATOR
The SSI 73K224L modulates a serial bit stream into
di-bit pairs that are represented by four possible phase
shifts as prescribed by the Bell 212NV.22 standards.
The base-band signal is then filtered to reduce intersymbol interference on the band limited 2-wire PSTN
line. Transmission occurs on either a 1200 Hz (originate mode) or 2400 Hz carrier (answer mode).
ASYNCHRONOUS MODE
The Asynchronous mode is used for communication
with asynchronous terminals which may communicate
at 600,1200, or 2400 biVs + 1%, -2.5% even though the
modem's output is limited to the nominal bit rate ±.01 %
in DPSK and QAM modes. When transmitting in this
mode the serial data on the TXD input is passed
through a rate converter which inserts or deletes stop
bits in the serial bit stream in order to output a signal
that is the nominal bit rate ±.01%. This signal is then
routed to a data scrambler and into the analog modulator where quad-biVdi-bit encoding results in the out-
3-106
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
put signal. Both the rate converter and scrambler can
be bypassed for handshaking, and synchronous operation as selected. Received data is processed in
a similar fashion except that the rate converter now
acts to reinsert any deleted stop bits and output data to
the terminal at no greater than the bit rate plus 1%. An
incoming break signal (low through two characters) will
be passed through without incorrectly inserting a stop
bit.
The SYNC/ASYNC converter also has an extended
Overspeed mode which allows selection of an output
overspeed range of either +1% or +2.3%. In the extended Overspeed mode, stop bits are output at 718 the
normal width.
Both the SYNC/ASYNC rate converter and the data
descrambler are automatically bypassed in the FSK
modes.
SYNCHRONOUS MODE
Synchronous operation is possible only in the QAM or
DPSK modes. Operation is similar to that of the Asynchronous mode exceptthat data must be synchronized
to a provided clock and no variation in data transfer rate
is allowable. Serial input data appearing at TXD must
be valid on the rising edge of TXCLK.
TXCLK is an internally derived 1200 or 2400 Hz signal
in Internal mode and is connected internally to the
RXCLK pin in Slave mode. Receive data at the RXD pin
is clocked out on the falling edge of RXCLK. The
asynchlsynch converter is bypassed when Synchronous mode is selected and data is transmitted at the
same rate as it is input.
PARALLEL BUS INTERFACE
Eight 8-bit registers are provided for control, option
select, and status monitoring. These registers are
addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as seven consecutive memory locations. Six control registers are readlwrite memory. The
detect and ID registers are read only and cannot be
modified except by modem response to monitored
parameters.
SERIAL CONTROL INTERFACE
The serial Command mode allows access to the
SSI 73K324 control and status registers via a serial
control port. In this mode the AO, A 1, and A2 lines
provide register addresses for data passed through the
DATA pin under control of the RD and WR lines. A read
operation is initiated when the RD line is taken low. The
next eight cycles of EXCLK will then transfer out eight
bits of the selected addresss location LSB first. A write
takes place by shifting in eight bits of data LSB first for
eight consectuive cycles of EXCLK. WR is then pulsed
low and data transfer into the selected register occurs
on the rising edge of WR.
DTMF GENERATOR
The DTMF generator controls the sending of the sixteen standard DTM F tone pairs. The tone pair sent is
determined by selecting TRANSMIT DTMF (bit D4)
and the 4 DTMF bits (DO-D3) of the TONE register.
Transmission of DTMF tones from TXA is gated by the
TRANSMIT ENABLE bit of CRO (bit D1) as with all
other analog signals.
3-107
I
SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
PIN DESCRIPTION
POWER
NAME
TYPE
DESCRIPTION
GND
I
System Ground.
VDD
I
Power supply input, 5V -5% +10%. Bypass with .22 J..lF and 22 J..lF capacitors
to GND.
VREF
0
An internally generated reference voltage. Bypass with .22 J..lF capacitor to
GND.
ISET
I
Chip current reference. Sets bias current for op-amps. The chip current is set
by connecting this pin to VDD through a 2 MQ resistor. Iset should be bypassed
to GND wtth a .22 J..lF capacttor.
PARALLEL MICROPROCESSOR INTERFACE
ALE
I
Address latch enable. The falling edge of ALE latches the address on ADOAD2 and the chip select on CS.
ADOAD7
1/0 I
Tristate
Addressldata bus.These bidirectional tri-state multi-plexed lines carry information to and from the internal registers.
CS
I
Chip select. A low on this pin allows a read cycle or a write cycle to occur. ADOAD7 will not be driven and no registers will be written if CS (latched) is not
active. CS is latched on the falling edge of ALE.
ClK
0
Output clock. This pin is selectable under processor control to be either the
crystal frequency (for use as a processor clock) or 16 x the data rate for use
as a baud rate clock in QAM/DPSK modes only. The pin defaults to the crystal
frequency on reset.
INT
0
Interrupt. This open drain weak pullup, output signal is used to inform the
processor that a detect flag has occurred. The processor must then read the
detect register to determine which detect triggered the interrupt. INTwill stay
active until the processor reads the detect register or does a full reset.
RD
I
Read. A low requests a read of the SSI 73K224l internal registers. Data
cannot be output unless both RD and the latched CS are active or low.
RESET
I
Reset. An active high Signal on this pin will put the chip into an inactive state.
All control register bits (CRO, CR1, CR2, CR3, Tone) will be reset. The output
of the ClK pin will be set to the crystal frequency. An internal pull down resistor
permits power on reset using a capacitor to VDD.
WR
I
Write. A low on this informs the SSI73K224l that data is available on ADO-AD7
for writing into an internal register. Data is latched on the rising edge of WR.
No data is written unless both WR and the latched CS are active (low).
Note: The serial control mode is provided in the parallel versions by tying ALE high and CS low. In this
configuration AD7 becomes DATA and ADO, AD1 and AD2 become AD, A1 and A2, respectively.
3-108
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
DTE USER INTERFACE
DESCRIPTION
NAME
TYPE
EXCLK
I
External Clock. This signal is used in synchronous transmission when the
external timing option has been selected. In the external timing modethe rising
edge of EXCLK is used to strobe synchronous transmit data available on the
TXD pin. Also used for serial control interface.
RXCLK
OfTristate
Receive Clock. Tri-stateable. The falling edge of this clock output is coincident
with the transitions in the serial received data output. The rising edge of
RXCLK can be used to latch QAM or DPSK valid output data. RXCLK will be
active as long as a carrier is present.
0
Received Digital Data Output. Serial receive data is available on this pin. The
data is always valid on the rising edge of RXCLK when in synchronous mode.
RXD will output constant marks if no carrier is detected.
OfTristate
Transmit Clock. Tri-stateable. This signal is used in synchronous transmission
to latch serial input data on the TXD pin. Data must be provided so that valid
data is available on the rising edge of the TXCLK. The transmit clock is derived
from different sources depending upon the synchronization mode selection. In
Internal Mode the clock is generated internally. In External Mode TXCLK is
phase locked to the EXCLK pin. In Slave Mode TXCLK is phase locked to the
RXCLK pin. TXCLK is always active.
I
Transmit Digital Data Input. Serial data for transmission is input on this pin. In
synchronous modes, the data must be valid on the rising edge of the TXCLK
clock. In asynchronous modes (2400/1200/600 bitls or 300 baud) no clocking
is necessary. DPSK data must be + 1%, -2.5% or +2.3%, -2.5 % in extended
overspeed mode.
RXD
TXCLK
TXD
ANALOG INTERFACE AND OSCILLATOR
RXA
I
TXA
a
Transmit analog output to the phone line.
XTL1
XTL2
I
1/0
These pins are forthe internal crystal oscillator requiring a 11.0592 MHz
parallel mode crystal. Two capaCitors from these pins to ground are also
required for proper crystal operation. Consult crystal manufacturer for proper
values. XTL2 can also be driven from an external clock.
Received modulated analog signal input from the phone line.
3-109
•
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
PIN DESCRIPTION (continued)
SERIAL MICROPROCESSOR INTERFACE
NAME
TYPE
DESCRIPTION
AO-A2
I
Register Address Selection. These lines carry register addresses and should
be valid during any read or write operation.
DATA
I/O
Serial Control Data. Data for a read/write operation is clocked in or out on the
falling edge of the EXCLK pin. The direction of data flow is controlled by the
RD pin. RD low outputs data. RD high inputs data.
RD
I
Read. A low on this input informs the SSI 73K322L that data or status
information is being read by the processor. The falling edge of the RD signal
will initiate a read from the addresses register. The RD signal must continue
for eight falling edges of EXCLK in order to read all eight bits of the referenced
register. Read data is provided LSB first. Data will not be output unless the RD
signal is active.
WR
I
Write. A low on this input informs the SSI73K322L that data or status information
has been shifted inthroughthe DATA pin and is availableforwritingto an internal
register. The normal procedure for a write is to shift in data LSB first on the DATA
pin for eight consecutive falling edges of EXCLK and then to pulse WR low. Data
is written on the rising edge of WR.
Note: In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the pins;
AD, A1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.
3-110
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO, A1 and
A2 address lines in serial mode, or the ADO, AD1 and
AD2 lines in parallel mode. The address lines are
latched by ALE. Register CRO controls the method by
which data is transferred over the phone line. CR1
controls the interface between the microprocessor and
the SSI73K224L internal state. DR is a detect register
which provides an indication of monitored modem
status conditions. TR, the tone control register, controls the DTM F generator, answer and guard tones and
RXD output gate used in the modem initial connect
sequence. CR2 is the primary DSP control interface
and CR3 controls transmit attenuation and receive
gain adjustments. All registers are read/write except
for DR and IDwhich are read only. Register control and
status bits are identified below:
REGISTER BIT SUMMARY
CONTROL
REGISTER
a
CONTROL
REGISTER
1
DETECT
REGISTER
TONE
CONTROL
REGISTER
CONTROL
REGISTER
CRO
CR1
000
001
MODULATION
OPTION
TRANSMIT
PATTERN
1
MODULATION
TYPE
1
MODULATION
TYPE
0
TRANSMIT
PATTERN
ENABLE
DETECT
INTERRUPT
a
SPECIAL
REGISTER
NOTE:
TRANSMIT
MODE
TRANSMIT
ENABLE
ANSWER!
ORIGINATE
CLK
CONTROL
RESET
TEST
MODE
1
TEST
MODE
CARRIER
DETECT
SPECIAL
TONE
DETECT
CALL
PROGRESS
DETECT
SIGNAL
QUAUTY
1
a
a
DR
010
RECEIVE
LEVEL
PATTERN
S1DET
RECEIVE
DATA
TR
011
RXD
OUTPUT
CONTROL
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF3
DTMF2
DTMF11
EXTENDED
OVERSPEED
DTMFO/GUARDI
ANSWER
CR2
100
TRANSMIT
S1
16 WAY
RESET
DSP
TRAIN
INHIBIT
EQUALIZER
ENABLE
CR3
101
3
TRANSMIT
ATTEN.
2
TRANSMIT
ATTEN.
1
TRANSMIT
ATTEN.
0
TXD
SOURCE
SQ
SELECT 1
SQ
SELECT 0
SR
101
ID
110
TRANSMIT
ATTEN.
10
REGISTER
BYPASS
SCRAMBLER
TRANSMIT
MODE
UNSCR
MARK
DETECT
2
CONTROL
REGISTER
3
TRANSMIT
MODE
2
ID
10
When a register containing reserved control
bits is written into, the reserved bits must be
programmed as O's.
3-111
•
SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
REGISTER ADDRESS TABLE
~~~~~~~ --------------~
OAM:
DPSK:
0=2400 B ITIS
0=1200 BITIS
1=600 BITIS
FSK: 0=103 MODE
I=V.2l
0010=EXT SYNCH
0011=SLAVESYNCH
0100=ASYCH 8 BITs/CHAR
0101=ASYCH 9 BITs/CHAR
0110=ASYCH 10 BITs/CHAR
0111=ASYCH 11 BITs/CHAR
lXOO=FSK
O=DISABLE
TXA OUTPUT
I=ENABLE
TXAOUTPUT
O=ANSWER
I=ORIGINATE
0=1800 HzG.T.
2225 Hz ANS TONE
GENERATED.
1=550 Hz G.T.
2100 Hz ANS TONE
GENERATED &
DETECTED (V.21. V22)
O=ACCESS CR3
I=ACCESS
SPECIAL
REGISTER
O=DSP IN
O=NORMAL
DEMOD MODE
DOTTING
1=S 1
1=DSP IN CALL
PROGRESS
MODE
OOXX=73K212L, 322L. 321 L
01 XX=73K221 L. 302L
10XX=73K222L
1100=73K224L
1110=73K324L
1101=73K312L
3-112
O=RX=TX
I=RX=16 WAY
O=DSP
INACTIVE
1=DSP
ACTIVE
O=ADAPTEO
ACTIVE
I=ADAPTEO
FROZEN
O=ADAPTEO
ININIT
1=ADAPT EO
OK TO ADAPT
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 0
CRO
000
04
07
06
05
MOOUL.
OPTION
MOOUL.
TYPE 1
MOOUL.
TYPE 0
BIT NO.
DO
01
03
02
01
DO
TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
ENABLE ORIGINATE
MOOE2
MODE 1
MOOEO
NAME
CONDITION
Answer/
Originate
0
Selects answer mode (transmit in high band, receive
in low band).
1
Selects originate mode (transmit in low band, receive in
high band).
0
Disables transmit output at TXA.
Transmit
Enable
DESCRIPTION
Enables transmit output at TXA.
1
Note: Transmit Enable must be set to 1 to allow
activation of Answer Tone or OTMF.
05 04 03 02
05,04,
03,02
Transmit
Mode
0
0
0
0
Selects power down mode. All functions disabled
except digital interface.
0
0
0
1
Internal synchronous mode. In this mode TXCLK is an
internally derived 600,1200 or 2400 Hz signal. Serial
input data appearing at TXO must be valid on the rising
edge of TXCLK. Receive data is clocked out of RXO on
the falling edge of RXCLK.
0
0
1
0
External synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 600,1200 or 2400 Hz clock
must be supplied externally.
0
0
1
1
Slave synchronous mode. Same operation as other
synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.
0
1
0
0
Selects asynchronous mode - 8 bits/character (1 start
bit, 6 data bits, 1 stop bit).
0
1
0
1
Selects asynchronous mode - 9 bits/character (1 start
bit, 7 data bits, 1 stop bit).
0
1
1
0
Selects asynchronous mode - 10 bits/character (1 start
bit, 8 data bits, 1 stop bit).
0
1
1
1
Selects asynchronous mode - 11 bits/character (1 start
bit, 8 data bits, Parity and/or 1 or 2 stop bits).
X
0
0
Selects FSK operation.
1
06 05
06,05
Modulation
Type
QAM
1
0
0
0
OPSK
0
1
FSK
3-113
•
SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 0
07
CRO
000
05
06
MODUL.
OPTION
BIT NO.
07
(Continued)
MODUL.
TYPE 1
04
02
03
01
DO
MODUL. TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
TYPE 0
MODE 2
MODE 1
ENABLE ORIGINATE
MODE 0
CONDITION
NAME
Modulation
Option
DESCRIPTION
0
OAM selects 2400 bit/so DPSK selects 1200 bit/so
FSK selects 103 mode.
1
DPSK selects 600 bit/so
FSK selects V.21 mode.
CONTROL REGISTER 1
CR1
001
BIT NO.
07
06
05
TRANSMIT
PATIERN
1
TRANSMIT
PATIERN
0
ENABLE
DETECT
INT.
NAME
CONDITION
04
02
01
DO
RESET
TEST
MODE
1
TEST
MODE
0
03
BYPASS
ClK
SCRAMB CONTROL
DESCRIPTION
01 DO
01, DO
02
03
Test Mode
Reset
Clock Control
0
0
Selects normal operating mode.
0
1
Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiverto
use the same carrier frequency as the transmitter. To
squelch the TXA pin, TRANSMIT ENABLE bit as well
as Tone Reg bit 02 must be low.
1
0
Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is ignored.
1
1
Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit data carrrier at
TXA pin.
0
Selects normal operation.
1
Resets modem to power down state. All control register
bits (CRO, CR1, CR2, CR3 and Tone) are resetto zero
except CR3 bit 02. The output of the clock pin will be
set to the crystal frequency.
0
Selects 11.0592 MHz crystal echo output at ClK pin.
1
Selects 16 X the data rate, output at ClK pin in DPSK/
OAM modes only.
3-114
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 1
CR1
001
D7
D6
D5
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INT.
SIT NO.
D4
D5
(Continued)
D4
D2
D1
DO
RESET
TEST
MODE
1
TEST
MODE
0
D3
BYPASS
ClK
SCRAMB CONTROL
NAME
CONDITION
Bypass
Scrambler
0
Selects normal operation. DPSK and QAM data is passed
through scrambler.
1
Selects Scrambler Bypass. Bypass DPSK and QAM
data is routed around scrambler in the transmit path .
0
Disables interrupt at INT pin. All interrupts are normally
disabled in power down mode.
1
Enables INT output. An interrupt will be generated with
a change in status of DR bits D1-D4 and D6. The
answer tone and call progress detect interrupts are
masked when the TX enable bit is set. Carrier detect is
masked when TX DTMF is activated. All interrupts will
be disabled if the device is in power down mode.
Enable Detect
Interrupt
DESCRIPTION
D7 D6
D7,D6
Transmit
Pattern
0
0
Selects normal data transmission as controlled by the
state of the TXD pin.
0
1
Selects an alternating mark/space transmit pattern for
modem testing and handshaking. Also used for S1
pattern generation. See CR2 bit D4.
1
0
Selects a constant mark transmit pattern.
1
1
Selects a constant space transmit pattern.
DETECT REGISTER
D7
DR
010
RECEIVE
S1
lEVEL
PATTERN
INDICATOR DETECT
SIT NO.
DO
D1
D6
NAME
D5
D4
D3
RECEIVE
DATA
UNSCR.
MARK
DETECT
CARR.
DETECT
CONDITION
D2
D1
DO
SIGNAL
ANSWER
CAll
TONE
PROG.
QUALITY
DETECT DETECT INDICATOR
DESCRIPTION
Signal Quality
Indicator
0
Indicates normal received signal.
1
Indicates low received signal quality (above average
error rate). Interacts with special register bits D2, D1.
Call Progress
Detect
0
No call progress tone detected.
1
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in
the normal 350 to 620 Hz call progress bandwidth.
3-115
•
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
DETECT REGISTER (Continued)
07
DR
010
06
RECEIVE
S1
LEVEL
PAITERN
INDICATOR DETECT
BIT NO.
02
04
03
02
01
DO
RECEIVE
DATA
UNSCR.
MARK
DETECT
CARR.
DETECT
ANSWER
TONE
DETECT
CALL
PROG.
SIGNAL
QUALITY
INDICATOR
NAME
CONDITION
Answer Tone
Received
0
No answer tone detected.
1
In Call Init mode, indicates detection of 2225 Hz
answer tone in Bell mode (TR bit 00=0) or 2100 Hz if
in CCIIT mode (TR bit 00=1). The device must be in
originate mode for detection of answer tone. Both
answer tones are detected in demod mode.
Carrier
Detect
0
No carrier detected in the receive channel.
1
Indicated carrier has been detected in the received
channel.
Unscrambled
Mark
Detect
0
No unscrambled mark.
1
Indicates detection of unscrambled marks in the
received data. Should be time qualified by software.
03
04
05
DESCRIPTION
05
Receive
Data
06
S1 Pattern
Detect
0
No S1 pattern being received.
1
S1 pattern detected. Should be time qualified by software. S1 pattern is defined as a double di-bit (0011 00 .. )
unscrambled 1200 biVs DPSK signal. Pattern must be
aligned with baud clock to be detected.
Receive Level
Indicator
0
Received signal level below threshold, (typical::: -25
dBmO); can use receive gain boost (+18 dB).
1
Received signal above threshold.
07
Continuously outputs the received data stream. This
data is the same as that output on the RXD pin, but it
is not disabled when RXD is tri-stated.
TONE REGISTER
TR
011
07
06
RXD
OUTPUT
CONTR.
TRANSMIT
GUARD
TONE
BIT NO.
DO
(Continued)
NAME
DTMF 01
Answerl
Guard Tone
05
04
TRANSMIT TRANSMIT
DTMF
ANSWER
TONE
CONDITION
03
DTMF3
02
01
DO
DTMF 11
DTMF 01
DTMF2 EXTENDED ANSWERI
OVERGUARD
SPEED
DESCRIPTION
06 05 04 DO
DO interacts with bits 06, OS, and 04 as shown.
X
X
1
X
Transmit DTMF tones.
X
1
0
0
Select Bell mode answer tone. Interacts with DR bit 02
and TR bit 05.
X
1
0
1
Select CCIIT mode answer tone. Interacts with DR bit
02 and TR bit 05.
3-116
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
TONE REGISTER (Continued)
TR
011
07
06
RXO
OUTPUT
CONTR.
TRANSMIT
GUARO
TONE
BIT NO.
00
05
NAME
CONDITION
OTMF 0/
Answer!
Guard Tone
06 05 04 00
1
1
OTMF 1/
Extended
Overspeed
03
02
OTMF3 OTMF 2/
4WIRE
FOX
01
00
DTMF 1/
OTMF 0/
EXTENDED ANSWER/
OVERGUARO
SPEED
DESCRIPTION
00 interacts with bits 06, 05, and 04 as shown.
0
0
0
Select 1800 Hz guard tone.
0
0
1
Select 550 Hz guard tone.
04 01
01
04
TRANSMIT TRANSMIT
ANSWER
OTMF
TONE
01 interacts with 04 as shown.
0
0
Asynchronous QAM or OPSK +1.0% -2.5%. (normal)
0
1
Asynchronous QAM or OPSK +2.3% -2.5%. (extended
overspeed)
04 02
02
OTMF 2!
4WIRE
FOX
0
0
Selects 2 wire duplex or half duplex
0
1
02 selects 4 wire full duplex in the modulation mode
selected. The receive path corresponds to the ANS/
ORIG bitCRO 00 intermsof highorlowbandselection.
The transmitter is in the same band as the receiver, but
does not have magnitude filtering or equalization on its
signal as in the receive path.
3-117
•
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
TONE REGISTER (Continued)
TR
011
07
06
RXD
OUTPUT
CONTR.
TRANSMIT
GUARD
TONE
BIT NO.
NAME
04
05
TRANSMIT TRANSMIT
DTMF
ANSWER
TONE
CONDITION
02
03
01
DO
DTMF 11 DTMF 01
EXTENDED ANSWERI
OVERGUARD
SPEED
DTMF3 DTMF 21
4WIRE
FOX
DESCRIPTION
03 02 01 DO
03,02,
01,00
DTMF 3,
2,1,0
0
1
0
1
0
1
o1
Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTMF and TX enable bit (CRO, bit
01) is set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT
04
TX DTMF
(Transmit
DTMF)
DTMFCODE
03 02 01 DO
TONES
LOW HIGH
1
0
0
0
1
697
1209
2
0
0
1
0
697
1336
3
0
0
1
1
697
1477
4
0
1
0
0
770
1209
5
0
1
0
1
770
1336
6
0
1
1
0
770
1477
7
0
1
1
1
852
1209
8
1
0
0
0
852
1336
9
1
0
0
1
852
1477
0
1
0
1
0
941
1336
"
1
0
1
1
941
1209
#
1
1
0
0
941
1477
A
1
1
0
1
697
1633
B
1
1
1
0
770
1633
C
1
1
1
1
852
1633
0
0
0
0
0
941
1633
0
Disable OTMF.
1
Activate DTMF. The selected OTMF tones are transmitted continuously when this bit is high. TX DTMF
overrides all other transmit functions.
Note: OTM FO - DTM F2 should be set to an appropriate state after DTM F dialing to avoid unintended operation.
3-118
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
TONE REGISTER
(Continued)
07
06
05
TR
011
RXO
OUTPUT
CONTA.
TRANSMIT
GUARD
TONE
BIT NO.
NAME
04
TRANSMIT TRANSMIT
ANSWER
OTMF
TONE
Transmit
Answer Tone
06
07
01
OTMF3 OTMF 21
4WIRE
FOX
DO
DTMF 11
OTMF 01
EXTENDED ANSWERI
OVERGUARO
SPEED
DESCRIPTION
CONDITION
05 04 00
05
02
03
05 interacts with bits 04 and DO as shown. Also
interacts with DR bit 02 in originate mode. See Detect
Register description.
0
0
X
Disables answer tone generator.
1
0
0
In answer mode, a Bell 2225 Hz tone is transmitted
continuously when the Transmit Enable bit is set.
1
0
1
Likewise, a CCITT 21 00 Hz answertone is transmitted.
Transmit
Guard Tone
0
Disables guard tone generator.
1
Enables guard tone generator. (See DO for selection of
guard tones.) Bit 04 must be zero.
RXO Output
Control
0
Enables RXO pin. Receive data will be output on RXO.
1
Disables RXO pin. The RXO pin reverts to a high
impedance with internal weak pull-up resistor.
CONTROL REGISTER 2
CR2
100
BIT NO.
DO
01
02
03
07
06
05
04
0
SPEC
REG
ACCESS
CALL
INIT
TRANSMIT
S1
03
02
01
DO
16 WAY
RESET
OSP
TRAIN
INHIBIT
EQUALIZER
ENABLE
NAME
CONDITION
Equalizer
Enable
0
The adaptive equalizer is in its initialized state.
1
The adaptive equalizer is enabled. This bit is used in
handshakes to control when the equalizer should calculate its coefficients.
Train
Inhibit
0
The adaptive equalizer is active.
1
The adaptive equalizer coefficients are frozen.
RESET OSP
0
The OSP is inactive and all variables are initialized.
1
The OSP is running based on the mode set by other
control bits
0
The receiver and transmitter are using the same decision plane (based on the Modulator Control Mode).
1
The receiver, independent of the transmitter, is forced
into a 16 point decision plane. Used for QAM handshaking.
16Way
DESCRIPTION
3-119
I
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
CONTROL REGISTER 2
CR2
100
BIT NO.
04
(Continued)
07
06
05
04
0
SPEC
REG
ACCESS
CALL
INIT
TRANSMIT
S1
NAME
CONDITION
Transmit
S1
0
Callinit
0
1
06
Special
Register
Access
0
1
07
Not used at this time
0
02
01
DO
16WAY
RESET
OSP
TRAIN
INHIBIT
EQUALIZER
ENABLE
DESCRIPTION
The transmitter when placed in alternating mark/space
mode transmits 0101 ...... scrambled or not dependent
on the bypass scrambler bit.
When this bit is 1 and only when the transmitter is placed
in alternating mark/space mode by CR 1 bits 07, 06, and
in OPSK or QAM, an unscrambled repetitive double dibit
pattern of 00 and 11 at 1200 biVs (S1) is sent.
The OSP is setup to do demodulation and pattern
detection based on the various mode bits. Both answer
tones are detected in demod mode concurrently; TRDO is ignored.
The OSP decodes unscrambled mark, answer tone
and call progress tones.
Normal CR3 access.
Setting this bit and addressing CR3 allows access to
the SPECIAL REGISTER. See the SPECIAL REGISTER for details.
Only write zero to this bit.
1
05
03
CONTROL REGISTER 3
CR3
101
03,02,
01,00
Transmit
Attenuator
o
0
0
0-
Sets the attenuation level of the transmitted signal
in 1dB steps. The default (03-00=0100) is for a transmit level of -10 dBmO on the line with the recommended hybrid transmit gain. The total range is 16 dB.
04
Receive
Gain Boost
Boost is in the path. This boost does not change
reference levels. It is used to extend dynamic range by
compensating for internally generated noise when
receiving weak signals. The receive level detect signal
and knowledge of the hybrid and transmit attenuator
setting will determine when boost should be enabled.
3-120
SSI73K224L
V.22bis/V.22/V.21, Bell 212A!1 03
Single-Chip Modem
SPECIAL REGISTER
SR
101
03
02
D1
TXO
SOURCE
SIGNAL
QUALITY
LEVEL
SELECT1
SIGNAL
QUALITY
LEVEL
SELECTO
06
TXBAUO CLK
TXBAUO clock is the transmit baud-synchronous clock that can be used to
synchronize the input of arbitrary quad/di-bit patterns. The rising edge of
TXBAUO signals the latching of a baud-worth of data internally. Synchronous
data to be entered via the TXOALT bit, CR3 bit 07, should have data
transitions that start 1/2 bit period delayed from the TXBAUO clock edges.
05
RXUNOSCR
DATA
This bit outputs the data received before going to the descrambler. This is
useful for sending special unscrambled patterns that can be used for
signaling.
03
TXO SOURCE
This bit selects the transmit data source; either the TXO pin if ZERO or the
TXOALT if this bit is a ON E. The TRANSM IT PATTERN bits 07 and 06 in CR 1
override either of these sources.
SIGNAL
OUALITY
LEVEL
SELECT
The signal quality indicator is a logical ZERO when the signal received is
acceptable for low error rate reception. It is determined by the value of the
Mean Squared Error (MSE) calculated in the decisioning process when
compared to a given threshold. This threshold can be set to four levels of error
rate. The SOl bit will be low for good or average connections. As the error rate
crosses the threshold setting. the SOl bit will toggle at a 1.66 ms rate. Toggling
will continue until the error rate indicates that the data pump has lost
convergence and a retrain is required. At that point the SOl bit will be a ONE
constantly. The SOl bit and threshold selection are valid for QAM and
OPSK only and indicates typical error rate.
02, 01
o
10.4
BER
NOTE: This register is "mapped" and is accessed by setting CR2.bit 06 to a ONE and addressing CR3. This
register provides functions to the 73K224L user that are not necessary in normal communications.
Bits 07-04 are read only, while 03-00 are read/write. To return to normal CR3 access, CR2 bit 06
must be returned to a ZERO.
3-121
I
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
ID REGISTER
ID
110
D7
D6
D5
D4
ID
3
ID
2
ID
1
ID
0
BIT NO.
NAME
D7, D6,
Device
Identification
Signature
D5,D4
CONDITION
DESCRIPTION
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
VDD Supply Voltage
7V
Storage Temperature
-65 to 150°C
Soldering Temperature (10 sec.)
260°C
Applied Voltage
-0.3 to VDD+0.3V
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITIONS
VDD Supply voltage
MIN
NOM
MAX
UNITS
4.5
5
5.5
V
2
2.2
MQ
External Components (Refer to Application section for placement.)
0.22
VREF Bypass capacitor
(VREF to GND)
Bias setting resistor
(Placed between VDD and ISET pins)
ISET Bypass capacitor
(ISET pin to GND)
0.22
JlF
VDD Bypass capacitor 1
(VDD to GND)
0.22
JlF
VDD Bypass capacitor 2
(VDD to GND)
22
XTL 1 Load Capacitance
Depends on crystal requirements
XTL2 Load Capacitance
Clock Variation
1.8
TA, Operating Free-Air
Temperature
3-122
JlF
18
39
pF
27
pF
-0.01
+0.01
%
-40
85
°c
Depends on crystal requirements
(11.0592 MHz) Crystal or external clock
JlF
18
SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VOO = recommended range unless otherwise noted.)
PARAMETER
CONDITIONS
100, Supply Current
ClK = 11.0592 MHz
MIN
NOM
MAX
UNITS
18
25
mA
5
mA
0.8
V
ISET Resistor = 2 MQ
1001, Active
Operating with crystal oscillator,
1002, Idle
< 5 pF capacitive load on ClK pin
3
Digital Inputs
Vll, Input low Voltage
VIH, Input High Voltage
All Inputs except Reset
XTl1, XTl2
2.0
VOO
V
Reset, XTl1 , XTl2
3.0
VOO
V
100
f.lA
IIH, Input High Current
VI = VOO
Ill, Input low Current
VI = OV
Reset Pull-down Current
Reset = VOO
-200
f.lA
2
50
f.lA
2.4
VOO
V
0.4
V
-50
f.lA
Maximum permitted load
25
pF
All Oigitallnputs
10
pF
Digital Outputs
VOH, Output High Voltage
10= 10H Min
lOUT = -0.4 mA
VOL, Output low Voltage
10 = lOUT = 1.6 mA
RXO Tri-State Pull-up Curr.
RXO = GNO
-2
Capacitance
Maximum Capacitive load
ClK
Input Capacitance
3-123
I
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
QAM/DPSK Modulator
Carrier Suppression
Measured at TXA
Output Amplitude
TX scrambled marks
ATT =0100 (default)
35
-11.5
dB
-10.0
-9
dBmO
FSK Modulator/Demodulator
Output Freq. Error
ClK = 11.0592 MHz
-.31
Transmit level
ATT = 0100 (Default)
Transmit Dotting Pattern
-11.5
TXA Output Distortion
All products through BPF
Output Bias Distortion
at RXD
Dotting Pattern measured at RXD
Receive level -20 dBm, SNR 20 dB
Output Jitter at RXD
Integrated for 5 seconds
Sum of Bias Distortion and
Output Jitter
Integrated for 5 seconds
+.20
%
-9
dBmO
-45
dB
-10
+10
%
-15
+15
%
-17
+17
%
-9
dBmO
-40
dB
+0.25
%
-10
-8
dBmO
-8
-6
dBmO
-10.0
Answer Tone Generator (2100 or 2225 Hz)
Output Amplitude
ATT = 0100 (Default level)
-11.5
-10
Not in V.21
Output Distortion
DTMF Generator
Distortion products in receive band
Not in V.21
Freq. Accuracy
-0.03
=0100, DPSK Mode
= 0100, DPSK Mode
Output Amplitude
Low Band, ATT
Output Amplitude
High Band, ATT
Twist
High-Band to Low-Band, DPSK Mode
1.0
3.0
dB
Refer to Performance Curves
-43
-3.0
dBmO
-34
0
dBmO
Receiver Dynamic Range
Call Progress Detector
Detect level
2.0
In Call Init mode
460 Hz test signal
Reject level
-40
dBmO
Delay Time
-70 dBmO to -30 dBmO STEP
25
ms
Hold Time
-30 dBmO to -70 dBmO STEP
25
ms
NOTE: Parameters expressed in dBmO refer to the following definition:
o dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
3-124
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/103
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
CONDITIONS
PARAMETERS
Receive Gain
Carrier Detect
Threshold
All Modes
Hysteresis
All Modes
Delay Time
FSK
DPSK
OAM
Hold Time
FSK
DPSK
OAM
Answer Tone Detectors
MIN
-48
UNITS
-43
dBmO
ms
2
70 dBmO to -6 dBmO
25
37
70 dBmO to -40 dBmO
25
37
ms
-70 dBmO to -6 dBmO
7
17
ms
-70 dBmO to -40 dBmO
7
17
ms
-70 dBmO to -6 dBmO
25
37
ms
-70 dBmO to -40 dBmO
25
37
ms
-6 dBmO to -70 dBmO
25
37
ms
-40 dBmO to -70 dBmO
15
30
ms
-6 dBmO to -70 dBmO
20
29
ms
-40 dBmO to -70 dBmO
14
21
ms
-6 dBmO to -70 dBmO
25
32
ms
-40 dBmO to -70 dBmO
18
28
ms
-48
-43
dBmO
6
50
ms
6
50
ms
DPSK Mode
Cailinit Mode, 2100 or 2225 Hz
Hold Time
Pattern Detectors
MAX
=On for lower input level measurements
Detect Level
Detect Time
NOM
DPSK Mode
S1 Pattern
Delay Time
For signals from -6 to -40 dBmO,
10
55
ms
Hold Time
-6 to -40 dBmO, Demod Mode
10
45
ms
Delav Time
For signals from -6 to -40
10
45
ms
Hold Time
cailinit Mode
10
45
ms
Unscrambled Mark
Receive Level Indicator
-22
Detect On
Valid after Carrier Detect
1
DPSK Mode
-28
dBmO
4
7
ms
200
300
Output Smoothing Filter
Output Impedance
TXA pin
Output load
TXA pin; FSK Single
Tone out for THO = -50 dB
in .3 to 3.4 kHz range
Q
KQ
10
50
pF
Maximum Transmitted
4 kHz, Guard Tones off
-35
dBmO
Energy
10 kHz, Guard Tones off
-55
dBmO
12 kHz, Guard Tones off
-65
dBmO
3-125
I
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
Anti Alias Low Pass Filter
Out of Band Signal Energy
(Defines Hybrid TransHybrid loss requirements)
Level at RXA pin with receive
Boost Enabled
Scrambled data at 2400 bitls
in opposite band
Sinusoids out of band
-14
dBm
-9
dBm
Transmit Attenuator
Range of Transmit Level
Default AIT=0100 (-10 dBmO) 1111-0000
Step Accuracy
-21
-6
dBmO
-0.15
+0.15
dB
300
n
1.5
mVrms
±7
Hz
+0.02
%
Output Impedance
200
Clock Noise
TXA pin; 153.6 kHz
Carrier Offset
Capture Range
Originate or Answer
±5
Recovered Clock
Capture Range
% of frequency (originate or
answer)
-0.02
Guard Tone Generator
Tone Accuracy
550 Hz
+1.2
1800 Hz
-0.8
%
Tone Level
550 Hz
-4.5
-3.0
-1.5
dB
(Below QAM/DPSK
Output)
1800 Hz
-7.5
-6.1
-4.5
dB
Harmonic Distortion
550 Hz
-50
dB
(700 to 2900 Hz)
1800 Hz
-50
dB
Timing (Refer to Timing Diagrams)
Parallel Mode
TAL
CS/Addr. setup before ALE Low
30
ns
TLA
CS/Addr. hold after ALE Low
6
ns
TLC
ALE Low to RD/WR Low
40
ns
TCL
RD/WR Control to ALE High
10
ns
TRD
Data out from RD Low
TLL
ALE width
TRDF
Data float after RD High
TRW
RDwidth
90
25
40
70
3-126
ns
ns
ns
ns
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
Parallel Mode (Continued)
TWW
WR width
70
ns
TOW
Data setup before WR High
70
ns
TWO
Data hold after WR High
20
ns
TRCK
Clock High after RD Low
250
TAR
Address setup before RD Low
TRA
Address hold after RD Low
TRD
RD to Data valid
TRDF
Data float after RD High
TCKDR
Read Data out after Falling
Edge of EXCLK
Serial Mode
T1
ns
ns
0
350
ns
300
ns
40
ns
300
ns
TWW
WR width
350
ns
TAW
Address setup before WR Low
50
ns
TWA
Address hold after Rising
Edge of WR
50
ns
TCKDW
Write Data hold after Falling
Edge of EXCLK
200
ns
TCKW
WR High after Falling
Edge of EXCLK
330
TDCK
Data setup before Falling
Edge of EXCLK
50
ns
T1, T2
Minimum Period
500
ns
NOTE: T1 and T2 are the low/high periods, respectively, of EXCLK in serial mode.
3-127
T1 + T2
ns
I
SSI73K224L
V.22bis/V.22N.21, Bell 212A/1 03
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
~
~
ALE
F4c
...
TRW
TlC-"-
-+-
AD
TCl -"-
-"-
,f-
TlC
WIT
TLA
cs
TWW
--K
.f~
TAL
ADDRESS
~-
TRD
i.!.I
~D
TRDF
~
TOW
~READDATA~
-~-
-1-
ADDRESS
-~-
EXClK
AO-A2
DATA
WRITE TIMING DIAGRAM (SERIAL VERSION)
---41
T2
14--
EXCLK
---+--------------------H:
DATA
3-128
.J
~WRITEDATA}-
READ TIMING DIAGRAM (SERIAL VERSION)
AO-A2
J
-\L
ADO-AD7
.L
SSI73K224L
V.22bis/V.22/V.21 , Bell 212A/1 03
Single-Chip Modem
SSI 73K224L BER vs S/N-DPSK LOW BAND
'\
1\'\
\[\
II
LOW BAND RECEIVE
-30dBm
DPSK OPERATION
1200 BITIS
SSI 73K224L BER vs S/N-DPSK HIGH BAND
t
'\'\
\\
I~\
10-3
10-3
1\\
1\ \
Q
\~M ........
~
a:
a:
0 10-4
a:
a:
>---l
LU
!;i:
a:
a:
0
a:
a:
1\ \
LU
t::
CD
-1
..... v
Cl, C2, FLAT
I
~\
v \\
10-5
r--
rc~
1\1
1'---'
\\
\
\\
4
12
10
14
16
4
10-3
\\
~
IIII "'.~"'~'"
-30dBm
OAM OPERATION
2400 BITtS
/'
LU
I
HIGH BAND RECEIVE ,
-30 dBm
OAM OPERATION
2400 BITtS
~~
I~
10-3
-GJ
\
Irr;-~
IL-..---'
LU
~
a:
a:
0 10-4
a:
a:
10-5
.........
l\\
~~
\~
3002
LU
L
""t ~.J
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CD
:\
-
~L C 2 J
~' IL
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t--.. .\ \'l
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10-5
11\
\\
_\~
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\
\ ~
l\
8
10
12
14
16
16
\
,\
~~ r--r--
1\
~
co
14
SSI73K224L
BER vs S/N-QAM-HIGH BAND
~
L:~ ......... ~
t::
12
SIGNAL TO NOISE (dB)
SSI73K224L
BER vs S/N-QAM-LOW BAND
,
10
8
SIGNAL TO NOISE (dB)
\
I
~\
\ 1\
10-6
Cl, 3002, FLAT
........ V
\
t::
\
~
a:
a:
0 10-4
a:
a:
t
\'
10-4
co
\1\
1
J
\1\
LU
~
10-5
LU
-30dBm
DPSK OPERATION
1200 BITIS
\
\
LU
I HIGH BAND RECEIVE
\l\
\1\
18
10
20
12
14
16
SIGNAL TO NOISE (dB)
SIGNAL TO NOISE (dB)
3-129
18
20
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
SSI73K224L BER vs CARRIER OFFSET
1
I
_L
I HIGH BAND RECEIVE
-30dBm
OAM OPERATION
t
2400 BITtS
10""
H
I
C217dBSIN
\
"
~
-12
-8
-4
I
300217 dB SIN
I
\
~
:::::: r-- r--
4
12
CARRIER OFFSET (HZ)
3-130
SSI73K224L
V.22bis/V.22/V.21, Bell 212A/1 03
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
(Top View)
GND
CLK
AD
XTl1
RXA
XTL2
VREF
'::::;::::
RXA
ADO
VREF
AD1
ISET
RESET
AD2
RXClK
RESET
ISET
AD3
RXD
RXCLK
AD4
TXD
27
~::t::::tAM'P.tlMt: :,:::~
26
bIIt?Mtb.IBi@wr:'
32-Lead PLCC
10
RXD
AD5
"OS
TXD
AD6
EXCLK
11
EXClK
AD7
TXClK
12
TXClK
ALE
IN''F
lNi
WR
TXA
TXA
RD
VDD
13
15
14
NlC [
16
17
18
19
17
18
19
600-Mil
28-Pin DIP
400-Mil
22-Pin DIP
32, 44-Pin PLCC
~
IUJ
!l2
~
...J
Q
z
52 51
~ Cx
a: a:
Q
z
Q
z
cx
I-
Q
Z
Q
Z
co
CJ)
<.)
~
...J
...J
<.)
~ Q x
UJ
Z
0
C
«
I-
~
,::j
xI-
xl-
c
G
Z
«
x
a:
a:
>
28
27
26
...J
50 49 48 47 46 45 44 43 42 41
N/c
u-
~
<.)
UJ
AD1
25
RESET
24
ISET
23
RXClK
22
RXD
21
TXD
INTB
N,c
N/c
RXA
TXA
N,c
N/c
N,c
N/c
GND
VDD
N/c
31
ClK
N/C
AD6
20
cs
N/C
AD7
19
EXClK
N,c
RDB
XTAL1
WRB
XTAL2
N/C
N,c
ALE
15 16 17 18 19 20 21
22 23 24 25
14
15
I~ ~
c
c
>
13
~
«
16
17
«
X
~
I-
18
~
...J
~
I-
28-Pin PLCC
t-0 cN c'" c c c45 dB.
PARALLEL BUS INTERFACE
Four a-bit registers are provided for control, option
select and status monitoring. These registers are ad3-135
dressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The detect register is read only
and cannot be modified except by modem response to
monitored parameters. The parallel bus interface is not
available in the 22-pin package.
SERIAL COMMAND INTERFACE
The serial command interface allows access to the
SSI 73K302L control and status registers via a serial
command port. In this mode the AO ,A1 and A2lines
provide register addresses for data passed through the
data pin under control of the RD and WR lines. A read
operation is initiated when the RD line is taken low. The
first bit is available after RD is brough low and the next
seven cycles of EXCLK will then transfer out seven bits
of the selected address location LSB first. A write takes
place by shifting in eight bits of data LSB first for eight
consecutive cycles of EXCLK. WR is then pulsed low
and data transfer into the selected register occurs on
the rising edge of WR.
SPECIAL DETECT CIRCUITRY
The special detect circuitry monitors the received analog signal to determine status or presence of carrier,
answer tone and weak received signal (long loop
condition), special tones such as FSK marking and the
900 Hz soft carrier turn-off tone are also detected. A
highly frequency selective call progress detector provides adequate discrimination to accurately detect
lower quality call progress signals.
DTMF GENERATOR
The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode
is selected using the tone register and the transmit
enable (CRO bit 01) is changed from 0 to 1.
SOFT CARRIER TURN-OFF TONE GENERATOR
The soft carrier turn-off tone generator will output a
900 Hz tone. When activated in Bell 202 main channel
transmit mode, the output signal will shift to 900 Hz,
maintaining phase continuity during the transition.
3
SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
PIN DESCRIPTION
POWER
NAME
28·PIN
22·PIN
TYPE
DESCRIPTION
GND
28
1
I
System Ground.
VDD
15
11
I
Power supply input, 5V ±10%. Bypass with .1 and 22 J.lF
capacitors to GND.
VREF
26
21
0
An internally generated reference voltage. Bypass with
.1 J.lF capacitor to GND.
ISET
24
19
I
Chip current reference. Sets bias current forop-amps. The
chip current is set by connecting this pin to VDD through a
2 MQ resistor. ISET should be bypassed to GND with a
.1 J.lF capacitor.
PARALLEL MICROPROCESSOR INTERFACE
12
-
I
Address latch enable. The falling edge of ALE latches the
address on ADO-AD2 and the chip select on CS.
4-11
-
110
Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
registers.
CS
20
-
I
Chip select. A low on this pin during the falling edge of ALE
allows a read cycle or a write cycle to occur. ADO-AD? will
not be driven and no registers will be written if CS (latched)
is not active. The state of CS is latched on the falling edge
of ALE.
ClK
1
2
0
Output clock. This pin is selectable under processor control
to be either the crystal frequency (for use as a processor
clock) or 16 x the data rate for use as a baud rate clock in
DPSK mode only. The pin defaults to the crystal frequency
on reset.
INT
1?
13
0
Interrupt. This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.
RD
14
-
I
Read. A low requests a read of the SSI ?3K302l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.
RESET
25
20
I
Reset. An active high signal on this pin will put the chip into
an inactive state. All control register bits (CRO, CR1, Tone)
will be reset. The output of the ClK pin will be set to the
crystal frequency. An internal pull down resistor permits
power on reset using a capacitor to VDD.
ALE
ADO-AD?
3-136
SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
PIN DESCRIPTION (Continued)
PARALLEL MICROPROCESSOR INTERFACE (Continued)
NAME
WR
28-PIN
22-PIN
TYPE
13
-
I
DESCRIPTION
Write. A low on this informs the SSI 73K302L that data is
available on ADO-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are active low.
SERIAL MICROPROCESSOR INTERFACE
AO-A2
-
5-7
DATA
-
RD
WR
Note:
I
Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.
8
I/O
Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.
-
10
I
Read. A low on this input informs the SSI 73K302L that
data or status information is being read by the processor.
The falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output unless the RD Signal is active.
-
9
I
Write. A low on this input informs the SSI73K302L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the riSing edge
ofWR.
In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the
pins; AO, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.
The serial control mode is provided in the parallel control versions by tying ALE high and CS low.
In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2,
respectively.
3-137
I
SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
PIN DESCRIPTION (Continued)
DTE USER INTERFACE
NAME
28-PIN
22-PIN
TYPE
EXCLK
19
15
I
External Clock. This signal is used only in synchronous
DPSK transmission when the external timing option has
been selected. In the external timing mode the rising edge
of EXCLK is used to strobe synchronous DPSK transmit
data available on the TXD pin. Also used for serial control
interface.
RXCLK
23
18
0
Receive Clock. The falling edge of this clock output is
coincident with the transitions in the serial received DPSK
data output. The rising edge of RXCLK can be used to latch
the valid output data. RXCLK will be valid as long as a
carrier is present. In Bell 202 mode a clock which is 16 x
1200 or 16 x 150 baud data rate is output.
RXD
22
17
0
Received Data Output. Serial receive data is available on
this pin. The data is always valid on the rising edge of
RXCLK when in synchronous mode. RXD will output constant marks if no carrier is detected.
TXCLK
18
14
0
Transmit Clock.This signal is used only in synchronous
DPSK transmission to latch serial input data on the TXD
pin. Data must be provided so that valid data is available
on the rising edge of the TXCLK. The transmit clock is
derived from different sources depending upon the synchronization mode selection. In Internal Mode the clock is
1200 Hz generated internally. In External Mode TXCLK is
phase locked to the EXCLK pin. In Slave Mode TXCLK is
phase locked to the RXCLK pin. TXCLK is always active. In
Bell 202 mode the output is a 16 x 1200 baud clock or 16
x 150 baud to drive a UART.
TXD
21
16
I
Transmit Data Input. Serial data for transmission is applied
on this pin. In synchronous modes, the data must be valid
on the rising edge of the TXCLK clock. In asynchronous
modes (1200 or300 baud) no clocking is necessary. DPSK
must be 1200 biVs +1%, -2.5% or +2.3%, -2.5 % in
extended overspeed mode.
DESCRIPTION
ANALOG INTERFACE AND OSCILLATOR
RXA
27
22
I
TXA
16
12
0
Transmit analog output to the telephone line interface.
XTL1
XTL2
2
3
3
I
I
These pins are for the internal crystal oscillator requiring
a 11.0592 MHz parallel mode crystal and two load capacitors to Ground. XTL2 can also be driven from an external
clock.
4
Received modulated analog signal input from the telephone line interface.
3-138
SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
REGISTER DESCRIPTIONS
Four 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO and A 1
address lines in serial mode, or the ADO and AD1 lines
in parallel mode. The ADO and AD11ines are latched by
ALE. Register CRO controls the method by which data
is transferred over the phone line. CR1 controls the
interface between the microprocessor and the
SSI 73K302L internal state. DR is a detect register
which provides an indication of monitored modem
status conditions. TR, the tone control register, controls the DTM F generator, answer and guard tones and
RXD output gate used in the modem initial connect
sequence. All registers are read/write except for DR
which is read only. Register control and status bits are
identified below:
REGISTER BIT SUMMARY
CONTROL
REGISTER
1
DETECT
REGISTER
TONE
CONTROL
REGISTER
CONTROL
REGISTER
I
CRO
000
CR1
001
ENABLE
DETECT
INTERRUPT
BYPASS
SCRAMBLER!
ADD PH. Ea.
202
CLK
CONTROL
RESET
TEST
MODE
1
DR
010
RECEIVE
DATA
UNSCR.
MARKS
CARRIER
DETECT
SPECIAL
TONE
CALL
PROGRESS
TR
011
TRANSMIT
DTMF
DTMF3
DTMFI
202T
FOX
CR2
100
CR3
101
10
110
2
CONTROL
REGISTER
3
10
REGISTER
NOTE:
When a register containing reserved
control bits is written into, the reserved bits
must be programmed as O's.
3-139
TEST
MODE
0
SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
REGISTER ADDRESS TABLE
0-103 FSK
1.202 FSK
O.DISABLE
TXA OUTPUT
1.ENABLE
TXAOUTPUT
OOOO.PWR DOWN
ll00.FSK
0010.EXT SYNCH
00ll.SLAVE SYNCH
0100.ASYNCH 8 BITs/CHAR
0101-ASYNCH 9 BITs/CHAR
0110.ASYNCH 10 BITSICHAR
0111-ASYNCH 11 BITSICHAR
ll00·FSK BELL 103 OR 202
O.ENABLE
1.DISABLE
IN 212, 103 MODES:
O.ANSWER
1.0RIGINATE
IN 202 MODE:
o-RECEIVE @ 1200 BITtS,
TRANSMIT @ 150 BITtS
1.RECEJVE @ 150 BITtS,
TRANS'-tT@ 1200 BITtS
O.NORMAL
O.XTAL
o-NORMAL
1.BYPASS
1.16 X DATA
1.RESET
RATE OUTPUT
SCRAMBLER
1.ADD EXTRA
ATCLKPIN IN
PHASE Ea.
DPSK MODE ONLY
IN 202 ONLY
0.10/.
0.900 HZ SCT TONE IF
1.2.5%
IN ANSWER MODE
.2225 HZ ANSWER TONE
O.NORMAL OPERATION
IN 103 OR 212 ORIGINATE
1.FULL DUPLEX IN 202 MODE
MODES
1.FSKMARK
00XX.73K212L, 322L, 321 L
01 XX.73K221 L, 302L
10XX.73K222L
ll00.73K224L
1110.73K324L
1101.73K312L
3-140
SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
II
CONTROL REGISTER 0
CRO
000
D7
MODUL.
OPTION
BIT NO.
DO
D4
D3
D2
D1
D5
TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT
MODE 3
MODE 2
MODE 1
ENABLE
MODE 0
DO
ANSWER/
ORIGINATE
NAME
CONDITION
Answer/
Originate
0
Selects answer mode in 103 and 212A modes (transmit in high band, receive in low band) or in Bell 202
mode, receive at 1200 bit/s and transmit at 150 bit/so
1
Selects originate mode in 103 and 212A modes (transmit in low band, receive in high band) or in Bell 202
mode, receive at 150 bitls and transmit at 1200 bit/so
DESCRIPTION
Note: This bit works with TR bit DO to program special
tones detected in Tone Register. See detect and tone
registers.
D1
Transmit
Enable
0
")I~;:!m~~
1
Enables transmitoupu! at
.0~plJt
Note: Answer tone and DTMF TX control require TX
enable.
D5, D4,D3,
D2
Transmit
Mode
0
0
0
0
Selects power down mode. All functions disabled
except digital interface.
0
0
0
1
Internal synchronous mode. In this mode TXCLK is an
internally derived 1200 Hz signal. Serial input data
appearing at TXD must be valid on the rising edge of
TXCLK. Receive data is clocked out of RXD on the
falling edge of RXCLK.
0
0
1
0
External synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 1200 Hz ± 0.01 % clock must
be supplied externally.
0
0
1
1
Slave synchronous mode. Same operation as other
synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.
0
1
0
0
Selects DPSK asynchronous mode - 8 bits/character
(1 start bit, 6 data bits, 1 stop bit).
0
1
0
1
Selects DPSK asynchronous mode - 9 bits/character
(1 start bit, 7 data bits, 1 stop bit).
0
1
1
0
Selects DPSK asynchronous mode - 10 bits/character
(1 start bit, 8 data bits, 1 stop ~).
0
1
1
1
Selects DPSK asynchronous mode -11 bits/character
(1 start bit, 8 data bits, Parity and 1 or 2 stop bits).
o
0
Selects 103 or 202 FSK
3-141
Vl-'~I QlIVI
I
SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
CONTROL REGISTER 0 (Continued)
D7
CRO
000
D5
CONDITION
NAME
D7 D5 D4
D7
D2
D3
TRANSMIT TRANSMIT
MODE 3
MODE 2
MODUL.
OPTION
BIT NO.
D4
D1
DO
TRANSMIT TRANSMIT TRANSMIT
MODE 1
MODE 0
ENABLE
ANSWER/
ORIGINATE
DESCRIPTION
Selects:
Modulation
Option
CONTROL REGISTER 1
CR1
001
BIT NO.
D7
D6
D5
D4
D3
D2
D1
DO
TRANSMIT
PATIERN
1
TRANSMIT
PATIERN
0
ENABLE
DETECT
INTER.
BYPASS
SCRAMB/
ADD
PH. EQ.
ClK
CONTROL
RESET
TEST
MODE
1
TEST
MODE
0
NAME
CONDITION
DESCRIPTION
D1 DO
D1,DO
D2
Test Mode
Reset
0
0
Selects normal operating mode.
0
1
Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced
low. Not supported in FDX202 mode.
1
0
Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is ignored.
1
1
Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit carrier from
TXA pin.
0
Selects normal operation.
1
Resets modem to power down state. All control
register bits (CRO, CR1, Tone) are reset to zero. The
output of the ClK pin will be set to the crystal
frequency.
3-142
SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
CONTROL REGISTER 1 (Continued)
CR1
001
BIT NO.
03
04*
05
07
06
05
04
03
02
01
00
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
OETECT
INTER.
BYPASS
SCRAMB!
AOO
PH. EO.
ClK
CONTROL
RESET
TEST
MOOE
1
TEST
MOOE
0
NAME
CONDITION
ClK Control
DESCRIPTION
0
Selects 11.0592 MHz crystal echo output at ClK
pin.
1
Selects 16 X the data rate, output at ClK pin in OPSK
modes only.
Bypass
Scrambler!
Add Phase
Equalization
0
Selects normal operation. OPSK data is passed
through scrambler.
1
Selects Scrambler Bypass. DPSK data is routed
around scrambler in the transmit path. In Bell 202
mode, additional phase equalization is added to the
main channel filters when 04 is set to 1.
Enable Oetect
Interrupt
0
Oisables interrupt at INT pin.
1
Enables INT output. An interrupt will be generated with
a change in status of OR bits 01-04. The special tone
and call progress detect interrupts are masked when
the TX enable bit is set. Carrier detect is masked when
TX OTMF is activated. All interrupts will be disabled if
the device is in power down mode.
07 06
07, 06
Transmit
Pattern
0
0
Selects normal data transmission as controlled
by the state of the TXO pin.
0
1
Selects an alternating mark/space transmit pattern for
modem testing.
1
0
Selects a constant mark transmit pattern.
1
1
Selects a constant space transmit pattern.
* 04 should always be set to 1 when receiving 1200 biVs data and to 0 when transmitting 1200 biVs data in
202 mode.
3-143
•
SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
DETECT REGISTER
DR
010
BIT NO.
DO
D5
D4
D3
D2
D1
DO
RECEIVE
DATA
UNSCR.
MARK
CARR.
DETECT
SPECIAL
TONE
CALL
PROG.
LONG
LOOP
NAME
CONDITION
Long Loop
0
DESCRIPTION
Indicates normal received signal.
01
Call Progress
0
No call progress tone detected.
Detect
I--------t----------------------I
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in
the normal 350 to 620 Hz call progress band.
D2
Special Tone
Detect
o
No special tone detected as programmed by
CRO bit DO and Tone Register bit DO.
(1) 2225 Hz answer tone if DO of TR=O and the device
is in 8ell1 03 or 212A originate mode.
(2) Soft carrier turn-off tone if DO of TR=O and the
device is in 8ell202 answer mode.
(3) an FSK mark in the mode the device is set to
receive if DO of TR is set to 1.
03
Carrier Detect l---~--_l_~~~~~~~~~~~~~~~----J
Indicated carrier has been detected in the received
channel.
04
Unscrambled
Mark
Detect
D5
Receive
Data
No
(DPSK only) Indicates detection of unscrambled
marks in the received data. A valid indication requires
that unscrambled marks be received for> 165.5 ±
6.5 ms.
Continuously outputs the received data stream.
This data is the same as that output on the RXD pin, but
it is not disabled when RXD is tri-stated.
D6,D7
3-144
SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
TONE REGISTER
TR
011
07
06
05
04
RXO
OUTPUT
CONTR.
TRANSMIT
SOFT
CARRIER
TURN-OFF
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
OTMF
BIT NO.
NAME
CONDITION
OTMF 01
Special Tone
02
OTMF 21
202
OTMF3
FOX
01
DO
OTMF 11
OVERSPEED
OTMF 01
SPECIAL
TONE SEL
DESCRIPTION
05 04 DO
DO
03
DO interacts with bits 06, 04, and CRO as shown.
0
1
X
Transmit OTMF tones.
0
0
0
2225 Hz answer tone will be detected in 02 of DR if
originate mode is selected in CRO.
Detect/Select
900 Hz SCT tone will be detected in 02 of DR if Bell 202
answer mode is selected in CRO.
X
0
1
Mark of an FSK mode selected in CRO is to be detected
in 02 of DR.
1
0
0
2225 Hz answer tone will be generated when in
answer mode and transmit enable is selected in CRO.
1
0
1
2100 Hz answer tone will be generated when in
answer mode and transmit enable is selected in CRO.
04 01
01 interacts with 04 as shown.
0
Asynchronous OPSK 1200 bitls +1.0% -2.5%.
1
Asynchronous OPSK 1200 bitls +2.3% -2.5%.
01
OTMF 11
Overspeed
02
OTMF2/202T
0
Enables 202 half-duplex operation if 04=0
FOX
1
Enables 202 full-duplex operation if 04=0
0
0
03 02 01 DO
03,02,
01,00
OTMF 3,
2,1,0
0
1
0
1
0 01 1
Programs 1 of 16 OTMF tone pairs that will be
transmitted when TX OTMF andTX enable bit (CRO, bit
01) are set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT
1
697
1209
0
697
1
1
1336
1477
0
0
1
0
1
697
770
770
0
1
852
1209
0
1
852
852
1336
1477
0
941
1336
0
0
0
0
3
4
0
0
1
1
1
0
1
1
1
0
0
1
0
1
0
0
1
7
8
9
0
0
0
0
TONES
LOW HIGH
0
1
1
2
5
6
3-145
OTMF CODE
03 02 01 DO
770
1209
1336
1477
•
SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
TONE REGISTER
TR
011
(Continued)
07
06
05
04
RXD
OUTPUT
CONTA.
TRANSMIT
SOFT
CARRIER
TURN-OFF
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
BIT NO.
NAME
CONDITION
03
DTMF 2/
DTMF3
202T
FDX
KEYBOARD
EQUIVALENT
.
(cont.)
#
A
B
C
D
05
06
07
01
DO
DTMF 1/
OVERSPEED
DTMF 0/
SPECIAL
TONE SEL
DESCRIPTION
03, D2,
01,00
04
02
DTMFCODE
03 02 D1 DO
TONES
LOW HIGH
1
0
1
1
941
1
1
0
0
941
1477
1
1
0
1
697
1633
1
1
1
0
770
1633
1
1
1
1
852
1633
0
0
0
0
941
1633
1209
Transmit
DTMF
0
Disable DTMF.
1
Activate DTMF. The selected DTMF tones are
transmitted continuously when this bit is high.
TX DTM F overrides all other transmit functions.
Transmit
Answer Tone
0
Disables answer tone generator.
1
Enables answer tone generator. A 2225 Hz
answer tone will be transmitted continuously when the
transmit enable bit is set. To transmit answer tone, the
device must be in answer mode.
Transmit
SCT Tone
0
Disables SCT tone generator.
1
Transmit SCT tone in Bell 202 mode.
0
Enables RXD pin. Receive data will be output on
RXD.
1
Disables RXD pin. The RXD pin reverts to a high
impedance with internal weak pull-up resistor.
RXD Output
Control
Notes for Tone Register use:
1.
To detect SCT tone, 202 answer mode must be selected. To transmit SCT tone, 202 originate mode must
be selected.
2.
For answer tone detection, 103 or 212 originate mode must be active. To transmit answer tone, the
73K302 must be in 103 or 212 answer mode.
3.
After completion of DTMF dialing, bit 02 should be reset unless 202 full-duplex mode is selected.
3-146
SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
ID REGISTER
10
07
06
05
04
10
10
10
10
110
BIT NO.
CONDITION
NAME
DESCRIPTION
Indicates Device:
07 06 05 04
Device
07,06
Identification
•
Signature
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
VOO Supply Voltage
14V
Storage Temperature
-65 to 150°C
Soldering Temperature (10 sec.)
260°C
Applied Voltage
-0.3 to VOO+0.3V
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITIONS
VOO Supply voltage
TA, Operating Free-Air Temp.
Clock Variation
(11.0592 MHz) Crystal or external clock
MIN
NOM
MAX
UNITS
4.5
5
5.5
V
-40
+85
°C
-0.01
+0.01
%
2.2
MQ
External Components (Refer to Application section for placement.)
VREF Bypass Capacitor
(External to GNO)
0.1
Bias setting resistor
(Placed between VDD and (SET pins)
1.8
JlF
2
ISET Bypass Capacitor
(ISET pin to GNO)
0.1
JlF
VOO Bypass Capacitor 1
(External to GNO)
0.1
JlF
VOO Bypass Capacitor 2
(External to GNO)
22
XTL 1 Load Capacitor
Depends on crystal characteristics;
40
XTL2 Load Capacitor
from pin to GNO
20
3-147
JlF
pF
SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VOO = recommended range unless otherwise noted.)
PARAMETER
CONDITIONS
100, Supply Current
ISET Resistor
10DA, Active
1001, Power-down
1002, Power-down
MIN
NOM
MAX
8
12
mA
4
rnA
3
mA
UNITS
= 2 MQ
= 11.0592 MHz
ClK = 11.0592 MHz
ClK = 19.200 kHz
ClK
Digital Inputs
VIH, Input High Volt(!ge
Reset, XTl1 , XTl2
3.0
VOO
V
All other inputs
2.0
VOO
V
0.8
V
100
50
/lA
/lA
/lA
10
pF
Vll, Input low Voltage
0
Beset Pull-down Current
= VIH Max
VI = Vil Min
Reset = VDO
Input Capacitance
All Oigitallnput Pins
IIH, Input High Current
Ill, Input low Current
VI
-200
1
Digital Outputs
RXD Tri-State Pull-up Curr.
= -0.4 mA
10 MAX = 1.6 mA
10 = 3.6 mA
RXO = GNO
-50
/lA
CMAX, ClK Output
Maximum Capacitive load
15
pF
Capacitance, all Oigitallnput pins
10
pF
60
pF
15
pF
VOH, Output High Voltage
VOL, Output low Voltage
VOL, ClK Output
10H MIN
2.4
-1
VOO
V
0.4
V
0.6
V
Capacitance
Inputs
XTl1 , 2 load Capacitors
Depends on crystal
ClK
Maximum Capacitive load
3-148
15
SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = Recommended range unless otherwise noted.)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
-10
-9
dBmO
DPSK Modulator
Carrier Suppression
Measured at TXA
45
Output Amplitude
TX scrambled marks
-11
dB
FSK Modulator
Output Freq. Error
ClK
= 11.0592 MHz
-0.35
Transmit level
Transmit Dotting Pattern
-11
-10
-9
dBmO
-11.9
-10.9
-9.9
dBmO
THO in the alternate band
DPSK or FSK
-60
-50
dB
Output Bias Distortion
Transmit Dotting Pattern
InAlB@ RXD
±3
Total Output Jitter
Random Input in ALB @ RXD
DTMF Generator
Must not be in 202 mode
Soft Carrier Turnoff Tone
Harmonic Distortion
in 700-2900 Hz band
Freq. Accuracy
+0.35
%
%
-10
+10
%
-0.25
+0.25
%
Output Amplitude, low group
DPSK mode
-10
-9
-8
dBmO
Output Amplitude, High group
DPSK mode
-8
-7
-6
dBmO
2.0
3.0
dB
-28
dBmO
High-Band to low-Band
1.0
long loop Detect
Twist
With Sinusoid
-38
Dynamic Range
Refer to Performance Curves
Note:
45
Parameters expressed in dBmO refer to the following definition:
5V Version:
o dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
3-149
dB
I
SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
CONDITIONS
MIN
-3 dB points in 285 and 675 Hz
-38
NOM
MAX
UNITS
Call Progress Detector
Detect Level
dBmO
Reject Level
Test signal is a 460 Hz sinusoid
-45
dBmO
Delay Time
-70 dBmO to -30 dBmO STEP
20
40
ms
Hold Time
-30 dBmO to -70 dBmO STEP
20
40
ms
Hysteresis
2
dB
Carrier Detect
Threshold
DPSK or FSK receive data
-49
-42
dBmO
Delay Time
Bell 103
8
20
ms
Bell 212A
15
32
ms
Bell 202 Forward Channel
6
12
ms
Bell 202 Back Channel
25
40
ms
Bell 103
6
20
ms
ms
Hold Time
Bell 212A
10
24
Bell 202 Forward Channel
3
8
ms
Bell 202 Back Channel
10
25
ms
Hysteresis
2
dB
Special Tone Detectors
Detect Level
See definitions for
TR bit DO mode
-49
-42
dBmO
10
25
ms
Delay Time
Answer tone
Preceded by valid carrier·
4
10
ms
202 Main Channel Mark
10
25
ms
202 Back Channel Mark
20
65
ms
1270 or 2225 Hz marks
10
25
ms
900 Hz SCT tone
• If SCT duration >4ms, it is guaranteed to detect.
3-150
SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
MAX
UNITS
4
15
ms
900 Hz SCT tone
1
10
ms
202 Main Channel Mark
3
10
ms
202 Back Channel Mark
10
25
ms
1270 or 2225 Hz marks
5
15
ms
PARAMETERS
MIN
CONDITIONS
NOM
Special Tone Detectors (Continued)
Hold Time
Answer tone
Any Special Tone
-3
Output load
TXA pin; FSK Single
Tone out for THO = -50 dB
in 0.3 to 3.4 kHz
10
Out of Band Energy
Frequency> 12 kHz in all modes
See Transmit Energy Spectrum
Output Impedance
TXA pin
Clock Noise
TXA pin; 76.8 kHz or 122.88 kHz
in 202 main channel
Detect Freq. Range
dB
2
Hysteresis
+3
%
Output Smoothing Filter
kQ
50
pF
-60
dBmO
20
50
Q
0.1
0.4
mVrms
+10
Hz
100
ms
+625
ppm
50
ms
-5
+5
Hz
-1
+1
dB
Carrier VCO
Capture Range
Originate or Answer
Capture Time
-10 Hz to +10 Hz Carrier
Frequency Change
-10
40
DPSK Recovered Clock
Capture Range
% of data rate
-625
(center at 1200 Hz)
Data Delay Time
Analog data in at RXA pin to
receive data valid at RXD pin
30
Tone Generator
---"
...
~
Tone Accuracy
DTMF or FSK tones
Tone Level
For DTMF, must not be in 202 mode
3-151
----_ ....
•
SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
MIN
CONDITIONS
NOM
MAX
UNITS
Timing (Refer to Timing Diagrams)
.
TAL
CS/Addr. setup before ALE Low
TLA
CS/Addr. hold after ALE Low
TLC
ALE Low to RDIWR Low
TCL
RD/WR Control to ALE High
TRD
Data out from RD Low
TLL
ALE width
TRDF
Data float after RD High
TRW
RD width
TWW
WR width
TDW
Data setup before WR High
TWO
Data hold after WR High
TCKD
Data out after EXCLK Low
TCKW
WR after EXCLK Low
TDCK
Data setup before EXCLK Low
TAC
Address setup before control·
TCA
Address hold after control·
TWH
Data Hold after EXCLK
Control for setup is the falling edge of RD or WR .
Control for hold is the falling edge of RD or the rising edge of WR.
3-152
25
20
30
-5
0
30
0
200
140
40
ns
ns
ns
ns
140
ns
ns
5
25000
25000
ns
ns
ns
ns
10
ns
200
ns
150
150
ns
50
50
20
ns
ns
ns
SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
~
ALE
~_ _ _ _ _ _ __
TLC
TLC
TWD
ADO-AD7
~
--K
I..
TAL
ADDRESS } - - K READ DATA}--K ADDRESS } - - KWRITE DATA)f--
-=1'------------L-~I__-------I-~'-------1.-~+---- - -
READ TIMING DIAGRAM (SERIAL VERSION)
EXCLK
AO-A2
DATA
I t.1
TOW ...
--+
WRITE TIMING DIAGRAM (SERIAL VERSION)
EXCLK
AO-A2 - - - i - - - - - - - - - - - - - - - - - - - - - # - .
DATA
3-153
I
SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
SSI73K302L
SSI73K302L
BER vs SIN
BER vs SIN
~
10-3
I
\
~
\
~
~
\
\ \
~
a:
a:
0
a:
a:
LlJ
\
~~-
\
\
\~
10-4
\.
\.
\
I\~
LlJ
RECEIVE~
HIGH BAND
-30 dBm
DPSKOPERATION
1200 BITIS
\ \\
\\
'l\
l
\ L[
\
~H
\ ~~ I-i
r---r--1
~
3002W/O ]
EO.
1\\\\
\
\\'
t:::
Ql
[FLATW/O}
EO.
1\
FLATW/EO·I
f-\\ ~
1
\
RECEIVE LEVEL
-30 dBm
BELL 202 MODE
\
I \'r ~f2WB
I
~\
4
\\
10
~\\
\
1\
\
\
\\
\\~
\' \
14
16
10
4
SIGNAL TO NOISE (dB)
12
14
SIGNAL TO NOISE (dB)
SSI73K302L
SSI73K302L
BER vs RECEIVE LEVEL
BER vs PHASE JITTER
I HIGH
BAND RECEIVE
DPSK OPERATION
I HIGH
BAND RECEIVE ~
DPSK OPERATION
I
\
\
~.'
12
FLAT
\~\
1\
r
-
\ '!\
\
1\
\~ -r~~~\
10-5
C2
~3002
I
C2 LINE
10-3
--
j
3002 11 .5 dB SIN
./
I
SIN
\
=10.8 dB
/
SIN
10-5
k::::: :::::
Lvv
/"
/
~
I
f..- f.-
C210.8 dB SIN
1=rI--- I-r--
=15 dB
\.
10
-10
-20
-30
-40
4
-50
RECEIVE LEVEL (dBm)
12
16
PHASE JITIER (DEG.)
3-154
20
24
SSI73K302L
Bell 212A, 103,202
Single-Chip Modem
SSI73K302L
BER vs CARRIER OFFSET
I HIGH BAND RECEIVE } I DPSKOPERATION
•
10-4
3002 11.8 dB SIN
l
1\
\
C211.3 dB SIN
~
_r-
I-- I-I--I -
r\.
p-
v
~
V
~
~
10-6
12
-4
-8
-12
CARRIER OFFSET (HZ)
3-155
SSI73K302L
Bell 212A, 103, 202
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
GND
RXA
VREF
XTL1
GND
RXA
XTL2
VREF
ADO
RESET
AD1
ISET
AD2
RXCLK
AD3
RXD
RXCLK
AD4
TXD
RXD
AD5
cs
TXD
AD6
EXCLK
EXCLK
AD7
RESET
ISET
A1
CLK
XTl1
TXA
400-Mil
22-Pin DIP
4
3
2
1282726
25
24
8
PLCC PINOUTS
ARE THE SAME AS
THE 28-PIN DIP
23
22
21
ALE
INT
10
20
WR
TXA
11
19
Rrr
VDD
12 13 14 15 16 17 18
28-Pin
PLCC
600-Mil
28-Pin DIP
ORDERING INFORMATION
ORDER NO.
PART DESCRIPTION
PKG.MARK
SSI 73K302L with Parallel Bus Interface
28-Pin Dip
73K302L-IP
73K302L-IP
28-Lead PLCC
73K302L-IH
73K302L-IH
73K302SL-IP
73K302SL -I P
SSI 73K302L with Serial Interface
22-pin Dip
Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
0194 - rev.
3-156
Protected by the following Patents (4,691,172) (4,777,453)
©1989 Silicon Systems, Inc.
SSI73K312L
Bell 202, 103 and CCIlT V.23, V.21
Single-Chip Modem
January 1994
DESCRIPTION
FEATURES
The SSI 73K312L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a CCITT V.23, V.21, Bell 202, 103 FSK
modem. The 73K312L supports asynchronous 1200
bitls (600 bitls at V.23 half speed mode) with or without
75/150 bitls back channel (75 forV.23 and 150 for Bell
202) and 300 bitls FSK (V.21 or Bell 103). The
SSI 73K312L can also both detect and generate the
CCITT and Bell answertones needed for call initiation.
The SSI 73K312L integrates analog, digital, and
switched-capacitor array functions on a single substrate, offering excellent performance and a high level
of functional integration in a single 28- or 22-pin DIP or
28 pin PLCCconfiguration. The SSI73K312Loperates
from a single +5 V supply with very low power consumption ..
•
The SSI73K312L includes the FSK modulator/demodulatorfunctions, call progress and handshake tone monitor test modes, and a tone generator capable of producing DTMF, answer, calling and 900 Hz soft carrier turnoff tones. The SSI 73K312L is designed to appearto the
systems designer as a microprocessor peripheral, and
will easily interface with popular one-chip microprocessors (80C51 typical) for control of modem functions
through its 8-bit multiplexed addressldata bus or via an
optional serial command bus. An ALE control line
simplifies address demultiplexing. Data communications occur through a separate serial port only.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bell 202, 103 and CCITT V.23, V.21 single-chip
modem
Full-duplex operation at 0-300 bitls (V.21 and Bell
103)
V.23 modes 1, 2, (i.e., 0-600 bit/s and 0-1200 bit/s)
forward channel with or without 0-75 bitls back
channel
Bell 202 0-1200 bitls forward channel with or
without 0-150 bitls back channel
Full Duplex 4-wire mode operation in V.23 and
Bell 202 modes
Pin and software compatible with other
SSI K-Series 1-chip modems
Interfaces directly with standard microprocessors (8048, 80C51 typical)
Serial or parallel microprocessor bus for control
Serial port for data transfer
Call progress, carrier, precise answer tone
(2100 or 2225 Hz), and precise mark detectors
Precise calling tone and soft carrier turnoff
generators/detectors (1300 Hz, 900 Hz)
DTMF generator
Test modes available: ALB, DL, Mark, Space,
Alternating bit patterns
Adjustable transmit level
Precise automatic gain control allows 45 dB dynamiC range
CMOS technology for low power consumption
using 30 mW @ 5V from a single power supply
PIN DIAGRAM
BLOCK DIAGRAM
AOO·A07
elK
XTL1
XTl2
ADO
AD1
AD2
AD3
AD4
AD5
TXOo-------~
AD6
RXOo--------L_-.l
AD?
ALE
Wi=!
l1l5
0194 - rev.
3-157
CAUTION: Use handling procedures necessary
for a static sensitive component.
•
SSI73K312L
Bell 202, 103 and CCITI V.23, V.21
Single-Chip Modem
OPERATION
PASSBAND FILTERS AND EQUALIZERS
The SSI 73K312L is ideal for either free standing or
integral system modem applications where multistandard data communications is desired. Typical
uses include videotex terminals, low-cost integral
modems and built-in diagnostics for office automation
or industrial control systems. The 73K312L's high
functionality, low power consumption and efficient
packaging simplify design requirements and increase
system reliability in these applications. A complete
modem requires only the addition of the phone line
interface, a control microprocessor, and RS-232 level
converter for a typical system.
A high and low band filter is included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band signals in the
receive channel. Amplitude and phase equalization
are necessary to compensate for distortion of the
transmission line.
Quad-mode capability in one-chip allows full-duplex
V.21 and Bell 103 operation or asymetrical V.23 and
Bell 202 operation over the 2-wire switched telephone
network. V.23 and 202 mode full-duplex operation at
1200 biVs is also possible when operating on 4-wire
leased lines.
A soft carrier turn-off feature facilitates fast line turn
around when using the 202 or V.23 modes for halfduplex applications.
The SSI 73K312L is part of Silicon Systems K-Series
family of pin and function compatible single-chip
modem products. These devices allow systems to be
configured for higher speeds and Bell or CCITT
operation with only a single component change.
FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. V.21 mode uses 980 and
1180 Hz (originate, mark and space) or 1650 and
1850 Hz (answer, mark and space). V.23 mode uses
1300 and 2100 Hz for the main channel and 390 and
450 Hz forthe back channel. The modulation rate of the
back channel is up to 75 baud. Bell 103 mode uses
1270 and 1070 Hz (originate, mark and space) or 2225
and 2025 Hz (answer, mark and space). Bell 202 mode
uses 1200 and 2200 Hz for the main channel and 387
and 487 Hz for the back channel. The modulation rate
of the back channel is up to 150 baud. Demodulation
involves detecting the received frequencies and decoding them into the appropriate binary value.
AGC
The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
dynamic range of >45 dB.
PARALLEL BUS INTERFACE
Six 8-bit registers are provided for control, option select
and status monitoring. These registers are addressed
with the ADO, AD1, and AD2 multiplexed address lines
(latched by ALE) and appear to a control microprocessor as memory locations. Three control registers
and the tone register are read/write memory. The
status detect register is read only and cannot be
modified except by modem response to monitored
parameters. The parallel bus interface is not available
with the 22-pin package.
SERIAL COMMAND INTERFACE MODE
The serial command mode allows access to the SSI
73K312L control and status registers via a serial command port.lnthis modetheAO ,A1 andA2linesprovide
register addresses for data passed through the data
pin under control of the RD and WR lines. A read
operation is initiated when the RD line istaken low. The
first data bit is available after RD goes low. The next
seven cycles of EXCLK will then transfer out seven bits
of the selected address location LSB first. A write takes
place by shifting in eight bits of data LSB first for eight
consecutive cycles of EXCLK. WR is then pulsed low
and data transferred into the selected register occurs
on the rising edge of WR.
3-158
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
SPECIAL DETECT CIRCUITRY
The special detect circuitry monitors the received
analog signal to determine status or presence of carrier, answer tone and weak received signal (long loop
condition), special tones such as FSK marking tones,
calling tones and the 900 Hz soft carrier turn-off tone
are also detected. A highly frequency selective call
progress detector provides adequate discrimination to
accurately detect European call progress signals.
dual-tones determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone
register. Tone generation is initiated when the DTMF
mode is selected and the transmit enable (CRO bit D1)
is changed from 0 to 1.
SOFT CARRIER TURN-OFF TONE GENERATOR
The soft carrier turn-off tone generator will output a
900 Hz tone. When activated in Bell 202 main channel
transmit mode, the output signal will shift to 900 Hz,
maintaining phase continuity during the transition.
DTMF GENERATOR
•
The DTMF generator will output one of 16 standard
PIN DESCRIPTION
POWER
NAME
GND
TYPE
DESCRIPTION
I
System Ground.
VDD
I
VREF
0
ISET
I
Power supply input, 5V ±1 0%. Bypass with 0.1 and 22 ~F capacitors to ground.
An internally generated reference voltage. Bypass with 0.1
ground.
~F
capacitor to
Chip current reference. Sets bias current for op-amps. The chip current is set
by connecting this pin to VDD through a 2 MQ resistor. ISET should be
bypassed to GND with a 0.1 ~F capacitor.
PARALLEL MICROPROCESSOR INTERFACE
I
Address latch enable. The falling edge of ALE latches the address on ADOAD2 and the chip select on CS.
I/O
Address/data bus. These bidirectional tri-state multi-plexed lines carry information to and from the internal registers.
CS
I
Chip select. A low on this pin allows a read cycle or a write cycle to occur. ADOAD? will not be driven and no registers will be written if CS (latched) is not
active. The state of CS is latched on the falling edge of ALE.
ClK
0
Output clock. This pin is selectable under processor control to be either the
crystal frequency (for use as a processor clock) or clock depending on the
mode: 19.2 kHz (BeIl103), 15.36 kHz (V.21, V.23, Bell 202). The pin defaults
to the crystal frequency on reset.
ALE
ADO-AD?
3-159
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
PIN DESCRIPTION
(Continued)
PARALLEL MICROPROCESSOR INTERFACE (Continued)
TYPE
NAME
DESCRIPTION
INT
0
Interrupt. This open drain output signal is used to inform the processor that a
detect flag has occurred. The processor must then read the detect register to
determine which detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.
RD
I
Read. A low requests a read of the SSI 73K312L internal registers. Data
cannot be output unless both RD and the latched CS are active (low).
RESET
I
Reset. An active high signal on this pin will put the chip into an inactive state.
All control register bits (CRO, CR1, CR3) will be reset except for the D2 bit of
CR3 which will be set to one to allow nominal transmit power. The output of the
CLK pin will be set to the crystal frequency. An internal pull down resistor
permits power on reset using a 1 IlF capacitor to VDD.
WR
I
Write. A low on this informs the SSI 73K312L that data is available on ADOAD7 for writing into an internal register. Data is latched on the rising edge of
WR. No data is written unless both WR and the latched CS are active (low).
SERIAL MICROPROCESSOR INTERFACE MODE (See Serial Interface Timing Diagram)
ADO-AD2
I
Register Address Selection. These lines carry register addresses and should
be valid during any read or write operation.
AD7
I/O
Serial Control Data. Data for a read/write operation is clocked in or out on the
falling edge of the EXCLK pin. The direction of data flow is controlled by the
RD pin. RD low outputs data. RD high inputs data.
RD
I
Read. A low on this input informs the SSI 73K312L that data or status
information is being read by the processor. The falling edge of the RD signal
will initiate a read from the addressed register. The RD signal must continue
for seven falling edges of EXCLK in orderto read all eight bits of the referenced
register. Read data is provided LSB first. Data will not be output unless the RD
signal is active.
WR
I
Write. A low on this input informs the SSI 73K312L that data or status
information has been shifted in through the DATA pin and is available for writing
to an internal register. The normal procedure for a write is to shift in data LSB
first on the DATA pin for eight consecutive falling edges of EXCLK and then to
pulse WR low. Data is written on the rising edge of WR.
EXCLK
I
External Clock. Used for serial control interface to clock control data in or out
of the 73K312L.
Note:
The Serial Control mode is provided by floating ALE and CS or EXCLK tying ALE high and CS low.
This is identical to the serial interface or other K series devices. But the 22-Pin package is not
available with the 73K312L.
3-160
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
RS-232 INTERFACE
NAME
TYPE
DESCRIPTION
RXCLK
0
Receive Clock. In V.23 2-wire mode RXCLK equals 16 x 1200 if answering and
16 x 75 if originating. In Bell 202 2-wire mode RXCLK equals 16 x 1200 if
answering and 16 x 150 if originating. In V.21 or Bell 103 mode it equals 16
x 300.
RXD
0
Received Digital Data Output. Serial receive data is available on this pin. RXD
will output constant marks if no carrier is detected.
TXCLK
0
Transmit Clock. If 1200 bitls mode is selected, TXCLK equals 16 x1200 if
originating and 16 x 75 (V.23) or 16 x 150 (Bell 202) if answering. In V.21 or
Bell 103 mode it equals 16 x 300.
TXD
I
Transmit Digital Data Input. Serial data for transmission is input on this pin.
ANALOG INTERFACE AND OSCILLATOR
RXA
I
TXA
0
XTL1
XTL2
I
I
Received modulated analog signal input from the phone line.
Transmit analog output to the phone line.
These pins are for the internal crystal oscillator requiring a 11.0592 MHz
parallel mode crystal and two load capacitors to Ground. XTL 1 can also be
driven from an external clock.
3-161
•
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
REGISTER DESCRIPTIONS
Four 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO, A 1 and
A2 address lines in serial mode, or the ADO, AD1 and
AD2 lines in parallel mode. The ADO, AD1 and AD2
lines are latched by ALE. Register CRO controls the
method by which data is transferred over the phone
line. CR1 controls the interface between the micropro-
cessor and the SSI 73K312L internal state. CR3 controls the attenuation of the transmitted signal and
enables receive gain boost. DR is a detect register
which provides an indication of monitored modem
status conditions. TR, the tone control register, controls the DTMF generator, answer and RX output gate
used in the modem initial connect sequence. All registers are read/write except for DR which is read only.
Register control and status bits are identified below:
REGISTER BIT SUMMARY
CRO
CR1
001
CLK
CONTROL
RESET
TEST
MODE
1
TEST
MODE
0
DR
010
CARRIER
DETECT
SPECIAL
TONE
CALL
PROGRESS
LONG
LOOP
TONE
CONTROL
REGISTER
m
011
DTMF3
DTMF2I
V.23 FOX
202 FOX
DTMF1
DTMFO/
TONE SELECT
CONTROL
REGISTER
2
CR2
100
CONTROL
REGISTER
3
CR3
101
ID
110
CONTROL
REGISTER
1
DETECT
REGISTER
ID
REGISTER
NOTE:
When a register containing reserved
control bits is written into, the reserved bits
must be programmed as O's.
3-162
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
REGISTER ADDRESS TABLE
0=V.23 or BELL 103
1.V.21 or BELL 202
OOOO=PWR DOWN
1000.BELL 103 or 202
11 OO=CCITT V.23 or V.21
1110.CCITI V.23 MC HALF SPEED
RXDPIN
O.NORMAL
1.TRANSMITS
1. TRI STATE CALLING TONE IF
ORIGINATING IN CCITI
MODE. TRANSMITS
SCTTONE IF
ORIGINATING IN
BELL MODE.
O=SQUELCH
ANALOG
1.ENABLE
ANALOG
V.21 AND BELL 103:
O.ANSWER
1.0RIGINATE
V.23 AND BELL 202:
O.RECEIVE@ 1200/600 BITIS
TRANSMIT @75/150 BITIS
1=RECEIVE@751150 BITIS
TRANSMIT @ 1200/600 BITIS
O=NORMAL
1=ALLOWS V.23 or BELL 202 FULL
DUPLEX OPERATION
0000-1111 SETS TRANSMIT
ATTENUATOR 16 dB RANGE
DEFAULT.0100.-1 OdBm
00XX.73K212L, 322L, 321L
01XX.73K221L,302L
10XX.73K222L
11OO=73K224L
1110=73K324L
1101.73K312L
3-163
•
SSI73K312L
Bell 202, 103 and CCIIT V.23, V.21
Single-Chip Modem
CONTROL REGISTER 0
07
CRO
000
05
BIT NO.
00
03
04
02
01
TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT
MOOE2
MOOE 1
MOOEO
ENA8LE
MOOE3
SPEEO
SELECT
NAME
CONDITION
Answer/
Originate
0
00
ANSWER/
ORIGINATE
DESCRIPTION
Selects answer mode in V.21 or 8ell1 03 (transmit in high
band, receive in low band), or in V.23/8ell 202 modes,
receive at 1200/600 bitls and transmit at 75/150 bitls.
Selects originate mode in V.21 or Bell 103 (transmit in low
band, receive in high band), or in V.23/8ell 202 modes,
receive at 75/150 bit/s and transmit at 1200/600 bit/so If in
V.23/ 8ell202 and 02 of TR=1, selects full duplex operation in 4-wire configuration in main channel.
Note: This bit works with TR bit DO to program special
tones detected in Tone Register. See detect and tone
registers.
01
Transmit
Enable
Note: Answer tone and OTMF transmit control require
transmit enable.
05,04,03,
02
Transmit
Mode
05 04 03 02
0
0
0
0
Selects power down mode. All functions disabled except
digital interface.
3-164
SSI73K312L
Bell 202, 103 and CCITI V.23, V.21
Single-Chip Modem
CONTROL REGISTER 1
CR1
001
07
06
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
05
BIT NO.
NAME
CONDITION
01,00
Test Mode
01 DO
02
03
04
05
07,06
01
DO
RESET
TEST
MODE
1
TEST
MODE
0
DESCRIPTION
0
Selects normal operating mode.
0
1
Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced low.
1
1
Selects local digitalloopback. Internally loops TXO back
to RXO and continues to transmit data from TXA pin.
ClK Control
(Clock Control)
Add Ph. Eq.
Enable Detect
Interrupt
Pattern
02
03
0
Reset
Transmit
04
ENABLE ADD PH. EQ.
ClK
CONTROL
DETECT
INTER.
0
Selects normal operation.
1
Resets modem to power down state. All control register
bits (CRO, CR1, CR3 exceptfor 02 bit, Tone) are resetto
zero. CR3 bit 02 is set to one. The output of the clock pin
will be set to the crystal frequency.
0
Selects 11.0592 MHz crystal echo output at ClK pin.
1
Selects 19.2 kHz (Belli 03) or 15.36 kHz( V.21, V.23, Bell
202).
0
Selects normal equalization.
1
In V.23 or Bell 202 mode, additional phase equalization
is added in series with the main channel filters.
0
Disables interrupt at INT pin. All interrupts are normally
disabled in power down modes.
1
Enables INT output. An interrupt will be generated with
a change in status of DR bits 01-03. The special tone
and call progress detect interrupts are masked when the
TX enable bit is set. Carrier detect is masked when TX
OTMF is activated. All interrupts will be disabled if the
device is in power down mode.
07 06
0
0
Selects normal data transmission as controlled by the
state of the TXO pin.
0
1
Selects an alternating mark/space transmit pattern for
modem testing.
1
0
Selects a constant mark transmit pattern.
1
1
Selects a constant space transmit pattern.
3-165
•
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
DETECT REGISTER
DR
010
DO
Long Loop
D1
Call Progress
0
D3
D2
D1
DO
CARR.
DETECT
SPECIAL
TONE
CALL
PROG.
LONG
LOOP
No call progress tone detected.
~----------~----------------------------------~
Detect
D2
Special Tone
Detect
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in the
normal 350 to 620 Hz call progress band.
o
No special tone detected as programmed by CRO bit DO
and Tone Register bit DO.
The tone is selected by bits in CRO and TR.
D3
Carrier Detect
o
No carrier detected in the receive channel.
Indicated carrier has been detected in the received
channel.
D5
D6,D7
Receive
Data
Continuously outputs the received data stream. This data
is the same as that output on the RXD pin, but it is not
disabled when RXD is tri-stated.
Not used.
3-166
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
TONE REGISTER
TR
011
07
06
05
04
RXO
OUTPUT
CONTR.
TRANSMIT
CALLING
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
OTMF
BIT NO.
DO
NAME
CONDITION
01
DO
OTMF 1
OTMF 01
TONE SELECT
02
03
OTMF3 OTMF 21
V.23 FOX
202 FOX
DESCRIPTION
In CCID mode, the Tone detected in 02 bit of TR is Ma~
of FSK selected if this bit is O.
2100 Hz if this bit is 1 and originating,
1300 Hz if this bit is 1 and answering.
In Bell mode, the Tone detected in 02 bit of TR is
2225 Hz if this bit is and originating
900 Hz (SCT) if this bit is and answering
Mark of FSK selected if this bit is 1.
Tone Select
a
a
03 02 01 DO
03,02,
01, DO
OTMF 3,
2,1,0
a a a
1
1
1
01
Programs 1 of 16 OTMF tone pairs that will be
transmitted when TX OTMF and TX enable bit (CRO, bit
01) is set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT
TONES
LOW HIGH
#
a a a
a a 1
a a 1
a 1 a
a 1 a
a 1 1
a 1 1
1 a a
1 a a
1 a 1
1 a 1
1 1 a
0
941
1477
A
1
1
0
1
697
1633
B
1
1
1
0
770
1633
C
0
1
1
1
1
852
1633
0
a a
0
941
1633
1
2
3
4
5
6
7
8
9
a
..
3-167
OTMF CODE
03 02 01 DO
1
697
1209
0
697
1336
1
697
1477
0
770
1209
1
770
1336
0
770
1477
1
852
1209
0
852
1336
1477
1
852
0
941
1336
1
941
1209
•
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
TONE REGISTER
BIT NO.
D2
(Continued)
NAME
CONDITION
V.23/
0
Bell 202
1
Normal Operation
Enables V.23 or Bell 202 full-duplex operation if D4=0.
FDX
D4
A 4-wire configuration is required in this mode.
TX DTMF
0
Disabled DTM F.
1
Activates DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF
overrides all other transmit functions.
TXANS
0
Disables answer tone generator.
(Transmit
Answer tone)
1
Enables answer tone generator. A 21 00 Hz or 2225 Hz
answer tone will be transmitted continuously when the
transmit enable bit is set. If TR: DO = 0, a 2225 Hz tone
will be generated. If TR: DO = 1, a 2100 Hz tone will be
generated. The device must be in answer mode.
TX Calling Tonel
0
Disables calling or SCT tone generator.
1
Transmit calling tone if originating in CCITT mode.
Transmit SCTtone if originating in Bell mode. Transmits
neither if answering.
Transmit
DTMF
D5
D6
DESCRIPTION
SCT (Soft Carrier
Turn-Off)Tone
D7
RXD Output
Control
0
Enables RXD pin. Receive data will be output on RXD.
1
Disables RXD pin.The RXD pin reverts to a high impedance with internal weak pull-up resistor.
CONTROL REGISTER 3
"".".,
.
,'
.....
" ..
CR3
101
>
)
> .'"
BIT NO.
,
""" ..
<
. ,' ......... >
""«'.'." . '. .
,.",
>
". ".. >.' .:.:.
",.>:, ·,i"·:··'
......:
/",><"
>y"
'>, . . "../
NAME
."
... ,.' ...
'.',
.... ,
D4
D3
RECEIVE
ENABLE
BOOST
TRANSMIT
ATTEN.
3
CONDITION
D2
D1
DO
TRANSMIT TRANSMIT TRANSMIT
ATTEN.
ATTEN .
ATTEN.
0
2
1
DESCRIPTION
D3 D2 D1 DO
D3,D2
D1, DO
D4
Transmit
Attenuator
0
1
0
1
0
1
01
Sets the attenuation level of the transmitted signal in
1 dB steps. The default (D3-DO = 01 00) isfora transmit
level of -10 dBmO at the line with the recommended
hybrid transmit gain. The total range is 16 dB.
Receive
0
12 dB receive front end boost is not used.
Gain Boost
1
Boost is in the path. This boost does not change
reference levels. It is used to extend dynamic range by
compensating for internally generated noise when
receiving weak signals. The receive level detect signal
and knowledge of the hybrid and transmit attenuator
setting will determine wtlen boost should be enabled.
3-168
SSI73K312L
Bell 202, 103 and CCITT V.23, V. 21
Single-Chip Modem
ID REGISTER
07
06
05
04
10
3
10
2
10
1
10
0
10
110
BIT NO.
NAME
07,06
CONDITION
DESCRIPTION
Oevice
Identification
Signature
•
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may permanently damage the device.
PARAMETER
RATING
VOO Supply Voltage
7V
Storage Temperature
-65 to 150°C
Soldering Temperature (10 sec.)
260°C
Applied Voltage
-0.3 to VDD + 0.3V
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MAX
UNITS
5.5
V
3.0
VOO
V
2.0
VOO
V
0
0.8
MIN
CONDITIONS
4.5
VDD Supply voltage
NOM
Digital Pins
VIH, Input High Voltage
Reset, XTL 1 , XTL2
All other inputs
VIL, Input Low Voltage
IOH, Output High Current
IOL, Output Low Current
-40
TA, Operating Free-Air
Temperature
3-169
V
rnA
-0.4
1.6
rnA
+85
°C
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
RECOMMENDED OPERATING CONDITIONS
PARAMETER
(Continued)
CONDITIONS
MIN
NOM
VREF Bypass Capacitor
(External to GND)
0.1
Bias setting resistor
(Placed between VDD
and ISET pins)
1.8
ISET Bypass Capacitor
(ISET pin to GND)
0.1
J.lF
VDD Bypass Capacitor
(External to GND)
0.1
J.lF
MAX
UNITS
2.2
MQ
External Components*
J.lF
*Refer to Application section for placement.
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)
MIN
PARAMETER
CONDITIONS
100, Supply Current
ClK = 11.0592 MHz
NOM
MAX
UNITS
IDDA, Active
ISET Resistor = 2 MQ
10
rnA
IDD1, Power-down
ClK = 11.0592 MHz, ISET = GND
3
rnA
IDD2, Power-down
ClK = 19.200 KHz. ISET = GND
2
rnA
100
J.LA
J.LA
Digital Inputs
IIH, Input High Current
VI = VIH Max
Ill, Input low Current
VI = Vil Min
-200
Reset Pull-down Current
Reset = VDD
1
50
j.tA
VOH, Output High Voltage
10 = -0.4 rnA
2.4
VDD
V
VOL, Output low Voltage
10 = 1.6 rnA
0.4
V
Capitance. all Digital Input pins
10
pF
Digital Outputs
Capacitance
Inputs
XTl1 load Capacitor
Depends on crystal
39
pF
XTl2 load Capacitor
Depends on crystal
15
pF
ClK
Maximum Capacitive load
15
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C. VDD = Recommended range unless otherwise noted.)
NOTE: The following parameters expressed in dBmO refer to the following definition:
odB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
3-170
pF
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
MIN
CONDITIONS
NOM
MAX
UNITS
FSK Modulator
Output Freq. Error
ClK
= 11.0592 MHz
-0.38
+0.38
%
Transmit level
Transmit Dotting Pattern
-11
-9
dBmO*
Harmonic Distortion
in 700-2900 Hz band
THD in the alternate band FSK
-60
-50
dB
Transmit Dotting Pattern in ALB @ RXD
±5
Output Bias Distortion
Total Output Jitter
Random Input in ALB @ RXD
DTMF Generator
TR bit 04=1, CRO bit 01 = 1
Twist
Long Loop Detect
-15
+15
-0.25
+0.25
%
-10
-8
dBmO*
High Band
-8
-6
dBmO*
High-Band to low-Band, as above
1.0
3.0
dB
Not valid for
-38
-28
dBmO
Bell 202 V.23 back channel
Dynamic Range
Call Progress Detector
%
low Band
Freq. Accuracy
Output Amplitude
%
2.0
45
dB
Test signal is a 460 Hz sinusoid
Detect level
-39
0
dBmO
-45
dBmO
Delay Time
35
ms
Hold Time
35
Reject level
Hysteresis
Carrier Detect
2
For a sinusoid at
fr~q.
Threshold
ms
dB
= (Mark + Space)/2
-48
-43
dBmO
Delay Time
V.21
10
15
20
ms
103
8
15
20
ms
V.23 Main Channel RCV
6
10
12
ms
202 Main Channel RCV
6
8
12
ms
202, V.23 Back Channel
25
30
40
ms
V.21
6
10
20
ms
103
6
12
20
ms
202, V.23 Main Channel
3
6
8
ms
202, V.23 Back Channel
10
15
25
ms
Hold Time
2
Hysteresis
dB
* All transmit levels are at the default value of the transmit attenuator in CR3: 03-DO = 0100. Transmit range is
-6 dBmO to -22 dBmO nom.
3-171
•
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
PARAMETERS
(Continued)
CONDITIONS
MIN
Detect Level
See definitions for
TR bit DO mode
Delay Time
-70 dBmO to -30 dBmO step
NOM
MAX
UNITS
-49
-42
dBmO
10
25
ms
Special Tone Detectors
2100 Hz V.21 CCITI
Answer Tone
1300 Hz V.23 Mark
10
25
ms
390 Hz
V.23 Back Channel Mark
20
65
ms
980 or 1650 Hz V.21 Marks
10
25
ms
2225 Hz Bell Answer Tone
10
35
ms
4
10
ms
1200 Hz Bell 202
Main Channel Mark
10
25
ms
387 Hz Bell 202
Back Channel Mark
20
65
ms
1270 or 2225 Hz
Bell 103 Marks
10
30
ms
2100 Hz V.21 CCITI
Answer Tone
4
15
ms
900 Hz SCT tone
Hold Time
Assumes that SCT follows data in
a phase continuous manner
-30 dBmO to -70 dBmO step
1300 Hz V.23 Mark
3
10
ms
390 Hz
V.23 Back Channel Mark
10
25
ms
980 or 1650 Hz
V.21 Marks
5
15
ms
2225 Hz Bell
Answer Tone
4
15
ms
900 Hz SCT tone
1
10
ms
1200 Hz Bell 202
Main Channel Mark
3
10
ms
387 Hz Bell 202
Back Channel Mark
10
25
ms
1270 or 2225 Hz
Bell 103 Marks
4
15
ms
Hysteresis
Detect Freq. Range
2
Any Special Tone
-3
3-172
dB
+3
%
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
MIN
CONDITIONS
NOM
MAX
UNITS
Output Smoothing Filter
Output load
TXA pin; FSK Single
Tone out for THD = -50 dB
in .3 to 3.4 kHz
10
kn
Out of Band Energy
Frequency> 12 kHz in all modes
Output Impedance
TXA pin
200
300
n
TXA pin:
V.21 @ 61.44 kHz
103 @ 76.8 kHz
V.23 or 202 MC @ 122.88 kHz
V.23 or 202B @ 15.36 kHz
0.2
0.4
mVrms
Clock Noise
-60
dBmO
Timing (Refer to Timing Diagrams)
Parallel Mode
Tll
CS/Addr. setup before ALE
CS/Addr. hold after latch
latch to RD/WR control
RD/WR Control to latch
Data out from RD
ALE width
TRDF
Data float after READ
TAL
TlA
TlC
TCl
TRD
25
ns
20
ns
30
ns
-5
0
ns
140
ns
5
ns
ns
30
0
ns
TRW
READ width
200
25000
TWW
WRITE width
140
25000
TDW
Data setup before WRITE
40
ns
TWD
Data hold after WRITE
10
ns
ns
Serial Mode
1
2
TCKDR
Data out after ClK
TCKW
WRITE after elK
200
TDCK
Data setup before ClK
150
ns
TAW
Address setup before controi1
50
ns
ns
300
ns
ns
TWA
Address hold after controP
50
TWW
Write width
200
ns
TCKDW
Data hold after write
250
ns
TAR
Address setup before control 2
0
ns
TRA
Address hold after control 2
TRD
Data out from RD
TRDF
Data float after READ
Control for setup is the falling edge of WR.
Control for hold is the falling edge of WR.
Control for setup is the falling edge of RD or EXClK.
Control for hold is the falling edge of ADor EXClK.
3-173
400
0
ns
350
ns
100
ns
•
SSI73K312L
Bell 202, 103 and CCITT V.23, V.21
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
ALE
~
~
TlC
TRW
-,
1m
TCl
-,-
r
TlC
J
~D
TOW
"
--K ADDRESS } - - - K READ DATA}---K ADDRESS )i--{WRITE DATA}TLA
l
~
TWW
4.-
WR
ADO-AD7
.L
-=1-
TAL
'J
TRD
TRDF
~
~
-~-
-~-
-~-
READ TIMING DIAGRAM (SERIAL MODE)
EXClK
WRITE TIMING DIAGRAM (SERIAL MODE)
EXClK
HTWW
-----+----------------------------------------~~i
ADO-AD2
---+-------------------------i+A
AD7
3-174
SSI73K312L
Bell 202, 103 and CCITI V.23, V.21
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
(Top View)
44-Lead PLCC
ClK
GND
XTL1
RXA
XTL2
VREF
/6
N/C [
7
32
',?mtSW ::~i: tJ
31
5
RESET
ADO
AD1
ISET
AD2
RXClK
AD3
RXD
AD4
TXD
AD5
•
32-Lead PLCC
10
CS
AD6
EXClK
::::::ttMKr W::J:l
11
AD7
TXCLK
':'::Mptt dK il
12
ALE
1NT
WR
TXA
RD
VDD
13
21
14
N/C [
15
16
17
18
19
20
:~
17
18
19
29
27
P N/C
28
600-Mil
28-Pin DIP
32, 44-Pin PLCC
~
UJ
!!2
Q
:5 c
~
Q
Q
x
z a:: a::
z z
52 51
cx
~
Q
Q
z z
CD
C/)
()
:5
~
UJ
Q
Z
50 49 48 47 46 45 44 43 42 41
:5
()
0
c
x
«
~
::J
~
:J
~
x
x
::.c
-l
()
40
39
N/C
38
INTB
N,c
37
RXA
36
TXA
N,c
35
N/C
N,c
34
N/C
«
x
u..
Z
28
27
26
c
(!J
a::
UJ
a::
>
AD1
25
RESET
24
ISET
AD3
23
RXCLK
AD4
22
RXD
21
TXD
N/C
GND
33
VDD
NIC
32
N/C
AD6
10
20
CS
ClK
31
N/C
AD7
11
19
EXClK
N,c
30
RDB
XTAL1
29
WRB
XTAL2
28
N/C
N,c
27
ALE
15 16 17 18 19 20 21
22 23 24 25 26
12
13
14
15
16
17
18
UJ
I~ I&!
c
c
>
«
x
I~
::.c
-l
-l
«
~
()
x
~
28-Pin PLCC
0 c cM cV c c
~ ~ ~~
:s0
N/C
N/C
~ ~
~
64-Lead TQFP
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
SSI73K312L
28-Pin Dip
PKG.MARK
73K312L-IP
73K312L-IP
28-Lead PLCC
73K312L-281H
73K312L-281H
32-Lead PLCC
73K312L-321H
73K312L-321H
44-Lead PLCC
73K312L-IH
73K312L-IH
52-Lead QFP
73K312L~IG
73K312L-IG
64-Lead TQFP
73K312L-IGT
73K312L-IGT
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
0194 - rev.
3-176
Protected by the following patents: (4,691,172) (4,777,453)
©1989 Silicon Systems,lnc.
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
January 1994
DESCRIPTION
FEATURES
The 881 73K321 L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a CCITT V.23 and V.21 compatible modem,
capable of 0-300 bit/s full-duplex or 0-1200 bitls halfduplex operation over dial-up telephone lines. The
73K321 L provides 1200 bit/s operation in V.23 mode
and 300 biVs in V.21 mode. The 881 73K321 L also can
both detect and generate the 2100 Hz answer tone
needed for call initiation. The 881 73K321 L integrates
analog, digital, and switched-capacitor array functions
on a single substrate,offering excellent performance
and a high level of functional integration in a single 28or 22-pin DIP configuration. The 881 73K321 L operates from a single +5V supply with very low power
consumption.
•
One-chip CCITT V.23 and V.21 standard
compatible modem data pump
•
Full-duplex operation at 0-300 bit/s (V.21) or
0-1200 bit/s (V.23) forward channel with or
without 0-75 bits/s back channel
The 881 73K321 L includes the F8K modulator/demodulator functions, call progress and handshake
tone monitortest modes, and a tone generator capable
of producing DTMF, answer, calling tones. The
881 73K321 L is designed to appear to the systems
designer as a microprocessor peripheral, and will easily interface with popular one-chip microprocessors
(80C51 typical) for control of modem functions through
its 8-bit multiplexed address/data bus orvia an optional
serial control bus. An ALE control line simplifies address demultiplexing. Data communications occurs
through a separate serial port only.
(Continued)
•
•
Full Duplex 0-1200 bitls (V.23) In 4-wire mode
Pin and software compatible with other
8S1 K-Series 1-chlp modems
•
Interfaces directly with standard microprocessors (8048, 80C51 typical)
•
Serial or parallel microprocessor bus for
control
•
Serial port for data transfer
•
Call progress, carrier, precise answer tone
(2100 Hz), calling tone (1300 Hz) and FSK mark
detectors
•
DTMF generator
•
Test modes available: ALB, DL, RDL, Mark,
Space, Alternating bit patterns
•
PreCise automatic gain control allows 45 dB
dynamic range
•
8pace efficient 28-pin PLCC package available
•
CMOS technology for low power consumption
using 30 mW @ 5V from a single power supply
BLOCK DIAGRAM
PIN DIAGRAM
elK
ADO-AD7
'------'
XTL1
XTl2
TXA
ADO
AD1
RXA
AD2
AD3
SMART
DIALING
&
iN'f0-----!
FUO:C~~~S 1 4 - - - - - - - - '
TXDo-------~
RXDo--------L
I
AD4
AD5
ADS
AD7
ALE
vm
1m
0194 - rev.
3-177
•
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DESCRIPTION (Continued)
The SSI 73K321 L is ideal for either free standing or
integral system modem applications where multi-standard data communications over the 2-wire switched
telephone network is desired. Typical uses include
videotex terminals, low-cost integral modems and
built-in diagnostics for office automation or industrial
control systems. The 73K321 L's high functionality,low
p')wer consumption and efficient packaging simplify
design requirements and increase system reliability in
these applications. A complete modem requires only
the addition of the phone line interface, a control
microprocessor, and RS-232 level converter for a
typical system. The SSI 73K321 L is part of Silicon
Systems K-Series family of pin and function compatible single-chip modem products. These devices allow
systems to be configured for higher speeds and Bell or
CCITT operation with only a single component change.
OPERATION
FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. V.21 mode uses 980 and
1180 Hz (originate, mark and space) or 1650 and
1850 Hz (answer, mark and space). V.23 mode uses
1300 and 2100 Hz for the main channel and 390 and
450 Hz forthe back channel. The modulation rate of the
back channel is up to 75 baud. Demodulation involves
detecting the received frequencies and decoding them
into the appropriate binary value.
PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band Signals in the
receive channel. Amplitude and phase equalization
are necessary to compensate for distortion of the
transmission line and to reduce intersymbol interference in the bandlimited receive signal.
AGC
The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
receiver dynamic range of >45 dB.
PARALLEL BUS INTERFACE
Four 8-bit registers are provided for control, option
select and status monitoring. These registers are addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The detect registeris read only and
cannot be modified except by modem response to
monitored parameters. The parallel bus interface is not
available with the 22-pin package.
SERIAL COMMAND INTERFACE
The Serial Command mode allows access to the SSI
73K321 L control and status registers via a serial
command port. In this mode the AO , A1 and A2 lines
provide register addresses for data passed through the
data pin under control of the RD and WR lines. A read
operation is initiated when the RD line is taken low. The
first bit is available after RD is brought low and the next
seven cycles of EXCLK will then transfer out seven bits
of the selected address location LSB first. A write takes
place by shifting in eight bits of data LSB first for eight
consecutive cycles of EXCLK. WR is then pulsed low
and data transferred into the selected register occurs
on the rising edge of WR.
SPECIAL DETECT CIRCUITRY
The special detect circuitry monitors the received
analog signal to determine status or presence of carrier, answer tone and weak received signal (long loop
condition), special tones such as FSK marking and the
1300 Hz calling tone are also detected. A highly frequency selective call progress detector provides adequate discrimination to accurately detect European
call progress signals.
DTMF GENERATOR
The DTMF generator will output one of 16 standard
tone-pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Dialing is initiated when the DTMF mode is selected using the tone register and the transmit enable
(CRO bit D1) is changed from 0 to 1.
3-178
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
PIN DESCRIPTION
POWER
NAME
28-PIN
22-PIN
TYPE
DESCRIPTION
GND
28
1
I
System Ground.
VDD
15
11
I
Power supply input, 5V ±10%. Bypass with 0.1 and 22 ~F
capacitors to GND.
VREF
26
21
0
An internally generated reference voltage. Bypass with
0.1 ~F capacitor to GND.
ISET
24
19
I
Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 MQ resistor. ISET should be bypassed to GND with a
0.1 ~F capacitor.
PARAllEL MICROPROCESSOR INTERFACE
12
-
I
Address latch enable. The falling edge of ALE latches the
address on ADO-AD2 and the chip select on CS.
4-11
-
I/O
Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
registers.
CS
20
-
I
Chip select. A low during the falling edge of ALE on this pin
allows a read cycle or a write cycle to occur. ADO-AD7 will
not be driven and no registers will be written if CS (latched)
is not active. The state of CS is latched on the falling edge
of ALE.
CLK
1
2
0
Output clock. This pin is the output of the crystal oscillator
frequency only in the SSI 73K321.
INT
17
13
0
Interrupt. This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.
RD
14
-
i
Read. A low requests a read of the SSI 73K321 l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.
RESET
25
20
i
Reset. An active high signal high on this pin will put the chip
into an inactive state. All control register bits (CRO, CR1,
Tone) will be reset. The output of the ClK pin will be set to
the crystal frequency. An internal pull down resistor permits
power on reset using a capacitor to VDD.
ALE
ADO-AD7
3-179
•
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
PIN DESCRIPTION (Continued)
PARALLEL MICROPROCESSOR INTERFACE (Continued)
NAME
WR
28·PIN
22·PIN
TYPE
13
-
I
DESCRIPTION
Write. A low on this informs the SSI 73K321 L that data is
available on ADO-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.
SERIAL MICROPROCESSOR INTERFACE
AO-A2
-
5-7
DATA
-
RD
WR
Note:
I
Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.
8
I/O
Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.
-
10
I
Read. A low on this input informs the SSI 73K321 L that
data or status information is being read by the processor.
The falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.
-
9
I
Write. A low on this input informs the SSI73K321 L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the rising edge
ofWR.
In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the
pins; AO, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.
The Serial Control mode is provided in the 28-pin version by tying ALE high and CS low. In this
configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2, respectively.
3-180
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DTE USER INTERFACE
NAME
28-PIN
22-PIN
TYPE
DESCRIPTION
EXCLK
19
15
I
External Clock. Used for serial control interface to clock
control data in or out of the 73K321 L.
RXCLK
23
18
0
Receive Clock. A clock which is 16x1200,or16x 75 inV.23
mode, or 16 x 300 baud data rate is output in V.21.
RXD
22
17
0
Received Digital Data Output. Serial receive data is available on this pin. The data is always valid on the rising edge
of RXCLK when in Synchronous mode. RXD will output
constant marks if no carrier is detected.
TXCLK
18
14
0
Transmit Clock. TXCLK is always active. In V.23 mode the
output is either a 16 x 1200 baud clock or 16 x 75 baud, in
V.21 mode the clock is 16 x 300 baud.
TXD
21
16
I
Transmit Digital Data Input. Serial data for transmission is
input on this pin. In Asynchronous modes (1200 or 300
baud) no clocking is necessary.
ANALOG INTERFACE AND OSCILLATOR
RXA
27
22
I
Received modulated analog signal input from the phone
line.
TXA
16
12
0
Transmit analog output to the phone line.
XTL1
XTL2
2
3
3
4
I
I
These pins are for the internal crystal oscillator requiring
a 11.0592 MHz Parallel mode crystal and two load capacitors to Ground. XTL2 can also be driven from an external
clock.
3-181
•
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
REGISTER DESCRIPTIONS
Four 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AD and A 1
address lines in Serial mode, orthe ADO and AD1 lines
in Parallel mode. The ADO and AD1 lines are latched by
ALE. RegisterCRO controls the method by which data
is transferred over the phone line. CR1 controls the
interface between the microprocessor and the
SSI 73K321 L internal state. DR is a detect register
which provides an indication of Monitored modem
status conditions. TR, the tone control register, controls the DTM F generator, answer and guard tones and
RXD output gate used in the modem initial connect
sequence. All registers are read/write except for DR
which is read only. Register control and status bits are
identified below:
REGISTER BIT SUMMARY
CONTROL
REGISTER
1
CRO
000
CR1
001
CLK
CONTROL
RESET
TEST
MODE
1
TEST
MODE
0
LONG
LOOP
DETECT
REGISTER
DR
010
CARRIER
DETECT
SPECIAL
TONE
CALL
PROGRESS
TONE
CONTROL
REGISTER
TR
011
DTMF3
DTMF2I
V.23 FOX
DTMF1
CONTROL
REGISTER
2
CR2
100
CONTROL
REGISTER
3
CR3
101
10
110
10
REGISTER
NOTE:
When a register containing reserved
control bits is written into, the reserved bits
must be programmed as D's.
3-182
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
REGISTER ADDRESS TABLE
0.V.23 FSK
1=V.21 FSK
OOOO=PWR OOWN
11oo=FSK
0001.TRANSMIT DTMF, CALL PROGRESS DETECTION
O.DISABLE
TXAOUTPUT
1.ENABLE
TXAOUTPUT
IN V.21 MODE:
O=ANSWER
1.0RIGINATE
IN V.23 MODE:
O=RECEIVE@ 1200 BITIS,
TRANSM IT @ 75 BITIS
1.RECEIVE @ 75 BITIS,
TRANSMIT @ 1200 BITIS
•
O.HALF DUPLEX V.23
1-ALLOWS V.23 FULL
DUPLEX OPERATION
OOXX.73K212l, 322l, 321L
01XX.73K221l, 302L
10XX=73K222L
11oo.73K224L
1110=73K324L
1101.73K312L
3-183
o-ANSWER TONE FREO.-2225 Hz
FSK MARK Will BE INDICATED
BY SPECIAL TONE BIT IN DR
1.ANSWER TONE FREO.=2100 Hz
EITHER 2100 Hz (IN ORIG.) OR
1300 Hz (IN ANS.) WILL BE
INDICATED BY SPECIAL TONE
BITINDR
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
CONTROL REGISTER 0
D7
CRO
000
05
SIT NO.
00
02
01
00
TX OTMF
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
04
TRANSMIT TRANSMIT
MOOE3
MOOE 2
MODUL.
OPTION
NAME
CONDITION
Answer/
Originate
o
DESCRIPTION
Selects Answer mode in V.21 (transmit in high band,
receive in low band) or in V.23 mode, receive at
1200 biVs and transmit at 75 biVs.
Selects Originate mode in V.21 (transmit in low band,
receive in high band) or in V.23 mode, receive at 75 biVs
and transmit at 1200 biVs. If in V.23 and D2 of TR=1,
selects V.23 full duplex operation in 4-wire configuration.
Note: This bit works with TR bit 00 to program special
tones detected in Tone Register. See detect and tone
registers.
01
o
Transmit
Enable
Disables transmit output at TXA.
Note: Answer tone and OTMF TX control require TX
enable.
05,04,03,
02
Transmit
Mode
05 04 03 02
Transmit OTM F
o
02
06
Unused
07
Modulation
Option
0
0
o
0
Selects Power Down mode. All functions disabled except
ital interface.
Not used; must be written as a "0."
Selects:
FSK CCITT V.23 mode.
FSK CCITT V.21 mode.
3-184
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
CONTROL REGISTER 1
CR1
001
07
06
05
04
03
02
01
DO
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTER.
ADD
PH. Ea.
ClK
CONTROL
RESET
TEST
MODE
1
TEST
MODE
0
BIT NO.
NAME
CONDITION
01, DO
Test Mode
01 DO
02
DESCRIPTION
0
0
Selects Normal Operating mode.
0
1
Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced low.
1
0
Selects remote digitalloopback. Received data is looped
back to transmit data internally, and RXD is forced to a
mark. Data on TXD is ignored.
1
1
Selects local digitalloopback. Interna"y loops TXD back
to RXD and continues to transmit data from TXA pin.
Reset
0
Selects normal operation.
1
Resets modem to power down state. A" control register
bits (CRO, CR1, Tone) are reset to zero. Theoutputofthe
clock pin will be set to the crystal frequency.
Not supported in the SSI 73K321.See the TXClK and
RXClK pin descriptions for 16x the data rate clocks.
03
ClK Control
(Clock Control)
Program as
0
04
Add Ph. Eq.
0
Selects normal equalization.
1
In V.23 mode, additional phase equalization is added to
the main channel filters when 04 is set to 1.
0
Disables interrupt at INT pin. A" interrupts are
normally disabled in Power Down modes.
1
Enables INT output. An interrupt will be generated with
a change in status of OR bits 01-03. The special tone and
call progress detect interrupts are masked when the TX
enable bit is set. Carrier detect is masked when TX OTMF
is activated. A" interrupts wi" be disabled if the device is
in Power Oown mode.
05
Enable Detect
Interrupt
07,06
07 06
Transmit
Pattern
0
0
Selects normal data transmission as controlled by the
state of the TXO pin.
0
1
Selects an alternating mark/space transmit pattern for
modem testing.
1
0
Selects a constant mark transmit pattern.
1
1
Selects a constant space transmit pattern.
3-185
I
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DETECT REGISTER
DR
010
DO
Long Loop
01
Call Progress
Detect
02
SpeCial Tone
Detect
0
03
02
01
DO
CARR.
DETECT
SPECIAL
TONE
CALL
PROG.
LONG
LOOP
No call progress tone detected.
r------------r------------------------------------~
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in the
normal 350 to 620 Hz call progress band when C RO 02 = 1.
o
No special tone detected as programmed by
CRO bit DO and Tone Register bit DO.
(1) 2100 Hz answer tone if DO of TR=1 and the device is
in V.21 Originate mode.
(2) 1300 Hz calling tone if DO of TR=1 and the device is
in V.21 or V.23 Answer mode.
(3) an FSK mark forthe mode the device is set to receive
in if DO of TR = O.
03
05
06,07
Carrier Detect l-----~----__l_~~~~~~~~~~~~~~--------_I
Receive
Data
Continuously outputs the received data stream. This
data is the same as that output on the RXD pin, but it is
not disabled when RXD is tri-stated.
Not used.
3-186
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
TONE REGISTER
TR
011
07
06
05
04
03
02
01
RXO
OUTPUT
CONTR.
TRANSMIT
CALLING
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
OTMF
OTMF3
OTMF2
OTMF 1
BIT NO.
DO
NAME
CONDITION
OTMF 0/
Answer Tone/
06 05 04 DO
Special Tone/
Detect/Select
00
OTMF 0/
ANS. TONE/
SPECIAL
TONE/ SEL
DESCRIPTION
DO interacts with bits 06, 05, 04, and CRO as shown.
X
X
1
X
Transmit OTMF tones.
X
X
0
0
Mark of an FSK mode selected in CRO is to be detected
in 02 of DR.
X
X
0
1
2100 Hz answer tone will be detected in 02 of OR ifV.21
Originate mode is selected in CRO.
1300 Hz calling tone will be detected in 02 of DR if V.21
or V.23 Answer mode is selected in CRO.
X
1
0
0
Transmit 2225 Hz answer tone in Answer mode.
X
1
0
1
Transmit 2100 Hz answer tone in Answer mode.
03 02 01 DO
03,02,
01, DO
OTMF 3,
2,1,0
0
1
0
1
0 01 1
Programs 1 of 16 OTMF tone pairs that will be
transmitted when TX OTMF and TX enable bit (CRO, bit
01) is set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT
3-187
OTMF COOE
03 02 01 DO
TONES
LOW HIGH
1
0
0
0
1
697
1209
2
0
0
1
0
697
1336
3
0
0
1
1
697
1477
4
0
1
0
0
770
1209
5
0
1
0
1
770
1336
1477
6
0
1
1
0
770
7
0
1
1
1
852
1209
8
1
0
0
0
852
1336
9
1
0
0
1
852
1477
0
1
0
1
0
941
1336
I
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
TONE REGISTER (Continued)
BIT NO.
NAME
CONDITION
DESCRIPTION
KEYBOARD
EQUIVALENT
03,02,
01,00
.
(Cont.)
06
1
0
1
1
941
#
1
1
0
0
941
1477
A
1
1
0
1
697
1633
B
1
1
1
0
770
1633
C
1
1
1
1
852
1633
0
0
0
0
0
941
1633
Disabled DTMF.
1
Activates DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF
overrides all other transmit functions.
Transmit
Answer Tone
0
Disables answer tone generator.
1
Enables answer tone generator. A 21 00 Hz answer tone
will be transmitted continuously when the transmit enable bit is set. The device must be in Answer mode.
Transmit
Calling Tone
0
Disables calling tone generator.
1
Transmit calling tone in either mode.
RXD Output
Control
0
Enables RXD pin. Receive data will be output on RXD.
1
Disables RXD pin. The RXD pin reverts to a high impedance with internal weak pull-up resistor.
10 REGISTER
07
06
05
04
10
10
10
10
110
BIT NO.
NAME
CONDITION
07 06 05 04
07,06,05
04
1209
0
07
10
TONES
LOW HIGH
Transmit
DTMF
04
05
DTMFCODE
03 02 01 DO
DESCRIPTION
Indicates Device:
Device
Identification
Signature
3-188
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
VDD Supply Voltage
14V
Storage Temperature
-65 to 150°C
Soldering Temperature (10 sec.)
260°C
Applied Voltage
-0.3 to VDD+0.3V
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITIONS
MIN
NOM
VDD Supply voltage
4.5
5
5.5
V
TA, Operating Free-Air
Temperature
-40
+85
°C
-0.01
+0.01
%
2.2
MO
Clock Variation
(11.0592 MHz) Crystal or
external clock
MAX
UNITS
External Components (Refer to Application section for placement.)
VREF Bypass Capacitor
(External to GND)
0.1
Bias setting resistor
(Placed between VDD
and ISET pins)
1.8
J.lF
2
ISET Bypass Capacitor
(ISET pin to GND)
0.1
J.lF
VDD Bypass Capacitor 1
(External to GND)
0.1
J.lF
VDD Bypass Capacitor 2
(External to GND)
22
XTL 1 Load Capacitor
Depends on crystal characteristics;
40
XTL2 Load Capacitor
from pin to GND
20
3-189
J.lF
pF
I
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VDD = recommended range unless otherwise noted.)
PARAMETER
MIN
CONDITIONS
IDD1, Power-down
= 2 MQ
= 11.0592 MHz
ClK = 11 .0592 MHz
IDD2, Power-down
ClK = 19.200 kHz
100, Supply Current
IDDA, Active
NOM
MAX
UNITS
8
12
rnA
4
rnA
3
rnA
V
ISET Resistor
ClK
Digital Inputs
VIH, Input High Voltage
Reset, XTl1 , XTl2
3.0
VDD
All other inputs
2.0
VDD
V
0
0.8
V
100
~
Vll, Input low Voltage
IIH, Input High Current
VI = VIH Max
Ill, Input Low Current
VI = Vil Min
-200
Reset Pull-down Current
Reset = VDD
1
Input Capacitance
All Digital Input Pins
~
10
~
pF
VDD
V
50
Digital Outputs
VOH, Output High Voltage
IOH MIN = -0.4 rnA
2.4
VOL, Output low Voltage
10 MAX = 1.6 rnA
0.4
V
VOL, ClK Output
10=3.6mA
0.6
V
-50
~
15
pF
-1
RXD Tri-State Pull-up Curro
RXD=GND
CMAX, ClK Output
Maximum Capacitive Load
3-190
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = Recommended range unless otherwise noted.)
PARAMETERS
CONDITIONS
MIN
-0.35
NOM
MAX
UNITS
FSK Modulator
Output Freq. Error
CLK = 11.0592 MHz
Transmit Level
Transmit Dotting Pattern
Harmonic Distortion
in 700-2900 Hz band
TH 0 in the alternate band FSK
Output Bias Distortion
Transmit Dotting Pattern in ALB @ RXD
Total Output Jitter
Random Input in ALB @ RXD
-11
+0.35
%
-10
-9
dBmO
-60
-50
dB
+10
%
0/0
±3
-10
NOTE: Parameters expressed in dBmO refer to the following definition:
o dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
DTMF Generator
Freq. Accuracy
+0.25
%
Output Amplitude
Low Band, CRO bit 02=1
-10
-9
-8
dBmO
Output Amplitude
High Band, CRO bit 02=1
-8
-7
-6
dBmO
Twist
2.0
-0.25
High-Band to Low-Band, as above
1.0
Long Loop Detect
Not valid for V.23 back channel
-38
Dynamic Range
Refer to Performance Curves
3.0
dB
-28
dBmO
43
dB
Call Progress Detector
Detect Level
-3 dB points in 285 and 675 Hz
Reject Level
Test signal is a 460 Hz sinusoid
-45
dBmO
Delay Time
-70 dBmO to -30 dBmO STEP
40
ms
Hold Time
-30 dBmO to -70 dBmO STEP
40
ms
Hysteresis
-38
dBmO
2
dB
Carrier Detect
Threshold
Single Tone
-48
-43
V.21
10
20
ms
V.23 Forward Channel
6
12
ms
V.23 Back Channel
25
40
ms
V.21
6
20
ms
V.23 Forward Channel
3
8
ms
V.23 Back Channel
10
25
ms
dBmO
Delay Time
Hold Time
Hysteresis
2
3-191
dB
I
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
(Continued)
MAX
UNITS
-48
-43
dBmO
2100 Hz answer tone
10
25
ms
1300 Hz calling tone
10
25
ms
390 Hz
V.23 back channel mark
20
65
ms
980 or 1650 Hz
V.21 marks
10
25
ms
PARAMETERS
CONDITIONS
MIN
Detect Level
See definitions for
TR bit DO mode
Delay Time
-70 dBmO to -30 dBmO Step
NOM
Special Tone Detectors
Hold Time
-30 dBmO to -70 dBmO Step
2100 Hz answer tone
4
15
ms
1300 Hz calling tone
3
10
ms
390 Hz
V.23 back channel mark
10
25
ms
980 or 1650 Hz
V.21 marks
5
15
ms
2
Hysteresis
dB
%
Any Special Tone
-3
Output load
TXA pin; FSK Single
Tone out for THD = -50 dB
in .3 to 3.4 kHz
10
Out of Band Energy
Frequency> 12 kHz in all modes
Output Impedance
TXA pin, TXA Enabled
20
50
0
TXA pin; 76.8 kHz or
122.88 kHz in V.23 main channel
0.1
0.4
mVrms
Detect Freq. Range
+3
Output Smoothing Filter
Clock Noise
3-192
kO
50
pF
-60
dBmO
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
MIN
CONDITIONS
NOM
MAX
UNITS
Timing (Refer to Timing Diagrams)
"
TAL
CSI Addr. setup before ALE Low
25
ns
TLA
CS/Addr. hold after ALE Low
20
ns
TLC
ALE Low to RD/WR Low
30
ns
TCL
RD/WR Control to ALE High
TRD
Data out from RD Low
TLL
ALE width
TRDF
Data float after RD High
TRW
RDwidth
TWW
WR width
-5
0
30
0
200
140
TOW
Data setup before WR High
40
ns
TWO
Data hold after WR High
10
ns
TCKD
Data out after EXCLK Low
TCKW
WR after EXCLK Low
TDCK
Data setup before EXCLK Low
TAC
Address setup before control"
TCA
Address hold after control*
TWH
Data Hold after EXCLK
Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.
3-193
ns
140
ns
5
ns
25000
25000
ns
ns
200
ns
ns
150
150
ns
50
50
20
ns
ns
ns
I
SSI73K321L
CClll V.23, V.21
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
~
ALE
~
~
TlC
AD
TRW
J
TCl
J
-,-
-r
TlC
~ TAL --..
ADO-AD7
(;S'
J
-+
WR'
--K
-='}-
TLA
"J
ADDRESS
TRD
TRDF
~
>t----K
~
READ DATA
>t----K
-~-
-~-
ADDRESS
TWW
.I
~D
>t----K
TOW
'"
WRITE DAT1-
-~-
READ TIMING DIAGRAM (SERIAL VERSION)
EXClK
AO-A2
DATA
--+
WRITE TIMING DIAGRAM (SERIAL VERSION)
EXClK
HTWW
-----+----------------------------------------r-~i
TCKW
AO-A2
----+---------------------------I*-A
DATA
3-194
I~
I~
TCA
SSI73K321L
CCITT V.23, V.21
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(TOP VIEW)
ClK
GND
RXA
XTl2
VREF
RXA
VREF
XTll
RESET
Al
VDD
GND
XTll
ADO
RESET
ADl
ISET
AD2
RXClK
ISET
AD3
RXD
RXClK
AD4
TXD
RXD
ADS
cs
TXD
AD6
EXClK
EXClK
AD7
TXClK
TXClK
ALE
TNT
INT
WR
TXA
TXA
AD
VDD
400-Mil
22-Pin DIP
4
3 2
1262726
25
24
6
PLCC PINOUTS
ARE THE SAME AS
THE 28-PIN DIP
10
11
23
22
21
20
19
12 13 14 15 16 17 16
28-Pin
PLCC
600-Mil
28-Pin DIP
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
SSI 73K321 L with Parallel Bus Interface
28-Pin 5V Supply
Plastic Dual-In-Line
73K321 L-IP
73K321 L-IP
Plastic Leaded Chip Carrier
73K321 L-IH
73K321 L-IH
73K321 SL-IP
73K321 SL-IP
SSI 73K321 L with Serial Interface
22-Pin 5V Supply
Plastic Dual-In-Line
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents. patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly. the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems. Inc .• 14351 Myford Road. Tustin. CA 92680-7022. (714) 573-6000. FAX: (714) 573-6914
~92
- rev.
3-195
Protected by the following patents: (4.691.172) (4.777.453)
©1989 Silicon Systems. Inc.
•
Notes:
3-196
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
January 1994
DESCRIPTION
FEATURES
The SSI 73K322L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a CCITT V.23, V.22 and V.21 compatible
modem, capable of 1200 or 0-300 bit/s full-duplex
operation or 0-1200 biVs half-duplex operation with or
without the back channel over dial-up lines. The
SSI 73K322L is an enhancement of the SSI 73K221 L
single-chip modem with performance characteristics
suitable for European and Asian telephone systems.
The SSI 73K322L produces either 550 or 1800 Hz
guard tone, recognizes and generates a 2100 Hz
answer tone, and supports V.21 for 300 Hz FSK
operation. It also operates in V.23, 1200 biVs FSK
mode. The SSI73K322L integrates analog, digital, and
switched-capacitor array functions on a single
substrate,offering excellent performance and a high
level of functional integration in a single 28- or 22-pin
DIP configuration. The SSI 73K322L operates from a
single +5V supply with very low power consumption.
The SSI 73K322L includes the DPSK and FSK
modulator/demodulator functions, call progress and
handshake tone monitor test modes, and a tone
generator capable of producing DTMF, answer, calling
and 550 or 1800 Hz guard tone. This device supports
V.23, V.22 (except mode v) and V. 21 modes of
operation, allowing both synchronous and
One-chip CCITT V.23, V.22 and V.21 standard
compatible modem data pump
Full-duplex operation at 0-300 bitls (FSK) or 600 and
1200 bitls (OPSK) or 0-1200 bitls (FSK) forward
channel with or without 0-75 bit/s back channel
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Serial or parallel microprocessor bus for control
Serial port for data transfer
Both synchronous and asynchronous modes of
operation
Call progress, carrier, precise answer tone
(2100 Hz), calling tone (1300 Hz) and FSK mark
detectors
DTMF and 550 or 1800 Hz guard tone generators
Test modes available: ALB, OL, ROL, Mark, Space,
Alternating bit patterns
Precise automatic gain control allows 45 dB
dynamic range
CMOS technology for low power consumption
using 30 mW @ 5V from a single power supply
Surface mount PLCC package available
(Continued)
BLOCK DIAGRAM
PIN DIAGRAM
MJO-MJ7
1m
TXA
WIf
ALE
-cs
RXA
RESET
TXD
RXD
0-------1Iooi
o--------L_-----1
CAUTION: Use handling procedures necessary
for a static sensitive component.
0194 - rev.
3-197
•
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
DESCRIPTION (continued)
asynchronous communications. The SSI 73K322L is
designed to appear to the systems designer as a
microprocessor peripheral, and will easily interface
with popular one-chip microprocessors (80C51 typical) for control of modem functions through its 8-bit
multiplexed address/data bus or via an optional serial
control bus. An ALE control line simplifies address
demultiplexing. Data communications occurs through
a separate serial port only.
The SSI73K322L is ideal for use in either free standing
or integral system modem products where multi-standard data communications over the 2-wire switched
telephone network is desired. Its high functionality, low
power consumption and efficient packaging simplify
design requirements and increase system reliability. A
complete modem requires only the addition of the
phone line interface, a control microprocessor, and
RS-232 level converter for a typical system. The
SSI 73K322L is part of Silicon Systems K-Series family
of pin and function compatible single-chip modem
products. These devices allow systems to be configured for higher speeds and Bell or CCITT operation
with only a single component change.
OPERATION
ASYNCHRONOUS MODE
Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous fashion. The SSI 73K322L includes ASYNC/SYNC and
SYNC/ASYNC converters which delete or insert stop
bits in order to transmit data at a regular rate. In
Asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC converter. The
ASYNC/SYNC converter accepts the data provided on
the TXD pin which normally must be 1200 or 600 bitls
+ 1.0%, -2.5%. The rate converter will then insert or
delete stop bits in orderto output a signal which is 1200
or 600 biVs± 0.01% (± 0.01% is the crystal tolerance).
The SYNC/ASYNC converter also has an extended
overspeed mode which allows selection of an output
overspeed range of either +1% or +2.3%. In the extended overspeed mode, stop bits are output at 7/8 the
normal width.
The serial data stream from the transmit buffer or the
rate converter is passed through the data scrambler
and onto the analog modulator. The data scrambler
can be bypassed under processor control when
unscrambled data must be transmitted. If serial input
data contains a break signal through one character
(including start and stop bits) the break will be
extended to at least 2 • N + 3 bits long (where N is the
number of transmitted bits/character).
Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC converter. The ASYNC/ASYNC converterwill reinsert any deleted stop bits and output data
at an intra-character rate (bit-to-bit timing) of no greater
than 1219 bit/so An incoming break signal (low through
two characters) will be passed through without incorrectly inserting a stop bit.
SYNCHRONOUS MODE
The CCITT V.22 standard defines synchronous operation at 600 and 1200 bit/so Operation is similarto that of
the Asynchronous mode except that data must be
synchronized to a provided clock and no variation in
data transfer rate is allowable. Serial input data appearing at TXD must be valid on the rising edge of
TXCLK.
TXCLK is an internally derived signal in Internal mode
and is connected internally to the RXCLK pin in Slave
mode. Receive data at the RXD pin is clocked out on
the falling edge of RXCLK. The ASYNCH/SYNCH
converter is bypassed when Synchronous mode is
selected and data is transmitted out at the same rate as
it is input.
DPSK MODULATOR/DEMODULATOR
In DPSK mode the SSI 73K322L modulates a serial bit
stream into di-bit pairs that are represented by four
possible phase shifts as prescribed by the V.22 standards. The base-band signal is then filtered to reduce
intersymbol interference on the bandlimited 2-wire
telephone line. Transmission occurs using either a
1200 Hz (Originate mode) or 2400 Hz carrier (Answer
mode). Demodulation is the reverse of the modulation
process, with the incoming analog signal eventually
decoded into di-bits and converted back to a serial bit
stream. The demodulator also recovers the clock
which was encoded into the analog signal during
modulation. Demodulation occurs using either a
1200 Hz carrier (Answer mode or ALB Originate mode)
or a 2400 Hz carrier (Originate mode or ALB Answer
mode). The SSI 73K322L uses a phase locked loop
coherent demodulation technique for optimum
receiver performance.
3-198
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. V.21 mode uses 980 and
1180 Hz (originate, mark and space) or 1650 and
1850 Hz (answer, mark and space). V.23 mode uses
1300 and 2100 Hz for the main channel and 390 and
450 Hz for the back channel. The modulation rate of
the back channel is up to 75 baud. Demodulation
involves detecting the received frequencies and
decoding them into the appropriate binary value. The
rate converter and scrambler/descrambler are automatically bypassed in the V.21 or V.23 modes.
PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay equalization and rejection of out-of-band signals in the
receive channel. Amplitude and phase equalization
are necessary to compensate for distortion of the
transmission line and to reduce intersymbol interference in the bandlimited receive signal. The transmit
signal filtering approximates a 75% square root of
raised Cosine frequency response characteristic.
AGC
The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
receiver dynamic range of >45 dB.
passed through the data pin under control of the RD
and WR lines. A read operation is initiated when the RD
line is taken low. The first bit is available after RD is
brought low and the next seven cycles of EXCLK will
then transfer out seven bits of the selected address
location LSB first. Awrite takes place by shifting in eight
bits of data LSB first for eight consecutive cycles of
EXCLK. WR is then pulsed low and data transferred
into the selected register occurs on the rising edge
ofWR.
SPECIAL DETECT CIRCUITRY
The special detect circuitry monitors the received
analog signal to determine status or presence of carrier, answer tone and weak received signal (long loop
condition), special tones such as FSK marking and the
1300 Hz calling tone are also detected. A highly frequency selective call progress detector provides adequate discrimination to accurately detect European
call progress signals.
DTMF GENERATOR
The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode
is selected using the tone register and the transmit
enable (CRO bit D1) is changed from 0 to 1.
PARALLEL BUS INTERFACE
Four 8-bit registers are provided for control, option
select and status monitoring. These registers are addressed with the ADO, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations. Two control registers and the tone register are
read/write memory. The detect registeris read only and
cannot be modified except by modem response to
monitored parameters.
SERIAL COMMAND INTERFACE
The serial command interface allows access to the
SSI 73K322L control and status registers via a serial
command port (22-pin version only). In this mode the
AO , A 1 and A2lines provide register addresses for data
3-199
•
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
PIN DESCRIPTION
POWER
28-PIN
22-PIN
TYPE
DESCRIPTION
GND
NAME
28
1
I
System Ground.
VDD
15
11
I
Power supply input, 5V ±1 0%. Bypass with 0.1 and 22 J.1F
capacitors to GND.
VREF
26
21
0
An internally generated reference voltage. Bypass with
0.1 J.1F capacitor to GND.
ISET
24
19
I
Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 MQ resistor. ISET should be bypassed to GND with a
0.1 J.1F capacitor.
PARALLEL MICROPROCESSOR INTERFACE
12
-
I
Address latch enable. The falling edge of ALE latches the
address on ADO-AD2 and the chip select on CS.
4-11
-
I/O
Address/data bus. These bidirectional tri-state multiplexed lines carry information to and from the internal
registers.
CS
20
-
I
Chip select. A low on this pin during the falling edge of ALE
allows a read cycle or a write cycle to occur. ADO-AD7 will
not be driven and no registers will be written if CS (latched)
is not active. The state of CS is latched on the falling edge
of ALE.
ClK
1
2
0
Output clock. This pin is selectable under processor control
to be either the crystal frequency (for use as a processor
clock) or 16 x the data rate for use as a baud rate clock in
DPSK modes only. The pin defaults to the crystal frequency
on reset.
INT
17
13
0
Interrupt. This open drain output signal is used to inform the
processor that a detect flag has occurred. The processor
must then read the detect register to determine which
detect triggered the interrupt. INT will stay low until the
processor reads the detect register or does a full reset.
RD
14
-
I
Read. A low requests a read of the SSI 73K322l internal
registers. Data cannot be output unless both RD and the
latched CS are active or low.
RESET
25
20
I
Reset. An active high Signal on this pin will put the chip into
an inactive state. All control register bits (CRO, CR1, Tone)
will be reset. The output of the ClK pin will be set to the
crystal frequency. An internal pull down resistor permits
power on reset using a capacitor to VDD.
ALE
ADO-AD7
3-200
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
PARALLEL MICROPROCESSOR INTERFACE (Continued)
NAME
WR
28-PIN
22-PIN
TYPE
13
-
I
DESCRIPTION
Write. A low on this informs the SSI73K322L that data is
available on ADO-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.
SERIAL MICROPROCESSOR INTERFACE
AO-A2
-
5-7
DATA
-
RD
WR
Note:
I
Register Address Selection. These lines carry register
addresses and should be valid during any read or write
operation.
8
I/O
Serial Control Data. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.
-
10
I
Read. A low on this input informs the SSI73K322L that data
or status information is being read by the processor. The
falling edge of the RD signal will initiate a read from the
addressed register. The RD signal must continue for eight
falling edges of EXCLK in order to read all eight bits of the
referenced register. Read data is provided LSB first. Data
will not be output unless the RD signal is active.
-
9
I
Write. A low on this input informs the SSI73K322L that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on
the DATA pin for eight consecutive falling edges of EXCLK
and then to pulse WR low. Data is written on the rising edge
ofWR.
In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the
pins; AO, A 1, A2, DATA, and an unconnected pin. Also, the RD and WR controls are used differently.
The Serial Control mode is provided in the parallel control versions by tying ALE high and CS low.
In this configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2,
respectively.
DTE USER INTERFACE
NAME
28-PIN
22-PIN
TYPE
EXCLK
19
15
I
DESCRIPTION
External Clock. This signal is used only in synchronous
DPSK transmission when the external timing option has
been selected. In the External Timing mode the rising edge
of EXCLK is used to strobe synchronous DPSK transmit
data available on the TXD pin. Also used for serial control
interface.
3-201
•
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
RS-232 INTERFACE
(Continued)
NAME
28-PIN
22-PIN
TYPE
DESCRIPTION
RXCLK
23
18
0
Receive Clock. The falling edge of this clock output is
coincident with the transitions in the serial received DPSK
data output. The rising edge of RXCLK can be used to latch
the valid output data. RXCLK will be valid as long as a
carrier is present. In V.23 or V.21 mode a clock which is
16 x1200 (or 16 x 75) or 16 x 300 Hz baud data rate is
output, respectively, for driving a UART.
RXD
22
17
0
Received Data Output. Serial receive data is available on
this pin. The data is always valid on the rising edge of
RXCLK when in Synchronous mode. RXD will output
constant marks if no carrier is detected.
TXCLK
18
14
0
Transmit Clock. This signal is used only in synchronous
DPSK transmission to latch serial input data on the TXD
pin. Data must be provided so that valid data is available
on the rising edge of the TXCLK. The transmit clock is
derived from different sources depending upon the Synchronization mode selection. In Internal Mode the clock is
1200 Hz generated internally. In External Mode TXCLK is
phase locked to the EXCLK pin. In Slave Mode TXCLK is
phase locked to the RXCLK pin. TXCLK is always active. In
V.23 or V.21 mode the output is a 16 x 1200 (or 16 x 75) or
16 x 300 Hz baud clock, respectively for driving a UART.
TXD
21
16
I
Transmit Data Input. Serial data fortransmission is applied
on this pin. In Synchronous modes, the data must be valid
on the rising edge of the TXCLK clock. In Asynchronous
modes (1200 or 300 baud) no clocking is necessary. DPSK
must be 1200/600 biVs +1%, -2.5% or +2.3%, -2.5 % in
Extended Overspeed mode.
ANALOG INTERFACE AND OSCILLATOR
RXA
27
22
I
Received modulated analog signal input from the telephone line interface.
TXA
16
12
0
Transmit analog output to the telephone line interface.
XTL1
XTL2
2
3
3
4
I
I
These pins are for the internal crystal oscillator requiring
a 11.0592 MHz Parallel mode crystal and two load capacitors to Ground. XTL2 can also be driven from an external
clock.
3-202
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
REGISTER DESCRIPTIONS
Four 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO and A 1
address lines in Serial mode, orthe ADO and AD1lines
in Parallel mode. The ADO and AD1 lines are latched by
ALE. Register C RO controls the method by which data
is transferred over the phone line. CR1 controls the
interface between the microprocessor and the
SSI 73K322L internal state. DR is a detect register
which provides an indication of monitored modem
status conditions. TR, the tone control register, controlsthe DTMF generator, answerandguardtonesand
RXD output gate used in the modem initial connect
sequence. All registers are read/write except for DR
which is read only. Register control and status bits are
identified below:
REGISTER BIT SUMMARY
CONTROL
REGISTER
CRO
000
CRl
001
1
DETECT
REGISTER
DR
010
TONE
CONTROL
REGISTER
TR
011
CONTROL
REGISTER
2
CR2
100
CONTROL
REGISTER
CR3
101
10
110
I
ENABLE
DETECT
INTERRUPT
BYPASS
SCRAMBLER!
ADD PH. EQ.
(V.23)
RECEIVE
DATA
3
10
REGISTER
NOTE:
When a register containing reserved
control bits is written into, the reserved bits
must be programmed as O's.
3-203
CLK
CONTROL
RESET
UNSCR.
MARKS
CARRIER
DETECT
SPECIAL
TONE
TRANSMIT
DTMF
DTMF3
DTMF2I
V.23 FOX
TEST
MODE
TEST
MODE
1
0
CALL
PROGRESS
LONG
LOOP
DTMFll
OVERSPEED
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
REGISTER ADDRESS TABLE
0.1200 BITIS DPSK
1=600 BITIS DPSK
O.V.23 FSK
1.V.21 FSK
oooo.PWR DOWN
000l.INT SYNCH
0010.EXT SYNCH
0011.SLAVE SYNCH
0100.ASYNCH 8 BITSiCHAR
0101.ASYNCH 9 BITSiCHAR
0110.ASYNCH 10 BITSICHAR
0111.ASYNCHll BITs/CHAR
1100.FSK
O.DISABLE
TXAOUTPUT
1.ENABLE
TXAOUTPUT
IN V.21 OR V.22 MODE:
O.ANSWER
1.ORIGINATE
IN V.23 MODE:
O.RECEIVE @ 1200 BITIS.
TRANSMIT @ 75 BITIS
1.RECEIVE @75 BITIS.
TRANSMIT@ 1200 BITIS
O.XTAL
1.16X DATA
RATE OUTPUT
ATCLK PIN IN
DPSKMODE
ONLY
O.NORMAL
l=ALLOWS V.23 FULL
DUPLEX OPERATION
00XX.73K212L. 322L. 321L
01XX.73K221 L. 302L
10XX.73K222L
1100.73K224L
1110.73K324L
1101.73K312L
3-204
0.1800 Hz G.T. (V.22).
2225 Hz ANS TONE
GENERATED. FSK
MARK DETECT
SELECTED
1=550 Hz G.T. (V.22)
2100 Hz ANS TONE
GENERATED &
DETECTED (V.21. V.22)
1300 Hz DETECTED (V.23)
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
CONTROL REGISTER 0
CRO
000
07:11: 05
MODUL.
OPTION
BIT NO.
DO
high
::,'
.:,'
04
03
02
01
TRANSMIT TRANSMIT TRANSMIT TRANSMIT TRANSMIT
MODE 3
MODE 2
ENABLE
MODE 1
MODE 0
DO
ANSWER/
ORIGINATE
NAME
CONDITION
Answer/
0
Originate
Selects Answer mode in V.21 and V.22 (transmit in
band), receive in low band or in V.23 HDX mode,
receive at 1200 biVs and transmit at 75 bit/so
1
Selects Originate mode in V.21 and V.22 (transmit in
low band),receive in high band or in V.23 HDX mode,
receive at 75 biVs and transmit at 1200 bit/so
DESCRIPTION
Note: This bit works with TR bit DO to program special
tones detected in Tone Register. See detect and tone
registers.
01
0
Transmit
Enable
Disables transmit output at TXA.
1
Enables transmit output at TXA.
Note: Answer tone and DTMF TX control require TX
enable.
05 04 03 02
05,04,03,
02
Transmit
Mode
0
0
0
0
Selects Power Down mode. All functions disabled
except digital interface.
0
0
0
1
Internal Synchronous mode. In this mode TXCLK is an
internally derived 1200 Hz signal. Serial input data
appearing at TXD must be valid on the rising edge of
TXCLK. Receive data is clocked out of RXD on the
falling edge of RXCLK.
0
0
1
0
External Synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internallyto EXCLK pin, and a 1200 Hz± 0.01%clock must
be supplied externally.
0
0
1
1
Slave Synchronous mode. Same operation as other
Synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.
0
1
0
0
Selects DPSK Asynchronous mode - 8 bits/character
(1 start bit, 6 data bits, 1 stop bit).
0
1
0
1
Selects DPSK Asynchronous mode - 9 bits/character
(1 start bit, 7 data bits, 1 stop bit).
0
1
1
0
Selects DPSK Asynchronous mode - 10 bits/character
(1 start bit, 8 data bits, 1 stop bit).
0
1
1
1
Selects DPSK Asynchronous mode - 11 bits/character
(1 start bit, 8 data bits, Parity and 1 or 2 stop bits).
1
1
o
0
Selects FSK
3-205
I.
•
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
CONTROL REGISTER 0 (Continued)
07
CRO
000
05
MODUL.
OPTION
SIT NO.
04
TRANSMIT TRANSMIT
MODE 3
MODE 2
NAME
CONDITION
07 05 04
07
03
02
01
DO
TRANSMIT TRANSMIT TRANSMIT
MODE 1
MODE 0
ENABLE
ANSWER/
ORIGINATE
DESCRIPTION
Selects:
Modulation
Option
FSK CCITT V.21 mode.
CONTROL REGISTER 1
CR1
001
SIT NO.
07
06
05
04
03
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTER.
BYPASS
SCRAMB/
ADD
PH. Ea.
ClK
CONTROL
NAME
CONDITION
02
01
DO
RESET
TEST
MODE
1
TEST
MODE
0
DESCRIPTION
01 DO
01, DO
02
Test Mode
Reset
0
0
Selects normal operating mode.
0
1
Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be
forced low.
1
0
Selects remote digital loopback. Received data is
looped back to transmit data internally, and RXD is
forced to a mark. Data on TXD is ignored.
1
1
Selects local digital loopback. Internally loops TXD
back to RXD and continues to transmit carrier from
TXA pin.
0
Selects normal operation.
1
Resets modem to power down state. All control register bits (CRO, CR1, Tone) are reset to zero. The output
of the ClK pin will be set to the crystal frequency.
3-206
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
CONTROL REGISTER 1
CR1
001
BIT NO.
03
D4
05
(Continued)
D7
D6
D5
D4
D3
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
ENABLE
DETECT
INTER.
BYPASS
SCRAMB/
ADD
PH. EQ.
ClK
CONTROL
NAME
0
CONDITION
ClK Control
D2
D1
DO
RESET
TEST
MODE
1
TEST
MODE
0
DESCRIPTION
0
Selects 11.0592 MHz crystal echo output at ClK
pin.
1
Selects 16 X the data rate, output at ClK pin in DPSK
modes only.
Bypass
Scrambler/
0
Selects normal operation. DPSK data is passed
through scrambler.
Add Phase
Equalization
1
Selects Scrambler Bypass. OPSK data is routed
around scrambler in the transmit path. In V.23 mode,
additional phase equalization is added to the main
channel filters when D4 is set to 1.
Enable Detect
0
Disables interrupt at INT pin.
1
Enables INT output. An interrupts will be generated
with a change in status of DR bits D1-D4. The special
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TX DTMF is activated. All interrupts will be
disabled if the device is in power down mode.
D7 D6
07,06
Transmit
Pattern
0
0
Selects normal data transmission as controlled by the
state of the TXD pin.
0
1
Selects an alternating mark/space transmit pattern for
modem testing.
1
0
Selects a constant mark transmit pattern.
1
1
Selects a constant space transmit pattern.
3-207
I
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
DETECT REGISTER
DR
010
BIT NO.
D5
D4
D3
D2
D1
DO
RECEIVE
DATA
UNSCR.
MARK
CARR.
DETECT
SPECIAL
TONE
CALL
PROG.
LONG
LOOP
NAME
CONDITION
DO
Long Loop
0
D1
Call Progress
Detect
D2
Special Tone
Detect
DESCRIPTION
I
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in
the normal 350 to 620 Hz call progress band.
0
No special tone detected as programmed by C RO bit DO
and Tone Register bit DO.
(1 ) 2100 Hz answer tone if DO of TR=1 and the device
is in V.21 or V.22 originate mode.
(2) 1300 Hz calling tone if DO of TR=1 and the device
is in V.21, or V.22 answer mode.
(3) an FSK mark in the mode the device is set to
receive.
D3
Carrier Detect
Indicated carrier has been detected in the received
channel.
D4
D5
D6,D7
Unscrambled
Mark
Receive
Data
0
No
Indicates detection of unscrambled marks in
the received data. A valid indication requires that
unscrambled marks be received for> 165.5 ± 6.5 ms.
Continuously outputs the received data stream. This
data is the same as that output on the RXD pin, but it
is not disabled when RXD is tri-stated.
Not used.
3-208
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
TONE REGISTER
TR
011
07
06
05
04
RXO
OUTPUT
CONTR.
TRANSMIT
GUAROI
CALLING
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
OTMF
BIT NO.
DO
NAME
CONDITION
03
01
02
DO
OTMF 21 OTMF 11
OTMF 01
OTMF3 V.23 FOX OVER- G.T.lANSW'/
SPEED
SP. TONE!
SELECT
DESCRIPTION
06 05 04 DO
DO interacts with bits 06, 04, and CRO as shown.
OTMFO
X
X
1
X
Transmit OTMF tones.
Guard Tonel
Answer Tone
1
X
0
0
Select 1800 Hz guard tone if in V.22 and Answer mode
inCRO.
Special T onel
OetecVSelect
1
X
0
1
Select 550 Hz guard tone if in V.22 and Answer mode
in CRO.
X
X
0
0
Mark of an FSK mode selected in CRO is to be detected
in 02 of DR.
X
X
0
1
2100 Hz answer tone will be detected in 02 of DR if
V.21 or V.22 Originate mode is selected in CRO.
1300 Hz calling tonewill be detected in 020f DR ifV.21,
or V.22 Answer mode is selected in CRO.
X
1
0
0
Transmit 2225 Hz Answer Tone
X
1
0
1
Transmit 2100 Hz Answer Tone
01 interacts with 04 as shown.
04 01
01
OTMF 11
Overspeed
02
OTMF 21
V.23 FOX
0
Asynchronous OPSK 1200 or 600 bitls +1.0% -2.5%.
0
0
Asynchronous OPSK 1200 or 600 bitls +2.3% -2.5%.
1
0
Half-duplex asymetric operation in V.23 mode.
1
Full-duplex (4-wire) operation in V.23 mode.
03 02 01 DO
03,02,
OTMF 3,
0
0
0 0-
Programs 1 of 16 OTMF tone pairs that will be
01,00
2,1,0
1
1
1
transmittedwhenTX OTMF andTXenable bit (CRO, bit
01) are set. Tone encoding is shown below:
1
KEYBOARD
EQUIVALENT
3-209
OTMF CODE
03 02 01 DO
TONES
LOW HIGH
1
0
0
0
1
697
1209
2
0
0
1
0
697
1336
3
0
0
1
1
697
1477
4
0
1
0
0
770
1209
5
0
1
0
1
770
1336
6
0
1
1
0
770
1477
7
0
1
1
1
852
1209
•
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
TONE REGISTER (Continued)
TR
011
07
06
05
04
RXD
OUTPUT
CONTR.
TRANSMIT
GUARD/
CALLING
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
BIT NO.
NAME
CONDITION
03,02,
01,00
03
KEYBOARD
EQUIVALENT
07
DTMFCODE
03 02 01 DO
TONES
LOW HIGH
1
0
0
1
0
0
0
1
852
9
852
1336
1477
0
1
0
1
0
941
1336
1
0
1
1
941
1209
1
1
0
941
1477
1
1
0
0
1
697
1633
#
A
06
DO
DTMF 0/
GUARD/
SPECIAL
TONESEL
8
..
05
01
DESCRIPTION
(Cont.)
04
02
DTMF 2/ DTMF 1/
DTMF3 V.23 FOX OVERSPEED
B
1
1
1
0
770
1633
C
1
1
1
1
852
1633
0
0
0
0
0
941
1633
Transmit
DTMF
0
Disable DTMF.
1
Activate DTMF.The selected DTMF tones are
transmitted continuously when this bit is high.
TX DTM F overrides all other transmit functions.
Transmit
Answer Tone
0
Disables answer tone generator.
1
Enables answer tone generator. A 2100 Hz answer
tone will be transmitted continuously when the transmit
enable bit is set. The device must be in Answer mode.
To transmit answer tone, the device must be in DPSK
Answer mode.
TX Guard or
Calling Tone
0
Disables guard/calling tone generator.
1
Transmit guard tone if in V.22 and answering;
otherwise transmit calling tone, in any other mode
including V.23 mode.
0
Enables RXD pin. Receive data will be output on
RXD.
1
Disables RXD pin. The RXD pin reverts to a high
impedance with internal weak pull-up resistor.
RXD Output
Control
3-210
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
10 REGISTER
ID
110
D7
D6
D5
D4
ID
ID
ID
ID
NAME
BIT NO.
CONDITION
DESCRIPTION
D7 D6 D5 D4
D7,D6,D5
D4
Indicates Device:
Device
Identification
•
Signature
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
VDD Supply Voltage
14
V
Storage Temperature
-65 to 150
°C
260
°C
-0.3 to VDD+0.3
V
Soldering Temperature (10 sec.)
Applied Voltage
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
VDD Supply voltage
4.5
5
5.5
V
TA, Operating Free-Air Temp.
-40
+85
°C
-0.01
+0.01
0/0
2.2
MQ
PARAMETER
Clock Variation
CONDITIONS
(11.0592 MHz) Crystal or external clock
MAX
UNITS
External Components (Refer to Application section for placement.)
VREF Bypass Capacitor
(External to GND)
0.1
Bias setting resistor
(Placed between VDD and ISET pins)
1.8
JlF
2
ISET Bypass Capacitor
(ISET pin to GND)
0.1
JlF
VDD Bypass Capacitor 1
(External to GND)
0.1
JlF
VDD Bypass Capacitor 2
(External to GND)
22
XTL 1 Load Capacitor
Depends on crystal characteristics;
40
XTL2 Load Capacitor
from pin to GND
20
3-211
JlF
pF
SSI73K322L
CCITI V.23, V.22, V.21
Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C. VDD = recommended range unless otherwise noted.)
PARAMETER
CONDITIONS
100, Supply Current
ISET Resistor
= 11.0592 MHz
= 11.0592 MHz
ClK = 19.200 KHz
IDDA. Active
ClK
IDD1. Power-down
ClK
IDD2. Power-down
MIN
NOM
MAX
UNITS
8
12
rnA
4
rnA
3
rnA
= 2 MQ
Digital Inputs
VIH, Input High Voltage
Reset. XTl1. XTl2
3.0
VDD
V
All other inputs
2.0
VDD
V
0
0.8
V
100
50
JlA
JlA
JlA
10
pF
VDD
V
0.4
V
Vll, Input low Voltage
IIH, Input High Current
VI = VIH Max
Ill, Input low Current
VI
Reset Pull-down Current
= Vil Min
Reset = VDD
Input CapaCitance
All Digital Input Pins
-200
1
Digital Outputs
= -0.4 rnA
VOH, Output High Voltage
10H MIN
VOL, Output low Voltage
10 MAX = 1.6 rnA
VOL, ClK Output
10=3.6mA
RXD Tri-State Pull-up Curro
RXD=GND
CMAX, ClK Output
Maximum Capacitive load
2.4
-1
0.6
V
-50
JlA
15
pF
Capacitance
Inputs
CapaCitance, all Digital Input pins
XTAl1, 2 load CapaCitors
Depends on crystal characteristics
ClK
Maximum Capacitive load
3-212
15
10
pF
60
pF
15
pF
SSI73K322L
CClll V.23, V.22, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = Recommended range unless otherwise noted.)
MIN
CONDITIONS
PARAMETERS
NOM
MAX
UNITS
DPSK Modulator
Carrier Suppression
Measured at TXA
45
Output Amplitude
TX scrambled marks
-11
dB
-10
-9
dBmO
FSK Modulator
Output Freq. Error
ClK
= 11.0592 MHz
-0.35
Transmit level
Transmit Dotting Pattern
-11
Harmonic Distortion
in 700-2900 Hz band
+0.35
%
-10
-9
dBmO
TH D in the alternate band
DPSK or FSK
-60
-50
dB
Output Bias Distortion
Transmit Dotting Pattern
InALB@ RXD
±3
Total Output Jitter
Random Input in ALB @ RXD
-10
+10
%
Must be in V.22 mode
-.25
+.25
%
Output Amplitude
Low Band, V.22 mode
-10
-9
-8
dBmO
Output Amplitude
High Band, V.22 mode
-8
-7
-6
dBmO
2.0
3.0
dB
-28
dBmO
%
DTMF Generator
Freq. Accuracy
High-Band to Low-Band, V.22 mode
1.0
long Loop Detect
With Sinusoid
-38
Dynamic Range
Refer to Performance Curves
Twist
Note:
45
Parameters expressed in dBmO refer to the following definition:
odB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
3-213
dB
I
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
PARAMETERS
(Continued)
CONDITIONS
MIN
-38
NOM
MAX
UNITS
Call Progress Detector
Detect Level
-3 dB points in 285 and 675 Hz
Reject Level
Test signal is a 460 Hz sinusoid
-45
dBmO
Delay Time
-70 dBmO to -30 dBmO STEP
40
ms
Hold Time
-30 dBmO to -70 dBmO STEP
40
ms
Hysteresis
dBmO
2
dB
Carrier Detect
Threshold
DPSK or FSK receive data
-48
-43
dBmO
ms
Delay Time
V.21
10
20
V.22
15
32
ms
V.23 Forward Channel
6
12
ms
V.23 Back Channel
25
40
ms
Hold Time
V.21
6
20
ms
V.22
10
24
ms
V.23 Forward Channel
3
8
ms
V.23 Back Channel
10
25
ms
Hysteresis
2
dB
Special Tone Detectors
-48
-43
dBmO
2100 Hz answer tone
10
25
ms
1300 Hz calling tone
10
25
ms
390 Hz
V.23 back channel mark
20
65
ms
Detect Level
See definitions for
TR bit DO mode
Delay Time
3-214
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
CONDITIONS
MIN
MAX
UNITS
10
25
ms
4
15
ms
NOM
Special Tone Detectors (Continued)
980 or 1650 Hz
V.21 marks
Hold Time
2100 Hz answer tone
1300 Hz calling tone
3
10
ms
390 Hz
V.23 back channel mark
10
25
ms
980 or 1650 Hz
V.21 marks
5
15
ms
2
Hysteresis
Detect Freq. Range
Any Special Tone
-3
TXA pin; FSK Single
Tone out for THD = -50 dB
in 0.3 to 3.4 kHz
10
dB
+3
%
Output Smoothing Filter
Output load
kQ
50
pF
Out of Band Energy
Frequency> 12 kHz in all modes
-60
dBmO
Output Impedance
TXA pin, TXA enabled
20
50
Q
TXA pin; 76.8 kHz or
122.88 kHz in V.23 main channel
0.1
0.4
mVrms
+10
Hz
100
ms
+625
ppm
50
ms
Clock Noise
CarrierVCO
Capture Range
Originate or Answer
Capture Time
-10Hz to +10 Hz Carrier
Freq. Change Assum.
-10
40
Recovered Clock
Capture Range
% of frequency
center frequency
(center at 1200 Hz)
Data Delay Time
Analog data in at RXA pin to
receive data valid at RXD pin
3-215
-625
30
•
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
CONDITIONS
MIN
Tone Accuracy
550 or 1800 Hz
-20
Tone Level
550 Hz
-4.0
(Below DPSK Output)
1800 Hz
-7.0
Harmonic Distortion
550 Hz
NOM
MAX
UNITS
+20
Hz
-3.0
-2.0
dB
-6.0
-5.0
dB
-50
dB
Guard Tone Generator
700 to 2900 Hz
Timing (Refer to Timing Diagrams)
.
TAL
CS/Addr. setup before ALE Low
TLA
TLC
25
ns
CS/Addr. hold after ALE Low
20
ns
ALE Low to RD/WR Low
30
ns
TCL
RD/WR Control to ALE High
-5
TRD
Data out from RD Low
0
TLL
ALE width
30
TRDF
Data float after RD High
TRW
ns
140
ns
0
5
ns
RDwidth
200
25000
ns
TWW
WR width
140
25000
ns
TDW
Data setup before WR High
40
10
ns
ns
TWD
Data hold after WR High
TCKD
Data out after EXCLK Low
TCKW
WR after EXCLK Low
150
ns
TDCK
Data setup before EXCLK Low
150
ns
TAC
Address setup before control·
50
ns
TCA
Address hold after control·
50
ns
TWH
Data Hold after EXCLK
20
Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.
3-216
ns
200
ns
SSI73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
ALE
~
~
~
TlC
1m
TRW
-'l-
TCl
J
-,'-
TlC
TLA
I
ADO-AD7
CS
J
-+-
WR
--K
--=1-
TAL
"
ADDRESS
TRD
.I!J
>I-----K
TRDF
~
READ DATA
-~-
>I-----K
-i-
ADDRESS
J
TWW
~D
>I-----K
t
TOW
WRITE
DATA~
-~-
READ TIMING DIAGRAM (SERIAL VERSION)
EXClK
AO-A2
DATA
--+
WRITE TIMING DIAGRAM (SERIAL VERSION)
EXClK
HTWW
-----r--------------------------------------~~i
AO-A2 - - - + - - - - - - - - - - - - - - - - - - - - - - - - - t + I \
DATA
3-217
I
SSI73K322L
CClll V.23, V.22, V.21
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
(Top View)
ClK
GND
XTL1
RXA
XTl2
VREF
RXA
VREF
RESET
ADO
RESET
AD1
ISET
AD2
RXClK
ISET
AD3
RXD
TXD
RXClK
AD4
RXD
ADS
cs
TXD
AD6
EXClK
EXClK
AD7
TXClK
ALE
TXA
WR
AD
400-Mil
22-Pln DIP
4
3
2
1282726
25
24
8
PLCC PINOUTS
ARE THE SAME AS
THE 28·PIN DIP
10
TXA
23
22
21
20
11
19
VDD
12 13
600-Mil
28-Pin DIP
14 15
16 17 18
28-Pin
PLCC
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
ORDER NO.
PART DESCRIPTION
PKG.MARK
SSI 73K322L with Parallel Bus Interface
28-Pin 5V Supply
Plastic Dual-In-Line
73K322L-IP
73K322L-IP
Plastic Leaded Chip Carrier
73K322L-IH
73K322L-IH
73K322SL-IP
73K322SL -I P
SSI 73K322L with Serial Interface
22-Pin 5V Supply
Plastic Dual-In-Line
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
0194 - rev.
3-218
Protected by the following Patents (4,691,172) (4,777,453)
©1989 Silicon Systems, Inc.
SSI73K324L
CCITI V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
January 1994
FEATURES
DESCRIPTION
The SSI 73K324L is a highly integrated single-chip
modem IC which provides the functions needed to
design a Quad-mode CCITT and Bell 212A compatible
modem capable of operation over dial-up lines. The
SSI73K324L adds V.23 capability to the CCITT
modes of Silicon Systems' 73K224 one-chip modem,
allowing a one-chip implementation in designs intended for European markets which require this added
Modulation mode. The SSI 73K324L offers excellent
performance and a high level of functional integration
in a single IC. The device supports V.22bis, V.22, Bell
212A, V.21, and V.23 operating modes, allowing both
synchronous and asynchronous operation as defined
by the appropriate standard.
The SSI 73K324L is designed to appear to the
Systems Engineer as a microprocessor peripheral,
and will easily interface with popular one-chip
microcontrollers (80C51 typical) for control of modem
functions through its 8-bit multiplexed address/data
bus. A serial control bus is available for applications not
requiring a parallel interface. An optional package with
only the serial control bus is also available. Data
communications occurs through a separate serial port.
(Continued)
One chip Multi-mode CCITT V.22bis, V.22, V.21,
V.23 and Bell 212A compatible modem data pump
FSK (75, 300, 1200 bit/s), DPSK (600, 1200 bitls),
or OAM (2400 bitls) encoding
Pin and software compatible with other
SSI K-Series family one-Chip modems
Interfaces directly with standard microprocessors
(8048, 80C51 typical)
Serial and parallel microprocessor bus for control
Selectable asynch/synch with internal bufferl
debuffer and scrambler/descrambler functions
All synchronous (internal, external, slave) and
Asynchronous Operating modes
Adaptive equalization for optimum performance
over all lines
Programmable transmit attenuation (16 dB, 1 dB
steps), and selectable receive boost (+18 dB)
Call progress, carrier, answer tone, unscrambled
mark, S1, SCT (900 Hz) calling tone (1300 Hz) and
signal quality monitors
DTMF, answer, calling, SeT and guard tone
generators
Test modes available: ALB, Dl, RDl; Mark, Space
and Alternating bit pattern generators
CMOS technology for low power consumption
4-wire full duplex operation in all modes
BLOCK DIAGRAM
8· BIT
~p
BUS
VF
GAIN BOOST
0194 - rev.
3-219
CAUTION: Use handling procedures necessary
for a static sensitive component.
•
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DESCRIPTION (Continued)
The 881 73K324L offers full hardware and software
compatibility with other products in Silicon Systems'
K-Series family of single-chip modems, allowing system upgrades with a single component change. The
SS I 73K324L is ideal for use in free-standing or integral
system modem products where full-duplex 2400 bitls
operation with Alternate mode capability is required. Its
high functionality, low power consumption, and efficient packaging simplify design requirements and
increase system reliability. A complete modem
requires only the addition of the phone line interface, a
control microprocessor, and RS-232 level converters
for a typical system.
The 881 73K324L is designed to provide a complete
V.22bis, V.22, Bell 212A, V.21, and V.23 compatible
modem on a chip. Many functions were included to
simplify implementation in typical modem designs. In
addition to the basic 2400 bitls QAM, 1200/600 bitls
DPSK and 1200/300/75 bitls FSK modulator/demodulator sections, the device also includes synch/asynch
buffering, DTMF, answer, soft carrier, guard, and calling tone generator capabilities. Handshake pattern
detectors simplify control of connect sequences, and
precise tone detectors allow accurate detection of call
progress, answer, calling, and soft carrierturn off tones.
All Operating modes defined by the incorporated standards are included, and Test modes are provided. Most
functions are selectable as options, and logical defaults are provided. The device can be directly interfaced to a microprocessor via its 8-bit multiplexed
address/data bus for control and status monitoring.
Data communications takes place through a separate
serial port. Data may also be sent and received through
the control registers. This simplifies designs requiring
speed buffering, error control and compression.
FUNCTIONAL DESCRIPTION
QAM MODULATOR/DEMODULATOR
The SSI 73K324L encodes incoming data into quadbits represented by 16 possible signal points with
specific phase and amplitude levels. The baseband
signal is then filtered to reduce intersymbol interference on the band limited telephone network. The
modulator transmits this encoded data using either a
1200 Hz (Originate mode) or 2400 Hz (Answer mode)
carrier. The demodulator, although more complex,
essentially reverses this procedure while also recovering the data clock from the incoming signal. Adaptive
equalization corrects for varying line conditions by
automatically changing filter parameters to compensate for line characteristics.
DPSK MODULATOR/DEMODULATOR
The SSI 73K324L modulates a serial bit stream into
di-bit pairs that are represented by four possible phase
shifts as prescribed by the Bell 212NV.22 standards.
The baseband signal is then filtered to reduce intersymbol interference on the band limited 2-wire PSTN
line. Transmission occurs on either a 1200 Hz (Originate mode) or 2400 Hz carrier (Answer mode).
Demodulation is the reverse of the modulation process, with the incoming analog signal eventually decoded into di-bits and converted back to a serial bit
stream. The demodulator also recovers the clock
which was encoded into the analog signal during
modulation. Demodulation occurs using either a
1200 Hz carrier (Answer mode or ALB Originate mode)
or a 2400 Hz carrier (Originate mode or ALB Answer
mode). The SSI73K324L use a phase locked loop
coherent demodulation technique that offers excellent
performance. Adaptive equalization is also used in
DPSK modes for optimium operation with varying
lines.
FSK MODULATOR/DEMODULATOR
The FSK modulator/demodulator produces a frequency modulated analog output signal using two
discrete frequencies to represent the binary data. V.21
frequencies of 980 and 1180 Hz (originate mark and
space),or1650 and 1850 Hz (answer mark and space)
are used in V.21 mode. V. 23 mode uses 1300 and
2100 Hz forthe main channel or 390 and 450 Hz forthe
back channel. Demodulation involves detecting the
received frequencies and decoding them into the
appropriate binary value. The rate converter and
scrambler/descrambler are automatically bypassed in
the FSK modes.
PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and to provide compromise delay
equalization as well as rejection of out-of-band signals.
The transmit signal filtering corresponds to a --J75%
raised cosine frequency response characteristic.
3-220
SSI73K324L
CClll V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
ASYNCHRONOUS MODE
PARALLEL CONTROL INTERFACE
The Asynchronous mode is used for communication
with asynchronous terminals which may transfer data
at 600, 1200, or 2400 bitls + 1%, -2.5% even though the
modem's output is limited to the nominal bit rate ±.01 %
in OPSK and OAM modes. When transmitting in this
mode the serial data on the TxO input is passed
through a rate converter which inserts or deletes stop
bits in the serial bit stream in order to output a signal
that is the nominal bit rate ±.01%. This signal is then
routed to a data scrambler and into the analog modulator where di-bit or quad-bit encoding results in the
output signal. Both the rate converter and scrambler
can be bypassed for handshaking and synchronous
operation as selected. Received data is processed in
a similar fashion except that the rate converter now
acts to reinsert any deleted stop bits and output data to
the terminal at no greater than the bit rate plus 1%. An
incoming break signal (low through two characters) will
be recognized and passed through without incorrectly
inserting a stop bit.
Eight 8-bit registers are provided for control, option
select, and status monitoring. These registers are
addressed with the ADO, A01, and A02 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as seven consecutive memory locations. Six contol registers are read/write. The detect
and 10 registers are read only and cannot be modified
except by modem response to monitored parameters.
The SYNC/ASYNC converter has an extended
Overspeed mode which allows selection of an output
speed range of either + 1% or +2.3%. In the extended
Overspeed mode, some stop bits are output at 7/8 the
normal width.
Both the SYNC/ASYNC rate converter and the data
descrambler are automatically bypassed in the FSK
modes.
SYNCHRONOUS MODE
Synchronous operation is possible only in the OAM or
OPSK modes. Operation is similar to that of the Asynchronous mode except that data must be synchronized
to a clock and no variation in data transfer rate is
allowable. Serial input data appearing at TXO must be
valid on the rising edge of TXCLK.
TXCLK is an internally derived 1200 or 2400 Hz signal
in Internal mode and is connected internally to the
RXCLK pin in Slave mode. Receive data at the RXO pin
is clocked out on the falling edge of RXCLK. The
asynch/synch converter is bypassed when Synchronous mode is selected and data is transmitted out at
essentially the same rate as it is input.
3-221
SERIAL CONTROL INTERFACE
The Serial Command mode allows access to the
SSI 73K324L control and status registers via a serial
control port. In this mode the AO, A 1, and A2 lines
provide register addresses for data passed through the
DATA pin under control of the RO and WR lines. A read
operation is initiated when the RO line is taken low. The
next eight cycles of EXCLK will then transfer out eight
bits of the selected addresss location LSB first. A write
takes place by shifting in eight bits of data LSB first for
eight consectuive cycles of EXCLK. WR is then pulsed
low and data transfer into the selected register occurs
on the rising edge of WR.
TONE GENERATOR
The OTMF generator controls the sending of the sixteen standard OTMF tone pairs. The tone pair sent is
determined by selecting TRANSMIT OTMF (bit 04)
and the 4 OTMF bits (00-03) of the TONE register.
Transmission of OTMF tones from TXA is gated by the
TRANSMIT ENABLE bit of CRO (bit 01) as with all
other analog signals.
FULL DUPLEX OPERATION
Four-wire full duplex operation is allowed in all modes.
This feature allows transmission and reception in the
same band for four wire applications only.
3
SSI73K324L
CCITI V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
PIN DESCRIPTION
POWER
TYPE
DESCRIPTION
GND
I
System Ground.
VDD
I
Power supply input, 5V -5% +10%. Bypass with 0.22).lF and 22).lF capacitors
to GND.
VREF
a
An internally generated reference voltage. Bypass with 0.22).lF capacitor to
GND.
ISET
I
Chip current reference. Sets bias current for op-amps. The chip current is set
by connecting this pin to VDD through a 2 MQ resistor. Iset should be bypassed
to GND wnh a 0.22 ).IF capac nor.
NAME
PARALLEL MICROPROCESSOR INTERFACE
ALE
ADOAD7
I
Address latch enable. The falling edge of ALE latches the address on ADOAD2 and the chip select on CS.
I/O /
Address/data bus.These bidirectional tri-state multi-plexed lines carry information to and from the internal registers.
CS
Tristate
I
ClK
a
Output clock. This pin is selectable under processor control to be either the
crystal frequency (for use as a processor clock) or 16 x the data rate for use
as a baud rate clock in QAM/DPSK modes only. The pin defaults to the crystal
frequency on reset.
INT
0
Interrupt. This open drain weak pullup, output signal is used to inform the
processor that a detect flag has occurred. The processor must then read the
detect register to determine which detect triggered the interrupt. INT will stay
active until the processor reads the detect register or does a full reset.
RD
I
Read. A low requests a read of the SSI 73K324l internal registers. Data
cannot be output unless both RD and the latched CS are active or low.
RESET
I
Reset. An active high signal on this pin will put the chip into an inactive state.
All control register bits (CRO, CR1, CR2, CR3, Tone) will be reset. The output
of the ClK pin will be set to the crystal frequency. An internal pull down resistor
permits power on reset using a capacitor to VDD.
Chip select. A low on this pin allows a read cycle or a write cycle to occur. ADOAD7 will not be driven and no registers will be written if CS (latched) is not
active. CS is latched on the falling edge of ALE.
<
WR
I
Write. A low on this informs the SSI73K324L that data is available on ADO-AD7
for writing into an internal register. Data is latched on the rising edge of WR.
No data is written unless both WR and the latched CS are low.
Note: The Serial Control mode is provided in the parallel versions by tying ALE high and CS low. In this
configuration AD7 becomes DATA and ADO, AD1 and AD2 become AO, A1 and A2, respectively.
3-222
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
RS-232 INTERFACE
NAME
TYPE
EXCLK
I
External Clock. This signal is used in synchronous transmission when the
external timing option has been selected. In the External Timing mode the
rising edge of EXCLK is used to strobe synchronous transmit data available
on the TXD pin. Also used for serial control interface.
RXCLK
OfTristate
Receive Clock Tri-statable. The falling edge of this clock output is coincident
with the transitions in the serial received DPSKJOAM data output. The rising
edge of RXCLK can be used to latch the valid output data. RXCLK will be valid
as long as a carrier is present. In V.23 orV.21 mode a clock which is 16 x 1200/
75 or 16 x 300 Hz data rate is output, respectively.
0
Received Data Output. Serial receive data is available on this pin. The data is
always valid on the rising edge of RXCLK when in Synchronous mode. RXD
will output constant marks if no carrier is detected.
OfTristate
Transmit Clock Tri-statable. This signal is used in synchronous DPSKJOAM
transmission to latch serial input data on the TXD pin. Data must be provided
so that valid data is available on the rising edge of the TXCLK. The transmit
clock is derived from different sources depending upon the Synchronization
mode selection. In Internal Mode the clock is generated internally (2400 Hz for
QAM, 1200 Hz for DPSK or 600 Hz for half-speed DPSK). In External Mode
TXCLK is phase locked to the EXCLK pin. In Slave Mode TXCLK is phase
locked to the RXCLK pin. TXCLK is always active. In V.23 or V.21 mode the
output is a 16 x 1200/75 or 16 x 300 Hz clock, respectively.
I
Transmit Data Input. Serial data for transmission is input on this pin. In
Synchronous modes, the data must be valid on the rising edge of the TXCLK
clock. In Asynchronous modes (2400/1200/600 biVs, or 75/300 baud) no
clocking is necessary. DPSK/OAM data must be +1%, -2.5% or +2.3%, -2.5
% in Extended Overspeed mode.
RXA
I
Received modulated analog signal input from the phone line.
TXA
0
Transmit analog output to the phone line.
XTL1
XTL2
I
I/O
These pins are forthe internal crystal oscillator requiring a 11.0592 MHz
Parallel mode crystal. Two capacitors from these pins to ground are also
required for proper crystal operation. Consult crystal manufacturer for proper
values. XTL2 can also be driven from an external clock.
RXD
TXCLK
TXD
DESCRIPTION
ANALOG INTERFACE
3-223
•
SSI73K324L
CClll V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
PIN DESCRIPTION
(continued)
SERIAL MICROPROCESSOR INTERFACE
DESCRIPTION
NAME
TYPE
AO-A2
I
Register Address Selection. These lines carry register addresses and should
be valid during any read or write operation.
DATA
I/O
Serial Control Data. Data for a read/write operation is clocked in or out on the
falling edge of the EXCLK pin. The direction of data flow is controlled by the
RD pin. RD low outputs data. RD high inputs data.
RD
I
Read. A low on this input informs the SSI 73K324L that data or status
information is being read by the processor. The falling edge of the RD signal
will initiate a read from the addressed register. The RD signal must continue
for eight falling edges of EXCLK in order to read all eight bits of the referenced
register. Read data is provided LSB first. Data will not be output unless the RD
signal is active.
WR
I
Write. A low on this input informs the SSI73K324L that data or status information
has been shifted in through the DATA pin and is available for writing to an internal
register. The normal procedure for a write is to shift in data LSB first on the DATA
pin for eight consecutive falling edges of EXCLK and then to pulse WR low. Data
is written on the rising edge of WR.
Note: In the serial, 22-pin version, the pins ADO-AD7, ALE and CS are removed and replaced with the pins;
AO, A1, A2, DATA, and EXCLK. Also, the RD and WR controls are used differently.
3-224
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
REGISTER DESCRIPTIONS
the SSI 73K324L internal state. DR is a detect register
which provides an indication of monitored modem
status conditions. TR, the tone control register, controis the DTMF generator, answer, guard tones, SCT,
calling tone, and RXD output gate used in the modem
initial connect sequence. CR2 is the primary DSP
control interface and CR3 controls transmit attenuation
and receive gain adjustments. All registers are read/
write except for DR and ID which are read only.
Register control and status bits are identified below:
Eight 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the AO, A1 and
A2 address lines in Serial mode, or the ADO, AD1 and
AD2 lines in Parallel mode. The address lines are
latched by ALE. Register CRO controls the method by
which data is transferred over the phone line. CR1
controls the interface between the microprocessor and
REGISTER BIT SUMMARY
CONTROL
REGISTER
0
CRO
000
MODULATION
OPTION
MODULATION
TYPE
1
MODULATION
TYPE
0
TRANSMIT
MODE
2
TRANSMIT
MODE
1
TRANSMIT
MODE
0
TRANSMIT
ENABLE
ANSWER!
ORIGINATE
CONTROL
REGISTER
1
CRl
001
TRANSMIT
PATIERN
1
TRANSMIT
PATIERN
0
ENABLE
DETECT
INTERRUPT
BYPASS
SCRAMBLER!
ADD PH. EQ.
(V.23)
CLK
CONTROL
RESET
TEST
MODE
1
TEST
MODE
0
DR
010
RECEIVE
LEVEL
PATIERN
SlDET
RECEIVE
DATA
UNSCR.
MARK
DETECT
CARRIER
DETECT
SPECIAL
TONE
DETECT
CALL
PROGRESS
DETECT
SIGNAL
QUALITY
TONE
CONTROL
REGISTER
TR
011
RXD
OUTPUT
CONTROL
TRANSMIT
GUARD TONEI
SCT/CALLING
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF3
DTMF2I
4WIRE FOX
DTMF1/
OVERSPEED
DTMFO/GUARD/
ANSWER!
CALLING/SCT
CONTROL
REGISTER
2
CR2
100
SPECIAL
REGISTER
ACCESS
CALL
INITIALIZE
TRANSMIT
Sl
16 WAY
RESET
DSP
TRAIN
INHIBIT
EQUALIZER
ENABLE
CR3
101
RECEIVE
GAIN
BOOST
TRANSMIT
ATIEN.
3
TRANSMIT
ATIEN.
2
TRANSMIT
ATTEN.
1
TRANSMIT
ATIEN.
0
SPECIAL
REGISTER
SR
101
TXBAUD
CLOCK
RX UNSCR.
DATA
10
REGISTER
ID
110
ID
ID
DETECT
REGISTER
CONTROL
REGISTER
3
NOTE:
TXDALT
TRISTATE
TX/RXCLK
When a register containing reserved control
bits is written into, the reserved bits must be
programmed as O's.
3-225
I
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
REGISTER ADDRESS TABLE
~~~:~~~~ --------------~
OAM: 0---2400 Bms
DPSK: 0=1200 Bms
1=600 Bms
FSK: 0=V.23
oo10=EXT SYNCH
ooll=SLAVESYNCH
01OO=ASYCH 8 BfTSICHAR
0101=ASYCH 9 BfTSICHAR
0110=ASYCH 10 BITSICHAR
0111=ASYCH 11 BITSICHAR
1Xoo=FSK
1=V.21
GUARD:
O· 1800 HZ
1·550HZ
ANSWER: 0·2225 HZ
1-2100 HZ
CALLING: 0 - 1300 HZ
SCT:
1 - 900 HZ
O=ACCESS CRa
1=ACCESS
SPECIAL
REGISTER
O=DSP IN
O=NORMAL
DEMOD MODE
DOTTING
1=DSP IN CALL
1=S 1
PROGRESS
MODE
OOXX=73K212L, 322L, 321L
01XX=73K221 L, lO2L
1OXX= 73K222L
11OO=73K224L
1110=73K324L
1101=73K312L
3-226
O=RX=TX
1=RX=16WAY
O=DSP
INACTIVE
l=DSP
ACTIVE
O=ADAPTEO
ACTIVE
1=ADAPT EO
FROZEN
O=ADAPTEO
ININIT
1=ADAPT EO
OK TO ADAPT
SSI73K324L
CCITI V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CONTROL REGISTER 0
CRO
000
07
06
MODUL.
OPTION
MODUL.
TYPE 1
BIT NO.
DO
NAME
04
05
D3
D2
D1
DO
MODUL. TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
MODE 1
MODE 0
ENABLE ORIGINATE
TYPE 0
MODE2
CONDITION
Answer/
Originate
DESCRIPTION
0
Selects Answer mode (transmit in high band, receive in
low band) or in V.23 HDX mode, receive at 1200 bitls
and transmit at 75 bitls.
1
Selects Originate mode (transmit in low band,receive
in high band) or in V.23 HDX mode, receive at 75 bitls
and transmit at 1200 bit/so
Note: This bit works with Tone Register bits DO and D6
to program special tones detected in the Detect Register. See Detect and Tone Registers.
D1
Transmit
0
Enable
1
Disables transmit output at TXA.
Enables transmit output at TXA.
Note: Transmit Enable must be set to 1 to allow
activation of Answer Tone, DTMF, or Carrier.
D5 D4 D3 D2
D5, D4,
D3,D2
Transmit
Mode
0
0
0
0
Selects Power Down mode. All functions disabled
except digital interface.
0
0
0
1
Internal Synchronous mode. In this mode TXCLK is an
internally derived 600, 1200 or 2400 Hz signal. Serial
input data appearing at TXD must be valid on the rising
edge of TXCLK. Receive data is clocked out of RXD on
the falling edge of RXCLK.
0
0
1
0
External Synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 600, 1200 or 2400 Hz clock
must be supplied.externally.
0
0
1
1
Slave Synchronous mode. Same operation as other
Synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.
0
1
0
0
Selects Asynchronous mode - 8 bits/character (1 start
bit, 6 data bits, 1 stop bit).
0
1
0
1
Selects Asynchronous mode - 9 bits/character (1 start
bit, 7 data bits, 1 stop bit).
0
1
1
0
Selects Asynchronous mode -10 bits/character (1 start
bit, 8 data bits, 1 stop bit}.
0
1
1
1
Selects Asynchronous mode -11 bits/character (1 start
bit, 8 data bits, Parity and/or 1 or 2 stop bits).
1
X
0
0
Selects FSK operation.
3-227
•
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CONTROL REGISTER 0 (Continued)
BIT NO.
NAME
CONDITION
DESCRIPTION
06 05
06,05
07
Modulation
1
0
Type
0
0
OPSK
0
1
FSK
Modulation
Option
QAM
0
QAM selects 2400 bit/s. OPSK selects 1200 bit/so
FSK selects V.23 mode.
1
DPSK selects 600 bit/so
FSK selects V.21 mode.
CONTROL REGISTER 1
CR1
001
BIT NO.
07
06
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
NAME
04
05
03
ENABLE
BYPASS
ClK
DETECT SCRAMBI CONTROL
ADD PH.EQ
INT.
CONDITION
02
01
DO
RESET
TEST
MODE
1
TEST
MODE
0
DESCRIPTION
01 DO
01,00
02
03
Test Mode
Reset
ClK Control
(Clock Control)
0
0
Selects Normal Operating mode.
0
1
Analog loopback mode. loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same carrier frequency as the transmitter. To
squelch the TXA pin, transmit enable bit must be low.
Tone Register bit 02 must be zero.
1
0
Selects remote digitalloopback. Received data is looped
back to transmit data internally, and RXD is forced to a
mark. Data on TXD is ignored.
1
1
Selects local digitalloopback. Internally loops TXO back
to RXD and continues to transmit data carrrier at TXA pin.
0
Selects normal operation.
1
Resets modem to power down state. All control register
bits (CRO, CR1, CR2, CR3 and Tone) are reset to zero
except CR3 bit 02. The output of the clock pin will be set
to the crystal frequency.
0
Selects 11.0592 MHz crystal echo output at ClK pin.
1
Selects 16 X the data rate output at ClK pin in QAM and
DPSK only.
3-228
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CONTROL REGISTER 1 (Continued)
CR1
001
BIT NO.
D4
D5
D7,D6
D7
D6
D5
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
D4
D3
ENABLE
BYPASS
ClK
DETECT SCRAMS/ CONTROL
INT.
ADD PH.EO.
D2
D1
DO
RESET
TEST
MODE
1
TEST
MODE
0
NAME
CONDITION
Bypass
Scrambler/
Add Ph. Eq.
0
Selects normal operation. DPSK and QAM data is
passed through scrambler.
1
Selects Scrambler Bypass. DPSK and QAM data is
routed around scrambler in the transmit path. In the V.23
mode, additional phase equalization is added to the main
channel filters when D4 is set to 1.
Enable Detect
Interrupt
0
Disables interrupt at INT pin. All interrupts are normally
disabled in Power Down mode.
1
Enables INT output. An interrupt will be generated with a
change in status of DR bits D1-D4 and D6. The answer
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TX DTM F is activated. All interrupts will be disabled
if the device is in Power Down mode.
Transmit
Pattern
DESCRIPTION
D7
D6
0
0
Selects normal data transmission as controlled by the
state of the TXD pin.
0
1
Selects an alternating mark/space transmit pattern for
modem testing and handshaking. Also used for S1 pattern generation. See CR2 bit D4.
1
0
Selects a constant mark transmit pattern.
1
1
Selects a constant space transmit pattern.
3-229
•
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DETECT REGISTER
D7
DR
010
BIT NO.
DO
D1
D2
D5
D4
D3
D2
RECEIVE
DATA
UNSCR.
MARK
DETECT
CARRIER
DETECT
SPECIAL
TONE
DETECT
D6
RECEIVE
S1
LEVEL
PATTERN
INDICATOR DETECT
D1
DO
SIGNAL
CALL
PROG.
QUALITY
DETECT INDICATOR
NAME
CONDITION
Signal Quality
Indicator
0
Indicates normal received signal.
DESCRIPTION
1
Indicates low received signal quality (above average error
rate). Interacts with Special Register SQ bits D2, D1.
Call Progress
Detect
0
No call progress tone detected.
1
Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in the
normal 350 to 620 Hz call progress band.
Special Tone
Detect
0
Condition not detected
1
Condition detected
CRO DO TR DO CR2 D5
D3
D4
D5
D6
D7
Carrier Detect
Unscr. Mark
Detect
1
0
1
2225 Hz ±10 Hz answer tone detected in V.22bis, V.22,
V.21 modes.
1
1
1
2100 Hz ±21 Hz answer tone detected in V.22bis, V.22,
V.21 modes.
0
0
1
1300 Hz calling tone detected in V.22 bis, V.22, V.21, V.23
modes.
0
X
0
900 Hz SCT tone detected in V.23 mode.
I
X
0
2100 Hz or 2225 Hz answer tone detected in QAM, DPSK,
or V.21 Mode.
0
No carrier detected in the receive channel.
1
Indicated carrier has been detected in the received
channel. Should be time qualified by software.
0
No unscrambled mark being received.
1
Indicates detection of unscrambled marks in the received
data. Should be time qualified by software.
Continuously outputs the received data stream.
Receive
Data
This data is the same as that output on the RXD pin, but it
is not disabled when RXD is tri-stated.
S1 Pattern
Detect
0
No S1 pattern being received.
1
S1 pattern detected. Should be time qualified by software.
S1 is an unscrambled double dibit (11001100 ... ) sent in
DPSK 1200 bitls mode. Generated pattern must be properly aligned to transmitter baud clock to be detected.
Receive Level
Indicator
0
Received signal level below threshold,
(== -25 dBmO);can use receive gain boost (+18 dB.)
1
Received signal above threshold.
3-230
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
TONE REGISTER
07
TR
011
06
05
RXO
TRANSMIT TRANSMIT
OUTPUT
GUARO/
ANSWER
CONTR. CALLING/SC1
TONE
TONE
BIT NO.
00,04,
05,06
NAME
OTMF 0/
Guard Tone/
Answer Tone/
Calling/SCT
Tone/
Transmit
Select
01
OTMF 1/
Overspeed
02
CONDITION
04
03
02
TRANSMIT
OTMF
OTMF3
OTMF 2/
WIRE
FOX
01
00
OTMF 1/
DTMF 0/
OVERG.T.lANSW.I
SPEEO CALLING/SCT
TONEISEL
DESCRIPTION
06 05 04 00
00 interacts with bits 06, 05, 04, and CRO as shown.
X
X
1
X
Transmit OTMF tones (overides all other functions).
1
0
0
0
Select 1800 Hz guard tone if in V.22bis or V.22 and
Answer mode in CRO.
1
0
0
1
Select 550 Hz guard tone if in V.22bis or V.22 and
Answer mode in CRO.
Note: Bit 00 also selects the answer tone detected in Originate mode, see
Oetect Register Special Tone Oetect (bit 02) for details.
1
0
0
0
1300 Hz calling tone will be transmittted if V.21, V.22,
V.22bis or V.23 Originate mode is selected in CRO.
X
1
0
0
Transmit 2225 Hz Answer Tone. Must be in OPSK
Answer mode.
X
1
0
1
Transmit 2100 Hz Answer Tone. Must be in OPSK
Answer mode.
1
0
0
1
900 Hz SCT (soft carrier turnoff) tone transmitted in
V.23 75 biVs Receive mode. (CRO bit 00 = 1).
04 01
01 interacts with 04 as shown.
0
0
Asynchronous OAMIDPSK +1% -2.5%. (Normal).
0
1
Asynchronous OAMIDPSK, 2400, 1200 or 600 bit/s
+2.3% -2.5%. (Extended overspeed).
04 D2
OTMF 2/
4WIRE
FOX
0
0
Selects 2-wire full-duplex or half-duplex.
0
1
02 selects 4 wire full duplex in the Modulation mode
selected. The receive path corresponds to the ANS/
ORIG bit CRO 00 in terms of high or low band selection.
The transmitter is in the same band as the receiver, but
does not have magnitude filtering or equalization on its
signal as in the receive path.
Note: OTMFO - OTMF2 should be set to an appropriate state after OTMF dialing to avoid unintended operation.
3-231
•
SSI73K324l
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
TONE REGISTER
07
TR
011
(Continued)
06
05
04
TRANSMIT TRANSMIT
RXO
GUARDI
ANSWER
OUTPUT
TONE
CONTR. CALLING/SCT
TONE
BIT NO.
NAME
CONDITION
03,02,
01,00
OTMF 3,
2,1,0
04
=1
RXO Output
Control
01
DTMF 21
DTMF3
WIRE
FOX
00
OTMF 11
DTMF 0/
OVERGUARDI
SPEED CALLING/SCT
TONE SEL
DESCRIPTION
Programs 1 of 16 DTMF tone pairs that will be
transmitted when TX DTM F and TX enable bit (CRO, bit
01) is set. Tone encoding is shown below:
KEYBOARD
EQUIVALENT
07
02
03
TRANSMIT
DTMF
DTMFCODE
03 02 01 DO
TONES
LOW HIGH
1
0
0
0
1
697
1209
2
0
0
1
0
697
1336
3
0
0
1
1
697
1477
4
0
1
0
0
770
1209
5
0
1
0
1
770
1336
6
0
1
1
0
770
1477
7
0
1
1
1
852
1209
8
1
0
0
0
852
1336
9
1
0
0
1
852
1477
0
1
0
1
0
941
1336
"
1
0
1
1
941
1209
#
1
1
0
0
941
1477
A
1
1
0
1
697
1633
B
1
1
1
0
770
1633
C
1
1
1
1
852
1633
0
0
0
0
0
941
1633
0
Enables RXD pin. Receive data will be output on
RXO.
1
Oisables RXO pin.The RXO pin reverts to a high
impedance with internal weak pull-up resistor.
3-232
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CONTROL REGISTER 2
CR2
100
BIT NO.
00
01
02
03
04
05
06
07
07
06
05
04
0
SPEC
REG
ACCESS
CALL
INIT
TRANSMIT
S1
03
16 WAY
02
RESET
OSP
01
00
TRAIN
INHIBIT
EQUALIZER
ENABLE
NAME
CONDITION
Equalizer
Enable
0
The adaptive equalizer is in its initialized state.
1
The adaptive equalizer is enabled. This bit is used in
handshakes to control when the equalizer should
calculate its coefficients.
Train
Inhibit
0
The adaptive equalizer is active.
1
The adaptive equalizer coefficients are frozen.
RESET OSP
0
The OSP is inactive and all variables are initialized.
1
The OSP is running based on the mode set by other
control bits
0
The receiver and transmitter are using the same decision plane (based on the Modulator Control Mode).
1
The receiver, independent of the transmitter, is forced
into a 16 point decision plane. Used for QAM handshaking.
0
The transmitterwhen placed in alternating Mark/Space
mode transmits 0101 .... scrambled or not dependent
on the bypass scrambler bit and Modulation mode.
1
When this bit is 1 and only when the transmitter is
placed in alternating Mark/Space mode by CR1 bits
07, 06, an unscrambled repetitive double dibit pattern
of 00 and 11 at 1200 bitls (S 1) is sent.
0
The OSP is setup to do demodulation and pattern
detection based on the Various mode bits. Both answer
tones are detected in Oemod Mode concurrently; TR
00 is ignored.
1
The OSP decodes call progress, calling tones, unscrambled mark, and 2100 Hz and 2225 Hz answer
tones.
16 Way
Transmit
S1
Callinit
DESCRIPTION
Special
Register
Access
0
Normal CR3 access.
1
Setting this bit and addressing CR3 allows access to
the SPECIAL REGISTER. See the SPECIAL REGISTER for details.
N/A
0
Must be 0 for normal operation.
3-233
I
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CONTROL REGISTER 3
07
CR3
101
06
TXOALT TRISTATE
TXlRXCLK
BIT NO.
NAME
03
05
04
0
RECEIVE
ENABLE
BOOST
CONDITION
02
01
00
TRANSMIT TRANSMIT TRANSMIT TRANSMIT
ATTEN.
ATTEN.
ATTEN.
ATTEN.
3
2
1
0
DESCRIPTION
03 02 01 00
o-
03,02,
01,00
Transmit
Attenuator
04
Receive
Gain Boost
(18 dB)
0
18 dB receive front end boost is not used.
1
Boost is in the path. This boost does not change
reference levels. It is used to extend dynamic range by
compensating for internally generated noise when
receiving weak signals. The receive level detect signal
and knowledge of the hybrid and transmit attenuator
setting will determine when boost should be enabled.
05
Not Used
0
Not used. Only write zeros this location.
06
Tristate
TXCLKlRXCLK
0
TXCLK, RXCLK outputs driven
1
TXCLK, RXCLK outputs in Tristate mode
TXOALT
Spec. Reg. bit 03=1
07
0
1
0
1
0
1
1
Sets the attenuation level of the transmitted signal
in 1dB steps. The default (03-00=0100) is for a transmit level of -10 dBmO. The total range is 16 dB.
Alternate TX data source. See Special Register.
ID REGISTER
SPECIAL REGISTER
06
SR
101
03
02
01
TXO
SOURCE
SIGNAL
QUALITY
LEVEL
SELECT1
SIGNAL
QUALITY
LEVEL
SELECTO
05
06
TXBAUO CLK
TXBAUO clock is the transmit baud-synchronous clock that can be used to
synchronize the input of arbitrary quad/di-bit patterns. The rising edge of
TXBAUO signals the latching of a baud-worth of data internally. Synchronous
data to be entered via the TXOALT bit, CR3 bit 07, should have data
transitions that start 1/2 bit period delayed from the TXBAUO clock edges.
05
RXUNOSCR
OATA
This bit outputs the data received before going to the descrambler. This is
useful for sending special unscrambled patterns that can be used for signaling.
3-234
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
SPECIAL REGISTER
BIT NO.
(Continued)
NAME
DESCRIPTION
n-XO SOURCE
03
02,01
SIGNAL
QUALITY
LEVEL
SELECT
This bit selects the transmit data source; either the TXO pin if ZERO or the
TXOALT ifthis bit is a ONE. The TRANSM IT PATTERN bits 07 and 06 in CR1
override either of these sources.
The signal quality indicator is a logical zero when the signal received is
acceptable for low error rate reception. It is determined by the value of the
Mean Squared Error (MSE) calculated in the decisioning process when
compared to a given threshold. This threshold can be set to four levels of error
rate. The SOl bit will be low for good or average connections. As the error rate
crosses the threshold setting, the SOl bit will toggle at a 1 .66 ms rate. Toggling
will continue until the error rate indicates that the data pump has lost
convergence and a retrain is required. At that point the SOl bit will be a ONE
constantly. The SOl bit and threshold selection are valid for QAM and OPSK
only.
D2
D1
TYPICAL
THRESHOLD VALUE
0
0
10-5
BER (default)
0
1
10-6
BER
1
0
4
10-
BER
1
1
10-3
BER
UNITS
NOTE: This register is "mapped" and is accessed by setting CR2 bit 06 to a ONE and addressing CR3. This
register provides functions to the 73K324L user that are not necessary in normal communications.
Bits 07-04 are read only, while 03-00 are read/write. To return to normal CR3 access, CR2 bit 06
must be returned to a ZERO.
10
110
07
06
05
04
10
3
10
2
10
1
10
0
BIT NO.
NAME
07,06,05,
Device
0
Identification
0
1
Signature
1
0
1
1
1
1
1
1
CONDITION
07 06 05 04
04
0
X
I
03
I
02
I
01
DO
USER DEFINABLE PERSONALITY
DESCRIPTION
Indicates Device:
X
SSI 73K212L or 73K322L or 73K321 L
X
X
SSI 73K221 L or 73K302L
X
X
SSI73K222L
0
0
SSI73K224L
1
0
SSI73K324L
0
1
SSI73K312L
3-235
I
I
I
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
VDD Supply Voltage
7V
Storage Temperature
-65 to 150°C
Soldering Temperature (10 sec.)
260°C
Applied Voltage
-0.3 to VDD+0.3V
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITIONS
VDD Supply voltage
MIN
NOM
MAX
UNITS
4.5
5
5.5
V
External Components (Refer to Application section for placement.)
0.22
VREF Bypass capacitor
(VREF to GND)
Bias setting resistor
(Placed between VDD
and ISET pins)
ISET Bypass capacitor
(ISET pin to GND)
0.22
IlF
VDD Bypass capacitor 1
(VDDto GND)
0.22
IlF
VDD Bypass capacitor 2
(VDDto GND)
22
IlF
1.8
IlF
2
2.2
MQ
XTL 1 Load Capacitance
Depends on crystal requirements
18
39
pF
XTL2 Load Capacitance
Depends on crystal requirements
18
27
pF
-0.01
+0.01
%
-40
85
°C
Clock Variation
(11.0592 MHz) Crystal or
external clock
TA, Operating Free-Air
Temperature
3-236
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to 85°C, VOO =recommended range unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
100, Supply Current
ClK = 11.0592 MHz
NOM
MAX
UNITS
18
25
mA
5
mA
0.8
V
ISET Resistor = 2 MQ
1001, Active
Operating with crystal oscillator.
1002, Idle
< 5 pF capacitive load on ClK pin.
Digital Inputs
Vll, Input low Voltage
VIH, Input High Voltage
All Inputs except Reset
XTl1,XTl2
2.0
VOO
V
Reset, XTl 1, XTl2
3.0
VOO
V
100
-70
JlA
JlA
JlA
VOO
V
0.4
V
-50
JlA
25
pF
10
pF
IIH, Input High Current
VI = VOO
Ill, Input low Current
VI = OV
Reset Pull-down Current
Reset = VOO
-2
VOH, Output High Voltage
10 = 10H Min
lOUT = -0.4 rnA
2.4
Val, Output low Voltage
10 = lOUT = 1.6 mA
RXO Tri-State Pull-up Curro
RXO= GNO
-200
-30
Digital Outputs
-2
Capacitance
Maximum Capacitive load
ClK
Input Capacitance
All Digital Inputs
3-237
I
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
-10.0
-9
dBmO
QAM/DPSK Modulator
Carrier Suppression
Measured at TXA
Output Amplitude
TX scrambled marks
ATT=0100 (default)
-11.5
Output Freq. Error
ClK = 11.0592 MHz
-.31
Transmit level
ATT = 0100 (Default)
Transmit Dotting Pattern
-11.5
TXA Output Distortion
All products through BPF
Output Bias Distortion
at RXD
Dotting Pattern measured at RXD
Receive level -20 dBm, SNR 20 dB
-10
+10
%
Output Jitter at RXD
Integrated for 5 seconds
-15
+15
%
Sum of Bias Distortion and
Output Jitter at RXD
Integrated for 5 seconds
-15
+15
%
-9
dBmO
-40
dB
dB
35
FSK Modulator/Demodulator
-10.0
+0.20
%
-9
dBmO
-45
dB
2100 Hz Answer Tone Generator
Output Amplitude
Output Distortion
DTMF Generator
ATT = 0100 (Default level)
Not in V.21 or V.23 Mode
Distortion products in receive band
low Band--,-ATT = 0100
-0.03
+0.25
%
-10
-8
dBmO
Output Amplitude
Hiah Band ATT = 0100
-8
Twist
High-Band to low-Band
1.0
Receiver Dynamic Range
Refer to Performance Curves
-43
Call Progress Detector
In Callinit mode
Detect level
-10
Not in V.21 or V.23 mode
Freq. Accuracy
Output AmpJitude
-11.5
460 Hz input sianal
-34
Reject level
2.0
-6
dBmO
3.0
dB
-3.0
dBmO
0
dBmO
-40
dBmO
Delav Time
-70 dBmO to -30_dBmO_STEP
25
ms
Hold Time
-30 dBmO to -70 dBmO STEP
25
ms
Hysteresis
@ 460 Hz input signal
2
NOTE: Parameters expressed in dBmO refer to the following definition:
o dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
3-238
dB
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (continued)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
-43
dBmO
Carrier Detect Receive Gain Boost "On" for Lower Input Level Measurements
Threshold
QAM/DPSK or FSK receive data
Hysteresis
All Modes
Delay Time
FSK
DPSK
QAM
Hold Time
FSK
-48
2
dB
70 dBmO to -6 dBmO
25
37
70 dBmO to -40 dBmO
25
37
ms
-70 dBmO to -6 dBmO
7
17
ms
ms
ms
-70 dBmO to -40 dBmO
7
17
-70 dBmO to -6 dBmO
25
37
ms
-70 dBmO to -40 dBmO
25
37
ms
-6 dBmO to -70 dBmO
25
37
ms
-40 dBmO to -70 dBmO
15
30
ms
-6 dBmO to -70 dBmO
20
29
ms
-40 dBmO to -70 dBmO
14
21
ms
-6 dBmO to -70 dBmO
25
32
ms
-40 dBmO to -70 dBmO
8
28
ms
-48
-43
dBmO
Call INIT mode
2225 ± 10 Hz
2100±21 Hz
6
50
ms
1300 Hz calling tone
Tone Accuracy +3, -5%
10
45
ms
900 Hz SCT
Tone Accuracy ±9 Hz
10
45
ms
DPSK
QAM
Special Tone Detectors
Detect Level
See definitions for DO of Tone Register
Delay and Hold Time
2225 or 2100 Hz
answer tone
Receive V.23 main channel
Hysteresis
Pattern Detectors
2
dB
DPSK Mode
S1 Pattern
Delay Time
For signals from -6 to -40 dBmO,
10
55
ms
Hold Time
Demod Mode
10
45
ms
For signals from -6 to -40
10
45
ms
10
45
ms
-22
-28
dBmO
7
ms
Unscrambled Mark
Delay Time
Hold Time
Demod or call Init Mode
Receive Level Indicator
Detect On
Valid after Carrier Detect
DPSK Mode
1
3-239
4
I
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
MIN
CONDITIONS
NOM
MAX
UNITS
200
300
n
Output Smoothing Filter
Output Impedance
Output Load
TXA pin
TXA pin; FSK Single
kQ
10
Tone out for THO = -50 dB
in 0.3 to 3.4 kHz range
50
pF
Maximum Transmitted
4 kHz, Guard Tones off
-35
dBmO
Energy
10kHz, Guard Tones off
-55
dBmO
12 kHz, Guard Tones off
-65
dBmO
Anti Alias Low Pass Filter
Maximum allowed
Out-of-Band Signal Energy
(Defines Hybrid TransHybrid loss requirements)
Scrambled data at 2400 bitls in
opposite band
-14
dBm
Sinusoids out of band
-9
dBm
Transmit Attenuator
Range of Transmit Level
Default ATT
1111-0000
=
0100 (-10 dBmO)
Step Accuracy
Clock Noise
-21
-6
dBmO
-0.15
+0.15
dB
mVrms
1.5
TXA pin; 153.6 kHz
Carrier Offset
Capture Range
Originate or Answer
-7
±5
+7
Hz
+.02
%
Recovered Clock
Capture Range
% of data rate originate or answer
-.02
Guard Tone Generator
Tone Accuracy
550 Hz
+1.2
%
1800 Hz
-0.8
%
Tone Level
550 Hz
-4.5
(Below QAM/DPSK Output)
1800 Hz
-7.5
Harmonic Distortion
(700 to 2900 Hz)
550 or 1800 Hz
3-240
-3.0
-1.5
-6.1
-4.5
dB
dB
-50
dB
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (Continued)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
Timing (Refer to Timing Diagrams)
Parallel Mode:
TAL
CS/Addr. setup before ALE Low
30
ns
TLA
CS/Addr. hold after ALE Low
6
ns
TLC
ALE Low to RD/WR Low
40
ns
10
TCL
RD/WR Control to ALE High
TRD
Data out from RD Low
ns
90
ns
40
ns
TLL
ALE width
TRDF
Data float after RD High
TRW
RDwidth
70
ns
TWW
WR width
70
ns
TOW
Data setup before WR High
70
ns
TWO
Data hold after WR High
20
ns
25
ns
Serial Mode:
TRCK
Clock high after RD
TAR
Address setup before RD low
TRA
Address hold after RD low
TRD
RD to data valid
250
T1
0
ns
350
ns
110
TRDF
Data float after RD high
TCKDR
Read data out after falling edge
of EXCLK
ns
ns
50
ns
300
ns
TWW
WR width
350
ns
TAW
Address setup before WR
50
ns
TWA
Address hold after rising edge of WR
50
ns
TCKDW
Write data hold after falling edge
of EXCLK
200
ns
TCKW
WR high after falling edge of EXCLK
330
TDCK
Data setup before falling edge
of EXCLK
T1, T2
Minimum period
ns
50
ns
500
ns
Note: T1 and T2 are the low/high periods, respectively, of EXCLK in Serial mode.
3-241
T1& T2
I
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
ALE
~
~
~
....
TRW
TlC
1m
TCl
J
-:'-
-'I;-
TlC
TLA
L
cs
TWW
J
4-_
WR
ADO-AD7
1
--K
-=1-
TAL
,
ADDRESS
.I
TRD
>t----K
~D
TRDF
~
~
READ DATA
TDW
>t----K
-i-
-J-
ADDRESS
>t----K
I-
WRITE DATA)t--
-J-
READ TIMING DIAGRAM (SERIAL VERSION)
JL
EXCLK
AO-A2
DATA
WRITE TIMING DIAGRAM (SERIAL VERSION)
EXCLK
AO-/>2
---+--------------------+£A
DATA
3-242
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
551 73K324L BER vs 5/N
SSI 73K324L BER vs SIN
PRELIMINARY
\[\
I
PRELIMINARY
t
I HIGH BAND RECEIVE
1\\
-3Odlm
OAM OPERATION
2400BITtS
'\ ,¥ f--'l~.J I LOW BAND RECEIVE
~
\~
10-3
I
r\
C2
\1\
.L
t
-30dBm
OAM OPERATION
2400 BITtS
'\ ~
""':2J
\
\.
r
~\\.
V
\\
u
- -C~)
1\\
~
10-4
~
\.
~~
L
1.\
\\
r~J- \ \ L'-v\~
V
....;Q
\
IT
1\ \
10-6
18 19 20 21
22
10 11
12 13
SIGNAL TO NOISE (dB)
14 15 16 17
18 19
20 21
SSI 73K324L BER vs SIN
PRELIMINARY
PRELIMINARY
,
..j3002
/
I~
~-r'
I
I HIGH BAND RECEIVE
~
-30dBm
DPSK OPERATION
1200BITIS
t
3002
~
Ire;!
10-3
.....
\\\
1
@
-
.......... 1
~
~
~P-
\II
Ie
~~
,
I111
\\},
II
III
-
~~
t-I
~~
---,
~
[~
\\
\\~
~
10-6
8
t
~
1\
7
-3OdBm
DPSK OPERATION
1200BITtS
~
\\
6
I LOW BAND RECEIVE
C2
~
5
22
SIGNAL TO NOISE (dB)
5S1 73K324L BER vs SIN
IT
4
\'
,
rLf,-,
\ \\ ~·;~i ~
14 15 16 17
"
./
\~\
12 13
~
/
10-5
\ 1\
10 11
I
'i
9
10 11
W
r- -
12 13
14 15
FLAT
\
12 13
14 15
16
4
SIGNAL TO NOISE (dB)
5
6
7
8
9
10 11
SIGNAL TO NOISE (dB)
3-243
16
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
SSI 73K324L BER vs RECEIVE
SSI 73K324L BER vs SIN
PREUMINARY
PREUMINARY
lOAM OPERATION
2400BITIS
1
t
MAIN~~EL
IIr
I
;
1200bItIs
BACK CHANoIEL 7S bItIs
OPERATION FSK
t
'
\
\
1\
\
\
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
o
-0
RECEIVE LEVEL (dBm)
1
2
3
4
5
6
7
SNR LEVELS
3-244
8
9
10 11
12
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
PACKAGE PIN DESIGNATIONS
(Top View)
o
0
N
....J
0
::::J
~
0
<:
4
3
0
~
...J
~
28
2
2
0
Z
LA-
~
UJ
a:
32
31
N/C
30
29
AD1
28
RESET
UJ
27
3
~
....J
()
>
a:
>
x
a:
0
~
x
a:
U.
<:
Z
()
N
F!
x
0
<:
N/C
26
AD1
25
RESET
AD2
27
ISET
AD2
24
ISET
AD3
26
RXClK
AD3
23
RXClK
AD4
25
RXD
AD4
22
RXD
ADS
24
TXD
ADS
21
TXD
AD6
23
CS
AD6
20
CS
AD7
22
EXClK
AD7
19
EXClK
N/C
21
N/C
12
13
14
UJ
I~
I@
...J
<:
15
0
0
16
17
18
<:
I~
0
X
.....
>
15
~
...J
UJ
....J
<:
x
.....
!!l
0
Z
52 51
:so
0
0
0
al
:s
0
~
en
0
50 49 48 47 46 45 44 43 42 41
40
0
0
0
~ ~
>
19
20
~
....J
()
x
.....
0
~
li li
18
:s
li
~ ~
I~ I@
17
32-Pin PLCC
28-Pin PLCC
Ii:i
16
I
~ Z Z
ClK
GND
XTL1
RXA
39
NtC
38
INTB
37
NtC
ADO
RESET
RXA
36
TXA
AD1
ISET
VREF
NtC
35
NtC
AD2
RXCLK
NtC
34
NtC
AD3
RXD
GND
NtC
XTAL2
NtC
15 16 17 18 19 20 21
8«
0
Z
0
0
Z «
22 23 24 25 26
g 2!i 0 C3
« « « « « Z Sil
~
on
0
.....
0
z
0
Z
33
VDD
32
NtC
30
RDB
29
WRB
28
NtC
27
ALE
XTL2
VREF
AD4
TXD
AD5
CS
XTL1
RESET
ISET
RXCLK
A1
RXD
AD6
EXCLK
TXD
AD7
TXCLK
EXCLK
ALE
fN'j'"
TXCLK
WR
TXA
INT
RD
VDD
TXA
28-Pin DIP
52-Lead QFP
3-245
400-Mil
22-Pin DIP
SSI73K324L
CCITT V.22bis, V.22, V.21 , V.23, Bell 212A
Single-Chip Modem
CAUTION: Use handling procedures necessary
for a static sensitive component.
1.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ADO
~
Q
NIC
NIC
46
NIC
NIC
45
RXCLK
NIC
44
NIC
AD1
43
RXD
NIC
42
NIC
AD2
41
NIC
40
TXD
NIC
2
AD3
ISET
AD4
10
39
NIC
ADS
11
38
cs
AD6
12
37
EXCLK
NIC
13
36
NIC
AD7
14
35
NIC
NIC
15
34
NIC
NIC
NIC
64-Lead TQFP
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
SSI73K324L with Serial Bus Interface
22-Pin Plastic Dual-In-Line
73K324LS-IP
73K324LS-IP
28-Pin Plastic Dual-In-Line
73K324L-IP
73K324L-IP
28-Pin Plastic Leaded Chip Carrier
73K324L-281H
73K324L-281H
32-Pin Plastic Leaded Chip Carrier
73K324L-321H
73K324L-321H
44-Pin Plastic Leaded Chip Carrier
73K324L-IH
73K324L-IH
52-Pin Quad Flat Pack Package
73K324L-IG
73K324L-IG
64-Lead Thin Quad Flat Pack Package
73K324L-IGT
73K324L-IGT
SSI 73K324L with Parallel! Bus Interface
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Mytord Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
Protected by the following patents: (4,777,453)
(4,789,995) (4,870,370) (4,847,868) (4,866,739)
©1990 Silicon Systems, Inc.
3-246
0194 - rev.
Section
4
MODEM PROTOCOL
& BUS INTERFACE
•
4
4-0
551730246
Microcontroller
fttiMiUAMi·'"·Siit.,,,
December 1993
DESCRIPTION
FEATURES
8052 Compatible Instruction set
22 MHz Operation
HOLC Support logic (Packetlzer, 16 and 32
CRC, zero 10)
24 pins for user programmable 1/0 ports
The Silicon Systems 730246 high performance
microcontroller is based on the industry standard 8-bit
8052 implemented in Silicon Systems' advanced
submicron CMOS process. The processor has the
same attributes of the 8052 including Instruction cycle
time, UART, timers, interrupts, 256 bytes of on-chip
RAM and programmable I/O. The architecture has
been optimized for low power portable modem or
communication applications by integrating unique
features with the core CPU.
8 pins programmable chip select logic for
memory mapped peripheral eliminating glue
logic
3 external Interrupt sources (programmable
polarity)
16 dedicated latched address pins
Multiplexed data/address bus
Instruction cycle time Identical to 8052
Buffered oscillator (or OSC/2) output pin
The main feature is a user friendly HDLC packetizer,
accessed through the special function registers. It has
a serial 1/0, hardware support for 16- and 32-bit CRC,
zero insert/delete control, a dedicated interrupt and a
clear channel mode for by-passing the packetizer.
Other features include additional user programmable
1/0 with programmable bank select and chip select
logic, designed to eliminate board level glue logic.
Bank select circuitry to support up to 128K of
external program memory
For devices that require non-multiplexed address and
data buses, eight latched outputs forthe low byte ofthe
address are available.
100-Lead TQFP package available for PCMCIA
applications
Also available In 100-Lead QFP package
(continued)
BLOCK DIAGRAM
...--_ _ _ _- . PSEN
. - - - - - - . . . ALE
1293
4-1
•
551730246
Microcontroller
DESCRIPTION
DEVELOPER'S NOTE:
(continued)
The 730246 is also available in a 100-pin PGA
package for system developers. The PGA package
is more convenient and reliable for development
emulation systems than the other package styles.
Emulation systems for the 73D246 are available
through Signum Systems, 171 E. Thousand Oaks
Blvd., # 202, Thousand Oaks, CA 91360
(805) 371-4608.
The 730246 has two extra interrupt sources, an
external interrupt and a HOLC interrupt. The HOLC
interrupt has two registers associated with it: the H OLC
Interrupt Register which is used to determine the
source ofthe interrupt, and the HOLC Interrupt Enable
Register that enables the source of the interrupt.
The interrupt pins INTO and INT1 can be either
negative edge, positive edge or level triggered. INT2
pin is always edge triggered.
8052 REFERENCE
A buffered clock output has been added to support
peripheral functions such as UARTs, modems and
other clocked devices.
This Document will describe the features unique to the
730246. Please referto an 8052 Programmer's Guide,
Architectural Overview and Hardware Description for
details on the instruction set, timers, UART, interrupt
control, and memory structure.
Additional internal special function registers are used
for firmware control over the HOLC Packetizer, and
the programmable I/O ports.
For low power applications the 730246 supports two
power conservation modes: Idle and Power-down. In
the Power-down state the total current consumption is
less than 1 J.lA at room temperature.
This device is offered in small form factor 100-lead
TOFP packages for PCMCIA applications and
100- lead OFP packages.
4-2
551730246
Microcontroller
REGISTER DESCRIPTION
INTERRUPTS
The core chip provides 8 sources of interrupt; 3 external interrupts, 3 timer interrupts, a serial port interrupt, and
an HOLC interrupt. An external interrupt and an HOLC interrupt are unique to the 730246. They do not exist in
a normal 8052 product. Previously unused bits in the IE and IP registers are now serving functions for these
additional interrupt sources. The interrupt vector addresses are as follows:
SOURCE
VECTOR ADDRESS
INTO (lEO)
003H
TFO
OOBH
INT1 (IE1)
013H
TF1
01BH
RI + TI
023H
TF2 + EXF2
02BH
INT2 - ADDED INTERRUPT
033H
HOLC-AOOEOINTERRUPT
03BH
The external interrupt sources, INT(2:0), come from dedicated input pins. The apparent polarity of these pins
is individually controlled by bits in a special interrupt direction register,lDIR (addressA9). The interrupt pins INT1
and INTO can be either edge or level generated interrupts as indicated by bits 1 and 3 in the TCON register
(address 88). Pin INT2 is always an edge generated interrupt. A flag is set when a falling transition (rising if 10lR
bit 2 is set) on this pin is detected. This flag is automatically cleared when the interrupt is processed.
INTERRUPT ENABLE REGISTER (IE) SFR ADDRESS A8
Bit Addressable
Reset State OOh
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BITO
EA
EX2
ET2
ES
ET1
EX1
ETO
EXO
Note: BIT 6 differs from the 8052. This is a reserved bit in the 8052 and is used as a mask bit for external interrupt
2 in the core implementation. When BIT 6 is set to a 0, external interrupt 2 is disabled.
The mask bit for the HOLC interrupt source is BIT 0 of the HOLC control register.
INTERRUPT PRIORITY REGISTER (IP) SFR ADDRESS B8
Bit Addressable
Reset State OOh
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BITO
PHOLC
PX2
PT2
PS
PT1
PX1
PTO
PXO
Note: BIT 6 and BIT 7 differ from the 8052. These are reserved bits in the 8052 and are used to determine the
priority of external interrupt 2 and the HOLC in the core implementation. When BIT 6 is set to a 1, the interrupt
is set to the higher priority level.
4-3
•
SSI730246
Microcontroller
REGISTER DESCRIPTION (continued)
EXTERNAL INTERRUPT DIRECTION REGISTER (IDlR) SFR ADDRESS 92
Byte Addressable
Reset State OOh
BIT7
0
BIT6
BIT5
0
0
BIT4
BIT3
0
0
BIT2
INT02
BIT 1
BITO
INT01
INTOO
These bits determine the polarity of the corresponding external signals INT(2:0) which will result in an interrupt.
BITS(2:0) Interrupt Polarity Control
If the bit is set to a 0, a falling edge will trigger the interrupt. If the bit is set to a 1, a rising edge will trigger the
interrupt. Also, if the bit is set to a 1, level generated interrupts will occur when the corresponding pin is high and
the internal pin Signal to the timer controls will be inverted.
Bits 6 and 7 will always be read as O's.
POWER SAVING MODES
Low Power Modes
The SSI 730246 supports two power conservation modes, which are controlled by the PCON.1 and PCON.O
control bits of the PCON register.
If PCON.O is set, the SSI 730246 will go into a power saving mode where the oscillator is running, clocks are
supplied to the UART, timers, HOLC, and interrupt blocks, but no clocks are supplied to the CPU. Instruction
processing and activity on the address and data ports is halted. Normal operation is resumed when an unmasked
interrupt is requested or when a reset occurs.
If PCON.1 is set, the SSI73 0246 goes into its lowest power mode where the oscillator is halted. The total current
consumption in this state should be less than 1 J-La. The SSI 730246 will start its oscillator and begin to return
to normal operation when either a reset occurs, when a falling (rising if corresponding direction bit is set) edge
of an unmasked external interrupt from pins INT(2:0) is detected. Edges used in wakeup modes are not filtered
in the SSI 730246 so the user must be cautious of noise or small glitches inadvertently waking up the Chip. From
the time the edge that results in the wake up occurs, to the point at which an instruction is executed, depends
on the oscillato r start -up time. Three good oscillator pu Ises must be detected before the main internal clocks are
generated.
USER PROGRAMMABLE I/O
Port Control USR1, USR2, USR3, USR4
The core chip provides 32 user 1/0 pins. Each pin is programmed separately as either an input or as an output
by a bit in a direction register. If the bit in the direction register is set to a 1, the 1/0 control will treat the
corresponding pin as an input. If it is a 0, the pin will be treated as an output whose value is determined by the
port data register. The USR1 and USR2 port registers are accessed through the internal SFR bus. The USR3
and USR4 ports are accessed through the external memory bus by a MOVX instruction. The USR4 port provides
the user with an automatic chip select function if selected by the user. If the user does not require some (or any)
of the chip select pin options, he may program the USR4 port pins to operate in the same way as USR3 port pins.
4-4
SSI730246
Microcontroller
The USR DATA register contents determine pin values if chosen as an output. When reading from the DATA
register's SFR address, the pin logic values are returned as data except when the port address is the destination
address for a read-modify-write instruction. In this case, the latched register values are returned
as data. When reading data from a DATA registerthat is mapped in the external memory space, the pin values
are always returned as data.
USER 1 PORT
USRl DATA SFR Address 90
Bit Addressable
Reset State OOh
BIT7
BIT 6
BITS
BIT4
BIT3
BIT2
BIT 1
BITO
USR17
USR16
USR15
USR14
USR13
USR12
USR1 1
USR10
Bits in this register will be asserted on the USR1 (7:0) pins if the corresponding direction register bit is a O.
Reading this SFR's address will return data reflecting the values of pins USR 1(7:0) except when address 90h
is the destination address for a read-modify-write instruction. In this case, the latched register values are
returned as data.
USR1 port signals are also used as timer controls. In applications where the external signals are required for
timer count modes, the corresponding port pin should be configured as an input.
USR1
USR1
USR1
USR1
BITO
BIT1
BIT2
BIT3
TIMER 0 TO PIN
TIMER 1 T1 PIN
TIMER 2 T2EX PIN
TIMER 2 T2 PIN
USRl Port Direction (DIR1) SFR Address 91
Byte Addressable
Reset State FFh
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BITl
BITO
DIR17
DIR16
DIR15
DIR14
DIR13
DIR12
DIR1 1
DIR10
This register is used to designate the USR1 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR1 pin is programmed as an output that will be driven by the corresponding USR1 DATA
register bit. If the register bit is a 1 , the corresponding pin will be treated as an input.
After a reset, the USR1 pins will present a high impedance output state and the input values will not be driven
from the pin, but will be driven to a 0 internally. The pins will assume normal I/O operation once the processor
has written the port direction register. This feature will ensure the core chip is in a low current state at reset
(you don't want to drive out against external inputs, and you don't want floating inputs).
4-5
•
SSI730246
Microcontroller
REGISTER DESCRIPTION (continued)
USER2 PORT
USR2 Port Data SFR Address 08
Bit Addressable
Reset State OOh
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BIT 0
USR27
USR26
USR25
USR24
USR23
USR22
USR21
USR20
Bits in this register will be asserted on the USR2(7:0) pins if the corresponding direction register bit is a O.
Reading this SFR's address will return data reflecting the values of pins USR2(7:0) except when address D8h
is the destination address for a read-modify-write instruction. In this case, the latched register values are
returned as data.
USR2 Port Direction (DIR2) SFR Address D9
Byte Addressable
Reset State FFh
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BIT 0
DIR27
DIR26
DIR25
DIR24
DIR23
DIR22
DIR21
DIR20
This register is used to designate the USR2 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR2 pin is programmed as an output that will be driven by the corresponding USR2 I/O DATA
register bit. If the register bit is a 1 , the corresponding pin will treated as an input.
After a reset, the USR2 pins will present a high impedance output state and the input values will not be driven
from the pin, but will be driven to a 0 internally. The pins will assume normal I/O operation once the processor
has written the port direction register. This feature will ensure the core chip is in a low current state at reset (you
don't want to drive out against external inputs, and you don't want floating inputs).
USR3 Port Data External address 0000
Byte Addressable
Reset State OOh
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BITO
USR37
USR36
USR35
USR34
USR33
USR32
USR31
USR30
Bits in this register will be asserted on the USR3(7:0) pins if the corresponding direction register bit is a O.
Reading this SFR's address will return data reflecting the values of pins USR3(7:0).
If the bank select feature is chosen, USR3 PIN7 acts as address bit 17 and USR3 data bit 7 is ignored.
USR3 1/0 Port Direction (DIR3) External Address 0001
Byte Addressable
Reset State FFh
BIT7
BIT6
BITS
BIT4
BIT3
BIT 2
BIT1
BITO
DIR37
DIR36
DIR35
DIR34
DIR33
DIR32
DIR31
DIR30
4-6
551730246
Microcontroller
This register is used to designate the USR3 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR3 pin is programmed as an output that will be driven by the corresponding USR3 DATA
register bit. If the register bit is a 1, the corresponding pin will be treated as an input.
After a reset, the USR3 pins will present a high impedance output state and the input values will not be driven
from the pin, but will be driven to a 0 internally. The pins will assume normal 1/0 operation once the processor
has written the port direction register. This feature will ensure the core chip is in a low current state at reset (you
don't want to drive out against external inputs, and you don't want floating inputs).
If the bank select feature is chosen, USR3 PIN7 is forced to be an output.
Bank Select (BNKSEL) External Address 0002
Byte Addressable
Reset State OOh
BIT7
BIT6
BIT5
BIT4
BIT3
BIT 2
BIT 1
BITO
B7
B6
B5
B4
B3
BSEN
BS1
BSO
This resister is used to accommodate systems where more than 64 Kbytes (up to 128 Kbytes) of program
memory are required. USR3 PIN 7 acts as an address pin, A16, if BSEN is set to a 1 and if the processor is
fetching an instruction and not data memory. If BSEN is set to a 1, A15 is also modified during instruction fetches
as shown. If BSEN is a 0, no alterations to address bit A15 are made, and USR3 PIN 7 is a function of USER3
bit 7 and DIR3 bit 7.
Bits (7-3) are general purpose read/write register bits.
A15 is the value of the 16th address bit as it appears at pin A15.
A15' is the address from port 2 internal logic, the value that will appear as the most significant addressbitif
no bank select feature is chosen.
A16 is the value of the 17th and MSB of the instruction address seen at the USR3 7 port pin, if the bank select
feature is selected. If the bank select feature is not selected, USR3 7 acts as a normal USR3 1/0 port pin.
BSEN
BS1
BSO
A15'
A15
A16
ADDRESS
0
0
1
1
1
1
*
*
*
*
OK - 32K
32K - 64K
0
0
1
1
0
1
0
1
USR37
USR37
0
0
0
0
1
1
1
1
0
1
0
1
OK - 32K
32K - 64K
0
1
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
1
1
* = Don't care.
4-7
1
OK - 32K
64K - 96K
0
1
0
1
OK - 32K
96K -128K
0
0
0
1
OK - 32K
64K - 96K
I
551730246
Microcontroller
REGISTER DESCRIPTION (continued)
Example: Bank 2 is selected
BSEN = 1, BS1 = 0, BSO
BANK 3
=1
BANK 2
Bank 2 is selected
If A 15' is a 1, fetches will come from Bank 2
Bank 2 will overlay Bank 1
BANK 1
BANKO
That is all fetches that would normally occur
from Bank 1 will come from Bank 2
0- 32K
FIGURE 8: Bank Select
USER4 PORT
USR4 Port Data External Address 0003
Byte Addressable
Reset State OOh
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BITO
USR47
USR46
USR45
USR44
USR43
USR42
USR41
USR40
Bits in this register will be asserted on the USR4(7:0) pins if the corresponding direction register bit is a 0 and
if the corresponding bit in the chip select enable register, 0005, is set to a O. Reading this register will return data
reflecting the values of pins USR4(7:0).
USR4 I/O Port Direction (DIR4) External Address 0004
Byte Addressable
Reset State FFh
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BITO
DIR47
DIR46
DIR45
DIR44
DIR43
DIR42
DIR4
1 DIR40
This register is used to designate the USR4 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR4 pin is programmed as an output that will be driven by the corresponding USR4 I/O DATA
register bit if the corresponding bit in the chip select enable register, 005, is set to a O. If the register bit is a 1,
the corresponding pin will treated as an input only if the corresponding bit in register 005 is set to a O.
After a reset, the USR4 pins will act as chip select outputs.
4-8
551730246
Microcontroller
USR4 Port Chip Select Enable (CSEN) External Address 0005
Byte Addressable
Reset State FFh
BIT7
BIT6
BITS
BIT4
BIT3
BIT 2
BIT 1
BITO
CSEN7
CSEN6
CSEN5
CSEN4
CSEN3
CSEN2
CSEN 1
CSENO
This register is used to designate the USR4 pins as either user programmable II Os or as chip select (CSOB CS7B) functions on a pin by pin basis. This feature is designed to help reduce external glue logic for peripheral
memory mapped devices. The chip select function is programmed by setting the appropriate bits in the CSEN
register. When a chip select pin is enabled by setting the corresponding CSEN bit to a 1 , all data and direction
information from registers 0003 and 0004 for this bit are ignored and the selected port becomes an output. If
the bit is reset to a 0, the pin will be treated as a normal programmable user 1/0 pin as defined by registers 0003
and 0004.
The chip select pins have a defined memory map. The intent is that the outputs can be wire ORed together for
a flexible selection of peripheral chip selects. All chip selects will be disabled (forced to a logic 1. It is assumed
that all chip selects are active low) after the read or write is completed, and the appropriate chip select will be
enabled as the next new external addresses is asserted. After a reset, the CSB pull-up devices are all enabled,
that is, all chip select outputs are high. Users must account for this if these pins are intended to be general
purpose liDs.
The chip selects partition a 64K memory space as follows:
CHIP SELECT PIN
ADDRESS
RESERVED FOR INTERNAL USE
# BYTES
OOOOH - OOFFH
256
CSO (USR4.0)
01 OOH - 01 FFH
256
CS1
0200H - 03FFH
512
(USR4.1)
CS2 (USR 4.2)
0400H - 07FFH
1K
CS3 (USR 4.3)
0800H - OFFFH
2K
CS4 (USR 4.4)
1OOOH - 1FFFH
4K
CS5 (USR4.5)
2000H - 3FFFH
8K
CS6 (USR 4.6)
4000H - 7FFFH
16K
CS7 (USR 4.7)
8000H - FFFFH
32K
Note: You can't read from external addresses OOOOH-OOFFH. These are reserved for SSI 730246 internally
defined registers
4-9
•
•
SSI730246
Microcontroller
REGISTER DESCRIPTION (continued)
HOLC CONTROL REGISTER 0
HOLC Control Register 0 (HOLCO) SFR Address CO
Bit Addressable Reset State OOXX 0000 b
Bits 5 and 4 are read only bits
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BITO
WRXD
WPTXD
TXD
R
PRXD
R
RXD
CTRL1
RXD
CTRLO
PTX
CTRL1
PTX
CTRLO
This register controls the basic set-up of the DTE and modem pins RXD, TXD, PRXD, and PTXD.
BIT7WRXO
BIT 7 allows the processor to write directly to the SSI 730246 RXD output pin. The value of BIT 7 will appear
at the PTXD pin only if BIT 1 is a 1 and BIT 0 is a O.
BIT6WPTXO
BIT 6 allows the processor to write directly to the SSI 730246 PTXD output pin. The value of BIT 6 will appear
at the PTXD pin only if BIT 1 is a 1 and BIT 0 is a O.
BIT5TXD
BIT 5 is a read only bit that reflects the value at the SSI 730246 TXD input pin.
BIT4PRXD
BIT 4 is a read only bit that reflects the value at the SSI 730246 PRXD input pin.
BIT 3 BIT 2 RXD Control
BIT 3 and BIT2 control the source of the SSI 730246 RXD output pin. This output goes to the DTE's RS232
interface. The source of this signal can be the core's UART TXD output, the PRXD output from a modem
peripheral (clear channel), the DTE's TXD(echo), or the value written into bit 7 of this register.
BIT3
BIT2
0
0
0
1
PRXD BUFFERED (CLEAR CHANNEL)
1
0
TXD BUFFERED (ECHO)
1
1
WRXD (BIT 7)
RXD OUTPUT
UART TXD OUTPUT
4-10
551730246
Microcontroller
BIT 1 BIT 0 PTXO Control
BIT 1 and BITO control the source of the SSI730246 PTXO output pin. This output goes to the modem's TX data
input. The source of this signal can be the core's HOLC TX output, the OTE's TXO output (clear channel), or the
value written into bit 6 of this register.
BIT1
BITO
0
0
HOLC TX Output
0
1
TXO Buffered (Clear Channel)
1
0
WPTXO (BIT 6)
1
1
0
PTXO Output
HOlC CONTROL REGISTER 1
HOlC Control Resister 1 (HDlC1) SFR Address C1
Byte Addressable
Reset State OOh
BIT7
BIT6
BITS
BIT4
BIT3
BIT 2
BIT1
BITO
HOLC
RST
CLK CRTL
CLK
EN
RXCRC
32
RXCRC
16
TXCRC
32
ZERO
10
HOLC
EN
This register controls the basic set-up of the HOLC block. This register will be written during initialization and
not during normal message processing.
BIT 7 HOlC Software Set
When BIT7 is a 1, the HOLC circuit is reset and held in a low power state and no interrupts from the HOLCcircuitry
will be generated. When a 0 is written to this bit, the HOLC circuit will behave according to its control bits. BIT
7 and the power on reset signal are OR'ed together to form a reset Signal for the HOLC block.
BIT 7 is cleared to a 0 upon a power up reset.
BIT 6 ClK CRTl Clock Out Control
Bit 6 controls the frequency of the clock output pin. The clock output is either the oscillator's output signal divided
by two or a buffered ocscillator output signal.
BIT 6
CLOCK OUT
0
OSC
OSC/2
1
BIT 6 is cleared to a 0 upon a reset.
BIT S ClK Clock Out Enable
BIT 5 enables the clock at the clock output pin if it is set to a 1. The clock pin output can be held to a 0, without
halting the oscillator, by writing this bit to zero. This will reduce system power if the clock pin is not used or if a
power reduction mode is required.
BIT 5 is cleared to a 0 upon a reset.
4-11
•
SSI730246
Microcontroller
HDLC CONTROL REGISTER 1 (continued)
BIT 4 BIT 3 RX CRC Control
BIT 4 and BIT 3 determine the type of CRC remainder that will be checked at the end of a received frame. There
is a 16-bit CRC, and a 32-bit CRC that the HDlC block can support. If both BIT 4 and BIT 3 are reset, bits 7 and
6 of the HDlC STATUS register will be held to a O. If both BIT 4 and BIT 3 are 1s, a special CRC search mode
is enabled where both bits 7 and 6 of the HDlC status register are enabled. This mode is used during a
connection to determine which CRC is used by the initiating modem. If the 16-bit CRC remainder is not matched
at the end of the received frame, then BIT 6 of the HDlC STATUS register is set. If the 32-bit CRC remainder
is not matched at the end of the received frame, then BIT 7 of the HDlCSTATUS register is set. Once the correct
CRC type is established during a connection, either BIT 4 or BIT 3 should be set to a 1 enabling the appropriate
INVALID CRC status bit.
BIT4
BIT3
0
0
1
1
0
1
0
1
CRCTYPE
NOCRC Check
Enable CRC16 Status
Enable CRC32 Status
Enable CRC16 Status and CRC32 Status
BIT 2 TXCRC Control
BIT 2 controls the CRC type to be transmitted. If BIT 2 is reset to a 0, a 16-bit CRC will be transmitted with the
SEND CRC command. If BIT 2 is set to a 1, a 32 bit CRC will be transmitted.
BIT 1 Zero Insert/Delete Control
When BIT 1 is set to a 1, a 0 will be transmitted if either the SEND DATA or SENDCRC bits of the HDLCTX
CONTROL are set after five consecutive 1s have been transmitted. Also, when this bit is set, a 0 will be removed
from the received data stream if it immediately follows a pattern of a 0 followed by five consecutive ones. If BIT
1 is reset to a 0, no Os will be inserted during transmission, and no Os will be deleted during reception.
BIT 1 is cleared to a 0 upon a reset.
BIT 0 HOLC Interupt Enable
When BIT 0 is reset to a 0, the HDlC will be prevented from generating an interrupt. The status bits that indicate
the source of the interrupt can still be set allowing the HDlC block to be serviced in a polled mode.
BIT 0 is cleared to a 0 upon reset.
HDLC TX Control Resister (HTXC) SFR Address C2
Byte Addressable
Reset State OOh
BIT 7
BIT6
BITS
BIT4
BIT 3
BIT2
BIT 1
BITO
0
0
0
DIV16
ClK
SEND
ABORT
SEND
CRC
SEND
DATA
SEND
FLAG
This register is used to control the source of data that appears on the PTXD pin. Bits are shifted out on every
rising edge of the PTXCLK pin input. If no control bits are set, or more than 1 TX CONTROLbit is set, the PTXD
pin will go to a binary 1.
4-12
551730246
Microcontroller
BIT 7 • BIT 5 Always 0
BIT 4 16X Clock Select
Under normal synchronous operation, the PTXCLKand PRXCLK are used to receive and transmit data PRXD
and PTXD. The clock rate is equal to the data rate. In asynchronous modes, a clock 16 times the bit rate is
provided at PTXCLK and PRXCLK.
When BIT 4 is set to a 1 for asynchronous operation, the clocks at the PTXCLK and PRXCLK pins are divided
by 16 to provide transmit and receive shift clocks. An internal clock for sampling incoming PRXD data is
synchronized by detecting any falling edge on the PRXD data pin. The rising edge of this internal clock, which
used to sample incoming data, is delayed from the falling data edge by 8 PRXCLK periods and will continue at
this phase and at a PRXCLKl16 frequency until another falling PRXD edge is detected.
If BIT 4 is reset to a 0, the rising edge of PTXCLK is used to sample the data at PRXD, and the falling edge of
PTXCLK is used to shift new data onto PTXD.
BIT 3 is cleared to a 1 upon a reset.
BIT 3 Abort
When BIT 3 is set to a 1, a series of consecutive 1s will immediately be transmitted through the PTXD pin on
every falling edge of PTXCLK. The message will have been aborted after 2 TX ready interrupts are received.
No Os will be inserted during the abort transmission.
BIT 3 is cleared to a 1 upon a reset.
BIT 2 Send CRC
When BIT 2 is set, the bytes in the TX CRC generator will be inverted and serially transmitted to the PTXD output
on the falling edge on PTXCLK as soon as the present data byte transmission is completed. If BIT 1 of the HDLC
control register is a 0, a 0 will be inserted into the CRC data stream after five consecutive 1s are transmitted.
As soon as the last bit of the CRC is sent, a series of Flags will be automatically sent until another TX control
bit is set. No TX Ready interrupts will be generated during the transmission of the CRC bytes. A TX Ready
interrupt will be generated as the first bit of each Flag byte is transmitted indicating that the CRC transmission
has been completed. This should be cleared by a dummy write to the TX DATA register.
BIT 2 will be cleared to a 0 upon a reset.
BIT 1 Send Data
When BIT 1 is set, the data is the TX data register will be serially transmitted through the PTXD pin on every
falling edge of PTXCLK, LSB first. If BIT 1 ofthe HDLC control register is a 0, a 0 will be inserted into the data
stream after five consecutive 1s are transmitted. After all eight data register bits have been sent, the HDLC will
continue to send data by loading the parallel serial transmit register with new transmit register data, unless either
a TX underrun is detected or one of the other TX control bits has been set. This bit will be cleared by the HDLC
circuitry as soon as a TX underrun is detected. A TXRDY interrupt will be generated at as the first data of each
data byte is transmitted. BIT 1 will be cleared to a 0 upon a reset.
BIT 0 Send Flag
When BIT 0 is set, a pattern of 7E will be transmitted to the PTXD output as soon as either the next data byte
or CRC has completed transmission. No Os will be inserted during the flag transmission. When BIT 0 is reset
back to a 0, the HDLC circuitry will complete the flag byte in progress and then transmit according to bits in the
TX CONTROL register. TX Ready interrupts will be generated as each byte of flag transmission is initiated.
BIT 0 will be cleared to a 0 upon a reset.
4-13
•
SSI730246
Microcontroller
REGISTER DESCRIPTION (continued)
HOLCSTATUS REGISTER
HOLC Status Register (HSTAT) SFR Address C3
Byte Addressable
Reset state OOh
Read only register
If any of the HDLC status bits are set, BIT 1 of the HDLC INTERRUPT register (NEW STATUS) will be set
if the corresponding bit in the HDLC INTERRUPT ENABLE register is set.
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BITO
INVAL
CRC32
INVAL
CRC16
TX
UNDRN
RX
OVRN
INVAL
FLAG
ABORT
DET
IDLE
DET
FLAG
DET
BIT 7 Invalid CRC32
BIT 7 will be set if the CRC search mode or the 32-bit CRC is enabled by the HDLC control register and an
incorrect remainder for the 32-bit CRC is detected at the last received byte prior to receiving a flag.
BIT 7 will by cleared upon a reset and is cleared by a read of the HDLCSTAT register.
BIT 6 Invalid CRC16
BIT 6 will be set if the CRC search mode or the 16-bit CRC is enabled by the HDLC CONTROL register and an
incorrect remainder for the 16-bit CRC is detected at the last received byte prior to receiving a flag.
BIT 6 will by cleared upon a reset and is cleared by a read of the HDLC STAT register.
BIT 5 TX Underrun
When BIT 5 is set, a transmit underrun condition has been detected. This is a condition where the HDLC has
finished transmitting a message byte, but no new data has been loaded into the TX DATA register, and no other
transmit control bit has been set. This bit will be set only if the SEND DATA bit, BIT 1 of the TXCONTROL register
is set. The transmit data is double buffered since the TX data register is downloaded into a TX serial register
when the HDLC begins to transmit a new data byte. At the time of loading the TX serial register, a TX READY
interrupt is generated. This interrupt must be serviced by either loading a new data byte (the next data byte to
be transmitted) into the TX data register, or by setting another TX control bit, before the current data byte has
completed transmission (at which pOint anotherTX READY interrupt would be generated). If a TX UNDERRUN
is detected, the HDLC will abort the current transmission by sending continuous 1s and will reset the SEND
DATA control bit in the TX CONTROL register.
BIT 5 will by cleared upon a reset and is cleared by a read of the HDLCSTAT register.
BIT 4 RX Overrun
When BIT 4 is set, a receive overrun condition has been detected. This is a condition where the HDLC has
received a new byte, but the last received data byte has not yet been read from the RX data register. As soon
as a new data byte has been received in an eight bit serial register, it is loaded into the RX data register and a
NEW RX DATA interrupt is generated. If this interrupt is not serviced by reading the RX data register during the
time another new data byte is received, the RX OVERRUN status bit will be set. The new received data will not
overwrite the older unread data.
BIT 4 will by cleared upon a reset and is cleared by a read of the HDLCSTAT register.
4-14
551730246
M icrocontroller
BIT 3 Invalid Flag
When BIT 3 is set, an invalid flag has been detected. This is a condition where a 7E pattern with no inserted Os
is detected, and this pattern did not originate on a byte boundary. Note, two consecutive flags may share a 0,
so that the second (or subsequent) flag may not appear to be on a byte boundary. This condition does not result
in an invalid flag indication. Instead, the bit counter is reset to
o.
BIT 3 will by cleared upon a reset and is cleared by a read of the HOLC STAT register.
BIT 2 Abort Detect
When BIT 2 is set, an abort condition has been detected. This is a condition where seven consecutive 1s, with
no inserted Os, are received after an active state. BIT 2 will be cleared upon a reset and is cleared by a read of
the HOLC STAT register.
BIT 1 Idle Detect
When BIT 1 is set, the first indication of an idle state is detected. An idle state is declared when 15 consecutive
1s, with no inserted Os, are received after an active state.
BIT 1 will be cleared upon a reset and is cleared by a read of the HOLC STAT register.
BIT 0 Flag Detect
When BIT 0 is set, the HOLC has received a 7E pattern with no inserted O's. BIT 0 will by cleared upon a reset
and is cleared by a read of the HOLCSTAT register.
HDLC INTERRUPT ENABLE REGISTER
HDLC Interrupt Enable Register (HIE) SFR Address C4
Byte Addressable
Reset state OOh
If the bit is set, the corresponding interrupt source is enabled.
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BITO
TXROY
IE
RXROY
IE
TXROY
EN
RXROY
EN
INVAL
FLG IE
ABORT
IE
IOLE
IE
FLAG
IE
BIT 7 Transmitter Ready Interrupt Enable
When BIT 7 is set, an HOLC interrupt will be generated if BIT 0 ( TX ROY) of the HOLC INTERRUPT register
is also set. If BIT 7 is reset to a 0, no HOLC interrupt indication will be given as TX ROY is set. This interrupt enable
allows the TX ROY to be a polled bit. Note that BIT 5 of this register is a pre-mask to the TX ROY bit, that is, it
will prevent the TX ROY bit from ever being set.
BIT 7 will be cleared upon a reset.
BIT 6 Receiver Ready Interrupt Enable
When BIT 6 is set, an HOLC interrupt will be generated if BIT 1 ( RXROY) of the HOLC INTERRUPT register
is also set. If BIT 6 is reset to a 0, no HOLC interrupt indication will be given as RX ROY is set. This interrupt
enable allows the RX ROY to be a polled bit. Note that BIT 4 of this register is a pre-mask to the RX ROY bit,
that is, it will prevent the RX ROY bit from ever being set.
BIT 6 will be cleared upon a reset.
4-15
•
SSI730246
Microcontroller
HOLe INTERRUPT ENABLE REGISTER
(continued)
BIT 5 Transmit Ready Enable
BIT 5 is used to enable the TX ROY and TX UNOERRUN interrupt sources. When BIT 5 is set, the transmitter
ready indication will set BIT 0 of the HOLC interrupt register. The TX ROY indication will go active as the first
bit of a message byte is being transmitted, except du ring CRC transmission. Also, if this bit is set, the TX underrun
condition will result in a NEW STATUS interrupt. If IT5 is reset to a 0, BIT 0 of the HOLC INTERRUPT register
will not be set, and no corresponding HOLC interrupt will be generated. Also, a Tx underrun condition, as
indicated by BIT 5 of the HOLC STATUS register, will not result in an HOLC interrupt or in setting the NEW
STATUS interrupt bit.
BIT 5 will be cleared upon a reset.
BIT 4 Receiver Ready Enable
BIT 4 is used to enable the RX ROY and RX OVERRUN interrupt sources. When BIT 4 is set, the receiver ready
indication will set BIT 1 of the HOLC INTERRUPT register. The RX ROY indication will go active when a data
byte (a byte that is not a flag, idle, or an abort pattern) is loaded into the RX OATA register. Also, if this bit is set,
the RX overrun condition will result in a NEW STATUS interrupt. If BIT 4 is reset to a 0, BIT 1 of the HOLC
INTERRUPT register will not be set, and no corresponding HOLC interrupt will be generated. Also, a Rx overrun
condition, as indicated by BIT 4 of the HOLC STATUS register, will not result in a HOLC interrupt or in setting
the NEW STATUS interrupt bit.
BIT 4 will be cleared upon a reset.
BIT 3 Invalid Flag Interrupt Enable
When BIT 3 is set, a HOLC interrupt will be generated if BIT 3 ( INVALIO FLAG) of the HOLC STATUS register
is also set. If BIT 3 is reset to a 0, BIT 2 ( NEW STATUS) of the HOLC INTERRUPT register will not be set as
a result of an invalid flag boundary detection and no HOLC interrupt will be generated.
BIT 3 will be cleared upon a reset.
BIT 2 Abort Detect Interrupt Enable
When BIT 2 is set, a HOLC interrupt will be generated if BIT 2 (ABORT OETECT) of the HOLC STATUS register
is also set. If BIT 2 is reset to a 0, BIT 2 ( NEW STATUS) of the HOLC INTERRUPT register will not be set as
a result of an abort pattern detection and no HOLC interrupt will be generated.
BIT 2 will be cleared upon a reset.
BIT 1 Idle Detect Interrupt Enable
When BIT 1 is set, an HOLC interrupt will be generated if BIT 1 (IOLE OETECT) ofthe HOLC STATUS register
is also set. If BIT 1 is reset to a 0, BIT 2 (NEW STATUS) of the HOLe INTERRUPT register will not be set as
a result of an idle pattern detection and no HOLC interrupt will be generated.
BIT 1 will be cleared upon a reset.
BIT 0 Flag Detect Interrupt Enable
When BIT 0 is set, a HOLC interrupt will be generated if BIT 0 (FLAG OETECT) of the HOLC STATUS register
is also set. If BIT 0 is reset to a 0, BIT 2 ( NEW STATUS) of the HOLC INTERRUPT register will not be set as
a result of a flag pattern detection and no HOLC interrupt will be generated.
BIT 0 will be cleared upon a reset.
4-16
551730246
Microcontroller
HDLC INTERRUPT REGISTER
HDLC Interrupt Register (HINT) SFR Address C5
Byte Addressable
Read Only register
Reset State OOh
BIT7
BIT 6
BIT 5
BIT4
BIT3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
NEW
STAT
DATA
ROY
TX
ROY
This register is used to determine the source of HDLC interrupts. If one or more of these register bits are
set, the HDLC interrupt will go active if BIT 0 of the HDLC CONTROL register is set to a 1.
BIT 2 New Status
When BIT 2 is set, an unmasked HDLC status bit from the HDLC STATUS register is set.
BIT 2 will by cleared upon a reset and is cleared by a read of the HDLC STATUS register.
BIT 1 Data Ready
When BIT 1 is set, a new received byte has been loaded into the RX DATA register. Note, received bits that are
flag, abort, or idle patterns are not considered data, and will not be loaded into the RX DATA register. All inserted
Os have been removed from this byte. The RX DATA register must be read prior to the completed reception of
the next data byte.
BIT 1 will by cleared upon a reset and is cleared by a read of the RX DATA register.
BIT 0 TX READY
BIT 0 is set if any TX control bit is set as the first bit of data, flag or an idle byte is being transmitted. While
transmitting the current byte, the HDLC state machines are ready for commands pertaining to the next byte to
be transmitted. A new data byte must be loaded into the TX DATA register to clear the TX READY status bit.
BIT 0 will by cleared upon a reset and is cleared by writing to the TX DATA register.
RX DATA REGISTER
RX Data Register (RXD) SFR Address C6
Byte Addressable
Reset state XXh
Read Only
BIT7
BIT6
BIT5
BIT4
BIT3
BIT 2
BIT 1
BITO
RX
DAT7
RX
DAT6
RX
OATS
RX
DAT4
RX
DAT3
RX
DAT2
RX
OAT
RX
DATO
BIT 7 • BIT 0 Received Data Byte
BIT 7through BIT 0 is the received data byte (LSB is received first) with all inserted Os removed. A DATA READY
interrupt will be generated when a new data byte is received. Reading this register will clear the DATA READY
interrupt.
4-17
•
SSI730246
Microcontroller
REGISTER DESCRIPTION (continued)
TX DATA REGISTER
TX Data Register (TXD) SFR Address C7
Byte Addressable
Reset state XXh
Write Only
BIT7
BIT6
BIT5
BIT4
BIT3
BIT 2
BIT 1
BITO
TX
DAT7
TX
DAT6
TX
DAT5
TX
DAT4
TX
DAT3
TX
DAT2
TX
DAT1
TX
DATO
BIT 7· BIT 0 Transmit Data Byte
BIT 7 through BIT 0 will be transmitted at the next byte boundary (LSB first) if the TX CONTROL SEND DATA bit
is set. The HDLC will insert all necessary Os. A TX READY interrupt will be generated when a new data byte can
be loaded into the TX DATA register. Writing this register will clear the TX READY interrupt.
REGISTER
ADDRESS
BIT 7
BIT 6
BITS
BIT4
BIT 3
BIT2
BIT 1
BIT 0
HDlC
CONTROL 0
HDlC
CONTROl1
TX
CONTROL
HDlC
STATUS
HDlC INT
ENABLE
HDLCINT
SOURCE
co
WRXD
WPTXD
TXD
PRXD
RXD
CTRl1
RXD
CTRlO
CLKCTRl
CLK
EN
RXCRC32
RXCRC16
TXCRC32
SEND
ABORT
INVAl
FLAG
INVAL
FlAG IE
SEND
CRC
ABORT
DETECT
ABORT
IE
NEW
STATUS
PTXD
CTRl1
ZERO
ID
SEND
DATA
IDLE
DETECT
IDLE
IE
RX
READY
PTX
CTRlO
HDlC
EN
SEND
FlAG
FlAG
DETECT
FlAG
IE
C1
RESET
C2
0
0
0
C3
INVAl
CRC32
TXRDY
IE
IN VAl
CRC16
RXRDY
IE
TX
UNDER RUN
TXRDY
EN
DIV16
CLK
RX
UNDER RUN
RXRDY
EN
C5
0
0
0
0
0
RX DATA
C6
RXDAT7
RXDAT6
RXDAT5
RXDAT4
RXDAT3
RXDAT2
RXDAT1
RXDATO
TX DATA
C7
TXDAT7
TXDAT6
TXDAT5
TXDAT4
TXDAT3
TXDAT2
TXDAT1
TXDATO
C4
FIGURE 9: HDLC SFR Registers
4-18
TX
READY
551730246
Microcontroller
RESET (option to set)
COMPUTE
DATA
FIGURE 11: CRC 16
The eRe check field is generated by the transmitter.
The computation starts with the first transmitted bit
after the opening flag and stops at the last data bit prior
to the frame check sequence bytes, and excludes
inserted as. The eRe generating logic is initialized to
all as. The bits are shifted in and operated on by the
generating polynomial, X 16 + X12 + X 5 + 1. During eRe
transmission, the bytes in the eRe generating logic
are transmitted, high order bit first.
The receiver also initializes its eRe computation logic
to all ones after the beginning flag. Its polynomial
generator (also X 16 + X12 + X 5 + 1) should see the same
value as the transmitter's polynomial generator as the
last data bit is received. Note the receiver's polynomial
generator does not process inserted as. After the bytes
are received in the frame check sequence, a remainder
of 1111 0000 1011 1000 should be detected in the
receiver's polynomial generator. If this is not the case,
it is assumed that the preceding frame was in error and
an invalid eRe is declared.
4-19
•
SSI730246
Microcontroller
REGISTER DESCRIPTION (continued)
SET
COMPUTE
DATA
FIGURE 12: 32 Bit CRC
ones after the beginning flag. Its polynomial generator
should see the same value as the transmitter's polynomial generator as the last data bit is received. Note the
receiver's polynomial generator does not process inserted Os. After the bytes are received in the frame
check sequence, a remainderof 110111101011 1011
0010000011100011 (XO) through ~2, respectively}
should be detected in the receiver's polynomial generator. If this is not the case, it is assumed that the
preceding frame was in error and an invalid CRC is
declared.
The CRG check field is generated by the transmitter.
The computation starts with the first transmitted bit
after the opening flag and stops at the last data bit prior
to the frame check sequence bytes, and excludes
inserted Os. The CRC generating logic is initialized to
all ones. The bits are shifted in and operated on by the
generating polynomial, X32 + X26 + X23 + X22 + X16 + X12
+X11 +X10+X8+X7 +X5+X4 +X2+X+ 1. DuringCRC
transmission, the bytes in the CRC generating logic are
inverted and transmitted, high order bit first. The receiver also initializes its CRC computation logic to all
4-20
SSI73D246
Microcontroller
PIN DESCRIPTION
NAME
TYPE
PSEN
0
RESET
VND
OSCIN
OSCOUT
VPD
CLKOUT
I
GND
I
0
I
0
TXD
I
RXD
0
PTXCLK
I
DESCRIPTION
Program store enable. This output occurs only during a fetch to external
program memory. (Active low)
Input which is used to initialize the processor. (Active high)
Negative digital voltage. (Digital Ground)
Crystal input for internal oscillator, also input for external source.
Crystal oscillator output.
Positive digital voltage (+5V Digital Supply)
Clock output programmable either OSC/2, OSC/1 or logic O.
Serial input port to 730246 from DTE same as RXD UART input.
Serial output port of 730246 UART to DTE.
Input clock used to transmit data PTXD.
PTXD
0
HDLC Packetizer TX output. This pin can also be programmed to the DTE's
TXD output (clear channel) or the value written into bit 6 of the HDLC control
register. Connects to modem device TXD.
PRXCLK
I
Input clock used to receive data PRXD.
PRXD
I
Serial input port (from modem device).
INT(O )-INT(2)
I
External interrupt 0,1 and 2.
USR1 (0) -USR1 (7)
I/O
User programmable I/O port.
USR2(0} -USR2(7}
I/O
User programmable I/O port.
USR3(0) -USR3(7)
I/O
User programmable I/O port. If the bank select feature is chosen, USR (7) acts
as address bit 17 and USR3 data bit 7 is ignored. Register BNKSEL bit2 (BSEN)
enables bank select, bit 1 (BS1) and bit 0 (BSO) select the appropriate bank.
USR4(0} -USR4(7)
I/O
User programmable I/O port also Chip select enable.
RD
0
Output strobe activated during a bus read. Can be used to enable data onto
the bus from an external device. Used as a read strobe to external data
memory. (Active low)
WR
0
Output strobe during a bus write. Used as a write strobe to external data
memory. (Active low)
ALE
0
Address Latch Enable output pulse for latching the low byte of the address
during accesses to external memory.
AD(0}-AD(7)
I/O
Data bus lines-I/O for devices that require multiplexed address and data bus.
A(0)-A(15)
0
Address bus lines-output latched address for devices that require separate
data and address bus.
NO CONNECTS
No connections, leave open.
4-21
•
SSI730246
Microcontroller
~ffi[}External RAM
(Movx dalB, addr)
0100hO
FFh
D-
On chip externally
addressed memory
Mapped Register
(Movx dalB, addr)
Internal RAM
Indirect addressing only
(mov@Ri)
SFRs direct addressing only
(Mov dalB, addr)
Direct & Indirect addressing
(mov dalB, addr)
(mov@Ri)
FIGURE 1: Memory Map
BANK 3
ADDRESS
96K -128K
32K-64K
64K-96K
32K-64K
BANKO
BANKO
BANKO
ADDRESS
ADDRESS
ADDRESS
0-32K
0-32K
0-32K
BANK 1
SELECTED
BANK 2
SELECTED
BANK 3
SELECTED
FIGURE 2: 128K of Bank-Selected Program Memory
4-22
0-32K
SSI730246
Microcontroller
Address locations 0008 - OOFF are reserved for future use
I
I
0008
0000
USER3
DIR3
I
I
I BNKSEL I
USER4
I
I
DIR4
I
I
I
I
CSEN
I
I
OOOF
0007
FIGURE 3: Memory Mapped Registers
FF
F8
FO
F7
B
EF
E8
EO
ACC
08
*USER2
E7
OF
*DIR2
07
DO
PSW
C8
T2CON
CO
'HDLCO
sa
IP
so
P3
B7
AS
IE
AF
'HDLC1
RCAP2L
RCAP2H
TL2
TH2
'TXC
'HSTAT
'HIE
*HINT
*HRXD
*HTXD
C7
BF
A7
AO
P2
98
SCON
90
*USER1
*DIR1
'IDIR
88
TCON
TMOD
TLO
TL1
80
PO
SP
DPL
DPH
t
CF
9F
SBUF
97
THO
8F
TH1
PCON
* Unique to the SSI 730246. There may not be an equivalent function on an 8052.
BIT ADDRESSABLE
FIGURE 4: 730246 SFR Map
4-23
87
•
SSI730246
Microcontroller
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may cause permanent damage to this device.
PARAMETER
RATING
Supply Voltage
-0.5 to +7.0V
Pin Input Voltage
-0.5 to Vcc +0.5V
Storage Temperature
-55 to + 150°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
4.5 to 5.5V
Oscillator Frequency
DC to 22 MHz
Operating Temperature
-40 to +85°C
DC CHARACTERISTICS
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Input Low Voltage
VIL
(Except OSCIN, RESET, TEST)
-0.5
0.2 Vee- 0.1
V
Input Low Voltage
OSCIN, RESET, TEST
-0.5
0.2 Vcc
V
0.2 Vee +0.9
Vcc+ 0.5
V
0.7 Vcc
Vcc + 0.5
V
VIL
Input High Voltage
VIH
(Except OSCIN, RESET, TEST)
Input High Voltage
OSCIN, RESET, TEST
VIH
Output Low Voltage
(Except OSCOUT)
VOL
101
= 3.2 rnA
0.45
V
Output Low Voltage
OSCOUT
VOLOSC
101
= 2.0 rnA
0.45
V
Output High Voltage
(Except OSCOUT)
VOH
loh
= 3.2 rnA
Vee - 0.45
V
Output High Voltage
OSCOUT
VOHOSC
loh
= 2.0 rnA
Vee - 0.45
V
Input Leakage Current
(Except OSCIN)
ilL
Vss < Vin < Vee
Input Leakage Current
OSCIN
ilL
Vss < Vin < Vee
±1
±1
~
60
~
Maximum Power Supply
Normal Operation
1001
22 MHz
30 pF/pin
40
rnA
Maximum Power Supply
Idle Mode
1002
22 MHz
6
rnA
Maximum Power Supply
Power Down Mode
1003
10
~
10
pF
Pin Capacitance
CIO
@1 MHz
4-24
SSI730246
Microcontroller
ACTIMING
PARAMETER
MIN
CONDITION
NOM
MAX
UNIT
22.2
MHz
Oscillator Frequency
FOSe
0
Oscillator Period
TOSe
45
ns
ALE Pulse Width
TLHLL
2TOSe -10
ns
Address Valid To ALE low
TAVLL
TOSe
ns
Address Valid to ALE low
TLLAX
TOSe -10
ns
ALE low to PSEN low
TLLPL
TOSe -10
ns
PSEN Pulse width low
TPLPH
3TOSe - 20
PSEN Low to Valid Inst In
TPLIV
Address to Valid Inst In
TAVIV
Input Instr Hold-PSEN Hi
TPXIX
ns
3TOSe - 50
ns
5TOSe - 50
ns
ns
0
PSEN Instr Float-PSEN Hi
TPXIZ
20+
ns
PSEN Low to Address HIZ
TPLAZ
10
ns
RD Pulse Width
TRLRH
6TOSe - 20
WR Pulse Width
TWLWH
6TOSe - 20
RD Low to Valid Data In
TRLDV
Data Hold After RD
TRHDX
Data Float After RD
TRHDZ
ALE Low to Valid Data In
TLLDV
ALE low to RD or WR low
TLLWL
ns
ns
5TOSe - 50
ns
0
20+
3TOSe - 20
ns
ns
8TOSe - 50
ns
3TOSe + 20
ns
Data Valid to WR low
TOVWX
TOSe
ns
Data Hold After WR Hi
TWHOX
TOSe -10
ns
RD low to Address Float
TRLAZ
10
The SSI 730246 timing is very similar to the 8051
except in AO(7:0), the multiplexed address data port
known as port 0 in the 8051. Its timing has been altered
somewhat to allow more address setup time for
peripheral program ROM and memory mapped
peripherals. This is important at 22 MHz operation. The
8052 has a "dead" cycle of one oscillator period between
the time PSEN goes high, indicating that the instruction
ROM will release the AO(7:0) bus, to the time the
processor will assert address on the AO(7:0) bus. This
dead time of one whole oscillator cycle has been
shortened to approximately 15 ns after the PSEN (or
RO) signal is sensed to be high.
4-25
ns
The timing specification for TPXIZ and TRHOZ of a
maximum of 15 ns can be violated at the expense of
increased operating current. The SSI 730246 will
begin asserting the AO(7:0) bus approximately 20 ns
after PSEN or RO go high. This should be ample time
forthe control signals in the peripheral device to turn off
their pad drivers. If the peripheral device does not
release the bus promptly, there will be a short time
where there is contention on the AO(7:0) bus between
the processor and peripheral. This should not prevent
proper operation, but it will increase operating current
slightly.
I
SSI730246
Microcontroller
OSCIN
TLHLL
ALE
TPLPH
AO(7:0)
INSTRIN
AO-A7
TAVIV
TPXIX
A(15:0)
A(15:O)
TAVLL
FIGURE 5: External Program Memory Read Cycle
Tose
TllWl
RD ----------------------~-----.~----T~----_r~~r---------TRLDV
AD (7:0)
DATA IN
TlLDV
A (15:0)
FIGURE 6: External Data Memory Read Cycle
4-26
SSI730246
Microcontroller
lose
-i
~
OSCIN
ALE
ru.WL
TRLRH
RD
- - - - - - - - - - + - - + -... I...------t----'~ . - - - - - lOVWX
AD (7:0)
DATA OUT
AO-A7
I
A (15:0)
FIGURE 7: External Data Memory Write Cycle
4-27
551730246
Microcontroller
USER INTERFACE
SSI73D2248 DEVICE SET
iR
ti.m
iR
ti.m
CD
CD
M
M
OH
OH
HS
HS
m-s
~m
~i5CD
OCD..,::
C1'S
RXD
EXCLK
~
,.;C1'S
j
i
TXA
~
~ TXA
RXA
!
~ RXA
-RXl5
~ AGO
.. AG1
... POWER
EXCD<
~DRT
D'fR..,::
FITS
.... 'RTS"
iXD~
~TXD
.....
ROOK
~Am<
~DSR
DSR.,;:
mGNO
AA10UT
AA20UT
ENT
RBllN
RB21N
RB31N
RB41N
18
14
15
AMOUT
TB10UT
TB20UT
TB30UT
TB40UT
26
_19.
TA2IN
ENAA
RAlIN
RA21N
RA31N
RA4IN
+
~
~~F
22
I
~
ATS
fXD
~
AXCLK
TXCLK
1
1
~~~~28 ~ ~T11°1r3
C102
:0:;
m~
~_ _ _ _ _ _ _ _ _ _ _C_1_01111L--...~11000PFI
T I
I~~
~~
S11Q
~
~A70
~
2
D102
1NS228
XMOUT
s:en
_. en
(')-
TECCOR
SIDACTOR
O~
(')W
,O'SA1
00
:::::IN
...
~
675-8005
MIDCOM
R106
(0)
CD
+SVD
11~
-
+5VD
U101
211 12
g
2
R112
200Q
73M376
0
1§.
14
m~1 ~: ~
IMON~
-
C103
§J---11
.1~F
AGO
~
17
I
Rev
-
AG1
HKL
LOOP
10
HOO'i(
C10S
w
C106
o
-
-
-
-
-
-I
:d
20~
R110
R111
,-
38.4~
390pF
~C/rl!
~
2
.........
5
-u--'
'"~, 1, "~~
AQV214
:
4
R115 :
14
e10e
II
-I'T
0.1 ~F
+SVD
tIL
1\ 10~F
~
S6~
RJ11
-1-
R116
_ _ _ _ _ _ _ _ _ 1 __
8.2~
1/4W
t--J I
SP?
II
33~F
~--+-----------'
i I~~"
U104
RING
RING
C112
For caller /.0.
RJ4
RJS
RJ6
R107
SPEAKER
t-I
RJ1
~w
DGND
R113
5.1 KQ
RJ11
J102
PHONE
+5 VA
J
.j:>.
-
f - -f --,.
;---
DGND
C104 ---L-.
0.1MF , -
**
-~
~
AOX
-
,
----L-C107
~
AG1
'POWER
-
~
I·'" ~~~
SOQ1/2W
AQV214
AROMAT
I
AUX
---L-.
, - C109
0.15 ~F 300V
NON-POLARIZED CAPACITOR
AGND
** The tracks to the wires within the dashed lines should be as short as possible.
D104
lN914
DGND
** The tracks to the wires within the dashed lines should be as short as possible.
FIGURE 15: Telephone Interface
SSI730246
Microcontroller
R3
20K
~
=.
2
3
4
-=:J
-=:J
-=:J
<
>:
01
GND
OSCIN
65
GN~
~GND
USR3.2
74
56
57
-+.
ALE
USA2.0
USR1.7
USR1.6
USR1.5
47
46
A6
AS
A1
AO
AD7
AD6
1lfR
=
RING
I
AD4
AD3
36
35
37
11
A6
AS
A4
A3
I
100
98
'7
DO
DO
96
_ _ _ _ _ ADO - A07
93
92
66
6.
--F ~;R4.0
~
22-
IUSR4.,
=
.
10
67
88
TXD
~NlC
1=
AI1
A10
A.
A8
"
34
33
6.
88
90
20
AI1
A10
A.
USR2.1
~
II
USR2.7
USR2.6
USR2.3
USR2.2
--+
=
=
WA
All
USA2.5
~
0
USA3.1
USR2.4
60
~
12~Pf
MR
.CD
DUM
HOOK
~
I.l&L--
V
oseD
64
fA
Ii!R
1=
0
20p!
GND
~
~
~2
DO
7
6
5
730246-IG
RXCLK
TXCLK
MTXD
-=-----
=---
.01
~
U,
~
~
~
~
~
~
~
~
~
~
~
A16
20
11
AO
A1
01
A2
02
A3
A4
AS
AS
A7
12
"
15
DO
01
02
05
06
AS
A.
"0
AI1
.,2
A1,
A14
"5
a
llE
FIGURE 16A: 2248 Modem System Interconnect - Front End
4-31
SSI730246
Microcontroller
CLKOUT - - - - - - - - - - - - - - - - - - ,
WR--------._________-+_-, >
~------~~----------+-.
ALE--H-----h
I
A4
10K
'-+--~~ AD
12
11
10
u6
D5
D4
D3
D2
9
ALE
AD7
AD6
ADS
AD4
AD3
DO
4
3
±
ADl
ADO
XTL2
VDD
TXA
tNT
TXCLK
EXCLK
CS
AXD
AXCLK
ISET
XTl1
AESET
VAEF
AXA
CLK
GND
18
20
~
22
23
('
R5
('
2M
25
26
,,7
28
~
I-orr--+++++-+-I-----,
:;:::::::;- ~.1 ~F
31
h,,---i-H--J-JH--i---1r--+---'---<
S8] 73K224L-321H
ADO-AD7------_+-!_-I
Cl1 :::::::::::
O.1jJF
USA4.7 - - - - - - - ,
VCC
AGND
({
(
>
A41
',>
20K
USA 4.0
AXCLK
TXCLK
MTXD
MAXD
EXCLK
ALE
U4
AO
A1
10
9
'"
A3
A2
A4
AS
AS
AS
AO
A(
A8
A9
A1u
A11
A12
A13
A14
vec
L
A8
-A./'
A1
SRAM
00
01
02
03
04
05
DO
D1
15
16
18
u"
D3
D4
D5
u6
D7
25
24
21
23
A9
A11
A12
A13
A14
20
22
---2!......
cs
OE
WE
vec
~
GND
~GND
VCC
51257ALL
FIGURE 16B: 2248 Modem System Interconnect - Back End
4-32
AXA
551730246
Microcontroller
100-Pin PGA (For developement purposes only; not a production package.)
BOND
PRO
PIN #
SIGNAL NAME
BOND
PRO
PIN #
SIGNAL NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
82
81
C2
C1
02
01
E2
E1
F3
F2
F1
G2
G3
G1
H1
H2
H3
J1
J2
K1
K2
NO CONNECT
NO CONNECT
USR27
USR26
USR25
USR24
USR23
USR22
USR21
USR20
VPO
GNO
USR47
USR46
USR45
USR44
USR43
USR42
USR41
USR40
USR30
USR31
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
USR32
USR33
USR34
USR35
USR36
USR37
GNO
RO
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
M7
L7
N7
N8
M8
L8
N9
M9
N10
M10
N11
N12
M11
N13
M12
M13
L12
L13
K12
K13
J12
J13
H11
H12
H13
G12
G11
G13
F13
F12
F11
E13
E12
013
012
C13
WR
ALE
00
01
02
03
04
05
06
07
VPO
AO
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
PSEN
RESET
GNO
OSCOUT
L1
M1
L2
N1
M2
N2
M3
N3
M4
N4
M5
N5
L6
M6
N6
63
64
65
66
67
68
69
70
71
72
4-33
I
551730246
Microcontroller
100-Pin PGA
BOND
PRO
(continued)
PIN #
SIGNAL NAME
BOND
PRO
SIGNAL NAME
PIN#
73
813
OSCIN
87
87
74
C12
NO CONNECT
88
C7
INTO
75
A13
NO CONNECT
89
A7
GND
76
812
NO CONNECT
90
A6
USR10
77
A12
NO CONNECT
91
86
USR11
78
811
VPD
92
C6
USR12
79
A11
CLKOUT
93
A5
USR13
80
810
TXD
94
85
USR14
81
A10
RXD
95
A4
USR15
82
89
PTXCLK
96
84
USR16
83
A9
PTXD
97
A3
USR17
84
C8
PRXCLK
98
A2
NO CONNECT
85
B8
PRXD
99
83
NO CONNECT
86
A8
INT2
100
A1
NO CONNECT
INT1
N
M
L
K
J
H
-+~~~~--------+-------~~~~~rG
F
E
D
C
8
A
2
3
4
5
6
78
9
10 11
FIGURE 17: 100-Pin Plug-In Package
4-34
12 13
SSI730246
Microcontroller
PACKAGE PIN DESIGNATIONS
(Top View)
N/C
N/C
N/C
N/C
2
3
Ai
4
A2
N/C
5
N/C
USR31
USR30
A3
6
USR40
A4
7
USR41
A5
8
USR42
A6
9
USR43
A7
10
USR44
A8
11
A9
12
A10
USR45
13
64
63
USR46
USR47
A11
14
62
N/C
A12
A13
A14
15
16
61
17
A15
PSEN
18
19
VPD
USR20
USR21
USR22
USR23
RESET
20
USR24
VND
OSCOUT
21
USR25
22
23
USR26
OSCIN
60
59
USR27
N/C
NIC
NIC
51
~~~~gM~~~~~~~~~~~~~~~~~~~
10o-Lead TQFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
4-35
N/C
I
SSI73D246
Microcontroller
PACKAGE PIN DESIGNATIONS
(Top View)
NlC
N/e
N/e
N/C
N/C
NlC
NlC
N/e
NlC
N/C
Al
K2.
A3
A4
AS
AS
USR31
USR30
USR40
USR41
USR4Z
USR43
USR44
USR45
USR46
USR47
VND
VPO
USRZO
USRZl
USR22
USR23
USR24
USR25
USRZ6
USRZ7
A7
AS
A9
Al0
All
A12
A13
A14
A15
~
RESET
VND
OSCOUT
OSCIN
N/C
N/C
N/C
N/e
N/C
NlC
N/e
N/e
N/C
N/C
100-Lead QFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for final
design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1193
4-36
©1993 Silicon Systems, Inc.
5517302240
V.22bis 2400 Bitls
Modem Device Set
Oecember 1992
DESCRIPTION
FEATURES
The SSI 7302240 is a set of two ICs that provide the
data pump functions needed to design a high-performance, low-power 2400 bitls intelligent modemforuse in
dial-up telephone network applications. The SSI
7302240 consists of the SSI 73K224L 1-chip multimode modem along with the SS1730600, acompanion
supervisory controller that provides a complete "AT"
command and feature set compatible with industry
standard products.
•
Multi-mode V.22bisN.22N.21 & Bell 212A1103 compatible device set for intelligent modem designs
•
Full duplex operation at 0-300, 1200 and 2400 bitls
with all synch & asynch operating modes
•
Includes high-level "AT" command interpreter
compatible with 2400 bitls industry standard products
•
SSI 73K600 Controller Compatible with other
K-series products
The SSI 7302240 includes operating modes compatible with CCITT V.22bis, V.22, and V.21 , as well as Bell
212A and 103 data communications standards. Using
advanced CMOS processes that integrate analog,
digital signal processing and switched capacitor filter
functions on the same chip, the SSI 7302240 offers
excellent performance, full modem features and the
lowest power consumption available in a compact 2chip set.
•
•
Complete complement of "AT" modem features
(continued)
Selectable automatic speed detect, handshake and
autobaud functions
•
Supports external non-volatile memory to store
user configurations
•
Adaptive equalization for optimum performance
over all lines
•
Dynamic range from -3 to ·45 dBm
(continued)
BLOCK DIAGRAM
Relay Drivers
Volume Control
User Interface
m
VC2
NVSK
~
~
NOVRAM
RST
TXD
RXD
RINGO
TXINT
NVRM
fiE
X2
Xl
GND
GND
RXA
VREF
RESET
ISET
RXCLK
RXD
voo
ADO
ADl
AD2
AD3
AD4
ADS
ADS
AD7
XEN
~
EXCLK
TX~
~
TXA
VOO
ffi
m
AA
CO
~
m
m
A(N
LED Drivers
12 - rev.
4-37
CAUTION: Use handling procedures necessary
for a static sensitive component.
•
SSI73D2240
V.22bis 2400 Bitls
Modem Device Set
DESCRIPTION
QAM MODULATOR/DEMODULATOR
(continued)
The SSI 7302240 scrambles and encodes the
2400 biVs incoming data into quad bits represented by
16 possible signal points as specified by CCITT recommendation V.22 bis. The modulator transmits this encoded data using either a 1200 Hz (originate mode) or
2400 Hz (answer mode) carrier. The demodulator
reverses this procedure and recovers a data clock from
the incoming signal. Adaptive equalization corrects for
different line conditions by automatically changing filter
parameters to compensate for line characteristics.
The SSI 7302240 can be used in free-standing and
integral modem designs where full-duplex 2400 bit/s
operation is required. Single 5V supply operation with
extremely low power draw make it ideal for battery
powered terminals, lap-top PCs and other power sensitive applications.
FEATURES (continued)
Call progress, carrier and answer tone
detectors provide intelligent dialing functions
•
DTMF and CCITT guard tone generators
•
Test modes available - ALB, DL, RDL for
complete test capability
•
All CMOS technology for low power
consumption « 600mW using ±5V)
DPSK MODULATOR/DEMODULATOR
In OPSK mode the SSI7302240 modulates the 1200
bit/s incoming data using a subset of the QAM signal
points as specified by CCITT recommendation
V.22bis, V.22 and Bell 212A. The OPSK demodulator
is similar to the QAM demodulator.
FSK MODULATOR/DEMODULATOR
OPERATION
The FSK transmitter frequency modulates the analog
output signal using two discrete frequencies to represent the binary data. The Bell 103 standard frequencies of 1270 and 1070 Hz (originate mark and space)
and 2225 and 2025 Hz (answer mark and space) orthe
V.21 standard frequencies of 980 and 1180 Hz (originate mark and space) and 1650 and 1850 Hz (answer
mark and space) are used when this mode is selected.
Demodulation involves detecting the received frequencies and decoding them into the appropriate binary value.
The SSI 7302240 is a complete V.22bis intelligent
modem contained in two CMOS ICs. The device set
forms the basis for a high performance stand-alone
modem product with self-contained command interpreter, indicator LEOs, and interface lines for an RS232 serial port. Both data and commands are passed
over the serial port as in conventional intelligent modem designs.
The SSI 7302240 provides the QAM, PSK and FSK
modulator/demodulator functions, call progress and
handshake tone monitors, test modes and a tone
generator capable of producing OTMF, answer and
CCITT guard tones. This device supports the V.22bis,
V.22, V.21 and Bell 212A1103 operating modes, both
synchronous and asynchronous. The SSI7302240 is
designed to provide functions needed for an intelligent
modem and includes auto-diaVaut~-answer, handshake with auto-fallback, and selectable pulse or
OTMF dialing sequences to simplify these designs.
PASSBAND FILTERS AND EQUALIZERS
A bandsplit filter is included to shape the amplitude and
phase response of the transmit signal to a square root
75% raised cosine and provide rejection of out-of-band
signals in the receive channel.
ASYNCHRONOUS MODES
The character asynchronous modes are used for communication between asynchronous terminals which
may vary the data rate from +1.5% to -2.3%. When
transmitting in this mode the serial data on the TXO
input is passed through a rate converter which inserts
or deletes stop bits in the serial bit stream in order to
output the data within 0.01 %. The signal is routed to a
data scrambler (following the CCITT V.22bis algorithm) and into the modulator. The 7302240 recognizes a break Signal and handles it in accordance with
The SSI 7302240 consists of two devices. The
SSI 73K224L is an analog processor and OSP that
perform the filtering, timing adjustment, level detection
and modulation/demodulation functions. The
SSI730600 is a command processor that provides
supervisory control and command interpretation. The
SSI 730600 is also compatible with the SSI 73K212,
221 and 222 K-series modem ICs.
4-38
8817302240
V.22bis 2400 Bitls
Modem Device Set
specifications. Received data is processed in a similar
fashion except that the rate converter now acts to
reinsert any deleted stop bits. An incoming break signal
will be passed through without incorrectly inserting a
stop bit.
SYNCHRONOUS MODES
8ynchronous operation is possible only with the QAM
or OP8K modes. Operation is similar to that of the
asynchronous mode except that data must be synchronized to a provided clock and no variation in data
transfer rate is allowable. External synchronous mode
is provided for a user supplied clock accurate to
±0.01%. 8erial input data appearing at TXO must be
valid on the rising edge of TXCLK. Receive data at the
RXO output is clocked out on the rising edge of RXCLK.
The async/synch converter is bypassed when synchronous mode is selected and data is transmitted out
at the same rate as is input. The RXCLK, TXCLK and
EXCLK are for synchronous modes only.
AUTOMATIC HANDSHAKE
The 881 7302240 will automatically perform a complete handshake as defined by the V.22bis, V.22 and
Bell 212N103 standards to connect with a remote
modem. The 881 7302240 automatically determines
the speed and operating mode and adjusts its operation to correspond to that of an answering modem
when originating a call.
ADAPTIVE EQUALIZATION WITH AUTO-RETRAIN
The 881 7302240 uses adaptive equalization which
automatically compensates for varying line characteristics by adjusting taps on a mUlti-tap FIR filter. Optimum performance is obtained with this technique over
a wide range of line conditions. When the line quality
deteriorates to a specified level the 8817302240 can
automatically initiate a retrain of the equalizer to reestablish data communications without the need to go
through a complete handshake sequence.
"AT" COMMAND INTERPRETER
The 8817302240 includes an AT command interpreter
which is compatible with the Hayes 2400 8martmodem™ command set. Functions and features includedwith intelligent modems are provided by the 881 •
7302240 command interpreter. The 881 730600 con•
troller may also be used with the 881 73K212, K221 ,
and K222. It will function with these parts in the modes
supported by the device. It will still support the Hayes
8martmodem™ 2400 commands even though operation at 2400 bitls will not be permitted. The controller
reads the device signature of the modem IC installed to
determine which modes should be allowed.
NON-VOLATILE MEMORY
The 881 7302240 supports connection to an external
non-volatile memory (National 9346 or equivalent) to
store dial strings and the current AT command configuration. If NOVRAM is not present, the factory default
configuration is automatically used, but dial string
storage is not permitted.
TEST MODES
The 881 7302240 allows use of Analog Loopback,
Digital Loopback and Remote Digital Loopback test
modes. Full test mode capability allows testing of the
modem and interface functions from the local terminal
using the appropriate control commands, or remotely
using the ROL function.
4-39
SSI73D2240
V.22bis 2400 Bitls
Modem Device Set
SPEED/PROTOCOL COMPATIBILITY GUIDE
7302240 originating
CCITT
Bell
Calling a:
Bell
CCIIT
300
1200
300
1200
2400
300
(103)
300
300
-
-
300
1200
(212)
300
1200
1200
1200
2400 1
(224)
300
1200
-
1200
2400
300
(V.21)
-
-
300
-
-
1200
(V.22)
300
1200
-
1200
1200
2400
(V.22bis)
300
1200
-
1200
2400
7302240 answering
CCITT
1
as:
CCITT
Bell
Bell
as:
Called from a:
300
1200
300
1200
2400
300
(103)
300
300
-
-
300
1200
(212)
300
1200
1200
1200
2400
(224)
300
1200
-
1200
2400
300
(V.21)
-
-
300
-
-
1200
(V.22)
300
1200
1200
1200
2400
(V.22bis)
300
1200
-
1200
2400
A Bell 2400 is a V.22bis using a 2225 Hz answer tone without unscrambled marks.
4-40
SSI7302240
V.22bis 2400 Bitls
Modem Device Set
"AT" COMMANDS SUPPORTED
(Note: s=string; n=decimal, 0-255; x=Boolean, 0/1 =false/true)
COMMAND
OPTIONS
DEFAULT
AI
Repeats last command line
N/A
A
Answer
N/A
Bx
BELUCCITT = 1/0 answer tone @1200 (N/A @2400)
1
OS= n
Dial string specified by n, n = 0-3
n=O
Ex
Command echo, 0/1 = off/on
1
Hn
Hook status, 0/1 = on/off
N/A
In
10 code, 0/1/2 (see Table 8)
N/A
Ln
Speaker volume, (0)1/2/3 = lo/med/hi
2
Mn
Speaker, 0/1/2/3 = control (see Table 3)
1
On
Online, 0/1/2/3 = online/retrain/no retrain (see Table 4)
N/A
P
Pulse dial
Pulse
Qx
Quiet result, 0/1 = 1-quiet
0
R
Reverse originate
N/A
Sn=n
Set S register (see Table 2)
N/A
Sn?
Return value in register n (see Table 2)
N/A
T
Touch tone dial
Pulse
Vx
Verbose result, 0/1 = off/on
1
Xn
Result code, 0/1/2/3/4 (see Table 1)
4
Yx
Enable long space disconnect, 1 = enable
0
Zx
Restore from Non-Volatile Memory, x = 0 or 1
N/A
&Cx
Carrier detect override, 0/1 = on/normal
0
&On
OTR mode, 0/1/2/3 (see Table 5)
0
&F
Restore to factory configuration
N/A
&Gn
CCITT guard tone, 0/1/2 = off/1800/550
0
&Jx
Auxiliary relay control
0
&Mn
AsynclSync mode, 0/1/2/3 (see Table 6)
0
4-41
•
SSI73D2240
V.22bis 2400 Bitls
Modem Device Set
"AT" COMMANDS SUPPORTED (continued)
COMMAND
OPTIONS
DEFAULT
&Px
Pulse dial mode, 011 =U.S./U.K.
0
&Qx
Same as &M
N/A
&Rx
Enable RTS/CTS
0
&Sx
DSR override, OI1=U.S./U.K.
0
&Tn
Test mode (see Table 7)
&V
View active configuration and user profiles
N/A
N/A
&Wx
Write current configuration to NVRAM x = 0 or 1
0
&Xn
Sync Tx clock mode, 011/2=inVext/slave
0
&Yx
Designate default user profile ZO or Z1
&Zn= s
Store a telephone number n = 0-3
N/A
N/A
Factory configuration':
B1 E1 F1 L2 M1 P
ao
V1 X4 YO &CO &00 &GO &JO &MO &PO &RO &SO &T4 &XO
Dial string arguments:
, = delay
; = return to command
@ = silent answer
s = dial stored number
! = flash
W = wait for tone
R=reverse mode
TABLE 1: Result Codes
Xn
VOCAL/NUMERIC RESULT CODE
XO
OKlO, CONNECTI1, RINGl2, NO CARRIERl3, ERROR/4
X1
All functions of XO + CONNECT (RATE)11 = 300,5 = 1200,10 = 2400
X2
All functions of X1 + NO DIAL TONE/6
X3
All functions of X1 + BUSYI7
X4
A" functions of X3 + NO DIAL TONE/6
TABLE 2: S Registers Supported
Sn
FUNCTION
UNITS
DEFAULT
S02
Answer on ring
No. of rings
000
S1
Ring counter
No. of rings up to 8
000
S2
Escape code
ASCII CHR$()
043
S3
Carriage return
ASCII CHR$()
013
,
If the NOVRAM has not been initialized it may be necessary to Power down/Power up and type AT&F& W
to properly initialize modem state.
2 Stored in NVRAM with &W command
1
4-42
SSI7302240
V.22bis 2400 Bitls
Modem Device Set
TABLE 2: S Registers Supported
NUMBER
S4
(continued)
FUNCTION
UNITS
Line feed
ASCII CHR$()
DEFAULT
010
S5
Back space
ASCII CHR$()
008
S6
Wait for dial tone
Seconds
002
S7
Wait for carrier
Seconds
030
88
Pause time
Seconds
002
89
Carrier valid
100 milliseconds
006
810
Carrier drop out
100 milliseconds
014
S11
DTMF tone duration
1 millisecond
070
812
Escape guard time
20 milliseconds
050
S13
*S142
N/A
Unused
Bit mapped register
Decimal 0-255
170
N/A
815
Unused
816
Test register
Decimal #
000
818
Test timer
Decimal 0-255
000
819
Unused
820
N/A
N/A
Unused
*8212
Bit mapped register
Decimal 0-255
000
*S222
Bit mapped register
Decimal 0-255
118
*8232
Bit mapped register
Decimal 0-255
S24
8252
Unused
DTR delay
10 milliseconds
005
8262
CT8 delay
10 milliseconds
001
*8272
Bit mapped register
Decimal 0-255
064
007
N/A
* The bit mapped register functions are equivalent to normal "AT" command modem registers. They are not
needed for evaluation of the 7302240 capabilities.
Asynchronous character formats supported:
[Number of data bits, parity (even/odd/none), number of stop bits]
1200/2400 bitls: 7N2, 7E1, 701, 8N1
300 bitls: 7N2, 7E1, 701, 8N1
2 Stored in NVRAM with &W command
4-43
•
SSI7302240
V.22bis 2400 Bitls
Modem Device Set
TABLE 3: Speaker Modes
TABLE 6: Synchronous Modes
Mn
SPEAKER MODE
&Mn
SYNCHRONOUS MODE
MO
Speaker off
&MO
Asynchronous
M1
Speaker on during connect only
&M1
M2
Speaker on always
Sync mode entered upon completion of
connect sequence
M3
Speaker on during call progress
&M2
Dial stored number on OFF to ON transition of OTR and go online
&M3
Manual dial using OTR as talk data
switch
TABLE 4: 0 Modes
On
ONLINE/RETRAIN MODE
00
Return online
01
Return online with retrain
02
03
TABLE 7: Test Modes
&Tn
TEST MODE
Enable automatic retrain (default)
&TO
End/Abort test
Disable automatic retrain
&T1
Initiate local analog loopback (L3)
&T3
Initiate local digitalloopback
&T4
Permit remote digital loopback (L2)
&T5
Prohibit remote digitalloopback
TABLE 5: DTR Modes
&Dn
DTR MODE
&T6
Initiate remote digitalloopback (L2)
&00
Ignore OTR
&T7
&01
Initiate ROL with self-test and error
detector
Go to command state if ON to OFF
detected
&T8
Initiate ALB with self-test and error
detector
&02
Go to command state and disable autoanswer if ON to OFF detected
&03
Initialize modem with NVRAM if ON to
OFF detected
TABLE 8: 10 Codes
4-44
In
CODE
10
Product code (249)
I1
ROM checksum
12
Checksum test
13
Product revision
14
Software copyright
5517302240
V.22bis 2400 Bitls
Modem Device Set
HARDWARE INTERFACE
POWER SUPPLIES AND CLOCKS
LABEL
PIN CONNECTION
I/O
DESCRIPTION
73K224L
730600
40
VDD
I
15
GND
I
28
GND
I
28
X1
I
ClK
0
1
RST
I
25
Positive supply (+5V)
System ground
Digital ground
19
Clock input 11.0592 MHz
Clock output 11.0592 MHz
Reset (10 p.F & 8.2k)
9
DAAINTERFACE
RxA
I
27
Receive analog from OM
TxA
0
0
0
16
Transmit analog to DAA
VC1
VC2
6
Audio volume control
4
Audio volume control
RINGO
I
12
From ring indicator
OH
0
0
1
Off hook relay control
21
Auxiliary relay control
AUX
RS-232IV .24 INTERFACE
RI
HS
0
0
22
Ring indicator output
23
Indicates high speed
Digital data from terminal
TXD
I
21
10
RXD
22
11
Digital receive data
3
Data carrier detect
DSR
0
0
0
EXClK
I
19
RXClK
23
Receive clock ouptut
18
Transmit clock output
CTS
0
0
0
RTS
I
2
Request to send
DTR
I
7
Indicates DTE available
DCD
TXClK
24
Data set ready
External T x sync clock input
8
Clear to send
4-45
•
SSI7302240
V.22bis 2400 Bitls
Modem Device Set
HARDWARE INTERFACE (continued)
LED DISPLAY SIGNAL SOURCE
PIN CONNECTION
LABEL
I/O
730600
DESCRIPTION
TR
LED
28
Data terminal ready (Active Low)
SO
LED
11
Transmit data (Mark
RO
LED
10
Receive data (Mark
CD
LED
25
Data carrier detect (Active Low)
HS
LED
23
High speed indicator (Active Low)
MR
LED
27
Modem readyltest in progress (Active Low)
AA
LED
26
Auto answer indicator (Active Low)
OH
LED
1
= High)
= High)
Off hook indicator (Active Low)
NVRAM INTERFACE 730600
NVCE
0
15
NVCE
NVRM
liD
14
NVRM
NVSK
0
5
NVSK
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VDD Supply Voltage
UNIT
RATING
73K224L
7
V
73D600
7
V
-65 to 150
°C
260
°C
V
Storage Temperature
Soldering Temperature (10 sec.)
Applied Voltage
-0.3 to VD D+0.3
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection
devices and all outputs are short-circuit protected.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
External Components (Refer to Application section for placement.)
VREF Bypass capacitor
(VREF to GND)
Bias setting resistor
(Placed between VDD
and ISET pins)
1.8
ISET Bypass capacitor
(ISET pin to GND)
0.1
VDD Bypass capacitor 1
(VDDto GND)
0.1
VDD Bypass capacitor 2
(VDDto GND)
22
0.1
4-46
JlF
2
2.2
MQ
JlF
JlF
JlF
SSI73D2240
V.22bis 2400 Bitls
Modem Device Set
RECOMMENDED OPERATING CONDITIONS
PARAMETER
(continued)
MIN
CONDITIONS
NOM
MAX
UNITS
External Components· 730600
VDD Bypass Capacitor
XTL 1 , 2 Load Capacitors
Clock Variation
~F
VOOto GNO
1
Typical, depends on crystal
15
40
pF
-0.01
+0.01
%
0
55
°C
5
5.5
V
25
30
rnA
3
5
rnA
(11.0592 MHz) Crystal or
external clock
TA, Operating Free-Air
Temperature
DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to +85°C, VOO = recommended range unless otherwise noted.)
VDD Supply Voltage
730600, 73K224l
4.75
100, Supply Current
CLK = 11.0592 MHz
73K224L
ISET Resistor
= 2 Mn
1001, Active
1002, Idle
730600
CLK = 11.0592 MHz
1001, Active
16
rnA
1002, Idle
3.7
rnA
0.8
V
2.0
VOO
V
3.0
VOO
V
100
~
Digital Inputs 73K224L
Vll, Input low Voltage
VIH, Input High Voltage
All Inputs except Reset
XTL1, XTL2
Reset, XTL 1 , XTL2
IIH, Input High Current
VI = VIH MAX
Ill, Input low Current
VI
Reset Pull-down Current
Reset = VOO
= VIL MIN
~
-200
5
50
~
2.4
VOO
V
Digital Outputs 73K224L
VOH, Output High Voltage
10 = 10H Min
lOUT = -0.4 rnA
VOL, Output Low Voltage
10 = lOUT = 1.6 rnA
0.4
V
VOL, ClK Output
lOUT = 3.6 mA
0.6
V
RXO Tri-State Pull-up Curro
RXO=GNO
-50
~
-5
Capacitance 73K224L
Inputs
Input capacitance, all Oigitallnput
pins
10
pF
CLK
Maximum Capacitive Load
15
pF
4-47
•
SSI7302240
V.22bis 2400 Bitls
Modem Device Set
DC ELECTRICAL CHARACTERISTICS (continued)
PARAMETER
MIN
CONDITIONS
MAX
UNITS
0
.2VDD-.1
V
Reset, X1
.7VDD
VDD
V
All Other Pins
.2VDD
+.9
VDD
V
-50
~
-500
~
NOM
Digital Inputs 730600
VIL, Input Low Voltage
VIH, Input High Voltage
ilL, Low Input Current
Vin = 0.45 V
ITL, Logic 1 to 0
Transition Current
Vin = 2.0V
Digital Outputs 730600
VOH Output High Voltage
All Ports
Except ALE, ADO-7
IOH = -80~
2.4
ADO-7, ALE
IOH = -400~
2.4
V
VOL Output Low Voltage
All Ports
Except ALE, ADO-7
IOL = 1.6 rnA
0.45
ADO-7, ALE
IOL =3.2 rnA
0.45
V
125
kn
Reset Pull Down Resistor
40
V
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNITS
Carrier Suppression
Measured at TXA
Output Amplitude
TX scrambled marks
35
-11.5
-10.0
-9
dBmO
+.20
%
QAM/DPSK Modulator
dB
FSK Modulator
Output Freq. Error
CLK = 11.0592 MHz
-0.31
Transmit Level
Transmit Dotting Pattern
-11.5
Output Distortion
All products through BPF
Sum of Output Bias
Distortion and Output Jitter
Transmit Dotting Pattern
in ALB @ RXD Bell 103 Originate
-10.0
-20
-9
dBmO
-45
dB
+20
%
-9
dBmO
-40
dB
2100 Hz Answer Tone Generator
Output Amplitude
Output Distortion
-11.5
All products though BPF
-10
NOTE: Parameters expressed in dBmO refer to the following definition:
odB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the OM design.
4-48
SSI7302240
V.22bis 2400 Bit/s
Modem Device Set
DYNAMIC CHARACTERISTICS AND TIMING (continued)
PARAMETERS
MIN
CONDITIONS
NOM
MAX
UNITS
+0.25
%
DTMF Generator
Freq. Accuracy
0.03
Output Amplitude
-10
-8
dBmO
Output Amplitude
-8
-6
dBmO
Twist
Receiver Dynamic Range
Call Progress Detector
Detect Level
High-Band to Low-Band
1.0
3.0
dB
Refer to Performance Curves
-43
-3
dBmO
-34
0
dBmO
-50
dBmO
25
ms
25
ms
2.0
In Call Init mode
460 Hz test signal
Reject Level
Delay Time
-70 dBmO to -30 dBmO STEP
Hold Time
-30 dBmO to -70 dBmO STEP
Hysteresis
dB
2
Carrier Detect
Threshold
FSK receive data
-51
-40
dBmO
Threshold
QAM/DPSK receive data
-49
-43
dBmO
Hysteresis
All Modes
DPSK
Delay Time
QAM
DPSK
Hold Time
QAM
Answer Tone Detectors
dB
2
-70 dBmO to -6 dBmO
15
20
25
ms
-70 dBmO to -40 dBmO
15
20
25
ms
-70 dBmO to -60 dBmO
25
30
35
ms
-70 dBmO to -40 dBmO
25
33
41
ms
-6 dBmO to -70 dBmO
15
22
28
ms
-40 dBmO to -70 dBmO
10
15
20
ms
-6 dBmO to -70 dBmO
44
60
66
ms
-40 dBmO to -70 dBmO
21
26
31
ms
Callinit Mode
Detect Level
-56
-45
dBmO
Detect Time
For signals from
7
40
ms
Hold Time
-6 to -40 dBmO. 2100 or 2225 Hz
10
50
ms
Detect Time
Demod Mode for signals from
4
26
ms
Hold Time
-6 to -40 dBmO. 2100 or 2225 Hz
11
43
ms
4-49
•
SSI73D2240
V.22bis 2400 Bitls
Modem Device Set
DYNAMIC CHARACTERISTICS AND TIMING (continued)
PARAMETERS
CONDITIONS
Pattern Detectors
DPSK Mode
MIN
NOM
MAX
UNITS
S1 Pattern
Delay Time
For signals from -6 to -40 dBmO,
5
65
ms
Hold Time
Demod Mode
4
45
ms
Delay Time
For signals from -6 to -40 dBmO,
5
45
ms
Hold Time
Demod or call Init Mode
5
45
ms
-21
dBmO
Unscrambled Mark
Receive Level Indicator
Detect On
Valid after Carrier Detect
ms
10
Output Smoothing Filter
Output Impedance
TXApin
200
Output load
TXA pin; FSK Single
300
n
kn
10
Tone out for THO = -50 dB
in 0.3 to 3.4 kHz range
50
pF
Maximum Transmitted
4 kHz, Guard Tones off
-35
dBmO
Energy
10kHz, Guard Tones off
-55
dBmO
12 kHz, Guard Tones off
-65
dBmO
-14
dBm
-9
dBm
1.5
mVrms
±10
Hz
Anti Alias Low Pass Filter
(Frequency kHz)
Out of Band Signal Energy
(Defines Hybrid Trans-
Level at RXA pin with receive
Boost Enabled
Hybrid loss requirements)
Scrambled data at 2400 bitls
in opposite band
Sinusoids out of band
Clock Noise
TXA pin; 153.6 kHz
73K224L
Carrier Offset
Capture Range
Originate or Answer
4-50
±7
5517302240
V.22bis 2400 Bitls
Modem Device Set
DYNAMIC CHARACTERISTICS AND TIMING
PARAMETERS
(continued)
CONDITIONS
MIN
% of frequency originate or
-.02
NOM
MAX
UNITS
+.02
%
+1.18
%
Recovered Clock
Capture Range
answer
Guard Tone Generator
Tone Accuracy
550 Hz
-0.7
1800 Hz
Tone Level
550 Hz
-5.0
-3.0
-2.0
dB
(Below QAM/DPSK
Output)
1800 Hz
-8.0
-6.0
-5.0
dB
Harmonic Distortion
550 Hz
-60
dB
(700 to 2900 Hz)
1800 Hz
-60
dB
Timing (Refer to Timing Diagrams)
CSIAddr. setup before ALE
CS/Addr. Hold after latch
30
ns
TLA
20
ns
TLC
Latch to RD/WR control
40
ns
TAL
ns
TCL
RD/WR Control to Latch
0
TRD
Data out from RD
0
TLL
ALE width
50
TRDF
Data float after READ
25000
160
ns
5
ns
25000
ns
ns
TRW
READ width
0
171
TWW
WRITE width
140
TOW
Data setup before WRITE
150
ns
TWO
Data hold after WRITE
20
ns
1 : Control for setup is the falling edge of RD or WR.
Control for hold is the falling edge of RD or the rising edge of WR.
ALE
k-TI=41
~~-----~-------------
ADO-AD7
cs
--='}'------
t 1
TX3
013
VSS
GNO
C'DO'"-"'-I
3 0· ~
t-j---~S1_;_---t---+~f--~;--7.7--------==-======:J
+5V +5V
01\)1\)
C'D~I\)
MCl45406
+5V
10K <;
itIS
I EC'O
.~V
~
A2~
~C8
ij.II'F
~CIO
I
0.11'F
c::::!ill
~22I'F
m
m~
~
i>ll-
.sv
U80 ~,12
~(~
74HCTi6'
1
TlCO
RXO
..-=---....
~
~
""""""-'
~
~
~
!:mE
MAlEO
TRlEO
FIGURE 5: 7302240 Interconnect
3:
<
a:
>
27
UJ
8
LL
o
a
o
32
432
26
31
30
N/C
29
NlC
AD1
28
RESET
AD2
27
ISET
AD3
26
RXClK
SSI
73K224l-28IH
SSI
AD4
12
13
14
15
16
17
25
RXD
AD5
24
TXD
AD6
23
CS
AD7
22
EXClK
N/C
21
N/C
73K224l-32IH
18
o
o
>
14
15
16
17
18
19
•
20
28·Pin PLCC
32·Pin PLCC
52 51 50 49 48 47 46 45 44 43 42 41
N/C
ADO
N/C
N/C
N/C
RXA
TXA
N/C
N/C
N/C
N/C
GND
551
VDD
73K224l-IG
1.
64 63 62 61
INTB
60 59 58 57 56 55 54 53 52 51 50 49
48
ISET
N/C
46
N/C
RXCLK
N/C
45
N/C
44
N/C
AD1
43
RXD
42
N/C
N/C
N/C
N/C
ClK
31
N/C
N/C
30
RDB
XTAL1
29
WRB
N/C
47
SSI
AD2
73K224-IGT
AD3
41
N/C
40
TXD
AD4
10
39
N/C
AD5
11
38
cs
XTAl2
28
N/C
AD6
12
37
EXCLK
N/C
27
ALE
N/C
13
36
N/C
AD7
14
35
N/C
N/C
15
34
N/C
33
N/C
15 16 17 18 19 20 21
22 23 24 25 26
N/C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
52· Lead PLCC
54· Lead TQFP
4-59
5517302240
V.22bis 2400 Bit/s
Modem Device Set
:.::
en
PIN DIAGRAMS
>
N 18 I~ /I
z §Zoo:o
(TOP VIEW)
6
5
4
3
2
0
0
0
0
Ci
N
0
C')
0
> « « « «
1 44 43 42 41 40
39
AD4
ClK
GND
ITfR
38
ADS
XTL1
XTl2
RXA
CTS
37
AD6
VREF
RST
36
AD7
35
XEN
ADO
RESET
AD1
ISET
AD2
RXClK
VCl
~
TXD
SSI
73D600-IH
34
N/C
RXD
33
ALE
N/C
AD3
RXD
AD4
TXD
RINGD
32
AD5
cs
TXINT
31
PS8
TIl
AD6
EXClK
NVRM
30
MR
AD?
TXClK
NVCE
29
AA
ALE
INT
WR
AD
TXA
18 19 20 21 22 23 24 25 26 27 28
I~ I~
VDD
28-Pin DIP
N
~
X x
o
0
I~ 10: len
10: 10
I~O
~z«
44-Pin PLCC
40-Pin DIP
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
SSI 73D2240-IP
SSI 7302240 Dual In-Line Package
28-pin Plastic DIP
73K224L-IP
40-pin Plastic DIP
73D600A-IP
SSI 73D2240-IH
SSI 7302240 Surface Mount Package
73K224L-281H
28-pin Plastic Leaded Chip Carrier
32-pin Plastic Leaded Chip Carrier
73K224L-321H
44-pin Plastic Leaded Chip Carrier
73D600C-IH
52-Lead Quad Fine Pitch Package
73K224L-IG
64-Lead Thin Quad Flat Pack Package
73K224-IGT
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Copyright Notice:
The software contained within certain components of the Silicon Systems, Inc. SSI 7302240 is copyright protected and may only be used in
conjunction with the SSI 7302240 product as supplied by Silicon Systems, Inc. No license to reproduce this software is granted or implied.
This material may not be reproduced in any form without the express written permission of Silicon Systems, Inc. © Copyright 1989. All rights
reserved.
Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX (714) 573-6914
Protected by the following patents:
(4,777,453) (4,789,995) (4,870,370) (4,847,868) (4,866,739)
©1990 Silicon Systems, Inc.
1292 - rev.
4-60
SSI 7302248/2348
MNP5, V.42bis Datacom
Modem Device Set
I4iM'''iiLUN'I·III[,111
January 1993
DESCRIPTION
FEATURES
The SSI 7302248/2348 Chip Sets consists of two
CMOS integrated circuits which provide the data pump
and protocol functions required to implement a high
performance 2400 bitls modem with error control and
data compression. The 7302248 basic modem function is provided by the SSI 73K224L modem chip and
is compatible with CCITT V.21, V.22, V.22bis and Bell
103 and 212A protocols. The error control functions
are provided by modular software running in the SSI
730246 controller. Modules are available for MNP4,
and V.42. Compression software modules can be can
be added to the controller; MNP5 and V.42bis are
available. Provisions for customization of the Command Set are provided, forming the basis for an International Modem.
•
•
The 7302348 differs from the 7302248 in that it uses
the 73K324L instead ofthe 73K224L forthe data pump.
The 73K324L replaces the Bell 103 300 baud FSK
mode of operation with the CCITT V.231200 baud FSK
mode. The software is also modified to support V.23.
The two products are otherwise identical.
Combines Modem and Protocol Controller
Supports 0 - 300, 1200 and 2400 bit/s with both
Sync and Async Modes
•
•
Modular Software Design Allows Customization
Modem Protocols:
Bell 103, 212A
CCITT V.22, V.22bis
•
Error Control/Compression Protocols
Available: MNP4, MNP5, CCITT V.42, V.42bis
•
Supports Non-volatile Memory to Store User
Configurations and Phone Numbers
•
CMOS Design for Low Power Consumption
•
TQFP packages available for PCMCIA applications
MNP5, V.42bis Datacom
Modem Device Set
0193
4-61
CAUTION: Use handling procedures necessary
for a static sensitive component.
•
SSI 7302248/2348
MNP5, V.42bis Datacom
Modem Device Set
FUNCTIONAL DESCRIPTION
Commands are provided to inform the modem which
action is appropriate.
The SSI 7302248/2348 chip set forms the basis for an
international modem design incorporating the most
advanced error control and compression algorithms.
The set consists of two chips, the SSI 73K224L
(73K324L) modem and the 730246 controller.
Customization of the controller is one of the features of
this chip set; software modules allow the modem
vendor to provide a range of features from a standard
hardware platform.
The 73K224L (73K324L) provides the QAM, PSK and
FSK modulator and demodulator functions, call
progress and handshake tone monitors, test modes
and a tone generator capable of producing OTMF,
answer and CCITT guardtones. This single-chip modem supports the V.22bis, V.22, V.21 and Bell 1031
CCITTV.23/212A operating protocols in both sync and
async modes. Low level functions of the controller
provide for automatic detection of OTE speed, autodial, auto-answer, handshake with fallback and call
progress detection.
The 73D246 controller handles both the low level
modem functions as well as protocol negotiation and
protocol operation. Software modules can be chosen
to provide the desired protocols for product
customization and differentiation. In addition, the "AT'
command set source code will be available for those
desiring to provide unique or country dependent
features.
TEST MODES
The 7302248/2348 chip set has provisions for three
test modes: analog loopback, digital loopback and
remote digitalloopback. Analog loopback allows data
to be sent into the local modem, have it modulated and
then demodulated and returned to the local terminal.
Oigitalloopback requires t/;Je cooperation of the user at
the remote end and allows data to be sent to the remote
modem, demodulated, then remodulated and returned
to the local end. Remote digital loopback allows the
same capability, without the need for a remote operator; signals are sent to the remote modem which
perform the switching task that a remote operator
would have done.
AT COMMAND INTERPRETER
The SSI 7302248/2348 includes an AT Command
Interpreter which is a superset of the Hayes 2400
Smartmodem™ command set. Common application
software will be able to control the modem though this
interpreter. Additional commands have been added to
provide for control of the MNP and CCITT V.42 modes.
NON-VOLATILE MEMORY
A serial NVRAM provides 256 bytes of storage for
configuration information and telephone numbers.
Current hardware provides for a 2K bit memory of
which about 400 bytes are used for setup and
telephone number storage. The remaining 1600 bytes
are avaliable. Memory address space allocated to
Basic capabilities of the modem are those found in the
73K224L (73K324L) Single-Chip Modem and are
listed in the separate 73K224L (73K324L) data sheet.
AUTOMATIC HANDSHAKE
The 7302248/2348 will automatically perform a complete handshake with a called or calling modem and
enter the data transfer mode. Afterthe link between the
two modems has been established, the modems may
remain in the normal data mode or negotiate a link
which has error control and data compression.
4-62
SSI 7302248/2348
MNP5, V.42bis Datacom
Modem Device Set
non-volatile RAM is 8K, so an expansion factor of 4 is
available. Alternatively, the address space could be
decoded for more hardware functionality.
PROTOCOLS
Microcom Networking Protocol (MNP)
MNP4 is a protocol offering error control while MNP5
offers data compression. Data to be transmitted is
broken into blocks of varying sizes, depending on line
conditions, and sent to the remote modem along with
a 16-bit Cyclic Redundancy Check word. If the algorithm used to derive the CRC word at the transmitter
does not produce an identical word when exercised on
the received data, a line error is assumed, and the
block is repeated. Data compression is obtained by
transmitting a short set of characters for a longer
redundant set. At the receiver, the short string is
replaced with the longer string that it represented, and
the data stream is returned to its original state.
CCITT V.42 and V.42bis
The CCIIT has ratified a set of protocols which operate
in a mannersimilarto MN P. MNP4corresponds to V.42
while MNP5 corresponds with V.42bis. Greater efficiency is offered, but the tradeoff is a larger memory
space requirement. MNP5 requires an 8K buffer, while
V.42bis requires 32K. Data files which show compression ratios approaching 2:1 with MNP5 may show
ratios of nearly 4:1 with V.42bis.
4-63
ADDITIONAL INFORMATION
The Silicon Systems Protocol Design Manual defines
the AT commands. Please contact your local Silicon
Systems sales office or Silicon Systems headquarters
in Tustin for a copy of the SSi Protocol Design Manual.
•
SSI 7302248/2348
MNP5, V.42bis Datacom
Modem Device Set
AT COMMAND SUMMARY
Command
Description
AT
command prefix - precedes command line
Command
X4
Description
enable features represented by resun codes 0-7, 10-12
carriage return character - terminates command line
YO
disable long space disconnect
A
go into answer mode; attempt to go to on-line state
Y1
enable long space disconnect
AI
re-execute previous command line;
not preceded by AT nor followed by
ZO
reset modem
&CO
assume data carrier always present
BO
select CCITT V.22 standard for 1200 bitls communication
S1
select Sell 212A standard for 1200 bitls communication
D
dial number that follows; attempt to go to on-line state, originate
mode
DS=n
dial stored number in location "n° (0-3)
EO
Disable character echo in command state
&C1
track presence of data carrier
&00
ignore DTR signal
&D1
assume command state when an on-to-off
transition of DTR occurs
&D2
hang up and assume command state when an on-to-off
transition of DTR occurs
E1
Enable character echo in command state
&D3
reset when an on-to-off transition of DTR occurs
HO
go on hook (hang up)
&F
recall factory settings as active configuration
Hl
go off hook; operate auxiliary relay
&GO
no guard tone
10
request product indentification code
&G 1
550 Hz guard tone
11
perform checksum on firmware ROM; return checksum
&G2
1800 Hz guard tone
12
perform checksum on firmware ROM;
returns OK or ERROR result codes
&K
flow control method
LO or L1 low speaker volume
L2
medium speaker volume
L3
high speaker volume
MO
speaker off
M1
speaker on until carrier detected
M2
speaker always on
M3
speaker on until carrier detected, except during dialing
00
go to on-line state
01
go to on-line state and initiate equalizer retrain at 2400 bitls
00
modem returns result codes
01
modem does not return result codes
Sr
set pointer to register "r"
Sr=n
set register "r" to value "n°
Sr?
display value stored in register "r"
VO
display result codes in numeric form
V1
display result codes In verbose form (as words)
WO
negotiation progress result codes not returned
Wl
negotiation progress result codes returned
XO
enable features represented by result codes 0-4
Xl
enable features represented by result codes 0-5, 10-12
X2
enable features represented by result codes 0-6,10-12
X3
enable features represented by result codes 0-5, ?, 10-12
4-64
&MO
asynchronous mode
&M1
synchronous mode 1
&M2
synchronous mode 2
&M3
synchronous mode 3
&05
error control mode
&06
automatic speed buffering (ASB)
&TO
terminate test in progress
&T1
initiate local analog loopback
&T3
initiate local digitalloopback
&T4
grant request from remote modem for RDL
&T5
deny request from remote modem for RDL
&T6
initiate remote digitalloopback
&T?
initiate remote digitalloopback with self test
&T8
initiate local analog loopback with self test
&V
view active configuration, user profiles, and stored numbers
&WO
save storable parameters of active configuration
&XO
modem provides transmit clock signal
&Xl
data terminal provides transmit clock signal
&X2
receive carrier provides transmit clock Signal
&Zn=x
store phone number "x" in location "n° (0-3)
551 7302248/2348
MNP5, V.42bis Datacom
Modem Device Set
Dial string arguments:
, = delay
; = return to command
@ = silent answer
s = dial stored number
! = flash
W = wait for tone
R=reverse mode
If the NovRAM has not been initialized it may be necessary to Power down/Power up and type AT&F&W
to properly initialize modem state.
TABLE 1: Result Codes
Xn
VERBOSEITERSE RESULT CODES
XO
OKlO, CONN ECT/1 , RINGl2, NO CARRIER/3, ERROR/4
X1
All functions of XO + CONNECT (RATE)/1
X2
All functions of X1 + NO DIAL TONE/6
X3
All functions of X1 + BUSYI7
X4
All functions of X3 + NO DIAL TONE/6, NO ANSWERl8
= 300,5 = 1200,10 = 2400
TABLE 2: S Registers Supported
Sn
FUNCTION
UNITS
S01
Answer on ring
No. of rings on which to answer
DEFAULT
0002
S1
Ring counter
No. of rings accumulated
000
S2
Escape code
ASCII CHR Decimal 0-127
043
S3
Carriage return
ASCII CHR Decimal 0-127
013
S4
Line feed
ASCII CHR Decimal 0-127
010
S5
Back space
ASCIICHR
008
S6
Wait for dial tone
Seconds
002
S7
Wait for carrier
Seconds
030
S8
Pause time
Seconds
002
89
Carrier valid
100 milliseconds (0.1 sec)
006
S10
Carrier drop out
100 milliseconds (0.1 sec)
014
S11
DTMF tone duration
1 millisecond (0.001 sec)
070
812
Escape guard time
20 milliseconds (0.05 sec)
S13
Unused
*S141
050
N/A
Bit mapped register
Decimal 0-255
Stored in NVRAM with &W command.
Modem will not answer until value is changed to 1 or greater.
4-65
170
SSI 7302248/2348
MNP5, V.42bis Datacom
Modem Device Set
TABLE 2: S Registers Supponed (Continued)
NUMBER
FUNCTION
UNITS
N/A
815
Unused
816
Test register
Decimal #
000
817
SSi Special test register
Decimal 0-255
096
818
Test timer
Decimal 0-255
000
S19
Unused
S20
Unused
N/A
N/A
*S21 1
Bitmapped register
Decimal 0-255
*S22
1
Bitmapped register
Decimal 0-255
118
*S231
Bitmapped register
Decimal 0-255
007
S24
000
N/A
Unused
1
DTR delay
10 milliseconds (0.01 sec)
005
S261
CTS delay
10 milliseconds (0.01 sec)
001
Bitmapped register
Decimal 0-255
064
S25
*S27
1
S36
Negotiation failure treatment
S37
Desired modem line speed
S38
Hang-up timeout
20
S39
Current flow control setting
3
S43
Current DCE speed
0
5
Decimal 0-9
000
S46
Protocol/Compression selection
2
S48
Feature negotiation action
7
S49
ASB Buffer low limit
1-249
2-250
S50
ASB Buffer high limit
S82
Break select register
S95
Extended result code bit map
8
16
128
0
* The bitmapped register functions are equivalent to normal "AT" command modem registers.
1
DEFAULT
Stored in NVRAM with & W command
4-66
SSI 7302248/2348
MNP5, V.42bis Datacom
Modem Device Set
PACKAGE PIN DESIGNATIONS
(Top View)
N/C
N/C
NlC
N/C
NlC
NlC
N/C
NlC
N/C
NlC
Al
USR31
A2
USR30
A3
USR40
A4
USR41
A5
A6
USR42
A7
USR43
USR44
A8
USR45
A9
Ala
USR46
66
USR47
TEST
All
16
65
A12
17
64
VPD
A13
18
63
USR20
A14
19
62
USR21
USR22
A15
20
61
'f5S"rn
21
60
USR23
RESET
22
59
USR24
VND
23
58
USR25
OSCOUT
24
57
USR26
OSCIN
25
56
55
USR27
54
NlC
53
52
NlC
51
Nle
NlC
NlC
N/C
NlC
N/C
551730246
Controller
100-Lead QFP
4-67
NlC
NlC
•
SSI 73D2248/2348
MNP5, V.42bis Datacom
Modem Device Set
PACKAGE PIN DESIGNATIONS
(Top View)
NlC
NlC
NlC
NlC
NlC
N/C
A1
USR31
A2.
USR30
A3
USR40
A4
USR41
A5
USR42
AS
USR43
A7
USR44
USR45
A8
A9
USR46
A10
USR47
A11
TEST
A12
VPP
A13
USR20
A14
USR21
A15
PSEN
USR22
RESET
USR24
VND
USR25
OSCOUT
USR26
USR23
OSCIN
USR27
NlC
NlC
NlC
NlC
SSI730246
Controller
100-Lead TQFP
4-68
SSI 7302248/2348
MNP5, V.42bis Datacom
Modem Device Set
~
Q Q \;<
Q \;<
z z
z
~
6463 62 61
~
:5
(,)
~
Cl
z
~
Q
z
(,)
Z
x<
f-
UJ
UUJ
en
a: Q UJ
a: Z > z a:
(,)
60 59 58 57 56 55 54 53 52
51
50 49
N/C
ADO
ISET
N/C
46
N/C
N/C
RXClK
N/C
NlC
N/C
AD1
43
RXD
N/C
42
NlC
AD2
41
NlC
AD3
40
TXD
AD4
39
N/C
AD5
38
cs
AD6
37
EXClK
N/C
36
N/C
AD7
35
NlC
N/C
34
N/C
N/C
33
N/C
•
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Q Q
z
Z
UJ
...J
<
~ ~
Q
Z
~ ~
Cl
Q
~ Z
~ ~ ~
~
...J
(,)
Q Q
Z
Z
X
f-
SSI73K224L
Single Chip Modem
64-Lead TQFP
~
~
...J
(,)
f-
Cl
UJ
x Q Q Cl
x
sa zQ a:x a:
z z f-
52 51
Q
Z
~ ~
...J
(,)
x
UJ
~
...J
(,)
Q x
Z
f-
50 49 48 47 46 45
N/C
m
N/C
N/C
RXA
TXA
NlC
N/C
NlC
N/C
VDD
GND
N/C
ClK
N/C
Nle
RD
WR
N/C
XTl2
ALE
N/C
15 16 17 18 19 20 21
8<
Q
Z
~ 0<
N
Cl
<
t')
..,.
Cl
Cl
<
<
III
0
(continued)
N/C
ClK
GND
XTL1
RXA
VREF
RESET
ISET
RXClK
XTl2
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
18 19
20
ALE
~
::.::
...J
WR
~
Fill
~
.....
0
SSI73K224L
Single Chip Modem
32-Pin PLCC
0
!i
&2
X
u.
~
~
(!)
II:
-<
x
w
II:
>
1
28
27
26
0
25
RESE
RXD
TXD
24
ISET
23
RXC~,
~
22
RXD
0
EXClK
21
TXD
TXCLK
lNf
20
~
19
EXCL~
TXA
VDD
SSI73K224L
Single Chip Modem
28-Pin DIP
14
15
16
17
18
~ ~ ~
c
c
>
-<
~
~
d~
12
13
SSI73K224L
Single Chip Modem
28-Pin PLCC
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Copyright Notice:
The software contained within certain components of the SSI 7302248 is copyright protected and may only be used in conjunction with the
SSI 7302248 product as supplied by Silicon Systems. No license to reproduce this software is granted or implied. This material may not be
reproduced in any form without the express written permission of Silicon Systems, Inc. © Copyright 1992. All rights reserved.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1992 Silicon Systems, Inc.
Protected by the following patents: (4,777,453) (4,847,868)
(4,789,995) (4,870,370) (4,866,739)
0193
4-70
5S17302910
Microcontroller
'_'MiUNme"IIIIIII,'IDecember 1993
DESCRIPTION
FEATURES
8052 Compatible Instruction set
22 MHz Operation
Operates at 3.3V and 5V
HOLC Support logic (Packetizer, 16 and 32
CRC, zero 10)
24 pins for user programmable I/O ports
8 pins programmable chip select logic for
memory mapped peripheral eliminating glue
logic
3 external interrupt sources (programmable
polarity)
16 dedicated latched address pins
The Silicon Systems 7302910 high performance
microcontroller is based on the industry standard 8-bit
8052 implemented in Silicon Systems' advanced
submicron CMOS process. The processor has the
same attributes of the 8052 including Instruction cycle
time, UART, timers, interrupts, 256 bytes of on-chip
RAM and programmable I/O. The architecture has
been optimized for low power portable modem or
communication applications by integrating unique
features with the core CPU.
The main feature is a user friendly HDLC packetizer,
accessed through the special function registers. It has
a serial I/O, hardware support for 16- and 32-bit CRC,
zero insert/delete control, a dedicated interrupt and a
clear channel mode for by-passing the packetizer.
Multiplexed data/address bus
Instruction cycle time Identical to 8052
Buffered oscillator (or OSC/2) output pin
1.8432 MHz UART clock available
Bank select circuitry to support up to 128K of
external program memory
1~O-Lead TQFP package available for PCMCIA
applications
Also available in 100-Lead QFP package
Other features include additional user programmable
I/O with programmable bank select and chip select
logic, designed to eliminate board level glue logic. It
also includes two general purpose input ports with
programmable wakeup capability.
For devices that require non-multiplexed address and
data buses, eight latched outputs forthe low byte of the
address are available.
(continued)
BLOCK DIAGRAM
r-----~ JISm
. . - -_ _- . A L E
1293- rev.
4-71
•
5517302910
Microcontroller
DESCRIPTION
DEVELOPER'S NOTE:
(continued)
The 73D2910 has two extra interrupt sources, an
external interrupt and a HOLC interrupt. The HOLC
interrupt has two registers associated with it: the H OLC
Interrupt Register which is used to determine the
source of the interrupt, and the HOLC Interrupt Enable
Register that enables the source of the interrupt.
The state of the external interrupts can be read through
a register allowing the interrupt pins to be used as
inputs. The interrupt pins INTO and INT1 can be either
negative edge, positive edge or level triggered. INT2
pin is always edge triggered.
Two buffered clock outputs have been added to
support peripheral functions such as UARTs, modems
and other clocked devices. The main internal
processor clock frequency can be divided by 2 for
power conservation in functional modes that only
require half the clock speed.
Additional internal special function registers are used
for firmware control over the HOLC Packetizer, the
clocks and the programmable I/O ports.
To accommodate processor peripherals when
operating at 22 MHz the processor's timing has been
altered somewhat to allow more address setup time for
slower peripheral program ROM and memory mapped
peripherals. This can offer the system designers an
advantage when using higher (22 MHz) oscillator
frequency.
For low power applications the 730291 0 operates from
3 to 5 volts at 22 MHz and supports two power
conservation modes: Idle and Power-down. In the
Power-down state the total current consumption is less
than 1 ~ at room temperature.
This device is offered in small form factor 1~O-lead
TOFP packages for PCMCIA applications and
1~O-lead aFP packages.
4-72
The 7302910 is also available in a 100-pin PGA
package for system developers. The PGA package
is more convenient and reliable for development
emulation systems than the other package styles.
Emulation systems for the 7302910 are available
through Signum Systems, 171 E. Thousand Oaks
Blvd., #202, Thousand Oaks, CA 91360
(805) 371-4608.
8052 REFERENCE
This Document will describe the features unique to the
7302910. Please refer to an 8052 Programmer's
Guide, Architectural Overview and Hardware
Description for details on the instruction set, timers,
UART, interrupt control, and memory structure.
5517302910
Microcontroller
PACKAGE PIN DESIGNATIONS
(Top View)
NlC
NlC
NlC
NlC
NlC
Al
A2
A3
A4
AS
A6
A7
1.8
A9
Al0
All
A12
A13
A14
A15
1'Srn
RESET
VND
OSCOUT
OSCIN
NlC
NlC
CLK20UT
NlC
NlC
g~S~~~~~~~~i~~~~~~~~
1M
79
78
77
76
75
74
73
72
10
71
70
11
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
58
23
24
57
56
25
26
55
27
54
28
53
52
29
30
51
N/C
N/C
USRSO
N/C
USRSl
USR31
USR30
USR40
USR41
USR42
USR43
USR44
USR45
USR46
USR47
I
VND
VPO
USR20
USR21
USR22
USR23
USR24
USR25
USR26
USR27
N/C
N/C
N/C
N/C
N/C
100-Lead QFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for final
design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1293 - rev.
4-73
©1993 Silicon Systems, Inc.
Notes:
4-74
SSI 73D2950/2950T
V.29N.27terN.22bisN.22JV.21N.23, Bell 212A1103, MNP2-5,
V.42N.42bis, Low Power FAX/Data Modem Chip Set
PM'iiiMt,'iillll,·jli
December 1993
DESCRIPTION
FEATURES
The SSI 73D2950 modem chip set is capable of both
data and facsimile transmission and reception. It is a
high performance, low voltage, low power, and small
form factor design intended for embedded applications
and battery operation. It may be implemented directly on
the motherboard of a portable computer.
Facsimile Speeds
The SSI 73D2950 chip set consists of three CMOS
integrated circuits which provide all the "Control,"
"Pump" and "Hybrid" functions required to implement an
intelligent V.22bis data & V.29 facsimile modem. The
three chips are the SSI 7302910 Controller (2910),
SSI 73D2920 Digital Signal Processor (2920) and the
SSI 73D2930 Analog Front End Line Interface Chip
(AFELlC) (2930).
V.29 - 9600, 7200 bltls, (send & receive)
V.27ter - 4800,2400 bitls, (send & receive)
V.21 ch2 - 300 bltls, (send & receive)
Facsimile Protocols
EIA-578 Class 1
Industry Class 2
Data Speeds
V.22bls - 2400 bltls
V.22, Bell 212 - 1200 bltls,
V.22 half speed - 600 bltls
V.21, Bell 103 - 300 bltls
V.23, 1200 bltls, 75 bltls
I
Data Protocols
V.42 I MNP2-4 error control
V.42bis I MNP-5 data compression
73D2950T
Truespeech™ voice compression
High compressionlHigh Audio quality
Scalable sampling rates
Low computation power
(continued)
BLOCK DIAGRAM
HOOK
------1
1
1
1
L
I---OC TIP
1 - - - - 0 RING
- - - - HIGH VOLTAGE ISOLATION
CAUTION: Use handling procedures necessary
for a static sensitive component.
1293
4-75
551 73D2950/2950T
V.29/V.27terN.22bis/V.22IV.21N.23, 8e1l212A11 03, MNP2-5,
V.42N.42bis, Low Power FAX/Data Modem Chip Set
To complete the 7302950 chip set core, a 32Kx8
SRAM, 1Mbit ROM and (optionally) a serial E2PROM
are added.
FEATURES (continued)
Other
Low chip count, 3 ICs + ROM I RAM
The 7302950 chip set supports the following:
High quality transformerless DAA
A serial EEPROM (4k bit x 1) for configuration and
phone number storage.
Partially line powered
Low power, less than 150 mW from host
Automatic power down when not active
Software drivers for LED support in the 7302910
for both Fax and Data modes.
Serial EEPROM support for configuration and
telephone number storage
"Dumb" mode with an optional hardware switch. If
enabled, Facsimile mode is disabled.
Designed for 3.3 or 5-Volt systems
The 7302920 provides a CMOS pulse width modulated
signal to be used for monitoring the analog transmission
and reception (speaker output). This output may be
used directly to drive a high impedance speaker or low
pass filtered for input to a separate speaker driver.
FUNCTIONAL DESCRIPTION
The 7302950 consists ofthree CMOS integrated circuits
which provide all the "Control," "Pump" and "Hybrid"
functions required to implement an intelligent V.22bis
data & V.29 facsimile. The three chips are the SSI
7302910 microcontroller (2910) ,SS173D2920 Digital
Signal Processor (2920) and the SSI 7302930 Line
Interface Chip (2930).
The 7302950 is designed to be used as a stand alone
or "box" modem communicating via a serial interface.
The DCE to DTE I/O is a CMOS level inverted EIA-2321
V.24 compatible interface. The user may add an EIA232/V.24 level driver, a UART or PCMCIA interface.
The following EIA-232 signals are supported:
The 7302950 is designed for a single +3.3V or 5V
±10% supply and for minimum power consumption
«150 mW@3.3v2910+ROM/RAMand2920). The
7302950 supports automatic power down (Idle) mode
via an internal watchdog timer. The 7302950 chip set
will also accept a request to power down( <10 J,JA) from
the DTE via hardware control.
The 7302950 supports a OTE interface with "Autobaud"
capability from 300 to 19.2K bits per second. The OTEI
DCE interface rate must be equal to or greater than the
desired modulation rate. All data and Facsimile modes
supports a RAM data buffer. The serial interface supports
in-band (XON/XOFF) orout-ot-band (CTSIRTS) flow control.
NAME
CIRCUIT
DESCRIPTION
SO
103
Data to transmit
RD
104
Data received
RTS
105
DTE ready to transmit data (to DCE)
CTS
106
DCE ready to transmit data (to DTE)
DSR
107
Data set ready, modem ready to operate (TO DTE)
DTR
108
Data terminal ready (to DCE)
RLSD
109
Data carrier detected (to DTE)
RATE
112
Indicates to DTE rate selected by DCE
RI
125
Ring indicate to DTE
TC
114
Transmit signal element timing to DTE
RC
115
Receive signal element timing to DTE
EC
113
Transmit signal element timing to DCE
4-76
SSI 73D2950/2950T
V.29N.27terN.22bisN.22IV.21N.23, Bell 212A11 03, MNP2-5,
V.421V.42bis, Low Power FAX/Data Modem Chip Set
LINE/HYBRID INTERFACE
The SSI 73D2930 AFELIC derives its power from the
DC voltage supplied by the PSTN. It contains the
hybrid, receive ADC, and transmit DAC and interfaces
to the DSP and PSTN network. Among the functions
performed by this circuit are ring detect and the AC and
DC impedance characteristics.
The 73D2930 AFELIC requires a few external
components. See the 73D2950 Design Manual for
detailed information.
QAM MODULATOR /DEMODULATOR
The 73D2950 encodes incoming data into quad bits
represented by 16 possible Signal points with specific
phase and amplitude levels. The base band signal is
then filtered to reduce inter-symbol interference on the
band limited telephone network. The modulator
transmits this encoded data using either a 1200 Hz
(Originate mode) or 2400 Hz (Answer mode) carrier.
The demodulator, although more complex, essentially
reverses this procedure while also recovering the data
timing from the incoming signal. Adaptive equalization
corrects for varying line conditions by automatically
changing filter parameters to compensate for line
characteristics.
DPSK MODULATOR/DEMODULATOR
The 73D2950 modulates a serial bit stream into di-bit
pairs that are represented by four possible phase shifts
as prescribed by the Bell 212A1V.22 standards. The
~ase-band signal is then filtered to reduce inter-symbol
Interference on the band limited 2-wire PSTN line.
Transmission occurs on either a 1200 Hz (Originate
mode) or2400 Hz carrier (Answermode). Demodulation
is the reverse of the modulation process, with the
incoming analog signal eventually decoded into di-bits
and converted back to a serial bit stream. The
demodu lator also recovers the data timing which was
encoded into the analog signal during modulation.
Adaptive equalization is also used in DPSK modes for
optimum operation with varying line conditions.
FSK MODULATOR/DEMODULATOR
mode uses 980 and 1180 Hz (originate, mark and
space) or 1650 and 1850 Hz (answer, mark and space).
V.23 mode uses 1300 & 2100 for the main channel
mark/space tones & 390/450 Hz for the back channel.
Demodulation involves detecting the received
frequencies and decoding them into the appropriate
binary value. The rate converter and scramblerl
descrambler are automatically bypassed in the FSK
modes.
PASSBAND FILTERS AND EQUALIZERS
High and low band filter functions are performed in the
73D2920 and are included to shape the amplitude and
phase response ofthe transmit and receive signals and
provide compromise delay equalization and rejection
of out-of-band signals. Amplitude and phase
equalization are necessary to compensate for distortion
of the transmission line and to reduce inter-symbol
interference in the band limited receive signal. The
transmit signal filtering corresponds to the appropriate
CCITT defined frequency response characteristic for
the mode being used.
ASYNCHRONOUS DPSK/QAM MODES
The asynchronous mode is used for communication
with asynchronous terminals which may communicate
at 600,1200, or 2400 biVs +1 %, -2.5% while the
73D2920's output is limited to the CCITT and Bell
specified modulation bit rate of ±.01 % in DPSK and
QAM modes. When connected to asynchronous modes
the serial data on the TXD input is passed through a
rate converter which inserts or deletes stop bits in the
serial bit stream in order to output a signal to the
modulatorthatisthe nominal bit rate±.01%. This signal
is then routed to a data scrambler and into the modu lator
where quad-biVdi-bit encoding results in the output
signal. Both the rate converter and scrambler can be
bypassed for synchronous operation or handshaking
as required. Received data is processed in a similar
fashion except that the rate converter now acts to
reinsert any deleted stop bits and output data to the
terminal.
An incoming break signal (lOW through two characters)
will be passed through without incorrectly inserting a
stop bit.
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. The Bell 103 standard
frequencies of 1270 and 1070 Hz (originate mark and
space) and 2225 and 2025 Hz (answer mark and
space) are used when this mode is selected. V.21
Both the SYNC/ASYNC rate converter and the data
descrambler are automatically bypassed in the FSK
modes.
4-77
4
SSI 73D2950/2950T
V.29N.27terN.22bisN.22IV.21N.23, Bell 212A11 03, MNP2-5,
V.421V.42bis, Low Power FAX/Data Modem Chip Set
FUNCTIONAL DESCRIPTION
RECEIVER TIMING
(continued)
The timing recovery circuit can adjust to a ± 0.02 %
frequency offset from the local timing source.
SYNCHRONOUS MODE
Synchronous operation is available in the phase
encoded modes. Operation is similar to that of the
asynchronous mode except that data is synchronized
to a provided clock and no variation in the nominal data
transfer rate is allowable. Serial input data appearing at
TXO must be valid on the rising edge of TXCLK. (In
FSK mode the clock runs at 16 times the data rate.)
DTMF GENERATION
OTMF tones are generated by using Hayes AT dialing
commands. Register S11 controls the duration of the
OTMFtones and spacing between tones. Smart dialing
functions are controlled by the Xn command and
modifiers.
TXCLK is an internally generated bit rate clock in
internal synchronous mode. In slave synchronous
mode, the transmit timing is locked to the receive
clock. A pin is also provided to allow synchronization to
an externally provided clock in external synchronous
mode.
CLASS 1 AND CLASS 2 FAX MODES
The SSI7302950 is capable of synchronous 9600 and
7200 (V.29), and 4800 and 2400 (V.27ter) bitls half
duplex operation with error detection.
The modem satisfies the telecommunications
requirements specified in CCITT recommendations
V.29, V.27 ter, V.21 Channel 2, T.3, and T.4, and the
binary signaling requirements of T.30. The 7302950
can operate at speeds of 9600,7200, 4800,2400, and
300 bitls. The 7302950 also performs HOLC framing!
deframing according to T.30 at speeds of 9600,7200,
4800,2400, and 300 bit/s.
Receive data atthe RXO pin is clocked out on the falling
edge of RXCLK. The async/sync converter is bypassed
when synchronous mode is selected.
FSK DATA RATES
In FSK modes bits are transmitted and received as they
arrive from the OTE and analog interfaces. No rate
conversion or synchronization is performed. Nominally
Bell 103 & V.21 modulation are 300 biVs. For V.23 the
main channel is 1200 bitls and the back channel is 75
bit/s
The 7302950 is intended for use in Group 3 and Group
2 facsimile applications. Both Class 1 and Class 2
operation are supported by using the +FCLASS=n
(n=1 or 2) command.
SCRAMBLER/DESCRAMBLER
V.24/EIA·232 INTERFACE
The modem incorporates a self-synchronizing
scrambler/descrambler in accordance with CCITTV .221
V.22bis, Bell 212, V.29 or V.27 recommendations,
depending on the selected configuration.
Seven pins provide timing, data, and control signals for
implementing a CCITT recommendation V.24
compatible serial interface. These signals are TTL
compatible but for driving longer cables, these signals
can be easily converted to EIAlRS-232-C voltage levels.
The control signals are active low (inverted) from those
found on EIAlRS-232-C allowing standard inverting
buffers to be used. RXO and TXO are active high and
also inverted from those on EIAlRS-232-C interfaces.
RECEIVE LEVEL
The receiver satisfies V.21, V.221V.22bis, V.29 and
V .27 performance requirements for received line Signal
levels from -9 dBm to -43 dBm. The received line signal
level is measured between TIP and RING at the
telephone network interface.
Transmit Data (SO)
CARRIER RECOVERY
The modem obtains serial data to be sent from the local
OTE on the Send Oata (SO) input.
The carrier recovery circu it can track a ±7 Hz frequency
offset in the received carrier with less than a 0.2 dBm
degradation in bit error rate (BER).
Received Data (RD)
The modem presents received serial data to the local
OTE on the Received Oata (RXO) output.Received
Oata (RXO) is clamped to a constant mark whenever
the Received Line Signal Oetector (RLSO) is off.
4-78
SSI 7302950/29501
V.29/V.27terN.22bis/V.22IV.21N.23, Bell 212A11 03, MNP2-5,
V.421V.42bis, Low Power FAX/Data Modem Chip Set
Request To Send (RTS)
FIRMWARE DESCRIPTION
Request to Send (RTS) the modem to transmit data on
TXD when CTS becomes active.
Command and configuration of the modem is provided
by a Hayes™ compatible "AT" command interpreter.
The command section is divided into four parts:
1) commands valid independent of the value of
"FCLASS"; 2) commands valid in Data mode
(FCLASS=O); 3) commands valid in Class 1 Facsimile
mode (FCLASS=1); 4) commands valid in Class 2
Facsimile mode (FCLASS=2).
Clear To Send (CTS)
Clearto Send (CTS) indicates to the local DTE that the
modem will transmit any data present on TXD.
Received Line Signal Detector (RLSD)
For V.29 and V .27, Received Line Signal Detector
(RLSD) goes active atthe end ofthetraining sequence.
REQUIREMENTS
The modem always powers up in Data mode
(+FCLASS=O). General purpose commands, such as
those listed in sections are enabled in both
Data and Fax modes. Their respective values are
consistent independent ofthe state of u+FCLASS."The
Data modem code fits in a 64K x 8 ROM. Facsimile,
V.25bis and user command extensions require a 128K
x8 ROM.
GENERAL" AT" COMMANDS
The following commands are supported by the modem
in all modes (FCLASS=O,1 ,2):
4-79
A
Answer call
0
Dial (originate)
E
Echo
H
Hook control
I
10
L
Speaker volume
M
Speaker control
Q
Result code display
Sn
SFR control, see below
V
Verbose mode
X
Result code/CPO control
Zn
Recall stored profile n
•
•
551 73D2950/2950T
V.29N.27terN.22bisN.22IV.21 N.23, 8e1l212A11 03, MNP2-5,
V.42JV.42bis, Low Power FAX/Data Modem Chip Set
GENERAL "AT" COMMANDS (continued)
Data Modem
Dial Modifiers
The following commands are unique to the Data modem
(FCLASS=O)
Hook flash
@
Pause
B
Communications standard
Silent answer
C
Carrier control
Return to command mode
P
Pulse dial
R
Reverse dial
S=n
Dial stored number n
T
Tone dial
W
Wait for dial tone
N
Modem handshake speed
o
Go online
W
Negotiation progress message control
Y
Long space disconnect
EXTENDED "AT" COMMANDS
Extended " AT" Commands
&C
DCD options
DTR options
Guard tone
&F
Load factory defaults
&0
&J
Aux relay options
&G
&V
View profile
&K
Flow control enable
Leased line control
Store configuration in EEPROM
&L
&Yn
Power on configuration control
&M
Synclasync options
&Zn
Store phone number in EEPROM
&0
Communications mode
&R
RTS/CTS options
&S
Data set ready options
&Wn
Special Function Registers
Register
Description
0
Ring to answer on
2
4
5
Character
Ring counter
Character
Character
6
Blind dial wait time
8
"," wait time
11
14
15
21
22
23
27
30
DTMF dialing speed
Bit mapped options
Command timeout
Bit mapped options
Bit mapped options
Bit mapped options
Bit mapped options
Activity timer
4-80
&Tn
Test mode options
&Xn
Select sync clock source
&Yn
Power on configuration control
SSI 73D2950/2950T
V.29/V.27ter/V.22bisN.22/V.21N.23, Bell 212A11 03, MNP2-5,
V.421V.42bis, Low Power FAX/Data Modem Chip Set
Result Codes
DATA MODEM SPECIAL FUNCTION REGISTERS
The Data modem supports the following result codes.
Register
Description
Result Codes
2
Escape character
Verbose Result
7
Carrier wait time
9
Carrier recovery time
0
OK
1
CONNECT
2
RING
3
NO CARRIER
4
ERROR
5
CONNECT 1200
6
NO DIALTONE
7
BUSY
8
NO ANSWER
9
CONNECT 0600
10
CONNECT 2400
11
CONNECT 4800
12
CONNECT 9600
14
CONNECT 19200
40
CARRIER 300
46
CARRIER 120 0
47
CARRIER 2400
66
COMPRESSION: CLASS 5
67
COMPRESSION: V.42bis
69
COMPRESSION: NONE
70
PROTOCOL: NONE
77
PROTOCOL: LAP-M
80
PROTOCOL: ALT
4-81
10
Carrier loss time
12
Guard time
16
Test options
18
Test timer
20
HDLC address
25
DTR timer
26
RTS/CTS delay
36
Negotiation fallback control
37
DCE line speed control
39
Current flow control method
43
Current DCE speed
46
Feature negotiation action
47
Current compression status
48
Feature negotiation status
70
Max number of
retransmissions
82
Break signaling method
86
Connect failure cause code
95
Extended result code bit map
•
SSI 73D2950/2950T
V.29N.27terN.22bisN.221V.21N.23, Bell 212A1103, MNP2-5,
V.421V.42bis, low Power FAX/Data Modem Chip Set
CRS
V.25Bis COMMANDS (OPTIONAL)
Seven (7) V.25bis commands are supported in the
7302950. Futu re revisions will allow for protocol, speed
buffering and blacklisting. Commands are enabled via
a switch connected to one of the 7302910 user port
pins which is read on power up. The following is a list
of the basic V.25bis commands supported in the
7302950 firmware:
SET
This command dials using one of the stored
phone numbers stored with the PRN command.
If there is no number stored in the slot then the
modem will respond with a CFINS indication.
DIC
Auto baud to current DTE line speed.
Same as AT command.
CIC
Connect Incoming Call. Same as ATA
command. Answers the phone regardless of
the ring count set by the CNA command.
CRN
Call Request with Number.Parameters:
0-9 * # T P = &: /
Call Request with Stored number.
Parameters: 1-20
Disregard Incoming Call.
Parameters: None
This command can be issued anytime during
ringing but prior to the modem answering the
call. This command only affects the current
call. This condition may be canceled by the
CIC command.
PRN
Store / Delete Number.
Parameters: 1-20
This command stores the 10 number in one of
20 slots.
The V.25bis dial string is supplied with this
command. This command functions the same
as the ATD command. Valid dial string
parameters are shown in Table 1.
RLN
Request List of Stored Numbers.
Parameters: 1-20
This command requests either a single phone
number if a parameter is specified or all 20
phone numbers stored with the PRN command
if no number specified.
TABLE 1: Valid Dial String Parameters
0-9*#
Dial Digits
These are the digits to be dialed.
T
DTMF Dialing
When this command is encountered in a dial string the subsequent digits will
be dialed in DTMF mode.
P
PULSE Dialing
When this command is encountered in a dial string the subsequent digits will
be dialed in Pulse mode.
<
Short Pause
When this command is encountered in a dial string the firmware delays further
action by the time specified in S8 (Default of 2 seconds).
=
Long Pause
When this command is encountered in a dial string the firmware delays further
action by double the time specified in S8. NOTE: See < modifier.
Wait for dial tone
When this command is encountered in a dial string the mode will wait for the
detection of dialtone. The modem will wait forthe duration of the time specified
byS7.
/
&
Comment.
Flash
All characters in a dial string after this command will be ignored.
This is the same as the Hayes! flash character.
4-82
551 73D2950/2950T
V.29/V.27ter/V.22bis/V.22IV.21N.23, Bell 212A11 03, MNP2-5,
V.421V.42bis, Low Power FAX/Data Modem Chip Set
FACSIMILE MODEM
TIA-578 Class 1 Facsimile commands
"AT" Commands Supported:
Modulator commands:
Additional Dial Modifiers:
All of the following commands except +FTS and+FRS
must be the last command on the line.
Hook flash
Pause
+FTS=