1994_Silicon_Systems_Storage_Products 1994 Silicon Systems Storage Products
User Manual: 1994_Silicon_Systems_Storage_Products
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FIRST CLASS
CAR-RT SORT
..
···
·
·
·
·
·
·
..............•..•.................. ,·..
·
NOTICE
All products listed herein and subsequently sold by Silicon Systems, Inc. are covered by the
warranty, limitation of liability and patent indemnification provisions reflected in the Silicon
Systems Order Acknowledgement Form only. Silicon Systems, Inc. makes no warranty,
express or implied, statutory or by description regarding the information set forth herein and/
or freedom from patent infringement. Silicon Systems, Inc. reseNes the right to discontinue
production, change specifications and prices at any time and without notice.
Applications requiring mechanical and electrical parameters outside of the published
specifications are not recommended without additional review and acceptance by Silicon
Systems, Inc. Silicon Systems, Inc. further assumes no responsibility for the use of any
integrated circuit technology other than integrated circuit technology embodied in a Silicon
Systems, Inc. product. These products are not authorized for use as components in life
support devices or systems. No patents or licenses regarding the integrated circuit technology herein are implied unless otherwise stated.
© Copyright 1994 Silicon Systems, Inc. All rights reserved. Product and company names listed are trademarks of their
respective companies.
Contents
Target, Advanced and
Preliminary Information
In this data book the following conventions
are used in designating a data sheet
'Target," "Advanced" or "Preliminary":
Target SpecificationThe target specification is intended as an
initial disclosure of specification goals for
the product. Product is in first stages of
design cycle.
Advance InformationIndicates a product still in the design cycle,
undergoing testing processes, and any
specifications are based on design goals
only. Do not use for final design.
Preliminary DataIndicates a product not completely released to production. The specifications
are based on preliminary evaluations and
are not guaranteed. Small quantities are
available, and Silicon Systems should be
consulted for current information.
III
Index
Page #
Contents
.................................................................................................................................................... 111
Index ................................................................................................ ,.................................................................... IV
Numerical Product Index .....................................................................................................................................VII
Discontinued Parts List ...................... ,................. ;..............................................................................:................ VII
Product Selector Guide ......................................................................................................................................VIII
Winchester Disk Drive Product Family Chart ...................................................................................................... Xll
Section 1.
CUSTOM SOLUTIONS ................................................................................................................ 1-1
Section 2.
QUALITY ASSURANCE AND RELIABILITY .............................................................................. 2-1
Section 3.
HOD READIWRITE AMPLIFIERS
32Rl04C
32Rl17/117RI
117Nl17AR
32RS01fSOl R
32RSl ONSl OAR
32RSll/S11 R
32RS12/S12R
32RS121 IS121 R
32RS16/S16R
32RS161 R
32RS20/S20R
32RS21 1521 RIS211
32RS22/522R
32RS24R
32RS2SR
32RS27R
32RS28R
32RS281AR
32R1203N1203/AR
32R1Sl0BR
32R1S40R
32R2010R
32R2011 R
32R2020Rf21 R
32R2024R
32R202SR
32R2026R
32R2028R
32R2030N2031A
32R2041 RW
32R2060
32R2063Rf64R/6SR
32R211 ORf2111 R
32R2200Rf2201 R
322300/2300Rf
2301/2301 R
32R231 0/231 OR
32R2320/21 1221
23/24
32R2420
32R461 ON4611 N
4610B
4-Channel ReadIWrite Device .................................................................................................. .
2', 4-, 6-Channel ReadIWrite Device ........................................................................................ *
4-, 6-, 8-Channel ReadIWrite Device ........................................................................................ .
2-, 4-, 6-Channel ReadIWrite Device .........................................................................................
4-,6-, 8-Channel, Ferrite ReadIWrite Device ............................................................................ .
8-, 9-Channel, Thin Film ReadIWrite Device ............................................................................ .
14-Channel, Thin Film ReadIWrite Device ................................................................................ .
4-, 6-,8-Channel, Ferrite/MIG ReadIWrite Device .................................................................... .
10-Channel, Ferritel MIG ReadIWrite Device ........................................................................... .
4-Channel, Thin Film ReadIWrite Device .................................................................................. •
6-Channel, Thin Film ReadIWrite Device .................................................................................. .
4-, 6-Channel, Thin Film ReadIWrite Device ............................................................................ .
8-Channel, Thin Film ReadIWrile Device .................................................................................. .
4-Channel, Thin Film ReadIWrite Device .................................................................................. .
8-, 9-Channel, Thin Film ReadIWrite Device ............................................................................ .
9-Channel, Thin Film ReadIWrite Device ...................................................................................
14-Channel, 2-Terminal ReadIWrite Device ......................................................................... 3-1
SV, 4-Channel, 3-Terminal ReadIWrite Device ..................................................................... 3-9
MR Head ReadIWrite Device .............................................................................................. 3-19
6-Channel, MR ReadIWrite Device .....................................................................................3-29
10-, 16-Channel, Thin Film ReadIWrite Device ................................................................... 3-31
1O-Channel, Thin Film ReadIWrite Device .......................................................................... 3-39
SV, 2-, 4-, 10- Channel ReadIWrite Device ......................................................................... 3-49
SV, 4-Channel, Thin Film ReadIWrite Device ........................................................................... .
SV, 4-Channel, Thin Film ReadIWrite Device ..................................................................... 3-S9
SV, 4-Channel, Thin Film Read/Write Device ..................................................................... 3-67
SV, 10-Channel, Thin Film ReadIWrite Device ................................................................... 3-7S
SV, 2-, 4-Channel, Thin Film Read/Write Device ................................................................ 3-83
4-, 6-Channel, 2-Terminal ReadIWrite ................................................................................ 3-93
SV, 8-Channel, Thin Film ReadIWrite Device ............................................................................ .
SV, 4-Channel, Thin Film ReadIWrite Device ................................................................... 3-101
18-, 24-Channel, Thin Film ReadIWrite Device ................................................................. 3-113
SV, 4-Channel, Thin Film ReadIWrite Device ................................................................... 3-11S
3.3VIS.OV, 2-, 4-Channel, 2-Terminal ReadIWrite Device ................................................ 3-127
3.3VIS.OV, 2-, 4-Channel, 2-Terminal ReadIWrite Device ........................................................ *
3V, SV, 4-Channel, 2-Terminal ReadIWrite Device ........................................................... 3-13S
SV, 4-Channel, 2-Terminai ReadfWrite Device ................................................................. 3-147
SV, 2-, 4-, 8-Channel, Thin Film ReadfWrite Device ................................................................. .
• Data Sheet available upon request.
IV
Section 4.
DISCRETE CHANNEL
32D5321
32D5322
32D534A
32D535
32D5351A
32D5362A
32D5371 172/73/7 4
32D539
32D5391
32D5392
32D5393
32D5396/96A
32D4660
32D4661 14662
32D4663
32D4664
32D4665
32D4666
32D4680
32P541
32P541B
32P541C
32P544
32P547
32P5491
32P3000
32P3001
32P3011
32P3013
32P3015/3016
32P3030
32P3031
32P3040
32P3041
Section 5.
IN/{gPJlf
Section 6.
Data Synchronizer/2. 7 RLL ENDEC ........................................................................................ .
Data Synchronizer, 2, 7 RLL EN DEC .......................................................................................•
Data Synchronizer/MFM EN DEC ..............................................................................................•
Data Synchronizer, 2, 7 RLL ENDECIWrite Precompensation .................................................•
Data Synchronizer, 2, 7 RLL ENDECIWrite Precompensation .................................................•
Data Synchronizer,1, 7 RLL ENDECIWrite Precompensation ..................................................•
Data Synchronizer, 1, 7 RLL ENDEC IWrite Precompensation ................................................ .
Data Synchronizer, 1,7 RLL EN DEC, 8-Bit NRZ .....................................................................•
Data Synchronizer, 1,7 ENDEC, Serial NRZ ...........................................................................•
Data Synchronizer, 1, 7 ENDEC, Dual·Bit NRZ ........................................................................•
Data Synchronizer, 1,7 ENDEC, Window Shift, Write Precomp ..............................................•
Data Synchronizer, 1,7 RLL EN DEC, Window Shift, Write Precomp .................................. 4-1
Time Base Generator ...............................................................................................................•
Time Base Generator ...............................................................................................................•
Time Base Generator ...............................................................................................................•
Time Base Generator ...............................................................................................................•
Time Base Generator ...............................................................................................................•
Time Base Generator .......................................................................................................... 4·21
Time Base Generator .......................................................................................................... 4·31
Read Data Processor ...............................................................................................................•
Read Data Processor ...............................................................................................................•
Pulse Detector .....................................................................................................................4·35
Read Data Processor and Servo Demodulator ......................................................................... .
High Performance Pulse Detector ............................................................................................ .
Pulse Detector ...........................................................................................................................
Pulse Detector with Programmable Filter ................................................................................. .
Pulse Detector with Programmable Filter ................................................................................. .
Pulse Detector with Programmable Filter ................................................................................. .
Pulse Detector with Programmable Filter ............................................................................ 4·47
Pulse Detector with Programmable Filter ............................................................................ 4·59
Pulse Detector and Servo Demodulator ................................................................................... .
Pulse Detector and Servo Demodulator ................................................................................... .
Pulse Detector with Programmable Filter ............................................................................ 4·75
Pulse Detector with Programmable Filter ............................................................................ 4·85
PROGRAMMABLE ELECTRONIC FILTERS
32F8001
32F8002/8003
32F8011/8012
32F8020/8022
32F8020N8022N
802118023
32F8030
32F8101/8102J
8103/8104
32F8120
32F8130/8131
32F8144
Low·Power Programmable Electronic Filter .......................................................................... 5-1
Low-Power Programmable Electronic Filter ........................................................................5-13
Programmable Electronic Filter ...........................................................................................5-23
Programmable Electronic Filter ................................................................................................. .
Low·Power Programmable Electronic Filter ........................................................................ 5-35
Programmable Electronic Filter ........................................................................................... 5-47
Low·Power Programmble Electronic Filter .......................................................................... 5-57
Low·Power Programmable Electronic Filter ........................................................................ 5-69
Low·Power Programmable Electronic Filter ........................................................................ 5-77
Low·Power Programmable Electronic Filter ........................................................................ 5·85
READ CHANNEL COMBINATION DEVICES
32P548
32P5482
32P4331
32P4340/41
32P4720A
32P4722
32P4731 141
32P4742/42N
46/46A
32P4782
32P4901
Pulse Detector and Data Synchronizer Combination Device .................................................... .
Low Power Pulse Detector and Data Synchronizer .................................................................. .
Read Channel Device ................................................................................................................
Read Channel Device ........................................................................................................... 6-1
Pulse Detector & Data Separator .............................................................................................. .
Pulse Detector & Data Separator .............................................................................................. .
Read Channel with 1,7 ENDEC, 4-Burst Servo ........................................................................ .
Read Channel with 1,7 ENDEC, 4·Burst Servo .................................................................... 6·5
80 Mbitls Read Channel Device .......................................................................................... 6·67
PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo .................................................. 6·73
• Data Sheet available upon request.
v
Section 7.
rMfgrtl!'
rMfgrtl!'
rMfgrtl!'
rMfgrtl!'
rMfgrtl!'
rMfgrtl!'
Section 8.
HDD HEAD POSITIONING
32H569
32H4633
32H6110
32H6210
32H6215
32H6220
32H6230
32H6231
32H6240
32H6510
32H6520
32H6521
32H681 ON681 OB
32H6811/6811 B
32H6812
32H6814
32H6820
32H6825
32H6830
HDD SPINDLE MOTOR CONTROL
32M593A
32M594
32M595
32M7010
32M7011
Section 9.
rMfgrtl!'
rMfgrtl!'
rMfgrtl!'
rMfgrtl!'
Section 10.
Three-Phase Delta 5-1/4" Winchester Motor Speed Controller ................................................ .
Three-Phase Delta Motor Speed Controller .............................................................................. •
Hall Sensorless Motor Speed Controller ................................................................................... .
Hall Sensorless Motor Speed Driver/Controller .................................................................... 8-1
Hall Sensorless Motor Speed Driver/Controller .................................................................... 8-9
HDD CONTROLLER/INTERFACE
32C9001
32C9003
32C9020
32C9022
32C9023
32C9024
32C9301
32C9302
32C9340
32C9600
32C9800
PC/AT Combo Controller, 48 Mbit's ..................................................................................... 9-1
PC/AT Combo Controller, 48 Mbit's; 72 MbiVs; Dual-BitNRZ Interface ............................ 9-25
SCSI Combo Controller, 48 MbiVs, Single-Bit NRZ Interface ............................................. 9-49
SCSI Combo Controller, 48 Mbit's, Dual-Bit NRZ ............................................................... 9-73
SCSI Combo Controller, 72 Mblt's; Dual-Bit NRZ Interface ................................................ 9-99
SCSI Combo Controller, 80 Mbit's; Dual-Bit NRZ Interface .............................................. 9-125
PC/AT Combo Controller with Reed Solomon, 3V Operation ........................................... 9-151
PC/AT Combo Controller with Reed Solomon, 3V Operation ........................................... 9-175
PCMCIA Combo Controller with Reed Solomon, 32/48 Mbit's ......................................... 9-199
ATA-Z Storage Controller; 160-Mbit's, 8-bit NRZ Interface .............................................. 9-211
SCSI-3 Storage Controler; 160-Mbit's, 8-bit NRZlnterface .............................................. 9-221
OPTICAL/FLOPPY CIRCUITS
33P3700
33P3733A
33P3733/34
34P553/5531
34P3200
34P3201
34R1203R
Section 11.
Servo Motor Driver ................................................................................................................7-1
Hybrid Servo & Spindle Motor Controller ............................................................................ 7-17
Differential Amplifier ............................................................................................................ 7-59
Servo Demodulator ............................................................................................................. 7-63
Servo Demodulator ............................................................................................................. 7-79
Servo Controller .........................................................................................................................
Servo Motor Driver ......... :.................................................................................................... 7 -85
Servo Motor Driver ..............................................................................................................7-99
Servo Motor Driver ............................................................................................................ 7-113
5V Servo Motor Driver ....................................................................................................... 7-123
Embedded Servo Controller .............................................................................................. 7-129
Embedded Servo Controller .............................................................................................. 7-149
5V Servo & Motor Speed Drivers ...................................................................................... 7-165
Servo Motor Speed 5V Driver/DAC ................................................................................... 7-179
Servo & Spindle Driver With Shock Detection .................................................................. 7-195
Servo & Spindle Motor Speed Controller .......................................................................... 7-213
Servo & Spindle Predriver ................................................................................................. 7-229
Servo & Spindle Predriver ................................................................................................. 7-249
Servo DSP ................................................. :...................................................................... 7-263
8-, 48-Mbit's Magneto Optical Read Channel ..................................................................... 10-1
8-, 26.5-MbiVs Read Channel ............................................................................................. 10-3
8-, 26.5-MbiVs Read Channel ........................................................................................... 10-31
Pulse Detector and Synchronizer ...................................................................................... 10-61
Pulse Detector & Data Synchronizer for High Density Floppy Storage ............................. 10·87
Pulse Detector & Data Synchronizer, 250K to 8.0 Mbit's ............................................... 10-109
5V, 2-, 4·Channel, 3-Terminal; Read/Write Device ......................................................... 10-133
PACKAGING/ORDERING INFORMATION
See Section 11 index on page 11.
Section 12.
Section 13.
SALES OFFICES/DISTRIBUTORS ............................................................................................. 12-0
APPLICATION NOTES .............................................................................................................. 13-1
See Section 13 index on page 13 .
• Data Sheet available upon request.
VI
Numerical Index
551 Device Numbers
Page #
32C9001 ............................................ 9-1
32C9003 .......................................... 9-25
32C9020 .......................................... 9-49
32C9022 .......................................... 9-73
32C9023 """"""""""""'''''''''''''''''' 9-99
32C9024 ........................................ 9-125
32C9301 ........................................ 9-151
32C9302 ........................................ 9-175
32C9340 ........................................ 9-199
32C9600 ........................................ 9-211
32C9800 ........................................ 9-221
3205321 ............................................... .
3205322 ............................................. .
320534A ............................................... .
320535 ................................................. .
3205351A ............................................. .
3205362A ............................................ .
3205371/5372/5373/5374 .................... .
320539 ................................................. .
3205391 ............................................... .
3205392 ............................................... .
3205393 ............................................... .
3205396/5396A ................................ 4-1
3204660 ............................................... .
3204661/4622 ...................................... .
3204663
............................ ..
3204664 ............................................... .
3204665 ............................................... .
3204666 .......................................... 4-21
3204680 .......................................... 4-31
32H8001 ............................................ 5-1
32F8002/8003 ................................. 5-13
32F8011/8012 ................................. 5-23
32F8020/8022 ....................................... .
32F8020Al8022A18021/8023 .......... 5-35
32F8030 .......................................... 5-47
32F8101/8102/8103/8104 ............... 5-57
32F8120 .......................................... 5-69
32F8130/8131 ................................. 5-77
32F8144 .......................................... 5-85
32H569 .............................................. 7-1
32H4633 .......................................... 7-17
32H6110 .......................................... 7-59
32H6210 .......................................... 7-63
551 Device Numbers
Page #
32H6215 .......................................... 7-79
32H6220 ............................................... .
32H6230 .......................................... 7-85
32H6231 .......................................... 7-99
32H6240 ........................................ 7-113
32H6510 ........................................ 7-123
32H6520 ........................................ 7-129
32H6521 ........................................ 7-149
32H6810/6810B ............................ 7-165
32H6811/6811B ............................ 7-179
32H6812 ........................................ 7-195
32H6814 ........................................ 7-213
32H6820 ........................................ 7-229
32H6825 ........................................ 7-249
32H6830 ........................................ 7-263
32M593A ............................................... .
32M594 ................................................. .
32M595 ................................................. .
32M7010 ........................................... 8-1
32M7011 ........................................... 8-9
32P541 .................................................. .
32P541B ............................................... .
32P541C ......................................... 4-35
32P544 .................................................. .
32P547 .................................................. .
32P548 .................................................. .
32P5482 ................................................ .
32P5491 ................................................ .
32P3000 ................................................ .
32P3001 ................................................ .
32P3011 ................................................ •
32P3013 .......................................... 4-47
32P301513016 ................................. 4-59
32P3030 ............................................. ..
32P3031 ........................................... .
32P3040 .......................................... 4-75
32P3041 .......................................... 4-85
32P4331 ................................................ .
32P4340/4341 ................................... 6-1
32P4720A ............................................. .
32P4722 ................................................ .
32P4731/41 ........................................... .
32P4742142A14746146A .................... 6-5
32P4782 .......................................... 6-67
551 Device Numbers
* Data Sheet available upon request
Discontinued Parts List
The following parts are no longer supplied or supported by 5i1icon Systems.
32C4650
32C4651
32C9342
3204010
3204420
32F8000
32Hl0l
32Hl16A
32H523AR
32H566R
32H4631/4632
32P3010
32P4620/4622
32P4731
32P5411B
32P546
32P548
32P549
VII
Page #
32P4901 .......................................... 6-73
32Rl04C ............................................... .
32Rl17/117R1117A1117AR .................. .
32R501/501 R ........................................ .
32R510Al510AR ................................... .
32R511/511R ........................................ •
32R5121512R ........................................ .
32R5121/5121 R .................................... .
32R516/516R ........................................ .
32R5161R ............................................. •
32R520/520R ........................................ .
32R521 1521 Rl5211 ............................... .
32R522/522R .......................... .
32R524R ............................................... •
32R525R ............................................... .
32R527R ............................................... .
32R528R ............................................... .
32R5281AR ....................................... 3-1
32R1203A11203AR ........................... 3-9
32R1510BR ..................................... 3-19
32R1540R ....................................... 3-29
32R2010R ....................................... 3-31
32R2011R ....................................... 3-39
32R2020Rl2021R ........................... 3-49
32R2024 ........................ .
32R2025R ....................................... 3-59
32R2026R ....................................... 3-67
32R2028R ...................................... 3-75
32R2030Al2031A ............................ 3-83
32R2041RW .................................. 3-93
32R2060 ............................................... .
32R2063R12064 Rl2065R .............. 3-1 0 1
32R2ll0Rl2lll R ......... .. ..
.. ... 3-113
32R2200/2201R ............................ 3-115
32R2300/2300Rl2301/2301 R ....... 3-127
32R2310/2310R .................................... .
32R2320/21 122123/24 .......... .. ...... 3-135
32R2420 ........................................ 3-147
32R4610A/4611A14610B .................... ..
33P3700 .......................................... 10-1
33P3733A ....................................... 10-3
33P3733134 ................................... 10-31
34P553/5531 ................................. 10-61
34P3200 ........................................ 10-87
34P3201 ...................................... 10-109
34R1203R ................................... 10-133
32P5481
32Rl200R
32R 1220/21 122
32R2015R
34B580
340441
34R575
STORAGE PRODUCTS REFERENCE
Head Type
Device Number
Number of
Channels
Power
Capacitance
(pF)
Read
Gain
(typ)
Write Current
Noise
(nVNHz)
Range
(mAl
Supplies
(V)
IOt050
IOt050
+5,+12
Max Input
Max Input
Write
Data Ports
Min. Head
Swing
(V)
READ/WRITE AMPLIFIERS
SS132R117/117R
3 Terminal
2,4,6
2.1
20
100
SS132R501/501R
SS132R510A/510AR
3 Terminal
4,6,8
1.5
3 Terminal
3 Terminal
1.5
1.5
100
100
SS132R511/511R
2,4,6
4,6,8
23
20
SSI32R516
SSI 32R5161 R
3 Terminal
4,6,8
100
120
10 to 40
10to 60
3 Terminal
SS132R512/512R
SS132R5121/5121R
SSI32R524R
2 Terminal
10
8,9
14
1.3
1.3
20
18
18
35
150
150
SSI32R528R
SSI32R5281
SSI32RI510BR
2 Terminal
35
60
35
250
100
150
IOt060
IOt040
10 to 40
35
18
250
150
SSI32RI530
SSI32RI540
:s
2 Terminal
2 Terminal
2 Terminal
8
8,9
14
MR
MR
8
10
MR
MR
0.85
0.85
0.75
0.85
0.85
0.95
2 Terminal
0.84
26
150
SSI 32R2020R/2021 R
2 Terminal
2,4,10
0.8
20
22
300
150, 200, 300
SS132R20.24
2 Terminal
4
0.75
SSI32R2025
SSI32R2026
2 Terminal
0.75
0.75
22
300
2 Terminal
4
4
22
SSI 32R2030A/2031 A
2 Terminal
2,4
0.85
SSI32R2041
SSI32R2060
2 Terminal
SSI 32R2063/ 64/65
SSI32R2100
SSI32R2110
SSI32R2112
SSI 32R2200/2201
2 Terminal
4,6
8
4
0.8
0.75
0.75
35
22
22
300
250
10
24
20
4,6
0.70
0.70
0.70
0.70
SSI32R2300/2300R/2310
SSI 32R2320R/2420R
2 Terminal
4
2 Termianl
SS132R4610A/4611A
2 Terminal
2,4
2,4,8
2 Terminal
2 Terminal
2 Terminal
2 Terminal
2 Terminal
20 to 60
10 to 40
10 to 40
20 to 50
+5, +12
+5, +12
+5, +12
+5, +12
+5,
+5,
+5,
+5,
+12
+12
+12
+12
+5, +12
+5, +12
+5, -I
TTl
TTl
TTl
TTl
TTl
TTl
TTl
TTl
TTl
Differential
Differential
Differential
8.010-pk)
7.510-pk)
7.010-pkl
7.010-pkl
7.010-pkl
7.010-pkl
7.0Ipk-pkl
7.0 {pk-pkl
7.0Ipk-pkl
7.0 {pk-pkl
7.0 {pk-pkl
8.0Ipk-pkl
+5, -4.5
+5, -3
4,6
8
10
SSI32RI560
SSI 32R2010R/201 IR
IOt040
+5, +12
250
150
10to 25
5 to 35
+5, +12
5t040
+5
+5
5 to 35
5 to 35
+5
+5
10 to 35
+5
5,12
10 to 40
5 to 35
3 to 40
+5
+5
+5, +12
22
18
150,200
250
18
18
18
250
150
250
5t040
5 to 40
5 to 40
3 to 35
0.75
0.75
20
20
200
200
3 to 25
3 to 35
+5
+3.3/+5
+3.3/+5
0.85
35
200
IOt035
+5
----
+5, +12
+5, +12
Differential
TTl
TTl
TTl
TTl
TTl
ECL
TTl
TTl/Eel
Eel
ECL
Eel/TTl
Eel/TTl
TTl
ECl/TTl
TTl
7.0 {pk-pkl
4.2Ipk-pkl
4.2 {pk-pkl
4.2 {pk-pkl
4.2 {pk-pkl
3.4 {pk-pkl
7.0 {pk-pkl
4.2 {pk-pkl
4.2Ipk-pkl
10.0Ipk-pkl
10.0Ipk-pkl
1O.0Ipk-pkl
6.0Ipk-pkl
3.4 {pk-pkl
3.4 {pk-pkl
3.4Ipk-pkl
----_ ..
_-
-
STORAGE PRODUCTS REFERENCE
Device Number
Circuit Function
Features
Data Separator
Data Synchronizer I 2, 7 Rll ENDEC 7.5 to 10 Mbit/s
Data Synchronizer I 2, 7 Rll EN DEC 7.5 to 13 Mbitl s
DISCRETE CHANNEL
551
551
551
551
551
551
551
551
551
x
32D5321
32D5322
32D534A
32D5351 A
32D5362A
32D5371 12
32D5373/4
32D539
32D5391 12/3
Data Separator
Data Separator
Data Synchronizer / MFM ENDEC / Write Precompensation
Data Separator
Synchronizer I
Synchronizer I
Synchronizer I
Synchronizer I
Synchronizer I
Synchronizer I
Data Separator
551 32D4660/1/2/3/4/5/6
Time Base Generator
Up to 100 MHz Reference Frequency PLC for Constant Density Recording
551 32D4680
551 32P541
Time Base Generator
Read Data Processor
Up to 120 MHz, 1%Frequency Resolution
AGC, Amplitude & Time Pulse Qualification, Rll Compatible
551 32P541B
Read Data Processor
32P541 pin compatible, 32P541A wi Increased Data Rate to 24 Mbit/s
551 32P54lC
Read Data Processor
32P541 pin compatible, 32P541 A wi Increased Data Rate to 24 Mbit/s
551 32P544
Pulse Detector
32P541-type Pulse Detector wi Embedded Servo Electronics
551 32P547
Pulse Detector
32P544-type Pulse Detector wi Filter Multiplexer, Pulse Slimming Support
551 32P5491
Read Data Processor
32P549 pin compatible, 5 mW Idle Mode power, pd ~ 170 mW
551 32P3000/3001
Pulse Detector / Programmable Filter
64 Mbit/s Pulse Detector w/9-27 MHz Bessel filter (30001, 8-24 MHz filter (30011, +5V only
551 32P3013
Pulse Detector / Programmable Filter
48 Mbit/s Pulse Detector w/9-27 MHz Bessel filter, 4-burst servo capture
551 32P3015/3016
Pulse Detector / Programmable Filter
64 Mbitl s Pulse Detector w/9-27 MHz Bessel filter, 4-burst servo capture, adjustable RD pulse width
551 32P3030/31
Pulse Detector / Servo Demodulator
Pulse Detector w/2-burst servo demodulator, +5V only
SSI 32P3040/41
Pulse Detector / Programmable Filter
24-32 Mbit/s Pulse Detector w/2.5-13 MHz Bessel filter, +5V only
Data Separator
Data Separator
Data Separator
Data Separator
2, 7
1, 7
1, 7
1, 7
1, 7
1, 7
Rll ENDEC I
Rll ENDEC I
Rll ENDEC I
Rll ENDEC I
Rll ENDEC I
Rll ENDEC I
Data
Data
Data
Data
Data
Data
Write Precompensotion 8 to 18 Mbitl s
Write Precompensation 10 to 20 Mbitl s
Write Precompensotion 12 to 24 Mbitl s
Write Precompensation 15 to 32 Mbitl s
8-bit parallel NRZ 24 to 48 Mbit/s
Serial NRZ 24 to 40 Mbitl s
READ CHANNEL COMBINATION DEVICES
32P544-type wi 2, 7 Synchronizer, low Power, +5V only, <700 mW
SSI32P548
Pulse Detector / Dota Synchronizer
SSI32P5482
Pulse Detector / Data Synchronizer
Low power 32P548-type device (350 mWl, no Write Precompensation
551 32P47401 41
Complete Read Channel
4730 with 14 to 40 Mbit/s operation, A-B/C-D Servo
551 32P47421 42A
Complete Read Channel
4731 with 16 to 48 Mbit/s, Dual-bit NRZ, A-B/C-D Servo
551 32P47461 46A
Complete Read Channel
4730 with 16 to 48 Mbitl s, Dual-bit NRZ
551 32P4901
PR4, Ml Read Channel
Parital Response, Maximum likelihood channel, 24 to 72 Mbit/s, Dual-bit NRZ
I
I
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I
I
PROGRAMMABLE FILTERS
551 32F8001 18002
Low Power Programmable Electronic Filter
7-Pole Equiripple Active Filter, Programmable Cutoff Frequency I Pulse Slimming, 9 - 27 MHz (8001), 6-18 MHz (8002)
551 32F8003
Programmable Electronic Filter
7-Pole Equiripple Active Filter, Programmable Cutoff Frequency I Pulse Slimming, 5 - 13 MHz
551 32F8011 18012
Programmable Electronic Filter
7-Pole Bessel Active Filter, Programmable Cutoff Frequency I Pulse Slimming, (5 - 13 MHz, 8011) (6-15 MHz, 8012)
551 32F8020/8022
Low Power Programmable Electronic Filter
7-Pole Equiripple Active Filter, Programmable Cutoff Frequency I Pulse Slimming, 1.5 - 8 MHz
551 32F8030
Programmable Electronic Filter
7-Pole Equiripple Active Filter, Programmable Cutoff Frequency I Pulse S.limming, 250 kHz - 2.5 MHz
551 32F8101
Low Power Digitally Programmable Filter
8001 wISerial Port & DACs, 95 mW
551 32F8102
Low Power Digitally Programmable Filter
8002 w/Serial Port & DACs, 95 mW
551 32F8103
Low Power Digitally Programmable Filter
8003 w/Serial Port & DACs, 95 mW
SSI32F8104
low Power Digitally Programmable Filter
Similar to 8103, Fe range 3-9 MHz
STORAGE PRODUCTS REFERENCE
Device Number
Circuit Function
Features
PROGRAMNIABLE FILTERS (continued)
32FS020 with serial port and DACs
SSI32FS120
low Power Digitally Programmable Filter
SSI 32FS130/31
low Power Digitally Programmable Filter
32FS030 with serial port and DACs / 32FS131 ~ 150 kHz < Ie < 1.5 MHz
SSI32FS144
Low Power Digitally Programmable Filter
2 zero/7-pole linear phase filter, 7-bit serial shik register, 7-27 MHz
SSI32H569
SSI32H4633
SSI32H6110
SSI32H6210
SSI32H6215
SSI32H6220
SSI 32H6230/31
SSI32H6240
SSI32H6510
SSI32H6520
SSI32H6521
Servo Motor Driver
Servo 5V Demodulator
Head parking, spindle motor braking
Embedded & hybrid servo, Hall sensorless motor speed control, 5400 RPM
AV ~ 250 or 300, BW = 20 MHz, eo = 0.S5 nV!YHz
Di-bit ,quadrature servo pattern; PLl synchronization AGe adiustment
5V, 500 kHz frame rate dedicated servo demodulator
Servo Controller
Track
Servo Motor Driver
Servo 5V Driver
Servo Acquisition and DfA
Embedded Servo Controller
Head parking, spindle motor braking, voltage damp
Predriver for bipolar H-bridge
low voltage retract, 1Q drivers
1O-bit A/D D/A circuits, DSP interface
1O-bit A/D converter, 2.5 ~ digital delay, DSP interface
SSI32H6S10/6S10A/B
Servo/Spindle 5V Driver
Combo driver supports 5V@ 1.OA, voltage IN
SSI32H6S11 /11 B
SSI32H6S12
Servo/Spindle 5V Driver
Servo/Spindle 5V Driver
Combo driver supports 5V @ 1.OA, voltage IN, serial port with DACs
10-bit D/A converter, serial DSP interface
SSI32H6S14
Servo/Spindle 5V Driver
10-bit D/A converter, serial DSP interface
SSI32H6S20
Servo/Spindle 12V Driver
Servo head positioning and motor speed control
SSI32H6S25
Servo/Spindle 12V Driver
Window comparator, uncommitted opamp, reduced power dissipation
SSI32H6S30
Servo/Spindle DSP Controller
DSP with lO-bit A/D & dual D/A converters
HEAD POSITIIONING
x
Combo Servo & Motor Speed Control
Preamplifier -Thin Film head
Servo Demodulator
Servo Motor Driver
& seek mode operation; microprocessor interface
SPINDLE MOTOR CONTROL
SSI32M593A
3-phase Motor Speed Control
±O.037% speed accuracy; bipolar operation, 5 1/4 11 drives
SSI32M594
3-Phose Motor Speed Control
±0.037",6 speed accuracy; bipolar operation, 3 1/2" & 5 1/4" drives
SSI32M595
3-Phase Sensor-less MSC
Hall sensorless; motor speed control
SSI32M7010
Motor Speed Control 5V Driver
Hall sensorless; commutator digital speed control, 5V 1n driver
SSI32M7011
Motor Speed Control 5V Commutator
Hall sensorless; commutator, 5V 1Q driver
STORAGE PRODUCTS REFERENCE
Circuit Function
Features
SSI32C9001
ATA Combo Controller
48 Mbit/s; High Performance ATA Disk Controller
SSI32C9003
High Perf. ATA Combo Controller
72 Mbit/s; LBA mode; Automated multi commands
SSI32C9020
High Perf. SCSI Combo Controller
SSI32C9022
Dual-bit High Perf. SCSI Combo Controller
48 Mbit/ s; SCSI-2 compatible; Fast SCSI; single ended
Dual-bit NRZ, 48 Mbit/s; SCSI-2 compatible; Fast SCSI
SSI32C9023
Dual-bit High Perf. SCSI Combo Controller
Dual-bit NRZ, 72 Mbit/s; SCSI-2 compatible; Fast SCSI
SSI32C9024
Dual-bit High Perf. SCSI Combo Controller
Dual-bit NRZ, 72 Mbit/ s; SCSI-2 compatible; Fast SCSI; Differential
SSI32C9301
High Perf. ATA Combo Controller {3V, 5VI
32 Mbit/s 13Vj, 48 Mbit/s 15VI; LBA mode support
SSI32C9302
Dual-bit High Perf. ATA Combo Cont.13V, 5VI
Dual-bit NRZ, 48 Mbit/ s; LBA made support
SSI32C9340
SSI32C9600
Dual-bit PCMClA/ATA Combo Cantroller 13V, 5VI
ATA-2 Cantroller
Dual-bit NRZ, 48 Mbit/s 13V/5VI; 256 byte CIS
Dual-/8-bit NRZ; 160 Mbit/ s; ATA/ ATA- 2 Compatible; Wide Buffer; Advanced Reed-Solomon ECC
SSI32C9800
SCSI-3 Controller
Dual-/8-bit NRZ; 160 Mbit/ s; SCSI -2/SCSI -3 Compatible; Fast and wide; Advanced Reed-Solomon ECC
S5134P553/5531
Pulse Detector/Dato Synchronizer
S5134P3200
Pulse Detector/Data Synchronizer
SSI34P3201
SSI 34R 1203R
Pulse Detector/Data Synchronizer
0.6 - 1.6 Mbit/s data rate, MFM or 2, 7 RLL code
250K - 6 Mbit/s
250K - 8 Mbit/ s
5V, 2-, 4-Channel, 3-Terminal R/W
Selectable gain, 250 VIV and 85 VIV
Device Number
CONTROLLER/INTERFACE
FLOPPY DISK DRIVES
~
OPTICAL DISK DRIVES
SSI33P3700
Magneto Optical Read Channel
Pulse detector/filter/time base generator/data synchronizer, 8-48 Mbit/s
SSI 33P3733/3734
Read Channel, No ENDEC
Pulse detector/filter/time base generator/data separator, 8 - 26.5 Mbit/s
551 33P3733A
Read Channel, No ENDEC
33P3733 with MO pit qualifier
SS134P553/5531
Pulse Detector/Dota Synchronizer
0.6 - 1.6 Mbit/s data rate, MFM or 2, 7 RLL code
5S134P3200
Pulse Detector/Data Synchronizer
250K - 6 Mbit/ s
5S134P3201
Pulse Detector/Data Synchronizer
TAPE DRIVES
250K - 8 Mbit/ s
- - - - - - - -- - - - - - - -
WINCHESTER DISK DRIVE IC PRODUCT FAMILY
----------------------,
I
I
I
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-"
-
-
&L~if0"
R
,a 1
"
;"
I
MSC
551 32M593A
551 32M594
551 32M595
SSI32M7010
S5132M7011
HEAD
POSITIONING
~
S5132H569
SS132H4631
SSI 32H4633"
SSI32H6210
SSI32H6215
5S132H6220
SSI32H6230
SSI32H6240
SS132H6510
SS132H6520
SSI32H6521
3-TERMINAL
2-TERMINAL
S5132R1l7
S5132R117A
SSI32R1200
SSI32R501
SSI32R510A
SSI32R511A
SSI32R516
SSI32R5161
5S132R1220
SSI32R512
551 32R5121
SSI32R524
SSI32R528
SSI32R2010
SS132R2020/21
SSI32R2024
S5132R2025
SSI32R2026
SS132R2030/31A
S5132R2041
551 32R2060
551 32R2063/64/65
5S1 32R2100"
5S1 32R211 0"
551 32R2200/2201"
551 32R23OO/10/20
5S1 32R5281 A
MRHEAD
PREAMP
SSI32R1510BR
I
--------------------~
I
1---------1
I
I
I
I
iMSC & HEAD
POSITIONING
551 32H681 OAiB
551 32H6811 /B
S5132H6812
S5132H6814"
551 32H6815"
551 32H6820"
551 32H6825"
551 32H6826"
551 32H6830
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
5S132P3000
5S132P3001
551 32P3013
5S132P3015
5S132P3030
5S132P3040/41
5S1 32P4720/1"
551 32P541
SSI32P541B
551 32P544
5S132P547
Combo - 551 32P548
S5132P5482
Combo - 5S1 32P549/5491
Combo - 5S1 32P4730
Combo - 551 32P4741
Combo - SSI 32P4742
Combo - 5S1 32P4744
Combo - 5S1 32P4745
Combo - 5S1 32P4746"
Combo - S51 32P4750"
Combo - 5S1 32P4752"
Combo - 551 34P553/5531
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
5S1 3204040/41"
5S13204660
5S13204661
5513204662
S513204664
5513204665
5S13204666
5513205321
5513205322
551 320534A
5S1320535
5S13205351
S51 3205362A
5513205371
5513205372
5S13205373
S513205374
S51320539
5513205391
5513205392
S513205393
S51 3205396/96A
I
I
I
I
I
I
1______ _
5S132FBOOI
551 32F8002
551 32F8.011 /12
551 32F8020/20A
SSl32F8030
SSI32F8101/2/3/4
551 32F8120
551 32F8130/31
5S132F8144"
5S132C9001
551 32C9003
551 32C9020
551 32C9022
5S132C9023
5S132C9024
5S132C9301
5S132C9302
SSI 32C9340"
SSI 32C96OO"
5S1 32C9800"
'----,--.::--I-----i--:;::--I
" New or In Development
Section
1
CUSTOM
SOLUTIONS
1-0
CUSTOM SOLUTIONS
Faster to market for mixed-signal applications
SILICON SYSTEMS LEADS THE WA Y
DEVELOPING MIXED-SIGNAL CUSTOM
PRODUCTS.
Whatever your mixed-signal design application. Silicon
Systems gives you a competitive advantage. In communications, disk drives, other storage products. automotive control
systems, or other analog/digital signal processing applications,
you can depend on our technical know-how to do the job right
and turn your design around faster.
This is a story about leadership. Silicon Systems is dedicated to taking the point in the creation of high-performance,
application-specific custom, mixed-signal integrated circuits
(MSICs®).
CMOS. Bipolar. BiCMOS. Analog. Digital.
We've done it
Such dedication means we bring a lot to the party. Including truly innovative analog, digital, and mixed analog/digital
ICs. A full complement of mixed-signal CMOS, BiCMOS and
Bipolar wafer fabrication processes, state-of-the-art automated
design tools, production, assembly, test, and QA capability.
Our designers are an experienced bunch. They're uniquely
able to take a look at your specific application problem and
move quickly to the right IC solution.
Our team is particularly adept at identifying key issues
such as power, cost and performance trade-oils. So we can
gear our efforts toward delivering you an optimized solution,
manufactured with the appropriate fab process.
No one's more experienced
Morethan 20 years of successfullC design work makes us
the most experienced engineering team in the MSICs field. Add
it all up and you get a company that saves you time and money
while delivering you the most sophisticated mixed-signal custom ICs you can get.
::::'.2;::,
.. ",2,
.:»:<<
CMOS Analog Processing
For analog continuous time, samples data
(switched-capacitor implementation), and
high-current power transistor applications.
low power, high density capability also
allows inclusion of ROMs, RAMs, and
other analog/digital subsystems.
o
0
0
o
0
o
BiCMOS Signal Processing
For high-performance, low noise,
wide band signal acquisition and processing applications. Offers TTL and/or ECl
logic interfaces with high current drive.
o
o
o
0
o
0
0
Digital CMOS
For ASIC controllers, digital signal
processors, sequencers and data path
applications with on-board ROM, RAM,
and PLA SUb-systems. Offers standard
TTL and/or CMOS logic interfaces.
1-1
0
0
o
o
o
Complete single-chip 2400 bitls modem
14.4 kbps modem chip set
Direct-broadcast satellite descrambler
Servo and spindle motor controllers with 1.0
Amp motor interfaces
High-resolution analog data acquisition
Cellular baseband processor
Sub 1 nV/,IHz HDD RIW amplifiers
AGC, pulse detection amplifiers
High-speed data separators
Wideband transceivers
Plls (phase locked loops)
Optical signal processing
Digital cellular, PCS IF circuits
Digital communications lAN devices
Hard disk drive controllers
SCSI interface controllers
UARTs
Digital signal processors for hard
disk servo and telecommunications
CUSTOM SOLUTIONS
The right mix of analog and digital
SOPHISTICATED TOOLS FOR
STRUCTURED CUSTOM DESIGN
Providing total analog/digital systems on a chip allows you
to meet your cost and performance objectives whether you're
designing the next generation of communication, computer
peripheral, or industrial control systems.
At each offive design centers capable of worldwide service
- Tustin, San Jose and Nevada City, California; Tokyo and
Singapore - Silicon Systems employs PEGASYS, an internal
design automation system developed from carefully selected
vendor tools and our own proprietary software. Using Mentor
Graphics workstations for both electrical and physical design,
PEGASYS helps create complex designs while significantly
reducing schedules, costs and errors.
We've turned to CMOS to effectively implement lowpower, highly integrated systems solutions lor everything from
modems and cellular phones to hard disk drive controllers and
digital signal processors.
We've gone the BiCMOS route to meet the high-performance needs of products like wideband transceivers, wireless
IF modems, RIW amplifiers, low-noise amplifiers, pulse detectors, high-speed data separators and high-performance, lowpower combo devices.
By integratingthird-party tools and custom software, we're
better able to design and analyze mixed-signal integrated
circuits in all CMOS, Bipolar and BiCMOS technologies. It's an
approach that has given us the edge in mixed-signal design and
helped put Silicon Systems' customers in a favorable position
in the marketplace.
• Product and company
names are trademarks of
their respective companies
PEGASYS Design System
1-2
CUSTOM SOLUTIONS
Specnically, PEGASYS brings the following to each design:
• Chip floor planning
• Fully integrated design environment
• Analog device generators
• Methodology for precision circuit design
• Schematic driven layout
• Integrated electrical and physical design
• On-line point-to-point routing
• Unique blend of full-custom and automated layout
techniques
• Automatic place and route
• Compaction
• Complete layout verification
• Support of custom cells, standard cells, and compiled
blocks in any combination
• Full mixed-signal parasitic extraction
Our design automation staff integrates the third-party tools
and optimizes their use on the Mentor platform. This framework
can easily accommodate new tools when needed, and it
enables us to support a combination of analog and digital
design techniques in all CMOS, Bipolar and BiCMOS chip
designs. By mixing design methodologies, we can achieve
optimum systems performance, even when schedules are
tight.
• Design rule checking (drc)
• Layout-versus-schematic verification (lvs)
• Parasitic extraction/back annotation
• Output in industry standard GDS format
In the first generation Pegasys system, Silicon Systems
pioneered a device-generator based approach to precision
analog layout. In partnership with Mentor Graphics, we have
enhanced this technique for our current system, based on
Mentor Graphics VB ICstationi!!> tools. ICstationi!!> provides tremendous flexibility, combined with ease of customization, to
fully support analog and mixed-signal designs. A variety of
layout styles and techniques are combined to meet each chip's
specific requirements. Rigorous verification checks ensure the
quality and accuracy of the layout, for both physical and electrical properties. Post-layout simulation uses true parasitic modeling to handle remaining problems before first silicon fabrication.
Electrical design
A single CAE (computer aided engineering) environment
provides for schematic capture, synthesis, simulation, and fault
grading. We support this software with extensive libraries of
pre-designed cells and components. Highly specialized cells or
components can be designed and enhanced where required.
We simulate each circuit to meet precise performance specifications using:
• Analog circuit simulation
STATE OF THE ART CMOS DIGITAL AND
ANALOG PROCESSES
• Digital logic simulation
• VHDL simulation
Silicon Systems offers four proven CMOS process technologies for creating cost effective, highly integrated systems solutions. These processes combine small geometry digital circuit
capability with high performance analog capability. Table 1 summarizes Silicon Systems' CMOS process capabilities.
Our newest CK process is designed to support high
breakdown, high current power FETs, bipolar structure for
specialized analog needs, poly capacitors and resistors, low
noise differential amplifiers and high performance AID and
D/A converters. It also includes highly optimized and silicon
area efficient digital cells including DSPs, microcontrollers,
sequencers, memory managers and data paths.
The CJ process provides high performance analog and
digital cells and includes the same analog and digital complex
devices in our CK process.
Our CG process supports high-performance analog circuitry with precision poly-poly capacitors. Complex analog
circuitry includes 1.25 Amp power FETs, 12-bit switched capacitor analog to digital converters and low distortion operational amplifiers and filters. Complex digital circuitry includes
DSPs, microcontrollers, sequencers, memory mangers and
data paths.
The CH process also provides high quality, low voltage
coefficient, precision poly-poly capacitors that support high
performance switched-capacitor filtering and data conversion
(AID and D/A ) circuits.
• Mixed-mode simulation
• Switched-capacitor filter simulation
• Analog and mixed-mode behavioral simulation
Admittedly, simulation alone is not the key to perfecting
performance. That's why we work aggressively to refine our
understanding of models to make them work with simulation.
Inside our progressive device modeling and chara.cterization
(DMC) laboratory, we develop accurate circuit simulation models and parameters. The DMC lab provides complete device
model data for our processes using capabilities such as AC
measurement, statistical analysis and worst-case modeling.
Accurate models are a cornerstone of our design-for-quality
approach.
To ensure high quality test vectors, production test vectors
are derived from simulation vectors using the TSSI tools early
in the design process. The industry-standard Zycad fault simulator is then used to determine fault coverage.
Physical design
Our PEGASYS layout system aids the mask designer
through all physical design phases, ensuring consistency
throughout the design cycle. This flexible, fully integrated
environment supports a broad range of layout techniques, from
lull-custom to full-automation. Capabilities include:
1-3
CUSTOM SOLUTIONS
BiCMOS process technologies
BIPOLAR & BICMOS PROCESS
TECHNOLOGIES
Our BiCMOS process portfolio is expanding to support the
evolving demands of the mixed-signal IC market. Now in
production is our BCA process which combines 13 GHz NPNs
with 1.0~ CMOS features to support the design of efficient, high
performance, mixed-signal circuits. High bandwidth analog
circuits can be combined with dense digitallogicto support the
development of 5V data channels with transfer rates into the
120+ MbiVs range, while maintaining low power consumption.
The BCA technology has also allowed our designers to develop
3V only circuits to address very low power applications.
Our bipolar MSICs take advantage of two high-performance Bipolar processes: BK (for 12Vapplicajions) and BN (for
5V applications). The BK analog/digital process achieves its
higher vo~age operation and improves lateral PNP transistor
performance by using a lightly-doped epi layer.
In BK we provide deep N+ and P+ enhancement layers to
reduce both collector series and base resistance. Our use of
up-junction isolation gives us a major reduction in device area,
when compared with that of typical junction isolated processes.
Metal-poly capacitors with a nitride dielectric are used for
improving capacitor reliability.
Our second generation BiCMOS process, BCB, will provide the next step in performance with a parallel improvement
incircuit density. BCB advances our BiCMOS with O.8~ CMOS
feature sizes and improved interconnect capability resulting in
a significant performance step for CMOS logic. This will allow
implementation of mixed-signal circuits that support data transfer rates well beyond 200 MbiVs, while maintaining very low
power dissipation. The. dense digital advantages of BCB will
also expand the possibilities for cost effective customization
and programmability in both 5V and 3V environments.
BN. Low-power/8 GHz Bipolar at 5 volts
A noteworthy feature of a minimum. size BN process
transistor is that it's only about 1/5th the size of a minimum size
BK transistor. Because we employ full oxide isolation.in BN, we
can fabricate very fast, very small transistors and reduce
sidewall capacitances. This supports not only high speed, but
low power.
For a summary of our BiCMOS processes see Table 2.
The BN process features high-performance NPN transistors to support mixing high-performance emitter coupled logic
(ECL)with analog circuitry. To provide for strict TTL 1I0compatibility, we use superior PtSi Schottky diodes.
The resulting speed and packing density allows you to
effectively implement dense high-performance, low-power
Bipolar analog/digital capability into your system designs.
For a feature-by-feature comparison of Silicon Systems'
BK and BN Bipolar processes, see Table 3.
1-4
CUSTOM SOLUTIONS
<1< .
.....
i~rQ~s~ Typ~»
...•
APPli~ktiorl ....
. ypltage •. J:I'IDSS
CH
Si-Gate, single metal,
dual poly, PWell
12V
1BV
3.61J.
5.Bjl
6.41J.
nla
CG
Si-Gate, dual metal,
dual poly, PWell
5V
7V
1.51J.
3.01J.
4.51J.
6.01J.
• DDD SID structure
• Poly-poly capacitors
• Shrinkable to 1.21J.
CJ
Si-Gate, dual metal,
dual poly, NWell
5V
7V
1.01J.
2.01J.
3.01J.
3.31J.
• Ldd SID structure
• Poly-poly capacitors
• Shrinkable to O.BIJ.
CK
SI-Gate, dual metal,
dual poly, NWell
5V
7V
O.BIJ.
1.61J.
2.01J.
2.41J.
• Ldd SID structure
• Poly-poly capacitors
• Shrinkable to O.51J.
• DDD SID structure
• Poly-poly capacitors
• Low-voltage coefficient
• High n IOpoly resistors
• Epi substrate option
• Buried well-ring
TABLE 1: CMOS Process Chart
Dr~WJl
Gate· .
·i3YD!:iSbkigth
BCA:
BCB:
10V
5V
BV
1.01J.
O.BIJ.
2.61J.
1.6jl
2.0jl 2.01J. 2.41J.
Bipolar:
13GHz
3.21J. 3.Bjl 5.01J.
BV
15GHz
O.81J.
• High Performance NPNs
• Polysilicon emitters
• PtSi Schottky Diodes
• Poly resisters
• Gate Oxide Capacitors
• Poly Capacitors
• Sidewall Oxide Isolation
• Fuses
CMOS:
• Lightly Doped Drains
TABLE 2: BiCMOS Process Chart
...
. .•. . . . .•. . .
.J.> I.· « < . Emittef .>i\.1f>
p"~e!ls
Type
BK
Junction-isolated
12V
2 GHz
2.51J.
9.01J.
14.01J.
•
•
•
•
•
•
Polysilicon emitters
AI Schottky diodes
Nitride capacitors
Ion implanted resistors
Up/down junction isolation
Collector/base plugs
BN
Oxide-isolated
6V
BGHz
2.01J.
4.51J.
B.OIJ.
•
•
•
•
.•
•
High performance NPNs
PtSi Schottky diodes
Nitride capacitors
Ion implanted resistors
Sidewall oxide isolation
Collectorlbase plugs
. •.
.. .•. •
. BVbEC>
NPNF(
SizePi!ch
TABLE 3: Bipolar Process Chart
1-5
CUSTOM SOLUTIONS
Quality that delivers
A SUPERIOR FINISH FOR CMOS, BIPOLAR
ANDBICMOS
With effective systems such as PROMIS and our designfor-quality approach in place, Silicon Systems is prepared to
deliver you finished products you can really depend on. On
time. And within budget.
You might say this is the payoff window. The benefits of our
process technologies, design tools and our unique custom
approach all come together during wafer fabrication, test and
assembly.
For details on how you can take best advantage of Silicon
Systems' custom mixed-signal IC solutions, see your nearest
Silicon Systems representative, or contact us. Silicon Systems, Inc.
14351 Myford Road, Tustin, CA 92680-7022. 714-573-6000.
FAX: (714) 573-6914.
Our two manufacturing centers, located in Tustin and
Santa Cruz, California, can offer specialized capabilities to
match your particular fabrication requirements. Both facilities
provide you w~h high resolution stepper photolithography technology, positive resist, dry plasma etch systems, high current
ion implantation and automatic sputtering.
Fabrication sites in both Tustin and Santa Cruz accommodate
4-and 6-inch wafer fabrication and Bipolar, CMOS and BiCMOS
processes.
I
Design Spectlications ~
and Requirements
I
The right package
Silicon Systems offers a wide range of packages to meet
the small footprint requirements of advanced storage and
communication products. We continue to be innovative in
surface mount technology by providing PLCC, SO, VSOP,
VTSOP, OFP, TOFP, VTOFP and UTOFP packages. At our
ISO 9002-certified Singapore assembly & test facility we have
the full capability to support high qual~y automated packaging
while also maintaining rapid cycle times.
'*'
I Initial Design Review I
,
,
i
·
I
,
,
,
,
,
:I
Prom is. Quality through CAM
L
I
,
Process and Management Information System (PROMIS)
underscores our commitment to computer-aided manufacturing (CAM). And to delivering you a superior quality product on
time.
,
,
,
,
,
,
We use PROMIS to facilitate the data required in our
manufacturing, monitoring and statistical process control (SPC)
systems.
··,
,
,I
,
I
PROMIS also assists our SPC efforts, as does our commitment to fully train all of our manufacturing personnel in SPC
basics.
I
,
I
...
...
Final Layout Review
Test Program Creation
Photomask
Wafer Fab
Prototype
(Assembly, Test, Ship)
I
We design for quality
I
.
I
I
I
,
Final Review
Verify System Function
I
The results of such an effort are IC products that boast
lower defect rates, higher parametric performance and far
fewer redesigns. Moreover, our persistence in improving quality keeps us focused on finding better and faster ways to satisfy
future customer demands.
Evaluate Prototype
...
Release to Production
I
I
Customer Interface for Full-Custom
and Cell-Based Designs
1-6
...
• Automatic Placing
and Routing or
Hand-Packed Layout
• Automatic CircuH
Trace
,
With PROMIS we more effectively manage our inventory,
accurately track wafers in process, and closely monitor the
clean room environment.
It's our view that quality is nothing less than absolute
customer satisfaction. To achieve it, we begin far "upstream" in
the product development process. Our design-for-quality
approach scrutinizes the design itself with statistically based
models, comprehensive simulation tools and vigorous design
reviews.
Final Design Review
Design Componenls
• Schematic Capture
• Simulation
• Nellisting
I
Section
2
RELIABILITY &
QUALITY ASSURANCE
2
CONTINUOUS IMPROVEMENT
MISSION ~ OBJECTIVE
STATEMENT
Mission
Be the supplier of choice by exceeding customer expectations
through continuous improvements in our products. systems
and services.
Objectives
Provide world class quality in our products and services
through focus on:
Customer Partnering
Cycle Time Improvement
Process and System Improvements
Develop a culture that ensures the consistent use of continuous
improvement tools and fact based decision methodology by:
Senior Management Leadership
Employee Empowerment
Aggressive Goal Setting and Performance Measurement
Communication and Celebration of Successes
Alan V. King
",.,Ident. CEO
~!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
ilicon
Ji:
CheIYI A. Stock
Vice ",.,Ident. Cmpornte RA.QA
:DK ~.
2-0
Reliability and
Quality Assurance
SECTION 1
1.1
Our Reliability and Quality Assurance organizations are
committed to working closely with our customers to provide
assistance and acontinually improving level of product quality.
INTRODUCTION
Silicon Systems is committed to the goal of customer satis·
faction through the on·time delivery of defect free products
that meet the customer's expectations and requirements.
This section outlines Silicon Systems' ongoing activities for
the control and continual improvement of quality in every
aspect of our organization.
1.2
SILICON SYSTEMS' QUALITY MANDATE:
CONTINUOUS IMPROVEMENT
Continuous improvement is Silicon System's strategic thrust
for the 1990's. In order to ensure that all aspects of our
business are encompassed by this mandate, Corporate
Reliability & Quality Assurance has been chartered with the
responsibility for developing, educating and overseeing the
worldwide continuous improvement process. The continuous improvement initiative will lead to developing a new
organizational culture, changing attitudes and stronger ownership and accountability for total customer satisfaction.
Silicon Systems is diligently working to maintain and improve
its position as a world·class provider of mixed·signal inte·
grated circuits (MSICs®).
We realize and practice the concept that quality and reliability
must be designed and built into our products. In addition,
Silicon Systems utilizes rigid inspections and data analysis to
evaluate the acceptability and variation existing in incoming
materials and performs stringent outgoing quality verification. The manufacturing process flow is encompassed by an
effective system of test/inspection checks and in-line monitors which focus on the control and reduction of process
variation. These gates and monitors ensure precise adherence to prescribed standards and procedures.
1.3
CHARACTERISTICS OF SILICON SYSTEMS'
CONTINUOUS IMPROVEMENT PROCESS
Executive Steering Committee leadership and direction - defines the right things to do and provides
guidance - the right way to do them.
Continuous improvement is measured everywhere and
by everyone. Metrics that reflect pride in accomplishment are celebrated.
Silicon Systems also incorporates the use of statistical process control techniques into company operations. The control an\! reduction of the process variation by the use of
statistical problem solving techniques, analytical controls
and other quantitative methods ensures that Silicon Systems'
products maintain the highest levels of quality and reliability.
Benchmarking is employed as a method to shorten
learning curves and ensure successful ventures.
Quality management and employee empowerment are
encouraged at all levels.
~
f -",I_.M;;;;=.E:.::__oIl
-l__
_.
Sl.".g'P.o
..._
F.A. Lab
....
FIGURE 1: Organizational Chart
2-1
Reliability and
Quality Assurance
11 is the practice of Silicon Systems to have corporate quality
and reliability objectives encompass all of its activities. This
starts with a strong commitment of support from the corporate
level and continues with exceptional customer support long
after the product has been shipped.
Supplier partnership is a critical element of our quality
strategy.
This is· the essence of Silicon Systems - a total quality
involved company -forward looking and immersed in the goal
of customer satisfaction and best-in-class business pursuits.
1.4
Silicon Systems emphasizes the belief that quality and reliability must be built into all of its products by ensuring that all
employees are educated in the quality philosophy of the
company. Some of the features buill into Silicon Systems
quality culture include:
CORPORATE RELIABILITY AND
QUALITY ASSURANCE
It is the objective of the Corporate Reliability and Quality
Assurance organization to ensure that proactive quality
systems are inplaceto ensure that Silicon Systems'products
will meel or exceed customer requirements and expectations. In addition, the Reliability and Quality Assurance
Clrganization works to facilitate the timely implementation of
solutions and monitors the effectiveness of corrective actions. These organizational strategies support the continuing
enhancement of quality consciousness throughout Silicon
Systems.
1.5
ISO 9000 CERTIFICATION
Silicon Systems has determined that ISO 9000 certification
is an important strategy for achieving total customersatisfaction. Our Singapore assembly and test operations facility has
been ISO 9002 certified through SISIR and our domestic
facilities are currently in pursuit of this important industry
standard. We believe strongly that ISO 9000 certification
proves that Silicon Systems is doing the right things to do
things right.
1.
Structured training programs directed at wafer fabrication, test, process control personnel and supporting
organizations.
Team-based problem solving methodologies.
- Corporate-wide training of quality philosophy and
statistical methods.
2.
Stringent in-process inspection, gates, and monitors.
3.
Rigorous evaluation of designs, materials, and processing procedures.
4.
Stringent electricaitesting (1 00% and QC AQUSampie
testing).
5.
Ongoing reliability monitors and process verifications.
6.
Real-time use of statistical process control
methodology.
7.
Corporate level audits of manufacturing, subcontractors, and suppliers.
8.
Timely corrective action system.
9.
Control of non-conforming material.
These focused quality methods result in products which
deliver superior performance and reliability in the field.
SECTION 2: QUALITY ASSURANCE
2.1
2.2.1
QUALITY OBJECTIVES
INCOMING INSPECTIONS
Incoming inspection plays a key role in Silicon Systems'
quality efforts. Small variations in incoming material can
traverse the entire production cycle before being detected
much later in the process. By paying strict atlention to the
monitoring of materials at the earliest possible stage, variation can be reduced, resulting in a stable uniform process.
While all Silicon Systems employees have direct responsibility
for quality in their functions, the Quality Assurance Organizations have the ultimate responsibility for the reliable performance of our products. This is accomplished through the
development, administration and assessment offormal quality systems which assure Silicon Systems' management, as
well as our customers, that products will fulfill the requirements of customer purchase orders and all other specifications related to design, raw material and in process through
completion of the finished product.
2.2.2 IN-PROCESS INSPECTIONS
Silicon Systems has established key inspection monitors in
such strategic areas as wafer fabrication, wafer probe, assembly, and final test. These quality monitoring tests are
performed in addition to the intermediate and final inspections
found in the manufacturing process.
Corporate Quality Assurance supports, coordinates and actively participates in the formal qualification of suppliers,
material, processes, and products, and the administration of
quality systems and production monitors to assure that our
products meet Silicon Systems quality standards. Product
Quality Assurance provides the liaison between Silicon Systems and the customer for all product quality related concerns.
Quality control monitors have been integrated throughout the
manufacturing flow, so that data may be collected and analyzed to verify the results of intermediary manufacturing
steps. This data is used to document quality trends or long
term improvements in the quality of specific operations.
2-2
Reliability and
Quality Assurance
sign-related functions include ensuring that process spec~ication revisions are translated into updated design parameters and the translation of manufacturing process capability
into design guidelines. This is accomplished through the
identification and monitoring of critical process and device
parameters. Wafer level test at the early stages of process
development also plays a critical role. These elements,. included in Silicon Systems design for quality effort, support the
development of robust design rules which are as insensitive
as possible to inherent manufacturing variation. The result is
a product that delivers predictable and reliable long term
performance.
2.5
PPM REDUCTION PROGRAM
The primary purpose of a PPM reduction program is to
provide.a formalized feedback system in which data from
nonconforming products can be used to improve future
product consistency and reliability. The action portion of this
program is accomplished in three stages:
FIGURE 2
Quality Assurance Relationships
Quality Steering Committee
1.
Identification of defects by failure mode.
2.
Identification of defect causes and initiation of corrective
action.
3.
Measurement of results and setting of improved goals.
The data summarized from the established PPM program is
compiled as a ratio of units rejectedltested. This ratio is then
expressed in terms of defective parts per million (PPM).
Founded on a statistically valid database of PPM data and an
established five-year strategic plan identifying PPM improvement goals, Silicon Systems has consistently achieved excellent quality standards and will continue to progressively
improve PPM standards.
Abnormality control is being used to enhance the effectiveness of this process. In process monitors such as oxide
integrity, electromigration immunity and other parameters
monitor long term reliability as well as circuit performance.
2.3 QUAUTY STEERING COMMITTEE
The Corporate, Product and Manufacturing Quality Assurance organizations work closely together to provide leadership in the development, integration and assessment of
Silicon Systems' worldwide quality systems and procedures.
2.6
COMPUTER AIDED MANUFACTURING CONTROL
Computer Aided Manufacturing (CAM) is used throughout
Silicon Systems for the identification, control, collection and
dissemination of timely information for logistics control. Silicon Systems also uses this type of computerized system for
statistical process control and manufacturing monitoring.
PROMIS, (PROcess Management and Information System),
displays approved/controlled recipes, processes, and procedurils; tracks work-in-process;· reports accurate inventory
information; allows continuous recording of facilities data;
contains statistical analysis capabilities; and much more.
PROMIS allows for a paperless facility, a major element in
minimizing contamination of clean room areas.
This team approach ensures that policies and procedures are
standardized and facilitates rapid improvement in products,
processes and services.
2.4 DESIGN FOR QUAUTY
Since the foundation of a reliable product is rooted in the
design process, the Reliability and Quality Assurance organizations actively participate in comprehensive cross-functional reviews of design stages priortothe product's transition
to production status. These review stages assure a predictable and effective development cycle. Other important de-
2-3
II
Reliability and
Quality Assurance
TEST
Biased temperature/humidity
Highly accelerated stress test (HAST)
High temperature operating life (HTOll
Early Failure Rate
Steam pressure
Temperature cycling
Thermal shOck·
Salt atmosphere·
Constant acceleration
Mechanical shock
Solderability
lead integrity
Vibration, variable frequency
Thermal resistance
Electrostatic damage
latch-up
Seal fine and gross leak
CONDITIONS
B5°C/8So %RH
JDECA110
Mil 8830, Method 100S
. Mil 8830, Method 100S
121 CI1SPSI
Mil 8830, Method 1010
Mil 8830, Method 1011
Mil 8830, Method 1009
Mil 8830, Method 2001
Mil 8830, Method 2002
Mil 8830, Method 2003
Mil 8830, Method 2004
Mil 8830, Method 2007
Silicon Systems Method
Mil 8830, Method 301S
Silicon Systems Method
Mil Std 8830, Method 1014
Q
PURPOSE OF EVALUATION
Resistance to high humidity with bias
Evaluates package integrity
Resistance to electrical and thermal stress
Detect infant mortality
Resistance to hiQh humidity
Resistance to thermal excursion (airl
Resistance to thermal excursion (liquid)
Resistance to corrosive environment
Resistance to .constant acceleration
Resistance to mechanical shocks
Evaluates solderability of leads
Evaluates lead integrity before board assembly
Resistance to vibration
Evaluates thermal dissipation
Evaluates ESD susceptability
Evaluates latch-up susceptibility
Evaluates hermeticity of sealed packages
TABLE 1: Reliability Stress Tests
SECTION 3: RELIABILITY
3_1
3.3
Si\icon Systems has defined various programs that will
characterize product reliability levels on a continuous basis.
These programs can be categorically described by:
Table 1 lists reliability test methods that are in use at Silicon
Systems. This analysis of production monitor at Silicon
Systems provides valuable information on possible design!
process changes which assure continued improved reliabHity.
The monitors are periodically reviewed for effectiveness'and
imprc;lVements.
1.' Qualifications
Production monitors
2.
3.
4.:
5.
6.
:u
PRODUCTION MONITORS
This program has been established to randomly select a
statistically significant sample of. production products for
subjection to maximum stress test levels in order to evaluate
the useful life of the product in a field use environment.
RELIABILITY PROGRAM
Evaluations
Failure analysis
Wafer level reliability
Data collection and presentation for improvement
projects
3.4
EVALUATIONS
The evaluation program at Silicon Systems is an ongoing
effort that will continue defining standards which address the
reliability assessment of the circuit design, process parameters, and package of a new product. This program continuously analyzes updated performance characteristics of product as they undergo improvement efforts at Silicon Systems.
aVALIFICATIONS
Extensive qualification testing and data collection ensures
that ail new, product designs, processes, and packaging
configurations meet the absolute maximum rating's of design
and the worstcase performance criteria for endusers. A large
database generated by means of accelerated stress testing
results in.a high degree of confidence in predicting final use
performance. The qualification criteria used are periodically
reviewed to be consistent with Silicon Systems' Increasing
quality and reliability goals in support of our customers.
3.S
FAILURE ANALYSIS
The failure analysis function is an integral part of the Quality
and Reliability department at Silicon Systems. Silicon Systems has assembled a highly technical and sophisticated
failure analysis laboratory and staff. This laboratory provides
visual analysis, electrical reject mode arialysis, and both
2-4
Reliability and
Quality Assurance
destructive and non-destructive data to aid the engineers in
developing corrective action for improvement. These test
analyses may include metallurgical, optical, chemical, electrical, SEM with X-ray dispersive analysis, and E-Beam noncontact analysis as needed.
3.8
RELIABILITY METHODS
The Reliability Program utilizes a number of stress tests that
are presently being used to define performance levels of our
products. Many of these stress tests are per MIL-STD-883D
as shown in Table 1.
These conclusive in-house testing and analysis techniques,
are complemented by outside support, such as scanning
acoustic microscopy, focused ion beam, and complete surface and material analysis. This allows Silicon Systems to
monitor all aspects of product manufacturing to ensure that
the product of highest quality is shipped to our customers.
3.9
RELIABILITY PREDICTION METHODOLOGY
At Silicon Systems, the Arrhenius model is used to relate a
failure rate at an accelerated temperature test condition to a
normal use temperature condition.
The model basically states FR = A exp(-EalKT)
3.6
WAFER LEVEL RELIABILITY PROGRAM
Where:
A primary objective at Silicon Systems is to improve the
reliability of our products through characterization of our
manufacturing operations. The identification of specific failure
mechanisms occuring in the waferfabrication and assembly
processes is a prerequisite to effective corrective action
aimed at reducing defects and improving quality and reliability.
The primary advantage of wafer level reliability testing is the
speed at which results can be derived, thereby providing
additional response time and an early warning of process
changes. This tool provides Silicon Systems with a very rapid
analysis tool which allows for the early identification of
possible problems and a determination of their origin.
Failure rate
Constant
Ea
Activation Energy (eV)
K
Boltzmann's constant 8.62 x 10.5 eVI degree K
T
Absolute temperature (degree K)
SECTION 4:
4.1
ELECTROSTATIC DISCHARGE
PROGRAM
ESD PREVENTION
Silicon Systems recognizes that the protection of Electrostatic Discharge (ESD) sensitive devices from damage by
electrical transients and static electricity is vital. ESD safe
procedures are incorporated throughout all operations which
come in contact with these devices. Continuous improvement in the ESD protection levels is being accomplished
through the incorporation of increasingly robust protection
devices during the circuit design process as well as work area
improvements.
The continuous improvement approach taken at Silicon
Systems uses the wafer level reliability tests as tools to
improve the process, identify potential problems, determine
the sources of any process weakness and eliminate problems upstream in the process. This results in a focus on
reliability improvement that goes well beyond merely determining the projected lifetime of a product to a detailed
characterization, measurement and control of the specific
parameters which actuailly determine product lifetime.
3.7
FR
A
Silicon Systems' quality activity incorporates several protection measures forthe control of ESD. Some of the preventive
measures include handling of parts at static safe-guarded
workstations, the wearing of wrist straps during all handling
operations, the use of conductive lab coats in all test areas
and all areas which handle parts and the packaging of
components in conductive or anti-static containers.
DATA COLLECTION AND PRESENTATION FOR
IMPROVEMENT PROJECTS
Data collected from each element of the Reliability program
is summarized for scope and impact and distributed among
all engineering disciplines in the company. This data facilitates improvement and provides our customers an opportunity to review the performance of our product.
2-5
NOTES
2-6
Section
3
HDD READIWRITE
AMPLIFIERS
3
3-0
SSI 32R5281 AR
14-Channel Two-Terminal
Read/Write Device
July 1992
DESCRIPTION
FEATURES
The SSI 32R5281 AR Read/Write device is a bipolar
monolithic integrated circuit designed for use with twoterminal thin-film recording heads. It provides a low
noise read amplifier, write current control and data
protection circuitry for up to 14 channels. Power supply
fault protection is provided by disabling the write current generator during power sequencing. System write
to read recovery time is significantly improved by
controlling the read channel common mode output
voltage shift in the write mode. It requires +5V and
+12V power supplies and provides internal 7000
damping resistors. The 32R5281 AR offers power and
performance improvement over 32R5281 R.
• High performance:
Read mode gain = 250 VIV
Input noise 0.80 nV/-YHz max.
Input capacitance = 22 pF max.
Write current range 10 mA to 40 mA
Head voltage swing = 7 Vpp
Write current rise time = 9 ns
• Enhanced system write to read recovery time
=
=
• Differential Eel-like Write Data Input
• Power supply fault protection
• Write unsafe detection
• +5V, +12V power supplies
PIN DIAGRAM
BLOCK DIAGRAM
"'"
HOX
44
HOY
43
H13X
H1X
42
GNO
H1Y
H13Y
HS3
H'Y
I-l2X
H2V
H2X
H2Y
H3X
we
HOY
H3Y
ROY
H"
H4X
ROX
>lSY
"'"
HoY
H7X
"'"
HeX
HOY
H4Y
HSO
H5X
HS1
H5Y
HS2
H6X
vee
H6Y
WO
H7X
Wfj'
H7Y
WUS
Hex
GNO
HOY
HeY
VDD
H10X
H9X
H12Y
H10Y
H9Y
H12X
H10X
H11Y
H10Y
H11X
H"Y
44·lEADSOM
H13X
H13V
CAUTION: Use handling procedures necessary
for a static sensitive component
0792
3-1
SSI 32R5281 AR
14-Channel Two-Terminal
Read/Write· Device
CIRCUIT OPERATION
READ MODE
The read mode configures the SSI32R5281 R as a low
noise differential amplifier and deactivates the write
current generator and write unsafe detection circuitry.
The RDX and RDY outputs are emitter followers and
are in phase with the "X" and "Y" head ports. These
outputs should be Ae coupled to the load. The RDX,
RDY common mode voltage is maintained at the write
mode value, minimizing the transient between write
mode and read mode, substantially reducing the write
to read recovery time in the subsequent Pulse Detection circuitry.
The SSI32R5281AR addresses up to 14 two-terminal
thin film heads providing write drive or read amplification. Head selection and mode control is accomplished
with pins HSn, es and R/W, as shown in Tables 1 &~
Internal resistor pullups, provided on pins es and R/W
will force the device into a non-writing condition if either
control line is opened accidentally.
WRITE MODE
The write mode configures the SSI 32R5281AR as a
current switch and activates the Write Unsafe (WUS)
detection circuitry. Write current is toggled between
the X and Y direction of the selected head on each low
to high transition on the WD, Write Data input. (See
figure 1.)
IDLE MODE
The idle mode deactivates the internal write current
generator, the write unsafe detector and switches the
RDX, RDY outputs into a high impedance state. This
facilitates multiple device applications by enabling the
read outputs to be wire-OR'ed and the write current
programming resistor to be common to all devices.
A preceding read operation initializes the Write Data
Flip Flop (WDFF) to pass write current in the Xdirection of the head, i.e., into the X-port of the head.
HnX will be biased higher than HnY.
TABLE 1: Mode Select
The magnitude of the write current (O-pk) is given by:
Iw= Vwc
Rwc
where Vwc (We pin voltage) = 1.65V ± 5%, is programmed by an external resistor Rwc, connected from
pin we to ground. In multiple device applications, a
single Rwc resistor may be made common to all devices. The actual head current lx, y is given by:
RlW
0
0
1
0
1
0
1
1
MODE
Write
Read
Idle
Idle
TABLE 2: Head Select*
Ix y
Iw
,
1 +RhlRd
where:
Rh = head resistance + external wire resistance, and
Rd = damping resistance.
Power supply fault protection improves data security
by disabling the write current generator during a voltage fault or power supply sequencing. Additionally, the
write unsafe detection circuitry will flag any of the
conditions listed below as a high !evel on the open
collector output pin, WUS. Up to two positive transitions on the WD, Write Data input line, after the fault is
corrected, are required to clear the WUS flag.
• WD frequency too low
• Device not selected
• Open head
cs
HS3
HS2
HS1
HSO
HEAD
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
B
9
10
1
1
0
1
11
12
13
1
1
1
1
0= Low level
• Device in read mode
• No write current
1
1
1
1
0
0
0
0
1
1
0
0
1 = High level
*Unused heads should be left open.
3-2
SSI 32R5281 AR
14-Channel Two-Terminal
ReadlWrite Device
PIN DESCRIPTION
NAME
TYPE
DESCRIPTION
HSO- HS3
I
Head Select
CS
I
Chip Select: a low level enables the device
RIW
I
ReadlWrite: a high level selects Read mode
WUS
O·
Write Unsafe: Open collector output, a high level indicates an unsafe writing
condition
I
Differential Write Data inputs: a positive transition on WD toggles the direction
of the head current
WD,WD
HOX - H13X
HOY - H13Y
1/0
RDX,RDY
O·
X, Y Head Connections: Current in the X-direction flows into the X-port
WC
.
Write Current: used to set the magnitude of the write current
VCC
-
+5V Logic Circuit Supply
X, Y Read Data: differential read data output
VDD
-
~12V
GND
-
Ground
·When more than one RIW device is used, these signals can be wire OR'ed.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may permanently damage the device.
PARAMETER
SYMBOL
DC Supply Voltage
RATING
VDD
-0.3 to +13.5 VDC
VCC
-0.3 to +6 VDC
Write Current
Iw
100 rnA
Digital Input Voltage
Vin
-0.3 to VCC +0.3 VDC
Head Port Voltage
Differential Port Voltage
VH
IHnX - HnYI
WUS Pin Voltage Range
Output Current
RDX, RDY
WUS
Storage Temperature
-0.3 to +8 VDC
~VH
6VDC
Vwus
-0.3 to VCC VDC
10
-10 rnA
Iwus
+12mA
Tstg
-65 to + 150°C
3-3
SSI 32R5281 AR
14-Channel Two-Terminal
ReadlWrite Device
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
DC Supply Voltage
RATING
VDD
12± 10% VDC
VCC
5±10% VDC
Tj
+25 to +135°C
Operating Temperature
.
DC CHARACTERISTICS
Unless otherwise specHied, recommended operating conditions apply.
MIN
NOM
MAX
UNITS
-
36
TBD
mA
25+lw
TBD
mA
3
TBD
mA
Read Mode
-
22
TBD
mA
Write Mode
-
14
TBD
mA
Idle Mode
-
10
TBD
mA
540
700
mW
PARAMETER
CONDITIONS
VDD Supply Current
Read Mode
Write Mode
VCC Supply Current
.
Power Dissipation (Tj = + 135°C)
Idle Mode
Read Mode
Write Mode
Idle Mode
WD, WD Input Low Current (ilL 1)
VIL 1 = vec -1.625V
WD, WD Input High Current (IIH1)
VIH1 = VCC -0.72V
WD, WD Input Low Voltage (VIL1)
WD, WD Input High Voltage (VIH1)
R/W, CS, HSO-HS3
Input Low Current (IIL2)
VIL2= 0.8V
RlW, CS, HSO-HS3
Input High Current (IIH2)
VIH2= 2.0V
-
375+10.350lw 490 +l1.60lw
85
WUS Output Low Voltage (VOL)
110
mW
80
100
.!lA
!lA
VCC
VCC
VDC
-1.870
-1.625
VCC
VCC
-1.00
-0.720
-0.4
100
!lA
0.8
VDe
VDC
2.0
-
101=8 mA
VDD Fault Voltage
9.0
3.5
vce Fault Voltage
3-4
VDC
mA
RIW, CS, HSO-HS3
Input Low Voltage (VIL2)
R/W, CS, HSO-HS3
Input High Voltage (VIH2)
mW
.
-
0.5
VDC
-
10.3
VDC
4.2
VDC
SSI 32R5281 AR
14-Channel Two-Terminal
Read/Write Device
DC CHARACTERISTICS (continued)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
Head Current (HnX, HnY)
Write Mode,
~ VCC ~ 3.5V
~ VDD ~9.0V
-200
-
+200
~
Read/Idle Mode,
-200
-
+200
~
o
o
o ~VCC~5.5V
o ~ VDD ~13.2V
WRITE CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply, Iw = 20 mA, Lh = 500 nH, Rh = 30il
and f(WD) = 5 MHz.
~ Iw~40
1.57
1.65
1.73
Differential Head Voltage Swing
7
Vpp
-
-
-
Unselected Head Current
1
mA(pk)
Differential Output Capacitance
-
-
25
pF
500
700
950
il
WUS = low
1.7
-
-
MHz
WUS = high
-
-
500
kHz
10
-
40
mA
WC Pin Voltage (Vwc)
10
mA
Differential Output Resistance
WDI Transition Frequency
Write Current Range
V
READ CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply CL (RDX, ROY) < 20pF and
RL (RDX,RDY) = 1 kil.
PARAMETER
Input Noise Voltage
MIN
NOM MAX
UNITS
Vin= 1mVpp @ 300 kHz
210
250
290
VN
-idB
IZsl<5il, Vin=i mVpp
25
40
-3dB
IZsl<5il, Vin=i mVpp
35
55
-
MHz
-
0.57
0.80
nV/"fHz
Differential Voltage Gain
Bandwidth
CONDITIONS
BW = 15 MHz, Lh = 0, Rh = 0
MHz
Differential Input Capacitance
Vin - 1 mVpp~ f - 5 MHz
-
15
22
of
Differential Input Resistance
Vin = 1 mVpp, f = 5 MHz
300
565
-
n
Dynamic Range
Peak-to-peak AC input voltage
where gain falls to 90% of its
small signal value, f = 5 MHz
2.0
-
-
mVpp
Common Mode Rejection Ratio
Vem = 100 mVpp AC Coupled @ 5 MHz
54
-
-
dB
-
dB
-
dB
Power Supply Rejection Ratio
100 mVpp @ 5 MHz on VDD
100 mVpp @ 5 MHz on VCC
54
-
Channel Separation
Unselected channels driven
with 100 mVpp @ 5 MHz,
Vin = 0 mVpp
45
-
3-5
II
SSI32R5281 AR
14-Channel Two-Terminal
ReadlWrite Device
READ CHARACTERISTICS (continued)
PARAMETER
:'
CONDITIONS
:
Output Offset Voltage
MIN
NOM
MAX
UNITS
-400
-
+400
mV
RDX, ROY Common Mode
Output Voltage
Read Mode or Write Mode Vcc-2.5 Vcc - 2.1 Vcc-1.7
Single Ended Output Resistance
f = 5 MHz
Output Current
AC Coupled. Load,
RDXto ROY
VDC
-
-
30
0
3.2
-
-
mA
SWITCHING CHARACTERISTICS (See Figure 1)
Unless otherwise specified, recommended operating conditions apply, Iw = 20 rnA, Lh =' 500 nH, Rh = 300
and f(WD) = 5 MHz.
PARAMETER
CONDITIONS
MIN
MAX
UNITS
RIW
R/W to Write Mode
Delay to 90% of write current
-
'0.6
~
RlW to Read Mode
Delay to 90% of 100mV 10MHz
Read signal envelope or to 90%
decay of write current
-
0.6
~
CSto Select
Delay to 90% of write current or to
90% of 100mV 10MHz Read
signal envelope
-
0.6
~
CS to Unselect
Delay to 90% of write current
-
0.6
~
Delay to 90 % of 100mV 10MHz
Read signal envelope
-
0.4
~
Safe to Unsafe - TD1
0.6
2.0
~
Unsafe to Safe - TD2
-
1
~
CS
HSn
;
'.
HSO, 1, 2, 3 to any Head
WUS
Head Current
Prop. Delay - TD3
From 50 % points, Lh=OIJ,h, Rh=OO
-
32
ns
Asymmetry
WD has 50 % duty cycle and
1ns riselfall time, Lh=OIJ,h, Rh=OO
-
0.5
ns
Rise/Fall Time
10% - 90% points, Lh=OJ,Lh; Rh=On
-
9
ns
:
3-6
SSI 32R5281 AR
14-Channel Two-Terminal
Read/Write Device
TD1 _____
ir----
HEAD
CURRENT
Ilx -Iy)
FIGURE 1: Write Mode Timing Diagram
APPLICATIONS INFORMATION
The specifications, provided in the data section, account for the worst case values of each parameter taken
individually. In actual operation, the effects of worst case conditions on many parameters correlate. Tables 3 &
4 demonstrate this for several key parameters. Notice that under the conditions of worst case input noise, the
higher read back signal resulting from the higher input impedance can compensate for the higher input noise.
Accounting for this correlation in your analysis will be more representative of actual performance.
TABLE 3: Key Parameters Under Worst Case Input Noise Conditions
PARAMETER
Tj
Input Noise Voltage (Max.)
=25°C
Tj
TBD
=135°C
UNITS
0.80
nV/,!Hz
Differential Input Resistance (Min.)
TBD
TBD
Q
Differential Input Capacitance (Max.)
TBD
TBD
pF
TABLE 4: Key Parameters Under Worst Case Input Impedance Conditions
PARAMETER
Tj
=25°C
Tj
=135°C
UNITS
Input Noise Voltage (Max.)
TBD
TBD
nV/-,JHz
Differential Input Resistance (Min.)
TBD
TBD
Q
Differential Input Capacitance (Max.)
TBD
TBD
pF
3-7
SSI 32R5281 AR
14-Channel Two-Terminal
Read/Write Device
PACKAGE PIN DESIGNATIONS
THERMAL CHARACTERISTICS: 9ja
(Top View)
44-Lead SOM
HOX
H13Y
HOY
H13X
H1X
GNO
H1Y
HS3
H2X
"(;S
H2Y
RiW
H3X
we
H3Y
ROY
H4X
ROX
H4Y
HSO
H5X
HSl
H5Y
HS2
H6X
vee
H6Y
WO
H7X
WO
H7Y
WUS
H8X
GND
H8Y
VDD
H9X
H12Y
H9Y
H12X
Hl0X
HllY
Hl0Y
HllX
44-Pin SOM
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Mytord Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1992 Silicon Systems, Inc.
3-8
0792
SSI 32R1203A11203AR
+5V, 4-Channel, 3-Terminal
Read/Write Device
January 1994
DESCRIPTION
FEATURES
The SSI32R1203A is a bipolar monolithic integrated
circuit designed for use with center-tapped ferrite or
MIG recording heads. It provides a low noise read path
with a gain of 250 VN, write current control, and data
protection circuitry for as many as 4 channels. Power
supply fault protection is provided by disabling the write
current generator during power sequencing. A Power
Down mode (Idle) is provided to reduce power
consumption to less than 10 mW.
•
•
The $SI 32R1203A requires only a +5V power supply
and is available in a surface mount package.
•
•
•
+5V only power supply
Low power
- Pd :5 225 mW Read mode
- Pd :510 mW Idle mode
High Performance
- Input noise 1.2 nV,--JHz max.
- Input capacitance 19 pF max.
- Write current range 15 - 50 mA
- Head voltage swing 6.0 Vpk
250 VN read gain
=
=
=
=
Designed for center-tapped ferrite or MIG
heads
•
Power supply fault protection
•
Includes write unsafe detection
•
Enhanced Write to Read recovery
BLOCK DIAGRAM
vee
GND
wus
PIN DIAGRAM
veT
GND
HOX
HOY
~Ii".
ROX
H1X
ROY
H1Y
HOX
2
20
C"S"
19
RiW
18
we
HOY
3
H1X
4
H1Y
5
32R1203A
17
4
Channels
16
H2X
6
15
H2Y
7 .
14
HS1
H3X
8
13
VCC
H3Y
9
12
WDI
VCT
10
11
WUS
ROY
RDX
HSO
H2X
H2V
20-Lead .SOL, SOY
H3X
H3Y
CAUTION: Use handling procedures necessary
for a static sensitive component.
0194 - rev
3-9
SSI 32R1203A/1203AR
+5V, 4-Channel,3-Terminal
Read/Write Device
FUNCTIONAL DESCRIPTION
READ MODE·
WRITE MODE
In Read Mode, (R/W high and CS low), the circuit
functions as a low noise gain selectable differential
amplifier. The read amplifier input terminals are
determined by the Head Select inputs. The read amplifier
outputs (ROX, ROY) are emitter follower sources,
providing low impedance outputs. The amplifier polarity
is non-inverting between HnX, HnY inputs and ROX,
ROY outputs.
A source of recording current is provided to the head
center tap by an internal voltage reference, VCT. The
current is conducted through the head alternately into
an HnX terminal or an HnY terminal according to the
state of an internal flip-flop. The flip-flop is triggered by
the negative transition of the Write Data Input line
(WOI). A preceding Read mode selection initializes the
write data flip-flop, WOFF, to passwritecurrentthrough
the "X" side of the head. The write current magnitude is
determined by the value of an external resistor Rwc
connected between WC terminal and GNO, and is
given by:
IDLE MODE
Taking CS high selects the Idle mode which switches
the ROX and ROY outputs into a high impedance state
and deactivates the device. Power consu mption in this
mode is held to a minimum.
Iw = K/Rwc. where K = Write Current Constant
MODE SELECTION AND INDICATION CIRCUIT
WRITE MODE FAULT DETECT CIRCUIT
Logical control inputs which select mode and head
channel are TTL compatible. Their functions are
described in Table 1 and Table 2.
Several circuits are dedicated to detecting f~lUlt
conditions associated with the Write mOde. A logical
high level will be present at the Write Unsafe (WUS)
terminal if any of the following write fault conditions are
present:
TABLE 1: Head Select Table
Head Selected
HS1
HSO
Head center tap open
0
0
0
Head shorted
1
0
1
Head shorted to ground
2
1
0
No write current
3
1
1
•
•
•
•
•
•
WOI frequency too low
•
Device in Read or Idle mode
Head open
TABLE 2: Mode Select Table
Selected
Mode
Mode
Select
The Write Unsafe output is open-collector and is usually
terminated by an external resistor connected to VCC.
Two negative transitions on WOI, after the fault is
corrected, will clear the WUS flag.
A safe condition, WUS low, requires alternating voltage
spikes on both HnX and HnY that exceed VCT + 1.5V
at a rate equal to or higher than the Minimum Rate of
WOI for Safe condition.
In addition, the power su pply voltage level is monitored
by a circuit that inhibits the write current if VCC is too
low to permit valid data recording.
3-10
CS
R/W
1
X
Indicating &
Fault Outputs
WUS
Idle
high
0
1
Read
high
0
0
Write
active
SSI 32R1203A/1203AR
+5V, 4-Channel, 3-Terminal
Read/Write Device
PIN DESCRIPTION
NAME
TYPE
DESCRIPTION
HSO, HS1
I'
Head Select: Logical combinations select one of four Heads. See Table 1
CS
I
Chip Select: a low level enables device. Has internal pull-up resistor.
R/W
I'
Read/Write: a high level selects Read mode. Has internal pull-up resistor.
WUS
0'
WDI
I'
HOX-H3X
HOY-H3Y
I/O
RDX,RDY
0'
Write Unsafe: a high level indicates an unsafe writing condition.
Write Data In: negative transition toggles direction of head current.
X, Y head connections
X, Y Read Data: differential read signal output.
WC
-
VCT
-
Voltage Center Tap: voltage source for head center tap.
VCC
-
+5V
GND
-
Ground
Write Current: used to set the magnitude of the write current.
, When more than one R/W device is used, these signals can be wire OR'ed with unselected R/W devices.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
All voltages referenced to GND. Currents into device are positive.
PARAMETER
RATING
DC Supply Voltage
VCC
Digital Input Voltage Range
HS1, HSO, WDI, R/W, CS
-0.3 to +6 VDC
-0.3 to (VCC + 0.3 VDC)
Head Port Voltage Range
VH
-0.3 to (VCC + 3.0 VDC)
-0.3 to (VCC + 0.3 VDC)
Write Current Pin Voltage
Vwc
WUS Pin Voltage Range
Vwus
Write Current Zero-Peak
IW
60mA
RDX, ROY Output Current
10
-10 mA
RDX, ROY Pin Voltage
-0.3 to +6.0 VDC
VCC + 0.3 VDC
IveT
VCT Output Current Range
-60 mA to +10 mA
WUS Output Current Range
Iwus
-0.1 mA to +10 mA
Storage Temperature Range
Tstg
-65 to 150°C
Package Temperature (20 sec Reflow)
215°C
3-11
SSI 32R1203A/1203AR
+5V, 4-Channel,3-Terminal
Read/Write Device
ELECTRICAL SPECIFICATIONS (continued)
RECOMMENDED OPERATION CONDITIONS
CONDITIONS
PARAMETER
DC Supply Voltage
VCC
MIN
NOM
MAX
UNITS
4.75
5.0
5.25
VDC
15
j.tH
1
Head Inductance
Lh
Write Current Range
IW
15
50
mA
Junction Temperature Range Tj
+25
+135
°C
44
mA
mA
DC CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply.
POWER SUPPLY
VCC Supply Current (ICC)
Read Mode
33
1.4
2.0
Write Mode
31 + Iw
44+ Iw
mA
Read Mode
165
227
mW
7
10.5
mW
155 +
51w
230 +
5.51w
mW
0.8
VDC
Idle Mode
Power Dissipation
Idle Mode
Write Mode
DIGITAL 1/0
Input Low Voltage
CS, RiiN WDI, HSO, HS1
VIL
Input High Voltage
CS, R/W WDI, HSO, HS1
VIH
Input Low Current
CS, R/W WDI, HSO, HS1
ilL
VIL = O.4V
Input High Current
CS, R/W WDI, HSO, HS1
IIH
VIH = 2.7V
WUS Output Low Voltage
WUS Output High Current
VOL
IOH
2.0
VDC
-0.4
mA
20
jJA
IOL = 4.0 mA
0.5
VDC
VOH = 5.0V
100
jJA
3-12
SSI 32R1203A/1203AR
+5V, 4-Channel, 3-Terminal
Read/Write Device
WRITE MODE
PARAMETER
Center Tap Voltage
CONDITIONS
VCT
Head Current (per side)
Write Mode, Voltage Fault
o::;VCC ::;3.9V
1.0 kQ::; Rwc::; 3.3 kQ
Write Current Range
MIN
Write Mode/Idle Mode
Write Current Constant "K"
NOM
MAX
Vcc - 0.9
-200
Iwc to Head Current Gain
VOC
200
15
46
50
rnA
54
mA-kQ
mNmA
85
ROX, ROY Common Mode
Output Voltage
Vcc - 3
!lA
50
20
Unselected Head Leakage Current
UNITS
Vcc - 2.4 Vcc - 2
!lA
VOC
WOI Minimum Pulse Width
PWH VIL ;::: 0.2V
11
ns
See Figure 1
PWL VIN ;::: 2.4V
4
ns
Vee - 1.5
VOC
READ MODE
Center Tap Voltage
VCT
Input Bias Current (per side)
From VCT to HnX or HnY
Output Offset Voltage
ROX - ROY
-200
Common Mode Output Voltage
ROX + ROY
2
2
Common Mode Output Voltage
Change from Write to Read Mode
20
-100
FAULT DETECTION CHARACTERISTICS
Unless otherwise specified recommended conditions apply, Iw
Minimum Rate of WOI Input for
Safe condition
Vee - 2.4
60
!lA
+200
mV
3.5
VOC
+100
mV
= 30 rnA, Lh = 51lH, F(WOI) = 10 MHz.
150
Maximum Rate of WDI Input for
Unsafe condition
kHz
50
Minimum voltage value for
guaranteed write current turn-on
4.4
Maximum voltage value for
guaranteed write current turn-off
VOC
3.9
3-13
kHz
VOC
551 32R1203A/1203AR
+5V, 4-Channel, 3-Terminal
Read/Write Device
ELECTRICAL SPECIFICATIONS (continued)
DYNAMIC CHARACTERISTICS AND TIMING
Unless otherwise specified, recommended operating conditions apply and Iw = 30 mA, Lh = 5
f(WDI) = 5 MHz, CL(RDX, ROY) ::;; 20 pF.
~H,
WRITE MODE
PARAMETER
CONDITIONS
Differential Head Voltage Swing
Unselected Head Transient Current
MIN
NOM
6.0
6.4
1 ~H ::;; Lh ::;; 9.5 ~H
(1203AR only)
600
UNITS
V(pk)
2
Differential Output Capacitance
Differential Output Resistance
MAX
mA(pk)
15
pF
960
.0
300
V/V
READ MODE
Vin = 1 mVrms @ 1 MHz
200
Bandwidth (-3dB)
Ilsi < 5.0, Vin = 1 mVpp
30
Input Noise Voltage
BW= 15 MHz,
Lh = 0, Rh = 0
Differential Input Capacitance
Vin = 1 mVrms,
Differential Voltage Gain
f
= 5MHz
Differential Input Resistance
60
MHz
0.85
1.2
16
19
2
Dynamic Range
AC input voltage where
gain falls to 90% of its
small signal gain value,
f =5 MHz
2
Common Mode Rejection Ratio
Vcm = 100 mVpp@
1 MHz < f < 10 MHz
50
Power Supply Rejection Ratio
t;.Vcc =100 mVpp@
1 MHz < f < 10 MHz
45
Channel Separation
Unselected Channels:
Vin = 20 mVpp
1 MHz < f < 10 MHz
45
RDX, ROY Single Ended Output
Resistance
Output Current
250
3-14
±1.5
pF
k.o
mVpp
dB
75
dB
54
dB
30
AC Coupled Load,
RDXto ROY
nV/-vHz
.0
mA
SSI 32R1203A/1203AR
+5V, 4-Channel, 3-Terminal
Read/Write Device
SWITCHING CHARACTERISTICS
PARAMETER
CONDITIONS
NOM
MAX
UNITS
R/W
Read to Write
R/W to 90% of write current
50
400
ns
Write to Read
R/Wto 90% of
100 mV 10 MHz read signal
envelope or to 10% IW
0.15
1.0
!lS
Unselect to Select
CS to 90% of 100 mV 10 MHz
read signal envelope
1.0
2.0
!lS
0.05
0.6
!lS
0.6
!lS
CS
Select to Unselect
CS to 10% Ih
HSO, 1 to any Head
WUS
MIN
To 90% of 100 mV 10 MHz
read signal envelope
Safe to Unsafe (TD1)
Unsafe to Safe (TD2)
Head Current
(1203A only)
3.5
20
!lS
(1203AR only)
7.0
30
!lS
350
ns
40
ns
2
ns
20
ns
Write mode, after fault
cleared after 2nd transition
Rh = 0, Lh = 0
Prop. Delay (TD3)
From 50% points
Asymmetry
WDI has 50% Duty Cycle
and 1 ns Rise/Fall Time
Rise/Fall Time
10% - 90% Points
25
4
PWV
~
WDI
-+
wus
-..
r
TD1
TD2
<4-TD3
HEAD
CURRENT
( Ix-Iy)
* measured at 1.5V
FIGURE 1: Write Mode Timing Diagram
3-15
..
SSI 32R1203A/1203AR
+5V, 4-Channel, 3-Terminal
Read/Write Device
+5V
see Note 2
VCT
1..------<>------1 wus
, - - - - - - - - - - - - j - - j - - - ' ' ' ' - - - , see Note 1
SSI 32R1203A
RDX
READ
DATA
H3X
SSI32P549 READ DATA PROCESSOR
H3Y
----------------------------------------------~HSn
WC
GND
Rwe
see Note 3
NOTES
1.
2.
3.
Limit DC current from RDX and RDYto 100 J.IA and load capacitance t020 pF. In mUlti-chip application
these outputs can be wire-OR'ed.
The power bypassing capacitor must be located close to the 32R1203A with its ground returned directly
to device ground, with as short a path as possible.
To reduce ringing due to stray capacitance this resistor should be located close to the 32R1203A.
Where this is not desirable a series resistor can be used to buffer a long WC line.
FIGURE 2: Applications Information
3-16
SSI 32R1203A/1203AR
+5V, 4-Channel, 3-Terminal
Read/Write Device
PACKAGE PIN DESIGNATIONS
THERMAL CHARACTERISTICS: 9jA
(Top View)
20-Lead SOL, SOY
GNO
96° CIW
20
HOX
2
HOY
3
H1X
I
4
32R1203A
4
19
RNl
18
WC
17
ROY
Channels
H1Y
5
16
ROX
H2X
6
15
HSO
H2Y
7
14
HS1
H3X
8
13
VCC
H3Y
9
12
WOI
VCT
10
11
WUS
20-Lead SOL, SOY
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
ORDERING NUMBER
SSI32R1203A
20-Lead SOL
20-Lead SOY
SSI32R1203AR
20-Lead SOL
20-Lead SOY
PACKAGE MARK
SS132R1203A-CL
SS132R1203A-CV
SS132R1203A-CL
SS132R1203A-CV
SSI32R1203AR-CL
SSI32R1203AR-CV
SSI 32R1203AR-CL
SSI 32R1203AR-CV
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
0194- rev
3-17
©1993 Silicon Systems, Inc.
Notes:
3-18
SSI32R1510BR
MR Head Read/Write Device
"Miliilmt,';;,6iit.".
December 1993
DESCRIPTION
FEATURES
The 551 32R 151 OBR is an integrated circuit designed
for use with Magneto-Resistive recording heads. It
provides a write driver and a low noise read amplifier for
up to 8 channels. The device requires + 12V and +5V
power supplies and comes in a 68-pin PLCC package.
•
Head Swing
•
Rise Time
•
Minimal external components
•
Input Noise = 0.72
= 7.0 Vpp min
= 4 ns (Typ)
nV/" Hz
BLOCK DIAGRAM
VDD VCC
+12V +5V
GND
wus
FUiAW
RC
rl
CN1
CN2
cB1Xr-1~ CB1Y
SSI 32R151 OBR
MR Head Read/Write Device
FUNCTIONAL DESCRIPTION
that WUS does not necessarily turn on to flag a power
supply fault condition.
The SSI 32R1510BR addresses up to 8 MR heads
providing write drive or read amplification and MR
current biasing. Head selection and mode control is
accomplished with pins HSn, es and R/W as shown in
Tables 1 and 2.
WRITE MODE
Taking both es and RIW low selects Write mode which
configures the 32R1510BR as a current switch and
activates the Write Unsafe (WUS) detect circuitry.
Head current direction corresponds to the write data
input level (WDX, WDY).
READ BIAS ACTIVE IN WRITE (RBAW)
The RBAW pin is a TIL control signal. A low level
enables the MR bias current through the selected head
in Write mode (Table 3). It can be used to speed up the
write to read transition time. RBAWtiming is shown in
Figure 2.
READ MODE
Taking es low and RIW high selects Read mode which
activates the bias current generator and the differential
amplifier. The magnitude of the bias current is given by:
The magnitude of the write current is given by:
Iw= Vwc/Rwc
Ib = Ar • Vrc/Rrc
= Kr/Rrc
Rwc is connected from pin we to GND. Note the actual
head current Ihead is given by:
Ihead = Aw • Iw/(1 +Rh/Rd)
where Ar is the bias current gain and Kr is the product
of Ar and Vrc. Rrc is connected from pin Re to GND.
where Aw is the write current gain, Rh is the head
resistance, and Rd is the damping resistance.
WRITE MODE FAULT DETECT CIRCUIT (WUS)
Any of the following conditions will be indicated as a
high level on the Write Unsafe, WUS open collector
output:
WDI frequency too low
Device in Read or Idle mode
Head open
Head short to ground
No Head current
A voltage monitor, VMF, is provided for media biasing.
In Read mode its output is set at the head bias voltage
Vmr. When VMF sources over 7.5 mA, the chip assumes the media is not biased correctly, then the
device turns off Read mode, and WUS flags low to
indicate incorrect media biasing.
RDX and RDY are open collector outputs and should
be terminated with 100n load resistors.
IDLE MODE
In the case of a head short to ground, write current will
be turned off to prevent excessive current dissipation.
This will result in a pulsating WUS signal.
Taking es high selects Idle mode which switches the
RDX and RDY outputs into a high impedance state and
deactivates the internal write current source. This
facilitates multi-device installations by allowing the
read outputs to be wire OR'ed.
LOW VOLTAGE FAULT PROTECT
APPLICATION CAUTION
The voltage fault detection circuit improves data security by disabling the write current generator during a low
voltage fau It or power startup regardless of mode. Note
Care should be used when powering up the
32R1510R. An ESD protection diode is connected
between vee and VDD on the chip. If vee is powered
up before VDD, the ESD diode can suffer irreversible
breakdown and damage the device permanently.
TABLE 1: Mode SelectNMF Select
CS
R/W
VCTRL
MODE
0
0
X
Write
Dummy Head Center Voltage
0
1
X
Read
Selected Channel Center Voltage
1
X
0
Idle
High Impedance
1
X
1
Idle
Dummy Head Center Voltage
3-20
VMFVALUE
551 32R151 OBR
MR Head Read/Write Device
TABLE 3: Read Bias Active in Write
TABLE 2: Head Select
Head
HS2
HS1
HSO
Selected
0
1
2
3
4
5
6
7
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
MODE
R/W
RBAW
MR Head Bias Current
Read
1
X
On
Write
0
0
On
0
1 or Open
Off
1
1
1
0
1
PIN DESCRIPTION
CONTROL INPUT PINS
NAME
TYPE
DESCRIPTION
CS
I
Chip Select Input. A logical low level enables the circuit for a read or write
operation. Has internal pull up.
R/W
I
Readlwrite select. A logical low level enables the Write mode (when CS is
low). Has internal pull up.
VCTRL
I
Voltage Control. In Idle mode, a high level selects VMF to supply a bias
value. A low level selects high impedance.
RBAW
I
Read Bias Active In Write. A TTL low level enables the MR bias current
through the selected head in both Read & Write modes.
HSO, HS1,
HS2
I
Head select inputs. Logical combinations select one of eight heads.
See Table 2. Has internal pull down resistors.
HROX - HR7X
HROY - HR7Y
I
MR read element X, Y connections.
HWOX-HR7X
HWOY - HR7Y
0
MR write element X, Y, connections
HEAD TEMINAL PINS
DATA INPUT/OUTPUT PINS
WDX, WDY
I
Differential write data input.
RDX,RDY
0
Differential Read Data output. These open collector outputs are normally
terminated in 100Q resistors to VCC.
EXTERNAL COMPONENT CONNECTION PINS
WC
I/O
Resistor connected to GND to provide desired value of write current.
RC
Resistor connected to GND to provide selected value of bias current.
CN1, CN2
Noise decoupling capacitor for MR bias source.
CB1X, CB1Y
CB2X, CB2Y
DC blocking capacitors.
3-21
SSI32R1510BR
MR Head Read/Write Device
PIN DESCRIPTION
(continued)
CIRCUIT MONITOR PINS
NAME
TYPE
DESCRIPTION
WUS
0
Write Unsafe is an open-collector output with the off-state indicating that
conditions are not proper for a write operation.
WSV
0
0
0
Write Select Verify. Indicates that write current generator is active.
IMF
VMF
Current Monitor. Sinks 3 rnA of current when device is actiive.
Voltage Monitor. Provides equivalent voltage to MR element bias midpoint
[(V(HRnX) - V(HRnY))/2].
POWER, GROUND PINS
VCC
I
+5V logic circuit supply.
VDD
I
+12V power supply.
GND
I
Power supply common.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation beyond the maximum ratings may damage the device.
PARAMETER
RATING
Storage Temperature
-65 to 150°C
Junction Operating Temperature
+130°C
Positive Supply Voltage (VCC)
-0.3 to 6V
Positive Supply Voltage (VDD)
-0.3 to 14.0V
Voltage Applied to Logic Inputs
-0.3V to VCc+0.3V
All other Pins
-0.3V to Vcc+0.3V
3-22
551 32R151 OBR
MR Head ReadlWrite Device
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, 4.5V $ 5.5V, 10.8V $ VDD $ 13.2V, O°C $ Ta $ 70°C.
Current maximums are currents with the highest absolute value.
POWER DISSIPATION
PARAMETER
VCC Supply Current
CONDITIONS
MIN
UNIT
Read Mode, Isense = 8.5 mA
12
17
mA
18
25
mA
7
10
mA
Read Mode, Isense = 8.5 rnA
34+
Is·1.25
44+
Is·1.25
mA
Write Mode Iw = 30 mA
RBAW= High
34+lw
46+lw
mA
26
36
Idle Mode
Power Dissipation
MAX
Write Mode Iw = 30 rnA
Idle Mode
VDD Supply Current
NOM
.
Read Mode Isense = 8.5 mA
520 + 1.25
mA
mW
Is·VDD
Write Mode Iw = 30 rnA
RBAW= High
Idle Mode
570+
(VDD - 2)
'Iw
mW
340
mW
DIGITAL INPUTS AND OUTPUTS
0.5
V
Input low voltage (VIL 1)
(CS,R/W,VCTRL RBAW,HSO-HS2)
-0.3
0.8
V
Input high voltage (VIH1)
(CS,R/W,VCTRL,RBAW,HSO-HS2)
2.0
VCc+0.3
V
WSV, WUS Output low Voltage
lIoad = 4 mA
Input low current (ilL 1)
(CS,R/W,VCTRL,RBAW,HSO-HS2)
VIL1 = 0.8V
Input high current (IIH1)
(CS,R/W,VCTRL,RBAW,HSO-HS2)
VIH1 = 2.0V
-0.4
mA
100
~
Input low Voltage (VIL3)
(WDX, WDY)
Vcc-2.2
VIH3-0.3
V
Input high Voltage (VIH3)
(WDX, WDY)
VIL3
+0.3V
Vcc-O.5
V
Input low current (IIL3)
(WDX, WDY)
VIL3=Vcc-1.4
50
~
Input high current (IIH3)
(WDX, WDY)
VIH3 = Vcc-0.8
50
~
3-23
SSI32R1510BR
MR Head Read/Write Device
ELECTRICAL SPECIFICATIONS (continued)
ANALOG OUTPUT
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
IMF Current
CS=O
2.4
3
3.6
mA
IMF Current
CS = 1
0.1
mA
VMF Current
Sourcing
Sinking
VMF Over Current Protection
Voltage Monitor Output (VMF)
Read mode
Write in
Idle mode, VCTRL = 1
VMF Voltage Difference
VMF
READ -
VMF
WRITE
2.5
mA
0.8
mA
7.5
mA
Vmr-0.1
Vmr
Vmr+0.1
V
4.5
4.5
-0.3
5.5
5.5
6.5
6.5
0.3
V
V
V
READ MODE
Test performed with 100Q lead resistors from RDX & RDY to VCC
Read Bias Current Gain (Ar)
Read Mode
12
Idle Mode
Bias current setting Voltage (Vrc)
0.01
mA/mA
1.9
2.0
2.1
V
24
26
V
12
mA
10
uA
6.7
V
"Kr" Factor
Kr=Ar' Vrc
22
Ih Bias Current
(MR Element Bias Current)
Read Mode
6
Unselected bias Current
MR Head Bias Voltage (Vmr)
Selected Channel (Read)
mA/mA
4.3
5.5
Unselected Channel (Read)
4.9
V
Write, Idle Mode
4.9
V
MR Head Resistance (Rh)
20
36
55
Q
Differential Gain
110
150
190
VN
200
400
800
Differential Input Resistance
Dynamic Range
Input Voltage where gain
falls to 90% of its small
signal gain value f = 5 MHz
Input Referred Noise Voltage
0.72
Differential Input Capacitance
Q
mVpp
8
0.95
nWvHz
18
pF
100
MHz
Bandwidth
-3 dB, Vin = 1 mVpp Zs" 5Q
70
CMRR
Vin = 100 mVpp@ 5 MHZ
55
dB
PSRR
100 mVpp@ 5 MHZ
on VCC, VDD
50
dB
45
dB
Channel Separation
3-24
SSI 32R151 OBR
MR Head ReadlWrite Device
READ MODE (continued)
PARAMETER
CONDITIONS
Output Offset Voltage
MIN
NOM
-300
Output Voltage (Common mode)
Output Leakage Current
MAX
300
Vee-0.6
CS = 1
UNIT
mV
VDC
100
~
mNmA
WRITE MODE
Write Current gain (Aw)
0.92
0.99
1
Write Current Voltage, Vwe
Rh = 0
1.9
2.0
2.1
V
Write Current range
10
50
mA
9.0
Vpp
0.2
mA
Differential Head Voltage Swing
Unselected Head current
7.0
8.0
DC
AC
1
mApp
Head differential load resistance
360
450
540
0.
VDD Fault Voltage
8.5
9.2
10.0
VDC
VCC Fault Voltage
3.5
3.9
4.2
VDC
Head Current (HnX, HnY)
Write Mode, 0 ~ vee ~ 3.SV
-200
+200
~
Read/Idle Mode
-200
+200
~
o ~ VDD ~8.5V
o ~ VCC ~ 5.5V
o ~ VDD ~ 13.2V
SWITCHING CHARACTERISTICS
Conditions: Rh = 360., CB1 = CB2 = 0.047 J.lF, CN = 0.47 J.lF, Is = 8.5 mA, Iw = 30 rnA, T mode = 1 ms
PARAMETER
CONDITIONS
Head Switching
MIN
NOM
MAX
UNIT
to ± O.1V of Read DC and
90% of Read Envelope
1.5
3
J.lS
Write-Read Mode
RBAW = 1
to ± O.1V of Read DC and
90% of Read Envelope
1.5
2.5
J.lS
Write-Read Mode
RBAW=O
to ± O.1V of Read DC and
90% of Read Envelope
0.5
1.5
J.lS
Read-Write Mode
to 90% of Write Current
0.2
0.5
J.lS
Idle-Read/Write Mode
to ± 0.1V of Read DC and
90% of Read Envelope
5
10
J.lS
0.2
0.5
J.lS
0.7
1.5
J.lS
0.1
0.3
J.lS
Read/Write - Idle Mode
WUS Safe to Unsafe (TD1)
WDI Frequency too low
WUS Unsafe to Safe (TD2)
0.3
WSV Delay Time
50% R/W to 50% WSV
0.5
J.lS
IMF Delay Time
50% CSt to 50% IMF Current
0.5
J.lS
3-25
SSI32R1510BR
MR Head ReadlWrite Device
ELECTRICAL SPECIFICATIONS (continued)
SWITCHING CHARACTERISTICS (continued)
PARAMETER
CONDITIONS
Write Current
Rise/Fall time
MIN
NOM
MAX
UNIT
Lh = 200 nH
Rh =15 n
Iw=30 rnA
4
5
ns
Propagation delay
50%(WDX-WDY) to
50%(lx-ly)
4
Write current Asymmetry
Propagation delay
difference
ns
0.5
MR Head Bias _ _ _ _ _ _ _ _ _ _ _-,
ON
Current
OFF
RiW-----,
HIGH
WRITE
READ
WRITE
READ
LOW
, . . - - - - - - - - - HIGH orOPEN
RBAW--------~
LOW
FIGURE 2: Head Bias Current Timing
WDX-WDY
WUS
TD2
TD1
FIGURE 3: WUS Timing
3-26
ns
SSI 32R151 OBR
MR Head ReadlWrite Device
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
x >- x ?; x0
x >Q
~ ~ 0: 0: Q iii
iii
()
()
z
:I: :I: :I: :I: Z
>- x
;: ;: >- a:
~ :I: :I: a:
:I: :I:
9
8
7
6
5
4
3
-'
0:
I-
~ >
()
~
68 67 66 65 64 63 62 61
2
HR2X
Cl
Z
C!l
RBAW
0
HR2Y
WC
HW2X
RDY
HW2Y
RDX
HR3X
VMF
HR3Y
HSO
HW3X
HSI
HW3Y
HS2
HR4X
NIC
HR4Y
51
HW4X
CNY
CNX
HW4Y
VCC
HR5X
WDX
HR5Y
WDY
HW5X
WSV
HW5Y
WUS
NIC
IMF
28 29 30 31
Q
Z
x
'"
0:
:I:
~
0:
:I:
32 33 34 35 36 37 38 39 40 41
x >- xr- >x
r0: 0: ~
~ :I:
~ :I:
:I: :I:
:I:
~:I:
Q
Z
x
'"
III
()
~ Q
Z
III
()
Cl
z
C!l
Cl
Cl
>
42 43
Cl
Cl
>
a;!
58-Pin PLCC
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for final
design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
©1993 Silicon Systems, Inc.
3-27
1293 - rev.
Notes:
3-28
SSI32R1540R
6-Channel MR
ReadlWrite Am~lifler
.",~ til ~I;' Ii '%i).' ;1
January 1994
DESCRIPTION
The SSI32R1540R is a BiCMOS monolithic integrated
circuit designed for use with four-terminal, MagnetoResistive recording heads. It provides a write driver,
MR read bias current, low noise read amplifiers for both
the MR and inductive thin-film heads, and fault detection
circuitry for up to six channels. The device requires +5V
and -4.5V power supplies and comes in a 64-Lead
TQFP package.
FEATURES
..
MR read gain = 250 V/V
•
MR read input nOise = 0.65 nV'i'Hz (Nom)
•
•
•
•
•
MR read input resistance = 900n (Nom)
Thin-film read gain = 300 V/V
Thin-film read Input noise = 0.48 nV'i'Hz (Nom)
Thin-film read Input capacitance =12 pF (Nom)
Differential PEel write data input with FlipFlop
•
•
•
Head voltage swing = 7.0 Vpp (Nom)
Write current range = 5 - 30 mA
Self-switching damping resistance
•
•
+5V, -4.5V ±10% supply
Designed for four-terminal MR heads with
minimum external components
•
..
Write unsafe detection
Enhanced system write to read recovery time
•
Truly differentiall-bias/V-sense MR read Amp
MR head bias current range = 10 - 26 mA
•
Power supply fault protection
•
BLOCK DIAGRAM
c
Z
CI
!5i
::J
c
HROX
RIW
HROY
FAST
HWOX
eli
HWOY
ROX
ROY
HR1X
HR1Y
HW1X
TOX
TOY
HW1Y
••
•
WO
WIT
HR5X
VO
HR5Y
HSO
HW5X
HSl
HW5Y
HS2
~
~
<.>
~
u
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
0194
3-29
SSI 32R1540R
6-Channel MR
ReadlWrite Amplifier
PACKAGE PIN DESIGNATIONS
(Top View)
HRIX
NlC
HR1Y
47
HS2
HW1Y
46
~
HWIX
45
HSI
HR2X
44
HSO
HR2Y
43
WUS
HW2Y
42
TOY
HW2X
41
TOX
HR3X
40
VEE
HR3Y
39
GNO
VCC
HW3Y
38
HW3X
37
ROY
HR4X
36
ROX
HR4Y
35
FAST
HW4Y
34
NlC
32 33
N/C
HW4X
18 19 20 21
22 23 24 25 26 27 28 29 30 31
64·Lead TQFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
Target Specification: The target specification is intended as an initial disclosure of specifi.cation goals for the product. The specifications
are based on design goals. subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture
unless agreed to in writing.
No responsibility is assumed by Silicon Systems for use of this produC1 nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents. patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications al any time without notice. Accordingly. the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems. Inc.• 14351 Myford Road. Tustin. CA 92680-7022 (714) 573-6000. FAX (714) 573-6914
0194
3-30
©1993 Silicon Systems. Inc.
SSI32R2010R
10-Channel Thin Film
Read/Write Device
December 1993
DESCRIPTION
FEATURES
The SSI 32R2010R is ali integrated read/write circuit
designed for use with two terminal heads in disk drive
systems. The device contains up to ten channels of
read amplifiers and write drivers and also has an
internal write current source. An internal 300n damping resistor is supplied in Write mode, which is switched
to 1 kn in Read mode.
•
The circuit operates on +5V and + 12V power supplies
and is available in a 1a-channel, 36-pin SO package.
•
High performance
Read Mode Gain = 150 Typ VN
Input Noise = 0.58 nV/vtlztyp.
Input Capacitance = 15 pF typo
Write Current Range = 10 mA to 25 mA
Write Current Rise Time = 4 ns
Head Voltage Swing = 7 Vpp min
Write unsafe detection
•
Differential, ECl-like write data Input
•
Open collector read data output
•
•
Switch from 300n damping resistor to 1 kn
read input resistance
Power supply fault protection
•
+5V, +12V power supplies ±1 0%
BLOCK DIAGRAM
VDD1
GND
vee
PIN DIAGRAM
VD02
HSO
HOY
HS2
HS3
RDX
RDY
2
35
HS3
H1X
3
34
es
H1X
H1Y
4
33
RIW
H1Y
H2X
5
32
we
H2X
H2Y
6
31
ROY
H2Y
H3X
7
30
ROX
H3Y
8
29
HSO
H4X
9
28
32R2010R
10 10CM 27
HS1
H4Y
H5X
11
26
vee
H5Y
12
25
WOY
H6X
13
24
WOX
H6Y
14
23
WUS
H7X
H7X
15
22
VOO1
H7Y
H7Y
16
21
VOO2
H8X
H8X
17
20
H9Y
H8Y
H8Y
18
19
H9X
H3X
H3Y
WDX
H4X
Read
Preamplitier
WDY
And
Writ.
Current
Switch
H4Y
H5Y
H6X
H6Y
Write
Transition
Detector
Write
Fault
Detector
H9X
H9Y
wus
HS2
H5X
(lO-Channe~
we
GNO
HOY
HOX
HS1
1293 - rev.
36
HOX
3-31
36-lead SOM
CAUTION: Use handling procedures necessary
for a static sensitive component.
SSI 32R2010R
10-Cha.nnel Thin Film
ReadlWrite Device
FUNCTIONAL DESCRIPTION'
After the fault condition is removed, two transitions of
the write data input lines are required to clear WUS.
The Write Unsafe output is open-collector and is usually terminated by an external resistor connected to
VCC.
The SSI32R201 OR addresses up to 10 channels with
logic control inputs which are TTL compatible. Head
selection is accomplished as shown in Table l.tylode
selection is accomplished as shown in Table 2. The
mode select inputs have internal pull up cirCuits so that
if an input is open it will rise to the upper logic level and
force the device into a non-writing condition.
Additionarry, power voltage monitoring circuits are
used to detect VCC and VDD1 voltage levels. If either
is too low to permit valid data recording, write current is
inhibited.
"
WRITE MODE
READ MODE
In Write Mode (R/W and CS low) the circuit functions as
a current switch. The Head Select Inputs HSO, HS1,
HS2 and HS3 determine the selected head, The write
data inputs (WDX, WDY) determine the polarity of the
head current. When WDX is high and WDY is low,write
current is in the X direction. HNX is sinking current.
In Read Mode, (RIW high and CS low), the circuit
functions as a low noise differential amplifier. The read
amplifier input terminals are determined by the Head
Select inputs. The read amplifier outputs (RDX, RDY)
are open collector, requiring external load resistors
connected to VCC. The amplifier gain polarity is noninverting between HnX, HnY inputs and RDX, RDY
outputs.
The write current magnitude is adjusted by an external
resistor, Rwc, from WC to GND, and is given ,by:
Iw= VwcJRwc
The switch from write to read modes also changes the
resistance across HnX and HnY from its write damping
value of 3000 to its read mode input value of 1 kil.
Note that actual head current, Ihd. is:
Ihd = Iw/(1 +;) + loffset
IDLE MODE
Taking CS high selects the idle mode which switches
the RDX and RDY outputs into a high impedance state
and deactivates the internal write current source. This
facilitates multi device installations, by allowing the
read outputs to be wired OR'edand the write current
programming resistor to be common to,all devices.
where Rh is head resistance, Rd is write damping
resistance and (offset is a constant DC offset current.
WRITE MODE FAULT DETECT CIRCUIT
SeVeral circuits are dedicated to detecting fault conditionsassociatedwith the write mode. A logical high (off)
level will be present at the Write Unsafe (WUS) terminal if any of the following write fault conditions are
present:
Open head circuit (Iw ~ 20 mAl
Head shorted to ground
Write current transition frequency too low
Write mode not logically selected
A head shorted to ground condition results in a pulsating WUS signal.
3-32
SSI 32R2010R
10-Channel Thin Film
Read/Write Device
TABLE 2: Mode Select
TABLE 1: Head Select
Head Selected
HS3
HS2
HS1
HSO
CS
R/W
Mode
0
1
2
3
4
5
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
Write
Read
Idle
Idle
1
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
6
7
8
9
1
PIN DESCRIPTION
CONTROL INPUT PINS
NAME
TYPE
CS
I
R/W
I
HSO, HS1,
I
HS2, HS3
HEAD TERMINAL PINS
HOX-H9X,
I/O
HOY-H9Y
DATA INPUT/OUTPUT PINS
WDX, WDY
I/O
RDX, ROY
I/O
DESCRIPTION
Chip Select Input. A logical low level enables the circuit for a read or write
operation. Has internal pull up.
Readlwrite select. A logical low level enables the write mode (when CS is
low). Has internal pull up.
Head select inputs. Logical combinations select one of sixteen heads.
See Table 1. Has internal pull down resistors.
X, Y Head connections: Current in the X-direction flows into the X-port.
Differential write data input.
Differential Read Data output. These open collector outputs are normally
terminated in 100n resistors to VCC.
EXTERNAL COMPONENT CONNECTION PINS
WC
I/O
Resistor connected to GND to provide desired value of write current.
CIRCUIT MONITOR PINS
WUS
0
Write Unsafe is an open-collector output with the off-state indicating that
conditions are not proper for a write operation.
POWER, GROUND PINS
VCC
I
+5V Logic circuit supply.
VDD1
I
+12V power supply.
I
Positive power supply for write current drivers.
VDD2
I
GND
Power supply common.
3-33
SSI32R2010R
10-Channel Thin Film
Read/Write Device
ELECTRICAL SPECIFICATIONS
'.
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may permanently damage the device.
PARAMETER
RATING
Positive Supply Voltage, VCC
6VDC
Supply Voltage, VDD1, 2
13.5 VDC
Operating Junction Temperature
+130°C
Storage Temperature
-65 to + 130°C
Package Temperature (20 sec. reflow)
215°C
Input Voltages
-0.2 to VCC + 0.2 VDC
HSO,HS1,HS2,HS3,CS,RAN
Outputs
Read Data (RDX, RDY)
VCC -2.5 to VCC + 0.3 VDC
Write Unsafe (WUS)
-O.2V to
Current Reference (WC)
-80 rnA to 1.0 mA VDC
Head Outputs (Write Mode)
-80 mA to 1.0 rnA rnA
vee + O.2V
VDC
POWER SUPPLY
Unless otherwise specified, 4.5V ::; VCC ::; 5.5V, 10.8V:-;; VDD1, 2:-;; 13.2V, O°C:-;; T (ambient) :-;; 70°C.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Power Dissipation (Does not
Idle mode
195
295
mW
include power dissipation through
Read mode
440
775
mW
RDX, ROY load resistors)
Write mode
Positive Supply Current
ICC
(Includes RDX, ROY currents)
Positive Supply Current
Positive Supply Current
1001
IDD2
350+101w 530 + t121w
mW
Idle Mode
13
20
mA
Read Mode
27
35
mA
Write Mode
22
26
mA
Idle Mode.
10
12
mA
Read Mode
32
42
mA
Write Mode
23
28
mA
Idle Mode
0.5
2
mA
Read Mode
1
1.5
rnA
Write Mode
1 + Iw
2 + Iw
mA
3-34
SSI 32R2010R
10-Channel Thin Film
Read/Write Device
DC CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
High-level Input Voltage
VIH
(CS, RIW, HSO, HS1, HS2, HS3)
NOM
2.0
Low-level Input Voltage
VIL
(CS, RIW, HSO, HS1, HS2, HS3)
MAX
UNIT
-
V
0.8
V
IIH
High-level Input Current
(CS, RIW, HSO, HS1, HS2, HS3)
VIH = 2.7V
100
~
Low-level Input Current
ilL
(CS, RIW, HSO, HS1, HS2, HS3)
VIL = O.4V
-400
~
High-level Output Voltage
(WDX, WDY)
VIH
Vee-1.0
Vee - 0.72
V
Low-level Output Voltage
(WDX, WDY)
VIL
Vee - 1.87
Vee -1.625
V
WUS, Low Level Voltage
ILUS = 4 rnA
(denotes safe condition)
0.5
V
WUS, High Level Current
VHUS =5.0V
(denotes unsafe condition)
100
~
WRITE MODE
Test Conditions (Unless otherwise specified). VCC = 4.5 to 5.5V, Ta = 0 to +70°C, VDD = 10.8 to 13.2V,
Lh = 470 nH, Rh = 25n, WD Tr, Tf < 2 ns, Iw = 20 rnA.
PARAMETER
CONDITIONS
MIN
Current Range, Iw
NOM
MAX
UNIT
25
rnA
2.15
10
Write Current Voltage, Vwc
1.95
2.05
Differential Head voltage Swing
7.0
7.6
loffset
Unselected Head
Transient Current
0.5
Non adjacent heads tested
to minimize external coupling
effects
Differential Output
Capacitance
3-35
rnA
1
240
Head Damping Resistance
300
V
Vpp
mA(pk)
360
n
20
pF
II
SSI32R2010R
10-Channel Thin Film
Read/Write Device
ELECTRICAL SPECIFICATIONS (continued)
FAULT DETECTION CHARACTERISTICS
Test conditions same as Write Mode above (unless otherwise specified.)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
4.3
V
10.2
V
VCC Value for Write
Current Turn off
Ih < 1 rnA
3.7
4.0
VDD Value for Write
Current Turn off
Ih < 1 rnA
8.8
9.5
WDX, WDY Transition Frequency
WUS = Low (Guaranteed safe)
1.0
MHz
READ MODE
Tests performed with 1OOQ load resistors from RDX and RDY to VCC. Test conditions same as Write mode
(unless otherwise specified.)
PARAMETER
Differential Voltage Gain
Voltage Bandwidth
-3 dB
-1 dB
Input Noise Voltage
Differential Input Capacitance
Differential Input Resistance
CONDITIONS
MIN
NOM
MAX
Vin
= 1 mVpp, f = 300 kHz
= 1 mVpp
Zs < 5Q, Vin = 1 mVpp
Zs = OQ, Yin = OV,
Power Bandwidth = 20 MHz
Yin = OV, f = 5 MHz
Yin = OV, f = 5 MHz
120
150
180
Zs < 5Q, Vin
50
65
Dynamic Range @ 5 MHz
Input voltage where AC
gain falls to 90% of the gain
Common Mode Rejection Ratio
Yin = 100 mVpp, OV DC
f = 5 MHz
VCC or VDD = 100 mVpp
f = 5 MHz
Power Supply Rejection Ratio
20
MHz
35
0.75
nV/~Hz
15
20
pF
1500
Q
4
mVpp
60
90
dB
55
75
dB
90
Unselected channels are
driven with Yin = 20 mVpp
@5MHz
60
Output Offset Voltage
Rh = 0, Lh
=0
-250
Output Leakage Current
Idle Mode
Output Common Mode Voltage
Rh
Output Voltage Compliance
Adjust RDX, Y load voltage
source for <5% THD of either
output.
VCC-0.9
3-36
VN
MHz
0.58
400
Channel Separation
= 0, Lh = 0
UNIT
VCC -1.6
VCC-O.S
dB
250
mV
20
~
VCC -0.3
V
vce
V
SSI32R2010R
10-Channel Thin Film
Read/Write Device
SWITCHING CHARACTERISTICS
Test conditions same as Write Mode plus RDX, Y connected VCC through 100Q resistors, WUS with 1 kQ
to VCC.
PARAMETER
CONDITIONS
MIN
Idle to ReadlWrite Transition Time
Delay to 10 or 90% of Read
Output or Write Current
Read/Write to Idle Transition Time
Read to Write Transition Time
VLCS= 0.8V,
Delay to 90% of Iw
Write to Read Transition Time
VLCS = 0.8V, Delay to 90% of
10 MHz Read Signal, 100 mV
envelope
NOM
MAX
UNIT
75
150
ns
85
150
ns
85
150
ns
350
600
ns
500
ns
4.0
ns
Head Select Switching Delay
Read or Write Mode
Head Current Rise and Fall Times
10% to 90%
Iw = 25 mA, Lh = 0 nH
Rh= OQ
2.5
Iw = 15 mA, Lh = 1 IlH
Rh = 45Q
6
ns
0.5
ns
0.5
ns
15
ns
200
ns
0.5 +Tw*
J.1S
Head Current Rise and Fall
Difference
Head Current Switching Delay
Difference (Asymmetry)
WDX, WDY transitions 2 ns,
switching time asymmetry
0.2ns
Head Current
Propogation Delay
50% WD to 50% Iw
TD3
WUS
TD2
Unsafe to Safe Delay
After Write Data Begins
8
f(data) = 5 MHz
Write Mode (After 2 transitions
ofWD)
Unsafe to Safe Delay
WUS
After Write Mode Selected
Safe to Unsafe Delay
WUS
TD1
After Write Mode fault condition occurs
1.5
J.lS
Safe to Unsafe Delay
WUS
After exiting Write Mode
0.5
J.lS
*Tw is the period of the write data input.
(WDX·WDY)
TD1~
WUS
--.. -4-- TQ3
HEAD
CURRENT
(Ix ·Iy)
3-37
1,.-----
SSI 32R2010R
to-Channel Thin Film
Read/Write Device
PACKAGE PIN DESIGNATIONS
THERMAL CHARACTERISTICS: Gja
(Top View)
36-Lead SOM
HOX
I
75°C/W
GND
HOY
HS3
H1X
CS
H1Y
RiW
H2X
we
H2Y
RDY
H3X
RDX
H3Y
HSO
H4X
HS1
H4Y
H5X
HS2
vce
H5Y
WDY
H6X
WDX
H6Y
WUS
H7X
H7Y
VDD1
H8X
H9Y
H9X
VDD2
H8Y
CAUTION: Use handling procedures necessary
for a static sensitive component.
36-lead SOM
ORDERING INFORMATION
PART DESCRIPTION
SSI 32R2010R
36-lead SOM
ORDER NUMBER
PACKAGE MARK
32R2010R-CM
32R201 OR-1 OeM
No responsibility is assumed by Silioon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before pladng orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
©1991 Silicon Systems,lnc.
3-38
1293 - rev.
SSI32R2011R
10-Channel Thin Film
Read/Write Device
IT' Ii hil Mi.,,; .s" t" ;.
December 1993
DESCRIPTION
FEATURES
High performance
The SSI 32R2011 R is an integrated read/write circuit
designed for use with two terminal heads in disk drive
systems. The device contains up to ten channels of
read amplifiers and write drivers and also has an
internal write current source. An internal 300n
damping resistor is supplied in Write mode, which is
switched to 1 kn in Read mode.
Read Mode Gain
= 150 Typ V/v
Input Noise = 0.58 nV/..JHz typo
Input Capacitance = 15 pF typo
= 10 mA to 25 mA
= 4 ns
Head Voltage Swing = 7 Vpp min
Write Current Range
Write Current Rise Time
The circuit operates on +5V and +12V power supplies
and is available in a 10-channel, 36-pin SO package.
Write unsafe detection
Differential, ECl-like write data input
Open collector read data output
Switch from 300n damping resistor to 1 kn
read input resistance
Power supply fault protection
+5V, +12V power supplies ±10%
PIN DIAGRAM
BLOCK DIAGRAM
VODl
GND
vee
VDD2
r
HOX
~
HSO
Head
Select
Decode
HS1
HS2
HOY
ROX
Read
RDY
Amplifier
f"""',i'i
Read
Preamplifier
~~ I
t!
R/W
H2X
WC
H2X
H2Y
ROY
H2Y
H3X
ROX
H3X
H3Y
HSO
H4X
HS1
H4X
H4Y
Current
WO
WO
H6Y
WUS
H7X
VOO1
H7Y
H7Y
VDD2
H8X
H8X
H9Y
JHOY
H8Y
H9X
H7X
Write
Transition
Detector
Detector
:VDDl
:q
Mode
Select
Indicate
III
p
Write
Fault
Detector
H9X
H9Y
1293 - rev.
wus
vec
H6X
H6Y
[i
HS2
H5X
H5Y
H5Y
H6X
Source
Voltage
Fault
H4Y
H5X
(10-Channel)
Write
we
And
Write
Current
Switch
CS
H1Y
H3Y
WD
HS3
H1X
H1Y
~H1X
HS3
GNO
HOY
3-39
36-lead SOM
CAUTION: Use handling procedures necessary
for a static sensitive component.
II
SSI 32R2011 R
10-Channel Thin Film
Read/Write Device
FUNCTIONAL DESCRIPTION
The SSI 32R2011 R addresses up to 10 channels with
logic control inputs which are TTL compatible. Head
selection is accomplished as shown in Table 1. Mode
selection is accomplished as shown in Table 2. The
mode select inputs have internal pull up circuits so that
if an input is open it will rise to the upper logic level and
force the device into a non-writing condition.
After the fault condition is removed, two transitions of
the write data input lines are required to clear WUS.
The Write Unsafe output is open-collector and is usually
terminated by an external resistor connected to VCC.
Additionally, powervoltage monitoring circuits are used
to detect VCC and VD01 voltage levels. If either is too
low to permit valid data recording, write current is
inhibited.
READ MODE
WRITE MODE
In Read Mode, (R/W high and CS low), the circuit
functions as a low noise differential amplifier. The read
amplifier input terminals are determined by the Head
Select inputs. The read amplifier outputs (ROX, ROY)
are open collector, requiring external load resistors
(1000) connected to VCC. The amplifier gain polarity
is non-inverting between HnX, HnY inputs and ROX,
ROY outputs.
In Write Mode (R/W and CS low) the circuitfunctions as
a current switch. The Head Select Inputs HSO, HS1,
HS2 and HS3 determine the selected head. The write
data inputs (WO, WO) determine the polarity of the
head current. Write current is toggled between the X
and Y direction of the selected head on each low to high
transition of WO (see Figure 1). A preceding read
operation initializes the Write Data Flip Flop (WOFF) to
pass write current in the X-direction of the head (i.e.,
into the X-port).
The switch from Write to Read modes also changes the
resistance across HnX and HnYfrom its write damping
value of 3000 to its read mode input value of 1 kO.
The write current magnitude is adjusted by an external
resistor, Rwc, from WC to GNO, and is given by:
IDLE MODE
Iw= Vwc/Rwc
Taking CS high selects the Idle mode which switches
the ROX and ROY outputs into a high impedance state
and deactivates the internal write current source. This
facilitates multi device installations by allowing the
read outputs to be wired OR'ed and the write current
programming resistor to be common to all devices.
Note that actual head current, Ihd, is:
Ihd = Iw/( 1+ ~~) + loffset
where Rh is head resistance, Rd is write damping
resistance and loffset is a constant DC offset current.
TABLE 1: Head Select
WRITE MODE FAULT DETECT CIRCUIT
Several circuits are dedicated to detecting fault
conditions associated with the Write mode. A logical
high (off) level will be present at the Write Unsafe
(WUS) terminal if any of the following write fault
conditions are present:
• Open head circuit (Iw ;?: 20 rnA)
• Head shorted to ground
• Write current transition frequency too low
• Write mode not logically selected
3-40
Head Selected
HS3
HS2
HS1
HSO
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
SSI 32R2011 R
10-Channel Thin Film
Read/Write Device
TABLE 2: Mode Select
CS
R/W
Mode
0
0
Write
0
1
Read
1
0
Idle
1
1
Idle
PIN DESCRIPTION
CONTROL INPUT PINS
NAME
TYPE
DESCRIPTION
CS
I
Chip Select Input. A logical low level enables the circuit for a read or write
operation. Has internal pull up.
R/W
I
Readlwrite select. A logical low level enables the write mode (when CS is low).
Has internal pull up.
HSO, HS1,
HS2, HS3
I
Head select inputs. Logical combinations select one of sixteen heads.
See Table 1. Has internal pull down resistors.
x, Y Head connections:
HOX-H9X,
HOY-H9Y
Current in the X-direction flows into the X-port.
DATA INPUT/OUTPUT PINS
WD,WD
RDX, RDY
I
0
Differential write data input.
Differential Read Data output. These open collector outputs are normally
terminated in 100n resistors to vec.
EXTERNAL COMPONENT CONNECTION PINS
WC
I/O
Resistor connected to GND to provide desired value of write current.
Write Unsafe is an open-collector output with the off-state indicating that
conditions are not proper for a write operation.
POWER , GROUND PINS
vce
I
VDD1
I
+12V power supply.
VDD2
I
+ 12V power supply for write current drivers.
GND
I
Power supply common.
+5V Logic circuit supply.
3-41
SSI 32R2011 R
10-Channel Thin Film
Read/Write Device
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may permanently damage the device.
PARAMETER
RATING
Positive Supply Voltage, VCC
6VDC
Supply Voltage, VD01, 2
13.5 VOC
Operating Junction Temperature
+130°C
Storage Temperature
-65 to + 130°C
Package Temperature (20 sec. reflow)
215°C
INPUT VOLTAGES
HSO,HS1,HS2,HS3,CS,RAN
-0.2 to VCC + 0.2 VOC
OUTPUTS
Read Oata (ROX, ROY)
VCC -2.5 to VCC + 0.3 VOC
Write Unsafe (WUS)
-0.2V to VCC + 0.2V
Current Reference (WC)
-80 rnA to 1.0 rnA
Head Outputs (Write Mode)
-80 rnA to 1.0 rnA
POWER SUPPLY
Unless otherwise specified, 4.5V::; VCC::; 5.5V, 10.8V::; VD01, 2::; 13.2V, O°C::; T (ambient) ::; 70°C.
PARAMETER
CONDITIONS
Power Dissipation (Does not
Idle mode
include power dissipation through
Read mode
ROX, ROY load resistors)
Write mode
Positive Supply Current
ICC
(Includes RDX, ROY currents)
Positive Supply Current
Positive Supply Current
1001
1002
MIN
MAX
UNIT
195
295
mW
440
775
mW
NOM
350+ 10lw 530 + 11.21w
mW
Idle Mode
13
20
rnA
Read Mode
27
35
rnA
Write Mode
22
26
rnA
Idle Mode
10
14
rnA
Read Mode
32
49
rnA
Write Mode
23
28
rnA
Idle Mode
0.5
2
rnA
Read Mode
1
1.5
rnA
Write Mode
1 + Iw
2+lw
rnA
3-42
SSI 32R2011 R
1O-Channel Thin Film
Read/Write Device
DC CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
High-level Input Voltage
VIH
(CS, RIW, HSO, HS1, HS2, HS3)
NOM
2.0
Low-level Input Voltage
VIL
(CS, RIW, HSO, HS1, HS2, HS3)
MAX
UNIT
-
V
0.8
V
High-level Input Current
IIH
(CS, RIW, HSO, HS1, HS2, HS3)
VIH
= 2.7V
100
~
Low-level Input Current
ilL
(eS, RIW, HSO, HS1, HS2, HS3)
VIL
= 0.4V
-400
~
High-level Input Voltage
(WD, WD)
VIHI
Vee - 1.0
Vee- 0.72
V
Low-level Input Voltage
(WD, WD)
VILI
Vee - 1.87
Vee -1.625
V
WUS, Low Level Voltage
ILUS = 4 rnA
(denotes safe condition)
0.5
V
WUS, High Level Current
VHUS = 5.0V
(denotes unsafe condition)
100
~
WRITE MODE
Test Conditions (Unless otherwise specified). VCC = 4.5 to 5.5V, Ta
Lh = 470 nH, Rh = 25Q, WD Tr, Tf < 2 ns, Iw = 20 rnA.
Current Range, Iw
= 0 to +70°C, VDD = 10.8 to 13.2V,
10
25
rnA
2.15
V
Write Current Voltage, Vwc
1.95
2.05
Differential Head voltage Swing
7.0
7.6
Vpp
0.5
rnA
loffset
Unselected Head
Transient Current
Non adjacent heads tested
to minimize external coupling
effects
240
Head Damping Resistance
Differential Output
Capacitance
3-43
300
1
mA(pk)
360
Q
20
pF
I
SSI32R2011R
1O-ChanneIThin, Film
ReadIWrite, Device
ELECTRICAL SPECIFICATIONS (continued)
FAULT DETECTION CHARACTERISTICS
Test cOnditions same asWrite Mode above (unless otherwise specified.)
PARAMETER
CONDITION,S
MIN
NOM
MAX
UNIT
VCC Value for Write
Current Turn off
Ih< 1 rnA
3.7
4.0
4.3
V
VDD Value fOr Write
Current Turn off
Ih < 1 rnA
8.8
9.5
10.2
V
WD, WD Transition Frequency
WUS = Low (Guaranteed safe)
2.0
MHz
READ MODE
Tests performed with 100Q load resistors from RDX and RDYto VCC. Test conditions same as Write mode
(unless otherwise specified.)
Vin = 1 mVpp, f = 300 kHz
120
150
-3 dB
ZS < 5Q, Vin = 1 mV'pp
50
65
-1 dB
Zs < 5Q, Vin = 1 mVpp
20
Differential Voltage Gain
Voltage Bandwidth
180
VN
MHz
35
MHz
Input Noise Voltage
Zs = on . Vin = OV,
Power Bandwidth = 20 MHz
Differential Input Capacitance
Vin = OV, f = 5 MHz
Differential Input Resistance
Vin = OV, f = 5 MHz
Dynamic Range @ 5 MHz
Input voltage where AC
gain falls to 90% of the gain
Common Mode Rejection Ratio
Vin = 100 mVpp, OV DC
f= 5 MHz
60
90
dB
VCC or VDD = 100 mVpp
=5 MHz
55
75
dB
90
Power Supply Rejection Ratio
f
0.75
nV/-IHz
15
20
pF
1$00
Q
400
mVpp
4
Channel Separation
Unselected channels ar&
driven with Vin = 20 mVpp
@5MHz
60
Output Offset Voltage
Rh = 0, Lh
=0
"25'0
Output Leakage Current
Idle Mode
Output Common Mode Voltage
Rh = 0, Lh = 0
Output Voltage Compliance
Adjust RDX, Y load voltage
source for <5% THO of either
output.
3-44
0.58
dB
250
mV
20
~
vee -0.9 vee -0.5 vee -0.3
Vee-l.6
VCC
V
V
5S1 32R2011 R
10-Channel Thin Film
Read/Write Device
SWITCHING CHARACTERISTICS
Test conditions same as Write Mode plus RDX, Y connected VCC through 1000 resistors, WUS with 1 kO
to VCC.
.
PARAMETER
CONDITIONS
Idle to ReadIWrite Transition Time
MIN
NOM
MAX
UNIT
Delay to 90% of Read
Output or Write Current
75
150
ns
ReadIWrite to Idle Transition Time
Delay to 10% of Read
Output or Write Current
85
150
ns
Read to Write Transition Time
VLCS = 0.8V,
Delay to 90% of Iw
85
150
ns
Write to Read Transition Time
VLCS = 0.8V, Delay to 90% of
10 MHz Read Signal, 100 mV
envelope
350
600
ns
500
ns
4.0
ns
Head Select Switching Delay
Read or Write Mode
Head Current Rise and Fall Times
10% to 90%
Iw = 25 rnA, Lh
Rh =00
= 0 nH
Iw = 15 rnA, Lh = 1 IlH
Rh = 450
2.5
Head Current Rise and Fall
Difference
Head Current Switching Delay
Difference (Asymmetry)
WD, WD transitions 2 ns,
switching time asymmetry
0.2 ns
Head Current
Propogation Delay
50% WD to 50% Iw
Unsafe to Safe Delay
After Write Data Begins
TD3
WUS
TD2
f(data) = 5 MHz
Write Mode (After 2 transitions
ofWD)
WUS
Unsafe to Safe Delay
After Write Mode Selected
ns
6
8
0.5
ns
0.5
ns
15
ns
200
ns
0.5 +Tw*
J..LS
Safe to Unsafe Delay
WUS
TD1
After Write Mode fault condition occurs
1.5
J..LS
Safe to Unsafe Delay
WUS
After exiting Write Mode
0.5
J..LS
*Tw is the period of the write data input.
3-45
II
SSt 32R2011 R
10':'Channel Thin Film
ReadlWrite Device
HEAD
CURRENT
(Ix-Iy)
FIGURE 1: Write Mode Timing Diagram
SSI 32R2011 R
10-Channel Thin Film
Read/Write Device
PACKAGE PIN DESIGNATIONS
THERMAL CHARACTERISTICS: 9Ja
(Top View)
36-Lead SOM
HOX
I
75°C/W
GND
HOY
HS3
H1X
~
H1Y
RIW
H2X
we
H2Y
RDY
H3X
RDX
H3Y
HSO
H4X
HS1
H4Y
HS2
H5X
vee
H5Y
WD
H6X
Wi)
H6Y
WUS
H7X
VDD1
H7Y
VDD2
H8X
H9Y
H8Y
H9X
36-Lead SOM
CAUTION: Use handling procedures necessary
for a static sensitive ccmpcnent.
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022, (714) 573-6000, FAX: (714) 573-6914
11:)1993 SiliCon Systems, Inc.
3-47
1293- rev.
Notes:
3-48
SSI 32R2020R/2021 R.
5V, 2, 4, 6, 10-Channel
Thin-Film Read/Write Device
January 1993
DESCRIPTION
FEATURES
The SS132R2020R/2021 R are bipolar monolithic integrated circuits designed for use with two-terminal recording heads. They provide a low noise read amplifier, write current control, and data protection circuitry
for up to ten channels. The SSI 32R2020R/2021 R
provide internal 3200 damping resistors. Damping
resistors are switched in during write mode and
switched out during read mode. Power supply fault
protection is provided by disabling the write current
generator during power sequencing. System write to
read recovery time is significantly improved by controlling the read channel common mode output voltage
shift in the write mode. The 32R2021 R option provides
the user with a controllable write current adjustment
feature.
•
•
The SSI 32R2020R/2021 R require only +5V power
supplies and are available in a variety of packages.
They are hardware compatible with the 32R4610Al
4611 A read/write devices.
•
•
•
Write unsafe detection
•
Head short to ground protection
+5V ±10% supply
Low power
- PO = 130 mW read mode (Nom)
High Performance:
- Read mode gain = 300 VN
- Input noise = 0.56 nV/~Hz (Nom)
- Input capacitance = 16 pF (Nom)
- Write current range = 5-35 mA
•
Self switching damping resistance
•
Designed for two-terminal thin-film or MIG
heads with inductance up to 5.0 ~H
Pin compatible with the 32R4610AR/4611AR
Power supply fault protection
BLOCK DIAGRAM
VCC1
GND
wus
PIN DIAGRAM
veC2
cs
GNO
RiW
II
- PO = 3.3 mW idle (Nom)
•
HoX
HOY
l:%
HOX
RIW
HOY
WC
H1X
ROY
H1Y
ROX
H2X
HSO
ROX
ROY
H1X
H1Y
H2Y
HS1
H3X
VCC1
H3Y
WOI
WDI
H2X
H2Y
VCC2
WUS
20-PIN SOL
CAUTION: Use handling procedures necessary
for a static sensitive component.
0193 - rev.
WCADJ available on the 32R2021 R-4 24-pin option only
SSt 32R2020R/2021 R
5V, 2, 4, 6, 10-Channel
Thin-Film Read/Write Device
CIRCUIT OPERATION
The SSI 32R2020R/2021 R have the ability to address up to 10 two-terminal heads and provide write drive or read
amplification. Mode control and head selection are described in Tables 1 and 2. The TTL inputs RIW and CS have
internal pull-up resistors to prevent an accidental write condition. HSO, HS1, HS2 and HS3 have internal pulldown
resistors. Internal clamp circuitry will protect the IC from a head short to ground condition in any mode.
TABLE 1: Mode Select
TABLE 2: Head Select
CS
R/W
Mode
HS3
HS2
HS1
HSO
Head
0
0
0
Write
0
0
0
0
0
1
Read
0
0
0
1
1
1
0
Idle
0
0
1
0
2
1
1
Idle
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
PIN DESCRIPTION
NAME
HSO, HS1,
HS2, HS3
TYPE
t
CS
R/W
WUS
WDI
t
t
t
HOX - H9X;
HOY - H9Y
RDX, RDY
WC
WCADj'
DESCRIPTION
t
t
t
I
Head Select: selects one of ten heads
I
Chip Select: a high inhibits the chip
I
ReadIWrite : a high selects Read mode
0
Write Unsafe: a high indicates an unsafe writing condition
I
Write Data In: changes the direction of the current in the recording head
i/O
X, Y Head Connections
0
X, Y Read Data: differential read data output
Write Current: used to set the magnitude of the write current
Write Current Adjust: Used to fine tune the write current
VCC1
I
+5V Supply
VCC2
I
+5V Supply for Write current drivers
GND
!
Ground
* Available on 32R2021 R-4 24-pin option only
t When more than one R/W device is used, signals can be wire OR'ed
3-50
SSI 32R2020R/2021 R
5V, 2, 4, 6, 10-Channel
Thin-Film Read/Write Device
WRITE MODE
Taking both CS and RIW low selects Write mode which
configures the SSI 32R2020Rl2021 R as a current
switch and activates the Write Unsafe (WUS) detector
circuitry. Head current is toggled between the X and Y
side of the selected head on each high to low transition
of the Write Data Input (WDI). Changing from Read or
Idle mode to Write mode initializes the Write Data FlipFlop to pass write current into the "X" pin. In this case,
the Y side of the head will be higher potential than the
X side. The magnitude of the write current (O-pk) is
given by:
Iw= K·Vwc
Rwc
Rwc is connected from pin WC to GND. Note the
actual head current lx, y is given by:
Ix y
,
Iw
1 + Rh/Rd
HEAD SHORT TO GROUND PROTECTION
The 2020Rl2021 R provides a head short to ground
protection circuit in any mode. In Idle or Read Mode,
current out of the head port will not exceed 20 rnA if any
head is shorted to ground. In Write mode, if any head
is shorted to ground (regardless if it is selected or not)
the write current generator will turn off, the WUS flag
will go high, and current will be limited to less than 1 rnA
out of the head port.
WRITE UNSAFE
Any of the following conditions will be indicated as a
high level on the Write Unsafe, WUS, open collector
output.
Where:
Rh
POWER SUPPL Y FAULT PROTECTION
A voltage fault detection circuit improves data security
by disabling the write current generator during a voltage fault or power startup regardless of mode. Note
that WUS does not necessarily turn on to flag a power
supply fault condition.
= Head resistance plus external wire
resistance
WDI frequency too low
Device in Read mode
Chip disabled
No head current
Head opened
Head short to ground
Rd = Damping resistance
In write mode a 3200 damping resistor is switched in
across the Hx, Hy ports.
The 32R2021 R adds a feature which allows the userto
adjust the Iw current by a finite amount. The WCADJ
pin is used to adjust write current for write operations on
different zones of the disk. It is used by switching a
separate write current adjust resistor in and out on the
WCADJ pin or by connecting a DAC to that pin to sink
a controllable amount of current. The WCADJ pin is
nominally biased to VCC/2. Sinking current from this
pin to ground will divert a proportional amount of
current from the actual head current while maintaining
a constant current through the WC resistor and VCC.
Allowing WCADJ to float or pulling it high will cut off the
circuit and it will have no effect. A TTL gate can be used
as a switch with a small degradation in accuracy. The
amount of write current decrease is shown below:
To insure proper WUS operation, the product of write
current, WDI frequency, and head inductance should
be less than 500 mA·~·MHz. To insure no false WUS
trigger, the product of head current and head resistance (Ix,y-Rh) should be between 100 rnVand 1.7V.
WDI frequency too low is detected if the WDI frequency falls below 500 kHz (typ). Consult the WUS
Safe to Unsafe timing for range offrequency detection.
Device In Read mode and Chip disabled will flag
WUS if RlW is high or CS is high.
No head current will flag WUS if Rwc
s.elected head is present.
Iw head (decrease) (rnA) = (29 • VwcADJlRwcAOJ)
Head opened will flag WUS if Rh =
condition that VCC/lw < 0.25 VIrnA.
where:
VWCADJ = VCC/2 (VOlts)
co
= co and the
and under the
Head short to ground is described in the preceding
paragraph.
RwcAOJ = write current adjust setting resistor (kil)
Upon entering write mode, WUS is valid after two high
to low transitions of WDI following the required ReadWrite transition time (0.61JS max).
Example: For a 7.25 rnA head current decrease,
RWCADJ = (27·2.5) 17.25 = 10 kil
3-51
SSI 32R2020R/2021 R
5V, 2, 4, 6, 10-Channel
Thin-Film ReadIWrite Device
CIRCUIT OPERATION (continued)
READ MODE
The Read mode configures the SSI32R2020R/2021 R
as a low noise differential amplifier and deactivates the
write current generator. The damping resistor is
switched out of the circuit allowing a high impedance
input to the read amplifier. The RDX and RDY output
are driven by emitter followers. They should be AC
coupled to the load. The (X, Y) inputs are non-inverting
to the (X,Y) outputs.
Note that in Idle or Write mode, the read amplifier is
deactivated and RDX, RDY outputs become high im-
pedance. This facilitates multiple R/W applications
(wired-OR RDX, RDY) and minimizes voltage drifts
when switching from Write to Read mode. Note also
that the write current source is deactivated for both the
Read and Idle mode.
IDLE MODE
Taking CS high selects the idle mode which switches
the RDX and RDY outputs into a high impedance state
and deactivates the device. Power consumption in this
mode is held to a minimum.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may permanently damage the device.
PARAMETER
RATING
DC Supply Voltage
VCC1
-0.3 to +6 VDC
VCC2
-0.3 to +6 VDC
Write Current
Iw
60 rnA
Digital Input Voltage
Vin
-0.3 to VCC1 +0.3 VDC
Head Port Voltage
VH
-0.3 to VCC2 +0.3 VDC
Output Current: RDX, RDY
10
-6 rnA
Tstg
-65 to +150 °C
WUS
Storage Temperature
+8 rnA
RECOMMENDED OPERATING CONDITIONS
DC Supply Voltage
VCC1 = VCC2
5±10%
VDC
Operating Junction Temperature
Tj
+2510 +135
Recommended Head Load Range
Lh
0.3 - 5.0
°C
,
J.!H
DC CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified.
PARAMETER
VCC1 Supply Current
VCC2 Supply Current
MIN
CONDITIONS
NOM
MAX
UNIT
Read Mode
18
25
rnA
Write Mode
22
29
rnA
Idle Mode
0.6
0.95
rnA
8
11
rnA
4+lw
7+ Iw
rnA
0
0.2
rnA
Read Mode
Write Mode
Idle Mode
3-52
551 32R2020R/2021 R
5V, 2, 4, 6, 10-Channel
Thin-Film ReadlWrite Device
PARAMETER
CONDITIONS
Power Dissipation
Read Mode
MIN
MAX
130
200
130 + 41w 200 +4.31w
Write Mode
Idle Mode
VCC1 Fault Voltage
NOM
Iw< 0.2 mA
3.5
UNIT
mW
mW
3.3
6.5
mW
3.9
4.2
VDC
0.8
VDC
DIGITAL INPUTS
Input Low voltage (Vii)
Input High Voltage (Vii)
2.0
= 0.8V
= 2.0V
101 = 2 mAmax
Input Low Current
Vii
Input High Current
Vih
WUS Output Low Voltage (Vol)
VDC
-0.4
mA
100
J.lA
0.5
VDC
WRITE CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified.
Write Current Constant UK"
0.99
Write Current Voltage (Vwc)
WCADJ Voltage
SSI 32R2021 R
IWCADJ
= 0 to .5 mA
Ihead( Decrease)/lWCADJ
SSI 32R2021 R
1.15
1.25
1.35
V
2.0
VCC/2
3.0
VDC
23
27
31
mA/mA
IWCADJ Range
SSI 32R2021 R
0.0
Differential Head Voltage Swing
4.2
5.6
3.4
5.0
Open Head Iw
= 20 mA
0.5
Unselected Head Current
WDI Pulse Width
Vpp
1
Head Differential Damping
Resistance (Rd)
0.2V
Write Current Range (Iw)
PWH
10
ns
PWL
5
ns
5
Head Differential Load
Capacitance
3-53
mA(pk)
Q
320
ViI~
mA
Vpp
35
mA
25
pF
II
SSI 32R2020R/2021 R
5V, 2, 4, 6, 10-Channel
Thin-Film ReadlWrite Device
READ CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified. CL (RDX, RDY) < 20 pF,
RL (RDX, RDY) = 1 kQ.
PARAMETER
CONDITIONS
MIN
NOM
MAX
Yin
= 1 mVpp @1 MHz
= 1 mVpp
IZsl < 5Q, Yin = 1 mVpp
BW = 15 MHz, Lh = 0, Rh = 0
Yin = 1 mVpp, f = 5 MHz
Yin = 1 mVpp, f = 5 MHz
250
300
350
IZsl < 5Q, Yin
20
720
AC input voltage where gain
falls to 90% of its small signal
gain value, f = 5 MHz
2
mVpp
Yin = 0 VDC + 100 mVpp
@5MHz
55
dB
Power Supply Rejection Ratio
100 mVpp @ 5 MHz on VCC
50
dB
Channel Separation
Unselected channels driven
with Yin = 0 VDC + 100 mVpp
55
Differential Voltage Gain
Voltage BW
-ldB
-3dB
Input Noise Voltage
Differential Input Capacitance
Differential Input Resistance
Dynamic Range
Common Mode Rejection Ratio
f =5 MHz
Output Current
AC coupled load, RDX to RDY
RDX, RDY Common Mode
Output Voltage
MHz
45
0.56
0.75
nV/,fHz
16
22
pF
Q
1200
dB
±300
mV
50
Q
0.9
rnA
0.4 vee VCC/2
0.6 VCC
SWITCHING CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified. IW = 20 rnA, Lh = 1.0
f(Data) =5 MHz.
R/W
CS
VN
MHz
Output Offset Voltage
Single Ended Output Resistance
UNIT
VDC
IJ.H, Rh = 30Q
Read to Write
R/W to 90% of write current
0.1
0.6
J1S
Write to Read
R/Wto 90% of
100 mV Read signal envelope
0.1
0.6
J1S
Unselect to Select
CS to 90% of write current or
to 90% of 100 mV 10 MHz
0.2
1
J1S
Select to Unselect
CS to 10% of write current
0.11
0.6
J1S
0.11
0.6
J1S
2.0
3.6
J1S
0.1
0.6
J1S
HSO,1 to any Head
To 90% of 100 mV 10 MHz
Read signal envelope
WUS:
Safe to Unsafe (TD1)
Write mode, loss of WDI
transitions. Defines maximum
WDI period for WUS operation
Unsafe to Safe (TD2)
Fault cleared, from first neg
WDI transition
3-54
0.6
SSI 32R2020R/2021 R
5V, 2, 4, 6, 10-Channel
Thin-Film ReadIWrite Device
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
3
10
ns
1.0
ns
6
ns
Head Current:
WOI to Ix - Iy (lO3)
from 50% paints, Lh = 0, Rh
Asymmetry
WOI has 1 ns rise/fali time,
Lh =0, Rh =0
Rise/fall Time
10% to 90% points, Lh
Rise/fall Time
Lh = 1 IlH, Rh = 30n
=0
=0, Rh =0
4
15
ns
WDI
WUS
HEAD - - - f -...........
CURRENT
\,-----,1
(Ix -Iy)
FIGURE 1: Write Mode Timing Diagram
3-55
II
SSI 32R2020R/2021 R
5V, 2, 4, 6, 10.,Channel
Thin"Film Read/Write Device
PACKAGE PIN DESIGNATIONS
(Top View)
GND
~.
HOX
GND
HOX
~
GND
NiC
RJW
HOY
HOY
HS3
HOX
N/C
H1X
RIW
H1X
~
HOY
WCADJ
H1Y
we
H1Y
AlW
H1X
WC
H2X
ROY
H2X
WC
H1Y
RDY
H2Y
RDX
H2Y
RDY
H2X
RDX
H3X
HSO
H3X
RDX
H2Y
HSO
H3Y
HSl
H3Y
HSO
H3X
HSl
H4X
HS2
H4X
HSl
H3Y
VCCl
H4Y
VCC
H4Y
HS2
WC
WDI
H5X
WDI
H5X
VCCl
WUS
HSY
WUS
H5Y
WDI
H6X
WUS
H6Y
WC
VCC2
24-Pin SOL, SOV
24-Pin SOV
H7X
VCC2
wc
GND
cs
H7Y
HOX
AlW
HOX
RJW
Hax
H9Y
HOY
WC
HOY
WC
HaY
H9X
H1X
RDY
H1X
RDY
H1Y
RDX
H1Y
ROX
VCC2
HSO
H2X
HSO
VCCl
H2Y
HSl
WDI
H3X
VCCl
H3Y
WOI
~
GND
N/C
WUS
16-Pin SOL
VCC2
wus
20-Pin SOL, SOV
3-56
36-Pin SaM
SSI 32R2020R/2021 R
5V, 2, 4, 6, 10-Channel
Thin-Film ReadlWrite Device
ORDERING INFORMATION
PART DESCRIPTION
ORDER NUMBER
PACKAGE MARK
2-Channel
SSI32R202R
16-Lead SOL
32R2020R-2CL
32R2020R-2CL
20-Lead SON
32R2020R-2CN
32R2020R-2CN
20-Lead SOL
32R2020R-4CL
32R2020R-4CL
20-Lead SOV
32R2020R-4CV
32R2020R-4V
24-Lead SOV
32R2021 R-4CV
32R2021 R-4CV
32R2020R
24-Lead SOV
32R2020R-6CV
32R2020R-6CV
10-Channel
36-Lead SOM
32R2020R-10CM
32R2020R-10CM
4-Channel
SSI32R202R
32R2021R
6-Channel
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights ortrademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the. reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680 (714) 573-6000, FAX (714) 573-6914
Patent Pending
©1990 Silicon Systems, Inc.
0193 - rev.
3-57
Notes:
3-58
SSI 32R2025R
5V, 4-Channel
Thin-Film ReadlWrite Device
ti, Pb' hil mt.] ihbi't" ;.
December 1993
DESCRIPTION
FEATURES
The SSI 32R2025R is a bipolar monolithic integrated
circuit designed for use with two-terminal recording
heads. It provides a low noise read amplifier, write
current control, and data protection circuitry for up to
four channels. The SSI 32R2025R provides internal
6200 damping resistors. Damping resistors are
switched in during Write mode and switched out during
Read mode. Power supply fault protection is provided
by disabling the write current generator during power
sequencing. System write to read recovery time is
significantly improved by controlling the read channel
common mode output voltage shift in the Write mode.
The 32R2025R option provides the user with a controllable write current adjustment feature.
•
The SSI 32R2025R requires only +5V power supplies
and is available in 20-lead SO packages. It is hardware
compatible with the SSI32R2020R Read/Write device.
•
•
+5V ±10% supply
Low power
- PD
= 130 mW Read mode (Nom)
- PD
= 3.3 mW Idle (Nom)
High Performance:
- Read mode gain
= 300 VN
- Input noise = 0.56 nV"IHz (Nom)
- Input capacitance
= 16 pF (Nom)
= 5-35 mA
- Write current range
•
Self switching damping resistance
•
Designed for two-terminal, thin-film or MIG
heads with Inductance up to 5.0 J..LH
•
Pin compatible with the 32R2020R
•
Write unsafe detection
•
Power supply fault protection
•
Head shon to ground protection
BLOCK DIAGRAM
VCC1
GNO
wus
PIN DIAGRAM
VCC2
GND
cs
RiW
wc
HOX
RfR
HOY
e"S"
RDY
H1Y
RDX
H2X
HSO
RDX
H1X
ROY
H1Y
HS1
H3X
VCC1
WDI
WDI
H2X
VCC2
WUS
H2Y
20-LEAD SOL, SOY
H3X
H3Y
we
1293 - rev.
WCADJ available on the 32R2025R-4 24-pin option only
3-59
CAUTION: Use handling procedures necessary
for a static sensitive component.
551 32R2025R
5V, 4-Channel
Thin-Film Read/Write Device
CIRCUIT OPERATION
The SSI 32R2025R has the ability to address up to 4 two-terminal heads and provide write drive or read
amplification. Mode control and head selection are described in Tables.1 and 2. The TTL inputs R/W and CS have
internal pull-up resistors to prevent an accidental write condition. HSO and HS1 have internal pulldown resistors.
Internal clamp circuitry will protect the IC from a head short to ground condition in any mode.
TABLE 1: Mode Select
TABLE 2: Head Select
CS
R/W
Mode
HS1
HSO
Head
0
0
Write
0
0
0
0
1
Read
0
1
1
1
0
Idle
1
0
2
1
1
Idle
1
1
3
PIN DESCRIPTION
NAME
HSO, HS1
TYPE
t
CS
R/W
WUS
WDI
t
t
t
HOX - H3X;
HOY - H3Y
RDX, ROY
WC
I
Head Select: selects one of four heads
I
Chip Select: a high inhibits the chip
I
ReadlWrite : a high selects Read mode
0
Write Unsafe: a high indicates an unsafe writing condition
I
Write Data In: changes the direction of the current in the recording head
1/0
t
t
DESCRIPTION
0
X, Y Head Connections
X, Y Read Data: differential read data output
Write Current: used to set the magnitude of the write current
..
VCC1
I
+5V Supply
VCC2
I
+5V Supply for write cu rrent drivers
GND
I
Ground
t When more than one RIW device is used, Signals can be wire OR'ed.
3-60
SSI 32R2025R
5V,4-Channel
Thin-Film Read/Write Device
WRITE MODE
Taking both CS and R/W low selects Write mode which
configures the SSI32R2025R as a current switch and
activates the Write Unsafe (WUS) detector circuitry.
Head current is toggled between the X and Y side of the
selected head on each high to low transition of the
Write Data Input (WOI). Changing from Read or Idle
mode to Write mode initializes the Write Data Flip-Flop
to pass write current into the "X" pin. In this case, the Y
side of the head will be higher potential than the X side.
The magnitude of the write current (O-pk) is given by:
Iw= KoVwc
Rwc
Rwc is connected from pin WC to GND.
actual head current lx, y is given by:
Ix
Chip disabled
No head current
Head opened
Head short to ground
To insure proper WUS operation, the product of write
current, WOI frequency, and head inductance should
be less than 400 mA°J,JH°MHz. To insure no false WUS
trigger, the product of head current and head resistance (lx,y·Rh) should be between 100 mVand 1.7V.
WDI frequency too low is detected if the WDI frequency falls below 500 kHz (typ). ConsuH the WUS
Safe to Unsafe timing for range of frequency detection.
Device in Read mode and Chip disabled will flag
WUS if R/W is high or CS is high.
Note the
No head current will flag WUS if Rwc =
selected head is present.
_
Iw
,y-1 + Rh/Rd
Head opened will flag WUS if Rh =
condition that VcC/lw < 0.25 VIrnA.
Where:
Rh = Head resistance plus external wire resistance
Rd = Damping resistance
In Write mode a 620n damping resistor is switched in
across the Hx, Hy ports.
00
00
and the
and under the
Head short to ground is described in the preceding
paragraph.
Upon entering Write mode, WUS is valid after two high
to low transitions of WDI following the required ReadWrite transition time (0.61J.S max).
POWER SUPPLY FAULT PROTECTION
A voHage fauH detection circuit improves data security
by disabling the write current generator during a voltage fauH or power startup regardless of mode. Note
that WUS does not necessarily turn on to flag a power
supply fauH condition.
READ MODE
The Read mode configures the SSI32R2025R as a low
noise differential amplifier and deactivates the write
current generator. The damping resistor is switched
out ofthe circuit allowing a high impedance inputtothe
read amplifier. The RDX and RDY output are driven by
emitter followers. They should be AC coupled to the
load. The (X,Y) inputs are non-inverting to the (X,Y)
outputs.
HEAD SHORT TO GROUND PROTECTION
The 32R2025R provides a head short to ground protection circuit in any mode. In Idle or Read mode,
current out of the head port will not exceed 20 mA if any
head is shorted to ground. In Write mode, if any head
is shorted to ground (regardless if it is selected or not)
the write current generator will turn off, the WUS flag
will go high, and current will be limited to less than 2 rnA
out of the head port.
Note that in Idle or Write mode, the read amplifier is
deactivated and RDX, RDY outputs become high impedance. This facilitates muHiple RIW applications
(wired-OR RDX, ROY) and minimizes voHage drifts
when switching from Write to Read mode. Note also
that the write current source is deactivated for both the
Read and Idle mode.
WRITE UNSAFE
Any of the following conditions will be indicated as a
high level on the Write Unsafe, WUS, open collector
output.
IDLE MODE
Taking CS high selects the idle mode which switches
the ROX and ROY outputs into a high impedance state
and deactivates the device. Power consumption in this
mode is held to a minimum.
WDI frequency too low
Device in Read mode
3-61
ss,· 32R2025R
5V;.4-Channel
Thin-Film Read/WriteOevice
ELECTRICAL SPECIFICATIONS·
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may permanently damage the device.
PARAMETER
RATING
DC Supply Voltage
VCC1
-0.3 to +6 VDC
,
VCC2
-0.3 to +S VDC
Write Current
Iw
SOmA
Digital Input Voltage
Yin
-0.3 to VCC1 +0.3 VDC
Head Port Voltage
VH
-0.3 to VCC2 +0.3 VDC
Output Current: RDX, ROY
10
-SmA
WUS
Storage Temperature
,
.,
,
",'
,
+SmA
Tstg
"
-65 to +150°C
RECOMMENDED OPERATING CONDITIONS
DC Supply Voltage
VCC1 =VCC2
, Operating Junction Temperature
Recommended Head Load Range
Tj
.
5±10%
,"
VDC
+25 to +135
°C
0.3 - 5.0
J1H
Lh
DC CHARACTERISTICS
Recommended operating conditions apply unles&otherwise specified.
PARAMETER
VCC1 Supply Current
VCC2 Supply Current
' MIN
CONDITIONS
.
UNIT
18
25
rnA
22
29
rnA
Idle Mode
Read mode
,
0.6
0.95
rnA
Read mode,
8
11
mA
Write rnodif
4+lw
" 0 ,'"
7+lw
rnA
0.2
mA
130
200
mW
Read mode
130+41w 2OO+4.3Iw
WrHernode
Idle Mode
VCC1 Fault Voltage
MAX
Write mode
Idle Mode
Power Dissipation
NOM
{
IweI.
'7
23
.,
,.
22
20
36-lead SOM
HSO
HI'
HS2
VOC,
WD
WI!
WUS
WCADJ
V0C2
HOY
HOX
SSI 32R2028R
5V, 10-Channel
Thin-Film ReadlWrite Device
"
,
,,"
CIRCUIT OPERATION
The SSI 32R2028R has the ability to address up to 10 two-terminal heads and provide write drive or read
amplification. Mode control and head selection are described in Tables 1 and 2. The TTL inputs RJW and CS have
internal pull-up resistors to prevent an accidental write condition. HSO, HS1,HS2 and HS3 have internal pulldown
resistors. Internal clamp circuitry will protect the IC from a head short to ground condition in any mode.
TABLE 1: Mode Select
TABLE 2: Head Select
CS
R/W
Mode
HS3
HS2
HS1
HSO
Head
0
0
Write
0
0
0
0
0
0
1
Read
0
0
0
1
1
1
0
Idle
0
0
1
0
2
1
1
Idle
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
"
PIN DESCRIPTION
NAME
TYPE
DESCRIPTION
HSO, HS1, t
HS2, HS3
I
Head Select: selects one of ten heads
CS
I
Chip Select: a high inhibits the chip
t
I
ReadIWrite: a high selects Read mode
WUS
t
0
Write Unsafe: a high indicates an unsafe writing condition
WD,WD
t
I
Differential Write Data Input a negative transition of (WD- WD) toggles the
direction of the head current
R/W
HOX - H9X;
HOY - H9Y
I/O
X, Y Head Connections
RDX,RDYt
0
X, Y Read Data:. differential read data output
WC
t
Write Current used to set the magnitude of the write current
WCADJ
t
Write Current Adjust: Used to fine tunethe write current
VCC1
I
+5V Supply
VCC2
I
+5V Supply for Write current drivers
GND
I
Ground
tWhen more than one RIW device is used, signals can be wire OR'ed
3-76
SSI 32R2028R
5V, 10-Channel
Thin-Film Read/Write Device
WRITE MODE
POWER SUPPL Y FAULT PROTECTION
A voltage fault detection circuit improves data security
by disabling the write current generator during a voltage fault or power startup regardless of mode. Note
that WUS does not necessarily turn on to flag a power
supply fault condition.
Taking both CS and R/W low selects Write mode which
configures the SSI 32R2028R as a current switch and
activates the Write Unsafe (WUS) detector circuitry.
Head current is toggled between the X and Y side of the
selected head on each high to low transition of the
differential signal WD - WD. Changing from Read or
Idle mode to Write mode initializes the Write Data FlipFlop to pass write current into the "X" pin. In this case,
the Y side of the head will be higher potential than the
X side. The magnitude of the write current (O-pk) is
given by:
K V
HEAD SHORT TO GROUND PROTECTION
The SSI 32R2028R provides a head short to ground
protection circuit in any mode. In Idle or Read Mode,
current out of the head port will not exceed 20 mA if any
head is shorted to ground. In Write mode, if any head
is shorted to ground (regardless if it is selected or not)
the write current generator will turn off, the WUS flag
will go high, and current will be limited to less than 1 mA
out of the head port.
Iw=~
Rwc
Rwc is connected from pin WC to GND. Note the actual
head current lx, y is given by:
Ix y=
Iw
,
1 + Rh/Rd
WRITE UNSAFE
Any of the following conditions will be indicated as a
high level on the Write Unsafe, WUS, open collector
output.
Where:
Rh
= Head resistance plus external wire
Rd
= Damping resistance
resistance
WD frequency too low
Device in Read mode
Chip disabled
No head current
Head opened
Head short to ground
In Write mode a 320Q damping resistor is switched in
across the Hx, Hy ports.
The SSI32R2028R includes a feature which allows the
user to adjust the Iw current by a finite amount. The
WCADJ pin is used to adjust write current for write
operations on different zones of the disk. It is used by
switching a separate write current adjust resistor in and
out on the WCADJ pin or by connecting a DAC to that
pin to sink a controllable amount of current. The
WCADJ pin is nominally biased to VCC/2. Sinking
current from this pin to ground will divert a proportional
amount of current from the actual head current while
maintaining a constant current through the WC resistor
and VCC. Allowing WCADJ to float or pulling it high will
cut off the circuit and it will have no effect. A TTL gate
can be used as a switch with a small degradation in
accuracy. The amount of write current decrease is
shown below:
Iw head (decrease) (mA)
To insure proper WUS operation, the product 01 write
current, WD frequency, and head inductance should
be less than 500 mA-IlH-MHz. To insure no false WUS
trigger, the product of head current and head resistance (Ix,y-Rh) should be between 100 mV and 1.7V.
WD frequency too low is detected if the WD frequency falls below 500 kHz (typ). Consult the WUS
Safe to Unsafe timing for range offrequency detection.
Device in Read mode and Chip disabled will flag
WUS if R/W is high or CS is high.
No head current will flag WUS if Rwc =
selected head is present.
co
and the
Head opened will flag WUS if Rh = co and under the
condition that VCCllw < 0.25 V/mA.
= (29 - VwcADJlRwCADJ)
where:
Head shon to ground is described in the preceding
paragraph.
VWCADJ = VCC/2 (volts)
RWCADJ = write current adjust setting resistor (kQ)
Upon entering Write mode, WUS is valid after two
transitions of WD following the required Read-Write
transition time (0.6 jlS max).
Example: For a 7.25 mA head current decrease,
RWCADJ = (27 - 2.5) 17.25 = 10kn
3-77
II
551 32R2028R
5V, 10-Channel
Thin-Film Read/Write Device
CIRCUIT OPERATION (continued)
pedance. This facilitates multiple R/W applications
(wired-OR RDX, ROY) and minimizes voltage drifts
when switching from Write to Read mode. Note also
that the write current source is deactivated for both the
Read and Idle mode.
READ MODE
The Read mode configures the SSI32R2028R as a low
noise differential amplifier and deactivates the write
current generator. The damping resistor is switched
out of the circuit allowing a high impedance input to the
read amplifier. The RDX and ROY output are driven by
emitter followers. They should be AC coupled to the
load. The (X,Y) inputs are non-inverting to the (X,Y)
outputs.
IDLE MODE
Taking CS high selectsthe Idle mode which switches
the RDX and ROY outputs into a high impedance state
and deactivates the device. Power consumption in this
mode is held to a minimum.
Note that in Idle or Write mode, the read amplifier is
deactivated and RDX, ROY outputs become high im-
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may permanently damage the device.
PARAMETER
DC Supply Voltage
RATING
VCC1
-0.3 to +6 VDC
VCC2
-0.3 to +6 VDC
Write Current
Iw
60mA
Digital Input Voltage
Yin
-0.3 to VCC1 +0.3 VDC
Head Port Voltage
VH
-0.3 to VCC2 +0.3 VDC
Output Current: RDX, ROY
WUS
10
-6 mA
+8mA
Storage Temperature
Tstg
-65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
5±10%
VDC
Operating Junction Temperature
DC SupplyVoltage
VCC1 = VCC2
Tj
+25 to +135
°C
Recommended Head Load Range
Lh
0.3 - 5.0
~H
DC CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified.
PARAMETER
CONDITIONS
NOM
MAX
UNIT
VCC1 Supply Current
Read Mode
18
25
mA
Write Mode
Idle Mode
22
0.6
29
0.9
mA
mA
VCC2 Supply Current
MIN
Read Mode
8
11
mA
Write Mode
4+ Iw
7+ Iw
mA
0
0.2
mA
Idle Mode
3-78
SSI 32R2028R
5V, 10-Channel
Thin-Film ReadlWrite Device
DC CHARACTERISTICS
(continued)
PARAMETER
CONDITIONS
Power Dissipation
Read Mode
MIN
Write Mode
MAX
UNIT
130
200
mW
130+41w 200 + 4.31w
Idle Mode
VCC1 Fault Voltage
NOM
Iw< 0.2 mA
3.5
mW
3
5
mW
3.9
4.2
VDC
0.8
VDC
DIGITAL INPUTS
Input Low voltage (Vii)
HSX, CS, R/W
Input High Voltage (Vii)
HSX, CS, R/W
Input Low Current, HSX, CS, RIW
Vii = 0.8V
Input High Current, HSX, CS, RIW
Vih = 2.0V
WD, WD Input Low Current
Vii = VCC - 1.75V
VDC
-0.4
mA
100
70
Vih = VCC - 0.75V
WO, WD Input High Current
WD, WD Input Low Voltage
2.0
85
100
125
l1A
l1A
l1A
Vii
Vee
-1.870
Vee 1.625
VDC
WD, WD Input High Voltage Vih
Vee 1.50
Vee 0.5
VDC
0.5
VDC
WUS Output Low Voltage (Vol)
101 = 2 mAmax
WRITE CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified
Write Current Constant "K"
0.99
Write Current Voltage (Vwc)
1.15
1.25
1.35
V
2.0
VCC/2
3.0
VOC
Ihead(Decrease )/IWCADJ
23
27
31
mA/mA
IWCADJ Range
0.0
0.5
mA
WCAOJ Voltage
IWCADJ
= 0 to
.5 mA
Differential Head Voltage Swing
Open Head, Iw
= 20 mA
4.2
5.6
3.4
5.0
1
Unselected Head Current
Head Differential Damping
Resistance (Rd)
WD Pulse Width
Vpp
320
Vil:?!0.2V
Write Current Range (Iw)
PWH
10
PWL
5
5
Head Differential Load
Capacitance
3-79
mA (pk)
Q
ns
ns
35
mA
25
pF
II
551 32R2028R
5V, 10-Channel
Thin-Film ReadlWrite Device
READ CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified. CL (RDX, ROY) < 20 pF,
RL (RDX, ROY) = 1 kQ.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Differential Voltage Gain
Yin = 1 mVpp@1 MHz
250
300
350
VN
Voltage BW
-1dB
Ilsi < 5Q, Yin = 1 mVpp
20
-3dB
Ilsi < 5Q, Yin = 1 mVpp
40
MHz
45
MHz
Input Noise Voltage
BW = 15 MHz, Lh = 0, Rh = 0
Differential Input Capacitance
Yin = 1 mVpp, f = 5 MHz
Differential Input Resistance
Yin = 1 mVpp, f = 5 MHz
Dynamic Range
AC input voltage where gain
falls to 90% of its small signal
gain value, f = 5 MHz
2
mVpp
Common Mode Rejection Ratio
Yin = 0 VDC + 100 mVpp
@5MHz
55
dB
Power Supply Rejection Ratio
100 mVpp @ 5 MHz on VCC
50
dB
Channel Separation
Unselected channels driven
with Yin = 0 VDC + 100 mVpp
55
720
0.56
0.75
16
22
f =5 MHz
Output Current
AC coupled load, RDX to ROY
RDX, ROY Common Mode
Output Voltage
dB
±300
mV
50
Q
0.9
0.4
vee
pF
Q
1200
Output Offset Voltage
Single Ended Output Resistance
nV/"Hz
mA
VCC/2 0.6 VCC
VDC
SWITCHING CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified. IW = 20 mA, Lh = 1.0 /J.H, Rh = 30Q
f(Data) = 5 MHz.
R/W
CS
Read to Write
R/W to 90% of write current
0.1
0.6
f.1S
Write to Read
R/Wto 90% of
100 mV Read signal envelope
0.1
0.6
f.1S
Unselect to Select
CS to 90% of write current or
to 90% of 100 mV 10 MHz
0.2
1
f.1S
Select to Unselect
CS to 10% of write current
0.11
0.6
f.1S
To 90% of 100 mV 10 MHz
Read signal envelope
0.11
0.6
f.1S
3.6
f.1S
0.1
0.6
HSO,1 to any Head
WUS:
Safe to Unsafe (TD1)
Write mode, loss of WDI 0.6
transitions. Defines maximum
WDI period for WUS operation
Unsafe to Safe (TD2)
Fault cleared, from first neg
WDI transition
3-80
2.0
f.1S
SSI 32R2028R
5V, 10-Channel
Thin-Film Read/Write Device
SWITCHING CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified. IW = 20 mA, Lh
PARAMETER
CONDITIONS
MIN
Head Current:
= 0,
WD to Ix - Iy (TD3)
from 50% pOints, Lh
Asymmetry
WDI has 1 ns rise/fall time,
Lh
= 0, Rh =
Rh
=
°
°
= 0, Rh =
Riselfall Time
10% to 90% points, Lh
Riselfall Time
Lh = 1 j.LH, Rh = 300
°
= 1.0 j.LH, Rh = 300
NOM
MAX
UNIT
8
12
ns
1.0
ns
6
ns
4
15
ns
WD-WD
1 - - - - ' - -_ _ _ _ _
\
wus
'------
HEAD
CURRENT
(Ix -Iy)
FIGURE 1: Write Mode Timing Diagram
3-81
II
551 32R2028R
5V, 10-Channel
Thin-Film Read/Write Device
CAUTION: Use handling procedures necessary
for a static sensitive component.
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
Patent Pending
©1993 Silicon Systems, Inc.
1293 - rev.
3-82
SSI32R2030A/2031A
5V, 2, 4-Channel Thin-Film
Read/Write Device
January 1994
DESCRIPTION
FEATURES
The SSI 32R2030Al2031 A are bipolar monolithic integrated circuits designed for use with two-terminal thinfilm recording heads. They provide a low noise read
amplifier, write current control, and data protection
circuitry for up to four channels. The SSI 32R2030AR/
2031 AR option provides internal700Q damping resistors. Power supply fault protection is· provided by
disabling the write current generator during power
sequencing. System write to read recovery time is
significantly improved by controlling the read channel
common mode output voltage shift in the write mode.
The 32R2031A option provides for an additional feature providing the user with a controllable write current
adjustment feature.
•
•
The SSI 32R2030Al2031A require only +5V power
supplies and are available in a variety of packages.
5V±100/0
low power
- PD
•
= 175 mW read mode (Nom)
= 0.85 nV/;fHz max
Input capacitance = 35 pF max
Write current range = 10·35 rnA
-
•
•
•
•
•
Designed for two·terminal thin-film heads or
MIG heads up to 5 J.lH
Programmable write current source
Write unsafe detection
Enhanced system write to read recovery time
Power supply fault protection
Head short to ground protection
BLOCK DIAGRAM
GND
WUS
= 250 VN
- Input noise
•
VCC1
II
High Performance:
- Read mode gain
PIN DIAGRAM
VCC2
cs
GND
HOX
AIN
HOX
R!W
HOY
WC
H1X
RDY
H1Y
RDX
H2X
HSO
HOY
H1X
H1Y
WD'
H2Y
HS1
H3X
VCC1
H3Y
WDI
H2X
H2Y
HSO~
HS1~
VCC2
WUS
2D-PIN SOL
_
_
H3X
H3Y
CAUTION: Use handling procedures necessary
wc
0194 - rev.
WCAOJ
WCADJ available on the 32R2031A 24-pin option only
for a static sensitive component.
SSI 32R2030A/2031 A
5V, 2, 4-Channel Thin-Film
Read/Write Device
CIRCUIT OPERATION
The SSI 32R2030Al2031 A has the ability to address up to 4 two-terminal thin-film heads and provide write drive
or read amplification. Head selection and mode control are described in Tables 2 and 3. The TTL inputs R/w and
CS have internal pull-up resistors to prevent an accidental write condition. HSO, and HS1 have internal pulldowns.
Internal clamp circuitry will protect the IC from a head short to ground condition in any mode.
TABLE 1: Mode Select
TABLE 2: Head Select
CS
R/W
Mode
HS1
HSO
Head
0
0
Write
0
0
0
0
1
Read
0
1
1
1
0
Idle
1
0
2
1
1
Idle
1
1
3
PIN DESCRIPTION
NAME
TYPE
DESCRIPTION
HSO, HS1
I
Head Select: selects one of four heads
CS
I
Chip Select: a high inhibits the chip
R/W
WUS
WDI
t
t
t
HOX - H7X;
HOY - H7Y
RDX,HDY
WC
WCADJ'
VCC1
I
Read/Write : a high selects Read mode
0
Write Unsafe: a high indicates an unsafe writing condition
I
Write Data In: changes the direction of the current in the recording head
1/0
t
t
t
0
X, Y Head Connections
X, Y Read Data: differential read data output
Write Current: used to set the magnitude of the write current
Write Current Adjust: Used to decrease the write current by a finite amount
I
+5V Supply
VCC2
I
+5V Supply for Write current drivers
GND
I
Ground
'Available on 32R2031A 24-pin option only
t These signals can be wire OR'ed
3-84
SS132R2030A/2031 A
5V, 2, 4-Channel Thin-Film
Read/Write Device
WRITE MODE
Taking both CS and R/W low selects write mode which
configures the SSI 32R2030Al2031A as a current
switch and activates the Write Unsafe (WUS) detector
circuitry. Head current is toggled between the X and Y
side of the selected head on each high to low transition
of the Write Data Input (WDI). The WDI input pulse
width requirement is amplitude dependent and pull ups
are recommended at higher data rates, please refer to
the WDI pulse width specifications. Note that a preceding read or idle mode select initializes the Write Data
Flip-Flop to pass write current through the "X" side of
the head. The magnitude of the write current (O-pk) is
K • VWC
given by:
IW=--RWC
RWC is connected from pin WC to GND.
actual head current lx, y is given by:
Note the
pin to ground will divert a proportional amount of
current from the actual head current while maintaining
a constant current through the WC resistor and VCC.
Allowing WCADJ to float or pulling it high will cut off the
circuit and it will have no effect. For example, if the
nominal head current is set to 30 mA through WC with
WCADJ open, then for a 7.25 mA head current decrease, a 10 kn resistor would be connected from the
WCADJ pin to ground. A TTL gate could be used as a
switch with a small degradation in accuracy. To perform the same function, a DAC could be used, by
programming it to sink 0.25 mA from the WCADJ pin.
Iw head (Decrease) = (29 • VWCADJ I RWCADJ)
Where:
VWCADJ = Voltage on WCADJ pin = VCC/2
RWCADJ = Write current adjust setting resistor
VOLTAGE FAULT
Ix y
,
Iw
1 + Rh/Rd
A voltage Fault detection circuit improves data security
by disabling the write current generator during a voltage fault or power startup regardless of mode.
Where:
Rh = Head resistance plus external wire
READ MODE
resistance
Rd
The Read mode configures the SSI32R2030Al2031A
as a low noise differential amplifier and deactivates the
write current generator. The RDX and RDY output are
driven by emitterlollowers. They should be AC coupled
to the load. The (X,Y) inputs are non-inverting to the
(X,Y) outputs.
= Damping resistance
Any of the following conditions will be indicated as a
high level on the Write Unsafe, WUS. open collector
output.
WDI frequency too low
Note that in Idle or Write mode, the read amplifier is
deactivated and RDX, RDY outputs become high impedance. This facilitates multiple R/W applications
(wired-OR ROX, RDY) and minimizes voltage drifts
when switching from Write to Read mode. Note also
that the write current source is deactivated lor both the
Read and Idle mode.
Device in Read mode
Chip disabled
No write current
Afterfault condition is removed, one negative transition
on WDI is required to clear WUS.
The 32R2031 A adds a feature which allows the userlo
adjust the Iw current by a finite amount. The WCADJ
pin is used to adjust write current for write operations on
different zones of the disk. It is used by switching a
separate write current adjust resistor in and out on the
WCADJ pin or by connecting a DAC to that pin to sink
a controllable amount of current. The WCADJ pin is
nominally biased to VCC/2. Sinking current from this
IDLE MODE
Taking CS high selects the idle mode which switches
the ROX and ROY outputs into a high impedance state
and deactivates the device. Power consu mption in this
mode is held to a minimum.
3-85
551 32R2030A/2031 A
5V, 2, 4-Channel Thin-Film
Read/Write Device
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may permanently damage the device.
RATING
PARAMETER
DCSupply Voltage
VCC1
-0.3 to +7 VDC
VCC2
-0.3 to +7 VDC
Write Current
IW
80mA
Digital Input Voltage
Yin
-0.3 to VCC1 +0.3 VDC
Head Port Voltage
VH
-0.3 to VCC2 +0.3 VDC
Output Current: RDX, ROY
Storage Temperature
10
-10 mA
WUS
+12 mA
Tstg
-65 to + 150°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
DC Supply Voltage
Operating Junction Temperature
RATING
VCC1
5±10% VDC
VCC2
5±10% VDC
Tj
+25 to + 110°C
DC CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified.
PARAMETER
CONDITIONS
VCC1 Supply Current
Read Mode
Write Mode
, Head Select Pins
'Idle Mode
(HSO, HS1) Floating
VCC2 Supply Current
NOM
MAX
UNIT
(Vee±5%)
23
28
33
mA
(Vcc±10%)
19
28
37
mA
(Vee±5%)
21
24
27
mA
(Vee±10%)
17
24
31
mA
6
9
12
mA
(Vee±5%)
(Vee ±10%)
4
9
14
.mA
Read Mode
(Vee±5%)
5
8
11
mA
(Vee ±10%)
4
8
12
mA
Write Mode
(Vee±5%)
6
8+ Iw
10 + Iw
mA
(Vee±10%)
5
8 + Iw
11 + Iw
mA
(Vcc±5%)
0.1
0.2
0.4
mA
(Vee±10%)
0.1
Idle Mode
Power Dissipation
MIN
Read Mode
(Vee ±5%)
(Vee ±10%)
3-86
0.2
0.5
mA
175
230
mW
270
mW
SSI 32R2030A/2031 A
5V, 2, 4-Channel Thin-Film
Read/Write Device
DC CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
Power Dissipation (Continued)
Write Mode
MIN
NOM
150 + 41w 190 + 41w
(Vcc±5%)
(VCC±10%)
Idle Mode
(Vcc±5%)
3.8
IW<0.2 mA
UNIT
mW
230 +
4.41w
mW
50
65
mW
80
mW
4.0
4.2
VDC
0.8
VDC
(Vcc ±10%)
VCC1 Fault Voltage
MAX
DIGITAL INPUTS
Input Low voltage (VIL)
Input High Voltage (VIH)
2.0
VDC
Input Low Current
VIL = O.BV
Input High Current
VIH = 2.0V
-0.4
100
!lA
WUS Output Low Voltage (VOL)
101 = 2 mA max
0.5
VDC
mA
WRITE CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified.
Write Current Constant "K"
0.96
0.99
Write Current Voltage (VWC)
1.15
1.25
1.35
V
2.0
VCC/2
3.0
VDC
Ihead( Decrease )/lwCADJ
SS132R2031A12031AR
26
29
32
mAimA
IWCADJ Range
SS132R2031A12031AR
0.0
0.5
mA
0.021w
mApk
25
pF
950
n
n
WCADJ Voltage
SSI 32R2031 Al2031 AR
Differential Head Voltage Swing
IWCADJ = 0 to .5 mA
Ih (p-p) • Rh not to exceed
3.4V (Head Swing Min)
3.4
Vpp
Unselected Head Current
Head Differential Load
Capacitance
Head Differential Load
SSI32R2030Al32R2031A
4K
Resistance (Rd)
SSI32R2030AR/32R2031AR
560
WDI Pulse Width
Vii = 0.2V, Vih = 2.4V
(Ref: Figure 1)
Vii = 0.2V, Vih = VCC
Write Current Range (IW)
PWH
37
ns
PWL
5
ns
PWH
20
ns
PWL
5
ns
10
3-87
700
35
mA
SSI 32R2030Al2031 A
5V, 2, 4.;.Channel Thin-Film
Read/Write Device
READ CHARACTERISTICS
RecOmmended operating conditions apply unless otherwise specified. CL (RDX, ROY) < 20 pF,
RL (RDX, ROY) = 1 kn.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Differential Voltage Gain
= 1 mVpp @1 MHz
Ilsl < 50, Vin = 1 mVpp
200
250
300
VN
Voltage BW
-1dB
Vin
-3dB
Input Noise Voltage
Differential Input Capacitance
Differential Input Resistance
20
60
MHz
35
70
MHz
= 15 MHz, Lh = 0, Rh = 0
= 1 mVpp, f =5 MHz
Vin = 1 mVpp, f = 5 MHz
BW
0.6
0.85
nV/..JHz
Vin
27
35
pF
SSI32R2030Al2031A
835
2600
0
SSI32R2030AR/2031AR
360
550
0
Dynamic Range
AC input voltage where gain
falls to 90% of its small signal
gain value, f = 5 MHz
3
6
mVpp
Common Mode Rejection Ratio
Vin!= 0 VDC + 100 mVpp
@5MHz
45
80
dB
Power Supply Rejection Ratio
100. mVpp @ 5 MHz on VCC
40
70
dB
Channel Separation
Unselected channels driven
with Vin = 0 VDC + 100 mVpp
45
Output Offset Voltage
dB
-300
Single Ended Output Resistance
f = 5MHz
Output Current
AC coupled load, RDX to ROY
RDX, ROY Common Mode
Output Voltage
mV
40
0
1.4
2.0
3-88
+300
mA
vcc1/2
3.5
VDC
SSI 32R2030A/2031 A
5V, 2, 4-Channel Thin-Film
Read/Write Device
SWITCHING CHARACTERISTICS
Recommended operating conditions apply unless otherwise specified. IW = 20 rnA, Lh = 1.0 IlH, Rh
f(Oata) = 5 MHz.
= 30n
PARAMETER
CONDITIONS
R/W
Read to Write
Write to Read
CS
NOM
MAX
UNIT
R/W to 90% of write current
0.1
1.0
Il5
R/Wto 90% 01
100 mV Read signal envelope
0.5
1.0
Il5
Unselect to Select
CS to 90% of write current or
to 90% of 100 mV 10 MHz
0.4
1.0
Il5
Select to Unselect
CS to 10% of write current
0.4
1.0
Il5
To 90% of 100 mV 10 MHz
Read signal envelope
0.2
1.0
Il5
2.0
3.6
Il5
0.2
1.0
Il5
20
32
ns
HSO,1 to any Head
WUS:
MIN
Safe to Unsafe (T01)
Write mode, loss of WOI
transitions. Defines maximum
WOI period for WUS operation
Unsafe to Safe (T02)
Fault cleared from first neg
WOI transition
Head Current:
Lh
0.6
= 0, Rh = 0
WOI to Ix - Iy (T03)
from 50% points
Asymmetry
WOI has 1 ns rise/fall time
Rise/fall Time
10% to 90% points
1.0
ns
6
12
ns
TD2
~I
WDI
\
WUS
HEAD
CURRENT
(Ix -Iy)
/
FIGURE 1: Write Mode Timing Diagram
3-89
\
(
SSI 32R2030A/2031 A
5V, 2, 4-Channel Thin-Film
Read/Write Device
Worst Case Read Input Noise Voltage vs. Input Impedance for SSI 32R2030AR/2031AR
Case 1:
IC Base sheet resistance = Maximum
Hence, IC bias Current = Minimum
Tj
Case 2:
= 25°C
Tj
= 110°C
Units
nVtfHZ
Vn (Max)
.7
0.85
Rin (Min)
450
475
Q
Cin (Max)
28
30
pF
IC Base sheet resistance = Minimum
Hence, IC bias Current = Maximum
Tj
= 25°C
Tj
= 110°C
Units
nVtfHZ
Vn (Max)
.58
.65
Rin (Min)
360
400
Q
Cin (Max)
33
35
pF
Worst Case Read Input Noise Voltage vs. Input Impedance for SSI 32R2030N2031A
Case 1:
IC Base sheet resistance = Maximum
Hence, IC bias Current = Minimum
Tj
Case 2:
= 25°C
Tj
= 110°C
Units
nVtfHZ
Vn (Max)
.7
0.85
Rin (Min)
1525
1895
Q
Cin (Max)
28
30
pF
IC Base sheet resistance = Minimum
Hence, IC bias Current = Maximum
Tj
= 25°C
Tj
= 110°C
Units
nVtfHZ
Vn (Max)
.58
.65
Rin (Min)
835
1100
Q
Cin (Max)
33
35
pF
3-90
SSI32R2030AJ2031A
5V, 2, 4-Channel Thin-Film
ReadlWrite Device
PACKAGE PIN DESIGNATIONS
(Top View)
GNO
GNO
GNO
20
CS
HOX
2
19
RfN
16
c:S"
HOY
3
18
WC
4
17
ROY
HOX
2
15
RIW
H1X
HOY
3
14
WC
H1Y
H1X
4
ROY
H2X
H1Y
5
32R2030A 13
2
Channels 12
ROX
VCC2
6
11
HSO
NlC
7
10
VCCl
WUS
8
9
WOI
ROX
6
32R203OA 16
4
Channels 15
H2Y
7
14
HS1
H3X
8
13
VCCl
H3Y
9
12
WOI
10
11
WUS
VCC2
5
HSO
2o-Pin SOL, SOV
16-Pin SOL
24
~
N/C
2
23
RlW
HOX
3
22
N/C
HOY
4
21
WCADJ
WC
H1X
5
20
H1Y
6
ROY
H2X
7
32R2031A 19
4
Channels 18
ROX
H2Y
8
17
HSO
H3X
9
16
HS1
H3Y
10
15
VCC1
N/C
11
14
WOI
VCC2
12
13
WUS
24-Pln SOL, SOV
THERMAL CHARACTERISTICS: Gja
16-Pin SOL
105°CIW
20-Pin SOL
95°C/W
20-Pin SOV
125°CIW
24-Pin SOL
80°CIW
ORDERING INFORMATION
PART DESCRIPTION
SSI32R203OA
16-Pin SOL
ORDER NUMBER
PACKAGE MARK
32R2030A-2CL
32R2030A-2CL
20-Pin SOL
32R2030A-4CL
32R2030A-4CL
20-Pin SOV
32R2030A-4CV
32R2030A-4CV
SSI32R2031A
24-Pin SOL
32R2031A-4CL
32R2031A-4CL
24-Pin SOV
32R2031A-4CV
32R2031A-4CV
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
0194 - rev.
©1991 Silicon Systems,lnc.
I
Notes:
3-92
551 32R2041 RW
4, 6-Channel, Two-Terminal
Read/Write Device
lv' ti' na, mtt';; ,6" tt' ;1
December 1993
DESCRIPTION
FEATURES
The 551 32R2041 RW Read/Write device is a bipolar
monolithic integrated circuit designed for use with twoterminal thin-film recording heads. It provides a low
noise read amplifier, write current control and data
protection circuitry for up to 6 channels. Power supply
fault protection is provided by disabling the write current generator during power sequencing. System write
to read recovery time is significantly improved by
controlling the read channel common mode output
voltage shift in the write mode. The 551 32R2041 RW
requires +5V and +12V power supplies, and provides
internal 7000 damping resitors.
•
•
High performance:
Read mode gain = 250 V/V
Input noise = 0.80 nV/*IZ max.
Input capacitance = 22 pF max.
Write current range = 10 mA to 40 mA
Head voltage swing = 7 Vpp
Write current rise time = 9 ns
Enhanced. system write to read recovery time
•
Differential ECl-like Write Data input
•
Power supply fault protection
• Write unsafe detection
• +5V, +12V power supplies
BLOCK DIAGRAM
veo vee
GND
PIN DIAGRAM
wus
HOX
HOX
:iIiIIH
ROX
NlC
H1X
cs
HOV
H1Y
RIW
HIX
H2X
WC
H2Y
RDY
H3X
RDX
HIV
ROY
WD
GND
HOY
H2X
c:r..".",.".",.".",.".",++!
wtlLF-="""""""--:F'12.3
H3Y
HSO
H2Y
H4X
HS1
H'X
H4Y
HS2
H5X
VCC
H'V
H5Y
WD
NIC
W!)
H4V
NlC
WUS
HSl(
NIC
VDD
NIC
NIC
NIC
NlC
NlC
NlC
H4X
H5V
36·lEADSOM
6·Channel
CAUTION: Use handling procedures necessary
for a static sensitive component.
t293- rev.
3-93
II
SSI32R2041RW
4,6-Channel, Two-Terminal
Read/Write Device
CIRCUIT OPERATION
READ MODE
The SSI 32 R2041 RW addresses up to 6 two-terminal
thin film heads providing write drive or read amplification. Head selection and mode control is accomplished
with pins HSn, es and R/W, as shown in Tables 1 & 2.
Internal resistor pullups, provided on pins es and R/W
will force the device into a non-writing condition if either
control line is opened accidentally.
WRITE MODE
The write mode configures the SSI32R2041 RW as a
current switch and activates the Write Unsafe (WUS)
detection circuitry. Write current is toggled between
the X and Y direction of the selected head on each low
to high transition on the WD, Write Data input. (See
figure 1.)
A preceding read operation initializes the Write Data
Flip Flop (WDFF) to pass write current in the Xdirection of the head, i.e., into the X-port of the head.
HnX will be biased higher than HnY.
The read mode configures the SSI 32R2041 RW as a
low noise differential amplifier and deactivates the
write current generator and write unsafe detection
circuitry. The RDX and RDY outputs are emitter
followers and are in phase with the "XU and ny" head
ports. These outputs should be Ae coupled to the load.
The RDX, RDY common mode voltage is maintained at
the write mode value, minimizing the transient between
write mode and read mode, substantially reducing the
write to read recovery time in the subsequent Pulse
Detection circuitry.
IDLE MODE
The idle mode deactivates the internal write current
generator, the write unsafe detector and switches the
RDX, RDY outputs into a high impedance state. This
facilitates multiple device applications by enabling the
read outputs to be wire-OR'ed and the write current
programming resistor to be common to all devices.
TABLE 1: Mode Select
The magnitude of the write current (O-pk) is given by:
Iw= Vwc
Rwc
where Vwc (We pin voltage) = 1.65V ± 5%, is programmed by an external resistor Rwc, connected from
pin we to ground. In multiple device applications, a
single Rwc resistor may be made common to all devices. The actual head current lx, y is given by:
Power supply fault protection improves data security
by disabling the write current generator during a voltage fault or power supply sequencing. Additionally, the
write unsafe detection circuitry will flag any of the
conditions listed below as a high level on the open
collector output pin, WUS. Up to two positive transitions on the WD, Write Data input line, after the fault is
corrected, are required to clear the WUS flag.
o
o
o
WD frequency too low
Device not selected
Open head
R/W
MODE
0
0
0
1
1
0
Write
Read
Idle
Idle
1
1
TABLE 2: Head Select"
HS2
0
0
0
0
I
Iw
x,y 1+Rh/Rd
where:
Rh = head resistance + external wire resistance, and
Rd = damping resistance.
CS
1
1
0= Low level
HS1
0
0
HSO
0
1
1
1
1
0
1
0
1
2
3
0
0
1 = High level
·Unused heads should be left open.
Device in read mode
• No write current
0
3-94
HEAD
0
4
5
SSI32R2041RW
4, 6-Channel, Two-Terminal
Read/Write Device
PIN DESCRIPTION
NAME
TYPE
DESCRIPTION
HSO - HS2
I
Head Select
CS
I
Chip Select: a low level enables the device
RlW
I
WUS
O·
Write Unsafe: Open collector output, a high level indicates an unsafe writing
condition
I
Differential Write Data inputs: a positive transition on WD toggles the direction
of the head current
WD,WD
HOX - H5X
HOY -H5Y
I/O
RDX,RDY
O·
WC
VCC
VDD
GND
.
-
ReadlWrite: a high level selects Read mode
X, Y Head Connections: Current in the X-direction flows into the X-port
X, Y Read Data: differential read data output
Write Current: used to set the magnitude of the write current
+5V Logic Circuit Supply
+12V
Ground
·When more than one RIW device is used, these signals can be wire OR'ed.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may permanently damage the device.
PARAMETER
SYMBOL
DC Supply Voltage
Write Current
RATING
VDD
-0.3 to +13.5 VDC
VCC
-0.3 to +6 VDC
Iw
100 mA
Digital Input Voltage
Yin
-0.3 to VCC +0.3 VDC
Head Port Voltage
VH
-0.3 to +8 VDC
Differential Port Voltage
IHnX - HnYI
WUS Pin Voltage Range
Output Current
RDX,RDY
WUS
Storage Temperature
dVH
6VDC
Vwus
-0.3 to VCC VDC
10
-10 mA
Iwus
+12mA
Tstg
-65 to + 150°C
3-95
I
SSI32R2041RW
4, 6-Channel, Two-Terminal
Read/Write Device
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
DC Supply Voltage
RATING
VDD
12± 10% VDC
VCC
5± 10% VDC
Tj
+25 to + 135°C
Operating Temperature
DC CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply.
CONDITIONS
PARAMETER
VDD Supply Current
= +135°C)
MAX
UNITS
-
36
44
mA
-
25+ Iw
29 + Iw
mA
Idle Mode
-
3.5
4
mA
Read Mode
-
22
29
mA
Write Mode
-
14
18
mA
9
11.5
mA
540
740
mW
Idle Mode
Power Dissipation (Tj
NOM
Write Mode
Read Mode
VCC Supply Current
MIN
Read Mode
Write Mode
Idle Mode
370+10.35·lw 490 +ll.60lw
115
mW
WD. WD Input Low Current (ilL 1)
VIL 1 = VCC -1.625V
80
WD, WD Input High Current (IIH1)
VIH1 = VCC -0.72V
100
l!A
l!A
vee
VCC
VDC
-1.870
-1 ;625
WD. WD Input Low Voltage (VIL1)
WD. WD Input High Voltage (VIH1)
R/W. CS. HSO-HS2
Input Low Current (IIL2)
VIL2 = 0.8V
R/W. CS. HSO-HS2
Input High Current (IIH2)
VIH2 = 2.0V
87
mW
VCC
VCC
-1.00
-0.720
-0.4
mA
RIW, CS, HSO-HS2
Input Low Voltage (VIL2)
RlW. CS. HSO-HS2
Input High Voltage (VIH2)
WUS Output Low Voltage (VOL)
100
l!A
0.8
VDC
2.0
-
101=4 mA
VDD Fault Voltage
9.0
VCC Fau!t Voltage
3.5
3-96
VDC
VDC
-
0.5
VDC
10.3
VDC
4.2
VDC
SSI32R2041RW
4, 6-Channel, Two-Terminal
Read/Write Device
DC CHARACTERISTICS
(continued)
PARAMETER
Head Current (HnX, HnY)
CONDITIONS
MIN
NOM
MAX
UNITS
Write Mode,
-200
-
+200
!lA
-200
-
+200
!lA
0~VCC~3.5V
0~VDD~9.0V
Readlldle Mode,
o~VCC ~5.5V
o~ VDD ~13.2V
WRITE CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply, Iw = 20 mA, Lh = 500 nH, Rh = 30il
and f(WD) = 5 MHz.
WC Pin Voltage (Vwc)
1.57
1.65
1.73
V
Differential Head Voltage Swing
7
-
-
Vpp
Unselected Head Current
-
-
1
mA(pk)
Differential Output Capacitance
-
-
25
pF
500
700
950
il
WUS = low
1.7
MHz
-
-
-
WUS = high
500
kHz
40
mA
Differential Output Resistance
WDI Transition Frequency
Write Current Range
10
READ CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply CL (RDX, RDY) < 20pF and
RL (RDX,RDY) = 1 kil.
PARAMETER
CONDITIONS
MIN
Differential Voltage Gain
Vin=1mVpp@ 300 kHz
210
250
290
VN
-idB
IZsl<5il, Vin=1 mVpp
35
45
-
MHz
-3dB
IZsl<50, Vin=1 mVpp
50
65
-
MHz
Bandwidth
NOM MAX
UNITS
Input Noise Voltage
BW = 15 MHz, Lh = 0, Rh = 0
0.80
nV/,!Hz
Yin = 1 mVpp, f = 5 MHz
-
0.57
Differential Input Capacitance
15
22
pF
Differential Input Resistance
Yin = 1 mVpp, f = 5 MHz
300
565
Dynamic Range
Peak-to-peak AC input voltage
where gain falls to 90% of its
small signal value, f = 5 MHz
2.0
-
-
mVpp
Common Mode Rejection Ratio
Vcm = 100 mVpp AC Coupled @ 5 MHz
54
100 mVpp@ 5 MHz on VDD
100 mVpp@ 5 MHz on VCC
54
-
-
dB
Power Supply Rejection Ratio
Channel Separation
Unselected channels driven
with 100 mVpp@ 5 MHz,
Vin= 0 mVpp
45
-
-
dB
3-97
0
dB
II
SSI32R2041RW
4, 6-Channel, Two-Terminal
Read/Write Device
READ CHARACTERISTICS
(continued)
PARAMETER
MIN
CONDITIONS
NOM
MAX
UNITS
·400
·
+400
mV
RDX, ROY Common Mode
Output Voltage
Read Mode
2.3
2.9
3.S
VDC
Single Ended Output Resistance
f
=S MHz
.
·
SO
Q
Output Current
AC Coupled Load,
RDX to ROY
3.2
·
.
rnA
Output Offset Voltage
SWITCHING CHARACTERISTICS (See Figure 1)
Unless otherwise specified, recommended operating conditions apply, Iw = 20 rnA, Lh = SOO nH, Rh = 30Q
and f(WD) = S MHz.
R/W
R/W to Write Mode
Delay to 90% of write
current
-
0.2
0.6
J.lS
R/W to Read Mode
Delay to 90% of 100 mV
10 MHz Read signal
envelope or to 90% decay
of write current
-
0.3
0.6
J.lS
CS to Select
Delay to 90% of write
current or to 90% of
100 mV 10 MHz Read
signal envelope
-
0.3
0.6
J.lS
CS to Unselect
Delay 101 0% of write
current
-
0.2
0.6
IlS
HSO, 1, 2 to any Head
Delay to 90% of 100 mV
10 MHz Read signal
envelope
-
0.1
0.4
J.lS
-
0.6
2.0
J.lS
-
1
J.lS
CS
I
-
HSn
WUS
Safe to Unsafe - TD1
1----------
Unsafe to Safe - TD2
Head Current
Prop. Delay - TD3
From SO% points, Lh=O IlH,
Rh=OQ
-
-
32
ns
Asymmetry
WD has SO% duty cycle
and 1ns rise/fali time,
Lh=O Ilh, Rh=OQ
-
-
O.S
ns
Rise/Fall Time
10% - 90% points, Lh=O /lH,
Rh=OQ
-
-
S
ns
Rise/Fall Time
10% - 90% points, Lh=1
Rh=3SQ
/lH,
-
9
-
ns
3-98
SSI 32R2041 RW
4, 6-Channel, Two-Terminal
Read/Write Device
TD'-Ir-_ __
HEAD
CURRENT
(1x·1y)
II
FIGURE 1: Write Mode Timing Diagram
PACKAGE PIN DESIGNATIONS
(Top View)
GND
HOX
~
HOY
N/C
HOX
RlW
H1X
CS
HOY
WC
H1Y
H2X
Rfii
WC
H2Y
ROY
H3X
ROX
N/C
N/C
THERMAL CHARACTERISTICS*: 9ja
24-Lead VSOP
110°C/W
H1X
RDY
H1Y
RDX
GNO
24-Lead SOL
80°C/W
H2X
HSO
H3Y
36-Lead SOM
70°CIW
HSO
H2Y
HS1
H4X
HSl
H3X
VCC
H4Y
HS2
H3Y
WD
H5X
VCC
N/C
W[j
H5Y
WUS
N/C
WO
WO
N/C
WUS
N/C
VOO
N/C
N/C
N/C
N/C
N/C
N/C
·Care should be taken not to exceed the
maximum junction temperature. For example, on the 24-Lead VSOP, at a write
current of 25 rnA, the maximum ambient
temperature should not exceed 50°C.
VDD
24-Lead SOL, VSOP
36-Lead SOM
6-Channel
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use 01 this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in speCifications at any time without notice. Accordingly, the reader is cautioned to verily that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680'7022 (714) 573-6000, FAX (714) 573-6914
1293- rev.
3.-99
©1993 Silicon Systems,lnc.
Notes:
3-100
SSI 32R2063R164R165R
5V, 4-Channel Thin Film
Read/Write Device
'mIinil Mr.] i; ,6"t.] "
October 1993
DESCRIPTION
FEATURES
The SSI 32R2063R/64R/65R are Bipolar monolithic
integrated circuits designed for use with two-terminal
recording heads. They provide a low noise read
amplifier, write current control, and data protection
circuitry for up to four channels. The SSI 32R2063R
option provides internal 3500 damping resistors.
Damping resistors are switched in during Write mode
and switched out during Read mode. The SS132R20631
64/65 option does not provide a damping resistor.
Power supply fault protection is provided by disabling
the write current generator during power sequencing.
System write to read recovery time is significantly
improved by making the read channel outputs high
impedance. The device also offers multiple channel
"servo bank write" capability to assist in servo writing
operations. Servo write is selected either with a TTL
input (32R2063R/32R2064R) or with the WUS/SE pin
(32R2065R).
•
•
+5V ±10% supply
low power
• PO
- PO
•
= 120 mW Read mode (Nom)
= 7 mW Idle (Max)
High Performance:
- Read mode gain = (U) 150, (W) 250 V/V
-Input noise = 0.56 nVhiHz (Nom)
-Input capacitance
- Max write current riselfall time
(typical head)
- Head voltage swing
•
•
•
•
•
•
The SSI 32R2063R/64R/65R require only a +5.0V
power supply and are available in a variety of packages
and gain options.
GNO
= 3.4 Vpp min
Self switching damping resistance
Write unsafe detection
Power supply fault protection
Head short to ground protection
Differential Eel-like (32R2063R) or TTL
(32R2064R, 32R2065R) write data Inputs
PIN DIAGRAM
WU&'SE
HOX
RoW
= 15 nsec
Servo bank-write capability
BLOCK DIAGRAM
vee
= 16 pF (Nom)
- Write current range = 1-35 mA
~
GNO
20
HOX
19
RlW
HOY
18
we
H1X
17
ROY
HOY
~
ADX
ADY
H'X
HIV
WD
WlJJWD'
H2X
H2Y
H1Y
5
H2X
6
16
ROX
15
HSO
H2Y
14
HS1
H3X
13
Nle
H3Y
12
WOI
11
'SE:
vee
10
32R2063
4
Channels
20-lead SOL, VSOP
HSO
HS'
H3X
H3Y
CAUTION: Use handling procedures necessary
for a static sensitive component.
II
SSI32R2063R/64R/65R
5V, 4-Channel Thin Film
Read/Write Device
CIRCUIT OPERATION
The SSI32R2063R/64R/6SR has the ability to address up to 4 two-terminal heads and provide write drive or read
amplification. Mode control and head selection are described in Tables 1 and 2. The TIL inputs RfW, CSand
SE have internal pull-up resistors to prevent an accidental write condition. HSO and HS1 have internal
pulidown(W)lInternal pull up (U) resistors. Internal clamp circuitry will protect the IC from head short to ground
condition in any mode.
a
TABLE 1a: Mode Select (32R2063R, 32R2064R)
CS
R/W
SE
Mode
0
0
1
Single Channel Write. See Table 2.
0
0
0
Servo Write Channels 0, 1,2,3
0
1
1
X
Single Channel Read. See Table 2.
X
X
Idle.
TABLE 1b: Mode Select (32R2065R)
CS
R/W
WUS/SE
0
0
*
0
0
Vcc+1.S*
0
1
X
Single Channel Read. See Table 2.
X
Idle.
Mode
Single Channel Write. See Table 2.
Servo Write Channels 0, 1, 2, 3
"----
1
X
'WUS/SE functions as WUS in Write Mode unless it is pulled above Vce.
TABLE 2: Head Select
HS1
HSO
Head
0
0
0
0
1
1
1
0
2
1
1
3
SSI 32R2063R/64R/65R
5V, 4-Channel Thin Film
ReadlWrite Device
WRITE MODE
POWER SUPPL Y FAULT PROTECTION
Taking both CS and R/W low selects Write mode which
configures the SSI 32R2063R/64R/65R as a current
switch and activates the Write Unsafe (WUS) detector
circuitry. On the 32R2063R, head current is toggled
between the X and Y side of the selected head on each
low to high transition of WD-WD. On the 32R2064RI
65R, head current is toggled between the X and Y side
of the selected head on each high to low transition of
the Write Data Input (WDI). Note that a preceding Read
to Write transition or Idle to Write transition initializes
the Write Data Flip-Flop to pass write current into the
"X" side of the device. In this case, the Y side is higher
potential than the X side. The magnitude of the write
current (O-pk) is given by:
A voltage fault detection circuit improves data security
by disabling the write current generatorduring a voltage
fault or power startup regardless of mode. Note that
WUS does not necessarily turn on to flag a power
supply fault condition.
Iw=Aw. Vwc =K/
R
Rwc /F1wc
HEAD SHORT TO GROUND PROTECTION
The SSI32R2063R/64R/65R provides a head short to
ground protection circuit in any mode. In Idle or Read
Mode, current out of the head port will not exceed 20
mA if any head is shorted to ground. In Write mode, if
any head is shorted to ground (regardless if it is
selected or not) the write current generator will turn off,
the WUS flag will go high, and current will be limited to
less than 1 mA out of the head port.
WRITE UNSAFE
where Aw is the write current gain.
RWC is connected from pin WC to GND. Note the
actual head current lx, y is given by:
Any of the following conditions will be indicated as a
high level on the Write Unsafe, WUS, open collector
output.
WDI frequency too low
Device in Read mode
Device not selected
Device in Servo Write mode
No head current
Open head
Head short to ground
Ix y=
Iw
,
1 + Rh/Rd
Where:
Rh = Head resistance plus external wire
resistance
Rd
= Damping resistance
In Write mode a 350n damping resistor is switched in
across the Hx, Hy ports (32R2063R/64R/65R). The
unselected head potential is kept at ground.
WDI frequency too low is detected if the WDI frequency
falls below 1.67 MHz (typ). Consult the WUS Safe to
Unsafe timing for range of frequency detection.
SERVO WRITE MODE
Device in Read mode, Device in servo Write mode
and Chip disabled will flag WUS if R/W is high, if SE
is high, or CS is high.
Taking SE low and RIW low (32R2063R/64R) or taking
WUS/SEto Vcc+ 1.5 (32R2065R) activates Servo Write
mode. This mode allows forwriting to multiple channels
at once, which is useful during servo formatting. In this
mode, the write driver will drive channels 0,1,2, and 3
simultaneously.
No head current will flag WUS if Rwc =
selected head is present.
Head opened will flag WUS if Rh =
3-103
00
00
and the
SSI 32R2063R/64R/65R
5V,4-Channel Thin Film
ReadlWrite Device
Head short to ground is described in the preceding
paragraph.
Upon entering Write mode, WUS is valid after two low
to high transitions of WD-WD (32R2063R), or two high
to low transitions of WDI (32H2064R/65R) following
the required Read-Write transition time (0.6 JlS max).
After the fault condition is removed, two positive
transitions of WD-WD (32R2063R), or two negative
transitions of WDI (32R2064R165R) are required to
clearWUS.
READ MODE
emitter followers. They should be AC coupled to the
load. The HnX, HnY inputs are non-inverting to the
RDX, RDY outputs.
Note that in Idle or Write mode, the read amplifier is
deactivated and RDX, RDY outputs become high
impedance. This facilitates multiple RIW applications
(wired-OR RDX, RDY) and minimizes voltage change
when switching from Write to Read mode. Note also
that the write current source is deactivated for both the
Read and Idle mode. The unselected head potential is
kept atground.
IDLE MODE
The Read mode configures the devices as a low noise
differential amplifier and deactivates the write current
generator. The damping resistor is switched out of the
circuit allowing a high impedance input to the read
amplifier. The RDX and RDY output are driven by
Taking CS high selects the Idle mode which switches
the RDX and RDY outputs into a high impedance state
and deactivates the device. Power consumption inthis
mode is held to a minimum. The head potential is kept
at ground.
3-104
551 32R2063R/64R/65R
5V, 4-Channel Thin Film
ReadlWrite Device
PIN DESCRIPTION
CONTROUST ATUS
NAME
TYPE
DESCRIPTION
CS
I
Chip Select Input. A logical low level enables the device.
R/Wt
I
ReadIWrite. A logical high level enables Read mode. A logical low level
enables Write mode.
SE
I
Servo Enable. A low level enables servo bank Write mode. See Servo Enable
section (32R2063R, 32R2064R).
HSO,HS1
I
Head Select. Decoded address selects one of 4 channels. See Table 2.
WUSt
0
Write Unsafe. A high level indicates an unsafe writing condition. See WUS
section (32R2064R).
WUS/SEt
I/O
Write Unsafe/Servo Enable. When in Servo Bank Write mode, pulling this pin
above Vcc enables servo bank write. See Servo Enable section. Otherwise,
a high level indicates an unsafe writing condition. See WUS section
(32R2065R).
I
WC
Write Current. Sets the write current through the recording head.
HEAD TERMINAL CONNECTIONS
HOX-H3X
HOY-H3Y
X,Y Head Connections
DATA INPUT/OUTPUT
WDlt
I
Write Data In. A negative transition of WDI changes the direction of current
in the recording head (32R2064R, 32R2065R).
WD,WDt
I
Differential Write Data In. A positive transition of WD-WD changes the
direction of current in the recording head (32R2063R).
-~
RDX,RDYt
0
Differential Read Data Out. Emitter follower output.
POWER
VCC
+5 V power supply
GND
Ground
t When more than one Read/Write device is used, signals can be wire OR'ed.
3-105
SSI 32R2063R/64R/65R
5V, 4-Channel Thin Film
ReadlWrite Device
ELECTRICAL SPECIFICATIONS
Current maximums are currents with the highest absolute value
ABSOLUTE MAXIMUM RATINGS
Operation beyond the maximum ratings may damage the device.
RATING
PARAMETER
DC Supply Voltage
VCC
Write Current'
Iw
-0.3 to 7V
60mA
Digital Input Voltage
Yin
-0.3 to VCC+0.3V
Head Port Voltage
VH
-0.3 to VCC+0.3V
WUS Pin Voltage
Output Current
Vwus
10
-6mA
Iwus
+SmA
RDX,RDY
WUS
VCC+0.3V
Junction Operating Temperature
+135°C
Storage Temperature
-65 to + 150°C
RECOMMENDED OPERATING CONDITIONS
CONDITIONS
PARAMETER
DC Supply Voltage
VCC
Ambient Operating Temperature
5± 10%V
0° < Ta < 75°C
TEST CONDITIONS
Recommended operating conditions apply.
PARAMETER
CONDITIONS
Write Current, Iw
1-35 mA
Head Inductance, Lh
1 IlH
Head Resistance, Rh
30n
WD Frequency
5 MHz
WD,WD riselfall time (32R2063R)
1ns
WDI riselfall time (32R2064R/2065R)
1 ns
1.25/Iw, WUS available in bonding option.
WDI
wus
HEAD
CURRENT
(Ix -Iy)
'-----I
f--~/
FIGURE 1: Write Mode Timing Diagram
3-153
II
SSI32R2420
5V, 4-Channel
2-Terminal Read/Write Device
PACKAGE PIN DESIGNATIONS
(Top View)
GND
11
CS
VCC
20
SE
HOX
2
12
RlW
H3Y
2
19
WDI
HOY
3
13
WC
H3X
3
18
N/C
H1X
4
14
ROY
H2Y
4
17
HSI
H1Y
5
15
RDX
H2X
5
16
HSO
H2X
6
16
HSO
H1Y
6
15
RDX
H2Y
7
17
HS1
H1X
7
14
ROY
H3X
8
18
N/C
HOY
8
13
WC
H3Y
9
19
WDI
HOX
9
12
RiW
VCC
10
20
SE
10
11
CS
GND
20-Lead VSOP
20-Lead VSOP
(Invened)
32R2420RW-4CV (VSOP)
32R2420W-4CV (VSOP)
32R2420RIW-4CV
32R24201W-4CV
CAUTION: Use handling procedures necessary
for a static sensitive component.
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights ortrademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1993 Silicon Systems, Inc.
3-154
1193
Section
4
DISCRETE
CHANNEL
II
4
4-0
SSI 32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
tiP Ii ni' mtt] i; 'F" ttl Ii
October 1993
DESCRIPTION
FEATURES
The SSI 32D5396/96A Data Synchronizer/1, 7 RLL
ENDEC provides data recovery and data encoding for
storage systems which employ a 1, 7 RLL encoding
format. Data synchronization is performed with a fully
integrated high performance PLl. A zero phase restart
technique is used to minimize PLL acquisition time.
The VCO frequency setting elements are incorporated
within the SSI 32D5396/96A for enhanced performance and reduced board space. Data rate is established with a single external programming resistor. The
SSI 32D5396/96A utilizes an advanced bipolar process technology which affords precise decode window
control without the requirement of external devices.
The SSI 32D5396/96A requires a single +5V supply
and is available in 44-Pin PLCC and 36-Lead SaM
packages.
•
Data synchronizer and 1, 7 RLL ENDEC
•
Dual bit NRZ bus
•
24 to 54 Mbit/s operation
· Data rate programmed with a single
external resistor or current source
•
Fast acquisition phase locked loop with
improved zero phase restart technique
•
Fully integrated data separator
• No external delay lines or active devices
required
•
Programmable decode window symmetry
control
• Includes delayed read data and VCO clock
monitor points
•
Programmable write precompensation
•
Hard and soft sector operation
•
Uses standard 5V ± 5% supply
BLOCK DIAGRAM
RR
RClK
weLK
.-----1, RG
NRZO
C=:J'---y NRZ1
1093
A"'LOG
GND
4-1
DIGITA.L
G'D
* No WD Flip-Flop on 32D5396A
II
•
SSI 32D5396/5396A
Oata Sync/1, 7c RL(ENDEC
with.Write Pre,comp. and Window Shift
READ OPERATION
FUNCTIONAL DESCRIPTION
The data synchronizer utilizes a fully integrated fast
acquisition PLL to accurately develop the decode
window. Read Gate, RG, initiates the PLL locking
sequence and selects the PLL reference input; a high
level (Read Mode) selects the RD input and a low level
selects the external reference clock.
DATA/CLOCK RECOVERY CIRCUIT
The circuit is designed to perform data recovery and
data encoding in rotating memory systems which utilize
a 1, 7 RLLencodingformat.lnthe read mode the circuit
performs data synchronization, sync field search and
detect, address mark detect, and data decoding. In the
write mode, the circuit convertsNRZ data into the 1, 7
RLL format described in Table 1, performs write
precompensation, generates the preamble field and
inserts address marks as requested ..
In the read mode the falling edge of ORO enables the
phase detector while the rising edge is phase compared to the rising edge of veo. As depicted in Figure
1, DRDisa 1/3 cell wide (TVeO/2) pulse whose leading
edge is defined by the leading edge of RD. A decode
window is developed from theVeO clock.
This data rate is established by a single1%·external
resistor, RR, connected from the IREF pinto VPA. This
resistor establishes a reference current which sets the
VCO center frequency and the phase detector gain.
.
The value of this resistor is given by:
RR = (185/DR) - 1.7 kn
Where: DR
Shifting the symmetry of the veo cloc~effectively
shifts the relative position of the ORO pulse within the
decode window. Decode window control is provided
via the WS controls.
In the non-read modes, the PLL is locked to the
external reference clock. When the reference input to
the PLL is switched, the veo is stopped momentarily,
then restarted in an accurate phase alignment with the
next PLL referenCe input pulse, and the veo cloGk.
divider is reset.
= data rate in MbiVs
Alternately, the IREF pin can be driven from the SSI
3204666 in a constant density recording application.
IREF (mA)
=
3
185/;R _ 117
ADDRESS MARK DETECT
The circuit employs a dual mode phase detector; harmonic in the read mode and non-harmonic in the write
and idle modes. In the read mode, the harmonic phase
detector updates the PLL with each occurrence ofa
DLYD DATA pulse. In the write and idle modes, the
non-harmonic phase detector is continuously enabled,
thus maintaining both phase and frequency lock. By
acquiring Qoth phase and frequency lock to the input
reference frequency and utilizing a zero phase restart
technique, false lock to DLYD DATA is eliminated.
In soft sector read operation the circuit mustfirst detect
an address mark to be able to initiate the rest of the read
lock sequence. An address mark consists of two sets
of 7 "0" patterns followed by two sets of 11 "0" patterns.
To begin the read lock sequence the Address Mark
Enable (AMENB) is asserted .Iow by the controller. The
address mark detect (AMD) circuit then initiates a
search of the read data (R D) for an address mark. First
the AMD looks for a set of 6 "O"s within the 7 "0"
patterns. Having detected a 6 "0" the AMD then looks
for a 9 "0" set within the 11 "O"s.11 AMD does not detect
9 "O"s within 5 RD bits after detecting 6 "O"s it will restart
the address mark detect sequence and look for 6 "O"s.
When the AMD has acquired a 6 "0," 9 "0" sequence,
the AMD transitions low. AMD will remain low for the
duration of AMENB. When AMENB is released, AMD
will be released.
The phase detector incorporates a charge pump in
order to drive the loop filter directly. The polarity and
width of the output current pulses correspond to the
direction and magnitude of the phase error.
The READ GATE (RG) and WRITE GATE (WG) inputs
control the mode of the data/clock recovery section oi
the chip.
RG is an asynchronous input that should be initiated at
the start of a valid preamble or address mark. WG is
also an asynchronous input, but should not beterminated prior to the last output write data pulse.
PREAMBLE SEARCH
After the Address Mark (AM) has been detected, a
Read Gate (RG) can be asserted high, initiating the
remainder of the read lock sequence. When RG is
asserted, an internal counter counts positive transi4-2
SSI 32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
defined cell boundaries. The NRZ input data must be
synchronous with the rising edges of the WCLK.
tions of the incoming read data (RD) looking for 3
consecutive "3T' preambles. Once the counter reaches
count 3 the internal read gate enables, switching the
phase detector from the external reference clock to the
delayed read data input (ORO); atthe same time a zero
phase (internal) restart signal restarts the VCO in
phase with the ORO. This prepares the VCO to be
synchronized to data when the bit sync circuitry is
enabled after VCO lock is established.
Write precompensation circuitry is provided to compensate for media bit shift caused by intersymbol
interference. The circuit recognizes specific write data
patterns and can add or subtract delays in the time
position of write data bits to counteract the read back
bit shift. The magnitude of the time shift, TPC, is
determined by an external resistor on the WC8 pin.
The circuit performs write precompensation according
to the algorithm ouUined in Table 4.
VCO LOCK AND BIT SYNC ENABLE
When the internal counter counts 16 more data pulses
or a total of 19 positive transitions from RG enable, an
internal VCO lock signal enables. The VCO lock signal
activates the decoder bit synchronization circuitry to
define the proper decode boundaries. Also, at count
19, the internal RCLK source switches from the external reference clock to VCO clock signal which is phase
locked to ORO. The VCO is assumed locked at this
point. A maximum of 2 RCLK time periods may occur
for the RCLK transition, however, no short duration
glitches will occur. After the bit sync circuitry sets the
proper decode window (VCO in sync with RCLK and
RCLK in sync with the data) NRZ is enabled and data
is toggled in to be decoded for the duration of the read
gate.
The 881 3205396 includes an internal write data f1ipflop that divides the WD frequency by 2. The 881
32D5396A does not include the WD flip-flop, so this
device must be used with a preamp that includes a WD
flip-flop.
SOFT SECTOR
In hard sector operation, a high AMENB disables the
Address Mark Detection circuitry and AMD remains
inactive. A hard sector read operation does not require
an address mark search but starts with a preamble
search as with soft sector and sequences identically. In
all respects, with exception to the address mark search
sequence, hard sector read operation is the same as
soft sector read.
In soft sector operation, when read gate (RG) transitions low, VCO source and RCLK source switch from
RD and 2VCO/3, respectively, to the external reference clock. At the same time the VCO (internal) lock
goes inactive but the VCO is locked to the external
reference clock. After delay of 1 NRZ time period (min)
from RG low, the write gate (WG) can be enabled low
while NRZ is maintained (NRZ write data) low. The
address mark enable (AMENB) is made active (low) a
minimum of 1 NRZ time period later. The address mark
(consisting of 7 "O"s, 7 "O"s, 11 "O"s, 11 "O"s) and the
19 x "3T" preamble is then written by WD. While the
preamble is being written, WCLK is clocking in an all "0"
NRZ bit pair. At the end of Ihe write cycle, 8 WCLK
cycles of NRZ "0" lime passes 10 insure the encoder is
flushed of data; WG then goes high. WD stops toggling
a maximum of 1 NRZ time periods after WG goes high,
WRITE MODE
HARD SECTOR
In the write mode the circuit converts NRZdata from the
controller into 1, 7 RLL formatted data for storage on
the disk. The circuit can operate with a soft or hard
sector hard drive.
In hard sector operation, when read gate (RG) transi"
tions low, VCO source and RCLK switch references
and VCO lock (internal) goes inactive as with soft
sector but the AMENB (Address Mark Enable) is kept
high.
HARD SECTOR OPERATION
In soft sector operation the circuit generates a
"7,7,11,11" address mark and a preamble pattern
("3T's"). In hard sector operation the circuit generates
a 19 x ''3T'' preamble pattern but no preceding address
mark.
The circuit then sequences from RG disable to WG
enable and NRZ active as in soft sector operation.
NRZ'data is clocked into the circuit and latched on
4-3
II
SSI32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
TEST POINTS
The SSI 3205396 provides two (2) test points which can be utilized to evaluate window margin
characteristics.
(a) DRD,delayed read data - the positive edges represent the data bit pO!jlition
(b) VeOREI7, the veo reference which represents the input to the Phase Detector, synchronizer, and
1,7 decoder
The following figure describ~s the relationship between the various test points:
VCOREF
FIGURE 1: Te.st Poln.t Relationships
o
1,7RLL DATA
PHASED.ET
ENABLE .•
fmC·
NRZ alT CELL
.
l,---------,I'
, - - I_
_- - - ' -
I,
L
141~-------'-------l~~141---------"I~1
NOTE: • Denotes internal signal
FIGURE 2: Data Synchronization Waveform
4-4
SSI 32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
I
NRZ1
I
NRZO
X ~ X ~
X X ~ X X ~
t= n
PRESENT
I
Y2
t= n
Y3
Y1
PREVIOUS
CODE WORD
LAST BIT
I
I
NRZ1
NRZO
t=n+1
X
t=n+1
X
I
Y2
Y3
I
Y1
1.7 CODE
II CODEWORD
NEXT
I FIRST BIT
1 CODEWORD
FIGURE 3: NRZ Data Word Comparision to 1, 7 Code Word
(See Tables 1, and 2 for Decode Scheme)
; I
NRZ'
I
I
NRZ'
~DATAO
.1'"
------l~~
I
NRZ,
NRZ,
DATA 1
I
NRZ,
"'1'"
READ/WRITE DIRECTION
NRZ::
DATA2--
------I~~
FIGURE 4: Parallel/Serial Conversion Format
4-5
I
NRZ DATA
SSI32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
TABLE 1: Decode Table for (1, 7) RLL Code Set
ENCODED READ DATA
DECODED DATA
N N
Previous
Present
Next
yy
yyy
yy
RR
ZZ
2' 3'
0
1 0
1
XX
X 0
X 0
X 0
X 1
X 1
X 1
0
1 0
1
XX
123
000
000
000
1 0 0
1 0
1 0
1 0
1 0
1 0
1 0
0 1
001
001
1 0 1
1 2
XX
XX
XX
XX
0
1 0
1
0
1 0
1
XX
XX
XX
XX
1 0
0 1
0 0
1
1 1
1 1
1 0
1 0
0 1
0 0
0
0 1
0 0
(preamble)
0
1 0
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
TABLE 2: Encode Table for (1, 7) RLL Code Set
NRZ DATA
Present
N N
R R
Z
Z
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
NOTE: X
1
1
1
ENCODED WRITE DATA
Next
N N
R R
Previous
Present
Z
Z
Y
Y
Y
Y
1
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
3
X
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
2
0
0
1
0
3
0
1
0
1
0
0
0
0
= Don't Care
4-6
1
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
SSt 32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
TABLE 3: Clock Frequency
WG
RG
VCOREF
RCLK
DECCLK
ENCCLK
MODE
1
0
FREF
FREF/3
N/A
N/A
IDLE
1
1
RD
VCO/3
VCO
FREF
READ
0
0
FREF
FREF/3
FREF
FREF
WRITE
0
1
Undefined
Undefined Undefined
Undefined Undefined
Note 1: Until the VCO locks to the new source, the VCO entries will
be FREF.
2: Until the VCO locks to the new source, the VCO/3 entries will
be FREF/3.
TABLE 4: Write Precompensatlon Algorithm
BIT
BIT
BIT
BIT
BIT
n-2
n-1
n
n+1
n+2
BITn
1
0
1
0
1
NONE
0
0
1
1
0
1
0
0
0
0
EARLY
0
0
1
0
1
LATE
LATE:
COMPENSATION
NONE
Bit n is time shifted (delayed) from its nominal
time position towards the bit n+ 1 time position.
EARLY: Bit n is time shifted (advanced) from its nominal
time position towards the bit n-1 time position.
TABLE 5: Write Precompensatlon Magnitude
WP1
WPO
MAGNITUDE (WP)
0
0
3
0
1
2
1
0
1
1
1
0
TPC = WP x TPCO
The nominal magnitude,TPCO is extemally set
with a resistor on pin WCS.
TABLE 6: Window Shift Direction
WSD
DIRECTION
0
Early window (+TS)
1
Late window (-TS)
4-7
SSI32D5396/5396A
Data Sync/1, 7 RLL i5NDEC
with Write Precomp. and Window Shift
TABLE 7: Window Shift Magnitude
W1
W2
WO
MAGNITUDE (TSO)
1
1
1
No shift
1
1
.0
4% Minimum shift
1
0
1
8%
1
0
0
12%
0
1
0
1
0
0
1
~5%
0
18%
0
1
20%
0
0
22% Maximum shift
:
With resistor, RRS, connected between pins RS and VPA:
TS = T80 [RRS/(RRS
+ 0:8)]
2kO< RRS
.
PIN DESCRIPTION
INPUT PINS
NAME
TYPE
DESCRIPTION
VPA1, VPA2
I
5 volt analog power supply pins
VPD
I
5 voH digital power supply pin .
-
Analog ground pin
DGND
AMENB
I
ADDRESS MARK ENABLE. Used to enable the address mark detection and
address mark generation circuitry. Active 10wTTl input levels.
OW
I
DIRECT WRITEENABLE.l.lsed to enable the direct write mode. A high level
allows' normal write operation. A low level enables the encoder bypass path
mode. In this bypass mode, NRZO will directly clock the WD Flip-Flop while
WG = 0; Pin OW has ,an internal pull up resistor. TTL input levels.
EPD
I
ENABLE PHASE DETECTOR. A low level (coast mode) disables the phase
detectorand enables the Test Mode. This opens the PlL and the VCO will run
at the frequency commanded by thevoHage on the VCO IN pin. (In the Test
Mode, functions normally driven by the VCO are SWitched to FREF.) Pin EPD
has an internal pull-up resistor. TTL input levels.
FREF/FREF
I
REFERENCE FREQUENCy INPUT. The mputfrequency is at one and onehalf times the data rate. FREF/FREF should be driven by direct coupled
differential PECl.signals.
RD,RD
I
READ DATA. Encoded Read Data frolT}.the disk drive read channel. Differentia!+5 voHs offset ECl (PEeL) inpLJI leltels.
AGND
.'
Digital ground pin
4-8
SSI 32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
INPUT PINS (continued)
NAME
TYPE
DESCRIPTION
RG
I
READ GATE. Selects the PLL reference input and initiates the PLL synchronization sequence. A high level selects the RD input and enables the read
mode/address detect sequences. A low level selects the XTAL input. See
Table 2. TTL input levels.
WO, W1, W2
I
WINDOW CONTROL BITS. In Read Mode, pins WO and W1 and W2 control
the magnitude of the decode window shift. Each pin has an internal pull-up
resistor. TTL input levels.
WCLK
I
WRITE CLOCI<. Write mode dual-bit clock. Must be synchronous with the
NRZ input. For short cable delays, WCLK may be connected directly to pin
RCLK. For long cable delays, WCLK should be connected to an RCLK return
line matched to the NRZ data bus line delay. TTL input levels.
WPO,WP1
I
WRITE PRECOMPENSATION CONTROL BITS. In Write Mode, pins WPO
and WP1 control the magnitude of the write precompensation. Each pin has
an internal pull-up resistor. TTL input levels.
WG
I
WRITE GATE. Enables the write mode. See Table 2. Active low TTL input
levels.
WSD
I
WINDOW SYMMETRY DIRECTION CONTROL. Controls the direction ofthe
decode window shift. Pin WSD has an internal pull-up resistor. TTL input
levels.
AMD
0
ADDRESS MARK DETECT. Tristate output pin that is in its high impedance
state when WG is low or AMENB is high. When AMENB is low, this output
indicates address mark search status. A latched low level output appears
when an address mark has been detected. A high level on pin AMENB resets
pin AMD. TTL output levels.
DRD
a
DELAYED READ DATA. An open emitter ECL output test point. The positive
edges of this signal indicate the data bit position. The positive edges of the
DRD and VCO_REF outputs can be used to estimate window centering. The
time jitter of DRD's positive edge is an indication of media bit jitter. Two
external resistors are required to use this pin. They should be removed during
normal operation to reduce power dissipation.
FOEN
0
REFERENCE CLOCK ENABLE. When this output is high, the FREF clock is
controlling the intemal timing. When this output is low, the FREF clock is
internally disabled. The outputfrom pin FOEN can be used to disable the clock
applied to the FREF pin to reduce VCO jitter during read modes. TTL output
levels.
RCLK
0
READ CLOCK. A multiplexed dual-bit clock source used by the controller, see
Table 2. During a mode change, no glitches are generated and no more than
one lost clock pulse will occur. When RG goes high, RCLK initially remains
synchronized to FREF/3. After 19 read data pulses, RCLK is synchronized to
the Read Data. When RG goes low, RCLK is synchronized back to the
FREF/3. TTL output levels.
OUTPUT PINS
4-9
II
SSl32D5396/5396A
DataSync/1,7 RLL ENDEC
with Write Precomp. and Window Shift
PIN DESCRIPTION
(continued)
OUTPUT PINS (continued)
NAME
TYPE
DESCRIPTION
SD
0
SYNCHRONIZED DATA. An open emitter PECl output test point. Synchronized data before the decoder. Two external resistors are required to use this
pin. They should be removed during normal operation to reduce power
dissipation.
VCO REF
0
VCO REFERENCE. An open emitter PECl output test point. This is the VCO
reference input to the phase detector. The positive edges are phase locked to
Delayed Read Data. The negativeedgesof this open emitter output signal
indicate the edges of the decode window. Two external resistors are required
to use this pin. 'They shoUld be removed during normal operation to reduce
power dissipation.
WD,WD
0
WRITE DATA. Encoded write data output. The data is automatically
resynchronized (independent of the delay between RRC and WClK) to the
FREF reference clock. Differentia:l PECl output levels. Termination resistors
are-required.
BIDIRECTIONAL PINS
NRZO,
NRZ1
NRZ READ DATA PORT. Dual-bit port. Read data output when RG is high,
Write data input when WG is low. TTL input and output levels.
ANALOG PINS
IREF
- PDOUT
I
CURRENT REFERENCE INPUT. The VCO center frequency, the 1/3 cell
delay, and the phase detector gain are a function of the current sourced into
this pin,
-,
0
PHASE DETECTOR OUTPUT. Drives the loop filter input.
RS
I
WINDOW SYMMETRY ADJUST PIN. This pin allows analog adjustment of
the decode window shift magnitude. Used in conjunction with the digital
controls W) andW!'and W@ this pin can be used to scale the magnitude of
the preset window shift. Connect resistor to VPA.
VCOIN
I
VCO CONTROL INPUT. oriven by the loop filter output.
WCS
I
WRITE PRECOMPENSATION SET. Pin for the reference current to set the
write precompensation magnitude value. Connect resistor to VPA.
4-10
SSI 32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER
Supply Voltage, VPA1, VPA2, VPD
RATING
-0.3 to 6V
Storage Temperature
-65 to 150. o C
Lead Temperature (Soldering 10 sec.)
FOEN,NRl, WD, WD, AMD, DRD,
260°C
VCOREF pins
All other pins
-0.3 to (VPAlVPD+0.3)V or +12 mA
-0.3 to (VPAlVPD+0.3)V
RECOMMENDED OPERATING CONDITIONS
Supply Voltage, VPA1 = VPA2 = VPD = VCC
Junction Temperature, Tj
0< Tj < 135°C
Ambient Temperature, Ta
0< Ta < 70°C
4.75 < VCC < 5.25V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, 4.75 < VPAlVPD < 5.25, O°C < T(ambient) < 70°C, 25 °C < T(junction) < 135°C.
Currents flowing into the chip are positive. Current maximums are currents with the highest absolute value.
POWER SUPPLY CURRENTS AND POWER
PARAMETER
CONDITIONS
ICC (VPA, VPD)
Supply Current
Outputs and test point pins
open, Ta = 70°C
180
mA
PWR
Power Dissipation
Outputs and test point pins
open, Ta = 70°C
0.9
W
MIN
NOM
MAX
UNIT
DIGITAL INPUTS AND OUTPUTS
TTL Compatible Inputs: AMENB, EPD, DW, RG, WO, W1, W2, WCLK, WG, WPO, WP1, NRlO, NRl1,
WSD Pins
Input Low Voltage (VIL)
-0.3
0.8
V
Input High Voltage (VIH)
2.0
VPD+O.3
V
0.0
-0.4
mA
100
J.IA
Input Low Current
VIL = 0.4 V
Input High Current
VIH = 2.4 V
4-11
I
SSt 32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
DIGITAL INPUTS AND OUTPUTS
(continued)
TTL Compatible Outputs: AMD, FOEN, NRZO, NRZ1, RCLK pins
PARAMETER
MIN
CONDITIONS
Output Low Voltage
101 =4.0 mA
Output High Voltage
loh= -4001lA
NOM
MAX
O.S
2.4
UNIT
V
V
Digital Differential Inputs: RD, RD, FREF, FREF pins
Input Low Voltage (VIL)
VPA-2.~
VIH-O.S
V
Input High Voltage (VIH)
VIL+0.5
VPA-O.S
V
Differential Voltage
IVRD - VRDI
O.S
Input Low Current
VIL = Min
-100
Input High Current
VIH= Max
V
+100
IlA
IlA
Digital Differential Outputs: WD, WD pins
Output Low Voltage
101 = TBD
Output High Voltage
loh = TBD
f-- Differential Voltage
VPD-2.1
V
VPD-0.7
O.S
IVWD - VWDI
V
V
Test Point Output Levels
Test Point Output
High Level (DRD, VCOREF)
26212 to VPA,
40212 to GND, VPA = SV
Test Point Output
Low Level (DRD,VCOREF)
26212 to VPA,
40212 to GND, VPA = 5V
4-12
VPA
-1.02
V
VPA
-1.625
V
SSI 32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
DYNAMIC CHARACTERISTICS AND TIMING
READ MODE (See Figure 5)
PARAMETER
CONDITIONS
MIN
Read Data Pulse Width (TPRD)
NOM
8
MAX
UNIT
(2)TVCO
-8
ns
5
ns
Read Data Rise Time (TARD)
20% to 80%, CL ~ 10 pF
Read Data Fall Time (TFRD)
80% to 20%, CL ~ 10 pF
5
ns
Read Clock Rise Time (TRRC)
0.8V to 2.0V, CL ~ 15 pF
5
ns
Read Clock Fall Time (TFRC)
2.0V to 0.8V, CL ~ 15 pF
5
ns
NRZ (out) Set Up &
Hold Time (TDS, TDH)
10
ns
RCLK Low Time (TLRC)
0.8V, CL ~ 15 pF
13
ns
RCLK High Time (THRC)
2.0V, CL ~ 15 pF
15
ns
13
ns
AMD Set Up &
Hold Time (TAS, TAH)
RRC re-sync period (Tdc2)
TORC
Decode Window Centering
Accuracy
Decode Window
(2)TORC
ns
±0.75
ns
TVCO-O.75
ns
WRITE MODE (See Figure 6)
Write Data Rise Time (TRWD)
Write Data Fall Time (TFWD)
Write Data Clock Rise Time
(TRWC) CL~ 15 pF
Write Data Clock Fall Time
(TFWC) CL ~ 15 pF
NRZ Set Up TimeJTSNRZ)
NRZ Hold Time (THNRZ)
Precompensation Time Shift
Magnitude Accuracy (TPC)
20% to 80% Points
110QtoVPD,160QtoDGND
80% to 20% Points
110QtoVPD,160QtoDGND
0.8V to 2.0V,
2.0V to 0.8V,
5
ns
5
ns
10
ns
8
ns
ns
ns
5
5
TPCO = 0.22(Rc + 0.53)
Rc min=1 kil, TPC max=O.3TFREF
-0.5
WO = 1, W1 =1
WO = 0, W1 =1
WO = 1, W1 =0
WO = 0, W1.=0
4-13
TPCO
ns
ns
2TPCO
3TPCO
ns
ns
0.5
II
SSI 32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
DATA SYNCHRONIZATION
PARAMETER
CONDITIONS
VCO Center Frequency
Period (TVCO)
VCO IN=2.7V, VPA=VPD=5V
TO=3.6 (RR+1.7),
RR=(185/DR)-1.7K
MAX
UNIT
0.8TO
1.2TO
ns
1.0 V:o;; VCO IN
VPA - 0.6V
VPA=VPD = 5 V
± 25
±45
%
VCO Control Gain (KVCO)
wo = 27tlTVCO
1.0 V:o;;VCO IN
:0;; VPA - 0.6V
0.14 wo
0.26 wo
rad/s V
Phase Detector Gain (KD)
VPA= VPD = 5V
Read: KD = 660/(RR+0.53)
PLL REF = RD, 1T Pattern
Non-Read: KD = 330/(RR+0.53)
0.83KD
1.17KD
IJAIrad
0
±28
%
VCO Frequency
Dynamic Range
MIN
NOM
:0;;
.-
KVCO x KD Product Accuracy
VCO Phase Restart Error
Referred to RRC
1/3 Cell Delay
TD=1.8 (RR + 1.7); RR = k.Q
Phase Detect Centering
0
±1
rad
0.8TD
1.2TD
ns
0
±5
%
(± TV;O)
MODE CONTROL
WG
RG
AMENB
MODES
DESCRIPTION
1
0
1
Idle
Idle mode. VCO locked to external FREF reference.
RCLK synchronized to FREF. AMDtri-state.
1
0
0
AM Search
Read mode Address Mark search. VCO locked to external FREF reference. RCLKsynchronized to FREF. AMD
active.
1
1
1
Read Data
Read mode preamble search and data acquisition. VCO
switched from FREF to RD after preamble lock. RCLK
synchronized to RD after 19 "3T" patterns.
1
1
0
Undefined
Illegal state.
0
0
0
Write AM
Write mode Address Mark insertion. VCO locked to
external FREF reference. WD, WD active. AMDtricstate.
0
0
1
Write Data
Write mode preamble insertion and data write. VCO
locked to external FREF reference. RCLK synchronized
to FREF. WD, WD active. AMD tri-state.
0
1
1
Undefined
Illegal state.
1
0
Undefined
Illegal state.
-~
0
4-14
SSI 32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
RD--~
RCLK
1.5 V
NRZO, NAZI - - - j - - - - - - . - - /
TDS
II
FIGURE 5: Read Timing
14----TOWC---~
WDNAZ - - - - - - - - - - /
~--------,~5~
FIGURE 6: Write Timing
4-15
TFWe
:eotJ)
-, I» tJ).
........
::r 1». (,.)
:tEtJ)N
.., '< 0
::;:::SCJ1
(I)(')~
"
lJ :.:
u u
,v
u
"V
=:i:. CO
.
..,'tJ ...
~
~
"V
~
~~.'
·WG
(INTERNA4
-~
i, fe
1-
H
'..
I.
~
.,
I
1 NAl MIN
~V_
~
AMENB
J
MIN 38 NRZ IF JjQ
AMENB
..
_ _ _ _- - '
MIN OF(~O~~f~~~ENDED
MAX
•
~ '~_~~z~L____________________________________________~----------------------------______
__________
MAX OF 3; X aT (1,7) DELAV TOSVNC AMENB
TO INTERNAL STATE
MAX OF 5 NRl DELAV
5 NRZ PAD TO
FLUSH ENCODER
WDNRZ
'!"
:c
::;:
::::r
:e
I'lOO
';0
""I
::;:
~
,..
ADDRESS MARK
~I"
PREAMBLE
~ ENCODED DATA
('0, 3T PATTERN)
1 '
C'D
4Jc
m
.VCOIN
C'D
(')-
o m
WONRZ
VCO
SOURCE
ARC
SOURCE
ARC
3CJ)
~
"C '< CJ)
VCO LOCKS BUT VCO LOCK SIGNAL WILL STAY INACTIVE
m~~
I]
CJ)
::s .....
c",
Q.'"N
:e_. .II. . enC
V~~ X':L
XXX,,~
• ::s
mQ_
::Srw
X
Q.rco
°m~
:CZen
~ MAX 2 TIME PERIODS
CJ)c~
OF ARC
::::rmc:n
FIGURE 10: Write Data
•
=0>
SSI 32D5396/5396A
Data Sync/1, 7 RLL ENDEC
with Write Precomp. and Window Shift
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
~
~
6
5
S~
0
> a:
4
3
2
N/C
WCLK
0
Z
z
~ ~ zI? I?
1
•
0
0-
u..
~
44 43 42 41
40
N/C
39
SD
38
!Wi
37
VCO REF
IlW
10
36
PDOUT
11
35
VCOIN
AliArn
EPD
WG
IREF
RG
SD
15'Rl)
WCLK
r5W
VCOREF
WD
WI)
VCOIN
W5
12
34
VPA1
NRZO
13
33
WP1
NRZ1
14
32
WJ50
N/C
15
31
RS
DGND
16
30
WSD
RCLK
VPD
17
29
N/C
FOEN
AM!)
~
:.:
z
..J
()
W
0
a: u..
i
a:
(/J
~
PDOUT
NRZO
VPAl
NRZl
WPl
DGND
WPO
VPD
22 23 24 25 26 27 28
~ s:tb
AGND
VPA2
WD
18 19 20 21
Fill
RD
W
w
~ I~ ~ ~
44·Pin PLCC
RS
WSD
wo
FREF
Wi
W2
rnEF'
WCS
36-Pin SOM
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
Protected by the following patent: (4,803,445)
©1992 Silicon Systems, Inc.
4-20
1093
5513204666
Time Base Generator
I; t§ '" ,ii is' fJ .tiM
September 1993
DESCRIPTION
FEATURES
Programmable frequency output up to
The SSI3204666 is a high performance bipolar device
that provides a programmable frequency reference
and four internal control OACs to support hard disk
drive applications that use zoned recording
techniques. It is optimized for use with the 32P3000
family of pulse detectorlfilter devices and the 32053X
family of data separators. The frequency reference can
be programmed up to 108 MHz with better than 1%
resolution. The 7-bit OACs provide control of the 3 dB
cutoff frequency and pulse slimming of the electronic
filter, the hysteresis level of the pulse qualifier, and the
center frequency of the data separator. A single
latched TTL output is also provided to control switching
of .external loop filter components on the data
separator. A serial microprocessor interface reduces
the pin count and provides convenient access to the
internal program storage registers. The 3204666
requires a +5 VOC supply and is available in a 24-lead
SO and VSOP package.
108 MHz
1% frequency resolution
Differential PECl reference clock Input (FREF)
Differential PECl frequency reference output
(FOUT)
7-bit DAC for data separator center frequency
control (DACI)
7-bit DAC for filter Fc control (DACF)
7-bit DAC for filter boost/equalization control
(DACS)
7-bit DAC for hysteresis level control (DACP)
+5 VDC operation
Available in small footprint 24-lead SOL and
VSOP packages
BLOCK DIAGRAM
FREF
FREF
FCO~_.
0993 - rev.
4-21
I
991 32D4666
Tlme~Base Generator
FU'NCTIONALbESCRIPTION
SERIAL PORT OPERATION
FREQUENCY REFERENCE OPERATION
The 3204666 provides a simple serial port interface
that allows programming of the device's internal
registers. The write-only serial port is a three-line
interface that requires an enable signal (SOEN) along
with clock (SClK) and data (SOATA) Signals to program
the internal registers of the 3204666. Data is shifted
into. the registers in 8·bit bytes thiit are ,divided into four
bits of address and four bits of data. To load data into
the device, the enable pin (SO EN) is asserted for eight
clock cycles during which data can be presented on the
SOATA input pin. Data on the SOATA pin is clocked
into the device on the falling edges of the clock signal
provided on the SClK pin. The falling edge of SDEN
latches the data. internally and initiates. the function
selected. To save power the serial poi'tcircuitry is
powered down wilen the SDEN line is low. Because of
this, there isa minimum set-up and hold time for the
SOENsignal (referto specificatlons.) Taole 1 provides
the addresscto-function mapping for the internal
registers.
The 3204666 programmable frequency reference
accepts a differential PEel compatible clock source
and generates a differential PECl compatible reference
output (FOUT/FOUl). The output frequency of FOUT
is controlled by programming internal M and N counters
to set up internal divide-by ratios, The 7-bit N register
sets the divide-byfactorforthe input clock source. This
will determine the update frequency for the phase
detector. The value of this register is set based upon
the frequency of the input clock according tb the
following equation:
N = [(FIN )(256jl1 08] '- 1
where FIN is in MHz
The 8-bit M register sets the divide-by term forthe VCO
reference clock feeding back into the phase detector
and determines the centerfrequency of the VCO. The
value set in the M register is independent of the input
clock frequency, The value of the M register is
determined by the following equation:
FOUT = [(M+ 1)/(N+ 1)] x FIN
DAC OPERATION
The output of each of the four 7·bit DACs is control.led
by programming the associated register. In addition,
each OAC has a reference input that determines the.
maximum OAC output. The following equations are
used to calculate the OAC outputs:
IOACF = IR x FREGx 4/127 rnA
IOAcl = (7.41 E ·2 x IREG)/RR rnA, where RRjs in.kn
VOACP =[2 x PREG x (VRP - (VCA - VR3))]/127V
VOACS= (SREG x VR3)/127V
4-22
SSI3204666
Time Base Generator
TABLE 1: Data Packet Fields (X = Don't care bit)
ADDRESS BITS
REGISTER
DATA BITS
07
06
05
04
0
0
1
1
0
0
0
1
P Register
P Register
P3
0
0
1
1
1
1
0
1
I Register
I Register
13
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
1
1
0
0
0
1
1
1
1
1
1
0
1
S Register
S Register
F,e Register
F Register
M Register
M Register
N Register
N Register
1
1
1
Clocks data bit
1
I
I...
1
TC
03
02
01
DO
X
P6
P2
16
12
S6
S2
F6
F2
M6
M2
N6
N2
P5
Pi
15
11
S5
S1
F5
F1
M5
M1
N5
N1
P4
PO
14
X
X
S3
eo
F3
M7
M3
X
N3
10
S4
SO
F4
FO
M4
MO
N4
NO
I
.'1
SCLK
1 1
1
SDEN
J
~
SDEN Setup wrt SCLK falls
1
·
.
Loads dala Into
register
SDATA Hold wrt SCLK falls
SDATASetup
wrt SCLK falls
SDEN Hold wrt SCLK falls ~ 11- SDEN falls
1 1 1
before next
SCLK rise
1
f------1~
1
.
".
'I:
.
SDATA
FIGURE 1: Serial Port Timing Relationship
4-23
;1'------
I
SSI3204666
Time Base Generator
PIN DESCRIPTION
INPUT PINS
NAME
TYPE
DESCRIPTION
AGND
I
Analog ground pin.
DGND
I
Digital ground pin.
VCA,£
I
+5V analog power supply pins.
VCD
I
+5V digital power supply pin.
FOEN
I
This is a TIL compatible input that disables the output buffer of the FOUT pin
with a TIL low signal. This function is used to reduce jitter when the reference
output is not required.
FREF/FREF
I
Referenoe olock inputs. An 8 to 20 MHz differential PECl reference olock is
applied to these input pins. This serves as the reference for the internal PlL.
IR
I
Reference Current Input. The current applied to this pin provides the reference
for DACF.
SDATA
I
Serial port input data. Data input for an 8"bit internal shift register. The data
packet is transmitted MSB (07) first. The first four bits are the register address
and the last four bits are the data value. For loading data into both registers of
a DAC orthe M and N counters, it is suggested that the registers be loaded with
a minimum delay between paokets to reduce the output transients.
SClK
I
Serial Data Clock. Serial data is olooked into the internal shift register on the
falling edge of this input.
SDEN
I
Serial Data Enable. A high level TIL input on this pin will enable the olooking
of the internal shift register. The data in the shift register is latohed on the falling
edge of SDEN.
VR3
I
Reference Input Voltage. The voltage applied to this pin establishes the
referenoe for DACS.
VRP
I
Reference Input Voltage. The voltage applied to this pin establishes the
reference for DACP.
-
4-24
SSI3204666
Time Base Generator
OUTPUT PINS
NAME
TYPE
DESCRIPTION
DACF
0
Current DAC output. The output of this 7-bit current DAC is determined by the
contents of the F register and the current applied to the IR pin.
DACI
0
Current DAC output. The output of this 7-bit current DAC is determined by the
contents of the I register and the resistor across the VR1IVR2 pins.
DACP
0
Voltage DAC output. The output of this 7-bit voltage DAC is determined by the
contents of the P register.
DACS
0
Voltage DAC output. The output of this 7-bit voltage DAC is determined by the
contents of the S register.
FCO
0
Filter Control Output. This is a latched TTL output that can be used to switch
an external FET for changing the components of the data separator loop filter.
When CO is set to TTL high ("1") in the F register, the FCO output will be high.
FOUT/FOUT
0
Frequency Output. A differential PECl frequency reference output that is
determined by the M and N registers .and the FREF/FREF input frequency.
This output should be AC coupled into the reference input of the data separator
device.
-
Pll loop filter. An RC filter is connected to this pin to controlthe VCO voltage .
ANALOG PINS
. FlTR
VR1IVR2
Current setting resistor. A resistor is connected between these pins to set the
current reference for DACI.
4-25
II
SSI32D4666
Time Base Generator
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, the recommended operating conditions are as follows: 4.65V < POSITIVE
$UPPLYVOLTAGE < 5.25V, O°C < T (ambient). < 70°C, and 25°C < T(junction) < 135°C. Currents flowing
into the chip are positive. Current maximums are currents with the highest absolute value.
ABSOLUTE MAXIMUM RATINGS
Operation beyond the maximum ratings may damage the device.
PARAMETER
RATING
Storage Temperature
-65 to 150°C
Junction Operating Temperature, Tj
+150°C
Positive Supply Voltage (VCA, VCB, VCD)
-0.5Vto 7V
Voltage Applied to Logic Inputs
-0.5V to Vp+0.5V
RECOMMENDED OPERATING CONDITIONS
Positive Supply Voltage (VCA, VCB, VCD)
4.65V to 5.25V
Junction Operating Temperature, Tj
0:::; Tj:::; 130°C
Ambient Temperature, Ta
o:::;Ta:::; 70°C
POWER SUPPLY CURRENT AND POWER DISSIPATION
J:'ARAMETER
CONDITIONS
NOM
MAX
UNIT
ICC (VCA, B, D)
Outputs and test point pins open
77
110
mA
Pd Power Dissipation
Outputs and test point pins open
385
540
mW
0.8
V
-1.5
mA
MIN
TTL COMPATIBLE INPUTS
Input low voltage
Vil
Input high voltage
VIH
2.0
V
Input low current
ilL
VIL=0.4V
Input high current
IIH
VIH = 2.7V
20
J,iA
0.5
V
TTL COMPATIBLE OUTPUTS
Output low voltage
VOL
IOL = 2.0 mA
Output high voltage
VOH
IOH = -400 J,iA
2.4
V
VCA-1.02
V
PECl OUTPUT lEVELS (FOUT/FOUn
Output high level
VCA=5.0V
Output low level
VCA= 5.0 V
Single-ended output voltage swing
VCA= 5.0 V
Output current
IFOUT
4-26
VCA-1.45
V
0.75
0.95
V
-4.0
+4.0
mA
SSI3204666
Time Base Generator
PECl INPUT lEVELS (FREF/FREF)
PARAMETER
Input high level
CONDITIONS
VFIH
Input high current
IFIH
Input low level
VFIL
Input low current
MIN
MAX
UNIT
VFll-0.5
VCA-0.5
V
100
~
VCA = 5.0 V
VCA-2.2
VFIH-0.5
V
IFIL
Differential input
NOM
VCA = 5.0 V
VCA = 5.0 V
-100
~
0.5
V
FREQUENCY REFERENCE OUTPUT
Unless otherwise specified, FOUT = 30 MHz; loop filter components are C1 = 3300 pF, C2 = 270 pF,
R1 = 4.12 kQ; 4.65V -< VCn -< 5.25V· 0 -< Ta -< 70°C
Reference frequency
Output frequency
FIN
8
FOUT
--
Output jitter
JFO
Output duty cycle
DFO
20
MHz
108
MHz
0.5%
ps(RMS)
x TVCO
50% amplitude, FOUT = 108 MHz
42
58
M counter value
80
255
N counter value
18
127
RR resistor value
veo center frequency
TVCO
VCO dynamic range
VCO control gain
Phase detector gain
TVCO = (4.01 E-10) (RR/M)
+ 2.4 nsec; VCA = 5.0V,
RR = 4.75 kQ, FLTR = 2.7V,
M = 100, FIN = 20 MHz
lV600n, and
each side is loaded with < 10 pF to AGND, and AC coupled to DIN±. A 2000 pF capacitor is connected between
BYP and AGND. AGC pin is open.
Gain Range
.Output Offset Voltage
1.0 Vpp ::;; OUH ::;; 3.0 Vpp
4
Over entire gain range
-200
Maximum Output
Set by BYP pin
3.0
Voltage Swing
THD::;;5%
Differential Input Resistance
IN± = 100 mVpp
@2.5MHz
Differential Input Capacitance
IN± = 100 mVpp
@.2.5Ml1z
""
80
0
+200
VN
mV
Vpp
;
kn
5.0
10
pF
-,-
Common Mode Input
RJW= high
1.5
kn
Impedance
RlW= low
250
n
Input Noise Voltage
Gain set to maximum
Bandwidth
-3 dB bandwidth at
maximum gain
OUT+ & OUT- Pin Current
No DC path to AGND
CMRR (Input Referred)
IN± = 0 VDC + 100 mVpp
@ 2.5 MHz, gain set to max
PSRR (Input Referred)
100 mVpp@ 2.5 MHz
on VCC, gain set to max
4-40
5.5
15
nV/$z
MHz
32
3
mA
40
63
dB
30
66
dB
I
SSI32P541C
Pulse Detector
AGC AMPLIFIER (Continued)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
DIN± Input
Swing vs. AGC Input
25 mVpp~ IN±
250 mVpp, HOLD = high,
0.5 Vpp ~ DIN± ~ 1.5 Vpp
0.38
0.45
0.56
Vpp/V
~
6.0
%
D1N± Input Voltage
Swing Variation
25 mVpp ~ IN± ~ 250 mVpp
AGC Voltage
AGC open
AGC Pin Input Impedance
= OV
Slow AGC Discharge Current
(DIN+) - (DIN-)
Fast AGC Discharge Current
Starts at 0.9 IlS after RIW
goes high, stops at 1.8 jJ.S
after R/W goes high
AGC Leakage Current
HOLD
Slow AGC Charge Current
(DIN+) - (DIN-) = 0.8 VDC,
vary AGC until slow charge
begins
Fast AGC Charge Current
(DIN+) - (DIN-)
VAGC = 3.0V
Fast to Slow Attack
Switchover Point
Gain Decay Time (Td)
= low
= 0.8 VDC,
1.8
2.2
2.6
V
3.5
3.9
5.5
kO
3.5
4.3
6
70
102
150
JlA
JlA
-0.2
0
+0.2
JlA
-0.12
-0.17
-0.24
mA
-0.9
-1.2
-1.7
mA
[( DIN + ) - ( DIN - )]
125
%
IN± = 250 mVpp to
125 mVpp @ 2.5 MHz,
to 90% final value
20
Ils
IN± =50 mVpp to
25 mVpp at 2.5 MHz
to 90% final value
70
IlS
R/W = low to high
IN± = 250 mVpp
@ 2.5 MHz,
to 110% final value
2
IlS
[( DIN+)- (DIN- )]FINAL
oun
oun
Gain Attack Time
oun
WRITE MODE (R/W is low)
PARAMETER
CONDITION
MIN
NOM
250
Common Mode Input
Impedance
4-41
MAX
UNIT
0
II
SSI32P541C
Pulse Detector
ELECTRICAL SPECIFICATIONS (continued)
HYSTERESIS COMPARATOR
Unlessotherwise specified, recommended operating conditions apply. Input (DIN+) - (DIN-) is an AC coupled,
1.0 Vpp, 2.5 MHz sine wave. 0.5 VDC is applied to the HYS pin. RIW pin is high.
PARAMETER
CONDITIONS
MIN
NOM
0.6
=100 mVpp@ 2.5 MHz
DIN± = 100 mVpp@ 2.5 MHz
17.5
3
4.8
Input Signal Range
Differential Input Resistance
Differential Input Capacitance
DIN±
Common Mode.lnput
Impedance (Both Sides)
Level Pin Output Voltage
vs. DIN±
0.6 Vpp < DIN±
< 1.5 Vpp, 10 kQ betwe.en
LEVEL pin and AGND
Level Pin Output Offset Voltage
10 kQ betw.een LEVEL pin
and AGND
Level Pin Output Impedance
ILEVEL
UNIT
1.0
1.5
Vpp
20
22.5
kO
5.0
pF
5.5
kQ
1
120
= 0.2 mA
Level pin Maximum
Output Current
MAX
170
VNpp
250
mV
0
330
2.0
mA
Hysteresis Voltage at DIN±
vs. HYS Pin Voltage
0.3 V < HYS < 1:0V
HYS Pin Input Current
0.5 V < HYS < 1.5V
Comparator Offset Voltage
HYS pin at AGND
:51.5 kQ across DIN±
DOUT Pin Output Low Voltage
5 kQ from DOUT to GND
VPA -2.8
V
DOUT Pin Output High Voltage
5 kQ from DOUT to GND
VPA -2.4
V
4-42
0.19
-10.0
VN
0
~
5.0
mV
SSI32P541C
Pulse Detector
ACTIVE DIFFERENTIATOR
Unless otherwise specified, recommended operating conditions apply. Input CIN± is an AC-coupled, 1.0 Vpp,
2.5 MHz sine wave. 1000 in series with 65 pF are lied from DIF+ to DIF-.
PARAMETER
MAX
UNIT
1.0
1.5
Vpp
20
22.5
kO
5.0
pF
4.5
5.5
kQ
CONDITIONS
MIN
NOM
0.6
CIN±
17.5
Differential Input Capacitance
= 100 mVpp@ 2.5 MHz
CIN± = 100 mVpp @ 2.5 MHz
Common Mode Input Impedance
Both sides
3.5
Voltage Gain From
CIN± to DIF±
Resistor across DIF± is 2 kO
DIF+ to DIF- Pin Current
Differentiator impedance must
be set so as to not clip the
the signal for this current level
COUT Pin Output Low Voltage
5 kO from COUT to GND
VPA -2.8
COUT Pin Output High Voltage
5 kO from COUT to GND
VPA-2.4
V
47
ns
Input Signal Range
Differential Input Resistance
1
-0.7
0.7
COUT Pin Output Pulse Width
P.!N--~I
.9115
Lown
1 - - 1_
_
_
_
_
V
-----r-~__,
I .9115
__
1.9;;;l>-____
Fast Discharge Swftch
, - I_ _ _ _ _ _ _
!.9;lf---,---
1
1
1
-------:-1______ I (DIN+ - DIN-)
rnA
pm---~
1
Lown----r----.,
Fast Discharge Swftch
VN
I
------r':
1
1-------1
Fast
Charge
-25%
Ff
1
I
!
I
,.
------1-1-----1
1
1
----~I~~I_~__-
I
Slow
Charge
Fl\lure A: AGC Attack Sequence
FIGURE 7: AGC Timing Diagram
1 Fast
Discharge
!Slow
,
Discharge
Figure B: AGC Decay Sequence
II
SSI32P541C
Pulse Detector
ELECTRICAL SPECIFICATIONS
(continued)
QUALIFIER TIMING
Unless otherwise specified, recornrnended operating conditions applY. Inputs CIN;:!: and DIN;:!: are in-place as
a coupled, 1.0 Vpp, 2.5 MHz sine wave. 1OOQ in series with 65 pF are tied from DIF+ to DIF-. 0.5V is applied
to the HYS pin. COUT and DOUT each have a 5 kQ pull-down resistor (fortest purposes only.) RIW pin is high.
PARAMETER
CONDITIONS
Td1
D Flip-Flop Set Up
Time
Minimum allowable time
delay from (DIN+) - (DIN-)
exceeding hysterisis
point to (DIF+) - (DIF-)
hitting a peak value.
Td3
Propagation Delay
From positive peak toRD
output pulse
28
From negative peak to RD
output pulse
28
ns
1.0
ns
Td4
Propagation Delay
ITd3-Td41
Td5
MIN
+HYSTERESIS LEVEL
RD pin open
ns
-
8
I-+----'Ir--------~-_>,_-
H------\---f---------
DIFFERENTIATOR
COMPARATOR OUTPUT
VCCUT
RD OUTPUT
FIGURE 8: Read Mode Digital Section Timing Diagram
4-44
UNIT
ns
V(CIN+) - (CIN-)
and
OV I+------'r----/---'r---I'-----__\__
V(DIN+) - (DIN-)
-HYSTERESIS LEVEL
MAX
0
Pulse Pairing
RD Output Pulse Width
NOM
14
ns
SSI32P541C
Pulse Detector
PACKAGE PIN DESIGNATIONS
(Top View)
Q ~
z ::z:
+
u.
4
2
3
0
Ii. z+
0
(3
z+ Z
0
(3
28 27
LEVEL
N/C
AGC
DINaUT-
IN+
IN-
OUT+
21
HOLD
AGND
N/C
10
BYP
COUT
11
DGND
12
13 14 15
I~
Q
Z
Q
Z
t,)
t,)
>
II
16 17 18
~ Q
z
l::J
a
0
28·Pin PLCC
THERMAL CHARACTERISTICS: 9ja
28-Pin PLCC
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
I
ORDER NO.
I
PKG.MARK
I
32P541C-CH
I
32P541C-CH
SSI32P541C
28-Pin PLCC
Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
ofthird parties resulting from its use. No license is granted under any patents, patent rightsortrademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1293 - rev.
4-45
©1992 Silicon Systems, Inc.
Notes:
4-46
SSI32P3013
Pulse Detector with
Programmable Filter
November 1993
DESCRIPTION
FEATURES
The SSI 32P3013 is a bipolar integrated circuit that
provides all the data processing for pulse detection and
four-burst servo capture from encoded read signals. This
device can handle a NRZ data rate of 64 Mbitls.
•
•
Compatible with 64 Mbitls data rate operation
•
Automatic AGC actions: Low Drift AGC hold, fast
AGC recovery, and low AGe input impedance
control signals
•
Includes programmable pulse slimming equalization and programmable channel filter and
differentiator with no external filter components
•
±0.5 ns fiHer group delay variation from 0.3 FC to
FC, FC = 27 MHz
•
Independent positive and negative threshold
qualification to suppress error propagation
•
•
•
•
0.5 ns max pulse pairing
The SSI32P3013 inCludes an AGC amplifier with AGC
charge pump, a programmable 7-pole Bessel low pass
fiHer, a pulse qualification circuit, and a 4-burst servo
capture circuit. Automatic AGC control maintains a
constant Signal level into the pulse qualifier, and
achieves fast write-to-read recovery. A time
differentiator is inCluded in the servo signal path, if so
needed.
Ideal for constant density recording applications, the
SSI32P3013low pass fiHer has a programmable 9-27
MHz bandwidth and 0-13 dB boost for pulse slimming.
A time derivative of the read signal is also provided by
the fiHer for time qualification in peak detection.
The SSI 32P3013 requires only a +5V power supply
and is available in a 44-lead SOM package.
Fast Attack/Decay modes for rapid AGC recovery
II
Servo differentiator and 4-burst servo capture
+5V only operation
44-lead SOM package
BLOCK DIAGRAM
Q
g
0(
Z a
Q
z
!! II !! 8
RO
1193 - rev.
SSI32P3013
Pu Ise Detector with
Programmable Filter
AGC Actions
FUNCTIONAL DESCRIPTION
The AGC loop maintains a constant DP/DN signal level
at a nominal level, -1 Vppd. The AGC actions are
current charging and discharging to/from the external
BYP integrating capacitor, and are classified into the
following modes:
The SSI 32P3013 Pulse Detector/Filter with 4-Burst
Servo Capture is designed to support a 64 Mbitls NRZ
data rate. The signal processing circuits include a wide
band variable gain amplifier, a sophisticated dual-rate
AGC charge pump, a programmable electronic filter, a
pulse qualifier, a servo differentiator and a 4-burst
servo capture circuit.
Normal Read and Servo Read Mode
(RG=X,WG=1)
Modes of Operation
Slow Decay: When the DP/DN signal is below 1 Vppd,
a slow decay current, Id, charges the BYP capacitor.
The AGC amplifier gain is increased slowly. This slow
decay current tracks with the bandwidth of the filter.
Id = 0.008x IF/. AtT = 27°C, thetypicalld is4.8!lA when
the filter cutoff frequency is 27 MHz.
The SSI32P3013 can operate in one of three modes
as controiled by RG and WG.
Normal Read Mode RG = 0, WG = 1
In the normal Read Mode, the AGC actions are
active. The AGC amplifier processes the input
signal pulses; one-shot pulses are generated
at the RD and RD outputs for each qualified
signal peak. The ROO output buffer, which is
a TTL buffer of the RD/R 0, is disabled and its
output is pulled up high to reduce jitter and
noise.
Slow Attack: When the DP/DN signal exceeds 1 Vppd,
but is below 1.25 Vppd, a slow attack current, Ich,
discharges the BYP capacitor. The AGC amplifier gain
is decreased. The slow attack current is 20 times that
of the slow decay current. Thus, for a given BYP
capacitor, the slow attack response time is quicker than
the slow decay response.
Servo Read Mode RG = 1, WG = 1
Fast Attack: When the DP/DN Signal exceeds 1.25
Vppd, the device enters a Fast Attack mode. A fast
attack current, Ichf, discharges the BYP capacitor. The
AGC amplifier gain is quickly lowered. The fast attack
current is seven times that of the slow attack current.
In the servo Read Mode, the AGC actions
remain active (See note 1). The servo signal is
amplified, fullwave rectified, differentiated and
gated to the proper peak capture capacitor.
The pulse qualifier remains active, and the
RDO output is active to aid in servo decode.
In servo Read Mode, constant AGC amplifier gain is
generally desirable. Without an external AGC hold
control, the servo data amplitude should be made
lower than that of the data signal priorto the servo read
mode. The SSI32P3013 then enters the slow decay
mode, which has a very slow effect on the AGC
amplifier gain.
Write Mode RG = X, WG = 0
In the Write Mode, the AGC actions are suspended. The AGC amplifier input impedance
is clamped low to facilitate fast recovery. The
ROO output is disabled and pulled up high to
reduce jitter and noise.
Write Mode (HG = X, WG = 0)
AGC Amplifier
In the Write mode, the AGC charge pump is disabled.
This holds the AGC amplifier gain at its previous value.
The wide band AGC amplifier amplifies the read signal
from the read/write pre-amp to a signal level acceptable atthe pulse qualifier. The AGC amplifier gain is an
exponential function of the BYP voltage when referenced to VR.
Notes:
1. The servo signal should have a lower amplitude than
the data signal prior to the servo Read mode. Servo
read should be completed before and significant
change in AGC amplifier gain is resulted from the slow
decay AGC mode.
Av=Ao exp[(VBVP - VR)j (See note 2)
K
2. In a closed AGC loop, the sensitivity of Ao and K to
typical process variations is irrelevant. The typical
values of Ao and K are provided for reference only, and
not tested in production. Ao = 11, K = 0.22, VR = 3.6.
4-48
SSI32P3013
Pu Ise Detector with
Programmable Filter
Write-ta-Read Transition
(RG X, WG o-to-1)
=
IFI should be made proportional to IFOfor fctemperature stability. The cutoff frequency is related to the RX
resistor, IFO and IFI currents as the following:
=
When the SSI 32P3013 switches from the write to
Read mode, i.e., WG 0-to-1 transition, the device
remains in the low input impedance state for a preset
time period, TLZ. For the next time period, TFD, the
device then enters either the fast decay or Attack mode
depending on the signal level at the DP/DN pins. The
time periods are determined by an external resistor,
RT, from the lZIFD pin to ground.
fC(MHZ)=27.~.~
IFO Rx(! 45 kQ
-40
+40
%
TFD
Fast Decay
Timing Accuracy
TFD (J..lS) = RT(kQ)/37-0.85,
RT> 45 kQ
-40
+40
%
9
27
MHz
EQUALIZER/FILTER
The input signals are AC coupled to IN+ and IN-.
fC
Filter Cutoff Frequency
RX= 5 kQ
fc = 27 x IFI/(4 x IFO ) MHz
4 ~ IFOIIFI ~ 4/3
IFO
IFO Reference Current
IFO = 0.75/RX; Tj = 27°C
5 kQ > RX > 1.25 kQ
0.15
0.6
mA
IFI
IFI Program Current
Range
Tj = 2rC, 27 MHz> fc >
9 MHz
0.2
0.6
mA
FCA
FCA Filter FC Accuracy
fc = 27 MHz
RX
RX Range
AO
Normal Low Pass Gain
AO = (ON ±) 1 (IN±)
AD
Differentiated Low Pass
Gain
AD = (00 ±) 1 (IN±)
FBA
Frequency Boost Accuracy
-13
13
%
1.25
5
kQ
Fin = 0.67fc
1.4
2.2
VN
Fin = 0.67fc
0.8AO
1.2AO
VN
VBP= VRG
-1.5
+1.5
dB
VBPIVRG = 0.5
-1.0
+1.0
dB
4-55
II
SSI32P3013
Pu Ise Detector with
Programmable Filter
EQUALIZER/FIL TER (continued)
The input signals are AC coupled to IN+ and IN-.
PARAMETER
TGD1
Group Delay Variation
TGD2
MIN
CONDITIONS
MAX
UNIT
0 to VRG
-0.7
+0.7
ns
fe = 9 to 27 MHz, VBP = 0 to VRG
-2.5
+2.5
%
-200
200
mV
Ie : 27 MHz, VBP :
Ie > Fin> 0.3 Ie
--
NOM
Ie> Fin> 0.3 Ie
J1A < IFI
J1A
VOSVF Output Offset Voltage
Variation
200
DRF
VOF Filter Output
Fin = 0.67 Ie
THO: 1.5% max, ON±
THD: 2.5% max, OD±
RINF
Filter Input Resistance
CINF
Filter Input Capacitance
Dynamic Range
ROF
Filter Output Resistance
10F
Filter Output Current
VNN
Eout Output Noise
Voltage; ON+, ON-
VND
Eout Output Noise
Voltage; 00+, OD-
< 600
1.2
3.0
Vpp
3.9
kQ
7
30
10+ = 1.0 mA
-1.0
pF
60
Q
1.0
mA
BW: 100 MHz, RS: 50Q
VBP: 0, Ie = 27 MHz
2.8
5.0
mVRms
BW: 100 MHz, RS: 50Q
VBP: VRG, Ie = 27 MHz
5.8
8.5
mVRms
BW: 100 MHz, RS = 50Q
VBP = 0, Ie = 27 MHz
5.2
7.5
mVRms
BW = 100 MHz, RS: 50Q
VBP : VRG, Ie : 27 MHz
15.0
21.0
mVRms
9.6
14
kQ
2
5
pF
4
mV
DATA COMPARATOR
The input signals are AC coupled to DP and ON.
RIND
Differential Input Resistance
CINO
Differential Input Capacitance
8
VOSD Comparator Offset
Voltage (Note 1)
HYS
VSH
Threshold Voltage Gain
VTH - VRC : 0.3V
0.40
0.52
VN
VTH - VRC = O.9V
0.42
0.49
VN
Threshold Voltage
Hysteresis (Note 1)
.20
x
VN
GHYS x
(VTH-VRC)
TPDD Propagation Delay
IVTH
To DO
ns
6
2
VTH Input Bias Current
Note 1: Not directly measure able
4-56
J1A
SSI32P3013
Pulse Detector with
Programmable Filter
CLOCKING
The input signals are AC coupled to CP and CN.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
4
mV
9.7
14
kO
1.4
5
pF
DP-DN threshold to CP-CN
zero cross, CP-CN = 1 Vppd
at 18 MHz
0.3
1
ns
0.1
0.5
ns
VOSC Comparator Offset
Voltage (Note 1)
RINC
Differential Input
Resistance
CINC
Differential Input
Capacitance
TDS
D Flip-Flop Set Up Time
PP
Pulse Pairing
Vs = 1 Vpp, F = 18 MHz
TPDC
Propagation Delay from
CP-CN zero crossing
to RD
Vs = 20 mVpp square wave
8
ns
8
PWRD RD Output Pulse Width
10
16
ns
PWRT RDO, TTL Output Pulse
Width
30
45
ns
SERVO DIFFERENTIATOR/FULL·WAVE RECTIFIER
An external series network with R = 6000, C = 27 pF, L = 22 J.lF is connected between SDIF and SDIF to
determine the servo differentiator transfer function. The input signals are AC coupled to DP and DN.
Fin = 6.7 MHz at 1.0 Vppd.
ISDIF
SDIF+ to SDIF- pin current
Differentiator impedance
must be set so as not to
dip the signal for this level
1.4
2.0
2.6
mA
RDIF
Internal differentiator
pull-up resistors
Cannot be directly tested
0.4
0.6
0.8
kO
FWR
Input voltage range to
maintain FWR voltage
gain
Cannot be directly tested
0.1
2.0
Vppd
-10
10
%
-20
20
%
1
J.lA
RERR Rectification Error
AFWR FWR Voltage Gain from
DP/DN Inputs to PKA-D
Outputs
0.1 Vppd $ V(DP/DN) $1.0 Vppd
V(PKx) = 0.09+ 0.096 V(DP/DN),
Fin = 4 MHz
ISL
Channel disabled
Servo Output Leakage
Current
0.1
VCOS PKA-D Channel to
Channel Offset
1 Vppd input to DP/DN
PKA-PKB, PKC-PKD
-10
+10
mV
VAOS PKA-D Absolute Offset
Magnitude
1 Vppd input to DP/DN
(across all channels)
0
20
mV
Note 1: Not directly measureable
4-57
II
SSI32P3013
Pulse Detector with
Programmable Filter
PACKAGE PIN DESIGNATIONS
VIA-
23
(Top View)
VJA+
24
VRC
VRG
25
VTH
VOA+
26
PKD
VOA-
27
PKC
IN+
28
PKB
IN-
29
PKA
VBP
30
illD
THERMAL CHARACTERISTICS: 9jA
44-Lead SOM
31
GTC
10
31
GiS
IFO
RX
BYP
IFI
11
33
GTA
AGND
12
34
SOIF-
ON+
13
35
SDIF+
ON-
14
36
LZlFD
00-
15
37
fiG
WG
00+
16
38
ON
17
39
OGND
OP
18
40
!U5O
CN
19
41
VCO
CP
20
42
1'iD
VCA
21
43
RO
DO
22
44
H5iJJ
44-Lead SOM
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
SSI32P3013
40-Lead SOM
ORDER NUMBER
32P3013-CM
PACKAGE MARK
32P3013-CM
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights ortrademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1193 - rev.
4-58
©1993 Silicon Systems, Inc.
Patent Pending 90-049
551 32P3015/3016
Pu Ise Detector with
Programmable Filter
I;f! Pb' ita, Mr.,;; .b" t" ;.
October 1993
DESCRIPTION
FEATURES
The SSI 32P3015/3016 is a bipolar integrated circuit
that provides all the data processing for pulse detection
and four-burst servo capture from encoded read
signals. This device can handle a NRZ data rate of
72 Mbitls.
The SSI32P3015/3016 includes an AGC amplifier with
AGC charge pump, a programmable 7-pole Bessel low
pass filter, a pulse qualification circuit, and a 4-burst
servo capture circuit. AutomaticAGC control maintains
a constant signal level into the pulse qualifier, and
achieves fast write-to-read recovery. A time
differentiator is included in the servo signal path, if so
needed. The 32P3016 also has a level pin output.
Ideal for constant density recording applications, the SSI
32P3015/3016 low pass filter has a programmable 9-27
MHz bandwidth and 0-13 dB boost for pulse slimming. A
time derivative of the read signal is also provided by the
filter for time qualification in peak detection.
The SSI 32P3015/3016 requires only a +5V supply
voltage and are available in a 48-pin TQFP package. The
32P3015 is also available in a 44-pin SOM package.
..
•
..
..
..
..
..
..
..
It
Compatible with 72 Mblt/s data rate operation
Fast attack/decay modes for rapid AGC
recovery
Automatic AGC actions: Low Drift AGC hold,
fast AGC recovery, and low AGC input
Impedance control signals
Includes programmable pulse slimming
equalization and programmable channel filter
and dlfferentlator with no external filter
components
±0.5 ns filter group delay variation from 0.3FC
to FC = 27 MHz
Independent positive and negative threshold
qualification to suppress error propagation
0.5 ns max pulse pairing
Servo differentiator and 4-burst servo capture
+5V only operation
4S-pin TQFP package,44-pln SOM 32P3015 only
BLOCK DIAGRAM
~
~
~
i
88 H
i!l :!i
<
!! " g
S!
~ ~ ~
TTl
v....
RC
VIA·
PEel
III
RX
VB'
IFO
IFI
BY,
""'"
ves
1m
"'"
veA
1093 - rev.
II
SSI 32P3015/3016
Pulse Detector with
Programmable Filter
AGe ACTIONS
FUNCTIONAL DESCRIPTION
The AGC loop maintains aconstant DP/DN signal level
at a nominal level, -1 Vppd. The AGC actions are
current charging and discharging to/from the external
BYP integrating capacitor, and are classified into the
following modes:
The SSI 32P3015/3016 Pulse Detector/Filter with 4Burst Servo Capture is designed to support a
72 Mbit/sNRZ data rate. The signal processing circuits
include a wide band variable gain amplifier, a
sophisticated dual-rate AGC charge pump, a
programmable electronic filter, a pulse qualifier, a
servo differentiator and a 4-burst servo capture circuit.
Normal Read and Servo Read Mode
(RG = X. WG = 1) SG = X
Slow Decay: When the DP/DN signal is below 1 Vppd,
a slow decay current, Id, charges the BYP capacitor.
The AGC amplifier gain is increased slowly. This slow
decay current tracks with the bandwidth of the filter. Id
= 0.008 x IFI. At T = 27°C, the maximum Id is 4.5 !1A
when the filter cutoff frequency is 27 MHz.
MODES OF OPERATION
The SSI 32P3015/3016 can operate in one of three
modes as controlled by RG, WG, and SG.
Normal Read Mode RG
= 0, WG = 1, SG = X
In the normal Read Mode, the AGC actions areactive.
The AGC amplifier processes the input signal pulses;
one-shot pulses are generated at the RDand RD
outputs for each qualified signal peak. The ROO output
buffer, which is a TTL buffer of the RD/RD, is disabled
and its output is pulled up high to reduce jitter and
noise.
Slow Attack: When the DP/DN signal exceeds 1
Vppd, but is below 1.25 Vppd, a slow attack current,
Ich, discharges the BYP capacitor. The AGC amplifier
gain is decreased. The slow attack current is 20 times
that of the slowdecay current. Thus, for a given BYP
capacitor, the slow attack response time is quicker than
the slow decay response.
Servo Read Mode RG = 1, WG = 1, SG = 1
Fast Attack: When the DP/DN signal exceeds 1.25
Vppd, the device enters a fast attack mode. A fast
attack current, Ichf, discharges the BYP capacitor. The
AGC amplifier gain is quickly lowered. The fast attack
current is seven times that of the slow attack current.
,In the servo Read Mode, the AGC actions remain
active (See note 1). The servo signal is amplified,
fullwave rectified, differentiated and gated to the proper
peak capture capacitor. The pulse qualifier remains
active, and the ROO output is active to aid in servo
decode.
In servo Read Mode, constant AGC amplifier gain is
generally desirable. Without an external AGC hold
control, the servo data amplitude should be made
lower than that of the data signal priorto the servo read
mode. The SSI 32P3015/3016 then enters the slow
decay mode, which has a very slow effect on the AGC
amplifier gain.
Write Mode RG = X, WG = 0, SG =X
In the Write Mode, the AGC actions are suspended.
The AGC amplifier input impedance is clamped low to
facilitate fast recovery. The ROO output is disabled and
pulled up high to reduce jitter and noise.
Write Mode (RG = X, WG = 0) SG = X
In the write mode, the AGC charge pump is disabled.
This holds the AGC amplifier gain at its previous value.
AGC AMPLIFIER
The wide band AGC amplifier amplifies the read signal
from the read/write pre-amp to a signal level acceptable
at the pulse qualifier. The AGCamplifier gain is an
exponential function of the BYP voltage when
referenced to VR.
Notes:
1 . The servo signal should have a lower amplitude than
the data signal priorto the servo read mode. Servo read
should be completed before and significant change in
AGC amplifier gain is resulted from the slow decay
AGC mode.
Av=.Ao exp[(VBYP-VR)j (See note 2)
K
2. In a closed loop, the sensitivity of Ao and K to typical
process variations is irrelevant. The typical values of
Ao and K are provided for reference only, and not
tested in production. AO = 11, K = 0.22, VR = 3.6.
4-60
SSI 32P3015/3016
Pulse Detector with
Programmable Filter
Write-to-Read Transition
(RG = X, WG = 0-to-1) SG
=X
When the SSI 32P3015/3016 switches from the write
to read mode, i.e., WG 0-to-1 transition, the device
remains in the low input impedance state for a preset
time period. For the next time period, the device then
enters either the fast decay or attack mode depending
on the signal level at the DP/DN pins. The time period,
t, is determined by an external resistor, RT, from the LZI
FD pin to ground.
1: (I1S) = RT(kQ)
28
Forexample, with RT = 38 kQ, each time period is 1.36 J.lS.
PROGRAMMABLE FILTER
The SSI 32P3015/3016 includes a programmable low
pass filter following the AGC amplifier for (1) 2X voltage
gain from the AGC amplifier outputto the pulse qualifier
input, (2) noise limiting, (3) pulse slimming, and (4)
provision of a time differentiated signal. The low pass
filter is of a 7-pole 2-zero Bessel type. The filter's unboosted -3 dB bandwidth, defined as the cutoff
frequency, is programmable from 9-27 MHz; the high
frequency equalization is programmable from 0-13 dB
at the cutoff frequency.
Forprogrammable cutofffrequency, an external current
DAC can be used. IFO should be the reference current
into the DAC. The DAC output current drives IFI, which
is then proportional to the IFO. The DACF in the SSI
32D4661 Time Base Generator is designedto control Ic
of the Silicon Systems programmable filters. When the
DACF, which has a 4X current gain from its reference to
fullscale output, is used, 5 kQ RX is used. The fc is then
given by:
F Code
fc(MHz) = 27·-=--127
where F_Code is the decimal code equivalent to the 7bit input into the DACF.
The high frequency equalization is programmable with
two pins: VRG and VBP. The VRG is a bandgap
reference voltage, 2.3V typically. The voltage at the
VBP pin determines the amount of high frequency
boost at the cutoff frequency. The boost function is as
Kb.VBP
follows:
Boost(dB)=20Io91O[( VRG )+1]
Kb = 3.041 + 0.0276· fci
where fci is the ideal cutoff frequency in MHz.
The filter input is ac-coupled from the AGC amplifier
output. The filter's normal low pass output is ac-coupled
to the data channel of the pulse qualifier. The
differentiated low pass output is ac-coupled to the time
channel of the pulse qualifier.
For a fixed boost setting, a resistor divider between
VRG to ground can be used with the divided voltage at
the VBP pin. For programmable equalization, an
external voltage DAC can be used. VRG should be the
reference voltage to the OAC. The DAC output voltage
is then proportional to the VRG. The DAC in the SSI
32D4661 is designed to control the magnitude
equalization of Silicon Systems programmable filters.
The normalized 7-pole 2-zero Bessel filter transfer
function is given in Figure 1.
When DACs are used, the boost relation then reduces
S Code
to:
Boost(dB)=201091O[(Kb' 127 )+1]
The cutoff frequency, fc, is programmable with 3 pins:
RX, IFO and IFI. At the RX pin, an external resistor to
ground establishes a reference current:
PULSE QUALIFICATION
The SSI32P3015/3016 validates each DP/DN peak by
acombinationof level qualification and time qualification.
In level qualification, a dual-comparator threshold
detection eliminates errors due to low level additive
noise. In time qualification, the filter's differentiated
output is used to locate signal peaks.
IFO= 0.75 atT=270C
Rx '
IFI should be made proportional to IFO for Ic
temperature stability. The cutoff frequency is related to
the RX resistor, IFO and IFI currents as the following:
Level Qualification
fC(MHz)=27'~'~
The dual-comparator architecture allows independent
detection for positive and negative peaks. One
comparator detects a positive peak by comparing the
data signal with a positive threshold. The other
comparator detects a negative peak by comparing the
data signal with a negative threshold. Each comparator
has a small hysteresis, 20% of the set threshold, to help
qualify signals which just clear the set threshold.
IFO Rx(kQ)
For a fixed cutoff frequency setting, IFO and IFI can be
tied together. The cutoff frequency equation then
reduces to:
fC(MHz)=27'~
Rx(kQ)
4-61
I
SSI 32P3015/3016
Pulse Detector with
Programmable Filter
DP/DN signal produces 0.95 Vpeak output. With no
signal input, the outputs are set close to ground, with
little or no offset common to all four channels.
FUNCTIONAL DESCRIPTION (continued)
The SS132P3015/3016 comparator thresholds are set
by a DC voltage at the VTH pin, such as from a resistor
divider from VCA to VRC (see note 3). The threshold at
each comparator can be computed as: Hysteresis Gain
x (VTH - VRC). The thresholds at the two comparators
are of the same magnitude, but of opposite polarity.
GTA, GTB, GTC, and GTD are now generated on-chip,
using STROBE andSG as inputs. N.B.: There must be
exactly 4 strobe pulses withing the TRUE time of SG.
A two-bit counter and 4 gates produce:
The SS132P3015/3016 has three sets of pulse detector
outputs: RD/RD, RDO, and DO. RD/RD output is the
pseudo-ECL differential output. Corresponding to each
validated peak of the DP/DN signal, a one-shot pulse
occurs at the RD/RD output. The pulse width of the
one-shot pulse is determined by, an internal timing
circuit, and can be calculated by the equation below:
GTA from the first STROBE pulse,
GTS from the second STROBE pulse,
GTC from the third STROBE pulse,
GTD from the fourth STROBE pulse.
Resetting of PKA, PKB, PKC, and PKD must stitt be
done externally.
PWRD = 0.1 ns + (1.33 ns/kQ) RRX
VCS Pin: This is a third +5V pin, intended not to be
switched off by the customer in order to power down.
RDO is the TTL output of the pulse detector, logically
equivalent to RD/RD. Again, a one-shot pulse occurs
at the RDO output for each validated peak of the DPI
DN signal. The pulse width ofthis one-shot pulse is also
specified in the electrical specification. DO output is a
test point used to monitor the outputs of the internal
comparators. It is an open-emitter output requiring a 5
kQ external resistor pull-down to ground.
VCS is used as the high-voltage tie point for the ESD
diodes from the 5 TTL-level input pins:
1) STROBE
2)SG
3) RG
4)WG
The 32P3016 has a level output which is an amplified
peak capture of DP-DN. It can be computed as level
gain xDP - DN ppd + VRC.
5) HOLD
The purpose of this is to make it impossible for one or
more of the TTL-level input drives to attempt to support
the chip, via ESD diodes, when VCC and VCD are
switched off.
Four-Burst Servo Differentiator and Capture
The SSI32P3015/3016 supports advanced embedded
4-burst servo technique. The signal at the DP/DN input
can be time differentiated, fullwave rectified, and gated
onto the selected peak capture output.
VCS also supports the held servo voltages at pins PKA,
PKB, PKC, and PKD. This is done by using VCN as the
+5V supplyforSSIN, PKCTRLN (via VPB), and LSERVO.
The transfer function from the DP/DN to the servo
fullwave rectifier input is:
Av
RRX Pin: This pin connects to an external preciSion,
low T-C resistor, which is used to set the discharge
currents of the one-shots, OSE_A and OSE_B, which
in turn determine the pulse widths of the TTL ouput
pulse, RDT, and of the ECL ouput pulses, RD and RD.
This permits adjustment olthe pulse widths for differe nt
applications and/or for variations in on-Chip
capacitances, and reduces the pulse-width changes
caused by "corner" conditions.
2380Cs
LCs 2 +(R+48.1)Cs+1
where: R, L, and C are external passive components
across SDIF±
15 pF < C < 125 pF
s=jw
When the time differentiation function is not desired, a
2 kQ resistor should be used across the SDIF± pins.
Note 3: VCA is the +5V supply. VRC is the bandgap
voltage referenced from VCA, I.e., VRC = VCA - VRG.
The transfer function from th,e servo fullwave rectifier
input to the peak capture output is set so that a 1 Vppd
4-62
SSI 32P3015/3016
Pulse Detector with
Programmable Filter
+2.94933
S'+ 3.22597S + 2.94933
INPUT
3.32507
4.20534
s' + 2.75939S + 3.32507
s' + 1.82081S + 4.20534
Transfer function normalized for W = 21tfc
=1
AA and Ao are adjusted lor gain 01 2 at I = 0.67Ic.
Frequency scaling S = Sl21tfc
-KS'
S' + 3.22597S + 2.94933
FIGURE 1: Bessel Filter Transfer Function
BOOST (dB)
K = 2.94933 (10-2-0
-
-
1)
TABLE 1: Typical Change inf· 3 dB Point with Boost
Gain@fc (dB)
Gain@peak (dB)
fPeak/fc
f·3dB/fc
0
-3
0.00
no peak
1.00
0
1
-2
0.00
no peak
1.20
0.36
2
-1
0.00
no peak
1.47
0.76
3
0
0.15
0.62
1.74
1.22
Boost (dB)
K
4
1
1.00
1.08
1.96
1.73
5
2
2.12
1.24
2.13
2.30
6
3
3.35
1.24
2.28
2.94
7
4
4.56
1.39
2.42
3.65
8
5
5.82
1.39
2.54
4.46
9
6
7.04
1.39
2.66
5.36
10
7
8.24
1.39
2.77
6.38
11
8
9.41
1.39
2.88
7.52
12
9
10.55
1.39
2.98
8.79
13
10
11.70
1.55
3.08
10.22
Notes: 1. Ic is the original programmed cutoff frequency with no boost.
2. 1-3 dB is the new -3 dB value with boost implemented.
3. Ipeak is the frequency where the magnitude peaks with boost implemented.
e.g.,
Ic = 13 MHz when boost = 0 dB
if boost is programmed to 5 x dB then
Ipeak = 16.12 MHz
I - 3 dB = 27.69 MHz
4-63
I
551 32P30t5/3016
Pulse Detector with
Programmable Filter
PIN DESCRIPTION
INPUT PINS
NAME
TYPE
DESCRIPTION
VIM, VIA-
I
AGC Amplifier input pins. ..
IN+,IN-
I
Equalizerlfilter input pins.
DP,DN
I
Data inputs to data comparators and fullwave rectifier.
CP,CN
I
Differentiated data inputs to the clock comparator.
VTH
I
Threshold level setting input for the data comparators.
STROBE
I
TTL input. Enables servo gate according to Figure 3.
RG
I
TTL compatible input. When low, the device is in normal Read Mode.
WG
I
TTL compatible input. When low, the device is in Write Mode. When both RG
and WG are low, the device is in Servo Mode.
SG
I
TTL compatible input. When high the corresponding servo gate channel is
enabled.
HOLD
I
TTL compatible input. When low the AGC action is suspended.
OUTPUT PINS
NAME
TYPE
DESCRIPTION
VOM, VOA-
0
AGC amplifier output pins.
ON+,ON-
0
Equalizerlfilter normal output pins.
OD+,OD-
0
Equalizer/filter differentiated output pins.
DO
0
ECL compatible data comparator latch output pin.
RD,RD
0
ECL compatible read data output pins.
TTL compatible read data output.
RDO
0
SDIF+, SDIF-
-
Pins for external differentiating network for servo data.
PKA,PKB
0
Open npn emitter outputs that provide a fullwave rectified signal from the
PKC,PKD
LEVEL
servo differentiator. These outputs are referenced to AGND. These outputs
are high impedance when not enabled by STROBE and SG.
0
Open NPN emitter output that provides an amplified fullwave rectified signal
of DP-DN (32P3016 only.) The signal is referenced to VRC.
4-64
SSI 32P3015/3016
Pu Ise Detector with
Programmable Filter
ANALOG PINS
NAME
TYPE
DESCRIPTION
VRG
-
VBP
-
The equalizer high frequency boost is set by an external voltage applied to this
pin. VBP must be proportional to VRG. Programmable boost is implemented
by using a DAC that uses VRG as its reference. A fixed amount of boost can
be set by an external resistor divide network connected from VBP to VRG and
GND.
RX
-
Pin to set filter reference current. External resistor Rx from this pin to ground
sets the filter reference current IFO.
IFO
-
Reference current output pin. The reference current is normally supplied as
the reference current to a current DAC which generates the programmable
input current for the IFI pin.
IFI
-
Programmable filter input current pin. The filter cutoff frequency is proportional
to the current into this pin. The current must be proportional to the reference
current out of IFO. A fixed filter cutoff frequency is generated by connecting
IFO to IFI and selecting Rx to set the desired frequency.
LZlFD
-
Pin for external resistor to set timing for both Low-Z input and fast decay
modes.
BYP
-
The AGC integrating capacitor CA is connected between BYP and VCA.
RRX
VRC
VCA, VCD, VCS
AGND,DGND
Pin to set, via external R, output pulse widths.
Reference voltage pin for SERVO and LEVEL. VRC is referenced to VCA.
Reference voltage pin for the programmable filter. VRG is referenced to
ground.
Analog, Digital, and Servo +5V
Analog and Digital grounds.
4-65
II
SSI 32P3015/3016
Pulse Detector with
Programmable Filter
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, 4.5V fC > 9 MHz
0.2
0.6
mA
fC = 27 MHz
-13
13
%
1.25
5
kQ
EQUALIZER/FIL TER
The input signals are AC coupled to IN+ and IN-
,
",
fc
Filter Cutoff Frequency
RX = 5kQ
fC = 27 x IFI/(4 x IFO) MHz
4 ~ IFO/IFI ~ 4/3
IFO
IFO Reference Current
IFO = 0.75/RX; Tj = 27°C
5kQ > RX > 1 .25 kQ
-
IFI
IFI Program Current Range
FCA
FCA Filter FC Accuracy
RX
RX Range
AO
Normal Low Pass Gain
AO = (ON ±) / (IN±)
Fin = 0.67fc
1.4
2.2
VIV
AD
Differentiated Low
Pass Gain
AD = (OD ±) / (IN±)
Fin = 0.67fc
0.8AO
1.2AO
VIV
FBA Frequency Boost Accuracy
TGD1
TGD2
Group Delay Variation
VBP= VRG
-1.5
+1.5
dB
VBPIVRG = 0.5
-1.0
+1.0
dB
fc = 27 MHz, VBP = 0 to VRG
fc > Fin> 0.3 fC
-0.5
+0.5
ns
Ie = 9 to 27 MHz, VBP = 0 to VRG
-2.5
+2.5
0/0
fc > Fin> 0.3 fc
4-68
SSI 32P3015/3016
Pulse Detector with
Programmable Filter
EQUALIZER/FILTER (continued)
The input signals are AC coupled to IN+ and IN-.
PARAMETER
CONDITIONS
MIN
VOSVF
200 j1A,IFk600 j1A
-200
Output Offset Voltage
Variation
DRF
VOF Filter Output
Dynamic Range
RINF
Filter Input Resistance
CINF
Filter Input Capacitance
ROF
Filter Output Resistance
10F
VNN
VND
THO = 1.5% max
Fin = 0.67 fC
Eout Output Noise
Voltage; 00+, 00-
MAX
UNIT
200
mV
1.2
Vpp
3.0
kQ
10+ = 1.0 rnA
Filter Output Current
Eout Output Noise
Voltage; ON+, ON-
NOM
-1.0
7
pF
60
Q
1.0
rnA
BW = 100 MHz, RS = 50Q
VBP = 0, fC = 27 MHz
2.7
mVRms
BW = 100 MHz, RS = 50Q
VBP = VRG, fC = 27 MHz
5.7
mVRms
BW = 100 MHz, RS = 50Q
VBP = 0, fC = 27 MHz
5.5
mVRms
BW =100 MHz, RS = 50Q
VBP = VRG, fC = 27 MHz
13.0
mVRms
DATA COMPARATOR
The input Signals are ACcoupled to OP and ON.
VID
DP-DN Signal Range
1.5
Vpp
14
kQ
Differential Input
Capacitance
5
pF
VOSD"
Comparator Offset
Voltage
4
mV
LG""
Level Output Gain
0.788
VIV
RIND
Differential Input
Resistance
CIND
8
DP - ON = 0.25 to 0.5 VDC
LG = (VLEVEL - VRC)/2 • (DP -DN)
0.712
20
LBW'" Level Output Bandwidth
±1 dB referenced to 1 MHz
VLOS""
Output - VRC, IL = 50 j1A
-30
+30
mV
0.3 < VTH-VRC < 0.9
0.42
0.49
VIV
HYS
Level Offset Voltage
Threshold Voltage Gain
VSH*
Threshold Voltage
Hysteresis
TPDD
Propagation Delay
IVTH
To
~O,
DO
.20 x
GHYSx
(VTH
-VRC)
VIV
6
ns
2
VTH Input Bias Current
• Not externally measurable
MHz
•• 32P3016 only
4-69
j1A
II
SSI 32P3015/3016
Pulse Detector with
Programmable Filter
ELECTRICAL SPECIFICATIONS (continued)
Unless otherwise specified, 4.5V
48 47 46
c- o :x:
J a: J ,i; >a:
> :> > I:;;
0
>
"
45 44 43 42
VBP
.,
+
- g
> > :> :>
>
""-'" "c-0
S'
"'
~ it"
~
~ D-
D-
~
40 39 38 37
36
PKB
IN+
NIC
35
PKA
IN-
35
STROBE
N/C
3.
STROBE
VBP
3.
SG
IFO
33
SG
IFO
33
RRX
RX
32
RRX
AX
32
LEVEL
IFI
31
VCS
IFI
31
VCS
AGND
30
SOIFN
AGNO
30
SDIFN
ON+
29
SOIF?
ON+
29
SOIF?
ON-
28
LZlFD
ON·
28
LXlFD
FiG
WG
AGND
7"
N/C
10
27
FiG
NIC
10
27
00-
11
26
WG
OD-
11
26
OC+
12 13
Z
,.
15 16 17 18 19
D-
Q
" "
Z
z coQ
0
Q
>
:5
24 25
22
l~ "cr:
i@
0
Q
>
OD+
OGNO
DGND
z
I~
a.
" "
SSI32P3015
48-Lead TQFP
11
z
z
a.
<.)
Q
Q
Q
>
"o ~c:
fjllfil ~ ~
SSI32P3016
48-Lead TQFP
'Both Pin 7 and Pin 36 of the 32P3016 must be
connected to PCB analog ground. Pin 36 is not
connected to the chip's circuits. It is used as an
electrostatic shield.
Advance Information: Indicates a product still in the design cycle. and any specifications are based on design goals only. Do not use
for final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems.
Silicon Systems reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the data sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1093 - rev.
4-73
©1991 Silicon Systems, Inc.
Patent Pending 90-049
I
Notes:
4-74
SSI32P3040
Pulse Detector with
Programmable Filter
January 1994
DESCRIPTION
FEATURES
The SSI 32P3040 is a bipolar integrated circuit that
provides all data processing necessary for detection
and qualification of encoded read signals. The circuit
will handle a data rate of 32 Mbitls.
In read mode the SSI 32P3040 provides amplification
and qualification of head preamplifier outputs. Pulse
qualification is accomplished using level qualification
of differentiated input zero crossings. An AGC amplifier
is used to compensate for variations in head preamp
output levels, presenting a constant input level to the
pulse qualification circuitry. The AGC loop can be
disabled so that a constant gain can be used for
embedded servo decoding or other processing needs.
Write to read transient recovery is enhanced by providing AGC input impedance switching and a selectable
Fast Recovery mode that provides a higher decay
current.
Additionally, the SSI 32P3040 contains an integrated
programmable electronic filter with cutoff frequencies
between 2.5 and 13 MHz. High frequency boost (for
pulse slimming) of up to +9 dB is also provided. The SSI
32P3040 requires only a +5V power supply and is
available in 36-lead SOM and 32-lead TQFP packages.
•
•
•
Compatible with 32 Mbitls data rate operation
Fast attack/decay modes for rapid AGC recovery
Dual rate charge pump for fast transient recovery charge pump currents track programmable
channel bandwidth
•
Low drift AGC hold, fast AGC recovery, and low
AGC input impedance control signals. Circuitry
supports programmable gain non-AGC operation
•
Temperature compensated, exponential control AGC
•
Precision wide bandwidth fullwave rectifier
•
Supports programmable pulse slimming equalIzation and programmable channel filter and
differentlatorwith no external filter components
•
±2% Filter group delay variation from O.3FC to
FC
•
•
Servo burst output available
•
Differential hysteresis qualifier comparator to
ease clock channel timing
Accurate feed forward or fixed threshold set
BLOCK DIAGRAM
0194 - rev.
4-75
I
SSI32P3040
Pulse Detector with
Programmable Filter
FEATURES (continued)
•
•
•
•
•
goes low. In applications where AGC action is not
desired, the BYP voltage can be set by a resistor divider
network connected from VCC to VRC. If a
programmable gain is desired, the resistor network
could be driven by a current DAC. The precision
fullwave rectifierproduces an accurate Level and Servo
output signal. These outputs are referenced to the
reference voltage VRC. SERVO and LEVEL are
buffered open emitter outputs with 100 ohm series
current limiting resistors. These outputs could be further
filtered with external capaCitors.
1 ns max pulse pairing with sine wave input
5 mW low power idle mode
TTL read data output
+5V only operation
36-pin SaM and 32-pin TQFP packages
FUNCTIONAL DESCRIPTION
LEVEL has an internal 50 ).lA discharge current source.
An optional Servo output capaCitor discharge circuit can
be included. An external resistor connected to the RX
pin sets the electronic filter reference current which is
the source from pin IFO. If a programmable frequency
response is desired, a portion of the current from IFO,
which is proportional to absolute temperature, must be
injected into pin IFI. This could be accomplished by a
current DAC. Some frequency response programming
may be accomplished by connecting IFO to IFI and
switching different resistors to pin RX. Frequency boost
is accomplished by varying the voltage at VBP. VBP has
a nominal 100 mV built-in offset so that the circuit has 0
dB boost forVBP below 100 mV. The voijage at VBP
should be proportional to the reference voijage at pin
VRG.
The SSI32P3040 Pulse Detector is designed to support
a 32 MbiVs data rate. The signal processing circuits
include a wide band variable gain amplifier, a
programmable electronic filter, differentiator and pulse
slimming equalizer, a precision wide bandwidth
fullwave rectifier, and a dual rate charge pump. A fully
differential filter, differentiator, equalizer, and fullwave
rectifier are provided to minimize external noise pick-up.
To optimize recovery for constant density recording, the
AGC charge pump current tracks the programmable
filter current IF!. The differentiator zero tracks the
programmable filter cutoff frequency. Thus in constant
density recording applications, an approximately
constant differentiated signal amplitude is maintained.
The desired filter response and equalization are easily
programmed with the SSI 3204661, Time Base
Generator DACs. A dual rate attack charge pump and a
Fast Decay mode are included for fast transient
recovery. At maximum IFI current, the normal AGC
attack current is 0.28 mAo When the signal exceeds
125% of the nominal signal level, the attack current is
increased by a factor of 5. The nominal decay current at
max IFI is 5.6).lA. The decay current is increased 20
times when in the fast decay mode. In this mode,
transients that produce low gain will recover more
rapidly with the fast decay current, while transients that
produce high gain will put the circuit in the fast attack
recovery mode. The decay modes are automatically
controlled within the device. When R/W is low, the AGC
is in its hold mode and its input impedance is switched
low. When R/W is switched high. the AGC remains in the
hold and low input impedance state for 0.7!lS and then
switches to the fast decay mode for 0.7 ~s. The AGC
amplifier input impedance is reduced to allow quick
recovery of the AGC amplifier input AC coupling
capacitors. When the HOLD input is low, the AGC action
is stopped and the AGC amplifier gain is set by the
voltage at the BYP pin. In most applications, the BYP pin
voltage is stored on an external capacitor when HOLD
A differential comparator with floating hysteresis
threshold allows differential signal qualification for noise
rejection. An accurate feed forward qualification level is
generated by cornparing the difference between LEVEL
andVRC. VRC is referenced to VCA. Thus with the VTH
resistor network connected from VCA to VRC, an
accurate fixed threshold can be established. The
threshold is clamped to a minimum value of 50 mV. Thus
a qualified signal must exceed this minimum level even
when the VTH-VRC voltage is zero. A qualified signal
zero crossing triggers the output one shot. The one shot
period is set internally. Low level differential outputs are
provided for high speed operation and to rninimize noise
generation.
4-76
SSI32P3040
Pulse Detector with
Programmable Filter
INPUT
+2.94933
3.32507
4.20534
s' + 3.22597S + 2.94933
s' + 2.759395 + 3.32507
s' + 1.82081 S + 4.20534
Transfer function normalized for W = 21tfc = 1
AN and Ao are adjusted for gain of 2 at f = a.67fc.
Frequency sca!ing S = S'2n:fc
S' + 3.22597S + 2.94933
FIGURE 1: Bessel Filter Transfer Function
BOOST (dB)
K = 2.94933 (10-20-
-
1)
TABLE 1: Typical Change inl - 3 dB Point with Boost
Boost (dB)
Gain@/e (dB)
Gain@peak (dB)
IPeak/le
1-3dB/le
K
0
-3
0.00
no peak
1.00
0
1
-2
0.00
no peak
1.20
0.36
2
-1
0.00
no peak
1.47
0.76
3
0
0.15
0.62
1.74
1.22
4
1
1.00
1.08
1.96
1.73
5
2
2.12
1.24
2.13
2.30
6
3
3.35
1.24
2.28
2.94
7
4
4.56
1.39
2.42
3.65
8
5
5.82
1.39
2.54
4.46
9
6
7.04
1.39
2.66
5.36
10
7
8.24
1.39
2.77
6.38
11
8
9.41
1.39
2.88
7.52
12
9
10.55
1.39
2.98
8.79
13
10
11.70
1.55
3.08
10.22
Notes: 1.
-_.
fC is the original programmed cutoff frequency with no boost.
2.
f - 3 dB is the new -3 dB value with boost implemented.
3.
fpeak is the frequency where the magnitude peaks with boost implemented.
e.g., fC = 13 MHz when boost = 0 dB
if boost is programmed to 5 dB, then / - 3 dB = 27.69 MHz
/peak = 16.12 MHz
4-77
II
SSI32P3040
Pulse Detector with
Programmable Filter
PIN DESCRIPTION
INPUT PINS
NAME
TYPE
DESCRIPTION
I
AGC Amplifier input pins.
IN+,IN-
I
Equalizerlfilter input pins.
DP,DN
I
Data inputs to data comparators and fullwave rectifier.
CP,CN
I
Differentiated data inputs to the clock comparator.
VTH
I
Threshold level setting input for the data comparators.
R/W
I
TIL compatible input when high puts the charge pump in the normal mode.
PWR
I
TIL compatible input when high puts the circuit in its normal operating mode.
HOLD
I
TIL compatible input when low disables the AGC action by turning Off the
charge pump.
VOA+ VOA-
0
AGC amplifier outputpins.
ON+,ON-
0
Equalizerlfilter normal output pins.
00+,00-
0
Equalizer/filter differentiated output pins.
DOUT
0
Test point for monitoring the data F/F D-input. Usage requires an external
2.4 kQ resistorfrom DOUT to GND. (Not available in 32-pin TOFP package.)
COUT
0
Test points for monitoring the data F/F clock inputs. Usage requires an
external 2.4 kQ resistor from DOUT to GND.
(Not available in 32-pin TOFP package.)
VIA+, VIA-
OUTPUT PINS
RD
0
TIL compatible read data output pins.
LEVEL
0
Open NPN emitter output that provides a fullwave rectified signalforthe VTH
input. The signal is referenced to VRC.
SERVO
0
Open NPN emitteroutputthat provides a fullwave rectified servo signal. The
Signal is referenced to VRC.
-
Reference voltage pin for SERVO and LEVEL. VRC is referenced to VCA.
VRG
VBP
-
The equalizer high frequency boost is set by an external voltage applied to
this pin. VBP must be proportional to VRG. Programmable boost is implemented by using a DAC that uses VRG as its reference. A fixed amount of
boost can be set by an external resistor divide network connected from VBP
to VRG and GND.
RX
-
Pin to set filter reference current. External resistor Rx from this pin to ground
sets the filter reference current IFO.
ANALOG PINS
VRC
IFO
Reference voltage pin for the programmable filter. VRG is referenced to
ground.
Reference current output pin. The reference current is normally supplied
as the reference current to a current DAC which generates the programmable input current for the IFI pin.
4-78
SSI32P3040
Pulse Detector with
Programmable Filter
PIN DESCRIPTION
(continued)
ANALOG PINS (continued)
NAME
TYPE
DESCRIPTION
IFI
Programmable filter input current pin. The filter cutoff frequency is proportional
to the current into this pin. The current must be proportional to the reference
current out of IFO. A fixed filter cutoff frequency is generated by connecting
IFO to IFI and selecting Rx to set the desired frequency.
BYP
The AGC integrating capacitor CA is connected between BYP and VCA.
VCA, VCD,VCD2
Analog and Digital +5 volts.
AGND,DGND,
DGND2
Analog and Digital grounds.
I
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, 4.5V0.9 Final Value
BYP::;, 1000 pF, IFI = max
Gain Decay Time
Q
200
4-80
-200
5
34
+200
mV
10
nV/.yHz
44
p.s
SSI32P3040
Pulse Detector with
Programmable Filter
ANALOG PINS (continued)
PARAMETER
CONDITIONS
TGA
VIA± = 120 mV to 240 mV
VOA± <1.1 Final Value
BVP ~, 1000 pF, IFI = max
Gain Attack Time
MIN
NOM
MAX
UNIT
1.5
2
!.IS
AGCCONTROL
The input signals are AC coupled to DP and DN. Ca = 1000 pF, LEVEL load = 50 ).lA, SERVO load = 100).lA.
VDI
DP-ON Signal Input Range
ALO
Level (Servo) Output Gain
DP-DN = 0.25 to 0.5 VDC
LG = (VLEVEL - VRc)/2(DP-DN)
0.73
1.4
Vpp
0.81
VN
BWL
level (Servo) Output Bandwidth
1 dB
VLO
Level Offset Voltage
Output-VRC, IL = 50 ).lA
30
mV
VSO
Servo Offset Voltage
Output - VRC, IL = 100).lA
30
mV
ZLS
level (Servo) Output Impedance
IL = 100).lA
300
n
ID
Discharge Current
IDF
Fast Discharge Current
ICH
Charge Pump Attack Current
ICHF
Charge Pump Fast Attack
Current
IBVP Pin Leakage Current
VRC Reference Voltage
IVRC Output Drive
VRG Reference
IVRG Source Current
VAGC Pin Voltage
15
MHz
200
0.7 to 1.4 ~s after R/W goes
high
DP-DN = 1.35 Vpp
HOLD = low, VBYP = VCC -1.5V
0.008 x
IFI
rnA
20 x ID
rnA
50x ID
rnA
5x ICH
rnA
-0.1
VCC-2.S2
-0.75
2.15
1
0.1
VCC-2.1S
0.75
2.5
).lA
V
rnA
V
rnA
V
13.5
MHz
mV
0.7
rnA
VRC+l.0
EQUALIZER/FILTER The input signals are AC coupled to IN+ and IN-.
Ic
VRX
IFOR
Fi~er Cutoff Frequency
PTAT Reference Current
Set Output Vo~age
PTAT Reference Current
Output Current Range
Ic = 19.14(IFIIIFO)(1/Rx)
TA = 25°C
IRX = 0 - 0.7 rnA
Rx > 1,21 kn
TA = 25°C
1.21 kn < Rx < 7.73 kn
IFO = VRxlRx
4-81
2.5
850
0.11
II
SSI32P3040
Pulse Detector with
Programmable Filter
EQUALIZER/FILTER (continued)
PARAMETER
IFIR
PTAT Programming
Current Range
CONDITIONS
MIN
TA = 25°C, VRX = 850 mV
VBPR Input Voltage Range
IBP
NOM
MAX
UNIT
0.11
0.7
mA
0
VRG
V
3
~
Input Bias Current
FCA
FilterFC Accuracy
FC = 5 to 13.5 MHz
-12
+12
%
AO
[(ON±)]/[(IN±)]
Normal Gain
F = 0.67 FC
1.4
2.2
VN
AD
[(OD±)]/[(IN±)]
F = 0.67 FC
1.0AO
1.3AO
VN
0
9.5
dB
Diff Gain
FB
Frequency Boost at FC
FB = 20 log [1.884(VBP-0.1)
VBP cO.1>O
NRG+1]
FBA
Frequency Boost Accuracy FB = max
-1
+1
dB
TGD
Group Delay Variation
0.3 FC to FC = 13.5 MHz
FB = Oto max
-2
+2
%
VOO
Output Offset Voltage
Variation over entire frequency range
-200
+200
VOF
Filter Output Dynamic Range
THD = 1.5% max
THD = 3.0% max
F = 0.67 FC
1.0
1.25
RINF
Filter Input Resistance
CINF
Filter Input Capacitance
RO
Filter Output Resistance
IFOD
Filter Output Drive Current
VNN
Eout Output Noise Voltage
ON±
VND
. Eout Output Noise Voltage
OD±
mV
Vpp
Vpp
6.0
8.0
kQ
7
pF
70
85
Q
+1
mA
BW = 100 MHz, Rs = 50Q
IFI = 0.7 mA, VBP = 0
2.2
3.0
mVRMS
BW = tOo MHz, Rs = 50Q
IFI = 0.7 mA, VBP = VRG
3.0
4.5
mVRMS ..
BW = 100 MHz, Rs = 50Q
IFI = 0.7 mA, VBP = 0
5.4
6.4
mVRMS
BW = 100 MHz, Rs = 50Q,
1Ft = 0.7 mA, VBP= VRG
9.6
10.6
mVRMS
4.0
10= 0.5 mA
-1
4-82
SSI32P3040
Pulse Detector with
Programmable Filter
DATA COMPARATOR
The input signals are AC coupled to DP and ON.
RINDC Differential Input Resistnace
14
5
pF
0.42
0.49
VN
CINOC Differential Input Capacitance
ATH
Threshold Voltage Gain, Kth
0.3 < VTH-VRC < 0.75
kQ
7
VIAMIN Minimum Threshold Voltage
VTH-VRC ~ O.11V
.05
V
TPDDC Propagation Delay
To DOUT
10
ns
2.4 kQ from DOUT to GND
0.5
ITH
2
VTH Input Bias Current
DOUTSS DOUT Signal Swing
~
V
CLOCKING
The input signals are AC coupled to CP and CN.
RINCL Differential Input Resistance
7
CINCL Differential Input Capacitance
TDS
D F/F Set Up Time
OP-DN threshold to
CP-CN zero cross
TPP
Pulse Pairing
Vs = 1Vpp, F = 2.5 MHz
TPOCL Propagation Delay to RD
RDPW Output Pulse Width
Measured at 1.4V level
2.4 kQ from COUT to GND
4-83
kQ
5
pF
ns
0
14
Vs = 20 mVpp sq wave
COUTS Signal Swing
14
10
0.5
1
ns
20
ns
27
ns
V
II
SSI32P3040
Pulse Detector with
Programmable Filter
THERMAL CHARACTERISTICS:
PACKAGE PIN DESIGNATIONS
(Top View)
VTH
INVBP
23
2
LEVEL
32-Lead TQFP
124°CIW
36-Lead SOM
75°Cm
ala
VRG
VOA-
36
VIM
35
VIA-
VOM
34
33
32
BYP
VRC
31
LEVEL
SERVO
PWR
IFO
3
22
SERVO
RX
4
21
PWR
IN+
INVBP
IFI
5
20
RIW
IFO
30
RX
IFI
AGND
29
ON+
ON-
26
DGND
25
OD-
24
DGND2'
COUT
OD+
DN
23
22
DP
21
VCD2
DOUT
CN
20
RD
CP
19
VCA
AGNO
6
"RQ[j)
OUTN+
7
OGNO
OUTN-
8
17
9
10 11
veo
12 13 14 15 16
32-Lead TQFP
28
27
VTH
RJW
HOLD
VCD
36-Lead SOM
CAUTION: Use handling procedures necessary
for a static sensitive component
ORDERING INFORMATION
PART DESCRIPTION
SSI32P3040
32-Lead Thin Quad Flatpack
36-Lead Small Outline
ORDER NO.
32P3040-CGT
32P3040-CM
PKG.MARK
32P3040-CGT
32P3040-CM
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use, No license is granted under any patents, patent rights or trademarks of Silicon Systems, Silicon Systems
reserves the right to make changes in specifications at any time without notice, Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders,
Silicon Systems, Inc" 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
0194 - rev,
4-84
©1993 Silicon Systems, Inc,
Patents Pending
SSI32P3041
Pulse Detector with
Programmable Filter
December 1993
FEATURES
DESCRIPTION
•
The SSI 32P3041 is a bipolar integrated circuit that
provides all data processing necessary for detection
and qualification of encoded read signals. The circuit
will handle a data rate of 32 Mbitls.
In read mode the SSI 32P3041 provides amplification
and qualification of head preamplifier outputs. Pulse
qualification is accomplished using level qualification
of differentiated input zero crossings. An AGe amplifier
is used to compensate for variations in head preamp
output levels, presenting a constant input level to the
pulse qualification circuitry. The AGe loop can be
disabled so that a constant gain can be used for
embedded servo decoding or other processing needs.
•
Fast attack/decay modes for rapid AGC recovery
•
Dual rate charge pump for fast transient recovery charge pump currents track programmable
channel bandwidth
•
Low drift AGC hold, fast AGC recovery, and low
AGC input impedance control signals. Circuitry
supports programmable gain non-AGC operation
•
Temperature compensated, exponential control AGC
•
•
Write to read transient recovery is enhanced by providing AGe input impedance switching and a selectable
Fast Recovery mode that provides a higher decay
current.
Additionally, the SSI 32P3041 contains an integrated
programmable electroniC filter with cutoff frequencies
between 2.5 and 13 MHz. High frequency boost (for
pulse slimming) of up to 9.5 dB is also provided. The SSI
32P3041 requires only a +5V power supply and is
available in 36-lead SOM and 32-lead TQFP packages.
Compatible with 32 Mbitls data rate operation
Precision wide bandwidth ful/wave rectifier
Supports programmable pulse slimming equalization and programmable channel filter and
differentiatorwith no external filter components
•
±2% Filter group delay variation from 0.3 FC
toFC
•
•
Servo burst output available
•
Differential hysteresis qualifier comparator to
ease clock channel timing
Accurate feed forward or fixed threshold set
BLOCK DIAGRAM
1293 - rev.
4-85
SSI32P3041
Pulse ,Detector with
Pr'ogrammable Filter
goes low. In applications where AGC action is not
desired, the BYP voltage can be set by a resistor divider
network connected from VCC to VRC.1f a
programmable gain is desired, the resistor network
cOl\ld be driven by a current DAC. The precision
fullwave rectifier produces an accurate Level and Servo
output signal.· These outputs are referenced to the
reference voltage VRC. SERVO and LEVEL are
buffered open emitter outputs with 100 ohm series
current limiting resistors. These outputs could be further
filtered with external capacitors.
FEATURES {continued)
•
•
•
•
•
1 ns max pulse pairing with sine wave input
.s mW low power idle mode
TTL read data output
+5V only operation
36-pin SaM and.32-pin TQFP.packages
FUNCTIONAL DESCRIPilON
LEVEL has an internal 50 IJA discharge current source.
An optional Servo output capacitor discharge circuit can
be included. An external resistor connected to the RX
pin sets the electronic filter reference current which is
the source from pin IFO. If a programmable frequency
response is deSired, a portion of the current from IFO,
which is proportional to absolute temperature, must be
injected into pin IF!. This could be accomplished by a
current DAC. Some frequency response programming
may be accomplished by connecting IFO to IFI and
switching different resistors to pin RX. Frequency boOst'
is accomplished by varying the voltage at VBP. VBP has
a nominal 100 mV built-in offset so that the circuit has 0
dB boost for VBP below 100 mV. The voltage at VBP
should be proportional to the reference voltage at pin
VRG.
The SS132P3041 Pulse Detector is designed to support
a 32 MbiVs data rate. The signal processing circuits
include a wide band variable gain amplifier, a
programmable electronic filter, differentiator and pulse
slimming equalizer, a precision wide bandwidth
fullwave rectifier, and a dual ratElcharge pump. A fully
differential filter, differentiator, equalizer, and fullwave
rectifier are provided to minimize extemal nois.e pick-up.
To optimize recovery for constant density recording, the
AGC .charge pump current tracks the programmable
filter current IFI. The differentiator zero .tracks the
programmable filter cuto.ff frequency. Thus ir:J constant
density recording applications, an approximately
constant differentiated signal amplitude is maintained.
The desired filter response and equalization are easily
programmed with theSSI 32D4661, Time Base
.. Gener~tor DACs. A dual rate attack charge pump and a
Fast Decay mode are included for fast transient
recovery. At maximum IFI current, the oormal AGe
attack current is 0.28 mA. When the signal exceeds
125% of the nominal signal level, the attack current is
increased by a factor of 5. The nominal decay current at
max IFI is .s.61JA. The decay current is increased 20
times when in the fast decay mode. In this mode,
transients that produce low gain will recover more
rapidly with the fast decay current, while transients that
produce high gain will put the circuit in the fast attack
recovery mode. The decay' modes are' automatically
controlled within the device. When RIW is low, theAGC
is in its hold mode and its input impedance is switched
low. When RlW is switched high, the AGC remains in the
hold and low input impedance state for 2.31.1$ and then
switches to the fast decay mode for 0.7 JlS. The AGC
amplifier input impedance is reduced to allow quick
recovery of the AGC amplifier input AC coupling
capacitors. When the HOLD input is low, the AGC action
is stopped and the AGC" amplifier gain is set by the
voltage at the BYP pin. In most applications, the BYP pin
voltage is stored on an external capacitor when HOLD
A differential comparator with floating hysteresis
threshold allows differential signal qualification for noise
rejection. An accurate feed forward qualification level is
generated by comparing the difference between LEVEL
and VRC. VRC is referenced to VCA. Thus with the VTH
resistor network connected from VCA to VRC, an
accurate fixed threshold can be established. The
threshold is clamped to a minimum value of 50 mV. Thus
a qualified signal must exceed this minimum level even
when the VTH-VRC voltage is zero. A qualified signal
zero crossing triggers the output one shot. The one shot
period is set intemally. Low level differential outputs are
provided for high speed operation and to minimize noise
generation.
4-86
SSI32P3041
Pulse Detector with
Programmable Filter
3.32507
5'+ 2.759395 +3.32507
+2.94933
5'+ 3.225975 + 2.94933
INPUT
4.20534
5'+ 1.820815+ 4.20534
Transler function normalized for W =21tfc = 1
IV< and AD are adjusted for gain of 2 at f = 0.S7Ic.
Frequency scaling 5. S'21tfc
-K5'
5'+ 3.225975 + 2.94933
FIGURE 1: Bessel Filter Transfer Function
.
BOOST (dB)
K = 2.94933 (10-20-
•
1)
TABLE 1: Typical Change inf - 3 dB Point with Boost
Boost (dB)
Galn@fc (dB)
Gain@peak (dB)
0
-3
0.00
no peak
1.00
0
1
-2
0.00
no peak
1.20
0.36
2
-1
0.00
no peak
1.47
0.76
3
0
0.15
0.62
1.74
1.22
4
1
1.00
1.08
1.96
1.73
fPeaklfc
f-3dB/fc
K
5
2
2.12
1.24
2.13
2.30
6
3
3.35
1.24
2.28
2.94
7
4
4.56
1.39
2.42
3.65
8
5
5.82
1.39
2.54
4.46
5.36
9
6
7.04
1.39
2.66
10
7
8.24
1.39
2.77
6.38
11
8
9.41
1.39
2.88
7.52
12
9
10.55
1.39
2.98
8.79
13
10
11.70
1.55
3.08
10.22
Notes: 1. Ic is the original programmed cutoff frequency with no boost.
2. I - 3 dB is the new -3 dB value with boost implemented.
3. Ipeak is the frequency where the magnitude peaks with boost implemented.
e.g., Ic = 13 MHz when boost = 0 dB
if boost is programmed to 5 dB, then 1- 3 dB = 27.69 MHz
Ipeak= 16.12 MHz
4-87
II
551' 32P3041
Pulsepetector with
Programmable Filter
PIN DESCRIPTION
INPUT PINS
NAME
TYPE
VIA+, VIAIN+,INDP,DN
CP,CN
I
I
I
I
VTH
PWR
I
I
I
HOLD
I
RlW
OUTPUT PINS
VOM, VOAON+,ON00+,00DOUT
DESCRIPTION
AGC Amplifier input pins.
Equalizerlfilter input pins.
Data inputs to data comparators and fullwave rectifier.
Differentiated data inputs to the clock comparator.
Threshold level setting input for the data comparators.
TTL compatible input when high puts the charge pump in the normal mode.
TTL compatible input when high puts the circuit in its normal operating mode.
TTL compatible input when low disables the AGC action by turning off the
charge pump ..
:
AGC amplijier output pins.
Equalizerlfilter normal output pins.
Equalizerlfilter differentiated output pins.
Test point for monitoring the data F/F D-input. Usage requires an external
2.4 kil resistor from DOUTto GND. (Not available in 32-pin TOFP package.)
Test pOints for monitoring the data F/F clock inputs. Usage requires an
external 2.4 kQ resistor from COUT to GND.
(Not available in 32-pin TOFP package.)
TTL compatible read data output pins.
Open NPN emitter outputthat provides a fullwave rectified signalforthe VTH
input. Thesignal is referenced to VRC.
Open NPN emitteroutputthat provides a fullwave rectified servo signal. The
signal is referenced to VRC.
0
0
0
0
COUT
0
RD
LEVEL
0
SERVO
0
ANALOG PINS
VRC
-
VRG
-
VBP
-
0
..
RX
/
IFO
Reference voltage pin for SERVO and LEVEl. VRC is referenced to VCA.
Reference voltage pin for the. programmable filter. VRGis referenced to
ground.
The equalizer high frequency troost is set by an external voltage applied to
this pin. VBP must be pr.oportional to. VRG. Programmable boost is
implemented by using a DAC that usesVRG as its reference. A fixed amount
of boc;>st can be set by an external resistor divide network connected from
VBP to VRG and GND.
Pin to set filter reference current: External resistor Rx from this pin to ground
sets the filter reference current IFO.
Reference current output pin. The reference current is normally supplied
as the reference current to a current DAC which generates the programmable input current for the IFI pin.
4-88
SSI32P3041
Pulse Detector with
Programmable Filter
PIN DESCRIPTION
(continued)
ANALOG PINS (continued)
NAME
TYPE
DESCRIPTION
IFI
Programmable filter input current pin. The filter cutoff frequency is proportional
to the current into this pin. The current must be proportional to the reference
current out of IFO. A fixed filter cutoff frequency is generated by connecting
IFO to IFI and selecting Rx to set the desired frequency.
BYP
The AGC integrating capacitor CA is connected between BYP and VCA.
VCA, VCD,VCD2
Analog and Digital +5 volts.
AGND, DGND,
DGND2
Analog and Digital grounds.
II
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, 4.5V0.9 Final Value
BYP:,>, 1000 pF, IFI = max
34
44
J1S
TGA
Gain Attack Time
VIM = 120 mV to 240 mV
VOM <1.1 Final Value
BYP:,>, 1000 pF, IFI = max
1.5
2
J1S
4-90
551 32P3041
Pulse Detector with
Programmable Filter
EQUALIZER/FILTER (continued)
PARAMETER
TLZ
Low Impedance
Mode Time
CONDITIONS
MIN
RlW transitions
from low to high
1.5
NOM
MAX
UNIT
3.0
~
AGCCONTROL
The input signals are AC coupled to OP and ON. Ca = 1000 pF, LEVEL load = 50 ~, SERVO load = 100 ~.
PARAMETER
CONDITIONS
MIN
VOl
OP-ON Signal Input Range
ALO
Level (Servo) Output Gain
OP-ON = 0.25 to 0.5 VOC
LG = (VLEVEL - VAc)/2 (OP-ON)
Level (Servo) Output Bancmidth
1 dB
Level Offset VoHage
Output-VRC, IL = 50
UNIT
1.4
Vpp
0.81
VN
MHz
~
VSO
Servo Offset Voltage
Output - VRC, IL = 100 ~
ZLS
Level (Servo) Output Impedance
IL=
10
Discharge Current
10F
Fast Discharge Current
ICH
Charge Pump Attack Current
Charge Pump Fast Attack
Current
IBYP Pin Leakage Current
VRC
Reference Voltage
IVRC Output Drive
VRG Reference
IVRG Source Current
VAGC Pin VoHage
0.73
MAX
15
BWL
VLO
ICHF
NOM
100~
200
30
mV
30
mV
300
il
0.008 x
IFI
rnA
2.3 to 3.0 !lS after R/W goes
high
20 x ID
rnA
50x 10
rnA
OP-ON = 1.35 Vpp
5x ICH
rnA
HOLD = low, VBYP = VCC -1.5V
-0.1
VCC-2.S2
-0.75
2.15
1
0.1
VCC-2.1S
0.75
2.5
VRC+1.0
~
V
rnA
V
rnA
V
EaUALlZER/FILTER The input signals are AC coupled to IN+ and IN-
Ic
VAX
FiHer Cutoff Frequency
PTAT Reference Current
Set Output VoHage
IFOR
PTAT Reference Current
Output Current Range
Ic = 19.14(IFIIIFO)(1/Rx)
TA = 25°C
lAX = 0 - 0.7 rnA
Rx> 1.21 kil
TA = 25°C
1.21 kQ < Rx < 7.73 kQ
IFO = VAX/Rx
4-91
2.5
13.5
MHz
mV
0.7
rnA
850
0.11
I
SSI32P3041
Pulse Detector with
Programma'ble, Filter
EQUALIZER/FILTER (continued)
CONDITIONS
MIN
MAX
UNIT
IFIR
PTAT Programming,
Current Range
TA = 25°C, VRX = 850 mV
0.11
0.7
mA
VBPR
Input Voltage Range
..
0
VRG
V
IBP
Input Bias Current
3
pA
FCA
Filter FC AccuraCy
FC = 5 to 13.5 MHz
-10
+10
%
AO
[(ON±)]I[(1N±)) .
Normal Gain
F = 0.67 FC
1.4
2.2
VN
AD
[(OD±))I[(IN±))
Diff Gain
F = 0.67 FC
1.0AO
1.3AO
VN
FB
Frequency Boost at FC
FB = 20 log [1.884(VBP-0.1)
VBP -0.1>0
NRG+1]
0
9.5
dB
FBA
Frequency Boost Accuracy FB = max
~1
+1
dB
TGD
Group Delay Variation
-2
+.2 .'.
%
VOO
Output Offset Voltage
Variation over entire frequency range
-200
VOF
Filter Output Dynamic Range
THD = 1.5% max
THD = 3.0% max
F = 0.67 FC
1.0
1.25
P.,RAMETER.
RINF
Filter Input Resistance
CINF
Filter Input Capacitance
"
0.3 FC to FC = 13.5 MHz
FB = Oto max
4.0
RO
Filter Output Resistance
IFOD
Filter Output Drive Current
VNN
Eout Output Noise Voltage . BW = 100 MHz, Rs = 50n
ON±
.' IFI = 0.7 rnA, VBP = 0
VND
Eout Output Noise Voltage
OD±
...
10 =0.5 mA
NOM
+200
mV
Vpp
Vpp
6.0
70
8.0
kn
7
pF
85
n
+1
mA
2.2
3.0
mVRMS
BW = 100 MHz, Rs = 50n
IFI = 0.7 mA, VBP = VRG
3.0
4.5
mVRMS
BW = 100 MHz, Rs = 50n
IFI = 0.7 mA, V8P = 0
5.4
6.4
mVRMS
BW = 100 MHz, Rs = 50n
1Ft = 0.7 mA, VBP = VRG
9.6
10.6
mVRMS
-1
4-92
SSI32P3041
Pulse Detector with
Programmable Filter
DATA COMPARATOR
The input signals are AC coupled to DP and DN.
RINDC Differential Input Resistnace
7
14
5
pF
0.42
0.49
VIV
CINDC Differential Input Capacitance
ATH
Threshold Voltage Gain, Kth
0.3 < VTH-VRC < 0.75
~
VIAMIN Minimum Threshold Voltage
VTH-VRC
.05
V
TPDDC Propagation Delay
To DOUT
10
ns
2.4 kO from DOUT to GND
0.5
ITH
0.11V
kO
VTH Input Bias Current
DOUTSS DOUT Signal Swing
2
IJA
V
CLOCKING
The input signals are AC coupled to CP and CN.
RINCL Differential Input Resistance
7
CINCL Differential Input Capacitance
TOS
D F/F Set Up Time
DP-DN threshold to
CP-CN zero cross
TPP
Pulse Pairing
Vs
TPDCL Propagation Delay to RD
= 1Vpp, F = 2.5 MHz
Vs = 20 mVpp sq wave
RDPW Output Pulse Width
Measured at 1.4V level
COUTS Signal Swing
2.4 kO from COUT to GND
4-93
14
kO
5
pF
0
ns
14
10
0.5
1
ns
20
ns
20
ns
V
II
SSI32P3041
Pulse Detector with
Programmable Filter
THERMAL CHARACTERISTICS: Ilja
PACKAGE PIN DESIGNATIONS
(Top View)
,+
+
~
g >~
!:f> ~+ ~
11.
>m
124°CIW
36-Lead SOM
75° CIW
U
g:
VRG
VOAVOA+
32 31 30 29 28 27 26 25
INVBP
32-Lead TQFP
2
24
VTH
23
LEVEL
IN+
INVBP
IFO
3
22
SERVO
RX
4
~
PWR
IFI,
5
20
RIW
AGNO
6
19
RQ[O
AGNO
ON+
ON00-
7
18
OGNO
OUTN-
8
17
VCO
9
10 11 12 13 14 15 16
6
7
RX
8
9
10
11
36
35
VIA+
VIA- .
34
33
BYP
VRC
32
31
LEVEL
30
29
SERVO
PWR
VTH
28
RNJ
27
FIO[[j'
26
25
09NP
OGN02
COUT
VCO
12
13
14
24
23
ON
OP
15
22
16
21
CN
CP
17
1m
18
VCA
00+
32-Lead TQFP
3
4
5
IFO
1101
OUTN+
1
2
VC02
OOUT
36-LeadSOM
CAUTION: Use handling procedures necessary
lor a static sensitive component
ORDERING INFORMATION
PART DESCRIPTION
SSI32P3041
32-Lead Thin Quad Flatpack
36-Lead Small Outline
ORDER NO.
PKG.MARK
32P3041-CGT
32P3041-CGT
32P3041-CM
32P3041-CM
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use, No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1293 - rev.
4-94
©1993 Silicon Systems, Inc.
Patents Pending
Section
5
PROGRAMMABLE
ELECTRONIC FILTERS
5
5-0
SSI32F8001
Low-Power Programmable
Electronic Filter
October 1993
FEATURES
DESCRIPTION
Ideal for multi-ntte systems applications
The 551 32F8001 Programmable Electronic Filter
provides an electronically controlled low-pass filter
with a separate differentiated low-pass output. A
seven-pole, low-pass filter is provided along with a
single-pole, single-zero differentiator.. Both outputs
have matched delays. The delay matching is
unaffected by any amount of programmed equalization
or bandwidth. This programability combined with low
group delay variation make the 551 32F8001 ideal for
use in constant density recording applications. Pulse
slimming equalization is accomplished by a two-pole,
low-pass with a two-pole, high-pass feed forward
section to provide complimentary real axis zeros. A
variable attenuator is used to program the zero
locations.
Progntmmable filter cutoff frequency
to 27 MHz, 32F8001)
(S/2nfe)
Eq for fe = 27 MHz. S = S / [(2n)(27 x 106 )]
FIGURE 5: 32F8001 Normalized Block Diagram
TABLE 1: 32F8001 Frequency Boost Calculations, K = 1.31703 (10 BOOST (dB)/20 - 1)
Assuming 13 dB boost for
VBP = VPTAT
VBP
VPTAT
( 10 (FBI20) -1
3.73
I
Boost
K
VBP
VPTAT
1 dB
2dB
3dB
4dB
5 dB
0.16
0.34
0.54
0.77
1.03
0.033
0.069
0.110
0.157
0.209
or,
boost in dB=20109 [ 3.73
(V~~:T )+1]
i
I
Boost
K
VBP
VPTAT
6dB
7dB
8dB
9 dB
10 dB
11 dB
12 dB
13 dB
1.31
1.63
1.99
2.40
2.85
3.36
3.43
4.57
0.267
0.332
0.405
0.488
0.580
0.683
0.799
0.929
VBP
VPTAT
Boost
VBP
-VPTAT
0.1
0.2
0.3
0.4
0.5
2.753 dB
4.841 dB
6.523 dB
7.391 dB
9.142 dB
0.6
0.7
0.8
0.9
1.0
5-10
Boost
10.206
11.153
12.006
12.784
13.5
dB
dB
dB
dB
dB
SSI32F8001
Low-Power Programmable
Electronic Filter
TABLE 2: Calculations
Typical change in i-3 dB point with boost
Boost (dB)
Galn@fc (dB)
Gain@ peak (dB)
fpeaklfc
f-3dB/fe
0
-3
0.00
no peak
1.00
1
-2
0.00
no peak
1.21
2
-1
0.00
no peak
1.51
3
0
0.15
0.70
1.80
4
1
0.99
1.05
2.04
5
2
2.15
1.23
2.20
6
3
3.41
1.33
2.33
7
4
4.68
1.38
2.43
8
5
5.94
1.43
2.51
9
6
7.18
1.46
2.59
10
7
8.40
1.48
2.66
11
8
9.59
1.51
2.73
12
9
10.77
1.51
2.80
13
10
11.92
1.53
2.87
11
13.06
1.53
2.93
14
Notes:
1. ic is the original programmed cutoff frequency with no boost
2. i-3 dB is the new -3 dB value with boost implemented
3. ipeak is the frequency where the amplitude reaches its maximum
value with boost implemented
i.e., ic = 9 MHz when boost
= 0 dB
if boost is programmed to 5 dB then
i-3 dB = 19.8 MHz
ipeak = 11.07 MHz
5-11
II
SSI32F8001
Low-Power Programmable
Electronic Filter
PACKAGE PIN DESIGNATIONS
(Top View)
THERMAL CHARACTERISTICS: 9ja
i6-lead SON (150 mil)
N/C
16
VO_DIFF+
VO_NORM-
2
15
VO_DIFF-
VO_NORM+
3
14
PWRON
VCC
4
13
VPTAT
VIN-
5
12
N/C
VIN+
6
11
IFP
VBP
7
10
VHP
FBST
8
9
GND
16-lead SOL (300 mil)
100°CIW
16-Lead SON, SOL
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
I
ORDER NO.
I
32F8001-CL
I
PKG.MARK
SSI32F8001
i6-Lead SOL
i6-Lead SON
I
I
32F8001-CN
I
32F8001-CL
32F8001-CN
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1992 Silicon Systems, Inc.
5-12
Protected by the following patents: (5,063,309) (710,512) (823,067)
1093 - rev.
SSI32FS002/S003
Low-Power Programmable
Electronic Filter
'§ 'i" 11" 'E' ifa1m,
December 1993
FEATURES
DESCRIPTION
Ideal for mUlti-rate systems applications
Programmable filter cutoff frequency (/c = 6
to 18 MHz, 32F8002; Ic =4 to 13 MHz, 32F8003)
Programmable pulse slimming equalization
(0 to 13.5 dB boost atthe filter cutofffrequency)
The SSI 32F8002l8003 Programmable Electronic
Filters provide an electronically controlled low-pass
filter with a separate differentiated low-pass output. A
seven-pole, low-pass filter is provided along with a
single-pole, single-zero differentiator. Both outputs
have matched delays. The delay matching is
unaffected by any amount of programmed equalization
or bandwidth. This program ability combined with low
group delay variation make the SSI 32F8002/8003
idealfor use in constant density recording applications.
Pulse slimming equalization is accomplished by a twopole, low-pass with a two-pole, high-pass feed
forward section to provide complimentary real axis
zeros. A variable attenuator is used to program the
zero locations.
Matched normal and differentiated low-pass
outputs
Differential filter inputs and outputs
±10% cutoff frequency accuracy
±2% maximum group delay variation from
0.2 Icto Ic
Total harmonic distortion less than 1%
No external filter components required
+5V only operation
16-lead SON and SOL package
Pin compatible with SSI 32F8011
The SSI 32F8002l8003 programmable equalization
and bandwidth characteristics can be controlled by
external DACs. Fixed characteristics are easily
accomplished with three external resistors, in addition
equalization can be switched in or out by a logic signal.
The SSI32F800218003 require only a +5V supply and
is available in 16-lead SON and SOL packages.
PIN DIAGRAM
BLOCK DIAGRAM
VIN+
n..~~r;:::;';.::h ,J~~~~A..;...f~;-;:::l¥#6 VO_NORM+
VIN·
VO_NORM·
N/c
15
VO_DIFF+
VO_DIFF-
14
12
VBPO+++++++~~++~··
IFP rl+++"+9~:::::""l
p-~-,..4
VPTAT
11
10
••
VFP g---4~~~J
PWRON
FBST~~~"---7---=~~~'
16-Lead SOL, SON
CAUTION: Use handling procedures necessary
lor a static sensitive component.
1293 - rev.
5-13
II
SSI 32F8002/8003
Low-Power Programmable
Electronic Filter
FUNCTIONAL DESCRIPTION
If the SSI 32F8002/8003 cutoff frequency is set using
voltage VPTATto bias upa resistor tied to pin VFP, the
cutoff frequency is related to the resistor value by the
following formulas.
The SSI 32F8002/8003 are high performance
programmable electronic filter. They feature a 7-pole
0.05° equiripple linear phase filter with matched normal
and differentiated outputs.
fc (ideal, in MHz)
32F8002 = 30.0· IFP = 30.0 • 1.8/(3· Rx)
CUTOFF FREQUENCY PROGRAMMING
32F8003 = 21.67· IFP = 21.67 • 1.8/(3· Rx)
The SSI 32F8001 programmable electronic filter can
be set to a filter cutoff frequency from 9 to 27 MHz with
no boost.
Rx in kQ
If pin VFP is used to program cutoff frequency, pin IFP
should be left open.
Cutoff frequency programming can be established
using either a current source fed into pin IFP whose
output current is proportional to the SSI 32F8001
output reference voltage VPTAT, or by means of an
external resistor tied from the output voltage reference
pin VPTATto pin VFP. The former method is optimized
using the SSI 32D4661 Time Base Generator, since
the current source into pin IFP is available at the DAC
F output olthe SS132D4661. Furthermore, the voltage
reference input is supplied to pin VR3 of the
SSI 3204661 by the reference voltage from the VPTAT
pin of the SSI 32F8001. This reference voltage is
internally generated by a band-gap circuit in conjunction
with a temperature varying reference to create a voltage
which is proportional to absolute temperature.
MAGNITUDE EQUALIZATION PROGRAMMING
The magnitude equalization, measured in dB, is the
amount of high frequency peaking althe cutoff frequency
relative to the original-3 dB point. For example, when
12 dB boost is applied, the magnitude response peaks
up 9 dB above the DC gain.
The amplitude of the input signal at frequencies near
the cutoff frequency can be increased using this feature.
Applying an external voltage to pin VBP which is
proportional to reference output voltage VPTAT
(provided by the VPTAT pin) will set the amount of
boost. A fixed amount of boost can be set by an
external resistor divider network connected from pin
VBPtopinsVPTATandGND. No boost is applied if pin
FBST, frequency boost enable, is at a low logic level.
The VPTAT voltage will compensate for internal
temperature variation of the fc and boost circuits.
The amount of boost FB at the cutoff frequency Fc is
related to the voltage VBP by the formula
The cutoff frequency, determined by the -3dB point
relative to a very low frequency value (< 10 kHz), is
related to the current IVFP injected into pin IFP by the
following formulas.
FB (ideal, in dB) = 20 loglO[3.73(VBPIVPTAT)+1],
where 0 < VBP < VPTAT.
fC (ideal, in MHz)
32F8002
=
30.0 ·IFP
32F8003
=
21.67 ·/FP = 21.67· /VFP ·1.8IVPTAT
POWER ON 1 OFF
= 30.0 ·IVFP ·1.8IVPTAT
The SSI 32F8002/8003 support a Power Down mode
for minimal Idle mode power dissipation. When
PWRON is pulled up to TTL logic high, the device is
in Normal Operation mode. When PWRON is pulled
down to TTL logic low, or left open, the device is in the
Power Down mode.
where IFP and /VFP are in mA, VPTAT is in volts, Ta
= 25°C, 0.2 mA:s; IFP:s; 0.6 mA for F8002, and 0.185:s;
IFP:s; 0.6 mA for F8003.
If a current source is used to inject current into pin IFP,
pin VFP should be left open.
5-14
SSI32F8002/8003
Low-Power Programmable
Electronic Filter
PIN DESCRIPTION
NAME
TYPE
DESCRIPTION
VIN+. VIN-
I
Differential Signal Inputs. The input signals must be AC coupled to these pins.
VO_NORM+.
VO_NORM-
0
Differential Normal Outputs. The output signals must be AC coupled.
VO_DIFF+.
VO_DIFF-
0
Differential Differentiated Outputs. For minimum time skew. these outputs
should be AC coupled.
IFP
I
Frequency Program Input. The filter cutoff frequency fC. is set by an external
current IFP. injected into this pin. IFP must be proportional to voltage VPTAT.
This current can be set with an external current generator such as a DAC. VFP
should be left open when using this pin.
VFP
I
Frequency Program Input. The filter cutoff frequency can be set by programming a current through a resistor from VPTAT to this pin. IFP should be left
open when using this pin.
VBP
I
Frequency Boost Program Input. The high frequency boost is set by an
external voltage applied to this pin. VBP must be proportional to voltage
VPTAT. A fixed amount of boost can be set by an external resistor divider
network connected from VBP to VPTAT and GND. No boost is applied if the
FBST pin is grounded. or at logic low.
FBST
I
Frequency Boost. A high logic level or open enables the frequency boost
circuitry. A low input disables this function.
PWRON
I
Power On. A high logic level enables the Chip. A low level or open pin puts the
chip in a low power state.
VPTAT
0
PTAT Reference Voltage. This pin outputs a reference voltage which is
proportional to absolute temperature (PTAT). VBP. VFP or IFP must be
referenced to this pin for proper operation.
VCC
0
+5 Volt Supply.
GND
I
Ground
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
.
oJperatlon above maximum ratings may damage t he d eVlce.
PARAMETER
RATINGS
Storage Temperature
-65°C to + 150°C
Junction Operating Temperature. Tj
+130°C
Supply Voltage. VCC
-O.5Vto 7V
Voltage Applied to Inputs
-O.5Vto VCC
5-15
II
SSI32FSOO2lS003
Low-Power Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS (continued)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply voltage,
RATINGS
vcc
4.50V < VCC < 5.50V
Ambient Temperature
O°C < Ta < 70°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified recommended operating conditions apply.
Power Supply Characteristics
PARAMETER
ICC
Power Supply Current
ICC
Power Dissipation
MIN
CONDITIONS
Power Supply Current
PD
PWRON:<;O.BV
PWRON~2.0V
NOM
MAX
UNIT
0.1
0.5
rnA
46
60
rnA
= 5.0V
PWRON ~ 2.0V, VCC =55V
230
300
mW
275
330
mW
PWRON:<;O.BV
0.5
2.5
mW
O.B
V
PWRON
~
2.0V, VCC
DC Characteristics
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
High Level Input Current
IIH
VIH = 2.7V
Low Level Input Current
ilL
VIL = O.4V
-1.5
32FB002 fC = 30 MHz (IVFP)
rnA
6.0
1B.0
MHz
32FB003
4
13
MHz
fc = max.
-10
+10
F = 0.67 fc, FB = 0 dB
O.B
1.2
V/v
O.BAO
1.2AO
V/v
15.0
dB
14.5
dB
+1.5
dB
2.0
TTL input
V
20
J.!A
rnA
Filter Characteristics
Filter Cutoff Frequency
"fc
*(f -3dB)
fc = 21.67 MHz (IVFP)
rnA
Filter fc Accuracy
FCA
VO_NORM Diff Gain
AO
VO_DIFF Diff Gain
AD
F = 0.67 fc, FB = 0 dB
Frequency Boost at fc
FB
VBP = VPTAT
Frequency Boost Accuracy FBA
VBP/vPTAT = 1.0
5-16
fC = max.
12.0
13.5
fc = min.
11.5
13.0
!c=max.
-1.5
%
SSI32F8002/8003
Low-Power Programmable
Electronic filter
FILTER CHARACTERISTICS (continued)
PARAMETER
CONDITIONS
Group Delay Variation
TGDO
Without Boost (continued)
fC = max,
MIN
VBP =0
VPTAT
F = 0.2 fc to fC
8002
8003
fc= min,
8002
F = 0.2 fc to fc
8003
fc = 6 - 18 MHz,
fC = 4 - 13 MHz,
8002
8003
VBP
VPTAT=O
F = 0.2 fc to fc,
NOM
MAX
UNIT
+750
ps
-1
+1
ns
-2.25
+2.25
ns
-3
+3
ns
-2
+2
%
-3
+3
%
-750
+750
ps
-1
+1
ns
-2.25
+2.25
ns
-750
VBP
VPTAT=O
fC = 6 - 18 MHz,
fC = 4 - 13 MHz,
8002
8003
VBP =0
VPTAT
fc = max, VBP = VPTAT 8002
F = fcto 1.75 fc
Group Delay Variation
TGDB
With Boost
F = 0.2 fc to fc
8003
fe = min, VBP = VPTAT 8002
F = 0.2 to fe
8003
-3
+3
ns
fC = 6-18 MHz
8002
fC = 4 -13 MHz
8003
F = 0.2 fe TO fe, VBP = VPTAT
-2
+2
%
fe = 6 - 18 MHz,
8002
fe = 4 - 13 MHz,
8003
F '" fcto 1.75 fe, VBP '" VPTAT
-3
+3
%
THO =1% max, F =0.67 fe, VBP =OV
(1000 pF across Rx)
1
Vpp
THO =1.5% max, F=0.67 fe, VBP =OV,
Normal output (1000 pF across Rx)
1.5
Vpp
Filter Input Dynamic Range VIF
THO =2.0% max, F=0.S7 fe, VBP =OV,
Differentiated output
(1000 pF across Rx)
1.5
Vpp
Filter Output Dynamic RangeVOF
THO = 1% max, F = 0.67 fC
RLOAD ~ 1k.Q (1 000 pF across Rx)
1
Vpp
Filter Input Dynamic Range VIF
Filter Diff Input Resistance RIN
Filter Input Capacitance
Output Noise Voltage
Differentiated Output
3
CIN
EOUT
kn
4.3
7
pF
BW =100 MHz, Rs =50Q
8002
3.3
mVRms
fc = max, VBP = OV
8003
3
mVRms
5-17
I
551 32F8002/8003
Low-Power Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS (continued)
FILTER CONTROL CHARACTERISTICS
PARAMETER
MIN
CONDITIONS
Output Noise Voltage
EOUT
Normal Output
Output Noise Voltage
EOUT
EOUT
Normal Output
Filter Output Sink Current
8003
1.B
mVRms
BW =100 MHz, Rs =son
5.0
mVRms
4.3
mVRms
BW =100 MHz, Rs =son
B002
B003
B002
2.5
mVRms
Ie =max, VBP =VPTAT
8003
2.2
mVRms
10-
Reference Voltage
RO
VPTAT
PTAT Voltage Input
VFP
Programming Current
IVFP
VYBP
Voltage at pin IFP
V1FP
Power Up Time
mVRms
1
mA
10+ = 1.0 mA
Tj = 25°C
Ta = 25°C
Range
Programming Voltage
Range
UNIT
Ie =max, VBP =OV
2
Filter Output Source CurrentiO +
Filter Output Resistance
(Single ended)
MAX
B002
Ie =max, VBP =VPTAT
Differentiated Output
Output Noise Voltage
NOM
BW =100 MHz, Rs =son
2
rnA
60
n
1.B
V
213 VPTAT
V
8002
0.2
0.6
mA
B003
0.185
0.6
mA
0
VPTAT
V
2/3 VPTAT
lyFP = 0 mA
V
fc
= min
1.5
/lS
fc
= max
1
/lS
1
/lS
Power Down Time
5-18
SSI 32F8002/8003
Low-Power Programmable
Electron ic Filter
N/C
VO_NORMVO_NORM+
VCC (+5V)
VINVIN+
VBP
FBST
VO_DIFF+
VO_DIFFPWR_ON
N/C
IFP
VFP
GND
R,
RBP1
RBP2
VPTAT = 1.8V (25°C)
VVFP = 2/3 (VPTAT)
IVFP range: 0.2 mA to 0.6 mA@25°C, 32F8002
IVFP range: 0.185 mA to 0.6 mA @25°C, 32F8003
Fixedfrequency programming is accomplished as shown inthe drawing above.
VPTAT 1
In this case IVFP (programming current) is equivalent t o -3-'R
x
i.e.,
fc = 27 MHz then
IVFP = 0.6 mA @25°C
Rx = 1 KQ
Fixed boost programming is also accomplished as shown above. In this case
VVsP is set by a voltage divider, where VVsp is a fraction of VPTAT.
i.e.,
boost = 9 dB then,
VBP/vPTAT = 0.488
RBP2
R
9 dB = 20 log [3.73 (0.488) + 1]
1
(VPTAT
)=0.953
---1
VBP
Cx = 1000 pF - Cx is needed for lower THO at lower fc.
BP1
FIGURE 4: 32F8002/8003 Applications Setup
5-19
I
SSI 32F8002/8003
Low-Power Programmable
Electronic Filter
INPUT
1.31703
2.95139
5.37034
S2+ S 1.68495 + 1.31703
S2+ S 1.54203 + 2.95139
S2+ S 1.14558 + 5.37034
S2+S 1.68495 + 1.31703
Normalized for roc = (21t) fe = 1
AN and AD are adjusted for unity gain (0 dB) at F = 0.67 fe
Denormalize the frequency by substituting S -> (SI21tfe)
Eq for fe = 27 MHz, S = S I [(21t)(27 x 10"))
FIGURE 5: 32F8001 Normalized Block Diagram
TABLE 1: 32F8001 Frequency Boost Calculations, K
Assuming 13 dB boost for
VBP = VPTAT
VBP
VPTAT
( 10 (FB/20)) -1
3.73
Boost
K
VBP
-VPTAT
1 dB
2 dB
3 dB
4dB
5dB
0.16
0.34
0.54
0.77
1.03
0.033
0.069
0.110
0.157
0.209
VBP
-VPTAT
Boost
VBP
-VPTAT
0.1
0.2
0.3
0.4
0.5
2.753 dB
4.841 dB
6.523 dB
7.391 dB
9.142 dB
0.6
0.7
0.8
0.9
1.0
or,
boost in dB:20109 [ 3.73
= 1.31703 (10 BOOST (dB)I20 - 1)
(V~~:T )+1]
5-20
I
I
Boost
K
6dB
7dB
8dB
9dB
10 dB
11 dB
12 dB
13 dB
1.31
1.63
1.99
VBP
-VPTAT
0.267
0.332
2040
00405
00488
2.85
3.36
3.43
4.57
0.580
0.683
0.799
0.929
Boost
10.206
11.153
12.006
12.784
13.5
dB
dB
dB
dB
dB
SSI32F8002/8003
Low-Power Programmable
Electronic Filter
TABLE 2: Calculations
Typical change in 1-3 dB point with boost
Boost (dB)
Gain@/c (dB)
Gain@ peak (dB)
Ipeakl/c
1-3dB/lc
0
1
2
-3
-2
-1
0.00
0.00
0.00
no peak
1.00
1.21
1.51
3
4
5
6
7
8
9
10
11
0
1
2
0.70
1.05
1.23
1.33
1.38
1.43
1.46
1.48
1.51
1.51
1.53
1.80
2.04
2.20
2.33
2.43
2.51
2.59
2.66
2.73
2.80
2.87
1.53
2.93
12
13
8
9
10
0.15
0.99
2.15
3.41
4.68
5.94
7.18
8.40
9.59
10.77
11.92
14
11
13.06
3
4
5
6
7
no peak
no peak
Notes: 1. Ie is the original programmed cutoff frequency with no boost
2.
1-3 dB is the new -3 dB value with boost implemented
3. Ipeak is the frequency where the amplitude reaches its maximum
value with boost implemented
i.e.,
Ic = 9 MHz when boost = 0 dB
if boost is programmed to 5 dB then
1-3 dB = 19.8 MHz
Ipeak = 11.07 MHz
5-21
I
SSI32FS002/S003
Low-Power Programmable
Electronic Filter
PACKAGE PIN DESIGNATIONS
(Top View)
THERMAL CHARACTERISTICS: 6ja
NlC
16
VO_DI FF+
VO_NORM-
2
15
VO_DIFF-
VO_NORM+
3
14
PWRON
VCC
4
13
VPTAT
VIN-
5
12
N/C
VIN+
6
11
IFP
VBP
7
10
VHP
FBST
8
9
GND
16-lead SON (150 mil)
105·cm
16-lead SOL (300 mil)
100·cm
16-Lead SON, SOL
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
SSI32FBOO2
16-Lead SOL
32F8002-CL
32F8002-CL
16-Lead SON
32F8002-CN
32FBOO2-CN
SSI32FBOO3
16-Lead SOL
32F8003-CL
32FBOO3-CL
16-Lead SON
32FBOO3-CN
32FBOO3-CN
Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
5-22
©1993 Silicon Systems, Inc.
Protected by the following patents: (5,063,309) (710,512) (823,067)
1293 - rev.
SSI 32FS011/S012
Programmable
Electronic Filter
December 1993
DESCRIPTION
FEATURES
The SSI 32F8011/8012 Programmable Electronic
Filter provides an electronically controlled low-pass
filter with a separate differentiated low-pass output.
A seven-pole, Bessel-type, low-pass filter is provided
along with a single-pole, single-zero differentiator. Both
outputs have matched delays. The delay matching is
unaffected by any amount of programmed high frequency peaking (boost) or bandwidth. This programmability, combined with low group delay variation makes
the SSI 32F8011/8012 ideal for use in many applications. Double differentiation high frequency boost is
accomplished by a two-pole, low-pass with a twopole, high-pass feed forward section to provide complementary real axis zeros. A variable attenuator is used
to program the zero locations, which controls the
amount of boost.
•
Ideal for:
- constant density recording applications
- cellular telephone applications
- radio
• data acquisition
-LAN
•
Programmable filter cutoff frequency
(SSI 32F8011 Ic = 5 to 13 MHz)
(SS132F8012 Ic = 6 to 15 MHz)
•
Programmable high frequency peaking
(0 to 9.5 dB boost at the filter cutoff frequency)
•
Matched normal and differentiated low-pass
outputs
•
•
Differential filter input and outputs
TheSSI32F8011/8012 programmable boost and bandwidth characteristics can be controlled by external
DACs or DACs provided in the SSI 3204661 Time
Base Generator. Fixed characteristics are easily accomplished with three external resistors, in addition
boost can be switched in or out by a logic signal.
The SSI32F8011/8012 requires only a+5V supply and
is available in 16-pin SON and SOL packages.
±0.75 ns group delay variation from
0.2 Ic to Ic = 13 MHz
•
Total harmonic distortion less than 1%
•
+5V only operation
•
16-lead SON, and SOL packages
BLOCK DIAGRAM
PIN DIAGRAM
VO_NORM+
VO_NORM-
VIN+
VIN-
VO_DIFF+
VO_DIFF-
VBP
VO_DIFF+
VO_NORM-
VO_DIFF-
VO_NORM+
PWRON
VCC1
VR
VIN-
VCC2
VIN+
IFP
VBP
VFP
VR
IFP
VFP
FBST
GND2
PWRON
FBST
1293 - rev.
GND1
5-23
CAUTION: Use handling procedures necessary
for a static sensitive component.
I
SS132F8011/8012
Programmable
Electronic Filter
If the 32F8011/B012 cutoff frequency is set using voltage VR to bias up a resistor tied to pin VFP, the cutoff
frequency is related to the resistor value by the following
formulas.
FUNCTIONAL DESCRIPTION
The SS132F8011/8012, a high performance programmable electronic filter, provides a low pass Bessel-type
seven pole filter with matched normal and differentiated outputs. The device has been optimized for usage
with several Silicon Systems products, including the
SSI 3204661 Time Base Generator, the SSI 32P54x
family of Pulse Detectors, and the SSI 32P4720
Combo chip (Data Separator and Pulse Detector).
SSI32F8011
Fc (ideal, in MHz)
= 16.25·IFP = 16.25·2.2/(3·Rx)
SSI32FB012
Fc (ideal, in MHz) = 18.75·IFP = 1B.75·2.2/(3·Rx)
where Rx is in kn, 0.917
fc = Max fc, VBP = OV
F = 0.2 fc to fc
-0.75
S.5
9.5
+0.75
ns
TGDB Group Delay Variation
With Boost>
fC = Max fc, VBP = VR
F = 0.2 fc to fc
-0.75
+0.75
ns
VIF
Filter Input Dynamic Range
THO = 1% max, F = 0.67 fc
(no boost)
VOF
Filter Output Dynamic Range
THD = 1% max, F = 0.67 fC
RIN
Filter Diff Input Resistance
CIN
Filter Diff Input Capacitance'
1.5
Vpp
Vpp
1.5
3.0
kn
3.S
2.5
7
pF
EOUT Output Noise Voltage>
Differentiated Output
BW = 100 MHz, Rs = 50n,
Ifp = o.s mA, VBP = o.ov
5.5
6.S
mVRms
EOUT Output Noise Voltage>
Normal Output
BW = 100 MHz, Rs = 50n
'fp = o.s mA, VBP = o.ov
2.75
3.6
mVRms
EOUT Output Noise Voltage>
Differentiated Output
BW = 100 MHz, Rs = 50n
Ifp = o.s mA, VBP = VR
6.0
S.1
mVRms
EOUT Output Noise Voltage>
Normal Output
BW = 100 MHz, Rs = 50n
Ifp = o.s mA, VBP = VR
3.25
4.4
mVRms
• Not directly testable in production, design characteristic.
5-26
SSI 32F8011/8012
Programmable
Electronic Filter
ELECTRICAL CHARACTERISTICS (continued)
Filter Characteristics (continued)
PARAMETER
MIN
CONDITIONS
10-
Filter Output Sink Current
10+
Filter Output Source Current
RO
Filter Output Resistance
Single ended
NOM
MAX
UNITS
1.0
rnA
2.0
rnA
Source Current (10+) = 1 rnA
60
Q
MAX
UNITS
2.40
V
2.0
rnA
Filter Control Characteristics
PARAMETER
CONDITIONS
VR
Reference Voltage Output
IVR
Reference Output
Source Current
MIN.
NOM
2.0
I
GND1
VO_DIFF+
VO_NORM-
VO_DIFF-
VO_NORM+
PWR_ON
VCC1 (+5V)
VR
VIN-
VCC2 (+5V)
VIN+
IFP
VBP
R,
VFP
FBST
GND2
Rsp,
FIGURE 1: 32F8011/8012 Applications Setup, i6-Pin SO or DIP
VR = 2.2V
IVfp = 0.33VRlRx
VFP = 0.667 VR
IVfp range: 0.31 rnA to 0.8 rnA
(5 MHz to 13 MHz for SSI 32F8011)
(6 MHz to 15 MHz for SSI 32F8012)
VFP is used when programming current is set with a resistor from VA. When VFP is used I FP must be left
open.
5-27
SS132FS011/S012
Programmable
Electronic Filter
Rx
Four
ToC.... Sync
CACI
To Data Sync
CACM
ToOalaSync
FIGURE 2: Applications Setup, Constant Density Recording
32F8011/f,J012, 32P54X, 3204661
IOF = DACF output current
F = DAC setting: 0-127
IOF = (0.98FoVR)/127Rx
Full scale, F = 127
Rx = (0.98FoVR)112710F
For range of Max fc then IFP = 0.8 rnA
Rx = current reference setting
resistor
Therefore, for Max programming current
range to 0.8 mA:
VR = Voltage Reference = 2.2V
Rx = (0.98)(2.210.8) = 2.7 kO
Please note that in setups such as this where IFP is used for cutoff frequency programming VFP must be left
open.
5-28
SSI32F8011/8012
Programmable
Electronic Filter
49.4.--~--.,---~--.,---~--.,---~--.,---~-~
4B.41---t---t---t---t---t---t---t---t---t----I
47.41---t---t---t---t---t---1---I---1---I----I
fe = 10.4 MHz
a) No Boost
b) Max Boost
e) Ideal Bessel Filter
-
46.4~-tl--;;;;;:::~~==f==t=t=1--.....~-+~~-1
45.4 f-__-__-__+-__-__-__+____-__-+_-_ __- __-__f__-__-__+__-__-__-I---l--~""""-;:--+"'\r---i~b
------ --........
"'" '\
'
44.41----+---I----+---I----+---I----+--'-'-",!...----P~__I
""
"
\.
"-
a
43.41----+---1----+---1----+---1----+---1---'4--__1
"'\
42.41----+---1----+---1----+---1----+---1----+--".--1
\
\,
I
41.41----+---1----+---1----+---1----+---1----+---41'
40.41----+---~--+---~--+---~--+---~--+----l
39.4 '----'---'----'---'----'---'----'---'----'----'
4.0
2.0
B.O
6.0
10.0
12.0
14.0
16.0
1B.O
20.0
Frequency (MHz)
FIGURE 3: 32F8011/8012 Typical Group Delay Variation (Differentiated Output)
b
/f \
/.. f.-'
--
V
/ /t?
/~ ~r;:
\
~e
a
c\\
ce_\ \
1\
\ !\ \
\ \
\
j0;V
\r\
/
I/ 1/1/
./V
\
\
\
0.100
b<:: P\
~Xf
o/y
r
0.100
10
Frequency (MHz)
10
~
Frequency (MHz)
FIGURE 5: 32F8011/8012 Differented Low Pass
Output Response (VO_DIFF)
FIGURE 4: 32F8011/8012 Normal Low Pass
Output Response (VO_NORM)
d) fe = 10 MHz Max Boost
e) fe; 15 MHz No Boost
f) fe; 15 MHz Max Boost
a) fe; 5 MHz No Boost
b) fe; 5 MHz Max Boosl
e) fe; 10 MHz No Boost
5-29
SSI32F8011/8012
Programmable
Electronic Filter
a)
•
fe = 5 MHz (Ref = 80 ns)
Il) fe = 10 MHz (Ref = 45 ns)
e)
1\
\\
fe
= 15 MHz (Ref = 35 ns)
....... ~
\
" \.
l\.
-
c
\
\
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
\
\
\
22.5
25.0
Frequency (MHz)
FIGURE 6: 32F8011/8012 Typical Group Delay Variation
(DIfferentiated Output) Maximum Boost
. a)
b)
e)
......
..............
~
------l_J
'\
-- --- - -
- --~
'\-
----,-
---..!
\
1\
\
\
Frequency (MHz)
FIGURE 7: 32F8011/8012 Typical Group Delay Variation
(Differentiated Output) No Boost
5-30
fe = 5 MHz (Ref = 80ns)
fe =10 MHz (Ref = 45 ns)
fe = 15 MHz (Ref = 35 ns)
551 32F8011/8012
Programmable
Electronic Filter
-
a)
b)
e)
~ r-...
\
--- ----
\
\
----- ----- ----
-M
~--
------- ------
r-
C
\
1\
\
\
\
2.5
5.0
7.5
10.0
\
Ie = 5 MHz (Ref = 80 ns)
Ie = 10 MHz (Ref = 45 ns)
Ie = 15 MHz (Ref = 35 ns)
12.5
15.0
17.5
20.0
\
22.5
II
25.0
Frequency (MHz)
FIGURE 8: 32F8011 /8012 Typical Group Delay Variation
(Normal Low Pass Output) Maximum Boost
a)
b)
e)
I---
"'1'\
>
12
- ----\\
U>
c:
~
>.
~
REF f -
-------- -----
Q
a.
--------- ------- I-~
1\--
:>
e
r--
Cl
-------- -----
i "-1\
\
~
1\
\
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
C
\
22.5
Frequency (MHz)
FIGURE 9: 32F8011/8012 Typical Group Delay Variation
(Normal Low Pass Output) No Boost
5-31
25.0
Ie = 5 MHz (Ref = 80 ns)
Ie = 10 MHz (Ref = 45 ns)
Ie = 15 MHz (Ref = 35 ns)
SSI32F8011/8012
Programmable
Electronic Filter
INPUT
+2.94933
S'+ 3.22597S + 2.94933
3.32507
4.20534
s' + 2.75939S + 3.32507
s· + 1.82081 S + 4.20534
-KS'
S· + 3.22597S + 2.94933
Normalized for roc = (2n) Ie = 1
AN and AD are adjusted for unity gain (0 dB) at F = 0.67 Ie
Denormalize the frequency by substituting S --+ (Sl2nle)
Eq for Ie = 13 MHz, S = S / [(27<)(13 10 6 = S / 8.16814 1
0
»
FIGURE 12: 32F8011/8012 Normalized Block Diagram
TABLE 1: 32F8011/8012 Frequency Boost Calculations
Assuming 9.2 dB boost for VBP
= VR
VBP _ (10(FBI20»)_1
VR =
1.884
or,
boost in dB == 20 log
[1.884 (~:) + 1J
K
Boost
1 dB
2dB
3dB
4dB
5dB
VBPNR
0.065
0.137
0.219
0.310
OA13
0.36
0.76
1.22
1.73
2.30
Boost
6dB
7dB
8dB
9dB
K
2.94
3.65
4.46
5.36
VBPNR
0.528
0.658
0.802
0.965
VBPNR
Boost
VBPNR
Boost
0.1
0.2
0.3
0.4
0.5
1.499 dB
2.777 dB
3.891 dB
4.879 dB
5.765 dB
0.6
0.7
0.8
0.9
1.0
6.569
7.305
7.984
8.613
9.200
dB
dB
dB
dB
dB
TABLE 2: Calculations
Typical change in f-3 dB point
with boost
Boost (dB) Gain @ Ie (dB) Gain @ peak (dB)
-3
-2
·1
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
0.00
0.00
0.00
0.15
1.00
2.12
3.35
4.56
5.82
7.04
Notes: 1. fc is the original programmed cutoff frequency with no boost
2. f-3 dB is the new -3 dB value with boost implemented
3. fpeak is the frequency where the magnitude peaks with boost implemented
i.e., Ic = 13 MHz when boost = 0 dB
if boost is programmed to 5 dB then f-3 dB
= 27.69 MHz, {peak = 1.6.12 MHz
5'-32
fpeak/le f-3dB/le
no peak
no peak
no peak
0.62
1.08
1.24
1.24
1.39
1.39
1.39
1.00
1.20
1.47
1.74
1.96
2.13
2.28
2.42
2.54
2.66
SS132FS011/S012
Programmable
Electronic Filter
BOOST (dB)
TABLE 3: Typical Change Inl - 3 dB Point with Boost· K = 2.94933 (10-2 0-
-
1)
Boost (dB)
Galn@/e (dB)
Galn@peak (dB)
IPeakl/e
1-3dB/le
K
0
-3
0.00
no peak
1.00
0
1
-2
0.00
no peak
1.20
0.36
2
-1
0.00
no peak
1.47
0.76
3
0
0.15
0.62
1.74
1.22
4
1
1.00
1.08
1.96
1.73
5
2
2.12
1.24
2.13
2.30
6
3
3.35
1.24
2.28
2.94
7
4
4.56
1.39
2.42
3.65
8
5
5.82
1.39
2.54
4.46
9
6
7.04
1.39
2.66
5.36
10
7
8.24
1.39
2.77
6.38
Notes: 1. fC is the original programmed cutoff frequency with no boost.
2. f - 3 dB is the new -3 dB value with boost implemented.
3. fpeak is the frequency where the magnitude peaks with boost implemented.
e.g., fC = 13 MHz when boost = 0 dB
if boost is programmed to 5 dB then
fpeak = 16.12 MHz
f - 3 dB = 27.69 MHz
5-33
II
SSI32F8011/8012
Programmable
Electronic Filter
PIN DIAGRAM
Thermal Characteristics: 6jA
(Top View)
1S-lead SON (150 mil)
1S-lead SOL (300 mil)
GND1
VO_DIFF+
VO_NORM-
VO_DIFF-
VO_NORM+
PWRON
VCC1
1000 CIW
VR
VIN-
VCC2
VIN+
IFP
VBP
VFP
FBST
GND2
i6-lead SON, SOL
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
I
ORDER NO.
I
PKG.MARK
I
32F8011-CN
I
32F8011-CN
SSI32F8011
i6-lead SON (150 mil)
1S-lead SOL (300 mil)
J
32F8011-CL
1
32F8011-CL
I
32F8012-CN
I
32F8012-CN
SSI32F8012
is-lead SON (150 mil)
is-lead SOL (300 mil)
I
32F8012-CL
I
32F8012-CL
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use, No license is granted under any patents, patent rights ortrademarks of Silicon Systems, Silicon Systems
reserves the right to make changes in specifications at any time without notice, Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders,
Silicon Systems, Inc" 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1293 - rev,
5-34
©1989 Silicon Systems, Inc,
Patent Nos, (497,863) (500,778) (516,717)
SSI32FS020A/S022A/S021/S023
Low-Power Programmable
Electronic Filter
December 1993
DESCRIPTION
FEATURES
The SSI 32F8020Al8022A Programmable Electronic
Filter provides an electronically controlled low-pass
fiHer with a separate differentiated low-pass output. A
seven-pole, 0.050 Equiripple-type linear phase, lowpass filter is provided along with a single-pole, singlezero differentiator. Both outputs have matched delays.
The delay matching is unaffected by any amount of
programmed equalization or bandwidth. The SSI
32F8021/8023 does not have differentiated outputs.
This programability combined with low group delay
variation makes the SSI 32F8020Al8022A18021/8023
idealforuse in constant density recording applications.
Double differentiation pulse slimming equalization is
accomplished by a two-pole, low-pass with a twopole, high-pass feed forward section to provide
complimentary real axis zeros. A variable attenuator is
used to program the zero locations.
•
The SSI 32F8020Al8022A programmable equalization and bandwidth characteristics can be controlled by
external DACs or DACs provided in the 881 3204661
•
•
•
•
•
•
•
•
•
•
Ideal for constant density recording
applications
Programmable filter cutoff frequency (/c: 1.5
to 8 MHz)
.
Programmable pulse slimming equalization
(0 to 9. dB b()ost at the filter cutoff frequency)
Matched normal and differentiated low,pass
outputs (S81 32F8020A/8022A)
Differential fiHer Input and outputs
±10% cutoff frequency accuracy
±2% maximum group delay variation from
1.5-8 MHz
Total harmonic distortion less than 1%
No external filter components required
+5V only operation
16-pln SON and SOL package
(continued)
BLOCK DIAGRAM
VIN+
VIN-
PIN DIAGRAM
VO_DIFF+lNC
VO_NORM+
VO_NORM-
VO_NORM·
2
VO_DIFF-/NC
VO_NORM+
3
'PWRON
VR
VO_DIFF+lNC
VO_DIFF-INC
AX
IFO
vep
VR
IFI/IFC
FBSTIlZ
FBSTiCZ
IFVIFC
• Pin 8
RX
IFO
PWRON
1293 - rev.
Patent # 5,063,309
5-35
FBST - SSI 32F8020Al8021
LZ - SSI 32F8022A18023
= IFI- SSI32F8020Al8022A
• Pin 10
IFe - SSI32F802118023
• Pin 15 & 16 = VO_DIFF- SS132F8020Al8022A
NIC - SSI32F802118023
CAUTION: Use handling procedures necessary
for a static sensitive componem.
I
SSI 32F8020Al8022A/802118023
Low-P.ower· Programmable
Electronic Filter
Forprogrammable cutoff frequency, an extemal current
DAC can be used. The IFO should be the reference
current into the DAC. The DAC output current drives
IFI, which is then proportional to IFO. The DACF in the
SSI 3204661 Time Base Generator is designed to
control Ic of the Silicon Systems programmable filters.
When the DACF, which has a 4Xcurrent from its
reference to full scale output is use.d, a 5-kQ RX is
used. The Ic is then given as follows:
DESCRIPTION (continued)
SSI3204661 time base generator. Fixed characteristics
are easily accomplished with three extemal resistors.
Exter.nal DACs are required forthe SSI32F8021/8023
to program the cutoff frequency. Forthe SSI32F8020Al
8021 , equalization can be switched in or out by a logic
signal.The input impedance of the $SI 32F8022A1
8023 can be clamped low for fast recovery from input
overload.
/c(MHz)=8x F Code
127
The SSI 32F8020Al8022A18021/8023 require only a
+SVsupply and are available in 16-Lead SON and SOL
packages.
where F_Code is the decimal code equivalent to the
7-bit digital input for the DACF. The cutoff frequency
programming for the SSI 32F8021/8023 is shown in
Figure 3.
FUNCTIONAL DESCRIPTION
The SSI 32F8020Al8022A18021/8023 is a high
performance programmable electronic filter. It features
a 7-pole 0.05° phase equiripple filter with matched
normal and differentiated outputs. "T:he d~vice has
been optimized for usage with several Silicon Systems
products, including the SSI 3204661 .Time Base
Generator, the SSI 32P54Xfamily pulse detectors, and
the SSI 32P4720 combo chip (Data Separator and
Pulse Detector).
MAGNITUDE EQUALIZATION PROGRAJVlMING
The magnitude equalization, measured in dB, is the
amount of high frequency peaking atthe cutoff frequency
relative to the original -3 dB point. For example, when
9 dB boost is applied, the magnitude response peaks
up 6 dB above the DC gain.
The magnitude equalization is programmable with two
pins: VR and VBP. The VR is a bandgap reference
voltage, 2.3V typically. The voltage at the VBP.pin
determines the amount of high frequency boost. The
boost function is as follows:
CUTOFF FREQUENCY PROGRAMMING
The cutoff frequency, fc, of the. SSI 32F8020Al8022A
is defined as the -3dB filter bandwidth with no magnitude
equalization applied, and is programmable from 1.5
MHz to 8 MHz.
VBP
Boost(dB):=2010g1O[1.884( VR )+1]
The cutoff frequency is programmable with 3 pins: RX,
IFO and IF!. At the RX pin, an external resistor to
ground establishes a reference current:
For a fixed boost setting, a resistor divider between VR
to ground can be used with the divided voltage at the
VBP pih. For programmable equalization, an external
voltage DAC can be used. VR should be the reference
voltage to the DAC. The DAC output voltage is then
proportional to VA. The DACS in the SSI 3204661 is
designed to control the magnitude equalization of
Siliexln Systems programmable filters. When DACS is
used, the boost relation then reduces to:
IFO~ 0.75 atT=27 C
0
RX
IFI should be made proportional to IFOfortemperature
stability. The cutoff frequency is related to the RX
resistor, IFO and IFI currents as follows:
IFI
1.25
fc(MHz)~8x IFO x Rx(kQ)
Boost(dB)=2010g 10[1.884(
For a fixed cutoff frequency setting, IFO and IFI can be
tied together. The cutoff frequency equation then
reduces to:
1. 25
fc(MHz)=8x Rx(kQ)
S Code
127· )+1]
where S_Code is the decimal code equivalent to the
7-bit digital input for the DACS.
Forthe SSI 32F8020Al8021,the equalization function
can be disabled when FBST is pulled to logic O. For the
SSI32F8022A18023, the VBP pin should be grounded
to achieve 0 dB boost.
5-36
SSI 32F8020A/8022A/8021/8023
Low-Power Programmable
Electronic Filter
LOW INPUT IMPEDANCE (SSI32F8022A18023 only)
POWER ON/OFF
When the LZ is at logic 1 or left open, the SS132FS022A1
S023 input is at high impedance state. When the LZ is
pulled to logic 0, the SSI 32FS022A1S023 input is
clamped to a low impedance state, 200 n typical.
The SSI32FS020AlS022A1S021/S023 support a power
down mode for minimal Idle mode power dissipation.
When PWRON is pulled up to logic 1, the device is in
normal operation mode. When PWRON is pulled down
to logic 0, or left open, the device is in the power down
mode.
PIN DESCRIPTION
NAME
DESCRIPTION
VIN+, VIN-
DIFFERENTIAL SIGNAL INPUTS.
VO_NORM+,
VO_NORM-
DIFFERENTIAL NORMAL OUTPUTS.
VO_DIFF+
VO_DIFF-
DIFFERENTIAL DIFFERENTIATED OUTPUTS.
RX
PTAT REFERENCE CURRENT SET. PTAT (proportional to absolute temperature)
reference current IFO is equivalent to the current set on this pin.
IFO
PTAT CURRENT REFERENCE OUTPUT. This pin ouputs a PTAT reference current
which is extemally scaled for control input into IFI.
IFI
FREQUENCY PROGRAM INPUT. The filter cutoff frequency fc, is set by an external
current IFI, injected into this pin. IFI must be proportional to current IFO. This current
can be set with an external current generator such as a DAC, referenced to IFO.
VBP
FREQUENCY BOOST PROGRAM INPUT. The slimmer high frequency boost is set by
an external voltage applied to this pin. VBP must be proportional to voltage YR. A fixed
amount of boost can be set by an external resistor divider network connected from VBP
to VR and GND. No boost is applied if the FBST pin is grounded, or at logic low.
FBST
(32FS020AlS021 )
FREQUENCY BOOST. A high logic level or open input enables the frequency boost
circuitry. No boost is applied if the FBST pin is grounded, or at logic low.
LZ
(32FS022A /8023)
LOW IMPEDANCE MODE. With a low logic level, the analog input impedance is
switched low for fast recovery from input overload. With a high logic level or left open, the
input is at high impedance state.
PWRON
POWER ON. A high logic level circuit enables the chip. A low level puts the chip in a low
power state. A low or open circuit disables the chip.
VR
REFERENCE VOLTAGE. Internally generated reference voltage.
VCC
+5 VOLT SUPPLY.
GND
GROUND
5-37
SSI 32F8020A/8022A/8021/8023
Low-Power Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
RATING
PARAMETER
Storage Temperature
-65 to + 150°C
Junction Operating Temperature, Tj
+130°C
Supply Voltage, VCC
-0.5 to 7V
Voltage. Applied to Inputs
-0.5 to VCCV
RECOMMENDED OPERATING CONDITIONS
Supply voltage, VCC
4.50V < VCC < 5.50V
Ambient Temperature
O°C < Ta < 70°C
Power Supply Characteristics
CONDITIONS
PARAMETER
ICC
PD
Power Supply Current
Power Dissipation
MIN
NOM
PWRON~0.8V
MAX
UNIT
0.5
rnA
PWRON ~2.2V
SSI32F8021/8023
26
32
rnA
PWRON~ 2.2V
SSI 32F8020Al8022A
35
41
rnA
3
mW
PWRON~0.8V
PWRON ~ 2.2V, VCC
SSI32F8021/8023
= 5V
130
160
mW
PWRON ~ 2.2V, vec
SSI32F8021/8023
= 5.5V
143
176
mW
PWRON ~ 2.2V, VCC
SSI 32F8020Al8022A
= 5V
175
205
mW
PWRON ~ 2.2V, VCC
SSI 32F8020Al8022A
= 5.5V
193
226
mW
5-38
SSI 32F8020Al8022A18021/8023
Low-Power Programmable
Electronic Filter
DC Characteristics
PARAMETER
CONDITIONS
MIN
VIH
TTL input
2.0
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
High Level Input Current
VIH = 2.7V
ilL
Low Level Input Current
VIL=0.4V
VICM
VOCM
NOM
MAX
V
0.8
20
-1.5
VIN± Input
UNIT
V
~
rnA
(Vcc
-1.5)
-0.3
(Vee
-1.5)
+0.3
V
Common Mode Voltage
VO_NORM± Output
Common Mode Voltage
VCC-2.3
-0.5
VCC-2.3
+0.5
V
VIN± open
-0.4
+0.4
V
Rx = 5k.Q
1.5
8.0
MHz
VOFFVO_NORM± Output Offset
Filter Characteristics
fC
FiHer Cutoff Frequency
IFI
fC (MHz) = 8· 4.IFO
(32F8020Al8022A)
IFC
fC (MHz) = 8· 4.IFO
(32F8021/8023)
FiHer fc Accuracy
fC (nominal) = 8 MHz
-10
AO
VO_NORM Diff Gain
F = 0.67 fe, FB = 0 dB
0.8
AD
VO_DIFF Diff Gain
(32F8020Al8022A)
F = 0.67 fe, FB = 0 dB
0.8AO
FB
Frequency Boost at fc
FCA
FB(db)=20 log
[1.884(V::)+1]
1.0
+10
%
1.2
VN
1.2AO
VN
9.2
dB
VBP=VR
FBA Frequency Boost Accuracy
FB (ideal) = 9.2 dB
TGDO
fc = 8 MHz, VBP = OV
F = 0.2 fc to 1.75 fc
Group Delay Variation
Without Boost
fc = 1.5 MHz - 8 MHz
F = 0.2 fc to 1.75 fe, VBP = ov
TGDB
Group Delay Variation
With Boost
fC = 8 MHz, VBP = VR
F = 0.2 fC to 1.75 fc
fc = 1.5 MHz - 8 MHz
F = 0.2 fc to 1.75 fe, VBP = VR
5-39
-1
+1
dB
-1.3
+1.3
ns
-2
+2
%
-1.3
+1.3
ns
-2
+2
%
II
5S1 32F8020A/8022A/8021 18023
Low-Power Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS (continued)
Filter Characteristics
(continued)
PARAMETER
CONDITIONS
MIN
VOF Filter Output Dynamic Range
THO = 1% max, F = 0.67 Ic
1.0
Vpp
VOF Filter Output Dynamic Range
THO = 1.5%, F = 0.67 Ic
VO_DIFF±, Ic =1.5 MHz,
0< Ta < 10°C,
THO = 2%, F = 0.67 jc
32FS020AlS021
32FS022A1S023 LZ = 1 or open
1.5
Vpp
RIN
Filter Diff Input Resistance
CIN
Filter Input Capacitance
3.0
Output Noise Voltage
Differentiated Output
BW = 100 MHz, Rs =50n
Ic = S MHz, VBP = O.OV
MAX
4.0
200
32FS022A1S023 LZ = 0
EOUT
NOM
UNIT
kn
400
n
7
pF
6.3
7.5
mVRms
2.7
4.0
mVRms
9.4
11.0
mVRms
3.7
4.5
mVRms
(32FS020AlS022A)
EOUT
EOUT
BW = 100 MHz, Rs = 50n
Output Noise Voltage
Normal Output
Ic = S MHz, VBP = O.OV
Output Noise Voltage
Differentiated Output
Ic = S MHz, VBP = VR
Output Noise Voltage
Normal Output
= 100 MHz, Rs = 50n
Ic = S MHz, VBP = VR
BW = 100 MHz, Rs = 50n
(32FS020AlS020A)
EOUT
10-
Filter Output Sink Current
10+
Filter Output Source Current
RO
Filter Output Resistance
(Single ended)
BW
1.0
mA
2.0
mA
10+ = 1.0 mA
60
n
2.2
2.45
V
0
2.3
V
Filter Control Characteristics
VR
Reference Voltage
VBP
Frequency Boost Control
Voltage Range
VR = 2.3V
FBOOST = 0 to 9.2 dB
VRX
PTAT Reference Current
Set Output Voltage
TA = 25°C
IRX = 0 - 0.6 mA
Rx> 1.25 kn
IFO
PTAT Reference Current,
Output Current Range
TA = 25°C
1.25 kQ < Ri< < 6.S kn
IFO = VRx/Rx
VRX = 750 mV
RIFO
VIFO
IFO Output Impedance
750
0.11
mV
0.6
50
IFO Voltage Compliance
0
5-40
mA
kn
Vcc -1
V
SSI 32FS020AlS022A1S021/S023
Low-Power Programmable
Electronic Filter
Filter Control Characteristics
PARAMETER
CONDITIONS
MIN
MAX
UNIT
0.11
0.6
mA
. 1.0
2.5
kQ
NOM
IFI
PTAT Programming
Current Range
TA = 25°C, VRX = 750 mV
32F8020Al8022A
RIFI
IFllnput Impedance
32F8020Al8022A
VIFI
IFI VoHage Compliance
32F8020Al8022A
0.5
2.5
V
IFC
PTAT Programming
Current Range
TA = 25°C, VRX = 750 mV
32F8021 18023
0.11
0.6
mA
TPWR
TBST
TFBW
Power On
Recovery Time
DC voltages within
20 mV of final values
500
ns
Boost Change Recovery
DC voHages within
20 mV of final values
500
ns
Bandwidth Change Recovery
DC voHages within
20 mV of final values
500
ns
32F8020Al22A
NIC
VO_NORMVO_NORM+
vce (+5V)
VIN-
VR---"---,
RX~
VIN+
,...-,---VBP
~~
GND
lR,
=
RBI"
VR=2.3V
VRX = 750 mV @25°C
IFO= VRXiRx
IFI range: 0.11 mA to 0.60 mA @25°C
(1.5 to 8 MHz NO BOOST)
Fixed frequency programming is accomplished as shown in the drawing above. In this case IFI
(programming current) is equivalent to IFO (reference current). Programming current is then set
by VRxlRx.
where:
Ic = 8.0 MHz then
IFI = IFO = 0.60 mA @25 DC
Rx = 750 mV/0.60 mA = 1.25 kQ
FIGURE 1: 32FS020AlS022A Applications Setup
5-41
II
551 32F8020A/8022A/8021/8023
Low-Power Programmable
Electronic Filter
IN+
IN-
BY?
VR
= 2.3V
VRX = 750 mV @25°C
IFO = VRx/Rx
IFI range: 0.11 mA to 0.60 mA @25°C
(1.5 to 8 MHz NO BOOST)
In this case the IFI (programming current) is scaled from IFO (reference
current) through OACF on the 3204661. OACF has a current gain of 4;
therefore, the reference current should be set to 25% of the maximum desired
IFI (programming current).
where:
Ic (max) = 8.0 MHZ then
IFI (max) = 0.60 mA @25°C
IFO (max) = 0.15 rnA
therefore Rx
= 750 mV/O.15 rnA = 5 kQ
FIGURE 2: Applications Setup, Constant Density Recording
32F8020A/8022A,32P54X,32D4661
5-42
SSI 32F8020A/8022A/8021/8023
Low-Power Programmable
Electronic Filter
IFO
IFC
II
EXTERNAL DEVICES
VRX = 750 mV @25°C
IRX= IFO
IFC programming range: u. I I mA to 0.60 rnA @25°C
(1.5 to 8.0 MHz: No Boost)
The IFC (programming current) is scaled from IFO (reference current) by the
set-up shown above. Assuming the DAC current gain =4.0, then programming
is accomplished as follows:
MAX programming current required: IFC = 0.6 mA (fc = 8.0 MHz) @25°C
IFO = IFC/8 = 0.075 mA (MAX) @25°C
IRX = IFO
IRX = 750mV/Rx @25°C
Rx=5kQ
FIGURE 3: 32F8021 18023 Frequency Programming
5-43
SSI 32F8020A/8022A/8021 18023
Low-Power Programmable
Electronic Filter
INPUT
1.31703
2.95139
5.37034
S2+ S 1.68495 + 1.31703
S2+ S 1.54203 + 2.95139
S 2+ S 1.14558 + 5.37034
S2+ S 1.68495 + 1.31703
Normalized for roc = (21t) Ic = 1
AN and AD are adjusted for unity gain (0 dB) at F = 0.67
Denormalize the frequency by substituting S ..... (SI21t/c)
Eq for Ic = S.O MHz. S = S I [(21t)(S X 106 )]
DIFFONLYON
32F8020Al8022A
Ic
FIGURE 4: 32F8020Al8022A18021/8023 Normalized Block Diagram
BOOST (dB)
TABLE 1: 32F8020A/8022A Frequency Boost Calculations. K = 1.31703 (10-20Assuming 9.2 dB boost for VBP
(1 0(FB/20)
VBP_
VR
= VR
)-1
1.884
or,
boost in dB =: 20 log [1.884
(~:) + 1]
-1)
Boost
VBPNR
K
1 dB
0.065
0.16
2 dB
0.137
0.34
3dB
0.219
0.54
4dB
0.310
0.77
5dB
0.413
1.03
6 dB
0.528
1.31
7dB
0.658
1.63
8 dB
0.802
1.99
9dB
0.965
2.40
VBPNR
Boost
0.1
1.499 dB
0.2
2.777 dB
0.3
3.891 dB
0.4
4.879 dB
0.5
5.765 dB
0.6
6.569 dB
0.7
7.305 dB
0.8
7.984 dB
0.9
8.613 dB
1.0
9.200 dB
5-44
SSI 32FS020AlS022A1S021/S023
Low-Power Programmable
Electronic Filter
TABLE 2: Calculations
Typical change in 1-3 dB point and frequency peak with boost.
Boost (dB)
Galn@/c (dB)
Gain@peak (dB)
Ipeak/lc
1-3 dBllc
0
-3
0.00
no peak
1.00
1
-2
0.00
no peak
1.21
2
-1
0.00
no peak
1.51
3
0
0.15
0.70
1.80
4
1
0.99
1.05
2.04
5
2
2.15
1.23
2.20
6
3
3.41
1.33
2.33
7
4
4.68
1.38
2.43
8
5
5.94
1.43
2.51
9
6
7.18
1.46
2.59
NOTES: 1.
2.
3.
Ic is the original programmed cutoff frequency with no boost.
1-3 dB is the new -3 dB value with boost implemented.
Ipeak is the frequency where the magnitude peaks when boost is
implemented.
Le., Ic = 8 MHz when boost = 0 dB if boost is programmed to 5 dB then
1-3 dB = 17.6 MHz
Ipeak = 9.84 MHz
5-45
II
SSI 32F8020A/8022A/8021/8023
Low-Power Programmable
Electronic Filter
THERMAL CHARACTERISTICS:
PACKAGE PIN DESIGNATIONS
(Top View)
eja
16-Lead SON, SOL (150 mil)
N/C
VO_DIFF+
N/C
N/C
VO_NORM-
VO_DIFF-
VO_NORM-
N/C
VO_NORM+
PWRON
VO_NORM+
PWRON
VCC
VR
VCC
VR
VIN-
RX
VIN-
RX
VIN+
IFO
VIN+
IFO
VBP
IFI
LZ FBST
VBP
LZ
GND
IFI
FBST
GND
(8023) (8021)
(8022A) (8020A)
32FB021/B023
32FB020A/B022A
16·Lead SON, SOL
16·Lead SON, SOL
CAUTION: Use handling procedures necessary
for a static sensi~ve component.
ORDERING INFORMATION
PART DESCRIPTION
SSI 32F8020A
SSI 32F8022A
SSI32F8021
SSI32F8023
ORDER NUMBER
PACKAGE MARK
16-Lead SON
32F8020A-CN
32F8020A-CN
16-Lead SOL
32F8020A-CL
32F8020A-CL
16-Lead SON
32F8022A-CN
32F8022A-CN
16-Lead SOL
32F8022A-CL
32F8022A-CL
16-Lead SON
32F8021-CN
32F8021-CN
16-Lead SOL
32F8021-CL
32F8021-CL
16-Lead SON
32F8023-CN
32F8023-CN
16-Lead SOL
32F8023-CL
32F8023-CL
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Mytord Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1293 - rev.
5-46
©1991 Silicon Systems, Inc.
Patent # 5,063,309
SSI32F8030
Programmable
Electronic Filter
December 1993
DESCRIPTION
FEATURES
The SSI32F8030 Programmable Electronic Filter provides an electronically controlled low-pass filterwith a
separate differentiated low-pass output. A sevenpole, 0.05 0 Equiripple-type linear phase, low-'-pass
filter is provided along with a single-pole, single-zero
differentiator. Both outputs have matched delays. The
delay matching is unaffected by any amount of programmed high frequency peaking (boost) or bandwidth. This programability, combined with low group
delay variation makes the SSI 32F8030 ideal for use in
many applications. Double differentiation high frequency boost is accomplished by a two-pole, lowpass with a two"'"Pole, high-pass feed forward section
to provide complementary real axis zeros. A variable
attenuator is used to program the zero locations, which
controls the amount of boost.
•
The SSI32F8030 programmable boost and bandwidth
characteristics can be controlled by external DACs or
DACs provided in the SSI 32D4661 Time Base Generator. Fixed characteristics are easily accomplished
with three external resistors. In addition, boost can be
switched in or out by a logic signal.
•
Total harmonic distortion less than 1%
•
+5V only operation
•
16-Lead SON, and SOL packages
•
5 mW idle mode
Ideal for:
- constant density recording applications
- magnetic tape recording
•
Programmable filter cutoff frequency
(fc = 250 kHz to 2.5 MHz)
•
Programmable high frequency peaking
(0 to 9 dB boost at the filter cutoff frequency)
•
Matched normal and differentiated low-pass
outputs
•
•
Differential filter input and outputs
±3.0% group delay variation from
0.2 fC to 1.75 fc, 0.25 MHz:5 fc :5 2.5 MHz
The SSI 32F8030 requires only a +5V supply and is
available in 16-Lead SON, and SOL packages.
BLOCK DIAGRAM
PIN DIAGRAM
VIN+
VO_NORM+
GNDl
VIN-
VO_NORM-
VO_NORM-
2
VO_NORM+
3
VO_DIFF+
VO_DIFF-
VCC1
VO_DIFF+
VO_DIFFPWRON
VR
VCC2
IFP
VFP
VBP
VR
IFP
VFP
PWRON
FBST
CAUTION: Use handling procedures necessary
for a static sensitive component.
1293 - rev.
5-47
II
SSI32F8030
Programmable
Electronic Filter
FUNCTIONAL DESCRIPTION
SLIMMER HIGH FREQUENCY BOOST
PROGRAMMING
The SS132F8030, a high performance programmable
electronic filter, provides a low pass O.Oso Equirippletype linear phase seven polefilterwith matched normal
and differentiated outputs. The device has been optimized for usage with several Silicon Systems products, including the SSI32D4661 Time Base Generator,
the SSI32PS4x family of Pulse Detectors, and the SSI
32P4720 Combo device (Data Separator and Pulse
Detector).
The amplitude of the output signal at frequencies near
the cutoff frequency can be increased using this feature. Applying an external voltage to pin VBP which is
proportional to reference output voltage VA (provided
by the VA pin) will set the amount of boost. A fixed
amount of boost can be set by an external resistor
divider network connected from pin VBP to pins VA and
GND.· No boost is applied if pin FBST, frequency boost
enable, is at a low logic level.
CUTOFF FREQUENCY PROGRAMMING
The amount of boost FB at the cutoff frequency Fc is
related to the voltage VBP by the formula
The SSI 32F8030 programmable electronic filter can
be set to a filter cutoff frequency from 2S0 kHz to 2.S
MHz (with no boost).
FB (ideal, in dB) = 20 10910[1.884(VBPIVA)+ 1), where
O:2.0V
28
42
rnA
PD
Power Dissipation
PWRON;:>:2.0V
140
231
mW
PO
Power DisSipation
PWRON
3
mW
2.0
VCC+0.3
V
-0.3
0.8
V
~0.8V
DC Characteristics
VIH
High Level Input Voltage
VIL ..
Low Level Input Voltage
TTL input
IIH
High Level Input Current
VIH = 2.7V
ilL
Low Level Input Current
VIL = O.4V
20
-1.5
~
mA
Filter Characteristics
Ic = 1.25 MHz unless otherwise stated
FCA
Filter Ic Accuracy
AO
VO_NORM Diff Gain
AD
VO_DIFF Diff Gain
1.125
1.375
MHz
FB = 0 dB
0.8
1.20
VN
FB = 0 dB
0.9AO
1.1AO
VN
10.4
dB
%
using IFP pin: IFP = 0.4 rnA or
using VFP pin: Rx = 1.84 k.Q
fc,
F = 0.67 fc,
F = 0.67
9.2
FBA Frequency Boost Accuracy
VBP= VR
8.0
TGDO
Group Delay Variation
Without Boost'
0. 25 MHz ~ fc ~ 2.5 MHz
F = 0.2 Ic to 1.75 fc
-3
+3
Group Delay Variation
With Boost'
0.25 MHz ~ fc ~ 2.5 MHz
VBP = VR, F = 0.2 Ic to 1.75 Ic
-3
+3
TGDB
fC
VIF Filter Input Dynamic Range
THO = 1% max, F = 0.67
VOF
Filter Normal Output
Dynamic Range
THD = 1% max, F = 0.67
Filter Normal Output
Dynamic Range
THD = 1% max, F = 0.67 Ic
%
1.0
Vpp
1.0
Vpp
1.0
Vpp
1.0
Vpp
1.0
Vpp
(no boost. 1000 pF capacitor across Rx)
VOF
VBP
VBP
fC
=0 (1000 pF capacitor across Rx)
= VR (1000 pF capacitor across Rx)
0.67fc
VOF Filter Differentiated Output
Dynamic Range
THD = 1% max, F =
VOF Filter Differentiated Output
Dynamic Range
THD = 1% max, F = 0.67 Ic
VBP =VR (1000 pF capacitoracross Rx)
VBP
=0
(1000 pF capacitor across Rx)
5-50
SSI32F8030
Programmable
Electronic Filter
Filter Characteristics (continued)
PARAMETER
CONDITIONS
RIN
Filter DiU Input Resistance
CIN
Filter Diff input Capacitance'
MIN
NOM
MAX
UNIT
3.0
4.0
5.0
kQ
3.0
pF
EOUT
Output Noise Voltage'
Differentiated Output
BW = 100 MHz, Rs = 50Q,
lip = 0.8 mA, VBP = O.OV
2.7
3.2
mVRms
EOUT
Output Noise Voltage'
Normal Output
BW = 100 MHz, Rs = 50Q
lip = 0.8 mA, VBP = O.OV
1.6
2.0
mVRms
EOUT
Output Noise Voltage'
Differentiated Output
BW = 100 MHz, Rs = 50Q
lip = 0.8 mA, VBP = VR
3.1
3.8
mVRms
EOUT
Output Noise Voltage'
Normal Output
BW = 100 MHz, Rs = 50Q
IIp = 0.8 mA, VBP = VR
1.8
2.2
mVRms
EOUT
Output Noise Voltage'
Differentiated Output
BW = 10 MHz, Rs = 50Q,
lip = 0.08 mA, VBP = O.OV
1.8
2.1
mVRms
EOUT
Output Noise Voltage'
Normal Output
BW = 10 MHz, Rs '" 50Q
lip = 0.08 mA, VBP = O.OV
1.0
1.2
mVRms
EOUT
Output Noise Voltage'
Differentiated Output
BW = 10 MHz, Rs '" 50Q
lip = 0.08 mA, VBP = VR
2.0
2.5
mVRms
EOUT
Output Noise Voltage'
Normal Output
BW = 10 MHz, Rs = 50Q
lip = 0.08 mA, VBP = VR
1.1
1.5
mVRms
10-
Filter Output Sink Current
1.0
mA
10+ Filter Output Source Current
2.0
mA
RO
Filter Output Resistance"
Sinking 1 mA from pin
70
Q
2.40
V
2.0
mA
• Not directly testable in production, design characteristic.
" Single ended
Filter Control Characteristics
VR
IVR
2.0
Reference Voltage Output
Relerence Output
Source Current
5-51
SSI32F8030
Programmable
Electronic Filter
2
I
1
1.8
1\
1.6
\
1.4
en
2::
~
Cii
0
1 ifp
2 ifp
3 ifp
4 ifp
5 ifp
6 ifp
80 ~A
= 224 ~A
= 368 ~A
=512 ~A
= 656 ~A
= 800 ~A
(fc 250 kHz)
(fC = 700 kHz)
(fC= 1.15 MHz)
(fc = 1.6 MHz)
(fc = 2.05 MHz)
(fc = 2.5 MHz)
f-
ff-
1.2
\
1.0
~
0.8
1\
0.6
\
\
3
0.4
""
0.2
0.0
lOOk
300k
200k
400k 500k
700k
lmeg
~
\.
------ -"2meg
4meg 5meg
Frequency (Hz)
FIGURE 1: Typical Normal/Differentiated Output Group Delay Response
GND1
VO_DIFF+
VO_NORM-
VO_DIFF-
VO_NORM+
PWR_ON
VCC1 (+5V)
VIN-
VCC2 (+5V)
VR
IFP
VIN+
VBP
C,
R,
VFP
FBST
GN02
RBP'
FIGURE 1: 32F8030 Applications Setup 16·Pin SO
VR
= 2.2V
IVfp
VFP = .667 VR
= .33VR/Rx
IVfp range: 0.08 mA to 0.8 mA
(0.25 MHz to 2.5 MHz)
Cx = 1000 pF needed for THO at low Ic
VFP is used when programming current is set with a resistor from VR.
When VFP is used IFP must be left open.
5-52
6
r::::::: ~
r--
3meg
5
SSI32F8030
Programmable
Electronic Filter
IOF ; DACF output current
F = DAC setting: 0-127
IOF ; (0.98F·VR)/127Rx
Full scale, F = 127
Rx; (0.98F·VR)/12710F
For range of Max Ic ; 2.5 MHz then IFP = 0.8 mA
Rx = current reference setting resistor
Therefore, for Max programming current range to 0.8 rnA:
VR = Voltage Reference = 2.2V
Rx = (0.98)(2.210.8) = 2.7 kQ
Please note that in setups such as this where IFP is used for cutoff frequency programming VFP must be left open.
FIGURE 2: Applications Setup, Constant Density Recording
32F8030, 32P54X, 32D4661
INPUT
+1.31703
S '+ S 1.68495 + 1.31703
2.95139
S '+ S 1.54203 + 2.95139
5.37034
S'+ S 1.14558+ 5.37034
-KS'
S'+ S 1.68495+ 1.31703
Normalized for roc = (211) fc = 1
AN and AD are adjusted for unity gain (0 dB) at F = 0.67 fc
Denormalize the frequency by substituting S --> (S/211fc)
Eq for Ic = 2.5 MHz, S = S I [(211)(2.5.10 6 )] = S / (1.57080 • 10 7)
FIGURE 3: 32F8030 Normalized Block Diagram
5-53
SSI32F8030
Programmable
Electronic Filter
TABLE 1 : 32F8030 Frequency Boost Calculations - K
Assuming 9.2 dB boost for
VBP= VR
VBP _
(1 0(F8I2O»)_1
VR
1.884
Boost
K
VBPNR
Boost
K
VBPNR
1 dB
2dB
3dB
4dB
5dB
0.16
0.34
0.54
0.77
1.03
0.065
0.137
0.219
0.310
0.413
6dB
7dB
8dB
9dB
1.31
1.63
1.99
2.40
0.288
0.358
0.437
0.526
VBPNR
Boost
VBPNR
0.1
0.2
0.3
0.4
0.5
1.499 dB
2.777 dB
3.891 dB
4.879 dB
5.765 dB
0.6
0.7
0.8
0.9
1.0
or,
boost in
= 1.31703 (100oo8T (.8)'''' -1)
dB=20109[1.884(~:)+1]
Boost
6.569
7.305
7.984
8.613
9.200
dB
dB
dB
dB
dB
TABLE 2: Calculations
Typical change in
Boost (dB)
Gain @ fe(dB)
Gain @ peak(dB)
fpeak/fe
f-3 dB/fe
0
1
2
3
4
5
6
7
8
9
-3
-2
-1
0
1
2
3
4
5
6
0.00
0.00
0.00
0.15
0.99
2.15
3.41
4.68
5.94
7.18
no peak
no peak
no peak
0.70
1.05
1.23
1.33
1.38
1.43
1.46
1.00
1.21
1.51
1.80
2.04
2.20
2.33
2.43
2.51
2.59
1-3 dB point
with boost
Notes: 1.
Ie is the original programmed cutoff frequency with no boost
2. 1-3 dB is the new -3 dB value with boost implemented
3. Ipeak is the frequency where the magnitude peaks with boost implemented
i.e.,
Ic = 2.5 MHz when boost = 0 dB
if boost is programmed to 5 dB then f-3 dB = 5.5 MHz
Ipeak = 3.075 MHz
5-54
SSI32F8030
Programmable
Electronic Filter
PACKAGE PIN DESIGNATIONS
(Top View)
GND1
VO_NORMVO_NORM+
VCC1
VO_DIFF-
16-lead SON (150 mil)
1050 C/W
PWRON
16-lead SOL (300 mil)
1000 C/W
VR
VIN-
VCC2
VIN+
IFP
VBP
VFP
FBST
Thermal Characteristics: 9jA
VO_DIFF+
GND2
16-Lead SON, SOL
II
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
ORDER NUMBER
PACKAGE MARK
16-lead SON (150 mil)
32F8030-CN
32F8030-CN
16-lead SOL (300 mil)
32F8030-CL
32F8030-CN
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is grained under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1293 - rev.
5-55
©1991 Silicon Systems, Inc.
Patent Pending
Notes:
5-56
SSI 32F81 01/8102/8103/8104
Low-Power Programmable Filter
,tt!Iihltl Nt.]" ·6Ut•,;,
December 1993
DESCRIPTION
FEATURES
The 32F810X is a high performance, low power, digitally programmable low-pass filter for applications requiring variable-frequency filtering. The device consists of three functional blocks: [1] a 7th-order 0.05°
Equiripple Low-Pass filter, [2] two DACs for controlling
the fiHer cutoff frequency and high-frequency peaking
(boost), and [3] a Serial Port for programming the fc
and Boost DACs. The device is offered in four frequency options: the 32F81 01,9-27 MHz; 32F81 02,618 MHz; 32F8103, 4-12 MHz; & 32F81 04, 3-9 MHz.
•
Programmable cutoff frequency:
32F8101 • 9 to 27 MHz
32F8102 • 6 to 18 MHz
32F8103· 4 to 12 MHz
32F8104· 3 to 9 MHz
•
Progr~mmable boost/equalization of 0 to 14.3 dB
•
Matched normal and differentiated outputs
•
± 10% Ic accuracy
•
± 2% maximum group delay variation
•
Less than 1% total harmonic distortion
•
Low·Z Input switch controlled by LOWZ pin
•
No external filter components required
•
95 mW nominal power, <5 mW Idle
Cutoff frequency and boost are controlled by the two
on-chip 7-bit DACs, which are programmed via the 3line serial interface. Boost is programmable from 0 to
14.3 dB nominally at maximum fc, and is implemented
using two symmetrical, real-axis zeroes. Both boost
and fc control do not affect the flat group delay response.
The 32F81 OX device is ideal for variable data rate and
variable frequency shaping applications. It requires
only a +5V supply and has an Idle mode for minimal
power dissipation. The SSI32F81 OX is available in 16lead SON, and 20-Lead SOY packages.
BLOCK DIAGRAM
PIN DIAGRAM
VO_DIFF+
VO_DIFF·
RX
SCLl<
veD
SOEN
SOl
AGNO
16·Lead SON
veA AGND
1293 - rev.
veo DONO
SDEN
SOl
CAUTION: Use handling procedures necessary
for a static sensitive component.
SClK
5-57
II
SSI 32F81 01/8102/81 03/81 04
Low;;.Hower Programmable Filter
FUN~TIONAL
FILTER OPERATION
DESCRIPTION
The SSI32F810X programmable filter consists of an
electronically controlled low-pass filter with a separate
differentiated low-pass output. A se~en-pole.low-pass
filter is provided along with a Single-pole. single-zero
differentiator. Both outputs h,lVe matched delays. The
delay matching is unaftected by any amount of programmed equalization or bandwidth. Programmable
bandwidth and boost/equalization is provided by internal7-bit control DACs; High-frequency boost equalization is accomplished by a two-pole. low-pass with a
two-pole •. high-pass feed forward section to provide
complimentary real axis zeros. A variable attenuator is
used t (SI27tte)
Eq for Ie = 27 MHz. S = S I [(21t)(27 x 1.06 )]
FIGURE 1: 32F8101/81 02/81 03/8104 Normalized Block Diagram
5-58
SSI 32F81 01 /81 02/81 03/81 04
Low-Power Programmable Filter
TABLE 1: Calculations
Typical change in f-3 dB point with boost
Boost (dB)
Gain@fc (dB)
Gain@ peak (dB)
fpeaklfc
0
-3
0.00
no peak
1.00
0
1
-2
0.00
no peak
1.21
0.16
2
-1
0.00
no peak
1.51
0.34
3
0
0.15
0.70
1.80
0.54
4
1
0.99
1.05
2.04
0.77
5
2
2.15
1.23
2.20
1.03
6
3
3.41
1.33
2.33
1.31
7
4
4.68
1.38
2.43
1.63
8
5
5.94
1.43
2.51
1.97
2.40
f-3dBlfc
K
9
6
7.18
1.46
2.59
10
7
8.40
1.48
2.66
2.85
11
8
9.59
1.51
2.73
3.36
12
9
10.77
1.51
2.80
3.93
13
10
11.92
1.53
2.87
4.57
14
11
13.06
1.53
2.93
5.28
15
12
14.18
1.56
3.0
6.09
Notes: 1. fC is the original programmed cutoff frequency with no boost
2. f-3 dB is the new -3 dB value with boost implemented
3. fpeak is the frequency where the amplitude reaches its maximum
value with boost implemented
i.e., fc
= 9 MHz when boost = 0 dB
if boost is programmed to 5 dB then
f-3 dB = 19.8 MHz
fpeak
4. K
=
1.31703 (10
BOOST (dB)
20
- 1)
5-59
= 11.07 MHz
II
SSI 32F81 01/8102/8103/8104
Low-Power Programmable Filter
BOOST/EQUALIZATION CONTROL
After the SDEN goes high, the first 16 pulses applied to
the SCLK pin will shift the data presented at the SDATA
pin into an internal shift register on the rising edge of
each clock. An internal.counter prevents more than 16
bits from being shifted into the register. The data in the
shift register is latched when SDEN goes low. If less
than 16 clock pulses are provided before SDEN goes
low, the data transfer is aborted.
The programmable equalization is also controlled by
an internal DAC. The?-bit Filter Boost Control Register
(FBCR) determines the amount of.equalizationthat will
be added to the 3 dB cutoff frequency, asfollows:
Boost = 20 log [(0.0339 • FBCR) + 11 (dB)
20 log [(0.0283· FBCR) + (3.75·10-5·
FBCR· DACF) + 11
All transfers are shifted into the serial port LSB first. The
first byte of the transfer is address and instruction
information. The LSB of this byte is the R/W bit which
determines ifthe transfer is a read (1) or a write (0). The
remaining seven bits determine the internal register to
be accessed. The second byte contains the programming data. At initial power-up, the contents of the
internal registers will be in an unknown state and they
must be programmed prior to operation. During power
down modes, the serial port remains active and register programming data is retained.
For example, with the DAC set for maximum output
(FBCR = 7Fhex or 127) at the maximum cutoff frequency (DACF =7F hex or.127) there will be 14.3 dB
of boost added atthe 3 dB frequency. This will result in
+10 dB of signal boost above the 0 dB baseline.
SERIAL INTERFACE OPERATION
The serial interface is a CMOS bi-directional port for
reading and writing programming data fror:ntto the internal registers of the 32F81 OX. For data tr(lnsfers SDEN
is brought high, serial data is presented at the SDATA
pin, and a serial clock is -<
L
DATA8-BIT
.)----
FIGURE 2: Serial Port Data Transfer Format
Load data
,
SDEN
SCLK
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-,finIO Register
~.~ SO
EN setup
wrl SCLK rises
I
b
L. SO EN hold
I I wrllo SCLK rises
: - : SCLK period
FIGURE 3: Serial Interface Timing Diagram" Writing Control Register
5-60
TABLE 2: Serial Port Register Mapping
REGISTER NAME
~ ~
ADDRESS
« F_Code:,> 127
1.5
8
MHz
= 127
F_Code = 21
-10
+10
%
-15
+15
1.5to 8 MHz
100
F = 0.67 fC
0.7
1.1
VN
F = 0.67 fc
0.90 AO
1.2AO
VN
0
10
dB
F_Code
FB(dB) =20 log (0.01703 (S_Code) +1)
%
kHz
oto 10 dB, Ta < 22 °C
oto 10 dB, Ta > 22 °C
-1.5
+1.5
dB
FBA Frequency Boost Accuracy
-1
+1
dB
TGDO
0.2 fC - fc
-2%
gdm
+2%
gdm
ns
fe -1.75 fC
-3%
gdm
+3%
gdm
ns
0.2 fC - fC
-2%
gdm
+2%
gdm
ns
fC-1.75fc
-3%
gdm
+3%
gdm
ns
Boost Resolution
1.5 to 8 MHz
.25
dB
VOF Filter Output Dynamic Range
THO =1.5% max, VBP =0, VO_NORM
1.5
Vppd
1.5
Vppd
1.0
Vppd
1.0
Vppd
FBA Frequency Boost Accuracy
gdm
TGDB
Group Delay Variation
Without Boost
fc = 1.5 - 8 MHz
= group delay magnitude
Group Delay Variation
With Boost
fc
= 1.5 - 8 MHz
1000 pF capacitor across Rx
F_Code = 127
VOF Filter Output Dynamic Range
THO =3.5% max, VBP =0, VO_OIFF
1000 pF capacitor across Rx
F_Code = 127
VOF Filter Output Dynamic Range
THO =1.5% max, VBP = 0, VO_NORM
1000 pF capacitor across Rx
F_Code = 21
VOF Filter Output Dynamic Range
THO =2.0% max, VBP =0, VO_DIFF
1000 pF capacitor across Rx
F_Code = 21
5-73
II
SSI32F8120
Low-Power Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS (continued)
Filter CharacterlstIC$.(continued)
PARAMETER
MIN
CONDITIONS
RIN Filter Oiff Input Resistance
CIN
MAX
Output Noise Voltage
(VO_NORM)
BW = 100 MHz. 0 dB Boost
son input
10 dB Boost
Ic =8MHz
EOUT
Output Noise Voltage
(VO_OIFF)
BW = 100 MHz•. 0 dB Boost
son input
10 dB Boost
Ic = 8 MHz
UNIT
kn
Filter Input Capacitance
EOUT
10-
NOM
3.0
7
pF
1.8
3
mVRms
.2.35
.4
mVRms
4.2
6
mVRms
5.85
9
mVRms
Filter Output Sink Current
1.0
rnA
10+ Filter Output Source Current
3.0
mA
RO
Filter Output Resistance
(Single ended)
Output source current. 10+ = 1rnA
60
TC Period; SCLK
100
n
ns
T1 SO EN Setup to SCLK Falls
10
TC/2-10
ns
T2A SO EN Hold wrt SCLK Falls
10
TC/4
ns
T2B SOEN Falls prior to SCLK Rises
25
ns
T3 SOl Setup to SCLK Falls
25
ns
T4 SOl Hold to SCLK Falls
25
100 rnVpp @5 MHz on VCA. VCD
Common Mode Rejection Ratio
Vin = 0 VDC + 100 rnVpp@5MHz
30
50
Bias:
Vin+. Vin-
VCC=5V
2.5
2.9
3.3
V
VO_NORM+.VO_NORM-
VCC =5V
2.8
3.2
3.6
V
VO_OIFF+. VO_OIFF-
VCC=5V
2.8
3.2
3.6
V
+150
rnV
Output offset
Normal and Oifferentiated
40
ns
Power Supply Rejection Ratio
-150
5-74
70
dB
dB
SSI32F8120
Low-Power Programmable
Electronic Filter
TABLE 2: Calculations
Typical change in f-3 dB point with boost
Boost (dB)
Gain@fc (dB)
Gain@ peak (dB)
fpeak/fc
f-3dBlfc
0
-3
0.00
no peak
1.00
0
1
-2
0.00
no peak
1.21
0.16
K
2
-1
0.00
no peak
1.51
0.34
3
0
0.15
0.70
1.80
0.54
4
1
0.99
1.05
2.04
0.77
1.03
5
2
2.15
1.23
2.20
6
3
3.41
1.33
2.33
1.31
7
4
4.68
1.38
2.43
1.63
8
5
5.94
1.43
2.51
1.97
9
6
7.18
1.46
2.59
2.40
10
7
8.40
1.48
2.66
2.85
Notes: 1. fC is the original programmed cutoff frequency with no boost
2. f-3 dB is the new -3 dB value with boost implemented
3. fpeak is the frequency where the amplitude reaches its maximum value with
boost implemented
i.e., fc
= 2 MHz when boost = 0 dB
if boost is programmed to 5 dB then
= 4.40 MHz
fpeak = 2.46 MHz
1-3 dB
5-75
II
SSI32F8120
Low-Power Programmable
Electronic Filter
THERMAL CHARACTERISTICS: 9ja
PACKAGE PIN DESIGNATIONS
(Top View)
1000 C/W
16-lead SOL
20-lead SOY
N/C
20
N/C
OGNO
16
VO_OIFF+
VO_OIFF-
OGNO
2
19
VO_OIFF+
VO_NORM-
2
15
Vq_NORM-
3
18
VO_OIFF-
VO_NORM+
3
14
RX
VO_NORM+
4
17
RX
VCA
4
13
SCLK
VCA
5
16
SCLK
VIN-
5
12
VCO
VIN-
6
15
VCO
VIN+
6
11
SOEN
VIN+
7
14
SOEN
VBP
7
10
SOl
VBP
8
13
SOl
VFP
8
9
VFP
9
12
AGNO
N/C
10
11
NlC
AGNO
16-Lead SOL
2Q-Lead SOY
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
SSI32F8120
ORDER NUMBER
PACKAGE MARK
16-Lead SOL
32F8120-CL
32F8120-CL
20-Lead SOY
32F8120-CV
32F8120-CV
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
ofthird parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX 7141573-6914
Patent No. 5,063,309, Patent Pending 823,067
Cl993 Silicon Systems,lnc.
5-76
1294 - rev.
SS132F8130/8131
Low-Power Programmable
Electronic Filter
November 1993
DESCRIPTION
FEATURES
The SSI32F813018131 Programmable Electronic Filters are digitally· controlled low pass filters with a
normal low pass output and a time differentiated low
pass output. The low pass filter. is of a 7-pole / 2-zero
0.05° phase equiripple type, with flat group delay
response beyond the passband.
•
Programmable filter cutoff frequency (551
32F8130 FC=0.20 t.o 2.2 MHz, 551 32F8131: FC
= 0.15to 1.4 MHz)wHh no external components,
serial data connections to mlnlmze pin count
•
•
Power Down mOde «5 mW)
The SS132F8130/8131 bandwidth and boost are controlled by two on-Chip 7-bit DACs, which are programmed via a 3-line serial interface. The SSI32F8130
filter bandwidth is programmable from 200 kHz to 2.2
MHz. The SSI32F8131 is programmable from 150 kHz
to 1.4 MHz. The boost is programmable from 0 to 10
dB. Because the boost function is implemented as two
zeros on the real axis with opposite sign, the flat group
delay characteristic is not affected by the boost programming.
The SS132F8130/8131 are ideal for multi-rate, equalization applications. They require only a +5V supply
and have a Power Down mode for minimal idle dissipation. The SS132F8130/8131 is available in a 16-lead
SOL package.
Programmable pulse slimming equalization
(0 to 10 dB boost at the flHer cutoff frequency)
•
Matched normal and differentiated low-pass
outputs
•
•
•
•
•
Differential filter Inputs and outputs
II
Programming via Internal 7-bH DACs
No external filter components required
+5V only operation
5upports constant density recording
BLOCK DIAGRAM
PIN DIAGRAM
VO_NORM (S/2rcIc)
Eq for Ic = 27 MHz, S = S I [(2rc)(27 x 10")]
FIGURE 2: 32F8144 Normalized Block Diagram
PACKAGE PIN DESIGNATIONS
(Top View)
THERMAL CHARACTERISTICS: 9ja
EXTCAP+
VCA
EXT CAP-
VIN+
[Z
20-lead SOL
VONORM-
20-lead SOY
VONORM+
VBP
VINAGNO
YAP
SCLK
VO OIFF+
VCO
VO OIFF-
SOEN
VFP
RX
SOl
OGNO
CAUTION: Use handling procedures necessary
for a static sensitive component.
20-lead SOL, SOY
ORDERING INFORMATION
PART DESCRIPTION
ORDERING NUMBER
PACKAGE MARK
SSI32F8144
20-Lead SOL (300 mil)
32F8144 - CL
32F8144 - CL
SSI32F8144
20-Lead SOV (220mil)
32F8144 - CV
32F8144 - CV
Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No respcnsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573:6914
©1993 Silicon Systems, Inc.
Protected by the following patents: (5,182,477), (5,063,309)
Patent Pending: 710, 512
5-92
0194 - rev.
Section
6
READ CHANNEL
COMBINATION DEVICE
II
6
6-0
SSI 32P4340/4341
Read Channel Devices
a"bi"iMt.", ,Flit.,"
December 1993
User selectable internal LOW-Z and fast
decay period
0.75 ns max. pulse pairing (sine wave
input)
Adjustable level decay current (4-bit)
SERVO CAPTURE
4-burst servo capture (A-B, CoD 32P4340)
(A, B, C, D32P4341)
Internal hold capacitors
Separate registers for servo Ic and VTH
Adjustable level decay current (4-blt)
Adjustable servo peak detector current
PROGRAMMABLE FILTER
Programmable cutoff frequency of 4.5 to
15MHz
Programmable boost/equalization of 0 to
13dB
Matched normal and differentiated outputs
± 10% Ic accuracy
± 30% programmable group delay
variation
less than 1% total harmonic distortion
No external filter components required
TIME BASE GENERATOR
Better than 1% frequency resolution
Up to 60 MHz frequency output
Independent M and N divide-by registers
VCO center frequency matched to data
synchronizer VCO
DATA SEPARATOR
Fast acquisition phase lock loop with zero
phase restart technique
Integrated 1,7 RLL Encoder/Decoder
Programmable decode window symmetry
Window shiH control ±i5% (4-bit)
Includes delayed read data and veo
clock monitor points
Programmable write precompensation (3-bit)
DESCRIPTION
The 32P4340/4341 device is a high performance
SiCMOS single chip read channellC that contains all
the functions needed to implement a complete zoned
recording read channel for hard disk drive systems.
Functional blocks include the pulse detector,
programmable filter, 4-burst servo capture, time base
generator, and data separator with 1,7 RLL ENDEC.
Data rates from 14 to 40 Mbitls can be programmed
using an internal DAC whose reference current is set
by a single external resistor.
Programmable functions of the 32P4340/4341 device
are controlled through a bi-directional serial port and
banks of internal registers. This allows zoned
recording applications to be supported without
changing external component values from zone to
zone.
FEATURES
GENERAL
Power supply range (3.0 to 5.5 volts)
Programmable 14 to 40 Mbitls data rate
Complete zoned recording support
Low power operation (350 mW typical
@3.3V)
BI-directional serial port for register
access
Register programmable power
management (Sleep mode <1.0W)
Small footprint 64-lead TQFP package
PULSE DETECTOR:
Dual rate charge pump for fast transient
recovery
Low DriH AGC hold circuitry
Temperature compensated, exponential
control AGC
Wide bandwidth, high precision full-wave
rectifier
Dual mode pulse qualification circuitry
CMOS RDIO output for servo timing
This is an abridged version of the SSI 32P4340/4341 data sheet. For a complete copy contact your
local Silicon Systems sales office, or calli -800-624-8999, ext. 151.
1293
6-1
II
:O(/)
-'
8
~
5 Fa -
Test points -
g; ~
0
CL
a.
ZCL
U
U
Cl
Q.
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~
mC.W
ON
RX
n
VIA
rl-+-l ..... J
.. I"'II'~'[;CMTI
VIA r'l-4-l 1-.c
r+-, I .---L---._
rf
DOr'\~DAUUADI
C
nlFFFRFt,iTIATOR
1
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I
I
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I L..j;?tt1 ;-:--; I I I
,~
II
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::T"tJ
m~
:JW
:J~
I
(1)-
-~
OW
(I)~
!S. ...L
(')
(I)
VSAGC~
VDAGC
en
'"
I.
ROC+--=-~
I
I
S-PORT
I 1I ~
SG
,
G b","_~, I
_
I,
fA
I I II
SHOT
~
COUT
FROM
SERIAL
PORT
.. DOUT
VPG
I
~I
...,
Cl
Z
t/)
>
Cl
Z
>
w
~
o
~
CD :J:
~ :5
0
:J:
~
I-- VPG
CT
FIGURE 1(a): 32P4340 Front End Block Diagram
i
Cl
Z
>
CD
.(
OCD
, +
0...:
LL
w
a:
t/)
...J
g
~
5 15 -
CJ
~
z "-
g; is
Test points -
<..l <..l
-g;
Q.
i
RX
VIA
ViA
VSAGC
VDAGC~
'"W
HOm~\
I I I
S-PORT
~ ~IVTHDAcl
-
I
~
I I II
~
I
FROM
SERIAL
PORT
COUT
.. DOUT
&
VPG
:I:J
CD
Q)
I
...J
w
>
~ CJ
Z
&1
> >
UJ
...J
I----
UJ
..:
Q.CJ)
OCJ)
R >< >R ><
X;3' >R X X >f: .~
NRZ DATA
NRZ1
NRZO
Y1
Y2
----
PRESENT
CODE WORD
NRZ1'
Y3
1,7CODE
/
PREVIOUS CODE
WORD LAST BIT
•
NEXT CODE WORD
FIRST BIT
FIGURE 13: NRZ Data Word to 1,7 Code Word Bit Comparison
(Reference Table4 for decode scheme)
RRC
1.5V
1 - - - - - TORC - - - - - - I
TF~ ~
~ ~
TRRC
NRZO/1
FIGURE 14: NRZ Read Timing
6-20
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
READ MODE (continued)
Write Mode Operation
Window Shift
Write mode is entered by asserting WG high ("1 ") while
RG and SG are held low ("0"). A preamble pattern of at
least 19 '3T' patterns must be generated before any
coded data can be written. The 3T preamble is written
by holding both NRZO and NRZ1 low ("0") while WCLK
is toggled. The first non zero NRZ input bits indicate the
end of the preamble pattern. After a delay of 3 WCLK
time periods, non-preamble data begins to toggle out
WD. At the end of the write cycle, 3 WCLK cycles of
blank NRZ should be added to insure the encoder is
flushed of data before the WG can be transitioned low.
WD stops toggling a maximum of 2 WCLK time periods
after WG goes low. Reference Figures 15 and 17 for
detailed timing information. In Figure 15, note that the
NRZ1 bit is shifted into the encoder first and the N RZO
bit is shifted into the encoder second. Because two bits
are clocked into the device on each WCLK pulse, the
encoder will always generate a predictable pattern.
Shifting the phase of the VCO-clock effectively shifts
the relative position of the ORO pulse within the decode
window. Decode window control is provided via the WS
control bits of the Window Shift Control Register
(WSCR).
NON READ MODE
In the non-Read modes, the PLL is locked to the
reference clock. This forces the VCO to run at a
frequency which is very close to that required for
tracking actual data. When the reference input to the
PLL is switched, the VCO is stopped momentarily, then
restarted in an accurate phase alignment with the next
PLL reference input pulse. By minimizing the phase
alignment error in this manner, the acquisition time is
substantially reduced.
WRITE MODE
Direct Write Function
In the Write mode the circuit converts NRZ data from
the controller into 1,7 RLL formatted data for storage on
the disk. Write mode is entered by asserting the write
gate (WG) while the RG and SG are held low. During
Write mode the VCO and the RRC are referenced to
the internal time base generator signal. The write data
output is a negative going TTL signal for the 32P4742
and a differential PECL signal for the 32P4742A. For
the 32P4742A, the rising edge of the WD pin is the
active edge. External termination of the WD/WD pins is
required on the 32P4742A.
The 32P4742 includes a Direct Write (OW) function
that allows the NRZO data to bypass the encoder and
write precomp circuitry. When the OW bit is set in the
CBR, the data applied to NRZO will bypass the encoder
and write precomp and directly control the WDI output
buffer. This allows the user to perform DC erase and
media tests. A rising edge at NRZO causes a rising
edge on WD, a falling edge at NRZO causes a falling
edge on WD. This information applies tothe 32P4742.
A rising edge at NRZO causes a rising edge on WD and
a falling edge on WD. A falling edge at NRZO causes a
falling edge on WD and a rising edge on WD. This
information applies to the 32P4742A.
6-21
I
•
SSI 32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
WCLK
I-----Towc-----t
1.SV
NRZO/i _ _- - - - - - '
TSNRZ
THNRZ
SERIALIZED DATA STREAM
NRZi
NRZO
I
NRZi
DATA 0
WD
I
NRZO
I
NRZi
DATA 1
--------~
(32p~~an-d32-p47-46A-MIYI------>t Two
I
1 TRJt =ko
FIGURE 15: WD and NRZ Write Timing
6-22
NRZO
DATA 2
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
RG~
RG
1
(internal) _ _ _ _ _ _ _---'
RD
(internal)
1001001001
~~
RESTART
h
-+-----------11
n
1'---------------------1
V\
FLTR
--r-----------~I
VCOLOCK
L-
IGAIN SHIFT, IF ENABLED
'-~.----------------------------~
1
RRC
1 RRC 1 RRC (max)
(max)
BIT SYNC
SEARCH - - j - - - - - DISABLE - t - - - I - - j
H·
I
ENABLE~L_ _ _ _ _ _ _ __
NRZOI
NRZ1-+-------~--~~-----------~~~--~~~---
RRC
SOURCE __~------------~----~
PHASE
DETECTOR
SOURCE
VCOCLOCK
--+---'
FREF CLOCK
1
INTERNAL
1
1
COUNTER_~-----------~----~~------~-------------3
14191- (Raw data pulse count)
FIGURE 16: Read Mode Locking Sequence
6-23
I
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
RG
~~~____________________________________~
I--j
1 NRZ (min)
1 NRZ (min)
r
WG
WG
(intemal)
21 RRC (min)
kx-x\
I--l
I
NRZOI
NRZ1
13 NRZ (max)
3 NRZ PAD
TO FLUSH
ENCODER
JiJLrul
.1. ..
DATA
EDGE
FLTR
VCO
LOCK
sou~g~
~-------------------------------
~~-----------------------------------AD t R E F / 2
SOU~~~ VCO/3
FREF/3
1 RRC (max)
RRC
ENCODE
DATA
XX
XX-FIGURE 17: Write Data Operation
6-24
SSI 32P4742/47 42A/474614746A
Read Channel with
1,7 ENDEC, 4-burst Servo
FUNCTIONAL DESCRIPTION
(continued)
OPERATING MODES AND CONTROL
The device has several operating modes that support
read, write, servo, and power management functions.
Mode selection is accomplished by controlling the read
gate (RG), write gate (WG), servo gate (SG), and
PWRON pins. Additional modes are also controlled by
programming the Power Down Control Register
(PDCR), the Control A (CAR) register, and the Control
B (CSR) register via the serial port.
External Mode Control
(SG), and PWRON pins with TTL compatible signals
(refer to Table 3). For normal operation the PWRON
pin is driven low. Du ring normal operation the device is
controlled by the read gate (RG), write gate (WG), and
servo gate (SG) pins. Servo gate (SG) determines the
active mode of the device. When SG is high, the device
enters the Servo mode, regardless of the state of either
RG orWG. When SG is low, RG and WG can be used.
When RG is highthe device is in Read mode regardless
ofthe state ofWG. WhenSG and RG are both low, WG
is brought high to enter Write mode. If SG, RG, and WG
pins are all low the device will be in Idle mode.
All operating modes of the device are controlled by
driving the read gate (RG), write gate (WG) , servo gate
REGISTER DESCRIPTION
Control Registers
The serial port registers allow the user to configure the device. The register map for the device is shown in
Table 4. The bits of these registers are defined as follows:
POWER DOWN CONTROL REGISTER (PDCR)
BIT
NAME
0
PD/SVO
Pulse detector/servo power enable: Determines the state of the pulse
detector and servo circuits when PWRON pin is low.
o =Circuits enabled
1 = Circuits powered down
1
TBGKD
TIme base KD select: Determines the phase detector gain of the time
base generator.
o =KD is 3x nominal value
1 = KD is 1x nominal value
2
FLTR
Filter power enable: Determines the state of the filter when PWRON
pin,is low.
o= Filter enabled
1 = Filter powered down
3
DS
Data separator power enable: Determines the state of the data
separator circuit when PWRON pin is low.
o= Data separator enabled
1 = Data separator powered down
4
TBG
Time base generator power enable: Determines the state of the Time
base generator circuit when PWRON pin is low.
o= Time base generator enabled
1 = Time base generator powered down
5-7
N/A
DESCRIPTION
Device ID: These bits are a read only ID code for the device.
6-25
I
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
REGISTER DESCRIPTION
(continued)
DATA MODE CUTOFF (DACF)
BIT
NAME
0-6
DMC
Filter cutoff selling for Data mode. Substitute this value for DACF into
the cutoff calculation for the filter in Data mode operation.
7
N/A
Not used. Set to zero.
DESCRIPTION
SERVO MODE CUTOFF (DACF)
0-6
DMC
Filtercutoff setting for Servo mode. Substitute this value for DACF into
the cutoff calculation for the filter in Servo mode operation.
7
WDB
Buffer type: Determines if the TTL write data buffer is enabled.
0= enabled
1 = disabled
FILTER BOOST REGISTER (DACS)
0-6
FBC
7
SBE
Filter boost setting. Substitute this value for DACS into filter calculations.
Servo boost enable: Determines if boost is enabled when SG is high.
o = Boost disabled when SG is high
1 = Boost enabled when SG is high
DATA THRESHOLD REGISTER (VTHDAC)
0-6
DTH
7
DQ
Data threshold setting. Substitute this value for VTHDAC into the
threshold calculation for Data mode operation.
Qualifier select: Determines the type of qualifier used in Data mode.
o = Hysteresis qualifier
1 = Dual comparitor qualifier
SERVO THRESHOLD REGISTER (VTHDAC)
0-6
STH
7
SQ
Servo threshold setting. Substitute this value for VTHDAC into the
threshold calculation for Servo mode operation.
Qualifier select: Determines the type of qualifier used in Servo mode.
o= Hysteresis qualifier
1 = Dual comparitor qualifier
6-26
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
CONTROL A REGISTER (CAR)
BIT
NAME
DESCRIPTION
0
EPDT
Enable Phase Detector (Time Base Generator): This bit disables the
output of the phase detector to the VCO. An extemal voltage applied
across the TFLT pins drives the VCO to a fixed frequency.
o= Phase detector charge pump disabled
1 = Phase detector charge pump enabled
1
UT
Enable Pump Up Current (Time Base Generator): This bit enables a
test mode for checking the charge pump output current. The charge
pump will source a fixed DC current from TFLT and sink the current
atTFLT.
o= No current
1 = Pump up current enabled
2
DT
Enable Pump Down Current (Time Base Generator): This bit enables
a test mode for checking the charge pump output current. The charge
pump will source a fixed DC current from TFLT and sink the current
atTFLT.
o= No current
1 = Pump down current enabled
3
MTP3E
4
BYPT
5/6
TMSO/1
These bits select the test point signal sources (ref Table 8)
7
FDTM
This bit continuously enables the AGC fast decay current.
o = Fast decay current always on
1 = Normal fast decay operation
Set to 1 for normal operation.
This bit enables the MTP3 test point output buffer.
o= Test point disabled
1 = Test point enabled
This bit enables a Time Base Generator Bypass mode where the
FREF input is connected to the data separator phase detector input.
o= Time base enabled
1 = Time base bypassed
6-27
I
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 EN DEC, 4-burst Servo
REGISTER DESCRIPTION
(continued)
CONTROL B REGISTER (CBR)
BIT
NAME
0
OW
1
GS
2
RDIO
This bit enables the ROIO pin as an input.
= RDIO is an output
1 = RDIO is an input
3
EPDD
Enable Phase Detector (Data Separator): This bit disables the output
of the phase detector to the VCO. An external voltage applied across
the DFLT pins drives the VCO to a fixed frequency.
= Phase detector charge pump disabled
1 = Phase detector active
DESCRIPTION
This bit enables the directwrite (Bypass Endec) function.
= Normal operation
1 = Bypass encoder, NRZO buffered to WD (orWD/WDfor32P4742A
and 32P4746A)
o
This enables the data sep. phase detector gain switch in Read mode.
= Normal operation
1 = Gain shift until 14 x 3T (Read mode only)
o
o
o
4
UD
Enable Pump Up Current (Data Separator): This bit enables a test
mode for checking the charge pump output current. The charge pump
will sourceafixed DC currentfrom DFLT and sink the current at DFL T.
= No current
1 = Pump up current enabled
o
5
DO
Enable Pump Down Current (Data Separator): This bit enables a test
mode for checking the charge pump output cu rrent. The charge pump
will source a fixed DC current from DFL T and sink the current at DFLT.
= No current
1 = Pump down current enabled
o
6
MTP1,2E
7
-
This bit enables the multiplexed test pOints (MTP1 , 2)
0= Test points disabled
1 = Test points enabled
Not used. Set to zero.
N COUNTER REGISTER
0-6
N
7
LZT
N counter value.
Low-Z time period: Determines the time period for the Low-Z and fast
decay one-shots.
0=1 JlS nominal time-out (0.4 JlS HOLD on SG edges)
1 = 2 JlS nominal time-out (0.5 JlS HOLD on SG edges)
M COUNTER REGISTER
0-7
M
M counter value.
6-28
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
DATA RECOVERY REGISTER (DRCR)
BIT
NAME
0-6
IDAC
7
TM
DESCRIPTION
Center frequency DAC value. Sets the center frequency for the data
synchronizer VCO and the TBG VCO.
Test mode bit: SSi use only. Set to 0 for normal operation.
WINDOW SHIFT REGISTER (WSR)
Window shift DAC value.
0-3
WS
4
WSD
Window shift direction.
0= Early
1 = Late
5
WSE
Window shift enable.
0= Disable
1 = Enable
6-7
TDACO/1
DACOUT test point select: Selects the DAC output to be provided on
the DACOUT test point. The preferred setting when DACOUT is not
being monitored is to set TDACO = 1 and TDAC1 = 0:
TDAC1
TDACO
0
0
1
1
0
1
0
1
DAC MONITORED
Filter Fc DAC
Qualifier threshold DAC (VTH)
Window shift DAC
Write precomp DAC; the selection of the early
or late DAC is controlled by the WPE bit.
WPE =O-Late
WPE = 1 - Early
WRITE PRECOMP REGISTER (WPR)
0-2
WPE
Write precomp early DAC value.
3
WPE
Write precomp enable.
0= Disable
1 = Enable
4-6
WPL
Write precomp late DAC value.
7
SRST
Servo reset select. Set to 1 for normal operation.
6-29
I
SS132P474214742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
REGISTER DESCRIPTION
(continued)
AGC LEVEL REGISTER (ALR)
0-3
ADAC
AGC level DAC value. Sets AGC level in Servo mode.
0000 = 1 Vpp
1111 = 0.75 Vpp
4-7
PDAC
Servo peak detector current DAC value. Sets the servo peak detector
current in 6 ~ steps.
0000 = 6 ~ charge current
1111 = 96 ~ charge current
Power Down Control
For power management, the PWRON pin can be used in conjunction with the Power Down Control Register
(PDCR) to setthe Operating mode ofthe device. The PDCR provides a control bit for each ofthe functional blocks.
When the PWRON pin is brought high ("1'J the device is placed into Sleep mode «0.5 rnA) and all circuits are
powered down except the serial port. This allows the user to program the serial port registers while still conserving
power. Register information is retained during the Sleep mode so it is not necessary to reprogram the serial. port
registers after returning to an Active mode. When the PWRON pin is low ("0"), the contents of the PDCR determine
which blocks will be active. Register mapping for the PDCR is shown in Table 4. To improve recovery time from
the Sleep mode, the inputs to the filter and AGC circuits are placed into a Low-Z mode.
6-30
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
TABLE 3: Mode Control Table
(f)
DAC
CONTROL en
w
a:
I- w
(f)
I0 (f)
:r:
!> u.<.) 0CD I>-
CONTROL
LINE
12fi?
<.9
~ a:
<.9
<.9
(f)
$:
DEVICE MODE
off off off off
1
X
X
X
SLEEP MODE: All functions are powered down. The serial
port registers remain active and register programming data is
saved.
0
0
0
1
WRITE MODE: The pulse detector is inactive. The data
synchronizer VCO is locked to the internal time base generator
Write precomp circuit is clocked by internal time base.
DR DR DR DR
0
1
0
X
READ MODE: The pulse detector is active. The data
synchronizer begins the preamble lock sequence.
DR DR DR DR
0
X
1
X
SERVO MODE: The pulse detector is active and the servo
control registers are enabled for the Fc DAC and the VTH
DAC. RDIO is also active. The data synchronizer and time
base generator can be disabled using the PDCR.
0
0
0
0
SR SR
On it SSE
IDLE MODE: The contents of the PDCR determine which
blocks are powered-up. In normal operation with all blocks
powered-up, the pulse detector is active, the data synchronizer
VCO is locked to the time base generator, and the data control
registers are used tor VTH and FC.
= data register, SR
=
servo register, off
= disabled
DAC Control Key: DR = data register, SR = servo register, off = disabled
6-31
=1
DR DR DR DR
It multiple control signals are active, the priority order will be
PWRON, SG, RG, and WG. For example, if SG and RG are
both "1", the Servo mode will be active.
DAC Control Key: DR
of SR
I
..... J](J)
CD (J)
~
...... m-
mC.W
ZON
TABLE 4: Serial Port Register Mapping
REGISTER NAME
z:
co
«
ADDRESS
~ ~
POWER DOWN CONTROL
0 0
0 0 0 1 0 0
DATA MODE CUTOFF
0 0
0 0 0 1
1 0
SERVO MODE CUTOFF
0 0
1 0 0 1
1 0
FILTER BOOST
0 0
0 1 0 1 1 0
C:::r"'O
DATA BITMAP
07
DO
--
--
TBG
I = Disable
0= Enable
DATASEP
I = Disable
0= Enable
FILTER
I = Disable
0= Enable
TBGKD
I = Ix KD
0=3xKD
PDISERVO
I = Disable
0= Enable
FCDDACF
BIT6
FCDDACF
BITS
FcoDACF
BIT4
FCDDACF
BIT3
FcoDACF
BIT2
FCDDACF
BIT I
FCDDACF
BITO
FcsDACF
BIT 6
FcsDACF
BITS
FcsDACF
BIT4
FcsDACF
BIT3
FcsDACF
BIT2
FcsDACF
BIT I
FcsDACF
BITO
DACS
BIT6
DACS
BITS
DACS
BIT4
DACS
BIT3
DACS
BIT2
DACS
BIT I
DACS
BITO
TDDAC
BIT6
ToDAC
BITS
TDDAC
BIT4
TDDAC
BIT3
TDDAC
BIT2
TDDAC
BIT I
TDDAC
BITO
~:~~
TsDAC
BIT6
TsDAC
BITS
TsDAC
BIT4
TsDAC
BIT3
TsDAC
BIT2
TsDAC
BITI
TsDAC
BITO
FD Test
I = Disable
0= Enable
TMSI
TMSO
*
MTPII2
I = Enable
O=Disable
PUMPDWN
I =ON
O=OFF
Low-ZTime
I =21's
o=liuo
NCOUNT
BIT6
NCOUNT
BITS
NCOUNT
BIT4
NCOUNT
BIT3
NCOUNT
BIT2
NCOUNT
BIT I
NCOUNT
BITO
--
.
Buffer Type
1 = 4742A
0= 4742
Servo Boost
I = Enable
0= Disable
Data Qual.
DATA THRESHOLD
0 0 0 1 0 1 0 0
SERVO THRESHOLD
0 0
1 0 0 1 0 0
CONTROL A
0 0
1 1 0 1 0 0
CONTROL B
0 0
0 1 1 0
N COUNTER
0 0
0 0
MCOUNTER
0 0
0 1 1 1 0 0
MCOUNT
BIT7
MCOUNT
BIT6
MCOUNT
BITS
MCOUNT
BIT4
MCOUNT
BIT3
MCOUNT
BIT2
MCOUNT
BIT I
MCOUNT
BITO
DATA RECOVERY
0 0
0 0 1 0 0 0
Test Mode
I = Reset
0= Normal
DAC
BIT6
DAC
BITS
DAC
BIT4
DAC
BIT3
DAC
BIT2
DAC
BITI
DAC
BITO
WINDOW SHIFT
0 0
0 0
1 0
1 0
TDACI
TDACO
WINSHFT
I = Enable
O=Disable
WSDIR
I = Late
0= Earlv
~
~
WS;
WSO
1 0
SarvoResat
I =HiRes
0= Nonnal
W[2
WIT
war
WRPRCMP
I = Enable
o = Disable
~
WET
WBi
PDAC
BIT3
PDAC
BIT2
PDAC
BIT I
PDAC
BITO
ADAC
BIT3
ADAC
BIT2
ADAC
BITI
ADAC
BITO
I\)
0 0
1 1 0 0
WRITE PRECOMP
0 0 0 1 1 0
AGC LEVEL
0 1 0 0 0 1 0 0
~:~~
Servo Qual.
PUMPDWN PUMP UP PHASEDET
TBG
MTP3
I = Bypass I = Enable
I =ON
I =ON
I = Enable
O=OFF
0= Disable
0= Normal 0= Disable
O=OFF
PUMP UP PHASE DET
GAINSHFT DIRWRITE
RDIO
I =ON
I =ON
I = Enable
I =ON
I = Input
O=OFF
0= Disable O=OuinUI
O=OFF
O=OFF
• Denotes SSllnternal test bits. These bits should be sat to 0 in normal operation.
mm.l=lo
O::l~
~
::l N
.I=IoCDI
-.1=10
C":e
...
C _. ~
""t
_
- I~
t/)::r»
(J)
.1=10
CD
......
<
o
en
""t
.1=10
:Ii;
~
en
»
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
REGISTER DESCRIPTION
All transfers are shifted into the serial port LSB first. The
first byte of the transfer is address and instruction
information. The LSB of this byte is the R/W bit which
determines ifthetransfer is a read (1) ora write (0). The
remaining 7-bits determine the internal register to be
accessed. Table 4 provides register mapping
information. The second byte contains the programming
data. In Read mode (R!W=1) the 32P4742 will output
the register contents of the selected address. In Write
mode the device will load the selected register with
data presented on the SOATA pin. At initial power-up.
the contents of the internal registers will be in an
unknown state and they must be programmed prior to
operation. During power down modes. the serial port
remains active and register programming data is
retained.
(continued)
SERIAL INTERFACE OPERATION
The serial interface is a bi-directionalport for reading
and writing programming data from/to the internal
registers of the 32P4742. For data transfers SOEN is
brought high. serial data is presented at the SOATA
pin. and a serial clock is applied to the SCLK pin. After
the SOEN goes high. the first 16 pulses applied to the
SCLK pin will shift the data presented atthe SOATA pin
into an internal shift register on the rising edge of each
clock. An internal counter prevents more than 16 bits
from being shifted into the register. The data in the shift
register is latched when SO EN goes low. Ifless than 16
clock pulses are provided before SOEN goes low. the
data transfer is aborted.
L
SD:J
SDA_T_A_-« ....._A_D_D_R_E_S_S_.B_-B_I_T....JX"'--_D_AT_A_._B_-B_IT_....J>SCLK
FIGURE 18: Serial Port Transfer Format
6-33
I
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
VP
VP
INPUT
VCM
'iNPOi c::>-''--II---l
INPUT
VN
VN
DIFFERENTIAL ANALOG INPUT
(CP, CN, DP, DN)
CMOS INPUT
(pWROfiI, SDEN, SDATA,SCLK)
VP
INPUT
=--1---+
VN
DIFFERENTIAL AMPLIFIER INPUT
(VIA, VIA, IN, TN)
TIL COMPATIBLE CMOS
INPUT WITH PULL-UP
INPUT
FREF INPUT
FIGURE 19(a): Input Structures
6-34
SS132P4742/4742A14746/4746A
Read Channel with
1,7 EN DEC, 4-burst Servo
VP
VP
+----c>
OUTPUT
VN
+---+----c:::> OUTPUT
t---c:> OUTPUT
VN
ANALOG SERVO OUTPUT
DIFFERENTIAL OUTPUT
VP
VP
OUTPUT
'----c:::> OUTPUT
OUTPUT
VN
VN
PECUOPEN EMITTER OUTPUT
CMOS OUTPUT
FIGURE 19(b): Output Structures
6-35
I
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
PIN DESCRIPTION
POWER SUPPLY PINS
NAME
-
TYPE
DESCRIPTION
VPA
Data separator PLL analog power supply pin
VPB
Time base generator PLL analog power supply pin
VPC
VPD
VPD2
VPG
VNA
Internal ECL, CMOS logic power supply pin
TTL buffer I/O digital power supply pin
VNB
Time base generator PLL analog ground pin
VNC
VND
TTL buffer I/O digital ground pin
VNG
Pulse detector, filter, servo analog ground pin
--
WD buffer digital power supply pin
Pulse detector, lilter, servo analog power supply pin
Data separator PLl analog ground pin
Internal ECl, CMOS logic ground pin
INPUT PINS
VIA, VIA
I
AGC AMPLIFIER INPUTS: Differential AGC amplifier input pins.
DP,DN
I
ANALOG INPUTS FOR DATA PATH: Differential analog inputs to data
comparators, lUll-wave rectifier.
CP, CN
I
ANALOG INPUTS FOR CLOCK PATH: Differential analog inputs to the clock
comparator.
PWRON
I
Power Enable: TTL compatible CMOS power control input. A low level CMOS
input enables power to circuitry according to the contents of the PDCR. A high
level CMOS input shuts down all circuitry.
HOLD
I
HOLD CONTROL: TTL compatible CMOS control pin which, when pulled low,
disables the AGC charge pump and holds the AGC amplifier gain at its present
value.
STROBE
I
BURST STROBE: TTL compatible CMOS burst strobe input. A high level TTL
input will enable the servo peak detector to charge one of the burst capacitors.
The falling edge of STROBE increments an internal counter that determines
which burst capacitor will charge onthe next STROBE pulse (reference Figure
7(a), 7(b) for timing.)
RESET
I
RESET CONTROL INPUT: TTL compatible CMOS reset input. A low level
TTL input will discharge the internal servo burst hold capacitors on channels
A-D.
IN,IN
I
FILTER SIGNAL INPUTS: The AGC output signals must be AC coupled into
these pins.
6-36
SSI 32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
INPUT PINS
(continued)
I
REFERENCE FREQUENCY INPUT: Frequency reference input for the time
base generator. FREF should be driven either by a direct coupled TTL signal
or by an AC coupled ECL signal.
I/O
NRZ I/O PORT: TTL compatible CMOS NRZ data port. In Read mode, valid
data is output on these pins with each cycle of RRC. In Write mode, data input
on these pins is clocked into the device by WCLK.
RG
I
READ GATE: TTL compatible CMOS read gate input. A high level TTL input
selects the RD input and enables the Read mode/address detect sequences.
A low level selects the FREF input.
SG
I
SERVO GATE: TTL compatible CMOS servo gate input. A high level TTL
input activates the Servo mode by selecting the servo control registers, the
RDIO pin active in Idle mode, the PPOL pin also active in Idle mode, and the
RTS resistor.
WCLK
I
WRITE CLOCK: TTL compatible CMOS write clock input. Must be synchronous with the Write Data NRZO/1 input. For short cable delays, WCLK may be
connected directly to pin RRC.For long cable delays, WCLK should be
connected to an RRC return line matched to the NRZ data bus line delay.
WG
I
WRITE GATE: TTL compatible CMOS write gate input. A high level input
enables the Write mode.
MTP1,2,3
0
MULTIPLEXED TEST POINTS: Open emitter ECL output test pOints. Internal
test signals are routed to these test points as determined by the CAR and CBR.
Two pull up and down resistors are required to use this pin. They should be
removed during normal operation to reduce power dissipation. (Reference
Table 8)
00,00
0
FILTER DIFFERENTIATED OUTPUTS: Filter differentiated outputs. These
outputs are AC coupled into the CP/CN inputs.
ON,ON
0
FILTER NORMAL OUTPUTS: Filter normal low pass output signals. These
outputs are AC coupled into the DP/DN inputs.
PPOL
0
PULSE POLARITY: Pulse polarity CMOS compatible output. The output is
high when the pulse being qualified is positive and it is low when the pulse
being qualified is negative.
RDIO
0
READ OAT A I/O: Bi-directional TTL compatible CMOS pin. RDIO outputs RD
pulses when in Idle or Servo modes of operation. RDIO is an input when the
ROIO bit is enabled in the CBR.
RRC
0
READ REFERENCE CLOCK: Read clock CMOS compatible output. During
a mode change, no glitches are generated and no more than one lost clock
pulse will occur. When RG goes high, RRC initially remains synchronized to
FOUT. When the Sync Bits are detected, RRC is synchronized to the ORO.
When RG goes low, RRC is synchronized back to the FOUT.
FREF
NRZO/1
OUTPUT PINS
6-37
I
SSt 32P474214742A14746/4746A
Read Channel with
1, 7ENDEC, 4-burst Servo
OUTPUT PINS (continued)
VOA, VOA
0
AGC AMPLIFIER OUTPUT: Differential AGC amplifier output pins. These
outputs are ac coupled into the filter inputs (INIIN).
WD
0
WRITE DATA (32P4742!4746): CMOS encoded write data. The falling edge
of WD represents the data bit. WD is internally synchronized to the FOUT
reference clock. When direct write is active WD is toggled by the signal
presented on the NRZO pin.
WD/WD
0
WRITE DATA (32P4742A14746A): Differential PECLencodedwritedata. This
output format is a bond option. The rising edge of the WD pin represents the
data bit (precomped edge). These are open emitter outputs, and an external
pull-down resistor is required.
ANALOG PINS
A,B,C,D
(32P4742/4742A)
SERVO OUTPUTS: These outputs are processed versions of the voltages
captijred on the servo hold capa,citors. They are referenced to an internally
generated, O.5V baseline.
A-B, C-D, A+B
(32P4746/4746A)
SERVO OUTPUTS: These outputs are processed versions of the voltages
captured on the servo hold capacitors. They are referenced to SREF.
BYP
The AGCintegrating capacitor CA, is connected between BYP and VPG.
TFLTITFLT
PLL LOOP FILTER: These pins are the connection points for the time base
generator loop filter.
DACOUT
DAC VOLTAGE TEST POINT: This test point monitors the outputs of the
internal DACs. The source DAC is selected by programming the two MSBs of
the WSCR register;
DFLTIDFLT
PLL LOOP FILTER: These pins are the connection points for the data
separator loop filter.
lEVEL
An NPN;emitter output that provides a full-wave rectified signal from the DP,
ON inputs. An external capaCitor should be connected from lEVEL to VPG to
set the hysteresis threshold time constant in conjunction with RTS and RTD.
An internal current source provides 60 IlA of pull-down current at this pin.
RR
REFERENCE RESISTOR INPUT: An external 1% resistor is connected from
this ph, to VNA to establish a precise internal reference current for the data
separator and time base generator.
RTS
SERVO TIME CONST~NT RESISTOR INPUT: An external resistor is connectedfrom this pin to LEVEL to establish the hysteresis threshold time
constant when in Servo mode.
. RTD
DATA TIME CONSTANT RESISTOR INPUT: An external resistor is connected from this pin to LEVEL to establish the hysteresis threshold time
constant when not in Servo mode.
6-38
SS132P4742/4742A14746/4746A
Read Channel with
1,7 ENDEC,4-burst Servo
ANALOG PINS
(continued)
RX
REFERENCE RESISTOR INPUT: An external 1% resistor is connected from
this pin to VNG to establish a precise PTAT (proportional to absolute
temperature) reference currentfor the filter. A 1000 pF capacitor should be
.placed in parallel with this resistor.
MAXREF
SERVO REFERENCE: An external voltage output that can be used as the
reference for an external ND converter. This represents the maximum output
voltage for the A, B, C, and D outputs.
SERIAL PORT PINS
SDEN
SERIAL DATA ENABLE: Serial enable CMOS input. Ahigh level input enables
the serial port.
SDATA
SERIAL DATA: Serial data CMOS input. NRZ programming data for the
internal registers is applied to this input.
SCLK
SERIAL CLOCK: Serial clock CMOS input. The clock applied to this pin is
synchronized with the data applied to SDATA.
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, the recommended operating conditions are as follows: 4.5V < POSITIVE
SUPPLY VOLTAGE < 5.5V, O°C < T (ambient) < 70°C, and 25°C < T(junction) < 135°C. Currents flowing into
the chip are positive. Current maximums are currents with the highest absolute value.
ABSOLUTE MAXIMUM RATINGS
Operation beyond the maximum ratings may damage the device
Storage temperature
-65 to 150°
Junction operating temperature
+130°C
Positive supply voltage (Vp)
-0.5 to 7V
Voltage applied to any pin
-0.5V to Vp+0.5V
6-39
I
SSI32P474214742A!4746/4746A
Read Channel with
1,7ENDEC, 4-burst Servo
ELECTRICAL SPECIFICATIONS (continued)
POWER SUPPLY CURRENT AND POWER DISSIPATION
Unless otherwise specified, Ta = 26°C and data rate = max. All test points and outputs are open. The test
points are disabled.
MIN
NOM
MAX
UNIT
PWRON=O
All blocks enabled
85
125
mA
PWR
Power Dissipation
PWRON=O
All blocks enabled
425
690
mW
Sleep Mode Current
PWRON=1
SG, RG, WG, STROBE,
RESET, WClK = 0
All other CMOS inputs = 1
0.5
rnA
Servo Mode Current
PWRON -0
SG= 1
Power Reg. = 14 hex
70
mA
0.8
V
CONDITION
PARAMETER
ICC
VPn
45
DIGITAL INPUTS AND OUTPUTS
nL COMPATIBLE INPUTS
Inputs will float high "1" if left open.
Input low voltage
Vil
Input high voltage
VIH
V
2.0
Input low current
III
Vil =O.4V
-20
~
Input high current
IIH
VIH =.2.4V
-20
~
1.5
V
CMOS COMPATIBLE INPUTS
Schmitt trigger type, do not leave open. Nominal1.0V hysteresis around VPD/2.
Input low voltage
VPC = 5.0 volts
Input high voltage
VPC = 5.0 volts
V
3.5
CMOS COMPATIBLE OUTPUTS
Output low voltage
0.5
IOl = 4.0 mA, VPD = 5.0V
4.5
V
V
Output high voltage
IOH = -4.0 mA, VPD = 5.0V
Rise time
0.8 to 2.0 volts
Cl $; 15 pF
5
ns
Fall time
2.0 to 0.8 volts
Cl $; 15 pF
5
ns
6-40
SSI 32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
FREFINPUT
PARAMETER
CONDITION
MIN
Recommended input level
AC-coupled
1.5
Input resistance
Ref. only, nol measured on ATE
NOM
MAX
UNIT
2.0
Vp-p
11
kU
TEST POINT OUTPUT lEVELS (MTP1, MTP2, MTP3)
Output high level
2610 to VPA
402U to VNA
for reference use only
Output low level
2610 to VPA
402U to VNA
for reference use only
V
VPA-1.0
VPA-1.62
V
PECl OUTPUT lEVELS (WD,WD for 32P4742A)
I 402U to VND
I 402U to VND
Output high level
Output low level
IVPA.1.01
I
I
IVPA -1.601
I
J
V
V
SERIAL PORT
SCLK Data Clock period
Read from Serial Port
140
Write to Serial Port
100
ns
Read from Serial Port
60
ns
Write to Serial Port
40
ns
Read from Serial Port
60
ns
ns
SCLK low time
TCKL
SCLK high time
TCKH
40
ns
Enable to SCLK
TSENS
35
ns
SCLK to disable
TSENH
100
ns
Data set-up time
TDS
15
ns
Data hold time
TDH
15
Write to Serial Port
SDATA tri-state delay TSENDL
SDATA turnaround time
SCLK falls to Valid Data
SDEN low time
TTRN
TDSKEW
ns
50
70
Cload:O;; 15 pF
0
TSL
200
6-41
ns
ns
50
ns
ns
I
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
Ir-----------------~}~------------------~
SDEN
Tc
SCLK
Tds
SDATA
(READ)
----'
SDATA
(WRITE)
FIGURE 18: Serial Port Timing
ELECTRICAL SPECIFICATIONS (continued)
PULSE DETECTOR CHARACTERISTICS
AGC AMPLIFIER
Input signals are AC coupled to VIA/VIA, VOA/VOA outputs are AC coupled to INIIN, and ONION are AC
coupled to DP/DN. A 1000 pF capacitor (CBYP) is connected from BYP to VPG. Unless otherwise specified,
outputs are measured differentially at VOAIVOA, FIN = 8 MHz,and filter boost = 0 dB.
PARAMETER
CONDITION
Input range
Fin
DP-DN voltage
22 ~ VIA ~ 240 mVpp
HOLD = 1, boost = 0 dB
20 ~ VIA ~ 100 mVpp
HOLD = 1, boost = 13 dB
0.85
= 1, DACA = 0000
SG = 1, DACA = 1111
HOLD = 0
I @ BYP = -50 (lA
I @ BYP = +50 (lA
0.85
0.60
MIN
= Fc, 0 dB boost
13 dB boost
DP-DN voltage (servo)
SG
AGC gain
minimum
maximum
Gain sensitivity
BYP voltage change
AGC output total
harmonic distortion
VOA-VOA = 0.75 Vpp
VIA = 100 mVp-p
6-42
NOM
MAX
UNIT
240
mVpp
20
100
mVpp
0.85
1.15
Vpp
1.15
Vpp
1.0
1.15
Vpp
0.75
0.90
Vpp
1.0
VN
33
dBN
1.0
%
22
22
23
VN
28
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-bOrst Servo
AGC AMPLIFIER (continued)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Differential input impedance
WG=low
4.7
6.0
8.4
kQ
WG = high; or Low-Z
100
350
600
Q
WG = low
2.5
3.3
5.0
kQ
WG = high; or Low-Z
150
250
350
Q
Single-ended input impedance
Output offset voltage
Gain = 1.0 to 22
Input noise voltage
Gain
200
=22, VIAIVIA are shorted
10
15
mV
nW-lHz
Bandwidth
Gain = 22, CL S 15 pF
35
MHz
CMRR
Gain = 22, F = 5 MHz
40
dB
PSRR
Gain = 22, Fc = 5MHz
45
Single-ended output resistance
dB
125
275
Q
AGCCONTROL
The input signals are AC coupled into DN/DP,CBYP = 1000 pFto VPA. CT = 10000 pF, RTS = RTD = open.
Decay current
Attack current
VBYP =VPG - 2.3V, OP-ON
Normal decay (ID)
=OV
-3.0
-4.0
-5.0
IJA
Fast Decay mode (IDF)
-0.8
-1.2
-1.6
mA
VBYP = VPG - 2.3V
Normal attack (ICH)
DP-DN = 0.55V
0.13
0.17
0.22
mA
Fast Attack mode (ICHF)
DP-DN = 0.675V
7x ICH
BYP leakage current
HOLD = 0, 1 S Gain s 22
-50
Low-Z duration
WG 1 to 0
Low-Z bit = 0
0.5
Low-Z bit = 1
Fast decay duration
LEVEL pull-down current
1.0
Low-Z bit = 0
0.5
1.0
nA
1.5
jlS
jlS
1.5
2.0
FIN = 6to 18 MHz
IDP-DNI = 0.5
rnA
50
2.0
Low-Z bit = 1
LEVEL output voltage
(with respect to RTD/RTS)
8x ICH 9.6 x ICH
jlS
jlS
0.29
0.33
0.37
VNpp
IDP-DNI = 1.0
0.60
0.67
0.74
VNpp
IDP-DNI = 1.5
0.88
1.0
1.12
VNpp
40
60
80
IJA
Vlevel = VPG - 2.3V
6-43
II
SSI32P4742/4742A/4746/47 46A
Read Channel with
1,7 ENDEC, 4-burst Servo
ELECTRICAL SPECIFICATIONS (continued)
DATA COMPARATOR
The input signais are AC coupled into DP/DN.
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Differential input resistance
WG=O
6.5
9
12.5
Single-ended input resistance
WG=1
200
500
725
kn
n
Threshold (T"Io) accuracy
41 < VTHDAC < 109
0.3 ~ VLEVEL - VRTD ~ 0.75
T"Io = TnDAC x 93%/127
1""/0 + 5
"10
12.5
kQ
0.6
ns
T"Io - 5
CLOCK SECTION
The input signals are AC coupled into CP/CN.
Differential input resistance
Pulse pairing
6.5
9
Data threshold register= 196
and 63
Measured at the falling edge
of RDIO
Data rate "= 16 MbiUs
Fc = 9 MHz, 0 dB boost
VIA = 100mVpp@6 MHz
SERVO CAPTURE CHARACTERISTICS
Unless otherwise specified: a 4 MHz sine wave is AC-coupled into DP/DN inputs; STROBE and RESET
durations are 1.0 J.IS; and DACP is set to "0100" with the Servo Reset bit setto "1".
MAXREF output voltage
ISOURCE = 0 rnA
MAXREF load regulation
ISOURCE = 0 to -4.5 rnA
2.94
A, B, C, 0 output low voltage
ISINK = 0.2 rnA
RESET = 0
0.16x
3.1
0.17 x
3.26
V
40
rnV
0.18 x
V
MAXREF MAXREF MAXREF
+ 0.15
MAXREF-A,B,C,D high voltage
ISOURCE = 0 rnA
0
A, B, C, D.output resistance
ISOURCE/SINK = 0.2 rnA
A, B, C, 0 gain
0.2 Vpp < (DP - ON)
~
1.0 Vpp
0.0 Vpp ~ (DP - ON)
~
0.2 Vpp
0.35 x VPG ~ SREF ~ 0:55 x VPG
A-B, C-D, A+B low voltage
6-44
2.35
VN
2.35
VN
0.4x
VPG
0.55 x
VPG
V
1.0
~
0.2
VPG ·0.75
A-B, C-D, A+B high voltage
50
2.25
0
0.35 x
VPG
SREF input range
SREF input bias current
2.15
V
{1
"
V
0.5
V
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
SERVO CAPTURE CHARACTERISTICS
(continued)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
A-B, C-O gain
0.2 Vpp < (OP - ON) :5 1 Vpp
1.8
2.0
2.2
V/V
A+Bgain
o Vpp:5 (OP - ON) :5 0.2 Vpp
0
0.2 Vpp < (OP - ON) :5 1 Vpp
0.9
o Vpp:5 (OP - ON) :5 0.2 Vpp
0
1.0
2.2
V/V
1.1
V/V
1.1
V/V
A-B, C-O, offset voltage
OP/ON = 0.5 Vpp
Offset = loutput (RESET = 0) output (RESET = 1)1
30
mV
Burst capture time
OP - ON = 1.0 Vpp
Output ~ 95% of final value
1.0
(..LS
Burst reset time
OP - ON = 1.0 Vpp
Output :5 5% of final value
1.0
I1s
RESET on/off delay
From RESET 1.4V crossing
150
ns
A,B,C,Ooffset voltage
OP-ON = 0.5 Vpp, RESET = 1
Offset = difference between
any two channels
60
mV
ROIO pulse width
CL= 15 pF
Measured at 1.5V crossing
10
15
ns
PPOL to ROIO setup time
PPOL riselfall to
ROIO fall measured @ 1.5V
crossing
CL:515pF
8
6-45
ns
II
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
ELECTRICAL SPECIFICATIONS (continued)
PROGRAMMABLE FILTER CHARACTERISTICS
Unless otherwise specified: Rx = 12.1 !
-
::l ~
f-'!.~
c: _. ~
~
,....
t/)::t>
-
O'=: . . .
-en ~
CD
......
<
en
iii;;
......
~
en
~
o
~
>
~
CT
'----t---+I---
0
0
18
(5 ~ z0
w
g; 13
&~
<
60 59 58 57 56 55 54 53 52 51 50 49
ViA
48
B
VIA
2
47
C
MAXREF
BYP
3
46
ROCD'
4
45
0
VNG
5
44
RTD
'PWRON
6
43
RTS
VPC
7
42
VNC
SOATA
8
41
SG
SCLK
9
40
OACOUT
SOEN
10
39
N/C
FREF
11
38
STROBE
MTP3
12
37
~
VPB
13
36
mm
TFLT
14
35
PPOL
m:T
15
34
MTP2
VNB
MTP1
32P4742
54-Lead TQFP
6-59
I
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
...J
~
>
~
a: ~
1.
64 63 62 61
VIA
w
o
Q.
10
0
z
0
~
Z
0
Q.
0
Z
u
Q.
U
60 59 58 57 56 5554 53 52 51
>
W
...J
«
50 49
48
B
VIA
2
47
C
BYP
3
46
MAX REF
HOLD
4
45
D
VNG
5
44
RTD
f5WRON
6
43
RTS
VPC
7
42
VNC
SDATA
8
41
SG
SCLK
9
40
DACOUT
SDEN
10
39
N/C
FREF
11
38
STROBE
MTP3
12
37
~
1'IT5lO
VPB
13
36
TFLT
14
35
PPOL
TITi'
15
34
MTP2
32 33
MTPl
VNB
16 17 18 19 20 21
a:
z z > a: Us: >
~
32P4742A
54-Lead TQFP
6-60
~
f-
...J
LL
0
a:
«
a. a: «
z
>
>
SS132P4742/4742A14746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
lor a static sensitive component.
(Top View)
...J
~ ~
VIA
~ ~
1!;
> c0
II:
18
w
~ ~ ti
D..
c
Z
0
D..
0
Gj
...J
m
+
<
1.
6463 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
C-D
VIA
2
47
A-B
SREF
BVP
3
46
FIC5['D"
4
45
DACOUT
VNG
5
44
RTD
l5WROO'
6
43
RTS
VPC
7
42
VNC
SDATA
8
41
SG
SCLK
9
40
LATCHO
SDEN
10
39
LATCH1
FREF
11
38
STROBE
MTP3
12
37
~
VPB
13
36
'ROlO
TFLT
14
35
PPOL
34
MTP2
32 33
MTP1
TFI:T
VNB
15
16 17
18 19 20 21
Cl
II:
~ ~
c N
D..
> II:
Z
22 23 24 25 26 27 28 29 30 31
~
Z
c
~
Z
> II:
~
...J
~
~
D..
>
~ ~
32P4746
64-Lead TQFP
6-61
!:i
tt
U.
c
>
II:
II:
<
~
I
SSI 32P4742147 42A/4746147 46A
Read Channel with
1,7 ENDEC, 4-burst Servo
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
-J
g~
~ ~
Cl
£;
Q.
>
8
~.
i5 ~
Z
a
Q.
a
Z
0
Q.
0
w
III
-J
«
>
W
+
ilIA
C-D
VIA
2
47
A-B
BYP
3
46
SREF
HOm
4
45
DACOUT
VNG
5
44
RTD
]5WR<5N
6
43
RTS
VPC
7
42
VNC
SDATA
8
41
SG
SCLK
9
40
LATCHO
SDEN
10
39
LATCH1
FREF
11
38
STROBE
MTP3
12
37
RESET
VPB
13
36
lmiO
TFLT
14
35
PPOL
iIU'
15
34
MTP2
32 33
MTP1
VNB
~
~ ~
aQ.
>
~ crIi:lZ
Z
a
z
>
0
cr
cr
:.::
-J
~
'"a ~. ~
>
Q.
32P4746A
64-Lead TQFP
6-62
I-J
,LL
a
« cr
«
cr
Q.
>
~
SSI32P4742/4742A/4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
VOA
~
X
II:
9
8
(!)
++- Z
-'
W
~
?;
a..
>
0
~
0
~
7
6
5
4
3
2
1
0
Z
10
•
a..
Z
0
0
Z
()
a..
()
>
w
-'
0
()
c(
0
u.
0
::2:1
(/)
68 67 66 65 64 63 62 61
60
VC_Ot
59
FOt
ViA
11
VIA
12
58
B
BYP
13
57
C
HOTI5
14
56
MAXREF
VNG
15
55
0
PWRON
16
54
RTO
VPC
17
53
RTS
SOATA
18
52
VNC
SCLK
19
51
SG
SDEN
20
50
DACOUT
FREF
21
49
N/C
MTP3
22
48
STROBE
VPB
23
47
RESET
TFLT
24
46
R1Ji5
if[f
25
45
PPOL
VNB
26
44
MTP2
27 28 29 30 31
(!)
()
II:
Z
~
32 33 34 35 36 37 38 39 40 41
0
0
0
a.. N Na: Z
> a:
Z
Z >
()
II:
II:
'"-'
()
~
N
0
a..
>
~
tThese pins are for SSi test purposes only.
They should be left open in normal use.
32P4742
68-Pin CLCC
6-63
~
~
u.
0
c(
a..
>
II:
II:
42 43
c(
Z
Ii:
> I::2:
I
SSI 32P474214742A!4746/4746A
Read Channel with
1,7 ENDEC, 4-burst Servo
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
++- Z
...J
~
X
0:
9
8
C}
[L
I~
~
>
7
6
5
a
0
4
z
18
0
fa
3
2
1
•
z
a
a..
a
68 67
z
(.)
[L
(.)
w
>
w
...J
0(.)
[L
32 33 34 35 36 37
N 0:
~ aZ
z z >
0:
(.)
0:
0:
:.:
...J
(.)
N
C}
a[L :;:
:;: >
t These pins are for SSi test purposes only.
They should be left open in normal use.
32P4742A
58-Pin CLCC
6-64
38 39 40 41
42 43
~
> ~
!:i
u.
a
0:
0:
0
~
0
~
8
7
6
5
4
3
2
1
II:
C
Z
VOA
VIA
•
Z
C
0-
C
68 67
Z
0
a.
0
W
a!
w
-'
«
>
+
++- Z
0 0
0
::;:1
LL-
CI)
C
66 65 64 63 62 61
VIA
60
VC_Ot
59
FOt
58
C-O
BYP
13
57
A-B
mm
14
56
SREF
VNG
15
55
OACQUT
~
16
54
RTO
VPC
17
53
RTS
SOATA
18
52
VNC
SCLK
19
51
SG
SOEN
20
50
LATCHO
FREF
21
49
LATCH1
MTP3
22
48
STROBE
VPB
23
47
11ESET
TFLT
24
46
ROIO
TFLT
25
45
PPOL
VNB
26
44
MTP2
27 28 29 30 31
(!j
II:
0
Z
~
c
0-
>
N
II:
Z
32 33 34 35 36 37
0
N
c
Z
a: >
z
0
:.:
a:
0
II:
-'
::
'" ~
>
C
0-
t These pins are for SSi test purposes only.
They should be left open in normal use.
32P4746
68-Pin CLCC
6-65
38 39 40 41
42 43
~
«
Z c::
> ~
~
LLc
~
>
II:
II:
I
SSI32P474214742A14746/4746A
Read Channel with
1,7 ENDEC; 4-bursfServo
PACKAGE PIN DESIGNATIONS
CAUTiON: Us&handling procedures necessary
for a static sensitive component
(Top View)
VOA
98765432
10
68 67
•
66 65 64 63 62 61
60
VC_Ot
ViA
11
VIA
12
58
G-O
BYP
13
57
A-B
'Rm]j
14
66
SREF
VNG
15
55
OACOUT
~
16
54
RTO
VPC
t7
53
RTS
SOATA
18
52
VNC
59
FOt
SCU<
19
51
SG
SOEN
20
50
LATCHO
FREF
21
49
LATCH1
MTP3
22
48
STROBE
VPB
23
47
'RESET
TFlT
24
46
mo
'fF['f
25
45
PPOl
VNB
26
44
MTP2
27 28 29 30 31
00"'"
32 33 34 35 36 37 38 39 40 41
0
42 43
0
3:~~~~
z z
tThese pins are for SSi test purposes only.
They should be left open in normal use.
32P4746A
68-Pln CLCC
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in speCifications at any time without notice. Accordingly, the reader is cautioned to verity that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1993 Silicon Systems, Inc.
6-66
1293
SSI32P4782
80 Mbitls Read Channel Device
i;' '~QI a4§n tiii t.",
January 1994
DESCRIPTION
The 32P4782 device is a high performance BiCMOS
single chip read channel IC that, together with the
32D4680 timebase generator, contains all the functions
needed to implement a complete zoned recording read
channel for hard disk drive systems. Functional blocks
include the pulse detector, programmable filter, servo
functions, data synchronizer, window shift, write
precompand 1,7RLLENDEC. Data rates from 25to 80
Mbills can be programmed using an internal DAC
whose reference current is set by a single external
resistor.
The programmable functions of the 32P4782 device
are controlled through a bi-directional serial port and
banks of internal registers.This allows zoned recording
applications to be supported without changing external
component values from zone to zone.
The 32P4782 utilizes an advanced BiCMOS process
technology along with advanced circuit design
techniques which result in a high performance device
with low power consumption.
FEATURES
GENERAL
• Programmable data rate, Internal DAC
controlled: 25 to 80 Mblt/s
• Complete zoned recording application
support
• Low power operation (550 mW typical @ 5V)
• BI-directlonal serial port for register access
• Register programmable power management
(Sleep mode <5 mW)
• Power supply range (4.5 to 5.5 volts)
• Small footprint 64-lead TQFP package
AGC
• LowZ and fast Decay timing Independently set
by two external resistors
• Fast Decay current set by an external resistor
• Low Drift AGC Hold circuitry
• Separate Read and Servo AGC levels (4-bit
DAC)
• Temperature compensated, exponential
control AGC
• Wide bandwidth, high precision full-wave
rectifier
• Wide bandwidth, high precision multirate
charge pump
PULSE DETECTOR
• DP, ON pins LowZ switch for rapid transient
recovery
• Pulse qualification circuitry can be configured
via serial port to support one of three modes of
operation:
- bit by bit qualification with polarity check
- bit by bit qualification without polarity check
- analog Viterbi detector
• Independent control of positive and negative
thresholds levels in the data comparators
• CMOS RDIO signal output for servo timing
support
• 0.3 ns max. pulse pairing with sine wave input
guaranteed by design
SERVO CAPTURE
• 4-burst servo capture with A, B, C and 0
outputs.
• Separate full wave rectifier connected to filter
differentiated output.
• Separate registers for filter cutOff, AGC level
and qualification threshold during Servo mode
(continued)
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
0194
6-67
I
SSI32P4782
80 Mbitls Read Channel Device
FEATURES (continued)
PROGRAMMABLE FILTER
•
•
•
•
•
•
•
•
•
Cutoff frequency programmable viCi serial port:
- 9 to 27 MHz (3 to 9 MHz at degraded specs for
fiHering in Servo mode)
Advanced architecture minimizes fiRer settling
characteristics whefl switching between Servo
mode and Oata mode
Programmable boost/equalization range of 0 to
13dB
Programmable Group Delay Equalization with
asymmetric zeroes control
.
Matched normal and differentiated outputs
±10% Fc accuracy over operating temperature
and supply ranges
±2% maximum group delay variation (SSOO ps @
Ic", 27 MHz)
Less than 1% total harmonic distortion
No external filter components required
DATA SEPARATOR
High performance dual-bit NRZ interface
• Integrated 1,7 RLL Encoder Decoder
• Fast acquisition phase lock loop with zero phase
restart technique
• Fully integrated data separator
•
•
- no external delay lines or active components are
required .
. .
- no external active PLLcomponents are required
Programmable decode window symmetry control
via serial port
- window shift control ±350/0 (3-bit)
- delayed read data and VCO clock monitor points
Programmable write precompensation (3-bit) .
- independent control of three precompensation
levelS .
The target specification is intended as an initial disclosure of specification goals for the product The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless egreed to in writing.
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FIGURE 1: Block Diaaram (Front-end)
gl\)
SSI32P4782
80 Mbitls Read Channel Device
6'
C
>410M
%
u
as
~
E
I!!
Cl
as
C
~
g
QM
OM
iii
N
w
a:
;:)
(!)
iL
V.lllas
~l::>S
N30S
1!
i!i
~
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
6-70
SSI32P4782
80 Mbitls Read Channel Device
PACKAGE PIN DESIGNATIONS
(Top View)
11.
~
~
0
!t
::;:
11.
>
III
~~~~~~
Z
0
2;
Z
0
~ ;:2
t'; In 11.
til
"
11.
PKC
VIAP
VIAN
2
47
PKD
AGCDEl
3
46
VPA2
VNA2
WRDEl
4
45
PWRON
5
44
RDIO
SDEN
6
43
VNS
SDATA
7
42
LEVElP
SClK
8
41
VRC
VPD2
9
40
LEVELN
VND2
10
39
I'Wrn
FlT
SG
11
38
WG
12
37
FlTO
RG
13
36
FlT1
VNDIO
14
35
m
VPDIO
15
34
VPA3
VNA3
RClK
z
u.
~ ~ ~ a:W
~ z z u. u.
"
..J
~ ~ ~
0 z0
~ >
§
u.
W
~
0
'"
i>
i
a:
a:
64-Lead TQFP
CAUTION:
Use handling procedures necessary
for a static sensitive component.
Target Specification: The target specification is inlended as an initial disclosure of specification goals for the product. The specifications
are based on design goals, subject to change and are not guaranleed. Silicon Systems assumes no obligation regarding future manufacture
unless agreed 10 in writing.
No responsibility is assumed bY Silicon Syslems for use of this product nor for any infringements of palents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Syslems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon SySlems, Inc., 14351 Myford Road, TUstin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
0194
©1993 Silicon Systems, Inc.
I
Notes:
6-72
_'{. .
Abridged Version
JiJkon~rJfonJ®·
SSI32P4901
PRML Read Channel with
PR4, 8/9 ENDEC, FWR Servo
A TDK Group Company
1mPh' ni; mt., i' ,S" t" ;.
January 1994
GENERAL DESCRIPTION
FEATURES
The SSI32P4901 is a high performance BiCMOS read
channellC that provides all of the functions needed to
implement an entire Partial Response Class 4 (PR4)
read channel for zoned recording hard disk drive
systems with data rates from 24 to 72 Mbit/s.
GENERAL:
Register programmable data rates from 24 to
72 Mbitls
Sampled data read channel with Vlterbl
qualification
Programmable flHer for PR4 equalization
Three tap transversal filter for adaptive PR4
equalization
8/9 GCR ENDEC
Data ScramblerlDescrambler
Functional blocks include AGC, programmable filter,
adaptive transversal filter, Viterbi qualifier, 8/9 GCR
ENDEC, data synchronizer, time base generator, and
FWR servo. Programmable functions such as data
rate, filter cutoff, filter boost, etc. are controlled by
writing to the serial port registers so no external
component changes are required to change zones.
Programmable write precompensatlon
Low operating power (O.75W typical at 5V)
The SSI 32P4901 utilizes an advanced BiCMOS
process technology along with advanced circuit design
techniques which result in high performance devices
with low power consumption.
Register programmable power management
«5 mW Power Down mode)
(continued)
The part requires a single +5V power supply and is
available in a 100-Lead TQFP package.
I
BLOCK DIAGRAM
...
-
PERR
,-==-r--..,NUP
IYPS
IYP
NRZG-1
"""
"""'" ,L_---.-_-'
SO"
.......,
..
$B.""
SEIIIlIIT
.
......
WG
.
,
~~
0194
6-73
:
a~ II~
SSI32P4901
PRML Read Channel with
PR4, 8/9 EN DEC, FWR Servo
FEATURES (continued)
TIME BASE GENERATOR:
Dual-bit and byte wide bi-directional NRZ data
interfaces
Better than 1% frequency resolution
Serial interface port for access to internal program
storage registers
Independent M and N divide-by registers
Single power supply (5V ± 10%)
Up to 81 MHz frequency output
No active external components required
DATA SEPARATOR:
Small footprint 1OO-pin TQFP package
Fully integrated data separator includes data
synchronizer and 8/9 GCR ENDEC
AUTOMATIC GAIN CONTROL:
Dual mode AGC, analog during acquisition,
sampled during read data
Register programmable to 72 Mbit/s operation
Separate AGC level storage pins for data and
servo
Decision directed clock recovery from data
samples
Dual rate attack and decay charge pump for rapid
AGC recovery
Adaptive (+) and (-) clock recovery thresholds for
use with asymmetrical amplitude signals (e.g. from
MR heads)
Fast Acquisition, sampled data phase lock loop
Programmable, symmetric, charge pump currents
during read data
Programmable damping ratio for data
synchronizer Pll is constant for all data rates
Charge pump currents track programmable data
rate
Data scrambler/descrambler to reduce fixed
pattern effects
low drift AGC hold circuitry
low Z input switch
Dual-bit and byte wide NRZ data interfaces
AGC hold, fast recovery, and AGC input
impedance control signals
Time base tracking, programmable write
precompensation
Wide bandwidth, precision full-wave rectifier
Differential PECl write data output
Integrated sync byte detection
FILTER/EQUALIZER:
Programmable, 7-pole, continuous time filter
provides:
Hard and soft sector operation
SERVO:
• Channel filter and pulse slimming equalization
for equalization to PR4
Wide bandwidth, precision full-wave rectifier
Buffered FWR analog servo output with selectable
reference voltage
• Programmable cutoff frequency from 8 to 24
MHz
• Programmable boost /equalization of 0 to 13 dB
Separate, automatically selected, registers for
servo Fc, boost, and threshold
• ±0.5 ns group delay variation from 0.3 Fc to Fc,
with Fc =24 MHz
Compatible with SSI 32H6521 Embedded Servo
Controller
• Minimizes size and power
• low Z input switch
Three tap self adapting transversal filter for fine
equalization to PR4
No external components required
PULSE QUALIFICATION:
Sampled Viterbi qualification of signal equalized to
PR4
Dual level pulse qualifier for servo reads
FUNCTIONAL DESCRIPTION
The SSI 32P4901 implements a complete high
performance PR4 read channel, including an AGC,
programmable filter/equalizer, adaptive transversal
filter, Viterbi pulse qualifier, time base generator, data
separator with 8,9 ENDEC and scrambler/descrambler,
and FWR servo, that supports data rates up to 72 Mbitls.
A serial port is provided to write control data to the 16
internal program storage registers.
6-74
SSI32P4901
PRML Read Channel with
PR4, 8/9 ENDEC, FWR Servo
AGC CIRCUIT DESCRIPTION
The automatic gain control (AGC) circuit is used to
maintain a constant signal amplitude at the input of the
pulse detector while the input to the amplifier varies.
The circuit consists of a loop of circuit blocks that
include the AGC amplifier and charge pump, the
programmable continuous time filter, and the precision
wide band full wave rectifier. Depending on whether
the read is of servo or data type, the specific blocks
utilized in the loop are slightly different. Both loop paths
are fully differential to minimize susceptibility to noise.
During servo reads the loop consists of the AGC
amplifier with a continuous dual rate charge pump, the
programmable continuous time filter, and the precision
wide band full wave rectifier. The gain of the AGC
amplifier is controlled by the voltage stored on the
BYPS hold capacitor (C ByPS)' The dual rate charge
pump drives CByPS with currents that drive the differential
voltage at DP/DN to 1.27 Vppd. Attack currents lower
the V ByPS which reduces the amplifier gain. The dual
rate attack charge pump is included for fast transient
recovery. At maximum data rate, the normal AGC
attack current is 180 !lAo When the signal exceeds
125% of the nominal signal level, the attack current is
increased by a factor of 7. The nominal decay current
at maximum data rate is 1 !lA, and increases by 8
times when the FASTREC input is high. In this mode,
transients that produce low gain will recover more
rapidly with the Fast Decay current, while transients
that produce high gain will put the circuit in the fast
attack Recovery mode.
°
For data reads, the loop described above is used
during address mark detection and until the data
synchronizer is locked to the incoming VCO preamble,
except that the BYP hold capacitor (C ByP ) is now used.
After this point, the loop is switched to include the AGC
amplifier with a sampled dual rate charge pump, the
programmable continuous time filter, full wave rectifier,
arid the sampling 3-tap adaptive equalizer to more
accurately control the signal amplitude into the Viterbi
qualifier. In this sampled AGC mode, a symmetrical
attack and decay charge pump is used. The "1" sample
amplitudes are sampled and held and compared to a
threshold to generate the error current. The maximum
charge pump current value can be programmed from
the Sample Loop Control Register to 0, 20, 40, or 60
!lAo
To optimize recovery for constant density recording,
both of the AGC charge pumps' currents track the data
rate value loaded in the Data Rate Register.
6-75
For maximum application flexibility, all AGC mode
control inputs are designed to be externally controlled.
When the LOWZ input is high, Low-Z mode is activated.
In the Low-Z mode, the AGC amplifier input impedance
is reduced to allow quick recovery of the AGC amplifier
input AC coupling capacitors. This mode should be
activated during and for a short time after a write
operation.
When the HOLD input is low, the dual rate attack
charge pumps are disabled. This de-activates the AGC
loop. The AGC amplifier gain will be held constant at a
level set by the voltage at the BYP or BYPS pins.
In most applications, the BYP and BYPS pin voltages
are stored on external capacitors. In applications where
AGC action is not desired, the BYP and BYPS voltages
can be set by resistor divider networks connected from
VPA to VRC. If programmable gain is desired, the
resistor network could be driven by a current DAC.
PULSE QUALIFICATION CIRCUIT DESCRIPTIONS
This device utilizes two different types of pulse
qualification, one primarily for servo reads and the
other for data reads.
Dual Level Qualifier
During servo reads (SG high) a dual level type of pulse
qualifier is used. The level qualification thresholds are
set by a 7-bit DAC which is controlled by the Servo
Level Threshold Register. The register value is relative
to the peak voltage at the output of the continuous time
filter, and the DAC is referenced to a fixed internal
reference voltage. The positive and negative thresholds
are equal in magnitude. The state of the adaptive
threshold level enable (ALE) bit in the WPIL T Register
does not affect this DAC's reference. The RDS and the
PPOL outputs of the level qualifier indicate a qualified
servo pulse and the polarity of the pulse, respectively.
In Data Read mode (RG high), the same dual level
qualifier as was used for servo reads, is used for
Address Mark Detection and for ensuring pulse polarity
changes during VCO sync field counting. It's qualification
thresholds are set by a 7 -bit DAC which is controlled by
or the Data Level Threshold Register. The register
value is relative to the peak voltage at output of the
continuous time filter and the DAC is referenced to an
fixed internal reference voltage. The positive and
negative thresholds are equal in magnitude. The state
of the adaptive threshold level enable (ALE) bit in the
WPIL T Register does not affect the DAC's reference
until the sync field count has been achieved. The RDS
I
•
SSI32P4901
PRML Read Channel with
PR4, 8/9 EN DEC, FWR Servo
Dual Level Qualifier (continued)
and the PPOL outputs of the level qualifier are not
active in Data Read mode.
Viterbl Qualifier
The second type of pulse qualification, the viterbi
qualifier, is only used during Data Read mode after the
sync field count has been achieved. The viterbi qualifier
has two significant blocks, one that feeds the other.
The first block is the sampled pulse detector and the
second is the survival sequence register.
The sampled pulse detector performs the pulse
acquisition/detection in the sampled domain. It aquires
pulses by comparing the code clock sampled level of
the analog waveform to the positive and negative
thresholds established by the programmable viterbi
threshold window. The viterbi threshold window is
defined to be the difference between the positive and
negative threshold levels. The threshold window, Vth,
is set by a 7-bit DAC which is controlled by the Viterbi
Detector Control Register. While the window size is
fixed by the programmed Vth value, the actual positive
and negative thresholds track the most positive and the
most negative samples of the equalized input signal.
For example, the Viterbi positive Signal threshold, Vpt
=Vpeak (+) max ifthe previous detected level was (+).
ViterbB. +th
Threshold
Window
-th
If the previous detect level was (-), Vpt =Vpeak(-)max
+ Vth, where Vpeak (-) max is the maximum amplitude
of the previously detected negative Signal. Normally
Vth is set to equal Vpeak (approx. 500 mV).
After the pulses have been detected they must be
further qualified by the survival sequence registers and
aSSOCiated logic. This logic guarantees that for
sequential pulses of· the same polarity within the
maximum run length, only the latest is qualified. By
definition, this is the pulse of greatest amplitude.
The viterbi qualifier is implemented as two parallel
qualifiers that operate on interleaved samples. Each
qualifier has a survival sequence register length of 5.
PROGRAMMABLE FILTER CIRCUIT DESCRIPTION
The on-chip, continuous time, low pass filter has register
programmable cutoff and boost settings, and provides
both normal and differentiated outputs. It is a 7th order
filter that provides a 0.05° phase equiripple response.
The group delay is relatively constant up to twice the
cutoff frequency. For pulse slimming two zero
programmable boost equalization is provided with no
degradation to the group delay performance. The
differentiated output is created by a Single-pole, singlezero differentiator. Both the boost and the filter cutoff
frequency are programmed through internal7-bit DACs,
fL--------.>."".--~----".__---.~~---_I__If__--->-
+ pulse detect ~'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....J~
.....JnL-___---'nL-_____
- pulse detect _ _ _ _ _ _ _ _ _ _ _ _
--
.....-
For sequential pulses of the
same polarity, the latest is
selected by the survival sequence
register logic since it is always
of greater magnitude.
Viterbi detector
output
FIGURE 1: Viterbl Detection
6-76
SSI32P4901
PRML Read Channel with
PR4, 8/9 ENDEC, FWR Servo
accessed via the serial port logic. The nominal boost
range at the cutoff frequency is 0 to 13 dB and is
controlled by the Data Boost Register or the Servo
Boost Registerin the Servo mode. The cutoff frequency,
Fc is variable from 3 to 24 MHz and controlled by the
Data Cutoff Register or Servo Cutoff Register in the
Servo mode. The cutoff and boost values for Servo
reads are automatically switched when Servo mode is
entered.
The current reference forthe filter DACs is set using a
single 12.1 K resistor, from the VRX pin to ground. The
voltage at VRX is proportional-to-absolute-temperature
(PTAT).
ADAPTIVE EQUALIZER CIRCUIT DESCRIPTION
Upto 7 dB of cosine equalization for fine shaping of the
incoming read signaltothe PR4 waveshape is provided
by a 3 tap, sampled analog, transversal filter wit.h ~n
adaptive multiplier coefficient. The same multiplier
coefficient (k m) is used for both of the outside taps. The
value of k is adjusted to force "zero" samples to zero
volts. A spmecial equalizer training pattern, located after
the VCO sync field in the sector format, is used to
provide an optimum signal forthe equalizerto adaptto.
The adaptive property of the equalizer is enabled or
disabled by the AEE bit in the Sample Loop Register.
If the adaptive property is enabled, whether adaptation
occurs only during the training pattern or both during
the training pattern and the user data is controlled by
the AED bit in the Sample Loop Register.
TIME BASE GENERATOR CIRCUIT DESCRIPTION
The time base generator (TBG) is a PLL based circuit,
that provides a programmable reference frequency to
the data separator for constant density recording
applications. This time base generatoroutputfrequency
can be programmed with a better than 1% accuracy via
the M, N and DR Registers. The TBG output frequency,
Fout, should be programmed as close as possible to
((9/8) • NRZ Data Rate). The time base also supplies
the timing reference for write precompensation so that
the precompensation tracks the reference time base
period.
The time base generator requires an external passive
loop filterto control its PLL locking characteristics. This
filter is fully-differential and balanced in orderto reduce
the effects of Common mode noise.
In Read, Write and Idle modes, the programmable time
base generator is used to provide a stable reference
frequency for the data separator. In the Write and Idle
modes, the Time Base Generatoroutput, when selected
by the Control Test Mode Register, can be monitored
atthe TPA+ and TPA-test pins. In the Read mode, the
TBG output should not be selected for output on the
test pins so that the possibility of jitter in the data
separator PLL is minimized.
x----r~
km
'----_ yn = km Xn + Xn·1 + km Xn·2
km coefficient adapts to force '0' samples to OV.
FIGURE 2: 3-Tap Adaptive Equalizer
6-77
I
SSI32P4901
PRML Read Channel with
PR4, 8/9 ENDEC, FWR Servo
TIME BASE GENERATOR CIRCUIT DESCRIPTION
(continued)
The reference frequency is programmed using the M
and N registers of the time base generatorvia the serial
port, and is related to the external reference clock
input, FREF, as follows:
FTBG = FREF [(M + 1) + (N + 1)]
The M and N values should be chosen with the
consideration of phase detector update rate and the
external passive loop filter design. The Data Rate
Register must be set to the correct VCO center
frequency. The time base generator PLL responds to
any changes to the M and N registers, only afterthe DR
register is updated.
The DR register value, directly affects the following:
- center frequency of the time base generator
VCO,
- center frequency of the data separator VCO,
- phase detector gain of the time base generator
phase detector,
- phase detector gain of the data separator phase
detector,
- write precompensation
The reference current for the DR DAC is set by an
external resistor, RR, connected between the GND
and RR pins.
RR
Sampled Read Data
from Adaptive Equalizer
= 12.1 kn
DATA SEPARATOR CIRCUIT DESCRIPTION
The Data Separator circuit provides complete encoding,
decoding, and synchronization for 8/9 (0,4,4) GCR
data. In Data Read mode, the circuit performs address
mark detect, clock recovery ,code word synchronization,
decoding, sync byte detection, descrambling, and NRZ
interface conversion. In the Write mode, the circuit
generates address marks, generates the VCO sync
field, scrambles and converts the NRZ data into 8/9
(0,4,4) GCR format, precodes the data, and performs
write precompensation.
The circuit consists of five major functional blocks; the
data synchronizer, 8/9 ENDEC, NRZ scrambler/
descrambler, NRZ interface, and write precompensation.
Data Synchronizer
The data synchronizer uses a fully integrated, fast
acquisition, PLL to perform two main functions.
The first of these functions is used in Data Read mode
to recover the code rate clock from the incoming read
data. The second is used in Write mode to generate a
code rate clock that is used to encode and precode
NRZ data to form the write data (WD, WD) outputs. To
achieve these two functions, the data synchronizer
PLL uses two separate phase detectors to drive the
loop. A decision-directed phase detector is used in the
Read mode and phase-frequency detector is used in
the Idle, Servo, and Write modes.
In the Read mode the deCision-directed timing recovery
updates the PLL by comparing amplitudes of adjacent
"one" samples or comparing the "zero" sample
magnitude to ground for the entire sample period. The
determination of whether a sample is a "one" or a
"zero" is performed by a dedicated, Dual mode, threshold
KDS
DSClK
Ref.rence Frequency
from Time Base Generator
V
FIGURE 3: Data Synchronizer Phase Locked Loop
6-78
SSI32P4901
PRML Read Channel with
PR4, 8/9 ENDEC,FWR Servo
comparator. This comparator's threshold levels are
determined by the value, Lth, programmed in the Data
Threshold Register. The fixed level threshold before
the sync field count (SFC) has been achieved will be
1.27times the threshold level after SFC since this is the
ratio ofthe peak signalto the sampled WPIL T Register.
EN DEC
The ENDEC implements an 8/9 (0,4,4) Group Coded
Recording (GCR) algorithm. The code has a minimum
of no zeros between ones and a maximum of four zeros
between ones for the interleaved samples. During
write operations the encoder portion of the ENDEC
converts 8 bit parallel, scrambled or nonscrambled,
data to 9 bit parallel code words that are then converted
to serial format. In data read operation, after the code
word boundry has been detected, the decoder portion
of the ENDEC converts 9 bit parallel, viterbi qualified,
data to 8 bit NRZ format.
The adaptive reference allows the specification of the
threshold value to be a percentage of an averaged
peak value. When Adaptive mode is selected, the fixed
thresholds are used until the sync field count (SFC) has
been reached, then the adaptive levels are internally
enabled. The time constant of the single pole filter that
controls the rate of adaptation, is programmable by bits
TC3-1 in the WPIL T Register.
Scrambler/Descrambler
The scrambler/descramblercircuit is provided to reduce
fixed pattern effects on the channel's performance. It is
enabled or disabled by bit 2 of the Control Operating
Register. In Write mode, if enabled, the circuit scrambles
the 8 bit internal NRZ data before passing it to the
encoder. Only user data, i.e., the NRZ data following
the sync byte, is scrambled. In Data Read mode, only
the decoded NRZ data after the sync byte is
descrambled. The scrambler polynomial is:
In the Write and Idle modes the non-harmonic phasefrequency detector is continuously enabled, thus
maintaining both phase and frequency lock to the time
base generator's VCO output signal, FTBG • The polarity
and width of the detector's output current pulses
correspond to the direction and magnitude ofthe phase
error.
The two phase detectors' outputs are muxed into a
single differential charge pump which drives the loop
filter directly. The loop filter requires an external
capacitor. The loop damping ratio is programmed by
bits 6-0 in the Damping Ratio Control Register. The
programmed damping ratio is independent of data rate.
H(X)= 1 <8l X7 <8l X10.
ReLK
DBl
DBO
_ _ _ _ _~A
bit 6
X
bit 4
X
bit 2
X
bit 0
X
X
bit 0
bit 6
Read Mode-Dual Bit
WCLK
DBl
DBO
-------<
bit 6
bit 4
X
bit 2
X
bit 6
X
bit 4
Write Mode-Dual Bit
ReLK
~~_ _ _ _ _ _ _~
/
"-
byte 1 _ _ __
NRZO-7------<~_ _ _ _ _ _----"=-=_ _ _ _ _~ '--~::...;..
byte 0
X
Read Mode-Byte Wide
/
"-
NRZO-7------<~_ _ _ _ _ _-----'"'.::..::..
byte'O _ _ _ _ _~ '---.=!..::....:...
byte 1 _ _ __
X
Write Mode-Byte Wide
FIGURE 4: RCLK, WCLK VS. NRZ Data
6-79
I
SSI32P4901
PRMlRead Channel with
PR4, 8/9 ENDEC,FWR Servo
NRZ Interface
detected. The first non-zero data presented will be the
sync byte (96H). The NRZ interface is at a high
impedance state when not in Data Read mode. In ByteWide mode, an even parity bit, NRZP, is generated for
each output byte.
The NRZ interface circuit provides the ability to interface
with either a dual bit or Byte wide controller. The NRZ
interface type is specified by the programming of bit 4
of the Control Operating Register. If byte Wide mode is
selected, the circuit does not reformat the data before
passing it to and from the internal 8 bit bus. If Dual Bit
mode is selected, the NRZ interface circuitconvertsthe
external dual bit bus to the internal 8 bit bus. Only the
selected NRZ interface is enabled and the other can be
left floating. Both the byte wide and dual bit interfaces
define the most significant bit of the interface as the
most significant bit of the data and the dual bit interface
defines the first pair clocked in or out as the most
significant pair.
Write Precompensation
The write precompensation circuitry is provided to
compensate for media bit shift caused by magnetic
nonlinearities. The circuit recognizes specific write
data patterns and can add delays in the time position
of write data bits to counteract the magnetic nonlinearity
effect. The magnitude of the time shift, WPC, is
programmable via the Write Precomp Register and is
made proportional to the time base generator's VCO
period (i.e., data rate). The circuit performs write
precompensation only on the second of two consecutive
"ones" and only shifts in the late direction. If more than
two consecutive "ones" are written, all but the first are
precompensated in the late direction.
Forboth byte wide and dual bit operation, the NRZwrite
data is latched by the 32P4901 on the rising edge of the
WCLK input. The WCLK frequency must be appropriate
forthe data rate chosen or else overflow/underflow will
occur. It is recommended that WCLK be connected to
RCLK to prevent this from occurring. In Byte-Wide
mode, as each NRZ byte is input to the 32P4901, its
parity is checked against the controller supplied parity
bit NRZP. If an error is detected, the PERR output pin
goes high and remains high until WG goes low.
SERVO CIRCUIT DESCRIPTION
Embedded servo capture is provided with a buffered
full-wave rectified (FWR) output. The differential signal
across the DP/DN inputs is applied to a full-wave
rectifier. The output signal of the rectifier is the rectified
servo burst signal, level-shifted above SREF (which is
a bandgap reference from VPA1). The output at the
SEROUT pin is selectable between the FWR output
and two references, SREF and SREF + 200 mV. When
the SG is high (active) the FWR output is selected for
In Data Read mode, the NRZ data will be presented to
the controller near the falling edge of RCLK so that it
can be latched by the controller on the rising edge of
RCLK. When RG goes high, the selected NRZ interface
will output low data until the sync byte has been
Burst A
Burst C
~
Burst B
AGe
Burst D
SG
SELVRC ~
don't care when SG=1
SREF + 200mV
SEROUT~~
SREF
assume resistive only loading
at output.
FIGURE 5: Servo Function Diagram
6-80
SSI32P4901
PRML Read Channel with
PR4, 8/9 EN DEC, FWR Servo
+ Threshold
-( +LSth)
OP/ON
_
.....(-LSth)
- Threshold
PPOL
FIGURE 6: RDS and PPOL vs. DP/DN Relationship
the SEROUT pin. When SG is low (i.e., during the data
field) then the SEROUT pin is selected between SREF
and SREF + 200 mV, depending on the input at
SELVRC.
The dual level pulse qualifier outputs RDS and PPOL
are enabled when the servo gate input (SG) goes high
and provide the indication of a qualified servo pulse
and the polarity of the pulse, respectively.
SG.
SEI.VBQ
S[;BQUI
1
1
FWR Output
1
0
FWR Output
0
1
SREF
0
0
SREF +200 mV
SERIAL PORT CIRCUIT DESCRIPTION
The serial port interface is used to program the
32P4901's sixteen internal registers. The serial port is
enabled for data transfer when the Serial Data Enable
(SDEN) pin is high (0).
When SDEN is high, the data presented to the Serial
Data (SDATA) pin will be latched into the 32P4901 on
each rising edge of the Serial Clock (SCLK). Rising
edges of SCLK should only occur when the desired bit
of address ordata is being presented on the serial data
line. Serial data transmissions must occur in 16-bit
packets. If more than 16 rising edges of SCLK are
6-81
received during the time that SDEN is high, the additional
SCLK and SDATA information will be ignored. During
a serial data transmission, if SDEN is switched low
before 16 SCLK pulses are received, that serial
transmission will be aborted. For all valid transmissions,
the data is latched into the internal register on the falling
edge of SDEN.
Each 16 bit transmission consists of 8 address bits first,
and then the 8 data bits. The address bits select the
internal register to be written to. The address and data
fields are input LSB first, MSB last, where LSB is
defined as Bit O. The four MSB address bits are
reserved for other types of devices using the SSI serial
port protocol and must be set to zero when addressing
the 32P4901. Figure 7 shows the serial interface timing
diagram.
I
SSI32P4901
PRML Read Channel with
PR4, 8/9 ENDEC, FWR Servo
SDEN
SCLK
SDATA
FIGURE 7: Serial Interface Timing
DESCRIPTION OF OPERATING MODES
The fundamental Operating modes of the 32P4901 are
controlled by the SERVO GATE (SG), READ GATE
(RG),and WRITE GATE (WG) input pins.Theexc~usive
assertion of any these inputs causes the device to
enter that mode. If none of these Inputs is asserted, the
device is in the IDLE mode. If more than one of the
inputs is asserted, the mode is determined by the
following hierarchy: SG overrides RGwhich overrides
WG. The mode that is overriding takes effect
immediately.
RG and SG are asynchronous inputs and may be
initiated or terminated at any position onthe disk. WG
is also an asynchronous input, but should no~e
terminated prior to the last output write data (WDIWD)
pulse.
IDLE MODE OPERATION
If SG, RG, and WG are not active, the 32P4901 is in Idle
mode. When in Idle mode, the Time Base Generator
and the Data Separator PLL are running and the Data
Separator PLL is phase-frequency locked to the TBG
VCO output. The AGC, continuous time filter, and
pulse qualifiers are active but the outputs of the pulse
qualifiers are disabled. The continuous time filter is
using its programmed values for cutoff frequency and
boost determined by the Data mode registers.
SERVO MODE OPERATION
If SG is high, the device is in the Servo mode. This
mode is the same as Idle exceptthatthe filter cutoff and
boost settings are switched from those programmed
for Data Read mode to those programmed for Servo
mode, and the RDS, PPOL, and SEROUT outputs are
enabled. The assertion of SG causes Read mode,
Write mode, and the power down register settings for
the front end to be overriden.
WRITE MODE OPERATION
The 32P4901 supports three different Write modes;
Normal Write mode, direct Write mode #1 and direct
Write mode #2. The Direct Write modes require that
either the Direct write bit, bit 0 of the Control Operating
Register, or the DWR pin be active. All three Write
modes require that the data separator be powered on.
Normal Write Mode
The 32P4901 is in the normal Write mode if WG is high,
DWR is high, and the direct write bit in the Control
Operating Register is low. A minimum of one NRZ time
period must elapse after RG goes low before WG can
be set high. The data separator PLL is phase-frequency
locked to the TBGVCO output in this mode.
In normal Write mode, the circuit first auto generates an
address mark.( soft sector only), then auto generates
the VCO sync pattern, and Jinally scrambles the
incoming NRZ data from the controller, encodes it into
8/9 GCR formatted data, precodes it, precompensates
it, feeds it to a write data toggle flip-flop, and outputs it
to the preamp for storage on the disk. The w,rite data
flip-flop is reset when WG goes low to ease testing. The
Circuit can operate in either soft or hard Sector modes.
Normal Write Mode· Soft Sector
In soft sector operation, when the write gate (WG) goes
high, the NRZ inputs must be low and must be held low
6-82
SSI32P4901
PRML Read Channel with
PR4, 8/9 ENDEC, FWR Servo
forthe duration of the address mark and VCO sync field
generation. The address mark enable (AMENB) should
be made active (low) a minimum of 1 NRZ time period
after rising WG to initiate the generation of the address
mark sequence at the WD/WD outputs. The address
mark sequence consists offour8 "0" gaps (=9T). {(1, 1,
1,1,1,1,1,1,1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1,
1, 1, 1, 1, 1, 1 , -1, -1, -1, -1, -1 , -1, -1, -1 , -1) in the write
current domain} AMENB should be held low for 5 NRZ
time periods minimum and then returned high. Next,
the circuit generates the VCO sync field (=2T) at the
WD/WD outputs. ((1,1,-1,-1,1,1,-1,-1 ... ) in the write
current domain} While the preamble is being written,
WCLK must continue to clock in all (0) NRZ data. After
the required sync field has been written (approximately
8 byte times, min.), the NRZ data must be changed to
93H for a minimum of 5 byte times to write the minimum
5 byte equalizertraining pattern. The device will continue
to autogenerate the sync field pattern until the first 93H
is latched at NRZ interface, and detected. Next, the
NRZ data must be changed to 96H for 1 byte time to
write the sync byte. Now the user NRZ data may be
written. Finally, after the last byte of user data has been
clocked in, the WG must remain high for a minimum of
34 NRZ bit times in Byte-Wide mode to ensure the that
the device is flushed of data (The delay is 37 NRZ bit
5 BYTES MIN.
Normal Write· Hard Sector
In hard sector operation, the circuit performs exactly
the same as in soft sector except that the AMENB input
pin will be held high so the address mark pattern is not
generated.
Direct Write Mode #1
In this Direct Write mode, the NRZ data from the bytewide interface bypasses the scrambler and the 8/9
encoder, but is precoded and precompensated before
going to the write data flip-flop and then to the WD/WD
output pins. WCLK is required to clock the byte-wide
NRZ data into the NRZ interface. Direct Write mode #1
is entered simply by setting the DW bit (bit 0) in the
Control Operating Register. This mode is not valid
when using the dual-bit NRZ interface.
Direct Write Mode #2
In this Direct Write mode, the data presented at the
DWI/DWI input pins directly toggles the write data flipflop which drives the WD/WD output pins. No WCLK is
required in this mode, and the WD/WD output is not
VCO SYNC
FIELD
TRAINING
SEQUENCE
8 BYTES MIN.
5 BYTES MIN.
OOH
NRZ DATA (WRITE)
times in Dual Bit mode). WG can then go low. WD/WD
stops toggling a maximum of 2 NRZ (RCLK) time
periods after WG goes low.
OOH
SCRAMBLED AND ENCODED
USER DATA
1 BYTE
96H
93H
USER DATA
~
WG
~
~~------~
FIGURE 8: Soft Sector Write Sequence
NRZ DATA (WRITE)
VCO SYNC
FIELD
TRAINING
SEQUENCE
B BYTES MIN.
5 BYTES MIN.
OOH
93H
SCRAMBLED AND ENCODED
USER DATA
1 BYTE
96H
WG
FIGURE 9: Hard Sector Write Sequence
6-83
USER DATA
II
SSI32P4901
PRML Read Channel with
PR4, 8/9'ENDEC', FWR Servo
Direct Write Mode #2 (continued)
resynchronized. Direct Write mode #2 is entered simply
by driving the DWR input low.
Data Read Mode Operation
Data Read mode is initiated by setting the Read Gate
(RG) input pin high. This action causes the data
synchronizer to begin to acquisition of the clock from
the incoming VCO sync pattern. To achieve this, the
data synchronizer utilizes a fully integrated fast
acquisition PLL to accurately develop the sample clock.
This PLL is normally locked to the time base generator
output, but when the Read Gate input (RG) goes high,
the PLL's reference input is sWitched to the fittered
incoming read Signal.
SOFT SECTOR OPERATION
In soft sector read operation the circuit must first detect
an address mark before initiating the rest of the read
lock sequence.
Address Mark Detect
The address mark consists of four sets of 8 "0" (=9T)
patterns{(1,O,O,O,O,O,O,O,O,-1,O,O,O,O,O,O,O,O,1,O,O,O,O,
0,0,0,0,-1,0,0;0,0,0,0,0,0,1) in the read domain}. This
pattern was chosen because the interval between
polarity changes ofthe read back pattern has 9 nominal
clock periods which is illegal in an 8/9 (0,4,4) code. The
maximum zero read data pattern for a legal 819 (0.4,4)
code word is 5 nominal clock periods between polarity
changes. The read signal polarity changes are detected
by the dual level pulse detector. Address mark detection
is accomplished by counting the clocks (as "O's")
between the polarity changes.
To begin the soft sector read sequence the Address
Mark Enable (AMENB) input pin must be asserted low.
The address mark detect (AMD) circuit then initiates a
search of the level qualified read data (RD) for an
address mark. First the AMD looks for a set of 7 "O's"
within the 8 "0" patterns. Having detected a 7 "0" the
AMD then looks for two more 7 "0" gaps. If the AMD
does not detect three 7 "0" gaps within 38 code clock
periods it will restart the address mark detect sequence
and look for 7 "O's." When the AM D has acquired a 7 "0"
3-gap sequence, the AMD output pin transitions low.
The AMD will remain low for the duration of AMENB.
When the AMENB is released, the AM Dwill be released.
Acquisition of OS VCO Sync
After the Address Mark (AM) has been detected, the
Read Gate input can be assertli1d high, initiating the
remainderof.the read sequence. WhenHG is asserted
an internal counter begins counting the pulses that are
qualified by the. dual level pulse qualifier given the
polarity changes of. the incoming 1,1, -1, -1 ,1 ,1 read
back pattern de.fined by the VCO sync field. When the
count reaches 4, the internal read gate is asserted and
the DS Pl,L input is switched from the TBG's VCO
output to the sampled data input. This is also the point
at which theDS PLL's phase detector is switched from
the phase-frequency detector to the decision directed
phase detector. The counter is also used to determine
whether the selected sync field count, SFC, has been
achieved. The SFC, is the point at which the data
synchronizer PLLis assumed to be locked and settled
(VCO lock). At SFC is also when the phase detector
gain switch andthe AGC mode switch occur. To allow
for different preamble lengths, the SFC can be set to
VCOSYNC
FIELD
NRZDATA
SCRAMBLED AND ENCODED
USER DATA
4 BYTES MIN.
8 BYTES MIN.
5 BYTES MIN.
HIGHZ
OOH
OOH
1 BYTE
96H
U
RG
I
Figure 10: Soft Sector Read Sequence
6-84
USER DATA
SSI 32P49.01
PRML Read Channel with
PR4, 8/9 ENDEC, FWR Servo
64, 80, 96 or 128 from the Sample Loop Control
Register. These values for the SFC may be thought of
as the number of code clock periods in the sync field,
butthey actually represent twice the number of incoming
polarity changes required.
VCO Lock, PO Gain, AGC Mode Switch, and Code
Word Boundry Detector Enable
At SFC, one of two phase tracking methods will be
chosen depending on the Enable Phase Detector Gain
Switching (GS) bit in the Control B Register. When the
GS bit is low, the phase detector gain is reduced by a
factor of 5 after the SFC count is reached. When the GS
bit is high, no phase detector gain switching takes place.
Also after SFC, the AGC feedback will be switched
from the continuous time fullwave rectifier to sampled
data feedback.
At SFC, the internal VCO lock signal activates the code
word boundry detection circuitry to define the proper
decode boundaries. Also, at count SFC, the RCLK
generator source switches from the TBG's VCO output
to the DS VCOciock signal which is phase locked to the
incoming read data samples. The DS VCO is assumed
locked to the incoming read samples at this point. A
maximum of 1 RCLK time period may occur for the
RCLK transition, however, no short duration glitches
will occur. After the code word detection circuitry finds
the proper code word boundry, the RCLK generator is
resynchronized to guarantee that the RCLK is in sync
with the data. The RCLK and NCLK outputs will not
glitch and may not toggle during the RCLK generator
resynchronization for up to 2 byte times maximum.
Adaptive Equalizer Training Sequence
As was previously discussed, in a normal write
sequence, a minimum of 5 bytes of NRZ 93H and one
byte of 96H must be written between the end of the
VCO sync field and the beginning of the user data. The
5 bytes of 93H are 8/9 encoded and precoded during
Write mode to produce the adaptive equalizer training
pattern. During Read mode, this sequence (10011 0011
read data sequence) is used to adaptively train the
three tap transversal filter in a zero forcing manner. The
error at the filter output is integrated to derive the tap
weight multiplying coefficient, Km. The filter input and
output tap will have the same Km. It is anticipated that
the continuous time equalizer will be used for coarse
equalization and that transversal filter will be used
adaptively for fine tuning. This will reduce Km's range
and accuracy requirements. Since there are encoded
user data patterns that will not produce an equalizer
correction error, an equalization hold during Data mode
can selected from the Sample Loop Control Register.
After the training pattern, if the loop is active during
data, the equalizer loop gain will be reduced by 4. The
loop's integration time constant is made inversely
proportional to the selected data rate.
Also at the code word boundry detect, the internal9-bit
code words are allowed to pass to the ENDEC for
decoding. This decoding will occur until read gate is
deasserted.
GAP
NRZ DATA
HIGH Z
VCO SYNC
FIELD
TRAINING
SEQUENCE
8 BYTES MIN.
5 BYTES MIN.
OOH
OOH
SCRAMBLED AND ENCODED
USER DATA
1 BYTE
96H
RG
FIGURE 11: Hard Sector Read Sequence
6-85
USER DATA
I
SSI32P4901
PRML Read Channel with
PR4, 8/9 ENDEC, FWR Servo
Sync Byte Detect and NRZ Output
As the read data is 8/9 decoded, it is compared to an
internally fixed sync byte (96H). When a match is
found, the sync byte detect (SBD) pin goes low and the
NRZ output data that until now was held low, is changed
to.96H. The next byte presented on the NRZ outputs is
the first byte of user data. SBD will remain low and NRZ
data will continue to be presented at the NRZ interface
until the read gate is deasserted at which point SBD
goes high and the NRZ outputs go to a high impedance
state.
HARD SECTOR OPERATION
In hard sector operation, Address Mark search and
detection is not required, so by setting AMENB high,
the Address Mark Detection circuitry is disabled and
AMD remains inactive. A hard sector read operation
begins with the assertion of RG which starts the VCO
sync field counting as in soft Sector mode and
sequences identically. In all respects, with exception of
the lack of an address mark search sequence, hard
sector read operation is the same as soft sector read.
Down Register bit disables that section of the circuit.
The power down information from the Power Down
Register takes effect immediately after the SDEN pin
goes low.
When the PDWN input is low, the chip goes into full
Power Down mode regardless of the power down
register settings or the state of the SG input.
When PDWN is high and SG will force the AGC, filter,
and pulse qualifier circuits (front end) to be active by
overriding the front end register bit. The back end
Power Down register bits, which include the Data
Separator and Tme Base Generatorare not affected by
the SG input.
The serial port is active in all Power Down modes.
The time to restart from a full power down is dependent
on the PLL loop filter and the data rate.
The truth table for the various modes of operation is
shown below.
POWER DOWN OPERATION
The power Management modes of the 32P4901 are
determined by the states of the Power Down Register
bits and the PDWN and SG inputs. The individual
sections of the chip can be powered down or up using
the Power Down Register. A high level in a Power
TABLE 1: Operation Mode Truth Table
SG, PDWN
1,1
1,0
0,1
0,0
Front End
ON
OFF
R
OFF
Data Separator
R
OFF
R
OFF
Timebase Generator
R
OFF
R
OFF
ON
ON
ON
ON
Serial Port
--
R = Controlled by register bit.
(Register bit =1 turns CirCUits OFF, Register bit = 0 turns CircUits ON)
6-86
SSI32P4901
PRML Read Channel with
PR4, 8/9 ENDEC, FWR Servo
PIN DESCRIPTION
POWER SUPPLY PINS
NAME
TYPE
DESCRIPTION
VPA
-
AGC/Filter analog circuit supply
VPF
-
Time Base Generator PLL analog circuit supply
VPT
-
Time Base Generator digital supply
VPP
-
Data Separator PLL analog circuit supply
TTL Buffer 1/0 digital supply
-
AGC/Filter analog circuit ground
VPD
VPC
VPS
VNA
VNF
Internal ECL, CMOS logic digital supply
Sampled data processor supply
Time Base Generator PLL analog circuit ground
-
TTL Buffer 1/0 digital ground
VIM, VIA-
I
AGC AMPLIFIER INPUTS: Differential AGC amplifier input pins
DP,DN
I
ANALOG INPUTS FOR DATA PATH: Differential analog inputs to data
comparators, full-wave rectifier
CP,CN
I
ANALOG INPUTS FOR CLOCK PATH: Differential analog inputs to the clock
comparator
VNT
VNP
VND
VNC
VNS
Time Base Generator digital ground
Data Separator PLL analog circuit ground
Internal ECL, CMOS logic digital ground
Sampled data processor ground
ANALOG INPUT PINS
ANALOG OUTPUT PINS
NAME
TYPE
DESCRIPTION
TPA+, TPA-
0
TEST PINS: Emitter output test points. Various signals are multiplexed to
these test points by the Test Point Control Register. The signals include the
equalizer control voltage and output, various timing loop control signals and
the viterbi survival register outputs. The test points are provided to show how
the signal is being processed. Internal "pull down" resistors to ground are
provided. To savepowerwhen not in Test mode, the Control Test Register bits
3 - 5 must be set to "0".
TPB+,TPB-
0
TEST PINS: Emitter output test pOints similarto TPA+ and TPA-. The pins are
used to look at the other phase of the interleaved signals.
ATO
0
ANALOG TEST OUT: A test point used to indicate the operation of controlled
functions which cannot be easily determined by direct testing of the circuit pins.
The selected output is determined by the address in the serial control register.
6-87
II
SSI32P4901
PRML Read Channel with
PR4,8/9 ENDEC, FWR Servo
ANALOG OUTPUT PINS (CONTINUED)
DESCRIPTION
NAME
TYPE
ATRN
0
ANALOG TEST OUT RETURN: A test point used as the ATO return.
ON+.ON-
0
FILTER NORMAL OUTPUTS: These are the filter normal low pass output.
They should be AC coupled to the data comparator in the pulse qualifier. Open
emitter output with internal pulldown. If driving more than coupling cap.
external pull down resistor to ground may be required.
00+.00-
0
FILTER DIFFERENTIATED OUTPUTS: These are the filter time differentiated low pass output. They should be AC coupled. for low DC offset. to the
clock comparator in the pulse qualifier. Open emitter output with internal
pulldown. If driving more than coupling cap. external pull down resistor to
ground may be required.
SEROUT
0
MULTIPLEXED SERVO OUTPUT: Open Emitter. Requires external pull
down to GND.
SREF
0
SERVO REFERENCE OUTPUT: +2.0V DC reference voHage. baseline for
servo bursts. Open Emitter. Requires external pull down to GND.
ANALOG CONTROL PINS
.
BYP
-
The data AGC integrating capacitor. CBYP. is connected between BYP and
VPA. This pin is used when in data Read mode (RG = 1).
BYPS
-
The servo AGC integrating capacitor. CBYPS. is connected between BYPS
and VPA. This pin is used when in servo Read mode (SG = 1).
FLTR1+. FLTR1-
-
TBG PLL LOOP FILTER: Differential connection points for the time base
generator PLL loop fiHer components.
FLTR2+.FLTR2-
-
OS PLL LOOP FILTER: Differential connection points for the data separator
PLL loop filter capacitor.
RR
-
CURRENT REFERENCE RESISTOR INPUT: An external 1% 12.1 k.Q
resistor is connected from this pin to ground to establish a precise internal
reference current for the data separator and the time base generator DACs.
VRX
-
FILTER REFERENCE RESISTOR INPUT: An external 1% 12.1 k.Q resistor is
connected from this pin to ground to establish a precise PTAT (proportional to
absolute temperature) reference current for the filter DACs.
VRC
-
AGC REFERENCE VOLTAGE: VRC is derived by a bandgap reference from
VPA1.
LOWZ
I
LOW-Z MODE INPUT: TTL compatible control pin which. when pulled high.
the input impedance is reduced to allow rapid recovery of the input coupling
capacitor. When pulled low. keeps the AGC amplifier and fiHer input impedance high. An open pin is a logic high.
FASTRE.C
I
FAST RECOVERY: TIL CO mpatible control pin which. when pulled high. puts
theAGC charge pump in the fast Decay mode. An open pin is a logic high.
'
[,
DIGITAL INPUTPINS
6-88
SSI32P4901
PRML Read Channel with
PR4, 8/9 ENDEC, FWR Servo
DIGITAL INPUT PINS (continued)
NAME
TYPE
DESCRIPTION
AMENB
I
ADDRESS MARK ENABLE: TTL compatible control pin which, when pulled
low, enables the address mark detection and generation circuitry. An open pin
is a logic high.
PDWN
I
POWER DOWN CONTROL CONTROL: TTL compatible power control pin.
When set to logic low, the entire chip is in Sleep mode with all circuitry, except
serial port, shut down. This pin should be set to logic high in normal Operating
mode. Selected circuitry can be shut down by the Power Down Register. An
open pin is a logic high.
HOLD
I
AGC HOLD CONTROL INPUT: TTL compatible control pin which, when
pulled low, holds the AGC amplifier gain constant by turning off the AGC
charge pump. The AGC loop is active when this pin is either at high or open.
FREF
I
REFERENCE FREQUENCY INPUT: Reference frequency for the time base
generator. FREF may be driven either by a direct coupled TTL signal or by an
AC coupled ECL signal. When bits 2 or 7 of the Control Test Register are set,
FREF replaces the VCO as the input to the data separator.
WCLK
I
WRITE CLOCK: TTL compatible input that latches in the data at the selected
NRZ interface on the rising edge. Must be synchronous with the write data
NRZ input. For short cable delays, WCLK may be connected directly to pin
RCLK. For long cable delays, WCLK should be connected to an RCLK return
line matched to the NRZ data bus line delay. An open pin is at logic high.
RG
I
READ GATE: TTL compatible input that, when pulled high, selects the PLL
reference input and initiates the PLL synchronization sequence. A high level
selects the RD input and enables the Read mode/address detect sequences.
A low level selects the time base generator output. An open pin is at logic high.
WG
I
WRITE GATE: TTL compatible inputthat, when pulled high, enables the Write
mode. An open pin is at logic high.
SG
I
SERVO GATE: TTL compatible input that, when pulled low, enables the Servo
Read mode. An open pin is at logic high.
SELVRC
I
SERVO REFERENCE SELECT: TTL compatible input. When SG is low this
input selects between the SREF reference (SELVRC = high) and the SREF +
200 mV level (SELVRC = low) for presentation at the SEROUT output.
VRDT
I
VITERBI READ DATA: A TTL or AC coupled PECL compatible input to the
data separator back end, fortesting purposes only. This pin is controlled by the
VRDT bit in the Control Test Register.
DWR
I
DI RECT WRITE MODE 2 ENABLE: Enables DWI, DWI inputs to the write data
flip-flop when input is low. TTL levels. Open pin ia at logic high.
DWI,DWI
I
DIRECT WRITE INPUTS: Inputs connect to the toggle input of the write data
flip-flop when DWR is low. PECL input levels. Can be left open.
6-89
I
SSI32P4901
PRML Read Channel with
PR4, 8/9 EN DEC, FWR Servo
DIGITAL INPUT PINS (continued)
NAME
TYPE
DESCRIPTION
SCLK
I
SERIAL DATA CLOCK: Positive edge triggered clock input for the serial data.
TTL input levels.
SDATA
I
SERIAL DATA: Input pin for serial data; 8 address bits first followed by 8 data
bits. The address and data bits are entered LSB first, MSB last. TTL input
levels.
SDEN
I
SERIAL DATA ENABLE: A high level input enables data loading. The data is
internally parallel latched when this input goes low. TTL input levels.
DIGITAL BIDIRECTIONAL PINS
NAME
TYPE
NRZO-7
I/O
DESCRIPTION
BYTE WIDE NRZ DATA PORT:. TTL compatible bi-directional input/output.
Input to the encoder when WG is high. Output from the decoder when RG is
high. Can be left open if not used.
NRZP
I/O
NRZ DATA PARITY BIT: Active when in Byte Wide mode. TTL compatible bidirectional input/output. Generales even read parity when RG is high, and
accepts even write parity when WG is high. Can be left open if not used.
DBO-1
I/O
DUAL BIT NRZ DATA PORT: TTL compatible bi-directional input/output. Input
to the encoder when WG is high. Output from the decoder when RG is high.
Can be left open if not used.
6-90
SSI32P4901
PRML Read Channel with
PR4, 8/9 ENDEC, FWR Servo
DIGITAL OUTPUT PINS
RCLK
0
READ REFERENCE CLOCK: A multiplexed clock source used by the controller. When RG is low, RCLK is synchronized to the time base generator output,
FTBG • When RG goes high, RCLK remains synchronized to FTBG until the SFC
is reached. At that time, RCLK is synchronized to the data separator VCO.
During a mode change, no glitches are generated and no more than one lost
clock pulse will occur. TTL output levels.
NCLK
0
NIBBLE CLOCK: A half-byte clock synchronized to RCLK. It runs at twice the
frequency of RCLK. CMOS output levels.
AMD
0
ADDRESS MARK DETECT: Tristate output pin that is in its high impedance
state when WG is high or AMENB is high. When AMENB is low, this output
indicates address mark search status. A latched low level output appears
when an address mark has been detected. A high level on pin AMENB resets
pin AMD. CMOS output levels.
SBD
0
SYNC BYTE DETECT: Transitions low upon detection of sync byte. This
transition is synchronized to the sync byte. Once it transitions low, SBD
remains low until RG goes low, at which point it returns high. CMOS output.
WD,WD
0
WRITE DATA: Write data flip-flop output. The data is automatically resynchronized (independent of the delay between RCLK and WCLK) to the
reference clock FTBG , unless in Direct Write mode. Differential PECL output
levels.
VRDT
0
VITERBI READ DATA: An input to the data separator back end, used for
testing. TIL input levels or an AC coupled ECL signal. This pin is controlled
by the VRDT bit in the Control Test Register.
RDS
0
SERVO READ DATA: Read Data Pulse output for servo read data. Active low
CMOS output. Output active when SG is high, and high when SG is low.
PPOL
0
SERVO READ DATA POLARITY: Read Data Pulse polarity output for servo
read data. Active high CMOS output. Negative pulse = low, positive pulse =
high. Output active when SG is high.
6-91
II
"tI"tIen
en
,I:::I.==--
:0:0
=- w
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mil\)
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FIGURE 12: Application Diagram
cO"'"
mo :::r
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m
~ (1)
::!
-::e
en -..
....
041
(1):T
~
c:;
0
SSI32P4901
PRML Read Channel with
PR4, 8/9 EN DEC, FWR Servo
PACKAGE PIN DESIGNATIONS
(Top View)
u u
....
....
2 2
VIA·
VIA+
0
~
xu":
.........
>2>
~
2
,; 0
..
0
0
z io
0
~
2
2
0
...
0
2
U
...
U
..: u.... u.... u.... u....
2
>
2
..
2
2
..,
., ... '"
., .,., .,... .,'" .,'" ., .,.., .,
'"'" '" '" '" '" '" '" '" '" '" '"
II>
N
_
0
N
2
;;;
....
'"'" ~~., 2
., ...'" ... ......
u u
....
2
0
N/C
SEROUT
N/C
BYP
BYPS
SREF
mrn
VRC
lOWZ
RR
N/C
FASTREC
VRDT
SElVRC
SClK
N/C
SDATA
VPS
SDEN
VNS
VPF
TPA+
FREF
TPA·
VNF
TPB+
VPT
TPB·
FlTR1+
VPS
FLTR1·
ATO
VNT
ATRN
DWI
VNS
15Wl
VPP
tlWl'I
WG
FLTR2·
WD
VNP
vm
RG
II
FlTR2+
...
N
.. ;: . ...., ... . ..'" . .,.. ..'"
., ;;; .. ..... .. . . ...., ... ... .. .'" .... '"
aa~ I .... ....
...
0_
.,N '"
.., ..,
N
~ ~I ~
Nf'I')
...
U1u:t
....
CO
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tr')
f'I')
'"
tw)
N
N
N
0
2
>
0
0
0
UJ
C"')
N
N
0
;::;
2
2
2
2
2
..,
'"
0
>
N
0
N
N
N
2
2
2
2
..J
U
~
VNC
51
VPC
II)
u u
II)
N
o
...
II)
..
2
2
2
100-Lead TQFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
NOTE: This is an abridged version of the 32P4901 (x2) data sheet. For a complete copy
call 1-800-624-8999 ext. 151
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
ofthird parties resulting from its use. No lioense is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notioe. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1994 Silicon Systems, Inc.
0194
6-93
Notes:
6-94
Section
7
HOD HEAD
POSITIONING
7
7-0
SSI32H569
Servo Motor Driver
December 1993
DESCRIPTION
FEATURES
The SSI32H569 Servo Motor Driver is a bipolar device
intended for use in Winchester disk drive head positioning systems employing linear or rotary voice coil
motors. When used in conjunction with a position
controller, such as the SSI 32H6220 Servo Controller,
and a position reference, such as the SSI 32H6210
Servo Demodulator, the device allows the construction
of a high performance, dedicated surface head positioning system.
•
Predrlver for linear and rotary voice coil
motors
•
Interfaces directly to MOSFET H-Bridge motor
driver
•
Class B linear mode and constant velocity
retract mode
•
Precision differential amplifier for motor
current sensing
It
The SSI 32H569 serves as a transconductance amplifier by driving 4 MOSFETs in an H-bridge configuration, performs motor current sensing and limits motor
current and velocity. In its linear tracking mode, class
B operation is guaranteed by crossover protection
circuitry, which ensures that only one MOSFET in each
leg of the H-bridge is active. The MOSFET drivers are
disabled when motor velocity or current exceed externally programmable limits. In addition, automatic head
retraction and spindle braking may be initiated by a low
voltage condition or upon external command.
Motor current and velocity limiting circuitry
•
Automatic head retract and spindle braking
signal on power failure
•
•
External digital enable
Servo loop parameters programmed with
external components
•
Advanced bipolar Ie requires under 240 mW
from 12V supply
•
Available In 20-pin DIP or SO packaging
(continued)
PIN DIAGRAM
BLOCK DIAGRAM
ERR
VEl-
I
1--"""""'-1''''
vee
ERR·
VElOCITYI
C;URRENT
L.. IT
SOOTI}_ _ _~__+-~_~
___+-__
'R
lOWV
ERR +
EN
VREF
OUTA
SOUT
OUTS
~-<
ERR
VEl-
SE1
VEL
SE2
ERR-
ERR.
VREF
SRK
OUTO
SE3
OUTe
GND
VUM
vet..
20-Pin SO, DIP
CAUTION: Use handling procedures necessary
for a static sensitive component.
vee
1293 - rev.
LOIN
EN
7-1
SSI32H569
Servo Motor Driver
actual motor acceleration. If SOUT is integrated, using
opamp A3 and an external RC network, the resulting
Signal, VEL, is proportional to the motor velocity.
DESCRIPTION (continued)
The SSI32H569 is implemented in an advanced bipolar process and dissipates less than 240 mW from a
12V supply. The IC is available in 20-pin DIP and
20-pin SO packaging.
Both SOUT and VEL are connected to window comparators, which are used to detect excessive motor
current or velocity . The comparator outputs disable the
MOSFET drivers until the motor comes within limits
again. The VLlM pin may be used to program the
voltage limits for the window comparators. The maximum voltage excursion allowed about VREF is (VREFVLlM). An on-Chip resistor divider sets a default value
for VLlM and if VLlM is connected to ground, the
windowing is effectively disabled.
FUNCTIONAL DESCRIPTION
(Refer to block diagram and typical application Fig.2)
The SSI 32H569 has two modes of operation, linear
and retract. The retract mode is activated by.a power
supply failure or when the control signal EN is false.
Otherwise the device operates in linear mode.
The SSI32H569 has low voltage monitor circuitry that
will detect a loss of voltage on the VREF, VCC or
LOWV pins. The power supply pin, VCC, should be
connected to the disk drive's spindle motor so that its
stored rotational energy may be used to hold up VCC
briefly during a power failure. LOWV is used to detect
a system power supply failure. When a low voltage
condition is detected, the MOSFET drivers switch from
linear operation to retract mode. In this mode a constant voltage is applied across the motor which will
cause the heads to move at a constant speed. A
mechanical stop must be provided for the heads when
they reach a safe location. The current limiting circuitry
will disable the MOSFET drivers when motor current
increases due.to loss of the velocity-induced back
EMF. An open collector output, BRK, which is active
while the device is in retract mode, is provided for
spindle motor braking. An external RC delay may be
used to defer braking until the heads are retracted. For
proper operation of the SSI 32H569, a pullup resistor
on BRK is required even if the BRK output is not used.
During linear operation, an acceleration signal from the
servo controller is applied through amplifier A 1, whose
three connections are all available externally. RC
components may be used to provide loop compensation at this stage. The ERR signal drives two precision
amplifiers, each with a gain of 8.5. The first of these
amplifiers is inverting, and is formed from opamp A4,
an on-Chip resistor divider and an off-chip complementary MOSFET pair. The second is non-inverting, and is
formed in a similar manner from opamp AS. Feedback
from the MOSFET drains, on sense inputs SE1 and
SE3, allows the amplifiers gains to be established
precisely. The voice coil motor and a series current
sense resistor are connected between SE1 and SE3.
Crossover protection circuitry between the outputs of
A4 and AS, and the external MOSFETs, ensures class
B operation by allowing only one MOSFET in each leg
of the H-bridge to be in conduction. The crossover
separation threshold, illustrated in Figure 5, is the
maximum drive on any MOSFET gale when the motor
voltage changes sign. The crossover circuitry can also·
disable all MOSFETS simultaneously (to limit motor
current or velocity) or apply a constant voltage across
the motor (to retract the heads at a constant velocity).
An example of an entire servo path implemented with
the SSI 32H569 and its companion devices, the
SSI32H6210 and 32H6220, is shown in Figure10.
Motor current is sensed by a small resistor placed in
series with the motor. The voltage drop across this
resistor is amplified by a differential amplifier with a
gain of 4 (A2 and associated reSistors), whose inputs
are SE1 and SE2. The resulting voltage, SOUT, is
proportional to motor current, and hence acceleration.
This signal is externally fed back to A 1, so that the
signal ERR represents the difference between the
desired acceleration (from the servo controller) and the
7-2
Cv
VElocrrvl
CURRENT
RV
UMIT
4R
RF
Y,N
DISABLE DRIVERS
VREF~
~
TOSPINDLEMQTOR
BRAKING TRANSISTOR
RBAK
••V
vec
(TOMOTORDRIVER)~
C/)
TO SPINDLE MOTOR
(D
r
~
o
~C/)
-C/)
0FIGURE 2: Typical Application
"'w
eN
:::c
<(11
(Den
:!.
•
... CD
S,S132H569
Servo Motor Driver
PIN DESCRIPTION
POWER
NAME
PIN
TYPE
DESCRIPTION
VCC
20
-
POSITIVE SUPPLY - 12V power supply. Usually taken from spindle motor
supply. Spindle motor stored energy permits head retraction during power
failure. If VCC falls below 9V. a forced head retraction occurs.
LOWV
19
I
LOW VOLTAGE - System 12V supply. Ifthis inputfalls below 9V. a forced
head retraction occurs.
VREF
4
I
REFERENCE VOLTAGE - 5.4V input. All analog signals are referenced
to this voltage. If VREF falls bel()w 4,3V. a forced head retraction occurs.
GND
10
-
GROUND
PIN
TYPE
ERR
1
0
POSITION ERROR- Loop compensation amplifier output. This signal is
amplified by the MOSFET drivers and applied to the motor by an external
MOSFET H-bridge. as follows:
ERR-
2
I
POSITION ERROR INVERTING INPUT - Inverting input to the loop
compensation amplifier.
ERR+
3
I
POSITION ERROR NON-INVERTING INPUT - Non-inverting input to the
loop compensation amplifier.
SOUT
5
0
MOTOR CURRENT SENSE OUTPUT - This output provides a voltage
proportionalto the voltage drop across the external current sense resistor.
as follows:
CONTROL
.
NAME
DESCRIPTION
SE3-SE1 ,. 17(ERR-VREF)
SOUT-VREF,.4(SE2-SE1)
VEL-
6
I
VELOCITY INVERTING INPUT -Inverting input to the velocity integrating
amplifier. The non-inverting input is connected internally to VREF.
VEL
7
0
VELOCITY OUTPUT - Output of the velocity integration amplifier. This
signal is internally applied to a window comparator whose output limits
motor drive current when the voltage at VEL exceeds a set limit.
BRK
8
0
BftAKE OUTPUT - Active high. open collector output which may be used
to enable an external spindle motor braking transistor upon power failure
or deassertion of EN.
VLlM
11
I
LIMITING VOLTAGE - The voltage at this pin sets motor current and
velocity limits. Limiting occurs when:
or
ISOUT-VREFI> VREF-VLlM
IVEL-VREFI>VREF-VLlM.
An internal resistor divider establishes a default value that may be
externally adjusted.
704
SSI32H569
Servo Motor Driver
CONTROL (Continued)
NAME
PIN
TYPE
DESCRIPTION
SE2
14
I
MOTOR CURRENT SENSE INPUT - Non-inverting input to the current
sense differential amplifier. It should be connected to one side of an
external current sensing resistor in series with the motor. The inverting
input of the differential amplifier is connected internally to SE1.
EN
18
I
ENABLE - Active high TTL compatible input enables lineartracking mode.
A low level will initiate a forced head retract.
PIN
TYPE
9
I
FETDRIVE
NAME
SE3
DESCRIPTION
MOTOR VOLTAGE SENSE INPUT - This input provides feedback to the
non-inverting MOSFET driver amplifier. It is connected to one side of the
motor. The gain to this point is:
SE3-VREF = 8.5(ERR-VREF)
OUTC
12
0
P-FET DRIVE (NON-INVERTING) - Drive signal for a P channel MOSFET
connected between one side of the motor and VCC. This MOSFET drain
is connected to SE3.
OUTO
13
0
N-FET DRIVE (NON-INVERTING) - Drive signalforan Nchannel MOSFET
connected between one side of the motor and GND. This MOSFET drain
is connected to SE3. Crossover protection circuitry ensures that the P and
N channel devices driven by OUTC and OUTD are never enabled
simultaneously.
SE1
15
I
MOTOR VOLTAGE SENSE INPUT - This input provides feedback to the
inverting MOSFET driver amplifier. It is connected to the current sensing
resistor which is in series with the motor. The gain to this point is:
SE1-VREF = -8.5(ERR-VREF)
This input is internally connected to the current sense differential amplifier
inverting input.
OUTB
16
0
N-FET DRIVE (INVERTING) - Drive signal for an N channel MOSFET
connected between the current sense resistor and GND. This MOSFET
drain is also connected to SE1.
OUTA
17
0
P-FET DRIVE (INVERTING) - Drive signal for a P channel MOSFET
connected between the current sense resistor and VCC. This MOSFET
drain is also connected to SE1. Crossover protection circuitry ensures that
the P and N channel devices driven by OUTC and OUTD are never
enabled simultaneously.
7-5
SSI32H569
Servo Motor Driver
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(Maximum limits indicates where permanent device damage occurs. Continuous operation at these limits
is not intended and should be limited to those conditions specified in the DC operating characteristics.)
PARAMETER
CONDITIONS
MIN
VCC
VREF
SE1, SE2, SE3
All other pins
Storage temperature
Solder temperature
TYP
MAX
UNITS
0
16
V
0
10
V
-1.5
15
V
0
14
V
-45
10 sec duration
165
°C
260
°C
RECOMMENDED OPERATION CONDITIONS (Unless otherwise noted, the following conditions are valid
throughout this document.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
Normal Mode
9
12
13.2
V
Retract Mode
3.5V
14
V
VREF
5
7
V
Operating temperature
0
70
°C
ICC, VCC current
20
rnA
IREF, VREF current
2
rnA
DC CHARACTERISTICS
A1, LOOP COMPENSATION AMPLIFIER
Input bias current
Input offset voltage
500
nA
3
mV
Voltage swing
About VREF
2
V
Common mode range
About VREF
±1
V
Load resistance
To VREF
4
Load capacitance
kQ
100
pF
Gain
80
dB
Unity gain bandwidth
0.5
MHz
CMRR
1<20 kHz
60
dB
PSRR
1<20 kHz
60
dB
7-6
SSI32H569
Servo Motor Driver
A2, CURRENT SENSE AMPLIFIER
PARAMETER
CONDITIONS
MIN
TYP
Input impedance
SE1 to SE2
3.5
5
Input offset voltage
MAX
UNITS
2
mV
kO
Output voHage swing
VREF-4
VCC-1.2
V
Common mode range
0
VCC-O.2
V
Load Resistance
4
To VREF
kO
Load Capacitance
Output impedance
1<40 kHz
Gain (SOUT-VREF)/(SE1-SE2)
VSE2 = VREF
4
3.9
Unity gain bandwidth
100
pF
20
0
4.1
0.5
VN
MHz
CMRR
1<20 kHz
52
dB
PSRR
1<20 kHz
60
dB
A3, VELOCITY INTEGRATING AMPLIFIER
PARAMETER
CONDITIONS
MIN
TYP
Input bias current
Input offset voHage
Voltage swing
Common mode range
Load resistance
MAX
250
nA
2
mV
VREF-4
VCC-1.2
V
4.5
6
V
10
To VREF
kO
Load capacitance
80
RB, internal feedback resistor
UNITS
100
pF
150
kO
MAX
UNITS
65
%
WINDOW COMPARATORS AND LIMITING
PARAMETER
Window comparator threshold
(SOUT-VREF or VEL-VREF)
VREF-VLlM
Threshold hysteresis
VLlM voltage
TYP
MIN
CONDITIONS
35
No external parts
VREF-l.B
50
VLlM input resistance
7-7
50
V
VREF-2.2
V
kO
SSI32H569
Servo Motor Driver
POWER SUPPLY MONITOR
PARAMETER
CONDITIONS
MIN
IILowvl < 0.5 mA
VCC fail threshold
LOWV fail threshold
VREF fail threshold
TYP
MAX
UNITS
8.5
9
9.8
V
8.5
9
9.8
V
4.3
4.8
3.9
Hysteresis (LOWV, VCC)
Hysteresis (VREF)
V
250
mV
110
mV
EN input low voltage
IIILI < 0.5 mA
EN input high voltage
IIIHI < 40 uA
2
V
BRK voltage
normal mode, IIOLI < 1 mA
0.4
V
BRK leakage current
retract mode
10
(.1A
1
ms
MAX
UNITS
0.8
V
BRK delay (from power fail or
EN false to BRK floating)
MOSFET DRIVERS
PARAMETER
CONDITIONS
SE3 Input impedance
To VREF
MIN
TYP
10
25
kO
OUTA,OUTC
voltage swing 1101<1 rnA
0.7
VCC-1
V
OUTB,OUTO
voltage swing 1101<1 mA
1
VCC-1
V
2
V
VTH,
Crossover separation threshold
Slew rate
(OUTA, OUTB, OUTC, OUTO)
Ck1000 pF
Crossover time
300 mV step at ERR
1.4
Output impedance (OUTA,B,C,D)
Transconductance
I(OUTA,B,C,D)/(ERR-VREF)
Gain (-(SE1-VREF)/(ERR-VREF)
or (SE3-VREF)/(ERR-VREF) )
Offset current
V/fJ.S
5
8
kQ
8
mAN
8.5
Rs = 0.20, RF = RIN,
VIN=VREF
Retract motor voltage
(SE1-SE3)
0.7
7-8
fJ.S
50
1
9
VN
20
mA
1.3
V
SSI32H569
Servo Motor Driver
APPLICATIONS INFORMATION
LOOP COMPENSATION
A typical SSI32H569 application is shown in Figure 2.
The selection criteria for the external components
shown are discussed below. Figure 3 shows the
equivalent circuit and equations for the DC motor used
in the following derivations. While the nomenclature
chosen is for a rotating motor, the results are equally
applicable to linear motors.
The transfer function of the SSI32H569 in the application of Figure 2 is shown in Figure 4(a). If the zero due
to RL and CL in the loop compensation circuit is chosen
to cancelthe pole due to the motor inductance, Lm, then
the transfer function can be simplified as shown in
figure 4(b), under the assumption that this pole and the
pole due to the motor mechanical response are widely
separated. CL may then be chosen to set the desired
open loop unity gain bandwidth.
MOTOR CURRENT SENSE AND LIMITING
The series resistor which senses motor current, Rs, is
chosen to be small compared to the resistance of the
motor, Rm. A value of Rs = 0.2Q is typical in disk drive
applications. The window comparator threshold, programmed by VLlM, must be chosen to cause limiting
when the motor current reaches its maximum permissible value. If iMAX is the maximum motor current in
Amps, then this value may be chosen as follows:
68 ' Rs
CL=-------------------2,lt' RF' (Rm+ R s)' BW
where BW is the
unity gain open
loop bandwidth
The closed loop response of the servo driver and motor
combination, using the component values and simplifying assumptions given above, is given by:
VLlM=VREF-4' Rs' iMAX (V)
~(S)= __1_.~. ___________
VLlM may be set with a resistor divider whose thevenin
resistance is substantially less than the output resistance of the VLlM pin (50 kQ). The window comparators have hysteresis (typically 50% of their threshold,
VREF-VLlM) to prevent multiple triggerings of the
driver disable signal.
Vin
R in
4· Rs
(1 +
s
)
2,lt'BW
(This analysis neglects the pole due to the output
impedance of the MOSFET drivers and the MOSFET
gate capacitance, an effect that may be significant in
some systems).
VELOCITY LIMITING
The values of Rv and Cv in the velocity integrator are
chosen to produce a voltage excursion of VREF-VLlM,
when the motor speed is at its maximum permissible
value. Rv must be large enough to prevent overloading
of opamp A2. The following equation ignores the effect
of RB, the internal resistor between VEL and VELwhich prevents saturation of A3 due to offsets. For the
motor in Figure 3, with maximum velocity roMAX
(rad/s) these components may be chosen as follows:
RF is chosen to be sufficiently large to avoid overloading A2 (RF II Rv > 4kQ). The input resistor, RIN, sets the
conversion factor from servo controller output voltage
to servo motor current. RIN is chosen such that the
servo controller intemal voltages are scaled conveniently. The resistor Ros is optional and cancels out the
effect of the input bias current of Ai.
Rv I! RF > 4kQ (A20u1pUtloading restriction)
The external components Ro and Co have no effect on
the motor dynamics, but may be used to improve the
stability of the MOSFET drivers. The load represented
by the motor, ZM, is given by:
C v=
Ras = Rinl! RF
4R s,J9'roMAX
(F)
(VREF-VLlM)' Rv' Km
At frequencies above (Rs+Rm)/(2 'It' Lm) Hz, this load
L
K 2
ZM=(Rs+Rm)(1+S--m-)(1+
m
)(Q)
Rs+Rm
S 'J9' (Rs+Rm)
7-9
II
SSI32H569
Servo Motor Driver
LOOP COMPENSATION (continued)
POWER FAILURE OPERATION
becomes entirely inductive, which is undesireable. AD
and Co may be used to add some parallel resistive
loading at these frequencies.
The power supply forthe SS132HS69, VCC, should be
taken from the system 12V supply through a Schottky
diode (maximum O.SV drop at If =3A) and connected
to Ihediskdrive spindle motor. If the system power
fails, the IC will continue to operate as the spindle motor
becomes a generator. The SSI 32HS69 will detect the
powerfailure and cause a forced head retract, continuingto operate with VCC as low as3.SV. The power fail
mode will commence if eitherVCC or LOWVfalls below
9V, orVREFfalls below4.3V, or EN is false. Hysteresis
on the low voltage thresholds prevents the device from
oscillating between operating modes when the power
supply is marginal.
H"BRIDGE MOSFETS
The MOSFETs chosen for the H-bridge should have
gate capacitances in the range of SOO-1000 pF. The
MOSFET input capacitance forms part of the compensation forthe MOSFET drivers, so values below SOO pF
may cause some driver instability. Excessive input
capacitance will degrade the slew mode performance
of the drivers.
When the motor voltage is changing polarity, the crossoverprotection circuits at outputs OUTA-OUTD ensure
that the maximum MOSFET gate drive is less than 2V
(the crossover separation threshold), as illustrated in
Figure 5. The thresholds of the MOSFET devices
chosen should be as large as possible to minimize
conduction in this region. If the device thresholds are
significantly less than the crossover separation
threshold, the Nand P channel devices in each leg of
the H-bridge will conduct simultaneously, causing unnecessary power dissipation.
The BRK output, which is pulled low during normal
operation, floats during a power failure. This allows an
external transistor to be enabled lor spindle motor
braking. An external AC delay may be added to defer
braking until head retraction is complete, since the
spindle motor is required to generate the supply voltage during retraction.
im
JSm
Km
im
Armature current (A)
ro
Motor speed (rad/s)
J8
Moment of inertia of
rotor (Kg. M2 )
Km
Torque constant (V.S.)
e
Back E.M.F. (V)
Lm
Winding inductance (H)
Rm
Winding resistance (
Nomenclature used is for rotary motor
FIGURE 3: Equivelant Circuit For Fixed Field DC Motor
7-10
n
SSI32H569
Servo Motor Driver
WINDING IMPEDANCE
LOOP COMPENSATION
MECHANICAL RESPONSE
CURRENT SENSE
FIGURE 4(A): Transfer Function of SSI32H569
in Typical Application with Fixed Field DC Motor
MECHANICAL RESPONSE
_'-J
/1
1
-
RIN
1<--
.~
/
LOOP COMPENSATION
"/
1
1+
Km2
17
SCL(Rs+ Rm}
SJe (Rs + Rm)
CURRENT SENSE
V
Rs
4 RF
JeR m
-- «
Km 2
i"
Rm
Lm
FIGURE 4(8): Simplified Transfer Function of
SSI 32H569 In DC Motor Application
7-11
"/
II
SSI32H569
Servo Motor Driver
MOSFET GATE DRIVE
,
vee
-
- - - -,- - - - - - - - - -1- -
-
-
-
-
-
-
-
-
-
-
-
-
•
I
(CROSSOVER
SEPAAATJOIII
TtflESHa..Ol
.
ERR
(ERROR SIGNAL INPUT)
"'lEF
(HORIZONTAL SCAlf IS GREATlY EXPANDED)
FIGURE 5): Crossover Protection
RVlIM
(Q)
1 MEG
+ "'
-N.
+
300K
H -:- r-~ '. -: -d
-:1
T ..., -1-
4-
~
Rs
=.5Q
T
-1- I-
..j..
'!'lJJJ_'_'_'_'_'_I_LI LL
IH-
200K
.T ..., -
:~~ -+
100K _
r
T
-I -1- ,-
~-,
-1- ,-
1'-
R s =.5 Q
,
,-,
,
.r
,-
I
1 f T
rrr
r r r
100K
r- t- t- t- t-t -+ -+ .., -I -I - ' ,- t- 1- t- t- I- +-1--+-+--1-1
-!-!-!-!-!-I-I-~~
-'- ...l -I
....J.J _! _1_1_ 1_ 1_ L I- 1- .l-
T -t -t ., -I -I -1-;-;-
-+
--'~""":'"
6
-II
T -, -
T .., -1- r- T .., -1- r- j 4-",- 'r- T . , ... -I _,_ '- ... -I _,_ '- .. -I _'~"'--'" -I _
_I _,_ L J. J _,_ ,_ J:-':J _
5
T "1 I I
. T , 1 -, -, -,
_ .L J _,_ L J.
4
'!'l..!J-.J_'_'_'_'_I_i_'_ !...!..
I I I I I I I I I I I r I I I
. 'I 'I "I '"j -, -, - - -, - ,- ,- ,- I" I" I"
·Tlll~.
-4 -1_ I- -'- -I -
-:- -: -:- :- ~- -: =;~~. -: -:- ~ -:- -:-
T -, -,-
+ _________-,_-,
1. j J.J -' _'_I_I_'_I_L 1_ I L L
~ -1- I- + --I -1- I- + -4 -
L.J _,_ L 1. .J _,_ L .l .J_
_ L .J _,_
SOOK
RVlIM
(n)
7
I MAX
(AMPS)
'MAX
(AMPS)
FIGURE 6: RVLlM To Ground Typical Motor
Current limit
FIGURE 7: RVLlM To VREF Typical Motor
Current Limit
7·12
SSI32H569
Servo Motor Driver
1.0 ,.-_ _ _ _ _......._ _ _ _ _-.-_ _---,.-_-, 100K
--------
0.1
10K
ASSUMPTIONS:
R, = 0.2n
RF = 10K
RL (a)
C L (I'F)
Rm =30
Lm =600j.IH
1K
.01
.001 ~----------------~-1'00
1K
100
10K
100K
BANDWIDTH
(Hz)
FIGURE 8: Typical Motor Driver Compensation
II
1.7
__ ..... __ .+
__
I
I
1- _ _ 1 _ _ -1 __
I
I
: 'LIMIT:.
+
I
3.4a~p
I
Ry
.10KQ
Km
• .Slbs/amp
Mass • .00026 SLUG
I
I
.1
-
-
-l I
30
-
4R,
I
: 'LIMIT
1- 4 amp
+ - -
I- -
I
I
40
• VUM
'llolrr
-1- I
50
V. AX
60
..... I
70
-
+- - I
I- I
80
90
-
100
( ......
/ ... )
FIGURE 9: Typical Motor Velocity limit
7-13
pa.a
EN
80C51
VPD
X1
J~z
----'-
0
ADO-7
1 - - -.....--«
LOWV
+ 12V
~ CSyp
VPA
C BYP
ALE
A15
cs
RBIAS
RD
RD
AGND
WR
WR
INT
INT
SE3
FP1
DGND
DGND
Vee
0.1 ~
~
....
F
~~~t
READ HEAD
C vca
N
Q
0
IN.
SYNC
IN·
vca
OUTB
RP4
FP4
.:~ ~ I
RV
CPK
CAD
W
BP1
'
TW
,j
FV2
I
FV3
I I
BP2
SSI32H622D
LF
FV1
T vw I SSI 32H621 0
EOUT
,m----'!'>--~----4>----1 SOUT
IW--l
C L3
I
VREF
f
+5V
~I-I
JW
;OMPENSATION
AGND
RVCO
OUTC r·--------------------------------------~
VEL·
VELOCITY
LOOP FILTER
FV4
CAGC
.,..
=1
Cv
SYNC
CLOCK FP3
CAZ
C1
VEL
VELOCITY
INTEGRATOR
ERR
RSRK
SSi32H569
I
ERR·
BRK
TO SPINDLE MOTOR
BRAKING TRANSISTOR
ERR+
VREF
VREF
ROS
SERVO
DEMODULATOR
SERVO
MOTOR DRIVER
SERVO
CONTROLLER
CBYP
c
<"
CD
~
H·BRIDGE
MOTOR
DRIVER
FP2
CLD
C2
RW~
THR
N
~
=+~S'L
Rp2
s:::t
0<11
_(7)
0<0
I
SE1
RESET
VDO
.5V
+ 12VTO
SPINDLE
MOTOR
SE2
POSITION
LOOP FILTER
VCC
GND
-
O and reset otherwise.
7
NO
Active HIGH when N>-Q and reset otherwise.
The corresponding interrupt events TRKCS INT, COUNT INT and BURST INT will be reset when this register
is read by the f.lP. Also, the TRKCS, COUNT and BURST bits in this register are reset after being read.
7-28
SSI32H4633
Hybrid Servo &
Spindle Controller
ADC ADDRESS/DATA REGISTER
Address: 3
Access: Read/Write
Reset: Undefined
Description: When Written, the least significant 4 bits of the register define the analog input to the 8-bit AID
converter. After conversion, the 8-bit digital word of the analog input is stored into the register.
Register contents when Written:
BIT
NAME
DESCRIPTION
0
1
ADC
ADC
ADC
ADC
AID Converter Input Select. These 4 bits define the analog input to
the AID converter per table below:
2
3
SELO
SEL1
SEL2
SEC3
BIT3
BIT2
BIT1
BITO
ADCINPUT
ADC Vref
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BURST1
VREF
1
BURST2
VREF
1
0
BURST3
VREF
1
1
BURST4
VREF
1
0
0
1
PES1
VREF
PES2
VREF
1
SOUT
VREF
1
SENSE
SENSEREF
1
0
0
0
0
1
0
1
0
1
0
1
0
ADCIN
VREF
1
1
VREF
VREF
1
1
0
0
1
0
1
0
SUM1
VREF
1
1
1
1
SUM2
VREF
1
1
1
4
1
0
0
1
1
PESO
VREF
N
NOREF
0
NOREF
ERR
VREF
X4 Enable. When set HIGH, the analog input to the AID converter will
be multiplied by 4 before converted into a digital value.
X4
-
5,6,?
1
1
1
Undefined
Register contents when Read:
BIT
NAME
DESCRIPTION
O..?
ADCO .. ?
Digital output of the AID converter in 2's complement format. ADC7
corresponds to the sign bit.
7-29
I
SSI32H4633
Hybrid Servo &
Spindle Controller
TRACK COUNT AND HYBRID SERVO CONTROL REGISTER
Address: 4 and 5
Access: ReadlWrite
Reset: 00
Description: In a hybrid servo application, the dedicated servo channel is supported by a 12-bit track crossing
counter with a 4-bit hybrid control register. The counter is preset by the ~p and counts down by one whenever
the head crosses a track boundary. The LSB B bits of the counter are defined at register 4 as follows:
BIT
NAME
DESCRIPTION
0.. 7
TRACKO .. 7
LSB of the track crossing counter 0..7. When written, these bits preset
the track counter. When read, they reflect the counter state.
The MSB 4 bits of the counter along with the hybrid control bits are latched when the LSB B bits are read. The
hybrid control bits, QUADO, QUAD1, SELECT Q and CALIB are ''write only." They are defined at register 5 as
follows:
BIT
NAME
DESCRIPTION
0 .. 3
TRACKB .. 11
MSB of track crossing counter B.. 11. When written, these bits preset
the track counter. When read, they reflect the counter state.
4
QUADO
QUAD1
Quadrant Select. These 2 bits select the quadrant per table below:
5
QUAD1
QUADO
Quadrant Selected
0
0
-Q
0
1
1
0
1
N
-N
Q
1
6
SELECTQ
Quadrant Select Enable. Select quadrant with QUADO and QUAD1
when set HIGH.
7
CALIB
Calibration Enable. When set HIGH, the device is in the calibration
mode in which analog inputs Nand Q are tied to a DC reference level,
NQREF; the analog input SERIN is tied to the DC reference level,
SEREF.
ERROR DAC DATA REGISTER
Address: 6
Access: Write
Reset: 00
BIT
NAME
DESCRIPTION
0..7
DACO .. 7
Digital input to the D/A converter in 2's complement format. DAC7
corresponds to the sign bit.
7-30
SSI32H4633
Hybrid Servo &
Spindle Controller
EMBEDDED SERVO GAIN CONTROL REGISTER
Address: 7
Access: Write
Reset: 00
BIT
NAME
DESCRIPTION
0
GAINO
Embedded Servo Burst Amplitude Gain Select.
1
GAIN1
These two bits define the gain setting for the embedded servo differential amplifier per table below:
2
3
4
5
GAIN2
GAIN3
GAIN4
GAIN5
Gain, dB
GAIN1
GAINO
0
0
-6
0
1
-3
1
0
0
1
1
3
Embedded Servo Burst Amplitude Gain Select.
These four bits define the gain setting for the sample/hold amplifier per
table below:
GAINS
GAIN4
GAIN3
GAIN2
Gain,dB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
0
1
1
0
0
0
1
1
1
0
1
6
SYNC SEL
Sync Input Select. When set HIGH, the frame rate to sample dedicated
quadrature position signals Nand Q is derived internally from SYSCLK.
Otherwise, it is provided externally from the servo demodulatorthrough
SYNC and VCO inputs.
7
TCHE
Track Clock Hysteresis Enable. When set HIGH, an internal timing
hysteresis is added for deriving the TRKCK output.
7-31
I
SSI32H4633
Hybrid Servo &
Spindle Controller
TRANSCONDUCTANCE, PRESCALER & MODE CONTROL REGISTER
Address: 8
Access: Write
Reset: Bit 4 and 5 only
Bit
Name
Description
0
TEST
Test Mode Enable. When set HIGH, the device is in the test mode
where the testing time for the spindle motor speed control function is
shortened.
1
SLEEP
Power-down Mode Enable. When set HIGH, the device is in the powerdown mode where all analog circuitry is de-biased, the clock is disabled
and the output drivers are pulled to logical HIGH.
2
TGAINO
TGAIN1
Transconductance Select. The transconductance gain of spindle
motor lower drivers is defined per table below:
3
4
5
6
7
SCALEO
SCALE1
MODEO
MODE1
TGAIN1
TGAINO
Gain
0
0
0
1
2
4
1
0
1
1
8
16
SYSCLK Prescaler. To accommodate different system clocks which
may be used, the prescaler selects a proper divider to generate a fixed
clock at 500 kHz per table below:
SCALE1
SCALEO
SYSCLK(MHz)
0
10
20
0
0
1
Divider
16
1
0
8
6
1
1
4
8
12
Spindle Mode Control. These two bits define the number of motor
poles per table below:
MODE1
0
MODEO
POLES
0
4
COMMUlINDEX
12
0
1
8
24
1
0
12
36
1
1
N/A
N/A
7-32
SSI32H4633
Hybrid Servo &
Spindle Controller
EMBEDDED SERVO TIMING WINDOW CONTROL REGISTER
Address: 9
Access: Write
Reset: 00
Description: The embedded servo position burst timing controller generates four timing windows. The sample
control register matches these timing windows with four SAMPLE/HOLD circuits. The ~P writes into the register
a control pattern which will provide a necessary sampling to compare the required bursts in a proper polarity and
sequence. In this manner, the ~P can mix and commutate the bursts so that the position error signal is always
in the same direction.
BIT
NAME
DESCRIPTION
0,1
WDSH1
Define timing window for SAMPLE/HOLD 1. Bit 0 is LSB.
2,3
WDSH2
Define timing window for SAMPLE/HOLD 2. Bit 2 is LSB.
4,5
WDSH3
Define timing window for SAMPLE/HOLD 3. Bit 4 is LSB.
6,7
WDSH4
Define timing window for SAMPLE/HOLD 4. Bit 6 is LSB.
The timing window is selected per table below:
StH Timing Window
MSB
LSB
0
0
Timing window 1
0
1
Timing window 2
1
0
Timing window 3
1
1
Timing window 4
7-33
I
SSI32H4633
Hybrid Servo &
Spindle Controller
PA
I
SAM>LEJ)
!
N>O
N,..Q
OR
00
OUADO
QUAD1
PESO
Te,",
FIGURE 2: Dedicated Servo Position Processor
""N~
CALIS _
DlfF
PEAK
OETECTQR
fWP
SEJ£f
-
2
GAIN 0-1
LATCH
HOlD
BUlST]!lEO
£E-
vrnJ[T
WOOUT
FfII
SAMPLE WlNOOW 1 •• "
SE..,
SW
S"-'
'--._J-_'SEl'
FIGURE 3: Embedded Servo Burst Amplitude Processor & Timing Controller
7-34
SSI32H4633
Hybrid Servo &
Spindle Controller
ERR
SOUl
\/RETRACT
\/BOOGE
I
I
51:? SE1
'RREF C:;~----+y
VBEMFVBYPAOUTR
>---~-+~>---~------4r----~~'
HENABlE
RETRACT
>-----~----~-----cJ~
\/REF
HENAIll,
RETRACT
SE,
FIGURE 4: Servo Position Error Amplifier
II
VREF
PWR~)---+-----+-------------------------~
PSB
RETRACT
c::>---------I--l"-
>----c::> SYSRST
PSV c::>-------+-~
IBRC>-------l:==.::J
"'AS
RCRST
• These gates are powered from VBPYv;a pull-up resistors.
FIGURE 5: Voltage Fault & Servo Head Retract Logic
7-35
SSI32H4633
Hybrid Servo &
Spindle Controller
FIGURE 6: Spindle Motor Speed Control
---7-----(
POWER-DOWN
ANALOG
CIRcurrs
X4
VREF~I
ERREF
NOREF
UP
SENSEREF
INTERFACE
fo----<:::JBUSMOOE
fo------<:::::JIID
fo------<:::::JWIl
SElO... 3
fo-----<:::::J~
READ
f----{=>m
L~~~~j+__-"W",R!CrrE"-L_ _ _ _ _~-";'<-I~::=:>AD (0:7)
FIGURE 7: Data Acquisition & Microprocessor Bus Interface
7-36
SLEEP
-.......s-~op--<:::J PWRDN
SSI32H4633
Hybrid Servo &
Spindle Controller
3031
0
1
2
3
..
5
6
7
8
9
10 11 12 13 ,,, 15 16 17 18 19 20 21 22 23 24 25 26 Zl 28 29 30 31
0
1
2
3
..
5
8
7
8
9
10 11 12 13 14 15
VCO
SYNC
SAMPLE N
-+-----,
a¢=========+xllll
===========
liZZ2un
L
SAMPLEa..J
FIGURE 8: Dedicated Servo Timing Diagram
~
j4-'EXDW
EXDET~~---------------------------------------------------------
SAMPLE
I
--ii-----'
ACQUISITION - - I f - - - - - - - '
DISCHARGE --1-----'
~-------------------------4INT--------------------------~·~1
BURST READY
-t;=============~;;;=============;:j-'
XWG
"I
~-t-DH-L-~---------------------'XHL--------------------------;·I
~I
---'r----
______________________________________
FIGURE 9: Embedded Servo Timing Diagram with Internal Timing Source
7-37
SSI32H4633
Hybrid Servo &
Spindle Controller
~
f4-i EXOW
Exoa--f1~--------------------------------------------
~~po~sTI
SAMPLEX
-;----111
r_I'-_ _....Jr_IL_ _____'r_IL_ _ _ _ __
:tN~~~N
ACQX_r-_ _
BURST READY
~--~r-IL------'r-IL------'r-IL------'r-I~~--
-+__-------.----------------------------------------+-------'
I
tOWG
-~
WGOUT
RW
,
---...i f-oI-- tOHL
t XHL
~----~.L I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
FIGURE 10: Embedded Servo Timing Diagram with External Timing Source
ALE
tASEH
~
AD (0:7)
(READ)
JI[j
RWD
~
ADeO:7)
(WRITE)
'I'm
RWD
FIGURE 11: Intel Microprocessor Bus Interface Timing Diagram
7-38
SSI32H4633
Hybrid Servo &
Spindle Controller
AS--.../
~----"'"
~~AS~~~A!!:H~
AD (0"1 - - - - - . . . :
ADDRESS
DDA~
-1---------,-+-----:"
~DHRS1-'
.
DATA
~--+---
(....01
J--------'ASDS---'-----,1~==!!!DS!!!!PW!!!:.=~
D S - - - - -_ _ _+-_ _ _ _ _ _ _ _ _.../
'C!I _ _ _ _" '
FIGURE 12: Motorola Microprocessor Bus Interface Timing Diagram
7-39
0: INTERRUPT
CONTROUSTATUS
1: SPINDLE
CONTROUSTATUS
WRITE
2: SERVO
CONTROUSTATUS
READ
3.:ADC
CONTROUSTATUS
#
WRITE
READ
#
#
WRITE
#
WRITE
0
COMMUINT
COMMUINT
0
liJ5liRI(
LOCK
0
HENABLE
0
ADCSELO
ADCO
0
TRACKO
TRACKO
1
LOCK INT
LOCK INT
1
UNIPOLAR
OV ER
1
SWON
1
ADCSELl
ADCl
1
TRACKl
TRACKl
2
BURSTINT
BURSTINT
2
INDEXSEL
COMMU
2
3
TRKSINT
TRKS INT
3
MENABLE
PERCHKS
3
4
COUNTINT
COUNTINT
4
ADVANCE
PERCHK4
5
5
STATO
6
6
STATl
7
STAT2
7
~
MSTINT
MSTINT
5: TRACK COUNT MSa &
HYBRID SERVO CONTROL
#
WRITE
READ
WRITE
READ
#
WRITE
2
ADCSEL2
ADC2
2
TRACK2
TRACK2
TIMING
TRKS
3
ADCSEL3
ADC3
3
TRACK3
TRACK3
4
DIBURST
COUNT
4
X4
ADC4
4
TRACK4
TRACK4
PERCHK3
5
LEAD
5
ADC5
5
TRACK5
TRACKS
PERCHK2
6
TlMO
NO
6
ADC6
6
TRACK6
TRACK6
7
TlMl
N~
7
ADC7
7
TRACK7
TRACK?
7: EMBEDDED SERVO
GAIN CONTROL
READ
#
WRITE
READ
8: TRANSODNDUCTANCE
PRESCALER & MODE CONTROL
#
WRITE
READ
9: EMBEDDED SERVO TIMING
WINDOW CONTROL
#
WRITE
0
TRACK8
TRACK6
0
DACO
0
GAINO
0
TEST
0
WDSELO
1
TRACK9
TRACK9
1
DACl
1
GAINl
1
SLEEP
1
WDSal
2
TRACK10
TRACK10
2
DAC2
2
GAIN2
2
TGAINO
2
WDSEL2
3
TRACKll
TRACKll
3
DAC3
3
GAIN3
3
TGAINl
3
WDSEL3
4
OUADO
4
DAC4
4
GAIN4
4
SCALEO
4
WDsa4
5
OUADl
5
DAC5
5
GAINS
5
SCALEl
5
WDSEL5
6
SELECT 0
6
DAC6
6
SVNcsa
6
MODEO
6
WDSEL8
7
CALiB
7
DAC7
7
TCHE
7
MODEl
7
WDSEL7
------
READ
BURST
6: ERROR DAC DATA
#
READ
(J)::E:en
4:TRACK COUNT LSB
--
-- -
-
FIGURE 13: SS132H4633 Register Map
-_.. __ ... -
--
READ
,,'<
en
_. c::T :::s~W
9:-0:1\)
CD·::Ii
.. en
OCD~
O~· w
:::s18V
IBEMF
-
5.0
rnA
CONDITIONS
..
..
MIN
Digital input voltages
VIND
-0.3
VDD+0.3
V
Analog input voltages
VINA
-0.3
VDD+0.3
V
Storage temperature
Tstg
"65
150
Lead temperature
TI
-
300
°c·
°C
7-46
SSI32H4633
Hybrid Servo &
Spindle Controller
OPERATING ENVIRONMENT LIMITATIONS
The recommended operating conditions for the device are indicated in the table below. Performance
specifications do not apply where the device is operating outside these limits.
PARAMETER
SYMBOL
MIN
NOM
MAX
UNIT
Supply voltage applied at
VPA,VPB,VPC,VPD,VPG
VDD
4.75
-
5.25
V
Signal ground applied at
VNA,VNB,VNC,VND,
VND2,VNG
GND
0.0
-
0.0
V
Bridge voltage applied
atVBRIDGE
VBRIDGE
4.75
-
13.2
V
Bypass voltage applied
at VBYP
VBRIDGE
-VBYP
0.0
-
0.8
V
Back-emf voltage applied
atVBEMF
VBRIDGE
-VBEMF
-5.0
-
0.8
V
Ambient temperature
TA
0.0
70.0
°C
±0.01
%
100
pF
kQ
CONDITIONS
System clock (10 MHz, Max)
Fc
Capacitive load on digital
outputs
CL
-
-
Analog input impedance
Rin
100
-
-
-
-
20
of
Rout
10
-
-
kQ
Cout
-
-
40
pF
RBIAS
-
-
±1
%
Cin
Load on analog outputs
Bias resistor (22.6 kQ, Typ)
DC CHARACTERISTICS
The following electrical specifications apply to the digital input and output signals over the recommended
operating range unless otherwise noted. Positive current is defined as entering the device. Minimum and
maximum are based upon the magnitude of the number.
Supply current
IDD
VDD=5.25V
Output logic "I" voltage
Voh
10h=-0.4 mA
VDD=4.75V
2.4
-
Output logic "0" voltage
Vol
101=1.6 mA
VDD=4.75V
-
-
0.4
V
Input logic "1" voltage
Vih
VDD=4.75V
2.0
V
Vii
VDD=4.75V
-
-
-
Input logic "0" voltage
0.8
V
-
Normal mode
Power-down mode
-
-
7·47
50
mA
5
rnA
-
V
II
SSI32H4633
Hybrid Servo &
Spindle Controller
ELECTRICAL SPECIFICATIONS (continued)
DC CHARACTERISTICS (continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
Input logic "1" current
lih
Vih=5.25V
VDD=5.25V
-
-
10
~
Input logic "0" current
iii
ViI=O.O
VDD=5.25V
-
-
-10
~
Input capacitance
Cin
-
-
10
pF
MIN
NOM
MAX
UNIT
N,O comparator hysteresis
5
-
30
mV
Commutator comparator
offset
-
-
±30
mV
N,O input voltage
w.r.t GND
0.5
-
3.7
V
NOREF w.r.t. GND
1.9
-
2.9
V
-
-
±1.1
V
0.96
1.0
1.04
VN
-
-
±50
mV
60
85
120
kHz
SERIN w.r.t. GND
2.0
VDD
V
SEREF w.r.t. GND
2.0
3.0
V
FUNCTIONAL CHARACTERISTICS
Dedicated Servo Position Processor
PARAMETER
CONDITIONS
N,O input voltage
w.r.t NOREF
Channel gain from N,O
to PESO
PESO offset
PESO output comer frequency
Embedded Servo Burst Amplitude Processor
DC offset at PES1,PES2
BURST1=BURST2=0.5V
BURST3=BURST4=0.5V
-30
-
DCoffsel at SUM1 ,SUM2
BURST1 =BURST2=0.5V
BURST3=BURST4=0.5V
0
-
SERIN inputvoltage
Channel gain=-6 dB
0.0
swing w.r.t. SEREF
Channel gain=O dB
0.0
Servo burst frequency
0.5
Input impedance at
20
-
SERIN, SEREF
7-48
2.0
Vp
1.0
Vp
2.0
MHz
-
kQ
10
pF
20
mV
-250
mV
SSI32H4633
Hybrid Servo &
Spindle Controller
Embedded Servo Burst Amplitude Processor (continued)
MIN
NOM
MAX
UNIT
Differential gain error
at PES1 ,PES2,SUM1 ,SUM2
-
-
±0.1
dB
Integral gain error
at PES1 ,PES2,SUM1 ,SUM2
-
-
±1.0
dB
PES1 ,PES2 output swing
w.r.t. VREF
-
-
±1.1
V
SUM1 ,SUM2 output swing
w.r.t. VREF
-
-
1.1
V
10
-
-
kQ
40
pF
PARAMETER
CONDITIONS
Allowable load at PES1, PES2,
-
SUM 1,SUM2 to VREF
Embedded Servo Timing
The following timing specifications are applied when the internal servo timing block is selected by pulling the
TIMING bit to logical LOW. Timing measurements are defined in Figure 3 and made at 50% VDD with 50 pF
load capacitances for all pins, unless otherwise noted.
PARAMETER
SYMBOL
Burst cell time
TIMO='O'
tBST
MIN
NOM
MAX
UNIT
-
5.0
TIMO='O'
TIM1='1'
-
8.0
TIMO='1'
TIM1='1'
-
10.0
-
J..IS
TIM1='0'
0.5
-
ISST
J..IS
TIMO='1'
TIM1='O'
EXDET pulse width
tEXDW
Internal first sampling time
from EXDET rise
LEAD='O'
tSPD
LEAD='1'
Sampling pulse width
TIMO='O'
TIM1='0'
TIMO='1'
TIM1='0'
TIMO='O'
TIM1='1'
TIMO='1'
TIM1='1'
6.0
Ils
J..IS
J..IS
1.0
-
1.7
J..IS
(tBST+1.0)
-
(tBST+1.7)
Ils
-
2.0
-
J..IS
-
3.0
-
J..IS
5.0
-
J..IS
7.0
J..IS
2.0
-
0.75
-
J..IS
0.25
-
J..IS
tspw
Acquisition pulse width
tAPW
Discharge pulse width
tDIS
Nonoverlapping time between
sampling & acquisition pulses
tNON
7-49
J..IS
SSI32H4633
Hybrid· Servo &
Spindle Controller
Embedded Servo Timing (continued)
PARAMETER
SYMBOL
Burst ready interrupt from
EXDET rise
DIBURST='0' LEAD='O'
DIBURST='1' LEAD='O'
DIBURST='0' LEAD='1'
DIBU RST ='1' LEAD='1'
tiNT
WGOUT & RW delay time
from EXDET rise
tDWG
WGOUT & RW hold time
from EXDET rise
DIBURST='0' LEAD='O'
DIBURST='1' LEAD='O'
DISURST='0' LEAD='1'
DIBURST='1' LEAD='1'
tXWG
HOLD delay time from EXDET
rise
LEAD='O'
LEAD='1'
tDHL
HOLD hold time from EXDET
rise
DIBURST='0' LEAD='O'
DIBURST='1' LEAD='O'
DIBURST='0' LEAD='1'
DIBURST='1' LEAD='1'
tXHL
MIN
NOM
MAX
UNIT
(4tBST+S.2)
(2tBST+S.2)
(StB-.£T+S.2)
(3tBST+S.2)
-
(4tBST+S.9)
(2tBST+S.9)
(StB-.£T+S.9)
(3tBST+S.9)
~
0.1
~
(4tBST+1.7)
(2tSST+ 1. 7)
(StBST+ 1. 7)
(3tBST+ 1.7)
~
-
0.0
-
(4tBST+1.0)
(2tBST+1.0)
(StBST+1.0)
(3tBST+1.0)
-
0.2
-
(tBST+0.2)
(4tBST+1.0)
-
(2ta~n+ 1.0)
-
(StSST+ 1.0)
(3tBST+ 1.0)
~
~
~
~
~
~
0.7
~
(tBST+0.7)
~
(4tSST+1.7)
(2tSSI+ 1. 7)
(StBST+ 1. 7)
(3tBST+ 1.7)
~
~
~
~
The following timing specifications are applied when the internal servo timing block is selected by pulling the
TIMING bit to logical HIGH. Timing measurements are defined in Figure 4 and made at SO% VDD with SO pF
load capacitances for all pins, unless otherwise noted.
-
5.0
~
-
~
2
-
-
tNON
0.0
-
-
~
Burst ready interrupt from last
ACQXfall
tiNT
5.2
-
5.9
~
WGOUT & RW delay time from
EXDETrise
tDWG
0.0
-
0.1
~
EXDET pulse width
tEXDW
0.5
SAMPLEX delay time from
EXDET rise
tSPD
0.2
SAMPLEX pulse width
tspw
3
ACQX pulse width
tAPW
Nonoverlapping time between
SAMPLEX & ACQX pulses
7-50
~
~
SSI32H4633
Hybrid Servo &
Spindle Controller
Embedded Servo Timing (continued)
PARAMETER
SYMBOL
MIN
NOM
MAX
UNIT
WGOUT & RW hold time from
last ACQX fall
tXWG
1.0
-
1.7
J..IS
HOLD delay time from first
SAMPLEX rise
tDHL
0.2
-
0.7
J..IS
HOLD hold time from last
ACQXfall
tXHL
1.0
-
1.7
J..IS
Head Positioner MOSFET Driver
PARAMETER
CONDITIONS
MIN
NOM
MAX
VRETRACT voltage
VBEMF = 3V
0.3
0.9
V
VBEMF = 12V
0.4
-
1.2
V
Retract offset
VBEMF=3V
-
UNIT
VRETRACT = 0.5V
-70
mV
VBYP = 4V to 13V
-70
-
50
VBEMF= 6V
70
mV
VBEMF = 12V
IAOUTR<1mA
-150
-
150
mV
1.5
-
V
-
V
-
-
1
JJA
-
V
Voh at AOUTR
VBEMF = 4V VBYP = 4V
loh
= -1mA
VBEMF = 3V VBYP = 4V
1.3
Leakage current at AOUTR
RETRACT = LOW
AOUTR = OV to 14V
Voh at AOUTA, AOUTC
loh = -1 mA
VBRIDGE-1.5
-
VBRIOGE-0.1
-
-
1
V
-
V
Voh at AOUTO
JJA
101 = 10 JJA
loh =-10 JJA
loh =-10 JJA
Vol at AOUTB, AOUTD
101
loh = -1
V
VBYP-0.5
-
= 1 mA
-
-
1
V
101 = 10 JJA
-
-
0.2
V
±3
mV
SOUT/(SE1-SE2)
3.9
-
4.1
V/V
SE1/ERR, SE3/ERR
14.0
-
15.4
V/V
ERRAMP input offset
-
-
±10
mV
1000
-
-
V/V
-
-
45
f..1S
20
-
-
kQ
Vol at AOUTA, AOUTC
Voh at AOUTB
VBRIOGE-0.5
Input offset at SOUT
ERRAMP gain
Output crossover time
CL = 600 pF at AOUTA,C
CL = 150 pF at AOUTB,D
PFET VTH = -2V
NFETVTH = 2V
RX = 50 kQ
Input impedance at SE1,
SE2,SE3
7-51
V
II
SSI32H4633
Hybrid Servo &
Spindle Controller
Head Positioner MOSFET Driver (continued)
PARAMETER
CONDITIONS
Output resistance at SOUT
Analog switch one
resistance at SWIN
MIN
NOM
MAX
UNIT
-
-
350
n
600
n
-
-
100
n
1.0
-
1.4
V
MIN
NOM
MAX
UNIT
2.0
-
-
V
-
-
800
n
550
n
0.2
-
1.2
V
-80
20
mV
2.27
2.34
2.41
V
-
-
±15
mV
SYSCLK duty cycle
40
-
60
%
EXTINDX pulse width
200
-
ns
3
-
I1S
Output resistance at ERR
Output voltage at VX
Voltage Reference and Voltage Fault Circuit
PARAMETER
CONDITIONS
VPB voltage for SYSRST
& RCRST in operation
On resistance at RCRST
VPB>3.5V
VBYP>4V
VPB>3.5V
VBYP>10V
RCRST input threshold
VBYP=4V
IBR voltage w.r.t. VREF
Output voltage at VREF
11I1<10J.IA
PSB,PSV comparator offset
Spindle Motor Speed Control
Timing resistor at EXTRC
0.01
-
10
Mn
Timing capacitor at EXTRC
100
-
-
pF
Delay time variation relative
to TO'
-
-
±5
%
Advance pulse width
Vii at BRAKE
VBEMF = 5V
0
V
VBEMF = 5V
1.5
-
0.3
Vih at BRAKE
-
V
Output voltage swing at PROP 'out<0.1mA
& INTEGRAL
0
-
VBIAS±5%
V
DAC step size at PROP &
INTEGRAL
32
-
39
mV
-
-
300
n
Output impedance at PROP & 0.5V
J OUTPUT1 (+)
J OUTPUT2 (-)
I
8
NlC
INPUT2(-)
2
7
VCC
SEE NOTE
3
6
OUTPUT2(-)
GND
4
5
OUTPUT 1 (+)
GND
S-PlnSON
CAUTION: Use handling procedures necessary
for aSiatic sensllive component
1292 - rev.
7-59
I
SSI32H6110
Differential Amplifier
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS - operating above maximum ratings may damage the device
PARAMETER
,
RATING
UNIT
Power Supply Voltage (VCC)
7
V
±1
V
Storage Temperature Range
-65 to 150
°C
Operating Ambient Temperature, Ta
10 to 100
°C
Operating Junction Temperature, Tj
10 to 135
°C
Differential Input Voltage
-
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITIONS
Supply Voltag~ (VCC)
MIN
NOM
MAX
UNIT
4.50
5.0
5.50
V
Input Signal (Vin)
1.0
mVpp
Ambient Temperature
0
+100
°C
Operating Junction Temperature
0
+135
°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
RL = 1200
Vin = 1mVpp, RL = 1200
Ta = 25°C, f = 1 MHz
225
300
375
mV/mV
RL = 1000
Vin = 1mVpp, Rl = 1000
Ta = 25°C, f = 1 MHz
200
250
300
mV/mV
Bandwidth (3 dB)
Vin = 1mVpp, CL = 15 pF
RL =1200
10
30
Gain Sensitivity (Supply)
Ta = 25°C
Gain Sensitivity (Temp.)
15°C < Ta < 55°C
Input Noise Voltage
Input Referred, Rs = 0
Input Capacitance (Differential)
Vin = 1 mVpp, f = 5 MHz
Gain (Differential)
0.6
Input Resistance (Differential)
200
MHz
4.0
%IV
-0.16
%/OC
0.85
nV/YHz.
35
pF
0
Common Mode Rejection
Ratio (Input Referred)
Vin = 100 mVpp, f = 1 MHz
60
dB
Power Supply
Rejection Ratio (Input Referred)
Vin = 100 mVpp, f = 1 MHz
54
dB
7-60
SSI32H6110
Differential Amplifier
ELECTRICAL CHARACTERISTICS, (Continued)
Unless otherwise specified, recommended operating conditions apply.
PARAMETER
CONDITIONS
MIN
Input Dynamic
Range (Differential)
AC input voltage where
gain falls to 90% of its small
signal value, f = 5MHz,
RL = 1200
5.0
Output Offset
Voltage (Differential)
Inputs shorted
Output VoHage (Common Mode)
Inputs shorted together and
Outputs shorted, RL = 1200
NOM
MAX
UNIT
mVpp
-400
±50
+400
mV
veC-O.56
vcc-o.ss
VCC-1.2
V
10
pF
34
rnA
Single Ended Output Capacitance
Power Supply Current
VCC =5V
23
Input DC VoHage
Common Mode
2.0
V
APPLICATION INFORMATION
RECOMMENDED LOAD CONDITIONS
Vee
1.
Input is directly coupled to the head.
2.
Ce's are AC coupling capacitors.
3.
RL's are DC bias and termination resistors, 1200
recommended.
4.
REO. represents equivalent load resistance.
5.
Ceramic capacitors (0.1 ~F) are recommended for
good power supply noise filtering.
Req
Ce
Req
GND
FIGURE 1: Connection Diagram
7-61
II
SSI32H6110
DifferentiatAmplifier
PACKAGE PIN DESIGNATIONS
(Top View>.
INPUT 1 (+)
8
N/C .(See N01e)
INPUT2(-)
2
7
VCC
SEE NOTE
3
6
OUTPUT 2 (-)
GND
4
5
OUTPUT 1(+)
8-Pln SON
NOTE : N/C pin must be left open and not connected to any circuit etch.
ORDERING INFORMATION
PART DESCRIPTION
ORDERING NUMBER
PACKAGE MARK
5S1 32H611 0 Differential Amplifier
a-Pin SON
32H6110-CN
H6110
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of pa1ents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Sys1ems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1292 - rev.
©1990 Silicon Systems, Inc.
7-62
SSI32H6210
Servo Demodulator
'#'§"iUUf'H·"6'
February 1992
DESCRIPTION
FEATURES
The SSI 32H6210 Servo Demodulator is a bipolar
device intended for use in Winchester disk drives with
dedicated surface head positioning systems. It processes a di-bit quadrature pattern read from the servo
surface by a preamplifier, such as the SSI32H101 or
SS132H116, and generates normal and quadrature (N
and Q) position reference signals. These signals provide the servo controller with position errorfeedback. A
complete position control system can be realized with
the SSI 32H6210 and its companion devices, the
SSI 32H6220 Servo Controller and SSI 32H6230
Servo Motor Driver.
•
•
•
The SSI 32H621 0 incorporates an input amplifier with
automatic gain control and offset cancellation, a phase
locked loop and sync separator to recover timing
information, and pulse area detectors to recover the
position information. External components are used to
set the operating characteristics of the SSI 32H6210,
such as AGC response, VCO center frequency, PLL
response and sync separator threshold. Its high performance analog/digital circuitry is capable of supporting servo frame rates of up to 400 kHz.
Servo signal dem<>dulation for dedicated surface head positioning systems
Supports industry standard di-bit quadrature
servo pattern with frame rates up to 400 kHz
N, Q outputs convey track crossing and position error information
•
PLL for timing recovery and synchronization
•
Adjustable sync separator threshold
•
Auto-zeroing AGC Input amplifier
•
AGCreference level adjustment
•
Precision bandgap voltage reference output
•
Advanced bipolar process dissipates less than
900 mW (5V, 12V)
•
Available in 28-pin PLCC, DIP, SO packages
I
BLOCK DIAGRAM
AGNO
OGM>
PIN DIAGRAM
VPA-
VREF IS."V)
VREF
THR
AGND
TW
CAZ
LOCK
AGCADJ
0AiA
IN+
SYNC
IN-
CLD
N/C
RVCO
CPK
LF
CAGC
BP2
CAD
TAD
BP1
N
C1
C2
Q
VPA
DGND
VCC
VCO
vco
0292- rev.
1W
lHR
nxTA
SYNC
Lf
BP1
BP2
ClO
LOCK
C1
C2
Rveo
28-PIN
DIP, so
SSI32H6210
Servo Demodulator
FUNCTIONAL DE:SCRIPTION
In a standard servo frame, the data and sync pulses are
more closely spaced than the information pulses (A-D).
This allows the sync detect circuit to recover the SYNC
pulses. A threshold, which is defined as percentage of
the peak signal atthe output ofthe AGC amplifier, is set
externally with RTH. Pulses which exceed this threshold are defined as valid pulses. As illustrated in Figure
6, at the end of the positive going half of a valid pulse,
a window, whose width is set by Rw and Cw, is opened.
If a second valid pulse occurs within this windqw, it is
recognized as a SYNC pulse. This pulse becomes the
input signal to a phase locked loop whose VCO clock
frequency is 32 times the SYNj:; frequency (servo
frame rate). The DATA output rises after a missing data
pulse. The example illustrated in Figure 6 includes the
case of a missing DATA pulse. The SYNC clock output,
which marks the start of a new servo frame,is derived
from the VCO output so that the clock continues to run
when a data pulse is missing. Absolute positioning
information such as track 0 and gU,ardband flags may
be encoded on the servo surface by the omission of
data pul,ses.
To generate the servo pattern shown in the. timing
diagram, Figure 5, the DATA and SYNC pulses must
be written to,overlap as shown in Figure 7.
The phase detector compares the' detected sync
pulses wifh the SYNC output. A current pulse proportional to the phase error is applied to an external loop
filter network connected to the LF pin, to generate the
VCO control voltage. If improved power supply rejection is required, bypassing may be provided at pins
BP1 and BP2. The VCO center frequency is determined by the external components Rvco and Cvco.
A lock detect circuit measures the phase difference
between the detected sync pulses and the sync output.
When this difference exceeds haH of a VCO clock
cycle, a pulse of discharge current is applied to CLD.
Otherwise a pulse of charging current. is applied to
CLD.
A clamp circuit limits the swing of the CLD pin and also
insures that a small amount of hysteresis is present.
When the voltage on CLD falls below the upper clamp
level by more than the "lock margin," the open collector
LOCK output transistor is turned on. Likewise, when
the voltage on CLD rises above the lower clamp level
by more than the "unlock margin," the LOCK output
transistor is turned off.
(Refer to block diagram, and typical application, Fig.2)
The SSI 32H6210 processes servo position
information which is read from a dedicated surface by
a pre-amplifier. The servo information must conform to
the 'di-bit quadrature' pattern which is iIIu$trated in
Figure 4. Servo frames, consisting of data' and sync
pulses followed by four information pulses (A, B, C, D)
are prerecorded along each track of the servo surface.
All the servo frames on an individual track are identical,
but in the radial direction four different frame types are
encountered, with every fourth track being identical.
The N signal generated by the SSI 32H6210 is
proportional to the difference in sizes of pulses A and
B, while the Q signal is proportional to the differ!3nce
between pulses C and D. When the read head is off
track, the read signal is'effectively a linear interpolation
between the prerecorded information of two adjacent
tn:icks, making it possible to sense the head
displacement exactly.
"
The SSI 32H6210 has a differential input amplifier
which incorporates' offset voltage cancellation and
automatic gain control. An external read preamplifier
must provide a differential input signal of 23 to 400 mV
peak to peak from the servo read head. This Signal is
applied to a pulse detectorwhose output is proportional
to the area under the input pulse.
An AGC circuit adjusts the input gain so that the
maximum pulse detector output is 2V peak. The AGC
circuit incorporates a peak detector which stores the
maximum pulse area signal on the external capacitor
CPK. This signal is compared to an internal amplitude
reference and the input amplifier gain is adjusted until
they are equal. The capacitor CAGC determines the
response time of the gain control circuit. An offset
cancellation circuit', whose response is set with the
external capacitor CAl;, ensures that the average level
at the differential amplifier output is zero.
An AGe adjust (AGCADJ) pin allows the user to adjust
the AGC reference level. AGCADJ can be driven with
a potentiometer or a D/A ( a simple Pulse Width
Modulated signal is usually sufficient.) This pin is left
open if no AGC adjustment is required.
All internal analog Signals are referenced to a 5.4V
bandgap reference voltage. This level is available at
the VREF output, which is capable of supplying 10 rnA
to the rest of the servo path electronics.
7-64
SSI32H6210
Servo Demodulator
FUNCTIONAL DESCRIPTION (Continued)
Internal timing windows are generated from the recovered SYNC pulse and VCO clock. These windows,
WA, WB, WC, and WD, in Figure 5, enable the four
peak detectors to capture the A, B, C and D information
pulses. The Nand Q analog outputs are formed by
differencing adjacent pulses. These outputs change
during a servo frame and only become valid afterthe D
pulse has been detected. Nand Q should be sampled
by the servo controller on the next falling edge of the
SYNC output clock.
An example of an entire servo path implemented with
the SSI 32H6210 and its companion devices, the
SSI32H6220 and SS132H6230, is shown in Figure 9.
lOY
Rl
SV
VREF(5.4~
_-o----,
PWM_.P~W-.......
12'1
5V
(ANALOG) (DIGITAL)
!l
~------------~~-'~i
ffi
~iiio::l
Q
E~~g
mwCl)z
~------------~~-'~ffig8
CAD
VREF
FIGURE 2: Typical Application
7-65
I
SSI32H6210
Servo Demodulator
PIN DESCRIPTION
POWER
NAME
TYPE
VREF
a
REFERENCE VOLTAGE - 5.4V output. All analog signals are referenced to this voltage.
AGND
ANALOG GROUND
VCC
-
DGND
-
DIGITAL GROUND
VPA
DESCRIPTION
ANALOG SUPPLY - 12V power supply.
DIGITAL SUPPLY - 5V power supply.
INPUT AMPLIFIER
NAME
TYPE
DESCRIPTION
CAZ
-
AUTOZERO CAPACITOR - A capacitor which sets the response of the
input amplifier offset cancellation circuit should be connected between
this pin and analog ground.
IN+
I
NON-INVERTING INPUT - AGC input amplifier connection. The noninverting output of the differential servo pre-amplifier should be AC
coupled to this pin.
IN -
I
INVERTING INPUT - AGC input amplifier connection. The inverting
output of the differential servo pre-amplifier should be AC coupled to this
pin.
CPK
-
PEAK HOLD CAPACITOR - A capacitor which is used by the peak
detector of the AGC circuitry must be connected between this pin and
analog ground.
CAGC
-
AGC CAPACITOR - A capacitor which sets the AGC attack and decay
times must be connected between this pin and analog ground.
AGCADJ
I
AGC Adjust - This pin allows for AGC reference level adjustment. It is
driven by a potentiometer or D/A. Normally this pin is left open.
TIMING RECOVERY
NAME
TYPE
DESCRIPTION
VCO
a
VCO OUTPUT - TTL compatible digital clock which is 32 times the sync
frequency (servo frame rate).
C2,C1
-
VCO CAPACITOR - Connection points for a capaCitor which sets the
VCO center frequency in conjunction with an external resistor connected to RVCO.
BP1,BP2
-
PLL BYPASS - Bypass capaCitors may be connected between these
pins and analog ground to provide additional power supply rejection in
the phase locked loop.
7-66
SSI32H6210
Servo Demodulator
TIMING RECOVERY (Continued)
NAME
TYPE
DESCRIPTION
LF
-
PHASE LOCKED LOOP FILTER - An external RC network which sets
the PLL loop characteristics must be connected between this pin and
analog ground.
RVCO
-
VCO RESISTOR - Connection for a resistor which sets the VCO center
frequency, in conjunction with the capacitor between pins C1 and C2.
The resistor must be connected between this pin and the VREF output.
SYNC
0
SYNC OUTPUT - TIL compatible digital clock whose falling edge
indicates the presence of valid analog signals on the Nand Q outputs.
There is one SYNC cycle per servo frame.
DATA
0
DATA OUTPUT - Active low TIL compatible digital output that indicates
the presence 01 a data pulse in the servo frame. This signal is updated
on the falling edge of the SYNC output.
TW
-
TIMING WINDOW - A resistor and capaCitor must be connected in
parallel between this pin and analog ground to set a timing window
which is used in detecting SYNC pulses.
THR
-
PULSE THRESHOLD - A resistor which sets a threshold for SYNC and
OATA pulse detection must be connected between this pin and VCC
(digital5V supply).
CLD
-
LOCK DETECT CAPACITOR - The value of this capacitor determines
how quickly the LOCK output responds (1000 pF).
LOCK
0
LOCK OUTPUT - An open collector output that indicates the lock status
of the PLL.
POSITION INFORMATION
NAME
TYPE
DESCRIPTION
CAD
-
AREA DETECTOR CAPACITOR - A capacitor, which forms an integrator to sense the pulse area of the servo position signals, must be
connected between this point and analog ground.
N
0
N OUTPUT - This sampled analog signal is the normal position
reference output. N is referenced to VREF and is periodic in radial
displacement, with a period of 4 tracks.
Q
0
Q OUTPUT - This sampled analog signal is the quadrature position
reference output. Q is referenced to VREF and is periodic in radial
displacement, with a period of 4 tracks. It is 90 degrees out of phase with
N.
7-67
II
SSI32H6210
Servo Demodulator
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(Maximum limits indicate where permanent device damage occurs. Continuous operation at these limits is
not intended and should be limited to those conditions specified in the DC operating characteristics.)
PARAMETER
CONDITIONS
MIN
VCCvoltage
MAX
UNITS
8
V
0
16
V
-0.5
VCC+O.5
V
0
VPAvoltage
Voltage on PLL inputs
Voltage on other inputs
Storage Temp.
Solder Temp.
TYP
0
14
V
-45
160
°C
260
°C
10 sec. duration
RECOMMENDED OPERATION CONDITIONS (Unless otherwise noted, the following conditions are valid
throughout this document.)
PARAMETER
CONDITIONS
VPA, analog supply
Supply noise
MIN
TYP
MAX
10.8
12
13.2
V
0.1
Vpp
F<1 MHz
VCC, digital supply
4.75
Ta, ambient temperature
5
0
VCO operating range
Load resistance
5.25
V
70
°C
12.8
MHz
10
To VREF
UNITS
kQ
Load capacitance
50
pF
MAX
UNITS
50
mA
60
mA
DC CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
IPA, VPA current
ICC, VCC current
IlA
VOH, digital output high
IIOHI<40
VOL, digital output low
IIOLI<1.6 mA
2.4
0.5
IREF, VREF
output current capacity
VREF output voltage
V
10
5.1
IIREFI<10 mA
7-68
V
mA
5.4
5.7
V
SSI32H6210
Servo Demodulator
ELECTRICAL SPECIFICATIONS (Continued)
AC CHARACTERISTICS
MAX
UNITS
lOUT = 0-10 mA
1 IlF bypass to AGND
Frequency<15MHz
12
n
Output impedance
F = 1 MHz
100
n
Voltage per track
Referenced to VREF
23-400 mVpp differential
AGCADJopen
2.2
V
20
mV
PARAMETER
CONDITIONS
VREF output impedance
MIN
TYP
N, Qoutputs
1.8
2
Offset voltage
Output noise
-55
10 Hz---"VIJVIr--1"-----------i
A typical SSI 32H621 0 application is shown in Figure 2.
The selection criteria for the external components
shown are discussed below.
is OV to Vee)
VAGCAOJ
R2
INPUT AMPLIFIER
The autozero circuit is effectively a high pass filter,
whose pole frequency is given by:
fAZ=
RGURE3:
220
Hz
C AZ ( J.IF)
for example
With a value of 10 J..l.F for CAZ, the autozero circuit's
corner frequency will be 22 Hz. This is sufficient for DC
offset rejection and it will not interfere with the servo
signal.
f fN'I
K = .318, dv = 0.26V, R1 = 20.4k,
R2 = 9.5k
The amplitude of N & Q signals can be adjusted using
the AGCADJ input. If it is desired to adjust the N & Q
amplitude by ± ~ V volts, the values of R 1 and R2 can
be calculated from K and dv as shown infigure 3.
390
Hz
CAGC( J.IF)
When R1 & R2 are calculated, a filter capacitor C is
calculated from the replication rate of the J..l.P duty cycle
output. The parallel combination of R1, R2, RAGC
minimizes the ripple of VAGC, and yet still provides
sufficient response time to changes in duty cycle.
For a nominal bandwidth of 10kHz, CAGC should be
0.039 J..l.F. With a 1% capacitor, the variation in actual
bandwidth will be +/- 50% due to the tolerance of
internal components. The AGC peak detector capacitor should always be set to 1500 pF. This represents a
reasonable tradeoff between leakage current tolerance and storage aperture time.
SYNC DETECTOR
Two sync detector parameters may be adjusted with
external components. The first is the valid pulse threshold. The threshold is expressed as a percentage of a
full scale pulse (Since the sync detector follows the
AGC and input amplitude variations are removed). The
threshold is determined with resistor RTH as follows:
The pulse area detector storage capacitor must be
chosen to keep the AGC circuit operating within its
linear range. Its value is related to the VCO frequency
as follows:
CAD
620
pF, where fvco is the VCO freq.
fvco(MHz)
Threshold
Larger values for CAD are required with lower VCO
frequencies in order to maintain constant signal levels
within the device, since the integration time is increased.
K=2
V AGCADJ (typ )
VCC (min)
VCC = 5V ± 5%, Ta = 0-70 D C
VREF = 5.4V ± 6%
if:~ V = O.4V,
then:
The AGC response may be characterized in terms of
the open loop unity gain bandwidth of its control loop.
The nominal value for this loop is set by CAGC as follows:
AGCADJ~p~
0.44
.100(%)
RTH (kQ)
For example, a value of RTH = 1.0 kQ sets the valid
pulse threshold at 44% of full scale. This prevents false
triggering on noisy signals, but does not unduly shorten
the sync pulse.
dv=~~~~~V~_____
A timing window is used to detect sync pulses, since
the sync and data pulses are more closely spaced than
any other pulses in a valid servo signal. The delay from
the zero crossing of the data pulse to the leading edge
of the sync pulse is 1.5 cycles of the VCO clock. The
next most closely spaced pulses (which must be rejected by the sync detect circuit) are separated by 3
AGCADJGain (max)
_ R AGC (min) ( V AGCADJ (min)
K
dv
R1-
K
R2=1_K(R1)
7-71
II
SSI32H6210
Servo Demodulator
APPLICATIONS INFORMATION (Continued)
SYNC DETECTOR (Continued)
The phase detector is a digitally controlled charge
pump, which injects a current into the loop filter whose
average value is proportional to the phase error. The
detector gain, Kd, is fixed at 32lJ.A1rad. If a loop filter
consisting of a series resistor and capacitor is used, as
shown in Figure 2, the phase locked loop becomes a
second order system with the following transfer
function:
VCO cycles. Thus the timing window should be set for
2 cycles of the VCO clock, to allow reliable detection of
the sync pulse while suppressing false syncs. The
timing window is determined as follows:
0.4 ( Rw • Cw ) + 43 • 10·g
The resistor Rw should always be set to 5.6 kn, which
means that for a 2 cycle window, Cw is given by:
C
900
w == fvco(MHz)
(s/oon)2
phase error (s) ==
input phase
1+ 2· ~. sl oon+(sl oon)2
19 F
p
where:
For a 12.8 MHz clock, Cw should be chosen as 5.1 pF.
00 n ( natural freq. ) = V(( I~"v".--<-A->'V~-'-/\-'lv:--r---i!Vtr
N
SERVO
SIGNAL
I
I
A
f /\ /\:
B
C
/\
A
I
D
A
I
/\
tv
- - -t--''-+V+--'rV-,-r----L-'''""V7-..L..---""'c--r-~'---"""""""""7fI,--'--\V-+-\V-r-.
SERVO
SIGNAL
Q
-
V'
I
I
ABC
f /\~
-I-+*'f7:
- - t -L
~~RNV~
V
-r41
,
I
V'
I
/\
V:
v
ABC
D
V
~
I
1-1.--------
SERVO FRAME
TIME OR ROTATION
(ALONG TRACK N +2)
I
Av A:v, /\j,V:V .
------It /\VA:V :/\V
TIME OR ROTATION
(ALONG TRACK N + 1)
I
I
:/\~
A:.....:,,"'--c,---LA-'T---r--------'----'\---t--'-4+-h~.
:v
I
V'
D
TIME OR ROTATION
(ALONG TRACK N)
TIMEORRQTATION
(ALONG TRACK N +3)
---------I.i
RADIAL DISPLACEMENT (TRACKS)
FIGURE 4: Pre-recorded Servo Signal and Servo
Demodulator Output vs. Radial Displacement
7-73
I
C/)C/)
CDC/)
...
-
!
~
WA
WB
we
hi
WO
FIGURE 5: Timing Diagram
SSI32H6210
Servo Demodulator
DATA
D
SYNC
A
D
C
B
SYNC
CROsz~~g --+-~
VALID PULSE
Rw, Cw TIMING WINDOW
INTERNAL SYNC
DETECTION
DA'f)\" OUTPUT
SYNC DETECT
(DERIVED FROM
VCOCLOCK)
N, Q OUTPUTS
_______~r_1
I
--------------~i------------------------------~--~~
-------------~r_1
~
I
I
~
I
I
I~
STABLE
STABLE
I
I
I
:'4
I
I
I
SERVO FRAME
.:
I
I
FIGURE 6: Sync and DATA Pulse Detection
27
28
I
29
30
31
o
VCOCLOCK
DATA PULSE -------f"
SYNC PULSE
SUM (DATA+SYNC)-------/
FIGURE 7 : Servo Writer Data-Sync Pulse Generation
7-75
2
I
12V
5V
en en
VREF (5.4V)
(Den
<-
O~
R1
PWMfrom~
vee
VPA I
OJ:
(DOl
12V
5V
(ANALOG) (DIGITAL)
~~~4.
C pK
1500 pi
3~
00
Co
C
CPK
!.
o""'I
GAIN
CONTROL
A
N
FROM
SERVO
PREAMPLIFIER
~~
"
_ J
~
IN.
POSITION REFERENCE
SIGNALS TO SERVO
CONTROLLER
Q
CAC
~
I
CAD
PHASE LOCKED LOOP
veo
RVCO • 11kO
51 pF FOR
12.8 MHz
~
%TH
-100 1.0kOFOR37%
}
TO SERVO CONTROLLER
SERVO DATA
Cilnl'27t= 4600 Hz
, •. 68
FIGURE 8: Design Example for 400 kHz Frame Rate
VREF
I
CLOCK
TOSERVQ
CONTROLLER
PO.O
EN
LOWV
80C51
Xl
....I-
~~Z
0
GND
ALE
ALE
A15
es
RBIAS
RD
RD
AGND
WR
INT
+ 12VTO
SPINDLE
MOTOR
SE3
SE2
FPl
SEl
VCC
I
H· BRIDGE
MOTOR
DRIVER
OUTA
VDD
.5V
OUTB
DGND
Rl
FP2
N
PWMfromv.P~
R2
....,
f':_ •• _
v
RESET
-;-'
....,
.l-
I
VPA
XO
WR
\'.,2V
INS820
Vee
ADO-7
INT
~
+ 12V
VPD
ADO·7
I
a
~
CLOCK
~~IN+
[---+--<0-----"
=1
, Cl
FV2
C2
+1~V~ vpA
V
~CW I:
RVCO
FVl
=
I ,
j
j
CLAMP
JWL-+-If-I"'"!- - - - 1
AGNO
VREF
$OUT
.5V
SSI32H6~~SK1~ IT'~
Ii
SERVO
DEMODULATOR
O~C ~.--------------------------------
~~~f~~ER
FV4
IN-
SERVO 0.1 ~ F
READ HEAD
Rwi
FP4
SYNC
ERR
RBRK
SS132H6230
ERR·
LOOP COMPENSATION
VREF
TO SPINDLE MOTOR
BRAKING TRANSISTOR
BRK
ERR +
VREF
ROS
SERVO
CONTROLLER
SERVO
MOTOR DRIVER
CBYP
w
en
a:
:I:
I-
:><:
0
~ 9
28 27
IN+
DATA
IN-
SYNC
N/C
LF
CPK
c
~
CLD
CPK
RVCO
CAGC
21
CAD
LF
BP2
N
BP1
12 13 14 15 16 17 18
0
«a..
>
28·Pln DIP,SOL
0
0
8
> >
c
z
<
g
~ ~
Z
0
0..
0
<
~
~
BYP
VTHR
VIA
RCTW
ViA
VPD
VREF
21
N
DATA
SVOPUL
Q
VND
TP1
SYNC
TP2
NIC
!.1
z
~
I-- CIl
0
~~~ml~
Ii I-g
0
~
32-Lead TQFP
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify thattheclata
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680 (714) 573-6000, FAX (714) 573-6914
0193 - rev.
7-84
©1992 Silicon Systems, Inc.
SSI32H6230
Servo Motor Driver
June 1993
DESCRIPTION
FEATURES
The SSI 32H6230 Servo Motor Driver is a bipolar
device intended for use il1 Winchester disk drive head
positioning systems employing linear or rotary voice
coil motors. When used in conjunction with a position
controller, such as the SSI32H6220 Servo Controllers,
and a position reference, such as the SSI 32H6210
Servo Demodulator, the device allows the construction
of a high performance, dedicated su.rface head
positioning system.
The SSI 32H6230serves as a transconductance
amplifier by driving 4 MOSFETs in an H-bridge
configuration, performs motor current sensing and
limits motor current. In its linear tracking mode, class 8
operation is guaranteed by crossover protection
circuitry, which ensures that only one MOSFET in each
leg of the H-bridge is active. The MOSFET drivers are
disabled when motor velocity. or current exceed
externally programmable limits. In addition, automatic
head retraction and spindle braking may be initiated by
a low voltage condition or upon external command.
Predrlver for linear and rotary v()lce coli
motors
Interfaces directly to MOSFET H-Brldge motor
driver
Class B linear mode and constant velocity
.retract mode
FET disable function
Precision differential amplifier for motor
current sensing .
Clamp ·for motor current limiting
AutomatiC head retract and spindle braking
signal on power failure
External digital enable
Servo loop parameters programmed with
external components
Advanced bipolar IC requires under 240 mW
from 12V supply
Available In 2o-pln DIP or SO packaging
(Continued)
BLOCK DIAGRAM,
PIN DIAGRAM
0 ......
ERR
7-85
VCC
LOWV
ERR·
2
19
ERR +
3
18
EN
VREF
4
17
OUTA
SOUT
5
·16
OUTS
CLAMP
6
15
SE1
DISABLE
7
14
SE2
BRK
8
13
OUTD
SE3
9
12
OUTC
10
11
VLlM
GND
0693 - rev.
20
SSI32H6230
S~rv'o lVIotor Driv~r
DESCRIPTION
An adjustable voltage clamp is provided to prevent
over current to the motor. It accomplishes the current
limiting by clamping the voltage excursion at the input
of A1. The voltage clamp values are programmed by
VREF and VU M.VUM is the lower clamp value and the
upper clamp limit is 2 • VREF - VUM.
(continued)
The SSI 32H6230 is implemented in an advanced
bipolar process and dissipates less than 240 mW from
a 12V supply. The IC is available in 20-pin DIP and
20-pin SO packaging.
The disable function will cause all4 bridge FETstoturn
off. Note that this function does not override the retract
function.
FUNCTIONAL DESCRIPTION
(Refer to block diagram and typical application Fig.2)
The SSI32H6230 has low voltage monitor circuitry that
will detect a loss of voltage on the VREF, VCC or
LOWV pins. The power supply pin, VCC, should be
connected to the disk drive~s spindle motor so that its
stored rotational energy may be used to hold up VCC
briefly during a power failure. LOWV is used to detect
a system power supply failure. When a low voltage
condition is detected; the MOSFET drivers switch from
linearoperationto retract mode. In this mode aconstant
voltage is applied across the motor which will cause the
heads to move at a constant speed. A mechanical stop
must be provided forthe heads when they reach a safe
location. The current limiting Circuitry will disable the
MOSFET drivers when motor current increases due to
loss of the velocity-induced back EMF. An open collector
output, BRK, which is active while the device is in
retract mode, is provided for spindle motor braking. An
external RC delay may be used to defer braking until
the heads are retracted.
The. SSI 32H6230 has two modes of operation, linear
and retract. The retract mode is activated by a power
supply failure or when the control signal EN is false.
Otherwise the device operates in linear mode;
During linear operation, an acceleration signatfrom the
servo controller is applied through amplifier A1, whose
three connections are all available externally. RC
components may be used to provide loop compensation
at this stage. The ERR signal drives two precision
amplifiers, each with a gain of 8.5. The first of these
amplifiers is inverting, and is formed fromopamp A4,
an on-chip resistor divider and an off-chip
complementary MOSFET pair. fhe. second is noninverting, and is formed in a similar manner from
opamp A5. Feedback from the MOSFET drains, on
sense inputs SE1and SE3, allows the amplifiers gains
to be esta~lished precisely. The voice coil motor and a
series current sense resistor are connected between
SE1 andSE3.
Two examples of an entire servo path implemented
with the SSI 32H6230 and its companion devices, the
SSI 32H567, 32H568, and the SSI32H621 0, 32H6220
are shown in Figure 7.
Crossover protection circuitry between the outputs of
A4 and A5, and the external MOSFETs, ensures class
B operation by allowing only one MOSFET in each leg
of the H-bridge to be in conduction. The crossover
separation threshold, illustrated in Figure 5, is the
maximum drive on any MOSFET gate when the motor
voltage changes sign. The crossover circuitry can also
disable .all MOSFETS simultaneously (to limit motor
current or velocity) or apply a constant voltage across
the motor (to retract the heads at a constant velocity).
Motor current is sensed by a small resistor placed in
series with the motor. The voltage drop across this
resistor is amplified by a differential amplifier with a
gain of 4 (A2 and associated reSistors), whose inputs
are SE1 and SE2. The resulting voltage, SOUT, is
proportional to motor current, and hence acceleration.
This signal is externally fed back to A1, so that the
signal ERR represents the difference between the
desired acceleration (from the servo controller) and the
actual motor acceleration.
7-86
DISABlE
4R
ACCELERATION ERROR
DISABLE DRIVERS
~
.....
TO SPINOLE MOTOR
BRAKING TRANSISTOR
RBAK
••v
~~1~
.12V
1
CONTROl SIGNAL FROM
MICROPROCESSOR OUTPUT POAT
en
CD
~
o
3: en
FIGURE 2: Typical Application
-oen
...
o
W
N
C~
:::!.
Q)
IICLAMP I >10 IlA
I = 10 IlA
0.1
-3
3
%
20
0
~VREF
VLlM Voltage
-1
VLlM Accuracy
V
+1
%
POWER SUPPLY MONITOR
VCC fail threshold
LOWV fail threshold
IILowvl < 0.5 mA
VREF fail threshold
8.5
9
9.8
V
8.5
9
9.8
V
3.9
4.3
4.8
V
Hysteresis (LOWV, VCC)
250
mV
Hysteresis (VREF)
110
mV
EN input low voltage
IIiLI < 0.5 mA
EN input high voltage
IIiHI <40 uA
BRKvoltage
BRK leakage current
0.8
V
2
V
normal mode, IIOLI < 1 mA
0.4
V
retract mode
10
~
1
ms
BRK delay (from power fail or
EN false to BRK floating)
7-91
SSI32H6230
Servo Motor Driver
ELECTRICAL SPECIFICATIONS
(continued)
MOSFET DRIVERS
PARAMETER
CONDITIONS
SE3 Input impedance
To VREF
MIN
TYP
10
25
MAX
UNITS
kQ
OUTA, OUTC
voltage swing 1101<1 mA
0.7
VCC-1
V
OUTB,OUTO
voltage swing 1101<1 mA
1
VCC-1
V
2
V
VTH,
Crossover separation threshold
Slew rate
(OUTA, OUTB, OUTC, OUTO)
Ck1000 pF
Crossover time
300 mV step at ERR
1.4
V/j..IS
5
j..IS
Output impedance (OUTA,B,C,D)
50
kQ
Transconductance
I(OUTA,B,C,D)/{ERR-VREF)
8
mAN
Gain (-(SE1-VREF)/(ERR-VREF)
or (SE3-VREF)/(ERR-VREF) )
Offset current
8
.. -
8.5
Rs = 0.2Q, RF = RIN,
VIN=VREF
Retract motor voltage
(SE1-SE3)
0.7
7-92
1
9
VN
20
mA
1.3
V
SSI32H6230
Servo Motor Driver
APPLICATIONS INFORMATION
where SW is the
unity gain open
loop bandwidth
A typical SSI32H6230 application is shown in Figure 2.
The selection criteria for the external components
shown are discussed below. Figure 3 shows the
equivalent circuit and equations for the DC motor used
in the following derivations. While the nomenclature
chosen is for a rotating motor, the results are equally
applicable to linear motors.
The closed loop response of the servo driver and motor
combination, using the component values and
simplifying assumptions given above, is given by:
MOTOR CURRENT SENSE AND LIMITING
1
RF
The series resistor which senses motor current, Rs, is
chosen to be small compared to the resistance of the
motor, Rm. A value of Rs = 0.2Q is typical in disk drive
applications.
im
-(s)
VLlM, RIN1, and RIN2 must be chosen to keep the
motor current below Imax. The voltage clamp values
programmed by VREF and VLlM must be chosen to
cause limiting when the motor current reaches its
maximum permissible current in amps, this value may
be chosen as follows:
Where: Rin = RIN1 + RIN2
Ilmaxi= CLAMP
RIN2
Yin
= - _ 0 _ _ 0 _ _ _ _-
Rin
4
0
Rs
s
(1 +
)
2,1t o SW
(This analysis neglects the pole due to the output
impedance of the MOSFET drivers and the MOSFET
gate capacitance, an effect that may be significant in
some systems.)
RF is chosento be sufficiently large to avoid overloading
A2 (RF > 4 kQ). The input resistor, RIN, sets the
conversion factor from servo controller output voltage
to servo motor current. RIN is chosen such that the
servo controller internal voltages are scaled
conveniently. The resistor Ros is optional and cancels
out the effect of the input bias current of A 1.
.-...BE...
4 Rs
0
Where the upper clamp limit is 2 VREF - VLlM and the
lower clamp limit is VLlM. If VLlM is left open, a value
of 0.667 • VREF will appear. The upper clamp limit is
then 1.33 VREF and the lower clamp limit is 0.667·
VREF. The values of RIN1, RIN2 must be chosen to
satisfy the maximum swing of Yin before Iimitingoccurs,
0
0
Vine max) =CLAMP
Roo = Rin!! RF
(1 + ~i~~ )-:( VREF) + VREF
The external components RD and CD have no effect on
the motor dynamics, but may be used to improve the
stability of the MOSFET drivers. The load represented
by the motor, ZM, is given by:
and they should also satisfy the maximum current
VCLAMP can source or sink
Yin (max) [ Actual ]- CLAMP ~1 mA
RIN1
At frequencies above (Rs+Rm)/(21t Lm) Hz, this load
becomes entirely inductive, which is undesireable. RD
and CD maybe used to add some parallel resistive
loading at these frequencies.
0
LOOP COMPENSATION
The transfer function of the SSI 32H6230 in the
application of Figure 2 is shown in Figure 4(a). If the
zero due to RL and CL in the loop compensation circuit
is chosen to cancel the pole dueto the motorinductance,
Lm, then the transfer function can be simplified as
shown in Figure 4(b), under the assumption that this
pole and the pole due to the motor mechanical response
are widely separated. CL may then be chosen to set the
desired open loop unity gain bandwidth.
7-93
SSI32H6230
Servo Motor Driver
APPLICATIONS INFORMATION
POWER FAILURE OPERATION
(continud)
The. power supply for the SSI 32H6230, VCC, should
betaken from the system 12V supply through a schottky
diode (maximum O.SV drop at If = 3A) and connected
to the disk drive spindle motor. If the system power
fails, the IC will continue to operate as the spindle motor
becomes a generator. The SSI32H6230 will detect the
power failure and cause a forced head retract, continuing
to operate with VCC as low as 3.SV. The power fail
mode will commence if either VCC or LOWVfalis below
9V, or VR EF falls below 4.3V, or EN is false. Hysteresis
on the low voltage thresholds prevents the device from
oscillating between operating modes when the power
supply is marginal.
H-BRIDGE MOSFETS
The MOSFETs chosen for the H-bridge should have
gate capacitances in the range of SOO-1000 pF. The
MOSFET input capacitance forms part of the
compensation for the MOSFET drivers, so values
below SOO pF may cause some driver instability.
Excessive input capacitance will degrade the slew
mode performance of the drivers.
When the motor voltage is changing polarity, the
crossover protection circuits at outputs OUTA-OUTD
ensure that the maximum MOSFET gate drive is less
than 2V (the crossover separation threshold), as
illustrated in Figure S. The thresholds of the MOSFET
devices chosen should be as large as possible to
minimize conduction in this region. If the device
thresholds are significantly less than the crossover
separation threshold, the Nand P channel devices in
each leg of the H-bridge will conduct simultaneously,
causing unnecessary power dissipation.
The BRK output, which is pulled low during normal
operation, floats during a power failure. This allows an
external transistor to be enabled for spindle motor
braking. An external RC delay may be added to defer
braking until head retraction is complete, since the
spindle motor is required to generate the supply voltage
during retraction.
.
im
Jam
Km
im
Armature current (A)
m
Motor speed (rad/s)
Je
Moment of inertia of
rotor (Kg. M 2 )
Km
Torque constant (Nm/A)
Ke
Motor voltage constant (V/rad/s)
e
Back E.M.F. (V)
Lm
Winding inductance (H)
Rm
Winding resistance ( n
Nomenclature used is for rotary motor
FIGURE 3: Equivalent Circuit for Fixed Field DC Motor
7-94
SSI32H6230
Servo Motor Driver
WINDING IMPEDANCE
LOOP COMPENSATION
1
17( 1 +SCLR L )
MECHANICAL RESPONSE
e
CURRENT SENSE
FIGURE 4A: Transfer Function of SSI 32H6230 in
Typical Application with Fixed Field DC Motor
LOOP COMPENSATION
MECHANICAL RESPONSE
---~-7I -~
/~-
""
/'
-'/'
1
K m2
1+
SJ9
17
SCL(Rs+ Rm)
(As + Rm)
CURRENT SENSE
Rs
4RF
1/
I'-
FIGURE 48: Simplified Transfer Function of
SSI 32H6230 in DC Motor Application
7-95
"
/'
II
SSI32H6230
Servo Motor Driver
MOSFET GATE DRIVE
vee - - - - - - - - - - - - - - - - 1- _ _ _ _ _ _ _ _ _ _ _ _ _ _
vee
(CROSSOVER
SEPARATION
THRESHOLD)
ERR
(ERROR SIGNAL INPUT)
VAEF
(HORIZONTAL. SCALE IS GREAltY EXPANDED)
FIGURE 5: Crossover Protection
1.0
ASSUMPTIONS:
lOOK
I
0.1
- - T - - - - - - - -
10K
As =0.20
Rt==10K
Rm=30
lm =600 I!H
.01
lK
100
.001
100
lK
lOOK
10K
BANDWIDTH
(Hz)
FIGURE 6: Typical Motor Driver Compensation
7-96
po.o
EN
LOWV
+12V
80C51
INSB20
VPD
XI
0
ADO-7
Vee
A00-7
VPA
XO
ALE
ALE
A15
os
RBIAS
AGND
RD
RD
WR
WR
INT
INT
C
+12VTO
BYP
SPINDLE
MOTOR
SE3
FPl
SE2
H-BRIDGE
MOTOR
DRIVER
SEI
Vee
GND
f
RESET
OUTA
VDD
OUTS
DGND
DGND
PRE
.....
cO
""'-J
THR
N
N
0
0
FP2
VCC
~
n of ••
IN-
I::
SI
REA'
FP4
OUTO
IN+
SYNC
SYNC
OUTC
VCO
CLOCK
PE
CLD
FV4
CAZ
Cl
CAGe
';I
BY!!
C2
CPK
VPA
CAD
CLAMP
55132H622O
FV2
SOUT
BPI
~
+5V
FVl
BP2
ERR
SKI
TW
SSl32H6230
SK2
VE
SSl32H6210
RW
RSRK
LF
ERR-
AGND
RVCQ
VREF
SRK
CJ)
TO SPINDLE MOTOR
BRAKING TRANSISTOR
ERR+
VREF
VREF
RDS
. SERVO
)EMQOULATOR
SERVO
CONTROLLER
SERVO
MOTOR DRIVER
CSYP
f
CD
~
o
3:CJ)
oCJ)
--
O~
"'1\)
O:J:
:::!.
<
en
I\)
CD~
FIGURE 7: Complete Example of Servo Path Electronics Using the SS132H6210/6220/6230 Chip Set
...0
SSI32H6230
Servo Motor Driver
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
vee
ERR
ERR-
LOWV
EN
ERR+
VREF
OUTA
SOUT
OUTB
CLAMP
SE1
DISABLE
SE2
BRK
OUTD
SE3
OUTC
GND
VLlM
20-Pln DIP, SO
ORDERING INFORMATION
PART DESCRIPTION
I
ORDER NO.
I
PKG.MARK
I
I
32H6230-CP
I
32H6230-CP
SSI 32H6230, Servo Motor Driver
20-Pin DIP
20-Lead SOL
32H6230-CL
I
32H6230-CL
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems.
Silicon Systems reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the data sheetis current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1989 Silicon Systems, Inc.
0693 - rev.
7-98
SSI32H6231
Servo Motor Driver
June 1993
DESCRIPTION
FEATURES
The SSI 32H6231 Servo Motor Driver is a bipolar
device intended for use in Winchester disk drive head
positioning systems employing, linear or rotary voice
coil motors.
•
The SSI32H6231 serves as a transconductance amplifier by driving 4MOSFETs in an H-bridge configuration, performs motor current sensing and limits motor
current and velocity. In its linear tracking mode, class
B operation is guaranteed by crossover protection
circuitry, which ensuresthatonlyone MOSFET in each
leg of the H-bridge is active. Head retraction and
spindle braking may be initiated by a low voltage
condition or upon external command.
•
Class B linear mode and constant velocity
retract mode
•
PreCision ,differential amplifier for motor
current sensing
External digital enable
The SSI32H6231 is implemented in a precision bipolar
process and dissipates less than 240 mW from a 12V
supply. The IC is available in 20-pin SOy packaging.
•
•
•
•
•
Predrlver for linear and rotary voice coil
motors
Interfaces directly to MOSFET H-Bridge motor
driver
Servo loop parameters programmed with
external components
Precision bipolar IC requires under 240 mW
from 12V supply
Available in 20-pln SOY packaging
PIN DIAGRAM
BLOCK DIAGRAM
WRI'RO'f
.---------------------1"r---------------------------------,
ERR
.3
ERRERR+
4R
VREF
SE2
SOUT
SOUT
A3·
SE1
ACCELERATION ERROR
ERR
OUTA
'-'-"'==';.FJr-"'"1..,.J
ERR·
OUTB
A3
A3+
SE3
ERR+ ~_....-
GND
VREF
UYoN
OUTD
VOLTAGE
MONITOR
VLOA
20-Pin SOY
OUTC
vee
vee
0693 - rev.
GND
EN
7-99
CAUTION: Use handling procedures necessary
for a static sensitive component.
SSI"32H6231
Servo Motor Driver
FUNCTIONAL DESCRIPTION
(Refer to block diagram and typeial application Fig. 2)
The SSI 32H6231 has two modes of operation, linear
and retract. The retract mode is activated by a VREF
failure orwhen the control signal EN is false. Otherwise
the device operates in linear mode.,
During linear operation, an aCceleration signal from the
servo controller is applied through amplifier A1, whose
three connections are all available externally. RC components may be used to provide loop compensation at
this stage~ The ERR signal drives two precision amplifiers, each with a gain of 8.5. The first o·f these amplifiers is inverting, and is formed frQm opamp A4, an onchip resistor divider and an off-chip complementary
MOSFET pair. The .second ·is non-inverting, and is
formed in a similar manner tram opamp AS. Feedback
from the MOSFET drains, on sense inputs.sE1 and
SE3, allows the amplifiers gains. lobe established
precisely. The voice coil rootor and a series current
sense resistor are connected between SE1 and SE3.
Crossover protection circuitry between the outputs of
A4 and AS, and the external MOSFETs, ensures class
Soperation by allowing only one MOSFET in each leg
of the H-bridge to be in conduction. The crossover
separation threshOld~ illustrated in Figure 5, is the
maximum drive on any MOSFET gate when the motor
voltage changes sign. The crossover circuitry can also
apply a constant voltage across the motor (to retract
the heads at a constant velocity).
Motor current is sensed by a small resistor placed in
series with the motor. The voltage drop across this
resistor is amplified by a differential amplifier with a
gain 0.1 4 (A2 and associated reSistors), whose inputs
are $E1 and SE2. The resulting voltage, S0UT, is
proportional to motor current, and hence acceleration.
This signal is externally fed back to A1., so that the
signal ERR represents the difference between the
desired acceleration (from the servo controller) and the
actual motor acceleration.
SOUT is connected to a window comparator, which is
used to detect excessive motor current. When excessive current is detected, WRPROT is pulled low. The
VLlM pin may be used to program the voltage limit for
the window comparator. The maximum voltage excursion allowed a\:)ol)t VREF is (VREF-VLIM). An on-Chip
resistor divider sets a default value for VLlM and if vLI M
is connected to ground, the windowing is effectively
disabled.
.
The SSI32H6231 has low voltage monitor circuitry that
will detect a loss of voltage on VREF. The power supply
pin, VCC, should be connected to the disk drive's
spindle motor so that its stored rotational energy may
be used to holdup VCC Mefly during a power failure.
When a low voltage condition is detected, the MOSFET
drivers switch from linear operation to retract mode. In
this mode a constant voltage is applied across the
motorwhich will cause the heads to move at a constant
speed. A mechanical stop must be provided for the
heads when they reach a safe location.
7-100
WlU'llOT
'R
"F
ACCELERATION ERROR
"IN
V",
";"
§
VREF)----4--r--O-":.;."::;Oc'-Ir-,-I-------I
LOW
VOLTAGE
MONITOR
GNO
vee
IN5820
TO SPINDLE MOTOR
r
(/)
(I)
lTOMOTORDR1VER)~ + 12V
<
o
(SYSTEM
SUPPLy)
CONTROL SIGNAL FROM
MICROPROCESSOR OUTPUT PORT
3:(1)
--
O(/)
FIGURE 2: Typclal Application
o""'l
CA»
I\)
OJ:
:::::!.
en
VREF-VLlM
An internal resistor divider establishes a default value that may be externally
adjusted.
7-102
SSI32H6231
Servo Motor Driver
NAME
TYPE
DESCRIPTION
SE2
I
MOTOR CURRENT SENSE INPUT - Non-inverting input to the current sense
differential amplifier. It should be connected to one side of an external current
sensing resistor in series with the motor. The inverting input of the differential
amplifier is connected internally to SE1.
EN
I
ENABLE - Active high TTL compatible input enables linear tracking mode. A
low level will initiate a forced head retract.
I
MOTOR VOLTAGE SENSE INPUT - This input provides feedback to the noninverting MOSFET driver amplifier. It is connected to one side of the motor.
The gain to this point is:
OUTC
0
P-FET DRIVE (NON-INVERTING) - Drive signal for a P channel MOSFET
connected between one side of the motor and VCC. This MOSFET drain is
connected to SE3.
OUTO
0
N-FET DRIVE (NON-INVERTING) - Drive signal for an N channel MOSFET
connected between one side of the motor and GND. This MOSFET drain is
connected to SE3. Crossover protection circuitry ensures that the P and N
channel devices driven by OUTC and OUTD are never enabled simultaneously.
SE1
I
MOTOR VOLTAGE SENSE INPUT - This input provides feedback to the
inverting MOSFET driver amplifier. It is connected to the current sensing
resistor which is in series with the motor. The gain to this point is:
FET DRIVE
SE3
SE3-VREF
SE1-VREF
= S.5(ERR-VREF)
= -S.5(ERR-VREF)
This input is internally connected to the current sense differential amplifier
inverting input.
OUTB
0
N-FET DRIVE (INVERTING) - Drive signal for an N channel MOSFET
connected between the current sense resistor and GND. This MOSFET drain
is also connected to SEi.
OUTA
0
P-FET DRIVE (INVERTING) - Drive signal for a P channel MOSFET connected
between the current sense reSistor and VCC. This MOSFET drain is also
connected to SE1. Crossover protection circuitry ensures that the P and N
channel devices driven by OUTC and OUTD are never enabled simultaneously.
7-103
II
SSI32H6231
Servo'Motor Driver
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(Maximum limits indicates where permanent device damage occurs. Continuous operation at these limits
is not intended and should be limited to those conditions specified in the DC operating characteristics.)
PARAMETER
RATING
VCC
VREF
oto 16V
oto 10V
SE1, SE2, SE3
-1.5 to 15V
All other pins
oto 14V
Storage temperature
-45 to 165°C
Solder temperature - 10 sec duration
260°C
RECOMMENDED OPERATION CONDITIONS (Unless otherwise noted, the following conditions are valid
throughout this document.)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
VCC
Normal Mode
9
12
13.2
V
Retract Mode
3.5
14
V
4.8
7
V
0
70
°C
ICC, VCC current
20
mA
IREF, VREF current
2
mA
VREF
Operating temperature
DC CHARACTERISTICS
Al, LOOP COMPENSATION AMPLIFIER
Input bias current
Input offset voltage
Voltage swing
About VREF, VREF = 5.4
Common mode range
About VREF, VREF < Vcc-3
Load resistance
To VREF
500
nA
3
mV
2
V
±1
V
4
kf.!
Load capacitance
100
Gain
80
Unity gain bandwidth
0.5
pF
dB
1
MHz
CMRR
1<20 kHz
60
dB
PSRR
1<20 kHz
60
dB
7-104
SSI32H6231
Servo Motor Driver
A2, CURRENT SENSE AMPLIFIER
PARAMETER
CONDITIONS
MIN
NOM
Input impedance
SE1 to SE2
1.0
1.5
SE2to VR
5
7.5
MAX
kQ
kQ
Input offset voltage
Output voltage swing
2.0
VREF
= 5.4
Common mode range
Load Resistance
To VREF
mV
VREF-4
VCC-2.0
V
0
VCC-O.2
V
kQ
20
Load Capacitance
Output impedance
UNIT
k40 kHz
Gain (SOUT-VREF)/(SE1-SE2)
3.9
4
Unity gain bandwidth
0.5
1
100
pF
20
Q
4.1
VN
MHz
CMRR
k20kHz
52
dB
PSRR
k20 kHz
60
dB
A3 AMPLIFIER
Input bias current
Input offset voltage
Voltage swing
Common mode range
Load resistance
ToVREF
250
nA
2
mV
VREF-4
VCC-1.2
V
2.5
6
Load capacitance
100
Gain
60
Unity gain bandwidth
150
V
kQ
10
pF
dB
kHz
250
WINDOW COMPARATOR
Window comparator threshold
(SOUT-VREF)
ISOUT - VREFI increasing
Threshold hysteresis
VLlM voltage
No external parts
VLlM input resistance
7-105
VREF-VLlM
V
30
mV
92
94
8
15
96
% VREF
kQ
SSI32H6231
Servo Motor Driver
ELECTRICAL SPECIFiCATIONS (continued)
POWER SUPPLY MONITOR
PARAMETER
CONDITIONS
VREF fail threshold
MIN
NOM
MAX
UNIT
2.6
3.3
4.0
V
Hysteresis (VREF)
85
mV
EN input low vo.ltage
IIiII < 40 IJA
EN input high voltage
llihl < 1 mA
2
V
WRPROTVol
11011 < 1 mA
0.4
V
10
IJA
10
Ils
0.8
V
WRPROT leakage current
WRPROT delay
SOUT = VREF to VREF + 0.6V
MOSFET DRIVERS
SE3 Input impedance
To VREF
10
OUTA,.pUTC
voltage swing 1101<1 rnA
OUTB,OUTO
voltage swing 1101<1 mA
"
0.7
VCC-1
V
1
VCC-1
V
2
V
VTH,
Crossover separation threshold
Slew rate
(OUTA, OUTB, OUTC, OUTO)
CI<1000 pF
Crossover time
300 mV step at ERR
ill
25
0.5
1.4
V/J.LS
6
J.LS
Output impedance (OUTA,B,C,D)
50
kO
Transconductance
I(OUTA!B,C,D)/(ERR-VREF)
8
mAN
Gain (-(SE1~\tREF)/(ERR-VREF)
or (SE3-VREF)/(ERR-VREF) )
8.2
Offset current
Rs = 0.20, RF = RIN,
VIN=VREF
Retract motor voltage
(SE1-SE3)
Vcc= 6V
0.7
7-,106
8.7 '
1
9.2
VN
20
rnA
1.3
V
SSI32H6231
Servo Motor Driver
APPLICATION INFORMATION
A typical SSI32H6231 application is shown in Figure 2.
The selection criteria for the external components
shown are discussed below. Figure 2 shows the
equivalent circuit and equationsforthe DC motor used
in the following derivations. While the nomenclature
chosen is for a rotating motor, the results are equally
applicable to linear motors.
LOOP COMPENSATION
The transfer function of the SS132H6231 in the application of Figure 2 is shown in Figure 4(a). If the zero due
to RL and CL in the loop compensation circuit is chosen
to cancel the pole due to the motor inductance, Lm, then
the transfer function can be simplified as shown in
Figure 4(b), under the assumption that this pole and the
pole due to the motor mechanical response are widely
separated. CL may then be chosen to set the desired
open loop unity gain bandwidth.
where BW is the
unity gain open
loop bandwidth
RL=
RF is chosen to be sufficiently large to avoid overloading A2 (RF 1/ Rv > 4 kil). The input resistor, RIN, sets the
conversion factor from servo controller output voltage
to servo motor current. RIN is chosen such that the
servo controller intemal voltages are scaled conveniently. The resistor Res is optional and cancels out the
effect of the input bias current of A1.
The external components Ro and Co have no effect on
the motor dynamics, but may be used to improve the
stability of the MOSFET drivers. The load represented
by the motor, ZM, is given by:
At frequencies above (Rs+Rm)/(2·x· Lm) Hz, this load
L
K 2
ZM=(Rs+Rm)(1+s--m-)(1+
m
)(1.1)
Rs+Rm
S • J9· (Rs+Rm)
becomes entirely inductive, which is undesireable. Ro
and CD may be used to add some parallel resistive
loading at these frequencies.
H-BRIDGE MOSFET
Lm
CL• (Rm+Rs)
The closed loop response of the servo driver and motor
combination, using the component values and simplifying assumptions given above, is given by:
im
1 _
RF_ ·_-..;.....--(s)=-_·
Vin
Rin 4· Rs (1 +
s
)
2·x·BW
(This analysis neglects the pole due to the output
impedance of the MOSFET drivers and the MOSFET
gate capacitance, an effect that may be significant in
some systems).
The MOSFETs chosen for the H-bridge should have
gate capacitances in the range of 500-1000 pF. The
MOSFET input capacitance forms part of the compensation forthe MOSFET drivers, so values below 500 pF
may cause some driver instability. Excessive input
capacitance will degrade the slew mode performance
of the drivers.
When the motor voltage is changing polarity, the crossover protection circuits at outputs OUTA-OUTD ensure
that the maximum MOSFET gate drive is less than 2V
(the crossover separation threshold), as illustrated in
Figure 4. The thresholds of the MOSFET devices chosen should be as large as possible to minimize conduction in this region. If the device thresholds are significantly less than the crossover separation threshold, the
N and P channel devices in each leg of the H-bridge will
conduct simultaneously, causing unnecessary power
dissipation.
7-107
SSI32H6231
Servo Motor Driver
APPLICATION INFORMATION
becomes a generator. The SSI32H6231 can be commanded to perform a forced head retract, continuing to
operate with VCC as low as 3.5V; The head retract
modewiIJ commence if VREF falls below 3.3V, or EN
is false. Hysteresis on the low voltage threshold prevents the device from oscillating between operating
modes when the power supply is marginal.
(continued)
POWER FAILURE OPERATION
The power supply for the SSI 32H6231, VCC, should
betakenfromthe system 12V supplythrough a Schottky
diode (maximum O.5V drop at If';' 3A) and connected
to the disk drive spindle motor. 1fthe system power
fails, the IC will continue to operate asthe spindle motor
im
Jaco
Km
im
Armature current (A)
co·
Motor speed (radis)
Ja
Moment of ine.rtia of
rotor (Kg. M2 )
Km
Torque constant (V.S.)
e
Back E.M.F. (V)
Lm
Winding inductance (H)
Rm
Winding resistance (
Nomenclature used is for rotary m6tor
FIGURE 3: Equivalent Circuit for Fixed Field DC Motor
7-108
n
SSI32H6231
Servo Motor Driver
WINDING IMPEDANCE
LOOP COMPENSATION
1
17(1+SCLRL I
MECHANICAL RESPONSE
8
CURRENT SENSE
FIGURE 4A: Transfer Function of SSI 32H6231
In Typical Application wHh Fixed Field DC Motor
MECHANICAL RESPONSE
--J
/1 -
1
RIN
I
1
/)K-
"
+
"'-
./
LOOP COMPENSATION
"'-
1
1+
17
./
Km2
SCL(R.+ Rm
SJ9(R. +Rml
CURRENT SENSE
R.
./
RF
"'-
4 -
J9Rrn
Rm
Km 2
Lm
-- «
FIGURE 48: Simplified Transfer Function of
SSI 32H6231 in DC Motor Application
I
"'-
./
II
SSI32H6231
Servo Motor Driver
MOSFETOATE DRIVE
vee . - - - ,- - - - - - - - - - - - :- - - -' -' - - - - - - - - - -
VCC-VTH - -
.
,."" .""."
SEPARATlCW
VTH
_ -
___ -
-
_
. ________ _
ll
>
Z
4
3
2
1
28
27 26
Q
Z
f:::l
0
5
25
A-COMP
24
OUTB
23
B-COMP
OUTA
ERR
[}-------1-f-+----/II..,....---l >--t-----j
SOUT
ERR·
22
SE1
9
21
SE2
RETRACT
10
20
D-COMP
PFAIL
11
19
OUTD
DISABLE
OUTB
SE'
PS1
7
12 13 14 15 16
17
18
ili+
c..l
a.
:::;
OUTO
PS2
aUTe
1.3V
GND
1292 - rev.
PFA1L
BRK
AoCOMP
B-COMP C-COMP
D-COMP
'"
(j,
(/)
0-
0-
Cl
Z
Cl
'"
UJ
(/)
8~
0
CAUTION: Use handling procedures necessary
for a static sensitive component.
SSI32H6240
Servo Motor Driver
Cross over protection circuitry between the outputs of
A4 and AS and the external power transistors ensure
Class B operation by allowing only one transistor in
each leg of the H-bridge to be in conduction. The
crossover circuitry can also disable all Power Transistors simultaneously (to limit motor current or velocity)
or apply a constant voltage across the motor (to retract
the heads at a constant velocity.)
FUNCTIONAL DESCRIPTION
(Refer to block diagram and typical application Fig.2)
There are three modes of operation ofthe SS132H6240:
Disable, Retract, and Linear. The circuit mode is controlled by the DISABLE, RETRACT, PSi, and PS2
pins.
DISABLE mode turns off the output drivers. OUTA and
OUTC are pulled to VCC through internal 1.S kQ
resistors. OUTB and OUTD are pulled to GND through
internal1.S k.Q resistors. Disable mode does not override Retract mode.
RETRACT mode turns off OUTB and OUTC. OUTD is
turned on. OUTA is turned on in a special manner to
force 1V at SE1. Retract mode does override Disable
mode.
POWER FAIL mode occurs when either PSi or PS2
fall below 1.3V. Power fail overrides Retract and
Disable inputs and forces the chip into RETRACT
mode.
When the RETRACT pin is pulled low the SSI32H6240
will go into retract mode. The BRK pin will go high.
When the DISABLE pin is pulled high it will cause all 4
bridge power transistors to turn off. PFAIL and BRK will
remain low if PSi, PS2, and RETRACT pins do not
change.
During linear mode operation an acceleration signal
from the servo controller is applied through amplifier
Ai. Amplifier Ai's three connections are available for
connection to external loop compensation components. The ERR signal drives two precision amplifiers,
each with a gain of 8.S. The first of these amplifiers is
inverting, and is formed from opamp A4, an on-Chip
resistor divider, and an off-chip complementary Bipolar
Power Transistor pair. The second amplifier is noninverting and is formed in a similar manner from opamp
A5. Feedback from external transistor's collectors on
sense inputs SE1 and SE3 allows the amplifier's gains
to be precisely set. The voice coil motor and a series
current sense resistor are connected between SE1
and SE3. The output of the amplifiers will provide the
base current for the external H-Bridge Bipolar Power
Transistors. The chip is designed to work with external
transistors with a minimum Beta of 40 and minimum IT
of 40 MHz. The base bias resistors for the external
bridge transistors are internal to the IC.
Motor current is sensed by a small resistor placed in
series with the motor. The voltage drop across this
resistor is amplified by a differential amplifier with a
gain of 2 (A2 and associated reSistors), whose inputs
are SE1 and SE2. The resulting output voltage, SOUT,
is proportional to motor current, and hence acceleration. This signal is externally fed back to Ai so that the
signal ERR represents the difference between the
desired acceleration (from the servo controller) and the
actual motor acceleration. The total output offset
current (Vin= Vref, Rsense =0.5Q) is lessthanS.5 mAo
The SSI32H6240 has low voltage monitor circuitry that
will detect a decrease in the voltage at PSi and PS2
pins. The +SV and + 12V power supplies are divided
down by extemal resistors and then compared to an
internal1.25V ±5% reference. The power supply pin,
VCC, should be connected to the disk drive's spindle
motor so that its stored rotational energy may be used
to hold up VCC briefly during a power failure. When a
low voltage condition is detected on either the PSi or
PS2 pins the BIPOLAR drivers switch from linear
operation to retract mode. In this mode a constant
voltage is applied across the motor which will cause the
heads to move at a constant speed. A mechanical stop
must be provided for the heads when they reach a safe
location. External current limiting circuitry is required
for both the linear and retract modes of operation. An
open collector output, PFAIL, which is low in the linear
mode, will go high to indicate a power failure. This
signal is gated with the RETRACT input signal to force
the chip into the Retract mode during power failure and
to signal a BRK spindle. A BRK spindle is signaled by
forcing a High level on the BRK open collector output
which is normally low in the Linear mode. The BRK pin
is provided for spindle motor braking. An extemal RC
delay may be used to defer braking until the heads are
retracted.
7-114
DISABLE
+5V
.12V
~
'"
1.3=
D-t
CJ)
CD
<
o
--
3:CJ)
0CJ)
Ow
FIGURE 2: 551 32H6240 Typical Application
""II\)
C:::Z:
~. C')
I\)
CD~
<
•
""10
SSI32H6240
Servo Motor Driver
PIN DESCRIPTION
POWER
NAME
TYPE
DESCRIPTION
VCC
-
POSITIVE SUPPLY - Usually taken from spindle motor supply. Spindle motor stored
energy permits head retraction during power failure. If either a "Power Failure" or a
"Retract" is asserted a forced head retraction occurs. Usually supplied through a
power Schottky diode from Spindle Motor Supply.
5-voH power supply
+5V
I
VREF
I
REFERENCE VOLTAGE - 5.0V input. All analog signals are referenced to this input.
GND
-
GROUND
CONTROL
NAME
TYPE
DESCRIPTION
ERR
0
POSITION ERROR- Loop compensation amplifier output. This signal is amplified by
the BIPOLAR drivers and applied to the motor by an external BIPOLAR H-bridge, as
follows: SE3-SE1 = 17 (ERR-VREF)
ERR-
I
POSITION ERROR INVERTING INPUT - Inverting input to the loop compensation
amplifier.
ERR+
I
POSITION ERROR NON-INVERTING INPUT - Non-inverting input to the loop
compensation amplifier.
SOUT
0
MOTOR CURRENT SENSE OUTPUT - This output provides a voHage proportional
to the voltage drop across the external current sense resistor, as follows: SOUTVREF=4 (SE2-SE1)
BRK
0
BRAKE OUTPUT - Active high, open collector output which may be used to enable an
external spindle motor braking transistor upon power failure. External resistor may be
tied to +5 or +12V.
DISABLE
I
DISABLE DRIVERS INPUT - Logic level input. An input high level will cause all
4 bridge BIPOLAR Power Devices to turn off. DISABLE does not override retract.
RETRACT
I
RETRACT INPUT - Logic level low will assert a forced head retraction. RETRACTwili
override DISABLE. RETRACT will continue to work at VCC=3.5V.
PS1
I
POWER SENSE 1 - 12V sense input to power fail comparator.
PS2
I
POWER SENSE 2 - 5V sense input to power fail comparator.
PFAIL
0
POWER FAIL- Powerfail indicator open collector output. Floats if either supply goes
below threshold.
1.3V
0
0
0
0
0
INTERNAL REFERENCE MONITOR - Used for testing purposes only.
A-COMP
B-COMP
C-COMP
D-COMP
AMPLIFIER A COMPENSATION - Compensation capacitor pin
AMPLIFIER B COMPENSATION - Compensation capacitor pin
AMPLIFIER C COMPENSATION - Compensation capacitor pin
AMPLIFER D COMPENSATION - Compensation capacitor pin
7-116
SSI32H6240
Servo Motor Driver
CONTROL (Continued)
NAME
SE2
TYPE
I
DESCRIPTION
MOTOR CURRENT SENSE INPUT - Non-inverting input to the current sense
differential amplifier. It should be connected to one side of an external current sensing
resistor in series with the motor. The inverting input of the differential amplifier is
connected internally to SE1.
BIPOLAR DRIVE
SE3
I
MOTOR VOLTAGE SENSE INPUT - This input provides feedback to the non-inverting
BIPOLAR driver amplifier. It is connected to one side of the motor. The gain to this
point is: $E3-VREF = 8.5 (ERR-VREF)
SE1
I
MOTOR VOLTAGE SENSE INPUT - This input provides feedback to the inverting
BIPOLAR driver amplifier. It is connected to the current sensing resistor which is in
series with the motor. The gain to this point is:
SE1 - VREF = -8.5 (ERR-VREF)
OUTA
0
PNP DRIVE (INVERTING) - Drive signal for a PNP power transistor connected
between the current sense resistor and VCC. The PNP collector is also connected to
SE1. Crossover protection circuitry ensures that the PNP andNPN devices driven by
OUTA and OUTB are never simultaneously enabled.
OUTB
0
NPN DRIVE (INVERTING) - Drive signal for an NPN power transistor connected
between the current sense resistor and GND. This NPN collector is also connected
to SE1.
OUTC
0
PNP DRIVE (NON-INVERTING) - Drive signal for a PNP power transistor connected
between one side of the motor and VCC. This PNP collector is connected to SE3.
Crossover protection circuitry ensuresthatthe PNP and NPN devices driven by OUTC
and OUTD are never simultaneously enabled.
OUTO
0
NPN DRIVE (NON-INVERTING) - Drive signal for an NPN powertransistorconnected
between one side of the motor and GND. This NPN collector is connected to SE3.
Crossover protection circuitry ensures thatthe PNP and NPN devices driven byOUTC
and OUTD are never simultaneously enabled.
7-117
II
SSI.32H6240
Servo Motor Driver
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(Maximum limits indicates where permanent device damage occurs. Continuous operation at these limits
is not intended and should be limited to those conditions specified in the DC operating characteristics.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
0
16
V
VREF
0
10
V
+5V
0
7
V
SE1, SE2, SE3
-1.5
15
V
DISABLE, RETRACT
-.3
+5V+.3
V
All other pins
-.3
VCC+.3
V
Storage temperature
.-45
165
°C
260
°C
Solder temperature
10 sec duration
RECOMMENDED OPERATION CONDITIONS (Unless otherwise noted, the following conditions are valid
throughout this document.)
VCC
Normal Mode
Retract Mode
12
13.2
13.2
5
5
5.5
5.5
70
°C
13
20
mA
15V, +5V Current
0.6
1
mA
IREF, VREF current
300
9
3.5V
4.5
4.5
0
+5V
VREF
Operating temperature
V
V
V
V
DC CHARACTERISTICS
ICC, VCC current
~
A1, LOOP COMPENSATION AMPLIFIER
Input bias current
Input offset voltage
Voltage swing
Abou1VREF
2
Common mode range
Abou1VREF
±1
Load resistance
ToVREF
4
Gain
Unity gain bandwidth
CMRR
1<20 kHz
PSRR
f<20 kHz
7-118
500
nA
3
mV
V
V
k.Q
80
dB
1
MHz
60
dB
60
dB
SSI32H6240
Servo Motor Driver
A2, CURRENT SENSE AMPLIFIER
PARAMETER
CONDITIONS
MIN
TYP
Input impedance
SE1 to SE2
7.0
10
Input offset voltage
SE1 = SE2 = VREF
Output voltage swing
Common mode range
Load Resistance
ToVREF
Output impedance
1<40 kHz
Gain (SOUT-VREF)/{SE1-SE2)
VSE2 = VREF
MAX
UNITS
kG
2
mV
VREF-4
VCC-1.2
V
0
VCC-O.2
20
1.95
Unity gain bandwidth
V
kQ
4
2
2.05
Q
VN
1
MHz
CMRR
1<20 kHz
52
dB
PSRR
1<20 kHz
60
dB
POWER SUPPLY MONITOR
1.3V pin voltage
1.3V pin open
US
1.25
1.31
V
PSi threshold
1.25
V
PS2 threshold
1.25
V
20
mV
PSi, PS2 Hysteresis
PSi, PS2 Input Bias Current
PSi, PS2 = 1.3V
PFAIL VOL
Linear mode IOC = 1mA
0.4
BRKVOL
Linear mode IOC = 1mA
0.4
V
PFAIL IOH
Retract mode VOH = 12V
10
).LA
).LA
1
V
BRK IOH
Retract mode VOH = 12V
10
).LA
DISABLE ilL
VIL = O.SV
2
20
).LA
RETRACT ilL
VIL = O.SV
2
10
).LA
DISABLE IIH
VIH = 2.4
1
10
).LA
RETRACT IIH
VIH = 2.4
1
10
).LA
DISABLE and RETRACT
1.4
Threshold Voltaae
7-119
V
I
SSI32H6240
Servo Motor Driver
BIPOLAR DRIVERS
PARAMETER
CONDITIONS
SE3 Input Impedance
To VREF
MIN
TYP
10
25
MAX
UNITS
kO
A Comp, C Comp Voltage Swing
wI Extemal Trans.
vcc -1.4
VCC-.7
V
B comp, 0 Comp Voltage Swing
wI Extemal Trans.
0.7
1.4
V
Output Impedance
A, B, C, 0 Comp
Output Off, No Extemal Trans.
Transconductance
I (A, B, C, 0 Comp)/(ERR-VREF)
Gain
-(SE1-VREF)/(ERR-VREF) or
(SE3-VREF)/(ERR-VREF)
Includes External Trans.
Offset Current
(A2 Vos)
Rs = 0.50 Rf
Yin = Vref
8
= Rin
0.7
= 0.8V
Vout
Out B, Out 0
Current Limit
Vcc = 10.8V, Out B, 0
Vcc = 12.0V, Out B, 0
Out A, Out C
Sink Current
Vout
kQ
6
mAN
8.5
9
3.5
Retract Motor Vottage
(SE1-SE3)
Out B, Out 0
Source Current
75
1.3
mA
1.7
20
= 11.2V
= 0.8V
= 0.8V
20
23
VN
V
mA
25
27
20
30
33
mA
mA
mA
Band 0 Output
NPN Output Transistor Beta
Ic = 20mA Vce
= 10V
20
VN
A and C Output
PNP Output Transistor Beta
Ic = 20mA Vce
= 10V
10
VN
7-120
BOCS1
1 - 1- - - - - - - - - - - - - . . - -_ _
I
I
0
(.,.
~XO
+12V
J1'RE'T'RlIl:T
:k:~~~:, :~'~ fT
kPS2
~X,
J~z
PO.O
IIN~
r l DISABLE
~I
Vee
.1
-W
PS'
GND
CS
RSIAS
RD
AGND
WR
WR
INT
INT
'bc
I
I r 1r
wI I
+5V)
1
cSVP.l
~RES~
q
DGND
THR
VeeNI-------l
D.' ""
~
~
IN+
~
IN.
SERVO 0.1
READ HEAD
SYNC
=F
I---<
ACOMP
BCOMP SE' I----+-~rr_____-o0.5
RS
CS,
=E RP4
AS'
PE
1--......_-'-___--,
C,
FV4
C2
SSI32H&220
II
1--..........,
CveD
CSVP
VPA
BP2
"1
RW
=
""F
~
"
.
SERVO
DEMODULATOR
FV2
sour
I-t-+---+---,NII-
SP'
l
FV1
SK'
I---------~+;/Jjy
TW
SSI 32118210
~D1
Cb
SYNC
CLOCK
----i--t--..,
1-1
ourAK
=~
JLF
'2V
SE2
Co
=IE Rp3
FP4
ourcrl---I---+-----\---+------.
1~1
RP2
,I l
N
a ----------I a
~
5V
cp,-L
FP21
OGND
1-1
-.j
Rp'=f
VDD
~RTH
PREAM'UFIER
FP'~
~ S~~~°Motor
Csvp
SK2
VE
:L{*-
~.s5VV:---t--+---~---...1
5vI '(
• •
OUTO II
ERR
SSI 32H62AO
SRK
ERR·
L-~~E_F__~
SERVO
CONmOLLER
en
CD
<
ROS
o
CSVP
f
:s::en
-Oen
Ow
""'II\)
FIGURE 3: Complete Example of Servo Path Electronics using the SS132H6210/6220/6240 Chip Set
•
C::::r::
:!. en
>
"1
~
j:!
:::l
0
1 28 27 26
ERR+
25
VREF
A-COMP
OUTB
SOUT
23
B-COMP
BRK
22
SEl
SE2
DISABLE
21
~
20
D-COMP
PFAIL
19
ouro
12 13 14 15 16 17 18
>
It)
+
0
~ ~ z(!l rnrn
"~ :::;;
0
9
:::l
.0
()
28-Pln PLCC
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use tor
final design.
No responsibility is assumed by Silicon Systems for use of this product nor tor any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX: (714) 573-6914
1292 - rev.
©1990 Silicon Systems, Inc.
7-122
SSI32H6510
5V Servo Driver
'W'§'hi""'I·M6'
January 1993
DESCRIPTION
FEATURES
The SSI32H651 0 is a fully integrated power amplifier for
use in disk drive head positioning systems employing
linear or rotary voice coil motors. It is intended for use in
5V systems and is capable of generating ±1 Amp motor
currents. The part is intemally thermal overload protected.
•
•
36-pin SO package
Internal 1A power devices
•
•
NMOS output stage
Total on resistance less than 1.30 at 500 rnA
•
Thermal overload protection
The SSI32H651 0 is a power transconductance amplifier for use in driving voice coil type servo motors
(VCMs). The SSI 32H651 0 has two primary modes of
operation, normal (or linea~) and retract. The retract
mode is activated by a power supply failure or when
RETRACT is asserted. Otherwise the device operates
in linear mode.
•
No deadband, low distortion, class B output
•
Low power sleep mode
•
•
Gain select switch optimizes performance with
S-bit DACs
Built In retract circuitry
•
Power fault detection
BLOCK DIAGRAM
VP
VP
PIN DIAGRAM
VP
000
GNO
saUT
SWIN
ERRM
swaN
GND
GND
SEl
VMl
SE2
RF
ERR
VP
VRETRACT
VP
VP
VBYPl
VP
RIN
VP
VLN
GND
RC
VP
cc
VP
VBGAP
IBR
SVS'RST
~
""
VP
VP
VCH
~
SLEEP
TSll"
SLEEP
RBIAS
0193 - rev.
THTEST
7-123
CAUTION: Use handling procedures necessary
for a static sensitive component.
I
SSI32H6510
5V Servo Driver
DESCRIPTION (continued)
POWER AMPLIFIER
The SSI32H651 0 consists offive major blocks: SOUT
amplifier, ERR amplifier, retract amplifier, power amplifier, and control circuitry. These parts are each described in this section. External components needed
for proper operation of the SSI 32H6510 are also
described.
The power amplifier is a fixed gain voltage amplifier
with differential inputs and outputs. Its input is the
differential voltage between ERR and VBGAP. Its
output drives the VCM directly.
SOUT AMPLIFIER
This amplifier generates a voltage at SOUT that is
proportional to positioner current. It does this by sensing the voltage across Rs, amplifying it, and referencing the result to VREF. Since the common mode
voltage on Rs can range over the full power supply,
while the differential voltage is a few millivolts, the
SOUT amplifier is designed to have very high input
common mode rejection, and. very low input offset.
RETRACT AMPLIFIER
When a voltage fault is sensed, or when RETRACT is
asserted, the SSI32H651 0 enters retract mode. Inthis
mode, it is assumed that no current is available from VP
(VP may actually be at GND potential). Thus power for
this mode comes from VBEMF, the rectified spindle
back EMF voltage, and from VBYP1, a voltage generated from the external storage capacitor CBYP. The
retract amplifier is powered by VBYP1. It senses the
voltage at VRETRACT and raises VM1 to be equal to
VRETRACT. The drain olthe source follower is VBEMF.
ERR AMPLIFIER
CONTROL CIRCUITRY
The ERR amplifier is a high gain op amp. Due to the
fixed gain of the power amp, ERR is proportional to the
VCM voltage. The negative input of this amplifier is the
system summing junction--currents proportional to the
desired VCM current, the measured VCM current, and
the VCM voltage are summed here.
The control circuitry consists of voltage monitoring
circuitry, a thermal overload circuit, and control logic.
The inputs to the control circuitry are the external
signals RETRACT, VCHK, and SLEEP, along with
internal signal from the thermal overload detector (visible externally on TSD). Table 1 describes the behavior
of the part in response to these inputs.
TABLE 1: IC Mode Selection
INPUT
SLEEP
CHIP FUNCTION
RETRACT
VCHK>VBGAP
TSD
BRIDGE
RETRACT
X
X
0
0
Off
Off
0
X
X
0
1
Off
On
0
X
X
1
0
Off
1
X
0
1
1
Off
Off
On
1
0
1
1
1
On
1
1
i
1
1
Off
Off
Off
7-124
SYSRST
1
SSI32H6510
5V Servo Driver
PIN DESCRIPTION
NAME
TYPE
DESCRIPTION
VP
Power
The positive power supply. The VP pins are thermally connected to the die and
provide a low thermal resistance path to the circuit board. All VP pins should
be shorted together.
GND
Power
The negative power supply. All GND pins should be. shorted together.
SWaN
Dig In
Turns on the switch between ERRM and SWIN.
SWIN
An In
SOUT
An Out
The current sense amplifier output. SOUT is referenced to VREF.
ERR
An Out
The error amplifier output. ERR is used to provide compensation to the
transconductance loop. ERR is referenced to VBGAP.
One side of an analog switch connected to ERRM.
ERRM
An In
The error amplifier negative input.
VREF
An In
The reference voltage for the error amplifier and the current sense amplifier.
RETRACT
Dig In
When low, forces a retract.
THTEST
Dig In
Test input.
VCHK
An In
Comparator input for power supply monitoring. When VCHK is below VBGAP,
an internal voltage fault is generated.
VBGAP
An Out
An internal voltage reference for use with the powersupply monitorcomparator.
IBR
An Out
A resistor is tied from this pin to ground to establish the bias current for internal
circuitry.
Dig In
Turns off the output drivers. Does not override the retract function when a
voltage fault occurs. Powers down all but the voltage monitor and retract
circuitry.
TSD
OIC Out
Thermal Shut Down. When low, this open collector output indicates that .the
junction temperature has exceeded the recommended operating range and
that the part is in thermal shutdown.
RCRST
OIC Out
This pin serves the dual purpose of providing power-on-reset and stretching
short VFAULT pulses to a width suitable for the host microcontrolier. An
external RC network sets the minimum width of any SYSRST pulse.
SYSRST
OIC Out
When low, this open collector output indicates that an internal voltage fault has
occurred.
SLEEP
VRETRACT
An In
The retract Voltage. Supplied externally by a diode reference.
VBYP1
An In
The bypassed power supply. An external capacitor is connected to this node
to store charge for use by the retract circuitry.
VBYP2
An In
The other side of the bypass capacitor is connected here.
VBEMF
An In
Rectified spindle back emf Voltage. This input provides current to the internal
retract power FET.
7-125
I
SSI32H6510
5V Servo Driver
PIN DESCRIPTION (continued)
TYPE
DESCRIPTION
VM2
An Out
One side of the voice coil motor.
VM1
An Out
The other side of the voice coil motor and sense resistor combination.
NAME
SE1, SE2
An In
The sense voltages around the sense resistor.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation of the part outside these limits may result in degradation or failure of the device.
RATING
UNITS
7
V
-0.3 to 16
V
V
All others
-0.3 to 12
-0.3 to VP+.3
Storage Temperature
-45 to 165
°C
260
°C
2
Amp
150
°C
PARAMETER
Power Supply, VP
Voltage on any pin
VBEMF, VBYP1, VBYP2, SYSRST, RCRST
VM1, VM2, SE1, SE2
Solder Temperature (10 sec duration)
Output Current - I(VM1), I(VM2)
Junction Temperature
V
RECOMMENDED OPERATING CONDITIONS
The performance specifications for this part apply only when the operating environment is within this specified
range.
PARAMETER
CONDITIONS
Power Supply, VP
Junction Temperature
MAX
UNIT
4.75
5.25
V
0
125
°C
1.0
Amp
MIN
Output Current - I(VM1), I(VM2)
NOM
VBEMF
1.0
14
V
VREF
0.5
VP-2
V
RF
10
kQ
RC
10
kQ
RBIAS
VBYP1 - Retract Mode
7·126
21.5
22.5
kQ
3
14
V
SSI32H6510
5V Servo Driver
PERFORMANCE SPECIFICATIONS
DESCRIPTION
CONDITIONS
MIN
VP Supply Current:
Normal operation, Imotor = 0
Sleep mode
NOM
MAX
UNITS
15
mA
2
mA
4.1
VIV
-3
3
mV
0.15
VP-1
V
-10
10
mV
ERR output swing
1.6
3.25
V
GAIN (VM1-VM2)/(ERR-VBGAP)
11
13
VIV
VBGAP
2.13
2.37
V
VCHK offset
-15
15
mV
-50
50
mV
SOUT gain
3.9
SOUT input offset (SOUT
= VREF)
SOUT output swing
ERRM input offset (ERR
= ERRM)
Retract offset
VRETRACT
= 0.5V
VRETRACT input impedance
kQ
500
Output voltage drop: VP-IVM1-VM21
lmotor = ± 0.5A, Tj
0.65
V
Imotor =
0.15
V
= 25°C
± O.1A, Tj = 25°C
Thermal shutdown temperature
Thermal shutdown hysteresis
120
140
°C
3
7
°C
45
IJS
2
%THD
Crossover time
imotor = 10mA p 1000 Hz
Crossover distortion
Imotor
= 10mA p 1000 Hz
Digital open collector output, sink current:
SYSRST,RC_RST,TSD
1.6
Vol = O.4V
SWIN on resistance
mA
250
7-127
Q
II
SSI32H6510
5V Servo Driver
PACKAGE PIN DESIGNATIONS
(Top View)
VREF
SOUT
VBEMF
SWIN
VBVP2
ERRM
SWON
GND
GND
SEl
VMl
SE2
NlC
ERR
VP
VREmACT
VBVPl
VM2
VP
VP
VP
VP
THTEST
GND
VP
VP
VP
VP
VBGAP
IBR
SLEEP
36-Lead SOM
ORDERING INFORMATION
PART DESCRIPTION
SSI32H6510
ORDER NUMBER
36-Lead SOM
32H6510
PACKAGE MARK
32H6510
Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights ortrademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
0193 - rev.
©1991 Silicon Systems, Inc.
7-128
SSI32H6520
Embedded Se.rvo Controller
I; i§ '" ,j 'IE' fi ,JiG'
December 1993
DESCRIPTION
FEATURES
The 32H6520 Embedded Servo Controller is a CMOS
monolithic integrated circuit housed in a 48-pin TQFP
and operates on a single +5.0 volt supply. It provides
one 10-bit AID converter with 2.5 J.lS conversion time,
and two 10-bit D/A converters with 2.5 J.lS digital delay
as well as Motorola/Intel compatible bus interface
(Motel) to commonly used microcontrollers such as
SOC196 and 68HC11. In addition, it includes bus interface logic to support DSP-based, such as TMS320XX,
digital servo applications.
Embedded Servo Burst Processor
•
Servo control for Winchester disk drives with
embedded servo sectors
•
For use in I1P/DSP-based digital servo
applications
•
Pulse area detects and S/H circuits for up to
four embedded servo bursts
•
Programmable gain adjustment from -2.S dB to
3.2 dB
(continued)
BLOCK DIAGRAM
II
STAAT
ROADRO
)--->- -1>---=--------------------¢ VREF
VREF~-+-r.::=:::-l
VROK_-c..~--.J
P~T~--------~------7
IBR
PSV
VAEF
PAOCESSOA INTERFACE
AND
REGISTERS
(6.88ITS)
1293 - rev.
7-129
SSI32H6520
Embedded Servo Controller
FEATURES (continued)
Data Acquisition and Microprocessor/DSP Bus
Interface
•
Motel bus interface compatible with 80Ci96
and 68HCii
•
Bus interface logicto support DSP-based digital
servo applications
•
Eight internal registers and address decoding
•
Two i0-bit D/A converters with 2.5 lIS digital
delay
•
One 8-channeli O-bit AID converter with 2.5 lIS
conversion time
General Functions
•
Voltage fault detection
•
Low power CMOS design
•
48-pin TQFP
FUNCTIONAL DESCRIPTION
The 32H6520 can be divided into four major sections:
embedded servo burst processor, voltage fault detector/logic, data acquisition and microprocessor/DSP
bus interface.
EMBEDDED SERVO BURST PROCESSOR
The embedded servo burst processor extracts the head
position error information from the embedded servo
bursts using an area detection technique. The area
detection technique provides improved noise immunity
over peakdetector. The embedded servo burst processorcontains a differentiaVgain amplifier, four pulse area
detectors and required timing logic. First, a full waverectified analog signal from a read data channel, such
as SSI 32P4620, is provided at SERIN through an
external resistor equal to Rint and a DC reference level
forthefullwave-rectified analog signal at SEREFthrough
another external resistor equal to Rint. To accommodate a wide dynamic range of servo burst amplitudes
and process variations of the integration capacitor Cint,
the differential signal between SERIN and SEREF is
scaled under lIP control. The gain of the differential
amplifier ranges from -2.8 dB to 3.2 dB in a step of 0.4
dB, as defined in the SERVO GAIN CONTROL register.
The output of the differentiaVgain amplifier is then
provided to four pulse area detectors whose output are
proportional to the area above the DC reference level
during time intervals defined by an external timing
source through INTEG. Each area detector applies an
on-Chip capacitor Cint equal to 10 pF to integrate the
incoming pulses during the integration interval andthen
hold the integrated voltage outputs thereafter. Note that
the max ±20% tolerance of on-Chip capacitors can be
calibrated out by adjusting the gain of the preceding
amplifier. Finally, the integrated voltage outputs at
BURSTi, BURST2, BURST3 and BURST4 are providedto a 1O-bit AID converterunderllP control and will
be discharged during a time interval defined by an
external timing source through INTAZ. For proper
operatons, the lime interval defined by the INTAZ must
be no less than 0.5 !lS and be applied only once per
servo frame preceding the integration pulses defined by
the INTEG.
Limited timing logic is included to generate all the timing
signals required for the embedded servo burst processor, per figure 1. These timing signals control the
integration, sample/hold of the pulse area detectors.
The number of embedded servo bursts supported by
this circuit are two, three or four. The BSTSELO and
BSTSEL 1 bits in the SERVO CONTROL register configure the internal timing logic to generate a servo burst
ready interrupt after the last servo burst is captured.
VOLTAGE FAULT DETECTOR/LOGIC
The voltage fault detector monitors the power supply
applied at PSV through an external resistor divider,
which defines the trigger level for power supply failure.
An open-drain output VFAULT is pulled HIGH by an
external resistor when a power supply failure is sensed
by the PSV comparator. The user-defined trigger level
for voltage failure is applied at PSV. Another open-drain
output, opposite logic polarity as the pin VFAULT and
with an additional RC delay, is provided at SYSRST.
The amount of SYSRST delay is determined by an
external RC connected to the pin, RCRST.
DATA ACQUISITION
The AID converter is multiplexed to eight different
analog inpuls by programming the ADC SELO,
ADC SEL 1, and ADC SEL2 bits in the ADC ADDRESS
register by the lIP. The eight analog inputs multiplexed
to the AID converter are four embedded servo processor outputs at BURSTi, BURST2, BURST3 and
BURST4 and four external analog inputs through four
T/H amplifiers. These T/H amplifiers sample extemal
7-130
SSI32H6520
Embedded Servo Controller
DATA ACQUISITION
(continued)
analog inputs during the time interval defined by an
external timing source applied at ADCSH. If the sampling of four external analog inputs is not necessarily
synchronized, AOCSH must be tied to HIGH. The NO
conversions on these external analog inputs are always referenced to the internal voltage reference at
2.23 volts. An operational amplifier with uncommitted
inputs is provided to implement a level shifting function
for the external analog input applied to AUXINP. The
output of the operational amplifier is tied to ADCIN1.
The NO converter starts to acquire a new analog input
whenever the conversion is completed. A minimum of
1 JlS is required to acquire an analog input to the NO
converter. Actual conversion is started by reading the
NO MSB register or by an external timing source
appliedtoADCSTR. The NO address lines ADC SELO,
ADC SEL 1, and ADC SEL2 will be incremented by one
after the NO conversion is started. The automatic
increment of the address lines is employed to eliminate
repetitive write operations by the JlP to the ADC ADDRESS register required for converting the consecutive analog inputs.
The NO converter runs synchronously with the internal
4 MHz clock which is used for various circuits on the
32H6520 and divided down from the system clock
SYSCLK by a prescaler. Therefore there would be a
maximum of 0.25 JlS of latency between a conversion
request and the actual start of the conversion. The
output is coded in 2's complement.
Similarly, the D/A converters run synchronously with
the internal 2 MHz clock and the conversion is started
by writing to the corresponding D/A input register. The
output of the first D/A converter is referenced to an
external analog input, DACREF1 and the output of the
second D/A converter is referenced to an external
analog input, DACREF2. In the "normal" mode when
STBEN1 (STBEN2) bit in the ADC ADDRESS register
is reset, the D/A output will be automatically applied to
DACOUT1 (DACOUT2) during the conversion. In the
"strobe" mode, the D/A output will be applied to
DACOUT1 (DACOUT2) at the falling edge of RD for a
read to the corresponding D/A MSB DATA register.
MICROPROCESSOR/DSP BUS INTERFACE
The 32H6520 is provided with Motorola/Intel compatible bus interface for a direct connection to popular
microcontrollers such as 80C196 and 68HC11. It also
contains logic to interface with TMS320XX for DSPbased servo applications. Bus control signals ALE, RD,
WR and BUSMODE are interpreted differently, as described in table 1, based upon the type of processors
being used. When the 32H6520 is interfaced with
TMS320XX, the pin DSPMODE must be tied to HIGH
and the pin BUSMODE is redefined as XFER/SEL. The
pin BUSMODE must be tied to HIGH for an Intel bus
interface and LOW for a Motorola bus interface. The
ASE pin gates the ALE/AS input and can be used to shut
off the ALE/AS to minimize noise on the chip when the
JlP interface is not active. The CS pin performs a similar
function on the rest of the JlP bus inputs. The timing
diagrams for different processors are depicted in Figures 2, 3 and 4.
TABLE 1: Microprocessor/DSP Bus Interface
32H6520
Intel
Motorola
TMS320XX
DSPMODE
LOW
LOW
HIGH
BUSMODE
HIGH
LOW
XFER/SEL (PAO)
CS (PAi)
CS
CS
CS
ALE
ALE
AS
N/C
RD
RD
DS;E; or
Clock Phase 2
REN
WR
WR
R/W
WE
7-t31
II
SSI32H6520
Embedded Servo Controller
REGISTER DESCRIPTIONS
The 32H6520 contains eight a-bit internal registers
which provide control, option select and status monitoring. The registers are addressed with a 3-bit register
address which is latched from inputs at ADO(LSB),
AD1, and AD2(MSB) at the falling edge of ALE. The
registers 0, 2, and 3 are read/write memory, and the
registers 1, 4, 5, 6, and 7 are write only memory. The
registers are summarized in Table 2.
TABLE 2: Register Descriptions
ADDRESS
TYPE
0
R/W
REGISTER NAME
INTERRUPT MASK/STATUS
SERVO GAIN CONTROL & PRESCALER
1
W
2
R/W
ADC LSB DATA
3
R/W
ADC ADDRESS & MSB DATA
4
W
DAC1 LSB DATA
5
W
DAC1 MSB DATA
6
W
DAC2 LSB DATA
7
W
DAC2 MSB DATA
INTERRUPT MASK/STATUS REGISTER
Address: 0
Access: Read/Write
Reset: Bit 0, 1 only
Register contents when Written:
NAME
DESCRIPTION
0
BURST INT
When set HIGH, interrupt is enabled on the embedded servo position bursts ready.
1
ADCINT
When set HIGH, interrupt is enabled on the completion of the AID conversion.
BIT
2-7
Unused.
Register contents when Read:
BIT
NAME
DESCRIPTION
0
BURSTRDY
Active high indicates that the embedded servo bursts are ready.
1
ADCRDY
Active high indicates that the AID conversion is completed.
Each interrupt event status will be reset after the J.!P reads this register. The interrupt control register determines
if the event will actually cause a latched assertion of the IlP signal INT.
7-132
SSI32H6520
Embedded Servo Controller
SERVO GAIN CONTROL & PRESCALER REGISTER
Address: 1
Access: Write
Reset: 00
BIT
NAME
DESCRIPTION
0
1
SCALEO
SCALE1
SYSCLK Prescaler. To accommodate different system clocks, the prescaler selects
a proper divider to generate a fixed clock at 4 MHz per table below:
2
3
4
5
6
7
GAINO
GAIN1
GAIN2
GAIN3
BSTSELO
BSTSEL1
SCALE1
SCALEO
SYSCLK(MHz)
0
0
16
4
0
1
12
3
1
0
8
2
1
1
4
1
Divider
Servo Burst Amplitude Gain Select. These four bits define the gain setting for
the differential/gain amplifier per table below:
GAIN3
GAIN4
GAIN3
GAl NO
Gain, dB
0
0
0
-2.8
0
0
0
0
1
0
0
1
0
-2.0
-2.4
0
0
1
1
-1.6
0
1
0
0
-1.2
0
1
0
1
-0.8
0
1
1
0
-0.4
0
1
1
1
+0.0
1
0
0
0
+0.4
1
0
0
1
+0.8
1
0
1
+1.2
1
0
1
0
1
1
1
0
0
+2.0
1
1
0
1
+2.4
1
1
1
0
+2.8
1
1
1
1
+3.2
+1.6
Burst Number Select. These two bits define the number of embedded servo bursts
per sector.
BSTSEL1
BSTSELO
# of Bursts
0
0
2
0
1
3
1
0
4
7-133
SSI32H6520
Embedded Servo Controller
ADC LSB DATA REGISTER
Address: 2
Access: Read/Write
Reset: Bit 5, 6, 7 only
Register contents when Written:
BIT
NAME
0-4
DESCRIPTION
Unused.
5
SLEEP'
Power-down Mode Enable. When set HIGH, the device is in the sleep mode where
all analog circuitry are de-biased, the clock is disabled, anQ the bandgap
voltage, reference voltage fault logic and processor interface stay active.
6
STBEN1
When set HIGH, the analog output of the DACi is transferred and held onto
DACOUTi.
7
STBEN2
When set HIGH, the analog output of the DAC2 is transferred and held onto
DACOUT2.
Register contents when Read:
Description: After AID conversion, the least significant 2 bits ofthe 1O-bit digital word is stored into the register.
Unused. Logic LOW is provided to these bits.
0-5
6,7
ADCO, ADCi
The LSB 2 bits of the AID converter output in 2's complement format.
ADC ADDRESS & MSB DATA REGISTER
Address: 3
Access: Read/Write
Reset: Bits 0, 1, 2, and 3 only
Description: When Wrjtten, the least significant 3 bits of the register define the analog input to the 1O-bit AID
converter. After conversion, the most significant 8 bits of the i0-bit digital word is stored into the register.
Register contents when Written:
0
1
2
ADC SELO
ADC SRi
ADC SEL2
AID Converter Input Select. These 3 bits define the analog inputlo the AID converter
per table below:
BIT2
BIT1
BITO
ADCINPUT
0
0
0
ADCINi
0
0
1
ADCIN2
0
1
0
ADCIN3
0
1
1
ADCIN4
1
0
0
BURSTi
1
0
1
BURST2.
1
1
0
BURST3
1
1
1
BURST4
,.
7-134
..
SSI32H6520
Embedded Servo Controller
ADC ADDRESS & MSB DATA REGISTER (continued)
BIT
NAME
DESCRIPTION
3
ADC CALIB
When set HIGH, VREF (2.23 volts) is applied to the AJD converter input.
4-7
Unused.
Register contents when Read:
ADC2-9
The MSB 8 bits of the AJD converter output in 2's complement. ADC9 is the sign bit.
DAC1 LSB DATA REGISTER
Address: 4
Access: Write
Reset: 00
0-5
6,7
Unused.
DACO,
DAC1
The LSB 2 bits to the DAC1 in 2's complement.
DAC1 MSB DATA REGISTeR
Address: 5
Access: Write
Reset: 00
0-7
I DAC2 - 9
The MSB 8 bits to the DAC1 in 2's· complement, DAC9 is the sign bit.
DAC2 LSB DATA REGISTER
Address: 6
Access: Write
Reset: 00
0-5
6
7
Unused.
DACO,
DAC1
The LSB 2 bits to the DAC2 in 2's complement.
DAC2 MSB DATA REGISTER
Address: 7
Access: Write
Reset: 00
DAC2-9
The MSB 8 bits to the DAC2 in 2's complement. DAC9 is the sign bit.
7-135
SSI32H6520
Embedded Servo Controller
PIN DESCRIPTION
POWER SUPPLIES
NAME
DESCRIPTION
VPA
Analog +5V supply.
VPD
Digital +5V supply. It must be shorted to analog +5V supply extemally.
VNA
Analog ground.
VND
Digital ground. It must be shorted to analog ground externally.
PSALT
Alternate Voltage Supply to power the voltage fault logic during a voltage fault. This
power supply should be taken from the system +5V supply through a Schottky diode and
be connected to a capacitor, which is used to hold up PSALT briefly during a voltage fault.
EMBEDDED SERVO BURST PROCESSOR
NAME
TYPE
DESCRIPTION
SERIN
I
Servo Burst Input - Full-wave rectified analog signal generated from a read
data channel. This input is to extract the position information from
embedded servo bursts.
SEREF
I
Servo Burst Reference - A DC reference level for the full-wave rectified
analog signal SERIN.
INTEG
I
Pulse Area Detector Enable - This TTL compatible input, when HIGH,
activates thepulse area detectors.
INTAZ
I
Integrator Capacitor Reset - This TTL compatible input, when HIGH,
discharges the holding capacitors, Cin!.
VOLTAGE FAULT DETECTION
PSV
I
Fault Voltage Comparator Input - A voltage input for the low voltage
comparlltor. This input should be connected to an extemal resistor divider.
The resistor divider divides its corresponding supply voltage to a proper
value which is comparable with the intemal voltage reference at 2.23 volts.
VREF
0
VREF Output - A buffered voltage reference at 2.23 volts.
IBR
0
Pin for connection to an external resistor (from GND) to establish a
reference current for bias currents required for analog circuits.
VFAULT
0
Voltage Fault Indication - An open-drain output which is pulled HIGH when
a supply voltage fault is detected.
SYSRST
0
Reset Output - An open-drain output which is pulled LOW with an amount
of delay determined by an external RC connected to the pin RCRSTwhen
a supply voltage fault is detected.
RCRST
0
Pin for connection to an external RC to implement the
delay of active LOW SYSRST.
7-136
SSI32H6520
Embedded Servo Controller
MICROPROCESSORIDSP BUS INTERFACE
NAME
TYPE
DESCRIPTION
ALE
I
Address Latch Enable - Falling edge latches the register address from the
ADO - AD7 address/data bus.
ASE
I
Address Strobe Enable - When set LOW, this input enables ALE input to
the device.
CS
I
Chip Select - Active LOW signal enables the device to respond to IJ.P read
or write.
WR
I
Write Strobe - In Intel p.P applications, active LOW signal causes the data
onthe address/data bus to be written to the addressed register if CS is also
active.
RD
I
Read Strobe - In Intel !J.P applications, active LOW signal causes the
contents of the addressed register to be placed on the address/data bus
if CS is also active.
ADO-AD7
I/O
Address/Data Bus - 8-bit bus which carries register address information
and bidirectional data. These pins are in the high impedance state when
not used.
BUSMODE
I
Mode Select - When active HIGH, Intel bus interface is selected. Otherwise, Motorola bus interface is selected. For DSP interface, when
DSPMODE set HIGH, this input is redefined as XFERISEL.
INT
0
Interrupt Strobe - An open-drain output which signals the p.P to respond
to the device. It is released when all pending interrupts have been serviced
by the !J.P.
DSPMODE
I
DSP Mode Select - When active HIGH, DSP bus interface is selected.
SYSCLK
I
System Clock Input - A TTL compatible input for the system clock which
is divided down with a prescaler to generate internal timing signals.
DACOUT1
0
DAC 1 Output - A 1O-bit D/A output which converts a digital word from the
!J.P into an analog signal.
DACREF1
I
DAC1 Output Reference - An external analog input to be provided to
DAC1 as a reference voltage for DACOUT1.
DACOUT2
0
DAC2 Output - A 10-bit D/A output which converts a digital word from the
p.P into an analog signal.
DACREF2
I
DAC2 Output Reference - An external analog input to be provided to
DAC2 as a reference voltage for DACOUT2.
ADCIN1
ADCIN2
ADCIN3
ADCIN4
I
External ND inputs.
ADCSH
I
ND Analog Sampling Input Strobe - A TTL compatible control signal.
During active HIGH, four track/hold amplifiers prior to the ND converter
will sample external ND analog inputs.
DATA ACQUISITION
7-137
II
SSI32H6520
Embedded Servo Controller
DATA ACQUISITION (continued)
NAME
TYPE
DESCRIPTION
ADCSTR
I
AID Conversion Start Strobe - A TTL compatible control signal whose
rising edge triggers the start of the AID conversion.
AUXINP
I
Level Shifter Noninverting Input - Noninverting input to the level-shifting
amplifier.
AUXINM
I
Level Shifter Inverting Input - Inverting input to the level-shifting amplifier.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Exposure to absolute maximum rating conditions for extended periods may cause permanent damage to the
device or affect device reliability.
SYMBOL
PARAMETER
RATING
VDD
Supply voltag.e applied at VPA, VPD
-0.3 to 7.0V
GND
Signal ground applied at VNA, VND
O.OV
PSALT
Supply voltage applied at PSALT
-0.3 to 7.0V
VIND
Digital input voltages
-0.3 to VDD +0.3V
VINA
Analog input· voltages
-0.3 to VDD +0.3V
Tstg
Storage temperature
-65 to 150°C
TI
Lead temperature (10 seconds)
300°C
RECOMMENDED OPERATING CONDITIONS
The recommended operating conditions forthe device are indicated in the table below. Performance specifications
do not apply where the device is operating outside these limits.
SYMBOL
PARAMETER
VDD
Supply voltage
applied at VPA, VPD
GND
PSALT
CONDITIONS
MIN
MAX
UNIT
4.5
5.25
V
Signal ground
applied at VNA, VND
0.0
0.0
V
Supply voltage
applied at PSALT
3.0
6.0
V
TA
Ambient temperature
0.0
Fc
System clock
(16MHz, Max)
Tc
System clock duty
cycle
40
7-138
NOM
70.0
°C
±0.1
%
60
%
SSI32H6520
Embedded Servo Controller
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CLOAO
Capacitive load on
digital outputs
RBIAS
Bias resistor (22.6 kn)
(continued)
CONDITIONS
MIN
NOM
-
MAX
UNIT
100
pF
±1
%
DC CHARACTERISTICS
The following electrical specifications apply to the digital input and output signals over the recommended
operating range unless othelWise noted. Positive current is defined as entering the device. Minimum and
maximum are based upon the magnitude of the number.
100
Supply current
Normal mode
Sleep mode
VDD = 5.25V
-
25
2
mA
mA
2.4
-
V
-
0.4
V
-
Voh
Output logic "1" voltage
loh = -O.4mA, VDD = 4.5V
Vol
Output logic "0" voltage
101 = 1.6mA, VDD = 4.5V
Vih
Input logic "1" voltage
VDD = 4.5V
2.0
-
V
Vii
Input logic "0" voltage
VDD=4.5V
-
0.8
V
-
1
-1
IlA
IlA
10
pF
VDD
V
lih
Input logic "1" current
Vih = 5.25V, VDD = 5.25V
iii
Input logic "0" voltage
Vii = 0.0, VDD = 5.25V
Cin
Input capacitance
FUNCTIONAL CHARACTERISTICS
EMBEDDED SERVO BURST AMPLITUDE PROCESSOR
SERIN with respect to GND
1.0
SEREF with respect to GND
1.0
-
3.0
V
1.5
Vp
SERIN input voltage
Servo gain = -2.8 dB
0.0
-
swing with respect to SEREF
Servo gain = 0 dB
0.0
-
1.0
Vp
1.0
-
MHz
Input impedance at
Servo gain = -2.8 dB
15
20
5.0
25 .
SERIN, SEREF
Servo gain = 0 dB
18
24
30
kn
Cin = 2 pF nominal
Servo gain = 3.2 dB
21
28
35
kn
Cint integration time, tiNT
Integrates to within 1% of
1.0
IJ.S
Cint discharge time, tOISCH
0.5
Ils
Burst integration timing window
separation, tNON
0.5
IJ.S
Servo burst ready, tROY
0.1
IlS
Servo burst frequency
7-139
kn
II
SSI32H6520
Embedded Servo Controller
EMBEDDED SERVO BURST AMPLITUDE PROCESSOR
(continued)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Servo channel ouput when
SERIN shorted with SEREF
SEREF = 2V
1.40
-
1.75
V
Servo channel gain step size
Guaranteed Monotonic
1.0
1.05
1.1
V/V
Servo channel slope deviation
SERIN from 0.2 Vp to 0.8 Vp
-
-
±6
0/0
VPA voltage for SYSRST
& RCRST in operation
2
-
5.25
V
On resistance at RCRST
-
-
100
Q
Rint = 63 kQ
Rint = 63 kQ
VOLTAGE REFERENCE AND VOLTAGE FAULT CIRCUIT
RCRST input threshold
-
1.6
V
-
±40
mV
2.23
2.30
V
10
-
kQ
-
100
pF
-
±15
mV
-
2.5
V
-
MHz
±10
mV
-
kQ
40
pF
± (VREF/2)
-
V
10
-
Bits
0.8
PSALT=3V
ISR voltage with respect to VREF
VREFvoltage
No load
2.16
Allowable load at VREF
PSV comparator offset
AID INPUT UNCOMMITTED OPERATIONAL AMPLIFIER
AUXINP Input Voltage
With respect to GND
Unit-gain bandwidth
1.25
2
Input-referred D.C. offset
-
Allowable load at ADCIN
5.0
DATA ACQUISITION
AID Converter
ADCIN full-scale voltage
with respect to VREF
-
Resolution
-
Acquisijion time
Conversion time
LSS voltage
1.0
IlS
2.5
VREFI
-
J1.S
V
±1.0
LSB
1024
Differential nonlinearity
Guaranteed Monotonic
7-140
-
-
SSI32H6520
Embedded Servo Controller
D/A Converter
PARAMETER
CONDITIONS
DAC full-scale voltage
with respect to DACREF
MIN
NOM
MAX
UNIT
-
±(VREF/2)
-
V
-
10
-
Bits
2.5
-
IlS
5.0
-
Ils
-
VREFI
-
V
±1.0
LSB
~-
Resolution
Digital delay
Output settling time
To within ±0.5 LSB
LSB voltage
1024
Differential nonlinearity
Guaranteed Monotonic
-
-
DACREF1, DACREF2
1.5
2.3
V
DACOUT1, DACOUT2
0.3
3.5
V
Intel Microprocessor Interface Timing
The following timing specifications are applied when an Intel bus interface is selected by pulling the BUS MODE
pin to logical HIGH and the DSPMODE pin to logical LOW. Timing measurements are made at 50% VDD with
100 pF load capacitances for all pins, unless otherwise noted .
....
SYMBOL
PARAMETER
tALPW
Pulse width, ALE HIGH
CONDITIONS
MIN
45
tAS
Muxed address valid time
to ALE fall
tAH
Muxed address hold
time after ALE fall
tDDR
Read data delay time from RD fall
NOM
MAX
UNIT
ns
7.5
-
20
-
ns
-
60
ns
ns
tDHR
Read data hold time after RD rise
0
50
ns
tRDPW
Pulse width, RD LOW
75
-
ns
tDSW
Write data setup time to WR rise
40
tDHW
Write data hold time after WR rise
10
tWRPW
Pulse width, WR LOW
'RWD
RD or WR delay time from ALE fall
ns
ns
50
-
25
-
ns
ns
tcss
CS setup time prior to ALE fall
0
-
ns
tCSH
CS hold time after RD or WR rise
0
ns
tASES
ASE setup time prior to ALE fall
45
-
tASEH
ASE hold time to ALE fall
0
-
ns
7-141
ns
II
SSI32H6520
Embedded Servo Controller
Motorola Microprocessor Interface Timing
The following timing specifications are applied when a Motorola bus interface is selected by pulling the
BUSMOOE pin to logical LOW and the OSPMOOE pin to logical LOW. Timing measurements are made at 50%
VOO with 100 pF load capacitances for all pins, unless otherwise noted.
SYMBOL
PARAMETER
tASPW
Pulse width, AS HIGH
CONDITIONS
MIN
45
tAS
Muxed address valid
time to AS fall
tAH
MAX
UNIT
ns
7.5
-
Muxed address hold
time after AS fall
20
-
ns
to OR
Read data delay time
from OS rise
-
100
ns
tOHR
Read data hold time
after OS fall
0
50
ns
tOSPWR
Pulse width, OS HIGH
duringHEAO
100
-
ns
tosw
Write data setup time
prior to OS fall
60
-
ns
tOHW
Write data hold time
after OS fall
10
-
ns
tospww
Pulse width, OS HIGH
during WRITE
100
-
ns
tASOS
OS delay time from
AS fall
25
-
ns
tASRW
R/W delay time from
AS fall during WRITE
25
-
ns
tRWH
R/W hold time after
0
-
ns
OS fall during WRITE
NOM
ns
tess
es setup time prior
to AS fall
0
-
ns
tesH
es hold time after
OS fall
0
-
ns
tASES
ASE setup time prior
to AS fall
45
-
ns
tASEH
ASE hold time
after AS fall
0
-
ns
7-142
SSI32H6520
Embedded Servo Controller
DSP Interface Timing
The following timing specifications are applied when a OSP bus interface is selected by pulling the OSPMOOE
pin to logical HIGH. Timing measurements are made at 50% VOO with 100 pF load capacitances for all pins,
unless otherwise noted.
SYMBOL
PARAMETER
tALPW
Pulse width,
XFERISEL LOW
tALHW
MAX
UNIT
75
-
ns
XFERISEL hold time
afterWR rise
0
-
ns
tOOR
Read data delay time
from REN fall
-
60
ns
tOHR
Read data hold time
after REN rise
0
50
ns
tROPW
Pulse width
REN LOW
50
-
ns
tosw
Write data setup time
prior to WR rise
40
-
ns
tOHW
Write data hold time
after WR rise
10
-
ns
tWRPW
Pulse width, WR LOW
50
CS setup time
prior to WR
25
-
ns
tCSSW
. tCSSR
CS setup time prior
toREN
25
-
ns
tCSH
CS hold time after
REN or WR rise
0
-
ns
CONDITIONS
7-143
MIN
NOM
ns
II
SSI32H6520
Embedded Servo Controller
I~DISC~ 1
INTAZ~------------------------
I..
INTEG _ _ _ _.....JI
tiNT
'NON
101..
101
L-Jr----'L-J
INT1-----'
INT2------------'
INT3------------------.....J
INT4-------------------------------------'
~
BURSTREAOY------------------------------------~~
FIGURE 1: Embedded Servo Burst Processor Timing Diagram
t ALPW
ALE
lASES
t
AO(O:7)
(REAO)
t ASEH
:{
lAS
tAH
tOOR
L
J
I'
'1
r
t ROPW
I RWO
i
less
'}
lAS
AO(O:7)
(WRITE)
L
r
tAH
tosw
J
1
tOHR
L
=r
tOHW
V
r
t Rwo
IWRPW
i
FIGURE 2: Intel Microprocessor Bus Interface Timing Diagram
7-144
SSI32H6520
Embedded Servo Controller
lASPW
AS
lASES lASEH
~
lAS
lAH
100R
10HR
L
AD (0:7)
(READ)
"\
I
"\
\
lASOS
10SPWR
OS
C
lAS
AD (0:7)
(WRITE)
r
r-rlCSH
lAH
10SW
10HW
r
/j
1ASOS
OS
\
10SPWW
-{
~
lASRW
"
FIGURE 3: Motorola Microprocessor Bus Interface Timing Diagram
t ALPW
XFER~
tOOR
AO (0:7)
(REAO)
./
tOHR
I
J4- t ALHW
t ROPW
AO(O:7)
(WRITE)
p-
~
tcSSW
~
I
./
~tALHW
tosw
r
t WRPW
FIGURE 4: TMS320XX Bus Interface Timing Diagram
7-145
tOHW
II
men
3 en
cr;
CD
I\)
1: SERVO GAIN CONTROL
&PRESCALER
0: INTERRUPT MASKISTATUS
#
WRITE
READ
#
WRITE
0
BURSTINT
BURSTRDY
0
SCALEO
1
ADCINT
ADCRDY
1
SCALEl
READ
2:ADC LSB DATA
3: ADC ADDRESS & MSB DATA
READ
#
WRITE
READ
0
'0'
0
ADCSELO
ADC2
1
'0'
1
ADCSELl
ADC3
#
WRITE
2
GAINO
2
'0'
2
ADCSEL2
ADC4
3
3
GAINl
3
'0'
3
ADC CALIB
ADC5
4
4
GAIN2
4
'0'
4
ADCG
5
5
GAIN3
5
SLEEP
'0'
5
ADC7
6
6
BSTSELO
6
STBENl
ADCO
6
ADC8
7
7
BSTSELl
7
STBEN2
ADCl
7
ADC9
2
'"
5: DACl MSB DATA
4: DACl LSB DATA
READ
#
WRITE
0
0
DAC2l
1
1
DAC3l
#
WRITE
READ
6: DAC2 LSB DATA
#
WRITE
READ
d,UI
I\)
CAO
CD
~
o
oo
-::l
....
o
CD
-:-'
;::
8:::c
CD en
7: DAC2 MSB DATA
#
WRITE
0
0
DAC22
1
1
DAC32
2
2
DAC4l
2
2
·DAC42
3
3
DAC5l
3
3
DAC52
4
4
DAC6l
4
4
DAC62
5
5
DAC7l
5
5
DAC72
6
DACOl
6
DAC8l
6
DAC02
6
DAC82
7
DACl 1
7
DAC9l
7
DAC12
7
DAC92
FIGURE 5: SSI 32H6520 Embedded Servo Processor Register Map
READ
....
SSI32H6520
Embedded Servo Controller
PACKAGE PIN DESIGNATIONS
(Top View)
".
Z
uUJ (3
a: 0
> «
'"
(3
Z
N
'" S §
x x «0 «0 8
:::J :::J
«
'" z
(3 (3
::E
Z
Z
0..
z
«
0..
0
0
« « «
> « «
0
48 47 46 45 44 43 42 41
u-
UJ
a: 0
0
'"
0
u::
UJ
a:
0
«
'"
40 39 38 37
NIC
36
NIC
RD
PSV
3
34
WR
PSALT
4
33
BUSMODE
32
ALE
VFAULT
SYSRST
6
RCRST
VNA
8
SEREF
31
INT
30
ASE
29
CS
28
VPD
SERIN
10
27
AD7
INTEG
11
26
AD6
22 23 24 25
N/C
NlC
12 13
14 15 16 17 18 19 20 21
a:
-I
« :c
en
o 0tii 0'"
en
0
0
>« «
UJ
0
0
::E
Ci '" «
0
'" «0" «"'0
«
« '"
« '"
0
0..
en
0
48-pin TQFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
SSI32H6520
48-pin TQFP
ORDER NUMBER
32H6520-CGT
PACKAGE MARK
32H6520-CGT
Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights ortrademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1989 Silicon Systems, Inc.
1293 - rev.
7-147
Notes:
7-148
SSI32H6521
Embedded Servo Controller
I;Ii'''.ii ;" pi .816'
December 1993
DESCRIPTION
FEATURES
The SSI 32H6521 Embedded Servo Controller is a
CMOS monolithic integrated circuit housed in a
44-lead SO and operates on a single +5.0 volt supply.
II provides one 1O-bit NO converter with 2.5 J.lS conversion time, and two 10-bit DtA converters with 2.5 J.lS
digital delay. In addition, it includes bus interface logic
to support DSP-based, such as TMS320C25, digital
servo applications.
Embedded Servo Burst Processor
•
Servo control for Winchester disk drives with
embedded servo sectors
•
For use in DSP-based digital servo applications
•
Pulse area detects and StH circuits for up to
four embedded servo bursts
•
Programmable gain adjustment from -2.8 dBto
3.2dB
, (continued)
BLOCK DIAGRAM
-1:>-----0;"""""'"
L -_ _ _ _ _ _<~------~D~'
~
~
~
l'
~
.-
i
i :!l !l~
II
psy
...
DSP INTERFACE
REGISTERS
l80UITSI
1293- rev.
7-149
§
~
SS132H~521
Embed(ied Servo, ControUer
FEATURES' 'l~~tinued)
Data Acquisition and DSP Bus Interface
•
Bus interface logic to support DSP~based digital servo applications
•
Eight internal registers and address decoding
•
Two 10-bit D/A converters with 2.5 ~ digital
delay
•
One 8-channel 1O-bit NO converter With 2.5 ~
conversion time
hold the integrated voltage outputs thereafter. Note that
the max ±20% tolerance of on-chip capacitors can be
calibrated out by adjusting the gain of the preceding
amplifier. Finally, the integrated voltage outputs at
BURST1, BURST2, BU13ST3 and BURST4 are provided to a 1O-bit ND converter under DSP control and
will be discharged during a time interval defined by an
external timing source through INTAZ. For proper
operatons, the time interval defined by the INTAZ must
be no less than 0.5 ~ C;lnd be applied pnlY once per
servo frame preceding the integrationpulses defined by
the INTEG.
General Fonctlons
•
Voltage fault detection
•
Low power CMOS design
FUNCTIONAL DESCRIPTION
The SSI 32H6521 can be divided into four major sections: embedded servo burst processor, voltage fault
detector/logic, data acquisition and DSP bus interface.
Limited timing logic is included to generate all the timing
signals required for the embedded servo burst processor, per Figure 1. These timing signals control the
integration, sample/hold of the pulse area detectors.
The number of embedded servo bursts supported by
this circuit are two, three or four. The BSTSELO and
BSTSEL 1 bits in the SERVO CONTROL register configure the internal timing logic to generate a servo burst
ready interrupt after the last servo burst is captured.
VOLTA.GE FAULT DETECTOR/LOGIC
EMBEDDED SERVO BURST PROCESSOR
The embedded servo burst processor extracts the head
position error information from the embedded servo
bursts using an area detection technique. The area
detection technique provides improved noise immunity
over peak detection. The embedded servo burst processor contains a differential/gain amplifier, four pulse
area detectors and required timing logic. First, a full
wave-rectified analog signal from a read data channel,
such as SSI32P4622, is provided at SERIN through an
external resistor equal to Rint and a DC reference level
forthe full wave-rectified analog signal at SEREF through
another external resistor equal to Riirt. To accommodate a wide dynamic range of servo burst amplitudes
and process variations of the integration capacitor Cint,
the differential signal between SERIN and SEREF is
scaled under DSP control. The gain of the differential
amplifier ranges from -2.8 dB to 3.2 dB in a step of 0.4
dB, as defined in the SERVO GAIN CONTROL register.
The output of the differentiaVgain arnplifier is then
provided to four pulse area detectors whose outputs are
proportional to the area above the DC reference level
during time intervals defined by an external timing
source through INTEG. Each area detector applies an
on-chip capacitor Cint equal to 10 pF to integrate the
incoming pulses during the integration interval and then
The voltage fault detector monitors the power supply
applied at PSV through an external resistor divider,
which defines the trigger leyel for power supply failure.
An open-drain output VFAUL T is pulled HIGH by an
external resistor when a power supply failure is sensed
by the PSV comparator. The user-defined trigger level
for voltage failure is applied at PSV. Another open-drain
output, opposite logic polarity as the pin VFAULT and
with an additional RC delay, is provided at SYSRST.
The amount of SYSRST delay is determined by an
external RC connected to the pin, RCRST.
DATA ACQUISITION
The NO converter is multiplexed to eight different
analog inputs by programming the AOC SELO,
ADC SEL 1, and ADC SEL2 bits in the ADC ADDRESS
register by the DSP. The eight analog inputs multiplexed to the AID converter are four embedded servo
processor outputs at BURST1, BURST2, BURST3 and
BURST4 and fou r external analog inputs through four
T/H amplifiers. These T/H amplifiers sample external
analog inputs during the time interval defined by an
external timing source applied at ADCSH. If the sampling of four external analog inputs is not necessarily
synchronized, ADCSH must be tied to HIGH. The NO
7~150
SSI32H6521
Embedded Servo Controller
conversions on these external analog inputs are always referenced to the internal voltage reference at
2.23 volts. An operational amplifier with uncommitted
inputs is provided to implement a level shifting function
for the extemal analog input applied to AUXINP. The
output of the operational amplifier is tied to ADCIN1.
The AID converter starts to acquire a new analog input
whenever the conversion is completed. A minimum of
1 I1S is required to acquire an analog input to the AID
converter. Actual conversion is started by reading the
AID MSB register or by an external timing source
applied to ADCSTR. The AID address lines ADC SELO,
ADC SEL1, and ADC SEL2 will be incremented by one
after the AID conversion is started. The· automatic
increment of the address lines is employed to eliminate
repetitive write operations by the DSP to the ADC
ADDRESS register required for converting the consecutive analog inputs.
The AID converter runs synchronously with the internal
4 MHz clock which is used for various circuits on the SSI
32H6521 and divided down from the system clock
SYSCLK by a prescaler. Therefore there would be a
maximum of 0.25 I1S of latency between a conversion
request and the actual start of the conversion. The
output is coded in 2's complement.
Do not read from the device during AID conversion.
Digital noise generated by the read cycle may be
coupled into the AID converter. Coupled noise can
prevent 10-bit accuracy.
Similarly, the D/A converters run synchronously with
the internal 2 MHz clock and the conversion is started
by writing to the corresponding D/A input register. The
output of the first D/A converter is referenced to an
external analog input, DACREF1 and the output of the
second D/A converter is referenced to an external
analog input, DACREF2. In the "normal" mode when
STBEN1 (STBEN2) bit in the ADC ADDRESS register
is reset, the D/A output will be automatically applied to
DACOUT1 (DACOUT2) during the conversion. In the
"strobe" mode, the D/A output will be applied to
DACOUT1 (DACOUT2) at the falling edge of RD for a
read to the corresponding D/A MSB DATA register.
DSP BUS INTERFACE
The SSI 32H6521 provides interface logic for a direct
connection to TMS320CXX DSP. It contains an 8-bit
data bus and 3 address lines for communicating with
eight internal registers. Bus control signals are CS, CS,
STRB and RIW. The address lines are internally latched
when the device is selected (CS active low and CS
active high). The timing requirements for the DSP bus
interface are depicted in Figure 2.
Avoid accessing this device while the servo burst capture, D/A or AID conversion is in progress. Digital bus
noise will couple into the signal path through the substrate and corrupt the signal. To maintain signal integrity, it is recommended that read operations be avoided
during servo burst capture, and sufficient time be allowed for the last AID conversion tQ be completed.
7-151
SSI·32H6521
Embedded Servo Controller
REGISTER DESCRIPTIONS
The 32H6521 contains eight 8-bit internal registers
which provide control:option select and status monitoring. The registers are addressed with a 3-bit register
address which is latched from inputs at ADRO(LSB).
ADR1. and ADR2(MSB) while the device is selected.
The registers 0.2, and 3 are read/Write memory, and the
registers 1. 4, 5, 6, and 7 are write only memory. The
registers are summarized in Table 2.
TABLE 2: Register Descriptions
ADDRESS
TYPE
0
R/W
1
W
REGISTER NAME
INTERRUPT MASK/STATUS
SERVO GAIN CONTROL & PRESCALER
2
R/W
ADC LSBDATA
3
R/W
ADC ADDRESS & MSB DATA
4
W
DAC1 LSB DATA
5
W
DAC1 MSB DATA
6
W
DAC2 LSB DATA
7
W
DAC2 MSBDATA
INTERRUPT MASK/STATUS REGISTER
Address: 0
Access: Read/Write
Reset: Bit O. 1 only
Register contents when Written:
BIT
NAME
DESCRIPTION
0
BURST INT
When set HIGH, interrupt is enabled on the embedded servo position bursts ready.
1
ADCINT
When set HIGH, interrupt is enabled on the completion of the AID conversion.
2-7
Unused.
Register contents when Read:
BIT
NAME
DESCRIPTION
0
BURSTRDY
Active high indicates that the embedded servo bursts are ready.
1
ADCRDY
Active high indicates that the AID conversion is completed.
Each interrupt event status will be reset after the DSP reads this register. The interrupt control register determines
if the event will actually cause a latched assertion of the DSP signal INT.
7-152
SSI32H6521
Embedded Servo Controller
SERVO GAIN CONTROL & PRESCALER REGISTER
Address: 1
Access: Write
Reset: 00
BIT
NAME
DESCRIPTION
0
1
SCALEO
SCALE1
SYSCLK Prescaler. To accommodate different system clocks, the prescaler selects
a proper divider to generate a fixed clock at 4 MHz per table below:
2
3
4
5
GAl NO
GAIN1
GAIN2
GAIN3
SCALE1
SCALEO
SYSCLK(MHz)
Divider
0
0
16
4
0
1
12
3
1
0
8
2
1
1
4
1
Servo Burst Amplitude Gain Select. These four bits define the gain setting for
the differential/gain amplifier per table below:
GAIN3
GAIN4
GAIN3
GAINO
0
0
0
0
-2.8
0
0
0
1
-2.4
0
0
-2.0
0
1
1
0
0
1
-1.6
0
1
0
0
-1.2
0
1
0
1
-0.8
0
1
1
1
0
-0.4
1
1
+0.0
1
1
0
0
0
+0.4
0
0
1
+0.8
1
0
1
0
+1.2
1
1
1
0
1
1
+1.6
1
0
0
+2.0
1
0
1
+2.4
1
1
1
1
0
1
+2.8
1
0
1
6
7
BSTSELO
BSTSEL1
Gain, dB
+3.2
Burst Number Select. These two bits define the number of embedded servo bursts
per sector.
# of Bursts
BSTSEL1
BSTSELO
0
0
2
0
1
3
1
0
4
7-153
II
SSI32H6521
Embedded Servo Controller
ADC LSB DATA REGISTER
Address: 2
Access: Read/Write
Reset: Bit 5, 6, 7 only
Register contents when Written:
BIT
NAME
0-4
DESCRIPTION
Unused.
5
SLEEP
Power-down Mode Enable. When set HIGH, the device is in the sleep mode where
all analog circuitry are de-biased, the clock is disabled, and the bandgap
voltage, reference voltage fault logic and processor interface stay active.
6
STBEN1
When set HIGH, the analog output of the
DACOUT1.
7
STBEN2
When set HIGH, the analog output of the DAC2 is transferred and held onto
DACOUT2.
DAC1 is transferred and held onto
Register contents when Read:
Description: After AID conversion, the least significant 2 bits of the 1O-bit digital word is stored into the register.
0-5
6,7
Unused. Logic LOW is provided to these bits.
ADCO, ADC1
The LSB 2 bits of the AID converter output in 2's complement format.
ADC ADDRESS & MSB DATA REGISTER
Address: 3
Access: Read/Write
Reset: Bits 0, 1, 2, and 3 only
Description: When Written, the least significant 3 bits of the register define the analog input to the 1O-bit AID
converter. After conversion, the most significant 8 bits of the 1O-bit digital word is stored into the register.
Register contents when Written:
0
1
2
ADC SELO
ADC SEL1
ADC SEL2
AID Converter Input Select. These 3 bits define the analog input to the AID converter
per table below:
--
BIT2
BIT1
BITO
0
0
0
ADCIN1
0
0
1
ADCIN2
0
1
0
ADCIN3
0
1
1
ADCIN4
ADCINPUT
1
0
0
BURST1
1
0
1
BURST2
1
1
0
BURST3
1
1
1
BURST4
7-154
SSI32H6521
Embedded Servo Controller
ADC ADDRESS & MSB DATA REGISTER
(continued)
BIT
NAME
DESCRIPTION
3
ADC CALIB
When set HIGH, VREF (2.23 volts) is applied to the ND converter input.
4-7
Unused.
Register contents when Read:
ADC2-9
The MSB 8 bits of the ND converter output in 2's complement. ADC9 is the sign bit.
DACl LSB DATA REGISTER
Address: 4
Access: Write
Reset: 00
0-5
6, 7
Unused.
DACO,
DAC1
The LSB 2 bits to the DAC1 in 2's complement.
DACl MSB DATA REGISTER
Address: 5
Access: Write
Reset: 00
DAC2-9
The MSB 8 bits to the DAC1 in 2's complement, DAC9 is the sign bit.
DAC2 LSB DATA REGISTER
Address: 6
Access: Write
Reset: 00
0-5
6
7
Unused.
DACO,
DAC1
The LSB 2 bits to the DAC2 in 2's complement.
DAC2 MSB DATA REGISTER
Address: 7
Access: Write
Reset: 00
DAC2-9
The MSB 8 bits to the DAC2 in 2's complement. DAC9 is the sign bit.
7-155
II
SSI32H6521
Embedded Servo Controller
PIN DESCRIPTION
POWER SUPPLIES
NAME
DESCRIPTION
VPA
Analog +5V supply.
VPD
Digital +5V supply. It must be shorted to analog +5V supply externally.
VNA
Analog ground.
VND
Digital ground. It must be shorted to analog ground externally.
PSALT
Alternate Voltage Supply to power the voltage fault logic during a voltage fault. This
power supply should be taken from the system +5V supply through a Schottky diode and
be connected to a capacitor, which is used to hold up PSALT briefly during a voltage fault.
EMBEDDED SERVO BURST PROCESSOR
NAME
TYPE
SERIN
I
Servo Burst Input - FUll-wave rectified analog signal generated from a read
data channel. This input is to extract the position information from
embedded servo bursts.
SEREF
I
Servo Burst Reference - A DC reference level for the full-wave rectified
analog signal SERIN.
INTEG
I
Pulse Area Detector Enable - This TTL compatible input, when HIGH,
activates the pulse area detectors.
INTAZ
I
Integrator Capacitor Reset - This TTL compatible input, when HIGH,
discharges the holding capacitors, Cint.
DESCRIPTION
VOLTAGE FAULT DETECTION
PSV
I
Fault Voltage Comparator Input -A voltage input for the low voltage
comparatof. This input should be connected to an external resistor divider.
The resistor divider divides its corresponding supply voltage to a proper
value which is comparable with the internal voltage reference at 2.23 volts.
VREF
0
VREF Output - A buffered voltage reference at 2.23 volts.
IBR
0
Pin for connection to an external resistor (from GND) to establish a
reference current for bias currents required for analog circuits.
VFAULT
0
Voltage Fault Indication - An open-drain output which is pulled HIGH when
a supply voltage fault is detected .
SYSRST
0
.Reset Output - An open-drain output which is pulled lOW with an amount
of delay determined by an external RC connected to the pin RCRSTwhen
a supply voltage fault is detected.
RCRST
0
Pin for connection to an external RC to implement the
delay of active LOW SYSRST.
7-156
SSI32H6521
Embedded Servo Controller
DSP BUS INTERFACE
NAME
TYPE
DO - 07
I/O
DESCRIPTION
8-Bit Bidrectional Data Bus. - These bidirectional data pins are in the high
impedance state when the device is not selected
ADRO -ADR2
I
3-bit address lines to select an internal register for I/O.
STAB
I
Data Strobe. - The data on the data bus is written to the addressed register
at the rising edge of STRB.
R/W
I
READ/WRITE Enable. - When low, the data is to be written to the
addressed register. Otherwise, the contents of the addressed register are
placed on the data bus.
CS,CS
I
2-Bit Chip Select Lines. - This device is selected when CS is low and CS
is high.
INT
0
Interrupt - An open-drain output which signals the DSP to respond to the
device. It is released when all pending interrupts have been serviced by
the DSP.
SYSCLK
I
System Clock Input - A TTL compatible input for the system clock which
is divided down with a prescaler to generate internal timing signals.
DACOUT1
0
DAC 1 Output - A 1O-bit 0/A output which converts a digital word from the
DSP into an analog signal.
DACREF1
I
DAC1 Output Reference - An external analog input to be provided to
DAC1 as a reference voltage for DACOUT1.
DACOUT2
0
DAC2 Output - A 1O-bit 0/ A output which converts a digital word from the
DSP into an analog signal.
DACREF2
I
DAC2 Output Reference - An external analog input to be provided to
DAC2 as a reference voltage for DACOUT2.
ADCIN1
ADCIN2
ADCIN3
ADCIN4
i
External NO inputs.
ADCSH
I
NO Analog Sampling Input Strobe - A TTL compatible control signal.
During active HIGH, four track/hold amplifiers prior to the NO converter
will sample external NO analog inputs.
ADCSTA
I
NO Conversion Start Strobe - A TTL compatible control signal whose
rising edge triggers the start of the NO conversion.
AUXINP
I
Level Shifter Noninverting Input - Noninverting input to the level-shifting
amplifier.
AUXINM
I
Level Shifter Inverting Input - Inverting input to the level-shifting amplifier.
DATA ACQUISITION
7-157
II
SSI32H6521
Embedded Servo Controller
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Exposure to absolute maximum rating conditions for extended periods may cause permanent damage to the
device or affect device reliability.
SYMBOL
PARAMETER
RATING
VDD
Supply voltage applied at VPA, VPD
-0.3 to 7.0V
GND
Signal ground applied at VNA, VND
O.OV
PSALT
Supply voltage applied at PSAL T
-0.3 to 7.0V
VIND
Digital input voltages
-0.3 to VDD + 0.3V
VINA
Analog input voltages
-0.3 to VDD + 0.3V
Tstg
Storage temperature
-65 to 150°C
TI
Lead temperature (10 seconds)
300°C
RECOMMENDED OPERATING CONDITIONS
The recommended operating conditions forthe device are indicated inthe table below. Performance specifications
do not apply where the device is operating outside these limits.
MAX
UNIT
4.5
5.25
V
Signal ground
applied at VNA, VND
0.0
0.0
V
PSALT
Supply voltage
applied at PSAL T
3.0
6.0
V
TA
Ambient temperature
0.0
70.0
°c
Fc
System clock
(16MHz, Max)
±0.1
%
Tc
System clock duty
cycle
40
60
%
CLOAD
Capacitive load on
digital outputs
-
50
pF
RBIAs
Bias resistor (22.6 kn)
±1
%
SYMBOL
PARAMETER
VDD
Supply voltage
applied at VPA, VPD
GND
CONDITIONS
MIN
NOM
'---
7·158
SSI32H6521
Embedded Servo Controller
DC CHARACTERISTICS
The following electrical specifications apply to the digital input and output signals over the recommended
operating range unless otherwise noted. Positive current is defined as entering the device. Minimum and
maximum are based upon the magnitude of the number.
SYMBOL
PARAMETER
CONDITIONS
IDD
Supply current
Normal mode
Sleep mode
VDD = 5.25V
MAX
UNIT
25
5
mA
mA
2.4
-
V
-
0.4
V
MIN
NOM
-
Voh
Output logic "1" voltage
loh = -O.4mA, VDD = 4.5V
Vol
Output logic "0" voltage
101 = 1.6mA, VDD = 4.5V
Vih
Input logic "1" voltage
VDD = 4.5V
2.0
-
V
Vii
Input logic "0" voltage
VDD =4.5V
-
0.8
V
1
(.IA
-
-1
(.IA
10
pF
VDD
V
3.0
V
lih
Input logic "1" current
Vih = 5.25V, VDD = 5.25V
Iii
Input logic "0" voltage
Vii = 0.0, VDD = 5.25V
Cin
Input capacitance
-
FUNCTIONAL CHARACTERISTICS
EMBEDDED SERVO BURST AMPLITUDE PROCESSOR
SERIN with respect to GND
1.0
SEREF with respect to GND
1.0
-
SERIN input voltage
Servo gain = -2.8 dB
0.0
-
1.5
Vp
swing with respect to SEREF
Servo gain = 0 dB
0.0
1.0
Vp
1.0
-
5.0
MHz
15
20
25
k.Q
30
kQ
35
k.Q
Servo burst frequency
Input impedance at
Servo gain = -2.8 dB
SERIN, SEREF
Servo gain = 0 dB
18
24
Cin = 2 pF nominal
Servo gain = 3.2 dB
21
28
Cint integration time, tiNT
Integrates to within 1% of
1.0
IlS
Cint discharge time, tDISCH
0.5
Burst integration timing window
separation, tNoN
0.1
!lS
Servo burst ready, t RDy
0.1
!lS
7-159
I
SSI32H6521
Embedded Servo Controller
EMBEDDED SERVO BURST AMPLITUDE PROCESSOR
(continued)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Servo channel ouput when
SERIN shorted with SEREF
SEREF = 2V
Rint = 63 kU
1.45
-
1.75
V
Servo channel gain step size
Guaranteed Monotonic
1.0
1.05
1.1
VN
Servo channel slope deviation
SERIN from 0.2 V p to 0.8 V p
-
-
±10
mV
100
mV
Rint = 63 kU
Channel mismatch
Note: Servo channel Includes the servo burst capture circUit, ND and D/A converters.
VOLTAGE REFERENCE AND VOLTAGE FAULT CIRCUIT
VPA voltage for SYSRST
& RCRST in operation
-
On resistance at RCRST
RCRST input threshold
PSALT=3V
2
-
5.25
V
-
-
100
U
0.8
1.6
V
±100
mV
2.16
2.23
2.30
V
-
kU
IBR voltage with respect to VREF
VREF voltage
No load
Allowable load at VREF
10
PSV comparator offset
100
pF
-
±15
mV
-
3.25
V
AID INPUT UNCOMMITIED OPERATIONAL AMPLIFIER
AUXINP Input Voltage
With respect to GND
1.25
Unit-gain bandwidth
1
-
-
MHz
Input-referred D.C. offset
-
-
±10
mV
Allowable load at ADCIN
5.0
-
-
kU
40
pF
-
V
-
Bits
DATA ACQUISITION
AID Converter
ADCIN full-scale voltage
with respect to VREF
-
Resolution
-
10
Acquisition time
1.0
Conversion time
-
2.5
LSB voltage
-
VREFI
(VREF/2)
J1S
J1S
-
V
±1.0
LSB
1024
Differential nonlinearity
Guaranteed Monotonic
7-160
-
-
SSI32H6521
Embedded Servo Controller
D/A Converter
MIN
NOM
MAX
UNIT
DAC full-scale voltage
with respect to DACREF
-
±(VREF/2)
-
V
Resolution
-
10
-
Bits
Digital delay
-
2.5
-
JlS
-
5.0
-
JlS
VREFI
1024
-
V
-
PARAMETER
Output settling time
CONDITIONS
--
To within ±1 LSB
-
LSB voltage
-
±1.0
LSB
DACREF1, DACREF2
1.5
2.3
V
DACOUT1, DACOUT2
0.3
3.5
V
Differential nonlinearity
Guaranteed Monotonic
DSP Interface Timing
The following timing specifications are applied for a OSP bus interface. Timing measurements are made at 50%
VOO with 50 pF load capacitances for data pins, unless otherwise noted.
SYMBOL
PARAMETER
MAX
UNIT
tSTRBS
ADRO .. 2/CS/CS/R/W
setup time prior to
STRBfall
10
-
ns
tOOR
Read data delay time
from STRB fall
-
50
ns
tOHR
Read data hold time
after STRB rise
0
20
ns
tDSW
Write data setup time
prior to STRB rise
20
-
ns
tOHW
Write data hold time
after STRB rise
10
-
ns
CONDITIONS
7-161
MIN
NOM
I
SSI32H6521
Embedded Servo Controller
I~DISC~I
INTAZ~'-------------------------
I..
tINT
INTEG _ _ _ _ _...JI
t NON
·1..
·1
~r----,L-.-J
INT1-------'
INT2-------------'
INT3------------------...l
INT4---------------------------'
I~
BURSTREADY-------------------------------...lr-FIGURE 1: Embedded Servo Burst Processor Timing Diagram
=x
I
ADRO .. 2
CS,CS
X
WRITE
I
I
I
-
I
I
I
R1W~
I
I
STRB
-:
I
I
I
I
/
tSTRBS
I
I
I
I
I
t DSW :tDHW
:tDDR
:tDHR
Ilt .... :
:-.;
!++i
:.
DO ..7
X
READ
'(
:;
I
I
I
'(
:;
FIGURE 2: TMS320CXX DSP Bus Interface Timing Diagram
7-162
><==
1: SERVO GAIN CONTROL
&PRESCALER
0: INTERRUPT MASKISTATUS
#
WRITE
READ
#
WRITE
0
BURSTINT
BURSTRDY
0
SCALEO
0
1
ADCINT
ADCRDY
1
SCALEl
READ
#
3: ADC ADDRESS & MSB DATA
READ
#
WRITE
READ
'0'
0
ADCSELO
ADC2
1
'0'
1
ADCSEL1
ADC3
WRITE
2
2
GAINO
2
'0'
2
ADCSEL2
ADC4
3
3
GAINl
3
'0'
3
ADC CALIB
ADC5
4
4
GAIN2
4
'0'
4
ADC6
5
5
GAIN3
5
SLEEP
'0'
5
ADC7
6
6
BSTSELO
6
STBEN1
ADCO
6
ADC6
7
7
BSTSEL1
7
STBEN2
ADCl
7
ADC9
~
5: DACl MSB DATA
4: DACl LSB DATA
(])
'"
2: ADC LSB DATA
#
READ
7: DAC2 MSB DATA
6: DAC2 LSB DATA
#
WRITE
0
0
DAC22
DAC3l
1
1
DAC32
2
DAC42
#
WRITE
0
0
DAC2l
1
1
WRITE
READ
#
WRITE
READ
2
2
DAC4l
2
3
3
DAC5l
3
3
DAC52
4
4
DAC6l
4
4
DAC62
5
DAC7l
5
6
DACOl
6
DAcal
6
7
DACll
7
DAC9l
7
5
-----------
5
DAC72
DAC02
6
DAC82
DAC12
7
DAC92
----
FIGURE 5: 551 32H6520 Embedded 5ervo Processor Register Map
READ
m
3
C"
C'D
Co
Co
C'D
Co
en
C'D
""l
< en
°en
0ow
::sN
:;":I:
OOl
=01
C'D N
•
""l
.....
SSI32H6521
Embedded Servo Controller
PACKAGE PIN DESIGNATIONS
(Top View)
VPA
AUXINM
AOCIN1
AUXINP
AOCIN2
OACREF2
AOCIN3
OACOUT2
AOCIN4
OACOUT1
VREF
OACREF1
STRB
IBR
psv
RfN
PSALT
AOR2
VFAULT
AOR1
SYSRST
INT
l'lCRST
AORO
CS
VNA
SEREF
VPO
SERIN
CAUTION: Use handling procedures necessary
for a static sensitive component.
07
INTEG
06
INTAZ
05
ADCSH
04
ADCSTR
03
SYSCLK
D2
VNO
01
CS
DO
44-lead SOM
ORDERING INFORMATION
PART DESCRIPTION
SSI32H6521
44-pinSOM
ORDER NUMBER
PACKAGE MARK
32H6521-CM
32H6521-CM
Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights ortrademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1993 Silicon Systems, Inc.
7-164
1293 - rev.
SSt 32H681 OA/681 08
5V Servo &
Motor Speed Drivers
I; t§" 11" 'E' fi .m6'
December 1993
FEATURES
DESCRIPTION
The 551 32H6810N6810B 5ervo/MSC Drivers. a
CMOS monolithic integrated circuit housed in a 48lead TQFP package. operates from a single 5V supply.
It provides a fully integrated servo driver and a spindle
motor commutator with internal power FETs. The
servo driver is intended for use in disk drive head
positioning systems employing linear or rotary voice
coil motors. The commutator in conjunction with a
microprocessor (1l.P) or digital signal processor (DSP).
provides a complete spindle motor speed control
system. The device is ideal for use in 5V small-form
disk drive applications.
48-lead TOPF package
Internal1.0A Servo/MSC drivers
NMOS output stage, no blocking diodes
required
No deadband, low distortion, class·B output
for Servo driver
Gain select switch for a wide dynamic range of
servo inputs
Optimal commutation delay without external
components or Hall sensors
Reduced dv/dt on commutation· no snubber
networks required
Unipolar and Bipolar modes for MSC driver
Multiple Brake/Retract modes
Internal precision voltage reference
Power fault detection with built· in retract
circuitry
Thermal overload protection
Low power CMOS design with Sleep mode
PIN DIAGRAM
48 47 48 45 44 43 42 41
40 39 38
COMMU
GAIN
RRAMP
INCOM
VSMP2
VVMN1
VM1
VSMN2
VSMP1
VVMN2
VSMN1
SE2
14 15 16 17 18 19 20 21
u.
~
>
a: ::; z
ffi a: '!!:
ffi (/)
VND
22 23
z
'>
CAUTION: Use handling procedures necessary
48-Lead TOFP
1293 - rev.
7-165
for a static sensitive component
SSI 32H681 OA/681 08
5V Servo &
Motor Speed Drivers
<
SDUT
VREF
~
SEl
X4
SE2
~
VRETR
SOUTAMP
VBYPl
-l
ERRM
SWON
SWIN
ERR
d..
=k,RETR
,t-"
6J
1/
~
~
~12
~
-+
1
>
VPOWERAMP
-
VBG
I
I
IBR
-
VBGAP
GENER
t
BIAS
I
r--
VBYP2
VBEMF
VVMP
l,RETR
VMl
-<>
0
~
+RETR
VM2
VVMN(2)
I ="HEf~
=
llTSO
SE1NSE
DISABLE
THTEST
m:lIST
VCHK
FAULT
HANDLER
SUEEP
~
~
~
._
~~C»-l~
=
RETR
PFLOAT. SFLOAT
RESET
DISABLE
OTSD
=
2
VSMP(2)
SFLOAT--.
BRAKE--.
SLEE~
GAIN
~
RRAMP
SPM
OUTPUT
DRIVERS
A
UN!
VIN
2
~
RESET _____
~
ADVANCE
SYSCLK
~~
TIME
BASE
INCOM
~~
ADAPTIVE
DELAY
VPA
COMMUTATOR
I
VNA
VPD VND
COMMU
BLOCK DIAGRAM
7-166
VSMN(2)
r-VBGAP SLEEP BRAKE RETRACT
CONDITION
ANALOG POSITIONER
A,B,C
0
X
1
X
Power Fault
On
Retract
Float
0
X
0
X
Power Fault
On
Retract
LowZ
toGND
1
1
1
1
Sleep
Off
Float
Float
1
1
0
1
Sleep/Brake
Off
Float
LowZ
toGND
1
1
0
0
Sleep/Retract
Off
Retract
LowZ
toGND
1
1
1
0
Sleep/Retract
Off
Retract
Float
1
0
0
X
Brake/Retract
On
Retract
LowZ
toGND
1
0
1
0
Retract
(Spindle Run)
On
Retract
Active
1
0
1
1
Run
On
Active
Active
X
X
X
X
Thermal
Shutdown
On
Float
Float
TABLE 2: Operating Mode Control
NOTES:
1. BRAKE internally linked to force retract.
2. Voltage fault circuit is never turned off.
3. Counter is reset when sleep input is high.
The circuit also provides an over temperature detection function. If the die temperature exceeds
135°C (approximately), OTSD is asserted low and all output drivers are turned off. The drivers will
become operative after the temperature is reduced and ADVANCE is asserted high.
7-169
I
SSI32H681 OA/681 08
5V Servo &
Motor Speed Drivers
PIN DESCRIPTION
POWER SUPPLIES
NAME
TYPE
DESCRIPTION
VPA
I
Supply: Analog positive power supply.
VNA
I
Ground: Analog ground.
VPD
I
Supply: Digital positive power supply.
VND
I
Ground: Digital ground. VND is circuitry ground and also the low side input to
the current SENSE amplifier and thus care should be taken to see that VND
and the low side of the external Rsense resistor are at the same potential.
VVMP
I
Supply: Positve supply for voice coil motor.
VVMN1, VVMN2
I
Supply: Negative supply for voice coil motor.
POSITIONER
SWON
I
Turns on the switch between ERRM and SWIN.
SWIN
I
Analog switch, the other side of the switch is connected to ERRM.
SOUT
0
The current sense amplifier output. SOUT is referenced to VREF.
ERR'
0
The error amplifier output. ERR is used to provide compensation to the
transconductance loop. ERR is referenced to VBGAP.
ERRM
I
The error amplifier negative input.
VREF
I
The reference voltage for the error amplifier and the current sense amplifier.
VRETRACT
I
The retract Voltage. If left open, the retract voltage will be the default setting.
This value can be over-ridden by biasing VRETRACT externally.
VM1
0
Connection for voice coil motor and sense resistor.
VM2
0
Connection for the other side of voice coil motor.
SEt, SE2
I
Sense voltage on the sense resistor.
MOTOR SPEED CONTROL
SYSCLK
I
COMMU
0
0
REVCLK
UNIPOLAR
I
System clock (input) pin. SYSCLK is2 MHz nominal and is used to generate
internal timing signals.
Commutation count pin. COMMU is the LSB of the commutation counter.
REVCLK is COMMU divided by six.
Unipolar mode (inverse) select pin. This pin will turn all upper drivers off when
low. Pulled high internally to provide the default bipolar mode.
7-170
SSI 32H681 OA/681 OB
5V Servo &
Motor Speed Drivers
MOTOR SPEED CONTROL (continued)
NAME
TYPE
DESCRIPTION
ADVANCE
I
Advance pin. ADVANCE is controlled by microprocessor during start mode to
increment the commutation counter. The rising edge of ADVANCE will
increment the counter. ADVANCE held high will inhibit internal incrementing
of the counter, ADVANCE held low permits the normal operation of commutation from back-emf events.
INCOM
I
Commutation delay control. Adaptive commutation delay may be adjusted
from its nominal value of 3/7 of the commutation interval by sinking or sourcing
current from this pin. It is recommended that INCOM pin be pulled high during
start-up.
VIN
I
Control Voltage input pin. The internal driver transistors and internal predriver
circuits form a transconductance amplifier which will set motor current in
relation to VIN. In conjunction with Rsense at VSMN input and the gain of the
Sense amplifier, transconductance (Gm) will be Gm = Im/VIN =
11 (Rsense • 5).
A,B,C
0
Motor Drive Outputs. These pins provide drive to the motor coils.
CT
I
Back EMF input from motor coil center tap. Input connected to the center tap
for sensing generated back emf voltages. It is also derived internally from A,
B, C through a resistor network (y-connection).The circuit uses the back-emf
voltages to determine rotor position and effect commutation.
RRAMP
I
Lower driver turn-off dv/dt setting resistor. External resistor from VPD to this
pin sets the dv/dt slope of the motor coil voltage when the lower drivers are
commutating to the off state. The dv/dt is given approximately by the relationship dv/dl (volts/second) = 1.5'1 OE1 O/Rramp. Typicalvalue: RRAMP = 200K.
GAIN
I
Sense amplifier gain control pin. In normal operation, this pin is tied to high to
gain
set sense amplifier gain = 5. In low motor current operation, amplifier
= 10 can be set by tying this input to low.
VSMP1,VSMP2
I
Supply: Positive supply for spindle motor.
VSMN1, VSMN2
I
Supply: Negative for spindle motor. Current monitoring sense amplifier (high
side) input pin and motor current returns to ground. All pins must be
connected with low resistance circuit board traces. The lower driver
transistor current (hence motor current) comes out of these pins to Rsense
resistor to monitor motor current. During normal (at speed) operation, the
circuit will control the voltage across this resistor (multiplied by the gain of 5 in
the sense amplifier) to match VIN.
VVMP. VVMN, VSMP and VSMN conductors must be sized in accordance
with anticipated motor current. The analog and digital supplies should
be bypassed separately. VPA and VPD should be shorted externally,
VNA and VND should be shorted externally.
7-171
I
SSI 32H681 OA/681 08
5V Servo &
Motor Speed Drivers
PIN DESCRIPTION
MISCELLANEOUS
NAME
TYPE
VBYP1
I
DESCRIPTION
The bypassed power supply. An external voltage for BRAKE and RETRACT
circuitry. An external capacitor is attached to this pin and an internal circuit will
charge this pin to VCC. The charge on this capacitor is used by the brake and
retract function when VCC is removed (power-off). The capacitor must hold
sufficient charge during the period when VCC is lost while retract is taking
place (20 to 50 ms) so it will have enough voltage to drive the outputs during
braking. Very IiItle current is used during power-off braking so that C can be
chosen from the retract conditions:
C
~
Tretract • Ivbyp (float mode) / .5 volt
or approximately:
C ~ 40E-6' Tretract
This pin is normally a diode drop below VPA, rising by VBEMF during retract.
VBYP2
I
The other side ofthe bypass capacitor connection. This pin is normally at VNA,
rising to VBEMF during retract.
VBEMF
I
Rectified spindle back emf voltage. This voltage drives the internal retract
FET.
SLEEP
I
Sleep pin. When asserted high, internal counters and registers are cleared.
Refer to Table 2. Also forces an internal voltage fault which causes a head
retract. Disablesal! output drivers, powers down all other circuitry except the
over-temperature and voltage fault circuitry;
RETRACT
I
Retract (inverse) pin. When asserted low, forces a retract. Refer to Table 2.
BRAKE
I
Brake (inverse) pin. BRAKE is used to provide a delay between the initiation
of fault-induced head retract and motor braking. A capacitor to ground and a
resistor to SYSRST are selected such that 1 .2 • R· C is equal to the maximum
time required for retract. Refer to Table 2.
OTSD
0
Over-Temperature Sense Detect. Excessive die temperature will bring this
open drain output low. Spindle motor and positioner drivers are disabled
whenever OTSD is asserted.
VCHK
I
Comparator input for power supply monitoring.
VBGAP
0
An internal voltage reference for use with the power supply monitor comparator.
IBR
0
A resistor is tied from this pinto ground to establish the bias current for internal
circuitry.
RCRST
110
This pin serves the dual purpose of providing power on reset and stretching
short VFAULT pulses to a width suitable for the host microcontroller. An
external RC network sets the minimum width of any SYSRST pulse.
SYSRST
0
When low, this open drain output indicates that an internal voltage fault has
occured or that RCRST has been pulled low.
7-172
SSI 32H6810A/6810B
5V Servo &
Motor Speed Drivers
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may permanently damage the device.
PARAMETER
RATING
Supply Voltage
VPA, VPD,
VVMP, VSMP (1, 2)
-0.3 to 7V
-0.3 to 7V
Output Current
Imax (in or out of
A, B, C, VM1, VM2)
-1.0to 1 Amp
Analog I/O
Voltage on pins
VIN, RRAMP,
CT, A, B, C, VBEMF,
VBYP1, VBYP2
VM1, VM2, SE1, SE2
All other pins
Storage Temperature
Tslg
-0.3 to VPD + 0.3V
-0.3 to 12V
-0.3 to 7V
-0.3 to VPD + O.3V
-65 to 150°C
Tlead
oto 300°C
Supply Voltage
VPA,VPD
VVMP, VSMP
4.5 to 5.5V
4.5 to 5.5V
Supply Current
I (VPA + VPD)
20mA
I (VPA + VPD +
VVMP + VSMP)
Sleep mode
20 mA
Lead Temperature
(10 sec duration)
OPERATING CONDITIONS
IVVMP
0.4A
IVSMP
0.5 A
I
--
VBEMF
1 to 10V
VREF
0.5 to VPA-2V
VIN
Vin, VSMN1, VSMN2 *
Normal operation
oto 2.5V
oto 0.5V
RF
10 kil
RC
10 kil
RBIAS
112 to 114 kil
Ambient Temperature
Ta
Capacitive Load Digital I/O
CI
oto 70°C
oto 100 pF
• Transconductance gain from VIN to motor current (steady-state) will be given by: G
1/( Rsense • 5)
7-173
= ImotorlVlN =
SSI 32H681 OA/681 DB
5V Servo &
Motor Speed Drivers
OPERATING CONDITIONS (continued)
PARAMETER
RATING
Analog Outputs
CI
oto SO pF
Resistive Load Analog Outputs
RI
10 kQ
Power Dissipation
Pd
SOOrnW
PARAMETRIC REQUIREMENTS
Digital Input/Output
PARAMETER
CONDITIONS
MIN
Fclk, SYSCLK
1.S
Twh, Twl, SYSCLK width high or low
40
Input Leakage (UNIPOLAR)
-SO
NOM
MAX
UNIT
2.S
MHz
ns
Input Leakage (all other pins)
10
fJA
fJA
Vii (BRAKE)
1.2
V
0.8
V
Vih (BRAKE)
10
2
Vii (all other digital inputs)
Vih (all other digital inputs)
Output Sink current
V
2
V
Vo
= O.4V
1.6
rnA
Vo
= 0.4V
4
rnA
= -100 fJA
lout = 2.0 rnA
2.4
V
os Yin < 2.SV
-1
RCRST,OTSD
SYSRST
Digital Output COMMU, REVCLK
Voh
lout
I
Vol
0.4
V
+1
fJA
VIN
Input Current
Outputs A, S, C
Total voltage drop
across power FETs
32H6810A
Irnotor
=500 rnA, VPD =4.SV
7-174
SSI 32H681 OA/681 08
5V Servo &
Motor Speed Drivers
CT, And A, B, C, When Not Driving
PARAMETER
CONDITIONS
Rin
-0.3V::;; Yin < 7V
MIN
NOM
5K
9K
Cin@CT
Cin@A,B,C
MAX
UNIT
20
pF
200
pF
!lA
!lA
!lA
Q
VBYP1
IVBYP1 (run)
VDD = 4.5V
100
IVBYP1 (retract)
VDD = 0.5V, VBYP1 = 3V
20
IVBYP1 (brake)
VDD::;; 0.5V, VBYP1 = 3V
10
BEMF
IBEMF
VBEMF = 4V
IBEMF (retract)
I (VM1) = I (VM2) = 0,
I (VBYP2) = 0
300
20
!lA
!lA
SOUT
Gain
Input Offset
SOUT = VREF
Output Swing
RL = 10 kQ to VREF
3.9
4.1
-3
3
mV
0.15
VP-1
V
-15
15
mV
1.55
VP -1.25
V
VN
--
ERR
ERRM Input Offset
ERR = ERRM
ERR Output Swing
POSITIONER
(VM1 - VM2) / (ERR - VBGAP)
11
13
V
Crossover Time
Imotor = 10 mA, PP @ 1 kHz,
RL= 16Q, RSENSE = 0.5Q
10
25
J.1S
Output Distortion
Imotor = 100 mA, PP @ 100 Hz
RL= 16Q, RSENSE = 0.5Q
2
%THD
2.13
2.37
V
-15
15
mV
VBGAP
Bandgap Voltage
lout < ±0.2 mA
VCHK
Offset
7-175
II
SSI 32H681 OA/681 0.8
5V Servo &
Motor Speed. DriverS
OUTPUT VM1 , VM2
PARAMETER
Total voltage drop
across power FETs
CONDITIONS
MIN
VRETRACT = 0.1 V
VBEMF;::: 1V
-100
NOM
1= 400 mA
MAX
1
UNIT
V
0
mV
SWIN
On Resistance
RETRACT
VRETRACT
Offset
RL = 160
VRETRACT = 0.5V
VBEMF= 1V
VBYP1 = 4.5V
VM1 = VM2
VRETRACT = 0.5V
VBEMF = 1.5V
VBYP1 = 4.5V
VM1 = VM2
Short Circuit Current
60
mA
100
mA
OTSO (Thermal Shutdown)
Die temperature
125
10
T. sec
0.5
81-----I-;..----+---"<+---1----+--I
1
2
10
~
(steady state)
RJa, deg elw
8.5
12.5
17.8
52.5
87.5
2F=====~,~~~1~0~Soc~~---r~~~~---t--~
: Steady sate
Junction temperature
at 125°C
is assumed
ot==IC:l~~j=~~8to=r==lJoo;~~~.J..J
Ambient Temperature, deg C
FIGURE 1: Power Dissipation Derating
7-176
SSI 32H681 OA/681 08
5V Servo &
Motor Speed Drivers
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
II I~ I~ I~
Cl.
W
w
...J
(/)
Z
~
~
.....
(/)
w
:z:
.....
(.)
:z:
> .....
(/)
48 47 46 45 44 43 42 41
w
I~
<..l
Z
~
...J
« (.)
(/)
aCl. >
a >> « (/)
40 39 38 37
VBYP2
36
COMMU
VBYP1
35
GAIN
VPA
34
RRAMP
VRETRACT
33
INCOM
VBEMF
32
VSMP2
VVMN1
31
C
VM1
30
VSMN2
VVMP
29
B
VM2
28
VSMP1
VVMN2
27
A
VNA
26
VSMN1
SE2
14 15 16 17 18 19 20 21
W
(/)
.....
0
(/)
;:)
LL-
w
rr:
>
rr:
rr:
w
::;;
z
rr:
rr:
rr: ~
(/)
~
w
Cl.
rr:
00
0
« ::s
~
>
22 23 24 25
.....
<..l
Il.
Z
~
...J
(.)
>
W
rr:
I
VND
z
:>
;:)
48-Lead TQFP
ORDERING INFORMATION
ORDER NO.
PART DESCRIPTION
PACKAGE MARK
SSI 32H681 OA
48-Lead TOFP
32H6810A-CGT
32H6810A-CGT
SSI32H6810B
48-Lead TOFP
32H6810B-CGT
32H6810B-CGT
Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations
and are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems.
Silicon Systems reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the data sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1293 - rev.
7-177
©1993 Silicon Systems, Inc.
Notes:
7-178
SSI 32H6811/6811 8
Servo Motor Speed
5V Driver/DACs
Ii' ,iiiliil Mr'l
'iit'lII
December 1993
DESCRIPTION
FEATURES
The SSI 32H6811f6811B Servo and MSC Drivers, a
CMOS monolithic integrated circuit housed in a 64lead TQFP package, operates from a single 5V supply.
It provides a fully integrated servo driver and a spindle
motor commutator with internal power FETs. The
servo driver is intended for use in disk drive head
positioning systems employing linear or rotary voice
coil motors. The commutator in conjunction with a
microprocessor (IlP) or digital signal processor (DSP),
provides a complete spindle motor speed control
system. It also includes two 1O-bit DfA converters, with
a serial interface to commonly used IlP or DSP, for
commanding the servo positioner and the spindle
motor respectively. The device is ideal for use in 5V
small-form disk driver applications.
•
Internal 1.0A servo driver with no deadband,
class-B output
•
•
Thermal overload protection
•
•
Power fault detection with built-in retract
circuitry
1O-bit VCM Of A convener with 41ls digital delay
Gain select switch for a wide dynamic range of
servo inputs
•
Internal precision voltage reference
•
Programmable commutation delay for optimal
motor efficiency
•
10-bit MSC Of A convener with 41ls digital delay
•
Internal1.0A spindle driver
•
Switch-mode current limiting for spindle motor
stan-up
•
Serial interface compatible with 80C196 and
68HC16
•
Low power CMOS design with Sloop mode
•
64-lead TQPF package
PIN DIAGRAM
DDDDDDDDDDDD
NIC
COMMU
0TSlJ
47
ADVANCE
VBGAP
46
\lIN
THTEST
45
RRAMP
VPA
44
cr
VRETR
43
VSMP2
V8EMF
42
WMN1
41
VMl
40
WMP
10
39
VM2
11
38
VVMN2
12
37
NIC
13
3Ei
N/e
NIC
14
35
NIC
NIC
15
NIC
16 17 18 19 20 21
22 23 24 25 26 27 28 29 30 31
64-LEAD TQFP
1293 - rev.
VSMN2
7-179
VSMP1
VSMN1
34
NIC
32 33
Nle
CAUTION: Use handling procedures necessary
for a static sensitive component.
SSI 32H6811/6811 B
Servo Motor Speed
5V DriverlDACs
+
SOUT
-
-
SE'
+
SE2
x.
VRETR
SOUT AMP
VBYPl
PDAC
VBYP2
VBEMF
VVMP
WMN1,2
VM'
ERREF
fARM
ERR AMP
VM2
1
POWER AMP
SWIN
ERR
0fSD
VBG
2.2SV
THTEST
=
IBR
RETR
$YSAST
VCHK
¢-------1
SOAC
¢-----<
VIN
r - - - - - - - 7 ' L - - o VSMP1, 2
¢---------------+I
I--------<~ RRAMP
SCATA
seLK
SDEN
ADVANCE ¢-------~
'----+-1-7Y--Q
YSMN1,2
SYSClK
lNCOM
BRAKE ¢-------~
COM/REV ~------j
VPA
VNA
VPO
VND
FIGURE 1: SSI 32H681116811 B Functional Block Diagram
7-180
SSI32H6811/68118
Servo Motor Speed
5V Driver/DACs
assumed that no current is available for VVMP. Thus
power for this mode comes from VBEMF, the rectified
spindle back emf voltage, and from VBYP1, a voltage
generated from an external storage capacitor CBYP.
The retract amplifier is powered by VBYP1. It senses
the voltage at VRETR and, through a power NMOS
source follower, raises VM 1 to VRETR. The drain olthe
source follower is VBEMF.
FUNCTIONAL DESCRIPTION
As shown in Figure 1, the SSI32H6811 can be divided
into four major sections: Servo positioner, Spindle
motor commutator/driver, Control circuitry and Serial
interface port.
Servo Positioner
The servo positioner is a power transconductance
amplifier for use in driving a voice coil servo motor
(VCM). It has two Primary modes of operation, normal
(or linear) and retract. The Retract mode is activated by
a power supply failure orwhen RETR is asserted low
while BRAKE being high. Otherwise the device operates in Linear mode. The servo positioner consists of
SOUTamplifier, ERR amplifier, retract amplifier, power
amplifier and 10-bit VCM O/A converter.
VCM D/A Converter
Switched-capacitor circuit technique is employed to
implement the VCM O/A converter with two non-overlapped clock phases, one phase for auto-zeroing and
another one for evaluation. These two phases run
synchronously with an internal 250 kHz clock, which is
derived directly from the system clock at SYSCLK.
The request of the VCM O/A converter is .initiated by
writing to the VCM O/A register (00) through the serial
interface port. The input data word must be coded in
two's complement form. Note that there would be a
maximum of 2 lJSec of latency between a conversion
request and the actual start of conversion. The conversion delay from the actual start of conversion to when
the analog output begins to slew to a new value is
2 lJSec. Therefore a maximum of 4IJSec is required for
a conversion in addition to the time needed for completion of a serial data transfer, which is equalto 16/SCLK.
SOUT Amplifier
The SOUT amplifier generates a voltage at SOUT,
proportional to positioner current, by sensing the voltage across Rs, ampl.ifying and referencing to ERREF.
Since the Common mode voltage on Rs can range over
the full power supply, while the differential voltage is in
the order of millivolts, the SOUT amplifier is realized
with a high input Common mode rejection and low input
offset.
The VCM O/A converter provided at POAC is referenced to ERREF, which also serves as a reference
voltage for the error amplifier and the current sense
amplifier.
ERR Amplifier
The ERR amplifier is a high gain op amp. Oue to the
fixed gain of the power amp, ERR is proportional to the
VCM voltage. The negative input of this amplifier is the
system summing junction for the currents which are
proportional to the desired VCM current, the measured
VCM current, and the VCM voltage.
Spindle Motor Commutator/Driver
The spindle motor commutator in conjunction with
external components provides the motor driving capability for starting, accelerating and rotational speed
regulation forbrushless DC motors withoutthe need for
Hall sensors. The speed regulation control loop is
completed with a IlP or OSP external to this device.
Power Amplifier
The power amplifier is a fixed gain voltage amplifier
with differential inputs and outputs. Its input is the
differential voltage between ERR and VBG. Its output
drives the VCM directly through an internal NMOS
bridge. An internal charge pump generates gate voltages higher than VVMP so the upper NMOS devices
can drive VM1 and VM2 up to VVMP.
Retract Amplifier
When a voltage fault is sensed, or when RETR is
asserted low while BRAKE being high, the servo
positioner enters into Retract mode. In this mode, it is
Commutator
Motor armature position is determined by monitoring
the coil voltage of thewindingthat is not presently being
driven by the drivers. The back EMF from the coil, in
conjunction with the state of the output drivers, indicates the armature position. The back EMF is compared with a reference at CT and initiates commutation
is compared with a reference at CT and initiates commutation "events"when the appropriate comparison is
7-181
II
SSI 32H6811/6811 B
Servo Motor Speed
5V Driver/DACs
made. CommutatiOn is the sequential switching of
drive current to the motor windings. Because the back
comparison should occur, it is preferred to delay commutation by a predetermined time after the comparison. There are two modes of commutation delay,
namely adaptive or one-shot, which can be selected
via the M, N bits in the mode register (10) per table 1.
In Adaptive mode (defauH), the commutation delay is
provided by a circuit which measures the interval
between comparison events and delays commutation
by a time equal to 3/7 of the prior measured interval.
The circuit is adaptive and will provide the optimum
delay for a wide range of motor speeds (-80% to 50%
of the nominal value). Since tlW commutation of motor
coils typically causes transients, thecommutation de~
lay circuit also provides a noise blanking function which
prevents the circuit from responding back EMF comparison events for a period of time equal to the maximum of 5/7 of the interval between events and 64J.lS
after the comparison event. INCOM pin can be selected as a test pin if it is high impedance, otherwise it
should be selected as "IN" for the Adaptive mode to
work properly.
In one-shot mode, an input voltage at.INCOM pin will
provide a fixed delay and noise blank. Forstart-.up,
INCOM = VDD/2 is recommended;delay will be about
500 microseconds and noise blank about 850 microseconds. The commutation table is described in ,Table 2 ..
Motor speed control may be accomplished bymeasuring
the period of the output sign\il atCOM/REV. COM/R EV
may be defined as either COMMU, the LSB. of the
commutation counter, or REVCLK, the revolution clock
of the motor, selected via the bit COM/REV in the mode
register (10).
Transconductance Amplifier
Input pin VIN is the non-inverting input of a
transconductance amplifier which uses the lower driver
transistor, that is presently active per the commutation
state, as the power driver element. An external resistor
is used to sense the current flowing through the drive
transistor source (and hence the motor coil current).
The voltage across the sense resistor is amplified by a
gain stage (Av = 5, 10,20 or 30 selected by the GAIN
bits in the MODE register) and fed to the inverting input
of the transconductance output stage.
The 1O-bit MSC D/A converter, referenced to VBGl2, is
provided. at SDAC for converting the commanding
signal in digital format into an analog voHage. Its
operation is similarto the VCM D/A converter, but is
initiated by writing tothe MSCD/Aregister (01) in two's
complement form.
Power Amplifier
The output pins A, Band C are intended to drive motor
coils directly. The output drivers operate to reduce
switching noise transients bY limiting dv/dt during
commutation. Each .outpulcohsists oJ two N-channel
MOSFET drivers,one for pullup to VSMPl or VSMP2
andoneforpulidowntoVSMNl orVSMN2. Thepullup
FETfunctions as a switch (1.50 maximum) with voHage
rise and fall times of about 25 microseconds. The
pulldown FETis a part ofthetransconduct\ioce amplifier
which converts the voHage VIN into motor current
(Imotor = VIN/(Rsense • Av), where Av is either 5, 10,
200r 30). When the pulldown output is commutating to
the off state, dv/dt on the respective pin is controlled
such that dvldt is approximately 151RRAMP volts per
microseconds, where RRAMP is measured in kohms.
TA.BLE 1: Modes of Commutation Delay
.
..
MODE REGISTER (10)
M
N
SWITCH
MO.DE
DELAY
MODE
INCOM
PIN
0
0
NO
Adaptive
Test (default)
0
1,2
NO
Adaptive
In
0
3
NO
Adaptive
In
>0
X
YES
One Shot
In
7-182
SSI 32H6811 /6811 B
Servo Motor Speed
5V Driver/DACs
Motor Start-Up
interface, determines the basic switching parameters
for the operation. The M (3 bits) sets the minimum "on"
time of the lower drivers and sample delay time. The N
(2 bits) sets the switching period. The timing is given by:
Motor starting is accomplished by a companion I1P or
DSP via ADVANCE, RETR, BRAKE and COM/REV.
The I1P can assert RETR and BRAKE low to initialize
the commutation counter and then increment the counter
with ADVANCE. After RETR and BRAKE are asserted
low and de-asserted (the power-up condition for preparation to begin a starting sequence), the commutation
state will be state 0 per TABLE 1, but the lower driver
output B remains inactive to prevent current flowing
through the motor (out of A which is high). On the first
ADVANCE set high, the commutation state 1 is selected and the drivers are per TABLE 1. ADVANCE at
logic high excludes internal commutations. COMMU
provides feedback to the I1P on motor activity.
Minimum "on" time = (M+ 1) • 4.5 !J.S
Sample delay time = M • 4.5 !J.S
Switching period = (N+2) • (M+1) ·4.5!J.S
Hence, Minimum duty cycle = 1/(N+2)
Sample delay time, defined as the time from turning the
lower drivers "on" until switching transients have settled,
is a function of the particular application and will be
determined by the user.
The value of M=O is defined as Linear mode, no
switching except normal commutation will occur.
Switch-Mode Operation
Switch-Mode Operation (continued)
Switch-mode operation is provided for limiting the
motor current during motor start-up. Two values M and
N,loaded into the mode register (10) through the serial
For a proper switch-mode. operation, three flyback
diodes from outputs A, B, and C, and a blocking diode
from the system power supply VCC to the VSMP1 and
Pullups
B
C
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
Pulldowns
B
STATE
COMMU
A
0
0
1
2
0
OFF
OFF
ON
OFF
ON
OFF
3
4
1
ON
OFF
OFF
OFF
ON
OFF
0
ON
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
OFF
OFF
ON
5
A
C
TABLE 1: Commutation States
VCHK>
VBG
RETR
BRAKE
0
x
x
x
Shutdown
ON
Active
Float
Float
1
0
x
0
Fault/Break
OFF
Active
Retract
LowZ
1
0
x
1
Fault/Retract
OFF
Active
Retract
Float
0
0
Sleep
OFF
Reset
Float
Float
0
1
Retract
ON
Active
Retract
Float
1
0
Brake
ON
Active
Float
LowZ
Run
ON
Active
Active
Active
OTSD
1
Mode
Analog
TABLE 2: Mode of Operations
7-183
Counter
VCM
Driver
MSC
Driver
II
SSI32H6811/6811B
Servo Motor Speed
5V Driver/DACs
VSMP2 pins are required. The flyback diodes will
provide power for retract (during power failure) at pins
VSMP1 and VSMP2.
Control Circuitry
The control circuitry consists of a power fault detector,
a thermal overload circuit, and control logic. The inputs
to the control circuitry are VCHK, RETR, and BRAKE,
along with the internal signals from the thermal overload detector. The voltage fault detector monitors the
system power supply vee to prevent the VCM driver
from responding to a false command during a power
failure. The system power supply is applied at VCHK
through an external resistor divider and compared with
an internal voltage reference at VBG.
Four operating modes are selected via RETR and
BRAKE (when th~ system power supply is present) per
Table 2. With RETR and BRAKE asserted low, the
VCM drivers are in a high impedance state, the MSC
driver outputs A, B, and C are low impedance to ground
(without current limiting), and analog circuits are debiased. This is the "Sleep" mode. It also provides
dynamic' braking to the spindle motor. With RETR
BIT
NAME
DESCRIPTION
o (LSB)
R/W
ReadlWrite control. It must be '0' for this device since all of its registers are write
only.
1,.2,3
DID0 .. 2
Device ID.These three bits define the SSI device for which the serial communication is,to be established. '111' is designated for this device.
4,5
ADDRO .. 1
Register address. These two bits define the internal register to which data is
transferred.
ADDR1
ADDRO
Register
0
0
VCM D/A
0
1
MSC D/A
1
0
Mode
1
1
Reserved
GAlN1
GAINO
Gain
0
0
30
0
1
20
1
0
10
1
1
5
The mode register (10) is defined as:
0
SWON
1,2
GAl NO, 1
Analog switch enable
Sense amplifier gain select, default 0,0
3
UNIPOLAR
4
NO
LSB of N value - minimum duty cycle
5
N1
MSB of N value
6
MO
LSB of M value - sample delay time
Unipolar mode enable
7
M1
M value
8
M2
MSB of M value:
9
COM/REV
Select COMMU(,;,O) or REVCLK (=1)
7-184
SSI 32H6811 /68118
Servo Motor Speed
5V Driver/DACs
asserted, BRAKE de-asserted, both VCM and MSC
drivers are in a high impedance state, and the retract
amplifier is activated and powered by the back emf of
a spinning motor for retracting heads. For BRAKE
asserted, and RETR de-asserted, the VCM drivers are
in a high impedance state, the MSC driver outputs are
low impedance to ground (without current limiting), and
analog circuits are biased. Normal mode is given for
RETR and BRAKE de-asserted.
When a power failure is sensed, the SYSRST is asserted low and the Retract mode is activated. If the die
temperature exceeds approximately 135 oC, the OTSD
is asserted low and all output drivers (both VCM and
MSC) are turned off. The drivers will become operative
after the temperature is reduced and the ADVANCE is
asserted high.
Serial Interface Port
A synchronous serial port, compatible with the commonly used JlP such as 80C196 and 68HC16, is used
to input digital words for D/Aconverters and mode
registers. It is shift register based I/O interface and
consists of three pins SDEN, SCLK and SDATA. Data
from uP is transferred 8 bits (one byte) at a time with the
LSB first. A complete transfer requires two bytes which
are formatted into an instruction and a data field.
Data received through SDATA is clocked into an internal16-bit shift register at the rising edge of SCLK while
SDEN is active high. Atthe end of each transfer, SDEN
must return low. If SDEN remains high after the last bit
(which is the MSB of the second byte) is received, any
additional data on SDATA will be ignored. Data must
be two bytes for each transfer. If, for any reasons,
SDEN is brought low prior to the completion of the
second byte, the write operation of ·the data will be
aborted.
The instruction field includes the first six bits of the first
byte and is defined per the table below. The data field
is 1O-bit wide and includes the last two ·oits of the first
byte and the second byte.
II
7-185
SSt 32H6811/68118
Servo Motor Speed
5V Driver/OACs
PIN DESCRIPTION
POWER SUPPLIES
NAME
TYPE
DESCRIPTION
VPA
Analog positive supply.
VNA
Analog ground.
VPD
Digital positive supply. It should be shorted externally with VPA.
VND
Digital ground. It should be shorted externally with VNA. VND is also the low
side input to the current sense amplifier of the spindle motor and thus care
should be taken to keep VND and the low side of the external resistor Rsense
at the same potential.
VVMP'
Positive supply used for voice coil motor.
VVMP1,2
Negative supply used for voice coil motor.
VSMP1,2
Positive supply used for spindle motor.
VSMN1,2
Negative supply used for spindle motor. They are also the high side inputs to
the current sense amplifier of the spindle motor.
• The circuit board contacts for VVMP, VVMN1, VVMN2, VSMP1, VSMP2, VSMN1, andVSMN2 must be
sized in accordance with anticipated motor currents. All pins must be connected with low resistance circuit
board traces.
SERVO POSITIONER
SWIN
I
The analog switch input. The other side of the switch is connected to ERRM.
ERRM
I
The inverting input of the error amplifier.
ERREF
I
The reference voltage for the error amplifier, the VCM D/A converter and the
current sense amplifier.
ERR
0
The error amplifier output. ERR is to provide compensation to the
transconductance loop and is reference to VBG.
SOUT
0
The current sense amplifier output. SOUT is referenced to ERREF.
VRETR
I
The retract voltage. If left open, the retract voltage will be the default setting.
Otherwise, it can be over-ridden by biasing VRETR externally.
VBYP1
I
The bypassed power supply. An external capacitor is connected to this node
to store charge for use by the retract circuitry. This pin is normally adiode drop
below vee, rising by VBEMF during retract.
VBYP2
I
The other side of the bypass capacitor is connected to this pin. It is normally
at ground, rising to VBEMF during retract.
VBEMF
I
Rectified spindle back emf voltage. This input provides current to the internal
retract power amplifier.
-
7-186
SSI 32H6811 /6811 B
Servo Motor Speed
5V Driver/DACs
SERVO POSITIONER
NAME
VM1
(continued)
TYPE
DESCRIPTION
One side of the voice coil motor.
VM2
0
0
The other side of the voice coil motor and sense resistor combination.
SE1,SE2
I
The voltage across the sense resistor for the voice motor current.
RETR
I
When asserted low, it forces a retract. Refer to Table 2.
POAC
0
The 1O-bit VCM 0/A converter output. It is referenced to ERREF.
SPINDLE MOTOR COMMUTATOR/DRIVER
SYSCLK
I
System clock input. SYSCLK is internally divided by a divider to generate an
internal clock at 2 MHz.
COM/REV
0
When the COM/REV bit in the mode regsiteris low, this pin is defined as the
LSB of the commutation counter. Otherwise, it is defined as the revolution
clock of the spindle motor.
ADVANCE
I
ADVANCE is used to increment the commutation counter externally. The
rising edge of ADVANCE will increment the counter by 1. When held high, it
inhibits the counter from internal incrementing. When held low, it permits the
normal operation of commutation from back emf events.
INCOM
I
Commutation delay control. Adaptive commutation delay may be adjusted
from its nominal value of one half the commutation interval by sinking or
sourcing current from this pin. This should be done via an external control loop
which can compensate for the range of intemal circuit parameter variations.
SDAC
0
The 10-bit MSC D/A converter output. It is referenced to VBG/2.
VIN
I
Control voltage input. The combination of the MOSFET drivers and the
predriver circuit forms a transconductance amplifier which sets the motor
current in relation to VIN. In conjunction with Rsense connected at VSMN and
the gain of the sense amplifier, the transconductance is defined by:
A,B,C
0
Spindle motor driver outputs.
CT
I
Back emf input from spindle motor coil center tap. Internal circuit uses the back
emf voltages to determine the rotor position and effect commutation.
RRAMP
I
Lower driver turn-off dv/dt setting resistor. External resistor from VPA to this
pin sets the dv/dt slope of the motor coil voltage when the lower drivers are
commutating to the off state. The dv/dt is approximately given by the relationship: dv/dt=15/RRAMP, where dv/dt is expressed in volts/J.ls and RRAMP
in kn.
BRAKE
I
BRAKE is used to provide a delay between the initiation of fault-induced head
retract and spindle motor braking. A capacitor to ground and a resistor to
SYSRST are selected such that 1.2RC is equal to the maximum time required
for retract.
Gm = ImNlN = 1/(Rsense ·4)
7-187
II
SSI 32H6811 /6811 B
Servo Motor Speed
5V Driver/DACs
CONTROL CIRCUITRY
DESCRIPTION
NAME
TYPE
VCHK
I
Comparator input for power supply monitoring. When VCHK is below VBG, an
internal voltage fault is generated.
VBG
0
Voltage reference, generated from the internal bandgap voltage, for use with
the power supply monitor comparator.
IBR
0
A resistor is tied from this pin to ground to establish a bias current for internal
circuitry.
RCRST
O/C
This pin serves the dual purpose Qf providing power-on-reset and stretching
short internal VFAULT pulses to a width suitable for the host micro controller.
An external RC network sets the minimum width of any SYSRST pulse. If
RCRST is pulled low by external circuitry, this device will enter into the Retract
mode and puU.SYSRST low.
SYSRST
O/C
Whe n low, this open-collector output indicates that an internal voltage fault has
occurred.
OTSD
O/C
Thermal shut-down. When low, this open- collector output indicates that the
junction temperature has exceeded the recommended operating range and
the device is in thermal shut-down. In thermal shut-down, all output drivers are
turned off and analog circuit de-biased.
I
Biased low with an internal pull-down. When asserted high, RETR will be
connected to the thermal overload test circuitry for use as a test input.
THTEST
SERIAL INTERFACE PORT
SDATA
I
Serial data input passing digital words for internal registers.
SCLK
I
Serial data timing reference. The rising edge olthe SCLK is to strobe SDATA
while SDEN is asserted high.
SDEN
I
Serial data transfer enable. When active high, the serial data transfer is
enabled.
7-188
SSI 32H6811/6811 B
Servo Motor Speed
5V Driver/DACs
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Exposure to absolute maximum rating conditions for extended periods may cause permanent damage to the
, device or affect device reliability.
PARAMETER
RATING
Supply voltage @
VPA, VPD, VVMP, VSMP1, VSMP2
Motor current @
A, B,C, VM1, VM2
Vdd-0.3
Imax
Input voHage @
VIN, RRAMP
Yin
7.0V
±1.0A
-0.3 to VDD + 0.3 V
Input voHage @
CT,A,B,C,VBEMF,VBYP1,VBYP2
VM1, VM2, SE1, SE2
Other pins
Storage temperature
Lead temperature
(10 sec duration)
Tstg
Tlead
-0.3 to 12.0 V
-0.3 to 7.0 V
-0.3 to Vdd V
-65 to 150°C
oto 300°C
RECOMMENDED OPERATING CONDITIONS
The recommended operating conditions for the device are indicated in the table below. Performance
specifications do not apply when the device is operated outside the recommended conditions.
PARAMETER
Supply voHage
MIN
Vdd
NOM
4.5
MAX
UNIT
5.5
V
Supply current
VPA,VPD
Sleep mode
Idd
25
rnA
Isleep
1.0
rnA
VBYP1,braking
Ibrk
10
~
VBYP1,retract
Iret
20
~
V
Input voltage@ VBEMF
1.0
Input voltage @ ERREF
0.5
Input voltage @ VIN
Ambient temperature
Ta
Capacitive load on digital outputs
CI
7-189
10
VDD-2.0
V
0
VBG
2.5
V
0
70
°C
100
pF
SSI32H6811/68118
Servo Motor Speed
5V Driver/DACs
RECOMMENDED OPERATING CONDITIONS (continued)
PARAMETER
SYMBOL
Analog output load
CI
MIN
NOM
MAX
40
RI
10
UNIT
pF
kQ
System clock
Frequency tolerance
Ic
6
Pulse width
Twh, Twl
40
Biasing resistor Rbias = 22.6 kQ
Rbias
22
External resistors
Rf,Rc
10
Power dissipation
Pd
10
MHz
ns
24
k.Q
--~
kQ
500
mW
MAX
UNIT
PERFORMANCE SPECIFICATIONS
DIGITAL 110
PARAMETER
CONDITIONS
MIN
NOM
Digital input@ SDATA, SCLK, SDEN, ADVANCE, SYSCLK, RETR
Vii
V
0.8
...-
Vih
2.0
V
Iii, lih
±10
IlA
2.0
V
±10
IlA
Digital input @ BRAKE
Vii
Vih
1.2
"-----.
-------"
--
liI,lih
V
Digital OIC output @ RCRST, SYSRST, OTSD
= Vdd
loh
Voh
101
Vol = 0.4
Digital Output @ COM/REV
Vol
Voh
10
4
IlA
mA
--
= 2.0 mA
loh = ·100 IlA
0.4
101
7-190
2.4
V
V
SSI 32H6811/6811 B
Servo Motor Speed
5V Driver/DACs
SERVO POSITIONER
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
BEMF current
Normal mode
VBEMF =4V
300
~
Retract mode
VBEMF = 3V, Imotor = 0
20
~
3.9
4.1
VN
-3
3
mV
0.15
VDD-1
V
±15
mV
0.15
VDD-1.25
IVBYP2= 0
SOUT amplifier
Gain
Input offset
SOUT=VBG
Output swing
RL = 10 kQ toERREF
ERRAMP amplifier
Input offset
ERR = ERRM
Output swing
Gain
Unit Gain Bandwidth
V
dB
60
ERR = ERRM
-15
11
13 '
VN
RL = 16Q Tj = 25°C,
0.4
0.6
AN
25
~
15
mV
Power amplifier (VCM Driver)
Gain (VM1-VM2)/(ERR-VBG)
Output voltage drop
lmotor = 0.2A
Bridge crossover time
Ivcm = 10 mA, pp@ 1 kHz
RL = 16Q
VCM output THO
Ivcm=100 mA, pp@ 100 Hz
2
%
250
Q
-100
0
mV
-1
1
~
RL = 16Q
SWIN on resistance
Retract amplifier (retract), VRETR = 0.5V, VBEMF > 1V, RL = 16Q
offset
VRETR
Maximum output current, VRETR = 0.5V, VBYP1 = 4.5V
VBEMF = 1V, VM1 = VM2
60
VBEMF = 1.5V, VM1 = VM2
100
mA
mA
±10
Retract Amplifier (normal)
VRETR leakage
7-191
~
SSI 32H6811/6811 B
Servo Motor Speed
5V Driver/OACs
SPINDLE MOTOR COMMUTATOR/DRIVER
PARAMETER
Tshift, Shift Range in commu delay
CONDITIONS
INCOM
MIN
NOM
= 0 to 0.8V
MAX
UNIT
±15
%
a-pole Motor @ 3600 rpm
Input current @ VIN
0< VIN < 2.5V
±1
~
Total FETs voltage drop
Imotor = 0.5A
0.85
V
Outputs @ CT, A, B, C while not driving
Rin
-0.3V < Yin < 7V
Cin
CT
Cin
A. B, C
10
kQ
20
pF
200
pF
2
5.5
V
2.13
2.37
V
±15
mV
CONTROL CIRCUITRY
Vdd voltage for SYSRST
& RCRST in operation
VBG
lout < +0.2 mA
VCHK comparator offset
Thermal shutdown
Temperature threshold
Hysteresis
125
°C
5
°C
D/A CONVERTER
Full-scale voltage
Resolution
VBG
V
10
bits
Digital Delay
LSB volatge
4
IJ.S
±1
LSB
VBG
V
V
VBG/1024
Dnferential nonlinearity
ERREF
VBG/2
SERIAL INTERFACE PORT
SDEN setup time prior to SCLK
Tsens
35
ns
SDEN hold time after SCLK
Tsenh
50
ns
SDATA setup time prior to SCLK rise
Tds
15
ns
SDATA hold time after SCLK fall
Tdh
15
ns
SCLK pulse width
Tpw
100
ns
7-192
SSI 32H6811 /6811 B
Servo Motor Speed
5V Driver/DACs
Tds~
,Tdh
SDATA----<
(Wrlto)
FIGURE 2: SSI32H6811 Serial Interface Timing Diagram
APLICATIONS INFORMATION
10r-------~~-----r------~------~--------r_~
8~---~~---r--~~-----~-----~~
T. sec
Ria, deg elw
0.5
1
2
10
8.5
12.5
17.8
52.5
87.5
(steady state)
ti
~6~====~~--t-~~t---~~----t-----1-----I
~
~
I
E
:::>
4r--------+-+------+-----~~----~~~--~._~~------_r------_1
2F======*~~--T_~--~------~~~~~~--_r----__1
10 sec
o
100
Ambient Temperature, deg C
Junction temperature at 125°C is assumed
FIGURE 3: Power Dissipation Derating
7-193
120
II
SS132H6811/6811 B
Servo Motor Speed
5V Driver/DACs
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
60 59 58 57 56 55 54 53 52 51
NIC
om!
VeGAP
THTEST
VPA
VRETR
YBEMF
WMN1
VM'
VVMP
VM2
WMN2
NIC
NIC
NIC
NIC
64·LEAD TQFP
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use
for final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems.
Silicon Systems reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the data sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
11:>1993 Silicon Systems, Inc.
7-194
1293- rev.
SSI32H6812
Servo & Spindle Driver with
Shock Detection
November 1993
FEATURES
DESCRIPTION
The 32H6812 Servo/MSC Driver, a CMOS monolithic
integrated circuit housed in a 48-lead TQFP package,
operates from a single 5V supply. It provides a fully
integrated servo driver and a spindle motor speed
controller with internal power FETs. The servo driver is
intended for use in disk drive head positioning systems
employing linear or rotary voice coil motors. The
spindle driver in conjunction with a microprocessor
(IlP) or digital signal processor (DSP), provides a
complete spindle motor speed control system. It also
includes one 10-bit D/A converter, a serial interface
compatible with commonly used IlP or DSP, and power
fault circuitry. The device is ideal for use in 5V small
form-factor disk drive applications and is available in a
48-Lead TQFP package.
48-lead TQPF package
Internal 1A servo driver with no deadband,
class-B output
Power fault detection with built-In retract
circuitry
1D-bH VCM 01 A converter with 4 IlS digital delay
Internal precision voltage reference
Programmable commutation delay for optimal
motor efficiency
Closed loop speed control at 5400 rpm
Internal1A spindle driver
Serial interface compatible with Intel 80C196
and Motorola 68HC16
Low power CMOS design with Sleep mode
Internal shock detection circuitry
PIN DIAGRAM
48 47 46 45 44 43 42 41 40 39 39 37
VGP
GIN
.2
36
sell<
35
SDATA
SDEN
GOUT
34
GSUM
33
VPD
VPA
32
VSMP
31
C
30
VSMN
VRETR
VBEMF
7
VVWN
29
B
VM1
28
VSMP
A
VVMP
10
27
VM2
11
26
VVMN
12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSMN
CT
48-Lead TQFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
1193 -
rev.
7-195
BLOCK DIAGRAM
Rt
l-~L.:::..-f-l SPINDLE
CT
VNO
7-196
SSI32H6812
Servo & Spindle Driver with
Shock Detection
FUNCTIONAL DESCRIPTION
Retract Amplifier
As shown in the block diagram, the 32H6812 can be
divided into four major sections: servo positioner, spindle
motor speed controller/driver, control circuitry and serial
interface port.
When a voltage fault is sensed, or when RETR bit is
asserted low while BRAKE bit is high, the servo
positioner enters into Retract mode. In this mode, it is
assumed that no current is available for VVMP.Thus
power for this mode comes from VBEMF, the rectified
spindle back emf voltage, and from VBYP1, a voltage
generated from the external storage capacitor CBYP.
The retract amplifier is powered by VBYP1. It senses
the voltage at VRETR and, through a power NMOS
source follower, raises VM1 to VRETR. The drain ofthe
source follower is VBEMF.
SERVO POSITIONER
The servo positioner is a power transconductance
amplifier for use in driving a voice coil servo motor
(VCM). It has two primary modes of operation, normal
(or linear) and retract. The retract mode is activated by
a powersupplyfailure or when RETR bit is asserted low
with BRAKE (bit) being high. Otherwise the device
operates in linear mode. The servo positioner consists
of SOUT amplifier, ERR amplifier, retract amplifier,
power amplifier and 10-bit VCM D/A converter.
SOUT Amplifier
The SOUT amplifier generates a voltage at SOUT
proportionalto positioner current, by sensing the voltage
across an external resistor Rs, amplifying it and
referencing it to VBG. Since the common mode voltage
on Rs can range over the full power supply, while the
differential voltage is in the order of millivolts, the SOUT
amplifier is realized with high input common mode
rejection and low input offset.
ERR Amplifier
The ERR amplifier is a high gain op amp. Due to the
fixed gain of the power amp, ERR is proportional to the
VCM voltage. The negative input of this amplifier is the
system summing junction for the currents which are
proportional to the desired VCM current, the measured
VCM current, and the VCM voltage.
Power Amplifier
The power amplifier is a fixed gain voltage amplifier
with differential inputs and outputs. Its input is the
differential voltage between ERR and VBG. Its output
drives the VCM directly through an internal NMOS
bridge. An internal charge pump generates gate
voltages higher than WMP so the upper NMOS devices
can drive VM1 and VM2 up to VVMP.
VCM D/A Converter
Switched-capacitor circuitry is employed to implement
the VCM D/A converter with two non-overlapped clock
phases, one phase for auto-zeroing and another one
for evaluation. These two phases run synchronously
with an internal 500KHz clock, which is derived directly
from the system clock at SYSCLK.
The request of the VCM D/A converter is initiated by
writing to the VCM D/A register (00) through the serial
interface port. The input data word must be coded in
two's complement form. Note that there would be a
. maximum of 2 IlS of latency between a conversion
request and the actual start of conversion. The
conversion delay from the actual start of conversion to
when the analog output begins to slew to a new value
is 2 1lS. Therefore a maximum of 4 IlS is required for a
conversion, in addition to the time needed forcompletion
of a serial data transfer, which is equal to 16/SCLK.
When MSCDAC bit in the MSC_MODE register is low
(default), VCM D/A converter output is provided at
PDAC and is referenced to V8G. V8G also serves as
a reference voltage for the error amplifier and the
current sense amplifier. If MSCDAC bit is asserted
high, D/A converter output will be switched to LF pin
and referenced to VBG/2.
7-197
SSI32H6812
Servo & Spindle Driver with
Shock Detection
SPINDLE MOTOR SPEED
CONTROLLER/DRIVER (CONTINUED)
bit (MSC_MODE bit 0) rising edge will advance the
motor to next commutation state (see Table 1).
The spindle motor speed controller in conjunction with
a ~P or DSP and external components provides the
motor driving capability for starting, accelerating and
rotational speed regulation for brush less DC motors
without the need for Hall sensors.
When the motor achieves sufficient speed to generate
adequate back EMF voltage, ADVANCE and START
bits are reset by the ~P. The motor will then continue to
accelerate using the internal commutation delay
selected by the DELAY bits (MSC_MODE bits 4 and 5).
To set the motor start-up current, MSCDAC bit
(MSC_MODE bit 7) should be asserted to high. The
transconductance amplifier input LF will then be
provided from the VCM DfAconverter. By programming
VCM DAC and sense amplifier gain (GAINO,1 bits in
MSC_MODE), motor start-up current will be:
SPINDLE MOTOR START-UP
Typical spindle motor start-up is accomplished with a
companion ~P. The commutation counter and the
period counter can be initiated at power on or at START
bit (MSC_MODE bit 6) rising edge. START bit should
be held high during start-up to mask false commutation
due to transient on the motor coils (A, B, C). STAN DBY
bit (CONT_MODE bit 2) can then be asserted to high
along with RETR = BRAKE = 1 (this is Standby mode,
see Table 2 ) to activate the spindle drivers and align
the motorto startcup position (state 0). EachADVANCE
VLF
G·
IMotor = - • am
RSense
where voltage at LF pin will be precharged to the DAC
output voltage. For fast precharging, external LF resistor
(RL in Fig. 1) will also be shorted to ground through the
SWpin.
Table 1: Commutation States
PULLDOWNS
PULLUPS
STATE
COMMU·
A
B
C
0
0
OFF
ON
OFF
1
1
OFF
OFF
2
0
OFF
OFF
3
I
4
5
I
I
-
C.
A
B
ON
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
,
1
ON
OFF
OFF
OFF
ON
OFF
0
ON
OFF
OFF
OFF
OFF
ON
1
OFF
ON
OFF
OFF
OFF
ON
7-198
SSI32H6812
Servo & Spindle Driver with
Shock Detection
SPINDLE MOTOR SPEED REGULATION
LOOp Filter
The motor speed regulation loop consists of a period
counter, speed eiTor detector, charge pump, loop filter
and transconductance loop; as well as a commutatorto
determine the sequential switching of driver current to
the motor winding.
An external RC lowpass filter must be connected atthe
LF pin. LF also serves as the input to the
transconductance amplifier. When the MSCDAC bit is
asserted high during start-up and acceleration, external
resistor RL is shorted to ground and the VCM D/A
converter will .be used to precharge the external
capacitors at the LF pin, and thus set the motor start
current.
Period Counter
A 500 kHz period cOljnter starts with counts 5555
(5400.54 rpm) at the beginning of each revolution and
counts down. Period resolution is therefore 2 IJ.S. The
counter resets at the end of each revolution.
Speed Error Detector
The speed error detector measures the difference
between each motor revolution (a-pole or 12-pole
selected by POLE in MSC_MODE bit 3) and the period
counter and feeds this speed error to the charge pump
circuit. When speed error is within ±321J.S (15.55 rpm)
the. motor is in "LOCK" The LOCK co.ndition can be
monitored on COM/REV pin by setting CRLO = 0 and
CRL 1 = 1 (MSC_MODE bits a and 9). A logic HIGH on
COM/REV pin then indicates motor speed is in LOCK.
If the speed error exceeds 10241J.S (497.66 rpm) too
slow, the TOOSLOW condition can be monitored on
COM/REV pin by setting CRLO = 1 and CRL 1 = 1. A
logic HIGH on COM/REV pin will then indicate motor
speed is too slow.
Charge Pump
A constant current source of 60 J.IA is used to charge or
discharge for a 2 IJ.S time multiple determined by the
pUlse-width modulation of the speed error. When the
motorspeed error exceeds 10241J.S too fast, the charge
pump will discharge the LF pin for the whole period.
Transconductance Loop
Input pin LF is the non-inverting input of a
transconductance amplifier, which uses the lower driver
transistor that is presently active per the commutation
state, as the power driver element. An external resistor
is used to sense the motor coil current. The voltage
across the sense resistor is amplified by a gain stage
(Gain =5,10,20 or30 selected by the GAIN bits inthe
MSC_MODE register) and fed to the inverting input of
the transconductance amplifier.
The output pins A, 8 and C are intended to drive motor
coils directly. The output drivers operate to reduCe
switching noise transients by limiting dv/dt during
commutation. Each output consists of two N-channel
MOSFET drivers, one for pullup to VSMP1 or VSMP2
and one for pulldown to VSMN1 or VSMN2. The pullup
FET functions as a switch with voltage rise and fall
times of about 25 microseconds. The pulldown FET is
a part of the transconductance amplifier which converts
the voltage LF into motor current (I motor . = VLF/
(RSENSE • Gain)). When the pulldown output is
commutating to the off state, dv/dt on the respective pin
is controlled such that dv/dt is approximately 15/RRAMP
volts per IJ.S, where RRAMP is measured in kil.
When the MSCDAC bit is asserted to high, the charge
pump is disabled. LF voltage will then be provided from
the VCM D/A converter. If the MSCDAC bit is low
(default) and the speed regulation loop is activated, LF
voltage will be limited to V8G to avoid excess current
on the drivers. Since leakage current on LF pin can
introduce speed error, leakage current on LF pin is
limited to within 60 nA in order to achieve the highest
speed accuracy.
7-199
SSI32H6812
Servo & Spindle Driver with
Shock Detection
SPINDLE MOTOR
SPEED REGULATION (CONTINUED)
CONTROL CIRCUITRY
The control circuitry consists of a power fault detector,
a shock detection circuit, and control logic.
Commutator
Motor armature position is determined by monitoring
the coil voltage of thewinding that is not presently being
driven by the drivers. The back EMF from the coil, in
conjunction with the state olthe output drivers , indicates
the armature position. The back EMF is compared with
a reference at center tap and initiates commutation
"events" when the appropriate comparison is made.
Because the back EM F comparison event occurs prior
to the time when optimum commutation should occur,
it is preferred to delay commutation by a predetermined
time after the comparison. There are two modes 01
commutation delay: adaptive and fixed delay. These
are selected via the DELAY bits in the MSC MODE
register. In adaptive mode (default), the commutation
delay is provided by a circuit which measures the
interval between comparison events and delays
commutation by a time equal to 3/7 olthe prior measured
interval, The circuit is adaptive and will provide the
optimum delay for a wide range of motor speeds (-80%
to 50% of the nominal value). Since the commutation of
motor coils typically causes transients, the commutation
delay circuit also provides a noise blanking function
which. prevents the circuit from responding to back
EMF comparison events for a period of time equal to
the greater of 517 of the interval between events or 64
IlS after the comparison event. In fixed delay mode, a
fixed delay and noise blank is provided. A longer fixed
delay might be desirable during start-up to prevent the
device from adapting to high frequency noise. The
commutation table is shown in Table 1.
The voltage fault detector monitors the system power
supply VCC to preventthe VCM driverfrom responding
to a false command during a power failure. The system
power supply is applied at VCHK through an external
resistor divider and compared with an internal voltage
reference at VBG. Hysteresis is generated internally at
the VCHK comparator.INhen a power fault is sensed,
even for a brief power drop, POR pin will be pulled low
regardless of the capacitance loading. Retract mode is
activated during power fault.
Three power saving modes are provided, "Sleep,"
"Standby" and "Shockslp," along with three operating
modes. All are selected with RETR, BRAKE, STANDBY,
and SHOCKSLP bits per Table 2. With RETR and
BRAKE low, both the VCM drivers and MSC drivers are
in a high impedance state, and analog circuits are debiased; this is the "Sleep" mode. With RETR and
BRAKE high, and STANDBY high, MSC section is
biased with spindle drivers activated; this is the
"Standby" mode. With RETR low, BRAKE high, both
VCM and MSC drivers are ina high impedance state,
and the retract amplifier is activated and powered by
the back EM F of a spinning motor for retracting heads.
With BRAKE low, and RETR high, the VCM drivers are
in a high impedance state, the MSC driver outputs are
low impedance to ground (without current limiting), and
the analog circuits are biased. Run mode occurs when
RETR and BRAKE bits are high and STANDBY and
SHOCKSLP bits are low.
A 2-axis shock detection circuitry is implemented to
sense the shock signal at XIN and YIN pins. The shock
signal across XIN, XREF pins (andYIN,YREF pins) is
amplified and full-wave rectified and then summed
with the other axis component at GSUM.This signal
then goes through a lowpass filter and is compared to
VBG/2. When SHOCKSLP is high, the shock detection
circuitry is turned off; this is "SHOCKSLP" mode.
7-200
SSI32H6812
Servo & Spindle Driver with
Shock Detection
TABLE 2: Power Management/Operation Modes
MODE
J5rnf
'Rrnf
tmAI
.~ 4 r----+_~---+_---.::""'+_---"___+_-~-+_---+_--__f
::a
o
20
40
60
80
100
Ambient Temperature, deg C
Junction temperature at 125°C is assumed
FIGURE 1: Power DIssipation Derating
7-211
120
SSI32H6812
Servo & Spindle Driver with
Shock Detection
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
48 47 46 45 44 43 42 41 40 39 38 37
VGP
36
SCLK
GIN
35
SDATA
GOUT
34
SDEN
GSUM
33
VPD
VPA
32
VSMP
VRETR
31
C
VBEMF
30
VSMN
WWN
29
B
VM1
WMP
VM2
WMN
10
11
28
VSMP
27
A
26
12 13 14 15 16 17 18 19 20 21
22 23 24 25
VSMN
CT
48-Lead TQFP
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only, Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc. 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1993 Silicon Systems, Inc.
7-212
1193 - rev.
SSI32H6814
5V Servo/Motor Speed Driver
'M ME' na, mt.,; hE" t" ;.
January 1994
DESCRIPTION
FEATURES
The SSI 32H6814 Servo/MSC Driver is a CMOS
monolithic integrated circuit housed in a 64-lead TQFP
package which operates from a single 5V supply. It
provides .a fully integrated servo driver and a spindle
motor commutator with internal power FETs. The
servo driver is intended for use in disk drive head
positioning systems employing linear or rotary voice
coil motors. The commutator in conjunction with a
microprocessor (IlP) or digital signal processor (DSP),
provides a complete spindle motor speed control
system. It also includes two 1O-bit D/A converters, with
a serial interface to commonly used IlP or DSP, for
commanding the servo positioner and the spindle
motor, respectively. The device is ideal for use. in 5V
small-form disk drive applications.
64-lead TQPF package
Internal 1.0A servo driver with no deadband,
class-B output
Thermal overload protection
Power fault detection with built-in retract
circuitry
1O-bit VCM 01 A converter with 41ls digital delay
Gain select switch for a wide dynamic range of
servo inputs
Internal precision voltage reference
Programmable commutation delay for optimal
motor efficiency
Internal 1.25A spindle driver
PIN DIAGRAM
'"
... 48
V2P5
47
~
46
VSMN
C
IBR
3
VNA
45
VRETR
44
VSMP
VBEMF
43
B
WMN
42
VSMN
VMl
41
A
9
40
VSMP
VM2
10
39
C
WMN
11
38
VSMN
VM1
12
37
B
WMP
13
38
VSMP
A
WMP
VM2
14
35
WMN
15
34
VSMN
THTEST
16
33
SENSE
64-Lead TQFP
0194
REm
VCHK
7-213
CAUTION: Use handling procedures necessary
for a static sensitive component.
II
SSI32H6814
5V Servo/Motor Speed Driver
SOUT
EAREF
~--------------~~+
-r---------------------------------------------,
SEl
r-------------~~~~-
+r-----------------------------------------------~
SE2
SOUT
AMP
VAETA
VBYPl
VBYP2
PDAC
VBEMF
VVMP(2)
EAAM
VM1(2)
SWIN
VM2(2)
ERR
VVMN(3)
VBG
5fSIl"
IBA
THTEST
RCAST
VCHK
VCHKTH
VCHKTL
VSMP(3)
SDAC
AAAMP
A(2)
V2P5
B(2)
VIN
C(2)
SENSE
VSMN(4)
SENAEF
SDEN
SDATA
SCLK
COMMUTATOR
ADVANCE
SYSCLK
INCOM
CT
VPA
VNA
VPD
VND
~ COM/REV
Figure 1: Block Diagram
7-214
SSI32H6814
5V Servo/Motor Speed Driver
POWER AMPLIFIER
FEATURES (continued)
Switch-mode current limiting for spindle motor
start-up
Serial interface compatible with 80C196 and
68HC16
Low power CMOS design with Sleep mode
FUNCTIONAL DESCRIPTION
The power amplifier is a fixed gain voltage amplifier
with differential inputs and outputs. Its input is the
differential voltage between ERR and VBG. Its output
drives the VCM directly through an internal NMOS
bridge. An internal charge pump generates gate
voltages higherthan VVMP so the upper NMOS devices
can drive VM1 and VM2 up to VVMP.
RETRACT AMPLIFIER
As shown in the block diagram, the SSI 32H6814 can
be divided into four major sections: servo poSitioner,
spindle motor commutator/driver, control circuitry and
serial interface port.
SERVO POSITIONER
The servo positioner is a power transconductance
amplifier for use in driving a voice coil servo motor
(VCM). It has two primary modes of operation, normal
(or linear) and retract. The retract mode is activated by
a power supply failure or when RETR is asserted low
while BRAKE being high. Otherwise the device operates
in linear mode. The servo positioner consists of SOUT
amplifier, ERR amplifier, retract amplifier, power
amplifier and 10-bit VCM D/A converter.
SOUT AMPLIFIER
The SOUT amplifier generates a voltage at SOUT,
proportionalto positionercurrent, by sensing the voltage
across an external resistor Rs, amplifying and
referencing to ERREF. Since the common mode
voltage on Rs can range over the full power supply,
while the differential voltage is in the order of millivolts,
the SOUT amplifier is realized with a high input common
mode rejection and low input offset.
ERR AMPLIFIER
The ERR amplifier is a high gain op amp. Due to the
fixed gain of the power amp, ERR is proportional to the
VCM voltage. The negative input of this amplifier is the
system summing junction for the currents which are
proportional to the desired VCM current, the measured
VCM current, and the VCM voltage.
When a voltage fault is sensed, or when RETR is
asserted low while BRAKE being high, the servo
positioner enters into retract mode. In this mode, it is
assumed that no current isavaiiablefromVVMP. Thus
power for this mode comes from VBEMF, the rectified
spindle back emf voltage, and from VBYP1, a voltage
generated from the external storage capacitor CBYP.
The retract amplifier is powered by VBYP1. It senses
the voltage at VRETR and, through a power NMOS
source follower, raises VM1 to VRETR. The drain of
the source follower is VBEMF.
VCM D/A CONVERTER
Switched-capacitor circuit technique is employed to
implement the VCM D/A converter with two nonoverlapped clock phases, one phase for auto-zeroing
and another one for evaluation. These two phases run
synchronously with an internal 500 kHz clock, which is
derived directly from the system clock at SYSCLK.
The request of the VCM D/A converter is initiated by
writing to the VCM D/A register (00) through the serial
interface port. The input data word must be coded in
two's complement form. Note that there would be a
maximum of 2 IlS of latency between a conversion
request and the actual start of conversion. The
conversion delay from the actual start of conversion to
when the analog output begins to slew to a new value
is 21lS. Therefore a maximum of 41lS is required for a
conversion, in addition to the time needed for completion
of a serial data transfer, which is equal to 16/SCLK. The
VCM D/A converter provided at PDAC is referenced to
ERREF, which also serves as a reference voltage for
the error amplifier and the current sense amplifier.
SPINDLE MOTOR COMMUTATOR/DRIVER
The spindle motor commutator in conjunction with
external components provides the motor driving
capability for starting, accelerating and rotational speed
regulation forbrushless DC motors withoutthe need for
Hall sensors. The speed regulation control loop is
completed with a ~P or DSP external to this device.
7-215
II
SSI32H6814
5V Servo/Motor Speed Driver
FUNCTIONAL DESCRIPTION (continued)
COMMUTATOR
Motor armature position is determined by monitoring
the coil voltage ofthewinding that is not presently being
driven by the drivers. The back emf from the coil, in
conjunction with the state ofthe output drivers, indicates
the armature position. The back emf is compared with
a reference at CT and initiates commutation "events"
when the appropriate comparison is made.
Commutation is the sequential switching of drive current
to the motor windings. Because the back emf
comparison event occurs priorto the time when optimum
commutation should occur, it is preferred to delay
commutation by a predetermined time after the
comparison. There are two modes of commutation
delay, namely adaptive or one shot, which can be
selected via the M, N bits in the mode register (1 0) per
table 1. In adaptive mode (default), the commutation
delay is provided by a circuitry which measures the
interval between comparison events and delays
commutation by a time equal to 317 of the prior measured
interval. The circuit is adaptive and will provide the
optimum delay for a wide range of motor speeds (-80%
to 50% of the nominal value). Since the commutation
of motor coils typically causes transients, the
commutation delay circuit also provides a noise blanking
function which prevents the circuit from responding
back emf comparison events for a period of time equal
to the maximum of 5/70f the interval between events
and 64 IlS after the comparison event. INCOM pin can
be selected asa test pin if it is high impedance in the
adaptive mode, otherwise it should be selected as "IN"
for the adaptive mode to work properly. In one shot
mode, an input voltage at INCOM pin will provide a fix
delay and noise blank. For start~up, INCOM = Vdd/2.is
recommended, delay will be about 500 IlS and noise
blank about 850 j.LS. The commutation table is described
in Table 2.
Motor speed control may be accomplished by measuring
the period of the output Signal at COM/REV. COMI
REV may be defined as either COMMU, the LSB ofthe
commutation counter, or REVCLK, the revolution clock
of the motor, selected via the bit COM/REV in the mode
register (10).
TRANSCONDUCTANCE AMPLIFIER
Input pin VIN is the non-inverting input of a
transconductance ampJifierwhich uses the lower driver
transistor, that is presently active per the commutation
state, as the power driver element. An external resistor
is used to sense the current flowing through the drive
transistor source (and hence the motor coil current).
The voltage across the sense resistor is amplified by a
gain stage (Av=5, 10, 200r30 selected by the GAIN bits
in the MODE register) and fed to the inverting input of
the transconductance output stage.
The 1O-bit SPM 0/A converter, referenced to VBG/2, is
provided at SDAC for converting the commanding
Signal in digital format into an analog voltage. Its
operation is similar to the VCM D/A converter, but is
initiated by writing to the SPM D/A register (01) in two's
complement form.
POWER AMPLIFIER
The output pins A, Band C are intended to drive motor
coils directly. The output drivers operate to reduce
switching noise transients by limiting dv/dt during
commutation. Each output consists of two N-channel
MOSFET drivers, one for pullup to VSMP and one for
pulldown to VSMN. The pullup FET functions as a
switch with voltage rise and fall times of about 25 j.LS.
The pulldown FET is a part of the transconductance
amplifier which converts the voltage VIN into motor
current (Imotor=VIN/(RSENSEAv), where Av is either
5,10,20 or 30). When the pulldown output is
commutating to the off state, dv/dt on the respective pin
is controlled such that dv/dt is approximately 15/RRAMP
volts per 1lS, where RRAMP is measured in kn.
TABLE 1: Modes of Commutation Delay
MODE REGISTER (10)
M
N
SWITCH DELAY
MODE
DELAY
MODE
INCOM
PIN
0
0
No
Adaptive
Test (Default)
0
1,2
No
Adaptive
In
0
3
No
One Shot
In
0
X
Yes
One Shot
In
7-216
SSI32H6814
5V Servo/Motor Speed Driver
MOTOR START-UP
Motor starting is accomplished by a companion IJ.P or
DSP via ADVANCE, RETR, BRAKE and COM/REV.
The IJ.P can assert RETR and BRAKE lowto initiate the
commutation counter and then increment the counter
with ADVANCE. After RETR and BRAKE are asserted
low and de-asserted (the power-up condition for
preparation to begin a starting sequence), the
commutation state will be state 0 per Table 1, but the
lower driver output B remains inactive to prevent current
flowing through the motor (out of A which is high). On
the first ADVANCE set high, the commutation state 1 is
selected and the drivers are perTable 2. ADVANCE at
logic high excludes internal commutations. COMMU
provides feedback to the IJ.P on motor activity.
SWITCH-MODE OPERATION
Switch-mode operation is provided for limiting the
motor current during motor start-up. Two values M and
N, loaded into the mode register (1 0) through the serial
interface, determines the basic switching parameters
forthe operation. The M (3 bits) sets the minimum "on"
time of the lower drivers and sample delay time. The N
(2 bits) sets the switching period. The timing is given by:
Minimum "on" time = (M + 1) • 4 IJ.S
Sample delay time = M • 4 IJ.s
Switching period = (N + 2) • (M + 1) • 4 IJ.S
Hence, Minimum duty cycle = 1/(N+2)
Sample delay time, defined as the time from turning the
lower drivers "on"until switching transients have settled,
is a function of the particular application and will be
determined by the user.
The value of M=O (Default) is defined as linear mode,
no switching except normal commutation will occur.
For a proper switch-mode operation, three flyback
diodes from outputs A, B, and C, and a blocking diode
from the system power supply VCC to the VSMP pins
are required. The flyback diodes will provide power for
retract (during power failure) at pins VSMP, Also, a
voltage level should be provided at INCOM pin as the
threshold for the one-shot commutation delay.
CONTROL CIRCUITRY
The control circuitry consists of a power fault detector, a
thermal overload circuit, a voltage tolerance detector,
and control logic. The inputs to the control circuitry are
VCHK, VCHKTL, VCHKTH, RETR, and BRAKE, along
with the internal Signals from the thermal overload detector.
The power fault detector monitors the system power
supply VCC to prevent the VCM driver from responding
to a false command during a power failure. The system
power supply is applied at VCHK through an external
resistor divider and compared with an internal voltage
reference at VBG. When a power failure is sensed, the
SYSRST is asserted low and the retract mode is activated.
The thermal overload circuit monitors the die
temperature to prevent an excessive current flowing
through VCM or SPM drivers. If the die temperature
exceeds approximately 135°C, the OTSD is asserted
low and both drivers are turned off. The drivers will
become operative after the temperature is reduced
and the ADVANCE is asserted high.
The voltage tolerance detector generates an active low
signal VTOL when either VCHTL goes below VBG or
VCHTH goes above VBG. Note that no servo retract is
activated in this case.
Four operating modes are selected via RETR and
BRAKE (when the system power supply is present) per
Table 3. With RETR and BRAKE asserted low, both
TABLE 2' Commutation States
STATE
COMMU
PULLDOWN PULLDOWN
A
B
PULLDOWN
C
PULLUP
A
PULLUP
B
PULLUP
C
0
0
OFF
ON
OFF
ON
OFF
OFF
1
1
2
O'
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
3
1
ON
OFF
OFF
OFF
ON
OFF
4
0
ON
OFF
OFF
OFF
OFF
ON
5
1
OFF
ON
OFF
OFF
OFF
ON
7-217
I
SSI32H6814
5V Servo/Motor Speed Driver
must return low. If SDEN remains high after the last bit
(which is the MSB of the second byte) is received, any
additional data on SDATA will be ignored. Data must be
two bytes for each transfer. If, for any reasons, SDEN
is brought low prior to the completion of the second byte,
the write operation of the data will be aborted.
FUNCTIONAL DESCRIPTION (continued)
CONTROL CIRCUITRY
the VCM drivers and SPM drivers are in a high
impedance state, and analog circuits are de-biased.
This is the "sleep" mode. With RETR asserted, BRAKE
de-asserted, both VCM and SPM drivers are in a high
impedance state, and the retract amplifier is activated
and powered by the back emf of a spinning motor for
retracting heads. For BRAKE asserted, and RETR deasserted, the VCM drivers are in a high impedance
state, the SPM driver outputs are low impedance to
ground (without current limiting), and analog circuits
are biased. Normal mode is given for RETR and
BRAKE de-asserted.
The instruction field, as defined in Table 4, includes the
first 6 bits of the first byte. The data field is 1a-bit wide
and includes the last two bits of the first byte and the
second byte.
SERIAL INTERFACE PORT
A synchronous serial port, compatible with the
commonly used IlP such as 8aCi96 and 68HCi6, is
used to input digital words for D/A converters and mode
registers. It is shift register based I/O interface and
consists of three pins:SDEN, SCLK and SDATA. Data
from IlP is transferred 8 bits (one byte) at a time with
LSB first, MSB last, where LSB is defined as Bit
A
complete transfer requires two bytes which are
formatted into an instruction anda data field. Figure 2
shows the serial interface timing diagram.
a
The serial port is enabled for data transfers when the
Serial Data Enable (SO EN) pin is pulled high. SDEN
should be asserted high prior to any transmission and it
should remain high until the completion of the transfer.
At the end of each transfer SDEN should be brought low.
Serial data applied to SDATA is clocked into an internal
i6-bit shift register at the rising edge of SCLK while
SDEN is active high. At the end of each transfer, SDEN
TABLE 3: Mode of Operations
VCHK
>VBG
RETR
BRAKE
MODE
a
x
Shutdown
ON
Active
Float
Float
a
Faull/Brk
OFF
Active
Retract
LowZ
1
a
a
x
x
x
x
1
1
Faull/Ret
OFF
Active
Retract
Float
1
1
a
0
Sleep/Brk
OFF
Reset
Float
Float
OTSD
ANALOG
VCM
SPEED
COUNTER DRIVER
SPM
DRIVER
1
1
0
1
Retract
ON
Active
Retract
Float
1
1
1
0
Brake
ON
Active
Float
LowZ
1
1
1
1
Run
ON
Active
Active
Active
7-218
SSI32H6814
5V Servo/Motor Speed Driver
TABLE 4: Instruction Field Definition
BIT
NAME
DESCRIPTION
o (LSB)
R/W
Read/write control. It must be 'O'forthis device since all of its registers are write
only.
1,2,3
DIDO .. 2
These three bits define the SSI device for which the serial communication is
to be established. '111' is designated for this device.
4,5
ADDRO .. 1
Register address. These two bits define the internal register to which data is
transferred.
ADDR1
ADDRO
Register Name
0
0
VCM D/A
0
1
SPM b/A
1
0
Mode
t
1
Reserved
The mode register (10) is defined in Table 5.
TABLE 5' MOde Register Definition
BIT
NAME
DESCRIPTION
0
SWON
Analog switch enable.
1
GAINO
Sense amplifier gain select.
2
GAIN1
GAIN1
GAINO
Gain Selected
0
0
30(Default)
0
1
20
1
0
10
1
1
5
Start-up mode enable. It should be asserted high during spindle start-up
when the commutation is commanded bya train of ADVANCEpulses.
During spindle running, it should be asserted low (default) to .allow self
internal commutation
3
START
4
NO
LSB of N value - minimum duty cycle.
5
Nt
MSB of N value.
S
MO
LSB of M value - sample delay time.
7
M1
M value.
8
M2
MSB of M value.
9
COM/REV
Select COMMU (COM/REV==O, default) or REVCLK (COM/REV=1).
7-219
SSI32H6814
5V Servo/Motor Speed Driver
PIN DESCRIPTION
POWER SUPPLIES
NAME
TYPE
DESCRIPTION
Analog ground.
VPD
-
VND
-
Digital ground. It must be shorted externally with VNA.
VVMP
-
Positive supply used for voice coil motor.
VPA
VNA
VVMN
VSMP
VSMN
Analog positive supply.
Digital positive supply. It must be shorted externally with VPA.
Negative supply used for voice coil motor.
Positive supply used for spindle motor.
Negative supply used for spindle motor.
SERVO POSITIONER
NAME
TYPE
SWIN
I
The analog switch input. The other side of the switch is connected toERRM.
DESCRIPTION
ERRM
I
The inverting input of the error amplifier.
ERREF
I
The reference voltage forthe error amplifier, the VCM D/A converter and the
current sense amplifier.
ERR
0
The error amplifier output. ERR is to provide compensation to the
transconductance loop and is reference to VBG.
SOUT
0
The current sense amplifier output. SOUT is referenced to ERREF.
VRETR
I
The retract voltage. Retract voltage must be provided externally at VRETR
pin.
VBYP1
I
The bypassed power supply. An external bypass capacitor is connected to this
node to store charge for use by the retract circuitry. This pin is normally a diode
drop below VCC, rising by VBEMF during retract.
VBYP2
I
The other side of the bypass capacitor is connected to this pin. It is normally
at ground, rising to VBEMF during retract.
VBEMF
I
Rectified spindle back emf voltage. This input provides current to the internal
retract power amplifier.
VM1
0
One side of the voice coil motor.
VM2
0
The other side of the voice coil motor and sense resistor combination.
SE1,SE2
I
The voltage across the sense resistor for the voice motor current.
RETR
I
Retract control pin. Refer toTable 3.
0
The 1O-bit VCM D/A converter output. It is referenced to ERREF.
PDAC
7-220
SSI32H6814
5V Servo/Motor Speed Driver
SPINDLE MOTOR COMMUTATOR/DRIVER
NAME
SYSCLK
TYPE
I
DESCRIPTION
System clock input at 10 MHz.
COM/REV
0
When the COM/REV bit in the mode register is low, this pin is defined as the
LSB of the commutation counter. Otherwise, it is defined as the revolution
clock of the spindle motor.
ADVANCE
I
ADVANCE is used to increment the commutation counter externally. The
rising edge of ADVANCE will increment the counter by 1. When held high, it
inhibits the counter from internal incrementing. When held low, it permits the
normal operation of commutation from back emf events.
INCOM
I
Commutation delay control. Adaptive commutation delay may be adjusted
from its nominal value of one half the commutation interval by sinking or
sourcing current from this pin. This should be done via an external control loop
which can compensate for the range of internal circuit parameter variations.
SDAC
0
VIN
I
The 10-bit SPM D/A converter output. It is referenced to VBG/2.
Control voltage input. The combination of the MOSFET drivers and the
predriver circuit forms a transconductance amplifier which sets the motor
current in relation to VIN. In conjunction with Rsense connected at VSMN and
the gain of the sense amplifier, the transconductance is defined by
Gm = ImlVlN = 1/(RSENSEgain), gain=5, 10,20,30.
A,B,C
0
Spindle motor driver outputs.
CT
I
Back emf input from spindle motor coil center tap. Internal circuit uses the back
emf voltages to determine the rotor position and effect commutation.
RRAMP
I
Lower driver turn-off dv/dt setting resistor. External resistor from VPA to this
pin sets the dv/dt slope of the motor coil voltage when the lower drivers are
commutating to the off state. The dv/dt is approximately given by the relationship: dvldt=15/RRAMP, where dv/dt is expressed in volts/)l5 and RRAMP in
kil.
SENSE
i
Current sense amplifier non-inverting input. The current sense resistor connected to the sources of lower driver transistors is to monitor the current
flowing through the spindle motor. The device will control the voltage across
the sense resistor to match VIN. This pin provides a Kelvin connection to the
high side of the sense resistor and must be shorted with VSMN externally.
SENREF
I
Current sense amplifier inverting input. It provides a Kelvin connection to the
low side of the sense resistor.
BRAKE
I
BRAKE is used to provide a delay between the initiation of fault-induced head
retract and spindle motor braking. A capacitor to ground and a resistor to
SYSRST are selected such that 1.2RC is equal to the maximum time required
for retract.
7-221
II
SS132H6814
5V Servo/Motor, Speed Driver
PIN
DE~CRIPTION (continued)
CONTROL CIRCUITRY
NAME
TYPE
VCHK
I
Comparator inputfor monitoring power supply. When VCHK goes below VBG,
an internal voHage fauH is generated and hence the servo head retract is
activated.
VBG
0
Voltage reference at 2.23V, generated from the internal bandgap voHage, for
use with the power supply monitor comparator.
VCHKTL
I
Comparator input for monitoring supply voHage tolerance. When VCHKTL
goes below VBG, VTOL will be pulled low.
VCHKTH
I
Comparator input for monitoring supply voltage tolerance. When VCHKTH
goes above VBG, VTOL will be pulled low.
VTOL
OlD
When tow, this open-collector output indicates that either VCHKTL goes below
or VCHKTH goes above VBG.
V2PS
0
VoHagereference at 2.SV, generated from the intemal bandgap voltage.
IBR
0
A resistor is tied from this pin to ground to establish a bias current for internal
circuitry.
RCRST
OlD
This pin serves the dual purpose of providing power-bn-reset and stretching
short internal voHage fault pulses to a width suitable for the host micro
controller. An external RC network sets the minimum width of any SYSRST
pulse. If RCRST is pulled low by external circuitry, this device will enter into the
retract mode and pull SYSRST low.
SYSRST
OlD
When low, this open-collector output indicates that an internal voltage fault has
occurred.
OTSO
010
Thermal Shutdowrl. When low, this open-collector output indicates that the
junction temperature has exceeded the recommended operating range and
the device is in thermal shut-down. In thermal shut-down, all output drivers are
turned off and analog circuit de-biased.
I
Biased low with an internal pUlldo'jVn. When asserted high, RETR will be
connected to the thermal overload test circuitry for use as a test input.
THTEST
DESCRIPTION
SERIAL INTERFACE PORT
SOATA
I
Serial data input passing digital words for internal registers.
SCLK
I
Serial data timing reference. The rising edge of the SCLK is to strobe SOATA
while SOEN is asserted high.
SO~N
I
Serial data transfer enable. When active high, the serial data transfer is
enabled.
7-222
SSI32H6814
5V Servo/Motor Speed Driver
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Exposure to absolute maximum rating conditions for extended periods may cause permanent damage to
the device or affect device reliability.
PARAMETER
RATING
Supply voltage @
VPA, VPD, VVMP, VSMP
Vdd
Motor current @
VM1, VM2
A,B,C
Ivcm
Ispm
Input voltage @
CT,A,B,C,VBEMF, VBYP1,VBYP2
VM1, VM2, SE1 , SE2
All other pins
Storage temperature
±1A
±1.25A
Yin
-0.3 to 12V
-0.3 to 7V
-0.3 to Vdd + 0.3
Tslg
Lead temperature
-0.3 to 7V
Tlead
-65 to 150°C
oto 300°C
RECOMMENDED OPERATING CONDITIONS
The recommended operating conditions for the device are indicated in the table below. Performance
specifications do not apply when the device is operated outside the recommended conditions.
PARAMETER
Supply voltage
Supply current
VPA,VPD
VVMP
VSMP
Sleep mode
Input voltage @ VBEMF
Input voltage @ VIN
Input voltage @ ERREF
Ambient temperature
CONDITION
MIN
Vdd
_ Idd.
Ivmp.
Ismp
Isleep.
VBEMF
VIN
ERREF
Ta
MAX
UNIT
4.5
5.5
V
1
20
0.6
1
1
10
mA
A
A
mA
V
0
2.5
V
VBG/2
VBG
V
0
70
°C
100
pF
40
pF
kQ
Capacitive load on
digital outputs
CI
Analog output load
CI
RI
10
System clock fc = 10 MHz
fc
Frequency tolerance
Pulse Width
Twh, Twl
40
Biasing resitor,
Rbias = 22.6 kQ
Rbias
External resistors
Rf, Rc
10
7-223
NOM
±O.1
%
60
ns
±5
%
kQ
II
SSI32H6814
5V ServolMotor Speed Driver
ELECTRICAL SPECIFICATIONS (continued)
DIGITAL 110
PARAMETER
Digital input @ SDATA,SClK,SDEN
ADVANCE,SYSCLK,RETR
Vii
Vih
iii lih
Digital input @ BRAKE
Vii
Vih
iii IIh
Digital O/C output @
RCRST,SYSRST,OTSD, VTOl
loh
101
Digital output @ COM/REV
Vol
Voh
CONDITIONS
MIN
NOM
MAX
0.8
2
+1
1.2
2.4
±1
1
Voh=Vdd
Vol=O.4V
-4.0
101=2.0 rnA
loh=-100 uA
2.4
UNIT
V
V
uA
V
V
uA
uA
rnA
0.4
V
V
SERVO POSITIONER
The following VCM performance specifications are measured with 7.50 resistive load, unless otherwise
noted.
PARAMETER
CONDITIONS
VBYP1 current
Normal mode
Retract mode
Brake mode
Poweroff,VBYP1=3V
Poweroff,VBYP1=3V
BEMF current
Normal mode
Retract mode
SOUT amplifier
Gain
Input offset
Output swing
CMRR
MIN
MAX
UNIT
100
10
10
uA
uA
uA
300
10
uA
uA
4.1
±3
Vdd-l
VN
mV
V
0.15
±10
Vdd-l.2S
dB
MHz
mV
V
11
13
VN
VBEMF=4V
Power off, VBEMF=3V
VRETR=0.5V, VBYP1=4V
3.9
SOUT= ERREF
Rl = 10 kO to ERREF
ERRAMP amplifier
Gain
Unit gain bandwidth
Input offset
Output swing
0.15
NOM
60
1
Power amplifier gain
(VM1-VM2)/(ERR-VBG)
7-224
SSI32H6814
5V Servo/Motor Speed Driver
SERVO POSITIONER (continued)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Total voHage drop
across power FETs
Imotor=0.6A
0.9
V
VCM bridge crossover time
Ivcm=10 mA,peak step input
10
J.IS
VCM output THD
Ivcm=0.1 A,peak @ 100 Hz
2
%
SWIN on resistance
100
Q
Retract amplifier (normal)
VRETR leakage current
±1
llA
0
mV
Retract amplifier (retract)
VRETR input impedance
Offset
Maximum output current
VBEMF=1.0V
VBEMF=1.5V
VRETR=0.5V,VBEMF~1V
VBYP1=4.5V,VM1=VM2
VRETR=0.5V
500
-100
kQ
60
100
mA
mA
SPINDLE MOTOR COMMUTATOR/DRIVER PARAMETER
Input leakage current @ VIN
0:>:VIN:>:2.5V
+1
llA
Total voltage drop across
powerFETs
Imotor=1.0A
1
V
Rin @ A,B,C while not driving
-0.3V:>:Vin:>:7V
10
kQ
Rin @ CT while not driving
-0.3V:>:Vin:>:7V
3
kQ
2
V
CONTROL CIRCUITRY
Vdd voHage for SYSRST
& RCRST in operation
On resistance at RCRST
VBG
100
louk±0.2 mA
2.16
VCHK comparator offset
V2P5
louk±0.2mA
2.42
VCHKTL, VCHKTH
comparator offset
Thermal shutdown
temperature threshold
125
7-225
Q
2.3
V
+10
mV
2.58
V
+10
mV
145
°C
II
SSI32H6814
5V Servo/Motor Speed Driver
ELECTRICAL SPECIFICATIONS (continued)
OIl. CONVERTER
PARAMETER
CONDITIONS
MIN
Full-scale voltage
Resolution
NOM
MAX
UNIT
VBG
V
10
bits
4
Digital delay
~
VBG/1024
LSBvoltage
Differential nonlinearity
V
1
LSB
SERIAL INTERFACE PORT
The following timing measurements are made at 50% Vdd for all signals, unless otherwise noted.
SDEN setup time
prior to SCLK fall
Tsens
35
ns
$DEN hold time
after SCLK rise
Tsenh
50
ns
Tsl
200
ns
SDATA setup time
prior to SCLK rise
Tds
15
ns
SDATA hold time
after SCLK rise
Tdh
15
ns
SCLK pulse width
Tckpw
100
ns
SCLK high time
Tckh
.40
ns
SCLK low time
Tckl
40
SDEN low time
_....._-_._.
ns
,>
SDEN
SCLK
SDATA
FIGURE 2: Serial Interface Port Timing Diagram
7-226
SSI32H6814
5V Servo/Motor Speed Driver
PACKAGE PIN DESIGNATIONS
(Top View)
:I:
....I
:I:
:I:
t;: t;:
()
()
> >
$ &l
VCHK
~ fa
'"
CD
w
>
()
::;::
z w
....I
Z
0: Il'" c <> a::!l c ()en ::;::....I
w
z c
()
Il- >
c
~
~
~ > > > < 8 > en en en en
~ I~
10 ~
CD
III
~
co
III
"-
III
CD
III
v
tll III
<')
III
'"
III
in
0
III
~ 48
RETR
V2P5
2
47
BRAKE
IBR
3
46
VSMN
VNA
4
45
C
VRETR
5
44
VSMP
VBEMF
6
43
B
VVMN
7
42
VSMN
VM1
8
41
A
VVMP
9
40
VSMP
VM2
10
39
C
VVMN
11
38
VSMN
VM1
12
37
B
VVMP
13
36
VSMP
VM2
14
35
A
VVMN
15
34
VSMN
THTEST
16
33
SENSE
"-
w
co
~
en '"
en
W
CD
~
I-
:l
g
v
'" '"'" '" '"
a: Cl
a: III
w >
u.
:::iE
z
CD
~
<')
~
()
<
I
'"
:::iE
()
Z
ll-
w
Il- 0
:::iE
§
a: a:
c :> <
> () <
a: a: en ~
Ilen
a:
~
w w
a:
l-
()
U.
w
a:
z
w
en
64-Lead TQFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
«:>1994 Silicon Systems, Inc.
7-227
0194
Notes:
7-228
SSI32H6820
Servo/Spindle
Predriver
§ Nii Um mt.,,; Ib" t" ;.
November 1993
DESCRIPTION
FUNCTIONAL DESCRIPTION
The SSI 32H6820 is a CMOS monolithic integrated
circuit housed in a 64-pin TQFP, operates from a single
+5V supply and provides control signals for external
FET drivers operating on 5 to 12 volt supplies. In
addition to supporting disk drives with embedded servo
sectors, it contains all timing and control functions
necessary to start, drive, and brake a 3-phase, 4-, 8-,
12-, 16-pole brushless DC spindle motor without
sensors. The circuit is controlled via the Silicon
Systems standard 3-wire serial port.
As shown in Figure 1, the SSI32H6820 can be divided
into four major sections: servo head positioning control,
spindle motor speed control, digital control, and
miscellaneous functions.
FEATURES
SERVO HEAD POSITIONING CONTROL
The SS132H6820 is intended for a servo head positioner
for disk drives with embedded servo sectors. The head
positioning control section contains the following
sections: servo position error amplifier, H-bridge
MOSFETpre-driver, actuator current sense, and voltage
fault detection and servo head retract.
Servo Head Positioning Control
Servo control for embedded servo head
positioning systems
H-bridge MOSFET pre-driver for linear and
rotary voice coil motor
Class B linear mode and constant voltage
retract mode
Active head retract on power failure
Spindle Motor Speed Control
3-phase 4-, 8-, 12-, 16-pole bipolar/unipolar
operation without need for sensors
Programmable precision speed regulation 2Jls
speed resolution
"At speed" indication
Motor peak current limiting function
Pulse amplitude modulation (PAM) for bridge
MOSFET drivers
Dynamic braking function on power failure
General Functions
Voltage fault detection fortwo supply voltages
low power CMOS design, two low power idle
states
Three wire serial control interface
8 bit Digital-to-analog converter for voice coil
control
Available in 64-lead TQFP package
1193
SERVO POSITION ERROR AMPLIFIER
The servo driver has two modes of operation, linear
and retract. The retract mode is activated by a power
supply failure or when the control signal RETRACT is
low. Otherwise the driver operates in linear mode.
During linear operation, the microcontroller acquires
servo burst amplitudes and analyzes them to establish
a position error signal. The microcontrollerdevelops a
digital error signal which is sentlo the 8-bit D/Aconverter
(with output ERRDAC and reference ERRREF) and is
applied to an amplifier whose three connections, ERRM,
ERRP and ERR, are available externally. External RC components may be used to establish the gain and
bandwidth of this amplifier. Additional analog input via
SWIN may be provided to this amplifier by setting the
SWON bit in the SERVO CONTROL register.
H-BRIDGE MOSFET PRE-DRIVER
The error signal ERR generated from the position error
amplifier drives two precision differential amplifiers,
each with a gain of 15. The differential amplifier outputs,
AOUTA, AOUTB, AOUTC and AOUTD drive an external
MOSFETbridge powered by VBRIDGE. Feedback
from the MOSFET drain terminals via sense inputs
SE1 and SE3 allow the differential amplifier gains to be
established precisely. The voice coil actuator and a
current sense resistor are connected in series between
SE1 and SE3. Included in the output control circuitry is
a crossover protection function which ensures class B
operation by permitting only one MOSFET in each leg
of the bridge to be in conduction. The crossover circuit
can be adjusted for different MOSFET threshold
voltages with a resistorconnectedto VX. The crossover
7-229
II
SSI32H6820
Servo/Spindle
Predriver
YPO
YPA
EXTRG
==="'-' llUT1JI'A
·.... ·••.·•· •.• ··Y'1-++f~APPiD
COILA
1.'=lA==""=LJ 00TUPl!
" ' 1 4 + b b F b i D COILB
kP±'t'iD 15O'TUl'C
RRAMP
VBRAKE
H4841£J
OlIrA
PHP'*H.J
OlIrB
···.""'4=-=bb"O COMP
ERROAC ~~~=-~~~~~~~--~~-l4-
__ CK.·.·
ERRo-~~~...,
ERR REF
f+-~+C-rl.J
Sf~~=~~+-~=~=~~~--~
,""',.UHIIV.I+PP-rl.J
:::~::]~~~~~~~~~~~~~~~~4
SEl
AOlIrA
I+-bbHJ AOlIrB
SWIN
1+=-=--rl.J
AOlIrC
1+=~-rl.J AOlIrO
SCLK
r\:;"';.:L:LL"+~77~7'7Jd7K77~~="L.
l+-"7bHJSE3
SOATA
r-~"':,-,----u
SOEN
VREF
VBEMF
• . •,iy;cSC+4~ VBYP
Q;.tc+==-+4H~~:""1
21: ~==-=-.qJ
AOlIrR
IBR Lb=-=-=-=---'+""1
c:==========f=::~~~:g~~===f~~
VCHK1
VCHK2
~
l1l:I1ST
lY-=,..~~-'7-"p..~
=
.L;-."'4bb=-HJ VRETR
.
[};--=,..--+-~.,.-'-.,.-'--~-.,.-'-~ .•. .
VNO
VNA
Figure 1: 551 32H6820 Block Diagram
SSI32H6820
Servo/Spindle
Predriver
FUNCTIONAL DESCRIPTION (continued)
SPINDLE MOTOR START·UP
H·BRIDGE MOSFET PRE·DRIVER
Motor starting is accomplished with the IlP utilizing
various features contained in the motor speed control
circuitry. The IlP can write to the commutation counter
and set it to a predetermined value with STATO, STAT1,
STAT2 bits. The counter can then be incremented with
the ADVANCE pin which also excludes internal
commutations when held HIGH. Bit REVCOM informs
the IlP on motor activity. The IlP can enable the drivers
with MEN and UNI bits as required.
(continued)
circuitry can be commanded by the IlP to shut down the
MOSFET drivers and thus remove currentto the external
bridge.
MOTOR CURRENT SENSE
Motor current is sensed by a resistor placed in series
with the actuator. The voltage drop across the resistor
is level-shifted and amplified by adifferential amplifier
with a gain of 4. The resulting signal, SOUT, is
proportional to actuator current. This signal is externally
fed back to the position error amplifier so that the error
signal ERR represents the difference between the
desired and actual actuator currents.
VOLTAGE FAULT DETECTION AND SERVO HEAD RETRACT
During retract, a constant voltage is applied across the
actuator in order to cause a constant velocity head
retraction. This is accomplished by applying the voltage
stored on VBYP to AOUTD and by driving AOUTR with
an amplifier that monitors SE1. The amplifier is powered
by VBEMF. During retract, VRETR is biased by an
intemal voltage reference and determines the retract
voltage. Atother times, power is saved by disconnecting
VRETR from the voltage reference and letting it be
pulled to VBEMF by a high value resistor. External
components (a diode, for instance) can be connected
between VRETR and ground to modify the retractvoltage.
An .open-drain output, SYSRST, which is active low
while the servo driver is in retract mode, is provided for
spindle motor braking. An external R-C delay may be
used to defer braking until the head is retracted. The
minimum duration of SYSRST being active low is
determined by the extemal capacitor which is connected
to pin RCRST.
SPINDLE MOTOR SPEED CONTROL
In conjunction with several external components,the
spindle motor speed control provides the starting,
accelerating, and precise rotational speed regulation
functions. The circuit will control 4-, 8-, 12-, or 16-pole
brushless DC motors withoutthe need for Hall sensors;
It will operate in either bipolar or unipolar drive mode.
Control, configuration, and status monitoring are
handled by a companion ASIC orllP. The complete
speed control loop is contained in the circuit and the IlP
is only required during start and to monitor status.
7-231
Under IlP control, initial open-loop commutation
sequence is provided to the commutation logic which
thereby advances and accelerates the spindle motor.
The start-up process settles the motor initially by
selecting the bits STATO, STAT1, STAT2 in Register 0
to energize a proper motor winding. Motor current is
enabled by setting the MEN bit in Register O. The
commutation state is advanced by raising the
ADVANCE pin. The period between ADVANCE pulses
will be based upon the motor and load characteristics
and decreased gradually during the acceleration of the
motor. The IlP may look atthe REVCOM pin information
indicating whether the motor has achieved a sufficient
speed. Once the motor has achieved a sufficient speed,
ADVANCE is held low and the motor will accelerate to
target speed.
Motor rotor position is determined by monitoring the
coil voltage of the winding that is not presently being
driven by the drivers. The back-emf at the coil in
conjunction with the state of the output drivers indicates
rotor position. The back-emf is compared to a reference
at CT and initiates "commutation events" when the
appropriate comparison is made. Commutation is the
sequential switching of the drive current to the motor
windings. Since the back-emf comparison event occurs
prior to the time when optimum commutation should
occur, it is thus required to delay actual commutation
by a predetermined time after the comparison. The
commutation delay is provided by a non-retriggerable
one-shot circuit wherein the time delay is a function of
external R-C timing components connected at EXTRC.
Because commutation of the motor windings typically
results in large transient voltages which could falsely
indicate "commutation events," the one-shot circuit
also provides a "noise filter" function which holds off
retriggeringfurther and blanks the back-emf comparison
events for a period of time (approximately one half the
commutation delay) after commutation (Figure 3). The
commutation states are defined inTable 4.
II
SSI32H6820
Servo/Spindle
Predriver
FUNCTIONAL DESCRIPTION (continued)
SPINDLE MOTOR SPEED REGULATION
Motor speed regulation is accomplished with mixed
analog and digital techniques, converting a motor
speed error derived from a reference clock and a
period counter into a voltage. The voltage translates
into a motor current across the current sense resistor
regulating the motor speed. The speed regulation loop
consists of a period counter, proportional and integral
channels, two 6-bit D/A converters and a linear
transconductance amplifier.
In .operation, the motor speed error is determined by
measuring the period of each revolution with a500 kHz
clock signal. Period resolution is therefore 2 J.lS with the
desired period being given by:
period = (load count + 6) • 2.0 J.lSec
Both register 3 and register4 must be written, in order,
via the serial data interface to accomplish writing a new
period value.
The period counter is loaded with the desired count
initially, and period measurement results in residual
counts (ideally zero) in the period counter as it counts
down during the index-to-index time interval. The
residual count is fed to the proportional D/A converter
(5-bit plus sign) whose output is provided at PROP. No
perioderrorwilloutput half of VB lAS at PROP, too short
a period will output a value less than half of VB lAS, and
too long a period will output a value greater than half of
VBIAS depending on the amount of error. When the
residual count is within ±15 counts of zero, the motor is
indicated as "in lock." The lower eight bits of the period
counter are fed to an accumulator which adds the
present period residue to the previous accumulation
thus accomplishing an integrating effect to force the
speed error to zero over time. The upper six bits of the
accumulator are fed to the integral DAC whose output
is INTEGRAL. Gross period errors will cause PROP
and INTEGRAL to saturate at the appropriate extreme
to achieve the maximum corrective control voltage.
The outputs at PROP and INTEGRAL are connected to
VIN with an external resistor network. The outputs of
the proportional DAC and Integral DAC give coefficients
given by:
Kp = (RPS·2)/(2.35v/64)/4ne-6)
K, = (RPS·')/(2.35v/64)/(16ne·6 )
(RPS is the desired motor speed in revolutions per
second.)
The resistor values should be selected to modify the
coefficients given above to values required for proper
loop response based upon motor requirements. The
input VIN is the non-inverting input of the linear
transconductance amplifier which uses the lower driver
transistor that is presently active per the commutation
state. An external resistor is used to sense the current
flowing through the drive transistor drain (and hence the
motor coil current). The voltage across the sense resistor,
the difference between SENSE and SENSEREF, is
amplified by a programmable gain stage and fed to the
inverting input of the transconductance amplifier. The
gain of the programmable amplifier is determined by GO
and G1 bits.
MOTOR PEAK CURRENT LIMITING
When the period error exceeds 256 counts too slow, the
voltage at VLlM is selected as the control voltage in lieu
of VIN. VLlM is to be used to set the motor peak current
during start-up and acceleration. The motor current is
limited to a value such that the voltage across the sense
resistor (SENSE - SENSEREF) times the gain of the
sense amplifier (5, 10, 15, 20) is equal to VLlM.
MOTOR BRAKING
Fault conditions on power supplies and internal voltage
reference generator will trigger an internal retract
condition. The internal retract condition will cause all
pre-driver outputs to the states which will tu rn the driver
transistors off, allowing the motor to coast. BRAKE
typically has a capacitor to ground attached and is
connected to pin SYSRST via a resistor. SYSRST
goes low in the retract condition, and thus BRAKE will
go low after the R-C delay. When BRAKE goes low, all
external N-FETs are activated to achieve dynamic
braking of the motor. The circuitry for these operations
is powered by voltage on VB RAKE stored on an
external capacitor.
DynamiC braking can also be activated under external
serial port control by setting BRK to HIGH in REG O.
During dynamic braking, the control loop is opened.
EXTERNAL INDEX APPLICATION
Normal operation is performed with an internal index
signal derived from the commutation counter (scaled
via the MOand M 1 bits based upon the numberof motor
poles). For both an internal "index" or External Index,
the period between index signals is measured as
described above and used to control the PROP and
INTEGRAL outputs.
7-232
SSI32H6820
Servo/Spindle
Predriver
DATA CONVERSION AND SERIAL INTERFACE
MISCELLANEOUS FUNCTIONS
An a-bit D/A converter which runs synchronously with
the internal 500 kHz clock is provided. The converter
is 2's complement format (7 Fhex is positive full scale,
80 hex is negative full scale and Reset condition is 00
hex, midscale). Conversion is started by writing to the
D/A register address, Register 2. The output of the DI
A converter is ERRDAC and is referenced to ERREF.
The output is held constant between data loads. The
circuit is configured and controlled via the Serial data
inputs in accordance with the standard Silicon Systems
Serial interface Specifications.
The miscellaneous functions include generating the
reference voltages VREF and VBIAS, and the voltage
fault detection circuits which activate power fault retract
and braking operation. A voltage fault detector which
can monitor two voltage supplies is included to prevent
the actuator from responding to a false error signal
during a power failure. Retract mode is started when a
power supply failure is sensed by the VCHK1 orVCHK2
comparators orwhen RETRACT is pulled low externally.
Per the timing diagram (Figure 2), data are clocked into
the serial port on the rising edge of SCLK. It is required
that 16 data clocks be used for all transfers for proper
operation. The data are loaded from the serial interface
to the destination registers (controlled parameter) when
SDEN is lowered signalling the end of serial data transfer.
The internal bias currents for analog functions are set
by an external resistor connected between IBR and
ground. A 23.7 kil ±1% resistor should be used for
proper operations.
TABLE 1: Serial Data Format
Data bit 1
R/W control - must be a 0, this circuit is write-only
Data bit 2
Circuit ID bit - must be 1
Data bit 3
Circuit ID bit - must be 1
Data bit 4
Circuit ID bit - must be 1
Data bit 5
Register address bit 0
Data bit 6
Register address bit 1
Data bit 7
Register address bit 2
I
Data bit a
Register address bit 3 - not used, 1 or 0 allowed
Data bit 9
Register data bitO
- - I--~------.-----------------.-------
Data bit 10
Register data bit 1
Data bit 11
Register data bit 2
Data bit 12
Register data bit 3
Data bit 13
Register data bit 4
Data bit 14
Register data bit 5
Data bit 15
Register data bit 6
Data bit 16
Register data bit 7
7-233
---
---_._----- - . .
. .- - - -
-------~-----
"'Doooo
~(I)OO
TABLE 2: Operating Modes
MODE
SLEEP (1)
VFAULT
condition
X
RETRACT
PIN
X
BRAKE
PIN
X
SLEEP
BIT
1
HEN
BIT
X
MEN
BIT
X
BRK
BIT
X
pas
driver
float
(I)~-
SPINDLE
driver
o.18V
IBEMF
Signal pins
VMAX
Storage temperature
Tstg
Lead temperature
Tlead
0.1 to 18
0.1 to 14.0
0.1 to 14.0
5.0
-0.3 to VDD + 0.3
-65 to 150
300
OPERATING ENVIRONMENT LIMITATIONS
The recommended operating conditions for the device are indicated in the table below. Performance
specifications do not apply where the device is operating outside these limits
PARAMETER
MIN
NOM
MAX
UNIT
VDD
CONDITIONS
4.5
-
5.5
V
VBRIDGE
4.5
-
13.2
V
Ta
0.0
-
70.0
°C
System clock
Fc
3.92
4
4.08
MHz
Capacitive load
CL
100
pF
-
kQ
Supply voltage applied
at VPA,VPD
Bridge voltage
applied at VBRIDGE, VM
Ambient temperature
VM
digital outputs
Analog input impedance
100
Rin
7-241
-
SSI32H6820
Servo/Spindle
Predriver
ELECTRICAL SPECIFICATIONS (continued)
OPERATING ENVIRONMENT LIMITATIONS
PARAMETER
(continued)
MIN
NOM
MAX
UNIT
Cin
-
-
20
pF
Rout
10
-
-
kQ
Cout
-
-
40
pF
CONDITIONS
Load on analog outputs
23.7 ill
RBIAS
Bias resistor
±1
%
DC CHARACTERISTICS
The following electrical specifications apply to the digital input and output signals over the recommended
operating range unless otherwise noted. Positive current is defined as entering the device. Minimum and
maximum are based upon the magnitude of the number.
IDD
Supply current
VDD = 5.5V
-
SLPO
-
-
SLP1
Supply current
on VBRAKE
IBRK
VB RAKE = 12V
VDD = OV
Supply current
on VBVP
IBVP
VBVP = 12V
Output logic 1
Voh
. loh = -0.4 mA
VDD = 4.5V
Output logic 0
Vol
30
mA
15
mA
50
llA
-
-
25
25
llA
llA
2.4
-
-
V
-
-
0.4
V
--
- - - - - - - ..-
101=1.6 mA
VDD=4.5V
-"--,--------
Input logic 1
Vih
VDD=4.5V
2.0
-
V
Input logic 0
Vii
VDD=4.5V
-
0.8
V
Input logic 1 current
lih
Vih=5.5V
VDD=5.5V
-
-
10
llA
Input logic 0 current
iii
ViI=O.O
VDD=5.5V
-
-
-10
llA
-
-
10
pF
Input capacitance
---
Cin
7-242
SSI32H6820
Servo/Spindle
Predriver
FUNCTIONAL CHARACTERISTICS
Head Positioner MOSFET Driver
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
VRETR voltage
VBEMF= 3V
0.3
0.9
V
VBEMF = 12V
0.4
-
1.2
V
VBEMF=3V
VRETRACT = 0.5V
-70
50
mV
VBEMF = 6V
VBYP = 4V to 13V
-70
70
mV
VBEMF = 12V
IAOUTR < lmA
-150
-
150
mV
loh= -1 mA
VBEMF =4V
VBYP =4V
1.5
-
-
V
VBEMF =3V
VBYP =4V
1.3
-
-
V
1
(JA
Retract offset
Voh at AOUTR
Leakage current at AOUTR
Voh at AOUTA, AOUTC
RETRACT = LOW
AOUTR = OV to 14V
-
loh = -1 mA
VBRIDGE·1.5
loh = -1 (JA
VBRIDGE .c.l
-
V
V
Vol at AOUTA, AOUTC
101 = 10 (JA
-
1
V
Voh at AOUTB
loh = -10 (JA
VBRIDGE ·0.5
V
Voh at AOUTD
loh = -10 (JA
VBYP ·0.5
-
Vol at AOUTB, AOUTD
101 = 1 mA
1
V
-
-
101 = 10 (JA
-
Input offset at SOUT
SOUT/(SE1-SE2)
3.9
SE1IERR, SE3/ERR
14.0
ERRAMP input offset
-
-
mV
4.1
VN
15.4
VN
±10
mV
-
VN
-
45
I!S
-
-
kQ
350
Q
-
600
Q
-
100
Input impedance at SE1, SE2, SE3
20
-
Analog switch on-resistance at SWIN
-
Output resistance at ERR
-
"
TBD
7-243
V
±3
1000
Output resistance at SOUT
Output current from VX
0.2
-
ERRAMPgain
Output crossover time PFET VTH =-2V
CL =600 pF at AOUTA,C NFET VTH =2V
CL =150 pF at AOUTB,D RX =50 k.Q
V
Q
(JA
II
SSI32H6820
Servo/Spindle
Predriver
ELECTRICAL SPECIFICATIONS (continued)
FUNCTIONAL CHARACTERISTICS (continued)
Voltage Reference and Voltage Fault Circuit
PARAMETER
CONDITIONS
MIN
NOM
2.0
VPA voltage for SYSRST
& RCRST in operation
On resistance at RCRST
VPA> 3.5V
VBRAKE > 4V
VPA> 3.5V
VBRAKE> 10V
RCRST input threshold VBRAKE = 4\1
IBR voltage w.r.t. VREF
--
Output vOltage at VREF IILI < 10 !lA
--
VCHK1, VCHK2 comparator offset
MAX
UNIT
-
V
-
-
800
11
-
-
550
11
0.8
2.0
V
-80
-
20
mV
2.28
2.35
2.42
V
2.25
-
2.45
V
40
-
60
%
200
-
-
ns
3
-
-
/lS
10
M11
-
Spindle Motor Speed Control
SYSCLK duty
_. cycle
EXTINDX pulse width
- - _._--_.
Advance pulse width
Timing resistor at EXTRC
0.01
Timing capacitor at EXTRC
100
.--.
Delay time variation relative to TO
"---.--~-
Vii at BRAKE
Vih at BRAKE
..
--.~.-
pF
±5
%
0
-
0.8
V
2.0
-
..
= 5V
. -r---.
VBRAKE = 5V
..... _._--_......-
- - - - - - - - - - - - - - - f---
lout < 0.1 rnA
_ ... _._-_._._.._.- r " ' - ' - - ' - ' - " - ' - " - ' - - -
DAC step size at PROP,
INTEGRAL
-
_.... _._-_._._._--_ _ - _ . _ . - 1 - - -- _ .
VBRAKE
Output voltage swing at PROP
& INTEGRAL
-
---~-,-"-"'.---
0
1---_._---
33
- - f---..
Output impedance at PROP,
INTEGRAL
0.5V < Vout < 2.0V
lout = 0.1 rnA
- - - - - - r---'
Input voltage at VIN & VLlM
Input leakage current at
VIN & VLlM
V
40
mV
300
11
..- - .
-
-
-
-50
-
25
mV
0
-
2.35
V
-
-
±1
JlA
--
--,---
VBIAS
±5%
f - - - . - - ,...---'
---- - - - _ . _ - - - _ .
VBIAS output w.r.t. VREF
--~-
-
V
• NOTE: TO is the commutation delay and is given by the relationship TO = 0.56RC. Suggested value for
C would be 470 to 1000 pF. An external Rand C must be provided such that TO is greater than 10 /lS (R
= 22 k11, C = 470 pF).
7-244
SSI32H6820
Servo/Spindle
Predriver
Spindle Motor Speed Control
(continued)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Output resistance at
OUTUP (A,B,C) & OUTCT
Output HIGH
pulled to VM
5
-
20
kQ
Vol at OUTUP (A,B,C) &
OUTCT
lout = 3mA
VM = 13.2V
-
1.0
V
Voh, OUT (A,B,C)
Vpd=5V, Vm~6V
lout = -50 !lA
Vol at OUT (A,B,C)
Input voltage at SENSE
--
4.5
-
lout = 1 mA
V
1.0
V
0.5
V
-_.
0.0
Av = 5
V
O.OV < Vin < 1.0V
-
-
0.05
Input leakage current
at SENSE
±10
!lA
Input leakage current
at SENSE REF
O.OV < Vin < 0.05V
-200
-
10
!lA
-
-
20
pF
-
±10
%
-
kQ
-
-
10
pF
30
-
-
kQ
-
10
pF
-30
+30
)lS
0.0
Input voltage at SENSEREF
Input capacitance at
SENSE & SENSEREF
Gain variation
-
Input impedance at COIL(A,B,C)
Av = 5,10,15,20
-0.3V < Vin < 15V
Input capacitance at COIL(A,B,C)
Input impedance at CT
Input capacitance at CT
-
LOCK indication range
.-
-~----.------.-~-~--
100
------- _"- - - - ..
Speed resolution
2
)lS
The motor speed control loop can be described as: H(s)=Kp+Ki/s
The transconductance gain from VIN or VLlM to the steady-state current flowing through the motor is given by
G = 1/(RSENSE • AV)
Error D/A Converter
ERRDAC full-scale voltage
swing w.r.t ERREF
-
±(VREF/2)
-
V
Resolution
-
8
-
Bits
Conversion time'
-
4.0
)lS
LSB voltage
mV
-
VREF/256
1.568
1.616
1.664
V
-
±5
mV
Differential linearity error
-
-
±0.75
LSB
Relative accuracy"
-
-
±1.0
LSB
±0.5
LSB
Output voltage at ERREF
ERRDAC offset w.r.t. ERREF
-
Power supply sensitivity
7-245
SSI32H6820
Servo/Spindle
Predriver
ELECTRICAL SPECIFICATIONS(continuedj
Error DIA Converter (continued)
"A maximum of 4 jJS of latency between a conversion request and the actual start of conversion must be added
to this conversion time of 4 jJS to calculate the total delay time from a conversion request to the completion of
conversion.
""Relative accuracy is the deviation of the analog value at any code (relative to the full analog range of the Of
A transfer characteristic) from its theoretical value (relative to the same range). after the full-scale range has
been calibrated.
Serial Data Interface
PARAMETER
CONDITIONS
SDEN enable to SCLK delay
Tsens
SOEN hold past SCLK
Tsensh
SDATA setup
Tds
SDATA hold time
Tdh
SDATA address word
to data word
Tad
SCLK cycle time
MIN
-
Tc
SCLK width low
Twcl
SCLK width high
Twch
---- - -
NOM
MAX
35
40
15
15
ns
40
100
40
40
ns
ns
ns
ns
ns
ns
ns
SDEN
Tsensh
SCLK
SDATA
f-FIGURE 2: Timing Diagram
UNIT
Data
word-.f
SSI32H6820
Servo/Spindle
Predriver
EXTRC
(EXTERNAL RC
ONE-SHOT
TIMING SET)
L ________
NB
SOS
_~_L=t=
MOTOR COIL
(ONE OF THREE PHASES)
(BIPOLAR OPERATION)
__""",---' .....1 - - - -
COMMUTATION
,---::::::::::::::;;::::c'!w.'w. . .", . . . . ,. . . . . . . .
BACK EMF CROSSING POINT
COMMUTATION
.L ______ _
-- - NB
T ..--------'
SOS _____..-
J- - -
BACK EMF CROSSING POINT
CD
..
COMMUTATION
COMMUTATION
BACK EMF CROSSING POINT
COMMUTATION
NB = NOISE BLANK = 0.29 RC
SO-S = START ONE-SHOT
CD = COMMUTATION DELAY = 0.56 RC
FIGURE 3: One-Shot Commutation Delay Timing Diagram
7-247
SSI32H6820
Servo/Spindle
Predriver
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
w
"-
'a:"
0
>- OJ Ui ~ Sl x
~ > en en en >
....::J'" ....:::0OJ g::J
~ f!' 0en en
w w
"
VRETR
ERRP
VBEMF
47
SYSCLK
46
ERRDAC
VND
45
IBR
VREF
ERREF
BRAKE
44
RCi'iS'i'
43
VCHKl
S'i'SliS'f
42
VCHK2
RETRACT
41
VNA
SDATA
40
EXTRC
SDEN
10
39
NCI
SCLK
11
38
VBIAS
ADVANCE
12
37
PROP
EXTINDX
13
36
INTEGRAL
REVCOM
14
35
VLlM
LOCK
15
34
VIN
VPD
16
33
COMP
17 18 19 20 21
~
o ~ "a
:'j ;5
::J
0
22 23 24 25 26 27 28 29 30 31
32
g g
LL
~
~
u
a
§;
i5
u
::J
0
UJ
"'"~ "> ~
a:
OJ
>
W
UJ
en a:
Z
w UJ
en !{,!
UJ
en
54-Lead TQFP
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other
rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems.
Silicon Systems reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the data sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1193
7-248
©1993 Silicon Systems, Inc.
SSI32H6825
Servo and Spindle Predriver
aNuugMt,'I;,kUt.".
January 1994
DESCRIPTION
FEATURES
The Servo and Spindle Predriver (SSP) is designed to
drive a 3-phase hall-sensorless motor and a voice coil
actuator with external MOS power devices.
•
•
Improvements to the actuator driver include a window
comparator to quickly catch high currents caused by
power FET failure in the actuator bridge, an
uncommitted opamp for use in a notch filter, and
reduced power dissipation.
•
•
Improvements to the spindle driver include significantly
reduced power dissipation, a IJ.P controlled start up
ramp to replace the imprecise analog ramp, an external
PWM input to allow PWM frequencies above the
audible range, active pu"up on the P driver, adjustable
N-channel slew rate, and improved spindle brake
performance.
•
•
•
Spindle driver is PWM during run and start
Commutator Is driven by a phase lock loop for
high jitter Immunity
Significantly reduced power dissipation
Adjustable slew rate to minimize stress In the
powerFETs
Microprocessor controlled spindle start up
Window comparator to monitor actuator
bridge fault
Small footprint 48-lead TQFP package
PIN DIAGRAM
VREF
Nl
4B 47 46 45 44 43 42 41
1.
40 39 3B 37
36
2
OUTe
A3N
OUTO
RBK
NlP
R8RACf
~
SE3
CBRAKE
6
RSR
PH3
B
P2
P3
evco
P1
PH2
9
PH1
10
N1
Rveo
Re
11
N2
12 13 14 15 16 17 1B 19 20 21
22 23
N3
48-lead TQFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
0194 - rev.
7-249
II
SSI32H6825
Servo and Spindle Predriver
BLOCK DIAGRAM
RIN
POSIN
RF
o------..JV'--....- - - - - - - - - v " V ' - - - - - - - ,
RC
CC
7-250
SSI32H6825
Servo and Spindle Predriver
FUNCTIONAL DESCRIPTION
ACTUATOR
The actuator section consists of A 1 through A5, the
window comparator, the VREF check, and the XOVER
blocks. It is functionally identical to the SSI 32H6231.
During linear operation, an acceleration signal from the
servo controller is applied through amplifier A 1, whose
three connections are all available externally. RC
components may be used to provide loop compensation
at this stage. The ERR signal drives two precision
amplifiers, each with a gain of 8.5. The first of these
amplifiers is inverting, and is formed from opamp A4,
an on-chip resistor divider and an off-chip
complementary MOSFET pair. The second is noninverting, and is formed in a similar manner from
opamp A5. Feedback from the MOSFET drains, on
sense inputs SE1 and SE3, allows the amplifiers gains
to be established precisely. The voice coil motor and a
series current sense resistor are connected between
SE1 and SE3.
Crossover protection circuitry between the outputs of
A4 and A5, and the external MOSFETs, ensures class
B operation by allowing only one MOSFET in each leg
of the H-bridge to be in conduction. The crossover
separation threshold, illustrated in Figure 1, is the
maximum drive on any MOSFET gate when the motor
voltage changes sign. The crossover circuitry can also
apply a constant voltage across the motor (to retract
the heads at a constant velocity).
Motor current is sensed by a small resistor placed in
series with the motor. The voltage drop across this
resistor is amplified by a differential amplifier with a
gain of 4 (A2 and associated resistors), whose inputs
are SE1 and SE2. The resulting voltage, SOUT, is
proportional to motor current, and hence acceleration.
This signal is externally fed back to A 1, so that the
signal ERR represents the difference between the
desired acceleration (from the servo controller) and the
actual motor acceleration.
SOUT is connected to a window comparator, which is
used to detect excessive motor current. When excessive
current is detected, WRPROT is pulled low. The VLlM
pin may be used to program the voltage limit for the
window comparator. The maximum voltage excursion
allowed about VREF is (VREF-VLlM). An on-Chip
resistor divider sets a default value for VLI M and if VLI M
is connected to ground, the windowing is effectively
disabled.
The SSI32H6825 has low voltage monitor circuitry that
will detect a loss of voltage on VREF. The power supply
pin, VP, should be connected to the disk drive's spindle
motor so that its stored rotational energy may be used
to hold up VP briefly during a power failure . When a low
voltage condition is detected, the MOSFET drivers
switch from linear operation to retract mode. In this
mode a constant voltage is applied across the motor
which will cause the heads to move at a constant
speed. A mechanical stop must be provided for the
heads when they reach a safe location.
The spindle driver monitors spindle back EMF and
generates drive signals to 3 MOSFET power bridges.
This section includes current limit, a back EMF
monitoring circuit to determine commutation points, a
phase locked loop to remove jitter from the commutation
times, and a delayed spindle brake circuit.
COMMUTATOR
The commutator drives the spindle motor windings in
the proper sequence to operate the 3 phase spindle
motor. In Run mode, the commutator is clocked by
ClK, the VCO output. In Start mode, the commutator
is clocked by external pulses applied to the ADVANCE
pin. Table 1 shows the commutator sequence and
identifies which power FETS are on.
The commutator phase detector technology is licensed
from Synektron, patent no. 4,928,043.
7-251
II
SSI32H6825
Servo and SpindlePredriver
MOSFET GATE DRIVE
VCC -
- - - - -
-
__ - I. _ _ _ _ _ _ _ _ _
I
VCC - VTH _ _ _ _ _ _
(CROSSOVER
SEPARATION
THRESHOLD)
VTH - - - - - -
ERR
(ERROR SIGNAL INPUT)
VREF
(HORIZONTAL SCALE IS GREATLY EXPANDED)
FIGURE 1: Crossover Protection
Table 1· Commutator Sequence
STATE
N1
N2
N3
P1
P2
P3
RST
OFF
ON
OFF
ON
OFF
ON
A
OFF
OFF
ON
ON
OFF
OFF
B
OFF
OFF
ON
OFF
ON
OFF
C
ON
OFF
OFF
OFF
ON
OFF
0
ON
OFF
OFF
OFF
OFF
ON
E
OFF
ON
OFF
OFF
OFF
ON
F
OFF
ON
OFF
ON
OFF
OFF
PHASE ERROR AMPLIFIER
The PHASE ERROR circuit compares the undriven winding with the average of the other two voltages. Depending
on the result of the comparison and the state of the commutator, a positive or negative current is put out on the
RC pin. Table 2 shows which winding is undriven and which polarity of current is output when that winding is
positive with respect to the average of the other two.
Table 2: Undriven Winding and Polarity
Commutator State
Undriven Winding
Polarity
A
PH2
Source
B
PH1
Sink
C
PH3
Source
--
D
PH2
Sink
E
PH1
Source
F
PH3
Sink
7-252
SSI32H6825
Servo and Spindle Predriver
FUNCTIONAL DESCRIPTION (continued)
ONE SHOT
PHASE ERROR AMPLIFIER (continued)
The one shot is triggered whenever ISENSE exceeds
VLlMIT (nominally 0.1V). When the one shottimes out,
it will remain high if ISENSE is still above VLlMIT.
During the time the one shot output is high, the N
drivers are turned off. This behavior implements PWM
over-current limit, where the peak current is VLlMITI
The PHASE ERROR circuit is only used when mode =
RUN. In all other modes, RC is forced to VIOL ' an
internally generated voltage that will cause the veOto
idle at approximately 1/20 of the run rate.
The magnitude of the current at RC is the sum of a
constant cu rrent and a current proportional to the VCO
frequency. The constant current value is set by RPH
which is biased to 1.2V nominally. The proportional
current is set by RVCO, the same resistor that controls
the VCO current. The RVCO pin is nominally the same
voHage as the RC pin.
VCO
The VCO is a triangle wave oscillator with a wide
frequency range set by RVCO and CVCO. The voltage
swing on CVCO is nominally 2.2V. The frequency
formula is:
Fv
CO -
VAC
8.8 RvcoCVco
The VCO is reset if ENABLE = 1 and RESET = O.
During VCO reset, the ClK output is forced low. The
first VCO clock will occur immediately on exiting reset.
This timing relationship is shown in Figure 1.
RSTVCO
RMS '
VOLTAGE REFERENCE
The voltage reference circuit generates voltage and
current references for the rest of the MSC section.
Specifically, these voltages are3.3V, VRETRACT, and
VLlMIT. The circuit als6generates the bias voltage:
1.2V + Vbe (40 ~).
NOUT AND POUT
The NOUT drivers drive the gates of the N channel
power FETs. They have an adjustable source current
set by RSR" During BRAKE, the NOUT drivers are
disabled and all N channel power FETs are turned on.
The POUT drivers drive the P channel power FETs.
The POUT drivers are not deactivated during PWM.
DIGITAL INPUTS
All digital inputs are pulled to ground with a 20 kn
(nominal) resistor to ensure a known state during
system power failure.
----------~
CVCO
vce
ADVANCE
~------________________~
NOTE: RSTVCO = ~. ffi:SEi
FIGURE 2: veo Timing Diagram
7-253
SSI32H6825
Servo and Spindle Predriver
PIN DESCRIPTION
SUPPLIES
NAME
TYPE
DESCRIPTION
GNDD
GNDA
GROUND Digital and Analog Grounds.
VCC
POWER
System 5V power supply.
VP
POWER
The 12V supply, diode protected from system 12V. Bridge supply for the
spindle and actuator FETs.
VREF
AN INPUT
REFERENCE VOLTAGE. All actuator analog signals are referenced to this
voHage.
VLlM
AN INPUT
LIMITING VOLTAGE. The voltage at this pin sets the WRPROT window
comparator limits. Limiting occurs when:
ACTUATOR
ISOUT-VREFI> VREF-VLlM
An internal resistor divider establishes a defauH value that may be externally
adjusted.
ERR
AN OUTPUT
POSITION ERROR. The loop compensation amplifier output. This signal is
amplified by the MOSFET drivers and applied to the motor by an external
MOSFET H-bridge as follows:
SE3-SE1 = 17(ERR-VREF)
loopcompen~
ERRM
AN INPUT
POSITION ERROR INVERTING INPUT. Inverting input to the
sation amplifier.
ERRP
AN INPUT
POSITION ERROR NON-INVERTING INPUT. Non-inverting input to the loop
compensation amplifier.
SOUT
AN OUTPUT
MOTOR CURRENT SENSE OUTPUT. This output provides a voltage proportional to the voltage drop across the external current sense resistor, as follows:
SOUT-VREF = 4(SE2-SE1)
AN OUTPUT
WRITE PROTECT. Active low, an open collector output which is asserted
when SOUT exceeds the window comparator limits.
SE2
AN INPUT
MOTOR CURRENT SENSE INPUT. Non-inverting input to the current sense
differential amplifier. It should be connected to one side of an external current
sensing resistor in series with the actuator. The inverting input of the differential amplifier is connected internally to SE1.
SE1
AN INPUT
MOTOR VOLTAGE SENSE INPUT. This input provides feedback to the
inverting MOSFET driver amplifier and to the current senSe amplifier. It is
connected to the current sensing resistor which is in series with the motor. The
gain to this point from ERR is:
WRPROT
SE1-VREF =-8.5(ERR~VREF)
7-254
SSI32H6825
Servo and Spindle Predriver
PIN DESCRIPTION
(continued)
ACTUATOR (continued)
NAME
TYPE
DESCRIPTION
SE3
AN INPUT
MOTOR VOLTAGE SENSE INPUT. This input provides feedback to the non
inverting MOSFET driver amplifier. It is connected to one side of the motor.
The gain to this point from ERR is:
SE3-VREF = 8.5(ERR-VREF)
OUTA,OUTC
AN OUTPUT
P-FET DRIVE. Drive signal for a P channel MOSFET connected between one
side of the motor and VP.
OUTB,OUTD
AN OUTPUT
N-FET DRIVE. Drive signal for an N channel MOSFET connected between
one side ofthe motor and GND. Crossover protection circuitry ensures thatthe
P and N channel devices connected to the same side of the motor are never
enabled simultaneously.
AN INPUT
NON-INVERTING A3 INPUT. Positive input to A3, the uncommitted opamp.
A3P
A3N
A3
AN INPUT
INVERTING A3 INPUT. Negative input to A3, the uncommitted opamp.
AN OUTPUT
A3 OUTPUT. The output of A3, the uncommitted opamp.
P1, P2,P3
AN OUTPUT
P CHANNEL SPINDLE FET DRIVERS. These pins are connected to the three
P channel power MOSFETs in the spindle motor power bridge.
N1, N2, N3
AN OUTPUT
N CHANNEL SPINDLE FET DRIVERS. These pins are connected to the three
N channel power MOSFETs in the spindle motor power bridge.
RSR
COMPONENT
SOURCE CURRENT LIMIT. The peak source current at N1 .. N3 is set at 20x
the current through RSR.
DIG INPUT
PULSE WIDTH MODULATION INPUT. Modulates the N channel power
MOSFETs to control spindle motor current.
COMPONENT
ONE SHOT CAPACITOR. Sets the time delay in the one shot. The one shot
is clocked whenever the current in the spindle exceeds a limit controlled by
RMs '
AN INPUT
SPINDLE CURRENT SENSE. Connects to the spindle current sense resistor,
RMs ' and is used during startup as part of the current limit circuitry.
VCOITACH
DIG OUTPUT
SPEED CONTROL OUTPUT. Under normal operation (DISPWR - 1), this pin
provides the speed sensitive signal used by the llP to control spindle speed.
When DISPWR = 0, the pin provides the output of the TACH comparator.
RVCO
COMPONENT
VCO RESISTOR. Sets the speed range of the VCO. The voltage at RVCO is
forced to track RC.
SPINDLE
PWMIN
COS
ISENSE
7-255
I
SSI32H6825
Servo and Spindle Predriver
SPINDLE (continued)
NAME
TYPE
CVCO
COMPONENT
VCO CAPACITOR. Sets the speed range of the VCO.
RC
COMPONENT
PLL LOOP FILTER. Sets the time constant for the PLL in Run mode. In all
other modes, it is connected to a DC voltage, VIOLE' ViOlE determines the VCO
frequency at which crossover from startup to run should occur (by lowering
ENABLE).
RPH
COMPONENT
PHASE ERROR CURRENT SET. The pump current in the phase error
amplifier is the sum of the VCO current (through RVCO) and the current
through RPH.
AN INPUT
SPINDLE MOTOR TERMINALS. These pins are used to calculate the phase
error in the PLl.
RETRACT
DIG INPUT
POWER FAIl. Active low, this digital input should be asserted by external
power fault detection circuitry. When low, this pin forces an actuator retract.
BRAKE
AN INPUT
BRAKE. Active low, this input is pulled low by external circuitry to perform a
delayed brake.
CBRAKE
COMPONENT
BRAKE CAPACITOR. A large capacitor is connected to CBRAKE to provide
pullup to the N channel spindle MOSFETsduring brake.
RBK
o/cOUTPUT
BRAKE RESISTOR. A high value (10 Meg) resistor is connected between
CBRAKE and RBK to pull upthe base of the brake transistor. This pin is pulled
low while BRAKE is not asserted.
DISPWR
DIG INPUT
DISABLE POWER. Active low, this input turns off the high and low sides of
the spindle drivers .. A brake command will over-ride DISPWR. An internal puli
down resistor guarantees a logic 0 when DISPWR floats.
ENABLE
RESET
DIG INPUT
MODE CONTROLS. These inputs control the spindle modes according to the
following truth table:
PH1,PH2,PH3
DESCRIPTION
CONTROL
ENABLE
0
0
1
1
RESET
0
1
0
1
MODE
Run
Brake
Start
Preset
RC
Run
VIOLE
VIOLE
VIOLE
VCO
Run
Idle
Rst
Idle
Commutator
Run
Rst
Run
Rst
Note:
Spindle braking is activated in Brake mode. Brake mode, whether activated by
ENABLE and RESET or by a power failure is internally latched and can only
be turned off by asserting Preset mode.
ADVANCE
DIG INPUT
COMMUTATION ADVANCE. A rising edge onthis pin will cause the commutator to advance whenever RESET is low. While high, ADVANCE prevents
other commutation clocks from occurring.
7-256
SSI32H6825
Servo and Spindle Predriver
ELECTRICAL SPECIFICATIONS
Recommended conditions apply unless otherwise specified.
ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may cause permanent damage to this device.
PARAMETER
RATING
VP
oto 14V
VCC
Oto 7V
VREF
SE1,SE2,SE3,N1,N2,N3,BRAKE,CBRAKE,RBK,OUTD
oto 10V
oto 15V
PH1,PH2,PH3
-2 to 15V
VCOTACH, DISPWR, PWMIN, ADVANCE,RESET,
ENABLE,RETRACT
oto VCC
All other pins
Oto VP
Storage Temperature
-45 to 165"C
Solder temperature - 10 sec duration
260"C
RECOMMENDED OPERATING CONDITIONS
Unless otherwise noted, the following conditions are valid throughout this document.
PARAMETER
VP
MIN
NOM
MAX
UNIT
Normal Mode
9
12
13.2
V
Retract Mode
3.5
14.0
V
4.5
7
V
0
70
·C
20
35
mA
-5
10
mA
2
mA
CONDITION
VREF
Operating Temperature
DC CHARACTERISTICS
VP Current
VCC Current
VREF Current
SE2= VREF
7-257
SSI32H6825
Servo and Spindle Predriver
A1 , LOOP COMPENSATION AMPLIFIER
CONDITIONS
PARAMETER
MIN
TYP
Input bias current
Input offset voltage
..
Voltage swing
About VREF = 5.4
nA
3
mV
V
1
-1.3
V 1H • wrt VP
V
V
kQ
4
to VREF
UNIT
500
±2
Common mode range
V 1L
Load resistance
MAX
100
Load capacitance
. pF
Gain
80
dB
Unity gain bandwidth
0.5
MHz
CMRR
60
dB
PSRR
60
dB
A2, CURRENT SENSE AMPLIFIER
Input Impedance - SE1
SE2= VREF
1.8
3.3
Input Impedance - SE2
SE1 = VREF
4.8
9.6
Input offset voltage
SE1 = SE2 = VREF
kQ
kQ
2.0
mV
Output voltage swing
1.4
VOL
VOH • wrt VP
-1.3
Common mode range
V 1L
V 1H • wrtVP
Load ReSistance
0
VP
~
10.0V. VREF = 5.0
to VREF
V
V
V
-0.2
V
20
kQ
Load capacitance
100
pF
Output impedance .
20
Q
Gain (SOUT-VREF)/SE1-SE2)
3.9
Unity gain bandwidth
0.5
MHz
CMRR
52
dB
PSRR
60
dB
7-258
4.0
4.1
VN
SSI32H6825
Servo and Spindle Predriver
ELECTRICAL SPECIFICATIONS (continued)
A3 AMPLIFIER
PARAMETER
CONDITIONS
MIN
TYP
Input bias current
Input offset voltage
MAX
UNIT
2S0
nA
2
mV
1.4
V
Voltage swing
VOL
-1.2
VOH ' wrt VP
V
Common mode range
V 1L
2.S
V 1H ' wrt VP
Load resistance
to VREF
V
-3
V
10
kQ
Load capacitance
100
pF
Gain
60
dB
Unity gain bandwidth
1S0
kHz
CMRR
60
dB
PSRR
60
dB
WINDOW COMPARATOR
Window comparator threshold
ISOUT-VREFI increasing
Threshold hysteresis
VLlM voltage
No external parts
VLlM input resistance
WRPROTVol
VREF-VLlM
V
SO
mV
92
94
8
15
101 < 1 rnA
WRPROT input leakage
WRPROT delay
SOUT = VREF to VREF + 0.6V
96
%VREF
kQ
0.4
V
10
J.1A
10
j.l.S
4.0
V
VREF MONITOR
VREF fail threshold
VREF Descending
2.6
3.3
85
Hysteresis
7-259
mV
II
SSI32H6825
Servo and Spindle Predriver
ACTUATOR MOSFET DRIVERS
MIN
TYP
to VREF
10
25
OUTA, OUTC voltage swing
IIOUTI < 1 mA
0.7
VCC-1
V
OUTB, OUTD voltage swing
IIOUTI < 1 mA
1
VCC-1
V
2
V
PARAMETER
CONDITIONS
SE3 Input impedance
MAX
kO
VTH, crossover separation
threshold
Slew rate, OUTA..D
CL < 1000 pF
Crossover time
300 mV step at ERR
0.5
V/1iS
6
Output impedance, OUTA..D
Transconductance
I(OUTA .. O)/(ERR-VREF)
Gain
-(SE1-VREF)/(ERR-VREF) or
(SE3-VREF)/(ERR-VREF)
Retract motor voltage
VP>5V
UNIT
liS
50
kO
8
mNV
8
8.5
9
VN
0.7
0.82
1.0
V
VCO (unless otherwise specified, CVCO = 0.01 IlF, RVCO = 12 kil)
VRC
Typical frequency
8.8 RyCO CyCO
Run Frequency
RC = 2.0V
Idle Frequency
Mode = Preset
Reset Phase Error
RC = VIDLE
Hz
1705
1894
2083
Hz
85
100
115
Hz
36
Degree
PHASE ERROR AMPLIFIER (unless otherwise specified, RVCO=12 kil, RPH=not used)
VRC (VIOLE)
Mode = Preset
Pump Current at RC
Start Mode
V RC = V IDLE , RPH = 00
Run Mode, at speed
V RC = 2V
100
mV
4
f.l.A
f.l.A
80
Source/Sink Current Mismatch
V RC = 2V
5
PHi Input Offset, State B
PH2 = VP, PH3 = 0
PHi Input Offset, State E
PH2 = 0, PH3 = VP
PH2 Input Offset, State A
PH2 Input Offset, State 0
PH3 Input Offset, State F
PHi = VP, PH2 = 0
PH3 Input Offset, State C
PHi = 0, PH2
=VP
RPH Voltage
RPH = 120 kil
%
-60
60
mV
-60
60
mV
PHi = VP, PH3 = 0
-60
60
mV
PHi = 0, PH3 = VP
-60
60
mV
-60
60
mV
-60
60
mV
7-260
..-
1.2
V
SSI32H6825
Servo and Spindle Predriver
ELECTRICAL SPECIFICATIONS (continued)
MOTOR CURRENT CONTROL
PARAMETER
MIN
TYP
MAX
UNIT
90
100
110
rnV
COS = 0.002 ~F
15
25
35
~
TA = 25'C
0.8
1.2
1.6
V
0.1
~
CONDITIONS
ISENSE threshold (VLlMIT)
One shot off time
BRAKING CIRCUIT
BRAKE threshold
BRAKE bias current
NMOS MOTOR DRIVER OUTPUTS (N1, N2, N3)
Source Current
Sink Current
RSC = 50k, VOUT = 4V
3
6
rnA
RSC = 100k, VOUT = 4V
2
4
rnA
9
25
rnA
1
V
-2.5
V
VOUT=4V
Output Low Voltage
Isink= 5 rnA
Output High Voltage (wrt VP)
Isource = 0.1 rnA
PMOS MOTOR DRIVER OUTPUTS (P1, P2, P3)
Source Current
VOUT=VP-4
20
Sink Current
VOUT = VP-4
9
Output Low Voltage
Output High Voltage (wrt VP)
rnA
25
rnA
Isink= 1 rnA
1.5
V
Isource p = IsourceN = 5 rnA
-1
V
DIGITAL INPUTS;
0.8
Vil
VIH
V
2.0
V
200
~
Open circuit voltage
(excluding RETRACT)
0.4
V
IIH (RETRACT)
20
~
IIH (excluding RETRACT)
VIN = 4V
VIN - 4V
7-261
II
SSI32H6825
Servo and Spindle Predriver
PACKAGE PIN DESIGNATIONS
CAUTION, Use handling procedures neoessary
for a S1atic sensitive ccmpcnent.
(Top View)
g
~
o 0
VREF
A3
48 47 48 45 44 43 42 41 40 39 38 37
1.
36
~
2
A3N
A3P
4
~
l!RARE'
6
CVCO
SE3
OUTC
34
OUTO
33
RSK
32
CBRAKE
31
RSR
30
PI
PH3
8
29
P2
PH2
9
29
P3
PHI
10
27
Nl
RVCO
11
29
N2
12 13 14 15 16 17 18 19 2D 21" 22 23 24 25
N3
RC
48·Lead TQFP
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned 10 verify that the data
sheet is current belore placing orders.
Silicon Systems, Inc., 14351 My/ord Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1993 Silicon Systems,lnc.
7·262
1293 - rev.
SSI32H6830
Servo DSP
"PkiUiiMt,";·kUt.".
December 1993
DESCRIPTION
The SSI 32H6830, designated as the SEEKERTM,
contains a DSP, a 10-bit ADC, two 10-bit DACs, and
sufficient I/O pins to perform the servo and MSC
functions of a hard disk drive with no overhead to the
master microprocessor. When fully programmed, the
SEEKERTM performs self-contained seek, track, and
spindle control functions. When the device is given a
track destination, it will seek to the desired track,
generate an interrupt when it arrives on track, and then
servo on the track. As a spindle controller, the
SEEKERTM will start the motor, spin it up to a speed
indicated by the microprocessor, and generate an
interrupt when proper speed has been achieved. The
spindle controller is also capable of phase locking to a
master spindle index and maintaining a specified phase
with respect to the master index. The DSP will allow
more sophisticated algorithms with better phase margin than those implemented with a microprocessor.
The program and constants for the DSP are stored in
the microprocessor ROM and are uploaded to the
DSP. The part is optimized for use with the SSI
32H6810A motor speed commutator and servo amplifier device.
The SEEKER™ offloads all sector rate processing
from the microprocessor and allows it to spend nearly
100% of its time dealing with the controller chip; an
essential feature as data rates approach 48 Mbitls. It
also allows better algorithms to be implemented with
less phase delay. This results in faster, quieter seek
times and higher track bandwidths.
FEATURES
•
Self contained seek, track, spindle start,
spindle run, and spindle sync capability
•
Can operate at a multiple of the sector rate to
reduce latency time between seek command
and start of seek
•
•
•
•
OSP with 16 x 16 multiply In 200 ns
•
10-blt 2 IlS AOC with 6 Input MUX
Two 10 bit OACs
Serial IlP port for uploading program memory
from system IlP
Interfaces with pulse detectors containing on
board peak detectors such as SSI 32P548 and
SSI32P4730
PIN DIAGRAM
~ Q Q Q Q Q Q Q Q Q Q Q Q Q Q ~
> z z z z z z z z z z z z z z >
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DOur
1
48
ADVANCE
2
.6=
~.
MASTER
47
SEROur
HALTDSP
RAMBUSV
4
45
MSCHGAIN
5
44
POR
1AT
6
43
START
SOATA
7
42
SLEEP
SOEN
8
41
TO
SCLK
9
40
COMMU
VND
10
39
DSPCK
VNA
11
38
LOCAL
1N4
12
37
TCK
INO
t3
36
DIN2
IN1
14
35
DINt
1N2
15
34
VPO
1N3
16
33
VPA
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
5~~::E!i5tti!2~a..otl;glt-~
~gii!l!:-~5-l!::g~lli~!i~i1i
:>
'"
1293- rev.
>
II:
~
en
64·Lead TQFP
CAUTION: Use handling procedures necessary
for a static sensitive component
II
SSI32H6830
Servo DSP
BLOCK DIAGRAM
",
R2
INREf
VPA
I
VPO
"UX
VNA
IN'
VNo
IH2
ceCA I+--.--===U~U~X~DE~CA~_ _ _ _~
MUX RST
l+--l-rU:!!UX:.!"~ES~E!.T-------~
SERVO
ZEROREF
"OON>
SREF
I
TIMING
i
START
USC
SEQ_lEN
ADCSTART
UR"
1--+--11-----------'
Q----t----->i
STATEN
~
DSf'
RM,48USY
k----------DHAl~
~
"BIAS
f---------..-1
DlNl
OINl
DSPCK
lOCAl
MASTER
7-264
OOI.4IdU
ADVANCE
~
MSCHGAN
1m'
SWl
SW2
OOUT
SSI32H6830
Servo DSP
FUNCTIONAL DESCRIPTION
demodulator. Some possible uses for the flag bits are:
warning the DSP that certain sector data as bad, and
in oversampling applications, indicating to the DSP
which start pulses are at the beginning of a sector.
HARDWARE FUNCTIONAL BLOCKS
Front End
The SEEKER™ front end consists of a 10-bit two's
complement ADC, a 6-input MUX and some amplifiers
whose gain can be set with external components. The
Iront end is intended to be driven by pulse detectors like
the SSI 32P548 that have internal peak detectors or
integrators. External resistors perform gain and offset
correction.
Front End Timing
A start pulse sets the MUX address to five, raises
RAM BUSY, and initiates a sequence of consecutive
ADC conversions. The result of each conversion is
stored in the data RAM (DRAM) address 0 through 5,
respectively. The M UX inputs are converted in reverse
numerical order for INO through IN3. When the
conversions are complete, other status words such as
the state of the period and phase timers, the target
track, and the current track are inserted in the DSP
DRAM and a DSP code pass is started.
The start pulse can be generated by hardware (the
START pin or an internal counter) or software
(STARTBIT in FSTATUS.) If STRTEN (in FSTATUS)
is high, the start signal is taken from the START pin. If
it is low, the internal counter generates a start signal
every 512 DSP clocks. STARTBIT generates a start
regardless of any other pin or bit.
Spindle Control Hardware
The MSC portion of the seeker will support start, run,
and synchronized spindle modes. The MSC hardware
consists of a period timer and a phase timer. The period
counter starts on the rising edge of LOCAL and transfers
its count to a latch when the next rising edge occurs. A
status bit, LlNDEX, is set whenever new data is available
at the latch. The status bit will be high for one DSP code
pass. The phase timer is also started on every LOCAL
rising edge. It is stopped when MASTER rises. A status
bit, MINDEX, indicates when new data from the phase
timer is available. By comparing the value of the period
timer and the phase timer, the actual phase error
betwe.en local and master can be determined. The
DSP controls spindle start by monitoring COMMU and
asserting ADVANCE. See the SSI 32H6810 or
equivalent data sheet for more details.
Il P Serial Port
Through the serial port, the JlP can read FSTATUS and
any DRAM or IRAM memory word. It can write the
FSTATUS and TTRACK registers as well as any DRAM
or IRAM word. The registers are internally double
buffered and can be accessed by the IlP at any time.
Access to RAM must be limited to when the DSP is idle.
The format of the serial port data string is consistent
with other Silicon Systems serial interfaces.
DSPTiming
When the DSP is started, the ADC values, DSPIN,
. TTRACK, PHTIME, PTIME, and TRACK have already
been loaded in DRAM. These values will not be updated
again until the next start pulse occurs. When the DSP
reaches a STOP instruction, it halts,lowers RAMBUSY
and waits for another start signal.
DAC1 and DAC2
These DACs are 10 bits wide. They are memory
mapped to DRAM address 2 and 3 for DAC 1 and 2,
respectively. Each DAC has its own zero-reference
input. The full scale swing of each DAC is ±VBGAP/2.
These DACs are intended to drive the servo and
spindle buffers.
Track ID
The current track ID is demodulated and converted to
binary by external circuitry. It is then supplied to the
SEEKERTM through a dedicated serial port. The track
ID is transferred to DRAM address 10 when a DSP start
pulse is received. Depending on the TRKMSB bit in the
FSTATUS word, track ID is rece ived either LSB or MSB
first. Since the track ID register can handle up to 16 bits,
the unused bits can be utilized as flag bits from the
TTRACK Memory
This 16 bit word is accessed by the IlP serial port. It is
double buffered sothe JlP does not need to synchronize
to RAM BUSY. When TTRACK is programmedto a new
target track, the next DSPSTART pulse will transfer it
to DRAM and cause a seek to begin.
7-265
I
SSI32H6830
Servo DSP
FUNCTIONAL DESCRIPTION
SEROUT
(continued)
FSTATUS Memory
This 16-bit word can be read and written by the I1P. It
is double buffered so the IlP does not need to
synchronize to RAMBUSY.
This is an output serial port used for diagnostic purposes.
Whenever the DSP writes to this port, the bits are
shifted out at the DSP clock rate. SEROUT normally
sits high. A leading zero prefixes all outputs as a
marker. This pin is useful for monitoring internal data
words while the DSP is operating in real time.
Interrupt
The INT output is controlled by the DSP. It is typically
used to indicate an eventof interest to the IlP such as
spindle control achieving lock, orthe head arriving at its
target, or at other times, spindle control losing lock or
the head falling off track. Upon receiving the interrupt,
the I1P should read FSTATUS to determine the interrupt
type. Reading FSTATUS clears the INT output.
Software Interface to I1P
The IlP is able to read or write any word in the IRAM or
DRAM. In addition, it is able to read and write the
FST ATUS register, and to write the TTRACK register.
FSTATUS Register-Read
The first 4 bits are interrupt status bits. They are written by the DSP and cause an interrupt to be initiated whenever
they change state. The second four bits are information bits and do not affect INT. The third group of 4 bits are
interrupt flags, indicating which of the interrupt status bits caused an interrupt. The last 4 bits are for version control
and future reserved functions. Note that whenever FSTATUS is read, INT is de asserted and the interrupt flags
are cleared.
Name
Description
0
Spare_INT
When this bit changes state, INT is asserted.
1
Ontrack
Indicates that the head is on track. When this bit changes state,
INTis asserted.
2
Acspeed
Indicates that the spindle is at speed. When this bit changes
state, INT is asserted.
3
Phase_lock
Indicates that the local index is phase locked to the master index.
When this bit changes state, INT is asserted.
4
Track/Seek
Indicates if the DSP is in track mode.
5
RAM BUSY
Indicates the DSP RAM is servicing the DSP and is "locked out"
of the IlP serial interface.
Bit
-~-----.---.
6
DSTAT11
Bit 11 of DSPSTATUS
7
DSTAT12
Bit 12 of DSPSTATUS
8
INTFO
Is set when bit 0 changes state. Is cleared when FSTATUS is
read.
9
INTF1
Is set when bit 1 changes state. Is cleared when FSTATUS is
read.
10
INTF2
Is set when bit 2 changes state. Is cleared when FSTATUS is
read.
11
INTF3
Is set when bit 3 changes state. Is cleared when FSTATUS is
read.
7-266
SSI32H6830
Servo DSP
FSTATUS Register-Read
(continued)
Bit
Name
Description
12
REVO
LSB of revision number.
13
REV1
MSB of revision number.
14
RESERVED
15
RESERVED
FSTATUS Register-Write
0
STRTEN
Selects DSPSTART from the timing block instead of the divideby-512 counter.
1
TRKMSB
Sets the TRACK 10 serial to parallel converter to "MSB first"
mode.
2
HALTBIT
Serves the same purpose as the HALTDSP pin. When asserted,
the DSP will continue executing its current code pass and then will
remain idle, ignoring both external and internal hardware start
pulses. This bit should be set by the f..lP during initialization of the
SEEKERTM.
3
STARTBIT
Is a third way of creating a "start." When HALTBIT is asserted, this
is the only way to create a "start." If this bit is programmed to 1,
the usual sequence of ADC conversions and data transfers to
DRAM is initiated. The DSP code pass will not be initiated,
however. Instead the DSP will wait for SS pulses. STARTBIT is
automatically cleared after it is written.
4
SS
This bit is ignored except if HALTBIT is asserted. In that case,
every "one" written to SS causes the DSP to advance one clock
cycle. SS is automatically cleared after it is written.
5
RESETBIT
Resets the SEEKER™ to the state where the f..lP serial interface
has complete access. This bit should be set by the f..lP before
initializing the SEEKERTM .
6
RESUMEBIT
Terminates the single step mode by resuming DSP execution at
full speed.
7
FS7
A spare bit for communication from f..lP to DSP.
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Servo DSP
FUNCTIONAL DESCRIPTION
(continued)
Serial Port
The serial port is designed to be shared by other devices. For this reason, a device ID is included in the preamble.
The device ID conforms to the Silicon Systems standard: 1-R/W, 2-Pulse Det, 3-Filter, 4-Data Sep, 5-ENDEC,
6-Time Base, 7-Servo/MSC. Bit 0 of the serial port is received first. Each bit string received by the serial port can
be unlimited in length but consists of the following initial fields:
Bit#
0
Field
R/W
1.. 3
Device ID
4 .. 5
Type
6 .. 7
8.115
16.. or 8 ..
Description
.
Indicates whether data is to be read or written.
Identifies the device being programmed (LSB is bit 1). Must be
'7' to communicate with this part.
Indicates which memory is addressed (LSB is bit 4):
0
FSTATUS
1
TTRACK (write only)
2
DRAM or ACCUMULATOR
3
IRAM or PROGRAM COUNTER
Address bank
The bank address for memories with more than 256 words.
These bits are ignored if FSTATUS orTTRACK is being accessed.
Note that if bank is 11, type 2 and 3 become ACCUMULATOR
and PROGRAM COUNTER respectively.
Address
The RAM address (LSB is bit 8). This field must always be sent
except when accessing FSTATUS or TTRACK.
Data
The data (LSB first). If RAM data is being read or written,
consecutive data words can be concatenated. The address will
automatically increment after each 16 (DRAM) or 20 (IRAM) bits.
The address bank is automatically incremented when necessary.
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Servo DSP
DSP Memory Map
The DSP communicates with the SEEKER™ chip through memory mapped regions of DRAM. The first 10 words
are mapped to various hardware resources as defined below. Note that the first four words are ''write protected."
The remaining words are initialized at the beginning of each DSP code pass and may then be modified or
overwritten by the DSP.
DRAM Address
Written by DSP
Read by DSP
0
ADC5 (write protected)
DSPSTATUS
1
ADC4 (write protected)
SEROUT
2
ADC3 (write protected)
DACt
3
ADC2 (write protected)
DAC2
4
ADC1
5
--
ADCO
6
DSPIN
7
TTRACK
8
PTIME (period time)
9
PHTIME (phase time)
10
TRACK
I--.
DSPSTATUS and DSPIN
DSPIN is the word the DSP uses to communicate with bits set by the IlP or by SEEKERTM input pins. DSPSTATUS
is the word the DSP uses to control bits read by the IlP and external pins controlled by the DSP. Whenever the
first 4 bits of DSPSTATUS are changed by the DSP, INT is asserted. The bits in DSPIN and DSPST ATUS are
defined below.
BIT
DSPSTATUS (Written by DSP)
DSPIN (Read by DSP)
0
COMMU (from COMMU pin)
SPARE_INT (to FSTATUS)
1
LlNDEX (from period timer)
ONTRACK (to FSTATUS)
2
MINDEX (from phase timer)
ATSPEED (to FSTATUS)
3
DINt (from DIN1 pin)
PHLOCK (to FSTATUS)
TRACK/SEEK (to FSTATUS)
4
DIN2 (from DIN2 pin)
5
LOCAL (from LOCAL pin)
UNIPOLAR (to pin)
6
MASTER (from MASTER pin)
MSCHGAIN (to pin)
7
FS7 (from FSTATUS)
ADVANCE (to pin)
DOUT (to pin)
8
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SSI32H6830
Servo DSP
FUNCTIONAL DESCRIPTION
DSPSTATUS and DSPIN
(continued)
(continued)
DSPIN (Read by DSP)
BIT
DSPSTATUS (Written by DSP)
9
SWON (to SWi , SW2 switch)
10
DSTATii (to FSTATUS)
11
DSTAT12 (to FSTATUS)
12
not used
~
~-
--~-~~~-~~-~
13
not used
14
not used
15
not used
PIN DESCRIPTION
The following description lists each pin, associates a pin type to it, and provides a brief description of the pin's
function.
NAME
TYPE
DESCRIPTION
VPA,VPD
VCC
Analog and digital power supplies.
VNA, VND
GND
Analog and digital grounds.
INO,IN1,
IN2,IN3
Ana In
MUXOUT
Ana Out
INM
Ana In
AOUT
Ana Out
INP
The four primary inputs automatically converted by the AlD. These inputs
drive a low resistance analog switch.
-- f--=--~
The output of the INO .. IN3 mux.
The inverting input to amplifier Ai.
The output of amplifier Ai.
Ana In
The non-inverting input to Ai.
Ana In
The voltage reference input. This will determine the full scale swing of the
ADC and the two DACs.
Ana Out
The ADC zero reference output. Can be used by the Ai resistor network to
level shift INO through IN3.
~~
VBGAP
ZEROREF
IN4
Ana In
IN5
Ana Out
The output of amplifier A5.
Ana In
The inputs to amplifier A5.
IN5N,IN5P
A direct input to the ADC mux.
RBIAS
Ana Out
A resistor to ground from this pin sets the biascurrentforthe analog circuitry.
SERVO
Ana Out
The output of the servo DAC.
SREF
Ana In
MSC
Ana Out
MREF
Ana In
The servo DAC reference. The DAC output swing will be SREF-0.5·VBGAP
to SREF+0.5·VBGAP.
f---=--
The output of the MSC DAC.
The MSC DAC reference. The DAC output swing will be MREF-0.5·VBGAP
to MREF+0.5·VBGAP.
7-270
SSI32H6830
Servo DSP
NAME
TYPE
DESCRIPTION
SW1, SW2
Ana In
The two terminals of an uncommitted analog switch. The switch is controlled
by the SWON bit in the DSP STATUS word.
ADCSOUT
Dig Out
A test point from the ADC. This test point is connected to the output of the
ADC comparator.
START
Dig In
A rising edge on START initiates consecutive ADC conversions and causes
a pass through the DSP code to begin.
DSPCK
Dig In
The master clock (20 MHz) for the chip.
SLEEP
Dig In
Reduces the supply current of the chip. All analog circuitry is deactivated,
with outputs becoming high impedence. The chip clock is deactivated. No
data will be lost in RAM due to the use of static RAM.
POR
Dig In
SDEN
Dig In
SCLK
Dig In
SDATA
Dig 110
The J..lP serial interface data. This pin is an input except for the data cycles
of a serial read request.
TCK
Dig In
The clock for the current track serial input.
- -I -
Chip reset. This pin is for diagnostic purposes and should be grounded in
normal operation.
The J..lP serial interface enable. SCLK and SDAT A are ignored and the
interface reset when SDEN is low.
e---
The J..lP serial interface clock.
-
TO
--
Dig In
The data for the current track serial input.
SEROUT
Dig Out
The serial output from the SEROUTword memory mapped into DRAM. This
output can be used to monitor the DSP during real time applications.
RAM BUSY
Dig Out
When high, the DSP is executing code. When low, it is waiting for a START
pulse.
HALTOSP
Dig In
When high, halts the DSP. Similar in function to HALTBIT in FSTATUS. This
pin or HALTBIT should be asserted during J..lP access of DRAM and IRAM.
LOCAL
Dig In
The local index pulse. The period counter measures the time between
LlNDEX pulses.
MASTER
Dig In
The master index pulse. The phase timer measures the time from LlNDEX
to MINDEX.
--
COMMU
Dig In
The input from the BEMF comparator on the MSC chip.
ADVANCE
Dig Out
The output to the MSC chip.
UNIPOLAR
Dig Out
An uncommitted DSP output bit that can be used to command the external
MSC commutator to switch to unipolar mode.
MSCHGAIN
Dig Out
An uncommitted DSP output bit that can be used to command the external
MSC commutator to switch gains.
INT
Dig OlD
The interrupt output for the DSP.
DOUT
Dig Out
An uncommitted output bit that can be programmed by the DSP.
DIN1, DIN2
Dig In
Uncommitted input bit that can be read by the DSP.
7-271
SSI32H6830
Servo DSP
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Exposure to absolute maximum rating conditions for extended periods may cause permanent damage to the
device or affect device reliability.
PARAMETER
RATING
Supply voltage VPA, VPD
Pin voltage
Ana In
Ana Out
Dig In
Dig Out
Storage temperature
Lead temperature
(10 sec duration)
Vdd
-0.3 to 7.0V
Vinai
-0.3 to VDD+0.3V
Vinao
-0.3 to VDD+0.3V
Vindi
-0.3 to VDD+0.3V
Vindo
-0.3 to VDD+0.3V
Tstg
Tlead
-65 to 150°C
oto 300°C
RECOMMENDED OPERATING CONDITIONS
The recommended operating conditions forthe device are indicated in the table below. Performance specifications
do not apply when the device is operated outside the recommended conditions.
PARAMETER
RATING
Supply voltage
Vdd
4.5 to 5.5V
Ambient temperature
Ta
oto 70°C
Capacitive load on digital outputs
CI
50 pF
Analog output load
CI
50 pF
-------~.,-,.-.-.,---
RI
20kQ
."".-----,.--,-""---.------------~----
System clock Jc = 20 MHz
Jc
Freq. tolerance
Pulse width
Biasing resistor, Rbias = 56.3 kQ
VBGAP tolerance, VBGAP = 2.25V
Twh,Twl
-0.01 to 0.01%
20 to 30 ns
Rbias
-5 to 5%
VBGAP
-5 to 5%
7-272
..
SSI32H6830
Servo DSP
PERFORMANCE SPECIFICATIONS
SUPPLY CURRENT (FSTART = 5 kHz, DSP ACTIVE TIME = 25 J.lS)
PARAMETER
VPA
.-- ..
CONDITIONS
---~-
Idda - " - - - - - - --_._--
VPD
MIN
NOM
----
Idd
MAX
UNIT
24
mA
13
mA
VPA, Sleep mode
Iddas
TBD
mA
VPD, Sleep mode
Idds
TBD
mA
2.0
V
1
f.lA
0.4
V
DIGITAL 1/0
Digital input
0.8
Vii
V
Vih
1iI,lih
Digital Output (except INT)
Vol
10/ = 2.0 mA
Voh
loh = -100
f.lA
Vdd-.4
V
Digital Output (INT)
Vol
0.4
101 = 4.0 mA
V
SERVO DIA CONVERTER
Positive Full-scale voltage
Digital=Ox1 FF
SREF+
VBGAP/2
Negative Full-scale voltage
Digital=Ox200
Resolution
V
SREFVBGAP/2
V
10
bits
4
Digital Delay
VBGAPI
1024
LSB voltage
Differential nonlinearity
Offset
7-273
J.lS
V
i
LSB
TBD
mV
I
SSI32H6830
Servo DSP
ELECTRICAL SPECIFICATIONS (continued)
MSC D/A CONVERTER
PARAMETER
CONDITIONS
MIN
Positive Full-scale voltage
Digital = Ox1 FF
--
Negative Full-scale voltage
Digital = Ox200
Resolution
Digital Delay
---- -_._-_.
- - - ---
NOM
MAX
UNIT
MREF+
VBGAP/2
V
MREFVBGAP/2
V
10
bits
--
LSB voltage
Differential nonlinearity
Offset
4
I!S
VBGAP/
1024
V
1
LSB
TBD
mV
ADC CONVERTER
Positive full-scale input
Digital Output = Ox1 FF
VBGAP
Negative full scale input
Digital Output = Ox200
VBGAP/9
V
10
bits
Resolution
Conversion time
(includes MUX delay)
- - ----
V
2
I!S
- - --
VBGAP/
1152
LSB voltage
Differential nonlinearity
V
1
LSB
AMPLIFIERS
Gain
Unit gain bandwidth
Input offset
dB
50
-- --
MHz
1
---
20
mV
0.2
3.5
V
0
Vdd
V
1.8
I!S
100
Q
-20
-.~------
Output swing
Input common mode Range
Settling time to 0.1%full scale
step, inverting unity gain
MUX
On Resistance
7-274
SSI32H6830
Servo DSP
SW1, SW2 SWITCH
PARAMETER
CONDITIONS
MIN
On Resistance
NOM
MAX
UNIT
100
Q
J.lP SERIAL INTERFACE PORT TIMING
SCLK
Period
TCLK
50
ns
Low Time
TCKL
15
ns
High Time
TCKH
25
ns
TSENS
20
ns
60
ns
5
ns
SDEN
Setup Time
~---------
Hold Time
TSENH
SDATA
Setup Time
TDS
Hold Time
TDH
Read Delay
TPD
Disable Delay
- - _._-----_.
__ ._._-------
2
CL = 0 to 50 pF
4
TSENDL
ns
60
ns
25
ns
J.lP TRACK ID PORT TIMING
TCK
Period
TCLK
20
ns
Low Time
TCKL
10
ns
High Time
TCKH
10
ns
TO
Setup Time
TDS
3
ns
Hold Time
TDH
2
ns
7-275
I
SSI32H6830
Servo DSP
SOEN
---.-J
LAST WRITE CLOCK
~J.
> - - 1-
F1RSTAEADClOCK
J
SCLK
'-<:
TDS---1
SDATA
(WRITE)
X
SOATA
(READ)
Z
R/W
~
f--
X
R/W
X
100
Z
100
Z
II
X
101
101
102
Z
x~
--l
r
-
-
-
~SENH
)~
I
H"~
102
FIGURE 1: Serial Port Data Transfer Format
PROGRAMMER'S DESCRIPTION
DATA REG AND MULT REG
This programmer's description of the SEEKERTM DSP
contains a register level description of the DSP that is
detailed enough to illustrate each opcode. It also
contains a description of each opcode.
These registers store the data from the DRAM. This
permits the DRAM to perform other operations during
a multiply. A STORE or the setup cycle of an MLD or
MADD instruction will be executed while a previous
MLD or MADD instruction is completing.
REGISTER LEVEL DESCRIPTION
SEQUENCER
The DSP consistsof an arithmetic unit and an instruction
unit..The arithmetic unit consists of a data RAM (DRAM),
a shifter, an ALU, and an accumulator. The instruction
unit consists of instruction RAM (IRAM) and a program
counter. Figure 2 shows the contents of the DSP.
In a one-clock cycle, the DSP is capable of shifting a
data word upto± 15 bits and adding ittothe accumulator.
A 4-cycle multiply is implemented in the multiply and
accumulate functions.
DRAM
The DRAM stores data and coefficients for use by the
DSP. The first 11 addresses of the DRAM are memory
mapped to on-chip resources. In addition, a lookup
command allows the DSP to use portions of DRAM as
lookup tables.
This logiC block controls the execution of instructions
by monitoring the state of the accumulator, the DRAM,
and the IRAM. When the resources required by the
next instruction are available, the sequencer permits
that instruction to execute.
FLAGS
Certain instructions cause one of the three flags to be
updated with the sign bit of the accumulator. The flags
are used by the instruction unit during conditional
jumps.
SHIFTER
The shifter shifts the DATA REG word up to ±15 bits in
one clock cycle. Unused left hand bits are sign extended
and unused right hand bits are zero filled. The shifter
has a 24-bit input and output width. The 16-bit word
from DATA REG is sign extended 4 bits and padded
with 4 zero bits below the LSB before entering the
shifter.
7-276
SSI32H6830
Servo DSP
ALU
SHORT/LONG FORM DESCRIPTION
The ALU is capable of performing an add, subtract,
absolute value, XOR, AND, OR, and NEG function.
The list of opcodes details the choices,
There is instruction memory capacity for 1K by 10-bit
short form commands or 500 bytes by 20-bit long form
commands. Short form is a 10-bit command which
uses relative addressing, whereas long form is a 20-bit
command with direct addressing.
ACCUMULATOR
The accumulator is 16 bits with 4 extra LSB bits and 4
extra sign bits. The extra LSB bits minimize the rounding
error when partial products are summed during a
multiply. The top 4 sign bits are used as an aid in
identifying overflow. They also are used in extended
precision calculations where they are shifted to the
least significant bits of the 16-bit accumulator.
MULTIPLIER DESCRIPTION
DR, MR, and SR are three different pointers to DRAM
which are updated with each reference. The assembler
will insert short forms of each command if the pointer
reference is close enough to its previous referencethat
relative addressing can be used. Every instruction has
a short form except AND, OR, XOR, store commands
that use /RET, and jump instructions conditional on F2
or F3. The relative address distance is listed in each
opcode description.
The multiplierreturns the top 16 bits of a 16x16 product.
An additional 4 LSBs are calculated to improve the
truncation accuracy of the product. A RADIX register
shifts the multiplicand (pointed to by DR) a certain
number of bits to the left.
If it is desired to force a long or short version of a
particular command, an.L or .S suffix can be appended
to the command. Alternatively, a short instruction can
be forced by specifying a relative address such as '+1'
or '+2'.
This multiplier facilitates the use ofthetwo's complement
fractional representation. For instance if RADIX is set
to zero, each 16 bit number should be thought of as a
signed fraction whose full scale value approaches
±1.0. The value of the fraction is calculated by the
following equation:
ALU INSTRUCTIONS WITH MULTIPLY
value =
-2 ob15 + 2· 1b 14 + 2· 2 b13 + ... + 2· 15 bo
Two such numbers multiplied together will yield an
answer in the same format. For instance Ox4000 (0.5)
multiplied by Ox4000 (0.5) results in Ox2000 (0.25).
Alternatively, if it is desired to represent numbers
whose integer value can approach ±16, set RADIX to
4 and use the following formula:
value = -2 4 b15 + 23 b14 + 22 b13 + '" + 2. 11 bo
With this format, Ox0400 (0.5) multiplied by Ox1800
(3.0) results in OxOCOO (1.5).
OPCODE LIST
The following opcodes are implemented in the
SEEKERTM DSP. Parameters in [square] brackets are
optional. Parameters enclosed in {curly} brackets form
a list from which only one parameter may be chosen.
Parameters may be placed in any order within all
instructions except MLD and MADD. Opcodes, symbols
and all options are case insensitive.
MLD
DramDR DramMRVF1]
Loads the data register with DramDR and the multiplier
register with DramMRand initiates a multiply and load.
The value in DramDR is shifted left by RADIX before
being multiplied. The MLD instruction requires either 4
or 5 cycles to execute. The 5th cycle is not needed if the
previous ALU instruction was an MLD or MADD and
was followed by fewer than 4 non-ALU instructions. If
F1 is specified, the F1 flag will be updated with the sign
bit olthe accumulator result. Relative address distance
for both DR and MR addresses is +2, -1.
MADD DramDR DramMR[/F1]
Loads the data register with DramDR and the multiplier
register with DramMR and initiates a multiply and add.
The value in DramDR is shifted left by RADIX before
being multiplied. The MADD instruction requires either
4 or 5 cycles to execute. The 5th cycle is not needed if
the previous ALU instruction was an MLD or MADD
and was followed by fewerthan 4 non-ALU instructions.
If F1 is specified, the F1 flag will be updated with the
sign bit of the accumulator result. Relative address
distance for both DR and MR addresses is +2, -1.
7-277
I
SSI32H6830
ServoDSP
MULTIPLIER CONTROL INSTRUCTIONS
R.ADIX n [/RET]
Sets the amount of left shift "bias" to be performed on
DR during MLD and MADD instructions, This command
is effectively defining the location of the radix point in
the MR word. The RET option will cause a subroutine
return. The RADIX command is always short form and
is the only short form instruction with a RET option.
ALU INSTRUCTIONS WITH SHIFT
LDS
DramDR {/SHL=n, ISHR=nj [/F1) [lABS)
Loads the contents of DramDRin the accumulator after
being shifted as specified. Relative address distance
is +2, -1. F1 indicates that the F1 flag is to be updated
with the sign of the result. ABS indicates that the
absolute value of DramDR is to be used. If F1 or ABS
is specified, the long form of the instruction is used.
LDNS DramDR {/SHL=n, ISHR=nj [/F1]
Loads the negative contents of DramDR in the
accumulator after being shifted as specified. Relative
address distance is +2, -1. F1 indicates that the F1 flag
is to be updated with the sign of the result. If F1 is
specified, the long form of the instruction is used.
ADDS DramDR {/SHL=n, ISHR=nj [lABS) [/F1)
Adds the contents of DramDRto the accumulator after
being shifted as specified. F1 indicates that the F1 flag
is to be updated with the sign of the result. ABS
indicates that the absolute value of DramDR is to be
used. If F1 or ABS is specified, the long form of the
instruction is used. Relative address distance is +2, -1.
SUBS DramDR {/SHL=n, ISHR=nj [lABS) [lF1)
Subtracts the contents of DramDRto the accumulator
after being shifted as specified. F1 indicates thatthe F1
flag is to be updated with the sign of the result. ABS
indicates that the absolute value of DramDR is to be
used. If F1 or ASS is specified, the long form of the
instruction is used. Relative address distance is +2, -1.
XSIGN DramDR {/SHL=n, ISHR=nj [/F1]
Multiplies the accumulator by the sign of DramDR-if
DramDR is negative, the accumulator will be inverted.
If F1 is specified, the F1 flag is updated with the sign of
the accumulator at the end of the command's execution.
Relative address distance is +4, -3.
DramDR [IINV] {lSHL=n, ISHR=nj
AND
ANDs the contents of DramDRto the accumulator after
being inverted and shifted as specified. There is no
short form of this instruction.
OR
DramDR {lSHL=n, ISHR=nj
ORs the contents of DramDRto the accumulator after
being shifted as specified. There is no short form ofthis
instruction.
XOR
DramDR {lSHL=n, ISHR=nj
XORs the contents of DramDRto the accumulator after
being shifted as specified. There is no short form of this
instruction.
7-278
SSI32H6830
Servo DSP
ALU INSTRUCTIONS
STORE COMMANDS
LD
DramDR[/ABS] [/F1]
Loads the contents of DramDR in the accumulator. If
[ABS] is specified, the absolute value of DramDR is
loaded. If F1 is specified, the F1 flag is updated with the
sign of the accumulator at the end of the command's
execution. Relative address distance is +4, -3.
STO
DramSR [/RET] [{IF2, IF3}]
Store the accumulator in DramSR. If F2 or F3 is
specified, the appropriate flag will be updated with the
sign ofthe value being stored. Relative address distance
is +2, -1. If RET is specified, the long form of this
instruction is used.
LDN
DramDR [/F1]
Loads the negative contents of DramDR in the
accumulator. If F1 is specified, the F1 flag is updated
with the sign of the accumulator at the end of the
command's execution. Relative address distance is
+4, -3.
STOSAT
DramSR [/RET] [{IF2, IF3}]
Store the accumulator in DramSRwith saturation logic
enabled. If F2 or F3 is specified, the appropriate flag
will be updated with the sign of the value being stored.
Relative address distance is +2, -1. If RET is specified,
the long form of this instruction is used.
ADD
DramDR[/ABS] [/F1]
Adds the contents of DramDR to the accumulator. If
[ABS] is specified, the absolute value of DramDR is
added. If F1 is specified, the F1 flag is updated with the
sign oUhe accumulator at the end of the command's
execution. Relative address distance is +4, -3.
STOLSW DramSR [/RET] [{IF2, IF3}]
Store the least significant word. This command stores
the accumulator in DramSR and then shifts the sign
bits right by 16 bits. The extra LSB bits are cleared. If
F2 or F3 is specified, the appropriate flag will be
updated with the signofthevalue being stored. Relative
address distance is +2, -1. If RET is specified, the long
form of this instruction is used.
SUB
DramDR [lABS] [/F1]
Subtracts the contents of DramDR from the
accumulator. If [ABS] is specified, the absolute value of
DramDR is subtracted. If F1 is specified, the F1 flag is
updated with the sign of the accumulator at the end of
the command's execution. Relative address distance
is +4, -3.
XSIGN DramDR[/F1]
Multiplies the accumulator by the sign of DramDR-if
DramDR is negative, the accumulator will be inverted.
If F1 is specified, the F1 flag is updated with the sign of
the accumulator at the end of the command's execution.
Relative address distance is +4, -3.
STODR
DramSR [/RET] [{IF2, IF3}]
Stores the DATA REG contents in DramSR. This
command permits fast data moves since the data does
not have to flow through the accumulator pipeline. If F2
or F3 is specified, the appropriate flag will be updated
with the signofthe value being stored. Relative address
distance is +2, -1. If RET is specified, the long form of
this instruction is used.
NOP
An arithmetic command that does nothing. It is
sometimes useful before STO and conditional JMP
commands. This command is always short.
LKUP
Loads the accumulator with the left justified DRAM
value pointed to by the accumulator. The upper 8 bits
of the accumulator are used as the DRAM address.
The SAT module is always activated during LKUP.
This command is always short.
7-279
SSI 32H683()
Servo DSP
PROGRAM CONTROL
JMP
label:·
An unconditional jump. Relative address distance is
+8, -7.
JSUB label:·
An unconditional subroutine call. This is always a long
instruction.
.
JF
label: {/F1, IF2, IF3}
Jump if flag is one. Relative.address distance is +8,7. If F2 or F3 is specified, the long form is used.
JFS
label: {/F1, IF2, IF3}
Jump if flag is zero. Relative address distance is +8, 7. If F2 or F3 is specified, the long form is used.
JALU
A computed jump. The jump address is taken from the
bottom 9 bits of the accumulator. This is a short
instruction.
STOP
Stops execution of the program. The program restarts
on a rising edge of DSPSTART pulse.
COMMAND SEQUENCING
Althoughthe SEEKER™ DSP is a pipeline architecture,
instruction sequencing is unaffected· except in one
case.
Commands that depend on accumulator results such
as STORE and conditional jump must allow one cycle
to occur after the accumulator instruction completes. If
the accumulator instruction requires more than one
cycle to complete (MLD or MADD), the STORE or
conditional jump must be placed one ALU instruction
afterthe accumulator command. This allows the result
to propagate into the accumulator before it is stored.
Example 1: Calculate C=A·S and E=A·B+D.
;Ioad accumulator with A·B
MLD
AS
ADD
D
;add D to accumulator
STO
C
;store A·S in C
STO
E
;store A·S+D in E
Example 2: Calculate C=A·S and E=A·S+D·F.
MLD A S
;Ioad accumulator with A·S
MADD D F;add D·F to accumulator
STO
C
;store A·S in C
NOP
;NOP is an ALU instruction
STO
E
;store A·S+D·F in E
CYCLE COUNTING
All instructions execute in one cycle except MLD and
MADD instructions which require a setup cycle and 4
ALU cycles. During a multiply, the sequencer will
execute upto 4 non-ALU instructions until it encounters
another ALU command. Non-ALU commands include
JUMP, STORE, and the setup cycle of MLD and MADD
instructions. Thus it is often possible to store results
and setup the next multiply without consuming clock
cycles.
Example 3: Calculate a 2 pole Chebyshev low pass:
vout = Z·l (v. + K3 vout )
Vx
= v r· 1 + Y;n~l - v outK2
LD
MADD
MADD
VX
VIN K1
VOUTNK2
MADD
VOUTK3
STO
VX
LD
VX
STO
VOUT
;(1 clock) load vx
;(5 clock) OLDVX + K1·VIN
;(4 clock) the setup for this
instruction occurs during the
previous instruction.
;(4 clock) the setup for this
instruction occurs during the
previous instruction.
;(0 clock) VX=OLDVX +
K1·VIN + K2·VOUT
;(1 clock) begin new
calculation
;( 1 clock) VOUT=VX +
K3·VOUT
Thus this biquad requires 16 cycles to execute. Note
that NK2 = -K2.
7-280
SSI32H6830
Servo DSP
ASSEMBLER INPUT FILE
The assembler input lile contains both DRAM initialization information and IRAM instructions. A typical structure
lor the file is:
;** '* ** *****
*.*. '* '* ** .... '* '* **** '* sample input fil e*'* .. *** **** **.. **** *.*
'*
'*
;sample.asm
;comments extend from; to end 01 line
;indicates the beginning 01 a DRAM section which will specify addresses
.dorg 0
;beginning with O. II no value is specified, the addressing will start where the last
;.dorg section ended.
zero:
data 0
;values can be expressed in decimal
qrtr:
data Ox2000
;or hex
x2:
data 256
data
;DRAM labels are optional
data
prod:
data 0
adc1:
dac1 :
data 0
;more than one label can refer to the same address
temp:
data jump1
;a DRAM value can be another DRAM or IRAM label.
.org
;indicates the beginning of an IRAM section. As in the .dorg case, a value can be
;specified to indicate where in the IRAM the code is to be inserted.
Ids
qrtr Ishl=1
;Ioad qrtr into accumu lator after being shifted by 1 bit to the left
radix
;indicate that multipliers have the radix point 1 bit from left
slo
x2
madd
adc1 qrtr
nop
;store Ox4000 into x2
!Ii
;multiply adc1 times qrtr times two (due to RADIX), update 11
;wait one arith cycle before result is valid for sto or jmp
jf IIi
jump1
;jump if f1 is one
sto
prod
;sto prod if positive
jmp
end
jump1:
;Iabels can be on a line by themselves
sto
dac1
end:
stop
;il neg, send prod to dac1
;******************************* end of sample file *******************
7-281
II
SSI32H6830
Servo DSP
AOOR
1
2
3
4
5
WRITE
DSPSTATUS
READ
ADCS
ADC4
ADC3
A0C2
AOCl
AOCO
DSPIN
SERour
CACl
CAC2
IRAM (512 x 20)
6
7
TIRACK
9
PTIME
PHTIME
•
10
PROGRAM
COUNTER
ADDR
/0
TRACK
DRAM (1961( 16)
ADDR
/
•
ADDR
OATA
t
LOOKUPADDR
;.
7
I
I
JMPADDR/
0
16
•
DRAM BUS
¥
¥
16
¥
MUlTREG
DATA REG
SAT
~
20
I
24
l;-
I
I 24
4S
SHIFTER
.tALU
t
ACCUMULATOR
f4
t
I
SHIFTCTAL
I
l6
QPCODE
SEQUENCER
/5
I
COUNTER CTRL
! ALUCTRl
I
4LSB
FLAG
/ JALUADDR
0
FIGURE 2: Programmer's Model
7-282
SSI32H6830
Servo DSP
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
"!?>
\1
z z\1 z\1 z\1 z\1 z\1 z\1 z\1 z\1 z\1 z\1 z\1
64 63
62 61
60
59
58 57 56
55
z
~ z\1 "
>
54 53 52 51
50 49
DOUT
48
ADVANCE
47
SEROUT
lJiiiii50CIJl
46
~
HAlTDSP
MASTER
RAMBUSV
45
MSCHGAIN
44
POR
iN'i'
43
START
SLEEP
SDATA
SDEN
TD
SClK
COMMU
DSPCK
VND
VNA
11
lOCAL
1N4
TCK
INO
DIN2
IN1
D1N1
1N2
VPD
VPA
IN3
t-
:J
0
x
:J
'"
18
19
20
21
o.
U)
'"
0.
..
">
:
),>----,,
,
CS _________
'.
I
Tda
....
~----~-J,
Cs
,
i
I
I
Tds
"1'",
.. 'Ch
\...__________----'f
ttl
'\,'-----------
.,
,
__I Tsrw'-4-
RiW
______________~____~l
:\
I
~ ~'---T-hrw--------------
\'--_---JI
READY
__: ;.-Tdrdy
MAO:7
FIGURE 3: Motorola Register Multiplexed Read Timing
9-10
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbitls
ALE
AD(7:O)
1
Ta
\
---------'i~~~------~~~,~--------------------------------------As ' Ah
Wds
Wdh
( ' ),
~:)~----------------~'=-~=~~!.~=~~'----------{'=-~=~:'~~=:~.,
,,
,
CS
,
'!~--~~------T__~\
,'-------------
---------------...,-',
'Cs
Tw:
,~~:~
~'_
READY
__:
MA(7:0)
~,4
Ch
,
~,
_______Jl
\------'/
: . -Tdrdy
,~----------------~--------------------------
FIGURE 4: Intel Register MuHiplexed Write Timing
ALE
____~__JI~,.~~Ta---~~~;~---------------------------------
}_
AD(7:0)
As
'
~
}
\
.... ..'
Wds
' Ah
~'.4 ~:
'
Wdh
~
:
"
cs
I
:...
--------------~,,
,
Cs
,
,
~'4
,,',.
'
.'
Ch ,
~'-------------'l
,
~Tsrw'4-
RiW
\'-----------
,
Tds
I
------------~----~\'-~'r_----------~:
~: ~Thrw
READY
MA(7:O)
,
,
--.. i-- Tma
:{
--'
\'--_--1/
:___ Tdrdy
"
FIGURE 5: Motorola Register Multiplexed Write Timing
9-11
II
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbitls
ELECTRICAl.. SPECIFICATIONS (continued)
NON-MULTIPLEXED BUS MICROPROCESSOR INTERFACE TIMINGS (FIGURE 6)
PARAMETER
Tmas
MIN
CONDITIONS
MA(7:0) valid to DS i
NOM
MAX
UNIT
5
ns
Tmah
DS J.. to MA(7:0) invalid
5
ns
Cs
CS valid to DS i
20
ns
Ch
OS J..toCS J..
Tda
RD J.. or DS J.. to Read Data Valid
Except Read of WCS
RD J.. or DS J.. to Read Data Valid
Read ofWCS
Tds
DSwidth
0
ns
30
ns
50
ns
ns
80
OS J.. to read data invalid
Tsrw
RlW valid to DS i
Thrw
DS i to RIW invalid
DS i to READY J.. (Motorola) Note 3
Tdrdy
Wds
Write data valid to R/W i or OS J..
Wdh
R/W i or DS J.. to write data invalid
Note 1: i indicates rising edge
Tdh
0
25
ns
20
ns
20
ns
30.
ns
40
ns
10
ns
J.. indicates falling edge •
Note 2:
Loading capacitor = 30pF
Note 3:
Ready is not shown and is not used by Motorola processors. Timing provided for information only.
~E~------------------------Tmah ~
........'Tmas
MA(7:0)
=:::x
.
,
.
,
K = = '
,~~------------~~
I
I
cs~'
I
I
:\
--..: :""'-cs
~
:____
'.".-'::Ch-
~ --'\'~:,-.=====_Td_S=.====~1.,
-
READ TIMING
AD(7:0) OUT
t
-'
Tda
I
Tdh
>--
-_===~'==x -----------7--',
L.,
,
:\'4__'---Th-rw-
_,
, ,
:~Tsrw
,
,
WdS, •• :•• ~
WRITE TIMING
AD(7:Q) IN
I
~
_
I4--TSIW
I
I
--....
I
I4--Thrw
~ ~,-_'_~_~_ _'--,l
FIGURE 6: Non-Multiplexed Bus Timing Diagrams
9-12
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbit/s
DISK READ/WRITE TIMING (FIGURES 7 AND 8)
PARAMETER
T
RRCLK
CONDITIONS
MIN
Single bit NRZ
20.8
NOM
MAX
UNIT
ns
Dual bit NRZ
41
ns
Single bit NRZ
8.5
ns
Dual bit NRZ
16
T/2
RRCLK high/low time
Tr = Tf
RRCLK rise and fall time
0
ns
2
ns
Os
NRZ in valid to RRCLK i
3
Dh
RRCLK ito NRZ in invalid
4
As'
AMD valid to RRCLK i
3
Dv
RRCLK ito NRZ out
3
20
ns
3
20
ns
Wv'
RRCLK ito WAM out
Note:
i indicates rising edge
-
ns
.
ns
ns
-
J. indicates falling edge
• These specifications are only applicable in the Soft Sector mode.
T
,..
T/2
.'
Tf ..........:
; . - __:
: . - - Tr
RRCLK
NRZD. NRZi
(read)
------------~(~--~>~------------
~
Ds
'
,
,
~
II
FIGURE 7: Disk Read Timing
,
RRCLK
.---/
~
,
~
~
~--~,
~--~,
: :
:
__, Dv
~,
1
NRZ DATA (write)
Dv
I
,,
1
,
FIGURE 8: Disk Write Timing
9-13
1
-...: wv ~
:..-.-:
:
--------------~~
,
I
~
,
,
1
Wv
:-4i
---------------------+:--~(
I
/~---
;.r-,
I
~-----------'
1
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbit/s
ELECTRICAL SPECIFICATIONS (continued)
BUFFER MEMORY READIWRITE TIMING PARAMETERS (FIGURES 9 THROUGH 13)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
T
SVSCLK period
25
ns
T/2
SVSCLK high/low time
10
ns
Tav
SVSCLK t to address valid
Note 1
18
ns
Tmsv
SVSCLK t to MS..1-
Notes 1,6
18
ns
Tmsh
SVSCLK t to MSt
Note 1
18
ns
Tmv
SVSCLK t to MOE..1-
Note 1
18
ns
Tmh
SVSCLK t to MOEt
Note 1
18
ns
Twv
SVSCLK t to WE..1-
Note 1
18
ns
Twh
SVSCLK t to WEt
Note 1
18
ns
Tdov
SVSCLK t to data out valid
Note 1
18
ns
Tdoh
SVSCLK t to data out invalid
Note 1
18
ns
Tdis
Data in valid to MOE t (SRAM)
5
ns
Data in valid to CAS t (DRAM)
5
ns
MOE t to data in valid (SRAM)
0
ns
CAS t to data in valid (DRAM)
0
ns
Tdih
Trv
SVSCLK t to RAS..1-
Note 1
18
ns
Trh
SVSCLK t to RASt
Note 1
18
ns
ns
Trav
SYSCLK to row address valid
Note 1
18
Trah
SVSCLK t to row address invalid
Note 1
18
ns
Tcv
SVSCLK t to CAS..1-
Note 1
18
ns
Tch
SVSCLK t to CASt
Note 1
18
ns
Tcav
SVSCLK t to column address valid
Note 1
18
ns
Tcah
SVSCLK t to column address invalic
0
9-14
ns
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbit/s
BUFFER MEMORY READIWRITE FUNCTIONAL PARAMETERS (FIGURES 9 THROUGH 13)
PARAMETER
CONDITIONS
(continued)
MIN
UNIT
Trwl
RAS.], to RASi
Notes 2,3
«RWL + 3)oT)
ns
Trwh
RASi to RASJ.
Notes 2, 4
«RWH + 1)oT)
ns
Tcwl
CASJ. to CAsi
Note 2
«CWL + 1)oT)
ns
Tcwl
CAsi to CASJ.
Notes 2, 5
«CWL + 1)oT)
ns
Note:
Loading capacitance = 30 pF
Note 1:
The measured delay for any of the signal indicated by this note will not vary from the measured delay
of any other signal indicated by this note by more than ±2 ns.
Note 2:
RWL, RWH, CWL and CWH are fields in the Buffer Manager Timing Control Register (54H). Each
is a two bit field which can contain a value of 0, 1, 2, or 3. These values determine the minimum
number of SYSCLK periods (T) for the associated signal width.
Note 3:
The minimum width value of Trwl will be generated for refresh cycles and for any buffer memeory
access cycle except when multiple page mode accesses are performed. When multiple page mdoe
accesses are performed, the width of the RAS low pulse is extended until the end of the last CAS
low cycle.
Note 4:
The minumum value of Trwh will be generated whenever the Buffer Manager determines that a
buffer request is pending at the ocmpletion of the current memory cycle and a page mode access
can not be used either because page mode operation is not enabled or the needed location is not
within the current page.
Note 5:
The minumum value of Tcwh will be generated only between consecutive page mode accesses.
Note 6:
MS will rise only if the Buffer Manager determines that no additional requests for buffer access are
pending. If the Buffer Manager determines that another access is to be Made, MS is kept low
between the accesses for improved speed.
I
9-15
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbit/s
.,
T
:~••.__~____~_________T_w_b~a~____________~__~.~:
SYSCLK
,,
~
,,
, , '
:~ Tmv
Tmh-+-:
~
----+---~~~----------------~l~------,
10
-...,
BAO:17
:
I
•
I
,~ Tav
--.
:.:.:. Tah
~r-----------'-------:----,*
~------------~--------------------~--~~,~-----
~
- - . : : . - Tmsv
,
~ Tmsh
\~------~---~---~-----r~~l.
----..:, :.., Tdih
BOO:7
-----------4(~_______~____~*,~--~:~~)-------~,
Note: Twba equals one buffer RAM acCess cycle in SYSCLK periods.
FIGURE 9: SRAM Read Timing
9-16
~Tdis
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbit/s
SYSCLK
I
~'I
I
:'-Twv
Twh~
I
I
~
I
I
Y
I
I
I
---'
I
r4-r
I
---'
~Tav
I
~
BAO:17
I
I
~I
~
I
I
I
~I
;"-Tmsv
BOO:7
:---- Tmsh
1.
\
I
I
I
I
~Tdov
-..:
~Tah
I
~
I
:'-Tdoh
~
~
Note: Twba equals one buffer RAM access cycle in SYSCLK periods.
FIGURE 10: SRAM WrHe Timing
9-17
I
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbitls
SYSCLK
Tmsv
BA(11;O)
FIGURE 11: DRAM Timing, Refresh Cycle (Shown with WRL
=0)
SYSCLK
8A(11:0)
READ
BO(7:0)
WRITE
BO(7:0)
FIGURE 12: DRAM Timing, Standard Cycle (Shown with RWL
9-18
=0 and CWL =0)
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbit/s
SYSCLK
BA(11:0)
READ
BO(7:0)
WRITE
BO(7:0)
FIGURE 13: DRAM Timing, Fast Page Cycles (Shown with RWL
=0, RWH =0, CWL =0 and CWH =0)
SYSCLK
b
-----I"
l=
I~.-______~--_4----~~1
Trwl
I-- Tewl - -
------------~I
I
Trwh
--I
~
Tcwh--l
~I_~I
BA(11:0)
FIGURE 14: DRAM Timing (Showing the Relationship of RWL, RWH, CWL and CWH to overall timing)
9-19
II
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbit/s
ELECTRICAL SPECIFICATIONS (continued)
HOST DMA 8116-BIT INTERFACE TIMING PARAMETERS (FIGURE 15)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
DAEQl
DAEQ J, from DACK J,
40
ns
ADTA
lOA J, 10 HD[0:15] valid
50
ns
25
ns
HD[0:15] seluplo lOW
30
WDHlD
i 10 HD[0:15]lri-slale
i
HD[0:15] hold from lOW i
10
ns
AWPUlSE
lOA/lOW pulse width
80
ns
DMASET
DACK J, 10 IOAIIOW J,
0
ns
DMAHlD
DACK hold from IOAIIOW i
0
ns
ADHlD
lOA
WDS
2
ns
,,---_ _ _--.,
OREO
~
'i-,.'-_____-------,-----I/
1
I"
"'1
1 OREOl
~
1
-------'i-,.
;-
1'-' _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J I
.1
I~
OMASET
~~
_______
I~
1
I~
1
1
--------~I-------I
.1
y.(
1
ROTA
:
>K',-------
I~
.1
1
1 ROHLD
1
HO[O:15] (write)
OMAHlO
.1
RWPUlSE
HO[O:151 (read)
.~
1,,------------~II~~==========~~
1
~I
.
1
1
-----------~)Kr--~:---~>K~----------
I..
WOS
.1"
WOHlO
FIGURE 15: Host DMA 8/16·Blt Inter1ace Timing
9-20
.1
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbit/s
HOST DMA 8/16-BIT INTERFACE TIMING PARAMETERS (DEMAND MODE) (FIGURE 16)
PARAMETER
MIN
CONDITIONS
DMASET
DACK .!. to IORIIOW .!.
NOM
MAX
0
UNIT
ns
RDTA
lOR.!. to HD [0:15} valid
RDHlD
lOR ito HD [0:15] tristate
WDS
HD [0:151 setup to lOW i
30
ns
WDHlD
HD [0:15] hold from lOW i
10
ns
2
50
ns
25
ns
RWPUlSE
IORIIOW low
80
ns
RWPAUSE
(ORIIOW high
40
ns
DREOl
DREO .!. from IORIiOW .!.
DMAHlD
DACK hold from (ORIIOW i
40
ns
ns
0
,
DREO
~~-D-MA-S-E-T------------------------~~~______________
~,
,
-----.--.;
DMAHLD
,
,~,~
:
:
~,...----
'~'__________________________+ -__-4'-J~
:...
"
~;...
RWPUlSE
~,...
RWPAUSE
,~.______----"/i'/
---..:
HD[O:15] (read)
,
:
~,
RDHlD :
;. . . . . . . :
I
,
'"
v,...--+--------'--------,,-------/'
___----'bK---'-:==x----,..------..X
I
I
,
HDIO:15] (write)
'...
~
: RDTA
~:
, DREOl ,
WDS
,
==========~~~:~X~
~
WDHlD
_____x===x_____ I
FIGURE 16: Host DMA 8/16-Bit Interface Timing (Demand Mode)
9-21
X,--_
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbit/s
ELECTRICAL SPECIFICATIONS (continued)
HOST PROGRAMMED I/O TIMING PARAMETERS (FIGURE 16)
PARAMETER
CONDITIONS
MIN
NOM
HCSO J." AO:2, A9 J." or
HSC1 ito IOCS16 J.,
CS16L
IOCHL
IORIIOW J., to IOCHRDY J.,
IOCHTW·
IOCHRDY pulse width
0
MAX
UNIT
25
ns
30
ns
5x
BCLK
ns
50
ns
20
ns
RDTA
lOR J., to HD[0:15) valid
RDHLD
lOR ito HD[0:15) tri-state
WDS
HD[0:15) setup to lOW i
30
ns
WDHLD
HD[0:15) hold from lOW i
10
ns
2
---
-------~--~,-,.-~-
- - - - t--------
--
RWPULSE
IORIIOW pulse width
80
ns
ADRSET
HCSO, AO:2, A9/HCS1
setup to IORIIOW J.,
25
ns
ADRHLD
HCSO, AO:2, A9,HCS1 hold,
from IORIIOW i
5
ns
• Maximum specification applies when Auto Wait State Generation is disabled (Register 40H, Bit 2 is reset)
RESET ASSERTION TIMING PARAMETERS (FIGURE 17)
PARAMETER
CONDITIONS
MIN
Trpwl
Not power on reset
500
ns
Power on reset
7.5
J.lS
RST pulse width low
9-22
NOM
MAX
UNIT
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbitls
-'X'_________________----JX'_____
AO:2.A9 _ _ _ _
~~-----'><~----------------~>C'----!~16~'----------------~-J~
,'"
AORSET
..
,"
RWPULSE
,
,
~
..
IOCHL-:
II
IOCHlW
.'X
ROTA
X..
AORHLO
,(
'
WOS
FIGURE 16: Host Programmed I/O 8/16-81t Timing
SYSCLK
RST
Trpwl
:...
'\
I
"
"
Note: RST must be low for a minimum of 11 periods of SYSCLK.
FIGURE 17: RESET Assertion Timing
9-23
...:
/
SSI32C9001
PC-AT Combo Controller
With Reed Solomon, 48 Mbit/s
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
BA10
BAll/DMOE
BAl21RAS
BA13IBDP
BA14/FAULT
GND
BA 15/MS/READY/AINT
BA 16IMS/INPUT
WE
CAS/SMOE
SYSCLK
VDD
GND
RST
RRCLK
AMD/SECTOR
INDEX/INPUT
NRZO
NRZl
OUTPUT
WG
RG
DINT/INT
MA7
MAS
76
~
...« ~ '"« :;f '"«
0
~< ~ z(!l
'"
C1i
III III III III III III III III III
...'"
t'!: ......
"''''
~O
......
lll$
'"to
to
'"
III III
"'''"
'" 0'" III0
III III III III
'"
~l3 to <0 ~ml8
...
0
°l~
za:
...
ex> to
III III III
0
III (!lI I
0
to'"
'" "''''
0
I
0
I
Ulif/l ~u;
50
49
48
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
47
46
HDBll
45
44
HDB3
HDB12
HDB2
41
HDB13
40
HVDD
39
HDBl
HDB14
HOBO
36
35
34
GND
lOW
32
lOR
31
30
IORDY
DACK
29
IRQ
IOCS16
26
...J
'" ...0« '"0« '"0« 0«
0 0
'" '" ~ 0 I::' 10> I~ 0 0 z
'"« ::.«"" ««««~O
::.
> (!l
::. ::. ::. ::. ~ ICs ,
HDB9
Al
PDIAG
0
«
;:
«
100-Lead TQFP
Advance Information: Indicates a product still in the design cycle. and any specifications are based on design goals only. Do not use for final
design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents. patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly. the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems. Inc.• 14351 Myford Road. Tustin. CA 92680-7022 (714) 573-6000. FAX: (714) 573-6914
0194 - rev.
9-24
©1992 Silicon Systems. Inc.
Patents Pending: (91-060) (91-057)
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
'4'4 II "ll;k' ,;, .mg.
January 1994
DESCRIPTION
FEATURES
The SSI32C9003 is an advanced CMOS VLSI device
which integrates major portions of the hardware
needed to build an ATA disk drive. The 32C9003 has
a dual bit NRZ interface to allow interfacing with channel ICs supporting this interface. The circuitry of the
SSI 32C9003 includes a complete ATA interface, an
advanced buffer manager, a high performance disk
formatter and an 88 bit Reed-Solomon ECC with fast
"on-the-fly" hardware correction. The SSI 32C9003
provides maximum performance while minimizing micro controller intervention.
•
ATA Interface
Single chip PC AT controller
Full ANSI ATA compliance
Direct PC bus connection with on board 24
mA drivers
PC transfers to 6.7 megawords per second
Supports PIO, DMA and Multiword DMA
(EISA Class B Demand DMA)
Logic for daisy chaining 2 drives
Operate as master, slave or both
The SSI 32C9003 is capable of transfers of up to 80
megabits per second on the disk interface and 6
megawords per second across the ATA bus. In
addition, on-the-fly error corrections and microcontroller accesses to the buffer memory can occur
during transfers.
Hardware support for write-multiple and
read-multiple commands
Automatic command decoding of Write,
Write Long, Write DMA, Write Multiple,
Write Buffer and Format commands
(continued)
(continued)
BLOCK DIAGRAM
"I
1- - HOsTtNTERFACE I
HDB (15:0)
A: Pl.:.:
r-=:::::J
H-..::::.J
1
1OW~ '----"'""I
I ~
IORDY
~
HOST FIFO
16 BYTE
J
DREQ
~
TASK FILE
I
I
I
rs.
I
f----:--+
HOST
CONTROL
AD (7:0)
MA (7:0)
I
;:r9""~~___=-=~=-=c=-c~
~
mll!ll1 .,
WIliRJW~
r'
READV/AlI'JT r'
mITr'
lmlT/mT
~
I
I
H---
_:
~
I I
Ir-+---..~o :~~7:0)
BUFFER
ARBITRATOR
,
I
II.
I
1
'-r
+----+!-? BA17~/m
BA16/lViS"
~ BA(15:O)
I
~~
1---~1~1~'i~:::::::C:::ON==T::::RO::::L~f~
..c~I-=-=====.-o~
~~
1-0
J
~
I
DRAM/SRAM
I
f--r---'"
FAULT
L
.r! RG
I
SEQ~~~CER f-----+-':'-----------~
1+--+-'~---------__1
f--f-1----------I'"i~J~ "AI~----~(-oD~A~~A~~~-----~
,,
CS __________
:...
Tda
_:
,
: lr----~----------~----~\
,
,L-----,
~,
, ,,
,"
Cs
.'",
.'1.
,
Tr
,
\,
,
,1..READY
,
,
I
__ ;--Tma
MA(7:0)
--,
,
Ch
/
\'--_ _--.J
:~Tdrdy
:(
FIGURE 2: Intel Register Multiplexed Read Timing
9'34
.,
,
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
ALE
________
-J{~~.---~T=a----~~~L------------------------------------------
t ..
~
AD(7:0)
Tdh
As .: .. Ah .. ,
ADDRESS
~
}
DA~A
(
,
Tda
I I
~
I
,....----------I~~,
\
, L-_________
CS
~:4---~C=S~-~~:44~----~T=dS~--~~~:~----C-h--~~~:
,
,
\'-_____--'t
,
,,
...... Tsrw r4-R/W
:, \'-----------------,
----7----',
...... ,4-Thrw
\'--_--'1
:___ Tdrdy
READY
,
~~Tma
:(
, ,'------------------------------------------------
MA(7:0)
FIGURE 3: Motorola Register Multiplexed Read Timing
,
ALE
I..,
r
As
AD(7:0)
~\L------------------------------------------
Wds Wdh
Ta
~--------~,
,
CS
,
,
:..
,
~,.
Ah
~~
' . . . . . I ...
.,.1
,,
,
Cs
.,.
,
,
Tw
.,
,
\'------
\'----_ _ _ _ _...11.
WR
, Ch '
,~,
,
READY
,
~,
-..:
MA(7:0)
\'--_--'1
:___ Tdrdy
~Tma
'(
FIGURE 4: Intel Register Multiplexed Write Timing
9-35
II
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
ALE
.\~-------~------------__
_______1..
Ta
,;'--'-'--<'-,
As
AD(7:0)
Ah
Wds
Wdh
--------~'=·~=·~:=·~=·1'
(
r------~'=.~=.=:'.==~.J'~------~: {
"
CS
,
~
RiW
.
\, ' - - - - - - ,
Td.
Cs
Ch
'
"'1- .. :
~L_ _ _ _ _..-J/'
,
_ _ _ _ _ _ _ _-+_ _ _
....
.:..,'Tsrw~
'\
:[
,,
'
~
READY
,
----
~Thrw
~'-----'/
~Tdrdy
MA(7:0)
FIGURE 5: Motorola Register Multiplexed Write Timing
ALE
~:Tmas
Tmah~1
--v
'
~---+-----------+----1r--
V - - ,
MA(7:0)
cs
-1
~I
I4--Cs
"L,---=-_
~
:~Ch
ns----;*~~·~~~~~~~=_T_dS_-~~~~~~~~:(r----READ TIMING
AO(7:O) OUT
~
i
.-'"--;>--
---...J:-""'x:;---------'-~
Tdh
: \c.____
~
WRITE TIMING
AO(7:O) IN
:..-Thrw
____~-------~W~dS~:.~.~:.~=,.)~"Wd-h
~
v---~
~Tsrw
~
I4--Thrw
R1W ~'-_ _ _ _ _ _ _ _ _~l
FIGURE 6: Non-Multiplexed Bus Timing Diagrams
9-36
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
ELECTRICAL SPECIFICATIONS (continued)
Disk Read/Write Timing (Figure 7)
PARAMETER
CONDITIONS
Trrc
Trrc
Trrcl
Trrcl
Trrch
Trrch
Dis
Dih
As
RRCLK period (dual bit)
RRCLK period (single bit)
RRCLK low time (dual bit)
RRCLK low time (single bit)
RRCLK high time (dual bit)
RRCLK high time (single bit)
NRZ in valid to RRCLK high
RRCLK high to NRZ in invalid
AMD valid to RRCLK high
(soft sector only)
Dv
RRCLK high to NRZ1, NRZO
out valid
Dvw
WCLK low to NRZ1, NRZO
out valid
Trwl
RRCLK high to WCLK low
Trwh
RRCLK low to WCLK high
Twckh
WCLK high time (dual bit)
Twckh
WCLK high time (single bit)
Twckl
WCLK low time (dual bit)
Twckl
WCLK low time (single bit)
Note: Loading capacitance = 10 pF
MIN
NOM
MAX
27.8
20.8
11.1
8.5
11.1
8.5
3
3
3
-3
8.3
6.3
8.3
6.3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
18
ns
+3
ns
18
18
ns
ns
ns
ns
ns
ns
II
FIGURE 7: Disk Interface Timing
9-37
SSI32C9003
PC..AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
ELECTRICAL SPECIFICATIONS (continued)
BUFFER MEMORY READIWRITE TIMING PARAMETERS (Figures 8 through 14)
MIN
PARAMETER
NOM
MAX
UNIT
T
SYSCLK period
25
ns
T/2
SYSCLK high/low time
10
ns
Tav
SYSCLK i to address valid (Note 1)
18
ns
Tmsv
SYSCLK i to MS .l. (Notes 1, 6)
18
ns
Tmsh
SYSCLK i to MS,l, (Note 1)
18
ns
Tmv
SYSCLK i to MOE .l. (Note 1)
18
ns
Tmh
SYSCLK i to MOE.l. (Note 1)
18
ns
Twv
SYSCLK i to WE .l. (Note 1)
18
ns
Twh
SYSCLK i to WE .l. (Note. 1)
18
ns
Tdov
SYSCLK i to data out valid (Note 1)
18
ns
Tdoh
SYSCLK i to data out invalid (Note 1)
18
ns
Tdis
Data in valid to MOE i (SRAM)
5
ns
0
ns
Data in valid to CAS i (DRAM)
Tdih
MOE i to data in valid (SRAM)
CAS i to data in valid (DRAM)
Trv
SYSCLK i to RAS " (Note 1)
18
ns
Trh
SYSCLK i to RAS
18
ns
Trav
SYSCLK i to row address valid (Note 1)
18
ns
Trah
SYSCLK i to row address invalid (Note 1)
18
ns
Tcv
SYSCLK i to CAS .l. (Note 1)
18
ns
Tch
SYSCLK i to CAS i (Note 1)
18
ns
Tcav
SYSCLK i to column address valid (Note 1)
18
ns
Tcah
SYSCLK i to column address invalid
i (Note 1)
0
9-38
ns
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
BUFFER MEMORY READIWRITE FUNCTIONAL PARAMETERS (Figures 8 through 14) (continued)
PARAMETER
CONDITIONS
TYPICAL
UNIT
Trwl
RAS J.,to RAS i
Notes 2, 3
(RWL + 3)-T
ns
Trwh
RAS i to RAS J.,
Notes 2,4
(RWH + 1)·T
ns
Tcwl
CAS J.,to CAS i
Note 2
(CWL + 1)·T
ns
Tcwh
CAS ito CAS J.,
Notes 2, 5
(CWL+ 1)·T
ns
Notes:
Loading capacitance = 30 pF
Note 1:
The measured delay for any of the signal indicated by this note will not vary from the measured delay
of any other signal indicated by this note by more than ±2 ns.
Note 2:
RWL, RWH, CWL.and CWH are fields in the Buffer Manager Timing Control Register (54H). Each
is a two bit field which can contain a value of 0, 1, 2, or 3. These values determine the minimum
number of SYSCLK periods (T) for the associated signal width.
Note 3:
The minimum width value of Trwl will be generated for refresh cycles and for any buffer memory
access cycle except when multiple page mode accesses are performed. When multiple page mode
accesses are performed, the width of the RAS low pulse is extended until the end of the last CAS
low cycle.
Note 4:
The minumum value of Trwh will be generated whenever the Buffer Manager determines that a
buffer request is pending at the completion of the current memory cycle and a page mode access
can not be used because the needed location is not within the current page, or a new memory
request is being processed.
Note 5:
The minumum value of Tcwh will be generated only between consecutive page mode accesses.
Note 6:
MS will rise only if the Buffer Manager determines that no additional requests for buffer access are
pending. If the Buffer Manager determines that another access is to be made, MS is kept low
between the accesses for improved speed.
II
9-39
551 32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
SYSCLK
~:
I~Tmv
Tmh~:
~,.--'_ _ __
--~-~~~~-----------r,~t
----:---,
____I
:,
~:
BA(17:0)
......... Tmsv
I
~:
,--
~~.--------------+-T'~~
~
:--- Tav
;..- lav
~--------------~~~
~
B0(7:0)
. : . . - Tmsh
r--
Tdih
----------------------------------~~r------,
,
~
~Tdis
Note: Twba is a functional parameter that gives the duration of one RAM data buffer access cycle in SYSCLK
periods. The value is programmed in bits 1-0 of register 54H. These examples show Twba = 4T.
FIGURE 8: SRAM Read Timing
SYSCLK
~
Twh~
+- TM'
;",--;-'_______
------;-------,~~'------------------------'-~1
,:
,
BA(17:0)
~
~Tmsv
~
~fu
~
14- Tmsh
'~fu
~~--------------~t===
'----------------------------------~,
80(7:0)
FIGURE 9: SRAM Write Timing
9-40
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
SYSCLK
Tmsv
BA(11:0)
FIGURE 10: DRAM Timing, Refresh Cycle (Shown with WRL
= 0)
SYSCLK
Mg
~
II
CAS
MOE"
BA(11:0)
READ
~
BO(7:0)
WRITE
~
BO(7:0)
FIGURE 11: DRAM Timing, Standard Cycle (Shown with RWL
9-41
=0 and CWL =0)
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual BitNRZ Interface
SYSCLK
BA(11:0)
READ
BD(7:0)
WRITE
BD(7:0)
FIGURE 12: DRAM Timing, Fast Page Cycles (Shown with RWL
= 0, RWH = 0, CWL = 0 and CWH = 0)
SYSCLK
b
- - - - t -I
1=
I~
~.------~----r_--~--~I
I---l
------------11
I
,---I---,I
Trwl
Tcwl - -
Tcwh
Trwh
--I
~
BA(11:0)
FIGURE 13: DRAM Timing (Showing the Relationship of RWL, RWH, CWL and CWH to overalttiming)
9-42
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
ELECTRICAL SPECIFICATIONS
(continued)
AT Host Interface Timing Parameters
MIN
PARAMETER
NOM
MAX
UNIT
DREQl
DACK .J, to DREQ .J,
40
ns
DREQD
lOR .J, or lOW .J, to DREQ .J,
40
ns
50
ns
RDTA
lOR .J, to HD(15:0) valid
DMASET
DACK .! to lOW.! or lOR .J,
ns
0
i or lOW i to DACK i
DMAHlD
lOR
RDHlD
lOR ito HD (15:0) hi-Z
2
ns
WDS
HD(15:0) setup to lOW i
30
ns
WDHlD
HD(15:0) hold from lOW i
10
ns
RWPUlSE lOR or lOW low pulse width
80
ns
RWH
lOR or lOW high pulse width
50
CS16l
HCSO .J" A(2:0) .!, A9.J, or HCS1 ito IOCS16.!
0
20
ns
ns
20
ns
25
ns
IOCHl
lOR or lOW .J, to IOCHRDY .J,
ADRSET
HCSO, A(2:0), A9/HCS1 setup to lOR .J, or IOW.J,
25
ns
ADRHlD
HCSO, A(2:0), A9/HCS1 hold from lOR i or lOW i
5
ns
Note: Loading capacitance = 30 pF
Functional Specification
PARAMETER
IOCHTW
CONDITIONS
IOCHRDY pulse width
MIN
0
NOM
MAX
UNIT
5xBCLK
ns
II
9-43
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--J~
1
DREO
,~
~,
I DREOl
I
--------~~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___J~
:~
I
I~
I
~I
RWPUlSE
1
-------------r'-----~
1
~
:
HD[O:15) (read)
~:
RWH
1
/,~------~------~~
----------------~~
,~
1
~~_ _ _ _ _ _ _ _ ____
1
'-.
~I
1 RDHlD
I
~I
RDTA
0
1
I
~~---~:---~%~----------
HD[O:15) (write)
----------------"
'~
~,~
WDS
~I
WDHlD
FIGURE 14: Host DMA 8-16 Bit Interface Timing (Non-demand mode)
AO:2
____
,-=>K~___
--,-----~*
1
------~ 'r_---------------------~
________~~
Ir-_____
>K~
~
1
CS16L
______~
/
1 ~---------------------+-~
I ..
RWH
)'
lORiioW
.. I
RW PULSE
AORHLO
ADRSET
IOCHL~
~
i lll
.'
~
1
1
{
~i
IOCHTW
1
>K
HD[O:15] (read)
-I
ROTA
I
HD[O:15) (writej
r--------'----~Ir_----------
________________~>KI~========~I~====~>K~-------------1l1li
~
~i"
WDS
.. I
WOHLD
FIGURE 15: Host Programmed 1/08-16 Bit Timing
9-44
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
DREQ
'.
------/
~'----------~'
:. ~,
,
1
:
DREQD
: .
1
,~--_
DMAHLD
~~_______'._______~_____
. ~;,C________
~:.
,
DMASET
RW PULSE
,
...:.'
~:
RWH
1
-----~----~~~---~),I~------~~-,--------------~-~'r_~----~,r_-------
'.
,
HD[O:15] (read)
,
HD[O:15] (write)
I. . .'
).(:
RDATA
~'
1
1
1
X'--___
RDHLD
•
,
----------------~>(~-----~X~--
:.
WDS
~I"
WDHLD
~:
FIGURE 16: Host DMA 8/16·81t Interface Timing (Demand Mode)
ELECTRICAL SPECIFICATIONS (continued)
RESET Assertion Timing Parameters (Figure 17)
PARAMETER
Trpwi
RST pulse width low
CONDITIONS
MIN
NOT Power On Reset
500
ns
Power On Reset
7.5
J.LS
NOM
MAX
SYSCLK
:..
mrr
Trpwl
.:
----------~~~__~____~/,~,----------~l.r------
FIGURE 17: RESET Assertion Timing
9-45
UNIT
II
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
ADO
HDB3
62
29
63
64
28
27
65
66
26
25
67
24
HDB14
HDBO
68
23
AD7
69
22
VDD
HDB15
GND
70
71
21
GND
20
MAO
DREQ
72
73
19
18
MAl
74
17
IORDY
75
16
MA3
MA4
iJACK
76
15
GND
77
78
14
13
12
MA7
VDD
GND
ALE
HDB12
HDB2
HDB13
GND
HVDD
HDBl
lOW
m
HVDD
IRQ
ADl
AD2
AD3
AD4
ADS
AD6
MA2
MA5
MA6
lOCSf6
79
80
A1
81
11
10
JS!WiG
82
9
lm/os
AD
83
A2
84
8
7
WRiRiW
CS
HCSO
FICS1
l5ASJl"
85
6
5
"RSi
4
GND
VDD
GND
86
87
88
BAD
89
BAl
90
~
120-Lead TQFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
9-46
~
"
•
~ ~
3
2
SYSCLK
~fJS
WE
SSI32C9003
PC-AT Combo Controller
80 Mbit/s, Dual Bit NRZ Interface
GNO
BA6
103
104
64
GNO
63
62
HOBll
HOB4
61
HOB10
BAS
105
106
BAg
107
60
HOB5
BAlD
BAll
VOO
GNO
108
109
110
111
59
58
HVOO
GNO
57
HOB9
BA12
112
HOB6
HOB8
BA13
BA14
BA15
113
114
56
55
54
~
115
53
52
BA16f~
116
51
VOO
BA17f~
117
50
VOO
GNO
118
119
49
48
BOP
120
121
47
FAULT
INPUT
INDEX
AMlifSECTOR
RRCLK
122
45
GNO
B02
123
44
NRZl
B03
124
43
NRZO
B04
B05
125
126
WCLK
OUTPUT
B06
B07
127.
128
42
41
40
39
RG
BA7
BOO
BOl
CAUTION: Use handling procedures necessary
for a static sensitive component.
46
HOB7
GNO
WG
128-Lead TQFP
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
120-Lead TOFP
SS132C9003-CGT2
SSI 32C9003-CGT2
128-Lead TOFP
SS132C9003-CGT
SSI 32C9003-CGT
128-Lead OFP
SSI 32C9003-CG
SSI 32C9003-CG
Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX: (714) 573-6914
0194 - rev.
Patents Pending: 93-119,91-057
9-47
©1993 Silicon Systems, Inc.
I
Notes:
9-48
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
tiU ti' niJ Mt.,;, .6" t" ,.
January 1994
DESCRIPTION
FEATURES
The SSI32C9020 is an advanced CMOS VLSI device
which integrates major portions of the hardware
needed to build an SCSI disk drive. The circuitry of the
SSI 32C9020 includes a complete SCSI target
interface, an advanced buffer manager, a high
performance disk formatter and an 88-bit ReedSolomon ECC with fast "on-the-fly" hardware
correction. The SSI 32C9020 provides maximum
performance while minimizing micro controller
intervention.
•
SCSI Bus Interface
Full SCSI-2 Compatibility
Direct bus interface logic with on-Chip
48 mA drivers
Synchronous transfer rates up to
10 megabytes per second
Asynchronous transfer rates up to
5 megabytes per second
Parity generation and checking
The SSI32C9020 is capable of concurrent transfers of
up to 48 megabits per second on the disk interface and
10 megabytes per second across the SCSI bus. In
addition, on-the-f1y error corrections and micro
controller accesses to the buffer memory will not
degrade the throughput during transfers.
The SSI32C9020 is one of a family of Silicon Systems'
single chip disk controllers which support a wide range
Auto Command Mode (ACM) SCSI state
machine performs high level SCSI
sequences without microprocessor
Intervention
Four level ACM command FIFO supports
automatic execution of multiple ACM
commands
(continued)
(continued)
BLOCK DIAGRAM
GPIOO-2
PAREN
SOB (7:0)
~
~
~ID
8
~
~
:
CS
ALEIM!NiiiI
~
WRlRiW
DiNT
SiNi
RST
0194 - rev.
...---
g
?1.
Q
.~
READY
I
~
RDIOS
,
~
r+
I
I
I
I
I
I
MICRO.
PROCESSOR
INTERFACE
i
I
I
I
I
I
I
DlsKFORMA ITER - SEQUENCER
WCS
31 X5
-I
~
I
I
I
I
I
4-.
DRAMISRAM
CONTROL
I
I
1
I
-r
I
r'o BA16iRAS
:1
BA17,cps
:1
BA(lS:O)
WE
I
I
I
I
I
MOE"
i:1 MS
~
_F Ats
SYSCLK
F
r rl
Jo'
""
L--------------l
11
DISK FIFO
8 BYTE
I
SERDES
I
l.(
STACK
SPLIT FIELD
SUPPORT
LOGIC
'l '- -,
J ~
'-----
II
I
ECC
CHKIGEN
I,
t
:
~I':
ECC
CORRECTOR
t
I
J
L __________________________
---_._-_._--
9-49
INPUT/oUTPUT
INDEX
RG.WG
J" RRCLK
11
C
0
M
P
A
R
E
BO(7:0)
Q BOP
I
I
BUFFER
ARBITRATOR
I
I
AD (7:0)
DATA
MULTIPLEXER
H
SCSI
INTERFACE
I
MA(7:0)
H
rI
A'fN
Itm:
I
Q
I/O ~
BSY
I BUFFER MANAGER
HOST DATA BUS
~P BUS
I
I
~
NRZ
II
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
DESCRIPTION
•
(continued)
of device interfaces. The SSI 32C9022 provides the
same basic capabilities as the SSI 32C9020 but has a
dual NRZ disk interface. Other family members
support AT and PCMCIA interfaces. All members are
based on a common architecture allowing major
portions offirmwareto be reused. The Silicon Systems'
chip family is illustrated in the hierarchy chart shown in
Figure 1.
The high level of integration within the SSI 32C9020
represents a major reduction in parts count. When the
SSI 32C9020 SCSI Controller is combined with the
SSI 32R2010 Read/Write device, the SSI 32P3000
Pulse Detector, the SSI 3205391 Data Synchronizer
with 1,7 ENDEC, the 32H4631 Servo and Motor Speed
Controller, an appropriate micro controller and
memory, a complete, cost efficient, high performance
intelligent drive solution is created.
•
FEATURES (continued)
Hardware support for automatic handling of
SCSI-2 command queuing
Automatic SCSI COB size determination
Automatic SCSI Disconnect and Reconnect
Sixteen byte data FIFO between SCSI
channel and Buffer Manager
Buffer Manager
Direct support of DRAM or SRAM
SRAM throughput to 20 megabytes per
second
SRAM size up to 256k bytes
DRAM throughput to 17.78 megabytes per
second
DRAM size up to 1 megabyte
Programmable memory timing
Buffer RAM segmentation with flexible
segment sizes from 256 bytes to 1 megabyte
Dedicated host, disk and microprocessor
address pointers
Internal buffer protection circuit provides
buffer integrity
Disk Formatter
NRZ Data Rates to 48 megabitsls
Automatic multi-sector transfer
Header or microprocessor based· split data
field support
Advanced sequencer organized in 31 x 5
bytes
88-bit Reed Solomon ECC with "on-the-fly"
fast hardware correction circuitry
32 Mbitls NRZ.
AT Controller,
56· Bit ECC
32 Mbitls NRZ,
SCSI Controller,
88·Bil RlS ECC
48 Mbitls NRZ,
AT Controller,
88·Bit RlS ECC
48 Mbitls NRZ,
SCSI Controller,
88-Bit RlS ECC
Dual·Bit NRZ
48 Mbitls NRZ.
PCMCINATA Controller,
88-Bit RlS ECC
Dual-bit NRZ
3V15V
48 Mbitls NRZ,
ATA Controller.
88·Bit RlS ECC
Dual-bit NRZ
3V15V
48 Mbitls NRZ,
ATA Controller,
88-Bit RlS ECC
Dual-Bit NRZ
3V15V
80 Mbitls NRZ,
ATA Controller,
88-Bit RlS ECC
Dual BitNRZ
80 Mbitls NRZ,
SCSI Controller,
88-Bil RlS ECC
Dual-Bil NRZ
160 Mbitls NRZ,
ATA Controller,
144-Bil RlS ECC
Dual-/8-bit NRZ
160 Mbitls NRZ,
SCSI-3 Conlroller,
144·Bil RlS ECC
Dual·/8-bit NRZ
SCSI Differential
FIGURE 1: Silicon Systems' Disk Controller Chip Hierarchy
9-50
80 Mbitls NRZ,
SCSI Conlroller,
88-Bil RlS ECC
Dual·8iINRZ
SCSI Differential
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
-
•
•
Capable of correcting up to four 1O-bit symbols
in error
Guaranteed to correct one 31-bit burst or two
11-bit bu rsts
Hardware on-the-fly correction of either an 11or 31-bit single burst error within a half sector
time
Detects up to one 51-bit burst or three 11-bit
bursts
Microprocessor Interface
Supports both multiplexed or non-multiplexed
microprocessors
Separate or combined host and disk interrupts
Programmable wait state insertion
Other Features
Internal power down mode
Available in 100-pin QFP
FUNCTIONAL DESCRIPTION
The SSI 32C9020 contains the following four major
functional blocks:
Microprocessor Interface
SCSI Interface
bandwidth capabilities of the Buffer Manager
guarantee sustained full speed transfers across the
SCSI bus. The high level of automation of the ACM
minimizes SCSI bus overhead. The net result is
maximized performance with minimum SCSI bus band
width utilization.
The Disk Formatter performs the serialization and
deserialization of data. It provides all of the necessary
functions to control track formatting. header search.
and the reading and writing .of data. The heart of the
Disk Formatter is an advanced programmable
sequencer which is flexible enough to interface to a
wide variety of readlwrite channels. The sequencer
can contain 31 instructions. each of which is 5 bytes
(40 bits) in width. The width of the instructions allows
for sophisticated branching techniques which increase
the flexibility and power of the sequencer. The flexible
disk interface can be configured through a wide range
of capabilities. This allows the SSI 32C9020 to
interface with nearly any readlwrite channel and allows
the user of the SSI 32C9020 to select the readlwrite
channel best suited to the device. Of course. by
selecting the SSI 32C9020 controller and the
SSI 32D5391 Data Synchronizer with 1.7 EN DEC. you
are guaranteed a problem free interface.
Within the Disk Formatter are the ECC generator/
checker and ECC corrector. The generator/checker
provides the ability to generate or check a 32-bit ECC
for headers and an SS-bit Reed Solomon code for data.
If the checker detects an error in an 88-bit Reed
Solomon data field. the syndrome information is
transferred into the corrector. The corrector performs
the necessary operations to determine if the error was
correctable and interfaces directly with the buffer
controller to perform the correction automatically.
The corrector performs its correction within one haH of
a sector time. This guarantees that the corrector will
always be available to correct the next sector if
necessary.
Disk Formatter
Buffer Manager
The Microprocessor Interface allows the local
microprocessor access to all of the SSI 32C9020
internal control registers and any location within the
buffer memory. The microprocessor. by writing and
reading the internal registers can control all activities of
the SSI 32C9020. The microprocessor can elect to
perform SCSI and/or disk operations directly. or it can
.enable the advanced features of the SSI 32C9020
which can perform all typical operations automatically.
The SCSI Interface block handles all SCSI activities.
The SCSI interface includes 48 mA drivers allowing for
direct connection of the SSI32C9020 to the SCSI bus.
The SCSI interface logic includes Auto Command
Mode (ACM) logic. an advanced state machine
capable of handling a variety of complex SCSI
sequences without microprocessor intervention. The
microprocessor can queue up to four ACM commands
into the ACM Command FIFO to create even more
sophisticated command sequences. The SCSI block
interfaces directly with the Buffer Manager via an
internal speed matching FIFO. This FIFO. plus the
As its name implies. the Buffer Manager manages the
data buffer of the controller. The Buffer Manager can
support either SRAM or DRAM. When configured to
operate with DRAM. the Buffer Manager automatically
performs necessary refresh cycles. The buffer
manager creates all of the necessary timing and
control signals for a wide range of memory types and
speeds. The Buffer Manager interfaces with the buffer
memory. the SCSI Interface block. the data path of the
Disk Formatter block. the ECC corrector and the
microprocessor. If more than one of these devices
9-51
9
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
requires access to the buffer memory, the Buffer
Manager arbitrates the requests automatically. The
Buffer Manager of the SSI 32C9020 can sustain SCSI
operations at the rate of 10 megabytes per second,
Disk Formatter operations at 48 megabits per second
(6 megabytes per second) and still have sufficient band
width left to handle on-the-fly ECC corrections and
microprocessor accesses without degrading
performance on any of the interfaces.
.
PIN DESCRIPTION
The following convention is used in the pin description:
(I)
denotes an input
(0)
denotes an output
(Z)
denotes a tri-state output
(OD)
denotes an open drain output
GENERAL
NAME
TYPE
DESCRIPTION
VDD
POWER SUPPLY PIN, VCC
GND
GROUND
HOST INTERFACE
SDBP
I/O
SCSI DATA BUS PARITY. Odd parity bit for the SCSI data bus;
SDB(7:0)
I/O
SCSI DATA BUS BITS 7-0.
ATTENTION. This active low signal is used by the initiator to request a
message out phase.
ATN
I
BSY
I/O
ACK
I
SRST
I
SCSI RESET. This active low signal is used to reset the SCSI controller.
MSG
0
MESSAGE. This active low signal is used to indicate a message phase.
SEL
I/O
SELECT. This active low signal is used to indicate either a selection or
reselection phase.
C/D
0
COMMAND/DATA. This signal is used to indicate either a command or data
phase.
REQ
I
REQUEST. This active low signal is used in the handshake protocol to initiate
,
a data byte transfer.
T/O
I
INPUT/OUTPUT. This signal is used to indicate the direction of data transfer.
PAR EN
I
SCSI PARITY ENABLE. This active high .signal is used to enable parity
checking of the SCSI data bus. Parity checking is disabled when this pin is
held low.
BUSY. This active low signal is used to indicate when the bus is active.
ACKNOWLEDGE. This active low signal is used in the handshake protocol to .
indicate the completion of a data byte transfer.
9-52
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
DISK INTERFACE
NAME
GPI0(2:0)
TYPE
1/0
INDEX
I
INPUTI
1/0
DESCRIPTION
INPUT/OUTPUT. These pins are used to indicate the SCSI ID of the target
device. The pins can be programmed as outputs for test purposes only.
INDEX. Input for index pulse received from the drive.
DISK SEQUENCER INPUT/OUTPUT. Ageneral purpose control (output) and
status (input) pin configured by the Output Enable Bit of Register 71 H, bit 7.
At power-on, this pin is an input. As an input, it can be used to synchronize the
disk sequencer to an external event. As an output, it is controlled by bit 2 of the
Control Field of the disk sequencer.
AMD/SECTOR
I/O
ADDRESS MARK DETECT/SECTOR. This pin is used in the hard sector
mode as the sector input. A pulse on this pin indicates a sector mark is found.
In the soft sector mode a lOW-level input indicates an address mark was
detected. The device powers up in soft sector default mode.
RG
0
READ GATE. During disk data read, this pin is asserted. Active high.
WG
0
WRITE GATE. During disk data write, this pin is asserted. Active high.
RRCLK
I
READ/REFERENCE CLOCK. This pin is used to clock data on the NRZ pin
into and out of the device.
1/0
NON RETURN TO ZERO. This Signal is the read data input from the disk drive
when the read gate signal is asserted; it is the write data output to the disk drive
when the write gate Signal is asserted.
NRZO
MICROPROCESSOR INTERFACE
RST
I
RESET. An asserted low input generates a component reset that holds the
internal registers at reset, stops all operations within the chip, and deasserts
all output Signals. All input/output signals are set to the high-Z state during the
assertion of this signal.
ALE/M/NM
I
ADDRESS LATCH ENABLE/MUL TIPLEXED/NON-MUL TIPLEXED ADDRESS SELECT. When tied high or left floating after reset, the microprocessor interface is configured as non-multiplexed. When driven low, then the
microprocessor interface is configured as multiplexed. In this case this pin
functions as the address latch enable, and the MA(7:0) pins are the
demultiplexed address outputs.
CS
I
CHIP SELECT. Active high Signal, when asserted, the internal registers ofthe
SSI 32C9020 can be accessed.
WR/R/W
I
WRITE STROBE/READIWRITE. In the Intel bus mode, when an active low
signal is present with CS signal high, the data is written to the internal registers.
RD/DS
I
In the Motorola bus mode, this signal acts as the R/W signal.
READ STROBE/DATA STROBE. In the Intel bus mode, when an active low
signal is present with CS signal high, internal register data is read.
In the Motorola mode, this signal acts as the OS signal. OS when active high
is data strobe.
9-53
II
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
MICROPROCESSOR INTERFACE
NAME
DINT
TYPE
(continued)
DESCRIPTION
O,OD,l DISK INTERRUPT. An active low signal indicates the controller is requesting
microprocessor service from the disk side. This signal is programmable for
either a push-pull or open-drain output circuit. This signal powers up in the
high-l state. Register 4F bit 3 enables the pull-up.
SINT
O,OD,l SCSI INTERRUPT. This signal is generated by the SCSI controller and is an
interrupt line to the microprocessor. It is programmable for either a push-pull
or open drain output circuit. This signal powers up in the high-l state. The
interrupt is sourced from the SCSI Interrupt Register. Register 4F bit 3 enables
the pull-up. This signal is also programmable to be either an active high or
low interrupt.
AD(7:0)
I/O
ADDRESSIDATA BUS. When configured in the Intel mode, these lines are
multiplexed, bidirectional microprocessor register address and data lines.
MA(7:0)
1/0
MICROPROCESSOR ADDRESS BUS: These signals are nonmultiplexed
address input or latched address output lines.
READY
0
READY: When this signal is deasserted low, the microprocessor shall insert
wait states to allow time for the chip to respond.
IIMC
I
INTEUMOTOROLA: This signal selects the microprocessor interface to be
used. When this signal is asserted high, it selects the Intel bus control
interface. When this signal is deasserted low, it selects the Motorola bus
control interface. This signal has an internal pull-up to allow the default
selection of the Intel bus control interface.
When configured in the Motorola mode, these lines are bidirectional data lines.
BUFFER MANAGER INTERFACE
BA(15:0)
0
BUFFER MEMORY ADDRESS LINES 0:15. Active high, for direct connection
to a Static or Dynamic RAM address lines 0:15.
BA16/RAS
0
BUFFER MEMORY ADDRESS 16: In SRAM mode, fordirectconnectionto a
Static RAM address line 16.
ROW ADDRESS STROBE: In DRAM mode, for direct connection to a
Dynamic RAM Row Address Strobe signal.
BA17ICAS
0
BUFFER MEMORY ADDRESS 17: In SRAM mode, for direct connection to a
Static RAM address line 17.
ROW ADDRESS STROBE: In DRAM mode, active low, for direct connection
to a Dynamic RAM Column Address Strobe signal.
BD(7:0)
1/0
BUFFER MEMORY DATA BUS. 7 through O. Active high, buffer data bus that
connects directly to the buffer RAM data lines.
9-54
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
BUFFER MANAGER INTERFACE
NAME
TYPE
DESCRIPTION
BOP
I/O
BUFFER MEMORY DATA PARITY. This signal provides odd parity for the
buffer memory data bus during transfers to/from the buffer memory to the
buffer RAM.
MOE
0
MEMORY OUTPUT ENABLE. This signal is asserted low only for buffer
memory read operations.
WE
0
WRITE ENABLE. Active low, write enable for the buffer RAM.
SYSCLK
I
SYSTEM CLOCK. This signal is used to synchronize the buffer RAM access,
including the generation of memory address bits, write enable WE, and
memory output enable MOE.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Maximum limits indicate where permanent device damage occurs. Continuous operation at these limits is not
intended and should be limited to those conditions specified in the DC operating characteristics.
PARAMETER
RATING
Power Supply Voltage, VCC
7V
Ambient Temperature
oto 70°C
Storage Temperature
-65 to 150°C
Power Dissipation
750mW
Input, Output pins
-0.5 to VCC + 0.5V
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
VCC Power Supply Voltage
ICC Supply Current
MIN
4.5
UNITS
V
50
rnA
250
J.IA
-0.5
0.8
V
2
VCC+O.5
V
ICCS Supply Current
VOIH Input High Voltage
MAX
5.5
Ta = 25"C Outputs Unloaded
VIL Input Low Voltage
NOM
VOL Output Low Voltage
All pins except SCSI interface,
IOL=2mA
0.4
VOL Output Low Voltage
SCSI interface pins,
IOL=48 rnA
0.5
V
VOH Output High Voltage
10H = -400 J.IA
2.4
V
It Input Leakage Current
0< VIN < VCC
10
J.IA
CIN Input Capacitance
10
pF
COUT Output Capacitance
10
pF
9-55
-10
I
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
ELECTRICAL SPECIFICATIONS
(continued)
Microprocessor Interface Timing Parameters
PARAMETER
CONDITIONS
Ta
Ale width
Tma
Address valid to MAO:? valid
Tr
RD Width
As
Ah
- - - - -1-------
MIN
NOM
MAX
20
UNITS
ns
30
ns
80
ns
Address valid to ALE J,
5
ns
ALE J, to address invalid
10
ns
ns
Cs
CS Valid to RD J, or DS i
20
Ch
RD i or DS J, to CS J,
0
Tda
RO J, or OS i to read data valid
Tds
DSwidth
80
Tdh
RD i or OS J, to read data invalid
0
Tsrw
R/W valid to DS i
20
Thrw
DS J, to R/W invalid
20
Tdrdy
RD J, to READY J, (Intel) or
OS i to READY J, (Motorola)
Wds
Write data valid to WR i or
DS J, to write data invalid
Wdh
WR i or OS J, to write data invalid
Note:
i indicates rising edge
ns
60
ns
ns
25
ns
ns
ns
30
ns
40
ns
10
ns
5
ns
J, indicates falling edge
Non-Multiplexed Bus Interface Timings
Tmas
MA(?:O) valid to OS J,
Tmah
DS ito MA(?:O) invalid
5
ns
Cs
CS valid to OS J,
20
ns
Ch
OS i to CS J,
Tda
DS i to read data valid
Tds
DSwidth
ns
0
-
60
80
Tdh
OS i to read data invalid
0
Tsrw
R/W valid to OS J,
20
Thrw
OS i to R/W invalid
20
Tdrdy
OS i to READY J, (Motorola)
WOS
Write data valid to WR i or OS
Wdh
WR i or OS
J.. to write data invalid
Note 1: i indicates rising edge
ns
25
J, indicates falling edge
Note 2: Loading capacitor = 30 pF
9-56
ns
ns
ns
30
J..
ns
ns
40
ns
10
ns
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
ALE __________
J)':~~-----T-a----.~~~---------------------------------------------'''As~ : .. Ah.,
( Address )
AD(7:0)
~
'I
CS ----------------~,
,
I ...
.'..
,,
Cs
(,
Tda
...:
Tr
,
----------------~------------~'\
,,~------------~
\L___
READY
-J
,
~
__:
:~Tdrdy
i+- Tma
'(
MA(7:O)
,~--------------------------------------------------
FIGURE 2: Intel Register Multiplexed Read Timing
ALE
__________
J)'~; ---T~a~~.~~;~--------------------------------------------
__
Tdh
, .. As .. : .. Ah .. ,
AD(7:0)
~
,,
'
CS
'I
-----------------7--',
.
Tda
D~ta
(,
..,.,
),
,
.,'\
,,
Ch
I
",',..
, :"'..--------••~,,.....I-------------.........
, ----~~,
I
DS
Cs
:
Tds
___________________~--------~l~--------------,\.,
,
~Tsrw"_
------------~--~I
--,'\
, ,
04-- Thrw
\,---------,1
READY
__:
:~Tdrdy
MA(7:0)
FIGURE 3: Motorola Register Multiplexed Read Timing
9-57
I
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
ALE
J
Ta
\
-----'''''~_--___l~~''---------------------
_________________~-~~-~-~~-~-----------'..~\...._~D~~ta~j)f-----~'.. .1
Wds
._AS_:4Ah_.
AD(7:0)
(
Add'ress
Wdh
)
1
"
cs ________________
1
1
I
\
~,-J,
I~-------------
Tw
Cs
\'------Jl,
Ch
1
~
READY
\'--_~I
1
,
~Tdrdy
~'1
1
1
~: ;"'-Tma
'(
MA(7:0)
,~-------------------------------------------------
FIGURE 4: Intel Register Multiplexed Write Timing
ALE
________~f~.~--T-a__~.~\~-------------------------------------1
1
Wdh
'•Wds.,,1 ....
'
, .. As. :.. Ah .. ,
~
AD(7:0)
Address
~
~
II
cs
~~ ~
____~l
1
~ ...
os ______________
~--
\
1 ~-----------
:
Cs
Tds
I
Ch
I
·1'"
",'" -:
/.--------,\
__------J,
1'---,--------------
1
RIW
.... Tsrw'4-
--------------~----,~L~,,----------~·~f
~
I,
--: : . -Thrw
~'-----'/
READY
: - - Tdrdy
1
~~Tma
MA(7:0)
:{
I,
FIGURE 5: Motorola Register Multiplexed Write Timing
9-58
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
ALE
~'Tmas
Tmah ~
~,---,-I- - - - - - - + - - 1 t'~'.
"---,-I
MA(7:o)
I
~
,
os
---'~"'~---Td·--_~t
~C8
--...,
READ TIMING
~
: Tda
:
I
I
\
f~~'------~',
cs
'
--:::c--
'c:-.
:"-Ch
:d~ I
....J.;_
.. -'Xr-:- - - - - - ' - :----i~
AO(7:o)OUT _ _
,
MV - - , - ' - :------~:\,-_ _
_____:
:....-Tsrw
--.....:
,
I
,
I
,
!
WRITE TIMING
AD(7:o) IN
Wds(
I
-
,
: . . -Thrw
,
I
I
t4--Tsrw
I
.:~ .~
~
I
I-4--Thrw
MV~'-_'_ _ _ _ _ _~'1
FIGURE 6: Non-Multiplexed Bus Timing Diagrams
II
9-59
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
ELECTRICAL SPECIFICATIONS (continued)
Disk Interface Timing
PARAMETER
MIN
CONDITIONS
NOM
MAX
UNITS
ns
T
RRCLK
20.8
T/2
RRCLK highllow time
8.5
Tr, Tf
RRCLK rise and fall time
0
Os
NRZ in valid to RRCLK i
3
ns
Oh
RRCLK i to NRZ in invalid
3
ns
As
AME valid to RRCLK i
3
Ov
RRCLK ito NRZ out
3
Note:
i indicates rising edge
ns
2
ns
15
Loading capacitor = 10 pF
:.......I - - - - T - - - - I....:
~~--~7,~----~~~--~7,~---,
I
I
I
I
:~:
----l
•
Dv :~
_NR_Z_O_AT_A~(W_rit~e)_ _ _ _ _~:_~~~_ _ _ _~~~
FIGURE 7: Disk Write Timing
..
T
:
RRCLK
NRZ (read)
..
'. "
/.'
T/2
...
T/2
~:
:
--:
Tf~:
/.
<:...-... ?
Os
"
'
:~'-----'
As
.
/
FIGURE 8: Disk Read Timing
9-60
ns
:-~:
~Tr
ns
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
BUFFER MEMORY READ/WRITE TIMING PARAMETERS (Figures 9 through 14)
PARAMETER
CONDITIONS
MIN
NOM
MAX
25
UNIT
T
SYSCLK period
ns
T/2
SYSCLK high/low time
Tav
SYSCLK i to address valid
Note 1
Tmsv
SYSCLK i to MS,J..
Notes 1,6
18
ns
Tmsh
SYSCLK
Note 1
18
ns
Tmv
SYSCLK i to MOE,J..
Note 1
18
ns
10
ns
-~
i
i
to Msi
to MOEi
18
ns
Tmh
SYSCLK
Note 1
18
ns
Twv
SYSCLK i to WE,J..
Note 1
18
ns
Twh
SYSCLK i to WEi
Note 1
18
ns
Tdov
SYSCLK i to data out valid
Note 1
18
ns
Tdoh
SYSCLK i to data out invalid
Note 1
18
ns
Tdis
Data in valid to MOE i (SRAM)
5
ns
0
ns
Data in valid to CAS i (DRAM)
Tdih
MOE i to data in valid (SRAM)
CAS i to data in valid (DRAM)
Trv
SYSCLK i to RAS,J..
Note 1
18
ns
Trh
SYSCLK i to RASi
Note 1
18
ns
Trav
SYSCLK i to row address valid
Note 1
18
ns
Trah
SYSCLK i to row address invalid
Note 1
18
ns
- -r - - -
~-
Tcv
SYSCLK i to CAS,J..
Note i
18
ns
Tch
SYSCLK i to CAsi
Note 1
18
ns
Tcav
SYSCLK i to column address valid
Note 1
18
ns
Tcah
SYSCLK i to column address invalic
0
9-61
ns
II
SSI32C9020
SCSI Combo Contr.oller
48 Mbit/s; single bit NRZ interface
ELECTRICAL SPECIFICATIONS (continued)
BUFFER MEMORY READ/WRITE TIMING PARAMETERS (Figures 9 through 14)
(continued)
PARAMETER
CONDITIONS
MIN
UNIT
Trwl
RAStto RASi
Notes 2,3
«RWL + 3) • T)
ns
Trwh
RASito RASt
Notes 2, 4
«RWH + 1) • T)
ns
Tcwl
CASt to CAsi
Note 2
«CWL + 1) • T)
ns
Tcwl
CASito CASt
Notes 2, 5
«CWL + 1) • T)
ns
Note:
Loading capacitance = 30 pF
Note 1:
The measured delay for any olthe signal indicated by this note will not vary from the measured delay
of any other signal indicated by this note by more than ±1 ns.
Note 2:
RWL, RWH, CWL and CWH are fields in the Buffer Manager Timing Control Register (54H). Each
is a two bit field which can contain a value of 0, 1, 2, or 3. These values determine the minimum
number of SYSCLK periods (T) for the associated signal width.
Note 3:
The minimum width value of Trwl will be generated for refresh cycles and for any buffer memory
access cycle except when multiple page mode accesses are performed. When multiple page mode
accesses are performed, the width of the RAS low pulse is extended until the end of the last CAS
low cycle.
Note 4:
The minumum value of Trwh will be generated whenever the Buffer Manager determines that a
buffer request is pending at the ocmpletion of the current memory cycle and a page mode access
can not be used either because page mode operation is not enabled or the needed location is not
within the current page.
Note 5:
The minumum value of Tcwh will be generated only between consecutive page mode accesses.
Note 6:
MS will rise only if the Buffer Manager determines that no additional requests for buffer access are
pending. If the Buffer Manager determines that another access is to be Made, MS is kept low
between the accesses for improved speed.
--
9-62
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
SYSCLK
I
I
___---1-:,:4-TmV
MOE
I
\
~r-'I----
Tmh---...:
I
I,
I
I
I
I
I~-----------~
I
I
1
~"cTmsv
I
~I
~Tmsh
I \L. __________________________~I~;,-----
I
,-
I
--.: 14- Tay
~ ;.-Tav
===J--------------~I~I~
BA(17:0)
I
B0(7:0)
f.-Tdh
-.:
------------------~c=!)~--I
I
~
~Tds
Note: Twba is a functional parameter that gives the duration of one RAM data buffer access cycle in SYSCLK
periods. The value is programmed in bits 1-0 of register 54H. These examples show Twba = 4T.
FIGURE 9: SRAM Read Timing
SYSCLK
II
I
I
I
I
I
I
I
I
:-r
---.----r~~L--------------------~~y:
~
~TWY
Twh---.
I _ Tmsv
_
---.
I
_Tmsh
_, r -
~
, ,L-----------------,J
______;
I
;+-Tav
I
~-----------------,~
IL=
-
BA(17:0)
I
_
B0(7:0)
r4-Tav
I
I
r4-Tdov
--'--;--,~
I
I
_Tdoh
C
: I
---r;-~,~---------------~-FIGURE 10: SRAM Write Timing
9-63
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single, bit NRZ interface
SYSCLK
Tmsv
BA(11:0)
FIGURE 11: DRAM Timing, Refresh Cycle (Shown with WRL
=0)
SYSCLK
8A(11:0)
READ
B0(7:0)
WRITE
BO(7:0)
FIGURE 12: DRAM Timing, Standard Cycle (Shown with RWL = 0 and CWL = 0)
9-64
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
SYSCLK
BA(11:0)
READ
BO(7:0)
WRITE
BO(7:0)
FIGURE 13: DRAM Timing, Fast Page Cycles (Shown with RWL
= 0, RWH = 0, CWL = 0 and CWH = 0)
SYSCLK
----f""b
1=
~.------~--~----~~I
I---l
:
..
Trwl
------------~I
BA(11:0)
Tewl -
Column Address
I I~~I
Tewh
Column Address
Trwh
--I
~
Row Address
FIGURE 14: DRAM Timing (ShOwing the Relationship of RWL, RWH, CWL and CWH to overall timing)
9-65
I
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
ELECTRICAL SPECIFICATIONS (continued)
PARAMETER
MIN
MAX
(Fast) (Fast)
MIN
MAX
(Slow) (Slow)
UNIT
Trl
REO Deassertion Time
Tids
Setup time SCSI Data to REO']' (write to SCSI bus)
Tidh
Hold time REO']' to SCSI Data invalid (write to bus)
37
63
43
43
Tal
Minimum ACK Assertion Width Required
10
ns
Tods
Data Hold from ACK,], (Read from the SCSI bus)
5
ns
Todh
Data Hold from ACK,], (Read from the SCSI bus)
12
ns
Trh
REO Assertion Time
48
ns
52
ns
ns
ns
Note: All timing parameters are measured with 200 pF load, two SCSI terminator loads, ACK filter turned off.
i------'Talrh,----I
\b-------+-------~/
\r---------J
-Tids
I---Tidlh-----<~I
SCSIDala
From Device
SCSIDala
From Initiator
FIGURE 15: SCSI Synchronous Timing
9-66
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
ELECTRICAL SPECIFICATIONS (continued)
PARAMETER
MIN
MAX
UNIT
Tods
Data Setup to ACK'/' (SCSI Output phase)
5
ns
Todh
Data Hold form ACK'/' (SCSI Output phase)
12
ns
49
Talrh
ACK'/'to REOt
Tids
Data Setup to REO'/' (SCSI Input phase)
80
ns
Tidh
Data Hold from ACK'/' (SCSI Input phase)
29
ns
ns
Note: All timing parameters are measured with 200 pF load, two SCSI terminator loads, ACK filter turned off.
Trl
1-----
Trh
---1
---I---Tidh
SCSI Data Bus
Tods
FIGURE 16: SCSI Asynchronous Timing
9-67
II
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
Synchronous Data In/Out Phase
PARAMETER
CONDITIONS
MIN
Txtrp*
Synchronous Transfer Period
(see note)
Tsrl
SYSFREO high to REO low
Tsrh
SYSFREO high to REO high
60
ns
Tdov
SYSFREO high to data
oul valid
40
ns
Tdsu
Data setup to ACK low
55
ns
Tdh
Data hold from ACK low
40
ns
MAX
NOM
UNITS
ns
50
-
Note: Txtrp is the Synchronous Transfer Period as defined by the Synchronous Control Register (Reg: 43H).
SYSFREO is a function of the BUFCLK and is determined by the prescale value as defined by the Clock
Control Register (Reg: 49H) .
,,........II------Txfrp - - - - - - I....,'
,
,
:..-1/2 Txfrp ~,
~ 1/2 Txfrp
,
,,
SYSFREO
,
--..: : . - - Tsrl
I
----...:,
~::.-Tsrh --..: : . - - Tsrl
r
i
,,
I
I
,,
REO - , - - - - - - - - - , \ ' - -_ _~/
,
'
...
Tdov
.
,
,
'
~~~~:7 ~I-
:...
________
Tdov
__'~'-
,
,
'
..'
...
Tdh
Tdsu
ACK - - - - - - - - - - , \ '
_ _ _ _ _ _ __
/
',------,.
FIGURE 17: Even Number of SYSFREQ Cycles/SCSI Transfer Period
9-68
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
,
' ...I------Txfrp - - - - - - - - . . . ',
,....
,
,,
,
,
~1/2Txfrp~
~1/2Txfrp~
,
,,
,
,,
.
,
,
,,
~:, ,:....-- Tsrl
~', ,~Tsrh
~:, ,:....-- Tsrl
,,
,,
,,
>YSFREO
REO - - " - - - - - - - - - ,
,
,
:...
\~
.'
,
:....
,
Tdov
, ,
____~:l~----~~
.'
,
Tdov
'r-----
SOB 0 : 7 '
SOBP
~'--_ _ _ _ _ _---'~'--_ __
.'
,
,
'...
:
Tdsu
:
...
Tdh
ACK - - - - - '- -___\'-------'/
FIGURE 18: Odd Number of SYSFREQ Cycles/SCSI Transfer Period
Wait for Selection
PARAMETER
Tbsd
MIN
CONDITIONS
Bus Settle Delay (400 ns)
to the assertion of BSY
NOM
3T +90
MAX
UNITS
~T +90
ns
Note: T is the SCSI Clock Period (SCP) as defined in Register 49H (CLKCTL).
Selection~',
End
\~______~'____________
BSY ___________~J
,
SEL \
!
,
'
~ Tbsd - . ;
~----------------',
,
SOB (7:0)SI0
j-----
-----------------'0,------,
-LI________
SOB (7:0)010 \ \ . . . . _ _ _ _ _ _ _ _ _ _ _ _ _
ATN
--r----------------------
\'----------------------------------FIGURE 19: Wait for Selection
9-69
I
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
Arbitration
MIN
MAX
UNITS
Tbfsd
Bus Settle Delay (400 ns) +
Bus Free Delay (800 ns) to the
assertion of BSY and SDB olD
6T + 110
7T+110
ns
Tad
Arbitration Delay (2.4 J.lSec)
to the assertion of SEL (win) or
deassertion of BSY and
SDB olD (lost)
-
13T + 100
ns
Tbcsd
Bus Clear Delay (800 ns)+
Bus Settle Delay (400 ns) to
end of Arbitration Phase
-
6T + 100
ns
CONDITIONS
PARAMETER
NOM
Note: T is the SCSI Clock Period (SCP) as defined in Register 61 H (CLKCTL).
BSY
--L.c=
__h_,/_ _ _ _ _-
"~~""""------'~'-_ _ _
I
I
I
I
I
I
I
I
~Tbfsd --"~Tad ~
SEL~~~~:----~~----rrt~-_-_~h_'/_____________
I
I
SOB (7:0)010
---------.\~_ _ _ _
SOB (7:0)010
---------------::-~-T-b-CS-d-----,.\'------
11_________
_ ' _ r_
=._
.L_
_
'
i'---___
End Arbitration~;'-- Begin
I
Reselection
FIGURE 20: Arbitration
9-70
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
Reselection
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
6T + 100
ns
Tbcsd
Bus Clear Delay (800 ns) +
Bus Settle Delay (400 ns) to
end of Arbitration Phase
Tdskd1
Two Deskew Delays (90 ns)
to the deassertion of BSY
-
160
ns
Tbsd
Bus Settle Delay (400 ns) to
the assertion of BSY
-
2T +40
ns
2T + 70
ns
Two Deskew Delays (90 ns)
1T +70
to the deassertion of SEL,
SDB o10 ' and SDB OID
Note: T is the SCSI Clock Period (SCP) as defined in Register 61 H (CLKCTL).
Tdskd2
BSY
Start
1
Reselection ~
__________
j
~----~I
\---_\..!.>-I_ _--'-1
1
1
:
. -Tbcsd
1
1
--":~Tdskd1
1
.. :~
Tbsd-':~Tdskd2~:
1
1
SEL~~______~____________________~;'--
---'r
SDB (7:0)0ID _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
--'r
SDB (7:0) DID - - - - - - - - - - \ ' -_ _ _ _ _ _ _ _ _ _ _ _
1
10
------~\_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
FIGURE 21: Reselection
9-71
I
SSI32C9020
SCSI Combo Controller
48 Mbit/s; single bit NRZ interface
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
~ z
~! ~ ~ ~ ~ ~ ~I~ I~ ~ ~ ~ ~ IQI~18 Iml~ ~ ~ I~I~ ~ I~ ~ I~~ I~ ~
BA7
81
BA8
BAg
82
83
BA10
BAil
84
BA12
BA13
86
o
50
49
48
47
46
85
GND
SDB4
SDB3
SDB2
SDBI
SDBO
87
45
44
GND
BA14
BA15
88
43
GND
89
42
GPI02
VDD
90
41
GPIOI
GND
91
40
GPIOO
BDP
92
39
NRZ
BDO
93
38
RRCLK
BDI
94
37
WG
BD2
36
BD3
35
RG
RST
BD4
34
33
BD5
CDe
BD6
BD7
o
IWIWlfll
10
32
31
WAM/AMD/SEC
INDEX
INPUTIOUTPUT
GND
fll ,,,,
IC!>
z03::<------~~'__
,,--~'~
.. ~~l'----ADDRESS
__D..J.~_T_A_)
CS
I,
__________________
~,_J,
..
,
,
Cs
,
Tds
Ch
.1....
DS _________. -_ _ _~!.
,
,
.,..1
'\
,~-------------------
,
, ,
--...Tsrw~
RNV __________~----_,r_------l),'
'\
,
,~------------------
--...
~Thrw
READY _________- L_ _ _ _ _~
,
,
,
,
\'--_.-J/
~,
:..-- Tdrdy
~ ;'-Tma
MA(7:0) _ _ _ _ _ _
~:«==================
,'
FIGURE 3: Motorola Register Multiplexed Read Timing
9-107
I
SSI32C9023
SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
ALE
/
\L_______________________________
Ta
------' ...,..-------II~~" As
AD(7:0)
Ah
'
Wds
Wdh
..~=~~~'~..~::::!~l'
----------------
I
~
I
~Td s
I
Note: Twba is a functional parameter that gives the duration of one RAM data buffer access cycle in SYSCLK
periods. The value is programmed in bits 1-0 of register 54H. These examples show Twba = 4T.
FIGURE 8: SRAM Read Timing
9-113
II
SSI32C9023
SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
Twba
:~"~----~------------------------------------------------J""':
SYSCLK
,
~'I
:'-Twv
Twh--':
I
I
r4--i-
V
\
I
I
~
r4-Tmsv
~:
\
/:
I
~
~:
:'-Tav
,
I
X
BA(17:0)
I
~I
BD(7:0)
J4-Tmsh
J4-Tav
I
X
I
~:
:---- Tdov
------X
________
J4- Tdoh
C
~----J,~--------------------------------------------------~-----,
FIGURE 9: SRAM Write Timing
9-114
SSI32C9023
SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
SYSCLK
Tmsv
MS
RAS
CAS
MOE
BA(11:0)
Row/Refresh Addr
WE
FIGURE 10: DRAM Timing, Refresh Cycle (Shown with WRL = 0)
I
9-115
SSI32C9023
SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
SYSCLK
BA(11:0)
READ
BO(7:0)
WRITE
BO(7:0)
FIGURE 11: DRAM Timing, Standard Cycle (Shown with RWL
9-116
= 0 and CWL = 0)
SSI32C9023
SCSI Combo Controller
80 Mbitls; dual bit NRZ interface
FIGURE 12: DRAM Timing, Fast Page Cycles (Shown with RWL = 0, RWH
= 0, CWL = 0 and CWH = 0)
SYSCLK
!.
Trwl
----I
.. ~
1=
~I______~----~--~--~I
I-- Tcwl - - Tcwh --l
------------~I
I
Trwh
--I
~
I~~I
BA(11:0)
FIGURE 13: DRAM Timing (Showing the Relationship of RWL, RWH, CWL and CWH to overall timing)
9-117
I
SSI32C9023
SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
SCSI Asynchronous Timing Paraemeters
PARAMETER
CONDITIONS
Tods
SCSI Output Phase
5
SCSI Output Phase
12
Data Setup to ACK.j,
MIN
NOM
MAX
UNITS
ns
Todh
Data Hold from ACK.j,
Talrh
ACK.j,to REoi
Tids
Data Setup to REo.j,
SCSI Input Phase
80
ns
Tidh
Data Hold from ACK.j,
SCSI Input Phase
29
ns
--
ns
49
ns
Note: All timing parameters are measured with 200 pf load, two SCSI terminator loads with ACK Filter turned
off.
Talrh
\
/
\
SCSI Data
From Device
~
-
Tids
I--Tid
Valid
Tods
SCSI Data
From Initiator
.
--
Todh
f--
FIGURE 14: SCSI Asynchronous Timing
9-118
SSI32C9023
SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
SCSI Synchronous Timing Paramenters
PARAMETER
MAX
UNITS
REO Assertion Time
37
48
ns
Trl
REO Deassertion Time
ns
Setup time SCSI Data to REO-!' Write to SCSI bus
Tidh
Hold time REO-!' to
SCSI Data invalid
63
43
43
52
Tids
Tal
Minimum ACK Assertion
Width Required
Tods
Data Setup to ACK-!,
Todh
Data Hold from ACK-!,
Trh
CONDITIONS
Write to bus
MIN
NOM
ns
ns
10
ns
Read from the SCSI bus
5
ns
Read from the SCSI bus
12
ns
Note: All timing parameters are measured with 200 pf load, two SCSI terminator loads, ACK filter turned off.
Trl
~--Trh--~
--j-..Tidh
SCSI Data Bus
II
FIGURE 15: SCSI SynchronOUS Timing
9-119
SSI32C9023
SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
Synchronous Data In/Out Phase
PARAMETER
CONDITIONS
(see note)
Txtrp·
Synchronous Transfer Period
Tsrl
SYSFREO high to REO low
Tsrh
SYSFREO high to REO high
Tdov
SYSFREO high to data
out valid
Tdsu
Data setup to ACK low
Tdh
Data hold from ACK low
MIN
NOM
MAX
UNITS
50
60
40
ns
ns
55
40
ns
ns
ns
ns
Note: Txtrp is the Synchronous Transfer Period as defined by the Synchronous Control Register (Reg: 43H).
SYSFREO is a function of the BUFCLK and is determined by the prescale value as defined by the Clock
Control Register (Reg: 49H).
.
' ...I -_ _ _ _ Txfrp -~--~.~,
,.....
,
,
,
:.--1/2
Txfrp--...,
,
,
,
,
i.-- 1/2 Txfrp ~:,
,
,,
~:
: . - Tsrh
~::.Tsrl
,,
,
SYSFREO
REO
I
I
I
I
I
I
I
I
I
:!r-------L
--r------'-,\
,'"
.' ________ .' ________
.'
'--------i-',
Tdov
- . : : . - Tsrl
I
I
I
,
~g~~:7 ~'-
:....
,
:...
Tdov
-'~',
Tdsu
Tdh
ACK - - - - - - - - , - - - - . \ '
/
',------,.
FIGURE 16: Even Number of SYSFREQ Cycles/SCSI Transfer Period
9-120
SSI32C9023
SCSI Combo Controller
80 Mbit/s; dual bit NRZinterface
'.I-_
....
_ _ _ Txfrp
--------I~~,
1
1....- 1/2 Txfrp-..
1
,
1
,
,
,
1
: . -1/2 Txfrp ~
,
1
3YSFREO
,
~::..Tsrl
1 ,
I
I
I
REO ____________.,' 1
.
:
1
~::..Tsrl
1 ,
~'I ,~Tsrh
'\
I
:lr---------.L
,
,
:...
Tdov
1
1
'--------,J,
~,
Tdov
SOB O:7Ir------------,~
SOBP
~
A.~L,____
Tdsu
ACK
Tdh
-----------,,,'--_-1/
FIGURE 17: Odd Number of SVSFREO Cycles/SCSI Transfer Period
Walt for Selection
PARAMETER
Tbsd
MIN
CONDITIONS
Bus Settle Delay (400 ns)
to the assertion of BSY
NOM
3T +90
MAX
UNITS
4T +90
ns
Note: T is the SCSI Clock Period (SCP) as defined in Register 49H (CLKCTL).
End Selection ~,
BSY _ _ _ _ _ _ _~/.
SEL
~
\~______~'__________
: . -Tbsd
-+-:
1
\,--,-----------------~!
,
V..------
SOB (7:0)SI0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..LL"_ _ _ _ _ __
SOB (7:0)010 ,
ATN
--L..I_______
_______________
---r------------------------
\~----------------FIGURE 18: Wait for Selection
9-121
II
SSI32C9023
SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
Arbitration
PARAMETER
MAX
UNITS
Tbfsd
Bus Settle Delay (400 ns) +
Bus Free Delay (800 ns) to the
assertion of BSY and SDBolD
CONDITIONS
6T + 110
MIN
NOM
7T + 110
ns
Tad
Arbitration Delay (2.4 llSec)
to the assertion of SEL (win) or
deassertion 01 BSY and
SDB 01D (lost)
-
13T + 100
ns
Tbcsd
Bus Clear Delay (800 ns)+
Bus Settle Delay (400 ns) to
end of Arbitration Phase
-
6T + 100
ns
Note: T is the SCSI ClockPeriod (SCP) as defined in Register 61H (CLKCTL).
BSY
~""""~:----.\~ _ _ _...L_c=
__//______
,
i
,
i
,
~Tbfsd ~~
Tad
''
~
'
~~~i_ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _~'_ _ _
SEL
SOB (7:0)010
~"''''~i
~
I,/
\r
II
~'---------
\~
____~r==
__
,
1,/
. _ f_
I
__ _ _ _ _ __
SOB (7:0) DID - - - - - - - - - - - - - - - - : : ...-T-b-C-Sd---,~\'-------
End
FIGURE 19: Arbitration
9-122
1'--__
Arbitration~;'--
Begin
Reselection
SSI32C9023
SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
Reselection
PARAMETER
MIN
CONDITIONS
-
Tbcsd
Bus Clear Delay (800 ns) +
Bus Settle Delay (400 ns) to
end of Arbitration Phase
Tdskd1
Two Deskew Delays (90 ns)
to the deassertion of BSY
-
Tbsd
Bus Settle Delay (400 ns) to
the assertion of BSY
Tdskd2
Two Deskew Delays (90 ns)
to the deassertion of SEL,
SDB o1D ' and SDBD1D
. - - - - -...
.-----
NOM
~~-
f----
MAX
UNITS
6T + 100
ns
- - f----
160
ns
-
2T + 40
ns
1T +70
2T + 70
ns
Note: T IS the SCSI Clock Penod (SCP) as defined In Register 61H (CLKCTL).
Start
'
Reselection ~
\----1-;.>-1
----------~----~I
,
1
I
----7--
1
~ Tbcsd ~:'--Tdskd1 ~~Tbsd ----.-:.-- Tdskd2--..:
I
I
I
SEL\:
I
r
I
~--------~--------------------------------~,
SDB (7:0)010
SDB (7:0) DID
____________________________~r_
\~____________~r_
1
1
\~-----------------------FIGURE 20: Reselection
9-123
II
SSI32C9023
SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
PACKAGE PIN DESIGNATIONS
(Top View)
VDD
BA7
BA8
BA9
BA10
BAll
8A12
BA13
BA14
BA15
VDD
VDD
GND
GND
BDP
BDO
BDl
BD2
BD3
BD4
BD5
BD6
BD7
NIC
NIC
VDD
103
104
105
106
107
108
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
43
42
41
40
39
127.
128
GND
SliB4
ml!l3
GND
"Sr5ll2
Sl5lIT
SOliD
GND
GND
GPI02
GPIOl
GPIOO
NRZl
NRZO
NIC
GND
RRCLK
NIC
WCLK
WG
RG
RST
PJ;1I)/SEC
INDEX
INPUT/OUTPUT
GND
0000
ZZClO
CJ(!J»
128-Lead QFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for
final design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights of
third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the rightto make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX: (714) 573-6914
©1991 Silicon Systems, Inc.
Patent Pending: 91-060
9-124
0194 - rev
SSI32C9024
Differential SCSI Combo Controller
80 Mbit/S)dual bit NRZ interface
RkJiU§mt,"',6Ut."i
December 1993
DESCRIPTION
FEATURES
The SSI 32C9024 is an advanced CMOS VLSI device
which integrates major portions of the hardware needed
to build a SCSI disk drive with differential support. The
circuitry of the SSI 32C9024 includes a complete SCSI
target interface, an advanced buffer manager, a high
performance disk formatter and an 88 bit ReedSolomon ECC with fast "on-the-fly" hardware correction. The SSI32C9024 provides maximum performance
while minimizing micro controller intervention.
•
SCSI Bus Interface
Full SCSI-2 Compatibility
Direct bus interface logic with on-Chip
48 mA drivers for single ended operation
Control signals for operation with external
differential tranceivers
Synchronous transfer rates up to
10 megabytes per second
Asynchronous transfer rates up to
5 megabytes per second
Parity generation and checking
Auto Command Mode (ACM) SCSI state
machine performs high level SCSI
sequences without microprocessor
intervention
Four level ACM command FIFO supports
automatic execution of multiple ACM
commands
Hardware support for automatic handling
of SCSI-2 command queuing
Automatic SCSI COB size determination
Automatic SCSI Disconnect and Reconnect
Sixteen byte data FIFO between SCSI
channel and Buffer Manager
The SSI 32C9024 provides a Dual Bit Interface to the
ENDEC. The Dual Bit Interface allows an effective
transfer rate of upto 80 megabits per second on the disk
interface by utilizing two parallel NRZ data signals and
a clock rate of 40 MHz. The reduction of overall clock
rates between the SSI32C9024 and the ENDEC can be
of great benefit to the designer.
The SSI32C9024 can sustain concurrenttransfers of up
to 80 megabits per second transfer rate to the disk and
10 megabytes per second across the SCSI bus.
(continued)
(continued)
BLOCK DIAGRAM
¢.
'I'··· 'I
GPIOO·' - - - - l
mI(7,0)
mw
hmG
------i
----i
""";=H=O~STEoA~:rA=BU=S=:::::;;'~.U:FFE~-R~i.iANA~-:G£J~~-I_ __ ¢~~
"'0 0-"_--Ii
;
m:
------i
; : Q _ _- - j
=
=
11....
P-
?BOP
m~~!.cE I
0----1
.-----<0[)
~--a BA17~
I
~§~~~~~~5~)
::~'"
SDOE
ARB_BSY
BSYOUT
____
AD (7:0)
MA(7:0)
Q-_ _ _. , - - - - ,
~
Q4----.j
Q..._ - - . j
csQ+-_--I
ALElMm
MICRO-
m!losm Q+-_--I P~iR~:COER
Wf'JPRI
~_--I
1ffiTQ-+-_--j
mTQ+----j
Q+-_--j
READY
1293 - rev.
J
SYSClK
_~ECTOR
AG
SELOUT
TARGET
I~
BA1~
9-125
~~UTIOUTPUT
INPUT
INDEX
FAUlT
RRClK
WCLK
NRZO,l
II
SSI32C9024
Differential SCSI Combo Controller
80 Mbit/s; dual bit NRZ inter·face
DESCRIPTION (continued)
FEATURES (continued)
The SSI32C9024 is one of a family of Silicon Systems'
single chip disk controllers which support a wide range
of device interfaces. The SSI32C9023 is a single ended
only version of the SSI 32C9024. The SSI 32C9022 is
pin compatible with the SSI32C9024 but supports disk
data transfers rate up .to only 48 megabits per second.
Other family members support AT and PCMCIA interfaces. The Silicon Systems' chip family is illustrated in
the hierarchy chart shown in Figure 1. All members are
based on a common architecture allowing major portions of firmware to be reused.
•
The high level of integration within the SSI 32C9024
represents a major reduction in parts count. When the
SSI 32C9024 SCSI Controller is combined with the
SSI32R2110 ReadIWrite device, SSI32P4782 Combination Read Channel, SSI 32D4680 Time Base Generator, SSI32H4631 Servo and Motor Speed Controller,
an appropriate microcontroller and memory, a complete, cost efficient, high performance intelligent drive
solution is created.
•
Buffer Manager
- Direct support of DRAM or SRAM
SRAM throughput t020 megabytes
per second
SRAM size up to 256k bytes
DRAM throughput to 17.78 megabytes
per second
DRAM size up to 1 megabyte
Programmable memory timing
Buffer RAM segmentation with flexible segment sizes from 256 bytes to 1 megabyte
Dedicated host, disk and microprocessor
address pointers
Internal buffer protection circuit provides
buffer integrity
Disk Formatter
Dual Bit NRZ Interface
Effective Data Rates to 80 megabits/s
Automatic mUlti-sector transfer
Header or microprocessor based split data
field support
Advanced sequencer organized in
31 x 5 bytes
88-bit Reed Solomon ECC with "on-the-fly"
fast hardware correction circuitry
Capable of correcting up to four 1O-bit
symbols in error
32 MbiVs NRZ,
AT Controlier,
56-BitECC
32 MbiVs NRZ,
SCSI Controlier,
88·Bit RlS ECC
48 MbiVs NRZ.
AT Controlier,
88·Bit RlS ECC
48 MbiVs NRZ.
SCSI Controlier,
88-Bit RlS ECC
Dual·Bit NRZ
48 MbiVs NRZ.
PCMCIAIATA Controlier,
88·Bit RlS ECC
Dual-bit NRZ
3V!5V
48 MbiVs NRZ,
ATA Controlier,
88·Bit RlS ECC
Dual-bit NRZ
3V!5V
80 MbiVs NRZ,
ATA Controlier,
88-Bit RlS ECC
Dual BitNRZ
48 MbiVs NRZ,
ATA Controlier,
88·Bit RlS ECC
Dual-Bit NRZ
3V!5V
160 MbiVs NRZ,
ATA Controlier,
144-Bit RlS ECC
Dual·/8·bit NRZ
160 MbiVs NRZ,
SCSI-3 Controlier,
144·Bit RlS ECC
Dual·/8·bit NRZ
SCSI Differential
FIGURE 1: Silicon Systems' Single Chip Controller Hierarchy
9-126
SSI32C9024
Differential SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
•
•
Guaranteed to correct one 31-bit burst or
two ii-bit bursts
Hardware on-the-fly correction of an ii-bit
single burst error within a half sector time
Detects up to one 51-bit burst or three ii-bit
bursts
Microprocessor Interface
Supports both multiplexed or
non-multiplexed microprocessors
Separate or combined host and disk interrupts
Programmable wait state insertion
Other Features
Internal power down modes
Available in 128-pin QFP
FUNCTIONAL DESCRIPTION
The SSI 32C9024 contains the following four major
functional blocks:
Microcontroller Interface
SCSI Interface
Disk Formatter
Buffer Manager
The Microprocessor Interface allows the local microprocessor access to all of the SSI32C9024 internal control
registers and any location within the buffer memory. The
microprocessor, by writing and reading the internal
registers can control all activities of the SSI 32C9024.
The microprocessor can elect to perform SCSI and/or
disk operations directly, or it can enable the advanced
features of the SSI 32C9024 which can perform all
typical operations automatically.
The SCSI Interface block handles all SCSI activities. The
SCSI interface includes all of the signals necessary for
implementing a differential SCSI interface using external
differential transceivers. The SSI32C9024 also includes
48 mA drivers allowing for direct connection of the SSI
32C9024 to the SCSI bus. The SCSI interface logic
includes Auto Command Mode (ACM) logic, an advanced state machine capable of handling a variety of
complex SCSI sequences without microprocessor intervention. The microprocessor can queue up to four ACM
commands into the ACM Command FIFO to create even
more sophisticated command sequences. The SCSI
block interfaces directly with the Buffer Manager via an
internal speed matching FIFO. This FIFO, plus the
bandwidth capabilities of the Buffer Manager guarantee
sustained full speed transfers across the SCSI bus. The
9-127
high level of automation of the ACM minimizes SCSI bus
overhead. The net result is maximized performance with
minimum SCSI bus bandwidth utilization.
The Disk Formatter performs the serialization and
dese~ialization of data. If provides all of the necessary
functions to control track formatting, header search, and
the reading and writing of data. The heart of the Disk
Formatter is an advanced programmable sequencer
which is flexible enough to interface to a wide variety of
read/write channels. The sequencer can contain 31
instructions, each of which is 5 bytes (40 bits) in width.
The width of the instructions allows for sophisticated
branching techniques which increase the flexibility and
power of the sequencer. The flexible disk interface can
be configured through a wide range of capabilities. This
allows the SSI 32C9024 to interface with nearly any
readlwrite channel and allows the user of the SSI
32C9024 to select the readlwrite channel best suited to
the device. Of course, by selecting the SSI 32C9024
controller and the 32P4782 Combination Read Channel, you are guaranteed a problem free interface.
Within the Disk Formatter are the ECC generator/
checker and ECC corrector. The generator/checker
provides the ability to generate or check a 32 bit ECC for
headers and an 88 bit Reed Solomon code for data. If
the checker detects an error in an 88 bit Reed Solomon
data field, the syndrome information is transferred into
the corrector. The corrector performs the necessary
operations to determine if the error was correctable and
interfaces directly with the buffer controller to perform
the correction automatically. The corrector performs its
correction within one half of a sector time. This guarantees that the corrector will always be available to correct
the next sector if necessary.
As its name implies, the Buffer Manager manages the
data buffer of the controller. The Buffer Manager can
support either SRAM or DRAM. When configured to
operate with DRAM, the Buffer Manager automatically
performs necessary refresh cycles. The Buffer Manager
creates all of the necessary timing and control signals for
a wide range of memory types and speeds. The Buffer
Manager interfaces with the buffer memory, the SCSI
Interface block, the data path of the Disk Formatter
block, the ECC corrector and the microprocessor. If
more than one of these devices requires access to the
buffer memory, the Buffer Manager arbitrates the requests automatically. The Buffer Manager of the SSI
32C9024 can sustain SCSI operations at the rate of 10
megabytes per second, Disk Formatter operations at 80
megabits per second (10 megabytes per second).
II
SSI32C9024
Differential SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
PIN DESCRIPTION
The following
(I)
(0)
(Z)
(OD)
convention is used in the pin description:
denotes an input
denotes an output
denotes~ a tri-state output
denotes an open drain output
GENERAL
NAME
TYPE
DESCRIPTION
VOD
POWER SUPPLY PIN
GND
GROUND
HOST INTERFACE
SDBP
1/0
SCSI DATA BUS PARITY. Odd parity bit for the SCSI data bus.
SDB(7:0)
1/0
SCSI DATA BUS BITS 7-0.
ATN
I
._,--
ATTENTION. This active low signal is used by the initiatorto request a message
out phase.
BSY
1/0
ACK
I
ACKNOWLEDGE. This active low signal is used in the handshake protocol to
indicate the completion of a data byte transfer.
SRST
I
SCSI RESET. This active low signal is used to reset the SCSI controller.
MSG
0
MESSAGE. This active low signal is used to indicate a message phase.
SEL
1/0
SELECT. This active low signal is used to indicate either a selection or
reselection phase.
CID
0
COMMANDIDATA. This signal is used to indicate either a command or data
phase.
REQ
I
REQUEST .. This active low signal is used in the handshake protocol to initiate
a data byte transfer.
BUSY. This active low signal is used to indicate when the bus is active.
-..
---~,------.----,---
-
-~
I
INPUT/OUTPUT. This signal is used to indicate the direction of data transfer.
1/0
INPUT/OUTPUT. These pins are used to indicate the SCSI 10 of the target
device. The pins can be programmed as outputs for test purposes only.
SDOE
0
SCSI DATA BUS OUTPUT ENABLE.
ARB_BSY
0
Enables BSY output in arbitration phase.
BSYOUT
0
Enables BSY output in phases other than arbitration phase.
SELOUT
0
Enables SEL output.
TARGET
0
Enables Target mode; lJsedto control the SCSI phase signals 10, CD, and MSG.
1/0
GPIO(2:0)
DIFFERENTIAL SCSI
9-128
SSI32C9024
Differential SCSI Combo Controller
80 Mbitls; dual bit NRZ interface
DISK INTERFACE
NAME
TYPE
INDEX
INPUT/
OUTPUT
I
I/O
INPUT
AMD/
SECTOR
I
I/O
RG
WG
RRCLK
0
0
I
WCLK
NRZi
I/O
NRZO
I/O
FAULT
I
0
DESCRIPTION
INDEX. Input for index pulse received from the drive.
DISK SEQUENCER INPUT/OUTPUT. A general purpose control (output) and status
(input) pin configured by the Output Enable Bit of Register 71 H, bit 7.
At power-on, this pin is an input. As an input, it can be used to synchronize the disk
sequencer to an external event. As an output, it is controlled by .bit 2 of the Control Field
of the disk sequencer.
INPUT: This pin can be used to synchronize the disk to an external event.
ADDRESS MARK DETECT/SECTOR. This pin is used in the Hard Sector mode as the
sector input. A pulse on this pin indicates a sector mark is found.
In the Soft Sector mode, a low-level input indicates an address mark was detected. The
device powers up in Soft Sector Default mode.
READ GATE. During disk data read, this pin is asserted. Active high.
WRITE GATE. During disk data write, this pin is asserted. Active high.
READ/REFERENCE CLOCK. This is a clock signal generated from an external data
synchronizer. This clock is used to synchronize the input NRZ data and clock the disk
formatter of the Chip.
WRITE CLOCK. This signal clocks the NRZ data out in the dual NRZ Interface mode.
NON RETURN TO ZERO 1. In dual NRZ mode, this signal is the most significant bit read
data input from the disk drive when the read gate signal is asserted; it is the most significant
bit write data output to the disk drive when the write gate Signal is asserted. In single NRZ
mode, this signal is not used and should be grounded. NRZ1 is the leading bit of the bit pair.
In Write mode, the MSB of the data bytes always appears on NRZ1.
NON RETURN TO ZERO. In dual NRZ mode, this signal is the least significant bit read data
input from the disk drive when the read gate signal is asserted; it is the least significant bit
write dataoutputto the disk drive when thewrite gate signal is asserted. In single NRZ mode,
this signal is used to transfer NRZ data tolfrom the read channel chip.
FAULT: This input when asserted indicates to the chip that a fault has occurred with the disk.
The disk sequencer will stop and both RG and WG pins will be deasserted.
MICROPROCESSOR INTERFACE
RST
I
ALE/MINM
I
CS
I
WRIR/W
I
RESET. Anasserted low input generates acomponent resetthat holds the intemal registers
at reset, stops all operations within the chip, and deasserts all output signals. All inpuVoutput
signals are set to the high-Z state during the assertion of this signal.
ADDRESS LATCH ENABLE/MULTIPLEXED/NON-MULTIPLEXED ADDRESS SELECT.
When tied high or left floating after reset, the microprocessor interface is configured as nonmultiplexed. When driven low, then the microprocessor interface is configured as multiplexed. In this case this pin functions as the address latch enable, and the MA(7:0) pins are
the demultiplexed address outputs.
CHIP SELECT. Active high signal, when asserted, the internal registersofthe SSI32C9022
can be accessed.
WRITE STROBE/READ/WRITE. Inthe Intel bus mode, when an active low signal is present
with CS signal high, the data is written to the internal registers.
In the Motorola bus mode, this signal acts as the RIW signal.
9·129
II
SSI32C9024
Differential SCSI Combo Controller
80 Mbit/s;dual bit NRZ interface
MICROPROCESSOR INTERFACE (continued)
NAME
RD/DS/DS
DINT
TYPE
I
DESCRIPTION
READ STROBE/DATA STROBE. When the Intel bus control interface is selected (the IIMC
is high), this signal acts as the RD signal. When the read strobe signal is asserted low and
the CS signal is asserted high, the data from the specified register will be driven to the AD
signals.
When the Motorola bus control interface is selected (the IIMCis low) this signal acts as the
data strobe signal. A high on the RlW signal along with this signal asserted and the CS signal
asserted high indicates a read operation. A low on the RIW signal along with this signal
asserted and the CS signal asserted high indicates a write operation. Note when nonmultiplexed Motorola bus configuration is chosen, the data strobe is an active low input.
0,00,l DISK INTE RRUPT. An active low signal indicates the controller is requesting microprocessor service from the disk side. This signal is programmable for either a push-pull or opendrain output circuit. This signal powers up in the high-Z state. Register 4F bit 3 enables the
pull-up.
O,OO,Z SCSI INTERRUPT. This signal is generated by the SCSI controller and is an interrupt line
to the microprocessor. It is programmable for either a push-pull or open drain output circuit.
This signal powers up in the high-Z state. The interrupt is sourced from the SCSI Interrupt
Register. Register 4F bit 3 enables the pull-up. This signal is also programmable to be either
an active high or low interrupt.
ADDRESSIDATA BUS. When configured in the Intel mode, these lines are multiplexed,
1/0
bidirectional microprocessor register address and data lines.
When configured in the Motorola mode, these lines are bidirectional data lines.
MICROPROCESSOR ADDRESSBUS: These signals are nonmultiplexed address input or
1/0
latched address output lines.
READY: When this signal is deasserted low, the microprocessor shall insert wait stateS to
0
allow time for the chip to respond.
.._-_._------INTEUMOTOROLA: This signal selects the microprocessorinterfaceto be used. When this
I
signal is asserted high, it selects the Intel bus control interface. When this signal is
deasserted low, it selects the Motorola bus control interface. This signal has an internal pullup to allow the defau~ selection of the Intel bus control interface.
.----,~.--.~------------.--~---------"-~.-------.--".---"-,~,.
SINT
AD(7:0)
MA(7:0)
READY
IIMC
BUFFER MANAGER INTERFACE
BA(15:0)
0
BA16/RAS
0
BA17/CAS
0
BD(7:0)
1/0
BUFFER MEMORY ADDRESS LINES 15 through O. Active high, for direct connection to
a Static or Dynamic RAM address lines.
BUFFER MEMORY ADDRESS 16: In SRAM mode, for direct connection to a Static RAM
address line 16.
ROW ADDRESS STROBE: In DRAM mode, for direct connection to a DynamiC RAM Row
Address Strobe signal.
BUFFER MEMORY ADDRESS 17: In SRAM mode, for direct connection to a Static RAM
address line 17.
ROW ADDRESS STROBE: In DRAM mode, active low, for direct connection to a Dynamic
RAM Column Address Strobe signal.
BUFFER MEMORY DATA BUS. 7 through O. Active high, buffer data bus that connects
directly to the buffer RAM data lines.
9-130
SSI32C9024
Differential SCSI Combo Controller
80 Mbit/s; dual bit NRZ interface
ELECTRICAL SPECIFICATIONS
BUFFER MANAGER INTERFACE (continued)
BOP
I/O
MOE
0
MS
WE
SYSCLK
0
0
I
BU FFER MEII(IORY OATA PAR lTV. This signal provides odd parity for the buffer memory
data bus during transfers to/from the buffer memory to the buffer RAM.
MEMORY OUTPUT ENABLE. In SRAM mode this signal is asserted low when every buffer
memory access is active. In DRAM mode this signal is asserted low only for buffer memory
read operation.
MEMORY SELECT. An active low signal indicates external memory is selected.
WRITE ENABLE. Active low, write enable for the buffer RAM.
SYSTEM CLOCK. This signal is used to synchronize the buffer RAM access, including the
generation of memory address bits, write enable WE, and memory output enable MOE.
ABSOLUTE MAXIMUM RATINGS
Maximum limits indicate where permanent device damage occurs. Continuous operation at these limits is not
intended and should be limited to those conditions specified in the DC operating characteristics.
PARAMETER
RATING
Power Supply VoHage, VCC
7V
Ambient Temperature
oto 70°C
Storage Temperature
-65 to 150°C
Power Dissipation
750mW
Input, Output pins
-0.5 to VCC + 0.5V
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
..
4.50
VCC Power Supply VoHage
ICC Supply Current
Ta = 25'C Outputs Unloaded
V
50
rnA
250
-0.5
0.8
~
V
2.0
ICCS Supply Current
VIL Input Low Voltage
5.50
vcc + 0.5
V
VOL Output Low Voltage
All pins except SCSI interface,
IOL=2 mA
0.4
V
VOL Output Low Voltage
SCSI interface pins,
IOL=48 mA
0.5
V
VOH Output High Voltage
10H
=-400~
2.4
V
IL Input Leakage Current
o----
_~~xr:------'-:~--,~
AD(7:0) OUT _ _---;-:
RJW
---.l :
-..-:
:
~Tsrw
WRITE TIMING
~
I
\'--:....-Thrw
I
I
Wds , . . . ,"
~
AD(7:0) IN
I
~
I
I
1'4--- Tsrw
I
~
.. Wdh
I
F-
~ Thrw
RlW ~,--_'_ _ _ _ _ _ _'~J
FIGURE 6: Non-Multiplexed Bus Timing Diagrams
ELECTRICAL SPECIFICATIONS (continued)
MICROPROCESSOR INTERFACE TIMING PARAMETERS
Disk Read/Write Timing (Figure 7)
PARAMETER
T
CONDITIONS
MIN
3.3V
MAX
3.3V
MIN
5V
MAX
5V
UNIT
RRCLK period (dual bit)
41
41
ns
RRCLK period (single bit)
31
20.8
ns
RRCLK low time (dual bit)
16
16
ns
RRCLK low time (single bit)
12
8.5
ns
Ds
NRZ in valid to RRCLK high
5
3
ns
Dh
RRCLK high to NRZ in invalid
5
3
ns
As
AMD valid to RRCLK high
(soft sector only)
5
3
ns
Dv
RRCLK high to NRZ1, NRZO
out valid
5
Tr, Tt
RRCLK rise and fall time
Note:
Loading capacitance
T/2
27
3
= 10 pF
9-163
3
18
ns
2
ns
II
SSI32C9301
PC-AT Combo Controller
With Reed Solomon, 3V Operation
T
:--
/ :4
RRCLK
NRZ (read)
.:
...
T/2
.;
T/2
~
•
Tf~:
~:
~
------------~<
:.-
~:
: . - - Tr
y.----
>~-----------
~
Os:
,
~ Oh 04--
,,'-----.---'/
~
As
'
FIGURE 7: Disk Read Timing
,
,
I - - - - T - - - - - l....:
....
I' ...
RRCLK
~'----~~~--~~
,
'
,~
:
NRZ DATA (write)
~~---
'------'
~-
Dv
,,
,
I
-...: Ov ~
I
I
------------'~~~----~~i~
I
:.-.;
!
Wv
I
- . ; Wv ~
I
I
-------------~~~---------'~
FIGURE 8: Disk Write Timing
9-164
SSI32C9301
PC-AT Combo Controller
With Reed Solomon, 3V Operation
BUFFER MEMORY READIWRITE TIMING PARAMETERS (Figures 8 through 13)
PARAMETER
CONDITIONS
MIN
3.3V
MAX
3.3V
MIN
5V
MAX
5V
UNIT
T
SYSCLK period
28
25
ns
T/2
SYSCLK high/low time
12
10
ns
Tav
SYSCLK t to address valid
(Note 1)
Tmsv
SYSCLK t to MSt
(Notes 1, 6)
Tmsh
SYSCLK t to MSt
(Note 1)
Tmv
SYSCLK t to MOEt
(Note 1)
Tmh
SYSCLK t to MOEt
(Note 1)
Twv
SYSCLK t to WEt
(Note 1)
35
35
35
35
35
35
35
35
35
18
ns
18
ns
18
ns
18
ns
18
ns
18
ns
18
ns
18
ns
18
ns
Twh
SYSCLK t to. WEt
Tdov
SYSCLK t to data out valid
(Note 1)
Tdoh
SYSCLK t to data out invalid
(Note 1)
Tdis
Data in valid to MOEt (SRAM)
Data in valid to CASt (DRAM)
5
5
ns
Tdih
MOEt to data in valid (SRAM)
CASt to data in valid (DRAM)
0
0
ns
Trv
SYSCLK t to RASt
(Note 1)
Trh
SYSCLK t to RASt
(Note 1)
Trav
SYSCLK t to row address valid
(Note 1)
Trah
SYSCLK t to row address invalid
(Note 1)
Tcv
SYSCLK t to CASt
(Note 1)
Tch
SYSCLK t to CASt
(Note 1)
Tcav
SYSCLK t to column address valia
(Note 1)
Tcah
SYSCLK t to column address invalid
----,~
-"--~,---
.
(Note 1)
35
35
35
35
35
35
35
0
9-165
0
18
ns
18
ns
18
ns
18
ns
18
ns
18
ns
18
ns
ns
II
SSI32C9301
PC-AT Combo Controller
With Reed Solomon, 3V Operation
ELECTRICAL SPECIFICATIONS
(continued)
BUFFER MEMORY READIWRITE FUNCTIONAL PARAMETERS (Figures 9 through 12) (continued)
PARAMETER
CONDITIONS
MIN
UNIT
Trwl
RASito RASt
Notes 2, 3
(RWL + 3)oT
ns
Trwh
RASt to RASi
Notes 2, 4
(RWH + 1)oT
ns
Tcwl
CASita CASt
Note 2
(CWL + 1)oT
ns
Tcwl
CASt to CAsi
Notes 2, S
(CWL + 1)oT
ns
Note:
Loading capacitance = 30 pF
Note 1:
The measureddelay for any of the signal indicated by this note will not vary from the measured delay
of any other signal indicated by this note by more than TBD (3V), ±2 ns (SV).
Note 2:
RWL, RWH, CWL and CWH are fields in the Buffer Manager Timing Control Register (S4H). Each
is a two bit field which can contain a value of 0, 1,2, or 3. These values determine the minimum
number of SYSCLK periods (T) for the associated signal width.
Note 3:
The minimum width value of Trwl will be generated for refresh cycles and for any buffer memory
access cycle except when multiple page mode accesses are performed. When multiple page mode
accesses are performed, the width of the RAS low pulse is extended until the end of the last CAS
low cycle.
Note 4:
The minumum value of Trwh will be generated whenever the Buffer Manager determines that a
buffer request is pending at the completion of the current memory cycle and a page mode access
can not be used either because page mode operation is not enabled or the needed location is not
within the current page.
Note 5:
The minumum value of Tcwh will be generated only between consecutive page mode accesses.
Note 6:
MS will rise only if the Buffer Manager determines that no additional requests for buffer access are
pending. If the Buffer Manager determines that another access is to be made, MS is kept low
between the accesses for improved speed.
9-166
SSI32C9301
PC-AT Combo Controller
With Reed Solomon, 3V Operation
SYSCLK
,
,
I
~I
I
MS
BA(17:0)
:4-
Tmv
Tmh-----.:
~r-'-----
~L-----------------------~,~t
I
~:
---..'
l.4- Tmsv
-----:
~
___T_av__________________________---r""-~'_ f.- Tav
I
.:.-
Tmsh
~~------------------------------4--r~~
===x
';r=
~ ;"-Tdh
BO(7:0)
---------------------------------~~~-----,
,
~,
~Tds
Note: Twba is a functional parameter that gives the duration of one RAM data buffer access cycle in SYSCLK
periods. The value is programmed in bits 1-0 of register 54H. These examples show Twba = 4T.
FIGURE 9: SRAM Read Timing
SYSCLK
--
,
TWh~
!...t--Twv
II
~
-----,----~\~----------------------~~fr,:------,
BA(17:0)
~
~Tmsv
----.:
~Tav
-.....,
,
I
r4-Tav
====x----------------------------------"'--'t=
,
-.........,
8D(7:0)
_Tmsh
,
~I
r4- Tdov
14- Tdoh
----~:~*~------------------------~:.=x==
FIGURE 10: SRAM Write Timing
9-167
SSI32C9301
PC-AT Combo Controller
With Reed Solomon, 3V Operation
SYSCLK
Tm.v
BA(11:0)
FIGURE 11: DRAM Timing, Refresh Cycle (shown with WRL
= 0)
SYSCLK
BA(11:0)
READ
BO(7:0)
WRITE
BO(7:0)
FIGURE 12: DRAM Timing, Standard Cycle (shown with RWL
9-168
=0 and CWL =0)
SSI32C9301
PC-AT Combo Controller
With Reed Solomon, 3V Operation
SYSCLK
BA(11:0)
READ
BD(7:0)
WRITE
BD(7:0)
FIGURE 13: DRAM Timing, Fast Page Cycles (shown with RWL
=0, RWH =0, CWL =0 and CWH =0)
SYSCLK
I..
Trwl
- - - - ..
l~
1=
~I______~---+--~--~I
~ Tewl - Tcwh --l
-----------ll
1
Trwh
--I
~
1,-------,1
BA(11:0)
FIGURE 14: DRAM Timing (showing the relationship of RWL, RWH, CWL and CWH to overall timing)
9-169
SSI32C9301
PC-AT Combo Controller
With Reed Solomon, 3V Operation
ELECTRICAL SPECIFICATIONS (continued)
AT Host Interface Timing Parameters
MIN
3.3V
PARAMETER
MAX
3.3V
MIN
5V
MAX
5V
UNIT
DREQl
DACK ,J, to DREQ ,J,
50
40
ns
RDTA
IOR,J, to HD(15:0) valid
70
50
ns
DMASET
DACK ,J, to lOW ,J, or lOR ,J,
0
0
ns
DMAHlD
lOR i or lOW i to DACK i
0
0
ns
RDHLD
lOR ito HD (15:0) hi-Z
2
WDS
HD(15:0) setup to lOW i
40
25
30
2
25
ns
ns
ns
10
10
RWPUlSE lOR or lOW low pulse width
80
80
ns
RWH
lOR or lOW high pulse width
50
50
ns
CS16l
HCSO ,J" A(2:0) ,J" A9,J, or HCS1 ito IOCS16,J,
30
25
ns
IOCHl
lOR ,J, or lOW ,J, to.IOCHRDY ,J,
35
30
ns
ADRSET
HCSO, A(2:0), A9/HCS1 setup to lOR ,J, or IOW,J,
25
25
ns
ADRHlD
HCSO, A(2:0), A9/HCS1 hold from lOR i or lOW i
10
5
ns
WDHLD
HD(15:0) hold from lOW i
Note: loading capacitance = 30 pF
Functional Specification
PARAMETER
IOCHTW
CONDITIONS
IOCHHDY pulse width
MIN
0
9-170
NOM
MAX
UNIT
5xBCLK
ns
SSI32C9301
PC-AT Combo Controller
With Reed Solomon, 3V Operation
I. . .1 ________________________________
I
/~------~~
OREO
~
/
--J,
~,
: OREOl
I
---------~~~--------------------------------------------~/
:..
I
RWH
I
.:
I
~~------------~~~I'~==========~;r~------------~~,I
I. .
I
.1
RWPUlSE
___________________~----------~I
HO[O:15] (write)
~(
I'"
:
HD[O:15] (read)
------r---~I
ROTA
I
.1
____________________
~-
I. . .1
I
I ROHLD
I
'
~------------------
I
--------------------~)K~----~:----~)K~--------------------
I..
.1"
WOS
WOHlO
.1
FIGURE 15: Host Programmed 1/08-16 Bit Timing
AO:2,A9
----------~Ir---------------------------------------~Ir_--------________
~~
>K~______~
I'
I
__________~ I
I r_---------
________~~~----------~------------------~>K~-------~
I CS16L I
/
~------------'--------------------..,.-+----'
I
RWH
I
I
~~----------~----~~
lMill5W
.1
I..
..I
, . AORSET
I
IOCHL-:
I
~i"
HO[O:15] (read)
RWPULSE
IOCHTW I
>K
I
.1
I~
I
AORHLO
I
I
{
"I
~I
ROTA
HO[O:15] (wrbe)
Ir----------~------~Ir_----------------________________~>KI~========~I~====~>K~-------------14
......
• I 'II
WDS
11'1
WOHLO
FIGURE 16: Host DMA 8-16 Bit Interface Timing (Non-demand mode)
9-171
SSI32C9301
PC-AT Combo Controller
With Reed Solomon, 3V Operation
DREO
___--.J/
), : - - - - - - - - -
,
,~~,
: DREOL :
,
:~
~,
, DMAHLD '"..-_ _ __
~~----~------~,
~:~
... ,--~~~(------. . ' .:
:~
DMASET
HD[O:15] (read)
RW PULSE
------------~---~' ~--+'----~'r----_
_ _ _ _ _ _:__-..J).(:
X ______
'~
,
HD[O:15] (write)
RWH
'
~'
RDATA'
,~
RDHLD
~'
•
,
------~~~~--~)(~--~----~><
,
' '----WDS
WDHLD
,~
...
------------~,
'. .'
FIGURE 17: Host DMA 8/16·8it Interface Timing (Demand Mode)
RESET Assertion Timing Parameters (Figure 18)
PARAMETER
Trpwi
RST pulse width low
CONDITIONS
MIN
NOT Power On Reset
500
NOM
MAX
ns
Power On Reset
7.5
J.1S
SYSCLK
Trpwl
:....
I
~I
,, ,CIl!DCJ en en en
~M3;2i13
N
'"
<0
Ei
0
0
en en
°l~
....
D
Z
Cl
~ ~ ~ ~
0
'"
N
26
..,.
DACK
'"'" '"'" '" '"'"
II
..,.
.... to
0
D D D D D ~OIOCI~IO~ «
« « «"' « «'" «'" ~~~~t'5
D
I;,;
o
I
I
100-Lead TQFP
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for final
design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX: (714) 573-6914
0194 - rev.
9-173
©1991 Silicon Systems, Inc.
Patents Pending (91-060)(91-057)
Notes:
9-174
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3V Operation
'41 Ph' hi mt'l" ,P" til ,.
December 1993
DESCRIPTION
FEATURES
The SSI 32C9302 is an advanced CMOS VLSI device
which integrates major portions of the hardware
needed to build an ATA disk drive. The SSI 32C9302
can operate on 3.3V or 5V allowing use in
3.3V, 5V, or dual voltage disk drives. The 32C9302 has
a dual bit NRZ interface to allow interfacing with
channel ICs supporting this interface. The 32C9302
also supports serial NRZ mode to allow interfacing with
ICs supporting 1his interface. The circuitry of the SSI
32C9302 includes a complete ATA interface, an
advanced buffer manager, a--------1~~'''!:~.~'''~~.~'---------------: )
I
'1
~~-----
----------------~~,
i
Cs
,"
I
--------T--~~~_______~/~~-------
-
Ch
I
\'-------'/
READY
~
~Tdrdy
I
~ ;"-Tma
'(
MA(7:0)
,~----------------------------------------------------
FIGURE 4: Intel Register Multiplexed Write Timing
ALE
Wds
'.,. .,.'
I
cs
----------------~~
I
I
1
I
__
Cs
Wdh
.,.'
:
(
AD(7:0)
..
)
I
\\-.- - - - -
I
Tds
I
I
Ch
~!. ----~~~:4------------~.~:~--~.:
'\
I
,~------------~,
I
I
________________, -____~....::., Tsrw __
\~~
',--'---------------
____________:~t
____: : . - Thrw
READY
I
I
I
~,
\'------'/
l.4- Tdrdy
I
~: ;'-Tma
MA(7:0)
:{-----------------------------------FIGURE 5: Motorola Register Multiplexed Write Timing
9-186
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3V Operation
ALE
~:Tmas
Tmah~
',~
=::JGc-,-'------------'----1~
MA(7:O)
cs
---1 '
_____ I
, "':;--,::--_
~CS
~
:~Ch
t~·____T_d_S~~~====:~
,
,
TIS
-
READ TIMING
I
Tda
I
1dh
~
----i--.......,xr--------i----i.>---,
, ,
,
, \~--
AD(7:0) OUT
,I4-Tsrw
~:
WRITE TIMING
:4-Thrw
WdS~ .. '. ,.~
AD(7:0) IN
--...: :4-
R/W
TSM
~ Thrw
___:
~'-_' _ _ _ _ _ _ _ _ _ _,...Jl
FIGURE 6: Non-Multiplexed Bus Timing Diagrams
II~ Trrch
...:
I
I
~Trr~
RRCLK~
i
~
~
_I
-~
I-i
~Dis I
I_I
I
I
~Trrcl
~Oih
I
NRZ1, NRZO J(--'----'¥\iALIOIOATA~""""'.·i-I- - - - - Read
''If'.
I
,"-"'t'---'----~'-
I
As
~
AIiilO--'---l1
11_,
~
WCLK
I
I
I
I
-I~I
:
I Twckl
~I-I--OVW--'I
I
~
I
-+i
I
I_Twckh
Trwh I
1-
I
I
I
'
~~'
Xl---___---'X'--______
NRZ1, N~~t~--;':---1-\:
-: : :_OV
FIGURE 7: Disk Interface Timing
9-187
II
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3V Operation
ELECTRICAL SPECIFICATIONS (continued)
MICROPROCESSOR INTERFACE TIMING PARAMETERS
Disk Read/Write Timing (Figure 7)
CONDITIONS
PARAMETER
MIN
3.3V
MAX
3.3V
MIN
5V
MAX
5V
UNIT
41
41
ns
RRCLK period (single bit)
31
20.8
ns
RRCLK low time (dual bit)
16
16
ns
Trrc
RRCLK period (dual bit)
Trrc
Trrcl
-
Trrcl
RRCLK low time (single bit)
12
12
ns
Trrch
RRCLK high time (dual bit)
16
16
ns
Trrch
RRCLK high time (single bit)
12
12
ns
Dis
NRZ in valid to RRCLK high
5
3
ns
Dih
RRCLK high to NRZ in invalid
5
3
ns
As
AMD valid to RRCLK high
(soft sector only)
5
3
ns
Dv
RRCLK high to NRZi , NRZO
out valid
Dvw
WCLK low to NRZ1, NRZO
out valid
Trwl
RRCLK high to WCLK low
Trwh
RRCLK low to WCLK high
27
-3
+3
-3
27
27
12
Twckh WCLK high time (dual bit)
18
ns
+3
ns
18
ns
18
ns
12
ns
Twckh WCLK high time (single bit)
9
9
ns
Twckl
WCLK low time (dual bit)
12
12
ns
Twckl
WCLK low time (single bit)
9
9
ns
Note:
Loading capacitance = 10 pF
.._.-
9-188
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3V Operation
BUFFER MEMORY READIWRITE TIMING PARAMETERS (Figures 8 through 13)
PARAMETER
CONDITIONS
MIN
3.3V
MAX
3.3V
MIN
5V
MAX
5V
UNIT
T
SYSCLK period
35
25
ns
Tt2
SYSCLK hightlow time
12
10
ns
Tav
SYSCLK t to address valid
(Note 1)
30
18
ns
Tmsv
SYSCLK t to MSt
(Notes 1,6)
30
18
ns
Tmsh
SYSCLK t to MSt
(Note 1)
30
18
ns
Tmv
SYSCLK t to MOEt
(Note 1)
30
18
ns
Tmh
SYSCLK t to MOEt
(Note 1)
30
18
ns
Twv
SYSCLK t to WEt
(Note 1)
30
18
ns
Twh
SYSCLK t to WEt
(Note 1)
30
18
ns
Tdov
SYSCLK to data out valid
(Note 1)
30
18
ns
Tdoh
SYSCLK to data out invalid
(Note 1)
30
18
ns
Tdis
Data in valid to MOEt (SRAM)
Data in valid to CASt (DRAM)
5
5
ns
Tdih
MOEi to data in valid (SRAM)
CASi to data in valid (DRAM)
0
0
ns
Trv
SYSCLK t to RASt
(Note 1)
30
18
ns
Trh
SYSCLK i to RASt
(Note 1)
30
18
ns
Trav
SYSCLK to row address valid
(Note 1)
30
18
ns
Trah
SYSCLK i to row address invalid
(Note 1)
30
18
ns
Tcv
SYSCLK t to CASt
(Note 1)
30
18
ns
Tch
SYSCLK t to CASt
(Note 1)
30
18
ns
Tcav
SYSCLK i to column address va lie
(Note 1)
30
18
ns
Tcah
SYSCLK t to column address invalid
0
9-189
0
ns
II
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3V Operation
ELECTRICAL SPECIFICATIONS (continued)
BUFFER MEMORY REAOIWRITE FUNCTIONAL PARAMETERS (Figures 8 through 13) (continued)
PARAMETER
CONDITIONS
TYPICAL
UNIT
Trwl
RASJ, to RASi
Notes 2, 3
(RWL + 3)oT
ns
Trwh
RASi to RASJ,
Notes 2,4
(RWH + 1)'T
ns
Tcwl
CASJ, to CAsi
Note 2
(CWL + 1)oT
ns
Tcwh
CAsi to CASJ,
Notes 2, 5
(CWL +1)oT
ns
Notes:
Loading capacitance = 30 pF
Note 1:
The measured delay for any of the signal indicated by this note will not vary from the measured delay
of any other signal indicated by this note by more than ±2 ns.
Note 2:
RWL, RWH, CWL and CWH are fields in the Buffer ManagerTiming Control Register (54H). Each
is a two bit field which can contain a value of 0, 1, 2, or 3. These values determine the minimum
number of SYSCLK periods (T) for the associated signal width.
Note 3:
The minimum width value of Trwl will be generated for refresh cycles and for any buffer memory
access cycle except when multiple page mode accesses are performed. When multiple page mode
accesses are performed, the width of the RAS low pulse is extended until the end of the last CAS
low cycle.
Note 4:
The minumum value of Trwh will be generated whenever the Buffer Manager determines that a
buffer request is pending at the completion of the current memory cycle and a page mode access
can not be used because the needed location is not within the current page, or a new memory
request is being processed.
Note 5:
The minumum value of Tcwh will be generated only between consecutive page mode accesses.
Note 6:
MS will rise only if the Buffer Manager determines that no additional requests for buffer access are
pending. If the Buffer Manager determines that another access is to be made, MS is kept low
between the accesses for improved speed.
9-190
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3V Operation
SYSCLK
,
,
_ _--<-_-_-'-'~:~ Tmv
,
}~
Tmh~:
~.---'_ _ __
______________________~'-J{ ,
,
~
~Tmsy
---'----..:',
,
I
,-----
--------------------------~_T'~~
-',
~Tav
Tav
~-----------------------~~i~
-'-+<,
----..;
BO(7:0)
':'-Tmsh
\L.
,
BA(17:0)
~:
;...-
:'-Tdih
----------------------------------~~~----,
,
----'1
:~ Tdis
Note: Twba is a functional parameter that gives the duration of one RAM data buffer access cycle in SYSCLK
periods. The value is programmed in bits 1-0 of register 54H. These examples show Twba = 4T.
FIGURE 8: SRAM Read Timing
SYSCLK
,
I
---....:
~Twv
Twh~
I~
---~---.--~~----------------------~_4fr7:-------,
~
_ _ _ Tmsh
r4-Tmsv
,
,
~,'
y----
, \L.---------------------------------r'~p
,
I
BA(17:0)
80(7:0)
-
___
r4- Tav
,
,
r4- Tdov
_Tdoh
~-J~L--------------------~~
FIGURE 9: SRAM Write Timing
9-191
II
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3V Operation
SYSCLK
Tmsv
BA(11:0)
FIGURE 10: DRAM Timing, Refresh Cycle (Shown with WRl
= 0)
SYSCLK
Tmsv
--
~
HTmsh
Trv
-j
I
Tcv
r-
Trh
H
Tch
r-
Tmv I-Tray
BA(11:0)
=
::J
="""""
Tcav~
Trah~
Row Address
-*-
I
;--" .jTmh
I
Tcah
I- ~
Column Address
READ
Tdis
BO(7:0)
WRITE
Twv
-j
I
Tdov
BO(7:0)
Tdih
" Read Data
--------1
Twh
H
Tdoh
i----l
----------------~(~____
w_rit_eD_a_ta___)~-------
FIGURE 11: DRAM Timing, Standard Cycle (Shown with RWl = 0 and CWl
9-192
= 0)
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3V Operation
SYSCLK
BA(11:0)
READ
BO(7:0)
WRITE
BO(7:0)
FIGURE 12: DRAM Timing, Fast Page Cycles (Shown with RWL
=0, RWH =0, CWL =0 and CWH =0)
SYSCLK
..
b
Trwl - - - - I .
r:
~.----~--~--~~I
I---1
:
------------~I
I
Tcwl - -
Tcwh
Trwh
--I
~
~I~I
BA(11:0)
FIGURE 13: DRAM Timing (Showing the Relationship of RWL, RWH, CWL and CWH to overall timing)
9-193
II
SSI32C9302
PC..AT Combo Controller
With Reed Solomon, 3.3V Operation
ELECTRICAL SPECIFICATIONS (continued)
AT HOST INTERFACE TIMING PARAMETERS (Figures 14 through 16)
PARAMETER
CONDITIONS
MIN
3.3V
MAX
3.3V
MIN
5V
MAX
5V
UNIT
40
ns
DREOl
DACK J, to DREO J,
50
DREOD
lOR J, or lOW J, to DREO J,
50
40
ns
RDTA
lOR J, to HD(15:0) valid
70
50
ns
DMASET
DACK J, to lOW J, or lOR J,
0
ns
0
DMAHlD
lOR i or lOW i to DACK i
0
RDHlD
lOR ito HD (15:0) hi-Z
2
0
WDS
HD(15:0) setup to lOW i
30
30
ns
WDHlD
HD(15:0) hold from lOW i
10
10
ns
20
2
ns
20
ns
RWPUlSE lOR or lOW low pulse width
80
80
ns
RWH
lOR or lOW high pulse width
50
50
ns
CS16l
HCSO J,. A(2:0) J, or
HCS1 ito IOCS16 J,
30
20
ns
IOCHl
lOR or lOW J, to IOCHRDY J,
35
25
ns
ADRSET
HCSO. A(2:0). HCS1
setup to lOR J, or lOW J,
ADRHlD
HCSO. A(2:0). HCS1 hold
from lOR i or lOW i
5
Note: loading capacitance = 30 pF
FUNCTIONAL SPECIFICATION
IOCHTW
IOCHRDY pulse width
9-194
25
ns
5
ns
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3V Operation
.,
,--------..'
DREO
~
,,'"
~~----------------~/
, DREOl
~~--------------------~/
,
RWH
,
~::,~==========~;(~--------------..~,
lORilOW
'...
,
.'
RW PULSE
,
, ,..------r----.. ' , - - - - - - - - - - )K,
>K~__________
• ' '---~,' ...._===i.;.i,
RDHlD '
,
'
,
-----------t-----~
:
,'"
HD[O:15] (read)
RDTA
.'
---------------------------..)K~------~:---------..)K~--------------
.,...
HD[O:15] (write)
'...
WDS
WDHLD
FIGURE 14: Host DMA 8-16 Bit Interface Timing (Non-demand mode)
--------..,r_-------------------~
AO:2
________~~
>K~
________
________~~,---------------------~'r_---->K~_________
~
/
, CS16L , ~------------------+~
RWH
!.
..
..!
ADRSET
~
'
IOCHL _ _:
HD[O:15] (read)
HD[O:15] (write)
FIGURE 15: Host Programmed 1/08-16 Bit Timing
9-195
I
.. ,'
~I.~------~
ADRHLD
i
.. '
I
II
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3V Operation
DREQ
------/
.'
,.,.
.:.
,
.,
'S,:'--______
,
: DREQD
:.,.
.'.
~
,
,~_ _ __
DMAHLD
~~--------~------------'~----~/~~---~-----
:.
DMASET
RW PULSE
~
.:
RWH
'
,
vr--------~~+-----
,'~------/'
~
,
,
-----------J--------)','/----r:----..
'. .' ,. .'
HD[O:15] (read)
.
,
HD[O:15] (write)
v/ " - - - - -
~:
RDATA'
RDHLD
,
'
.'. .'
-------------~l(~-~-~X
----------------------------'
,
,.,.
'
WDS
'-----
WDHLD
FIGURE 16: Host DMA 8/16-Bit Interface Timing (Demand Mode)
ELECTRICAL SPECIFICATIONS (continued)
POWER SUPPLY
PARAMETER
CONDITION
MIN
Trpwi
NOT Power On
Reset
500
ns
Power On Reset
7.5
jlS
RST pulse width low
NOM
MAX
SYSCLK
:...
Trpwl
,
;4-----------.....c..-'----------~
.. ,
----------~ ,
'\
I
/
~----------~l.~------
/'
FIGURE 17: RESET AssertionTiming
9-196
UNIT
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3V Operation
PACKAGE PIN DESIGNATION
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
omco ...... wlO
(!}COCOCOCOCOCDCllCOCO
120-Lead TQFP
9-197
SYSCLK
MOEiMS
WE
II
SSI32C9302
PC-AT Combo Controller
With Reed Solomon, 3.3VOperation
PACKAGE PIN DESIGNATION
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
GND
BA6
BAr
BAS
BAg
BAl0
BAll
VOO
GND
BA12
BA13
BA14
BA1S
BAl61rornBA171~m
VOO
GNO
BOP
BOO
BOl
BD2
BD3
BD4
B05
B06
B07
103
104
64
63
62
61
60
59
58
57
66
55
54
53
52
51
50
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
49
48
47
46
45
44
43
42
41
40
39
127.
126
GNO
HOBll
HOB4
HOB10
HOB5
HVOO
GNO
HOB9
HOB6
HOBB
HOB7
mm:r
GNO
VOO
FAULT
INPUT
INDEX
lWlrlSECTOR
RRCLK
GNO
NAZl
NRZO
WCLK
OUTPUT
WG
RG
128-Lead QFP. TQFP
Advance Information: Indicates a product still in the design cycle, and any specifications are based on design goals only. Do not use for final
design.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights ortrademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX: (714) 573-6914
Patents Pending 93-119, Patent Allowed 91-057
9-198
©1991 Silicon Systems, Inc
1293 - rev.
SSI32C9340
PCMCIA Combo Controller with
Reed Solomon, 48 Mbit/s
i 'j'~[§g~N§"[¥jj[.';i
January 1994
DESCRIPTION
FEATURES
The SSI 32C9340 is a CMOS VLSI device which
integrates major portions of the hardware needed to
build a PCMCIA and/or ATA drive hard disk controller.
The SSI 32C9340's place in the Silicon Systems' chip
family is illustrated in the hierarchy chart in Figure 1. It
provides most of the functional circuitry necessary to
build a PCMCIA intelligent disk.
HOST INTERFACE:
The SSI 32C9340 is capable of supporting
interleaved host and disk transfers while maintaining a
disk data transfer rate of up to 48 Mbitls.
The SSI 32C9340 includes a multi-port Buffer
Manager, a storage controller and a high performance
PCMCIA host interface block that incorporates
extensive hardware support - including direct
connection to a PCMCIA or ATA bus.
The SSI 32C9340 performs all the controller functions
for the peripheral device including: Serialization and
deserialization of data; and, ECC generation,
checking and on-the-fly data correction.
•
PCMCIA/ATA and ATA compatible host
interface
•
Hardware and software compatible with
PCMCIA bus standard, reviSion 2.0
•
Programmable 256-byte PCMCIA CIS integrated
•
High Current drivers for direct connection to
the PCMCIA or AT bus
•
Both memory and I/O interfaces supported for
PCMCIA
•
Includes IBM AT compatible Task File registers
and PCMCIA configuration registers
•
Hardware added to provide Multi-Sector data
transfers without microprocessor intervention
•
Automatic BUSY, INTRQ
•
16 byte FIFO to improve throughput
•
PC transfers to 4(6.7@5V)megawords/second
(continued)
BLOCK DIAGRAM
~llJISJ:'
STSCHGJ1'llIAll"
HOriSErnA
flWE'
.----l---1l
JmlillACR:
lOR'.lOW
HDB (15:0)
BA151liilS2
+--+-~-o BA131llOl'
'--+--LJ
'--+--11
LJ""--'-"
~
BA121llAS
O
1_-4_~~~H~O~ST~B~US~~
_ _ _ _'-~~~__~__~__
_
WP/1O"CS16
BA11I1lIiIDE"
oo~
WAlT/=m:lV
rn=KtllllEO"
Rll!1JSV/IRQ
+----+---lJ
HCE2
BA (10:0), BA14. BA16
IJS"
A (8:0). A10
HRESET/RllESET
SYSCLK (40 MHZ)
~
FlCET/~
MA(7:0)
6------+------1------4
AD (7:0)
[1------+
ALE/MImI
11---4
cs [ } - - - - ;
WRiR!W [ } - - - - ;
RD/Oll [ } - - - - ;
WCLK
,,.----,.--u
RRCLK
A!;!l5tSECTOR
INDEX
I~~~~CE
,.----,.--u
NRZO
"'-'--0
NRZ1
RG
li!!C" LJ-----i
WG
1/0
READY/AII'IT LJ-----i
RSTU---4
L __---.!::===l..-.___-'=D=/S=K=FO=R=MA=TT=E=R===========':==:':r'
OUTPUT
INPUT
INPUT2
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
0194 - rev.
II
SSI32C9340
PCMCIA Combo Controller with
Reed Solomon, 48 Mbit/s
FEATURES (continued)
•
Automatic command decoding of write. write long.
write DMA. write multiple. write buffer and format
commands
•
•
8-byte stack lor header information storage
•
Sector header or microprocessor-based split data
field processing logic supporting embedded servo
and zone-bit recording
Supports variable data field length
•
Automatic update of the host task file registers in
both LBA mode and Cyl/HdiSec mode
•
Support for ATA master/slave operation
•
•
Power-down 10 pins
•
BUFFER MANAGER:
•
16-byte disk data FIFO
Disk transfer rate up to 48 Mbitls NRZ
Power Down Mode
MICROPROCESSOR INTERFACE:
Supports Buffer RAM throughput up to:
5V: 20 MByte/sec for S RAM and 17.78 MByte/
sec for DRAM (with 40MHz SYSCLK)
3.3V: 16 MByte/sec for SRAM and 14 MByte/
sec for DRAM (with 30 MHz SYSCLK)
•
•
High speed intemal register access
•
Supports both
microprocessers
Programmable wait state insertion
Intel and Motorola type
•
Programmable microprocesssor scratch pad area
•
ERROR CORRECTION LOGIC:
Auto data streaming capability
•
•
Supports Multiple sector host data transfer
•
Supports up to 1M byte DRAM and up to 128K
SRAM
Enhanced 16-bit CRC polynomial with one orderof
magnitude better burst error detection than
CCITT-CRC16
•
•
Supports variable DRAM and SRAM timings and
sizes
Non-interleaved 88-bit Reed Solomon Code of
degree 8 operation on 10-bit symbols
•
•
Automatic on-the-fly in-buffer error correction
•
Calculation of buffer offsets and masks for on-thefly ECC within one half of a sector time.
•
On the fly in-buffer correction accomplished in no
more than 3 buffer reads and writes through an
independent channel
•
Capable of correcting by software four 10-bit
symbols in error
•
Guaranteed to correct by software one 31-bit burst
or two 11-bit bursts
Advanced sequencer organized in 31 x 5 bytes
•
Detects up to one 51-bit burst or three 11-bit bursts
Advanced branch and interrupt logic
OTHERS:
Defect management support
•
•
•
Automatic power supply level detection circuit
•
Avaiable in 120-pin surface mount TQFP
•
Reloadtransfercounterand hostaddress pointers
•
•
•
•
Supports page mode DRAM access
•
Provides protection logic for buffer data allowing
simultaneous host and disk accesses to the same
buffer segment.
Programmable DRAM page mode burst length
Programmable DRAM refresh period
Separate host. disk. and microprocessor buffer
RAM address pOinters
DISK FORMATTER:
•
•
•
•
•
•
Supports multiple-sector data transfers
NRZ byte synchronization time out timer
Three-index counter providing limit of search and
retry
Selectable on-the-fly error correction span of
11 bits signal burst
JEDEC conform ant 3.3V specification
TTL-Level compatible input receivers at 3.3Vor 5V
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals.
subject to change and are nol guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-200
SSI32C9340
PCMCIA Combo Controller with
Reed Solomon, 48 Mbit/s
FUNCTIONAL DESCRIPTION
The SSI32C9340 is capable of operating in either a 3.3
volt or 5 volt environment.
The SSI 32C9340 contains the following four major
functional blocks:
Microprocessor Interface
PCMCINATA Interface
Disk Formatter
Buffer Manager
The Microprocessor Interface allows the local
microprocessor access to all of the SSI 32C9340
internal control registers and any location within the
buffer memory. The microprocessor, by writing and
reading the internal registers, can control all activities
of the SSI 32C9340. The microprocessor can elect to
perform host and/or disk operations directly, or it can
enable the advanced features of the SSI 32C9340
which can perform these operations automatically.
The PCMCINATA Interface block can interface with
the PCMCIA interface as a PCMCINATA device or
with a PC AT bus. The SSI 32C9340 has on-board
sensing logic to help determine whether it is operating
in either the PCMCIA or ATA mode. The interface
includes 12 mA (8 mA @3.3V) drivers allowing for
direct connection of the SSI 32C9340 to either the
PCMCIA or PC AT bus. The interface is highly
automated, capable of performing multiple block
transfers without micro- controller involvement. The
PCMCINATA block interfaces directly with the Buffer
Manager via an internal speed matching FIFO. This
FI FO, the bandwidth capabilities of the Buffer Manager,
plus the advanced features of the PCMCINATA
Interface guarantee sustained full speed transfers.
The Disk Formatter performs the serialization and
deserialization of data. It provides all of the necessary
functions to control track formatting, header search,
and the reading and writing of data. The heart of the
Disk Formatter is an advanced programmable
sequencer. The sequencer can contain31 instructions,
each of which is 5 bytes (40 bits) in width. The width of
the instructions allows for sophisticated branching
techniques which increase the flexibility and power of
the sequencer. The disk interface can be configured
through a wide range of capabilities. This allows the
SSI 32C9340 to interface with nearly any readlwrite
channel. This allows the user of the SSI 32C9340 to
select the read/write channel best suited to the device.
Of cou rse, by selecting the SSI32C9340 controller and
the SSI 32P4330 Read Channel with 1,7 ENDEC, you
are guaranteed a problem free interface.
Within the Disk Formatter are the ECC generator/
checker and ECC corrector. The generator/checker
provides the ability to generate or check a 32 bit ECC
for headers and an 88 bit Reed Solomon code for data.
I! the checker detects an error in an 88 bit Reed
Solomon data field, the syndrome information is
transferred into the corrector. The corrector then
performs the necessary operations to determine if the
error was correctable and, if it was correctable, the
corrector interfaces directly with the buffer controller
and performs the correction automatically. The corrector
performs its correction within one half of a sector. This
guarantees that the corrector will always be available
to correct the next sector if necessary.
The Buffer Manager manages the data buffer of the
controller. The Buffer Manager can support either
SRAM or DRAM. When configured to operate with
DRAM, the Buffer Manager automatically performs
necessary refresh cycles. The buffer manager creates
all olthe necessary timing and control signals for a wide
range of memory types and speeds. Besides interfacing
with the buffer memory, the Buffer Manager interfaces
with the ATA Interface block, the Disk Formatter block,
the ECC corrector and the microprocessor. If more
than one of these devices requires access to the buffer
memory, the Buffer Manager arbitrates the requests
automatically. The Buffer Manager olthe SSI32C9340
can sustain ATA operations at the rate of 4 (6.7@ 5V)
megawords per second, Disk Formatter operations at
48 megabits per second and still have sufficient
bandwidth left to handle on-the-fly ECC corrections
and microprocessor accesses without degrading
performance on any of the interfaces.
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-201
II
SSI32C9340
PCMCIA Combo Controller with
Reed Solomon, 48 Mbit/s
32 MbiVsNRZ,
AT Controller,
56-B~ ECC
32 Mbitls NRZ,
SCSI Controller,
88-Bit RIS ECC
48 MbiVs NRZ,
AT Controller,
88-Bit RIS ECC
48 Mbitls NRZ,
SCSI Controller,
88-Bit RlS ECC
Dual-Bit NRZ
48 MbiVs NRZ,
SCSI Controller,
BB-Bit RIS ECC
48 MbiVs NRZ,
PCMCIAIATA Controller,
BB-Bit RlS ECC
Dual-b~ NRZ
48 Mbit/s NRZ,
ATA Controller,
88-Bit RlS ECC
Dual-b~ NRZ
48 Mbitls NRZ,
ATA Controller,
88-Bit RIS ECC
Dual-Bit NRZ
3V/5V
3V/5V
3V/5V
80
NRZ,
SCSI Controller,
88-Bit RlS ECC
Dual-Bit NRZ
SCSI Differential
80 Mbitls NRZ,
ATA Controller,
88-Bit RIS ECC
Dual B~ NRZ
160 Mbit/s NRZ,
ATA Controller,
144-Bit RIS ECC
Dual-/8-b~ NRZ
160 Mbitls NRZ,
SCSI-3 Controller,
144-Bit RIS ECC
Dual-/8-b~ NRZ
SCSI Differential
FIGURE 1: Silicon Systems's Disk Controller Chip Hierarchy
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-202
SSI32C9340
PCMCIA Combo Controller with
Reed Solomon, 48 Mbit/s
PIN DESCRIPTION
I = input, 0 = output; Z = tri-state output, 00
inactive state to VCC or GND, respectively.
= open drain output. All unused inputs must be tied to the
BUFFER MANAGER INTERFACE
NAME
TYPE
BA16
I/O
DESCRIPTION
BUFFER ADDRESS 16. In SRAM mode, this pin may be configured as buffer
address 16.
BA15/MS2
0
BUFFER ADDRESS 15/MEMORY SELECT. In SRAM mode, this pin may be
configured as buffer address 15 or memory select 2 for 2nd bank of memory.
After RST is asserted, this signal will be high.
BA14
I/O
BUFFER MEMORY ADDRESS 14. This signal is used for addressing the buffer
memory in SRAM mode.
BA13/BDP
I/O
BUFFER MEMORY ADDRESS 13/BUFFER MEMORY PARITY. This signal
is used for addressing the buffer memory in SRAM mode, or as the buffer data
parity value in DRAM mode.
BA12/RAS
0
BUFFER MEMORY ADDRESS 12!ROW ADDRESS STROBE: This signal is
used for addressing the buffer memory in SRAM mode or as the row address
strobe in DRAM mode. After RST is asserted, this signal will be high.
BA11/DMOE
0
BUFFER MEMORY ADDRESS 11/DRAM MEMORY OUTPUT ENABLE.
This signal is used for addressing the buffer memory in SRAM mode, or as the
memory output enable pin in DRAM mode. After RST is asserted, this signal
will be high.
BA(10:0)
0
BUFFER MEMORY ADDRESS LINES. These are signals 10-0 for addressing
the buffer memory.
BD(7:0)
I/O
BUFFER MEMORY DATA BUS. These eight signals are bits 7-0 of the 8-bit
parallel data lines to/from the buffer memory. Note that BD6 is used to select
between the Intel- and Motorola-style microprocessor interfaces. If BD6 is
externally pulled up when RST is asserted, Intel mode is used; if BD6 is
externally pulled down when RST is asserted, Motorola mode is used.
CAS/SMOE
0
COLUMN ADDRESS STROBE/SRAM MEMORY OUTPUT ENABLE. This
signal is used as the column address strobe in DRAM mode, or the memory
output enable in SRAM mode. After RST is asserted, this signal will be high.
MS
0
MEMORY SELECT. An active low signal indicates external memory is
selected (chip enabled) or 1st bank of memory is selected.
SYSCLK
I
SYSTEM CLOCK. This signal is used to synchronize the buffer RAM access,
including the generation of memory address lines, write enable WE, and
memory output enable MOE. In power down mode, this signal is shut off from
the internal logic and hence buffer memory access is inhibited.
WE
0
WRITE ENABLE. This active low output signal is used to strobe the data into
the RAMs from the DAta bus. For both buffer memory applications, this line is
tied directly to the SRAM or DRAM control pin.
--
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-203
II
SSI32C9340
PCMCIA Combo Controller with
Reed Solomon, 48 Mbit/s
PIN DESCRIPTION
(continued)
MICROPROCESSOR INTERFACE
NAME
TYPE
DESCRIPTION
RST
I
RESET. An asserted active low input generates a component reset that holds
the internal registers of the SSI 32C9001 at reset, stops all operations within
the chip, and deasserts all output signals. All inpuVoutput signals and Host
outputs are set to the high-Z state.
ALE/M/NM
I
ADDRESS LATCH ENABLE/MUL TIPLEXED/NON-MUL TIPLEXED ADDRESS SELECT. When tied high, the microprocessor interface is configured
as non-multiplexed. When driven low, the microprocessor interface is configured as multiplexed. In this case this pin functions as the address latch enable,
and the MA(?:O) pins are the demultiplexed address outputs.
CS
I
CHIP SELECT. This signal must be asserted high for all microprocessor
accesses to the registers of this chip.
WR/R/W
I
WRITE STROBE/READ/WRITE. In the Multiplexed address/data bus mode,
when an active low signal is present with CS Signal asserted high, the data on
the ADO:? is written to the internal registers.
In the Non-Multiplexed address/data bus mode, this signal acts as the RIW
signal. A high on this input along with the RD/DS signal asserted and the CS
signal asserted high indicates a read operation. A low on this input along with
the RD/DS signal asserted and the CS signal asserted high indicates a write
operation. See table below.
CS
WR!R/W
Rri/DS
Mux/Non-Mux
Action
High
Low
High
Intel Multiplexed
Write to internal registers.
High
High
Low
Intel Multiplexed
Read from internal registers.
High
Low
High
Motorola Multiplexed
Write to internal registers.
High
Low
Low
Non-Multiplexed
Write to internal registers.
High
High
High
Motorola Multiplexed
Read from internal registers.
High
High
Low
Non-Multiplexed
Read from internal registers.
Low
X
X
MorN
No action.
Note: X denotes don't care.
RD/DS
I
READ STROBE/DATA STROBE. In the Multiplexed address data bus mode,
when an active low signal is present with CS signal high, internal registers will
be accessed.
In the Non-Multiplexed address data mode, this signal acts as the OS signal.
A high on R/W, with the CS and OS signals asserted, indicates a read
operation. A low on the R/W signal, with the OS and the CS symbols asserted,
indicates a write operation to the internal registers. Note: OS is active high in
multiplexed mode, active low in non-multiplexed.
The target speCification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-204
SSI32C9340
PCMCIA Combo Controller with
Reed Solomon, 48 Mbit/s
NAME
TYPE
DESCRIPTION
DINT/INT
0,00
INTERRUPT. This signal is an interrupt line to the microprocesor. It is the
combined interrupt line of the disk side and host side interrupts when pin
READY/AINT is programmed as ready; otherwise, it only signals the occurrence of disk side interrupt events. This signal is programmable for either a
push-pull or open-drain output circuit. This signal powers up as an open drain
output. May be programmed as active high or low; reset state is active low.
I/O
ADDRESS/DATA BUS. When configured in the Multiplexed address data
mode, these lines are multiplexed, bidirectional data path to the microprocessor. During the beginning of the memory cycle the bus captures the low order
byte of the microprocessor address. These lines provide communication with
the controller device's internal registers and the buffer memory.
AD(7:0)
When configured in the Non-Multiplexed Microprocessors mode, these lines
are bidirectional data lines only.
MA(7:0)
READY/AINT
I/O
MICROPROCESSOR ADDRESS BUS. This a-bit output bus is the AD(7:0)
bus latched by the ALE pin during the address phase of a Multiplexed address
data type microprocessor cycle. These signals are the address input when
used with a non-multiplexed bus microprocessor.
0,00
READY/HOST SIDE INTERRUPT. When programmed as the Ready function, this signal is deasserted low for the microprocessor to insert wait states
to allow time for the chip to respond to the access. When programmed as the
host side interrupt, this pin interrupts the microprocessor when there is a host
related interrupt event. The interrupt signal is programmable for either a pushpull oropen-drain output circuit. This signal powers up as the 'Ready' function.
DISK FORMATTER INTERFACE
INDEX
I
INDEX. This pin serves as the index function for the disk sequencer.
INPUT
i
INPUT. This signal is used to synchronize the disk sequencer to an external event.
INPUT2 (FAULT)
I
INPUT2. This pin is an input to the sequencer for tracking operations or can be
used as a fault function to stop the sequencer.
OUTPUT
0
DISK SEQUENCER OUTPUT. This pin is controlled by bit 2 of the Control
Field of the disk sequencer.
AMD/SECTOR
I/O
ADDRESS MARK DETECT/SECTOR. In Hard Sector mode, this is the input
for the sector pulse from the disk drive. In Soft Sector mode, a low-level input
during a read indicates an address mark was detected.
RG
0
READ GATE. This active high output enables the reading of the disk. It is
asserted by the sequencer Control Field bits 5 and 6. It is automatically
deasserted at the end of the CRC or ECC.
WG
0
WRITE GATE. This active high output enables writing onto the disk. It is
asserted and deasserted by the sequencer Control Field bits 5 and 6.
I
READ/REFERENCE CLOCK. This pin is used in conjunction with the NRZ pin
to clock data in and out of the SSI32C9001 device. This input must be glitchfree to ensure correct operation of the chip.
RRCLK
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-205
II
SSI32C9340
PCMCIA Combo Controller with
Reed Solomon, 48 Mbit/s
PIN DESCRIPTION
(continued)
DISK FORMAITER INTERFACE (continued)
DESCRIPTION
NAME
TYPE
WCLK
0
WRITE CLOCK. This signal clocks the NRZ data out
NRZO
I/O
NRZ BIT O. This signal is the read data input from the disk drive when the read
gate signal is asserted; it is the write data output to the disk drive when the srite
gate signal is asserted. This pin is used for the least significant bit in dual bit
NRZ mode; it is used for the serial data stream in single bit NRZ mode.
NRZ1
I/O
NRZ BIT1. This signal is the read data input from the disk drive when the read
gate signal is asserted; it is the write data outputto the disk drive when the write
gate signal is asserted. This pin is used for the most significant bit in dual bit
NRZ mode; it is not used in single bit NRZ mode.
HOST INTERFACE PINS
WPIIOCS16
O,OD
WRITE PROTECT OR 16-BIT DATA SELECT. This signal can be used for
write protect or 16-bit transfer for PCMCIA common memory mode. In ATA
mode it indicates a 16-bit transfer is active on the host bus/.
R/BUSY/IRQ
O,Z
READY/BUSY/HOST INTERRUPT REQUEST. In PCMCIA mode, this pin is
the Ready/BUSY signal when configured with a memory interface. In ATA
mode, or in PCMCIA mode when configured with an I/O interface, this pin is
the host interrupt request, and is asserted to indicate to the host that the
controller needs attention. As an interrupt request, this pin is active high in ATA
mode, but active low in PCMCIA mode. This pin is always driven in PCMCIA
mode, but will be tri-stated when the drive is not selected or interrupts are not
enabled in ATA mode. This pin is driven low while RST is asserted, and
remains so until the interface mode (PCMCIA or ATA) is determined. If
PCMCIA mode is selected after reset, the chip is configured with a memory
interface, and this pin will reflect the status of the BUSY bit in the Drive Status
Register.
A(8:0), A10
I
HOST ADDRESS LINES. The host address lines A(8:0) and A 10 are used to
access the various PC/AT control, status, and data registers.
A9/HCS1
I
A9/HCS1. This is a multiplexed input pin. When in PCMCIA mode, or when
register 4CH, bit 3 is reset, this is host address line A9. When register 4CH,
bit 3 is set in ATA mode, this is Host chip select 1 (active low).
HCE1/HCSO
I
HOST CHIP SELECT O/CARD ENABLE 1. This signal when low, selects
access to the control, status, and data registers. It is configured as HCSO in
ATA mode, and as HCE1 (card enable 1) in PCMCIA mode.
O,Z
WAIT/I/O CHANNEL READY. This signal is asserted low to extend host
transfer cycles when the controller is not ready to respond. This pin is always
driven in PCMCIA mode, but will be tri-stated when a read or write is not in
progress in ATA mode. This pin is tri-state while RST is asserted, and remains
so until the interface mode (PCMCIA or ATA) is determined.
WAIT/IOCHRDY
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-206
SSI32C9340
PCMCIA Combo Controller with
Reed Solomon, 48 Mbit/s
NAME
INPACK/DREQ
TYPE
DESCRIPTION
O,Z
INPUT ACKNOWLEDGE/DMA REQUEST. In PCMCIA mode, this pin is configured as INPACK, and is asserted when a valid address and chip select are
present. In AT A mode, this pin is configured as the DMA request signal, and is
used during DMA transfer between the host and the controller. In ATA mode, this
pin is tri-statedwhen DMA transfers are notenabled. This pin is tri-statewhile RST
is asserted, and remains so until the interface mode (PCMCIA or ATA) is
determined.
REG/DACK
I
REGISTER SELECT AND I/O ENABLE/DMA ACKNOWLEDGE. In PCMCIA
mode, this pin is configured as REG, and selects the attribute memory space
or 1/0 space when asserted. In ATA mode, this pin is configured as DACK, and
is used as the DMA acknowledge signal during DMA data transfers.
lOR
I
I/O READ. Asserted by the host during a host I/O read operation. When
asserted with a valid address and chip selects, status or data is enabled onto
the host data bus.
lOW
I
110 WRITE. Asserted by the host during a host I/O write operation. When
-
asserted with a valid address and chip selects, data from the host data bus is
strobed into the controller.
HRESET/HRESET
I
HOST RESET. This signal, when active, initializes the control/status registers
and stops any command in process. It is active low in ATA mode, but active
high in PCMCIA mode.
I/O
HOST DATA BUS. This bus is used to transfer data and status between the
host and the controller. These pins are not driven while RST is asserted, and
remain so until the interface mode (PCMCIA or ATA) is determined.
HCE2
I
CARD ENABLE 2. This signal, when low, selects access to the control, status,
and data registers and may enable use of the upper half of the data bus. It is
used only in PCMCIA mode.
HOE/SELATA
I
OUTPUT ENABLE/SELECT ATA MODE. To determine which host interface
to use, this pin is sampled starting at least 81lS after RST is deasserted, and
continuing until at least 251!S after RST is deasserted. If this pin is high at any
time during this sampling period, the interface will immediately be configured
for PCMCIA mode, and the sampling will end. If the pin remains low throughout
the sampling period, the interface will be configured for ATA mode. Once in
PCMCIA mode, this pin is configured as output enable (HOE), and is asserted
by the host during a common memory or attribute memory read. When
asserted with a valid address and chip select, data is enabled onto the host
data bus. In ATA mode, this signal is ignored.
HDB(15:0)
The target specification is intended as an initial disclosure of specification goals lor the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-207
II
SSI32C9340
PCMCIA Combo Controller with
Reed Solomon, 48 Mbit/s
PIN DESCRIPTION
(continued)
HOST INTERFACE PINS (continued)
NAME
TYPE
DESCRIPTION
I
WRITE ENABLE. In PCMCIA mode, this signal is asserted by the host during
a common memory or attribute memory write. When asserted with a valid
address and chip select, data from the host data bus is strobed into the
controller. In ATA mode, this signal is ignored.
STSCHG/PDIAG
1,0
STATUS CHANGED/PASSED DIAGNOSTICS. In PCMCIA mode, this pin is
used as the Status Changed output. InATA mode, this pin is used as the
Passed Diagnostics signal and may be an input or an open-drain output. This
pin is tri-state while RST is asserted, and remains so until the interface mode
(PCMCIA or ATA) is determined.
SPKR/DASP
I/OD
SPEAKER/DRIVE ACTIVE-SLAVE PRESENT. In PCMCIA mode, this pin is
used as the Speaker pin, and is a push-pull output. In ATA mode, this pin is
used as the Drive Active/Slave Present signal, and is an input or an open-drain
output. InATA mode, this pin is used for Master/Slave drive communications
and/or lor driving an LED. This pin is tri-state while RST is asserted, and
remains so until the interface mode (PCMCIA or ATA) is determined.
HWE
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-208
SSI32C9340
PCMCIA Combo Controller with
Reed Solomon, 48 Mbit/s
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(Top View)
~~m~~~.MN-omm~8~gMN~8gm~~~~MN-
BAD
BA1
1.~~~~~~~~~~~~~-~-~~~-
mm
m
mmmOO
2
W
88
87
86
85
BA2
BA3
BM
BA5
4
5
GNO
A9iHCST
lOW
1M
mIDSIDTi\
A10
mn
84
FlCn/m:so
HOB15
HOB7
GNO
BAB
11
83
82
81
80
BA10
BAllilmM'
12
7S
HOB14
13
78
HOB6
BA1~
BA13II!DP
14
15
77
76
HOB13
HOB5
BAS
BA7
9
BAS
10
HVOO
BA14
16
75
HDB12
BA1~
17
BA16
18
19
20
74
73
72
71
GNO
HOB4
HOB11
21
70
JIlVlll"/SECTOR
22
23
69
NRZ1
B02
B03
VOO
GNO
BOO
B01
HOB3
68
NRZO
24
67
WCLK
BD4
25
66
GND
B05
26
D
65
RRCLK
84
26
26
~
OUTPUT
INDEX
~
~
B06
B07
cASiSl\lOE'
IilS"
~
INPUT2
INPUT
~~~~~~~~~~~~~t~~~ttg~~~~~~~~W~
120-Lead TQFP
Target Specification: The target specification is intended as an initial disclosure of specification goals for the product. The specifications
are based on design goals, subject to change and are not guaranteed.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights ortrademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verily that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX: (714) 573-6914
0194 - rev.
9-209
©1992 Silicon Systems, Inc.
Patent Pending (91-060)(91-057)
II
Notes:
SSI32C9600
ATA-2 Storage Controller
160 Mbit/s, a-Bit NRZ Interface
•Fi'~ tde rII;" tMiit.,"
January 1994
DESCRIPTION
FEATURES
The SSI32C9600 is an advanced CMOS VLSI device
which integrates major portions of the hardware
needed to build an ATA disk drive. The SSI32C9600
has an eight bit wide NRZ channel interface with disk
transfers rates up to 160 Megabits per second, an
advanced ATA interface which supports host transfer
rates up to 20 megabytes per second, and a sixteen bit
wide data buffer interface capable of supporting
concurrent full speed transfers on both disk and host
interfaces. The circuitry of the SSI32C9600 includes:
a complete, highly automated ATA interface; an
advanced, fully integrated Buffer Manager; a high
performance Disk Formatter; and two fast ReedSolomon ECC's, one forthe header field and a second
for the data field, both with on-the-f1y hardware
correction. The SSI32C9600 maximizes performance
while minimizing microcontroller intervention.
•
ATA Interface
Single chip PC AT controller (IDE)
Full ANSI ATA-1 and ATA-2 compliance
Direct PC bus connection with on-board 12
mA drivers
PC transfers to 10 megawords (20
megabytes) per second
Supports PIO, DMA and Multiword DMA
(EISA Class B Demand DMA)
Logic for daisy chaining 2 drives
Operates as Master, Slave or both
Automatic command decoding of Write,
Write Long, Write Multiple, Write DMA,
Write Buffer and Format commands.
(continued)
(continued)
BLOCK DIAGRAM
flFFRR:EcEQ;UuE;EN~CY0-0I-------0 SYSXI
IL:S~Y""".'.'H~E~S'Z~E~RJ--...,....~""9
r - BUFFER lNAGER -I
::-~~ - HoST iNTERFACE - ~
1
HOB (15:o)[>-T
A(2,0)[r+
~:
[J-i
IOROY
=:::J
r-:J
I
HOST DATA BUS
I
TASK FILE
---+L
IH •
r;~
lAO
1
1
HOST
1
CONTROl
1
1
1
-.J
AD (H')
I"
:
I
SEQ~~CER
I
311NSTRUCTlONS
1
:~~:
1
BS
1
CS
l}------+I PR't:ti'sOR - :
READY':: r
BUFFER
I
ARBITRATOR
:~:=SBD
BA14/BDP1
BA131BDPO
1
I
M
~
~
:
~/~
CONTROL
DINPUT1/SBD
f4-+-r----------[]
DINPUT2IFAUlT
~~:~
1
L
-
-rn---------
I DISK FIFO
DATA
Alilll'SECTOR
1
I
RRCLK
WClK
~-1:=32=B=YT=E~~ L_MU~X-.-r"r-III~I"Y NRZ (7:0)
I ....
g f-o
BA121"RAll
BA("'l)
M
DRAM/SRAM
~41~'-~======~===:8:=
WG
il
-+.
1
~
1 II
DISKFoRMATrER-
........
1
INTERFACE _
I
1
: .
1
c'::i.-+---,--,
= ru--+----+I
WRlRiW
tmTllNT
1
I
1
=ro[)+,
AL~:
:
DATA
I
--Lf.+!
MULTIPLEXER If-II----.,~ BO(15,0)
j.lP DATA BUS
HOST FIFO
32 BYTE
SYSXO
~
HEADER
FILE
-
1
' ,
+
SPliT FIELD
S~;;~~c"T
I CH~EN
J. I:
I
I ECC . I :
ICORRECTOR I 1
ttl
-~
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
0194
9-211
I
SSI32C9600
ATA-2 Storage Controller
160 Mbit/s, a-Bit NRZ Interface
DESCRIPTION (continued)
FEATURES (continued)
Hardware support for Read Multiple and Write
Multiple commands
The SSI 32C9600 also supports dual bit NHZ interfaces.
In dual bit mode, transfer rates up to 100 megabits per
second on the disk interface are supported.
Hardware support for Cyl/Hd/Sec and LBA
addressing modes, including automatic
updates of the host task file registers in both
modes
The highly automated· Header ECC logic performs
corrections on the header within one or two byte times,
and Data ECC is capable of performing corrections in
real time, allowing the SSI 32C9600 to read every
sector on the disk in a single revolution even if every
sector contained a correctable error.
The SSI 32C9600 is the latest in a line of sophisticated
disk storage controllers. Other Silicon Systems' disk
storage controllers include: the SSI 32C9800 SCSI-3
controller, with host transfer rates up to 20 megabytes
per second and disk data rates of up to 160 megabits
per second. The SSI 32C9001, SSI 32C9301,
SSI 32C9302 and SSI 32C9003 ATA controllers
provide dual and serial NRZ data rates to 80 Megabits
per second and ATA speeds to 13.3 megabytes per
second. The SSI 32C9020, SSI 32C9022,
SSI 32C9023 and SSI 32C9024 family members are
SCSI disk controllers supporting fast, 8-bit wide SCSI
interface, with disk data rates to 80 Megabits per
second. The SSI 32C9340 disk controller completes
the family providing PCMCIA/ATA compliant
interfaces. All members are based on a common
architecture allowing major portions of firmware to be
reused. The Silicon Systems' chip family is illustrated
in the hierarchy chart shown in Figure 1.
The high level of integration within the SSI 32C9600
represents a major reduction in parts count. When the
SSI 32C9600 ATA Controller is combined with the
SSI32R1510BRorSSI32R2110R Read/Writedevice,
the SSI32P4782 Read Channel (1 ,7) or SSI32P4901
PRML Read Channel (8/9), the 32H4631 Servo and
Motor Speed Controller, an appropriate microcontrolier
and memory, a complete, cost efficient, high
performance intelligent drive solution is created.
Automatic Multi-Sector data transfers without
microprocessor intervention
Automatic Host Interrupt and Busy lor multiple
sector transfers
32 byte FIFO to improve performance
Extensive Power Down modes
•
Buffer Manager
Direct support of DRAM or SRAM
SRAM: up to 256k bytes of memory with
throughput to 40 megabytes per second
DRAM: up to 8 megabyte of memory with
throughput to 36 megabytes per second
Buffer CRC and/or buffer parity for increased
data integrity
Programmable memory timing
Flexible buffer RAM segmentation
Dedicated host, disk and microprocessor
address pointers
Buffer streaming with internal buffer protection
circuit providing buffer integrity
•
Disk Formatter
8-Bit NRZ interface supporting data rates to
160 megabits per second, or
2-Bit NRZ interface supporting data rates to
100 megabits per second
Automatic multi-sector transfers
Error tolerant sync detection
Header based split data field support
Advanced sequencer organized in 31 x 4 bytes
Timeouts for sync detection, sector or index
pulse detection, and retry limiting
144-bit Reed Solomon ECC for the data field,
with "on-the-fly" fast hardware correction
circuitry
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-212
SSI32C9600
ATA-2 Storage Controller
160 Mbit/s, a-Bit NRZ Interface
Capable of correcting up to six 8-bit
symbols in error
Guaranteed to correct a single 41-bit error
burst, or two 17-bit error bursts
FUNCTIONAL DESCRIPTION
The SSI 32C9600 contains the following four major
functional blocks:
Microprocessor Interface
ATA Interface
Disk Formatter
Buffer Manager
Fast hardware on-the-fly correction
assures continuous data transfers even if
consecutive sectors are in error
40-bit Reed Solomon ECC forthe headerfield,
with "on-the-fly" hardware correction circuitry
which completes within 1 or 2 byte times
Guaranteed to correct a single 9-bit error
burst
•
Microprocessor Interface
Supports both multiplexed or non-multiplexed
microprocessors
Separate host and disk interrupts
1024 byte buffer window with wait stated or
polled access
•
Other Features
Frequency synthesizers for buffer clock
Internal Power Down mode
Available in 128-pin OFP or TOFP
The microprocessor interface allows the local
microprocessor access to all of the SSI 32C9600
internal control registers and any location within the
buffer memory. The microprocessor, by writing and
reading the internal registers, can control all activities
of the SSI 32C9600. The microprocessor can elect to
perform host and/or disk operations directly, or it can
enable the advanced features of the SSI 32C9600
which can perform these operations automatically.
The ATA Interface block handles all PC AT bus activities.
The AT A interface includes 12 mA drivers allowing for
direct connection of the SSI32C9600 to the PC AT bus.
The ATA interface block is highly automated, capable
of performing multiple block transfers without microcontroller involvement. The ATA block interfaces directly
with the Buffer Manager via an internal speed matching
(continued)
32 MbiVs NRZ.
AT Controlier.
56·Bit ECC
32 MbiVs NRZ,
SCSI Controller,
66·Bit RlS ECC
46 MbiVs NRZ,
AT Controller,
66·Bit RlS ECC
46 MbiVs NRZ,
SCSI Controlier,
88·Bit RlS ECC
Dual·Bit NRZ
46 MbiVs NRZ,
PCMCIAIATA Controlier,
86·Bit RlS ECC
Dual·bit NRZ
3V/5V
46 MbiVs NRZ,
ATA Controller,
66·Bit RlS ECC
Dual·bit NRZ
3V/5V
48 MbiVs NRZ,
ATA Controller,
68·Bit RlS ECC
Dual·Bit NRZ
3V/5V
80 MbiVs NRZ,
AT A Controller.
86·Bit RlS ECC
Dual Bit NRZ
160 MbiVs NRZ,
ATA Controlier,
144-Bit RlS ECC
Dual·/8·bit NRZ
160 MbiVs NRZ,
SCSI·3 Controlier,
144·Bit RlS ECC
Dual·/S·bit NRZ
SCSI Differential
FIGURE 1: Silicon Systems' Disk Controller Chip Hierarchy
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-213
I
SSI32C9600
ATA.. 2 Storage Controller
160 Mbitls, a-Bit NRZ Interface
FUNCTIONAL DESCRIPTION (continued)
FIFO. This FIFO, the bandwidth capabilities of the
Buffer Manager, plus the advanced features of the ATA
Interface guarantee sustained full speed transfers
across the PC AT bus.
The disk formatter performs the serialization and
deserialization of data. It provides all of the necessary
functions to control track formatting, header search,
and the reading and writing of data. The heart of the
disk formatter is an advanced programmable
sequencer. The sequencer can contain 31 instructions,
each of which is 4 bytes (32 bits) in width. The width of
the instructions allows for sophisticated branching
techniques which increase the flexibility and power of
the sequencer. The flexible disk interface can be
configured through a wide range of capabilities.
This allows the SSI 32C9600 to interface with many
different read/write channels and allows the user of the
SSI32C9600 to selectthe read/write channel best suited
to the device. Of course, by selecting the SSI 32C9600
controller and the SSI 32P4901 PRML read channel
(8/9), you are guaranteed a problem free interface.
Within the disk formatter are the ECC generator/checker
and ECC corrector. The generator/checker provides
the ability to generate or check a 40-bit Reed-Solomon
ECC for headers and a 144-bit Reed-Solomon code for
data. The header ECC circuitry performs correction of
the header bytes within one ortwo byte times, minimizing
delays. The data ECC correction circuitry performs
data corrections rapidly. The data ECC circuitry
guarantees that the correction logic will always be
available to correct the next sector if necessary.
The disk formatter provides additional reliability by use
of error tolerant sync detection. This feature allows the
creation of a multi-byte sync field and the detection of
data synchronization even in the event of errors within
the sync field.
The buffer manager manages the data buffer of the
controller. The buffer manager can support either SRAM
or DRAM. When configured to operate with DRAM, the
buffer manager automatically performs necessary
refresh cycles. The buffer manager creates all of the
necessary timing and control signals for a wide range
of memory types and speeds. Besides interfacing with
the buffer memory, the buffer manager interfaces with
the ATA Interface block, the disk formatter block, the
ECC corrector and the microprocessor. If more than
one of these blocks requires access to the buffer
memory, the buffer manager arbitrates the requests
automatically. The buffer manager of the SSI32C9600
can sustain AT A operations at the rate of 10 megawords
(20 megabytes) per second, disk formatter operations
at 160 megabits per second and still has sufficient
band-width left to handle on-the-fly ECC corrections
and microprocessor accesses without degrading
performance on any of the interfaces.
Besides the ability to generate and check data parity,
the ATA interface also includes a CRC generation and
checking capability. During writes, a CRC can be
generated on data received from the host and checked
when the data is transferred to the Disk Formatter. The
CRC is part of the data ECC and is always written by the
Disk Formatter. If the ATA interface generates the
CRC, then the Disk formatter writes the CRC field that
was generated by the ATA interface to the media, or the
Disk Formatter generates the CRC itself. During reads
the CRC is read from the media by the Disk Formatter.
If buffer CRC is enabled, the Disk Formatter writes the
CRC to the buffer and the CRC is re-checked by the
ATA interface when the data is transferred to the host,
or the Disk Formatter checks the CRC that is read from
the media. The addition of CRC to the ATA interface
adds a high degree of integrity, and detects most
memory errors that may occur in the buffer memory.
The target specification is intended as an initial disclosure of specification goals lor the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-214
SSI32C9600
ATA-2 Storage Controller
160 Mbit/s, 8-Bit NRZ Interface
PIN DESCRIPTION
The following convention is used in the pin description:
(I)
denotes an input
(0)
denotes an output
(1/0)
denotes a bidirectional signal
(Z)
denotes a tri-state output
(OD)
denotes an open drain output
Active low signals are denoted by a bar on top of the signal name and dual function pins are denoted with a
slash between the two signals - A9/HCS1.
GENERAL
NAME
TYPE
DESCRIPTION
VDD
-
POWER SUPPLY PIN
GND
-
GROUND
A(2:0)
I
HOST ADDRESS LINES. The Host Address lines A(2:0) are used to access
the various host control, status, and data registers.
HCS1
I
HOST CHIP SELECT 1. This pin selects access to the control block task file
registers.
HCSO
I
HOST CHIP SELECT O. This pin selects access to the command block task
file registers.
IOCS16
OD
16 BIT DATA TRANSFER. An open drain active low output that indicates that
a i6-bit buffer transfer is active.
IRQ
O,Z
HOST INTERRUPT. Asserted active high to indicate to the Host that the
controller needs attention.
10RDY
O,Z
1/0 CHANNEL READY. This signal is asserted low to extend host transfer
cycles when the controller is not ready to respond. This pin will be tristated
when a read or write is not in progress.
DREQ
O,Z
DMA REQUEST. The active high DMA Request signal is used during DMA
transfer between the Host and the controller.
DACK
I
DMA ACKNOWLEDGE. This active low signal is used during DMA transfer
between the host and the controller.
lOR
I
1/0 READ. This active low pin is asserted by the Host during a Host read
operation. When asserted with HCSO , HCS 1, or DACK, data from the device
is enabled onto the host data bus if the device is currently selected.
lOW
I
1/0 WRITE. Asserted active low by the HOST during a HOST write operation.
When asserted with HCSO , HCS1, or DACK, data from the host data bus is
strobed into the device.
-
HOST INTERFACE
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-215
II
SSI32C9600
ATA-2 Storage Controller
160 Mbit/s, a-Bit NRZ Interface
PIN DESCRIPTION (continued)
HOST INTERFACE (continued)
I
HOST RESET. This active low signal stops all commands in progress and
initializes the control/status registers - This signal can also "wake up" the
device while it is in power down mode.
I/O
HOST DATA BUS. These bits are used for word transfers between the Buffer
Memory and the Host; bits (7:0) are used for status, commands, or ECC byte
transfers.
DASP
1,00
DRIVE ACTIVE/DRIVE 1 PRESENT. This is a time-multiplexed signal which
indicates that a drive is active, or that Drive 1 is present.
PDIAG
1,00
PASSED DIAGNOSTICS. This signal is an output when configured as
Drive 1 and an input when configured as Drive O.
HRESET
HDB(15:0)
DISK INTERFACE
NAME
TYPE
INDEX
I
DESCRIPTION
INDEX. This pin serves as the index function forthe disk sequencer. When the
INPUTfunction is not available on the BA 16 pin, this pin can function as input
or index.
DOUTPUT
0
DISK SEQUENCER OUTPUT. This pin is controlled by bit 2 of the control field
of the disk sequencer.
DINPUT1/SBD
I
DISK SEQUENCER INPUT 1: This pin may be used to synchronize the
sequencer to an external event.
DINPUT2IFAULT
I
DISK SEQUENCER INPUT 2: This pin may be used to synchronize the
sequencer to an external event, or as a write fault signal.
AMD/SECTOR
I
ADDRESS MARK DETECT/SECTOR. In Hard Sector mode, this is the input
for the sector pulse from the disk drive. In Soft Sector mode, a low-level input
during a read indicates an address mark was detected.
RG
0
READ GATE. This active high output enables the reading of the disk. It is
asserted at the beginning of the PLO for header and data field by the
sequencer. It is automatically deasserted at the end of the CRC or ECC.
WG
0
WRITE GATE. This active high output enables writing onto the disk. It is
asserted and deasserted by the sequencer.
RRCLK
I
READ REFERENCE CLOCK. This pin is used in conjunction with the NRZs
pin to clock data in. It is also used as a clock forthe disk sequencer and is used
to generate WCLK.
WCLK
0
WRITE CLOCK. This signal clocks the NRZ data out.
NRZ (7:0)
110
NON RETURN TO ZERO. These signals are the read data input 0 through 7
from the disk drive when the read gate Signal is asserted; it is the write data
output to the disk drive when the write gate signal is asserted. NRZ7 is the most
significant bit.
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-216
SSI32C9600
ATA-2 Storage Controller
160 Mbit/s, 8-Bit NRZ Interface
MICROPROCESSOR INTERFACE
NAME
TYPE
DESCRIPTION
RST
I
RESET. An asserted active low input generates a component reset that holds
the internal registers of the controller at reset, stops all operations within the
chip, and deasserts all output signals. All input/output signals and Host outputs
are set to the high-Z state.
ALE/M/NM
I
ADDRESS LATCH ENABLE/Multiplexed or Non-multiplexed address select:
If this input is constantly low, the microprocessor interface is configured with
non-multiplexed address and data busses. If this input is ever high, the
microprocessor interface is configured with a multiplexed address and data
bus. In this case, this pin functions as the address latch enable, and the latched
address is output on the MA(7:0) pins.
CS
I
CHIP SELECT. This signal must be asserted high for all microprocessor
accesses to the registers of this chip.
WR/R/W
I
WRITE STROBE/READ/WRITE. When the Intel bus control interface is
selected, this signal acts as the WR signal. When the Write strobe signal is
asserted low and the CS signal is asserted high, the data on the AD lines will
be written to the register.
When the Motorola bus control interface is selected, this signal acts as the
R/W signal. A high on this input along with the RD/DS signal asserted and the
CS signal asserted high indicates a read operation. A low on this input along
with the RD/DS signal asserted and the CS signal asserted high indicates a
write operation.
RDIDS
DINTIINT
AD(7:0)
I
READ STROBE/DATA STROBE. When the Intel bus control interface is
selected, this signal acts as the RD signal. When the read strobe signal is
asserted low and the CS signal is asserted high, the data from the specified
register will be driven onto the AD signals.
When the Motorola bus control interface is selected, this signal acts as the OS
signal. A high on the R/W signal along with this signal asserted and the CS
signal asserted high indicates a read operation. A low on the RIW signal along
with this signal asserted and the CS signal asserted high indicates a write
operation.
0,00
DISK INTERRUPT. This signal is an interrupt line to the microprocessor. It is the
combined interrupt line of the disk side and host side interrupts when pin
READY/AINT is programmed as Ready; otherwise, it only signals the occurrence of disk side interrupt events. This signal is programmable for either a
push-pull or open-drain output circuit. This signal powers up in the high-Zstate.
I/O
ADDRESS/DATA BUS. When configured in the Multiplexed mode, these lines
are multiplexed, bidirectional data path to the microprocessor. During the
beginning of the memory cycle the bus captures the low order byte of the
microprocessor address. These lines provide communication with the controller device's internal registers and the buffer memory.
When configured in the Non-multiplexed mode, these lines are bidirectional
data lines.
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-217
II
SSI32C9600
ATA-2 Storage Controller
160 Mbit/s, a-Bit NRZ Interface
PIN DESCRIPTION (continued)
MICROPROCESSOR INTERFACE (continued)
NAME
TYPE
MA(7:0)
110
MICROPROCESSOR ADDRESS BUS: This 8-bit output bus is the AD(7:0)
bus latched by the ALE pin during the low order address phase of a Multiplexed
type microprocessor cycle. These signals are non-multiplexed address input
when used with a Non-multiplexed microprocessor.
MAl (9:8)
I
MICROPROCESSOR ADDRESS INPUTS: These signals are address input
lines lor bits 9 and 8 of the address. They are inputs regardless of whether
multiplexed or non-multiplexed data and address busses are used. In the
multiplexed mode, these bits are latched internally with the ALE signal; in the
non-multiplexed mode, they are not latched.
O,OD
READY/HOST SIDE INTERRUPT: When programmed as the Ready function, this signal is deasserted low for the microprocessor to insert wait states
to allow time for the chip to respond to the access. When programmed as the
host side interrupt, this pin interrupts the microprocessor when there is a host
related interrupt event. The interrupt signal is programmable for either a pushpull oropen-drain output circuit. This signal powers up as the 'Ready'function.
I
BUFFER WINDOW SELECT: This signal is asserted during microprocessor
access of the buffer window.
READY/AINT
BS
DESCRIPTION
BUFFER MANAGER INTERFACE
NAME
TYPE
DESCRIPTION
SYSXI
I
CRYSTAL INPUT/SYSTEM CLOCK: This is the crystal input to the buffer
manager frequency synthesizer, or the clock input that is used to generate
buffer memory access cycles when the frequency synthesizer is bypassed.
SYSXO
0
CRYSTAL OUTPUT.
CAS/SMOE
0
COLUMN ADDRESS STROBE/SRAM MEMORY OUTPUT ENABLE: This
signal is used as the column address strobe in DRAM mode, or the memory
output enable in SRAM mode. After RST is asserted, this signal will be high.
WE
0
WRITE ENABLE: This signal is asserted low when a buffer memory write
operation is active.
BD(15:0)
I/O
BUFFER MEMORY DATA BUS: These signals are bits 15-0 of the 16-bit
parallel data lines to/from the buffer memory.
BA16/XCLK
0
BUFFER ADDRESS 16/SYNTHESIZER OUTPUT CLOCK: This signal is either
the output of the frequency synthesizer, or buffer address 16. At reset, this signal
is the equivalent of the signal at SYSXI (input clock to the frequency synthesizer.)
BA 15/AINT/SBD
110
BUFFER ADDRESS 15/AT INTERRUPT/SYNC BYTE DETECT: This signal
may be used for addressing the buffer memory in SRAM mode, or as a
separate local microprocessor interrupt forthe host interface, or as a sync byte
detect signal input for the disk formatter. After RST is asserted, this signal will
be configured as SBD (i.e., as an input).
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-218
SSI32C9600
ATA-2 Storage Controller
160 Mbit/s, 8-Bit NRZ Interface
BUFFER MANAGER INTERFACE
TYPE
NAME
DESCRIPTION
BA14/BDP1
I/O
BUFFER MEMORY ADDRESS 14/BUFFER DATA PARITY 1: This signal is
used for addressing the buffer memory in SRAM mode, or as the parity bit for
BD(15:8) in DRAM mode.
BA13/BDPO
I/O
BUFFER MEMORY ADDRESS 13/BUFFER DATA PARITY O:This signal is
used for addressing the buffer memory in SRAM mode, or as the parity bit for
BD (7:0) in DRAM mode.
BA12/RAS
0
BUFFER MEMORY ADDRESS 12/ROW ADDRESS STROBE: This signal is
used for addressing the buffer memory in SRAM mode, or as the row address
strobe in DRAM mode. After RST is asserted, this signal will be high.
BA(11:0)
0
BUFFER MEMORY ADDRESS LINES: These are bits 11-0 for addressing
the buffer memory.
MSIDMOE
0
MEMORY SELECT/DRAM MEMORY OUTPUT ENABLE: This pin is configured
as memory select in SRAM mode, or as memory output enable in DRAM mode.
II
Target Specification: The target specification is intended as an initial disclosure of specification goals for the product. The specifications
are based on design goals, subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture
unless agreed to in writing.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
ofthird parties resulting from its use. No license is granted under any patents, patent rights ortrademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing order
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
© 1993 Silicon Systems, Inc.
9-219
0194
Notes:
9-220
SSI32C9800
SCSI-3 Storage Controller
160 Mbit/s, a-Bit NRZ Interface
• iji Ii tAl ~N'" 'iiittl ;,
December 1993
FEATURES
DESCRIPTION
The SSI SSI 32C9800 is an advanced CMOS VLSI
device which integrates major portions of the hardware
needed to build an SCSI disk drive. The SSI32C9800
has an eight bit wide NRZ channel interface with disk
transfers rates up to 160 Megabits per second, an
advanced SCSI-3 interface which supports host
transfer rates up to 20 megabytes per second, and a
sixteen bit wide data buffer interface capable of
supporting concurrent full speed transfers on both disk
and host interfaces. The circuitry of the SSI SSI
32C9800 includes: a complete, highly automated SCSI
interface; an advanced, fully integrated Buffer
SCSI Bus Interface
Full SCSI-2 and SCSI-3 compatibility
Direct bus interface logic with on-chip
48 rnA SCSI tolerant drivers
(continued)
(continued)
Synchronous transfer rates up to 20
megabytes per second (fast and wide)
Asynchronous transfer rates up to 10
megabytes per second (wide)
Parity generation and checking
BLOCK DIAGRAM
I FREQUENCY
SYNTHESIZER
GPIO 0·2
PAREN
SOB (15:0)
SDBP. SDBPl
MSG
~
HOST OAT A BUS
~P DATA BUS
~
~
c/O
I
SCSI
INTERFACE
I
I
f+-
:
I
I
-OIsKFORMATTER- -
I
liMe
~
!o,
l'IDAJS
wFIIRNl
DiiiffAliIT
~
SINT
READY/AfNT
RST
r--i-
e
~
~
MICRO·
PROCESSOR
INTERFACE
l-
I
I
I
I
I
I
I
I
I
I
I
I
I I
I
I
H
~
,
~
II
I
~
I
BUFFER
I
ARBITRATOR
t
~
"l
~
I
DRAM/SRAM
CONTROL
~~
:
I
I
..J
I
"'1
Jl
I DISK FIFO
32 BYTE
in
DATA
MUX
C
0
M
P
A
R
E
'---
I
1
BD(15:0)
BA16/XCLK
BA15/AINTISBD
BA14/BDPl
BA13/BDPO
BA121RAS
BA(11:0)
WE
CAS/MOE
Ms/DMOE
AMDISECTOR
RG
:s WG
:s INDEX
SEQUENCER
WCS
31 INSTRUCTIONS
I
I
I
I
I
I
I :
DATA
~ MULTIPLEXER
SYSXI
] SYSXO
:- -BUFFER !ANAGER
S}
AD (7:0)
MAl (9:8)
MA(7:0)
BS
CS
ALE/M/NM
1
I
HEADEHJ
FILE
SPUT FIELD
SUPPORT
LOGIC
L
~
DINPUT1 ISBD
DINPUT2IFAULT
DOUTPUT
I
.J..,
I
:s WCLK
"l NRZ (7:0)
I
H
I
ECC
CHKIGEN
III
RRCLK
* :
I
ICOR~~TORI :
t
I
---------------------------I
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
1293
9-221
II
SSI32C9800
SCSI-3 Storage Controller
160 Mbit/s, 8-Bit NRZ Interface
DESCRIPTION (continued)
FEATURES
(continued)
Auto Command Mode (ACM) SCSI state
machine performs high level SCSI sequences
without microprocessor intervention
Four level ACM command FIFO supports
automatic execution of multiple ACM
commands
Hardware support for automatic handling of
command queuing
Manager; a high performance Disk Formatter; and two
fast Reed-Solomon ECC's, one forthe header field and
a second for the data field, both with on-the-fly
hardware correction. The SSI SSI 32C9800
maximizes performance while minimizing
microcontroller intervention.
The SSI SSI 32C9800 also supports dual bit NRZ
interfaces. In dual bit mode, transfer rates up to 100
megabits per second on the disk interface are
supported.
Automatic SCSI CDB size determination
Automatic SCSI disconnect and reconnect
Thirty-two byte data FIFO between SCSI
channel and Buffer Manager
Buffer Manager
Direct support of DRAM or SRAM
SRAM: up to 256k bytes of memory with
throughput to 40 megabytes per second
DRAM: up to 8 megabyte of memory with
throughput to 36 megabytes per second
Buffer CRC or buffer parity for increased data
integrity
Programmable memory timing
Flexible buffer RAM segmentation
Dedicated host, disk and microprocessor
address pointers
Buffer.streaming with internal buffer protection
circuit providing buffer integrity
Disk Formatter
8-Bit NRZ interface supporting data rates to
160 megabits per second, or
2-Bit NRZ interface supporting data rates to
100 megabits per second
Automatic multi-sector transfers
Error tolerant sync detection
Header or microprocessor based split data
field support
Advanced sequencer organized in 31 x 4
bytes
Timeouts for sync detection, sector or index
pulse detection, and retry limiting
144-bit Reed Solomon ECC for the data field,
with "on-the-fly" fast hardware correction
circuitry
Capable of correcting up to six 8-bit
symbols in error
The highly automated Header ECC logic performs
corrections on the header within one or two byte times,
and Data ECC is capable of performing corrections in
real time, allowing the SSI 32C9800 to read every
sector on the disk in a single revolution even if every
sector contained a correctable error.
The SSI SSI 32C9800 is the latest in a line of
sophisticated disk storage controllers. Other Silicon
Systems' disk storage controllers inClude: the SSI
32C9600 ATA-2 controller, with host transfer rates up
to 22 megabytes per second and disk data rates of up
to 160 megabits per second. The SSI 32C9001, SSI
32C9301, SSI 32C9302 and SSI 32C9003 ATA
controllers provide dual and serial N RZ data rates to 80
Megabits per second and ATA speeds to 13.3
megabytes per second. The SSI SSI 32C9020, SSI
32C9022, 32C9023 and SSI32C9024 family members
are SCSI disk controllers supporting fast, 8-bit wide
SCSI interface, with disk data rates to 80 Megabits per
second. The SSI SSI 32C9340 disk controller
completes the family providing PCMCIA/ATA
compliant interfaces. All members are based on a
common architecture allowing major portions of
firmware to be reused. The Silicon Systems' chip
family is illustrated in the hierarchy chart shown in
Figure 1.
The high level of integration within the SSI SSI
32C9800 represents a major reduction in parts count.
When the SSI SSI 32C9800 SCSI Controller is
combined with the SSI SSI 32R1510BR or SSI SSI
32R2110R Read/Write device, the SSI SSI 32P4782
Read Channel (1,7) or SSI 32P4901 PRML Read
Channel (8/9), the SSI 32H4631 Servo and Motor
Speed Controller, an appropriate microcontroller and
memory, a complete, cost efficient, high performance
intelligent drive solution is created.
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-222
SSI32C9800
SCSI-3 Storage Controller
160 Mbit/s, 8-Bit NRZ Interface
Guaranteed to correct a single 41-bit error
burst, or two 17-bit error bursts
Fast hardware on-the-fly correction
assures continuous data transfers even if
consecutive sectors are in error
40-bit Reed Solomon ECC forthe headerfield,
with "on-the-f1y" hardware correction circuitry
which completes within 1 or 2 bytes time
Guaranteed to correct a single 9-bit error
burst
Microprocessor Interface
Supports both multiplexed or non-multiplexed
microprocessors
Separate host and disk interrupts
1024 byte buffer window with wait states or
pulled access
Other Features
Internal power down mode
Frequency synthesizer for buffer clock
Available in 144 OFP or TOFP and 128 OFP or
TOFP packages
FUNCTIONAL DESCRIPTION
The SSI 32C9800 contains the following four major
functional blocks:
Microprocessor Interface
ATA Interface
Disk Formatter
Buffer Manager
The microprocessor interface allows the local
microprocessor access to all of the SSI 32C9800
internal control registers and any location within the
buffer memory. The microprocessor, by writing and
reading the internal registers, can control all activities
of the SS132C9800. The microprocessor can elect to
perform host and/or disk operations directly, or it can
enable the advanced features of the SSI 32C9800
which can perform these operations automatically.
The SCSI Interface block handles all SCSI activities.
The SCSI interface includes 48 mA drivers allowing for
direct connection of the SSI32C9800 to the SCSI bus.
In addition, the SCSI interface contains control signals
for use with off-chip differential transcievers. The SCSI
interface logic includes Auto Command Mode (ACM)
(continued)
bit/s NR,
Z
32 M'
AT Controller,
56-B~ ECC
48 MbiVs NRZ,
AT Controller,
88-Bit RIS ECC
I¥isw§§ I
I
r,~,"~
I
I32C9001 I
48 MbiVs NRZ,
SCSI Controller,
88-Bit RIS ECC
I
I32C9340 I
48 MbiVsNRZ,
PCMC IA/ATA Controller,
88-Bit RIS ECC
Dual-b~ NRZ
3V/5V
~'~I
32 MbiVs NRZ,
SCSI Controller,
88-Bit RIS ECC
I
I32C9020 I
I
I32C9301 I
I
I32C93021
I
I32C9003 I
48 MbiVs NRZ,
ATA Controller,
88-Bit RIS ECC
Dual-b~ NRZ
3V/5V
48 Mbitls NRZ,
ATA Controller,
88-Bit RIS ECC
Dual-Bit NRZ
3V/5V
80 Mbitls NRZ,
ATA Controller,
88-Bit RIS ECC
Dual B~ NRZ
I32C9022 I
I
I
I32C9023 I
48 MbiVs NRZ,
SCSI Controller,
88-Bit RIS ECC
Dual-Bit NRZ
I
I32C9024 I
80 MbiVsNRZ,
SCSI Controll er,
88-Bit RlS ECC
Dual-Bit NRZ
SCSI Different ial
80 Mbit/s NRZ,
SCSI Controller,
88-Bit RIS ECC
Dual-Bit NRZ
[32C9600
J
160 MbiVs NRZ,
ATA Controller,
144-Bit RIS ECC
Dual-/8-bit NRZ
I
32C9800
j
160 Mbitls NRZ,
SCSI·3 Controller,
144-Bit RIS ECC
Dual-/8-b~ NRZ
SCSI Differential
FIGURE 1: Silicon Systems' Disk Controller Chip Hierarchy
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding luture manufacture unless agreed to in writing.
9-223
II
SSI32C9800
SCSI-3 Storage Controller
160 Mbit/s,8-Bit NRZ Interface
FUNCTIONAL DESCRIPTION (continued)
logic, an advanced state machine capable of handling
a variety of complex SCSI sequences without
microprocessor intervention. The microprocessor can
queue up to four ACM commands into the ACM
Command FIFO to create even more sophisticated
command sequences. The SCSI block interfaces
directly with the Buffer Manager via an internal speed
matching FIFO. This FIFO, plus the bandwidth
capabilities oft he Buffer Managerguarantee sustained
full speed transfers across the SCSI bus. The high
level of automation of the ACM minimizes SCSI bus
overhead. The net result is maximized performance
with minimum SCSI bus band width utilization.
The disk formatter performs the serialization and
deserialization of data. It provides all of the necessary
functions to control track formatting, header search,
and the reading and writing of data. The heart of the
disk formatter is an advanced programmable
sequencer. The sequencer can contain 31 instructions,
each of which is 4 bytes (32 bits) in width. The width of
the instructions allows for sophisticated branching
techniques which increase the flexibility and power of
the sequencer. The flexible disk interface can be
configured through a wide range of capabilities. This
allows the SSI 32C9800 to interface with many different
read/write channels and allows the user of the
SSI32C9800 to select the read/write channel best suited
to the device. Of course, by selecting the SSI 32C9800
controller and the SSI 32P4901 PRML read channel
(8/9), you are guaranteed a problem free interface.
Within the disk formatter are the ECC generator/checker
and ECC corrector. The generator/checker provides
the ability to generate orcheck a 40-bit Reed-Solomon
ECC for headers and a 144-bit Reed-Solomon code for
data. The header ECC circuitry performs correction of
the header bytes within one or two byte times,
minimizing delays. The data ECC correction cirCUitry
performs data corrections rapidly. The data ECC
circuitry guarantees that the correction logic will always
be available to correct the next sector if necessary.
The disk formatter provides additional reliability by use
of error tolerant sync detection. This feature allows the
creation of a multi-byte sync field and the detection of
data synchronization even in the event of errors within
the sync field.
The buffer manager manages the data buffer of the
controller. The buffer manager can support either
SRAM or DRAM. When configured to operate with
DRAM, the buffer manager automatically performs
necessary refresh cycles. The buffer manager creates
all ofthe necessary timing and control signals for a wide
range of memory types and speeds. Besides interfacing
with the buffer memory, the buffer manager interfaces
with the ATA Interface block, the disk formatter block,
the ECC corrector and the microprocessor. If more
than one of these devices requires access to the buffer
memory, the buffer manager arbitrates the requests
automatically. The buffer manager of the SSI32C9800
can sustain SCSI operations althe rate of 10 megawords
(20 megabytes) per second, disk formatter operations
at 160 megabits per second and still has sufficient
band-width left to handle on-the-fly ECC corrections
and microprocessor accesses without degrading
performance on any of the interfaces.
Besides the ability to generate and check data parity,
the SCSI interface also includes a CRC generation and
checking capability. During writes, a CRC can be
generated on data received from the host and checked
when the data is transferred to the Disk Formatter. The
CRC is part of the data ECC and is always written by the
Disk Formatter. If the SCSI interface generates the
CRC, then the Disk Formatter writes the CRC field that
was generated by the SCSI interface to the media, or
the Disk Formatter generates the CRC itself. During
reads, the CRC is read from the media ;by the Disk
Formatter. If Buffer CRC is enabled, the Disk Formatter
writes the CRC to the buffer and the CRC is re-checked
by the SCSI interface when the data is transferred to the
host, or the Disk Formatter checks the CRC that is read
from the media. The addition of CRC to the SCSI
interface adds a high degree of integrity, and detects
most memory errors that may occurin the buffer memory.
The. target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. SIlicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-224
SSI32C9800
SCSI-3 Storage Controller
160 Mbitls, 8-Bit NRZ Interface
PIN DESCRIPTION
The following
(I)
(0)
(Z)
(OD)
convention is used in the pin description:
denotes an input
denotes an output
denotes a tri-state output
denotes an open drain output
GENERAL
NAME
TYPE
-
VDD
GND
DESCRIPTION
POWER SUPPLY PIN
GROUND
HOST INTERFACE
SDBP, SDBP1
I/O
SCSI DATA BUS PARITY. Odd parity bit for the SCSI data bus.
SDB(15:0)
I/O
SCSI DATA BUS BITS 7-0.
ATN
I
ATTENTION. This active low signal is used by the initiator to request a
message out phase.
BUSY. This active low signal is used to indicate when the bus is active.
BSY
I/O
ACK
I
ACKNOWLEDGE. This active low signal is used in the handshake protocol to
indicate the completion of a data byte transfer.
SRST
I
SCSI RESET. This active low signal is used to reset the SCSI controller.
MSG
0
MESSAGE. This active low signal is used to indicate a message phase.
SEL
I/O
SELECT. This active low signal is used to indicate either a selection or
reselection phase.
C/D
0
COMMAND/DATA. This signal is used to indicate either a command or data phase.
REQ
I
REQUEST. This active low signal is used in the handshake protocol to initiate
a data byte transfer.
I
INPUT/OUTPUT. This signal is used to indicate the direction of data transfer.
I/O
INPUT/OUTPUT. These pins are used to indicate the SCSI ID of the target
device. The pins can be programmed as outputs for test purposes only.
I
INDEX. This pin serves as the index function forthe disk sequencer. When the INPUT
function is not available on the BA 16 pin, this pin can function as input or index.
0
DISK SEQU ENCER OUTPUT. This pin is controlled by bit 2 of the controllield
of the disk sequencer.
DINPUT1/SBD
I
DISK SEQUENCER INPUT 1: This pin may be used to synchronize the
sequencer to an external event.
DINPUT2/FAULT
I
DISK SEQUENCER INPUT 2: This pin may be used to synchronize the
sequencer to an exteranl event, or as a write fault signal.
I/O
-
GPI0(2:0)
DISK INTERFACE
INDEX
DOUTPUT
-
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-225
II
SSI32C9800
SCSI-3 Storage Controller
160 Mbit/s, 8-Bit NRZlnterface
PIN DESCRIPTION (continued)
DISK INTERFACE (continued)
NAME
TYPE
DESCRIPTION
I
ADDRESS MARK DETECT/SECTOR. In Hard Sector mode, this is the input
forthe sector pulse from the disk drive. In Soft Sector mode, a low-level input
during a read indicates an address mark was detected.
RG
0
READ GATE. This active high output enables. the reading of the disk. It is
asserted at the beginning of the PLO for header and data field by the
sequencer. It is automatically deasserted at the end of the CRC or ECC.
WG
0
WRITE GATE. This active high output enables writing onto the disk. It is
asserted and deasserted by the sequencer.
RRCLK
I
READ REFERENCE CLOCK. This pin is used in conjunction with the NRZs
pin to clock data in. It is also used as a clock forthe disk sequencer and is used
to generate WCLK.
WCLK
0
WRITECLOCK. This signal clocks the NRZ data out.
NRZ (7:0)
I/O
NON RETURN TO ZERO. These signals are the read data input 0 through 7
from the disk drive when the read gate signal is asserted; it is the write data
output to the disk drive when the write gate signal is asserted. NRZ7 is the most
siQnificant bit
AMD/SECTOR
MICROPROCESSOR INTERFACE
NAME
TYPE
DESCRIPTION
RST
I
RESET. An asserted active low input generates a component reset that holds
the internal registers of the controller at reset, stops all operations within the
chip, and deasserts all output signals. All inpuVoutput signals and Host outputs
are set to the high-Z state.
ALEIM/NM
I
ADDRESS LATCH ENABLE/Multiplexed or Non-multiplexed address select:
If this input is constantly low, the microprocessor interface is configured with
non-multiplexed address and data busses. If this input is ever high, the
microprocessor interface is configured with a multiplexed address and data
bus. In this case, this pin functions as the address latch enable, and the latched
address is output on the MA(7:0) pins.
CS
I
CHIP SELECT. This signal must be asserted high for all microprocessor
accesses to the registers of this Chip.
WR/R/W
I
WRITE STROBE/READ/WRITE. When the Intel bus control interface is
selected, this signal acts as the WR signal. When the Write strobe signal is
asserted low and the CS signal is asserted high, the data on the AD lines will
be written to the register.
When the Motorola bus control interface is selected, this signal acts as the
R/W signal. A high on this input along with the RDIDS signal asserted and the
CS signal asserted high indicates a read operation. A low on this input along
with the RD/DS signal asserted and the CS signal asserted high indicates a
write operation.
--
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals,
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-226
SSI32C9800
SCSI-3 Storage Controller
160 Mbit/s, 8-Bit NRZ Interface
MICROPROCESSOR INTERFACE
NAME
TYPE
RDIDS
I
(continued)
DESCRIPTION
READ STROBE/DATA STROBE. When the Intel bus control interface is
selected, this signal acts as the RD signal. When the read strobe signal is
asserted low and the CS signal is asserted high, the data from the specified
register will be driven onto the AD signals.
When the Motorola bus control interface is selected, this signal acts as the DS
signal. A high on the R/W signal along with this signal asserted and the CS
signal asserted high indicates a read operation. A low on the R/W signal along
with this signal asserted and the CS signal asserted high indicates a write
operation.
DINTIINT
AD(7:0)
O,OD
DISK INTERRUPT. This signal is an interrupt line to the microprocessor. It is
the combined interrupt line of the disk side and host side interrupts when pin
RDY/AINT is programmed as Ready; otherwise, it only signals the occurrence
of disk side interrupt events. This signal is programmableforeither a push-pull
or open-drain output circuit. This signal powers up in the high-Z state.
I/O
ADDRESS/DATA BUS. When configured in the Multiplexed mode, these lines
are multiplexed, bidirectional data path to the microprocessor. During the
beginning of the memory cycle the bus captures the low order byte of the
microprocessor address. These lines provide communication with the controller device's internal registers and the buffer memory.
When configured in the Non-multiplexed mode, these lines are bidirectional
data lines.
MA(7:0)
I/O
MICROPROCESSOR ADDRESS BUS: This 8-bit output bus is the AD(7:0)
bus latched by the ALE pin during the low order address phase of a Multiplexed
type microprocessor cycle. These signals are non-multiplexed address input
when used with a Non-multiplexed microprocessor.
MAl (9:8)
I
MICROPROCESSOR ADDRESS INPUTS: These signals are address input
lines for bits 9 and 8 of the address. They are inputs regardless of whether
multiplexed or non-multiplexed data and address busses are used. In the
multiplexed mode, these bits are latched internally with the ALE signal; in the
non-multiplexed mode, they are not latched.
O,OD
READY/HOST SIDE INTERRUPT: When programmed as the Ready function, this signal is deasserted low for the microprocessor to insert wait states
to allow time for the chip to respond to the access. When programmed as the
host side interrupt, this pin interrupts the microprocessor when there is a host
related interrupt event. The interrupt signal is programmable for either a pushpull oropen-drain output circuit. This signal powers up as the 'Ready' function.
I
BUFFER WINDOW SELECT: This signal is asserted during microprocessor
access of the buffer window.
RDY/AINT
BS
The target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals.
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing.
9-227
SSI32C9800
SCSI-3 Storage Controller
160 Mbit/s, 8-Bit NRZ Interface
PIN DESCRIPTION (continued)
BUFFER MANAGER INTERFACE
NAME
TYPE
SYSXI
I
SYSXO
0
CRYSTAL OUTPUT.
CAS/SMOE
0
COLUMN ADDRESS STROBE/SRAM MEMORY OUTPUT ENABLE: This
signal is used as the column address strobe in DRAM mode, or the memory
output enable in SRAM mode. After RST is asserted, this signal will be high.
WE
0
WRITE ENABLE: This signal is asserted low when a buffer memory write
operation is active.
BD(15:0)
110
BUFFER MEMORY DATA BUS: These signals are bits 15-0 of the 16-bit
parallel data lines to/from the buffer memory.
BA16/XCLK
0
BUFFER ADDRESS 16/SYNTHESIZER OUTPUT CLOCK: This signal is either
the output of the frequency synthesizer, or buffer address 1q. At reset, this signal
is the equivalent of the signal at SYSXI (input clock to the frequency synthesizer.)
BA15/AINT/SBD
I/O
BUFFER ADDRESS 15/AT INTERRUPT/SYNC BYTE DETECT: This signal
may be used for addressing the buffer memory in SRAM mode, or as a
separate local microprocessor interrupt forthe host interface, or as a sync byte
detect signal input for the disk formatter. After RST is asserted, this signal will
be configured as SBD (Le., as an input).
BA14/BDP1
I/O
BUFFER MEMORY ADDRESS 14/BUFFER DATA PARITY 1: This signal is
used for addressing the buffer memory in SRAM mode, or as the parity bit for
BD(15:8) in DRAM mode.
BA13/BDPO
I/O
BUFFER MEMORY ADDRESS 13/BUFFER DATA PARITY 0: This signal is
used for addressing the buffer memory in SRAM mode, or as the parity bittor
BD (7:0) in DRAM mode.
BA12/RAS
0
BUFFER MEMORY ADDRESS 12/ROW ADDRESS STROBE: This signal is
used for addressing the buffer memory in SRAM mode, or as the row address
strobe in DRAM mode. After RST is asserted, this signal will be high.
BA (11:0)
0
BUFFER MEMORY ADDRESS LINES: These are bits 11-0for addressing the
buffer memory.
MS/DMOE
0
MEMORY SELECT/DRAM MEMORY OUTPUT ENABLE: This pin is configured
as memory select in SRAM mode, or as memory output enable in DRAM mode.
DESCRIPTION
CRYSTAL INPUT/SYSTEM CLOCK: This is the crystal input to the buffer
manager frequency synthesizer, or the clock input that is used to generate
buffer memory access cycles when the frequency synthesizer is bypassed.
Target Specification: The target specification is intended as an initial disclosure of specification goals for the product. The specifications
are based on design goals. subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture
unless agreed to in writing.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing order
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
© 1993 Silicon Systems, Inc.
9-228
1293
Section
10
OPTICAL/FLOPPY
CIRCUITS
II
10
10-0
SSI33P3700
8-48 Mbit/s Magneto
0ilical Read Channel
•i' '~VI4§§n[¥nt."i
DESCRIPTION
Th.e SSI33P3700 is a high performance SiGMaS single
chip read channel IG that contains all the functions
needed to implement a complete zoned recording read
channel for magneto optical (MO) drive systems.
Functional blocks include a sum and difference
amplifier, input attenuator, pulse detector,
programmable filter, time base generator, and data
synchronizer. MO data rates from 8 to 48 MbiVs for 1,7
code or 6 to 36 MbiVs for 2,7 code can be programmed
usi~g an internal DAG whose reference current is set by
a smgle external resistor.
Programmable functions of the SSI33P3700 device are
controlled through a bidirectional serial port and banks
of i~ter~al registers. This allows zoned recording
applicatIOns to be supported without changing external
component values from zone to zone.
The SSI 33P3700 utilizes an advanced SiGMaS
proce~s techn~logy along wHh advanced circuit design
techmques which resuH in a high performance device
with low power consumption.
FEATURES
GENERAL
Programmable MO/EMBOSS data rates of 8 to
~ Mbitls (1,7 RLL), or 6 to 36 Mbit/s (2,7 RLL)
mternal DAC controlled
Complete zoned recording application support
Low power operation (TBD mW typical @ 5V)
Bidirectional serial port register access
Register programmable power management
(Sleep mode < TBD mW)
Power supply range (4.5 to 5.5 V)
Small footprint 64-lead TQFP package
PULSE DETECTOR
Provides head amplifier difference for MO
signals and sum for emboss signals
Dual programmable attenuator (x 1/16 min, 4 bit
resolution) for emboss and MO data with Low-Z
switch and internal multiplexer
Fast Attack/Decay modes for rapid AGC
recovery
Dual rate charge pump for fast transient
recovery
January 1994
Low drift AGC hold circuitry
Temperature compensated, exponential
control AGC
Wide bandwidth, high precision full-wave
rectifier
Programmable LEVEL pin time constant with
separate MO and emboss
Optimized pulse qualification circuitry for pit
mark recording with input clamp circuit
Internal fast decay timing
External Low-Z control pin
0.5 ns maximum pulse pairing with sine wave
input
PROGRAMMABLE FILTER
Programmable cutoff frequency of 4 to 24 MHz
Programmable boost/equalization of 0 to 13 dB
Matched normal and differentiated outputs
±20% Fc accuracy (Fc = 4 to 8 MHz)
±15"10 Fc accuracy (Fc = 8 to 24 MHz)
±3% maximum group delay variation
Less than 1.5% total harmonic distortion
Low-Z input switch controlled by LOW_Z pin
No external filter components required
TIME BASE GENERATOR
BeHer than 1% frequency resolution
Up to 75 MHz frequency output
Independent divide by M and N registers
VCO center frequency matched to data
synchronizer VCO
VCO (FOUT) output available in all modes but
power down
DATA SYNCHRONIZER
Fast acquisition phase lock loop with zero
phase restart technique
Fully integrated data synchronizer - no
external delay lines, active devices, or active
PLL components
Programmable decode window symmetry
control via serial port
Window shift control ±30% (4-bit)
Includes delayed read MO/emboss data and
VCO clock monitor points
Separate qualifier output (ROO) and data
separator input (RDI)
The. target specification is intended as an initial disclosure of specification goals for the product. The specifications are based on design goals
subject to change and are not guaranteed. Silicon Systems assumes no obligation regarding future manufacture unless agreed to in writing:
0194
10-1
II
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Target Specification: The target specification is intended as an initial disclosure of specification goals for the product. The specifications
are based on deSign goals~ subject to change and are not guaranteed.
No responsibility is assumed by Silicon Systems for use of this product nor for any Infringements of patents and lrademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights ortrademarils of Silicon Systems. SHicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Siflcon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 5~OOO, FAX (714) 5~14
0194
10-2
11:>1993 SHicon Systems, Inc.
SSt 33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
I; i§ '" ,"'i'f' .ifte'
December 1993
Wide bandwidth, high precision full-wave
rectifier
Programmable LEVEL pin time constant with
separate MO data and embos~"reglsters
Separate Read and emboss AGC levels (4-bit DAC)
DESCRIPTION
The SSI 33P3733A device is a high performance
BiCMOS single chip read channellC that contains all
the functions needed to implement a complete zoned
recording read channel for magneto-optical (MO) drive
systems. Functional blocks include the pulse detector,
programmable filter, time base generator, and data
synchronizer. MO data rates from 8 to 26.5 Mbitls for
(1,7) code, 6 to 20 Mbitls for (2,7) code can be
programmed using an internal DAC whose reference
current is set by a single external resistor.
Pulse qualification circuitry is provided for Pit
Mark detection
Internal fast decay timing
External LOW_'1. control pin
0.5 ns max. pulse pairing with sine wave input
PROGRAMMABLE FILTER
Prog rammable cutoff frequency of 4 to 12 MHz
Programmable functions of the SSI 33P3733A device
are controlled through a bi-directional serial port and
banks of internal registers. This allows zoned
recording applications to be supported without
changing external component values from zone to
zone.
Programmable boost/equalization ofOto 13 dB
Matched normal and differentiated outputs
± 10 to 15"10 Ic accuracy
± 2"10 maximum group delay variation
The SSI 33P3733A utilizes an advanced BiCMOS
process technology along with advanced circuit design
techniques which result in a high performance device
with low power consumption.
Less than 1.5"10 total harmonic distortion
Low-Z input switch controlled by LOW_'1. pin
No external filter components required
TIME BASE GENERATOR
FEATURES
Better than 1"10 frequency resolution
Programmable MO data rate of 8 to 26.5 Mblt/s
for (1,7) code, 6 to 20 Mblt/s for (2,7) code,
Internal DAC controlled
Complete zoned recording application
support
Up to 75 MHz frequency output
Independent divide-by M and N registers
VCO center frequency matched to data
synchronizer VCO
Low-power operation (375 mW typical @ 5V)
VCO (FOUT) output available independent of
the mode
DATA SEPARATOR
Bi-directional serial port for register access
Register programmable power management
(Sleep mode <5 mW )
Fast acquisition phase lock loop with zero
phase restart technique
Power supply range (4.5 to 5.5 volts)
Dual rate charge pump for fast transient
recovery
Fully integrated data separator
- No external delay lines, active devices, or
active PLL components required
Programmable decode window symmetry
control via serial port
- Window shift control ± 30"10 (4-bit)
Low Drift AGC hold circuitry
-
Small footprint 64-lead TQFP package
PULSE DETECTOR
Fast Attack/Decay modes for rapid AGC
recovery
Temperature compensated, exponential
control AGC
1293
10-3
Includes delayed read MO data and VCO
clock monitor points
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SSI 33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
FUNCTIONAL DESCRIPTION
The SSI 33P3733A implements a high performance
complete read channel, including pulse detector,
programmable active fiHer, time base generator, and
data synchronizer, at MO data rates up to 26.5 Mbitls
for (1 ,7) code, 20 Mbitls for (2,7) code. A circuit block
diagram is shown in Figure 1.
PULSE DETECTOR CIRCUIT DESCRIPTION
The pulse detector, in conjunction with the
programmable fiRer, provides all the MOdata processing
functions necessary for detection and qualification of
encoded read signals. The signal processing circuits
include a wide bandwidth variable gain amplifier, a
precision wide bandwidth fullwave rectifier, and a dual
rate charge pump. The entire signal path is fullydifferential to minimize external noise pick up.
AGCCIRCUIT
The gain of the AGC amplifier is controlled by the
voHage (VSYpx) stored on the BYPx hold capacitor
(CBYPX). A dual rate charge pump drives CBYPX with
currents that depend on the instantaneous differential
voHage at the DP/DN pins. Attack currents lower VBYPX
which reduces the amplifier gain, while decay currents
increase VSYPX which increases the amplifier gain.
When the Signal at DP/DN is greater than 100% of the
programmed AGC level, the nominal attack current of
0.18 rnA is used to reduce the amplifier gain. If the
Signal is greater than 125% of the programmed AGC
level, a fast attack current of eight (8) times nominal is
used to reduce the gain. This dual rate approach allows
AGC gain to be quickly decreased when it is too high!
low yet minimizes distortion when the proper AGC level
has been acquired.
A constant decay current of 4 ~ acts to increases the
amplifiergainwhenthe signal at DP/DN is less than the
programmed AGC level. The large ratio (0.18 mA:4~)
of the nominal attack and nominal decay currents
enable the AGC loop to respond to the peak amplitudes
of the incoming read signal rather than the average
value. A Fast Decay Current mode is provided to allow
the AGC gain to be rapidly increased, if required. In
Fast Decay mode, the decay current is increased by a
factor of 21.
In Read mode and Write mode, the reference voHage
for the AGC charge pump is a nominal 1.0V. When
MOEG is high, the reference voltage for the AGC
charge pump is set by a 4-bitDAC (DACA) controlled
by the serial port. The DAC output voHage is offset so
that "1111" resuHs in a O. 75Voutput, and "0000" resuHs
in a 1.00V output:
VAGC
=1.00· (DACA x 0.01667) Vpp
where DACA is the decimal value of the DACA register
When the chip is in Power Down mode, the AGC dual
rate charge pump is disabled.
Upon power up, the Low-Zlfast decay sequence should
be executed to rapidly recover from any transients or
drift which may have occurred on the BYPx hold
capacitors.
BYPMO AND BYPE CONTROL VOLTAGE
The BYPMO capacitor voHage will be held constant
(subject to leakage currents) during Sleep mode,
Emboss mode (MOEG = high), Write mode, or when
the HOLD signal is high. Upon the transition of PWRON
from high to low, there is a 1 ).IS delay inserted before
the AGC charge pump is allowed to drive the BYPMO
capacitor. When MOEG is high, the charge pump
drives the BYPE capacitor. When MOEG is low, the
BYPE capacitor voltage will be held constant (subject
to leakage currents).
AGC MODE CONTROL
When write gate (WG) is driven low, the dual rate
charge pump is disabled causing the AGC amplifier
gain to be held constant. When the WG pin tranSitions
from low to high, the LOW_Z mode can be entered
using the LOW_'1. control pin. When this pin is brought
low, the input impedance at both the AGC amplifier and
the programmable filter are reduced to allow for quick
recovery of the AC coupling capacitors. When the
LOW_'1. pin goes high, the Fast Decay mode is triggered
allowing rapid acquisition of the proper AGC level. The
duration of the Fast Decay mode is internally set at a
nominal 1 ).IS. Fast Decay mode is also triggered by a
transition of the MO/emboss gate (MOEG) pin in either
direction. When the pulse detector is powered-down,
VBYPX will be held constant subject to leakage currents
only.
External control for enabling the dual rate charge pump
is also provided. Driving the HOLD pin high forces the
dual rate charge pump output current to zero. In this
mode, VBYPX will be held constant subject to leakage
currents only.
10-6
SSI33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
ROO OUTPUT PIN
PROGRAMMABLE FILTER CIRCUIT
DESCRIPTION
A CMOS compatible, 6 ns wide (min), Raw Data Output
(ROO) signal is provided. This pin will be held low when
either RG is high or WG is low to reduce noise and
accompanying jitter during Read or Write modes. This
pin is also controlled by CBR bit 2 (ROllO register bit).
When CBR bit 2 goes high, ROO will be held High-Z.
The SSI 33P3733A programmable filter consists of an
electronically controlled low-pass filter with a separate
differentiated low-pass output. Aseven-pole,low-pass
filter is provided along with a single-pole, single-zero
differentiator. Both outputs have matched delays. The
delay matching is unaffected by any amount of
programmed equalization orbandwidth. Programmable
bandwidth and boost/equalization is provided by internal
7-bit control OACs. The programmable characteristics
are automatically switched during Emboss mode to
improve signal to noise ratio. Differentiation pulse
slimming equalization is accomplished by a two-pole,
low-pass with a two-pole, high-pass feed forward section
to provide complimentary real axis zeros. A variable
attenuator is used to program the zero locations.
RDIINPUT PIN
A TTL compatible pin read data input (ROI) is provided
as a read data input to the data synchronizer from an
external qualification circuit. ROI is available when
CBR bit 2 (ROllO register bit) goes high.
HYSTERESIS COMPARATOR QUALIFICATION
The SSI 33P3733A provides a hysteresis comparator
pulse qualification circuit for Pit Mark detection. This
circuit uses only the differentiated signal forqualification.
The differentiated Signal is connected to both the
hysteresis and zero cross comparators. A positive
peak that clears the established threshold level will set
the hystereSiS comparator. A peak of the opposite
polarity must clear the negative threshold level to reset
the hysteresis comparator. A positive edge of the
hysteresis comparator output sets the O-Flip-Flop
high. This in turn feeds into the O-input of the second
O-Flip-Flop which is triggered by the negative edge of
the zero cross comparator output. This output triggers
the one-shot. Timing for the hysteresis comparator is
shown in Figure 2.
The filter implements a 0.05 degree equiripple linear
phase response. The normalized transfer functions
(i.e., Wc = 2 mc = 1) are:
VnormNi = [(-Ks2 + 17.98016)/0(s)] x AN
and
a
VdiffNi = (VnormNi) x (slO.86133) x AD
where 0 (s)=
(S2 + 1.68495s + 1.31703)(S2 + 1.54203s +
2.95139)(S2 + 1 .14558s + 5.37034)(s + 0.86133),
AN and AD are adjusted for a gain of 2 at fs = (213)fc.
DP/DN
II
CP/CN
DATA
CLOCK
ONESHOT
FIGURE 2: Hysteresis Comparator Timing Diagram
10-7
-SS133P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
BOOST/EQUALIZATION CONTROL
FUNCTIONAL DESCRIPTION (continued)
The programmable equalization is also controlled by
an internal DAC. The 7-bit Filter Boost Control Register
(FBCR) determines the amount of equalization that'
will be added to the 3 dB cutoff frequency, as follOWS:
FILTER OPERATION
AC coupled differential signals from the AGC are
applied to the FIP/FIN inputs of the filter. To improve
settling time of the coupling capacitors, the FIP/FIN
inputs are placed into a Low-Z state when the LOW Z
pin is brought low. The programmable bandwidth and
boost/equalization features are controlled by internal
DACs afld the registers programmed through the serial
port. The current reference for both DACs is set using
a single 12.1 ill external resistor connected from pin
RX to ground. The voltage at pin RX is proportional to
absolute temperature (PTAT) , hence the current for
the DACs is a PTAT reference current.
Boost = 20 log [(0.0273 x FBCR) + 1J (dB)
For example, with the DAC set for maximum output
(FBCR= 7fH or 127)therewill be 13dBof boost added
at the 3 dB frequency. This will result in +10 dB of
signal boost above the 0 dB baseline. When MOEG is
active the boost can be disabled by setting bit 7 in
Control A register (CAR). When bit 7 is "0" and MOEG
is active the boost will automatically be set to 0 dB. If
bit 7 is "1" the boost will remain at its programmed
value regardless of the state of MOEG.
BANDWIDTH CONTROL
The programmable bandwidth is set by the filter cutoff
DAC. This DAC has two separate 7-bit registers that
can program the DAC value as follows:
TIME BASE GENERATOR CIRCUIT DESCRIPTION
The time base generator, which is a PLL based circuit,
provides a programmable frequency reference for
constant density recording applications. Thefrequency
can be programmed with an accuracy better than 1%.
An external paSSive loop filter is required to control the
PLL locking characteristics. The filter is fully-differential
and balanced in order to suppress common mode
noise generated, for example, from the data
synchronizer's PLL.
Ic = 0.09449 x DACF (MHz)
where DACF = MODMCR or EMCR value
In the MO Data mode, the MO Data Mode Cutoff
Register (MODMCR) is used to determine the filter's
3 dB cutoff frequency. In the Emboss mode, the Emboss
Mode Cutoff Register (EMCR) is used. Switching ofthe
registers is controlled by the MO/emboss gate (MOEG)
pin. The filter cutoff set by the internal DAC is the
unboosted 3 dB frequency. When boost/equalization is
added, the actual 3 dB point will move out. Table 1
provides information on boost verses 3 dB frequency.
In Read, Write and Idle modes, the time base generator
is programmed to provide a stable reference frequency
for the data synchronizer. In Read mode the internal
reference clock is disabled after the data synchronizer
has achieved lock and switched overto read MO data
as the source for the RRC. This minimizes jitter in the
data synchronizer PLL. The reference frequency is
programmed using the M and N registers of the time
base generator via the serial port, and is related to the
external reference clock input, FREF, as follows:
TABLE 1: 3 dB cutoff frequency versus boost
magnitude.
BOOST
(dB)
Ic
(3 dB)
BOOST
(dB)
Ic
(3 dB)
0
1.00
7
2.42
8
2.51
1
1.21
2
1.50
9
2.59
3
1.80
10
2.66
4
2.04
11
2.73
5
2.20
12
2.80
6
2.32
13
2.86
Reference Frequency = «M+1)/(N+1))FREF
10-8
SSI33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
The data synchronizer also requires an external passive
loop filter to control its PLL locking characteristics. The
filter is again fully-clifferential and balanced in order to
suppress common mode noise which may be generated
from the time base generator's PLL.
TIME BASE GENERATOR
CIRCUIT DESCRIPTION (continued)
The VCO center frequency and the phase detector
gain of the time base generator are controlled by an
internal OAC addressed through the MO data recovery
control register (MOORCR). This OAC also sets the
1/3 cell delay for (1,7) code or 1/4 cell delay for (2,7)
code, VCO center frequency, and phase detector gain
for the data synchronizer circuitry. When changing
frequencies, the M and N registers must be loaded first,
followed by the MOORCR register. Afrequencychange
is initiated only when the MOORCR register has been
changed.
MODE CONTROL
The read gate (RG) and write gate (WG) inputs control
the Device Operating mode. RG is an asynchronous
input and may be initiated or terminated at any position
on the disk. WG is also an asynchronous input, but
should not be terminated prior to the last output write
MO data pulse.
Fvco = [12.5/(RR + 0.4)]
x [(0.622 x IOAC) + 4.27) MHz;
for Fvco < 24 MHz
READ MODE
The data synchronizer utilizes a fully integrated fast
acquisition PLL to accurately develop the decode
window. Read gate (RG) initiates the PLL locking
sequence and selects the PLL reference input; a high
level (Read mode) selects the internal RO input and a
low level selects the reference clock. In the Read mode
the falling edge of ORO enables the phase detector
while the rising edge is phase compared to the rising
edge of the VCO reference (VCOR). ORO is a 1/3 (for
(1,7) code or 1/4 for (2,7) code) cell wide (TVCO) pulse
whose leading edge is defined by the falling edge of
RD. A decode window is developed from the VCOR
clock.
Fvco = [12.5/(RR + 0.4)]
x [(0.7 x IOAC) + 1.4) MHz
Where IDAC is the value in the MOORCR and RR is the
value (kil) of the external RR resistor.
DATA SYNCHRONIZER CIRCUIT DESCRIPTION
In the Read mode, the data synchronizer performs
sync field search and data synchronization. Inthe Write
mode, the circuit provides write precompensation. Data
rate is established by the time base generator and the
internal reference DACI controlled by the MODRCR.
The DAC generates a reference current which sets the
VCO center frequency, the phase detector gain, and
the 1/3 or 1/4 cell delay.
PREAMBLE SEARCH
When RG is asserted, an internal counter is triggered
to count positive transitions of the incoming read MO
data, RD. Once the counter reaches a count of 3, the
internal read gate is enabled. This switches the phase
detector reference from the internal time base to the
delayed read data (ORO) signal. At the same time an
internal zero phase restart signal restarts the VCO in
phase with the ORO. This prepares the VCO to be
synchronized to MO data when the bit sync circuitry is
enabled after VCO lock is established.
PHASE LOCKED LOOP
The circuit employs a Dual mode phase detector;
harmonic in the Read mode and non-harmonic in the
Write and Idle modes. In the Read mode the harmonic
phase detector updates the PLL with each occurrence
of a ORO pulse. In the Write and Idle modes the nonharmonic phase detector is continuously enabled, thus
maintaining both phase and frequency lock onto the
reference frequency of the internal time base generator.
By acquiring both phase and frequency lock to the input
reference frequency aroJ utilizing a zero phase restart
technique, the VCO transient is minimized and false
lock to DLYD DATA is eliminated. The phase detector
incorporates a charge pump in order to drive the loop
filter directly. The polarity and width of the output
current pulses correspond to the direction and
magnitude of the phase error.
10-9
II
I
SSI 33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
FUNCTIONAL DESCRIPTION (continued)
WRITE MODE
VCO LOCK AND BIT SYNC ENABLE
Write mode is entered by asserting the write gate (WG)
while the RG is held low. During Write mode the VCO
and the RRC are referenced to the intemal time base
generator signal.
One of two VCO locking modes will be entered
depending on the state of the gain shift (GS) bit, or bit
1, in the Control B register. If GS = "1,· the phase
detector will enter a Gain Shift mode of operation. The
phase detector starts out in a High Gain mode of
operation to support fast phase acquisition. After an
internal counter counts the first 11 transitions of the
internal ORO Signal, the gain is reduced by a factor of
3. This reduces the bandwidth and dampening factor of
the loop by v3 which provides improved jitter
performance in the MO data follow mode. The counter
continues to count the next 5 ORO transitions (a total of
19 pulses from assertion of RG) and then asserts an
internal VCO lock signal.
When the VCO lock signal is asserted, the internal
RRC source is also switched from the time base
generator to the VCO clock signal that is phase locked
to ORO. During the internal RRC switching period the
external RRC signal may be held for a maximum of 2
VCO clock periods, however no short duration glitches
will occur.
OPERATING MODES AND CONTROL
The SSI33P3733A has several operating modes that
support Read, Write, Emboss, and power management
functions. Mode selection is accomplished by controlling
the read gate (RG), write gate (WG), MO/emboss gate
(MOEG), and PWRON pins. Additional modes are also
controlled by programming the Power Down Control
Register (PDCR), the Control A register (CAR), and the
Control B register (CBR) via the serial port.
EXTERNAL MODE CONTROL
When the GS bit is set to "0· the phase detector gain
shift function is disabled. The VCO lock sequence is
identical to that of the Gain Shift mode explained
above, except that no gain shift is made after the first
11 transitions.
All operating modes of the device are controlled by
driving the read gate (RG), write gate (WG), MO/emboss
gate (MOEG), and PWRON pins with TTL compatible
signals. For normal operation the PWRON pin is driven
low. During normal operation the SSI 33P3733A is
controlled by the read gate (RG), write gate (WG), and
MO/emboss gate (MOEG) pins. When RG is high and
WGis high the device is in Read mode. When WG is low
and RG is low the device is in Write mode. If the RG is
low and WG is high the device will be in Idle mode.
During the Idle mode, the MOEG pin can be activated to
enable the Emboss mode of operation.
WINDOW SHIFT
POWER DOWN CONTROL
Shifting the phase of the VCO clock effectively shifts
the relative position olthe ORO pulse within the decode
window. Decode window control is provided via the WS
control bits of the Window Shift Control Register
(WSCR). Further description of the WSCR is provided
in the window shift control section.
For power management, the PWRON pin can be used
in conjunction with the Power Down Control Register
(PDCR) to set the Operating mode of the device. The
PDCR provides a control bit for each of the functional
blocks. When the PWRON pin is brought high ("1") the
device is placed into Sleep mode «5 mW) and all
circuits are powered down except the serial port. This
allows the user to program the serial port registers
while still conserving power. Register information is
retained during the Sleep mode so it is not necessary
to reprogram the serial port registers after returning to
an Active mode. When the PWRON pin is driven low
("0"), the contents olthe PDCR determine which blocks
will be active. Register mapping for the PDCR is shown
in Table 3. To improve recovery time from the Sleep
mode, the LOW_Z pin should be asserted following
power down to initiate the AGC recovery sequence.
NON-READ MODE
In the Non-Read modes, the PLL is locked to the
reference clock. This forces the VCO to run at a
frequency which is very close to that required for
tracking actual MO data. When the reference input to
the PLL is switched, the VCO is stopped momentarily,
then restarted in an accurate phase alignment with the
next PLL reference input pulse. By minimizing the
phase alignment error in this manner, the acquisition
time is substantially reduced.
10-10
SSI33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
SERIAL INTERFACE OPERATION
The serial interface is a CMOS bi-directional port for
reading and writing prog ram ming data from/to the internal
registers of the SSI 33P3733A. The serial port data
transfer format is shown in Figure 3. For data transfers
SDEN is brought high, serial data is presented at the
SDATA pin, and a serial clock is applied to the SCLK pin.
After the SDEN goes high, the first 16 pulses applied to
the SCLK pin will shift the data presented at the SDATA
pin into an internal shift register on the rising edge of
each clock. An internal counter prevents more than 16
bits from being shifted into the register. The data in the
shift register is latched when SDEN goes low. If less
than 16 clock pulses are provided before SDEN goes
low, the data transfer is aborted.
All transfers are shifted into the serial port LSB first. The
first byte of the transfer is address and instruction
information. The LSB of this byte is the RIW bit which
determines ifthe transfer is a read (1) or a write (0). The
remaining 7-bits determine the internal register to be
accessed. Table 3 provides register mapping information.
The second byte contains the programming data. In
Read mode (RlW=1) the SSI 33P3733A will output the
register contents of the selected address. In Write mode
the device will load the selected register with data
presented on the SDATA pin. At initial power-up, the
contents of the internal registers will be in an unknown
state and must be programmed prior to operation.
During power down modes, the serial port remains
active and register programming data is retained.
Detailed timing information is provided in Figure 4.
II
10-11
SSI 33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
S~
SDATA
SCLK
L
<'---_----J>-<'---_----Jr-~ATA, 8-BIT
ADDRESS,8-BIT
"---
FIGURE 3: Serial Port Data Transfer Format
TABLE 2: MODE CONTROL
CONTROL
LINE
i
DAC
CONTROL
a:
I- w
en
I-
CJ
w
en
enw
0
0
m
~
CJ
a: ::E
0
I~
1
X
X
X
SLEEP MODE: All functions are powered down. The serial
port registers remain active and register programming data is
saved.
0
0
0
0
WRITE MODE: The pulse detector is inactive. The data
MR MRMR MR
synchronizer VCO is locked to the internal time base generator.
0
1
0
1
READ MODE: The pulse detector is active. The data
synchronizer begins the preamble lock sequence. RDIO is
active
MR MRMR MR
0
0
1
1
EMBOSS MODE: The pulse detector is active and the emboss
control registers are enabled for the Fc DAC and the VTH
DAC. The data synchronizer and time base generator can be
disabled using the PDCR.
ER ER off ER
0
0
0
1
IDLE MODE: The contents of the PDCR determine which
blocks are powered-up. In normal operation with all blocks
powered-up, the pulse detector is active, the data synchronizer
VCO is locked to the time base generator, and the MO data
control registers are used for VTH and FC.
MR MRMR MR
All other states are illegal. If an illegal state is programmed,
the chip function will be in an indeterminable state, but no
damage will occur.
MR MRMR MR
- -
- -
I
DEVICE MODE
DAC CONTROL KEY: MR
= MO DATA REGISTER, ER = EMBOSS RIGISTER,
10-12
>
l-
tt.
off
off off off
OFF
I
= DISABLED
REGISTER NAME
ADDRESS
co
c(
~~
~
DO
DATASEP
FILTER
lBG
1=DISABLE 1=DISABLE 1=DISABLE
O:ENABLE O=ENABLE O:ENABLE
--
PD
1=DISABLE
O:ENABLE
FcuDAC
BIT2
FcuDAC
BIT 1
FcuDAC
BITO
FeE DAC
BIT3
FeeDAC
BIT 2
Fee DAC
BIT 1
FeeDAC
BIT 0
FaDAC
BIT 4
FaDAC
BIT3
FaDAC
BIT 2
FaDAC
BIT 1
FaDAC
BITO
TMDAC
BITS
TMDAC
BIT4
TMDAC
BIT 3
TMDAC
BIT2
TMDAC
BIT1 .
TIIDAC
BITO
TEDAC
BITS
TEDAC
BIT 4
TEDAC
BIT3
TEDAC
BIT 2
TEDAC
BIT 1
TEDAC
BIT 0
0
--
--
--
o
0 1 1 0
--
FcuDAC
BIT6
FcuDAC
BITS
FCMDAC
BIT 4
FcuDAC
BIT3
o
0 1 1 0
--
Fee DAC
BIT 6
Fee DAC
BITS
FeeDAC
BI14
1=ENABLE
O:DISABLE
FaDAC
BIT 6
FaDAC
BITS
0 1 0 1 0 0
1=DUAL
O:HYS
TMDAC
BIT6
EMBOSS THRESHOLD
0 0 1 0 0 1 0 0
1=DUAL
O:HYS
TEDAC
BIT 6
CONTROL A
o
CONTROL B
0 0 0 1 1 0 0 0
--
NCOUNTER
0 0 0 0 1 1 0 0
--
NCOUNT
BIT6
NCOUNT
BITS
NCOUNT
BI14
NCOUNT
BIT 3
NCOUNT
BIT 2
NCOUNT
BIT 1
NCOUNT
BITO
MCOUNTER
0
MCOUNT
BIT7
MCOUNT
BIT6
MCOUNT
BIT 5
MCOUNT
BIT4
MCOUNT
BIT 3
MCOUNT
BIT 2
MCOUNT
BIT1
MCOUNT
BIT 0
DATA RECOVERY
0 0 0 0 1 0 0 0
--
DACI
BIT 6
DACI
BITS
DACI
BI14
DACI
BIT 3
DACI
BIT 2
DACI
BIT 1
DACI
BITO
WINDOW SHIFT
o
TDAC1
TDACO
WINSHFT
1=ENABLE
O=DISABLE
WSDIR
1=LATE
O:EARLY
WS3
WS2
WSf
W§f
AGCLEVEL
0 1 0 0 0 1 0 0
--
--
--
--
AGCDAC
BIT3
AGCDAC
BIT 2
AGCDAC
BIT 1
AGCDAC
BITO
HYSTERESIS DECAY
0 1 0 1 0 1 0 0
EMBOSS
BIT3
EMBOSS
BIT2
EMBOSS
BIT 1
EMBOSS
BIT 0
DATA
BIT 3
DATA
BIT2
DATA
BIT 1
DATA
BITO
POWER DOWN CONTROL
o
0
o
0 0 1
o
MO DATA MODE CUTOFF
0
o
0
EMBOSS MODE CUTOFF
0 0 1
FILTER BOOST
0 0 0 1 0 1 1 0
MO DATA THRESHOLD
0
EMBOSS BOOST
CAl
DATA BITMAP
D7
o
Fast Decay
0 1 1 0 1 0 0
o
0 1 1 1 0 0
test mode
O:ENABLE
lBGTEST PUMPDWN PUMP UP PHASE DET
lBG
POINT
1=ENABLE
1=BYPASS
1=TPON
1=TP ON
ENABLE
O:NORMAL
O:TPOFF
O:TPOFF O=DISABLE
IIDIIO
PUMPDWN PUMP UP PHASE DET 1=RDlIJrIIUT GAINSHFT
MTPE
1=TPON
1=ENABLE
1 =ON
1=ENABLE
1=TPON
O:TPOFF O=DISABLE o=HOI DISABLE
O=OFF
O:DISABLE O=TPOFF
TMS1
TMSO
--
-"""""
Q)
0 0 0 1 0 1 0
'---
:eN
-en
-... "'0'
_.(J1
s::S::
m2:
~cn
"'0:0(1)
5.(1)(1)
cnm-
TABLE 3: Serial Port Register Mapping
•
(l)a.w
OO~
c::::rw
I»m .......
=::;'w
:::!:::;,w
(1)(1)>
... -
SSI33P3733A
8-26.5 Mbitls Read Channel
w/Pit Mark Pulse Qualifier
FUNCTIONAL DESCRIPTION (continued)
CONTROL REGISTERS
Control registers CAR and CBR allow the userto configure the SSI33P3733A test points for evaluation of different
internal signals and also control other device functions. CAR controls functions of the pulse detector, filter, and
time base generator. CBR controls test pOints and functions of the data separator. The bits of the CA and CB
registers are defined as follows:
CONTROL REGISTER CA
BIT
NAME
FUNCTION
0
EPDT
Enable Phase Detector (Time Base Generator)
1
UT
Pump Up (TFlTR sources current, TFlTR sinks Current)
2
DT
Pump Down (TFlTR sinks current, TFLTR sources Current)
3
ET
4
BYPT
Bypass Time Base Generator Circuit Function
5
TMSO
Control bit for selecting test point source (see Table 4)
6
TMS1
Control bit for selecting test point source (see Table 4)
7
FDTM
Constant fast decay current test mode
Enable Time Base Generator Test Point Output
CONTROL REGISTER CB
-
0
1
2
GS
ROllO
Not Used
Enable Phase Detector Gain Switching
RDI and ROO pins control
3
EPDD
Enable Phase Detector (Data Separator)
4
UD
Pump Up (DFlTR sources current, DFlTR sinks current)
5
DO
Pump Down (DFlTR sinks current, DFlTR sources current)
6
MTPE
7
-
Enable Test Points MTP1, 2, 3 (see Table 4)
Not used
10-14
SSI33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
PIN DESCRIPTION
POWER SUPPLY PINS
NAME
TYPE
VPD, VPD2
-
VPG
-
VNA
-
VPA
VPB
VPC
VNB
VNC
VND, VND2
VNG
DESCRIPTION
Data separator Pll analog power supply pin
Time base generator Pll analog power supply pin
Internal ECl, CMOS logic power supply pin
CMOS buffer 1/0 digital power supply pin
Pulse detector, filter, analog power supply pin
Data separator Pll analog ground pin
Time base generator Pll analog ground pin
Internal ECl, CMOS logic ground pin
CMOS buffer 1/0 digital ground pin
Pulse detector, filter, analog ground pin
INPUT PINS
AIP,AIN
I
AGC AMPLIFIER INPUTS: Differential AGC amplifier input pins.
DP,DN
I
ANALOG INPUTS FOR MO DATA PATH: Differential analog inputs to fullwave rectifier. These inputs do not have the internal DC bias.
CP,CN
I
ANALOG INPUTS FOR CLOCK PATH: Differential analog inputs to the clock
comparator, and data comparators. (connect CP to DP, CN to DN externally)
lOW_Z
I
lOW IMPEDANCE ENABLE: TTL compatible input pin that activates the lowZ switches. A low level activates the switches and the falling edge of the
internal lOW_Z triggers the fast decay circuit.
PWRON
I
POWER ENABLE: TTL compatible power control input. A low level input
enables power to circuitry according to the contents of the PDCR. A high level
input shuts down all circuitry.
HOLD
I
HOLD CONTROL: TTL compatible control pin which, when pulled high,
disables the AGC charge pump and holds the AGC amplifier gain at its present
value.
FIP, FIN
I
FilTER SIGNAL INPUTS: The AGC output signals must be AC coupled into
these pins.
FREF
I
REFERENCE FREQUENCY INPUT: Frequency reference input for the time
base generator. FREF may be driven either by a direct coupled TTL signal or
by an AC coupled ECl signal. Pin FREF has an internal pull down resistor.
RDI
I
READ DATA INPUT: TTL compatible input. RDI is provided as a read data
input to the data synchronizer from an external qualification circuit. RDI is
available when CBR bit 2 goes high.
10-15
II
SSI 33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
INPUT PINS
(continued)
NAME
TYPE
DESCRIPTION
RG
I
READ GATE: TIL compatible read gate input. A high level TIL input selects
the RD input and enables the Read mode/address detect sequences. A low
level selects the FREF input.
MOEG
I
MO/emboss GATE: TTL compatible MO/emboss gate input. A high level TIL
input activates the Emboss mode by selecting the emboss control registers,
the RTS resistor, and the BYPE capacitor.
WG
I
WRITE GATE: TTL compatible write gate input. A low level TIL input enables
the Write mode.
MTP1-3
0
MULTIPLEXED TEST POINTS: Open emitter ECL outputtest pOints. Internal
test signals are routed to these test points as determined by the CAR and CBR.
External resistors are required to use these pins. They should be removed
during normal operation to reduce power dissipation.
SDO
0
SYNCHRONIZED READ DATA: CMOS output pin. Read MO data output
when RG is high.
FOP, FDN
0
DIFFERENTIAL DIFFERENTIATED OUTPUTS: Filter differentiated outputs.
These outputs are AC coupled into the CP/CN inputs.
FNP, FNN
0
DIFFERENTIAL NORMAL OUTPUTS: Fitter normal low pass output signals.
These outputs are AC coupled into the DP/DN inputs.
ROO
0
RAW DATA OUTPUT: CMOS output pin. The rising edge of ROO indicatesthe
presence of a valid MO data pulse. ROO is low when either RG is high orWG
is low. When CBR bit 2 goes high, ROO will be held High-Z.
RRC
0
READ REFERENCE CLOCK: Read clock CMOS output. During a mode change,
no glitches are generated and no more than one lost clock pulse will occur. When
RG goes high, RRC initially remains synchronized to the reference clock. When
the Sync Bits are detected, RRC is synchronized to the Read MO Data. When RG
goes low, RRC is synchronized back to the reference clock.
AOP,AON
0
AGC AMPLIFIER OUTPUT: Differential AGC amplifier output pins. These
outputs are AC coupled into the fitter inputs (FIP/FIN).
FOUT
0
TIME BASE GENERATOR VCO OUTPUT: CMOS output pin. This clock signal is the
data separator PLL reference. This output is independent of the RGIWG pin.
PPOL
0
PULSE POLARITY: Pulse polarity CMOS output pin. The output is high when
the pulse being qualified is positive and it is low when the pulse being qualified
is negative.
OUTPUT PINS
10-16
SSI33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
ANALOG PINS
NAME
TYPE
DESCRIPTION
BYPMO
-
The AGC Read mode integration capacitor CBYPMO, is connected between
BYPMO and VPG.
BYPE
-
The AGC Emboss mode integration capacitor CBYPE, is connected between
BYPE and VPG.
DACOUT
-
DAC VOLTAGE TEST POINT: This test point monitors the outputs of the
internal DACs. The source DAC is selected by programming the two MSBs of
the WSCR register (see Table 5).
TFLT,TFLT
-
PLL LOOP FILTER: These pins are the connection points for the time base
generator loop fiHer.
DFLT, DFLT
-
PLL LOOP FILTER: These pins are the connection points for the data
separator loop filter.
LEVEL
-
An NPN emitter output that provides a full-wave rectified signal from the DP,
DN inputs. An external capacitor should be connected from LEVEL to VPG to
set the hysteresis threshold time constant in conjunction with the internal
current DAC, (DACA).
RR
-
REFERENCE RESISTOR INPUT: An external 12.1 kil, 1% resistor is connected from this pin to VNA to establish a precise internal reference current for
the data separator and time base generator.
RX
-
REFERENCE RESISTOR INPUT: An exlernal12.1 kn, 1% resistor is connected from this pin to ground to establish a precise PTAT (proportional to
absolute temperature) reference current for the filter.
SDEN
-
SERIAL DATA ENABLE: Serial enable CMOS input. A high level TTL input
enables the serial port.
SDATA
-
SERIAL DATA: Serial data CMOS input. NRZ programming data for the
internal registers is applied to this input.
SCLK
-
SERIAL CLOCK: Serial clock CMOS input. The clock applied to this pin is
synchronized with the data applied to SDATA.
SERIAL PORT PINS
II
10-17
SSI 33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, the recommended operating conditions are as follows: 4.5V < POSITIVE
SUPPLY VOLTAGE < 5.5V, DoC < T (ambient) < 70°C, and 25°C < T(junction) < 135°C. Currents flowing into
the chip are positive. Current maximum are currents with the highest absolute value.
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER
RATING
Storage Temperature
-65 to 150°C
Junction Operating Temperature
+135°C
Positive Supply Voltage (Vp)
-0.5 to 7V
Voltage Applied to Logic Inputs
-0.5V to Vp + 0.5V
All other Pins
-0.5V to Vp + 0.5V
POWER SUPPLY CURRENT AND POWER DISSIPATION
PARAMETER
CONDITIONS
ICC (VPA,B,C,D,G)
Outputs and test point pins
open, Ta = 27°C,
VPn = 5V, 24 Mbitls
75
mA
PWR
Power Dissipation
Outputs and test point pins
open, Ta = 27°C,
VP = 5V, 24 Mbil/s
375
mW
MIN
Sleep mode Power
PWRON = 1
Emboss mode Power
PWRON = 0
TBG Disabled
Data Sep. Disabled
NOM
MAX
5
UNIT
mW
mW
200
DIGITAL INPUTS AND OUTPUTS
TTL Compatible Inputs
Input low voHage
VIL
Input high voltage
VIH
-0.3
0.8
V
2
VPD +0.3
V
Input low current
ilL
VIL = O.4V
-100
Input high current
IIH
VIH = 2.4V
50
ItA
ItA
CMOS Compatible Inputs· Schmitt trigger type (not to be left open.) Nominall.0V hysteresis around VPD12.
Input low voltage
-0.3
1.5
V
Input high voltage
3.5
VPD +0.3
V
10-18
551 33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
CMOS Compatible Outputs
Output low voltage
5V,25°C
IOL = 4.07 mA
Output high voltage
5V,25°C
IOH = -4.83 mA
Rise time
4.5V, 70°C, C = 15 pF
8
ns
FaUtime
4.5V, 70°C, C = 15 pF
8
ns
0.5
V
V
4.5
PSEUDO ECl OUTPUT LEVELS (MTP1, MTP2, MTP3)
For all tests, 26H1 to VPA and 402Q to VNA with VPA = 5.0V
Output high level
V
VPA
-1.02
Output low level
VPA
-1.62
V
SERIAL PORT
SCLK period
TCLK
100
ns
SCLK low time
TCKL
40
ns
SCLK high time
TCKH
40
ns
Enable to SCLK
TSENS
35
ns
SCLK to disable
TSENH
35
ns
Data set-up time
Tos
15
ns
Data hold time
TOH
15
ns
SDATA tri-state delay
SDATA turnaround time
SDEN low time
TSENOL
50
ns
TTRN
70
ns
TSL
200
ns
II
10-19
SSI 33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
SDEN
1(
~
L
TSENS
TTRN
SClK
TDSH
SDATA
(READ)
"---1
SDATA \
(WRITEJ _ _
ANI
RMI
\
L
ADDRO
ADDR6
ADDRO
00
00
FIGURE 4: Serial Port Timing Information
10-20
DATA 7
DATA 7
)-
}-
SSI33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
ELECTRICAL SPECIFICATIONS (continued)
PULSE DETECTOR CHARACTERISTICS
AGC Amplifier
Input signals are AC coupled to AIP/AIN, AOP/AON outputs are AC coupled to FIP/FIN, and FDPIFDN are AC coupled
to CP/CN. CP/CN and DP/DN are connected to each other. 1000 pF capacitors are connected from BYPMO to VPG
(CBYPMO) and from BYPE to VPG (CBYPE). Unless otherwise specified, outputs are measured differentially at AOP/AON,
FIN = 8 MHz, and filter boost = 0 dB.
PARAMETER
CONDITIONS
Input range
Filter boost 0 to 13 dB
20
DP-DN voltage
AlP - AIN = 0.1 Vpp
0.9
MOEG = high, AGC DAC = 0
0.9
MOEG = high, AGC DAC = 15
0.68
DP-DN voltage variation
MIN
UNIT
190
mVpp
1
1.1
Vpp
1
1.1
Vpp
0.76
0.84
Vpp
8
%
20 mV < AlP - AIN < 190 mV
Gain range
18
0.45
Gain sensitivity
BYPx voltage change
AOP-AON dynamic range
THO = 1%
0.6
Differential input impedance
LOW_Z= high
4.7
VN
dBN
28
Vpp
6
8.4
kQ
350
Q
LOW_Z= high
3.3
kQ
LOW_Z= low
250
Q
LOW_Z= low
Single-ended input impedance
MAX
NOM
Single-ended output impedance
AOP/AON to ground
120
Q
Output offset voltage variation
Gain = 0.45 to 18
200
mV
Input noise voltage
Gain = 18, AOP - AON = OV
Bandwidth
Gain = 18, CL ~ 15 pF
20
nV/.,JHz
35
MHz
CMRR
Gain = 18, Ic = 5 MHz
40
dB
PSRR
Gain = 18, Ic = 5 MHz
45
dB
Gain decay time
AlP - AIN = 250 to 125 mY,
AOP - AON > 0.9 Final Value
36
J.lS
Gain attack time
AlP - AIN = 125 to 250 mY,
AOP - AON < 1.1 Final Value
0.65
J.lS
AGCControl
The input signals are AC coupled into DN/DP, CBYPX = 1000 pF to VPG, MOEG
DP-DN input range
For test only
Decay current
Normal decay
Attack current
= low.
1
1.5
Vpp
10
4
Fast Decay mode
10F
21 x 10
I1A
I1A
Normal attack
ICH
0.18
mA
ICHF
8 x ICH
mA
Fast Attack mode
10-21
II
551 33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
AGC Control (continued)
PARAMETER
CONDITIONS
MIN
BYPMO leakage current
WG = high
-10
LEVEL output gain
IDP-DNI = 0.5 to 1.5V
0.60
LEVEL output bandwidth
-1 dB
LEVEL pin pull-down current
DACL = 0000
MAX
UNIT
10
nA
0.65
0.70
VNpp
1.56
3.125
4.69
47
50
53
JJA
JJA
1
1.5
Vpp
Fast decay duration
NOM
1
j.LS
MHz
10
DACL = 1111 where ILEVEL =
3.125 x (1 + DACL) JJA
Data Comparator
The input signals are AC coupled into DP/DN.
DP-DN input range
Differential input resistance
MO
1
Differential input capacitance
5
Threshold voHage hysteresis
10
pF
%T
Threshold voHage gain
(KTH) tolerance
0.47 < lOP - DNI < 1.19
T = VTHDAC x 0.93/127
38 < VTHDAC < 127
Minimum threshold voHage
lOP - DNI < 0.16
VTHMIN = VTHDAC ·97.6%/127
PPOL rise time
10% to 90% points, CL ~ 15 pF
8
ns
PPOL fall time
90% to 10% points, CL ~ 15 pF
8
ns
1.5
Vpp
T + 10
T - 10
%
V
VTHMIN
Clock Section
The input signals are AC coupled into CP/CN.
CP-CN input range
Comparator offset voHage
Differential input resistance
-4
4
mV
LOW_Z = Off
2.5
7.5
kO
LOW_Z=On
0.6
1.6
kQ
5
pF
0.5
ns
15
ns
Differential input capacitance
Pulse pairing
DP/DN = 1 Vpp sine,
CP/CN = 1 Vpp - 900sine
Fsine = 8 MHz
ROO pulse width
CL $15 pF
6
RDI input pulse width
ns
10
ROO rise time
10% to 90% points, CL $15 pF
8
ns
ROO fall time
90% to 10% points, CL $ 15 pF
8
ns
10-22
SSI33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
Programmable Filter Characteristics
PARAMETER
CONDITIONS
Filter cutoff range
fc @ -3 dB point
Ic = (0.09449 MHz) x DACF,
MIN
NOM
4
MAX
UNIT
12
MHz
%
Boost = 0 dB
42::; DACF::; 127
DACF = MODMCR
Filter cutoff accuracy
DACF
DACF
FNP, FNN differential gain (AN)
FDP, FDN differential gain (Ao)
Frequency boost @
fc = 12 MHz
Boost accuracy
= 127
= 42 to
F = 0.67 x
fc,
F = 0.67 x fc,
DACS
-10
10
DACF < 127
-15
15
%
boost = 0 dB
1.6
2.4
VN
1.2 AN
VN
boost
= 0 dB
FNP, FNN; FOP, FDN
Filter output THD @ 1 vpp
Filter differential input resistance
O.SAN
= 127
= 37
@ 9 dB, DACS = 67
@ 13 db, DACS = 127
fc = 4 to 12 MHz
F = 0.2 Ic to fc, Boost = 0 and 3dB
fc = 4 to 12 MHz
F = fC to 1.75 fc, Boost=3dB
F = 0.67 fc
Ic = 4 to 12 MHz
Normal
-1
+1
dB
-1.25
+1.25
dB
-1.5
+1.5
dB
-2
+2
%
-3
+3
%
1.5
0/0
kn
3
Low-Z
140
Filter differential input capacitance
Output noise voltage
differentiated output
differentiated output
normal output
normal output
= 100 MHz, Rs = 50Q
= 12 MHz, boost = 0 dB
= 12 MHz, boost = 13 dB
= 12 MHz, boost = 0 dB
= 12 MHz, boost = 13 dB
pF
BW
fc
fc
Ic
fc
2.6
mVRms
5.6
mVRms
2
mVRms
3.6
mVRms
mA
0.5
Filter output offset voltage
Rx resistance
n
7
Filter output sink current
Filter output source current
Filter output resistance
Rx pin voltage
dB
13
@ 6 dB, DACS
MO/Emboss mode group delay
variation
2
200
2
single ended
Ta = 2rC
Tj = 127°C
200
600
SOO
1% fixed value
12.1
10-23
mV
mA
n
mV
mV
kQ
a
551 33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
PULSE DETECTOR CHARACTERISTICS (continu~)
Time Base Generator Characteristics
PARAMETER
MIN
MAX
UNIT
8
20
MHz
75
MHz
-TBD
goal
= 200
+TBD
goal
= 200
ps
(rms)
M counter range
2
255
N counter range
2
127
0.85 TO
1.15 TO
ns
CONDITIONS
FREF input range
NOM
FOUT frequency range
FOUT jitter
TOUT = 1/FOUT
Loop acquisition time
= 30 IlS
VCO center frequency period
(TVCO)
Fvco = [12.5/(RR + 0.4)]
x [(0.622 x IDAC)+ 4.27] MHz
TFLT - TFLT = TBD
Fvco< 24 MHz
Fvco = [12.S/(RR + 0.4)] x [(0.7 x
IDAC) + 1.4] MHz
VCO dynamic range
-2V ~TFLT - TFLT ~+2V
FOUT= 36 MHz
RR = 12.1 kQ
±25
±45
%
VCO control gain
KVCO
c.oi = 21t1TVCO
-2V ~ TFLT - TFLT ~ +2V
0.12 c.oi
0.24c.oi
rad/(V-S)
Phase detector gain
KD
KD = [12.5/(RR+0.4)J x (0.656
x IDAC + 3.38) x 10.6
0.83 KD
1.17 KD
Alrad
KVCO x KD product accuracy
-28
RR resistor range
+28
FREF input low time
20
FREF input high time
20
%
kQ
12.1
ns
ns
FOUT rise time
10% to 90% points. CL!O 20 pF
8
ns
FOUT fall time
90% to 10% points. CL!O 20 pF
8
ns
DATA SYNCHRONIZER CHARACTERISTICS
Read Mode
Read clock rise time
TRRC
10% to 90% points
15 pF
8
ns
CL~
Read clock fall time
TFRC
90% to 10% points
CL ~ 15 pF
8
ns
RRC duty cycle
Except during re-sync
40
60
%
TRD
During re-sync
40
%
10
ns
SDO out set-up and
hold time (TSDS. TSDH)
1/2 code bit cell delay
TO = TVCO/2
0.8 TO
10-24
1.2TO
ns
SSI33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
Data Synchronization
PARAMETER
CONDITIONS
VCO center frequency
period (TVCO)
Fvco =[12.5/(RR + 0.4)]
x [(0.622 x IDAC) + 4.27] MHz
TVCO = 1/FVCO,
DFLT - DFL T =TBD
RR = 12.1 kQ
Fvco < 24 MHz
Fvco = [12.5/(RR + 0.4)) x
[(0.7 x IDAC) + 1.4] MHz
VCO dynamic range
-2V ~ DFLT - DFLT S,+2V
VCO control gain
KVCO
MAX
UNIT
0.85 TO
1.15 TO
ns
±25
±45
%
wi = 21t1TVCO
-2V s, DFLT- DFLT +2V
0.12 wi
0.24 wi
rad/(V-S)
Phase detector gain
KD
Idle mode = 1 x KD
Read mode =3 x KD
Read mode after gain shift =
1 x KD
KD = [12.5/(RR + 0.4)]
x (0.656 x IDAC + 3.38)
x 10.6
0.83 KD
1.17 KD
Alrad
VCO phase restart error
Fvco
-2
+2
ns
-0.75
+0.75
ns
=72 MHz
Decode window center accuracy
Decode window width
MIN
TVCO
- 0.75
NOM
ns
a
10-25
SSI33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
APPLICATIONS INFORMATION
WINDOW SHIFT CONTROL
Window shift magnitude is set by the value in the Window Shift (WS) register. The WS register bits are as
follows:
BIT
NAME
0
WSO
1
WS1
2
WS2
3
WS3
FUNCTION
4
WSD
Window shift direction. O=early, 1=late
5
WSE
Window shift enable
6
TDACO
Used to route signals to DAC test point
7
TDAC1
Used to route signals to DAC test point
The window shift magnitude is set as a percentage of the full decode window, in 2% steps. This results in
a window shift capability of ± 30% of the full decode window. The tolerance of the window shift magnitude
is ± 30%. Window shift should be set during Idle mode or Write mode.
WS3
WS2
WS1
WSO
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
10-26
Shift Magnitude
No shift
2% (minimum shift)
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
24%
26%
28%
30% (maximum shift)
SSI33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
RRC
~---TORC - - - - . - j
SDO
15VTFRC~ 1=
TRRC=:.j
--~tT:si~s:f-~1.5V_FIGURE 5: SDO Read Timing
TABLE 4: Multiplexed Test Point Signal Selection
MTP3
MTPE
TMS1
TMSO
MTP1
MTP2
0
X
X
OFF
OFF
OFF
ORO
DSREF
DOUT
COUT
1
0
0
VCOREF
1
0
1
RD
1
1
0
-
1
1
1
SET
RESET
COUT
Output of the pulse qualifier clock circuit
DOUT
Output of the pulse qualifier data comparators
DSREF
Output of the time base generator
NCTR
RD
Ncounter output of the time base generator
RESET
Output of the negative threshold comparator
SET
Output of the positive threshold comparator
NCTR
COUT
Read MO data output from the pulse qualifier
TABLE 5: DACOUT Test Point Signal Selection
TDAC1
TDACO
DAC MONITORED
0
0
Filter Ic DAC
0
1
Qualifier threshold DAC (VTH)
1
0
Window shift DAC
1
1
Unused
10-27
I
~Q)(I)
_1(1)
WRITE
MODE
READ
MODE
I --- -U---------u
PWRON
RGJ
READ
MODE
TRACK
FOLLOW
U
I
I
I
WG
MOEG
n
n
I
L
I
n
C(l)W
-ll»
CD
en
Q)
Oc.
n
n
n
n
DEVICEn,-------"~r-----~~~-----4.~H-----~~~------m-~------~~------~~------~~
MODEU'______-m~L-~~~~~~~~~m-~~~a=~~~--~~~~~~~~~~~~------~~
-----1---------------,
Z SERIAL
PORT
(X)
When MOEG is HIGH the device will
switch to the VE register for the
threshold DAC and Fc DAC and the
RTS resistor for the LEVEL pin
output.
s:CJ1W
mS:"tJ
W
-,c~-.~
"tJct. W
CD
I
Inl
I I
_. W
::9.~-
Prior to entering the Track Follow mode, the
Power Down Control Register is changed to
disable the Data Separator and Time Base
Generator blocks. Data can be loaded with
PWRON either LOW or HIGH.
NOTES:
_____
1) When the PWRON pin is LOW ("0") the Power
Down Control Register is active. All blocks that have
the~ bit set to "1" will be powered down. When
the PWRON pin is HIGH ("1") the device goes into a sleep
mode with aU blocks powered down except the serial port.
2) When the threshold DAC reference is switched, there is a maximum
settling time of l.5l1sec for the DAC.
FIGURE 6: Power Control Timing
Prior to returning to read mode (or write
)
mode) the Power Down Control Register is
changed to enable the Data Separator and
Time ~nerator blocks. Load data
while PWRON is HIGH.
When RG is low and W?3 is high, the
device will enter an idle state where the
AGC is active and the data synchronizer is
locked to the internal FREF.
CO
e!.::::T
--::s
~ ::s
::::;:Q)
CD
551 33P3733A
8-26.5 Mbit/s Read Channel
w/Pit Mark Pulse Qualifier
PACKAGE PIN DESIGNATIONS
Thermal Characteristics: 9jA
I
(Top View)
75° CIW
64-lead TOFP
w
g:
"'
0-
0
Z
< ~
x
0:
Z
0-
u: u:
">
0-
0-
Cl
u.
Z
Cl
0-
u. Zu.
Z
Z
u.
-'
W
Z
Cl
0-
Cl
Z
0-
""
>
~
AIN
N/C
AlP
47
BYPMO
46
N!C
NIC
HOLD
45
N!C
VNG
44
OACOUT
mw_z
43
VNC
VPC
42
MOEG
SOATA
41
1'WIml'I
40
N/C
seLK
SDEN
10
39
N/C
FREF
11
38
ROO
MTP3
12
37
RDI
VPB
13
36
WG
TFLT
14
35
MTP2
Tm
15
34
VNB
MTPl
VNA
[;'! S
Z
>
I-
-'
::>
f2 >~ ~
Cl
0-
>
"
0:
0:
Cl
Z
>
8
II)
QQQi~<
Z Z
0 ~
Z
0:
0:
64·Lead TQFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
SSI 33P3733A
64-Lead TOFP
ORDER NUMBER
33P3733A-CGT
PACKAGE MARK
33P3733A-CGT
Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
ofthird parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the rightto make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1293
10-29
©1993 Silicon Systems, Inc.
II
Notes:
10-30
SSI33P3733/34
8-26.5 Mbit/s Read Channel
December 1993
Wide bandwidth, high precision full-wave
rectifier
Programmable LEVEL pin time constant with
separate MO data and emboss registers
Separate Read and emboss AGC levels (4-bit DAC)
Dual mode pulse qualification circuitry (user
selectable)
Internal fast decay timing
External LOW_Z control pin
0.5 ns max. pulse pairing with sine wave input
DESCRIPTION
The SSI 33P3733/34 device is a high performance
SiCMOS single chip read channellC that contains all
the functions needed to implement a complete zoned
recording read channel for magneto-optical (MO) drive
systems. Functional blocks include the pulse detector,
programmable filter, time base generator, and data
synchronizer. MO data rates from 8 to 26.5 Mbitls for
(1,7) code, 6 to 20 Mbitls for (2,7) code can be
programmed using an internal DAC whose reference
current is set by a single external resistor.
Programmable functions of the SSI 33P3733/34
device are controlled through a bi-directional serial port
and banks of internal registers. This allows zoned
recording applications to be supported without
changing external component values from zone to
zone.
The SSI 33P3733/34 utilizes an advanced SiCMOS
process technology along with advanced circuit design
techniques which result in a high performance device
with low power consumption.
FEATURES
Programmable MO data rate of 8 to 26.5 Mbit/s
for (1,7) code, 6 to 20 Mbit/s for (2,7) code,
internal DAC controlled
Complete zoned recording application
support
Low-power operation (375 mW typical @ 5V)
BI-dlrectlonal serial port for register access
Register programmable power management
(Sleep mode <5 mW )
Power supply range (4.5 to 5.5 volts)
Small footprint 64-lead TQFP package
PULSE DETECTOR
Fast Attack/Decay modes for rapid AGC
recovery
Dual rate charge pump for fast transient
recovery
Low Drift AGC hold circuitry
Temperature compensated, exponential
control AGC
1293
PROGRAMMABLE FILTER
Programmable cutoff frequency of 4 to 12 MHz
Prog rammable boost/equalization of 0 to 13 dB
Matched normal and differentiated outputs
± 10 to 15% Ic accuracy
± 2% maximum group delay variation
Less than 1.5% total harmonic distortion
Low-Z input switch controlled by LOW_Z pin
No external filter components required
TIME BASE GENERATOR
Better than 1% frequency resolution
Up to 75 MHz frequency output
Independent divide-by M and N registers
VCO center frequency matched to data
synchronizer VCO
VCO (FOUT) output available In both Read and
Write mode
DATA SEPARATOR
Fast acquisition phase lock loop with zero
phase restart technique
Fully integrated data separator
- No external delay lines, active devices, or
active PLL components required
Programmable decode window symmetry
control via serial port
- Window shift control ± 30% (4-bit)
- Includes delayed read MO data and VCO
clock monitor points
Programmable write precompensation (3-bit)
(33P3734)
10-31
II
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FIGURE 1B: Block Diagram, Back End
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SSI 33P3733/34
8-26.5 Mbit/s Read Channel
FUNCTIONAL DESCRIPTION
The SSI 33P3733/34 implements a high performance
complete read channel, including pulse detector,
programmable active filter, time base generator, and
data synchronizer, at MO data rates up to 26.5 Mbitls
for (1,7) code, 20 Mbit/s for (2,7) code. A circuit block
diagram is shown in Figure 1 .
PULSE DETECTOR CIRCUIT DESCRIPTION
The pulse detector, in conjunction with the
programmable filter, provides allthe MO data processing
functions necessary for detection and qualification of
encoded read signals. The Signal processing circuits
include a wide bandwidth variable gain amplifier, a
precision wide bandwidth fullwave rectifier, and a dual
rate charge pump. The entire signal path is fullydifferential to minimize external noise pick up.
AGCCIRCUIT
The gain of the AGC amplifier is controlled by the
voltage (VBYPX) stored on the BYPx hold capacitor
(CBYPX). A dual rate charge pump drives CBYPX with
currents that depend on the instantaneous differential
voltage at the DP/DN pins. Attack currents lower VBYPX
which reduces the amplifier gain, while decay currents
increase VBYPX which increases the amplifier gain.
When the Signal at DP/DN is greater than 100% of the
programmed AGC level, the nominal attack current of
0.18 mA is used to reduce the amplifier gain. If the
signal is greater than 125% of the programmed AGC
level, a fast attack current of eight (8) times nominal is
used to reduce the gain. This dual rate approach allows
AGC gain to be quickly decreased when it is too highl
low yet minimizes distortion when the proper AGC level
has been acquired.
A constant decay current of 4 ~ acts to increases the
amplifier gain when the signal at DP/DN is less than the
programmed AGC level. The large ratio (0.18 mA:4~)
of the nominal attack and nominal decay currents
enable the AGC loop to respond to the peak amplitudes
of the incoming read signal rather than the average
value. A Fast Decay Current mode is provided to allow
the AGC gain to be rapidly increased, if required. In
Fast Decay mode, the decay current is increased by a
factor of 21.
In Read mode and Write mode, the reference voltage
for the AGC charge pump is a nominal 1.0V. When
MOEG is high, the reference voltage for the AGC
charge pump is set by a 4-bit DAC (DACA) controlled
by the serial port. The DAC output voltage is offset so
that"1111"results in a 0.75Voutput, and "0000" results
in a 1.00V output:
VAGC
= 1.00 - (DACA x 0.01667) Vpp
where DACA is the decimal value of the DACA register
When the chip is in Power Down mode, the AGC dual
rate charge pump is disabled.
Upon power up, the Low-Zlfast decay sequence should
be executed to rapidly recover from any transients or
drift which may have occurred on the BYPx hold
capacitors.
BYPMO AND BYPE CONTROL VOLTAGE
The BYPMO capacitor voltage will be held constant
(subject to leakage currents) during Sleep mode,
Emboss mode (MOEG = high), Write mode, or when
the HOLD signal is high. Upon the transition of PWRON
from high to low, there is a 1 IlS delay inserted before
the AGC charge pump is allowed to drive the BYPMO
capacitor. When MOEG is high, the charge pump
drives the BYPE capacitor. When MOEG is low, the
BYPE capacitor voltage will be held constant (subject
to leakage currents).
AGC MODE CONTROL
When write gate (WG) is driven low, the dual rate
charge pump is disabled causing the AGC amplifier
gain to be held constant. When the WG pin transitions
from low to high, the LOW_Z mode can be entered
using the LOW_Z control pin. When this pin is brought
low, the input impedance at both the AGC amplifier and
the programmable filter are reduced to allow for quick
recovery of the AC coupling capacitors. When the
LOW_Z pin goes high, the Fast Decay mode is triggered
allowing rapid acquisition of the proper AGC level. The
duration of the Fast Decay mode is internally set at a
nominal 1 1lS. Fast Decay mode is also triggered by a
transition of the MO/emboss gate (MOEG) pin in either
direction. When the pulse detector is powered-down,
VBYPX will be held constant subject to leakage currents
only.
External control for enabling the dual rate charge pump
is also provided. Driving the HOLD pin high forces the
dual rate charge pump output current to zero. In this
mode, VBYPX will be held constant subject to leakage
currents only.
10-34
S51 33P3733/34
8-26.5 Mbit/s Read Channel
RDIO OUTPUT PIN
HYSTERESIS COMPARATOR QUALIFICATION
A CMOS compatible, 10 ns wide (min), Raw Data
Output (RDIO) signal is provided. This pin will be held
low when either RG is high orWG is lowto reduce noise
and accompanying jitter during Read or Write modes.
Its rising edge indicates the presence of a valid MO
data pulse.
When the Hysteresis Qualification mode is selected,
the same threshold qualification comparators and clock
comparators are used to implement a polarity checking
rule. In this mode, a positive peak that clears the
established threshold level will set the hysteresis
comparator and trigger the bidirectional one-shot that
creates the read MO data pulses. In order to get
another pulse clocked out, a peak of the opposite
polarity must clear the negative threshold level to reset
the hysteresis comparator and trigger the bidirectional
one-shot. Hysteresis comparator timing is shown in
Figure 2B.
QUALIFIER SELECTION
The 33P3733/34 provides both hysteresis and dual
comparator pulse qualification circuits that may be
independently selected for Read mode and Embossed
mode operation. For Read mode operation the pulse
qualifier method is selected by setting the MSB in the
MO data threshold control register (MODTCR). The
lower 7 bits of the MODTCR also set the hysteresis
level of the comparators for Read mode. For Emboss
mode operation the pulse qualifier method is selected
by setting the MSB in the emboss threshold control
register (ETCR). The lower 7 bits of the ETCR set the
hysteresis level of the comparators for Emboss mode.
DUAL COMPARATOR QUALIFICATION
When in Dual Comparator mode, independent positive
and negative threshold qualification comparators are
used to suppress the error propagation of a positive and
negative threshold hysteresis comparator. However a
slight amount of hysteresis is included to increase the
comparator output time when a signal that just exceeds
the threshold level is detected. This eases the timing
with respect to the zero crossing clock comparator. A
differential comparator with programmable hysteresis
threshold allows differential signal qualification for noise
rejection. The floating hysteresis threshold, VTH, is
driven by a multiplying DAC which is driven by LEVEL
and referenced to VRC. Hysteresis thresholds from 10
to 80% may be set with a resolution of 1%. The internal
currentsink LEVEL DAC (DACL) and external capacitor
CT set the hysteresis threshold time constant. DACL is
switched between two 4-bit registers by MO/emboss
gate (MOEG) to determine the sink current magnitude
in MO Data mode and Emboss mode. In MO Data
mode, the four LSBs of the Hysteresis Decay Register
(HDR) determine the value of the pull-down current. In
Emboss mode the four MSBs are selected. The LSB
value of DACL is 3.125).lA, and DACL is offset by 1 LSB
such that "0000" corresponds to 3.125 ).lA, and "1111"
results in 50 ).lA. A qualified Signal zero crossing at the
CP-CN inputs triggers the output one shot. Dual
comparator timing is shown in Figure 2A.
PROGRAMMABLE FILTER CIRCUIT DESCRIPTION
The SSI 33P3733/34 programmable filter consists of
an electronically controlled low-pass filter with a
separate differentiated low-pass output. A seven-pole,
low-pass filter is provided along with a Single-pole,
single-zero differentiator. Both outputs have matched
delays. The delay matching is unaffected by any amount
of programmed equalization or bandwidth.
Programmable bandwidth and boost/equalization is
provided by internal 7-bit control DACs. The
programmable characteristics are automatically
switched during Emboss mode to improve signal to
noise ratio. Differentiation pulse slimming equalization
is accomplished by a two-pole, low-pass with a twopole, high-pass feed forward section to provide
complimentary real axis zeros. A variable attenuator is
used to program the zero locations.
The filter implements a 0.05 degree equiripple linear
phase response. The normalized transfer functions
(Le., Wc = 2 re/c = 1) are:
VnormlVi = [(-Ks2 + 17.98016)/D(s)] x AN
and
VdiffIVi = (VnormlVi) x (s/0.86133) x AD
where D (s)=
(S2 + 1.68495s + 1.31703)(S2 + 1.54203s +
2.95139)(S2 + 1 .14558s + 5.37034)(s + 0.86133),
AN and AD are adjusted for a gain of 2 at fs = (213)/c.
10-35
II
SSI 33P3733/34
8-26.5 Mbit/s Read Channel
I
DATA+
Jl
DATA-
a~
ONE
SHOT
--.ll
I
n
h
I
I
n
fL
n
FIGURE 2A: Dual Comparator Timing Diagram
FIGURE 28: Hysteresis Comparator Timing Diagram
10-36
L
IL
S51 33P3733/34
8-26.5 Mbit/s Read Channel
BOOST/EQUALIZATION CONTROL
FUNCTIONAL DESCRIPTION (continued)
FILTER OPERATION
AC coupled differential signals from the AGC are
applied to the FIP/FIN inputs of the filter. To improve
settling time of the coupling capacitors, the FIP/FIN
inputs are placed into a Low-Z state when the LOW_Z
pin is brought low. The programmable bandwidth and
boost/equalization features are controlled by internal
DACs and the registers programmed through the serial
port. The current reference for both DACs is set using
a single 12.1 ill external resistor connected from pin
RX to ground. The voltage at pin RX is proportional to
absolute temperature (PTAT), hence the current for
the DACs is a PTAT reference current.
BANDWIDTH CONTROL
The programmable bandwidth is set by the filter cutoff
DAC. This DAC has two separate 7-bit registers that
can program the DAC value as follows:
Ic = 0.09449 x DACF (MHz)
where DACF = MODMCR or EMCR value
In the MO Data mode, the MO Data Mode Cutoff
Register (MODMCR) is used to determine the filter's
3 dBcutofffrequency.lnthe Emboss mode, the Emboss
Mode Cutoff Register (EMCR) is used. Switching ofthe
registers is controlled by the MO/emboss gate (MOEG)
pin. The filter cutoff set by the internal DAC is the
unboosted 3 dB frequency. When boost/equalization is
added, the actual 3 dB point will move out. Table 1
provides information on boost verses 3 dB frequency.
TABLE 1: 3 dB cutoff frequency versus boost
magnitude
BOOST
(dB)
0
Ic
Ic
(3 dB)
BOOST
(dB)
(3 dB)
1.00
7
2.42
8
2.51
1
1.21
2
1.50
9
2.59
3
1.80
10
2.66
4
2.04
11
2.73
5
2.20
12
2.80
6
2.32
13
2.86
The programmable equalization is also controlled by
an internal DAC. The 7 -bit Filter Boost Control Register
(FBCR) determines the amount of equalization that will
be added to the 3 dB cutoff frequency, as follows:
Boost = 20 log [(0.0273 x FBCR) + 1] (dB)
For example, with the DAC set for maximum output
(FBCR = 7fHor 127) there will be 13dBof boost added
at the 3 dB frequency. This will result in + 10 dB of signal
boost above the 0 dB baseline. When MOEG is active
the boost can be disabled by setting bit 7 in Control A
register (CAR). When bit 7 is "0" and MOEG is active
the boost will automatically be set to 0 dB. If bit 7 is "1"
the boost will remain at its programmed value regardless
of the state of MOEG.
TIME BASE GENERATOR CIRCUIT DESCRIPTION
The time base generator, which is a PLL based circuit,
provides a programmable frequency reference for
constant density recording applications. The frequency
can be programmed with an accuracy better than 1%.
An external passive loop filter is required to control the
PLL locking characteristics. The filter is fully-differential
and balanced in order to suppress common mode
noise generated, for example, from the data
synchronizer'S PLL.
In Read, Write and Idle modes, the time base generator
is programmed to provide a stable reference frequency
for the data synchronizer. In Read mode the internal
reference clock is disabled after the data synchronizer
has achieved lock and switched over to read MO data
as the source for the RRC. This minimizes jitter in the
data synchronizer PLL. The reference frequency is
programmed using the M and N registers of the time
base generator via the serial port, and is related to the
external reference clock input, FREF, as follows:
Reference Frequency
10-37
= «M+1)/(N+1»FREF
II
I
SSI 33P3733/34
8-26.5 Mbit/s Read Channel
TIME BASE GENERATOR
CIRCUIT DESCRIPTION (continued)
The VCO center frequency and the phase detector
gain of the time base generator are controlled by an
internal OAC addressed through the MO data recovery
control register (MOORCR). This OAC also sets the
1/3 cell delay for (1,7) code or 1/4 cell delay for (2,7)
code, VCO center frequency, and phase detector gain
for the data synchronizer circuitry. When changing
frequencies, the M and N registers must be loaded first,
followed by the MOORCR register. A frequency change
is initiated only when the MOORCR register has been
changed.
Fvco = [12.5/(RR + 0.4)]
x [(0.622 x IOAC) + 4.27] MHz;
for Fvco < 24 MHz
Fvco = [12.5/(RR + 0.4)]
x [(0.7 x IOAC) + 1.4] MHz
where IOAC is the value in the MOORCR and RR is the
value (ka) of the external RR resistor.
DATA SYNCHRONIZER CIRCUIT DESCRIPTION
In the Read mode, the data synchronizer performs
sync field search and data synchronization. Inthe Write
mode, the circuit provides write precompensation. Oata
rate is established by the time base generator and the
intemal reference DACI controlled by the MODRCR.
The DAC generates a reference current which sets the
VCO center frequency, the phase detector gain, and
the 113 or 1/4 cell delay.
PHASE LOCKED LOOP
The circuit employs a dual mode phase detector;
harmonic in the Read mode and non-harmonic in the
Write and Idle modes. In the Read mode the harmonic
phase detector updates the Pll with each occurrence
of a ORO pulse. In the Write and Idle modes the nonharmonic phase detector is continuously enabled, thus
maintaining both phase and frequency lock onto the
reference frequency of the intemal time base generator.
By acquiring both phase and frequency lock to the input
reference frequency and utilizing a zero phase restart
technique, the VCO transient is minimized and false
lock to DlYO DATA is eliminated. The phase detector
incorporates a charge pump in order to drive the loop
filter directly. The polarity and width of the output
current pulses correspond to the direction and
magnitude of the phase error.
The data synchronizer also requires an external passive
loop filter to control its Plliocking characteristics. The
filter is again fully-differential and balanced in order to
suppress common mode noise which may be generated
from the time base generator's PlL.
MODE CONTROL
The read gate (RG) and write gate (WG) inputs control
the Device Operating mode. RG is an asynchronous
input and may be initiated or terminated at any position
on the disk. WG is also an asynchronous input, but
should not be terminated prior to the last output write
MO data pulse.
READ MODE
The data synchronizer utilizes a fully integrated fast
acquisition Pll to accurately develop the decode
window. Read gate (RG) initiates the Pll locking
sequence and selects the Pll reference input; a high
level (Read mode) selects the internal RD input and a
low level selects the reference clock. In the Read mode
the falling edge of ORO enables the phase detector
while the rising edge is phase compared to the rising
edge of the VCO reference (VCOR). ORO is a 1/3 (for
(1,7) code or 1/4 for (2,7) code) cell wide (TVCO) pulse
whose leading edge is defined by the falling edge of
RD. A decode window is developed from the VCOR
clock.
PREAMBLE SEARCH
When RG is asserted, an intemal counter is triggered
to count positive transitions of the incoming read MO
data, RD. Once the counter reaches a count of 3, the
internal read gate is enabled. This switches the phase
detector reference from the intemal time base to the
delayed read data (ORO) signal. At the same time an
intemal zero phase restart signal restarts the VCO in
phase with the ORO. This prepares the VCO to be
synchronized to MO data when the bit sync circuitry is
enabled after VCO lock is established.
10-38
SS133P3733/34
8-26.5 Mbit/s Read Channel
VCO LOCK AND BIT SYNC ENABLE
WRITE MODE (551 33P3734)
One of two VCO locking modes will be entered
depending on the state of the gain shift (GS) bit, or bit
1, in the Control B register. If GS = "1", the phase
detector will enter a gain shift mode of operation. The
phase detector starts out in a high gain mode of
operation to support fast phase acquisition. After an
internal counter counts the first 11 transitions of the
internal DRD Signal, the gain is reduced by a factor of
3. This reduces the bandwidth and dampening factor of
the loop by "3 which provides improved jitter
performance in the MO data follow mode. The counter
continues to count the next 5 DRD transitions (a total of
19 pulses from assertion of RG) and then asserts an
internal VCO lock signal.
Write mode is entered by asserting the write gate (WG)
while the RG is held low. During Write mode the VCO
and the RRC are referenced to the intemal time base
generator signal.
When the VCO lock Signal is asserted, the internal
RRC source is also switched from the time base
generator to the VCO clock signal that is phase locked
to DRD. During the internal RRC switching period the
external RRC signal may be held for a maximum of 2
VCO clock periods, however no short duration glitches
will occur.
When the GS bit is set to ''0'' the phase detector gain
shift function is disabled. The VCO lock sequence is
identicalto that ofthe gain shift mode explained above,
except that no gain shift is made after the first 11
transitions.
WINDOW SHIFT
Shifting the phase of the VCO clock effectively shifts
the relative position ofthe DRD pulse within the decode
window. Decode window control is provided via the WS
control bits of the Window Shift Control Register
(WSCR). Further description of the WSCR is provided
in the window shift control section.
NON-READ MODE
In the Non-Read modes, the PLL is locked to the
reference clock. This forces the VCO to run at a
frequency which is very close to that required for
tracking actual MO data. When the reference input to
the PLL is switched, the VCO is stopped momentarily,
then restarted in an accurate phase alignment with the
next PLL reference input pulse. By minimizing the
phase alignment error in this manner, the acquisition
time is substantially reduced.
DIRECT WRITE FUNCTION
The 551 33P3734 includes a Direct Write (DW) function
that allows the EWDATA MO data to bypass the write
precomp circuitry. When the D3 bit of the WPR is set to
zero, the MO data applied to EWDATA will bypass the
write precomp and directly control the EWRD output
buffer. This allows the user to perform DC erase and
media tests.
OPERATING MODES AND CONTROL
The 551 33P3733/34 has several operating modes that
support Read, Write, Emboss, and power management
functions. Mode selection is accomplished by controlling
the read gate (RG), write gate (WG), MO/emboss gate
(MOEG), and PWRON pins. Additional modes are also
controlled by programming the Power Down Control
Register (PDCR), the Control A register (CAR), and the
Control B register (CBR) via the serial port.
EXTERNAL MODE CONTROL
All operating modes of the device are controlled by
driving the read gate (RG), write gate (WG), MO/emboss
gate (MOEG), and PWRON pins with TTL compatible
signals. For normal operation the PWRON pin is driven
low. During normal operation the 551 33P3733/34 is
controlled by the read gate (RG), write gate (WG), and
MO/emboss gate (MOEG) pins. When RG is high and
WG is high the device is in Read mode. When WG is low
and RG is low the device is in Write mode. If the RG is
low and WG is high the device will be in Idle mode.
During the Idle mode, the MOEG pin can be activated to
enable the Emboss mode of operation.
1()'39
I
I
SSI 33P3733/34
8-26.5 Mbit/s Read Channel
FUNCTIONAL DESCRIPTION (continued)
SERIAL INTERFACE OPERATION
POWER DOWN CONTROL
The serial interface is a CMOS bi-directional port for
reading and writing program ming data from/to the internal
registers of the SSI 33P3733/34. The serial port data
transfer format is shown in Figure 3. For data transfers
SDEN is brought high, serial data is presented at the
SDATA pin, and aserial clock is applied to the SCLK pin.
After the SDEN goes high, the first 16 pulses applied to
the SCLK pin will shift the data presented at the SDATA
pin into an internal shift register on the rising edge of
each clock. An internal counter prevents more than 16
bits from being shifted into the register. The data in the
shift register is latched when SDEN goes low. If less
than 16 clock pulses are provided before SDEN goes
low, the data transfer is aborted.
For power management, the PWRON pin can be used
in conjunction with the Power Down Control Register
(PDCR) to set the operating mode of the device. The
PDCR provides a control bit for each of the functional
blocks. When the PWRON pin is brought high ("1 ") the
device is placed into Sleep mode «5 mW) and all
circuits are powered down except the serial port. This
allows the user to program the serial port registers
while still conserving power. Register information is
retained during the Sleep mode so it is not necessary
to reprogram the serial port registers after returning to
an active mode. When the PWRON pin is driven low
("0"), the contents ofthe PDCR determine which blocks
will be active. Register mappingforthe PDCR is shown
in Table 3. To improve recovery time from the Sleep
mode, the LOW_Z pin should be asserted following
power down to initiate the AGC recovery sequence.
All transfers are shifted into the serial port LSB first. The
first byte of the transfer is address and instruction
information. The LSB of this byte is the RIW bit which
determines if the transfer is a read (1) or a write (0). The
remaining 7-bits determine the internal register to be
accessed. Table 3 provides register mapping information.
The second byte contains the programming data. In
Read mode (RIW=1) the SSI33P3733/34 will outputthe
register contents of the selected address. In Write mode
the device will load the selected register with data
presented on the SDATA pin. At initial power-up, the
contents of the internal registers will be in an unknown
state and must be programmed prior to operation.
During power down modes, the serial port remains
active and register programming data is retained.
Detailed timing information is provided in Figure 4.
10-40
SSI 33P3733/34
8-26.5 Mbit/s Read Channel
S~
SDATA
<
ADDRESS, a-BIT
>-<
~_--.-J
SCLK
L
DATA, a-BIT
>-
~_--.-J
FIGURE 3: Serial Port Data Transfer Format
TABLE 2: MODE CONTROL
CONTROL
LINE
IZ~
DAC
CONTROL
Ien
(!)
w
~
en
w
a:
w
Ien
U5
~ (!)
a:
0
~
I~
1
X
X
X
0
0
0
0
0
1
0
1
READ MODE: The pulse detector is active. The data
synchronizer begins the preamble lock sequence. RDIO is
active
MR MRMR MR
0
0
1
1
EMBOSS MODE: The pulse detector is active and the emboss
control registers are enabled for the Fc DAC and the VTH
DAC. The data synchronizer and time base generator can be
disabled using the PDCR.
ER ER off ER
0
0
0
1
IDLE MODE: The contents of the PDCR determine which
blocks are powered-up. In normal operation with all blocks
powered-up, the pulse detector is active, the data synchronizer
VCO is locked to the time base generator, and the MO data
control registers are used for VTH and FC.
MR MRMR MR
- - -
-
All other states are illegal. If an illegal state is programmed,
the chip function will be in an indeterminable state, but no
damage will occur.
MR MRMR MR
:r:
DEVICE MODE
I-
>
0
u.
>-
:I:
off off off off
SLEEP MODE: All functions are powered down. The serial
port registers remain active and register programming data is
saved.
WRITE MODE: The pulse detector is inactive. The data
MR MRMR MR
synchronizer VCO is locked to the internal time base generator.
Write precomp circuit is clocked by internal time base.
(881 33P3734)
DAC CONTROL KEY: MR = MO DATA REGISTER, ER = EMBOSS RIGISTER, OFF = DISABLED
10-41
I
REGISTER NAME
~~
ADDRESS
DATA BITMAP
D7
FILTER
TBG
DATASEP
l=DISABLE l=DISABLE l=DISABLE
O=ENABLE O=ENABLE O=ENABLE
FCM DAC
BITl
FCM DAC
BITO
FCE DAC
BIT3
FCE DAC
BIT 2
FCE DAC
BITl
FCE DAC
BITO
cnW
F. DAC
BIT4
F. DAC
BIT3
F. DAC
BIT2
F.DAC
BIT 1
F. DAC
BITO
(D~
C-
--
MO DATA MODE CUTOFF
0 0 0 0 0
0
--
FCM DAC
BIT6
FCMDAC
BIT5
FCM DAC
BIT4
FCMDAC
BIT3
EMBOSS MODE CUTOFF
0 0 1 0 0 1 1 0
--
FCE DAC
BIT6
FCE DAC
BIT5
FCE DAC
BIT4
l=ENABLE
O=DISABLE
F.DAC
BIT6
F. DAC
BITS
FILTER BOOST
0 0 0 1 0 1 1 0
MO DATA THRESHOLD
0 0 0 1 0 1 0 0
l=DUAL
O=HYS
TMDAC
BIT6
TuDAC
BITS
TM DAC
BIT4
TMDAC
BIT3
TMDAC
BIT 2
TM DAC
BITl
TMDAC
BITO
EMBOSS THRESHOLD
0 0 1 0 0
l=DUAL
O=HYS
TEDAC
BIT6
TE DAC
BITS
TE DAC
BIT4
TE DAC
BIT 3
TE DAC
BIT2
TE DAC
BIT 1
TE DAC
BITO
TMSO
TBG
l=BYPASS
O=NORMAL
1 0 0
0 0 1 1 0 1 0 0
CONTROL B
0 0 0 1 1 0 0 0
--
N COUNTER
0 0 0 0 1 1 0 0
--
NCOUNT
BIT6
NCOUNT
BIT5
NCOUNT
BIT4
NCOUNT
BIT3
NCOUNT
BIT 2
NCOUNT
BITl
NCOUNT
BITO
M COUNTER
0 0 0 1 1 1 0 0
MCOUNT
BIT7
MCOUNT
BIT6
MCOUNT
BIT5
MCOUNT
BIT4
MCOUNT
BIT3
MCOUNT
BIT2
MCOUNT
BITl
MCOUNT
BITO
DATA RECOVERY
0 0 0 0 1 0 0 0
--
DACI
BIT6
DACI
BIT5
DACI
BIT4
DACI
BIT3
DACI
BIT2
DACI
BIT 1
DACI
BITO
WINDOW SHIFT
0
0 0 0 1 0
1 0
TDACl
TDACO
WINSHFT
l=ENABLE
O=DISABLE
WSDIR
l=LATE
O=EARLY
WS3
WS2
WlIT
~
WRITE PRECOMP
0 0 0 1 1 0
1 0
--
Wl:2
WIT
W[Q
WRPRCMP
l=ENABLE
O=DISABLE
WE2
WET
we>
AGC LEVEL
0 1 0 0 0 1 0 0
--
--
--
--
AGCDAC
BIT3
AGCDAC
BIT 2
AGCDAC
BIT 1
AGCDAC
BITO
HYSTERESIS DECAY
0
EMBOSS
BIT3
EMBOSS
BIT 2
EMBOSS
BITl
EMBOSS
BITO
DATA
BIT3
DATA
BIT2
DATA
BIT 1
DATA
BITO
1 0 0
_.""
c::!:W
J]W
MTPE
PUMPDWN
l=ENABLE
l=TP ON
O=DISABLE O=TPOFF
PUMP UP
l=TP ON
O=TP OFF
TABLE 3: Serial Port Register Mapping
O
::T
Q)
:::l
:::l
PUMP UP PHASE DET
l=ENABLE
l=TP ON
O=TP OFF O-DISABLE
GAINSHFT
RDIO
PHASE DET
1 =ON
l=ENABLE 1 = INPUT
O=OFF
O_DISABLE O=OUTPUT
CONTROL A
1 0
3:"'0
o-W
PUMP OWN
l=TP ON
O=TPOFF
Fast Decay
test mode
O=ENABLE
1 0
CJ1W
Q)
TMSl
W
FCM DAC
BIT2
--
EMBOSS BOOST
•
PO
l=DISABLE
O_ENABLE
--
1
0')-
--
0 0 0 0 0 1 0 0
1
(lOC/)
NC/)
DO
POWER DOWN CONTROL
~
I\J
<0
«
TBGTEST
POINT
ENABLE
(D
--
!
551 33P3733/34
8-26.5 Mbit/s Read Channel
FUNCTIONAL DESCRIPTION (continued)
CONTROL REGISTERS
Control registers CAR and CBR allow the user to configure the SSI 33P3733/34 test points for evaluation of
different internal signals and also control other device functions. CAR controls functions of the pulse detector, filter,
and time base generator. CBR controls test points and functions of the data separator. The bits of the CA and CB
registers are defined as follows:
CONTROL REGISTER CA
BIT
NAME
FUNCTION
0
EPDT
Enable Phase Detector (Time Base Generator)
1
UT
Pump Up (TFLTR sources current, TFLTR sinks Current)
2
DT
Pump Down (TFLTR sinks current, TFLTR sources Current)
3
ET
Enable Time Base Generator Test Point Output
4
BYPT
Bypass Time Base Generator Circuit Function
5
TMSO
Control bit for selecting test pOint source (see Table 4)
6
TMS1
Control bit for selecting test point source (see Table 4)
7
FDTM
Constant fast decay current test mode
CONTROL REGISTER CB
0
-
Not Used
1
GS
Enable Phase Detector Gain Switching
2
RDI
RDIO Pin Input Control
3
EPDD
Enable Phase Detector (Data Separator)
4
UD
Pump Up (DFLTR sources current, DFLTR sinks current)
5
DD
Pump Down (DFLTR sinks current, DFLTR sources current)
6
MTPE
7
-
Enable Test Points MTP1, 2,3 (see Table 4)
Not used
I
10-43
SSI33P3733/34
8-26.5 Mbit/s Read Channel
PIN DESCRIPTION
POWER SUPPLY PINS
NAME
TYPE
DESCRIPTION
Time base generator Pll analog power supply pin
VPC
-
VPD, VPD2
-
CMOS buffer 1/0 digital power supply pin
VPG
-
Pulse detector, filter, analog power supply pin
VPA
VPB
VNA
VNB
VNC
Data separator Pll analog power supply pin
Internal ECl, CMOS logic power supply pin
Data separator Pll analog ground pin
Time base generator Pll analog ground pin
Internal ECl,CMOS logic ground pin
-
CMOS buffer 1/0 digital ground pin
AIP,AIN
I
AGC AMPLIFIER INPUTS: Differential AGC amplifier input pins.
DP, ON
I
ANALOG INPUTS FOR MO DATA PATH: Differential analog inputs to MO
data comparators, full-wave rectifier.
CP,CN
I
ANALOG INPUTS FOR CLOCK PATH: Differential analog inputs tothe clock
comparator.
lOW_Z
I
lOW IMP E DANC E ENABLE: TTL compatible input pin that activates the lowZ switches. A low level activates the switches and the falling edge of the
internal lOW_Z triggers the fast decay circuit.
PWRON
I
POWER ENABLE: TTL compatible power control input. A low level input
enables power to circuitry according to the contents of the PDCR. A high level
input shuts down all circuitry.
HOLD
I
HOLD CONTROL: TTL compatible control pin which, when pulled high,
disables the AGC charge pump and holds the AGC amplifier gain at its present
value.
FIP, FIN
I
FilTER SIGNAL INPUTS: The AGC output signals must be AC coupled into
these pins.
FREF
I
REFERENCE FREQUENCY INPUT: Frequency reference input for the time
base generator. FREF may be driven either by a direct coupled TTL signal or
by an AC coupled ECl signal. Pin FREF has an internal pull down resistor.
EWDATA
I
WRITE INPUT: TTL compatible write MO data input. (SSI 33P3734)
EARLY, lATE
I
WRITE PRECOMPENSATION CONTROL: TTL compatible inputs. The
EARLY and lATE signals control on-the-fly precompensation of the
EWDATA. (SS133P3734)
VND, VND2
VNG
Pulse detector, filter, analog ground pin
INPUT PINS
10-44
SSI 33P3733/34
8-26.5 Mbit/s Read Channel
INPUT PINS
(continued)
NAME
TYPE
DESCRIPTION
RG
I
READ GATE: TTL compatible read gate input. A high level TTL input selects
the RD input and enables the Read mode/address detect sequences. A low
level selects the FREF input.
MOEG
I
MO/emboss GATE: TTL compatible MO/emboss gate input. A high level TTL
input activates the Emboss mode by selecting the emboss control registers,
the RTS resistor, and the BYPE capacitor.
WG
I
WRITE GATE: TTL compatible write gate input. A low level TTL input enables
the Write mode.
MTP1-3
0
MULTIPLEXED TEST POINTS: Open emitter ECL output test pOints. Internal
test signals are routed to these test points as determined by the CAR and CBR.
External resistors are required to use these pins. They should be removed
during normal operation to reduce power dissipation.
SDO
0
SYNCHRONIZED READ DATA: CMOS output pin. Read MO data output
when RG is high.
FOP, FDN
0
DIFFERENTIAL DIFFERENTIATED OUTPUTS: Filter differentiated outputs.
These outputs are AC coupled into the CP/CN inputs.
FNP, FNN
0
DIFFERENTIAL NORMAL OUTPUTS: Filter normal low pass output signals.
These outputs are AC coupled into the DP/DN inputs.
RDIO
I/O
READ MO DATA I/O: Bi-directional CMOS output / TTL compatible input pin.
RDIO is an output when RG is low and the RDIO bit is low in the CBR. RDIO
is an input when the RDIO bit is high in the CBR. The minimum RDIO input
pulse width is TBD ns. The RG and pulse detector functions override the bit
in the CBR. When RDIO is used as an input pin, 1/3 or 1/4 cell delay in the data
synchronizer is made from the rising edge.
RRC
0
READ REFERENCE CLOCK: Read clock CMOS output. During a mode change,
no glitches are generated and no more than one lost clock pulse will occur. When
RG goes high, RRC initially remains synchronized to the reference clock. When
the Sync Bits are detected, RRC is synchronized to the Read MO Data. When RG
goes low, RRC is synchronized back to the reference clock.
AOP,AON
0
AGC AMPLIFIER OUTPUT: Differential AGC amplifier output pins. These
outputs are AC coupled into the filter inputs (FIP/FIN).
EWRD
0
WRITE MO DATA: Encoded write MO data CMOS output. When direct write
is active EWRD is directly driven by EWDATA.
FOUT
0
TIME BASE GENERATOR VCO OUTPUT: CMOS output pin. This clock signal is the
data separator PLL reference. This output is independent of the RG/WG pin.
PPOL
0
PULSE POLARITY: Pulse polarity CMOS output pin. The output is high when
the pulse being qualified is positive and it is low when the pulse being qualified
is negative. (SSI 33P3733)
OUTPUT PINS
10-45
I
SSI 33P3733/34
8-26.5 Mbit/s Read Channel
PIN DESCRIPTION
(continued)
ANALOG PINS
NAME
TYPE
DESCRIPTION
BYPMO
-
The AGC Read mode integration capacitor CBYPMO, is connected between
BYPMO and VPG.
BYPE
-
The AGC Emboss mode integration capacitor CBYPE, is connected between
BYPE and VPG.
DACOUT
-
DAC VOLTAGE TEST POINT: This test point monitors the outputs of the
internal DACs. The source DAC is selected by programming the two MSBs of
the WSCR register (see Table 5).
TFLT,TFLT
-
PLL LOOP FILTER: These pins are the connection points for the time base
generator loop filter.
DFLT,DFLT
-
PLL LOOP FILTER: These pins are the connection points for the data
separator loop filter.
LEVEL
-
An NPN emitter output that provides a full-wave rectified signal from the DP,
DN inputs. An external capacitor should be connected from LEVEL to VPG to
set the hysteresis threshold time constant in conjunction with the internal
current DAC, (DACA).
RR
-
REFERENCE RESISTOR INPUT: An external 12.1 kn, 1% resistor is connectedfrom this pin to VNA to establish a precise internal reference currentfor
the data separator and time base generator.
RX
-
REFERENCE RESISTOR INPUT: An external 12.1 kil, 1% resistor is connected from this pin to ground to establish a precise PTAT (proportional to
absolute temperature) reference current for the filter.
SDEN
-
SERIAL DATA ENABLE: Serial enable CMOS input. A high level TTL input
enables the serial port.
SDATA
-
SERIAL DATA: Serial data CMOS input. NRZ programming data for the
internal registers is applied to this input.
SCLK
-
SERIAL CLOCK: Serial clock CMOS input. The clock applied to this pin is
synchronized with the data applied to SDATA.
SERIAL PORT PINS
10-46
SSI 33P3733/34
8-26.5 Mbit/s Read Channel
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, the recommended operating conditions are as follows: 4.5V < POSITIVE
SUPPLY VOLTAGE < 5.5V, O°C < T (ambient) < 70°C, and 25°C < T(junction) < 135°C. Currents flowing into
the chip are positive. Current maximum are currents with the highest absolute value.
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER
RATING
Storage Temperature
-65 to 150°C
Junction Operating Temperature
+135°C
Positive Supply Voltage (Vp)
-0.5 to 7V
Voltage Applied to Logic Inputs
-0.5V to Vp + 0.5V
All other Pins
-0.5V to Vp + 0.5V
POWER SUPPLY CURRENT AND POWER DISSIPATION
PARAMETER
CONDITIONS
ICC (VPA,B,C,D,G)
Outputs and test point pins
open, Ta = 27°C,
VPn = 5V, 24 Mbit/s
75
mA
PWR
Power Dissipation
Outputs and test point pins
open, Ta = 27°C,
VP = 5V, 24 MbiUs
375
mW
Sleep mode Power
PWRON = 1
Emboss mode Power
PWRON =0
TBG Disabled
Data Sep. Disabled
MIN
NOM
MAX
5
UNIT
mW
mW
200
DIGITAL INPUTS AND OUTPUTS
TTL COMPATIBLE INPUTS
Input low voHage
VIL
Input high voltage
VIH
-0.3
0.8
2
V
VPD +0.3
V
Input low current
ilL
VIL = O.4V
-100
Input high current
IIH
VIH = 2.4V
50
llA
llA
CMOS COMPATIBLE INPUTS - Schmitt trigger type (not to be left open.) Nominal1.0V hysteresis around VPO/2.
Input low voHage
-0.3
1.5
V
Input high voltage
3.5
VPD + 0.3
V
10-47
I
SSI33P3733/34
8-26.5 Mbit/s Read Channel
DIGITAL INPUTS AND OUTPUTS (continued)
CMOS COMPATIBLE OUTPUTS
0.5
V
Output low voltage
5V,25°C
IOL = 4.07 mA
Output high voltage
5V,25°C
IOH = -4.83 mA
Rise time
4.5V, 70°C, C = 15 pF
8
ns
Fall time
4.5V, 70°C, C = 15 pF
8
ns
V
4.5
PSEUDO ECl OUTPUT lEVELS (MTP1, MTP2, MTP3)
For all tests, 261 f.l to VPA and 402f.l to VNA with VPA = 5.0V
Output high level
V
VPA
-1.02
VPA
-1.62
Output low level
V
SERIAL PORT
SCLK period
TCLK
100
ns
SCLK low time
TCKL
40
ns
SCLK high time
TCKH
40
ns
Enable to SCLK
TSENS
35
ns
SCLK to disable
TSENH
35
ns
Data set-up time
TDS
15
ns
TDH
15
Data hold time
SDATA tri-state delay
SDATA turnaround time
SDEN low time
ns
50
TSENDL
ns
TTRN
70
ns
TSL
200
ns
10-48
551 33P3733/34
8-26.5 Mbit/s Read Channel
SDEN
l<:
~
TSENS
L
TTRN
SCLK
SDATA
(READ)
"--J
SDATA \
(WRITE) _ _
RAN
RAN
\
L
ADDRO
ADDR6
ADDRO
aD
aD
DATA 7
DATA 7
'j)-
FIGURE 4: Serial Port Timing Information
I
10-49
SSI33P3733/34
8-26.5 Mbit/s Read Channel
ELECTRICAL SPECIFICATIONS (continued)
PULSE DETECTOR CHARACTERISTICS
AGC AMPLIFIER
Input signals are AC coupled to AIP/AIN, AOP/AON outputs are AC coupled to FIPIFIN, and FNP/FNN are AC coupled
to OP/ON. 1000 pF capacitors are connected from BYPMO to VPG (CSYPt.o) and from BYPE to VPG (CSYPE). Unless
otherwise specified, OU1puts are measured differentially at AOP/AON, FIN = 8 MHz, and finer boost = 0 dB.
PARAMETER
CONDITIONS
Input range
Filter boost 0 to 13 dB
DP-DN voltage
AlP - AIN
DP-DN voltage variation
MIN
= 0.1
MAX
UNIT
190
mVpp
0.9
1
1.1
Vpp
MOEG = high, AGC DAC = 0
0.9
1
1.1
Vpp
MOEG = high, AGC DAC = 15
0.68
0.76
0.84
Vpp
Vpp
20 mV < AlP - AIN < 190 mV
Gain range
0.45
Gain sensitivity
BYPx voltage change
AOP-AON dynamic range
THD= 1%
0.6
Differential input impedance
LOW_Z= high
4.7
8
%
18
VN
dBN
28
Vpp
6
8.4
kn
350
n
LOW_Z= high
3.3
kn
LOW_Z= low
250
n
LOW_Z=low
Single-ended input impedance
NOM
20
Single-ended output impedance
AOP/AON to ground
120
n
Output offset voltage variation
Gain = 0.45 to 18
200
mV
Input noise voltage
Gain = 18, AOP - AON = OV
Bandwidth
Gain = 18, CL::; 15 pF
20
nVI..JHz
35
MHz
CMRR
Gain = 18, Ic = 5 MHz
40
dB
PSRR
Gain = 18, Ic = 5 MHz
45
dB
Gain decay time
AlP - AIN = 250 to 125 mV,
AOP - AON > 0.9 Final Value
36
iJS
Gain attack time
AlP - AIN = 125 to 250 mY,
AOP - AON < 1.1 Final Value
0.65
iJS
AGCCONTROL
The input signals are AC coupled into DN/DP, CBYPX = 1000 pF to VPG, MOEG = low.
DP-DN input range
For test only
Decay current
Normal decay
Attack current
1
1.5
Vpp
~
10
4
Fast Decay mode
IOF
21 x 10
~
Normal attack
ICH
0.18
mA
ICHF
8 x ICH
mA
Fast Attack mode
10-50
SSI33P3733/34
8-26.5 Mbit/s Read Channel
AGC CONTROL (continued)
PARAMETER
CONDITIONS
MIN
BYPMO leakage current
WG = high
-10
Fast decay duration
MAX
UNIT
10
nA
0.70
JlS
VNpp
1
LEVEL output gain
IDP-DNI = 0.5 to 1.5V
LEVEL output bandwidth
-1 dB
LEVEL pin pull-down current
NOM
0.60
0.65
MHz
10
DACL = 0000
DACL = 1111 where ILEVEL =
3.125 x (1 + DACL) J.1A
1.56
3.125
4.69
47
50
53
J.1A
J.1A
1
DATA COMPARATOR
The input signals are AC coupled into DP/DN.
1.5
Vpp
LOW_Z= Off
8.0
14
kQ
LOW_Z= On
0.4
1.2
kQ
5
pF
DP-DN input range
Differential input resistance
Differential input capacitance
Threshold voltage hysteresis
%T
10
Threshold voltage gain
(KTH) tolerance
0.47 < IDP - DNI < 1.19
T = VTHDAC x 0.93/127
38 < VTHDAC < 127
Minimum threshold voltage
IDP - DNI < 0.16
VTHMIN = VTHDAC· 97.6%/127
PPOL rise time (SSI33P3733)
10% to 90% points, CL ~ 15 pF
8
ns
PPOL fall time (SSI 33P3733)
90% to 10% points, CL ~ 15 pF
8
ns
1.5
Vpp
T + 10
T -10
%
V
VTHMIN
CLOCK SECTION
The input signals are AC coupled into CP/CN.
CP-CN input range
Comparator offset voltage
-4
4
mV
Differential input resistance
8
14
kQ
5
pF
0.5
ns
Differential input capacitance
Pulse pairing
DP/DN = 1 Vpp sine,
CP/CN = 1 Vpp - 900sine
Fsine = 8 MHz
RDIO pulse width
CL:515pF
6
RDIO input pulse width
15
ns
ns
10
RDIO rise time
10% to 90% points, CL :5 15 pF
8
ns
RDIO fall time
90% to 10% points, CL :5 15 pF
8
ns
10-51
II
SSI 33P3733/34
8-26.5 Mbit/s Read Channel
PULSE DETECTOR CHARACTERISTICS (continued)
PROGRAMMABLE FILTER CHARACTERISTICS
PARAMETER
CONDITIONS
Filter cutoff range
fc @ -3 dB point
fc = (0.09449 MHz) x DACF,
MIN
NOM
4
MAX
UNIT
12
MHz
Boost = 0 dB
42 ~ DACF ~ 127
DACF = MODMCR
Filter cutoff accuracy
DACF = 127
-10
10
DACF = 42 to DACF < 127
-15
15
%
%
FNP, FNN differential gain (AN)
F = 0.67 x fc, boost = 0 dB
1.6
2.4
VN
FDP, FDN differential gain (AD)
F = 0.67 x fc, boost = 0 dB
0.8 AN
1.2 AN
VN
Frequency boost @ fc = 12 MHz
DACS = 127
Boost accuracy
@ 6 dB, DACS = 37
-1
+1
dB
@ 9 dB, DACS = 67
-1.25
+1.25
dB
-1.5
+1.5
dB
-2
+2
%
+3
0/0
1.5
0/0
13
@ 13 db, DACS
= 127
MO/Emboss mode group delay
variation
fc = 4 to 12 MHz
F = 0.2 fe to fe, boost = 0 and 3 dB
FNP, FNN; FDP, FDN
fc = 41012 MHz
F= fc to 1.75 fc, boost = 3 dB
Filter Output THD @ 1 Vpp
F = 0.67 fC
fc = 4 to 12 MHz
Filter differential input resistance
2
Normal
-
-3
kQ
3
Filter differential input capacitance
differentiated output
differentiated output
normal output
normal output
7
fC
fc
fe
fc
= 12 MHz, boost = 0 dB
2.6
mVRms
= 12 MHz, boost = 13 dB
5.6
mVRms
2
mVRms
3.6
mVRms
0.5
rnA
= 12 MHz, boost = 0 dB
= 12 MHz, boost = 13 dB
Filter output offset voltage
Rx resistance
pF
BW = 100 MHz, Rs = 50Q
Filter output sink current
Filter output source current
Filter output resistance
Rx pin voltage
Q
140
Low-Z
Output noise voHage
dB
200
mV
200
rnA
Q
2
Single ended
Ta = 27°C
Tj = 127°C
1% fixed value
10-52
600
800
mV
mV
12.1
kQ
SSI 33P3733/34
8-26.5 Mbit/s Read Channel
TIME BASE GENERATOR CHARACTERISTICS
PARAMETER
CONDITIONS
FREF input range
MIN
NOM
TOUT = 1/FOUT
Loop acquisition time
= 30 J.lS
M counter range
N counter range
VCO center frequency
period
TVCO
VCO dynamic range
VCO control gain
KVCO
Phase detector gain
KD
UNIT
20
MHz
75
MHz
-TBD
goal.
= 200
+TBD
goal
= 200
ps
(rms)
2
255
8
FOUT frequency range
FOUT jitter
MAX
2
127
0.85 TO
1.15 TO
ns
-2V $; TFLT - TFLT $; +2V
FOUT=36 MHz
RR = 12.1 kO
±25
±45
%
(Oi = 27tlTVCO
-2V $; TFLT - TFLT $; +2V
0.12(Oi
0.24 (Oi
rad/(V-S)
KD =[12.5/(RR+0.4)] x (0.656
x IDAC + 3.38) x 10-6
0.83 KD
1.17 KD
Alrad
Fvco = [12.5/(RR + 0.4)]
x [(0.622 x IDAC)+ 4.27] MHz
TFLT - TFLT = TBD
Fvco< 24 MHz
Fvco =[12.5/(RR + D.4)] x [(D.7 x
IDAC) + 1.4] MHz
KVCO x KD product accuracy
-28
RR resistor range
+28
FREF input low time
20
FREF input high time
20
%
kn
12.1
ns
ns
FOUT rise time
1D% to 9D% points, CL:>. 2D pF
8
ns
FOUT fall time
9D% to 1D% points, CL :>.2D pF
8
ns
DATA SYNCHRONIZER CHARACTERISTICS
READ MODE
Read clock rise time
TRRC
10% to 90% points
CL$;15pF
8
ns
Read clock fall time
TFRC
90% to 10% points
CL $; 15 pF
8
ns
60
%
RRC duty cycle
SDO out set-up
and hold time
TRD
Except during re-sync
40
During re-sync
40
%
10
ns
TSDS, TSDH
1/3 or 1/4 cell delay
TD =TVCO/2
0.8TD
10-53
1.2TD
ns
II
SSI33P3733/34
8-26.5 Mbit/s Read Channel
DATA SYNCHRONIZER CHARACTERISTICS (continued)
WRITE MODE (551 33P3734)
PARAMETER
Write MO data pulse width
TWD
CONDITIONS
MIN
1.5V, CL::; 15pF
Tvco
cO.5
NOM
MAX
UNIT
Tveo
+0.5
ns
Write MO data rise time
TRWD
10% to 90% points, CL ::; 15 pF
8
ns
Write MO data fa/l time
TFWD
90% to 10% points, CL ::; 15 pF
8
ns
EARLY, LATE set-up time
TSEL
5
ns
EARLY, LATE hold time
THEL
5
ns
0.8 to 2V
CL::; 15 pF
10
ns
2 to 0.8V, CL ::;15 pF
8
ns
-1
1
ns
Fveo = [12.5/(RR + 0.4)]
x [(0.622 x IDAC) + 4.27] MHz
TVCO = 1/FVCO,
DFLT - DFLT = TSD
RR = 12.1 kO
Fveo < 24 MHz
Fvco = [12.5/(RR + 0.4)] x
[(0.7 x IDAC) + 1.4] MHz
0.85 TO
1.15 TO
ns
VCO dynamic range
-2V ::; DFLT - DFLT ::; +2V
±25
±45
%
VCO control gain
wi = 27t1TVCO
-2V ::; DFLT- DFLT +2V
0.12 wi
0.24 wi
rac:V(V-S)
0.83 KD
1.17 KD
Nrad
-2
+2
ns
-0.75
+0.75
ns
Write MO data input
rise lime
TRWC
Write MO data input
fa/l time
TFwe
Write MO data jitter
24 Mbit/s, 3T
DATA SYNCHRONIZATION
VCO center frequency
period
Phase detector gain
TVCO
KVCO
KD
VCO phase restart error
Idle mode = 1 x KD
Read mode = 3 x KD
Read mode after gain shift =
1 x KD
KD = [12.5/(RR + 0.4)]
x (0.656 x IDAC + 3.38)
x 10·s
Fvco
= 72 MHz
Decode window center accuracy
Decode window width
TVCO
- 0.75
10-54
ns
SSI33P3733/34
8-26.5 Mbit/s Read Channel
WINDOW SHIFT CONTROL
Window shift magnitude is set by the value in the Window Shift (WS) register. The WS register bits are as
follows:
BIT
0
NAME
FUNCTION
WSO
1
WS1
2
WS2
3
WS3
4
WSD
Window shift direction. O=early, 1=late
5
WSE
Window shift enable
6
TDACO
Used to route signals to DAC test point
7
TDAC1
Used to route signals to DAC test point
The window shift magnitude is set as a percentage of the full decode window, in 2% steps. This results in
a window shift capability of ± 30% of the full decode window. The tolerance of the window shift magnitude
is ± 30%. Window shift should be set during Idle mode or Write mode.
WS3
WS2
WS1
WSO
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
10-55
Shift Magnitude
No shift
2% (minimum shift)
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
24%
26%
28%
30% (maximum shift)
II
SSI 33P3733/34
8-26.5 Mbit/s Read Channel
DATA SYNCHRONIZER CHARACTERISTICS (continued)
WRITE PRECOMP CONTROL (SSI 33P3734)
Write precomp rnagnitude is set by the value in the Write Precomp (WP) register. The WP register bits
are as follows:
BIT
NAME
0
WEO
1
WEi
2
WE2
3
WPE
4
WLO
5
WL1
6
WL2
7
-
FUNCTION
Write precomp enable
Not used
The write precomp magnitude is calculated as:
TPE = n x 0.04 x TREF
where n = precomp magnitude scaling factor as shown below. The magnitude of early precomp is set by
the WEx bits. The magnitude of late precomp is set by the WLx bits. TREF is the period of the reference
frequency provided by the internal time base generator.
WE2
WEi
WEO
Precomp Magnitude
Scaling Factor
W[2
WL1
WLO
1
1
1
No precomp
1
1
1
1
1
0
1X
1
1
0
1
0
1
2X
1
0
1
1
0
0
3X
1
0
0
0
1
1
4X
0
1
1
0
1
0
5X
0
1
0
0
-0
0
1
6X
0
0
1
0
0
7X (maximum)
0
0
0
--
10-56
SSI33P3733/34
8-26.5 Mbit/s Read Channel
RRC
/4----TORC ----~
soo
15VTFRC~ ~
TRRC=i
-----~T:si~s:f--1-.5V---FIGURE 5: SOO Read Timing
EWDATA
J.SV
EARLY/ _ _ _ _ _ _ _----'
LATE
TSEL
THEL
FIGURE 6: EWRO and EWOATA Write Timing
10-57
II
SSI 33P3733/34
8-26.5 Mbit/s Read Channel
DATA SYNCHRONIZER CHARACTERISTICS (continued)
TABLE 4: Multiplexed Test Point Signal Selection
MTPE
TMS1
TMSO
MTP1
MTP2
MTP3
0
X
X
OFF
OFF
OFF
1
0
0
VCOREF
ORO
DSREF
1
0
1
RD
DOUT
COUT
1
1
0
-
1
1
1
SET
RESET
COUT
Output of the pulse qualifier clock circuit
DOUT
Output of the pulse qualifier data comparators
DSREF
Output of the time base generator
NCTR
Ncounter output of the lime base generator
RD
RESET
Read MO data output from the pulse qualifier
Output of the negative threshold comparator
SET
Output of the positive threshold comparator
TABLE 5: DACOUT Test Point Signal Selection
TDAC1
TDACO
0
0
DAC MONITORED
Filter Ic DAC
0
1
Qualifier threshold DAC (VTH)
1
0
Window shift DAC
1
1
Write precomp DAC
10-58
NCTR
COUT
WRITE
MODE
READ
MODE
u----u
PWRON
RG
READ
MODE
TRACK
FOLLOW
J----U----]
I
L
I
I
WG
n
MOEG
nI
Inl
I I
I
I
n
n
n
n
n
DEVICE~,-------ri-;r-----~,,~-----T~~-----.r-n------'r-m-----~~~------~~------n-o
MODE •
~------~~------~~------~~------~~------~~------~~~-----=~~-----¥~
SERIAL - - - - - + - - - - - - - - - - - - - - - - - - i
PORT
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u.
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0::
27
39
OIF+
38
DIF-
3
37
VPA1
4
36
DOUT
35
COUT
34
VPA2
33
ROT
AGND2
6
ROT
NlC
7
N/C
N/C
8
32
Nle
REFClK
NlC
9
31
REF ClK
DGND
N/C
10
30
DGND
34P5531
i'l5WN
11
29
VPD
FlTR
WG
12
28
FlTR
IREF
N/C
13
27
IREF
VPD
WG
50 49 48 47 46 45 44 43 42 41 40
10
2
14 15
16 17 18 19 20 21 22 23 24 25 26
UJ
II:
52-Lead QFP
52-Lead QFP
CAUTION: Use handling procedures necessary
1293 - rev.
10-61
for a static sensitive component.
II
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(1)CD~
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EGC
VEGC
...-------'Q veo cu< (TPl
BYP
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mrn
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-
L::J I I
1 "ooh~;~' 14
J
~
~
~
~
~
~
~
~
• 34P5531 only
BLOCK DIAGRAM
CAUTION: Use handling procedures necessary
for a static sensitive com ponent.
I
T
~~,
I
'< C -C
::::JCDen
(')-en
:::rCDW
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...CD
SSI 34P553/5531
Pulse Detector &
Data Synchronizer
CIRCUIT OPERATION
PULSE DETECTOR SECTION
READ MODE
The SSI34P553/5531 enters into the Read mode when
the WG pin is pulled low. In the Read mode, the SSI
34P55315531 provides amplification and pulse level
qualification of the signal applied to the input pins of the
AGC amplifier.
AGC AMPLIFIER
An amplified head output signal is AC coupled to the IN+
and IN- pins of the AGC amplifier. To control the gain of
the AGC amplifier, the signal at the DIN± pins is fullwave rectified and amplified. The resulting voltage is
compared to the voltage level present at the AGC pin. If
the voltage level is higher than the AGC pin reference
level, the 5S1 34P55315531 will enter into an Attack
mode. If ft is lower than the AGC pin voltage the device
will enter into a Decay mode.
Attack Mode. The SSI 34P55315531 contains a dual
rate attack charge pump that is controlled by the instantaneous level at DIN±. When the voltage from the full
wave rectifier exceeds the AGC pin voltage by greater
than 125%, a Fast Attack mode is entered. During fast
attack, 1.4 mA of current is supplied to the network on
the BYP pin. When the full wave rectifier voltage exceeds the AGC pin voltage by 100 to 125%, the Slow
Attack mode is entered. During slow attack the charge
current supplied to the BYP pin is 0.18 mAo This dual
rate charge pump allows the AGC to recover rapidly
during write to read transitions while minimizing distortion once the AGC amplitude is within range.
Decay Mode. Two intemally controlled Decay modes
.are provided by the SSI34P553/5531. Upon a swftch to
Write mode, the device holds the gain at its last value
and the AGC inputs are swftched to low impedance.
When the device is switched back from write to read, the
gain remains held and the AGC inputs remain in a low
impedance state for 0.91J.S. At this time, if the new gain
required is more than the held value the device enters
into the Decay mode. A fast decay current of 0.12 mA
is automatically switched on for a period of 0.91J.S. After
0.9 IJ.S the device will sink a steady state slow decay
current of 4.5 ~ (reference Figure 7.)
AGC Level Control. The AGC level is controlled by the
voltage presented on the AGC pin. The AGC pin is
intemally biased at approximately 2.3V which sets the
signal at the DiNt pins to 1.0 Vpp under nominal
conditions. The voltage at the AGC pin can be externally
controlled by connecting a resistor between the AGC pin
and either VPA1 or AGND1. When a resistor is connected from AGC to VPA1 the voltage on the AGC pin
can be increased (Figure 1a). When a resistor is
connected from AGC to AGND1 the voltage on the AGC
pin can be decreased (Figure 1b). The new DIN± input
target level is nominally (VAGC -0.75)"0.64 Vpp. The
output of the AGC amplifier has a maximum swing of 3.0
Vpp that can be controlled using the AGC pin. The 3.0
Vpp swing supports the use of extemal filters that have
up to 6 dB of loss. A multi-pole Bessel or an equiripple
linear phase filter is typically used for fts linear phase or
constant group delay characteristics.
5V
(1 B r J RAGC
int
Rex!
V
V
VNlC _
VNlC- (5-V) Rlnt .V
VRe",
Rint + Rext
Rlnt+ Rext
V _ VoHage at AGC pin with pin o]>8n (2.3V nominal)
Rint _ AGe pin input impedance (2.5 Kn typical)
Rext _ External Resistor
FIGURES 1A & 1B: AGC Voltllge
Thegain of the AGC amplifier is directly controlled by the
voltage at the BYP pin (VBYP) or the VEGC pin as
shown in Figure 2. The AGC amplifier has open collector
outputs that can sink up to 4.0 mA of current. For correct
operation over the gain range each output should be
pulled up to VPAI through a 340 n resistor as shown in
Figure 3.
10-03
GainVN
80
45
4
I
2.5
VSYP(VollS)
FIGURE 2: AGC Gain
OUT.
OUT-
~
DIN-
E
DIN>
FIGURE 3: AGC FIHer
SSI34P553/5531
Pulse Detector &
Data Synchronizer
PULSE QUALIFICATION
The SSI 34P553/5531 uses both amplitude and time
qualification to digitize the incoming data pulses. In the
amplitude channel the signal is sent to a hysteresis
comparator. A hysteresis trip level is externally set
such that only pulses that exceed the required signal
level will trip the comparator. This prevents false qualification of baseband noise. The hysteresis trip level
can be either a fixed level or a fraction of the DIN±
voltage level.
Hysteresis Level. A fixed hysteresis level can be set
by applying a DC voltage to the HYS pin. This is a
simple method for hysteresis control but it does not
compensate well for internal variances from device to
device. A more effective approach is to feed forward a
percentage of the voltage level at the DIN± pins. This
approach is accomplished by using a filter/divider
network .between the LEVEL and HYS pins. The
LEVEL pin output voltage is a rectified and amplified
version of the voltage level applied to the DIN± pins.
The gain in this circuit is set so that a 1· Vpp signal
applied to DIN± will result in a 1 Vpk (typical) output
signal at the LEVEL pin. An external capacitor to
AGND1 should be used on the LEVEL pin to maintain
a DC level. An external voltage divider can be connected
between the LEVEL pin and AGND1 to provide the
hysteresis programming voltage to the HYS pin. The
HYS pin voltage determines the percentage of the
DIN± input signal that will trip the hysteresis comparator of the SSI 34P553/5531. The transfer function 01
the HYS pin for setting the threshold percentage is:
Hysteresis Threshold = 0.41 x VHYS
where VHYS is the voltage applied to the HYS pin. For
example, with a 1.0 Vpp signal at DIN± the LEVEL pin
output will be 1.0 Vpk. Using a 50% resistor divider
between LEVEL and AGND1 would result in a HYS pin
voltage of 0.5V and that would produce a hysteresis
threshold of 0.20V in both the positive and negative
direction. This translates to a hysteresis threshold
percentage of 40% of DIN±.
Because the SSI 34P553/5531 circuits are internally
biased 10 the same levels, the technique of feeding
forward the LEVEL pin voltage helps to offset process
related internal tolerance variations. In addition, the
feed forward technique speeds up transient recovery
by allowing qualification of input pulses while the AGC
is still settling, such as during write to read recovery or
head change recovery. Care should be taken in
selecting the hysteresis level time constant so that
pattern induced low amplitude signals are not missed.
The SSI 34P553/5531 has a built in minimum of ±50
mV threshold for level qualification even when the HYS
pin is grounded. This prevents false triggering due to
baseband noise during a DC erase gap.
The outputs of the hysteresis comparator are the "0"
inputs of the D-type flip-flop. One side of the hysteresis
comparator outputs is provided as the DOUT pin test
point. The DOUT pin can be monitored by connecting
a 3 to 6 kn resistor to AGND2. When the DOUT pin is
not used, it can be pulled up to VPA1 to save power.
In the time channel the signal is differentiated to transform signal peaks to zero crossings which are detected
and used to trigger a bi-directional one-shot. The oneshot output pulses are used as the clock input of the 0
flip-flop. The COUT pin provides the one-shot output
for test purposes. It also requires an external 3 to 6 KQ
pull-down resistor for testing.
The differentiatorfunction is accomplished by an external network between the DIF+ and DIF- pins. The
transfer function from DIN± to the comparator input
(not DIF±) is:
Av
-2000Cs
LCs 2 +C(R+92)s+1
where: C, L, R are external passive components
20 pF < C < 500 pF
s=jro = j27t1
During normal operation, the time channel clocks the 0
flip-flop on every positive and negative peak of the
DIN± input. The 0 input to the flip-flop only changes
state when the DIN± input exceeds the hysteresis
comparator threshold opposite in polarity to the previous threshold exceeding peak.
The time channel, then, determines signal peak timing
and the amplitude channel determines validity by
blocking signal peaks that do not exceed the hysteresis
comparator threshold. The delays in each of these
channels to the 0 flip-flop inputs are well matched. The
o flip-flop output triggers a one-shot that sets the ROO
output pulse width.
10-64
SSI34P553/5531
Pulse Detector &
Data Synchronizer
WRITE MODE
tinuously enabled, thus maintaining both phase and
frequency lock. By acquiring both phase and frequency
lock to the crystal reference oscillator and utilizing a
zero phase restart technique, false lock to DLYO DATA
is eliminated.
In Write Mode the SSI 34P553/5531 Pulse Detector
section is disabled and preset for the following Read
Mode. The digital circuitry is disabled, (ROO pin held
high), the input AGC amplifier gain is held at its previous value and the AGC amplifier input impedance is
reduced.
The phase detector incorporates a charge pump in
order to drive the loop filter directly. The polarity and
width of the output current pulses correspond to the
direction and magnitude of the phase error. Figure 4
depicts the average output current as function of the
input phase error (relative to the VCO period.)
Holding the AGC amplifier gain and reducing input
impedance shortens system Write to Read recovery
times.
The lowered input impedance improves settling time
by reducing the time constant of the network between
the SSI 34P553/5531 and a head preamplifier such as
the SS134R1203R. Write to read timing is controlled to
maintain the reduced impedance for 0.91J.S before the
AGC circuitry is activated. Coupling capacitors should
be chosen with as Iowa value as possible consistent
with adequate bandwidth to allow more rapid settling.
DATA SYNCHRONIZER SECTION
The SSI 34P55315531 is designed to perform data
synchronization in rotating memory systems which utilize a 1, 7 RLL and MFM encoding format. In the Read
Mode the SS134P553/5531 performs Data Synchronization. The interface electronics and architecture of the
SSI 34P553/5531 have been optimized for use as a
companion device to the WD 42C22 controllers.
The SSI 34P553/5531 can operate with data rates
ranging from .6 to 1.6 MbiUs. This data rate is established by a single 1% extemal resistor, RR, connected
from pin IREF to VPA2. This resistor establishes a
reference current which sets the VCO center frequency, the phase detector gain, and the 1/4cell delay.
The value of this resistor is given by:
RR= 5.97 -178(kQ)MFM
DR
.
RR= 7.96 -178(kQ)17
DR'
,
Where: DR
=
Data Rate in Mbitls
An external TTL compatible reference may be applied
to REFCLK
The SSI 34P553/5531 employs a Dual Mode Phase
Detector: Harmonic in the Read Mode and Non-Harmonic in Write and Idle Modes. In the Read Mode the
Harmonic Phase Detector updates the PLL with each
occurrence of a DLYD DATA pulse. In the Write and
Idle Modes the Non-Harmonic Phase Detector is con-
The READ GATE (RG), and WRITE GATE (WG),
inputs control the device mode as described in Table 1.
RG is an asynchrouous input and may be initiated or
terminated at any position on the disk. WG is also an
asynchronous input, but should not be terminated prior
to the last output Write Data pulse.
READ OPERATION
The Data Synchronizer utilizes a fully integrated fast
acquisition PLL to accurately develp the decode window. Read Gate, RG, initiates the PLL locking sequence and selects the PLL reference input; a high
level (Read Mode) selects the Read Data input and low
level selects the crystal reference oscillator.
In the Read Mode the rising edge of DLYO DATA
enables the Phase Detector while the falling edge is
phase compared to the rising edge of the VCO. As
depicted in Figure 5, DLYO DATA is a 1/4 cell wide
(TVCO/2) pulse whose leading edge is defined by the
leading edge of Read Data. VCO is generated from the
rising edges of the VCO clock. By utilizing a fully
integrated symmetrical VCO running at the code rate,
VCO is insured to be accurate and centered symmetrically about the falling edges of DLYD DATA. The
accuracy of the 1/4 cell delay only affects the retrace
angle of the phase detector and does not influence the
accuracy of VCO.
Shifting the symmetry of the VCO clock effectively
shifts the relative position of the DLYO DATA pulse
within the decode window. This powerful capability
easily facilitates defect mappings, automatic calibration, window margin testing, error recovery, and systematic error cancellation. For enhanced disk drive
testability and error recovery, decode window control is
provided via a IlP port (WSL, WSD, WSO, WS1) as
described in Table 2. In application not utilizing this
feature, WSL should be left open or connected to
VPA2, while WSD, WSO, and WS1 can be left open.
10-65
II
•
SSI 34P553/5531
Pulse Detector &
Data Synchronizer
In Non-Read Modes, the PLL is locked to REFCLK.
This forces the vce to run at a frequency which is very
close to that required for tracking actual data and thus
minimizes the associated frequency step during acquisition. When RG transitions, the vce is stopped momentarily, then restarted in an accurate phase alignment with the next PLL reference input pulse. By
minimizing the phase alignment in this manner, the
acquisition time is substantially reduced.
Window shifts in the range of ±5% to±20% of TVCe
are easily programmed by latching the appropriate
control word into the. Window Shift Register with the
WSL pin. Shifts in the positive or negative directions
result in early or late decode windows respectively, as
depicted in Figure 6. Additionally, for small systematic
error cancellation, a resistor; R, connected from either
RS (Early) or RF (Late) to ground wiil provide analog
control over the decode window. The magnitude of this
shift, TSA'is determined by:
POWER DOWN MODE
A Power Down mode is provided to reduce power
usage during the idle periods. Taking PDWN low
causes the device to go into complete shutdown.
TSA=o.25TVce(1 3260+R)
5950+R
Where: R is in n
Pins RF and RS are intended to .be used as a trim and
should be restricted to ±3% window shifts. They-can be
used in conjunction with the digital control port.' .
MODE CONTROL
The SS134P553/5531 Circuit mode is controlled bythe
PDWN , HOLD, RG, and WG pins as shown in Table 1~
TABLE 1: Mode Control
FiOCi5
WG
RG
0
0
1
1
Read Mode vce Locked toXTAL
0
1
1
1
Read Mode vce Locked to Read Data
0
X
0
1
Read Mode AGC gain held constant"
1
0
X
1
Write Mode AGC gain held constant"
Input impedance reduced
X
X
X
0
Power SI:lUtdown mode
PDWN1
• AGC gain Will dnft at a.rate determined by BYP capacitor and Hold mode leakage current.
10-66
SSI34P553/5531
Pulse Detector &
Data Synchronizer
TABLE 2: Decode Window Symmetry Control
Ts, NOMINAL WINDOW SHIFT
WSD
WS1
WSO
+TS3
0
0
0
+TS2
0
0
1
+TS1
0
1
0
0
0
1
1
0
-TS3
1
0
-TS2
1
0
1
-TS1
1
1
0
0
1
1
1
AVERAGE
OUTPUT CURRENT
AVERAGE
OUTPUT CURRENT
10
,
-21t I
'" ERROR
"'ERROR
-10
a) HARMONIC MODE
b) NON-HARMONIC MODE
Note 1) 10 is the magnitude of the charge pump current.
2) Phase error is relative to the VCO period
FIGURE 4: Phase Detector Transfer Function
10-67
1/1
SSI 34P553/5531
Pu Ise Detector &
Data Synchronizer
01010101011101010101011101010101
READ DATA
mm
-----------~
PLL_REF
-----------'m
,-------------------, , - - - - - - - - - -
veo
PHASE DET
ENABLE _ _ _ _ _ _ _ _ _---'
FIGURE 5: Data Synchronization Waveform Diagram
READ
DATA
1100
I
0
I
0
I
1
U
I
0
I
REAO
DATA
I
0
I
0
ROO
I
1
I
0
I
U
READ
DATA
RliO
PLL_REF
PLL_REF
VCO
veo
VCO
(DECODE
NINOOW)
(DECODE
WINDOW)
(DECODE
WINDOW)
(a) EARLY
I
0
I
0
I
1
U
PLL_REF
(b) NORMAl
FIGURE 6: Decode Window
10-68
(e) LATE
I
0
I
SSI34P553/5531
Pulse Detector &
Data Synchronizer
PIN DESCRIPTION
NAME
TYPE
VPA1
VPA2.
I
I
I
Analog (+5V) supply pin for data synchronizer block.
AGND1
DESCRIPTION
Analog (+5V) power supply for pulse detector.
Analog ground pin for pulse detector block.
AGND2
I
Analog ground pin for data synchronizer block.
VPD
I
Digital (+5V) power supply pin.
DGND
I
Digital ground pin.
IN+,IN-
I
Analog signal input pins.
OUT+,OUT-
0
Read path AGC Amplifier output pins.
DIN+, DIN-
I
Analog input to the hysteresis comparator, and differentiator.
CIN+, CIN-
I
Analog input to the clock comparator, differentiator. (34P5531 only)
DIF+, DIF-
I/O
Pins for external differentiating network.
COUT
0
Test point for monitoring the flip-flop clock input. A 5 kQ pull down resistor
is required. When not in use, leave open orpull upto VPA1 to save power.
DOUT
0
Test point for monitoring the flip-flop D-input. A 5 kQ pull down resistor is
required. When not in use, leave open or pull up to VPA1 to save power.
BYP
I/O
An AGC timing capacitor or network is tied between this pin and AGND1.
AGC
I
0 _
LEVEL
Reference input voltage for the read data AGC loop.
0
Output from fullwave rectifier that may be used for input to the hysteresis
comparator.
HYS
I
Hysteresis level setting input to the hysteresis comparator.
TRKAA
0
Full wave rectifier output. This output has the same DC level as the LEVEL
pin, i.e.,~O.3VwithnoACsignal and~ WOP with a Wpp AC signal at DIN+/
DIN-.
HOLD
I
TTL compatible pin that holds the AGC gain when pulled low.
EGC
I
External Gain Control. This is a TTL input pin that allows the AGC gain to
be controlled by either BYP or the VEGC pin voltage. When EGC is high,
the AGC gain is controlled by VEGC and the internal charge pump to BYP
is disabled.
VEGC
I
The voltage at this pin is used to control the AGC gain when the EGC pin
is held high.
RDO
0
Read Data Output. This is the TTL output from the pulse detector. This
signal may be fed directly into the RDT input.
IREF
I
Timing program pin: the VCO center frequency, Phase Detector Gain and
the 1/4 cell delay are a function of the current source into pin IREF. The
current is set by an external resistor, RR connected from IREF to VPA2.
FLTR
I/O
Filter pin: the phase detector output and VCO input node. The loop filter
is connected to this pin.
10-69
I
SSI 34P553/5531
Pulse Detector &
Data Synchronizer
PIN DESCRIPTION
(continued)
NAME
DESCRIPTION
TYPE
SRD
0
Synchronized Read Data: read data that has been re-synchronized to VCO clock.
WSD
I
Window Symmetry Direction: controls the directions of the optional window symmetry shift. Pin WSD has an internal resistor pull-up.
WSO
I
Window symmetry control bit: a low level introduces a window shift of 5% TORC
(read reference clock period) in the direction established by WSD pin. WSO has an
internal resistor pull-up.
WS1
I
Window Symmetry Control bit: a low level introduces a window shift of 15% TORC
(read reference clock period) in the direction established by WSD. A low level at both
WSO and WS1 will produce the sum of the two window shiftS. Pin WS1 has an
internal resistor pull-up.
WSl
I
Window Symmetry latch: used to latch the input window symmetry control bits
WSD, WSO, WS1 into the internal DAC. An active low level latches the input bits.
RF,RS
I
WINDOW SYMMETRY ADJUST PINS: Provides analog control over the decode
window symmetry; typically used to null out any window symmetry offset. A resistor
connected from either RF or RS to AGND will provide magnitude and direction
control. They can be used in conjunction with the digital control port WSD, WSO,
WS1.
RG
I
Read gate: selects the Pll reference input and initiates the Pll synchronization
sequence. A high level selects the internal RD± inputs. A low level selects the crystal
reference oscillator, Pin RG has an internal resistor pullup.
WG
I
Write Gate: enables the Write mode. Pin WG has an internal resistor pullup.
VCOClK
0
VCO ClK: An open emitter ECl output test point. Two external resistors are required
to perform this test. They should be removed during normal operation for reduced
power dissipation.
RDT
I
Read Data input. This TTL input comes from the RDO output of the pulse detector.
This Signal is active low.
PDWN
I
Power Down input. When this input is low, the chip enters low Power mode. This
pin has an internal pullup resistor, and may be left open or tied high if not used.
REFClK
I
Reference Clock. This is a TTL input at the code rate that is used as the reference
for the VCO in Idle mode.
VCO
0
VCO output. This is the VCO signal converted to a TTL level.
Pll_REF
0
Pll Reference Test Point. In Write and Idle modes, this is the reference oscillator
signal. In Read mode, it is the delayed read data (ORO) signal. This is an ECl level
output. Pll_REF can be compared to VCOClK to see the window centering
accuracy.
10-70
SSI34P55315531
Pulse Detector &
Data Synchronizer
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, 4.5V
~
VPA 2 ~ 5.5V, 25°C
~
Tj
~
135°C, 1.2 MHz ~ 1ffVCO ~ 2.4 MHz.
ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may cause permanent damage to this device.
PARAMETER
RATING
5V Supply Voltage, VPA1, VPA2, VPD
6.0V
Pin Voltage (Analog pins)
-0.3 to VPA1, 2 + 0.3 V
Pin Voltage (All others)
-0.3 to VPD + 0.3 V or +12 mA
Storage Temperature
-65 to 150°C
Lead Temperature (Soldering 10 sec.)
260 °C
RECOMMENDED OPERATING CONDITIONS
Currents flowing into the chip are positive.
PARAMETER
CONDITIONS
MIN
NOM
Supply Voltage (VPA 1, 2 & VPD)
4.5
5.0
Tj Junction Temperature
25
MAX
UNIT
5.5
V
135
°C
NOM
MAX
UNIT
POWER SUPPLY
PARAMETER
CONDITIONS
IVPA1, 2 Supply Current
IVPD
Outputs unloaded
PDWN= high or open
110
143
mA
PDWN= low
Outputs unloaded
44
57
mA
Ta = 25°C, outputs unloaded
PDWN= high or open
550
790
mW
PDWN = low
Outputs unloaded
220
315
mW
Pd
Power dissipation
10-71
MIN
I
SSl34P553/5531
Pulse Detector &
Data Synchronizer
ELECTRICAL SPECIFICATIONS (continued)
LOGIC SIGNALS
PARAMETER
MIN
CONDITION
NOM
MAX
UNIT
V
VIL
Input Low Voltage
-0.3
0.8
VIH
Input High Voltage
2.0
VCC+0.3
ilL
Input Low Current
VIL = O.4V
-0.4
ilL
WG Input Low Current
VIL = O.4V
-0.8
IIH
Input High Current
VIH = 2.4V
100
~
VOL
Output Low Voltage
IOL=4.0 rnA
0.5
V
VOH Output High Voltage
10H = -400~
VOHT Test Point
2620 to VPD
4020 to GND
VPD= 5.0V
VOHT-VPD
Output High Level
PLL_ REF, VCOCLK
VOLT Test Point
Output Low Level
PLL_REF, VCOCLK
* Output load
IS
rnA
V
2.4
2620 to VPD
4020 to GND
VPD = 5.0V, VOHT - VPD
V
rnA
-0.85
V
-1.75
V
a 4K resistor to 5V and a 10 pF capacitor to DGND.
MODE CONTROL
Enable to/from PDWN
Transition Time
Settling time of external
capacitors not included,
PDWN pin high to/from low
Read to Write TranSition Time
WG pin low to high
Write to Read
Transition Time
WG pin high to low
AGC setting not included
HOLD On to/from HOLD Off
Transition Time
HOLD pin high to/from low
0.4
RG Time Delay
0.9
20
J.IS
1.0
1.6
J.IS
J.IS
1.0
Il s
100
ns
READ MODE (WG is low)
AGC AMPLIFIER
Unless otherwise specified, recommended operating conditions apply. Input signals are AC coupled to IN±.
OUT± are loaded differentially with 3400 x 2 to VPA 1, and each side is loaded with < 10 pF to AGND1, and AC
coupled to DIN±. A 0.1 JlF capacitor is connected between BYP and AGND1. AGC pin is open.
Gain Range
1.0 Vpp :s; (OUT+) - (OUT-)
:S;3.0 Vpp
4
80
VN
AGC Input Range
AGC output = 1Vpp differential
25
250
mVpp
Output Offset Voltage Variation
Over entire gain range
-500
+500
mV
Maximum Output
VoHage Swing
Set by BYP or VEGC pin
3.0
10-72
Vpp
SSI34P553/5531
Pulse Detector &
Data Synchronizer
AGC AMPLIFIER (continued)
PARAMETER
Differential Input Resistance
CONDITION
(IN+) - (IN-) = 100 mVpp
2.5 MHz
MIN
NOM
MAX
UNIT
4
5.4
7.5
kQ
5
10
pF
(a)
Differential Input Capacitance
r-----
(IN+) - (IN-) = 100 mVpp
@2.5MHz
Single Ended Input
WG = low, IN+ or IN-
Impedance
WG = high, IN+ or IN-
2
Input Noise Voltage
Gain set to maximum, Rs = 0
BW= 15 MHz
Bandwidth
-3 dB bandwidth at
maximum gain
12
2.7
4
kQ
160
250
Q
5
15
nV/,1Hz
MHz
mA
OUT+ & OUT- Pin Current
No DC path to AGND1
2.5
CMRR (Input Referred)
(IN+) = (IN-) = 100 mVpp
@ 5 MHz, gain set to max
40
dB
PSRR (Input Referred)
VPA1, 2 = 100 mVpp
@ 5 MHz, gain set to max
30
dB
(DIN+) - (DIN-) Input
Swing VS. AGC Input
(DIN+) - (DIN-) = (VAGC - K1) • K2
4.0
25 mVpp ~ (IN+) - (IN-)
250 mVpp, HOLD = high,
0.5 Vpp ~ (DIN+) - (DIN-)
~ 1.5 Vpp
~
K1
0.5
0.8
0.95
V
K2
0.54
0.64
0.74
Vpp/V
5.0
%
2.3
2.6
V
25 mVpp ~ (IN+) - (IN-)
250 mVpp
(DIN+) - (DIN-) Input Voltage
Swing Variation
~
AGC Voltage
AGC open
2.0
1.8
2.5
3.8
kQ
Slow AGC Discharge Current
(DIN+) - (DIN-) = OV,
AGC pin open
2.8
4.5
6
~
Fast AGC Discharge Current
Starts at 0.9 JlS after WG
goes low, stops at 1.8 JlS
after WG goes low
AGC Pin Input Impedance
mA
0.12
BYP Leakage Current
HOLD = low
-0.2
+0.2
~
Slow AGC Charge Current
(DIN+) - (DIN-) = 0.563 VDC,
AGC pin open
-0.11
-0.18
-0.25
mA
Fast AGC Charge Current
(DIN+) - (DIN-) = 0.8 VDC,
AGC pin open
-0.9
-1.4
-1.9
mA
Fast to Slow Attack
Switchover Point
[( DIN+)- (DIN -)]
[( DIN+)- (DIN- l]FINAL
10-73
125
%
II
SSI34P553/5531
Pulse Detector &
Data Synchronizer
ELECTRICAL SPECIFICATIONS (continued)
AGC AMPLIFIER
(continued)
PARAMETER
CONDITION
Gain Decay Time (Td)
(IN+) - (IN-) = 250 mVpp to
125 mVpp@0.6 MHz,
(OUT+) - (OUT-) to 90% final
value
MIN
(IN+) - (IN-) =50 mVpp to
25 mVpp at 0.6 MHz
(OUT+) - (OUT-) to 90%
final value
Gain Attack Time
190
WG = high to low
(IN+) - (IN-) = 250 mVpp
@ 0.6 MHz, (OUT+) - (OUT-)
to 110% final value
NOM
MAX
UNIT
100
180
~
300
550
~
8
15
~
160
250
n
WRITE MODE (WG is high)
Single Ended Input
Impedance (Each Side)
IN+ or IN-
I
HYSTERESIS COMPARATOR
Unless otherwise specified, recommended operating conditions apply. Input (DIN+) - (DIN-) is an AC coupled,
1.0 Vpp, 0.6 MHz sine wave. 0.5 VDC is applied to the HYS pin. WG pin is low.
Input Signal Range
1.5
Vpp
5.5
8
kn
4
8
pF
1.5
2.75
4
kQ
Differential Input Resistance
(DIN+) - (DIN-) = 100 mVpp
@0.6MHz
Differential Input Capacitance
(DIN+) - (DIN-)
@0.6MHz
Single Ended Input
Impedance (Each Side)
DIN+ or DIN-
Level Gain
0.6 Vpp < (DIN+) - (DIN-)
< 1.5 Vpp, 10K between
LEVEL and AGND
0.80
1.00
1.25
VNpp
Slope of Level Gain
Calculated from
0.6 Vpp < (DIN+) - (DIN-)
< 1.5 Vpp
0.75
0.87
1.00
VNpp
Intercept of Level Gain
DIN±
-0.6
-0.4
-0.2
V
3
= 100 mVpp
= 0 Vpp
Level Gain
Level Pin Output Impedance
Slope + (IntercepUDIN)
ILEVEL = 0.2 mA
Level pin Maximum
Output Current
100
1.5
10-74
200
300
n
mA
SSI 34P553/5531
Pulse Detector &
Data Synchronizer
HYSTERESIS COMPARATOR (continued)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Hysteresis Gain
0.3V < HYS < 1.0V
0.30
0.41
0.50
VN
Slope of Hysteresis Gain
Calculated from
0.3V < HYS < 1.0V
0.34
0.42
0.46
VNpp
Intercept of Hysteresis Gain
HYS= OV
-0.05
0.00
0.05
V
Slope + (InterceptiHYS V)
Hysteresis Gain
HYS Pin Current
0.3 V < HYS < 1.0V
DOUT Pin Output Low Voltage
5 kQ from DOUT to AGND2
VPA2
-2.5
DOUT Pin Output High Voltage
5 kQ from DOUT to AGND2
VPA2
-2.0
-5
IlA
VPA2
-1.35
V
VPA2 -1.6 VPA2
-1.1
V
0.0
VPA2 -2
ACTIVE D1FFERENTIATOR
Unless otherwise specified, recommended operating conditions apply. Input (DIN+) - (DIN-) is an AC-coupled,
1.0 Vpp, 0.6 MHz sine wave. 100 Q in series with 265 pF are tied from DlF+ to DIF-.
Input Signal Range
Differential Input Resistance
(CIN+) - (CIN-) = 100 mVp-p
@2.5MHz
Differential Input Capacitance
(CIN+) - (CIN-) = 100 mVp-p
@2.5MHz
Common Mode Input Impedance
Both sides
Voltage Gain From
CIN±to DIF±
(DIF+ to DIF-) = 2 kQ
DIF+ to DIF- Pin Current
Differentiator impedance must
be set so as to not clip the
signal for this current level
COUT Pin Output Low Voltage
5 kQ from COUT to GND
VPA2
-2.5
COUT Pin Output High Voltage
5 kQ from COUT to GND
VPA2
-2
8
2.0
COUT Pin Output Pulse Width
10
2.5
Vp-p
14
kQ
5.0
pF
3.5
kQ
VN
1
+0.7
rnA
VPA2
-1.35
V
VPA2 -1.6 VPA2
-1.1
V
-0.7
VPA2 -2
36
10-75
1.5
ns
I
SSI 34P553/5531
Pulse Detector &
Data Synchronizer
ELECTRICAL SPECIFICATIONS (continued)
QUALIFIER TIMING (See Figure 8)
Unless otherwise specified, recommended operating conditions apply. Inputs (DIN+) - (DIN-) are an AC
coupled, 1.0 Vpp, 0.6 MHz sine wave. 100n in series with 265 pF are tied from DIF+ to DIF-. 0.5V is applied
to the HYS pin. COUT and DOUT have a 5 kQ pull-down resistor (fortest purposes only.) WG pin is low. RDO
is loaded with a 4 kQ resistor to VPD and a 10 pF capacitor to DGND.
PARAMETER
CONDITIONS
Td1
D Flip-Flop Set Up
Time
Minimum allowable time
delay from (DIN+) - (DIN-)
exceeding hysteresis
point to (DIF+) - (DIF-)
hitting a peak value.
Td3
Propagation Delay
From positive peak of DP/DN
to RDO output pulse
60
110
ns
Td4
Propagation Delay
From negative peak of DP/DN
to RDO output pulse
60
110
ns
6
ns
55
nS
ITd3-Td41
Td5
MIN
NOM
25
UNIT
ns
0
Pulse Pairing
Output Pulse Width
MAX
36
SYNCHRONIZER SECTION
READ MODE
TRVCO, VCO Output Rise Time
0.8V to 2.0V, CL::; 15 pF
8
ns
TFVCO, VCO Output Fall Time
2.0V to 0.8V, CL::; 15 pF
5
ns
(TVCO)
+12
ns
10
ns
TSRD, SRD Output Pulse Width
(TVCO)
-12
TRSRD, Read Data Rise Time
0.8V to 2.0V, CL::; 15 pF
TFSRD, Read Data Fall Time
2.0V to 0.8V, CL::; 15 pF
TPSRD, SRD Output
Setup/HoldTime
Falling edge of VCO to
either edge of SRD
TRD, ROT Input Pulse Width
8
ns
-15
15
ns
20
(TVCO)
-20
ns
15
ns
O.26TVCO
O.74TVCO
ns
-10
+10
TFRD, RDT Input Fall Time
TWVCO, VCO Output
Pulse Width (Includes Effects of
Window Shift)
10-76
--
SSI 34P553/5531
Pu Ise Detector &
Data Synchronizer
WINDOW SYMMETRY CONTROL CHARACTERISTICS
PARAMETER
MIN
CONDITIONS
NOM
MAX
UNIT
TWSS WSO , WS1, WSD
Set Up Time
50
ns
TWSH WSO, WS1, WSD
Hold Time
0
ns
DATA SYNCHRONIZATION
PARAMETER
CONDITIONS
TVCO VCO Center Frequency
Period
VCO IN = 2.7V
TO = 83.8 (RR + 1.78),
RR = 3kto 9k
VPA2 =5.0V
VCO Frequency
Dynamic Range
KVCO VCO Control Gain
KD
Phase Detector Gain
·
KVCO x KD Product
Accuracy
·
1.0V ~ VCO IN
VPA2= 5.0V
coo = 27t/ TO
1.0V ~ VCO IN
MAX
UNIT
0.8TO
1.2TO
ns
±22
±45
%
0.160)()
0.25 coo
radls V
0.83 KD
1.17 KD
Alrad
-28
+28
%
.02 TVCO
ns
MIN
~
VPA2-0.6V
~
VPA2-0.6V
KD = 0.538/ (RR+500)
VPA2 = 5.0V
VCO Phase Restart Error
NOM
ns
12
Decode Window
Centering Accuracy
-.02 TVCO
Decode Window
0.9TVCO
ns
TS1
Decode Window Time
Shift
TWS1 = .05 TVCO
WSO = 0; WSI = 1
TWS1
ns
TS2
Decode Window Time
Shift
TWS2 = .15 TVCO
WSO = 1; WSI = 0
TWS2
ns
TS3
Decode Window Time
Shift
TWS3 = .2 TVCO
WSO = 0; WSI = 0
TWS3
ns
TSA
Decode Window Time
Shift
TWSA
ns
·
lWSA=0.29TVCO(1- 3260+R)
5950+R
WSO = 1 ; WSI = 1
Not directly testable; design characteristics
10-77
II
SSI34P553/5531
Pulse Detector &
Data Synchronizer
WG-----,
WG-----,
lowQ - - - - , - - : : - - - - - ,
lowQ ----,-.;;-9fJ.S-::-1
.9fJ.S 1-_ _ _ _ _ __
Fast Discharge Switch
!.s;;;lL.____
~f-------'--1
Fast Discharge Switch
1
(DIN+ - DIN-)
-25%
1
I
Ff
.
1
1
------c-:~ I
Fast
Charge
!
..
1
-------'-1"'----.1
-----+-1---------1
1
:
I Fast
Discharge
Slow
Charge
Figure A: AGC Attack Sequence
1
Slow
Discharge
Figure B: AGC Decay sequence
FIGURE 7: AGe Timing Diagram
+HYSTERESIS LEVEL
V(CIN+) - (CIN-)
aoo
1
----~I~~I_~_--
ovH--~~---r-~r--+----\
V(DIN+) - (DIN-)
-HYSTERESIS LEVEL
V (DIN+ - DlN-)
DIFFERENTIATOR
COMPARATOR OUTPUT
RDO TEST PT
OUTPUT
FIGURE 8: Read Mode Digital Section Timing Diagram
10-78
SSI34P553/5531
Pulse Detector &
Data Synchronizer
~~~ _ _ _ _ _ _ _~~.5V
WSD
I--
TWSS
1.5X~ _ _ _ _ _ _ _ __
-1--
TWSH
--I
~
~~5V_ _ _ _ _ _ _ _ _ __
FIGURE 9: Window Symmetry Control Timing
veo
1.5V
1.SV
A
SRD
_ _ _ _~
2.0V
~
2.0V
1.5V
O.8V
1.5V
O.8V
""r-----
~-----
TSRD ----~~I
~~
~~
TRSRD
TRSRD
FIGURE 10: Read Mode Timing
TRveo
TFveo
veo
1.5V
1nS + 00,,2
(11)
C=damping factor
=natural frequency
O>n
For loop filter (a), C2 is normally chosen to be much
smaller than Cl so that it does not affect the loop
transfer function significantly. Assuming that Cl " C2
and sR 1Cl « 1 atthe frequencies of interest, (6) reduces
to:
(8)
10-81
The damping factor and natural frequency of (10) can
be extracted:
(12)
ron =
Cl (1- a TonKoKdRl)
Rl_ aTo
Cl
r-~~~~-
nKoKdCl
I; ----'-.I-c---=""'-:-:=_;_;'--;:::-2
1-aTonKoKdRl
(13)
II
SSI34P553/5531
Pulse Detector &
Data Synchronizer
Substituting (8) into (4) gives the transfer function for
Idle mode:
(14)
90 (s)
For the SS134P553: RR= 5D~ -1.79(kQ)=8.17kQ
where DR = Data Rate in Mbitls
=128-106 rad/sec
K =017
o
. roo .
Volt
Or(s)
Kd
Again, this is in the form of a second order transfer
function. The damping factor and natural frequency are
found to be:
(15)
/i)n=~nKoKd
C1
R1 ,...,..,--:-:--::-
(16)
'=2".vnKoKdC1
0.62 = 71.51-10-0 A/rad
RR+500
KT = 0.171t = 0.534
Assuming a length of 20 2T patterns, then:
t = (20) (2) (833) ns = 33.3 J.IS
ron=2Z- = 1. 71-10 5 rad/s
33. 3 J.IS
C 1 = 1565 pF + 165.6 pF = 1.73 nF
To design the loop for proper read mode operation
using (12) and (13), R, and C, must be found in terms
of the damping factor and natural frequency.
R1 =5.02 kQ
The resulting loop filter is shOwn in Figure 13.
To do this, first find 1;Iron, then solve for R 1C 1 .
R1C1=2, +aTo
(17)
/Un
Substitute this value for R1 C 1 into the equation for ron
and solve for C1 •
nKoKd
(2')
CF--2-+aTonKoKd -+aTo
/i)n
/Un
(18)
Now that C1 is known, RIcan be found by dividing (17)
through by C1 •
(19)
FIGURE 13
The value of C 2 = C 1/10 is chosen to damp out
transients on the FILT pin and meet the requirement
C2 ccC1 ·
EXAMPLE 1
Assumethatthe data rate iSO.6 Mbitls, ~=0.7, a length
of 20 2T patterns for the loop to lock is used, and
ront= 5.7 for error < 1%.
n = 0.5 due to the .2T pattern.
When the loop locks to the reference oscillator in Idle
mode, the looptransferfunction is given by (14), and ron
and ~ are given by (15) and (16). Rl and C 1 from
Example 1 can be substituted into these equations to
find the resulting natural frequency and damping factor
in Idle mode.
1
1
To= 10 = 1.2-106 = 833ns
roo = 21t
to = 21t (1.2 - 10
6)
= 7.54 - 106 rad/s
CXo= 0.5
1().82
SSI 34P553/5531
Pu Ise Detector &
Data Synchronizer
LOOP
FILTER
READ
DATA
REF.
OSC.
EN
VCO
-------~
SEL
MODE
FIGURE 14A: Standard Configuration of a Data Synchronizer Phase-Locked Loop
PHASE DETECTOR
----------------,
, +
VCO
LOOP
FILTER
Ko
F(s)
S
,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ J ,
FIGURE 148: Phase-Lock Loop System Representation
II
II
L---..J IL----.
+10
PHASEDETJ,W>?J!
0
--------------,U'---------.JI
"0
U .-----
FIGURE 15A: Phase Detector Timing with Ideal Quarter Cell Delay. For an ideal pulse (1), there is no phase
detector output. When a pulse is shifted late (2) or early (4) by less than the quarter cell delay time, the phase
detector output is negative or positive, respectively. When the read data is shifted late (3) or early (5) by more than
the quarter cell delay time, a phase detector output polarity error occurs. In this case, the output polarity becomes
positive for a late shifted pulse and negative for an early shifted pulse.
10-83
II
SSI34P553/5531
Pulse Detecto'r&
Data Synchronizer
READDATA~
-:u
u
~
U
~'-----T2 I
T1 :4.'4
CASE 1: DELAYOUTPUTIS EXACTLY
h BIT CEll. Tl -
________~Il~------__
.:
'4
Tl
.:4.
T2
s---LJLJL
~
CASE 2: DELAY OUTPUT IS GREATER THAN
CASE 3: DELAY OUTPUT IS LESS THAN
h BIT CEll TIME.
T2
h SIT CELL TIME. Tl > T2
Tl < T2
FIGURE 158: Timing of Phase Detector Enable Logic. The read data input pulse can shift to the left by T1 and
to the right by T2 before an error occurs in the phase detector output polarity, If the quarter cell delay output is not
exactly 1/4 bit cell wide, then T1 '" T2, as shown in cases 2 and 3.
LOOP
FILTER
READ DATA
vco
REFOSC
~~¥ROL
f-...,..-~
----------'
FIGURE 16A: Modified Data Synchronizer Phase-Locked-Loop with Quarter Cell Delay Control
Quar\erCell
Delay Gain
Phase Detector
j. -
-
-
-
-
-
-
-
-
-
-
-
-.
I
FIGURE 168: Modified Data Synchronizer System Representation
10-84
SSI34P553/5531
Pulse Detector &
Data Synchronizer
THERMAL CHARACTERISTICS: aja
PACKAGE PIN DESIGNATIONS
(Top View)
52-Lead QFP
52 51
50 49 48 47 46 45 44 43 42 41
DIF+
a
0
Ei ,:! ..'- + + ,
:::> :::> z z z
."
z
I 75° CNoI
,
~
CD
~ ~
;!; :f
52 51
50 49 48 47 46 45 44 43 42 41
0
0
Ci U Ci
~
0
~
'"0>-
:I:
DIF+
a
DIF-
DIF-
VPA1
37
VPA1
DOUT
36
DOUT
COUT
COUT
34
VPA2
34P553
34P5531
RDT
N/C
NlC
31
REFCLK
DGND
VPD
WG
FLTR
WG
NlC
IREF
NlC
16 17 18 19 20 21 22 23 24 25
REFCLK
DGND
NlC
VPD
15
VPA2
Rlli
FLTR
27
0
0
>
15
16 17 18 19 20 21
5!
ffi ~
u.
II:
'"0
oJ'
0
W
a.
52-Lead QFP
..J
12
Z
0
IREF
22 23 24 25 26
~ ~ ~
c
~
il:
'"
II:
>
52-Lead QFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
I
ORDERING NUMBER
I
PACKAGE MARK
32P553-CG
I
32P553-CG
32P5531-CG
I
32P5531-CG
SSI 32P553 Pulse Detector & Data Synchronizer
52-Lead QFP
I
SSI32P5531 Pulse Detector & Data Synchronizer
52-Lead QFP
I
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No lioense is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notioe. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1293 - rev.
10-85
©1991 Silicon Systems, Inc.
II
Notes:
10-86
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
I;Gi",'"6'fI-m6'
December 1993
DESCRIPTION
FEATURES
The SS134P3200 is a high performance pulse detector
and data synchronizer integrated circuit. This device is
designed for use in high density floppy storage
applications conforming to the JEIDA standard. The
pulse detection portion of this device detects and
validates amplitude peaks output from a disk drive read
amplifier. The data synchronization portion is a 2,7
RLL or M FM data synchronizer with window shift and
write pre-compensation capability. The SSI34P3200
supports a Sleep mode for minimal power dissipation
in non-operational periods.
•
The SSI 34P3200 features a 3-pin serial port for easy
selection of data rate and operating configurations
•
The SSI 34P3200 is available in a 52-lead QFP
package.
•
•
5V Operation only
Low Operating Power
•
Sleep Mode
•
•
•
•
Highly Integrated Pulse Detector & Data
Synchronizer
Ideal for High Density Floppy Storage
Application in JEIDA Standard
Operating Data Rate: 250KlSOOKl1M/2M13M1
4.5M/6M NRZ bits per second
Supports 2,7 RLL or MFM Encoding Format
3-Pln Serial Port Programming: Data Rate
Selection, Window Symmetry COntrol & Test
Mode
Fast Acquisition Phase Lock Loop & Zero
Phase Restart Technique
BLOCK DIAGRAM
IN+
IN·
.----;;----<,1
vco eLK
VEGC
_Modo
"PuR
00.....
CONTROL
t---+---o
S)tIc:tvalit...
CAUTION: Use handling procedures necessary
for a static sensitive component
1293· rev.
10-87
RG
WG
SRD
II
I
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
FUNCTIONAL 'DESCRIPTION
AGC AMPLIFIER & AGC CONTROL
The SSI 34P3200 is a pulse detector and data
synchronizer circuit. Its three main functions are:
The AGC amplifier provides signal amplification prior
to pulse qualification. The amplifier gain is linear
function of a gain control voltage, Figure 1. The gain
control voltage is either the BYP voltage when EGC =
logic high, or the VEGC voltage when EGG = logic low.
Validate and time-position preserve the analog
pulses (IN±) from a read-write pre-amplifier.
Extract the encoded data bit and its corresponding
clock signal.
Provide write precompensation function for write
data signal.
The SSI 34P3200 major functional blocks ,are:
AGC amplifier & AGC control
a
Inthe normal Read mode, i.e., with the AGC active, the
DIN± input signal is regulated to a nominal level which
is set by the voltage at the AGC pin. With the AGe pin
open, the nominal DIN± level is 1 VPPD (peak-to-peak
differential). This nominal DIN± level can be adjusted
with an extemal resistor tied from the AGC pin to either
VPA1 or AGND1, as shown in Figure 2. The DIN±
voltage level is nominally 1.0 VppdN x VAGC.
Pulse qualifier
Window shift
The AGC actions are current charging and discharging
the external BYP integrating capacitor. They are
described as follows:
Write precompensation
Slow Decay
Serial port decode & registers
When the instantaneous DIN± signal is below the
nominal level, a slowdecay~urrent, 4.5J,!A, discharges
the BYP capacitor. The AGC amplifier gain is increased
slowly.
'
Data synchronizer
AGC
AMPLIFIER
GAIN
Slow Attack
SLOPE = 120 VN
80
40
When the instantaneous DIN± signal exceeds the
nominal level but is below 125% of the nominal level, a
slow attack current, 0.18 rnA, charges the BYP capacitor.
The AGC amplifier gain is decreased.
4
2.56 V
V@ BYPNEGC
FIGURE 1: AGC AmplHler Gain
vs BYPNEGC Voltage
RAGC
P:
Rext
RAGC
~vee
+
-
YVAGC
-=
V@AGC = VAGC + (Vee - VAGCl RAGC
RAGe + Rext
-=
Rext
I'
.AGC
VAGC
V@AGC= VAGC Rext
RAGC + Rext
FIGURE 2: AGC Loop Reference Adjustment
10-88
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
Fast Attack
When the instantaneous DIN± signal exceeds 125% of
the nominal level, the device enters a fast attack mode.
A fast attack current, 1.3 rnA, charges the BYP capacitor.
The AGC amplHier gain is quickly lowered.
Write-to-Read Recovery
With a logic high to logic low transition of the WG, the
SSI 34P3200 enters the write-to-read recovery mode.
The input impedance remains in low impedance state
for 0.9 JlS for fast input DC coupling recovery. Then, the
device restores to high input impedance state, and
enters into a fast decay mode for 0.9 JlS. In the fast
decay mode, a continuous 0.12 rnA current discharges
the BYP capacitor. The AGC amplHier gain is increased
very quickly. (Otherwise only the slow decay mode is
Write
available to increase the AGC amplifier gain.) Figure 3
shows the write-to-read AGC action timing.
The following AGC actions, except that of write-to-read
recovery, can be suspended with the HOLD =logic low.
The AGC amplifier gain is then held constant, except
for leakage effect.
With EGC = logic low, the AGC amplHier gain is
determined by the VEGC voltage. With a fixed external
DC voltage, or a second AGC control loop atthe VEGC
pin, the AGC amplifier gain is set independent of the
on-Chip AGC control loop, such as when read signal is
over a servo demodulation field.
The AGC amplHieroutputs are emitter follower outputs.
Read
Write
WG
I
I
I
I
: 0.9 JlS :
I
Low Input
Impedance
Read
WG
I
I
I
I
: 0.9 JlS :
I
I
I
I
Impedance
I
F~
Switch
I
low Input
I
I
I
I
I
I
I
F~
I
I
Switch
DIN±
I'
I
~
::
Envelope
!~
~I
Fast
Anack
I
I
~:
:~
I
Fast " ,
Attack
Fast
Decay
I
I
DIN±
I
I
I
I
I
125% of nominal level
Envelope
I
I
I
I
I
I
I
"
I
I
I
I
I
I
I
Fast I Slow I
• Decay' Anack
Slow
Anack
FIGURE 3: AGC Action Timing In Wrlte-to-Read Recovery
1~9
II
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
Time Qualification
FUNCTIONAL DESCRIPTION (continued)
PULSE QUALIFIER
The pulse qualifier validates each DIN± peak by· a
combination of level qualification and time qualification.
In level qualification, a hysteresiscomparatoreliminates
errors due to .low level additive noise. In time
qualification, the AGC amplifier output is time
differentiated to locate the signal peaks in time.
Level Qualification
The level qualification is accomplished by comparing
the DIN± signal with a set threshold. The SSI34P3200
allows two ways of setting the thresholds: fixed
threshold or DIN± tracking threshold. Fixed threshold
can be simply set by a DC voltage at the HYS pin, such
as a resistor from VPA 1 to ground. The threshold atthe
comparator can be computed as:
Hysteresis Gain x V@HYS.
For high performance system application, however,
DIN± tracking threshold is recommended.
Time qualification is used to locate DIN± peaks. With
time differentiation, each DIN± peak is translated into
a zero crossing, which clocks a on-chip flip-flop in the
pulse qualifier. The SSI 34P3200 supports on-chip or
off~chip differentiation.
On-Chip Differentiation
The on-chip differentiation is accomplished by
connecting an external RLC network across the DIF±
pins. The DIN+ and CIN-+- pins should be tied together,
as well as the DIN- and CIN- pins.
Off-Chip Differentiation
For constant density recording applications, a
differentiation function with a low pass cut-off frequency
tracking the data rate can maximize the signal-to-noise
ratio performance. A time differentiated input can be
applied attheCIN± pins, separated from the DIN±pins.
A 3.5 kO resistor should be placed across the DIF±
pins.
This function can best be supported by the Silicon
DIN± tracking threshold has the advantage of shorter
Systems programmable filters, such as the SSI
write-to-read recovery time and lower probability of
32F8030, F8130/8131. Thefilters featu re both a normal
error with input amplitude drop out The threshold is
low pass output and a differentiated low pass output.
designed as a percentage of the DIN± peak voltage.
The low pass cut-off frequency is programmable by the .
This technique can be implemented by feeding the
userto track the data rate. The signal delays of the two
LEVEL output, through a resistor divider, to the HYS
signal pathS are well matched.
pin.The LEVEL output, amplified peak capture of DIN±
signal, can be computed as: Level Gain x DlN± ppd.
Qualified Read Data
With the resistor divider, a fraction of the LEVEL output
Upon level and time qualification, a one-shot data
is presented at the HYS pin. The threshold, as a
pulse is generated for every validated peak of the DIN±
function of DIN±, can be summarized as: Level Gain
signal. This read data pulse can be monitored at the
x Resistor Dividing Ratio x Hysteresis Gain x DIN±
RDO pin, when OEN = LogiC high. In high speed normal
ppd. For a typical case of 1Vppd DIN± Signal, assume
Read mode, it is recommended that the RDO output
equal value resistors in the divider network, the
be disabled for lower noise performance with OEN =
threshold is 1 x O.5x O.36x 1 =O.18V. This represents
Logic low. The pulse detector read data can be used as
36% threshold on a 1Vppd signal. While both the Level
input to the data synchronizer. Alternately, external
Gain and the Hysteresis Gain bear a moderatetolerance ,
input at the RDI pin can be used as input to the data
due to typical process variation, they inversely track
synchronizer.
each other to yield a much tighter threshold accuracy
Figure 4 summarizes the pulse detector function.
in a closed loop.
While the external resistor divider ratio determines the
qualification setting, the total resistance and the peak
capture capacitor should be optimized for the system
data rate. The RC time constant must be small enough
to allow 990d response to changing DIN± peak, but
large enough to provide a constant threshold after a
long duration of input absence.
10-90
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
:.: Td1
DIN±
+ Hysteresis
Threshold
I
I
----1'----
- - - - - - - - - - - - - - - - - - - - - - - ---Hysteresis
Threshold
I
I
I
I
DOUT~
:
I
Differentia~torI
Comparator
Ompm
L
.
~----~
I
_ _-U
eOUT
I
Td3"': :-. --. : - Td4
I
I
I
I
r---1 I r - - - - - - - - - - - - .
L.J
L.J
~
RDO - - - ' 1
FIGURE 4: Read Mode Pulse Detector Timing
DATA SYNCHRONIZER
The data synchronizer is used to extract the clock and
the encoded data signals from the read data signal.
The input source to the data synchronizer can be from
the pulse qualifier or from an external source via the
RDI pin.
The 551 34P3200 is designed to perform data
sy~chronization for the following operating data rates,
which are selected through a serial port register RO:
Rate
NRZ Data Rate
Encoding Format
6 Mbitls
2,7 RLL
2
4.5 Mbitls
2,7 RLL
3
3 Mbitls
2,7 RLL
4
2 Mbitls
MFM
5
1 Mbitls
MFM
6
500 Kbitls
MFM
7
250 Kbitls
MFM
10-91
For both the 2,7 RLL and MFM encoding formats, the
encoded bit rate, as well as the data synchronizer
clock, is at twice the NRZ data rate. Thus, the required
data synchronizer clock rate isfrom500 kHzto 12 MHz.
To accommodate the wide data rate dynamiC range,.
the 551 34P3200 employs a novel data synchronizer
phase locked loop (PLL) architecture (see block.
diagram). While the voltage controlled oscillator (veO)
operates only between 6 MHz to 12 MHz, a dividedown function is used to generate the lower frequency
clock. For Rates 1-3, the veo operates at 12 MHz, 9'
MHzand6MHz, respectively. For Rates 4-7, the veo
operates at 8 MHz and the divide-down factor, N, is
from 2 to 16.
'II
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
FUNCTIONAL DESCRIPTION
(continued)
DATA SYNCHRONIZER (continued)
With the serial register RO programmed for a specific
data rate, the 551 34P3200 would properly decode the
proper veo frequency and the divide-down factor.
Furthermore, the 1/4 cell delay duration, i.e., one half
of the encoded bit period, is also set properly for each
operating mode.
When the 551 34P3200 is in the Idle mode, the veo
should lock to an external reference clock, FREF. For
Rates 1-3, the FREF should be 12 MHz, 9 MHz and 6
MHz, respectively. For Rates 4-7, the FREFshould be
SMHz.
The 551 34P3200 employs a dual mode phase detector:
harmonic in the Read mode and non-harmonic in tfle
Write and Idle modes. In the Read mode, the harmonic
phase detector updates the PLL with each occurrence
of a read data pulse from the pulse qualifier. In the
Write and Idle modes, the non-harmonic phase detector
is continuously enabled, thus maintaining both phase
and frequency lock. Figure 5 shows the phase detector
transfer function. By acquiring both phase and
frequency lock to the FREF and utilizing a zero phase
restart technique, false lock to the pulse detector read
data is eliminated.
The phase detector incorporates a charge pump in
order to drive the loop filter directly. The polarity and
width of the output current pulses correspond to the
direction and magnitude of the phase error.
Because of the wide data rate dynamic range, the 551
34P3200 provides four high impedancellow impedance
switchable nodes, FL 1-4, for external loop filter
component switching. When the node is in high
impedance state, the external component connected
to this node is switched out. When the node is in low
impedance. state, the external component is included
in the loop filter network.
The various operating modes of the data synchronizer
. are discussed in the following section.
Average
Output Current
Average
Output Current
10
2'
Phase
Error
Phase
Error
-~
(a) Harmonic Mode
(b) Non-Harmonic Mode.
Note 1) 10 is the magnitude of the. charge pump current
2) Phase error is relative to the +N counter output period
FIGURE 5: Phase Detector Transfer Function
10-92
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
Encoded
Data
1IDI
DlVD
DATAl
IaIaI IaI
1
-u-~
rl
DlVD
DATA2
+NCIock
Encoded
Data
DlVD
DATAl
+NClock
I
III I
Decode
Window
1
'1m!
DLVD
DATA2
..J1Jlhn
I a I a I I 0·1
Decode
Window
U
--A-AJlSLhn
I
I II I
I
Encoded
Data
1
U
lim
DlVD
DATAl
DlVD
DATA2
+N Clock
-----Il!-
-----rlJlJlJhn
I
III
Decode
Window
(b) Normal
(a) Late
IaIa I IaI
(c) Early
FIGURE 6: Decode Window & Window Shift Directions
WINDOW SHIFT
SERIAL PORT DECODE & REGISTERS
To enhance the data decode function, the SSI34P3200
supports a window shift function for the highest three
data rate operations. Shifting the pulse widlh of the 114
cell delay output shifts the relative pOSition of the DLYD
DATA pulse within the decode window. This powerful
capability, supported through serial register R1, easily
facilitates defect mappings, automatic calibration,
window margin testing, error recovery, and systematic
error cancellation.
The SSI34P3200 provides a 3-pin serial port to facilitate
the following digital controls:
The window shift can be set to ±5%, ±7.5%or±10%of
the decode window. Figure 6 defihes the direction of
the window shift. Refer to the Serial Port Decode &
Registers section for serial port register assignment.
WRITE PRECOMPENSATION
• Data rate (Register 0: Bits 2-0)
• Window shift (Register 1: Bits 3-0)
• Write pre-comp (Register 2: Bit 0)
• Data synchronizer input source (Register 2: Bit 2)
The 3 serial port pins are SDEN, SDI and SCLK. Figure
7 shows a timing diagramof the serial data transmission.
Each data transmission consists of a 8-bit packet. Bit
7 being the most significant bit (MSB). The 8-bit packet
is divided into two fields: Bit7-4 address field, Bit 3-0
data field. These registers are reset to 0 when the
power-on function is used.
Write precompensation circuitry is provided to
compensate for media bit shift caused by intersymbol
interference. The magnitude of the time shift, TPC, is
determined by an external resistor on the WCS pin,
with Rp from WCS to VPA2. TPC is given as:
TPC = 1.6 X 10.3 Rpns
10-93
II
SSI.34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
FUNCTIONAL DESCRIPTION
(continued)
SE61ALPORT Dj::CODE & REGISTERS
(continued),
The register ~ssignment is as follows:
Register 0
Bit3 ..
Address 0000
Not used
NRZ Data Rate
VCOFrequency
Divide Down
FLO
FL1
FL2
FL3
FL4
000
6 Mbitls
12 MHz
1
LowZ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
001
4.5 Mbitls
9MHz
1
LowZ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Bit 2-0
010
3 Mbitls
6MHz
1
LowZ
Hi-Z
011
2 Mbitls
8MHz
2
Hi-Z
LowZ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
100
1 Mbitls
8 MHz
4
Hi-Z
LowZ
LowZ
101
500 Kbitls
8 MHz
8
Hi-Z
LowZ
LowZ
LowZ
Hi-Z
110
250 Kbitls
16
Hi-Z
LowZ
LowZ
LowZ
LowZ
Register 1
Address 0001
8MHz
The window shift function is available for the 6 Mbitls, 4.5 Mbitls and 3 Mbitls data rates.
Bit 3
Window shift Enable
0
Disabled
1
Enabled
Bit 2
0
1
Bits 1-0
Window shift direction
Early
Late
.
"
Window sh.ift magnitude
00
10 % of RRC period
01
7.5%
10
5%
11
0%
.'
10-94
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
Register 2
Address 0010
Bits 3,1
Not used
Bit 2
Data Synchronizer Input Source
0
From internal pulse qualifier output
1
From the RDI pin
Bit 0
Write Pass Through
1
Write synchronizer is a simple buffer
0
Write synchronizer & pre-comp is active
clocks data b~
I
I
i'6- TC_
I
SCLK
,n
,T2A
~ SOEN setu!,
SOEN hold
SOEN
I wrt SCLK falls
~ SOEN falls
wrt SCLK falls I I
I !,rior to SCLK
,--.;-1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---,T2B rises
I
J
T3 : T4
SOl setup
, I
wrt SCLK falls I-I""
SOl
~
07
SOl holds
!oad d,,!a
.'
wrt SCLK falls
Into regIster
'----'x
I
X 06 X 05 X 04 X 03
02
~'---'----
X X X,--_
01
DO.
FIGURE 7: Serial Port Timing
II
10-95
SSI34P3200
Pulse Detector & Data ,Synchronizer
for High Density Floppy Storage
OPERATION MODES
The SSI 32P3200 can support the following operating modes:
RG
mrn
EGG
SLEEP
0
0
1
1
1
0
0
0
1
1
0
0
X
0
1
Read
VCO locked to Pulse Qualifier DLYD DATA
AGC active
0
1
1
1
1
Read
VeO locked to Pulse Qualifier DLYD DATA
AGC gain held constant by BYP
0
1
0
1
1
Read
VCO locked to Pulse Qualifier DLYD DATA
AGC gain held constant by VEGC
0
1
X
0
1
Write
AGC gain held constant by BYP
Input impedance lowered
VCO locked to FREF
1
X
X
1
1
Write
AGC gain held constant by VEGC
Input impedance lowered
VCO locked to FREF
1
X
X
0
1
X
X
X
0
Mode,
WG
Idle
VCO locked to FREF
AGC active
Idle
VCO locked to FREF
AGC gain held constant by.BYP
Idle
VCO locked to FREF
AGC gain held constant by VEGC
Power Shutdown
X
10-96
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
READ MODE
close to that required for tracking actual data and thus
minimizes the associated frequency step during
acquisition. When RG transitions, the vca is stopped
momentarily, then restarted in an accurate phase
alignment with the next PLL reference input pulse. By
minimizing the phase alignment in this manner (phase
error ~ 0.5 rads), the acquisition time is substantially
reduced.
In the Read mode, the rising edge of DLYD DATA
enables the phase detector while the falling edge is
phase compared to the rising edge of the +N counter.
As depicted in Figure 8, DLYD DATA is 1/4 cell wide
(TYCa /2/ N) pulse whose leading edge is defined by
the leading edge of Read Data. RRC is generated from
the rising edge of the +N counter output. The accuracy
of the 1/4 cell delay only affects the retrace angle of the
phase detector and does not influence the accuracy of
RRC.
With the PLL in lock, the encoded data bit is resynchronized before output to the SRD pin. Figure 9
shows the Read mode timing.
In the non-Read modes, the PLL is locked to FREF.
This forces the VCato run at a frequency which is very
Encoded
Data
101010101011101010101011101010101
DLYD DATA
+N Counter
Output
Phase Detector
Enable
FIGURE 8: Data Sychronizer Timing
,
--.:
I
I
:----
:,..----..:
RRC
SRD
TWRC
_ _- I I
:cI
FIGURE 9: Read Mode Timing
10-97
II
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
be chosen with as low a value as possible consiStent
with adequate bandwidth. to. allow more rapid settling.
OPERATION MODES (continued)
WRITE MODE
Write Data Input can be re-synchronized to the Read
Reference Clock before feeding toa write driver. Figure
10 shows the Write mode timing.
In the Write mOde. the SS! 34P3200 pulse detector is
disabled and preset for the subsequent Read mode.
The digital circuitry is disabled. the inputAGC amplifier
gain is held at its previous value and theAGC amplifier
input impedance is reduced.
By a serial register bit control. the SSI34P3200can be
placed in the write pass through mode. The synchronizer
and the pre-comp function are disabled and act as a
.
buffer only.
Holding the AGC amplifier gain and reducing input
impedance shortens system write-to-read recOvery
times.
POWER SHUTDOWN
The lowered input impedance improves settling time
by reducing the time constant of the network between
the SSI34P3200 and a head preamplifier such as the
SSI'34R1203R. Write-to-read timing is controlled to
maintain the reduced impedance for 0.9 ~ before the
AGC circuitry is activated. Coupling capacitors should
\
,~
I
For reduc,ed power dissipation during non-operational
periods. the SSI34P3200 can be switched inio a Sleep
mode. The serial port registerswill remain powered up
during Sleep mode. Therefore no reprogramming is
required following a logic low to logic high SLEEP
transition.
I
_________________
,-J,
I
•
,.
TSP ~~. THP
RRC
---J/
\
TSWO "" ....
WOI
,'---
/
______________~I.'r----------~~~~______________
\"'-......If
•
Earl
.... THWO
Late
I
\
~_\.-----"""'----1
".......I-____....
~" Late WOO Pulse Width
•
•
....~I-______-I..
~. Nominal WOO Pulse Width
•
•
.........------..;...--.......' Early WOO Pulse Width
•
FIGURE 10: Write Mode Timing
to-98
•
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
PIN DESCRIPTION
ANALOG INPUT PINS
NAME
TYPE
DESCRIPTION
IN+.IN-
I
AGC amplifier inputs.
D1N+. DIN-
I
Data inputs to hysteresis comparator and full-wave rectifier.
CIN+. CIN-
I
Data inputs to time-channel qualification.
HYS
I
Hysteresis input to establish the hysteresis threshold of the data comparator.
AGC
I
The voltage at the AGC pin determines the nominal level at the DIN± pins.
BYP
I
The voltage at the BYP pin controls the AGC amplifier gain when EGC = logic
high.
VEGC
I
The voltage althe VEGC pin controls the AGC amplifier gain when EGC = logic
low.
DIGITAL INPUT PINS:
FREF
I
TTL reference clock input to data synchronizer.
OEN
I
TTL RDO Output Enable input: RDO enabled with OEN=logic high. RDO
forced to high with OEN=logic low.
RDI
I
TTL external input source to the data synchronizer.
RG
I
TTL Read Gate input.
WG
I
TTL Write Gate input. Enables Write mode.
WDI
I
TTL Write Data Input.
EARLY
I
TTL write precompensation control input to shift write data pulse early.
LATE
I
TTL write precompensalion control input to shift write data pulse late.
SLEEP
I
TTL power shutdown control. The device is in power shutdown mode when
SLEEP = logic low. The device is in normal operational state when SLEEP =
logic high, or left open.
HOLD
I
TTL input that holds the AGC gain constant when pulled to low.
When left open, this input is at logic high.
EGC
I
TTL input. When EGC = logic low, the AGC amplifier gain is controlled by the
voltage at VEGC.when EGC = logic high, or left open, the AGC amplifier gain
is controlled by the voltage at BYP.
SDI
I
TTL Serial Data Input.
SCLK
I
TTL Serial Clock. Negative edge triggered clock input for serial register.
SDEN
I
TTL Serial Data Enable. A high level input enables data loading. The data is
latched on the falling edge of SDEN.
10-99
II
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
PIN DESCRIPTION (continued)
ANALOG OUTPUT PINS:
NAME
TYPE
DESCRIPTION
OUT+,OUT-
0
AGC amplifier emitter follower output pins.
LEVEL
0
Open emitter output from fullwave rectifier that may be used for input to the
HYSpin.
FLO-4
0
Loop fiHer connection pins. Either high impedance or low impedance state.
ANALOG CONTROL PINS:
DIF+,DIF-
-
Pins for external differentiating network. When off-chip differentiator is used,
a 3.5 kO resistor should be tied across DIF+ and DIF-.
IREF
-
Input reference currentfor VCO bias. A 7.5 kO resistor should be tied between
IREF and VPA2.
FLTR
-
Loop filter pin.
WCS
-
Write precomp set: used to set the magnitude of the write pre-compensation
time via an external resistor, Rp to AGND2.
DIGITAL OUTPUT PINS:
ROO
0
TIL output of the pulse detector read data. This output is enabled with
OEN=logic high. It is forced to high with OEN=logic low.
RRC
0
Read Reference Clock: a multiplexed TIL clock source used by the controller.
Inthe Read mode, this clock isthe encoded bit rate. In the Write mode, it is the
FREF divided down by the N factor. No short clock pulses are generated during
a mode change.
SRD
0
Synchronized Read Data: a TTL read data that has been re-synchronized to
read clock.
WDO
0
Write Data Output: a TIL output that is an input to the RIW amplifier.
COUT
0
Time qualification one-shot test point: open emitter output which requires an
external 1 kO pull down resistor when used. The pin should be left open in
normal operation to reduce power.
DOUT
0
Data comparator lest point: open emitter output which requires an external
1 kn pull down resistor when used. The pin should be left open in normal
operation to reduce power.
ORO
0
Delay Read Data test point: open emitter output which requires an external
5 kn pull down resistor when used.
VCO eLK
0
VCO test point: open emitter output which requires an external 5 kn pull down
resistor when used.
10-100
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
POWER & GROUND
NAME
TYPE
VPA1
VPA2
VPD
AGND1
AGND2
DGND
DESCRIPTION
-
Analog supply to the pulse detector section.
Analog supply to the data synchronizer section.
Digital supply.
Analog ground to the pulse detector section.
Analog ground to the data synchronizer section.
Digital ground.
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, the recommended operating conditions apply.
ABSOLUTE MAXIMUM RATINGS
Operation beyond the maximum ratings may damage the device.
PARAMETER
RATING
Storage Temperature
-65 to + 150°C
Junction Operating Temperature
+130°C
Supply Voltage, VPA1-2, VPD
-0.7 to +7V
Voltage Applied to Inputs
-0.3 to Supply + 0.3V
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
4.5V < VPA1, VPA2, VPD < 5.5V
Ambient Temperature, Ta
O°C < Ta < 70°C
POWER SUPPLY
PARAMETER
NOM
MAX
UNIT
Outputs unloaded
4.5V < VPA1, VPA2, VPD < 5.5V
450
650
mW
Output unloaded;
SLEEP = logic low
40
60
mW
CONDITIONS
Power Dissipation Active
PO
Power Down Dissipation
PDS
10-101
MIN
II
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
ELECTRICAL SPECIFICATIONS (continued)
LOGIC SIGNALS
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
TIL Input Low Voltage
VIL
-0.3
0.8
V
TIL Input High Voltage
VIH
2
vcc +0.3
V
-0.4
rnA
TIL Input Low Current
ilL
VIL = 0.4V
TIL Input High Current
IIH
VIH = 2.7V
0.1
rnA
0.8V - 2.0V transition
0.1
j.lS
IOL= 4.0 mA
0.5
V
TIL Input Switching Time
TS
TIL Output Low Voltage
VOL
TIL Output High Vollage
VOH
IOH = -400~
Test Point Output High Voltage VOHT1
(DOUT, COUT)
1 kQto DGND
VPA - 2.4
V
Test Point Output Low Voltage VOLT1
(DOUT, COUT)
1 kQto DGND
VPA- 2.8
V
Test Point Output High Voltage VOHT2
(VCOCLK, DRD)
5 kQ to DGND
4.2
V
Test Point Output Low Voltage VOLT2
(VCOCLK, DRD)
5 kQ to DGND
3.6
V
V
2.7
MODE CONTROL
Read-to-Write Transition TDRW
WG pin logic low to logic high
Write-to-Read Transition TDWR
WG pin logic high to logic low;
AGC settling not included
HOLD On to Off/Off to
On Transition
TDH
HOLD pin high to/from low
transition
Power shutdown mode
to Read/Write Delay
TDSL
Settling time of external
capacitor not included
0.1
~s
ReadlWrite Mode
TDOFF
to power shutdown Delay
Settling time of external
capacitor not included
10
j.lS
Low Input
PWIMS
Impedance Pulse Width
WG pin logic high to logic low. Not
directly testable
0.9
j.lS
Fast Discharge
Pulse Width
WG pin logic high to logic low
following PWIMS. Not directly
testable
0.9
j.lS
c
PWFDC
10-102
0.5
0.9
1
j.lS
1.3
j.lS
1
~s
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
AGC AMPLIFIER
Unless otherwise specified, recommended operating conditions apply. Input signals, 100 mVppd at 1.0 MHz,
are AC coupled to IN±. OUH are AC coupled to DIN±.
A 2000 pF capacitor is connected between BYP and AGND1. AGC pin is open.
PARAMETER
CONDITIONS
Minimum Gain Range
MIGR
Maximum Gain Range
MAGR
Output Offset
Voltage Variation
VOS
Maximum Output
Voltage Swing
VOMX
Differential Input Impedance RIN
MAX
UNIT
4
V/V
V/V
80
Over entire gain range
Set by AGC pin
-200
IN± = 100 mVppd @ 1.0 MHz
WG
WG
VIN
Gain set to maximum,
BW = 3 MHz, short IN+ to IN-
Bandwidth
BW
Gain set to maximum
referenced to 1.0 MHz
200
mV
Vppd
kQ
5
= logic low, IN+ = IN= logic high, IN+ = IN-
Input Noise Voltage
0
3
IN± = 100 mVppd
Differential Input Capacitance CIN
Single Ended Output
Impedance on OUH
NOM
1.0 Vppd ::; OUH ::; 3.0 Vppd
Single Ended
Input Impedance
ZCMH
MIN
10
pF
250
kQ
Q
15
nV/.,fHz
1.5
MHz
15
100
ROUT
Q
Input Referred
CMRR
Common Mode Rejection
IN+ = IN- = 100 mVpp
@ 1.0 MHz gain set to maximum
40
dB
Input Referred Power
Supply Rejection
PSRR
1.0 Vpp@ 1.0 MHz on VPA1
gain set to maximum
80
dB
DIN± Input Swing
vsAGC Input
KAGC
25 mVppd ::; IN± ::; 250 mVppd ;
HOLD = logic high
0.5 Vppd < DIN± < 1.5 Vppd
0.7
DIN± Input Swing
Variation with IN±
dDIN
25 mVppd ::; IN± ::; 250 mVppd
-6
AGCopen
0.8
2.5
AGC Open Voltage
VAGC
AGC Pin Input Impedance
RAGC
1.3
Vppd/V
6
%
1
1.2
V
3.8
6.0
kQ
1
Slow AGC Discharge Current
ISO
DIN± = OV
3
4.5
6
IlA
Fast AGC Discharge Current
IFD
Starts at 0.9 J.S after WG high to low transition
Stops at 1.8 J.S after WG high to low transition
0.08
0.12
0.16
rnA
AGC Leakage Current
ILK
HOLD
= logic low
DIN± = 0.8 VDC
-50
0
50
nA
-0.12
-0.18
-0.24
rnA
-0.9
-1.3
-1.7
rnA
Slow AGC Charge Current ISC
vary AGC until slow charge begins
Fast AGC Charge Current
IFC
DIN± = 0.8 VDC
vary AGC until fast charge begins
10-103
II
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
ELECTRICAL SPECIFICATIONS (continued)
AGe AMPLIFIER
(continued)
PARAMETER
Fast to Slow Attack
Switchover Point
CONDITIONS
FSSP
MIN
TGD
TGA
UNIT
125
%
IN±= 250 mVppd to 125 mVppd@ 1.0 MHz
OUT± to 90% final value
12
IJS
IN± =50 mVppd to 25 mVppd @1.0 MHz
60
IJS
WG = logic high to logic low
IN± = 250 mVppd @ 1.0 MHz
OUT± to 110% final value
2
IJS
oun to 90% final value
Gain Attack Time
MAX
DIN±{fast) / DIN±(slow)
-
Gain Decay Time
NOM
HYSTERESIS COMPARATOR
Unless otherwise specified, recommended operating conditions apply. Input DIN± is AC coupled, 1.0 Vppd
@ 1.0 MHz sinewave. 0.5 VDC is applied to the HYS pin. WG = 0
Input Signal Range
IRHC
Differential Input Resistance RHCD
Differential Input Capacitance
CHCD
DIN± = 100mVppd
1.5
Vppd
25
ill
15
20
5
pF
4
5
6
ill
0.75
1
1.25
VNppd
DIN± = 100 mVppd @ 1.0 MHz
Single Ended Inpullmpedance RHCC
DIN+ = DIN-
Level Gain from
DIN± to LEVEL
KLD
0.5 Vppd $ DIN± $ 1.5 Vppd
10 kQ from LEVEL to AGND1
270 pF from LEVEL to AGND1
Level Pin Output
Offset Voltage
VLOS
DIN± = 0 Vppd; 10 ill
from LEVEL to AGND1
100
mV
ZLV
I @ LEVEL = -0.2 rnA,
DIN± = 0.5 VDC
350
Q
Level Pin Output Impedance
Level Pin Maximum
Output Current
Hysteresis Gain
KHYS
0.3V < HYS < 1.0 V
HYS Pin Current
IHYS
0.5V < HYS < 1.5 V
Comparator Offset
Voltage
VHCOS
rnA
1.5
ILMX
HYS pin at AGND; < 1.5 kQ
across DIN+ to DIN- 5 kQ from
DOUTto DGND
10-104
V/V
0.36
-10
0
(.IA
10
mV
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
ACTIVE DIFFERENTIATOR
Unless otherwise specified, recommended operating conditions apply. Input CIN± is AC coupled, 1.0 Vppd,
1.0 MHz sinewave.
100Q resistor in series with 220 pF capacitor are tied across DIF+ to DIF-.
PARAMETER
Input Signal Range
CONDITIONS
= 100 mVppd
= 100 mVppd @ 2.0 MHz
CIN+ = CIN-
Differential Input Resistance RADD
CIN±
Differential Input Capcitance
CIN±
Single Ended
Input Impedance
MIN
NOM
IRAD
CADD
RADC
Voltage Gain
from CIN± to DIF±
KAD
3.5 kQ from DIF+ to DIF-
DIF+ to DIF- Pin Current
IDIF
Differentiator impedance must be
set so as not to clip the signal
for this current level
Comparator Offset Voltage VADaS
DIF± AC coupled, 5 kQ from COUT
to DGND
COUT Pin Output
High Voltage
5 kQ from COUT to DGND
PWC
15
4
20
5
MAX
UNIT
1.5
V
25
kQ
5
pF
6
kQ
V/V
1
-1.0
0
1.0
rnA
5
mV
30
ns
QUALIFIER TIMING
Unless otherwise specified, recommended operating conditions apply. Inputs CIN± and DIN± are in-place
as AC coupled, 1.0 Vppd, 1.0 MHz sinewave. 100Q resistor in series with 220 pF capacitor are tied from DIF+
to DIF-. 0.5V is applied to the HYS pin.
ROO is enabled as output. OEN
D Flip Flop Set Up Time
TD1
= 1. WG = 0
Minimum allowable time delay
from DIN± exceeding hysteresis
point to DIF± hitting a peak value.
ns
0
Propagation Delay from
TD3
Positive Peak to ROO Pulse
60
ns
Propagation Delay from
TD4
Negative Peak to ROO Pulse
60
ns
Pulse Pairing
I TD3 - TD41
ROO Pulse Width
PP
TRD
20
10-105
25
3
ns
30
ns
II
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
ELECTRICAL SPECIFICATIONS (continued)
SYNCHRONIZER SECTION
WRITE MODE
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Write Data Input
Setup Time to RRC
TSWD
Rising edge of WDI to
rising edge of RRC
15
ns
Write Data Input
Hold Time after RRC
THWD
Falling edge of WDI to
rising edge of RRC
3
ns
TSP
Falling edge of EARLY-f LATEto falling edge of RRC
40
ns
EARLY-fLATETHP
Input Hold Time after RRC
Rising edge of EARLY-f LATEto second falling edge of RRC
10
ns
Precomp Time
Shift Magnitude
TPC
TPCO = 1.6 X 10-3 Rp
VPA2. = 5.0V
O.8xlPCO
Write Data Output
Pulse Width
TWO
CL~ 15 pF
To = Read Reference Clock Period
TO-2TPCO TO-TPCO
Write Pass Through
Delay from WDI to WOO
TPD
EARLY-fLATEInput Setup Time to RRC
TPCO
1.2TPCO
ns
TO+
2TPCO
ns
30
ns
READ MODE
Read Reference
Clock Rise Time
TRRC
0.8V to 2.0V; CL ~ 15 pF
8
ns
Read Reference
Clock Fall Time
TFRC
2.0V to O.8V; CL ~ 15 pF
5
ns
Read Reference
Clock Pulse Width
TWRC
To = Read Reference Clock Period
O.5oTo-10
O.5oTo+10
ns
Read Data Pulse Width
TSRD
To = Read Reference Clock Period
To -5
To+5
ns
Read Data Rise Time
TRSRD
0.8V to 2.0V ; CL ~ 15 pF
Read Data Fall Time
TFSRD
2.0Vto 0.8V; CL
SRD Output Setup
wrt RRC Rise
TSSRD
15
ns
SRD Output Hold
wrt RRC Rise
THSRD
15
ns
RDI Pulse Width
TRDI
~
15 pF
To = Read Reference Clock Period
10-106
15
10
ns
8
ns
To
ns
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
DATA SYNCHRONIZATION
PARAMETER
VCO Center
CONDITIONS
TVCO
Frequency Period
V@FLTR = 2.7V, VPA2 = 5.0V
Serial Reg 0 = XOOO
Tl=83ns
Serial Reg 0 = XOOl
Tl = 111 ns
MIN
NOM
MAX
UNITS
0.8 Tl
Tl
1.2 Tl
ns
±24
±34
±45
%
Serial Reg 0 = XOl 0 Tl=167ns
Serial Reg 0 = Other Tl = 125 ns
VCO Frequency
Dynamic Range
VCO Control Gain
VDR
KVCO
Phase Detector Gain
KD
FL 1-4 High Impedance
FLZH
FL 1-4 Low Impedance
FLZL
KVCO x KD Product Accuracy
1.0V:::; V@ FLTR:::; VPA2 - 0.6V
VPA2 =5V
V@ FLTR = 2.7V; coo = 27t1TVCO
0.140)0 0.200)0 0.260)0 rad/s-V
KD = 0.621(RR + 527)
VPA2 = 5V (RR = 7.5 kil)
0.83 KD
1.17 KD
100
-28
0
28
4
PRE
Nrad
kQ
2
KPA
VCO Phase Restart Error
KD
Q
%
ns
To
ns
Decode Window
DW
Decode Window
Center Accuracy
DWCA
Decode Window
TSl
Serial Register 1 = 1XOO
±10% To
ns
Shift Magnitude
TS2
Serial Register 1 = 1XOI
±7.5% To
ns
TS3
Serial Register 1 = 1XI 0
15% To
ns
To = Read Refrence Clock Period
To - 2
-5% To
+5% To
ns
MISCELLANEOUS TIMING
RG, WG Time Delay
100
RWTD
ns
SERIAL PORT SECTION
SCLK Period
TC
100
SDEN Setup to SCLK
Tl
10
TC/2 -10
ns
ns
TC -10
ns
SDEN Hold after SCLK
T2A
10
SDEN Falls prior to
SCLK rises
T2B
25
ns
SDI Setup to SCLK
T3
25
ns
SDI Hold after SCLK
T4
25
ns
10-107
II
SSI34P3200
Pulse Detector & Data Synchronizer
for High Density Floppy Storage
THERMAL CHARACTERISTICS: 9ja
PACKAGE PIN DESIGNATIONS
(Top View)
52-lead OFP
me-
.t
cZ
,.! ,.,.
. .
~~
>
CD i!:
52 51
50 49 48 47 46 45 44 43 42 41
0-
0
~
C)
c[
:::>
0
:::>
0
~
I
75°C/W
Z z Z
i5 0
0
l
LEVEL
SIm>"
2
HVS
N/c
3
OIF.
SOl
4
OIFVPAl
SCLK
SOEN
DEN
WCS
7
llOO
RDf
woo
8
Dill
9
EJiJl[Y
10
ooUT
WOI
11
COUT
RRC
12
FREF
WG
13
31
AGND2
ORO
14 15 16 17 18 19 20 21 22 23 24 25
!f
0
a:
rn
0
z
8
~
0
0::
>
u.
0-
~
U.
W
g;
~
0-
>
::';
U.
~ ~
-'
U.
9U.
52-Lead QFP
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
SSI 34P3200 - 52-lead OFP
34P3200-CG
PKG.MARK
34P3200-CG
Preliminary Data: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are not guaranteed. Small quantities are available, and Silicon Systems should be consulted for current information.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems_ Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc. 14351 Myford Road, Tustin. CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
1293 - rev.
10-108
©1992 Silicon Systems, Inc.
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbit/s
I; t§'" ,ii IS' fi .Mb'
December 1993
DESCRIPTION
FEATURES
The SSI34P3201 is a high performance pulse detector
and data synchronizer integrated circuit. This device is
designed for use in high density floppy storage
applications. The pulse detection portion of this device
detects and validates amplitude peaks output from a
disk drive read amplifier. The data synchronization
portion is a 1,7 RLL or MFM data synchronizer with
window shift. The SSI34P3201 supports a Sleep mode
for minimal power dissipation in non-operational
periods.
•
Highly Integrated Pulse Detector & Data
Synchronizer
•
Ideal for High Density Floppy Storage
Applications
•
Operating Data Rate: 250K to 8.0M NRZ bits per
second selectable through the serial port
•
Supports 1,7 RLL, MFM, FM, and GCR
Encoding Format
•
The SSI 34P3201 features a 3-pin serial port for easy
selection of data rate and operating configurations.
3-Pin Serial Port Programming: Data Rate
Selection, Window Shift & Test Mode
•
The SSI 34P3201 is available in a 52-lead QFP
package.
Fast Acquisition Phase Lock Loop & Zero
Phase Restart Technique
•
5V Operation only
•
Low Operating Power
•
Sleep Mode
BLOCK DIAGRAM
'''''N,..----D---Q VCOCLK
SQUELCH
=
VEGC
BYP
Freq/f'hase LocK
Loop
F~\9f
Data Rata
WinclowShiIt
VCOF
Serial Port
D"""'"
Ragistsrs
1293 -
rev.
10-109
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbitls
FUNCTIONAL DESCRIPTION
AGC AMPLIFIER & AGC CONTROL
The SSI 34P3201 is a pulse detector and data
synchronizer circuit. Its two main functions are:
The AGC amplifier is to provide signal amplification
prior to pulse qualification. The amplifier gain is a linear
function of a gain control voltage, Figure 1. The gain
control voltage is either the BYP voltage when EGC =
logic high, or the VEGC voltage when EGC = logic low.
• Validate and time-position preserve the analog pulses
(IN±) from a read-write preamplifier.
• Extract the encoded data bit and its corresponding
clock signal.
The SSI 34P3201 major functional blocks are:
• AGC amplifier & AGC control
• Pulse qualifier
• Data synchronizer
• Window shift
In the normal Read mode, Le., with the AGC active, the
DIN± input signal is regulated to a nominal level which
is set by the voltage at the AGC pin. With the AGC pin
open, the nominal DIN± level is 1 Vppd (peak-to-peak
differential). This nominal DIN± level can be adjusted
with an extemal resistor tied from the AGC pin to either
VPA1 or AGND1, as shown in Figure 2. The DIN±
voltage level is nominally 1.0 VppdN x VAGC.
The AGC actions are current charging and discharging
the external BYP integrating capacitor. They are
described as follows:
• Serial port decode & registers
AGC Amplifier
Gain
120
Slope = 200 VN
63
6
2.56 V
V@ BYPIVEGC
FIGURE 1: AGC Amplifier Gain VS. BYPNEGC Voltage
p:
RAGC Rext
RAGC
11
~cc
+
AGC
- VAGC
YVAGC
'=' V@AGC = VAGC
Rext
+ (Vcc - VAGC) RAGC
RAGC + Rext
'='
V@AGC= VAGC Rext
RAGC + Rext
FIGURE 2: AGC Loop Reference Adjustment
10-110
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbit/s
Slow Decay 1 (R4, bit 0 = 0)
When the instantaneous DIN± signal is below the
nominal level, a slow decay current, 4.5 ~, discharges
the BYP capacitor. The AGC amplifier gain is increased
slowly.
Slow Decay 2 (R4, bit 0 = 1)
When the instantaneous DIN± signal is below the
nominal level, a slow decay current, 0.1 rnA, discharges
the BYP capacitor. The AGC amplifier gain is increased.
Slow Attack
When the instantaneous DIN± signal exceeds the
nominal level but is below 125% ofthe nominal level, a
slow attack current, 0.18 rnA, charges the BYP capacitor.
The AGC amplifier gain is decreased.
Fast Attack
When the instantaneous DIN± signal exceeds 125%of
the nominal level, the device enters a Fast Attack
mode. A fast attack current, 1.3 rnA, charges the BYP
capacitor. The AGC amplifier gain is quickly lowered.
Write-ta-Read Recovery
With a logic high to logic low transition of the WG, the
SSI34P3201 enters the Write-to-Read Recovery mode
Write
except while SQUELCH is set to high. The input
impedance remains in the low impedance state for
0.9 ps for fast input DC coupling recovery. The device
then restores to high input impedance state, and enters
into a Fast Decay mode for 0.9 ps. In the Fast Decay
mode, a continuous 0.1 rnA current discharges the
BYP capacitor. The AGC amplifier gain is increased
very quickly. This additional Fast Decay mode current
is disabled when the Slow Decay 2 mode is active.
Figure 3 shows the nominal write-to-read AGC action
timing.
The AGC input impedance is also controlled by the
SQUELCH pin. When SQUELCH is asserted high, the
AGC input impedance becomes low impedance.
The above AGC actions, except that of write-to-read
recovery, can be suspended with the HOLD =logic low.
The AGC amplifier gain is then held constant, except
for leakage effect.
With EGC = logic low, the AGC amplifier gain is
determined by the VEGC voltage. With a fixed external
DC voltage, or a second AGC control loop at the VEGC
pin, the AGC amplifier gain is set independent of the
on-chip AGC control loop, such as when read signal is
over a servo demodulation field.
The AGC amplifier outputs are emitterfolloweroutputs.
Read
Write
WGlI-____
WG
...--.
10.9ps.
•
Low Input
Impedance
Read
i
~
10.9~1
Low Input
Impedance
•
•
Fast Discharge I+=+t
s~6.9~~
-----J...~:
II
omr-n-•
I
F~
I 0.9 ~I
SWitch
125% of nominal level
OIN±
E~veloe
I
I
Envelope
I
• Fast
I
IAttack,
I Fast
IDecay
•
•
•I Fast •I Slow ••
I
I
•
I
•
Fast : Slow •
: Decay IAttaCk:
I
I
I
I
IAttackjAttack.
I
I
I
~
:
:
FIGURE 3: AGC Action Timing In Wrlte-to-Read Recovery
10-111
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbit/s
FUNCTIONAL DESCRIPTION
Time Qualification
(continued)
PULSE QUALIFIER
The pulse qualifier validates each DIN± peak by a
combination of level qualification and time qualification.
In level qualification, a hysteresis comparator eliminates
errors dueto low level additive noise.lntime qualification,
the AGC amplifier output is time differentiated to locate
the signal peaks in time.
Level Qualification
The level qualification is accomplished by comparing
the DIN± Signal with a set threshold. The SSI34P3201
allows two ways of setting the thresholds: fixed threshold
or DIN± tracking threshold. Fixed threshold can be
simply set by a DC voltage at the HYS pin, such as a
resistor from VPA1 to ground. The threshold at the
comparator can be computed as: Hysteresis Gain x
V@HYS. For high performance system application,
however, DIN± tracking threshold is recommended.
DIN± tracking threshold has the advantage of shorter
write-to-read recovery time and lower probability of
error with input amplitude drop out. The threshold is
designed as a percentage of the DIN± peak voltage.
This technique can be implemented by feeding the
LEVEL output, through a resistor divider, to the HYS
pin. The LEVEL output, amplified peak capture of DIN±
Signal, can be computed as: Level Gain x DIN±ppd.
With the resistor divider, a fraction ofthe LEVEL output
is presented at the HYS pin. The threshold. as a
function of DIN±, can be summarized as: Level Gain x
Resistor Dividing Ratio x Hysteresis Gain x DIN±ppd.
For a typical case of 1 Vppd DIN± signal, assume equal
value resistors in the divider network, the threshold is 1
x O.Sx 0.38 x 1 = 0.19V. This represents 38% threshold
on a 1 Vppd signal. While both the Level Gain and the
Hysteresis Gain bear a moderate tolerance due to
typical process variation, they inversely track each
other to yield a much tighter threshold accuracy in a
closed loop.
While the extemal resistor divider ratio determines the
qualification setting, the total resistance and the peak
capture capacitor should be optimized for the system
data rate. The RC time constant must be small enough
to allow good response to changing DIN± peak, but
large enough to provide a constant threshold after a
long duration of input absence.
Time qualification is used to locate DIN± peaks. With
time differentiation, each DIN± peak is translated into
a zero crossing, which clocks an on-chip flip-flop in the
pulse qualifier. The SSI 34P3201 supports on-chip or
off-chip differentiation.
ON-CHIP DIFFERENTIATION
The on-chip differentiation is accomplished by
connecting an external RLC network across the DIF±
pins. The DIF1-, DIF2-, and DIF3- pins are provided for
wide code rate variation. These differentiators are
selected by Register 4, bits 1 and 2. The DIN+ and
CIN+ pins should be tied together, as well as the DINand CIN- pins.
OFF-CHIP DIFFERENTIATION
For constant density recording applications, a
differentiation function with a low pass cut-off frequency
tracking data rate can maximize the signal-to-noise
ratio performance. A time differentiated input can be
applied allhe CIN± pins, separated from the DIN± pins.
A 1.2 kQ resistor should be placed across the DIF±
pins.
This function can best be supported by the Silicon
Systems programmable filters, such as the SSI32 F8030
and the SSI 32F8130/8131. The filters feature both a
normal low pass output and a differentiated low pass
output. The low pass cut -off frequency is programmable
by the user to track the data rate. The signal delays of
the two signal paths are well matched.
Qualified Read Data
Upon level and time qualification, a one-shot data
pulse is generated for every validated peak of the DIN±
signal. This read data pulse can be monitored at the
RDO pin, when OEN = logic low. In high speed normal
Read mode, itis recommended that the RDO output be
disabled for lower noise performance with OEN = logic
high. The pulse detector read data can be used as input
to the data synchronizer. Alternately, external input at
the RDI pin can be used as inputtothedata synchronizer.
Figure 4 summarizes the pulse detector function.
10-112
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbit/s
': Td1
DIN±
+ Hysteresis
Threshold
- Hysteresis
Threshold
DOUT
~
Differentiator
Comparator
Output
COUT
I
Td3": : Pulse Detector
Read Data
Output Oioo)
~
f-- Td4
r----------
LrL.J
U-
FIGURE 4: Read Mode Pulse Detector Timing Diagram
DATA SYNCHRONIZER
The data synchronizer is used to extract the clock and
the encoded data signals from the read data signal.
The input source to the data synchronizer can be from
the pulse qualifier or from an external source via the
RDI pin.
The 881 34P3201 is designed to perform data
synchronization for operating data rates of 250K to
8.0M NRZ bits per second. Data rates are selected
through a combination of serial port register RO for +N
and serial port register R2 for veo center frequency.
The following is a partial list of possible data rates:
+N
Code Clk (MHz)
NRZ Data Rate
Encoding Format
VCO Freq
8 MbiVs
1,7 RLL
12
6 MbiVs
MFM
12
1
4 MbiUs
1,7 RLL
12
2
6.0
3.429 MbiUs
1,7 RLL
10.286
2
5.143
3.2 MbiUs
1,7 RLL
9.6
2
4.8
3.0 MbiUs
1,7 RLL
9.0
2
4.5
2.667 Mbit/s
1,7 RLL
8.0
2
4.0
2.4 MbiUs
MFM
9.6
2
4.8
1.6 MbiUs
1,7 RLL
9.6
4
2.4
1.2 MbiVs
MFM
9.6
4
2.4
1.0 MbiUs
MFM
8.0
4
2.0
600 KbiUs
MFM
9.6
8
1.2
500 KbiUs
FM
8.0
8
1.0
10-113
12.0
12.0
II
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbit/s
DATA SYNCHRONIZER
(continued)
Forthe 1,7 RLL format, the encoded bit rate, as well as
the data synchronizer clock, is at 1.5 times the NRZ
data rate. For the MFM encoding format, the encoded
bit rate, as well as the data synchronizer clock, is at
twice the NRZ data rate. Thus, the required data
synchronizer clock rate is from 0.5 to 12 MHz.
To accommodate the wide data rate dynamic range,
the SSI 34P3201 employs a novel data synchronizer
phase locked loop (PLL) architecture (see Block
Diagram). While the voltage controlled oscillator (VCO)
operates only between 6 MHz to 12 MHz, a dividedown function is used to generate the lower frequency
clocks.
With the serial register RO programmed for a specific
divide-down factor and serial register R2 programmed
for a specific VCO center frequency, the SSI34P3201
would decode the proper NRZ data rate. The 1/2 code
cell delay duration is also set properly for each operating
mode.
When the SSI 34P3201 is in the Idle mode, the VCO
should lock to an external reference clock, FREF,
which needs to be the same frequency as the VCO
divided by N for proper operation.
The SSI34P3201 employs a dual mode phase detector:
Phase Lock mode and Frequency Lock mode. In the
Read mode, the mode of the phase detector is
programmable. With Fast Sync = logic low, the phase
detector operates in the Phase Lock mode whereby the
phase detector updates the PLL with each occurrence
of a read data pulse from the pulse qualifier. With Fast
Sync = logic high, the phase detector operates in the
Frequency Lock mode. In the Write and Idle modes, the
Frequency Lock mode phase detector is continuously
enabled, thus maintaining both phase and frequency
lock. Figure 5 shows the phase detector transfer
function. By acquiring both phase and frequency lock
to the FREF and utilizing azero phase restarttechnique,
false lock to the pulse detector read data is eliminated.
The phase detector incorporates a charge pump in
order to drive the loop filter directly. The polarity and
width of the output current pulses correspond to the
direction and magnitude olthe phase error. The charge
pump gain during the PLL acquisition phase in the
preamble area is controlled by LTD as shown in
Figure 6. The selection of Frequency Lock mode (Fast
sync 2: FS2) or Phase Lock mode (Fast sync 1: FS1)
during preamble area is controlled through the serial
port. The phase detector and charge pump output (high
Z) are disabled when COAST is low.
Because of the wide data rate dynamic range, the SSI
34P3201 provides five high impedancellow impedance
switchable nodes, FLO-4, for external loop filter
component switching. The impedance of these FLO-4
nodes are controlled by register 2 bit 0 and register 3 bit
0-3. When the node is in high impedance state, the
external component connected to this node is switched
out. When the node is in low impedance state, the
external component is included inthe loopfi/ter network.
The various operating modes of the data synchronizer
are discussed in the Operation Modes section.
Average
Output Current
Average
Output Current
Phase
Error
21< Phase
Error
(a) Phase lock Mode
(b) Frequency lock Mode
Note 1) 10 is the magnitude of the charge pump current
2) Phase error is relative to the +N counter output period
FIGURE 5: Phase Detector Transfer Function
10-114
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbitls
PHASE LOCK MODE
PREAMBL
RG
LTD
DATA
I
Fast Sync =0
---i
MODE:
IDLE
F81
58
Phase Detection:
FREQ
PHASE
PHASE
Gain:
LOW
HIGH
LOW
FREQUENCY LOCK MODE
I
RG
LTD
PREAMBL
DATA
I
Fast Sync = 1
---i
MODE:
IDLE
F82
88
Phase Detection:
FREQ
FREQ
PHASE
GaIn:
LOW
HIGH
LOW
FIGURE 6: PLL Acquisition Mode During Preamble
II
10-115
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbit/s
FUNCTIONAL DESCRIPTION
(continued)
WINDOW SHIFT
To enhance the data decode function, the SSI34P3201
supports a window shift function for code rates 3 Mbitls
and above. Shifting the pulse width of the % code cell
delay output shilts the relative position of the OLYO
DATA pulse within the decode window. This powerful
capability, supported through serial register R1, easily
facilitates defect mappings, automatic calibration,
window margin testing, error recovery, and systematic
error cancellation.
The window shift can be set to ±20%, ±30% or ±40%
ofthedecode half window. Figure 7definesthedirection
of the window shift. Reier to the Serial Port Decode &
Registers section for serial port register assignment.
Encoded
Data
I 0I0 I 1I 0I
Encoded
Data
I 0I 0 I 1I 0I
Encoded
Data
I 0I 0 I 1I 0I
RDf
--u---
RDf
--u---
RDf
--u---
DLYD
DATAl
~
DLYD
DATAl
DLYD
DATA2
+N Clock
-r4-s-L
JlJ1ful
DLYD
DATA2
I I Iq I
Decode
Window
I
Decode
Window
I
+N
Clock
---LJU1l-ul
I
II I
I
(a) Early
DLYD
DATAl
DLYD
DATA2
+N Clock
--Jirl
.JLJl.1ru-L
I
Decode
Window
(b) Normal
II I
I
(c) Late
FIGURE 7: Decode Window & Window Shift Directions
SERIAL PORT DECODE & REGISTERS
The SSI34P3201 provides a 3-pin serial port to facilitate
the following digital controls:
• Phase/Frequency Lock mode (Register 0: Bit 3)
• N value (Register 0: Bits 2-0)
The 3 serial port pins are SOEN, SOl and SCLK. Figure
8 shows a timing diagramofthe serial data transmission.
Each data transmission consists of an 8-bit packet, Bit
7 being the most significant bit (MSB). The 8-bit packet
is divided into two fields: Bit 7-4 address field, Bit 3odata field. All register bits are reset to 0 at power-up.
• Window shift (Register 1: Bits 3-0)
• VCO center frequency (Register 2: Bits 3-1)
• FLO-4 switch control (Register 2: Bit 0,
Register 3: Bits 3-0)
• Data sychronizer input source (Register 4: Bit 3)
OIF (Register 4: Bits 2 - 1)
• ISO (Register 4: Bit 0)
10-116
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbit/s
The register assignment is as follows:
Register 0
Bit 3
Address 0011
Register 3
Address 0000
Register 2
Fast Sync register
Bits 3, 2,1,0
Bit 0
0: Phase Lock mode (FS1)
o
1 : Freq Lock mode (FS2)
FLO-4 Switch Control
Register 3
o0
0 0
All off (All Hi Z)
x
x x x 1
FLO on (FLO : Low Z)
N register
x
x x 1 x
FL1 on (FL 1 : Low Z)
000
N= 1
x
x 1 x x
FL2 on (FL2 : Low Z)
001
2
x
1 x x x
FL3 on (FL3 : Low Z)
010
4
x x x x
FL40n (FL4 : Low Z)
Bits 2,1,0
o1
Register 1
1 :
8
X X:
16
Address 0001
Register 4
Address 0100
Bit 3
Data synchronizer input source
o
Window Shift
Bit 3
From interanl pulse qualification
output
From the RDI pin
0: Disable
Bit 2, 1
1 : Enable
o0
o1
o
Bit 2
0: Direction Early
1 : Direction Late
Bit 1, 0
DIF and ISD Register
DIF Register
DIF1DIF2DIF3Unused
Window shift magnitude
Bit 0
o 0 : 40% of half window
o 1 : 30% of half window
o : 20% of half window
ISD Register
o
Slow Decay 1
Slow Decay 2
: 0% of half window
Register 2
Address 0010
Bits 3,2,1
000
001
010
011
o0
o1
1 0
1 1
Bit 0
veo register
veo center frequency = 6 MHz
veo center frequency = 7 MHz
veo center frequency = 8 MHz
veo center frequency =9 MHz
veo center frequency = 10 MHz
veo center frequency = 11 MHz
veo center frequency = 12 MHz
veo center frequency = 13 MHz
MSB of FL register
10-117
II
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbitls
clocks data bit
I
I
I
I
j4- TC~
SCLK
:r2A
~
I
SDEN
J
:Isc~tf lalls
SDEN hold
SDENsebJll
I wrt SCLK lalls
I
T3 : T4
~ SDEN lalls
IT2BI ~:~ II> SCLK
wrt SCLK lalls I
:ls~r~IaIiS
load data
into register
1c___--.
~'-----
l"
."
.
i. . .
1,---,. r----. r--, r----. r--, r - - , r---,. r - - , , - - -
SDI
FIGURE 8: Serial Port Timing Diagram
OPERATION MODES
The SSI 34P3201 can support the following operating modes:
Mode
Idle
WG
RG
HOLD
EGC
SLEEP
LTD
0
0
1
1
1
X
0
0
0
1
1
X
0
0
X
0
1
X
0
1
1
1
1
1
VCO locked to FREF
AGC active
Frequency lock phase detection
I charge pump X1 (KD2)
Idle
VCO locked to FREF
AGC gain held constant by BYP
Frequency lock phase detection
I charge pump X1 (KD2)
Idle
VCO locked to FREF
AGC gain held constant by VEGC
Frequency lock phase detection
I charge pump X1 (KD2)
Read
VCO locked to Pulse Qualifier DLYD DATA
AGC active
Phase lock phase detection
I charge pump X1 (KD2)
10-118
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbitls
WG
RG
HOLD
EGC
SLEEP
LTD
Read
VCO locked to Pulse Qualifier DLYD DATA
AGC gain held constant by BYP
Phase lock phase detection
I charge pump Xi (KD2)
0
1
0
1
1
1
Read
VCO locked to Pulse Qualifier DLYD DATA
AGC gain held constant by VEGC
Phase lock phase detection
I charge pump Xi (KD2)
0
1
X
0
1
1
Write
AGC gain held constant by BYP
Input impedance lowered
vce locked to FREF
1
X
X
1
1
X
Write
AGC gain held constant by VEGC
Input impedance lowered
VCO locked to FREF
1
X
X
0
1
X
FS1
0
1
X
X
1
0
FS2
Serial port register 0, bit 3 = 1
vce locked to preamble
Frequency lock phase detection
I charge pump X3 (KDi)
0
1
X
X
1
0
Power Shutdown
X
X
X
X
0
X
Mode
Serial port register 0, bit 3 = 0
VCO locked to preamble
Phase lock phase detection
! charge pump X3 (KDi)
II
10-119
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbitls
1
1
I~TWRr..1
1
I
:,...-'""""\1
RRC
SRD
1
1
4 - TSRD ---..•
1
FIGURE 10: Read Mode Timing
WRITE MODE
In the Write mode, the SSI34P3201 pulse detector is
disabled and preset for the subsequent Read mode.
The digital circuitry is disabled, the input AGC amplifier
gain is held at its previous value and the AGC amplifier
input impedance is reduced.
Holding the AGC amplifier gain and reducing input
impedance shortens system write-to-read recovery
times.
The lowered input impedance improves settling time
by reducing the time constant of the network between
the SSI34P3201 and a head preamplifier such as the
5S1 34R1203R. Write-to-read timing is controlled to
maintain the reduced impedance for 0.9 ~ before the
AGC circuitry is activated. Coupling capacitors should
be chosen with as Iowa value as possible consistent
with adequate bandwidth to allow more rapid settling.
POWER SHUTDOWN
For reduced power dissipation during non-operational
periods, the 5S134P3201 can be switched into a Sleep
mode. The serial port registers will remain powered up
during Sleep mode. Therefore no reprogramming is
required following a logic low to logiC high SLEEP
transition.
II
10-121
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbitls
PIN DESCRIPTION
ANALOG INPUT PINS
NAME
TYPE
IN+,IN-
I
AGC amplifier inputs.
DESCRIPTION
DIN+,DIN-
I
Data inputs to hysteresis comparator and full-wave rectifier.
CIN+,CIN-
I
Data inputs to time-channel qualification.
HYS
I
Hysteresis input to establish the hysteresis threshold of the data comparator.
AGC
I
The voltage at the AGC pin determines the nominal level at the DIN± pins.
BYP
I
The voltage at the BYP pin controls the AGC amplifier gain when EGC = logic
high.
VEGC
I
The voltage at the VEGC pin controls the AGC amplifier gain when EGC = logic
low.
FREF
I
TTL reference clock input to data synchronizer.
DEN
I
TTL ADO Output Enable input: ADO enabled with DEN = logic low, ADO
forced to high with DEN = logic high.
ADI
I
TTL external input source to the data synchronize~.
AG
I
TTL Read Gate input.
WG
I
TTL Write Gate input. Enables Write mode.
LTD
I
TTL Lock to Data asynchronous input.
SLEEP
I
TTL power shutdown control. The device is in Power Shutdown mode when
SLEEP = logic low. The device is in normal operational state wMn SLEEP =
logic high, or left open.
HOLD
I
TTL input that holds the AGC gain constant when pulled low. When left open,
this input is at logic high.
EGC
I
TTL input. When EGC = logic low, the AGC amplifier gain is controlled by the
voltage at VEGC. When EGC = logic high, or left open, the AGC amplifier gain
is controlled by the voltage at BYP.
SQUELCH
I
TTLinput. The AGC input impedance is reduced when SQUELCH = logic high.
When SQUELCH = logic low, the AGC input impedance is normal.
COAST
I
TTL input. When COAST = logic low, the phase detector and charge pump
output are disabled (high Z).
SOl
I
TTL Serial Data Input.
SCLK
I
TTL Serial Clock. Negative edge triggered clock input for serial register.
SDEN
I
TTL Serial Data Enable. A high level enables data loading. The data is latched
on the falling edge of SO EN.
DIGITAL INPUT PINS
10-122
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbitls
ANALOG OUTPUT PINS
NAME
TYPE
DESCRIPTION
OUT+.OUT-
0
AGC amplifier emitter follower output pins.
LEVEL
0
Open emitter output from fullwave rectifier that may be used for input to the
HYSpin.
TRKAA
0
Open emitter output from fullwave rectifier with an additional gain of 1.333 over
LEVEL.
FLO-4
0
Loop filter connection pins. Either high impedance or low impedance state.
ANALOG CONTROL PINS
DIF+. DIF1-,
DIF2-. DIF3-
0
Pins for external differentiating network. When off-chip differentiator is used.
a 1.2 kg resistor should be tied across DIF+ and DIFX-.
IREF
0
Input reference currentfor VCO bias. A 7.5 kg resistor should be tied between
IREF and VPA2.
FLTR
0
Loop filter pin.
DIGITAL OUTPUT PINS
RDO
0
TTL output of the pulse detector read data. This output is enabled with
OEN = logic low. It is forced high with OEN = logic high.
RRC
0
Read Reference Clock: a multiplexed TTL clock source used by the controller.
In the Read mode, this clock is the encoded bit rate. In the Write mode, it is
FREF. No short clock pulses are generated during a mode change.
SRD
0
Synchronized Read Data: a TTL read data that has been re-synchronized to
read clock.
COUT
0
Time qualification one-shot test point: open emitter output which requires an
external 1 kn pull down resistor when used.
DOUT
0
Data comparator test point: open emitter output which requires an external
1 kg pull down resistor when used.
DRD
0
Delay Read Data test point: open emitter output which requires an external
5 kn pull down resistor when used.
VCOCLK
0
VCO test point: open emitter output which requires an external 5 kg pull down
resistor when used.
-
Analog supply to the pulse detector section.
POWER & GROUND
VPA1
VPA2
VPD
AGND1
AGND2
DGND
Analog supply to the data synchronizer section.
Digital supply.
Analog ground to the pulse detector section.
Analog ground to the data synchronizer section.
Digital ground.
10-123
II
SSI34P3201
Pulse Detector & Data Synchronizer,
250K to 8.0 Mbit/s
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, the recommended operating conditions apply.
ABSOLUTE MAXIMUM RATINGS
Operation beyond the maximum ratings may damage the device.
PARAMETER
RATING
Storage Temperature
-65 to + 150°C
Junction Operating Temperature
+130°C
Supply Voltage, VPA 1-2, VPD
-0.7 to +7V
Voltage Applied to Inputs
-0.3 to Supply + 0.3V
RECOMMENDED OPERATING CONDITIONS
PARAMETER
RATING
Supply voltage
4.5V < VPA1, VPA2, VPD < 5.5V
Ambient Temperature, Ta
O°C < Ta < 70°C
POWER SUPPLY
PARAMETER
CONDITION
Power Dissipation Active
PO
Power Down Dissipation
PDS
MIN
NOM
MAX
UNIT
Outputs unloaded
4.5V < VPA1, VPA2, VPD
~
a.
~
+
~
()
0z
~
Cl
~ <
~ 0
t-!.
:::>
0
+
~
0
~
0
z+ ~
()
(3
ECG
SLEEP
2
39
LEVEL
38
HYS
TRKAA
SQUELCH
3
37
SOl
4
36
VPA1
SCLK
5
35
DIF+
SDEN
6
34
DIF1-
OEN
7
33
DIF2-
RDO
8
32
DIF3-
RDI
9
31
AGND2
COAST
10
30
DOUT
LTD
11
29
COUT
RRC
12
28
FREF
WG
13
27
ORO
14 15 16 17 18 19 20 21
22 23 24 25 26
0
:.: 0 a: "~ -'
w
a.
'" u..-''" :; -'0
~ a:
z0 -' >
CIl
Cl
8 "-~ 90 >~ "- "- "- "0
~
52-Lead QFP
ORDERING INFORMATION
ORDER NO.
PART DESCRIPTION
SSI 34P3201 - 52-Lead QFP
34P3201-CG
PKG.MARK
34P3201-CG
Preliminary Dala: Indicates a product not completely released to production. The specifications are based on preliminary evaluations and
are nol guaranteed. Small quantities are available, and Silicon Systems should be consulted for current infonnation.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data
sheet is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1993 Silicon Systems, Inc.
10-132
1293 - rev.
SSI 34R1203R
+5V, 2, 4-Channel, 3-Terminal
Read/Write Device
January 1994
DESCRIPTION
FEATURES
The SSI34R1203R is a bipolar monolithic integrated
circuit designed for use with center-tapped ferrite or
MIG recording heads. It provides a low noise read path
with selectable gains of 85 and 250 VIV, write current
control, and data protection circuitry for as many as 4
channels. Power supply fault protection is provided by
disabling the write current generator during power
sequencing. A Power Down mode (Idle) is provided to
reduce power consumption to less than 10 mW. Included is a write current boost feature which can be
selected without using additional external resistors.
•
•
•
Internal 7500 damping resistors are provided. It requires only a +5V power supply and is available in a
surface mount package.
•
•
•
•
•
•
Pin selectable gain, 250 VN and 85 VN
+5V only power supply
Low power
- Pd s; 220 mW Read mode
- Pd s; 10 mW Idle mode
High Performance
- Input nOise = 1.2 nV/fflz max.
- Input capacitance = 19 pF max.
- Write current range = 15 - 50 mA
- Head voltage swing = 6.0 Vpk
Designed for center-tapped ferrite or MIG
heads
TTL selectable write current boost
Power supply fault protection
Includes write unsafe detection
Enhanced Write to Read recovery
PIN DIAGRAM
BLOCK DIAGRAM
vee
GNO
WUS
VCT
GND
HOX
24
fiG
~
NIC
2
23
HOX
3
22
RiW
HOY
4
21
WC
H1X
5
20
ROY
H1V
6
H2X
7
34R1203R 19
4
Channels 18
HSO
H2Y
8
17
HS1
H3X
9
16
vee
H3Y
10
15
WOI
VCT
11
14
WUS
12
13
WllOOSi
HOY
ROX
H1X
ROY
ROX
H1Y
H2X
HSO~m~.
II
H2Y
H3X
vee
HS111B
H3Y
24-Lead VSOP
CAUTION: Use handling procedures necessary
for a static sensitive component.
SSI34R1203R
+5V, 2, 4-Channel, 3-Terminal
ReadlWrite Device
DESCRIPTION
WRITE MODE
In addition, the power supply vonage level is monitored
by a circuit that inhibits the write current if VCC is too
low to permit valid data recording.
A source of recording current is provided to the head
center tap by an internal voltage reference, VCT. The
current is conducted through the head alternately into
an HnX terminal or an HnY terminal according to the
state of an internal flip-flop. The flip-flop is triggered by
the negative transition of the Write Data Input line
(WDI). A preceding read mode selection initializes the
write data flip-flop, WDFF, to pass write currentthrough
the "X" side of the head. The write current rnagnitude is
deterrnined by the value of an external resistor Rwc
connected between WC terminal and GND, and is
given by:
READ MODE
In Read Mode, (RIW high and CS low), the circuit
functions as a low noise gain selectable differential
amplifier. The read amplifier input terminals are determined by the Head Select inputs. The read amplifier
outputs (RDX, ROY) are emitter follower sources,
providing low impedance outputs. The amplifier polarity is non-inverting between HnX, HnYinputs and RDX,
ROY outputs. Taking HG low selects high gain
(250 VN). Taking HG high or open selects low
gain (85 VN).
Iw = KlRwc, where K = Write Current Constant
In addition, this current can be given a 30% boost
without switching in additional resistance values by
pulling WBOOST low.
WRITE MODE FAULT DETECT CIRCUIT
Several circuits are dedicated to detecting fault conditions associated with the Write mode. A logical high
level will be present at the Write Unsafe (WUS) terminal if any of the following write faun conditions are
present:
• Head open
•
•
•
•
•
•
IDLE MODE
Taking CS high selects the Idle mode which switches
the RDX and ROY outputs into a high impedance state
and deactivates the device. Power consumption in this
mode is held to a minimum.
MODE SELECTION AND INDICATION CIRCUIT
Logical control inputs which select mode and head
channel are TIL compatible. Their functions are described in Table 1 and Table 2.
TABLE 1: Head Select Table
Head Selected
HS1
HSO
Head shorted
0
0
0
Head shorted to ground
1
0
1
2
1
0
3
1
1
Head center tap open
No write current
WDI frequency too low
Device in read or idle mode
TABLE 2: Mode Select Table
The Write Unsafe output is open-collector and is usually terminated by an external resistor connected to
VCC. Two negative transitions on WDI, after the fault
is corrected, will clear the WUS flag.
A safe condition, WUS low , requires alternating vonage spikes on both HnX and HnY that exceed VCT +
1.5Vat a rate equalto or higher than the Minimum Rate
of WDI for Safe condition.
10-134
Mode
Select
Selected
Mode
CS
R/W
1
X
Indicating &
Faun Outputs
WUS
Idle
high
0
1'
Read
high
0
0
Write
active
SSI34R1203R
+5V, 2, 4-Channel, 3-Terminal
Read/Write Device
PIN DESCRIPTION
NAME
110
DESCRIPTION
I"
Head Select: Logical combinations select one of four Heads. See Table 1
CS
I
Chip Select: a low level enables device. Has internal pull-up resistor.
RJW
I"
ReadlWrite: a high level selects read mode. Has internal pull-up resistor.
WUS
0"
WDI
I"
HSO, HS1
Write Unsafe: a high level indicates an unsafe writing condition.
Write Data In: negative transition toggles direction of head current.
HOX-H3X
HOY-H3Y
1/0
X, Y head connections
RDX, RDY
0"
X, Y Read Data: differential read signal output.
-
WC
Write Current: used to set the magnitude of the write current.
WBOOST
I"
A logic low signal on this pin increases the magnitude of write current by
typically 30%.
VCT
-
Voltage Center Tap: voltage source for head center tap.
VCC
-
+5V
GND
HG
I'
Gain select: HG low selects 250 VN. HG high or open selects 85 VN.
Ground
" When more than one RIW device is used, these signals can be wire OR'ed with unselected RIW devices.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND. Currents into device are positive.)
PARAMETER
RATING
DC Supply Voltage
VCC
Digital Input Voltage Range
HS1, HSO, WDI, RIW, CS, WBOOST, HG
-0.3 to +6 VDC
-0.3 to (VCC + 0.3 VDC)
Head Port Voltage Range
VH
-0.3 to (VCC + 3.0 VDC)
Write Current Pin Voltage
Vwc
-0.3 to (VCC + 0.3 VDC)
WUS Pin Voltage Range
Vwus
Write Current Zero-Peak
IW
60 rnA
RDX, RDY Output Current
10
-10 rnA
RDX, RDY Pin Voltage
-0.3 to +6.0 VDC
VCC +0.3 VDC
VCT Output Current Range
IVCT
-60 rnA to +10 rnA
WUS Output Current Range
Iwus
-0.1 rnA to +10 rnA
Storage Temperature Range
Tstg
Package Temperature (20 sec Reflow)
-65 to 150°C
215°C
10-135
I
SSI34R1203R
+5V, 2, 4-Channel, 3-Terminal
Read/Write Device
RECOMMENDED OPERATION CONDITIONS
PARAMETER
DC Supply Voltage
CONDITIONS
VCC
MIN
NOM
MAX
UNITS
4.75
5.0
5.25
VDC
Head Inductance
Lh
1
15
JJ.H
Write Current Range
IW
15
50
mA
Tj
+25
+135
°C
Junction Temperature Range
DC CHARACTERISTICS
(Unless otherwise specified, recommended operating conditions apply.)
POWER SUPPLY
VCC Supply Current (ICC)
Read Mode
32
42
mA
Idle Mode
1A
2.0
mA
31 + Iw 44+ Iw
Write Mode
Power Dissipation
Idle Mode
Write Mode
mA
220
mW
7
10.5
mW
155 +
Slw
230 +
S.51w
mW
0.8
VDC
160
Read Mode
DIGITAL I/O
Input Low Voltage
CS, R/Vi WDI, HSO, HS1,
WBOOST, HG
VIL
Input High Voltage
CS, R/Vi WDI, HSO, HS1,
WBOOST, HG
VIH
Input Low Current
CS, RlW WDI, HSO, HS1,
WBOOST,HG
ilL
VIL = OAV
Input High Current
CS, R/W WDI, HSO, HS1,
WBOOST, HG
IIH
VIH = 2.7V
20
J.lA
WUS Output Low Voltage
VOL
IOL=4.0 mA
0.5
VDC
WUS Output High Current
IOH
VOH =5.0V
100
J.lA
2.0
VDC
-OA
mA
WRITE MODE
Center Tap Voltage
VCT
Write Mode/Idle Mode
Head Current (per side)
Write Mode, Voltage Fault
0::::; VCC::::; 3.9V
Write Current Range
1.0 k.Q ::::; Rwc ::::; 3.3 k.Q
10-136
VDC
Vee - 0.9
-200
200
J.lA
15
50
mA
SSI 34R1203R
+5V, 2, 4-Channel, 3-Terminal
Read/Write Device
WRITE MODE (continued)
PARAMETER
CONDITIONS
Write Current Constant uK"
MIN
46
NOM
50
MAX
UNITS
54
mA-kQ
1.35
rnA/rnA
rnA/rnA
20
Iwc to Head Current Gain
WBOOST - Write Current
Boost Factor
WBOOST=Low
1.25
1.30
Unselected Head Leakage Current
85
ROX. ROY Common Mode
Output Voltage
~
Vcc-3 Vee - 2.4 Vcc - 2
VOC
WOI Minimum Pulse Width
PWH VIL ;::: 0.2V
11
ns
See Figure 1
PWL VIN ;::: 2.4V
4
ns
Vee - 1.5
VOC
READ MODE
Center Tap Voltage
VCT
Input Bias Current (per side)
From VCT to HnX or HnY
Output Offset Voltage
ROX-RDY
-200
Common Mode Output Voltage
RDX + RDY
2
20
Vee - 2.4
60
!lA
+200
mV
3.5
VDC
+100
mV
2
Common Mode Output Voltage
Change from Write to Read Mode
-100
FAULT DETECTION CHARACTERISTICS
Unless otherwise specified recommended conditions apply. Iw = 30 rnA. Lh = 51J.H. F(WDI) = 10 MHz.
Minimum Rate of WDI Input for
Safe condition
kHz
150
Maximum Rate of WDI Input for
Unsafe condition
50
Minimum voltage value for
guaranteed write current turn-on
VDC
4.4
Maximum voltage value for
guaranteed write current turn-off
3.9
10-137
kHz
VDC
I
SSI34R1203R
+5V, 2, 4-Channel, 3-Terminal
Read/Write Device
DYNAMIC CHARACTERISTICS AND TIMING
(Unless otherwise specified, recommended operating conditions apply and Iw = 30 rnA, Lh = 5 j.l.H,
f(WDI) = 5 MHz, CL(RDX, RDY) s 20 pF.)
WRITE MODE
PARAMETER
CONDITIONS
Differential Head Voltage Swing
Unselected Head Transient Current
1 ~H s Lh s 9.5
MIN
NOM
6.0
6.4
~H
Differential Output Capacitance
Differential Output Resistance
600
MAX
UNITS
2
mA(pk)
15
pF
960
0
V(pk)
READ MODE
Differential Voltage Gain
Yin = 1 mVrms @ 1 MHz
HG = High
HG = Low
Bandwidth (-3dB)
IZsl < 50, Yin = 1 mVpp
Input Noise Voltage
BW= 15 MHz,
Lh = 0, Rh = 0
Differential Input Capacitance
Yin = 1 mVrms, f = 5MHz
Differentiallnpul Resistance
68
200
250
30
60
AC input voltage where
gain falls to 90% of its
small signal gain value,
f =5 MHz
Common Mode Rejection Ratio
Vem = 100 mVpp@
1 MHz < f < 10 MHz
50
Power Supply Rejection Ratio
LlVee =100 mVpp@
1 MHz < f < 10 MHz
45
Channel Separation
Unselected Channels:
Yin = 20 mVpp
1 MHz < f < 10 MHz
45
102
VN
300
VN
MHz
0.85
1.2
nVI',iHz
16
19
pF
460
Dynamic Range
860
75
dB
dB
dB
54
30
AC Coupled Load,
RDXlo RDY
10-138
±1.5
0
mVpp
2
RDX, RDY Single Ended Output
Resistance
Output Current
85
0
rnA
SSI34R1203R
+5V, 2, 4-Channel, 3-Terminal
Read/Write Device
SWITCHING CHARACTERISTICS
PARAMETER
RfW
CS
NOM
MAX
UNITS
Read to Write
R/W to 90% of write current
50
400
ns
Write to Read
R/Wto 90% of
100 mV 10 MHz read signal
envelope or to 10% IW
0.15
1.0
I1s
Unselect to Select
CS to 90% of
100 mV 10 MHz
read signal envelope
1.0
2.0
I1S
0.05
0.6
I1s
0.6
I1S
30
I1S
350
ns
40
ns
2
ns
20
ns
Select to Unselect
CSto 10% Ih
HSO, 1 to any Head
WUS
MIN
CONDITIONS
To 90% of 100 mV 10 MHz
read signal envelope
7
Safe to Unsafe (TD1)
Unsafe to Safe (TD2)
Write mode, after fault
cleared after 2nd transition
Head Current
Rh
= 0, Lh = 0
Prop. Delay (TD3)
From 50% points
Asymmetry
WDI has 50% Duty Cycle
and 1 ns Rise/Fall Time
Rise/Fall Time
10% - 90% Points
25
4
PWL*
---+-
WDI
~
WUS
~
r
TDl
TD2
-4-TD3
HEAD
CURRENT
( Ix -Iy)
* measured at 1.5V
FIGURE 1: Write Mode Timing Diagram
10-139
•
I
SSI34R1203R
+5V, 2, 4-Channel, 3-Terminal
Read/Write Device
+5V
VCT
SSI34R1203R
READ
DATA
SS132P549 READ DATA PROCESSOR
TTL
Control
----------------------------------------------~HSn
WC
GND
00
Rwc
see Note 3
NOTES
1.
2.
3.
Limit DC current from RDX and RDY to 100 J.lA and load capacitance to 20 pF. In multi-chip application
these outputs can be wire-OR'ed.
The power bypassing capacitor must be located close to the 34R1203R with its ground returned directly
to device ground, with as short a path as possible.
To reduce ringing due to stray capacitance this resistor should be located close to the 34R1203R.
Where this is not desirable a series resistor can be used to buffer a long WC line.
FIGURE 2: Applications Information
10-140
SSI 34R1203R
+5V, 2, 4-Channel, 3-Terminal
Read/Write Device
PACKAGE PIN DESIGNATIONS
(Top View)
GNO
FiG
NIC
~
HOX
RiW
HOY
we
H1X
ROY
H1Y
ROX
H2X
HSO
H2Y
HS1
H3X
vee
H3Y
WOI
veT
WUS
vee
WBOOSf
THERMAL CHARACTERISTICS: Gja
24-lead VSOP
CAUTION: Use handling procedures necessary
for a static sensitive component.
24-Lead VSOP
ORDERING INFORMATION
PART DESCRIPTION
ORDERING NUMBER
PACKAGE MARK
SS134R1203R-4CV
34R1203R-4CV
SSI 34R1203R
24-Lead VSOP
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights orlrademarks 01 Silicon Systems. Silicon Systems
reserves the rightto make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX: (714) 573-6914
0194 - rev.
10-141
©1993 Silicon Systems, Inc.
II
Notes:
10-142
Section
11
PACKAGING/ORDERING
INFORMATION
II
11
11-0
Silicon Systems
Packaging Index
DUAL·IN·L1NE PACKAGE (DIP)
Plastic
Ceramic
PINS
PAGE NO.
8,14,16 & 18
11-3
20,22,24 & 24S
11-4
28,32 & 40
11-5
8,14,16&18
11-6
22,24 & 28
11-7
20, 28
11-8
SURFACE MOUNTED DEVICES (SMD)
Quad (PLCC)
Quad Flatpack (QFP)
Thin Quad Flatpack (TQFP)
Very Thin Quad Flatpack (VTQFP)
Ultra Thin Quad Flatpack (UTQFP)
Small Outline (SOIC)
Package
Width (mil)
Pitch (mil)
32&44
11-9
52 &68
11-10
52 & 100
11-11
128
11-12
32 &48
11-13
64 & 100
11-14
120 & 128
11-15
48&64
11-16
100
11-17
120
11-18
64 & 100
11-19
8,14 & 16 SON
11-20
16,18,20,24 & 28 SOL
11-21
SON
150
34 SOL
11-22
SOL
300
32 SOW
11-22
SOW
400
SOM
300
I
0.8
36S0M
11-22
44S0M
11-23
Very Small Outline Package (VSOP)
20 & 24
11-23
Very Thin Small Outline Package (VTSOP)
16 & 20
11-24
Ultra Thin Small Outline Package (UTSOP)
24&36
11-25
11-1
II
SHIPPING OPTIONS
R
Tape and Real
PIN COUNT
OPTION
32B
32C
320
N
32F
32H
32M
32P
32R
33P
348
340
34P
34R
SSP
66F
67F
730
73K
73M
75T
78A
78P
780
HOD Interface
HOD Controlier
HOD Data Recovery
Electronic Filter
HOD Head Positioning
HOD Motor Speed Controller
HOD Pulse Detection
HOD ReadlWrite Amp
Optical Pulse Detection
FDD Interface
FDD Data Recovery
FDD Pulse Detection
FDD ReadlWrite Amp
Tapa Drive Pulse Detection
Standard Automotive
Standard Automotive
Modem Devlos Set
K-Series Modem
Modem/Modem Support
Tone Signalling
Analog Telecom
Digital Telecom
LAN Products
PACKAGE TYPE
MODIFIERS
F
J
K
L
LP
LT
LV
LZ
M
S
SL
R
RM
T
U
U
V
W
X
y
Z
C
F
G
GT
GV
FAX Capab11Jty
Burn-In (168 Hours)
Bum-In (48 Hours)
Low Power
AT Commands, MNP5
AT Commands
AT Commands, MNP5, V.42
AT Commands, MNP5, V.42, V,42bis
Mirror Image
Serial Version
Low Power Serial
Damping Resistor
Resistor, Mirror Image
100 VN Read Mode Gain (RIW)
150 VN Read Mode Gain (RIW)
(for HOD products)
UART (for Comm products)
200 VN Read Mode Gain (RIW)
250 VN Read Mode Gain (RIW)
300 V N Read Mode Gain (RIW)
350 VN Read Mode Gain (RIW)
400 VN Read Mode Gain (FVW)
cannot US9 A-£ in left position
H
P
T
S
N
L
W
M
V
VT
Side-Brazed Ceramic
Flatpack
OFP, Quad Flatpack (2.5 mm height)
TOFP, Thin Ouad Flatpack (1.4 mm height)
Very Thin Quad Flalpack (1.0 mm height)
PLCC
Plastic Dip
Metal Can
Plastic, Skinny Dip
Small Outline, Narrow (150 mil.)
Small Outline, Large (300 miJ.)
SmaIJ Qutline, Wide (400 mil.)
Small Outline, (300 mil.), Fine Pitch (0.8 mm)
Very Smali Outline (220 miJ.) Fine Pitch (0.65
Very Thin Small Outline (1.0 mm height)
TEMPERATURE RANGE
C
I
Commercial (0 "C to +70 "C)
Industrial (-40·C to +85 ·C)
~CJ)
0.=
CD _.
:::::!. (')
::l 0
(Q::l
::lCJ)
0',<
""t
en
Q)
CD
3 ....
=3
g en
Package Information
Plastic DIP
PIN NO. 1
IDENT.
0.770(19 .... )
0.745 (18.923)
0.400 (10.160)
0.350 (9.980)
~~
0.050(1.270)
0.285 (7.239)
I
0.215 (5.461)
0.145 (3.660)
,
0.150 (3.810)
0.125 (3.175)
t
,
J~
0.310 (7.874)
0.020 (0.508)
0-150
f~HHPHHH
HH
HHH
0.200 (5.080)
0.140 (3.556
0.150 (3.810)
0.125 (3.175
)
r-0.l00lYP.(2.540)
0.015 (0.381)
0.023 (0.584)
8-Pin Plastic
-~
~ ~ ~ -----r
~
~~
0.070 (1.778)
0.015 (0.381)
r-0.l001YP.(2.540)
0.015 (0.381)
0.023 (0.584)
,r
14-Pin Plastic
0.770(19.558)
0.745118,923)
16-Pin Plastic
::±;mRRMN-+
~~
r-0.l001YP.(2.54OI
0.015 (0.381)
~
~'4:::::::J~
0.930 ZU22)
O.aao(22.352)
HI·Pin Plastic
~~~lll~ H H H H H
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H H H
g.~:~810)
.
(175)
-1
11-1
-~
~
~O.l00l"lP.(2.S40)
-1r-~
MI5(0.381)
11-3
II
Package Information
IDENT.
PIN NO.
,-00'
-:ra;:58)*
0.260 (6.096)
(6.604)
G'ra
1.040 (26.416)
1.010 (25.654)
'--
20 Pin Plastic
*24S Pin Plastic
* 1.195 (30.353\
1.175 (29.845)
~:~~~~;:~:)~WV1\AMM) *~.:g~~!g.::~i
~ ~==~
* 0.135 (3.429)
~
*0140(3.556)0.150(3.810)
0.120 (3.048) 0.125 (3.175)
~~
~
r-0.100TYP.(2.540)
-
-
0.015 (0.381)
0.023 (0.584)
1.100 (27.940)
1.080 (27.432)
...
22-Pin Plastic
I
24-Pin Plastic
~.Gl0 (15.494)
.585 (14.859)
11-4
Y
0-15"
___
Package Information
~,~: ::::: ::: :: ]f
I.
)~\~~CI52).·.·. ~
~
•. 220(.....
60tr:
.'253."
'-m-
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28-Pin Plastic
1
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1.670{42.418)
1.625(41.275)
[=!t~~m\ ~ :ll!W
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32.pln Plastic
~
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:.015(1381)
(
)
2.070 (SU7I)
2.020(5.....)
4O-i'ln PlastIc
11-5
II
Cerdip
Package Information
-D.To...
!
0.290 (7.366)
IDENT.
0.280
-----I-
~
I
0.550 13.970
0.380 (9.652)
0.332 (8.433)
0.280 (7.112)
0.332
J
PIN NO. 1
I
O.no(19.55B)
0.690 (17.526)
~
0.325 (8255)
0.290(7.366)
MIN
0.020~
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0100TVP-1
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0.175(4.445)
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~ .~-1 r- ~.,..
.
0.038 (0.965) 0.125 (3.115)
UN
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O.01210~05!
0.175 (4.445)
-I
14-Pin Cerdip
0.332 (8.433)
0.280 (7.112)
0.830 (21.<162)
0.770 (19.558)
0.325 (8.255)
0.290 (7.366)
i-,---
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0.020
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0.030 (0.965)
MIN
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0.175 (4:445)
0.105 (2....7)
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0.021 (0.533)
0.015 (0.381) ---
.
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0.332
MAX
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0.105
O175
.
0.175
0.125
0.060
0.038
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0.125 (3.175)
0.030 (2.413)
~'-~ ~~~~~~]r
I·
16-Pin Cerdip
~
-1f0.021
0.Q15
11-6
(I.-
~~
18-Pin Cerdip
Package Information
~:,-p~
0.432 (10,973)
MAX
22-Pin Cerdip
·
0.420 (10.668)
~~~T~~m·~' ~~-::-~::::
MAX
I I
I I
~:: ~~::~} -+ I--
0,175 (4.445)
0,'00TYP,(2.540)-1
~
II
~
II
0.060 (1,524)
0.038 (0.965)
0-15"
0,023 (0,584)
0.015 (0.381)
..,
~,-1 ~ ~ ~ ~ ~ ~ ~ ~ ~]
J-
0.020 10.508)
0.632 (16.053)
MAX
24-Pin Cerdip
'1
,='"--
tI ~g
T
0.01010.254)"'.
0.07011.718)
R
0.190 (.U26)
~
~
I I
II
O.100TYP.
0.060(1.524)
(2.540)
0.038(0.965)
0.023 (0.584)
0.015(0.381)
0.175(4.4451
II
mm:mi
0.023(0.584)
~
0-15"
0.632 (16.053)
MAX
0.625(15.875)
MAX
O.023(O.584~~lr-
~
a.lOOTYP.
(2.540)
0.060(1.524)
~
0.023(0.584)
0.015(0.381)
0-15-
11-7
~
28-Pln Cerdlp
II
Package Information
0.395 (10.033)
(9.779)
~_ _ _ 0.38s
0.354 (8.992)
Quad (PLCC)
~
I
~---0.350 ( 8 . 8 9 ) - -
___
rt
0.395 (10.033)
MM
~_ _ _ r
0.042 (1.067)
________
,.~·056(lA22)
PIN NO.1 IDENT.J
0.354 (8.992)
O.~T" " T" "0
(8......,.-.89)T""""""T""""T""r-r--'
104--~. (7.366)
0.320 (8.128)
0.050 TYP (1.27)
20-Pin Quad PLCC
0.495 (12.573)
0.485 (12.319)
[
[
o.495 (12.573)
.485 (12.319)
[
[
r
r
[
0.075 (1.905)
0.065 (1.651)
]
PIN NO.1 IDENT.J
]
]
0
0
J
.165(:r~r------...
I
.160(ltl-l-l+l~r-lJL~
~
--!I I/4--
0.456 (11.65 0)
0)
.~ ~~ ~~ l[
~
0.020 (0.506)
.
"'I"~.~. ..
'_I"·..
28-Pin Quad PLCC
11-8
0.ojO(1.270)
0.016 (0.406)
0.390 (9.906)
0.430 (10.922)
r
0.045 (1.140)
0.020 (0.508)
Package Information
Ir-.449(11.4O)~I
."3111.51).
IT-~,~J
iT
595 (15.11)
:515(14.86)
32-Pin Quad PLCC
:::~:::~
--.----t~-JT
PIN NO.1 IDENT.
T
-J.
. -, L
I
0..,511.905)J
~
O.'.. !..9';
."
0.200('.000)
--l I--
0 .... (1270)
0.016(0.406)
~
0.S66(16.6&2)
44-Pin Quad PLCC
11-9
LLt
-.T
:::~\~~:
O~(16.002},
0690114.966)
II
Packag e Information
.785(19.939)
.795 (20.193)
n
=""'l
.m«.b(~::;:;::;ir~AFi~-,,~., I
_~~
\t .-
I
L ~1
'05OTYP(l'j!j)
.016 (0.406)
.020 (0.506)
.045 (1.140)
.020 (0.506)
.690 (17.272)
.730 (18.542)
52-Pin Quad PLCC
.985 (25.019)
.995 (25.273)
..
--.
.045(1.140)
.020 (0.506)
68-Pin Quad PLCC
11-10
Package Information
Quad Flatpack (QFP)
52-Lead Quad Flatpack
NOTE: Controlling dimensions are in mm
U3{O.078)
2.13(0.084)
140------
13.77(0.542)
14.03 (0.552)
~I'--------- ::~:~::::---------I'I
1 - - - - - :!:~~:~:~~:----o-j
f - - - - - - - :~:~~:~:~~~~------l
100-Lead Quad Flatpack
NOTE: Controlling dimensions are in mm
11-11
II
Package Information
'."(O.772)
20.12(0.792)
~
~
3.62(O"") _
~1
_
--I
14.12(0.55&)
0.70 (0.028)
~
U(O.102j·
2.8(0.110)
··'·(O·OO6)~1
0.30 (0.012)
•
•
16.95 (0.667)
17.45 (0.687)
128-Lead Quad Flatpack
NOTE: Controlling dimensions are in mm
11-12
I
Package Information
Thin Quad Flatpack (TQFP)
8.7 (0.343)
9.3 (0.366)
...-_ _ _f - _ 24
17
32-Lead Thin Quad Flatpack
NOTE: Controlling dimensions are in mm
8.7(0.343)
9.3(0.366)
48-Lead Thin Quad Flatpack
NOTE: Controlling dimensions are in mm
II
0.60 (0.024) Typ.
11-13
Package Information
54-lead Thin Quad Flatpack
NOTE: Controlling dimensions are in mm
""1-1-------- ,~~~~::) --------1-1
1 - - - - - - - - ~:::~~:::~: - - - - - - - 4
100-lead Thin Quad Flatpack
15.7(0.618)
16.3(0.641)
NOTE: Controlling dimensions are in mm
PIN No. 1 Indicator
1 - - - - - - - t31:.kOi~~3i9~O
,
0.00(0)
0.20 (0.008)
11-14
Package Information
120-lead Thin Quad Flatpack
15.7 (0.618)
16.3 (0.641)
NOTE: Controlling dimensions are in mm
PIN No.1 Indicator
- - l b : : = r = 1===iL~~
0.18 (0.007)
0.27 (0.01 t)
0.40 TYP.(O.016)
1.40 (0.055)
1.60 (0.063)
0.20 (0.008)
~I
~~uuuuuuuu) ~
21.7(0.'~)
I
22.3(0.87.)
~--------~!:~;~:~~--------------~
•
r-
0.50
(0.Q197)TYP
I
·1
128-lead Thin Quad Flatpack
NOTE: Controlling dimensions are in mm
11-15
I
'°"-11
0.70 (0.028)
Package Information
Very Thin Quad Flatpack (VTQFP)
8,7(0.343)
9.3 (0.366)
48-Lead VTQFP
NOTE: Controlling dimensions are in mm
Pin #1 Identification
14----
,oo;r:--r-il
--i f..-
~
6.8(0.268) SO _ _ _~
7.2 (0.283)
0.60 (O,024)
64-Lead VTQFP
NOTE: Controlling dimensions are in mm
Pin'1 Identificajon
""'I-r------ 9~:~;.(~~::~ -------.j_j
11-16
Package Information
\ - - - - - - - - - - 15.7(0.618) _ _ _ _ _ _ _ _+l~1
16.3 (0.641)
15.1 (0.618)
16.3 (0.641)
PIN No. 1 Indicator
13.8(0.543) SO _ _ _ _ __
14.2 (0.559)
j.- 0.60 (0.024) TYP. --j
r-
1.00 (0.039)
1.20 (0.047)
I
0.18 (0.007)
0.27 (0.011)
1aD-Lead VTQFP
NOTE: Controlling dimensions are in mm
II
11-17
Package Information
1----------
15.7(0.618) " - - - - - - - - - - - - 1
16,3 (0.641)
15.7 (0.618)
16.3 (0.641)
PIN No. 1 Indicator
I_
13.80 (0.543) sa
14.20 (0.559)
.1
1.00 (0.039)
1.20 (0.047)
~~=::s::~==r=*=L
0.1J! (0.007)
0.27 (0.011)
0.40 TYP .(0.016)
120-Lead VTQFP
NOTE: Controlling dimensions are in mm
11-18
0.00(0)
0.20 (0.008)
Package Information
Ultra Thin Quad Flatpack (UTQFP)
64-Lead Ultra Thin Quad Flatpack
~I
NOTE: Controlling dimensions are in mm
Pin" identification
1--1-------- 9;:.~~~~------....·'"1
0.00(0)
0.20(0.008)
f
0.70 (0.027)
0.90 (0.035)
t
100-Lead Ultra Thin Quad Flatpack
15.7 (0.618)
16.3(0.641)
NOTE: Controlling dimensions are in mm
PIN No.1 Indicator
0.70 (0.027)
1 - - - - - - - -,1'73;:l-!.k",OiS:"'::'tJ9iT~'- - - - - - - 1 0.90(0.035)
,
11-19
I
Small Outline (SON)
Package Information
r-
-1
.050 TYP. (1.270)
•
.160 (4.064)
.150 (3.Bl0)
8-Lead SON
t
.200 (5.0BO)
.245 (6.223)
-.230 (5.B42)
.1B5 (4.699)
.010 (0.254)
.070(1.77B)'~
.060 (1.524)
~ Q..RJ:LHJl~
.016 nom (0.40)
\
I .:::::
\
8
1
--I f..-
r
1.003(0.076)
.185 (4.699)
-.170 (4.31B)
,
0
--I
r-
o.oso TYP. (1.270)
0.160 (4.064)
0.150 (3.810)
PIN NO.1 - - . - . .
BEVEL
0.D70(1.778)
0.060(1.524)
14-Lead SON
---'-
0.3SO (8.990)
0.245 (6.223)
0.330 (8.382)
0.230 (5.842)
0.010 (0.254)
'~
L
I 0.003(0.076)
~
--..f J..-
0.016 nom
(o:;-f
-1
r-
.OSOTYP. (1.270)
---,.160 (4.084)
.150 (3.810)
16-Lead SON
.400 (10.160)
.245 (6.223)
.380 (9.652)
. 070(1.778)
060(1.524)
.230 (5.842)
r~
.010 (0.254)
1.003 (0.076)
--L
L
--..f J..-
.016 nom (0.40)
1
(
\
fO:=
i=O
.185 (4.699)
.170 (4.318)
11-20
Package Information
-1
r-
Small Outline (SOL)
-1
.050 TYP. (1.270)
I .285 (~239)
I .285 (7.239)
.420 (10.668)
PINN01_~:;:;::::;::;::;::;:::;:::;:::;:;::::;:::;:::;::;::::~-*-
.390 (9.906)
-'-l';:::;=;:rn=r;:=r;::;=;=;:;::;:::;L--L!-
IUUl~ UUI
BEVEL
r
.'10(2.794)t
.092(2.336)
\
(
F~ J
BEVEL
.445 (11.303)
.395(10.033)1
.010 (0.254)
.320 (6.128)
I .003(0.076)
.110(2.794)
.092 (2.336)
L~~
L
~ i--.016 nom (0 40)
r-
-1
.050TYP. (1.270)
,-
.305 (7.747)
Co'
=(6.509)
.285 (7.239)
:
~ :~V~~I-F ::::~;: II II IIl1l--±-
.495(12.573)
_ II _
~ ~.016nom(0.40)
.050 TYP. (1.270)
---,-
.390 (9.906)
~~v~fl_F .515(13.081)~-.-L i
C~
r-
.420 (10.668)
.285 (7.239)
010 (0.254)
.320 (8.128)
~
.110(2.790)
~OO3(O.076l
C
~
.010 (0.254)
~~003(O'076)
~-~-~.~.-~----~--
.092 (2.336)
---.
-I1-0I6nom(0.40)
I
f
24-Lead SOL
20-Lead SOL
-1
r-
.050 TYP. (1.270)
:~ '-(F
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~~
28-Lead SOL
~ UUUUUI
.605(17.653) - ,
.092 (2.336)
t
18-Lead SOL
.305 (7.747)
.110(2.790)
1.003 (0.076)
lli~---..L
f
-1
.092 (2.336)
,010 (0.254)
fL~
16-Lead SOL
.110(2.790)
I
U UI
.335 (8.509)
c==:J
~ f..-.016 nom (0.40)
.050 TYP. (1.270)
I
+
.305 (7.747)
.
PIN NO.1
r-
f~
L
.010 (0.254)
1.003 (0.076)
---..L
~ i--016nOm(040)
t
.335 (8.509)
.320 (S.128)
11-21
II
Package Information
Small Outline (SOL/SOM/SOW)
--1 r--
0.040 TVP. (1.02)
-r
0.305 (7.741)
0.285 (7.239)
PINNO.1~
.~,
0.110(2.790),
F=:::::;~
-L
t===:::==\~
34-Lead SOL
0.010 (0.254)
I 0.003(0.076)
0.092 (2.336)L rnAH.PJ~-L
j
r
L0016 (040)TYP
--1 r--
0.050 TVP. (1.270)
0.405 (10.287)
0.385 (9.779)
:'\~'-F~:~~
0.110(2.790)'~
0.092 {2.336)
L
32-Lead SOW
I
~
-..I J..-
0.016 nom (0.40)
r
0.435 (11.049)
0.420 (10.668)
0.010 (0.254)
0.003 (0.076)
3S-Lead SOM
(Fine Pitch)
O.110(2.790)C~
~
I~
10.003
(0.076)
0.092(2.336)
j Lo.".(o.75ITVP. j L'.'31s(o.80ITYP.j LO.•:::!:TvP.
11-22
Package Information
~~V~~'
-,
EI EI EI EI EI EI EI
0.730
0.305 (7.747)
0.420 (10.668)
0.285 (7.239)
0.390 (9.906)
(1B.542) EI EI EI EI EI EI ElI~
i
44-Lead SOM
(Fine Pitch)
r-0.71O(1B.034)~
rt
0.0115(0.29)
j
~
~~:: ~:~: L cil1t111nnI1l1I1i1)J1PJ1JtnntiH-foOO3 (0.076)
j Lo.030(0.75)1YP. j Lo.0315 (O.BO)TYP.j LO.,2.0.20
Package Information
VSOP
NOTE: Controlling dimensions are in mm
L
0.77 (0.030)
,-
0.53 (0.021)
B.1 (0.319)
1
PtNNO.1--..
BEVEL
F
5.25 !.211)
(0.207)
7.25 (0.285)
7.15(0.2B1)
U U U
I
L
--II---
0.35 (0.014)
0.25 (0.010)
+
I
2.05(0.OB1)f~
1.BO(0.071)
7.7 (0.303)
I"
20-Lead VSOP
I
~
f
0 (0)
0.20 (o.oOB)
-1
NOTE: Controlling dimensions are in mm
7.4 (0.291)
-,
,-
O.65~~026)
~CF:~ ~ :::::::1 +
7.B (0.307)
---' L
r-
~ uuuUI
0.75 (0.03)
7.7(0.303)
0.45 (0.02)
1.45(0.057)
1.05(0.041)
~
f~
L
-.j I---
0.28 (0.011)
0.1B (0.007)
11-23
0.20 (O.OOB)
I
~
f
0(0.0)
24-Lead VSOP
II
Package Information
VTSOP
NOTE: Controlling dimensions are in mm
~~T
6.1 0 (0.240)
1 6.70 (0.264)
1
PINNO.1~
IU U I
BEVEL
1.1 0 Max
~
C
0.65
1
4.90(0.,,,,
5 .10 (0.201)
U U
I
4.50(0.176)
4.30 (0.169)
I
0.00 (0)
mr-r.,.....,--,-rr-TT........,......,...,.....,.-T"I
0.70 (0.028)
0.50 (0.20)
esc
16-Lead VTSOP
NOTE: Controlling dimensions are in mm
[~
F
0.65
esc
4.50 (0.176)
4.30 (0.169)
6.60 (0.260)
6.40 (0.252)
I
UUU
I
0.00(0)
~20(o.o08)
1
20-Lead VTSOP
11-24
0.70 (0.028)
0.50 (0.20)
Package Information
UTSOP
~~~T
I~Iu
~
I::::
u=;=;=n=;=;=;=r6'20(0'244)~UI~
ru
u
U
6,60(0,259)
U
24-Lead UTSOP
u
4,20 (0,165)
~
4,60 (0,181)
0,00 (0)
0,60 Typ,
(0,024)
36-Lead UTSOP
i
6.10 (0.240)
6.70 (0.264)
+
I~I
C
~
4.60 (0.1B1)
0]0 (0.027)
0.90 (0.035)
C
~I 1 "0,00(0)
0-~.20 (0.008)
O,SO Typ, (0,0197)
j
L
0,22 Typ, (0.009)
j
Lf
11-25
d1(
----I f.-
hs
0.60 Typ,
(0.024)
I
cfi/igyt~
Small Form Factor Pac.kage Selec.tor Guide
11-26
~~
Small form factor Package Selector Guide
I
11-27
~~
Small form factor Package Selector Guide
11-28
Section
12
SALES OFFICESI
DISTRIBUTORS
II
12
12-0
United States
Regional Offices & Sales Representatives
NORTHWEST
HEADQUARTERS
Jon Tammel, Area Director
Silicon Systems, Inc.
2001 Gateway Place
Suite 301 East
San Jose, CA 95110
Ph: (408) 432-7100
FAX: (408) 453-5988
CALIFORNIA
Magna Sales
Santa Clara
Ph: (408) 727-8753
FAX: (408) 727-8573
IOAHO
Western Technical Sales
Boise
Ph: (208) 376-8700
FAX: (208) 376-8706
MINNESOTA
COLORAOO
FLORIOA
MISSOURI
Lange Sales
Littleton
Ph: (303) 795-3600
FAX: (303) 795-0373
Colorado Springs
Ph: (719) 632-8340
FAX: (719) 632-8419
Technology Mktg. Assoc. ITMA)
Orlando
Ph: (407) 281-9195
FAX: (407) 281-3971
West Palm Beach
Ph: (407) 964-0009
FAX: (407) 965-0650
St Petersburg
Ph: (813) 577-3304
FAX: (813) 577-0935
rush & west associates, inc.
St Louis
Ph: (314) 965-3322
FAX: (314) 965-3529
MONTANA
Lange Sales
Boise, ID
Ph: (208) 323-0713
FAX: (208) 323-0834
NEW MEXICO
Western High Tech Marketing, Inc.
Albuquerque
Ph: (505) 884-2256
FAX (505) 884-2258
TEXAS
Western Technical Sales
Beaverton
Ph: (503) 644-8860
FAX: (503) 644-8200
OM Associates, Inc.
Austin
Ph (512) 794-9971
FAX (512) 794-9987
Richardson
Ph: (214) 690-6746
FAX: (214) 690-8721
Houston
Ph: (713) 789-4426
FAX: (713) 789-4825
WASHINGTON
UTAH
OHMS Technology, Inc.
Minneapolis
Ph: (612) 932-2920
FAX: (612) 932-2918
OREGON
Western Technical Sales
Bellevue
Ph: (206) 641-3900
FAX: (206) 641-5829
Spokane
Ph: (509) 922-7600
FAX: (509) 922-7603
SOUTHWESTERN
HEADQUARTERS
Larry Cleland, Area Manager
Silicon Systems, Inc.
3445 Penrose Place, Suite 140
Boulder, CO 80301
Ph: (303) 440-9780
FAX (303) 440-9783
Tustin Office
Ph: (714) 832-5310
FAX: (714) 832-5247
ARIZONA
Western High Tech Marketing, Inc.
Scottsdale
Ph: (602) 860-2702
FAX: (602) 860-2712
CALIFORNIA
Hadden Associates
San Diego
Ph: (619) 565-9444
FAX: (619) 565-1802
SC Cubed
Thousand Oaks
Ph (805) 496-7307
FAX: (805) 495-360'1
Tustin
Ph: (714) 731-9206
FAX: (714) 731-7801
Lange Sales
Salt lllke City
Ph: (801) 487 -0843
FAX: (801) 484-5408
EASTERN
HEADQUARTERS
Wayne Taylor, Area Manager
Silicon Systems, Inc.
53 Stiles Road
Salem, NH 03079
Ph: (603) 898-1444
FAX: (603) 898-9538
Georgia Sales Office
Dan Kilcourse
Ph: (404) 409-8405
FAX (404) 368-1060
Detroit Sales Office
Fabian Battaglia
108 E. Grand River, Suite 6
Brighton, MI 48116
Ph: (313) 229-2811
FAX: (313) 229-3266
GEORGIA
Technology Mktg. Assoc. ITMA)
Norcross
Ph: (404) 446-3565
FAX: (404) 446-0569
ILLINOIS
Circuit Sales, Inc.
Itasca
Ph: (708) 773-0200
FAX (708) 773-2721
INDIANA
Arete Sales, Inc.
Fort Wayne
Ph (219) 423-1478
FAX: (219) 420-1440
Indianapolis
Ph: (317) 293-1425
FAX (317) 293-1428
Micro Components, Inc
Kokomo
Ph: (317) 454-6988
FAX (317) 454-6987
IOWA
Cahill, Schmitz & Howe
Cedar Rapids
Ph: (319) 377-8219
FAX (319) 377-0958
rush & west associates, Inc.
Davenport
Ph: (319) 388-9494
FAX: (319) 388-9609
NEW JERSEY - SOUTH
OmniSales
Erdenheim, PA
Ph: (215) 233-4600
FAX: (215) 233-4702
NEW YORK
Electra Sales
Rochester
Ph: (716) 427-7860
FAX: (716) 427-0614
East Syracuse
Ph: (315) 463-1248
FAX: (315) 463-1717
Technical Marketing Group
Melville
Ph (516) 351-8833
FAX: (516) 351-8667
NO. CAROLINA
Technology Mktg. Assoc. ITMA)
Raleigh
Ph: (919) 872-5104
FAX: (919) 872-5086
OHIO
PENNSYLVANIA
See Indiana
Omni Sales
Erdenheim
Ph (215) 233-4600
FAX: (215) 233-4702
MARYLAND
MASSACHUSETIS
Orion Group
Southington
Ph: (203) 621-8371
FAX: (203) 628-0494
Technical Marketing Group
West Caldwell
Ph: (201) 226-3300
FAX: (201) 226-9518
KENTUCKY
Huntsville
CONNECTICUT
NEW JERSEY - NORTH
rush & west associates, Inc.
Olathe
Ph (913) 764-2700
FAX (913) 764-0096
KANSAS
Technology Mktg. Assoc. ITMA)
Ph: (205) 883-7893
FAX: (205) 882-6162
(Refer calls to)
rush & west associates, inc.
Davenport, IA
Makin Associates
Cincinnati
Ph (513) 871-2424
FAX: (513) 871-2524
Dublin
Ph: (614) 793-9545
FAX: (614) 793-0256
Mayfield Village
Ph: (216) 461-3500
FAX: (216) 461-1335
Burgin-Kreh Associates
Baltimore
Ph: (410) 265-8500
FAX (410) 265-8536
ALABAMA
NEBRASKA
Mill-Bern Associates
Woburn
Ph (617) 932-3311
FAX: (617) 932-0511
MICHIGAN
Trilogy Marketing, Inc.
Bloomfield Hills
Ph: (313) 338-2470
FAX: (313) 338-6720
12-1
VIRGINIA
Burgin-Kreh Associates
Refer calls to
Burgin-Kreh. Maryland
WISCONSIN
Circuit Sales, Inc.
Waukesha
Ph (414) 542-6550
FAX: (414) 542-2711
I
International
Distributors & Sales Representatives
EUROPE
HEADQUARTERS
Neil Harrison, Area Manager
Silicon Systems, Europe
The Business Centre
Gor-ray House
758-760 Great Cambridge Rd.
Enfield
Middlesex EN13RN, England
Ph: (44) 81-443·7061
FAX: (44) 81-443-7022
TLX: 825824 BUSTEC G (ref. ENFIELD)
AUSTRIA
Codico Gmbh
Wien
Ph: (43) 1-86·24-28
FAX: (43) 1-86-32-57
BELGIUM
Alcorn Electronics nv/sa
Kontich
Ph: (32) 3·458·3033
FAX: (32) 3-458-3126
DENMARK
C-BB West
Ikast
Ph: (45) 9725-0816
FAX: (45) 9725-0815
ENGLAND
Magna Technology (Rep. Sales only)
Swallowfield, Brookshire
Ph: (44) 73-488·0211
FAX: (44) 73-488-2116
Pronto (Distribution Sales only)
liford, Essex
Ph: (44) 81-554-6222
FAX: (44) 81·518·3222
TLX: 895-4213 PRONTO G
Sirelta Microelectronics LTD
(Distribution Sales only)
Ph: (44) 73-425-8080
FAX: (44) 73·425·8070
FINLAND
Dy Bexab Finn-Crimp Ab
Espoo
Ph: (358) 0-5023200
FAX: (358) 0-5023294
TLX: 121926 KOMDL SF
FRANCE
ITALY
TURKEY
Cefra/S.p.A.
Gruppo Sprague Italiana
Milano
Ph: (39) 2-4801-2355
FAX: (39) 2-4800·8167
Inter
Istanbul
Ph: (90) 1·349-9400
FAX: (90) 1-349·9430
THE NETHERLANDS
RUSSIA
Alcom Electronics BV
2908 LJ Capelle NO IJSSEL
Ph: (31) 10-451-9533
FAX: (31) 10-458-6482
TLX: 26160
PT.G.
Laguna Beach, California
Ph: (714) 499-6736
FAR EAST
NORWAY
(excluding Japan)
Hans H Schive
Asker
Ph: (47) 66-900·900
FAX: (47) 66-904-484
TLX: 19124 SKIVE N
HEADQUARTERS
K. S. Ong, Area Manager
Silicon Systems, Singapore
3015A Ubi Road 1, #01-01
Kampong UBI Industrial Estate
Singapore 1440
Ph: (65) 744-7700
FAX: (65) 748-2431
PORTUGAL
Diode
Lisbon
Ph: (351) 1-571390
FAX: (351) 1-534987
AUSTRALIA
R&D Electronics
Victoria
Ph: (61) 3·558·0444
FAX: (61) 3-558·0955
SPAIN
Diode
Madrid
Ph: (34) 1-555·3686
FAX: (34) 1-556-7159
TLX: 42148 DIODE E
Ami/ron, SA
Madrid
Ph: (34) 1·542·09-06
FAX: (34) 1-541-76-55
HONG KONG
GET, Ltd.
Wanchai
Ph: (852) 520-0922
FAX: (852) 865-0639
SWEDEN
Bexab Technology AB
Taby
Ph: (46) 8·630-8800
FAX: (46) 8-732-7058
TLX: 136888 BEXTE S
EllypticAG
Zurich
Ph: (41) 1-493-1000
FAX: (41) 1-492-2255
TWX: 822-542 EL YP CH
At/antik E/eklronik GmbH
Munich
Ph: (49) 89-857-0000
FAX: (49) 89-857-3702
Hamburg
Ph: (49) 40-241-072
FAX: (49) 40·241-074
GREECE
Peter Caritato &Associates, Ltd.
Athens
Ph: (30) 1-902·0115
FAX: (30) 1-901-7024
TLX: 216-723 CARl GR
IRELAND
Memec Ireland, Ltd.
Limerick, Republic of Ireland
Ph: 353-61-411842
FAX: 353-61·411888
Monte Vista International
5976 W. Las Positas Blvd., Suite 220
Pleasanton, CA 94588 U.S.A.
Ph: (510) 463·8693
FAX: (510) 463-8732
REP. OF SOUTH AFRICA
Prime Source (PTY) LTO
Orange Grove
Ph: 27-11·444·7237
27·11-444-7298
ISRAEL
Rapac Electronics
Tel Aviv
Ph: (972) 3-6450333
FAX: (972) 3-493272
TLX: 342173 RAPAC IL
CHIHUAHUA & SONORA ONLY
Western High Tech. Marketing
Albuquerque, New Mexico
Ph: (505) 884-2256
FAX: (505) 884-2258
All other areas:
SDNIKA
Mexico City
Ph: (52) 5-754-6480
FAX: (52) 5-752-2787
Guadalajara
Ph: (52) 36-474250
FAX: (52) 36-473433
BRAZIL
PHILIPPINES
AFRICA (excluding So. Africa)
MEXICO
MALAYSIA
EllypticAG
GERMANY
Intemix
Tokyo
Ph: (81) 3-3369-1105
FAX: (81) 3-3363-8486
TLX: 781-26733
SOUTH AMERICA
Maribor
Ph: (38) 62-24561
AFRICA &MIDDLE EAST.
JAPAN
ARGENTINA
NEW ZEALAND
MISIL
Rungis Cedex
Ph: (33) 1-45-60-00-21
FAX: (33) 1·45·60-01-86
Den Suzuki, Area Manager
1-13·1 Nihonbashi, Chuo-Ku
Tokyo 103, Japan
Ph: (81) 3·5201·7231
FAX: (81) 3-5201-7232
TLX: J24270
J26937
Hanaro Corporation
Seoul
Ph: (82) 2·516·1144
FAX: (82) 2·516·1151
EASYLlNK: 62057328
Apex Electronics, Ltd.
Wellington
Ph: (64) 4-385-3404
FAX: (64) 4-385-3483
YUGOSLAVIA
SSi/TDK CORP. HEADQUARTERS
KOREA
Dynamar Computer Products
Penang
Ph: 604-228-1860
FAX: 604·228-1420
SWITZERLAND
JAPAN
Maetan Enterprises
Manila
Ph: (632) 812-3307
(632) 827-5154
FAX: (632) 818-3550
SINGAPORE
Dynamar Computer Products
Ph: (65) 281-3388
FAX: (65) 281-3308
TLX: RS26283 DYNAMA
TAIWAN
Dynamar Taiwan Co., Ltd.
Taipei
Ph: (886) 2·577·5670
FAX: (886) 2-577-5867
THAILAND
Dynamar Computer Products
Bangkok
Ph: (662) 376-0132
FAX: (662) 376-0133
12-2
YEL S. R. L
Buenos Aires
Ph: (45) 1-372-7140
FAX: (45) 1·476-2551
Hitech
Sao Paulo
Ph: (55) 11·536·0355
FAX: (55) 11-240-2650
CHILE
Victronics, Ltd.
Santiago Centro
Ph:
(56·2) 633-0237
(56-2) 633-2787
FAX: (56-2) 633-4432
CANADA
(Sales Offices)
BRITISH COLUMBIA
Enerlec
Richmond
Ph: (604) 273-0882
FAX: (604) 273·0884
ONTARIO
Har-Tech
Downsview
Ph: (416) 660-3419
FAX: (416) 660-5102
Nepean
Ph: (613) 726-9410
FAX: (613) 726-8834
QUEBEC
Har-Tech
Pointe Claire
Ph: (514) 694-6110
FAX: (514) 694-8501
North American
Authorized Distributor Offices
UNITED STATES
ALABAMA
Hamilton/Hal/-Mark
Huntsville
Ph (205) 837-8700
FAX:(205) 830-2565
Nu Horizons
Huntsville
Ph: (205) 722-9930
FAX: (205) 722-9348
CONNECTICUT
MICHIGAN
OKLAHOMA
Hamilton/Hall-Mark
Cheshire
Ph: (203) 271-2844
FAX: (203) 272-1704
Nu Horizons
Ph: (203) 265-0162
Hamilton/Hall-Mark
Detroit
Ph: (313) 416-5800
FAX (313) 416-5811
Hamilton/Hall-Mark
Tulsa
Ph: (918) 254-6110
FAX: (918) 254-6207
MINNESOTA
PENNSYLVANIA
Hamilton/Hal/-Mark
Bloomington
Ph: (612) 881-2600
FAX: (612) 881-9461
Nu Horizons
Mount Laurel, New Jersey
Ph: (215) 557-6450 - PA
Ph (609) 231-0900 - NJ
FAX: (609) 231-9510 - NJ FAX
FLORIDA
Aved, Inc.
Phoenix
Ph: (602) 951-9788
FAX: (602) 951-4182
Hamilton/Hall-Mark
SI. Petersburg
Ph: (813) 541-7440
FAX: (813) 544-4394
FI. Lauderdale
Ph (305) 484-5482
FAX: (305) 484-4740
Nu Horizons
FI. Lauderdale
Ph (305) 735-2555
FAX (305) 735-2880
CALIFORNIA
GEORGIA
ARIZONA
Hamilton/Hal/-Mark
Phoenix
Ph (602) 437 -1200
FAX (602) 437 -2348
Hamilton/Hall-Mark
Los Angeles
Ph (818) 773-4500
FAX: (818) 773-4555
Costa Mesa
Ph: (714) 641-4100
FAX: (714) 641-4149
Sacramento
Ph (916) 624-9781
FAX: (916) 961-0922
San Diego
Ph: (619) 751-7540
FAX (619) 277-6136
San Jose
Ph: (408) 432-4000
FAX: (408) 745-6679
Aved, Inc.
San Diego
Ph: (619) 558-8890
FAX: (619) 558-3018
Tustin
Ph (714) 573-5000
FAX: (714) 573-5050
Western Micro Technology
Greater LA area
Ph 1(800) 634-2248
Irvine
Ph: (714) 637-0200
FAX (714) 998-1883
San Diego
Ph: (619) 453-8430
FAX (619) 453-1465
Saratoga
Ph: (408) 725-1660
FAX: (408) 446-0413
COLORADO
Aved
Wheat Ridge
Ph: (303) 422-1701
FAX (303) 422-2529
Hamilton/Hall-Mark
Englewood
Ph (303) 790-1662
FAX (303) 790-4991
Hamilton/Hall-Mark
Norcross
Ph: (404) 623-4400
FAX: (404) 476-8806
Nu Horizons
Norcross
Ph: (404) 416-8666
FAX: (404) 416-9060
ILLINOIS
Hamilton/Hall-Mark
Bensenville
Ph (708) 860-3800
FAX: (708) 773-7969
INOIANA
Hamilton/Hall-Mark
Indianapolis
Ph: (317) 872-8875
FAX (317) 876-7165
KANSAS
Hamilton/Hal/-Mark
Lenexa
Ph: (913) 888-4747
FAX (913) 888-0523
MARYLAND
Hamilton/Hal/-Mark
Columbia
Ph: (410) 988-9800
FAX: (410) 381-2036
Nu Horizons
Columbia
Ph (410) 995-6330
FAX (410) 995-6332
MASSACHUSETTS
Hamilton/Hall-Mark
Peabody
Ph (508) 532-3701
FAX (508) 532-9802
Nu Horizons
Ph (617) 246-4442
FAX (617) 246-4462
Western Miero Technology
Ph (617) 273-2800
FAX: (617) 229-2815
MISSOURI
Hamilton/Hall-Mark
SI. Louis
Ph: (314) 291-5350
FAX (314) 291-0362
NEW JERSEY
Hamilton/Hall-Mark
No. New Jersey
Ph: (609) 751-2520
FAX (609) 751-2552
Fairtield
Ph (201) 515-3000
FAX: (201) 515-4475
Nu Horizons
Pine Brook
Ph (201) 882-8300
FAX: (201) 882-8398
Western Micro Technology
SO. New Jersey/Philadelphia
Ph (609) 596-7775
FAX: (609) 985-2797
NEW YORK
Hamilton/Hall-Mark
Ronkonkoma
Ph: (516) 737-0600
FAX (516) 737-0838
Rochester
Ph: (716) 475-9130
FAX (716) 475-9119
Nu Horizons
Amityville
Ph: (516) 226-6000
FAX: (516) 226-0082
Rochester
Ph: (716) 292-0777
FAX: (716) 292-0750
NORTH CAROLINA
HamiltonlHall-Mark
Raleigh
Ph (919) 872-0712
FAX: (919) 878-8729
TEXAS
Hamilton/Hall-Mark
Austin
Ph (512) 258-8848
FAX: (512) 258-3777
Dallas
Ph: (214) 553-4300
FAX: (214) 553-4395
Houston
Ph (713) 781-6100
FAX (713\ 953-8420
UTAH
Aved, Inc.
Salt Lake City
Ph: (801) 975-9500
FAX: (801) 977-0245
WASHINGTON
Western Micro Technology
Redmond
Ph (206) 828-2741
FAX (206) 828-2719
WISCONSIN
Hamilton/Hal/-Mark
New Berlin
Ph: (414) 797-7844
FAX: (414) 797-9259
CANADA
ONTARIO
Har- Tech Electronics
Downsview
Ph (416) 660-3419
FAX: (416) 660-5102
BRITISH COLUMBIA
Enerlee
Surrey
Ph: (604) 273-0882
FAX: (604) 273-0884
OHIO
HamiltonlHall-Mark
Solon
Ph: (216) 349-4632
FAX: (216) 248-4803
Worthington
Ph (614) 888-3313
FAX (614) 888-0767
OREGON
Western Micro Technology
Beaverton
Ph: (503) 629-2082
FAX: (503) 629-8645
12-3
II
Notes:
12-4
Section
13
APPLICATION
NOTES
PAGE #
CONTENTS
32F8001 Application Note ......................................................................... 13-1
32F8011 Application Note ......................................................................... 13-7
32F8020A Application Note ..................................................................... 13-13
32F8030 Application Note ....................................................................... 13-19
32P3000 Application Note ....................................................................... 13-25
32P4730/31/41/42/44/46 Application Note .............................................. 13-35
Servo Controllers and Motor Drivers ....................................................... 13-85
Sensorless Motor Speed Control ........................................................... 13-125
Snubbing Network for Spindle Motors ................................................... 13-167
Setting Speed Control Loop Compensation Gains ................................ 13-169
13
II
13-0
551 32F8001
Programmable Electronic Filter
November 1993
INTRODUCTION
The objectives of this application note are:
• To present a description of the SSI 32F8001
Analog filtering is a universal requirement in any signal
processing system. Filter design is now made easy
with the programmable filters from Silicon Systems
Inc. Whether the requirement is a fixed filtering characteristic or a programmable response, this family of
programmable filters offers distinct advantages of design simplicity, accuracy, versatility and board space
saving. Additional features, such as high frequency
boost, differentiated outputs, are also available. This
application note focuses on the SSI 32F8001, cutoff
frequency programmable from 9-27 MHz.
• To discuss its applications
• To present a typical fixed response design
• To present a programmable response application
VIN+
VO_NORM+
VIN-
VO_NORM-
VO_DIFF+
VO_DIFF-
VBP
VPTAT
IFP
VFP
PWRON
FBST
FIGURE 1: Block Diagram
INPUT
1.31703
s'+ S 1.68495 + 1.31703
2.95139
S'+ S 1.54203 + 2.95139
5.37034
S'+ S 1.14558 + 5.37034
~"1-::..-__-K..::S:...'_ _--r~ Transfer Function normalized for (j) = 2 1t fc = 1,
S'+ S 1.68495+ 1.31703
=
fc cutoff frequency
AN and AD are adjusted for unity gain (0 dB) at f
Frequency scaling s s I 2 1t fc
Eq. for fc 27 MHz, s sl[21t) (27 x 10')]
=
=
=
=.067 fc
FIGURE 2: The 551 32F8001 Transfer Function
CAUTION: Usa handling procedures necessary
1193 - rev.
13-1
for a static sensitive cofTl>Onent.
II
SSI32F8001
Programmable Electronic Filter
1.0 DESCRIPTION
• A current sink input can be fed into the IFP pin. A
1 kQ resistor should be placed across the VPTAT
and the VFP pins. With a current sink DAC, this
design also allows a microcontroller to change the
filter response dynamically. To achieve the highest
accuracy and temperature stability, the current
sink DAC should be referenced to the reference
voltage at the VPTAT pin. The design equation for
this current sink value is:
The SSI 32F8001 is a programmable 7-pole 0.05 0
equiripple linear phase low pass filter in a silicon bipolar
integrated circuit. Figures 1 and 2 show the block
diagram and the filter transfer function.
The SSI 32F8001 cutoff frequency and high frequency
boost can be independently controlled by two control
signals. Two sets offilteroutputs are available: normal
low pass output and differentiated low pass output. As
an equiripple linear phase type filter, the filter outputs
exhibit constant group delay in the pass band and out
to 1.75 Ic. Furthermore, the delays through the normal
output and the differentiated output are well matched.
The input and outputs of the SSI32F8001 are differential signals, requiring external AC coupling capacitors.
The given transfer function shows the relationship
between the input and the two sets of outputs. Typical
differential input resistance is 4 k,Q.
1.1
CUTOFF FREQUENCY PROGRAMMING
The cutoff frequency, defined to be the -3dB corner
frequency with no boost, can be programmed between
9 - 27 MHz. It can be set by one of three methods:
• A resistor can be inserted between the VPTAT
and the VFP pins. This setting is only used for a
fixed response design. The IFP pin should be left
open. The design equation for this resistor value
is:
Rx (kQ) = 27/ Ic (MHz)
IFP (rnA) = 0.0222 x (27 -Ic) (MHz)
A design example is given in Section 4.
1.2
VBP =VPTATx (10"(FB/20) - 1} / 3.46 where FB is in
dB.
Design example is given in Section 3.
A design example is given in Section 4.
With a finite boost, the magnitude response peaks at a
frequency slightly higher than the original cutoff frequency. The effective pass band bandwidth is wider.
• A current source input can be fed into the IFP pin.
The VFP pin should be left open. A current source
digital-to-analog converter (DAC), such as the
DACF in the SSI32D4661 Time Base Generator,
allows a microcontroller to change the filter response dynamically. To achieve the highest accuracy the current source DAC should be referenced to the reference voltage at the VPTAT pin.
The design equation forthis current source value
is:
IFP (rnA) = 0.0222 x
HIGH FREQUENCY BOOST CONTROL
The high frequency boost function is especially desirable for pulse slimming and magnitude equalization
applications. This function can be enabled or disabled
by a TIL logic input at the FBST pin. With FBST = TIL
logic high oropen, the amount of high frequency boost,
measured at the cutoff frequency, can be programmed
from 0 to 13.5 dB at Ic by a voltage input at the VBP pin.
External resistors can be designed in for a fixed filter
response. For a programmable high frequency boost,
a voltage DAC, such as the DACS in the SSI 3204661
Time Base Generator, can be used to control the VBP
pin. This input voltage should be made proportional to
the reference voltage at the VPTAT pin for accuracy.
The design equation for this control voltage is:
1.3
OTHER FEATURES OF THE SS132F8001
The SSI 32F8001 features excellent constant group
delay. At jc = 27 M Hz, the group delay variation from 0.2
Ic to jc is less than 0.5 ns. Furthermore, the high
frequency boost function does not affect the group delay
variation. Group delay variation is within ±4% out to
1.75/c.
Ic (MHz)
In addition to the normal low pass output, the SSI
32F8001 also provides a differentiated low pass output
of the input signal. The signal delay is well matched to
the normal output.
A design example is given in Section 4.
13-2
SSI32F8001
Programmable Electronic Filter
The SSI32 F800 1 provides a reference voltage VPTAT
lor the DAC references. Because the internal filter
control circuitry is referenced to VPTAT, the control
currentforfilter cutoff frequency and control voltage for
high frequency boost should be referenced to VPTAT.
tradeoff. One application is constant density recording
for high capacity storage products. As the data rate
increases from the inner tracks to the outer tracks, the
filter cutoff frequency can be scaled accordingly to
maximize the signal-to-noise performance. The high
frequency boost function provides pulse slimming for
accurate pulse detection.
The SSI32F8001 can be switched into a sleep mode,
dissipating less than 2.5 mW, by a TTL input at PWRON.
Two package options are available forthe SSI32F800 1:
16-lead SOL and 16-lead SON. The small feature size
of the 16-lead SON package offers significant board
space saving.
2.0 APPLICATIONS
A programmable filter is a versatile component in any
signal processing system. Some areas of applications
include fixed response filtering, variable data rate processing and adaptive equalization.
A programmable filter offers a revolutionary approach
to adaptive equalization. In signal transmission applications, an equalization filter is used to combat channel
distortion. The magnitude of channel distortion is often
not known a priori. Adaptive equalization can dynamically shape the equalization function. With an appropriate external adaptive sensing function, the cutoff frequency and the high frequency boost olthe SSI32F8001
can be dynamically programmed through microprocessor control.
3.0 FIXED RESPONSE DESIGN
PROCEDURE
For fixed response filtering applications, the SSI
32F8001 offers a simple-to-use solution. The once
complex design of cutoff frequency or magnitude equalization is now rendered to simple resistance calculation. The narrow 16-pin small outline package offers
significant board space economy.
This section suggests some design guidelines to apply
the SSI 32F8001 as a fixed response filter. Figure 3
shows the design schematic. Rx determines the filter's
cutoff frequency, defined as the -3 dB frequency with
no boost. The ratio of RB1 and RB2 determines the
amount of high frequency boost.
In variable data rate processing, a programmable filter
can be used to optimize bandwidth and signal-to-noise
Vee
~C1 1
1 ·
C2
0.01~~ .I..?1~F
-=-
-=-
VO_NORMVO_NORM+
H
H
1
NlC
VO_DIFF+
C3
C4
2 VO_NORM.
VO_DIFF·
3 VO_NORM+
PWRON
+5V~
VCC1
VPAT
16
C7
15
14
5 VIN·
N/C ~
VIN+~
6 VIN.
IFP
FBST .'-
~
10
VBP
VFP
FBST
GND 9
32F8001
VO_DIFF+
• PWRON
13
VIN-~
~
~
~
C 8 H• VO_DIFF·
r
Rx
;-
RB2
~
-4=--
FIGURE 3: The 32F8001 Setup as a Fixed Response Filter
13-3
II
SSI32F8001
Programmable Electronic Filter
3.0 FIXED RESPONSE DESIGN
PROCEDURE (continued)
4.0 PROGRAMMABLE RESPONSE
DESIGN PROCEDURE
Given fc, cutoff frequency in MHz, and FB,· high
This section suggests some design guidelines to apply
the SSI 32F8001 as a programmable filter. The high
frequency boost can be controlled by a voltage DAC
driving the VBP pin. The VBP voltage should be between 0 and VPTAT. The cutoff frequency can be
controlled by a current DAC. The application setup for
using a current source DAC is different from the one
using a current sink DAC. Both are presented below.
frequency boost in dB:
• Rx can be calculated, as given in Section 1.
Rx (kil) = 27/ fC (MHz)
VoHage across Rx is 0.33 VPTAT. The current
through Rx is 0.33 (VPTAT / Rx).
Rx should be between 1 kQ to 3 kil, i.e., fC
between 9 MHz to 27 MHz.
4.1
• RB1/RB2 sets FB, and can be determined as
follows:
RB1 / RB2 = 3.46/ (10A( FB / 20) -1) - 1
PROGRAMMABLE FILTER USING A CURRENT SOURCE DAC
Figure 4 shows the setup schematic ofthe SSI32F8001
using an external current source DAC to control the
filter's cutoff frequency.
.
• Total current drawn out of the VPTAT pin should be
limited to 2 rnA max. Thus, RB1 and RB2 should be
designed accordingly.
• The IFP pin should be left open ...
VCC~ ~
Cl
~
..
C2
O.Ol~..l.I5'.lvF
1 NlC
VO_DIFF+
C3
VO_NORM-
~
2 VO_NORM.
C4
VO_NORM+
~
3 VO_NORM+
VO_DIFFPWRON
4 VCC
VPTAT
VIN-~
5 VIN-
NIC
VIN+~
6 VIN+
IFP
+5V
VFP
16
lS
C7H
. • VO_DIFF+
C8
~
VO_DIFF-
14
13
12
11
10
GND 9
32F6001
FIGURE 4: The SSI 32F8001 Setup Schematic Using a Current Source DAC for Cutoff
Frequency Control .
13-4
SSI32F8001
Programmable Electronic Filter
4.2
Design guidelines for the SSI 32FB001 :
PROGRAMMABLE FILTER USING CURRENT
SINKDAC
• The VFP pin should be left open.
Figure 5 shows the setup schematicofthe SSI32FB001
using an external current sink DAC to control the filter's
cutoff frequency. The high frequency boost control is
the same as in Section 4.1.
• Both the current source DAC and the voltage DAC
should reference to VPTAT for accuracy.
o
o
The reference bias current drawn from VR should
be less than 2 rnA.
Some design guidelines:
The IFP current and the filter cutoff frequency are
related as follows:
Ic (MHz) = 45
x IFP (rnA) x
• Rxshould besetto1 kQbetweenVPTATandVFP.
~
• Both the current source DAC and the voltage DAC
should reference to VPTAT for accuracy and temperature stability.
VPTAT
IFP should be between 0.2 rnA to 0.6 rnA with
VPTAT = 1.BV (at room temperature).
• The total current drawn from VPTAT should be
less than 2mA. This includes the 0.6mA through
Rx. Thus, the current sink DAC and the voltage
DAC reference should not draw more than 1.4 rnA.
• The VBP voltage and the high frequency boost are
related as follows:
FB = 20 x log (3.46 x VBP / VPTAT + 1) dB
o
NlC
VO_NORMVO_NORM+
H
H
VD_DIFF+
C3
2 VO_NORMC4
3 VO_NORM+
+5V
4 VCC1
VIN-~
VIN-
VIN+~
6 VIN+
VO_DIFF-
16
15
PWRON 14
The IFP current and the cutoff frequency are
related as follows:
fc (MHz) = 27 - 45 x IFP (rnA) x VPTAT
1.B
IFP should be between 0 rnA to 0.4 rnA.
C7
~
C8
f-----Onent.
II
SSI 32F8020A
Programmable Electronic Filter
'4br, niii t."'~ Mtl
3)
1.0 DESCRIPTION
The SSI 32F8020A is a programmable 7-pole 0.05'
equiripple low pass filter in a silicon bipolar integrated
circuit. Figures 1 and 2 show the block diagram and the
filter transfer function.
The SSI 32F8020A cutoff frequency and high frequency boost can be independently controlled by two
control signals. Two sets of filter outputs are available:
normal low pass output and differentiated low pass
output. As a 0.05' equiripple type filter, the filter outputs
exhibit constant group delay beyond its cutoff frequency. Furthermore, the delays through the normal
output and the differentiated output are well matched.
The input and outputs of the SSI ;32Fa020A are differential signals, requiring external ac coupling capacitors. The given Iransferfunction shows the relationship
between the input and the two sets of outputs. The
maximum input signal is 2.0 Vpp differential. The
differential input resistance is 4 1<0 (typ.).
1.1
CUTOFF FREQUENCY CONTROL
The cutoff frequency, defined to be the -3dB corner
frequency with no boost, is programmable from 1.5 - 8
MHz. It can be set by one of three methods:
1) A resistor is connected between Rx and Ground.
The IFO and IFI pins are shorted. This setting is
only used for a fixed response design. The design
equation for this resistor value is:
Rx (kQ)
= 10.00 I fC (MHz)
A design example is given in Section 3.
2)
A current source input can be fed into the IFI pin.
With a current source digital-to-analog converter
(DAC), such as the DACF in the SSI 32D4661
Time Base Generator, this design allows a
microcontroller to change the filter response dynamically. A resistor from Rx to Ground is needed
to establish a bias current on the IFO pin. To
achieve the highest accuracy and temperature
stability, this bias current on the IFO pin is used to
reference the current source DAC.This bias current should be set such that the maximum DAC
output current is 0.6 mA at room temperature. The
design equations for Rx and the current source
value are:
Rx (kQ) = 0.75 liFO (mA) at T = 27°C
IFI (mA) = 0.075 x fC (MHz)
A current sink input can be fed into the IFI pin. With
a current sink DAC, this design also allows a
microcontroller to change the filter response dynamically. To achieve the highest accuracy and
temperature stability, the current sink DAC should
be referenced to the proportional to absolute temperature voltage at the Rx pin, nominally at 750
mY. The DAC maximum sinking current should be
at least 0.49 mA. A resistor from Rx to Ground is
needed. The total current drawn from the Rx pin
needs to be 0.6 mA at room temperature. The IFO
and IFI pins are shorted. The design equations for
Rx and this current sink value are:
Rx (1<0) = 0.75 I ( 0.6 - IDAC Bias) (mA)
IFI (mA) = 0.60 - 0.075 x fC (MHz)
A design example is given in Section 4.
1.2
HIGH FREQUENCY BOOST CONTROL
The high frequency boost function is especially desirable for pulse slimming and magnitude equalization
applications. This function can be enabled or disabled
by a TTL logic input at the FBST pin. With FBST = TTL
logic highoropen, the amount of high frequency boost,
measured at the cutoff frequency, can be programmed
from 0 to 9 dB by a voltage input at the VBP pin.
External resistors can be used in for a fixed filter
response. For a programmable high frequency boost,
a voltage DAC, such as the DAC5 in the 5S132D4661,
can be used to control the VBP pin. This input voltage
should be made proportional to the reference voltage
at the VR pin for accuracy and temperature stability.
The design equation for this control voltage is:
VBP = VR x (10"(FB/20) -1) I 1.884
where FB is in dB.
Design example is given in Section 3.
With a finite boost. the magnitude response peaks at a
frequency slightly higher than the original cutoff frequency. The effective pass band bandwidth is also
wider.
1.3
OTHER FEATURES OF THE SSI32F8020A
The SSI 32F8020A is a 7-pole 0.05' equiripple type
filter. It features excellent constant group delay. The
group delay variation from 0.2fcto 1.75 fc is less than
± 2% of the total filter delay. Furthermore, the high
frequency boost function does not affect the group
delay variation.
A design example is given in Section 4.
13-14
SSI32F8020A
Programmable Electronic Filter
Iii Ur'ItaUi til;' ~ Mtl
In addition to the normal low pass output, the SSI
32F8020A also provides a differentiated low pass
output of the input signal. The signal delay is well
matched to the normal output.
.
complex design of cutoff frequency or magnitude equalization is now rendered to simple resistance calculations. The narrow 16-pin small outline package offers
significant board space economy.
The SSI 32F8020A provides a temperature compensated reference voltage, VR, and a proportional to
absolute temperature voltage, Rx, for the DAC references. The filter cutoff frequency should be referenced
to the current at the Rx pin. The high frequency boost
control should be referenced to the voltage at the VR
pin.
In variable data rate processing, a programmable filter
can be used to optimize bandwidth and signal-to-noise
tradeoff. One application is constant density recording
for high capacity storage products. As the data rate
increases from the inner tracks to the outer tracks, the
filter cutoff frequency can be scaled accordingly to
maximize signal-to-noise performance. The high frequency boost function provides pulse slimming for
accurate pulse detection.
The SSI32F8020A can be switched into a sleep mode,
dissipating less than 2.5 mW, by a TIL low level input
at the PWRON pin.
Two package options are available for the SSI
32F8020A: 16-pin SOL and 16-pin SON. The small
feature size of the 16-pin SON package offers significant board space saving.
2.0 APPLICATIONS
A programmable filter is a versatile component in any
signal processing system. Some areas of applications
include fixed response filtering, variable data rate processing and adaptive equalization.
A programmable filter offers a revolutionary approach
to adaptive equalization. In signal transmission applications, an equalization filter is used to combat channel
distortion. The magnitude of channel distortion is often
not known a priori. Adaptive equalization can dynamically shape the equalization function. With an appropriate external adaptive sensing function, the cutoff frequency and the high frequency boost of the SSI
32F8020A can be dynamically programmed through
microprocessor control.
For fixed response filtering applications, the SSI
32F8020A offers a simple-to-use solution. The once
VOO~C1 1
1 C2•
0.01~~ lO.l~F
N/C
VO_NORM-
H
VO_DIFF+
C3
2 VO_NORM-
VO_DIFF-
3 VO_NORM+
PWRON
C4
VO_NORM+
~
4 VCC
VR
VIN- •
5 VIN-
AX
VIN+~
6 VIN+
FBST.
a
+5V
~
16
15
M
VO_DIFF+
c a H•
VO_DIFF-
C7
14
13
12
IFO 11
IFI 10
7 VBP
FBST
GND 9
32F8020A
FIGURE 3: The 32F8020A Setup as a Fixed Response Filter
13-15
I
SSI32F8020A
Programmable Electronic Filter
4.0 PROGRAMMABLE RESPONSE
3.0 FIXED RESPONSE DESIGN
DESIGN PROCEDURE
PROCEDURE
This section suggests some design guidelines to apply
the SSI 32F8020A as a programmable filter. The high
frequency boost can be controlled by a voltage DAC
driving the VBP pin. The VBP voltage should be be·
tween 0 and VR. The cutoff frequency can be controlled by a current DAC. The application setup for
using a current source DAC is different from the one
using a current sink DAC. Both are presented below.
This section suggests some design guidelines to apply
the SSI 32F8020A as a fixed response filter. Figure 3
shows the design schematic. Rx determines the filter's
cutoff frequency, defined as the ·3 dB frequency with
no boost. The ratio of RB1 and RB2 determines the
amount of high frequency boost
Given fc, cutoff frequency in MHz,. and FB, high
frequency boost indB:
Rx (kQ)
PROGRAMMABLE FILTER USING A
CURRENT SOURCE DAC
4.1
• Rx can be calculated, as given in Section 1.
= 10.00 / fc (MHz)
Voltage across Rx is 0.75V, and is proportional to
the absolute temperature.
Figure 4 shows the setup schematicofthe SSI32F8020
using an external current source DAC to control the
filter's cutoff frequency.
Rx should be between 1.25 kQ to 6.67 kQ, i.e., fc
between 1.5 MHz to 8 MHz.
Some design guidelines:
• The current source DAC Should be referenced to
the IFO current. The voltage DAC should reference to VR.
• RB1/RB2 sets FB, and can be determined as
follows:
RB1 / RB2 = 1.884/ (10"( FB / 20) -1) - 1
• The reference bias current drawn from VR should
be less than 2 rnA.
• Total current drawn out of the VR pin should be
limited to 2 rnA max. Thus, RB1 and RB2 should be
designed accordingly.
• The IFO current biases the current source DAC for
0.6 rnA maximum output at room temperature.
• The IFO and IFI pins are shorted together.
Va:~11 ~
J.
C1
0.01,i
C2
-J.?l J1f
NIC
C3
VO_NORM-H
C4
VO_NORM+ ~
-=-
2 VO_NORM3 VO_NORM+
+5V
4
VO_OIFF+
15
VO_OIFF- I - - - _C-j8
VIN-
RX
VIN+~
6 VIN+
FBST.
B FBST
VBP
VO_OIFF+
VO_OIFF·
14
VR
5
H
PWRON 1 - - - - - j H PWRON
vee
VIN-~
16
1-'-=-----.:C7:..:..jH
13
12
Rx
IFO 11
IFI 10
GNO 9
CURRENT SOURCE
CAC
32FB020A
FIGURE 4: The SSI 32F8020A Setup Schematic Using a Current Source DAC for Cutoff
Frequency Control
13-16
SSI 32F8020A
Programmable Electronic Filter
*4 U~" (iii [.'1' ~ Mt,
4.1
Some design guidelines:
PROGRAMMABLE FILTER USING A
CURRENT SOURCE DAC (continued)
• The Ax resistor determines the IFO current.
Ax (kO) = 0.75 / IDAC Bias (rnA)
• The IFI current and the filter cutoff frequency are
related as follows:
• The current sink DAC should reference to the
voltage at the Ax pin.
The voltage DAC should reference to VA.
IFI should be between 0.11 rnA to 0.6 mA at room
temperature.
• The IFO and IFI pins are shorted.
• The total current drawn from VA should be less
than 2 rnA.
The total current drawn from the Ax pin should be
0.6mA.
• The VBP voltage and the high frequency boost are
related as follows:
FB = 20 x log (1.884 x VBP / VA + 1) dB
Ax (kO) = 0.75/ ( 0.6 - IDAC Bias) (rnA)
• The IFI current and the cutoff frequency are related
as follows:
Ic (MHz) = 13.33 x IFI (mA)
4.2
Ic (MHz) = 8 - 13.33 x IFI (rnA)
PROGRAMMABLE FILTER USING
CURRENT SINK DAC
IFI should be between 0 rnA to 0.49 rnA.
Figure 5 shows the setup schematicofthe SSI32F8020
using an external current sink DAC to control the filter·s
cutoff frequency. The high frequency boost control is
the same as in Section 4.1.
Vex
-> 1 1
C1
~
C2
o.ol~l ~.lI'F
FIGURE 5: The SSI 32F8020A Setup Schematic Using a Current Sink DAC for Cutoff
Frequency Control
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1992 Silicon Systems, Inc.
13-17
1193 -
rev.
Notes:
13-18
SSI32F8030
Programmable Electronic Filter
November 1993
INTRODUCTION
The objectives of this application note are:
Analog filtering is a universal requirement in any signal
processing system. Filter design is now made easy
with the programmable filters from Silicon Systems
Inc. Whether the requirement is a fixed filtering characteristic or a programmable response, this family of
programmable filters offers distinct advantages of design simplicity, accuracy, versatility and board space
savings. Additional features, such as high frequency
boost, differentiated outputs, are also available. This
application note focuses on the SSI 32F8030, cutoff
frequency programmable from 250 kHz - 2.5 MHz.
• To present a description of the SSI 32F8030
• To discuss its applications
• To present a typical fixed response design
• To present a programmable response application
VO_NORM+
VO_NORM-
VIN+
VIN-
VO_DIFF+
VO_DIFF-
VBP
VR
IFP
VFP
PWRON
FBST
FIGURE 1: Block Diagram
INPUT
+1.31703
s + 1.68495 + 1.31703
-KS'
s + 1.68495 + 1.31703
2.95139
S'+ 1.54203+2.95139
5.37034
S '+ 1.14558 + 5.37034
Transler Function normalized lor co = 2 " Ic = 1
AN and AD are adjusted lor unity gain (0 dB) at 1= 0.67
Frequency scaling s = s 12 " Ic
Ic
FIGURE 2: The 551 32F8030 Transfer Function
1193 - rev.
13-19
CAUTION: Use handling procedures necessary
for a static sensitive co~nent.
I
SSI32F8030
Programmable Electronic Filter
A design example is given in Section 4.
1.0 DE$CRIPTION
The 881 32FS030 is a programmable 7-pole 0.050
Equiripple low pass filter in a silicon bipolar integrated
circuit. Figures 1 and 2 show the block diagram and the
filter transfer function.
• A current sink input can be fed into thelFP pin. A
9170 resistor should be placed across the VR
and the VFP pins. With a current sink DAC, this
design also allows a microcontrollerto change the
filter response dynamically. To achieve the highest accuracy and temperature stability, the current sink DAC should be referenced to the temperature compensated reference voHage at the
VR pin. The design equation for this current sink
value is:
.
The 8S1 32FS030 cutoff frequency and high frequency
boost can be independently controlled by two control
signals. Two sets offilteroutputs are available: normal
low pass output and differentiated low pass output. As
a 0.05 0 Equiripple type fiHer, the filter outputs exhibit
constant group delay beyond the pass band. Furthermore, the delays through the normal output and the
differentiated output are well matched.
The input and outputs of the SSJ 32F8030 are differential
signals, requiring external AC coupling capacitors. The
given transfer function shows the relationship between
the input and the two sets of outputs. The maximum
input signal is at least 1.0 Vpp differential, with differential input resistance 4 k.Q typical.
1.1
CUTOFF FREQUENCY PROGRAMMING
The cutoff frequency, defined to be the -3 dB corner
frequency with no boost, can be programmed between
250 kHz - 2.5 MHz. It can be set by one of three methOds:
• A resistorcan be inserted between the VR and the
VFP pins. This setting is only used for a fixed
response design. The IFP pin should be left open.
The design equation for this resistor value is:
Rx (kO) = 2.2921 fc (MHz)
A design example is given in Section 4.
1.2
HIGH FREQUENCY BOOST CONTROL
The high frequency boost function is especially desirable for pulse slimming. and magnitude equalization
applications. This function can be enabled or disabled
by a TIL logic input at the FBST pin. With FBST = TIL
logic high or open, the amount of high frequency boost
measured at the cutoff frequency can be programmed
from 0 to 9 dB by a voHage input at the VBP pin. Extemal
resistors oan be designed in for a fixed fiHer response.
For a programmable high frequenoy boost, a voltage
DAC,such as the DACS in the SSI32D4661 Time Base
Generator, oan be used to control the VBP pin. This
input voHage should be made proportional to the referenoevoHage althe VR pin for accuracy and temperature
stability.The design equation for this control voltage is:
VBP= VR x(101l(FB/20) -1)1 1.8S4 where FB is indB.
A design example is given in Section 4.
Design example is given in Section 3.
• A current source input can be fed into the IFP pin.
The VFP pin should be left open. A current source
digital-to-analog converter (DAC), such as the
DACF in the 8S132D4661 Time Base Generator,
allows a microcontroller to change the filter response dynamically. To achieve the highest accuracy and temperature stability, the current
source DAC should be referenced to the temperature compensated reference voltage at the VR
pin. The design equation for this current source
value is:
IFP (mA) = 0.3~0 x fc (MHz)
IFP (mA) = 0.320 x (2.5 - fc) (MHz)
With a finite boost, the magnitude response peaks at a
frequenoy slightly higher than the original outoff frequency. The effective passband bandwidth is wider.
1.3 OTHER FEATURES OF THE SS132F8030
The SSI 32FS030 is a 7-pole 0.05 0 Equiripple filter. It
features exoellent constant group delay. The group
delay variation from 0.2 fo to 1.75 fC is less than 3% of
mean group delay. Furthermore, the high frequency
boost function does not affect the group delay variation.
In addition to the normal low pass output, the 881
32FS030 also provides a differentiated low pass output
of the input signal. The signal delay is well matched to
the normal output.
13-20
SSI32F8030
Programmable Electronic Filter
The SSI 32F8030 provides a temperature compensated reference voltage, VR, for the DAC references.
Because the internal filter control circuitry is referenced
to VR, the control current for filter cutoff frequency and
control voltage for high frequency boost should be
referenced to VR.
tradeoff. One application is constant density recording
for high capacity storage products. As the data rate
increases from the inner tracks to the outer tracks, the
filter cutoff frequency can be scaled accordingly to
maximize the signal-to-noise performance. The high
frequency boost function provides pulse slimming for
accurate pulse detection.
The SSI 32F8030 can be switched into a sleep mode,
dissipating < 5 mW, by a TTL input at PWRON.
Programmable filter offers a revolutionary approach to
adaptive equalization. In signal transmission applications, an equalization filter is used to combat channel
distortion. The magnitude of channel distortion is often
not known a priori. Adaptive equalization can dynamically shape the equalization function. With an appropriate external adaptive sensing function, the cutoff frequency and the high frequency boost ofthe SSI32F8030
can be dynamically programmed through a microprocessor control.
Two package options are availableforthe SS132F8030:
16-pin SOL and 16-pin SON. The small feature size of
the 16-pin SON package offers significant board space
saving.
2.0 APPLICATIONS
A programmable filter is a versatile component in any
signal processing system. Some areas of applications
include fixed response filtering, variable data rate processing and adaptive equalization.
3.0 FIXED RESPONSE DESIGN
PROCEDURE
For fixed response filtering applications, the SSI
32F8030 .offers a simple-to-use solution. The once
complex deSign of cutofffrequency or magnitude equalization is now rendered to simple resistance calculation. The narrow 16-pin small outline package offers
significant board space economy.
This section suggests some design guidelines to apply
the SSI 32F8030 as a fixed response filter. Figure 3
shows the design schematic. Rx determines the filter's
cutoff frequency, defined as the -3 dB frequency with
no boost. The ratio of RB1 and RB2 determines the
amount of high frequency boost.
In variable data rate processing, a programmable filter
can be used to optimize bandwidth and signal-Io-noise
~
C3
~ 2
GND'
VO_DIFF+ r-'_6_ _C_7
VO_NORM-
VO_DIFF.'5
VO_NORM-
~
VO_NORM+
~
VIN-
~
5 VIN-
VIN+
.~
6 VIN+
3 VO_NORM+
+5V>----=-
vcc,
VA
FaST
.">---' ~
VO_DIFF·
•
~
+5V
Ax
fa, ~
VFP f-"O_ _ _- - '
GND2 9
FaST
?WRON
f-"~3----1>--""
IFP~
,---!.. vap
VO_DIFF+
'4
?WRON
VCC2
CB
H
H
'-----3=2==F80""30""
~
t-
Ra2~
<;
-
FIGURE 3: The 32F8030 Setup as a Fixed Response Filter
13-21
I
SSI32F8030
Programmable Electronic Filter
3.0 FIXED RESPONSE DESIGN
PROCEDURE (continued)
4.0 PROGRAMMABLE RESPONSE
DESIGN PROCEDURE
Given fe, cutoff frequency in MHz, and FB, high
frequency boost in dB:
This section suggests some design guidelines to apply
the SSI 32F8030 as a programmable finer. The high
frequency boost can be controlled by a voltage DAC
driving the VBP pin. The VBP voltage should be between 0 and VR. The cutoff frequency can be controlled by a current DAC. The application setup for
using a current source DAC is different from the one
using a current sink DAC. Both are presented below.
• Rx can be calculated, as given in Section 1.
Rx (kn) = 2.292/ fc (MHz)
Voltage across Rx is 0.33 VR. The current through
Rx is 0.33 (VR / Rx).
Rxshould be between 917n to 9.17 kn, i.e., fc
between 250 kHz to 2.5 MHz.
4.1
• RB11RB2 sets FB, and can be determined as
follows:
RB1 / RB2 = 1.884/ (1 Oll( FB / 20 ) - 1) - 1
PROGRAMMABLE FILTER USING A CURRENT SOURCE DAC
Figure 4 shows the setup schematicofthe SSI32F8030
using an external current source DAC to control the
filter's cutoff frequency.
• Total current drawn out of the VR pin should be
limited to 2 rnA max. Thus, RB1 and RB2 should be
designed accordingly.
• The IFP pin should be left open.
Va;
~
C1
1 1
~
C2
0.01J1~ ~.lJ1F
GND1
-
C3
VO_NORM-
~
2
VO_NORM-
VO_DIFF+
VO_DIFF-
C4
VO_NORM+
~
3 VO_NORM+
+5V
4 VCC1
VIN-~
5
VIN+~
6 VIN+
VIN-
7 VBP
FBST.
8 FBST
PWRON
VR
16
C 7 H• VO_DIFF+
15
C 8 H• VO_DIFF-
14
13
VCC2
VFP
10
GND2 9
32F8030
-
FIGURE 4: The SSI 32F8030 Setup Schematic Using a Current Source DAC for Cutoff
Frequency Control
13-22
SSI32F8030
Programmable Electronic Filter
4.2
Design guidelines for the SSI 32FS030:
o
o
o
The VFP pin should be left open.
Both the current source DAC and the voltage DAC
should reference to VR for accuracy and temperature stability.
Figure 5 shows the setup schematic ofthe SSI32FS030
using an external current sink DAC to control the filter's
cutoff frequency. The high frequency boost control is
the same as in Section 4.1 .
The reference bias current drawn from VR should
be less than 2 rnA.
Some design guidelines:
o
o
o
PROGRAMMABLE FILTER USING CURRENT
SINK DAC
The IFP current and the filter cutoff frequency are
related as follows:
Rx should be set to 917Q between VR and VFP.
Jc (MHz) = 3.125 x IFP (rnA)
• Both the current source DAC and the voltage DAC
should reference to VR for accuracy and temperatu re stability.
IFP should be between O.OS rnA to O.S rnA.
o
The VBP voltage and the high frequency boost are
related as follows:
FB = 20 x log (1.SS4 x VBP I VR + 1) dB
o
The total current drawn from VR should be less
than 2 rnA. This includes the O.S rnA through Rx.
Thus, the current sink DAC and the voltage DAC
reference should not draw more than 1.2 rnA.
The IFP current and the cutoff frequency are
related as follows:
Jc (MHz) = 2.5 - 3.125 x IFP (rnA)
IFP should be between 0 rnA to 0.72 rnA.
VCC~C1 1
0.01f1~
1 •
C2
.I..o.1f1F
GND1
VO_NORMVO_NORM+
H
H
C3
-=-
C4
t5V
~
VIN- •
VINt.~
FBST •
VO_NORMt
3 VO_NORM.
>----'
VCC1
VIN-
VO_DIFFt
VO_DIFF·
PWRON
VR
VCC2
6 VINt
IFP
7 VBP
VFP
FBST
16
15
C7
~
VO_DIFF+
C B H• VO_DIFF-
14
• PWRON
13
12
t5V
11
10
GND2
32FB030
FIGURE 5: The SSI 32F8030 Setup Schematic Using a Current Sink DAC for Cutoff Frequency Control
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1991 Silicon Systems, Inc.
13-23
1193 - rev.
Patents Pending 497,863/500,778/710,512
Notes:
13-24
SSI32P3000
Evaluation Board
'*i U~" iii[.u, ~ stj
November 1993
INTRODUCTION
The SSI 32P3000 is a high performance pulse detector
for 48 Mbitls storage system applications. It provides
the complete solution for detection and qualification of
encoded read signals. The AGe function, noise limiting
filtering, pulse slimming,level and time qualifications are
all integrated into one Chip. Additional features include
input impedance control, fast AGe recovery from writeto-read transition, and independent positive and negative threshold qualifications.
The objectives of this application note are to:
• Present a brief description of the SSI 32P3000
• Present a description of the evaluation board of
the SSI 32P3000
• Explain in detail key features of the SSI32P3000
While the evaluation board design does not suggest
optimized component values, which vary with system
requirements, it presents a means to evaluate the
performance ofthe SS132P3000. Test setups in evaluation of pulse pairing, exercise of fast recovery function
and others are suggested in this application note.
1_0 DESCRIPTION OF THESSI32P3000
The AGe amplifier compensates for variations in head
preamp output levels, and presents a constant input
level to the pulse qualification circuitry. The AGe action
can be suspended to hold at a constant gain in embedded servo decode or other processing needs.
A programmable 7-pole Bessel low pass filter is included. Two sets of filter outputs are available: normal
low pass output and differentiated low pass output. The
signal delays of the two outputs are well matched, ideal
in pulse qualification. The filter cutoff frequency can be
(continued)
r--{>---
6
FAST
REG
(AGC) (llCIm) SERVO
AGND
OGND
VGA
t---Nv-~~VTHYYR
J
Figure 1: The SSI 32P3000 Block Diagram
1193-rev
VGD
+5V
I
SSI32P3000
Evaluation Board
1.0
DESCRIPTION OF THE SSI 32P3000
(continued)
programmed from 9 to 27 MHz, via a current input. Up
to 13 dB high frequency boost (for pulse slimming) can
also be independently programmed. The SSI32P3000
is ideal for constant density recording.
Both level qualification and time qualification are used in
the SSI32P3000 pulse qualification. For level qualification, the filter output peak can be fed forward to establish
the comparator hysteresis threshold. This allows the
threshold to track the comparator input amplitude, and
to qualify data while AGC amplifier settling is still in
transition. The 32P3000 employs a dual-comparator
qualification scheme, which allows independent positive and negative threshold detection. This has the
advantage of reducing error propagation. Fortime qualification, the differentiated filter output translates each
input peak into a zero crossing, and is used in clocking
the comparator outputs.
The filter inputs and outputs are not brought out to pin
terminals, but accessible at the pads of their respective
coupling capacitors.
3.0 EQUIPMENT AND SOFTWARE
REQUIREMENTS
To facilitate the following demonstrations of the SSI
32P3000 with the Silicon Systems 48 MB Demo Board,
the following equipment and software are needed:
IBM PC with parallel port
Silicon Systems proprietary software 4 bit.exe
Silicon Systems parallel port cable
+5V power supply to Silicon Systems 48 MB
Demo Board
TTL pattern generator
Signal generator, with amplitude modulation
input
Oscilloscope
Spectrum analyzer, with a tracking output, for
filter characteristics measurements
Time interval analyzer. for pulse pairing measurement
For each peak ofthe VIA+/-, there is a one-shot pulse at
the differential AD output. The pulse width of the oneshot pulse is determined by a user selected resistor at
theOSTpin.
The SSI32P3000 is available in a 36-pin SOM package.
4.0 DEMONSTRATIONS
2.0 DESCRIPTION OF THE EVALUATION
BOARD
The SSI 32P3000 can be evaluated with the 48 MbiVs
Demo Board from Silicon Systems. This board is designed with the Silicon Systems 48 MbiVs chip set:
32P3000 (36-pin SOM) as the pulse detector, 32D4661
(24-pin DIP) as the time base generator; and 32D539
(44-pin PLCC) as the data synchronizer with 1,7 ALL
ENDEC. The SSI 32D4661 provides two digital-toanalog converters (DAC) to program the filter cutoff
frequency and the high frequency boost function of the
SSI32P3000 filter. In evaluating the SSI32P3000, the
SSI 32D539 is not needed.
This evaluation board requires the Silicon Systems
Parallel Port Cable to interface between a PC parallel
port and the SSI 32P4661. This reduces the filter
programming to simple inputs through an IBM PC.
Details in programming steps are discussed in a later
section.
The analog inputs, VIA+/-, mode control inputs, LOWZ,
HOLD- and FAST AEC, and read data outputs, AD+/- of
the SSI32P3000 are accessible through pin terminals.
Four demonstration setups are presented in this section
for:
general functionality
pulse pairing
filler characteristic
fast recovery exercise
4.1
SOFTWARE SETUP & COMMANDS
To facilitate filter cutoff frequency and high frequency
boost control, a parallel port and Silicon Systems software are used to command the two 7-bit DACs in the SSI
32D4661.
Type 4 bit v 25 to access the Silicon Systems proprietary
software program for controlling the DACs.
In evaluating the SSI 32P3000, only two functions are
controlled from the keyboard: the filter cutoff frequency
andlhe high frequency boost. Because each DAC inthe
SSI 32D4661 is a 7-bit DAC and the Silicon Systems
Serial Comm Board data is 4-bit wide, two registers are
needed for each function control. Aegisters (address) 8
and 9 are for high frequency boost control; Aegisters 10
13-26
SSI32P3000
Evaluation Board
If' ij~" liit.", ~ Mil
100 I div
mean = R 261 PS
sigma = 03.61
rei = 28.090 nsl
I
X:ROOO PS
Y:486
Figure 5: Histogram of RD Periods with 18 MHz Sinusoidal Input
No Bimodal Distribution => Pulse Pairing less than 500 ps
4.3
PULSE PAIRING MEASUREMENT
(continued)
The test procedure is as follows:
Feed a low jitter sinusoidal input
Measurethe time distance between RD pulses,
corresponding to one positive peak detection
and one negative peak detection
Histogram plot measurements
Significant pulse pairing will appear as a bimodal distribution of time period measurements
4.4 FILTER CHARACTERISTIC
The 551 32P3000 is ideal for constant density recording
application with its programmable filter. The filter is a 7pole Bessel low pass filter with normal output, as well as
differentiated output. The normal output is for level
qualification; the differentiated output is for time qualification. Their signal delays are well matched. The group
delay is maintained within ±300 ps from 0.3 Ic to Ic. The
filter cutoff frequency can be programmed from 9 MHz
to 27 MHz through a current input atthe IFI pin. The high
frequency boost can be programmed from 0 to 13 dB
through a voltage input at the VBP pin.
Ic = 45xIFIMHz; .IFlinmA(atroomtemp.)
Boost = 20 x log [ Kb (VBP I VRG) + 1 ] dB;
VRG is reference voltage at Pin 1.
Kb = 3.041 + 0.0276 x fCi, where fci is the
ideal cutoff frequency.
Pulse pairing can becalrulated as half of the
time distance between two peaks in the histogram plot
Figure 4 shows a setup for the pulse pairing measurement. The 551 32P3000 has demonstrated less than
500 ps pulse pairing, as shown in Figure 5.
Figure 6 shows a test setup to evaluate the frequency
response of the 551 32P3000 filter. The 551 32D4661
provides two 7-bit DACs for ease of programming.
13-29
I
SSI32P3000
Evaluation Board
IMpr,ltWin'u'lMI
• IBM PC wi Parallel port
·4B~
• Silicon Systems Parallel port cable
.sV
GNO
L _ _ _J - - - - - - = - - j FASTREC
--~~-.....jVIA+
I SSI 320539 I
'------" VIA-
Silicon Systems 48MB
Evaluation BoaR!
Figure 6: SS132P3000 Evaluation Board FiUer Characteristic Setup
The full scale DAC valu~, i.e., Code 127, corresponds to
maXimum cutoff frequency, 27 MHz, or maximum boost,
13 dB. In decimal code, the cutoff frequency and high
frequency boost can be calculated as follows:
For example, the user wants to program the filter to
14 MHz cutoff with 3 dB boost. TheDAC codes are
calculated as the following:
Ic = 27 MHz x ( DACF Code) 1127;
42 ~ DACF Code ~ 121
DACS Code = 127 x [.101\( 3/20) -1] 13.467 = 15,
DACF Code = 127x 14/27 = 66, Rl0=4 Rll =2;
Boost= 20 x log [Kb x ( DACS Code) 1127 + 1] dB;
o~ DACS Code ~ 127
Because the Silicon Systems Serial Communication
Board works with 4-bit nibbles, each 7-bit code is
divided into two registers. For cutoff frequency control,
Rl0 .and R11 represents the 3 most significant bits
(MSB) and the 4 least significant bits (lSB), respectively. Only the lower 3 bits of Rl0 4-bit nibble is used.
For high frequency boost control, R8.and R9 represents
the 3 MSBs and the 4 lSBs, respectively.
R8=0 R9=15.
At the keyboard, the user enterS R8=OR9=15 Rl0=4
Rll=2, followed by Alt. T.
To evaluate the frequency response of the filter, the
AGC amplifier gain must be held constant, HOlD=O.
The tracking output of the spectrum analyzer sweeps
the signal over a frequency spectrum. The filter output
can be examined at the pad of C5 on the board. Figure
7 shows the filter responses at 9 MHz and at 27 MHz.
Figure 8 shows the filter response with no boost and that
with maximum boost.
13-30
SSI32P3000
Evaluation Board
and 11 are for filter cutoff frequency control. Other
registers are used to control the SSI32D539 functions
which are not covered in this application note.
Upon power up of the evaluation board, these registers
must be initialized by the user. Press Alt 8 (selects
register 8), Ait 9 (selects register 9), Ait A (selects
register 10) and Ait B (selects register 11). Using the
cursor keys, position the cu rsor to the appropriate value
column. Press the enter key and then backspace to
erase its contents. Key in the new value and press enter
again. Pressing AIt Ttransmits all selected registers. For
now, type R8=OR9=OR10=7R11=15, followed by AltT.
Details are given in Section 5.4 filter characteristics
discussion. The above command sets the filter at 27
MHz cutoff frequency with no boost.
4.2
GENERAL FUNCTIONALITY
REC=O. With an 18 MHz, 200 mVpp sinusoidal input,
the RD/RD shows a pulse corresponding to each positive peak and each negative peak, as Shown in Figure 3.
The pulse width has been preset to be - 10 ns, with RT
= 3 kQ. The user may change the pulse width by
replacing RT.
RT = 1960 + Pulse Width / [ 0.157 ( 22 pF + Cstray ) 1
RT should be between 2 kQ to 8 kQ.
4.3 PULSE PAIRING MEASUREMENT
The SSI32P3000 has demonstrated excellent pulse
pairing performance, less than 500 ps. Pulse pairing is
one of the most critical parameters of any pulse detector. It is defined to be the systematic time error from
ideal, caused by comparator threshold offset, in pulse
detection of an input signal peak.
Figure 2 shows a general setup to evaluate the SSI
32P3000. In normal read operation, the following conditions should be set: LOWZ=O, HOLD=1 and FAST
• IBM PC wi parallel pan
·4 BIt
• Silicon Systems parallel pan cable
r-~==--I---------~~~m
f--------'-'---I
~
L ______J---------.!:.....--j FAST REC
I
SSI 320539
I
Silicon Syslems 48MB Evaluadon Board
Figure 2: SSI 32P3000 Evaluation Boal1f General Setup
13-27
I
SSI32P3000
Evaluation Board
Oscilloscope E
Autoscale
)
( cancel)
(
Stop
~~
C2
X-17.SmV
0-14.4 mV
C1
X3.80V
03.81 V
Figure 3: Normal Read Function: 18 MHz Sinusoidal Input (top) and RD Pulses (bottom)
• IBM PC wI RS232 on COM1
·4B1T
• Silicon Systems parallel port cable
i-==-l-----,,--..j VIA.
- - ' ' - - - ' VIA·
Osdloscope
A bimodal distribution
is a measure of pulse pairing.
PP - 0.5 I( Distance between two peaks
X .. Time Interval
Y .. Occurrence
Figure 4: SSI 32P3000 Evaluation Board Pulse Pairing Setup
13-28
SSI32P3000
Evaluation Board
REF -29.3 dBm
1 dB/DIV
.......
,
MARKER 27 790 600.0 Hz
-35.20 dBm
RANGE .0 dBm
- .............. """-
'\
..............
..
.......
"\ \
.......
,
..........
'"
~
',,-
'\.
\
START 100 000.0 Hz
STOP 40 000 000.0 Hz
RBW 30 kHz
VBW 30 kHz
ST.2 SEC
Figure 7: SSI 32P3000 Filter Magnitude Responses at 9 MHz (left) and 27 MHz (right) Cutoff
OFFSET.O Hz
RANGE.O dBm
REF -1S.0 dBm
SdB/DIV
,.,.
--... i"-o..
~
~
:,...-"""
~
-
13.40 dB
r-...
..........
~
'" I"'-.....
START 100000.0 Hz
RBW 30 kHz
Figure 8:
.............
STOP 40 000 000.0 Hz
VBW 30 kHz
ST.2 SEC
Cutoff Frequency = 14 MHz. The SS132P3000 Filter Response with no boost
(bottom) and with maximum boost (top)
13-31
I
SSI32P3000
Evaluation Board
• User Control
Fast Recovery: To recover the AGC amplifier gain
from a low gain condition rapidly, the FAST REC
can be .asserted. With FAST REC = 1, a fast decay
current, 0.16 x IFI, charges CBYP continuously,
indepehdent of signal level. While the ~~st a~d
Slow Attacks are still active, the AGC amphflergam
settles quickly to -125% of nominal. When the
FAST REC returns to 0, the Fast Attack and Slow
Attack actions restore the AGC amplifier gain to
100% level.
4.5 AGC ACTIONS & RECOVERY
The SSI 32P3000 has the following AGC control features:
• Automatic
Fast Attack: When the DIN+/- input .exceeds the·
preset nominal level (1 Vpp) by 25%, a fast attack
current, 2.24 x IFI, quickly discharges CBYP and
lowers the AGC amplifier gain.
Slow Attack: When DIN+/- input exceeds the preset
nominal level by less than 25%, a slow attack
current, 0.32 x IFI, discharges CBYP and lowers the
AGC amplifier gain until DIN+/- returns to nominal
level.
Slow Decay: When the DIN+/- input falls below the
preset nominal level, a small decay current, O.OO~
x IFI, charges CBYP and increases the AGC amplIfier gain until DIN+/- returns to nominal. Because
Fast Attack and Slow Attack currents are much
larger than that of Slow Decay, it is obvious that
AGC amplifier gain can be lowered quickly, but can
only be increased very slowly. The purpose of the
large ratio between attack/decay current is to ensure that the AGC settles to the peak-to-peak
voltage amplitude.
Hold: When HOLD = 0, all the above AGC actions
are suspended. TheAGC amplifier gain is held
constant, except for leakage effects.
The setup in Figure 9 is used to demonstrate the
advantage of the FASTRECfunction. Figures 10 & 11
show the AGC amplifier gain recovery time without and
with the FAST RECfunction, respectively. Withoutthe
FAST REC function, the AGC amplifier gain slowly
recovers to the 100% nominal level, due to the small
decay current. With the FAST REC function, the AGC
amplifier gain qu ickly reaches 125%+. When the FAST
REC returns to 0, the attack time is very short. One
application of the FAST RECJunction is.immediately
after a long holdperiodduring which the gain could have
drifted low.
-18M PCW/Parallel port
Sllcon Systama
..MBEvaluafon_
Figure 9: SSI 32P3000 Evaluation Board AGC Recovery Setup
13-32
SSI32P3000
Evaluation Board
eij r' ItMii t.hi~ Mtl
Figure 10: AGC Recovery Without Using FAST REC
FAST REC = 0
HOLD
Analog Input: Amplitude Modulated to Simulate Gain Change
DIN±
Figure 11: AGC Recovery With FAST REC
FASTREC
HOLD
Analog Input
DlN±: Note fast recovery settling to above 100% and attacking
at the end of fast recovery
13-33
I
..t~<
~
>0>
lB
o
Q:!
~
3
-'"
:;!"
Q:!
~----~~_4FOEN
VCO
~
-[
;::I
'"tt.
?
§;
co
~
~
SCATA
DGNO
XLl
Xl2
'"
<0
3
~
~a
VA31IR
FCD
FLTR
FCLK
~-----------=88~1~32~~~OO~1
sell<.
~.
CorJl)Or'l&nt
~~
RX
R~~
AT
RP
RS
Cl
C2
C3
0.
C5·12
e13, C15·20
C14
CBYP
Values
~~bn
5kn
10~~ariabieResistor
T80
TBO
613 :t
VOA-
BYP
IN+
VRC
-J;
~
W
eQ)N
~ Cl~ PWRIN
T
::::-0
(oGNOIN
OW
::l0
mg
VTH
LEVELt---"-+-j
SERVO
~
oQ)
1----------"
-
"""l
Q.
~~
~~
CN
CP
+5V
:I---_______ _
~
_+_+--'
001------------_+_+--'
VCA
SS132P3000
.5V
~-C18
+SV~
j1i'
..:r:.. C19
-:
~
I
~..
81
I IIII
I;tl
~
WCLK .~-----,
SBl-
Pin 22: 3204661
1N456
~
_8
Xl
12.000 MHz Crystal
1000 pF
Oscillator
~
NRZ7
NRZ6.
NRZ5'
NRZ4
NRZ3.
NRZ2 •
NRZS
NRZ4
NRZ3
NRZ2
NRZ1.
NAZO
NRZl
NRZO
NRZP.
NRZP
PERR.
551 320539
PERR
mm o~~~
~:i
11.",,,,,O~S;!;!~N
>0
ccz 3:13=1<
GNO~+5V~+
RCLK 0)>---------'
NCLK
WOo)>---------'
0»-------
xx~::
I ~I
L--~+5V
RP
Pin 4: 3204661
.... ,,'
~~
co
'f'
T
0.1 ""
0.01 ""
10""
1000 pF
01
...
VIA·
AM!::
0.22""
0.022""
~
g
VIA.
VOA.
lka
Tao
TBO
3
en
""0
00-
3.3""
~
VRG
00.
CL
3
men
-"-----1 veA
2
"
~
JlL
RR
AGNO
OACM
~~
~
FIGURE 12: 551 32P3000 1 5513205391 5513204661 Evaluation Board 5chematlc
...""
iA4.Ur Using an SSI32P4730/31/41142/44/46
JUIam!!}.rJWflJ Single-Chip Read Channel Device
_,f,
®
A TDK Group Company
ttPP!(ltjj(·'~'t(·)jj
January 1994
Bi-directional serial port programming
INTRODUCTION
Silicon Systems is pleased to introduce the SSI
32P4730/31/41/42/44/46, the highest performance
single-chip read channel devices available. These
devices contain all the functions needed to implement
a complete zoned recording read channel for hard disk
drive systems. The functional blocks include a pulse
detector, programmable filter, 4-burst servo circuit,
time base generator, and a data separator with a 1,7
RLL ENDEC. Refer to the respective data sheets for
functional block diagrams. The operating NRZ data
rate is programmable from 8 to 27.3 Mbitls forthe SSI
32P4730/31, 16-40 Mbitls forthe SSI32P4741/44, and
16-48 Mbitls for the SSI 32P4742/46.
While the SSI32P4730/44/46 and SSI32P4731/41/42
provide a 4-burst servo capture circuitry, the distinction
is in the servo output form. The SSI 32P4730/44/46
featuresA+B, A-B and C-Doutputs. The SS132P4731/
41/42 features individual Burst A, S, C and D outputs.
This application note details the operation of all
functional blocks of the SSI 32P4730/31/41/42/44/46.
This is an abridged version of the application notes, a
more detailed note is available upon request. Design
notes and evaluation techniques are suggested when
applicable. This note is intended to supplement the
data sheet. For updated device parameter limits, the
user is recommended to refer to the electrical
specification.
Flexible power management less than 1 mW in
complete power down
Wide power supply range 4.5 to 5.5 V
Small footprint 64-pin TQFP package
PULSE DETECTOR
Fast Attack/Decay mode for rapid AGC
recovery
Dual rate charge pump for fast transient
recovery
Programmable qualification threshold
Low drift AGC hold circuitry
Temperature compensated, exponential
control AGC
Wide bandwidth, high precision full-wave
rectifier
Dual mode pulse qualification circuitry (user
selectable)
CMOS RDIO and PPOL signal output for servo
timing support
Internal Low-Z and fast decay timing for rapid
transient recovery and AGC acquisition
0.5 ns max pulse pairing
SERVO CAPTURE
4-burst servo capture
Internal hold capacitors
Separate registers for filter cutoff and
qualification threshold in Servo mode
FEATURES
Programmable data rate 8-27 Mbitls for SSI
32P4730/31, 14-40 Mbitls for SSI 32P4741/44,
and 16-48 for SSI 32P4742/46
Servo AGC level programmable via 4-bit DAC
P4730/44/46 : A+B, A-B and C-O Outputs
Low power dissipation:
- 400 mW typ @ 24 Mbitls and 5V supply
for the SSI 32P4730/31
P4731/41/42 : Burst A, B, C and D outputs
PROGRAMMABLE FILTER
Cutoff frequency programmable from 3 to 9
MHz, within ±10% accuracy (6-18 MHz for 41/
42/44)
Boost programmable from 0 to 13 dB
- 425 mW typ @ 40 Mbit/s and 5V supply
for the SSI 32P4741/44
- <500 mW typ @ 48 Mbitls and 5V supply
for the SSI 32P4742/46
NOTE: This document serves as a supplement to the data sheet for the device. The user is
recommended to refer to the data sheet electrical specifications for performance limits. The
information within this document is preliminary. Verification is in progress.
0194 - rev.
13-35
I
Using anSSI 32P4730/31/41/42144/46
Single-Chip Read Channel Device
FEATURES (continued)
Matched normal and differentiated outputs
Constant group delay, within ±~Io variation
Low Z input switch for rapid transient recovery
No extemal filter components needed
< 1"10 THO
TIME BASE GENERATOR
Better than 1% frequency resolution
Up to 75 MHz frequency output
Independent M and N divide-by counters
VCO center frequency matched to data
synchronizer VCO
DATA SEPARATOR
Fast acquisition phase lock loop with zero phase
restart technique
Programmable phase detector gain switch for fast
acquisition and low jitter.
Integrated 1,7 RLL encoder/decoder (Dual bit
interface for 4742146)
Fully integrated Data Synchronizer-no external
active devices needed
Programmable decode window symmetry control
via serial port
Programmable write precompensation with
independent early and late shift magnitudes (3-bit)
Hard and soft sector operation (soft sector not
available on the 4742146)
CONTROL REGISTER MAPPING &SERIAL
INTERFACE DESCRIPTION
For flexible system applications, the SSI32P4730/31/
41/42144/46.fe.atures 14 control registers for device
configuration. The control words can be loaded to or
read back from these registers via the 3-pin serial
interface. This section defines the register mapping
and the serial interface timing.
Upon· power up from no supply voltage state, the
control register are at random state, and should be
programmed before system operation. The control
register contents are retained when the device is
powered down to Idle mode, i.e., with PWRON = 1.
13-36
Using an SSt 32P4730/31/41/42/44/46
Single-Chip Read Channel Device
COMMAND REGISTER MAPPING
Power Down Control Register Address (A6 .. AO) = 0000010 = 02 HEX
D7 (MSB) - D5
D4
D3
D2
Internal hardwired for factory use only.
=1
=0
Time Base Generator is disabled, reducing power dissipation by 100 mW.
Time Base Generator is active. (Normal mode)
=1
Data Separator is disabled, reducing power dissipation by 120 mW.
=0
Data Separator is active. (Normal mode)
=1
Programmable Filter is disabled, reducing power dissipation by 100 mW.
Programmable Filter is active. (Normal mode)
=0
D1
DO (LSB)
=0
Timebase Generator phase detector gain = 1 X KD.
Timebase Generator phase detector gain = 3 X KO (0 - Normal mode).
=1
=0
Pulse Detector/Servo is disabled, reducing power dissipation by 75 mW.
Pulse Detector/Servo is active. (Normal mode).
=1
Data mode Cutoff Register Address (6 .. AO) = 0000011= 03 HEX
07 (MSB)
=0
06 .. DO
Set to zero
Filter cutoff frequency control in the data Read mode.
Ic (MHz) = 9' Code/127 (18' Code/127 for 41/42/44/46)
Maximum code, 1111111 or 127 decimal, represents the maximum 9 MHz
cutoff frequency (18 MHz for 41/42144146).
Minimum code is 42, for 3 MHz cutoff frequency (6 MHz for 41/42/44/46).
Servo mode Cutoff Register Address (A6 .. AO) = 0010011 = 13 HEX
D7 (MSB)
=1
=0
D6 .. DO
TTL WD buffer disabled (SSI 32P4742/46 only).
TTL WD buffer enabled (Normal mode)
Filter cutoff frequency control in the Servo mode.
Filter Boost Register Address (A6 .. AO) = 0001011
07 (MSB)
=1
=0
= OBHEX
Filter boost remains active in the Servo mode.
Filter boost is disabled in the Servo mode.
Filter boost control setting Boost (dB) = 20 log [(0.0273' Code) + 1]
Maximum boost, 13 dB, isset with Code = 127 decimal.
Minimum code, 0, represents no boost.
D6 .. DO
Data Threshold Register Address (A6 .. AO) = 0001010 = O~EX
D7 (MSB)
D6 .. DO
=1
Window Threshold Qualification in Data mode
=0
Hysteresis Threshold Qualification in Data mode
Qualification threshold percentage setting in Data mode
Qual % = 93% • Code/127
Qual % should be limited between 30% to 80%. Thus, this code should be
restricted from 41 to 109.
13-37
I
Using an SSI 32P4730/31/41/42/44/46
Single-Chip Read Channel Device
CONTROL REGISTER MAPPING & SERIAL INTERFACE DESCRIPTION (continued)
Servo Threshold Register Address (A6 .. AO) = 0010010 = 12HEX
D7 (MSB)
=1
=0
D6 .. DO
Window Threshold Qualification in Servo mode
Hysteresis Threshold Qualification in Servo mode
Qualification threshold percentage selling in Servo mode
Control A Register Address (A6 .. AO) = 0011010 = 1AHEX
D7 (MSB)
=1
=0
D6-5
Not in fast decay current Test mode (Normal mode)
Fast decay current is always turned on, for test use only other AGC actions,
such as HOLD, attack, ... remain active.
Test point source select bits, work in combination with Control B Register: D6
D4
=1
=0
Frequency synthesizer is bypassed. TBG output = FREF.
Frequency synthesizer is active. TBG output = FREF • [(M+ 1)/(N+ 1)] (Normal
mode).
D3
=1
=0
Enables test point MTP3.
Test point MTP3 forced to Logic 1 (Normal mode).
D2
=1
=0
TBG phase detector pump down state, for test use only.
Not in TBG phase detector pump down Test mode (Normal mode).
D1
=1
=0
TBG phase detector pump up state, for test use only.
Not in TBG phase detector pump up Test mode (Normal mode)
DO
=1
=0
TBG phase detector active (Normal mode)
TBG phase detector disabled, allowing pump up/down Test modes
Only one bit of {DO, D1, D2} can be set to 1 at anyone time. Violation causes indeterminate state.
Control B Register Address (A6 .. AO) = 0001100 = OC HEX
D7 (MSB)
=0
Set to zero for normal use
D6
=1
=0
Enables test points MTP1 and MTP2
Test points MTP1 and MTP2 forced to Logic 1 (Normal mode)
D5
=1
=0
Data Separator phase detector pump down state, for test use only
Not in Data Separator phase detector pump down Test mode (Normal mode)
D4
=1
=0
Data Separator phase detector pump up state, for test use only
Not in Data Separator phase detector pump up Test mode (Normal mode)
D3
=1
Data Separator phase detector active (Normal mode)
Data Separator phase detector disabled, allowing pump up/down Test modes
=0
Only one bit of {D3, D4, D5} can be sello 1 at anyone time. Violation causes indeterminate state.
13-38
Using an SSI 32P4730/31/41/42/44/46
Single-Chip Read Channel Device
Control B Register (continued)
D2
=1
=0
The RDIO pin is an input pin
The RDIO pin is an output pin (Normal mode)
D1
=1
=0
Data Separator phase detector gain shift is enabled
Data Separator phase detector gain shift is disabled (Normal mode)
DO
=1
=0
Direct write enabled, Le., write data bypasses the ENDEC
direct write disabled, Le., write data is encoded before appearing at write data
output (Normal mode)
N Counter Register Address (A6 .. AO) - 0000110 - 06-HEX
D7 (MSB)
=x
D6 .. DO
= 1 Extended 2 JlS low-Z write to read recovery
= 0 Normal 1 JlS low-Z recovery (Normal mode)
7-bit N counter code in Time Base Generator frequency synthesizer.
N Counter can be programmed anytime, but becomes effective only after a
subsequent Date Rate Register programming.
M Counter Register Address (A6 .. AO) - 0001110 - OEHEX
D7 .. DO
8-bit M counter code in Time Base Generator frequency synthesizer. Fout =
[(M + 1)/(N + 1) I . Fref, Fout = TBG output frequency Fref = Reference
frequency@ FR EF pin M Counter can be programmed anytime, but becomes
effective only after a subsequent Date Rate Register programming.
- 04H"<
Data Rate Register Address (A6 .. AO) - 0000100 D7 (MSB)
=1
=0
D6 .. DO
Test mode- resets internal flip-flops
Normal use (Normal mode)
Per data rate, code sets the VCO center biasing
SSI32P4730/31: IDAC Code = (3' DR MHz - 3.84 )/0.614
SSI32P4741/42/44/46: IDAC Code = (1.5· DR MHz - 3.84 )/0.614
For 20 Mbit/s (40 Mbitls for 41/42/44/46) operation, Code = 91, Le., 1011011
Window Shift Register Address (A6 .. AO) - 0000101 - 05H"Y
D7 .. D6
=
=
=
=
00
01
10
11
Fc DAC output, Le., filter cutoff, @ DACOUT
Vth DAC output, Le., qualification threshold, @ DACOUT
WS DAC output, Le., window shift, @ DACOUT
WP DAC output, Le., write precomp, @ DACOUT
Selection of early or late DAC is made by the WP enable bit in the Write
Precomp Req.
Note: The DACOUT pin must not be loaded. Loading affects DAC performance.
13-39
II
Using an SSI 32P4730/31/41/42/44/46
Single-Chip Read Channel Device
CONTROL REGISTER MAPPING & SERIAL INTERFACE DESCRIPTION (continued)
Window Shift Register (continued)
D5
=1
=0
Window shift function enabled
Window shift function disabled
D4
=1
=0
Window shift direction: Late
Window shift direction: Early
D3-0
4-bit code to set the window shift magnitude. Window Shift % of Data
Separator VCO Period = 30% - Code' 2%. For 20% shift, Code = 5, i.e., 0101
Write Precomp Register Address (A6 .. AO) = 0001101 = OD HEX
D7
=1
=0
D6 .. D4
D3
High Resolution Peak Detector Reset. Peak detector capacitors are reset at
the 0.5 voll baseline. (Normal mode)
Low Resolution Peak Detector Reset. Capacitors are reset below the 0.5 volt
baseline.
3-bit code to set the write precomp late magnitude.
=1
=0
D2 .. DO
= 000
= 001
= 010
= 011
= 100
= 101
= 110
= 111
Write Precomp function enabled.
Write Precomp function disabled.
3-bit code to set the write precomp early magnitude.
The need and direction of write precomp is determined by data pattern. But
precomp magnitude is programmable via this register as the following:
7xTS
TS = 0.04 'Encoded bit period
6x
5x
4x
3x
2x
1x
No Precomp
AGe Level Register Address {A6 .. AD} = 0100010 = 22 HEX
D7 .. D4
DACP 4-bit code to set peak detector current used to charge the internal 10
pF hold capacitor during the burst acquisition from 6 !lA to 96 !lAo
Code = (1-6 !lA}/5.625. For 6!lA code =0, i.e., 0000
D3 .. DO
4-bit code to set the AGC nominal level at the DP/DN in the Servo mode only.
Nominal level at DP/DN = 1 - Code' 0.0153 Vppd For 0.8 Vppd at DP/DN,
code = 13, i.e., 1101
13-40
Using an SSI 32P4730/31/41/42/44/46
Single-Chip Read Channel Device
SERIAL INTERFACE FORMAT
Reading from a Control Register
The SSI 32P4730/31/41/42144/46 supports a 3-pin
serial interface to write to and read from the control
registers. The three pins are SDEN which enablesl
disables a serial transfer, SCLK which synchronizes
the transfer, and SDATA which is the bi-directional
data pin.
A control register read is also enabled with SDEN =1.
The user must first input the read instruction bit and the
register address. The register content is then
subsequently clocked out at the SDATA pin. The data
packet is structured as: '1' for reading + 7 address bits
(with LSB first) + tristate delay + 8 data bits (with LSB
output first). Each rising edge of SCLK clocks the
instruction bit & the address bits into the device. A
falling edge clocks out the register content. Thus, the
controller may use the rising edge to receive the data.
The SDEN falling edge returns the SDATA pin as an
input pin. Figure 2 illustrates the timing diagram of
reading from a control register.
It is important to terminate the external source at the
SDATA pin within the tristate delay to avoid contention
with the output buffer of the sSI32P4730/31/41/42144/46 ..
Writing to a Control Register
A data transfer is enabled with SDEN = 1. The data
packet is structured as a 16-bit word: '0' for writing + 7
address bits (with LSB first) + 8 command bits (with
LSB first). Each rising edge of SCLK clocks the data
into a 16-bit shift register. Only the first 16 SCLK rising
edges after SDEN becomes 1 are recognized by the
serial interface. The SCLK rising edges after the first 16
are ignored. The 16th rising edge loads the command
bits into the designated register. If less than 16 clock
pulses are provided before SDEN goes low, the data
transfer is aborted. Figure 1 illustrates the timing
diagram of loading command into a register.
The SDEN, SCLK and SDATA are schmitt trigger
CMOS compatible inputs. The minimum input high
threshold is VPD/2 + 0.5V. The maximum input low
threshold is VPD/2 - 0.5 V. VPD is the digital +5V power
supply. These pins should not be left floating at any
time. External pull ups, either through external
resistors to VPD or by external source, are required to
bias them at a known state.
Load data
.--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~o Register
--!~
SDEN
SDEN setup
wrt SCLK rises
H
•
• : SDEN hold
~: wit to SCLK rises
SCLK period
SCLK
SDATA setup. : , SDATA hold
wrt SCLK rises ~ wrt SCLK rises
SDATA 1m'(1
I Aol Al~1XXXXX
FIGURE 1: Serial Interface Timing Diagram - Writing Control Register
SDEN
-.J
SCLK
..
SDATAoutputactive ~..J.
wrt SCLK rises :
::I
SDATA:m'"
L-
I SCLK hold for
~ SDATA turnover
I
:..: SDEN hold
:
I wit to SCLK rises
:
SDATA output
:-.: tristate after
•
: SDENfal1s
SDATApropdeJay
wrt to SCLK falls
~ 001 011 02 103[040
06
1 07)--
FIGURE 2: Serial Interface Timing Diagram - Reading Control Register
13-41
II
Using an SSI32P4730/31/41/42144/46
Single-Chip Read Channel Device
CONTROL REGISTER MAPPING &
SERIAL INTERFACE DESCRIPTION
MODES OF OPERATION & POWER
MANAGEMENT
(continued)
The SSI32P4730/31/41/42/44/46 has several
Operating modes that support Read, Write, Servo and
power management functions. Mode selection is
accomplished by controlling the read gate (RG), write
gate (WG), servo gate (SG) and PWRON pins.
Additional modes are controlled by programming the
Power Down Control Register (PDCR), the Control A
Register (CAR), and the Control B Register (CBR).
This section discusses the controls of each mode. The
detailed operating functions are presented in the
f()lIowing the foll()wing section.
, REGISTER DECODE TIMING
An important consideration in the use of the serial port
is the time taken to decode and change DAC and
control settings. The following is a list of nominal
decode timings taken for the SS132P4730131/41/421
44/46, actual times are application dependent. These
measurements are taken from the 16th rising edge of
SCLK to the.occurrence of the programmed change.
REGISTER
NAME
REGISTER
ITEM
Power Down
TBG
Power Up = 2 J.LS
Data Separator
Filter
Pulse Detector
Max Ic change
Power Up =0.5 JlS
Power Up =25 JlS
Power Up =50 lIS
<1 ps
Data mode
Cutoff
Servo mode
Cutoff
Filter Boost
change
Data
Threshold
Servo
Threshold
Control A
Control B
DECODE
TIME
Max Ic change <1 J.LS
Max boost
<1 J.LS
Threshold %
change
Threshold %
change
MTP3 enable
MTP1,2 enable
RDIOinpuV
output
0.3 J.LS
0.3 J.LS
0.1 J.LS
0.1 J.LS
0.5 J.LS
POWER MANAGEMENT
For optimal overall system power saving, the· SSI
32P4730/31/41/42/44/46 allows flexible power down
options. With PWRON = 1, the entire device is powered
down, except the serial interface and the control register.
With PWRON =0, the device is in Normal Operation
mode. Each individual function can be powered down
by programming the Power Down Control Register. An
important consideration in exercising the power down
functions is the recovery time.
The recovery time from a Power Down mode is
application dependent. While most ofthe internal nodes
within the device can recover very quickly, the I/O DC
bias settling times depend on the external ac-coupling
and bypass capacitors. All TIL logic inputs are not
affected by any power down state. However, for low
power down dissipation, these logic inputs are
recommended to logic '1' state. All TTL logic outputs
are in high impedance states. These logic outputs
return to active state in less than 1 J.LS after power up.
The following are some, notes on the other I/Os power
down recovery behavior.
13-42
Using an SS132P4730/31/41/42144/46
Single-Chip Read Channel Device
II0s power down recovery behavior
Pin
Nominal Voltage
Power Down Voltage
Typical Recovery Time
VIA±
3.5V
4.0V
2J.1S
VOA±
3.5V
4.6V
3J.1S
IN±
3.5V
3.9V
5J.1S
ON±
2.3V
4.7V
2.8 J.1S
OD±
2.3V
4.7V
0.5 J.1S
DP,DN
3.4V
5.0V
6J.1S
CP,CN
3.6V
4.6V
12 J.1S
RX
0.7V
OV
1.5 J.1S
MTP1,2,3
3.6V
3.6V
350 J.1S
TFLT±
- 2V
OV
13 J.1S loop filter dependent
OV
13 J.1S loop filter dependent
DFLT±
- 2V
LEVEL
0.67(Vpp@DP/DN)+2.6V
Leakage effect only
< 1 J.1S
RR
1.6V
OV
0.5 J.1S
RTS (Data mode)
3.0V
3.9V
20 J.1S
RTS (Servo mode)
2.6V
3.9V
0.8 J.1S
RTD (Data mode)
2.6V
3.9V
0.8 J.1S
3.0V
RTD (Se.rvo mode)
3.9V
20 J.1S
A-B
At SREF when Reset
5V
0.5 J.1S
C-D
At SREF when Reset
5V
0.5 J.1S
A+B
At SREF when Reset
5V
0.5 J.1S
BYP
2- 3.5V
Leakage effect only
MAXREF
3.1V
OV
0.5 J.1S
A,B,C,D
At 0.5V when Reset
OV
0.5 J.1S
5.0V
1J.1S
DACOUT
RDIO, PPOL
1J.1S
13-43
II
Us'ingan SSI32P4730/31141/42144/46
Single-Chip Read Channel Device
While the SSI 32P4730/44/46 and the SSI32P47311
41/42 feature different servo outputs, all share the
MODES OF OPERATION & POWER
MANAGEMENT (continued)
READ MODE
When PWRON = 0, RG = 1, WG = X, and SG = 0, the
SS132P4730/31/41142144/46 is in data Read mode. All
the control bits in the Power Down Control Register
l)1ust be reset to o.
rn the data Read mode, all functions ofthe SSI32P47301
31/41/42144/46, exceptthe servo, are active. TheAGC
amplifier amplifies the read signal. The low pass filter
bandlimits the high frequency noise and applies pulse
slimming. The pulse qualifier validates each valid signal
peaks. The time base generator provides an internal
frequency reference to the data separator at 3X (1.5X
forthe SSI32P4741/42144/46) the NRZ data rate. The
data· separator phase locked loop is .locked onto the
read data pulses from the pulse qualifier. The clock is
extracted from the data bits. The data is re~synchronized
and decoded into NRZ data,
The servo outputs remain valid and are held constant
from the previous servo sampling.
WRITE MODE
When PWRON = 0, RG = O,WG = 1, andSG = O,the
SS132P4730/31/41/42144/46 is in Write mode. At the
~ast the data separator and the time base generator
control bits in the Power Down Control Register must
be reset to O.
In the Write mode, the SSI 32P4730/31/41/44/46
accepts the NRZIN input at each rising edge afthe
WCLK. The data is encoded intQ 1,7 RLL codes, unless
t.he ENDEC bypass is chosen for direct write. Write
precompensation, if enabled, is applied to selected
data pattern. The coded data is re-synchronized at the
WD output by the internal data separator reference
clock.
The pulse detector and programmable filter are not
used in the Write mode. The AGC amplifier gain is held
constant at prior to entering the Write mode. The servo
outputs remain valid and are held constant from the
previous servo sampling.
SERVO MODE
same servo sampling sequence in operation. In the
Servo mode, the AGC amplifier remains active. A servo
AGC pattern should be provided for servo AGC with the
HOLD input at '1'. With the HOLD input at '0', the AGC
amplifier gain is held constant. The servo A, B, C and
.0 bursts are sampled and captured.
The servo operation, with the distinctions between the
SSI 32P4730/44/46 and the SSI 32P4731/41/42, is
detailed in the following section.
READ MODE EVALUATION
As a single-chip read channellC, the SS132P4730131!
41/42144/46 supports many functions in Read mode
alone. This section discusses the functions of the
various blocks. Where appropriate, lab experiments
are suggested in evaluation.
PULSE DETECTOR FUNCTION
The pulse detector is the first block in the block diagram
of the SSI 32P4730/31/41/42144/46. It amplifies,
validates and time·preserves the read signal from a
readlwrite pre~amp, such as the SSI 32R2020. The
pulse detector block includes the wideband AGC
amplifier. the AGC control circuitry, the 7-pole
programmable low pass fitter, and the pulse qualifier.
AGC AMPLIFIER & CONTROL
The wideband AGe amplifier accepts a low amplitude
read Signal, typically <200 mVppd, and amplifies it to a
largeramplitude priorto pulse qualification. Because of
varying head-to-media conditions. the amplifier gain is
automatic-gain controlled to provide a 1 Vppd signal at
the DP/DN pins. The amplifier gain is an exponential
function of the voHage at the BYP pin. For reference
usecmly, the gain function isAv= 12 exp{ 2.5 (V@BYP
+2.15 - VPA)}.lnternalclampcircuitryclampsthe BYP
pin voHage between -2.0V and -3.5V. The clamp
resistance is <1 on. It is advised not to sink or source
more than 3 rnA at the BYP pin.
The AGC actions are current charging and discharging
the external BYP integrating capacitor to maintain a 1
Vppd at the DP/DN pins. They are described as follow:
When PWRON = 0, RG = X, WG = X, and SG = t, the
SSI32P4730131/41/42144/46 is in Servo mode. At the
least, the pulse detectorlservo and the programmable
fiHer control bits in the Power Down Control Register
must be reset to O.
13-44
Using an SSI 32P4730/31/41/42144/46
Single-Chip Read Channel Device
Slow Decay
attack sequence commences. (Otherwise only
the Slow Decay mode is available to increase the
AGC amplifier gain.) Figure 3 shows the write-toread AGC action timing. This same sequence is
executed when the device switches from Power
Down to Power Up mode.
When the instantaneous DP/DN signal is below
1 Vppd, a slow decay current, 4.0 uA, charges the
BYP capacitor. The AGe amplifier gain is increased slowly.
SlowAHack
When the instantaneous DPIDN signal exceeds
1 Vppd, but is below 1.25 Vppd, a slow attack
current, 0.18 rnA, discharges the BYP capacitor.
The AGC amplifier gain is decreased.
Fast Attack
When the instantaneous DP/DN signal exceeds
1.25 vppd, the device enters a Fast Attack mode.
A fast attack current, 1.26 rnA, discharges the
BYP capacitor. The AGC amplifier gain is quickly
lowered.
Wrlte-to-Read Recovery
With a 1-10-0 transition of the WG,the SSI
32P4730/31/41/42144/46 enters the Write-toRead Recovery mode. The input impedance
remains in low impedance state for 1 ~ for fast
input DC coupling recovery. Then, the device
restores to high input impedance state, and
enters into a Fast Decay mode. In the Fast
Decay mode, a continuous high current quickly
charges the BYP capacitor until the Signal at DPI
ON exceeds 125% of nominal. After reaching
125%, the high current is disabled and the slow
Read-ta-Servo, Servo-to-Read Recovery
With a 1-10-0 or 0-to-1 transition of the SG, the
SSI 32P4730/31/41/42144/46 enters a HOLDI
Fast Decay mode time period as set by the LowZ time bit in the N-Counter Register. When bit 07
= 0 and there is a transition of SG, the AGC
enters a HOLD mode for 0.4 ~. Following the
HOLD period, the AGC enters a Fast Decay
mode until the signal at DP/DN exceed 125% of
the level set by the SERVO AGC Level register
in Servo mode, or 1 Vpp in Data mode. If the
signal does not reach 125% within the timeout
period, as set by the Low-Z time bit in the NCounter Register, nominally 1 ~, the fast decay
sequence ends and normal AGC actions are
reinstated.
All the AGC actions are suspended in anyone of the
following conditions:
HOLD = 0, or
Write mode.
The AGC amplifier gain is then held constant, except
for leakage effect.
Write
wa-J~_-:-___
SG--.J
I
I
I
I
II'" I
I
Low Input
Impedance
Low I~put
.
t";;;l
Fo.t Diocho,-S~"u':"L--
I'''.ID ' - - -
I
I
I
I
I
~
DPIDN
Envelope
'I
L-I
I
t";:o;;:1 ,
s~
r----1
I~
I
I
Fast Diocho,-e
I
I
I 0.41"'1
I
I
I
I
I
I
I
I
I
I
125% of nominal level
: :r
125%ofnominallovel
----.\......Y'lk-i
DP/DN
E~velOpe
I
I
I
~
I
I
t
I
J
I
I
! Fast:
I
tasl'
Slow
Decay
Attack
I
Decay
FIGURE 3: AGe Action Timing In Recovery
13-45
I
I
I
Slow I
Attack
II
Using an SSr32P4730/31/41/42144/46
Single-Chip Read Channel Device
and CT set the hysteresis threshold time constant
when not in the Servo mode.
READ MODE EVALUATION (continued)
Low Pass FlHer Function
From the head/media point to the AGC amplifier output,
the signal path should have very wide bandwidth, and
is therefore noisy. To reduce false pulse qualification,
the SSI 32P47XX includes a 7-pole 0.05° phase
equiripple programmable low pass fiHerto reject noise
beyond the signal frequency of interest. In addition, this
filter provides pulse slimming equalization for improved
pulse pairing performance. Ideal for zoned bit recording
applications, the filter bandwidth and the pulse slimming
equalization are both programmable through the serial
port. The filter's normal low pass output, ON±, is the
inputto the pulse qualifier.
Hysteresis Qualification: When the Hysteresis
Qualification mode is selected, the same Threshold
Qualification mode is selected, the same threshold
qualification comparators and clock comparators are
used to implement a polarity checking rule. In this
mode, a positive peak that clears the established
threShold level will set the hysteresis comparator and
trigger the bidirectional one-shot that creates the read
data pulses. In order to get another pulse clocked out,
a peak of the opposite polarity must clear negative
threshold level to reset the hysteresis comparator and
trigger the bidirectional one-shot.
An additional function of the filter is to provide a time
differentiated signal of the read data, i.e., 90° phase
lead. EClCh read data peak is translated into a zerocrossing at the OD±. This time differentiated output is
used in time qualification as described in the next topiC.
The control and the dynamics of the fiHer are discussed
in the following sections.
Pulse Qualifier Function
The pulse qualifier transforms each valid analog read
data pulse into a digital pulse, while preserving the
relative time position of each valid pulse peak. Each
DP/DN pulse is validated by a combination of level
qualification and time qualification. The SSI 32P47XX
supports two methods of level qualification: window
threshold qualification and hysteresis qualification. In
time qualification, the time differentiated filter output is
used to locate the signal peaks in time.
Level Qualification
The two options in level qualification are: window
threshold qualification and hysteresis qualification.
Window Threshold (Qual Comparator) Qualification:
When in window Threshold Qualification mode,
independent positive and negative threshold
qualification comparators are used. A slight amount of
local hysteresis is included to increase the comparator
output time when a signal that just exceeds the threshold
level is detected. This eases the timing with respect to
the zero crossing clock comparator. Any peak,
regardless of polarity, which exceeds the programmed
threshold level triggers the read data one-shot.
Qualification thresholds from 10% to 80% may be set
with a resolution of 1%. A parallel R-C network of RTD
----------------I·
-.- ------,-···-1' x
--tS
l.
y
Qual
%=2!...
y
·100%
.............................",.
.. -
................ ..
FIGURE 4: Qualification Percentage Definition
Qualification threshold in percentage is defined to be
the distance between the positive threshold and the
negative threshold as a percentage of the DP/DN
peak~to-peak. The SSI 32P47XX has a 7-bit DAC to
allow flexibility in qualification % setting through serial
port programming, with better than 1% resolution.
Qualification Percentage
=93%· DAC Code/127.
Because the qualification percentage should be
between 30% to 80%, the DAC Code must be limited
between 41 and 109, in decimal. Operation outside of
this range may result in qualification percentage setting
inaccuracy.
The qualification threshold DAC can accept its 7-bit
input code from one of two registers, Data Threshold
Register or Servo Threshold Register, depending on
the Operation mode. Thus, the qualification percentage
can be set separately for the normal data Read mode
and the Servo mode. The MSB bit (D7) of each register
selects the level qualification method, either window
threshold or hysteresis.
Qualification Threshold Time Constant: Because the
qualification threshold is set as a percentage of the
pulse qualifier input's peak-to-peak swing, this threshold
can track with any long term signal amplitude variation
at the DP/ON input.
13-46
Window Threshold Qualification
Hysteresis Qualification
DP/DN
r-----il>--
1'\15
Dour
1'\15
DPIDN
-l1Yesh'
~------~~eOUT
CPfCN ---I
>---- elK
DPIDN
DP/DN
G
C
en
m
_.
_. ::::J
CP/CN
~
.....
01
I
- Threshold
\W/I
\!)
II
VV VV
~
/I
- Threshold
CP/CN
II
v
DOUT
I:
r-----ILIG___________~
02
eLK
eLK
02
01
1'\15
1'\15
1m
9m
_. -
"'Cw
:01\)
(I)"tJ
Q)~
c. .w. . .
COUT
01
::::JCO
COQ)
(i)::::J
I
@ .--------.I=@'--_ _ _--'
O~
::rw
Q)...A.
::::J::::J!:
(1)-~
FIGURE 5: Window Threshold Qualification & Hysteresis Qualification
-
c~
_.
(I)~
<~
(')~
(1)0)
II
Using an SSI 32P4730/31/41142144/46
Single-Chip Read Channel Device
READ MODE EVALUATION (continued)
Qualification Threshold Time Constant (continued)
An external R-C network, with an internal 50 IlA pull
down current source, from the LEVEL output to the
RTD pin (or the RTS pin for Servo mode) determines
the tracking time constant. During the AGC Fast Decay
mode, there is an internal 1.8 rnA pull-down current to
discharge the capacitor at LEVEl. The advantage of
this function is to allow the qualification voltage to be
set after the AGe has settled, guaranteeing that it is not
set too high.
There are two constraints in determining this R-C time
constant:
This time constant should not be too small
such that the threshold may track the noise.
This time constant should not be too large
such that reasonably lower amplitude pulses
are not qualified.
Both constraints are system dependent, specifically
the head/media combination. The user must determine
these limits. However, it is accurate to say that the time
constant should be smaller than that of the AGC loop.
Otherwise, theAGC loop will restore 1 Vppd at the DPI
DN input, and this defeats the purpose of the tracking
threshold.
Lab Experiment 6.1 Pulse Detector Qualification
Threshold Time Constant
The SSI32P47XX supports a tracking qualification
threshold in pulse detection. Givena change in input
signal amplitude, at a rate faster than the AGC loop can
respond, the qualification threshold can remain as a
fixed percentage of the signal level, if its time constant
is set properly. This qual threshold time constant is
determined by an external R-C network between the
LEVEL pin and the RTD (or RTS) pin, with an internal
50 IlA pull down current at the L~VEL pin. Because the
LEVEL voltage is the reference voltage for the internal
7-bit threshold setting DAC, the percentage difference,
in (V@LEVEL - RTD) is the same as the qualification
threshold voltage. The key point is then to allow tlie
LEVEL voltage track with any change in signal amplitude
with the two constraints discussed above.
For this experiment, the' AGC time constant is made
artificially large with a 0.01 uF BYP capacitor. This is to
suppress the AGC action to emphasis the qualification
threshold time constant effects.
What would happen if the qualification threshold time
constant is too large?
A 0.033 J.LF capacitor is connected between the LEVEL
pin and the VPG pin. The resistor is omitted, but the
internal pull down current provides a discharge path.
With 50 IlAdischarge current, the maximum decay rate
at the LEVEL pin is 50 1lAI0.033 W = 1.52 mVIJ.LS.
Nominally, the LEVEL voltage is at 0.65V above the
RTD(RTS) voltage. Thus, the percentage change rate
of the qualification threshold voltage is 1.52/650 x
100% per J.LS = 0.24%/J.LS. (The actual qualification
percentage change is then 0.24%/J.LS x Set Qual Level.
If the qualification level is set at 50%, for example, the
qualification percentage change rate is 0.12%/J.LS.) If
the DP/DN signal changes faster than this rate, the
qualification threshold may not stay at 50% level.
Photo 1A shows the dynamic input signal, the LEVEL
voltage and the RDIO. The input signal changes gradually from 100 mVppd to 40 mVppd, and remains at 40
mVppd for 10 J.LS. The qualification level is set at 50%.
Because of the large time constant, the LEVEL voltage
does not track with the input amplitude. The qualification threshold remains at 50% of the larger input signal.
As a result, the pulses of 40 mVppd are not qualified
and missed. Photo 6.1.2 shows the same signal dy. namics with a 330 pF capacitor from the LEVEL pin to
the VPG pin.
What would happen if the qualification threshold time
constant is too small?
To exaggerate the effects, no external capacitor, except parasitics from scope probe, is placed between
the,LEVEL pin and the VPG pin. As shown in Photo 1A,
the inp!Jt signal has a sequence of 100 mVppd pulses,
followed by a '0' period for 500 ns and two weak pulses
of 20 mVppd. The qualification level is set at 50%.
Should the threshold stays rigid, the two weak pulses
would not be qualified. Because of the small time
constant, the LEVEL voltage varies very rapidly with
the instantaneous input signal. The qualification threshold drops very quickly. As a result, the two weak pulses
are qualified. Photo 6.1.4 shows the same input dynamics, but with a 330 pF capacitor across the LEVEL
pin and the VPG pin. The LEVEL voltage is kept to a
small change during the 500 ns period. The weak
pulses, are not qualified.
13-48
Using an SSI 32P4730/31/41/42144/46
Single-Chip Read Channel Device
:~;;:}
!oj"!
;'
DP/DN
DP/DN
Level
Level
,w<"<,y;,,"'l'_,",w,">;;,,,,,,,
;,
, ,
,)({
"
,
~
,
It'~ M~%;j
*
."
~
,,(,
,
,~~
~~
~ b~
i (
S~<}~
dl~m:t
$
i 1)1~
PHOTO 1A: Qualification threshold at 50%; 0.33
I1F from LEVEL to VPG. Input
changes from 100 mVppd. Large
qual threshold time constant»
Missing RDIO pulses.
PHOTO 1B: Qualification threshold at 50"4; 330
pF from LEVEL to VPG. Input
changes from 100 mvppd. Proper
qual threshold time constant» All
RDiO pulses present.
PHOTO 1C: Qualification threshold at 50%; no
cap from LEVEL to VPG. Input with
"noise blips" at 20"4 amplitude.
Small qual threshold time constant
» False trlgered ROIO pulses.
PHOTO 1D: Qualification threshold at 50"4; 330
. pF from LEVEL to VPG Input with
"noise blips" at .200/0 amplHude.
Proper qual threshold time constant
» No false trlgered RDIO pulses.
13-49
II
Using an SSI32P4730/31/41/42/44/46
Single-Chip Read Channel Device
READ MODE EVALUATION (continued)
PULSE DETECTOR I/O & TEST POINTS
An excellent troubleshooting aid is to know the inputs, the outputs and the available test points. For the pulse
detector portion, this is a list of the related pins:
NAME
TYPE
DESCRIPTION
VIA±
I
Differentialanalog input to the AGC amplifier: The input should be ac-coupled
from the source. The input amplitude should be limited to between 20 mVppd
to 240 mVppd when no boost is applied at the fItter. When boost is applied, the
input amplitude should be lowered, as not to exceed the dynamic range of the
AGC amplifier and the filler. The DC bias voltage is approximately 3.5V.
VOA±
0
Differential analog output of the AGC amplifier: The output should be accoupled to the the filter input. In a closed AGC loop, its amplitude depends on
the filter cutoff and boost setting. The DC bias voltage is approximately 3.5V.
BYP
I
AGC amplifier gain control pin: The input voltage controls the AGC amplifier
gain. An integrating capacitor should be connected from the BYP pin to VCC.
This voltage should be between 2V to 3.5V.
HOLD
I
TIL logic input: When HOLD = 0, the AGC amplifier gain is held constant.
When HOLD = 1, or left open, the AGC loop is active.
IN±
I
Differential analog input of the filter: The DC bias voltage is approximately
3.5V. The VOA± should be ac-coupled to this input.
ON±
0
Differential normal low pass filter output: This output should be ac-coupled to
the DP/DN input. It is simply the filtered version of the IN±. In a closed AGC
loop, it should be - 1 Vppd. The filter has a nominal gain of 2.0V/V in the
passband. However, the gain can be higher at frequency where boost is
applied. The DC bias voltage is approximately 2.3V.
OD±
0
Differential differentiated low pass filter output: This output should be accoupled to the CP/CN input. It isthe bandlimited time differentiated version of
the IN±. Every peak (positive or negative) is translated into a zero crossing. Its
amplitude is frequency dependent. The DC .bias voltage is approximately
2.3V.
DP/DN
I
Differential input to the pulse qualifier: The ON± should be ac-coupled to this
input. The DC bias voltage is approximately 3.6V.
CP/CN
I
Differential input to the time qualifier: TheOD± should be ac-coupled to this
input. The DC bias voltage is approximately 3.6V.
RDIO
I/O
Read data I/O pin: This is a bi-directional TIL compatible pin. When Control
B Register 02 = 1, the RDIO is an input pin for the data separator. When the
Control B Register 02 = 0, the RDIO is an output pin. When this pin is
configured as an output pin and both RG = WG = 0, the RDIO represents the
pulse detector read data output. A pulse is generated for every qualified peak.
With either RG or WG being 1, the RDIO is held at static 1.
PPOL
I/O
Pulse polarity indicator: This is an optional TIL output indicating the polarity
of the input pulse. A positive qualified pulse puts a logic '1' at the PPOL output.
A negative qualified pulse puts a logic '0' at the PPOL output. This output is
enabled when RG = WG = O.
13-50
Using an SS132P4730/31/41/42144/46
Single-Chip Read Channel Device
PULSE DETECTOR I/O & TEST POINTS (continued)
NAME
TYPE
DESCRIPTION
DACOUT
0
Multiplexed DAC output: When Window Shift Register (05 HEX): 07-6 = 01,
DACOUT represents the qualification threshold setting DAC output. The
qualification threshold DACOUT voltage can be estimated to be about 4.96 (0.0129 x DACVth) Volts, where DACVth is equal to the 7 bit register value of
the pulse detector qualification threshold in data or Servo mode
MTP1-3
-
Open emitter output test points: These test points are governed by the
following logic control.
Control B Reg
Control A Reg
06
05
06
MTP1
MTP2
MTP3
0
0
X
1
1
i-
1
1-
0
1
X
i-
1
0
0
VCOREF
OS-IN
SRD
1
0
1
RD·
DOUT
DSREF
1
1
0
P~Q
PUQ
SRD
1
1
1
SET
RESET
NCTR
VCOREF
I
OS-IN
I
= inputto data synchronizer in Read mode, this is the delayed read data. In non
. Read mode, this isthe output of the time base generator/2 (/1 for 4741/42144)
= reference input to the data synchronizer phase detector,
VCO REF = VCO /2(= VCO for 4741/42144)
OS REF
0
= reference frequency to the data separator, i.e., time base generator output
NCTR
I
= time base FREF divided down signal, an input to the time base phase
detector
RD
I
= Read data output of the pulse detector, i.e., input to the 1/3 cell delay
DOUT
0
= output of the data comparator in hysteresis qualification
SET
0
= output of the positive threshold comparator in window threshold qualification
RESET
0
= output ofthe negative threshold comparator inwindow hreshold qualification
SRD
I
= Synchronized Read Data, qualified pulses sychronizedto the OS VCO, input
to the'Decoder
PDQ
-
= Data Separator phase Detector pump down edge, for testing use
PUQ
1
1-
= Data Separator Phase Detector pump up edge (inverted), for testing use
= logiC 1
= logic 1, but with slightly higher power dissipation
13-51
II
Using an SSI 32P4730/31 /41 /42/44/46
Single-Chip Read Channel Device
READ MODE EVALUATION (continued)
PULSE PAIRING
Pulse pairing causes decode window margin degradation. In pulse detection, each signal peak, positive or
negative, transforms into a digital pulse. Due to comparator offset in the time channel qualification, a positive
peak and a negative peak may be detected with a slight time skew. Pulse pairing is defined in Figure 6.
DPtDN
Puis. Pairing _
I Tl • T~
2
ic- T1+T2~
FIGURE 6: Pulse Pairing Definition
Lab Experiment 2 Pulse Pairing
Pulse pairing degrades the decode window margin the most when the decode window is the smallest, Le., the
highest data rate. Pulse pairing is expected to be worse with signal having slower slew rate althe qualification
thresholds. This lab experiment examines the pulse pairing with a 2.25 MHz sinusoidal input, Le., the lowest
frequency signal of 24 Mbit/s operation, A 1 Vppd sine wave is fed directly into DP/DN at 2.25 MHz, the same
signal is fed into CP/CN with a 90° phase-lead, and filtered to remove 2nd and 3rd harmonics. With a time
interval analyzer, the distance between successive pulses at the RD is "histogram-ed". The histogram will
include the effect of pulse pairing from the pulsedetectof. While the jitter is gaussian distributed, the pulse
pairing is a systematic error for a given part. When significant pulse pairing is present, the historgram would
show a bi-modal distribution with two peaks. In a jitter dominant distribution, the insignificant pulse pairing
would be unobservable.
PHOTO 1E: Time Distribution of RD with 2.25 MHz sinusoidal input. Guassian distribution - no
bl-modal distribution. Noise jitter - 201 ps; Pulse pairing < 0.05 ns.
Higherfrequency read data signals produce faster transitions through zero atthe CP/CN inputs. This reduces
the effect of any offset at the clock comparator. Pulse slimming equalization emphasizes the high frequency
components 01 the input signal which leads to less pulse pairing.
13-52
Using an SSI 32P4730/31/41/42144/46
Single-Chip Read Channel Device
PROGRAMMABLE FILTER CHARACTERISTICS
The 551 32P4731/31/41/42144/46 features a on-chip programmable 7-pole 0.05° phase equiripple low pass
fiRer/equalizer. This filter serves three functions: (1) noise limiting low pass fiRer of the read data signal, (2)
time differentiating the read data signal for signal peak. location, and (3) high frequency boost for pulse
slimming equalization. The cutoff frequency, to be defined below, is programmable from 3 MHz to 9 MHz(6
to 18 MHZ for 551 32P4741/42144/46). The boost function can be programmed up to 13 dB. Both functions
are controlled by command registers programmable via the serial interface.
The cutoff frequency, fc, is defined to be the -3 dB bandwidth with no boost. When finite boost is applied, the
effective -3 dB bandwidth is higher than the cutoff frequency. Table 2 lists the bandwidth increase vs the
applied boost ..
Table 1 Filter Bandwidth Increase vs Boost
Boost (dB)
New -3dB Bandwidth /
Cutoff Frequency
Boost (dB)
0
1
1.00
1.21
7
8
New -3dB Bandwidth /
Cutoff Frequency
1.50
9
2.42
2.51
2.59
10
2.66
5
1.80
2.04
2.20
11
12
2.73
2.80
6
2.32
13
2.86
2
.
3
4
The high frequency boost is defined to be the amount of magnilude rise at the cutoff frequency, relative to the
original-3 dB point. A 13 dB boost would mean a 10 dB peaking above the passband.
8iquod3
2.95139
131703
.2+ 1.68495. + 131703
8iquod4
537034
•z.. 1.$4.203. + 295139
.2+ 1.14558. + S.37034
Biquod2
• ~ 1.68495. + 131703
Nonnalized for me = 21t I. = 1 radls
Denonnalize the frequency by substituting s => (s/21t I.)
e.g.,
f.
I~~RM
s+ 0.86133
I~ ~
= 8.0 MHz, s=>sI[21t(8x 106 )]
FIGURE 7: Programmable Filter Normalized Transfer Function
AN = 1.17 and AD = 1.51 for unily gain (0 dB) at 0.67 fe
K varies from 0 to 4.57 for boost up to 13 dB, where
Boost (dB) = 20 log 0.759284 (1.31703 + K)
Figure 7 shows the normalized transfer function of the programmable fiRer. As a 0.05° phase equiripple filter,
the group delay variation is minimal within the passband and up to - 2 x fC. One fact not denoted in the transfer
function diagram is thatthe DIFF± output is delayed by 1.2 ns relative to the NORM±. This is to ensure sufficient
data setup time for a flip-flop in the pulse qualifier.
An 1% 12.1 kQ resistor and a 0.01 IlF are needed from the RX pin to ground for fiRer biasing.
13-5.3
II
Usihgan SSI 32P4730/31/41/42144/46
Single-Chip Read Channel Device
READ MODE EVALUATION (conlinued)
CUTOFF CONTROL
For optimizedsignal-to"noise performance in a zoned recording application, the SSI32P4731/31/41/42144/
46 provides a programmable low pass filter. The filter cutoff frequency isprogrammablefrom3MHzt09MHz(6
to 18MHZfor4741142144) by the Ic DAC, anon-chip.7-bit DAC.ln any non-Servo mode, i.e.,SG == 0, the Fc
DAC is controlled by the Data mode Cutoff Register. In the Servo mode, i.e., SG == 1, the Ic DAC is controlled
by the Servo mode Cutoff Register. This allows immediate banqwidth adjustment switching between data
Read and Servo mo,des.
..
'.
The filter cutoff frequency is determined as: Ic (MHz) == 9 Code/127 (18 o Code1127 for SSI 32P4741 142/44/
46). In general, the cutoff frequency should be set to about the maximum signal frequency at the given data
rate. However, the user should optimize the filter cutoff setting for a given head/media system combination.
0
BOOST CONTROL
For pulse slimming application, the programmable filter allows high frequency boost equalization. The filter
boost is programmable from 0 to 13 dB by the Fb DAC, an on-chip 7-bit DAC. The Fb DAC is controlled by
the lower 7 bits ofthe FiHer Boost Register. In the Servo mode, i.e., SG == 1, the boost can be enabled/disabled
by the MSB of this control register.
The filter boost is set as: Boost (dB) == 20 log [(0.0273 Code) + 1). This boost setting should be optimized
for lowest bit error rate for a given head/media system combination.
0
Lab Experiment 3 Programmable Filter Frequency Response.
In zoned bit recording application, the data transfer rate increases from the inner zone toward the outer zone.
For optimized signal-to-noise performance, the accuracy -in setting the programmable cutoff and boost is
critical. This lab experiment is to examine the filter's magnitude and group delay response.
Magnitude & Group Delay Frequency Response
With a network analyzer, the frequency response of the SSI32P4731 131/41/42144/46 programmable filter can
be swept very easily. The sweeping source is applied to the filter input directly. The filter output is returned
to the network analyzer for magnitude & group delay response analysis. One note is thaUhe source signal
must be kept small enough such that its output is within 1 Vppd at all time, not to exceed the dynamic range.
The filter has a nominal gain of 2 V/V Without boost applied. When maximum 13 dB boost is applied, the input
source should be kept below 150 mVppd. For this experiment, the input source is set to 100 mVppd.
Furthermore; the device is in Idle mode. The Fc DAC is controlled by the Data mode Cutoff Register.
13-54'
Using an SSI 32P4730/31/41/42/44/46
Single-Chip Read Channel Device
BANDWIDTH CONTROL SWITCH FROM DATA MODE CUTOFF REGISTER TO SERVO MODE CUTOFF
REGISTER
To support system application flexibility, the SSI32P4730/31/41/42144/46 allows automatic filter bandwidth
switch from the Data Read mode to the Servo mode. When SG = 0, the cutoff control is from the Data mode
Cutoff Register. When SG =1, the cutoff control is from the Servo mode Cutoff Register. In the Servo mode,
when the boost is enabled by the MSB of the Filter Boost Register, the same boost setting is used as in the
data Read mode. The boost function can be disabled in the Servo mode by setting the MSB to 1.
However, there is no easy way to monitor bandwidth change in the frequency domain following a SG transition.
One method to assess the bandwidth switching time is measure the settling time of the filter output amplitude,
which is caused to change due to bandwidth switching. This experiment is done as follows:
Program the Data mode Cutoff Register to 127, i.e., 9 MHz fc in Data Read mode,
Program the Servo mode Cutoff Register to 42, i.e., 3 MHz fc in Servo Read mode,
Program the Filter Boost Register to 127, and boost disabled in Servo mode,
Input a 100 mVppd @ 9 MHz signal,
Stay in data Read mode for 10 IJ.S, with AGC loop active,
Remain in Data Read mode for 51J.S, with AGC gain held constant,
Switch to Servo mode,
Observe the filter output amplitude change, because input frequency is out of servo cutoff.
Return to data Read mode and activate the AGC loop.
Photo 1F shows the SG transition and the filter output amplitude change. After the SG 0-to-1 transition, the
filter output amplitude settles in 320 ns.
PHOTO 1F: SSI 32P4730/31 Filter ContrOl Switching from Data Mode to Servo Mode
13-55
II
Using an SSI 32P4730/31/41/42144/46
Single-Chip Read Channel Device
READ MODE EVALUATION (continued)
Programmable Filter 110 & Test Points
In troubleshooting the programmable filter, the following 1/0 and test points should be examined:
IN±
Differential analog input of. the fiHer:The DC bias voHage is approximately 3.5V. The AGC
amplifier output, VOA±, should be ac-coupled to this input.
ON±
Differential normal low pass fiHer output: This output should be ac-coupled to the DP/DN input.
It is simply the filtered version of the IN±. In a closed AGCloop, it should be - 1 vppd. The fiHer
has a nominal gain of 2.0VN in the passband. However, the gain can be higher at frequency
where boost is applied. The DC bias voltage is approximately 2.3V.
OD±
Differential differentiated low pass fiHer output: This output should be ac-coupled to the CP/CN
input. It is the bandlimited time differentiated version of the IN±. Every peak (positive or
negative) is translated into a zero crossing. Its amplitude is frequency dependent. The DC bias
voHage is approximately 2.3V.
RX
Reference resistor pin: An external 1% 12.1 kn resistor and a 0.01 f.J.F capacitor should be
connected from this pin to ground. The voltage at this pin is proportional to absolute
temperature. At room temperature ambient, this voltage is typically measured to be 700 mV.
DACOUT
MuHiplexed DAC output: When Window Shift Register (05 HEX): D7-6 == 00, DACOUT == Ic
DAC. The voltage at DACOUT in this mode can be estim;lted to be 0.7 +(0.006425· DACFc)
where DACFc is the 7-bit register value of fiHer cutoff frequency in data or Servo mode.
TIME BASE GENERATOR FUNCTIONALITY
The SSI32P4731/31/41/42144/46 includes a time base generatorto support the variable data rate in a zoned
recording application. The data separator VCO requires a 3X (t.5X for SSI 32P4741/42144/46) data rate
reference frequency (not to be confused with FREF, whichisreference to the time base generator). Thus, for
24 Mbitls operation, a 72 MHz ( 36 MHZ for SSI 32P4741/42/44/46) reference is needed to the data separator.
The lime base generator provides such a stable reference frequency.
The SSI32P4731131/41/42144/46 time base generator is a phase locked loop based frequency synthesizer,
Figure 6.4.1. If Control A Register: D4 == 0, the time base g.enerator output, Fout, is made programmable by
loading two divide-down factors achieving belterthan.1% resolution up to 75 MHz. If the Control A Register:
D4 == 1, the frequency synthesizer is bypassed. The time base.generator output is at the same frequency as
FREF. FREF should be limited beween 8 MHz to?O MHz ..
In the frequency synthesizer Active mode, Fout == FREF· {(M+ 1)/(N + 1)]. The N factor is a 7-bit code in the
N Counter Register. The M factor is a 8-bit code in the M Counter Register. How do you determine the optimal
Nand M codes? There are several important factors.to consider in qhoosing M & N values.
A high frequency resolution is gained by using higher M & N values.
The size of the loop filter integrating capacitor is dependant upon the value of N. The capacitor
should be kept small to avoid large physical geometry &high leakage typically associated with large
capacitors.
13-56
Using an SSI32P4730/31/41/42144/46
Single-Chip Read Chann~1 Devic.~
C2
rll-::-
TFLT~
FREF
TFLT
SSl32P471O 131
-----1
+ (N + 1)
f--r--
--
Phase
DetecIof
veo
Foul
to Data Saparator
+(M+l)
FIGURE 8: Time Base Generator Functional Model Diagram
For a given loop filter design, the TBG must be stable for the frequency settings of aU zones. In
theory, if the damping factors in aU zones are kept above 0.707, stability can be guaranteed. In
practice, a damping factor of 1 is suggested.
While the TBG loop filter is a differential design, any effect due to the Common mode bias mismatch
between the positive and negative sides should be minimized. By using the lowest M and N values,
with acceptable frequency resolution, the phase update rate would be the highest and the Common
mode mismatch effect would be minimized. As an additional advantage, the. integrating capacitor
would be higher using lower M and N values. The integrated mismatch effect would be a smaller
error voltage across the VCO control pins.
It can be seen from the analysis that follows that it is possible to maintain a dam(Jing factor of z = 1 for all zones
by making (M + 1) proportional to the data rate squared. Figure 9 illustrates a flow chart to determine the M
and N codes.
The M and N counters can be programmed anytime. However, they only become effective after a Data Rate
Register programming. This is to reduce any transient condition for the phase locked loop in new data rate
programming.
An external differential passive loop filter is needed in the phase locked loop. This loop fiHer design allows a
design trade-off between PLL settling time and noise jitter performance. The differential architecture
minimizes external noise pickup. The loop filter design details are presented in the next section.
13-57
II
UsinganSSI 32P4730/31/41/42!44/46
Single-Chip Read Channel Device
Select N(O), where N(O) is the N value for the lowest data rate zone.
N(O) = 2 is suggested to start with.
Compute N(i) and M(i) for the highest data rate zone, where
N(i) = INTEGER ( IN(O) + 11· I (KVCO(i) • KDQ) • DataRate(O) )
I ( KVCO(O) • KD(O) • DataRate(i) ) 1}. 1
M(i) ~ INtEGER (IN(O) + 11· I (3· Data Rate(i» I FREFI}· j
No
No
No
FIGURE 9: M & N Codes for Time Base Generator
1s:.58
Using an SSI32P4730/31/41/42/44/46
Single-Chip Read Channel Device
READ MODE EVALUATION (continued)
TIme Base Generator Loop Filter Design
The SSI 32P4731 131 141142144/46 requires a loop filter to control the PLL locking characterisitcs. While there
are several types of filters that can be used to perform this function, a simple differential integrating filter,
Figure 8 has proven to be very effective.
In designing the loop filter for the TBG PLL, two key considerations should be noted:
PLL settling time
.
In zoned recording application, the TBG output frequency must vary with data rate changes from one
zone to another. When the M Counter Register is updated, the PLL will acquire and settle to the correct
output frequency. This settling time should be less than the minimum track-to-track seek time.
•
C1 capacitor must have low leakage. Typically, C1 should be selected to be less than 0.1 IlF.
The loop filter bandwidth must be large enough for the PLL to settle fast. Yet, the time jitter performance is
improved by a lower filter bandwidth. Thus, the bandwidth should only be large enough to meet the PLL settling
time requirement.
Figure 8 shows the functional model diagram. C2 is typically designed to be only one-tenth of C1, for high
frequency noise shuntpurpose. It may be neglected in the R1 and C1 design consideration. From secondorder linear analysis, the loop response can be shown to be:
KD = Phase Detector Gain
eI reference input phase
eo= VCO output phase
=
vyeo = loot
eo =
eo
e. =
• F(s)
KVCO·Vyeo
(M + 1)
F(s) = Loop Filter Transfer Function
KVCO = VCO Gain
KVCO • KD • F(s) I (M+ 1)
F(s) = RI + _1_
SCI
s + KVCO· KD· F(s) I (M+l)
KVCO • KD • (1 + s RICI)/[CI(M+ 1)]
s 2;- s KVCO • KD· RI + KVCO • KD
'{mI) CI(M+l)
Let the characteristics equation be written as:
ro! =
KVCO • KD
CI(M +1)
KVCQ·KD·RI
2(M+ 1)w"
M & N values are selected through the algorithm given in Figure 9 A damping factor of ~ = 1 is chosen, and
M is proportional to the data rate so that the damping factor and bandwidth remain constant as the data rate
decreases. The acquisition time of the loop is set-up to accomodate a zero phase restart and allow for 1 %
maximum phase error after phase acquisition. According to Figure 2 in the Data Synchronizer Family
Application
this gives
an wnT = 5.2 Where T = settling time, T must be less than track-to-track seek time,
•
.
typically <0.1 ms
13-59
II
USing an SS132P4730/31141/42144/46
Slngle;.Chip Read Channel Device
READ MODE EVALUATION (continued)
Time Base Generator Loop Filter Design (continued)
For the SSI 32P4730/31 at 24 MbH/smaximum data rate and the SSI 32P4741/42144/46 and 48 MbHls
maximum data rate the timebase generator will run at 72 MHz. Given FREF = 18 MHz, the loop filter design
KVCO = 0.17 wVCO = 0.17 - 2pi- 72 = 76.9 Mrad/(V-sec)
is as follows: From the data sheet,
DR Code = 108 for 24 MbHls (48 Mbitls for SS132P474X)
(refer to electrical spec for
KD = 2.0304 - DR Code + 10.4394 = 229.71lA/rad ,
correct value)
C1 = 0.086 J.JF C2 = 0.0086 J.JF R1 = 4470
'
In the following table, R1, C1 and C2 are chosen base,d on the maximum data rate. ron and ~a(e then
recalculated based on other data rate requirements and the '~alculated loop filter component values.
ZONE
DATA RATE FOUT
N
M
FOUTDRCODE
KD
KVCO
T
ron
(ms)
Kradls
Z
(MbHls)
(ideal) MHz
0
24 (48)
72
18 75
72
108
229.7
76.9
0.100
52.0
1
1
20 (40)
60
14 49
60
88
189.1
64
0.098
53.1
1.02
(actual) MHz
(IlA/rad) Mrad/(V-s)
2
18 (36)
54
13 41
54
79
170.8
57.7
U.100
52.2
1.00
3
15 (30)
45
11 29
45
65
142.4
48
0.101
51.5
.991
4
12 (24)
36
8
17
36
50
112
38.5
0.099
52.7
1.01
Time Base Generator Jitter Performance
Jitter performance is an important figure of merit for a time base generator. For a single-chip read channel
device, jitter can degrade a drive system in two areas: (1) noisy reference clock to the data separator, and (2)
write data clock instability. Because the data separator is re-trained and re-Iocked to the read data pattern,
the former is not as critical as the latter.
One method to minimize the TBG output jitter is by limiting the TBG PLL loop filter bandwidth. However, the
loop bandwidth must be wide enough to allow fast acquisition time.
The SSI 32P4731 131/41142144/46 features very low output jitter. With the proper loop filter deSign, the SSI
32P4731 131/41/42144/46 rms jitter is specified as <200 ps. For deSign purposes, the tilne jitter six sigma would
be <+ or - 600 ps.
Lab Experiment 4 Time Base Generator JHter Measurement
This lab experiment demonstrates the SSI 32P4731/31/41/42144/46 time base generator low jitter performance. Because jitter is the uncertainty of the zero crossings at the time base generator output, the lowest
output frequency signal should be the worst case representative. Using ,12 MbHls as the, lowest data rate
calculated for the SSI 32P4730 in the previous section, the lowest TBG output frequency would be 36 MHz.
The loop filter is that as calculated in Section 6.4.1. The MTP3 test point is configured to monitor the data
separator reference clock, which is the TBG output. The SSI 32P4730 is in Write mode, RG = SG = 0, WG
=1. With an 18 MHz FREF clock to the TBG PLL, the N Counter Register is loaded with N = 8decimal.
The M Counter Register should be programmed to M = 17decimal for 24 MHz TBG output and the Data Rate
Register is programmed for 12 Mbitls.The MTP3 period is histogramced with a time interval analyzer and an
active FET probe. Photo 2A shows a Gaussian distribution ofthe time jitter, withone,standard \;leviation of 150
ps. The importance of measuring TBGjitter is to see it's effect on Write Data jitter performance. The bestway
of measuring this is to directly measure Write Data~ Using the previous settings, WCLK is tied to RRC and
NRZIN is pulled low. A '3T' pattern appears as WD which is histogram-ed with a TIA. Photo 2B shows a
Gaussian distribution of the time jitter, with one s.d. of 61 ps.
13-60
Using an SSI 32P4730/31/41/42/44/46
Single-Chip Read Channel Device
PHOTO 2A: SSI 32P4730/31 Time Base Generator Jitter Measurement.
Time Base Generator 1/0 & Test Points
The SSI32P4731/31/41/42/44/46 Time Base Generator has only one input and two test points.
FREF
TTL frequency reference input: This input provides a reference input to the TBG PLL. It should
be limited to between 8 MHz to 20 MHz. When the TBG is bypassed, as commanded by Control
A Register: D4, the data separator PLL reference is the signal at the FREF input.
MTP3
This test point can be configured to monitor the TBG PLL output clock, FOUT.
MTP2
This test point moniters the input to the Data Separator phase detector, i.e., the timebase
generator output in Idle mode.
PHOTO 2B: SSI 32P4730/31 Write Data Jitter Measurement
13-61
II
Using an SSI32P4730/31/41/42/44/46
Single-Chip Read Channel Device
READ MODE EVALUATION (continued)
DATA SEPARATOR FUNCTIONALITY
The SSI32P4731/31/41/42/44/46 Data Separator performs the following functions:
Synchronization,
RLL 1,7 encode & decode,
Address mark generation & detection (for soft sector application),
Preamble generation & detection,
Write pre-compensation,
Window shift adjustment.
Synchronization
For synchronization, the data separator has two objectives:
Clock regeneration, and
Encoded data synchronization.
Clock Regeneration
Because the data is coded with the clock signal, the clock must be regenerated for precise timing. Forthe SSI
32P4731/31/41/42/44/46, the clock regeneration is accomplished with a phase locked loop comprised of a
phase detector, a loop filter and a voltage controlled oscillator (VCO). The VCO runs at 3X (1.5X for SSI
32P4741/42/44/46) the NRZ data rate. For 24 MbiVs operation, the VCO should run at 72 MHz (36 MHZ for
SSI32P4741/42/44/46). How would the VCO clock align with the encoded data bits?
In the Idle mode, i.e., RG = WG = SG = 0, the VCO is phase & frequency locked to the time base generator
output, Foul, which can be either a frequency synthesized signal or FREF. With the TBG output at 3X (1.5X)
the NRZ data rate, the VCO is centered for a subsequent readlwrite cycle. The RRC is at the NRZ data rate,
which is Foutl3. (Foutl1.5 for SSI32P4741/42/44/46).
Entering into the Read mode, i.e., RG O-to-1 transition and following the first 3 ORO transitions, the phase
detector reference input switches from the TBG output to the delayed read data, ORO. A preamble pattern
of 19 '3T' is used for training the VCO to phase-lock to the ORO.
To reduce the initial phase error, the SSI 32P4731/31/41/42/44/46 employs a zero-phase restart technique
which, after 3 ORO transitions, halts the VCO momentarily until the 4th ORO transition is detected. The initial
phase error is limited to below 2 ns ofthe decode window. For 24 Mbitls operation, this represents - 7% error,
or 0.45 radian.
One of the two VCO Locking modes will be entered depending on the state of the gain shift (GS) bit, or bit 1,
in the Control B register. If GS ="1," the phase detector will enter a Gain Shift mode of operation. The phase
detector starts out in a High Gain mode of operation to support fast phase acquisition. After an internal counter
counts the first 14 transitions of the internal of the internal ORO signal, the gain is reduced by a factor of three.
This reduces the bandwidth and damping factor of the loop by v3 which provides improved jitter performance
in the Data Follow mode. The counter continues to count the next 5 ORO transitions (a total of 19 x 3T from
assertion of RG) and then asserts an internal VCO lock signal.
With the internal VCO lock asserted, the following two events are initiated:
The RRC is now switched from Foutl3(1.5 for 474X) to VCO /3(1.5 for 474X). During this switching,
the RRC may be held static for a maximum of 2 NRZ clock periods. However, the sSI32P4731/31/
41/42/44/46 guarantees no glitch on RRC.
The data synchronizer decode window, to be defined in the next section, boundaries are by the next
two '3T' pattern.
Following this, the NRZ output is enabled and the data is toggled through the decoder throughout Read mode.
13-62
Using an SSI 32P4730/31/41/42/44/46
Single-Chip Read Channel Device
When the Gain Shift bit is set to "0", the phase detector gain shift function is disabled. The VCO lock sequence
is identical to that of the Gain Shift mode explained above, except that no gain shift is made after the first 14
'3T's' (i.e., the phase detector is always in high Gain mode). Figure 9 illustrates the clock regeneration process.
RG
RRC
.J
uncertain. but no gUtdl; hand
off from Fout to veo;
RRC aligning to ORD
~
___ .n....rL.JUL.. __ IlJl •••••• Ji1...I"1...fLI
VCO
VC0+2 ~ ___
DRD
o
®
®
1
Iran-.... VCM
32H6810A
D/A
AID
FIGURE 4: Servo System Interconnection Example
Area and Peak Detectors
Area and peak detection are different approaches to demodulating the fine position information contained in the
servo frame. These two detection schemes differ in their respective features.
Area detection relies on integration of some aspect of the fine poSition burst signal. Area detection tends to offer
superior noise rejection but requires greater timing precision. Symmetrical noise appearing during the burst will
both add and subtract from the integralthereby canceling itself out. The integration window should be synchronous
with the burst zero crossings for consistent area demodulation and some form of zero-crossing detector is
required. Area detection can be performed over fewer cycles of burst and therefore the total servo frame time can
be reduced yielding greater user data capacity.
Peak detection is simpler to implement but is more sensitive to noise. The peak detector sampling window may
be enabled asynchronously with the burst carrier and therefore this type of demodulator is most compatible with
digital timing ASICs. Though simple in concept, the peak detector always needs some form of signal conditioning
to improve noise rejection. The attack time of the peak detector can be slowed so that the final demodulated value
represents an average of multiple cycles. This averaging approach reduces the contribution of a noise spike at
the expense of requiring more burst cycles to complete the sample.
The following table lists various Silicon Systems devices which offer embedded servo demodulation functions:
DEVICE
TYPE
COMMENT
SSI32H4633
Peak
Four peak detectors
SSI32H6520
Area
Four area detectors
SSI32H6521
Area
SSI32H6830
external
Four area detectors
Four differential AID inputs
SSI32P544
Peak
Dual peak detectors
SSI32P3013/15/16
Peak
Four peak detectors
SSI32P3031
Peak
Dual peak detectors
SS132P4741/42146
Peak
Four peak detectors
SSI32P4901
rectifier
Full wave rectifier only
13-89
II
Servo Controllers and
Motor Drivers
SERVO DEMODULATORS (continued)
Read Channel and Servo Controller Interface
The interface between the servo controller and the read channel will be determined by the type of embedded servo
demodulator used. Many read channel devices include peak detectors which will feed an analog multiplexer in the
servo controller. Other read channel devices full-wave rectify the read signal andthe servo controller demodulates
the position signal using area integration.
The read channel and servo controller interface is best illustrated by two examples. The first example relies upon
peak detection performed in the read channel and data conversion in the servo controller. The second example
demodulates the servo position signal in the servo controller using area integration.
Peak Detection and Data Conversion
An example which implements peak detection in the read channel device and data conversion in the servo controller
is found in the 32P4746/SSI32H6521 interface. This interface consists of four Signals illustrated in Figure 5.
A servo reference voltage of approximately 2 .25V issupplied by the servo controller from the band-gap reference
on the SSI32H6521 to the SSI32P4746 SREF pin. The SSI32P4746 provides three processed position signals
representing burst differences A-B, C-D and sum A+B. These three position signals are zero referenced to SREF
such that when A=B, the voltage on the BURST A-B pin will be SREF.
The processed bursts from the SSI32P4746 are directly connected to the SSI 32H6521 analog inputs ADCIN2,
ADCIN3, and ADCIN4. AID conversions may be started from the digital timing generator by triggering the ADCSTR
pin on the SSI 32P4746 or by the microcontroller reading the SSI32H6521 register address three.
In this example, the area integration capability of the SSI32H6521 was not used; instead, the external AID inputs
through the analog multiplexer were utilized to acquire the position information. The SSI 32H6520 read channel
interface is identical to the SSI 32H6521.
The SSI32H6830 SEEKER™ DSP offers a similar data conversion interface. The SSI32H6830 does not contain
area inte~rators but does offer external AID inputs like the SSI 32H6521 used above. Figure 6 illustrates the
SEEKER M interface which makes use of a configurable differential amplifier useful in scaling the burst amplitude
to match the AID conversion range.
32H6521
32P4746
A-B
1 - - - - - - - - - 1 ADCIN2
C-D
I - - - - - - - - - f ADCIN3
I - - - - - - - - - f ADCIN4
SREF
I - - - - - - - - - f VREF
FIGURE 5: Peak Detection Interface Example
13-90
Servo Controllers and
Motor Drivers
Ri
R2
32P4742
A
B
C
MUX
D
MAXREF
32H6830
ZEROREF
FIGURE 6: Alternative Peak Detection Example
Full"Wave Rectification and Area Integration
An example which implements full-wave rectification in the read channel device and area integration in the servo
controller is found in the 32P490i/SS132H652i interface. This interface consists of two signals illustrated in figure 7.
The read channel device is responsible for full-wave rectifying the servo burst. The servo controller accepts from
the read channel, the fUll-wave rectified signal and zero signal reference. The SEROUT pin of the SSI 32P4901
is the full-wave rectified signal and the zero reference is output on pin SERREF. A differential amplifier in the servo
controller internally level shifts the position signal for integration and presentation to the analog multiplexer for
ND conversion. Discrete resistors configure the integration gain constant by connecting the SSI32H6521 SERIN
and SREF pins to the SSI 32P4901 SEROUT and SERREF pins respectively.
The SSI 32H6520 read channel interface is identical to the SSI 32H6521. The SSI 32H4633 includes a
programmable gain differential amplifier and peak detector which offers a similar interface as that of the
SSI 32H6521.
32P4901 PR4ML Read Channel
SERREF
SREF
SEROUT
SERIN
32H652i Servo Demod Controller
FIGURE 7: Area Detector Example
13-91
II
Servo Controllers and
Motor Drivers
SERVO DEMODULA'TORS (continued)
Matching Signal Levels and Conversion Ranges
The electrical interface between the read channel and the servo controller consists of reference offsets, burst
signal levels, and AID conversion ranges. In each application, the reference and signal level ofthe servo burst must
be matched to the servo controller AID converter. There is considerable variety in Silicon Systems read channel
servo interfaces and this section provides design details forthe three representative examples outlined inthe prior
section.
The 32P4746/SSI 32H6521 Interface
The32P4746/SS132H6521 servo interface is illustrated in figure 5. With VREF supplied by the SSI32H6521 being
2.25V, the voltage on the A-B and CoD pins will be 2.25V when the differences are zero. The servo AGC level is
programmable in the SSI32P4746 and may be set as low as O.75V. This lower value is preferred because the
signal swing levels will be closer to the range acceptable by the AID converter. Figure 8 illustrates the burst signal
level swing compared to AID conversion range. Note that the differencing pins (A-B and CoD) are internally
amplified by 2 prior to summing with SREF while the summing pin (MB) is unity gain.
In this example with the servo level set for O.75V, the differencing signal swing exceeds the conversion range of
the AID converter while the zero references are identical. The differencing swing will range from 0.75 up to 3.75V
absolute or ± 1.5V relative to VREF. The summing Signal at the A+B pin will be O.75V relative to VREF. The
AID conversion range of the SSI 32H6521 is ±1.125V relative to VREF.
For the differencing channels A-B and CoD, the effect of exceeding the. AID conversion range is not important.
While on track, the difference should be fairly small and well within the AID conversion range. The AID conversion
range is 75% that of the potential signal swing and sufficiently covers the linear range available from two bursts.
When the difference is large, by design the alternate burst pair should be used since A and B are laid down in
quadrature with C and D. Negative conversion values will be read when A<:BorC=B or C>=D.
The summing channel A+B voltage is always positive relative to VREF. At track center, one-half of the peak A
detector and one-half the peakB detector should sum up to approximately O.75Von the A+B pin. This value is
well within the AID converter range. The sum A+B is used to normalize the difference A-B to yield.a fractional
tracking error. The peak detectorwindowtiming should be "commutated" so that the bursts to track on are captured
in the A and B detectors.
Burst
+1.5
1t+H1+I+1+tt1+ --- - '+1 .125
AID
VREF -
lH-I,I+l+H#I+--- -',,1 .125
-1.5
-
FIGURE 8: Truncated SSI 32P4746/SSI 32H6521 Range.
13-92
Servo Controllers and
Motor Drivers
The 32P47421SSI 32H6830 Interface
The 32P4742/SSI 32H6830 servo interface is illustrated in figure 6. With the SSI 32H6830 VBGAP supplied
externally (such as from a SSI32H6810A) of 2.25V, the AID zero reference will be 5/9ths VBGAP or 1.25V. The
SSI 32P4742 internally generates a maximum reference MAXREF which is approximately 3V and corresponds
to slightly greater than the greatest burst peak amplitude possible (available on the A,B,C, or D pins). The four
bursts are internally referenced to a base line which is approximately 0.5V and is derived from MAXR EF. The servo
AGC level is adjustable but in this case, selection of 1V is assumed since there is no advantage in a smaller Signal.
With the 1V servo level, the signals at the burst pins A,B,C, and D will vary between 0.5 and 2.75V approximately.
Note that each burst pin from theSSI32P4742 is amplified internally by 2.25.
This interface requires both signal level scaling and reference matching. The SSI32H683.0 offers an interface well
suited to this task. The burst signals are applied to an analog multiplexer which feeds the differential amplifier
through a common resistor thereby minimizing offsets. Level scaling is achieved by selecting the gain determining
resistor ratio R2/R1 and reference matching through the divider made up of R3 and R4.
Figure 9 illustrates the signal levels involved in this SSI 32P4742/SSI 32P6830 interface. Assuming the burst
signals range from zero to 3V provides some saturation margin. The AID conversion range is 2V peak-to-peak.
The necessary signal level scaling will therefore map 3V to 2V and will be a gain of 2/3.. As an example, choosing
R1 of 30K and R2 of 20 kQ provides such a gain.
The reference divider is chosen by selecting a nominal or on-track burst amplitude. In this example, 1.5V (onehalf the assumed swing) was selected. By these design choices, when the bursts are 1.5V then the AID conversion
should indicate a value of O. With this choice, the voltage drop across R3 will be 1.5V and R4 will be 0.25V.
Choosing a divider current compatible with the MAXREF source such as 100 microamps, yields resistances of
15 kQ for R3 and 2500ns for R4.
The differential amplifier in the SSI 32H6830 will invert the sense of the burst signal. With the values chosen in
this design example, bursts yielding 1.5V on the output pins will yield a conversion value of zero. A missing burst
of zero amplitude will yield a maximum positive conversion value (by design it will not be saturated) and a peak
burst will yield a minimum negative conversion value (again not saturated by the design choices).
The assignment of nominal or on-track burst amplitude is not critical. This nominal amplitude will translate to the
zero value read from the AID converter. In practice, this nominal on-track value will vary and therefore, the track
following algorithm must difference the bursts to derive a purely relative measurement without relying on
absolutes. The best nominal value will be close to the center of burst variation to maximize the dynamic range
available in the AID converter.
Burst Range
3.0
. .1
2.25
1.5
o
AID
11.25 V
1--..LL.U.L.L.I.LI.L.I.U..I..Io.&:-;""- -
0.25
FIGURE 9: Shifted and Scaled SSI 32P4742/SS1 32H6830 Range
13-93
Servo Controllers and
Motor Drivers
SERVO DEMODULATORS (continued)
The 32P4901/SS1 32H6521 Interface
The 32P4901/SS132H6521 servo interface is illustrated in figure 7. The interface between read channel and servo
controller is particularly simple in this interface. A single signal SEROUT is generated by the SSI32P4901 which
is the full-wave rectified version of the bursts. The SEROUT signal is referenced to the voltage on the SERREF
pin which is in turn generated internally within the SSI 32P4901. The offset betweenSEROUT and SERREF is
never negative and will be no more than 50 mY.
SERREF is approximately 2V. TheAGC section drives the differential voltage across the DP/DN pins to 1.27V
peak-to~peak. The relative output voltage at SEROUTwill be the product ofthe full-wave rectifier gain and the burst
signal peak-to-peak amplitude. In the 32P4901 , the full-wave rectifier gain is typically 0.75 so that the peak voltage
from the rectifier will reach approximately 1V.
Setting the Area IntegrationGaln
The SSI 32H6520 and SSI 32H6521 implement area integrators. An external resistor connecting the 32P4901
SEROUT pin to the SSI32H6521 SERIN pin configures the gain constant ofthe integrator. Calibratioiris provided
to tweak the gain constant by programming the gain of the input differential amplifier. Figure 10 illustrates the area
integrator arrangement.
Yin
Vburst
i
I
c
FIGURE 10: Area Integratorwlfh Calibration Feature
Note that in this integrator, the ratiO of R1 and R2 is the means to tweak the gain. Further, the gain is adjusted by
the ratio of R1 and R2 as indicated in the transfer function relating integrator output to SERIN pin input below:
RINT is the resistance which externally sets the integrator gain constant. R1 and R2 are intemal and their respective
ratio is programmable through the GAIN bits in register 1. The GAIN bits provide for gain adjustment of -2.8 to +3.2
dB which is sufficient to account fot variation in the internal oapaoitor C1NT and R1NT.The tolerance of C1NT is 20%
and the programmable gain offers adjustment of at least 28% so that a 5% tolerance RINT resistor is acceptable.
13-94
Servo Controllers and
Motor Drivers
The area integrators are internally level shifted such that zero input will yield an integral voltage of approximately
1.5V. The output of the integrator is sampled with an AID converter with a zero reference of nominally 2.25V and
an AID conversion range of ± 1.125V. This implies that the peak integrator output should not exceed 1.875V as
illustrated in figure 11. To allow for some margin, limit the peak integrator value to 1.5V.
Integrator
.... 3.375
t
+
1.875
2.25
AID
1.5
1.25
FIGURE 11: SSI 32P4901/SS1 32H6521 Range Shifting
As a design example, consider a maximum rectified burst amplitude output of 1Vat SEROUT relative to SERREF
from the 32P4901 which is VSERIN below. The integration window is to be one microsecond and the peak integrated
burst VBURST is 1.5V. Choose RINT from the formula:
R
-
TNT -
VSERTN
VBURSf
•
Tw
CTNT
where Tw is the window width. In this example, RINT is found to be approximately 66 kQ.
Demodulator Offset Calibration
Demodulator offset calibration is a procedure which determines the servo burst Signal base line. For all three read
channeVservo controller interface examples given in this applications note, this calibration is implemented by
placing the read channel into a specific mode which inturn forces the burst signal to a known voltage. For example,
the SELSREF pin in conjunction with SG high forces SEROUT to the reference in the 32P4901. Having fixed the
burst Signal, an AID conversion is performed and the corresponding value read indicates the base line or zero
signal level. Each burst will require a base line measurement. This calibration may account for offsets.in the read
channel, servo controller analog multiplexer offset, and servo controller integrator offset. Any offset in the AID
converter itself is calibrated out separately as detailed in a later section.
A second calibration may be performed with the SSI 32H6521. Adjustment of the integrator gain constant as
detailed in a prior section is implemented by adjusting the GAIN bits in register 1. After establishing the base line,
the servo system may tweak the gain so that the peak burst amplitude is adjusted to some design target value such
as 1.5V (relative to the base line).
13-95
II
Servo Controllers and
Motor Drivers
SERVO CONTROLLERS (continued)
ANALOG TO DIGITAL CONVERSION
The servo controller provides NO conversion necessary in a digital servo system for a hard disk drive. The NO
converter captures the demodulated servo position signals as discussed in detail in the prior section. In addition,
the NO may be used to capture samples of positioner motor current and other application specific signals.
Silicon Systems servo controllers all offer extensive and flexible NO conversion resources. NO conversion
consists of source selection through an analog multiplexer, an NO converter, and register interface. The Silicon
Systems servo controllers listed below all offer NO conversion:
DEVICE
RESOLUTION
SOURCES
COMMENT
SS132H4633
8-bit
16
1 external input
SSI32H6520
10-bit
8
4 external inputs
SS132H6521
10-bit
8
4 external inputs
SSI32H6830
10-bit
6
all external inputs
Analog Multiplexer
The analog multiplexer is register accessible and bits in the register are decoded to determine the source which
will be routed to the NO converter. The lists below illustrate the diversity in multiplexer sources:
SSI32H4633
SSI32H6520/21
SSI32H6830
BURSTs 1. .4
BURST 1. .4
IN 2 .. 5 bursts
PES 2 .. 0
AOCIN 1.. .4
IN 0 .. 1 external
N andQ
VREF
ERR and SOUT
SENSE
AOCIN
VREF
SUM 1 and 2
The SSI 32H4633 includes sources from the embedded servo peak detector for BURST, analog differenced
signals for bursts pairs in PES 1 and 2, analog summed signals at SUM 1 and 2, dedicated servo demodulator
signals PES 0 and N/Q, VCM power amplifier signals ERR and SOUT, spindle motor sense current at SENSE,
an external NO input at AOCIN, and a calibration input of VREF. The SSI 32H6520 and SSI 32H6521 provide
selection of the four integrator BURST Signals, four external NO inputs at AOCIN 1. .4, and VREF for calibration.
The SSI 32H6830 divides source inputs into a group of four in IN 2 ..5 intended for burst peak capture including
a differential amplifier, and two in IN 0 .. 1 for external use.
13-96
Servo Controllers and
Motor Drivers
ADC Conversion
Starting a Conversion
AID conversion is started in the various Silicon Systems servo controllers in different ways. Two methods of
starting a conversion are possible; hardware conversion relies upon a digital timing signal which initiates the
AID conversion generated from the digital timing ASIC. Programmed conversion occurs when the microcontroller
reads or writes a registerto initiate the next AID conversion. The table below lists how each Silicon Systems servo
controller initiates AID conversion:
DEVICE
HARDWARE TRIGGERED
PROGRAM INITIATED
SSI32H4633
none
Write MUX register
SSI32H6520
ADCSTR
Read MSB 01 AID
SSI32H6521
ADCSTR
Read MSB of AID
SSI32H6830
START
none
In the SSI 32H4633, conversions are initiated after writing register 3 with the analog multiplexer selection code.
The conversion will be complete and available in six microseconds.
The SSI32H6520 and SSI32H6521 offer two methods of starting a conversion. The ADCSTR pin is a hardware
trigger which when raised high begins the first AID conversion. This feature is intended to implement a pipe lined
conversion scheme such that the first burst is converted automatically by hardware, once the first conversion is
complete the microcontroller is notified, and the microcontroller completes the conversion of the remaining bursts
by reading the AID MSB register. Figure 12 illustrates this pipelining feature of the SSI 32H6520/21. Since the
AID value is 10 bits wide in the SS132H6520/21 , two 8-bit register reads are required. When all ten bits are desired,
read the LSB first followed by the MSB to begin the next conversion. If only eight bits of resolution are needed,
the LSB may be ignored.
The SSI 32H6830 implements totally automatic conversion of all six input sources. This conversion is triggered
by the rising edge of the START Signal. The converted values are all available in their corresponding registers
which are accessible to the DSP program.
1sl Mux Settling
,
ADCSTR
'
---lJrl-----------------------------------D
ignore
B
C
,: A
AID
Conversion
Time
Burst
Time
: I
)
I I
I
r-,-"":',
C
,'-
,,'
A
B
(' C
D
--~----~--~~--~-----------------------
AID done
Status
_ _
n
n
n
-----' , _ _--' ,_---' ,_ _n
I L-
FIGURE 12: AID Conversion Pipelining in SSI32H6521
13-97
I
Servo Controllers and
Motor Drivers
ANALOG TO DIGITAL CONVERSION (continued)
Conversion Time
AID conversion time is specified for each servo controller. Total conversion time consists of delay through the
muHiplexer, actual AID conversion time, and in some cases an access latency. In some devices, there is an
additional digital latency time which is due to internal clocking. This latency will vary from 0 to 21lS. The table below
provides conversion timing for the various servo controllers discussed in this note:
DEVICE
MULTIPLEXER
SS132H4633
included
SSI32H6520
SSI32H6521
SSI32H6830
LATENCY
TOTAL
(max)
4.0 JlS
2.0 JlS
6.0 JlS(max}
1JlS
2.5 JlS
0
3.5/2.5 JlS Note 1
1JlS
2.5 JlS
0
3.5 JlS
Note 1
included
2.0 JlS
12 JlS
12 JlS
Note 2
CONVERSION
Note 2
lFor the SSI 32H6520/21, the multiplexer time can be pipelined and therefore will apply only to the very first
conversion. Each successive conversion requires only 2.5 J.1S.
2The SSI 32H6830 automatically converts all six sources and stores the results in separate registers. Each
conversion (including multiplexer delay) is 2 J.1S so that the total latency indicated above is really the time from
START assertion to the DSP running.
ADC Offset Calibration
ADC offset calibration is implemented by forcing a known voltage into the AID converter. This forcing voltage is
the reference voltage the AID converter uses internally such as VREF. In the SSI 32H4633, this VREF source is
selectable in the MUX register. For the SSI 32H6520/21 devices, a separate bit named ADC CALIB in the ADC
MSB data register overrides all other MUX selections. ADC offset calibration should be performed first and
represents the electrical offset error of the AID and multiplexer block. Later measurements may compensate for
this electrical offset by subtracting this offset value in firmware.
DIGITAL TO ANALOG CONVERSION
Many Silicon Systems servo devices include D/A converters. Some of these devices are servo controllers while
others are servo motor predrivers and drivers. The table below identifies those devices with D/A converters and
their features:
DEVICE
RESOLUTION
COMMENT
SSI32H6811
1O-bit
Dual spindle and VCM DACs
SS132H6812
1O-bit
VCM DAC
SS132H6820
8-bit
VCM DAC
SSI32H6520
10-bit
Dual DACs with separate reference
SSI32H6521
10-bit
Dual DACs with separate reference
SSI32H4633
8-bit
VCM DAC
SSI32H6830
1O-bit
Dual DACs with separate reference
13-98
Servo Controllers and
Motor Drivers
D/A conversion time may consist of two parts in some devices. D/A conversion time refers to the time taken by
the D/A converter to settle within some specified percentage of the final value. In some devices, there is an
additional digilallatency time which is due to intemal clocking. This latency will vary from 0 to 2~S. The table below
indicates the D/A conversion times for these devices:
DEVICE
LATENCY
CONVERSION
TOTAL
SSI32H6811
4.0~
4.0~
SSI32H6812
4.0~
4.0~
SSI32H6820
4.0~
4.0~
SSI32H6520
2.5~
2.5~
SSI32H6521
2.5~
2.5~
SSI32H4633
4.0~
SSI32H6830
4.0~
2.0~
6.0~
4.0~
Strobe Mode
The SSI 32H6520 and SSI 32H6521 offer D/A strobe modes which allow the two D/A outputs to change
simultaneously. Strobe mode is selected by manipulating the STBEN1 and STBEN2 bits in register 2. The idea
of strobe mode is to allow time for the microcontrolier to compute and update the DIA registers and then with a
single register write, simultaneously direct both D/As to assume their new values. Figure 13 illustrates how the
strobe bits may be used in an application seeking to change the D/A voltages synchronously.
--.
Compute error 1
value and write
to DAC1
~
Compute error 2
value and write
to DAC2
~
Update both DIAs
by setting and
clearing STBENs
~
FIGURE 13: Using STBEN to Synchronously Update Both D/As
Switched Capacitor DI As
Some Silicon Systems servo controllers implement switched capacitor D/As instead of static ladder D/As.
Switched capacitor D/As must be updated at a minimum frequency or else they will drift from the programmed
value. For all Silicon Systems capacitor D/As, an update frequency 01 at least ten Hz will insure insignificant drift
effects. The following servo controllers implement capacitor D/As:
SSI32H6811
SSI32H6812
SSI32H6820
SSI32H6520
SSI32H6521
SSI32H6830
13-99
I
Servo Controllers and
Motor Drivers
SERVO CONTROLLERS (continued)
DIGITAL INTERFACE
The digital interface between the microcontroller and the servo controller varies considerably between individual
device types. Some devices are parallel bus oriented with address, data, and control lines. Other devices rely upon
a high speed synchronous serial link with an address/data protocol. The SSI 32H6830 is a DSP with internal
ND and D/A resources which appear as internal registers. The table below identifies the interface type for each
servo controller:
DEVICE
INTERFACE
COMMENT
SS132H6811
Serial
SSI32H6812
Serial
6-bit header, 10-bit data
SSI32H6820
Serial
8-bit header, 8-bit data
SSI32H6520
Parallel
8-bit Intel/Motorola flP
SSI32H6521
Parallel
8-bit TMS 32C025
SSI32H4633
Parallel
8-bit Intel/Motorola flP
SS132H6830
Register
Internal register file
6-bit header, 1O-bit data
Data Format
Data format primarily deals with the .orientation of the bits within words transferred between the ND and D/A
converters. For all of the Silicon Systems servo devices, the data format is such that all values are left justified.
Left justification implies thallhe most significant bit is on the left while the least significant bit is on the right. Figure
14 illustrates how both 8 and 10-bit values compatible with Silicon Systems D/A and ND converters are to be
formatted.
in the serial links, the data portion of the serial packet matches the D/A and ND bit width. For the parallel bus
interfaces, the bus width is only eight bits wide. For 1 O-bit wide values, the upper eight bits are accessible in the
MSB data register and the least two bits are accessible in the LSB data register. In the SSI32H6520, the LSB data
register is on an even address and the MSB data register is one ascending address higher. In this arrangement,
the 1O-bit value may be accessed as· either two successive 8-bit values or one i6-bit word following the INTEL
80C196 convention.
8 Bit Byte
MSB
17
0
ILSB
10 Bit Word
MSB 19
ignored
2
I 11 0
xx
xxxx
LSB
FIGURE 14: Data Format for Left Justified 8 and 10 Bit Values
13-100
Servo Controllers and
Motor Drivers
Microcontroller Interfaces
The microcontroller interfaces supported by the SSI32H6520 and SSI32H4633 are both Intel80C196 and Motorola
68HC11 compatible. The interface is a parallel bus consisting of 8 data lines multiplexed with three or four address
lines depending upon the device. A separate control line identified as ALE decodes the register address from
register data. Figure 15 illustrates the INTEL interface supported by the SSI 32H6520 and SSI 32H4633.
AD7 .. 0
AD7 .. 0
ALE
ALE
RD
RD
WR
WR
A8 .. 15
Decode
I
32H6520,
32H4633
CS
I
INT
INT
FIGURE 15: Intel Compatible Parallel Bus
DSP Interfaces
Two Silicon Systems servo controllers offer high speed bus interfaces. A high speed interface differs from the
microcontrolier interface due to transfer speed and demultiplexed implementation. The SSI32H6520 provides an
approximate DSP interface by breaking register transfers down into two successive cycles; the first cycle latches
register address, the second cycle transfers register data. The SSI 32H6521 implements directly an 8-bit bus
which is directly compatible with a TMS32C025. Figure 16 illustrates the DSP interface between the 32C025 and
the SSI 32H6521.
07 .. 0
07 .. 0
A2 .. 0
ADR2 .. 0
and CS options
STRB
STRB
R/W
R/W
__________________
~
INT
FIGURE 16: TMS 32025 Compatible Bus
13-101
32H6521
I
Servo Controllers and
Motor Drivers
DIGITAL INTERFACE (continued)
Interrupts and Status Registers
Extensive interrupt and status information is available in the different Silicon Systems servo controllers. Interrupts
can be selectively enabled to notify the microcontrol/erof an event such as conversion completion. Status registers
reflect interrupt assertion and can be polled by the microcontrol/er as an alternative to using interrupts. The
following controllers offer these features:
DEVICE
INTERRUPT
STATUS
SSI32H6520
INT
Burst and ADC complete
SSI32H6521
INT
Burst and ADC complete
SSI32H4633
INT
Extensive MSC and VCM
SS132H6830
INT
Extensive user definable
Using Interrupts and Status with the SSI 32H6520/21
The SSI 32H6520 and SSI 32H6521 implement two bits which reflect status for both NO conversion and burst
integration completion. Register 0 is the status register with bit 0 being BURST INT and bit 1 being AOC INT
complete. For the SSI 32H6520, register 0 also serves as an interrupt mask which when written can selectively
enable INT pin assertion.
Figure 17 shows a timing example of how the status and interrupt pin work together in a typical application. The
INT pin assertion occurs when either enabled status bit becomes true. Any asserted interrupt event is cleared when
the microcontroller reads register O. If interrupts are not used, register 0 may be polled for completion status.
INT
,,
I
I
I,
I
I,,
I
i Interrupt
,
I
I
Status Bit
I
I
NO Complete
: Latency
._L
I
I
I
I
I
I
I
L
L_.IlP Read Status
FIGURE 17: Interrupt Cycle in SSt 32H6520/21
Interrupts and Status in the SSI 32H6830
Status in the SSI 32H6830 consists of DSP execution and user definable flags. DSP execution flags indicate to
the microcontroller when the OSP is busy or available for access. User definable flags provide a means of
communication between the microcontroller and the DSP indicating application specific events such as on-track,
seek-complete, and spindle lock. The status of the SSI32H6830 is enhanced with flags which indicate when states
change. The SSI 32H6830 can assert an interrupt to the microcontroller through the status register. Status flags
and interrupts are cleared by the microcontroller when the status register FSTATUS is read.
13-102
Servo Controllers and
Motor Drivers
The 551 32H4633 Status and Interrupt System
The SSI 32H4633 interrupt system is quite extensive. This device offers status and interrupt enabling masks for
events from the servo and spindle sections including commutation, speed lock, embedded servo burst capture
complete, dedicated servo track crossing, and seek terminal track count. Interrupt status is read from register 0
and MSC interrupts are cleared by reading the spindle status register 1 while servo interrupts are cleared by
reading servo status register 2.
VCM MOTOR CURRENT
Sampling VCM motor current is useful for two reasons. First, electrical calibration of the D/A and VCM
transconductance power amplifier can be performed. Second, motor current can be used by an observer to
estimate head velocity in track and seek algorithms.
SOUT and Offset
In Silicon Systems VCM drivers, motor current is measured by a differential amplifier amplifying the voltage
developed across a sense resistor. The sense resistor is placed in series with the VCM motor itself and typically
has a very small value such as a few tenths of an Q. The sense amplifier has a fixed voltage gain typically of 4
and the output appears at the SOUT pin. The voltage at SOUT is fed back to the error summing amplifier to close
the loop and set the VCM power amplifier gain (detailed in later sections).
Accurate measurement of VCM motor current is essential and requires minimum sense amplifier offset. The sense
amplifiers implemented in Silicon Systems servo drivers are either continuous time in bipolar devices or switched
capacitor in CMOS devices. The sense amplifier characteristics for the VCM drivers and predrivers are listed
below:
DEVICE
SENSE INPUT
OFFSET MAX
SENSE
GAIN
COMMENT
SSI32H569
2mV
4
SSI32H4633
3mV
4
switched cap
SSI32H6230
2mV
4
continuous time
SSI32H6231
2mV
4
continuous time
SSI32H6240
2mV
2
continuous time
SSI32H6510
3mV
4
switched cap
SSI32H6810A
3mV
4
switched cap
SSI32H6811
3mV
4
switched cap
SSI32H6812
3mV
4
switched cap
SSI32H6820
3mV
4
switched cap
SS132H6825
2mV
4
continuous time
continuous time
Sense Amplifier Gain Variation
In the bipolar predrivers including the SSI 32H569, SSI 32H6230/31, and SSI32H6240 there is a common mode
voltage sensitivity which will result in sense amplifier gain variation. The data sheets specify the sense amplifier
gain to be within ±2.5%; however, this measurement is performed only at a specific common mode voltage such
as 6V. As the common mode voltage swings from near zero up towards the 12V supply, the sense gain will vary.
13-103
I
Servo Controllers and
Motor Drivers
VCM MOTOR CURRENT (continued)
Sense Amplifier Gain Variation (continued)
The voltage sensitivity is due to the input resistors making up the sense differential amplifier having a voltage
coefficient. The sense gain variation can be viewed in two ways. First, sense gain tolerance will be ± 2.5% about
a transfer function which accounts for the voltage coefficient. A second view lumps voltage coefficient and
tolerance together for a composite uncertainty of ± 5%. In the SSI 32H569, the composite uncertainty would
become 3.8 to 4.2 VIV as compared to 3.9 to 4.1 VIV.
Using Uncommitted Op-Amps
A few Silicon Systems servo controliers offer an uncommitted op-amp. This can be useful in translating or amplifying
motor current for greater NO conversion resolution. The following devices offer such an uncommitted op-amp:
DEVICE
COMMENT
SSI32H6231
Independent op-amp A3
SSI32H6825
Independent op-amp A3
SSI32H6520
Op-amp with output connected as ADCIN1
SSI32H6521
Op-amp with output connected as ADCIN1
SS132H6830
Op-amp with output connected as INS
The uncommitted op-amps in the SSI 32H6231 and SSI 32H6825 are general purpose op-amps with minimum
unity gain bandwidth products of 150 KHz, 60 dB gain, and low input offset of ± 2 mY. The op-amps in the SSI
32H6520, SSI 32H6521, and SSI 32H6830 are better suited to amplification of SOUT since they offer higher
minimum unity gain bandwidth of at least 1 MHz.
Figure 18 illustrates an application using AS in the SSI 32H6830 to amplify SOUTfrom an SS132H6810A VCM
driver. In this example, the VCM peak current is assumed to be 0.5 amp and the sense resistor is 0.10. The peak
voltage relative to VREF from the SOUT pin will be computed as:
VSOUT =
4 • Rs • 1M
so that
VSOUT =
4 • 0.1 • 0.5
Using these example parameters, the peak SOUT voltage will be 200 mY. The AID conversion range will be 1V
peak and therefore, an amplification of four is suggested (leave some conversion margin to avoid saturation).
SOUT
__-+______-r+-,IN5P
VREF
VB GAP 1---.1'---.1..--1 VBG
32H6830
32H6810A
FIGURE 18: Using the Uncommitted Op-Amp to Sense 1m
13-104
Servo Controllers and
Motor Drivers
VCM Current Offset Calibration
VCM current offset calibration should usually be performed at power up. The intent of this calibration is to
determine what value written to the D/A really corresponds to zero VCM motor current. The offset in the D/A is
usually small such as ± 15 mY. Offsets in the VCM error summing amplifier may be tens of millivolts. The sense
amplifier will also have an offset as listed earlier. Voltage offsets will translate into VCM current offsets. The
accumulative offset can be canceled so that values written to the OfA converter are not biased.
When working to cancel output offset, some point in the measurement chain must be considered accurate. The
low offset in Silicon Systems sense amplifiers suggest that the value appearing at SOUT is a good starting point.
A calibration routine would program the VCM OfA to near zero current and then measure SOUTthrough an AID
conversion. A Simple routine begins below zero and sequentially ascends higher while sampling at each point. The
point where SOUT is closest to zero (of course this assumes the NO converter offset is already calibrated out)
will be the correction value to use when writing the DfA. This correction value should be subtracted from all values
written to the OfA converter. If an amplifier is placed between SOUT and the NO, the offset in this amplifier will
degrade the measurement slightly.
Sense Amplifier SVSCLK Dependence
The switched capaCitor sense amplifiers rely upon a system clock for timing. Sometimes, it is necessary to supply
the device with a SVSCLK frequency which is not that specified in the data sheet. For example, the SSI 32H681 OA
specifies a nominal clock frequency of 2 MHz and a range of 1.5 to 2.5 MHz. SVSCLK in this device affects the
sense amplifier, charge pump, OfA, and the adaptive commutation logiC in the MSC block. The SS132H6811 data
sheet specifies 8 MHz with a tolerance of only ±O.1 %. This particular specification is actually misleading because
this device likewise can be shifted in frequency over a considerable range (9 MHz is acceptable).
When SYSCLK is shifted from the data sheet value, the device behavior changes. Shifting higher in frequency is
better than shifting down. When shifting higher in frequency, the sample rate for SYSCLK dependent circuits
likewise is shifted higher. In general, the following effects will be noticed:
FUNCTION
SHIFT LOWER
SHIFT HIGHER
Adaptive
commutation range
RPM range
lower
RPM range
higher
VCM Bandwidth
Reduced
Increased
VCM Slew Rate
Reduced
Increased
DAC settling time
Increased
Reduced
In general, shifts of ± 15% will be insignificant. Larger shifts in frequency should be verified with Silicon Systems.
13-105
II
Servo Controllers and
Motor Drivers
SERVO DRIVERS
Servo drivers are actually a mix of VCM predriversand integrated power drivers. The drivers can be characterized
as either being a predriver or driver, and being 12 or 5V compatible. Beyond these characteristics, the basic
topology of all Silicon Systems servo drivers are essentially the same.
5 AND 12V APPLICATIONS
Silicon Systems 5V and 12V servo applications tend to also divide down into integrated power and predrivers. In
fact, all12V servo drivers are predrivers and all5V devices include integrated power drivers. The 12V applications
will tend to be aimed at high capacity, high performance designs fitting into 3.5" and some 2.5" form factors. The
5V devices are applicable to 2.5" and smaller form factors.
PREDRIVER VERSUS INTEGRATED POWER
The predriver differs from the integrated power driver because the predriver requires extemal power MOSFETs.
Figure 19 illustrates an interconnection between a predriver, external MOSFETs, and VCM motor. Figure 20
illustrates the direct connection made between an integrated power driver and the VCM motor.
The predriver relies on an external H bridge arrangement which consists of pairs of P and N channel MOSFETs.
The upper driver is a P channel while the lower is an N channel MOSFET. Four interconnections between the
predriver and MOSFETs are required to control the gates. In addition, three interconnections are required to close
the legs of the H bridge locally and to differentially sense VCM motor current.
The integrated power driver connects directly to the VCM motor through a single sense resistor. Two differential
interconnections are made to the sense resistor to minimize offset induced across any common PCB trace (SE1
and VM1J.
Both arrangements rely upon a single error summing amplifier which accepts a VCM command voltage. Feed back
is arranged to implement a transconductance gain stage which forces current through the VCM motor in response
to the input command voltage. Figure 21 illustrates the basic small signal topology of the Silicon Systems' VCM
servo drivers.
+12V
SE2
Blocking diode
C
SE1
OUTA
OUTB
oum
OUTC
SE3
FIGURE 19: Predriver Connection to External MOSFETs
13-106
Servo Controllers and
Motor Drivers
SE2
SE1
'-..
,/
Rs
VM1
0--
>
VCM
,--
-
VM2
FIGURE 20: Integrated Power Driver VCM Connection
Vin
Vref
VCM
FIGURE 21: Basic Small Signal Topology of Driver
13-107
I
Servo Controllers and
Motor Drivers
SERVO DRIVERS (continued)
VCM POWER AMPLIFIER
The VCM power amplifier may be implemented with either the Silicon Systems predriveror integrated power driver
devices. This section discusses how to design VCM power amplifiers.
Transconductance Gain
The DC transconductance gain is determined by the simple equation:
GDC = _1_ •
R/N
..!!L
AsRs
where GDC is the DC transconductance gain in amps per volt, RIN is the input resistor, RF is the feed back resistor
from SOUT, Av is the sense gain, and Rs is the current sense resistor.
Sense Resistor Characteristics
The sense resistor Rs should be chosen to be as small as possible to minimize loss. A lower limit to the value of
this sense resistor is typically 0.10 and is based on signal to noise ratio. A non-inductive sense resistor is best
and the power rating should be sufficient to avoid significant thermal shift in value. For peak currents of 500 rnA
and 0.50s, an one-half watt rating should be sufficient.
Bandwidth
In the recommended VCM amplifiertopology, a single RC network is used to both compensate the power amplifier
and set the bandwidth. The following analysis provides the reasoning behind this design approach.
Figure 21 is the basic small signal driver topology. If the BEMF voltage generated when the motor is moving can
be neglected, the circuit analysis is greatly simplified. Under these assumptions, the VCM is modeled simply as
a series resistor Rm and inductor Lm.
The design objective is to determine values for the compensating components RL and CL. Determination of the
compensation components requires an analysis of the circuit transfer function. A straight forward approach of
analysis is summing the currents in the virtual ground node of the error summing amplifier.
Assuming the current entering the virtual ground node due to VIN is ';n:
and the currents entering the node from compensation and current feedback are I[ and 'F:
IF
At the virtual ground:
13-108
Servo Controllers and
Motor Drivers
v0 is the voltage across the sum of the VCM load and sense resistor. The voltage at the ERR pin determines the
current through the compensation network. The input referred voltage on ERR will be V0 divided by Av.
The voltage on SOUT is the As amplified voltage developed across the sense resistor Rs due to the current 1M. The
sense of polarity between VIN and the VCM voltage V0 is non-inverting. In the physical implementation, the VCM
voltage is differential and V0 corresponds to the voltage at either the VM 1 pin or AlB driver pair.
Rearranging the summation of currents yields:
Substituting for V0 and rearranging for the required transfer function through algebraic gymnastics yields:
1M
1
VlN =- RlN • AVAsRs( RL
RFAV( RL + YscJ
+ YsCJ+RF(Rs +RM +sLM )
Rewriting all frequency dependent factors in normalized form results in:
To compensate the electrical pole in the denominator above due to the VCM motor, choose RL and CLso that the
zero in the numerator exactly cancels the motor pole. To accomplish this cancelation, equate the two time
constants:
When the compensation is chosen so that the zero cancels the VCM motor pole exactly, the transfer function
simplifies to:
1M
1
RFAV
VlN =- RlN • AvAsRs+sRLCdRs+RM)
The compensated transfer function has only one pole and can be rewritten more clearly as:
13-109
II
Servo Controllers and
Motor Drivers
VCM POWER AMPLIFIER
(continued)
Bandwidth (continued)
The closed-loop -3d8 frequency will be:
In an application, the required bandwidth is known. CLcan be determined to meet the bandwidth specification. RL
can be found once CL is determined by making use of the relationship which equates the compensating zero and
VCM motor pole lime constants. The final component solutions are below:
CL =
AvAsRs
2n o RF(Rs +RM )oBW
RL=
LM
CdRs+RM)
Inthese equations, As is the sense amplifier gain and Ay is the differential gain from the output of the errorsumming
amplifier ERR pin to the VCM load. The sense gain for each device type was listed in a prior section, the differential
voltage gain Av is listed below:
DEVICE
SSI32H569
Av
17
SSI32H4633
29.4
SSI32H6230
17
SSI32H6231
17
SSI32H6240
17
SSI32H6510
12
SSI32H6810A
12
SSI32H6811
12
SS132H6812
12
SSI32H6820
29.4
SSI32H6825
17
13-110
Servo Controllers and
Motor Drivers
External Power Devices
Silicon Systems servo predrivers require external power devices to drive the VCM. The criteria for choosing
compatible power devices vary among the predrivers. The table below provides selection criteria:
CRITERIA
SSI32H569
EXAMPLE DEVICE
500-1000pF,Vgs>2V
SSI32H4633
IRFR020,IRFR9020
Si9952DY
SSI32H6230
500 -1000 pF, Vgs >2V
IRFR020,IRFR9020
SSI32H6231
500 -1000 pF, Vgs > 2V
IRFR020,IRFR9020
SSI32H6240
b > 40, ft > 40 MHz
BCP68,BCP69
SSI32H6825
Si9952DY
SSI32H6820
Si9952DY
The criteria for theSSI 32H569,SSI 32H6230, andSSI32H6231 are based on two factors. The gate capacitance
must be in the specified range because it contributes to the amplifier compensation. The cross-over protection
level in these predrivers is fixed at approximately 2V. The MOSFET turn-on threshold Vgs must be greater than
the protection level.
Cross Over Adjustment
In the SSI 32H4633 and SSI 32H6820, a means to adjust the cross-over protection threshold is available. The
voltage on pin VX sets the cross-over protection level directly. The pin has a default of 1.0 to 1.4V. A resistor may
be added to ground to modify the voltage on VX.
Gain Switching
Gain switching is a technique which adjusts the transconductance gain of the VCM driver to match the operating
mode. Usually there are track-following and track-seeking hard disk servo modes. The D/A converter voltage
range is fixed; therefore, the power amplifier gain can be adjusted to optimize the driver dynamic range for the
operating mode.
In Silicon Systems servo drivers, gain switching is implemented by changing the input resistance to the error
summing amplifier using an analog switch. In track-following mode, the analog switch is left open. When trackseeking, the analog switch is closed to parallel in the seek input resistorwhich in turn increases the transconductance
gain. The following devices support the gain switching feature:
DEVICE
GAIN SWITCHING CONTROL
SS132H4633
SW-ON bit in servo control register
SS132H6810A
SWONpin
SSI32H6811
SWONpin
SS132H6820
SWON bit in register 1
13-111
II
Servo Controllers and
Motor Drivers
RETRACT AND POWER FAULT
In most hard disk drives, the data heads must be moved away from useful data areas when the power fails. This
removal is referred to as head "retraction". Retract is implemented within the VCM servo driver and because of
its dependency upon power fault detection, all SSI servo drivers include a power fault detector as well. Powerfault
detection includes comparators sensing the supply voltage, band-gap precision reference, timing circuits, and
power fault control signals.
RETRACT METHODS
Head retraction in Silicon Systems servo drivers is implemented in several different ways. Fundamentally, all
methods are the same because they rely upon forcing a voltage during power failure across the VCM motor to
cause the positioner to move the data head into a landing area.
H Bridge.Retraction
Head retraction canbe implemented by unbalancing the H bridge driver so that a current will flow through the VCM.
The following devices implement this kind of retraction through external power devices of the indicated type:
DEVICE
DRIVER TYPE
SSI32H569
MOSFET
SSI32H6230
MOSFET
SSI32H6231
MOSFET
SSI32H6240
Sipolar Transistor
SS132H6825
MOSFET
H bridge retraction is accomplished by turning on the "A" and "0" drivers while turning off the "S" and "C" drivers.
For the devices implementing this retract method, the means triggering retract vary as listed below:
DEVICE
POWER SENSE
VREF
CONTROL
SSI32H569
LOWV or VCC<9V
VREF<4.3V
EN
SSI32H6230
LOWV or VCC<9V
VREF<4.3V
EN
SSI32H6231
VCC<9V
VREF<3.3V
SSI32H6240
Two comparators
SS132H6825
EN
RETRACT
VREF<3.3V
RETRACT
Velocity Limiting
The retract voltage applied across the VCM is constant and serves to limit head velocity. Head velocity is limited
because the voltage across the VCM is sensed by pins SE1 and SE3 and then compared to an internal reference.
The "A" predriveroutput is adjusted so that the feed back voltage across SE1 and SE3 equals this internal reference.
When the head moves, the back-electromotive-force (BEMF) generated across the VCM adds to the total voltage
developed across the VCM resistance. As the head gains velocity, the BEMF increases and ultimately is limited
when the BEMF voltage equals the internal reference and the applied retract current goes to zero. When the head
stops against the crash stop, the current is limited to the retract reference divided by the VCM resistance. For
example, if the VCM resistance is 160 and the reference is approximately 1V, then the current will limit to:
13-112
Servo Controllers and
Motor Drivers
[MAX
=){6
or 62 rnA
The tolerance in the intemal reference used to establish retract voltage is fairly wide. For all but the SS132H6825
this reference is specified as being 0.7 to 1.3V. The SSI 32H6825 has a tighter specification of 0.7 to 1V. There
is no way to adjust the retract voltage reference.
Finally, the retract circuit will typically work to a voltage at VCC as low as 3V. Below this point, the voltage across
the VCM will rapidly decrease.
An Alternative Retract Scheme
This group of pre drivers relies upon a blocking diode to isolate the VCM H bridge from the 12V supply during failure.
An alternative retract scheme is shown in figure 22 and offers the advantage of not requiring the VCM blocking
diode. Removal ofthe blocking diode is atthe cost of adding two additional enhancement mode retract MOSFETs,
some discrete components, and losing velocity limiting during retract.
During power fault, the predriver "A" and "D" outputs will turn on as usual. As the 12V supply drops to zero, the
retract current due to the H bridge itself will become insignificant (since there is no blocking diode isolating VCC).
However, during fault BRK will become high impedance allowing the gates of the two additional N channel
MOSFETs to move upwards to spindle BEMF voltage thereby turning on the retract MOSFETs. A resistor may
be necessary to limit current and the diode/resistor is added to insure noise immunity.
vee
A
01
pe
B
D
BRK
VBEMF
FIGURE 22. Alternative Retract Circuit
Disabling Retract
Some applications implement a mechanical retract or have other reasons to disable the automatic retract function.
For this group of predrivers, the circuit shown in figure 23 may be useful. This circuit works by turning on the NPN
transistor during power fault so that the gate voltage on the "D" gate driver cannot rise. The resistance in series
with the "D" driver gate will introduce some phase shift and so its value must be chosen carefully.
13-113
II
Servo Controllers and
Motor Drivers
OUTO
BRK
VBEMF
FIGURE 23: Disabling Retract In VCM Predrlver
RETRACT METHODS (continued)
BRK Pin pull-up
The SS132H569, SS132H6230, and SSI32H6240 all include a special BRK pin which is the collector of an NPN
transistor. When retraction occurs, this NPN transistor is turned off thereby allowing the voltage at the collector
to rise. Early data sheets indicated that this pin must be pulled high even if it is not used. This is no longer true
and this pin may be left floating.
Transistor Retraction
An alternative to H bridge retraction is to source the retract current into the VCM motor through an additional device
such as an NPN transistor. Tt)e SSI 32H6820 and SSI 32H4633 implement this kind of retraction.
One of the disadvantages of H bridge retraction discussed in the prior section is that the retract level is not
adjustable. In the SSI 32H4633 and SSI32H6820, a pin named VRETR accepts an externally applied retract
reference voltage. VRETR has a default high impedance voltage source ranging from 0.3 to O.9V which can be
externally overdriven. Figure 24 shows how transistor retraction is implemented. This circuit will typically work
down to 3V.
+12V
Blocking diode
1------.---- VBEMF and
Spindle Supply
VRETR
A
c
B
D
FIGURE 24: Transistor Retract
13-114
Servo Controllers and
Motor Drivers
No diodes are required to protect the NPN transistor from reverse emitter/base breakdown because during normal
operation, AOUTR is high impedance. If the retract level is high, the addition of a series resistor between the NPN
collector and VBEMF supply is helpful to distribute power dissipation.
Velocity limiting
The retract voltage applied across the VCM is constant and serves to limit head velocity. Head velocity is limited
because the voltage across the VCM is sensed by the SE1 pin and then compared to VRETR. The base current
of the NPN is adjusted so that the feed back voltage at SE1 equals VRETR. When the head moves, the backelectromotive-force (BEMF) generated across the VCM adds to the total voltage developed across the VCM
resistance. As the head gains velocity, the BEMF increases and ultimately is limited when the BEMF voltage
equals VRETR and the applied retract current goes to zero. When the head stops against the crash stop, the
current is limited to VRETR divided by the VCM resistance.
Typically, a resistor and diode combination is used to generate the retract reference as shown in figure 25. The
resistance is chosen to provide a small current such as a few hundred microamps and the diode serves to provide
a fairly constant reference of approximately O.7V. Other retract levels can be derived from dividers working off the
reference diode.
VBEMF
VRETR
1
~
:&:
Diode serves as
retract reference
FIGURE 25: Setting Retract Level
Integrated Retraction
All Silicon Systems integrated power servo drivers implement retraction with internally dedicated MOSFETs which
are enabled during retract. VM1 is switched to an internal MOSFET as the voltage source and VM2 is saturated
towards ground. The following integrated power drivers implement this retract method:
SSI32H6510
SS132H6810
SSI32H6811
SSI32H6812
All of these devices implement a programmable retract level. A VRETRACT pin is provided which requires an
external voltage which in turn will set the VCM retract Voltage. There is no default VRETRACT level in these
devices, an external reference must be supplied.
Velocity limiting
The retract voltage applied across the VCM is constant and serves to limit head velocity. Head velocity is limited
because the voltage across the VCM is sensed by the SE2 pin and then compared to VRETRACT. The internal
N channel retract MOSFET is controlled by the comparator thereby adjusting the voltage on the VCM through the
VM1 pin. When the head moves, the back-electromotive-force (BEMF) generated across the VCM adds to the total
voltage developed across the VCM resistance. As the head gains velocity, the BEMF increases and ultimately is
13-115
I
Servo Controllers and
Motor Drivers
RETRACT METHODS
Velocity Limiting
(continued)
(continued)
limited when the BEMF voltage equals VRETRACT and the applied retract current goes to zero. When the head
stops against the crash stop, the current is limited to VRETRACT divided by the VCM resistance.
Typically, a resistor and diode combination is used to generate the retract reference as shown in figure 25. The
resistance is chosen to provide a small current such as a few hundred microamps and the diode serves to provide
a fairly constant reference of approximately O.7V. Other retract levels can be derived from dividers working off the
reference diode.
Retract to Brake Transition
Often in hard disk designs, it is necessary to free spin the spindle motor during a retract period and then transition
into a spindle braking mode. Free spinning provides the necessary energy to power the retract circuits for a few
hundred milliseconds thereby insuring that the head is over a landing area prior to braking the motor. A means
to implement this scheme is to use a delay circuit which is triggered by power fault and upon time out, the spindle
is placed into a brake mode. Most Silicon Systems sensor-less spindle drivers provide a BRAKE pin for this
purpose and the Silicon Systems Sensor-less MSC Applications Note discusses this technique in detail.
Using Spindle BEMF Voltage for Retract
A popular method for powering the retract circuit upon power failure is to full-wave rectify the spindle motor BEMF.
For all Silicon Systems predrivers, an external "blocking" diode is required to isolate the 12V supply from the upper
P channel MOSFETs during powerfault. For Silicon Systems integrated power drivers, the MOSFETs are stacked
N channel devices and no "blocking" diode is required. The Silicon Systems Sensor-less MSC Applications Note
discusses this subject thoroughly.
POWER FAULT DETECTION
Power fault detection is implemented by the servo drivers in various ways. Many have internal fixed thresholds
while others provide comparators accepting a user supplied sample of the supply voltages. The table below lists
the types of fault detection implemented and any digital fault signals generated:
DEVICE
FAULT DETECTION METHOD
SIGNAL
SSI32H569
VCC, LOWV, and VREF qualification
BRK
SSI32H6230
VCC, LOWV, and VREF qualification
BRK
SSI32H6231
VCC
SSI32H6240
PS1 and PS2 comparators
PFAIL,BRK
SSI32H6510
VCHK comparator
SYSRST
SSI32H6810A
VCHK comparator
SYSRST
SSI32H6811
VCHK comparator
SYSRST
SSI32H6812
VCHK comparator
POR
SSI32H6820
VCHK1 and VCHK2 comparators
SYSRST
SSI32H6825
Internal reference qualification
SSI32H6520
PSV comparator
SYSRST
SSI32H6521
PSV comparator
SYSRST
SSI32H4633
VCHK1 and VCHK2 comparators
SYSRST
13-116
Servo Controllers and
Motor Drivers
Power Fault Operation
In some Silicon Systems devices, power fault consists of either retract or linear mode such as the SSI 32H569.
Other devices provide digital signals suitable for system wide reset such as the SSI 32H6810A. Figure 26
illustrates the power fault phases in devices like the SSI 32H6810A.
5V
4V
2V
ov
time
Power
Fail
Normal Operation
Power
Fail
I---....,.~--------
-----~---....
: ---I
I
I
: RCRST
I Delay
FIGURE 26: Power Fault Phases
Setting the FauH Threshold
Devices which implement a comparator for power fault detection require an external resistor divider to sample the
supply voltage. Some devices have two comparators (such as the SSI32H6240 or SS132H6820) so that both the
12 and 5V supplies may be monitored. The threshold voltage should be chosen carefully (particularly not too high
and causing false detection) and should consider the various tolerances involved including:
1. Minimum operating supply voltage
2. Tolerance in band-gap reference
3. Tolerance in resistor divider components
4. Ccmparator offset
As a design example, consider a minimum system operating voltage of 4.5V in a SS132H681 OA application. The
band-gap tolerance is± 3% and ± 1% resistors are to be used. The comparatorolfset is ± 15 mV and the nominal
band-gap reference is 2.25V.
The tolerance in the two divider resistors can be additive. Factoring in the comparator offset, compute the resistor
divider to yield 2.25V for a supply voltage 95% of 4.5V less 15 mV. In this example, this supply voltage trip point
will be 4.26V and selecting the divider to draw 100 microamps yields values:
(Vtrip Rupper =
R
which yields values of 20.1 K and 22.5
k.Q
2.25
_
lower -
2.25)
-"-1-0":"0-'-1O--6-z'100 .10-6
respectively.
13-117
I
Servo Controllers and
Motor Drivers
POWER FAULT DETECTION
(continued)
Adding HystereSIS
Hysteresis may be added to power fault detectors which rely upon a comparator and generate a SYSRST signal.
A resistor added between the SSI 32H6810A VCHK pin and SYSRST will add Hysteresis to the comparator
threshold. When power is first applied, SYSRST is asserted low thereby setting the power-up threshold. When
SYSRST is negated high, the current through the Hysteresis resistor will add to the voltage developed at VCHK
effectively lowering the power-down threshold. The Hysteresis is approximately given by the formula below:
R10wer
TT
Y
hysteresis =
Rlower
+ Rhysteresis
0
5
If Rlower is 22.5 kil, approximately 100 mVof Hysteresis is introduced with a RHysteresisof 1 MQ.
Minimum Operating Voltage
Power fault detectors require a minimum voltage for successful operation. All devices generating a SYSRST
power fault signal will correctly assert SYSRST low down to 2V.
Fault Signal Usage
The type and usage ofthe power fault signal will depend greatly upon how it is generated. Some ofthe fault signals
are conditioned and compatible with microcontrollers for system wide reset while others aren't.
PFAIL and BRK
PFAIL and BRK are the collectors of NPN transistors. An external pull-up resistor is required and this pull-up is
typically connected to VBEMF (the rectified spindle BEMF voltage). Typically, the minimum resistance will be
10 kQ and use of these signals will be limited to analog circuits including switching external MOSFETs during
retract. No Silicon Systems spindle drivers can accept this BRK signal to initiate braking. In the 5S1 32H6240,
PFAIL is available which separately reflects the power fault state while BRK also responds to the RETRACT pin.
The SYSRST Pin
SYSRST is designed to be suitable for system wide reset. In all devices supporting this fault signal, an external
RC network provides conditioning which can assure minimum assertion time. Figure 27 illustrates the typical circuit
found in the SSI32H681 OA. The following is a design example which will condition the SYSRST assertion so that
it has a minimum pulse width of approximately 10 ~S.
The RCRST threshold varies from 0.8 to 2V in the SSI 32H6820. The resistor will charge the capacitor towards
5V. The voltage on RCRSTwill follow the basic relationship:
Vmst =
5(1- eYre)
so that solving for the relationship between delay time "t" and RC when the threshold is chosen to be 0.8 yields:
RC=
-1
1n( 5 - ;crst )
or approximately:
RC = 5.7 0
With R of 47 kQ, C is found to be approximately 1 ~Fd.
13-118
(
Servo Controllers and
Motor Drivers
-r-----v'''--.-----.
RESET
VCHK
--1---1
VBGAP
-If----...l--j
PSALTI_I-_ _ _ _~======~
FIGURE 27. Power Fault Detector
POR
In the SS132H6812, the device pin count has been greatly minimized. The POR pin itself shares the job of signaling
power fault and conditioning. This signal will usually not be directly compatible with the microcontroller due to the
slow rise time (when capacitance is added) and requires intermediate buffering. Routing POR through some form
of non- inverting TTL buffer will do the job.
Capacitance may be added to POR. The threshold is approximately 400 mV so an approximate RC time constant
for a desired "t" can be computed from:
RC=12·t
SLEEP MODES
Sleep modes provide a means to reduce power consumption when functions such as servo are not needed. The
table below lists how each Silicon Systems servo device supports sleep modes:
DEVICE
SLEEP MODE
SSI32H569
none
SSI32H6230
DISABLE
SSI32H6231
none
EFFECT
VCM
SSI32H6240
DISABLE
VCM
SSI32H6510
SLEEP
VCM
SSI32H6810A
SLEEP
VCM and MSC
SS132H6811
SLEEP
VCM and MSC
SS132H6812
SLEEP ,STANDBY,SHOCKSLP
VCM or MSC or SHOCK
SSI32H6820
SLEEP,HEN,MEN
VCM orMSC
SSI32H6825
DISPWR
MSConly
SSI32H6520
SLEEP
Entire Device
SSI32H6521
SLEEP
Entire Device
SSI32H4633
HENABLE,MENABLE,PWRDN
VCM or MSC or Device
13-119
II
Servo Controllers and
Motor Drivers
RETRACT AND POWER FAULT (continued)
SLEEP MODES (continued)
Dual function devices like the SSI32H681 OA and SSI32H6811 respond to sleep by turning off both the servo and
spindle sections. Selective sleep modes are offered in others which allow servo/MSC combination devices to
power down servo while maintaining spindle operation.
Multiple Power Down Modes
Servo/MSC combination devices which offer selective sleep modes such as the SSI32H6812 can support multiple
power down modes. As an example, the SSI 32H6812 supports the following power down modes selected by
programming bits in the control register:
MODE
CONDITION
SHOCK
Independently power down shock detector
SLEEP
Both VCM and MSC float, power fault active
STANDBY
VCM float, MSC active
RUN
Both VCM and MSC active
VCM LIMITING
VCM limiting are techniques used to insure that the data head is controlled in a non-hazardous way.
VELOCITY LIMIT
Linear mode velocity limiting is supported in the SSI 32H569 only. Velocity limiting during retract is discussed in
the Retract and Power Fault section. Velocity limiting is performed by integrating motor current from SOUT and
comparing the result against a window. When the integrator exceeds the window, then the driver is turned off.
When the driver is off, the integrator discharges and ultimately will return back into the window where the driver
is enabled once more. This behaviormay oscillate between enabled and disabled with a period determined by the
veloc~y integrator gain.
In general, the servo system should never lose control of the head but if it does happen, velocity limiting can provide
a means to insure that the head velocity is within the crash stop rating. Formulas and constraints for computing
the necessary components are found in the SSI 32H569 data sheet.
CURRENT LIMIT
VCM current limiting is a common technique which may be implemented for different reasons and in differentways.
Limiting the output current may serve to protect the head from achieving dangerous velocities. Limiting the
command current allows higher power amplifier gain while maintaining a limit on peak current. Generating a write
protect warning is useful in detecting conditions where a large servo error has been encountered and it is possible
that any pending write operation may miss track center.
Limiting the Output Current
Only the SSI 32H569 implements output current limiting. The motor current at SOUT is compared against a
window. If the current exceeds the window, the driver is disabled. When disabled, the current will decay and once
again current will be within the comparison window so that the driver re-enabled. This behavior will oscillate while
the excessive command current conditions exist.
13-120
Servo Controllers and
Motor Drivers
Limiting the Command Current
In a transconductance amplifier, a voltage is applied as input and a current is forced through the load. The input
voltage commands an output current through the load. If a limiter is placed between the command voltage and
the error summing amplifier within the transconductance amplifier, then the output current will saturate when the
input exceeds the limiter.
The SSI 32H6230 implements a limiting circuit. Figure 28 illustrates how the limiter is connected. The limiter
voltage is a CLAMP of fixed voltage. The resistors RIN1 and RIN2 determine where the CLAMP will be in effect.
The formula below computes the input command voltage (relative to VREF) at which the limiter will be active:
v.. . = RlNl + RlN2 • CLAMP
ltmd
RINI
When the absolute value of the input command voltage exceeds VUmH ' the output current will be limited to whatever
V UmH commands. Note that in the computation of amplifier gain, RIN is the sum of RIN1 and RIN2 .
I..--------I'---il
1>
CLAMP
RIN1
VIN - - " . . . ,
I
,!IN2
ERRM
32H6230
FIGURE 28: Limiting Command Current
Write Protect Warning
Write protect warning is implemented by comparing motor current at SOUT against a window. When motor current
exceeds the limits of the window, a digital output signal named WRPROT is asserted. The intent of WRPROT is
to stop any write operations in progress often by negating the WR line to the write amplifier and stopping the
sequencer in the data formatter. Write protect is implemented in the SSI32H6231 and SSI32H6825. In both parts,
the window is adjustable and can be defeated.
13-121
II
Servo Controllers and
Motor Drivers
SHOCK DETECTION
The SSI 32H6812 offers a shock detection feature useful in disabling writes to the disk when the drive is
mechanically shocked in plane with the head positioner motion. Two shock detectors are orthogonally mounted
on the drive electronics PCB. When a mechanical shock occurs, a small voltage pulse appears across the
piezoelectric crystal within the detector and the signal is amplified by the electronics within the SSI32H6812. The
amplified signal is applied to full wave rectifiers which merge both X and Y components together into a composite
signal. A low pass fiHer smoothesthe shock signal and a comparison is made to a presetthreshold. When the shock
signal exceeds the threshold, a digital signal is generated which can be routed to logic which will disable any active
write operation and signal the microcontroller.
SHOCK DETECTORS
A representative shock sensor is manufactured by TDK. Figure 29 outlines the device mechanically. This particular
device generates approximately 1.6 mV per unit gravity or G. Its capacitance is roughly 350 pF and only two of
the four su/face mount pads are active.
c
I
0
:
:·1
Sensor Output
I
FIGURE 29: Shock Sensor
SHOCK DETECTOR CIRCUIT TOPOLOGY
Figure 30 shows the basic topology for the shock detector electronics.
As illustrated, the piezoelectric shock signal is amplified by 40, full-wave rectified, filtered, then compared.
Neglecting the effect of the full-wave rectifier and writing a transfer function for the remaining amplifier and filter
blocks yields:
GCOMP
FIGURE 30: Shock Detector Topology
13-122
Servo Controllers and
Motor Drivers
As a design example, the corner frequency was chosen to be 10KHz. Choosing the following components:
R,=10 kQ, R2=7.9 kQ, R3=37 kQ and C,=2300 pF, C2=250 pF
yields the bode plot in figure 31 below:
60
40
..........
!'-..
~
20
20 log (Ih(i· 2· It· Fli)
"
o
'\
~
-20
~
....
100
1'10 6
1000
FIGURE 31: shock Sensor filter Response
The DC gain's approximately 150 and the detection threshold is VBG/2 or 1.125V. This threshold will be crossed
when the shock detector amplitude exceeds seven millivolts or approximately four G. The detection sensitivity is
adjusted by changing the discrete components configuring the filter.
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents
and trademarks or other rights of third parties resulting from its use. No license is granted under any patents,
patent rights or trademarks of Silicon Systems. Silicon Systems reserves the right to make changes in
specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is
current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1993 Silicon Systems, Inc.
13-123
0194
Notes:
13-124
Sensorless
Motor Speed Control
Application Note
------------------a
13-125
Sensorless Motor Speed Control
INTRODUCTION
Silicon Systems offers a.wide tange:in hall-sensorless
motor speed controllers. This application note is a
comprehensive MSC design guide explaining how the
MSC family members are different and how to apply
them successfully. The range of MSC components
includes those with and without integratedpoWerdrivers
or ·on-chip speed regulation. The Silicon Systems
products discussed in this note are the following:
DEVICE
DRIVE TYPE
SPEED
CONTROL
SSI32M595
predriver
yes
SSI32M7010
integrated
yes
SSI32M7011
integrated
no
SS132H6810A
integrated
no
SSI32H6811
integrated
no
SS132H6812
integrated
yes
SSI32H6820
predriver
yes
device to place in the motor to sense absolute rotor
position. For a three phase motor, three Hall sensors
may be used to directly decode the next motor
commutation state. Hall sensors offer a closed-loop
method of absolutely determining the rotor position
and to properly commutate the motor under all speed
conditions. Hall sensors burden the motor deSign,
particularly small motor deSign, with the need to place
the sensors in the motor and the extra wires forthe Hall
bias and output. The SSI32M593 and SSI32M594 are
examples of Hall sensor MSC circuits capable of driving
external Power MOSFETs at 12V.
An alternative to Hall effect sensors is to electronically
detect the rotor position by examining the backelectromotive-force or BEMF generated by a rotating
motor. This Hall-sensorless method eliminates the
need for Hall sensors to be mounted in the motor and
simplifies the motor wiring. For a DELTA type motor,
only the three wires for motor terminals A, B, and C
connect the motor to the MSC circuit; no additional
wires are required as there would be if Hall sensors
were used.
MOTOR SPEED CONTROLLERS
Silicon Systems' motor speed control or MSC circuits
are responsible for commutating DC brushless, three
phase motors. In a hard-disk drive, the motor controlled
is the spindle motorwhich is responsible for rotating the
platters at a fixed and precise speed. The MSC circuit
commutates the motor drivers, regulates speed, and
drives current through the motor windings.
Motor commutation is .the act qf,qriving current through
the motor windings in such a way as to sustain a
desired rotational direction. Commutation traditionally
has been implemented by placing some kind of sensor
onthe m9tor shaJt. Hall effec,;tsensors are an ideal
The Hall sensorlesstechnique is not as robust compared
to a design using Hall sensors. Since BEMF is detected
for commutation, there is a lower limit to motor speed.
This lower limit is very significant particularly when
starting the motor. An open-loop startup algorithm
steps the motor in a manner similar to stepper motors.
This stepping or ramping of the motor continues for
several revolutions until the motor reaches a minimum
speed necessary for reliable BEM F generation. Once
the minimum speed is reached, a transition is made to
sense the BEMF and the motor then operates much
like a Hall sensor motor. Figure 1 graphically illustrates
an open-loop startup algorithm.
Open loop startup ramp
Self spin up
1111111--_ _ __
ADVANCE signal
J
COMMU signal
~l%"ff///h'-1j
Motor leg voltage
~Wij//////A
Figure 1. Open Loop Startup Waveforms
13-126
Sensorless Motor Speed Control
5 AND 12 VOLT
The components discussed in this MSC family
application note includes those intended for a 12Vor 5V
motor drive. The 12V compatible components are all
predrivers. The 5V components are a mix of predrivers
and integrated drivers. The 5V predrivers are actually
components capable of operating at either 5V or 12V
such as the SSI 32M595. Examples.of 5V integrated
drivers include devices like the SSI 32M7010 and
SSI 32H681 OA.
PREDRIVER VERSUS INTEGRATED POWER
A predriver MSC circuit requires external power
MOSFETs. These power MOSFETs directly connect
to the motor and deliver current typically in the ampere
range. The predriver translates the commutation state
and motor current command into signal levels which
are connected directly to the gates of the external
power MOSFETs. There are three pairs of control
signals, each pair consists of one signal intended for a
lower N channel and one for an upper P channel
MOSFET. The Signal names for motor terminal "A"
MOSFET drivers are OUTA (the lower N channel driver
gate) and OUTUPA (the upper P channel driver gate).
An integrated MSC circuit includes power MOSFETs
within its package. Such a device has three pins
identified as A, B, and C which in turn directly connect
tothe motor. The integratedpowerdevicesfrom Silicon
Systems use a stacked N channel arrangement which
eliminates the need for a blocking diode when
implementing retract upon power failure (see a later
section on blocking diodes).
presented at the VIN pin ofthe MSC component. As the
motor is commutated, the transconductance amplifier
is internally switched from motor terminal to motor
terminal. Only one motor terminal at a time is controlled
and the particular terminal controlled is the lower one
which sinks current. The motor terminal current sourced
from the upper power driver is operated in a switched
mode.
Digital speed control functions found in devices such
as the SSI 32M595, SSI 32H6812, SSI 32M701 0, and
SSI 32H6820 are intended to update the speed error
once per revolution. The speed error resembles a
pulse of duration equal to the motor revolution period
with an amplitude determined from a proportionalintegral compensator.
Linear control is often preferred to PWM because in
smaller hard-disk drives, the switching neise .of PWM is
easily coupled into the read channel electrenics. Linear
contrel is a disadvantage for applicatiens requiring
high currents, particularly when starting since the
MOSFETswill dissipate significantpowerwhile limiting
the start current.
Pulse Width Modulation
CONTROL METHODS
Pulse width modulation is implemented in the
SSI 32H6811. In the SSI 32H6811, "switch-mode
.operation" is enabled and configured by writing to the
mode register ( address 10). Bits M and N setup the
switching duty cycle so that the motor start current can
be controlled. Switch mode is intended to provide an
alternative way of starting the metor, this particular
method avoids operating the lower MOSFETs in linear
mode. In switched mode, the cemmutation delay method
is fixed in one shet mede.
There are two major control methods used to implement
speed control in MSC circuits. These two are pulse
amplitude modulation PAM and pulse width modulation
PWM. Most Silicon Systems MSC components
implement PAM while one supports both methods.
Fer the SSI 32H6811 , switched mede is used for
starting and a transitiento PAM is made .once themetor
reaches seme minimum speed. In general, PWM or
switched mode makes the least power dissipatien
demands on the power MOSFETs.
Pulse Amplitude Modulation (Linear Control)
CHOOSING COMPONENTS AND SIGNALS
Pulse amplitude modulation is really a linear control
scheme updated at a regular rate. In this method, an
error voltage is applied to a transconductance amplifier
which sets the motor current. This is a linear control
scheme because the transconductance amplifier
attempts to close the loop by forcing motor current to
satisfy the command current (actually a voltage)
This sectien presents detailed design infermation for
choosing the external compenents and signals which
must be connected to Silicon Systems' MSC
compenents.
13-127
I
Sensorless Motor Speed Control
Transconductance Power Amplifier Gain
All Silicon Systems MSC components implement a
linear transconductance power amplifier which accepts
a command current (in the form of a voltage) and
attempts to force a current through the motor. The pin
which receives the current command is named VIN on
all parts except the SSI 32H6812. For all components,
motor current is sampled across a sense resistorwhich
connects all three lower Nchannel MOSFET sources
to ground. This sampled motor current is amplified by
a sense amplifier and then compared to the command
input at VIN. This is a closed transconductance loop
which translates the command (in voltage) to an output
current through the motor. Figure 2 illustrates how the
transconductance amplifier is configured.
The design equations for the power amplifier gain are
derived from the following relationships:
V SENSE = ISENSE • RSENSE
VFEEDBACK = ISENSE • RSENSE
The transconductance loop attempts to force the
feedback voltage Vfeedback to equal the command
voltage at the VIN pin. When this condition is satisfied,
the amplifier is operating linearly. otherwise the amplifier
is saturated. For linear operation:
VIN = VFEEDBACK = IMOTOR • RSENSE ·GAINsENSE
so solving for the transfer function:
=
K
a
VIN
IMOTOR
VIN
=
1
RSENSE • GAINsENSE
where Ka is the spindle amplifier transconductance
gain.
Choosing the Sense Resistor and Sense Gain
Rsense
Figure 2. Transconductance Amplifier Configuration
The sense amplifier gain varies across the MSC
components as indicated in the table below:
DEVICE
SENSE GAIN
PROGRAM
METHOD
SSI32M595
4
Fixed
SSI32M7010
4/8
4 at startup,
When starting the motor, the maximum value of VIN
voltage should be applied which will result in a limiting
peak start current. Since run current is usually much
smaller than start current, trade-ofts between VIN
voltage, sense resistance, and sense amplifier gain
may be necessary. Ideally, the amplified sense voltage
Vsense should be around 0.75V so when possible, a
fixed sense resistor and programmable sense gain
should be employed.
The design approach for choosing the sense resistor
is to first calculate Rsense to satisfy the start current
requirement knowing that the input voltage at VIN (see
the following section for parts with internal speed
control) ranges from zero to approximately 2.5V:
8 in linear
control mode
SSI32M7011
4
Fixed
SSI32H6810A
5 or 10
Pin strap
SSI32H6812
5,10,20,30
Register
SSI32H6811
5,10,20,30
Register
SSI32H6820
5,10,15,20
Register
RSENSE =
2.5
.
ISTART • GalnSENSE
where GAINsENSE is the smallest value available such
as 5 forthe SSI32H681 OA and ISTART is the target st art
current. As a design example, consider a target 1A
start current in a SSI32H6810A application:
RSENSE =
13,128
~
I • 5
= 0.5Q
Sensorless Motor Speed Control
If the run current for the particular motor above drops
to 150 mA, the higher sense gain of 10 should be
employed to increase the amplitude of VSENSE as
indicated below:
IMOTOR
GAIN
VSENSE
0.15A
5
0.375V
0.15A
10
0.75V
Programmable gain offers a way of adjusting V SENSE to
a sufficient amplitude which maximizes the signal-tonoise ratio and generally improves the transconductance amplifiertransient response. Components
such as the SSI 32H6811 offer even higher sense
amplifier gains.
Target Speed, Motor Poles, and SYSCLK Frequency
All Silicon Systems MSC components provide some
means for indicating motor speed. Some of these
devices include an internal speed control function
which relies on the speed indication. The speed of the
motor is determined by the numberof poles in the rotor.
The number of commutations a three phase motor
experiences per revolution is determined by the number
of rotor/stator alignments computed below:
Coms REV = 3 • NpOLES
yielding for typical pole counts:
12 for 4 pole motor,
24 for 8 pole motor, and
36 for 12 pole motor.
Startup Current In Devices with Speed Control
Silicon Systems components with speed control
generate the start current command internally. Instead
of using the VIN pin, an internal reference voltage is
selected. The table below lists what this reference is
and how it is selected:
DEVICE
METHOD
SS132H6812
VCM DAC redirected to LF pin
SS132H6820
VLlM pin when more than 3% sloVl
SSI32M595
2.25V when more than 3% slow
SSI32M7010
2.25V when more than 3% slow
This Coms rev relationship results since each motor
pole aligns once with each statorwinding per revolution.
Silicon Systems MSC components determine' one
revolution by counting the number of commutations;
the speed indicated is the time taken for one revolution
to occur. The following table indicates how each
component indicates motor speed:
For theSSI 32M595 and SSI 32M7010, the start
current command voltage is fixed at 2.25V. For the
SSI 32H6820, the VLlM pin voltage provides a
programmable start current command. In the
SSI 32H6820, VLlM can be tied to the band-gap
reference for simplicity. For all three parts, when the
motor is faster than 3% slow, then the VIN pin is
selected for motor current commands.
The SSI32H6812 differs from the other three because
a second order discrete filter is used to compensate the
motor. In the SS132H6812, the voltage across this filter
at the LF pin is directly connected to the
transconductance amplifier. For starting and
initialization, the VCM positioner DAC can be redirected
to force the LF pin voltage. This redirection is
accomplished by setting the MSCDAC bit in the
MSC_MODE register.
13-129
I
Sensorless Motor Speed Control
Target Speed, Motor POles,
and SYSCLK Frequency (continued)
DEVICE
METHOD
COMMENT
SSI32M595
8 poles assumed
Change in metal mask
SSI32M7010
8 poles assumed
Change in metal mask
SSI32M7011
REVCLK every 12 commutations
Externally divided for more than 4-pole
applications
SSI32H6810A
REVCLK every 12 commutations
Externally divided for more than 4-pole
applications
SS132H6811
REV every 12 commutations
Externally divided for more than 4-pole
applications
SSI32H6812
REV every 24 or36 commutations
8- or 12-pole motor selection
SSI32H6820
4,8,12,16 poles
Register programmable
Devices such as the SSI 32M595 and SSI 32M7010
are fixed in the number of poles assumed; therefore,
operation with motors having other than eight poles is
best handled with a metal mask option. When using the
either the SSI32M595 orSSI32M701 0 (as is with eight
poles assumed) with a four pole motor, two mechanical
revolutions occur for every one revolution electrically
detected. For a twelve pole motor, every 2/3 mechanical
revolution resuHs in the 24 Commutations necessary to
indicate a revolution.
For devices like the SSI 32M595 and SSI 32M7010,
speed control of motors having other than eight poles
is still possible. As an example, assume a four pole
motor is to be controlled at 3600 RPM. Instead of
supplying a 2 MHz SYSCLK to the component, supply
it with a 1 MHz clock. This correction works because
two mechanical revolutions of 3600 RPM will occur in
1/30th of a second, and cutting SYSCLK to one-half
shifts the period timer to count down. from 8333 in
1/30th of asecond (instead of 1/60th). The sample rate
is now 30 Hz instead of 60 Hz and the resolution is 4 ~
instead of 2 ~, but for. most applications this is still
much higher than the control open-loop bandwidth.
Twelve pole emulation is not as successful because
the samples are not always based on the same
commutation edge. This ping-pong sampling in 12 pole
motor may introduce a small degree of speed
measurement uncertainty.
Devices having internal speed control measure the
period of one revolution with SYSCLK. The frequency
of SYSCLK varies for the devices listed below, but
internally the clock is divided by the same factors with
a count resolution of 2 ~. The frequency of SYSCLK
is based on a 3600 RPM target speed and is used as
follows:
DEVICE
SYSCLK
SYSCLK USAGE
SSI32M595
SSI32M7010
SSI32M7011
SSI32H6810A
SSI32H6811
SSI32H6812
SSI32H6820
2 MHz
Speed control reference
Speed control reference and adaptive commutation
Used only for adaptive commutation circuit
Used for VCM sense and adaptive commutation
Clock used by DACs, VCM sense, and adaptive commutation
Speed control reference, VCM sense, and adaptive commutation
Used for programmable speed control counters, YCM sense.
amplifier, and DAC
2 MHz
2MHz
2MHz
8 MHz
1 MHz
4MHz
13-130
Sensorless Motor Speed Control
The devices having built-in speed control are the
551 32M595, 551 32M7010, 551 32H6812, and
551 32H6820. The 551 32H6820 target speed is
programmable by setting a revolution period value into
registers. The 551 32M595 and 551 32M7010 may
operate at other target speeds by scaling the SYSCLK
frequency. This scaling is a simple linear relationship
as follows:
F:
SYSCLK
=
TARGETRPM (2 MHz)
3600
For example, an 8-pole motor operating at 5400 RPM
with a 551 32M595 would require a 5Y5CLK frequency
of 3 MHz. Other parameters shift with frequency such
as the proportional and integral DAC gains of Kp and
KI. Not all parts lend themselves to scaling 5YSCLK.
The target speedofthe SSI32H6812 is 5400 RPM. For
the 5S1 32H6812, a similar scaling relationship as
given above for the SSI 32M595 can be computed for
target speeds other than 5400 RPM. Change the
demoninatorto 5400 and the base frequency to 1 MHz.
Any scaling of frequency for this component must be
carefully considered since this SSI 32H6812 device is
a combination of M5C and VCM functions. SYSCLK
effects the VCM block also; therefore, changes in
SYSCLK should be small and performed only to tweak
the RPM.
External Power Drivers
Silicon Systems' MSC predrivers require external power
drivers to connect to the motor. The two MSC predrivers
are the SSI 32M595 and SSI 32H6820; both
components are 5V and 12V compatible. Connection
from the predriverto the power devices is throughthree
pair of signals. Each pair consists of an upper P
channel gate signal denoted as OUTUPx where x is A,
B, or C motor terminal; and a lower N channel gate
signal denoted as OUTx. Figure 3 illustrates typical
connections for a predriver such as the SSI 32H6820
and external power drivers. A later section discusses
blocking diodes and hard disk head retraction
implementation.
The power MOSFETs chosen must be compatible with
the predrivervoltage levels. Of course turn-on resistance
and peak current are deciding factors; however,
MOSFET gate threshold is a key parameter. As an
example, consider the SSI32H6820with the upper and
lower output swings:
+12V
OUTUPA
OUTUPB
OUTUPC
OUTA
"J
OUTB
OUTC
I
Rsense
Figure 3. Predrlver Connections to External MOSFETs
13-131
I
Sensorless Motor Speed Control
SIGNAL
OUTX
Vol
1Vmax@1mA
Voh 4.5V min with vm =12V and -50
1Vmax@3mA
Voh
12 V - pulled up with resistor
INITIALIZATION METHOD
SSI32M595
Clear RESET low
SSI32M7010
Clear both BRAKE and
RESET low
SSI32M7011
Clear both BRAKE and
RESET low
SSI 32H681 OA
Clear both SLEEP and
BRAKE low
SSI32H6811
Clear both BRAKE and
RETR low
SSI32H6812
Program the START bit in
MSC_MODE
SSI32H6820
Program the STAT bUs in
register 0
J.IA
OUTUPX
Vol
DEVICE
The lower N channel MOSFET must saturate with 4.5V
on the gate and yet be completely turned off below 1V.
A nominal gate threshold of 2V or 3V is necessary to
meet these switching conditions. The upper P channel
MOSFET has similar constraints when operating at 5V;
however, for 12V operation the swing in gate voltage is
so much wider that almost anything will work.
Startup Methods
STARTING THE MOTOR
Starting a sensorless motor is more difficult than a
motor with Hall sensors orbrushes. Back EMF sensing
requires a minimum motor speed to generate sufficient
voltage for detection. When first starting the motor, no
BEMF will be available and therefore some alternative
scheme must be used to determine when to commutate.
Initializing Commutation State
The initial commutation state can be asserted by the
microcontroller. The methods for performing this
initialization vary with each component family. In
general, there is little advantage in initializing the
commutation state to a specific value because the rotor
may be anywhere. When current is first applied, the
rotor need only move forward or backward by at most
one commutation angle to align with the applied stator
field. The table below summarizes how each MSC
component commutation state can be initialized:
Various ways have be.en devised to compensate for
the lack of BEM Fwhenstarting the motor. Most startup
methods are open-loop in nature. The basic open-loop
scheme is to operate the motor as if it were a stepper
motor, synchronously following a commutation
sequence which accelerates the motor speed up to the
minimum RPM necessary for BEMF detection. The
generation of the commutation sequence often is by a
microprocessor, based on a table of timing values
implementing a startup prOfile.
Open-loop startup schemes suffer in reliability when
the motor or load conditions change. If the motor
cannot follow the commutation sequence, the motor
may fail to start. All open-loop startup methods s~ould
test for motor rotation and must retry to startup If the
motorfailed to spin up. Typically, two orthree revolutions
are all that is required to start the motor. For a 12 pole
motor the commutation sequence should provide 72
or mo~e steps of open-lOOp commutation sequencing.
13-132
Sensorless Motor Speed Control
Computing a Startup Profile
An open loop commutation sequence can be calculated
knowing the motor number of poles, numberof phases,
torque constant, start motor current, load inertia, and
number of steps. The procedure below generates a
series of commutation timing values which can serve
as a starting pointforthe startup commutation sequence.
First, determine the distance traveled during each
commutation to be:
L\.
=
2 •
Np
•
11:
N"
where the subscript "i" corresponds to each
commutation sequence step ranging from 0 to the
number of steps required. Each distance is computed
as:
The instantaneous velocity at time
from:
As an example, consider a design having the following
properties:
Je = 0.024 and kT = 3.7 in consistent units,
When constant acceleration is assumed (which is
reasonable for low RPM where the peak start current is
constant), the angular acceleration (neglecting friction)
is found from:
= Kr • 1M
Je
where
1m = 1A peak start current,
Np = 12 poles and Nacket: send the word stored in R2 (MSB) and R3 (LSB)
; to the SSI 32H6811
send"'packet:
SETB
CLR
MOV
JNB
CLR
MOV
JNB
CLR
RET
SDEN
TI
SBUF,R3
TI,$
TI
SBUF,R2
TI,$
SDEN
Assert SDEN to enable serial transfer
Send the LSB first
wait for transfer to complete
Send MSB
Drop SDEN to end transfer
; --------------------------------------------------i
; REVCLK watchdog interrupt handler
; --------------------------------------------------i
time int:
CLR
CLR
MOV
MOV
EA
TR1
TH1,itOffh
TL1,itOffh
; turn off timer
;Set timer to value which signals
;that it has expired.
rphase is an internal variable read in rev cnt int
and it divides rev cnt interrupts by 3 because the
test motor was 12 pole
MOV
rphase,B
; Set
; and
ORL
ANL
SETB
RETI
signals tested in C code indicated motor stalled
not locked or racing
sys_status,lIMOTOR_STALL
sys_status,#«MOTOR_RACE OR MOTOR_LOCK) XOR Offh)
EA
; --------------------------------------------------i
; REVCLK interrupt handler
; ----------------------------------~---------------;
13-140
Sensorless Motor Speed Control
rev int:
CLR
EA
decrement phase counter
DJNZ rphase,riOO
; take this path on the 3rd interrupt, measure period now
CLR
TR1
stop timer
MOV
rphase,#3
reset phase counter
MOV
revcnt,TH1
store timer count in locs C code sees
revcnt+1,TL1
MOV
MOV
TH1,#0
reset timer to count next period
MOV
TL1,#1
SETB TR1
SJMP riOl
riOO: LJMP rexit2
riOI:
; Save machine state here - dependent on C compiler useage
; clear stall flag if TH1 was < Offh (now in revcnt)
MOV
A,revcnt
INC
A
JZ
ri1
;jumps if was stalled
ANL
sys_status,#{MOTOR_STALL XOR Offh) ;not stalled
ri1:
; check for racing motor (indicates stalled spindle and
motor oscillation)
MOV
R4,revcnt
MOV
RS,revcnt+1
MOV
R2,#00fh
; 10000 RPM @ 8 MHz
MOV
R3,#OaOh
LCALL ?UI CMP LT_L02 ;Borrow compiler int compare sub
JZ
ri2
;nonzero means not less than such that
;the motor must not be oscillating
ORL
sys_status,#MOTOR_RACE
set MOTOR RACE
ANL
sys_status,#{MOTOR_LOCK XOR Offh)
; clear MOTOR LOCK
SJMP rexit
; motor is not racing, so clear MOTOR_RACE flag
ri2: ANL
sys_status,#{MOTOR_RACE XOR Offh)
; if motor is supposed to be running, as indicated by
; MOTOR_RUN flag, then call speed control function
MOV
A,sys status
ANL
A,#MOTOR_RUN
JZ
rexit
MOV
no parameters on stack
RI,#O
LCALL speed_control
rexit:
rexit2:
SETB
RETI
EA
13-141
II
Sensor less Motor Speed Control
COMMUTATION DELAY
Silicon Systems MSC components implement two
different methods for de laying motorcommutation from
the detection of the BEMF event. These two methods
of commutation timing are fixed delay and adaptive
delay. Most components implement one or the other,
however, the SSI32H6811 and SSI32H6812 provide
both. The table below identifies the methods used by
the MSC family members:
changing slope corresponding to a sine wave. For
trapezoidal motors, optimum commutation delay results
in only a very slight improvement in motor efficiency.
Fixed commutation offers a Simple, robust design. The
single RC time constant configures the motorthroughout
its operating range. For a broad range of motor
applications, fixed commutation delay is superior
because it offers greater noise rejection compared to
adaptive methods.
DEVICE
METHOD
Extending the Noise Gate Interval
SSI32M595
Fixed
SSI32M7010
Adaptive
SSI32M7011
Adaptive
SSI 32H681 OA
Adaptive
SSI32H6811
Both, programmable mode
In some instances when using the SSI 32M595 or
SSI 32H6820, one fixed delay is not sufficient. These
instances occur when the start current transients do
not die off quickly enough and false BEMF events are
detected. This failure occurs because the fixed
commutation delay also provides a noise blanking
interval. At high target RPMs, the time constant is small
so the large amplitude transients present at startup still
have significant amplitude after the noise blanking
interval has expired.
SSI32H6812
Both, programmable mode
SSI32H6820
Fixed
Fixed Commutation Delay
Fixed commutation is implemented with a nonretriggerable oneshot. When the BEMF event is sensed,
the one shot is triggered. The one shot duration is
programmable with an external resistor and capacitor
network in the SSI32M595 and SS132H6820. The one
shot duration is internally set within the SSI 32H6811
and SS132H6812.
The fixed commutation delay provides two functions.
The first function is to delay the actual advancement of
the commutation state counters from the sensing of the
BEMF event. Choosing the RC network for the target
RPM results in optimum motor operation. The second
function of the delay circuit is to provide a noise-gating
interval where the transient noise resulting from motor
commutation is ignored.
When a single delay time constant is not sufficient, an
analog switch and series resistor may be added to
extend the commutation delay over wider range of
operating conditions. Figure 5 illustrates such a circuit.
The analog switch is open when starting the motor,
then closed usually after the startup. ramp is complete.
The RC time constant is based on just the resistor and
capacitor itself at startup; during run the RC time
constant is based on the parallel resistance of the two
resistors and the capacitor. The microprocessor is
responsible for closing the analog switch.
When using fixed commutation delay, the same delay
duration is present throughout the operating region of
the motor. This means that the delay used at startup is
the same as that for the target operating speed. Only
the target operating speed is optimum; startup does not
operate at the optimum point.
Most hard-disk motors are very trapezoidal in nature.
This means that the BEMF voltage waveform across
the motor windings appear to have a trapezoidal shape
for a constant speed. The slope of the transition from
most positive to most negative is fairly great unlike the
13-142
+5V
EXTRC
Enable
at RUN
Figure 5. Extending Fixed Commutation Delay
Sensorless Motor Speed Control
Design Example
Adaptive Commutation Delay
Forthe SSI32H6820, the RC network is placed at the
EXTRC pin. The capacitor goes to ground while the
resistor pulls up to 5V. The minimum resistance is 10K
with a maximum of 10 MQ, capacitance must be
greaterthan 100 pF. From the data sheets the following
is given:
Adaptive commutation delay does not require any
external components. Instead, the adaptive
commutation delay circuit determines the optimum
commutation time by observing the prior period. In this
way, the next commutation period is predicted by
looking at the prior period history.
1"d
=
1"n
= 0.29
0.56 • R • C
• R • C
sec
sec
where td is the commutation delay period and tn is the
additional noise blanking interval occurring after the
delay. These time constants must be chosen so that:
where tc is the target RPM commutation period. If this
constraint is not met, the motor will fail to commutate
properly at the target speed. This false commutation
will appear as rough, irregular operation indicated by a
very irregular drive voltage waveform at the motor
terminals.
If the target speed is 5400 RPM and the motor is 12
pole, the target commutation period is:
1"c =
36
.6~400
or approximately 309 J.IS
Choose the sum of td + tn to be less than tc to build in
margin. Picking this sum to be:
The SSI32H6810A is an example of a device which
implements only adaptive commutation delay. In the
SSI 32H6810A, the adaptive circuit delays the
advancement of the motor commutation state counter
by 3/7ths of the prior commutation period. The noise
blanking interval following motor commutation is an
additional2/7ths (specified in the data book as 517ths
from the beginning of the commutation period).
The adaptive commutation delay circuit has a very
wide range of operation. This range is specified relative
to a nominal target speed of 3600 RPM. For the
SSI 32H681 OA, the adaptive range is -80% to +50%.
Though a nominal target speed is given, this value
does not suggest a necessary operating speed. Instead,
the nominal speed given is based on the frequency of
SYSCLK which internally sets the rate at which the
adaptive circuit switched capacitors operate.
For the SSI 32H681 OA, there are restrictions on what
values SYSCLK can assume because this clock is
used also in the positioner motor sense amplifier. In a
device like the SSI32M7011, SYSCLK can be modified
freely since it only effects the adaptive circuit itself. The
nominal frequency is linearly scaled with SYSCLK.
For the SSI 32H6810A, the adaptive commutation
delay operating ranges versus the allowed range in
SYSCLK are:
SVSCLK
RPM
Low end
RPM
Nominal
allowing for 20 % total error in the RC network, yields
a design target:
1.5 MHz
540
2700
.4050
2MHz
720
3600
5400
"'rc :; 250 J.IS
2.5 MHz
900
4500
6750
"rrc
= 0.8
• 'fc
Choosing a common value for C of .01
R= ....c =25kQ
C
~Fd, yields
R of:
RPM
High end
Adaptive commutation may improve motor operating
performance slightly. It has the advantage that the
motor commutation is dynamic and may improve spin
up time slightly. Also, no external components are
necessary to configure the commutation delay. The
adaptive circuit has the disadvantage of greater noise
sensitivity compared to fixed delay.
13-143
II
Sensorless Motor Speed Control
Selecting the SSI 32H6811 Delay Mode
The SSI32H6811 provides programmable commutation
modes. The mode register at address 01 contains both
the M and N bits which are decoded as follows:
M
N
Commutation
Delay Method
Comment
0
0
Adaptive
INCOM effects
adaptive timing
0
1
Adaptive
INCOM ignored
0
2
Adaptive
INCOM ignored
0
3
Fixed,
one-shot
INCOM
effects one-shot
timing
<>0
X
Fixed,
one-shot
PWM,INCOM
one-shot timing
where:
is the noise blanking interval such
as 8S0 J..lS,
Np is the number of poles, and
N the number of phases.
"C n
With 12 poles and three phases, RPM MAX is 1960 RPM.
Clearly, the microprocessor must switch from one-shot
mode into adaptive mode before this maximum RPM is
reached or else miscommutation will occur. Note that
if one-shot mode is desired under all conditions, setthe
voltage at INCOM lower so that a higher target RPM
can be reached. The lower limit of INCOM voltage is
approximately O.SV.
Programming the SSI32H6812 Delay Mode
The table above shows that both M and N bits within the
mode control register effect commutation delay and
the power control method. Forthe SS132H6811, PWM
is a switched mode of operation intended for used only
at startup.
The pin INCOM can effect the commutation delay
circuits of both methods. When M is zero and Nis 1 or
2, the commutation delay is adaptive and INCOM is
ignored. In all other modes, INCOM is an input.
Generally, INCOM is not useful in modifying the adaptive
delay timing. However, the voltage on INCOM must be
externally set for one-shot mode. Typically, a voltage
divider is used to setup the voltage on INCOM using the
following guidelines:
INCOM
VOLTAGE
ONE-SHOT
DELAY
O.SV
1S0 J..ls
2.5V
SOO J..lS
The SSI 32H6812 offers both adaptive and fixed
commutation delay like the SSI 32H6811. The
SSI32H6812 delay mode is selected by programming the
DELAY bits in the MSC_MODE register as lis' 3d below:
DELAY1
DELAYO
0
I--
0
0
1
Fixed at 1S0 J..lS
1
0
Fixed at 300 J..ls
1
1
Fixed at SOO J..lS
Fixed commutation places an upper bound on the
operating motor speed. When the motor speed
increases, the commutation period decreases and
miscommutation will occur when these are equal. The
maximum RPM before miscommutation occurs under
these one-shot conditions is computed from:
RPM
Max
SettinglNCOM for 2.SV yields the best overall oneshot timing well suited for starting the motor. The
SOO J..lS one-shot commutation delay results in a total
noise blanking interval of 8S0 J..lS which should be
sufficient in all cases to insure that the startup current
amplitudes die down to insignificant levels. The
maximum RPM before miscommutation occurs under
these one-shot conditions is computed from:
MODE
Adaptive
= _ _6_0_ _
Tn.
Np • N~
where: "Cn is the fixed delay period, such as SOO J..lS
Np is the number of poles, and
N the number of phases.
With 12 poles and three phases, R PM MAX is 3300 RPM.
Clearly, the microprocessor must switch from fixed
delay mode into adaptive mode before this maximum
RPM is reached or else miscommutation will occur.
13·144
Sensorless Motor Speed Control
MOTOR OSCILLATION
The SS132H6810A, SS132H6811, and SSI32H6812
are intended for small form factor hard-disk drives
typically of 2.5" or less. The motor voltage constant of
many of these drive motors is particularly low and
therefore, these devices offer sensitive comparators to
detect the BEMF at low speeds. Under certain
circumstances, it is possible for the motor to get into a
condition where it will oscillate. When this oscillation
occurs, the motor will not spin.
Motor oscillation occurs when the motor is energized
but it is not turning. Under this Situation, there is no
BEMF for the comparators to detect. Without BMF,
noise can falsely trigger a BEMF detection event.
When this happens the commutation state counter is
advanced and more noise is generated by the very act
of commutation. lithe motor is notturning, this sequence
will continue and increase in frequency. Very quickly,
the motor will break into oscillation.
The conditions which may leadto motor oscillation are:
It is possible to detect motor oscillation since the
resulting frequency is much higher than the operating
commutation rate. Such a detector could be
implemented in the startup firmware during the test to
see if the motor is spinning after the ramp. The test for
spinning may involve counting the number of
commutation state changes over a fixed period of time.
If it is observed that the period of state changes is less
than some threshold, it may be deduced that the motor
is oscillating and the startup should be retried.
Finally, snubbers may eliminate oscillation. Snubbers
effect the transient waveform across the motor. In 12V
designs, there may be high amplitude voltage transients
during startup which take a long time to die out to a
negligible value. The SSI32M595 does not implement
dVIdT limiting and therefore snubbers are the only way
to modify the transient response.
ADVANCE MISCOMMUTATION
ADVANCE miscommutation is the event where the
commutation state counter did not properly respond to
Ihe rising edge of the ADVANCE signal during startup.
The causes for miscommutation are:
1.
The motor can't follow the startup ramp
2.
The terminal speed at the end of the ramp is
too low
2. Low BEMF and comparator noise
3.
The motor rotor is stuck
3. Motor following ramp too closely
The steps to solve oscillation are:
1. ADVANCE pulse width too wide
ADVANCE Pulse Width Too Wide
1.
Insure the motor can follow the ramp
2.
Insure terminal speed generates at least 100
mVBEMF
3.
Select fixed commutation delay during startup
4.
Implement software detector for oscillation
5.
Implement snubbers (sometimes needed in
12V drives)
By making sure the motor can follow the ramp, the
occuranceof oscillation will be avoided. This is because
a rotating motor generates BEMF which will dominate
all noise sources. Of course, the terminal speed of the
ramp must provide sufficent speed to generate at least
100 mVof BEMF though more is always better.
Fixed delay offers better noise rejection compared to
adaptive. In general, the longer fixed delays are better.
The adaptive circuit will adapt to the noise itself and
quickly move to the shortest commutation interval. In
these parts, this minimum interval is 125 IJ.s yielding a
commutation state change frequency of 8 kHz.
All Silicon Systems MSC devices to date except the
SSI 32H6812 rely on the ADVANCE pulse during
startup 10 block BEMF detection. (The SSI32H681 OB
and SSI 32H6811 B implement a new design which
prevents miscommutation; this section is not applicable
to these new parts.) Internal to the device, ADVANCE
is logically OR'ed with the signal associated with BEMF
detection events. During startup, the rising edge of
ADVANCE will increment Ihe commutation state
counter. The startup firmware should keep ADVANCE
high most of the time and lower it only briefly to assert
the next low-Io-high transition.
In this design, there is a brief window where a collision
between the ADVANCE edge and a BEMF detection
event can occur. Depending upon the width of the
ADVANCE pulse, the collision can result in the following
outcomes:
13-145
a. No commutation error
b. Failure to commutate
c. Double commutation
I
Sensorless Motor Speed Control
ADVANCE Pulse Width Too Wide
(conlinued)
Figure 6 below illustrates graphically the possible
outcomes:
ADVANCE
I
BEMF
CK
OK
I
I
OK
I
I
OK
I
L
I
Double commutation
Early. bulOK
J
Early. bulOK
OK
Figure 6 - Advance/BEMF Event Collisions
Low BEMF and comparator noise
Mlscommutation SolutIon
Inthe 681 X MSC devices, the comparator sensitivity is
particularly high. This sensitivity is high so that the low
BEMF generated by small form-factor drives can be
detected. During startup, there is very little BEMF and
therefore any noise may trigger the comparators to
falsely detect BEMF events. This increases the chance
for ADVANCE.pulse collision discussed in item 1
above.
Solutions which insure proper startup commutation are
itemized as follows:
Motor following ramp too closely
During open loop startup discussed earlier, the motor
is accelerated by following a commutation ramp. If the
motor is following the ramp very closely such that there
is essentially no "slip," then a true BEMF event may
occur precisely at the time where the next ADVANCE
pulse is to be generated. The occurance of this is rare
but it does relate to item 1 above. Often, increasing the
speed of the ramp slightly will eliminate this event from
occuring.
DEVICE
SOLUTION
SSI32M595
Minimize ADVANCE width, t>21JS
SSI32M7010
SSI32M7011
SSI32M6810A
SSI32M6811
SSI32M6812
SSI32M6820
PulllNCOM high during startup
PulllNCOM high during startup
PulllNCOM high during startup
Pull INCOM high during startup
Assert START bit to block
Program STAT bits to set state
The SSI 32M595, SSI 32M7010, SSI 32M7011, and
SSI 32H6820 devices tend to have lower comparator
sensitivity and therefore should not be subject to
comparator noise. Typically for these parts, the only
type of event which results in miscommutation is due to
the motor following the ramp too closely.
Pulling up INCOM refers to a technique of forcing +5V
13-146
Sensorless Motor Speed Control
on the INCOM pin during startup. This method can be
implemented by placing a PNP transistor with the
emitter at +5V, collector on INCOM, and the base
controlled through a resistor. Typically a 10k Q resistor
and a 2N2222A type transistorwill work. It is necessary
to provide some output signal which can sink base
current and turn on the transistor during startup. When
switching to run, the transistor should be turned off.
See Figure 7 for a circuit diagram to pulllNCOM high.
COMMUTATION TRANSIENTS
When the motor is com mutated, transient voltages and
currents result. The magnitude of these transients can
be reduced in various ways across the Silicon Systems
MSC product family. The table below indicates what
methods are available to each component in the MSC
family:
DEVICE
+5V
32H6810A
INCOM
TRANSIENT REDUCING
METHOD
SSI32M595
External Snubbers
SSI32M7010
dVIdT limiting
SSI32M7011
dV/dT limiting
SSI 32H681 OA
dV/dTlimiting
SSI32H6811
dV/dT limiting
SSI32H6812
dV/dT limiting
SSI32H6820
dV/dT limiting
The commutation transient is generated by the switching
off of current in a motor leg while commutating as figure
8 illustrates. Each motor leg has a significant inductance
and when the conduction path for the current in the
motor leg is abruptly reduced, the energy stored in the
charged inductor discharges resulting in a transient.
tJP pulls base low to turn on transistor which in turn
pulls INCOM towards five volts to eliminate collisions.
Figure 7. PulllNCOM High to Eliminate
Miscommutation
The SSI 32H6812 and SSI 32H6820 differ from the
balance ofthe MSC parts. The SSI32H6812 has a bit
which when set high blocks all BEMF events and insure
no miscommutation. The SSI 32H6820 has three bits
which directly specify the next commutation state. In
the SSI32H6820, it is recommended to program these
bits instead of pulsing ADVANCE when
miscommutation is a concern.
The current rise when turning on a motor leg is
determined by the electrical time constant of the motor
inductance and total series resistance of the motor and
drivers. By commutation sequence design, there will
not be any initial current flowing in the motor leg.
When turning off a motor leg, the energy stored in the
inductor can be thought of as an initial condition modeled
by current source which will decay in amplitude. The
decay time constant will be determined by the motor
inductance and the total resistance making up the
inductor discharge path. The voltage polarity of the
transient is determined by which end of the motor leg
is switched off. If the upper leg is switched off while the
lower leg is held near ground, the transient voltage will
be negative in amplitude. When the lower leg is switched
off while the upper leg is held near the supply voltage,
the transient voltage will be positive in amplitude.
Negative going transients are limited by diodes to
ground as shown in figure 8. Positive going transients
are limited in different ways depending on the circuit
implementation. Figure 8 illustrates the transient
response for a device with stacked N channel MOSFET
integrated drivers such as the SS132H6810A.
13-147
I
Sensorless Motor Speed Control
,
Upper MOSFET A
sources current
Upper MOSFET A
turns off
Lower MOSFET C
sinks pin C near
ground
Upper MOSFET switch turning off results in negative transient clamped by diode
Lower MOSFET C
sinks pin C near
ground
Pin Crises
positive
above +V
+
Lower MOSFET C
turns off
Lower MOSFET switch turning off results in positive transient
Figure 8. Switching Transients with Integrated Drivers
13-148
Sensorless Motor Speed Control
COMMUTATION TRANSIENTS (continued)
The SSI 32M6810A internally implements stacked N
channel MOSFETs. The lower N channel devices have
kick back diodes useful for rectifying the spindle motor
for retract purposes. The SSI 32H6810A does not
require a blocking diode since there is no inherent
parasitic diode across the upper N channel FET. Three
external diodes are added to complete the full-wave
rectification of BEMF for retract voltage. The common
point of these three diodes is connected to the VBEM F
pin on the SSI 32H6810A. The positive transient
discharge path is a high impedance consisting of the
upper diode to and into the VBEMF pin. Limit the peak
transient voltage with sufficient dVIdT adjustment.
RRAMP is a resistor which sets an internal current
source responsible fortu ming offthe driver by lowering
the gate voltage. The amplitude of this current source
determines the speed at which the driver gate voltage
drops. Actually, the lower driver turn off effects the
dl/dT (rate of change in current) in the motor leg. The
transient normally observed is the voltage which results
across the inductorfrom the dropping motor current as
described in the basic equation:
When using external power MOSFETs such as with the
SSI32H6820, kick-back protection diodes are always
found across the P and N channel MOSFET sections.
The lower protection diode shunts the motor terminal to
ground through the sense resistor. In a bipolar (fullwave) drive mode, the positive transient is discharged
through low impedance made up by the upper kickback diode and P channel MOSFET currently switched
on. In unipolar drive mode, the discharge path is a high
impedance because there isn't an upper P channel
MOSFET. For unipolar mode , the peak transient voltage
may significantly rise above the spindle voltage supply
and must be limited by dV/dT or snubbers.
Snubber networks are RC networks placed across the
motor windings. "Snubbing" networks are designed to
provide a path forthe transient current to flow when the
motor leg is turned off. The basic network is a series
resistor and capaCitor combination which is placed
across two adjacent motor terminals, three such
networks are needed for a three phase motor.
Adjusting dV/dT with RRAMP
In most Silicon Systems MSC components, the lower
driver turn-off time can be adjusted. When the lower
driver is turned off in a slower, controlled manner
(compared to an abrupt switching off), the positive
going transient voltage amplitude is reduced. This
dV/dT (rate of change in voltage) limiting action of the
lower driver serves to discharge the inductor and
reduce the transient voltage developed across the
inductor discharge path.
A resistor is used to adjust the lower driver gate turn off
time. Forthe SSI32H6811, the following relationship is
specified:
dV
dl
15
V
RRAMP
J1S
where RRAMP is in kf2.
dI
Vindue/or = L·
dt
Snubber Networks
The design of the snubber network is completely
discussed in the Silicon Systems application note
titled: Snubbing Network Design for Spindle Motors.
INTERNAL SPEED CONTROL
Several Silicon Systems MSC family members provide
internal speed control while the rest require external
speed control. There are two types of internal speed
control provided in Silicon Systems MSC components:
1. Digital PI configured with resistors
2. Charge pump and loop filter
Both speed control methods make use of a crystal
based clock for precise digital period measurement
and internally compute velocity error. The PI
(proportional-intregal) type digitally integrates the error,
generates analog voltages from DACs, and configures
compensation with resistors. The charge pump type
applies a current proportional to the speed errorthrough
a second order passive filter which configures the
compensation.
Digital PI Speed Control
The SSI 32M595, SSI 32M7010, and SSI 32M6820 all
provide internal digital PI speed control. The
SSI32M6820 differs slightly from the others because it has
programmable target speed and number of motor poles.
13-149
I
Sensorless Motor Speed Control
Startup and Linear Control Modes
The previous model references the following parameters:
The internal speed control circuit operates in two
modes. The startup mode is automatically entered
when the motor speed is more than 3% slow. If the
target speed is 3600 RPM, startup mode is active when
the motor is not turning up through 3492 RPM. When
in startup mode, the voltage applied to the spindle
transconductance power amplifier is fixed. Linearcontrol
mode is entered when the motor speed is greater than
3% slow. When in linear mode, the voltage to the
transconductance amplifier is taken from the VIN pin.
The fixed voltage used in startup mode varies between
the three components:
DEVICE
STARTUP VOLTAGE
SSI32M595
2.25V interna.lly supplied
SSI32M7010
2.25V internally supplied
SSI'32H6820
Taken from VLlM pin
Parameter
Target speed
377 radians/sec or 3600 RPM
Kp-dac
Proportional error gain
Ki-dac
Integral error gain
Ka
Transconductance gain
Kt
Motor torque constant
J
Motor and load inertia
Laplace operator
'S
Kp
Compensator proportional term
Ki
Compensator integral term
The parameters Kp-dac and Ki-dac are speed sensitive
and can be computed as follows: '
.
K _
The SSI32H6820 offers another degree of freedom in
choosing the sense resistor. The interaction between
the startup command voltage and the current sense
resistor allow tradeoffs between the two to best satisfy
the dynamic range of the motor operating currents.
Alternatively, VLlM may be directly strapped to VBIAS
eliminating the need for external components.
=
p dac
8333 counts, • .035 volts
RPS" 2 • n rads
counts
= 0.775V/rad/sec@ 3600 RPM (60 RPS)
and
K~dac =
PI'Speed Control Model
The, small signalspeedcontroJ model is illustrated in
Figure 9 below. In this model, the friction term typically
represented by the symbol B has been assumed to be
zero.
RPS
-4- •
K p_dac
= 11_6 V/rad @ 3600 RPM
+,
Target Speed, ~
377RADISEC
Spindle
Velocity
RAD/SEC
Figure 9. Small Signal Speed Control Model
13-150
Sensorless Motor Speed Control
PI Speed Control Model (continued)
Note that the integral term is taken from the upper 6 bits
of an 8-bit digital accumulator which effectively divides
the integral gain by 4. Thesample rate of the accumulator
is in RPS (60 for 3600 RPM) so the factor RPS/4 results.
The Silicon Systems application note titled: Setting
Speed Control Loop Compensation Gains, provides a
detailed design example based on the model above.
The control circuit itself is not purely continuous and by
design has a sample rate equal to the revolution rate of
the motor. When the target bandwidth is small such as
a few hertz, and thetargetspeed is high such as 60 RPS,
the model approximates acontinuous system fairly well.
Resolution and Tolerance
The resolution of the speed control circuit is entirely
determined by the digital clock rate used decrementing
the period counter. When SYSCLK is 2 MHz in the
SSI 32M7010, the period counter is clocked at
500 kHz. Due to sampling uncertainty, there is an
inherent plus or minus one count of error. Since one bit
is .012% at3600 RPM, the total envelope of uncertainty
is specified as 0.036%.
Regulation tolerance is a function of the entire system.
The resolution of the speed control circuit is very small
compared to the system variables such as bearing
friction, changes in load such as when seeking, jitter in
the speed indicator, and powersupplyvariation. Setting
the speed control loop compensation effects the
dynamic response to changes in speed and ultimately
determines how quickly the loop settles.
The programmed load count is 6 less than the value
found from CountTOTAL . This difference of 6 is due to
internal digital delays, therefore the final load value is
5494. The bits setting the number of poles are MO and
M1 in register 1 of the SS132H6820. Forthis particular
example, set MO=O and M1=1 for 12 pole operation.
The hexadecimal equivalent of 5494 is 1576H. Register
3 should be written with hexadecimal 76H followed by
15H for register 4.
Speed LOCK Indication
The three MSC components supporting internal speed
control provide a speed LOCK pin. This indicator is
asserted high when the period measurement is within
+-15 counts or±0.2%ofthetargetspeed. LOCK can be
used as an indicator that the motor has spun up to
speed from startup. In has a fairly wide tolerance which
minimizes its sensitivity to brief speed error. The falling
edge of LOCK could serve as an interrupt source
though polling may be better.
Using an External Speed Indicator
Provisions exist in the three MSC devices with internal
speed control to accept an external speed indicator.
This speed indicator should transition once per indicated
revolution. The devices transition to the external Signal
in slightly different ways:
DEVICE
SELECTION METHOD
SSI32M595
Assert INDXSEL and apply
speed signal to INDXlCOMMU
pin
Programmable Speed Control
SSI32M7010
The SSI32H6820 offers programmable speed control.
Register addresses 3 and 4 hold the period counter
value which is 15 bits in width. This counter is clocked
at 500 kHz just like the SSI32M595 and SSI32M701 o.
Assert INDXSEL and apply
speed Signal to INDXlCOMMU
pin
SSI32H6820
Program INDX_SEL bit in
register 0 and apply speed
signal to EXT INDX
As an example, consider a 12-pole motor intended to
run at a target speed of 5400 RPM. In this design
example, the following parameters are computed:
RPS = 5400 = 90 revs/sec
60
1
ms
f rev =--=11
RPS
rev
f
Countlalal
= 2. ~O-6 = 5500 counts
External speed indication may be attractive in some
designs to enhance speed control tolerance. In normal
Internal mode, the speed indicator is derived from the
BEMF zero crossings. By dividing the zero crossings
by the number of commutations per revolution, the
same zero crossing is always used. Even so, there may
still be some inherent uncertainty in this analog event.
By taking a signal from the digital servo timing ASIC in
a hard disk drive, the speed indication jitter can be
greatly minimized. When an external speed indicator is
13-151
II
Sensorless Motor Speed Control
Using an External Speed Indicator
SSI 32H68l2 Speed Control Model
(continued)
used, BEMF crossings are initially used to spin up and
stabilize the motor. Then once LOCK is found, the
microprocessor will transition to the external indicator.
Figure 10 provides a small-signal block diagram of a
speed control system based on the SSI 32H68l2.
The model below references the following parameters:
Increasing Spindle Bandwidth
The SSI 32H6820 provides programmable speed
control. When programmable speed control is used
with the external speed indicator, it is possible to
change sample rates under microprocessor control.
Changing samples rates could be implemented by
using the once-per-revolution signal derived from the
BEMF zero crossings during spin up and initial speed
control; then transition to the external speed indicator
with a higher sample rate and corresponding smaller
value in the programmable speed count registers.
Changing sample rates has the disadvantage of having
non-optimum compensation in one olthe control modes.
An alternative to changing the sample rate is to externally
derive a speed indicator from the commutation event
signal REVCOM. This design would divide the R EVCOM
signal (either REVCLK or COMMU which is
programmable) by a value which would correspond to
a signal which could be derived from the servo timing
ASIC. In this way, spinup and initial lock would be
established using a signal actually derived from the
BEMF crOSSings but made to look like the signal which
will later be generated from the data head. When speed
lock is established, the external speed indicator would
be switched to the real head signal. This method would
allow more samples per revolution and thus lend itself
to higher speed control bandwidths.
Parameter
Target Speed
Kc
Kpmp
H(s)
Ka
5400 RPM
Speed error in counts/rad/sec
Pump circuit in:
seconds/count· amp/seconds
Impedance of loop filter
Transconductance gain in
amps/volt
Motor model with:
Kt - torque constant of motor
J - inertia of motor/load
Kt/(sJ+B)
B - friction
These model parameters above are computed as
indicated below:
K
c
5555 counts
1 rev
== 5555 counts • ---==----90 rev/sec
==
K
pmp
2*10-6 sec
count
l80n: rad/sec
.
60'10-6 amp
---'-c.,--_---'-
~O sec
so that
K pmp ==1.08.10-9
SSI 32H68l2 Charge Pump and Loop Filter
2n: rads
and
amp
count
Only the SSI32H6812 implements a charge pump and
loop filter for speed control. A charge pump consisting of
a current source of amplitude proportional to speed error
charges or discharges the voltage across the loop filter.
A second order discrete filter consisting of two capacitors
and a resistor configure the compensation filter.
Target
speed
speed
5400 RPM
Figure 10. SSI32H6812 Small Signal Speed Control Model
13-152
Sensorless Motor Speed Control
SSI32H6812 Speed Control Model
Design Example
(continued)
The transconductance gain of the power amplifier is
determined by both the sense resistor and sense
amplifier gain setting programmed through the serial
interface. Sense amplifier gain settings Of 5,10,20, and
30 are programmable. The power amplifier gain is
computed from:
K =_1_
a
In a particular application, the filter components were
chosen as follows:
R = 300 K
C1
= 0.1 ~Fd
C2 = 1.0 ~Fd
which yielded corner frequencies of:
G.Rs
where G is the sense amplifier gain and Rs is the sense
resistor.
Loop Filter
The loop filter presents an impedance through which
the charge pump current source is forced. Figure 11
illustrates the components making up this filter.
The voltage developed across this filter serves as the
current command amplified by the transconductance
power amplifier. H(s) is found to be:
fz = 0.5 Hz and fp
= 5.8 Hz.
For this particular example, the constant parameters
were lumped together forming a term "g" below and the
friction B was assumed to be zero.
g = kc • kp • ki • ka • (kt/J)
g = 7.345. 10-5
The modeled open-loop gain was plotted below where
GH(s) was defined to be:
GH(s) = g • H(s)
From the open-loop gain plots, the Odb cross-over
frequency for this particular example is approximately
three hertz while the phase margin is approximately 53
degrees.
Charge pump
Figure 11. Loop Filter
H(s) =__
1_.
s-r+1
C1+ C2 s(sk-r + 1)
where
and
k=~
C1+C2
The transfer function offers a "pole" at the origin which
provides the integration necessary to implement a type
1 system. The numerator of H(s) provides the "zero"
which is adjusted to achieve necessary phase margin.
The parameter k will always be less than 1 so that the
pole time-constant in the denominator will less than the
zero. The corner frequencies determined by kand"t are:
1
'z = -m
2
j,
1
and fp = 2-1.~
/1.1<.,
13-153
I
Sensorless Motor Speed Control
hili
40
I
20
~~
I~ i"'o roo,.
I
o
I
I
I
I
I
~~I~
-20
I
I
-40
I
I
I
I
I
0.1
i
...... '-....
I
I
I
I
I
I
I
I
II
I
~
~ ... f'-o ....
I
I
10
Figure 12. GH(s) Open loop Gain Plot
230
r-
220
r-
(f) 210
r-
10
Figure 13. Open loop Phase Plot
13-154
Sensorless Motor Speed Control
External Speed Control
System Operating Specification
When motor speed is externally controlled, the MSC
component is responsible only for commutating and
providing a transconductance amplifier for motor current
control. The control signal itself is externally generated
by some device designed to compare actual speed with
the target speed and generate a compensating current
command to make the necessary speed correction.
The system operating specification consists primarily
of rise time, settling time, and percentage overshoot
design goals. Various techniques and approximations
existfortranslating these transient system specifications
into the frequency domain such that the open-loop
phase and gain margins can be specified.
Characterize The Uncompensated System
This section provides two digital speed control design
examples. The first is implemented using the Silicon
Systems digital signal processor named the
SSI32H6830 SE EKE R@. The second is based on an
80C51 microcontroller. It is natural to implement speed
control with a microprocessor or DSP since the startup
method discussed earlier relies uponan external digital
device.
Digital Design Approach
This design example will employ a PI compensator.
Both proportional and integral error components will be
generated and then summed together to form a
composite correction current command. This speed
control compensation is determined by two gain terms
identified as Kp and Ki denoting the proportional and
integral gains. These gains are chosen by analyzing
the Bode plot of the uncompensated system and
choosing values such that the compensated system
will meet the target specifications.
This design example approaches the problem in the
following steps:
Digital Speed Control Model
2. Characterize the uncompensated system
The small signal digital speed control model is illustrated
in Figure 14 below. The motor friction term typically
referenced by the symbol B is assumed to be zero.
3. Compute compensation to satisfy system
specification
The open loop transfer function for this model is found
to be:
1. System operation specifications
4. Implement speed control algorithm
5. Evaluate system performance
Targ et Speed,
Spindle
Velocity
RAD/SEC
377
RAD/SEC
Figure 14. Small Signal Digital Speed Control Model
13-155
II
Sensorless Motor Speed Control
Digital Speed Control Model
(onlinued)
In the transfer function T(s) above, some parameters
are more difficult to determine than others. The ratio
K/J is dependent upon the motor and load conditions;
Klach ' Ka, and Kdac are electrical and are. easily
determined. This particular design approach lumps all
these factors together through charaCterization so that
individual parameter specification is not necessary.
This approach is therefore somewhat empirical and
requires the uncompensated system to exist and be
characterized.
Set Kp to 1 and Kj to 0 to obtain the uncompensated
system response. In some cases, Jt is necessary to
have more gain in the loop for stable and sufficient
uncompensated operation. In these low gain cases,
increase Kp as necessary but maintain Kj at O. Use the
test value for Kp as reference, and compute the required
change in gain relative to this reference.
Computing Compensation
The PI compensator is:
K.
(jw oKp +
K+-1..=
p
jw
jw
System Characterization
System characterization is made possible by breaking the
uncompensated control loop with the circuit shown in
Figure 15. This popular technique allows the
uncompensated system to continue operating while a
disturbance signal is added for system evaluation. Note
that the magnitude and phase of the error signal is
unaltered and is summed with an external disturbance.
The system open loop gain GH is found as the ratio below:
KJ
From the uncompensated open-loop Bode plots, the
necessary compensator gain and phase shift can be
determined. Equating this gain Av and phase shift 8
to the compensator elements yields two conditions:
Condition 1
GH = Error Signal
VIN
Condition 2
Error
Signal
w
>--I--VIN
K )
E> = Tan-1( ~
0
-
90 degrees
+
Rearranging each condition so that soluti.ons for Kp and
Kj are found yields the design equations:
. Disb.nbance .
Figure 15. Breaking the Loop for Open Loop
Gain Testing
The uncompensated system is characterized by
introducing a disturbance signal with a magnitude
which is small such as 10% of the steady state error
signal, and sweeping the disturbance over a suitable
range such as 100 mHz to 10Hz. The idea is to select
values for Kp and Ki so that at the compensated openloop gain crossover frequency, the loop gain is equalto
1.0 (0 dB) with the required phase margin. A Bode
magnitude plot of the uncompensated open-loop
response will indicate how much gain must be added to
reach the desired crossover frequency. Examination of
the phase plot indicates the necessary phase shift to
achieve the specified phase margin.
and
13-156
K.=
•
woK
p
Tan(E> + 90)
Sensorless Motor Speed Control
Design Example
This PI compensation method is illustrated in the
following example. The compensation method is digitally
implemented with a sample rate of 78 Hz. The sample
rate is important when computing the real value of K j as
will be shown later.
The motor and load system was characterized by
sweeping the disturbance over the frequency range of
100 mHz to 10 Hz. The value of K was set to one.
Figure 16 shows the uncompen;ated open loop
response. Note that zero degrees on the plot is actually
180 degrees phase delay. This means that actual
phase shift is 180-76.65 or 103.35 degrees at 2 Hz
For a 2 Hz cross-over frequency, we require
25.5 dB (18.33 VN) of Av gain. Choosing a design goal
of 45 degrees of phase margin, the compensator
phase shift will need to add an additional phase shift of:
For Kp ' the representation is found using the equation
above to be:
31948 == 15.6 • 211>-1 which is 07CCCH
16
The value for Kj must be further processed by taking
into account the update rate of the digital integrator.
The computed value of Kj must be divided by the
sample rate yielding:
K·
'real
K·
= - - ' - where Fsample is the sample rate
Fsample
so that
K.
'real
9 = 135-103.35 or 31.65 degrees.
18.332
With the computed compensation, the open-loop system
performance was evaluated and is plotted in Figure 17.
As the plot indicates, the gain and phase-margin are
very near the design targets. Since the sample rate to
bandwidth ratio is 36 in this example, the digital
compensator is a fair approximation of a continuous
time solution. Errors between the target and actual
performance can be traced to the digital compensator
sampling effect introduced by the use of the numerical
integration "backward" rule, fixed point computational
limitations, and system noise.
=15.6
(1+ Tan (901-31.65) J
2
and
K. =
I
2· 2n· 15.6
Tan(90 - 31.65)
120.8
The values for Kj and K are represented in digital
format as 16-bit, fixed-~oint binary code. In the
SSI32H6830 SEEKERII!l DSP, K will be represented
as 7CCC hexadecimal where the decimal point is
between bits 11 and 10 (considering the LSB as bit 0
and the MSB as bit 15). This decimal point placement
is achieved in the SEEKERII!l by using the RADIX
instruction with an argument of 4. Effectively, the
RADIX 4 instruction informs the multiplier to treat Kp as
a signed number with a range of ± 16. The binary
representation is found as follows:
representation
78
Representing Kj in hexadecimal using the RADIX 4
instruction yields a hexadecimal value of OC66H.
Applying the design equations for Kp and Kj yield:
Kp=
= 120.8 = 1.55
Speed Control Algorithm
Difference Equation
The digital compensator implemented in this example
was derived by applying the backward rule as an
approximation of H(s) by H(z):
z-I
s ';= - - where T is the sample period
T· z
This translates:
K.
T· z
H(s)=K +-l!l!. intoH(z)=Kp+Km.-P
s
z-I
value of constant • 2 bitr-l
full scale range
13-157
II
Sensorless Motor Speed Control
r-----------~~----~------------~--~~_,180deg
10 dB
-10 dB
odeg
-30 dB
-50 dB
-70 dB
~~
______~__~~__~________~----~--~
10 Hz
1.0 Hz
0.1 Hz
-180d~
Figure 16. Uncompensated Open-Loop
50dB
~------------------------~--~----------~180deg
30dB
Odeg
10 dB
-10dB
-30 dB
L...;._ _ _' " - -_ _ _ _ _ _--"-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
0.1Hz·
-180 deg
10Hz
1.0Hz
Figure 17. ColTlpensated Open-Loop
Rearranging so that the z terms appear as powers of
-1 yields:
and solving for y[k] in the time domain by recognizing
that Z·l is the z domain delay operator as in:
Y[z]~
y[k]
and
VIz] •
where Kj above is the "real" Kj computed earlier as
Kireal which is the same as Kint multiplied by T.
Z·l ~
y[k-1]
finally yielding the difference equation:
Expanding H(z) yields:
y[k] = K.Il • (x[k] -'-.x[k -1]) + Ki • x[k] + y[k -1]
1-z-1 + K~
I K
H{z) = Y{z) = K
X{z)
p
p
l-z
1
13-158
Sensor less Motor Speed Control
SEEKERGD PI Code Example
The SEEKERGD firmware used for the example digital speed control compensator is given in listing 2. This
firmware runs on an SS132H6830 SEEKERGD DSP. The SEEKERGD has an instruction execution time of 50 ns
except forthe multiplier which completes in 200 ns. The device has separate ALU and multiplier functional units
so in some instances, a NOP is required to synchronize internal pipeline delays and data flow. There are no
immediate memory operations, all constants come from data RAM. The data RAM is 16-bits wide while the
instructions have short 10-bit and long 20-bit forms.
Data references are both to general purpose RAM and to special functions. General purpose RAM references
include those that are variable and those that are constant. Constants are just variables which don't change. LIMIT
is an example of a constant while EO is a variable. The reference "pTime" is a special function register which
measures the period of one revolution with a bit resolution of 1.6 IJ.S. DAC2 is the reference name for the 2's
complement 10-bit DAC used to command motor current.
listing 2. SEEKERGD Speed Control
;Entry point to speed control firmware
;The example sample rate was 78 Hz
LD pTime IFI
NOP
JF OVERFLOW IFI
JMP GETERROR
;Read period counter and put MSB into Fl
;pipeline delay unique to the SEEKER
;branch if period is 8000H for overflow
;no overflow, compute speed error
OVERFLOW:
LD.L MOSTPOS
;limit period counter to max pos number
;MOSTPOS is data location with 7FFF
GETERROR:
;accumulator has valid period error now
SUB.L TGTSPEED
NOP
Sto EO If2
;e(k)
=
revolution period - target period
;save elk) in variable EO, sample MSB
;and put sign of error into F2
Perform switch based on speed error.
If too slow, assert
maximum DAC voltage for maximum motor current command
Also, reset integrator.
If above this minimum speed threshold,
operate in linear control mode.
Note that F2 holds the sign of speed error e(k). If F2 is
true, then elk) is negative and the motor is too fast.
JF LIN MODE IF2 ;If too fast, stay in linear mode
;and slow down by friction
Otherwise, elk) is positive, compare to switch threshold
SUB LOW_SPEED IFI
; LOW_SPEED is the threshold to switch
NOP
JF LIN MODE IFI ;Above the minimum speed so use
;linear control
13-159
II
Sensorless Motor Speed Control
Listing 2.
SEEKER® Speed Control
(continued)
; Force the DAC to most positive value when too slow
LD MOSTPOS
STODR DAC2
;Copy directly to the MSC DAC
STOP
;Work all done, wait for next sample
Linear mode velocity error computation
LIN MODE:
ld EO
;Get error e(k)
Sub.l E1
;Compute e(k)-e(k-1)
nop
Sto.l Error
;Save value in temp location for multiply
Radix 4
MId Error Kp
Madd EO Ki
Stodr E1
Add.l Y1
nop
Stosat Y1 /F2
;Select RADIX 4 in Kp or Ki representation
;Compute Kp(e(k)-e(k-1»
;Compute Kp(e(k)-e(k-1»+Ki*e(k)
;Overlap Madd by updating e(k-1)=e(k)
;Y(k)=Kp(e(k)-e(k-1»+Ki*e(k)+Y(k-1)
Ld Xl
;Load saturated version of correction Y(k)
;Update Y(k-1), use saturation, F2 is sign
Map the computed result to the 10 bit DAC, perform limiting
JF CheckDwn /F2 ;If negative, check if too negative
JMP CheckTop
;Else check if too positive
nop
CheckDwn:
;Test is too negative
add LIMIT
;LIMIT is a variable fixed at 512
nop
JF fixbottom /F2;Too negative so limit at -512
Jmp output
;Value is ok, output as is
nop
FixBottom:
ld.l MOSTNEG
;MOSTNEG is a constant of 8000H
stodr dac2
;Output limited value to DAC
Stop
;Work all done, wait for next sample
CheckTop:
sub.l LIMIT
nop
jf Output /F2
jmp FixTOp
FixTop:
ld MOSTPOS
stodr Dac2
Stop
Output:
Lds Tmp /shl=6
nop
stosat DAC2
STOP
;Test if too positive
;LIMIT is a variable fixed at 512
;Value is OK, output as is
;Too positive, limit at +512
;MOSTPOS is constant of 7FFF
;Output limited value to DAC
;Work all done, wait for next sample
;Output the error command to DAC
;Shift result up to map into 10 bit DAC
;Write to DAC using saturation
;Work all done, wait for next sample
13-160
Sensorless Motor Speed Control
"C" Code Speed Control Example
This section provides a "C"language speed control example which is called by the assembly language REV_INT
interrupt handlerin listing 1. This speed control example was implemented on an 80C51 microcontrollersupporting
an SSI 32H6811.
Listing 3. Speed Control
II
Definitions and explanations concerning constants used later:
II
II
At 8 MHz, REVCNT period should be 7407 counts for 5400 RPM,
minus 10 counts for interrupt handler overhead *1
#define TARGET (7407 - 10) II This is the target compared later
II to the measurement in REVCNT var
#define KP «signed char)85)
#define KI «signed char)36)
II
PI coefficents
#define USEC(a) «unsigned int) «a)/1.5))
II uS -> int val
#define abs (a) « (a) >0) ? (a) : - (a))
I I absolute value
II The following include
#define VCM OxOe 1* VCM DAC is reg 0*1
#define MSC Oxle 1* MSC DAC is reg 1*/
#define MODE Ox2e 1* MODE register is reg 2*1
II bit masks used in C code below
#define REV Ox8000 II COM/REV* bit is 1 for REVCLK
#define M SHIFT 12 II shift code to access M bit field
#define N SHIFT 10 II shift code to access N bit field
#define DAC SHIFT 6 II shift code to access both DAC fields
#define GAIN 30 0
II code for sense gain of 30
#define GAIN 20 Ox80
II code for sense gain of 20
#define GAIN 10 OxlOO II code for sense gain of 10
#define GAIN 5 Ox180
II code for sense gain of 5
#define UNI Ox200
II code enabling unipolar mode
#define SWON Ox40
II code turning on analog switch
1* sys_status flags [routine responsible for setting/clearing] */
#define MOTOR RUN OxOl 1* motor should be running
[start_motor, brake_motor] *1
#define MOTOR START
Ox02 /* motor starting [start_motor] *1
#define MOTOR STALL
Ox04 1* [watchdog interrupt] *1
#define MOTOR RACE
Ox08 1* motor racing (probably stalled
and oscillating) *1
#define MOTOR LOCK
OxlO 1* motor speed within 15.55 RPM
of target */
13-161
II
SensorlessMotor Speed Control
Listing 3. Speed Control
(continued)
II Maximum period error for motor lock is 32 uSec (15.55 RPM)
*define LOCK USEC(32)
II macro used to return int for 32uS
II
Implement
yl=kp(xl-xO)+ki(xl)+yO
signed char xO;
short int yO;
II
II
xO is previous error, xl is current error
previous correction, yl is next correction
void speed control (void)
{
1* Called by REV INT interrupt handler servicing REVCLK.
Mustn't do anything that depends upon interrupts being enabled!
Because interrupts are disabled during this functions
execution, we can save time by manipulating sys status
directly. *1
-
II
II
II
long int t;
short int xl;
short int yl;
used to check if period is too long
xl is current error
next correction to be computed below
1* compute period error *1
t = «unsigned short)revcnt - TARGET);
xl = (t > 32767)
? 32767
: t;
II
limit error to 16 bits
1* check for speed lock *1
if(abs(xl) < LOCK)
( II Yes, in lock
sys status 1= MOTOR_LOCK;
) else
{ II No, out of lock
sys status &= -MOTOR_LOCK;
I
-
1* at 8 MHz, REVCNT period should be 7407 counts for 5400 RPM,
compensator output *1
1* saturate output when we are far from being locked *1
if(abs(xl) < 63)
{ II linear region so compute correction
II In this particular implementation, scaling has been
II implemented for numerical reasons. The shifting
II below is part of this scaling along with lumped
II scaling in Kp and Ki factors below:
yl = (KP*«signed char)xl - xO) + KI*xl + (yO«4»»4;
II saturate correction value
if (yl > 511)
yl = 511;
II 10 bit DAC positive limit
if (y1 < -512)
y1 = -512;
xO = xl;
II
II
II
10 bit DAC negative limit
update previous error term
In this particular example, the run gain must be 10
I REV 1 GAIN_10 I (l«N_SHIFT»;
send~acket(MODE
13-162
1* calculate
Sensorless Motor Speed Control
else
{ II error too large so saturate as needed
if(xl > 0)
{ II much too slow, apply maximum positive correction
yl
511;
xO = 63;
}
else
{ II much too fast, apply minimum correction
yl = -512;
xO = -64;
}
send~acket(MODE
REV I GAIN_5
(l«N_SHIFT));
}
1* update the DAC *1
send~acket(MSC
yO = yl;
I (yl«
DAC_SHIFT));
II update previous correction term
}
Disabling On-Chip Control
For the devices having internal digital PI speed control
such as the SSI 32M595, SSI 32M7010, and
SSI32H6820 an automatic switch is made from startup
mode into linear control. This modal switch is based on
the motor being within 3% of the target speed. In all
devices, this switching can be defeated by fooling the
component. Thiscan be performed by selecting external
speed indication mode and providing a signal at the
INDX pin such as SYSCLK itself. With the switch mode
disabled in this way, the VIN pin will always be selected
as the command for motor current.
the positioner motor by acting as a voltage sourcewhile
the spindle motor free spins using the generator action
of the motor itself. Figure 18 illustrates this function.
...........1--........-0
VBEMF
RETRACT AND BRAKING THE MOTOR
In hard disk drives, the spindle driver is responsible for
providing voltage to the positioner during power fault.
This voltage is necessary so that the positioner can
implement a head retraction. The voltage from the
spindle is full-wave rectified and presented to Silicon
Systems components at the VBEMF pin.
BEMF generation
BEMF voltage is full-wave rectified by the spindle
driver. In designs using external power MOSFETs,
kick-back protection diodes inherent in PIN channel
MOSFETs can be used to perform this function. The
lower N channel diode routes current from ground,
through the sense resistor, through the diode, and back
into the negative going motor winding. The upper P
channel diode connects the positive going motorwinding
to the VBEMF point. This VBEMF source now powers
Figure 18. Generation of VBEMF for Retract
In integrated power devices like the SS132H6810A, the
spindle drivers are stacked N channel MOSFETs. The
lower diodes are built into the package. It is necessary
to add three external diodes from each motor terminal
to the common VBEMF point. The upper N channel
MOSFET in the Silicon Systems components do not
have the parasitic diode always found across P channel
drivers. This design eliminates the need for blocking
diodes as well.
In most designs, the diodes in the SSI 32H681 OA or
external MOSFET drivers will be sufficient. If the drop
across them is too great, however; it may be necessary
to add Schottky diodes in parallel with the integrated
diodes. It may be beneficial to connect the motor
windings to VBEMF with Schottky diodes.
13-163
II
Sensorless Motor Speed Control
Blocking Diodes
POWER DISSIPATION CURVES
A blocking diode is necessary only when external
MOSFET drivers are used. This need arises from the
fact that the upper P channel MOSFET has an inherent
parasitic diode. This upper diode can be used to complete
the set necessary for full-wave rectification of spindle
motor but only when the cathodes of these diodes are
isolated from the power supply. For this reason, a
"blocking" diode isolates the power supply (which will be
dropping) from the VBEMF point. This has the
disadvantage of requiring a component and reducing
the voltage available to the spindle motor by the drop
across one diode. Figure 3 shows the blocking diode
and how it isolates VBEMF from the supply voltage.
Data sheets for Silicon Systems' devices with integrated
power drivers for spindle or servo motors have typically
specified drive capability in two ways. These two drive
specifications are "ABSOLUTE MAXIMUM RATING"
and "RECOMMENDED OPERATING CONDITIONS."
The absolute maximum rating is a maximum current
such as 1A beyond which the component may be
damaged. The recommended operating condition is
intended to suggest a typical current amplitude. In fact,
the recommended operating condition is of very little
use since it does not reflect power dissipation versus
time. A spindle motor draws considerable current when
starting then drops off while running. Silicon Systems
is now providing power dissipation curves for many of
its integrated power devices. Power dissipation curves
provide answers to "how much current can the device
deliver" based on the time duration and ambient
temperature expected.
Dynamic Braking and Free Spin
Most MSC family components have a controlled brake
feature; the SSI32H6812 does not. This feature allows
the MSC operation to behave in two ways in response
to a power failure. These modes of operation are
determined by the voltage on the BRAKE pin. When
BRAKE is above a voltage threshold, the spindle motor
will free-spin during power fault. When the BRAKE
voltage is belowthis threshold, the circuit will dynamically
brake the motor. Figure 19 illustrates this bimodal
braking operation.
This braking feature is intended to be used with an
external RC network which provides a programmable
free spin to brake delay. If an RC network is connected
so that the resistor is from SYSRST (an open drain
reset signal available on Silicon Systems' positioner
components) to BRAKE, and a capacitor connects
BRAKE to ground, then the time taken for the brake
capacitor voltage to decay below the threshold
determines the free spin delay.
Normal
Freespin
Brake
-
In any application, power will be dissipated in the motor
loads, the sense resistors, and the drivers. Figure 20
illustrates the approximate power dissipation curves
for the SSI 32H6810A (this figure is only an
approximation, please request the full page plot for
actual analysis). The vertical axis of the power curves
is power dissipation in watts inside the SSI32H6810A
only. The horizontal axis is ambient temperature. The
power curves consist of a family of individual test
conditions; each test condition represents a different
time duration of power dissipation.
In a hard-disk drive, power diSSipation is not constant.
The power dissipation during startup is greatest and
then drops to a fairly small constant value while running.
The VCM dissipation is very much dependent upon
seek activity and is usually very small while track
following. Because of the differences in power
dissipation based on operating conditions, it is best to
isolate operation into particular modes. Example modes
are listed in the following:
FAULT
V\/\ '\/\./\.7'\.'>0
Threshold
Figure 19. Bimodal Braking Operation
13-164
Sensorless Motor Speed Control
Operating Modes
MODE
CONDITION
Startup
Peak 1A start current, dissipation
primarily in spindle driver resistance
for a few seconds
Seek
Small spindle run current typically
100 mA along with peak VCM currents
possibly as high as 500 mA
Track
Small spindle run current ypically
100 mA along with small VCM
currents varying in time typically with
average of 50 mA (measured at
IWMPpin)
Fault
triggering the over-temperature shut-down circuit.
Seeking is an application sensitive activity; even so, the
power curves indicate that the drive could seek
indefinitely out to an ambient temperature of 60 or 70°C.
Many data sheets may not yet include power curve
information. Please contact Silicon Systems' Servo/
MSC applications forthis information if you don't already
have it.
p
6
watts
4
Retract current holding VCM in
position and typically under 50 mA
2
Operating mode power dissipation can be computed
using the simple equation:
p = [2 • R
infinite
o
20
40
60
80
100
120
'C
Figure 20. Power Dissipation Curves
where P is power, I is current, and R is resistance. For
each mode, power dissipation can be computed (not
counting the worst case 100 mW dissipation in other
circuits such as bandgap, digital, and misc analog) as
tabularized in the example below for spindle resistance
of 1.7 and VCM resistance of 2.50:
MODE
DISSIPATION
Startup
1.7 walts (12 • 1.7)
Seek
642 mW [(0.1 2 • 1.7)+(0.52 .2.5)]
Track
23 mW [(0.1 2 • 1.7)+(0.052 • 2.5)]
Fault
6mW
Clearly in this example, startup is the most demanding
operating mode. Looking at the power curves in Figure
20 show that the startup conditions can't be asserted
indefinitely since the infinity curve intersects the vertical
axis at less than 1.7 watts. The ten-second duration
curve is very near 1.7 walts but this plot does not give
sufficient resolution to precisely determine where its
intersection is. The two-second curve intersects at
approximately five watts and is well above 1.7 watts
through 90°C. The plots show that the peak start current
of 1A can be dissipated for nearly 10 seconds without
Silicon Systems. Inc., 14351 Myford Road, Tustin. CA 92680-7022 (714) 573-6000, FAX: (714) 573-6914
©1993 Silicon Systems, Inc.
13-165
1293
Notes:
13-166
Snubbing Network Design
for Spindle Motors
Silicon Systems 32M595, 32H4631
'4 U." tiii t.h' ~ Mg
The use of an RC snubber network placed across each
winding of a three-phase brushless motor may be
beneficial in reducing the switching EMF and acoustic
noise of the motor. Further, use of the snubber is
generally required when applying the SSI 32M595 or
32H4631 in systems using 12 volt unipolar (HALFWAVE) drive modes. Use of snubbers in the unipolar
drive mode reduces the amplitude of the switching
transients which can be as large as 20 volts. When the
individual motor phase and snubber circuit is considered as a simple L-R-C circuit, the following design
approach may be taken to compute the necessary
snubber Rand C values.
c.
d.
Where 1: denotes the time constant of the
motor and snubber circuit and t is the time
allowed for this decay to occur. We can solve
for the necessary -(V1:) by:
Loge (1/1000) = -6.908
and since V1: = 6.908, and t=694 ~ec, then 1:
= 694e-6 + 6.908, which equals 100.5 ~ec.
1. DetermIne the necessary time constant for the
network.
The motor circuit and the snubbing network to be
added will be designed so as to create a second
order exponentially decaying step response. The
remaining amplitude should be a small value at the
time the next commutation zero crossing is expected to occur. Since the zero crossing occurs
roughly 1/2 of a commutation cell period after
commutation occurs (due to the chip intentional
commutation delay), one can calculate the allowable time for the decay and specify the snubbing
network by following through this example:
2. Computing the required snubbing capacitor.
a.
Peak amplitude of transient is 12 volts (12 volt
UNIPOLAR)
b. Die down to 1/1000 of initial transient in 1/2
commutation cell period. This will result in 12
mV remaining. The remaining transient voltage can alter the commutation angle. In a
typical unipolar application with a Kt (torque
constant) of 3.5 oz-in/Amp the magnitude of
the BEMF signal used for commutation when
at speed (assumes 3600 RPM) is 9.3 volts
peak. The amount of commutation shift, or
jitter due to residual transient voltage in
degrees of electrical angle is:
Angleshift = ± [SIN·1 (.012/9.3)] = .074'
Which is, of course, negligible.
0691
Decay period (1/2 the commutation cell time)
is 694 ~ec for a 4-pole motor at 3600 RPM.
Motor inductance is 3.5 mH, resistance is 70,
and torque constant, Kt , is 3.5 oz-inlAmp.
Knowing that the transient dies down exponentially as:
v= e(·th)
13-167
The motor and snubber circuit equivalent circuit is
shown in Figure 1.
Solving for the transient response at
RCS+1
v=
Lm C S2 +(R m + R)C S + 1
Where: Lm C = 1!w1l2 , and wll is the natural
frequency in radians, and (Rm + R)C = 2~Wll ' and
~ is the damping constant of the second order
characteristic equation which defines the time
constant,
1: = 1/(~Wll).
When critical damping is desired, as it is now, 1:
reduces to 1/ww
In our example 1: is 100.5e-6 sec, and in the
calculation Lm xC = 1/w1l 2 , therefore to calculate
C when Lm is known:
C=
1: 2
ILm.
In the example Lm is 3.5 mH, therefore C = (1 00.5e6)2/3.5e-3
C = 2.89 JlFd
II
Snubbing Network Design
for Spindle Motors
Silicon Systems 32M595, 32H4631
3. Computing the resistor.
Summary
The total resistance in the circuit determines the
damping factor. The characteristic equation has
(Rm + R) x C equaling 2 times the damping factor
divided by the natural frequency, wtt . The total
resistance for a damping factor of 1 (critical damping is desired) is: H(total) =(2 x 'C)/C
R(total) =(2 x 100.Se-6)/2.8ge-6
R(total)
= 69.7n.
This approach can be iterated to result in ~ more
common snubbing capacitor value by changing the
target time constant. Too much snubbing will cause a
shift in the zero crossing time resulting in poorer motor
performance. Further, the snubber may result in some
noticeable power and torque loss, but using this approach generally will yield good working values.
To find R (the snubbing resistor) the motor resistance is subtracted from the total resistance just
calculated:
69.7 - Rm( which is 7n), therefore:
R = 62.7n.
1:1
/~C
I
V
~
Figure 1: Motor and Snubber Circuit Equivalent Circuit
13-168
Setting Speed Control
Loop Compensation Gains
The speed control compensation is controlled by two
gain terms Kp and K;, the proportional and integral gains.
These gains are set by the selection of two resistors.
This document presents a method of determining those
two gains and then the resistor values. The derivation
of the gains will be shown by using the linearized block
diagram and the transfer function obtained from that
simplification. The amount of errorthatthis will introduce
due to the speed control being a sampled system is
within tolerable limits at most bandwidths necessary for
disk drive spindle applications. Of course the presentation ofthis method does nottry to indicate this is the only
way these gains may be determined, or even the best
way. It is one method only and the user may elect
another method that will best suit his needs.
This is where:
KA is the transconductance gain of the driver circuit
which is a function of Rsense ( see the respective part
data sheet).
KT is the motor torque constant. Use units that are
compatible with J such as oz-iniAmp and oz-insec2 , or newton-meters/Amp & Kilogram-meters2 •
J is the load rotating inertia. Use units that are
compatible with KT.
S is the Laplace operator.
Kp is the proportional gain calculated.
The simplified, linearized block diagram is seen in
Figure 1; the derivation of the open loop transfer
function is shown.
K; is the integral gain calculated.
REF 377
RAO/SEC ..
TRANSCONDUCTANCE
INERTIA
SIMPUFIED
REF 377
RADISEC ...
TRANSFER FUNCTION
OPEN LOOP TRANSFER FUNCTION
=
11.6 ~I ~t KT (1 + ·ii~~ S)
FIGURE 1: Motor Speed Control Linearized Block Diagram
0691
13-169
II
Setting Speed Control Loop
Compensation Gains
From the open loop transfer function the loop gain is:
Let some values be assumed as an example and solve
for the gains:
Let:
KA = 1.0 Amplvolt
KT = 3.5 oz-in/Amp
J = .0098 oz-in-sec2
BW= 1 Hz.
LG= 11.6K;KA KT (1+ .775Kp S)
J S2
11.6 K;
This can be expanded to:
LG= 11.6K;KAKT
J S2
+
KAKT .775Kp
JS
Ki = (.707 x .0098 x (21t1 )2)/(11.6 x 1.0 x 3.5) = .00674
The problem is to select values for Kp and Ki that will
allow the loop gain to come to 1.0 (0 dB) at the desired
bandwidth frequency; and with a phase margin of the
desired amount considering stability and performance
(usually 45 to 60 degrees).
Evaluate the loop gain at the bandwidth frequency and
calculate the unknown gains.
Where: LG = 1.0 at an angle of -135 degrees
(45 degrees phase margin)
S=jw
BW = desired bandwidth frequency in Hertz
w = 21tBW
Kp = (.707 x .0098 x (21t1))/(.775 x 1.0 x 3.5) = .016
These gains and assumed values can be put into the
loop gain equation and as a design verification a bode
plot can be made with SERVOCALC®, see Figure 2.
LG = 11.6 (.00674)(1.0)(3.5) (1 + .775 (.016) S)
(.0098) S2
11.6 (.00674)
In polynomial form:
LG(s) = 4.429 S + 27.923
S2
This polynomial is entered into the USER POLYNOMIAL module of SERVOCALC® and a Bode plot made.
As can be seen in the figure the 0 dB crossover is at 1
Hz and the phase margin is 45°.
Separate both sides of the equation into their real and
imaginary parts:
-.707, - j .707 =
-11.6 K;KAKT
. KAKT .775 Kp
J w2
,-J
Jw
Now thatthe gains have been calculated they need to be
set in to the Circuit with resistors Rp and Ri as in the data
sheet. Let the summing resistor be Ro from the Vin pin to
ground as on the data sheet; a suggested value is 10
KQ. Solving for the resistors in the general case:
The real part can be solved directly for Ki and the
imaginary part for Kp:
-.707 =
Rp =Ro
(~
Kp
R; = Ro ( 1 - KK p
-116 KKK
.707 J (2nBW)2
.
; A T solving: K; = _.,....,..-:,...,-'---:-:----'_
J (2nBW)2
11.6 KAKT
-1)
-
1)
I
And solving for our example case:
_j .707 = _ j KA KT .775 Kp solving: Kp = .707 J (2nBW)
J (2nBW)
.775 KAKT
Rp= 610KQ
RI = 1.45 MQ
13-170
0691
Setting Speed Control Loop
Compensation Gains
g dB20 dB.
."
• ..
~
+180°
.
~
o dB.
~
~
~
• ••
- ..
0
1°
iii::!'
!::iiiiii
I!!!!: !::iii ::iii
1
·20 dB.
2
3
4
5
6 7 8
10
20
Ii\!
30
~
40
iii!I ·180°
50 60 70 100
••••• FREQUENCY IN Hz ...... MULTIPLY BY FREQUENCY MULTIPLIER; .1
FIGURE 2: Open Loop Bode Plot
Silicon Systems. Inc" 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
0691
13-171
©1991 Silicon Systems, Inc,
Notes:
Notes:
Notes:
Silicon Systems, Inc.
Storage Products Division
14351 Myford Road , Tustin , CA 92680
Ph (714) 573-6000, Fax (714) 573-6914
© 1994 Silicon System s Printed in the U.S.A.
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