1994_Siliconix_Power_Products 1994 Siliconix Power Products
User Manual: 1994_Siliconix_Power_Products
Open the PDF directly: View PDF 
.
Page Count: 562
| Download | |
| Open PDF In Browser | View PDF |
Power Products Data Book
1994
Siliconix
A Member of the TEMIC Group
About Siliconix
Siliconix designs and manufactures semiconductor products that regulate and manage power supplies and
enable the digitally-operated microprocessor to interface with real-world analog signals. The company's
power transistors and integrated circuits are mainly used for power management and motion control in
computers, hard disk drives, automobiles, and telecom systems. The company's analog switches,
multiplexers, and low-power transistors are used to sense, switch, and route signals in video, multimedia,
instrumentation, and test equipment in both the industrial and hi-rei environments.
Siliconix provides products and technologies that directly answer the market's demand for smaller, more
efficient, and more cost-effective components. The company's LITE FOOT'" discrete power transistors
are the industry's most compact solution for motion control in hard disk drives and for load management
in portable computers. These miniaturized products can be mounted directly to the printed circuit board
and are the first such products thin enough to fit inside any standard PCMCIA card. Siliconix introduced
the first true surface-mount power transistor on the market with its LITILE FOOT® product line.
Besides computer and computer peripheral products, LITILE FOOT has been designed into telecom
systems, automotive air bag triggers, and numerous other applications where space-savings and efficiency
are at a premium.
Siliconix power integrated circuits combine interface circuitry with power functions. A family of regulator
and controller ICs designed for use with Ul lLE FOOT discretes offers the optimal level of intcgration
for dc-to-dc conversion in battery-operated equipment, including laptop and notebook computers. For
data storage customers the company has produced highly integrated chips for voice coil and spindle motor
control. New products include power ICs for computers equipped with dual battery packs or PCMCIA
slots, and power ICs for bus control in automobiles.
Siliconix is a member ofTEMIC, the microelectronics enterprise of AEGwithin the Daimler-Benz Group.
The company now shares the technologies and applications expertise of its sister companies and takes
advantage of a combined international sales network.
TEMIC
Siliconix
Table of Contents
General Information
Alpha-Numeric Index .............................................................................. i
About This Data Book ............................................................................ ii
Selector Guides ................................................................................ iii
LITILE FOOT® ............................................................................. iv
LITE FOOT'" ............................................................................... vi
Power ICs .................................................................................. vii
Power MOSFETs .............................................................................. ix
Power MOSFET Military Selector Guide ......................................................... xi
Ordering Information
Power Products Nomenclature .................................................................. xii
Section 1: LITTLE FOOT
Introduction
Si9400DY: P-Channel Enhancement-Mode MOSFET ................................................ 1-1
Si9405DY: P-Channel Enhancement-Mode MOSFET ................................................ 1-5
Si9407DY: P-Channel Enhancement-Mode MOSFET ................................................ 1-9
Si9410DY: N-Channel Enhancement-Mode MOSFET ............................................... 1-13
Si9420DY: N-Channel Enhancement-Mode MOSFET ............................................... 1-17
Si9430DY: P-Channel Enhancement-Mode MOSFET ............................................... 1-21
Si9433DY: P-Channel Enhancement-Mode MOSFET ............................................... 1-25
Si9434DY: P-Channel Enhancement-Mode MOSFET ............................................... 1-29
Si9435DY: P-Channel Enhancement-Mode MOSFET ............................................... 1-33
Si9925DY: Dual N-Channel Enhancement-Mode MOSFET .......................................... 1-37
Si9928DY: Dual Enhancement-Mode MOSFET (N- and P-Channel) ................................... 1-41
Si9933DY: Dual P-Channel Enhancement-Mode MOSFET ........................................... 1-47
Si9936DY: Dual N-Channel Enhancement-Mode MOSFET .......................................... 1-51
Si9939DY: Dual Enhancement-Mode MOSFET (N- and P-Channel) ................................... 1-55
Si9940DY: Dual N-Channel Enhancement-Mode MOSFET .......................................... 1-61
Si9942DY: Dual Enhancement-Mode MOSFET (N- and P-Channel) ................................... 1-65
Si9943DY: Dual Enhancement-Mode MOSFET (N- and P-Channel) ................................... 1-71
Si9944DY: Dual N-Channel Enhancement-Mode MOSFET .......................................... 1-77
Si9945DY: Dual N-Channel Enhancement-Mode MOSFET .......................................... 1-81
Si9947DY: Dual P-Channel Enhancement-Mode MOSFET ........................................... 1-85
Si9948DY: Dual P-Channel Enhancement-Mode MOSFET ........................................... 1-89
Si9950DY: Complementary MOSFET Half-Bridge .................................................. 1-93
Si9952DY: Dual Enhancement-Mode MOSFET (N- and P-Channel) ................................... 1-99
Si9953DY: Dual P-Channel Enhancement-Mode MOSFET .......................................... 1-105
Si9955DY: Dual N-Channel Enhancement-Mode MOSFET ......................................... 1-109
Si9956DY: Dual N-Channel Enhancement-Mode MOSFET ......................................... 1-113
Si9958DY: Dual Enhancement-Mode MOSFET (N- and P-Channel) .................................. 1-117
Si9959DY: Dual N-Channel Enhancement-Mode MOSFET ......................................... 1-123
TEMIC
Table of Contents
Siliconix
Section 2: LITE FOOT
Introduction
Si6433DQ: P-Channel Enhancement-Mode MOSFET ................................................ 2-1
Si6436DQ: N-Channel Enhancement-Mode MOSFET ................................................ 2-3
Si6447DQ: P-Channel Enhancement-Mode MOSFET ...............•................................ 2-5
Si6542DQ: Dual Enhancement-Mode MOSFET (N- and P-Channel) .................................... 2-7
Si6953DQ: Dual P-Channel Enhancement-Mode MOSFET ............................................ 2-9
Si6956DQ: Dual N-Channel Enhancement-Mode MOSFET .......................................... 2-11
Section 3: Power Conversion, PCMCIA Interface and Battery Management
Introduction
Si9100: 3-W High-Voltage Switchmode Regulator .................................................... 3-1
Si9102: 3-W High-Voltage Switchmode Regulator .................................................... 3-9
Si9104: High-Voltage Switchmode Regulator ........................................................ 3-16
Si9105: 1-W High-Voltage Switchmode Regulator ................................................... 3-24
Si9110/9111: High-Voltage Switchmode Controllers ............................. '" .................. 3-31
Si9112: High-Voltage Switchmode Controller ....................................................... 3-38
Si9114: High-Frequency Switchmode Controller .................................................... 3-44
Si9120: Universal Input Switchmode Controller ..................................................... 3-49
Si9145: Low-Voltage Switchmode Controller ........................................................ 3-55
Si9150: Synchronous Buck Converter Controller .................................................... 3-62
Si9710: PCMCIA Interface Switch ................................................................ 3-68
Si9711: PCMCIA Interface Switch ................................................................ 3-72
Si9717: Battery Disconnect Switch ................................................................ 3-76
Si9718: Battery Disconnect Switch ................................................................ 3-79
Section 4: Motor Control and MOSFET Drivers
Introduction
D469A: Quad High-Current Power Driver .......................................................... 4-1
Si991O: Adaptive Power MOSFET Driver ........................................................... 4-5
Si9961: 12-V Voice Coil Motor Driver .... " ................................... , ................... 4-10
Si9976: N-Channel Half-Bridge Driver ............................................................ 4-17
Si9978: Configurable H-Bridge Driver ............................................................. 4-22
Si9979: 3-Phase Brushless DC Motor Controller .................................................... 4-28
Section 5: Bus Interface
Si9241: Single-Ended Bus Driver .................................................................. 5-1
Si9243: Single-Ended Bus Driver .................................................................. 5-5
TEMIC
Siliconix
Table of Contents
Section 6: N-/P-Channel MOSFETs
Introduction
BUZ11: N-Channel Enhancement-Mode Transistor .................................................. 6-1
BUZ71/71A: N-Channel Enhancement-Mode Transistors .............................................. 6-5
BUZ171: P-Channel Enhancement-Mode Transistor .................................................. 6-9
IRF51O: N-Channel Enhancement-Mode Transistor ................................................. 6-13
IRF520: N-Channel Enhancement-Mode Transistor ................................................. 6-17
IRF530: N-Channel Enhancement-Mode Transistor ................................................. 6-21
IRF540: N-Channel Enhancement-Mode Transistor ................................................. 6-25
IRF9530: P-Channel Enhancement-Mode Transistor ................................................. 6-29
IRFD020: N-Channel Enhancement-Mode Transistor ................................................ 6-33
IRFD110: N-Channel Enhancement-Mode Transistor ................................................ 6-37
IRFD120/123: N-Channel Enhancement-Mode Transistors ........................................... 6-41
IRFD9020: P-Channel Enhancement-Mode Transistor ............................................... 6-45
IRFD9120/9123: P-Channel Enhancement-Mode Transistors .......................................... 6-49
MOD100B/100C: Four N-Channel Enhancement-Mode Transistors .................................... 6-53
MOD200B/200C: Four N-Channel Enhancement-Mode Transistors .................................... 6-57
MOD400B/400C: Four N-Channel Enhancement-Mode Transistors .................................... 6-61
MOD500B/500C: Four N-Channel Enhancement-Mode Transistors .................................... 6-65
Si8956AZ/883: Quad N-Channel Enhancement-Mode MOSFET ...................................... 6-69
SMD/SMUlOP05: P-Channel Enhancement-Mode Transistors ........................................ 6-73
SMD10P06: P-Channel Enhancement-Mode Transistor .............................................. 6-77
SMD10P06L: P-Channel Enhancement-Mode Transistor ............................................. 6-79
SMD/SMU15N05: N-Channel Enhancement-Mode Transistors ........................................ 6-83
SMD15N06: N-Channel Enhancement-Mode Transistor .............................................. 6-87
SMD/SMU25N05-45L: N-Channel Enhancement-Mode Transistors, Logic Level ......................... 6-89
SMD/SMU30N03-30L: N-Channel Enhancement-Mode Transistors, Logic Level ......................... 6-93
SMP20P10: P-Channel Enhancement-Mode Transistor ............................................... 6-97
SMP25N05-45L: N-Channel Enhancement-Mode Transistor, Logic Level .............................. 6-101
SMP30NlO: N-Channel Enhancement-Mode Transistor ............................................. 6-105
SMP40N10: N-Channel Enhancement-Mode Transistor ............................................. 6-109
SMP40P06: P-Channel Enhancement-Mode Transistor .............................................. 6-113
SMP50N06-25: N-Channel Enhancement-Mode MOSFET .......................................... 6-117
SMP60N03-10L: N-Channel Enhancement-Mode Transistor, Logic Level .............................. 6-121
SMP60N06-14: N-Channel Enhancement-Mode Transistor .......................................... 6-125
SMP60N06-18: N-Channel Enhancement-Mode Transistor .......................................... 6-129
SMW20P10: P-Channei Enhancement-Mode Transistor ............................................. 6-133
SMW45NlO: N-Channel Enhancement-Mode Transistor ............................................ 6-137
SMW60N06-18: N-Channel Enhancement-Mode Transistor .......................................... 6-141
SMW60N10: N-Channel Enhancement-Mode Transistor ............................................ 6-145
SMW70N06-14: N-Channel Enhancement-Mode Transistor .......................................... 6-149
SUB60N06-08: N-Channel Enhancement-Mode Transistor .......................................... 6-153
SUP/SUB50N06-18: N-Channel Enhancement-Mode Transistor ...................................... 6-155
TEMIC
Table of Contents
Siliconix
Section 6: N-/P-Channel MOSFETs (Cont'd)
SUP60N06-08: N-Channel Enhancement-Mode Transistor ...........................................
SUP/SUB60N06-14: N-Channel Enhancement-Mode Transistor ......................................
SUP/SUB60P06-20: P-Channel Enhancement-Mode Transistor .......................................
2N6849: P-Channel Enhancement-Mode Transistor .................................................
2N6851: P-Channel Enhancement-Mode Transistor .................................................
2N7075: N-Channel Enhancement-Mode Transistor ................................................
2N7076: N-Channel Enhancement-Mode Transistor ................................................
2N7077: N-Channel Enhancement-Mode Transistor ................................................
2N7078: N-Channel Enhancement-Mode Transistor ................................................
2N7079: P-Channel Enhancement-Mode Thansistor .................................................
2N7080: P-Channel Enhancement-Mode Transistor .................................................
2N7081: N-Channel Enhancement-Mode Transistor ................................................
2N7085: N-Channel Enhancement-Mode Transistor ................................................
2N7086: N-Channel Enhancement-Mode Transistor ................................................
2N7089: P-Channel Enhancement-Mode Transistor .................................................
2N7090: P-Channel Enhancement-Mode Transistor .................................................
2N7091: P-Channel Enhancement-Mode Transistor .................................................
2N7224: N-Channel Enhancement-Mode Transistor ................................................
2N7225: N-Channel Enhancement-Mode Transistor ................................................
2N7227: N-Channel Enhancement-Mode Transistor ................................................
2N7228: N-Channel Enhancement-Mode Transistor ................................................
6-157
6-161
6-163
6-165
6-169
6-173
6-177
6-181
6-185
6-189
6-193
6-197
6-201
6-205
6-209
6-213
6-217
6-221
6-223
6-225
6-227
Section 7: Appendix
Siliconix Faxback ............................................................................ 7-1
Application Notes . ............................................................................ 7-3
Reliability Report . ............................................................................ 7-5
Packaging Information ....................................................................... 7-9
Military Information ........................................................................ 7-20
Cross Reference ............................................................................. 7-23
Section 8: Sales Offices ...................................................................
8-1
General Information
.,. ,
TEMIC
Alpha/Numeric Index
Siliconix
BUZ11 ........... 6-1
Si9105 ........... 3-24
Si9948DY. . . . . . . .. 1-89
SMW60NI0 ....... 6-145
BUZ171 .......... 6-9
Si9110 ........... 3-31
Si9950DY ......... 1-93
SMW70N06-14 .... 6-149
BUZ71 ........... 6-5
Si9111 ........... 3-31
Si9952DY ......... 1-99
SUB50N06-18 ..... 6-155
BUZ71A ......... 6-5
Si9112 ........... 3-38
Si9953DY ......... 1-105
SUB60N06-08 ..... 6-153
SUB60N06-14 ..... 6-161
D469A ........... 4-1
Si9114 ........... 3-44
Si9955DY ......... 1-109
IRF510 ........... 6-13
Si9120 ........... 3-49
Si9956DY ......... 1-113
IRF520 . . . . . . . . . .. 6-17
Si9145 ........... 3-55
Si9958DY ......•.. 1-117
IRF530 ........... 6-21
Si9150 ........... 3-62
Si9959DY ......... 1-123
IRF540 . . . . . . . . . .. 6-25
Si9241 ........... 5-1
Si9961ACY ....... 4-10
SUB60P06-20 ..... 6-163
SUP50N06-18 ..... 6-155
SUP60N06-08 ..... 6-157
SUP60N06-14 ..... 6-161
IRF9530 .......... 6-29
Si9243 ........... 5-5
Si9976DY ......... 4-17
IRFD020 ......... 6-33
Si9400DY ......... 1-1
Si9978DW ........ 4-22
IRFDlI0 ......... 6-37
Si9405DY ......... 1-5
Si9979CS ......... 4-28
IRFDl20 ......... 6-41
Si9407DY ......... 1-9
SMDI0P05 ....... 6-73
IRFDl23 ......... 6-41
Si9410DY ......... 1-13
SMDI0P06 ....... 6-77
2N7075 ........... 6-173
IRFD9020 ........ 6-45
Si9420DY ......... 1-17
SMDlOP06L ...... 6-79
2N7076 ........... 6-177
IRFD9120 ........ 6-49
Si9430DY. . . . . . . .. 1-21
SMD15N05 ....... 6-83
2N7077 ........... 6-181
IRFD9123 ........ 6-49
Si9433DY. . . . . . . .. 1-25
SMD15N06 ....... 6-87
2N7078 ........... 6-185
MODI00B ........ 6-53
Si9434DY. . . . . . . .. 1-29
SMD25N05-45L ... 6-89
2N7079 ........... 6-189
MOD100C ........ 6-53
Si9435DY . . . . . . . .. 1-33
SMD30N03-30L ... 6-93
2N7080 ........... 6-193
MOD200B ........ 6-57
Si9710CY ......... 3-68
SMPZOPI0 . . . . . . .. 6-97
2N7081 ........... 6-197
MOD200C . . . . . . .. 6-57
Si9711CY ......... 3-72
SMP25N05-45L .... 6-101
2N7085 . . . . . . . . . .. 6-201
MOD400B ........ 6-61
Si9717CY ......... 3-76
SMP30N10 ........ 6-105
2N7086 ........... 6-205
MOD400C ........ 6-61
Si9718CY ......... 3-79
SMP40NI0 ........ 6-109
MOD500B ........ 6-65
Si9910 ........... 4-5
SMP40P06 ........ 6-113
MOD500C . . . . . . .. 6-65
Si9925DY ......... 1-37
SMP50N06-25 ..... 6-117
Si6433DQ ........ 2-1
Si9928DY ......... 1-41
SMP60N03-I0L .... 6-121
Si6436DQ ........ 2-3
Si9933DY. . . . . . . .. 1-47
SMP60N06-14 ..... 6-125
Si6447DQ ........ 2-5
Si9936DY ......... 1-51
SMP60N06-18 ..... 6-129
Si6542DQ ........ 2-7
Si9939DY. . . . . . . .. 1-55
SMUI0P05 ....... 6-73
Si6953DQ ........ 2-9
Si9940DY ......... 1-61
SMU15N05 ....... 6-83
SUP60P06-20 ..... 6-163
2N6849 . . . . . . . . . .. 6-165
2N6851 ........... 6-169
2N7089 ........... 6-209
2N7090 ........... 6-213
2N7091 ........... 6-217
2N7224JANTX .... 6-221
2N7224JANTXV ... 6-221
2N7225JANTX .... 6-223
2N7225JANTXV . .. 6-223
Si6956DQ ........ 2-11
Si9942DY ......... 1-65
SMU25N05-45L ... 6-89
2N7227JANTX .•.. 6-225
Si8956AZ/883 ..... 6-69
Si9943DY ......... 1-71
SMU30N03-30L ... 6-93
2N7227JANTXV . .. 6-225
Si9100 ........... 3-1
Si9944DY ......... 1-77
SMW20P10 ....... 6-133
2N7228JANTX .... 6-227
Si9102 ........... 3-9
Si9945DY ......... 1-81
SMW45NI0 ....... 6-137
2N7228JANTXV ... 6-227
Si9104 ........... 3-16
Si9947DY ......... 1-85
SMW60N06-18 .... 6-141
5962-9098301MCA. 4-1
About This Data Book
The products detailed in this data book include both discrete and integrated devices for power control,
conversion, and switching in computers, automobiles, data storage, communications, industrial, and hi-rei
systems.
Siliconix' power MOSPET offerings include its LITTLE FOOT® and LITE FOOT'" families of small-outline
devices, plus a distinguished selection of low-on-resistance products in other packages rated for both the
industrial and military temperature ranges. Devices available in TO-220 and TO-263 packages include the
company's 60-V 'frenchFE1S, the first power MaSPETh on the market to offer a maximum on-resistance as low
as 8 mQ at 10-V gate drive.
Siliconix power ICs for power management and motor control serve applications ranging from load Switching in
battery-operated portable computers to dc-to-dc conversion in communications systems. Bus interface ICs
include devices designed for such protocols as ABUS and ISO 9141.
For More Information
To request additional literature, please call your 10cal1EMIC Sales Representative. Office listings with phone
and fax numbers are available in Section 8. In North America, you may also request information directly from
Siliconix at 1-800-554-5565.
For Technical Support
In addition to the individual data sheets, Siliconix offers a number of Application Notes to help you with your
designs. Please refer to the Application Note listing in Section 7, and use our FaxBack system at 1-408-970-5600
to obtain copies.
ii
TEMIC
Selector Guides
Siliconix
•
~
•
TSSOP
SO-8
SO-14
4-Pin DIP
••
SQFP-48
8-Pin DIP
LCC-20
, .
SO-24WB
SO-16WB
SO-16
16-Pin DIP
14-PinDIP
=
..
•
PLCC-20
~.~
~\.....
TO-252
(DPAK)
TO-251
cu ....
IUcu
~
519
,,~
~
TO-263
(D2PAK)
..
~'.",
'\
\':
\.
\::.
TO-205AF
(T0-39)
MOD
(Straight Lead)
TO-220
TO-257
MOD
(Bent-Up Lead)
.
,.
>.
y
TO-254
~\
"-
TO-247
MOD
(Bent-Down Lead)
iii
S(on) (0)
Vns(V}
VOS= lOV
20
0.1
30
Vos = 4.5 V
Vas==2.7V
In (A)
Configuration
8.PinSOIC
Page
0.05
008
±5
Dual
Si9925DY
1·37
±3.5
Dual
Si9956DY
1·113
0.2
0.03
0.05
±7
Single
Si9410DY
1·13
0.05
0.08
±S
Dual
Si9936DY
1·51
0.05
0.07
±5.3
Dual
50
0.13
0.2
±3
Dual
Si9955DY
1-109
±2
Dual
Si9959DY
1-123
60
0.1
0.2
±3.3
Dual
Si9945DY
1-81
200
1
±1
Single
Si9420DY
1-17
240
6
8
±0.4
Dual
Si9944DY
1-77
0.3
16·PinSOIC
Page
Si9940DY
1-61
~
~
~
~
o
o
~
@)
rJ1
f'D
......
f'D
~
P-Channel MOSFETs
"""'"
o
-S
Packages
Maximum Ratings
Il>S(on) (0)
Vns(V}
Vas=-lOV
Vos= -6V
Vos= -4.5V
Vos= -2.7 V
0.04
-12
1-29
Single
Si9433DY
1-25
0.065
0.1
±5.4
0.11
0.19
Dual
Si9933DY
1-47
Single
Si9430DY
1-21
0.16
±4.3
Single
Si9405DY
1-5
0.19
±3.5
Dual
Si9947DY
1-85
±2.3
Dual
Si9953DY
1-105
±2.5
Single
Si9400DY
1-1
0.105
±5.1
Single
Si9435DY
1-33
0.15
0.24
±3
Single
Si9407DY
1-9
0.28
0.5
±2
Dual
Si9948DY
1-89
0.055
--
Page
Si9434DY
±5.8
0.25
-60
8·PinSOIC
Single
±3.4
0.065
0.1
-30
Configuration
±6.4
0.09
0.05
-20
ID(A)
-- ---
0.4
0.07
~
....
~
f'D
~
....
III
~.
...
~
tTJ
~
~
C"')
c
I
t
MOSFET:S
Maximum Ratings
00
....
.n...
o
::I
....
-
Packages
rns(on) (0)
VDS(V)
VGS = ±lOV
VGs=±6V
~
VGS = ±4.SV
VGS
= ±Z.7V
ID(A)
Configuration
20
0.05
O.OB
±5
N-Channel
-20
0.13
0.19
±3.2
P-Channel
0.15
±3.5
N-Channel
0.19
±3.5
P-Channel
20
-20
0.1
0.12
20
0.125
0.25
±3
N-Channel
-20
0.16
0.3
±2.B
P-Channel
20
0.125
0.25
±3
N-Channel
-20
0.2
0.35
±2.5
P-Channel
25
0.1
0.15
±3.5
N-Channel
-25
0.25
30
0.4
±2.3
P-Channel
0.05
0.07
O.OB
±3.5
N-Channel
-30
0.1
0.12
0.16
±3.5
P-Channel
50
0.3
1
±2
N-/P-Channel Half-Bridge
8-PinSOIC
Page
Si992BDY
1-41
Si995BDY
1-117
Si9943DY
1-71
Si9942DY
1-65
Si9952DY
1-99
Si9939DY
1-55
16-PinSOIC
C1
~
~
1-93
~
~
o
o
~
@)
rJ1
~
~
~
~
f""fo-
o
~
~
......
=
Q.
"
~
General
Information
~
~
Page
c:
Si9950DY
~
ttj
s.
~
N-Channel MOSFETs
Maximum Ratings
~
~
Packages
l"JlS(on} (0)
= lOV
=4.5 V
In (A)
Configuration
8-PinTSSOP
Page
20
0.100
0.200
±2.5
Dual
Si6956DQ
2·23
30
0.050
0.080
±4.2
Single
Si6436DQ
2-3
VGS
VDS(V}
VGS
~
o
o
~
~
P-Channel MOSFETs
Maximum Ratings
r:I1
....
~
Packages
rn5(on) (0)
VGS= -lOY
Vns(V)
-12
-20
VGS= -4.5 V
VGS= -1.7V
ID(A)
Configuration
8-PinTSSOP
Page
0.075
0.110
±3.5
Single
Si6433DQ
2-1
0.100
0.190
±3.0
Single
Si6447DQ
2-5
0.200
0.350
±1.7
Dual
Si6953DQ
2-15
~
~
o
""""
'"1
~
=
jIooIje
~
~
Complementary MOSFETs
I
Maximum Ratings
VDS(V)
20
- 20
_A
r
VGS= ±lOV
VGS= ±4.5V
ID(A)
Configuration
I
0.100
0.350
0.200
0.200
±2.5
± 1.7
N-Channel
·P-Channel
I
B
Packages
8-PinTSSOP
Si6542DQ
Page
2-7
• •,
•
~
.... t:rj
g' ~
....=
\I.l
)ioIoq
~
C"'.l
Power Conversion, PCMCIA Interface and Battery Management
....
.n...
o
....
=
(11
Recommended Operating Range
Function
Peak Output Current (A)
Voltage Range (V)
Part Number
Packages
Page
3-1
3-W High-Voltage Switchmode Regulator
2.5
10 -70
Si9100
14-Pin Plastic DIP
20-PmPLCC
3-W High-Voltage Switchmode Regulator
2
10 - 120
Si9102
14-Pm Plastic DIP
20-PmPLCC
3-9
High-Voltage Switchmode Regulator
2
10 -120
Si9104
14-Pm Plastic DIP
16-Pin Widebody SOIC
20-PinPLCC
3-16
l-W HIgh-Voltage Swltchmode Regulator
2
10 -120
Si910S
14-Pin Plastic DIP
16-Pin Widebody SOIC
20-PinPLCC
3-24
HIgh-Voltage Switchmode Controller
±0.2sa
10 -120
Si9110
14-Pin Plastic DIP
14-PinSOlC
14-Pin CerDIP
3-31
High-Voltage Switchmode Controller
±02S a
10 -120
Si9111
14-Pm Plastic DIP
14-PinSOlC
14-Pin CerDIP
3-31
High-Voltage Switchmode Controller
±0.2sa
9 - 80
Si9112
14-Pm Plastic DIP
14-PinSOlC
3-38
High-Frequency Switchmode Controller
±O.4 a
15 - 200
S19114
14-Pin Plastic DIP
14-PinSOlC
3-44
Universal Input Switchmode Controller
±0.2sa
10 - 450
Si9120
16-Pin Plastic DIP
16-PmSOlC
3-49
Low-Voltage Switchmode Controller
±0.2a
2.7 -7
Si914S
16-Pin SOIC
16-Pin TSSOP
3-55
Synchronous Buck Converter Controller
±O.25 a
6.0 - 16.5
Si91S0
14-PinSOlC
3-62
1.0b
N.A
Si9710CY
16-PinSOIC
3-68
PCMCIA Interface Switch
1.0b
N.A
Si9711CY
16-Pin SOIC
3-72
Battery Disconnect Switch
3.5
6 -18
Si9717CY
16-PinSOIC
3-76
Battery Disconnect Switch
3.5
6 -18
Si9718CY
16-PinSOIC
3-79
l
~
('1
I
00
ro
-~
~
I
~
o
~
....~
~
:§:
~
General
Infonnation
t.rj
~
1-1
n
'"1
PCMCIA Interface Switch
Notes
a. Driver output
b. Multiple outputs
~
~
~:
Motor Control and MOSFET Drivers:
Recommended Operating Range
Function
Quad High-Current Power Driver
Adaptive Power MOSFET Driver
Peak Output Current (A)
1.5"
±1"
Voltage Range (V)
i
Part Number
Packages
Page
D469A
14-Pin Plastic DIP
14-Pm Sidebraze
4-1
~
108 -16.5
Si9910
8-Pin Plastic DIP
8-PinSOlC
4-5
(1
00
12 - 15
~
12-V Voice Coil Motor Driver
1.8
16
Si9961
24-Pin SOIC
4-10
N-Channel Half-Bridge Driver
±0.5"
20 - 40
Si9976
14-PinSOlC
4-17
Configurable H-Bridge Driver
±o.sa
20 - 40
Si9978
24-Pin SOIC
4-22
3-Phase Brushless DC Motor Controller
±O.s"
20 - 40
Si9979
48-Pin SQFP
4-28
Notes
a. Driver output
~
~
~
~
~
o
~
~
-.
=
Bus Interface
Q.
~
RecuDlll1ended Operating Range
Peak Output Cur« nt (A)
Voltage Range (V)
Part Number
Packages
Single-Ended Bus Driver
N.A
5V,8-35V
Si9241
8-Pin SOIC
5-1
Single-Ended Bus Driver
N.A
5 V,8 - 35 V
Si9243
8-PinSOlC
5-5
Function
Page
'J.J
....
....
n
o
....
=
~
l-03
tr'.j
~
~
C":l
N-Ch
rI.l
Maximum Ratings
v(BMSS
30
50
60
100
-=....8....·
I
1~i'}
In
(A)
Packages
PD
(W)
TO·220AB
Page
0.03
30
50
0.01
60
105
SMP60N03·10L
6·121
BUZll
6·1
SMP25N05·45L
6·101
BUZ71
6·5
BUZ71A
6·5
0.04
30
75
0.045
25
50
0.045
25
70
0.1
2.4
1
0.1
14
40
0.1
15
40
0.12
13
40
J)2PAK
TO·l63
Page
60
150
SUP60N06·08
6·157
SUB60N06·08
6·153
60
100
SUP60N06-14
6-161
SUB60N06·14
6-161
0.014
60
150
SMP60N06-14
6·125
0.014
70
150
SUP50N06·18
6·155
125
SMP60N06-18
6·129
46
105
SMP50N06·25
6·117
15
40
0.4
1.1
1
0.025
60
180
0.04
40
125
48
83
60
105
0.018
60
0.025
0.1
TO·2S1
Page
SMD30N03·30L
6·93
SMU30N03·30L
6·93
SMD25N05·45L
6·89
SMU25N05·45L
6·89
SMD15N05
0.008
0.018
Page
Page
TO·247AD
SUB50N06·18
6·83
SMU15N05
6·83
SMW70N06·14
6·149
SMW60N06·18
6-141
~
~
o00
6·87
45
150
30
100
SMP30NlO
6·105
0.085
27
125
IRF540
6·25
0.18
14
75
IRF530
6·21
0.3
1.3
1
0.3
8
40
IRF520
6·17
0.6
1
1
06
4
20
IRF510
~
SMW60NlO
6·145
~
SMW45NlO
6·137
00
6·41
6·109
0.06
~
~
IRFD120
6-41
IRFDllO
6-37
~
~
f""f-
o
~
6·13
---
...~
Q..
$;.
~
General
Information
~
1-1
~
IRFD123
0.04
~
6·33
6-155
SMD15N06
SMP40NI0
Page
trj
n
IRFD020
0.014
0.018
DPAK
TO·2S2
4·Pin
DIP
TO·2S0
~
l<
P-Channel
Maximum Ratings
v(BMSS
-SO
-60
-100
Packages
~~D)
In
(A)
(W)
TO·22OAB
Page
0.4
-7
40
BUZl71
6·9
0.28
-1.6
1
0.28
-10
40
J)ZPAK
TO·1O
PD
Page
TO·lS'!
Page
SMDlOPOS
6·73
SMU10POS
6-73
0.02
-60
150
SUP60P06-20
6-163
0.045
40
125
SMP40P06
6-113
0.28
10
40
SMDlOP06L
6·79
0.28
10
42
SMDlOP06
6-77
0.8
0.8
0.2
-20
125
0.2
-20
150
0.3
-12
75
0.6
-1
1
SUB60P06-20
Page
DPAK
T()'152
TO·247AD
Page
4·PinDIP
TO·l50
Page
IRFD9020
6-45
IRF9S30
6-29
SMW20P10
-
-
-
-
-
~
~
IRFD9123
6-97
101
o
00
6-163
1
SMP20P10
l
6-49
~
...
00
6-133
IRFD9120
6-49
f'D
f'D
~
f""f'-
o
101
~
.,..
=
Q..
f'D
~
.....\I:l...
n
o
....
=
~
trj
~
1-4
C""J
.......
N-Channel Hermetic Packages and Industry-Standard Military MOSFETs
Maximum Ratings
t')
Packages
Q
Hermetic Power Module
V(B~SS
100
200
400
500
(/.l
l'])~on)
( )
In
(A)
Pn
(W)
0.065
30
150
0075
20
60
0.08
21
150
0081
34
150
0.15
13
50
0.1
28
150
0.105
27.4
150
0.11
21
150
0.16
14
60
0.3
15
150
0.35
15
150
Lead Bent Down
Page
Lead Bent Up
Page
TO-254AA
Page
2N7075
6-173
TO-257AB
6-53
6-221
IRFM150
2N7081
6-57
MOD200C
2N7076
6-177
2N7225
6-223
MOD40OC
IRFM250
6-2oe
14
150
2N7227
6-225
IRFM350
150
2N7078
6-185
IRFM450
0.43
13
150
0.515
12
150
2N7228
6-227
00.
~
MOD500BIC
6-65
IRFM450
592
--
20
0.1
0.5
LCC-20
Quad
Si8956AZ/883
I 6-69
~
P-Channel Hermetic Packages and Industry-Standard Military MOSFETs
Packages
Maximum Ratings
V(B~SS
-100
-200
l'])~on)
( )
In
(A)
Pn
(W)
0.2
-14
70
0.21
-17
100
0.3
6.5
25
0.3
-10
60
0.5
9.5
100
0.8
-5.7
60
0.8
-4
25
TO-205AF
Page
TO-254AA
2N7079
2N6849
TO-257AB
Page
Equivalent
Commercial
Part
2N7091
6-217
2N7091
QPLProduct
in Accordance
With 195001
IRFF9130
2N7089
6-209
2N7090
6-213
564
2N7089
2N7080
6-193
2N7090
IRFF9230
6-169
...............~
g
...
00.
~
~
r')
2N7079
6-189
6-165
2N7080
2N6851
Page
564
S"
"'1
~
......
~
~
~.
General
Information
~
~
0
592
t!j
n
~
MOD400BIC
13
MOD500C
592
IRFM350
6-181
6-61
0.4
6-65
~
~"'1
2N7086
0.415
MOD500B
....
=
~
592
2N7081
MOD200BIC
6-57
2N7077
6-61
6-197
IRFM250
2N7086
MOD400B
2N7085
MODlOOB/C
2N7224
MOD200B
6-201
6-53
MODlOOC
QPLProduct
in Accordance
With 195001
IRFM150
2N7085
MODlOOB
Page
Equivalent
Commercial
Part
~
TEMIC
Ordering Information
Siliconix
Power Products Nomenclature
For Power MOSFETs
S
Manufacturer-Siliconix
M
P
60
N
06
-
18
L
T
M: MOSPOWER, U: Ultrahigh Density MOSPOWER
Package: B - TO-263 (I)2PAK)
C - Chip
D - TO-2S2 (DPAK)
P - TO-220
U - TO-2S1
w- TO-247
Maximum Drain Current in Amperes
Polarity: N - N-Channel, P - P-Channel
Breakdown Voltage (Multiply by 10 for Voltage)
rnS(on) in Milliohms (Where Applicable)
Logic Level (Where Applicable)
xii
(06/01/94)
LITTLE FOOT®
,
' , : , '';I
.:..:
.s _ _
"
;
,.
:;.~,
;
,
" r-!,
~
I.
...
.' ...-""",.,,,.;,.'
'"~v
II
About LITTLE FOOT
Siliconix' LITTLE FOOT® is the industry's first and largest family of small-outline, surface-mount power
MOSFETh for motion control and load management in space-sensitive applications from the portable
computer to the automobile. LITTLE FOOT products come in single and dual versions and can be
mounted directly to printed circuit boards, where they are fully compatible with other surface-mounted
components. First designed for computers and computer peripheral products, LITTLE FOOT is now
widely used in telecom s~tems, automotive air bag triggers, and numerous other applications where
space-savings and efficiency are at a premium.
TEMIC
Si9400DY
Siliconix
P-Channel Enhancement-Mode MOSFET
Product Summary
rnS(on) (Q)
Vns(V)
0.25 @VGS
-20
0.40@VGS
= -lOY
= -4.5 V
In (A)
±2.5
±2.0
S
S
SO·8
N~OI~ ~
S
3
6
D
G
4
5
D
Top View
DDDD
P·Channel MOSFET
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain·Source Voltage
VDS
-20
Gate-Source Voltage
VGS
±20
Continuous Drain Current (TJ = 150'C)
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation (Surface Mounted on FR4 Board)
ID
±2.0
IDM
±10
Is
-2.0
A
2.5
ITA=25'C
PD
ITA=70'C
Operating Junction and Storage "Thmperature Range
V
±2.5
ITA=25'C
ITA = 70'C
Unit
1.6
W
TJ, Totg
-55 to 150
·C
Symbol
Limit
Unit
RthJA
50
'c/w
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board)
P-34826-Rev. G (05/16/94)
1·1
TEMIC
Si9400DY
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
-1.0
1YP"
Max
Unit
±100
nA
Static
Vas(tb)
VDS = Vas.ID = -250 JlA
Gate-Body Leakage
lass
VDS =OV,Vas = ±20V
Zero Gate Voltage Drain Current
IDSS
On-Slale Drain Currenlb
ID(on)
Gate Threshold Voltage
Drain-Source On-Slale Resislanceb
Forward lI'ansconductanceb
Diode Forward Vollageb
roS(on)
V
VDS = -16 V, Vas = OV
-2
VDS - -16 V, Vas - Ov, TJ - 55'C
-25
VDS
S
-5 V, Vas = -10V
-10
~A
A
Vas- -lOV,ID= lA
0.16
0.25
Vas = -4.5 V, ID = 0.5 A
0.30
0.40
gf.
VDS = -15 V, ID = -2.5 A
2.5
VSD
Is = -1.25 A, Vas = OV
-0.9
-1.6
5.4
25
0
S
V
Dynamic"
TOlal Gale Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Thm-On Delay TIme
Id(on)
Rise TIme
Thrn-Off Delay TIme
Ir
Id(off)
Fan TIme
tf
Source-Drain Reverse Recovery TIme
Irr
VDS= -10 V, Vas = -10V,ID = -2.0 A
0.9
nC
1.4
10
VDD = -10V, RL = 100
ID" -1A, VaEN= -10V,Ra=60
IF = 2 A, di/dt = 100 N~s
40
10
40
38
90
27
50
69
100
ns
Noles
a. For design aid only; not subjecl to produclion lesting.
b. Pulse test; pulse width S 300~. duty cycle S 2%.
1-2
P-34826-Rev. G (05/16/94)
TEMIC
Si9400DY
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
Transfer Characteristics
20
10
~
8"
c
,
15
8
8"
I
6V
b
"§
Q
Q
5V
.E
3Y,2V
~
0
0
2
4
.E
4V
2
J
0
6
8
o
10
6
2
VOS - Drain-to-Source Voltage (V)
e-8
.~
d
0
600
VGS=4.5:!
0.4
- ----
0.2
o
,e,
500
§
.~
400
\
\
a-
300
\ "CI'''
Ii:'
0.6
'i
g
Capacitance
~
~
200
U
VGs=10V
100
2
~
"
OIl
.i:!
IO=2A
.
~
§
6
"
0
til
.9..
4
"
2
:;;
~
0
/
V
/
/
/
2.0
V
V
I
5
15
10
20
1.5
~~
~'O
.~ .§
~"il
d
On-Resistance ys. Junction Temperature
.' ,'-
VGS = lOV
10 = LOA
e-
E
1.0
~~
/
o
~
c,.ss
VOS - Drain-to-Source Voltage (V)
Gate Charge
, .l
Vos= 10V
8 I--
\J"
o
5
4
10 - Drain Current (A)
10
~
I
0
o
10
700
[
0.8
8
VGS - Gate-to-Source Voltage (V)
On-Resistance ys. Drain Current
1.0
I--
,I
6
c
.~
25·C
125·C
~
7V
10
f!..-
I.
Tc= -55·C
I
8V
J
0.5
---
...- ",..
V
/
o
2
3
4
Og - Thtal Gate Charge (nC)
P-34826-Rey. G (05/16/94)
6
-50 -25
0
25
50
75
100
125
150
TJ - Junction Temperature ("C)
1-3
TEMIC
Si9400DY
Siliconix
'IYPical Characteristics (25°C Unless Otherwise Noted)
20
S
10
C
Source-Drain Diode Forward Voltage
~Lj V
I
8
j
I
~
=
rSl
-
I
I
I
.,
1
o
0.4
0.4
~
r-
~
.-
TJ = 25°C
0
0.2
\
I
J
I
0.1
o
0.8
1.2
1.6
2.0
2.4
o
0.5
E
§
~
0.0
~
~
....-
-0.5
---
i-"""""
80
--
8
-
10
Single Pulse Power
100
"..
6
V GS - Gate-to-Source Voltage (V)
Threshold Voltage
JJ~
I'--
2
VSD - Source-to-Drain Voltage (V)
1.0
I
ID=2.5A
0.3
.!
'i!
"
~
4
/
I
2
o
1
/
1.4
8
!;j~
-'"§
.!:, e
"
c ~
O~
J
V
.l
_I
1.6 _VGs=lOV
ID=3A
1.2
0.8
I~
/
o
/
."
10
15
20
Qg - Thlal Gate Charge (nC)
P-35337-Rev. C (05/02/94)
30
40
50
25
V
1
-'"
L
V
/
/
"
0.4
a
5
20
10
On-Resistance vs. Junction Temperature
2.0
/
1
ID=3A
--
J
Co..
VDS - Drain-to-Source Voltage (V)
Gate Charge
10
Cus
\
U
a
o
I'-
I
ID - Drain Currenl (A)
~
1>'0
,g
10
6
VGS - Gate-to-Source Voltage (V)
0.5
e-
r
;;;
c
P
16
r/P25'C
25'C
-50 -25
a
25
50
75
100
125
150
TJ - Junction Temperature ('C)
1-11
TEMIC
Si9407DY
Siliconix
'fYpical Characteristics (25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
~
I
10
"~
r-
u
TJ = 150'C
I
I
I
~
IV
I,
'"
~
II
0.3
~
TJ=25'C-
I
o
ID=3A -
~
g
I
.:!1
I
0.4
e.
I
I
0
0
0.2
I
0.1
o
0.4
On-Resistance vs. Gate-to-Source Voltage
0.5
0.8
1.2
1.6
i'-.
o
2
1.0
0.5
E
.~
i.,....o-"
0.0
~
~
:d'
Co
~
Threshold Voltage
JJ~
6
10
Single Pulse Power
100
V
.".,.V
4
VOS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
~
80
./
\
60
" . i--""'"
,
40
-0.5
20
'I'
oI
-50 -25
0
25
50
75
100
125
150
111111111 I !JtI1ffi--111111111
0.01
TJ - Temperature ('C)
0.1
10
II
30
TIme (sec)
Normalized Thermalll:ansient Impedance, Junction-to-Ambient
2
I
"
E Duty Cycle -
0.21
III
0.5
...
0.1
==
-
-
-~jjiii
~
I
om
.-
10- 4
Single Pulse
10-3
mJL
~~
t2
tl
0.05
0.02
Notes:
1. Duty Cycle,D =
t2
2. Per Unit Base =llthJA "'" SOoC/W
3 TJM - TA = PDMZtbJA(t)
~I-'
I I"""" I
4 Surface Mounted
10- 2
to-I
10
30
Square Wave Pulse Duration (sec)
1-12
P-35337-Rev. C (05/02/94)
TEMIC
Si9410DY
Siliconix
N-Channel Enhancement-Mode MOSFET
Product Summary
Vns(V)
rnS(on) (Q)
30
= 10 V
=5 V
0.050@VGS = 4.5 V
0.030 @ V GS
0.040 @ V GS
In (A)
±7.0
±6.0
±5.4
DDDD
SO-8
N/C
s
S
G
0"
2
7
D
3
6
D
4
5
D
~
0
0
~
~
~
-
lbpV!ew
S
S
~
~
N-Channel MOSFET
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Symbol
Limit
Drain-Source Voltage
Parameter
VDS
30
Gate-Source Voltage
VGS
±20
Unit
V
±7.0
ITA;25"C
Continuous Drain Current (T] ; 150"C)
ID
ITA= 70"C
±5.8
A
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
IDM
±20
Is
2.8
2.5
ITA=25"C
Maximum Power Dissipation (Surface Mounted on FR4 Board)
PD
ITA = 70"C
Operating Junction and Storage Thmperature Range
1.6
W
T].T,tg
-55 to 150
"C
Symbol
Limit
Unit
RthIA
50
"C;W
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board)
P-35964-Rev. G (06/13/94)
1-13
TEMIC
Si9410DY
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
1.0
1yP"
Max
Unit
±loo
nA
Static
VGS(th)
VDS = VGs. ID = 250 I!A
Gale-Body Leakage
IGSS
VDS = OY,VGS = ±20V
Zero Gale Vollage Drain Currenl
IDSS
On-Slale Drain Currenlb
ID(on)
Gale Threshold Voltage
Drain-Source On-Slale Resislance b
Forward 1fansconduclanceb
Diode Forward Vollageb
TDS(on)
V
VDs=24Y,VGs=OV
2
VDS = 24 Y, VGS = 0 Y, TJ = SsoC
2S
VDS" SY, VGS = 10V
20
I!A
A
VGS = lOY, ID =7.0A
0.026
0.030
VGS = SY, ID = 4.0A
0.034
0.040
VGS - 4.SY, ID - 3.5 A
0.042
O.OSO
gf,
VDS = lSY, ID = 7.0A
14
VSD
Is =2A, VGS = OV
0.75
1.1
30
50
VDS = lSY, VGS = 10Y,ID = 2A
3.4
Q
S
V
Dynamic"
Thlal Gale Charge
Qg
Gale-Source Charge
Qgs
Gale-Drain Charge
Qgd
Thrn-On Delay TIme
Id(on)
Rise TIme
Thrn-Off Delay TIme
I,
1cl(off)
Fall TIme
If
Source-Drain Reverse Recovery TIme
I"
nC
10.5
VDD = 2SY,RL = 25 Q
ID '" 1 A, VGEN = 10Y,RG = 6Q
IF = 2 A, dildl = 100 N!'s
13
30
30
60
95
150
80
140
ns
100
Noles
a. Guaranleed by design, nol subjecllo produclion lesling.
b. Pulse lesl; pulse widlh s 300 !,S, duty cycle s 2%.
1-14
P-3S964-Rev. G (06/13/94)
TEMIC
Si9410DY
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
20
~t
VGS
16
S
E
E
a
12
.'Q'"
o
12
'2
8
Q
V
4
"t::
ac
4V
8
..9
r
= 10,9,8,7,6 V
5V
16
S
1l:ansfer Characteristics
20
..9
JL:,:=-5T125'C
4
3V
0
o
2
o
5
4
3
2
Vns - Drain-to-Source Voltage (V)
~
0.08
~
----
VGS = 4.5 V
0.04
J
VGs=10V
~.
1500
! \ '-.::
1\ r--.
o
o
8
12
16
o
5
~
.1
J
~
~
"
6
0
~
~
4
~
2
/
d
0
/
/
o
15
20
25
30
On-Resistance vs_ Junction Temperature
2.0
/
e!.
1.6 -
LsJov
1
In = 7.0 A
8
a~
.'iii]
1.2
~';;
dE
J
,. "..".V
.....-
0 0 0.8
I~
/
II
10
d..
Vns - Drain-to-Source Voltage (V)
Gate Charge
Vns= 15V
8 r-- In =2A
c!..
" ............
In - Drain Current (A)
10
c,..
1000
I
U
500
o
E
8
2000
~
0
I
6
Capacitance
2500
e!.
j
~;,
4
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Drain Current
0.12
A
~
/
",
V
0.4
o
5
10
15
20
Qg - Thtal Gate Charge (nC)
P-35964-Rev. G (06/13194)
25
30
-50 -25
0
25
50
75
100
125 150
TJ - Junction Temperature (0C)
1-15
TEMIC
Si9410DY
Siliconix
'J)pical Characteristics (25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
20
S
10 _
/ /
J
T1- 15O 'C
8"
I
J
~
I
I
'"
1
0.6
j
0.08
~
0.06
\
~ r--
0
J
I
/
0.4
T1=25'C -
l
J
0.10
e..
I
~
On-Resistance vs. Gate-to-Source Voltage
0.12
Io=7A
0.04
0.02
0.00
0.8
5
4
Threshold Voltage
20
r-.... r-..
10 = 2501lA
~
..........
~
~
10
Single Pulse Power
0.5
0.0
9
25
1.0
~
8
Vas - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
€
~
7
6
r-.... r--..
-0.5
\
15
..........
10
"- .....
"'"
5
o
-1.0 L . I _ - L . _ ' - - - - ' - _ - ' - - _ - L . _ ' - - - - ' - _ - '
-50 -25 0
25
50
75 100 125 150
I II 1111111 111111111 1111llltt±tHlli1
0,01
T1 - Thmperature ('C)
0.1
10
100
Time (sec)
Normalized Thermal1l:ansient Impedance, Junction-to-Ambient
2
I
II
.2
==
DutyCycle
~;
-
0.2
"&18
·n.
Jl.s
ill]
"' .
~~
0.1
=
1111
0.5
....
~~
o.~
0.05
Notes:
ffiJL
-~l-I
'2 -
I
_
1..000""'"
0.02
si~glepU1se
0.01
10- 4
I.DutyCjde,D=
f,
2 Per Unit Base = RtbIA = SOoC/W
3 TJM - TA = POMZthJA(t)
V
10-3
i--'"
4 Surface Mounted
I
10-2
10- 1
I I I II III
10
I
30
Square Wave Pulse Duration (sec)
1-16
P-35964-Rev. G (06/13194)
TEMIC
Si9420DY
Siliconix
N-Channel Enhancement-Mode MOSFET
Product Summary
Vns(V)
rnS(on) (Q)
In (A)
200
1.0 @ VGS = 10 V
± 1.0
DDDD
SO·8
N/C
S
S
G
0
D
2
7
3
6
D
D
4
5
D
~
0
0
ThpView
S
~
S
~
N-Channel MOSFET
~
~
~
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Symbol
Limit
Drain-Source Voltage
Parameter
VDS
200
Gate-Source Voltage
VGS
±20
ID
ITA= 70'C
Pulsed Drain Current
IDM
Continuous Source Current (Diode Conduction)
Is
PD
ITA = 70'C
Operating Junction and Storage Temperature Range
±O.B
±10
A
1.0
2.5
ITA=25'C
Maximum Power DissipatIOn (Surface Mounted on FR4 Board)
V
±1.0
ITA= 25'C
Continuous Drain Current (TJ = 150'C)
Unit
1.6
W
TJ,T,tg
-55 to 150
'C
Symbol
Limit
Unit
RthJA
50
'c/w
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board)
P-35420-Rev. D (06/06/94)
1-17
TEMIC
Si9420DY
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
2
1YP"
Max
Unit
±loo
nA
Static
VOS(th)
VDS = Vas, ID = 250 JlA
Gate-Body Leakage
loss
VDS = OY,Vos = ±20V
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(on)
VDS;': lOY, Vas = 10V
roS(on)
Vas = lOY, ID = 1.0 A
gr,
VDS = 15 Y, ID = 1.0 A
1.5
VSD
Is = LOA, Vas = OV
Gate Threshold Voltage
Drain-Source On-State Resistanceb
Forward 1l-ansconductanceb
Diode Forward Voltageb
V
VDS = 160Y, Vas = OV
2
VDS - 160 Y, Vas - 0 Y, TJ - 55'C
25
5.0
~A
A
1.0
Q
0.7
1.2
V
8.6
16
0.8
S
Dynamic"
Thtal Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Thrn-On Delay TIme
Rise TIme
Thrn-Off Delay TIme
VDS = 100Y, Vas = lOY, ID = 1.0 A
t.l(off)
FaJITIme
tf
Source-Drain Reverse Recovery TIme
tIT
nC
3.2
td(on)
t,.
1.5
VDD = 100Y,RL = lOOQ
ID '" LOA, VOEN = 10Y,Ro = 6 Q
IF = 1.0 A, di/dt = 100 N~
7
14
12
24
26
50
15
30
ns
130
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse ~est; pulse width s 3OO~, duty cycle s 2%.
1-18
P-3S420-Rev.D (06/06/94)
TEMIC
Si9420DY
Siliconix
l)'pical Characteristics (25°C Unless Othenvise Noted)
Output Characteristics
1l-ansfer Characteristics
10
8Y
s
"~
a
7Y
8
S
""
t:
:s
U
I----,jlf----I-----i---t 6 Y
"
"
'@
.~
Q
Q
E
2
E
5Y
4
2
4Y
0
0
4
8
12
16
YDS - Drain-to-Source Voltage (V)
0
]§
~
0
/
YGS= lOY
1.00
~
-
0.80
c;:;-
V
.eo
!!
400
300
I\,
200
1\
)3
'iij
c..
a
I
U
100
o
o
2
4
6
~ ...... ""'" """
o
5
~
12
~'ii
8
I
4
0
]§'"
j~
,e
"
~
O~
I~
J
/
o
15
20
25
IYGS
2.0 l-- ID=lA
8
/
0
~
~
V
/
0
10
30
JlOyl
/1/
~
Coss
35
On-Resistance vs. Junction Temperature
2.5
/
I
YDS= 100Y
16 I-- ID = lA
t---
YDS - Drain-to-Source Voltage (V)
Gate Charge
20
c;.. -
\\
ID - Drain Current (A)
:s
10
Capacitance
0.60
5'"
8
500
J
~
6
600
1.20
0.40
4
2
YGS - Gate-to-Source Voltage M
On-Resistance vs. Drain Current
1.40
~
8
0
20
./
1.5
1.0
",.
0.5
"",
V
./
L
/
/
o
4
8
12
Og - Thtal Gate Charge (nC)
P-3S420-Rev. 0 (06/06/94)
16
-50 -25
0
25
50
75
100
125 150
TJ - Junction Temperature Cc)
1-19
TEMIC
Si9420DY
Siliconix
1Ypical Characteristics (25°C Unless Othenvise Noted)
Source-Drain Diode Forward Voltage
20
~
-=~
10
f=
TJ
150'C
~
e.
1.5
1.0
TJ = 25'C
.1
~
.
0
,,
I
I
8
I I
@
:I
ell
II
.::
I
1
\
!
ID = 1A
a
0.5
o
0.5
1.0
1.5
2
5
Threshold Voltage
9
10
Single Pulse Power
20
€
g
\
15
~
0.00
~
~
8
7
25
0.50
~
6
VGS - Gate-to-Source Voltage (V)
Vso - Source-to-Drain Voltage (V)
1.00
-....
I
I
I/
o
On-Resistance vs. Gate-to-Source Voltage
2.0
10
-0.50
I'...
5
J 111111111
I
-1.00
-50
0
50
100
150
0.01
TJ - Thmperature ('C)
111111111 1IIIJJlttttttlliI
0.1
10
100
Time (sec)
Normalized Thermal 'ftansient Impedance, Junction-to-Ambient
2
I
III
Duty Cycle - 0.5
-
0.2 1,
0.1
I
0.05
~
0.02
Single Puis.:;..,.
0.01
10-4
i--
-
Notes'
~
-jtll~
-12
1. Duty Cycle, D =
2 PerUnttBase
.,;
tl
t2
=RtbJA = SOoC/W
3. TJM - TA = PDMZthJA(t)
V"
10-3
HlSL
4. Surface Mounted
I I IIIIIII
10-2
10- 1
10
I
30
Square Wave Pulse Duration (sec)
1-20
P-35420-Rev. D (06/06/94)
TEMIC
Si9430DY
Siliconix
P-Channei Enhancement-Mode MOSFET
Product Summary
Vns(V)
rnS(on) (Q)
In (A)
±5.8
-20
= -10 V
0.065 @VGS = -6 V
0.090 @ VGS = -4.5 V
0.050 @ VGS
±4.9
±4.0
s s s
SO-8
'0
D
S
2
7
D
S
3
6
D
G
4
5
D
E-4
0
0
~
r.l
Top View
~
DDDD
E-4
P·Channel MOSFET
1-4
~
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Symbol
Limit
Drain-Source Voltage
Parameter
VDS
-20
Gate-Source Voltage
VGS
±20
Continuous Drain Cnrrent (TJ = 150'C)
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation (Surface Mounted on FR4 Board)
Operating Junction and Storage Thmperature Range
ID
±4.6
IDM
±15
Is
-2.4
A
2.5
ITA = 25'C
ITA= 70'C
V
±5.B
ITA=25'C
ITA= 70'C
Unit
PD
1.6
W
TJ,Tstg
-55 to 150
'C
Symbol
limit
Unit
R,hJA
50
'c/w
Thermal Resistance Ratings
Parameter
Maximum Junction-ta-Ambient (Surface Mounted on FR4 Board)
P-35963-Rev. E (05/24/94)
1-21
TEMIC
Si9430DY
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
-1.0
1YP"
Max
Unit
nA
Static
Vas(th)
Vos = Vas. 10 = -250 fLI\
Gate-Body Leakage
lass
Vos= OV,Vas = ±20V
±loo
Vos = -16 V, Vas = OV
-1
Zero Gate Voltage Drain Current
lOSS
Vos = -10V, Vas = OV, TJ = 70·C
-5
Gate Threshold Voltage
On-State Drain Currentb
10(on)
Drain-Source On-State Resistanceb
roS(on)
Forward 'llansconductanceb
Diode Forward Voltageb
Voss -5V,Vas--1OV
-15
Vos s -5 V, Vas = -4.5 V
-3.6
V
fLI\
A
Vas = -10V, 10 = -5.3 A
0.040
0.050
Vas- -6V,lo- -3.6 A
0.055
0.065
Vas - -4.5 V, 10 = -2.0 A
0.070
0.090
8f,
Vos = -15 V, 10 = -5.3 A
8.0
Vso
Is - -2.4 A, Vas - OV
-0.9
-1.2
25
50
Q
S
V
Dynamic"
Thtal Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
"furn-On Delay Time
ld(on)
Rise Time
"furn-Off Delay Time
Vos= -10 V, Vas = -10V,Io = -5.3 A
td(olf)
tl
Source-Drain Reverse Recovery Time
trr
nC
8
tr
Fall Time
5
10
55
Voo = -10V, RL = lOQ
-1A, VaEN= -lOV,Ra=6Q
IF = -2.4 A, dildt = 100 NI1S
14
30
22
60
50
120
2S
100
85
100
ns
Notes
Guaranteed by design. not subject to production testing.
b. PuIse test; pulse width S 300 118. duty cycle S 2%.
1-22
P-3S963-Rev. E (05/24/94)
TEMIC
Si9430DY
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
lransfer Characteristics
16
16
V'v'VVOS = 10,9,8, 7,6V
~
12
$
V
;;;
8
c
'
.............
'- -
ID - Drain Current (A)
5
5
~
c,.,.
0.05
4
Capacitance
0.25 ,--,---,--,----,--,---"T----,
.!a
~
i:
o
3
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
0.20
-55'C
0
0
ej
IJ 25~C
"r-
2
Qg -
4
6
8
10
0.6
-50
50
100
150
TJ - Junction Temperature ('C)
Thtal Gate Charge (nC)
P-36733-Rev. C (05/24/94)
o
Preliminary
1-45
TEMIC
Si9928DY
Siliconix
1Ypical Characteristics
P-Channel
(25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
10
On-Resistance vs. Gate-to-Source Voltage
0.20 ,-------,----,,------.----,-------,
I I
I I
c - Tl= 150'C
I I
I
~
I
!?!-
g
Tl = 25'C
I I
I I
g
!c
I
.,
0
I
I
I
0
0.4
0.15
0.10
0.05
0.8
1.2
1.6
L....._ _..L.._ _--'-_ _ _' - -_ _...J
o
2.0
VSD - Source-to-Drain Voltage (V)
Threshold Voltage
1.0
2
4
8
6
Vos - Gate-ta-Source Voltage (V)
25
Single Pulse Power
20
0.5
€
.~
15
~
0.0
~
~
10
~
\
-0.5
-1
:1 111111111 1111it""111 II
I
-SO
SO
0
150
100
,
10-2
Tl - Temperature ('C)
10-1
10
30
Time (sec)
Normalized Thermal 'ftansient Impedance, Junction-to-Ambient
2
===
I I IIIIII
DutyCycle
--
0.5
-0.2
~~
0.1
F= 0.05
.....
f--- 0.02
0.01
10- 4
I
I.oo!!I
~
Single Pulse
10-3
Notes
BUL
~ f-:.j
t2
1.DutyCycle,D=
tl
Tz
2. Per Unit Base =R2bJA = 62SoC/W
3. TJM - TA
. /V
= PDMZtb.JA(t)
4. Surface Mounted
10-2
10- 1
10
30
Square Wave Pulse Duration (sec)
1-46
Preliminary
P-36733-Rev. C (05/24/94)
TEMIC
Si9933DY
Siliconix
Dual P-Channel Enhancement-Mode MOSFET
Product Summary
Vns(V)
rnS(on)
In (A)
(Q)
= -4.5 V
= -3.0 V
0.19 @VGS = -2.7 V
-20
0.11
@VGS
±3.4
0.15
@VGS
±2.9
±2.6
SO-8
SI
Gl
S2
G2
0
D1
2
7
Dl
3
6
D2
4
5
D2
ThpView
P-Channel MOSFET
P-Channel MOSFET
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
-20
Gate-Source Voltage
VGS
±12
V
±3.4
ITA=25°C
Continuous Drain Current (TJ = IS0'C)
Vnit
ID
ITA=70°C
±2.7
A
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
IDM
±8
Is
-2.0
2.0
ITA=2Soc
Maximum Power Dissipation (Surface Mounted on FR4 Board)
PD
ITA= 70'C
Operating Junction and Storage Thmperature Range
W
1.3
TJ, T stg
-5510150
°C
Symbol
limit
Unit
RthJA
62.5
'c/w
Thermal Resistance Ratings
Parameter
Maximum Junction-Io-Ambient (Surface Mounted on FR4 Board)
P-35898-Rev. D (05/24/94»
Preliminary
1-47
TEMIC
Si9933DY
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
-0.8
1)p"
Max
Unit
nA
Static
VGS(th)
VOS = VGS, 10 = -250 Jl.A
Gate-Body Leakage
IGSS
VOS = 0'1 VGS = ±12 V
±100
VOS - -16v,VGS - OV
-1
Zero Gate Voltage Drain Current
loss
Gate Threshold Voltage
On-State Drain Currentb
10(011)
Drain-Source On-State Resistanceb
roS(on)
Forward 'fransconductanceb
Diode Forward Voltageb
V
-5
VOS = -10'1 VGS = Ov,TJ = 70'C
VOS S -5v,VGS = -4.5 V
-8
Vos s -5 V, VGS = -2.7 V
-2
Jl.A
A
Vos - -4.5 'lID - -3.2 A
0.09
VOS = -3.0 'lID = -2.0 A
0.120
0.11
0.15
VGS = -2.7'110 = -1 A
0.135
0.19
gr.
VOS = -9'110 = -3.4 A
8
Vso
Is = -2.0 A, VGS = OV
-0.9
-1.2
8
20
Vos = -6 V, VOS = -4.5 'lID = -3.2 A
1.6
g
S
V
Dynamic"
Thtal Gate Charge
Og
Gate-Source Charge
Ogs
Gate-Drain Charge
Ogd
3.5
1I1rn-On Delay TIme
td(on)
22
40
tr
43
80
35
70
20
40
75
100
Rise TIme
1I1rn-Off Delay TIme
td(olf)
Fall TIme
tl
Source-Drain Reverse Recovery TIme
trr
Voo = -6 V, RL = 6 g
10" -1A,VGEN=-4.5v,RG=6g
IF - -2.0A,dildt -100N!'s
nC
ns
Notes
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 flS, duty cycle s 2%.
1-48
Preliminary
P-3S898-Rev.D (05/24194»
TEMIC
Si9933DY
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
10
V
II'
~
E
6
--=
~
E
8
I
"c
U
c
.~
.~
Q
Q
E
~
Vas=5,4V
31V
8
~
'fransfer Characteristics
10
E
2
4
2
TC=t25O~
2,1 V
0
4
2
6
o
10
2
VDS - Drain-la-Source Vollage (V)
On-Resistance vs. Drain Current
Capacitance
2000
~
020
.fj
l3
C:
0
g
§
1500
8
.!
.!!l
~
0.15
e
1000
I
U
0.10
500
\
~
~
\
- r-...........
"'--
c,."
0.05
0
0
3
2
o
6
Gate Charge
5
I
I
~
"co
~
-
VDs=6V
ID =3.2A
/
~
§
/
"
0
"
~
o
(
o
Iss
6
2
-
8
10
On-Resistance vs. Junction Temperature
1.6
V
_
LV
I
Vas=4.5V
ID = 3.2A
V
I
2
c.,
VDS - Drain-to-Source Voltage (V)
ID - Drain Currenl (A)
~...
3
Vas - Gate-la-Source Voltage (V)
025
8
25~C
-55°C
0
0
e!..
IJ"1-:.<
~V
./
/
~
2
4
8
10
0.6
-50
o
50
100
150
TJ - Junction Temperature (0C)
Og - Thlal Gate Charge (nC)
P-35898-Rev. D (05/24/94))
~
Preliminary
1-49
TEMIC
Si9933DY
Siliconix
'lYpical Characteristics (25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
10
On-Resistance vs. Gate-to-Source Voltage
0.20 , - - -....-,-------.---,...---'----,
I
-
I
TJ=150'C
I
I
~
1_
I I
~
TJ = 25'C
I I
I
-
0.15
.1
~
0
I
!
'"
0.10
e
J
I
0.4
0
0.05
1.2
0.8
1--_ _....J.._ _ _.L..._ _......l._ _-----'
o
2.0
1.6
Threshold Voltage
1.0
6
2
8
VGS - Gate-ta-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
Single Pulse Power
25
20
0.5
~
8
15
.~
0.0
~
@.:
~
10
1\
\
-0.5
5
-1 I
-50
50
100
150
10-2
II
,,'"
r-- 0.2
Jl-
0.1
'Ei~
~1
0.1
~~
l
10
30
TIme (sec)
11111
~ DutyCycle
"Ow
10-1
Normalized Thermal 'Iransient Impedance, Junetion-to-Ambient
2
";8
F;;
-
o
0
TJ - Thmperature ('C)
.~
\
0.5
.... :: ..
F= 0.05
I
~
~
Single Pulse
10-3
Notes:
:.mIL
-V~
.....
-002
0.01
10-4
--
1 Duty Cycle
t~ = ..!!.
'2
,
2. Per Unit Base = RthJA = 62.SoC/W
3. TJM - TA = POMZthJA{t)
4. Surface Mounted
. / i-'
10-2
10-1
10
30
Square Wave Pulse Duration (sec)
1-50
Preliminary
P-35898-Rev. D (05(24/94»
TEMIC
Si9936DY
Siliconix
Dual N-Channel Enhancement-Mode MOSFET
Product Summary
rnS(on) (Q)
Vns(V)
0.050 @ VGS
30
0.080@VGS
= 10 V
= 4.5 V
In (A)
±5.0
±3.9
D1 D1
D2 D2
SO-8
S1
G1
S2
G2
0
D1
2
7
D1
3
6
D2
4
5
D2
G2~
G1~
E-4
0
0
~
~
ThpView
S1
E-4
E-4
S2
N-Channel MOSFET
::3
N-Channel MOSFET
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
30
Gate-Source Voltage
Vas
±20
Continuous Drain Current (TJ
Unit
V
~
±5.0
ITA- 25·C
150·C)
ITA ~ 70·C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
ID
±40
Is
1.7
ITA~25·C
Maximum Power Dissipation (Surface Mounted on FR4 Board)
ITA~ 70·C
Operating Juncllon and Storage Temperature Range
±4.0
IDM
A
2
PD
W
1.3
TJ. Tstg
-55 to 150
·C
Symbol
Limit
Unit
RthJA
62.5
.C/W
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board)
P-34118-Rev. C (04104/94)
Preliminary
1-51
TEMIC
Si9936DY
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
1
1YP"
Max
Unit
±l00
nA
Static
Gate Threshold Voltage
VGS(tb)
Vns = VGS. In = 250!lA
Gate-Body Leakage
IGSS
Vns = OV,VGS = ±20V
Zero Gate Voltage Drain Current
Inss
On-State Drain Currentb
In(on)
Drain-Source On-State Resistanceb
Forward 1ransconductanceb
Diode Forward Voltageb
Vns- 24 V,VGS - OV
2
Vns = 24 V, VGS = 0 V, TJ = 55°C
20
Vns '" 5V,VGS = 10V
TDS(on)
V
20
!lA
A
VGS = 10 V, In = 5.0A
0.04
0.050
VGS = 4.5 V, In = 3.9 A
0.06
0.080
gr,
Vns = 15 V, In = 5.0 A
8
Vsn
Is =1.7 A, VGS = OV
0.75
1.2
13
35
Vns = 15 V, VGS = 10 V, In = 5.0 A
1.5
g
S
V
Dynamic*
Thtal Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
1IIrn-On Delay TIme
Rise TIme
111m-Off Delay TIme
12
td(on)
tr
Vnn = 15 V, RL = 15 g
In'" 1A, VGBN= lOV,RG= 6g
Id(off)
Fall TIme
tf
Source-Drain Reverse Recovery TIme
trr
nC
3.7
IF = 5.0 A, dildt = 100 NflS
30
10
25
25
50
10
50
120
160
ns
Notes
a.
b.
Guaranteed by design. not subject to production testing.
Pulse test; pulse width s 300 "". duty cycle s 2%.
1-52
Preliminary
P-34118-Rev. C (04/04/94)
TEMIC
Si9936DY
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
V
40
V~s~9,8,~V
C
~
r
~
"
U
20
.~
16r-----~----_+~~--t-----~
6V
30
$
Transfer Characteristics
20r------r------r--,~-r----__,
I'"
12r-----~------~~---+----~
5V
8r------r------__-----+----~
~y
Q
10
.E
4V4
0
J
o
~
3,2,1 V
2
4
6
8
i-----+----hh
o------..
o
10
2
VDS - Drain-ta-Source Voltage (V)
~--L-----~--~
4
8
VGS - Gate-ta-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
0.30
e.
~
1600
0.25
I
,
VGS~4.5V
~
0.20
1200
.f'J
~
I
0.15
0
0.10
/
J
J
a
800
U
400
I
VGS~
0.05
o
·1
lOV
o
o
4
12
8
16
20
1\ ~ss
~ - ....
I\J:'
~
o
5
~
Gate Charge
"
bO
I
VDS~ 15V
ID ~5A
8
~
~
1!
6
V
"
0
'"g
"
'iil
4
~
2
o
2.0
/
/
1.8
1.6
·5 .~
1.2
~]
J
o" ~
20
25
30
On-Resistance vs. Junction Temperature
e--
_I.
I.
VGs~10V
ID~
SA
,
1.4
;'
..",
./
1.0
0.8
Ie
V
o
e.8
B~
I
tj
I
/
/
15
VDS - Drain-Io-Source Voltage (V)
ID - Drain Current (A)
10
10
c;"
i-""'"
."
~~
0.6
0.4
0.2
o
3
6
9
12
15
-50 -25
Og - Thtal Gate Charge (nC)
P-34118-Rev. C (04/04/94)
0
25
50
75
100
125
150
TJ - Junction Temperature ("C)
Preliminary
1-53
TEMIC
Si9936DY
Siliconix
1)rpical Characteristics (25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
20
TJ = 150
S
.
0.6
cd~
0.5
e..
10
On-Resistance vs. Gate-to-Source Voltage
0.4
~
I
J.-
11
~
1 II
~
6
I
-
I
'"
'"
o
0.4
I
TJ= ~'C
0.3
0
I
J
0.2
ID=5A
I
o
0.8
1.2
1.6
I
0.1
2.0
o
VSD - Source-to-Drain Voltage (V)
8
6
10
VGS - Gate-to-Souree Voltage (V)
Threshold Voltage
1.0
"
4
2
Single Pulse Power
25
20
0.5
~
~
..........
.~
0.0
-:;
.......... r--....
~
~
-
ID = 250 j.LA
r-..... j'-....
-0.5
15
1\
10
......... ....
\
.......
r-- ...
o I 111111111 111111111 I mllill 111111111
-1.0 '-1_---'--_-'------'_--'-_--'-_-'---''----'
-SO -25 0
25
50
75 100 125 150
0.Q1
0.1
100
10
TJ - Thmperature ('C)
TIme (sec)
Normalized Thermal 'Iransient Impedance, Junction-to-Ambient
2
I
II1I
:: Duty Cycle
0.5
-
0.2
~
==
....
Notes:
c::~
0.1
irLJL
0.05
~~
1. Duty
- O.j
0.Q1
10-4
V
10-3
Cyc:1e,'~ = 21.
'2
2. Pcr Umt Base = RthJA = 62.S o CIW
3. TJM - TA = PnMZthJA(')
4. Surface Mounted
~Single Pulse
II
10-2
10-1
I
I II 1 1111
10
1
30
Square Wave Pulse Duration (sec)
1-54
Preliminary
P-34118-Rev. C (04/04/94)
TEMIC
Si9939DY
Siliconix
Dual Enhancement-Mode MOSFETs (N- and P-Channel)
Product Summary
rDS(on) (Q)
In (A)
0.05 @ V GS = 10 V
±3.5
0.07 @ V GS = 6 V
±3
0.08 @ VGS = 4.5 V
±2.5
O.lO@VGs= -10V
±3.5
VDS(V)
N-Channel
30
P-Channel
0.12@VGS = -6V
±3
0.16 @VGS = -4.5 V
±2.5
-30
D1 D1
S2
H
0
0
SO-8
SI
Gl
S2
G2
0
D1
2
7
Dl
3
6
D2
4
5
D2
G1
o-1
~
G2,
~
~
H
~
:3
SI
ThpView
D2 D2
N-Channel MOSFET
P-Channel MOSFET
Absolute Maximum Ratings (TA = 2S o C Unless Otherwise Noted)
Parameter
Symbc>l
N-Channel
P-Channel
Drain-Source Voltage
VDS
30
-30
Gate-Source Voltage
VGS
±20
±20
±3.5
±3.5
±2.8
±2.8
IDM
±14
±14
Is
1.7
Continuous Drain Current (TJ = 150"C)
ITA = 25"C
ITA= 70"C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation
(Surface Mounted on FR4 Board)
ITA = 25"C
ITA=70"C
Operating Junction and Storage Thmperature Range
ID
Unit
V
A
-1.7
2.0
Po
1.3
W
TJ. Tstg
-55 to 150
"C
Symbol
N- or P- Channel
Unit
RtbJA
62.5
"C/W
Thermal Resistance Ratings
Parameter
Maximum Junction-to·Ambient (Surface Mounted on FR4 Board)
P-35258-Rev. B (05/16/94)
Preliminary
1-55
TEMIC
Si9939DY
Specifications (TJ
Siliconix
= 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
1YP"
Max
Unit
Static
Gate Threshold Voltage
Gate-Body Leakage
I N-Ch
VDS ~ VGs. ID ~ 250 IlA
VGS(th)
VDS ~ VGS. ID ~ -250 IlA
~
VDS
IDSS
~
-24 V, VGS
~
-15 V, VGS
~
OV
0 V, TJ
~
VDS" 5V,VGS
~
70'C
10V
s -5 V, VGS ~ -10V
VDS
ID(on)
~
VDS ., 5V, VGS
s
VDS
4.5 V
-5V,VGS~
~
~
-4.5 V
Forward 1ransconductanceb
Diode Forward Voltageb
-1
5
P-Ch
14
P-Ch
-14
N-Ch
3.5
P-Ch
-2.5
0.10
0.05
0.07
P-Ch
0.10
0.12
2.5 A
N-Ch
0.06
o.os
~
2A
P-Ch
0.13
0.16
VDS - 15 V, ID - 3.5 A
N-Ch
S
P-Ch
5
~
6V,ID
-6
~
V,ID~3A
VGS
~
4.5 V, ID
VGS
~
-4.5 V, ID
VDS
~
Is
~
Is
~
3A
-15 V, ID
~
~
1.7 A, VGS
-3.5 A
~
-1.7 A, VGS
OV
~
OV
IlA
A
N-Ch
3.5 A
nA
-5
N-Ch
0.04
VGS~
VSD
P-Ch
N-Ch
o.os
VGS
gf.
1
P-Ch
10V, ID
VGS~ -10V,ID~3.5A
roS(on)
N-Ch
N-Ch
VGS
Drain-Source On-State Resistanceb
V
±100
VDS ~ 15 V, VGS - 0 V, TJ - 70'C
VDS
On-State Drain Currentb
1.0
-1.0
VDS - Ov, VGS - ±20V
IGSS
VDs~24V,VGs~OV
Zero Gate Voltage Drain Current
I P-Ch
0.05
0
S
N-Ch
0.80
1.2
P-Ch
-O.SO
-1.2
N-Ch
i3
35
P-Ch
13
35
N-Ch
2.1
P-Ch
2.8
N-Ch
5.3
P-Ch
4.1
V
Dynamic"
Thtal Gate Charge
Og
Gate-Source Charge
Og.
VDS ~
N-Channel
10V, VGS ~ 10V,ID
VDS ~
Gate-Drain Charge
Thrn-On Delay TIme
Rise TIme
Thrn-Off Delay TIme
Fall TIme
Source-Drain Reverse Recovery TIme
~
3.5 A
P-Channel
-10 V, VGS ~ -10V
ID ~ -3.5 A
Ogd
td(nn)
tr
td(off)
N-Channel
VDD ~ 15 V, RL ~ 150
ID '" 1A, VGEN~ 10V,RG~60
P-Channel
VDD ~ -15 V, RL ~ 150
ID'" -1 A, VGEN ~ -10V,RG ~ 60
tf
IF ~ 3.5 A, di/dt ~ 100 NtIS
trr
nC
N-Ch
11
P-Ch
10
30
N-Ch
17
40
30
P-Ch
21
40
N-Ch
26
50
P-Ch
24
50
N-Ch
11
50
P-Ch
9
50
N-Ch
70
120
P-Ch
40
100
ns
Notes
a. Guaranteed by design. not subject to production testing.
b. Pulse test; pulse width s 300 tIS. duty cycle s 2%.
1-56
Preliminary
P-3525S-Rev. B (05/16/94)
TEMIC
Si9939DY
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
r
20
16
~
12
Q
"
8
.E
4
.~
1l-ansfer Characteristics
20
5V
VGS = 10,9,8,7,6 V
25'C
/~
16
~
$
"
B
Output Characteristics
$
"
~
12
Q
8
B
"@
"
4V
r
.E
2,1 V
3V
1-
0
2
0
4
6
8
0
2
0
10
VDS - Drain-to-Source Voltage (V)
4
On-Resistance vs. Drain Current
Capacitance
1600
II
0.16
8
.~"
0.12
VGs=4.5V
~
"
0
-
0.08
1
i
g
..,..V
G:' 1200
J
~
!l
.~
800
Co
a
6V
VGS
1
u
400
0.04
VGs= 10V
o
4
2
6
8
10
Co~
\
~
'--t
o
12
o
5
ID - Drain Current (A)
r"
8
~
6
~
liS
4
2
0
/
20
25
30
On·Resistance vs. Junction Temperature
_I.
I,
1.6
e,
8
;~
_"0
.f)l.§
1.2
~-a
", =
o~
...
/
0.8
1 ~
...-
~~
/
~
V
~
"
i
g
V
o
15
VGs= 10V
ID = 3.5 A
I
0
~
2.0
/
0
~
/
)
VGs=10 V
ID = 3.5 A
10
C;~
VDS - Drain-to-Source Voltage (V)
Gate Charge
10
--
~
s
I
0
~
8
VGS - Gate-to-Source Voltage (V)
0.20
e,
N·Channel
0.4
o
3
6
9
12
15
-50 -25
25
50
75
100
125
150
TJ - Junction Temperature COc)
Qg - Thtal Gate Charge (nC)
P-35258-Rev. B (05/16/94)
0
P:reliminary
1-57
TEMIC
Si9939DY
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
20
J
ITJ = 150 C
§:
II
I
, TJ=25'C
o
0.4
0.4
~
0.3
0
I
.:!i
Il
§
I
I
I
0.5
~
!?!-
E
"t::
0.2
!
e
11
On-Resistance vs. Gate-to-Source Voltage
0.6
10
(3
~:I
r5l
1.2
1.6
= 3.5 A
ID
I
0.1
\.....
o
0.8
N·Channel
2.0
o
Vsn - Source-to-Drain Voltage (V)
4
2
6
10
8
VGS - Gate-to-Source Voltage (V)
Threshold Voltage
Single Pulse Power
1.0
25
20
~
0.5
~
0.0
.~
I""-.... r--...
.........
I
ID = 250JlA,
.........
~
~
..........
..........
-0.5
-1.0
-50 -25
15
~
... ......
25
50
75
100
125
\
5
r-...
o I 111111111 111111111 1]]11111 111111111
L I_ - ' - - _ ' - - - - ' _ - ' - _ - ' - _ ' - - - - ' _ - '
0
\
10
150
0.01
10
0.1
TJ - Thmperature ('C)
100
Time (sec)
Normalized Thermal 'ftansient Impedance, Junction-to-Ambient
2
I
III
:: Duty Cycle = 0.5
-
0.2
E
-
~
...... ::~
0.1
0.05
....
Notes
HlJL
fo-:.l
~
I- 0.02
.,
I ~iigli f~l~~
10-3
-
f,-1
2 Pcr Unit Base =
3. TJM - TA = PDMZtb.rA(t)
RtbJA = 62S o C/W
I
0.01
10- 4
'2
1. Duty Cycle,D =
4. Surface Mounted
II
10-2
10- 1
I
I II11III
10
I
30
Square Wave Pulse Duration (sec)
1-58
Preliminary
P-35258-Rev. B (05/16/94)
TEMIC
Si9939DY
Siliconix
P-Channel
lYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
10
r/lVGS
= 1O!9,8, 7,6,
~V
u
I
$
$
E
E
4V
~
u"
/'
"
'@
Q
~
"
'§
....-
u
E
2
0
j
Q
V
I
E
Transfer Characteristics
10
3V
7-
r
o
4
2
2
2,1 V
8
6
Tc~",jJc
-
I
'25'C
2
4
o
o
10
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Capacitance
On-Resistance vs. Drain Current
0.20
J
J
8
1600
/
VGS = 4.5 V . /
S
1l
.'l"
.<'l
:J
0.16
. /V
0.12
VGS = 6V
0::
.:
0
G:' 1200
C
1l
-
"'"
.~
I
!
U
400
0.04
o
o
o
2
~
II'"
0.08
VGS = 10V
E!
Coss
800
10
I~"
o
5
Gate Charge
~
"
~
1
VGS = 10 V
ID = 3.5 A
8
~
~
"
'".9
/
0
"
OJ
d
~
4
2
0
/
o
/
/
/
2.0
/
"
.~ ~
"
-
O~
I
1.2
0.8
~
g
§
25
30
./
12
15
~
V
/'"
......
V-
0.4
o
-50
o
50
100
150
TJ - Junction Temperature eC)
Og - Total Gate Charge (nC)
P-35258-Rev. B (05/16/94)
20
I.
VGS = 10V
ID = 3.5 A
1l
'"~
_-0
9
15
1.6
S
/
6
10
-
On-Resistance vs_ Junction Temperature
0::, S
'"
3
--
c,,,
VDS - Drain-to-Source Voltage (V)
ID - Drain Current (A)
10
i'-....
Preliminary
1-59
TEMIC
Si9939DY
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
20
I
Tl= 150'C / ,
~
On-Resistance vs. Gate-to-Source Voltage
0.20
r(
~
e.
10
;;
8
I
r5l"
I
0.16
\
i
.!!l
I
~
P-Channel
~
.
Tl = 25'C
0.12
0
I
-
i
'"
~
"~ r--
~T
0.08
0.04
0
0.5
1.0
1.5
2.0
o
2.5
Vso - Source-to-Drain Voltage (V)
4
2
VGS
Threshold Voltage
8
6
10
Gate-to-Source Voltage (V)
-
Single Pulse Power
1.0
25
20
0.5
~
.~
15
~
0.0
~
~
10
\
-0.5
5
~
o I 111111111 111111111 TIIIIIIII 111111111
-1.0 I
-50
0
50
100
150
0.01
Tl - Thmperature ('C)
10
0.1
100
Time (sec)
Normalized Thermal 1l-ansient Impedance, Junction-to-Ambient
2
J
III
= Duty Cycle = 0.5
:-- 0.2
-
1"..00
0.1
==
0.05
-
I- 0.02
0.01
10-4
I
Single Pulse
./
10- 3
'"
::
-
~
...
~""'"
Notes.
~
~
1. Duly
I-:.l.!l.
Cycl.,'b =
'2
2. Per Unit Base = RtbJA = 62S o CIW
3. TJM - TA = POMZthrA(I)
~
4. Surfaa: M;""'~,
10-2
10-1
10
30
Square Wave Pulse Duration (sec)
1-60
Preliminary
P-35258-Rev. B (05/16/94)
TEMIC
Si9940DY
Siliconix
Dual N-Channel Enhancement-Mode MOSFET
Product Summary
rDS(on) (Q)
VDS(V)
0.05
50
@ V GS
O.D7@VGS
= 10 V
= 4.5 V
ID (A)
±5.3
±4.5
SO-16*
SI
DI
SI
DI
GI
DI
S2
D2
S2
D2
G2
D2
Top View
N-Channel MOSFET
N-Channel MOSFET
*Conforms to standard SO-16 dimensions
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
50
Gate-Source Voltage
VGS
±20
Unit
V
Continuous Drain Current (TJ = 150'C)
ITA=7O'C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation (Surface Mounted on FR4 Board)
±5.3
ITA=25'C
ID
A
±20
Is
2.5
2.5
ITA = 25'C
PD
ITA = 70'C
Operating Junction and Storage Temperature Range
±4.2
IDM
W
1.6
TJ. Tstg
-55 to 150
'c
Symb!>l
Limit
Unit
RthJA
50
'crw
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board)
P-37009-Rev. D (06/01/94)
1-61
TEMIC
Si9940DY
Siliconix
Specifications (TJ = 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
1YP"
Max
Unit
±100
oA
Static
Gate Threshold Voltage
loss
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(on)
Drain-Source On-State Resistanceb
Forward 'fransconductanceb
Diode Forward Voltageb
~
250 ~A
VDS~OV,Vos~
±20V
VDS
VOS(th)
Gate-Body Leakage
~
Vos. ID
1.0
V
2
VDS - 40 V, VOS - OV
VDS
~
40 V, Vos
~
Ov, Tl
~
~
55'C
25
20
A
VDS
2:
5V,Vos
Vos
~
10 V, ID
~
5.3 A
0.042
0.05
VOS
~
4.5 V, ID
~
4.5 A
0.055
0,07
!If.
VDS
~
15 V, ID
~
5.3 A
VSD
Is
'DS(on)
~
1.5 A, Vos
10V
~
11
OV
~A
0
S
0.8
1.2
30
50
V
DynamiC'
Thtal Gate Charge
Og
Gate-Source Charge
Q gs
Gate-Drain Charge
Ogd
1IIrn-On Delay Time
Rise Time
1IIrn-Off Delay Time
VDs~25V, Vos~1OV,ID~2
A
2.5
nC
9.4
td(on)
17
40
t,
30
60
95
150
55
100
td(ofl)
Fail Time
tf
Source-Drain Reverse Recovery Time
trr
VDD ~ 25 V, RL ~ 25 0
ID '" lA, VOEN ~ 10V,Ro ~ 60
IF
~
1.5 A,dildt
~ 100N~
ns
130
Notes
a. Guaranteed by design. not sUbject to production testing.
b. Pulse test; pulse width :$ 300~. duty cycle s 2%.
1-62
P-37009-Rev. D (06101/94)
TEMIC
Si9940DY
Siliconix
'iYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
20
~
U
"
8
~
.E
"":::
12
a
.~
8
~
V
4
0
~
r;
12
'§
16
)/'
~
"~
VGS = 10,9,8,7,6,5 V
4V
16
'Iransfer Characteristics
20
.E
4
3V
~
0
o
1
2
2
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
0.10
0.08
5
0.06 r-- VGs-4.5V
~
.>'l
~
= 0.04
0
2000
V
~
./
1500
J l\
500
o
o
12
16
20
24
o
28
ID - Drain Current (A)
.1
1.
.."
VDs=25V
8 ' - ID =2A
~
6
~
4
~
2
~
~
"0
~
d
0
/
/
V
2.0
V
"
c,."
20
10
30
40
50
On-Resistance vs. Junction Temperature
J J
VGS = lOV
~
8
1.6
./
I- ID = 5.3 A
[ii~
_'0
.~ .~ 1.2
~OI
, Ei
V
".
~~
!
I
1/
o
c.,..
.......
VDS - Drain-to-Source Voltage (V)
Gate Charge
10
~
~
U
0.02
8
c;"
1000
I
J
4
5
~
VGS-I0V
o
4
Capacitance
2500
/
~
3
VGS - Gate-to-Source Voltage (V)
§
0.8
~
....
V V
, V
,,/
0.4
o
5
10
15
20
Og - Thtal Gate Charge (nC)
P-37009-Rev. D (06/01/94)
25
30
-50 -25
0
25
50
75
100
125 150
TJ - Junction Temperature ("C)
1-63
TEMIC
Si9940DY
Siliconix
'tYPical Characteristics (25°C Unless Otherwise Noted)
~
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
20
0.08
Tll=15O'J~ /
,
10
~
I
8
@
=
r5l
I
-
I
"~.3A
25'C
I
'I
J
"'
Tl
I
I
I
J
I
:[
e
I
0.02
0.00
0.4
0.8
0.6
1.0
1.4
1.2
o
1.6
.~
20
r\
0.0
~
~
\
15
~
10
2S
0.5
~
8
6
Single Pulse Power
Threshold Voltage
1.0
2
VGS - Gate-to-Source Voltage (V)
VSD - Source-ta-Drain Voltage (V)
10
-0.5
i'...
5
-1 I
-SO
o
SO
0
100
150
I 111111111 111111111 1IIIIlIttt±tt!lli
0.Q1
Tl - Thmperature ('C)
100
TIme (sec)
Normalized Thermal 'fransient Impedance, Junction-to-Ambient
2
';;
.!l
10
0.1
I
II I
Duty Cycle
0.5
~8
F::;
0.2
.~1
~Ei
~'OE
1:"
=E 1.0
0
20
24
6
Og - Thtal Gate Charge (nC)
10
0.8
/
V
/
./
0
6
§
§
P-35337-Rev. C (05/02194)
c,."
.1.
1
2
8
Co"
Vas = 10V
V
o
-
On-Resistance vs. Junction Temperature
1.6
/
c:l
~
./
c,,,
VDS - Drain-to-Source Voltage (V)
Gate Charge
I
~
"-
ID - Drain Current (A)
10
10
\
.~
0.12
o
8
Capacitance
1000
1
eI
6
2
Vas - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
0.30
25'C
I
IJ
2
0
1251,C
J
4
E
'fij,1
~
~
;;
~
Te= -55'C
~
0.6
-50
V
o
50
100
150
TJ - Junction Temperature ('C)
1-75
TEMIC
Si9943DY
Siliconix
P-Channel
1Ypical Characteristics (25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
10
On-Resistance vs. Gate-to-Source Voltage
0.5
/
/
/
/
/
/
$
/L
TJ = 150'C
E
J /
/ 1
~
a
~
0
0.5
/I
1.0
0.4
.!!a
0.3
B
1\
3
I>;:
TJ = 25'C
Ii
r5l"
e-8
0
"
0.2
J
0.1
o
1.5
2.5
2.0
3.0
........
o
.i
10
15
r\
10
i"I
-0.5
"...
I
o I 111111111 111111111 I IIl11W"
-1
-50
0
50
100
150
0.01
0.1
III
E
==
~lii
- o.d
.,,,,
'E:~
.ll-
DutyCycle
0.5
-
0.1
0.1 ~ 0.05
-
1~
!i""
=0.02
:z:
100
TIme (sec)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
.~ 8
IllItml
10
TJ - Temperature ('C)
"Bl>
8
6
20
~
iill
-
25
0.0
~
~
----
Single Pulse Power
Threshold Voltage
0.5
~
4
2
= 2.8 A
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
1.0
ID
Notes.
HlSL
f-:.j
~
'7 ~single Pulse
10-5
10- 4
tl
3. TJM - TA = PDMZrhIA(t)
4. Surface Mounted
I 1111111
0.01
t2
~.:~~:~ = Rtb!= 62SQOW
10-3
10- 1
3
Square Wave Pulse Duration (sec)
1-76
P-35337-Rev. C (05/02/94)
TEMIC
Si9944DY
Siliconix
Dual N-Channel Enhancement-Mode MOSFET
Product Summary
rnS(on) (Q)
In (A)
6@VGs= 10V
±OA
8@VGs =4.5V
±0.3
Vns(V)
240
DI DI
D2 D2
80-8
SI
GI
S2
G2
0
DI
2
7
DI
3
6
D2
4
5
D2
GI~
G2~
~
0
0r;..
~
ThpView
S2
SI
N-Channel MOSFET
E-4
N-Channel MOSFET
~
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
240
Gate-Source Voltage
Vas
±20
Continuous Drain Current (TJ
~
ITA~ 25'C
150'C)
ITA ~ 70'C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Operating Junction and Storage Thmperature Range
ITA~ 70'C
V
±0.4
ID
±0.3
IDM
±1.8
Is
04
ITA ~ 25'C
Maximum Power Dissipation (Surface Mounted on FR4 Board)
Unit
A
2
PD
W
1.3
T),Tstg
-55 to 150
'C
Symbol
Limit
Unit
RthJA
62.5
'c/w
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board)
P-35421-Rev. C (06/06/94)
1-77
TEMIC
Si9944DY
Specifications (TJ
Siliconix
= 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
0.5
'lyP"
Max
Unit
±100
nA
Static
Gate 'Threshold Voltage
VGS(tb)
VDS = VGS, ID = 250!lA
Gate-Body Leakage
IGSS
VDS = Ov, VGS = ±20V
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(on)
Drain-Source On-State Resistanceb
FOlWard 1l'ansconductanceb
Diode FOlWard Voltageb
roS(on)
V
VDS = 190V,VGS = OV
1
VDS = 190 V, VGS = Ov, TJ = 55°C
25
VDS ., 25 V, VGS = 10V
1.8
!lA
A
VGS = 10 V, ID = 0.4 A
2.8
6
VGS - 4.5 V, ID - 0.3 A
3.1
8
Sf,
VDS = 15V, ID = 0.4 A
0.6
VSD
Is =0.4 A, VGS = OV
0.75
1.2
4.6
6.0
VDS = 60 V, VGS = 10V, ID = 0.4 A
0.17
g
S
V
Dynamic"
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
111m-On Delay TIme
Rise TIme
111m-Off Delay TIme
Fall TIme
5
td(on)
tr
td(off)
tf
nC
1.75
VDD = 60V,RL = 150g
ID = 0.4 A, VGEN = 10 V, RG = 25 g
10
5
10
20
30
14
W
ns
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width s 300 I's, duty cycle S 2%.
1-78
P-3S421-Rev. C (06/06/94)
TEMIC
Si9944DY
Siliconix
'iYpical Characteristics (25°C Unless Otherwise Noted)
'fransfer Characteristics
Output Characteristics
20
J
f
I
r
1.6
~
;;
~
"
"§
1.2
u
Q
E
08
!
VGs=7,6,5V
1.6 r---,.---,----,.---,...-,...--.----,
J-
1.2
0.8 f---\---t---+...--t----t----i
3V
041--+--+~~+---r--1-~
'/'"
0.4
I--+--+--+---j~
2~
o
o
10
20
30
40
o
50
On-Resistance vs. Drain Current
e.
400
~
5
.!!l
~
3
0
2
~
V
V
~
~
VGS
I
VGS =OV
/
-- - -- --
VGS = 4.5V
lOV
320
G;'
.:;,
~
240
a
160
.~
~
I
!
U
E!
80
o
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
€
Gate Charge
"
~
~
6
r--
"
B
u
0
til
4
""
~
~
/
/
V
e.
~
"'~
-"tI
'5~
1.5
C
II
h
~~
1.0
I
0.5
o
0
2
3
4
Og - Thtal Gate Charge (nC)
P-3S421-Rev. C (06/06/94)
V
~'"
, 8
2
o
Jl
VGs= lOV
2.0 , - - io=0.3A
~
/
~
40
50
On-Resistance vs. Junction Temperature
2.5
/
Vos=60V
io = 0.4 A
30
20
VOS - Drain-to-Source Voltage (V)
I
8
bQ
Coss
10
io - Drain Current (A)
10
C;"
~
0
o
6
Capacitance
5
4
3
2
VGS - Gate-to-Source Voltage (V)
VOS - Drain-to-Source Voltage (V)
5
V
o
V
./
/
./
25
50
75
100
125
150
TJ - Junction Temperature (0C)
1-79
TEMIC
Si9944DY
Siliconix
'JYpical Characteristics (25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
1000
s
8"
fTJ
10
150'C
100
8
ej
I
On-Resistance vs. Gate-to-Source Voltage
V
ID=0.5A
6
.!!J
~
.
~
"
'"
0
0
-
4
\
I
10
'"
TJ
J
25'C
2
-
~=1.0A
ID=10.1A
0
0.5
0
1.0
1.5
2.0
o
2.5
Threshold Voltage
1.0
~
20
Single Pulse Power
20
15
~
0.0
~
~
16
25
0.5
~
12
4
Vas - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
f\
10
-0.5
~
......
I
-1
-50
0
50
100
o
150
I 111111111 IIIIIIIII 1ll1tttHHill1
0,01
0.1
10
TJ - Thmperature ('C)
100
TIme (sec)
Normalized Thermal 'll-ansient Impedance, Junction-to-Ambient
2
I
1= Duty Cycle
r-
II II
0.5
0.2
O.~
I- t:~
!;.o!lI
-~
1= 0.05
I::!iiIIIII
Notes:
BlIL
I-:.j
~
..,.
I-- 0.02
I
10- 5
/
10-4
t2
=
=
=
t1
1.DutyCycle,D=
t2
-
2. Per Unit Base = RtbIA = 62 S° C/W
L
0.01
-
3. TJM - TA
~in~er~~s711
I,
10-3
10-2
10- 1
,
-
=PDMZtbJA(t)
4. Surface Mounted
"'" "'
,
3
Square Wave Pulse Duration (sec)
1-80
P-35421-Rev. C (06/06/94)
TEMIC
Si9945DY
Siliconix
Dual N-Channel Enhancement-Mode MOSFET
Product Summary
rnS(on) (Q)
In (A)
O.lO@VGs= lOV
±3.3
0.20@ VGS = 4.5 V
±2.5
Vns(V)
60
DI DI
D2 D2
SO-8
SI
GI
S2
G2
0
DI
2
7
DI
3
6
D2
4
5
D2
GI~
G2~
E-4
0
0
~
f;ril
ThpView
SI
~
S2
E-4
E-4
N-Channel MOSFET
N-Channel MOSFET
::3
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
60
Gate-Source Voltage
VGS
±20
Unit
V
±3.3
ITA = 25'C
Continuous Drain Current (TJ = 150'C)
ID
ITA=70°C
Pulsed Drain Current
Continuous Source Current (DIode Conduction)
Is
Maximum Power Dissipation (Surface Mounted on FR4 Board)
10
1.7
2.0
ITA=25'C
PD
ITA=70'C
Operating Junction and Storage Temperature Range
±2.6
A
IDM
1.3
W
Tr, Tstg
-55 to 150
'C
Symbol
Limit
Unit
RthIA
62.5
'c/w
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board)
P-34120-Rev. D (04/04/94)
Preliminary
1-81
TEMIC
Si9945DY
Specifications (TJ
Parameter
Siliconix
-
25°C Unless Otherwise Noted)
Symbol
Test Condition
Min
1.0
'IYP"'
Max
Unit
±100
nA
Static
VGS(lh)
VDS = VGS, ID = 250 i'A
Gate-Body Leakage
IGSS
VDS= OV,VGS= ±20V
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(o,)
Gate Threshold Voltage
Drain-Source On-State Resistanceb
Forward Transconductanceb
DIode Forward Voltage b
VDS = 48 V, VGS = OV
1
VDS - 48 V, VGS - 0 V, TJ - 55°C
25
VDS:>: 5V,VGS = 10V
roS(o.)
V
10
i'A
A
VGS - 10 V, ID - 3.3 A
0.10
VGS = 4.5 V, ID = 2.5 A
0.20
gf.
VDS = 15 V, ID = 3.3 A
7.0
VSD
Is = 1.7 A, VGS = OV
0.8
1.2
15
30
VDS = 30 V, VGs=1OV,ID=3.3 A
2.1
Q
S
V
Dynamic"
Thtal Gate Charge
Qg
Gate-Source Charge
Q gs
Gate-Drain Charge
Qgd
Thrn-On Delay TIme
Rise TIme
Thrn-Off Delay TIme
nC
4.5
td(on)
9
25
tr
10
30
25
50
14
40
70
100
VDD = 30V,RL = 30Q
ID" lA, VGEN = 10V,RG = 6Q
td(off)
Fall TIme
tf
Source-Drain Reverse Recovery Time
trr
IF = 1.7 A, di/dt - 100 NilS
ns
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width S 300!'S, duty cycle s 2%.
1-82
Preliminary
P-3412(}-Rev. D (04/04/94)
TEMIC
Si9945DY
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
20
lv vG~
,
16
12
"eQ"
8
8
E
0
I.
1
= 9,8,7,16 V
5V
"
"
.~
Q
J
Ik
12
E
4V
8
4
3V
0
o
2
10
2
0
4
On-Resistance vs. Drain Current
1000
0.4
800
fi:'
,e,
8
8
"
.!:!
0.3
~
i:
0
l
--
0.2
-
0.1
o
J
.~"
VGs=4.5V
a-
I
.,/
600
400
I
1
VGs=lOV
U
200
o
o
2
6
8
10
"-
E
Vn~ =60V I
In = 0.4A
8
V
~
~
"
~
6
~
4
~
2
"
0
2.0
V
\..J:--
o
10
40
50
On-Resistance vs. Junction Temperature
V~S=l~V
/'
1.6
e8
lii~
_-0
1.2
"~
0:£
I
0.8
l
0.4
.~]
i>: os
,e
L
~
/
o
30
20
In = 3.3 A
/'
0
J
Coss
Vns - Drain-Io-Source Vollage (V)
Gate Charge
10
c,,,
\~
In - Drain Currenl (A)
~
...
10
Capacitance
0.5
.:!l
4
2
VDS - Drain-to-Source Voltage (V)
0.6
I
~
4V
2
~L~5'C
-55'C_
$
c
Q
Te l = 125'C I
4
7V
$
~
u"
.~
'Iransfer Characteristics
...-------':...-,r_----.-----.---,
20
1.2
1.0
0.8
./
0.6
-50
V
/'
-10
30
J
/
70
110
150
TJ - Junction Temperature ("C)
1-97
TEMIC
Si9950DY
Siliconix
P-Channel
lYpical Characteristics
(25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
10
On-Resistance vs. Gate-to-Source Voltage
0.6
I--- TJ
/
/
0.5
e.-
150'C,
I/TJ=25'C
j
0.4
~C
0.3
ID=lA
0
1
-
II
'"
~
0.1
J
I
I
I
o
0.4
\.
0.2
0.1
J
0
0.8
1.6
1.2
a
2.0
4
Threshold Voltage
Single Pulse Power
20
0.5
r-
15
~
0.0
~
~
~
16
25
1.0
.i
12
V GS - Gate-ta-Source Voltage (V)
VSD - Source-ta-Drain Voltage (V)
€
8
10
-0.5
J 111111111 111111111"IIIrnH±lII
5
I
-1
-50
o
50
100
150
001
0.1
10
TJ - Thmperature ("C)
100
TIme (sec)
Normalized Thermal Transient Impedance, Junction-to-Ambicnt
2
11,111
1= Duty Cycle
0.5
--
0.2
0.1
0.05
....- 1...,... .....
0.02
V
0.01
10-5
I
Notes:
BlSL
~ I-::.l
tz
t
1. Duty Cycle. D
{
2. Per UmlBase "" Rth1A = SsoC/W
3. T,M - TA = PDMZthJA(t)
Single Pulse
f I III
4. Surface Mounted
10-4
10-3
10-2
10- 1
3
Square Wave Pulse Duration (sec)
1-98
P-34826-Rev. E (05/16/94)
TEMIC
Si9952DY
Siliconix
Dual Enhancement-Mode MOSFET (N- and P-Channel)
Product Summary
Vns(V)
25
N-Channel
-25
P-Channe1
rnS(on) (Q)
In (A)
0.10@VGs= lOV
±3.5
0.15 @VGS = 4.5 V
±2.0
0.25 @ VGS = -10 v
±2.3
0.40@ VGS = -4.5 V
±1.8
Recommended upgrade: Si9939DYor Si9943DY
Lower profile/smaller size-see LITE FOOT m equivalent: Si6942DQ
S2
E-c
80-8
SI
GI
S2
G2
0
2
0
0
DI
7
DI
3
6
D2
4
5
D2
~
G21
f;;;':I
G1o---J
~
E-c
::3
ThpView
SI
D2 D2
N-Channel MOSFET
P-Channel MOSFET
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
N-Channel
P-Channel
Drain-Source Voltage
VDS
25
-25
Gate-Source Voltage
VGS
±20
±20
±3.5
±2.3
Continuous Drain Current (TJ = 150'C)
ITA=25'C
ITA = 70'C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation
(Surface Mounted on FR4 Board)
ID
±2.8
±1.9
IDM
±14
±9.2
Is
1.7
V
A
-16
2.0
ITA = 25'C
PD
ITA = 7D"C
Operating Junction and Storage Temperature Range
Unit
W
1.3
TJ,T,tg
-55 to 150
'C
Symbol
N- or P-Channel
Unit
RthJA
62.5
'c{w
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board)
P-34826-Rev. E (05/16/94)
1-99
TEMIC
Si9952DY
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Test Condition
Symbol
Min
'lYP"'
Max
Unit
Static
Gate Threshold Voltage
Gate-Body Leakage
VGS(tb)
Vos = VGS, 10 = 250!1A
N-Ch
1.0
Vos = VGS, 10 = -250!1A
P-Ch
-1.0
VOS=OV,VGS= ±20V
IGSS
VOS = 20 V, VGS = OV
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 1ransconductanceb
Diode Forward Voltageb
VOS = -20 V, VGS = OV
loss
V
Vos = 20 V, VGS =
ov, TJ = 55'C
±100
N-Ch
2
P-Ch
-2
N-Ch
25
Vos = -20 V, VGS = OV,TJ = 55'C
P-Ch
VOS '" 5V,VGS = 10V
N-Ch
3.5
VOs'" -5 V, VGS = -10V
P-Ch
-2.3
Io(on)
roS{on)
8fs
Vso
nA
!1A
-25
A
VGS = 10 V, 10 = 1A
N-Ch
0.08
VGS--lOV, Io=lA
P-Ch
0.13
0.25
VGS = 4.5 V, 10 = 0.5 A
N-Ch
0.12
0.15
VGS = -4.5 V, 10 = 0.5 A
P-Ch
0.20
0.40
Vos = 15 V, 10 = 3.5 A
N-Ch
5.0
VOS - -15 V, 10 - -3.5 A
P-Ch
3.2
Is = 1.25 A, VGS = OV
N-Ch
1.1
1.4
Is = -1.25 A, VGS = OV
P-Ch
-1.2
-1.6
0.10
Q
S
V
Dynamlca
Thtal Gate Charge
Og
N-Channel
Vos = 12.5 V, VGS = 10 V, 10 = 2.3 A
Gate-Source Charge
Gate-Drain Charge
Thrn-On Delay Time
Rise Time
Thrn-Off Delay Time
Fall Time
Ogs
P-r:hannel
Vos = -12.5 V, VGS = -lO V, 10 = -2.3 A
Ogd
td(on)
N-Channel
Voo = 25 V, RL = 25Q
10'" lA, VGEN = 10V,RG = 6Q
tr
td(off)
P-Channel
Voo = -25 V, RL = 25Q
10'" -lA,VGEN= -lOV,RG=6Q
tf
N-Ch
9.4
27
P-Ch
8.4
25
N-Ch
1.6
P-Ch
1.3
N-Ch
3.1
P-Ch
3.0
N-Ch
9
P-Ch
12
40
N-Ch
8
20
trr
Ip = 1.25 A, di/dt = 100 N""
20
P-Ch
19
40
N-Ch
45
90
P-Ch
42
90
N-Ch
25
50
P-Ch
27
50
69
100
N-Ch
Source-Drain Reverse Recovery Time
nC
P-Ch
ns
75
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width '" 300 liS, duty cycle", 2%.
1-100
P-34826-Rev. E (05/16/94)
TEMIC
Si9952DY
Siliconix
N-Channel
TYpical Characteristics
(25°C Unless Otherwise Noted)
Output Characteristics
16
:sc
~
6V
...".--
14
8
12
:s
U
SV
o@
Q
.E
'fransfer Characteristics
10
Vas = 10,9,8, 7V
V
4
0
I
2
4V
3V
0
o
3
2
4
r---_+----~----r---_+----~
o
Vos - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
0.12
'"
0
800
\;\----+---+----+----1
~
600
I--'~--_+_----_+------r------j
J
400
~~r-_I_=::::::~""'"'--...,.--~
200
!,,-t---i""""'-'l;;;;;;;;;;;;:::::::1
I
!
e
10
0.15
.!!l
~
8
Capacitance
1000
0.18
ej
6
4
2
Vas - Gate-to-Source Voltage (V)
U
VGs=10V
0.09
006
0
2
4
6
8
10
10
10 - Drain Current (A)
_,
10
~
g,
!l
~
§
:s
8 -
l
Gate Charge
VOS = 12.5 V
10= 2.3 A
6
/
)
0
til
g
b
OJ
4
2
0
II
2
4
e-8
1.4
/----j----r---+----1
N",:!
.!!l
~';i
~
E
1.2 /----+---+--""'~--__l
O~
I~
J
6
8
Q g - Thtal Gate Charge (nC)
P-34826-Rev. E (05/16/94)
Vas=10V
1D=2.2A
~
/
o
20
On-Resistance vs. Junction Temperature
1.6
/
Cl
~
/
15
VDS - Drain-to-Source Voltage (V)
10
12
1.0
f---+----:I''''--+----+----J
0.8
L -_ _ _ _- ' -_ _ _ _--'-_ _ _ _ _ _L -_ _ _ _- '
-50
0
50
100
150
TJ - Junction Temperature ("C)
1-101
TEMIC
Si9952DY
Siliconix
1Ypical Characteristics
N-Channel
(25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
20
g
I
TJ - 15JC
10
;;
~
On-Resistance vs. Gate-to-Source Voltage
0.20
~~
e-
0.16
!!
0.12
TJ = 25°C
'il!
~
\
§
8
I
~
I
I
"
I-
I
c!:
I
0
til
0
.,
o
0.8
0.4
I
I
I
1
0.08
0.04
0.00
1.2
1.6
o
2.0
VSD - Source-to-Drain Voltage (V)
~
§
.
~
4
6
8
10
Single Pulse Power
25
20
0.5
15
0.0
~
~
2
VGS - Gate-to-Source Voltage (V)
Threshold Voltage
1.0
-
I
/ I
I
,;:
&!
i\
10
-0.5
-'r100.
I
-1
-50
0
50
100
o
150
0.Q1
0.1
10
TJ - Thmperature CC)
Normalized Thermal 'fransient Impedance, Junction-to-Ambient
2
;;
I
IIII
.2
Duty Cycle
F:~
0.2
0.5
~8
0'0
.~~
-...
~E
~
Notes:
jj-
mIL
f-::.l
0.1
0.1
il"
~~
0.05
~"
I. DutyCyc:le,D
-
0.02
§
Z
100
TIme (sec)
2.PerUnltBase=R~=62SoC/W
Li""'"
3 TJM - TA = PDMZthJA(t)
Single Pulse
'I
0.01
10-5
,.'
I
-
::
:
-
-
4 Surface Mounted
I I
10-4
10-3
10-2
10-1
3
Square Wave Pulse Duration (sec)
1-102
P-34826-Rev. E (05/16/94)
TEMIC
Si9952DY
Siliconix
'fYpical Characteristics
P-Channel
(25°C Unless Otherwise Noted)
I#:
Output Characteristics
20
... 7V
16
IVV
$
C
":::
8
~
.E
1ransfer Characteristics
10
ViS ;10, 9, 8 V
12
10
8
6V
6
5V
r
8
4
r-----r_----~~
4
r-----r_--~r_----r_----r_--~
4V
2
......
3V
0
0
6
4
2
8
o
10
o
2
VDS - Drain-la-Source Vollage (V)
On-Resistance vs Drain Current
0.8
IVGS;4.5J
e.
j
~
!l
5
o
2
200
\
600
'g
a
I
U
VGS; 10V
o
400
,e,
,/
0.2
4
o
8
E
n"
8
§
6
r--
VDS; 12V
io; 2.3A
./
~
"
'".9
a
/
~
2
0
/
8
!l.
1.4
~
_'t:I
66
Ie.
Qg - Thlal Gale Charge (nC)
10
,
L
.,;'"
, Ei 1.2
./
1.0
0.8
4
.I .L
·5~
E!
P-34826-Rev. E (05/16/94)
20
16
VGS; 10V
io;2A
e.
,/
:[
2
12
24
On-Resistance vs. Junction Temperature
~
V
o
Co..
c,...
o
1.6
/
t!l
~
V
./
~ I"---
VOS - Drain-la-Source Vollage (V)
Gate Charge
I
c;..
"'-
iD - Drain Current (A)
10
10
\
\\
\
G;'
)
0
J
/
/
0.4
8
Capacitance
1000
800
0.6
6
V GS - Gate-la-Source Voltage (V)
./
-50
,,/
/
I
V
;/
o
50
100
150
TJ - Junction Temperature ee)
1-103
TEMIC
Si9952DY
Siliconix
P-Channel
1YPical Characteristics
(25°C Unless Otherwise Noted)
S
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
20
_I
10
1
~
Tr - 15
, ,
"
/ /
8""@
-?
/
"
'"
/
0
25'C
If
'"
/I
0.5
1.0
e!-
0.30
.1
~
.
0
0.20
~
\:D=2.3A
i"'--
J
II
-
0.40
e!
0.10
0.00
1.5
2.0
2.5
o
3.0
€
Threshold Voltage
20
0.5
15
0.0
\
10
1\
-0.5
5
-J
-so
so
0
100
o
150
0,01
10
0.1
100
TIme (sec)
Normalized Thermal 'fransient Impedance, Junction-to-Antbient
2
.2
"~8
= Duty Cycle
Fltii
"il8'
r-
III
0.5
i
0.2
.E;
il5
~~
-
-"
Tr - Thmperature ('C)
Jl~C;
10
Single Pulse Power
:s
I
8
25
8
tii
~
6
2
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
1.0
---
Notes:
HlSL
f-:.l
0.1
0.1 C::: 0.05
-
~
~0.02
~
10-5
t2
3. TJM - TA = POMZtb.JA(t)
lilLlJIL
10-4
...!1.
2. PerUmt Base = RthJA = 62.S o Crw
p.- ~single Pulse
0.01
t2
1.DutyCycle,D-
4. Surface Mounted
10-3
10-2
10-1
3
Square Wave Pulse Duration (sec)
1-104
P-34826-Rev. E (05/16/94)
TEMIC
Si9953DY
Siliconix
Dual P-Channel Enhancement-Mode MOSFET
Product Summary
fnS(on) (Q)
In (A)
0.25 @ VGS = -10 V
±2.3
0.40@VGS = -4.5 V
±1.5
Vns(V)
-20
Lower profile/smaller size-see LITE FOOT'" equivalent: Si6953DQ
SI
S2
SO-8
SI
G1
S2
G2
0
2
E-4
Dl
7
D1
3
6
D2
4
5
D2
G21
GIl
0
0f;o,j
~
-
ThpView
D1 D1
E-4
D2 D2
P-Channel MOSFET
~
P-Channel MOSFET
Absolute Maximum R.atings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
Vns
-20
Gate-Source Voltage
VGS
±20
Continuous Drain Current (TJ = 150°C)
In
Continuous Source Current (Diode Conduction)
ITA=7O°C
Operating Junction and Storage Temperature Range
±1.8
InM
±10
Is
-1.6
A
2.0
ITA=25°C
Maximum Power Dissipation (Surface Mounted on FR4 Board)
V
±2.3
ITA = 25°C
ITA=7O°C
Pulsed Drain Current
Unit
Pn
1.3
W
TJJ Tstg
-55 to 150
°C
Symbol
Limit
Unit
R,hJA
62.5
°CIW
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board)
P-34122-Rev. F (04104/94)
1-105
TEMIC
Si9953DY
Siliconix
Specifications (TJ - 25°C Unless Othernise Noted)
Parameter
Symbol
Test Condition
Min
-1.0
1yP"
Max
Unit
±100
nA
Static
Gate Threshold Voltage
VGS(th)
Vos = VGS, 10 = -250!,A
Gate-Body Leakage
IGSS
Vos=OV,VGs= ±20V
Zero Gate Voltage Drain Current
loss
On-State Drain Currentb
IO(on)
Drain-Source On-State Resistanceb
-0.50 i - - - - t - - - - + - - - - - j - - - - j
5
-1.00
L I_ - - ' _
JIIIIIIIIIIIIIIII""~1
-'--_--L_--'
_
o
-SO
So
100
....... ~
150
0.01
0.1
10
TJ - Thmperature ('C)
100
T!me(sec)
Normalized Thermal 'fran.ient Impedance, Junction-to-Ambient
2
I
III
Duty Cycle - 0.5
--
0.2
~iiii
0.1
0.05
.....!""'"
10-5
..!l.
t2
1. DulycycIe,D
t,
2. Per Unit Base = RtbJA = 62.S0crw
3 TJM - TA = PDMZtb.rA(t)
Single Pulse
I
mIL
I-:.l
~
0.02
0.01
Notes:
I
4 Surface Mounted
I I
10- 4
10-3
10-2
10-1
3
Square Wave Pulse Duration (sec)
1-112
P-34985-Rev. E (04/11/94)
TEMIC
Si9956DY
Siliconix
Dual N-Channel Enhancement-Mode MOSFET
Product Summary
rnS(on) (Q)
Vns(V)
OolO@VGS
20
0020@VGS
= lOV
= 4.5 V
In (A)
±3.5
±20O
Recommended upgrade: Si9936DY
Lower profile/smaller size-see LITE FOOT'" equivalent: Si6956DQ
80-8
S1
G1
S2
G2
0
D1
Z
7
D1
3
6
D2
4
5
D2
Top View
N-Channel MOSFET
N-Channel MOSFET
Absolute Maximum R.atings (TA = 25°C Unless Otherwise Noted)
Symbol
Parameter
Limit
Drain-Source Voltage
VDS
20
Gate-Source Voltage
VGS
±20
Unit
V
Continuous Drain Current (TJ = 150'C)
±3.5
ITA=25'C
ID
ITA= 70'C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Is
PD
ITA=70'C
Operating Junction and Storage Temperature Range
±14
1.7
200
ITA=Z5'C
Maximum Power Dissipation (Surface Mounted on FR4 Board)
±208
A
IDM
W
1.3
TJ,Tstg
-55 to 150
Symbol
Limit
Unit
RthJA
62.5
'c/w
'C
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board)
P34826-Revo G (05/16/94)
1-113
TEMIC
Si9956DY
Siliconix
Specifications (TJ = 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
1.0
lYP'
Max
Unit
±100
nA
Static
Gate Threshold Voltage
VGS(th)
VDS = VGS, ID = 250 itA
Gate-Body Leakage
IGSS
VDS= OV,VGS= ±20V
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward Transconductanceb
Diode Forward Voltage b
ID(on)
V
VDS = 16 V, VGS = OV
2
VDS -16 V, VGS - Ov, TJ - 55°C
25
VDS
2:
5V,VGS = 10V
14
A
V GS - 10 V, ID - 2.2 A
0.08
0.10
V GS = 4.5 V, ID = 1 A
0.12
0.20
gfs
VDS = 15 V, ID = 3.5 A
5.2
VSD
Is = 1.25 A, VGS = OV
0.9
1.4
9
30
VDs=lOV, VGS= 10V,ID = 1.8 A
0.7
rDS(on)
itA
Q
S
V
Dynamic"
Total Gate Charge
Qg
Gate-Source Charge
Q gs
Gate-Drain Charge
Qgd
nun-On Delay Time
Rise Time
Thrn-Off Delay Time
5
td(on)
tT
td(off)
Fall Time
tf
Source-Drain Reverse Recovery Time
trr
nC
3.5
VDD = 10 V, RL = 10 Q
ID" lA, VGEN=10V,RG=6Q
IF = 1.25 A, di/dt = 100 NIls
20
12
20
18
90
10
50
60
100
ns
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width :5 300 Ils, duty eycle :5 2%.
1-114
P34826-Rev. G (05/16/94)
TEMIC
Si9956DY
Siliconix
1:ypical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
Transfer Characteristics
16,-----,-----,---~rT--_,r---_,
20
16
~
"~
12
"
U
co
.f!
c:l
.E
8
4
0
0
5
4
3
2
o
6
2
On-Resistance vs. Drain Current
/
0.16
Capacitance
0.12
0
0.08
~
l
600
vlF4.5v
V
Ii::'
.e:
../
co
.~
1lco
.~
VGs= 10V
500
400
a
300
U
200
I
j
g-
2
8
1\
2.0
"'-
-
c,..
Coss
Cr...
B
~
1.0
I
2
On-Resistance vs. Junction Temperature
! J.
I--- ~
0.5
V
o
20
15
1.5
/
"
0
til
10
VGs= 10V
ID =2.2A
I
6
0
~
VDS - Drain-Io-Source Vollage (V)
j'
VDs=10V
r- ID = 1.8 A
E
~
""""0::1
o
10
Gate Charge
1-
~
~
I~
0
o
10
"
l\
100
ID - Drain Currenl (A)
~
\
0.04
o
10
8
700
0.20
e-8
6
4
VGS - Gale-la-Source Vollage (V)
VDS - Drain-la-Source Voltage (V)
-
-'
V
~
/
o
2
6
8
Og - Tolal Gale Charge (nC)
P34826-Rev. G (05/16/94)
10
-50 -25
0
25
50
75
100
125
150
TJ - Junction Temperature ("C)
1-115
TEMIC
Si9956DY
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
S
...
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
20
v
10
"I::
8
0.20
~
e..
j
"
~.
II
~
I-- TJ
"
=150'C I I
I
0
,
CI)
/I
I
'"
0
TJ
=25'C
o
'"
1.2
1.6
"-
2.0
o
2
VSD - Source-to-Drain Voltage (V)
~
~
0.5
0.0
100
""- ""-
I"'--
:d'
c,
~
-0.5
--'
~
ID = 2501lA - -
.......... ['-...
6
8
10
Single Pulse Power
140
120
~
4
VGS - Gate-to-Source Voltage (V)
Threshold Voltage
1.0
~3.5A
0.04
o
0.8
0.4
\
0.12
0.08
l
I
0.16
!
\
\
80
60
40
"
,
20
-1.0 - - ' - - - ' _ . L - - L - - . . l . . . - - - L - L - - - . J
-50 -25
0
25
50
75 100 125 150
'\~
r--.
L.I
0.001
TJ - Thmperature ('C)
=
"a8
Fia
.=!fllS"
.ll~1
""
II
0.5
-
0.1
=:::0.05
Z
0.01
--(1
10-4
~
c:~
0.1
1~
10
11111
DutyCyc1e
-0.2
...
0.100
TIme (sec)
Normalized Thermal 'Iransient Impedance, Junction-to-Ambient
2
.~
0.010
Notes:
HlSL
f-:.l
~
1. Duty
3. TJM - TA = PnMZthJ"A(t)
...... Single Pulse
10-3
Cycle.t~ = ...!!.
12
2. Per Unit BIIS6 = RthJA;::: 62 soC/W
."..
4. Surface Mounted
10-2
10- 1
10
30
Square Wave Pulse Duration (sec)
1-116
P34826-Rev. G (05/16/94)
TEMIC
Si9958DY
Siliconix
Dual Enhancement-Mode MOSFETs (N- and P-Channel)
Product Summary
rDS(on) (Q)
ID (A)
O.lO@VGs=lOV
±3.5
VDS (V)
N-Channel
0.12@VGS = 6 V
±3
0.15 @VGS = 4.5 V
±2.5
0.10@VGS = -lOV
±3.5
0.12@VGS = -6V
±3
0.19 @VGS = -4.5 V
±2.5
20
P-Channel
-20
Dl 01
S2
~
80-8
SI
Gl
S2
G2
0
0
0
01
2
7
01
3
6
02
4
5
02
Gl
o-1
~
G2i
r.:l
~
~
~
:s
Top View
SI
02 02
N·Channel MOSFET
Absolute Maximum Ratings (TA
P-Channel MOSFET
= 25°C Unless Otherwise Noted)
Parameter
Symbol
N-Channel
P-Channel
Drain-Source Voltage
VDS
20
-20
Gate-Source Voltage
VGS
±20
±20
±3.5
±3.5
±2.8
±2.8
IDM
±14
±14
Is
1.7
Continuous Drain Current (TJ = 150°C)
ITA = 25°C
ITA = 700C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation
(Surface Mounted on FR4 Board)
ITA = WC
ITA = 70°C
Operating Junction and Storage Temperature Range
ID
Unit
V
A
-1.7
2.0
PD
W
1.3
T], Tstg
-55 to 150
°C
Symbol
N- or P-Channel
Unit
RthJA
62.5
0c/w
Thermal Resistance Ratings
Parameter
Maximum Junction-to·Ambient (Surface Mounted on FR4 Board)
P-34125-Rev. E(04/04/94)
1-117
TEMIC
Si9958DY
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Test Condition
Symbol
Min
1YP"
Max
Unit
Static
Gate Threshold Voltage
Gate-Body Leakage
VOSCth)
Vns = Vos, In = 250 I1A
N-Ch
1.0
Vns = Vos, In = -250 I1A
P-Ch
-1.0
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward Transconductanceb
Diode Forward Voltageb
Inss
±100
Vns = OY,Vos = ±20V
loss
N-Ch
1
Vns = -16 Y, Vos = OV
P-Ch
-1
Vns - 10 Y, Vos - 0 Y, TJ - 70·C
N-Ch
5
Vns = 16 Y, Vos = OV
Zero Gate Voltage Drain Current
V
Vns = -lOY, Vos = OY, TJ = 700C
P-Ch
Vns ~ 5Y,Vos = 10V
N-Ch
14
Vnss-5 Y,Vos--l0V
P-Ch
-14
Vns ~ 5Y,Vos -4.5V
N-Ch
3.5
Vns S -5Y, Vos = -4.5 V
P-Ch
-2.5
Vos = lOY, In = 3.5 A
N-Ch
Vos - -lOY, In - 3.5 A
P-Ch
Vos = 6Y,ln = 3A
N-Ch
Vos = - 6 Y, In = 3 A
P-Ch
InCon)
Thtal Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Thrn-On Delay Time
td(on)
Rise Time
Thrn-Off Delay Time
tr
Id(off)
Fall Time
tf
Source-Drain Reverse Recovery Time
tIT
nC
3.7
12
VDD = 15 Y, RL = 150
IDe 1 A, VGEN = 10Y,RG = 60
IF = 1.25 A, dildt = 100 Nt's
30
10
25
25
30
10
50
120
160
ns
Notes
a. Pulse test; pulse width s 300 t'S, duty cycle S 2%.
b. Guaranteed by design, not subject to production testing.
2-4
Advance Information
(04/28/94)
TEMIC
Si6447DQ
Siliconix
P-Channel Enhancement-Mode MOSFET
Product Summary
Vns(V)
rnS(on) (Q)
ID(A)
-20
= -10 V
0.19 @VGS = -4.5 V
±3.0
O.lO@VGS
±2.2
S·
TSSOP-8
• Si6447DQ
• Source Pins 2, 3, 6 and 7
must be tied common.
ThpView
D
P-Channel MOSFET
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
-20
Gate-Source Voltage
VGS
±20
Continuous Drain Current (fJ
~
I
TA ~ 25'C
150'C)
ITA~70'C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation (Surface Mounted on FR4 Board)
Operating Junction and Storage Thmperature Range
V
±3.0
ID
±2.4
IDM
±20
Is
-1.25
ITA~25'C
ITA~70'C
Unit
A
1.5
PD
1.0
W
TJ, T.1g
-55 to 150
'C
Symbol
Limit
Unit
R1hJA
83
'c/w
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board, t
(04fl8!94)
s 10 sec.)
Advance Information
2-5
TEMIC
Si6447DQ
Siliconix
Specifications (TJ = 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
VGS(th)
VDS = Vos, In = -250 IlA
-1.0
IGSS
Vns = OV,VGS = ±20V
±100
VDS= -16V,VGs=OV
-2
VDS = -10V, VGS = OV, TJ = 70·C
-5
1YP
Max
Unit
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
IDSS
On-State Drain Current"
ID(on)
Drain-Source On-State Resistance3
l'DS(on)
Forward 1l'ansconductance"
Diode Forward Voltage"
VDs;,,-5V,VGs=-lOV
-14
VDS;" -5 V, VGS = -4.5 V
-2.5
V
nA
IlA
A
VGS - -10V,ID = 3.0A
0.10
VGS = -4.5 V, ID = 2.0 A
0.19
gr,
VDS = -15V,ID = -3.0A
4.0
Vsn
Is = -1.25 A, Vos = OV
-0.9
-1.2
13
30
Q
S
V
Dynamlcb
Thtal Gate Charge
Og
Gate-Source Charge
Og,
Gate-Drain Charge
Ogd
Thrn-On Delay TIme
td(on)
21
40
t,
12
25
12
30
11
20
50
100
RiseTIme
Thrn-Off Delay TIme
VDS = -10V, VGS = -10V,ID = -3.0A
td(off)
FaIl TIme
tf
Source-Drain Reverse Recovery TIme
trr
2
nC
5
Vnn = -10V, RL = 10Q
ID'" -lA,VGEN= -10V,RG=6Q
IF = -1.25 A, dildt = 100NflS
os
Notes
a. Pulse test; pulse width" 300!'S, duty cycle" 2%.
b.
2-6
Guaranteed by design, not subject to production testing.
Advance Information
(04/28/94)
TEMIC
Si6542DQ
Siliconix
Dual Enhancement-Mode MOSFET (N- and P-Channel)
Product Summary
Vns(V)
N-Channel
20
P-Channel
-20
rDS(on) (Q)
ID (A)
0.100@ VGS
= 10 V
= 4.5 V
0.200 @ V GS = -10 V
0.350 @ V GS = -4.5 V
±2.5
0.200@VGS
±1.7
±1.7
±1.3
S2
DI
TSSOP-8
•
G21
Si6542DQ
G1o-J
E-t
0
0
ThpVlew
S
D2
N-Channel MOSFET
P-Channel MOSFET
~
~
.l
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
N-Channel
P-Channel
Drain-Source Voltage
VDS
20
-20
Gate-Source Voltage
Vos
±20
±20
Continuous Drain Current (TJ
~
I TA ~ 25'C
150'C)
ITA~70'C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation (Surface Mounted on FR4 Board)
±2.5
±1.7
±2.0
±1.3
IDM
±20
±15
IS
1.25
ID
ITA~25'C
ITA-70'C
Operating Junction and Storage Thmperature Range
Unit
V
A
-1.25
1.0
PD
0.64
W
TJ, T'lg
-55 to 150
'C
Symbol
N- or P-Channel
Unit
RtbJA
125
'c/w
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surfac" Mounted on FR4 Board, t s 10 sec.)
(04/28/94)
Advance Information
2-7
TEMIC
Si6542DQ
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
1YP
Max
Unit
Static
Gate Threshold Voltage
Gate-Body Leakage
Vas(tb)
VDS = vas, ID = 250!1A
N-Ch
1.0
VDS = Vas, ID = -250!1A
P-Ch
-1.0
VDS = OY, Vas = ±20V
lass
On-State Drain Current"
Drain-Source On-State Resistance"
Forward 'fransconductance"
Diode Forward Voltage"
IDSS
±100
N-Ch
2
VDS= -16Y,Vas=OV
P-Ch
-2
VDS = 16 Y, Vas = OY, TJ = 55'C
N-Ch
25
VDS = -16 Y, Vas = OY, TJ = 55'C
P-Ch
-25
VDS '" 5Y,Vas = 10V
N-Ch
14
P-Ch
-10
VDS = 16 Y, Vas = OV
Zero Gate Voltage Drain Current
V
ID(on)
VDS
roS(on)
gf.
VSD
O!:
-5 Y, Vas = -lOY
nA
!1A
A
Vas = lOY, ID = 2.5 A
N-Ch
0.100
Vas = -lOY,ID = 1.7 A
P-Ch
0.200
Vas = 4.5 Y, ID = 1.7 A
N-Ch
0.200
Vas = -4.5 Y, ID = 1.3 A
P-Ch
0.350
VDS = 15 Y, ID = 2.5 A
N-Ch
VDS = -15 Y, ID = - 1.7 A
P-Ch
Is -1.25 A, Vas - OV
N-Ch
1.2
Is - -1.25 A, Vas - OV
P-Ch
-1.2
N-Ch
50
P-Ch
25
a
S
V
DynBmicb
Thtal Gate Charge
Gate-Source Charge
Gate-Drain Charge
Og
N-Channel
VDS = lOY, Vas = lOY, ID = 2.5 A
N-Ch
P-Channe!
P-Ch
VDS= -lOY, Vas = -lOY,ID= -1.7 A
N-Ch
Og.
Ogd
P-Ch
N-Ch
Thrn-On Delay TIme
RiseTIme
Thrn-Off Delay TIme
td(on)
N-Channel
VDD = lOY, RL = 100
ID !!! 1A, VaEN= 10Y,Ra = 60
t,
td(off)
ID
Fall TIme
tf
Source-Drain Reverse Recovery TIme
trr
nC
!!!
P-Channel
VDD = -lOY, RL = 100
-1 A, VaEN = -lOY, Ra = 6 a
20
P-Ch
40
N-Ch
20
P-Ch
40
N-Ch
90
P-Ch
90
N-Ch
50
P-Ch
50
IF = 1.25 A, di/dt = 100 NI"
N-Ch
100
IF = -1.25 A, di/dt = 100 NI"
P-Ch
100
ns
Notes
a. Pulse test; pulse width,,; 300 1", duty cycle,,; 2%.
b. Guaranteed by design, not subject to production testing.
2-8
Advance Information
(04{28(94)
TEMIC
Si6953DQ
Siliconix
Dual P-Channel Enhancement-Mode MOSFET
Product Summary
VDS(V)
rDS(on)
ID
(A)
= -10 V
±1.7
0.350 @ VGS = -4.5 V
±1.3
0.200 @ V GS
-20
(Q)
SI
S2
TSSOP-8
GIl
G21
Si6953DQ
ThpView
Dl
~
D2
P·Channel MOSFET
0
0
P·Channel MOSFET
~
:s~
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Symbol
Limit
Drain·Source Voltage
Vos
-20
Gate·Source Voltage
VGS
±20
Parameter
V
±1.7
ITA=25'C
Continuous Drain Current (TI = 150'C)
Unit
10
±1.3
ITA=70'C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation (Surface Mounted on FR4 Board)
ITA=25'C
ITA=70'C
Operating Junction and Storage Thmperature Range
10M
±15
Is
-1.25
A
1.0
Po
0.64
W
TI,Tstg
-55 to 150
'C
Symbol
Limit
Unit
RthIA
125
'CIW
Thermal Resistance Ratings
Parameter
Maximum Junction·to·Ambient (Surface Mounted on FR4 Board, t
(04/28/94)
s 10 sec.)
Advance Information
2-9
TEMIC
Si6953DQ
Specifications (TJ
Parameter
Siliconix
= 25°C Unless Otherwise Noted)
Symbol
Test Condition
Min
-1.0
'!yp
Max
Unit
±lOO
nA
Static
Gate Threshold Voltage
VaS(th)
Vns = Vas, In = -250flA
Gate-Body Leakage
loss
Vns = OY,Vas = ±20V
Zero Gate Voltage Drain Current
Inss
On-State Drain Currenta
In(on)
Drain-Source On-State Resistancea
rnS(on)
Forward 1l-ansconductancea
Diode Forward Voltagea
V
Vns= -16Y,Vas=OV
-2
Vns = -16 Y, Vas = OY, TJ = 55°C
-25
Vns;" -5 Y, Vas = -lOY
-10
Vns ;" -5 Y, Vas = -4.5 V
-1.5
A
Vas - -lOY, In - 1.7 A
0.200
Vas = -4.5 Y, In = 1.3 A
0.350
gr,
Vns = -15 Y, In = -1.7 A
Vsn
IS = -1.7 A, Vas = OV
flA
Q
S
-1.2
V
Dynamicb
Thtal Gate Charge
Og
Gate-Source Charge
Ogs
Gate-Drain Charge
Ogd
Thrn-On Delay Time
td(on)
Rise Time
Thrn-Off Delay Time
25
Vns = -lOY, Vas = -lOY, In = -1.7 A
tr
td(o!!)
Fall Time
te
Source-Drain Reverse Recovery Time
trr
nC
40
Vnn = -lOY, RL = 10Q
In'" -1 A, VaEN= -lOY,Ra = 6Q
40
90
ns
50
IF = -1.7 A, dildt =
100N~s
100
Notes
a. Pulse test; pulse width", 300 ~s, duty cycle", 2%.
b. Guaranteed by design, not subject to production testing.
2-10
Advance Information
(04128/94)
TEMIC
Si6956DQ
Siliconix
Dual N-Channel Enhancement-Mode MOSFET
Product Summary
VDS(V)
20
rDS(on) (Q)
ID (A)
O.lO@VGS = lOV
±2.5
0.20@VGS = 4.5 V
± 1.7
TSSOP·8
Si6956DQ
ThpView
N-Channel MOSFET
N-Channel MOSFET
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
Vos
20
Gate-Source Voltage
VGS
±20
Unit
V
ITA=25'C
Continuous Drain Current (TJ = 150'C)
±2.5
10
±2.0
ITA = 70'C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
10M
±20
Is
1.25
1.0
ITA=25'C
Maximum Power Dissipation (Surface Mounted on FR4 Board)
Po
ITA = 70'C
Operating Junction and Storage Temperature Range
A
0.64
W
TJ. Tstg
-55 to 150
'C
Symbol
Limit
unit
RthJA
125
'c/w
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient (Surface Mounted on FR4 Board. t s 10 sec.)
(04128{94)
Advance Information
2·11
TEMIC
Si6956DQ
Specifications (TJ
Parameter
Siliconix
= 25°C Unless Otherwise Noted)
Symbol
Test Condition
Min
1.0
'iYP
Max
Unit
±100
nA
Static
VGS(lh)
Vns = V GS, In = 250 ItA
Gate-Body Leakage
IGSS
Vns = OV,VGS= ±20V
Zero Gate Voltage Drain Current
Inss
On-State Drain Current"
In(on)
Gate Threshold Voltage
Drain-Source On-State Resistance"
Forward 1fansconductancea
Diode Forward Voltage"
rns(on)
V
Vns = 16 V, VGS = OV
2
Vns = 16 V, VGS = Ov, TJ = 55'C
25
Vns;" 5V,VGS = 10V
14
A
VGS = 10 V, In = 2.5 A
0.10
VGS = 4.5 V, In = 1.7 A
020
gls
Vns = 15 V, In = 2.5 A
Vsn
IS = 1.25 A, VGS = OV
ItA
g
S
1.2
V
Dynamicb
Thtal Gate Charge
Og
Gate-Source Charge
Ogs
Gate-Drain Charge
Ogd
Thrn-On Delay TIme
td(on)
RiseTIme
Thrn-Off Delay TIme
tr
td(off)
Fall TIme
tl
Source-Drain Reverse Recovery TIme
trr
50
nC
Vns = 10 V, VGS = 10V, In = 2.5 A
20
Vnn = 10V, RL = 109
In '" 1 A, VGEN = 10 V, RG = 6 g
20
90
ns
50
IF = 1.25 A, di/dt = 100 Nl's
100
Notes
a. Pulse test; pulse width s 300l'S, duty cycle s 2%.
b. Guaranteed by design, not subject to production testing.
2-12
Advance Information
(04/28/94)
Power Conversion, PCMCIA Interface & Battery Management •
About Power Management
Siliconix IC products for power control, conversion, and switching combine the functions of two or more
discretes in the same package and add useful protection features to ensure the reliability of designs. A
popular series of switchmode control ICs designed especially for the communications market simplifies
the design ofline cards, network terminators, battery adapters, and cable television repeaters. A family of
regulator and controller ICs designed for use with LfITLE FOOT discretes offers the optimal level of
integration for dc-to-dc conversion in battery-operated equipment, including laptop and notebook
computers. Highly-integrated products for the PCMCIA slot interface and for multiple battery-pack
designs reduce parts count significantly, and simplify both design and user operation.
TEMIC
Si9100
Siliconix
3-W High-Voltage Switchmode Regulator
Features
II 10- to 70-V Input Range
• Current-Mode Control
• On-Chip IS0-V, S-£1 MOSFET Switch
• Reference Selection
Si9100 - ± 1%
• High Efficiency Operation (> 80%)
• Internal Start-Up Circuit
• Internal Oscillator (1 MHz)
• SHUTDOWN and RESET
Description
The Si9100 high-voltage switchmode regulators are
monolithic BiCIDMOS integrated circuits which contain
most of the components necessary to implement
high-efficiency dc-to-dc converters up to 3 watts. They
can either be operated from a low-voltage dc supply, or
directly from a 10- to 70-V unregulated dc power source.
The Si9100may be used with an appropriate transformer
to implement most single-ended isolated power
converter topologies (i.e., f1yback and forward), or by
using a level shift circuit can generate a +S-V or a -5-V
non-isolated output from a -48-V source.
The Si9100 is available in 14-pin plastic DIP and 20-pin
PLCC packages. It is specified over the industrial,
D suffix (-40 to 85°C) temperature ranges.
Functional Block Diagram
FB
CaMP
14 (20)
DISCHARGE
OSC
IN
OSC
OUT
~
13 (18)
Error
Amplifier
10 (14)
VREF
Q
S
DRAIN
-VIN
1.2 V
2)'-----1
BIAS 01-(0-
Vee
(BODY)
Th
Internat
4 (7)
Circuits '-------------I--+-------:-:---~'-'-_'_O SOURCE
6(9)
SHUTDOWN
Undervottage Comparator
1----6-=-0=..0\0 RESET
Note: Figures in parenthesis represent pin numbers for 20-pin package.
P-34984-Rev. D (04/18/94)
3-1
TEMIC
Si9100
Siliconix
Absolute Maximum Ratings
Voltages Referenced to - VIN (Vee < + VIN + 0.3 V)
vee ................................................ 15V
+VIN ............................................... 70V
Vns ............................................... 150V
In (Peak) (Note: 300 II" pulse, 2% duty cycle) .............. 2.5 A
In (rms) .................... .................... 350 rnA
Logic Inputs (RESET,
SHUTDOWN, OSC IN) ................. -0.3 V to Vee + 0.3 V
Linear Inputs (FEEDBACK, SOURCE) . . . . . . . . . .. -0.3 V to 7 V
HV Pre-Regulator Input Current (continuous) ............. 3 rnA
Storage Temperature ........................... -65 to 125'C
Operating Thmperature ......................... -40 to 85'C
Junction Thmperature (TI) ............................. 150'C
Power Dissipation (Package)'
14-Pin Plastic DIP (J SUfflX)b ......................... 750 mW
20-Pin PLCC (N SufflX)c ............................ 1400 mW
Thermal Impedance (EllA)
14-Pin Plastic DIP ................................. 167'C/W
20-Pin PLCC ...................................... 90'C/W
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate6mWrCabove25'C
c. Derate 11.2 mWrC above 25'C
Recommended Operating Range
Voltages Referenced to - VIN
Vee ....................................... 9.5 V to 13.5 V
+VIN ........................................ 10Vt070V
lose ................................. '..... 40 kHz to 1 MHz
Rose ...................................... 24 kQ to 1 MQ
Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 7 V
Digitallnputs ...................................... 0 to Vee
Specifications 8
Thst Conditions
UnlessOtherwise Specified
Parameter
Limits
D SuffIX -40 to 85'C
Symbol
DISCHARGE = -vIN' = OV
Vee = lOY, +VIN = 48 V
RBJAS = 390 kQ, Rose = 330 kQ
Tempb
Mine
1YPd
Max"
VR
OSC IN = - VIN (OSC Disabled)
RL=10MQ
Room
3.92
4.0
4.08
V
kQ
Unit
Refeten~e
Output Voltage
Output Impedance"
ZoUT
Short Circuit Current
ISREF
Thmperature Stability"
TREF
VREF= -VIN
Room
15
30
45
Room
70
100
130
(.lA
0.5
1.0
mVrC
Full
Oscillator
Maximum Frequency"
Initial Accuracy
Voltage Stability
Thmperature Coefficiente
fMAX
fose
""flf
Rose =0
Room
1
3
Rose = 330 kn See Note f
Room
80
100
120
Rose = 150 kn See Note f
Room
160
200
240
""flf = f(13.5 V) - f, (9.5 V)/f(9.5 V)
Room
10
15
%
Full
200
500
ppml'C
4.00
4.04
V
25
500
nA
Tose
MHz
kHz
Error Amplifier
Feedback Input Voltage
VFB
FBTIedtoCOMP
OSC In = - VIN (OSC Disabled)
Room
Input BIAS Current
IFB
OSCIN = -VIN, VFB = 4 V
Room
3-2
3.96
P-34984--Rev. D (04/18/94)
TEMIC
Si9100
Siliconix
Specificationsa
Test Conditions
UnlessOtherwise Specified
Parameter
Symbol
DISCHARGE = - VIN = 0 V
Vcc = lOY, +VIN = 48 V
RBIAS = 390 ill. Rosc = 330 ill
D Suffix
D SuffIX -40 to 85"C
Tempb
Minc
'JYpd
Maxc
Unit
±15
±40
mV
Error Amplifier (Cont'd)
Input OFFSET Voltage
Vos
Room
Open Loop Voltage Gaine
AVOL
Room
Unity Gain BandwidthC
Dynamic Output Impedancee
BW
OSC IN = - VIN. (OSC Disabled)
60
80
dB
Room
1
MHz
g
Room
1000
2000
SOURCE (VFB = 3.4 V)
Room
-2.0
-1.4
SINK (VFB = 4.5 V)
Room
0.12
0.15
PSRR
OSC IN = - VIN. (OSC Disabled)
Room
50
70
Threshold Voltage
VSOURCE
RL = 100 g from DRAIN to VCC
VFB=OV
Room
1.0
1.2
1.4
V
Delay to Outpute
td
RL = 100 g from DRAIN to VCC
VSOURCE = 1.5 Y, See Figure 1
Room
100
200
ns
Input Voltage
+VIN
lIN = 100 J!A
Room
70
V
Input Leakage Current
+lIN
VCC
Room
10
~A
Output Current
Power Supply Rejection
ZOUT
lOUT
rnA
dB
Current Limit
Pre-RegulatorIStart-Up
2:
lOV
Pre-Regulator Start-Up Current
ISTART
Pulse Width,; 300 ~s
VCC=VUVLO
Room
8
15
Vcc Pre-Regulator Thrn-Off
Threshold Voltage
VREG
IpRE-REGULATOR = 10 J!A
Room
7.8
9.4
9.7
Undervoltage Lockout
VUVLO
RL = 100 g from DRAIN to Vcc
See Detailed Description
Room
7.0
8.8
9.2
VREG-VUVLO
VDELTA
Room
0.3
0.6
Icc
Room
0.45
0.6
1.0
rnA
IBIAS
Room
10
15
20
J!A
50
100
rnA
V
Supply
Supply Current
Bias Current
Logic
SHUTDOWN Delay<
tSD
SHUTDOWN Pulse Wid the
tsw
RESET Pulse Widthe
tRW
Latching Pulse Wldthe
SHUTDOWN and RESET Low
VSOURCE
VIN. See Figure 2
Room
Room
50
Room
50
tLW
Room
25
Input Low Voltage
VIL
Room
Input High Voltage
VIH
Room
Input Current
Input Voltage High
1m
VIN= 10V
Room
Input Current
Input Voltage Low
IlL
VIN=OV
Room
P-34984-Rev. D (04/18/94)
See Figure 3
ns
2.0
V
8.0
1
5
~A
-35
-25
3-3
TEMIC
Si9100
Siliconix
Specificationsa
Test Conditions
UnlessOtherwise Specified
Parameter
DISCHARGE = - VIN = 0 V
Vee = lOY, +VIN = 48V
RBIAS = 390 W, Rose = 330 W
Symbol
D SuII'lX
D SuffIX -40 to 85°C
Tempb
Mine
'JYpd
Full
150
180
Max"
Unit
MOSFET Switch
Breakdown Voltage
V(BR)DSS
Drain-Source On ResistanceS
VsouReE - VSHUTDOWN - OV
IDRAJN = 100 flA
VSOURCE
390kf.!
1
14
2
13
---l
~
4
Si9100DJ
10
L-----2
9
8
.
6
1N5819
==
1 (.IF
r
=f
1s;!
Y,W
"L
O.cJl.z(.lF
240kf.!
fll
5
7
0.1 (.IF
0.1 (.IF
12kQ
~~
1N4148
150kf.!
~
- VIN (-48 VDC)
• For additional information on using the Si9100 in telecommunications and ISDN power supplies. see AN713 and AN702.
3-8
P-34984-Rev. D (04/18/94)
TEMIC
Si9102
Siliconix
3-W High-Voltage Switchmode Regulator
Features
• 10- to 120-V Input Range
• Current-Mode Control
• On-chip 200-V, 7-0 MOSFET Switch
o SHUTDOWN and RESET
• High Efficiency Operation (> 80%)
• Internal Start-Up Circuit
• Internal Oscillator (1 MHz)
Description
The Si9102 high-voltage switchmode regulator is a
monolithic BiC/DMOS integrated circuit which contains
most of the components necessary to implement a
high-efficiency dc-to-dc converter up to 3 watts. It can
either be operated from a low-voltage dc supply, or
directly from a 10- to 120-V unregulated dc power
source.
This device may be used with an appropriate
transformer to implement most single-ended isolated
power converter topologies (Le., flyback and forward).
The Si9102 is available in 14-pin plastic DIP and 20-pin
PLCC packages, and is specified over the D suffix ( -40
to 85 D C) temperature range.
Functional Block Diagram
CaMP
FB
14 (20)
13 (18)
Error
Amplifier
VREF
DISCHARGE
10(14)
OSC OSC
IN OUT
~
Current-Mode
Q
S
DRAIN
-VIN
(BODY)
s..
~
__________________+-~~______________+-4~(~~~
SOURCE
de~
1..--_ _
I>-~I-+":":"'>"::';;IO
SHU'IDOW
1-----'-="""'''''0 RESET
Note: Figures in parenthesis represent pin numbers for 20-pin package.
P-34984-Rev. D (04/18/94)
3-9
TEMIC
Si9102
Siliconix
Absolute Maximum Ratings
Voltages Referenced to -VIN (Vee < +VIN + 0.3 V)
Vee ................................................ 15V
+VIN .............................................. 120V
Vns ............................................... 200V
In (Peak) (Note: 300 J1s pulse, 2% duty cycle) ............... 2 A
In (rms) ......................................... 250rnA
Logic Inputs (RESET,
SHUTDOWN, OSC IN) ................. -0.3 V to Vee + 0.3 V
Linear Inputs
(FEEDBACK, SOURCE) ...................... -0.3 V to 7 V
HV Pre-Regulator Input Current(continuous) ............. 3 rnA
Storage Thmperature . . . . . . . . . . . . . . . . . . . . . . . . . .. -65 to 125°C
Operating Thmperature ......................... -40 to 85'C
Junction Thmperature (TI) ............................. 150'C
Power Dissipation (Package)a
14-Pin Plastic DIP (J SufflX)b ......................... 750 mW
20-Pin PLCC (N SuffIX)· ............................ 1400 mW
Thermal Impedance (EllA)
14-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 167'C{W
20-Pin PLCC ...................................... 90'C{W
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate6mWrCabove25'C
c. Deratell.2mWrCabove25'C
Recommended Operating Range
Voltages Referenced to - VIN
Vee ....................................... 9.5Vto13.5V
Rose ...................................... 25WtolMn
Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 7 V
+VIN .: ..................................... 10Vto120V
fose ...................................... 40 kHz to 1 MHz
Digital Inputs ...................................... 0 to Vee
Specifications a
Test Conditions
Unless Otherwise Specified
Parameter
limits
D Suffix -40 to 85'C
Symbol
DISCHARGE = -VIN = OV
Vee = 10 V, +VIN = 48V
RBIAS = 390 kQ, Rose = 330 kQ
Thmpb
Mind
'JYpc
Maxd
Unit
VR
OSC IN = - VIN (OSC Disabled)
RL=10Mg
Room
Full
3.92
3.86
4.0
4.08
4.14
V
W
Reference
Output Voltage
Output Impedance"
ZoUT
Short Circuit Current
ISREF
Thmperature Stability"
TREP
VREF= -VIN
Room
15
30
45
Room
70
100
130
J1A
0.5
1.0
mV/'C
Full
Oscillator
Maximum Frequency"
Initial Accuracy
Voltage Stability
Thmperature Coefficient"
fMAx
fose
MIf
MHz
Rose =0
Room
1
3
Rose = 330 Icgg
Room
80
100
120
Rose = 150 Icgg
Room
160
200
240
Af/f = f(13.5 V) - f(9.5 V)1f(9.5 V)
Room
10
15
%
Full
200
500
ppm/'C
3.96
4.00
4.04
V
25
500
nA
Tose
kHz
Error Amplifier
Feedback Input Voltage
Input BIAS Current
Open Loop Voltage Gaine
Unity Gain Bandwidth"
Dynamic Output Impedancee
3-10
VPB
FB TIed to COMP
OSC IN = - VIN (OSC Disabled)
Room
IPB
Room
AVOL
Room
60
80
dB
Room
0.7
1
MHz
BW
ZoUT
OSCIN = - VIN, VPB = 4 V,
OSC IN = - VIN (OSC Disabled)
Room
1000
2000
g
P-34984-Rev. D (04/18/94)
TEMIC
Si9102
Siliconix
Specificationsa
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
DISCHARGE ~ - VIN ~ 0 V
Vee ~ 10 V, +VIN ~ 48 V
RBIAS ~ 390 k.Q. Rose ~ 330 k.Q
Limits
D SuffIX -40 to 85'C
lYpc
Max d
Unit
Room
-2.0
-1.4
rnA
Room
±15
±40
Tempb
Mind
Error Amplifier (Cont'd)
Output Current
Source (VFB
lOUT
Input OFFSET Voltage
Vas
Output Current
lOUT
Power Supply Rejection
PSRR
OSC IN
~
~
3.4 V)
- VIN (OSC Disabled)
Sink (VFB
~
4.5 V)
9.5 V S Vee S 13.5 V
mV
Room
0.12
0.15
rnA
Room
50
70
dB
Room
1.0
1.2
1.4
V
100
200
ns
Current Limit
RL
~
100 Q from DRAIN to Vee
Threshold Voltage
VSOURCE
Delay to Output"
td
RL ~ 100 Q from DRAIN to Vee
V SOURCE ~ 1.5 V, See Figure 1
Room
Input Voltage
+VIN
lIN ~ 100 "A
Room
120
V
Input Leakage Current
+lIN
Vee;;' 10V
Room
10
!'A
VFB~OV
Pre-ReguJatorIStart-Up
Pre-Regulator Start-Up Current
ISTART
Vee Pre-Regulator 1I1m·Off
Threshold Voltage
VREG
Pulse Width S 300!'S. Vee
~
7V
IpRE.REGULATOR ~ 10 !'A
RL
~
100 Q from DRAIN to Vee
See Detailed Description
Room
8
15
rnA
Room
7.8
9.4
9.7
Room
7.0
8.8
9.2
V
Undervoltage Lockout
VUVLO
VREG. -VUVLO
VDELTA
Room
0.3
0.6
Icc
Room
0.45
0.6
1.0
rnA
IBIAS
Room
10
15
20
!'A
50
100
Supply
Supply Current
Bias Current
Logic
SHUTDOWN Delay"
tSD
SHUTDOWN Pulse Width"
tsw
RESET Pulse Width"
tRW
Latching Pulse Wid the
SHUTDOWN and RESET Low
VSOURCE-
VIN. See Figure 2
Room
Room
50
Room
50
tLW
Room
25
Input Low Voltage
VIL
Room
Input High Voltage
VIH
Room
Input Current Input Voltage High
IIH
Input Current Input Voltage Low
IlL
See Figure 3
ns
2.0
V
P-34984-Rev. D (04/18/94)
VIN
~
10V
VIN~OV
8.0
Room
Room
1
-35
-25
5
!'A
3-11
TEMIC
Si9102
Siliconix
Specifications a
Limits
D Suffix -40 to 85'C
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
DISCHARGE = - VIN = 0 V
Vee = lOY, +VIN = 48 V
RBIAS = 390 W, Rose = 330 W
Tempb
Mind
'JYpc
200
220
Maxd
Unit
7
g
10
JlA
MOSFET Switch
Breakdown Voltage
VBR(DSS)
IDRAIN = 100 JlA
Full
fDS(on)
IDRAIN = 100 rnA
Room
Drain Off Leakage Current
IDSS
VDRAIN = 100 V
Drain Capacitance
CDS
Drain-Source On Resistance!
Room
5
Room
35
V
pF
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25'C, Full = as determined by Ibe operating temperature suffIX.
c. 'lYpical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. 'Thmperature coefficient of fDS(on) is 0.75% per 'c, typical.
g. CSTRAY Pin 8 = s 5 pF
Timing Waveforms
1.5 V ,.-----SOURCE
50%../
tr S 10 ns
0----/1
vee~~td
DRAIN
o
10%
Figure 1.
Figure 2.
Vee
SHUTDOWN
o -
Vee
RESET
o
Figure 3.
3-12
P-34984-Rev. D (04/18/94)
TEMIC
Si9102
Siliconix
1Ypical Characteristics
+VIN vs. + lIN at Start.Up
140
vie = ~VIJ
120
80
>
+
60
"-
I
100
~
Output Switching Frequency
vs. Oscillator Resistance
1M
V
1':
/
40
~
¥
~100k
J
..9
V
20
-
a
10
,/
~
10 k
15
20
100 k
10k
1M
rose - Oscillator Resistance (Q)
+lIN (rnA)
Pin Configurations
PDIP-14
Pin
Order Number
Function
14-PinDIP
Plastic DIP: Si9102DJ
BIAS
1
2
+VIN
2
3
5
Top View
PLCC-20
18
Order Number
Plastic PLCC: Si9102DN
20-Pin PLCC*
DRAIN
3
SOURCE
4
7
-VIN
5
8
Vee
6
9
OSCOUT
7
10
OSCIN
8
11
DISCHARGE
9
12
VREF
10
14
SHUTDOWN
11
16
RESET
12
17
COMP
13
18
FB
14
20
'Pins 1, 4, 6, 13, 15, and 19 = NIC
Top View
P-34984--Rev. D (04/18/94)
3-13
TEMIC
Si9102
Siliconix
Detailed Description
Pre-RegulatorIStart-Up Section
Due to the low quiescent current requirement of the
Si9102 control circuitry, bias power can be supplied from
the unregulated input power source, from an external
regulated low-voltage supply, or from an auxiliary
"bootstrap" winding on the output inductor or
transformer.
When power is first applied during start-up, +VINwill
draw a constant current. The magnitude of this current
is determined by a high-voltage depletion MOSFET
device which is connected between + V IN and Vee. This
start-up circuitry provides initial power to the IC by
charging an external bypass capacitance connected to
the Vee pin. The constant current is disabled when Vee
exceeds 9.4 V. If Vee is not forced to exceed the 9.4-V
threshold, then Vee will be regulated to a nominal value
of 9.4 V by the pre-regulator circuit.
As the supply voltage rises toward the normal operating
conditions, an internal undervoltage (UV) lockout
circuit keeps the output MOSFET disabled until Vee
exceeds the undervoltage lockout threshold (typically
8.8-V). This guarantees that the control logic will be
functioning properly and that sufficient gate drive
voltage is available before the MOSFET turns on. The
design of the IC is such that the undervoltage lockout
threshold will not exceed the pre-regulator turn-off
voltage. Power dissipation can be - minimized by
providing an external power source to Vee such that the
constant current source is always disabled.
Note: During start-up or when Vee drops below 9.4-V
the start-up circuit is capable of sourcing up to 20 mAo
This may lead to a high level of power dissipation in the
IC (for a 48-V input, approximately 1 W). Excessive
start-up time caused by external loading of the Vee
supply can result in device damage. Figure 4 gives the
typical pre-regulator current at start-up as a function of
input voltage.
BIAS
To properly set the bias for the Si9102, a 390-kQ resistor
should be tied from BIAS to - VIN. This determines the
magnitude of bias current in all of the analog sections
and the pull-up current for the SHUTDOWN and
RESET pins. The current flowing in the bias resistor is
nominally 15 1lA.
3-14
Reference Section
The reference section of the Si9102 consists of a
temperature compensated buried zener and trimmable
divider network. The output of the reference section is
connected internally to the non-inverting input of the
error amplifier. Nominal reference output voltage is 4 V.
The trimming procedure that is used on the Si9102
brings the output of the error amplifier (which is
configured for unity gain during trimming) to within
± 1 % of 4 V. This automatically compensates for the
input offset voltage in the error amplifier.
The output impedance of the reference section has been
purposely made high so that a low impedance external
voltage source can be used to override the internal
voltage source, if desired, without otherwise altering the
performance of the device.
Error Amplifier
Closed-loop regulation is provided by the error
amplifier, which is intended for use with
"around-the-amplifier" compensation. AMOS
differential input stage provides for low input current.
The noninverting input to the error amplifier (VREF) is
internally c.onnected to the output of the reference
supply and should be bypassed with a small capacitor to
ground.
Oscillator Section
The oscillator consists of a ring of CMOS inverters,
capacitors, and a capacitor discharge switch. Frequency
is set by an external resistor between the OSC in and
OSC out pins. (See Figure 5 for details of resistor value
vs. frequency.) The DISCHARGE pin should be tied to
-VIN for normal internal oscillator operation. A
frequency divider in the logic section limits switch duty
cycle to S 50% by locking the switching frequency to
one half of the oscillator frequency.
Remote synchronization can be accomplished by
capacitive coupling of a synchronization pulse into the
OSC IN terminal. For a 5-V pulse amplitude and O.5-IlS
pulse width, typical values would be 100 pF in series with
3 kQ to OSC IN.
P-34984-Rev. D (04/18194)
TEMIC
Si9102
Siliconix
Detailed Description (Cont'd)
SHUTDOWN and RESET
SHUTDOWN and RESET are intended for overriding
the output MOSFET switch via external control logic.
The two inputs are fed through a latch preceding the
output switch. Depending on the logic state of RESET.
SHUTDOWN can be either a latched or unlatched
input. The output is off whenever SHUTDOWN is low.
By simultaneously having SHUTDOWN and RESET
low, the latch is set and SHUTDOWN has no effect until
RESET goes high. The truth table for these inputs is
given in Table 1.
Table 1.
lhIth Table for the SHUTDOWN and RESET Pins
SHUTDOWN
Output
RESEr
H
H
Normal Operation
H
t.
Normal Operation (No Change)
L
H
Off (Not Latched)
L
L
Off (Latched)
r
L
Off (Latched, No Change)
Output Switch
Both pins have internal current source pull-ups and
should be left disconnected when not in use. An added
feature of the current sources is the ability to connect a
capacitor and an open-collector driver to the
SHUTDOWN or RESET pins to provide variable
shutdown time.
The output switch is a 7-Q , 200-V lateral DMOS device.
Like discrete MOSFETs, the switch contains an intrinsic
body-drain diode. However, the body contact in the
Si9102 is connected internally to - VIN and is
independent of the SOURCE.
Applications
Flyback Converter for Double Battery Telecommunications Power Supplies
...,
IN5819
100 Jill
+ VIN
GND
2l·
J3
== 0.1 ~F
300~H
20~F
+5V
O"L
J
220J'F
GND
4
5
7l
~
14
1
390kn
.1.
13
--.1
B
4
Si9102DJ
!
II
"
I
0.022~F
8
.
1 IN5819
6~
~ 47J'F
-5V
......
..!.!
10
5
~
9
;L
8
2Q
V,W
v
240kn
== 0.1 J'F
18kn
== 0.1 ~F
== 0.1 ~F
150kn
12kn
~ IN4148
-VIN( -96VDC)
P·34984-Rev. D (04/18/94)
3-15
TEMIC
Si9104
Siliconix
High-Voltage Switchmode Regulator
Features
• 10- to 120-V Input Range
• Current-Mode Control
• On-Chip 200-V, S-Q MOSFET Switch
• SHUTDOWN and RESET
• High Efficiency Operation (>80%)
• Internal Start-Up Circuit
• Internal Oscillator (1 MHz)
Description
The Si9104 high-voltage switchmode regulator is a
monolithicBiC/DMOS integrated circuit which contains
most of the components necessary to implement a
high-efficiency dc-to-dc converter up to 3 watts. It can
either be operated from a low-voltage dc supply, or
directly from a 10- to 120-V unregulated dc power
source.
This device may be used with an appropriate
transformer to implement most single-ended isolated
power converter topologies (i.e., flyback and forward).
The Si9104 is available in a 16-pin wide-body SOIC,
14-pin plastic DIP, and 20-pin PLCC, and are specified
over the D suffix (-40 to 85°C) temperature range.
Functional Block Diagram
FB
COMP
DISCHARGE
I .~ I
VREF
0-----...,...--1
OSC
IN
OSC
OUT
l~ I 1
r------t,
IY
"mp"uer
Current-Mode
Q
S
DRAIN
"'---0
1.2 V
BIAS
0----1
Th
Internal
Circuits
'-------------t-+------::-:---~-_o
-VIN
(BODY)
SOURCE
Vec
+VIN
3-16
Undervoltage Comparator
Preliminary
P--+-I---o
SHUTDOWN
~--~--o
RESET
P-34984-Rev. B (04/18/94)
TEMIC
Si9104
Siliconix
Absolute Maximum Ratings
Voltages Referenced to - VIN (Vee < + VIN + 0.3 V)
Vee ................................................ 15V
+VIN .............................................. 120V
Vns ............................................... 200V
In (Peak) (300 J1S pulse, 2% duty cycle) ..................... 2 A
In (rms) ......................................... 250 rnA
Logic Inputs (RESET,
SHUTDOWN, OSC IN) ................. -0.3 V to Vee + 0.3 V
Linear Inputs (FEEDBACK, SOURCE) . . . . . . . . . .. -0.3 V to 7 V
HV Pre-Regulator Input Current (continuous) ............. 3 rnA
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .. -65 to 125'C
Operating Temperature ......................... -40 to 85'C
Junction Temperature (TJ) ............................. 150'C
Power Dissipation (Package)'
14-Pin Plastic DIpb ................................. 750 mW
16-Pin Plastic Wide-Body SOice ...................... 900 mW
20-Pin PLCCd .................................... 1400 mW
Thcrmallmpedancc (SJA)
14-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 167'C/W
16-Pin Plastic Wide-Body SOIC ...................... 140'C/W
20-Pin PLCC ...................................... 90'C/W
Notes
a. Device mounted with all leads soldered or welded to PC boald.
b. Derate 6 mWI"C above 25'C.
c. Derate 7.2 mWI"C above 25'C.
d. Derate 11.2 mWI"C above 25'C.
Recommended Operating Range
Voltages Referenced to - VIN
Vee········································lOVto13.5V
+VIN ....................................... 10Vt0120V
Case ...................................... 40 kHz to 1 MHz
Rose ..................................... 25Wt01MQ
Linear Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 7 V
DigitRlInputs ...................................... 0 to Vcc
Specificationsa
Test Conditions Unless
Otherwise Specified
Parameter
Limits
DSufflx -40to85'C
Symbol
DISCHARGE = -VIN = ov, Vee = lOV
+ VIN = 48 V, RBIAS = 390 W
Rose=330W
Tempb
Mind
1Ypc
VR
OSC IN = - VIN (OSC Disabled)
RL= 10MQ
Room
Full
3.92
3.85
4.0
4.08
4.15
V
Room
15
30
45
W
Room
70
I
Maxd
Unit
Reference
Output Voltage
Output ImpedaneeC
ZoUT
Short Circuit Current
ISREP
100
130
JlA
Full
0.25
1.0
mVI"C
t = 1000 hrs., TA = 125'C
Room
5
25
mV
VREP= -VIN
Thmperature Stability"
Long Thrm Stability"
TREF
OsciUatllr
Maximum Frequency"
fMAX
Initial Accuracy
fose
Voltage Stability
Aflf
Thmperature Coefficient"
P-34984-Rev. B (04/18/94)
Rose = 0
Room
1
3
Rose = 330 kQ f
Room
80
100
120
Rose = 150 kkQ f
Room
160
200
240
Aflf = f(13.5 V) - f(10 V) / f(lO V)
Room
4
Full
Tose
Preliminary
MHz
kHz
10
15
%
200
500
ppm/'C
3-17
TEMIC
Si9104
Siliconix
Specifications a
Test Conditions Unless
Otherwise Specified
Symbol
DISCHARGE = -VIN = Ov, Vee = lOV
+ VIN = 48 V, RBIAS = 390 W
Rose=330W
VFB
FB TIed to COMP
OSC IN = - VIN (OSC Disabled)
Input BIAS Current
IFB
OSCIN = - VIN, VFB = 4 V
Input OFFSET Voltage
Vos
Parameter
Limits
D SuffIX -40 to 85'C
Tempb
Mind
'JYpc
Maxd
Unit
Room
3.96
4.00
4.04
V
Error AlnpHfler
Feedback Input Voltage
Open Loop Voltage Gain"
AVOL
Unity Gain Bandwidth"
BW
Dynamic Output Impedance"
OSC IN = - VIN (OSC Disabled)
Room
25
500
nA
Room
±15
±40
mV
Room
60
80
dB
Room
0.7
1
MHz
Room
1000
2000
Source (VFB = 3.4 V)
Room
-2.0
-1.4
Sink (VFB = 4.5 V)
Room
0.12
0.15
70
ZoUT
Output Current
lOUT
Power Supply Rejection
PSRR
10V S Vee S 13.5V
Room
50
VSOURCE
RL = 100g from DRAIN to Vee, VFB = OV
Room
1.0
Id
RL = 100 g from DRAIN to Vee
VSOURCE = 1.5 V, See Figure 1
Room
+VIN
lIN = 100 ).IA
Room
g
rnA
dB
Cunent Limit
Threshold Voltage
Delay to Output"
1.2
1.4
V
100
200
ns
Pre-RegulatorfStart-Up
Input Voltage
Input Leakage Current
120
V
Vee 2: 10V
Room
ISTART
Pulse Width S 300 Ils, Vee - 7 V
Room
8
15
Vee Pre-Regulator Thm-Off
Threshold Voltage
VREG
IpRE-REGULATOR = 10 ).IA
Room
7.8
9.4
9.8
Undervoltage Lockout
VUVLQ
RL = 100 g from DRAIN to Vee
See Detailed Description
Room
7.0
8.8
9.3
V
VREG-VUVLQ
VDELTA
Room
0.3
0.6
Icc
Room
0.45
0.6
1.0
rnA
IBIAS
Room
10
15
20
).IA
50
100
Supply
10
).IA
+lIN
Pre-Regulator Start-Up Current
rnA
,
Supply Current
Bias Current
I.AJglc
SHUTDOWN Delay"
tsn
SHUTDOWN Pulse Width"
tsw
RESET Pulse Width·
tRW
Latching Pulse Width"
SHUTDOWN' and RESET Low
VSOURCE - -VIN, See Figure 2
Room
Room
50
Room
50
tLW
Room
25
Input Low Voltage
VIL
Room
Input High Voltage
VIH
Room
3-18
See Figure 3
Preliminary
ns
2.0
8.0
V
P-34984-Rev. B (04/18/94)
TEMIC
Si9104
Siliconix
Speci6cations a
Test Conditions Unless
Otherwise Specified
Limits
D Suffrx -40 to 85'C
Symbol
DISCHARGE = -VIN = ov, Vee = lOV
+VIN = 48 V, RBIAS = 390 Jill,
Rose = 330kQ
Tempb
Input Current
Input Voltage High
1m
VIN = Vee
Room
Input Current
Input Voltage Low
IlL
VIN=OV
Room
-35
-25
200
220
Parameter
Mind
'!Ypc
Max d
1
5
Unit
Logic (Cont'd)
!1A
MOSFET Switch
VBR(DSS)
IDRAIN = 100 !1A
Full
rDS(en)
IDRAIN - 100 rnA
Room
Drain Off Leakage Current
IDSS
VDRAIN = 150 V
Drain Capacitancee
CDS
Breakdown Voltage
Drain-Source On-Resistance&
V
3
5
Q
Room
5
10
!1A
Room
35
pF
Notes
a_ Refer to PROCESS omON FLOWCHART for additional information_
b. Room = 25'C, Cold and Hot = as determined by the operating temperature suffIX.
c. 'lYpical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. CSTRAY @ OSC IN s: 5 pR
g. Temperature coefficient of roS(en) is 0.75% per 'c, typical.
Timing Waveforms
1.5V SOURCE
o -
r--r -
--j td
0~1O%
Vee
DRAIN
-
t[s10ns
...
SH"'UTD
...."'O"'W"""N Vee
tr s 10 ns
o
-
Figure 2.
Figure 1.
SHUTDOWN
::O----5o-<}1~"{50%f=~ ~ J~
RESET
0
r-r -
--j tSD
0~10%
Vee
DRAIN
_______
,,"Om
~;(50%
50% ~
, ~tRW__..J ' - -
Figure 3.
P-34984-Rev. B (04/18/94)
Preliminary
3-19
TEMIC
Si9104
Siliconix
lYpical Characteristics
Output Switching Frequency
vs. Oscillator Resistance
+VIN vs. +IIN at Start-Up
1M
140
Vie
=
I-vIII
120
.....
II
100
II
~
J
60
40
20
---
lOOk
.9
V
V
"'-
~
80
/
I
1-
o
10
15
10k
20
10k
1M
lOOk
rose - Oscillator Resistance (Q)
+lIN (rnA)
Pin Configurations
PDIP-14
SO-16
(Wide-Body)
PLCC-20
Top View
ThpView
Top View
Order Number: Si9104DJ
Order Number: Si9104DW
Order Number: Si9104DN
3-20
Preliminary
P-34984-Rev. B (04/18/94)
TEMIC
Si9104
Siliconix
Pin Configurations (Cont'd)
Pin Number
Function
14-Pln Plastic DIP
16-PlnSOIC
ZO-Pin PLCC
SOURCE
4
1
2
7
8
9
10
VREF
5
6
7
8
9
10
SHUTDOWN
RESET
COMP
12
13
FB
14
BIAS
1
2
3
"IN
Vee
OSColIT
OSCIN
DISCHARGE
+VIN
DRAIN
NC
4
5
6
7
8
9
10
11
11
12
13
14
16
3,15
11
12
14
16
17
18
20
2
3
5
1,4,6, 13, 15, 19
Detailed Description
Pre-RegulatorIStart-Up Section
Due to the low quiescent current requirement of the
Si9104 control circuitry, bias power can be supplied from
the unregulated input power source, from an external
regulated low-voltage supply, or from an auxiliary
"bootstrap" winding on the output inductor or
transformer.
When power is first applied during start-up, + VIN will
draw a constant current. The magnitude of this current
is determined by a high-voltage depletion MOSFET
device which is connected between + VIN and VCC. This
start-up circuitry provides initial power to the IC by
charging an external bypass capacitance connected to
the Vcc pin. The constant current is disabled when Vcc
exceeds 9.4 V. IfVcc is not forced to exceed the 9.4-V
threshold, then Vcc will be regulated to a nominal value
of 9.4 V by the pre-regulator circuit.
As the supply voltage rises toward the normal operating
conditions, an internal undervoltage (DV) lockout
circuit keeps the output MOSFET disabled until Vcc
exceeds the undervoltage lockout threshold (typically
8.8 V). This guarantees that the control logic will be
functioning properly and that sufficient gate drive
P-34984-Rev. B (04118/94)
voltage is available before the MOSFET turns on. The
design of the IC is such that the undervoltage lockout
threshold will not exceed the pre-regulator turn-off
voltage. Power dissipation can be minimized by
providing an external power source to Vccsuch that the
constant current source is always disabled.
Note: During start-up or when Vcc drops below 9.4-V
the start-up circuit is capable of sourcing up to 20 rnA.
This may lead to a high level of power dissipation in the
IC (for a 48-V input, approximately 1 W). Excessive
start-up time caused by external loading of the Vcc
supply can result in device damage. For typical
pre-regulator current at start-up as a function of input
voltage see Typical Characteristics, "+VIN vs. +IIN at
Start-Up" (page 3-20).
BIAS
To properly set the bias for the Si9104, a 390-k Q resistor
should be tied from BIAS to -V IN. This determines the
magnitUde of bias current in all of the analog sections
and the pull-up current for the SHUTDOWN and
RESET pins. The current flowing in the bias resistor is
nominally 15 (.lA.
Preliminary
3-21
TEMIC
Si9104
Siliconix
Detailed Description (Cont'd)
Reference Section
The reference section of the Si9104 consists of a
temperature compensated buried zener and trimmable
divider network. The output of the reference section is
connected internally to the non-inverting input of the
error amplifier. Nominal reference output voltage is 4 V.
The trimming procedure that is used on the Si9104
brings the output of the error amplifier (which is
configured for unity gain during trimming) to within
± 1.0% of 4 V. This compensates for the input offset
voltage in the error amplifier.
The output impedance of the reference section has been
purposely made high so that a low impedance external
voltage source can be used to override the internal
voltage source, if desired, without otherwise altering the
performance of the device.
pulse width, typical values would be 100 pF in series with
3kOtoOSCIN.
SHUTDOWN and RESET
SHUTDOWN and RESET are intended for overriding
the output MOSFET switch via external control logic.
The two inputs are fed through a latch preceding the
output switch. Depending on the logic state of RESET,
SHUTDOWN can be either a latched or unlatched
input. The output is off whenever SHUTDOWN is low.
By simultaneously having SHUTDOWN and RESET
low, the latch is set and SHUTDOWN has no effect until
RESEr goes high. The truth table for these inputs is
given in Table 1.
Thble 1:
lhIth Table for the SHUTDOWN and RESET Pins
Error Amplifier
Closed-loop regulation is provided by the error
amplifier, which is intended for use with negative
feedback compensation. A MOS differential input stage
provides for low input current. The noninverting input
to the error amplifier (VREF) is internally connected to
the output of the reference supply and should be
bypassed with a capacitor to ground (0.1 llF typically).
Osciiiator Section
The oscillator consists of a ring of CMOS inverters,
capacitors, and a capacitor discharge switch. Frequency
is set by an external resistor between OSC IN and OSC
OUT. (See Applications section for details of resistor
value vs. frequency.) The DISCHARGE should be tied
to, -VIN for normal internal oscillator operation. A
frequency divider in the logic section limits switch duty
cycle to :s; 50% by locking the switching frequency to
one half of the oscillator frequency.
Remote synchronization can be accomplished by
capacitive coupling of a synchronization pulse into the
OSC IN terminal. For a 5-V pulse amplitude and 0.5-11s
3-22
SHUTDOWN
RESEr
Output
H
H
Normal Operation
H
~
H
Normal Operation (No Change)
L
L
L
Off (Latched)
r
L
Off (Latched, No Change)
Off (Not Latched)
Doth pins have internal current :;curce pu11~ups and
should be left disconnected when not in use. An added
feature of the current sources is the ability to connect a
capacitor and an open-collector driver to the
SHUTDOWN or RESET pins to provide variable
shutdown time.
Output Switch
The output switch is a 5-0, 200-V lateral DMOS device.
Like discrete power MOSFETs, the switch contains an
intrinsic body-drain diode. However, the body contact in
the Si9104 is connected internally to -VIN and is
independent of the SOURCE.
Preliminary
P-34984-Rev. B (04/18/94)
TEMIC
Si9104
Siliconix
Applications
+VIN
GND
IN5819
100"H
o.J
2
L.
j3
:=0.1 "F
150"H
20"F
1
r
7l
1
16
2
~
14
:,=0.1 "F
I 150llOkQ
Ail" IN4148
i
6 -v
Pins 3, 9, 10, and 15 are no connect
IN( -48VDC)
Figure 4.
P·34984-Rev. B (04/18/94)
One·Watt Flyback Converter for Telecommunications Power Supplies
Preliminary
3-23
TEMIC
Si9105
Siliconix
l-W High-Voltage Switchmode Regulator
Features
• CCITT Compatible
• Current-Mode Control
• Low Power Consumption
(less than 5 mW)
• Current-Mode Control
• SHUTDOWN and RESET
• 10- to 120-V Input Range
• 200-V, 250-mA MOSFET
• Internal Start-Up Circuit
Description
The Si9105 high-voltage switchmode regulator is a
monolithic BiC/DMOS integrated circuit which contains
most of the components necessary to implement a
high-efficiency dc/dc converter in ISDN terminals up to
3 watts. A O.5-rnA max supply current makes possible
the design of a dc/dc converter with 60% efficiency at
25 mW, therefore meeting the recommended
performance under the CCnT I.430 specifications.
This device may be used with an appropriate
transformer to implement isolated flyback power
converter topologies to provide single or multiple
regulated dc outputs (i.e., ± 5 V).
The Si9105 is available in 16-pin wide-body sorc,
14-pin plastic, and 20-pin PLCC packages, and is
specified over the industrial, D suffix (-40 to 85°C)
temperature range.
Functional Block Diagram
FB
CaMP
DISCHARGE
OSC
IN
OSC
OUT
~~l l~
~
VREF
Clock V,
rose)
Current-Mode
Q
S
DRAIN
1.2 V
BIAS
0-----1
Th
Internal
Circuits
"'---0
L-----------+-+--------"---o
-VIN
(BODY)
SOURCE
Vee
Undervo!tage Comparator
3-24
1>---+-1---0
SHUTDOWN
I---~--o
RESET
P-34984-Rev. E(04/18/94)
TEMIC
Si9105
Siliconix
Absolute Maximum Ratings
Voltages Referenced to - VIN (Vee < + VIN + 03 V)
Vee .............................................. 15V
+VIN ............................................. 120V
Vos ........................................... 200V
10 (Peak)(?OO IJS pulse, 2% duty cycle) ..................... 2 A
10 (rms) ......................................... 250 rnA
Logic Inputs (RESET,
SHUTDOWN,OSCIN) ................. -03 V to Vee + 03V
Linear Inputs (FEEDBACK, SOURCE) . . . . . . . . . .. -0.3 V to 7 V
HV Pre-Reguiatorinput Current (continuous) ............. 5 mA
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .. -65 to 125'C
Operating Temperature ..............
-40 to 85'C
Junction 1emperature (TJ) ........... .... ....... . .. 150'C
Power DISsipation (Package)"
14-Pin Plastic DIP (J SuffIx)b .. . ..................... 750 mW
16-Pin Plastic Wide-Body SOIC (W SuffIX)C ............. 900 mW
20·Pm PLCC (N SuffIX)d ............. . ............ 1400 mW
Thermal Impedance (eJA)
14-Pin Plastic DIP ................................. 167'C!W
16-Pin Plastic Wide-Body SOIC . . . . . . . . . . . . . .. . ..... 140'C!W
20-Pm PLCC .. . ........... . .................... 90'C!W
Notes
a. Device mounted wIth all leads soldered or welded to PC board.
b. Derate 6 mW/,C above 25'C
c. Derate 7.2mW/'Cabove 25'C
d Derate 112mW/'Cabove25'C
Recommended Operating R.ange
Voltages Refereneed to - VIN
Vee ....................................... 10Vto13.5V
Rose .............. ....................... 25 ill to 1 MQ
+VIN ....................................... lOVto120V
Linear Inputs ................................ 0 to Vee - 3 V
fose ...................................... 40 kHz to 1 MHz
Digital Inputs ...................................... 0 to Vee
Specificationsa
Test Conditions Unless
Otherwise Specified
Parameter
Limits
D SuffIX -40 to 8S'C
Symbol
DISCHARGE = - VIN = 0 V
Vee = 10V,+VIN=48V
RBIAS = 820 ill, Rose = 910 kQ
Tempb
Mind
'IYPc
Max d
Unit
VR
OSC IN = VIN (OSC Disabled)
RL = 10MQ
Room
3.92
4.00
4.08
V
ill
Reference
Output Voltage
Output Impedance"
ZoUT
OSCIN = -VIN
Room
15
300
45
Short Circuit Current
ISREF
OSC IN = - VIN, VREF = - VIN
Room
70
100
130
)lA
Temperature Stability"
TREF
OSCIN = -VIN
Full
025
1.0
mV/,C
t = 1000 hrs, TA = 125'C
Room
5.00
25.00
mV
Long Term Stability"
Oscillator
Maximum Frequency"
fMAX
Rose = 0
Room
1
3
Initial Accuracy
fose
SeeNotee
Room
32
40
48
Voltage Stability
!;.f/f
!;.f/f = f (13.5 V) - f (9.5 V)/f (9.5 V)
Room
10
15
%
Full
200
500
ppm/'C
3.96
4
4.04
V
25
500
nA
60
80
Thmperature Coefficient"
Tose
MHz
kHz
Error Amplifier
Feedback Input Voltage
Input BIAS Current
Open Loop Voltage Gaine
P-34984-Rev. E(04/18/94)
FB TIed to COMP
OSC IN = - VIN (OSC Disabled)
Room
IFB
OSCIN = -VIN, VFB = 4 V
Room
AVOL
OSC IN = - VIN (OSC Disabled)
Room
VFB
dB
3-25
TEMIC
Si9105
Siliconix
Specifications a
Test Conditions Unless
Otherwise Specified
Parameter
Symbol
DISCHARGE = -VIN = OV
Vee = lOY, +VIN = 48 V
RBIAS = 820 kQ, Rose = 910 kQ
Limits
D SuffIX -40 to 85°C
Tempb
Mind
1YPc
Max 80%)
• Reference Selection
Si9110 - ±1%
Si9111 - ± 10%
• Internal Start-Up Circuit
• Internal Oscillator (1 MHz)
• SHU1DOWN and RESET
Description
The Si9110/9111 are BiC/DMOS integrated circuits
designed for use as high-performance switchmode
controllers. A high-voltage DMOS input allows the
controller to work over a wide range of input voltages
(10- to 120-VDC). Current-mode PWM control circuitry
is implemented in CMOS to reduce internal power
consumption to less than 10 mw'
A push-pull output driver provides high-speed switching
for MOSPOWER devices large enough to supply 50 W
of output power. When combined with an output
MOSFETand transformer, the Si9110/9111 can be used
to implement single-ended power converter topologies
(i.e., flyback, forward, and cuk).
The Si9110/9111 is available in 14-pin plastic DIP, SOIC
and CerDIP packages, and are specified over the
military, A suffix ( - 55 to 125 DC) and industrial, D suffix
(-40 to 85 DC) temperature ranges.
~
()
Functional Block Diagram
c2
-=
~
FB
CaMP
DISCHARGE
~M
13
14
OSC OSC
IN OUT
Error
Amplifier
.....
~a;
tnr
u~
~~
Ut'd
~;
Th
=~
t'
Vee
10
VREF
0
°iil
Current-Mode
r..~
~
~
Q
OUTPUT
S
-VIN
r..
~
If
1.2 V
Th
BIAS
Vee
SENSE
Circuits
6
Undervoltage
Comparator
+VIN
S
Q
R
11
12
SHUTDOWN
RESET
Pre-RegulatorlStart-Up
P-34830-Rev. C (04/25/94)
3-31
.....
.....
=t'd
o=:l
U
TEMIC
Si9110/9111
Siliconix
Absolute Maximum Ratings
Voltages Referenced to - VIN (Note: Vee < + VIN + 0.3 V)
Power Dissipation (Package)a
14-Pin eerDiP (KSufflX)b .......................... 1000 mW
14-Pin Plastic DIP (J Suffix)C ......................... 750 mW
14-Pin SOIC (Y SUfflX)d ............................. 900 mW
Vee ................................................ 15V
+VIN .............................................. 120V
Logic Inputs (RESET,
SHUIDOWN, OSC IN, OSC OU1) ....... -0.3 V to Vee + 0.3 V
Thermal Impedance (ElJA)
14-Pin eerDiP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1OO'C/W
14-Pin Plastic DIP ................................. 167'C/W
14-Pin SOIC ..................................... 140'C/W
Linear Inputs
(FEEDBACK, SENSE, BIAS, VREF) ...... -0.3 V to Vee + 0.3 V
HV Pre-Regulator Input Current (continuous) ............. 5 rnA
Storage Thmperature . . . . . . . . . . . . . . . . . . . . . . . . . .. -65 to 150'C
Operating Thmperature
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 10 mW/,C above 50'C.
c. Derate 6 mW/,C above 25'C.
d. Derate 7.2 mW/,C above 25'C.
(A Suffix) .............. -55tol25'C
(0 Suffix) .. .. .. .. . .. . ... -40 to 85'C
Junction Thmperature (TJ) ............................. 150'C
Recommended Operating Range
Voltages Refereneed to - VIN
Vee ....................................... 9.5Vto13.5V
+VIN ....................................... 10Vto120V
Rose ...................................... 25kQtolMg
Linear Inputs ................................ 0 to Vee - 3 V
fose ...................................... 40 kHz to 1 MHz
DigitalInputs ...................................... 0 to Vee
Specifications a
A Sufl"1X
-55 to 125'C
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
DISCHARGE = -VIN = OV
Vee = lOY, +VIN = 48 V
RBIAS = 390 kQ, Rose = 330 leg
D Sufl"1X
-40 to 85'C
'Thmpb
'JYpc
Mind
Maxd
Mind
Maxd
Si9110
Reom
4.0
3.92
4.08
OM
J.71..
~.vo
Si9111
Room
4.0
Si9110
Full
Unit
Reference
Output Voltage
VR
OSCIN = -VIN
(OSC Disabled)
RL= 10Mg
Si9111
Output Impedance"
ZoUT
Short Circuit Current
ISREF
Thmperature Stability"
TREF
VREP= -VIN
Full
• no
3.60
4.40
3.60
4.40
3.82
4.16
3.S6
4.14
4.46
V
3.50
4.48
3.52
Room
30
15
45
15
45
Room
100
70
130
70
130
i'A
Full
0.50
1.0
mV/'C
1.0
leg
Oscillator
Maximum Frequency"
Initial Accuracy
Voltage Stability
Thmperature Coefficient"
fMAX
fose
l1f!f
Rose=O
Room
3
1
Rose = 330 k, See Note f
Room
100
SO
120
80
120
Rose = 150 k, See Note f
Room
200
160
240
160
240
l1f!f=f(13.5 V) - f(9.5 V)/f(9.5 V)
Room
10
15
15
%
Full
200
500
500
ppm/'C
Si9110
Room
4.00
3.96
4.04
3.96
4.04
Si9111
Room
4.00
3.60
4.40
3.60
4.40
Room
25
Tose
1
MHz
kHz
Error Amplifier
Feedback Input Voltage
Input BIAS Current
3-32
VFB
IFB
FB Tied to COMP
OSCIN = -VIN
(OSC Disabled)
V
OSCIN - - VIN. VFB - 4 V
500
500
nA
P-34830-Rev. C (04/25/94)
TEMIC
Si9110/9111
Siliconix
Specifications a
A Suffix
-55 to 125'C
Test Conditions
Unless Otherwise Specified
Parameter
DISCHARGE = -VIN = OV
Vee = lOY, +VIN = 48 V
RBIAS = 390 kQ, Rose = 330 kQ
D Suffix
-40t085'C
Tempb
'JYpc
Vos
Room
±15
AVOL
Room
80
60
60
dB
Room
1.3
1
1
MHz
Room
1000
Source (VFB = 3.4 V)
Room
-2.0
Sink (VFB = 4 5 V)
Room
0.15
0.12
0.12
9.5 V s Vee s 13.5 V
Room
70
50
50
1.0
Symbol
Mind
Max d
Mind
Max d
Unit
±40
mV
Error Amplifier (Cont'd)
Input OFFSET Voltage
Open Loop Voltage Game
Unity Gain Bandwidth"
Dynamic Output
BW
Impedancee
ZOUT
Output Current
lOUT
Power Supply Rejection
PSRR
OSCIN = - VIN
(OSC Disabled)
±40
2000
2000
-1.4
Q
-1.4
rnA
dB
Current Limit
Threshold Voltage
VSOURCE
VFB=OV
Room
1.2
Delay to Output"
td
VSENSE = 1.5 Y, See FIgure 1
Room
100
1.4
1.0
150
1.4
V
150
ns
10
IlA
Pre-Regulator/Start-Up
Input Voltage
+VIN
lIN = 101lA
Room
Input Leakage Current
+lIN
Vee;;: 9.4 V
Room
120
120
Pre-Regulator
Start-Up Current
ISTART
Pulse Width S 300 "s, Vee = VULVO
Room
15
8
Vee Pre-Regulator
111m-Off Threshold
Voltage
VREG
IpRE-REGULATOR = 10 IlA
Room
86
7.8
9.4
7.8
9.4
8.9
7.0
8.9
10
V
8
rnA
V
Undervoltage Lockout
VUVLO
Room
8.1
7.0
VREG-VUVLO
VDELTA
Room
0.6
0.3
03
Supply
Supply Current
Bias Current
lee
CLOAD < 75 pF (Pin 4)
IBIAS
Room
0.6
0.45
1.0
0.45
1.0
rnA
Room
15
10
20
10
20
IlA
50
Logic
SHUTDOWN Delay<
tSD
CL = 500 pF, VSENSE - VIN
See Figure 2
Room
SHUTDOWN
Pulse Width"
tsw
See Figure 3
Room
50
50
RESET Pulse Width"
tRW
Room
50
50
Latching Pulse Width
SHUTDOWN and
RESET Low<
tLW
Room
25
25
100
100
ns
See Figure 3
Input Low Voltage
VIL
Room
Input High Voltage
VIH
Room
P-3483(}-Rev. C (04/25/94)
2.0
2.0
V
8
8
3-33
TEMIC
Si9110/9111
Siliconix
Specifications a
Test Conditions
Unless Otherwise Specified
ASuft-.x
-55 to 125'C
Symbol
DISCHARGE = -VIN = OV
Vee = lOY, +VIN = 48V
RBIAS = 390 ill, Rose = 330 ill
Thmpb
'JYpc
Input Current
Input Voltage High
1m
VIN=lOV
Room
1
Input Current
Input Voltage Low
IlL
VIN=OV
Room
-25
Output High Voltage
VOH
lOUT = -lOrnA
Room
Full
Output Low Voltage
VOL
lOUT = lOrnA
Room
Full
Output Resistance
ROUT
lOUT = 10 rnA, Source or Sink
Room
Full
Parameter
Logi~
Mind
Maxd
D Suffix
-40 to 85'C
Maxd
Mind
Unit
(Cunt'd)
5
5
J!A
-35
-35
9.7
9.5
9.7
9.5
Output
Rise1imee
tr
Fall1imee
tf
CL= 500pF
0.30
0.50
0.30
0.50
20
25
30
50
30
35
Room
40
75
75
Room
40
75
75
V
g
ns
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25'C, Full = as determined by the operating temperature suffIX.
c. 1Ypica1 values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
e. Guaranteed by design, not subject to production test.
f. CSTRAY Pin 8 = s 5 pR
Timing Waveforms
Vcc
1.5V
SENSE
tf S 10ns
SHU'IDOWN
o
o
~r90%
vcc
._ ....
O
OUTPUT
Figure 1.
.
~
Figure 2.
Vee
SHU'IDOWN
o -
Vee
RESET
o
Figure 3.
3-34
P-34830-Rev. C (04/25/94)
TEMIC
Si9110/9111
Siliconix
lYpical Characteristics
Output Switching Frequency vs.
Oscillator Resistance
+VIN vs. +lIN at Start-Up
140
1M
JeeJ -v~
120
......
II
100
~
1/
;;s
~
[
80
60
/
40
20
o
./
1- ~
10
g lOOk
I
.....
,/
10k
10k
20
15
I'..
'"
lOOk
1M
rose (Q)
+lIN (rnA)
Pin Configurations
Dual-In-Line and sOle
BIAS
14 FB
+VIN
Order Numbers
SENSE
OUTPUT
11 SHUIDOWN
-VIN
10 VREF
CerDIP: Si9110AK
Plastic DIP: Si9110DJ, Si9111DJ
SOlC: Si9110DY, Si9111DY
DISCHARGE
1bpView
Detailed Description
Pre-RegulatorIStart-Up Section
Due to the low quiescent current requirement of the
Si9110/9111 control circuitry, bias power can be supplied
from the unregulated input power source, from an
external regulated low-voltage supply, or from an
auxiliary "bootstrap" winding on the output inductor or
transformer.
When power is first applied during start-up, +VIN (pin 2)
will draw a constant current. The magnitude of this current
is detennined by a high-voltage depletion MOSFET device
which is connected between +VIN and Vcc (pin 6). This
start-up circuitry provides initial power to the IC by
charging an external bypass capacitance connected to the
Vcc pin. The constant current is disabled when Vcc
exceeds 8.6 V. If Vcc is not forced to exceed the 8.6-V
P-34830-Rev. C (04/25/94)
threshold, then Vcc will be regulated to a nominal value of
8.6 V by the pre-regulator circuit.
As the supply voltage rises toward the normal operating
conditions, an internal undervoltage (UV) lockout
circuit keeps the output driver disabled until V cc
exceeds the undervoltage lockout threshold (typically
8.1 V). This guarantees that the control logic will
be functioning properly and that sufficient gate drive
voltage is available before the MOSFET turns on. The
design of the IC is such that the undervoltage lockout
threshold will be at least 300 mV less than the
pre-regulator turn-off voltage. Power dissipation can be
minimized by providing an external power source to Vcc
such that the constant current source is always disabled.
3-35
TEMIC
Si9110/9111
Siliconix
Detailed Description (Cont'd)
Note: During start-up or when Vcc drops below 8.6 V
the start-up circuit is capable of sourcing up to 20 rnA.
This may lead to a high level of power dissipation in the
IC (for a 48-V input, approximately 1 W). Excessive
start-up time caused by external loading of the Vcc
supply can result in device damage. Figure 4 gives the
typical pre-regula tor current at BiC/DM OS as a function
of input voltage.
BIAS
To properly set the bias for the Si9110/9111, a 390-kQ
resistor should be tied from BIAS (pin 1) to -VIN
(pin 5). This determines the magnitude of bias current
in all of the analog sections and the pull-up current for
the SHUDOWN and RESET pins. The current flowing
in the bias resistor is nominally 15 11A.
Reference Section
The reference section of the Si9110 consists of a
temperature compensated buried zener and trimmable
divider network. The output of the reference section is
connected internally to the non-inverting input of the
error amplifier. Nominal reference output voltage is 4 V.
The trimming procedure that is used on the Si9110
brings the output of the error amplifier (which is
configured for unity gain during trimming) to within
± 1% of 4 V. This compensa tes for input offset voltage in
the error amplifier.
The output impedance of the reference section has been
purposely made high so that a low impedance external
voltage source can be used to override the internal
voltage source, if desired, without otherwise altering the
performance of the device.
The noninverting input to the error amplifier (VREF) is
internally connected to the output of the reference
supply and should be bypassed with a small capacitor to
ground.
Oscillator Section
The oscillator consists of a ring of CMOS inverters,
capacitors, and a capacitor discharge switch. Frequency
is set by an external resistor between the OSC IN and
OSC OUT pins. (See Figure 5 for details of resistor value
vs. frequency.) The DISCHARGE pin should be tied to
-VIN for normal internal oscillator operation. A
frequency divider in the logic section limits switch duty
cycle to :::; 50% by locking the switching frequency to
one half of the oscillator frequency.
Remote synchronization is accomplished by capacitive
coupling of a positive SYNC pulse into the OSC IN
(pin 8) terminal. For a 5-V pulse amplitude and 0.5-l1s
pulse width, typical values would be 100 pF in series with
3 kQ to pin 8.
SHUTDOWN and RESET
SHUTDOWN (pin 11) and RESET (pin 12) are
intended for overriding the output MOSFET switch via
external control logic. The two inputs are fed through a
latch preceding the output switch. Depending on the
logic state of RESET, SHUTDOWN can be either a
latched or unlatched input. The output is off whenever
SHUTDOWN is low. By simultaneously having
SHUTDOWN and RESET low, the latch is set and
SHUTDOWN has no effect until RESET goes high. The
truth table for these inputs is given in Table 1.
Table 1: Truth Table for the SHUTDOWN and RESET Pins
Applications which use a separate external reference,
such as non-isolated converter topologies and circuits
employing optical coupling in the feedback loop, do not
require a trimmed voltage reference with 1% accuracy.
The Si9111 accommodates the requirements of these
applications at a lower cost, by leaving the reference
voltage untrimmed. The 10% accurate reference thus
provided is sufficient to establish a dc bias point for the
error amplifier.
Error Amplifier
Closed-loop regulation is provided by the error
amplifier, which is intended for use with
"around-the-amplifier" compensation. AMOS
differential input stage provides for low input current.
3-36
SHUTDOWN
RESET
Output
H
H
Normal Operation
H
t.
Normal Operation (No Change)
L
H
Off (Not Latched)
L
L
Off (Latched)
.f"
L
Off (Latched. No Change)
Both pins have internal current source pull-ups and
should be left disconnected when not in use. An added
feature of the current sources is the ability to connect a
capacitor and an open-collector driver to the
SHUTDOWN or RESET pins to provide variable
shutdown time.
P·34830-Rev. C (04/25/94)
TEMIC
Si9110/9111
Siliconix
Detailed Description (Cont'd)
Output Driver
The push-pull driver output has a typical on-resistance
of20 Q. Maximum switching times are specified at 75 ns
for a 500-pF load. This is sufficient to directly drive
MOSFETs such as the 2N7004, 2N7005, IRFD120 and
IRFD220. Larger devices can be driven, but switching
times will be lon~er, resulting in higher switching losses.
In order to dnve large MOSPOWER devices, it is
necessary to use an external driver Ie such as the
Siliconix D469A. The D469A can swit~h very large
devices such as the SMM20N50 (500 V, 0.3 Q) in
approximately 100 ns.
Applications
IN5822
f.~--~---~---o @075A
+5V
GNDo----r------------------~----------~
OSCSYNC
PULSE
2
0.022"F
13
0.1 "F
Vee
>-_ _ _......!!.l6
10
,~'::F .
-5V
@0.25A
1N4148
Si91l0
2N7004
18 k
12k
Hl
Y,W
-48V
Figure 4.
P·34830-Rev. C (04125/94)
S-Watt Power Supply for Telecom Applications
3-37
TEMIC
Si9112
Siliconix
High-Voltage Switchmode Controller
Features
_ 9- to 80-V Input Range
- Current-Mode Control
- High-Speed, Source-Sink Output Drive
_ High Efficiency Operation (> 80%)
_ Internal Start-Up Circuit
- Internal Oscillator (1 MHz)
- SHUTDOWN and RESET
Description
The Si9112 is a BiC/DMOS integrated circuit designed
for use in high-efficiency switchmode power converters.
A high-voltage DMOS input allows this controller to
work over a wide range of input voltages (9- to 80-VDC).
Current-mode PWM control circuitry is implemented in
CMOS to reduce internal power consumption to less
than 10mW.
A CMOS output driver provides high-speed switching of
MOSPOWER devices large enough to supply 50 W of
output power. When combined with an output
MOSFET and transformer, the Si9112 can be used to
implement single-ended power converter topologies
(i.e., fJyback, forward, and cuk).
The Si9112 is available in 14-pin plastic DIP, and SOIC
packages, and is specified over the industrial, D suffix
(-40 to 85°C) temperature range.
Functional Block Diagram
FB
COMP
DISCHARGE
OSC
IN
1b
Vee
10
Q
01ITPUT
S
-VIN
1.2 V
BIAS
1b
Internal
Circuits
3
SENSE
Vee
Undervoltage Comparator
S
Q
R
11
12
SHUTDOWN
RESET
Pre-Regulator/Start-Vp
3-38
P-34983-Rev. C (04fZ5!94)
TEMIC
Si9112
Siliconix
Absolute Maximum Ratings
Voltages Referenced to - VIN (Vee < + VIN + 0.3 V)
V~
Junction Temperature (Tl) ............................. 150°C
................................................
~V
+VIN ............................................... 80V
Logic Inputs
(RESET, "SH~Ui'iT'i'DV'O"WUiUN, OSC IN) ......... -0.3 V to Vee + 0.3 V
Linear Inputs (FEEDBACK, SENSE) ...... -0.3 V to Vee to 0.3 V
HV Pre-Regulator Input Current (continuous) ............ 25 rnA
(Power Dissipation Limited)
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .. -65 to 150°C
Operating Temperature ......................... -40 to 85°C
Power Dissipation (Package)a
14-Pin Plastic DIP (J SuffIx)b ......................... 750 mW
14-Pin SOIC (Y SuffIX)C ............................. 900 mW
Thermal Impedance (EllA)
14-Pin Plastic DIP ........................ .
14-PinSOIC
167"C/W
140°C/W
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate6mWrCabove25°C.
c. Derate 7.2 mWrCabove 25°C.
Recommended Operating Range
Voltages Referenced to - VIN
Vee ......................................... 9Vto13.5V
Rose ...................................... 25 ill to 1 MQ
+ VIN ......................................... 9 V to 80 V
fose ...................................... 40 kHz to 1 MHz
Linear Inputs ................................ 0 to Vee - 3 V
Digital Inputs ...................................... 0 to Vee
Specifications a
Limits
D SuffIX -40 to 85°C
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
DISCHARGE = -VIN = OV
Vee = 9Y, +VIN = 12V
RBlAS = 270 ill, Rose = 330 ill
VR
OSC IN = - VIN (OSC Disabled)
RL= 10MQ
Tempb
Mind
Type
Max·
Unit
Room
3.88
3.82
4.0
4.12
4.14
V
ill
Reference
Output Voltage
Output Impedancee
ZOUT
Short Circuit Current
ISREF
Temperature Stability"
TREF
VREF- -VIN
Full"
Room
15
30
45
Room
70
100
130
I'A
0.5
1.0
mV/oC
Full
Oscillator
Maximum Frequency"
fMAX
Initial Accuracy
fose
Voltage Stability
M/f
Temperature Coefficiente
Rose = 0
Room
1
3
Rose = 330 k, See Note f
Room
80
100
120
Rose - 150 k, See Note f
Room
160
200
240
M/f = f(13.5 V) - f(9.5 V) / f(9.5 V)
Room
9
15
%
Full
200
500
ppmrC
4.00
4.08
V
±15
±40
mV
25
500
Tose
MHz
kHz
Error Amplifier
Feedback Input Voltage
Input Offset Voltage
Input BIAS Current
Open Loop Voltage Gaine
Unity Gain Bandwldthe
Dynamic Output Impedancec
Output Current
Power Supply Rejection
VFB
FB ned to COMP
OSC IN = - VIN (OSC Disabled)
Room
Vas
OSC IN = - VIN (OSC Disabled)
Room
IFB
OSCIN - - VIN, VFB - 4 V
Room
AVOL
OSCIN = - VIN
Room
60
BW
OSC IN = - VIN (OSC Disabled)
Room
1
ZOUT
Error Amp Configured for 60 dB gain
Room
1000
2000
Source VFB = 3.4 V
Room
-2.0
-1.4
Sink VFB = 4.5 V
Room
0.12
0.15
9V" Vee" 13.5 V
Room
50
70
lOUT
C
P-34983-Rev. C (04/25/94)
PSRR
3.92
80
nA
dB
1.5
MHz
Q
rnA
dB
3-39
TEMIC
Si9112
Siliconix
Specificationsa
Umits
D SuffIX -40 to 85"C
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
DISCHARGE = - VIN = 0 V
Vee = 9V,+VIN = 12V
RBIAS = 270 ill, Rosc = 330 ill
Tempb
Minf
1.0
1YPc
MaxB
Unit
Current Umit
Threshold Voltage
VSOURCE
VFB=OV
Room
Delay to Output"
td
VSENSE = 1.5 V, See Figure 1
Room
1.2
1.4
V
100
150
ns
Pre-Regulator/Start-Up
10~A
Input Voltage
+VIN
Input Leakage Current
+lIN
Vee '" 9.4 V
Room
Pre-Regulator Dropout Voltage
Vcc
+VIN = 10 V, RLOAD = 4 katPin6
Room
VUVLO
+0.1
VREG
IpRE.REGULATOR = 10 ~
Room
8.0
Undervoltage Lockout
VUVLO
See Detailed Description
Room
VREG-VUVLO
VDELTA
Room
Vee Pre-Regulator Thrn-Off
Threshold Voltage
lIN =
Room
V
80
10
~
8.7
9.4
V
7.2
8.1
8.9
0.3
0.6
Supply
Supply Current
Bias Current
Icc
CL
S
75 pF (Pin 4)
IBIAS
Room
0.6
Room
15
Room
50
1.0
rnA
~
Logic
SHUTDOWN Delay"
tSD
CL = 500pF
VSENSE = -VIN, See Figure 2
SHUTDOWN Pulse Width"
tsw
Room
50
RESET Pulse Wid the
tRW
Room
50
25
See Figure 3
100
ns
Latching Pulse Width
SHUTDOWN and RESET Low"
LLW
Room
Input Low Voltage
VIL
Room
Input High Voltage
Vm
Room
Input Current Input Voltage High
1m
VLOGIC- Vcc
Room
Input Current Input Voltage Low
IlL
VIN=OV
Room
-35
Output High Voltage
VOH
lOUT = -lOrnA
Room
Full
8.7
8.5
Output Low Voltage
VOL
lOUT = lOrnA
Room
Full
Output Resistance"
ROUT
lOUT = 10 rnA, Source or Sink
Room
Full
20
25
30
35
Room
40
75
Room
40
75
2.0
V
5
~
7.0
1
25
Output
Rise TIme<
tr
FallTImee
tf
CL= 500pF
0.3
0.5
V
g
ns
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25"C, Full = as determined by the operating temperature suffIX.
c. 'iYPical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
e. Guaranteed by design, not subject to production test.
f. CSTRAY Pin 8 = S 5 pR
3-40
P-34983-Rev. C (04/25/94)
TEMIC
Si9112
Siliconix
Timing Waveforms
Vee
SHUTDOWN
SENSE
o
Ir S 10 ns
d
~
Vee
OUTPUT
0-
50%
Ie s lOns
o Vee
90%
OUTPUT
o
Figure 1.
~rnnDL
~~
Figure 2.
Vee
SHUTDOWN
o -
Vee
RESET
o -
Figure 3.
'!ypical Characteristics
Output Switching Frequency
vs. Oscillator Resistance
+VIN vs. +lIN at Start.Up
140
1M
V~e= ~v~
120
I"'-
100
'"
80
60
/
40
-
20
o
10
S
V
./
I10k
15
+I1N(mA)
P·34983-Rev. C (04/25/94)
{lOOk
I
20
10k
lOOk
1M
rose - Oscillator Resistance (Q)
3·41
TEMIC
Si9112
Siliconix
Pin Configurations
Dual-In-Line and SOIC
BIAS
FB
+VIN
eOMP
SENSE
Order Numbers
RESET
OUTPUT
SHUTDOWN
-VIN
Plastic DIP: Si9112DJ
sOle: Si9112DY
Vee
OseOUT
ThpView
Detailed Description
Pre-RegulatorIStart-Up Section
Due to the low quiescent current requirement of the
Si9112 control circuitry, bias power can be supplied from
the unregulated input power source, from an external
regulated low-voltage supply, or from an auxiliary
"bootstrap" winding on the output inductor or
transformer.
When power is first applied during start-up, +VIN
(pin 2) will draw a constant current. The maguitude of
this current is determined by a high-voltage depletion
MOSFET device which is connected between +VIN and
Vee (pin 6). This start-up circuitry provides initial
power to the Ie by charging an external bypass
capacitance connected to the Vee pin. The charging
current is disabled when Vee exceeds 8.7 V. If Vee is not
forced to exceed the 8.7-V threshold, then Vee will be
regulated to a nominal value of 8.7 V by the
pre-regulator circuit.
As the supply voltage rises toward the normal operating
conditions, an internal undervoltage (UV) lockout
circuit keeps the output driver disabled until Vee
exceeds the UV lockout threshold (typically 8.1 V). This
guarantees that the control logic will be functioning
properly and that sufficient gate drive voltage is
available before the MOSFET turns on. The design of
the IC is such that the undervoltage lockout threshold
will be at least 300 mV less than the pre-regula,tor
turn-offvoItage. Power dissipation can be minimized by
providing an external power source to Vee such that the
pre-regulator circuit is disabled.
BIAS
To properly set the bias for the Si9112, a 270-k g resistor
should be tied from BIAS (pin 1) to - VIN (pin 5). This
3-42
determines the magnitude of bias current in all of the
analog sections and the pull-up current for the
SHUTDOWN and RESET pins. The current flowing in
the bias resistor is nominally 15 1lA.
Reference Section
The reference section of the Si9112 consists of a
temperature compensated buried zener and trimmable
divider network. The output of the reference section is
connected internally to the non-inverting input of the
error amplifier. Nominal reference output voltage is 4 V.
The trimming procedure that is used on the Si9112
brings the output uf th~ ellOI diliplifier (which is
configured for unity gain during trimming) to within
± 2% of 4 V. This automatically compensates for input
offset voltage in the error amplifier.
The output impedance of the reference section has been
purposely made high so that a low impedance external
voltage source can be used to override the internal
voltage source, if desired, without otherwise altering the
performance of the device.
Error Amplifier
Closed-loop regulation is provided by the error
amplifier. The emitter follower output has a typical
dynamic output impedance of 1000 g, and is intended
for use with "around-the-amplifier" compensation. A
MOS differential input stage provides low input leakage
current. The noninverting input to the error amplifier
(VREF) is internally connected to the output of the
reference supply and should be bypassed with a small
capacitor to ground.
P-34983-Rev. e (04/25/94)
TEMIC
Si9112
Siliconix
Detailed Description (Cont'd)
Oscillator Section
The oscillator consists of a ring of CMOS inverters,
capacitors, and a capacitor discharge switch. Frequency
is set by an external resistor between the OSC IN and
OSC OUT pins. (See Typical Characteristics for details
of resistor value vs. frequency.) The DISCHARGE pin
should be tied to -VIN for normal internal oscillator
operation. A frequency divider in the logic section limits
switch duty cycle to oS 50% by locking the switching
frequency to one half of the oscillator frequency.
Remote synchronization can be accomplished by
capacitive coupling of a SYNC pulse into the OSC IN
(pin 8) terminal. For a 5-V pulse amplitude and 0.5-!ls
pulse width, typical values would be 100 pF in series with
3kQtopin8.
Table 1: Truth Table for the SHUTDOWN and RESET Pins
SHUTDOWN
RESET
Output
H
H
Normal Operation
H
t.
Normal Operation (No Change)
L
H
Off (Not Latched)
L
L
Off (Latched)
L
Off (Latched, No Change)
r
Both pins have internal current source pull-ups and
should be left disconnected when not in use. An added
feature of the current sources is the ability to connect a
capacitor and an open-collector driver to the
SHUTDOWN or RESET pins to provide variable
shutdown time.
SHUTDOWN and RESET
Output Driver
SHUTDOWN (pin 11) and RESET (pin 12) are
intended for overriding the output MOSFET switch via
external control logic. The two inputs are fed through a
latch preceding the output switch. Depending on the
logic state of RESET, SHUTDOWN can be either a
latched or unlatched input. The output is off whenever
SHUTDOWN is low. By simultaneously having
SHUTDOWN and RESET low, the latch is set and
SHUTDOWN has no effect until RESET goes high. The
truth table for these inputs is given in Table 1.
P·34983-Rev. C (04/25194)
The push-pull driver output has a typical on-resistance
of 20 Q. Maximum switching times are specified at 75 ns
for a 500 pF load. This is sufficient to directly drive 60-V,
25-A MOSFETs. Larger devices can be driven, but
switching times will be longer, resulting in higher
switching losses.
For applications information refer to AN703.
3-43
TEMIC
Si9114
Siliconix
High-Frequency Switchmode Controller
Features
• 15- to 200-V Input Range
• Current-Mode Control
• Internal Start-Up Circuit
• Latched SHUIDOWN
• Soft-Start
• 1.5-MHz Error Amp
Description
The Si9114 is a BiC/DMOS current-mode pulse width
modulation (PWM) controller IC for high-frequency
dc/dc converters. Single-ended topologies (forward and
flyback) can be implemented at frequencies up to
1 MHz. The oscillator has an internal divide-by-two that
limits the duty ratio to 50%. An oscillator sync output
allows converters to be synchronized in phase as well as
in frequency, in a master/slave configuration.
minimize supply current requirements.
The high-voltage DMOS transistor allows the IC to
interface directly to bus voltages up to 200 V. Other
features include a 1.5% accurate voltage reference,
1.5-MHz (min) bandwidth error amplifier, shutdown
logic control, soft-start and undervoltage lockout
circuits.
The output inverter can typically source 500 rnA and sink
700 rnA. Shoot-through current is all but eliminated to
The Si9114 is available in 14-pin plastic DIP and SOlC
packages, and is specified over the industrial, D suffix
( -40 0 C to 85 0 C) temperature range.
Functional Block Diagram
CURRENT
FB
COMPENSATION
SENSE
SYNC
~-;,:;--F-----iE-----Amplifier
I
I
Rose
8
10
,-1--..1....,
I
I
4-@
I
I
I
SS
,
I
I
,--...,---,1
Enable
NI
VREF
Case
9
+
Gen
I
I
I
I
I
I
112
71
Vee
Q
s
I
111
I
I
I
I
12
DRIVER
OlITPUT
SHUTDOWN
Undervoltage
Lockout
9.2V
L _________________________________ J
3-44
Preliminary
P-36732-Rev. B (05/30/94)
TEMIC
Si9114
Siliconix
Absolute Maximum Ratings
Voltages Referenced to - VIN
Vee ............................................... 18V
+VIN(Note: Vee<+VIN+O.3V) ..................... 200V
Logic Input (SHUTDOWN, SYNC) ...... -03 V to Vee + 0.3 V
Linear Inputs (FEEDBACK, SENSE,
SOFf·START) ......................... -0.3 V to Vee + 0.3 V
HV Pre-Regulator Input Current (continuous) ............. 5 mA
Storage Temperature. . . . .. .................... -65 to 150'C
Operating Temperature ......................... -40 to 85'C
Junction Temperature (TI) .. . ........................ 150'C
Power Dissipation (Package)'
14-Pin Plashc Dip (J SuffIx)b . . ...................... 750 mW
14-Pin SOIC (Y SuffIx)c. ..... . ................... 900 mW
Thermal Impedance (SIA)
14-Pin Plastic Dip
. . ....... 167'CfW
14-Pin SOIC ..................................... 140'CfW
Notes
a. Device mounted WIth all leads soldered or welded to PC board.
b. Derate 6 mWI'C above 25'C.
c. Derate 7.2 mW/'C above 25'C.
Recommended Operating Range
Voltages Referenced to - VIN
Vee .. .. .. .
. . ................... 9.5 V to 16.5 V
+VIN ...................................... 15Vt0200V
fose ..................................... 20 kHz to 2 MHz
Rose ...................................... 56 kQ to 1 MQ
. .. . .......... 47 pF to 200 pF
Linearinputs ................................ 0 to Vee - 4 V
Digital Inputs. . . . . . .. . ............................ 0 to Vee
Case .....................
Specifications
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
Limits
D SuffIX -40 to 85'C
Oscillator Disabled
-VIN = Ov, Vee = 10V
Min b
lYr"
Maxb
OSCDisabled, TA = 25'C
3.94
4.0
4.06
OSC Disabled
Over Voltage and Temperature Rangesc
3.88
4.0
4.12
Unit
Reference
Output Voltage
Short Circuit Current
Load Regulation
VR
V
ISREF
VREF = -VIN
-15
-5
mA
AVR/l~IR
IREF=Oto-3mA
3
40
mV
Oscillator
Initial Accuracy
fosed
Rose = 374 kQ, Case = 200 pF
90
100
110
Rose = 133 kQ, Case = 100 pF
450
500
5S0
1
2
%
200
500
ppml'C
AUf
Rose = 133 kQ, Case = 100 pF
AUf = [f(16.5 V) - f(9.5 V)]I f(9.5 V)
'Thmperature CoeffIcientC
OSCTC
-40 :S TA :S 85'C, fose = 100 kHz
Sync Output Current (Master Mode)
ISYNC(M)
VRose:S SV
Sync Output Current (Slave Mode)
ISYNC(S)
VRose- Vee
Voltage Stability"
P-36732-Rev. B (OS130/94)
Preliminary
±1.0
±3.0
±1
kHz
mA
±SOO
nA
3-45
TEMIC
Si9114
Siliconix
Specifications a
Limits
D SuffIX -40 to 85'C
Test Conditions
Unless Otherwise Specified
Parameter
Error Amplifier (Cosc
Symbol
Oscillator Disabled
-VIN = ov, Vee = 10V
Minb
Typ"
Maxb
±25
±200
nA
±5
±25
rnV
Unit
= - VlN OSC Disabled)
Input BIAS Current
IFB
VFB = 5 V, NI = VREF
Input OFFSET Voltage
VOS2
Open Loop Voltage Gain·
AVOL
65
88
dB
BW
1.5
2.3
MHz
Unity Gain Bandwidth·
-2.0
Source (VFB = 3.5 V, NI = VREF)
Output Current
Power Supply Rejection
lOUT
PSRR
Sink (VFB = 4.5 V, NI = VREF)
1.0
4.0
9.5 V s Vee s 16.5 V
SO
88
-1.0
rnA
dB
Pre-Regulator/Start-Up
Input Leakage Current
Pre-Regulator Start-Up Current
Vee Pre-Regulator Voltage
+lIN
ISTAR!"
<1
+VIN = 200 V, Vee"' 10V
+VIN = 48 V, tpw S
300~.
Vee = VUVLO
20
10
~A
rnA
8.8
9.1
9.4
VPR -VUVLO (Thrn-On)
VDELTA
0.1
0.2
0.7
Undervoltage Lockout Hysteresis
VHYST
0.18
0.3
0.4
VPR
+VIN=48V
8
V
Supply
Supply Current
lee
CLOAD S 50pF
I
I
fose = 100 kHz
1.3
2.5
fose = 500 kHz
1.8
3.0
rnA
Protection
Current Limit Threshold Voltage
VSENSE
VFB = OV,NI = VREF
1.23
1.30
V
Current Limit Delay to Output·
Id
VSENSE = 1.5 V, See Figure 1
70
100
ns
SHUTDOWN Logic Threshold
VSD
2.5
0.5
V
SHUTDOWN Delay to Latched Output·
tSD
See Figure 2
0.30
1.0
~s
SHUTDOWN Pull-Up Current
ISD
VSD = OV
12
17
30
Soft-Start Current
Iss
12
17
30
1.7
0.5
Output Inhibit Voltage
VSS(off)
Soft-Start Voltage to Disable Driver Output
Output High Voltage
VOH
lOUT = -lOrnA
Output Low Voltage
VOL
lOUT = lOrnA
1.15
~A
V
MOSFET Driver
Peak Output Current·
ISOURCE
VOUT= OV
ISINK
VOUT=Vee
9.85
9.9
0.05
0.15
-400
-200
V
rnA
500
700
Notes
a. 'lYpical values are for DESIGN AID ONLY. not guaranteed nor subject to production testing.
b.
The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c.
d.
Guaranteed by design. not subject to production test.
CSTRAY S 5 pF on Case.
3-46
Preliminary
P-36732-Rev. B (05/30/94)
TEMIC
Si9114
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Oscillator Frequency
1000
r--- _
I--- r--- -
!5
100pF
150pF
200pF
!
"
~" 'r-.. ...
~~
100
"e
~
r
10
10
""."
~
40
~
20
E
Note: These curves were
measured in a board with
3.5 pF of external parasitic
II-
cartrTlll1
o
1000
1
"g
U
.;:.
c.
c.
:s
CIl
I
u
.5l
Vee = 12V
Case = 47 pF
9
10
/
16
12
V
8
/
4
o
V
I
l/
-
io-""'"
~
12
13
14
R~se=1127~
Case = 47pF
fs = 500kHz
1
9
t::
:s
U
.;:.
c.
c.
:s
6
""
CL=100~
~
11
P
,~
",
",
~
" ,V
16
17
CIl
I
u
CL=OpF
-
3
.5l
"
CL = 1000pF
Q
~
o
15
Supply Current vs. Supply Voltage
12
V
CL= 2500p~'
20
tr for CL = 1000 pF
Vee - Supply Voltage (V)
V
24
-
--"\
o
Supply Current vs. Output Frequency
[
I. J
tf for CL = 2500 pF
Itf forlCL =II000IPF
I I
36
r-
I
-
0
100
28
J
tr for CL = 2500 pF
~.L
I I
-
...
rose - Oscillator Resistance (kQ)
32
I I I
.... ~
60
~
.B
I
Output Driver Rise and Fall Time
80
47pF
-"1--
1
0 --"\
200
400
600
800
o
1000
9
fOUT - Output Frequency (kHz)
10
11
12
13
14
15
16
17
Vee - Supply Voltage (V)
Switching Frequency vs. Supply Voltage
1.05
R~sc ~56~
Case = 47pF
:i
1.00
~
0.95
,.. ....- ~
~
-
"
:s
C"
I.t:"
on
0.90
:§"
~
0.85
~
0
8
9
10
11
12
13
14
15
16
17
Vee - Supply Voltage (V)
P-36732-Rev. B (05/30/94)
Preliminary
3-47
TEMIC
Si9114
Siliconix
Timing Waveforms
Vee
1.5 V-
50%
Current
--j
Vee-
Output
Output
r
tf:S; lOns
ITU"'1"'D"'O"'W"N'"
"'SH
tr:s; lOns
Sense
tSD
~o
Figure 2.
Figure 1.
Pin Configurations
Dual-In-Line and sOle
Vee
SHUTDOWN
CURRENT SENSE
VREF
DRIVER OUTPUT
NI
-VIN
FB
SYNC
COMPENSATION
SS
Order Numbers
Plastic DIP: Si9114DJ
SOIC: Si9114DY
Case
7
8
Rose
Top View
Applications
+VIN
SO
VREF
NI
FB
COMP
SS
Vee
SENSEr---+-----r-~
OUT / - - / - - - t - t '
- VIN r--l--...,
SYNC
Case
Rose
U1
Si9114
-48 V (-42 to -56 V)
Figure 3.
3-48
15-W Forward Converter Schematic
Preliminary
P·36732-Rev. B (05/30/94)
TEMIC
Si9120
Siliconix
Universal Input Switchmode Controller
Features
• 10- to 4S0-V Input Range
• Current-Mode Control
• 12S-mA Output Drive
• Internal Start-Up Circuit
• Internal Oscillator (1 MHz)
• SHUTDOWN and RESET
Description
The Si9120 is a BiC/DMOS integrated circuit designed for
use in low-power, high-efficiency off-line power supplies.
High-voltage DMOS inputs allow the controller to work
over a wide range of input voltages (10- to 450-VDC).
Current-mode PWM control circuitry is implemented in
CMOS to reduce quiescent current to less than 1.5 mA.
A CMOS output driver provides high-speed switching
for MOSFET devices with gate charge, Qg, up to 25 nC,
enough to supply 30 W of output power at 100 kHz.
These devices, when combined with an output MOSFET
and transformer, can be used to implement single-ended
power converter topologies (i.e., flyback and forward).
The Si9120 is available in a 16-pin plastic DIP and SOlC
packages, and is specified over the industrial, D suffix
(-40 to 85°C) temperature range.
~
Functional Block Diagram
CJ
~
~
FB
COMP
DISCHARGE
14
15
OSC
OUT
t%
Error
Amplifier
VREF
OSC
IN
101
-= ....
:S5i
uS
~~
u=
~;
Th
=~
t'
Vee
Q
0;
Current-Mode
'"'~
~::;
Q
OUTPUT
S
-VIN
~'"'
£
1.2 V
16
BIAS 0----1
Vce
Th
Internal
Circuits
7
'-------------t--+-------:::------o
Undervoltage Comparator
12
13
SENSE
SHU'IDOWN
RESET
Pre-Regulator/Start-Up
P34830--Rev. D (04125/94)
~=
Q=
U
3-49
TEMIC
Si9120
Siliconix
Absolute Maximum Ratings
Voltages Referenced to -VIN (Note: Vee < +VIN + 0.3 V)
Vee ................................................ 15V
+VIN .............................................. 450V
Logic Inputs (RESET
SHUTDOWN, OSC IN, OSC OUI) ....... -0.3 V to Vee + 0.3 V
Unearlnput
(FEEDBACK, SENSE, BIAS, VRBF) ............. -0.3 V to 7 V
HV Pre-Regulator Input Current (continuous) ............. 5 rnA"
Continuous Output Current (Source or Sink) . . . . . . . . . . .. 125 rnA
Storage Thmperature . . . . . . . . . . . . . . . . . . . . . . . . . .. -65 to 150°C
Operating Temperature ......................... -40 to 85°C
Junction Thmperature (TI) ............................. 150°C
Power Dissipation (Package)b
16-Pin Plastic DIP (J Sufflx)C ......................... 750 mW
16-PinSOIC(YSufflx)d ............................. 9OOmW
Thermal Impedance (EllA)
16-Pin Plastic DIP ................................. 167°C/W
16-Pin SOIC ..................................... 140°C/W
Notes
a. Continuous current may be limited by the applications maximum
input voltage and the package power dissipation.
b. Device mounted with all leads soldered or welded to PC board.
c. Derate6mWrCabove25°C.
d. Derate 7.2 mWrC above 25°C.
Recommended Operating Range
Voltages Referenced to - VIN
Vee ....................................... 9.5Vto13.5V
+VIN ....................................... 10Vt0450V
fose ...................................... 40 kHz to 1 MHz
Rose ...................................... 25WtolMQ
Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to Vee - 3 V
Digital Inputs ...................................... 0 to Vee
Specifications8
Test Conditions
Unless Otherwise Specified
Parameter
Limits
D SuffIX -40 to 85°C
Symbol
DISCHARGE = -VIN = OV;
Vee = 10V +VIN = 300 V
RBIAS = 390 kn Rose = 330 W
Tempb
Mine
'JYpd
Max"
VR
OSC IN = - VIN (OSC Disabled)
RL=10MQ
Room
Full
3.88
3.82
4.0
4.12
4.14
V
kQ
Unit
Reference
Output Voltage
Output Impedance<
ZOUT
Short Circuit Current
ISRBF
Thmperature Stability"
TREF
VRBF= -VIN
Room
15
30
45
Room
70
100
130
i!A
0.5
1.0
mVrC
Full
Oscillator
Maximum Frequency"
Initial Accuracy
Voltage Stability
Thmperature Coefficient·
fMAX
fose
Aflr
Room
1
3
CSTRAY Pin 9 S
5 pF, Rose = 330 W
Room
80
100
120
Cs-rRAY Pin 9 S
5 pF, Rose = 150 kQ
Room
160
200
240
Rose = 0
Af/f = f(13.5 V) - f(9.5 V) / f(9.5 V)
Tose
MHz
kHz
Room
10
15
%
Full
200
500
ppm/°C
4.08
V
Error Amplifier
Feedback Input Voltage
VFB
FB ned to COMP
OSC IN = - VIN (OSC Disabled)
Room
3.92
Input BIAS Current
IFB
Room
2S
500
nA
Input OFFSET Voltage
Vos
OSCIN= -VIN
Room
±15
±40
mV
Open Loop Voltage Gainc
AVOL
OSCIN -
VIN
Room
60
80
dB
BW
OSCIN -
VIN
Room
1.0
1.5
MHz
Unity Gain Bandwidth"
Dynamic Output Impedancee
ZoUT
Output Current
lOUT
Power Supply Rejection
PSRR
3-50
OSCIN=
VIN, VFB = 4 V
Error Amp configured for 60 dB gain
Room
1000
2000
Source VFB - 3.4 V
Room
-2.0
1.4
Sink VFB = 4.5 V
Room
0.12
9.5 V :S Vee :S 13.5 V
Room
50
0.15
70
Q
rnA
dB
P34830-Rev. D (04/25/94)
TEMIC
Si9120
Siliconix
Specifications a
Test Conditions
Unless Otherwise Specified
Limits
D Suffix -40 to 85'C
v.
Parameter
Symbol
DISCHARGE = - VIN = 0
Vee = 10V +VIN = 300 V
RBIAS = 390 kQ Rose = 330 ill
Tempb
Mine
1.0
1Ypd
MaX<
Unit
Current Limit
Threshold Voltage
VSOUReE
VFB=OV
Room
Delay to Output"
td
VSENSE = 1.5 V. See Figure 1
Room
1.2
1.4
V
100
150
ns
10
JU\
Pre-Regulator/Start-Up
Input Voltage
+VIN
lIN = 10 JU\
Room
Input Leakage Current
+ lIN
Vee
Room
Vee Pre-Regulator Thrn-Off
Threshold Voltage
VREG
Undervoltage Lockout
VREG-VUVLO
2:
9.4 V
450
V
Room
7.8
8.6
9.4
VUVLO
Room
7.0
8.1
8.9
VDELTA
Room
0.3
0.6
IpRE-REGULATOR = 10 ~A
V
Supply
Supply Current
Bias Current
Icc
CL = 500 pF at Pin 5
Room
Room
IBIAS
10
0.85
1.5
rnA
15
20
JU\
50
100
Logic
SHUIDOWN Delay"
tso
SHUTDOWN Pulse Width"
tsw
RESET Pulse Width"
tRW
Latching Pulse Width
SHUIDOWN and RESET Low"
CL = 500 pF, VSENSE = - VIN
See Figure 2
~
Room
Room
50
Room
50
tLW
Room
25
Input Low Voltage
VIL
Room
Input High Voltage
Vm
Room
Input Current Input Voltage High
1m
VIN -lOV
Room
Input Current Input Voltage Low
IlL
VIN-OV
Room
See Figure 3
ns
....
2.0
1
,
V
JU\
-25
Output High Voltage
Output Low Voltage
Output Resistance
VOH
lOUT = -lOrnA
Full
V
lOUT = lOrnA
ROUT
lOUT = 10 rnA, Source or Sink
Room
Full
20
25
30
35
Room
40
75
Room
40
75
tr
te
CL=500pF
0.3
0.5
Q
ns
The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is llsed in this data sheet.
d. 1Ypical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing
c. Guaranteed by design, not subject to production tcst.
P34830-Rev. D (04/25/94)
=~~
0=
=~
U
Notes
a. Refer to PROCESS OmON FLOWCHART for additional information.
b. Room = 25'C, Cold and Hot = as determined by the operating temperature suffix.
c.
~;
i:'
~~
9.7
9.5
VOL
Fall Time"
~~
0
"{jJ
Room
Full
Rise Timee
uS
u~
5
Output
Room
--=
~
:!l~
8.0
-135
~
~
3-51
'~"'
~
TEMIC
Si9120
Siliconix
Timing Waveforms
Vee
SHU1DOWN
s
o ~
SENSE
Vee
OUTPUT
o
.5V
50%
tr
10ns
tr s 10ns
o -
~
Vee
OUTPUT
0'
~rnnOL
~
Figure 2.
Figure 1.
Vee
SHU1DOWN
o -
Vee
RESET
o -
Figure 3.
1Ypica! Characteristics
Output Switching Frequency
vs. Oscillator Resistance
1M
I"-
~
[
5 lOOk
.B
10k
10k
lOOk
1M
rose - Oscillator Resistance (Q)
3-52
P34830-Rev. D (04/25/94)
TEMIC
Si9120
Siliconix
Pin Configurations
sOle
Dual-In-Line
BIAS
+VIN
BIAS
+VIN
NC'
FB
FB
NC'
COMP
COMP
SENSE
SHUTDOWN
-VIN
-VIN
VREF
VREF
DISCHARGE
Vee
OSCOUT
OSCIN
8
RESET
SHUTDOWN
OUTPUT
DISCHARGE
Vee
OSCOUT
SENSE
RESET
OUTPUT
OSCIN
Top View
Top View
Order Number: Si9120DJ
Order Number' Si9120DY
Note: Pms 2 and 3 are removed
Detailed Description
Pre-ReguJator/Start-Up Section
Due to the low quiescent current requirement of the
Si9120 control circuitry, bias power can be supplied from
the unregulated input power source, from an external
regulated low-voltage supply, or from an auxiliary
"bootstrap" winding on the output inductor or
transformer.
When power is first applied during start-up, +VIN
(pin 1) will draw a constant current. The magnitude of
this current is determined by a high-voltage depletion
MOSFET which is connected between +VIN and Vcc
(pin 7). This start-up circuitry provides initial power to
the IC by charging an external bypass capacitance
connected to the Vcc pin. The constant current is
disabled when Vcc exceeds 8.6 V. If Vcc is not forced to
exceed the 8.6-V threshold, then Vcc will be regulated
to a nominal value of 8.6 V by the pre-regulator circuit.
As the supply voltage rises toward the normal operating
conditions, an internal undervoltage (VV) lockout
circuit keeps the output driver disabled until Vcc
exceeds the undervoltage lockout threshold (typically
8.1 V). This guarantees that the control logic will be
functioning properly and that sufficient gate drive
voltage is available before the MOSFET turns on. The
design of the IC is such that the undervoltage lockout
threshold will be at least 300 mV less than the
pre-regulator turn-off voltage. Power dissipation can be
minimized by providing an external power source to Vcc
such that the constant current source is always disabled.
P34830-Rev. D (04/25/94)
Note: When driving large MOSFETs at high frequency
without a bootstrap Vcc supply, power dissipation in the
pre-regulator may exceed the power rating of the IC
package.
BIAS
To properly set the bias for the Si9120, a 390-kQ resistor
should be tied from BIAS (pin 16) to - VIN (pin 6). This
determines the magnitude of bias current in all of the
analog sections and the pull-up current for the
SHUTDOWN and RESET pins. The current flowing in
the bias resistor is nominally 15 flA.
Reference Section
The reference section of the Si9120 consists of a
temperature compensated buried zener and trimmable
divider network. The output of the reference section is
connected internally to the non-inverting input of the
error amplifier. Nominal reference output voltage is 4 V.
The trimming procedure that is used on the Si9120
brings the output of the error amplifier (which is
configured for unity gain during trimming) to within
± 2% of 4 V. This compensates for input offset voltage
in the error amplifier.
The output impedance of the reference section has been
purposely made high so that a low impedance external
voltage source can be used to override the internal
voltage source, if desired, without otherwise altering the
performance of the device.
3-53
TEMIC
Si9120
Siliconix
Detailed Description (Cont'd)
Error Amplifier
Closed-loop regulation is provided by the error amplifier,
which is intended for use with "around-the-amplifier"
compensation. A MOS differential input stage provides for
high input impedance. The noninverting input to the error
amplifier (VREF) is internally connected to the output of
the reference supply and should be bypassed with a small
capacitor to ground.
Oscillator Section
The oscillator consists of a ring of CMOS inverters,
capacitors, and a capacitor discharge switch. Frequency is
set by an external resistor between the OSC IN and OSC
our pins. (See Typical Characteristics for details of
resistor value vs. frequency.) The DISCHARGE pin
should be tied to -VIN for normal internal oscillator
operation. A frequency divider in the logic section limits
switch duty cycle to :S 50% by locking the switching
frequency to one half of the oscillator frequency.
SHU1DOWN and RESET low, the latch is set and
SHU1DOWN has no effect until RESET goes high. See
Table 1.
Both pins have internal current source pull-ups and should
be left disconnected when not in use. An added feature of
the current sources is the ability to connect a capacitor and
an open-collector driver to the SHU1DOWN or RESEr
pins to provide variable shutdown time.
Table 1: lhItb Table for tbe SHU1DOWN and RESET Pins
SHUTDOWN
RESET
H
H
H
L
L
S
L
OUTPUT
Normal Operation
Normal Operation (No Change)
H
Off (Not Latched)
L
Off (Latched)
L
Off (Latched-No Change)
Output Driver
SHUTDOWN and RESET
SHU1DOWN (pin 12) and RESEr (pin 13) are intended
for overriding the output MOSFEf switch via external
control logic. The 1";.'0 inpu.~ are fed through :l latch
preceding the output switch. Depending on the logic state
of RESET. SHU1DOWN can be either a latched or
unlatched input. The output is off whenever
SHU1DOWN is low. By simultaneously having
3-54
The push-pull driver output has a typical on-resistance of
20 Q maximum switching times are specified at 75 ns for
a 500-pF load. This is sufficient to directly drive MOSFEfs
such as the IRF820, BUZ78 or BUZSO. Larger devices can
he driven, hut switching times will be longer. resulting in
higher switching losses.
For applications information refer to ANl07 and ANl08.
P34830-Rev. D (04/25/94)
TEMIC
Si9145
Siliconix
Low-Voltage Switchmode Controller
Features
Benefits
Applications
•
•
•
..
•
•
•
•
•
co
• DC/DC Converters
2.7-V to 7-V Input Operating Range
PWM Control
High-Speed, Source-Sink Output Drive (200 rnA)
Internal Oscillator (up to 2 MHz)
Standby Mode
• 50-100% Duty-Cycle Controllable Maximum
Cellular Telephones
Portable Computers
Handheld Instruments
Distributed Power Systems
Palmtop/PDA Terminals
Description
The Si9145 switchmode controller IC is ideally suited for
high efficiency dc/dc converters in battery input powered
systems. Operation is guaranteed down to 2.7 V; with a
minimum start-up voltage of 3.0 V making the Si9145
ideal for use with NiCd, NMH, and lithium ion battery
packs. A mode select pin allows the output driver
polarity to be programmed allowing the device to
function as a step-up or step-down converter.
voltage monitor with standby mode and a 200-mA
output driver. Supply current in normal operation is
typically 1 rnA and 250 IlA in standby mode.
The Si9145 implements conventional voltage mode
control. The maximum duty cycle can be limited by
voltage on DMAXISS pin and frequency can be externally
programmed by selection of Rose and Cose.
Features include a precision bandgap reference, a wide
bandwidth error amplifier, a 2-MHz oscillator, an input
The Si9145 is available in 16-pin SOlC and TSSOP
packages and is specified over the industrial
temperature range (-25°C to +85°C).
Functional Block Diagram
1.5 V
Reference
Voo
Generator
r---------------------~O V~
UVLOSET
s
ENABLE
L--------I-------jR
MODESELECf
DMAX/SS
COMP
Vs
NI
Logic
.>----+-----1 Control
FB
MOSFET DRIVER
GND
Case
Oscillator
Rose
P-35931-Rev. A (05/023/94)
Advance Information
3-55
TEMIC
Si9145
Siliconix
Absolute Maximum Ratings
Power Dissipation (Package)"
16-Pin SOIC (Y SufflX)b ............................. 900 mW
16-Pin TSSOP (Q SufflX)C ........................... 925 mW
Voltages Referenced to GND.
VDD,VS .............................................. BV
PGND ............................................. ±0.3 V
~m~
.........................................
Thermal Impedance (SJA)
16-Pin SOIC ..................................... 140°C/W
16-Pin TSSOP .................................... 135°C/W
~V
Linear Inputs ........................ -0.3 V to VDD to +0.3 V
Logic Inputs ......................... -0.3 V to VDD to +0.3 V
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 7.2 mW/oC above 25°C.
c. Derate 7.4 mWrC above 25°C.
Continuous Output Current. . . . . . . . . . . . . . . . . . . . . . . . .. 100 rnA
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .. -65 to 125°C
Operating Junction Temperature ........................ 150°C
Recommended Operating Range
Voltages Referenced to GND.
VDD .......................................... 2.7Vt07V
Vs ............................................ 2.7Vt07V
fose ....................................... 2 kHz to 2 MHz
Rose ...................................... 5 kQ to 250 kQ
Case ...................................... 47pFt0200pF
Linear Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to VDD
DlgitalInputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to VDD
VREF Load Resistance ............................... >150 kQ
Specifications a
Test Conditions
Unless Otherwise Specified
Parameter
2.7V s VDD S 7V,VDD = Vs
GND = PGND, -25°C S TA S 85°C
Symbol
Limits
B SuffIX - 25 to 85°C
Min b
lYpc
Max b
Unit
Reference
Output Voltage
IREF
= -10 ~A
VREF
1.455
TA = 25°C
1.485
1.545
1.50
1515
1.0
1.1
V
Oscillator
Maximum Frcquencyd
fMAX
Initial Accuracy
fose
Rose Voltage
= 3.0 V, Case = 47 pF, Rose = 5.0 kQ
Vee = 3.0V
TA = 25°C
Case = TBD pF, Rose = TBD kQ
Vee
1.0
VDMAX50%
100% DMAX/SS
VDMAXI00%
Temperature Stabilityd
3-56
MHz
3.0
50%DMAX/SS
Voltage Stability
0.9
VRose
Oscillator Start Voltage
DMAX/SS Input Current
2.0
IDMAX
MIf/!iV
MIAt
V
1.25
MODE SELECT = VDD
1.54
= 0 to VDD
-100
100
2.7V s VDD s 7V,Reft04.8V
-16
+16
DMAX
2.7 V s VDD s 4.2 V, Ref to 3.5 V
TA = 25°C
-6
+6
3.8 V s VDD s 5.6 V, Refto4.7V
-7
+7
Referenced to 25°C
-5
Advance Information
±3
nA
%
+5
P-35931-Rev. A (05/023/94)
TEMIC
Si9145
Siliconix
Specifications a
Test Conditions
Unless Otherwise Specified
Parameter
Error Amplifier (Case
2.7V s VDD S 7Y,VDD = Vs
GND = PGND, -25'C S TA S B5'C
Symbol
Limits
B SuffIX - 25 to B5'C
Minb
lYpc
Maxb
Unit
= GND, OSC DISABLED)
Input Bias Current
Open Loop Voltage Gain
IFB
VNI
= VREF, VFB = 1.0V
Offset Voltage
Vas
Unity GalD Bandwidthd
BW
Output Current
lEA
-1.0
47
AVOL
-15
VNI - VREF
~A
55
0
+15
to
= 1 Y, NI - VREF)
= 2 Y, NI - VREF)
Sink (VFB
rnA
OB
50
PSRR
rnV
MHz
-1.0
Source (VFB
Power Supply Rejection
dB
60
dB
Input Voltage Monitor
TBD
VUVLOHL
VDD High to Low
VUVLOLH
VDD Low to HIgh
Hysterrsis
VHYS
VUVLOLH - VUVLOHL
UVLO Input Current
IUVLO
VUVLO - 0 to VDD
-100
= 2.7 Y,lour = -to mA
2.55
Under Voltage Lockout
1.0
TBD
V
12
200
mV
100
nA
MOSFET Driver
Output HIgh Voltage
VOH
Output Low Voltage
VOL
Peak Output Current
ISOURCE
VDD - 2.7 Y, Vour - 0 V
Peak Output Current
ISINK
VDD - 2.7 Y, Vour - 2.7 V
VDD
VDD - 2.7 Y,lour - 10 rnA
150
2.60
V
0.06
015
-lBO
-130
rnA
200
Logic
ENABLE Delay to Output
tdEN
ENABLE Logic Low
VENL
ENABLE Logic HIgh
VENH
ENABLE Input Current
35
V
O.BVDD
ENABLE
lEN
MODE SELECT Logic Low
VMODEL
MODE SELECT Logic High
VMODEH
MODE SELECT Input Current
ns
0.2VDD
= 0 to VDD
-10
1.0
0.2VDD
O.BVDD
MODE SELECT - 0 to VDD
IMODE
10
10
~
V
~A
Over Temperature Sense
Trip Point
TTRIP
Output Low
VOTSL
VDD - 2.7Y, lour -1
Output High
VOTSH
VDD - 2.7Y,lour - -1
'c
150
~
~A
0.06
255
0.15
V
2.6
Supply
IDD
Supply Current - Shutdown
Notes
a. CSTRAY
= 2.7 Y, COSC = 1 MHz, Rose = 7.5 ill
1.1
TBD
VDD -7 Y, fosc - 1 MHz, Rosc - 7.5 ill
1.4
TBD
ENABLE-Low
250
TBD
VDD
Supply Current - Normal
rnA
~
< 5 pF on Casc.
h. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet
c.
d.
lYpicaI values are Cor DESIGN AID ONLY, not guaranteed nor subject to production testing.
Guaranteed by design, not subject to production testing.
P-35931-Rev. A (05/023/94)
Advance Information
3-57
TEMIC
Si9145
Siliconix
Timing Waveforms
Start-Up (UVLO)
Normal (Duty Cycle Limit)
Standby
ENABLE
MODESELECf
I
1.2V~
UVLOSET
~I
I
Rose
- - - - 11
i
I
~V
I
L
1.0V
I
I
I
Case
-~~
OUTPUT DRIVER
=----.nrlJ"L ""LSl.......fLJ
I
I
ON
OFF
>1.5V
Set for 50% Max.
DMAxfSS
Figure 1. Si9145 TlIDing Diagram (MODE SELECT
Start-Up (UVLO)
=High)
Standby
Normal (Duty Cycle Limit)
ENABLE
MODESELECf
UVLOSET
Rose
I
1.2V~ I
~i
~V
I
I
i
1.0 V
L
I
I
----II
I
Case
~'~
OUTPUT DRIVER
=----uLJLJ . JL..SL.JLI
I
I
OFF
ON
DMAX/SS
Figure 2.
3-58
Si9145 Timing Diagram (MODE SELECT
Advance Information
=Low)
P-35931-Rev. A (05/023/94)
TEMIC
Si9145
Siliconix
Pin Configurations
SO-16
VDD
MODE SELECf
SO-16 (TSSOP)
OUTPUT DRIVER
IS
2
VDD
MODE SELECf
COMP
4
UVLOSET
13
12
ENABLE
DMAX/SS
COMP
Vs
OUTPUT DRIVER
2
3
4
13
FB
PGND
UVLOSET
ENABLE
NI
Case
VREF
GND
7
Case
Rose
ThpView
GND
Order Number: Si9145BQ
Top View
Order Number: Si9145BY
Pin Description
Pin 1:
Pin 5: FB
VDD
The positive power supply for all functional blocks
except output driver. A bypass capacitor is required.
Pin 2: MODE SELECT
Pin used to enable max duty cycle limit and set output
polarity of controller. When connected to V DD, the max
duty cycle function is enabled by using the DMAX/SS pin.
The max duty cycle limit is usually for forward, flyback,
and boost converters. The output polarity is high when
the PWM circuitry wants the external device "on".
When connected to GND, the max duty cycle is not
limited usually for buck converters driving a p-channel
MOS. The output polarity is low when the PWM
circuitry wants the external PMOS "on".
Pin 3: DMAX/SS
Pin 6: NI
The non-inverting input ofthe error amplifier. In normal
operation it is externally connected to the VREF pin.
Pin 7: VREF
This pin supplies 1.5 V trimmed to ± 1%. The reference
voltage is generated by a band-gap reference.
PinS: GND
When max duty cycle function is enabled (MODE
SELECT = VDD), the voltage on this pin limits the max
duty cycle. Below 1.0 V the duty cycle is 0 and above
1.5 V the duty cycle is not limited, and can be 100%
depending on the PWM circuitry. The addition of
external components can implement a soft start
function.
Pin4: COMP
Output of error amplifier. A compensation network is
connected from this pin to the FB pin to stabilize the
system. This pin drives one input of the internal pulse
width modulation comparator.
P-35931-Rev. A (051023/94)
The inverting input of the error amplifier. External
resistors are connected to this pin to set the regulated
output voltage. The compensation network is also
connected to this pin.
Negative return for VDD.
Pin 9: Rose
This pin is the equivalent of a 1.0-V source derived from
the on-chip V REF. When a low T.C. resistor is externally
connected from this pin to GND, a temperature
independent current is generated internally. This
current is used as the charging current source connected
to the Cosc pin. The current is internally multiplied by
2 and is used as the discharging current source connected
to the Cosc pin. Therefore, the external resistor is one
of the factors that determine the oscillator frequency.
Advance Information
3-59
TEMIC
Si9145
Siliconix
Pin Description
Pin 10: Cosc
Pin 13: UVLOSET
An external capacitor is connected to this pin to set the
oscillator frequency. Internal current sources alternately
charge and discharge the external capacitor. The
oscillator waveform is a symmetrical triangular type with
a typical voltage swing between 1.0 V and 1.5 V.
This pin will place the chip in the standby mode if the
UVLO voltage is below 1.2 V. Once the UVLO voltage
exceeds 1.2 Y, the chip operates normally. There is a
built-in hysteresis of 200 mY, the UVLO pin must drop
below 1.0 V before the chip enters the standby mode.
Pin 11: OTS
Pin 14: PGND
This pin indicates an over-temperature condition on the
chip. An outputlowindicates an over-temperature fault.
The output is latched low and must be set with the
ENABLE pin going low then high, or by turning power
off and on.
The negative return for the Vs supply.
Pin 12: ENABLE
A logic high on this pin allows normal operation. A logic
low places the chip in the standby mode. In standby mode
normal operation is disabled, supply current is reduced,
the oscillator stops and the output is high for MODE
SELECf = low, and low for MODE SELECf = high.
Pin 15: OUTPUT DRIVER
CMOS push-pull output. This pin drives the external
MOSFET and is capable of sinking 200 rnA or sourcing
180 rnA with Vs equal to 2.7 V.
Pin 16: Vs
The positive terminal of an external battery or power
supply. The voltage on this pin powers the CMOS output
driver. A bypass capacitor is required.
Applications
Figure 3. Non·Isolated Step Up Boost Converterfor VOUT > VIN
L1
Bl
Cl
C2
D1
2.7V-7V
OV
Figure 4. Non·Isolated Step Down Buck Converter for VOUT < VIN
3-60
Advance Information
P-35931-Rev. A (05/023/94)
TEMIC
Si9145
Siliconix
Application Examples (Cont'd)
BI
CI
2.7V-7V
'---1>------t----O +Vo
~--~--~------+------~----~__o
Figure S.
P-3593I-Rev. A (05/023/94)
ov
Non-Isolated Synchronous Buck Converter for VOUT < VIN
Advance Information
3-61
TEMIC
Si9150
Siliconix
Synchronous Buck Converter Controller
Features
• 6- to 16.5-V Input Range (Si9150CY)
• Voltage-Mode PWM Control
• Low-Current Standby Mode
• Multiple Converters Easily Synchronized
• Over-Current Protection
• Enable Control
• Duall00-mA Output Drivers
• 2% Band Gap Reference
Description
The Si9150 synchronous buck regulator controller is
ideally suited for high-efficiency step down converters in
battery-powered equipment. Combined with the
Si9943DY MOSFET half-bridge, a 90% efficient, 7.5-W,
3.3-V or 5-V power supply can be implemented using
standard surface-mount assembly techniques. The wide
input range allows operation from NiCd or NiMH
battery packs using six to ten cells.
MOSFET, which eliminates the need for a current sense
resistor.
Duty ratios of 0 to 100% and switching frequencies up to
300 kHz are possible. The IC can be disabled by pulling
EN low (Inn = 100 IlA), or the 2.5-V reference can be
maintained, with all other functions disabled, by pulling
STBY low (Inn = 500 itA).
Over-current protection is achieved by sensing the
on-state voltage drop across the high side p-channel
The Si9150 is available in a 14-pin SDIC and rated for
the commercial temperature range of 0 to 70°C.
Functional Block Diagram
Oscillator,
Comparators,
& Error Amp
Reference
Generator
7
~---1------0I~~
2
STBYo-----------+----L-/
VDD
Q
S
BreakBefore_.-----.--:L.-Make
Logic
6
VREF
11
GNn
Synchronous Buck Regulator Controller
3-62
Preliminary
P-3S0S4-Rev. B (04/18/94)
TEMIC
Si9150
Siliconix
Absolute Maximum Ratings
Voltages Referenced to GND.
Power Dissipation (Package)a
14-Pm SOIC (Y SufflX)b ............................. 900 mW
VDD ................................................ 18V
Thermal Impedance (EllA)
14-Pin SOIC ........................ . ........... 140·C/W
ISENSElnput ............................. -2VtoVDD+2V
All Other Inputs ........................ -0.3 to VDD + 0.3 V
P-Gate, N-Gate Continuous Source/sink Current. . . . . . . . .. 50 rnA
Storage Temperature. . . . . . . . . . . . . .. ........... -65 to 125·C
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 7.2 mW("C.
Operating Junction Thmperature ........................ 150·C
Specifications a
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
Limits
C SuffIX - 0 to 70·C
Min b
6.0 s VDD s 16.5 V
"JYpc
Maxb
Unit
Reference
Output Voltage
TA ~ 25·C, Measured at Feedback", Pin 5
2.45
2.50
2.55
TMIN to TMAXd
2.425
2.500
2.575
VREF
V
Oscillator
Maximum Frequency
fMAX
Case ~94.3 pF, Rose ~ 28.7 k, TA ~ 25'C[
255
300
345
Initial Accuracy
fose
Case ~2l2 pF, Rose ~ 41.2 k, TA ~ 25'C[
85
100
115
TA ~ 2S·C, 100 kHz
2.05
2.65
2.85
V
-5
±3
+5
%
25
500
nA
60
72
25
mV
Oscillator Ramp Amplitude
Vose
Thmperature Stabilityd
fTEMP
VDD
~
10 V, TMIN to TMAX
kHz
Error Amplifier
Input BIAS Current
IB
Open Loop Voltage Gaind
AVOL
Offset Voltage
VOS
Unity Gain Bandwidthd
BW
VFB~VREF
10
1
Source, VeoMP
Output Current
Power Supply Rejection
lOUT
~
1.5
-0.30
2.50 V
dB
MHz
-0.20
rnA
Sink, VeoMP = 1.0 V
PSRR
1
2.5
50
70
0.43
0.49
0.55
V
500
1000
ns
dB
Protection
VCL
Current Limit Delay to Outputd
td
TA=2S·C
Undervoltage Lockout Voltage
VUVLO
Upper Threshold
Undervoltage Hysteresis
VHYS
Softstart Pull-Up Current
Iss
TA = 2S'C, VDD
~
Current Limit Threshold Voltage
lOV
5.4
5.7
6.0
0.10
0.17
0.25
V
!!A
20
Supply
Supply Current - Enable Low
IOFF
Supply Current - Enable High
Icc
Supply Current - STBY Low
ISB
P-35054-Rev. B (04/18/94)
CL ~ 0 pF, fose - 100 kHz, VDD
Preliminary
~
10 V
60
100
~A
2.2
3.0
rnA
300
500
~A
3-63
TEMIC
Si9150
Siliconix
Specifications a
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
Limits
C Suff", - 0 to 70'C
6.0 s VDD S 16.5 V
Minb
9.75
"JYpc
Maxb
Unit
Output
Output High Voltage
VOH
lOUT = lOrnA, VDD = 10V
Output Low Voltage
VOL
lOUT = -10 rnA, VDD = 10V
Output Resistance
ROUT
lOUT = 100 rnA, VDD = 10 V
Rise TImed
t,
Fall TImed
tr
0.25
CL = BOOpF, VDD = 10V
10
20
30
60
30
60
0.25
1
V
!J
ns
Logic
Delay to Output
td(EN)
Enable Pull-Up Resistance
REN
Thansition High to Low
500
~s
kIJ
STBY Pull-Up Current
ISTBY
TA = ZS'c, VSTBY = Ov. VDD = 10V
-25
-20
-15
Thrn-On Threshold
VENH
VDD = 10 V. Rising Input Voltage
6
6.B
B
Thrn-Off Threshold
VENL
VDD = 10 V. Falling Input Voltage
2
3.75
5
f.IA
V
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. 1}>pical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Guaranteed by design, not subject to production test.
e. The voltage reference is trimmed with the feedback (Pin 5) connected to compensation (Pin 4) so that the effect of the error amplifier's input
offset voltage is eliminated.
e. Case includes the PC board's parasitic capacitance.
Typical Chanicteristics
Oscillator Characteristics
1000
.....
~
""
I'" ~~
50pF
.~ !~~~
200pF
10
10
100
1000
rose - Oscillator Resistance (kIJ)
3-64
Preliminary
P-3S0S4-Rev. B (04/1BI94)
TEMIC
Si9150
Siliconix
Pin Configuration
sOle
EN
VDD
S'IJ\NOllY
P·GATE
SS
N·GATE
CaMP
GNO
Fll
RT
VREF
CT
SYNC
lSENSE
ThpView
Order Number: Si9150CY
Pin Description
Pin 1: EN
Pin 4: Compensation (COMP)
When this pin is low, the IC is shut down. After a low
signal is applied to EN, then COMp, REF, R'fi and CT
settle toward ground; N-GATE, STBY and Soft-Start
are grounded; and P·GATE is pulled high. The current
consumption is no more than 100 IlA in this state. This
input's threshold has substantial hysteresis so that a
capacitor to GND can be used to delay restart after the
current limit is activated. After VENH is exceeded, one
clock cycle elapses before N-GATE and P-GATE are
enabled. EN is pulled up to V00 through a SOO-k resistor
and is pulled down internally when the current limit is
triggered.
This pin is tied directly to the output of the error
amplifier. The feedback network which insures the
stability of an application uses this pin. COMP settles
low when either EN or STBY is pulled low.
Pin 5: Feedback (FB)
This pin is attached directly to the inverting input of the
error amplifier. This pin is used to regulate the power
supply's output voltage.
Pin 6: Reference (VREF)
Pin 2: STBY
Has a function similar to EN. The differences are that
the EN pin is unaffected, that the reference is still
available, that bias currents are,still present internally,
and that this pin's pull up current is present. This pin
should be used to disable an application if the reference
voltage is still needed.
The internaI2.5-V reference generator is attached to this
pin through a 5-g resistor. A O.l-IlF bypass capacitor is
needed to suppress noise. Also note that the generator
has an open emitter; it will not pull down. The maximum
current that the generator will source before it current
limits is about 10 rnA. Many parts of the IC use this
voltage, so it is important not to overload the reference
generator.
Pin 3: Soft·Start (SS)
Pin 7: ISENSE
This pin limits the maximum voltage that the error
amplifier can output. A capacitor between this pin and
ground will limit the rate at which the duty factor can
increase during initial power up, during a restart when
EN or STBY goes high, or after the current limit is
triggered. A capacitor here can prevent an application
from triggering the Si91S0's current limit during startup.
Soft-Start is pulled low if either EN or STBY is low.
This pin should be attached to the switched node (the
drains of the application's p-channel and n-channel
MOSFETh). If the voltage between Voo and this pin is
more then 0.46 V while the P-GATE is low, the current
limit is activated. The current limit is relatively slow to
prevent false triggering due to noise. Activating the
current limit causes EN to be pulled to GND. ISENSE may
be operated from Voo + 2 V to GND - 2 V.
P·350S4--Rev, B (04/18/94)
Preliminary
3-65
TEMIC
Si9150
Siliconix
Pin Description (Cont'd)
This pin forces the clock to reset when low, and is also
pulled low when the clock resets itself. Thus if several
Si9150's have their sync pins shorted together, they will
be synchronized; the shortest duration clock will control
the other clocks.
the p-channel power MOSFET. For noise immunity, it is
best to separa te the logic ground from the power ground.
The logic ground should be decoupled to Voo through
at least a l-IlF capacitor. The two grounds may be
connected by a path that is long compared to the the path
from Voo to the source of the application's p-channel
MOSFET.
Pin 9: CT
Pin 12: N-GATE
A capacitor from this pin to ground is charged until it
reaches 2.5 V; at which point the capacitor is rapidly
discharged. The resulting sawtooth with about 1 V added
is compared to the input voltage at COMP to determine
whether P-GATE and N-GATE should be high or low.
The maximum recommended value for Case is 200 pF
(See Typical Characteristics). The capacitor's charging
current is controlled by Pin 10, Rl'
This pin is used to drive the application's n-channel
MOSFET. When turning the n-channel MOSFET off,
the p-channel MOSFET will not be turned on until
N-GATE is within a few volts of ground. This pin is low
while either EN or STBY is low.
PinS: SYNC
Pin 10: RT
The IC applies 2.5 V to this pin, and the current is
mirrored and applied to Pin 9 while charging the
capacitor. The minimum recommended value of Rose is
20 kQ (Figure 1).
Pin 11: GND
Since the Si9150 has a high-side current limit, it is
important that Voo track the voltage on the source of
3-66
Pin 13: P-GATE
This pin is used to drive the application's p-channel
MOSFET. The break before make circuitry for the
P-GATE is complimentary to that for the N-GATE. This
pin is high while either EN or STBY is low.
Pin 14: VDD
This pin powers the IC. The connection between this pin
and the source of the p-channel FET should be as short
as practical. Read Pin 11's description for bypassing
suggestions.
Preliminary
P-3S0S4-Rev. B (04/18/94)
TEMIC
Si9150
Siliconix
Applications
- - - - - - - - - ----------.,I~
EN
100""
20Y
43!'lI
+sv
lOOl1F
GND
RlN
Si9150
Application Circuit
Figure 1. "'ypical
"'
P-35054-Rev. B (04/18/94)
Preliminary
3-67
TEMIC
Si9710CY
Siliconix
PCMCIA Interface Switch
Features
• Reverse Blocking Switches
• HiZ Outputs in the Off-State
• Single SO-16 Package
• CMOS Inputs with Hysteresis
• Extremely Low RoN
• Low Power Consumption
• Safe Power-Up
Description
The Si9710CY switch is a monolithic switch designed to
meet the needs ofthe PCMCIA interface. The inputs are
fully CMOS compatible and incorporate all the level
shift and interface required to be driven by any CMOS
driver. The external inputs can be driven to 3.3-V or S-V
by setting VL at the appropriate level. The switches are
low RON and can carry the maximum currents found on
the PCMCIA interface.
The S-V and 3.3-V switches do not have the parasitic
diode found in vertical DMOS power switches.
Low RON is achieved by using MOSFETs driven off the
+12-VIN input. All level shifting is built into the
PCMCIA switch.
The Si9710CY is available in an SO-16 package and is
rated over the commercial temperature range 0 to 70°C.
Functional Block Diagram
I~
+12VIN
+3.3 VIN
+3.3VIN
(13)
I
SI
I
I
(l1J
I
I
I
(9)
I
I
I
I
I
I
I
I
I
I
I
(10)
S3
I
I
rr
I
I
:I
I
I
I
(14)
3-68
(15)
LevelSbift
and
(16)
Drivers
(4)
(5)
(6)
(7)
S4
(8)
I
(12)
I
I
:
Vpp
Vpp
Vee
Vee
Vee
Vee
'fruth Table - SI through S4
Logie
Switch
0
OFF
1
ON
(2)
(1) ~
(3)
Preliminary
P-34980--Rev. B (05/09/94)
TEMIC
Si9710CY
Siliconix
Absolute Maximum Ratings
Voltages Referenced to Ground
Vpp ................................................. 15V
VL ................................................... 7V
+12 VIN ............................................. 15V
All Pins ............................................ -0.5 V
+5VIN·······.··········.······.·· .. · .. ·· ......... · .. 7V
+3.3VIN ............................................. 7V
S! through S4 (CMOS Inputs) ...................... VL + 0.5 V
lOUT Vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 300 mA
Vee ................................................. 7V
PD Max: (TA = 25'C) ............................. 710 mW
(TA = 70'C) ............................. 390 mW
lOUT Vee ....................................... 1500mA
Junction Temperature ................................. 125'C
Thermal Ratings
RaJA ........................................... 140 'c{w
Recommended Operating Conditions
+12 VIN ....................................... 12 V:t 10%
IOUTVee ....................................... 1000mA
+5VIN ......................................... 5V:t 10%
+ 3.3 VIN ..................................... 3.3 V :t 10%
lOUT Vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 150 rnA
VL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.0 V :t 10%
Specifications
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
+5 VIN = 5 Y, +3.3 VIN = 3.3 V
+12 VIN = 12 Y, VL = 5.0Y, GND = OV
Limits
C SuffIX, 0 to 70'C
Min"
1YP
Max"
Unit
SwItch 1
On-Resistance
RON
1= 120mA, +12 VIN = 10.8 V
S! =VL,S2 = GND
orfCurrent (+12 VIN to Vpp)
IOFF
+12 VIN = 13.2 Y, Vpp = OV
S! =GND
Swilching TIme
tS!(on)
CL = 0.1
~F,
TA=25'C
200
TA-70'C
250
TA-25'C
1
TA=70'C
10
S2 = Low, RL = 100 Q, See Figure 1
tS!(off)
0.1
1
0.5
4
mQ
i!A
~
Switch 2
On-Resistance
RON
1= 120mA, +12VIN = 10.8 V
S2=S3=VL
Off Corrent
IOFF
Vpp = 13.2Y, Vee = OV
+12 VIN = 13.2 V
Swilching TIme
tS2(on)
tS2(ofl)
CL = 0.1
TA=25'C
300
TA-70'C
350
TA-25'C
1
TA=70'C
10
~F,
RL = 100Q,S! = S4 = GND
S3 = VL, See Figure 1
0.1
1
0.5
4
mQ
i!A
~s
Switch 3
On-Resistance
RON
1= 500 mA, +12 VIN = 10.8 V
S3=VL
Off Corrent
IOFF
+5VIN = 5.5Y, Vee = OV
Switching TIme
tS3(on)
tS3(off)
P-34980-Rev. B (05/09/94)
TA=25'C
200
TA-70'C
250
TA=25'C
1
TA=70'C
10
+5 VIN = 5 Y, CL = 0.1 ~F, Vee to GND
RL = 100 Q, Vee to GND, See Figure 2
Preliminary
0.1
1
0.5
4
mQ
~A
~s
3-69
TEMIC
Si9710CY
Siliconix
Specifications
Limits
C SUffIX, 0 to 70' C
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
+5 VIN = 5 V, +3.3 VIN = 3.3 V
+12VIN = 12 V, VL = 5.0V,GND = OV
1YP
Min"
Max"
Unit
Switch 4
On-Resistance
RON
Off Current
IOFF
tS4(on)
Switching TIme
tS4(off)
1= 500mA, +12 VIN = 10.8 V
S4=VL
TA=25'C
150
TA=70'C
185
+3.3 VIN = 3.6 V, Vee = 0 V
TA=25'C
1
~=S3=S4=GND
TA-70'C
10
+3.3 VIN = 3.3 V, CL = 0.1 JlF, S3 = GND
RL = 100 Q, See Figure 2
0.1
1
0.5
4
mQ
I1A
Jls
Power Supply
+ 12 VIN Current
1+12VIN(1)
Sl = S4 =
I+12VIN(2)
Sl = S4
VLCurrent
GND,~
=VL,~
10
= S3= VL
= S3 = GND
10
IVL(l)
Sl = S4 = GND, S2 = S3 = VL
10
IVL(2)
Sl =S4 =VL'~ = S3 =GND
10
I1A
Switch Control Inputs
Input Voltage High
VJ(lI)
Input Voltage Low
Input Hysteresisb
VJ(L)
VJ(lI)-VJ(L)
Input Current High
IJ(lI)
IInput Current Low
VL = 3.3 V
2.8
2.4
VL=5V
4.0
3.3
VL= 3.3V
1.1
0.4
VL=5V
1.5
0.8
VL= 3.3 V
0.5
1.3
VL=5V
0.8
1.8
1.0
Sl through S4 = VL, VL = 5 V
-
Sl through S4 - GND, VL -- 5 V
i
-1.U
i
V
I1A
Notes
a. The algehraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. Guaranteed by design, not subject to production testing.
Timing Waveforms
Sx
Sx
GND
GND
GND
GND
Figure 2.
Figure 1.
3-70
Preliminary
P-34980-Rev. B (05/09/94)
TEMIC
Si9710CY
Siliconix
Pin Configuration
SOIC-16
S3
S2
S4
Sl
GND
VL
Vpp
+12VIN
Vpp
Vee
Vee
+ 5VlN
Vee
+3.3VlN
Vee
+3.3VlN
Top View
Order Number Si9710CY
Pin Description
Pin Number
Symbol
1
S3
2
S4
3
GND
Description
Control input for selecting +5 VlN to Vee. The PCMCIAterminology for this pin is Vee_ENl'
Control input for selecting +3.3 VlN to Vee. The PCMCIA terminology for this pin is Vee_END.
Ground connection.
4,5
Vpp
Program and peripheral voltage to PCMCIA slot.
6,7,8,12
Vee
Supply voltage to slot.
9,10
+3.3 VlN
11
+5VIN
13
+12 VlN
14
VL
Rail voltag\, for switch control inputs, selectable to 5-V or 3.3-V.
15
Sl
Control input for selecting +12 VIN to Vpp. The PCMCIA terminology for this pin is Vpp_ENl'
16
S2
Control input for selecting Vee to Vpp. The PCMCIA terminology for this pin is Vpp_END.
P-34980-Rev. B (05/09/94)
+ 3.3-V supply.
+5-V supply.
+ 12-V supply.
Preliminary
3-71
TEMIC
Si9711CY
Siliconix
PCMCIA Interface Switch
Features
• Reverse Blocking Switches
• Hi-Z Outputs in the Off-State
• Single SO-16 Package
• CMOS Inputs with Hysteresis
• Extremely Low RoN
• Low Power Consumption
• Safe Power -Up
Description
The Si9711CY is a monolithic switch designed to meet
the needs of the PCMCIA interface. The inputs are fully
CMOS compatible and incorporate all the level shift and
interface required to be driven by any CMOS driver. The
external inputs can be driven to 3.3-V or S-V by setting
VL at the appropriate level. The switches are low RON
and can carry the maximum currents found on the
PCMCIA interface.
The S-V and 3.3-V switches do not have the parasitic
diode found in vertical DMOS power switches.
Low RON is achieved by using MOSFETs driven off the
+12-VIN input. All level shifting is built into the
Si9711CY.
The Si9711CY is packaged in an SO-16 package and is
rated over the commercial temperature range 0 to 70°C.
Functional Block Diagram
+12 VIN
(13)
(11)
+3.3 VIN
+3.3VIN
(9)
(10)
I
Sl
I
I
I
I
3-72
S3
I
I
I
I
I
I
I
I
(14)
I
:
(4)
n·
I
I
(15)
Level Shift
(16)
Drivers
and
(6)
(7)
S4
:I
I
:
:
(5)
(8)
II
(12)
I
:
Vpp
Vpp
Vee
Vee
Vee
Vee
1l:uth Table - Sl through S4
Logk
Switch
0
OFF
1
ON
(2)
(1)
(3)
Preliminary
P-37016-Rev. B (06/01/94)
TEMIC
Si9711CY
Siliconix
Absolute Maximum Ratings
Voltages Referenced to Ground
Vpp ................................................ 15 V
VL .................................................. 7V
All Pms ............................................ -0.5 V
+12VIN ............................................. 15V
lOUT Vee ........................................... 1.5 A
+5VIN···············································7V
+3.3VIN ............................................. 7V
I'D Max: (TA = 25'C) ............................. 710 mW
(TA = 70'C) ............................. 390 mW
SI through S4 (CMOS Inputs) ...................... VL + 0.5 V
Junction Thmperature ................................. 125'C
lOUT Vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 300 rnA
Thermal Ratings
RSJA ........................................... 140 'CIW
Vee ................................................ 7V
Recommended Operating Conditions
+12VIN ...................................... 12V± 10%
IOUTVee ............................................ lA
+5VIN ........................................ 5V± 10%
lOUT Vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 150 rnA
+3.3 VIN ..................................... 3.3 V ± 10%
VL ........................................... 5.0V ± 10%
Specifications
Test Conditions
Unless Otherwise Specified
Parameter
Switch
Symbol
+5 VIN = 5 V, +3.3 VIN = 3.3 V
+12 VIN = 12 V, VL = 5.0 V, GND = OV
Limits
C Sufftx, 0 to 70'C
Min"
1YP
Max"
Unit
1
On-Resistance
RON
1= 120 rnA, +12 VIN = 10.8 V
SI =VL,S2 = GND
Off Current (+12 VIN to Vpp)
IOFF
+12 VIN = 13.2 V, Vpp = OV
SI =GND
Switching TIme
tSI(on)
tSI(o[!)
TA=25'C
200
TA =70'C
250
TA- 25'C
1
TA-70'C
10
CL = 0.1J.lF, S2 = Low, RL = 100 Q, See Figure 1
0.1
1
0.5
4
mQ
"A
'"
Switch:!
TA=25'C
RON
1= 120 rnA, +12 VIN = 10.8 V
S2 = S3 =VL
300
On-Resistance
TA=70'C
350
Off Current
Vpp = 13.2 V, Vee = OV
+12 VIN = 13.2 V
TA=25'C
1
IOFF
TA=70'C
10
Switching TIme
tS2(on)
tS2(of!)
CL = 0.1 "F, RL = 100 Q, SI = S4 = GND,
S3 = VL, See Figure 1
0.1
1
0.5
4
mQ
!1A
'"
Switch 3
On-Resistance
RON
1= 500 rnA, +12 VIN = 10.8 V
S3=VL
Off Current
IOFF
+5VIN = 5.5 V, Vee = OV
TA-25'C
200
TA-70'C
250
TA=25'C
1
TA=70'C
10
!1A
4
'"
1
Id(on)
Switching TIme
tramp(on)
+5 VIN = 5 V, CL = 0.1 "F, Vee to GND
RL = 100 Q, Vee to GND, See Figure 2
200
0.5
tS3(of!)
P-37016-Rev. B (06/01/94)
mQ
Preliminary
3-73
TEMIC
Si9711CY
Siliconix
Specifications
Test Conditions
Unless Otherwise Specified
Parameter
Limits
C SuffIX, 0 to 70'C
+SVIN = S Y, +3.3 VIN = 3.3 V
+12 VIN = 12 Y, VL = S.OY, GND = OV
Symbol
1YP
Min'
Max'
Unit
Switch 4
On-Resistance
RON
Off Current
IOFF
I = SOO rnA, + 12 VIN = 10.8 V
S4=VL
TA = 2S'C
ISO
TA = 70'C
185
+3.3 VIN = 3.6 Y, Vee = 0 V
TA = 2S'C
1
Sz=~=S4=GND
TA=70'C
10
",A
1
td(on)
Switching TIme
mQ
+3.3 VIN = 3.3 Y, CL = 0.1",1\ S3 = GND
RL = 100 Q, See Figure 2
tramp(on)
200
0.5
tS4(off)
"'"
4
Power Supply
+ 12 VIN Current
I+12VIN(I)
SI = S4 = GND, S2 = S3= VL
10
I+12VIN(2)
SI - S4 - VL, S2 - S3 - GND
10
IVL(I)
SI = S4 - GND,S2 - S3 - VL
10
IVl.(2)
SI- S4 - VL,S2 - S3 - GND
10
VLCurrent
j.LA
Switch Control Inputs
Input Voltage High
VJ(H)
Input Voltage Low
VJ(L)
Input Hysteresisb
VJ(H)-VJ(L)
Input Current High
II(H)
I Input Current Low
Il(L)
I
VL = 3.3 V
2.8
2.4
VL=5V
4.0
3.3
VL-3.3V
1.1
0.4
VL=5V
1.5
0.8
VL=3.3V
0.5
1.3
VL=5V
0.8
1.8
SI through S4 - VL, VL - 5 V
Sl
I
throug..~
V
1.0
Sot - GND. v L - 5 V
I
1.0
I
I
j.LA
I
I
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. Guaranteed by design, not subject to production testing.
Timing Waveforms
vPP:rL
RL
~
CL
S3 orS4
/
GND
/
SO%
50%
90%
GND
10%
/
50% \ \ .
'------
Vee
90%
,\0%
-=~-I--~
-tsx(off)
-
-tSX(off)
Id(on) -
Figure 1. t,t(on) and tSX(on)
3-74
tramp(on)
Figure 2. tramp(on)
Preliminary
P-37016-Rev. B (06/01/94)
TEMIC
Si9711CY
Siliconix
Pin Configuration
80-16
S3
S2
S4
SI
GND
VL
vpp
+12VIN
Vpp
Vee
Vee
+5VIN
Vee
+3.3 VIN
Vee
+3.3 VIN
Top View
Order Number: Si9711CY
Pin Description
Pin Number
Symbol
1
S3
2
S4
3
GND
Description
Control input for selecting +5 VIN to Vee. The PCMCIA terminology for this pin is Vee_EN1.
Control mput for selecting + 3.3 VIN to Vee. The PCMCIA terminology for this pin is Vee_ENo.
Ground connection.
4,5
Vpp
Program and peripheral voltage to PCMCIA slot.
6,7,8,12
Vee
Supply voltage to slot.
9,10
+3.3 VIN
11
+5VIN
+5-Vsupply.
13
+12 VIN
+ 12-V supply.
14
VL
Rail voltage for switch control inputs, selectable to 5-V or 3.3-y'
15
SI
Control input for selectmg +12 VIN to Vpp. The PCMCIA terminology for this pin is Vpp_EN1'
16
S2
Control input for selecting Vee to Vpp. The PCMCIA terminology for this pin is Vpp_ENo.
P-37016-Rev. B (06/01/94)
+3.3-V supply.
Preliminary
3-75
TEMIC
Si9717CY
Siliconix
Battery Disconnect Switch
Features
•
•
•
•
•
6- to 18-V Operation
Separate Logic Voltage Input
Undervoltage Lockout (UVL) @ VL = 3 V
Shutdown Control Capability
Safe Power Down
Description
The Si9717CY is a reverse blocking switch for battery
disconnect applications. It is an integrated solution for
multiple battery technology designs or designs that
require isolation from the power bus during charging.
The Si9717CY is available in a 16-pin SOIC package and
is rated for the commercial temperature range of 0 to
70·C.
Functional Block Diagram
CBP
CP
7
A
10
6 ru;;de;I
ENABLE o--::-j Voltage
111
h
Detect
I
G~ ~j. I
=-Ol---+-_...J
Absolute Maximum Ratings
Voltage Referenced to GND
VA,VB ....................................... -0.3t020V
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 to 10 V
Storage'Thmperature . . . . . . . . . . . . . . . . . . . . . . . . . .. -65 to 12S·C
Power Dissipation ...................................... 2 W
VENABLE. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . .. -0.3 to 10 V
Notes: Device mounted with all leads soldered to PC board.
Recommended Operating Range
VA, VB (see note) ................................. 6to 18 V
VIN .............................................. OtoSV
lAB (continuous) ......... . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 4 A
lAB x VA (continuous) .............................. Ot040W
Minimum Cycle Time (turn-on to turn-on) ................ 10 ms
VENABLE. .. . . .. . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . .. 0 to 5 V
3-76
Operating Thmperature ............................ 0 to 70·C
Junction Thmperature ............................. 0 to IS0·C
Notes:
a. Si9717CY is functional at VA, VB = Sto 6 V with higher supply
current. See lA(on) specification.
Advance Information
(06/07/94)
TEMIC
Si9717CY
Siliconix
Specifications
Test Conditions
Unless Otherwise Specified
Parameter
6V;;; VA;;; 18V
CVDD = 0.1 fll'; CP = 0.02 "F
Temp'
RAB
VA = 10 V, IA = 1 A
Room
0.06
g
IAB(ofl)
VA=16V,VB=OV
Room
10
flA
Symbol
On-Resistance
Leakage Current
Limits d
IN Low Threshold
VIN(L)
Full
IN High Threshold
VIN(H)
Full
Minb
lYPc
Maxb
1
4.0
IN Input Current
IIN(H)
VIN= 5.0V
Full
1
Thrn-On Delay IN to A or B
tON(IN)
Full
10
Thrn-Off Delay IN to A or B
tOFF(IN)
ENABLE = 5V,VA=10V,RL=5g
'lest Circuit 1
Full
10
VENABLE(L)
Full
3.0
VENABLE(H)
Full
ENABLE Low Threshold
ENABLE High Threshold
ENABLE Input Current
IENABLE(H)
Setup Time
from ENABLE to Switch
On-State Drain
IA(on)
Off-State Drain
IA(ofl)
V
flA
fl S
V
4.4
VENABLE-5V
Full
50
VA - 10 V, VIN - 0 V, Test Circuit 2
Room
2.0
VA - 6 V, VIN - 0 V, 'lest Circuit 2
Full
10
AB Shorted, VA - 10 V, VENABLE = 5 V
Full
60
AB Shorted, VA - 5 V, VENABLE - 5 V
Full
300
AB Shorted, VA - 10 V, VENABLE - 0 V
Full
10
tENABLE(H)
Unit
flA
ms
flA
Notes:
a. Room = 25°C, Full = as determined by the operating temperature suffIX.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. 1)Ipical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Thsted at room temperature, high temperature guaranteed by statistical data correlation techniques.
Test Circuit
10V
B
tON(IN)
Test Circuit 1
tOFF(IN)
A
5V~
5V
1--.,...oCP
B
10
g
r
VENABLE 50%
OV
O02flF
.
I
I
I
I
Vcp - - - - !
Test Circuit Z
(06/07/94)
Advance Information
3-77
TEMIC
Si9717CY
Siliconix
Pin Configuration and 1hIth Table
80-16
ENABLE
IN
SwItch Controner State
SwItch
0
0
Inactive
X
A
B
0
1
Inactive
X
A
B
1
0
Set-Up
Off
A
B
1
1
Active
On
GND
GND
A
B
ENABLE
IN
CBP
CP
GND
GND
ThpView
Order Number: Si9717CY
Pin Description
Pin NUDlber
Symbol
1,8,9,16
GND
2,3,4,5
A
6
ENABLE
Description
Common connection for negative battery terminals_
A-terminal of the battery switch, bidirectional.
Logic input, ENABLE. Activates charge pump and switch drive logic.
7
CBP
10
CP
Charge pump output terminal. Requires external capacitor connected to pin 9.
11
IN
Logic input, IN. A high level turns on the switch.
12,13,14,15
B
B-terminal of the battery switch, bidirectional.
Internally generated logic power supply, Voo. Requires external bypass capacitor connected to pin 8.
Applications Diagram
80-16
GND
GND
A
Battery-E
~
A
B
Si9717CY
Th dc/de
B
IN (From Battery Controller)
Logic (Voo) - - ENABLE
lOOnF
:3--
~
CP ~ 20nF
GND---'
CBP
' - - GND
ThpView
3-78
Advance Information
(06/07/9 4)
.qt(7Z Z-
TEMIC
Si9718CY
Siliconix
Battery Disconnect Switch
Features
•
•
•
•
•
6- to 18-V Operation
Separate Logic Voltage Input
Undervoltage Lockout (UVL) @ VL = 3 V
Shutdown Control Capability
Safe Power Down
Description
The Si9718CY is a reverse blocking switch for battery
disconnect applications. It is an integrated solution for
multiple battery technology designs or designs that
require isolation from the power bus during charging.
The Si9718CY is available in a 16-pin SOICpackage and
is rated for the commercial temperature range of 0 to
70°C.
Functional Block Diagram
3
CBP
CP
o-~7--------------------~--------------------------~~~-4r-----~~A
10
ENABLE
'---;.e-+--t--r''-<>B
IN
GND
8
16
Absolute Maximum Ratings
Voltage Referenced to GND
VA. VB ....................................... -0.3 to 20V
VIN .......................................... -0.3tol0V
Storage Thmperature ........................... -65 to 12S'C
Power Dissipation ...................................... 2 W
VENABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 to 10 V
Notes: Device mounted with all leads soldered to PC board.
Recommended Operating Range
VA. VB (See note a) ................................ 6 to 18 V
VIN .............................................. Ot05V
lAB (continuous) .................................. 0 to 3.5 A
lAB x VA (continuous) .............................. 0 to 35 W
Minimum Cycle Time (turn-on to turn-on) ....•........... 10 ms
VENABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 5 V
P-36849-Rev. C (06/06/94)
Operating Temperature ............................ 0 to 70'C
Junction Thmperature ............................. 0 to 150'C
Notes:
a. Si9718CY is functional at VA. VB = 5 to 6 V with higher supply
current. See IA(on) specifIcation.
Preliminary
3-79
TEMIC
Si9718CY
Siliconix
Specifications
Test Conditions
Unless Otherwise Specified
Parameter
6V ~ VA ~ 18V
CVDD = 0.1 ~F, CP = 0.02 ~F
Temp"
RAB
VA = 10V,IA = 1A
Room
0.08
Q
IAB(off)
VA = 16 V, VB = OV
Room
10
~
Symbol
On-Resistance
Leakage Current
Limitsd
IN Low Threshold
VIN(L)
Full
IN High Threshold
VIN(H)
Full
Minb
lYPc
Maxb
1
V
4.0
IN Input Current
IIN(H)
VIN=S.OV
Full
1
11Irn-On Delay IN to A or B
tON(IN)
ENABLE = Sv, VA = 10'1, RL = 5 Q
Thst Circuit 1
Full
10
111m-Off Delay IN to A or B
Full
10
ENABLE Low Threshold
VENABLE(L)
Full
3.0
ENABLE High Threshold
VENABLE(H)
Full
ENABLE Input Current
IENABLE(H)
Setup TIme
from ENABLE to Switch
toFF(IN)
tENABLE(H)
On-State Drain
lA(on)
Off-State Drain
IA(olf)
Unit
~A
"'"
V
4.4
VENABLE-SV
Full
SO
VA - 10 V, VIN - 0 V, Test Circuit 2
Room
2.0
VA = 6 V, VIN - 0 V, Thst Circuit 2
Full
10
AB Shorted, VA = 10 V, VENABLE - 5 V
Full
60
AB Shorted, VA - 5 V, VENABLE - 5 V
Full
300
AB Shorted, VA - 10 V, VENABLE - 0 V
Full
10
~A
ms
~
Notes:
a. Room = 2S'C, Full = as determined by the operating temperature suffIX.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. 'tYpical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Thsted at room temperature, high temperature guaranteed by statistical data correlation techniques.
Test Circuit
10V
B
tON(IN)
Test Circuit 1
tOFF(IN)
A
SV
SV
1--.,....oCP
-11--.--0
OUTx
Note: lest repeated for inverting input.
Figure 1.
P-36736-Rev. D (05130194)
Switching Time Test Circuit
4-3
TEMIC
D469A
Siliconix
lYPical Characteristics
Supply Current vs. Thmperature
20
16
12
j
8
35
11 I~putsl= 3 ~
r-.. .......
......
---
~
I
I
I
-
Vnn = 15V
l"- I'-
I
\
-45 -35 -15 0
./
l/
15 30 45
60 75
./'
20
j
15
5
o
90 105120
o
...... f-" l -I-- i--"
-
I--"
I-
l/
V"
"""- VAIl Channels Switching _ -
",..
./
10
JVnn = 15V -
Vnn= 12V
o
I
25
All Inputs = GND
4
I
Vnn = 15V
30 f- f= 100kHz
""'" r--.
-~ ....
Vnn=12V
r-.. ....
~
Supply Current vs. Capacitive Load
I
One Channel Switching
I
I
I
2000
1000
'Thmperature ('C)
I
3000
I
4000
5000
Capacitive Load (pF)
Switching Threshold vs. Supply Voltage
3.0
1000
2.5
100
2.0
E
j
~
10
1.5
."..-
1.0
-
.---l..--""
~
0.5
0.0
6
10
8
Switching Frequency (Hz)
Switching Time vs. Capacitive Load
60
Vnn = 12V
VIN = Ot03 V
One Channel Switching
55
~
"e
laFF.......
50
~
40
35
30
25
~
l/ l/
I;:V
1/
;.0'"
o
1000
75
~
~
~
f~
16
5000
/
/
50
45
40
25
4000
I
I
VIN = Ot03V
One Channel Switching -
55
30
3000
I
60
35
2000
Vn~ = i5V '
70
65
~
Capacitive Load (pF)
4-4
~
... V V
OIl
14
Switching Time vs. Capacitive Load
)~ V;ON
45
!==
~
I
12
Vnn(V)
,;
o
/
/ ."
/.. .,1000
2000
t ON/
/
/
tOFF
,. .,3000
,"-
4000
5000
Capacitive Load (pF)
P-36736-Rev. D (05/30/94)
TEMIC
Si9910
Siliconix
Adaptive Power MOSFET Driver!
Features
• dv/dt and di/dt Control
• U ndervoltage Protection
• Short-CircUIt Protection
• trr Shoot-Tbrough Current Limiting
• Low Quiescent Current
• CMOS Compatible Inputs
• Compatible with Wide Range of MOSFET Devices
• Bootstrap and Charge Pump Compatible
(High-Side Drive)
Description
The Si9910 Power MOSFET driver provides optimized
gate drive signals, protection circuitry and logic level
interface. Very low quiescent current is provided by a
CMOS buffer and a high-current emitter-follower
output stage. This efficiency allows operation in
high-voltage bridge applications with "bootstrap" or
"charge-pump" floating power supply techniques.
Fault protection circuitry senses an undervoltage or
output short-circuit condition and disables the power
MOSFET. Addition of one external resistor limits
maximum di/dt of the external Power MOSFEf. A fast
feedback circuit may be used to limit shoot-through
current during trr (diode reverse recovery time) in a
bridge configuration.
The non-inverting output configuration minimizes
current drain for an n-channel "on" state. The logic
input is internally diode clamped to allow simple
pull-down in high-side drives.
The Si9910 is available in 8-pin plastic DIP and SOIC
packages, and are specified over the industrial, D suffix
(-40 to 85°C) temperature range.
Functional Block Diagram
R3
VDS~-------------------------------------------------Jv\Ar-------4
*l00kn
VDD
~~~~r---+-------~----------------.
DRAIN
Cl
PULL-UP
R2
*2to5pF
*2500
PULL-DOWN
INPUT ~~~~~-----------t---I
ISENSE
Vss
*1Ypical Values
1. Patent Number 484116.
P-34829-Rev. E (04/18/94)
4-5
TEMIC
Si9910
Siliconix
Absolute Maximum Ratings
Voltages Referenced to V ss Pin
VDD Supply Range ........................... -0.3 V to 18 V
Pin 1,4, 5, 7, 8 ........................ -0.3 Vto VDD + 0.3 V
Pin 2 ................................ -0.7 V to VDD + 0.3 V
Input Current .................................... ± 20 rnA
Peak Current (Ipk) ...................................... 1 A
Storage 1emperature . . . . . . . . . . . . . . . . . . . . . . . . . .. -65 to 150'C
Operating Thmperature ......................... -40 to 85'C
Junction Thmperature (TJ) . . . . . . . . . . . . . . . . . . . . . .. . .... 150'C
Power Dissipation (Package)"
8-Pin sorc (Y SufflX)b .............................. 700 mW
8-Pin Plastic DIP (1 Suffix)b .......................... 700 mW
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 5.6 mWI'C above 25'C.
Specifications a
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
VDD 10.8 V to 16.5 V
TA = OperatingThmperature Range
Limits
Minc
Maxc
Unit
6.0
0.35xVDD
V
2.0
3.0
'JYpb
Input
High Level Input Voltage
Vm
Low Level Input Voltage
VIL
Input Voltage Hysteresis
Vh
High Level Input Current
1m
VIN = VDD
±1
Low Level Input Current
IlL
VIN=OV
±1
High Level Output Voltage
VOH
IOH = -200 rnA
Low Level Output Voltage
VOL
IOL= 200 rnA
0.70XVDD
0.90
7.4
J1A.
Output
VDD-3
10.7
1.3
3
8.3
9.2
10.6
Max Is = 2 rnA, Input High
100 mV Change on Drain
0.5
0.66
08
Input High
8.3
9.1
10.2
12
20.0
Undervoltage Lockout
Vuvw
ISENSE Pin Threshold
Vm
Voltage Drain-Source Maximum
VDS
Input Current for VDS Input
IVDS
Peak Output Source Current
Ios+
1
Peak Output Sink Current
Ios-
-1
V
J1A.
A
Supply
Supply Range
Supply Current
10.8
VDD
16.5
IDDl
Output High, No Load
0.1
1
IDD2
Output Low, No Load
100
500
V
J1A.
Dynamic
Propagation Delay TIme Low to High Level
tpLH
120
Propagation Delay TIme High to Low Level
tpHL
135
Rise TIme
Fall TIme
t,
CL= 2000pF
tl
50
ns
35
Overcurrent Sense Delay (VDS)
tDS
1
!-,S
Input Capacitance
Cm
5
pF
Notes
a. Refer to PROCESS OPTION FLOWCHAIIT for additional information.
b. 'iYPicaI values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c.
The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
4-6
P-34829-Rev. E (04/18194)
TEMIC
Si9910
Siliconix
AC Testing Conditions
VDD
'-......,.-------- VSS
IN _ _ 2.o~
(IN
~
L)
VOH
OUT
VOL
Pin Configurations
PDIP·8
SO·8
VDSOs
2
7
INPUT
VDD
DRAIN
PULL-UP
Pull-DOWN
VDS
INPUT
VDD
DRAIN
3
6
Vss
4
5
ISENSE
ThpView
Order Number:
SI9910DJ
0
2
7
3
6
4
5
PULL-UP
PULL-DOWN
Vss
ISENSE
ThpView
Order Number:
SI9910DY
Pin Description
Pin 1: VDS
Pin 1 or VDS is a sense input for the maximum
source·drain voltage limit. Two microseconds after a high
transition on input pin 2, an internal timer enables the
VDS(max) sense circuitry. A catastrophic overcurrent
condition, excessive
on-resistance, or insufficient
gate.drive voltage can be sensed by limiting the maximum
voltage drop across the power MOSFEf. An external
resistor (R3) is required to protect pin 1 from overvoltage
during the MOSFET "off" condition. Exceeding VDS(max)
latches the Si9910 "off." Drive is re-enabled on the next
positive· going input on pin 2. If pin 1 is not used, it must
be connected to pin 6 (Vss).
Pin 2: INPUT
A non-inverting, Schmidt trigger input controls the state
of the MOSFET gate·drive outputs and enables the
protection logic. When the input is low (:5 VIL), VDD
is monitored for an undervoJtage condition
(insufficiently charged bootstrap capacitor). If an
P-34829-Rev. E (04/18/94)
undervoltage (:5 VDD(min» condition exists, the driver
will ignore a tum-on input signal. An undervoltage
(:5 VDD(min» condition during an "on" state will not be
sensed.
Pin3: VDn
VDD supplies power for the driver's internal circuitry
and charging current for the power MOSFET's gate
capacitance. The Si9910 minimizes the internal IDD in
the "on" state (gate-drive outputs high) allowing a
"floating" pow~r supply to be provided by charge pump
or bootstrap techniques.
Pin4: DRAIN
Drain is an analog input to the internal dv/dt limiting
circuitry. An external capacitor (Cl) must be used to
protect the input from exposure to the high.voltage
("off" state) drain and to set the power MOSFET's
maximum rate of dv/dt. If dv/dt feedback is not used,
pin 4 must be left open.
4·7
TEMIC
Si9910
Siliconix
Pin Description (Cont'd)
Pin 5: ISENSE
ISENSE in combination with an external resistor
(Rl) protects the power MOSFET from potentially
catastrophic peak currents. ISENSE is an analog
feedback that limits current during the power
MOSFET's transition to an "on" state. It is intended to
protect power MOSFETh (in a half-bridge arrangement)
from "shoot-through" current, resulting from excess
di/dt and trr of flyback diodes or from logic timing
overlap. An 0.8-V drop across (R1) should indicate
a current level that is approximately four times the
maximum allowable load current. When the ISENSE
input is not used, it should be tied to pin 6 (Vss).
Pin 6: Vss
Vss is the driver's ground return pin. The applications
diagram illustrates the connection of Vss for
source-referenced "floating" applications (half-bridge,
high-side) and ground-referenced applications
(half-bridge, low-side).
Pin 7: PULL-DOWN
Pin 8: PULL-UP
Pull-up and pull-down outputs collectively provide the
power MOSFET gate with charging and discharging
currents. Thrn "on" or "off" di/dt can be limited by
adding resistance (R2) in series with the appropriate
output.
Applications
"Floating" High-Side Drive Applications
As demonstrated in Figure 1, the Si9910 is intended for
use as both a ground-referenced gate driver and as a
"high-side" or source-referenced gate driver in
half-bridge applications. Several features of the Si9910
permit its use in half-bridge high-side drive applications.
A simple and inexpensive method of isolating a floating
supply to power the Si9910 in high-side driver
applications had to be provided. Therefore, the Si9910
was desigued to be compatible with two of the most
commonly used floating supply techniques:
the
bootstrap and the charge pump. Both of these
techniques have limitations when used alone. A
properly designed bootstrap circuit can provide
low-impedance drive which minimizes transition losses
and the charge pump circuit provides static operation.
The Si9910 is configured to take advantage of either
floating supply technique if the application is not
sensitive to their particular limitations, or both
techniques if switching losses must be minimized and
static operation is necessary. The schematic above
illustrates both the charge pump and bootstrap circuits
used in conjunction with an Si9910 in a high-side driver
application.
Input signal level shifting is accomplished with a passive
pull-up (R4) and the Siliconix VN50300 (500-V/300-Q)
4-8
MOSFET for pull-down in applications below 500 V.
Complete specifications for the VN50300 can be found
in the SiliconixLow-Power Discretes Data Book. One of
the VN50300's most important features in this
application is its extremely low Coso (output or drain)
capacitance. Coso (typically 5 pF), plus the Si991O's input
capacitance (also typically 5 pF) plus any stray board
capadt~n(".e. Total node capacitance defines the value of
R4 needed to guarantee an input transition rate which
safely exceeds the maximum dv/dt rate of the output
half-bridge. Another feature of the VN50300 is its
inherently low saturation current. Using level-shift
devices with higher current capabilities may necessitate
the addition of current-limiting components such as R5.
Bootstrap Undervoltage Lockout
When using a bootstrap capacitor as a high-side floating
supply, care must be taken to ensure time is available to
recharge the bootstrap capacitor prior to turn-on of the
high-side MOSFET. As a catastrophic protection against
abnormal conditions such as start-up, loss of power, etc.,
an internal voltage monitor has been included which
monitors the bootstrap voltage when the Si9910 is in the
low state. The Si9910 will not respond to a high input
signal until the voltage on the bootstrap capacitor is
sufficient to fully enhance the power MOSFET gate. For
more details, please refer to Application Note AN705.
P-34829-Rev. E (04/18/94)
TEMIC
Si9910
Siliconix
Applications (Cont'd)
Vnn (12 to 15 V)
Vnn
Vns
R3
DRAIN
Cl
PULL-UP
R2
D1
R4
PULL-DOWN
01
INP'UI'Q---II-f-t----H
ISENSE
Rl
Vnn
Vns
R3'
DRAIN
Cl'
PULL-UP
R2'
VN50300
rC'Mos'
02
~
I
I
4C4
I
I
I
I
I
I
R5
-;:-
PULL-DOWN
INPUT
ISENSE
VSS
C2 = Bootstrap Cap
C3 = Chargepump Cap
Figure 1.
P-34829-Rev E (04/18/94)
High-Voltage Half-Bridge with Si9910 Drivers
4-9
TEMIC
Si9961
Siliconix
12-V Voice Coil Motor Driver
Features
• 1.8-AH-Bridge Output
• Qass B Linear Operation
• Externally Programmable Gain and
Bandwidth
•
•
•
•
• Single 12-V Supply
• System Voltage Monitor with Fault
Output
Undervoltage Head Retract
Programmable Retract Current
Low Standby Current
Rail-to-Rail Output Swing
Description
The Si9961 is a linear actuator (voice coil motor) driver
suitable for use in disk drive head positioning systems.
The Si9961 contains all of the power and control circuitry
necessary to drive the VCM that is typically found in
3Y2-inch hard disk drives and optical disk drives. The
driver is capable of delivering 1.8 A at a nominal supply
of 12 V.
cross-conducting current and true Qass B operation during
linear tracking. Externally programmable gain switch at
the input sunmting junction increases the resolution and
dynamic range for a given DAC. The head retract circuitry
can be activated by either an undervoltage condition or an
external command. An external resistor is required to set
the VCM current during retract.
The Si9961 provides all necessary functions including a
motor current sense amplifier, a loop compensation
amplifier and a power amplifier featuring four
complementary MOSFEfs in a H-bridge configuration.
The output crossover protection ensures no
The Si9961 is constructed on a self-isolated BiC/DMOS
power IC process. The IC is available in 24-pin SO
package for operation over the commercial, C suffix (0
to 70°C) temperature range.
Functional Block Diagram
+-__~__-r-o°UTPUT
~VV~__________~__~________
A
I
~__-r~~1~900UTPUT
B
04
RE1RACT
i~T~6~~--------~----~
ENABLE
11
OA2 ~~r---------~----~
GAIN
SELECT
I
I
I
I L-p--....,...~-o---,
I
o1Q.l_
I
_ _ _ _ ..I
L_
4-10
iSENSE
OUT
20
21
3
RFB
iSENSE iSENSE SA
IN+
GND
SB
INP-35253-Rev. C (06/06/94)
TEMIC
Si9961
Siliconix
Absolute Maximum Ratings
Voltages Referenced to Common Pm
Operatmg Temperature ............................ 0 to 70'C
V + Supply Range .......... ............ .... -0.3 V to 16 V
Junction Temperature (TJ) ............................. 150'C
Pm (FAULl) .......................... -0.3 V to Vee + 0.3 V
Power Dissipation (Package)"
24-Pin SOlCb . . . . . . . . . . . . . . . . . . . . . . .. . ............ 3.125 W
Pin (Output A & B, Source A & B) ....... -0.3 V to VDD + 0.3 V
Pin (All Others) ....................... -0.3 V to V+ + 0.3 V
Maximum Clamp Current
Output A, Output B (Pulsed 10 ms at 10% duty cycle) ..... ± 1.8 A
Pin (All Others) .................................. ± 20 rnA
Storage Thmperaturc .......................... -65 to 150'C
Thermal Impedance (ElJA)"
24-Pin SOlC ...................................... 40'C/W
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 25 mWrCabove 25'C.
Specifications
Test Conditions
Unless Otherwise Specified
Parameter
Limits
C Suff", 0 to 70'C
Symbol
V+ = 12 V ±10%, VDD = 11.6 V ±1O%
Vee = 5V ±10%, VREF- = GND = OV
VREF = 5V ±5%
Min b
VOH
IOH = 1.0 A, VDD = 10.2 V, OAz= VREF ± 1 V
8.0
'!yp"
Maxb
Unit
1.1
V
Bridge Outpnts (AI, As)
High Level Output Voltage
Low Level Output Voltage
VOL
IOL = -1.0 A, OAz = VREF ± 1 V
Clamp Diode Voltage
VCL
IF = 1.0 A, ENABLE = High
Amplifier Gain
Output VRANGE = VREF ±2 V
Dynamic Crossover Current
Slew Rate
2.5
12
16
18
10
Measured at VDD
SR
9.1
0.6
rnA
V/~S
1
Small Signal BandWIdth (-3 dB)
0.2
-60
Input Deadband
VN
MHz
60
mV
-8
8
mV
-50
50
Al, Loop Compensation Amplifier
Input Offset Voltage
Input Bias Current
Vos
IB
RLOAD = 10 ~ CLOAD = 100 pF to VREF
Unity Gain Bandwidth
Slew Rate
SR
Power Supply Rejection Ratio
PSRR
Open Loop Voltage Gain
AVOL
Output Voltage Swing
Gain Select = High, IA2 =5V
Va
1
V/~
1
@10kHz
50
dB
80
RLOAD = 10 ill to VREF
nA
MHz
VREF
VREF
-2
+2
V
A3, Current Sense Amplifier
Input Offset Voltage
Vas
Input Impedance
RIN
Small Signal Bandwidth ( - 3 dB)
Common Mode Rejection Ratio
Slew Rate
Gain
P-35253-Rev. C (06/06/94)
CMRR
SR
-5
5
mV
lSENSEIN + to ISENSEIN-
5
ill
RLOAD = 10 ~ CLOAD = 100 pF to VREF
1
MHz
@5kHz
50
dB
V/~s
2
3.9
4
4.1
VN
4-11
TEMIC
Si9961
Siliconix
Specifications
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
Limits
C SuffIX 0 to 70·C
V+ ~ 12 V ±10%, Voo ~ 11.6 V ±10%
Vee ~ 5V ±10%, VREF- ~ GND ~ OV
VREF ~ 5V ±5%
Min b
ThGND
-0.3
2
VREF
-2
VREF
+2
1yP"
Maxb
Unit
A3, Current Sense Amplifier (Cont'd)
Input Common-Mode
Voltage Range
VCM
Output Voltage Swing
Vo
V
RWAD
~
10kQ,CwAD
~
loopFtoVREF
Supply
Supply Current (Normal)
Static, No Load
REfRACT - High
2
5
ENABLE~Low
5
13
100
Supply Current (Standby)
0.01
Ice
Iv+
Icc
Static, No Load
Iv+
RETRACf - High
100
ENABLE
~
0.01
0.2
High
Normal Mode
10.2
Retract Mode
2.0
rnA
0.4
0.8
1.6
11.6
13.2
VoORange
Voo
VccRange
Vee
45
5
55
V+ Range
V+
10.8
12
13.2
14
V
Gain Selett Switch
RFB Switch Resistance
RINH Switch Resistance
IAZ-
~
5V
RINL Switch Resistance
108
240
135
300
810
1300
Q
VRE'(EXT)
Input Current
lREF
External Voltage Range
VREF
OAZ~VREF
0.15
0.40
0.65
rnA
4.75
5
5.25
V
3.82
4.12
4.42
Power Supply Monitor
Vcc Undervolt.ge Threshold
VREF
~
5.0V
Hysteresis
40
VREF~5.0V
V+ Undervolt.ge Threshold
9.1
Hysteresis
9.8
V
mV
10.6
100
V
mV
Gain Selett, RETRACf, ENABLE Input
3.5
Input High Voltage
Vrn
Input Low Voltage
VIL
Input High Current
IIH
VIN
~5V
-1
1
Input Low Current
IlL
VIN
~OV
-1
1
4-12
1.5
V
!iA
P-35253-Rev. C (06/06/94)
TEMIC
Si9961
Siliconix
Specifications
Test Conditions
Unless Otherwise Specified
Limits
C SuffIX 0 to 70'C
Symbol
V+ = 12 V ±10%, VDD = 11.6 V ±10%
Vee = 5V ±1O%, VREF- = GND = OV
VREF=5V±5%
Minb
'IYl'"
VOH
IOH= -100 "A
Vee
-0.8
Vee
-0.33
Output Low Voltage
VOL
IOL= 1.6 rnA
0.25
0.50
Output High Sourcing Current
IOHS
VOlrr=OV
400
1100
Parameter
Maxb
Unit
FAULT Output
Output High Voltage
RETRACT Current Control (RETRACT = Low,
IRET Bias Voltage
Output Current from
0.66
VOUTA
VDD = 2 Vto 14 Y,IOUTA = 30 rnA
VDD
-1
Retract Output Pull-Down Current
Iourn
VDD = 10 Y, Vourn = 5 V RRET = 3.74 kQ
RSB = 0.5 g TA = 2S'C
22
Maximum Emergency
Retract Current
Iourn
(Max)
VDD = 2 Y, Vourn = 0.7VRRET = < 10C
RSB = 0.5 g
40
Retract Output Pull-Up Voltage
Retract Current VDD Supply
Rejection Ratio
Retract Current
Temperature Coefficient
"A
Ato B)
VDD = lOY, RRET = 3.74 kQ
V(IRET)
V
V
30
38
rnA
VDD = 2 V to 14 Y, RRET = 3.74 kQ
3.0
%N
VDD = 10 Y, RRET = 3.74 kQ
-0.3
%/"C
Notes
a. 1Jpical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
Pin Configurations
24-Pin sOle
RINH
RFB
RINL
IAZOAZ
ISENSEOUT
FAULT
ISENSE (IN)SOURCEB
Vee
OUTPUTB
IRET
VDD (Spindle Supply)
EXTVREF
V+
OUTPUT A
RETRACf
Order Number: Si9961ACY
GND
GAlNSELECf
SOURCE A
ENABLE
GND
ISENSE (IN) +
VREFThpView
P-35253-Rev. C (06/06/94)
4-13
TEMIC
Si9961
Siliconix
Applications
Introduction
Head Retract
The Si9961 Voice Coil Motor (VCM) driver integrates
the active feedback and drive components of a
head-positioning servo loop for high-performance
hard-disk applications. The Si9961 operates from a 12-V
(± 10%) power supply and delivers 1 A of steady-state
output current. This device is made possible by a power
IC process which combines bipolar, CMOS and
complimentary DMOS technologies. CMOS logic and
linear components minimize power consumption,
bipolar front-ends on critical amplifiers provide
necessary accuracy, and complimentary (p- and
n-channel) DMOS devices allow the transconductance
output amplifier to operate from ground to VDD. Two
user-programmable, current feedback/input voltage
ratios may be digitally selected to optimize gain for both
seek and track following modes, to maximize system
accuracy for a given DAC resolution. An undervoltage
lockout circuit monitors the V + supply and generates a
fault signal to trigger an orderly head-retract sequence
at a voltage level sufficient to allow the spindle motor's
back EMF-generated voltage to supply the necessary
head parking energy. Head retract can also be
commanded via a separate RETRACT input. VCM
current during retract can be user programmed with a
single external resistor. External components are limited
to R/C filter components for loop compensation and the
resistors that are required to program gain, retract
current, and the load current sense.
A low on the RETRACT input pin turns output devices
Q1 and Q4 on, and output devices Q2 and Q3 off.
Maximum VCM current can be set during head retract
by adding an external resistor between the IRET pin and
ground. Maximum retract current may be calculated as:
User-Programmable Gains
During linear operation, the transconductance
amplifiers' gains (input voltage at VIN vs. VCM current,
in Figure 1) are set by external resistors R3 -+ Rs, RSA,
and RSB and selected by gain input. After selecting a
value for RSA and RSB that will yield the desired VCM
currentlevel, the High and Low feedback gain ratios may
be determined by the following:
(GAIN SELECf Input = High)
~
(GAIN SELECf Input = Low)
=
Low Gain
= (:;)
Where Rs = RSA = RsB
Input offset current may then be calculated as:
los =
1
+ RIN)) VOSAl +
4Rs
( ((Rs RIN
Where RIN = R3 or ~
4-14
5 VIAS3)
0.66 V
175 x I ret = 175 x R ret
Head retract can be initiated automatically by an
undervoltage condition (either the 12-V or 5-V supplies
on the Si9961) by connecting the FAULT output to the
RETRACT input.
A high ENABLE input puts both driver outputs in a
high-impedance state. The ENABLE function can be
used to eliminate quiescent output current when power
is applied but the head has been parked, stiph as a sleep
mode. A sleep-mode power down sequence should be
preceded by a retract signal since a power failure during
this state may not provide adequate spindle-motor back
EMF to permit head retraction.
SERVO Loop Characterization
As a test vehicle, the circuit in Figure 2 was constructed,
compensated, and characterized. The VCM chosen to
sen'e as the load was characterized using an I-IP4192A
Impedance Analyzer as follows: 2.7 mH @ f = 1 kHz/
1.5 mH @ f = 10 kHz (Lm), and 54.9 g f = 1 kHz/90.4 g
@ f = 10 kHz (R m).
To compensate the system for a closed-loop bandwidth
of 10kHz:
CL = 21t :;BW
RL
(~) ~
High Gain
lOUT =
=
(Rm ;ARSA)
LM
CL (Rm +
Rs~ =
=
540 pF (Used 560 pF)
29.5 kg (Used 28.7 kg)
The Bode plot of the Si9961 closed-loop ac response is
shown in Figure 3. The test equipment used to generate
the data were the HP3330B Automatic Synthesizer and
the HP3570A Network Analyzer. The -3-dB
breakpoint is slightly below 10 kHz. Maximum peaking
is approximately 0.22 dB at 2 kHz. Over a typical
servo-system mechanical bandwidth range of
100-500 Hz the maximum phase shift is 1.5 degrees.
The 20 dB/decade roll off is smooth from 10 kHz to
100kHz.
P-3S2S3-Rev. C (06/06/94)
TEMIC
Si9961
Siliconix
Applications (Cont'd)
12V
System
Supply
,..--------------,.----< Back EMF Supply
.----< 5-V Ref
>----------,-1.........
EXT
V+ 8
VREF
r-----------
7
VREF- 12
----
VDD 18
------
+~--~4~1~~~--_f~::~
p~
5
221
I
I
I
I L--.,---,-Jli--o---,
I
GAIN
tol
SELEcT r<>-r - -
p>==--J
i
ISENSE
I
RFB
2
R3
R4
OlIT
ISENSE lSENSE
IN+
A
IN13
24
21
20
R5
RSA
Figure 1.
Si9961 Typical Application
The motor's transient response to a SOO-mV (VREF
±2S0mV) input step is shown in Figure 4 (trace 1).
Figure 4, trace 2 shows the output voltage of buffer
amplifier A3, which represents the differential output
current. Output current peaking is less than 12% of the
total step amplitude and settling time is less than 250 IlS.
The linearity of the transconductance amplifier (around
a center value of 500 mA,lvolt) is shown in Figure 5. In
P-3S2S3-Rev. C (06/06/94)
RSB
this case, the output current sense resistors (RSA and
RSB) were ±S% tolerance, 0.5 Q Any mismatch
between RSA and RSB contribute directly to mismatch
between the positive and negative "full-scale". Including
the external resistor mismatch, the overall loop
nonlinearity is approximately 1% maximum over a
± 2S0-mV input voltage range.
4-15
TEMIC
Si9961
Siliconix
Applications (Cont'd)
~F
0.56
CL
8R
~__~____~OUT
10k
VCM
2.7mH@lkHz
(1.5 mH @ 10 kHz)
54.90@lkHz
(90.4 0 @ 10 kHz)
Gain =
Vs
::is..
VIN
RS
10kQ
0----+---+-<
~~~-------------------4
-=-
RSA
RSB
0.50
0.50
Figure 2. Transconductance Amplifier
2
o
......
-2
-4
!ll
.s
-6
'"
10
I
I
o
-10
Gain
-20
\
-30 ~
-40 :::0
hase Shi t
.~ -8
I I
I I
~-1O
s·
Figure 3.
CH2
-50 ~
......
~;Jtfmr 11111111111 ~~
100
CHl
VIN@lkHz
i
1k
10k
Frequency in HZ
VSENSE
2oomV/Dlv.
i
100 !1S/Div.
lOOk
Bode Plot of Si9961 Current Gain
"
~
~
Figure 4.
Motor Transient Response
3
2
"0
"il 0
@
r--- ...........
~
~ -1 r-VDD = 12V
.s -2 RSA = RSB = 0.5 0 ±5%
r-Rm =520
-3
Gm 5oo
~
-4
r-
i ll
-5
-300 -200 -100
0
100
VIN in mV
200
300
Figure S. Si9961 'fransconductance End Point Non-Linearity
4-16
P-35253-Rev. C (06/06/94)
TEMIC
Si9976DY
Siliconix
N-Channel Half-Bridge Driver
Features
Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single Input for High-Side and Low-Side MOSFETs
20- to 40-V Supply
Static (dc) Operation
Cross-Conduction Protected
Undervoltage Lockout
ESD and Short Circuit Protected
Fault Feedback
Power Supplies
Motor Drives
Office Automation
Computer Peripherals
Industrial Controllers
Robotics
Medical Equipment
Description
The Si9976DY is an integrated driver for an n-channel
MOSFET half-bridge_ Schmitt trigger inputs provide
logic signal compatibility and hysteresis for increased
noise immunity_ An internal low-voltage regulator
allows the device to be powered directly from a system
supply of20 to 40 volts_ Both half-bridge n-channel gates
are driven directly with low-impedance outputs.
Addition of one external capacitor allows an internal
circuit to level shift both the power supply and logic
signal for the half-bridge high-side n-channel gate drive.
An internal charge pump replaces leakage current lost in
the high-side driver circuit to provide "static" (dc)
operation in any output condition. Protection features
include an undervoltage lockout, cross-conduction
prevention logic, and a short circuit monitor. The
Si9976DY is available in the 14-pin sOle (surface
mount) package, specified to operate over the industrial
(-40 to 85°C) temperature range.
Functional Block Diagram
V+
Bootstrap
Regulator
2 CAP
VDD 4
Vee
o
7
8
5
FAULT
&:
~
IN 5
O.D1IlF
EN6
10
GND
_
P-37081-Rev. C (06/13/94)
GND
4-17
TEMIC
Si9976DY
Siliconix
Absolute Maximum Ratings
Voltage on IN, EN (pins 5, 6)
with respect to ground .................. -0.3 to VDD +0.3 V
Voltage on Vee (pin 7) ......................... -0.3 to +18 V
Voltage on V+, S1 (pins 3,13) ................... -0.3 to +50 V
Voltage on CAP, G1' (pins 2, 12) ................. -0.3 to +60V
Peak Output Current .................................. 0.5 A
Operating Thmperature (TA) ..................... -40 to 85'C
Storage Thmperature ........................... -50 to 150'C
Maximum Junction Thmperature (TJ) .................... 1ZS'C
Power Dissipationb ..................................... 1 W
ElJA ........................................... 100,C/Wb
Notes
a. Internally generated voltage for refe~ence only.
b. Derate 10 mWf'C above ZS'C.
c. PC board mounted with no forced air flow.
Specifications a
Test Conditions
UnlessOtherwise Specified
Parameter
Symbol
V+ =20t040V
TA = Operating Thmperatu~e Range
Limits
D SuffIX -40 to 85'C
Mine
'JYpb
Max"
Unit
1.0
V
Input
Input Voltage High (EN and IN)
VINH
Input Voltage Low (EN and IN)
VINL
4.0
Input Hysteresis Voltage
VH
Input Current-Input Voltage High
IINH
(EN and IN) VIN = 15 V
Input Current-Input Voltage Low
IINL
(EN and IN) VIN = 0 V
0.5
1
!1A
-1
Output
Output Voltage High, G1 d
Output Voltage High, G2e
Outpnt Vo1t~f;t· Tnw, Gl and G2
Sl = V+, lOUT = -lOrnA
VOUTH
Sl
= GND, lOUT =
-10 rnA
VOUTI.
Sl = GND. 10m = 60 rnA
Fault Output Voltage High
VOH
Vee = 4.5 V. lOUT = -0.2 rnA
Fault Output Voltage Low
VOL
Vee
10
12
12
15
1.2
3.5
= 4.5 V. lOUT = 0.6 rnA
3
V
4
0.3
Undervoltage Lockout 1
UVL1
11
Undervoltage Lockout 2
UVL2
14
Capacitor Current
lCAP
1.0
= GND, VCAP = OV
-10
Sl = GND, VCAP = 9V
-2
S1
rnA
Supply
V+ Supply Range
20
40
I+(H)
G2 High, No Load
1.7
3.5
I+(L)
G2 Low, No Load, Sl = GND
2
4.5
Vee Supply Current
Icc
Vee = 16.5 V
VDD Supply Voltagef
VDD
V + Supply Current
4.5
Vee Supply Range
4-18
15
16
V
rnA
16.5
V
10
!1A
17.5
V
P-37081-Rev. C (06/13/94)
TEMIC
Si9976DY
Siliconix
Speciticationsa
Test Conditions
UnlessOtherwise Specified
Parameter
Limits
D SuffIX -40 to 85"C
V+ =20t040V
TA = Operating Temperature Range
Symbol
Mine
JYpb
Max"
Unit
Dynamic
Propogation Delay TIme
Low to High Level
G1
350
G2
400
G1
150
G2
50
tpill
50% IN to VOUT = 5 Y, CL = 600 pF
Propogation Delay TIme
High to Low Level
tpHL
ns
Propogation Delay TIme, Low to High
Level, Enable-to-Fault Output
50% IN to FAULT = 2 Y, SI shorted to GND or V +
500
110
Output Rise TIme (G I, G2)
te
1 to lOY, CL = 600pf
Output Fall Time (Gl, G2)
tf
lOtol Y,CL= 600pf
50
Short Circuit Pulse Width
tse
50% to 50% OfVOUT
350
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. 1)1picai values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
d. To supply the output current of 10 rnA on a dc basis, an external13-V supply must be connected between the CAP pin and the SI pin with the
negative terminal of the supply connected to S1. This is not needed in an actual application because output currents are supplied by the CHOOT
capacitor. Voltage specified with respect to V+.
e. For testing purposes, the 10-mA load current must be supplied by an external current source to the VDD pin to avoid pulling down the VDO
supply.
f. Internally generated voltage for reference only.
'fiuth Thble
EN
IN
1
0
1
FAULT
Condition
OUTPUT
G10UT
GlOUT
Normal Operation
0
Low
High
1
Normal Operation
0
High
Low
0
X
Disabled
X'
Low
Low
1
0
Load Shorted to V +
Ib
Low
Low
1
1
Load Shorted to Ground
Ib
Low
Low
1
1
Undervoltage on CHOOT
0
Low
Low
1
0
Undervoltage on CHOOT
0
Low
High
X
X
Undervoltage on VOOc
1
Low
Low
Notes
a. FAULT output retains previous state until ENABLE rising edge.
b. Latch FAULT condition, reset by ENABLE rising edge.
c. VDD is an internally generated low-voltage supply.
P-37081-Rev. C (06/13/94)
4-19
TEMIC
Si9976DY
Siliconix
Pin Description
Pin 1
PinS: FAULT
No connection.
The Fault output is latched high when a short-circuit
output condition is detected. FAULT will return low
when the circuit is reset using the EN pin. The FAULT
output also indicates the status of the undervoltage
sense circuit on VDD, however the fault condition is
cleared automatically when the undervoltage condition
clears.
Pin2: CAP
Connection for the positive terminal of the bootstrap
capacitor CBOO1' A O.01-IlF CBOOT capacitor can be
used for most applications.
Pin3: V+
This is the only external power supply required for the
Si9976DY, and must be the same supply used to power
the half-bridge it is driving. The Si9976DY powers it's
low-voltage logic, low-side gate driver, and
bootstrap/charge pump circuits from self-contained
voltage regulators which require only a bootstrap
capacitor on the CAP pin and a bypass capacitor on the
VDDpin.
No voltage sensing circuitry monitors V + directly;
however, the low-voltage, internally generated VDD
supply and the bootstrap voltage (which are derived
from V +) are directly protected by undervoltage
monitors.
Pin 4: VDD
Connection to the internally generated low-voltage
supply which must be bypassed to ground with a 0.01-IlF
capacitor.
Pin 5: IN
Logic input. A low level input turns off the high-side
half-bridge MOSFET and, after an internally set dead
time, turns the low-side half-bridge MOSFET on. A
high input level has the opposite effect. The input is
compatible with 5-, 12- or 15-V logic outputs.
Pin9: G2
This pin drives the gate of the external low-side power
transistor.
Pinl0: GND
The ground return for V+, logic reference, and
connection for source of external low-side power
transistor.
Pin 11
No connection.
Pin 12: Gl
This pin drives the gate of the external high side power
transistor.
Pin 13: SI
Connection for the source of the external high-side
power transistor, the drain of the external low-side
power transistor, the negative terminal of the bootstrap
capacitor, and the system load. The voltage on this pin
is sensed by the circuitry that monitors the load for
shorts.
Pin 14
No connection.
Pin6: EN
Enable input. A low EN input level prevents turn on of
either half-bridge MOSFET. If the Si9976DY is
internally disabled as a result of an output short-circuit
condition, a low-to-high transition on EN is required to
clear the fault and resume operation. The input logic
levels are the same as IN.
Pin 7: Vee
If the FAULT output is used, the Vcc pin must be
connected to the logic supply voltage in order to set the
high level of the FAULT output. If the FAULT output is
not used, this pin may be left open with no effect on
internal fault sensing or protection circuitry.
4-20
SO-14
NC
NC
CAP
Sl
v+
G1
VDD
NC
GND
IN
EN
G2
FAULT
Vee
Top View
P-37081-Rev. C (06/13/94)
TEMIC
Si9976DY
Siliconix
Detailed Description
Power On Conditioning
Short Circuit Protection
Bootstrap-type floating supplies require that the
bootstrap capacitor be charged at power on. In the case
of the Si9976DY, this is accomplished by pulsing the IN
line low with the EN line held high, thus turning on the
low-side MOSFET and providing the charging path for
the capacitor.
This device is intended to be used only in a half-bridge
which drives inductive loads. A shorted load is presumed
if the load voltage does not make the intended transition
within an allotted time. Separate timing is provided for
the two transitions. A longer time is allowed for the
high-side to turn on (300 ns vs. 200 ns) since the
propagation delays are longer. Excessive capacitive
loading can be interpreted as a short. The value of
capacitance that is needed to produce the indication of
a short depends on the load driving capability of the
power transistors.
Operating Voltage: 20 to 40 V
The Si9976DY is intended to be powered by a single
power supply within the range of 20 to 40 V and is
designed to drive a totem pole pair of NMOS power
transistors such as those within the Si9955. The power
transistors must be powered by the same power supply as
this driver. In addition to the high-voltage power supply
(20 to 40 V), the Si9976DY must have a power supply
connected to the Vee terminal, if a fault output signal is
desired. This power supply provides operating voltage
for the fault output and allows the high output voltage
level to be compatible with system logic that monitors
the fault condition. The value of this power supply must
be within the range of 4.5 to 16.5 V to ensure
functionality of the output. Internal fault circuitry,
which is used for shorted-load protection, is not affected
by this power supply.
Cross-Conduction Protection
The high-side power transistor can only be turned on
after a fixed time delay following the return to ground of
the low-side power transistor's gate. The low-side
transistor can only be turned on after a fixed time delay
following the high-side transistor turn-off signal.
ESD Protection
Electrostatic discharge protection devices are between
VDD and GND, Vee and GND, and from terminals IN,
EN, G2, and FAULT to both VD D and GND. V +, CAP,
S1, and G1 are not ESD protected.
Fault Feedback
Detection of a shorted load sets a latch which turns off
both the high-side and the low-side power transistors.
If Vcc is present, a one level will be present on the
FAULT output. To reset the system, the enable input,
EN, must be lowered to a logic zero and then raised to
a logic one. The logic level of the input, IN, will
determine which power transistor will be turned on first
after reset. An undervoltage condition on VDD is not
latched, but causes a one level on the FAULT output, if
Vee is present.
Undervoltage Lockout
Static (de) Operation
During power up, both power transistors are held off
until the internal regulated power supply, VDD, is
approximately one Vbe from the final value, nominally
16 V. After power up, the undervoltage lockout circuitry
continues to monitor V DD. If an undervoltage condition
occurs, both the high-side and low-side transistors will be
turned off and the fault output will be set high. When the
undervoltage condition no longer exists, normal
function will resume automatically. Separate voltage
sensing of the bootstrap capacitor voltage allows a
turn-on signal to be sent to the high-side drive circuit if
either the bootstrap capacitor has full voltage, or the
load voltage is high (driven high by an inductive load or
shorted high). The voltage sensing circuit will allow the
high-side power transistor to turn on if an on signal is
present and the voltage on the bootstrap capacitor rises
from undervoltage to operating voltage.
All components of a charge pump, except the holding
(bootstrap) capacitor, are included in the circuit. This
charge pump will provide current that is sufficient to
overcome any leakage currents which would reduce the
enhancement voltage of the high-side power transistor
while it is on. This allows the high-side power transistor
to be on continuously. When the low-side power
transistor is turned on, additional charge is restored to
the bootstrap capacitor, if needed. The maximum
switching speed of the system at50% duty cycle is limited
by the on time of the low-side power transistor. During
this time, the bootstrap capacitor charge must be
restored. However, if the duty cycle is skewed so thatthe
on time of the high-side power transistor is long enough
for the charge pump to completely restore the charge lost
during switching, then the on time of the low-side power
transistor is not restricted.
4-21
P-37081-Rev. C (06/13/94)
TEMIC
Si9978DW
Siliconix
Configurable H-Bridge Driver
Features
• H-Bridge or Dual Half-Bridge Operation
• 20- to 40-V Supply
• Static (dc) Operation
• ESD Protected
• Fault Output
• Cross-Conduction Protected
• Current Limit
• Undervoltage Lockout
Description
The Si9978DW is an integrated driver for an n-channel
MOSFET H-bridge. The mode control allows operation
as either a full H-bridge driver or as two independent
half-bridges. The DlR/PWM input configuration allows
easy implementation of either sign/magnitude or
anti-phase PWM drive schemes for full H-bridges.
Schmitt triggers on the inputs provide logic signal
compatibility and hysteresis for increased noise
immunity. An internal low-voltage regulator allows the
device to be powered directly from a system supply of 20
to 40 volts. All n-channel gates are driven directly from
low-impedance outputs. The addition of one external
capacitor per half-bridge allows internal circuitry to level
shift both the power supply and logic signal for the
high-side n-channel gate drives. Internal charge pumps
replace leakage current lost in the high-side driver
circuits to provide "static" (dc) operation in any output
condition. Protection features include an undervoltage
lockout, cross-conduction prevention logic, and
overcurrent monitors.
The Si9978DW is available in the 24-pin wide-body
SOIC (surface mount) package, specified to operate
over the industrial (-40 to +85°C) temperature range.
Functional Block Diagram
'V+
Vnn
~24
1
, Bootstrap Reg. ,
I
I
Low-Voltage
Regulator
I erA
I
Vnn
Low-Side
I
, Charge Pump'
CT'B
High-Side
V.v. Lockout
I I
I--
Y
V.v. Lockout I
D1R/INA
QS/lNB
PWM/ENB
MODE
BRK
EN/ENA
CL/FAVLTB
FAULT/FAVLTA
4-22
3
5
4
.AA
Vnn
.AA
Vnn
2
..A
vv
Vnn
v
Vnn
.JI,/\/'v
I
Vnn
.J\A/Iv-
6
7
v
r-l.
lf
23
- CAP;,.
21
22
Bootstrap Reg.'
19
CAPB
Charge Pump , ~
17
I
Input
Logic
lf
GTB
18
Vnn
Vl?n
20
Vnn
~
"l-(' I
15
8
-b
9
11
I
12
I
One Shot
One Shot
Advance Information
GBB
GND
.......+
~I-
13
<:ij=jl-
14 0 ILB+
.....
P-34668-Rev. A (03/23194)
TEMIC
Si9978DW
Siliconix
Absolute Maximum Ratings
Voltage on pins 2-7 with respect to ground ........ -03 to 16.5 V
Voltage on pm 24 ............................... --0.3 to 50 V
Voltage on pins 17, 19, 21, 23 .................... -0.3 to +60 V
Voltage on pins 18, 22 ............................. -2 to 50 V
Operating Temperature (TA) .................... -40 to +8S·C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .. -50 to lS0·C
Maximum Junction Temperature (TJ) .................... lS0·C
Power Dissipation ....................... ........ . .. TBD
Recommended Operating Range
V+ ....................................... +20t040VDC
RA, RB ............................................ 100 kQ
Specifications
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
V+
~
20 to 40 V, TA
~
-40 to +8S·C
Limits
Min"
'JYpb
Max"
16
17.5
Unit
Power
Supply Voltage Range
V+
20
Logic Voltage
VDD
14.5
Supply Current
IDD~OmA
1+
40
4
V
rnA
Inputs (DIR, PWM, EN, QS, MODE, BRK)
High-State
VIH
Low-State
VIL
High-State Input Current
IIH
Low-State Input Current
IlL
4.0
1.0
VIH
~VDD
10
-50
VIL~OV
V
flA
Outputs
Low-Side Gate Drive, High State
VGBH
Low-Side Gate Drive, Low State
VGBL
High-Side Gate Drive, High State
VGI1I
High-Side Gate Drive, Low State
VGfL
Low-Side Switching, Rise 11me
14
16
17.5
14
16
18
1
1
110
trL
Low-Side Switching, Fall11me
tlL
High-Side Switching, Rise 11me
trH
High-Side Switching, Fall11me
tm
Rise 11me ~ 1 to 10 V
FaIl11me ~ 10 to 1 V
CL ~ 600pF
50
110
ns
50
Break-Berore-Make 11me
FAULT,CL
V
250
IOL~
VOL
0.4
lmA
V
Protection
Low-Side Undervoltage Lockout
Low-Side Hysteresis
High-Side U ndervoltage Lockout
12.2
UVLL
V
0.8
VH
UVLH
SA,B
~
OV
VDD-3.3V
Current Limit
Comparator Input Bias Current
1m
-5
Comparator Threshold Voltage
Vrn
90
One Shot Pulse Width
tp
Propagation Delay
tpd
flA
100
110
RA. RB - 100 k, CA. CB - 100 pF
8
10
12
RA. RB - 100 k, CA. CB - 0.001 J!F
80
100
120
CL- 600pF
600
mV
II.S
ns
Notes:
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. Guaranteed by design, not subject to production test.
P-34668-Rev. A (03/23/94)
Advance Information
4-23
TEMIC
Si9978DW
Siliconix
Truth Table
H-Bridge Mode
MODE
INA
EN!
EN;\.
QS[
INII
PWM/
ENII
1
1
1
1
SL
1
1
1
0
1
0
1
DlR/
GT;\.
GBA
GTII
GBII
0
L
X
H
L
L
SL
1
1
SL
0
L
X
SL
L
L
SL
1
1
1
SL
0
L
X
L
SL
H
L
1
1
SL SL
1
0
1
0
SL
0
L
X
L
1
X
1
X
X
1
L
X
L
1
X
0
X
X
X
L
X
L
1
X
1
X
X
0
SL
X
L
1
X
X
cu
FAULT/
FAULTB FAULTA
BRK ILA+ ILII+
X
X
X
X
Condition
Normal
Operation
L
1
1
L
H
1
1
Brake
L
L
L
1
1
Disable
L
L
L
"""l..J
"""l..J
Overcurrent
Undervoltage
onVDD
H
X
L
L
L
L
1
0
ILII+
GTA
GBA
GTII
GBII
CU
FAUI:f1l
FAULTI
FAULTA
L
H
L
L
L
1
1
Half-Bridge Mode
MODE
INA
EN!
ENA
QS!
INII
PWM/
ENII
0
1
1
X
0
X
L
DlR/
BRK IL;\.+
0
0
1
X
0
X
L
L
L
H
L
L
1
1
0
X
0
1
1
X
L
L
L
L
H
L
1
1
0
X
0
0
1
X
L
L
L
L
L
H
1
1
0
X
1
X
X
X
SL
X
L
L
X
X
1
L..f"
Condition
Normal
Operation
Overcurrent
onA
0
X
X
X
1
X
X
SL
X
X
L
L
L..f"
1
OverCllrrent
onB
0
X
X
X
X
X
X
X
L
L
L
L
0
0
U ndervoltage
onVDD
4-24
Advance Information
P-34668-Rev. A (03/23194)
TEMIC
Si9978DW
Siliconix
Pin Configuration
SO-24
(Wide Body)
V+
VDD
EN/ENA
CAPA
DIRJINA
SA
PWM/ENB
GTA
QSJINB
GBA
MODE
CAPB
BRK
SB
CL/FAULTB
GTB
FAULT/FAULTA
GBB
NC
GND
RAICA
ILB+
RBiCB
ILA+
Top View
Pin Description
Pin 1: VDD
Pin 4: PWM/ENB
VDD is an internally generated voltage. It is connected
to this pin to allow connection of a decoupling capacitor.
With the mode pin at logic "I", this pin is the PWM
input. It controls the switching of the active diagonal
pair. A logic "I" turns the active MOSFETs on, while a
logic "0" turns it off. The QS input determines whether
the bottom or both bottom and top MOSFETs are
switched. When implementing an anti-phase PWM
control, the PWM input is connected to a logic "I".
When the mode pin is at logic "0", this pin becomes the
ENABLE pin for half-bridge B.
Pin 2: EN/ENA
The EN input allows normal operation when at logic "1",
and turns all gate drive outputs off when at logic "0".
When the mode pin is at logic "1", EN controls the entire
H-bridge. When the mode pin is at logic "0", this pin
becomes the ENABLE pin for half-bridge A.
Pin 3: DIRJINA
The function ofthis pin is determined by the MOD E pin.
When the MODE pin is at logic "I", it is the DIR pin,
and when MODE is at logic "0", it is the INA pin.
As the DIR input, it is the direction control for the
H-bridge, and determines which diagonal pair of power
MOSFETs is active. A logic "I" turns on GTA and
enables GBB, while a logic "0" turns on GTB and enables
GB A . When implementing an anti-phase PWM control,
the DIR input serves as thc PWM input.
As the INA pin, it is the input that controls the "Pi.'
half-bridge. When at logic "I", the high-side MOSFET
is turned on, and when at logic "0", the low-side
MOSFET is turned on.
P-34668-Rcv. A (03123194)
Pin 5: QS/INB
With the mode pin at logic "I", this input determines
whether the bottom MOSFETs of the H-bridge or both
bottom and top MOSFETs switch in response to the
PWM signal. A logic "I" on this input enables only the
bottom MOSFETs. This is the default condition as this
pin is pulled up internally. When this pin is pulled to
ground, both the bottom and top MOSFETs are enabled.
This input controls the B half-bridge when the MODE
pin is at logic "0". When at logic "I", the high-side
MOSFET is turned on, and when at logic "0", the
low-side MOSFET is turned on.
Pin6: MODE
This input determines whether the Si9978 functions as
an H-bridge or as two independent half-bridges. When
the MODE pin is at logic "I", the Si9978 functions as an
H-bridge, and when MODE is at logic "0", it functions
as two independent half-bridges.
Advance Information
4-25
TEMIC
Si9978DW
Siliconix
Pin Description (Cont'd)
Pin 7: BRK
Pin 13: ILA + and Pin 14, ILB+
When this input is at logic "I", both bottom gate drives
are switched high, turning on the bottom MOSFETs.
When this input is at logic "0", the Si9978 operates
normally.
These are the overcurrent sense inputs. Internally, they
are connected to the noninverting inputs of the current
limit comparators. Externally they are connected to the
source(s) of the low-side MOSFET(s) and the current
sense resistor.
Pin 8: CL/FAULTB
Pin 15: GND
This is an open drain output which is active low. When
the MODE pin is at logic "I", this pin functions as CL
and indicates that the H-bridge is in current limit. It stays
low for the duration of the current limit one-shot. With
the MODE pin at logic "0", it serves as the FAULT
output for half-bridge B to indicate when an
undervoltage or overcurrent condition is detected.
When indicating an overcurrent condition, the output
stays low for the duration of the current limit one-shot.
The FAULT output resets automatically when the
condition clears.
The GND pin is the ground return for V + and the
ground reference for the logic. Also, this is the ground
reference input for the current limit comparators and is
connected to the ground side of the internal 100-mV
references. This pin should be connected directly to the
ground side of the current sensing resistors.
Pin 16: GBB and Pin 20, GBA
These pins drive the gates of the low-side power
MOSFETs.
Pin 17: GTB and Pin 21, GTA
Pin 9: FAULT/FAULTA
This is an open drain output which is switched low when
an undervoltage or overcurrent condition is detected.
When indicating an overcurrent condition, the output
stays low for the duration of the current limit one-shot.
When the MODE pin is at logic "I", this pin is the
H-bridge FAULT output. With the MODE pin at logic
"0", it ~~rve.s as the FAULToutpui [or half-bridge A. The
FAULT output resets automatically when the condition
clears.
These pins drive the gates of the high-side power
MOSFETs.
Pin 18: SB and Pin 22, SA
These are the source connections of the high-side power
MOSFETs, the drain of the external low-side power
MOSFET, the negative terminal of the bootstrap
capacitor, and the output for each half-bridge.
Pin 19: CAPB and Pin 23, CAPA
Pinl0: NC
These are the connections for the positive terminals of
the bootstrap capacitors CBA and C BB . A O.Ol-IlF
capacitor can be used for most applications.
The timing resistor and capacitor for the current limit
one-shot are connected to this pin. The values of the
resistor and capacitor determine the off time set by the
one-shot. The one-shot is triggered when the current
limit comparator detects an overcurrent condition.
Pin 24: V+
Pin 12: RBiCB
The timing resistor and capacitor for the current limit
one-shot are connected to this pin. The values of the
resistor and capacitor determine the off time set by the
one-shot. The one-shot is triggered when the current
limit comparator detects an overcurrent condition.
4-26
This is the only external power supply required for the
Si9978DW, and must be the same supply used to power
the H-bridge it is driving. The Si9978DW powers it's
low-voltage logic, low-side gate driver, and bootstrap/
charge pump circuits from self-contained voltage
regulators which require only a bootstrap capacitor on
the CAP pins.
No voltage sensing circuitry monitors V + directly;
however, the low-voltage, internally generated supply
and the bootstrap voltage (which are derived from V +)
are directly protected by undervoltage monitors.
Advance Information
P-34668-Rev. A (03/23/94)
TEMIC
Si9978DW
Siliconix
Applications
LITI'LEFOOT
V+
-
L
1
( C2
EN
DIR
PWM
QS
VDD
2
EN/ENA
3
DIR/INA
4
PWM/ENB
5
QS/lNB
--
~ MODE
7
BRK
8
9
CL
FAULT
BRK
CuFB
f1/FA
~ NC
..2!~
~
RA/CA
RBiCB
v+
CAPA
SA
GTA
GBA
CAPB
SB
GTB
GBB
GND
ILB+
II~
!;;
I
\.
24
~E--l
22
21
20
19
18
17
16
1/
Cs
I
I
I
15
~
ILA+ ~3
I
I
I
I
I
I
I
I
~
rl--.J
I
y
c:
I
L __ ,
I
I
I
I
I
I
I
A
B
OUT OUT
!
I
I
I
I
I
I
I
I
I
I
I
I
r44J I
q Q2-,
UJ
-'"
~-,I
I
jQ3
I
U1
1
/
r~5'I
C3)
:J7
ICI
QI
lw__ J
I
I
I
I
L_~
I
'--
R3
Si9978DW
Rz
Vee,0--0-
rRI
Cs
GND
1.
Figure 1.
P-34668-Rev. A (03/23/94)
Basic H-Bridge Circuit
Advance Information
4-27
TEMIC
Si9979CS
Siliconix
3-Phase Brushless DC Motor Controller
Features
• Hall-Effect Commutation
• 60· or 120· Sensor Spacing
• Integral High-Side Drive for all
N-Channel MOSFET Bridges
• PWMInput
•
•
•
•
• Quadrature Selection
• Tachometer Output
• Reversible
• Braking
• Output Enable Control
Cross Conduction Protection
Current Limiting
Undervoltage Lockout
Internal Pull-Up Resistors
Description
bridge. PWM, direction, quadrature select, and braking
inputs are included for control along with a tachometer
output. Protection features include cross conduction
protection, current limiting, and undervoltage lockout.
The FAULT output indicates when undervoitage, over
current, disable, or invalid sensor shutdown has
occurred.
The Si9979CS is a monolithic brushless dc motor
controller with integral high-side drive circuitry. The
Si9979 is configured to allow either 60 0 0r 120°
commutation sensor spacing. The internal low-voltage
regulator allows operation over a wide input voltage
range, 20- to 40-V dc.
The Si9979CS provides commutation from Hall-effect
sensors. The integral high-side drive, which utilizes
combination bootstrap/charge pump supplies, allows
implementation of an all n-channel MOSFET 3-phase
The Si9979CS is specified to operate over the
commercial (O°C to 70°C) temperature range.
Functional Block Diagram
V+
Vnn
I
43
I
Low-Voltage
Regulator
Y--i
Low-Side
INB
INc
60/120
3
4
5
FIR
6
PWM
BRK
TACH
FAULT
v
v-
Vnn
VnD
.JV\IIr
7
8
VnD
v-
VREF
.JV\IIr
.JV\IIr
.JV\IIr
VREF
A
9
vv-
CAPA CAPB CAPe
J T 1.
IU.v.
High-Side
Lockout
~
36
34-0
I
I
-1
-1
Vnn
.AAA
I~
Charge Pump
1I
.A
.A
EN
QS
4-28
1
2
I
Vnn
VREF
U.v. Lockout
INA
I
Bootstrap Reg.
42
I I
I
35
0
I
32
I~
30
Bootstrap Reg.
Charge Pump
I
I.(
I
Bootstrap Reg.
Charge Pump
I
2.
CAPe
~
26
Input
Logic
VnD
I
11
GTB
31
GTe
27
Sc
~
V
VREF
~
VREF
VREF
GBB
~ GBc
10
~6,21'24
11
18
I
17
One Shot
I
I
Advance Information
L
-=-
37-41.44-48
<1H1
......
20
19
0
GND
0 Is-
Is+
P-34651-Rev. A (03/25/94)
TEMIC
Si9979CS
Siliconix
Absolute Maximum Ratings
Voltage on Pin 42 ...................................... 50 V
Voltage on Pins 1-4, 10, 11 ............. -0.3 V to VOO + 0.3 V
Voltage on Pins 5-9 .......................... -0.3 V to 5.5 V
Voltage on Pins 26, 28, 30, 32, 34, 36 ...................... 60 V
Voltage on Pins 27, 31, 35 .......................... -2 to 50 V
Operating Temperature ............................ 0 to 70·C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .. -65 to 150·C
Junction Temperature (TJ) ............................. 150·C
Power Dissipation (Po) ............................... 0.7 W
Recommended Operating Range
v+ ........................................ +20t040VoC
RT ............................................. 10 k.Q Min
Specifications
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
Limits
C SuffIX: 0 to 70·C
V+ =20t040V
Mina
-20 rnA :S Ioo:S OmA
14.5
1YPb
Max"-
16
17.5
Unit
Power
Supply Voltage Range
V+
Logic Voltage
Voo
Supply Current
1+
Logic Current
100
20
100 =
ornA
40
V
4.5
rnA
-20
Commutation Inputs (INA. IND, INC. 60/120)
High-State
Vm
Low-State
VIL
4.0
High-State Input Current
1m
Vm- Voo
Low-State Input Current
IlL
VIL= OV
1.0
V
10
~A
-50
Logic Inputs (FIR, EN, QS, PWM, BRK)
High-State
Vm
Low-State
VIL
High-State Input Current
1m
Vrn - 5.5 V
Low-State Input Current
IlL
VIL= OV
2.0
0.8
V
10
~
-125
Outputs
LoW-Side Gate Drive, High State
VGBH
Low-Side Gate Drive, Low State
VGBL
High-Side Gate Drive, High State
VGTH
High-Side Gate Drive, Low State
VGTL
Low-Side Switching, Rise TIme
trL
Low-Side Switching, Fall TIme
tlL
High-Side Switching, Rise TIme
trH
High-Side Switching. Fall TIme
tfH
Break-Before-Make TIme
TACH Output/FAULT Output
TACH Output Pulsewidth
P-34651-Rev. A (03/25/94)
14
16
17.5
0.1
16
18
V
0.1
70
Risetime = 1 to 10 V
Falltime = 10 to 1 V
CL= 600pF
25
100
ns
40
tBLH
100
tBHL
300
VOL
0.15
IOL= 1.0mA
300
tT
Advance Information
600
0.4
V
ns
4-29
TEMIC
Si9979CS
Siliconix
Specifications
Limits
C SuffIX: 0 to 70'C
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
'JYpb
Mina
V+ = 20t040V
Maxa
Unit
Protection
Low-Side Undervoltage Lockout
12.2
UVLL
Low-Side Hysteresis
High-Side Undervoltage Lockout
VH
0.8
UVLH
VDD3.3
SA,B.C = OV
V
Current Limit
Comparator Input Bias Current
1m
-5
Comparator Threshold Voltage
Vrn
90
Common Mode Voltage
VCM
One Shot Pulse Width
f!A.
100
110
mV
1
V
0
tp
RT - 10 k CT - O.OOlI'F
8
10
12
RT = 10kCT - O.D1I'F
80
100
120
I's
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. 'lYpical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Commutation Truth Table
Outputs
Inputs
Sensors
(60 0 Spacing)
Sensors
(120° Spacing)
Thp Drive
INA
INB
INc
INA
INs
INc
EN
FIR
BRK
Is+
GTA
GTB
0
0
0
1
1
1
0
0
0
1
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
1
1
1
0
0
1
0
1
1
1
1
0
0
0
1
1
1
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
1
0
0
0
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
1
1
0
0
L
L
L
L
L
L
1
L
L
L
1
1
0
0
L
L
L
1
1
0
0
L
L
L
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
1
1
1
0
0
1
X
X
1
X
1
X
1
1
1
1
X
X
X
X
X
X
0
1
1
X
X
X
X
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Conditions
Bottom Drive
GTe GBA GBs
GBc
FAULT
0
0
1
1
0
0
0
0
0
0
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
1
0
1
1
0
0
0
0
1
0
0
1
1
0
0
0
1
1
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
Disable
Power Down
Brake
OverlinBRK
Over I
Notes: L. Any valid sensor combination
x. Don't care
4-30
Advance Information
P-34651-Rev. A (03/25/94)
TEMIC
Si9979CS
Siliconix
Pin Configuration
SQFP-48
36
CAPA
SA
GTA
GBA
60/120
EN
FiR
QS
CAPB
6
SB
GTB
PWM
GBB
CAPe
BRK
TACH
Se
FAULT
GTe
GND
GBe
Q
Q
Q
Q
,i;' f-o +
I
Q Q
Q Q
~~~~l'~~~~~~~
ThpView
Pin Description
FJR (ForwardlReverse)
Pins 1-3: INA, IND, INc
Pin 6:
INA. INB, and INc are the commutation sensor inputs,
and are intended to be driven by open collector Hall
effect switches. These inputs have internal pull up
resistors tied to VDD, which eliminates the need for
external pull up resistors.
A logic "I" on this input selects commutation for motor
rotation in the "forward" direction. This is the default
condition as this pin is pulled up internally. When this
pin is pulled to ground, the commutation sensor logic
levels are inverted internally, causing reverse rotation.
Pin 4: 60/120
This input determines whether the bottom MOSFETs or
both bottom and top MOSFETs switch in response to the
PWM signal. A logic "I" on this input enables only the
bottom MOSFETs. This is the default condition as this
pin is pulled up internally. When this pin is pulled to
ground, both the bottom and top MOSFETs are enabled.
Pin 7: QS (Quadrature Select)
The 60/120 input allows the use of the Si9979 with either
a 60· or 120· commutation sensor spacing. An internal
pull up resistor, which is tied to VDD. sets the default
condition to 60· spacing. 120· spacing is selected by
pulling this input to ground.
Pin8: PWM
Pin 5: EN (Enable)
A logic "I" on this input allows commutation of the
motor. This is the default condition as this pin is pulled
up internally. When this pin is pulled to ground, all gate
drive outputs are turned off.
P·34651-Rev. A (03/25/94)
An open collector (drain) or TTL compatible signal is
applied to this input to control the motor speed. The QS
input determines which MOSFETs are switched in
response to the PWM signal. If no PWM signal is being
used, this input is left open. It is pulled up internally,
which allows the MOSFETs to follow the commutation
sequence.
4-31
Advance Information
TEMIC
Si9979CS
Siliconix
Pin Description (Cont'd)
Pin9: BRK
Pin 20: IS-
With this input at logic "1", the top MOSFETs are turned
off and the bottom MOSFETh are turned on, shorting
the motor windings together. This provides a braking
torque which is dependent on the motor speed. This is
the default condition as this pin is pulled up internally.
When this pin is pulled to ground, the MOSFETs are
allowed to follow the commutation sequence.
This pin is the ground reference for the current limit
comparator. It should be connected directly to the
ground side of the current sense resistor to enhance
noise immunity.
Pins 12-16: 21-24,37-41,44-48, GND
These pins are the return path for both the logic and gate
drive circuits. Also, they serve to conduct heat out of the
package, into the circuit board.
Pin 10: TACH
This output provides a minimum 300 nanosecond output
pulse for every commutation sensor transition, yielding
a 6 pulse per electrical revolution tachometer signal.
This output is open drain.
Pin25: GBe
This is the gate drive output for the bottom MOSFET in
Phase C.
Pin 11: FAULT
Pin26: GTe
The FAULT output switches low to indicate that at least
one of the following conditions exists, controller disable
(EN), undervoltage lockout, invalid commutation
sensor code shutdown, or overcurrent shutdown. This
output is open drain.
This is the gate drive output for the top MOSFET in
Phase C.
Pin 17: RT/CT
The junction of the current limit one shot timing resistor
and capacitor is connected to this pin. This one-shot is
ttiggered by the CUlrent linlit colnpaJatoJ when ali
overcurrent condition exists. This action turns off all the
gate drives for the period defined by RT and On thus
stopping the flow of current.
Pin 18: RT
Pin 27: Sc
This pin is negative supply of the high-side drive
circuitry. As such, it is the connection for the negative
side of the bootstrap capacitor, the top MOSFET
Source, the bottom MOSFET Drain, and the Phase C
output.
Pin28: CAPe
This pin is the positive supply of the high-side circuitry.
The bootstrap capacitor for Phase C is connected
between this pin and SC.
Pin29: GBB
One side of the current limit one shot timing resistor is
connected to this pin.
This is the gate drive output for the bottom MOSFET in
Phase B.
Pin 19: IS+
Pin30: GTB
This is the sensing input of the current limit comparator
and should be connected to the positive side of the
current sense resistor. When the voltage across the
current sense resistor exceeds 100 mY, the comparator
switches and triggers the current limit one-shot. The
one-shot turns off all the gate drives for the period
defined by RT and Cll thus stopping the flow of current.
If the overcurrent condition remains after the shutdown
period, the gate drives will be held off until the
overcurrent condition no longer exists.
This is the gate drive output for the top MOSFET in
Phase B.
4-32
Pin 31: SB
This pin is negative supply of the high-side drive
circuitry. As such, it is the connection for the negative
side of the bootstrap capacitor, the top MOSFET
Source, the bottom MOSFET Drain, and the Phase B
output.
Advance Information
P-34651-Rev. A (03/25/94)
TEMIC
Si9979CS
Siliconix
Pin Description (Cont'd)
Pin32: CAPB
This pin is the positive supply of the high-side circuitry.
The bootstrap capacitor for Phase B is connected
between this pin and SB.
Pin33: GBA
This is the gate drive output for the bottom MOSFET in
Phase A.
Pin34: GTA
This is the gate drive output for the top MOSFET in
Phase A.
Source, the bottom MOSFET Drain, and the Phase A
output.
Pin36: CAPA
This pin is the positive supply of the high-side circuitry.
The bootstrap capacitor for Phase A is connected
between this pin and SA.
Pin 42: V+
The supply voltage for the Si9979 is connected between
this pin and ground. The internal logic and high-side
supply voltages are derived from V +.
Pin43:
VDD
is the internal logic and gate drive voltage. It is
necessary to connect a capacitor between this pin and
ground to insure that the current surges seen at the turn
on of the bottom MOSFETs does not trip the
undervoltage lockout circuitry.
VDD
Pin3S: SA
This pin is negative supply of the high-side drive
circuitry. As such, it is the connection for the negative
side of the bootstrap capacitor, the top MOSFET
Applications
LITILEFOOT
V+ o-~--------~--------------------------------~~~,,~~~--,
Si9979CS
42
43
Com!tation{
Sensors
0-+------------''-1
V+
GTA
VDD
SA
INA
CAPA
INB
GTB
0-/------"-1 INc
34
SB
CAPB
EN
FIR
9
GND
o-~------~~
__
C
Motor
Windings
CAPe
GBA
GBB
GBe
Is+
IsGND
12-16,21-24
37-41,44-48
~--------~
Figure 1.
P·34651-Rev. A (03/25/94)
Se
BRK
60/120
10
TACH 0-+------------""-1 TACH
QS
PWM IN 0-+-----------:''-1 PWM
11
FAULT o-+---------~~ FAULT
RT
RT/CT
GND
~--~~--~-r~~Th
GTe
__
~~---J
Three-Phase Brushless DC Motor Controller
Advance Information
4-33
TEMIC
Si9979CS
Siliconix
Applications (Cont'd)
V+~-------4--------------------------4r~~~
Si9979CS
42
43
eom!tation{
Sensor
2
C>-f-------+--~
9
V+
VDD
GTA
INA
CAPA
INB
GTB
INc
SB
CAPB
SA
EN
FiR
BRK
Sc
10
o-r---------~~
Notes:
GBA
1) If driving single phase
BLDC, tie INA. INIlo
and INc together and
GBB
GBc
drive with smgle hall.
2) If It is hemg used as
an H.bridgecontroller,
tie INA. IN8, and INc to
20
RT/CT
RT
GND. Use FiR input to
C
CT
Rs
GND
1b
B Motor
Windings
CAPc
60/120
TACH
QS
PWM
PWMIN o-r---------~~
11
FAULT o-r---------~~
FAULT
18
RT
17
TACH
~__-+-r~__~A
GTc
o-~------~--~--------~--+-+---~
change active diagonal
pair ofMOSFETh.
3) There is no TACH
output when connected
in this configuration.
-=Figure 2. Single H-Bridge Controller
v+ O~
MC14OZ1
Si9979CS
v+
GTA I-"!!.'------------~i--t.:f)
SA
LK
2
CPo
•
IN8
GT8
INc
S8
r--.,---------i-l''-1
EN
FiR
BRK
60/120
TACH
[0
o-t-----:-------"'I
TACH
QS
PWM IN 0-+----------:':-1
11
FAULT
O-i-::===:ftl
18
GND o-~----~~--~--------~-4-+--~
.Figure 3. 1hree-Phase AC Motor Controller
4-34
Advance Information
P-34651-Rev. A (03/25/94)
TEMIC
Si9979CS
Siliconix
Applications (Cont'd)
V+
Voo' - - t - - - - , .
~----~-lV+
1.------.___-1
Voo
Si9979
Voo'
= Voo - VBE
Figure 4. External Voo Regulator
P-34651-Rev. A (03/25/94)
Advance Information
4-35
TEMIC
Bus Interface . .
TEMIC
Si9241
Siliconix
Single-Ended Bus Driver
Features
Benefits
Applications
o Single-Ended Transceiver
o Survives Shorts and uansients on Automotive Bus
• Wide Power Supply Voltage Range
o Fault Detection
o ISO 9141 Compatible
• Single-Wire Multiplexer Interface
• ISO Diagnosis Bus
• 1rucks
• Automobiles
• uactors
Description
The Si9241 is a monolithic bus driver designed to provide
bidirectional serial communication in automotive
diagnostic applications.
The device incorporates protection against overvoltages
and short circuits to GND or VB. The transceiver pin is
protected and can be driven beyond the VB voltage.
A fault detector provides an active low in case of short
circuit to VB or an open load prevent proper data
transmission. The open drain Fault output can be wire
or-ed. The CS input can be tied high for receive only
interfaces.
In the event of an over temperature condition, the
output is immediately switched off and a fault indicated.
This condition can only be reset once the over
temperature condition is removed, and CS is toggled
high.
The Si9241 is built on the Siliconix BiC/DMOS process.
This process supports bipolar transistors, CMOS and
DMOS. An epitaxial layer prevents latchup.
The RX output is capable of driving CMOS or
1 X LSTTL load.
The Si9241 is available in a space efficient 8-pin SO
package. It operates reliably over the automotive
temperature range (-40 to 125°C).
Pin Configurations and lFunctional Block Diagram
Narrow Body
SO Package
VDD
VB
?
?
RXo-~------------------~
VDD
V D D u B RX
TX
2
7
CS
FAULT
3
6
VB
K
4
5
GND
K
cso---+-~~-+--~~
TXo---+-----~--~~
Top View
Order Number:
FAULT
0---1--------1
Si9241EY
P-34770-Rev. A (04/05/94)
5-1
TEMIC
Si9241
Siliconix
Output Table and State Diagrams
OverThmp
Power On
Inputs
State
Variable
Output
Table
Over Thmp· CS
CS
TX
A
B
C
RXK
K
FAULT
Short Circuit
0
0
0
1
1
1
1
1
0
0
1
1
x
0
0
x
0
1
1
1
0
1
1
K
1
x
1
1
1
1
K
HiZ
H,Z
0
K
HiZ
0
0
0
1
1
x
1
1
1
1
1
0
1
1
0
1
1
1
Power On
CS
Open Circuit
Power On
X
X
Commenh
OverThmp
Short Circuit
Open Circuit
Receive Mode
X= "1" or "0"
HiZ = High Impedance State
CS
Note: Over Temp is a condition and not meant to be a logic signal.
Absolute Maximum Ratings
Voltage Referenced to Ground
Voltage On VBAT ..................................... 45 V
Voltage K ................................ -3 to VBAT + 1 V
Voltage or Max. Current On Any Pin
(Except VBAT, K) ............... -03 to Vnn + 03 V or 10 rnA
Voltage on Vnn ........................................ 7 V
Short Circuit Duration (to VBAT or GND) . . . . . . . . . .. Continuous
Operating Temperature (TA) .................... -40 to 125"C
Junction and Storage Temperature ................. -55 to 150"C
Thermal Resistance alA ............................... TBD
Specificationsa
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
Vnn = 4.5 to 5.5 V, VBAT = 8 to 35 V
Limits
E SuffIx: -40 to 125"C
Tempb
Minc
'JYpd
Maxc
Unit
'Jioansmttter and lA>gtc Levels
CS, TX Input Low Voltage
VILT
Full
CS, TX Input High Voltage
Vnrr
Full
K Output Low Voltage
VOLK
Full
K Output High Voltage
VOHK
K Rise, Fall TImes
tn tf
K Output Sink Resistance
Rsi
K Output Capacitance"
Co
TX Input Capacitance"
CS, TX Input Current
5-2
RL = 510Q CL = lOnF
See Thst Circuit
Full
1.5
3.5
0.2VBAT
V
0.91 VBAT
Full
96
IlS
CS=OV,TX=OV
Full
110
Q
CS=OV
Full
20
CINT
Full
10
lINT
Full
-60
-4
pF
JlA.
P-3477G-Rev. A (04/05/94)
TEMIC
Si9241
Siliconix
Specifications a
Test Conditions
Unless Olherwise Specified
Parameter
Symbol
VDD = 4.5 to 5 5 V, VBAT = 8 to 35 V
Limits
E SuffIX: -40 to 125°C
Tempb
Mine
1Ypd
Max"
004
VBAT
0.30VBAT
Unit
Receiver
K Input Low Voltagef
VIl.K
Full
K Input High Voltagef
VIHK
Full
RX Output Low Voltage
VOLR
RX High Voltage
VOHR
K Input Currents
IIHK
0.70VBAT
0.6
VBAT
V
CS=4V
VIl.K. VIlL = 0.30 VSAT
IOLR = 1 rnA
Full
VIHK. VIHL = 0.70 VBAT
IOHR = -40~A
Full
2.8
VIHK= VBAT
Full
15
004
20
~
Supplies
Bat Supply Current
lBAT
Logic Supply Current
IDD
CS. TX = 1.5 V
KOpen
Full
2.7
5.0
Full
1
3.0
rnA
Miscellaneous
Baud Rate
Fault Output Low Voltage
BR
RL = 510 ~ CL = 10 nF
Full
VOLF
VILT - Ov, VK - VB. IOLF - 1 rnA
Full
lOA
kBaud
0.4
V
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25°C. Ccld and Hot = as determined by the operating temperature suffIX.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. is used in this data sheet.
d. 'lYpical values are for DESIGN AID ONLY. not guaranteed nor subject to production testing.
e. Guaranteed by design. not subject to production test
f. Hysterisis 0.2 VBAT typical.
'fest Circuit
VB
VDD
VB
Si9241
RL
K
TX 0---1--'\_
CL
-
VK
GND
P-34770-Rev. A (04/05/94)
5-3
TEMIC
Si9241
Siliconix
Application
Diagnostic Thster
ECU
K-Line
I/Os
Micro-Controller
r---+-.I.~~
Si9241
L-Line
VDD 0 - - - - 1 1 - - - -
Si9241
ECU = Electronic Control Unit
5-4
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Bus
P-3477O-Rev. A (04/05/94)
TEMIC
Si9243
Siliconix
Single-Ended Bus Driver
Features
• Single-Ended Transceiver
• Survives Shorts and Transients on Automotive Bus
• Wide Power Supply Voltage Range
• Fault Detection
• IS09141 Compatible
Description
The Si9243 is a monolithic bus driver designed to provide
bidirectional serial communication in automotive
diagnostic applications.
to protect the IC. The fault will be reset when TX toggles
"high".
TX is set "high" for receive only.
The device incorporates protection against overvoltages
and short circuits to GND or VBA'P The transceiver pin
is protected and can be driven beyond the VBATvoltage.
The temperature and short circuit fault detection
feature is still active as in the Si9242, but the FAULT
signal is not brought out. In the transmit mode, load
shorts and opens are generally detected by the processor
monitoring RXK and TX. When the two mirror each
other there is no fault, but the Si9243 will tum off the K
output in the event of over temperature or short circuit
The RX output is capable of driving CMOS or
1 x LSTTL load.
The Si9243 is built on the Siliconix BiC/DMOS process.
This process supports bipolar transistors, CMOS and
DMOS. An epitaxial layer prevents latchup.
The Si9243 is available in a 8-pin SO package and
operates over the automotive temperature range (-40
to 125°C).
Pin Configurations and Functional Block Diagram
GND
L
RXL
Narrow Body
so Package
E~~BAT
RXK
K
o-----i-<
TX~GND
Top View
Order Number:
Si9243EY
VDD
I - - -_ _K----'~
TX
Logic Circuitry
(See State Diagram and Truth Thble)
P-34770-Rev. A (04/05/94)
5-5
TEMIC
Si9243
Siliconix
Output Table and State Diagrams
OverThmp
Inputs
Power On
Over Thmp • TX
Short Circuit
Power On
State
Variable
Output
Table
TX
A
B
K
RXK
L
RXL
0
1
0
1
x
0
1
1
1
1
0
1
1
1
1
1
1
0
0
1
0
1
HiZ
HiZ
0
1
0
1
K
1
0
1
1
0
L
L
0
1
1
0
L
L
1
1
1
1
1
1
1
0
1
0
1
0
1
0
Comments
Over Temp
Short Circuit
TX
Note: Over Temp is a condition and not meant to be a lOgic signal.
Receive Mode
X = "1" or "0"
HiZ = High Impedance State
Absolute Maximum Ratings
Voltage Referenced to Ground
Voltage On VBAT ..................................... 45 V
Voltage K,L .............................. -3 toVBAT + 1 V
Voltage On Any Pin (Except VBAT, K)
or Max. Current. ................ -0.3 to VDD
+ 0.3 V or 10 rnA
Voltage on VDD ........................................ 7 V
Short Circuit Duration (to VBAT or GND) .. . . . . . . . .. Continuous
Operating Thmperature (TA) .................... -40 to 125·C
Junction and Storage Temperature ................. -55 to 150·C
Thermal Resistance
a JA
............................... TBD
Specifications a
Limits
E SuffIX: -40 to 125·C
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
VDD = 4.5 to 5.5 V. VBAT = 8 to 35 V
Tempb
Mine
'JYpd
MaX<
Unit
1i"allsmltter alld logic Levels
TX Input Low Voltage
VILT
Full
TX Input High Voltage
Vnrr
Full
K Output Low Voltage
YOLK
K Output High Voltage
VOHK
1.5
3.5
V
Full
RL = 510~ CL = 10nF
See Thst Circuit
Full
0.2VBAT
0.91 VBAT
K Rise, Fall Times
t"t!
Full
9.6
~s
K Output Sink Resistance
Rsi
Full
110
Q
K Output Capacitancee
Co
Full
20
TX Input Capacitancee
CINT
Full
10
TX Input Current
lINT
Full
5-6
TX=OV
-60
-4
pF
J1A.
P-34770-Rev. A (04/05194)
TEMIC
Si9243
Siliconix
Specifications a
Test Conditions
Unless Otherwise Specified
Parameter
Symbol
VDD = 4.5 to 5.5 Y, VBAT = 8 to 35 V
Limits
E Suffix: -40 to 125'C
Tempb
Mine
Typd
Max<
0.4 VBAT
0.3 VBAT
Unit
Receiver
LandK
Input Low Voltagef
VU.K
Full
LandK
Input High Voltagef
VrnK
Full
RXLandRXK
Output Low Voltage
VOLR
RXL and RXK High
Voltage
VOHR
Land K Input Currents
0.7VBAT
0.6VBAT
V
IrnK
TX=4V
VII.K, VILL = 030 VBAT
IOLR= 1 rnA
Full
VrnK, VrnL = 0.70 VBAT
IOHR = -40 I'f\
Full
2.8
VrnK= VBAT
Full
1.5
0.4
20
~A
Supplies
Bat Supply Current
IBAT
TX= 1.5Y,
K, LOpen
Full
2.7
5.0
Logic Supply Current
IDD
TX = 1.5Y,
K, LOpen
Full
1
3.0
BR
RL = 510 Q, CL = 10 nF
Full
rnA
Miscellaneous
Baud Rate
10.4
kBaud
Notes
a Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25'C, Cold and Hot = as determined by the operating temperature suffIX.
c. The a1gebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. 'iYPical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design. not subject to production test.
f. Hysterisis 0.2 VBATtypical.
Test Circuit
VDD
TX
o------1l--l
P-34770-Rev. A (04/05/94)
5-7
TEMIC
Si9243
Siliconix
Application
Diagnostic Thster
ECU
K-Line
5100
1
I/Os
Micro:Controller ,--+-J.C-...-I
0 40
.
L-Line
Von
Si9243
Eeu = Electronic Control Unit
I
I
I
I
I
I
I
I
I
I
J
I
I
Bus
J
J
J
J
I
5-8
P-34770-Rev. A (04/05194)
N-/P-Channel MOSFETs
•
About N-/P-Channel MOSFETs
Siliconix is the industry leader for low on-resistance power MOSFETh, which are offered in a wide range of
voltages and package types. Thchnologies packing as many as 8 million cells per square inch of silicon
make possible 60-V devices with n-channel on· resistance of 8 mg and p-channel on-resistance of
20 mg-the lowest maximum rated values for any given package on the market. Products in this section
include devices housed in the TO-22O, DPAK, D2PAK, and other packages rated for both the industrial
and military temperature ranges.
TEMIC
BUZII
Siliconix
N·Channel Enhancement·Mode 'fransistor
Product Summary
V(BR)nSS (V)
rnS(on) (Q)
In (A)
50
0,040
30
D
TO-220AB
o
DRAIN connected to TAB
GDS
S
Top V,ew
N-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Symbol
limit
Drain-Source Voltage
VDS
50
Gate-Source Voltage
VGS
±20
V
30
I Tc = 25"C
Continuous Drain Current
ID
19
ITc = 100"C
Pulsed Drain Current
75
I Tc=25"C
W
PD
30
ITc = 100"C
Operating JunctIOn and Storage Thmperature Range
Lead Temperature (lh6" from case for 10 sec,)
A
120
IDM
Power Dissipation
Unit
TJ, Tstg
-55 to 150
TL
300
"C
Thermal Resistance Ratings
Parameter
Symbol
'JYpical
Maximum
Junction-to-Ambient
R'hJA
75
Junction-to-Case
R'hJC
1.67
Case-to-Sink
P-36683-Rev, C (05/30/94)
R,hCS
Unit
"C/W
1,0
6-1
TEMIC
BUZII
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Test Condition
Symbol
Min
Typ"-
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 'fransconductanceb
V(BR)DSS
VGS = OY, ID = 250!JA
50
VGS(th)
VDS = VGS, ID = 1000!JA
2.1
IGSS
VDS = OY,VGS = ±20V
±100
VOS = 50Y, VGS = OV
250
Vos = 50Y, VGS = OY, TJ = 125'C
1000
loss
VDS = 2Y,VGS = 10V
10(on)
'OS(on)
V
4.0
30
0.030
0.040
VGS = lOY, ID = 15 A, TJ = 125'C
0.045
0.070
VDs=15Y,ID=15A
C;"
Co...
Cr.,
VGS = OY,Vos = 25Y,f= 1 MHz
4.0
"A
A
VGS = 10 Y, ID = 15 A
Sf.
nA
8.0
g
S
Dynamic
Input Capacitance
Output Capacitance
Reverse 'fransfer Capacitance
Thtal Gate ChargeC
Qg
Gate-Source ChargeC
Qgs
Gate-Drain ChargeC
Qgd
linn-On Delay TImec
RiseTImec
Thrn-Off Delay TImec
FallTImec
Vos = 25V;VGS = lOY, ID = 30A
td(o£f)
2000
1000
1100
260
400
52
75
14
Voo = 30 Y, RL = 10 g
10 =3A, VGEN = lOY, RG = 25 g
tf
Source-Drain Diode Ratings and Characteristics (fc .;,
nC
30
45
50
110
100
230
110
170
'S
30
ISM
120
Forward Voltageb
Vso
Reverse Recovery TIme
trr
Reverse Recovery Charge
Q rr
ns
2S'C)
Pulsed Current
CominUOUb Currenl
pF
22
td(on)
tr
1900
A
2.6
IF - 30 A, VGS - OV
IF = 30 A, dlF/dt = 100 NJlS
V
65
ns
0.16
"C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 "S, duty cycle s 2%.
c. Independent of operating temperature.
6-2
P-36683-Rev. C (05/30/94)
TEMIC
BUZII
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
r!
'1
Output Characteristics
50
40
E
"l::
30
'Cie
20
8c
E
7V
20
S
E
6V
S
15
Ci
10
"§
V
10
1
I
5V
V
E
5
o
0
2
4
6
8
10
o
VDS - Drain-la-Source Vollage (V)
'fransconductance
16
e-
0.20
12
.1
0.15
~
"
I
'" 0.10
g
g 0.05
8
0
I
I
"
4
0
0
15
30
45
60
o
75
VGs=10V
-r-
o
25
50
Capacitance
j
4000
G:'
~
,e,
l!
Co
a
2000
~
U
\
1000
o
~
rSl
---
'-.
o
10
20
I
c,,,,_
-
Co..
30
40
VDS - Drain-la-Source Vollage (V)
P-36683-Rev. C (05/30/94)
9
~
c,..
---
125
50
80
100
f
ID = 30A
Ar
12.5
10.0
VDS= 2 5 V /
::s
~~
I
100
Gate Charge
15.0
~
.~
75
ID - Drain Currenl (A)
5000
3000
)
VGS-20V
VGS - Gale-la-Source Vollage (V)
§
10
8
~
C
bO
6
On-Resistance vs. Drain Current
"0
J
4
0.25
8
c
~
2
J
J
'f
VGS - Gale-Io-Source Vollage (V)
20
€
~
4V
0
--- 25'C
125'C
Tc= -55'C
VGS = lO,9,8V
~~
~V
S
'fransfer Characteristics
25
7.5
t!)
5.0
~
2.5
o
I. '/ 40V
F
/
V
o
20
Qg
40
-
60
Thlal Gale Charge (nC)
6-3
TEMIC
BUZII
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
e.
400
1.50
, ./
a~
.ii"B 1.25
:J:l:!
~
,
V
§
1.00
:/
~ 0.75 . /
~
S
V
-10
~
.'-
~
TJ=150'C-
100
~
a
~
=
~
10
"'
/:I
0.50
-50
TJ=25'C
~,
./
8
o:@
Source-Drain Diode Forward Voltage
On-Resistance vs. Junction Temperature
1.75
30
70
1
150
110
I
o
3
2
VSD - Source-to-Drain Voltage (V)
TJ - Junction Temperature ('C)
Thermal Ratings
Maximum Drain Current vs. Case Temperature
30
S
.......
25
C
~
a=
20
Q
,
15
.9
10
'il
51
I
o
25
o
..........
50
~
S
"
I I
75
100
100
,
\.
I
125
I'
......
~,.
"
lO
F
=
i;;gle
1
150
10 ""
100"" -
.9
~
-
~
"
'il
Q
~2
by'DS(on)
J=
\
Safe Operating Area
500
35
- ... -,
~l;
I I I II
IIII
1
Tc - Case Temperature ('C)
10
Jill
-
'l~
IIII
-
10ms
+1,~--,
100
200
VDS - Drain-to-Source Voltage (V)
Normalized Thermal 'fransient Impedance, Junction-to-Case
2
II
Duty Cycle - 0.5
0.2
0.1
... 1-:::::
;;;-
0.05
0.02
~
~J
Single Pulse
0.01
10-5
l/'
I~
lO-4
lO-3
lO-2
lO-l
Square Wave Pulse Duration (sec)
6-4
P-36683-Rev. C (05/30/94)
TEMIC
BUZ71/71A
Siliconix
N-Channel Enhancement-Mode Transistors
Product Summary
Part Number
V(BR)nSS (V)
rnS(on) (Q)
In (A)
BUZ71
50
0.10
14
BUZ71A
50
0.12
13
D
TO-220AB
o
DRAIN connected to TAB
S
GDS
ThpView
N-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Symbol
BUZ71
BUZ71A
Drain-Source Voltage
VDS
50
50
Gate-Source Voltage
VGS
±20
±20
ITc=25·C
Continuous Drain Current
ITc = 100·C
Pulsed Drain Current
ID
IDM
I Tc=25·C
Power Dissipation
.ITc = l00·C
Operating Junction and Storage Thmperature Range
Lead Thmperature (1116" from case for 10 sec.)
Po
Unit
V
14
13
9
8.2
56
48
40
40
16
16
TJ,Tstg
-55 to 150
TL
300
A
W
·C
Thermal Resistance Ratings
Pararneter
Symbol
'JYpical
Maximurn
Junction-to-Ambient
RthJA
75
Junction-to-Case
RthJC
3.1
Case-to-Sink
RthCS
P-36735-Rev. C (05/30/94)
Unit
.C/W
1.0
6-5
TEMIC
BUZ71/71A
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VGS = Ov, 10 = 250 J1A
50
VGS(tb)
Vos = VGs. 10 = 250 J1A
2.1
IGSS
Vos-OV,VGS- ±20V
±100
= 40V,VGS =
250
Vos
Zero Gate Voltage Drain Current
On-State Drain Currentb
loss
10(on)
OV
Vos = 40V,VGS = Ov, TJ = 125'C
Vos = 2V,VGS = 10V
VGS = 10 V, 10 = 6A
Drain-Source On-State Resistanceb
roS(oo)
VGS = 10 V, 10 = 6A
TJ = 125'C
Forward 1tansconductanceb
V
4.0
1000
BUZ71
14
BUZ71A-
13
0.7
0.10
BUZ71A
0.10
0.12
BUZ71
0.13
0.18
0.17
0.20
BUZ71A
VOS = 15 V, 10 = 6A
Output Capacitance
Cos
Co..
VGS = OV,VOS = 25V,f= 1 MHz
Reverse 'fransfer Capacitance
c,...
3.0
J1A
A
BUZ71
gr,
nA
8.0
g
S
Dynamic
Input Capacitance
400
650
150
450
35
280
14
30
10tal Gate ChargeC
Qg
Gate-Source ChargeC
Qgs
Gate-Drain ChargeC
Qgd
4
td(on)
10
30
trr
20
85
Thrn-On Delay TImec
Rise TimeC
Thrn-Off Delay TImec
FaI1TImec
td(olf)
VOS = 25 V, VGS = 10 V, 10 = 13A
Voo = 30 V, RL = 109
10"" 3A, VGEN = 10V, RG = 25g
tl
pF
3
40
90
25
11U
nC
Source-Drain Diode Ratings and Characteristics (Tc = 2S"C)
14
BUZ71
Continuous Current
Pulsed Current
Foward Voltageb
Is
ISM
VSD
Reverse Recovery TIme
In-
Reverse Recovery Charge
Q rr
IF = Is. VGS= OV
IF = Is. dlF/dt = 100 NflS
BUZ71A
13
BUZ71
56
BUZ71A
48
BUZ71
1.8
BUZ71A
2.2
A
V
120
ns
0.5
"C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width :S 300 "". duty cycle :S 2%.
c. Independent of operating temperature.
6-6
P-36735-Rev. C (05/30/94)
TEMIC
BUZ71/71A
Siliconix
TYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
40
~
35
$
30
C
~
25
U
"
20
'eQ
15
..e
10
5
'fransfer Characteristics
30
P' VGS ~ 10,9,8 V
TC~
1/io-"""
7V
f/
,
$
6V
~
C
c
·il
15
Q
5V
125'C
20
a
J. V
~r
J,
,/
10
..e
5
4V
"
oV
o
o
2
4
8
10
o
VDS - Drain-la-Source Voltage (V)
'fransconductance
7.5
F
5.0
I
I
..,"
2.5
o
,
~
I
-55'C
0.20
25'C
I
125'C
&V
B 0.15
.~
~
.
0
0.10
§
~
II
10
15
20
25
0
10
I
200
o
50
40
"a1
=~
=~
60
~~
U tll
Gate Charge
~O
15.0
~
12.5
~
10.0
~
800
U
30
20
1D - Drain Currenl (A)
~
400
20V
0.05
30
.e:
a""
10
0
o
1000
.j
8
-""!VGS
I
Capacitance
600
6
V~"~1
e!.-
.....-::
VGS - Gale-la-Source Vollage (V)
8
4
On-Resistance vs. Drain Cnrrent
Tc~
€
'"""c
~
2
0.25
12.5
10.0
J
I
VGS - Gale-la-Source Voltage (V)
15.0
8
1;
~!-:25'C
-55'C
25
\'
c,,,
0
[/)
!
\'
o
~
C!l
7.5
5.0
I
~ss--
Co"
I
10
30
20
~
40
VDS - Drain-la-Source Voltage (V)
P-36735-Rev. C (05/30/94)
.~
Z
50
2.5
0
0
5
10
15
20
25
Og - Thlal Gale Charge (nC)
6-7
TEMIC
BUZ71/71A
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
/
1.75
e,
~ ~ 1.50
.~ .~
~] 1.25
'"
~
o~
~
1.00
!
.9
0.75
/'
fI
E
S
u
10
1!g
V
/
V
./
II
S
lL
/
_"0
I
Source-Drain Diode Forward Voltage
100
2.00
rn
~
----1
0.50
1
-50 -25
0
25
50
75
100
125
150
- - TJ-150°C
I.
I
TJ = 25°C
I
o
I
2
TJ - Junction Temperature (0C)
5
4
3
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
Maximum Drain Current vs. Case Temperature
15.0 . - - -.....- - - , . - - . - -.....---T'----,
Safe Operating Area
100
12.5 J==~~~:---+---I---+---l
S
S
E
10.0
'"
7.5
~
U
.;
limited
by roS(on)
E
8
Q
I
I
5.0
1-·1
0
50
25
75
I~:::t
=
-
100
125
150
11111
'r-.
~ ."'
.El
2.: I
10""
iciol~1
1ms
.~
Q
.El
' ...
10
....
0.1
Tc - Case Temperature (0C)
Tc 25°C
Single Pulse
I
11111
lOms
lOOms
dc
"
100
10
VDS - Drain-to-Source Voltage (V)
Normalized Thermal 'fransient Impedance, Junction-to-Case
2
II
Duty Cycle
0.5
0.2
-
_io!::
0.1
I"""
0.05
0.02
....-..I'
~ Single Pulse
0.Q1
10-5
6-8
'" "
10-4
10- 3
10-2
10-1
Square Wave Pulse Duration (sec)
P-36735-Rev. C (05/30/94)
TEMIC
BUZ171
Siliconix
P-Channel Enhancement-Mode Transistor
Product Summary
V(BR)nSS (V)
rnS(on) (Q)
In (A)
-50
0.40
-7.0
S
TO·220AB
o
DRAIN connected to TAB
GDS
D
Top View
P-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
-50
Gate-Source Voltage
VGS
±20
ID
-4.5
ITc = 100'C
Pulsed Drain Current'
40
LTC = 25'C
ITc = 100'e
Operating Junction and Storage Temperature Range
Lead Temperature (11t6" from case for 10 sec.)
A
-28
IDM
Power Dissipation
V
-7.0
I Tc=25'C
Continuous Dram Current
Unit
W
PD
16
TJ,T,tg
-55 to 150
TL
300
'c
Thermal Resistance Ratings
Parameter
Symbol
Iypital
Maximum
Junction-la-Ambient
RthJA
75
Junction-la-Case
RthJC
3.1
Case-to-Sink
RthCS
Unit
'e{W
1.0
Notes:
a. Pulse width lImited by maximum junction temperature
P-36731-Rev. D (05/30/94)
6-9
TEMIC
BUZ171
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Min
1YP
Symbol
Test Condition
Max
V(BR)DSS
VGS = 0 Y, 10 = -250!1A
-50
VGS(tb)
VDS = VGS, 10 = -1 rnA
-2.1
IGSS
VDS = OY, VGS = ±20V
±100
VDS = -50, VGS = OV
-250
VDS = -50 Y, VGS = OY, TJ = 125'C
-1000
Unit
Stati~
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistance b
Forward 'Iransconductanceb
loss
-4.0
-7.0
VDS = -lOY, VGS = -10V
VGS = -10 Y, 10 = -4.5 A
0.24
0.40
VGS - -lOY, 10 = -4.5 A, TJ -125'C
0.40
0.72
VDS - -15 Y, 10 - -4.5 A
1.5
nA
"A
A
ID(on)
roS(on)
gr,
V
2.8
g
S
Dynamic
Input Capacitance
C;..
Output Capacitance
Co..
Reverse 'Iransfer Capacitance
c",
1btal Gate Chargee
Qg
Gate-Source Chargee
Qgs
Gate-Drain Chargee
Qgd
Thm-On Delay TImee
RiseTImec
Thrn-Off Delay TImec
FallTImec
VGS = OY, VDS = -25Y, f= 1 MHz
VDS =
-25~
VGS = -lOY, 10 = -7 A
600
1200
325
500
100
230
16
20
3.8
nC
7.5
Id(on)
10
30
tr
50
95
25
90
50
75
td(orf)
pF
VDD = -30Y,RL= 109
10"'" -2.9 A, VGEN = -lOY, RG = 25 g
tr
ns
Source-Drain Diode Ratings and Characteristics (fc "" 2S·C)
's
-7.0
Pulsed Current
ISM
-28
Forward Voltageb
VSD
ContinlJotlS Current
Reverse Recovery TIme
trr
Reverse Recovery Charge
Q rr
-2.8
IF = -7 A, VGS = OV
IF = -7 A, dlF/dt = 100 N",
A
V
70
ns
0.15
!lC
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 "', duty cycle s 2%.
c. Independet of operating temperature.
6-10
P-36731-Rev. D (05/30/94)
TEMIC
BUZ171
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Output Characteristics
10
I/~VVGs=
I
8
;;
~
u
6
'2Q
E
2
o
.IJ
~
Tc= -55"C
4
$
7V
;;
~
"
"
j
3
I
U
.~
6V
Q
V"
2
J
E
5V
~
~'
4V
o
o
2
4
6
8
10
o
'fransconductance
0.5
~
2.0
8
0.4
~
0.3
.~"
'"
'0
1.5
1.0
,.,..,.- /
-
0.2
J
."
0.5
0
2
4
o
10
ID - Drain Current CA)
Capacitance
8
.~"
a
750
€
l"
u
250
o
@
"
r----. I--.
"
I
~
~
'"""'"
o
~
VDs=25V
ID=7A
8
V-
~
\
500
.9
C;"
I"'--I -
Coss
c,..,
;;
"
4
~
2
0
30
40
VDS - Drain-to-Source Voltage (V)
P-36731-Rev. D (05/30/94)
6
C1
20
25
50
V
./
I
0
til
~
10
20
Gate Charge
10
1000
6
15
ID - Drain Current (A)
1250
Ii:'
VGS = WV
0.1
o
0
I
VGS=10V
1=
0
I
bQ
10
On-Resistance vs. Drain Current
2.5
i
8
0.6
€
F
6
VGS - Gate-to-Source Voltage (V)
3.0
8
4
2
VDS - Drain-to-Source Voltage (V)
"
""""
2S;C
125"C
1O,9,8V
IV
~V
$
r
'fransfer Characteristics
I
/
o
/
/
12
16
Qg - Thtal Gate Charge (nC)
6-11
TEMIC
BUZ171
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
~
1.75
e-
I
r-
200
I
VGs= 10V
ID =7A
V
11
; ~ 1.50
.; 1l
~~
.: e 1.25
o~
~ ~ 1.00
e!
0.75
/'
./
V
V
/
~
100
1=
§:
TJ
150°C
;:;
!
"
TJ = 25°C
//
Ifl
~
:l
10
~
'"
i-"
0.50
-50
---
Source-Drain Diode Forward Voltage
On-Resistance vs. Junction Temperature
2.00
I,
-10
70
30
110
o
150
2
TJ - Junction Thmperature (0C)
4
3
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
Maximum Drain Current vs. Case Temperature
Safe Operating Area
100
10
§:
;:;
"t:
6
a
"
Q
---
§:
...........
.........
.;
.9
'" '""
......
4
I
:,
a
,
,
,
,
25
50
75
100
r-
1
150
....
~
by fDS(on)
10
._'"
10"" -
""' -
Illil
r,
.~
lms
Q
I
.9
"
TC = 25°C
I-- Single Pulse
,~
125
Ur:uted
0.5
2
....
.==
'" '" ,'" dc.EEE==
"'
~~~I
-
100 nlS
10
100
200
VDS - Drain-to-Source Voltage (V)
Tc - Case Thmperature CC)
Normalized Thermal Iransient Impedance, Junction-to-Case
2
II
Duty Cycle
0.5
-
0.2
-I-
0.1
0.05
0.02
P
0.01
10-5
jiiI"""
1tiliITif
10-4
10-3
10-2
10- 1
Square Wave Pulse Duration (sec)
6-12
P-36731-Rev. D (05/30/94)
TEMIC
IRF510
Siliconix
N-Channel Enhancement-Mode Transistor
Product Summary
V(BR)OSS (V)
fOS(on) (Q)
10 (A)
100
0.6
4.0
D
TO·220AB
o
Go---l
DRAIN connected to TAB
GDS
S
1bp View
N·Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Gate·Source Voltage
Symbol
limit
Unit
VGS
±20
V
4.0
Tc=25'C
Continuous Drain Current
Tc = 100'C
Pulsed Drain Current
10
2.5
Avalanche Current
L = O.3mH
Repetitive Avalanche Energy"
lAR
4.0
EAR
2.4
Tc = 25'C
Power Dissipation
TC = 100'C
Operating Iunction and Storage Temperature Range
Lead Temperature (1116" from case for 10 sec.)
A
16
10M
mJ
20
Po
W
8
T].T'lg
-55 to 150
TL
300
'C
Thermal Resistance Ratings
Parameter
Symbol
'Jypical
Maximum
RthJA
80
Junction-la-Case
RthJC
6.4
Case-to·Sink
Rthcs
Junction·to-Ambient
Unit
'c/w
1.0
Notes:
a. Duty cycle s 1%
P-35419-Rev. C (05130/94)
6-13
TEMIC
IRF510
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
V(BR)DSS
VGS = OY, 10 = 2501lA
100
VGS(tb)
Vos = VGs. 10 = 250 IlA
2.0
IGSS
Vos = OY, VGS = ±20V
±SOO
Vos - looY, VGS - OV
250
VOS - 80 Y, VGS = 0 Y, TJ - 125'C
1000
Typ"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 1ransconductanceb
loss
Vos = lOY, VGS = 10V
10(en)
'OSten)
4.0
4.0
0.48
0.60
VGS = 10 Y, 10 = 2.0 A, TJ = 12S'C
0.8
1.1
VOS = 15 Y, 10 = 2.0A
1.0
nA
IlA
A
VGS = lOY, 10 = 2.0A
Sfs
V
1.8
Q
S
Dynamic"
Input Capacitance
0"
Output Capacitance
Co"
Reverse Transfer Capacitance
c,,,
10tal Gate Chargee
Qg
Gate-Source Chargee
Q gs
Gate-Drain Chargee
Qgd
Thrn-On Delay TImee
RiseTImec
Thrn-Off Delay TImee
FaIlTImee
VGS = OY,Vos = 25Y,f= 1 MHz
VOS = 50'-:VGS = lOY, 10 = 4A
200
60
100
10
25
7
7.5
1.9
nC
td(en)
7
20
tr
14
25
15
25
9
20
td(elf)
Voo = 40Y, RL = 20Q
10",2.0A, VGEN = lOY, KG = 25 Q
tl
4.0
Pulsed Current
ISM
16
Forward Voltageb
Vso
trr
Reverse Recovery Charge
Q rr
ns
=25'C)
is
Reverse Recovery Time
pF
3.0
Source-Drain Diode Ratings and Characteristics (,fc
Contmuous current
180
2.5
IF- 4A, VGS = OV
IF = 4 A, dlF/dt = 100 N""
A
V
65
ns
0.12
,"C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 ,"S, duty cycle s 2%.
c. Independent of operating temperature.
6-14
P-35419-Rev. C (05/30/94)
TEMIC
IRF510
Siliconix
'IYpical Characteristics (25°C Unless Otherwise Noted)
5
r -__-,r-0_u~tP~u~t_C~hra-ra-c,te-r-is-ti-cs_.----_,
1l-ansfer Characteristics
5.0
4 1------1f---~<+-----± 7 v _1----_1
4.0
S
3 1------1r,~~-----I-----I----_I
C
~
a
.~
3.0
Q
2.0
.E
1.0
5V
4V
oL""""""r"",=""""'=~===~
o
1.0
2.0
3.0
4.0
0
5.0
2
0
VGS - Gate-to-Source Voltage (V)
Vns - Drain-to-Source Voltage (V)
1l-ansconductance
2.5
€
~
tl:s
..,
"
j
.'"
/
2.0
(/
1.5
VI
1.0
Tc= -55°C
i-"'"
125°C
e-
25°C
II
~
1.5
3.0
4.5
6.0
1.5
VGS= 10V
~
'I
o
2.0
.!!l
0.5
o
On-Resistance vs. Drain Current
2.5
V
V
d
0
1.0
I
0.5
0
7.5
J
o
t<;'
\
·i
a-
150
U
o
15
~
12
§
c;,.
..........
~
"
~SJ
o
~
10
20
Coss
30
40
Vns - Drain-to-Source Voltage M
P-35419-Rev. C (05/30/94)
9
12
15
I
In=4.0A
:s
0
til
\
J
75
~
I"
225
VGSr 20V
Gate Charge
18
300
~
6
3
/
In - Drain Current (A)
Capacitance
.e,
--
VV
~
VGS - Gate-ta-Source Voltage (V)
375
10
50
Vns=50V
9
~
~
,O;80V
C!l
6
~
3
0
r
/
o
/
2
6
8
10
12
Og - Thtal Gate Charge (nC)
6-15
TEMIC
IRF510
Siliconix
'J.Ypical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.25
TJ
2.00
OJ
'8
1.75
V
§'"~ 1.50
·ill
!l!'«
,e
Cl
6 1.25
V
I~
g
Source-Drain Diode Forward Voltage
100
1.00
V
§
0.75
~
0.50
-50
-10
30
V
/.
sc
/
I'"
/
:s
U
@
6
10
'"
-
I
I
'"
110
70
TJ = 150'C -
//
"t::
./
25'C
II
o
150
2
TJ - Junction Thmperature ('C)
3
5
4
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
Maximum Avalanche and Drain Current
vs. Case Temperature
Safe Operating Area
50
J
4
.............
S
-=~
3
8
.~
2
Q
I
S
"
10
F=~.""''''
E
u.r:i~T"
by IDS(on)
-=
..........
"'-
.9
~
U
.=
~
-
0.1
25
75
50
100
125
I
"
1 ms I
.9
\
0
100
~ I'......
I
r'\
I
lOJIS
"7
,
~~
Q
'- ,--
lOms
T,.. 25'C
Si~gle Pulse
100 ms
del
II
150
lO
Tc - Case Thmperature ('C)
100
VDS - Drain-to-Source Voltage (V)
Normalized Thermal1l:ansient Impedance, Junction-to-Case
2
IIII
F
DutyCycle
-
0.2
0.5
...
-
0.1
§" 0.05
-
=0.02
0.01
.-
iiiIfIII
~
Pulse
"7 ~';ngle
, '-111111
lO-5
10- 4
10-3
10-2
10- 1
Square Wave Pulse Duration (sec)
6-16
P-35419-Rev. C (05130/94)
TEMIC
IRF520
Siliconix
N-Channel Enhancement-Mode lransistor
Product Summary
V(BR)DSS (V)
rnS(on) (Q)
ID (A)
100
0.3
8.0
D
TO·220AB
o
Go-J
DRAIN connected to TAB
GDS
S
ThpView
N-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Gate-Source Voltage
Tc- 25'C
Continuous Drain Current
Symbol
limit
Unit
VGS
±20
V
In
8.0
Tc: 100'C
Pulsed Drain Current
Avalanche Current
L:03mH
Repetitive Avalanche Energy'
5.0
InM
32
IAR
8.0
EAR
9.6
Tc: 25'C
Power Dissipation
Tc: 100'C
Operating Junction and Storage 'Thmperature Range
Lead 'Thmperature (11r6" from case for 10 sec.)
A
mJ
40
W
Pn
16
TJ,Tstg
-55 to 150
TL
300
'C
Thermal Resistance Ratings
Parameter
Symbol
Junction-ta-Ambient
RthJA
Junction-to-Case
RthJC
Case-ta-Sink
Rthcs
Typical
Maximum
Unit
80
3.12
C'/W
1.0
Notes:
a. Duty cycle :s 1%
P·35419-Rev. C (05/30194)
6·17
TEMIC
IRF520
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
1YP"
'lest Condition
Min
V(BR)DSS
Vas = OY, 10 = 250 (.LA
100
VaS(tb)
Vos = Vas, 10 = 250 (.LA
2_0
lass
Vos = OY, Vas = ±20V
±500
Vos = looY, Vas = OV
250
Vos - SOY, Vas - OY, TJ -l25'C
1000
Max
Unit
Stati~
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 1tansconductanceb
loss
Vos = lOY, Vas = lOV
10(0')
Vas
= lOY, 10 -
S.O
4.0A
roS(on)
Vas = 10 Y, 10 = 4.0 A, TJ = 125'C
gr.
Vos = 15 Y, 10 = 4.0A
4.0
1.5
V
nA
"A
A
0.24
0.30
0.44
0.54
2.9
g
S
Dynamic:"
Input Capacitance
Cu,
Output Capacitance
Cos.
Reverse 1tansfer Capacitance
c,..
Thtal Gate Chargee
Qg
Gate-Source Chargee
Qg.
Gate-Drain Chargee
Qgd
Thrn-On Delay TIme"
RiseTImee
Thrn-Off Delay TImee
FallTImee
Spur~-Draln
Vas = OY, Vos = 25Y,f = 1 MHz
Vos = 50'-: Vas = lOY, 10 = SA
360
600
120
400
15
100
10
15
2.5
nC
5.2
Id(on)
7
40
t,.
30
70
30
100
17
70
Id(off)
pF
10 -
Voo = 40Y,RL = 109
4A, VaEN = lOY, Ra = 25 g
tf
ns
Diode RlItlll3s and Characteristies (Tc =lS·C)
Is
B.O
Pulsed Current
ISM
32
Forward Voltageb
Vso
Continuous Current
Reverse Recovery TIme
trr
Reverse Recovery Charge
Q rr
2.5
IF= SA, Vos = OV
IF = SA, dlF/dt = 100 N"s
A
V
100
ns
0.15
"C
Notes:
a. For design aid only; not SUbject to production testing.
b. Pulse test; pulse width S 300 "'. duty cycle S 2%.
c. Independent of operating temperature.
6-18
P-35419-Rev_ C (05/30/94)
TEMIC
IRF520
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
10
'fransfer Characteristics
10.0
VGs=1O,9,8V
8
8.0
7V
~
C
~
U
C
~
6
6.0
:0
U
"
.~
.~
6V
Q
,E
~
Q
,E
2
4.0
2.0
SV
4V
0
0
0
1.0
2.0
3.0
4.0
S.O
0
Vos - Drain-ta-Source Voltage (V)
3
-g
I
On-Resistance vs. Drain Current
1.0
2
Tc = -SsoC
~
2SoC
8
~
0.6
0
0.4
/.
r;
~
=
I
12SoC
..... V
F:
VGs=lOV
o
o
E
4
8
12
0.2
VGs=20V
0
16
20
o
S
VGS - Gate-to-Source Voltage (V)
~
j
~
.eo
400
U
io=8A
12
~
"
9
t!l
6
200
~
3
o
"
I~ss'o
10
~
c;"
~
Co..
20
30
0
40
VOS - Drain-ta-Source Voltage (V)
P-3S419-Rev. C (OS/30/94)
2S
I
Vos=SOV
0
I
I
20
IS
~
~
600
\.
I
IS
Gate Charge
18
800
·1
10
10 - Drain Current (A)
Capacitance
1000
)
-~, /
I
I
a
10
0.8
€
B
g
8
VGS - Gate-ta-Source Voltage (V)
'fransconductance
S
6
4
2
so
~
£
...Q'80V
r
/
:;
o
3
6
9
12
IS
18
Qg - Thta1 Gate Charge (nC)
6-19
TEMIC
IRF520
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.00
1.75
e.8
.Il
1.25
~O!
./
.. E!
o
~ 1.00
i
0.75
Ie.
~
~
V
./
~
V
~
W
10
"
"
25°C
TJ
0
en
'"
o
-50
H
~
0.50
0.25
TJ = 150°C
c
/'
3~
.~
/
/
1.50
Source-Drain Diode Forward Voltage
100
50
100
o
150
4
3
2
TJ - Junction Thmperature (0C)
5
VSD - Source-ta-Drain Voltage (V)
Thermal Ratings
Maximum Avalanche and Drain Current
vs. Case Temperature
10
8
~
..............
C
~c
6
Cl
4
'f!
I
,g
"" " "-
2
o
Safe Operating Area
100
Limited
by fDS(on)
~
10
"5t::
8
' ....
I
100 JlS
.~
.,'
~
1 ms I
i"iIII ~i'
Cl
t\~
10 JlS
l"-
I
I
10ms
100
,g
f - Tc
25°C
\
0.1
o
25
50
75
100
125
150
10
T c - Case Thmperature CC)
100
VDS - Drain-to-Source Voltage (V)
Normalized Thermal1ransient Impedance, Junction-to-Case
2
I
III
Duty Cycle
0.5
-
0.2
0.1
0.05
".
-~;;;
1"""0.02
.J.I'
~ Single Pulse
, " 1111
0.01
10-5
10-4
10-3
10-2
10-1
Square Wave Pulse Duration (sec)
6-20
P-35419-Rev, C (05/30/94)
TEMIC
IRF530
Siliconix
N -Channel Enhancement-Mode lransistor
Product Summary
V(BR)nSS (V)
rnS(on) (Q)
In (A)
100
0.18
14
D
TO·220AB
o
DRAIN connected to TAB
GDS
S
Top VIew
N-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
Vns
100
Gate-Source Voltage
VGS
±20
Tc: 25'C
Continuous Drain Current
Tc: 100'C
Pulsed Drain Current
L=O.lmH
Repetitive Avalanche Energy'
9.0
TC: 100'C
Operating Junction and Storage Thmperature Range
Lead Thmperature (1116" from ease for 10 sec.)
A
56
IAR
14
EAR
10
Tc: 25'C
Power DIssipation
V
14
In
InM
Avalanche Current
Unit
mJ
75
Pn
W
30
TJ,Tstg
-55 to 150
TL
300
'C
Thermal Resistance Ratings
Parameter
Junction~to-Ambient
Symbol
Iypica\
Maximum
RthJA
80
Junction-ta-Case
RthJC
1.67
Case-to-Sink
RthCS
Unit
'CIW
1.0
Notes:
a. Duty cycle ,,1 %
P-36852-Rev. D (06106/94)
6·21
TEMIC
IRF530
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
1YP"
Test Condition
Min
Max
V(BR)DSS
VGS = Ov, ID = 2501lA
100
VGS(tb)
VDS = VGS, ID = 250 IlA
2.0
IGSS
VDS= OV,VGS = ±20V
±500
VDS = 100 V, VGS = OV
250
VDS = 80 V, VGS = 0 V, Tl = 125'C
1000
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(on)
Drain-Source On-State Resistanceb
Forward 1I'ansconductanceb
'OSCon)
VDS = 10V, VGS = 10V
V
4.0
14
0.13
0.18
VGS = 10V, ID = 8 A, Tl = 125'C
0.24
0.30
VDS = 15 V, ID = 8 A
IlA
A
VGs=10V,ID=8A
!lis
nA
4.0
Q
S
Dynamic
Input Capacitance
C;"
Output Capacitance
Cas,
Reverse Transfer Capacitance
c,."
Thtal Gate ChargeC
Og
Gate-Source ChargeC
Qg,
Gate-Drain ChargeC
Qgd
'fum-On Delay TimeC
RiseTImec
'fum-Off Delay TimeC
Fall Timec
VGS = OV,VDS = 25V,f= 1 MHz
VDS = 50 V, VGS = 10V,ID = 14A
td(oll)
VDD = 100 V, RL = 25 Q
ID = 1.5 A, VGEN = 10 V, RG = 25 Q
tl
Source-Drain Diode Ratings and Characteristics (Tc
800
200
500
40
150
16
30
5
nC
7
30
20
75
20
40
10
45
14
Pulsed Current
ISM
56
Forward Voltageb
VSD
Reverse Recovery Time
Reverse Recovery Charge
trr
Q rr
ns
= 2S·C)
Is
Continuous Current
pF
7
td(on)
t,.
700
A
2.5
IF= 14 A, VGs=OV
IF = 14 A, dlF/dt = 100 N).Is
V
100
ns
0.7
).IC
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width :S 300).lS, duty cycle :S 2%.
c. Independent of operating temperature.
6-22
P-36852-Rev. D (06106/94)
TEMIC
IRF53 0
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
1l-ansfer Characteristics
Output Characteristics
10
15
TJ= -55 o
Cl
.E
~
6V
E
"@
E
6
a
...
4
5V
2
"
6
.E
3
0.4
0
0.8
1.2
1.6
o
2
I
1l-ansconductance
12
9
6
15
On-Resistance vs. Drain Current
0.5
I---~I---~I----
8
Tc
= -55°C
0.4
e!II
11
6
§
4
~
.!!l
0.3
~
<:
0
[!::
0.2
I
e!
I
'"
J
Vas - Gate-to-Source Voltage (V)
10
OIl
J
o
VDS - Drain-to-Source Voltage (V)
~
"""8
25°C
li50C
J
9
is
4V
0
§:
rJ
12
8
~
a
d "1-
2
0
5
0
10
15
20
0.1
0
25
0
10
Vas - Gate-to-Source Voltage (V)
20
Capacitance
Gate Charge
1"
1200
~
~
d
600
@
~
I
U
300
50
15.0
~
900
40
ID - Drain Current (A)
1500
.j
30
§
I
#~
A ~v
VDs=50V
10.0
0
~'iii
C;"
\
~ss
o
o
"
IDI= 13A 1
12.5
Co..
7.5
~
5.0
~
2.5
----
o
10
20
30
40
VDS - Drain-to-Source Voltage (V)
P-36852-Rev. D (06/06/94)
50
/
/
o
L
8
12
16
20
24
Qg - '!btat Gate Charge (nC)
6-23
TEMIC
IRF53 0
Siliconix
1YPical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.25
Source-Drain Diode Forward Voltage
100
e!8
1.75
~'"
/
.~ ~ 1.50
"f e
85
1.25
e
0.75
Ie
! 1.00
25°C
TJ
2.0
~
,.,
V
/
8
~
-10
TJ = 150°C -
/'
I
10
'"
-
I
'"
. . .V
0.50
-50
~
c
V
V
~
~
30
110
70
I
II
o
150
TJ - Junction Thmperature (0C)
2
4
3
VSD - Source-te-Drain Voltage (V)
Thermal Ratings
20
Maximum Avalanche and Drain Current vs.
Case Temperature
Safe Operating Area
100
lOllS
16
~
..............
C
8
12
r-.... .......
c
"e
8
Q
~
"-
I
.9
o
Limited
by IDSion)
c
~
8
"
~.
10
"
.~
,
100,,"
Ims
~.
~
Q
"\
-'roo
I
lOms
I
100 ms
dc =i
I'
I
.9
i== c
25°C
f:= Single Pulse
0.2
o
50
25
75
100
125
10
150
TC - Case Thmperature (0C)
100
VDS - Drain-te-Source Voltage (V)
Normalized Thermal 'Iransient Impedance, Junction-to-Case
2
I I
-
u
e
-0.2
....
0.1
...
=O.U~
=0.02
~
0.01
10-5
,.,..
-Isllerim
10- 4
10-3
10-2
10-1
Square Wave Pulse Duration (sec)
6-24
, P-36852-Rev. D (06/06/94)
TEMIC
IRF540
Siliconix
N -Channel Enhancement Mode Transistor
Product Summary
V(BR)DSS (V)
rDS(on) (Q)
ID (A)
100
0.085
27
o
TO·220AB
o
Go--J
DRAIN connected to TAB
GDS
S
Top VlCW
N-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Symbol
Unit
Limit
Dram-Source Voltage
Vns
100
Gate-Source Voltage
VGS
±20
V
TC = 25°C
Continuous Drain Current
Tc
= 100°C
Pulsed Drain Current
27
In
17
Avalanche Current
L= O.lmH
Repetitive Avalanche Energya
IAR
27
EAR
36
Tc = 100°C
Operating Junction and Storage Thmperature Range
Lead Thmperature (1116" from case for 10 sec.)
mJ
125
Tc=25°C
Power Dissipation
A
108
InM
W
Pn
50
TJ. Tstg
-55 to 150
TL
300
°C
Thermal Resistance Ratings
Parameter
Symbol
'JYpical
Maximum
Junction-ta-Ambient
RthJA
80
Junction-to-Case
RthJC
1.0
Case-to-Sink
RthCS
Unit
°C{W
1.0
Notes:
a. Duty cycle s 1%
P-36853-Rev. D (06/06/94)
6-25
TEMIC
IRF540
Specifications (TJ
Parameter
Siliconix
= 25°C Unless Otherwise Noted)
Symbol
Test Condition
Min
V(BR)DSS
VGS = Ov, ID = 2S01lA
100
VGS(th)
VDS = VGS,ID = 250 IlA
2.0
IGSS
VDS = Ov, VGS = ±20V
±SOO
VDS -looV, VGS - OV
250
VDS - 80 V, VGS - Ov, T1 = 12S"C
1000
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(on)
Drain~Source On-State Resistanceb
Forward'll-ansconductanoeb
roS(on)
VDS = 10 V, VGS = 10V
V
4.0
27
0.50
0.085
VGS = 10V, ID = 15 A, TJ = 125"C
0.10
0.15
VDS = 15V,ID = 15A
Output Capacitanoe
C;"
Cos.
VGS = Ov, VDS = 25 V, f= 1 MHz
Reverse 'll-ansfer Capacitanoe
c,,,
6.0
IlA
A
V GS - 10 V, ID - 15 A
gr.
nA
8
Q
S
Dynamic
Input Capacitanoe
1500
1600
480
800
110
200
38
60
'IOta! Gate ChargeC
Og
Gate-Souroe ChargeC
Qgs
Gate-Drain ChargeC
Qgd
111m-On Delay TImeC
td(on)
10
30
tr
40
60
30
80
12
30
RiseTImec
111m-Off Delay TImec
Fa!ITImec
td(off)
VDS = 50V;VGS = 10 V, ID = 27 A
10
pF
nC
17
VDD = 30V,RL = 2Q
ID = 15 A, VGEN = 10 V, RG = 4.7Q
tf
ns
Source-Drain Diode Ratings and Characteristits (fc = 2s oq
I:;
27
Pulsed Current
ISM
108
Forward Voltageb
VSD
Reverse Recovery TIme
t"
Q rr
C'.ontinnnnc:. 01rrpnt
A
Reverse Recovery Charge
2.5
IF=27 A, VGS =OV
IF = 27 A, dlp/dt = 100 NilS
V
150
ns
0.5
IlC
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width S 300 !Is, duty cycle S 2%.
c. Independent of operating temperature.
6-26
P-36853-Rev. 0 (06/06/94)
TEMIC
IRF540
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
II
/, j/
II!V
Output Characteristics
50
:s;;;
e
a
"
·01
IS
40
30
20
18V
:s;;;
7V-
10
u
40
t::
30
"
20
8
.~
Q
~
I
.E
VGs;1O.9V
'ftansfer Characteristics
50
16V
.E
I
V
10
5V
4V
0
4
0
6
0
10
8
2
0
Vns - Drain-lo-Source Voltage (V)
'ftansconductance
20
0.08
a
F:"
~
1l
Tc; -5S·C
12
le
"C
8"
8
2S·C
i-"""'"
J--
I(
o
o
10
20
30
40
VGS; lOV
B
0.06
0
0.04
e!
0.02
~i:
12S·C
f'
/
I
""'"
o
50
~--- ../V
VGS;20V -
o
25
VGS - Gale-lo-Source Vollage (V)
~
1"
fi:'
~
C 2000
1000
500
o
11
10
en
1
'iii
30
~
40
Vns - Drain-lo-Source Voltage (V)
P-368S3-Rev. D (06/06194)
150
Ii r
10.0
vns;sovf
7.5
//80V
I
5.0
I
I
20
125
50
f
J
In ;27A
12.5
0
Cl
~
o
"
c,,,
Ce"
100
Gate Charge
15.0
j
1a 1500 ~
\
75
In - Drain Currenl (A)
2500
I
50
Capacitance
3000
U
10
On-Resistance vs_ Drain Current
0.10
16
€
i"
8
VGS - Gale-lo-Source Vollage (V)
2.5
I
t·
0 0
20
Qg
40
-
60
80
Thlal Gale Charge (nC)
6-27
TEMIC
IRF540
Siliconix
'IYPical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
~
2.25
200
2.20
100
/
C!
'8 1.75
B:;;-
/
~
'~.1:1 1.50
~OI
8~ 1.25
~
I~
g
1.00
g
0.75
".
V
~
~
Source-Drain Diode Forward Voltage
. /~
150°C
I- TJ
/
a
V
II
@
"
'"
10
0
-
I
1
-10
70
30
TJ = 25°C
"'
",
0.50
-50
"
150
110
I
o
2
TJ - Junction Thmperature (0C)
4
3
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
Maximum Avalanche and Drain Current
vs. Case Temperature
30
~
25
........
'"
~
8"
20
'Qe"
15
I
10
.9
~
100
so
25
"'- .......
a
~
~
I
100
125
lOI'S
by fDS(oo)
t:
"\
75
Umited
~
,,;
......... ~.
10
.9
I'
1001'S
"
1ms
FI I III IIII
-
:I I I I I I ~
o
Safe Operating Area
500
Tc
2SOC
I
Smgle Pulse
1
10
150
TC - Case Temperature (0C)
VDS - Drain-to-Source Voltage (V)
Normalized Thermal1i'ansient Impedance, Junction-to.Case
2
= DutyCycle
-
=
IIII
~
0.5
0.2
_........
0.1
0.05
~
- 0.02
~
V
_
0.001 10 5
io-"
Single Pulse
11'111
10-4
10-3
10-2
10- 1
Square WlWe Pulse Duration (sec)
6-28
P-368S3-Rev. D (06/06/94)
TEMIC
IRF9530
Siliconix
P-Channel Enhancement-Mode fiansistor
Product Summary
V(BR)nSS (V)
fnS(on) (Q)
In (A)
-100
0.30
-12
S
TO·220AB
o
DRAIN connected to TAB
GDS
D
ThpView
P·Channel MOSFET
Absolute Maximum Ratings (Tc
= 25°C Unless Otherwise Noted)
Parameter
Symbol
Umlt
Drain-Source Voltage
VOS
-100
Gate-Source Voltage
VGS
±20
V
-12
Tc=2S'C
Continuous Drain Current (TJ = 150'C)
TC = 100'C
Pulsed Drain Current
Avalanche Current
Repetitive Avalanche Energy'
L=O.lmH
10
-7.5
10M
-48
IAR
-12
EAR
7.2
Tc=25'C
Maximum Power Dissipation
Tc = l00'C
Operating Junction and Storage Temperature Range
Lead Thmperature eh6" from case for 10 sec.)
Unit
A
mJ
75
W
Po
30
TJ,T,tg
-55 to 150
TL
300
'C
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient
Symbol
Maximum Junction-to-Case
RtbJC
RthCS
Maximum
Unit
80
RtbJA
Case-to-Sink
Notes:
a. Duty cycle
lYPical
1.67
'CIW
1.0
s 1%
P-36852-Rev. D (06/06/94)
6·29
TEMIC
IRF9530
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Limit
Parameter
Symbol
Min
lest Condition
1Yl'"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VGS = 0 V, ID = -250
VGS(th)
VDS = VGs.ID = -250
IGSS
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(on)
Drain-Source On-State Resistance b
Forward'Iransconductanceb
l'DS(on)
8/.
I1A
I1A
-100
-2.0
-4.0
VDS=OV,VGS= ±20V
±500
VDS = -100V,VGS = OV
-250
VDS = -80 V, VGS - Ov, Tr = 125'C
-1000
VDS - -10V, VGS - -10V
-12
0.25
0.30
VGS = -10V,ID = -7.5 A, Tr = 125'C
0.40
0.48
2.0
nA
I1A
A
VGS - -10 V, ID - -7.5 A
VDS = -15 V, ID = -7.5 A
V
3.2
Q
S
Dynamic
Input Capacitance
Cj"
Output Capacitance
Co..
Reverse 'Iransfer Capacitance
Cr..
Thtal Gate ChargeC
Og
Gate-Source ChargeC
Ogs
Gate-Drain ChargeC
Ogd
'nun-On Delay TImec
RiseTImec
Thrn-Off Delay TImeC
FallTImec
625
VGS = OV,VDS = -25 V, f= 1 MHz
VDS= -80 V, VGS= -10V,ID = -12A
td(oll)
450
105
200
26
45
3.4
pF
nC
13.5
td(on)
t,
700
280
VDD = -40 V, RL = 3.3Q
ID" -12 A, VGEN = -10V, RG = 2sQ
If
9
60
SO
140
60
140
40
140
ns
Source-Drain Diode Ratings and Characteristics
Is
-12
Pulsed Current
ISM
-48
Diode Forward Voltageb
VSD
Reverse Recovery TIme
tIT
Reverse Recovery Charge
0"
Continuous Current
A
-2.0
IF--12A,VGS-OV
IF = -12A, dildt = 100 NIlS
V
110
ns
0.4
"C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width S 300 lIS. duty cycle S 2%.
c. Independent of operating temperature.
6-30
P-368s2-Rev.D (06/06/94)
TEMIC
IRF9530
Siliconix
1Ypical Characteristics (25°C Unless Othemise Noted)
Negative signs omitted for clarity.
Output Characteristics
12.5
'Iransfer Characteristics
10
BV
B
10.0
§:
7V
"
~c
7.5
'2
5.0
.E
2.5
Q
6V
5V
2
4V
o
0
0
4
2
B
6
o
10
6
8
10
VGS - Gate-to-Source Voltage (V)
'Iransconductance
5
4
2
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
1.0
I
Tc= -55'C
",
€
!"
I
3
'"c
~
V
8c
O.B
5
0.6
<:
0.4
'5I>:
125'C
"
2
F:"
e.
25'C
0
'8
I
"
§
OIl
I
r-.-:V
5
0
10
15
20
o
25
10
= OV
E
12.5
~
10.0
"
~
7.5
"
5.0
g"
2000
~
Il
1500
I
iD= 12A
~
~
1000
I
\
500
o
OJ
Co"
~
~ ::-10
20
40
VDS - Drain-ta-Source Voltage (V)
P-36852-Rev. D (06/06/94)
2.5
o
30
40
50
50
40
50
!If
VG~= 50V ' /
0
J
30
Gate Charge
15.0
I
VGS
20
iD - Drain Current (A)
Capacitance
2500
o
--~
0.2
iD - Drain Current (A)
U
20V
o
0
j
~
/i
80 V
I
1/
1/
o
10
20
30
Og - 10tal Gate Charge (nC)
6-31
TEMIC
IRF9530
Siliconix
'fYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
On-Resistance vs. Junction Temperature
2.00
~
e~
l!!"
1.50
.~ .~
~] 1.25
=~
V
o~
I ~ 1.00
J
0.75
./
/
V
§:
,..-
~
~
~
TJ
150'C-
/
10
'"
V
I
o
0.50
-50
t 25,J~
100
v
1.75
Source-Drain Diode Forward Voltage
200
-10
30
110
70
150
o
II
2
5
3
Vsn - Source-to-Drain Voltage (V)
TJ - Junction Thmperature ('C)
Thermal Ratings
125
§:
8"
100
Maximum Avalanche and Drain Current
vs. Case Temperature
---
............
"" ~
.~
Q
5.0
I
.£l
2.5
§:
"\ ,
0
o
25
I III I
100
.......
7.5
Safe Operating Area
200
50
75
100
125
150
I-- Umitedby
I- 'DS(on)
~
....
"
~"
.~
~
II
10JIS
=
I
i.
1OOJlS
Ims ::
10
~
1I 1Oms
lOOms
I
.£l
1
-
Tc 25°C
Single Pulse
de ::l=l=
lrlllllill
11I1111111
10
100
2
Tc - Case Thmperature ('C)
m
500
VDS - Drain-ta-Source Voltage (V)
Normalized Thermal1ransient Impedance, Junction-to-Case
2
II
Duty Cycle
0.5
0.2
~
0.1
0.05
-
0.02
?
0.01
10-5
6-32
~
Single Pulse
I I-I IIIII
10- 4
10-2
10- 3
Square Wave Pulse Duration (sec)
10- 1
3
P-36852-Rev. D (06/06/94)
TEMIC
IRFD020
Siliconix
N-Channel Enhancement-Mode Transistor
Product Summary
V(DR)DSS (V)
rDS(on)
50
(Q)
0.10
ID (A)
2.4
D D
4-Pin DIP
G
D
S
ThpView
S
N-Channel MOSFET
Absolute Maximum Ratings (TA
= 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
SO
Gate-Source Voltage
Vas
±20
Unit
V
ITA
Continuous Drain Current
= 25'C
2.4
ID
ITA= 100'C
Pulsed Drain Current
IDM
ITA = 100'C
Operating Junction and Storage Thmperature Range
Lead Thmperature eh6" from case for 10 sec.)
A
19
1.0
ITA=25'C
Power Dissipation
1.5
Po
W
0.40
TJ,T,tg
-55 to 150
TL
300
Symbol
Maximum
Unit
RthJA
120
'c/w
'C
Thermal Resistance Ratings
Parameter
Junction·to-Ambient
P-36852-Rev. D (06/06/94)
6-33
TEMIC
IRFD020
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
lYJI"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 1tansoonductanceb
V(BR)DSS
VGS = O\1,ID = 250 "A
50
VGS(th)
VDS - VGS. ID = 250 J1A
2.0
IGSS
VDS = 0\1, VGS = ±20V
±5oo
VDS = 40\1, VGS = OV
250
IDSS
ID(on)
TDS(on)
Sf,
VDS = 40\1, VGS =
V
4.0
o\1, TJ = 125'C
VDs-2\1,VGs=10V
1000
2.4
0.08
0.10
VGS = 10 \1, ID = 1.4 A, Tr = 125'C
0.16
0.18
4.9
"A
A
VGS -10\1, ID = 1.4 A
VDS = 15\1, ID = 7.5 A
nA
5.5
Q
S
Dynamic
Input Capacitance
C;ss
Output Capacitance
Cess
Reverse Transfer Capacitance
c'ss
VGS = O\1,VDS = 25\1,f= 1 MHz
550
850
300
350
80
100
13
24
Thtal Gate ChargeC
Og
Gate-Source ChargeC
Ogs
Gate-Drain ChargeC
Ogd
5
Thrn-On Delay TImec
td(on)
10
13
tr
60
83
30
40
35
50
RiseTImec
Thrn-Off Delay TImec
FailTImec
lcI(of£)
VDS = 25 V; VGS = 10\1, ID = 15 A
VDD = 25\1, RL = 1.7Q
ID",,15 A, VGEN = 10\1,RG = 18Q
tf
3.5
pF
nC
ns
Source-Drain Diode Ratings and Characteristics (fi = 2S"C)
is
2.4
Pulsed Current
ISM
19
Forward Voltageb
VSD
Contmuous Current
Reverse Reoovery TIme
trr
Reverse Reoovery Charge
Orr
A
IF = 2.4 A, VGS
= OV
1.25
65
IF = 2.4 A, dlF/dt = 100 N"s
0.16
V
ns
0.85
"C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300!'S. duty cycle S 2%.
c. Independent of operating temperature.
6-34
P-36852-Rev. D (06/06/94)
TEMIC
IRFD020
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
30
25
~
-a
15
Q
VGS = lO,9V
10
125'C
~
7V
-a
~
:s
U
6V -
.~
Q
5V
5
.E
J
7.5
I
5.0
~
2.5
4V -
o
o
4
2
6
8
10
o
VDS - Drain-to-Source Voltage (V)
~
2
4
I-----'I----jl----jf- Tc = -5S'C
10
On-Resistance vs_ Drain Current
0.150
~
€
0.125
~
~
0.100
VGS= 10V
g
.~
1
1
0.075
VGS-20V
0
F
I
I
!
e
o
L-_~~_~~~~
o
5
10
__
15
~
__
20
~
0.050
0.025
0
25
0
10
VGS - Gate-to-Source Voltage (V)
Capacitance
g"
1200
~
@
900
·i
a ~ r-..
I
300
o
25
\'
o
'"
i'--
l
Co., -
~
t
10
20
30
40
VDS - Drain-ta-Source Voltage (V)
P-36852-Rev. D (06/06/94)
.~
10.0
7.5
0
5.0
~
2.5
'iii
a
50
=~
=~
~~
Z
12.5
1
4)
~O
6
C;ss-
-
Uri.!
Gate Charge
G:'
6
U
20
15.0
~
600
15
ID - Drain Current (A)
1500
~
6
VGS - Gate-to-Source Voltage (V)
'fransconductance
10,..-----,---,---,---,----,
8
If..-- 25'C
10.0
~
o~
.E
Tc= -S5'C
8V
II '1/
Vb ~
~
.~
/
///
20
:s
U
'fransfer Characteristics
12.5
/
0
5
10
15
20
25
Qg - Thtal Gate Charge (nC)
6-35
TEMIC
IRFD020
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Source-Drain Diode Forward Voltage
On-Resistance vs. Junction Temperature
1.75
100
25'C
TJ
~
/
1.50
8
tii~
.~] 1.25
&loa
=E
o1 ~ 1.00
~
I
0.75 ~
0.50
-50
V
V
i-"
./
TJ = 150'C
:sE
/'
/"
A
~
a
§
:s
/1
10
0
til
,
1
-
I
I
"'
-10
110
70
30
1
150
=
II
o
TJ - Junction Thmperature ('C)
2
3
5
4
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
Maximum Drain Current vs. Ambient Temperature
i---
:s
"
2.0
E
~
~
........
"'" \ ,
1.5
1.0
I
.9
0.5
o
o
........
:s
Limited
by rnS(on)
10
~
a
i-"
~~""
;'
-,
g"
!
.9
Ims
i.ii'ms
lOOms
""
I!!!!
0.1
F
1==
O.ot
TA-25'C
Single Pulse
I 1-,111111
~,,-
0.005
25
50
75
100
125
TA - Ambient Temperature ('C)
6-36
Safe Operating Area
100
2.5
150
0.1
10
100 200
VDS - Drain-to-Source Voltage (V)
P-36852-Rcv. D (06/06/94)
TEMIC
IRFDII0
Siliconix
N -Channel Enhancement-Mode lransistor
Product Summary
V(BR)nSS (V)
rnS(on) (Q)
In (A)
100
0.60
1.0
D D
4-Pin DIP
G
G~
D
S
Top View
S
N-Channel MOSFET
Absolute Maximum Ratings (TA
= 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
100
Gate-Source Voltage
VGS
±20
ITA~25'C
Continuous Drain Current
ITA~ 100'C
Pulsed Drain Current
ITA~25'C
ITA~ 100'C
Operating Junction and Storage Thmperature Range
Lead Temperature eh6" from case for 10 sec.)
V
1.0
ID
IDM
Power Dissipation
Unit
0.6
A
8.0
1.0
PD
0.4
W
T], Tstg
-55 to 150
TL
300
Symbol
Maximum
Unit
RthIA
120
'c/w
'C
Thermal Resistance Ratings
Parameter
Junction-to-Ambient
P-36735-Rev. C (05/30/94)
6-37
TEMIC
IRFDII0
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Thst Condition
Min
= Ov, 10 = 250llA
= YGs. 10 = 250 I1A
100
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VGS
VGS(tb)
Yos
IGSS
Zero Gate Voltage Drain Current
losS
On-State Drain Currentb
IO(on)
Drain-Source On-State Resistanceb
Forward Transconductanceb
1"))5(on)
Sf,
V
2.0
4.0
VOS - Ov, VGS - ±20V
±5oo
VOS -100V,VGS - OV
250
Vos = so V, VGS
= Ov, Tl = 125'C
Vos = 10 V, VGS = lOV
VGS = 10 V, 10 = O.SA
VGS = 10 V, 10 = O.S A, Tl = 125'C
VOS = 15 V, 10 = 0.8 A
1000
1.00
O.S
nA
I1A
A
0.5
0.60
0.8
1.0
1.5
0
S
Dynamle
Input Capacitance
Output Capacitance
C;"
Co..
Reverse 'Iran.fer Capacitance
c...
Thtal Gate ChargeC
Og
Gate-Source ChargeC
Ogs
Gate-Drain ChargeC
Ogd
Thrn-On Delay TimeC
RiseTImec
Thrn-Off Delay Timec
Fall Timec
VGS
= Ov, VOS = 25 V, f = 1 MHz
Vos
= 50 V, VGS = 10V,Io = 1 A
td(off)
200
60
100
10
25
6
7.0
1.5
pF
nC
3.0
td(on)
tr
lS0
Voo = 40V,RL = 500
10 ""O.SA, YGEN = 10 V, RG = 25'-1
tf
7
20
10
25
13
25
9
20
ns
S()urce-Drain Diode Ratings and Characteristics (fA = :tli°C)
Continuous Current
Is
1.0
Pulsed Current
ISM
8.0
Forward Yoltageb
Vso
Reverse Recovery Time
trr
Reverse Recovery Charge
Orr
IF
IF
= LOA, YGS = OY
= 1.0 A, dlF/dt = 100 NIlS
2.5
A
V
45
DS
0.25
IIC
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width S 300 1lS. duty cycle S 2%.
c. Independent of operating temperature.
6-38
P-36735-Rev. C (05/30/94)
TEMIC
IRFDII0
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
5
'Ibnsfer Characteristics
5.0
Vas = 10,9,8 V
""
3
Ci
2
~
U
·il
"
4.0
7V
~
~
E
~
3.0
"
U
·il
6V
"
2.0
.E
1.0
Ci
.E
5V
4V
0
0
0
1.0
2.0
3.0
4.0
5.0
0
2
1l:ansconductance
,/
2.0
€
(/
8
!ii
g
1.5
V/
"0
"
~
1.0
Tc= -55°C
I
e~
25°C
I
125°C
o
~0
J
1.5
3.0
4.5
6.0
2.0
Vas=10V
1.5
.!!l
"""'"
0.5
o
On-Resistance vs_ Drain Current
2.5
'I
F:
"""
V
V
~
-
0.5
0
7.5
o
6
Capacitance
"
.~
a-
lSO
~
§
c...
""""-.
U
75
o
Vns=50V
12
"0
"
u
;;
10
20
~
Co..
30
40
Vns - Drain-to-Source Voltage (V)
P-36735-Rev. C (05/30/94)
50
.D
r
c:l
""""'-
15
In= 4.0A
15
.9
c,j
12
I
(J)
\
I
o
9
E
Ii:'
5"
VaSj20V -
Gate Charge
18
E
.\
/
In - Drain Current (A)
300
,e,
8 225
v.V
J
1.0
Vas - Gate-to-Source Voltage (V)
375
10
Vas - Gate-to-Source Voltage (V)
Vns - Drain-to-Source Voltage (V)
2.5
8
4
3
0
/
o
~
~80V
/
2
4
6
8
10
12
Qg - Total Gate Charge (nC)
6-39
TEMIC
IRFDII0
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.8
Source-Drain Diode Forward Voltage
100
25'C
TJ
2.4
~
0.4
o
~
o
-60
./
V
/
S
~
~
"a
TJ
A'
lS0'C-
~
c
/
10
til
'"
60
120
II
o
180
2
3
4
S
VSD - Source-to-Drain Voltage (V)
TJ - Junction Thmperature ('C)
Thermal Ratings
1.2
Maximum Drain Current vs. Case Temperature
10
1.0
S
C
~
"
.............
0.8
...........
0.6
...........
0.4
.El
~
0.2
25
50
75
100
Tc - Case Temperature ('C)
6-40
lOOi
by'l:lS(on)
C
."
'
~
...........
.............
o
S
~IRFDll0 -
.~
o
lO~1
II 11111
Umiled
0
I
Safe Operating Area
20
10ms
'a"
,
~
125
150
Ci
I
t
II
Ims
lOOms
0.1
.El
Tc
2S'C
Sinl~~~ Pulse
dc
0.01
0.005
0.2
10
100
=
200
VDS - Drain-la-Source Vollage (V)
P-36735-Rev. C (OS/30/94)
TEMIC
IRFD120/123
Siliconix
N-Channel Enhancement-Mode 'fransistors
Product Summary
Part Number
V(BR)nSS (V)
rnS(on) (Q)
In (A)
IRFD120
100
0.3
1.3
IRFD123
60
0.4
1.1
D D
4-Pin DIP
G
D
S
Top View
S
N-Channel MOSFET
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Symbol
IRFD120
IRFD123
Drain-Source Voltage
VDS
100
60
Gate-Source Voltage
Vas
±20
±20
ITA; 25"C
Continuous Drain Current
ITA= 100"C
Pulsed Drain Current
ID
IDM
ITA=25"C
Power Dissipation
PD
ITA =l00"C
Operating Junction and Storage Thmperature Range
Lead Thmperature eh6" from case for 10 sec.)
1.3
1.1
0.8
0.7
5.2
4.4
1.0
1.0
0.4
0.4
Unit
V
A
W
TJ,T,tg
-55 to 150
TL
300
Symbol
Maximum
Unit
RthJA
120
"C/W
"C
Thermal Resistance Ratings
Parameter
Junction-to-Ambient
P-36852-Rev. D (06/06/94)
6-41
TEMIC
IRFD120/123
Specifications (TJ
Parameter
Siliconix
= 25°C Unless Otherwise Noted)
Symbol
Test Condition
Min
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
IRFD120
IRFDl23
Vos = Vas, 10 = 250 IlA
VaS(th)
loss
On-State Drain Currentb
10(on)
±500
250
Vos = 0.8 x V(BR)DSS, Vas = ov, TJ = 125'C
1000
Vos = 10V, Vas = lOV
fDS(on)
Vas = 10 V, 10 = 0.6 A, TJ = 125'C
Forward 1l"ansconductanceb
V
4.0
Vos = Ov, Vas = ±20V
Vas = 10V,lo = 0.6 A
Drain-Source On-State Resistance b
60
2.0
Vos = V(BR)DSS, Vas = OV
loss
Zero Gate Voltage Drain Current
100
Vas = ov, 10 = 2501lA
V(BR)DSS
IRFD120
1.3
IRFD123
1.1
0.22
0.30
IRFD123
0.30
0040
IRFD120
0.4
0.60
IRFD123
0.6
0.80
1.6
Vos = 15 V, 10 = 0.6 A
C;"
Co.,
Crss
Vas = OV,Vos = 25V,f= 1 MHz
IlA
A
IRFD120
Sf,
nA
0
S
Dynamic
Input Capacitance
Output Capacitance
Reverse 1l"ansfer Capacitance
Thtal Gate ChargeC
Og
Gate-Source ChargeC
Ogs
Gate-Drain ChargeC
Ogd
Thrn-On Delay TImec
RiseTImec
Thrn-Off Delay TImec
FallTImec
360
Pulsed Current
Forward Voltageb
10
Vos = 0.5 x V(BR)OSS. Vas = 10 V, 10 = 1.3 A
tr
Id(off)
Voo = 50 V, RL = 800
10 Q!.0.6 A, VaEN = 10 V, Ra = 25 0
tf
7
40
70
20
100
10
70
ISM
trr
Orr
no
= 25'C)
IRFD120
Reverse Recovery TIme
nC
20
1.3
Is
Vso
15
2.4
5.1
td(on)
Reverse Recovery Charge
pF
15
Source-Drain Diode Ratings and Characteristics ('fA
Continuous Current
120
Ip=Is,Vas=OV
IF = Is, dlp/dt = 100 NIlS
IRFD123
1.1
IRFD120
5.2
IRFD123
4.4
IRFD120
2.5
IRFD123
2.3
A
V
100
ns
0.15
!,C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 !,s, duty cycle S 2%.
c. Independent of operating temperature.
6-42
P-36852-Rev. D (06/06/94)
TEMIC
IRFD120/123
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
10
'Iransfer Characteristics
10.0
Vas=lO,9,8V
8.0
8
7V
~
~
...
;;
~
U
~
6
"
4
E
2
8
"
.;;
0
.~
6V
Cl
E
5V
4V
0
1.0
0
2.0
3.0
6.0
4.0
2.0
0
4.0
0
5.0
'Iransconductance
3
"C
"
~
F<
e.
Tc= -55'C
8
~
"
2
I
'"
co
o
/
25'C -
((;
I
125'C
0.8
g
~
0.6
~
=
0.4
0
V
o
Vas = lOV
I
8
12
16
0.2
Vas
0
20
5
Capacitance
a
15
~
12
!!
"
600
0
til
400
I
U
200
0
~
o
10
!
Ctss
~ss~
c""
20
30
40
Vns - Drain-to-Source Voltage (V)
P-36852-Rev. D (06/06/94)
20
-
25
Q,l
=~
=~
.!~
50
U
Z
9
(!)
6
~
3
0
0
3
6
Qg
-
9
OO
~O
.:;g
In = Maximum Continuous
~
5'"
,\.
15
Gate Charge
18
~
Q,
10
In - Drain Current (A)
800
.~
20V
I
0
Vas - Gate-to-Source Voltage (V)
1000
/
--
V
-..---- V
I
4
6
On-Resistance vs. Drain Current
1.0
4
€
4
Vas - Gale-lo-Source Voltage (V)
Vns - Drain-to-Source Voltage (V)
5
2
12
15
18
Thtal Gate Charge (nC)
6-43
TEMIC
IRFD120/123
Siliconix
'JYpical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.00
1.75
~
8
/
1.50
g~
111.25
./
~ 11.00
J
0.75 " ,
./
/'
Source-Drain Diode Forward Voltage
100
/
g
Tl=150 D C§
c
./
1/
8
§
~
"
10
Tl=2S D C
...'"
0.50
0.25
1
o
-50
50
100
150
o
Tl - Junction Temperature (DC)
3
2
4
5
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
Maximum Drain Current
vs. Ambient Temperature
1.6
Safe Operating Area
10
lOOjJS
1.3
C
1.0
c
a
0.7
a
~
.~
K, 'ut:ut~1'IJ
g
g
by roS(on)
"
~
'Q2
0
I
I
oS
oS
1 ms
I
10ms
lool~
0.1
TA 2S D C
, ,~ingle Pulse
dc=
0,01
0.005
o
25
50
75
100
125
TA - Ambient Temperature (DC)
6-44
150
0.5
10
100
500
VDS - Drain-to-Source Voltage (V)
P-368S2-Rev. D (06106/94)
TEMIC
IRFD9020
Siliconix
P-Channel Enhancement-Mode Thansistor
Product Summary
V(BR)nSS (V)
rnS(on) (Q)
In (A)
-50
0.28
-1.6
S
4-PinDIP
Top View
D D
P-Channel MOSFET
Absolute Maximum Ratings (TA
= 25°C Unless Otherwise Noted)
Symbol
Parameter
Limit
Drain-Source Voltage
Vos
-50
Gate-Source Voltage
VGS
±20
10
ITA= 100'C
Pulsed Drain Current
10M
ITA= 100'C
Operating Junction and Storage Temperature Range
Lead'Thmperature eh6" from case for 10 sec.)
-1.0
A
-13
1.0
ITA = 25'C
Power Dissipation
V
-1.6
ITA = 25'C
Continuous Drain Current
Unit
Po
0.40
W
TJ,T,tg
-55 to 150
TL
300
Symbol
Maximum
Unit
RtbJA
120
0c/w
'C
Thermal Resistance Ratings
Parameter
Junction-ta-Ambient
P-36852-Rev. D (06/06/94)
6-45
TEMIC
IRFD9020
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
'IyP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 'fransconductanceb
V(BR)OSS
VGS = Ov, 10 = -250 f1A
-50
VGS(th)
Vos = VGs. 10 = -250 f1A
-2.0
IGSS
Vos-OV,VGs= ±20V
±500
Vos = -50 V, VGS = OV
-250
loss
V
-4.0
-1000
Vos = -40 V, VGS = 0 V, TJ = 125'C
Vos= -2 V, VGS= -10V
lo(on)
roS(a.)
-1.6
0.24
0.28
VGS - -10 V, 10 - -1.1 A, TJ -125'C
0.40
0.50
Vos = -15 V, 10 - -1.1 A
c,..
Ca.,
c",
VGS = Ov, Vos = -25 V, f= 1 MHz
1.0
f1A
A
VGs= -10 V, 10 = -1.1 A
!!I,
nA
1.4
0
S
Dynamic
Input Capacitance
Output Capacitance
Reverse 'fransfer Capacitance
Thtal Gate ChargeC
Qg
Gate-Source ChargeC
Qg,
Gate-Drain ChargeC
Qgd
Thrn-On Delay TImec
RiseTImec
Thrn-Off Delay TImeC
FaIlTImec
VOS = -25
v: VGS = -10 V, 10 = -1.6 A
530
600
325
350
85
100
16
26
2.8
nC
5.0
td(aa)
10
12
t,
80
86
25
35
50
60
Voo = -25 V, RL= 150
10"" -1.6 A, VGEN = -lOV,RG = 180
td(alf)
tf
Source-Drain Diode Ratings And Characteristics
=
. Is
-1.6
ISM
-13
Forward Voltageb
Vso
c.urrent
Reverse Recovery Time
trr
Reverse Recovery Charge
Q rr
ns
CfA 2SQC)
Pulsed Current
('nr.tinnnu~
pF
-6.3
IF = -1.6 A, VGS = OV
IF = -1.6 A, dlF/dt = 100 Nl's
A
V
70
ns
0.15
l'C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width S 300 J1S. duty cycle S 2%.
c. Independent of operating temperature.
6-46
P-36852-Rev. D (06/06/94)
TEMIC
IRFD9020
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Output Characteristics
10
Ii:
8
/1/
~ '/
§:
;;;
8
"2~
.E
6
o~
o
4
J
;;;
":::
o@
6V
~
2
,I
.E
4V
4
6
8
o
10
25'C
V125'CI _
§:
5V
2
-55'C
:s
U
'1/
jV
fJ!.-
I
Tc~
7V
:; r
4
2
Iransfer Characteristics
5
I
I
VvGS~10,9,8~
o
2
Vos - Drain·to-Source Voltage (V)
I
~
4
6
8
10
VGS - Gate-la-Source Voltage (V)
Iransconductance
On-Resistance vs. Drain Current
0.5
€
e.
g
.!!l
~
j
~
0
"0
"
j
0.4
VGS~
0.3
r
1--1.I
.l
VGS~20V
0.2
I
J
.:l
bO
0
2
0
3
4
0.1
o
5
o
2.5
5.0
Capacitance
10
€
1000
G;'
I
"
;'
Vos ~ 25V
8 I- 10 ~ 1.6 A
750
~:s
6
1
500
'iii
I
U
4
/"
/
I
~
250
30
40
Vos - Drain-to-Source Voltage (V)
P-36852-Rev. D (06/06/94)
50
2
o
"
I
\!)
20
15.0
~
0
10
12.5
L
~
~
5"
10.0
Gate Charge
1250
.j
7.5
10 - Dram Current (A)
10 - Drain Current (A)
8
10V
V
o
8
12
16
20
Og - Thtal Gate Charge (nC)
6-47
TEMIC
IRFD9020
Siliconix
'lYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
On-Resistance vs. Junction Temperature
I
VGs= 10V
ID = l.1A
2.00 Ol
'8
1.75
V
N'i:i'
.~ .~ 1.50
~~
e
6
o ~ 1.25
V
I
!
e
1.00
0.75
JI"
/
/
TJ
./
s
8"
~
-10
30
150'C
A
//
II
(f
10
TJ = 25'C
til
~
""
0.50
-50
Source-Drain Diode Forward Voltage
100
2.25
70
o
150
110
TJ - Junction Thmperature ('C)
4
2
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
Maximum Drain Current
vs. Ambient Temperature
2.5
S
"~
50mm~l!!m~
2.0
1.5
U
-
.............
c
'01
Q
Safe Operating Area
1.0
i'-...
I
.fl
0.5
o
o
25
50
75
,
"
100
125
TA - Ambient Thmperature ('C)
6-48
0.1
\
0.01
150
0.1
10
100
VDS - Drain-to-Source Voltage (V)
P-36852-Rev. D (06/06/94)
TEMIC
IRFD9120j9123
Siliconix
P-Channel Enhancement-Mode lransistors
Product Summary
Part Number
V(BR)nSS (V)
rnS(on) (Q)
In (A)
IRFD9120
-100
0.60
-1.0
IRFD9123
-60
0.80
-0.8
S
4·PinDIP
G
D
S
Thp View
D D
P·Channel MOSFET
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Symbol
IRFD91Z0
IRFD9123
Drain-Source Voltage
Vos
-100
-60
Gate-Source Voltage
Vas
±20
±20
Parameter
Unit
V
ITA=25'C
Continuous Drain Current
10
-' TA = 100'C
Pulsed Drain Current
10M
ITA = 25'C
Power Dissipation
ITA = 100'C
Operating Junction and Storage Thmperature Range
Lead Thmpcrature eh6" from case for 10 sec)
Po
-1.0
-O.S
-0.6
-0.5
-S.O
-6.4
1.0
1.0
0.4
0.4
A
W
TJ. Tstg
-55 to 150
TL
300
Symbol
Maximum
Unit
RthJA
120
'CIW
'C
Thermal Resistance Ratings
Parameter
Junction-to-Ambient
P-36S52-Rev. D (06/06/94)
6·49
TEMIC
IRFD9120/9123
Specifications (TJ
Parameter
Siliconix
= 25°C Unless Otherwise Noted)
Symbol
Test Condition
Min
'JYpa
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
IRFD9120
VGs=OY,Io= -2501lA
V(BR)DSS
Vos = VGs. 10 = -250 IlA
VGS(tb)
IGSS
loss
-60
V
-2.0
-4.0
VOS = OY,VGS = ±20V
±500
-250
-1000
Vos = 0.8XV(BR)DSS. VGS - OY,TJ -125'C
IO(an)
Vos = -lOY, VGS = -lOY
roS(on)
VGS = -lOY, 10 = -0.8 A,
TJ = 125'C
Forward 1tansconductanceb
-100
VOS = V(BR)DSS. VGS = 0 V
VGS = -lOY, 10 = -0.8 A
Drain-Source On-State Resistanceb
IRFD9123
gr,
IRFD9120
-1.0
IRFD9123
-0.8
0.50
0.60
IRFD9123
0.60
0.80
IRFD9120
0.80
1.0
1.00
1.4
IRFD9123
0.8
IlA
A
IRFD9120
Vos = -15 Y, 10 = -0.8 A
nA
1.0
0
S
Dynamic
Input Capacitance
C;..
Output Capacitance
Co..
Reverse 1tansfer Capacitance
c,."
Thtal Gate ChargeC
Og
Gate-Source ChargeC
Ogs
Gate-Drain ChargeC
Ogd
111m-On Delay 11meC
td(an)
Rise Timec
111m-Off Delay 11meC
Fall11mec
VGS = OY, Vos = -25Y,f= 1 MHz
t,
td(off)
VOS =
-50~VGS
= lOY, 10 = -4A
350
450
205
350
80
100
9
20
1.S
pF
nC
5.6
Vnn = -50 V. RL = 620
10"" -O.SA, VGEN = -10Y,Ro = 250
tf
9
50
25
100
30
100
30
100
...
Source-Drain Diode Ratings and Characteristics (TA = 2S"C)
Continuous Current
Pulsed Current
Forward Voltageb
Is
. ISM
VSO
Reverse Recovery 11me
trr
Reverse Recovery Charge
Orr
IF = Is. VGS=OV
IF = Is. dlF/dt = 100 NJ.IS
IRFD9120
-1.0
IRFD9123
-0.8
IRFD9120
-S.O
IRFD9123
-6.4
IRFD9120
-6.3
IRFD9123
-6.0
A
V
SO
ns
0.18
!,C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 J.IS. duty cycle s 2%.
c. Independent of operating temperature.
6-50
P-36S52-Rev. D (06/06/94)
TEMIC
IRFD9120j9123
Siliconix
TYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Output Characteristics
10
1l:ansfer Characteristics
5
~c = -SS~C
9V
8
§:
;;
§:
8
8
3
C5
2
"
7V
..."
.:;
6V
.:;
.;;
C5
~
;;
8V
6
2
SV
4V
0
0
10
20
30
40
o
SO
~
o
1l:ansconductance
6
4
1.6
~
~
~
3
2
1.2
0.8
0
F
VOS= 10V
J---
I
[
e
"
co
0.4
Vos = 20V
o
2
6
8
10
I
o
2
4
In - Drain Current(A)
Capacitance
~
j
800
a""
~
400
u
200
o
~
::s
r':::: "'-
h=
o
10
20
30
C;,,-
.I
-
Co,,-
40
Vns - Drain-to-Source Voltage (V)
P-368S2-Rev. D (06/06/94)
8
10
Gate Charge
15.0
~
6
In - Drain Current (A)
1000
600
10
On-Resistance vs. Drain Current
"0
~
8
.~"
8
2.0
8
§
125°C
Vos - Gate-to-Source Voltage (V)
5
g
"
~
os
250C _
J'
I
2
Vns - Drain-to-Source Voltage (V)
€
I
WI
~
SO
~"
I
In =4A
12.5
VDs=50V ~
10.0
1
c:l
5.0
~
2.5
~
~V
7.5
I
I
o
I
o
4
Qg -
8
12
16
20
Thtal Gate Charge (nC)
6-51
TEMIC
IRFD9120/9123
Siliconix
'lYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
On-Resistance vs. Junction Temperature
2.00
I
VGs= 10V
~~
_"0
1.50
~1
1.25
.~ .~
=. .
o~
I
I~
1.00
0.75
V
0.50
-50
~V
V
V
V
;,r~
I-- Tl ~25'C
,/
1.75 I- ID = O.SA
Source-Drain Diode Forward Voltage
50
S
"~
U
I
10
.
'"
-.
§
/A
~ Tl~150'C -
II
0
I
I
-10
30
70
110
o
150
2
Tl - Junction "Il:mperature ("C)
3
4
5
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
Safe Operating Area
20
I J 1111
10
s
t~~)
S
"~
!
u
i
-,
....
I
100,..
1 I I
lOms
U
·eQ=
·eQ=
I
I
.El 0.50
0.25 '--0---'-25:--.....J5L...O-~75-.....Jl00--l.L25-~150
TA - Ambient "Il:mperature ("C)
6-52
0.1
.El
!.c
'25'C
l~i~~lt
0.01
0.005
0.1
I L
de=
10
100
500
VDS - Drain-to-Source Voltage (V)
P-36852-Rev. D (06/06/94)
TEMIC
MODIOOB/IOOC
Siliconix
Four N-Channel Enhancement-Mode Thansistors
Product Summary
V(BR)DSS (V)
rDS(on) (9)
ID (A)
100
0.08
21
D
D
S
D
S
G
G
S
D
G
G
S
D
Leadform Options
MOD100B . .. Bent Down
MODlOOC . .. Bent Up
S
N-Channel MOSFET
Absolute Maximum Ratings (Tc
= 25°C Unless Otherwise Noted)
Parameter
Symbol
.All Die
Single Die
Drain-Source Voltage
VDS
100
100
Gate-Source Voltage
VGS
±20
±20
21
84
Continuous Drain Current (TJ = 150·C)
I Tc=2S·C
ITc = 100·C
Pulsed Drain Current
ID
IDM
Avalanche Current (See Thermal Ratings)
IA
I Tc=2SoC
Maximum Power Dissipation
ITc = 100·C
Pn
21
70
125
440
Unit
V
A
21
150
400
60
100
W
Operating Junction and Storage 'Thmperature Range
Tl. Tstg
-55 to 150
°C
Isolation Voltage
VISOL
1000
V
Thermal Resistance Ratings
Parameter
Symbol
'JYpieal
SinglcDlc
.All Die
Maximum Junction·to-Ambient
RthIA
30
30
Maximum Junction-ta-Case
RthJC
0.83
0.31
Case-ta-Sink
RthCS
P-36734-Rev. D (05/30/94)
Unit
0C;W
0.1
6-53
TEMIC
MODIOOB/IOOC
Specifications (TJ
Siliconix
= 25°C Unless Otherwise Noted)
Limit
Parameter
Symbol
Test Condition
Min
1YP
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
ZeIO Gate Voltage Drain CUrrent
On-State Drain Current"
Drain-Source On-State Resistance"
V(BR)DSS
vos =
ov, lD = 250 !1A
100
V
2.0
4.0
VOS(th)
VDS = VOS. ID = 250 rnA
loss
VDS = OV,Vos = ±20V
±loo
VDS = 80 V, VOS = OV
250
VDS = 80 V, Vos = 0 V, TJ = 125'C
1000
IDSS
ID(on)
'OS(on)
gr,
Forward 1tansconductance"
VDS = 10V, VOS = 10V
21
0.070
0.08
Vos = 10 V, ID = 20 A, TJ = 125'C
0.100
0.120
9.0
!1A
A
VOS -10 V,ID - 20A
VDS = 15' V, ID = 20 A
nA
11.0
!>l
S
Dynamic:
Input Capacitance
c...
Output Capacitance
Co..
Cr.,
Reverse 1tansfer Capacitance
1btal Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Thrn-On Delay TIme
VOS = OV,VDS = 25V,f= 1 MHz
tf
td(off)
FaIl TIme
1100
pF
400
90
VDS = 50 V, Vos = 10V,ID = 21 A
td(on)
Ris.eTIme
Thrn-Off Delay TIme
2800
VDD = 24 V, RL = 1.2 !>l
ID .. 20 A, VOEN = 10 V, Ro = 4.7!>l
tf
125
18
22
30
65
15
35
30
100
50
125
20
100
nC
ns
SIlUl"ee-Draln Diode Ratings and Cbarac:teristks
Continuous Current
Is
21
Pulsed Current
ISM
125
Diode Forward Voltage"
VSD
Reverse Recovery TIme
trr
Reverse Recovery Charge
Q rr
A
Notes: .
a. Pulse test; pulse width :s 300 flS. duty cycle
b. Independent of operating temperature.
6-54
2.5
IF- 21 A, VOS- OV
IF =21A, di/dt = 100 N""
V
150
os
0.5
!,C
:s 2%.
P-36734--Rev. D (05/30/94)
TEMIC
MODIOOB/IOOC
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
50
~T.v Vas=~OV
9V
40
"
8
~
.~
Q
.E
30
20
10
0
8V -
/V/
V
~
fh
40
~
=
"t:
()
/'
.~
Q
~
~ .,.
30
"c:
7V
20
6V
5V
~
o
'ftansfer Characteristics
50
-
.E
10
4V
0
4
2
6
8
10
0
2
'ftansconductance
24
€
g
a
'""c:
~
F:'"
20
8
10
On-Resistance vs_ Drain Current
0.125
TC= -55°C
e.
0.100
10
j 0.075
~
8 0.050
5
g 0.025
15
VGS=10V
/20V.:::;;;;;;;;;o
g
I
"
bQ
6
Vas - Gate-to-Source Voltage (V)
VDS - Drain-Io-Source Vollage (V)
o
0
0
10
20
30
40
50
o
25
ID - Drain Currenl (A)
Capacitance
5000
~
g, 12.5
j
I
I- ID = 21 A
!!
Ii:'
~
,e:
~
g 3000
"
·i
0
10.0
c.
~
7.5
I
t.!l
5.0
~
2.5
a 2000
~
()
1000
0
0
10
20
30
40
VDS - Dram-la-Source Voltage (V)
P-36734-Rev. D (05/30/94)
75
100
125
Gate Charge
15.0
4000
0
50
ID - Drain Current (A)
50
V~s=
/
~~
50V
H
/80V
I
/
V
o
20
Qg
40
-
60
80
100
Thtal Gate Charge (nC)
6-55
TEMIC
MODIOOB/IOOC
Siliconix
1YPical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs, Junction Temperature
2.00
v
1.75
e!8
§~
1.50
~""
"5 .~
~OI
, E 1.25
c ..
~
o~
I
~
J
1.00
V
V
g
a
~
I
TJ= 15O°'l1
-
::I
0
til
10
TJ - 25°C
'"
II
II
-10
30
70
o
150
110
l::::==--
rf
§
V"
0.50
-50
~
100
C
~
./
0.75
Source-Drain Diode Forward Voltage
400
,
I
1.0
0.5
1.5
2.0
2.5
VSD - Source-to-Drain Voltage (V)
TJ - Junction 1l:mperature (0C)
Thermal Ratings
Maximum Avalanche and Drain Current
vs. Case Temperature
25
g
'"
20
8
15
\
c
"eQ
g
\
c
10
.£l
5
o
Safe Operating Area
500
100
-
Limited by
]
~- I-
fDS(on)
~
c
\
I
10
E
Tc 25°C
Single Pulse
''''
II IIII
o
25
50
75
100
125
TC - Case 1l:mperature ("C)
150
2
1O~
looJlS _
'«1
Q
"'I
......
L
lms
iOms
lOOms
de
I I
10
100
VDS - Drain-Io-Source Voltage (V)
500
Normalized Thermal 'fransient Impedance, Junction-to-Case
2
III
Duty Cycle
0.5
-
0.2
~iIJII
~
0.1
jII""
0.05
0.02
-,.....
0.01
V
10-5
6-56
""'" Single Pulse
1 1-111111
10-4
10-3
10-2
Square Wave Pulse Duration (sec)
10- 1
3
P-36734-Rev. D (05130/94)
TEMIC
MOD200B/200C
Siliconix
Four N -Channel Enhancement-Mode Thansistors
Product Summary
V(BR)DSS (V)
rDS(on) (Q)
ID (A)
200
0.11
21
D
D
S
G
G
S
D
D
S
G
G
S
D
Lcnclform Options
Go---I
MOD200B . .. Bent Down
MOD200C . " Bent Up
S
N-Channel MOSFET
Absolute Maximum Ratings (Tc
= 25°C Unless Otherwise Noted)
Symbol
Parameter
Single Die
All Die
Drain-Source Voltage
VDS
200
200
Gate-Source Voltage
Vas
±20
±20
21
84
Continuous Drain Current (TJ = 150'C)
I Tc=25'C
ITc= 100'C
Pulsed Drain Current
ID
IDM
Avalanche Current
IA
Maximum Power Dissipation
ITc= 25'C
PD
ITc= 100'C
17
56
100
360
Unit
V
A
21
150
400
60
100
W
Operatmg Junction and Storage 'Thmperature Range
TJ. 'f,tg
-55 to 150
'C
Isolation Voltage
VISOL
1000
V
Thermal Resistance Ratings
Parameter
Symbol
Typical
Single Die
All Die
Maximum Junction-to-Ambient
RthJA
30
30
Maximum Junction-to-Case
RthJC
0.83
0.31
Case-to-Sink
RthCS
P-36737-Rev. D (05/30/94)
Unit
'C/W
0.1
6-57
TEMIC
MOD200B/200C
Specifications (TJ
Siliconix
= 25°C Unless Otherwise Noted)
Limit
Parameter
Symbol
Min
Test Condition
Typ
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
200
V
2.0
4.0
loss
Vos=OV,Vos= ±20V
±100
Vos -160V, Vos - OV
250
Vos = 160 V, Vos = 0 V, TJ = 125'C
1000
loss
On-State Drain Current'
IO(on)
Forward nansconductance'
JlA
Vos - Vos. 10 - 250 rnA
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance"
Vos = Ov, 10 = 250
VOS(th)
l
Junction-to-Ambient Free Airb
RtbJA
Junction-ta-Case
RthJC
'JYpical
Maximum
2.3
3.0
60
Unit
0c/w
Notes:
a. Calculated Rating for TC = 25°C, for comparison purposes only. This cannot be used as continuous rating (see Absolute Maximum Ratings
and lYpical Characteristics).
b. Surface mounted on PC board or mounted vertically in free air.
P-36850-Rev. B (06/06/94)
-
~~
=l";riI
.ar..
(;)00
40
ITc=25°C
Maximum Power Dissipation
Unit
6-79
~O
.~
Z
-
TEMIC
SMDIOP06L
Siliconix
Specifications (TJ = 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
1yP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
Vas = OV,ID = -250 ~A
-60
VaS(th)
VDS = Vas. ID = -250 ~A
-1.0
lass
VDs=OV,Vas= ±20V
±100
VDS = -4S V, Vas = OV
-2
VDS = -4SV, Vas = OV,TJ = 125°C
-100
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(on)
Drain-Source On-State Resistance b
Forward 1fansconductanceb
rDS(on)
gf,
VDS = -5 V, Vas = -10V
V
-3.0
-10
~
A
Vas = -10V,ID = -2.3 A
0.2S
Vas = -4.5 V,ID = -1.6 A
0.35
VDS=-15V,ID=-SA
nA
1.0
0
S
Dynamic"
Input Capacitance
Cj"
Output Capacitance
Coss
Reverse 1fansfer Capacitance
c,.ss
Thtal Gate ChargeC
Qg
Gate-Source ChargeC
Qgs
Gate-Drain ChargeC
'furn-On Delay TImec
Rise Timec
'furn-Off Delay Timec
FallTImec
440
Vas = Ov, VDS = -25V,f= 1 MHz
140
pF
25
13
24
2.0
4.0
Qgd
4
S.O
td(on)
15
tr
td(off)
VDS = -30 V, Vas = -10V,ID = -lOA
VDD = -30V,RL= 30
ID'" -lOA, VaEN = -10V, Ra = 250
nC
50
ns
SO
SO
tf
Source-Dtain Diode Ratings and Characteristics
Is
-20
Pulsed Current
ISM
-24
Forward Voltageb
VSD
Continuous Current
Reverse Recovery TIme
tIT
Reverse Recovery Charge
Qrr
IF = -2.0 A, Vas = OV
IF = -2.0A,dildt =
100N~
-1.2
A
V
60
ns
0.07
!,C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 ~s. duty cycle S 2%.
c. Independent of operating temperature.
6-80
P-36SSO-Rev. B (06/06/94)
TEMIC
SMDIOP06L
Siliconix
'IYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
20r-____r-°_u_t~p_utrC-h-a-r-ac-trer-is-t-ic-s~~--~
Transfer Characteristics
20r-----r----,,----,,----,-----,
5 f----,jUt------t------t------j- 4 V
3Y,2V
o~================~
o
o
10
8
2
On-Resistance vs. Drain Current
,
0.7
0.6
~
1l
!"l
.~
0.5
'"
0.3
J
0.2
tl:'
.e:
8
iii
-
-
Vas
10V-
I
700
600
.~
0.1
o
900
800
l----""
~
0
a
I
500
400
I
2
6
10
~
Gate Charge
~
V
,1/
J J.
8 r- Vns =60V
In = 04A
~
§
S
6
CIl
.9
"
"
'OJ
~
/
4
2
0
2.5
/
8
iii~
_"tl
.~
V
\;;;:.1"
o
10
--
_I
1"
I
20
30
40
50
60
.§
On·Resistance vs. Junction Temperature
r-I 1lOl
VGS =
ID = 2.3 A
./
1.5
~'iiI
=, e
k
~~
!
a
V
2
2.0
~
/
o
"-
VDS - Drain-to-Source Voltage (V)
In - Drain Current (A)
10
\
200
o
~ss
\-
300
U
100
o
10
Capacitance
1000
~v~.,sv)
0.4
8
2
Vas - Gate-to-Source Voltage (V)
Vns - Drain-ta-Source Voltage (V)
./
1.0
0.5
VV
V
,/
V"
V
"
o
4
6
8
10
12
Q g - Thtal Gate Charge (nC)
P-36850-Rev. B (06/06/94)
14
16
-50 -25
0
25
50
75
100 125 150 175
TJ - Junction Temperature ("C)
6-81
TEMIC
SMDIOP06L
Siliconix
'JYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Source-Drain Diode Forward Voltage
20
S
;;
Threshold Voltage
1.0
/, ~
10
~
a
-
I
§
I
r5l
I I
:!
I II
I
o
~
TJ = 25°C
LU-
0.5
.~
I
TJ= 150°C
:s
€
0.0
........ ........
~
I
........
~
IS
>
r-... ~
-0.5
........ .....
r"..
1/
0.4
0.8
1.2
1.6
VSD - Source-to-Drain Voltage (V)
-1
-50 -25
2.0
0
25
50
75
100 125 150 175
TJ - Thmperature (0C)
Thermal Ratings
Maximum Drain Current vs. Case Temperature
Safe Operating Area
2.5
100 _
2.0
S
~:s
1.5
.~
1.0
...........
.......... i'oo..
S
10
'i:
......
U
~
~
~
A
~
==
T
_
J,;,;~iT1 r
~;.:'
byJDS(on)
....
I.........
10~s
100~s
1ms
10ms
lOOms
"\.
':1 1 I I I I I ~
o
25
50
75
100
125
150
175
0.1
TC - Case Thmperature (0C)
10
100
VDS - Drain-to-Source Voltage (V)
Normalized Thermal1i-ansient Impedance, Junction-to-Case
2
I II I
Duty Cycle - 0.5
-0.2
-
::~
0.1
==
0.05
;:::::: 0.02
1
~
0,01
10-4
T
Single Pulse
1
-
~
.....
~i"""
1111
10-3
10-2
10- 1
10
30
Square Wave Pulse Duration (sec)
6-82
P-3685(}-Rev. B (06/06/94)
TEMIC
SMD/SMU15N05
Siliconix
N-Channel Enhancement-Mode 1ransistors
175°C Maximum Junction Temperature
Product Summary
V(BR)DSS (V)
rDS(on) (Q)
IDa (A)
50
0.10
15
TO-2S1
D
TO-2S2
~
G
D
o
Go---J
Drain connected to Thb
S
Top View
Order Number:
G
SMD1SNOS
D
S
S
ThpView
Order Number:
N-Channel MOSFET
SMU1SNOS
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Symbol
SMD15N05
SMU15N05
Drain-Source Voltage
VDS
50
50
Gate-Source Voltage
Vas
±20
±20
3.3b
2.3"
1.9b
1.3"
24
24
ITA~25'C
Continuous Drain Currentb
ITA ~ 100'C
Pulsed Drain Current (maximum current limited by package)
ID
IDM
ITc ~ 25'C
Power Dissipation
lTA~2S'C
Operating Junction and Storage Thmperature Range
Lead Thmperature eh6" from case for 10 sec.)
PD
40
40
2.0b
1.00
Unit
V
A
W
T1, Tstg
-55 to 175
TL
300
'C
Thermal Resistance Ratings
Parameter
Symbol
lunction-to-Ambient Free Air, PC Board Mount
lunction-to-Ambient Free Air, Vertical Mount
Junction-to-Case
Rth1A
Rth1c
1Yp\cal
Maximum
50
60
125
Unit
'CfW
3.0
Notes:
a. Calculated Rating for Tc ~ 25°C, for comparison purposes only. This cannot be used as continuous rating (see Absolute Maximum Ratings
and lYpical Characteristics).
b. Surface mounted on PC board.
c. Free air, vertical mount.
P-368SG-Rev. C (06/06/94)
6-83
TEMIC
SMD/SMU15N05
Specifications (TJ
Parameter
Siliconix
= 25°C Unless Otherwise Noted)
Symbol
Test Condition
Min
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 'franseonductanceb
V(BR)DSS
Vas = OY, ID = ZSO flA
50
VoS(th)
VDS = Vas, In = ZSO J1A
2.0
loss
Vns=OY,Vos= ±20V
±100
Vns = 40 Y, Vas = OV
25
Vns = 40Y, Vas = OY, TJ = lZS0C
250
IDSS
ID(on)
fDS(on)
V
4.0
15
VDS = 5Y, Vas = 10V
0.07
0.10
Vas = 10 Y, In = 7.5 A, TJ = 125°C
0.13
0.18
3.0
Vns = 15Y,ID = 7.5 A
Output Capacitance
C;"
Cess
Vas = OY,VDS = ZSY,f= 1 MHz
Reverse 'fransfer Capacitance
c"..
J1A
A
Vas -lOY, ID -7.5 A
!If.
nA
4.8
Q
S
Dynamic
Input Capacitance
Thtal Gate Chargee
Og
Gate-Source Chargee
Ogs
Gate-Drain Chargee
Ogd
1I1rn-On Delay TImee
Rise Timec
1I1rn-Off Delay TImee
FailTImee
550
tcl(olf)
pF
100
15
Vns = 25 V; Vas = lOY, In = 15 A
30
3.5
nC
5
Id(on)
tr
320
VDD = ZSY,RL = 1.67Q
In = 15 A, VOEN = 10 Y, RO = 25Q
tf
15
30
50
85
80
90
80
110
ns
SllUrC4l-Drain Diode Ratings and Characteristics
Continuous Current
Is
Pulsed Current
ISM
Forward Voltageb
VSD
Reverse Reeovery TIme
trr
Reverse Recovery Charge
Orr
I
I
srYIDl5l"~05
3'1
SMU15N05
1.0
A
24
IF - 3.3 A, Vas - OV
IF = 3.3 A, dlp/dt = 100 Nfls
1.8
2.3
V
65
ns
0.16
(.lC
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width S 300 ,,", duty cycle S 2%.
c. Independent of operating temperature.
6-84
P-36850-Rev. C (06/06/94)
TEMIC
SMD/SMU15N()5
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
'll-ansfer Characteristics
40
30
S
30
~
25
U
20
""
.~
Q
15
.E
10
I
Tc~
35
S
"~
U
~
5V
,
20
,J
10
5
4V
0
0
0
6
2
8
10
~
o
'll-ansconductance
~ ",
9
6
ta
F:
.....
I
0
I
0.20
B
.1Il
rI
0.15
VGS~
~
125°C
.
0
lOV
-'
0.10
(/
~
I
J
I
I
8
25°C
II ~
.",
10
8
6
~
",
~
'0
"
"~
4
On-Resistance vs. Drain Current
0.25
L--5L _
12
€
2
VGS - Gate-ta-Source Voltage (V)
Vos - Drain-to-Source Voltage (V)
15
/125°C
j
15
.E
5
~f ~5OC
-55°C
25
VGs-20V
0.05
0
o
10
15
20
25
0
30
10
20
VGS - Gate-to-Source Voltage (V)
40
50
60
10 - Drain Current (A)
Capacitance
1000
30
Gate Charge
15
"
800
.,e,
8 600
.~
a
400
I
U
200
~
.~
\" ----
~ -.......---'"
~
c...
o
10
~lii
~
Co"
3
0
20
30
40
VOS - Drain-to-Source Voltage (V)
P-36850-Rev. C (06/06/94)
9
(!)
~"
0
12
~
~
50
=~
=r;ril
J~
U OO
~O
z
€
tL;'
'aj
0
5
10
15
20
25
Og - Thtal Gate Charge (nC)
6-85
TEMIC
SMD/SMU15N05
Siliconix
'tYpical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.00
~
1.75
e..
/
8
3 '" 1.50
.!!l !!
~:a
=E1.ZS
~~
~
1.00
~
1
~
J
10
6
'"
::
./
0.75
'I
$
V
/
V
/
Source-Drain Diode Forward Voltage
100
I
;---TJ=150°C
"
,r
J=
1
0.50
-50
-10
30
70
110
150
25°~
o
175
2
TJ - Junction 1l:mperature (0C)
5
4
3
VSD - Source-ta-Drain Voltage (V)
Thermal Ratings a
5Maximum Drain Current vs. Case Thmperature
4
$
~
a
3
Q
2
·til
$
I - - ..........
...........
o
~:~"!
75
100
125
150
0.1
Duty Cycle
C
J~8.
0.2
-"
'S"
\J__
,,'to
.~
"'-
11111
0.1
100
10
VDS - Drain-ta-Source Voltage (V)
IIII
0.5
0.1
0.05
].!l
.....
~
-
Z
Single Pulse
Recommended Minimum Drain Pad Size
for PC Board Surface Mount Applications (inches)
I I IIIII
III
0.01
10-4
10-3
a. Surface Mounted o~ PC Board.
6-86
4,"'=
Normalized Thermal1i-ansient Impedance, Junction-to-Case
2
~Fl
!l0
lOms
lOOms
1111
I IIIIIII
Tc - Case 1l:mperature ("C)
~E 0.1
"
Tc-ZSoC
~ Single Pulee
0.01
l'l~1lS
1ms
.....
E
r175
I'.'~~
"
I
.El
::rc
lOllS
Q
\
50
,
.
~~
25
t""..ITI'IIi'""
i'""
~
u"
'j!
~ r-.....
r---o
10
C
I
.El
Safe Operating Area
100
111111
10-2
JJIJII
10- 1
I
o.27S~
D~
DO
10
r=r-
~i-
r-ir-ir--f--
50
Square Wave Pulse Duration (sec)
P-36850-Rev. C (06/06194)
TEMIC
SMD15N06
Siliconix
N-Channel Enhancement-Mode Transistor
175°C Maximum Junction Temperature
Product Summary
V(BR)DSS (V)
fDS(on) (0)
IDa (A)
60
0.10
15
D
DPAK (TO-252)
D
G~
G
S
S
ThpView
N-Channel MOSFET
Absolute Maximum Ratings (l'c = 25°C Unless Otherwise Noted)
Symbol
Parameter
Limit
Drain-Source Voltage
Vos
60
Gate-Source Voltage
VGS
±20
V
15
ITe = 25'C
Continuous Drain Currentb
Unit
10
7.5
ITe= l00'C
Pulsed Drain Current (maximum current limited by package)
10M
Po
ITA= 25'C
Operating Junction and Storage Temperature Range
16
40
ITe = 25'C
Maximum Power Dissipation
A
2.0b
W
TJ, Tstg
-55 to 175
'c
Symbol
Limit
Unit
Thermal Resistance Ratings
Parameter
Junction-to-Ambient Free Air b
RthJA
60
Junchon-to-Case
RthJe
3.0
'CfW
Notes:
a. Calculated Rating forTe = 25°C, for comparison purposes only. This cannot be used as continuous rating (see Absolute Maximum Ratings
and 'iYpical Characteristics).
b. When mounted on I" square PCB (FR-4 material).
(05/31/94)
Preliminary
6-87
TEMIC
SMD15N06
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
'JypB
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VGS = OY,ID = 250 IlA
60
VGS(th)
VDS - VGS,ID - 250 IlA
2.0
IGSS
VDS = OY,VGS = ±20V
±100
VDS = 48 Y, VGS = OV
1
VDS = 48 Y, VGS = 0 Y, TJ = 125'C
500
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(an)
Drain-Source On-State Resistanceb
Forward 1tansconductanceb
roS(an)
VDS = 5Y,VGS = 10V
V
4.0
15
nA
IlA
A
VGS = 10 Y, ID = 7.5 A
0.10
VGS -lOY, ID = 7.5 A, TJ - 125'C
0.18
Q
gr,
VDS = lOY, ID = 7.5 A
Output Capacitance
C;"
Co..
VGS = OY,VDS = 25Y,f= 1 MHz
Reverse 1tansfer Capacitance
c,..
5.0
S
Dynamic"
Input Capacitance
Thtal Gate ChargeC
Qg
Gate-Source ChargeC
Ogs
Gale-Drain ChargeC
Qgd
Thrn·On Delay TImec
RiseTImec
Thrn-Off Delay TImec
FallTImec
TBD
td(olf)
pF
TBD
VDS = 30Y, VGS = 10Y,ID = 15 A
td(an)
tf
TBD
VDD = 30Y, RL= 1.670
ID'" 15 A, VGEN = 10 Y, RG = 250
tl
TBD
24
TBD
4.0
TBD
8.0
TBD
30
TBD
85
TBD
90
TBD
110
nC
os
Source-Drain Diode Ratings and Characteristics
Continuous Current
Is
Pulsed Current
ISM
Forward Voltageb
VSD
Reverse Recovery TIme
trr
Reverse Recovery Charge
Orr
'i'c= 25'C
15
A
16
IF = 3.3 A, VGS = OV
IF = 3.3 A, dUdt = 100 NilS
2.2
V
TBD
ns
TBD
IlC
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width S 300 flS, duty eycle S 2%.
c. Independent of operating temperature.
6·88
Preliminary
(05/31/94)
TEMIC
SMD/SMU25N05-45L
Siliconix
N-Channel Enhancem.ent-Mode Transistors, Logic Level
175°C Maximum Junction Temperature
Product Summary
Vns(V)
rnS(on) (Q)
IDa (A)
50
0.045
25
TO-2S!
D
~
TO-2S2
~
G
D
o
Dram Connected to Thb
S
ThpView
G
Order Number:
SMD2SNOS-4SL
D
S
S
Top View
N·Channel MOSFET
Order Number:
SMU2SNOS-4SL
Absolute Maximum Ratings (TA = 25°C Unless Otherwise Noted)
Parameter
Gate-Source Voltage
Symbol
Limit
Unit
Vas
±16
V
S.O
TA=2S'C
Continuous Drain Current (T1 = 1S0'C)b
TA= 100'C
Pulsed Drain Current
ID
Continuous Source Current (Diode Conduction)
Avalanche Current
Repetitive Avalanche Energy (Duty Cycle
:s 1%)
L=O.1mH
Is
S
IAR
25
EAR
31
TA=2S'C
Operating JunctIon and Storage 'Thmperature Range
A
PD
mJ
2b
T],Tstg
Q)
-55 to 175
=~
=r.:l
~~
W
U OO
~O
'c
Z
SO
Tc=2S'C
Maximum Power Dissipation
I
3.1
100
IDM
I~
~
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambientb
Symbol
'iYPical
Maximum Junction-ta-Case
Rth]C
RthCS
Unit
60
RthJA
Case-ta-Sink
Mrudmum
2.5
'C/W
1.0
Notes:
a. Calculated Rating for Tc = 25 0 C, for comparison purposes only. This cannot be used as continuous rating (see Absolute Maximum Ratings
and 1Ypical Characteristics).
b. Surface moun ted on PC board or mounted vertically in free air.
P-37394-Rev. E (06/20/94)
6-89
TEMIC
SMD/SMU25N05-45L
Specifications (TJ
Parameter
Siliconix
= 25°C Unless Otherwise Noted)
Symbol
Test Condition
Min
1yP"
Max
V(BR)DSS
VGS = OV,Io = 250 ~A
50
VGS(th)
VOS - VGs. 10 - 1 rnA
1.0
1.8
3.0
IGSS
VOS = OV,VGS = ±16V
±100
VOS = 40 V, VGS = OV
2
VOS - 40 V, VGS - 0 V, TJ - 125"C
100
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gale-Body Leakage
Zero Gale Vollage Drain Currenl
On-Slate Drain Currenlb
loss
IO(on)
Vos - 2 V, VGS - 10V
Forward 'fransconduclanceb
25
0.045
VGS = 10 V, 10 = 12.5 A, TJ = 125"C
0.060
0.080
VGS = 5 V, 10 = 12.5 A
0.045
0.070
gr.
Vos = 15 V, 10 = 12.5 A
19
C;"
Coss
Crss
VGS = Ov, Vos = 25 V, f = 1 MHz
roS(on)
nA
~A
A
0.035
VGS - 10 V, 10 - 12.5 A
Drain-Source On-Slale Resislanceb
V
Q
S
Dynamic
Inpul Capacilance
OUIPUI Capacilance
Reverse 'fraosfer Capacilance
Thlal Gale Chargee
Og
Gate-Source Chargee
Og,
Gate-Drain Chargee
Ogd
Thrn-On Delay TImee
RiseTImec
Thrn-Off Delay TImee
FaUTImec
950
320
pF
110
22
36
5
10
10
16
Id(on)
10
20
I,
21
40
35
60
20
40
Id(off)
VOS = 25 V, VGS= 10 V, 10 =25A
VOO = 25 V, RL = 1 Q
10'" 25 A, VGEN= 10V,RG=7.5Q
If
nC
ns
Source..Drain Diuuc Ratings and Ch!tr~cte!."istie! ('J'c = 25°C)
Pulsed Current
ISM
Diode Forward Vollage
VSD
IF = 25 A, VGS- OV
1.0
Reverse Recovery TIme
I"
IF = 25 A, dildt - 100 N~s
120
100
A
1.8
V
ns
Noles:
a. For design aid only; nol subjecllo production lesting.
b. Pulse test; pulse width s 300~. duty cycle s 2%.
c. Independenl of operating temperature.
6-90
P-37394-Rev. E (06/20/94)
TEMIC
SMD/SMU25N05-45L
Siliconix
,
'JYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
Transfer Characteristics
100
20
16
80
S
S;:
~
5V
8""
4V
~
60
"
U
't:le"
~
40
20
'iiI
Ci
12
8
:;;
T~ = 125'C
3V
o
0
0
6
2
8
10
o
Transconductance
On-Resistance vs. Drain Current
0.08
0.07
€
~
"8
.
F
8
~
125'C
0.06
~
0
/1/
10
!
e
0.03
5
10
VGS = 10V
15
20
25
30
VGs=20V
0.02
I
0.01
o
0
o
-
0.04
I
/I)'
5
35
o
8
VGS - Gate-to-Source Voltage (V)
16
Capacitance
ID ~ 25A
VDs=25V
1
~
"l'J'
~
2000
~
500
...Z
20
30
40
VDS - Drain-to-Source Voltage (V)
P-37394-Rev. E (06/20/94)
40
4
:j
2
50
V
/
/V
If
\!)
o
10
/
6
b
"'c,,'.L
o
/
8
rn
\.cL
I
U
o
i
~~,
u 1000
32
Gate Charge
10
1
24
ID - Drain Current (A)
2500
1500
-
0.05
.~
15
I
bIl
£.
25'C
20
~
...
5
4
3
VGS - Gate-to-Source Voltage (V)
25
"0
-55'C
2
VDS - Drain-to-Source Voltage (V)
30
-~
25'C
4
J
V
o
4
8
12
16
20
24
28
Qg - Thtal Gate Charge (nC)
6-91
TEMIC
SMD/SMU25N05-45L
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction 'Thmperature
2.4
~
eII
a~
.~]
r-
2.0
J ..!
GS
10 vi
./
In = 12.5 A
1.6
./
il!"
1.2
d E
o~
I ~ 08
",-
J . .".
"V
V
Source-Drain Diode Forward Voltage
100
~
s
/
~
II
8
~
.,/
10
"
I
0.4
I
50
75
I
I
I
V II
1
25
I
I
o
0
/
1.0'"
/'25'C
0
til
'"
-50 -25
,
150'C
TJ
100 125 150 175
0.5
0.7
0.9
1.1
1.3
1.5
1.7
Vsn - Source-la-Drain Voltage (V)
TJ - Junclion Thmperalure ('C)
Thermal Ratings
Maximum Avalanche and Drain Current
vs. Case 'Thmperature
5
..........
S
~"
4
3
·f"
0
'"
..........
2
.9
"-
o
25
":\
50
75
100
125
150
Tc - Case Thmperalure ('C)
I~I~
lOms
lOOms
\
0
100""
".
~~~~!'II~I'~'~jIT.~I~:1
Tc 25'C
Single Pulse
0.1
11111111111
0.01
175
de
0.1
10
Vns - Drain-Io-Source Vollage (V)
100
Normalized Thermal 'ftansient Impedance, Junction-to-Case
2
Duty Cycle
II I
0.5
0.2
;;
0.1
jjiII""
0.05
-
0.02
"7 ~ Single Pulse
I 1-111111
0.Q1
10-4
10-3
10-2
10-1
10
20
Square Wave Pulse Duration (sec)
6-92
P-37394-Rev. E (06/20/94)
TEMIC
SMD/SMU30N03-30L
Siliconix
N-Channel Enhancement-Mode Thansistors, Logic Level
Product Summary
Vos(V)
rOS(on)
30
loa (A)
(Q)
0.030
30
TO·251
TO·252
~
G 0
o
o
Go-l
Drain Connected to Tab
S
Top View
G
D
S
S
Top View
Order Number:
SMD30N03-30L
N-Channel MOSFET
Order Number:
SMU30N03-30L
Absolute Maximum Ratings (TA
= 25°C Unless Otherwise Noted)
Parameter
Symbol
Unit
Limit
Drain-Source Voltage
VDS
30
Gate-Source Voltage
VGS
±20
V
Continuous Drain Current (TJ ~ 150,C)b
TA~2S'C
TA~
100'C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Avalanche Current
Repetitive Avalanche Energy (Duty Cycle s 1%)
L
~
0.1 mH
60
ID
3.8
IDM
30
Is
6
IAR
30
45
EAR
Tc~25'C
Maximum Power Dissipation
TA~25'C
Operating Junction and Storage Thmperature Range
A
mJ
50
PD
W
2b
-55 to 150
TJ,Tslg
'C
Thermal Resistance Ratings
Parameter
Symbol
'fYpical
Maximum
Maximum Junction-ta-Ambientb
RthJA
60
Maximum Junction·to-Case
RlhJc
2.5
Case-ta-Sink
RthCs
Unit
'C;W
1.0
Notes:
a. Calculated Rating for Tc ~ 25 0 C, for comparison purposes only. This cannot be used as continuous rating (see Absolute Maximum Ratings
and 'lYpical Characteristics).
b. Surface mounted on PC board or mounted vertically in free air.
P-36853-Rev. E (06/06/94)
6-93
TEMIC
SMD/SMU30N03-30L
Specifications (TJ
Parameter
Siliconix
= 25°C Unless Otherwise Noted)
Symbol
'Thst Condition
V(BR)DSS
VGS = OV,lo = 250
Min
1YP"
Max
2.1
3.0
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward TIansconductanceb
fAA
30
VGS(tb)
Vos- VGS, 10 -1 rnA
1.0
IGSS
VOS= OV,VGS= ±20V
±500
Vos = 24 V, VGS = OV
25
Vos - 24 V, VGS = 0 V, Tr - 125 D C
250
loss
10(on)
'DS(on)
gr.
VOS = 2V, VGS = 10V
V
nA
fAA
A
30
VGS = 10 V, 10 = 15A
0.023
VGS = 10 V, 10 = 15 A, Tr = 125 D C
0.031
0.050
VGS = 5V,lo = 15A
0.Q35
0.045
Vos = 15 V, 10 = 15 A
15
0.030
Q
S
Dynamic
Input Capacitance
850
C;ss
Output Capacitance
Coss
Reverse 'fransfer Capacitance
c,."
VGS = OV,Vos = 25 V, f= 1 MHz
500
pF
220
Thtal Gate ChargeC
Qg
Gate-Source ChargeC
Qgs
Gate-Drain ChargeC
Qgd
Thrn-On Delay TImec
td(on)
9
15
tr
25
40
27
40
25
35
Rise Timec
Thrn-Off Delay TImec
FallTImec
td(off)
30
VOS = 15 V, VGS = 10 V, 10 = 30A
VOO = 20 V, RL = 0.6 Q
10'" 30 A, VGEN= 1OV,RG=7.5Q
tf
35
5
8
15
20
nC
ns
Source ..JJrain Diode RaiiDg~ and Cl;iiraL:t~rlstks ere ~ 2S cl C)b
Pulsed Current
ISM
Diode Forward Voltage
Vso
IF =6 A, VGS = OV
1.1
100
A
1.8
V
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width :S 300Il',dutycycle:s 2%.
c. Independent of operating temperature.
6-94
P-36853-Rev. E (06/06/94)
TEMIC
SMD/SMU30N03-30L
Siliconix
JYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
50
VvG! =
'Iransfer Characteristics
20
lO,9,~, 7,6V
40
~
~
5V
~
30
"
U
U
'@
.~
Q
VDS = 15V
E
E
~
I
16
20
12
8
Q
4V
E
10
o
E
A
lY
TJ = 125°C
4
j1
13V
o
o
2
4
3
-55°C
o
4
2
VDS - Drain-to-Source Voltage (V)
250C
6
8
10
VGS - Gate-to-Source Voltage (V)
'Iransconductance
On-Resistance vs. Drain Current
0.08
25
0.07
€
20
~
0.06
.1
0.05
8
a
g
.
15
~
'tl
I
10
F:
"
bQ
J
VGs=5V/
0.04
.......
0.03
I
!
5
§
o
20
10
40
30
o
10
VGS - Gate-to-Source Voltage (V)
!
1500
1000
I
U
500
o
40
Gate Charge
"
2000
~
30
12
~
~
20
ID - Drain Current (A)
Capacitance
2500
VGs=10V
0.01
0
0
"
0.02
~
~
~
@
I~
"
V
8
c...-
"'-
10
6
~
2
0
20
I
4
L
I
Cr.,
VDS - Drain-to-Source Voltage (V)
P-36853-Rev. E (06/06/94)
1
C!l
Cess
30
/
/
0
1\ '"o
I;=25A 1
VDs=15V
10 -
I
o
5
10
15
20
25
30
Og - Thtal Gate Charge (nC)
6-95
TEMIC
SMD/SMU30N03-30L
Siliconix
'iYpical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs_ Junction Temperature
Source-Drain Diode Forward Voltage
100
2.0
liD = 115 A
/
V "
TJ
150°C,/7
/ V 25 °C
E
8
~ ......
/
I-
S
/
@
)'/
10
::I
0
VGs= lOV
'"I
.:!;
I
I
o
-50 -25
0
25
50
75
100
125
0.4
150
Thermal Ratings
..............
S
4
"
1.1
1.2
1.3
1.4
1.5
1.6
Safe Operating Area
~ .........
·01
'"
Ci
I
.El
1.0
."-
6
E
U
0.8
loom.__
,
Maximum Avalanche and Drain Current
vs. Ambient Temperature
8
S
0.6
VSD - Source-to-Drain Voltage (V)
TJ - Junction Thmperature (0C)
2
0
o
25
50
75
100
"',
"\
125
I-
~
0.1
lOOms
1s
TA 25°C
Single Pulse
11111111
0.1
150
I'
'"
dc
1"-'1'.
10
III
lOs
100
VDS - Drain-to-Source Voltage (V)
TA - Ambient Thmpcraturc (0C)
Normalized Thermal 1l-ansient Impedance, Junction-to-Ambient
2
Duty Cycle
II
0.5
0.2
~
1--1"'"
~
0.1
0.05
0.02
Single Pulse
0.01
~
10-5
...-10-4
"..
10-3
10- 2
10- 1
Square Wave Pulse Duration (sec)
6-96
P-36853-Rev. E (06/06/94)
TEMIC
SMP20PIO
Siliconix
P-Channel Enhancement-Mode Transistor
Product Summary
V(BR)nSS (V)
rnS(on) (Q)
In (A)
-100
0.20
-20
D
TO·220AB
o
Go---J
Drain Connected to Tab
GDS
S
ThpView
N-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Symbol
limit
Drain-Source Voltage
Vns
-100
Gate-Source Voltage
VGS
±20
Unit
V
-20
TC - 2S'C
Continuous Drain Current (fJ = IS0'C)
Tc = 100'C
Pulsed Drain Current
Avalanche Current
Repetitive Avalanche Energy"
L=O.OSmH
In
-12
InM
-80
IAR
-20
20
EAR
Tc = 2S'C
Maximum Power Dissipation
Tc = 100'C
Operating Junction and Storage Temperature Range
Lead Thmperature e1t6" from case for 10 sec )
A
mJ
125
W
Pn
SO
TJ,Tstg
-S5 to 150
TL
300
·C
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient
Symbol
1Ypicai
Maximum
RthJA
80
Maximum Junctlon-ta-Case
RthJC
1.0
Case-to-Sink
Rthcs
Unit
'CfW
1.0
Notes:
a. Duty cycle s 1%
P-3S259--Rev. B (OS/16/94)
6-97
TEMIC
SMP20PIO
Siliconix
Specifications (TJ - 25°C Unless Othenvise Noted)
Limit
Parameter
Symbol
Min
Test Condition
Typ"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VGS = 0 V, ID = -250
"A
-100
VGS(tb)
VDS = VGS,ID - -250
"A
-2.0
IDSS
On-State Drain Currentb
ID(on)
Drain-Source On-State Resistanceb
Forward TIansconductanceb
VDS-OV,VGS- ±12V
±100
VDS- -80V,VGS-OV
-250
VDS - -80 V, VGS - Ov, Tr = 125'C
-1000
IGSS
Zero Gate Voltage Drain Current
rDS(on)
-4.0
VDS = -10V, VGS = -lOY
-20
0.15
0.20
VGS = -10V,ID = -12A, Tr = 125'C
0.24
0.30
VDS = -15V,ID = -12 A
4.8
nA
"A
A
VGS = -10 V, ID = -12A
gr,
V
6.7
Q
S
Dynamic
Input Capacitance
Cj"
Output Capacitance
Coss
c."
Reverse Transfer Capacitance
Total Gate Chargee
Og
Gate-Source Chargee
Ogs
Gate-Drain Chargee
Ogd
Thrn-On Delay TImee
td(on)
Rise Timec
Thrn-Off Delay TImee
FailTImee
1300
VGS = OV, VDS = -25 V, f= 1 MHz
pF
250
47
VDS = -SOV, VGS =' -10V,ID = -20A
tr
td(aff)
700
ID
~
VDD = -40 V, RL = 2.1 Q
-19A, VGEN = -10V, RG = 4.7Q
tf
60
10
18
27
36
10
30
50
80
25
80
15
60
nC
ns
Source-Drain Diode Ratings and Characteristics
Continuous Current
Is
-20
Pulsed Current
ISM
-80
Diode Forward Voltageb
VSD
Reverse Recovery TIme
trr
Reverse Recovery Charge
Orr
A
-1.7
IF = -20 A, VGS = OV
IF = -20 A, di/dt = 100 Nfls
V
150
ns
0.3
flC
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width S 300 fls, duty cycle S 2%.
c. Independent of operating temperature.
6-98
P-35259-Rev. B (05/16/94)
TEMIC
SMP20PIO
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Output Characteristics
25
Transfer Characteristics
12.5
Tc = -55'C
25'C~
9V
10.0
20
BV
~
7V
u"
"
15
~
7.5
"
5.0
'il
10
Q
6V
.£:
f-#/-/'f----i---j---j- 5 V
2.5
~
o
o
2
6
o
10
1l
7.5
-0
§
5.0
F<
I
"
00
2.5
1.00
~
25'C
,I'
d
,If
i
125'C
0.75
.1
Lilnit
Unit
VGS
16
V
Tc = 25'C
Continuous Drain Current (T] = 150'q
Tc = l00'C
25
In
±16
A
Pulsed Drain Current
100
IDM
Avalanche Current (see Thermal Ratings, page 6-104 )
Repetitive Avalanche Energy3
L-0.05mH
IAR
25
EAR
31
Maximum Power Dissipation
Tc = 100'C
Operating Junction and Storage Thmperature Range
Lead Temperature (1116" from case for 10 sec.)
mJ
70
Tc=25'C
Pn
W
36
T], Tstg
-55 to 175
TL
300
'C
Thermal Resistance Ratings
Parameter
Symbc>l
'JYpical
Maximum
Maximum Junction-ta-Ambient
RthJA
80
Maximum lunction-to-Case
RthJC
2.08
Case-to-Sink
Rthcs
Unit
'CIW
1.0
Notes:
a. Duty cycle s 1%
P-36850-Rev. D (06/06/94)
6-101
TEMIC
SMP25N05-45L
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Limit
Parameter
Symbol
Test Condition
V(BR)DSS
VGS = Ov, ID = 250
Min
Typ"
Max
1.5
3.0
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 1fansconductanceb
J!A
50
VGS(th)
VDS = VGS. ID = 1 rnA
1.0
IGSS
VDS = Ov, VGS = ±16 V
±100
VDS = 40V,VGS = OV
2
IDSS
ID(on)
roS(on)
Sf,
V
VDS = 40 V, VGS = 0 V, Tr = 125°C
100
VDS - 40 V, VGS - 0 V, Tr - 175°C
500
VDS - 2V, VGS -10V
25
nA
~A
A
VGS - 10 Y, ID - 12.5 A
0.035
0.045
VGS = 10 V, ID = 12.5 A, Tr = 125°C
0.060
0.080
VGS = 10 V, ID = 12.5 A, Tr = 175°C
0.062
0.085
VGS = 4.25 Y, ID = 12.5 A
0.045
0.060
VDS = 15 V, ID = 12.5 A
19
0
S
Dynamic
Input Capacitance
y"
Output Capacitance
Co..
Reverse 1fansfer Capacitance
c,."
Total Gate ChargeC
Qg
Gate-Source ChargeC
Qgs
Gate-Drain ChargeC
Qgd
Thrn-On Delay TImec
RiseTImec
Thrn-Off Delay TImec
FailTImec
950
VGS = OY,Vns = 25Y,f= 1 MHz
320
pF
110
22
VDS = 25 V, VGS
= lOY, ID = 25A
5
nC
10
td(on)
10
tr
25
40
35
60
20
40
td(olf)
VDD = 25 Y, RL = 1 0
ID ,,25 A, VGW = lOV,RG = 7.50
tl
20
ns
Source-Drain Diode Ratings and Characteristics
Is
25
Pulsed Current
ISM
100
Diode Forward Voltageb
VSD
Reverse Recovery TIme
trr
Continuous Current
A
Peak Reverse Recovery Current
Reverse Recovery Charge
IRM(rcc)
Q rr
IF
= 25 A, VGS = OV
IF = 25 A, dildt
1.0
1.8
V
120
ns
0.42
~C
= 100 N~
A
Notes:
II- For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 ~s. duty cycle s 2%.
c. Independent of operating temperature.
6-102
P-36850-Rev. D (06/06/94)
TEMIC
SMP25N05-45L
Siliconix
,
1Ypical Characteristics (25°C Unless Otherwise Noted)
'fransfer Characteristics
20
50
40
16
~
~
E
E
~
30
A
20
"2"
.E
10
4V
~
12
"2"
8
8
A
hllfF--+--+---+----+
J.
.E
3V
!J.9
::;;
25'C
T~ = 125'C
0
2
o
4
3
2
VOS - Drain-to-Source Voltage (V)
+e=
25
€
1l
20
~
"
'0
15
F:
10
~
I
"
bO
5
0
./
...-
/J V
On-Resistance vs. Drain Current
0.10
-~5'C
0.08
i5'C
e.
125'C
.~
0.06
d
0
0.04
1l
~
I VI
1/)'
If
o
I
i
ff
VGS= 10 V
0.02
o
10
15
20
25
30
35
10 - Drain Current (A)
Capacitance
2500
Gate Charge
10
E
"
2000
~
~
~
1500
a
I0 1=25A
8
I
U
500
VGs= 25V/
6
0
,L
1000
I
o
"
'".9
Co..
/
~
4
J
2
0
10
20
30
40
VOS - Drain-to-Source Voltage (V)
P-36850-Rev. D (06/06/94)
50
V
L
/
V
/
d
"<:""_1
o
1
J
~
.e:
I\.
L.--- I-
VGS = 4.25 V
10 - Drain Current (A)
.~
5
4
VGS - Gate-to-Source Voltage (V)
'fransconductance
30
-55'C
/
o
5
10
15
20
25
30
Og - 10tal Gate Charge (nC)
6-103
TEMIC
SMP25N05·45L
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.4
J
as =llOVI
Source-Drain Diode Forward Voltage
100
./
2.0 ; - ID = 12.5 A
~
./
V"
~~"-"-IV~"""-I--+--~
I- TJ = 150°C
/
V"
/
10
/ 'V
-
'/
. / TJ=25°c
V
I
I
"'
I
I
I
V I
o
-50 -25
0
25
50
75
100 125 150 175
0.5
TJ - Junction Thmperature (0C)
0.7
1.1
0.9
1.3
1.5
1.7
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
Maximum Avalanche and Drain Current
vs. Case Temperature
Safe Operating Area
500
30
I WI
25
~
~
"~
20
.~
15
U
Q
I
~
\
10
.fl
5
o
25
1==
Limited by
'DS(on)
"-
U
.~
Q
I
l~
50
75
100 125
150
Tc - Case Thmperature (0C)
~
,
"
10
100
I,
.fl
\
o
1=
"~
,,~
IWI
100
175
--.-.111
Tc = 25°C
SmglePulse
V
0.1
IIII
"'
IllilInS
10 InS
.....
100 InS
de
II
llJ
10
VDS - Drain-la-Source Vollage (V)
100
Normalized Thermal1ransient Impedance, Junction-to-Case
2
II
Duly Cycle - 0.5
0.2
_I-'"
0.1
~
0.05
...-
0.02
,,~
Single Pulse
0.01
10-5
6-104
10-4
10-3
10-2
Square Wave Pulse Duration (sec)
10- 1
3
P-36850--Rev.D (06/06/94)
TEMIC
SMP30NIO
Siliconix
N -Channel Enhancement-Mode Transistor
Product Summary
V(BR)nSS (V)
rnS(on) (Q)
In (A)
100
0.060
30
D
TO-220AB
o
Gcr-J
DRAIN connected to TAB
GDS
S
Top VIew
N-Channel MOSFET
Absolute Maximum Ratings (Tc - 25°C Unless Otherwise Noted)
Parameter
Umlt
Symbol
Dram-Source Voltage
VDS
100
Gate-Source Voltage
VGS
±20
Tc= 100'C
Pulsed Drain Current
ID
18
IAR
30
Avalanche Energy
L=O.3mH
EA
135
Repetitive Avalanche Energy'
L=O.lmH
EAR
45
Tc= 100'C
Operating Junction and Storage Temperature Range
Lead 1l:mperature eft6" from case for 10 sec.)
mJ
100
Tc=25'C
Power Dissipation
A
120
IDM
Avalanche Current
V
30
Tc = 25'C
Continuous Drain Current
Unit
PD
W
40
TJ,T'lg
-55 to 150
TL
300
'C
Thermal Resistance Ratings
Parameter
Junchon-la-Ambient
Symbol
'tYPical
Maximum
RlhJA
80
Junction-la-Case
RthJC
1.25
Case-to·Smk
RthCS
Unit
'c/w
1.0
Notes:
a. Duty cycle s 1%
P-36853-Rev. C (06/06/94)
6-105
TEMIC
SMP30NIO
Siliconix
Specifications (TJ = 25°C Unless Otherwise Noted)
Parameter
Test Condition
Min
TypB
V(BR)DSS
Vas = 0 V, ID = 250 J1A.
100
110
VOS(tb)
VDS - Vas. ID - 250 J1A.
2.0
Symbol
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(on)
Drain-Source On-State
Resistance b
Forward 'fiansconductanceb
VDS =
loss
fDS(on)
ov, Vas =
V
4.0
±100
±20V
VDS = 80 V, Vos = OV
25
VDS = 80 V, Vas = 0 V, TJ = 125'C
250
VDS = 5V,Vos = 10V
30
0.045
0.060
Vas = 10 V, ID = 18 A, TJ = 125'C
0.085
0.100
VDS = 15 V, ID = 18 A
7.0
"A
A
Vos -10V,ID = 18A
gr,
nA
10.0
0
S
Dynamic
Input Capacitance
C;"
Output Capacitance
Co"
c,.,.
Reverse 'fiansfer Capacitance
Thtal Gate Chargee
Qg
Gate-Source Chargee
Qg,
Gate-Drain Chargee
Qgd
Thrn-On Delay TImee
RiseTImee
Thrn-Off Delay TImee
FallTImee
1400
Vas = OV, VDS = 25 V, f= 1 MHz
pF
110
35
VDS = 50
v: Vas = 10V,ID = 30A
td(on)
tr
td(off)
480
ID
~
VDD = 50 V, RL = 1.670
30 A, VOEN = lOV, Ro = 4.70
tf
50
10
19
15
25
10
30
80
120
30
60
15
30
nC
ns
Source-Drain Diode Ratings and Characteristics (fc = 2S·C)
Continuous Current
Is
30
Pulsed Current
ISM
120
Forward Voltage b
VSD
A
IF = 30 A, Vas = OV
1.8
V
Reverse Recovery TIme
trr
130
ns
Reverse Recovery Charge
Q rr
0.45
"C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width S 300!'S. duty cycle S 2%.
c. Independent of operating temperature.
6-106
P-36853-Rev. C (06/06/94)
TEMIC
SMP30NIO
Siliconix
'JYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
50
"
.~
Q
~
8V
40
/J 1/
,
§:
8"
~GS;1O,19V
II /
40
30
§:
"
.
20
Q
6V
~
10
sv
A
0
30
.~
~
10
"~
a
7V
f!J / '
20
4V
o
'fransfer Characteristics
50
2
4
0
0
10
8
6
2
'fransconductance
20
0.08
12
"
"~
."
~I
'"
OIl
4
0
f
~
o
~
.....
--
~
Tc; -SS"C
....-
§
g
2S"C
~.!:
12S"C
0
VGS; lOV
0.06
J
0.02
20
30
40
50
o
..':: 2000
~
I
ID ;30A
g, 12.5
I 1000
U
500
o
~
l'.....
Q,,-
\
o
"
10
20
Ce,,-
VDS;SOVI!
~.b
7.5
0
5.0
~
2.5
0
30
40
VDS - Drain-ta-Source Voltage (V)
P-368S3-Rev. C (06/06/94)
10.0
0
OJ
~
125
150
50
"
J. V
g
(i;'
1500
100
Gate Charge
15.0
~
j
75
ID - Drain Current (A)
2500
a
50
25
Capacitance
3000
7
.--V VGS;20V
-
I
o
10
)
0.04
VGS - Gate-to-Source Voltage (V)
.~
10
On-Resistance vs. Drain Current
0.10
16
€
§
~
6
4
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
//80V
f
/
17
o
20
40
60
80
Og - Total Gate Charge (nC)
6-107
TEMIC
SMP30NIO
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.25
200
2.00
100
./
/'
0.75
..-
V
L
$
-10
30
. /~
-
~
TJ
/
~
I
:::
o
150
110
TJ
II
-,I
I
10
0
til
70
,
150'C
8
/
.... /
0.50
-50
Source-Drain Diode Forward Voltage
2
TJ - Junction Temperature ('C)
= 25'C
5
3
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
50
$
Maximum Avalanche and Drain Current vs.
Case Temperature
40
$
t;
~
3
u
-.....
30
"
.~
Cl
20
oS
100
t;
'"
~
"
25
............
75
50
ro--
Limited
by'DS(on)
lOflS
U
"r- ...'
'OJ
~
Q
I
oS
'-
] I I I I 11
o
Safe Operating Area
500
100
125
10
'"
100 flS
I
t I IIII 1II I111
~ Tc
..... C'o,....
SlOgle Pulse
10
150
Tc - Case Temperature ('C)
1 ms
I
10
~
a~~s
100
VDS - Drain-to-Source Voltage (V)
Normalized Thermal 'fransient Impedance, Junction-to-Case
2
III
:: Duty Cycle
r-
0.5
0.2
~
0.1
-
i=::
~
0.05
i= 0.02
I..........
0.01
10- 5
.... Single Pulse
1111111
10-4
10- 3
10- 2
10- 1
Square Wave Pulse Duration (sec)
6-108
P-36853-Rev. C (06/06/94)
TEMIC
SMP40NIO
Siliconix
N-Channel Enhancement-Mode Transistor
Product Summary
V(BR)nSS (V)
rnS(on) (Q)
In (A)
100
0.040
40
D
TO-220AB
o
Go--J
DRAIN connected to TAB
GDS
S
ThpView
N·Channel MOSFET
Absolute Maximum R.atings (Tc = 25°C Unless Otherwise Noted)
Parameter
limit
Symbol
Drain·Source Voltage
VDS
100
Gate·Source Voltage
VGS
±20
Tc=25'C
Continuous Drain Current
Tc = 100'C
Pulsed Drain Current
25
1AR
40
L=O.3mH
EA
240
Repetitive Avalanche Energy'
L= 0.05 mH
EAR
40
Operating Junction and Storage 'Thmperature Range
Lead Temperature (lh6" from case for 10 sec.)
mJ
125
Tc=25'C
Tc= 100'C
A
160
Avalanche Energy
Power Dissipation
V
40
1D
1DM
Avalanche Current
Unit
W
PD
60
TJ,T,tg
-55 to 150
TL
300
'C
Thermal Resistance Ratings
Parameter
Junction·to·Ambient
Symbol
'iYPical
Maximum
RthJA
80
Junction-la-Case
RthJC
1.0
Case· to-Smk
RthCS
Unit
'c/w
1.0
Notes:
a. Duty cycle s 1%
P-36665-Rev. B (06/06/94)
6-109
TEMIC
SMP40NIO
Siliconix
Specifications (TJ = 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 1tansconductanceb
V(BR)DSS
VGS
~
OY,ID
VGS(tb)
VDS
~
VGs. ID
IGSS
VDS
~
OY, VGS
VDS
IDSS
~
~
2S0J1A
100
~
250 J1A
2.0
~
80Y,VGS
±20V
±1oo
OV
25
~
VDS - 80Y, VGS - OY, TJ -125'C
250
40
VDS - 5 Y, VGS - 10 V
ID(on)
VGS -lOY,ID - 2SA
roS(on)
4.0
VGS ~ lOY, ID
~
2S A, TJ
VDS ~ 15 Y, ID
gr.
~
~
12S'C
25 A
15
V
nA
"A
A
0.030
0.040
0.055
0.072
0
S
W
Dynamic
Input Capacitance
q ..
Output Capacitance
c...
Reverse Transfer Capacitance
Cr..
Thtal Gate ChargeC
Qg
Gate-Source ChargeC
Qgs
Gate-Drain ChargeC
Qgd
Thrn-On Delay TImec
RiseTImec
Thrn-Off Delay TImec
FallTImec
~
OY, VDS
~
25Y, f~ 1 MHz
Ir
td(o!1)
pF
750
150
VDS ~ 50
v: VGS
~
10Y,ID
~
40A
Id(on)
VDD ~ SOY, RL ~ 1.250
ID - 40 A, VGEN ~ lOY, RG ~ 50
tf
Source-Drain Diode Ratings and Characteristics (Tc
Continuous Current
3000
VGS
62
80
20
30
26
35
17
30
80
120
40
60
20
40
nC
ns
=2S'C)
Is
40
Pulsed Current
ISM
180
Forward Voltageb
VSD
IF
~
40 A, VGS
~
OV
Reverse Recovery TIme
trr
120
Reverse Recovery Charge
Q rr
0.3
A
1.8
V
250
ns
"C
Notes:
a For design aid only; not subject to production testing.
h. Pulse test; pulse width s 300!'S. duty cycle S 2%.
c. Independent of operating temperature.
6-110
P-36665-Rev. B (06/06/94)
TEMIC
SMP40NIO
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
Transfer Characteristics
125
~
50
100
~
C
~
'a
t=s
C
9V
~
75
8V
c
40
30
c
'E
50
(:l
20
7V
~
~
25
6V
10
5V
0
0
0
2
4
10
8
2
0
Transconductance
On-Resistance vs. Drain Current
40
Iii
30
'0
c
I
F
20
I
'"
bIl
e-
Tc= -55'C
Il
1:>
:s
10
o
,
~
~
25'C ~
II
5
0.06
0
0.04
~..
12S'C
~
0.08
VGs= 10V
.-/
I
a!
50
25
75
100
I I
o
50
25
I
U
1000
Q,.
o
~
10.0
Vos=50V
'"
7.5
//
C!l
5.0
~
2.5
@
~
- ...
Co..
20
30
10
o
40
VOS - Drain-la-Source Vollage (V)
P-36665-Rev. B (06/06/94)
150
~rt'
A ~v
0
r--.....
o
10 = 40A
12.5
:s
\'
\...S
125
If
I.
€
"
~
J \
2000
100
Gate Charge
15.0
4000
3000
75
10 - Drain Current (A)
Capacitance
~
~
VGs=20V
125
5000
l'-
V ....-
0.02
o
o
J
V GS - Gate-la-Source Vollage (V)
~
10
0.10
50
€
8
VGS - Gate-to-Source Vollage (V)
VOS - Drain-Io-Source Vollage (V)
50
r-----
I
/
o
/
20
40
60
80
100
Og - Thlal Gale Charge (nC)
6-111
TEMIC
SMP40NIO
Siliconix
'JYpical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.25
Cl
1.75
~:;;'
.~ .§ 1.50
./
"f]
a 6 1.25
V
I~
g
1.00
V
§
0.75
~
100
2.00
'8
Source-Drain Diode Forward Voltage
200
V
V
/
g
I-- TJ
"";
U
V
/
~
r5l"
-10
30
",
II
10
-
TJ = 25'C
'"
I
70
110
I
I
1
-50
150'C
-;:::;-
o
150
TJ - Junction Thmperature ('C)
3
2
5
4
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
Maximum Avalanche and Drain Current
vs. Case Temperature
50
Safe Operating Area
500
II
I I
g
40
"""t:
8c
30
............
...
Q
20
I
'" "'
g
~
E
10
0
o
25
50
75
100
--I-j-I'
Limited
by fOS(on)
100
~-
~""
,
"
125
I
r,
I
~1O""
100
...c
Q
~~
10
'. ....
I
~ 1 rns
~,
"
.fl
-
Tc 25'C
Single Pulse
100 rns
/I
150
~ dc
10
TC - Case Thmperature ('C)
. lUrns
L....
I
100
VDS - Drain-to-Source Voltage (V)
Normalized Thermal 1ransient Impedance, Junction-to-Case
2
= -'
JI III
DutyCyc1e
0.5
- o.d
~~
0.;
== 0.05
=
-
0.02
I
~~
0.01
10-5
......
Single Pulse
III
10-4
IJ
10-3
10-2
10-1
3
Square Wave Pulse Duration (sec)
6-112
P-36665-Rev. B (06/06/94)
TEMIC
SMP40P06
Siliconix
P-Channel Enhancement-Mode 1ransistor
175°C Maximum Junction Temperature
Product Summary
V(BR)nSS (V)
rnS(on) (0)
In (A)
-60
0.045
-40
S
TO-220AB
o
DRAIN connected to TAB
GDS
D
Top VIew
P-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain·Source Voltage
VDS
-60
Gate-Source Voltage
Vas
±20
V
Tc~25'C
Continuolls Dram Current
Tc
~
100'C
Pulsed Drain Current
Avalanche Current
~
Avalanche Energy
L
Repetitive Avalanche Energy"
L~0.05mH
Tc
~
25'C
Tc
~
100'C
Power Dissipation
Operating Junction and Storage Temperature Range
0.1 mH
Unit
-40
1D
-30
1DM
-100
1AR
-40
EAS
90
EAR
45
A
mJ
125
W
PD
62
-55 to 175
TJ, Tstg
'C
Thermal Resistance Ratings
Parameter
Symbol
Junction-ta-Ambient
RthJA
Junction-to-Case
RthJC
Case-to-Sink
Rthcs
'JYpic:al
Maximum
Unit
80
1.2
'c/w
1.0
Notes:
a. Duty cycle s 1%.
P-36665-Rev. C (06/06/94)
Preliminary
6-113
TEMIC
SMP40P06
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
1YP"
Symbol
Test Condition
Min
Max
V(BR)DSS
VGS = 0 V, 10 = -250 J1A
-60
VGS(tb)
Vos = VGS, 10 = -1 rnA
-1
IGSS
Vos=OV,VGS= ±20V
±5oo
Vos = -48 V,VGS = OV
-25
Vos - -48 V, VGS - 0 V, TJ - 125'C
-250
Vos = -48 V, VGS = Ov, TJ = 175'C
-500
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
loss
Vos = -10V, VGS = -10V
10(on)
VGS -10V, lo=-20A
Drain-Source On-State Resistanceb
FOlWard 'fransconductanceb
roS(on)
-3
-40
J1A
0.045
0.080
VGS - -10 V, 10 - -20 A, TJ -175'C
0.090
VOS = -15 V, 10 = -20A
nA
A
0.038
VGS = -10V,lo = -20 A, TJ -125'C
gls
V
28
Q
S
Dynamic"
Input Capacitance
C;"
Output Capacitance
Cess
Reverse 'fransfer Capacitance
Cr..
Thtal Gate ChargeO
Qg
Gate-Source ChargeO
Qgs
Gate-Drain Charge"
Qgd
111rn-On Delay TImeo
RiseTImeo
111rn-Off Delay TImeo
FallTImeO
2600
VGS = OY, VOS = -25V,f= 1 MHz
td(olf)
pF
200
60
VOS = -30 V, VGS = -10V,lo = -40A
td(on)
tr
800
Voo = -30V,RL = 1.5 Q
10 s -20 A, VGEN = -lOY, RG = 2.5 Q
tl
Sour~e-Draln Diode Ratings and Characteristics (Tc
100
15
20
17
50
11
30
12
35
70
140
75
150
-40
Pulsed Current
ISM
-100
FOlWard Voltageb
VSO
Reverse Recovery TIme
Peak Reverse Recovery Current
Reverse Recovery Charge
IF = -40 A, VGS = OV
-1.2
81
trr
IRM(REC)
tIS
= ZS·C)
Is
Continuous Current
nC
IF = -40 A, dlF/dt = 100 AlJ1S
Q rr
-16
A
V
ns
7
A
0.3
!,C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 !,S, duty cycle S 2%.
c. Independent of operating temperature.
6-114
Preliminary
P-36665-Rev. C (06/06/94)
TEMIC
SMP40P06
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Output Characteristics
'fransfer Characteristics
160r-----r-----r----.-----,-----,
~-~--_+--+---f--_j
140
$
50r------r------.----,~r-----_.
401----+---I---4F=i 125'C
120~----~----~--~----~~~~
301----+---1--~-_r--~
20r------+------~E_----+-----~
101----+--~f_--_r--~
OE-__
~
o
____
~
____L -_ _
4
2
~
6
____
8
OL-____
~
1lc 0.045
VGs= 10V
.j
~
c
1
!
0.040
E!
,/
g
/"
1'-
2500
Co
a
1
V
,/
U
2000
\
1500
1000
500
10
20
30
40
50
60
70
8
6 -
2
o
2.0
1.8
e!-
/
Vns=30V
In=40A
/
o
/
8
/
1.4
c ..
1.2
&!'a
,s
E!
30
40
Og - Thtal Gate Charge (nC)
P-36665-Rev. C (06/06/94)
40
60
50
On-Resistance vs. Junction Temperature
r-
ILJOA
I
1.6
.;;j ~
~~
!
20
30
V
!ii~
If
10
20
10
_"tl
/
4
(!)
~
~
c,,,
Vns - Drain-to-Source Voltage (V)
/
~
~
"\
~0
80
Gate Charge
10
bl"
C;"
;:I
.~
In - Drain Current (A)
§
----
0
o
"
~
~
8
Capacitance
~ 3000
~
0.035
t;f'
6
3500
. . . .V
0
_ _ _ _ _ _L __ _ _ _
4
4000
/
/
~_L
VGS - Gate-tD-Source Voltage (V)
On-Resistance vs. Drain Current
e!-
__
2
Vns - Drain-to-Source Voltage (V)
0.050
~
o
10
50
60
/
1.0
0.8
/'
V
V
/
/
V
VGs= 10V
V
0.6
-50 -25
0
25
50
75
100 125 150 175
TJ - Junction Temperature (OC)
Preliminary
6-115
TEMIC
SMP40P06
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Source-Drain Diode Forward Voltage
100
g
g
/
~
u"
~
75
I-- TJ = 150'C f I f
;;
6
,
'"
"t:
-
a
45
0
30
, ..........
.~
TJ = 25'C
'"
60
;;
//
10
Maximum Avalanche and Drain Current
vs. Case temperature
J
0.4
1.2
1.6
o
2.0
25
Threshold Voltage
0.5
8
0.0
r--.. r--..
I
........
:[
13
>
-1
-50 -25
g
\
25
50
75
125
150
I~~ JlS
100
a
- Limited
- byroS(TI*
.~
~
175
1111
......
0
,
/
10
~
100 125 150 175
"-
'l'e
'\
IIII
1111
1 ms
10 ms
'1"OOms
Tc= 25'C
~
Single Pulse
11/111111111
0
100
;;
r--.. ........
-0.5
75
Safe Operating Area
300
ID -lmA
1"000..
50
Tc - Case Thmperature ('q
1.0
.3
~
0
0.8
Vso - Source-ta-Drain Voltage (V)
~
.........
~
15
o
~
..........
0.1
TJ - Thmperature ('q
111111111
Iffillm
10
100
VDS - Drain-to-Source Voltage (V)
Normalized Thermal1ransient Impedance, Junction-to-Case
2
IJ II
Duty Cycle - 0.5
r
0.2
0.1
i"""""
0.05
0.02
".
1 sJ~11
0.01
10-5
ri1 j
S
10- 4
10-3
10- 2
Square Wave Pulse Duration (sec)
6-116
Preliminary
P-36665-Rev. C (06/06/94)
TEMIC
SMP50N06·25
Siliconix
N-Channel Enhancement-Mode MOSFET, 25-mQ rDS(on)
175°C Maximum Junction Temperature
Product Summary
V (BR)DSS (V)
fDS(on) (0)
ID (A)
60
0.025
46
D
TO-220AB
o
DRAIN connected to TAB
GDS
S
ThpView
N-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Symb4>l
Limit
Drain-Source Voltage
Parameter
VDS
60
Gate-Source Voltage
Vas
±20
Tc= 100°C
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Avalanche Current
ID
32
IDM
200
Is
46
IAR
46
Avalanche Energy
L= O.lmH
EAS
125
Repetitive Avalanche Energy"
L- 0.05mH
EAR
62.5
Tc= 100'C
Operating Junction and Storage 1l:mperature Range
Lead 1l:mperaturc eh6" from case for 10 sec.)
A
mJ
105
Tc-25'C
Maximum Power Dissipation
V
46
Tc = 25°C
Continuous Drain Current (TJ = 175°C)
Unit
Po
W
53
TJJ Tstg
-55 to 175
TL
300
'c
Thermal Resistance Ratings
Parameter
Symb4>l
'tYPical
Maximum
Maximum Junction-ta-Ambient
RtbJA
80
Maximum Junction-ta-Case
RtbJC
1.4
Case-to-Sink
RthCS
Notes:
a. Duty cycle
Unit
'c/w
1.0
s 1%
P-37393-Rev. E (06/20/94)
6-117
TEMIC
SMP50N06-25
Siliconix
Specifications (TJ = 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
V(BR)DSS
VGS = ov, ID = 250
Min
'lyP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
iJA
60
VGS(th)
VDS = VGS.ID - lmA
2
IGSS
VDS = Ov, VGS = ±20V
±500
VDS - 48 V, VGS - OV
25
IDSS
ID(on)
V
4
VDS - 48 V, VGS - 0 V, Tr - l25'C
250
VDS - 48 V, VGS - OV,Tr -l75'C
500
VDS= lOV,VGs=10V
46
0.020
VGS = 10 V, ID = 25 A, Tr = 125'C
0.033
0.042
VGS = 10 V, ID = 25 A, Tr = 175'C
0.043
0.0525
gf.
VDS = 15 V, ID = 25 A
20
Output Capacitance
Q"
Co..
VGS = Ov, VDS = 25V,f= 1 MHz
Reverse 'fransfer Capacitance
c,."
120
Thtal Gate Charge
Qg
55
Forward 'fransconductanceb
roS(on)
iJA
A
VGS = 10V,ID = 25A
Drain-Source On-State Resistanceb
nA
0.025
Q
S
DynalJlic
Input Capacitance
Gate-Source Charge
Qg.
Gate-Drain Charge
Qgd
Thrn-On Delay TIme
Rise TIme
Thrn-Off Delay TIme
Fall TIme
2000
570
nC
80
9
15
24
40
td(on)
15
30
1r
20
35
40
65
15
30
td(off)
VDS = 30 V, VGS = 10 V, ID = 50A
VDD = 30 V, RL = 0.6 Q
ID ,,50A, VGBN = 10 V, RG = 2.5 Q
tf
ns
Source-Drain Diode Ratings and Characteristics
Diode Forward Voltageb
VSD
Reverse Recovery TIme
trr
Peak Reverse Recovery Current
Reverse Recovery Charge
IRM(rec)
Q rr
2.0
IF = 46 A, VGS = OV
130
IF = 46 A, dildt = 100 Nils
V
ns
10
A
0.7
IIC
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 lIS. duty cycle s 2%.
6-118
P-37393-Rev. E (06/20/94)
TEMIC
SMP50N06·25
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
1ransfer Characteristics
Output Characteristics
50
50
40
40
§::
~.;"
"
Q
.E
§::
6V
30
"~
30
Q
20
8
'e"
20
5V
.E
10
10
4V
0
0
0
2
4
10
6
2
0
1ransconductance
25
e..
!l
!!
€
j
'g
15
§
li
E!::
10
I
...
bO
5
0.025
0.020
~
0
0.Q15
J
0.010
0
Vas
--
10
20
30
40
20
~
Ii:' 3000
U 1000
o
~
6
~
4
~
Coss
~
2
0
10
20
30
40
Vos - Drain-to-Source Voltage (V)
P-37393-Rev. E (06(20/94)
50
II
8 -
~
@
=
a
Ctss
~~-
o
60
80
Gate Charge
10
E
u
~
40
10 - Drain Current (A)
Capacitance
I
-
I
o
50
4000
a
IL
Vas=20V
Vas - Gate-to-Source Voltage (V)
·12000
10
8
0.005
0
,e,
6
On-Resistance vs. Drain Current
0.030
30
20
4
Vos - Gate-to-Source Voltage (V)
Vos - Drain-to-Source Voltage (V)
Vos = 30V
10=50A
,/
/
o
/
V
/
/
/
10
20
30
40
50 55
Qg - Thtal Gate Charge (nC)
6-119
TEMIC
SMP50N06-25
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.4
I~
2.2 I- In
e.
2.0
~~
1.8
~25A
~
_"0
.~.~ 1.6
,/
~Ol
'= E
1.4
~
1.0
O~
~ ~ 1.2
V
, /V
0.8
0.6 ~
-20 -40
VGS~
0
V
J
Source-Drain Diode Forward Voltage
100
J
I
s
-T]
125'C
.-
./
/'
~
13
u
~
r5l"
JV I
10
-
./
/'
/
T]-2S'C
L
'"
10V
I
I
40
80
120
160
200
0.5
TJ - Junction'Thmperature ('C)
0.7
0.9
1.3
1.1
VSD - Source-ta-Drain Voltage (V)
Thermal Ratings
Maximum Avalanche and Drain Current
vs. Case 'Thmperature
SO
Safe Operating Area
500
III
11111
S
~
;;
~
30
Ci
20
"
111111111
~
40
.;
I
.fl
10
S;;
100
o
SO
25
75
100
125
150
~
.'
"
Ci
I
10
.fl
~I'
,=
'T,..-25'C ' Single Pulse
/
IJW ] 11111111
175
0.1
Tc - Case 'Thmperature ('C)
I~O ~
III III
1001'S
byrnS(oo)
.;
\
o
""17~==
ml
~
1\
1\
.-:-.,
10
'lms
III I
10ms
,
'"lOOms
tff
100
500
Vns - Drain-la-Source Voltage (V)
Normalized Thermal 'fransient Impedance, Junction-to-Case
2
II I
Duty Cycle
~
~
0.5
0.2
-
0.1
0.05
-",
;;;-
...--
0.02
V
0.01
10-5
J..-'Single Pulse
I 1-11111
10-4
10-3
10-2
10- 1
3
Square Wave Pulse Duration (sec)
6-120
P-37393--Rev. E (06/20/94)
TEMIC
SMP60N03-10L
Siliconix
N-Channel Enhancement-Mode lransistor, Logic Level
Product Summary
V(BR)DSS (V)
fDS(on) (Q)
ID (A)
30
0.01
60
D
TO·220AB
o
Go--J
DRAIN connected to TAB
GDS
S
Top View
N·Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Symbol
Limit
Drain·Source Voltage
Parameter
VDS
30
Gate·Source Voltage
Vas
±20
V
60
Tc=25'C
Continuous Drain Current
Tc = 100'C
Pulsed Drain Current
Iv
51
IAR
60
Avalanche Energy
L=O.lmH
EAS
180
Repetitive Avalanche Energy"
L= 0.05mH
EAR
90
Tc = 100'C
Operating Junction and Storage Temperature Range
Lead 'Thmperature (lft6" from case for 10 sec.)
mJ
105
Tc=25'C
Power Dissipation
A
240
IDM
Avalanche Current
Unit
W
PD
TJI
42
-55 to 150
Tstg
'c
300
TL
Thermal Resistance Ratings
Parameter
Symbol
lunction-ta-Ambient
RthJA
Junction-lo-Case
RthJC
Case·ta-Sink
RthcS
'JYplcal
Maximum
Unit
80
1.2
'CIW
10
Notes:
a. Duty cycle s 1%
P·36851-Rev. C (06/06/94)
6·121
TEMIC
SMP60N03-10L
Siliconix
Specifications (TJ = 25°C Unless Otherwise Noted)
Parameter
Min
1yP"
Symbol
Test Condition
Max
V(BR)DSS
vGS = 0 Y, 10 = 250 I1A
30
VGS(th)
VOS = VGS, 10 = 1 rnA
0.8
IGSS
VOS = OY,VGS = ±20V
±500
Vos = 24 Y,VGS = OV
25
Vos = 24 Y, VGS - 0 Y, TJ = 125'C
250
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward Transconductanceb
loss
10(00)
Vos = lOY, VGS = lOV
60
V
nA
I1A
A
VGS -lOY, 10 - 30A
0.007
0.010
VGS = 5Y,lo = 30A
0.010
0.Q15
VGS = 10 Y, 10 = 30 A, TJ = 125'C
0.009
0.014
Vos = 15Y,Io = 30A
45
TDS(on)
Sf.
3.0
0
S
Dynamic
Input Capacitance
Y..
Output Capacitance
Co..
c,...
Reverse 'fransfer Capacitance
Thtal Gate Chargee
Qg
Gate-Source Chargee
Q gs
Gate-Drain Chargee
Qgd
Thrn-On Delay TImee
td(an)
RiseTImee
Thrn-Off Delay TImee
FallTImee
t,
td(olf)
2600
VGS = OY,Vos = 25Y, f = 1 MHz
1500
pF
750
100
VOS = 15V:VGS = lOY, 10 = 60A
Voo = 30Y,RL= 10
10 - 30 A, VGEN = lOY, RG = 2.5 0
tl
120
10
15
45
75
14
30
25
50
65
100
45
80
nC
ns
Sonrl
limit
Drain-Source Voltase
VDS
-100
Gate-Source Voltage
VGS
±20
Unit
V
Tc~25'C
Continuous Drain Current (T]
~
150'C)
Tc
~
100'C
Pulsed Drain Current
Avalanche Current
L~005mH
Repetitive Avalanche Energy"
-20
ID
-13
IDM
-80
IAR
-20
20
EAR
Tc~25'C
Maximum Power Dissipation
Tc~100'C
Operating Junction and Storage Thmperature Range
Lead Thmperature eh6" from casc for 10 sec.)
A
mJ
150
PD
W
60
T],T,tg
-55 to 150
TL
300
'C
Thermal Resistance Ratings
Parameter
Symb(}l
Maximum Junction-to-Ambient
RthJA
Maximum Junction-to-Case
RthJC
Case-to-Sink
Rthcs
'iYpical
Maximum
Unit
40
0.83
'CIW
0.35
Notes:
a. Duty cycle s 1%
P-35259-Rev. C (05/16/94)
6-133
TEMIC
SMW20PIO
Specifications (TJ
Siliconix
= 25°C Unless Otherwise Noted)
Limit
Parameter
Symbol
Test Condition
Min
TypB
Max
Unit
Statie
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 'llansconductanceb
V(BR)DSS
VGS(tb)
IGSS
IDSS
-100
Vos = VGS. ID =
-2.0
V
-4.0
VOS - Ov, VGS = ±20 V
±100
VOS = -80 V, VGS = OV
-25
-250
VDS - -80 V, VGS - 0 V, TJ - 125'C
VDS = -1O V, VGS = -lOV
Io(on)
TOS(on)
fLA
-250 fLA
VGS = 0 V, ID = -250
-20
0.14
0.20
VGS = -10V,Io = -13A, TJ = 125'C
0.22
0.32
VOS = -15V,IO = -13 A
5.0
fLA
A
VGS = -10 V, 10 = -13A
8f.
nA
6
g
S
Dynamic
Input Capacitance
C;"
Output Capacitance
Co..
c,.,.
Reverse'llansfer Capacitance
Thtal Gate ChargeC
Og
Gate-Source ChargeC
Og,
Gate-Drain ChargeC
'Ibm-On Delay TImec
RiseTImec
'Ibm-Off Delay TImec
FallTImec
1300
VGS = Ov, VOS = -25 V, f = 1 MHz
700
pF
250
47
62
10
15
Ogd
27
35
td(on)
10
30
tr
50
80
25
80
15
60
td(olf)
VDS= - 50 V, VGs= -10V,ID = -20A
ID
~
Voo = -50 V, RL = 2.5 g
-20 A, VGEN = -10V, RG = 4.7 g
tf
nC
ns
Souree-Draln Diode Ratings and Characteristics
Is
-20
Pulsed Current
ISM
-80
Diode Forward Voltageb
VSD
Reverse Recovery TIme
Irr
Reverse Recovery Charge
Orr
Continuous Current
A
-2.0
IF = -20 A, VGS = OV
IF = -20 A, dildl = 1OON)ls
V
150
ns
0.3
)lC
Noles:
a For design aid only; not subject to production testing.
Pulse test; pulse width S 300 JlS. duty cycle S 2%.
Independent of operating temperature.
b.
c.
6-134
P-35259-Rev. C (05/16/94)
TEMIC
SMW20PIO
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Output Characteristics
25
D-ansfcr Characteristics
12.5
Tc= -55"C
9V
25"C~
20
10.0
S
E
~
::s
7V
U
.~
Q
E
~
::s
15
.~
Q
6V
I
.B
7.5
U
10
.B
5V
5.0
/
2.5
4V
0
~
0
0
2
6
o
10
8
J
I(
4
2
VDS - Drain-to-Source Voltage (V)
10
6
Vas - Gate-to-Source Voltage (V)
D-ansconductance
12.5
1ls"c
~
S
BV
V
On-Resistance vs. Drain Current
125
l
Tc = _ssoci
10.0
~
'::s"
"""§"
"'"
F;
7.5
5.0
I
'"
bIl
2.5
1.00
~-
€
,.
~
~
8
2S"C
I
Ii
125"C
~
",-
,
0.75
.f!)
d
0 0.50
:Il
!
e
Vas=10V
o
0
o
10
20
30
40
.-r
0.25
50
o
15
ID - Drain Current (A)
Vas=OV
~
2500
"
1
.g.
Ii:'
j
'[ij 1500
a
I
1000
U
500
o
~1C;ss
~
r5l
9
~
I--.
"
o
~oss
10
c,."
I
20
30
ID = 20A
12.5
V"'"~(
10.0
7.5
\!l
5.0
~
2.5
o
40
VDS - Drain-to-Source Voltage (V)
P-35259-Rev. C (05/16/94)
I
::s
\' ---r-r--
60
75
Gate Charge
15.0
I
.e 2000
45
ID - Drain Current (A)
Capacitance
3000
30
20V
50
V
/
/
V
o
15
30
45
60
75
Og - Thtai Gate Charge (nC)
6-135
TEMIC
SMW20PIO
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity,
On-Resistance vs, Junction Temperature
1.75
/
1.50
~
L
8
:i~
~'"
.~~
, .e
1.25
V
~
"~
~~
1.00
I
0,75
V
.J$
100
~
..-
S
"
~
if'
/'1 TJ=25"C
T J=150"C
8
!!
10
"
'"
0
-
../
0.50
-50
Source-Drain Diode Forward Voltage
200
~
I
0
-10
70
30
110
o
150
3
2
TJ - Junction Thmperature ("q
5
4
VSD - Source-tcrDrain Voltage (V)
Thermal Ratings
Maximum Avalanche and Drain Current
vs. Case Temperature
25
100
Safe Operating Area
=
=
10,,"
I
Limitedby
S
20
""
15
Cl
10
~
.............
~
U
'il"
I
S
"-
"-
.fl
5
o
~"
,
i'~
I
.fl
-
1 ms l
"
,
Q
I
"' I"
10
'a"
100
<
lDS(on)
10ms
100 ms
Tc=25'C
dc
Single Pulse
I
0,5
o
25
50
Tc
75
100
125
150
10
- Case Temperature (" q
100
200
VDS - Drain-to-Source Voltage (V)
Normalized Thermal 'Iransient Impedance, Junction-to-Case
2
II
Duty Cycle
0.5
0,2
~
0,1
0,05
-
0,02
0,01
V
10-5
'"
~ Single Pulse
I 1'111111
10-4
10- 3
10-2
10- 1
3
Square Wave Pulse Duration (sec)
6-136
P-35259-Rev, C (05/16/94)
TEMIC
SMW45NIO
Siliconix
N-Channel Enhancement-Mode Transistor
Product Summary
V(BR)DSS (V)
rDS(on) (Q)
ID (A)
100
0.040
45
D
TO·247AD
) 0 (
G~
l
S
G D S
Top View
N·Channel MOSFET
Absolute Maximum Ratings (Tc
Parameter
25°C Unless Othenvise Noted)
Symbol
Limit
Drain-Source Voltage
VDS
100
Gate-Source Voltage
VGS
±20
Tc = 100°C
Pulsed Drain Current
ID
27
IAR
45
Avalanche Energy
L = 0.3 mH
EA
300
RepetitIVe Avalanche Energya
L=O.02mH
EAR
20
m]
150
Tc = 25°C
Power Dissipation
Tc = 100°C
Operating Junction and Storage Temperature Range
Lead Temperature eft6" from case for 10 sec.)
A
180
IDM
Avalanche Current
V
45
Tc = 25°C
Continuous Drain Current
Unit
PD
W
60
TJ, Tstg
-55 to 150
TL
300
°C
Thermal Resistance Ratings
Parameter
Symbol
lunchon-la-Ambient
RthJA
J unction-to-Case
RthJC
Case· to-Sink
RthCS
'lYpical
Maximum
Unit
40
0.83
°CIW
0.35
Notes:
a.
Duty cycle ,;; 1%
P·37392-Rcv. C (06/20/94)
6-137
TEMIC
SMW45NIO
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
V(BR)DSS
Vas = OVoID = 250 ~A
100
Vas(th)
VDS = Vas, ID = 250 ~
2.0
lass
VDs=OV,Vas= ±20V
±100
VDS = 80 V, Vas = OV
25
VDS - 80 V, Vas - 0 V, TJ - 125'C
250
'JYp'
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(on)
Drain-Source On-State
Resistanceb
Forward 'fransconductanceb
£DS(nn)
gr,
VDS - 5V,Vas -10V
\
45
nA
~A
A
Vas - 10 V, ID = 27 A
0.030
0.040
Vas = 10 V, ID = 27 A, TJ = 125'C
0.058
0.072
VDS = 10 V, ID = 27 A
V
4.0
15
Q
S
Dynamic
Input Capacitance
Cj"
Output Capacitance
Cess
Reverse 'fransfer Capacitance
c,."
Thtal Gate ChargeC
Qg
Gate-Source Chargee
Qg,
Gate-Drain ChargeC
Qgd
Thrn-On Delay TImec
td(nn)
RiseTImec
Thrn-Off Delay TImec
FallTImec
tr
Icl(olf)
3000
Vas = OV,VDS = 25V,f= 1 MHz
750
pF
150
VDS = 50 V; Vas = 10V,ID = 45 A
VDD = 50V,RL = 1.1 Q
ID = 45 A, VaEN = 10V,Ra = 2.5 Q
II
72
100
26
35
31
40
17
30
80
120
40
60
20
40
nC
ns
Source-Drain Diode Ratings and Characteristics (Tc = 25°C)
is
45
Pulsed Current
ISM
180
Forward Voltageb
VSD
Cominuous Currem
Reverse Recovery TIme
trr
Reverse Recovery Charge
Q rr
2.5
IF = 45 A, Vas = OV
IF = 45 A, dlF/dt = 100 N~
A
V
130
ns
0.31
~C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 ~s, duty cycle S 2%.
c- Independent of operating temperature.
6-138
P-37392-Rev. C (06/20/94)
TEMIC
SMW45NIO
Siliconix
'iYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
'll-ansfer Characteristics
125 ,----,-----"-,----,----::MO---,
50
f-----I--....,.£...-+---1----1
40
100
S
E
~
75
"
Q
50
t--+-v-~"'---t---I'----I---j
20
25
hfH.A----j---t--
10
'01
a
30
o
~--~-~'---~'---~--~
a
2
6
10
o
2
VDS - Drain-Io-Source Voltage (V)
'll-ansconductance
"
"8
0.08
30
"C
20
'"
10
OIl
~
Tc = -55°C
~
F:
a
,~
~
§
25°C -
,---
II
~
1i5°C
~
25
50
75
100
0
0.04
J
0.02
'-" l,......-o
25
50
~
1 \
u 2000
I
U
1000
a
\'- I'...
~
a
j
-
10
Cjss
20
40
VDS - Drain-la-Source Vollage (V)
P-37392-Rev. C (06/20/94)
I
100
125
50
I
150
~
ID = 45A
12.5
~
10.0
c2"
7.5
~
Cess
30
1
Gate Charge
15.0
€
3000
75
ID - Drain Currenl (A)
Capacitance
~
-
VGs=20V
125
5000
4000
V
VGs= 10V
a
a
J
0.06
VGS - Gale-la-Source Voltage (V)
~
10
On-Resistance vs. Drain Current
40
§
~
6
0.10
50
€
4
V GS - Gale-Io-Source Voltage (V)
g
~
\!l
5.0
~
2.5
VDS=50V~ ~
I.
~OV
/
aV
a
/
20
40
60
80
100
Q g - 'lbtal Gale Charge (nC)
6-139
TEMIC
SMW45NIO
Siliconix
lYPical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Thmperature
~
e-II
ll~
l~
2.25
200
2.00
100
1.75
1.50
=@
~ ~ 1.25
l
a
1.00
0.75
/
V
./
/'
V
V
Source-Drain Diode Forward Voltage
~~
~
-.=
"
~
V
"
10
0
'",
-10
30
TJ = 25'C
1/
§
'"
I
I
0.50
-50
'(/
I- TJ = 150'C /
70
110
o
150
J
0.5
1.0
1.5
2.0
2.5
VSD - Source-to-Drain Voltage (V)
TJ - Junction Thmperature ("C)
Thermal Ratings
Maximum Avalanche and Drain Current
vs. ease Temperature
50
"-
~
40
~
-.=
~
Q
,
Safe Operating Area
300
I
~ted
100
.........
30
...c
20
'"
oS
10
-.=
... ,
~
",
~
8
·e1=1c
25
50
75
100
125
10 ""
100""
.....
lms
,
lOms
oS
100 ms
I-- Tr= 25'C
del
Single Pulse
10
150
Tc - Case Thmperature ("C)
100
200
VDS - Drain-ta-Source Voltage (V)
Normalized Thermal 'Il:-ansient Impedance, J unction-to-Case
2
1= Duty Cycle = 0.5
!~
.~1
r-
].s
1i11
~
i."
10
0.6
o
I
,::- ~t'-.
by lDS(oo)
~
0
-.=
I
O.~
....
0.1
0.1
ill!
~ 0.05
-
~~
i= 0.02
~
v . . ~~
e
iiNrPulsel
0.01
10-5
10-4
10-3
10- 2
10- 1
3
Square Wave Pulse Duration (see)
6-140
P-37392-Rev. C (06/20/94)
TEMIC
SMW60N06·18
Siliconix
N-Channel Enhancement-Mode Transistor, 1S-mQ rDS(on)
Product Summary
V(BR)OSS (V)
rOS(on) (0)
10 (A)
60
0.018
60
o
TO-247AD
DOl
Go-J
l
S
G D S
ThpView
N·Channel MOSFET
Absolute Maximum Ratings (Tc
= 25°C Unless Otherwise Noted)
Parameter
Symbol
Unit
limit
Drain-Source Voltage
VDS
60
Gate-Source Voltage
VGS
±20
V
60
Tc = 2S·C
Continuous Drain Current
Tc = 100·C
ID
40
A
Pulsed Drain Current
240
IDM
IAR
60
Avalanche Energy
L=O.lmH
EAS
180
Repetitive Avalanche Energya
L=0.05mH
EAR
90
Avalanche Current
CI)
mJ
105
Tc = 2S·C
Power Dissipation
Tc = 100·C
Operating Junction and Storage 1l:mperature Range
Lead Temperature (1116" from case for 10 sec.)
W
PD
42
T}. Tstg
-55 to 150
TL
300
Symbol
·C
'JYpical
Maximum
Junction-ta-Ambient
RthJA
40
Junction-ta-Case
RthJC
1.0
Case-Io-Smk
RthCS
Unit
.C/W
035
Notes:
a Duty cycle $1 %
P-368S1-Rev. D (06/06/94)
=~
=1";I;:l
~r;..
U OO
~O
I~
Z
Thermal Resistance Ratings
Parameter
-
6-141
TEMIC
SMW60N06·18
Siliconix
Specifications (TJ = 25°C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
ov, 10 = 2S0IJA
60
VOS(th)
Vos - Vos, 10 -lmA
2.0
loss
Vos = OV,Vos = ±20V
±500
Vos = 48 V, Vos = OV
25
Vos = 48 V, Vos = 0 V, TJ = 125°C
250
Zero Gate Voltage Drain Current
loss
On-State Drain Currentb
lo(on)
Drain-Source On-State
Resistanceb
Forward'Iransconductanceb
Vos =
V(BR)DSS
roS(on)
Vos = 10V, Vos = 10V
V
4.0
60
~A
A
Vos = 10V, 10 = 30A
0.013
0,018
Vos = 10 V, 10 = 30 A, TJ - 125°C
0.023
0.030
Vos = 15 V, 10 = 30A
45
Sf.
nA
0
S
Dynamic
Input Capacitance
Cj"
Output Capacitance
c...
Reverse 'fransfer Capacitance
c,,,
Thtal Gate ChargeC
Qg
Gate-Source ChargeC
Qgs
Gate-Drain ChargeC
Qgd
1IIrn-On Delay TImec
RiseTImec
1IIrn-Off Delay TImec
FallTImec
2600
Vos = OV, Vos = 25V,f = 1 MHz
tcl(oll)
85
Vos = 30
v: Vos = lOV,lo = 60A
Voo = 30V,RL= 10
10 - 30 A, VOEN = 10 V, Ro = 2.5 0
tl
SClUrce-Drain Diode Ratings and Characteristics (l'c
Cui1tinuuu~ Current
pF
200
ldeon)
tr
800
100
15
20
35
50
15
30
20
35
50
65
15
30
:
bO
0
20
25
-V
5
VGS ~ OV
~
~ 10.0
~
~ 1500
.!!
.~
U
500
----
o
o
10
20
30
~ss
-
40
Vns - Drain-to-Source Voltage (V)
P-37010-Rev. A(06/06!94)
-
r--
20
25
Jns
~
II'~
40
50
~
50V
sov
"a
7.5
t!l
5.0
I
~
2.5
II
~'iii
C;"
...........
c,ss~
15
l
In ~6.5A
€ 12.5
"
H
2000
1000
10
Gate Charge
15.0
I
I
20V
In - Drain Current (A)
Capacitance
a \.
~'\::: r--
V
I
o
In - Drain Current (A)
2500
10
O.S
.~
f/
F:
S
-55°C
e:,
I
3
6
On-Resistance vs. Drain Current
1.0
.L'
4
€
8
".
1:>
~
4
VGS - Gate-ta-Source Voltage (V)
Vns - Drain-to·Source Voltage (V)
11
II
0
50
o
10
Qg
20
-
30
Total Gate Charge (nC)
6-167
TEMIC
2N6849
Siliconix
1YPical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
On-Resistance vs. Junction Temperature
2.00
e~
"'~
~"O
1.50
V
.~ .~
~"iil
E 1.25
d
v
1.75
V
0:£
,~
J
1.00
0.75
o
..,-V
"'"
-so
Source-Drain Diode Forward Voltage
200
100
TJ
S;:
,
~
a
10
0
.At'
TJ=25°C _
/
§
"
'"
150°C
,!!;
J
h
0
-10
30
70
o
150
110
2
TJ - Junction Thmperature (0C)
5
4
3
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
Maximum Avalanche and Drain Current
vs. Case Temperature
10
S;:
~c
Safe Operating Area
10°mll~.
8
I-U:t:;-~· I?I:~
6
.............
.~
Q
10
~
I
.9
2
0
o
25
so
75
100
I
~ro~S(~on~)~II~'II~l~OO~JlS~11
E
.=
.'",
"
10,:,
'I.....
1ms
10~1
"-
125
\
0.1
10
150
TC - Case Temperature CC)
100
1000
VDS - Drain-to-Source Voltage (V)
Normalized Thermal 1l-ansient Impedance, Junction-to-Case
2
II
-
Duty Cycle - 0.5
P"
0.2
.---
0.1
....
:iii"'"
~~
0.05
0.02
-'
,.
singlePu~
0.01
10-5
10-4
10-3
10-2
10-1
Square Wave Pulse Duration (sec)
6-168
P-37010-Rev A(06/06i94)
TEMIC
2N6851
Siliconix
P-Channel Enhancement-Mode Transistor
Product Summary
V(BR)nSS (V)
rnS(on)
-200
(Q)
0.80
In (A)
-4.0
Parametnc limits in accordance with MIL-S-19500/564 where applicable.
S
TO-205AF
(TO-39)
D
Top VIew
P-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Symbol
Limit
Drain-Source Voltage
Parameter
VDS
-200
Gate·Source Voltage
Vas
±20
Continuous Drain Current (TJ = 150'C)
JD
-2.4
Pulsed Drain Current
JDM
-20
Avalanche Current
JAR
-3.1
ITc = 100'C
PD
10
TJ,Tstg
-55 to 150
TL
300
Symbol
Limit
Maximum Junction-ta-Ambient
RthJA
175
Maximum JunctIon-ta-Case
RthJC
5.0
Operating Junction and Storage Thmperature Range
Lead Thmperature (lh6" from case for 10 sec.)
A
25
I Tc=25'C
Maximum Power Dissipation
V
-4.0
I Tc=25'C
I Tc = 100'C
Unit
W
·C
Thermal Resistance Ratings
Parameter
P-37010-Rev. A(06/06/94)
Unit
'C(W
6-169
TEMIC
2N6851
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Limit
Parameter
Symbol
Min
Test Condition
JYpa
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VGS(tb)
IGSS
Zero Gate Voltage Drain Current
loss
On-State Drain Currentb
10(on)
Drain-Source On-State Resistanceb
Forward 'fransconductanceb
roS(on)
Sf.
VGS =
a V, 10 =
-1000
VOS = VGS. 10 = -250
I1A
I1A
-200
-4.0
-2.0
VOS= OV,VGS= ±20V
±100
Vos = -160 V, VGS = OV
-25
VOS - -160 V, VGS = Ov, TJ = 125'C
-250
VOS- -3.3V,VGS- -10V
-4.0
0.50
0.80
VGS = -10V,lo = -2.4 A, TJ = 125'C
1.0
1.6
2.
6.6
2.2
nA
I1A
A
VGS - -10 V, 10 - -2.4 A
Vos = -15V, 10 = -2.4 A
V
Q
S
Dynamic
Input Capacitance
q..
Output Capaeitance
Co..
Reverse 'fransfer Capacitance
c,.,.
Thtal Gate ChargeC
Og
Gate-Source Charge"
Ogs
Gate-Drain ChargeC
Ogd
Thrn-On Delay TImec
RiseTImec
Thrn-Off Delay TImec
FaIlTImec
625
VGS = Ov, Vos = -25V,f= 1 MHz
280
pF
105
VOS = -100V, VGS = -10 V, 10 = -4.0A
14.7
24
0.5
3.4
6.1
3.3
13.5
20.1
34.8
td(on)
9
50
tr
50
100
32
80
38
80
td(o£f)
Voo = -100 V, RL = 39Q
10" -2.4 A, VGEN = -10V,Ra = 7.5 Q
t£
nC
ns
Source-Drain Diode Ratings and Cbaracterlstlcs
Continuous Current
Is
-4.0
Pulsed Current
ISM
-20
Diode Forward Voltage b
Vso
Reverse Recovery TIme
trr
Reverse Recovery Charge
Orr
A
IF = -4.0 A, VGS = OV
IF = -4.0 A, dildt = 100 N~s
-0.8
160
1.6
-2.0
V
400
ns
~C
Notes:
a. For design aid only; not SUbject to production testing.
b. Pulse test; pulse width S 300~. duty cycle S 2%.
c. Independent of operating temperature.
6-170
P-37010-Rev. A(06/06/94)
TEMIC
2N6851
Siliconix
TYpical Characteristics (25°C Unless Otherwise Noted)
Negalive signs omitted for clarity
Output Characteristics
7.5
6V _
6.0
~
E
~
u"
E
~
"
4.5
3
U
3.0
E
1.5
0
4
~
"
.,
'~.~ 1.50
PI~
8!;
1.25
:[
1.00
Ie
e
/
V'
/
/
i/
0.50
-50
~5'C"""" ~L--
T] =
100
S
~
T]
150'C
I'
=
//
8
~
If
10
"
c}l
/
0.75
Source-Drain Diode Forward Voltage
200
-.,
/
I
-10
30
70
o
150
110
2
T1 - Junction Thmperature ('C)
5
4
3
Vsn - Source-to-Drain Voltage (V)
Thermal Ratings
15.0
12.5
Maximum Drain Current vs. ease Temperature
-
...........
C 10.0
C
I
I "I
100
S
8
...=
Safe Operating Area
200
7.5
" I"
5.0
.B
2.5
Umitedby
S
l'OS(on)
C
~
75
"
"\,
.~
Q
~. 1'00..'
I
.9
Tc 25'C
Siutge F-ulbe
100
125
150
III
5
Tc - Case Thmperature ('C)
lOllS -
J~illllS
1ms 11111 10ms
lOOms
';k"-
'11111
I
10
100
10002000
Vos - Drain-to-Source Voltage (V)
Normalized Thermal1ransient Impedance, Junction-to-Case
2
II
Duty Cycle
0.5
0.2
_~iiIII
~ ".
0.1
0.05
0.02
0.01
,
10
0.1
50
25
i<-
8
0
o
11111
y
10-5
..-
-
"""" Single Pulse
I 1'111111
10-4
10-3
10-2
10- 1
3
Square Wave Pulse Duration (sec)
6-188
P,36736-Rev. C (05/30/94)
TEMIC
2N7079
Siliconix
P-Channel Enhancement-Mode Thansistor
Product Summary
V(BR)DSS (V)
rnS(on) (Q)
ID (A)
-100
0.210
-17
TO-254AA
Hermetic Package
S
o
Case Isolated
D
D S G
P-Channel MOSFET
ThpView
Absolute Maximum Ratings (Tc
= 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
Vns
-100
Gate-Source Voltage
Vas
±20
Continuous Drain Current (TJ = 150'C)
In
-10.8
100
I Tc=25'C
ITc = 100'C
Operating Junction and Storage Temperature Range
Lead Temperature (l1t6" from case for 10 sec.)
A
-68
InM
Maximum Power Dissipation
V
-17
I Tc=25'C
ITc = 100'C
Pulsed Drain Current
Unit
Pn
W
40
TJ,Tstg
-55 to 150
TL
300
'C
Thermal Resistance Ratings
Parameter
Maximum Junction-ta-Ambient
Symbol
'JYpical
Maximum
RthJA
50
Maximum Junction-to-Case
RthJC
1.25
Case-ta-Sink
RthCS
P-36731-Rev. C (05/30/94)
Unit
'c/w
0.2
6-189
TEMIC
2N7079
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Limit
Parameter
Test Condition
Min
= 0 Y,Io = -250 !1A
= Vas. 10 = -250 !1A
VOS = OY,VOS = ±20V
Symbol
lYP"
Max
Vnit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
Vas
-100
VOS(th)
VOS
-2_0
loss
loss
On-State Drain Currentb
IO(on)
Forward 'fransconductanceb
±100
VOS = -80 Y, Vas = 0 Y, TJ
= 125'C
-250
= -lOY, Vas = -10V
= -10 Y, 10 = -10.8 A
Vas = -lOY, 10 = -10.8 A, TJ = 125'C
-17
VOS - -15Y, 10 - -10.8 A
5.0
Vos
Vas
'OS(on)
grs
V
nA
-25
Vos - -80Y, Vas - OV
Zero Gate Voltage Drain Current
Drain-Source On-State Resistanceb
-4_0
!1A
A
0_14
0_210
0_22
0.32
5.5
Q
S
Dynamic
Input Capacitance
C;..
Output Capacitance
Co..
Reverse 'fransfer Capacitance
c,."
1300
Vas
= OY, Vos = -25Y, f = 1 MHz
750
pF
300
Thtal Gate Charge"
Og
Gate-Source Charge"
Ogs
Gate-Drain Charge"
Ogd
Thrn-On Delay TIme"
td(on)
10
30
tr
50
80
25
80
15
60
Rise TIme"
Thrn-Off Delay TIme"
Fall TIme"
td(off)
47
VOS = -50 Y, Vas
10
~
= -10 Y,ID = -17 A
Voo = -SOY, RL = 2.7Q
-17 A, VOEN = -lOY, Ro = 4.7 Q
tf
60
10
18
27
36
nC
ns
Source·Drain Diode Ratings and Characteristits
Is
-17
Pulsed Current
ISM
-68
Diode Forward Voltageb
Vso
Reverse Recovery TIme
trr
Reverse Recovery Charge
Orr
Continuous Current
A
IF
IF
= -17 A, Vas = OV
= -17 A, di/dt = lOON!,!,
-2.0
V
150
ns
0.3
!,C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300!'!'. duty cycle s 2%.
c. Independent of operating temperature.
6·190
P-36731-Rev. C (05/30/94)
TEMIC
2N7079
Siliconix
'iYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Output Characteristics
25
9V
VOS=10V/
20
//
$
E
"l::
15
a
~
Ii ~
10
E
5
o
Tc= -55'C
25'C I
/'
:-..
10.0
II'"
BV
$
7V
~
E
~
J~ ""..
V
'f!"
5.0
5V
E
2.5
4V
~
0
o
10
6
2
2
I
4
/
10
6
Vos - Gate-to-Source Voltage (V)
Vos - Drain-ta-Source Voltage (V)
'fransconductance
12.5
~lt.C
ij
J'
7.5
Q
6V
I~
o
'fransfer Characteristics
12.5
I
On-Resistance vs. Drain Current
12.5
I
10.0
€
1l
"
Ii'"
7.5
"
5.0
'"
2.5
co
~
",.
;l
'0
J
v::
Tc= -55'C
10.0
25'C
~
125'C
~
.~
7.5
0
5.0
~
~
,11
I
J
2.5
o
0
0
20
10
30
40
50
Vos= 10V
o
25
3000 . -_ _r -_ _C.,..;ap;...a_c_it_an..,cr-e_ _-.-_--,
Vos = OV
2500 I \ - - - \ - - - + - - - I - - - - ! - - - - \
75
100
125
Gate Charge
15.0
~
..,
ell
~
2000
.~ 1500 ~~~~-~--~-_+--~
I
50
20V-
V
I
10 = 17 A
12.5
~
~
a
-
10 - Drain Current (A)
10 - Drain Current (A)
i
,
1000
Hr--~~~r_-~r_--\--_;
U
500
~
'"
~
7.5
Cl
"
5.0
~
2.5
o
10
20
30
40
Vos - Drain-to-Source Voltage (V)
P-36731-Rev. C (05/30/94)
50
Vos= 50V /
10.0
~rBOV
/
/
/
o
15
Qg
30
-
45
60
75
Total Gate Charge (nC)
6-191
TEMIC
2N7079
Siliconix
'iYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
On-Resistance vs. Junction Temperature
1.75
1.50
e.
,,~
_"0
.!!l ~
1.25
~~
!
1.00
~~
,e
"
N
e
0.75
~
/
V
g
V
TJ~25'C~
TJ -150'C
100
§:
;;
n
t
//
u"
~
1(/
10
6
til
V
I
./
0.50
-50
Source-Drain Diode Forward Voltage
200
'"
II
0
-10
30
70
110
o
150
2
3
5
4
VSD - Source-to-Drain Voltage (V)
TJ - Junction'Thmperature ('C)
Thermal Ratings
25 Maximum Drain Current vs. Case Temperature
Safe Operating Area
100
10,,",
§:
20
§:
;;
~
"
.............
15
~
'iiI
c:i
10
I
Limitedby
I--
roS(on)
c
t
"-
.El
u"
........
5
0
~
'0e"
~
10
~
100 ""'
"-,",
1 ms
I
I'\.
\
.El
I-- Tc ~ 25'C
1--1
10ms
100 ms
I
de I
SjWimi
1
o
25
50
75
100
l
125
2
150
10
100
200
VDS - Drain-to-Source Voltage (V)
Tc - Case'Thmperature ('C)
Normalized Thermal 'fransient Impedance, Junction-to-Case
2
LI
Duty Cycle - 0.5
0.2
~
~
0.1
0.05
0.02
::ijjjiil
P'
...,.
SinwePulse
0.01
J-.tr
10-5
10-4
10-3
10-2
10- 1
Square Wave Pulse Duration (sec)
6-192
P-36731-Rev. C (05/30/94)
TEMIC
2N7080
Siliconix
P-Channel Enhancement-Mode Transistor
Product Summary
V(BR)OSS
(V)
rOS(on)
-200
(Q)
0.500
10 (A)
-9.5
TO-254AA
Hermetic Package
S
o
Case Isolated
D
D S G
P-Channel MOSFET
Top View
Absolute Maximum Ratings (Tc
25°C Unless Otherwise Noted)
Symbol
Limit
Drain-Source Voltage
Vos
-200
Gate-Source Voltage
VGS
±20
Parameter
Unit
V
-9.5
I Tc = 25'C
Continuous Drain Current (TJ = 150'q
10
Pulsed Drain Current
Maximum Power Dissipation
ITc= 100'C
Operating Junction and Storage Thmperature Range
Lead Thmperature (lh6" from case for 10 sec.)
A
-38
10M
Po
W
40
TJ,Tstg
-55 to 150
TL
300
'C
Thermal Resistance Ratings
Parameter
Maximum Junction-lo-Ambient
Symbol
Maximum Junction-to-Case
RthJC
RthCS
Maximum
Uuit
50
RthJA
Case-to-Sink
P-37012-Rev. C (06/01/94)
'JYpical
=~
=~
~~
U~
100
I Tc=25'C
I I)
-6.1
ITc = 100'C
1.25
'e/W
0.2
6-193
~O
I~
Z
-
TEMIC
2N7080
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Limit
Parameter
Max
Test Condition
Min
V(1IR)DSS
Vas = 0 V, 10 = -250 JlA
-200
VaS(tb)
Vos - Vas. 10 = -250 JlA
-2.0
lass
Vos = OV,Vas = ±20V
±100
Vos = -160 V, Vas = OV
-25
Vos = -160 V, Vas = Ov, TJ = 125°C
-250
Symbol
1YP"
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 1tansconductanceb
loss
10(on)
roS(on)
Vos = -10 V, Vas = -lOV
V
-4.0
-9.5
0.28
0.500
Vas = -10 V, 10 = -6.1 A, TJ = 125°C
0.5
1.0
Vos = -15 V, 10 = -6.1 A
Output Capacitance
C;"
Co..
Vas = Ov, Vos = -25 V, f= 1 MHz
Reverse 1tansfer Capacitance
Cr..
4.0
JlA
A
Vas = -10 V, 10 = -6.1 A
gl,
nA
4.8
0
S
Dynatnic
Input Capacitance
Thtal Gate Chargee
Qg
Gate-Source Chargee
Q gs
Gate-Drain Chargee
Qgd
111m-On Delay Timee
td(on)
Rise Timee
111m-Off Delay Timee
Fall TimeC
tr
td(oll)
1300
450
pF
200
Vos = -laO V, Vas = -lOV, 10 = -9.5 A
VOO = -100 V, RL = 10.20
10 = -9.5 A, VaEN = -lOV, Ra = 4.70
te
55
75
9.0
15
30
45
10
25
30
50
35
80
16
40
nC
ns
Source-Drain Diode Ratings ahd Cbaracteristics
Continuous Current
Is
-9.5
Pulsed Current
ISM
-38
Diode Forward Voltageb
Vso
Reverse Recovery Time
trr
Reverse Recovery Charge
Q rr
A
-2.0
IF = -9.5 A, Vas = OV
IF = -9.5 A, di/dt = 100 Nfls
V
200
ns
1.0
flC
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 flS. duty cycle s 2%.
c. Independent of operating temperature.
6-194
P-37012-Rev. C (06/01/94)
TEMIC
2N7080
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Output Characteristics
25
Transfer Characteristics
10
sv
20
/~
S
~"
15
"
10
.E
5
.~
Q
0
r
)
1/
S
7V
~
o
25'C .....,
8
~"
I"
/
6
6V
'2Q
4
5V
.E
2
J
~
4V
4
2
o
s
6
10
o
8
'""
J
""'"
~
6
4
2
j
~
e-
Ir
g
25'C
V""
~
I
125'C
~
0
O.S
/
0.6
0.4 t - VGs=10V
0.2
o
0
5
10
15
20
25
o
Capacitance
~
VGS = OV
J:~
~
@
1500
I
10.0
r5l
7.5
\!)
5.0
~
2.5
9
~
0-
a 1000
I
~DS =
,
500
0
0
40
VDS - Drain-la-Source Vollage (V)
P-37012-Rev. C (06/01/94)
50
A
so
100
If'
100"/"
1.'"
160V
I
U
10
50
/
I
12.5 I- ID = 9.5 A
::s
.~
0
40
Gate Charge
15.0
2000
30
30
ID - Drain Current (A)
2500
20
20'l
20
10
ID - Drain Currenl (A)
~
J
-~V
I
r
0
10
On-Resistance vs. Drain Current
1.0
Tc - -55'C
g
g
6
VGS - Gale-la-Source Voltage (V)
Transconductance
€
II
4
2
VDS - Drain-la-Source Voltage (V)
10
1/12S.J
Tc= -55'C
VGS=/""-
~
o
20
40
60
Og - Thtal Gate Charge (nC)
6-195
TEMIC
2N7080
Siliconix
'l:ypical Characteristics (25°C Unless OtheIWise Noted)
Negative signs omitted for clarity.
On-Resistance vs. Junction Temperature
2.25
2.00
/
Cl
"8
1.75
§~
_"0
.lij § 1.50
~'il
,e
8~
I~
./
1.25
I TJ =
/
C
g
8
~
~
V
I
VI
10
-..
30
70
110
150°C ::
//
,
J
o
-10
~
~
TJ
S
/'
0.50
-50
25~C
100
/
1.00
0.75
V
/
Source-Drain Diode Forward Voltage
200
150
II
o
3
2
VSD - Source-ta-Drain Voltage (V)
TJ - Junction Thmperature ("C)
Thermal Ratings
12.5
Maximum Drain Current vs. Case Temperature
Safe Operating Area
70
,-
S
10.0
.............
c
8
7.5
0
5.0
S
il
............
'"
.~
I
.B
o
50
25
7S
100
Tc - Case Thmperature (0C)
/<
./
I
"
125
1])S(on)
.B
~
Tc
25°C
Single Pulse
o.JJ IIIIII
150
'-
"-
I
I
I
Til
1 ms
~
\
o
10,,"
~~~
10
...~c
~
2.5
,-
2
10
"~"
I II
lOms
I II
lOOms
de ' ,
IIIIII111
]
100
I
fi
500
Vns - Drain-to-Source Voltage (V)
Normalized Thermal 'ftansient Impedance, Jun~1ion-to-Case
2
II
Duty cycle
~
0.5
0.2
~
0.1
0.05
0.02
-L
~ ::iii jill
I""
...
Sin.m
0.01
10-4
10-3
10-2
10-1
3
Square Wave Pulse Duration (sec)
6-196
P-37012-Rev. C (06/01/94)
TEMIC
2N7081
Siliconix
N -Channel Enhancement-Mode Transistor
Product Summary
V(BR)nSS (V)
rnS(on) (Q)
In (A)
100
0.15
13
TO-2S7AB
Hermetic Package
D
o
Go-l
Case Isolated
S
G D S
ThpView
N-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
100
Gate-Source Voltage
VGS
±20
Continuous Drain Current (TJ = 150"C)
Pulsed Drain Current
ID
8.0
I Tc=25"C
ITc = 100"C
Operating Junction and Storage Thmperature Range
Lead Thmperature (lh6" from case for 10 sec.)
A
48
IDM
Maximum Power Dissipation
V
13
I Tc=25"C
ITc= 100"C
Unit
50
Po
W
20
TJ. Tstg
-55 to 150
TL
300
"C
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient
Symbol
Maximum Junction-to-Case
RthJC
Rthcs
Maximum
Unit
80
RthJA
Case-to-Sink
P-36736-Rev. C (05130/94)
'JYplcal
2.5
"C/W
1.0
6-197
TEMIC
2N7081
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Limit
Parameter
Symbol
Min
Test Condition
1YP"
Max
Unit
Static
Dram-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 'Iransconductanceb
f'A
100
VGS(th)
Vns = VGS, In = 250 "A
2.0
IGSS
Vns = OV,VGS = ±20V
±100
Vns = 80 V, VGS = OV
25
V(BR)DSS
Inss
In(on)
rnS(on)
VGS = Ov, In = 250
V
4.0
250
Vns = BOV, VGS = Ov, TJ = 125'C
13.0
Vns -lOV,VGS -lOY
0.12
0.15
VGS = 10 V, In = 8.0 A, TJ = 125'C
0.22
0.27
Vns = 15 V, In = 8.0 A
Output Capacitance
c,..
Cos,
VGS = ov, Vns = 25V,f = 1 MHz
Reverse 'Iransfer Capacitance
Cr..
f'A
A
VGS - 10 V, In = 8.0 A
gr.
nA
Q
4.0
5.0
S
Dynamic
Input Capacitance
30
9.0
9
20
td(on)
7
30
te
45
BO
30
60
10
40
Og,
Gate-Drain Charge"
Ogd
1I1rn-On Delay TIme"
Fall Time"
pF
35
6
Og
Gate-Source Chargee
1I1rn-Off Delay TIme"
190
17
Thtal Gate Charge"
Rise TIme"
600
Id(off)
Vns = 50 V, VGS = 10 V, In = 13 A
Vnn = 50V,RL = 3.B Q
In'" 13 A, VGEN = 10V, RG = 7.5
tr
Q
nC
ns
Source-Drain Diode Ratings and Characteristics
Continuous Current
Is
13
Pulsed Current
ISM
48
Diode Forward Voltageb
Vsn
Reverse Recovery TIme
tre
Reverse Recovery Charge
Ore
A
IF -13A, VGS - OV
100
IF = 13 A, di/dt = 100 NI's
0.7
2.5
V
300
ns
"C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width :$ 300 ""dutycycle :$ 2%.
c. Independent of operating temperature.
6-198
P-36736-Rev. C (05/30/94)
TEMIC
2N7081
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
8V
10
g
E
~
""
u
6
4
.E
2
rj 125lo C
12
g
J
9
t:
1
U
U
Q
.~
6
Q
5V
.E
J
3
)J
4V
0
0
0.4
0
0.8
1.2
1.6
o
2
'fransconductance
..,'""
"
~
0.4
e.11
25°C
125°C
.~"
0.3
=
0.2
I
VGS=10~ 20V~
~
4
0
F
.---:. ~
I
I
..,'"
On-Resistance vs. Drain Current
0.5
6
E
2
0.1
0
5
10
15
20
o
25
~
j
~
I
12.5 r- In = 12A
~
A~v
~ 10.0
~
600
"0
c,,,
300
\..~
0
0
10
20
7.5
C!l
5.0
~
2.5
0
30
40
Vns - Drain-Io-Source Vollage (V)
P-36736-Rev. C (05/30/94)
rJl
1...
\I~"
I
U
50
50
~
V
VGs= 50V
~
900
c.
40
Gate Charge
15.0
1200
.~
30
In - Drain Current (A)
Capacitance
1500
20
10
In - Drain Currenl (A)
a
V
o
0
~
g
12
9
VGS - Gale-Io-Source Voltage (V)
€
.~
6
6
Vns - Drain-Io-Source Voltage (V)
10
~25°C
TC= -55°C
8
"
'f!"
'fransfer Characteristics
15
/
/
V
o
8
12
16
20
24
Og - Total Gale Charge (nC)
6-199
TEMIC
2N7081
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.25
100
2.00
e.
1.75
8
B"
.~ .~ 1.50
e<:"iiI
d E 1.25
~~
J
1.00
0.75
V
V
0.50
-50
V
V
V
./
/
Source-Drain Diode Forward Voltage
200
J
F==
TJ
,
S
~
=
0
til
I
,
E
~
25'C
150'C
TJ
f
10
:!:
I
o
-10
70
30
150
110
I
o
2
TJ - Junction Thmperature ("C)
3
5
4
VSD - Source-to·Drain Voltage (V)
Thermal Ratings
20 Maximum Drain Current vs. Case Temperature
S
S
iil::
E
12
0
8
r-----....
.~
~
I
oS
4
.........
75
100
'.'.......... l'
0
I
~
oS
\
50
125
11
0.2
150
I
10'
ms
= Single
Tc 25'C
===
Pulse
100 ms
dc
1
11111
10
1
T c - Case Thmperature ('C)
1
100
VDS - Drain-to·Source Voltage (V)
Normalized Thermal 'n-ansient Impedance, Junction-to-Case
2
II
Duty Cycle
0.5
0.2
-
0.1
0.05
0.02
0.01
100 I
lms
·a
0
25
I
I'
~
8c
r---
o
IDS(OI1)
10
lOll-'
,
~
Limited by
16
"l::
8
Safe Operating Area
100
V
10-5
-
~
i-'
f'" Single Pulse
10-4
10-3
10- 1
3
Square Wave Pulse Duration (sec)
6-200
P-36736-Rev. C (05/30/94)
TEMIC
2N7085
Siliconix
N -Channel Enhancement-Mode lransistor
Product Summary
V(BR)DSS (V)
rDS(on) (Q)
ID (A)
100
0.D75
20
TO·257AB
Hermetic Package
D
o
Go--J
Case Isolated
S
G D S
Top View
N-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
100
Gate-Source Voltage
VGS
±20
Continuous Drain Current (TJ = 150'q
Pulsed Drain Current
ID
12
60
I Tc=25'C
PD
Lead Thmperature e116" from case for 10 sec.)
W
20
ITc = 100'C
Operating Junction and Storage Thmperature Range
A
80
IDM
Maximum Power Dissipation
V
20
I Tc = 25'C
I Tc = lOO'C
Unit
TJ,T,tg
-55 to 150
TL
300
'c
Thermal Resistance Ratings
Parameter
Symbol
lYPical
Maximum
Maximum Junction-to·Ambient
RtbJA
80
Maximum Junction-to-Case
RtbJC
2.1
Case-to-Sink
Rthcs
P-36736-Rev. B (05/30/94)
Unit
.c/w
1.0
6-201
TEMIC
2N7085
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Limit
Parameter
Symbol
lest Condition
Min
=OV,ID =250 (!A
=VGs. ID =250 (!A
100
'JYpa
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate 'Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VGS
VGS(tb)
VDS
IGSS
IDSS
On-State Drain Currentb
ID(on)
Forward 'Iransconductanceb
4.0
VDS-OV,VGS- ±20V
±100
=BOV, VGS =OV
VDS = BO V, VGS =0 V, T1 =125'C
VDS = 10 V, VGS =10V
VGS = 10 V,ID = 12A
25
VDS
Zero Gate Voltage Drain Current
Drain-Source On-State Resistanceb
V
2.0
rnS(on)
8f.
250
20
=15 V, In =12A
(!A
A
0.06
0.075
0.11
0.14
Q
VGS = 10 V, ID = 12 A, T1 = 125'C
Vns
nA
5.0
B.O
S
Dynam.ic
Output Capacitance
4ss
Co..
Reverse 'Iransfer Capacitance
c,..
Input Capacitance
Thtal Gate ChargeC
Og
Gate-Source ChargeC
Og,
Gate-Drain ChargeC
Ogd
'fiIrn-On Delay TImec
Id(on)
RiseTImec
'fiIrn-Off Delay TImec
FallTImec
t,
td(off)
1400
VGS = OV,VDS = 25 V, f= 1 MHz
480
pF
110
VDS = 50 V, VGS
=10V,ID =20A
=
Vnn 50V,RL = 2.5 Q
In '" 20 A, VGEN = 10V, RG = 4.7 Q
t(
35
50
10
20
18
25
13
30
85
120
35
80
75
95
nC
ns
Sauree-Drain Diode Ratings and Cbarad:erlsti~s
Continuous Current
Is
20
Pulsed Current
ISM
80
Diode Forward Voltageb
VSD
Reverse Recovery TIme
tIT
Reverse Recovery Charge
Orr
A
IF = 20 A, VGS=OV
150
IF = 20 A, dildt = 100 N!'S
0.5
2.5
V
400
ns
"C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 3oo!'S. duty cycle s 2%.
c. Independent of operating temperature.
6-202
P-36736-Rev. B (05/30/94)
TEMIC
2N7085
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
I
VGS =lOV/ '/9V I
50
40
""...
l::
30
U
"
"§
Q
.E
8V
40
II Y
'I!,/
~
20
~
I~ I'
III
0
o
""
~
7V
30
U
.~
~
/
10
'fransfer Characteristics
50
6V
Q
20
.E
10
5V
4V
0
4
2
0
10
'fransconductance
16
II
""""
~
~
O.OS
'"
btl
12
8
4
0
/
r
o
.,~
~
8
Tc = -55'C
-
25'C
~
125'C
VGs=lOV
.!!
"
.!f~
<5 li
6
1
!
e
L
100
2.00
'8
Source-Drain Diode Forward Voltage
200
/
1.50
1.25
1.00
,/
0.75
/'
S
c
e
f
a§
./
TI
~
=
150'11
lO
TI
-
=25'C
'"
I
..,.""
0.50
-50
~
I
-10
70
30
o
150
110
2
TI - Junction Thmperature ('C)
5
3
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
25 Maximum Drain Current vs. Case Temperature
Safe Operating Area
200
S
c
"
8
20
.............
15
==
f'...
c
c
..........
'O!
0
=
S
10
1
"'-
oS
5
8
75
100
....
1\
1ms
.......
10ms
,
i'
oS
=
~ Tc
125
100 1ms
25'C
de
Single Pulse
-
-lilli"~
IIIII
1
150
i
.....
10
100
VDS - Drain-to-Source Voltage (V)
Normalized Thermal 'ftansient Impedance, Junction-to-Case
2
DU~ Cy~le ~ ~.~ I
---
C
.2
h
--
0.2
F~
~~
i'
1
Tc - Case Thmperature ('C)
' ~"
:: ell.......
~E
iC.. r
~
100
c
0.1
50
roS(on)
'Cle
o
25
Umitedby
10
\
o
10~
jj
100
0.1
0.1
~ ;;;; [:=II'"
0.05
0.02
I
-
s+erUlu.r
I"'"
.JI'
"
....
0.01
10- 5
lO-4
lO-3
lO-2
10- 1
3
Square Wave Pulse Duration (sec)
6-204
P-36736-Rev. B (05/30/94)
TEMIC
2N7086
Siliconix
N-Channel Enhancement-Mode Transistor
Product Summary
V(BR)nSS (V)
rnS(on) (Q)
In (A)
200
0.16
14
TO-257AB
D
Hermetic Package
o
Case Isolated
S
G D S
TopV,ew
N-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Othernise Noted)
Parameter
Limit
Symbol
Drain-Source Voltage
VDS
200
Gate-Source Voltage
VGS
±20
V
14
ITc=2S"C
Continuous Drain Current (TJ = IS0"C)
ID
8.5
ITc = loo"C
Pulsed Drain Current
I Tc=25"C
ITc= 100"C
Operating Junction and Storage Temperature Range
Lead Thmperature (1116" from case for 10 sec.)
A
56
IDM
Maximum Power Dissipation
Unit
60
Po
W
23
TJ. Tstg
-55 to 150
TL
300
"C
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Ambient
Symbol
Maximum Junction-to-Case
RtbJC
RthCS
Maximum
Unit
80
RtbJA
Case-to-Sink
P-37012-Rev. B (06/01/94)
'JYpical
2.1
"CfW
1.0
6-205
TEMIC
2N7086
Specifications (TJ
Siliconix
= 25°C Unless Otherwise Noted)
Limit
Parameter
Symbol
Min
Test Condition
1Yt>"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward 'fransconductanceb
V(BR)DSS
VGS = Ov, 10 = 250
VGS(th)
VOS = VGS, 10 = 250
IGSS
loss
10(on)
ros(on)
gf,
flA
flA
200
V
2.0
40
VOS= OV,VGS = ±20V
±toO
Vos = 160 V, VGS = OV
25
Vos = 160 V, VGS = 0 V, TJ = 125°C
250
Vos -tov, VGS = 10V
14
~A
A
VGS - to V, 10 - 8.5 A
0.14
0.16
VGS - 10 V, 10 - 8.5 A, TJ - 125°C
0.25
0.30
Vos = 15 V, 10 = 8.5 A
nA
5.0
g
S
Dynamic
Input Capacitance
C;,.
Output Capacitance
Co"
c,..,
Reverse 'fransfer Capacitance
Thtal Gate Chargee
Og
Gate-Source Chargee
Og'
Gate-Drain Chargee
Ogd
Thrn-On Delay TImec
RiseTImec
Thrn-Off Delay TImec
FallTImec
1550
VGS = OV,Vos = ZSV,f= 1 MHz
td(off)
pF
220
44
VOS = 100 V, VGS = 10V,lo = 14A
ld(on)
tr
500
Voo = 100 V, RL = 7.1 g
10=14 A,VGEN=10V,RG=4.7 g
tf
77
10
15
26
35
10
30
60
100
30
80
40
95
nC
ns
S(lUfce·Drain Diode Ratings and Characteristics
Continuous Current
Is
14
Pulsed Current
ISM
56
A
Diode Forward Voltageb
VSD
Reverse Recovery TIme
trr
Reverse Recovery Charge
Orr
IF = 14 A, VGS =OV
IF = 14 A, dildt = 100 N~
150
0.5
2.0
V
650
ns
~C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width :s 3OO~, duty cycle :s 2%.
c. Independent of operating temperature.
6·206
P-37012-Rev. B (06/01/94)
TEMIC
2N7086
Siliconix
'tYpical Characteristics (25°C Unless Otherwise Noted)
Output Characteristics
25
16
20
~
C
I!
8
'@
Q
.E
1ransfer Characteristics
20
~
7V
C
u
t:
15
12
"
U
6V
Q
'"
8
.E
4
.~
10
5V
5
4V
0
0
0
4
2
6
8
10
0
1ransconductance
20
€
!l.
Ii
~
12
8
""
4
0
~
J
If
o
~
-
Tc = -55°C
j
25°C
~
...-::::
10
1
125°C
0
0.6
VGS = 10V
0.4
I
e!
20V
0.2
0
20
10
30
40
0
50
15
45
60
75
Gate Charge
15.0
€
VGS = OV
2500
30
ID - Drain Current (A)
Capacitance
3000
u
bO
2000
.~
1500
I
1000
~
10.0
"
7.5
~
i
~
5.0
~
2.5
U
500
o
~----~----~--~~--~----~
o
10
20
30
40
VDS - Drain-to-Source Voltage (V)
P-37012-Rev. B (06/01/94)
50
IU
=~
=~
!~
UrJ:l
~O
z.~
12.5
~
Ii:'
a
8
0.8
ID - Drain Current (A)
f
6
e!-
~I
bO
4
On-Resistance vs. Drain Current
1.0
16
"0
~'"
2
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
15
30
45
60
75
Qg - Thtal Gate Charge (nC)
6-207
TEMIC
2N7086
Siliconix
1Ypical Characteristics (25°C Unless Otherwise Noted)
On-Resistance vs. Junction Temperature
2.00
~
/
1.75
~~
1.50
~1
1.25
.;;;~""
.M
".
V
o~
J.
~
I
100
",-
0.75
/
1=
100
TJ
C
S
V
25°C
II
'I
u
§
/'
10
::J
0
'"I
:;
10"
0.50
-50
I150°C ~
TJ
S
..-IV
~
Source-Drain Diode Forward Voltage
200
II
1
-10
30
70
110
o
150
2
TJ - Junction Thmperature (0C)
4
3
5
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
20 Maximum Drain Current vs. Case Temperature
Safe Operating Area
100
lOllS
S
=
~
16
12
---
Limited by
..............
..........
~
'"I '"11
.......
8
~
.9
o
25
10
C
.~
Q
I
fDS(on)
S
50
75
100
125
r-
.~
I
.9
0.2
Jl......
0.1
1~
z
de
t- I 1'111111
2
10
ti
I II
100
500
VDS - Drain-to-Source Voltage (V)
II I
~!l
F:!a
"1l
~E 0.1
1 II
lOOms
1= Tc- 25°C
I-- Single Pulse
0.1
Iii!
Ims
lOms
I'
Q
150
Duty Cycle - 0.5
S'
~,
Normalized Thermal 'fransient Impedance, Junction-to-Case
2
.~
'.
,
B
Tc - Case Thmperature ("C)
C
.2
,"
.~
-
.....-!! i;Iiiiii
,;
0.05
0.02
SingleP~ ~
0.01
10-5
10-4
10-3
10-2
10- 1
3
Square Wave Pulse Duration (sec)
6-208
P-37012--Rev. B (06/01/94)
TEMIC
2N7089
Siliconix
P-Channel Enhancement-Mode Thansistor
Product Summary
V(BR)DSS (V)
rOS(on) (Q)
10 (A)
-100
0.30
-10
TO-257AB
Hermetic Package
S
o
Case Isolated
D
G D S
P-Channel MOSFET
ThpView
Absolute Maximum Ratings (Tc
= 25°C Unless Otherwise Noted)
Parameter
Symbol
limit
Drain-Source Voltage
Vns
-100
Gate-Source Voltage
Vos
±20
Continuous Drain Current (TJ = 150°C)
V
-10
I Tc=25°C
ITc = 100°C
Pulsed Drain Current
In
-6.7
60
ITc =25°C
I Tc=l00°C
Operating Junction and Storage Temperature Range
Lead Thmperature (lh6" from case for 10 sec.)
A
-40
InM
Maximum Power Dissipation
Unit
PD
W
24
TJ,T"g
-55 to 150
TL
300
°C
Thermal Resistance Ratings
Parameter
Maximum Junction-ta-Ambient
Symbol
'tYPical
Maximum
R,hJA
80
Maximum lunction-to-Case
RthJC
2.0
Case-to-Sink
R'hCS
P-36731-Rev. B (05/30/94)
Unit
0c/w
1.0
6-209
TEMIC
2N7089
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Limit
Parameter
Symbol
Min
Test Condition
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VOS(th)
loss
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currentb
ID(on)
Drain-Source On-State Resistanceb
Forward 'Itansconductanceb
fDS(on)
gr.
Vos =
ov, ID = -250 !1A
VDS = VOS, ID = -2S0
~A
-100
-2.0
-4.0
VDS = OV,Vos = ±20V
±100
VDS= -80V,Vos=OV
-25
VDS = -80 V, Vos = OV,TJ = 12S'C
-250
VDS = -10 V, VOS = -10V
-10
0.2S
0.30
VOS - -10 V, ID - -6.7 A, TJ - 12S'C
0.4
0.53
2.0
nA
!1A
A
Vos = -10 V, ID = -6.7 A
VDS - -lSV,ID - -6.7 A
V
3.0
'1
S
Dynallllc
Input Capacitance
C;..
Output Capacitance
Co..
Cr.,
Reverse 'Itansfer Capacitance
Thtal Gate ChargeC
Qg
Gate-Source ChargeC
Qg,
Gate-Drain ChargeC
Qgd
Thrn-On Delay Timec
Rise Timec
Thrn-Off Delay Timec
Fall Timec
62S
Vos = OV, VDS = -2SV,f= 1 MHz
td(olf)
pF
lOS
VDS = -SO V, VOS = -10V,ID = -lOA
td(on)
tr
280
VDD = -50 V, RL = 5'1
ID'" -lOA, VOEN= 10V,Ro= 7.5'1
tl
24
40
3.4
6.0
13.5
20
9
60
50
140
60
140
38
140
nC
ns
Sllurce-Drain Diode RlItlngs and Characteristics
Is
-10
Pulsed Current
ISM
-40
Continuous Current
A
Diode Forward Voltageb
VSD
Reverse Recovery Time
tIT
Reverse Recovery Charge
Q"
IF = lOA, VOS = OV
IF = 10 A, di/dt = 100 N~
110
0.4
-2.0
V
250
ns
~C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width.: 300 !,S, duty cycle': 2%.
c. Independent of operating temperature.
6-210
P-36731-Rev. B (05130/94)
TEMIC
2N7089
Siliconix
'iYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Output Characteristics
12.5
'fransfer Characteristics
10
BV
1O.0f---f-H-cFI----+---+--7V
7.5
6
6V
5.0 r--I.ft--::;;ii--I---!----I--~
4
SV
1.5
2
4V
o~:j===t==~==±=~
o
2
6
10
o
o
2
'fransconductance
~
I
3
"
~
os
11
5
Fl
0.6
~
125'C
=
0
8'
"
§
OIl
0
10
15
20
--
VGS = lOV
0.4
0.2
o
0
15
o
---
/
20V
10
20
30
~
40
50
40
50
ID - Drain Current (A)
ID - Drain Current (A)
Capacitance
Gate Charge
15.0
2500
~
g,
2000
...
12.5
I
I
r-
ID = lOA
os
IZ'
~ 10.0
,e,
~
~
.!:"i! 1.25
~!
J
Source-Drain Diode Forward Voltage
200
1.00
./"
0.75
/
TJ-25'C.~
S
.-
-="
8§
.:::
I
o
-10
150'C -
/
10
"
0
til
/'
0.50
-50
TJ
~
30
70
150
110
II
o
4
2
TJ - Junction Thmperature ("C)
5
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
12.5
Maximum Drain Current vs. Case Temperature
Safe Operating Area
50
10",
II I
S
-=~
7.5
.~
0
5.0
8
100
Umitedby
10.0
.............
~
I
r-
S
'5
'"
.fl
2.5
"
~
"~
roS(oo)
10
1J
8
"
' - i"o..
·il
"1,\
~
"i\
I
"
.fl
\
f:::=
10 ms
J
I"
Tc=2S n C
Single Pulse
100 1ms
de
0
o
25
50
75
toO
125
i
150
10
Tc - Case Thmperature ('C)
100
1
200
VDS - Drain-to-Source Voltage (V)
Normalized Thermal1ransient Impedance, Junction-to-Case
2
II I
Duty Cycle
0.5
0.2
",.
..... :::;Iiil
0.1
0.05
0.02,
0.01
! Pulse
Single
...,..
i""
-I~
10-5
10-4
10-3
10-2
to-1
3
Square Wave Pulse Duration (sec)
6-212
P-36731-Rcv. B (05130/94)
TEMIC
2N7090
Siliconix
P-Channel Enhancement-Mode Transistor
Product Summary
V(BR)nSS (V)
rnS(on) (Q)
In (A)
-200
0.80
-5.7
TO·257AB
Hermetic Package
S
o
Case Isolated
D
G D S
ThpView
P-Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Symbpl
Umlt
Drain-Source Voltage
Parameter
VDS
-200
Gate-Source Voltage
VGS
±20
Continuous Drain Current (Tl = 150'C)
Pulsed Drain Current
ID
-3.6
60
I Tc=25'C
ITc= 100'C
Operating Junction and Storage 1l:mperature Range
Lead Temperature e1t6" from case for 10 sec.)
A
-23
IDM
Maximum Power Dissipation
V
-5.7
I Tc=25'C
ITc= 100'C
Unit
PD
W
25
Tl,Tstg
-55 to 150
TL
300
'C
Thermal Resistance Ratings
Parameter
Symbol
'tYpical
Maximum
Maximum Junction-to-Ambient
RthlA
80
Maximum Junction-to-Case
RthJC
2.0
Case-ta-Sink
P-37012-Rev. C (06/01/94)
RthCS
Unit
'c/w
1.0
6·213
TEMIC
2N7090
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Limit
Parameter
Test Condition
Min
V(BR)DSS
vGS = 0 Y, In = -250 JlA
-200
VGS(tb)
Vns = VGS. In = -250 JlA
-2.0
Symbol
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
IGSS
Zero Gate Voltage Drain Current
Inss
On-State Drain Currentb
In(on)
Drain-Source On-State Resistance b
Forward 1tansconductanceb
rns(on)
gf,
-4.0
Vns = OY,VGS = ±20V
±100
Vns = -160Y, VGS = OV
-25
Vns = -160 Y, VGS = 0 Y, TJ = 125"C
-250
Vns = -lOY, VGS = -lOV
-5.7
0.5
080
VGS - -lOY, In - -3.6 A, TJ -l25"C
1.0
1.6
2.2
nA
I'A
A
VGS = -10 Y, In = -3.6 A
Vns = -15 Y, In = -3.6 A
V
2.7
Q
S
Dynamic
Input Capacitance
c;,..
Output Capacitance
Co..
c",
Reverse 1tansfer Capacitance
Thtal Gate ChargeC
Qg
Gate-Source ChargeC
Qgs
Gate-Drain ChargeC
Qgd
Thrn-On Delay TImec
Rise Timec
Thrn-Off Delay TImec
FallTImec
510
VGS = OY, Vns = -25Y, f= 1 MHz
td(off)
pF
75
Vns = -100Y, VGS = -lOY, In = -5.7 A
td(on)
tr
180
Vnn = -100Y,RL = 17Q
In = -5.7 A, VGEN = -10Y,RG = 7.5 Q
tf
27
35
3.4
6.0
15
25
9.0
50
33
100
80
100
50
80
nC
ns
SClUrce-Drain Diode Ratings ani! Cbaraeteristi~s
Is
-5.7
Pulsed Current
ISM
-23
Diode Forward VOltageb
Vsn
Reverse Recovery TIme
trr
Reverse Recovery Charge
Q rr
Continuous Current
A
IF = -5.7 A, VGS = 0 V
160
IF = -5.7 A, dildt = 100 N!'s
1.6
-2.5
V
400
ns
!,C
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width :s; 3001'". duty cycle :s; 2%.
c. Independent of operating temperature.
6-214
P-37012-Rev. C (06/01/94)
TEMIC
2N7090
Siliconix
TYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
12.5 ,----,----':....,--------,....,..-,
10.0 f---I----j----+----,#';""F-
I
125"C
~
;;;
"eQ"
Tc= -55"C
25"C
'-o.!
4
~
~
'fransfer Characteristics
5
;;;
~
7.S
"
'iiI
5.0
0
3
J
2
/
.3
~
0
o
4
2
6
8
o
10
2
Vos - Drain-to-Source Voltage (V)
6
8
10
Vos - Gate-to-Source Voltage (V)
'fransconductance
S
4
On-Resistance vs. Drain Current
1.50
I
Tc= -SS"C
€
~
g
4
/'
3
.iL
'g
§
lii
2
E!::
'"
bIl
1.25
..-
~
.!~
25"C
~
.
125"C
,P
/
1.00
Vos= 10V
0.75
V
0
0.50
o
2.5
5.0
7.5
10.0
12.5
...".",..
/"20V",.,
~
o
10
15
20
25
10 - Drain Current (A)
Capacitance
Gate Charge
15.0
1250
~
Vos=OV
j
1000
~
12.5
~
750
Vos=
::J
a
.~
9
~
500
I
"
U
250
~
0
7.5
l00~160V
r/
I
5.0
2.5
Ar
~
1
f- IO=rA
~ 10.0
.e:
a
./
0.25
10 - Drain Current (A)
~
I-'
J ::.-~
I
0
0
V
~
II
II
0
0
10
20
30
40
Vos - Drain-to-Source Voltage (V)
P-37012-Rev. C (06/01/94)
50
o
10
20
30
40
so
Qg - Thtal Gate Charge (nC)
6-215
TEMIC
2N7090
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
On-Resistance vs. Junction Temperature
2.25
2.00
e!8
1.75
'~.~ 1.50
~]
86
,~
J
1.25
1.00
0.75
V
/
V
/
/
V
/
§~
/
-10
30
I
Tl- 25'C
100
S
,
il
~
~
10
0
til
'"
I
o
0.50
-50
Source-Drain Diode Forward Voltage
200
70
110
150
J......--
Tl- 150 'C
=
~
"
I
o
Tl - Junction Thmperature ('C)
2
4
3
VSD - Source-to-Drain Voltage (V)
Thermal Ratings
6 Maximum Drain Current vs. Case Temperature
5
S
-=
8"
'E
,
---- -...........
4
3
"
'- .......
S
===
i..'~
,
.9
-
o
0.1
25
50
75
100
fDS(on)
1ms
Q
\,
125
101"'
100
I,.\.
"-
'E"
r\
.9
o
Ilmitedby
a
'\
2
10
-="t:
t\..
Q
Safe Operating Area
50
150
r-r--
I II
'"
1'0
T,.. 25'C
S;;;gle Pulse
lo'ms,
100 ms
de'l
III
111111
10
Tc - Case Thmperature ('C)
I"-
100
500
VDS - Drain-ta-Source Voltage (V)
Normalized Thermal 'Iransient Impedance, Junction-to-Case
2
"
Duty Cycle - 0.5
0.2
--
0.1
0.05
"'
~jjIi
--
0.02
r:..
I
Single Pulse
om
10-5
./
"'"
I .L..H1
10- 4
10-3
10-2
10-1
3
Square Wave Pulse Duration (sec)
6-216
P-37012-Rev. C (06/01/94)
TEMIC
2N7091
Siliconix
P-Channel Enhancement-Mode Transistor
Product Summary
V(BR)DSS (V)
rnS(on) (Q)
In (A)
-100
0.20
-14
TO-257AB
Hermetic Package
S
o
Case Isolated
D
G D S
P-Channel MOSFET
Top View
Absolute Maximum Ratings (Tc
= 25°C Unless Othenvise Noted)
Symbol
limit
Drain-Source Voltage
VDS
-100
Gate-Source Voltage
VGS
±20
Parameter
Continuous Drain Current (TJ
~
150'C)
ITc~25'C
ITc ~ 100'C
Pulsed Drain Current
-8.7
Operating Junction and Storage Temperature Range
Lead Thmperature eh6" from case for 10 sec.)
A
-56
IDM
ITc ~ 100'C
V
-14
ID
ITc~25'C
Maximum Power Dissipation
Unit
70
PD
W
27
TJ. Tstg
-55 to 150
TL
300
'C
Thermal Resistance Ratings
Parameter
Symbol
1Ypical
Maximum
Maximum Junction-to-Ambient
RthJA
80
Maximum Junction-to·Case
RthJC
1.8
Case· to-Sink
RthCS
P-36731-Rev. C (05/30/94)
Unit
'c/w
1.0
6-217
TEMIC
2N7091
Siliconix
Specifications (TJ - 25°C Unless Otherwise Noted)
Limit
Parameter
Symbol
Min
Test Condition
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
V(BRJDSS
Vas = 0 V, In = -250
VaS(th)
Vns = Vas, In = -250
loss
Zero Gate Voltage Drain Current
Inss
Drain Currentb
In(on)
On-State
Drain-Source On-State Resistanceb
Forward 'fransconductanceb
rns(on)
!lis
!1A
!1A
-100
V
-2.0
-4.0
Vns =OV,Vas = ±20V
±100
Vns = -80 V, Vas = OV
-25
Vns = -80 V, Vas = Ov, TJ = 125'C
-250
Vns- -10V,Vas- -10V
-14
!1A
A
Vas - -10 V, In - -8.7 A
0.15
0.20
Vas = -10V,ln = -8.7 A, TJ = 125'C
2.3
0.32
Vns = -15 V, In = -8.7 A
nA
5.0
0
S
Dynamic
Input Capacitance
Co"
Reverse 'fransfer Capacitance
c,."
Thtal Gate Chargee
Og
Gate-Source Chargee
Ogs
Gate-Drain Chargee
Thrn-On Delay TImee
Rise1imec
Thrn-Off Delay TImee
FallTImee
1300
C;"
Output Capacitance
Vas = OV, Vos = -25V,f= 1 MHz
750
pF
310
50
62
10
15
Ogd
27
35
td(on)
10
30
tr
50
80
40
80
40
60
td(off)
Vns = -50V, Vas = -lOV, In = -14A
VDO = -50 V, RL = 3.50
10 = -14 A, VaEN = -10V,Ra = 4.70
tf
nC
ns
Source-Drain Dil/de Ratings and Characteristics
IS
-14
Pulsed Current
ISM
-56
Diode Forward VoJtageb
VSO
Reverse Recovery TIme
trr
Reverse Recovery Charge
Orr
Continuous Current
A
IF = -14 A, Vas = OV
150
IF = -14 A,dildt = l00NiJ.S
0.3
-2.0
V
300
ns
flC
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width :5 300 iJ.S. duty cycle :5 2%.
c. Independent of operating temperature.
6-218
P-36731-Rev. C (05130/94)
TEMIC
2N7091
Siliconix
lYpical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
Output Characteristics
25
VGS~lOVI
20
//
§::
8""
"
';J
is
.E
15
~
10
o
Tc~
./
BV
§::
7V
8"
;'
~
.~
V
Q
6V
SV -
~
.E
5.0
/
2.5
~
4V
2
4
6
8
o
10
1:l
~
7.5
"
't:I
i
5.0
F:
J
'"
co
2.5
1.00
25°C
~
125°C
.~
~
I
d
,ill
5
0.75
I>:
"..-
<:
0
0.50
c-
VGs~10V
J
I
20
30
40
-
0.25
o
0
10
50
o
15
Capacitance
~
g,
12.5
r-
60
75
2000
~
10.0
1500
"
7.5
t!l
5.0
~
2.5
~
II'
I
ID~14A
5
~
J
45
Gate Charge
15.0
2500
a""
30
ID - Drain Current (A)
VGS~OV
.eo
1l
§
'g
20V -
"
ID - Drain Current (A)
3000
10
Tc~
".
0
8
6
On-Resistance vs. Drain Current
1.25
I-55°C
~-
§:
I(
V GS - Gate-to-Source Voltage (V)
1l:ansconductance
10.0
J
2
VDS - Drain-to-Source Voltage (V)
12.5
~1JC
~
7.5
0
o
-55°C
. 25°C ~
10.0
~
~~ i-""
5
1l:ansfer Characteristics
12.5
9V
VDS~
0
SOY
L
~~OV
1 /
1000
/
U
500
o
0
0
10
20
30
40
VDS - Drain-to-Source Voltage (V)
P-36731-Rev. C (05/30/94)
50
V
o
15
30
45
60
75
Og - Thtal Gate Charge (nC)
6-219
TEMIC
2N7091
Siliconix
'lYPical Characteristics (25°C Unless Otherwise Noted)
Negative signs omitted for clarity.
On-Resistance vs. Junction Temperature
1.75
1.50
~
8
B'ti'
.!9 u
~.t:i
/
1.25
=~
o~ 1.00
:/
I~
!
e
~
0.75
0.50
-50
/
V
~
S
iii
"
~
TJ = 150'C / /
a
~
10
~
---.-
'/
TJ = 25'C
....'"
o
-10
~
100
,/
V
Source-Drain Diode Forward Voltage
i"""'"
200
30
70
110
150
I
o
3
2
5
4
VSD - Source-to-Drain Voltage (V)
TJ - Junction 'Thmperature ('C)
Thermal Ratings
20 Maximum Drain Current vs. Case Temperature
Safe Operating Area
100
1001lS
S
16
iii
~
12
·01
'"
0
8
a
-
............
s
..........
~
i'...~
'"
I
oS
4
o
a
-
limited by
-
fDS(cn)
,,"
.,
1ms
I
r-....
"-
10
·eQ'"
10ms
I
~
oS
-
\
......
Tc =2S'C
Single Pulse
I
100m
""
dc ~
0.5
o
25
50
75
100
125
150
2
Tc - Case'Thmperature ('C)
10
100
WO
VDS - Drain-to-Source Voltage (V)
Normalized Thermalll:ansient Impedance, Junction-to-Case
2
II
Duty Cycle
0.5
0.2
~
,...
P"'"
0.1
0.05
0.02
singlePul~ ~
""
I 1"1111..
0.01
10-5
10-4
10-3
10-2
10-1
3
Square Wave Pulse Duration (sec)
6-220
P-36731-Rev. C (05/30/94)
TEMIC
2N7224JANTX/JANTXV
Siliconix
N -Channel Enhancement-Mode Transistors
Product Summary
Vns(V)
fnS(on) (Q)
In (A)
100
0.081
34
Parametric limits in accordance with MIL-S-I9500/592 where applicable.
TO-254AA
D
Hermetic Package
o
Case Isolated
S
D S G
N-Channel MOSFET
Top View
Absolute Maximum Ratings (Tc
= 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
Vns
100
Gate-Source Voltage
Vas
±20
Continuous Drain Current (TJ = 150°C)
IT c=25°C
ITc= 100°C
Pulsed Drain Current
Avalanche Current
ITc=25°C
Operating Junction and Storage Temperature Range
V
34
In
InM
Maximum Power Dissipation
Unit
21
136
A
IAR
34
Pn
150
W
TJ,Tstg
-55 to 150
°C
Symbol
Limit
Unit
RthJC
0.83
0c/w
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Case
P-37164-Rev. A (06106/94)
6-221
TEMIC
2N7224JANTX/JANTXV
Specifications (TJ = 25°C Unless Otherwise Noted)
Siliconix
Limit
Parameter
Symbol
Test Condition
Min
Vos = 0 V; 10 = 1000 !lA
100
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
V(BR)DSS
5.0
Vos - Vos, 10 - 250 J.lA, TJ - -SS'C
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistanceb
VOS(th)1
loss
loss
fDS(on)
Vos = Vos,lo = 250 J.lA, TJ = 2S'C
2.0
Vos = Vos, 10 = 250 J.lA, TJ = 12S'C
1.0
V
4.0
Vos = OV;Vos= ±20V
±100
Vos - OV; Vos = ±20V; TJ - 12S'C
±2oo
nA
Vos - 80 V; Vos = OV
25
Vos = 80 V; Vos = OV; TJ = 125'C
250
Vos = 100 V; Vos = 0 V; TJ = 12S'C
1000
Vos = 10V; 10 = 34A
0.081
Vos - 10 V; 10 - 21 A, TJ - 125'C
0.11
!lA
Q
Dynamic
Thtal Gate Chargee
Qg
Gate-Source ChargeC
Qgs
Gate-Drain ChargeC
Qgd
'fum-On Delay TImee
RiseTImec
'fum-Off Delay TImec
FaIlTImec
SO
Vos = 50 V; Vos = 10 V; 10 = 34A
td(off)
22
15
65
nC
35
td(on)
tr
125
8
Voo = 50V;RL= 1.47Q
10'" 34 A, VOBN= lOV;Ro = 2.35 Q
190
170
ns
130
tf
SCl!l"ce-Dre!!! DlQ(1,. RatIngs and Characteristics
Continuous Current
Is
34
Pulsed Current
ISM
136
Diode Forward Voltageb
Vso
IF = 34 A, Vos = OV
1.8
V
Reverse Recovery Time
trr
IF = 34 A, difdt = 100 NItS
500
ns
A
Notes:
a. For design aid only; not subjcctto production testing.
b. Pulse test; pulse width s 300 !,S, duty cycle s 2%.
c. Independent of operating temperature.
6-222
P-37164-Rev. A (06fQ6/94)
TEMIC
2N7225JANTX/JANTXV
Siliconix
N -Channel Enhancement-Mode 'l.ransistors
Product Summary
Vns(V)
rnS(on) (Q)
In (A)
200
0.105
27.4
Parametric limits in accordance with MIL-S-J9500/592 where applicable.
TO-254AA
D
Hennetic Package
o
Case Isolated
s
D S G
N-Channel MOSFET
ThpView
Absolute Maximum Ratings (Tc
= 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
200
Gate-Source Voltage
VGS
±20
Unit
V
Continuous Drain Current (TJ = 150°C)
27.4
ITc = 25°C
ITc = 100°C
ID
17
A
Pulsed Drain Current
Avalanche Current
Maximum Power Dissipation
ITc = 25°C
Operating Junction and Storage Thmperature Range
IDM
110
IAR
27.4
PD
150
W
TJ. Tstg
-55 to 150
°C
Symbol
Limit
Unit
RthJC
0.83
°crw
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Case
P-37164-Rev. A (06/06194)
6-223
TEMIC
2N7225JANTX/JANTXV
Specifications (TJ = 25°C Unless Otherwise Noted)
Siliconix
Limit
Parameter
Test Condition
Min
= Ov, In = 1000 !1A
= -SS·C
Vns = VGs. In = 250 jlA, TJ = 2S·C
Vns = VGs. In = 2S0 jlA, TJ = 12S·C
200
Symbol
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
V(BR)DSS
VGS
Vns = VGs. In = 2S0 jlA, TJ
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistanceb
VGS(lh)
IGSS
Inss
rnS(on)
5.0
2.0
1.0
Vns-OV,VGS- ±20V
±100
Vns - 0 V, VGS - ±20 V, TJ -l25·C
±WO
nA
Vns = 160 V, VGS = OV
= 160 V, VGS = Ov, TJ = 12S·C
250
Vns = 200 V, VGS = Ov, TJ = 12S·C
1000
VGS = 10 V, In = 27.4 A
0.105
VGS - 10 V, In - 17 A, TJ - 12S·C
0.17
Vns
V
4.0
25
~A
Q
Dynamic
'!btal Gate ChargeC
Qg
Gate-Source ChargeC
Q gs
Gate-Drain ChargeC
Qgd
Thrn-On Delay TImec
Rise l1mec
Thrn-Off Delay TImec
FallTImec
55
Vns = 100 V, VGS
= 10 V, In = 27.5 A
22
30
60
td(of!)
nC
35
td(on)
tr
115
8
190
Vnn = 100 V, RL = 3.6 Q
In '" 27.4 A, VGEN = 10 V, RG = 2.35 Q
170
ns
130
tf
Source-Drain Diode Ratings and Characteristics
Continuous Current
Is
27.4
Pulsed Current
ISM
110
Diode Forward Voltageb
Vsn
Reverse Recovery TIme
t ff
A
IF = 27.4 A, VGS = OV
IF - 27.4 A, di/dt
= 100 N~
0.8
1.9
V
950
ns
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width S 300 ~s. duty cycle S 2%.
c. Independent of operating temperature.
6-224
P-37164-Rev. A (06/06/94)
TEMIC
2N7227JANTX/JANTXV
Siliconix
N -Channel Enhancement-Mode Transistors
Product Summary
VDS(V)
rDS(on) (Q)
ID (A)
400
0.415
14
Parametnc ltmits in accordance with MIL-S-J9500/592 where applicable.
TO-254AA
Hermetic Package
D
o
G~
Case Isolated
S
D S G
ThpVlew
N·Channel MOSFET
Absolute Maximum Ratings (Tc = 25°C Unless Otherwise Noted)
Parameter
Symbol
limit
Drain-Source Voltage
VDS
400
Gate-Source Voltage
VGS
±20
Continuous Drain Current (TJ = 150°C)
Pulsed Drain Current
ID
IDM
Avalanche Current
Maximum Power Dissipation
ITc = 25°C
Operating Junction and Storage Temperature Range
V
14
lTC = 25°C
ITc = 100°C
Unit
9
56
A
IAR
14
PD
150
W
TJ.T,lg
-55 to 150
°C
Symbol
limit
Unit
RthJC
0.83
°CIW
Thermal Resistance Ratings
Parameter
Maximum lunction4o-Case
P-37164-Rev. A (06/06/94)
6-225
TEMIC
2N7227JANTX/JANTXV
Specifications (TJ = 25°C Unless Otherwise Noted)
Siliconix
Limit
Parameter
Symbol
Test Condition
Min
Vas = Ov, 10 = 1000 IlA
400
lYP'"
Max
Unit
Static
Drain-Source Breakdown Voltage
V(BR)OSS
Vos = Vas, 10 = 250 JU\, TJ = -55'C
Gate Threshold Voltage
VaS(tb)
Gate-Body Leakage
lass
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance b
loss
1'])S(on)
5.0
Vos - Vas, 10 - 250 JU\, TJ - 25'C
2.0
Vos = Vas, 10 = 250 JU\, TJ = 125'C
1.0
V
4.0
Vos = Ov, Vas = ±20V
±100
Vos = OV,Vas = ±20V,TJ = 125'C
±200
nA
Vos = 360 V, Vas = OV
25
Vos = 360 V, Vas = 0 V, TJ = 125'C
250
Vos = 400 V, Vas = 0 V, TJ = 125'C
1000
Vas - 10 V, 10 - 14 A
0.415
Vas = 10 V, 10 = 9A, TJ = 125'C
0.68
I'A
g
Dynamic
Thtal Gate ChargeC
Qg
Gate-Source ChargeC
Qg.
Gate-Drain ChargeC
Qgd
Thrn-On Delay TImec
RiseTImec
Thrn-Off Delay TImeC
FallTImec
Svurc~-D:-ein Diod~ R!:lti~glli
Continuous Current
52
Vos = 200 V, Vas = 10V,Io = 14A
td(off)
18
25
65
nC
35
td(on)
tr
110
5
Voo = 200 V, RL = 14.2 g
10'" 14 A, VaEN = 10 V, Ra = 2.35 g
te
190
170
ns
130
and CharacUristits
Is
14
Pulsed Current
ISM
56
Diode Forward Voltageb
Vso
IF = 14 A, Vas - OV
1.7
V
Reverse Recovery TIme
tIT
IF = 14 A, dildt - 100 NilS
1200
ns
A
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width s 300 liS, duty cycle s 2%.
c. Independent of operating temperature.
6-226
P-37164-Rev. A (06/06194)
TEMIC
2N7228JANTX/JANTXV
Siliconix
N-Channel Enhancement-Mode Transistors
Product Summary
Vns(V)
rnS(on) (9)
In (A)
500
0.515
12
Parametric limits in accordance with MIL-S-J9500/592 where applicable.
TO-2S4AA
Hermetic Package
D
o
G~
Case Isolated
S
D S G
N-Channel MOSFET
Top View
Absolute Maximum Ratings (Tc
= 25°C Unless Otherwise Noted)
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
500
Gate-Source Voltage
Vas
±20
Continuous Drain Current (TJ = 150'C)
Pulsed Drain Current
ID
IDM
Avalanche Current
Maximum Power Dissipation
ITc =25'C
Operating Junction and Storage Temperature Range
V
12
I Tc=2S'C
ITc = 100'C
Unit
8
48
A
IAR
12
PD
150
W
TJ. T,tg
-55 to 150
'C
Symbol
Limit
Unit
RthJC
0.83
'crw
Thermal Resistance Ratings
Parameter
Maximum Junction-to-Case
P-37164-Rev. A (06/06/94)
6-227
TEMIC
2N7228JANTX/JANTXV
Specifications (TJ = 25°C Unless Otherwise Noted)
Siliconix
Limit
Parameter
Symbol
Min
Test Condition
1YP"
Max
Unit
Static
Drain-Source Breakdown Voltage
Vos = 0 Y, 10 = 1000
V(BR)DSS
f.IA
500
5.0
VOS = Vos, 10 = 250 jU\, TJ = -55'C
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistanceb
VOS(th)
loss
loss
roS(on)
Vos - Vos, 10 - 250 jU\, TJ - 25'C
2.0
Vos = Vos, 10 = 250 jU\, TJ = 125'C
1.0
V
4.0
Vos = OY,Vos = ±20V
±100
= OY, Vas = ±20Y,TJ = l25'C
VDS = 400Y, Vos = OV
VDS = 400 Y, Vas = 0 Y, TJ = 125'C
±200
VDS - 500 Y, Vas - 0 Y, TJ - 125'C
1000
Vas -lOY,ID -12A
0.515
Vas = 10Y,ID = 8A, TJ = 125'C
0.9
nA
VDS
2.5
250
f.IA
Q
Dynamic
Thtal Gate ChargeC
Og
Gate-Source ChargeC
Ogs
Gate-Drain ChargeC
Ogd
Thrn-On Delay Tunec
td(on)
35
tr
190
Risenmec
Thrn-Off Delay limec
Faillimec
SQ!!r~-DI""ln
1d(olf)
55
VDS = 250Y, Vas = lOY, ID = 12A
VDD = 250 Y, RL = 20.8 Q
ID '" 12A, VaEN = lOY, Ra = 2.35 Q
120
5
19
27
70
170
nC
ns
130
tl
Diode Ratings and Characteristics
Continuous Current
Is
12
Pulsed Current
ISM
48
Diode Forward Voltageb
VSD
IF = 12 A, Vas = OV
1.7
V
Reverse Recovery lime
Irr
IF = 12 A, dildt = 100 NfIS
1600
ns
A
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width S 300 !,S, duty cycle S 2%.
c. Independent of operating temperature.
6-228
P-37164-Rev. A (06/06/94)
Appendix.
TEMIC
Faxback Information
Siliconix
FREE iNFO 24 HOURS A DAY
365 DAYS A YEAR
Siliiconix Faxback 408-970-5600
With Siliconix Faxback, all it takes is a touch-tone phone plus a few simple
commands. Data sheets and application notes on our power les, LITTLE
FOOT® power transistors, analog switches, analog multiplexers, and
low-power transistors will be sent to your fax machine - instantly!
How It Works
If you're calling for the first time, please follow these easy steps.
a
From a Touch-Tone Phone, Just Dial 408-970-5600
Siliconix Faxback will answer and lead you through a series of easy-to-understand automated voice
prompts.
Order A Directory
Soon after calling, you will be asked whether you want to order a directory. Please order any or all of
the directories listed below. A directory describes the available documents and gives you the Faxback
order numbers for those documents.
a
Power Products Data Sheet Directory
Includes power transistors and integrated circuits for use in computers, automobiles, telecom
systems, and a host of other applications. Data sheets and SPICE models are available for all
LITILE FOOT products, the industry's largest family of small-outline, surface-mount power
MOSFETs for motion control and load management.
a
Analog ICs Data Sheet Directory
Includes analog switches and multiplexers used to route signals in video, multimedia,
instrumentation, and test equipment in both the industrial and hi-rei environments.
a
Low-Power Discretes Data Sheet Directory
Includes JFETs, DMOS switches, low-power MaS transistors, low-leakage pico-amp diodes, voltage
controlled resistors, and current regulator diodes, packaged for both the industrial and hi-rei
environments.
a
Application Note Directory
Includes application notes for power products, analog ICs, and small-signal transistors.
(05/18/94)
7-1
TEMIC
Faxback Information
Siliconix
Enter Your Fax Number
When you're through ordering, Siliconix Faxback will ask you for the fax number of the machine you
want your directories sent to. Just type in the area code and phone number on your touch-tone phone.
If you are sending the information to a fax machine outside of North America, make sure you dial
"011" first.
Identify Your Fax
Faxback lets you choose how your documents will be addressed. You can enter your name or your voice
phone number. When the fax arrives at your selected destination, it will have your name or voice number
on the cover sheet to identify it.
Hang Up
The information you ordered will be sent immediately. It's as easy as 1 + 2
= 3!
Once you have received and reviewed your directories, just call back and enter the Siliconix Faxback
numbers of the data sheets and application notes you want.
In most cases, you will receive your documents within 5-10 minutes. If for some reason your fax machine
is in use when Faxback is ready to send your documents, Faxback will automatically call back - up to
three times (at two minute intervals) - until it reaches your fax machine. If after the third call your
machine is still in use, you will have to call back and order your documents again.
Enter Name
Call
.1-------'~,
(
)
Entering Your Name
In addition, you can use your touch-tone phone to spell out your name. Just follow this simple system.
The documents you request will be sent with a cover sheet bearing your name. Or you can choose simply
to have documents addressed to your ditect phone number.
D enters A, DR enters B; RRD enters C.
Special characters: D D - Q; D D D - Z; El El - SPACE.
To back up and correct a letter, press:D. To end, press: El. For complete instructions, press:~ .
To enter a letter, press its key 1, 2, or 3 times:
7-2
TEMIC
Applications Information
Siliconix
The following literature is designed to help you use Siliconix products in your applications. Call our FaxBack
system (408-970-5600) to have the document sent to you immediately via facsimile, or to order a copy to be
sent by mail, call 800-554-5565.
Application Notes for Siliconix Power Products Products
Application
Note
Number
FaxBack
Code
Number
Description
LITTLE FOOT'" MOSFETs
Designing with Complementary Power MOSFETs in Surfaee·Monnt (SO·8) Packages
AN801
8801
The LIlTLE FOOT complementary n- and p-channel Si9942DY can be used to drive inductive loads such as
motors, solenoids, and relays dlTectly, or it may be used as a low-impedance buffer to drive larger power
MOSFElS or capacitive loads. In 12-V battery-powered applications, the Si9942DY allows a substantial
increase In motor size without the need for additional heatsinking.
Low-Voltage Motor Drive Designs Using N·Channel Dual MOSFETS in Surface-Monnt Packages
AN802
8802
Dual n·channel LIlTLE FOOT devices offer on-resistance advantages which extend the power range of
surface-mount power devices. With the selection of a high-side gate drive circuit that complements an
application's needs, an n-channel half-bridge can provide a surface· mount option that is economical and
reliable.
Thermal Characteristics of Siliconu's LITTLE FOOT Family of Surface-Monnt MOSFETs
AN803
LITEFOOT~
8803
Sihconix' LIlTLE FOOT family of surface-mount power MOSFElS provides improved thermal transfer
characterisllcs, high current handling capability, and lower on-resistance compared with DPAK and SOT
packages. The copper lead frames designed for the LIlTLE FOOT family maximize heat transfer to the PC
board Combined with Siliconix' high-density transistor technologies, the result is a significantly extended range
for surface-mount devices in power applications.
MOSFETs
LITE FOOT, The Next Step in Surface-Mount Power MOSFETs
ANIOOI
8501
LITE FOOT is the first family of power MOSFElS combining high-density n- and p-channel technologies with
TSSOP packaging. With a 1.1 mm profile, LITE FOOT devices are small enough to fit into any standard
PCMCIA card. They provide an equally compact solution for load switching in small form-factor disk drives,
cellular telephones, notebook computers, PDAs, and other applications where space and battery life is at a
premium.
Power MOSFETs
Unclamped Inductive Switching Rugged MOSFETs for Rugged Environments
AN601
8601
This application note reviews the history of unclamped inductive switching (UIS) and examines various theories
pertaining to failure. It further identifies what appears to be two releated mechanisms -- thermal and bipolar -beheved to be responsible for failure during UIS and concludes by recommending how a power MOSFET
should be qualified for ruggedness in the data sheet.
PowerICs
Designing High-Frequency DC-to-DC Converters with the Si9114 Switchmode Controller
AN701
8701
AN702
8702
The Si9114 controller enables high-frequency power conversion by reducing delay times and adding additional
features over previous generation products. As a result, dc-to-dc converters can be designed for frequencies up
to 1 MHz with simple PWM topologies instead of the complex resonant ones. High-frequency designs with the
S19114 will enable deSigners to reduce the size of energy storage components, increase reliability by using
ceramic capacitors, and simplify the implementation of a distributed power architecture.
Efficient ISDN Power Converters Using the Si9100
(06/09/94)
The Si9100 power IC facilitates compliance with ISDN design requirements with a minimum number of
external parts. To illustrate this capability, a discontinuous conduction mode (DCM) flyback converter was
built and tested with measured effiCIency greater than 80% for a wide range of loads.
7-3
TEMIC
Applications Information
Siliconix
Application Notes for Siliconix Power Products Products (Cont'd)
Application
Note
Number
FaxBack
Code
Number
Description
PQwer ICs (CQnt'd)
Designing DC/DC Converters with the Si9110 Switchmode Controller
AN703
8703
Si9110 is the first BiC/DMOS switchmode controller IC to provide switching frequencies in the 100- to SOO-kHz
range while keeping current limit delay time under approximately 100 ns. 1h illustrate the Si911O's capabilities,
a lS-W forward converter is presented, providing 5-V and 12-V outputs from a 9- to 36-V input range.
AN704
8704
This application note specifically addresses design issues relating to emergency-designated ISDN terminals and
presents design details for a dc-ta-dc converter which conforms to the international standard.
Designing DClDC Converters to Meet CCITT Specifications for ISDN Terminals
The Si9910 Adaptive Power MOSFET Driver Improves Performance in High-Voltage Half-Bridge Applications
AN705
8705
The Si9910DY introduces a new generatton 01 "aoaptlve" power Ivi03:r.ET Sd.t~ dri.·Ci:i t!:i.:ot u:;~ ~!:.,': f:edb:!~!:
to protect the power MOSFET, while allowing logic-level control of high-voltage signals. When all of its
protective options are enabled, the Si9910DY is capable of controlling the power MOSFET dvldt, maximum
peak current, minimum gate-drive voltage, and maximum source-drain voltage drop.
Motor Drive Circuits Using the D469A
AN706
8706
The D469Acontains four independent drive channels, and each channel can be configured as a logically
inverting or non-inverting driver. Since the D469A is a CMOS device, it is compatible with low-power CMOS
logic and microprocessors and draws minimal quiescent current. In motor drive applications, the D469A
provides optimized gate drive signals and simplifies interface to the logic level control circuitry.
Designing Low-Power Off-Line F1yback Converters Using the Si9120 Switchmode Controller IC
AN707
8707
The Si9120 was designed to get high efficiency from low-power off-line power supplies. This current-mode
control PWM IC reduces typical quiescent power requirements to 0.85 rnA while driving a 500-pF load at SO
kHz. The chip contains MOS capacitors for the clock circuit, so the only external timing component required is
a resistor to set the operating frequency.
Low-Power Universal-Input Power Supply Achieve, High Efficiency
AN708
8708
AN709
8709
A f1yback circuit using the Si9120 PWM controller demonstrates that designing universal-input supplies can be
a simple task. Good regulation is achieved while maintaining the 3750-V ac input-to-output isolation mandated
by VDE. The Si9120 eliminates the need for external start-up circuitry, and its foldback current limiting
requires no feedback across the isolation boundary.
Designing with the Si9976DY N-Channel Half-Bridge Driver and Ln"ILE FOOT Duai MOSFET.
The combination of the Si9976DY and a liTTLE FOOT MOSFET rated between 2 and 5 A creates a powerful
and flexible solution for power switching in dc motor drives in 20- to 40-V systems.
High-Efficiency Buck Converter for Notebook Computers
AN710
8710
This application note presents a dc-to-dc converter consisting of the Si9150CY BiCMOS controller IC and
LITILE FOOT low-voltage MOSFE'Th. In notebook computers and other portable products, the converter
achieves a maximum efficiency of 94% while producing 400 rnA at 3.3 V with input voltage of 6 V. The low
losses of this efficient buck converter eliminate the need for heavy heat sinks and device packaging, and makes
energy that is normally consumed by the power converter available for the application.
A High-Voltage Half-Bridge Using the Si9901 with the Si9911 or Si9914
AN712
8712
AN713
8713
The Si9901 can be used with the Si9911 or Si9914 MOSFET drivers as a two-package approach to half-bridges
for applications in systems with operating voltages up to 500 VDC. The resulting chip set provides the best
available electrical isolation between the low and high sides, enhances noise immunity in level shifting cirCUitry,
and allows the use of cost-effective manufacturing processes.
A I-Watt F1yback Converter Using the Si9100
Power integrated circuit technology allows low-power CMOS control circuits to be combined with DMOS
power transistors in the Si9100. The resulting reduction in parts count decreases system cost, improves
reliability, and simplifies circuit design in feature phones and ISDN terminals.
A Compact Controller for Brushl.., DC Motors
AN714
7-4
8714
The Si9979 is a monolithic controller with integral high-side drive circuitry, allowing easy implementation of an
a11-n-channel three-phase bridge. An internal voltage regulator allows the Si9979 to operate over a wide input
voltage range, 20 to 40 V DC, and to power commutation sensors over this same range. Housed in a 7 mm
SQFP package, the Si9979 reduces assembly cost and simplifies both motor and electronics packaging.
(06/09/94)
TEMIC
Siliconix
Introduction
Reliability at Siliconix is ensured with two primary
programs: the Reliability Qualification Program and the
Reliability Monitoring Program. Siliconix publishes this
data by product family and it can be obtained by request
through your local sales office.
Qualification Program
Qualification programs of accelerated stress testing are
developed for the introduction of new devices (die
qualifications), packages, major process changes, new
materials or suppliers, new manufacturing equipment,
and new manufacturing locations.
A qualification starts after a qualification test plan is
developed. This plan specifies the following:
•
•
•
•
•
•
•
•
•
Purpose and scope
Device or geometry types and packages being
qualified
Process and assembly specs involved
Test vehicles and location
Tests and stresses
Duration of each stress
Sample sizes
Acceptance criteria
Number of lots required
Reliability Information
component is accelerated by applying stress that is more
severe than that encountered under normal operating
conditions. This acceleration is produced by elevating
temperatures, increasing humidity or pressure,
alternating hot and cold temperature, switching power
on and off, or some combination of these conditions.
The test results are used to predict normal operating
performance. In the sections below we present a brief
description of each stress.
Summary of Tests
High-Temperature Reverse-Bias (HTRB) Test
The mRB accelerated test is performed under reverse
biasing at an elevated temperature of 150°C or 175°C
with the drain-to-source junction reversed biased to 80%
of BVDSS.
According to the reliability monitor
specification, devices are to be tested at 168 hours
(providing a fast reaction and infant mortality
indication) and at the end point of 1000 hours.
Reliability failure rates (expressed in FITs-Failures In
Time) are then calculated from the long-term results.
The reverse-biased test condition checks the integrity of
the field termination and the quality of the body-drain
junction. This test also detects surface states, especially
in the termination area.
Monitoring Program
The Reliability Monitoring Program, which includes
accelerated life tests, is designed to continuously monitor
product reliability. The program furnishes up-to-date
failure-rate and failure-mechanism data which can be used
to predict and improve long-term reliability performance.
The Monitoring Program covers a wide range of
technologies and product lines manufactured by Siliconix.
In order to accomplish this, products are grouped by
similar technologies. For example, components built in the
same wafer fab, using the same manufacturing processes,
having similar complexity, functionality, and package types
are grouped into a technology family. One component or
more representing each technology group is monitored
according to a quarterly schedule.
The short-term and long-term monitor tests are outlined
in Tables 1 and 2. Also, the Reliability Monitor Program
is summarized in general outline form as a flow chart in
Figure 1 and with operating life data in Table 3.
Accelerated Reliability
Accelerated tests were developed to shorten the time
required for reliability testing. The life cycle of a
(06/09/94)
High-Temperature Gate-Bias (HTGB) Test
The mGB accelerated test is performed with the gate
biased to 80% of the gate-to-source voltage rating and at
an elevated temperature of 150°C or 175°C. Test points
are the same as for the HfRB stress. Biasing of the gate
accelerates failures due to oxide defects or the presence
of mobile ions. The long-term results are used in the
prediction of reliability failures.
Temperature Cycling Test
Temperature cycling exploits the differences in thermal
coefficients of expansion between silicon and the other
materials used in die fabrication and packaging. Each
cycle consists of lO-minute exposures (-60°C for
MOSPOWER Discretes, -65°C for Power ICs) and
150°C with a I-minute transfer at room temperature
between the temperature extremes. This test reveals
potential weaknesses in die and package materials and
construction and in the integration of the die and
package.
7-5
TEMIC
Reliability Information
Thermal Shock Test
The purpose of the thermal shock test is similar to that
of temperature cycling. This stress is more extreme,
however, due to the fact that the ambient medium is
liquid and not air, and the transition time is much shorter
than for temperature cycling.
Each cycle consists of a 5-minute exposure at -60°C or
-65° and 150°C with a maximum 10-second transfer
time between the temperature extremes.
Bias Humidity Test
The bia:; humidity
te~t is !!sed to test p!a5tic: r~t:'k~gp:cf
devices for the effects of moisture penetration while
Siliconix
electrical potentials are applied. The components are
placed in a biased condition and then are subjected for
1000 hours to a temperature of 85°C and a relative
humidity 85%. This test confirms package integrity.
Pressure Pot Test
In the pressure pot test, water vapor is forced into
non-hermetic packages via micro gaps in the
package-lead seal. Water is then carried to the die
surface via capillary action of the bond wires. Electrical
leakage may result. External contamination of the
package or lead finish may be transported to the die or
may directly cause corrosion of the leads.
Record Results and Failure
Mechanisms in Worldwide
Database
Customer Reliability
Reports and Summaries
Internal Reliability
Monitor Report
Figure 1. Reliability Monitor Flow (Short- and Long-Term Monitors)
7-6
(06/09/94)
TEMIC
Reliability Information
Siliconix
MOSPOWER Discretes
Table 1. Short-Term Reliability Monitor for MOSPOWER Discretes
Test
Condition
Sample Size
Te.tpoints
HfGB
150'Cor 17S'C
168 hours
HfRB
50
121 'c, 15 PSIG
Pressure Pot
96 hours (Plastic)
liquid to liquid. -65'C to 150'C
100 cycles
Solderability
MIL-SID-883D, M2003
(245'C ±5'g
Lead Integrity
MIL-SID-883D, M2OO4
Thennal Shock
15 leads
Marking Permanency
MIL-SID-883D, M201S
16
Salt Atmosphere
MIL-SID-883D, Ml009
15
24 hours (Hermetic)
Table 2. Long-Term Reliability Monitor
Test
Condition
Sample Size
Test Points
HTGB
150'C or 175'C
0, 168, 1000 hours
lITRB
50
Biased Humidity (Plastic)
85'C, 85% relative humidity
Thmperature Cycling
Air-to-air -65'C to 150'C
Power Cycling
0, 500, 1000 hours
0, 250, 1000 cycles
30
11 TJ = 100'C
0, 2000, 6000 cycles
Table 3. Operating Life Data
msa
Higb Temperature
Operating LiCe Technology
PowerMOS
Number of Units
Equivalent Device Hours
at SS'Cand0.6 eV
O.6eV
1.0eV
24,786
2,649,447,243
0.3
om
Note:
a. 1 failure per billion device hours
(06/09/94)
7-7
TEMIC
Reliability Information
Siliconix
Power IC's
Table 1. Short-Term Reliability Monitor for Power IC's
Test
Condition
Sample Size
'IIlst Points
Static Operating llie
168 hours
150"C
Dynamic Operating llie
50
Pressure Pot
121 "C, 15 PSIG
ThennaI Shock
96 hours (Plastic)
liquid to liquid. -60"C to 150"C
100 cycles
M70ffi
SoiderabiliLY
M!!'-STD-~R~n.
Lead Integrity
MIL-SlD-883D, M2OO4
lid 'lOrque
MIL-SlD-883D, M2024
Marking Pennanency
MIL-SID-883D, M2015
16
Salt Almosphere
MIL-SlD-883D, Ml009
15
(245"C ±5"C)
15 leads
(Hennetic)
24 hours (Hennetie)
Table 2. Long-Term Reliability Monitor
Test
Condition
Sample Size
Test Points
Static Operating Life
0, 168, 1000 hours
150"C
Dynamic Operating Life
50
Biased Humidity (Plastic)
85"C, 85% relative humidity
0, 500, 1000 hours
'Thmperature Cycling
Air-to-air -60"C to 150"C
0,250, 1000 cycles
Table 3. Operating Life Data
FITs"
Higb Temperature
Operating Life Technology
PowerIC
Number of Units
Equivalent Device Hours
at 55'C and 0.6 eV
O.6eV
1.0eV
2,097
4,618,752,555
7.2
0.35
Note:
a. 1 failure per billion device hours
7-8
(06/09/94)
TEMIC
Package Information
Siliconix
• Ceramic DIP, 8· to 16·Pin
Dim
[]Il
A
A1
b
b1
C
D 8
D 14
D 16
E
E1
e
e1
L
L1
1-2 J L1
~e~~~b1
1-2
f
S 8
S-14
S-16
e
Millimeters
Min
Max
Inches
Min
Max
4.06
5.08
1.27
2.16
1.14
1.65
0.38
0.51
0.20
0.30
9.40
10.16
19.05
19.56
19.05
19.56
6.60
7.62
7.62
8.26
2.54BSC
7.62BSC
5.08
381
3.18
3.81
0.51
1.14
0.64
1.52
1.65
2.41
0.38
1.14
0.160
0.200
0.050
0.085
0.045
0.065
0.D15
0.020
0.008
0.012
0.370
0.400
0.750
0.770
0.750
0.770
0.260
0.300
0.300
0.325
0.100BSC
0.300BSC
0.150
0.200
0.125
0.150
0.020
0.045
0.025
0.060
0.065
0.095
0.045
0.D15
0'
15'
0'
15'
• Hermetic Power Module
R
0P
Dim
A
A1
0b
D
Bent Up!Down,
Straight Leads
E
E1
e
e1
L
L1
0P
Q
R
S
Bent Up Lead
(06/10/94)
Millimeters
Min
Max
Inches
Min
Max
6.10
1.14
0.89
24.89
24.89
2.79
15.62
2.92
4.44
12.32
3.84
38.35
4.19
4.57
0.240
0.045
0.035
0.980
0.980
0.110
0.615
0.115
0.175
0.485
0.151
1.510
0.165
0.180
7.11
1.40
1.14
25.91
25.91
3.30
16.13
3.43
6.35
4.09
38.86
4.44
4.95
0.280
0.055
0.045
1.020
1.020
0.130
0.635
0.135
0.250
0.161
0.161
0.175
0.195
Bent Down Lead
7-9
....
~
'g
~
~
~
TEMIC
Package Information
Siliconix
• Plastic DIP, 8- to 20-Pin
O
1
2
ff
E
~
Dim
A
Al
A2
b
bl
c
D-8
EI
!
'~~ ,
[1-1&
t
I
II
A
,J~, JL,
~
L
I
I
"
\I
h
c
\\
\\
\
I--el--l
e~
D-16
D-20
E
EI
e
el
L
S-8
S-14
S-16
S-20
e
Millimeters
Min
Max
Inches
Min
Max
3.81
0.38
1.27
0.89
0.38
0.20
9.65
1727
18.93
24.89
5.59
7.62
2.29
7.37
2.79
1.02
1.02
0.38
1.02
O·
0.150
0.D15
0.050
0.Q35
0.015
O.OOB
0.380
0.680
0.745
0.980
0.220
0.300
0.090
0.290
0.110
0.040
0.040
0.D15
0.040
O·
5.08
1.27
2.03
1.65
0.51
0.30
11.68
19.30
21.33
26.92
7.11
8.26
2.79
7.87
3.81
2.03
2.03
1.52
2.03
15·
0.200
0.050
0.080
0.065
0.020
0.012
0.460
0.760
0.840
1.060
0.280
0.325
0.110
0.310
0.150
0.080
O.OBO
0.060
0.080
15·
• PLCC Package, 20-Pin
Dim
A
Al
b
bl
D
DI
E
e
L
Millimeters
Min
Max
Inches
Min
Max
4.20
4.57
2.29
3.04
0.66
0.81
0.33
0.55
9.78
10.03
8.89
9.04
7.37
8.38
1.27BSC
0.51 I
0.165
0.180
0.090
0.120
0.026
0.032
0.021
0.013
0.385
0.395
0.350
0.356
0.290
0.330
0.050BSC
0.020 I
Qf--==-I
7-10
(06/10/94)
TEMIC
Package Information
Siliconix
• Sidebraze DIP, 14- to 24-Pin
F9
--J!- c
r--
.
el----1
Dim
Millimeters
Min
Max
Inches
Min
Max
A
b
bl
c
D 14
D-16
D-20
D-24
E
El
e
el
L
Ll
Q
S-14
S-16
S-20
S-24
2.67
4.44
0.97
1.52
0.38
0.53
0.20
0.30
17.53
19.55
19.56
21.08
26.16
24.89
31.24
29.97
7.12
7.87
7.37
8.25
2.54 BSC
7.62BSC
3.18
4.44
0.64
1.39
0.25
0.77
2.41
0.51
1.65
0.77
1.65
0.77
2.41
0.105
0.175
0.Q38
0.060
0,015
0.021
0.008
0.012
0.690
0.770
0.770
0.830
0.890
1.030
1.180
1.230
0.280
0.310
0.290
0.325
0.100BSC
0.300BSC
0.125
0.175
0.025
0.055
0.010
0.030
0.095
0.020
0.065
0.030
0.065
0.030
0.095
Dim
Millimeters
Min
Max
Inches
Max
Min
1.35
1.75
0.10
0.20
0.35
0.45
0.18
0.23
5.00
4.69
8.75
8.55
9.80
10.00
4.05
3.50
5.70
6.30
1.27BSC
0.60 I 0.80
O·
8·
0.053
0.069
0.004
0.008
0.Q18
0.014
0.007
0.009
0.185
0.196
0.336
0.344
0.385
0.393
0.140
0.160
0.248
0.224
0.050BSC
0.024 . I 0.031
.. SO Package, 8- to 16-Pin
A
Al
B
c
D-8
D-14
D-16
E
El
e
L
e
(06/10/94)
O·
8·
7-11
TEMIC
Package Information
Siliconix
• SQFP, 48- to 64-Pin
Millimeters
Min
Max
Inches"
Min
Mal!
A
1.35
1.60
0.053
0.063
Al
b
C
D 18
D-64
0.04
0.14
0.117
690
9.90
8.70
0.16
0.26
0.177
0.002
0.006
0.005
0.272
0.390
0.343
0.461
0.006
0.010
0007
0.280
0.398
0.366
0.484
0.016
0.024
0.307
0.425
Dbn
DI-48
DI-64
/ " " Pin 1 Indicator
$
710
10.10
9.30
11.7
12.3
e
0.40
L-48
L-64
-
0.60
7.80
to.80
-
LI-48
7.80
LI-64
10.80
8.20
11.20
0.425
0.323
0.441
~
0.30
0.70
0.012
0.028
0'
7'
0'
7'
e
0.307
"For Reference Only
.TO-205AD/AF (TO-39)
7-12
Dim
Millimeters
Min
Max
Inches
Min
Max
A-AD
A-AF
Al
0b
0D-AD
0D-AF
0DI-AD
0DI-AF
e
el
j
k
L
6.10
6.60
4.07
4.57
0.23
1.04
0.41
0.53
8.51
9.39
8.64
9.39
7.75
8.51
8.01
8.64
5.08Bse
2.54 Bse
0.72 I 0.86
0.74 I 1.14
12.70 I 19.05
0.240
0.260
0.160
0.180
0.009
0.041
0.016
0.021
0.335
0.370
0.340
0.370
0.305
0.335
0.315
0.340
0.200Bse
0.100Bse
0.028 I 0.034
0.029 j 0.045
0.500 I 0.750
(06/10/94)
TEMIC
Package Information
Siliconix
• TO-220AB
Dim
0P
A
Al
0
I"b
c
])
E
"
"I
H
J
1.
1.1
I"P
Millimeters
Min
Max
Inches
Min
Max
4.32
1.14
1.27
0.76
0.38
14.60
10.03
2.41
4.95
5.97
2.41
13.08
0.170
0.045
0.0,0
0.030
O.ub
0.575
0.39'
0.09,
0.195
0.23'
O.Oy:
0.'1'
3.68
2.54
4.70
1.40
1.65
1.02
0.76
15.49
10.41
2.67
5.33
6.73
2-:79
14.22
3:81
3.94
3.05
0.145
0.100
0.185
0.055
0.06'
0.040
0.U30
0.610
0.410
0.10'
0.210
0.265
0.110
0.560
0.150
0.155
0.120
OETAILA-A
• TO-247AD
Dim
A
Al
A2
0
bl
b2
c
])
01
D2
D3
_I:>
"
L
1.1
lOP
(06/10/94)
Millimeters
Min
Max
4.70
1.,0
2.20
1.6,
1.02
2.87
0.40
20.80
4.j;!
5.30
2.50
2.59
2.13
1.40
3.13
0.79
21.40
5.49
6.48
6.20
16.:[6
5.84
5.38
b.4Y
5.46 Bse
19.81 1 20.32
-I 430
3.56
3.66
-
Inches
Min
Max
0.185
0.059
0.087
0.06,
0.040
0.113
0.016
-0;819
0.140
U.230
0.212
0.610
0.21~
0.209
0.098
0.102
0.084
0.055
0.123
0.031
0.845
0.210
0.255
0.244
0.640
Bse
0.780
1 0.800
1 0.177
0.140
0.144
-
7-13
TEMIC
Package Information
Siliconix
• TO-250 (4-Pin FETDIP)
Dim
Al
D
~
c
0
E
El
e
c,
L
Ll
MOlimeters
Min
Max
Inches
Min
Mali
0.86
0.)1
0.89
u.3J
4.93
5.97
7.62
2.29
7.62
3.18
0.89
0.034
0.020
0.u3)
0.013
0.194
0.235
0.300
0.090
0.300
0.125
0.Q35
1.12
0.61
1.14
0.43
5.03
6.48
8.26
2.79
7R7
4.06
1.40
0.044
0.lTl4
0.0",_
0.017
0.198
0.255
0.325
0.110
0.310
0.160
0.055
• TO-251 and TO-252
Millimeters
~~~
Dim
A
Al
A2
b
bl
b2
Io
~/I,: : rt,Y'1#I
I I
I
TO-2SI
L
ij
c
Cl
D
01
E
e
el
H
HI
L
Ll
Lz
L3
~~~
L!
Min
Max
2.21
2.39
0.89
1.14
0.03
0.23
0.71
0.89
0.76
1.14
5.44
5.23
0.46
0.58
0.46
0.58
5.97
6.22
4.49
5.00
6.48
6.73
2.29BSC
4.57BSC
4.32
9.65
10.41
8.89
9.53
0.64
1.02
0.89
1.27
1.02
1.52
0.51
-
Inches
Max
Min
0.087
0.094
0.035
0.045
0.001
0.09
0.028
0.035
0.030
0.045
0.206
0.215
0.Q18
0.023
0.Q18
0.023
0.235
0.245
0.177
0.197
0.255
0.265
0.090BSC
0.180BSC
0.170
0.380
0.410
0.355
0.375
0.025
0.040
0.035
0.050
0.040
0.060
0.020
Io
Iqf;=;:f;:::::;~!l
b~~el~L
7-14
TO-2S2
L3
bl
(06/10/94)
TEMIC
Package Information
Siliconix
• TO-254AA
I---E
~I_-;-+::r- 0P
II
11
f------'------."
e
iJ
Millimeters
Min I Max
Inches
Min I Max
0P
6.32 I 6.60
1.02 I 1.27
3.81 Bse
0.89
1.14
20.32
20.07
13.59
13.84
16.89
17.40
13.59
13.84
3.81 Bse
30.35 I 31.40
3.78
3.53 I
0.249 I 0.260
0.040 I 0.050
0.150Bse
0.035
0.045
0.790
0.800
0.535
0.545
0.685
0.665
0.535
0.545
0.150Bse
1.195 I 1.235
0.139 I 0.149
Dim
Millimeters
Min I Max
Inches
Min I Max
Dim
A
Al
A2
0b
D
Dl
D2
E
e
L
• TO-257AB
-~~--0P
+-11
A
Al
A2
0b
2 3
I
'
-4D4
,!!~
e
(06/10/94)
D
Dl
D2
D3
D4
E
e
L
0P
-
I 5.33
0.64 I 0.89
2.79Bse
0.89
1.14
16.26
17.02
10.41
10.92
16.26
17.02
0.51
13.20
13.72
10.92
10.41
2.54BSC
12.70 I 14.73
3.81
3.56
-
-
I 0.210
0.025 I 0.Q35
O.HOBse
0.035
0.045
0.645
0.665
0.410
0.430
0.645
0.665
0.020
0.520
0.540
0.410
0.430
0.100BSe
0.500 I 0.580
0.140 I 0.150
-
7-15
TEMIC
Package Information
Siliconix
• TO-263 (D2PAK)
Millimeters
Max
Min
Inches
Min
Max
4.32
0.71
1.27
0.33
1.14
8.64
0.170
0.028
0.050
0.013
0.045
0.340
~
4.70
1.02
1.65
0.51
1.40
9.65
5.72
10.03
10.41
7.87
8.64
9.02
9.53
2.54BSC
14.61 .1 15.88
1.40
1.78
1.27
Dim
MlIlimeters
Min
Max
Inches*
Min
Max
Dim
A
b
bl
C
Cl
D
D,
E
El
E2
e
L
Ll
-
I
0.185
0.040
0.065
0.020
0.055
0.380
0.225
0.395
0.410
0.310
0.340
0.355
0.375
0.100BSC
0.575
0.625
I 0.055
0.050
0.070
-
I
• TQFP, 64-Pin
A
0.977
1.177
0.039
Al
b
0.04
0.16
0.002
0.006
0.14
0.26
0.006
0.010
0.046
C
0.117
0.177
0.005
0.007
D
Dl
e
L
9.90
10.10
0.390
0.398
11.7
12.3
0.60
0.461
0.484
0.40
0.016
0.024
-
10.80
-
0.425
Ll
10.80
11.20
0.425
0.441
~
0.30
0.70
0.012
0.028
O·
4·
o·
4·
e
"For Reference Only
7-16
(06/10/94)
TJEMIC
Package Information
Siliconix
III TSSOp, 8-Pin
1
r
I Millimeters
Dim r-Min I Max
A
E
~J
1.20
0.15
0.25
1.05
0.30
J-
Inches
Mini Max--J
0.041
0.002
0.047_
o.oo~
3.10
4.50
6.60
0.041
012
0.010 I O. _
0.005
_
0.114 I 0.1210170 I 0.1~
0.244 J. ~~
L
0.65 BSC
0.50 I 0.70
0.025 BSC=0.020 I 0.028
0.039
Ll
R
0.09
b
c
E
I
0.127
t-O
e
(06/10/94)
1.05
0.05
I
2.90
4.30
6.20
II
1.0
0.004
0.004
I
I
_
7-17
TEMIC
Package Information
Siliconix
• Thpe and Reel Options
SECTIONA-A
Quantity Per Reel
DPAK
D2pAK
2000
800
2500
2500
2500
1500
SO-8
SO-14
SO-16
SO-24 [WB
--l I--w
SO-14
SO·8
Dim
A
B
C
D
E
F
G
H
0J
K
0K
L
ElL
M
0N
0P
T
V
W
7-18
SO·16
Millimeters
Max
Min
Jncltes
Min
Max
Millimeters
Min
Max
Incbes
Min
Max
Millimeters
Min
Max
Inches
Min
Max
11.9
1.65
5.10
6.30
7.90
3.90
5.10
0.25
1.50
1.90
1.50
328
0.469
0.065
0.201
0.248
0.311
0.154
0.200
0.010
0.059
0.075
0.059
12.91
15.9
1.65
9.05
6.55
7.90
3.90
9.05
0.25
1.50
1.90
1.40
328
0626
0.065
0.356
0.258
0.311
0.154
0.356
0.010
0.060
0.075
0.055
12.91
15.9
1.65
10.35
6.55
7.90
3.90
10.35
0.25
1.50
1.90
1.40
328
0.626
0.065
0.407
0.258
0.311
0.154
0.407
0.010
0.060
0.075
0.055
12.91
1.50
12.8
21.5
1.00
53.0
12.4
12.1
1.85
5.30
6.50
8.60
4.10
5.30
0.35
1.60
2.30
1.70
332
3'
2.50
13.2
22.5
2.00
54.0
14.4
0.059
0.504
0.847
0.039
2.087
0.488
0.476
0.073
0.209
0.256
0.339
0.161
0.209
0.014
0.063
0.091
0.067
13.07
3'
0.098
0.520
0.886
0.078
2.126
2.667
1.50
12.8
21.5
1.00
53.0
16.4
16.1
1.85
9.25
6.75
8.10
4.10
9.25
0.35
1.60
2.30
1.60
332
3'
2.50
13.2
22.5
2.00
54.0
18.4
0.059
0.054
0.847
0.039
2.087
0.646
0.634
0.073
0.364
0.266
0.319
0.161
0.364
0.014
0.063
0.091
0.063
13.07
3'
0.098
0.520
0.886
0.078
2.126
0.724
1.50
12.8
21.5
1.00
53.0
16.4
16.1
1.85
10.55
6.75
8.10
4.10
10.55
0.35
1.60
2.30
1.60
332
3'
250
13.2
22.5
2.00
54.0
18.4
0.059
0.054
0.847
0.039
2.087
0.646
0.634
0.073
0.415
0.266
0.319
0.161
0.415
0.014
0.063
0.091
0.063
13.07
3'
0.098
0.520
0.886
0.078
2.126
0.724
(06/10/94)
TEMIC
Package Information
Siliconix
• Jape and Reel Options (Cont'd)
SO-24 (Widebody)
Dim
A
B
C
D
E
F
G
H
11'1
K
II'K
L
8L
M
II'N
II'P
T
V
W
(06/l0I94)
Inches
Min
Max
Millimeters
Min
Max
10.3
11.2
0.406
0.441
1.65
15.9
10.8
11.9
3.90
15.9
0.25
1.50
2.8
1.50
328
1.85
16.1
11.0
12.1
4.10
16.1
035
1.60
3.2
1.70
332
3'
2.50
13.2
22.5
2.00
54.0
26.4
0.065
0.626
00425
00469
0.154
0.626
0.010
0.059
0.110
0.059
12.91
0.073
0.634
0.433
00476
0.161
0.634
0.014
0.063
0.126
0.067
13.07
3'
0.098
0.520
0.886
0.078
2.126
1.039
15.9
1.65
6.80
lOA
11.9
3.90
6.80
0.25
1.50
2.50
1.50
328
1.50
12.8
21.5
1.00
53.0
2404
0.059
0.504
0.847
0.039
2.087
0.961
J)2pAI{
DPAI{
Millimeters
Min
Max
1.50
128
21.5
1.00
53.0
16.4
Inches
Max
Min
Millimeters
Min
Max
16.1
0626
0.634
29.7
24.3
1.169
0.957
1.85
7.00
10.6
12.1
4.10
7.00
0.35
1.60
2.70
1.70
332
3'
2.50
13.2
22.5
2.00
54.0
18.4
0.065
0.268
0.409
00469
0.154
0.268
0.010
0.059
0.098
0.059
12.91
0.073
0.276
00417
0.476
0.161
0.276
0.014
0.063
0.1063
0.067
1307
3'
0.098
0.520
0.886
0.078
2.126
0.724
1.65
15.7
10.5
15.9
3.90
15.7
0.25
1.50
4.80
1.50
328
1.85
15.9
10.7
16.1
4.10
15.9
0.35
1.60
500
2.00
332
3'
2.50
13.2
22.5
2.00
54.0
26.4
0.065
0.618
0.413
0.626
0.154
0.618
0.010
0.059
0.189
0.059
12.91
0.073
0.626
0.422
0.634
0.161
0626
0.014
0.063
0.197
0.067
13.07
3'
0.098
0.520
0.886
0.078
2.126
1.039
0.059
0.504
0.847
0.039
2.087
0.646
1.50
12.8
21.5
1.00
53.0
2404
Inches
Min
Max
0.059
0.504
0.847
0.039
2.087
0.961
7-19
TEMIC
Military Information
Siliconix
Process Opiton Flows for Discrete Devices
Test and Condition
JANTXV
JANTX
Build and test in
Qual\tled 19500
Facility
Build Ottshore Test in
QuaJllled 19500
Facliity
-2&
Methods Per
MIL·S·19500
U.S. Build Only if
Specified"
Description
PowerMOS
ExtendedID·Rd
-1&
Build and test in
QuaJlIIed 19500
Facility
Ttst
IndnstriaJ Standard
1faceabilityto W/L
With Exception
X
N/A
N/A
N/A
SEM
2077
X
N/A
N/A
N/A
Internal VISUal
2069
Inhouse Spec
Inhouse Spec
Condition A
CondibonB
Inhouse Spec
ConditionB
Inhouse Spec
IND
Die Shear'
N/A
X
' ... /1 ..
?Jl A
N/A
Cert!DataC
2037
X
N/A
N/A
N/A
Stab Bake
1032
X
X
X
N/A
Thmp Cycle
1051
X
X
X
N/A
Centrifuge
(if reg.)
2006
X
X
X
N/A
PIND
2052·A
X
N/A
N/A
N/A
FineLeaJOpajakatu 5
FIN-00581 Helsinki
TEL: ~358~ 0-739100
FAX: 358 0-7015683
8-6
Farnell Electronic Services
16 Avenue des Andes
BP16
91941 Les Ulis Cedex A
TEL: ~3~ 1 64-46-02-00
1LX: 0351
FAX: (33) 1 64-46-95-95
SCAIB
80 Rue d' Arcueil
94523 Rungis Cedex
TEL: &~ 1 46-87-23-13
1LX:
67F
FAX: (33) 1 45-60-55-49
TEMIC
3. Avenue du Centre
B.P'309
78054 Saint-Quentin-en-Yvelines
TEL: ~33l1 30-60-70-00
FAX: 33 1 30-64-06-93
Germany
Eurodis Enalechnik Electronics
Sickingenstrasse 1 - 10SS3 Berlin
TEL: ~ 49130 3441043
FAX: 49 30 3449544
Eurodis Enatcchnik Electronics
Rbeinstrasse 24 - 64283 Darmsladt
TEL: ~ 49~ 6151 17410
FAX: 49 6151174111
Eurodis Enatechnik Electronics
St. Petersburger Str. 15 - 01069
Dresden
TEL: ~ 491351 4962400
FAX: 49 351 4962401
EurodlS Enatecbnik Electronics
Hddesheimer Str. 31 - 30169
Hannover
TEL: ~49~ 511816038
FAX: 49 511 816048
Eurodis Enatechnik Electronics
Henschelring 5 - 85551 Kircbheim
TEL: ~ 49~ 89 9049820
FAX: 49 89 90498240
Eurodis Enatechnik Electronics
Max-Stromeier Str. 1 - 78467
Konstanz
TEL: ~49~ 753161048
FAX: 49 7531 67260
Eurodis Enatechmk Electronics
Bueber Str. 100 - 90408 Numberg
TEL: ~ 49~ 911 34750
FAX: 49 911 347530
Eurodis Enatechnik Electronics
Scbillerstrasse 14 - 25451 Quickborn
TEL: 149~ 4106 612277
FAX: 49 4106612281
EurodlS Enatechnik Electronics
Breitwiesenstrasse 2S
70565 Stuttgart
TEL: ~ 49~ 711 7889770
FAX: 49 711 7889744
CEDDitronic
Bernbacherstrasse 9
90768 Filrth
TEL: ~49l911 752216
FAX: 49 911 7520064
CEDDitronic
Laatzener Str. 19
TEL: ~49~ 0511 87640
FAX: 49 0511 8764160
CED Dilronic
Benzstrasse 1 B
85551 Kirchbeim
TEL089 9038551
FAX: 49j 089 9030944
t9)
CED Dilronic
Julius-HOlder SIr. 42
70597 Slullgarl
TEL: 149~ 0711 720010
FAX: 49 0711 7289780
EBV
Beb_imst.3 D-I0585 Berlin
TEL: ~ 49l 030 3421041
FAX: 49 0303419003
EBV Elektronik
In der Meinewortb 21 - 30938
Burgwedel
TEL: ~ 49l 5139 80870
FAX: 49 51395199
EBV Elektronik
Schenckstrasse 99 - 60489 Frankfurt
99
TEL: ~ 49l 069 785037
FAX: 49 069 7894458
EBV Elektronik
Hans Pinsel Str. 4 - 88540 Haar
D-8013Haar
TEL: ~ 49~ 089 460960
FAX: 49 089 464488
EBV Elektronik
Mallbias-aaudius Str. 2a
41564 Kaarst
TEL: ~49l 02131 96770
FAX: 49 02131 967730
EBV Elektronik
BOblinger Str. 13 - 71229 Leonberg
TEL: ~ 49~ 7152 300090
FAX: 49 7152 75958
Farnell Electronic Services
Bahnlofstrasse 44 - 71696
Moghngen
TEL: ~49~ 07141 4870
FAX: 49 07141 487210
Ing. Buro Rainer Konig
Konigsberger Str. 16A - 12207
Berlin
TEL: ~ 49~ 30 7689090
FAX: 49 30 7738363
Spoerle Electronic
Kaekertstrasse 10
52072 Aachen
TEL: ~49~ 241889690
FAX: 49 241 8896923
Spoerle Electronic
Rudower Str. 27-29 - 12351 Berlin
TEL: ~4~ 30 606011
1LX: 8 029
FAX: (49) 30 6014057
Spoerle Electronic
Hopfigbeimer Slrasse 5 - 74321
Hletigheim-Bi!J~illg~l1
TEL: ~49~ 7142 70030
FAX: 40 7142 700360
Spoerle Electronic
Hildebrandstrasse 11 - 44319
Dortmund
TEL: ~~ 231 218010
1LX:
555
FAX: (49) 2312180167
Spoerle Electronic
1m Gerlertb 11_ - 63303 Dreieicb
TEL: ~4~ 6103 3040
1LX: 1 983
FAX: (49) 6103 304201
~oerle
Electronic
80s-Bunte Str. 2 - 79108 Frelburg
TEL: ~~ 761 510450
1LX:
1994
FAX: (49)761 502233
Spoerle Electronic
Rodeweg 18 - 37081 Gollingen
TEL: ~4~ 551 9040
TLX: 633
FAX: (49) 551 90446/48
Spoerle Eleclronic
Bereicb Hamburg
Winsbergring 42
22525 Hamburg
TEL: &424085313450
1LX: 1 4536
FAX: (49) 40 85313491
TEMIC
Siliconix
European Sales/Representatives/Distributors (Cont'd)
~mUlD!
(Coni'd)
Spoerle ElectroDlC
Roscherstrass.31 - 04105 Leipzig
TEL: ~ 49~ 341 5647201
FAX: 49 341 5852087
Spoerle Electronic
Rathsbergstrasse 17
90411 Nurnberg
TEL: ~ 491911 521560
FAX: 40 91J 5215635
Spoede Electronic
Fahringer Allee 17 - 85774
Unterfohnng
TEL: ~ 49~ 89 959990
FAX: 49 899509999/97
~1,,:~,r.~oflOri
E5
20094 Assago Mdano
TEL: ~39l2 824 701
FAX: 39 2824 70278
Lasl Elettronica
DIY. Dell. Sdvcstar Ltd. Spa
V. Le Fulvio Thstl 280
20126 Mdano
TEL: ~3Ql2 661 431
FAX: 39 2661 01385
TEMIC
Via Stephenson 94
20157 Mdano
TEL: ~39~ 2 33 2121
FAX: 39 233212201
ill:lli
1htechLtd.
4 Hayetzira St.
POB2436
Ra'Anana43100
TEL: f972l9 917277
FAX: 972 9 982616
Imm!!
MEMEC Ireland Ltd.
Block H - Lock Quay
Clare Street - LimerICk
Rep of Ireland
TEL: ~353~ 61 411 842
FAX: 353 61 411 888
EBV
Planetenbaan 2
3606 AK Maarssenbroek
TEL: (31) 03465-62353
FAX: (,iI03465-64277
Diode Components BY
Postbus 7139
5605 JC Eindhoven
De Run 1120
5503 LA Veldhoven
TEL: ~31l 040-545430
FAX: 31 040-535540
Diode Composants BV
Coltbaan 17
3439 NG Nieuwege
TEL: ~31~ 3402 91234
FAX: 31 3402 35924
AvnetDeMico
DIY. Della Avoet Adelsy Sri
V. Le Vittano Veneto 8
20060 Cmisello B. Milano
TEL: ~39l2 953 43600
FAX: 39 29522227
Camel Electronica Sri
Via Degli Artigianelli 6
20159Mdan
TEL: ~39l2 668 02 788
FAX: 39 266802 919
EBV ElektronIk Sri
Via C. Frova 34
20092 CinlSello B. Milano
TEL: 13912 660 17111
FAX: 39 2 660 17020
TEMIC
Principe de Vergara, 112
Apartad0235
28002 Madnd
TEL: ~34l1 5627600
FAX: 34 1 56275 14
Farnell Electronic Services
Ankdammsgatan 32
S-171 26 Solna
TEL: ~ 4618 835150
FAX: 46 8271807
TEMIC Nordic NS
KavallerIViigen 24, Rissne
P.O. Box 2042
17202 Sundbyberg, Sweden
TEL: ~ 4618 733-0090
FAX: 46 8 733-0558
TH's Elektronik AB
Arrendevagen 36
P.O. Box 3027
16303 Spanga
TEL: ~ 4618 36 2970
FAX: 46 8 761 3065
Norway
Switzerland
Farnell Electronic SeMCes
Nedre Kalbakkvei 88
N-I081 Oslo 10
TEL: ~ 47122 321270
FAX: 47 22 325120
AbaleeAG.
Grabenstrasse 9
8952 Sehlieren
TEL: 1-730-0455
FAX: 1-730-9801
ThhomcAlS
ll!!!x
RedlS Logar, S A
28002 Madrid
TEL: ~34l1 413 9111
FAX: 34 1 416 1971
fumIm
Netherlands
TEMIC TELEFUNKEN
microelectronIc
Theresienstrasse 2
0-74072 Heilbronn
Postfach 35 35
0-74025 Hedbronn
TEL: ~ 49~ 07131 67-0
FAX: 49 0713167-2100
EBV Elektromk Vertnebs
28049 Madrid
TEL: ~34l1 358 8608
FAX: 34 1 358 8560
P.O. Box 140 - Kalbakken
Kakkelovnskroken 1
N-0902 Oslo 9
TEL: ~47l22 161610
FAX: 47 22257317
EBV ElektroDlk
Vorstadstr.37
8953 DletIkon
TEL: 1-7401090
FAX: 1-7415110
~
Fabrimex DistrIbution AG
Em Unternehmen der Spoede
Electronic
Cherstrasse 4
81520pfIkon-Glattbrugg
TEL: ~ 41l1-874 6262
FAX: 41 1-8746200
RedisLogar
Rua Bernardo Luna
Nr.27-1¢Izda
1200 Lisbon
TEL: ~351l11-520101
FAX: 351 11-520004
.5niD.
ADM ElectroDlea S A
28009 Madnd
TEL: ~34l1 5304121
FAX: 34 1 5300164
Fabrimex Distribution AG
Ein Untrtnehmen dec
Spoede ElectroniC
8, rue des Pecheurs
1400 Yverdon-Ies-Bains
TEL: ~41l24-219222
FAX: 41 24-218141
1l!rku
ERDA Elektromk AS.
San Ve TIC AS.
Keskin Kalem Sokak 15
80300 Esentepi
Istanbul
TEL: ~90l1144-21-68
FAX: 90 127 50540
United Kingdom
Abacus Electronics Ltd.
Abacus House
Bone Lane
Newbury, Berks RG14 5SF
TEL: (4~ 0 635-36 222
1LX: S4589
FAX: (44) 0635-38670
Abacus ElectrOnICs Limited
Abacus House
Bone Lane
Newbury, Berks RG14 5SF
TEL: ~ 44l 0 635-36222
FAX: 44 0 635-38670
Abercorn Electronics Ltd.
Pardovan
PhilIp, LmIithgow EH49 6QZ
TEL: ~44) 506 834222
1LX: 7994
FAX: (44) 506 834 554
BCD Microelectronics Ltd
3 Station Road
Swaffbam Bulbeck,
Cambridge CBS ONB
TEL: ~ 44l 0223 812598
FAX: 44 0223812686
Future Electronics
Poyle Road - Colnbrook
Berkshire SL3 OEZ
TEL: ~ 44l 0753 687 000
FAX: 44 0753689 100
HB Electronics Ltd.
Lever Street - Bolton
Lancs BL3 6BI
TEL: ~4~ 204255 44
1LX: 378
FAX: (44) 204 384911
Macro-Marketmg Ltd.
Burnham Lane
Slough, Berkshire SLl 6LN
TEL: ~4~ 0628 604422
1LX: 4 945
FAX: (44) 0628 666873
Mlcromark
159 Boyn Valley Road
Maidenhead
Beushire SL6 4DT
TEL: ~ 44l 0628 76176
FAX: 44 0628 783799
TEMICUKLtd.
~t:litead Road
III
III
CJ
e0
Berkshire RG12 1LX
TEL: ~ 441344 485757
FAX: 44 344 427371
-=
rI.I
III
C"I.l
Asia Pacific and Rest of the World
t\l:wI!i!!B.
~
l!rm!.
YEL S.R.L.
Virrey Cevallos 143
1077 Buenos Airl!s
TEL: ~54) 140-1025, (54) 1
45-714 ,
(5~ 1 45-7163
FAX: f54) 1 40-1533, (54) 1
45-255
IRH Components
1-5 Carter Street
Lidcombe NWS 2141
Australia
TEL: ~61l2-364-1766
FAX: 61 2-647-1545 (no charge)
Inlectra
2629 Thnnmal Blvd.
Mt. View, CA 94043
TEL: ~41~ 967-8818
TLX: 45 45
FAX: (415) 967-8836
UNIAO DigItal
R. Georgia, 69
CEP 04559-010
Sao Paulo SP Brazd
TEL: ~55l11 533-0967
TEL: 55 11 241-8052
FAX: 55 11 533-6780
8-7
TEMIC
Siliconix
Asia Pacific and Rest of the World (Cont'd)
.lI!mJ:.K!mg
TEMIC Hong Kong Limited
Suite 1701, World Finance Centre
South Thwer, Harbour City
17 Canton Road, Dimshatsui
Kowloon
TEL: ~852l3789 789
FAX: 852 3755733
IwIiI.
Amspee ~S) Pte Ltd
213 Hen erson Road
#01-07 Henderson Industrial Park
Singapore 0315
TEL: ~65l271oo16
FAX: 65 2714112
mue Star Ltd.
Sabas 414/2 Veer
Savarkar Marg
Prabhadevi, Bombay 400025
TEL: f91l224306155
FAX: 91 224 307078
lHlIrl
1litech
:~r.t~~eir~ ~~-:
2436
MANANA 43100
TEL: ~9nl9 917277
FAX: 9n 9 982616
8-8
.Im!m
MmJm
Ryoden ltadin$ Co., Ltd.
3-15-15 Higashl-lkebukuro
Thshima-ku, Thkyo 170
TEL: ~81l3-5396-6233
FAX: 81 3-5396-6443
Scan Components (M) Sdn. Bhd.
761-B, Jalan Sultan AZlan Shah
11900 Sungai Nibong
Penang
TEL: f6Ol4-835136
FAX: 60 4-836320
TEMlC Japan K.K.
ROpcongi FIrst Bldg. 17F
1-9- Roppongi
Minato-Ko, Thkyo 106
TEL: ~81l3-5562-3321
FAX: 81 3-5562-3316
Thko,Inc.
1-17 Higashl-Yukigaya 2-Chome
Ohta-ku, Thkyo 145
TEL: ~81l3-3n7-1166
FAX: 81 3-3n7-1179
TOMEN Electronics Corp.
1-1 Uchisaiwaicho 2 Chome
Chl}'Oda-Ku, Thkyo 100
TEL Thkyo: ~81l3-3506-3690
FAX Thkyo: 81 3-3506-3497
KmA
Changnam Electronics Ltd.
Rm. 903, Hosung Bldg.
#44-22, Yoido-Dong
Youngdeungpo-Ku
Seoul
'
TEL: f82l2-7820412
FAX: 82 2-7853643
Mm&!l
TEMlC Mexican.
c/o AEG Mexican. S.A. de C.V.
Paseo De La Reforma
35-20
Col Jabacaler.
06030DF.
TEL: f52l5-546-92-76
FAX: 52 5-566-08-400
Arlington (76006)
Ion Associates Inc.
2221 E. Lamar, Ste. 250
TEL: 181 ~ 695.,'l000
FAX: 81 695-8010
Puet1oRico
MEC/Caribe
P.O. Box 5038
Coguas 00726
TEL: f809l746-9897
FAX: 809 746-9441
~
TEMIC
AEGBuilding
25 Thmpines Street 92, #02-00
1852
TEL: ~l788-6668
FAX: 65 788-3383
Sales Ii : (65) 788-0031
QuadRep Marketing (S) Pte. Ltd
1 Marine Parade Centnil
#12-05 Parkway Builders' Centre
1544
TEL: ~65l3461933
FAX: 65 3461911
Scan 1.l:chn~ (~ Pte Ltd
SO KaIlang
ru 04-01/03
KaIlang Basin Industrial Estate
1233
TEL: f65l2942112
FAX: 65 2961685
South Africa
Electrolinko&P1Y) Ltd.
P.O. Box 1 0
Copetown
8000
Republic of South Afnca
TEL: 1271215350
FAX: 27 4196256
Taiwan
TEMIC
6/F Room B, No. 297, Sec 2
Ho-Pin East Road
Thipei City, R.O.C.
TEL: 1886l2755-6108
FAX: 886 2755-4777
Dyuarnar Thiwan Co. Ltd.
13F No. 186, Sec. 4
Nanking East Road
Thir,i 10570, R.O.C.
TE : ~886l2 5775670
FAX: 886 2 5775867
IiIlIillIIIll
See Scan 1.l:chnology, Singapore
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:06:29 16:25:38-08:00 Modify Date : 2017:06:29 16:59:30-07:00 Metadata Date : 2017:06:29 16:59:30-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:3a636238-4b9b-a64b-8939-e2efba955643 Instance ID : uuid:e14d70ad-8735-fa41-847a-2670ce6f249e Page Layout : SinglePage Page Mode : UseNone Page Count : 562EXIF Metadata provided by EXIF.tools