1994_TI486SXLC_and_TI486SXL_Microprocessors_Reference_Guide 1994 TI486SXLC And TI486SXL Microprocessors Reference Guide
User Manual: 1994_TI486SXLC_and_TI486SXL_Microprocessors_Reference_Guide
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~TEXAS
.
INSTRUMENTS
TI486SXLC and TI486SXL
,; : Microprocessors
.. -...
.
,.,,'
1994
PC Systems Logic Products
==~===============-~
TI486SXLC and TI486SXL
Microprocessors
Reference Guide
~TEXAS
INSTRUMENTS
Printed on Recycled Paper
Important Notice
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated
by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask
work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1994, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This manual describes the TI486SXL(C) microprocessor product family. Each
chapter except for chapters 3 and 4 cover all versions of the microprocessors.
both the TI486SXLC and the T1486SXL. Chapter 3 explicitly covers the
TI486SXLC series and chapter 4 explicitly covers the TI486SXL series. This
document contains the following chapters:
Chapter 1
Product Overview
Chapter 1 introduces the features of the TI486SXLC and TI486SXL microprocessor series and defines the differences between them. Each series offers
a 3.3-volt version (TI486SXLC-V and TI486SXL-V) for battery-powered
applications. A functional block diagram, logic symbol, and I/O signal identifications are provided for each of the two series of microprocessors. Additional
material describes selected system architectures such as the execution
pipeline, the on-chip cache memory, and the power-management techniques.
The system-management mode (SMM) permits the TI486SXL(C) family of microprocessors to respond to and service interrupts with a higher priority than
standard 486 processors.
Chapter 2
Programming Interface
Chapter 2 describes the internal operations of the TI486SXL(C) family of microprocessors mainly from an application programmer's point of view. Included in this chapter are descriptions of processor initialization, the register
sets, memory addressing, various types of interrupts, system-management
mode, and the shutdown and halt process. Overviews of real, virtual-8086,
and protected operating modes are also included.
Chapter 3
TI486SXLC Microprocessor Bus Interface
Chapter 3 provides a summary of the TI486SXLC series processor signals
and descriptions of all inputs/outputs, functional timing and bus operations (including pipelined and nonpipelined addressing), various interfaces, and power
management.
iii
About This Manual
Chapter 4
TI486SXL Microprocessor Bus Interface
Chapter 4 provides a summary of the TI486SXL series processor signals and
descriptions of all inputs/outputs, functional timing and bus operations (including pipelined and nonpipelined addressing), various interfaces, and power
management.
Chapter 5
Electrical Specifications
Chapter 5 provides electrical specifications for the TI486SXL(C) family, including specifications for the 3.3-volt versions. The specifications include electrical
connection requirements for all package pins, maximum ratings, recommended operating conditions, dc electrical characteristics, and ac characteristics.
Chapter 6
Mechanical Specifications
Chapter 6 provides mechanical specifications for the TI486SXL(C) family that
include pin assignments, package physical dimensions, and package thermal
characteristics.
Chapter 7
Instruction Set
Chapter 7 summarizes the instruction set for the TI486SXL(C) family and provides detailed information of the instruction encoding. The instruction set is the
same for all TI486SXL(C) microprocessors. Instructions are listed in an
instruction set summary table that provides information on the flags affected
and the instruction clock counts for each instruction.
Appendix A
SMM Programmer's Guide
Appendix A provides detailed information including examples pertinent to programming the TI486SXL(C) system management mode (SMM). Included are
system-management interrupt (SMI) examples, testing/debugging SMM
code, power management features, loading SMM programs, detection of CPU
type, presence of SMM-capable devices, creating macros, and altering SMM
code limits.
Appendix B BIOS Modifications Guide
Appendix B discusses some BIOS changes that may need to be considered
by the PC designer. The areas considered are power-on and hard reset, protected-mode to real-mode switching, and soft reset. Examples of assembler
code for turning the cache on and off are provided.
Appendix C Design Considerations and Cache Flush
Appendix C provides design considerations, address bit A20 masking, and
general cache invalidation procedures.
iv
About This Manual/Style and Symbol Conventions
Appendix D OEM Modifications for 168-Pin CPGA
Appendix 0 describes the potential modifications an OEM needs to implement
on an existing 486SXlDXlDX4 motherboard to take advantage of the
TI486SXL 168 pin CPGA. A system implementation is described for a 3.3-V
system that supports a 5-V ISA and a 3.3-V VL bus and another implementation for a mixed 3.3-V/5-V system that supports a 5-V ISA and a 5-V VL bus.
Appendix E
Thermal Management in Microprocessor-Based Systems
Appendix E provides the reader with basic thermal concepts and the relationship between thermal measurements and the system. In addition, problems
associated with comparing thermal specifications from different manufacturers are discussed. Finally, corrective activity within JEDEC is detailed.
Appendix F
Ordering Information
Appendix F provides detailed ordering information showing what the components of the part number mean and a description of each microprocessor offered. Versions offered include 5-volt and 3.3-volt versions, each of which are
rated to operate at different speeds. The TI486SXLC series devices are packaged in the quad flat pack, and the TI486SXL series devices are packaged in
quad flat pack and ceramic PGA packages.
Appendix G Glossary
Appendix G contains explanations for the terms, abbreviations, and acronyms
used in this manual.
Style and Symbol Conventions
This document uses the following conventions.
o
Program code listings and program code examples are shown in a special typeface similar to a typewriter's.
Here is a sample assembler code program listing:
CLI
MOV
OR
o
EAX, CRO
; set bit 30, turn off cache
EAX, 40000000h ; for external cache coherency
In the instruction syntax descriptions, the instruction is in a bold typeface
and a description of the instruction is in italic typeface. Here is an example
of an instruction syntax and description:
RSM Resume from SMM Mode
o
Square brackets ( [ and] ) identify the location and sequence for specifying
register andlor memory options in the instruction opcode. Here's an example of an opcode that requires register and memory parameters:
Reference: Instruction ADD Integer Add (Register to Memory)
Opcode
= 0 [OOOw] [mod reg rim]
Read This First
v
Information About Cautions and Warnings / Trademarks
Information About Cautions and Warnings
This book may contain cautions and warnings.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Trademarks
AMD is a trademark of Advanced Micro Devices.
EPIC is a trademark of Texas Instruments Incorporated.
Intel is a trademark of Intel Corp.
vi
Contents
1
Product Overview ............................................................... 1-1
1.1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
1.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-4
1.3
TI486SXLC Series Overview .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-5
1.4
TI486SXL Series Overview .................................................. 1-9
1.5
Differences Between the TI486SXLC Series and TI486SXL Series ... . . . . . . . . . . .. 1-15
1.6
Differences Between the TI486SXL(C) Family and the TI486SLC/DLC Family ..... 1-16
1.7
Execution Pipeline ......................................................... 1-17
1.8
On-Chip Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-17
1.9
Clock-Doubled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-18
1.10 Power Management ....................................................... 1-18
1.10.1 System-Management Mode (SMM) ................................... 1-18
1.10.2 Suspend Mode and Static Operation .................................. 1-18
1.10.3 3.3-V Operation .................................................... 1-19
1.10.4 Mixed 3.3-V and 5-V Operation ....................................... 1-19
2
Programming Interface .......................................................... 2-1
2.1
Processor Initialization ...................................................... 2-2
2.2
Real Mode Versus Protected Mode ........................................... 2-5
2.3
Instruction-Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6
2.3.1
Lock Prefix ......................................................... 2-7
2.3.2 Register Sets ....................................................... 2-7
2.3.3 Address Spaces ..................................................... 2-8
2.4
Application Register Set .................................................... 2-10
2.4.1
General Purpose Registers .......................................... 2-11
2.4.2 Segment Registers and Selectors .................................... 2-12
2.4.3 Instruction Pointer Register .......................................... 2-14
2.4.4 Flag Word Register ........................... . . . . . . . . . . . . . . . . . . . . .. 2-14
2.5
System Register Set .................................................... :.. 2-16
2.5.1
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. 2-18
2.5.2 Descriptor-Registers and Descriptors ................................. 2-19
2.5.3 Task Register ...................................................... 2-23
2.5.4 Configuration Registers ............................................. 2-26
2.5.5 Debug Registers ................................................... 2-31
2.5.6 Test Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-33
2.6
Memory Address Space .................................................... 2-37
2.6.1
Offset Mechanism .................................................. 2-37
2.6.2 Real-Mode Memory Addressing ...................................... 2-38
2.6.3 Protected-Mode Memory Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-39
vii
Contents
2.7
2.8
2.9
2.10
2.11
3
viii
Interrupts and Exceptions .................................................. ,
2.7.1
Interrupts ..........................................................
2.7.2 Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.7.3 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.7.4 Interrupt and Exception Priorities .....................................
2.7.5 Exceptions in Real Mode ............................................
2.7.6 Error Codes .......................................................
System-Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.8.1
SMM Operations ...................................................
2.8.2 SMM Memory Space Header ........................................
2.8.3 SMM Instructions ..................................................
2.8.4 SMM Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.8.5 SMI Service Routine Execution ....................... " ..............
2.8.6 CPU States Related to SMM and Suspend Mode ...................... ,
Shutdown and Halt ........................................................
Protection ................................................................
2.10.1 Privilege Levels ....................................................
2.10.2 1/0 Privilege Levels .................................................
2.10.3 Privilege Level Transfers ............................................
2.10.4 Initialization and Transition to Protected Mode ..........................
Virtual-8086 Mode .........................................................
2.11.1 Memory Addressing ................................................
2.11 .2 Protection .........................................................
2.11.3 Interrupt Handling ..................................................
2.11.4 Entering and Leaving V86 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-43
2-43
2-44
2-45
2-46
2-47
2-48
2-49
2-50
2-51
2-52
2-54
2-54
2-55
2-57
2-57
2-58
2-58
2-58
2-59
2-60
2-60
2-60
2-60
2-61
TI486SXLC Microprocessor Bus Interface ......................................... 3-1
3.1
Input/Output Signals ........................................................ 3-2
3.1 .1
TI486SXLC Terminal Function Descriptions ............................. 3-4
3.1.2 Signal States During Reset and Hold Acknowledge ..................... 3-12
3.2
Bus-Cycle Definition ....................................................... 3-13
3.2.1
Clock Doubling Using Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-13
3.2.2 Power Management ................................................ 3-15
3.3
Reset Timing and Internal Clock Synchronization .............................. 3-17
3.4
Bus Operation and Functional Timing ........................................ 3-19
3.4.1
Bus Cycles Using Nonpipelined Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-20
3.4.2 Bus Cycles Using Pipelined Addressing ............................... 3-24
3.4.3 Locked BusCydes ................................................. 3-31
3.4.4 Interrupt-Acknowledge Cycles ........................................ 3-31
3.4.5 Halt and Shutdown Cycles ........................................... 3-33
3.4.6 Internal Cache Interface ............................................. 3-36
3.4.7 Address Bit-20 Masking ............................................. 3-38
3.4.8 Hold-Acknowledge State ............................................ 3-39
3.4.9 Coprocessor Interface ............................................... 3-42
3.4.10 SMM Interface ................................... '.................. 3-43
3.4.11 Power Management ................................................ 3-45
3.4.12 Float.............................................................. 3-48
Contents
4
TI486SXL Microprocessor Bus Interface .......................................... 4-1
4.1
Input/Output Signals ........................................................ 4-2
4.1.1
TI486SXL Terminal Function Descriptions .............................. 4-4
4.1.2 Byte Enable Line Definitions ......................................... 4-13
4.1.3 Write Duplication as a Function of BE3# - BEO# . . . . . . . . . . . . . . . . . . . . . . .. 4-14
4.1.4 Generating A 1 - AO Using BE3# - BEO# .............................. 4-14
4.1.5 Signal States During Reset and Hold Acknowledge ..................... 4-14
4.2
Bus-Cycle Definition ....................................................... 4-16
4.2.1
Clock Doubling Using Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-16
4.2.2 Power Management ................................................ 4-18
4.3
Reset Timing and Internal Clock Synchronization .............................. 4-20
4.4
Bus Operation and Functional Timing ........................................ 4-22
4.4.1
Bus Cycles Using Nonpipelined Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-23
4.4.2 Bus Cycles Using Pipelined Addressing ............................... 4-27
4.4.3 Bus Cycles Using BS16# ............................................ 4-34
4.4.4 Locked Bus Cycles ............. ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-37
4.4.5 Interrupt-Acknowledge Cycles ........................................ 4-37
4.4.6 Halt and Shutdown Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-39
4.4.7 Internal Cache Interface ............................................. 4-42
4.4.8 Address Bit-20 Masking ............................................. 4-45
4.4.9 Hold Acknowledge State ............................................ 4-46
4.4.10 Coprocessor Interface ............................................... 4-49
4.4.11 SMM Interface ..................................................... 4-50
4.4.12 Power Management ................................................ 4-52
4.4.13 Float (144-Pin QFP and 168-Pin PGA Pinouts Only) .................... 4-55
5
Electrical Specifications ........................................................ 5-1
5.1
Electrical Connections ....................................-. . . . . . . . . . . . . . . . . .. 5-2
5.1.1
Power and Ground Connections and Decoupling ........................ 5-2
5.1.2 Pullup/Pulidown Resistors ............................................ 5-2
5.1.3 NC Designated Terminals. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
5.1.4 Unused Signal Input Terminals ........................................ 5-3
5.2
Absolute Maximum Ratings .................................................. 5-4
5.3
Recommended Operating Conditions ......................................... 5-5
5.3.1
3.3-Volt Microprocessors With 5-Volt Tolerant Inputs, Outputs, and I/Os .... 5-5
5.3.2 3.3-Volt Microprocessors ............................................. 5-6
5.3.3 5-Volt Microprocessors ............................................... 5-6
5.4
DC Electrical Characteristics ................................................. 5-7
5.4.1
3.3-Volt Microprocessors With 5-Volt Tolerant Inputs, Outputs, and I/Os .... 5-7
5.4.2 3.3-Volt Microprocessors ............................................. 5-9
5.4.3 5-Volt Microprocessors .............................................. 5-12
5.5
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-16
5.5.1
Measurement Points for AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-16
5.5.2 CLK2 Timing Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-19
5.5.3 AC Data Characteristics Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-19
5.5.4 RESET Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-29
5.5.5 TI486SXLC Switching Waveforms .................................... 5-29
5.5.6 TI486SXL Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-32
Table of Contents
ix
Contents
6
Mechanical Specifications ....................................................... 6-1
6.1
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-2
6.2
Package Dimensions ......... , ... " ..... " ..... '" ................ " ....... 6-13
6.3
Thermal Characteristics .................................................... 6-18
6.3.1
Airflow Measurement Setup ........................................ " 6-20
6.3.2 Thermal Parameter Definitions ....................................... 6-21
7
Instruction Set .................................................................. 7-1
7.1
General Instruction Format ................................................... 7-2
7.2
Instruction Fields ........................................................... 7-3
7.2.1
Prefixes ............................................................ 7-4
7.2.2 Opcode Field ....................................................... 7-5
7.2.3 w Field ............................................................. 7-5
7.2.4 d Field .................. '" " ........................ " ............ 7-6
7.2.5 reg Field ........................................................... 7-6
7.2.6 mod and rim Field ........ '" " ...... " . " ............. , ............. 7-7
7.2.7 mod and base Fields ........................... '" ..... " .. " ........ 7-9
7.2.8 ss Field ........................................................... 7-10
7.2.9 index Field ......................................................... 7-10
7.2.10 sreg2 Field ........................................................ 7-10
7.2.11 sreg3 Field ........................................................ 7-11
7.2.12 eee Field .......................................................... 7-11
7.3
Flags ................................................................... " 7-12
7.4
Clock-Count Summary ..................................................... 7-13
7.4.1
Assumptions ....................................................... 7-13
7.4.2 Abbreviations ...................................................... 7-13
7.5
Instruction Set ........................................................... " 7-13
A
SMM Programmer's Guide ....................................................... A-1
A.1
SMM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-2
A.1.1
Introduction ......................................................... A-2
A.1.2 SMM Implementation ................................................ A-2
A.2
TI486SXL(C) Microprocessor Power Management Features. " .. " .... '" .... , ... A-3
A.2.1
Reducing the Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-3
A.2.2 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-3
A.3
SMM Feature Comparison ................................................... A-4
SMM Hardware Considerations .................. " .......... " ............... A-5
A.4
A.4.1 SMM Pins .......................................................... A-5
A.4.2 SMI# Pin Timing ..................................................... A-5
A.4.3 Address Strobes .................................................... A-5
A.4.4 Chipset READY# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-6
A.5
SMM Software Considerations ............................................... A-7
A.5.1
Exiting the SMI Handler .............................................. A-9
A.5.2 Accessing Main Memory At the Same Address as SMM Code . . . . . . . . . . . .. A-9
A.5.3 Miscellaneous Execution Details ... " ......... " ...... " ............... A-9
A.6
Enabling SMM ............................................................ A-11
A.7
SMM Instruction Summary and Macros ....................................... A-12
A.8
SM I Handler Example ...................................... ;............... A-17
A.9
Loading SMM Memory With an SMM Program From Main Memory .............. A-22
A.10 Detection of a TI Microprocessor ............................................ A-26
A.11 Detection of SMM Capable Version .......................................... A-28
x
Contents
A.12 Format of Data Used by SVDC/RSOC Instructions .............................
A.13 Altering SMM Code Limits ..................................................
A.14 Testing/Debugging SMM Code ..............................................
A.14.1 Software Only Debugging ...........................................
A.14.2 Software Debugging Example ........................................
A.14.3 Clearing the VM Flag Bit .............................................
A-32
A-34
A-3S
A-3S
A-36
A-42
B
BIOS
B.1
B.2
B.3
B.4
B.S
Modifications Guide .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Differences Between the TI486SLC/OLC BIOS and the TI486SXL(C) BIOS ........
Power-Up and Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Protected-Mode to Real-Mode Switching ......................................
Soft Reset-( CONTROL)( ALTJ ( DELETE) • . • • • • • • • • • • • . • • • • • • • • • • • • • • • • • • • • • • . • • • • • • •
Turning the Internal Cache On and Off ........................................
B-1
B-2
B-3
B-3
B-4
B-4
C
Design Considerations and Cache Flush ..........................................
C.1
Design Considerations ......................................................
C.2 Address Bit A20 Masking ........................ , ................. , .........
C.3 General Cache Invalidation ..................................................
C.3.1 Systems With No Secondary Cache or With a Parallel Secondary Cache ...
C.3.2 Systems With a Serial Secondary Cache ..................... '..........
C-1
C-2
C-3
C-4
C-4
C-S
o
TI4B6SXL OEM Modifications for 16B-Pin CPGA ................................... 0-1
0.1
Boards Supporting TI486SXL and Intel ........................................ 0-2
Boards Supporting TI486SXL and a 4860X .................................... O-S
0.2
0.3
Boards Supporting TI486SXL and a 4860X4 ................................... 0-6
0.4 Boards Supporting the VL Bus ............................................... 0-7
0.4.1 Cache Snooping .................................................... 0-7
0.4.2 VL-Bus Clock ........... " " ........................................ 0-7
0.4.3 VL-Bus Slot 10 Settings .............................................. 0-8
O.S
Power Planes for 3.3-V and 3.3-V/S-V Systems Using TI486SXL or 4860X4 ....... 0-9
0.S.1 Power Planes for 3.3-V Systems ...................................... 0-9
0.S.2 Power Planes for Mixed 3.3-V/S-V Systems ............................ 0-10
0.6 Chipset Support ........................................................... 0-11
E
Thermal Management in Microprocessor-Based Systems .......................... E-1
E.1
Introduction ................................................................ E-2
E.1.1 Thermal Impedance ................................................. E-3
E.1.2 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. E-3
E.1.3 Junction Temperature ................................................ E-3
E.2
Modes,of Heat Transfer ..................................................... E-4
E.2.1 Integrated Circuit Thermal Resistance ................................ " E-S
E.2.2 PWB Conductivity ................................................... E-7
E.2.3 Proximity of Integrated Circuit on Board ................................ E-8
E.2.4 Airflow.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. E-8
E.3
Thermal Specifications of Integrated Circuits ................................... E-9
E.3.1 System Dependence of RSJA and RSCA ..... . . . . . . . . . . . . . . . . . . . . . . . . .. E-9
E.3.2 Measurement of TA " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. E-10
E.3.3 Definition of Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. E-10
E.4
TI Thermal Specification Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. E-11
E.S
Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. E-14
E.6
Current Trends and Theory of Correction ..................................... E-14
E.7
Conclusions ............................................................... E-1S
Table of Contents
' xi
Contents
F
Ordering Information ............................................................ F-1
F.1
Part Number Components ................................................... F-1
F.2
Part Numbers for Microprocessors Offered ..................................... F-2
G Glossary ........................................................................ G-1
xii
Figures
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
TI486SXLC Functional Block Diagram ........................................... 1-6
TI486SXLC Logic Symbol .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-7
TI486SXLC Input and Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-8
TI486SXL Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-10
TI486SXL Logic Symbol (132-Pin PGA Package) ................................ 1-11
TI486SXL Logic Symbol (144-Pin QFP and 168-Pin PGA Packages) .............. 1-12
TI486SXL Input and Output Signals for 132-Pin PGA Package ..................... 1-13
TI486SXL Input and Output Signals for 144-Pin QFP and 168-Pin PGA Package ..... 1-14
TI486SXLC Memory and I/O Address Spaces .................................... 2-8
TI486SXL Memory and I/O Address Spaces ..................................... , 2-8
Application Register Set ...................................................... 2-10
General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-11
Segment Selector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-12
EFLAGS Register .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-14
System Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-17
Control Registers ............................................................ 2-18
Descriptor-Table (System-Address) Registers .................................... 2-20
Application- and System-Segment Descriptors ................................... 2-21
Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-23
Task (System-Address) Register ............................................... 2-23
32-Bit Task-State Segment (TSS) Table .................... : . . . . . . . . . . . . . . . . . . .. 2-24
16-Bit Task-State Segment (TSS) Table ......................................... 2-25
TI486SXLC Address Region Registers (ARR1-ARR4) ............................ 2-29
TI486SXL Address Region Registers~(ARR1-ARR4) ............................. 2-30
TI486SXLC Debug Registers .................................................. 2-31
TI486SXL Debug Registers ................................................... 2-32
Test Registers ............................................................... 2-33
Offset Address Calculation .................................................... 2-37
Real-Mode Address Calculation. " ..... , ............................... , ....... 2-38
Protected-Mode Address Calculation ........................................... 2':39
Selector Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-40
Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-41
Directory- and Page-Table Entry (DTE and PTE) Format .......................... 2-41
Error-Code Format ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-48
TI486SXLC Memory and 110 Address Spaces ................................... 2-49
TI486SXL Memory and I/O Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-50
SMM Execution Flow Diagram ................................................. 2-51
SMM Memory Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-52
SMM and Suspended-Mode Flow Diagram ...................................... 2-56
Table of Contents
xiti
Figures
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
4-1
4-2
4-3
4-4
4-5
4-6
4...:.7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
xiv
TI486SXLC Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. 3-2
Internal Processor Clock Synchronization ....................................... 3-17
Bus Activity From RESET Until First Code Fetch ................................. 3-18
Fastest Nonpipelined Read Cycles ............................................. 3-20
Various Nonpipelined Bus Cycles (No Wait States) ............................... 3-21
Various Nonpipelined Bus Cycles With Different Numbers of Wait States ............ 3-22
Nonpipelined Bus States ...................................................... 3-23
Fastest Pipelined Read Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-25
Various Pipelined Cycles (One Wait State) ...................................... 3-27
Fastest Transition to Pipelined Address Following Idle Bus State ................... 3-28
Transitioning to Pipelined Address During Burst of Bus Cycles ..................... 3-29
Complete Bus States ......................................................... 3-30
Interrupt-Acknowledge Cycles ................................................. 3-32
Nonpipelined Halt Cycle ...................................................... 3-34
Pipelined Shutdown Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-35
Nonpipelined Cache Fills Using KEN# (With Different Numbers of Wait States) ....... 3-36
Pipelined Cache Fills Using KEN# (With Different Numbers of Wait States) .......... 3-37
Masking A20 Using A20M# During Burst of Bus Cycles ........................... 3-38
Requesting Hold From Bus-Idle State ........................................... 3-40
Requesting Hold From Active Nonpipelined Bus .................................. 3-41
Requesting Hold from Active Pipelined Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-42
SMI# Timing ................................................................. 3-43
I/O Trap Timing .............................................................. 3-44
SUSP#-Initiated Suspend Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-45
HALT-Initiated Suspend Mode ................................................. 3-46
Stopping CLK2 During Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-47
Entering and Exiting Float ..................................................... 3-48
TI486SXL Functional Signal Groupings .......................................... 4-2
Internal Processor Clock Synchronization ....................................... 4-20
Bus Activity From RESET Until First Code Fetch ................................. 4-21
Fastest Nonpipelined Read Cycles ............................................. 4-23
Various Nonpipelined Bus Cycles (No Wait States) ............................... 4-24
Various Nonpipelined Bus Cycles With Different Numbers of Wait States ............ 4-25
Nonpipelined Bus States ...................................................... 4-26
Fastest Pipelined Read Cycles ................................................. 4-28
Various Pipelined Cycles (One Wait State) ...................................... 4-30
Fastest Transition to Pipelined Address Following Idle Bus State ................... 4-31
Transitioning to Pipelined Address During Burst of Bus Cycles ..................... 4-32
Complete Bus States .......................................................... 4-33
Nonpipelined Bus Cycles Using 8S16# ......................................... 4-35
Pipeliningand BS16# ......................................................... 4-36
Interrupt-Acknowledge Cycles ................................................. 4-38
Nonpipelined Halt Cycle ...................................................... 4-40
Pipelined Shutdown Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-41
Nonpipelined Cache Fills Using KEN# .......................................... 4-42
Nonpipelined Cache Fills Using KEN# and BS16# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-43
Pipelined Cache Fills Using KEN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-44
Masking A20 Using A20M# During Burst of Bus Cycles ........................... 4-45
Requesting Hold From Bus-Idle State ........................................... 4-47
Requesting Hold From Active Nonpipelined Bus ......... ; . . . . . . . . . . . . . . . . . . . . . . .. 4-48
Requesting Hold from Active Pipelined Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-49
Figures
4-25
4-26
4-27
4-28
4-29
4-30
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
7-1
A-1
A-2
C-1
C-2
C-3
D-1
D-2
D-3
D-4
D-5
E-1
E-2
E-3
E-4
E-5
E-6
SMI# Timing ................................................................. 4-50
1/0 Trap Timing .............................................................. 4-51
SUSP#-Initiated Suspend Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-52
HALT-Initiated Suspend Mode ................................................. 4-53
Stopping CLK2 During Suspend Mode .......... , .. , .... , ............ , .......... 4-54
Entering and Exiting Float ..................................................... 4-55
Internal Pullup/Pulidown-IV Characteristic ........................................ 5-3
TI486SXLC Drive Level and Measurement Points for AC Characteristics ............ 5-17
TI486SXL Drive Level and Measurement Points for AC Characteristics ............. 5-18
CLK2 Timing Measurement Points ............................................. 5-19
RESET Setup and Hold Timing ................................................ 5-29
TI486SXLC Input Signal Setup and Hold Timing ................................. 5-29
TI486SXLC Output Signal Valid Delay Timing .................................... 5-30
TI486SXLC Data Write Cycle Valid Delay Timing ...... . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-30
TI486SXLC Data Write Cycle Hold Timing ....................................... 5-31
TI486SXLC Output Signal Float Delay and HLDA Valid Delay Timing ............... 5-31
TI486SXL Input Signal Setup and Hold Timing ................................... 5-32
TI486SXL Output Signal Valid Delay Timing ..................................... 5-33
TI486SXL Data Write Cycle Valid Delay Timing .................................. 5-33
TI486SXL Data Write Cycle Hold Timing ........................................ 5-34
TI486SXL Output Signal Float Delay and HLDA Valid Delay Timing ................. 5-34
TI486SXLC Terminal Assignments .............................................. 6-2
132-Pin PGA TI486SXL Package Terminals (Bottom View) ......................... 6-4
132-Pin PGA TI486SXL Package Terminals (Top View) ............................ 6-5
144-Pin QFP TI486SXL Package Terminals (Top View) ............................ 6-7
168-Pin PGA TI486SXL Package Terminals (Bottom View) ......................... 6-9
168-Pin PGA TI486SXL Package Terminals (Top View) ........................... 6-10
1OO-Pin Thermally Enhanced Plastic QFP Package Dimensions (TI486SXLC) ....... 6-13
132-Pin Ceramic PGA Package Dimensions (TI486SXL) .......................... 6-14
144-Pin Plastic QFP Dimensions (TI486SXL) .................................... 6-15
144-Pin Ceramic QFP Package Dimensions (TI486SXL) .......................... 6-16
168-Pin Ceramic PGA Package Dimensions (TI486SXL) .......................... 6-17
Wind Tunnel Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-20
General Instruction Format ..................................................... 7-2
SMI# Timing .................................................................. A-5
SMM Memory Space Header ................................................... A-8
Cache Invalidation for the TI486SXLC and the 132-pin TI486SXL ................... C-4
Cache Invalidation for the 144- and the 168-Pin TI486SXL ......................... C-5
FLUSH# for 144-Pin and 168-Pin TI486SXL ...................................... C-5
FLUSH# Logic With a Serial Secondary Cache ................................... D-2
FLUSH# Logic With Level-2 Serial Cache ........................................ D-3
Hardware Flush .............................................................. , D-7
3.3-V VL-Bus Implementation ..... " ........... " ......... , .................... , D-9
Mixed 3.3-V/5-V VL-Bus Implementation ........................................ D-10
Effect of Component Operating Temperature on Component Failure Rate ............ E-2
Die Using a Temperature-Sensitive Electrical Parameter ........................... E-4
Diode Voltage Versus Temperature for a Typical Bipolar Device ..................... E-4
Metal Within Projected Footprint of Integrated Circuit .............................. E-8
Plotting Die Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. E-12
Wind Tunnel Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. E-13
Table of Contents
xv
Tables
1-1
1-2
1-3
1-4
1-5
1-6
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
3-1
3-2
3-3
3-4
3-5
xvi
TI486SXLC Product Offering ................................................... 1-3
TI486SXL Product Offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-3
TI486SXLC Microprocessors ................................................... 1-5
TI486SXL Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9
TI486SXLC and TI486SXL Signal Differences ................................... 1-15
TI486SXL and TI486SLC/DLC Feature Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-16
TI486SXLC Initialized Register Contents ......................................... 2-3
TI486SXL Initialized Register Contents .......................................... 2-4
Real Mode Versus Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
Segment Register Selection Rules ............................................. 2-13
EFLAGS Definitions ..................................................... :.... 2-15
CRO Bit Definitions ........................................................... 2-19
Segment Descriptor Bit Definitions ............................................. 2-22
Gate Descriptor Bit Definitions ................................................. 2-23
TI486SXLC Configuration Control Registers ..................................... 2-26
TI486SXL Configuration Control Registers ...................................... 2-26
CCRO Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-27
CCR1 Bit Definitions .......................................................... 2-28
ARR1-ARR4 Block Size Field ................................................. 2-30
DR6 and DR7 Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-32
TR6 and TR7 Bit Definitions ................................................... 2-34
TR6 Attribute Bit Pairs ........................................................ 2-34
TR3-TR5 Bit Definitions ..................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-36
Memory Addressing Modes ................................................... 2-38
Directory and Page-Entry (DTE and PTE) Bit Definitions .......................... 2-42
Interrupt-Vector Assignments .................................................. 2-46
Interrupt and Exception Priorities ............................................... 2-47
Exception Changes in Real Mode .............................................. 2-47
Error-Code Bit Definitions ..................................................... 2-48
SMM Memory Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-52
SMM Instruction Set .......................................................... 2-53
Descriptor Types Used for Control Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-59
TI486SXLC Signal Summary ................................................... 3-3
TI486SXLC Terminal Functions ................................................. 3-4
Signal States During Reset and Hold Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-12
Bus Cycle Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-13
Signal States During Suspend Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-16
Tables
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-13
7-1
7-2
7-3
TI486SXL Signal Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
TI486SXL Terminal Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
Byte Enable Line Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-13
Write Duplication as a Function of BE3#-BEO# .................................. 4-14
Generating A 1-AO Using BE3#-BEO# ......................................... , 4-14
Signal States During Reset and Hold Acknowledge .............................. , 4-15
Bus-Cycle Types ............................................................ , 4-16
Signal States During Suspend Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-19
Terminals Connected to Internal Pullup and Pulldown Resistors ..................... 5-2
Terminals Requiring External Pullup Resistors .................................... 5-3
Absolute Maximum Ratings .................................................... 5-4
TI486SXL-G Recommended Operating Conditions ................................ 5-5
TI486SXLC-V and TI486SXL-V Recommended Operating Conditions ................ 5-6
TI486SXLC and TI486SXL Recommended Operating Conditions. . . . . . . . . . . . . . . . . . .. 5-6
T1486SXL-G40 Electrical Characteristics ......................................... 5-7
T1486SXL2-G50 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-8
TI486SXLC-V25 Electrical Characteristics ........................................ 5-9
TI486SXL -V40 Electrical Characteristics ........................................ 5-10
T1486SXL2-V50 Electrical Characteristics ...................................... , 5-11
T1486SXLC-040 Electrical Characteristics ....................................... 5-12
T1486SXLC2-050 Electrical Characteristics ................................ _..... , 5-13
TI486SXL -040 Electrical Characteristics ........................................ 5-14
T1486SXL2-050 Electrical Characteristics ....................................... 5-15
Measurement Points for AC Characteristics ..................................... 5-16
AC Characteristics for TI486SXL -G40 .......................................... 5-20
AC Characteristics for TI486SXL2 -G 50 ........................................ , 5-21
AC Characteristics for TI486SXLC-V25 ......................................... 5-22
AC Characteristics for T1486SXL-V40 .......................................... 5-23
AC Characteristics for T1486SXL2-V50 ......................................... 5-24
AC Characteristics for T1486SXLC-040 ......................................... 5-25
AC Characteristics for T1486SXLC2-050 ....................................... , 5-26
AC Characteristics for TI486SXL -040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-27
AC Characteristics for TI486SXL2 -0 50 ......................................... 5-28
TI486SXLC Signal Names Sorted by Terminal Number. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
TI486SXLC Terminal Numbers Sorted by Signal Name. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
132-Pin PGA TI486SXL Signal Names Sorted by Terminal Number ......_. . . . . . . . . . .. 6-6
132-Pin PGA TI486SXL Terminal Numbers Sorted by Signal Name . . . . . . . . . . . . . . . . .. 6-6
144-Pin QFP TI486SXL Signal Names Sorted by Terminal Number . . . . . . . . . . . . . . . . .. 6-8
144-Pin QFP TI486SXL Terminal Numbers Sorted by Signal Name. . . . . . . . . . . . . . . . .. 6-8
168-Pin PGA TI486SXL Signal Names Sorted by Terminal Number .......... , ...... 6-11
168-Pin PGA TI486SXL Terminal Numbers Sorted by Signal Name ................ , 6-11
TI486SXL Signal Summary for 168-Pin PGA Pinout .............................. 6-12
TI486SXLC 100-Pin PQFP Thermal Resistance and Airflow ....................... 6-18
TI486SXL 132-Pin CPGA Thermal Resistance and Airflow ........................ 6-19
TI486SXL 144-Pin PQFP Thermal Resistance and Airflow ........................ , 6-19
TI486SXL 144-Pin CQFP Thermal Resistance and Airflow. . . . . . . . . . . . . . . . . . . . . . . .. 6-19
TI486SXL 168-Pin CPGA Thermal Resistance and Airflow ........................ 6-20
Instruction Fields .............................................................. 7-3
Instruction Prefix Summary ..................................................... 7-4
w Field Encoding .............................................................. 7-5
Table of Contents
xvii
Tables
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
A-1
A-2
A-3
A-4
A-5
A-6
D-1
0-2
E-1
E-2
E-3
E-4
E-5
F-1
F-2
xviii
d Field Encoding ................................... , ........... , .............. 7-6
reg Field Encoding ............................................................ 7-6
mod rIm Field Encoding ... , .................................................... 7-7
mod rIm Field Encoding Dependent on w Field ...... , ..... " ...................... 7-8
mod base Field Encoding ...................................................... 7-9
ss Field Encoding ............................................................ 7-10
index Field Encoding ......................................................... 7-10
sreg2 Field Encoding ......................................................... 7-10
sreg3 Field Encoding ......................................................... 7-11
eee Field Encoding ..... " .................... , ............................... 7-11
Flag Abbreviations ........................................................... 7-12
Action of Instruction on Flag ................................................... 7-12
Clock-Count Abbreviations .................................................... 7-13
Instruction Set ... , .................................... " ..................... 7-14
Power Management Options ................................................... A-3
SMM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-4
SMM Memory Space Header ...................................... . . . . . . . . . . . .. A-8
Setting SMM Register Bits .................................................... A-11
SMM Instruction Set with Clock Counts ......................................... A-13
EDX Register Data At Power-Up/Reset ......................................... A-28
VL-Bus Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 0-7
VL-Bus Slot ID Settings ........................................................ D-8
Thermal Conductivity of Packaging Materials ..................................... E-5
Thermal Performance of Various 486-Class Microprocessors ....................... E-6
Thermal Conductivity of PWBs With Various Amounts of Copper .................... E-7
RE>JA Versus Board Type ...................................................... E-8
R E>JA Versus Airflow .......................................................... E-9
TI486SXLC and TI486SXL Part Numbers ........................................ F-2
TI486SLC/E and TI486DLC/E Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. F-3
Examples
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
8-1
8-2
Accessing Main Memory Overlapping SMM Space ................................ A-9
SMM Setup ................................................................. A-11
Macros That Implement the Special SM Instructions .............................. A-14
Typical Coding Found In SMI Handlers .......................................... A-17
SMI Handler Routine ......................................................... A-22
Detection of a TI Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26
Detection of SMM Capable Version ............................................. A-28
Internal Descriptor Format ..................................................... A-32
Load SS Descriptor Values (Real Mode) ........................................ A-33
Debugging SMI Code ......................................................... A-36
Turning Internal Cache Off ..................................................... 8-5
Turning Internal Cache On ..................................................... 8-6
Table of Contents
xix
xx
Chapter 1
Product Overview
This chapter introduces the features of the TI486SXLC series and TI486SXL
series of microprocessors and defines the differences between them. The
TI486SXL series offers a -G version that operates at 3.3 volts and features 5-V
tolerant I/Os for use in either 3.3-volt-only or mixed 3.3-V/5-V systems. A
functional block diagram, logic symbol, and I/O signal identifications are
provided for the TI486SXLC and TI486SXL series of microprocessors.
Additional material describes selected system architectures such as the
execution pipeline, the on-chip cache memory, and the power-management
techniques. The system-management mode (SMM) permits the TI486SXL(C)
family of microprocessors to respond to and service interrupts with a higher
priority than standard 486 processors.
Topic
Page
1.1
. 'C'c' ,:, . , . , ..... , . , , 'c'c' . , , , . , , , , , .,'.....•..... c" •......• 1..2
1.2
Introduction c............................ ~ ................ c. • . • . .• 1-4
1.3
TI486SXLC Series Overview •...•.•.•.• , .• '. , •.. , ..••••.••.. ,c.. 1-5
1.4 .TI486SXL Secrias Overview •.
0
•• 0
........................
~
•
•
•
•
•
••
1-9
1.5
Differences Between cthe TI486SXLC Series cand
TI486SXL Series ........... ~ .....;....•. ~ ... ~ • . • .. . . . • • . .. . ... 1-15
1.6
Differences Between the TI486SXL(C) Family· and
TI486SLC/DLCFamily .••.•••.•.••:., ...•.•..••.•• ~ ...•••....•. 1-16
1.7
Execution Pipeline . ~ .... ~ ..
1.8
Ori-ChipCache. ~ ......... :.. •• • . . •.• • . . • .•• . . . . • •. •• . . . • • • . . . .1";17
1.9
'Clock-Doubled Mode,. "w . . . . co;'o' •• ;........................ o' ••• 1..18
:o . . . . . .
~
.....
0;'" . . . . . . .
~
.........
1.10 Power Management·:~ c' ••• -: • ~ •••••••••.•..;........ ;.; •.••••
0
0
cc. 1-17.
• • • • • ;.
1-18
1-1
Features
1.1
Features
The TI486SXLC and TI486SXL series microprocessors are attractive for new
486-compatible system designs as they are instruction-set and footprint compatible with existing platforms. Additionally, they implement high-performance
levels, including clock-doubled CPUs with on-chip 8K-byte cache, advanced
power-management techniques, and industry-standard pinouts that simplify
implementation of energy-efficient desktop and/or battery-powered notebook
systems. Their expanded features are:
o
o
o
1-2
486 architecture and performance
•
486-compatible instruction set and register set
•
On-chip 8K-byte, 32-bit instruction/data cache configured as two-way
set associative
•
Clock-doubled 3.3-V with 5-V tolerant I/Os, and 5-V versions
•
Highly optimized, variable-length pipeline
•
On-chip 16-bit hardware multiplier
High-performance, footprint-compatible upgrade path for existing
TI486SLC and TI486DLC platforms
•
Clock speeds up to 50 MHz
•
Industry standard footprints:
TI486SXLC series uses 100-pin QFP (486SLC footprint)
TI486SXL series uses 132-pin PGA (486DLC footprint), 144-pin plastic or ceramic QFP (486DLC footprint), and a 168-pin CPGA (4868X
footprint)
Advanced power-management features for battery-powered notebook
and energy-efficient desktop PC systems
•
System-management mode (SMM)
•
High-priority system-management interrupt (8MI) with separate
memory-address space
•
Suspend mode (initiated by either hardware or software)
•
Dynamic clock scaling
•
Fully static device permits clock-stop state
•
3.3-V versions provide approximately 60-percent power savings
•
3.3-V versions with 5-V tolerant inputs and outputs (available in the
TI486SXL series) can be used in 3.3-V-only or mixed 3.3-V/5-V
systems
Features
Features (Continued)
o
o
Texas Instruments EPICTM submicron CMOS technology
TI4B6SXLC series features 32-bit internal and 16-bit external buses. The
product offering is shown in Table 1-1 .
Table 1-1. TI486SXLC Product Offering
Speed (MHz)
TI486SXLC Series
Device Part Number
Supply Voltage
(V)
Core
TX486SXLC-V25-PJF
3.3
25
25
TX486SXLC-040-PJF
5
40
40,20t
TX486SXLC2-050-PJF
5
50
25
Bus
Package
100-pin QFP
t These microprocessors can be operated as nonclock-doubled 40 MHz or clock-doubled 20/40
MHz.
0
TI4B6SXL series features 32-bit internal and 32-bit external buses. Theproduct offering is shown in Table 1-2
Table 1-2. TI486SXL Product Offering
Speed (MHz)
TI486SXL Series
Device Part Number
Supply Voltage
(V)
Core
Bus
TX486SXL-040S-GA
5
40
40,20t
TX486SXL2-050S-GA
5
50
25
Package
132-pin PGA
TX486SXL -040-PCE
5
40
40,20t
144-pin TEP
TX486SXL-G40-HBN
3.3-V, 5-V tolerant
40
40,20t
TX486SXL2-G50-HBN
3.3-V, 5-V tolerant
50
25
144-pin ceramic QFP
TX486SXL -040-H BN
5
40
40,20 t
TX486SXL2-050-HBN
5
50
25
TX486SXL-G40-GA
3.3-V, 5-V tolerant
40
40,20t
TX486SXL2-G50-GA
3.3-V, 5-V tolerant
50
25
TX486SXL-V40-GA
3.3
40
40,20t
TX486SXL2-V50-GA
3.3
50
25
TX486SXL -040-GA
5
40
40,20t
TX486SXL2-050-GA
5
50
25
16B-pin PGA
t These microprocessors can be operated as nonclock-doubled 40 MHz or clock-doubled 20/40
MHz.
For an explanation of the part numbers see Appendix F.
Product Overview
1-3
Introduction
1.2 Introduction
The Texas Instruments TI486SXL(C) microprocessor family is comprised of
advanced x86-compatible processors that offer clock-doubled features for increased system performance. Each provides an internaI8K-byte, 32-bit cache
and integrated power management on a single chip.
The fully static, 486 instruction-set-compatible TI486SXLC series microprocessors are backward compatible with the TI486SLC/E. The TI486SXLC2
microprocessors contain a clock-doubled feature for increased system
performance of up to 50 MHz. The TI486SXLC series is an ideal solution for
battery-powered applications as it typically draws only 0.1-mA supply current
while the input clock is stopped in suspend mode. The TI486SXLC-V25 offers
additional power savings as it operates from a 3.3-V power supply.
The fully static, 486 instruction-set-compatible TI486SXL series microprocessors are available in three package types: a 132-pin PGA, 144-pin QFPs, and
a 168-pin PGA. The 132-pin PGA TI486SXL and TI486SXL2 are backward
compatible with the TI486DLC/E, the 144-pin QFP TI486SXL and TI486SXL2
are backward compatible with the 486DLC footprint, and the 168-pin PGA
TI486SXL and TI486SXL2 have the same footprint as the 486SX pinout (see
Appendix D, OEM Modifications for 168-Pin CPGA). The TI486SXL2 microprocessors contain a clock-doubled feature for increased system performance
of up to 50 MHz. The TI486SXL series is an ideal solution for battery-powered
applications as it typically draws only 0.1 mA while the input clock is stopped
in suspend mode. The T1486SXL-V40 and T1486SXL2-V50 offer additional
power savings as they operate from a 3.3-V power supply. The TI486SXL -G40
and T1486SXL2-G50 offer the equivalent power savings with the added capability to operate in either 3.3-V-only systems or in mixed 3.3-V/5-V systems.
The TI486SXL series microprocessors support 8-,16-, and 32-bit data types
and operate in real, virtual-8086, and protected modes. The TI486SXL(C) microprocessor family achieves high performance through use of a highly optimized, variable-length pipeline combined with a RISC-like, single-cycle
execution unit, an on-chip hardware multiplier, and an 8K-byte integrated
instruction and data cache.
1-4
T1486SXLC Series Overview
1.3 TI486SXLC Series Overview
The TI486SXLC series of microprocessors are implemented using Texas
Instruments EPICTM submicron CMOS technology. The combination of highperformance 486 operation, internal 8K-byte cache, advanced power
management, and small-form-factor package makes the TI486SXLC series
ideal for notebooklsubnotebook applications. A summary of the product
offering is shown in Table 1-3. Figure 1-1 is a functional block diagram and
Figure 1-2 is the logic symbol for the TI486SXLC microprocessors.
Table 1-3. TI486SXLC Microprocessors
Device
t
Supply Voltage (V)
Speed (MHz)
Core
Bus
TI486SXLC-V25
3.3
25
25
T1486SXLC-040
5
40
40,20+
T1486SXLC2-050
5
50
25
Packaget
100-pin QFP
Pinout and footprint compatible with TI486SLC/E.
+These microprocessors can be operated as nonclock-doubled 40 MHz or clock-doubled 20/40
MHz.
Product Overview
1-5
T1486SXLC Series Overview
Figure 1-1. TI486SXLC Functional Block Diagram
r----------------------·--------T--------,
1
Decoder
Control
"
, ,
ROM
Address
Sequencer 4
~
4--
1"-
II
Bus
Clock
-
CLK2
:
!
I
..
Microcode ROM
Immediate
,
,r
Execution Unit
Limit Multiplier
Unit
Unit
~
(fDala Bus
.+
3-lnput
Adder Shift Register
Unit
File
Unit
- ..
:1
1
Execution Pipeline
---------r - - - - - - - - - - - - - J
"
Memory
Management
Unit
Cache and Memory
Management
.
,
~
--+-
Prefetch
Unit
-----..
1
1
1
....
1
Clock control
1"1
1
.... SUSP#
1
Suspend ....
32 1/
Mode
1
SUSPA#
Internal
Control
I~
1
Data Bus
SMI#
I ..
1
....
SMM
1
SMADS#l...
Control
1
I"
1 Memory
Enhanced 386SX- 1
Compatible
1
Bus Interface
1
1
1
Byte
D15-DO
Data
....
__
1
..
/
I
Muxes
...
...
& I/O
Buffers
/16
1
Regs
~/
Control
L
-~
Immediate
.l
Branch Control
Core
Clock
1
16-byte
Instruction
Queue
Bus
Control
8 KByte
,
Instr/Data
Cache
-
....
.~
Data Address Bus
1
1
Control 1
1
1
1
1
A23-A1
~
Instruction
Address Bus
.
...
I ..
Address
Buffers
BHE#,
.~
TI486SXLC Microprocessor
..11
I"
~
Interface
~LE#!
/26
1
1
1
------------------------------- ---------
1-6
Tl486SXLC Series Overview
Figure 1-2. TI486SXLC Logic Symbolt
«I>
TI486SXLC
MICROPROCESSOR
CLK2
2x Clock Input
RESET
Non-Maskable Req.
INTR
SMI#
Interrupt
Control
Maskable Req.
...
....
'"
~
~
System Mgmt Int.
~
~ Float
KEN#
~
~ Cache Enable
FLUSH#
I'-
~
Cache Flush
~
Extension Req.
I'-
~
Extension Busy
~
~
Extension Error
BUSY#
ERROR#
SUSP#
I'-
SUSPA#
/'
A20M#
'"
~
Bus Ready l./1 .......
k---l ____
Next Address Req.
....
Bus
Cycle
Control
Address Strobe v ~
READY#
NA#
ADS#
SMADS#
ICache
Internal
Interface
Coprocessor
Interface
Bus
Cycle
Definition
Data/Control v
D/C#
Memory I/O v
M/IO#
Write/Read v
W/R#
Bus Lock ~
Suspend Req·1 Power
Suspend Ack.
HOLD
HLDA
Hold Ack.
SMM Address Strobe v ~
FLT#
PEREQ
....
I
Reset
NMI
.
Hold Request
Bus
Arbitration
Management
~ Address Bit 20 Mask
I Byte High En. 'V
Byte Low En. V
~
Byte
Enables
i"'-,.
I
LOCK#
BHE#
BLE#
I
DO
0
1
A1
•
•
•
•
•
•
•
•
•
•
•
•
D15
15
V<
Data)
I
Addresvv
23
A23
tThis symbol is in accordance with ANSI/IEEE Std 91-1991 and IEC Publication 617-12.
Product Overview
1-7
T1486SXLC Series Overview
The TI486SXLC includes two power-management signals (SUSP# and
SUSPA#). two cache-interface signals (FLUSH# and KEN#). an A20 mask
input (A20M#). and two SMM signals (SMADS# and SMI#) that are additions
to the 386SXsignai set. The TI486SXLC series has the same signal set as the
TI486SLC/E microprocessor and the complete list of TI486SXLC signals is
shown in Figure 1-3 .
. Figure 1-3. TI486SXLC Input and Output Signals
A20M# ----. 6.
A23-A1
BUSY# ----.
CLK2 ----.
AOS#
TI486SXLC
Microprocessor
BHE#
ERROR# ----.
BLE#
015-00
FLT# ----.
FLUSH# ----. •
O/C#
INTR ----.
HLOA
HOLD ----.
LOCK#
KEN# ----. •
M/IO#
NA# ----.
NMI----'
PEREQ ----.
SUSP# ----. •
REAOY# ----.
RESET ----.
1-8
•
Internal Cache Interface
•
Power Management
6.
A20 Mask
•
System Management Mode
•
•
•
SUSPA#
SMAOS#
SMI#
W/R#
TJ486SXL Series Overview
1.4 TI486SXL Series Overview
The TI486SXL series of microprocessors are implemented using Texas
Instruments EPIC submicron CMOS technology. The combination of
high-performance 486 operation, internal 8K-byte cache, 32-bit external data
path, and advanced power-management features makes the TI486SXL series
ideal for energy-efficient desktop and notebook applications. A summary of
the product offering is shown in Table 1-4. Figure 1-4 is a functional block
diagram and Figure 1-5 and Figure 1-6 are logic symbols for the 132-pin,
144-pin, and 168-pin TI486SXL microprocessors.
Table 1-4. TI486SXL Microprocessors
Device
Supply Voltage (V)
Speed (MHz)
Core
Bus
TI486SXL -G40
3.3-V, 5-V tolerant
40
40,20t
T1486SXL2-G50
3.3-V, 5-V tolerant
50
25
TI486SXL -V40
3.3
40
40,20t
T1486SXL2-V50
3.3
50
25
TI486SXL -040
5
40
40,20t
T1486SXL2-0501l
5
50
25
Package
144-pin OFP=I=, and
168-pin PGA §
168-pin PGA§
132-pin PGA=I=,
144-pin OFP*, and
168-pin PGA §
t These microprocessors can be operated as nonclock-doubled 40 MHz or clock-doubled 20/40
MHz.
+Pinout and footprint compatible with TI486DLC/E
§ Footprint compatible with 486SX. See Appendix 0, OEM Modifications for 168-Pin CPGA.
11 Available in 144-pin ceramic QFP and
168-pin PGA
Product Overview
1-9
T1486SXL Series Overview
Figure 1-4. TI486SXL Functional Block Diagram
r----------------------·--------r--------I
I
Decoder
~
...-
,r
,r
ROM
Address
Sequencer
......
...
Microcode ROM
n
Immediate
Control
,
,r
Limit Multiplier
Unit
Unit
Execution Pipeline
--------"
,+
~
I
---+
4
...
~
--.
Instruction
Address Bus
Data Address Bus
TI486SXL Microprocessor
L ______________________________
1-10
CLK2
SMI#
SMM
Control
I
--..
8 KByte
InstrlData
Cache
f
....
-
SMADS#
386DX-Compatible
Bus Interface
Byte
.....
Muxes
and 1/0
Registers
,
Prefetch
Unit
Clock
control
Memory
I
3-lnput
Adder Shift Register
Unit
File
Unit
I
_ SUSP#
Suspend
Mode
.... SUSPA#
Control
32/
Internal
Data Bus
I
_ _ _ _ _ _ _ _ _ _ _ _ _ -1I
Memory
Management ~
Unit
Cache and Memory
Management
,..-
tiData Bus
Execution Unit
Branch Control
,
I
I
I
I
I
I
I
I
I
I
Immediate
Control
,.
16-byte
Instruction
Queue
4--
Core
Clock
~
Bus
Clock
I
I
I
I
I
I
I
I
I
I
I
I
1•
1"-
031-00
Data
Buffers
Bus
Control
/
/32
......
Control
A31-A2
Address
Buffers
I
I
I
I
!
I-
I
I"
I ~
I-
I
I
I
I
I
I
I ..
I
I
I
I
I
I..
1I
I
I
II
BE3#~BEO# ,
/34
I
I
I
I _________!I
I ..
I"
~
Tl486SXL Series Overview
Figure 1-5. TI486SXL Logic Symbolt (132-Pin PGA Package)
TI486SXL
MICROPROCESSOR
(132-pin PGA)
CLK2
----I>
2x Clock Input
Bus
Arbitration
RESET
INTR
Interrupt
Control
Maskable Req.
~
..
~
'"
~ System Mgmt Int.
KEN#
'"
'" Cache Enable
FLUSH#
'"
~
PEREQ
I -.....
~-
HOLD
Hold Ack.
1---
HLDA
....
Bus Size 16 V1 ....
Non-Maskable Req.
....
Hold Request
Reset
---I
NMI
SMJ#
I
~
Bus Ready V1 .......
Bus
Cycle
Control
ICache
Internal
Cache Flush
Next Address Req.
Address Strobe v
Extension Req.
Coprocessor
Interface
'"
~
Extension Busy
ERROR#
'"
~
Extension Error
SUSP#
'"
'" Suspend Req'l Power
SUSPA#
/'
Suspend Ack.
A20M#
'"
...
~
SMM Address Strobe V ~
READY#
NA#
ADS#
SMADS#
Bus
Cycle
Definition
Data/Control V
D/C#
Memory I/O V
M/IO#
Write/Read V
W/R#
Bus Lock . . . . .
Management
~ Address Bit 20 Mask
LOCK#
Byte Enable 3 V "-
BE3#
Byte Enable 2 V "Byte
Enables Byte Enable 1 V . . . . .
BE2#
Byte Enable 0 V "-
BEO#
I
BE1#
I
DO
o
•
•
031
~
Interface
BUSY#
•
•
./1
BS16#
•
•
V<
Data)
I
Addrese>v
31
2
A2
•
•
•
•
31
A31
•
•
tThis symbol is in accordance with ANSI/IEEE Std 91-1991 and lEG Publication 617-12.
Product Overview
1-11
Tl486SXL Series Overview
Figure 1-6. TI486SXL Logic Symbolt (144-Pin QFP and 168-Pin PGA Packages)
TI486SXL
MICROPROCESSOR
(144-pin QFP and
168-pin PGA)
CLK2 - - - - I ' > 2x Clock Input
Hold Request
I - -....
~I---
HOLD
Hold Ack.
1----
HLDA
Busl
Arbitration
RESET
----I
NMI
FLT#
KEN#
......
......
"'"
~ System Mgmt Int.
'"
~ Float
I"--
~ Cache Enable
I'--
----'--">I
---L.::::oI
~ Cache Flush
MEMW#
I"---~
Memory Write
(ISA bus)
PEREQ - - - - - I
ERROR#
Interrupt
Control
Maskable Req.
FLUSH#
BUSY#
Bus Size 16 1/1 -
Non-Maskable Req.
INTR
SMI#
Reset
~
'"
-----L.:::.I ~
READY#
Next Address Req. 1/'1 ...
NA#
ADS#
Address Strobe V "'-
SMM Address Strobe V ...,::"'->---- SMADS#
Internal
Cache
Interface
Bus
Cycle
Definition
Data/Control V
D/C#
Memory I/O V
M/IO#
Write/Read V
W/R#
'"
'"
~ Suspend Req'l Power
+
W/R#
Write/Read V
Coprocessor
Interface
~
-----L.::>I
Bus Ready 1/1 ~
Bus
Cycle
Control
Extension Req.
Extension Busy
BS16#
Bus Lock r-...
LOCK#
Extension Error
Byte Enable 3 V ....."r-...>---_ _ BE3#
SUSP#
SUSPA#
A20M#
---,,/'-1
Suspend Ack.
Management
'" ~ Address Bit 20 Mask
BE2#
Byte Byte Enable 2 V r-...
Enables Byte Enable 1 V I-='r-...>--_ _ BE1#
Byte Enable 0 V r-...
00-----1
•
•
•
•
•
031
o
•
----I
2
I
•
Addresvv
31
tThis symbol is in accordance with ANSI/IEEE Std 91-1991 and lEG Publication 617-12.
+144-pin QFP has W/R# on pins 36 and 37. These terminals must be connected together.
1-12
1----
A2
•
•
•
31
BEO#
•
•
1----
A31
T1486SXL Series Overview
The TI486SXL includes two power-management signals (SUSP# and
SUSPA#), two cache-interface signals (FLUSH# and KEN#), an A20 mask
input (A20M#), and two SMM signals (SMAOS# and SMI#) that are additions
to the 3860X signal set. The 132-pin PGA TI486SXL has the same signal set
as the TI486DLC/E microprocessor while the 144-pin QFP and the 168-pin
PGA have two additional inputs, MEMW#, and FLT#. MEMW# is part of the
cache interface and FLT# can be used to float the bidirectional and output
signals. (See Appendix 0, OEM Modifications for 168-Pin CPGA.). The
complete list of TI486SXL signals is shown in Figure 1-7 for the 132-pin PGA
and Figure 1-8 for the144-pin QFP and 168-pin PGA.
Figure 1-7. TI486SXL Input and Output Signals for 132-Pin PGA Package
A20M#---' •
BS16# ---.
A31-A2
AOS#
BUSY#---'
CLK2 ----.
ERROR#---'
TI486SXL
Microprocessor
132-pin PGA
BE3#-BEO#
031-00
FLUSH#---' •
O/C#
INTR ---.
HLOA
HOLD ----.
LOCK#
KEN#---' •
M/IO#
NA#---'
NMI---'
PEREQ---'
SUSP# ----. •
•
•
•
SUSPA#
SMAOS#
SMI#
W/R#
READY# ----.
RESET ----.
•
Internal Cache Interface
•
Power Management
•
•
A20 Mask
System Management Mode
Product Overview
1-13
Tl486SXL Series Overview
Figure 1-8. TI486SXL Input and Output Signals for 144-Pin QFP and 168-Pin PGA Package
A20M# ----. ....
BS16# ----.
A31-A2
BUSY# ----.
CLK2 ----.
ERROR# ----.
AOS#
TI486SXL
Microprocessor
144-pin QFP and
168-pin PGA
BE3#-BEO#
031-00
FLT#
O/C#
FLUSH# ----. •
HLOA
INTR ----.
LOCK#
HOLO ----.
M/IO#
KEN# ----. •
MEMW#----' •
NA# ----.
NMI----'
PEREQ ----.
•
•
•
SUSPA#
SMAOS#
SMI#
W/R#
W/R#t
SUSP# ----. •
REAOY# ----.
RESET ----.
•
Internal Cache Interface
•
Power Management
.... A20 Mask
•
System Management Mode
t 144-pin QFP has W/R# on pins 36 and 37. These terminals must be connected together.
1-14
Differences Between the Tl486SXLC Series and Tl486SXL Series
1.5 Differences Between the TI486SXLC Series and TI486SXL Series
The TI486SXLC and the 132-pin TI486SXL are the same except for how the
pin signals are routed and utilized on the processors. Thus, the bus interfaces
/ are different but the CPU core and cache/memory management are the same.
The TI486SXLC has a physical address range of 16M bytes and the TI486SXL
has a physical address range of 4G bytes. Table 1-5 describes the signal
differences between the TI486SXLC and T1486SXL.
Table 1-5. TI486SXLC and TI486SXL Signal Differences
Description
TI486SXLC
(100-pin QFP)
TI486SXL
(132-pin PGA)
TI486SXL (144-pin QFP
and 168-pin PGA)
Data bus
16 bits wide (015-00)
32 bits wide (031-00)
32 bits wide (031-00)
Address bus
A23-A1
A31-A2
A31-A2
Byte enables
2 byte enables used
(BHE#, BLE#)
4 byte enables used
(BE3#-BEO#)
4 byte enables used
(BE3#-BEO#)
Float bus signal (FLT#)
supported
not supported
supported
Bus size 16 signal (BS16#)
not supported
supported
supported
MEMW# ISA signal
not supported
not supported
supported
The 144-pin QFP and the 168-pin PGA TI486SXL differs from both the
TI486SXLC and the 132-pin PGA TI486SXL by the addition of one signal,
MEMW#. This signal is part of the cache flush logic that is implemented
on-chip in the 144- and 168-pin versions of the T1486SXL. For a more detailed
description of this logic, see Appendix C, Design Considerations and Cache
Flush and Appendix 0, OEM Modifications for 168-Pin CPGA. The 144-pin
QFP and the 168-pin PGA TI486SXL contain the TI486SXLC signal FLT# that
is not implemented in the 132-pin PGA T1486SXL. This signal can be used to
float all bidirectional and output signals of the TI486SXL microprocessor when
it is used in conjunction with an upgrade socket. The 144-pin QFP differs from
the 168-pin PGA by the addition of a second W/R# input. As these two W/R#
inputs must be connected together, these devices are functionally the same.
Product Overview
1-15
Differences Between the Tl486SXL(C) Family and the Tl486SLCIDLC Family
1.6 Differences Between the TI486SXL(C) Family and the TI486SLC/DLC
Family
The TI486SXLC and the TI486SLC/E are the same in all respects except for
the cache size, cache organization, and the clock-doubled feature. The
TI486SXL and the TI486DLC/E are also the same in all respects except for the
same new features shown in Table 1-6. Signal differences between the
TI486SXLC and the 132-pin PGA TI486SXL, listed in Table 1-5, also apply for
the TI486SLC/E and TI486DLC/E, respectively.
Table 1-6. TI486SXL and TI486SLCIDLC Feature Differences
1-16
Description
TI486SXL(C) Family
TI486SLC/DLC Family
Cache size
8K bytes
1K byte
Cache organization
Two-way set
associative
Two-way set associative
or direct mapped
Clock doubled
Supported
Not supported
Execution Pipeline / On-Chip Cache
1.7 Execution Pipeline
The execution path in the TI486SXL(C} family of microprocessors consists of
five pipelined stages optimized for minimal instruction-cycle times. These five
stages are:
o
o
o
o
o
Code fetch
Instruction decode
Microcode ROM access
Execution
Memory/register file write-back
These stages have been designed with hardware interlocks that permit execution overlap for successive instructions.
The 16-byte instruction-prefetch queue fetches code in advance and prepares
it for decode, helping to minimize overall execution time. The instruction decoder then decodes four bytes of instructions per clock, eliminating the need
for a queue of decoded instructions. Sequential instructions are decoded
quickly and provided to the microcode. Nonsequential operations do not have
to wait for a queue of decoded instructions to be flushed and refilled before
execution continues. As a result, both sequential and nonsequential instruction execution times are minimized.
The execution stage takes advantage of a RISC-like, single-cycle execution
unit and a 16-bit hardware multiplier. The write-back stage provides singlecycle, 32-bit access to the on-chip cache and posts all writes to the cache and
system bus using a two-deep write buffer. Posted writes allow the execution
unit to proceed with program execution while the bus-interface unit completes
the write cycle.
1.8 On-Chip Cache
The 8K-byte, 32-bit on-chip cache in the TI486SXL(C} family of microprocessors maximizes overall performance by quickly supplying instructions and
data to the internal execution pipeline. An external memory access takes a
minimum of two clock cycles (zero wait states). For cache hits, the TI486SXL
series eliminates these two clock cycles by overlapping cache accesses with
normal execution pipeline activity. In addition, bus bandwidth is gained by
presenting instructions and data to the execution pipeline at up to 32 bits at a
time compared to 16 bits per cycle for an external memory access.
The TI486SXL(C} cache is an 8K-byte, write-through unified instruction and
data cache with lines that are allocated only during memory read cycles. The
cache is configured as two-way set associative, and the cache organization
consists of 1024 sets each containing two lines of four bytes each.
Product Overview
1-17
Clock-Doubled Mode / Power Management
1.9 Clock-Doubled Mode
The TI486SXL(C) family of microprocessors is designed with a clock-doubled
feature that provides an immediate performance increase and upgrade path
from the TI486SLC/DLC family of products. The clock-doubled feature can be
enabled using software by setting bit 6 of the Configuration Control register O.
When the microprocessor is in clock-doubled mode, the internal core is operating at the CLK2 frequency while the external bus interface remains at half
the CLK2 frequency. This provides a speed increase in the on-chip cache,
instruction decode, and instruction execution while the external interface remains the same.
In addition to the clock-doubled feature, the TI486SXL(C) microprocessor
family also supports dynamic clock scaling that enables the CLK2 input to be
scaled up or down. To take advantage of this feature (scaling or stopping the
CLK2 input) the processor must first be brought into the nonclock-doubled
mode. Dynamic clock scaling is transparent to the user since the processor
continues instruction execution in nonclock-doubled mode until the desired
frequency is reached within the PLL lock range to initiate clock-doubled mode.
This allows for increased bandwidth on demand without restriction to the user.
1.10 Power Management
The TI486SXL(C) family incorporates advanced power-managementfeatures
such as suspend mode, static operation, and operation at 3.3 V. These capabilities are attractive for battery-powered notebook and energy-efficient desktop PC systems.
1.10.1 System-Management Mode (SMM)
System-management mode (SMM) provides an additional interrupt and a
separate address space that can be used for system power management or
software-transparent emulation of liD peripherals. SMM is entered using the
system-management interrupt (SMI#) that has a higher priority than any other
interrupt. While running in protected SMM address space, the SMI interrupt
routine can execute without interfering with the operating system or
application programs.
After receiving an SMI# interrupt, portions of the CPU state are automatically
saved, SMM is entered and program execution begins at the base of SMM
address space. The location and size of the SMM memory is programmable
in the TI486SXL(C) microprocessor family. Seven SMM instructions have
been added to the 486 instruction set that permit saving and restoring the total
CPU state when in SMM mode.
1.10.2 Suspend Mode and Static Operation
The power-management features in the TI486SXL(C) family of microprocessors allow a dramatic reduction in the current required when the microproces-
1-18
Power Management
sor is in suspend mode (typically less than three percent of the operating current). Suspend mode is entered either by a hardware- or software-initiated
action. Using the hardware to initiate suspend mode involves a two-pin handshake using the SUSP# and SUSPA# signals.
The software initiates suspend mode through execution of the HALT instruction. Once in suspend mode, the microprocessor power consumption can be
further reduced by stopping the external clock input.
Note:
For the clock-doubled versions of the TI486SXL(C} microprocessor family,
suspend mode can be initiated while in clock-doubled mode as long as the
external input clock is not stopped. The external input clock can be stopped
after the microprocessor has been put into nonclock-doubled mode.
Since these microprocessors are static devices, no internal CPU data is lost
when the clock input is stopped.
1.10.3 3.3-V Operation
The TI486SXLC-V and TI486SXLC2-V versions operate from a 3.3-V supply.
Power consumed is typically only 30 percent of the power consumed while
operating at 5 V. The TI486SXLC-V25 operates at 25-MHz speed.
The TI486SXL-V and TI486SXL2-V versions operate from a 3.3-V supply.
Power consumed is typically only 30 percent of the power consumed by a microprocessor operating at 5 V. The T1486SXL-V40 can be operated in
clock-doubled mode at 40-MHz core and 20-MHz bus speeds, or in nonclockdoubled mode with both the core and bus speeds at 40 MHz. The
T1486SXL2-V50 operates at 50 MHz core and 25-MHz bus speeds in the
clock-doubled mode.
1.10.4 Mixed 3.3-V and 5-V Operation
The TI486SXL-G and TI486SXL2-G versions operate from both a 3.3-V and
a 5-V supply. These microprocessors feature 5-V tolerant inputs and outputs
meaning that they can be incorporated in system designs that utilize both
3.3-V and 5-V devices. These devices can be used in 3.3-V-only systems by
connecting the 5-V supply pin (VCCS) to the 3.3-V supply. The microprocessor
power consumption is typically only 30 percent of the power consumed by a
microprocessor operating at 5 V. The TI486SXL -G40 can be operated in
clock-doubled mode at 40-MHz core and 20-MHz bus speeds, or in nonclockdoubled mode with both the core and bus speeds at 40 MHz. The
T1486SXL2-G50 operates at 50-MHz core and 25-MHz bus speeds in the
clock-doubled mode.
Product Overview
1-19
1-20
Chapter 2
Programming Interface
In this chapter, the internal operations of the TI486SXL(C) family of microprocessors are described mainly from an application programmer's point of view.
Included in this chapter are descriptions of processor initialization, the register
sets, memory addressing, various types of interrupts, system-management
mode, and the shutdown and halt process. Overviews of real, virtual-8086,
and protected operating modes are also included.
Topic
Page
2.1
Processor Initialization ....•.•..•.. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Real ModeVersus Protected Mode ............................. 2-5
2.3
Instruction-Set Overview ...................................... 2-6
2.4
Application Register Set ...........•.......................... 2-10
2.5
System Register Set ............ oi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.6
Memory Address Space ........... ~ ... ; ....... ~ ............... 2-37
2.7
Interrupts and Exceptions ............. ~ ........... ~ .. .. • .. ... 2-43
2.S
System-Management Mode .................................... 2-49
2.9
Shutdown and Halt, •...................................•...... 2-57
2.10 Protection ................ _........ ;. ........................-.. 2-57
2.11 Virtual-S086 Mode .... . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 2-60
2-1
Processor Initialization
2.1
Processor Initialization
Each TI486SXL(C) family microprocessor is initialized when the RESET signal is asserted. The processor is placed in real mode and the registers listed
in Table 2-1 or Table 2-2 are set to their initialized values. RESET invalidates
and disables the cache, and turns off paging. For the clock-doubled versions
of the TI486SXL(C) microprocessor family RESET returns the processor to
the nonclock-doubled mode. When RESET is asserted, the microprocessor
terminates all local bus activity and all internal execution. During the time that
RESET is asserted, the internal pipeline is flushed and no instruction execution or bus activity occurs.
Approximately 350 to 450 CLK2 clock cycles (additional 220 + 60 if self-test is
requested) after deassertion of RESET, the processor begins executing
instructions at the top of physical memory (address location FF FFFOh for the
TI486SXLC series and FFFF FFFOh for the TI486SXL series). When the first
intersegment JUMP or CALL is executed, address lines A23-A20 for the
TI486SXLC series or A31-A20 for the TI486SXL series are driven low for
code-segment-relative memory-access cycles. While these address lines are
low, the microprocessor executes instructions only in the lowest 1M byte of
physical address space until system-specific initialization occurs via program
execution.
2-2
Processor Initialization
Table 2-1. TI486SXLC Initialized Register Contents
Register
Register Name
Initialized Contents
Comments
EAX
Accumulator
xx xxxxh
00 OOOOh indicates self-test
passed.
EBX
Base
xx xxxxh
ECX
Count
xx xxxxh
EDX
Data
xx 0400h + Revision ID
EBP
Base Pointer
xx xxxxh
ESI
Source Index
xx xxxxh
EDI
Destination Index
xx xxxxh
ESP
Stack Pointer
xx xxxxh
EFLAGS
Flag Word
00 0002h
EIP
Instruction Pointer
00 FFFOh
ES
Extra Segment
OOOOh
Base address set to 00 OOOOh
Limit set to FFFFh
CS
Code Segment
FOOOh
Base address set to 00 OOOOh
Limit set to FFFFh
SS
Stack Segment
OOOOh
DS
Data Seglllent
OOOOh
FS
Extra Segment
OOOOh
GS
Extra Segment
OOOOh
IDTR
Interrupt-Descriptor Table
Base=O, Limit=3FFh
CRO
Machine Status Word
00 0010h
CCRO
Configuration Control
CCR1
Configuration Control 1
xx xxx a (binary)
ARR1
Address Region 1
OOOFh
ARR2
Address Region 2
OOOOh
ARR3
Address Region 3
OOOOh
ARR4
Address Region 4
OOOOh
DR?
Debug
00 OOOOh
Note:
a
Revision ID = 10h
Base address set to 00 OOOOh
Limit set to FFFFh
OOh
4G-byte noncacheable region
x = Undefined value
Programming Interface
2-3
Processor Initialization
Table 2-2. TI486SXL Initialized Register Contents
Register
Register Name
Initialized Contents
Comments
EAX
Accumulator
xxxx xxxxh
0000 OOOOh indicates self-test passed
EBX
Base
xxxx xxxxh
ECX
Count
xxxx xxxxh
EDX
Data
xxxx 0421 h + Revision ID
EBP
Base Pointer
xxx x xxxxh
ESI
Source Index
xxxx xxxxh
EDI
Destination Index
xxxx xxxxh
ESP
Stack Pointer
xxxx xxxxh
EFLAGS
Flag Word
00000002h
EIP
Instruction Pointer
0000 FFFOh
ES
Extra Segment
OOOOh
Base address set to 0000 OOOOh
Limit set to FFFFh
CS
Code Segment
FOOOh
Base address set to 0000 OOOOh
Limit set to FFFFh
SS
Stack Segment
OOOOh
DS
Data Segment
OOOOh
FS
Extra Segment
OOOOh
GS
Extra Segment
OOOOh
IDTR
Interrupt-Descriptor Table
Base=O, Limit=3FFh
CRO
Machine Status Word
00000010h
CCRO
Configuration Control 0
OOh
CCR1
Configuration Control 1
xxxx xxxO (binary)
ARR1
Address Region 1
OOOFh
ARR2
Address Region 2
OOOOh
ARR3
Address Region 3
OOOOh
ARR4
Address Region 4
OOOOh
DR?
Debug
OOOOOOOOh
Note:
2-4
x
= Undefined value
Revision ID = 10h
Base address set to 0000 OOOOh
Limit set to FFFFh
4G-byte noncacheable region
Real Mode Versus Protected Mode
2.2 Real Mode Versus Protected Mode
When powered up or reset, the microprocessor is initialized to real mode. Real
mode establishes conditions that are backward compatible with the
8086/8088 microprocessors. Addressing capabilities are limited to the range
that is available on those two microprocessors, and the default operand size
is 16 bits.
The microprocessor can be switched from the real mode into protected mode,
where the extended capabilities of The TI486SXL(C) are available for use.
Protected mode provides enhanced memory management capabilities that include segment- and page-level protection.
Table 2-3 provides a comparison of real mode and protected mode. The microprocessor is in protected mode when the PE bit in Control register a is set.
After this bit is set, an intersegment JMP is used to load the CS register and
to flush the instruction-decode pipeline.
Table 2-3. Real Mode Versus Protected Mode
Real Mode
Protected Mode
Physical Memory is limited to 1M byte.
Physical memory is limited to 4G bytes.
Virtual memory of up to 4T bytes is available.
Default operand size is 16 bits.
Default operand size is 32 bits.
Segments are fixed at 64K bytes.
Segment size can vary from 1 byte to 4G
bytes.
Physical addresses are generated by Physical address are generated by apmultiplying the segment register value by plying paging, if enabled, to linear ad16 and adding an offset to the product.
dresses. Linear addresses are generated by adding an offset to a value calculated from information contained in segment descriptors. The value in a segment
register determines which of several possible segment descriptors will be used.
No hardware protection is provided for Segments can be given combinations of
segment access or use.
read, write, and execute permissions. Attempted access beyond the end of a segment is monitored.
There is no privileged code.
Code can have one of four privilege levels, with some processor instructions restricted to the most privileged level.
Programming Interface
2-5
Instruction-Set Overview
2.3 Instruction-Set Overview
The TI486SXL(C) microprocessor family instruction set can be divided into
eight types of operations:
o
o
o
o
o
o
o
o
Arithmetic
Bit manipulation
Control transfer
Data transfer
High-level-language support
Operating-system support
Shift/rotate
String manipulation
All instructions operate on as few as zero operands and as many as three operands. An NOP (no operation) instruction is an example of a zero operand
instruction. Two-operand instructions allow the specification of an explicit
source and destination pair as part of the instruction. These two-operand
instructions can be divided into eight groups according to operand types:
o
o
o
o
o
o
o
o
Register to register
Register to memory
Memory to register
Memory to memory
Register to 110
110 to register
Immediate data to register
Immediate data to memory
An operand can be held in the instruction itself (as in an immediate operand),
in a register, in an 1/0 port, or in memory. An immediate operand is prefetched
as part of the opcode for the instruction.
Operand lengths of 8, 16, or 32 bits are supported. Operand lengths of 8 or
32 bits are generally used when executing code written for 386- or 486-class
(32-bit code) processors. Operand lengths of 8 or 16 bits are generally used
when executing 8086 or 80286 code (16-bit code). The default length of an operand can be overridden by placing one or more instruction prefixes in front
of the opcode. For example, by using prefixes, a 32-bit operand can be used
with 16-bit code or a 16-bit operand can be used with 32-bit code.
Chapter 7, Instruction Set, lists each instruction in the TI486SXL(C) microprocessor family instruction set along with the associated opcodes, execution
clock counts, and effects on the Flag Word register.
2-6
Instruction-Set Overview
2.3.1
Lock Prefix
The LOCK prefix can be placed before certain instructions that read, modify,
then write back to memory. The prefix asserts the LOCK# signal to indicate to
the external hardware that the CPU is in the process of running multiple, indivisible memory accesses. The LOCK prefix can be used with the following
instructions:
o
o
o
o
Bit test instructions (BTS, BTR, BTC)
Exchange instructions (XADD, XCHG, CMPXCHG)
One-operand arithmetic and logical instructions
(DEC, INC, NEG, NOT)
Two-operand arithmetic and logical instructions
(ADC, ADD, AND, OR, SBB, SUB, XOR)
An invalid-opcode exception is generated if the LOCK prefix is used with any
other instruction or with the above instructions when no write operation to
memory occurs (i.e., the destination is a register).
2.3.2
Register Sets
There are 43 accessible registers in the TI486SXL(C) microprocessor and
these registers are grouped into two sets. The application register set contains
the registers frequently used by applications programmers, and the system
register set contains the registers typically reserved for use by operating-systems programmers.
The application register set is made up of:
o
o
Eight 32-bit General Purpose registers
Six 16-bit Segment registers
Dane 32-bit Flag Word register
Dane 32-bit Instruction Pointer register
The system register set is made up of the remaining registers that include:
o
o
o
o
o
Three 32-bit Control registers
Two 48-bit and two 16-bit System Address registers
Two 8-bit and four 16-bit (TI486SXLC) or 24-bit (TI486SXL) Configuration
registers
Six 32-bit Debug registers
Five 32-bit Test registers
Each application register is discussed in Section 2.4, Application Register Set,
page 2-10.
Each system register is discussed in Section 2.5, System Register Set, page
2-16.
Programming Interface
2-7
Instruction-Set Overview
2.3.3
Address Spaces
The microprocessor can directly address either memory or liD space.
Figure 2-1 and Figure 2-2 illustrate the range of addresses available for
memory address space and liD address space.
Figure 2-1. TI486SXLC Memory and 110 Address Spaces
Accessible
Programmed
I/O Space
Physical
Memory Space
FFFFFFh~----------~
Physical
Memory
16M bytes
FF FFFFh
8000FFh
00 FFFFh
00 OOOOh '_____________
..--
8000F8h
------..--
00 OOOOh a...-_ _ _ _ _ _ ___
Coprocessor
Space
TI486SXLC
Configuration
Register I/O
Space
000023h
000022h
Figure 2-2. TI486SXL Memory and 110 Address Spaces
Accessible
Programmed
I/O Space
Physical
Memory Space
FFFF FFFFh ~--------~
Physical
Memory
4G bytes
FFFF FFFFh
800000FFh
0000 FFFFh
0000 OOOOh ___________
2-8
..--
800000F8h
-----.
0000 OOOOh a...-_ _ _ _ ___
..--
Coprocessor
Space
TI486SXL
Configuration
Register I/O
Space
00000023h
00000022h
Instruction-Set Overview
2.3.3.1
Memory Address Space Range
For the TI486SXLC series, the addresses for physical memory range between
00 OOOOh and FF FFFFh ( 16M bytes). For the TI486SXL series, the addresses
for physical memory range between 0000 OOOOh and FFFF FFFFh (4G bytes).
Memory address space is accessed as bytes, words (16 bits), or doublewords
(32 bits). Wordsand doublewords are stored in consecutive memory bytes
with the low-order byte located in the lowest address. The physical address
of a word or doubleword is the byte address of the low-order byte.
Section 2.6, Memory Address Space, page 2-37, discusses in detail:
Memory addressing modes that are used to calculate the physical address
Memory management mechanisms, segmentation and paging, that can
be used to protect address spaces and also create an environment that
lets a small amount of physical memory simulate a large address space.
o
o
2.3.3.2
lID Address Space Range
The accessible I/O address space for both the TI486SXLC and TI486SXL microprocessors ranges between 00 OOOOh and 00 FFFFh (64K bytes). The coprocessor communication space for the TI486SXLC series exists in upper I/O
space between 80 00F8h and 80 OOFFh. The coprocessor communication
space for the TI486SXL series exists in the upper I/O space between 8000
00F8h and 8000 OOFFh. These coprocessor liD ports are automatically accessed by the CPU whenever an ESC opcode is executed. The liD locations
22h and 23h are used for Configuration register access on all versions of the
TI486SXL(C) microprocessors.
The TI486SXL(C) family of microprocessors address space is accessed using
IN and OUT instructions to addresses referred to as ports. The accessible liD
address space is 64K bytes and can be accessed as 8-bit, 16-bit, or 32-bit
ports. The execution of any IN or OUT instruction causes M/IO# to be driven
low, thereby selecting the liD space instead of memory space for loading or
storing data. The upper eight address bits of the TI486SXLC processor and
the upper sixteen bits of the TI486SXL processor are driven low during IN and
OUT instruction port accesses.
The microprocessor Configuration registers reside within the I/O address
space at port addresses 22h and 23h and are accessed using the standard IN
and OUT instructions. The Configuration registers are modified by writing the
index of the Configuration register to port 22h and then transferring the data
through port 23h. Accesses to the on-chip Configuration registers do not generate external 110 cycles. However, each port 23h operation must be preceded
by a port 22h write with a valid index value, otherwise the second and later port
23h operations are directed off-chip and generate external liD cycles without
modifying the on-chip Configuration registers. Also, writes to port 22h outside
of the microprocessor index range (COh to CFh) result in external I/O cycles
and do not affect the on-chip Configuration registers. Reads of port 22h are
always directed off-chip.
Programming Interface
2-9
Application Register Set
2.4 Application Register Set
The Application register set (Figure 2-3) consists of the registers most often
used by the applications programmer. These registers are generally accessible and are not protected from read or write access.
The General Purpose registers contents are frequently modified by assembly
language instructions and typically contain arithmetic and logical-instruction
operands.
The Segment registers contain segment selectors that index into tables located in memory. These tables hold the base address for each segment as well
as other information related to memory addressing.
The Flag Word register contains control bits used to reflect the status of previously executed instructions. This register also contains control bits that affect
the operation of some instructions.
The Instruction Pointer is a 32-bit register that points to the next instruction that
the processor executes. This register is automatically incremented by the processor as execution progresses.
Figure 2-3. Application Register Set
31
16 15
8 7
o
- - A H - - - ¥ - - - - A L - - EAX
- - S H - - - ¥ - - - - B L - - EBX
- - C H - - - o / - - - - C L - - ECX
General
Purpose
Registers
- - O H - - - o / - - - - O L - - EOX
SI
ESI
01
EOI
BP
EBP
SP
ESP
15
0
CS
SS
OS
Segment
Registers
ES
FS
GS
31
16 15
0
IP
Flag Word
2-10
I EIP
EFLAGS
}
Instruction
Pointer and
Registers
Application Register Set
2.4.1
General Purpose Registers
The General Purpose registers are divided into four Data, two Pointer, and two
Index registers as shown in Figure 2-4.
Figure 2-4. General Purpose Registers
Data Registers
o
8 7
16 15
31
- - A H - - - ¥ - - - - , A I - - A (Accumulator)
--SH---'¥----8[--
B (Base)
--cH---Cf----cr--
C (Count)
--OH---o/----[)[--
D (Data)
Pointer and Index Registers
2.4.1. 1
(ESP)
SP
BP (Base Pointer)
(ESP)
SP
SP (Stack Pointer)
(ESI)
SI
SI (Source Index)
(EDI)
01
DI (Destination Index)
Data Registers
The Data registers are used by the applications programmer to manipulate
data structures and to hold the results of logical and arithmetic operations. Different portions of the general Data registers can be addressed by using different names. An E prefix identifies the complete 32-bit register. An X suffix without the E prefix identifies the lower 16 bits of the register. The lower two bytes
of the register can be addressed with an H suffix to identify the upper byte or
an L suffix to identify the lower byte. When a source operand value specified
by an instruction is smaller than the specified destination register, the upper
bytes of the destination register are not affected when the operand is written
to the register.
2.4.1.2
Pointer and Index Registers
The Pointer and Index registers are:
BP or EBP
8P or ESP
81 or E81
01 or EDI
Base Pointer
Stack Pointer
Source Index
Destination Index
These registers can be addressed as 16- or 32-bit registers, with the E prefix
indicating 32 bits. These registers can be used as General Purpose registers;
however, some instructions use a fixed assignment of these registers. For example, the string operations always use E81 as the source pointer, EDI as the
destination pointer, and ECX as a counter. The instructions using fixed registers include double-precision multiply and divide, liD access, string operations, translate, loop, variable shift and rotate, and stack operations.
Programming Interface
2-11
Application Register Set
The TI486SXL(C) processors implement a stack using the ESP register. This
stack is accessed during the PUSH and POP instructions, procedure calls,
procedure returns, interrupts, exceptions, and interrupt/exception returns.
The microprocessor automatically adjusts the value of the ESP during operation of these instructions. The EBP register can be used to reference data
passed on the stack during procedure calls. Local data can also be placed on
the stack and referenced relative to BP. This register provides a mechanism
to access stack data in high-level languages.
2.4.2
Segment Registers and Selectors
Segmentation provides a means of defining data structures inside the memory
space of the microprocessor. There are three basic types of segments: code,
data, and stack. Segments are used automatically by the processor to determine the memory locations of code, data, and stack references.
There are six 16-bit Segment registers:
CS
DS
FS
GS
SS
ES
Code Segment
Data Segment
Additional Data Segment
Additional Data Segment
Stack Segment
Extra Segment
In real and virtual-8086 operating modes, a Segment register holds a 16-bit
segment base. The 16-bit segment base is multiplied by 16 and a 16-bit or
32-bit offset is then added to it to create a linear address. The offset size is dependent on the current address size. In real mode and in virtual-8086 mode
with paging disabled, the linear address is also the physical address. In virtual8086 mode with paging enabled, the linear address is translated to the physical address using the current page tables.
In protected mode, a Segment register holds a segment selector containing
a 13-bit index, a table indicator (TI) bit, and a two-bit requested-privilege-Ievel
(RPL) field as shown in Figure 2-5.
Figure 2-5. Segment Selector Register
15
3
2
o
Index
TI = Table Indicator
RPL
= Requested Privilege Level
The index points into a descriptor table in memory and selects one of 8192
(2 13) segment descriptors contained in the descriptor table. A segment descriptor is an eight-byte value used to describe a memory segment by defining
the segment base, the segment limit, and access control information.
2-12
Application Register Set
To address data within a segment, a 16-bit or 32-bit offset is added to the segment's base address. Once a segment selector has been loaded into a Segment register, an instruction needs to specify the offset only.
The table indicator (TI) bit of the selector defines the descriptor table into which
the index points. If TI = 0, the index references the global-descriptor table
(GOT). IfTI = 1, the index references the local-descriptor table (LOT). The GOT
and LOT are described in more detail later in this chapter.
The requested privilege level (RPL) field contains a 2-bit segment privilege
level (00 = most privileged, 11 = least privileged). The RPL bits are used when
the Segment register is loaded to determine the effective privilege level (EPL).
If the RPL bits indicate less privilege than the program, the RPL overrides the
current privilege level and the EPL is the lower privilege level. If the RPL bits
indicate more privilege than the program, the current privilege level overrides
the RPL and again the EPL is the lower privilege level.
When a Segment register is loaded with a segment selector, the segment
base, segment limit, and access rights are also loaded from the descriptor
table into a user-invisible or hidden portion of the Segment register, i.e.,
cached on-chip. The CPU does not access the descriptor table again until
another Segment register load occurs. If the descriptor tables are modified in
memory, the Segment registers must be reloaded with the new selector values.
The processor automatically selects a default Segment register for memory
references. Table 2-4 describes the selection rules. In general, data references use the selector contained in the OS register, stack references use the
SS register, and instruction fetches use the CS register. While some of these
selections can be overridden, instruction fetches, stack operations, and the
destination write of string operations cannot be overridden. Special segment
override prefixes allow the use of alternate Segment registers including the
use of the ES, FS, and GS Segment registers.
Table 2-4. Segment Register Selection Rules
Type of Memory Reference
Implied (Default)
Segment
Segment Override
Prefix
Code fetch
CS
None
Destination of PUSH, PUSHF, INT, CALL, PUSHA
instructions
SS
None
Source of POP, POPA, POPF, IRET, RET instructions
SS
None
Destination of STOS, MOVS, REP STOS, REP
MOVS instructions
ES
None
OS
SS
CS, ES, FS, GS, SS
CS, OS, ES, FS,GS
Other data references with effective address using
Base registers of:
EAX, EBX, ECX, EDX, ESI, EDI
EBP, ESP
Programming Interlace
2-13
Application Register Set
2.4.3
Instruction Pointer Register
The (extended) Instruction Pointer (EIP) register shown in Figure 2-3 on page
2-10 contains the offset into the current code segment of the next instruction
to be executed. The register is normally incremented with each instruction
execution unless implicitly modified through an interrupt, exception, or an
instruction that changes the sequential execution flow (e.g., jump, call).
2.4.4
Flag Word Register
The Flag Word register, EFLAGS, contains status information and controls
certain operations on the microprocessor. The lower 16 bits of this register are
referred to as the Flag register, FLAGS, that is used when executing 8086 or
80286 code. The flag bits are shown in Figure 2-6 and defined in Table 2-5.
Figure 2-6. EFLAGS Register
EFLAGS
(\,
/
FLAGS
(\,
/
2 2
4 3
3
1
1 1 1 1 1 1 1
8 7 6 5 4 3 2
I
10
PL
0 D I T S Z
P
A
C
F F F F F F 0 F 0 F 1 F
I
A
= arithmetic flag,
2-14
~
D = debug flag, S
o or 1 indicates reserved
\
1
0 9 8 7 6 5 4 3 2 1 0
I
A V
0 N
0 0 0 0 0 0 0 0 0 0 0 0 0 C M R
F
T
Alignment Check - - S
Virtual-8086 Mode - - S
Resume Flag - - . D
Nested Task Flag _.- S
I/O Privilege Level - - S
Overflow - - A
Direction Flag - - C
Interrupt Enable - - S
Trap Flag - - D
Sign Flag - - A
Zero Flag - - A
Auxiliary Carry - - S
Parity Flag - - A
Carry Flag - - A
\
= system flag,
C
= control flag
Application Register Set
Table 2-5. EFLAGS Definitions
Bit Position
Name
a
CF
Carry flag. CF is set when an operation results in a carry out of (addition) or borrow
into (subtraction) the most significant bit, cleared otherwise.
2
PF
Parity flag. PF is set when the low-order eight bits of the result contain an even
number of ones, cleared otherwise.
4
AF
Auxiliary carry flag. AF is set when an operation results in a carry out of (addition)
or borrow into (subtraction) bit position 3, cleared otherwise.
6
ZF
Zero flag. ZF is set if result is zero, cleared otherwise.
7
SF
Sign flag. SF is set equal to high-order bit of result (0 indicates positive, 1 indicates
negative).
8
TF
Trap enable flag. Once TF is set, a single-step interrupt occurs after the next
instruction completes execution. TF is cleared by the single-step interrupt.
9
IF
Interrupt enable flag. When IF is set, maskable interrupts (INTR input pin) are
acknowledged and serviced by the CPU.
10
DF
Direction flag. When cleared, DF causes string instructions to auto-increment
(default) the appropriate Index registers (ESI and/or EDI). Setting DF causes
auto-decrement of the Index registers.
11
OF
Overflow flag. Set if the operation resulted in a carry or borrow into the sign bit of
the result but did not result in a carry or borrow out of the high-order bit. Also set if
the operation resulted in a carry or borrow out of the high-order bit but did not result
in a carry or borrow into the sign bit of the result.
12, 13
10PL
I/O privilege level. While executing in protected mode, 10PL indicates the
maximum current privilege level (CPL) permitted to execute I/O instructions without
generating an exception 13 fault or consulting the I/O permission bit map. 10PL also
indicates the maximum CPL allowing alteration of the IF bit when new values are
popped into the EFLAGS register.
14
NT
Nested task. While executing in protected mode, NT indicates that the execution
of the current task is nested within another task.
16
RF
Resume flag. RF is used in conjunction with Debug register breakpoints. It is
checked at instruction boundaries before breakpoint exception processing. If set,
any debug fault is ignored on the next instruction.
17
VM
Virtual-8086 mode flag. If VM is set while in protected mode, the microprocessor
switches to virtual-8086 operation handling segment loads as the 8086 does, but
generating exception 13 faults on privileged opcodes. The VM flag can be set by
the IRET instruction (if current privilege level =0) or by task switches at any privilege
level.
18
AC
Alignment-check enable. In conjunction with the AM flag in CRO, the AC flag
determines whether or not misaligned accesses to memory cause a fault. If AC is
set, alignment faults are enabled.
Function
Programming Interface
2-15
System Register Set
2.5 System Register Set
The System register set (Figure 2-7) consists of registers not generally used
by application programmers. These registers are typically used by systemlevel programmers who generate operating systems and memory-management programs.
The Control registers control aspects of the microprocessor such as paging,
coprocessor functions, and segment protection. When paging is enabled and
a paging exception occurs, the Control registers retain the linear address of
the access that caused the exception.
The Descriptor Table registers and the Task register can also be referred to as
System Address or Memory Management registers. These registers consist
of two 48-bit and two 16-bit registers. These registers specify the location of
the data structures that control the segmentation used by the microprocessor.
Segmentation is a method of memory management.
The Configuration registers are used to control the clock-doubled operation
(for the TI486SXLC2 and T1486SXL2), on-chip cache operation, power-management features, and system-management mode. The clock-doubling,
cache, power-management, and SMM features can be enabled or disabled by
writing to these registers. Noncacheable areas of physical memory are also defined through the use of these registers.
The Debug registers provide debugging facilities for the microprocessor and
enable the use of data-access breakpoints and code-execution breakpoints.
The Test registers provide a mechanism to test the contents of both the on-chip
8K-byte cache and the translation lookaside buffer (TLB). The TLB is used as
a cache for translating linear addresses to physical addresses when paging
is enabled. In the following sections, the System register set is described in
greater detail.
2-16
System Register Set
Figure 2-7. System Register Set
31
o
16 15
I
CRO
Page-Fault Linear Address Register
CR2
Page-Directory Base Register
CR3
47
o
16 15
Base
Limit
GDTR
Base
Limit
IDTR
Selector
LDTR
Selector
TR
7
23
15
CCRO
CCRO
CCR1
CCR1
Address Region 1
ARR1
I
Address Region 2
ARR2
I
Address Region 3
ARR3
:
Address Region 4
ARR4
I
31
(TI486SXL only)
System Address
(Task Register)
Configuration
Registers
o
Linear Breakpoint Address 0
DRO
Linear Breakpoint Address 1
DR1
Linear Breakpoint Address 2
DR2
Linear Breakpoint Address 3
DR3
Breakpoint Status
DR6
Breakpoint Control
DR7
31
}
System Address
(Descriptor Table)
Registers
0
i
I
}
Control
Registers
Debug
Registers
0
Cache Test
TR3
Cache Test
TR4
Cache Test
TR5
TLB Test Control
TR6
TLB Test Status
TR7
Test
Registers
CCRO = Configuration Control 0
CCR1 = Configuration Control 1
Programming Interface
2-17
System Register Set
2.5.1
Control Registers
The Control registers (CRO, CR2, and CR3) are shown in Figure 2-8. The CRO
register contains system control flags that control operating modes and indicate the general state of the CPU. The lower 16 bits of CRO are referred to as
the machine status word (MSW). The CRO bit definitions are described in
Table 2-6. The reserved bits in CRO should not be modiJied.
Figure 2-8. Control Registers
12 11
31
0
Page-Directory Base Register (PDBR)
CR3
Page-Fault Linear Address
P
G
C
D
o
3
1
3
0
2
9
= Reserved
CR2
1
8
1
6
5
\-----------,V
S
E
M
3
2
T
0
4
M
P
P
E
CRG
0
/
MSW
When paging is enabled and a page fault is generated, the CR2 register retains
the 32-bit linear address of the address that caused the fault. CR3 contains the
20-bit base address of the page directory. The page directory must always be
aligned to a 4K-byte page boundary; therefore, the lower 12 bits of CR3 are
reserved.
When operating in protected mode, any program can read the Control registers. Privilege level 0 (most privileged) programs can modify the contents of
these registers.
2-18
System Register Set
Table 2-6. eRO Bit Definitions
Bit Position
Name
a
PE
MP
Function
Protected mode enable. Enables the segment-based protection mechanism. If PE =
1, protected mode is enabled. If PE = 0, the CPU operates in real mode, with
segment-based protection disabled, and addresses are formed as in an 8086-class
CPU.
Monitor processor extension. If MP = 1 and TS = 1, a WAIT instruction causes fault
7. The TS bit is set to 1 on task switches by the CPU. Floating-point instructions are
not affected by the state of the MP bit. The MP bit should be set to 1 during normal
operations.
2
EM
Emulate processor extension. If EM = 1, all floating-point instructions cause a fault 7.
3
TS
Task switched. Set whenever a task-switch operation is performed. Execution of a
floating-point instruction with TS = 1 causes a device-not-available (DNA) fault. If
MP = 1 and TS = 1, a WAIT instruction also causes a DNA fault.
. Reserved. Do not modify.
4
5
a
16
WP
Write protect. Protects read-only pages from supervisor write access. The 386-type
CPU allows a read-only page to be written from privilege levels 0-2. The TI486SXL(C)
CPU is compatible with the 386-type CPU when WP = O. WP = 1 forces a fault on a
write to a read-only page from any privilege level.
18
AM
Alignment-check mask. If AM = 1 , the AC bit in the EFLAGS register is unmasked and
allowed to enable alignment-check faults. Setting AM = a prevents AC faults from
occurring.
29
a
30
CD
Cache disable. If CD = 1, no further cache fills occur. However, data already present
in the cache continues to be used if the requested address hits in the cache. The cache
must also be invalidated to completely disable any cache activity.
31
PG
Paging enable. If PG = 1 and protected mode is enabled (PE
2.5.2
Reserved. Do not modify.
Reserved. Do not modify.
= 1), paging is enabled.
Descriptor-Table Registers and Descriptors
The Global-, Interrupt-, and Local-Oescriptor-Table registers (GOTR, IOTR
and LOTR) are used 10 specify the location of the data structures that control
segmented memory management.
2.5.2.1
Descriptor-Table (System-Address) Registers
The GOTR, IOTR, and LOTR, shown in Figure 2-9, are loaded using the
LGOT, L10T, and LLOT instructions, respectively. The values of these r~gisters
are stored using the corresponding store instructions. The GOTR and IOTR
load instructions are privileged instructions when operating in protected mode.
The LOTR can be accessed only in protected mode.
The Global-Oescriptor-Table register (GOTR) holds a 32-bit base address and
16-bit limit for the global-descriptor table (GOT). The GOT is an array of up to
8192 8-byte descriptors. When a Segment register is loaded from memory, the
TI bit in the segment selector chooses either the GOT or the local-descriptor
Programming Interface
2-19
System Register Set
table (LOT) to locate a descriptor. If TI = 0, the index portion of the selector is
used to locate a given descriptor within the GOT table. The contents of the
GOTR are completely visible to the programmer. The first descriptor in the
GOT (location 0) is not used by the CPU and is referred to as the null descriptor.
If the GOTR is loaded while operating in 16-bit operand mode, the microprocessor accesses a 32-bit base value but the upper 8 bits are ignored, resulting
in a 24-bit base address.
The Interrupt-Oescriptor-Table register (IOTR) holds a 32-bit base address
and 16-bit limit for the interrupt-descriptor table (lOT). The lOT is an array of
256 8-byte interrupt descriptors, each of which is used to point to an interrupt
service routine. Every interrupt that can occur in the system must have an
associated entry in the lOT. The contents of the IOTR are completely visible
to the programmer.
Figure 2-9. Descriptor-Table (System-Address) Registers
o
16 15
48
Base Address
Limit
GOTR
Base Address
Limit
IOTR
Selector
LOTR
The Local-Oescriptor-Table register (LOTR) holds a 16-bit selector for the local-descriptor table (LOT). The LOT is an array of up to 8192 8-byte descriptors. When the LOTR is loaded, the LOTR selector indexes an LOT descriptor
that must reside in the global-descriptor table (GOT). The contents of the selected descriptor are cached on-chip in the hidden portion of the LOTR. The
CPU does not access the GOT again until the LOTR is reloaded. If the LOT
description is modified in memory in the GOT, the LOTR must be reloaded to
update the hidden portion of the LOTR.
When a Segment register is loaded from memory, the TI bit in the segment selector chooses either the GOT or the LOT to locate a segment descriptor. If
TI = 1 , the index portion of the selector is used to locate a given descriptor within the LOT. Each task in the system may be given its own LOT, managed by
the operating system. The LOTs provide a method for isolating a given task's
segments from other tasks in the system.
2-20
System Register Set
2.5.2.2 Descriptors
The three types of descriptors are:
o
Application-segment descriptors that define code, data, and stack segments
o
o
System-segment descriptors that define an LOT segment or a TSS
Gate descriptors that define task gates, interrupt gates, trap gates, and
call gates
Application-segment descriptors can be located in either the LOT or GOT. System-segment descriptors can be located only in the GOT. Oependent on the
gate type, gate descriptors can be located in either the GOT, LOT, or lOT.
Figure 2-10 illustrates the descriptor format for both application-segment descriptors and system-segment descriptors. Table 2-7 lists the corresponding
bit definitions.
Figure 2-10. Application- and System-Segment Descriptors
31
24 23 22 21
20 19
16 15 14 13 12 11
A
Base 31-24
G
0
0
Base 15-0
V
L
Limit 19-16
P
DPL
0
T
8
o
7
Type
Base 23-16
+4
Limit 15-0
Programming Interface
2-21
System Register Set
Table 2-7. Segment Descriptor Bit Definitions
Bit
Position
Memory
Offset
Name
Description
31-24
7-0
31-16
+4
+4
+0
Base 31-24 Segment base address. A 32-bit linear address that points to the beBase 23-16 ginning of the segment.
Base15-0
19-16
15-0
+4
+0
Limit 19-16
Limit 15-0
Segment limit. In real mode, segment limit is always 64K bytes
(OFFFFh).
23
+4
G
Limit granularity:
0= byte granularity
1 = 4K-byte (page) granularity
22
+4
D
Default length for operands and effective addresses. Valid for code
and stack segments only:
0= 16 bit
1 = 32 bit
20
+4
AVL
Segment available
15
+4
P
Segment present
14-13
+4
DPL
Descriptor privilege level
12
+4
DT
Descriptor type:
0= system
1 = application
11-8
+4
Type
11
+4
E
10
+4
C/D
9
+4
RIW
8
+4
A
Segment type. System descriptor (DT = 0):
0010 = LDT descriptor
1001 = TSS descriptor, task not busy
1011 = TSS descriptor, task busy
Application descriptor (DT = 1):
0= data
1 = executable
If E is 0:
o = expand up, limit is upper bound of segment
1 = expand down, limit is lower bound of segment
If E is 1:
o = nonconforming
1 = conforming (runs at privilege level of calling procedure)
If E is 0:
o = nonreadable
1 = readable
If E is 1:
o = nonwritable
1 = writable
o = not accessed
1 = accessed
Gate descriptors provide protection for executable segments operating at different privilege levels. Figure 2-11 illustrates the format for gate descriptors
and Table 2-8 lists the corresponding bit definitions.
Task-gate descriptors are used to switch the CPU's context during a task
switch. The selector portion of the task-gate descriptor locates a task-state
segment. Task-gate descriptors can be located in the GOT, LOT, or lOT.
2-22
System Register Set
Figure 2-11. Gate Descriptor
31
8
16 15 14 13 12 11
Offset 31 -1 6
P
DPL
0
Type
Selector 15-0
o
7
0
0
0
Parameters
Offset 15-0
+4
+0
Table 2-8. Gate Descriptor Bit Definitions
Bit
Position
Memory
Offset
Name
Description
Offset used during a call gate to calculate the branch target
31-16
15-0
+4
+0
Offset 31-1 6
Offset 15-0
31-16
+0
Selector 15-0 Segment selector used during a call gate to calculate the branch target
15
+4
P
Segment present
14-13
+4
DPL
Descriptor privilege level
11-8
+4
Type
Segment type:
0100 = 16-bit call gate
0101 = tack gate
0110= 16-bit interrupt gate
0111 = 16-bit trap gate
1100 = 32-bit call gate
1110 = 32-bit interrupt gate
1111 = 32-bit trap gate
4-0
+4
Parameters
Number of 32-bit parameters to copy from the caller's stack to the
called procedure's stack
Interrupt-gate descriptors are used to enter a hardware interrupt service routine. Trap-gate descriptors are used to enter exceptions or software interrupt
service routines. Trap-gate and interrupt-gate descriptors can be located only
in the IDT.
Call-gate descriptors are used to enter a procedure (subroutine) that executes
at the same or a more-privileged level. A call-gate descriptor primarily defines
the procedure entry point and the procedure's privilege level.
2.5.3
Task Register
The Task register (TR) holds a 16-bit selector for the current task-state segment (TSS) table as shown in Figure 2-12. The TR is loaded and stored via
the LTR and STR instructions, respectively. The TR can be accessed only during protected mode and can be loaded only when the privilege level is 0 (most
privileged).
Figure 2-12. Task (System-Address) Register
o
15
Selector
Programming Interface
2-23
System Register Set
When the TR is loaded, the TR selector field indexes a TSS descriptor that
must reside in the global-descriptor table (GDT). The contents of the selected
descriptor are cached on-chip in the hidden portion of the TR.
During task switching, the processor saves the current CPU state in the TSS
before starting a new task. The TR points to the current TSS. The TSS can be
either a 286-type TSS (16-bit) or a 386/486-type TSS (32-bit) as shown in
Figure 2-13 and Figure 2-14. An I/O permission bit map is referenced in the
32-bit TSS by the I/O map base address.
Figure 2-13. 32-Bit Task-State Segment (TSS) Table
31
o
16 15
I/O Map Base Address
EOI
ESI
+40h
EBP
+3Ch
+38h
+34h
+30h
+2Ch
+28h
+24h
+20h
+1Ch
0 0 0 0 000000000 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
o0
o0
o0
o0
o0
o0
Selector For Task's LOT
0 0 0
GS
0 0 0
FS
0 0 0
OS
0 0 0
0 0 0
ss
cs
0 0 0
ES
ESP
EBX
EOX
ECX
EAX
EFLAGS
EIP
CR3
0 0 0 0 0 0 0 0 0 0 0
o0 o
0 0
ESP for CPL
0 0 0 0 0 0 0 0 0 0 0
o0
000
0 0 0 0 0 0 0 0 0 0 0
o0
000
0 0 0 0 0 0 0 0 0 0 0
o0
000
ESP for CPL
SS for CPL
=2
SS for CPL
=1
SS for CPL
=0
=2
=1
ESP for CPL = 0
0= Reserved
2-24
o
+64h
+60h
+5Ch
+58h
+54h
+50h
+4Ch
+48h
+44h
000 0 0 0 0 0 0 0 0 0 0
Back Link (Old TSS Selector)
01 T
+18h
+14h
+10h
+Ch
+8h
+4h
+Oh
System Register Set
Figure 2-14. 16-Bit Task-State Segment (TSS) Table
Selector For Task's LOT
+2Ah
OS
+28h
SS
+26h
CS
+24h
ES
+22h
DI
+20h
81
+1Eh
BP
+1Ch
SP
+1Ah
BX
+18h
OX
+16h
CX
+14h
AX
+12h
FLAGS
+10h
IP
+Eh
SP For Privilege Level 2
+Ch
SS For Privilege Level 2
+Ah
SP For Privilege Level1
+8h
SS For Privilege Level 1
+6h
SP For Privilege Level 0
+4h
SS For Privilege Level 0
+2h
Back Link (Old TSS Selector)
+Oh
Programming Interface
2-25
System Register Set
2.5.4
Configuration Registers
The TI486SXL(C) family microprocessors contain six registers that do not exist on other 80x86 microprocessors. These registers include two Configuration
Control registers (CCRO and CCR1) and four Address Region registers (ARR1
through ARR4) as listed in Table 2-9 and Table 2-10. The CCR and ARR registers exist in liD memory space and are selected by a register index number
via I/O port 22h. I/O port 23h is used for data transfer.
Table 2-9. TI486SXLC Configuration Control Registers
Register Name
Register Index
Configuration Control 0 (CCRO)
COh
8
Configuration Control 1 (CCR1)
C1h
8
Address Region 1 (ARR1)
C5h-C6h
16
Address Region 2 (ARR2)
C8h-C9h
16
Address Region 3 (ARR3)
CBh-CCh
16
Address Region 4 (ARR4)
CEh-CFh
16
Note:
Width
The following register index numbers are reserved: C2h, C3h, C4h, C7h, CAh, CDh, and
DOh through FFh.
Table 2-10. TI486SXL Configuration Control Registers
Register Name
Register Index
Configuration Control 0 (CCRO)
COh
8
Configuration Control 1 (CCR1)
C1h
8
Address Region 1 (ARR1)
C4h-C6h
24
Address Region 2 (ARR2)
C7h-C9h
24
Address Region 3 (ARR3)
CAh-CCh
24
Address Region 4 (ARR4)
CDh-CFh
24
Note:
Width
The following register index numbers are reserved: C2h, C3h, and DOh through FFh.
Each liD port 23h data transfer must be preceded by an liD port 22h register
selection, otherwise the second and later liD port 23h operations are directed
off-chip and produce external 110 cycles. If the register index number is outside
the COh-CFh range, external 110 cycles also occur.
2-26
System Register Set
The CCRO register (Table 2-11) determines if the 64K-byte memory area on
1M-byte boundaries and the 640K-byte to 1M-byte area are cacheable. This
register also enables certain functions associated with cache control, suspend
mode, and the clock-doubled mode.
Table 2-11. CCRO Bit Definitions
Bit Position
Register Index
°
NCO
Noncacheable 1M-byte boundaries:
If 1, sets the first 64K bytes at each 1M-byte boundary as noncacheable.
NC1
Noncacheable upper memory area:
If 1, sets 640K-byte to 1M-byte memory region noncacheable.
Description
2
A20M
Enable A20M# pin:
If 1, enables A20M#; otherwise pin is ignored.
3
KEN
Enable KEN# pin:
If 1, enables KEN#; otherwise pin is ignored.
4
FLUSH
5
BARB
Enable cache flush during hold:
If 1, enables flushing of the internal cache when hold state is entered.
6
CKD
Enable clock double:
If 1, enables clock-double mode.
If 0, disables clock-double mode.
7
SUS
Enable suspend pins:
If 1, enables SUSP# and SUSPA#.
If 0, SUSPA# floats; SUSP# is ignored.
Enable FLUSH# pin:
If 1, enables FLUSH#; otherwise pin is ignored.
Programming Interface
2-27
System Register Set
The CCR1 register (Table 2-12) is used to set up internal cache operation and
system-management mode (SMM). The ARR registers (Figure 2-15 on page
2-29, Figure 2-16 on page 2-30, and Table 2-9 and Table 2-10 on page 2-26)
are used to define the location and size of the memory regions associated with
the internal cache. ARR1-ARR3 define three write-protected or noncacheable memory regions as designated by CCR1 bits WP1-WP3. ARR4 defines
an SMM memory space or noncacheable memory region as defined by CCR1
bit SM4. Other CCR1 bits enable SMM pins and control SMM memory access.
The SMAC bit allows access to defined SMM space while not in an SMI service
routine. The MMAC bit allows access to main memory that overlaps with SMM
memory while in an SMI service routine for data access only.
Table 2-12. CCR 1 Bit Definitions
Bit Position
°
2-28
Register Index
Description
Reserved
SMI
Enable SMM pins:
If 1, SMI# and SMADS# are enabled.
If 0, SMI# is ignored and SMADS# floats.
2
SMAC
System management memory access:
If 1, noncode-segment prefixed data reads and writes to addresses within
the SMM memory space cause external bus cycles to be issued with
SMADS# active. SMI# is ignored.
If 0, no effect on access.
3
MMAC
Main memory access:
If 1 , all noncode-segment prefixed data reads and writes which occur within
an SMI service routine (or when SMAC = 1) access main memory instead
of SMM memory space.
If 0, no effect on access.
4
WP1
Access region 1 control:
If 1, region 1 is write protected and cacheable.
If 0, region 1 is noncacheable.
5
WP2
Access region 2 control:
If 1, region 2 is write protected and cacheable.
If 0, region 2 is noncacheable.
6
WP3
Access region 3 control:
If 1, region 3 is write protected and cacheable.
If 0, region 3 is noncacheable.
7
SM4
Access region 4 control:
If 1, region 4 is noncacheable SMM memory space.
If 0, region 4 is noncacheable. SMI# input ignored.
System Register Set
The ARR registers define address regions using a starting address and a block
size. The noncacheable region block sizes range from 4K bytes to 4G bytes
(Table 2-13). A block size of zero disables the address region. The starting address of the address region must be on a block size boundary. For example,
a 128K-byte block is allowed to have a starting address of OK bytes, 128K
bytes, 256K bytes, etc. The SMM memory region size is restricted to a maximum of 16M bytes. The block size must be defined for SMI# to be recognized.
Figure 2-15. TI486SXLC Address Region Registers (ARR1-ARR4)
Register Index
= C5h
Register Index
= C6h'
r__-----------A~----------__'r__----------~A~----------__,
7
I
A23
~tarting
0 7
Address
:
A 16 . A 15
4 3
I
0
Size
A 12_
I
ARR1
I
ARR2
I
ARR3
I
ARR4
.
Address Region 1
Register Index
= C8h
Register Index
= C9h
r__----------~A~----------__'r__-----------A~----------__,
7
0 7
I
A23
~tarting
Address
:
A16 . A15
4 3
A12
I
0
Size
.
Address Region 2
Register Index
= CBh
Register Index
= CCh
r__-----------A-----------__'r__----------~A~----------__,
7
0 7
Starting Address
I
A23
:
A16 . A15
4 3
A12
I
0
Size
.
Address Region 3
Register Index
= CEh
= CFh
'r__-----------A~----------
-----------A-----------__
r__
7
0
I
Starting Address
A23
Register Index
7
:
A16 . A15
4 3
A12
I
__,
Sizet
0
.
Address Region 4
tARR4 (Size) must be 4K bytes to 16M bytes if ARR4 is defined as SMM memory space.
Programming Interface
2-29
System Register Set
Figure 2-16. TI486SXL Address Region Registers (ARR1-ARR4)
Register Index = C4h
Register Index = C5h
A
A
7
o'(
,
A31
A24, A23
(
7
Register Index = C6h
A
o'(
,
7
,
0
43
Size
Starting Address
ARR1
A12
A16,A15
Address Region 1
Register Index = C7h
Register Index = C8h
A
A
7
o'(
,
A31
A24. A23
(
7
Register Index = C9h
A
o'(,
7
,
0
43
Size
Starting Address
ARR2
A12
A16.A15
Address Region 2
Register Index = CAh
(
A
7
Register Index = CBh
o'(7
A
Register Index = CCh
A
o'(
7
I
I
Starting Address
A31
,
0
43
A24.A23
Size
A12
A16.A15
ARR3
Address Region 3
Register Index = CDh
A
Register Index = CEh
7
o'(
,7
A31
A24,A23
(
A
Register Index = CFh
A.
o'(,
7
43
Sizet
Starting Address
A12
A16,A15
Address Region 4
t ARR4 (Size) must be 4K bytes to 16M bytes if ARR4 is defined as SMM memory space.
Table 2-13.ARR1-ARR4 Block Size Field
Bits 3-0
2-30
Block Size
,
0
Bits 3-0
Block Size
Oh
Disabled
8h
512K bytes
1h
4K bytes
9h
1M bytes
2h
8K bytes
Ah
2M bytes
3h
16K bytes
Bh
4M bytes
4h
32K bytes
Ch
8M bytes
5h
64K bytes
Dh
16M bytes
6h
128K bytes
Eh
32M bytes
7h
256K bytes
Fh
4G bytes
ARR4
System Register Set
2.5.5
Debug Registers
Six Debug registers (DRO-DR3, DRS, and DR?), shown in Figure 2-1? and
Figure 2-18, support debugging on the TI48SSXL(C) family of microprocessors. Memory addresses loaded in the Debug registers, referred to as breakpoints, generate a debug exception when a memory access of the specified
type occurs to the specified address. A breakpoint can be specified for a particular kind of memory access such as a read or a write. Code and data breakpoints can also be set allowing debug exceptions to occur whenever a given
data access (read or write) or code access (execute) occurs. The size of the
debug target can be set to 1, 2, or 4 bytes. The Debug registers are accessed
via MOV instructions that can be executed only at privilege level
o.
Figure 2-17. TI486SXLC Debug Registers
332222222222111111111
1098765432109876543209876543210
I I I I I I I
LEN RIW LEN
332
o
0 0 0 000
RIW
2
o
LEN
1
0
o
RIW
1
0
o
LEN RIW
00
0
0
o
0
o
0
BIB
T S
G
D
0
0011~1~1~1~ I~I~
o1 1
1
1 1
1 1
G L G L
1 1
0
0 DR7
1 B B B B DR6
3 2 1 0
Reserved
DR5
Reserved
DR4
Breakpoint 3 Linear Address
DR3
Breakpoint 2 Linear Address
DR2
Breakpoint 1 Linear Address
DR1
Breakpoint 0 Linear Address
DRO
All bits marked as 0 or 1 are reserved and should not be modified.
The Debug Breakpoint (n) Linear Address registers DRO-DR3 each contain
the linear address for one of four possible breakpoints. Each breakpoint is further specified by bits in the Debug Control register (DR?). For each breakpoint
address in DRO-DR3, there are corresponding fields L, RIW, and LEN in DR?
that specify the type of memory access associated with the breakpoint.
The RIW field can be used to specify execution as well as data-access breakpoints. Instruction-execution and data-access breakpoints are always taken
before execution of the instruction that matches the breakpoint.
The Debug Status register (DRS) reflects conditions that were in effect at the
time the debug exception occurred. The contents of the DRS register are not
automatically cleared by the processor after a debug exception occurs and
therefore should be cleared by software at the appropriate time. Table 2-14
lists the field definitions for the DRS and DR? registers.
Programming Interface
2-31
System Register Set
Figure 2-18. TI486SXL Debug Registers
332222222222111111111
1098765432109876543209876543210
LEN
3
RIW
3
o
o
0
0
LEN
2
o
0
RIW
2
o
0
LEN
1
o
0
R!W
1
0 0
LEN RIW
0
0
o
0
o
0
o0
G
G L G L
D 000 E E 3 3
B B
1 011
T S
1 1
1
GIL
2 2
1 1
G L
1 1
G L
0 0 DR7
1 B B B B DR6
3 2 1 0
Breakpoint 3 Linear Address
DR3
Breakpoint 2 Linear Address
DR2
Breakpoint 1 Linear Address
DR1
Breakpoint 0 Linear Address
DRO
All bits marked as 0 or 1 are reserved and should not be modified.
Table 2-14. DR6 and DR7 Field Definitions
Number
Of Bits
Register
Field
DR6
Bi
Bi is set by the processor if the conditions described by DRi, RIWi, and
LENi occurred when the debug exception occurred, even if the breakpoint
is not enabled via the Gi or Li bits.
BT
BT is set by the processor before entering the debug handler if a task
switch has occurred to a task with the T bit in the TSS set.
BS
BS is set by the processor if the debug exception was triggered by the
single-step-execution mode (TF flag in EFLAGS set).
DR7
Description
RlWi
2
Applies to the DRi Breakpoint (n) Linear Address register:
00 - Break on instruction execution only
01 - Break on data writes only
10 - Not used
11 - Break on data reads or writes
LENi
2
Applies to the DRi Breakpoint (n) Linear Address register:
00 - One-byte length
01 - Two-byte length
10 - Not used
11 - Four-byte length
Gi
If set to 1, breakpoint in DRi is globally enabled for all tasks and is not
cleared by the processor as the result of a task switch.
Li
If set to 1, breakpoint in DRi is locally enabled for the current task and is
cleared by the processor as the result of a task switch.
GD
Global disable of Debug register access. GD bit is cleared whenever a
debug exception occurs.
Code execution breakpoints can also be generated by placing the breakpoint
instruction (lNT3) at the location where control is to be regained. The single-
2-32
. ' V..... ,HI1I
Hp.{ll.c:m~r
Set
step feature can be enabled by setting the TF flag in the EFLAGS register. This
causes the processor to perform a debug exception after the execution of
every instruction.
2.5.6
Test Registers
The five Test registers, shown in Figure 2-19, are used in testing the CPU's
translation look-aside buffer (TLB) and on-chip cache. TR6 and TR7 are used
for TLB testing, and TR3-TR5 are used for cache testing. Table 2-15 and
Table 2-16 list the bit definitions for the TR6 and TR7 registers.
Figure 2-19. Test Registers
TLB Physical Address
31
TR7
12
TLB Linear Address
31
11
V
12
11
10
I
D
10
4
3
2
0
I D# IU I U# I R IR# I 0
0
0
oI C
3
2
0
9
9
8
8
7
7
6
6
5
5
4
Set Selection
31
12
11
10
9
8
7
TR5
6 5 4
,...- Valid
--....
0
Cache Tag Addresst
31
24
I TR6
TR4
12
11
9
8
7
6
5
4
3
2
0
I TR3
Cache Data
31
0
= Reserved
t
Bits 31-24 are reserved on the TI486SXLC.
2.5.6.1
TLB Test Registers
The microprocessor TLB is a four-way set-associative memory with eight entries per set. Each TLB entry consists of a 24-bit tag and 20-bit data. The 24-bit
tag represents the high-order 20 bits of the linear address, a valid bit, and three
attribute bits. The 20-bit data portion represents the upper 20 bits of the physical address that corresponds to the linear address.
The TLB Test-Control register (TR6) contains a command bit, the upper 20 bits
of a linear address, a valid bit, and the attribute bits used in the test operation.
The contents of TR6 are used to create the 24-bit TLB tag during both write
and read (TLB lookup) test operations. The command bit defines whether the
test operation is a read or a write.
The TLB Test-Data register (TR7) contains the upper 20 bits of the physical
address (TLB data field), two LRU bits, and a control bit. During TLB write operations, the physical address in TR7 is written into the TLB entry selected by
Programming Interface
2-33
System Register Set
the contents of TR6. During TLB lookup operations, the TLB data selected by
the contents of TR6 is loaded into TR7.
Table 2-15. TR6 and TR7 Bit Definitions
Register
Name
Bit
Position
TR6
31-12
Linear address
TLB lookup: The TLB is interrogated per this address. If one and only one match
occurs in the TLB, the rest of the fields in TR6 and TR7 are updated per the
matching TLB entry.
TLB write: A TLB entry is allocated to this linear address.
11
Valid bit (V)
TLB lookup: Always set to 1
TLB write: If set, indicates that the TLB entry contains valid data. If clear, target entry
is invalidated.
10-9
Dirty attribute bit and its complement (D, D#). (Refer to Table 2-16.)
8-7
User/supervisor attribute bit and its complement (U, U#). (Refer to Table 2-16.)
6-5
Read/write attribute bit and its complement (R, R#). (Refer to Table 2-16.)
o
Command bit (C)
If 0, TLB write
If 1, TLB lookup
31-12
Physical address
TLB lookup: data field from the TLB
TLB write: data field written into the TLB
11
Page-level cache disable bit (PCD). Corresponds to the PCD bit of a page-table
entry
10
Page-level cache write-through bit (PWT). Corresponds to the PWT bit of a
page-table entry
9-7
LRU bits
TLB lookup: LRU bits associated with the TLB entry prior to the TLB lookup
TLB write: ignored
4
PL bit
TLB lookup: If 1, read hit occurred. If 0, read miss occurred.
TLB write: If 1, REP field is used to select the set. If 0, the pseudo-LRU replacement
algorithm is used to select the set.
3-2
Set selection (REP)
TLB lookup: If PL is 1, set in which the tag was found. If PL is 0, undefined data
TLB write: If PL is 1, selects one of the four sets for replacement. If PL is 0, ignored
TR7
Description
Table 2-16. TR6 Attribute Bit Pairs
2-34
Bit (B)
Bit Complement (B#)
Effect on TLB Lookup
Effect on TLB Write
0
0
1
1
0
1
0
1
Do not match
Match if the bit is 0
Match if the bit is 1
Match if the bit is 1 or 0
Undefined
Clear the bit
Set the bit
Undefined
System Register Set
2.5.6.2
Cache Test Registers
The microprocessor on-chip cache is 8K bytes in size and is configured as twoway set associative.
The cache memory is physically split into two 4K-byte blocks each containing
1024 lines. Associated with each 4K-byte block are 256 twenty-bit tags implying there are four lines in a block that are associated with the same tag. These
four lines are consecutive at 16-byte boundaries. For each byte in a line, there
is a valid bit indicating which of the four data bytes actually contain valid data.
In addition, there is a valid bit associated with each block of four lines, which
when reset, indicates that none of the 16-bytes in the four lines of that block
contain valid data.
The LRU bit indicates which of the two sets was more recently accessed. The
LRU bit is uninitialized for a given set after RESET or FLUSH#. The set's LRU
bit will remain uninitialized until the first read allocation to that set occurs. The
first cache allocation to a given set will be to way 1 and the LRU bit will than
be equal to 1. In a similar manner, the tag and valid bits of a given set and way
are uninitialized until a read allocation occurs and the block valid bit is set.
The microprocessor contains three Test registers that allow testing of its internal cache. Using these registers, cache test writes and reads can be performed. Cache test writes cause the data in TR3 to be written to the selected
wayand entry in the cache. Cache test reads allow inspection of the data, valid
bits, and the LRU bit for the cache entry. For data to be written to the allocated
entry, the valid bits for the entry must be set prior to the write of the data. Bit
definitions for the cache Test registers are shown in Table 2-17.
Programming Interface
2-35
System Register Set
Table 2-17. TR3- TR5 Bit Definitions
Register Name
Bit Position
Description
TR3
31-0
Cache data
Cache read: data accessed from the cache
Cache write: to be written into the cache
TR4
31-12
Tag address
Cache read: tag address from which data is read
Cache write: data written into the tag address of the selected set
7
LRU
Cache read: the LRU bit associated with the cache set
Cache write: ignored
6-3
Valid bits
Cache read: four valid bits for the accessed line, (one bit per byte)
Cache write: valid bits written into the line
2
Block valid bit
Cache read: the block valid bit associated with the cache way
Cache write: the block valid bit written into the selected way
If 0, block is invalid (all 16 bytes are invalid).
If 1, block is valid (one or more bytes may be valid in 16-byte line).
12
Way selection
If 0, way 0 is selected.
If 1, way 1 is selected.
11 -4
Set selection. Selects one of 256 sets
3-2
Line selection. Selects one of four lines
1-0
Control
If 00,
If 01,
If 10,
If 11,
TR5
2-36
bits. These bits control reading or writing the cache.
ignored
cache write
cache read
cache invalidate
2.6 Memory Address Space
The TI486SXLC directly addresses up to 16M bytes of physical memory and
the TI486SXL directly addresses up to 4G bytes of physical memory. Memory
address space is accessed as bytes, words (16 bits), ordoublewords (32 bits).
Words and doublewords are stored in consecutive memory bytes with the loworder byte located in the lowest address. The physical address of a word or
doubleword is the byte address of the low-order byte.
With the TI486SXL(C) microprocessor family, memory can be addressed using nine different addressing modes. These addressing modes are used to calculate an offset address often referred to as an effective address. Depending
on the operating mode of the CPU, the offset is then combined using memorymanagement mechanisms to create and address a physical memory location.
Memory-management mechanisms on the microprocessor consist of segmentation and paging. Segmentation allows each program to use several independent, protected address spaces. Paging supports a memory subsystem
that simulates a large address space using a small amount of RAM and disk
storage for physical memory. Either or both of these mechanisms can be used
for management of the microprocessor memory address space.
2.6.1
Offset Mechanism
The offset mechanism computes an offset (effective) address by summing up
to three values: the base, the index, and the displacement. The base, if present, is the value in one of eight 32-bit General registers at the time of the execution of the instruction. The index, like the base, is a value that is determined
from one of the 32-bit General registers (except the ESP register) when the
instruction is executed. The index differs from the base in that the index is first
multiplied by a scale factor of 1, 2, 4 or 8 before the summation is made. The
third component of the memory address calculation is the displacement which
is a value of up to 32 bits in length supplied as part of the instruction.
Figure 2-20 illustrates the calculation of the offset address.
Figure 2-20. Offset Address Calculation
Index
Base
Displacement
Offset Address
(Effective Address)
Programming Interface
2-37
Memory Address Space
Nine valid combinations of the base, index, scale factor, and displacement can
be used with the TI486SXL(C) family instruction set. These combinations are
listed in Table 2-18. The base and index both refer to contents of a register as
indicated by [Base] and [Index].
Table 2-18. Memory Addressing Modes
Addressing Mode
Base
Index
Scale
Factor (SF)
Displacement
(DP)
Direct
X
Register indirect
X
Based
X
Index
X
Scaled index
X
Based index
X
X
Based scaled
index
X
X
Based index with
displacement
X
X
Based scaled index
with displacement
X
X
2.6.2
X
OA=DP
OA
=
X
OA
= [BASE] + DP
X
OA = [INDEX] + DP
X
OA
= ([INDEX] * SF) + DP
OA
= [BASE] + [INDEX]
[BASE]
OA = [BASE] + ([INDEX] * SF)
X
X
Offset Address (OA) Calculation
X
OA = [BASE] + [INDEX] + DP
X
OA
= [BASE] + ([INDEX] * SF) + DP
Real-Mode Memory Addressing
In real-mode operation, the TI486SXL(C) family of microprocessors address
only the lowest 1M bytes (2 20 ) of memory. To calculate a physical memory address, the 16-bit segment base address located in the selected Segment register is shifted left by four bits and then the 16-bit offset address is added. For
the TI486SXLC, the resulting 20-bit address is then extended with four zeros
in the upper address bits to create the 24-bit physical address. For the
TI486SXL, the resulting 20-bit address is then extended with 12 zeros in the
upper address bits to create the 32-bit physical address. Figure 2-21 illustrates the real-mode address calculation. Address offsets larger than 65,535
cause a general protection fault. Physical addresses beyond 1M byte cause
a segment-limit-overrun exception.
Figure 2-21. Real-Mode Address Calculation
Offset Mechanism
Offset Address
1-------------,
Linear Address = Physical Address
Selected Segment
Register
2-38
1--_---1
x16
Memory Address Space
The addition of the base address and the offset address can result in a carry.
Therefore, the resulting address can actually contain up to 21 significant address bits that address memory in the first 64K bytes above 1M byte.
2.6.3
Protected-Mode Memory Addressing
In protected mode, three mechanisms calculate a physical memory address.
o
o
o
Offset mechanism that produces the offset or effective address as in real
mode
Selector mechanism that produces the base address
Optional paging mechanism that translates a linear address to the physical memory address
The offset and base address are added together to produce the linear address
as illustrated in Figure 2-22. If paging is not used, the linear address is used
as the physical memory address. If paging is enabled, the paging mechanism
is used to translate the linear address into the physical address. The offset
mechanism is described earlier in this section and applies to both the real and
protected modes. The selector and paging mechanisms are described in the
following paragraphs.
Figure 2-22. Protected-Mode Address Calculation
Offset Mechanism
Offset Address
Linear Address
Selector Mechanism
2.6.3.1
Optional
Paging Mechanism
Physical
Memory
Address
Base Address
1---------------'
Selector Mechanism
Memory is divided into an arbitrary number of segments, each containing usually much less than the 2 32 -byte (4G-byte) maximum.
The six Segment registers (CS, OS, SS, ES, FS and GS) each contain a 16-bit
selector that is used when the register is loaded to locate a segment descriptor
in either the global-descriptor table (GOT) or the local-descriptor table (LOT).
The segment descriptor defines the base address, limit, and attributes of the
selected segment and is cached on the microprocessor as a result of loading
the selector. The cached descriptor contents are not visible to the programmer.
When a memory reference occurs in protected mode, the linear address is
generated by adding the segment base address in the hidden portion of the
Segment register to the offset address. If paging is not enabled, this linear address is used as the physical memory address. Figure 2-23 illustrates the operation of the selector mechanism.
Programming Interface
2-39
Memory Address
Spac~
Figure 2-23. Selector Mechanism
I---1----...,.---J
JO}
-
15
Selector
Load
...
Index
(Accessed
Segment
Register)
Selector
Segment
Descriptor
Segment
Descriptor
Global-Descriptor Table
Local-Descriptor Table
Memory
Reference
2.6.3.2
Til RPL
......
Descriptor
Cache
1----~ Base Address
Paging Mechanism
The paging mechanism supports a memory subsystem that simulates a large
address space with a small amount of RAM and disk storage. The paging
mechanism either translates a linear address to its corresponding physical address or generates an exception if the required page is not currently present
in RAM. When the operating system services the exception, the required page
is loaded into memory and the instruction is then restarted. Pages are always
4K bytes in size and are aligned to 4K-byte boundaries.
A page is addressed by using two levels of tables as illustrated in Figure 2-24.
The upper 10 bits of the 32-bit linear address are used to locate an entry in the
page-directory table. The page-directory table acts as a master index of up to
1K individual 32-bit pointers to second-level page tables. The selected entry
in the page-directory table, referred to as the directory-table entry, identifies
the starting address of the second-level page table. The page-directory table
itself is a page and is therefore aligned to a 4K-byte boundary. The physical
address of the current page directory is stored in the CR3 Control register, also
referred to as the Page-Directory Base register (PDBR).
2-40
Figure 2-24. Paging Mechanism
Linear Address
22 21
31
Directory-Table Index
(DTI)
o
12 11
Page-Table Index
(PTI)
Directory Table
Page-Frame Offset
(PFO)
Page Table
Page Frame
4KB
4 KB
4 KB
~
~
~
8
DTE
Physical Data
-
PTE
r---
o
....
...
o
o
Control Register
Bits 12-21 of the 32-bit linear address, referred to as the page-table index, locate a 32-bit entry in the second-level page table. This page-table entry (PTE)
contains the base address of the desired page frame. The second-level pagetable addresses up to 1K individual page frames. A second-level page table
is 4K bytes in size and is itself a page. The lower 12 bits of the 32-bit linear
address, referred to as the page-frame offset, locate the desired data within
the page frame.
Since the page-directory table can point to 1K page tables, and each page
table can point to 1K page frames, a total of 1M page frames can be implemented. Since each page contains 4K bytes, up to 4G bytes of virtual memory
can be addressed by the microprocessor with a single page-directory table.
In addition to the base address of the page table orthe page frame, each directory-table entry or page-table entry contains attribute bits and a present bit, as
illustrated in Figure 2-25 and listed in Table 2-19.
Figure 2-25. Directory- and Page- Table Entry (DTE and PTE) Format
12 11
31
Base Address
10
Available
9 8
7
6
5
4
o
A
PCD
3
2
U/S W/R
o
P
= Reserved
Programming Interface
2-41
Memory Address Space
Table 2-19. Directory- and Page- Table Entry (DTE and PTE) Bit Definitions
Bit Position
Field Name
Description
31-12
Base
Address
Specifies the base address of the page or page-table
11-9
Undefined and available to the programmer
8-7
Reserved and not available to the programmer
6
D
Dirty bit. If set, indicates that a write access has occurred to the page (PTE only,
undefined in DTE)
5
A
Accessed flag. If set, indicates that a read access or write access has occurred
to the page
4
PCD
Page caching disable flag. If set, indicates that the page is not cacheable in the
on-chip cache
3
2
o
Reserved and not available to the programmer
U/S
User/supervisor attribute. If set (user), page is accessible at all privilege levels.
If clear (supervisor), page is accessible only when CPL :::; 2.
W/R
Write/read attribute. If set (write), page is writable. If clear (read), page is read
only.
P
Present flag. If set, indicates that the page is present in RAM memory and
validates the remaining DTE/PTE bits. If clear, indicates that the page is not
present in memory and that the remaining DTE/PTE bits can be used by the
programmer
If the present bit (P) is set in the DTE, the page table is present and the appropriate page-table entry is read. If P = 1 in the corresponding PTE (indicating
that the page is in memory), the accessed and dirty bits are updated and the
operand is fetched. Both accessed bits (DTE and PTE) are set, if necessary,
to indicate that the table and the page have been used to translate a linear address. The dirty bit (D) is set before the first write is made to a page.
The present bits must be set to validate the remaining bits in the DTE and PTE.
If either of the present bits is not set, a page fault is generated when the DTE
or PTE is accessed. If P = 0, the remaining DTE/PTE bits are available for use
by the operating system. For example, the operating system can use these bits
to record where on the hard disk the pages are located. A page fault is also
generated if the memory reference violates the page-protection attributes.
2.6.3.3
Trans/ation Look-Aside Buffer
The translation look-aside buffer (TLB) is a cache for the paging mechanism
and replaces the two-level page-table lookup procedure for cache hits. The
TLB is a four-way, set-associative, 32-entry, page-table cache that automatically keeps the most commonly used page-table entries in the processor. The
32-entry TLB coupled with a 4K page size results in coverage of 128K bytes
of memory addresses.
The TLB must be flushed when entries in the page tables are changed. The
TLB is flushed whenever the CR3 register is loaded. An individual entry in the
TLB can be flushed using the INVLPG instruction.
2-42
Interrupts and Exceptions
2.7 Interrupts and Exceptions
The processing of either an interrupt or an exception changes the normal sequential flow of a program by transferring program control to a selected service
routine. Except for SMM interrupts, the location of the selected service routine
is determined by one of the interrupt vectors stored in the interrupt-descriptor
table.
All true interrupts are hardware interrupts and are generated by signal sources
external to the CPU. All exceptions, including so-called software interrupts,
are produced internally by the CPU.
2.7.1
Interrupts
External events can interrupt normal program execution by using one of the
three interrupt pins on the TI486SXL(C) family of microprocessors.
o
o
o
Nonmaskable Interrupt (NMI pin)
Maskable Interrupt (INTR pin)
SMM Interrupt (SMI# pin)
For most interrupts, program transfer to the interrupt routine occurs after the
current instruction has been completed. When the execution returns to the
original program, it begins immediately following the interrupted instruction.
The NMI interrupt cannot be masked by software and always uses interrupt
vector 2 to locate its service routine. Since the interrupt vector is fixed and is
supplied internally, no interrupt-acknowledge bus cycles are performed. This
interrupt is usually reserved for unusual situations such as parity errors and
has priority over INTR interrupts.
Once NMI processing has started, no additional NMls are processed until an
IRET instruction is executed, typically at the end of the NMI service routine.
If NMI is re-asserted prior to the execution of the IRET instruction, one and only
one NMI rising edge is stored and then processed after execution of the next
IRET.
During the NMI service routine, maskable interrupts are still enabled. If an unmasked INTR occurs during the NMI service routine, the INTR is serviced and
execution returns to the NMI service routine following the next IRET. If a HALT
instruction is executed within the NMI service routine, the microprocessor restarts execution only in response to RESET, an unmasked INTR, or an SMM
interrupt. NMI does not restart CPU execution under this condition.
The INTR interrupt is unmasked when the interrupt enable flag (IF) in the
EFLAGS register is set to 1. With the exception of string operations, INTR interrupts are acknowledged between instructions. Long string operations have
interrupt windows between memory moves that allow INTR interrupts to be acknowledged.
When an INTR interrupt occurs, the CPU performs two locked interrupt-acknowledge bus cycles. During the second cycle, the CPU reads an 8-bit vector
that is supplied by an external interrupt controller. This vector selects which of
Programming Interface
2-43
Interrupts and Exceptions
the 256 possible interrupt handlers will be executed in response to the interrupt.
The SMM interrupt has higher priority than either the INTR or NMI. After SMI#
is asserted, program execution is passed to an SMI service routine that runs
in SMM address space reserved for this purpose. The remainder of this subsection (2.7.2, Exceptions, through 2.7.6, Error Codes, page 2-48) does not
apply for SMM interrupts. SMM interrupts are described in Section 2.8, System-Management Mode, page 2-49.
2.7.2
Exceptions
Exceptions are generated by an interrupt instruction or a program error. Exceptions are classified as traps, faults, or aborts depending on the mechanism
used to report them and the restartability of the instruction that first caused the
exception.
2.7.2.1
Trap Exceptions
A trap exception is reported immediately following the instruction that generated the trap exception. Trap exceptions are generated by execution of a software interrupt instruction during single stepping, at a breakpoint, or by software interrupt instruction (INTO, INT3, INTn, BOUND) by a single-step operation, or by a data breakpoint.
Software interrupts can be used to simulate hardware interrupts. For example,
an INTn instruction causes the processor to execute the interrupt service routine pointed to by the nth vector in the interrupt table. Execution of the interrupt
service routine occurs regardless of the state of the IF flag in the EFLAGS register.
The one-byte INT3, or breakpoint-interrupt (vector 3), is a particular case of
the INTn instruction. By inserting this one-byte instruction in a program, the
user can set breakpoints in code that can be used during debug.
Single-step operation is enabled by setting the TF bit in the EFLAGS register.
When TF is set, the CPU generates a debug exception (vector 1) after the
execution of every instruction. Data breakpoints also generate a debug exception and are specified by loading the Debug registers (DRO-DR7) with the appropriate values.
2.7.2.2
Fault Exceptions
A fault exception is caused by a program error and is reported prior to completion of the instruction that generated the exception. By reporting the fault prior
to instruction completion, the CPU is left in a state that allows the instruction
to be restarted and the effects of the faulting instruction to be nullified. Fault
exceptions include divide-by-zero errors, invalid opcodes, page faults, and coprocessor errors. Debug exceptions (vector 1) are also handled as faults (except for data breakpoints and single-step operations). After execution of the
fault service routine, the instruction pointer points to the instruction that caused
the fault.
2-44
2.7.2.3
Abort Exceptions
An abort exception is a type of fault exception severe enough that the CPU
cannot restart the program at the faulting instruction. Abort exceptions include
the double fault (vector 8) and coprocessor segment overrun (vector 9).
2.7.3
Interrupt Vectors
When the CPU services an interrupt or exception, the current program's
instruction pointer and flags are pushed onto the stack to allow resumption of
execution of the interrupted program. In protected mode, the processor also
saves an error code for some exceptions. Program control is then transferred
to the interrupt handler (also called the interrupt service routine). Upon execution of an IRET at the end of the service routine, program execution resumes
at the instruction-pointer address saved on the stack when the interrupt was
serviced.
2.7.3.1
Interrupt-Vector Assignments
Each interrupt (except SMI#) and each exception is assigned one of 256 interrupt-vector numbers (Table 2-20). The first 32 interrupt-vector assignments
are defined or reserved. INT instructions acting as software interrupts can use
any of the interrupt vectors, 0 through 255. The nonmaskable hardware interrupt (NMI) is assigned vector 2.
In response to a maskable hardware interrupt (INTR), the microprocessor issues interrupt-acknowledge bus cycles used to read the vector number from
external hardware. These vectors should be in the vector range of 32-255 because vectors 0-31 are predefined.
2.7.3.2
Interrupt-Descriptor Table
The interrupt-vector number is used by the microprocessor to locate an entry
in the interrupt-descriptor table (lOT). In real mode, each lOT entry consists
of a four-byte far pointer to the beginning of the corresponding interrupt service
routine. In protected mode, each lOT entry is an eight-byte descriptor. The Interrupt-Oescriptor-Table register (IOTR) specifies the beginning address and
limit of the lOT. Following reset, the 10TR contains a base address of Oh with
a limit of 3FFh.
The lOT can be located anywhere in physical memory as determined by the
10TR register. The lOT can contain different types of descriptors: interrupt
gates, trap gates, and task gates. Interrupt gates are used mainly to enter a
hardware interrupt handler. Trap gates are generally used to enter an exception handler or software interrupt handler. If an interrupt gate is used, the interrupt enable flag (IF) in the EFLAGS register is cleared before the interrupt handier is entered. Task gates are used to make the transition to a new task.
Programming Interface
2-45
Interrupts and Exceptions
Table 2-20. Interrupt- Vector Assignments
Interrupt Vector
o
2.7.4
Exception Type
Divide error
Fault
Debug exception
Trap (see Note)
2
NMI interrupt
3
Breakpoint
Trap
4
Interrupt on overflow
Trap
5
BOUND range exceeded
Fault
6
Invalid opcode
Fault
7
Device not available
Fault
8
Double fault
Abort
9
Coprocessor segment overrun
Abort
10
Invalid TSS
Fault
11
Segment not present
Fault
12
Stack fault
Fault
13
General-protection fault
Fault
14
Page fault
FaultlTrap
15
Reserved
16
Coprocessor error
Fault
17
Alignment-check exception
Fault
18-31
Note:
Function
Reserved
32-255
Maskable hardware interrupts
Trap
0-255
Programmed interrupt
Trap
Some debug exceptions may report traps on the previous instruction and faults on the
next instruction.
Interrupt and Exception Priorities
As the TI486SXL(C) family of microprocessors executes instructions, each follows a consistent policy for prioritizing exceptions and hardware interrupts as
listed in Table 2-21. SMM interrupts always take precedence. Debug traps for
the previous instruction and next instruction are handled in the next priority.
When NMI and maskable INTR interrupts are both detected at the same
instruction boundary, the microprocessor services the NMI interrupt first.
The microprocessor checks for exceptions in parallel with instruction decoding
and execution. Several exceptions can result in a single instruction. However,
only one exception is generated upon each attempt to execute the instruction.
Each exception service routine should make the appropriate corrections to the
instruction and then restart the instruction. In that way, exceptions can be serviced until the instruction executes properly.
The microprocessor supports instruction restart after all faults except when an
instruction causes a task switch to a task whose task-state segment (TSS) is
2-46
Interrupts and Exceptions
partially not present. A TSS can be partially not present if the TSS is not page
aligned and one of the pages (where the TSS resides) is not currently in
memory.
Table 2-21. Interrupt and Exception Priorities
Priority
Description
Notes
Debug traps and faults from previous
instruction
Includes single-step trap and data breakpoints
specified in the Debug registers
2
Debug traps for next instruction
Includes instruction execution breakpoints
specified in the Debug registers
3
Nonmaskable hardware interrupt
Caused by N M I asserted
4
Maskable hardware interrupt
Caused by INTR asserted and IF = 1
5
Faults resulting from fetching the next
instruction
Includes segment not present,
general-protection fault, and page fault
6
Faults resulting from instruction decoding
Includes illegal opcode, instruction too long,
and privilege violation
7
WAIT instruction and TS
8
ESC instruction and EM = 1 or TS = 1
Device not available exception generated
9
Coprocessor-error exception
Caused by ERROR# asserted
10
Segmentation faults (for each memory
reference required by the instruction) that
prevent transferring the entire memory operand
Includes segment not present, stack fault, and
general-protection fault
11
Page faults that prevent transferring the entire
memory operand
12
Alignment-check fault
2.7.5
= 1 and MP = 1
Device not available exception generated
Exceptions in Real Mode
Many of the exceptions described in Table 2-20 are not applicable in real
mode. Exceptions 10, 11, and 14 do not occur in real mode. Other exceptions
have slightly different meanings in real mode, as listed in Table 2-22.
Table 2-22. Exception Changes in Real Mode
Vector Number
Protected-Mode Function
Real Mode Function
8
Double fault
Interrupt table limit overrun
10
Invalid TSS
11
Segment not present
12
Stack fault
SS segment limit overrun
13
General-protection fault
CS,DS,ES,FS,GSsegme~
limit overrun
14
Page fault
Programming Interface
2-47
Interrupts and Exceptions
2.7.6
Error Codes
When operating in protected mode, the following exceptions generate a 16-bit
error code:
o
o
o
o
o
o
o
Double fault
Alignment check
Invalid TSS
Segment not present
Stack fau It
General-protection fault
Page fault
The error-code format is shown in Figure 2-26 and the error-code bit definitions are listed in Table 2-23. Bits 15-3 (selector index) are not meaningful
if the error code was generated as the result of a page fault. The error code
is always zero for double faults and alignment-check exceptions.
Figure 2-26. Error-Code Format
3
15
Selector Index
o
2
S2
S1
SO
Table 2-23. Error-Code Bit Definitions
Fault
Type
Selector
Index
(Bits 15-3)
Page fault
S2 (Bit 2)
S1 (Bit 1)
SO (Bit 0)
Reserved
Fault caused by:
= not present page
1 = page-level protection violation
Fault occurred during:
= read access
1 = write access
Fault occurred during:
= supervisor access
1 = user access
lOT fault
Index of faulty
lOT selector
Reserved
Segment
fault
Index of faulty
selector
TI bit of faulty selector
2-48
o
o
o
If set, the exception
occurred while trying to
or
invoke
exception
hardware interrupt handler.
0
If set, the exception
occurred while trying to
invoke
exception
or
hardware interrupt handler.
System-Management Mode
2.8 System-Management Mode
System-management mode (SMM) provides an additional interrupt that can
be used for system power management or software-transparent emulation of
I/O peripherals. SMM is entered using the software-management interrupt
(SMI#) which has a higher priority than any other interrupt, including NMI. After
receiving an SMI#, portions of the CPU state are automatically saved, SMM
is entered and program execution begins at the base of SMM space
(Figure 2-27 and Figure 2-28). Running in protected SMM address space,
the interrupt routine does not interfere with the operating system or any application program.
Seven SMM instructions have been added to the TI486SXL(C) microprocessor family instruction set that permit saving and restoring the total CPU state
when in SMM mode. Two new pins, SMI# and SMADS#, support SMM functions.
Figure 2-27. TI486SXLC Memory and 110 Address Spaces
Physical
Memory Space
FFFFFFh~--------------------~
Potential
SMM Addres Space
FF FFFFh
Defined
SMM
Address
Space
Physical
Memory
16M bytes
4K bytes to
16M bytes
OOOOOOh ________________________
Non-SMM Mode
ADS#Active
SMADS#
Active
ADS#
Active
OOOOOOh ________________________
SMM Mode
Programming Interface
2-49
System-Management Mode
Figure 2-28. TI486SXL Memory and liD Address Spaces
Physical
Memory Space
FFFF FFFFh
Potential
SMM Address Space
FFFF FFFFh
Defined
SMM
Address
Space
Physical
Memory
4G bytes
4K bytes to
16M bytes
0000 OOOOh _ _ _ _ _ __
ADS#
Active
0000 OOOOh _ _ _ _ _ __
Non-SMM Mode
ADS#Active
2.8.1
SMADS#
Active
SMM Mode
SMM Operations
SMM operation is summarized in Figure 2-29. Entering SMM requires the
assertion of SMI# for at least four CLK2 periods. For the SMI# input to be recognized, the following Configuration register bits must be set as shown below:
SMI
8MAC
8M4
ARR4
CCR1 (1)
CCR1 (2)
CCR1 (7)
SIZE(3-0)
=1
=0
=1
>0
The Configuration registers are discussed in subsection 2.5, System Register
Set, page 2-16. After recognizing SMI# and prior to executing the SMI service
routine, some of the CPU-state information is changed. Prior to modification,
this information is automatically saved in the 8MM memory-space header located at the top of the 8MM memory space. After the header is saved, the CPU
enters real mode and begins executing the 8MI service routine starting at the
SMM memory base address.
The 8MI service routine is user definable and may contain system or powermanagement software. If the power-management software forces the CPU
to power down, or if the 8MI service routine modifies more than what is automatically saved, the complete CPU-state information must be saved.
2-50
System-Management Mode
Figure 2-29. SMM Execution Flow Diagram
SMI# Sampled Active
CPU State Stored in SMM
Address-Space Header
Program Flow Transfers
to SMM Address Space
CPU Enters Real Mode
Execution Begins at SMM
Address-Space Base Address
RSM Instruction Restores CPU
State Using Header Information
Normal Execution Resumes
A complete CPU-state save is performed by using MOV instructions to save
normally accessible information, and by using the SMM instructions to save
CPU information that is not normally accessible to the programmer. As will be
explained, SMM instructions (SVDC, SVLDT, and SVTS) are used to store the
LDTR, TSR, and Segment registers and their associated descriptor cache entries in aO-bit memory locations. After power up or at the end of the SM I service
routine, the MOV and additional SMM instructions (RSDC, RSLDT, and RSTS)
are used to restore the CPU state. The SMM RSM instruction returns the CPU
to normal execution.
2.8.2
SMM Memory Space Header
With every SMI interrupt, certain CPU-state information is automatically saved
in the SMM memory space header located at the top of SMM address space
(Table 2-24 and Figure 2-30). The header contains CPU-state information
that is modified when servicing an SMI interrupt. Included in this information
are two pointers. The current IP points to the instruction executing when the
SMI was detected. The next IP points to the instruction that will be executed
after exiting SMM. Also saved are the contents of Debug register? (DR?), the
extended Flag Word register (EFLAGS), and Control register 0 (CRO). If SMM
has been entered due to an 1/0 trap for a REP INSx or REP OUTSx instruction,
the current IP and next IP fields (Table 2-24) contain the same addresses and
the I and P fields contain valid information.
Programming Interface
2-51
SV~5tel77-"lIarla!J,ement
Mode
Table 2-24. SMM Memory Space Header
Name
Description
Size
DR?
The contents of the Debug register?
4 bytes
EFLAGS
The contents of the extended flag register
4 bytes
CRO
The contents of the Control register 0
4 bytes
Current IP
The address of the instruction executed prior to servicing the SMI interrupt
4 bytes
Next IP
The address of the next instruction that will be executed after exiting the SMM mode
4 bytes
CS Selector
Code Segment register selector for the current code segment
2 bytes
CS Descriptor
Code register descriptor for the current code segment
8 bytes
P
REP INSx/OUTSxt Indicator
P is 1 if current instruction has a REP prefix
P is 0 if current instruction does not have REP prefix
1 bit
IN, INSx, OUT, or OUTSx Indicator
I is 1 if current instruction performed is an I/O WRITE
I is 0 if current instruction performed is an I/O READ
1 bit
ESI or EDI
t
Restored ESI or EDI value. Used when it is necessary to repeat a REP OUTSx or 4 bytes
REP INSx instruction when one of the 1/0 cycles caused an SMI# trap
INSx = INS, INSB, INSW, or INSD instruction, and OUTSx = OUTS, OUTSB, OUTSW, or OUTSD instruction.
Figure 2-30. SMM Memory Space Header
o
31
Top of SMM ----.
Address Space
DR?
-4h
EFLAGS
-8h
CRO
-Ch
Current IP
-10h
Next IP
16 15
31
Reserved
I
0 -14h
CS Selector
-18h
CS Descriptor (Bits 63-32)
31
CS Descriptor (Bits 31-0)
Reserved
-1Ch
2 1 0
Ipl'l
-20h
-24h
Reserved
-28h
Reserved
-2Ch
ESI or EDI
2.8.3
-30h
SMM Instructions
The TI486SXL(C) microprocessor family automatically saves the minimal
amount of CPU-state information when entering SMM that allows fast SMI service routine entry and exit. After entering the SMI service routine, the MOV,
SVDC, SVLDT, and SVTS instructions can be used to save the complete CPU
2-52
Sv~)teln-lI.l/an'aaj9mI9nt
Mode
state information. If the SMI service routine either modifies more than what is
automatically saved or forces the CPU to power down, the complete CPUstate information must be saved. Since the TI486SXL(C) microprocessors are
static devices, their internal state is retained when the input clock is stopped.
Therefore, an entire CPU-state save is not necessary prior to stopping the input clock.
The new SMM instructions, listed in Table 2-25, can be executed only if:
(a) the current privilege level (CPL) = 0 and the SMAC bit (CCR1 , bit 2) is set;
or (b) CPL = 0 and the CPU is in an SMI service routine (SMI# = 0). If both these
conditions are not met and an attempt is made to execute an SMM instruction,
an invalid-opcode exception is generated. These instructions can be executed
outside of defined SMM space provided the above conditions are met. All of
the SMM instructions (except RSM) save or restore 80 bits of data, allowing
the saved values to include the hidden portion of the register contents.
Table 2-25. SMM Instruction Set
t
Instruction
Opcode
Format
Description
SVOC
OF 78 [mod sreg3 rim]
SVOC mem80t, sreg3
Save Segment register and Descriptor
Saves reg OS, ES, FS, GS, or SS to mem80
RSOC
OF 79 [mod sreg3 rim]
RSOC sreg3, mem80
Restore Segment register and Descriptor
Restores reg OS, ES, FS, GS, or SS from
mem80
(eS is automatically restored with RSM)
SVLOT
OF 7A [mod 000 rim]
SVLOT mem80
Save LDTR and Descriptor
Saves local-descriptor table
mem80
(LOTR)
to
RSLOT
OF 7B [mod 000 rim]
RSLOT mem80
Restore LDTR and Descriptor
Restores local-descriptor table (LOTR) from
mem80
SVTS
OF 7C [mod 000 rim]
SVTS mem80
Save TSR and Descriptor
Save Task-State register (TSR) to mem80
RSTS
OF 70 [mod 000 rim]
RSTS mem80
Restore TSR and Descriptor
Restores Task-State register (TSR) from
mem80
RSM
OF AA
RSM
Resume Normal Mode
Exits SMM mode. The CPU state is restored
using the SMM memory space header and
execution resumes at interrupted point.
mem80 = 80-bit memory location.
Programming Interface
2-53
System-Management Mode
2.8.4
SMM Memory Space
SMM memory space is defined by assigning address region 4 to SMM memory
space. This assignment is made by setting bit 7 (SM4) in the on-chip CCR1
register. ARR4, also an on-chip Configuration register, specifies the base address and size of the SMM memory space. The base address must be a multiple of the SMM memory space size. For example, a 32K-byte SMM memory
space must be located at a 32K-byte address boundary. The memory space
size can range from 4K bytes to 16M bytes.
SMM memory space accesses can use address pipelining, and are always
noncacheable. SMM accesses ignore the state of the A20M# input and drive
the A20 address bit to the unmasked value.
Access to the SMM memory space can be made while not in SMM mode by
setting the system-management access (SMAC) bit in the CCR1 register. This
feature can be used to initialize the SMM memory space.
While in SMM mode, SMADS# address strobes are generated instead of
ADS# for SMM memory accesses. Any memory accesses outside the defined
SMM space result in normal memory accesses and ADS# strobes. Data
(noncode) accesses to main memory that overlap defined SMM memory
space are allowed if bit 3 in CCR1 (MMAC) is set. In this case, ADS# strobes
are generated for data accesses only and SMADS# strobes continue to be
generated for code accesses.
2.8.5
SMI Service Routine Execution
Upon entry into SMM after the SMM header has been saved, the CRO,
EFLAGS, and DR7 registers are set to their reset values. The Code Segment
(CS) register is loaded with the base and limits defined by the ARR4 register
and the SMI service routine begins execution at the SMM base address in real
mode.
The routine must then save the value of any registers that can be changed by
the SMI service routine. For data accesses immediately after entering the SMI
service routine, the routine must use CS as a segment override. I/O port access is possible during the routine but care must be taken to save registers
modified by the I/O instructions. Before using a Segment register, the register's descriptor-cache contents should be saved using the SVDC instruction.
While executing in SMM space, execution flow can transfer to normal memory
locations.
Hardware interrupts (INTRs and NMls) can be serviced during an SMI service
routine. If interrupts are to be serviced while operating in SMM memory space,
the SMM memory space must be within the 0 to 1M-byte address range to assure proper return to the SMI service routine after handling the interrupt.
INTRs are automatically disabled when entering SMM since the IF flag is set
to its reset value. However, NMls remain enabled. If it is desired to disable NMI,
it should be done immediately after entering the SMI service routine by the system hardware logic.
Within the SMI service routine, protected mode can be entered and exited as
required, and real- or protected-mode device drivers can be called.
2-54
System-Management Mode
To exit the SMI service routine, a resume (RSM) instruction, rather than an
IRET, is executed. The RSM instruction causes the microprocessor to restore
the CPU state using the SMM header information and resume execution at the
interrupted point. If the full CPU state was saved by the programmer, the stored
values should be reloaded prior to executing the RSM instruction using the
MOV and the RSDC, RSLDT, and RSTS instructions.
2.8.6
CPU States Related to SMM and Suspend Mode
The state diagram shown in Figure 2-31 illustrates the various CPU states
associated with SMM and suspend mode. While in the SMI service routine, the
TI486SXL(C) microprocessor family can enter suspend mode either by
executing a HALT instruction or by asserting the SUSP# input.
During SMM operation and while in SUSP#-initiated suspend mode, an occurrence of either NMI or INTR is latched. In order for INTR to be latched, the IF
flag must have been set. The INTR or NMI is serviced after exiting suspend
mode.
If suspend mode is entered via a HALT instruction from the operating system
or application software, the reception of an SMI# interrupt causes the CPU to
exit suspend mode and enter SMM. If suspend mode is entered via the hardware (SUSP# = 0) while the operating system or application software is active,
the CPU latches one occurrence of INTR#, NMI, and SMI#.
Programming Interface
2-55
System-Management Mode
Figure 2-31. SMM and Suspended-Mode Flow Diagram
NMI or INTR
HALT*
IRET*
SUSP#
RESET------~~~~
=0
as/Application
Software
SUSP#
=1
(INTR, NMI, and SMI Latched)
Non-SMM Oerations
- -SMM
- -Operations
-------
INTR and NMI
* Instructions
2-56
(INTR and NMI
Latched)
Shutdown and Halt / Protection
2.9 Shutdown and Halt
Shutdown occurs when a severe error is detected that prevents further processing. An NMI input can bring the processor out of shutdown if the IDT limit is
large enough to contain the NMI interrupt vector (at least OOOFh) and the stack
has enough room to contain the vector and flag information (Le., stack pointer
is greater than OOOSh). Otherwise, shutdown can be exited only by a processor
reset.
The halt (HLT) instruction stops program execution and prevents the processor from using the local bus until restarted. The microprocessor then enters
a low-power suspend mode. INTR with interrupts enabled (IF bit in
EFLAGS = 1), SMI, NMI, or RESET forces the CPU out of the halt state. If interrupted, the saved code segment and instruction pointer specify the instruction following the HLT.
2.10 Protection
Segment protection and page protection are safeguards built into the
TI486SXL(C) microprocessor family protected-mode architecture that deny
unauthorized or incorrect access to selected memory addresses. These safeguards allow multitasking programs to be isolated from each other and from
the operating system. Page protection is discussed in subsection 2.6.3, Protected-Mode Memory Addressing, page 2-39. This section concentrates on
segment protection.
Selectors and descriptors are the key elements in the segment-protection
mechanism. The segment base address, size, and privilege level are established by a segment descriptor. Privilege levels control the use of privilege
instructions, 1/0 instructions, and access to segments and segment descriptors. Selectors are used to locate segment descriptors.
Segment accesses are divided into two basic types, those involving code segments (e.g., control transfers) and those involving data accesses. The ability
of a task to access a segment depends on:
o
o
o
o
the
the
the
the
segment type
instruction requesting access
type of descriptor used to define the segment
associated privilege levels
Data stored in a segment can be accessed only by code executing at the same
or a more privileged level. A code segment or procedure can be called only by
a task executing at the same or a less privileged level.
2. 10.1
Privilege Levels
The values for privilege levels range between 0 and 3. Level 0 is the highest
privilege level (most privileged), and level 3 is the lowest privilege level (least
privileged). The privilege level in real mode is effectively O.
The descriptor privilege level (DPL) is the privilege level defined for a segment
in the segment descriptor. The DPL field specifies the minimum privilege level
needed to access the memory segment pointed to by the descriptor.
Programming Interface
2-57
Protection
The current privilege level (CPL) is defined asthe current task's privilege level.
The CPL of an executing task is stored in the hidden portion of the Code Segment register and essentially is the DPL for the current code segment.
The requested privilege level (RPL) specifies a selector's privilege level and
is used to distinguish between the privilege level of a routine actually accessing memory (the CPL), and the privilege level of the original requestor (the
RPL) of the memory access. The lower privilege level (0 is highest) of RPL and
CPL is called the effective privilege level (EPL). Therefore, if RPL = 0 in a segment selector, the effective privilege level is always determined by the CPL.
If RPL = 3, the effective privilege level is always 3 regardless of CPL.
For a memory access to succeed, the effective privilege level (EPL) must be
at least as privileged as the descriptor privilege level (EPL ~ DPL). If the EPL
is less privileged than the DPL (EPL < DPL), a general-protection fault is generated. For example, if a segment has a DPL = 2, an instruction accessing the
segment succeeds only if executed with an EPL ~ 2.
2.10.2 1/0 Privilege Levels
The 1/0 privilege level (IOPL) allows the operating system executing at
CPL = 0 to define the least-privileged level at which 10PL-sensitive instructions can be used unconditionally. The 10PL-sensitive instructions include
CLI, IN, OUT, INS, OUTS, REP INS, REP OUTS, and STI. Modification of the
IF bit in the EFLAGS register is also sensitive to the 1/0 privilege level.
The 10PL is stored in the EFLAGS register. An 1/0 permission bit map is available as defined by the 32-bit task-state segment (TSS). Since each task can
have its own TSS, access to individual 1/0 ports can be granted through separate 1/0 permission bit maps.
If CPL ::;; 10PL, 10PL-sensitive operations can be performed. If CPL > 10PL,
a general-protection fault is generated if the current task is associated with a
16-bit TSS. If the current task is associated with a 32-bit TSS and CPL > 10PL,
the CPU consults the 1/0 permission bit map in the TSS to determine on a portby-port basis whether or not I/O instructions (IN, OUT, INS, OUTS, REP INS,
REP OUTS) are permitted, and the remaining 10PL-sensitive operations generate a general-protection fault.
2.10.3 Privilege Level Transfers
A task's CPL can be changed only through intersegment control transfers using gates or task switches to a code segment with a different privilege level.
Control transfers result from exception and interrupt servicing and from execution of the CALL, JMP, INT, IRET, and RET instructions.
2.10.3. 1 Control Transfers
The five types of control transfers are summarized in Table 2-26. Control
transfers can be made only when the operation causing the control transfer
references the correct descriptor type. Any violation of these descriptor-usage
rules causes a general-protection fault.
2-58
Protection
Table 2-26. Descriptor Types Used for Control Transfer
Descriptor
Referenced
Descriptor
Table
Intersegment within the same privilege JMP, CALL, RET, IRET
level
Code segment
GOT or LOT
Intersegment to the same or a more CALL
privileged level. Interrupt within task
Interrupt instruction, Excep(could change CPL level)
tion, External interrupt
Call gate
GOT or LOT
Type Of Control Transfer
Operation Types
Trap or interrupt lOT
gate
Intersegment to a less privileged level RET,IRET
(changes task CPL)
Code segment
GOT or LOT
Task switch via TSS
CALL, JMP
Task-state
segment
GOT
Task switch via task gate
CALL, JMP
Task gate
GOT or LOT
Task switch via task gate
IRET, Interrupt instruction, Task gate
Exception, External interrupt
lOT
Any control transfer that changes the CPL within a task results in a change of
stack. The initial values for the stack segment (SS) and stack pointer (ESP)
for privilege levels 0, 1, and 2 are stored in the TSS. Ouring a JMP or CALL
control transfer, the SS and ESP are loaded with the new stack pointer and the
previous stack pointer is saved on the new stack. When returning to the original privilege level, the RET or IRETinstruction restores the less-privileged
stack.
2.10.3.2 Gates
Gate descriptors provide protection for privilege transfers among executable
segments. Gates are used to transition to routines of the same or a more privileged level. Call gates, interrupt gates, and trap gates are used for privilege
transfers within a task. Task gates are used to transfer between tasks.
Gates conform to the standard rules of privilege.· In other words, gates can be
accessed by a task if the effective privilege level (EPL) is the same or more
privileged than the gate descriptor's privilege level (OPL).
2.10.4 Initialization and Transition to Protected Mode
The TI486SXL(C) microprocessor family switches to real mode immediately
after RESET. While operating in real mode, the system tables and registers
should be initialized. The GOTR and IOTR must point to a valid GOT and lOT,
respectively. The size of the lOT should be at least 256 bytes, and the GOT
must contain descriptors that describe the initial code and data segments.
The processor can be placed in protected mode by setting the PE bit in the
CRO register. After enabling protected mode, the CS register should be loaded
and the instruction-decode queue should be flushed by executing an intersegment JMP. Finally, all data Segment registers should be initialized with appropriate selector values.
Programming Interface
2-59
Virtua/-8086 Mode
2.11 Virtual-SOS6 Mode
Both real mode and virtual-8086 (V86) mode are supported by the
TI486SXL(C) microprocessor family, allowing execution of 8086 application
programs and 8086 operating systems. V86 mode allows the execution of
8086-type applications, yet still permits use of the TI486SXL(C) microprocessor-protection mechanism. V86 tasks run at privilege level 3. Upon entry, all
segment limits are set to FFFFh (64K) as in real mode.
2.11.1 Memory Addressing
While in V86 mode, Segment registers are used in the same manner as in real
mode. The contents of the Segment register are shifted left four bits and added
to the offset to form the segment base linear address. The TI486SXL(C) microprocessor family permits the operating system to select which programs use
the V86 address mechanism and which programs use protected-mode addressing for each task.
The TI486SXL(C) microprocessor family also permits the use of paging when
operating in V86 mode. Using paging, the 1M-byte address space of the V86
task can be mapped to anywhere in the 4G-byte linear address space of the
microprocessor CPU. As in real mode, linear addresses that exceed 1M byte
cause a segment-limit-overrun exception.
The paging hardware allows multiple V86 tasks to run concurrently, and provides protection and operating-system isolation. The paging hardware must
be enabled to run multiple V86 tasks or to relocate the address space of a V86
task to physical address space above 1M byte.
2.11.2 Protection
All V86 tasks operate at the lowest privilege level (level 3) and are subject to
all of the microprocessor protected-mode protection checks. As a result, any
attempt to execute a privileged instruction within a V86 task results in a general-protection fault.
In V86 mode, a slightly different set of instructions is sensitive to the 1/0 privilege level (IOPL) than in protected mode. These instructions are: CLI, INTn,
IRET, POPF, PUSHF, and STI. The INT3, INTO and BOUND variations of the
INT instruction are not 10PL sensitive.
2.11.3 Interrupt Handling
To fully support the emulation of an 8086-type machine, interrupts in V86 mode
are handled as follows. When an interrupt or exception is serviced in V86
mode, program execution transfers to the interrupt service routine at privilege
level 0 (i.e., transition from V86 to protected mode occurs) and the VM bit in
the EFLAGS register is cleared. The protected-mode interrupt service routine
then determines if the interrupt came from a protected-mode or V86 application by examining the VM bit in the EFLAGS image stored on the stack. The
interrupt service routine can then choose to allow the 8086 operating system
2-60
Virtual-8086 Mode
to handle the interrupt or can emulate the function of the interrupt handler. Following completion of the interrupt service routine, an IRET instruction restores
the EFLAGS register (restores VM = 1) and segment selectors and control returns to the interrupted V86 task.
2.11.4 Entering and Leaving Va6 Mode
V86 mode is entered from protected mode either by executing an IRET instruction at CPL = 0 or by task switching. If an IRET is used, the stack must contain
an EFLAGS image with VM = 1. If a task switch is used, the TSS must contain
an EFLAGS image containing a 1 in the VM bit position. The POPF instruction
cannot be used to enter V86 mode since the state of the VM bit is not affected.
V86 mode can be exited only as the result of an interrupt or exception. The
transition out must use a 32-bit trap or interrupt gate that must point to a nonconforming privilege level 0 segment (DPL =0), or a 32-bit TSS. These restrictions are required to permit the trap handler to IRET back to the V86 program.
Programming Interface
2-61
2-62
Chapter 3
TI486SXLC Microprocessor Bus Interface
This chapter provides a summary of the TI486SXLC series processor signals
and descriptions of all inputs/outputs, functional timing and bus operations (including pipelined and nonpipelined addressing), various interfaces, and power
management.
Topic
Page
.~
•...••............ ~ .•... \..• ~ ....•• 'o • • ~. • • 3..2
3.1
InputlOutputSignals
3~2
Bus-Cycle Definition ................... ~ ............... .; •. ~ .•.•. '3-13
3.3 . ResetTimingand InternafClockSyhchronization .' •. '" ........ ~ .3..17
""
3.4
~
, ,
~
: ;:'
"
, "e
'
,
'
,
"
',' ~
,
BusOperationand:Functi,onaITiirlihg ................... ~ .•.•• cO.·3-1~
3-1
Input/Output Signals
3.1
Input/Output Signals
This section describes the TI486SXLC series microprocessors' input and output signals. The discussion of these signals is arranged by functional groups
as shown in Figure 3-1. Table 3-1 gives a brief description of each signal.
Figure 3-1. TI486SXLC Functional Signal Groupings
2x Clock
CLK2
TI486SXLC
INTR
NMI
Reset
Address
Bus
RESET
{
Data
Bus
Bus
Cycle
Definition
Bus
Cycle
Control
3-2
{
{
A23-A1
BLE#
}
Interrupt
Control
}
Internal
Cache
Interface
SMI#
KEN#
FLUSH#
BHE#
D15-DO
A20M#
W/R#
PEREQ
D/C#
BUSY#
M/IO#
HOLD
NA#
HLDA
ADS#
SMADS#
}
Coprocessor
Interface
}
Bus
Arbitration
}
Power
Management
ERROR#
LOCK#
READY#
Address
Bit-20 Mask
SUSP#
SUSPA#
FLT#
Float
Control
Input/Output Signals
Table 3-1. TI486SXLC Signal Summary
Signal
Signal Name
Signal Group
ADS#
Address strobe
Bus-cycle control
A20M#
Address bit-20 mask
None
A23-A1
Address bus lines
Address bus
BHE#
Byte-high enable
Address bus
BlE#
Byte-low enable
Address bus
BUSY#
Processor extension busy
Coprocessor interface
ClK2
2X clock input
None
015-00
Data bus lines
None
D/C#
Data/control
Bus-cycle definition
ERROR#
Processor extension error
Coprocessor interface
FlT#
Float
None
FlUSH#
Cache flush
Internal cache interface
HlDA
Hold acknowledge
Bus arbitration
HOLD
Hold request
Bus arbitration
INTR
Maskable interrupt request
Interrupt control
KEN#
Cache enable
Internal cache interface
lOCK#
Bus lock
Bus-cycle definition
M/IO#
Memory/input-output
Bu~-cycle
NA#
Next address request
Bus-cycle control
NMI
Nonmaskable interrupt request
Interrupt control
PEREQ
Processor extension request
Coprocessor interface
READY#
Bus ready
Bus-cycle control
RESET
Reset
None
SMADS#
SMM address strobe
Bus-cycle control
SMI#
System management interrupt
Interrupt control
SUSP#
Suspend request
Power management
SUSPA#
Suspend acknowledge
Power management
W/R#
Write/read
Bus-cycle definition
definition
The following sections describe the signals and their functional characteristics. Additional signal information can be found in Chapter 5, Electrical Specifications. Chapter 5 documents the dc and ac characteristics for the signals including voltage levels, propagation delays, setup times, and hold times. Specified setup and hold times must be met for proper operation of the TI486SXLC
series microprocessors.
Tl486SXLC Microprocessor Bus Interface
3-3
Input/Output Signals
3.1.1
TI486SXLC Terminal Function Descriptions
Table 3-2 identifies and describes each of the TI486SXLC package terminals.
Table 3-2. TI486SXLC Terminal Functions
Terminal
Name
No.
Description
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
18
51
52
53
54
55
56
58
59
60
61
62
64
65
66
70
72
73
74
75
76
79
80
ADS#
16
Address Strobe (active low). This 3-state output indicates that the TI486SXLC
microprocessor has driven a valid address (A23-A 1, BHE#, BLE#) and bus-cycle
definition (M/IO#, D/C#, W/R#) on the appropriate output pins. During nonpipelined bus
cycles, ADS# is active for the first clock of the bus cycle. During address pipelining,
ADS# is asserted during the previous bus cycle and remains asserted until READY# is
returned for that cycle. ADS# floats while the microprocessor is in a hold-acknowledge
or float state.
A20M#
31
Address Bit-20 Mask (active low). This input causes the microprocessor to mask (force
low) physical address bit 20 when driving the external address bus or performing an
internal cache access. When the processor is in real mode, asserting A20M# emulates
the 1M-byte address wraparound that occurs on the 8086. The A20 signal is never
masked when paging is enabled regardless of the state of the A20M# input. The A20M#
input is ignored following reset and can be enabled using the A20M bit in the CCRO
Configuration register.
Address Bus (active high). The address bus (A23-A 1) signals are 3-state outputs that
provide addresses for physical memory and 1/0 ports. All address lines can be used for
addressing physical memory allowing a 16M-byte address space (00 OOOOh to FF
FFFFh). During 1/0 port accesses, A23-A16 are driven low (except for coprocessor
accesses). This permits a 64K-byte 1/0 address space (00 OOOOh to 00 FFFFh).
During all coprocessor 1/0 access address lines A22-A 16 are driven low and A23 is
driven high. This allows A23 to be used by external logic to generate a coprocessor
select signal. Coprocessor command transfers occur with address 80 00F8h and
coprocessor data transfers occur with addresses 80 OOFCh and 80 OOFEh. A23-A 1 float
while the CPU is in a hold-acknowledge or float state.
A20M# is internally connected to a pullup resistor to prevent it from floating active when
left unconnected.
3-4
Input/Output Signals
Table 3-2. TI486SXLC Terminal Functions (Continued)
Terminal
Name
No.
Description
BHE#
BLE#
19
17
Byte Enables (active low). Byte-low enable (BLE#) and byte-high enable (BHE#)
3-state outputs indicate which byte( s} of the 16-bit data bus are selected for data transfer
during the current bus cycle. BLE# selects the low byte (07-00) and BHE# selects the
high byte (015-08).
When BHE# and BLE# are asserted, both bytes (all 16 bits) of the data bus are selected.
BLE# and BHE# float while the CPU is in a hold-acknowledge or float state.
BHE# = BLE# = 1 never occurs during a bus cycle.
BUSY#
34
Coprocessor Busy (active low). This input indicates to the TI486SXLC that the
coprocessor is currently executing an instruction and is unable to accept another
opcode. When the microprocessor encounters a WAIT instruction or any coprocessor
instruction that operates on the coprocessor stack (Le., load, pop, arithmetic operation),
BUSY# is sampled. BUSY# is continually sampled and must be recognized as inactive
before the CPU supplies the coprocessor another instruction. However, coprocessor
instructions FNINIT and FNCLEX are allowed to execute even if BUSY# is active
because they are used for coprocessor initialization and exception clearing.
BUSY# is internally connected to a pullup resistor to prevent it from floating active when
left unconnected.
CLK2
15
2X Clock Input (active high). This input signal is the basic timing reference for the
TI486SXLC microprocessors. The CLK2 input is internally divided by two to generate
the internal processor clock. The external CLK2 is synchronized to a known phase of
the internal processor clock by the falling edge of the RESET signal. External timing
parameters are defined with respect to the rising edge of CLK2.
For the TI486SXLC2 microprocessors, the CLK2 input is used internally to generate the
internal core processor clock and the internal bus interface clock. The external CLK2 is
synchronized to a known phase of the internal processor clock by the falling edge of the
RESET signal. External timing parameters are defined with respect to the rising edge
of CLK2.
O/C#
24
Data/Control. This 3-state, bus-cycle-definition signal is low during control cycles and
is high during data cycles. Control cycles are issued during functions such as a halt
instruction, interrupt servicing, and code fetching. Data bus cycles include data access
from either memory or 110.
Tl486SXLC Microprocessor Bus Interface
3-5
Input/Output Signals
Table 3-2. TI486SXLC Terminal Functions (Continued)
Terminal
Name
No.
Description
00
01
02
03
04
05
06
07
08
D9
010
011
012
013
014
015
1
100
99
96
95
94
93
92
90
89
88
87
86
83
82
81
Oata Bus (active high). The data bus (015-00) signals are 3-state bidirectional signals
that provide the data path between the microprocessor and external memory and I/O
devices. The data bus inputs data during memory-read, I/O-read, and
interrupt-acknowledge cycles and outputs data during memory and I/O-write cycles.
Oata read operations require that specified data setup and hold times be met for correct
operation. The data bus signals float while the CPU is in a hold-acknowledge or float
state.
ERROR#
36
Coprocessor Error (active low). This input indicates that the coprocessor generated an
error during execution of an instruction. ERROR# is sampled by the microprocessor
whenever a coprocessor instruction is executed. If ERROR# is sampled active, the
processor generates exception 16 that is then serviced by the exception handling
software.
Certain coprocessor instructions do not generate an exception 16 even if ERROR# is
active. These instructions, which involve clearing coprocessor error flags and saving the
coprocessor state, are: FNINIT, FNCLEX, FNSTSW, FNSTCW, FNSTENV, FNSAVE.
ERROR# is internally connected to a pullup resistor to prevent it from floating active
when left unconnected.
FLT#
28
Float (active low). This input forces all bidirectional and output signals to a 3-state
condition. Floating the signals allows the microprocessor signals to be driven externally
without physically removing the device from the circuit. The microprocessor must be
reset following assertion or deassertion of FLT#. It is recommended that FLT# be used
only for test purposes.
FLT# is internally connected to a pullup resistor to prevent it from floating active when
left unconnected.
FLUSH#
30
Cache Flush (active low). This input invalidates (flushes) the entire cache. Use of
FLUSH# to maintain cache coherency is optional. The cache may also be invalidated
during each hold-acknowledge cycle by setting the BARB bit in the CCRO Configuration
register. The FLUSH# input is ignored following reset and can be enabled using the
FLUSH bit in the CCRO Configuration register.
FLUSH# is internally connected to a pullup resistor to prevent it from "floating active when
left unconnected.
3-6
Input/Output Signals
Table 3-2. TI486SXLC Terminal Functions (Continued)
Terminal
Name
HOLD
No.
4
Description
Hold Request (active high). This input indicates that another bus master requests
control of the local bus. The bus arbitration (HOLD, HLDA) signals allow the
microprocessor to relinquish control of its local bus when requested by another bus
master device. Once the processor has relinquished its bus (3-stated), the bus master
device can then drive the local bus signals.
After recognizing the HOLD request and completing the current bus cycle or sequence
of locked bus cycles, the microprocessor responds by floating the local bus and
asserting the hold-acknowledge (HLDA) output.
Once HLDA is asserted, the bus remains granted to the requesting bus master until
HOLD becomes inactive. When the microprocessor recognizes HOLD is inactive, it
simultaneously drives the local bus and drives HLDA inactive. External pullup resistors
may be required on some of the microprocessor 3-state outputs to ensure that they
remain inactive while in a hold-acknowledge state.
The HOLD input is not recognized while RESET is active. If HOLD is asserted while
RESET is active, RESET has priority and the microprocessor places the bus into an idle
state instead of a hold-acknowledge state. The HOLD input is also recognized during
suspend mode provided that the CLK2 input has not been stopped. HOLD is level
sensitive and must meet specified setup and hold times for correct operation.
HLDA
3
Hold Acknowledge (active high). This output indicates that the microprocessor is in a
hold-acknowledge state and has relinquished control of its local bus. While in the
hold-acknowledge state, the microprocessor drives HLDA active and continues to drive
SUSPA#, if enabled. The other microprocessor outputs are in the high-impedance state
allowing the requesting bus master to drive these signals. If the on-chip cache can
satisfy bus requests, the microprocessor continues to operate during hold-acknowledge
states. A20M# is internally recognized during this time.
The microprocessor deactivates HLDA when the HOLD request is driven inactive. The
microprocessor stores an NMI rising edge during a hold-acknowledge state for
processing after HOLD is inactive. The FLUSH# input is also recognized during a
hold-acknowledge state. If SUSP# is asserted during a hold-acknowledge state, the
microprocessor mayor may not enter suspend mode depending on the state of the
internal execution pipeline. Table 3-3 summarizes the state of the microprocessor
signals during hold acknowledge.
INTR
40
Maskable Interrupt Request. This level-sensitive input causes the processor to
suspend execution of the current instruction stream and begin execution of an interrupt
service routine. The INTR input can be masked (ignored) through the Flag Word register
IF bit. When unmasked, the microprocessor responds to the INTR input by issuing two
locked interrupt-acknowledge cycles. To assure recognition of the INTR request, INTR
must remain active until the start of the first interrupt-acknowledge cycle.
T1486SXLC Microprocessor Bus Interface
3-7
Input/Output Signals
Table 3-2. TI486SXLC Terminal Functions (Continued)
Terminal
Name
No.
Description
KEN#
29
Cache Enable (active low). This input indicates that the data being returned during the
current cycle is cacheable. When KEN# is active and the microprocessor is performing
a cacheable code-fetch or memory-data-read cycle, the cycle is transformed into a
cache fill. Use of the KEN# input to control cacheability is optional. The Noncacheable
Region registers can also be used to control cacheablity. Memory addresses specified
by the Noncacheable Region registers are not cacheable regardless of the state of
KEN#. I/O accesses, locked reads, SMM address space accesses, and
interrupt-acknowledge cycles are never cached.
During cached code fetches, two contiguous read cycles are performed to completely
fill the 4-byte cache line. KEN# must be asserted during both read cycles to cause a
cache line fill. During memory data reads, the microprocessor performs as many read
cycles as necessary to supply the required data to complete the current operation. Valid
bits are maintained for each byte in the cache line and each block of four lines, thus
allowing data operands of less than four bytes to reside in the cache.
If two read cycles are performed with the same address (A23-A2), KEN# must be
asserted during both cycles to cache the data in these cycles. If the data is cached, the
microprocessor ignores the state of the byte enables (BHE# and BLE#) and all data on
the bus is cached. The KEN# input is ignored following reset and can be enabled using
the KEN bit in the CCRO Configuration register.
KEN# is internally connected to a pullup resistor to prevent it from floating active when
left unconnected.
LOCK#
26
LOCK (active low). This 3-state, bus-cycle-definition signal is asserted to deny access
of the CPU bus to other bus masters. The LOCK# signal may be explicitly activated
during bus operations by including the LOCK prefix on certain instructions. LOCK# is
always asserted during descriptor and page table updates, interrupt- acknowledge
sequences, and when executing the XCHG instruction. The microprocessor does not
enter the hold-acknowledge state in response to HOLD while the LOCK# output is
active.
M/IO#
23
Memory/IO. This 3-state, bus-cycle-definition signal is low during I/O read and write
cycles and is high during memory cycles.
NA#
6
Next Address Request (active low). This input requests address pipelining by the
system hardware. When asserted, the system indicates that it is prepared to accept
new bus-cycle definition and address signals (M/IO#, D/C#, W/R#, A23-A 1, BHE#, and
BLE#) from the microprocessor even if the current bus cycle has not been terminated
by assertion of READY#. If the microprocessor has an internal bus request pending and
the NA# input is sampled active, the next bus-cycle definition and address signals are
driven onto the bus.
NC
27,45,
46
Make no external connection.
Note:
NC Terminals
Connecting or terminating (high or low) any NC terminal(s) may cause unpredictable results or nonperformance of the microprocessor.
3:-8
Input/Output Signals
Table 3-2. TI486SXLC Terminal Functions (Continued)
Terminal
Name
No.
Description
NMI
38
Nonmaskable Interrupt Request. This rising-edge-sensitive input causes the processor
to suspend execution of the current instruction stream and begin execution of an NMI
interrupt service routine. The NMI interrupt service request cannot be masked by
software. Asserting NMI causes an interrupt which internally supplies interrupt vector
2h to the CPU core. External interrupt-acknowledge cycles are not necessary since the
NMI interrupt vector is supplied internally. Once NMI processing has started, no
additional NMls are processed until an IRET instruction is executed.
The microprocessor samples NMI at the beginning of each phase two (<1>2) clock period.
To assure recognition, NMI must be inactive for at least eight CLK2 periods and then be
active for at least eight CLK2 periods. Additionally, specified setup and hold times must
be met to assure recognition at a particular clock edge.
PEREQ
37
Coprocessor Request (active high). This input indicates that the coprocessor is ready
to transfer data to or from the CPU. The coprocessor can assert PEREQ in the process
of executing a coprocessor instruction. The microprocessor internally stores the current
coprocessor opcode and performs the correct data transfers to support coprocessor
operations using PEREQ to synchronize the transfer of required operands.
PEREQ is internally connected to a pulldown resistor to prevent this signal from floating
active when left unconnected.
READY#
7
Ready (active low). This input is generated by the system hardware to indicate that the
current bus cycle can be terminated. During a read cycle, assertion of READY# indicates
that the system hardware has presented valid data to the CPU. When READY# is
sampled active, the microprocessor latches the input data and terminates the cycle.
During a write cycle, READY# assertion indicates that the system hardware has
accepted the microprocessor output data. READY# must be asserted to terminate every
bus cycle, including halt and shutdown indication cycles.
RESET
33
Reset (active high). When asserted, RESET suspends all operations in progress and
places the microprocessor into a reset state. RESET is a level-sensitive synchronous
input and must meet specified setup and hold times to be properly recognized by the
microprocessor. The microprocessor begins executing instructions at physical address
location FF FFFOh approximately 400 CLK2s after RESET is driven inactive (low).
While RESET is active, the microprocessor is initialized to nonclock-doubled mode (for
the TI486SXLC2) and all other input pins, except FLT#, are ignored. The remaining
signals are initialized to their reset state during the internal processor reset sequence.
The reset signal states for the microprocessor are shown in Table 3-3.
SMADS#
20
SMM Address Strobe (active low). SMADS#, a 3-state output, is asserted instead of the
ADS# during SMM bus cycles and indicates that SMM memory is being accessed.
SMADS# floats while the CPU is in a hold-acknowledge or float state. The SMADS#
output is disabled (floated) following reset and can be enabled using the SMI bit in the
CCR1 Configuration register.
Tl486SXLC Microprocessor Bus Interface
3-9
Input/Output Signals
Table 3-2. TI486SXLC Terminal Functions (Continued)
Terminal
Name
No.
Description
SMI#
47
System Management Interrupt (active low). This 3-state, bidirectional, level-sensitive
input/output signal is an interrupt with higher priority than the NMI interrupt. SMI# must
be active for at least four CLK2 clock periods to be recognized by the microprocessor.
After the 8M I is acknowledged, the SM 1# pin is driven low by the microprocessor for the
duration of the SMI service routine. The SMI# input is ignored following reset and can
be enabled using the SMI bit in the CCR1 Configuration register.
SMI# is internally connected to a pullup resistor to prevent it from floating active when
left unconnected.
SUSP#
43
Suspend Request (active low). This input requests the microprocessor to enter
suspend mode. After recognizing SUSP# active, the processor completes execution of
the current instruction, any pending decoded instructions, and associated bus cycles.
In addition, the microprocessor waits for the coprocessor to indicate a not-busy status
(BUSY# = 1) before entering suspend mode and asserting suspend acknowledge
(SUSPA#).
SUSP# is internally connected to a pullup resistor to prevent it from floating active when
left unconnected.
SUSPA#
44
Suspend Acknowledge (active low). This output indicates that the microprocessor has
entered the suspend mode as a result of SUSP# assertion or execution of a HALT
instruction.
Vee
8
9
5-V Power Supply. All pins must be connected and used.
10
21
32
39
42
48
57
69
71
84
91
97
3-10
Input/Output Signals
Table 3-2. TI486SXLC Terminal Functions (Continued)
Terminal
Name
Vss
W/R#
No.
Description
2"
5
11
12
13
14
22
35
41
49
50
63
67
68
77
78
85
98
Ground Pins. All pins must be connected and used.
25
Write/Read. This 3-state, bus-cycle-definition signal is low during read cycles (data is
read from memory or I/O) and is high during write bus cycles (data is written to memory
or I/O).
Tl486SXLC Microprocessor Bus Interface
3-11
Input/Output Signals
3.1.2
Signal States During Reset and Hold Acknowledge
RESET is the highest priority input signal. When RESET is asserted, the microprocessor aborts any current bus cycle and establishes real-mode buscycle definition with active buses. See Table 3-3 and Section 3.3, Reset Timing and Internal Clock Synchronization, page 3-17.
The hold-acknowledge state (Th) is entered in response to assertion of the
HOLD input during which the microprocessor floats all output and bidirectional
signals, except for HLDA and SUSPA#. In the hold-acknowledge state, all inputs except HOLD, FLUSH#, FLT#, SUSP# and RESET are ignored. See
Table 3-3 and subsection 3.4.8, Hold Acknowledge State, page 3-39. The
hold-acknowledge state provides the mechanism for an external device to acquire the system bus.
Table 3-3. Signal States During Reset and Hold Acknowledge
Signal Name
Signal State
During Reset
Signal State During
Hold Acknowledge
A20M#
Ignored
Input recognized
A23-A1
1
Float
Float
ADS#
BHE#, BLE#
0
Float
BUSY#
Initiates self test
Ignored
D15-DO
Float
Float
Float
D/C#
3-12
ERROR#
Ignored
Ignored
FLT#
Input recognized
Input recognized
FLUSH#
Ignored
Input recognized
HLDA
0
HOLD
Ignored
Input recognized
INTR
Ignored
Input recogn'ized
KEN#
Ignored
Ignored
LOCK#
1
Float
M/IO#
0
Float
NA#
Ignored
Ignored
NMI
Ignored
Input recognized
PEREQ
Ignored
Ignored
READY#
Ignored
Ignored
RESET
Input recognized
Input recognized
SMADS#
Float
Float
SMI#
Ignored
Input recognized
SUSP#
Ignored
Input recognized
SUSPA#
Float
Driven
W/R#
0
Float
Bus-Cycle Definition
3.2 Bus-Cycle Definition
The bus-cycle-definition signals consist of four 3-state outputs (M/IO#, D/C#,
W/R#, LOCK#) that define the type of bus-cycle operation being performed.
Table 3-4 defines the bus cycles for the possible states of these signals.
M/IO#, D/C#, and W/R# are the primary bus-cycle-definition signals and are
driven valid as ADS# (address strobe) becomes active. During nonpipelined
cycles, the LOCK# output is driven valid along with M/IO#, D/C# and W/R#.
During pipelined addressing, LOCK# is driven at the beginning of the bus
cycle, which is after ADS# becomes active for that cycle. The bus-cycle-definition signals are active low and float while the microprocessor is in a hold-acknowledge or float state.
Table 3-4. Bus Cycle Types
MIl 0#
D/C#
W/R#
LOCK#
0
0
0
0
0
0
0
0
0
1
X
0
X
0
0
0
Bus Cycle Type
Interrupt acknowledge
I/O data read
0
I/O data write
0
X
0
0
0
Memory code read
Halt: A23-A1=2h, BHE#=1 and BLE#=O
Shutdown: A23-A1=Oh, BHE#=1 and BLE#=O
0
0
0
0
Locked memory data read
Memory data read
0
Locked memory data write
Memory data write
x = Don't care
- = Does not occur
3.2.1
Clock Doubling Using Software Control
The clock-doubled feature of the TI486SXLC2 is enabled/disabled using
Configuration Control register 0 (CCRO), bit 6. The following can be used for
software enabling/disabling of CKD:
Set CKD programming sequence:
mov
out
in
mov
or
mov
out
mov
out
aI, OCOh
22h, al
aI, 23h
ah, al
ah, 40h
aI, OCOh
22h, al
aI, ah
23h, al
;select CCRO
;read CCRO
;save in AH
iset AH<6>
iselect CCRO
iwrite CCRO
Tl486SXLC Microprocessor Bus Interface
3-13
Bus-Cycle Definition
Reset CKD programming sequence:
mov
out
in
mov
and
mov
out
mov
out
3.2.1.1
ai, OCOh
22h, al
ai, 23h
ah, al
ah, OBFh
ai, OCOh
22h, al
ai, ah
23h, al
iselect CCRO
iread CCRO
isave in AH
ireset AH<6>
iselect CCRO
iwrite CCRO
Entering Clock-Doubled Mode
The TI486SXLC2 microprocessors power up in the nonclock-doubled mode.
To enter the clock-doubled mode, set CLK2 to the desired frequency inside the
phase-locked loop (PLL) lock range (see Table 5-5 and Table 5-6) and issue
the set CKD programming sequence. Approximately 20 ~s after the final OUT
instruction has exited the processor pipeline, the PLL locks and the CPU
enters clock-doubled mode. Until the PLL is locked, the processor continues
to operate in the nonclock-doubled mode.
3.2.1.2
Clock-Scaling Sequence
When the processor is in clock-doubled mode and the CLK2 input is to be
scaled or stopped, the reset CKD programming sequence should be issued.
The final OUT instruction exiting the processor pipeline causes the CKD bit to
be reset and puts the processor into nonclock-doubled mode. This must occur
prior to scaling or stopping the CLK2 input in order to prevent a synchronization
errorfrom occurring. This may be ensured by issuing aJUMP instruction, such
as JMP $+2, before scaling CLK2.
To return the processor to clock-doubled mode, set CLK2 to the desired frequency inside the PLL lock range and issue the set CKD programming sequence. Approximately 20 ~s after the final OUT instruction has exited the processor pipeline, the PLL locks and the processor enters clock-doubled mode.
3.2.1.3
Suspend Mode
Suspend mode can be initiated when the TI486SXLC2 microprocessor is in
clock-doubled mode as long as the CLK2 input is not scaled or stopped. Suspend mode does not disable the PLL; instead, changing the CLK2 frequency
causes the PLL to lose lock.
For more detailed information on entering and exiting suspend in nonclockdoubled mode, refer to subsection 3.2.2, Power Management.
In order to get the lowest possible power state, bring the microprocessor out
of clock-doubled mode, enter the suspend mode (using software or hardware),
and stop the CLK2 input.
3-14
Bus-Cycle Definition
3.2.2
Power Management
The power-management signals allow the TI486SXLC series microprocessors to enter suspend mode. Suspend-mode circuitry allows the microprocessor to consume minimal power while maintaining the entire internal CPU state.
3.2.2.1
Suspend Request (SUSP#)
Suspend request (SUSP#) is an active-low input that requests the TI486SXLC
series microprocessors to enter suspend mode. With the TI486SXLC2 microprocessors you should follow the procedure in subsection 3.2.1 to enter nonclock-doubled mode prior to scaling or stopping the CLK2 input. After recognizing SUSP# is active, the processor completes execution of the current
instruction, any pending decoded instructions, and associated bus cycles. In
addition, the microprocessor waits for the coprocessor to indicate a not-busy
condition (BUSY#=1) before entering suspend mode and asserting suspend
acknowledge (SUSPA#). During suspend mode, internal clocks are stopped
and only the logic associated with monitoring RESET, HOLD, and FLUSH# remains active. With SUSPA# asserted, the CLK2 input to the microprocessor
can be stopped in either phase. Stopping the CLK2 input further reduces current required by the microprocessor.
To resume operation, the CLK2 input is restarted (if stopped), followed by
deassertion of the SUSP# input. The TI486SXLC2 processors can enter
clock-doubled mode (subsection 3.2.1.1, Entering Clock-Doubled Mode) once
the CLK2 input reaches the desired frequency within the PLL lock range. The
processor then resumes instruction fetching and begins execution in the
instruction stream at the point it had stopped. The SUSP# input is level sensitive and must meet specified setup and hold times to be recognized at a particular clock edge. The SUSP# input is ignored following reset and can be enabled using the SUSP bit in the CCRD Configuration register.
3.2.2.2 Suspend Acknowledge (SUSPA#)
The suspend acknowledge (SUSPA#) output indicates that the TI486SXLC
series microprocessor has entered the suspend mode as a result of SUSP#
assertion or execution of a HALT instruction. If SUSPA# is asserted and the
CLK2 input is switching, the microprocessor continues to recognize FLT#, RESET, HOLD, and FLUSH#. In addition, the TI486SXLC2 microprocessor may
stay in clock-doubled mode while the CLK2 input is switching. If suspend mode
was entered as the result of a HALT instruction, the microprocessor also continues to monitor the NMI input and an unmasked INTR input. Detection of
INTR or NMI forces the microprocessor to exit suspend mode and begin
execution of the appropriate interrupt service routine. The CLK2 input to the
processor can be stopped after SUSPA# has been asserted to further reduce
the power requirement of the microprocessor. For this case, the TI486SXLC2
microprocessor must be brought out of clock-doubled mode prior to stopping
the CLK2 input to prevent a synchronization error. The SUSPA# output is disabled (floated) following reset and can be enabled using the SUSP bit in the
CCRD Configuration register.
Tl486SXLC Microprocessor Bus Interface
3-15
Bus-Cycle Definition
Table 3-5 shows the state of the TI486SXLC series microprocessor signals
when the device is in suspend mode.
Table 3-5. Signal States During Suspend Mode
Signal Name
Signal State During
Hold Acknowledge
Signal State During HaltInitiated Suspend Mode
A20M#
Ignored
Ignored
BHE#, BLE#
0
0
BUSY#
Ignored
Ignored
015-00
Float
Float
ERROR#
Ignored
Ignored
FLT#
Input recognized
Input recognized
FLUSH#
Input recognized
Input recognized
HLOA
0
0
HOLD
Input recognized
Input recognized
INTR
Latched
Input recognized
KEN#
Ignored
Ignored
M/IO#
0
0
NA#
Ignored
Ignored
NMI
Latched
Input recognized
PEREQ
Ignored
Ignored
REAOY#
Ignored
Ignored
RESET
Input recognized
Input recognized
SMI#
Latched
Input recognized
SUSP#
Input recognized
Ignored
SUSPA#
0
0
W/R#
0
0
A23-A1
AOS#
O/C#
LOCK#
SMAOS#
3-16
Reset Timing and Internal Clock Synchronization
3.3
Reset Timing and Internal Clock Synchronization
RESET is the highest priority input signal and is capable of interrupting any
processor activity when it is asserted. When RESET is asserted, the microprocessor aborts any bus cycle. Idle, hold-acknowledge, and suspend states are
also discontinued and the reset state is established. RESET is used when the
microprocessor is powered up to initialize the CPU to a known valid state and
to synchronize the internal CPU clock with external clocks. The TI486SXLC2
microprocessors are initialized to nonclock-doubled mode upon RESET going
active.
RESET must be asserted for at least 15 CLK2 periods to ensure recognition
by the microprocessor. If the self-test feature is to be invoked, RESET must
be asserted for at least 80 CLK2 periods. RESET pulses of less than 15 CLK2
periods may not have sufficient time to propagate throughout the microprocessor and may not be recognized. RESET pulses of less than 80 CLK2 periods
followed by a self-test request may incorrectly report a self-test failure when
no true failure exists.
Provided the RESET falling edge meets specified setup and hold times, the
internal processor clock phase is synchronized as illustrated in Figure 3-2.
The TI486SXLC internal processor clock is half the frequency of the CLK2 input and each CLK2 cycle corresponds to an internal CPU clock phase (<1».
Phase two (<1>2) of the internal clock is defined to be the second rising edge of
CLK2 following the falling edge of RESET. The TI486SXLC2 internal core
clock is the same frequency as the CLK2 input and the internal bus interface
clock is half the frequency of the CLK2 input. Phase two of the internal clock
is defined to be the second rising edge of CLK2 following the falling edge of
RESET.
Figure 3-2. Internal Processor Clock Synchronization
2 or <1>1
2 or <1>1
<1>2
CLK2
I
I
~
RESET
I
I
INTERNAL~
PROCESSOR
CLOCK
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~~__-IV-
Tl486SXLC Microprocessor Bus Interface
3-17
Reset Timing and Internal Clock Synchronization
Following the falling edge of RESET (and after self test if it was requested),
the microprocessor performs an internal initialization sequence for approximately 400 CLK2 periods. The microprocessor self-test feature is invoked if
the BUSY# input is in the active (low) state when RESET falls inactive. The
self-test sequence requires approximately (2 20 + 60) CLK2 periods to complete. Even if the self test indicates a problem, the microprocessor attempts
to proceed with the reset sequence. Figure 3-3 illustrates the bus activity and
timing during the microprocessor reset sequence.
Figure 3-3. Bus Activity From RESET Until First Code Fetch
~
Reset
I
~15ClK2 periods if not
I
going to request self test.
I ~ 80 ClK2 periods before
I requsting self-test.
CLK2
RESET
ClK
(Internal)
BUSY#
J1IU1JlJ1J
---?:,------'oS
x?oooa
I
~\
~
.10IIII
1
1
(
I
Internal
Initialization
If self test is performed, add
20 20 + 60* to these numbers
1
2
3
Cycle 1
Nonplpelined
1
(Read)
T1
T2
I
~7 ~8 ~9 (~2'~3~4;';95'
I U U WI
\
.1
YU YL
· Approximately
\
I
1<\>21<1>11<1>21<1>11<1>2 <\>1 <1>21<1>11<1>21
\. . r-\.
r1\.
\.../
~( 1 ' - . / 1 " -
r1\
High for no Self Test (see Note)
\~ ~
.~
Low to Begin Self Test
ERROR#~~ma
BHE#'BLE#,~
I
~ lO~
if
W/R#, M/IO#,
HLDA~
A23-A1 ~
"
IS
II
'i';
;~
',';
O/C#, ~ I High
lOCK#
ADS#
U to 30 ClK2
~
~Hi;~
I
I
IV
i\
:
Valid
:
Valid
I
"~
,/,
NA#~~ma"
READY#~~~
015-00
~--~s------ (Floating) ----.;c,-----.;c,--i---t-
SUSPA#
~--~s------ (Floating) ----.;c,-----.;c,--I---.L,
Note:
1
1
1
I
BUSY# should be held stable for 80 ClK2 periods before and after the ClK2 period in which RESET falling edge occurs.
Upon completion of self-test, the EAX register contains 0000 OOOOh if the
microprocessor passed its internal self test with no problems detected. Any
nonzero value in the EAX register indicates that the microprocessor is faulty.
3-18
Bus Operation and Functional Timing
3.4 Bus Operation and Functional Timing
The TI486SXLC series microprocessor communicates with the external system through separate, parallel buses for data and address. This is commonly
called a demultiplexed address/data bus. This demultiplexed bus eliminate,s
the need for address latches required in muttiplexed address/data bus configurations where the address and data are presented on the same pins at different times.
TI486SXLC series microprocessor instructions can act on memory data operands consisting of 8-bit bytes, 16-bit words, or 32-bit double words. The microprocessor bus architecture allows for bus transfers of these operands without
restrictions on physical address alignment. Any byte boundary may require
more than one bus cycle to transfer the operand. This feature is transparent
to the programmer.
The microprocessor data bus (D15-DO) is a 16-bit-wide bidirectional bus. Th,e
microprocessor drives the data bus during write bus cycles, and the external
system hardware drives the data bus during read bus cycles. The address bus
provides a 24-bit value using 23 signals for the 23 upper-order address bits
(A23-A1), defining which 16-bit word is being accessed, and two byte-enable
signals (BHE# and BLE#) to directly indicate which of the two bytes within the
word is active.
Every bus cycle begins with the assertion of the address strobe (ADS#). ADS#
indicates that the microprocessor has issued a new address and new buscycle-definition signals. A bus cycle is defined by four signals: M/IO#, W/R#,
D/C#, and LOCK#. M/IO# defines if a memory or I/O operation is occurring,
W/R# defines the cycle to be read or write, and D/C# indicates whether a data
or control cycle is in effect. LOCK# indicates that the current cycle is a locked
bus cycle. Every bus cycle completes when the system hardware returns
READY# asserted.
The TI486SXLC series microprocessor performs the following bus-cycle
types:
o Memory read
o Locked memory read
o Memory write
o Locked memory write
o I/O read (or coprocessor read)
o I/O write (or coprocessor write)
o Interrupt acknowledge (always locked)
o HalVshutdown
When the microprocessor has no pending bus requests, the bus enters the idle
state. There is no encoding of the idle state on the bus-cycle-definition signals;
however, the idle state can be identified by the absence of further assertions
of ADS# following a completed bus cycle.
It should be noted that all bus diagrams apply for all TI486SXLC series microprocessors. The TI486SXLC2 clock-doubled feature does not change the external microprocessor bus interface.
T1486SXLC Microprocessor Bus Interface
3-19
Bus Operation and Functional Timing
3.4.1
Bus Cycles Using Nonpipelined Addressing
The shortest time unit of bus activity is a bus state, commonly called a T state.
A bus state is one internal processor clock period in duration (two CLK2 periods in nonclock-doubled mode and one CLK2 period in clock-doubled mode).
A complete data transfer occurs during a bus cycle, composed of two or more
bus states.
3.4.1.1
Nonpipelined Bus States
The first state of a nonpipelined bus cycle is called T1. During phase one (<1>1,
first CLK2) of T1, the address bus and bus-cycle-definition signals are driven
valid and,to signal their availability, address strobe (ADS#) is simultaneously
asserted.
The second bus state of a nonpipelined cycle is called T2. T2 terminates a bus
cycle with the assertion of the READY# input and valid data is either input or
output depending on the bus-cycle type. The fastest microprocessor bus cycle
requires only these two bus states. READY# is ignored at the end of the T1
state.
Three consecutive bus read cycles, each consisting of two bus states, are
shown in Figure 3-4.
Figure 3-4. Fastest Nonpipelined Read Cycles
Cycle 1
I
Cycle 3
Nonpipelined
(Read)
Cycle 2
Nonpipelined ~~ Nonpipelined
(Read)
I
(Read)
T1
T2
T2
T1
I
I
I
<1> 1 I <1>2 I <1> 1 I <1>2 I <1>"1 I <1>2 I <1> 1 I
~
I
I
I
<1>2
I
I
CLK2
I
A23-A1, BHE#,
BLE#, M/IO#,
O/C#, W/R#
AOS#
NA#
REAOY#
~
I
I
015-00
(Input During Read)
I
I
I
V
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~
I
I
I
I
I
I
I
I
~
I
3-20
V~lid2
I
:1
I
I
I
~
+id3
l\
:1
I
l'--
I
I
I
I
I
I
I
I
I
I
I
I
~
I
I
I
I
I
I
I
I
~alid3
~
~
~
~
~--t--~--t--~--t--~
+id1
I
Note:
I
~
+d1
I
LOCK#
I
I
+id2
I
Fastest nonpipelined bus cycles consist of T1 and T2.
I
I
I
I
Bus Operation and Functional Timing
3.4.1.2
Nonpipelined Read and Write Cycles
Any bus cycle can be performed with nonpipelined address timing. Figure 3-5
shows a mixture of read and write cycles with nonpipelined address timing.
When a read cycle is performed, the microprocessor floats its data bus and the
externally addressed device then drives the data. The microprocessor requires that all data-bus pins be driven to a valid logic state (high or low) at the
end of each read cycle, when READY# is asserted. When a read cycle is acknowledged by READY# asserted in the T2 bus state, the microprocessor
latches the information present at its data-bus pins and terminates the cycle.
When a write cycle is performed, the data bus is driven by the microprocessor
beginning in phase two of T1. When a write cycle is acknowledged, the write
data remains valid throughout phase one of the next bus state to provide writedata hold time.
Figure 3-5. Various Nonpipelined Bus Cycles (No Wait States)
,
,
,
,
,
CLK2
Idle
Ti
,
,
,
,t4
,
I
I
W/R#~
ADS#
I
I
,
,
,
Cycle 2
Nonpipelined
(Read)
~
T1
==
,
A23-A1.~
BHE#, BLE#,
M/IO#, D/C#
Cycle 1
Nonpipelined
(Write)
T2
V~lid
1
,
T2
T1
~
I
~
I
I
I
I
Cycle 3
Nonpipelined
(Write)
~
,
,
I
,
,
,
Vflid2
I
I
T2
~
I
I
.,,
,
Idle
Ti
,
,
,
Cycle 4
Nonpipelined
(Read)
,t4
T1
~
~
V~lid3
V
,
,
I
I
I
I
I
T1
,
I
I
I
,
,
I
I
I
I
I
I
I
I
I
T2
,
,
,
.,,
Idle
Ti
,
I
V~lid4
I
I
~
I
I
I
I
I
I
NA#
REAOY#~i
_
LOCK#
!
+
End Cycle 1
Valid 1
X
i
Note:
~
:
End
9h
•
>+--1--<$)---
_ : . - :
End Cycle 2
Valid 2
I
015- 00
+.
_ :
CY~
!
End Cycle 4
Valid 4
~
Tl486SXLC Microprocessor Bus Interface
3-21
Valid 3
1---+-< : O~1: >1--$\:
i
out~
Idle states are shown here for diagram variety only.
Bus Operation and Functional Timing
3.4. 1.3
Nonpipelined Wait States
Once a bus cycle begins, it continues until acknowledged by the external system hardware using the READY# input. Acknowledging the bus cycle at the
end of the first T2 results in the shortest possible bus cycle, requiring only T1
and T2. If READY# is not immediately asserted however, T2 states are repeated indefinitely until the READY# input is sampled active. These intermediate T2 states are referred to as wait states. If the external system hardware
is not able to receive or deliver data in two bus states, it withholds the READY#
signal and at least one wait state is added to the bus cycle. Thus, on an address-by-address basis the system is able to define how fast a bus cycle completes.
Figure 3-6 illustrates nonpipelined bus cycles with one wait state added to
cycles 2 and 3. READY# is sampled inactive at the end of the first T2 state in
cycles 2 and 3. Therefore, the T2 state is repeated until READY# is sampled
active at the end of the second T2 and the cycle is then terminated. The microprocessor ignores the READY# input at the end of the T1 state.
Figure 3-6. Various Nonpipelined Bus Cycles With Different Numbers of Wait States
I
I
Idle
:
I
Ti
I
I
Cycle 1
Nonpipelined
I
I
Cycle 2
Nonpipelined
~
(Read)
~
(Write)
I
T1
T2
I . T1
I
I
Idle
~
T2
T2
I
Ti
I
I
Cycle 3
Nonpipelined
~
(Read)
I
T1
I
I
Idle
~
T2
T2
I
Ti
CLK2
I
I
___
I
I
B~~:~~~~ ~~~~~~ va~;li_d_1 ~~~ ~ va_li_d~2:
~
__
:
__
__
AOS#
I
I
____
I
V:
W/R#I.
I
I
I
I
I
__
~I::~
I
~
I
NA#~
I
I
-+~~~~~__~:__v_al_id~~~ ~~~~
I_I
I
I
I
I
I
I
'----J
I
I
I
I
I
~~----~---
_ _
~
READY#~: ~ i \%l~!~: I!llt
~+ ~
LOCK#
015-00
Note:
3-22
~
_
~
I;
End Cycle 1
V~lid 1
X
I:
:
,valid 2,
i
i i ii-$:
<
i
I
-.,---+----+-
I
In 1
Idle states are shown here for diagram variety only,
;
End
~
CY~~
~
:1
,Valid
I
•
!
End Cycle 3
_
~
~
: : }-I---+---+i iii i
i$ -
Out 2
In 3
-
Bus Operation and Functional Timing
3.4.1.4
Initiating and Maintaining Nonpipelined Cycles
The bus states and transitions for nonpipelined addressing are illustrated in
Figure 3-7. The bus transitions between four possible states: T1, T2, Ti, and
Th. Active bus cycles consist of T1 and T2 states, with T2 being repeated for
wait states. Bus cycles always begin with a single T1 state. T1 is always followed by a T2 state. If a bus cycle is not acknowledged during a given T2 and
NA# is inactive, T2 is repeated resulting in a wait state. When a cycle is acknowledged during T2, the following state is T1 of the next bus cycle if a bus
request is pending internally. If no internal bus request is pending, the Ti state
is entered. If the HOLD input is asserted and the microprocessor is ready to
enter the hold-acknowledge state, the Th state is entered.
Figure 3-7. Nonpipelined Bus States
HOLD Asserted
HOLD Negated
No Request
HOLD Asserted
READY# Asserted
HOLD Asserted
READY# Asserted
HOLD Negated
No Request
Always
Request Pending
HOLD Negated
READY# Asserted
HOLD Negated
Request Pending
Bus States:
T1
T2
Ti
Th
-
First clock of a nonpipelined bus cycle (CPU drives new address and asserts ADS#)
Subsequent clocks of a bus cycle when NA# has not been sampled asserted in the current bus cycle
Idle state
Hold acknowledge (CPU asserts HLDA)
The fastest bus cycle consists of two states: T1 and T2.
Tl486SXLC Microprocessor Bus Interface
3-23
Bus Operation and Functional Timing
Because of the demultiplexed nature of the bus, the address pipelining option
provides a mechanism for the external hardware to have an additional T state
of access time without inserting a wait state. After the reset sequence and following any idle bus state, the processor always uses nonpipelined address
timing. Pipelined or nonpipelined address timing is then determined on a
cycle-by-cycle basis using the NA# input. When address pipelining is not used,
the address and bus-cycle definition remain valid during all wait states. When
wait states are added and nonpipelined address timing is necessary, negate
NA# during each T2 state of the bus cycle except the last one.
3.4.2
Bus Cycles Using Pipelined Addressing
The address pipelining option allows the system to request the address and
bus-cycle definition of the next internally pending bus cycle before the current
bus cycle is acknowledged with READY# asserted. If address pipelining is
used, the external system hardware has an extra T state of access time to
transfer data. The address pipelining option is controlled on a cycle-by-cycle
basis by the state of the NA# input.
3.4.2.1
Pipelined Bus States
Pipelined addressing is always initiated by asserting NA# during a nonpipelined bus cycle. Within the nonpipelined bus cycle, NA# is sampled at the beginning of phase two of each T2 state and is only acknowledged by the microprocessor during wait states. When address pipelining is acknowledged, the
address (BHE#, BLE#, and A23-A 1) and bus-cycle definition (W/R#, D/C#,
and M/IO#) of the next bus cycle are driven before the end of the nonpipelined
cycle. The address status output (ADS#) is asserted simultaneously to indicate validity of these signals. Once in effect, address pipelining is maintained
in successive bus cycles by continuing to assert NA# during the pipelined bus
cycles.
As in nonpipelined bus cycles, the fastest bus cycles using pipelined address
require only two bus states. Figure 3-8 illustrates the fastest read cycles using
pipelined address timing. The two bus states for pipelined addressing are T1 P
and T2P or T1 P and T21. The T1 P state is entered following completion of the
bus cycle in which the pipelined address and bus-cycle-definition information
was made available and is the first bus state of every pipelined bus cycle. In
other words, the T1 P state follows a T2 state if the previous cycle was nonpipelined, and follows a T2P state if the previous cycle was pipelined.
3-24
Bus Operation and Functional Timing
Figure 3-8. Fastest Pipelined Read Cycles
Cycle 1
Pipelined
(Read)
I
~
Cycle 2
Pipelined
(Read)
Cycle 3
Pipelined
(Read)
CLK2
A23-A1,BHE#, --~------~~----~------~~----~------~~------~--BLE#, M/IO#,
O/C#, W/R# --..------_r-~----...,..------~...Jo..----_.,..------~~------....._---
AOS#
NA#
I
I
R~O~
I
I
LOCK#
015-00
(InputOuringRead)
~
~
~
I
Note:
~alid
__
I
~
1
~alid
2
~
~alid
~
3
1,__ ~ __ 1,__ ~ __ I, __ ~
~
,
I
~
,
I
~
,
I
Fastest pipelined bus cycles consist of T1 P and T2P.
Within the pipelined bus cycle, NA# is sampled at the beginning of phase two
(<1>2) of the T1 P state. If the microprocessor has an internally pending bus request and NA# is asserted, the T1 P state is followed by a T2P state and the
address and bus-cycle definition for the next pending bus request is made
available. If no pending bus request exists, the T1 P state is followed by a T21
state regardless of the state of NA# and no new address or bus-cycle information is driven.
The pipelined bus cycle is terminated in either the T2P or T21 states with the
assertion of the READY# input and valid data is either input or output depending on the bus cycle type. READY# is ignored at the end of the T1 P state.
3.4.2.2 Pipelined Read and Write Cycles
Any bus cycle can be performed with pipelined address timing. When a read
cycle is performed, the microprocessor floats its data bus and the externally
addressed device drives the data. When a read cycle is acknowledged by
READY# asserted in either the T2P or T21 bus state, the microprocessor
latches the information present at its data pins and terminates the cycle.
When a write cycle is performed, the data bus is driven by the microprocessor
beginning in phase two (<1>2) of T1 P. When a write cycle is acknowledged, the
Tl486SXLC Microprocessor Bus Interface
3-25
Bus Operation and Functional Timing
write data remains valid throughout phase one (-i--i-~<
~
I
Out 3 I
. :
V+d 4
I
~
~
_6
I
>-t-~i
Following any idle bus state (Ti), addresses are nonpipelined bus cycles, NA# is sampled only during wait states. Therefore, to begin address pipelining during a group of nonpipelined bus cycles requires a nonpipelined cycle with at least one
wait state (cycle 2 above).
Tl486SXLC Microprocessor Bus Interface
3-29
Bus Operation and Functional Timing
The complete bus-state-transition diagram, including operation with pipelined
address, is given in Figure 3-12. This is a superset of the diagram for nonpipelined address. The three additional bus states for pipelined address are
shaded.
Figure 3-12. Complete Bus States
HOLD Asserted
READY# Asserted.
HOLD Asserted
NA# Asserted •
(HOLD Asserted +
No Request)
READY# Asserted.
HOLD Asserted
HOLD Negated.
Request Pending
HOLD Asserted
_-r- READY# Asserted.
HOLD Negated.
No Request
Request Pending.
HOLD Negated
READY# Asserted.
HOLD Negated.
No Request
(No Request +
HOLD Asserted) •
NA# Asserted •
READY# Negated
I
I
I
I
I
I
I
I
NA# Negatedl
READY# Asserted.
HOLD Negated.
Request Pending
READY# Asserted.
HOLD Negated.
Request Pending
READY# Negated.
NA# Asserted •
HOLD Negated
Request Pending
READY# Negated
Request Pending
HOLD Asserted
NA# Asserted •
HOLD Negated.
Request Pending
READY# Asserted
READY# Negated
Bus States:
T1 - First clock of a nonpipelined bus cycle (CPU drives new address and asserts ADS#)
T2 - Subsequent clocks of a bus cycle when NA# has not been sampled asserted in the current bus cycle
T21 - Subsequent clocks of a bus cycle when NA# has been sampled asserted in the current bus cycle but there
is not yet an internal bus request pending (CPU does not drive a new address or assert ADS#)
T2P - Subsequent clocks of a bus cycle when NA# has been sampled asserted in the current bus cycle and
there is an internal bus request pending (CPU drives new address and asserts ADS#)
T1 P - First clock of a pipelined bus cycle
Ti - Idle state
Th - Hold acknowledge state (CPU asserts HLDA)
3-30
Bus Operation and Functional Timing
3.4.3
Locked Bus Cycles
When the LOCK# signal is asserted, the TI486SXLC series microprocessors
do not allow other bus master devices to gain control of the system bus.
LOCK# is driven active in response to executing certain instructions with the
LOCK prefix. The LOCK prefix allows indivisible read/modify/write operations
on memory operands. LOCK# is also active during interrupt-acknowledge
cycles.
LOCK# is activated on the CLK2 edge that begins the first locked bus cycle
and is deactivated when READY# is returned at the end of the last locked bus
cycle. When using nonpipelined addressing, LOCK# is asserted during
phase one (--r t---i---l
I. (Floating) I
I
I
1
1
I
1
Bus Operation and Functional Timing
3.4.5.2
Shutdown Indication Cycle
Shutdown occurs when a severe error is detected that prevents further processing. The TI486SXLC series microprocessor shuts down as a result of a
protection fault while attempting to process a double fault as well as the conditions referenced in Chapter 2, Programming Interface. A shutdown indication
cycle is performed signaling its entrance into the shutdown state. The shutdown indication cycle is identified by the state of the bus-cycle-definition signals (M/IO#=1, D/C#=O, W/R#=1, LOCK#=1) and an address of Oh
(A23-A 1=0, BHE#=1 , BLE#=O). The shutdown indication cycle must be acknowledged by asserting READY#. A shutdown microprocessor resumes
execution only when NM lor RESET is asserted. Figure 3-15 illustrates a shutdown cycle using pipelined addressing.
Figure 3-15. Pipelined Shutdown Cycle
I
Cycle 1
Pipelined
(Read)
1
1
1
.,...
I
I...
T1P
T2P
,
1
I
I
I
1
Idle
1
~
~
I
1
1
Cycle 2
Pipelined
(Shutdown)
,
I
T1P
T2P
,
Ti
Ti
Ti
Ti
1
CLK2
BHE#
M/IO#
:7
.......&.---'""\
Valid 1
W/R# - - r - - - - f
A23-A1,
BLE#,
D~#
Valid 1
remains
11~" CPU
shutdown until NMI, or
,
1
1
1
Shutdown cycle
~II
1
I
1
--r·-----~~----~I------~~~~~~~~~~~~~~~~~~~
:
:
-t,l
-+,I_ _
ADS#I
I
i\
I
I
!I
1
1
V
1
,I
I,
I,
!,
I,
I
I
I
I
I
I
I
I
I
I
NA#~ ~
~i~i
READY#
1
1
1
i
I
1
I
___
t i l
I
I
1
1
I
I:
1
I
1
1
1
1
1
1
1
1
1
1
~
(
~-t--~-<
undefin~
)--~
~I~
I
I
Shutdown cycle must be acknowledged by asserting READY#.
Wait states may be added to th,e cycle if desired.
vali~1
LOCK#
D1S-DO
RESET is
a~serted.
BLE# is IIOW for
I
(Floating)
t---+---~
i l l
I
,
1
Tl486SXLC Microprocessor Bus Interface
1
1
,
,
3-35
Bus Operation and Functional Timing
3.4.6
Internal Cache Interface
The TI486SXLC cache is an 8K-byte write-through unified instruction/data
cache with lines that are allocated only during memory read cycles. The cache
is configured as two-way set associative, and the cache organization consists
of 1024 sets each containing two lines of four bytes each.
3.4.6.1
Cache Fills
Any unlocked memory-read cycle can be cached by the TI486SXLC series microprocessor. The microprocessor does not cache accesses automatically to
memory addresses specified by the Noncacheable-Region registers. Additionally, the KEN# input can be used to enable caching of memory accesses
on a cycle-by-cycle basis. The microprocessor acknowledges the KEN# input
only if the KEN enable bit is set in the CCRO Configuration register.
As shown in Figure 3-16 and Figure 3-17, the microprocessor samples the
KEN# input one CLK2 before READY# is sampled active. If KEN# is asserted
and the current address is not set as noncacheable per the Noncacheable-Region registers, the microprocessor fills two bytes of a line in the cache with the
data present on the data bus pins. The states of BHE# and BLE# are ignored
if KEN# is asserted for the cycle.
Figure 3-16. Nonpipelined Cache Fills Using KEN# (With Different Numbers of Wait States)
I
Cycle 1
Nonpipelined
(Read-Cache Fill)
I
I
~
Cycle 2
Nonpipelined
(Read-Cache Fill)
CLK2
A23-A1, BHE#,
BLE#,
O/C#, M/IO#, W/R#
~
+id1
i\
I
V
I
AOS#
NA#
KEN#
REAOY#
LOCK#
015-00
(Input Ouring Read)
I
I
I
I
I
I
I
I
I
~
I
I
I
I
~
I
I
Valid2 :
I
I
I
I
•
I
I
i\I
V
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~
I
I
I
I
I
I
-I
I
I
I
I
I
I
I
I
I
~
~ __l __ ~ __ L
___J__ ~_J
~
I
3-36
I
I
Valid2 :
+d1
I
I
I
I
I
I
I
•
I
I
I
Bus Operation and Functional Timing
Figure 3-17. Pipelined Cache Fills Using KEN# (With Different Numbers of Wait States)
CLK2
A23-A1, BHE#,
Valid 1
Valid 2
BLE#,O/C#,
M/IO#, W/R# -"'---~~"""--.,...----..,.----!l-~--
Valid 3
. . . . -------
AOS#
NA#
KEN#
REAOY#
LOCK#
X
Valid 1
X
Valid 2
X
Valid 3
015-00
(Input During Read)
3.4.6.2
Flushing the Cache
To maintain cache coherency with external memory, the TI486SXLC series microprocessor cache contents should be invalidated when previously cached
data is modified in external memory by another bus master. The microprocessor invalidates the internal cache contents during execution of the INVD and
WBINVD instructions following assertion of HLDA if the BARB bit is set in the
CCRD Configuration register or following assertion of FLUSH# if the FLUSH
bit is set in CCRD.
The microprocessor samples the FLUSH# input on the rising edge of CLK2
corresponding to the beginning of phase two (<1>2) of the internal processor
clock. If FLUSH# is asserted, the microprocessor invalidates the entire contents of the internal cache. The actual point in time where the cache is invalidated depends upon the internal state of the execution pipeline. FLUSH# must
be asserted for at least two CLK2 periods and must meet specified setup and
hold times to be recognized on a specific CLK2 edge.
Tl486SXLC Microprocessor Bus Interface
3-37
Bus Operation and Functional Timing
3.4.7
Address Bit-20 Masking
The TI486SXLC series microprocessor can be forced to provide 8086 1M-byte
address wraparound compatibility by setting the A20 bit in the CCRO Configuration register and asserting the A20M# input. When the A20M# is asserted,
the 20th bit in the address to both the internal cache and the external bus pin
is masked (zeroed).
As shown in Figure 3-18, the microprocessor samples the A20M# input on the
rising edge of CLK2 corresponding to the beginning of phase two (<1>2) of the
internal processor clock. If A20M# is asserted and paging is not enabled, the
microprocessor masks the A20 signal internally starting with the next cache
access and externally starting with the next bus cycle. If paging is enabled, the
A20 signal is not masked regardless of the state of A20M#. A20 remains
masked until the access following detection of an inactive state on the A20M#
pin. A20M# must be asserted for a minimum of two CLK2 periods and must
meet specified setup and hold times to be recognized on a specific CLK2 edge.
Figure 3-18. Masking A20 Using A20M# During Burst of Bus Cycles
1
Idle
1
.14
Cycle 1
Nonpipelined
(Write)
1
Ti
1
1
Cycle 2
Nonpipelined
(Read)
1
1
.14
1
.~
1
T1
T2
1
T1
T2
T2P
1
Cycle 3
Pipelined
(Write)
Cycle 4
Pipelined
(Write)
1
1
.. 14
T2P
1
T1P
CLK2
1
1
A19-A1'~
A23-A21,
BHE#, BLE#,
M/IO#, D/C#
1
V~lid1 ~
I
W/R#
ADS#
A20M#
3-38
1
1
I
+d2
~
1
m~~'-l--l' '-_--+-1
--..if
I
~
1
Idle
.I~
1
1
T1P
1
1
+id4
T21
1
Ti
Bus Operation and Functional Timing
An alternative to using the A20M# pin is provided by the NCO bit in the CCRO
Configuration register. The microprocessor does not automatically cache
accesses to the first 64K bytes and to 1M byte + .64K bytes if the NCO bit is set.
This prevents data within the wraparound memory area from residing in the
internal cache and eliminates the need for masking A20 to the internal cache.
3.4.8
Hold-Acknowledge State
The hold-acknowledge state provides the mechanism for an external device
in a TI486SXLC microprocessor system to acquire the system bus while the
microprocessor is held in an inactive bus state. This allows external bus
masters to take control of the microprocessor bus and directly access system
hardware in a shared manner. The microprocessor continues to execute
instructions out of the internal cache (if enabled) until a system bus cycle is
required.
The hold-acknowledge state (Th) is entered in response to assertion of the
HOLD input. In the hold-acknowledge state, the microprocessor floats all output and bidirectional signals, except for HLDA and SUSPA#. HLDA is asserted
as long as the microprocessor remains in the hold-acknowledge state and all
inputs except HOLD, FLUSH#, FLT#, SUSP# and RESET are ignored.
State Th can be entered directly from a bus-idle state, as in Figure 3-19, or
after the completion of the current physical bus cycle if the LOCK signal is not
asserted, as in Figure 3-20 and Figure 3-21. The CPU samples the HOLD input on the rising edge of CLK2 corresponding to the beginning of phase one
(<1>1) of internal processor clock. HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold requirements are met in every bus state.
The hold-acknowledge state is exited in response to the HOLD input being negated. The next bus start is an idle state (Ti) if no bus request is pending, as
in Figure 3-19. If an internal bus request is pending, as in Figure 3-20 and
Figure 3-21 , the next bus state is T1. State Th is also exited in response to
RESET being asserted. If HOLD remains asserted when RESET goes inactive, the microprocessor enters the hold-acknowledge state before performing
any bus cycles provided HOLD is still asserted when the CPU is ready to perform its first bus cycle.
If a rising edge occurs on the edge-triggered NMI input while in state Th, the
event is remembered as a nonmaskable interrupt 2 and is serviced when the
state is exited.
T1486SXLC Microprocessor Bus Interface
3-39
Bus Operation and Functional Timing
Figure 3-19. Requesting Hold From Bus-Idle State
I
I
I
I
Idle
Ti
~
I
I
.1
Hold Acknowledge
Th
I
I
Th
I
I
I
Th
I
Idle
Ti
CLK2
III
HOLD
(Note 1)
I
HLDA
I
i
I
I
IV
~
~
A23-A1, BHE#, BLE#,
D/C#, M/IO#, W/R# _
ADS#
(Note 2)
I
I
I
I
~~~___
i
I
I·
1\
Ii
I
I.
i
I
I
I
---+
I i i
- . :I
-' (Floating) ~I - - - - I
l
I
I
I
I
I
~
I
I
I ,
I
I
I ~----I-. (Floating) l _____ LI
I
I
I
I
I
-----i
NA#~
~ADW
LOCK#
D15-DO Notes:
II
II
_
_
I
----1-' (Floating) 1----I
I
I
I
I
I
I
I
------I-------l-, (Floating) ..1------.1-------1
I
I
I
I
I
I
1) HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold requirements are
met in every bus state. Violating setup or hold requirements will result in incorrect operation.
2) For maximum design flexibility the CPU has no internal pullup resistors on its outputs. External pullups may be required on ADS# and other outputs to keep them negated during hold-acknowledge period.
3-40
Bus Operation and Functional Timing
Figure 3-20. Requesting Hold From Active Nonpipelined Bus
Hold Acknowledge
Cycle 1
Nonpipelined
(Read)
T1
T2
Th
T2
Cycle 2
Nonpipelined
(Write)
Th
T1
T2
CLK2
HOLD
(See Note)
I
I
HOLD asserted no later
than READY# asserted
HLDA
A23-A1, BHE#,
BLE#, BLE#,
D/C#, M/IO#, W/R#
I
I
_~,..-_--i._ _ _--l...._-+-_""
I
--,!,-~--..,.....---..,...--+-~
(FIO~,ting)
,
_--i---+-~
,
,
,
r--
I
I
,~-- (Floflting)
ADS#
...
I
I ,..---....I:~--
---K,'"--___
.
I
,
I
'1/
---1\1'
.
\l""l"'a_lid_2_ _
,
~
'-------",
NA#
READY#
(Negated, or last locked cycle)
LOCK#
015-00
I
:
Valid 1 :
I
I
I
-i----~,
,
,
Note:
,
(Floating)
,
(Florting)
I
+-6 '~I
(Flolting)
,
,
I
I
:
---K----.. .
\l-al-id-2-.......
I
---~-<
:
I
'----------,
Out 2
I
,
HOLD is a synchronous input and can be asserted at any CLK2 edge provided setup and hold requirements are met in
every bus state. Violating setup or hold requirements will result in incorrect operation.
Tl486SXLC Microprocessor Bus Interface
3-41
Bus Operation and Functional Timing
Figure 3-21. Requesting Hold from Active Pipelined Bus
Cycle 1
Pipelined
(Write)
T21
T21
T1P
Cycle 2
Nonpipelined
(Read)
Hold Acknowledge
Th
Th
T1
1
T2
CLK2
HOLD
(See Note) ~~~
HLDA
1
I
A23-A1, BHE#,
I
I
----r--~~~~~~~~'"
BLE#, D/C#,
M/IO#, W/R# -T"""--+---+-~~~~~~~-¥
- - (Floating)
I
1
READY#
J
~
D15-DO
V
I
~
II~I
~:~:
I
I
I
~
; Valid 1 ;
I
1
O~t X
i
I
Note:
I
•
V(Negated. or last locked cycle)
LOCK#
Valid 2
,..-+--+-----i----.....' - - - (FI~ating) - - {
I
ADS#
NA#
I
____________......
---K11,.."----...,1---.....,
O~t
1
1
r--
1
:
:
I
1
1
(Flatting) - - - {
:
:
. Valid 2
.
}-r--- (Fla~ting) --l--~
I
1
1
I
I
1
1
HOLD is a synchronous input and can be asserted at any CLK2 edge provided setup and hold requirements are met in
every bus state. Violating setup or hold requirements will result in incorrect operation.
3.4.9 Coprocessor Interface
The data-bus, address-bus, and bus-cycle-definition signals, as well as the coprocessor interface signals (PEREQ, BUSY#, ERROR#), are used to control
communication between the TI486SXLC microprocessor and a coprocessor.
Coprocessor or ESC opcodes are decoded by the microprocessor and the opcode and operands are then transferred to the coprocessor via liD port accesses to addresses 80 00F8h, 80 OOFCh, or 80 OOFEh. Address 80 00F8h
functions as the control-port address and 80 OOFCh and 80 OOFEh are used
for operand transfers.
3-42
Bus Operation and Functional Timing
Coprocessor cycles can be either read or write and can be either nonpipelined
or pipelined. Coprocessor cycles must be terminated by READY# and, as with
any other bus cycle, can be terminated as early as the second bus state of the
cycle.
BUSY#, ERROR# and PEREQ are asynchronous level-sensitive inputs used
to synchronize CPU and coprocessor operation. All three signals are sampled
at the beginning of phase one (2) CLK2 rising
edge and must meet specified setup and hold times to be recognized at a particular CLK2 edge. The time from assertion of SUSP# to activation of SUSPA#
varies depending on which instructions were decoded prior to assertion of
SUSP#. The minimum time from SUSP# sampled active to SUSPA# asserted
is two CLK2s. As a maximum, the microprocessor can execute up to two
instructions and associated bus cycles prior to asserting SUSPA#. The time
required for the microprocessor to deactivate SUSPA# once SUSP# has been
sampled inactive is four CLK2s.
Figure 3-24. SUSP#-Initiated Suspend Mode
1
<1>1 I <1>2
1
<1>1 I
1
<1>2
1
<1>1 I
<1>2
1 I
2
<1>1 I
<1>2
1 I
2
CLK2
SUSP#
BUSY#
1
2 CLK2s
1
~ Min ---.1
14-------
4 CLK2s
----6
1
SUSPA#
Tl486SXLC Microprocessor Bus Interface
3-45
Bus Operation and Functional Timing
If the microprocessor is in a hold-acknowledge state and SUSP# is asserted,
the processor mayor may not enter suspend mode depending on the state of
the microprocessor internal execution pipeline. If the microprocessor is in a
SUSP#-initiated suspend state and the CLK2 input is not stopped, the processor recognizes and acknowledges the HOLD input and stores the occurrence
of FLUSH#, NMI, and INTR (if enabled) for execution once suspend mode is
exited.
3.4.11.2 HALT-Initiated Suspend Mode
The TI486SXLC series microprocessor also enters suspend mode as a result
of executing a HALT instruction. The SUSPA# output is asserted no more than
17 CLK2s following a READY# sampled active for the HALT bus cycle as
shown in Figure 3-25. Suspend mode is then exited upon recognition of an
NMI or an unmasked INTR. SUSPA# is deactivated 12 CLK2s after sampling
of an active NMI or unmasked INTR. If the microprocessor is in a HALT-initiated suspend mode and the CLK2 input is not stopped, the processor recognizes and acknowledges the HOLD input and stores the occurrence of
FLUSH# for execution once suspend mode is exited.
Figure 3-25. HALT-Initiated Suspend Mode
Nonpipelined HALT
T1
T2
Ti
Ti
Ti
CLK2
(
1
1
1
NMI
17 CLK2s Max ~I~-----+-------
3-46
1
12
1
I
1
1'- CL~2S ~I
_ .......-~(I
1
) 1
I
SUSPA#
(( 1
~j~1--~----~--~I--~Jji
READY#
1
1
1
Bus Operation and Functional Timing
3.4.11.3 Stopping the Input Clock
Because the TI486SXLC series microprocessors are static devices, the input
clock (CLK2) can be stopped and restarted without loss of any internal CPU
data. This assumes, of course, that the TI486SXLC2 microprocessor is in nonclock-doubled mode when the input clock is stopped. (Refer to subsection
3.2.1, Clock Doubling Using Software Control, page 3-13.) CLK2 can be
stopped in either phase one (1) or phase two (<1>2) of the clock and in either
a logic-high or logic-low state. However, entering suspend mode prior to stopping CLK2 dramatically reduces the CPU current requirements. Therefore, the
recommended sequence for stopping CLK2 of the TI486SXLC2 series microprocessor from clock-doubled mode is:
1) Bring the processor out of clock-doubled mode
2) Initiate suspend mode
3) Wait for assertion of SUSPA# by the processor
4) Stop the input clock
Note:
Suspend mode can be entered while in clock-doubled mode as long as CLK2
is not scaled or stopped.
For all other cases, including the TI486SXLC2 in nonclock-doubled mode, the
recommended sequence is:
1) Initiate suspend mode
2) Wait for assertion of SUSPA# by the processor
3) Stop the input clock
The TI486SXLC series microprocessor remains suspended until CLK2 is restarted and suspend mode is exited as described above. While CLK2 is
stopped, the microprocessor can no longer sample and respond to any input
stimulus including the HOLD, FLUSH#, NMI, INTR, and RESET inputs.
Figure 3-26 illustrates the recommended sequence for stopping CLK2 using
SUSP# to initiate suspend mode. CLK2 should be stable for a minimum of 10
clock periods before SUSP# is deasserted.
Figure 3-26. Stopping CLK2 During Suspend Mode
M
I
CLK2
I
I
JiAAiJi}
I
$1
I $2
1
I $1
1
1
SUSP#
J'------~((~------------))
~~------~((~----------------~((
)j
:
_ _ _ _---...( (~----------------~((
I
((~--------~((~------------))
))
)j
))
10 CLK2s Min
1
1
)~
--+1-4-------------.,
-------...( (.,..--SUSPA#
I
(I
)j
BUSY#
I
))
\
,
'
11
((
((
((1r- _ _..JI
~---~)~)---~)~)--------~))
Tl486SXLC Microprocessor Bus Interface
3-47
Bus Operation and Functional Timing
3.4.12 Float
Activating the FLT# input floats all TI486SXLC bidirectional and output signals.
Asserting FLT# electrically isolates the microprocessor from the surrounding
circuitry. This feature is useful in board-level test environments. Since the microprocessor is packaged in a surface-mount QFP, it is not usually socketed
and cannot be removed from the motherboard when in-circuit emulation (ICE)
is needed. Float capability allows connection of an emulator by clamping the
emulator probe onto the microprocessor QFP without removing it from the circuit board.
FLT# is an asynchronous, active-low input. It is recognized on the rising edge
of CLK2. When recognized, it aborts the current bus state and floats the outputs of the microprocessor as shown in Figure 3-27. FLT# must be asserted
for a minimum of 16 CLK2 cycles. To exit the float condition, RESET should
be asserted and held asserted until after FLT# is deasserted.
Asserting the FLT# input unconditionally aborts the current bus cycle and
forces the microprocessor into the float mode. As a result, the microprocessors are not guaranteed to enter float in a valid state. After deactivating FLT#,
the CPU is not guaranteed to exit float in a valid state. The microprocessor
RESET input must be asserted prior to exiting float to ensure that the microprocessor is reset and that it returns in a valid state.
Figure 3-27. Entering and Exiting Float
CLK2
FLT# ,
CONTROL
DATA
ADDRESS
RESET
3-48
~
1
_ _ _ _ _ _ _ _ _ _ _- - . 1
Valid
X____
} - - - - - - - - - - - - - - - - - - - {_ _ _ _ _..J
-1}--{
Valid
~
Valid
L
} - - - - - - - - - - - - - - - - - - {_ _ _ _ _
X___
} - - - - - - - - - - - - - - - - - - {_ _- . . J
1
_ _ _ _-.-.6
Chapter 4
TI486SXL Microprocessor Bus Interface
This chapter provides a summary of the TI486SXL series processor signals
and descriptions of all inputs/outputs, functional timing and bus operations (including pipelined and nonpipelined addressing), various interfaces, and power
management.
Topic
4~1
Page
I nputlO utput Signals .' •.. ~. ~ ~ •..••••••••••• ~ • ;, ~ •. L •.•••.. ~'~ .. •. . .• 4..2
"
"
;-
BU$..Cy'CI~ Definition; ............ ~~ ............. ~ .i •• ~. ~ ••••• ~ .....L4;'15
"
~~"
':
'
'0
"
"i
0 ,'; "
,
Re$et '·nlllingaRCI:lijternaICI()ck$ynchr;Qnizati9n'; •. ~ :.' •••••..••~.' . ~." 4;.19
~u~Qperatiohantt :~:UR9tio,ri~al :;i:ni~9.·
4-1
Input/Output Signals
4.1
Input/Output Signals
This section describesthe TI486SXL series microprocessors' input and output
signals. The discussion of these signals is arranged by functional groups as
shown in Figure 4-1. Table 4-1 gives a brief description of each signal.
Figure 4-1. TI486SXL Functional Signal Groupings
2x Clock
CLK2
TI486SXL
INTR
NMI
Reset
RESET
Address {
A31-A2
Bus
BE3#--BEO#
SMI#
1
J
Interrupt
Control
KEN#
}
FLUSH#
Internal
Cache
Interface
tMEMW#
Data
Bus
D31-DO
Address
Bit-20 Mask
A20M#
-+W/R#
Bus-Cycle
Definition
W/R#
PEREQ
D/C#
BUSY#
M/IO#
LOCK#
BS16#
NA#
Bus-Cycle
Control
READY#
ADS#
SMADS#
4-2
Coprocessor
Interface
ERROR#
HOLD
}
HLDA
SUSP#
SUSPA#
t FLT#
t 144-pin QFP and 168-pin PGA pinout only
-+ 144-pin QFP pinout only
}
}
Bus
Arbitration
Power
Management
Float Control
Input/Output Signals
Table 4-1. TI486SXL Signal Summary
Signal
Signal Name
Signal Group
AOS#
Address Strobe
Bus-cycle control
A20M#
Address Bit-20 Mask
None
A31-A2
Address Bus Lines
Address bus
BE3#-BEO#
Byte enables
Address bus
BS16#
Bus size 16
Bus-cycle control
BUSY#
Processor extension busy
Coprocessor interface
CLK2
2X clock input
None
031-00
Data bus
None
D/C#
Data/control
Bus-cycle definition
ERROR#
Processor extension error
Coprocessor interface
FLT#t
Float
None
FLUSH#
Cache flush
Internal cache interface
HLDA
Hold acknowledge
Bus arbitration
HOLD
Hold request
Bus arbitration
INTR
Maskable interrupt request
Interrupt control
KEN#
Cache enable
Internal Cache interface
LOCK#
Bus lock
Bus-cycle definition
MEMW#t
ISA memory write
Internal cache interface
M/IO#
Memory/input-output
Bus-cycle definition
NA#
Next address request
Bus-cycle control
NMI
Nonmaskable interrupt request
Interrupt control
PEREQ
Processor extension request
Coprocessor interface
READY#
Bus ready
Bus-cycle control
RESET
Reset
None
SMADS#
SMM address strobe
Bus-cycle control
SMI#
System management interrupt
Interrupt control
SUSP#
Suspend request
Power management
SUSPA#
Suspend acknowledge
Power management
W/R#+-
Write/read
Bus-cycle definition
t 144-pin OFP and 168-pin PGA pinout only.
+- 144-pin OFP has W/R# on pins 36 and 37. These terminals must be connected together.
The following sections describe the signals and their functional characteristics. Additional signal information can be found in Chapter 5, Electrical Specifications. Chapter 5 documents the dc and ac characteristics for the signals including voltage levels, propagation delays, setup times, and hold times. Specified setup and hold times must be met for proper operation of the TI486SXL
series microprocessors.
Tl486SXL Microprocessor Bus Interface
4-3
Input/Output Signals
4.1.1
TI486SXL Terminal Function Descriptions
Table 4-2 identifies and describes each of the TI486SXLC package terminals.
Table 4-2. TI486SXL Terminal Functions
Name
Terminal
No.
132- 144- 168pin
pin
pin
Description
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
C4
A3
B3
B2
C3
C2
C1
03
02
01
E3
E2
E1
F1
G1
H1
H2
H3
J1
K1
K2
L1
L2
K3
M1
N1
L3
M2
P1
N2
73
74
75
76
77
78
86
87
88
89
90
93
94
95
104
106
107
108
109
110
113
114
61
60
59
58
84
83
82
81
014
R15
816
012
815
013
R13
011
813
R12
87
010
85
R7
09
03
R5
04
08
05
07
83
06
R2
82
81
R1
P2
P3
Q1
Address Bus (active high). The address bus (A31-A2) signals are threestate outputs that provide addresses for physical memory and I/O ports. All
address lines can be used for addressing physical memory allowing a
4G-byte address space (0000 OOOOh to FFFF FFFFh). During 1/0 port
accesses, A31-A 16 are driven low (except for coprocessor accesses). This
permits a 64-Kbyte 1/0 address space (0000 OOOOh to 0000 FFFFh).
AD8#
E14
26
817
Address 8trobe (active low). This 3-state output indicates thafthe TI4868XL
microprocessor has driven a valid address (A31-A2, BE3#-BEO#) and
bus-cycle definition (M/IO#, D/C#, W/R#) on the appropriate output pins.
During nonpipelined bus cycles, AD8# is active for the first clock of the bus
cycle. During address pipelining, AD8# is asserted during the previous bus
cycle and remains asserted until READY# is returned for that cycle. AD8#
floats while the microprocessor is in a hold-acknowledge or float state.
A20M#
F13
43
015
Address Bit-20 Mask (active low). This input causes the microprocessor to
mask (force low) physical address bit 20 when driving the external address
bus or performing an internal cache access. When the processor is in real
mode, asserting A20M# emulates the 1M-byte address wraparound that
occurs on the 8086. The A20 signal is never masked when paging is enabled
regardless of the state of the A20M# input. The A20M# input is ignored
following reset and can be enabled using the A20M bit in the CCRO
Configuration register.
During all coprocessor 1/0 access address lines A30-A 16 are driven low and
A31 is driven high. This allows A31 to be used by external logic to generate
a coprocessor select signal. Coprocessor command transfers occur with
address 8000 00F8h and coprocessor data transfers occur with address
8000 OOFCh. A31-A2 float while the CPU is in a hold-acknowledge or float
state.
A20M# is internally connected to a pullup resistor to prevent it from floating
active when left unconnected.
4-4
Input/Output Signals
Table 4-2. TI486SXL Terminal Functions (Continued)
Name
Terminal
No.
132- 144- 168pin
pin
pin
BE3#
BE2#
BE1#
BEO#
A13
B13
C13
E12
32
31
28
27
F17
J15
J16
K15
Description
Byte Enables BE3#-BEO# (active low). These 3-state outputs determine
which bytes within the 32-bit data bus are transferred during a memory or I/O
access (Table 4-3). During a memory write, one or both of the upper bytes
(0 and C) of the data bus can be duplicated in the lower bytes (B and A) of
the bus. This duplication is dependent on BE3#-BEO# as listed in Table 4-4.
Generating A1-AO using BE3#-BEO# can be achieved by using the
following equations:
AO = (BEO# • BE2#) + (BEO# • BE1 #)
A1 = BEO#. BE1#
The relationship between A1-AO and BE3#-BEO# is shown in Table 4-5.
BS16#
C14
115
C17
Bus Size 16 (active low). This input allows connection of the 32-bit
microprocessor data bus to an external 16-bit data bus. When this input is
activated, the microprocessor performs multiple bus cycles to couple read
and write accesses from devices that cannot provide (accept) 32 bits of data
in a single cycle. During bus cycles with BS16# active, data is transferred
using data bus signals 015-00 only.
BUSY#
B9
48
S4
Coprocessor Busy (active low). This input indicates to the TI486SXL that the
coprocessor is currently executing an instruction and is unable to accept
another opcode. When the microprocessor encounters a WAIT instruction or
any coprocessor instruction that operates on the coprocessor stack (Le.,
load, pop, arithmetic operation), BUSY# is sampled. BUSY# is continually
sampled and must be recognized as inactive before the CPU supplies the
coprocessor with another instruction. However, the following coprocessor
instructions are allowed to execute even if BUSY# is active because they are
used for coprocessor initialization and exception clearing: FNINIT, FNCLEX.
BUSY# is internally connected to a pullup resistor to prevent it from floating
active when left unconnected.
CLK2
F12
25
C3
2X Clock Input (active high). This input signal is the basic timing reference
for the TI486SXL series microprocessors. The CLK2 input is internally
divided by two to generate the internal processor clock. The external CLK2
is synchronized to a known phase of the internal processor clock by the falling
edge of the RESET signal. External timing parameters are defined with
respect to the rising edge of CLK2.
For the TI486SXL2 microprocessors, the CLK2 input is used internally to
generate the internal core processor clock and the internal bus interface
clock. The external CLK2 is synchronized to a known phase of the internal
processor clock by the falling edge of the RESET signal. External timing
parameters are defined with respect to the rising edge of CLK2.
Tl486SXL Microprocessor Bus Interface
4-5
Input/Output Signals
Table 4-2. TI486SXL Terminal Functions (Continued)
Name
Terminal
No.
132- 144- 168pin
pin
pin
O/C#
A11
35
M15
Oata/Control. This 3-state, bus-cycle-definition signal is low during control
cycles and is high during data cycles. Control cycles are issued during
functions such as a halt instruction, interrupt servicing, and code fetching.
Oata bus cycles include data access from either memory or 1/0.
00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
H12
H13
H14
J14
K14
K13
L14
K12
L13
N14
M12
N13
N12
P13
P12
M11
N11
N10
P11
P10
M9
N9
P9
N8
P7
N6
P5
N5
M6
P4
P3
M5
1
144
143
137
136
135
134
133
131
130
129
128
127
118
117
116
124
123
122
121
102
101
100
99
3
4
142
141
12
13
14
15
P1
N2
N1
H2
M3
J2
L2
L3
F2
01
E3
C1
G3
02
K3
F3
J3
03
C2
81
A1
B2
A2
A4
A6
86
C7
C6
C8
A8
C9
88
Oata Bus (active high). The data bus (031-00) signals are 3-state
bidirectional signals that provide the data path between the microprocessor
and external memory and 1/0 devices. The data bus inputs data during
memory read, 1/0 read, and interrupt-acknowledge cycles and outputs data
during memory and 1/0 write cycles. Oata read operations require that
specified data setup and hold times be met for correct operation. The data
bus signals float while the CPU is in a hold-acknowledge or float state.
ERROR#
A8
49
A12
Coprocessor Error (active low). This input indicates that the coprocessor
generated an error during execution of an instruction. ERROR# is sampled
by the microprocessor whenever a coprocessor instruction is executed. If
ERROR# is sampled active, the processor generates exception 16, that is
then serviced by the exception handling software.
Description
Certain coprocessor instructions do not generate an exception 16 even if
ERROR# is active. These instructions, which involve clearing coprocessor
error flags and saving the coprocessor state, are: FNINIT, FNCLEX,
FNSTSW, FNSTCW, FNSTENV, FNSAVE.
ERROR# is internally connected to a pullup resistor to prevent it from floating
active when left unconnected.
4-6
Input/Output Signals
Table 4-2. TI486SXL Terminal Functions (Continued)
Name
Terminal
No.
132- 144- 168pin
pin
pin
FLT#
40
C11
Description
Float (active low). This input forces all bidirectional and output signals to a
3-state condition. Floating the signals allows the microprocessor signals to
be driven externally without physically removing the device from the circuit.
The microprocessor must be reset following assertion or deassertion of
FLT#. This signal may be used in conjunction with an upgrade socket.
FLT# is internally connected to a pullup resistor to prevent it from floating
active when left unconnected.
FLUSH#
E13
42
C15
Cache Flush (active low). This input invalidates (flushes) the entire cache.
Use of FLUSH#to maintain cache coherency is optional. The cache may also
be invalidated during each hold-acknowledge cycle by setting the BARB bit
in the CCRO Configuration register. The FLUSH# input is ignored following
reset and can be enabled using the FLUSH bit in the CCRO Configuration
register.
FLUSH# is internally connected to a pullup resistor to prevent it from floating
active when left unconnected.
HOLD
014
7
E15
Hold Request (active high). This input indicates that another bus master
requests control of the local bus. The bus arbitration (HOLD, HLDA) signals
allow the microprocessor to relinquish control of its local bus when requested
by another bus master device. Once the processor has relinquished its bus
(3-stated), the bus master device can then drive the local bus signals.
After recognizing the HOLD request and completing the current bus cycle or
sequence of locked bus cycles, the microprocessor responds by floating the
local bus and asserting the hold acknowledge (HLDA) output.
Once HLDA is asserted, the bus remains granted to the requesting bus
master until HOLD becomes inactive. When the microprocessor recognizes
HOLD is inactive, it simultaneously drives the local bus and drives HLDA
inactive. External pullup resistors may be required on some of the
microprocessor 3-state outputs to ensure that they remain inactive while in
a hold-acknowledge state (or float state for the 144-pin QFP and 168-pin
CPUs).
The HOLD input is not recognized while RESET is active. If HOLD is asserted
while RESET is active, RESET has priority and the microprocessor places
the bus into an idle state instead of a hold-acknowledge state. The HOLD
input is also recognized during suspend mode provided that the CLK2 input
has not been stopped. HOLD is level-sensitive and must meet specified
setup and hold times for correct operation.
Tl486SXL Microprocessor Bus Interface
4-7
Input/Output Signals
Table 4-2. TI486SXL Terminal Functions (Continued)
Name
Terminal
No.
132- 144- 168pin
pin
pin
HLDA
M14
6
P15
Description
Hold Acknowledge (active high). This output indicates that the
microprocessor is in a hold-acknowledge state and has relinquished control
of its local bus. While in the hold-acknowledge state, the microprocessor
drives HLDA active and continues to drive SUSPA#, if enabled. The other
microprocessor outputs are in the high-impedance state allowing the
requesting bus master to drive these signals. If the on-chip cache can satisfy
bus requests, the microprocessor continues to operate during
hold-acknowledge states. A20M# is internally recognized during this time.
The microprocessor deactivates HLDA when the HOLD request is driven
inactive. The microprocessor stores an NMI rising edge during a
hold-acknowledge state for processing after HOLD is inactive. The FLUSH#
input is also recognized during a hold-acknowledge state. If SUSP# is
asserted during a hold-acknowledge state, the microprocessor mayor may
not enter suspend mode depending on the state of the internal execution
pipeline. Table 4-6 summarizes the state of the microprocessor signals
during hold acknowledge.
INTR
B7
53
A 16
Maskable Interrupt Request. This level-sensitive input causes the processor
to suspend execution of the current instruction stream and begin execution
of an interrupt service routine. The INTR input can be masked (ignored)
through the Flag Word register IF bit. When unmasked, the microprocessor
responds to the INTR input by issuing two locked interrupt-acknowledge
cycles. To assure recognition of the INTR request, INTR must remain active
until the start of the first interrupt-acknowledge cycle.
KEN#
B12
41
F15
Cache Enable (active low). This input indicates that the data being returned
during the current cycle is cacheable. When KEN# is active and the
microprocessor is performing a cacheable code fetch or memory data read
cycle, the cycle is transformed into a cache fill. Use of the KEN# input to
control cacheability is optional. The noncacheable region registers can also
be used to control cacheablity. Memory addresses specified by the
noncacheable region registers are not cacheable regardless of the state of
KEN#. I/O accesses, locked reads, SMM address space accesses, and
interrupt-acknowledge cycles are never cached.
During cached code fetches with BS16# asserted, two contiguous read
cycles are performed to completely fill the 4-byte cache line. KEN# must be
asserted during both read cycles to cause acache line fill. If BS16# is inactive,
only one bus cycle is required and KEN# must be asserted for the data to be
cached. During memory data reads, the microprocessor performs as many
read cycles as necessary to supply the required data to complete the current
operation. Valid bits are maintained for each byte in the cache line and for
each block of four lines, thus allowing data operands of less than four bytes
to reside in the cache.
If two read cycles are performed with the same address (A31-A2), KEN#
must be asserted during both cycles to cache the data in these cycles. If the
data is cached, the microprocessor ignores the state of the byte enables
(BE3#- BEO#) and four bytes of data (2 bytes if BS 16# is asserted) is cached.
The KEN# input is ignored following reset and can be enabled using the KEN
bit in the CCRO Configuration register.
KEN# is internally connected to a pullup resistor to prevent it from floating
active when left unconnected.
4-8
Input/Output Signals
Table 4-2. TI486SXL Terminal Functions (Continued)
Name
Terminal
No.
132- 144- 168pin
pin
pin
LOCK#
C10
MEMW#
Description
38
N15
LOCK (active low). This 3-state, bus-cycle-definition signal is asserted to
deny access of the CPU bus to other bus masters. The LOCK# signal may
be explicitly activated during bus operations by including the LOCK prefix
on certain instructions. LOCK# is always asserted during descriptor and
page table updates, interrupt-acknowledge sequences, and when
executing the XCHG instruction. The microprocessor does not enter the
hold-acknowledge state in response to HOLD while the LOCK# output is
active.
66
816
Memory Write (active low). This input is used in the cache interface logic
which flushes the cache in systems that hold the CPU during DMA and
MASTER cycles.
M/IO#
A 12
34
N16
Memory/IO. This 3-state, bus-cycle-definition signal is low during I/O read
and write cycles and is high during memory cycles.
NA#
D13
9
A 13
Next Address Request (active low). This input requests address pipelining
by the system hardware. When asserted, the system indicates that it is
prepared to accept new bus-cycle definition and address signals (M/IO#,
D/C#, W/R#, A31-A2, 8S16#, and 8E3#-8EO#) from the microprocessor
even if the current bus cycle has not been terminated by assertion of
READY#. If the microprocessor has an internal bus request pending and the
NA# input is sampled active, the next bus-cycle definition and address
signals are driven onto the bus.
NC
86
39
65
71
138
A3
A5
A14
A17
814
815
817
C10
C12
C14
D16
D17
F1
G15
H3
H15
J17
L15
N3
Q15
Q16
Q17
R16
Make no external connection.
Note:
NC Terminals
Connecting or terminating (high or low) any NC terminal(s) may cause unpredictable results or nonperformance of the microprocessor.
Tl486SXL Microprocessor Bus Interface
4-9
Input/Output Signals
Table 4-2. TI486SXL Terminal Functions (Continued)
Terminal
No.
132-
144-
168-
Name
pin
pin
pin
Description
NMI
B8
51
A15
Nonmaskable Interrupt Request. This rising-edge-sensitive input causes
the processor to suspend execution of the current instruction stream and
begin execution of an NMI interrupt service routine. The NMI interrupt service
request cannot be masked by software. Asserting NMI causes an interrupt
which internally supplies interrupt vector 2h to the CPU core. External
interrupt-acknowledge cycles are not necessary since the NMI interrupt
vector is supplied internally. Once NMI processing has started, no additional
NMls are processed until an IRET instruction is executed.
The microprocessor samples NMI at the beginning of each phase two (<1>2)
clock period. To assure recognition, NMI must be inactive for at least eight
CLK2 periods and then be active for at least eight CLK2 periods. Additionally,
specified setup and hold times must be met to assure recognition at a
particular clock edge.
PEREa
C8
50
R17
Coprocessor Request (active high). This input indicates that the
coprocessor is ready to transfer data to or from the CPU. The coprocessor
can assert PEREa in the process of executing a coprocessor instruction. The
microprocessor internally stores the current coprocessor opcode and
performs the correct data transfers to support coprocessor operations using
PEREa to synchronize the transfer of required operands.
PEREa is internally connected to a pulldown resistor to prevent this signal
from floating active when left unconnected.
READY#
G13
10
Ready (active low). This input is generated by the system hardware to
indicate that the current bus cycle can be terminated. During a read cycle,
assertion of READY# indicates that the system hardware has presented valid
data to the CPU. When READY# is sampled active, the microprocessor
latches the input data and terminates the cycle. During a write cycle,
READY# assertion indicates that the system hardware has accepted the
microprocessor output data. READY# must be asserted to terminate every
bus cycle, including halt and shutdown indication cycles.
A10
Reserved
RESET
F16
C9
45
C16
Reset (active high). When asserted, RESET suspends all operations in
progress and places the microprocessor into a reset state. RESET is a
level-sensitive synchronous input and must meet specified setup and hold
times to be properly recognized by the microprocessor. The microprocessor
begins executing instructions at physical address location FF FFFOh
approximately 400 CLK2s after RESET is driven inactive (low).
While RESET is active, the microprocessor is initialized to nonclock-doubled
mode (for the T1486SXL2) and all other input pins are ignored. The remaining
signals are initialized to their reset state during the internal processor reset
sequence. The reset signal states for the microprocessor are shown in
Table 4-6.
SMADS#
4-10
C6
29
B13
SMM Address Strobe (active low). SMADS#, a three-state output, is
asserted instead of the ADS# during SMM bus cycles and indicates that SMM
memory is being accessed. SMADS# floats while the CPU is in a
hold-acknowledge or float state. The SMADS# output is disabled (floated)
following reset and can be enabled using the SMI bit in the CCR1
Configuration register.
Input/Output Signals
Table 4-2. TI486SXL Terminal Functions (Continued)
Name
SMI#
Terminal
No.
132144168pin
pin
pin
C7
67
B10
Description
System Management Interrupt (active low). This 3-state, bidirectional,
level-sensitive, input/output signal is an interrupt with higher priority than the
NMI interrupt. SMI# must be active for at least four CLK2 clock periods to
be recognized by the microprocessor. After the SMI is acknowledged, the
SMI# pin is driven low by the microprocessor for the duration of the SMI
service routine. The SMI# input is ignored following reset and can be
enabled using the SMI bit in the CCR1 Configuration register.
SMI# is internally connected to a pullup resistor to prevent it from floating
active when left unconnected.
SUSP#
A4
63
C13
Suspend Request (active low). This input requests the microprocessor to
enter suspend mode. After recognizing SUSP# active, the processor
completes execution of the current instruction, any pending decoded
instructions, and associated bus cycles. In addition, the microprocessor
waits for the coprocessor to indicate a not-busy status (BUSY# = 1) before
entering suspend mode and asserting suspend acknowledge (SUSPA#).
SUSP# is internally connected to a pullup resistor to prevent it from floating
active when left unconnected.
SUSPA#
B4
64
B12
Suspend Acknowledge (active low). This output indicates that the
microprocessor has entered the suspend mode as a result of SUSP#
assertion or execution of a HALT instruction.
Vee
A1
AS
A7
A10
A14
C5
C12
012
G2
G3
G12
G14
L12
M3
M7
M13
N4
N7
P2
P8
5
11
16
17
30
44
52
55
56
62
68
79
85
91
98
103
105
119
125
132
139
B7
B9
B11
C4
C5
E2
E16
G2
G16
H16
K2
K16
L16
M2
M16
P16
R3
R6
R8
R9
R10
R11
R14
Power Supply. All pins must be connected and used.
47
J1
VCC5
5-V Power Supply
Tl486SXL Microprocessor Bus Interface
4-11
Input/Output Signals
Table 4-2. TI486SXL Terminal Functions (Continued)
Name
Terminal
No.
132- 144- 168pin
pin
pin
Description
Vss
A2
A6
A9
B1
B5
B11
B14
C11
F2
F3
F14
J2
J3
J12
J13
M4
M8
M10
N3
P6
P14
2
8
18
19
20
21
22
23
24
33
48
54
57
69
70
72
80
92
96
97
111
A7
A9
A11
B3
B4
B5
E1
E17
G1
G17
H1
H17
K1
K17
L1
L17
M1
M17
P17
Q2
R4
S6
S8
S9
S10
S11
812
S14
Ground Pins. All pins must be connected and used.
W/R#
B10
36
37
N17
Write/Read. This 3-state, bus-cycle-definition signal is low during read
cycles (data is read from memory or I/O) and is high during write bus cycles
(data is written to memory or I/O).
4.1.2
Byte Enable Line Definitions
These 3-state outputs determine which bytes within the 32-bit data bus are
transferred during a memory or liD access. See Table 4-3.
Table 4-3. Byte Enable Line Definitions
Byte Enable Line
4-12
Byte Transferred
BEO#
07-00
BE1#
015-08
BE2#
023-016
BE3#
031-024
InpuVOufpuf Signals
4.1.3
Write Duplication as a Function of BE3# - BEQ#
During a memory write, one or both of the upper bytes (D and C) of the data
bus can be duplicated in the lower bytes (B and A) of the bus. This duplication
is dependent on BE3#-BEO# as listed in Table 4-4.
Table 4-4. Write Duplication as a Function of BE3#-BEO#
BE3#-BEO#
031-024
023-016
015-08
07-00
Duplicated Data
0000
0
C
B
A
No
0001
0
C
B
X
No
0011
0
C
0
C
Yes
0111
0
X
0
X
Yes
1000
X
C
B
A
No
1001
X
C
B
X
No
1011
X
C
X
C
Yes
1100
X
X
B
A
No
1101
X
X
B
X
No
1110
X
X
X
A
No
Note:
4.1.4
BE3# - BEO# combinations not listed do not occur during TI486SXL bus cycles.
A = logical write data D7 - DO
B = logical write data D15 - D8
C = logical write data D23 - D16
D = logical write data D31 - D24
X = Don't care
Generating A 1 - AQ Using BE3# - BEQ#
Generating A 1-AO using BE3#-BEO# can be achieved by using the following
equations:
AO
= (BEO# •
A1
= BEO#. BE1#
BE2#) + (BEO# • BE1 #)
The relationship between A1-AO and BE3#-BEO# is shown in Table 4-5.
Table 4-5. Generating A 1-AO Using BE3#-BEO#
A31-A2
A1
AO
BE3#
BE2#
BE1#
BEO#
0
0
X
X
X
0
X
X
0
X
0
0
0
0
Note:
4.1.5
X
= Don't care
Signal States During Reset and Hold Acknowledge
RESET is the highest priority input signal. When RESET is asserted, the microprocessor aborts any current bus cycle and establishes real-mode bus-
TI486SXL Microprocessor Bus Interface
4-13
Input/Output Signals
cycle definition with active buses. See Table 3-3 and Section 4.3, Reset Timing and Internal Clock Synchronization, page 4-19.
The hold-acknowledge state (Th) is entered in response to assertion of the
HOLD input during which the microprocessor floats all output and bidirectional
signals, except for HLDA and SUSPA#. In the hold-acknowledge state, all inputs except HOLD, FLUSH#, FLT#, SUSP# and RESET are ignored. See
Table 3-3 and subsection 4.4.9, Hold Acknowledge State, page 4-45. The
hold-acknowledge state provides the mechanism for an external device to acquire the system bus.
Table 4-6. Signal States During RESET and Hold Acknowledge
Signal Name
Signal State
During Reset
Signal State During
Hold Acknowledge
A20M#
Ignored
Input recognized
A31-A2
1
Float
ADS#
1
Float
BE3#-BEO#
0
Float
BS16#
Ignored
Ignored
BUSY#
Initiates self test
Ignored
D31-DO
Float
Float
Float
D/C#
ERROR#
Ignored
Ignored
FLT#t
Input recognized
Input recognized
FLUSH#
Ignored
Input recognized
HLDA
0
1
HOLD
Ignored
Input recognized
INTR
Ignored
Input recognized
KEN#
Ignored
Ignored
LOCK#
1
Float
MEMW#t
Ignored
Input recognized
M/IO#
0
Float
NA#
Ignored
Ignored
NMI
Ignored
Input recognized
PEREQ
Ignored
Ignored
READY#
Ignored
Ignored
RESET
Input recognized
Input recognized
SMADS#
Float
Float
SMI#
Ignored
Input recognized
SUSP#
Ignored
Input recognized
SUSPA#
(Float
Driven
W/R#':t.
0
Float
t 144-pin OFP and 168-pin PGA only
':t. 144-pin OFP has W/R# on pins 36 and 37. These terminals must be connected together.
4-14
Bus-Cycle Definition
4.2
Bus-Cycle Definition
The bus-cycle-definition signals consist of four 3-state outputs (M/IO#, D/C#,
W/R#, LOCK#) that define the type of bus-cycle operation being performed.
Table 4-7 defines the bus cycles for the possible states of these signals.
M/IO#, D/C#, and W/R# are the primary bus-cycle-definition signals and are
driven valid as ADS# (Address Strobe) becomes active. During nonpipelined
cycles, the LOCK# output is driven valid along with M/IO#, D/C# and W/R#.
During pipelined addressing, LOCK# is driven at the beginning of the bus
cycle, which is after ADS# becomes active for that cycle. The bus-cycle-definition signals are active low and float while the microprocessor is in a hold-acknowledge or float state.
Table 4-7. Bus-Cycle Types
M/IO#
D/C#
W/R#
LOCK#
0
0
0
0
0
0
0
0
0
Bus-Cycle Type
Interrupt acknowledge
X
0
X
0
0
0
I/O data read
liD data write
0
0
X
0
0
0
Memory code read
Halt: A31-A2 = Oh, BE3#-BEO# = 1011
Shutdown: A31-A2 = Oh, BE3#-BEO# =1110
0
0
Locked memory data read
0
Memory data read
0
Locked memory data write
0
Memory data write
X = don't care
- = does not occur
4.2.1
Clock Doubling Using Software Control
The clock-doubled feature of the Tl486SXL2 is enabledldisabled using
Configuration Control register 0 (CCRO) bit 6. The following can be used for
software enablingldisabling of CKD:
Set CKD programming sequence:
mov
out
in
mov
or
mov
out
mov
out
aI, OCOh
22h, al
aI, 23h
ah, al
ah, 40h
aI, OCOh
22h, al
aI, ah
23h, al
;select CCRO
;read CCRO
;save in AH
;set AH<6>
;select CCRO
;write CCRO
Tl486SXL Microprocessor Bus Interface
4-15
Bus-Cycle Definition
Reset CKD programming sequence:
mov
out
in
mov
and
mov
out
mov
out
4.2.1.1
al, OCOh
22h, al
al, 23h
ah, al
ah, OBFh
al, OCOh
22h, al
al, ah
23h, al
;select CCRO
;read CCRO
;save in AH
;reset AH<6>
;select CCRO
;write CCRO
Entering Clock-Doubled Mode
The TI486SXL2 microprocessors power up in the nonclock-doubled mode. To
enter the clock-doubled mode, set CLK2 to the desired frequency inside the
phase-locked loop (PLL) lock range (see Table 5-5 and Table 5-6) and issue
the set CKD programming sequence. Approximately 20 ~s after the final OUT
instruction has exited the processor pipeline, the PLL locks and the CPU
enters clock-doubled mode. Until the PLL is locked, the processor continues
to operate in the nonclock-doubled mode.
4.2.1.2
Clock-Scaling Sequence
When the processor is in clock-doubled mode and the CLK2 input is to be
scaled or stopped, the reset CKD programming sequence should be issued.
The final OUT instruction exiting the processor pipeline causes the CKD bit to
be reset and puts the processor into nonclock-doubled mode. This must occur
prior to scaling or stopping the CLK2 input in order to prevent a synchronization
error from occurring. This may be ensured by issuing a JUMP instruction, such
as JMP $ + 2, before scaling CLK2.
To return the processor to clock-doubled mode, set CLK2 to the desired frequency inside the PLL lock range and issue the set CKD programming sequence. Approximately 20 ~s after the final OUT instruction has exited the processor pipeline, the PLL locks and the processor enters clock-doubled mode.
4.2.1.3
Suspend Mode
Suspend mode can be initiated when the TI486SXL2 microprocessor is in
clock-doubled mode as long as the CLK2 input is not scaled or stopped. Suspend mode does not disable the PLL; instead, changing the CLK2 frequency
causes the PLL to lose lock.
For more detailed information on entering and exiting suspend in nonclockdoubled mode, refer to subsection 4.2.2, Power Management.
In order to get the lowest possible power state, bring the microprocessor out
of clock-doubled mode, enterthe suspend mode (using software or hardware),
and stop the CLK2 input.
4-16
Bus-Cycle Definition
4.2.2
Power Management
The power management signals allow the TI486SXL series microprocessors
to enter suspend mode. Suspend-mode circuitry allows the microprocessor to
consume minimal power while maintaining the entire internal CPU state.
4.2.2.1
Suspend Request (SUSP#)
Suspend Request (SUSP#) is an active-low input that requests the TI486SXL
series microprocessors to enter suspend mode. With the TI486SXL2 microprocessors you should follow the procedure in subsection 4.2.1 to enter nonclock-doubled mode prior to scaling or stopping the CLK2 input. After recognizing SUSP# is active, the processor completes execution of the current
instruction, any pending decoded instructions, and associated bus cycles. In
addition, the microprocessor waits for the coprocessor to indicate a not-busy
condition (BUSY#=1) before entering suspend mode and asserting suspend
acknowledge (SUSPA#). During suspend mode, internal clocks are stopped
and only the logic associated with monitoring RESET, HOLD, and FLUSH# remains active. With SUSPA# asserted, the CLK2 input to the microprocessor
can be stopped in either phase. Stopping the CLK2 input further reduces current required by the microprocessor.
To resume operation, the CLK2 input is restarted (if stopped), followed by
deassertion of the SUSP# input. The TI486SXL2 processors can enter clockdoubled mode (subsection 4.2.1.1, Entering Clock-Doubled Mode) once the
CLK2 input reaches the desired frequency within the PLL lock range. The processor then resumes instruction fetching and begins execution in the instruction stream at the point it had stopped. The SUSP# input is level sensitive and
must meet specified setup and hold times to be recognized at a particular clock
edge. The SUSP# input is ignored following reset and can be enabled using
the SUSP bit in the CCRO Configuration register.
4.2.2.2
Suspend Acknowledge (SUSPA#)
The Suspend Acknowledge (SUSPA#) output indicates that the TI486SXL series microprocessor has entered the suspend mode as a result of SUSP#
assertion or execution of a HALT instruction. If SUSPA# is asserted and the
CLK2 input is switching, the microprocessor continues to recognize RESET,
HOLD, and FLUSH#. In addition, the TI486SXL2 microprocessor may stay in
clock-doubled mode while the CLK2 input is switching. If suspend mode was
entered as the result of a HALT instruction, the microprocessor also continues
to monitor the NMI input and an unmasked INTR input. Detection of INTR or
NMI forces the microprocessor to exit suspend mode and begin execution of
the appropriate interrupt service routine. The CLK2 input to the processor can
be stopped after SUSPA# has been asserted to further reduce the power requirement of the microprocessor. For this case, the TI486SXL2 microprocessor must be brought out of clock-doubled mode prior to stopping the CLK2 input to prevent a synchronization error. The SUSPA# output is disabled
(floated) following reset and can be enabled using the SUSP bit in the CCRO
Configuration register.
Tl486SXL Microprocessor Bus Interface
4-17
Bus-Cycle Definition
Table 4-8 shows the state of the TI486SXL series microprocessor signals
when the device is in suspend mode.
Table 4-8. Signal States During Suspend Mode
Signal Name
Signal State During
Hold Acknowledge
Signal State During HaltInitiated Suspend Mode
A20M#
Ignored
Ignored
BE3#-BEO#
0
0
8S16#
Ignored
Ignored
BUSY#
Ignored
Ignored
031-00
Float
Float
ERROR#
Ignored
Ignored
FLT#t
Input recognized
Input recognized
FLUSH#
Input recognized
Input recognized
HLOA
0
0
HOLD
Input recognized
Input recognized
INTR
Latched
Input recognized
KEN#
Ignored
Ignored
MEMW#t
Input recognized
Input recognized
M/IO#
0
0
NA#
Ignored
Ignored
NMI
Latched
Input recognized
PEREQ
Ignored
Ignored
REAOY#
Ignored
Ignored
RESET
Input recognized
Input recognized
SMI#
Latched
Input recognized
SUSP#
Input recognized
Ignored
SUSPA#
0
0
W/R#+
0
0
A31-A2
ADS#
O/C#
LOCK#
SMAOS#
t 144-pin QFP and 168-pin PGA only
+ 144-pin QFP has duplicate W/R# inputs on pins 36 and 37
4-18
Reset Timing and Internal Clock Synchronization
4.3
Reset Timing and Internal Clock Synchronization
RESET is the highest priority input signal and is capable of interrupting any
processor activity when it is asserted. When RESET is asserted, the microprocessor aborts any bus cycle. Idle, hold -acknowledge, and suspend states are
also discontinued and the reset state is established. RESET is used when the
microprocessor is powered up to initialize the CPU to a known valid state and
to synchronize the internal CPU clock with external clocks. The TI486SXL2 microprocessors are initialized to nonclock-doubled mode upon RESET going
active.
RESET must be asserted for at least 15 CLK2 periods to ensure recognition
by the microprocessor. If the self-test feature is to be invoked, RESET must
be asserted for at least 80 CLK2 periods. RESET pulses of less than 15 CLK2
periods may not have sufficient time to propagate throughout the microprocessor and may not be recognized. RESET pulses of less than 80 CLK2 periods
followed by a self-test request may incorrectly report a self-test failure when
no true failure exists.
Provided the RESET falling edge meets specified setup and hold times, the
internal processor clock phase is synchronized as illustrated in Figure 4-2.
The TI486SXL internal processor clock is half the frequency of the CLK2 input
and each CLK2 cycle corresponds to an internal CPU clock phase (cp). Phase
two (<1>2) of the internal clock is defined to be the second rising edge of CLK2
following the falling edge of RESET. The TI486SXL2 internal core clock is the
same frequency as the CLK2 input and the internal bus interface clock is half
the frequency of the CLK2 input. Phase two of the internal clock is defined to
be the second rising edge of CLK2 following the falling edge of RESET.
Figure 4-2. Internal Processor Clock Synchronization
<\> 2 or <\>1
<\> 2 or <\>1
<\>2
<\> 1
CLK2
I
I
RESET
!I
INTERNAL
PROCESSOR
CLOCK
-
I
I
I
I
I
I
I
I
~-~--~-------------------+!--------~!----
~'--__--IV-
Tl486SXL Microprocessor Bus Interface
4-19
Reset Timing and Internal Clock Synchronization
Following the falling edge of RESET (and after self-test if it was requested),
the microprocessor performs an internal initialization sequence for approximately 400 CLK2 periods. The microprocessor self-test feature is invoked if
the BUSY# input is in the active (low) state when RESET falls inactive. The
self-test sequence requires approximately (2 20 + 60) CLK2 periods to complete. Even if the self-test indicates a problem, the microprocessor attempts
to proceed with the reset sequence. Figure 4-3 illustrates the bus activity and
timing during the microprocessor reset sequence.
Figure 4-3. Bus Activity From RESET Until First Code Fetch
I...
I
going to request self-test.
~ 80 CLK2 periods before
1
1
n h,~es;;g~-tt·
CLK2 - '
II
BUSY#
I
I
~
~
Internal
Initialization
I
(
If self-test is performed, add
20 20 + 60* to these numbers
1
2
~ U LJ LJ W
) U U W)
~
ERROR#~
I
Cycle 1
Nonplpehned
(R d)
ea
T1
T2
YU YL
* Approximately
I
"
x?oooa
~\
I
3~7 ~8 ~91~:r~3;::4;;95'
';
RESET -----(
CLK
(Internal)
.1'"
Reset
~ 15 CLK2 periods if not
I
1<1>21<1>11<1>21<1>11<1>2<1>1 <1>21<1>11<1>2.1
\.
r\.
\..../
'-.,( I \..../ . I ' -
r1\
High to, no SeW-Test (see Note)
Low to Begin SeltTest
r1\
\~~
BB
~
~I
BE3#-~7~:: ~ LO:
M/IO#, HLOA Up to 30 CLK2
------.I
II
I',
V vali~
'/;
'/;
K Vali~
::
A36/t#~ ~ Hi9j~
1
LOCK# Up to 30 CLK2 ~
ADS#
~Hi9\~
A20M#, BS16#, ~
:
1
'i,
"~
~b 1 I
<1>2
I
I
-.~
T2
1 I <1>2
I
I
Cycle 2
.I~
Nonpipelined
I
(Read)
I
T2
I
<1>2 I 1 I <1>2 I
Cycle 3
Nonpipelined
(Read)
<1>2
I
I
~
T2
1 I <1>2
I
I
CLK2
(Input)
A31-A2,
BE3#-BEO#,
M/IO#, O/C#, W/R#
A08#
NA#
B816#
REAOY#
LOCK#
031-00
(Input During Read)
~
4-22
~
+id2
:1
V
I
1\
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i\
I
I
I
I
~
I
r
:\
I
I
I
I
+id1
~
~
:'--
I
I
I
I
I
I
I
I
I
I
~
~
:1
I
I
I
I
I
I
+id2
~alid3
I
I
I
I
I
I
I
I
I
+id3
~
~--+--~--+--~--+--~
I
Note:
V~lid 1
I
Fastest nonpipelined bus cycles consist of T1 and T2.
I
I
I
I
Bus Operation and Functional Timing
4.4.1.2
Nonpipelined Read and Write Cycles
Any bus cycle can be performed with nonpipelined address timing. Figure 4-5
shows a mixture of read and write cycles with nonpipelined address timing.
When a read cycle is performed, the microprocessor floats its data bus and the
externally addressed device then drives the data. The microprocessor requires that all data-bus pins be driven to a valid logic state (high or low) at the
end of each read cycle, when READY# is asserted. When a read cycle is acknowledged by READY# asserted in the T2 bus state, the microprocessor
latches the information present at its data-bus pins and terminates the cycle.
When a write cycle is performed, the data bus is driven by the microprocessor
beginning in phase two of T1. When a write cycle is acknowledged, the write
data remains valid throughout phase one of the next bus state to provide writedata hold time.
Figure 4-5. Various Nonpipelined Bus Cycles (No Wait States)
1
1
1
Idle
1
1
I~
1
1
1
Ti
1
Cycle 1
Nonpipelined
(Write)
1
1
.I~
Cycle 2
Nonpipelined
(Read)
1
T1
T2
1
1
T1
1
1
.I~
Cycle 3
Nonpipelined
(Write)
1
Idle
/
T1
1
T2
1
/
1
I~
.1
1
T2
/
1
Cycle 4
Nonpipelined
(Read)
1
1
1
Idle
.1
1
Ti
1
/
T1
1
/
1
T2
1
Ti
CLK2
~~~~~~~~~~~~~ va~;'i_~_1 ~:~)(~ V~f'_id_2 ~~~~ va~;li_d_3 ~:~~~~~ v_a~;lid_4 ~~:~~~
___
W/R#
__
__
"l"I"l'$Wt~~~""--+-i---\.~
__
i
ri
__
__
___
__
~~~~---i..i--~~~~
/
/
/
/
/Bus Size/
/Bus Size/
/Bus Sizel
A::
/
/
/
/Bus Size/
/
BS16#~+_+ _ + ~+ ~
REAOY#~:~i~:~:~
~+~+ ~; ~; ~
LOCK#
~
_
~
I;
End Cycle 1
V~lid 1
X
r
031-00-1---1-< : 0"11:
Note:
Ii
End Cycle 2
V~lid 2
)(
~
;1
End
V~lid 3
Cy_~
~
i
I;
End Cycle 4
V~lid 4
I:
>@??OX
~
>1-~<: O~~ >t--1--$-~
Idle states are shown here for diagram variety only.
Tl486SXL Microprocessor Bus Interface
4-23
Bus Operation and Functional Timing
4.4.1.3
Nonpipelined Wait States
Once a bus cycle begins, it continues until acknowledged by the external system hardware using the READY# input. Acknowledging the bus cycle at the
end of the first T2 results in the shortest possible bus cycle, requiring only T1
and T2. If READY# is not immediately asserted however, T2 states are repeated indefinitely until the READY# input is sampled active. These intermediate T2 states are referred to as wait states. If the external system hardware
is not able to receive or deliver data in two bus states, it withholds the READY#
signal and at least one wait state is added to the bus cycle. Thus, on an address-by-address basis the system is able to define how fast a bus cycle completes.
Figure 4-6 illustrates nonpipelined bus cycles with one wait state added to
cycles 2 and 3. READY# is sampled inactive at the end of the first T2 state in
cycles 2 and 3. Therefore, the T2 state is repeated until READY# is sampled
active at the end of the second T2 and the cycle is then terminated. The microprocessor ignores the READY# input at the end of the T1 state.
Figure 4-6. Various Nonpipelined Bus Cycles With Different Numbers of Wait States
I
I
I
I
I
Idle
Ti
I
I
Cycle 1
Nonpipelined
~
(Read)
I
I
T1
:
T2
I
I
Cycle 2
Nonpipelined
(Write)
I
·r
I
T1
T2
I
I
Idle
I
I
Ti
~
T2
I
I
I
r
I
I
I
Cycle 3
Nonpipelined
(Read)
T1
T2
Idle
I
T2
~
I
Ti
CLK2
BE~~t~:..kwmL
V~lid 1:X
~ :~: ~ bxxxxd
"'~~~~~-""""'i---+----~----,i~-.....,.~~~~---~--,...i---f~~~~
I .IV
I
I
II
I _ II__.....I..II __.....~
M/IO#, O/C#
W/R#
Valid
~
AOS#
I
I
I
.I
Valid
"-lo~~~o.a.-_....
I
I
I
I
I
I
I
I
I
IBus Sizel
I
I
I
~~~~
I
I
I
I
I
IBus Size I
I
NA#~~~
I Bus Sizel
I
I
BS16#~+~+~+_
~~~II
READY#~:~i"':~:~:~
~+~I
~
_
LOCK# _
I:
V~lid
End
1
Cycle
X
1
031-00
4-24
I;
1
1
<
Idle states are shown here for diagram variety only.
~
:
,Valid
1
1
1 -In $
:
~---+----+1
1
Note:
1
+~I
End
CY.~
_
:1
,Valid
!
~
1
Out: 2
:
+
End
Cycle
3
~
I I I - < $In)
}-f---+---+3 -1
1
1
I
Wxxxxx!
Bus Operation and Functional Timing
4.4.1.4
Initiating and Maintaining Nonpipelined Cycles
The bus states and transitions for nonpipelined addressing are illustrated in
Figure 4-7. The bus transitions between four possible states: T1, T2, Ti, and
Th. Active bus cycles consist of T1 and T2 states, with T2 being repeated for
wait states. Bus cycles always begin with a single T1 state. T1 is always followed by a T2 state. If a bus cycle is not acknowledged during a given T2 and
NA# is inactive, T2 is repeated resulting in a wait state. When a cycle is acknowledged during T2, the following state is T1 of the next bus cycle if a bus
request is pending internally. If no internal bus request is pending, the Ti state
is entered. If the HOLD input is asserted and the microprocessor is ready to
enter the hold-acknowledge state, the Th state is entered.
Figure 4-7. Nonpipelined Bus States
HOLD Asserted
HOLD Negated
Request Pending
HOLD Negated
No Request
HOLD Asserted
READY# Asserted
HOLD Asserted
READY# Asserted
HOLD Negated
No Request
Always
Request Pending
HOLD Negated
READY# Asserted
HOLD Negated
Request Pending
Bus States:
T1 - First clock of a nonpipelined bus cycle (CPU drives new address and asserts ADS#)
T2 - Subsequent clocks of a bus cycle when NA# has not been sampled asserted in the current bus cycle
Ti - Idle state
Th - Hold acknowledge (CPU asserts HLDA)
The fastest bus cycle consists of two states: T1 and T2.
Tl486SXL Microprocessor Bus Interface
4-25
Bus Operation and Functional Timing
Because of the demultiplexed nature of the bus, the address pipelining option
provides a mechanism for the external hardware to have an additional T state
of access time without inserting a wait state. After the reset sequence and following any idle bus state, the processor always uses nonpipelined address
timing. Pipelined or nonpipelined address timing is then determined on a
cycle-by-cycle basis using the NA# input. When address pipelining is not used,
the address and bus-cycle definition remain valid during all wait states. When
wait states are added and nonpipelined address timing is necessary, negate
NA# during each T2 state of the bus cycle except the last one.
4.4.2
Bus Cycles Using Pipelined Addressing
The address pipelining option allows the system to request the address and
bus-cycle definition of the next internally pending bus cycle before the current
bus cycle is acknowledged with READY# asserted. If address pipelining is
used, the external system hardware has an extra T state of access time to
transfer data. The address pipelining option is controlled on a cycle-by-cycle
basis by the state of the NA# input.
4.4.2. 1
Pipelined Bus States
Pipelined addressing is always initiated by asserting NA# during a nonpipelined bus cycle. Within the nonpipelined bus cycle, NA# is sampled at the beginning of phase two of each T2 state and is only ac~nowledged by the microprocessor during wait states. When address pipelining is acknowledged, the
address (BE3#-BEO#, and A31-A2) and bus-cycle definition (W/R#, D/C#,
and M/IO#) of the next bus cycle are driven before the end of the nonpipelined
cycle. The address status output (ADS#) is asserted simultaneously to indicate validity of these signals. Once in effect, address pipelining is maintained
in successive bus cycles by continuing to' assert NA# during the pipelined bus
cycles.
As in nonpipelined bus cycles, the fastest bus cycles using pipe lined address
require only two bus states. Figure 4-8 illustrates the fastest read cycles using
pipelined address timing. The two bus states for pipelined addressing are T1 P
and T2P or T1 P and T21. The T1 P state is entered following completion of the
bus cycle in which the pipelined address and bus-cycle-definition information
was made available and is the first bus state of every pipelined bus cycle. In
other words, the T1 P state follows a T2 state if the previous cycle was nonpipelined, and follows a T2P state if the previous cycle was pipelined.
4-26
Bus Operation and Functional Timing
Figure 4-8. Fastest Pipelined Read Cycles
I
~
Cycle 1
Pipelined
(Read)
Cycle 2
Pipelined
(Read)
Cycle 3
Pipelined
(Read)
CLK2
A31-A2,
BE3#-BEO#,
M/IO#, D/C#, W/R#
-or----~~a..---..,...---~:F_.a.---..,.._--~':!I_~--..,....-
AD8#
NA#
B816#
READY#
LOCK#
D31-DO
(Input During Read)
~--t--~--t--~--t--~
I
Note:
I
I
I
I
I
I
Fastest pipelined bus cycles consist of T1 P and T2P.
Within the pipelined bus cycle, NA# is sampled at the beginning of phase two
(2) of T1 P. When a write cycle is acknowledged, the
write data remains valid throughout phase one (<1>1) of the next bus state to provide write-data hold time.
4.4.2.3
Pipelined Wait States
Once a pipelined bus cycle begins, it continues until acknowledged by the external system hardware using the microprocessor READY# input. Acknowledging the bus cycle at the end of the first T2P or T21 state results in the shortest possible pipelined bus cycle. If READY# is not immediately asserted, however, T2P or T21 states are repeated indefinitely until the READY# input is
sampled active. Additional T2P or T21 states are referred to as wait states.
Figure 4-9 illustrates pipelined bus cycles with one wait state added to cycles
1 through 3. Cycle 1 is a pipelined cycle with NA# asserted during T1 P and a
pending bus request. READY# is sampled inactive at the end of the first T2P
state in cycle 1. Therefore, the T2P state is repeated until READY# is sampled
active at the end of the second T2P and the cycle is then terminated. The microprocessor ignores the READY# input at the end of the T1 P state. ADS#,
the address, and the bus-cycle-definition signals for the pending bus cycle are
all valid during each of the T2P states. Also, asserting NA more than once during the cycle has no additional effects. Pipelined addressing can only output
information for the next bus cycle.
Cycle 2 in Figure 4-9 illustrates a pipelined cycle, with one wait state, where
NA# is not asserted until the second bus state in the cycle. In this case, the
CPU enters the T2 state following T1 P because NA# is not asserted. During
the T2 state the microprocessor samples NA# asserted. Because a bus request is pending internally, and READY# is not active, the CPU enters the T2P
state and asserts ADS#, a valid address, and bus-cycle-definition information
for the pending bus cycle. The cycle is then terminated by an active READY#
at the end of the T2P state.
Cycle 3 of Figure 4-9 illustrates the case where no internal bus request exists
until the last state of a pipelined cycle with wait states. In cycle 3, NA# is asserted in T1 P, requesting the next address. Because the CPU does not have
an internal bus request pending, The T21 state is entered. However, by the end
of the T21 state, a bus request exists. Because READY# is not asserted, a wait
state is added. The CPU then enters the T2P state and asserts ADS#, a valid
address, and bus-cycle-definition information for the pending bus cycle. As
long as the CPU enters the T2P state at some point during the bus cycle, pipelined addressing is maintained. NA# needs to be asserted only once during the
bus cycle to request pipelined addressing.
4-28
Bus Operation and Functional Timing
Figure 4-9. Various Pipelined Cycles (One Wait State)
Cycle 1
Pipelined ~I ...
(Write)
I
I~
T2P
Cycle 2
Pipelined
(Read)
I
I
~
T2P
Cycle 3
Pipelined
(Write)
...
I
I
I
T21
~
T2P
...
I
I
I
Cycle 4
Pipelined
(Read)
CLK2
A31-A2, __~__~~__~__________~____~~________~~~~~________~
BE3#- BEO#,
Valid 2
M/IO#, O/C# --,.--------I~--~----~I------r------+.~---:------+-;~~~~--.,-----~
'I
I
I
I as soon
I
AOS# is asserted
I
I
I
as the CPU has another
bus cycle to perform, which is
not always immediately after
NA# is asserted.
I
I
I
I
I
W/R#
I
I
AOS#
I
1
1
1
1
As long as the CPU enters the T2P
state during cycle 3, address
pipelining is maintained in cycle 4.
I
I
I
I
I
I
8S16#
REAOY#
*'
o
I
I
'
I
l"A,A~~Aj~A~
LOCK#
Valid 2
I
031-00
I
NA# could have been asserted in
T1 P if desired. Assertion now is
the latest time possible to allow
the CPU to enter T2P state to
maintain pipelining in cycle 3.
Valid 3
I
I
I
I
I
1
I
1
I
I
_~...u_t....X"--"'I"':--~--~}--r--f--¢x,...l:----'-~-ut-3-"""'-
TI486SXL Microprocessor Bus Interface
4-29
Bus Operation and Functional Timing
4.4.2.4
Initiating and Maintaining Pipelined Cycles
Pipelined addressing is always initiated by asserting NA# during a nonpipelined bus cycle with at least one wait state. The first bus cycle following reset,
an idle bus, or a hold-acknowledge state is always nonpipelined. Therefore,
the microprocessor always issues at least one nonpipelined bus cycle following reset, idle, or hold acknowledge before pipelined addressing takes effect.
Once a bus cycle is in progress and the current address has been valid for one
entire bus state, the NA# input is sampled at the end of every phase one until
the bus cycle is acknowledged. Once NA# is sampled active, the microprocessor is free to drive a new address and bus-cycle definition on the bus as early
as the next bus state and as late as the last bus state in the cycle.
Figure 4-10 illustrates the fastest transition possible to pipelined addressing
following an idle bus state. In cycle 1, NA# is driven during state T2. Thus,
cycle 1 makes the transition to pipelined address timing, since it begins with
T1 but ends with T2P. Because the address for cycle 2 is available before cycle
2 begins, cycle 2 is called a pipelined bus cycle, and it begins with a T1 P state.
cycle 2 begins as soon as READY# assertion terminates cycle 1.
Figure 4-10. Fastest Transition to Pipelined Address Following Idle Bus State
Idle
Cycle 2
Pipelined
(Read)
Cycle 1
Nonpipelined
(Write)
1
1
1
1
1
Cycle 3
Pipelined
(Write)
T1
I
I
T2
1
:
T2P
:
T1P :
T2P
1
Cycle 4
Pipelined
(Read)
1
1
"'1 4
"'14
"'14
Ti
1
I
T1 P
I
1
T2P
1
T1 P
I
I
1
T21
T21
1
Ti
CLK2
W/R#
~~~'-l-/~
'-____
"+--¥
AOS#
LOCK#"
1
1
031-00...L--..L-{
1
Note:
4-30
1
Following any idle bus state (Ti) the address is always nonpipelined and NA# is sampled only during wait states. To start
address pipelining after an idle state requires a nonpipelined cycle with at least one wait state (cycle 1 above). The pipelined cycles (2, 3, and 4 above) are shown with various numbers of wait states.
Bus Operation and Functional Timing
Figure 4-11 illustrates transitioning to pipelined addressing during a burst of
bus cycles. Cycle 2 makes the transition to pipelined addressing. Comparing
cycle 2 to cycle 1 of Figure 4-10 (on page 4-30) illustrates that a transition
cycle is the same when it occurs and consists of at least T1, T2 (NA# is asserted at that time), and T2P (provided the microprocessor has an internal bus
request already pending). T2P states are repeated if wait states are added to
the cycle. Cycles 2, 3, and 4 in Figure 4-11 show that once address pipelining
is achieved it can be maintained with two-state bus cycles consisting only of
T1P and T2P.
Once a pipelined bus cycle is in progress, pipelined timing is maintained for
the next cycle by asserting NA# and detecting that the microprocessor enters
T2P during the current bus cycle. The current bus cycle must end in state T2P
for pipelining to be maintained in the next cycle. T2P is identified by the assertion of ADS#. Figure 4-10 and Figure 4-11 each show pipelining ending after
cycle 4. This occurs because the microprocessor does not have an internal
bus request prior to the acknowledgment of cycle 4.
Figure 4-11. Transitioning to Pipelined Address During Burst of Bus Cycles
I
I
Idle
I
I
I
Ti
I
I
I
I
I
I
I
I
I
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Nonpipelined
Nonpipelined
Pipelined
Pipelined
Idle
I
-I _
(Write)
I
(Read)
1_
(Write)
I
(Read)
..L
----·,..-------~··14~----------~.Mr~---I--~·~14~------~~~I~~~~
T1
T2
I
T1
T2
T2P
I
T1 P
I
T2P
I
T1 P
I
Ti
CLK2
AOS#
BS 16#
"\/\/\./\/\/V\/\.I\/\/\,/\/\/.... /\/\.I\/\I',/\/\/.... /\/\/\/\I',/\/\)'\/\/\/\I
READY#~
LOCK#
031-00
Note:
¢m$
I
I
I
I
I
Valid 1
i
~I_ _"",--
-1---r--{
Out 1
I
Following any idle bus state (Ti), addresses are nonpipelined bus cycles, NA# is sampled only during wait states. Therefore, to begin address pipelining during a group of nonpipelined bus cycles requires a nonpipelined cycle with at least one
wait state (cycle 2 above).
Tl486SXL Microprocessor Bus Interface
4-31
Bus Operation and Functional Timing
The complete bus-state-transition diagram, including operation with pipelined
address, is given in Figure 4-12. This is a superset of the diagram for nonpipelined address. The three additional bus states for pipelined address are
shaded.
Figure 4-12. Complete Bus States
HOLD Asserted
READY# Asserted.
HOLD Asserted
NA# Asserted.
(HOLD Asserted +
No Request)
READY# Asserted.
HOLD Asserted
HOLD Negated.
Request Pending
HOLD Asserted
~--r-
Request Pending.
HOLD Negated
READY# Asserted.
HOLD Negated.
No Request
READY# Asserted.
HOLD Negated.
No Request
(No Request +
HOLD Asserted) •
NA# Asserted •
READY# Negated
I
I
I
I
I
I
I
I
NA# Negatedl
READY# Asserted.
HOLD Negated.
Request Pending
READY# Asserted.
HOLD Negated.
Request Pending
READY# Negated
Request Pending
HOLD Asserted
NA# Asserted.
HOLD Negated •
Request Pending
READY# Asserted
READY# Negated
Bus States:
T1 - First clock of a nonpipelined bus cycle (CPU drives new address and asserts ADS#)
T2 - Subsequent clocks of a bus cycle when NA# has not been sampled asserted in the current bus cycle
T21 - Subsequent clocks of a bus cycle when NA# has been sampled asserted in the current bus cycle but there
is not yet an internal bus request pending (CPU does not drive a new address or assert ADS#)
T2P - Subsequent clocks of a bus cycle when NA# has been sampled asserted in the current bus cycle and
there is an internal bus request pending (CPU drives new address and asserts ADS#)
T1 P - First clock of a pipelined bus cycle
Ti - Idle state
Th - Hold acknowledge state (CPU asserts HLDA)
4-32
Bus Operation and Functional Timing
4.4.3
Bus Cycles Using BS16#
Assertion of B816# during a bus cycle effectively changes the TI4868XL microprocessor 32-bit bus into a 16-bit data bus. Although slower, the 16-bit data
bus usually requires less hardware interface circuitry and generally offers
greater compatibility with 16-bit devices.
4.4.3.1
Nonpipelined Cycles
With B816# asserted, all operand transfers physically occur on data bus lines
015-00. With B816# asserted during a 32-bit nonpipelined read or write,
additional bus cycles are issued by the CPU to transfer the data.
For data reads with only the two upper bytes selected (BE3# and/or BE2# asserted), data is read from 015-00.
For data writes with only the two upper bytes selected (BE3# and/or BE2# asserted), data is duplicated on 015-00 and no further action is required.
For data reads with all four bytes selected (at least BE1 #, BE2# asserted and
possibly BEO# and/or BE3# also asserted), the CPU performs two 16-bit read
cycles using data lines 015-00. Lines 031-016 are ignored.
Oata writes with all four bytes selected (at least BE1#, BE2# asserted and
possibly BEO# and/or BE3# also asserted), the CPU performs two 16-bit write
cycles using data lines 015-00. Bytes 0 and 1 (corresponding to BEO#, BE1 #)
are sent on the first bus cycle (part one) and bytes 2 and 3 (corresponding to
BE2#, BE3#) are sent on the second bus cycle (part two). BEO# and BE1 # are
always negated during the second 16-bit bus cycle. Figure 4-13 illustrates two
nonpipelined bus cycles using B816#.
TI486SXL Microprocessor Bus Interface
4-33
Bus Operation and Functional Timing
Figure 4-13. Nonpipelined Bus Cycles Using BS 16#
Transfer Requiring Two Cycles
on 16-Bit Data Bus
Transfer Requiring Two Cycles
on 16-Bit Data Bus
,
( ---------~~--------~(--------~~~-------Idle
,
,
Cycle 1
,
Cycle 1A
Nonpipelined , Nonpipelined
~ Write, Part One , Write, Part Two
--,~
,
Ti
I
,T1
T2
,
,
,
Cycle 2
,
Cycle 2A
Pipelined
,
Pipelined
~ Read, Part One ~ Read, Part Two
,~
--I
I
T1
T2
,
T1
I
T2,
T1
I
T1
,
,Idle
J
--I
,
Ti
CLK2
BE1#,BEO#~~~I[J;~=7)A~IW~azy!s
~ln~ac~ti~ve~=J~~=7AA~IW~a~YS~I~na~c~tiv~e~~~!~~
~
During Part 2 I "---..,.....----{
Duri~g Part 2 I
BE3~~1E~~:
~
M/IO#,D/C#-'l;~~~~
~
~
AD8#
~l
~~.
I
B816#
x
x x
:'\.
X ('\.
I
I:
n
x
I
xxx
x
x
:X
x
I
I
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."
~
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x
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X
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~~
I
I,
X X
IXJ\
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I _~~I~~
i~
x
x
x
l2on't x xx xxxx
Don't x xx
X
x
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Care x xxx x
I
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IX X X xx Xli>.
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XX xxx xx
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I
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J\
Qon't
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J\xx
i
Valid 2 :
I
I
k
I
I
1\
III
I
W/R#~
NA#
:x
ya:lid 1 :
."
I
16-Bit
I
I
:":"
Xli>.
x
XY'x
Xx~
."
IBUSSize:.e:.e:
READY#_I.I~I_I
I
I
I
16-Bit
I
I
~e:
16-Bit
I
LOCK#$m$
I
D15-DO
D31-
I
-I---r-.-{
I
~
va:id1:
: d15-dO:
Out
I
I
X
~31-d16:
Out
~31-d16
1---r-<: : out:
I
D16
:
I
I
:
V+2
16-Bit
I
I
:
~
>-+--$--t--qr-t---I
d15-dO
I
d31-d16
I
>-t--CP--l--Y--r--I
:
I
Ignored
I
Ignored
I
Note: Dn = physical data pin n
dn = logical data bit n
4.4.3.2
Pipelined Cycles
The input signal NA# is a request to the CPU to drive the address, byte enables, and bus status signals for the next bus cycle as soon as they become
internally available. Pipelining this address allows the system logic to anticipate the next bus-cycle operation.
The CPU cannot acknowledge both address pipelining and 8S16# for the
same bus cycle. If NA# is already sampled when 8S16# is asserted, the data
bus remains 32 bits wide. If NA# and 8S16# are asserted in the same window,
NA# is ignored and 8S16# remains effective (the data bus becomes 16 bits
wide). Figure 4-14 illustrates the interaction between NA# and 8816#.
4-34
Bus Operation and Functional Timing
Figure 4-14. Pipelining and as 16#
A Transfer Requiring Two Cycles
on 16-Bit Bus
( ~-------------~~------------~~
Previous I
Cycle 1A
I
Cycle 1B
Cycle 2
Cycle
Pipelined
I
Nonpipelined
Nonpipelined
____~.~~~--W--rit-e-,P-a-rt-O-n-e--~.14~----W-r-ite-,-P-art_T'_w_o__~~.______R_e_a_d______~
I
T2P
Idle
I
I
T2
I
T1
CLK2
BE1#,BEO#
-+~------~----------~
BE~,kE~~:~
--r ~
....__
M/IO#, O/C#
W/R#
AOS#
~ v~a:l_id_1 ~~
___
__
____
~
________
~:~)(~ va~~li_d_2
~:)(~ Va_li~d_3
~
i
i
__
__
__
__
---+-:----+-:----1----1\.:\ : : :
t-Y---+---.L..l-~W : U
~"--____! ----'
j;',..-----IIf---.j....---r-:
I
I
NA#
____
I
I
I
NA# must be negated in these T's to allow
I recognit:on of ass~rted BS1 ~# in final T2s.
\1V\/'\AA,f\AA,/V
I
I
I
I
, 16-Bit I
I 16-Bit I
I:
~1~IBUSSizel~IBUSSizel ~I
REAOY#
~ .~ I
LOCK#~
:
V~lid1
I
d31)16
~
I
tiiiilpii" Bl&
:x:'alid~
~
:
d15-dO:
:
d15-dO
.
d31-d16:
031-016
:
~
I
d
I
I
I
.,--q:>--<:
~ut
X . O~t
>-.,---+--q::>---i
i
I
I
I
-,--q:>--<'
-r----,.._-..,.....__ -----r--..,...-J>---~--+-_q:>_-1
I
I
I
I
d15-dO
015-00
:
"I
I
I
:
d31- d 16 :
0 ut
:
:
d31 -d16
or-.
J
I
I
I
I
I
I
I
I
On = physical data pin n
dn = logical data bit n
Cycle 1A is pipelined. Cycle 1B cannot be pipelined, but its address can be inferred from cycle 1 to externally simulate
address pipelining during cycle 1B.
Tl486SXL Microprocessor Bus Interface
4-35
Bus Operation and Functional Timing
4.4.4
Locked Bus Cycles
When the LOCK# signal is asserted, the TI486SXL series microprocessors do
not allow other bus master devices to gain control of the system bus. LOCK#
is driven active in response to executing certain instructions with the LOCK
prefix. The LOCK prefix allows indivisible read/modify/write operations on
memory operands. LOCK# is also active during interrupt-acknowledge cycles.
LOCK# is activated on the CLK2 edge that begins the first locked bus cycle
and is deactivated when READY# is returned at the end of the last locked bus
cycle. When using nonpipelined addressing, LOCK# is asserted during phase
one (--t--~ -<: undefine~ >--~
(Floating)
t---t---~
Bus Operation and Functional Timing
4.4.7
Internal Cache Interface
The TI486SXL cache is an 8K-byte write-through unified instruction/data
cache with lines that are allocated only during memory read cycles. The cache
is configured as two-way set associative, and the cache organization consists
of 1024 sets each containing two lines of four bytes each.
4.4.7. 1 Cache Fills
Any unlocked memory read cycle can be cached by the TI486SXL series microprocessor. The microprocessor does not cache accesses automatically to
memory addresses specified by the Noncacheable-Region registers. Additionally, the KEN# input can be used to enable caching of memory accesses
on a cycle-by-cycle basis. The microprocessor acknowledges the KEN# input
only if the KEN enable bit is set in the CCRO Configuration register.
As shown in Figure 4-18, the microprocessor samples the KEN# input one
CLK2 before READY# is sampled active. If KEN# is asserted and the current
address is not set as noncacheable per the Noncacheable-Region registers,
the microprocessor fills two bytes of a line in the cache with the data present
on the data bus pins.
Figure 4-18. Nonpipelined Cache Fills Using KEN#
Cycle 2
Nonpipelined
(Read - Cache Fill)
1
1
14
CLK2
1
A31-A2,
BE3#-BEO#,
O/C#, M/IO#, W/R#
~
1
A08#
B816#
1
+id1
1
1
1
~
Valid 2
1
V f\ V
$Wr ~
~
1
1
I
I
NA#
LOCK#
031-00
1
I
I
I
I
1
1
-I
REAOY#
__I~
~
V~lid1
~
I
I
I
KEN#
•
I
I
1
1
~
1
1
1
I
1
I
I
:
valid2:
•
~--+--~--~---~--~-~
I~I
-T-f1~1
Tl486SXL Microprocessor Bus Interface
4-41
Bus Operation and Functional Timing
As shown in Figure 4-19 and Figure 4-20 on page 4-43, the microprocessor
samples the KEN# input one CLK2 before READY# is sampled active. If KEN#
is asserted and the current address is not set as noncacheable per the
Noncacheable-Region registers, the microprocessor fills two bytes of a line in
the cache with the data present on the data bus pins. The states of
BE3#-BEO# are ignored if KEN# is asserted for the cycle.
Figure 4-19. Nonpipelined Cache Fills Using KEN# and 8S16#
I
I
Cycle 1
Nonpipelined
(Read - Cache Fill)
Cycle 2
Nonpipelined
(Read - Cache Fill)
~
CLK2
I
A31-A2,
BE3#-BEO#,
O/C#, M/IO#, W/R#
~
I
•
V
V
~ ~ 1"1.
Valid 1
I
A08#
B816#
NA#
KEN#
~
I
i\
I
I
I
I
I
I
I
~
~
--.:;..J
I
On = physical data pin n
dn = logical data bit n
4-42
I
KEN# must be asserted during both read
cycles in order for the cache fill to occur.
LOCK#
031-00
(Input During Read)
Valid 2
:
i\
I
I
REAOY#
I
I
I
I
+d1
I
~
I
: valid<
I
•
I
I
d1S-dO
I
_ _ ~I __ ~ __ LI ___ ..JI __ ~_..JI
d1S-dO
~
I
I
~
I
I
I
I
Bus Operation and Functional Timing
Figure 4-20. Pipelined Cache Fills Using KEN#
Cycle 2
Pipelined
(Read - Cache Fill)
Cycle 1
Pipelined
(Read - Cache Fill)
I
I
l1li
CLK2
A31-A2,
BE3#-BEO#,
D/C#, M/IO#, W/R#
Valid 3
Valid 1
AD8#
I
NA#
B816#
KEN#
I
W~_
-~
\1/: \1 ;,.......:-
.
.
.
-f-I
I
READY#
I
LOCK#
Valid 1
I
I
I
~
.1Valid 2
~
I
Valid13
D31-DO
(Input During Read)
4.4.7.2
Flushing the Cache
To maintain cache coherency with external memory, the TI486SXL series microprocessors cache contents should be invalidated when previously cached
data is modified in external memory by another bus master. The microprocessor invalidates the internal cache contents during execution of the INVD and
WBINVD instructions following assertion of HLDA if the BARB bit is set in the
CCRD Configuration register or following assertion of FLUSH# if the FLUSH
bit is set in CCRD.
The microprocessor samples the FLUSH# input on the rising edge of CLK2
corresponding to the beginning of phase two (<1>2) of the internal processor
clock. If FLUSH# is asserted, the microprocessor invalidates the entire contents of the internal cache. The actual point in time where the cache is invalidated depends upon the internal state of the execution pipeline. FLUSH# must
be asserted for at least two CLK2 periods and must meet specified setup and
hold times to be recognized on a specific CLK2 edge.
Tl486SXL Microprocessor Bus Interface
4-43
Bus Operation and Functional Timing
4.4.8
Address Bit-20 Masking
The TI486SXL series microprocessor can be forced to provide 8086 1M-byte
address wraparound compatibility by setting the A20 bit in the CCRO Configuration register and asserting the A20M# input. When the A20M# is asserted,
the 20th bit in the address to both the internal cache and the external bus pin
is masked (zeroed).
As shown in Figure 4-21, the microprocessor samples the A20M# input on the
rising edge of CLK2 corresponding to the beginning of phase 2 (<1>2) of the internal processor clock. If A20M# is asserted and paging is not enabled, the microprocessor masks the A20 signal internally starting with the next cache access and externally starting with the next bus cycle. If paging is enabled, the
A20 signal is not masked regardless of the state of A20M#. A20 remains
masked until the access following detection of an inactive state on the A20M#
pin. A20M# must be asserted for a minimum of two CLK2 periods and must
meet specified setup and hold times to be recognized on a specific CLK2 edge.
Figure 4-21. Masking A20 Using A20M# During Burst of Bus Cycles
1
Idle
1
I
Ti
4-44
·tll
1
Cycle 1
Nonpipelined
(Write)
T1
I
1
I
.1
T2
Cycle 2
Nonpipelined
(Read)
1
4
1
T1
I
T2
I
1
1
T2P
·rI.
1
Cycle 3
Pipelined
(Write)
T1 P
I
T2P
1
1
I
·r
1
Cycle 4
Pipelined
(Write)
T1 P
I
1
T21
1
Ti
Bus Operation and Functional Timing
An alternative to using the A20M# pin is provided by the NCO bit in the CCRO
Configuration register. The microprocessor does not automatically cache accesses to the first 64K bytes and to 1M byte + 64K bytes if the NCO bit is set.
This prevents data within the wraparound memory area from residing in the
internal cache and eliminates the need for masking A20 to the internal cache.
4.4.9
Hold Acknowledge State
The hold-acknowledge state provides the mechanism for an external device
in a TI486SXL microprocessor system to acquire the system bus while the
microprocessor is held in an inactive bus state. This allows external bus
masters to take control of the microprocessor bus and directly access system
hardware in a shared manner. The microprocessor continues to execute
instructions out of the internal cache (if enabled) until a system bus cycle is
required.
The hold-acknowledge state (Th) is entered in response to assertion of the
HOLD input. In the hold-acknowledge state, the microprocessor floats all output and bidirectional signals, except for HLDA and SUSPA#. HLDA is asserted
as long as the microprocessor remains in the hold-acknowledge state and all
inputs except HOLD, FLUSH#, SUSP# and RESET are ignored.
State Th can be entered directly from a bus-idle state, as in Figure 4-22, or
after the completion of the current physical bus cycle if the LOCK signal is not
asserted, as in Figure 4-23 and Figure 4-24. The CPU samples the HOLD input on the rising edge of CLK2 corresponding to the beginning of phase one
(1) of internal processor clock. HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold requirements are met in every bus state.
The hold-acknowledge state is exited in response to the HOLD input being negated. The next bus start is an idle state (Ti) if no bus request is pending, as
in Figure 4-22. If an internal bus request is pending, as in Figure 4-23 and
Figure 4-24, the next bus state is T1 . Th is also exited in response to RESET
being asserted. If HOLD remains asserted when RESET goes inactive, the
microprocessor enters the hold-acknowledge state before performing any bus
cycles provided HOLD is still asserted when the CPU is ready to perform its
first bus cycle.
If a rising edge occurs on the edge-triggered NMI input while in Th state, the
event is remembered as a nonmaskable interrupt 2 and is serviced when the
state is exited.
Tl486SXL Microprocessor Bus Interface
4-45
Bus Operation and Functional Timing
Figure 4-22. Requesting Hold From Bus-Idle State
I
I
I
I
Idle
Hold Acknowledge
Idle
Ti
Th
I
I
Th
I
I
Th
Ti
CLK2
III
HOLO
(Note 1)
HLOA
AOS#
(Note 2)
I
I
I
i~i
I
I
I
I
I
~--~V
I
A31-A2,
BE3#-BEO#,
O/C#, M/IO#, W/R#
I
I
~~~I--------~
I
:
----+~
I
I
:
:\----1
I
I
i----I
1
(Floating)
I
I
_ _
I
I
I
I
I
~
I
I
I
I '-----.1-- (Floating) -.1------1-'
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
BS16#,
NA#,
REAOY#
LOCK#
~----+I
031-00
Notes:
(Floating)
1-----_.
I
I
I
I
I
I
I
I
I I
I
I
I
I
--+------I------.J.-, (Floating) ..J------I------I
1) HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold requirements are
met in every bus state. Violating setup or hold requirements will result in incorrect operation.
2) For maximum design flexibility the CPU has no internal pullup resistors on its outputs. External pullups may be required on ADS# and other outputs to keep them negated during hold-acknowledge period.
4-46
Bus Operation and Functional Timing
Figure 4-23. Requesting Hold From Active Nonpipelined Bus
I~
1
Hold Acknowledge
Cycle 1
Nonpipelined
(Read)
1
T2
T1
T2
1
1
~I
.14
I
Th
1
Th
Cycle 2
Nonpipelined
(Write)
T1
1
1
~
T2
1
1
CLK2
1
HOLD
(See Note) -
.......-----i------i----
:I
I
\
~~------~------~
HOLD asserted no later
than READY# asserted
HLDA
1
1
A31-A2,--~~--~-----~--~-~
BE3#-BEO#,
D/C#, M/IO#, W/R# -+-..a.-----..,...-----...,...--~-__f
1
- - (Fla1ating )
I
ADS#
I
~-- (Flo~ting)
I
I
I
I~____~~____~
---K'-____
\l"Tt_lid__
2__
1
---i
~
I
,~_ _ _ _~.
1
V I
I
1
NA#
BS16#
READY#
(Negaled, or lasl locked cycle)
LOCK#
;
Note:
I
:
---K\",__---,I"""'\l_al_id_2_~
-+---- (~Iaaling) '-+---$--- (~Iaaling) .-~-<\",-~:_O_u_t2_~
I
D31-DO
Valid 1 ;
!
( - - (Fla~ling)
'-
I
I
1
1
HOLD is a synchronous input and can be asserted at any CLK2 edge provided setup and hold requirements are met in every bus state.
Violating setup or hold requirements will result in incorrect operation.
Tl486SXL Microprocessor Bus Interface
4-47
Bus Operation and Functional Timing
Figure 4-24. Requesting Hold from Active Pipelined Bus
Hold Acknowledge
Cycle 1
Pipelined
(Write)
1
I..
1
1
1
.1II1II
..1II1II
1
T1P
1
1
T21
T21
Cycle 2
Nonpipelined
(Read)
1
Th
1
Th
1
T1
T2
CLK2
HOLD
(See Note)
HOLD asserted in same bus
state as NA# asserted.
HLDA
I
I
1
1
1
1
1
-"'---+--':""""71:'~~~~~~~
A31-A2,
BE3#-BEO#,
D/C#, M/IO#, W/R# -.,---~-.,......~~~~~~~
I
- + - -........--~---~I
ADS#
NA#
LOCK#
!
1
1
I
'--- (FI~ating)
---K
1
- - (Flo1atin g )
:
Valid 2
1. .
1
--{
V
I
~
~
IIIIII
~
I~:
I
1
~
_
(Negated. or last locked cycle)
:
Valid 1
D31-~ ~-t""II"'x--_.:.
-O
....
:
I
~
- - (Flottin g)
.
I
~
I
I
I
--i
:
~alid
1
1
I
1
1
I
:
2
.
-~>+--. (Flo~ting) ---i--~
---O
..........
t 1 - -.......
:
I
Note:
1
1
~
BS1~$'!
READY#
1
I
1
HOLD is a synchronous input and can be asserted at any CLK2 edge provided setup and hold requirements are met in
every bus state. Violating setup or hold requirements will result in incorrect operation.
4.4.10 Coprocessor Interface
The data-bus, address-bus, and bus-cycle-definition signals, as well as the coprocessor interface signals (PEREQ, BUSY#, ERROR#), are used to control
communication between the TI486SXL series microprocessor and a coprocessor. Coprocessor or ESC opcodes are decoded by the microprocessor and
the opcode and operands are then transferred to the coprocessor via I/O port
accesses to addresses 8000 00F8h and 8000 OOFCh. Address 8000 00F8h
functions as the control-port address and 8000· OOFCh is used for operand
transfers.
4-48
Bus Operation and Functional Timing
Coprocessor cycles can be either read or write and can be either nonpipelined
or pipelined. Coprocessor cycles must be terminated by READY# and, as with
any other bus cycle, can be terminated as early as the second bus state of the
cycle.
BUSY#, ERROR#, and PEREQ are asynchronous level-sensitive inputs used
to synchronize CPU and coprocessor operation. All three signals are sampled
at the beginning of phase one (<1>1) and must meet specified setup and hold
times to be recognized at a given CLK2 edge.
4.4.11 SMM Interface
System Management Mode (SMM) uses two TI486SXL microprocessor pins,
SMI# and SMADS#. The bidirectional SMI# pin is a nonmaskable interrupt that
is a higher priority than the NMI input. SMI# must be active for at least four
CLK2 periods to be recognized by the microprocessor. Once the microprocessor recognizes the active SMI# input, the CPU drives the SMI# pin low for the
duration of the SMI service routine.
The SMADS# pin outputs the SMM address strobe that indicates an SMM
memory bus cycle is in progress and a valid SMM address is on the address
bus. The SMADS# functional timing, output delay times, and float delay times
are identical to the main memory address strobe (ADS#) timing.
4.4.11.1 SMI Handshake
The functional timing for SMI# interrupt is shown in Figure 4-25. Five significant events take place during an SMI# handshake:
1) The SM 1# input pin is driven active (low) by the system logic.
2) The CPU samples SMI# active on the rising edge of CLK2 phase one (<1>1).
3) Four CLK2s after sampling the SMI# active, the CPU switches the SMI#
pin toan output and drives SMI# low.
4) Following execution of the RSM instruction, the CPU drives the SMI# pin
high for two CLK2s indicating completion of the SMI service routine.
5) The CPU stops driving the SMI# pin high and switches the SMI# pin to an
input in preparation for the next SMI interrupt. The system logic is responsible for maintaining the SMI# pin at the inactive (high) level after the pin
has been changed to an input.
Figure 4-25. SMI# Timing
CLK2
(Input)
SMI#
~~i--~--~i----~)(~)l--~i/
I
I
I
I
I
I
I
I
2 3 4
I
I
I
I
5
Indicates that TI486SXL drives the SMI# pin.
Tl486SXL Microprocessor Bus Interface
4-49
Bus Operation and Functional Timing
4.4.11.2 liD Trapping
The TI4868XL series provides I/O trapping that can be used to facilitate power
management of I/O peripherals. When an I/O bus cycle is issued, the I/O address is driven onto the address bus and can be decoded by external logic. If
a trap to the SMI handler is required, the 8MI# input should be activated at
least three CLK2 edges prior to returning the READY# input for the I/O cycle.
The timing for creating an I/O trap via the SMI# input is shown in Figure 4-26.
The microprocessor immediately traps to the SMI interrupt handler following
execution of the I/O instruction, and no other instructions are executed between completion of the I/O instruction and entering the 8MI service routine.
The I/O trap mechanism is not active during coprocessor accesses.
Figure 4-26. liD Trap Timing
I
1/0 CYCLE
(Read or Write)
14
T2
I
T1
I
T2
I
T2
I
CLK2
(Input)
I
Address,
Byte Enables
ADS#
(Output)
READY#
SMI#
I
~
I
\mozxxxxxxxxxx
V :I'd
"'~~~~~~--Io._ _........_ _ _ _a.,...I_~_""""_ _ _--10~--11'~~~~~~~
I
I
V:
I
:
I
I
I
I
I
I
------~:\
I
~
!
\,--_~i~~~~~~
~II
:I \'-+I----------IlooJ/
I
I
I
j4--
4-50
3 CLK2s
~
Bus Operation and Functional Timing
4.4.12 Power Management
The power-management features in the TI486SXL(C} family of microprocessors allow a dramatic reduction in the current required when the microprocessor is in suspend mode (typically less than three percent of the operating current). Suspend mode is entered either by a hardware- or software-initiated
action. Using the hardware to initiate suspend mode involves a two-pin handshake using the SUSP# and SUSPA# signals. Using the software involves initiating the suspend mode through execution ofthe HALT instruction. Additional
power management can be achieved by stopping and restarting the input
clock. This technique is available because the TI486SXLC series microprocessors are static devices, meaning that clock can be stopped and restarted
without loss of any internal CPU data.
4.4.12.1 SUSP#-initiated Suspend Mode
The TI486SXL series microprocessor enters suspend mode when the SUSP#
input is asserted and execution of the current instruction, any pending decoded instructions, and associated bus cycles are completed. The microprocessor also waits forthe coprocessor to indicate a not-busy status (BUSY#=1)
prior to entering suspend mode. The SUSPA# output is then asserted. The
microprocessor responds to SUSP# and asserts SUSPA# only if the SUSP bit
is set in the CCRO Configuration register.
Figure 4-27 illustrates the microprocessor functional timing for SUSP#-initiated suspend mode. SUSP# is sampled on the phase two ($2) CLK2 rising
edge and must meet specified setup and hold times to be recognized at a particular CLK2 edge. The time from assertion of SUSP# to activation of SUSPA#
varies depending on which instructions were decoded prior to assertion of
SUSP#. The minimum time from SUSP# sampled active to SUSPA# asserted
is two CLK2s. As a maximum, the microprocessor can execute up to two
instructions and associated bus cycles prior to asserting SUSPA#. The time
required for the microprocessor to deactivate SUSPA# once SUSP# has been
sampled inactive is four CLK2s.
Figure 4-27. SUSP#-Initiated Suspend Mode
<\>1
I
<\>2
I
I
I <\>1 I <\>2 I <\>1 I <\>2
<\> 1 I<\>2
<\>1 I
<\>2
<\> 1 I<\>2
CLK2
SUSP#
BUSY#
~---
4 CLK2s - - - - -
SUSPA#
Tl486SXL Microprocessor Bus Interface
4-51
Bus Operation and Functional Timing
If the microprocessor is in a hold-acknowledge state and SUSP# is asserted,
the processor mayor may not enter suspend mode depending on the state of
the microprocessor internal execution pipeline. If the microprocessor is in a
SUSP#-initiated suspend state and the CLK2 input is not stopped, the processor recognizes and acknowledges the HOLD input and stores the occurrence
of FLUSH#, NMI, and INTR (if enabled) for execution once suspend mode is
exited.
4.4.12.2 Halt-Initiated Suspend Mode
The TI486SXL series microprocessor also enters suspend mode as a result
of executing a HALT instruction. The SUSPA# output is asserted no more than
17 CLK2s following READY# sampled active for the HALT bus cycle as shown
in Figure 4-28. Suspend mode is then exited upon recognition of an NMI or
an unmasked INTR. SUSPA# is deactivated 12 CLK2s after sampling of an active NMI or unmasked INTR. If the microprocessor is in a HALT-initiated suspend mode and the CLK2 input is not stopped, the processor recognizes and
acknowledges the HOLD input and stores the occurrence of FLUSH# for
execution once suspend mode is exited.
Figure 4-28. HALT-Initiated Suspend Mode
I
~ Nonpipelined HALT
I
I
T1
T2
4
I
I
I
Ti
Ti
Ti
CLK2
I
--\
ADS#
BE3#,BE1#,
BEQ#, M/IO#,
W/R#,
I
(( I
/~----+-II---~)) I
I\'-_ _ _..J.
I
I
I
I
I
I
I
I
I
AA
((
))
I
I
I
I
I
I
~I: ~I
I
I
I
~I
I
YJ/:
'I
~I ~. ~
A31-A2,-\
BE2#,D/C#
_~...,....,._ _ _ _ _ _ _ _~~~~~~~~
I
( I
READY#
I
(( I
) 1
I
1
)) 1
1
1
__-r-I
NMI
I
17 CLK2s Max -11.~-----f---.1
I
12
I
1
I
I'-CL~2Sl
L
(I
1
) 1
1
1
1
I
SUSPA#
1
1
4.4.12.3 Stopping the Input Clock
Because the TI486SXL series microprocessors are static devices, the input
clock (CLK2) can be stopped and restarted without loss of any internal CPU
4-52
Bus Operation and Functional Timing
data. This assumes, of course, that the TI486SXL2 microprocessor is in nonclock-doubled mode when the input clock is stopped. (Refer to subsection
4.2.1, Clock Doubling Using Software Control, page 4-15.) CLK2 can be
stopped in either phase one (<1>1) or phase two (<1>2) of the clock and in either
a logic-high or logic-low state. However, entering suspend mode prior to stopping CLK2 dramatically reduces the CPU current requirements. Therefore, the
recommended sequence for stopping CLK2 of the TI486SXLC2 series microprocessor from clock-doubled mode is:
1) Bring the processor out of clock-doubled mode
2) Initiate suspend mode
3) Wait for assertion of SUSPA# by the processor
4) Stop the input clock
Note:
Suspend mode can be entered while in clock-doubled mode as long as CLK2
is not scaled or stopped.
For all other cases, including the TI486SXLC2 in nonclock-doubled mode, the
recommended sequence is:
1) Initiate suspend mode
2) Wait for assertion of SUSPA# by the processor
3) Stop the input clock
The TI486SXL series microprocessor remains suspended until CLK2 is restarted and suspend mode is exited as described above. While CLK2 is
stopped, the microprocessor can no longer sample and respond to any input
stimulus including the HOLD, FLUSH#, NMI, INTR, and RESET inputs.
Figure 4-29 illustrates the recommended sequence for stopping CLK2 using
SUSP# to initiate suspend mode. CLK2 should be stable for a minimum of 10
clock periods before SUSP# is deasserted.
Figure 4-29. Stopping CLK2 During Suspend Mode
I
I
CLK2
SUSP#
hll
\
<1>1
I
<1>2
I
I
<1>1
I
<1>2
I
I
1
I
1
rI
~AAN-Lt-
<1>1
1
-------~((~----------------~((~--+---~(
))
)))
__
)
----~((~------------
1
BUSY#
-------\((
( (
))
))
1
( ( ' r - - - - - - - - -.....
((....- - - - - - - - - - - - I
))
))
1....- - - 10 CLK2s Min -----.t.1
1
_____---\((~----~
SUSPA#
))
\ _ _ _ _ _ _ _......(
(~----___*.())(~-------- ))~(
......(
I
V
_____
))
Tl486SXL Microprocessor Bus Interface
4-53
Bus Operation and Functional Timing
4.4.13 Float (144-Pin QFP and 168-Pin PGA Pinouts Only)
Activating the FLT# input on the 144-pin or 168-pin TI486SXL floats all bidirectional and output signals. Asserting FLT# electrically isolates the microprocessor from the surrounding circuitry. This feature is useful in systems designs
that contain an upgrade socket.
FLT# is an asynchronous, active-low input. It is recognized on the rising edge
of CLK2. When recognized, it aborts the current bus state and floats the outputs of the microprocessor as shown in Figure 4-30. FLT# must be asserted
for a minimum of 16 CLK2 cycles. To exit the float condition, RESET should
be asserted and held asserted until after FLT# is deasserted.
Asserting the FLT# input unconditionally aborts the current bus cycle and
forces the microprocessor into the float mode. As a result, the microprocessors are not guaranteed to enter float in a valid state. After deactivating FLT#,
the CPU is not guaranteed to exit float in a valid state. The microprocessor
RESET input must be asserted prior to exiting float to ensure that the microprocessor is reset and that it returns in a valid state.
Figure 4-30. Entering and Exiting Float
CLK2
FLT# ,
CONTROL
~
_ _ _ _ _ _ _ _ _ _ _ _,
Valid
DATA - - { } - {
ADDRESS
RESET
4-54
}_------------------{~_ _ _ _ _ _X~
Valid
___
C
} - - - - - - - - - - - - - - - - - - {_ _ _ _ _
~o....-_ _v_al_id_ __ ' } - - - - - - - - - - - - - - - - - - {_ _ _ _X___
------,
Chapter 5
Electrical Specifications
Electrical specifications for the TI486SXL(C) family of microprocessors are
provided in this chapter. The specifications include electrical connection requirements for all package pins, maximum ratings, recommended operating
conditions, dc electrical characteristics, and ac characteristics.
Page
Topic
5:2· Absolvt~ 'Maximl;lmR~tings . ·.. 0 . ; . . . . . ~ • • • "
.
.
·5.3flecQrnrt1e.,d~d O'pel'~~ing
5.4.
CQrlcfitions .;. d
••• ' ••••••• o ..............
. . . . . . . . . . ; '0. • • • • • • •'
.~
••
5-4
5-5
DC Electti~al·Characteri$ties .........'....... ~ •.. " .~ ...• ~ .......... ' 5~7
,
~,
"
_
"
'
, <
5~!? ·ACCha.ra.ct~ristics~
"
,:'
J ,
'
,
-,
,
>
.... '.......:..~ 0:; .~;; , •••••• ; '0. "'0 •• ~.. • • . •
•. 5.:16
5-1
Electrical Connections
5.1
Electrical Connections
This section provides specific requirements for power and ground connections, decoupling, termination of inputs with internal pullup/pulldown resistors,
termination of system functional inputs requiring external pullup resistors, termination of unused inputs, and connection to terminals designated NC.
5.1.1
Power and Ground Connections and Decoupling
The high-frequency operation of the TI486SXL(C) microprocessors makes it
necessary to install and test the devices using standard high-frequency techniques. The high clock frequencies used in the microprocessors and their output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the dc power leads with low-inductance decoupling capacitors, using
low-impedance wiring, and by making connection to all of the V CC, V CC5, and
Vss (GNO) terminals.
5.1.2
Pullup/Pulidown Resistors
Table 5-1 list~ the input terminals that are internally connected to pullup and
pulldown resistors (see Figure 5-1). The pullup resistors are connected to
VCC and the pulldown resistors are connected to VSS. When unused, these
inputs do not require connection to external pullup or pulldown resistors.
Note:
The internal pullup and pulldown resistors are designed to tie off the individual internal signal associated with that pin. External signals should not be terminated to any of these pins.
Table 5-1. Terminals Connected to Internal Pullup and Pulldown Resistors
Signal
TI486SXLC
100-Terminal
TI486SXL
132-Terminal
TI486SXL
144-Terminal
TI486SXL
168-Terminal
Resistor
A20M#
31
F13
43
D15
Pullup
8USY#
34
89
48
S4
Pullup
C14
115
C17
Pullup
A8
49
A12
Pullup
40
C11
Pullup
C15
Pullup
8S16#
ERROR#
36
FLT#
28
FLUSH#
30
E13
42
KEN#
29
812
41
F15
Pullup
66
816
Pullup
MEMW#
PEREQ
37
C8
50
R17
Pulldown
SMI#
47
C7
67
810
Pullup
SUSP#
43
A4
63
C13
Pullup
5-2
Electrical Connections
Figure 5-1. Internal PulluplPulldown-IV Characteristic
60
50
«:::t
40
-......
I
cCI): 30
j
0
20
10
0
/
/
o
I
/V
/
0.5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Voltage-V
It is recommended that the ADS# and LOCK# output terminals be connected
to pullup resistors, as indicated in Table 5-2. The external pullups ensure that
the signals remain negated during hold-acknowledge states.
Table 5-2. Terminals Requiring External Pullup Resistors
Signal
TI486SXLC
100-Terminal
TI486SXL
132-Terminal
TI486SXL
144-Terminal
TI486SXL
168-Terminal
ADS#
16
E14
26
S17
20-kQ pullup
LOCK#
26
C10
38
N15
20-kQ pullup
5.1.3
External
Resistor
NC Designated Terminals
Terminals designated NC should be left disconnected. Connecting or terminating any NC terminal(s) to a pullup resistor, pulldown resistor, or an active signal
can cause unpredictable results or nonperformance of the microprocessor.
5.1.4
Unused Signal Input Terminals
All signal inputs not used by the system designer and not listed in Table 5-1
should be connected eitherto VSsortoVCc. Connect active-high inputs to Vss
through a 20-k,Q (±100/0) pulldown resistor and active-low inputs to VCC
through a 20-k,Q (±1 0%) pullup resistor to prevent possible spurious operation.
Electrical Specifications
5-3
Absolute Maximum Ratings
5.2 Absolute Maximum Ratings
The absolute maximum ratings provide specific limits regarding power supply
and input voltages, input and output current limits, and operating and storage
temperatures.
Table 5-3 specifies the absolute maximum ratings for the TI486SXL(C) family
of microprocessors.
Table 5-3. Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)t
Min
Max
Unit
TI486SXLC and TI486SXL
With respect to VSS
-0.5
6.5
V
TI486SXLC-V, TI486SXL-V,
TI486SXLC-G, and TI486SXL-G
With respect to V SS
-0.3
5.5
V
Voltage on any terminal
With respect to V SS
-0.5
Case temperature
Power applied
-65
110
°C
Storage temperature
No bias
-65
150
°C
Parameter
Supply voltage, VCC
t
VCC+0.5
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended
operating conditions is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device
reliability.
5-4
Recommended Operating Conditions
5.3 Recommended Operating Conditions
Recommended operating conditions provide specific values for power supply
and input voltages, required input threshold ranges, output drive currents
available for system interfacing, and operating levels for clamp currents and
case temperature.
5.3.1
3.3-Volt Microprocessors With 5-Volt Tolerant Inputs, Outputs, and II0s
Table 5-4 presents the recommended operating conditions for the
TI486SXL-G 3.3-V microprocessors with 5-V-tolerant inputs, outputs, and
liDs.
During power up and power down conditions, the 3.3-V VCC terminals and the
5-VVCC5 terminal should be ramped simultaneously asthe 3.3-VVCCvoltage
should not exceed the 5-V VCC5 voltage by more than 1 V or the device may
not initialize correctly. Conversely, the 5-V V CC5 can exceed the 3.3-V VCC by
up to 2.25 V.
Table 5-4. TI486SXL -G Recommended Operating Conditions
Min
Max
Unit
VCC
Supply voltage t
With respect to VSS
See Note 1
3
3.6
V
VCC5
Supply voltage:j:
With respect to VSS
See Note 2
3
5.25
V
VIH
High -level input voltage
2
VCC5+ 0 .3
V
VIL
Low-level input voltage
-0.3
0.6
V
VILC
CLK2 low-level input voltage
-0.3
0.5
V
VIHC
CLK2 high -level input voltage
VCC-0.3
VCC5+ 0 .3
IOH
High -level output current
VOH
IOL
Low-level output current
VOL =VOL(max)
PLLLOCK
Phase -locked loop frequency
lock range
With respect to CLK 2
frequency
tc
Notes:
Case temperature
rnA
5
rnA
32
50
MHz
TI486SXLC in 100-pin
QFP
0
85
TI486SXL in 132- and
168-pin PGA
0
85
TI486SXL in 144-pin
QFP
0
85
= VOH(min)
Power
applied
V
-2
°c
1) VCC should be no more than 1 V greater than VCC5 during power up or the device may not initialize correctly.
2) VCC5 should be connected to the 3.3-V supply in a3.3-V~only system. In mixed systems (3.3/5 V) VCC5 should be
connected to the 5-V supply.
Electrical Specifications
5-5
Recommended Operating Conditions
5.3.2
3.3-Volt Microprocessors
Table 5-5 presents the recommended operating conditions for the
TI486SXLC-V and TI486SXL-V 3.3-V microprocessors.
Table 5-5. TI486SXLC-V and TI486SXL-V Recommended Operating Conditions
Min
VCC
Supply voltage
VIH
High -level input voltage
With respect to VSS
"Max
Unit
3
3.6
V
2
VCC+0.3
V
VIL
Low-level input voltage
-0.3
0.6
V
VILC
CLK2 low-level input voltage
-0.3
0.5
V
VIHC
CLK2 high -level input voltage
VCC-0.3
VCC+0.3
V
IOH
High -level output current
IOL
Low-level output current
VOL= VOL(max)
PLLLOCK
Phase -locked loop frequency
lock range
With respect to CLK2
frequency
Case temperature
tc
5.3.3
-2
rnA
5
rnA
32
50
MHz
TI486SXLC in 100-pin
OFP
0
85
TI486SXL in 132- and
168-pin PGA
0
85
TI486SXL in 144-pin OFP
0
85
VOH = VOH(min)
Power
applied
°c
5-Volt Microprocessors
Table 5-6 presents the recommended operating conditions for the
TI486SXLC and TI486SXL 5-V microprocessors.
Table 5-6. TI486SXLC and TI486SXL Recommended Operating Conditions
Min
Max
Unit
4.75
5.25
V
VCC
Supply voltage
VIH
High -level input voltage
2
VCC+0.3
V
VIL
Low-level input voltage
-0.3
0.8
V
VILC
CLK2 low-level input voltage
-0.3
0.8
V
VIHC
CLK2 high -level input voltage
3.7
VCC+0.3
IOH
High -level output current
IOL
Low-level output current
PLLLOCK
Phase -locked loop frequency
lock range
With respect to CLK 2
frequency
tc
5-6
Case temperature
With respect to VSS
V
VOH=VOH(min)
-1
rnA
VOL = VOL(max)
5
rnA
32
50
MHz
TI486SXLC in 100-pin
OFP
0
100
TI486SXL in 132- and
168-pin PGA
0
85
TI486SXL in 144-pin
OFP
0
100
Power
applied
°C
DC Electrical Characteristics
5.4 DC Electrical Characteristics
The dc electrical characteristics tables provide specific data regarding the capabilities of the TI486SXL(C) family microprocessors to interface directly with
either CMOS- or TTL-type system functions. Devices are offered for operation
in 3.3 and 5-volt mixed, 3.3-volt only, and 5-volt only systems.
5.4.1
3.3-Volt Microprocessors With 5-Volt-Tolerant Inputs, Outputs, and 1I0s
o
o
Table 5-7 covers the 3.3-V 40, 20-MHz TI486SXL-G40.
Table 5-8 on page 5-8 covers the 3.3-V 50-MHz TI486SXL2-G50.
Table 5-7. T1486SXL-G40 Electrical Characteristics at Recommended Operating
Conditions (Typical values are at VCC = 3.3 \I, VCC5 = 5 \I, and 1A = 25°C)
T1486SXL-G40
Parameter
VOL
Low-level output voltage
Test Conditions
0.4
II
Input current (leakage)
VIN = 0, VIN ~ VCC
See Note 1
IIH
High-level input current at
PEREQ
VIN = 2.4,
See Note 2
IlL
Low-level input current
VIL = 0.45 V,
See Note 3
Unit
V
V
10H =-0.2mA
VCC-O.4
Supply current (Active mode)
20 MHz (CLK2 = 40 MHz)
ICCSM
Supply current (Suspend mode)
20 MHz
(CLK2 = 40 MHz)
ICCSS
Standby supply current
CIN
Input capacitance
fc = 1 MHz,
COUT
Output or I/O capacitance
Input capacitance CLK2
CCLK
Max
2.4
10H =-1 rnA
High-level output voltage
Notes:
Typ
IOL=3 rnA
VOH
ICC
Min
-,:
~
±15
~A
200
~A
-400
~A
400
rnA
300
rnA
15
See Note 4
o MHz, Suspended/CLK2 stopped,
0.1
1
rnA
See Note 5
10
pF
fc = 1 MHz,
See Note 5
12
pF
fc = 1 MHz,
See Note 5
20
pF
See Note 4
1) Applicable for all input terminals except those with an internal pullup resistor. See Table 5-1.
2) PEREQ has an internal pulldown resistor.
3) Applicable for all inputs that have an internal pullup resistor. See Table 5-1.
4) All inputs at 0 or VCC. All inputs held static, (except CLK2 as indicated). All outputs unloaded (static lOUT = 0 rnA).
5) Not 100% tested
Electrical Specifications
5-7
DC Electrical Characteristics
Table 5-8. T1486SXL2-G50 Electrical Characteristics at Recommended Operating
Conditions (Typical values are at VCC = 3.3 V, VCC5 = 5 V, and 1A = 25°C)
Parameter
VOL
Low-level output voltage
VOH
High-level output voltage
II
Input current (leakage)
VIN = 0, VIN ;::: VCC
See Note 1
IIH
High-level input current at
PEREa
VIN = 2.4,
See Note 2
See Note 3
Min
Typ
Max
0.4
10L= 3 rnA
Unit
V
2.4
10H =-1 rnA
V
IOH =-0.2 rnA
VCC-O.4
IlL
Low-level input current
VIL = 0.45 V,
ICC
Supply current (Active mode)
25 MHz (CLK2 = 50 MHz)
ICCSM
Supply current (Suspend mode)
25 MHz
(CLK2 = 50 MHz)
ICCSS
Standby supply current
CIN
Input capacitance
fc = 1 MHz,
See Note 5
COUT
Output or 1/0 capacitance
fc = 1 MHz,
CCLK
Input capacitance CLK2
fc = 1 MHz,
Notes:
T1486SXL2-G50
Test Conditions
See Note 4
o MHz, Suspended/CLK2 stopped,
~
'%~
365
±15
~A
200
~A
-400
~A
500
rnA
20
rnA
1
rnA
10
pF
See Note 5
12
pF
See Note 5
20
pF
See Note 4
0.1
1) Applicable for all input terminals except those with an internal pullup resistor. See Table 5-1.
2) PEREQ has an internal pulldown resistor.
3) Applicable for all inputs that have an internal pullup resistor. See Table 5-1.
4) All inputs at 0 or VCC. All inputs held static, (except CLK2 as indicated). All outputs unloaded (static lOUT = 0 rnA).
5) Not 100% tested
5-8
DC Electrical Characteristics
5.4.2
3.3-Volt Microprocessors
o
o
o
Table 5-9 covers the 3.3-V 25-MHz TI486SXLC-V25.
Table 5-10 on page 5-10 covers the 3.3-V 40,20 MHz TI486SXL-V40.
Table 5-11 on page 5-11 covers the 3.3-V 50,25 MHz T1486SXL2-V50
Table 5-9. TI486SXLCB- V25 Electrical Characteristics at Recommended Operating
Conditions (Typical values are at Vee = 3.3 V and fA = 25°C)
TI486SXLC-V25
Parameter
Test Conditions
Min
Typ
0.4
VOL
Low-level output voltage
VOH
High-level output voltage
II
Input current (leakage)
VIN = 0, VIN ~ VCC
See Note 1
IIH
High-level input current at
PEREQ
VIN = 2.4,
See Note 2
See Note 3
10L= 3 rnA
Unit
V
2.4
10H =-1 rnA
V
10H =-0.2 rnA
VCC-O.4
~
IlL
Low-level input current
VIL = 0.45 V,
ICC
Supply current (Active mode)
25 MHz
ICCSM
Supply current (Suspend mode)
25 MHz
See Note 4
6
ICCSS
Standby supply current
oMHz, Suspended/CLK2 stopped,
0.1
CIN
Input capacitance
fc = 1 MHz,
COUT
Output or I/O capacitance
fc = 1 MHz,
CCLK
Input capacitance CLK2
fc = 1 MHz,
Notes:
Max
~
±15
/-LA
200
/-LA
-400
/-LA
285
rnA
225
rnA
1
rnA
See Note 5
10
pF
See Note 5
12
pF
See Note 5
20
pF
See Note 4
1) Applicable for all input terminals except those with an internal pullup resistor. See Table 5-1.
2) PEREa input has an internal pulldown resistor.
3) Applicable for all inputs that have an internal pullup resistor. See Table 5-1.
4) All inputs at 0 or VCC. All inputs held static, (except CLK2 as indicated). All outputs unloaded (static lOUT = 0 rnA).
5) Not 100% tested
Electrical Specifications
5-9
DC Electrical Characteristics
Table 5-10. T1486SXL·V40 Electrical Characteristics at Recommended Operating
Conditions (Typical values are at Vee = 3.3 V and 1A = 25°C)
T1486SXL-V40
Parameter
VOL
Low-level output voltage
VOH
High-level output voltage
Test Conditions
V
V
VCC-O.4
Input current (leakage)
VIN = 0, VIN ~ VCC
See Note 1
IIH
VIN = 2.4,
See Note 2
IlL
Low-level input current
VIL = 0.45 V,
See Note 3
ICC
Supply current (Active mode)
20 MHz (CLK2 = 40 MHz)
Standby supply current
Unit
2.4
10H =-1 mA
High-level input current at
PEREQ
ICCSS
Max
0.4
II
Supply current (Suspend mode)
Typ
10L= 3 mA
10H =-0.2 mA
ICCSM
Min
20 MHz
(CLK2 = 40 MHz)
±15
-;:
300
200
IlA
IlA
-400
IlA
400
mA
~
See Note 4
o MHz, Suspended/CLK2 stopped,
See Note 4
mA
15
0.1
1
mA
CIN
Input capacitance
fc = 1 MHz,
See Note 5
10
pF
COUT
Output or I/O capacitance
fc = 1 MHz,
See Note 5
12
pF
CCLK
Input capacitance CLK2
fc = 1 MHz,
See Note 5
20
pF
Notes:
1) Applicable for all input terminals except those with an internal pullup resistor. See Table 5-1.
2) PEREa has an internal pulldown resistor.
3) Applicable for all inputs that have an internal pullup resistor. See Table 5-1.
4) All inputs at 0 orVcc. All inputs held static, (except CLK2 as indicated). All outputs unloaded (static lOUT = 0 mAl.
5) Not 100% tested
5-10
DC Electrical Characteristics
Table 5-11. T1486SXL2- V50 Electrical Characteristics at Recommended Operating
Conditions (Typical values are at Vee = 3.3 V and 1A = 25°C)
T1486SXL2-V50
Parameter
Test Conditions
VOL
Low-level output voltage
VOH
High-level output voltage
II
Input current (leakage)
VIN = 0, VIN ~ VCC
See Note 1
IIH
High-level input current at
PEREQ
VIN = 2.4,
See Note 2
IlL
Low-level input current
VIL = 0.45 V,
See Note 3
Min
Typ
Max
0.4
10L= 3 rnA
Unit
V
2.4
IOH=-1 rnA
V
IOH =-0.2 rnA
VCC-O.4
ICC
Supply current (Active mode)
25 MHz (CLK2 = 50 MHz)
ICCSM
Supply current (Suspend mode)
25 MHz
(CLK2 = 50 MHz)
ICCSS
Standby supply current
±15
~200
~
o MHz, Suspended/CLK2 stopped,
/lA
500
rnA
365
0.1
See Note 4
/lA
-400
rnA
20
See Note 4
/lA
1
rnA
CIN
Input capacitance
fc = 1 MHz,
See Note 5
10
pF
COUT
Output or 1/0 capacitance
12
pF
CCLK
Input capacitance CLK2
= 1 MHz,
fc = 1 MHz,
See Note 5
See Note 5
20
pF
Notes:
fc
1) Applicable for all input terminals except those with an internal pullup resistor. See Table 5-1.
2) PEREQ has an internal pulldown resistor.
3) Applicable for all inputs that have an internal pullup resistor. See Table 5-1.
4) All inputs at 0 or VCC. All inputs held static, (except CLK2 as indicated). All outputs unloaded (static lOUT = 0 rnA).
5) Not 100% tested
Electrical Specifications
5-11
DC Electrical Characteristics
5.4.3
5-Volt Microprocessors
o
o
o
o
Table
Table
Table
Table
5-12
5-13
5-14
5-15
covers the 5-V 40, 20-MHz TI486SXLC-040.
on page 5-13 covers the 5-V 50, 25-MHz TI486SXLC2-050.
on page 5-14 covers the 5-V 40, 20-MHz TI4868XL-040.
on page 5-15 covers the 5-V 50. 25-MHz TI486SXL2-050.
Table 5-12. TI486SXLC-040 Electrical Characteristics at Recommended Operating
Conditions (Typical values are at Vee = 5 V and TA = 25°C)
Parameter
VOL
Low-level output voltage
VOH
High-level output voltage
II
Input current (leakage)
VIN = 0, VIN ~ VCC
See Note 1
IIH
High-level input current at
PEREQ
VIN = 2.4,
See Note 2
See Note 3
Min
Typ
Max
0.4
10L = 5 mA
V
V
10H =-0.2 mA
VCC-0.5
Low-level input current
VIL = 0.45 V,
ICC
Supply current (Active mode)
20 MHz (CLK2 = 40 MHz)
ICCSM
Supply current (Suspend mode)
20 MHz
(CLK2 = 40 MHz)
ICCSS
Standby supply current
CIN
Input capacitance
COUT
Output or 1/0 capacitance
fc = 1 MHz,
CCLK
Input capacitance CLK2
fc = 1 MHz,
See Note 4
o MHz, Suspended/CLK2 stopped
_'0k~
580
±15
~A
200
~A
-400
~A
725
mA
10
0.1
mA
1
mA
10
pF
See Note 5
12
pF
See Note 5
20
pF
See Note 4
fc = 1 MHz,
Unit
2.4
10H =-1 mA
IlL
Notes:
TI486SXLC - 040
Test Conditions
See Note 5
1) Applicable for all input terminals except those with an internal pullup resistor. See Table 5-1.
2) PEREQ has an internal pulldown resistor.
3) Applicable for all inputs that have an internal pullup resistor. See Table 5-1.
4) All inputs at 0 or VCC. All inputs held static, (except CLK2 as indicated). All outputs unloaded (static lOUT = 0 mA).
5) Not 100% tested
5-12
DC Electrical Characteristics
Table 5-13. T1486SXLC2-050 Electrical Characteristics at Recommended Operating
Conditions (Typical values are at Vee = 5 V and TA = 25°C)
TI486SXLC2 - 050
Parameter
Test Conditions
VOL
Low-level output voltage
VOH
High-level output voltage
II
Input current (leakage)
VIN = 0, VIN ~ VCC
See Note 1
IIH
High-level input current at
PEREQ
VIN = 2.4,
See Note 2
IlL
Low-level input current
VIL = 0.45 V,
See Note 3
ICC
Supply current (Active mode)
25 MHz (CLK2 = 50 MHz)
ICCSM
Supply current (Suspend mode)
25 MHz
(CLK2 = 50 MHz)
ICCSS
Standby supply current
CIN
Input capacitance
fc = 1 MHz,
COUT
Output or I/O capacitance
CCLK
Input capacitance CLK2
Notes:
Min
Typ
Max
0.45
IOL=5 mA
Unit
V
2.4
IOH=-1 mA
V
10H =-0.2 mA
VCC-0.5
~
,
,,:::::;=
±15
/lA
200
/lA
-400
/lA
850
mA
640
9
See Note 4
o MHz, Suspended/CLK2 stopped,
0.1
mA
1
mA
See Note 5
10
pF
fc = 1 MHz,
See Note 5
12
pF
fc = 1 MHz,
See Note 5
20
pF
See Note 4
1) Applicable for all input terminals except those with an internal pullup resistor. See Table 5-1.
2) PEREa has an internal pulldown resistor.
3) Applicable for all inputs that have an internal pullup resistor. See Table 5-1.
4) All inputs at 0.4 or VCC-O.4 (CMOS levels). All inputs held static, (except CLK2 as indicated). All outputs unloaded
(static lOUT = 0 mA).
5) Not 100% tested
Electrical Specifications
5-13
DC Electrical Characteristics
Table 5-14. TI486SXL -040 Electrical Characteristics at Recommended Operating
Conditions (Typical values are at nominal Vee = 5 Vand 1A = 25°C)
T1486SXL-040
Parameter
Test Conditions
Min
Typ
Max
0.45
VOL
Low-level output voltage
VOH
High-level output voltage
II
Input current (leakage)
VIN = 0, VIN ;::: VCC
See Note 1
IIH
High-level input current at
PEREQ
VIN = 2.4,
See Note 2
IlL
Low-level input current
VIL = 0.45 V,
See Note 3
ICC
Supply current (Active mode)
20 MHz (CLK2 = 40 MHz)
ICCSM
Supply current (Suspend mode)
20 MHz
(CLK2 = 40 MHz)
ICCSS
Standby supply current
CIN
Input capacitance
10L= 5 mA
V
10H =-0.2 mA
VCC-0.5
See Note 4
o MHz, Suspended/CLK2 stopped,
~200
±15
600
IlA
IlA
-400
IlA
800
mA
mA
10
1
mA
See Note 5
10
pF
pF
pF
See Note 4
0.1
COUT
Output or 1/0 capacitance
fc = 1 MHz,
See Note 5
12
CCLK
Input capacitance CLK2
fc = 1 MHz,
See Note 5
20
Notes:
V
2.4
10H =-1 mA
fc = 1 MHz,
Unit
1) Applicable for all input terminals except those with an internal pullup resistor. See Table 5-1.
2) PEREQ input has an internal pulldown resistor.
3) Applicable for all inputs that have an internal pullup resistor. See Table 5-1.
4) All inputs at 0 or VCC. All inputs held static, (except CLK2 as indicated). All outputs unloaded (static lOUT = 0 mA).
5) Not 100% tested
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
5-14
DC Electrical Characteristics
Table 5-15. T1486SXL2-050 Electrical Characteristics at Recommended Operating
Conditions (Typical values are at nominal Vee = 5 V and TA = 25°C)
Parameter
T1486SXL2-050
Test Conditions
VOL
Low-level output voltage
VOH
High-level output voltage
II
Input current (leakage)
VIN = 0, VIN ;::: VCC
See Note 1
IIH
High-level input current at
PEREQ
VIN = 2.4,
See Note 2
IlL
Low-level input current
VIL = 0.45 V,
See Note 3
ICC
Supply current (Active mode)
25 MHz (CLK2 = 50 MHz)
ICCSM
Supply current (Suspend mode)
25 MHz
(CLK2 = 50 MHz)
ICCSS
Standby supply current
o MHz, Suspended/CLK2 stopped,
CIN
Input capacitance
fc = 1 MHz,
COUT
Output or 1/0 capacitance
CCLK
Input capacitance CLK2
Min
Max
0.45
10L= 5 mA
Unit
V
2.4
10H =-1 mA
Notes:
Typ
V
10H =-0.2 mA
VCC-0.5
~
±15
JlA
200
JlA
-400
JlA
900
mA
670
10
See Note 4
mA
1
mA
See Note 5
10
pF
fc = 1 MHz,
See Note 5
12
pF
fc = 1 MHz,
See Note 5
20
pF
0.1
See Note 4
1) Applicable for all input terminals except those with an internal pullup resistor. See Table 5-1.
2) PEREQ input has an internal pulldown resistor.
3) Applicable for all inputs that have an internal pullup resistor. See Table 5-1.
4) All inputs at 0 or VCC. All inputs held static, (except CLK2 as indicated). All outputs unloaded (static lOUT = 0 mA).
5) Not 100% tested
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Electrical Specifications
5-1 5
AC Characteristics
5.5 AC Characteristics
The ac characteristics provide detailed information regarding measurement
points, specific timing requirements for setup and hold times, and propagation
delay times of the TI486SXL(C) microprocessors.
5.5.1
Measurement Points for AC Characteristics
The rising-clock-edge reference level VREFC, and other reference levels are
specified in Table 5-16 for the TI486SXL(C) family of microprocessors. Input
or output signals must cross these levels during testing.
Table 5-16. Measurement Points for AC Characteristics
Symbol
TI486SXLC-V and TI486SXL-V
TI486SXLC and TI486SXL
Unit
VREFC
1.5
2
V
VREF
1.2
1.5
V
VIHC
VCC-0.3
VCC-O.B
V
VILC
0.6
O.B
V
VIHD
2.3
3
V
VILD
0
0
V
Figure 5-2 and Figure 5-3 show delays (A and B) and input setup and hold
times (C and D). Input setup and hold times (C and D) are specified minimums,
defining the smallest acceptable sampling window during whic~ a synchronous input signal must be stable for correct operation.
The TI486SXLC microprocessor outputs A23-A 1, ADS#, BHE#, BLE#,
D/C#, HLDA, LOCK#, M/IO#, SMADS#, SMI#, and W/R# change only at the
beginning of phase one (Figure 5-2, <1>1). Outputs D15-DO (write cycles) and
SUSPA# change at the beginning of phase two (<1>2).
The TI486SXLC microprocessor inputs BUSY#, D15-DO (read cycles), ERROR#, FLT#, HOLD, PEREQ, and READY# are sampled at the beginning of
phase one (Figure 5-2, <1>1). Inputs A20M#, FLUSH#, INTR, KEN#, NA#, NMI,
SMI# and SUSP# are sampled at the beginning of phase two (<1>2).
The TI486SXL microprocessor outputs A31-A2, ADS#, BE3#- BEO#, D/C#,
HLDA, LOCK#, M/IO#, SMADS#, SMI#, and W/R# change only at the beginning of phase one (Figure 5-3, <1>1). Outputs D31-DO (write cycles) and SUSPA# change at the beginning of phase two (<1>2).
The TI486SXL microprocessor inputs BUSY#, D31-DO (read cycles), ERROR#, HOLD, PEREQ, and READY# are sampled at the beginning of phase 1
(Figure 5-3, <1>1). Inputs A20M#, BS16, FLUSH#, INTR, KEN#, NA#, NMI,
SMI# and SUSP# are sampled at the beginning of phase two (<1>2).
5-16
AC Characteristics
Figure 5-2. TI486SXLC Drive Level and Measurement Points for AC Characteristics
Tx
I
CLK2:
A23-Al, ADS#
BHE#, BLE#, D/C#,
HLDA, LOCK#,
M/IO#, SMADS#,
SMI#, W/R#
I
<1>2
v~----~-----l-----~----~
0
1411
OUTPUTS:
I
<1>1
~Min
Valid
Output n
~Max
I
I
I
I
:
I
I
VREF
I
I
I
0
~
I
Max
I
I
I
I
OUTPUTS:
Valid
Output n
. D15-DO,
SUSPA#
I
I
I
I
I
I
I
I
I
I
INPUTS:
A20M#,
FLUSH#,
INTR, KEN#,
NA#, NMI, SMI#,
SUSP#
~
.V
REF
Valid
Input
V
_
REF
I
I
I
I
I
~
INPUTS:
BUSY#,
D15-DO,
ERROR#, FLT#,
HOLD, PEREQ,
READY#
LEGEND: A
B
C
D
-
•
Valid
~
Maximum Output Delay Specification
Minimum Output Delay Specification
Minimum Input Setup Specification
Minimum Input Hold Specificaton
Electrical Specifications
5-17
AC Characteristics
Figure 5-3. TI486SXL Drive Level and Measurement Points for AC Characteristics
Tx
I
I
<\>1
<\>2
CLK2:
l-----~_ Max
OUTPUTS:
A31-A2, ADS#
BE3#-BEO#, D/C#,
HLDA, LOCK#,
M/IO#, SMADS#,
SMI#,W/R#
I
Valid
Output n
~------~~-Max
I
OUTPUTS:
Valid
Output n
D31-DO, SUSPA#
I
I
I
I
I
~
INPUTS:
A20M#, BS16,
FLUSH#, INTH,
KEN#, NA#, NMI,
SMI#, SUSP#
•
BUSY#, D31-DO,
ERROR#, HOLD,
PEREQ,READY#
5-18
VREF
Valid
Inpul
_
VRE~
I
I
I
I
I
I
I
I
~
INPUTS:
.EGEND: A
B
C
D
I
I
-
Maximum Output Delay Specification
Minimum Output Delay Specification
Minimum Input Setup Specification
Minimum Input Hold Specificaton
. VREF
Valid
Inpul
V
~
RE~
AC Characteristics
5.5.2
CLK2 Timing Measurement Points
The CLK2 timing measurement points are illustrated in Figure 5-4 for the
TI486SXL(C) family of microprocessors.
Figure 5-4. CLK2 Timing Measurement Points
~
I
~
I
T1
I
I
j4--T2a~
II4--T2b~
CLK2
---VIHC~-----=
-----
vREFC---VILC - -
~ ~T5
I
---:\¥----~=----~~:\~
-------T
Ii+-T3b-+1
I
1
I
~ ~T4
j4--T3a~
5.5.3
AC Data Characteristics Tables
Parametric ac characteristics include output delays, input setup requirements,
input hold requirements, and output float delays are based on the measurement points identified in Figure 5-2 on page 5-17, Figure 5-3 on page 5-18,
and Figure 5-4.
Electrical Specifications
5-19
AC Characteristics
5.5.3.1
AC Data for 3.3-Volt Microprocessors with 5-Volt Tolerant Outputs
o
o
Table 5-17 covers the 3.3-V 40, 20-MHz TI486SXL-G40.
Table 5-18 on page 5-21 covers the 3.3-V 50-MHz TI486SXL2-G50.
Table 5-17. A C Characteristics for TI486SXL -G40, VCC =3 V to 3.6 V,
VCC5 =4.75 V to 5.25 Vor 3 V to 3.6 V, TC,= 0 to 85°C
SYMBOl
PARAMETER
CLK2 clock-doubled frequency range
TI486SXlG40
MIN
MAX
32
40
UNIT
FIGURE
NOTES
MHz
ns
5-4
5-4
5-4
5-4
5-4
5-4
5-4
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
12.5
12.5
17
ns
5-12,5-15
5-12,5-15
5-15
CL = 50 pF
CL = 50 pF
Note 3
3
3
12.5
17
ns
5-12,5-15
5-15
CL = 50 pF
Note 3
AOS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
3
3
12.5
12.5
ns
5-12,5-15
5-12,5-15
CL
CL
T11
T11a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
17
3
3~7
ns
Note 3
Note 3
T12
T12a
T13
031-00 write data, SUSPA# valid delay
031-00 write data hold time
031-00 write data, SUSPA# float delay
~O20
5-15
5-15
ns
5-12,5-13
5-14
5-15
CL = 50 pF,
Note 5
Notes 3,6
T14
HOLA valid delay
17
ns
5-15
CL
T15
T16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
5
2
ns
5-11
5-11
T17
T18
BS16# setup time
BS16# hold time
5
2
ns
5-11
5-11
T19
T20
REAOY# setup time
REAOY# hold time
5
3
ns
5-11
5-11
T21
T22
031-00 read data setup time
031-00 read data hold time
5
3
ns
5-11
5-11
T23
T24
HOLD setup time
HOLD hold time
4
2
ns
5-11
5-11
T25
T26
RESET setup time
RESET hold time
4.5
2
ns
5-4
5-4
Note 5
T27
T27a
T28
T28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
5
5
5
5
ns
5-10
5-10
5-10
5-10
Note 4
Note 4
Note 4
Note 4
T29
T30
PEREO, ERROR#, BUSY# setup time
PEREO, ERROR#, BUSY# hold time
5
3
ns
5-10
5-10
Note 4
Note 4
T31
Clock-doubled PLL lock time
12.5
5
3.25
5
3.25
T1
T2a
T2b
T3a
T3b
T4
T5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
T6
T6a
T7
A31-A2 valid delay
SMI# valid delay
A31-A2 float delay
3
3
3
T8
T9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
T10
T10a
Notes:
5-20
1)
2)
3)
4)
4
4
14.5
20
IlS
= 50 pF
= 50 pF
= 50 pF
Note 7
Input clock can be stopped, therefore minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are guaranteed by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These following inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for
testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested.
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold-acknowledge state.
7) Delay time from setting CKO in CCRO to entering clock-doubled mode.
AC Characteristics
Table 5-18. AC Characteristics for TI486SXL2-G50, Vee = 3 V to 3.6 V,
VCC5 = 4.75 Vto 5.25 Vor3 Vto 3.6 V, Tc = 0 to 85°C
SYMBOL
PARAMETER
CLK2 clock-doubled
frequency range
T1
T2a
T2b
T3a
T3b
T4
T5
CLK2
CLK2
CLK2
CLK2
CLK2
CLK2
CLK2
period
high time
high time
low time
low time
fall time
rise time
T6
T6a
T7
A31-A2 valid delay
SMI# valid delay
A31-A2 float delay
T8
T9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
T10
T10a
AOS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
T11
T11a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
T12
T12a
T13
031-00 write data, SUSPA# valid delay
031-00 write data hold time
031-00 write data, SUSPA# float delay
T14
HOLA valid delay
T15
T16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
T17
T18
T1486SXL2-G50
MIN
MAX
32
50
20
7
4
7
5
UNIT
FIGURE
NOTES
MHz
ns
5-4
5-4
5-4
5-4
5-4
5-4
5-4
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
7
7
3
3
4
21
30
30
ns
5-12,5-15
5-12,5-15
5-15
CL = 50 pF
CL = 50 pF
Note 3
2.5
4
18
30
ns
5-12,5-15
5-15
CL = 50 pF
Note 3
ns
5-12,5-15
5-12,5-15
CL = 50 pF
CL = 50 pF
ns
5-15
5-15
Note 3
Note 3
ns
5-12,5-13
5-14
5-15
CL = 50 pF,
Note 5
Notes 3,6
ns
5-15
CL
5
3.5
ns
5-11
5-11
BS16# setup time
BS16# hold time
7
2
ns
5-11
5-11
T19
T20
REAOY# setup time
REAOY# hold time
9
4
ns
5-11
5-11
T21
T22
031-00 read data setup time
031-00 read data hold time
7
5
ns
5-11
5-11
T23
T24
HOLO setup time
HOLO hold time
9
3.5
ns
5-11
5-11
T25
T26
RESET setup time
RESET hold time
8
3
ns
5-4
5-4
Note 5
T27
T27a
T28
T28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
6
6
6
6
ns
5-10
5-10
5-10
5-10
Note 4
Note 4
Note 4
Note 4
T29
T30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
6
5
ns
5-10
5-10
Note 4
Note 4
T31
Clock-doubled PLL lock time
Notes:
~
30
30
~
27
2
4
22
2
22
20
Ils
= 50 pF
Note 7
1)
2)
3)
4)
Input clock can be stopped, therefore minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are guaranteed by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These following inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for
testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested.
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold-acknowledge state.
7) Oelay time from setting CKO in CCRO to entering clock-doubled mode.
Electrical Specifications
5-21
AC Characteristics
5.5.3.2 AC Data for 3.3-Volt Microprocessors
o
o
o
Table 5-19 covers the 3.3-V 25-MHz TI486SXLC-V25.
Table 5-20 on page 5-23 covers the 3.3-V 40, 20 MHz TI486SXL-V40.
Table 5-21 on page 5-24 covers the 3.3-V 50 MHZ TI486SXL2-050.
Table 5-19. AC Characteristics for TI486SXLC-V25, Vee = 3 V to 3.6 V
Te = O°C to 85°C
SYMBOl
PARAMETER
T1
T2a
T2b
T3a
T3b
T4
T5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
T6
T6a
T7
A23-A 1 valid delay
SMI# valid delay
A23-A 1 float delay
T8
T9
BHE#, BLE#, LOCK# valid delay
BHE#, BLE#, LOCK# float delay
T10
T10a
AOS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
T11
T11a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
T12
T12a
T13
015-00 write data, SUSPA# valid delay
015-00 write data hold time
015-00 write data, SUSPA# float delay
T14
HOLA valid delay
T15
T16
NA#, SUSP#, FLUSH#, KEN#, A20M# setup time
NA#, SUSP#, FLUSH#, KEN#, A20M# hold time
T19
T20
T1486SXlC-V25
MIN
MAX
20
7
4
7
5
UNIT
FIGURE
NOTES
ns
5-4
5-4
5-4
5-4
5-4
5-4
5-4
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
7
7
3
3
4
21
30
30
ns
5-7,5-10
5-7,5-10
5-10
CL = 50 pF
CL = 50 pF
Note 3
2.5
4
18
30
ns
5-7,5-10
5-10
CL = 50 pF
Note 3
4
4
19
19
ns
5-7,5-10
5-7,5-10
CL
CL
ns
5-10
5-10
Note 3
Note 3
ns
5-7,5-8
5-9
5-10
CL = 50 pF,
Note 5
Notes 3, 6
CL = 50 pF
Jf!
27
22
ns
5-10
5
3.5
ns
5-6
5-6
REAOY# setup time
REAOY# hold time
9
4
ns
5-6
5-6
T21
T22
015-00 read data setup time
015-00 read data hold time
7
5
ns
5-6
5-6
T23
T24
HOLO setup time
HOLO hold time
9
3.5
ns
5-6
5-6
T25
T26
RESET setup time
RESET hold time
8
3
ns
5-5
5-5
Note 5
T27
T27a
T28
T28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
6
6
6
6
ns
5-6
5-6
5-6
5-6
Note 4
Note 4
Note 4
Note 4
T29
T30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
6
5
ns
5-6
5-6
Note 4
Note 4
Notes:
1)
2)
3)
4)
22
Input clock can be stopped, therefore minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are guaranteed by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested.
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold acknowledge state.
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
5-22
2
= 50 pF
= 50 pF
AC Characteristics
Table 5-20. AC Characteristics for TI486SXL-V40, Vee =3 V to 3.6 V,
Te = 0 to 85°C
SYM·
BOl
PARAMETER
CLK2 clock-doubled frequency range
T1486SXl·V40
MIN
MAX
32
40
UNIT
FIGURE
NOTES
MHz
ns
5-4
5-4
5-4
5-4
5-4
5-4
5-4
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
12.5
12.5
17
ns
5-12,5-15
5-12,5-15
5-15
CL = 50 pF
CL = 50 pF
Note 3
3
3
12.5
17
ns
5-12,5-15
5-15
CL = 50 pF
Note 3
AOS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
3
3
12.5
12.5
ns
5-12,5-15
5-12,5-15
CL
CL
T11
T11a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
3
3
17
17,
ns
5-15
5-15
Note 3
Note 3
T12
T12a
T13
031-00 write data, SUSPA# valid delay
031-00 write data hold time
031-00 write data, SUSPA# float delay
~.
ns
5-12,5-13
5-14
5-15
CL = 50 pF,
NoteS
Notes 3,6
T14
HOLA valid delay
ns
5-15
CL
ns
5-11
5-11
T1
T2a
T2b
T3a
T3b
T4
T5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
T6
T6a
T7
A31-A2 valid delay
SMI# valid delay
A31-A2 float delay
3
3
3
T8
T9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
T10
T10a
12.5
5
3.25
5
3.25
4
4
2
4.5
17
= 50 pF
= 50 pF
= 50 pF
T15
T16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
"g
T17
T18
BS16# setup time
BS16# hold time
5
2
ns
5-11
5-11
T19
T20
REAOY# setup time
REAOY# hold time
5
3
ns
5-11
5-11
T21
T22
031-00 read data setup time
031-00 read data hold time
5
3
ns
5-11
5-11
T23
T24
HOLD setup time
HOLD hold time
4
2
ns
5-11
5-11
T25
T26
RESET setup time
RESET hold time
4.5
2
ns
5-4
5-4
NoteS
T27
T27a
T28
T28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
5
5
5
5
ns
5-10
5-10
5-10
5-10
Note 4
Note 4
Note 4
Note 4
T29
T30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
5
3
ns
5-10
5-10
Note 4
Note 4
T31
Clock-doubled PLL lock time
Notes:
2
20
I-ts
Note 7
Input clock can be stopped, therefore minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are guaranteed by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These following inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for
testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested.
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold-acknowledge state.
7) Delay time from setting CKO in CCRO to entering clock-doubled mode.
1)
2)
3)
4)
Electrical Specifications
5-23
AC Characteristics
Table 5-21. AC Characteristics for TI486SXL2-V50, Vee = 3 V to. 3.6 V,
Te = 0 to 85°C
SYMBOL
PARAMETER
T1486SXL2-V50
MIN
MAX
50
CLK2 clock-doubled frequency range
32
T1
T2a
T2b
T3a
T3b
T4
T5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
20
7
4
7
5
T6
T6a
T7
A31-A2 valid delay
SMI# valid delay
A31-A2 float delay
T8
T9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
T10
T10a
AOS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
T11
T11a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
T12
T12a
T13
031-00 write data, SUSPA# valid delay
031-00 write data hold time
031-00 write data, SUSPA# float delay
T14
HOLA valid delay
T15
T16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
T17
T18
UNIT
FIGURE
NOTES
MHz
ns
5-4
5-4
5-4
5-4
5-4
5-4
5-4
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
7
7
3
3
4
21
30
30
ns
5-12,5-15
5-12,5-15
5-15
CL = 50 pF
CL = 50 pF
Note 3
2.5
4
18
30
ns
5-12,5-15
5-15
CL = 50 pF
Note 3
$~O~
ns
5-12,5-15
5-12,5-15
CL = 50 pF
CL = 50 pF
30
ns
5-15
5-15
Note 3
Note 3
ns
5-12,5-13
5-14
5-15
CL = 50 pF,
Note 5
Notes 3,6
CL = 50 pF
«'30
4
4
19
27
4
22
2
22
ns
5-15
5
3.5
ns
5-11
-5-11
BS16# setup time
BS16# hold time
7
2
ns
5-11
5-11
T19
T20
REAOY# setup time
REAOY# hold time
9
4
ns
5-11
5-11
T21
T22
031-00 read data setup time
031-00 read data hold time
7
5
ns
5-11
5-11
T23
T24
HOLO setup time
HOLO hold time
9
3.5
ns
5-11
5-11
T25
T26
RESET setup time
RESET hold time
8
3
ns
5-4
5-4
Note 5
T27
T27a
T28
T28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
6
6
6
6
ns
5-10
5-10
5-10
5-10
Note 4
Note 4
Note 4
Note 4
T29
T30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
6
5
ns
5-10
5-10
Note 4
Note 4
T31
Clock-doubled PLL lock time
Notes:
5-24
1)
2)
3)
4)
20
Ils
Note 7
Input clock can be stopped, therefore minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are guaranteed by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These following inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for
testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested.
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold-acknowledge state.
7) Oelay time from setting CKO in CCRO to entering clock-doubled mode.
AC Characteristics
5.5.3.3
AC Data for 5-Volt Microprocessors
o
o
o
o
Table
Table
Table
Table
5-22
5-23
5-24
5-25
covers the 5-V 40,20 MHz TI486SXLC-040.
on page 5-26 covers the 5-V 50 MHz TI486SXLC2-050.
on page 5-27 covers the 5-V 40,20 MHz TI486SXL-040.
on page 5-28 covers the 5-V 50 MHz T1486SXL2-050
Table 5-22. AC Characteristics for TI486SXLC-040, Vee = 4.75 V to 5.25 \I,
Te = 0 to 100°C
TI486SXLC-040
SYMBOL
PARAMETER
CLK2 clock-doubled frequency range
MIN
MAX
32
40
T1
T2a
T2b
T3a
T3b
T4
T5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
T6
T6a
T7
A23-A 1 valid delay
SM 1# valid delay
A23-A 1 float delay
3
3
3
T8
T9
BHE#, BLE#, LOCK# valid delay
BHE#, BLE#, LOCK# float delay
T10
T10a
FIGURE
NOTES
MHz
ns
5-4
5-4
5-4
5-4
5-4
5-4
5-4
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
12.5
12.5
17
ns
5-7,5-10
5-7,5-10
5-10
CL = 50 pF
CL = 50 pF
Note 3
3
3
12.5
17
ns
5-7,5-10
5-10
CL = 50 pF
Note 3
AOS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
3
3
12.
ns
5-7,5-10
5-7,5-10
CL
CL
T11
T11a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
3
ns
5-10
5-10
Note 3
Note 3
T12
T12a
T13
015-00 write data, SUSPA# valid delay
015-00 write data hold time
015-00 write data, SUSPA# float delay
ns
3
14.5
5-7,5-8
5-9
5-10
CL = 50 pF,
Note 5
Notes 3,6
T14
HOLA valid delay
3
17
ns
5-10
CL
T15
T16
NA#, SUSP#, FLUSH#, KEN#, A20M# setup time
NA#, SUSP#, FLUSH#, KEN#, A20M# hold time
5
2
ns
5-6
5-6
T19
T20
REAOY# setup time
REAOY# hold time
5
3
ns
5-6
5-6
T21
T22
015-00 read data setup time
015-00 read data hold time
5
3
ns
5-6
5-6
T23
T24
HOLD setup time
HOLD hold time
4
2
ns
5-6
5-6
T25
T26
RESET setup time
RESET hold time
4.5
2
ns
5-5
5-5
Note 5
T27
T27a
T28
T28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
5
5
5
5
ns
5-6
5-6
5-6
5-6
Note
Note
Note
Note
T29
T30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
5
3
ns
5-6
5-6
Note 4
Note 4
T31
Clock-doubled PLL lock time
Notes:
12.5
5
3.25
5
3.25
UNIT
4
4
17
17
20
20
(ls
= 50 pF
= 50 pF
= 50 pF
4
4
4
4
Note 7
1)
2)
3)
4)
Input clock can be stopped, therefore minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are guaranteed by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested.
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold acknowledge state.
7) Delay time from setting CKO in CCRO to entering clock-doubled mode.
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Electrical Specifications
5-25
AC Characteristics
Table 5-23. AC Characteristics for TI486SXLC2-050, Vee
Te = 0 to 100°C
SYMBOL
PARAMETER
= 4.75 V to 5.25 V
T1486SXLC2-050
MIN
MAX
CLK2 clock-doubled frequency range
32
50
T1
T2a
T2b
T3a
T3b
T4
T5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
20
7
4
7
5
T6
T6a
T7
A23-A 1 valid delay
SMI# valid delay
A23-A 1 float delay
4
4
4
T8
T9
BHE#, BLE#, LOCK# valid delay
BHE#, BLE#, LOCK# float delay
T10
T10a
UNIT
FIGURE
NOTES
MHz
ns
5-4
5-4
5-4
5-4
5-4
5-4
5-4
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
21
30
30
ns
5-7,5-10
5-7,5-10
5-10
CL = 50 pF
CL = 50 pF
Note 3
4
4
21
30
ns
5-7,5-10
5-10
CL = 50 pF
Note 3
AOS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
4
4
21
ns
5-7,5-10
5-7,5-10
CL
CL
T11
T11a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
4
0
30
ns
5-10
5-10
Note 3
Note 3
T12
T12a
T13
015-00 write data, SUSPA# valid delay
015-00 write data hold time
015-00 write data, SUSPA# float delay
ns
4
22
5-7,5-8
5-9
5-10
CL = 50 pF,
Note 5
Notes 3,6
T14
HOLA valid delay
4
22
ns
5-10
CL = 50 pF
T15
T16
NA#, SUSP#, FLUSH#, KEN#, A20M# setup time
NA#, SUSP#, FLUSH#, KEN#, A20M# hold time
5
3
ns
5-6
5-6
T19
T20
REAOY# setup time
REAOY# hold time
9
4
ns
5-6
5-6
T21
T22
015-00 read data setup time
015-00 read data hold time
7
5
ns
5-6
5-6
T23
T24
HOLD setup time
HOLD hold time
9
3
ns
5-6
5-6
T25
T26
RESET setup time
RESET hold time
8
3
ns
5-5
5-5
Note 5
T27
T27a
T28
T28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
6
6
6
6
ns
5-6
5-6
5-6
5-6
Note 4
Note 4
Note 4
Note 4
T29
T30
PEREa, ERROR#, BUSY# setup time
PEREa, ERROR#, BUSY# hold time
6
5
ns
5-6
5-6
Note 4
Note 4
T31
Clock-doubled PLL lock time
Notes:
5-26
1)
2)
3)
4)
7
7
27
20
J-ts
= 50 pF
= 50 pF
Note 7
Input clock can be stopped, therefore minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are guaranteed by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested.
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold acknowledge state.
'
7) Delay time from setting CKO in CCRO to entering clock-doubled mode.
AC Characteristics
Table 5-24. AC Characteristics for TI486SXL -040, Vee =4.75 V to 5.25 V,
(for Te see Table 5-6)
SYMBOl
PARAMETER
CLK2 clock-doubled frequency range
T1486SXl-040
MIN
MAX
32
40
UNIT
FIGURE
NOTES
MHz
ns
5-4
5-4
5-4
5-4
5-4
5-4
5-4
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
12.5
12.5
17
ns
5-12,5-15
5-12,5-15
5-15
CL = 50 pF
CL = 50 pF
Note 3
3
3
12.5
17
ns
5-12,5-15
5-15
CL = 50 pF
Note 3
AOS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
3
3
12.5
12.5
ns
5-12,5-15
5-12,5-15
CL = 50 pF
CL = 50 pF
T11
T11a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
3
3
17
ns
5-15
5-15
Note 3
Note 3
T12
T12a
T13
031-00 write data, SUSPA# valid delay
031-00 write data hold time
031-00 write data, SUSPA# float delay
ns
5-12,5-13
5-14
5-15
CL = 50 pF,
Note 5
Notes 3,6
ns
5-15
CL
ns
5-11
5-11
T1
T2a
T2b
T3a
T3b
T4
T5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
12.5
5
3.25
5
3.25
T6
T6a
T7
A31-A2 valid delay
SMI# valid delay
A31-A2 float delay
3
3
3
T8
T9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
T10
T10a
4
4
11
~
2
14.5
=~
= 50 pF
T14
HOLA valid delay
T15
T16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
T17
T18
BS16# setup time
BS16# hold time
5
2
ns
5-11
5-11
T19
T20
REAOY# setup time
REAOY# hold time
5
3
ns
5-11
5-11
T21
T22
031-00 read data setup time
031-00 read data hold time
5
3
ns
5-11
5-11
T23
T24
HOLO setup time
HOLO hold time
4
2
ns
5-11
5-11
T25
T26
RESET setup time
RESET hold time
4.5
2
ns
5-4
5-4
Note 5
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
17
'~·5
2
T27
T27a
T28
T28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
5
5
5
5
ns
5-10
5-10
5-10
5-10
T29
T30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
5
3
ns
5-10
5-10
T31
Clock-doubled PLL lock time
Notes:
20
!lS
Note 7
1)
2)
3)
4)
Input clock can be stopped, therefore minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are guaranteed by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These following inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for
testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested.
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold-acknowledge state.
7) Oelay time from setting CKO in CCRO to entering clock-doubled mode.
Electrical Specifications
5-27
AC Characteristics
Table 5-25. AC Characteristics for TI486SXL2-050, Vee = 4.75 V to 5.25 V,
(for Te see Table 5-6)
PARAMETER
SYMBOL
T1486SXL2-050
MIN
MAX
CLK2 clock-doubled frequency range
32
50
T1
T2a
T2b
T3a
T3b
T4
T5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
20
7
4
7
5
T6
T6a
T7
A31-A2 valid delay
SMI# valid delay
A31-A2 float delay
T8
T9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
T10
T10a
AOS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
T11
T11a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
T12
T12a
T13
031-00 write data, SUSPA# valid delay
031-00 write data hold time
031-00 write data, SUSPA# float delay
UNIT
FIGURE
NOTES
MHz
ns
5-4
5-4
5-4
5-4
5-4
5-4
5-4
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
7
7
3
3
4
21
30
30
ns
5-12,5-15
5-12,5-15
5-15
CL = 50 pF
CL = 50 pF
Note 3
2.5
4
18
30
ns
5-12,5-15
5-15
CL = 50 pF
Note 3
4
4
.~~o~~
ns
5-12,5-15
5-12,5-15
CL = 50 pF
CL = 50 pF
ns
5-15
5-15
Note 3
Note 3
ns
5-12,5-13
5-14
5-15
CL = 50 pF,
Note 5
Notes 3,6
CL = 50 pF
19
1f'30
30
27
4
22
2
22
ns
5-15
5
3.5
ns
5-11
5-11
BS16# setup time
BS16# hold time
7
2
ns
5-11
5-11
T19
T20
REAOY# setup time
REAOY# hold time
9
4
ns
5-11
5-11
T21
T22
031-00 read data setup time
031-00 read data hold time
7
5
ns
5-11
5-11
T23
T24
HOLD setup time
HOLD hold time
9
3.5
ns
5-11
5-11
T25
T26
RESET setup time
RESET hold time
8
3
ns
5-4
5-4
Note 5
T27
T27a
T28
T28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
6
6
6
ns
6
5-10
5-10
5-10
5-10
Note 4
Note 4
Note 4
Note 4
T29
T30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
6
5
ns
5-10
5-10
Note 4
Note 4
T31
Clock-doubled PLL lock time
T14
HOLA valid delay
T15
T16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
T17
T18
Notes:
5-28
1)
2)
3)
4)
20
I-ls
Note 7
Input clock can be stopped, therefore minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are guaranteed by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These following inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for
testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested.
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold-acknowledge state.
7) Delay time from setting CKO in CCRO to entering clock-doubled mode.
AC Characteristics
5.5.4
RESET Setup and Hold Timing
RESET setup and hold timing for the TI486SXL(C) family of microprocessors
are illustrated in Figure 5-5.
Figure 5-5. RESET Setup and Hold Timing
CLK2
.,
I
I
I
I
I
.,(
j
RESET
~
T25
~
()~
T26~
5.5.5
TI486SXLC Switching Waveforms
Switching waveforms for the TI486SXLC microprocessors are illustrated in
Figure 5-6, Figure 5-7, Figure 5-8, Figure 5-9, and Figure 5-10 on pages
5-29 through 5-31.
Figure 5-6. TI486SXLC Input Signal Setup and Hold Timing
<1>2
<1>1
<1>2
<1>1
CLK2
'---...II
READY#
~ ---~:~-::: ~
HOLD_
:::
..
X%.
I+-T21-......-
D1S-DOR
PEREQ,ERROR#,~
I + - T29
BUSY#
:~
T30
rI////////IX.
~~~~~--------~------~~~~~
~
NA#, SUSP#,
FLUSH#, KEN#,
A20M#
----.lX%.
~
T1S
~
-
T16----.1
NMI, INTR, SMI#
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Electrical Specfications
5-29
AC Characteristics
Figure 5-7. TI486SXLC Output Signal Valid Delay Timing
<1>1
<1>2
<1>1
<1>2
CLK2
T8
Valid n+1
BHE#,
BLE#
LOCK#
T10,T10a
AOS#,O/C#, M/IO#,
SMAOS#, W/R#
Valid n+1
T6,T6a
Valid n+1
A23-A1, SMI#
SUSPA#
Figure 5-8. TI486SXLC Data Write Cycle Valid Delay Timing
<1>1
CLK2
'------' I
I
I
I
I
W/R#
T12
015-00
~
I
.: Min
I
~ Max
-----------~~
I
Valid
I~------~~~------------
I
5-30
I
AC Characteristics
Figure 5-9. TI486SXLC Data Write Cycle Hold Timing
1
CLK2
I
I
-.-1
I
k\~--------~-----------------------~dn+1
W/R#
I
T12a
015-00
I
I Min
Valid n
Valid n+1
Figure 5-10. TI486SXLC Output Signal Float Delay and HLDA Valid
Delay Timing
Ti or T1
Th
2
1
CLK2
I
2
1
I
I
2
BHE#, BLE#,
LOCK#
T11,T11a
AOS#,O/C#,
\I1/10#,SMAOS#,
W/R#
A23-A1
015-00 (Write
Data), SUSPA#
T14
HLOA
Electrical Specifications
5-31
AC Characteristics
5.5.6
TI486SXL Switching Waveforms
Switching waveforms for the TI486SXL microprocessors are illustrated in
Figure 5-11, Figure 5-12, Figure 5-13, Figure 5-14, and Figure 5-15 on
pages 5-32 through 5-34.
Figure 5-11. TI486SXL Input Signal Setup and Hold Timing
1
2
CLK2
--- I
'---.I
~ T19 ---~Ie---T20 ~
REAOY#.
HOLO.
~
:
I
I
~ T23-.....-411--
~T21
T22~~
~
031-00.
PEREQ,ERROR#,
~~ T29
:
T30
~~.
BUSY#~~
~~~~------------------~~~~
I
~
NA#, SUSP#,
FLUSH#, KEN#,
NENW#, A20M#
BS16
NMI, INTR, SMI#
5-32
T15,T32
~
T16,T33
~
AC Characteristics
Figure 5-12. TI486SXL Output Signal Valid Delay Timing
<1>2
<1>1
CLK2
T8----~--------~~
Valid n+1
BE3#-BEO#
LOCK#
T10
ADS#, D/C#,
M/IO#, SMADS#,
W/R#
Valid n+1
T6,T6a
Valid n+1
A31-A2, SMI#
SUSPA#
Valid n
Figure 5-13. TI486SXL Data Write Cycle Valid Delay Timing
<1>1
<1>1
<1>2
CLK2
'------' I
I
I
W/R#
I
I
/
--.J
T12
D31-DO
I
I
r~
Min
~ Max
-----------r-_""''''''"'~~---v-a-lid---
Electrical Specifications
5-33
AC Characteristics
Figure 5-14. TI486SXL Data Write Cycle Hold Timing
<1>1
<1>1
<1>2
CLK2
I
I
K
W/R#
---'I
I
:
1-.
Valid n+1
I ~--------~--------------------T12a~M'
031-00
Valid n
Valid n+1
Figure 5-15. TI486SXL Output Signal Float Delay and HLDA Valid Delay Timing
I
I
I
<1>2
CLK2
BE3#-BEO#,
LOCK#
T11,T11a
AOS#,O/C#,
M/IO#, SMAOS#,
W/R#
A31-A2
031-00
(Write Oata),
SUSPA#
T14
HLOA
5-34
I
I
Th
<1>1
I
<1>2
I
Ti or T1
<1>1
I
I
<1>2
Chapter 6
Mechanical Specifications
Mechanical specifications include pin assignments, package dimensions, and
thermal characteristics for each of the TI486SXL( C) microprocessors.
The TI486SXL( C) microprocessors are supplied in the following packages:
o
o
o
o
o
100-pin, thermally enhanced plastic quad flat package
132-pin, ceramic pin grid array package
144-pin, thermally enhanced plastic quad flat package
144-pin, ceramic quad flat package
168-pin, ceramic pin grid array package
Pin assignments provide both a pin locator drawing and two pin listings. One
pin listing is alphabetically by pin name and the other is (alpha)numerically by
pin number.
A pinout cross-reference, comparing industry-standard 486SX pinouts, is supplied for the 168-pin package at the end of the pin-assignment data.
Industry-standard dimensioned drawings are supplied for each package.
Thermal characteristics are supplied on each package that includes airflow
measurement setup data for correlation purposes.
Topic
6.1
Page
Pin"AsSlgnments... ••• ...........
" " , , ' '"'''H'''
6.2
"
. •.. ~~. ~ .. ~ ....••. 'c"
••••
,6..2
"/i":oc,
P,ckage:DimensiCjFls",,;,
....
~~ .~
•. ; ....... ~,; ~ ..• , ....'.; .• 6-13
6.3: ••:rl'lermaiChara~terisfic~,. ~ , •••. ~ ~.' • ,.a •• ,on
.!O • ••••••
~•••,
• • • , • • • '• •
6-18
6-1
Terminal Assignments
6.1
Terminal Assignments
The terminal assignments for the TI486SXLC microprocessors are shown in
Figure 6-1. The signal names are shown in Table 6-1 sorted by terminal numbers and in Table 6-2 sorted by signal names.
Figure 6-1. TI486SXLC Terminal Assignments
gmro~~~~~N~omro~~~~~N~omro~~
~mmmmmmmmmmrorororororororororo~~~~
DO
Vss
HLDA
HOLD
Vss
NA#
READY#
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
CLK2
ADS#
BLE#
A1
BHE#
SMADS#
Vcc
VSS
M/IO#
D/C#
W/R#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
0
Terminal # 1 Index Mark
(On Top Side)
,
(Top View)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A20
A19
A18
A17
Vcc
Vcc
VSS
VSS
A16
A15
A14
A13
VSS
A12
A11
A10
A9
A8
Vcc
A7
A6
A5
A4
A3
A2
~~romo~N~~~~~romo~N~~~~~romo
NNNN~~~~~~~~~~~~~~~~~~~~~
NC -
Make no external connection
Note:
NC Terminals
Connecting or terminating (high or low) any NC terminal(s) may cause unpredictable results or nonperformance of the microprocessor.
6-2
Terminal Assignments
Table 6-1. TI486SXLC Signal Names Sorted by Terminal Number
Term.
No.
Signal
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
00
Vss
HLOA
HaLO
Vss
NA#
REAOY#
VCC
Vec
Vec
Vss
Vss
Vss
Vss
eLK2
AOS#
BLE#
A1
BHE#
SMAOS#
Term.
No.
Signal
Name
Term.
No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Vee
Vss
M/IO#
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
O/C#
W/R#
LOCK#
NC
FLT#
KEN#
FLUSH#
A20M#
Vce
RESET
BUSY#
Vss
ERROR#
PEREa
NMI
Vec
INTR
Signal
Name
Vss
Vee
susP#
SUSPA#
NC
NC
SMI#
VCC
Vss
Vss
A2
A3
A4
A5
A6
A7
Vee
A8
A9
A10
Term.
No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Signal
Name
A11
A12
Vss
A13
A14
A15
Vss
Vss
Vee
A16
Vee
A17
A18
A19
A20
A21
Vss
Vss
A22
A23
Term.
No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Signal
Name
015
014
013
Vcc
Vss
012
011
010
09
08
Vce
07
06
05
04
03
Vec
Vss
02
01
Table 6-2. TI486SXLC Terminal Numbers Sorted by Signal Name
Signal
Name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
Term.
No.
Signal
Name
Term.
No.
18
51
52
53
54
55
56
58
59
60
61
62
64
65
66
70
72
73
74
75
A21
A22
A23
AOS#
A20M#
BHE#
BLE#
BUSY#
CLK2
00
01
02
03
04
05
06
07
08
09
010
76
79
80
16
31
19
17
34
15
1
100
99
96
95
94
93
92
90
89
88
Signal
Name
011
012
013
014
015
O/C#
ERROR#
FLT#
FLUSH#
HaLO
HLOA
INTR
KEN#
LOCK#
M/IO#
NA#
NMI
Ne
NC
NC
Term.
No.
87
86
83
82
81
24
36
28
30
4
3
40
29
26
23
6
38
27
45
46
Signal
Name
PEREQ
REAOY#
RESET
SMAOS#
SMI#
SUSP#
SUSPA#
Vcc
Vcc
Vce
Vee
Vcc
Vce
Vcc
Vcc
Vec
Vce
Vee
Vcc
Vce
Term.
No.
37
7
33
20
47
43
44
8
9
10
21
32
39
42
48
57
69
71
84
91
Signal
Name
Vcc
Vss
Vss
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W/R#
Term.
No.
97
2
5
11
12
13
14
22
35
41
49
50
63
67
68
77
78
85
98
25
Ne - Make no external connection
Note:
NC Terminals
Connecting or terminating (high or low) any NC terminal(s) may cause unpredictable results or nonperformance of the microprocessor.
Mechanical Specifications
6-3
Terminal Assignments
The terminal assignments for the 132-pin PGA TI486SXL microprocessors
are shown as viewed from the terminal side (bottom) in Figure 6-2 and as
viewed from the top side (component side when mounted on a PC board) in
Figure 6-3. The signal names are listed in Table 6-3 and Table 6-4 sorted by
terminal number and signal name respectively.
Figure 6-2. 132-Pin PGA TI486SXL Package Terminals (Bottom View)
Terminal # 1 Index Mark
(On Top Side)
BCD
1
2
3
4
5
6
7
8
9
10
11
12
13
E
F
G
H
J
K
L
M
N
p
\G8G88GGGGGGGGG
80GGG8G888GGGG
G88GGGG8GGGGGG
88G
8800
GGG
888
GGG
8G8
88G
888
GGG
888
GGG
888
888
GGG
888
888
TI486SXL
(Bottom View)
88888888888888
88888888988988
14
888889GGGGG8GG
NC -
Make no external connection
6-4
Terminal Assignments
Figure 6-3. 132-Pin PGA TI486SXL Package Terminals (Top View)
p
N
M
L
K
J
H
G
Terminal # 1 Index Mark
(On Top Side)
FED
C
B
GG8GGGG88GG8G
888GG8G88G888G
88888888888888
888
888
888
88G
888
eGG
888
88G
888
888
888
8SG
888
88G
888
8G8
8888888G888888
88888888888888
TI486SXL
(Top View)
GG8GGGGGG888GG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC - Make no external connection
Note:
NC Terminals
Connecting or terminating (high or low) any NC terminal(s) may cause unpredictable results or nonperformance of the microprocessor.
Mechanical Specifications
6-5
Terminal Assignments
Table 6-3. 132-Pin PGA TI486SXL Signal Names Sorted by Terminal Number
Term.
No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
81
B2
83
84
B5
86
87
88
Signal
Name
Term.
No.
B9
810
811
812
813
814
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
01
02
VCC
VSS
A3
SUSP#
VCC
VSS
VCC
ERROR#
VSS
VCC
O/C#
M/IO#
BE3#
VCC
VSS
A5
A4
SUSPA#
VSS
NC
INTR
NMI
Signal
Name
Term.
No.
BUSY#
03
012
013
014
E1
E2
E3
E12
E13
E14
F1
F2
F3
F12
F13
F14
G1
G2
G3
G12
G13
G14
W/R#
VSS
KEN#
8E2#
VSS
A8
A7
A6
A2
VCC
SMAOS#
SMI#
PEREQ
RESET
LOCK#
VSS
VCC
BE1#
8S16#
A11
A10
Signal
Name
Term.
No.
A9
VCC
NA#
HOLO
A14
A13
A12
8EO#
FLUSH#
AOS#
A15
VSS
VSS
CLK2
A20M#
VSS
A16
VCC
VCC
VCC
REAOY#
VCC
H1
H2
H3
H12
H13
H14
J1
J2
J3
J12
J13
J14
K1
K2
K3
K12
K13
K14
L1
L2
L3
L12
Signal
Name
A17
A18
A19
00
01
02
A20
VSS
VSS
VSS
VSS
03
A21
A22
A25
07
05
04
A23
A24
A28
VCC
Term.
No.
Signal
Name
Term.
No.
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
N2
N3
N4
N5
N6
08
06
A26
A29
VCC
VSS
031
028
VCC
VSS
020
VSS
015
010
VCC
HLOA
A27
A31
VSS
VCC
027
025
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Signal
Name
VCC
023
021
017
016
012
011
09
A30
VCC
030
029
026
VSS
024
VCC
022
019
018
014
013
VSS
Table 6-4. 132-Pin PGA TI486SXL Terminal Numbers Sorted by Signal Name
Signal
Name
Term.
No.
Signal
Name
Term.
No.
Signal
Name
Term.
No.
Signal
Name
Term.
No.
Signal
Name
Term.
No.
Signal
Name
Term.
No.
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A20M#
A21
A22
C4
A3
83
82
C3
C2
C1
03
02
01
E3
E2
E1
F1
G1
H1
H2
H3
J1
F13
K1
K2
A23
A24
A25
A26
A27
A28
A29
A30
A31
AOS#
8EO#
BE1#
8E2#
8E3#
8S16#
BUSY#
CLK2
L1
L2
K3
M1
N1
L3
M2
P1
N2
E14
E12
C13
B13
A13
C14
89
F12
A11
H12
H13
H14
J14
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
K14
K13
L14
K12
L13
N14
M12
N13
N12
P13
P12
M11
N11
N10
P11
P10
M9
N9
P9
N8
P7
N6
026
027
028
029
030
031
ERROR#
FLUSH#
HLOA
HOLO
INTR
KEN#
LOCK#
M/IO#
NA#
NMI
NC
PEREQ
REAOY#
RESET
SMI#
SMAOS#
P5
N5
M6
P4
P3
M5
A8
E13
M14
014
87
B12
C10
A12
013
88
B6
C8
G13
C9
C7
C6
SUSP#
SUSPA#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A4
84
A1
A5
A7
A10
A14
C5
C12
012
G2
G3
G12
G14
L12
M3
M7
M13
N4
N7
P2
P8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A2
A6
A9
81
85
811
814
C11
F2
F3
F14
J2
J3
J12
J13
M4
M8
M10
N3
P6
P14
810
O/C#
00
01
02
03
W/R#
NC - Make no external connection
Note:
NC Terminals
Connecting or terminating (high or low) any NC terminal(s) may cause unpredictable results or nonperformance of the microprocessor.
6-6
Terminal Assignments
The terminal assignments for the 144-pin, QFP TI486SXL microprocessors
are shown as viewed from the top side (component side when mounted on a
PC board) in Figure 6-4. The signal names are listed in Table 6-5 and
Table 6-6 sorted by terminal number and signal name, respectively.
Figure 6-4. 144-Pin QFP TI486SXL Package Terminals (Top View)
A20
A21
VSS
VSS
A22
A23
BS16#
015
014
013
VCC
VSS
019
018
017
016
VCC
VSS
012
011
010
09
08
VCC
07
06
05
04
03
NC
VCC
VSS
027
026
02
01
72
71
109
110
111
112
113
114
115
116
70
69
68
67
66
65
64
63
62
61
60
59
58
117
118
119
120
121
122
123
124
125
126
127
57
56
55
TI486SXL
54
53
52
51
50
49
48
128
129
130
131
132
133
134
135
136
47
46
45
137
138
44
43
42
41
40
39
~ ~~
Terminal # 1 Index Mark
1 4 1 / (On Top Side)
142
143
144
a
38
37
VSS
NC
VSS
VSS
VCC
SMI#
MEMW#
NC
SUSPA#
SUSP#
VCC
A24
A25
A26
A27
VSS
VCC
VCC
VSS
INTR
VCC
NMI
PEREQ
ERROR#
VSS
NCNCC5 t
BUSY#
RESET
VCC
A20M#
FLUSH#
KEN#
FLT#
NC
LOCK#
W/R#
O~~M~~m~romo~NM~~m~romo~~M~~m
~~M~~m~rom~~~~~~~~~~~~N~~~NN~NMMMMMMM
NC - Make no external connection
This pin is VCC5 for the T1486SXL-G40 and TI486SXL2-G50. It is NC for all other devices.
t
Mechanical Specifications
6-7
Terminal Assignments
Table 6-5. 144-Pin QFP TI486SXL Signal Names Sorted by Terminal Number
Term.
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Signal
Name
Term.
No.
00
Vss
024
025
Vce
HLOA
HOLO
Vss
NA#
REAOY#
Vcc
028
029
030
031
Vce
Vcc
Vss
Vss
Vss
Vss
Vss
Vss
Vss
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Signal
Name
Term.
No.
eLK2
AOS#
BEO#
BE1#
SMAOS#
Vce
BE2#
BE3#
Vss
M/IO#
O/C#
W/R#
W/R#
LoeK#
NC
FLT#
KEN#
FLUSH#
A20M#
Vce
RESET
BUSY#
NCNce5t
Vss
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Signal
Name
Term.
No.
ERROR#
PEREa
NMI
Vcc
INTR
Vss
Vce
Vce
Vss
A27
A26
A25
A24
Vcc
susP#
SUSPA#
NC
MEMW#
SMI#
Vcc
Vss
Vss
Ne
Vss
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Signal
Name
A2
A3
A4
A5
A6
A7
Vce
Vss
A31
A30
A29
A28
Vce
A8
A9
A10
A11
A12
Vce
Vss
A13
A14
A15
Vss
Term.
No.
Signal
Name
Term.
No.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Vss
Vee
023
022
021
020
Vee
A16
Vec
A17
A18
A19
A20
A21
Vss
Vss
A22
A23
BS16#
015
014
013
Vec
Vss
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Signal
Name
019
018
017
016
Vcc
Vss
02
011
010
09
08
Vec
07
06
05
04
03
NC
Vce
Vss
027
026
02
01
Table 6-6. 144-Pin QFP TI486SXL Terminal Numbers Sorted by Signal Name
Signal
Name
Term.
No.
Signal
Name
Term.
No.
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A20M#
A21
A22
A23
A24
73
74
75
76
77
78
86
87
88
89
90
93
94
95
104
106
107
108
109
43
110
113
114
61
A25
A26
A27
A28
A29
A30
A31
AOS#
BEO#
BE1#
BE2#
BE3#
BS16#
BUSY#
CLK2
60
59
58
84
83
82
81
26
27
28
31
32
115
48
25
35
1
144
143
137
136
135
134
133
O/C#
00
01
02
03
04
05
06
07
Signal
Name
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
Term.
No.
131
130
129
128
127
118
117
116
124
123
122
121
102
101
100
99
3
4
142
141
12
13
14
15
Signal
Name
ERROR#
FLT#
FLUSH#
HLOA
HOLO
INTR
KEN#
LoeK#
M/IO#
MEMW#
NA#
NMI
Ne
NCNec5t
NC
NC
NC
PEREa
REAOY#
RESET
SMI#
SMAOS#
susP#
SUSPA#
Term.
No.
49
40
42
6
7
53
41
38
34
66
9
51
39
47
65
71
138
50
10
45
67
29
63
64
Signal
Name
Vcc
Vce
Vee
Vcc
Vcc
Vec
Vcc
Vcc
Vec
Vcc
Vce
Vee
Vcc
Vcc
Vec
Vcc
Vcc
Vce
Vcc
Vcc
Vce
Vss
Vss
Vss
Term.
No.
Signal
Name
Term.
No.
5
11
16
17
30
44
52
55
56
62
68
79
85
91
98
103
105
119
125
132
139
2
8
18
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
W/R#
W/R#
19
20
21
22
23
24
33
48
54
57
69
70
72
80
92
96
97
111
112
120
126
140
36
37
Ne - Make no external connection
t This pin is VCC5 for the T1486SXL-G40 and TI486SXL2-G50. It is NC for all other devices.
Note:
NC Terminals
Connecting or terminating (high or low) any NC terminal(s) may cause unpredictable results or nonperformance of the microprocessor.
6-8
Terminal Assignments
The terminal assignments for the 168-pin, PGA TI486SXL microprocessors
are shown as viewed from the terminal side (bottom) in Figure 6-5 and as
viewed from the top side (component side when mounted on a PC board) in
Figure 6-6. The signal names are listed in Table 6-7 and Table 6-8 sorted by
terminal number and signal name, respectively. In addition, Table 6-9 shows
a cross-reference between the 168-pin TI486SXL pinout and the 486SX pinout.
Figure 6-5. 168-Pin PGA TI486SXL Package Terminals (Bottom View)
Terminal # 1 Index Mark
(On Top Side)
8
1
C
0
E
F
G
H
J
K
L
M
N
p
Q
R
s
8888G88~8888G88G
288888888080888888
388888888888888888
4888
888
5888
888
6888
888
788G
GGG
888
888
@88
888
11888
0088
a
9
~~a
~~V
a~~
TI486SXL
(Bottom View)
V~~
10
12
13
14
15
16
17
888
888
888
088
888
888
88888888888888888
88888888888888888
88888888888888888
NC - Make no external connection
tThis pin is VCC5 for the T1486SXL-G40 and TI486SXL2-G50. It is VCC for all other devices.
Mechanical Specifications
6-9
Terminal Assignments
Figure 6-6. 168-Pin PGA TI486SXL Package Terminals (Top View)
Terminal # 1 Index Mark
(On Top Side)
s
R
Q
p
N
M
L
J
K
H
G
FED
C
B
G8GGGGGG~GGG8GB8
88888888808888888
88888888888888888
888
888
GGG
G88
88G
G88
GGG
888
888
888
aaa
\!J\JV
\J\J\!J
888
G8@
888
888
888
888
888
888
888
888
88888888888888888
88888888888888888
a~f::::\
TI486SXL
(Top View)
88GG8GGGGGG8G8888
NC -
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Make no external connection
t This pin is VCC5 for the T1486SXL-G40 and TI486SXL2-G50. It is VCC for all other devices.
Note:
NC Terminals
Connecting or terminating (high or low) any NC terminal(s) may cause unpredictable results or nonperformance of the microprocessor.
6-10
Terminal Assignments
Table 6~7. 168-Pin PGA TI486SXL Signal Names Sorted by Terminal Number
Term.
No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
81
82
83
84
85
86
87
88
89
810
811
Signal
Name
020
022
NC
023
NC
024
VSS
029
VSS
Reserved
VSS
ERROR#
NA#
NC
NMI
INTR
NC
019
021
VSS
VSS
VSS
025
VCC
031
VCC
SMI#
VCC
Term.
No.
812
813
814
815
816
817
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
01
02
03
015
016
Signal
Name
Term.
No.
SUSPA#
SMAOS#
NC
NC
MEMW#
NC
011
018
CLK2
VCC
VCC
027
026
028
030
NC
FLT#
NC
SUSP#
NC
FLUSH#
RESET
8S16#
09
013
017
A20M#
NC
017
E1
E2
E3
E15
E16
E17
F1
F2
F3
F15
F16
F17
G1
G2
G3
G15
G16
G17
H1
H2
H3
H15
H16
H17
J1
J2
J3
Signal
Name
NC
VSS
VCC
010
HaLO
VCC
VSS
NC
08
015
KEN#
REAOY#
8E3#
VSS
VCC
012
NC
Vec
VSS
VSS
03
NC
NC
VCC
VSS
VCC(5 t )
05
016
Term.
No.
Signal
Name
Term.
No.
Signal
Name
Term.
No.
Signal
Name
J15
J16
J17
K1
K2
K3
K15
K16
K17
L1
L2
L3
L15
L16
L17
M1
M2
M3
M15
M16
M17
N1
N2
N3
N15
N16
N17
P1
8E2#
8E1#
NC
VSS
VCC
014
8EO#
VCC
VSS
VSS
06
07
NC
VCC
VSS
VSS
VCC
04
P2
P3
P15
P16
P17
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
R1
R2
R3
R4
R5
R6
A29
A30
HLOA
VCC
VSS
A31
VSS
A17
A19
A21
A24
A22
A20
A16
A13
A9
A5
A7
A2
NC
NC
NC
A28
A25
VCC
VSS
A18
VCC
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
A15
VCC
VCC
VCC
VCC
A11
A8
VCC
A3
NC
PEREQ
A27
A26
A23
8USY#
A14
VSS
A12
VSS
VSS
VSS
VSS
VSS
A10
VSS
A6
A4
AOS#
O/C#
VCC
VSS
02
01
NC
LOCK#
M/IO#
W/R#
00
Table 6-8. 168-Pin PGA TI486SXL Terminal Numbers Sorted by Signal Name
Signal
Name
Term.
No.
Signal
Name
Term.
No.
Signal
Name
Term.
No.
Signal
Name
Term.
No.
Signal
Name
A2
014 A29
P2
016
SMAOS#
J3
NC
A3
A3
R15 A30
P3
017
NC
A5
SUSP#
03
Q1
A4
S16 A31
018
C2
NC
A14 SUSPA#
A5
012 AOS#
S17 019
81
NC
A17 VCC
A6
S15 8EO#
K15 020
A1
NC
814 VCC
Q13 8E1#
A7
021
82
J16
NC
815 VCC
A8
R13 8E2#
J15
022
A2
NC
817 VCC
Q11
8E3#
A9
F17 023
A4
NC
C10 VCC
A10
S13 8S16#
C17 024
A6
NC
C12 VCC
A11
R12 8USY#
S4
025
C14 VCC
86
NC
A12
S7
CLK2
026
C3
C7
NC
016 VCC
Q10 O/C#
A13
M15 027
017 VCC
C6
NC
A14
00
P1
028
S5
C8
NC
F1
VCC
R7
01
A15
N2
029
A8
NC
G15 VCC(5t )
Q9
A16
02
N1
030
C9
NC
H3
VCC
Q3
A17
03
H2
031
88
NC
H15 VCC
A18
R5
04
ERROR# A12 NC
M3
J17
VCC
Q4
05
FLT#
A19
J2
C11
NC
L15
VCC
Q8
A20
06
L2
FLUSH#
C15 NC
N3
VCC
A20M#
015 07
L3
HLOA
P15 NC
015 VCC
Q5
A21
08
F2
E15 NC
HaLO
016 VCC
A22
09
01
INTR
A16 NC
07
017 VCC
A23
010
E3
KEN#
F15 NC
S3
R16 VCC
A24
011
C1
LOCK#
N15 PEREQ
06
R17 VCC
A25
R2
012
M/IO#
G3
N16 REAOY#
F16 VCC
A26
S2
013
02
MEMW#
816 Reserved
A10 VCC
A27
NA#
S1
014
K3
A13 RESET
C16 VCC
A28
R1
015
F3
NMI
A15 SMI#
810 VSS
NC - Make no external connection
tThis pin is VCC5 for the T1486SXL-G40 and TI486SXL2-G50. It is VCC for all other devices.
Term.
No.
813
C13
812
87
89
811
C4
C5
E2
E16
G2
G16
H16
J1
K2
K16
L16
M2
M16
P16
R3
R6
R8
R9
R10
R11
R14
A7
Signal
Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W/R#
Mechanical Specifications
Term.
No.
A9
A11
83
84
85
E1
E17
G1
G17
H1
H17
K1
K17
L1
L17
M1
M17
P17
Q2
R4
S6
S8
S9
S10
S11
S12
S14
N17
6-11
~
Table 6-9. TI486SXL Signal Summary for 168-Pin PGA Pinout
Q)I
~
I\)
Address
486SX
486SX
L
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
Data
Pin
486SX
486SX
L
DO
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
DO
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
Pin
486SX
486SXL
Pin
486SX
486SXL
Pin
S·
VCCNSS
Miscellaneous and Spares
Control
~
486SX
486SXL
Pin
Vee
Vee
Vee
Vee
Vee
Vee5(OX4)
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee(5t)
Vee
Vee
Vee
Vee
Vee
Vee
Vee
87, 89
811, C4
C5, E2
E16, G2
G16, H16
J1
K2
K16, L16
M2, M16
P16,R3
R6,R8
R9,R10
R11,R14
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A7,A9
A11,83
84,85
E1,E17
G1, G17
H1, H17
K1, K17
L1, L17
M1, M17
P17,02
R4,86
88,89
810,811
812,814
::t=.
~
cO·
:=:!
014
R15
S16
012
S15
013
R13
011
813
R12
87
010
S5
R7
09
03
R5
04
08
05
07
S3
06
R2
82
81
R1
P2
P3
01
P1
N2
N1
H2
M3
J2
L2
L3
F2
01
E3
C1
G3
02
K3
F3
J3
03
C2
81
A1
82
A2
A4
A6
86
C7
C6
C8
A8
C9
88
A20M#
AOS#
AHOLO
8EO#
8E1#
8E2#
8E3#
8LAST#
80FF#
8ROY#
8REO#
888#
8816#
CLK
A20M#
AOS#
NC
8EO#
8E1#
8E2#
8E3#
NC
NC
NC
NC
NC
8816#
CLK2
O/C#
O/C#
OPO
OP1
OP2
OP3
EA08#
FLU8H#
HLOA
HOLD
INTR
KEN#
LOCK#
M/IO#
NMI
PCO
PCHK#
PWT
PCLOK#
ROY#
RE8ET
W/R#
NC
NC
NC
NC
NC
FLU8H#
HLOA
HOLD
INTR
KEN#
LOCK#
M/IO#
NMI
NC
NC
NC
NC
REAOY#
RE8ET
W/R#
015
S17
A17
K15
J16
J15
F17
R16
017
H15
015
016
C17
C3
M15
N3
F1
H3
AS
817
C15
P15
E15
A16
F15
N15
N16
A15
J17
017
L15
016
F16
C16
N17
-
(LP) = Low Power. (S) = 486SX, (OX) = 4860X, and (OX4) = 4860X4
t This pin is Vee5 for the T1486SXL-G40 and TI486SXL2-G50. It is Vee for all other devices.
CLKSEL(LP)
NC
Reserved
Reserved
ERROR#
NC
NA#
NC
TOI(s/ox)
NC
SMI#
SMI#(s)
SUSPA#
NC
SMAOS#
NC
TM8
NC
. NC
NMI(ox)
MEMW#
TOO(s/OX)
SRESET(s)
NC
FLT#
UP#(S)
8MIACT#(s) NC
8USP#
NC
FERR#(ox)
NC
8TPCLK(s)
NC
PEREO
NC
8USY#
NC
A3
A10
A12
A13
A14
810
812
813
814
815
816
C10
C11
C12
C13
C14
G15
R17
84
:3
CI)
:=:!
Cij
Package Dimensions
6.2 Package Dimensions
The package dimensions for the TI486SXLC microprocessors are shown in
Figure 6-7. The package dimensions for the 132-pin, PGA TI486SXL microprocessors are shown in Figure 6-8, package dimensions forthe 144-pin QFP
versions are shown in Figure 6-9 and Figure 6-10, and the package dimensions for the 168-pin PGA TI486SXL are shown in Figure 6-11 .
Figure 6-7. 100-Pin Thermally Enhanced Plastic QFP Package Dimensions (TI486SXLC)
PJF(S-PQFP-G100)
PLASTIC QUAD FLATPACK
50
~
y
L
0.025 (O,64) 1
1-$-1.
0.012 (0,3O}
0.008 (0,20).
0.006 (0,15)
@
1.
26
0.006 (0,15) TYP
25
0.766(19,46)
0.734 (18,64)
sa --~
0.890(22,61)
0.870 (22,10)
0.912 (23,16)
0.888 (22,56)
sa - - - - - . t l
t
0.151 (3,81)
0.130 (3,30)
~
sa _ _ _~
0.046 (1,17)
0.036 (0,91)
it l
0.1;: (4,57)
~
MA~
Seating Plane
1=1 0.004{O,10j
'-----'------'--------'----'--~
40400931A 10/93
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MO-069
Thermally enhanced molded plastic package with a heat slug (HSL) exposed on bottom side of the package body.
Mechanical Specifications
6-13
Package Dimensions
Figure 6-8. 132-Pin Ceramic PGA Package Dimensions (TI486SXL)
CPGA-132 PIN
CERAMIC PIN GRID ARRAY
Pin # 1Index Mark
(On Top Side)
1,27 (0.50)
MAXTYP
I I I I I I I
~Ir-
1_
18,4(0.725)
no
1 '~@@@@@@@@@@@@~ - 16,5(0.650)
2 @@@@@@@I@@@@@@@ - 14,0(0.550)
3 @@@@@@@@@@@@@@ - 11,4(0.450)
4 @@@~
@@@ - 8,89(0.350)
5 @@@
@@@ - 6,35(0.250)
6 @@@
I
@@@ - 3,81 (0.150)
7@@)@_-L_@@@-0-1,27(8.050)
8 @@@
TI486SXL
@@@
9 @@@
(BOTT~M VIEW)
@@@
0,025 (0.001)R
10 @@@
@@@
MINTYP
"&
11 @@@
@@@
12 @@@@@@@@@@@@@@
0,47(0.0180)
13 @@@@@@@I@@@@@@@
14 ~ 0 @@@@@@@@@@@Q
~
o
U'
L
D E
----
F G
1,65 (0.065)
Swedge Pin
Standoff (4) Places
- - - - - - - 36,83 (1.450) - - - - - .
4,57 (0,180)1
J
3,05 (0.120)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
6-14
7/94
Package Dimensions
Figure 6-9. 144-Pin Plastic QFP Dimensions (TI486SXL)
PLASTIC QUAD FLATPACK
PCE(S-PQFP-G144)
73
108
72
109
~
L
~
1-$-1 o,13@1
0,65
144
37
o
0,16TVP
1
36
k- 22,75 sa TVP --------.t.1
~------------ 28,20
27,80
sa -----------.
31,45 sa ------~
30,95
7/94
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-022
Thermally enhanced molded plastic package with a heat spreader (HSP).
E. Foot length is measured from lead tip to a position on backside of lead O,25mm above seating plane (gage plane).
Mechanical Specifications
6-15
Package Dimensions
Figure 6-10. 144-Pin Ceramic QFP Package Dimensions (TI486SXL)
HBN (S-CaFP-G 144)
CERAMIC aUAD FLATPACK
73
108
72
109
~ 0,30TVP
T
~
144
37
o
0,16 NOM
1
I~. .-----
36
22,75 TVP
28,00
27,45
31,45
30,95
-------al~1
sa
f
3,42TVP
~
sa
i
0,25 MIN
0,95
0,65
S~_~M
4,07 MAX
~c>IO,10
I
9/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
6-16
~':Ji"v':Ji'ya
Dimensions
Figure 6-11. 168-Pin Ceramic PGA Package Dimensions (TI486SXL)
CPGA-168 PIN
CERAMIC PIN GRID ARRAY
-~--- 40,64 (1.60) TYP - - - - ~
i44.S(1.7S)TYPi
S
R
Q
@@~@@@@@@@@@@@~@@
p
N
M
L
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
K
J
H
G
F
E
0
0
4.0 (0.160)TYP
~~
0,46 (0.018) TYP
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
@@@
c
@@~@@@@@@@@@@@~@@
B
A
@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@
rt
H f ~ ffiHHHHHHl U n
@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@
1 2 3 4 5 6 7 8 9 1011121314151617
1
---.jj.-2,92 (0.115) TYP ~
2,54 (0.100) TYP
7/94
NOTES: A. All linear dimensions are in millimeters (inches).
B. This drawing is subject to change without notice.
Mechanical Specifications
6-17
Thermal Characteristics
6.3 Thermal Characteristics
The junction-to-ambient (typical) values vary for individual applications depending on factors relating to how the device is mounted and the surrounding
environment such as:
o
Circuit trace density of the printed circuit board (PCB) and/or the presence
or absence of ground or power planes internal to the PCB that affect the
ability of the board to conduct heat away from the device
o
Whether the device is soldered to the PCB or is inserted into a socket
o
Orientation of the PCB that the device is mounted on and the proximity of
adjacent PCBs or system enclosure features that impede natural convection air circulation around the device
o
Ambient air temperature in close proximity to the device and the proximity
of other high-power devices in the system
o
Presence of airflow over the device and the attachment of an external heat
sink as indicated by the data in Table 6-10 and Table 6-11
For the 1~O-pin and 144-pin QFPs, the values shown for thermal resistance
in Table 6-10 and Table 6-12 with a heatsink are examples of the estimated
improvement in thermal performance.
Note:
The final responsibility for verifying designs incorporating any version of a TI
microprocessor rests with the customer originating the design. Recommended case temperature extremes are specified in Table 5-4, Table 5-5,
and Table 5-6.
Table 6-10. TI486SXLC 1DO-Pin PQFP Thermal Resistance and Airflow
Thermal Resistance (OelW)
TI486SXLC 100-Pin PGFP
Without Heatsink
Airflow (FtlMin)
o
With Heatsinkt
RaJC
RaJA
RaJA
2
36
32
2
15
12
100
200
400
600
t
6-18
Round, omni-directional heatsink. Dimensions are approximately 1.125" diameter by 0.42"
high.
Thermal Characteristics
Table 6-11. TI486SXL 132-Pin CPGA Thermal Resistance and Airflow
Thermal Resistance (OCIW)
TI486SXL 132-Pin CPGA t
Airflow (FtiMin)
t
ReJC
RSJA
0
3
20
100
3
17
200
3
15
400
3
11
600
3
9
Thermal resistance values shown are based on measurements made on similar ceramic PGA
packages.
Table 6-12. TI486SXL PQFP Thermal Resistance and Airflow
Thermal Resistance caCIW)
TI486SXL 144-Pin PQFP:j:
Without Heatsink
Airflow (FtiMin)
o
With Heatsink§
RSJC
RSJA
RSJA
2
25
18
2
12
6
100
200
400
600
:j: Values shown are based on measurements made on similar 28 mm QFP packages.
§ Pin-Fin heatsink. Dimensions are approximately 1.2" long, by 1.3" wide, by 0.49" high.
Table 6-13. TI486SXL 144-Pin CQFP Thermal Resistance and Airflow
Thermal Resistance (OCIW)
TI486SXL 144-Pin CQFP1f
Airflow (FtiMin)
RSJC
RSJA
o
3
33
100
3
28
200
3
24
1f Thermal resistance values shown are based on measurements made on similar ceramic QFP
packages.
Mechanical Specifications
6-19
Thermal Characteristics
Table 6-14. TI486SXL 168-Pin CPGA Thermal Resistance and Airflow
Thermal Resistance eCIW)
168-Pin Ceramic PGA Package
Airflow (FtlMin)
RSJC
RSJA
0
3
18
100
3
15
200
3
13
400
3
10
600
3
8
Thermal resistance values shown are based on measurements made on similar ceramic PGA
packages.
6.3.1
Airflow Measurement Setup
The wind tunnel used for airflow measurements is represented schematically
in Figure 6-12.
Figure 6-12. Wind Tunnel Schematic Diagram
Device test board
Temperature and
anemometer-type
airflow probe
~
>
Airflow
>
~
~
I
Wind tunnel cross-section is 6" by 6".
(Dimensions are approximate.)
~
~
78 "
~
5"
II
I
I
I
~I~
24"
Fan
II
I
I
I
.
p
Typically, the devices undergoing thermal test are mounted on a test board
consisting of 0.062" thick FR4 printed circuit board material with one-ounce
copper etch. Surface-mount devices are soldered to the test board using
matching footprints with minimal circuit trace density required to electrically interconnect the device to the board. PGA devices are typically inserted in a
socket that is soldered to the test board.
6-20
Thermal Characteristics
6.3.2
Thermal Parameter Definitions
The maximum die temperature (TJmax) and the maximum ambient temperature (TAmax) can be calculated using the following equations:
Tjmax = TC + (P max x RSJC)
TAmax = TJ - (P max x RSJA))
where:
TJmax = Maximum average junction temperature (OC)
TC = Case temperature at top center of package (OC)
Pmax = Maximum device power dissipation (W)
RSJC = Junction-to-case thermal resistance (OC/W)
TAmax = Maximum ambient temperature (OC)
TJ = Average junction temperature (OC)
RSjA = Junction-to-ambient thermal resistance (OC/W)
Values for RSJA and RSJC are given in Table 6-10 and Table 6-11 for various
airflows.
Mechanical Specifications
6-21
6-22
Chapter 7
Instruction Set
This chapter provides information pertaining to the TI486SXL(C) microprocessor instruction set. Information is provided to explain the general instruction
format, fields, flags, clock-count summary, and detailed information on the
instruction encodings. All instructions are listed in the instruction set in Section
7.5, Instruction Set.
Topic
7.1
Page
Generallostructh;:m Format .. , ~ .••• , ......... , •.•••• , .. ~ .••••..• , ~ 7-2
7.2~ Instruction Fields, •.••. • d~:;',
••••• , •• " ••••, ••
7.3
Flags •• '," ••",.:~ . " ,',. ,,';' .; .. ", .. ,'. ,.,::.', '~ ,,", . ,,~ ',', ','. "". , • ~:; • , ~,~ • '. '. ~' .•",' •.' ~ ,.':7:-1'2
7.4
Clock..CountSuininary ..... " ~~, •. , . ~ •• ~~. ~ . ~
7.5
Instruction Set. , .... "... ,.~, ........................ ,;, ......... 7-13
•.• ~ ......... ,7..13
7-1
General Instruction Format
7.1
General Instruction Format
All of the TI486SXL(C) microprocessor family machine instructions follow the
general instruction format shown in Figure 7-1. These instructions vary in
length and can start at any byte address. An instruction consists of one or more
bytes that can include: prefix byte(s), at least one opcode byte, mod rim byte,
s-i-b (ss, index, and base fields) byte, address displacement byte(s) and immediate data byte(s). An instruction can be as short as one byte and as long
as 15 bytes. If there are more than 15 bytes in the instruction, a general protection fault (error code of 0) is generated.
Figure 7-1. General Instruction Format
Ip p p p p p p PiT T T T T T TTl mod
7
07
I ss
R R R rim
I
index base d321161al none id321161al none
0765320765320
optional prefix
opcode
byte(s)
(one or two bytes)
mod rim
byte
s-i-b
byte
address
displacement
/ (4, 2, 1 bytes,
V~-----',
or none)
,'--------
register and address
mode specifier
P - prefix bit
T - opcode bit
R - opcode bit or reg bit
7-2
immediate
data
(4, 2, 1 bytes,
or none)
Instruction Fields
7.2 Instruction Fields
The general instruction format shows the larger fields that make up an instruction. Certain instructions have smaller encoding fields that vary according to
the class of operation. These fields define information such as the direction of
the operation, the size of the displacements, register encoding and sign extension. All the fields are described in Table 7-1, and subsequent paragraphs
provide greater detail.
Table 7-1. Instruction Fields
Field Name
Description
Number of Bits
Prefix
Specifies segment register override, address and operand size,
repeat elements in string instruction, LOCK# assertion.
8 per byte
Opcode
Identifies instruction operation.
1 or 2 bytes
w
Specifies if data is byte or full size (full size is 16 or 32 bits).
d
Specifies direction of data operation.
s
Specifies if an immediate data field must be sign-extended.
reg
General register specifier
3
mod rim
Address mode specifier
2 for mod; 3 for rim
ss
Scale factor for scaled index address mode
2
index
General register to be used as index register
3
base
General register to be used as base register
2
sreg2
Segment register for CS, SS, OS, and ES
2
sreg3
Segment register for CS, SS, OS, ES, FS, and GS
3
eee
Control, debug, and test register specifier
3
Address
displacement
Address displacement operand
1, 2, or 4 bytes
Immediate data
Immediate data operand
1, 2, or 4 bytes
Instruction Set
7-3
Instruction Fields
7.2.1
Prefixes
Prefix bytes can be placed in front of any instruction. The prefix modifies the
operation of the immediately following instruction only. When more than one
prefix is used, the order is not important. There are five types of prefixes as
follows:
1) Segment override explicitly specifies which segment register an instruction will use.
2) Address size and operand size toggle between 16- and 32-bit addressing
modes. Prefixing the instruction for operand size or address size selects
the inverse of the current addressing mode. See also Section 2.1 , Processor Initialization, page 2-2.
3) Repeat is used with a string instruction that causes the instruction to be
repeated for each element of the string.
4) Lock is used to assert the hardware LOCK# signal during execution of the
instruction.
Table 7-2 lists the encodings for each of the available prefix bytes. The operand-size and address-size prefixes allow individual overriding of the default
value for operand size and effective-address size. The presence of these prefixes selects the opposite (nondefault) operand size and/or effective-address
size as the case may be.
Table 7-2. Instruction Prefix Summary
Prefix
7-4
Encoding
Description
ES:
26h
Override segment default, use ES for memory operand.
CS:
2Eh
Override segment default, use CS for memory operand.
SS:
36h
Override segment default, use SS for memory operand.
OS:
3Eh
Override segment default, use OS for memory operand.
FS:
64h
Override segment default, use FS for memory operand.
GS:
65h
Override segment default, use GS for memory operand.
Operand size
66h
Make operand size attribute the inverse of the default.
Address size
67h
Make address size attribute the inverse of the default.
LOCK
FOh
Assert LOCK# hardware signal.
REPNE
F2h
Repeat the following string instruction.
REP/REPE
F3h
Repeat the following string instruction.
Instruction Fields
7.2.2
Opcode Field
The opcode field is either one or two bytes long and specifies the operation to
be performed by the instruction. Some operations have more than one opcode, each specifying a different form of the operation. Some opcodes name
instruction groups. For example, opcode Ox80 names a group of operations
that have an immediate operand, and a register or memory operand. The
group opcodes use an opcode extension field of three bits in the following byte,
called the MOD RIM byte, to resolve the operation type. Opcodes for the entire
TI486SXL(C) microprocessor instruction set are listed in Table 7-17 on page
7-14. The opcodes are given in hex values unless shown within brackets ([ ]).
Values shown in brackets are binary values.
7.2.3
vv Field
The 1-bit field indicates the operand size during 16- and 32-bit data operations
as shown in Table 7-3.
Table 7-3. w Field Encoding
w Field
o
Operand Size
16-Bit Data Operations
Operand Size
32-Bit Data Operations
8 bits
8 bits
16 bits
32 bits
Instruction Set
7-5
Instruction Fields
7.2.4
d Field
The d field determines which operand is taken as the source operand and
which operand is taken as the destination as shown in Table 7-4.
Table 7-4. d Field Encoding
d Field
o
Direction Of Operation
Source Operand
Designation Operand
Register
reg
mod rim or mod ss-index-base
mod rim or mod ss-index-base
reg
-7
Register/Memory
Register/Memory
7.2.5
-7
Register
reg Field
The reg field determines which general registers are to be used. The selected
register is dependent on whether 16- or 32-bit operation is current and the status of the "w" bit as shown in Table 7-5.
Table 7-5. reg Field Encoding
7-6
reg Field
16-Bit
Operation
w Field Not
Present
32-Bit
Operation
w Field Not
Present
16-Bit
Operation
w=o
16-Bit
Operation
w=1
32-Bit
Operation
w=o
32-Bit
Operation
w=1
000
AX
EAX
AL
AX
AL
EAX
001
CX
ECX
CL
CX
CL
ECX
010
DX
EDX
DL
DX
DL
EDX
011
BX
EBX
BL
BX
BL
EBX
100
SP
ESP
AH
SP
AH
ESP
101
BP
EBP
CH
BP
CH
EBP
110
SI
ESI
DH
SI
DH
ESI
111
DI
EDI
BH
DI
BH
EDI
Instruction Fields
7.2.6
mod and rIm Field
The mod and rim sub-fields, within the mod rim byte, select the type of memory
addressing to be used. Some instructions use a fixed addressing mode (e.g.,
PUSH or POP) and therefore, these fields are not present. Table 7-6 lists the
addressing method when 16-bit addressing is used and a mod rim byte is present. Some mod rim field encodings are dependent on the w field and are shown
in Table 7-7.
Table 7-6. mod rim Field Encoding
mod rIm
16-Bit Address Mode
With mod rIm Byte
32-Bit Address Mode
With mod rIm Byte
And No s-i-b Byte Present
00000
DS:[BX+SI]
DS:[EAX]
00001
DS:[BX+DI]
DS:[ECX]
00010
SSS:[BP+SI]
DS:[EDX]
00011
SS:[BP+DI]
DS:[EBX]
00100
DS:[SI]
s-i-b is present (see subsection 7.2.7)
00101
DS:[DI]
DS:[d32]
00110
DS:[d16]
DS:[ESI]
00 111
DS:[BX]
DS:[EDI]
01 000
DS:[BX+SI+d8]
DS:[EAX+d8]
01 001
DS:[BXI+DI+d8]
DS:[EAX+d8]
01 010
SS:[BP+SI+d8]
DS:[EDX+d8]
01 011
SS:[BP+DI+d8]
DS:[EBX+d8]
01 100
DS:[SI+d8]
s-i-b is present (see subsection 7.2.7)
01 101
DS:[DI+d8]
SS:[EBP+d8]
01 110
SS:[BP+d8]
DS:[ESI+d8]
01 111
DS:[BX+d8]
DS:[EDI+d8]
10000
DS:[BX+SI+d16]
DS:[EAX+d32]
10001
DS:[BX+DI+d16]
DS:[ECX+d32]
10010
SS:[BP+SI+d16]
DS:[EDX+d32]
10011
SS:[BP+DI+d16]
DS:[EBX+d32]
10100
DS:[SI+d16]
s-i-b is present (see subsection 7.2.7)
10101
DS:[DI+d16]
SS:[EBP+d32]
10 110
SS:[BP+d16]
DS:[ESI+d32]
10 111
DS:[BX+d16]
DS:[EDI+d32]
11 000
11 111
See Table 7-7
See Table 7-7
Instruction Set
7-7
Instruction Fields
Table 7-7. mod rim Field Encoding Dependent on
7-8
w Field
mod rIm
16-Bit Operation
w=o
16-Bit Operation
w=1
32-Bit Operation
w=o
32-Bit Operation
w=1
11 000
AL
AX
AL
EAX
11 001
CL
CX
CL
ECX
11 010
OL
OX
OL
EOX
11 011
BL
BX
BL
EBX
11 100
AH
8P
AH
ESP
11 101
CH
BP
CH
EBP
11 110
OH
81
OH
E81
11 111
BH
01
BH
EOI
Instruction Fields
7.2.7
mod and base Fields
In Table 7-6, the note "s-i-b present" (for certain entries) forces the use of the
mod base field as listed in Table 7-8.
Table 7-8. mod base Field Encoding
mod rIm
32-Bit Address Mode With mod rIm
Byte and No s-i-b Byte Present
00000
DS:[EAX+(scaled index)]
00001
DS:[ECX+(scaled index)]
00010
DS:[EDX+(scaled index)]
00011
DS:[EBX+(scaled index)]
00100
SS:[ESP+(scaled index)]
00101
DS:[EBP+(scaled index)]
00110
DS:[ESI+(scaled index)]
00 111
DS:[EDI+(scaled index)]
01 000
DS:[EAX+(scaled index)+d8]
01 001
DS:[ECX+(scaled index)+d8]
01 010
DS:[EDX+(scaled index)+d8]
01 011
DS:[EBX+(scaled index)+d8]
01 100
SS:[ESP+(scaled index)+d8]
01 101
SS:[EBP+(scaled index)+d8]
01 110
DS:[ESI+(scaled index)+d8]
01 111
DS:[EDI+(scaled index)+d8]
10000
DS:[EAX+(scaled index)+d32]
10001
DS:[ECX+(scaled index)+d32]
10010
DS:[EDX+(scaled index)+d32]
10011
DS:[EBX+(scaled index)+d32]
10100
SS:[ESP+(scaled index)+d32]
10101
SS:[EBP+(scaled index)+d32]
10 110
DS:[ESI+(scaled index)+d32]
10 111
DS:[EDI+(scaled index)+d32]
Instruction Set
7-9
Instruction Fields
7.2.8
ss Field
The ss field (Table 7-9) specifies the scale factor used in the offset mechanism
for address calculation. The scale factor multiplies the index value to provide
one of the components used to calculate the offset address.
Table 7-9. ss Field Encoding
7.2.9
ss Field
Scale Factor
00
x1
01
x2
10
x4
11
x8
index Field
The index field (Table 7-10) specifies the index register used by the offset
mechanism for offset-address calculation. When no index register is used
(index field = 00), the ss value must be 00 or the effective address is
undefined.
Table 7-10. index Field Encoding
index Field
Index Register
000
EAX
001
ECX
010
EOX
011
EBX
100
none
101
EBP
110
ESI
111
EDI
7.2.10 sreg2 Field
The sreg2 field (Table 7-11) is a two-bit field that allows one of the four
286-type segment registers to be specified.
Table 7-11. sreg2 Field Encoding
7-10
sreg2 Field
Segment Register
Selected
00
ES
01
CS
10
SS
11
OS
Instruction Fields
7.2.11 sreg3 Field
The sreg3 field (Table 7-12) is three-bit field that is similar to the sreg2 field,
but allows use of the FS and GS segment registers.
Table 7-12.sreg3 Field Encoding
sreg3 Field
Segment Register
Selected
000
ES
001
CS
010
SS
011
DS
100
FS
101
GS
110
undefined
111
undefined
7.2.12 eee Field
The eee field is used to select the control, debug, and test registers as indicated in Table 7-13. The values shown are the only valid encodings for the eee
bits.
Table 7-13.eee Field Encoding
eee Field
Register Type
Base Register
000
Control register
CRO
010
Control register
CR2
011
Control register
CR3
000
Debug register
DRO
001
Debug register
DR1
010
Debug register
DR2
011
Debug register
DR3
110
Debug register
DR6
111
Debug register
DR?
011
Test register
TR3
100
Test register
TR4
101
Test register
TR5
110
Test register
TR6
111
Test register
TR?
Instruction Set
? -11
Flags
7.3 Flags
The instruction set summary table lists nine flags that are affected by the
execution of instructions. The conventions shown in Table 7-14 are used to
identify the different flags. Table 7-15 lists the conventions used to indicate
what action the instruction has on the particular flag.
Table 7-14. Flag Abbreviations
Abbreviation
Name of Flag
OF
Overflow flag
DF
Direction flag
IF
Interrupt enable flag
TF
Trap flag
SF
Sign flag
ZF
Zero flag
AF
Auxiliary flag
PF
Parity flag
CF
Carry flag
Table 7-15.Action of Instruction on Flag
Instruction Table
Symbol
Action
m
Flag is modified by the instruction
u
Flag is not changed by the instruction
o
Flag is reset to 0
Flag is set to 1
7-12
Clock Count Summary / Instruction Set
7.4 Clock-Count Summary
The clock-count summaries presented in Table 7-17 are based on assumptions associated with each individual instruction. Abbreviations that indicate
the clock-count conditions have been developed to simplify the presentation.
7.4.1
Assumptions
The following assumptions have been made in presenting the clock-count values for the individual instructions.
o
o
o
o
o
o
o
o
7.4.2
The instruction has been prefetched, decoded, and is ready for execution.
Bus cycles do not require wait states.
There are no local-bus HOLD requests delaying processor access to the
bus.
No exceptions are detected during instruction execution.
If an effective address is calculated, it does not use two general register
components. One register, scaling, and displacement can be used within
the clock count shown. However, if the effective-address calculation uses
two general register components, add 1 to the clock count shown.
All clock counts assume aligned 16-bit memory/IO operands for cachemiss counts.
If instructions access a misaligned 16-bit operand or a 32-bit operand on
even addresses, add two clock counts for read or write, and add four clock
counts for read and write.
If instructions access a 32-bit operand on odd addresses, add four clock
counts for read or write, and add eight clock counts for read and write.
Abbreviations
The clock counts listed in the instruction set summary table are grouped by operating mode and whether there is a register/cache hit or a cache miss. In
some cases, more than one clock count is shown in a column for a given
instruction, or a variable is used in the clock count. The abbreviations used for
these conditions are listed in Table 7-16.
Table 7-16. Clock-Count Abbreviations
Clock-Count
Symbol
Explanation
/
Register operand/memory operand
n
Number of times operation is repeated
L
Level of the stack frame
Conditional jump taken I conditional jump not taken
CPL
~
IOPL \ CPL > IOPL
7.5 Instruction Set
The TI486SXLC and TI486SXL instruction set is provided in Table 7-17.
Instruction name, encoding, flags that are affected, and instruction clock
counts for each instruction are shown. The clock-count values are based on
the assumptions described in subsection 7.4.1.
Instruction Set
7-13
~
......
s2"
Table 7-17. Instruction Set
CI)
~
Real-Mode
Clocks
Flags
Instruction
Opcode
AAA ASCII Adjust AL after Add
37
P
F
C
F
Reg!
Cache
Hit
m
u
m
5
5
m
u
m
u
4
4
m
u
m
u
17
17
5
5
1
3
3
1/3
1
5
5
5
1
3
3
1/3
1
5
5
5
1
3
3
1/3
1
5
5
5
1
3
3
1/3
1
5
5
5
6/10
10
0
0
S
F
F
Z
F
A
F
I
F
T
F
u
u
u
u
u
u
F
AAD ASCII Adjust AX before Divide
D50A
u
u
u
u
m
AAM ASCII Adjust AX after Multiply
D40A
u
u
u
u
m
AAS ASCII Adjust AL after Subtract
3F
u
u
u
u
u
u
m
u
m
m
u
u
u
m
m
m
m
m
ADC Add with Carry
Register to Register
Register to Memory
Memory to Register
Immediate to RegisterlMemory
Immediate to Accumulator
ADD Integer Add
Register to Register
Register to Memory
Memory to Register
Immediate to RegisterlMemory
Immediate to Accumulator
1 [OOdw] [11 reg rim]
1 [OOOw] [mod reg rim]
1 [001 w] [mod reg rim]
8 [OOsw] [mod 010 r/m]t
1 [010w]t
o [OOdw] [11 reg rim]
o [OOOw] [mod reg rim]
o [001w] [mod reg rim]
u
u
m
m
m
m
1
3
3
1/3
1
ARPL Adjust Requested Privilege Level
From RegisterlMemory
63 [mod reg rim]
0
u
u
u
m
m
u
m
1
3
3
1/3
1
62 [mod reg rim]
u
u
u
u
u
u
u
u
u
m
u
u
u
u
u
u
u
u
u
u
m
u
u
Real
Mode
Protected
Mode
1
2
1
2
1
2
3
2
1,4
2,5,6,7,8
1
2
5
5
5
u
11 +int
11
u
5/7+n
g"
Notes
5
5
5
u
11 +int
11
OF BC[mod reg rim]
Cache
Miss
0
[OOdw] [11 reg rim]
[OOOw] [mod reg rim]
[001 w] [mod reg rim]
[OOsw] [mod 100 r/m]t
[010w]t
u
Regl
Cache
Hit
m
8 [OOsw] [mod 000 r/m]t
2
2
2
8
2
BSF Scan Bit Forward
RegisterlMemory, Register
u
o [010w]t
AND Boolean AND
Register to Register
Register to Memory
Memory to Register
Immediate to RegisterlMemory
Immediate to Accumulator
BOUND Check Array Boundaries
If Out of range (Int 5)
If In Range
m
Cache
Miss
()
Protected-Mode
Clocks
9+n
5/7+n
9+n
~
Table 7-17. Instruction Set (Continued)
Real-Mode
Clocks
Flags
D
F
I
F
T
F
S
F
Z
F
F
A
F
P
F
C
F
u
u
u
u
u
m
u
u
u
0
Instruction
Opcode
BSR Scan Bit Reverse
Register/Memory, Register
OF BC[mod reg rim]
BSWAP Byte Swap
OF C[1 reg]
BT Test Bit
Register/Memory, Immediate
Register/Memory, Register
OF BA[mod 100 r/mlt
OF A3[mod reg rim]
BTC Test Bit and Complement
Register/Memory, Immediate
Register/Memory, Register
OF BA[mod 111 r/m]t
OF BB[mod reg rim]
BTR Test Bit and Reset
Register/Memory, Immediate
Register/Memory, Register
OF BA[mod 110 r/m]t
OF B3[mod reg rim]
s-
CI)
St
~
5"'
::::,
~
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
m
u
u
u
BTS Test Bit and Set
Register/Memory
R~ister ~hort ~rm)
u
u
-
-
-
OF BA[mod 101 rim]
_L-0F AB[rl'l0d reg rim]
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
Reg!
Cache
Hit
5/7+n
Protected-Mode
Clocks
Cache
Miss
Reg!
Cache
Hit
Cache
Miss
9+n
5/7+n
9+n
5
Notes
Real
Mode
Protected
Mode
1
2
1
2
1
2
1
2
1
2
5
3/4
3/6
5
7
3/4
3/6
5
7
4/5
5/8
6
9
4/5
5/8
6
9
4/5
5/8
6
9
4/5
5/8
6
9
4/5
5/8
6
9
4/5
5/8
6
9
m
m
m
t = immediate data
::J: = 8-bit displacement
§ = 16-bit displacement
~ = 32-bit displacement
m = Flag modified
u = Flag unchanged
1) Exception 13 fault (general protection) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum CS, OS, ES, FS, or GS segment
Notes:
limit (FFFFh). Exception 12 fault (stack segment limit violation or not present) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum SS limit.
2) Exception 13 fault occurs if the memory operand in CS, OS, ES, FS, or GS cannot be used due to either a segment limit violation or an access rights violation. If a stack limit
is violated, an exception 12 occurs.
3) This is a protected mode instruction. Attempted execution in real mode will result in exception 6 (invalid opcode).
4) An exception may occur, depending on the value of the operand.
5) LOCK# is asserted during descriptor table accesses.
6) All segment descriptor accesses in the GOT or LOT made by this instruction automatically asserts LOCK# to maintain descriptor integrity in multiprocessor systems.
7) JMP, CALL, INT, RET, and IRET instructions referring to another code segment causes an exception 13, if an applicable privilege rule is violated.
8) The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13 fault occurs.
s-
CI)
~
01
St
~
5"'
::::,
~
~
.....
~
Table 7-17. Instruction Set (Continued)
cr>
Real-Mode
Clocks
Flags
D
F
I
F
T
F
5
Z
F
F
F
A
F
P
F
C
F
u
u
u
u
u
u
u
u
u
0
Instruction
Opcode
CALL Subroutine Call
Direct within Segment
Register/Memory Indirect within Segment
E811
FF [mod 010 rim]
Reg!
Cache
Hit
Cache
Miss
7
8/9
10
Reg!
Cache
Hit
7
8/9
10
30
41
83
81+4x
262
293
179
238
296
182
49
97
95+4x
263
317
206
258
340
229
14
43
85
86+4x
267
298
181
243
301
184
34
51
99
100+4x
268
322
211
263
345
230
Direct Intersegment
Call Gate to Same Privilege
Call Gate to Different Privilege No Parameters
Call Gate to Different Privilege Parameters
16-Bit Task to 16-bit TSS
16-Bit Task to 32-bit TSS
16-Bit Task to V86 Task
32-Bit Task to 16-bit TSS
32-Bit Task to 32-bit TSS
32-Bit Task to V86 Task
9A [unsigned full offset,
selector]
12
Indirect Intersegment
Call Gate to Same Privilege
Call Gate to Different Privilege No Parameters
Call Gate to Different Privilege Parameters
16-Bit Task to 16-bit TSS
16-Bit Task to 32-bit TSS
16-Bit Task to V86 Task
32-Bit Task to 16-bit TSS
32-Bit Task to 32-bit TSS
32-Bit Task to V86 Task
FF [mod 011 rim]
14
CBW Convert Byte to Word
98
u
u
u
u
u
u
u
u
u
3
3
CDa Convert Doubleword to Quadword
99
u
u
u
u
u
u
u
u
u
1
2
CLC Clear Carry Flag
F8
u
u
u
u
u
u
u
u
0
1
1
17
CLD Clear Direction Flag
FC
u
0
u
u
u
u
u
u
u
1
1
CLI Clear Interrupt Flag
FA
u
u
0
u
u
u
u
u
u
5
5
CLTS Clear Task Switched Flag
OF06
u
u
u
u
u
u
u
u
u
4
4
CMC Complement the Carry Flag
F5
u
u
u
u
u
u
u
u
m
1
1
CMP Compare Integers
Register to Register
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator
m
u
u
u
m
m
m
m
m
3
3
3
8
3
1
3
3
1/3
1
1
3
3
1/3
1
[10dw] [11 reg rim]
[101 w] [mod reg rim]
[100w] [mod reg rim]
[OOsw] [mod 111 r/m]t
[110w]t
-
-
- - '---
~-
-
--
"-----
-- -
5
5
5
Cache
Miss
2
g:
C)
Protected-Mode
Clocks
Notes
:J
Real
Mode
Protected
Mode
1
2,6,7,8
9
5
5
5
10
11
1
2
~
Table 7-17. Instruction Set (Continued)
Real-Mode
Clocks
Flags
0
D
F
I
F
T
F
S
F
Z
F
A
F
P
F
Protected-Mode
Clocks
C
F
Regl
Cache
Hit
Cache
Miss
Regl
Cache
Hit
Cache
Miss
Real
Mode
Protected
Mode
8
9
8
9
1
2
5
7
8
5
7
8
1
2
1,4
2,4
1
2
Instruction
Opcode
F
CMPS Compare String
A [011w]
m
u
u
u
m
m
m
m
m
m
u
u
u
m
m
m
m
m
CMPXCHG Compare and Exchange
Register1, Register2
Memory, Register
OF B[OOOw] [11 reg2 reg1]
OF B[OOOw] [mod reg rim]
CWD Convert Word to Doubleword
99
u
u
u
u
u
u
u
u
u
1
2
CWDE Convert Word to Doubleword Extended
98
u
u
u
u
u
u
u
u
u
3
3
DAA Decimal Adjust AL after Add
27
u
u
u
u
m
m
m
m
m
4
4
DAS Decimal Adjust AL after Subtract
2F
u
u
u
u
m
m
m
m
m
4
4
m
u
u
u
m
m
m
m
u
DEC Decrement by 1
Register/Memory
Register (short form)
1/3
1
F [111w] [mod 001 rim]
4 [1 reg]
DIV Unsigned Divide
Accumulator by Register/Memory
Divisor: Byte
Word
Doubleword
F [011w] [mod 110 rim]
ENTER Enter New Stack Frame
Level = 0
Level = 1
Level (L) > 1
C8 [8-bit level]§
HLT Halt
F4
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
1/3
1
5
17
24
40
13/15
21/22
38/39
10
6+4*L
7
10
6+4*L
17
24
40
u
7
10
6+4*L
u
5
u
13/15
21/22
38/39
u
Notes
u
3
3
10
6+4*L
11
t =
s-
(I)
St
?5
8".
::J
fi?
-..
-;--J
......
-.....J
immediate data
:I: = 8-bit displacement
§ = 16-bit displacement
~ = 32-bit displacement
m = Flag modified
u = Flag unchanged
Notes:
1) Exception 13 fault (general protection) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum CS, DS, ES, FS, or GS segment
limit (FFFFh). Exception 12 fault (stack segment limit violation or not present) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum SS limit.
2) Exception 13 fault occurs if the memory operand in CS, DS, ES, FS, or GS cannot be used due to either a segment limit violation or an access rights violation. If a stack limit
is violated, an exception 12 occurs.
3) This is a protected mode instruction. Attempted execution in real mode will result in exception 6 (invalid opcode).
4) An exception may occur, depending on the value of the operand.
5) LOCK# is asserted during descriptor table accesses.
6) All segment descriptor accesses in the GDT or LDT made by this instruction automatically asserts LOCK# to maintain descriptor integrity in multiprocessor systems.
7) JMP, CALL, INT, RET, and IRET instructions referring to another code segment causes an exception 13, if an applicable privilege rule is violated.
8) The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13 fault occurs.
9) An exception 13 fault occurs if CPL is greater than IOPL .
1O)This instruction may be executed in real mode. In real mode, its purpose is primarily to initialize the CPU for protected mode.
11) An exception 13 fault occurs if CPL is greater than 0 (0 is the most privileged level).
s(I)
~
?5
8".
::J
~
~
Table 7-17. Instruction Set (Continued)
:J
(I)
~
(Xl
Real-Mode
Clocks
Flags
D
F
I
F
T
F
S
F
Z
F
F
A
F
P
F
C
F
u
u
u
u
u
u
u
u
u
0
Instruction
IDIV Integer (Signed) Divide
Accumulator by Register/Memory
Divisor: Byte
Word
Doubleword
IMUL Integer (Signed) Multiply
Accumulator by Register/Memory
Multiplier: Byte
Word
Doubleword
Register with Register/Memory
Multiplier: Byte
Word
Doubleword
Register/Memory with Immediate to Register2
Multiplier: Byte
Word
Doubleword
Opcode
Cache
Miss
Regl
Cache
Hit
Cache
Miss
Notes
Real
Mode
Protected
Mode
1,4
2,4
1
2
F [011 w][mod 111 rim]
14/15
23/24
40/41
m
u
u
u
u
u
u
u
18
25
44
14/15
23/24
40/41
18
25
44
m
F [011 w] [mod 101 rim]
3/5
3/5
7/9
7
7
13
3/5
3/5
7/9
7
7
13
3/5
3/5
7/9
7
7
13
3/5
3/5
7/9
7
7
13
3/5
3/5
7/9
7
7
13
3/5
3/5
7/9
7
7
13
16
16
16
16
16
16
17
17
1/3
1
5
1/3
1
5
20
20
14/20
6/21
OF AF[mod reg rim]
6 [1 Os1] [mod reg r/m]t
IN Input from 110 Port
Fixed Port
Variable Port
E [01 Ow] [port number]
E [110w]
INC Increment by 1
Register/Memory
Register (short from)
F [111w] [mod 000 rim]
4 [0 reg]
INS Input String from 110 Port
6 [110w]
INT Software Interrupt
INTi
Protected Mode:
Interrupt or Trap to Same Privilege
Interrupt or Trap to Different Privilege
16-Bit Task to 16-bit TSS by Task Gate
16-Bit Task to 32-bit TSS by Task Gate
16-Bit Task to V86 Task by Task Gate
32-Bit Task to 16-bit TSS by Task Gate
32-Bit Task to 32-bit TSS by Task Gate
32-Bit Task to V86 Task by Task Gate
V86 to 16-bit TSS by Task Gate
V86 to 32-bit TSS by Task Gate
V86 to Privilege 0 by Trap Gate/lnt Gate
Reg!
Cache
Hit
~
Protected-Mode
Clocks
u
m
CD[i]
u
u
u
u
u
u
u
m
u
m
u
m
u
m
9
u
1
u
u
u
u
u
u
u
u
u
u
u
m
0
u
u
u
u
u
u
14
16
57
91
265
296
177
241
299
180
241
299
106
58
92
266
320
205
261
343
232
261
343
114
2
1
2,9
1,4
5,6,7,8
g"
:J
~
Table 7-17. Instruction Set (Continued)
Real-Mode
Clocks
Flags
Instruction
Opcode
INT Software Interrupt (Continued)
INT3
CC
0
D
T
F
Z
F
I
F
S
F
F
F
A
F
P
F
C
F
u
m
0
u
u
u
u
u
u
Reg!
Cache
Hit
Cache
Miss
14
16
Protected Mode:
Interrupt or Trap to Same Privilege
Interrupt or Trap to Different Privilege
16-Bit Task to 16-bit TSS by Task Gate
16-Bit Task to 32-bit TSS by Task Gate
16-Bit Task to V86 by Task Gate
32-Bit Task to 16-bit TSS by Task Gate
32-Bit Task to 32-bit TSS by Task Gate
32-Bit Task to V86 by Task Gate
V86 to 16-bit TSS by Task Gate
V86 to 32-bit TSS by Task Gate
V86 to Privilege 0 by Trap Gate/lnt Gate
INTO
If OF == 0
If OF == 1 (INT4)
s-
CI)
==t
~
g.
:::,
~
.....
~
CD
Protected Mode:
Interrupt or Trap to Same Privilege
Interrupt or Trap to Different Privilege
16-Bit Task to 16-bit TSS by Task Gate
16-Bit Task to 32-bit TSS by Task Gate
16-Bit Task to V86 by Task Gate
32-Bit Task to 16-bit TSS by Task Gate
32-Bit Task to 32-bit TSS by Task Gate
32-Bit Task to V86 by Task Gate
V86 to 16-bit TSS by Task Gate
V86 to 32-bit TSS by Task Gate
V86 to Privilege 0 by Trap Gate/lnt Gate
t
=
CE
u
u
m
0
u
u
u
u
Protected-Mode
Clocks
Reg!
Cache
Hit
Cache
Miss
57
91
265
296
177
241
299
180
241
299
106
58
92
266
320
205
261
343
232
261
343
114
1
1
57
91
265
296
177
241
299
180
241
299
106
58
92
266
320
205
261
Notes
Real
Mode
Protected
Mode
1,4
5,6,7,8
u
1
15
1
17
343
232
261
343
114
:j: = 8-bit displacement
§ = 16-bit displacement
~ = 32-bit displacement
m = Flag modified
u = Flag unchanged
1) Exception 13 fault (general protection) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum CS, OS, ES, FS, or GS segment
limit (FFFFh). Exception 12 fault (stack segment limit violation or not present) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum SS limit.
2) Exception 13 fault occurs if the memory operand in CS, OS, ES, FS, or GS cannot be used due to either a segment limit violation or an access rights violation. If a stack limit
is violated, an exception 12 occurs.
3) This is a protected mode instruction. Attempted execution in real mode will result in exception 6 (invalid opcode).
4) An exception may occur, depending on the value of the operand.
5) LOCK# is asserted during descriptor table accesses.
6) All segment descriptor accesses in the GOT or LOT made by this instruction automatically asserts LOCK# to maintain descriptor integrity in multiprocessor systems.
7) JMP, CALL, INT, RET, and IRET instructions referring to another code segment causes an exception 13, if an applicable privilege rule is violated.
8) The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13 fault occurs.
9) An exception 13 fault occurs if CPL is greater than IOPL.
immediate data
Notes:
s-
CI)
==t
~
g.
:::,
~
--..J
N
Table 7-17. Instruction Set (Continued)
~
o
~
Real-Mode
Clocks
Flags
0
Instruction
Opcode
INVD Invalidate Cache
OF08
F
C
F
Regl
Cache
Hit
u
u
u
7
7
u
u
u
5
5
I
F
T
F
S
Z
A
P
F
0
F
F
F
F
u
u
u
u
u
u
u
u
u
u
u
INVLPG Invalidate TLB Entry
OF 01 [mod 111 rim]
u
IRET Interrupt Return
CF
m m m m m m m m m
Real Mode
Protected Mode
Within Task to Same Privilege
Within Task to Different Privilege
16-Bit Task to 16-bit TSS
16-Bit Task to 32-bit TSS
16-Bit Task to V86 Task
32-Bit Task to 16-bit TSS
32-Bit Task to 32-bit TSS
32-Bit Task to V86 Task
u
u
u
u
u
u
u
u
u
72:1=
OF 8211
u
8-Bit displacement
Full displacement
76:1=
OF 8611
JCXZ Jump on CX Zero
E3:1=
JElJZ Jump on Equal/Zero
8-Bit displacement
Full displacement
74:1=
OF 8411
JECXZ Jump on ECX Zero
E3:1=
JUJNGE Jump on Less/Not Greater or Equal
7C:I=
OF 8ClI
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
Real
Mode
Protected
Mode
17
37
78
260
314
203
255
339
226
8
411
512
411
613
411
512
411
613
713
713
411
512
411
613
713
713
411
512
411
613
u
u
CJ)
Cache
Miss
14
16
35
74
259
290
173
235
295
176
JBElJNA Jump on Below or Equal/Not Above
8-Bit displacement
Full displacement
Reg!
Cache
Hit
5""
~
Notes
2,5,6,7,8
14
JB/JNAElJC Jump on Below/Not
Above or EquaVCarry
8-Bit displacement
Full displacement
Cache
Miss
~
Protected-Mode
Clocks
8
8
8
8
8
~
Table 7-17. Instruction Set (Continued)
Real-Mode
Clocks
Flags
Instruction
Opcode
JLElJNG Jump on Less or Equal/Not Greater
8-Bit displacement
Full displacement
7E:j:
OF 8ElI
JMP Unconditional Jump
Short
Direct within Segment
RegisterlMemory Indirect within Segment
Direct Intersegment
Call Gate Same Privilege Level
16-Bit Task to 16-bit TSS
16-Bit Task to 32-bit TSS
16-Bit Task to V86 Task
32-Bit Task to 16-bit TSS
32-Bit Task to 32-bit TSS
32-Bit Task to V86 Task
Indirect Intersegment
Call Gate Same Privilege Level
16-Bit Task to 16-bit TSS
16-Bit Task to 32-bit TSS
16-Bit Task to V86 Task
32-Bit Task to 16-bit TSS
32-Bit Task to 32-bit TSS
32-Bit Task to V86 Task
s-
CI)
2
C)
5"'
::J
~
-....J
~
JNB!JAElJNC Jump on Not Below/
AbbveorEquaVNotCaffY
8-Bit displacement
Full displacement
0
0
S
Z
A
F
I
F
T
F
F
F
F
F
P
F
C
F
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
FF [mod 101 rim]
411
613
4
5
4
6
u
u
u
u
u
u
Real
Mode
1
13
u
Cache
Miss
Notes
Protected
Mode
8
411
512
7/8
9
u
Cache
Miss
Reg!
Cache
Hit
u
EB:j:
E911
FF [mod 100 rim]
EA [full offset, selector]
73:j:
OF 8311
Reg!
Cache
Hit
Protected-Mode
Clocks
10
14
8/9
10
27
45
265
296
182
241
299
185
45
266
320
209
261
343
232
39
47
270
301
184
246
304
187
39
47
271
325
214
268
348
237
u
2,6,7,8
8
411
512
411
613
t =
immediate data
:j: = 8-bit displacement
§ = 16-bit displacement
11 = 32-bit displacement
m = Flag modified
u = Flag unchanged
Notes:
1) Exception 13 fault (general protection) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum CS, DS, ES, FS, or GS segment
limit (FFFFh). Exception 12 fault (stack segment limit violation or not present) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum SS limit.
2) Exception 13 fault occurs if the memory operand in CS, DS, ES, FS, or GS cannot be used due to either a segment limit violation or an access rights violation. If a stack limit
is violated, an exception 12 occurs.
3) This is a protected mode instruction. Attempted execution in real mode will result in exception 6 (invalid opcode).
4) An exception may occur, depending on the value of the operand.
5) LOCK# is asserted during descriptor table accesses.
6) All segment descriptor accesses in the GDT or LDT made by this instruction automatically asserts LOCK# to maintain descriptor integrity in multiprocessor systems.
7) JMP, CALL, INT, RET, and IRET instructions referring to another code segment causes an exception 13, if an applicable privilege rule is violated.
8) The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13 fault occurs.
s-
CI)
~
~
5"'
::J
~
--...J
N
~
Table 7-17. Instruction Set (Continued)
==t
I\:)
Real-Mode
Clocks
Flags
F
0
F
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
u
u
u
u
u
u
u
u
u
0
Instruction
Opcode
JNBElJA Jump on Not Below or Equal/Above
8-Bit displacement
Full displacement
77:\:
OF 8711
JNElJNZ Jump on Not Equal/Not Zero
8-Bit Displacement
Full Displacement
75:\:
OF 8511
JNUJGE Jump on Not Less/Greater or Equal
8-Bit displacement
Full displacement
7D:\:
OF 8011
JNLElJG Jump on Not Less or Equal/Greater
8-Bit displacement
Full displacement
7F:\:
OF 8FlI
JNO Jump on Not Overflow
8-Bit displacement
Full displacement
71:\:
OF 8111
JNP/JPO Jump on Not Parity/Parity Odd
8-Bit displacement
Full displacement
7B:\:
OF 8BlI
JNS Jump on Not Sign
8-Bit displacement
Full displacement
79:\:
OF 8911
JO Jump on Overflow
8-Bit displacement
Full displacement
70:\:
OF 8011
JP/JPE Jump on Parity/Parity Even
8-Bit displacement
Full displacement
7A:\:
OF 8AlI
JS Jump on Sign
8-Bit displacement
Full displacement
78:\:
OF 8811
LAHF Load AH with Flags
9F
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
Regl
Cache
Hit
Cache
Miss
Protected-Mode
Clocks
Reg!
Cache
Hit
Cache
Miss
Real
Mode
Protected
Mode
8
411
512
411
613
411
512
411
613
411
512
411
613
411
512
411
613
411
512
411
613
411
512
411
613
411
512
411
613
411
512
411
613
411
512
411
613
411
512
411
613
2
2
u
8
8
u
8
u
8
u
8
u
8
u
8
u
8
u
8
u
u
a-:::s~
Notes
-
--
- -
~
Table 7-17. Instruction Set (Continued)
Real-Mode
Clocks
Flags
0
s-
~
g:
::,
~
-....J
r\)
w
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
u
u
u
u
u
m
u
u
u
Cache
Miss
Cache
Miss
11/12
14
19
Notes
Real
Mode
Protected
Mode
3
2,5,6,12
22
1
2,6,13
Opcode
LAR Load Access Rights
From RegisterlMemory
OF 02[mod reg rim]
LDS Load Pointer to OS
C5 [mod reg rim]
u
u
u
u
u
u
u
u
u
LEA Load Effective Address
No Index Register
With Index Register
80 [mod reg rim]
u
u
u
u
u
u
u
u
u
LEAVE Leave Current Stack Frame
C9
u
u
u
u
u
u
u
u
u
5
6
5
6
1
2
LES Load Pointer to ES
C4 [mod reg rim]
u
u
u
u
u
u
u
u
u
7
8
20
21
1
2,6,13
LFS Load Pointer to FS
OF B4[mod reg rim]
u
u
u
u
u
u
u
u
u
7
8
20
21
1
2,6,13
LGDT Load GOT Register
OF 01 [mod 010 rim]
u
u
u
u
u
u
u
u
u
9
9
9
9
1,10
2,11
LGS Load Pointer to GS
OF B5[mod reg rim]
u
u
u
u
u
u
u
u
u
7
8
7
8
1
2,6,13
LIDT Load !DT Register
OF 01 [mod 011 rim]
u
u
u
u
u
u
u
u
u
11
11
11
11
1,10
2,11
u
u
u
u
u
u
u
u
u
3
2,5,6,11
u
u
u
u
u
u
u
u
u
1,10
2,11
6
7
2
3
2
3
OF OO[mod 010 rim]
LMSW Load Machine Status Word
From RegisterlMemory
OF 01 [mod 110 rim]
LODS Load String
A [110w]
LOOP Offset Loop/No Loop
E2:t
t =
~
D
F
Reg!
Cache
Hit
Instruction
LLDT Load LOT Register
From RegisterlMemory
CI)
F
Reg!
Cache
Hit
Protected-Mode
Clocks
+
u
----
-_.
---
u
u
u u
L- -
u
_~
u
u
u u
_L.....-
u
u
u
u u
L....--.l-
u
u
u
16/17
18
5
8
5
8
6
6
6
6
~.~
_
~------L-
__
1
~
2
-
-
8
-
immediate data
= 8-bit displacement
§ = 16-bit displacement
11 = 32-bit displacement
m = Flag modified
u = Flag unchanged
Notes:
1) Exception 13 fault (general protection) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum CS, OS, ES, FS, or GS segment
limit (FFFFh). Exception 12 fault (stack segment limit violation or not present) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum SS limit.
2) Exception 13 fault occurs if the memory operand in CS, OS, ES, FS, or GS cannot be used due to either a segment limit violation or an access rights violation. If a stack limit
is violated, an exception 12 occurs.
3) This is a protected mode instruction. Attempted execution in real mode will result in exception 6 (invalid opcode).
4) An exception may occur, depending on the value of the operand.
5) LOCK# is asserted during descriptor table accesses.
6) All segment descriptor accesses in the GOT or LOT made by this instruction automatically asserts LOCK# to maintain descriptor integrity in multiprocessor systems.
7) JMP, CALL, INT, RET, and IRET instructions referring to another code segment causes an exception 13, if an applicable privilege rule is violated.
8) The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13 fault occurs.
9) An exception 13 fault occurs if CPL is greater than IOPL.
10)This instruction may be executed in real mode. In real mode, its purpose is primarily to initialize the CPU for protected mode.
11) An exception 13 fault occurs if CPL is greater than 0 (0 is the most privileged level).
12)Any violation of privilege rules as apply to the selector operand does not cause a Protection exception, rather, the zero flag is cleared.
13) For segment load operations, the CPL, RPL, and OPL must agree with the privolege rules to avoid an exception 13 fault. The segment's descriptor must indicate present or
exception 11 occurs (OS, OS, ES, FS, GS not present). If the SS register is loaded and a stack segment not present is detected, an exception 12 occurs.
s-
CI)
~
~
g.
::,
~
-....J
N
s-
Table 7-17. Instruction Set (Continued)
CI)
::t
~
Real-Mode
Clocks
Flags
F
D
F
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
Reg!
Cache
Hit
u
u
u
u
814
914
814
914
0
Instruction
Opcode
LOOPNZlLOOPNE Offset
EO:f:
u
u
u
u
u
LOOPZlLOOPE Offset
E1:f:
u
u
u
u
u
u
u
u
u
u
u
u
u
u
m
u
u
u
LSL Load Segment Limit
From Register/Memory
OF 03[mod reg rim]
LSS Load Pointer to SS
OF B2[mod reg rim]
u
u
u
u
u
u
u
u
u
LTR Load Task Register
From Register/Memory
OF OO[mod reg rim]
u
u
u
u
u
u
u
u
u
MOV Move Data
Register to Register/Memory
Register/Memory to Register
Immediate to Register/Memory
Immediate to Register (short form)
Memory to Accumulator (short form)
Accumulator to Memory (short form)
Register/Memory to Segment Register
Segment Register to Register/Memory
8 [11 Ow] [mod reg rim]
8 [1 01w] [mod reg rim]
C [011 w] [mod 000 r/m]t .
B [w reg]t
A [OOOw]~
A [001w]~
8E [mod sreg3 rim]
8C [mod reg rim]
MOV Move to/from Control/DebuglTest Registers
Register to CRO/CR2/CR3
CRO/CR2/CR3 to Register
Register to DRO-DR3
DRO-DR3 to Register
Register to DR6-DR7
DR6-DR7 to Register
Register to TR3-5
TR3-5 to Register
Register to TR6-TR7
TR6-TR7 to Register
OF 22[11
OF 20[11
OF 23[11
OF 21 [11
OF 23[11
OF 21 [11
OF 26[11
OF 24[11
OF 26[11
OF 24[11
MOVS Move String
A [01 Ow]
MOVSX Move with Sign Extension
Register from Register/Memory
OF B[111w] [mod reg rim]
MOVZX Move with Zero Extension
Register from Register/Memory
OF 8[011 w] [mod reg rim]
u
u
u
u
u
u
u
u
u
u
u
u
u
u
8
2
4
2
4
2
5
3
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
Real
Mode
~
Protected
Mode
8
8
14/15
17
19
20
16/17
18
1/2
1/2
1/2
1
2
2
15/16
1/3
2
4
2
3
2,5,6,12
3
2,6,13
3
2,5,6,11
1
2,6,13
4
2
18
3
c
11
14/3/3
2/3/3
10
9
10
9
10
11
8
9
u
Cache
Miss
5"
::J
Notes
u
reg]
reg]
reg]
reg]
reg]
reg]
reg]
reg]
reg]
reg]
u
Reg!
Cache
Hit
u
1/2
1/2
1/2
1
2
2
2/3
1/3
u
eee
eee
eee
eee
eee
eee
eee
eee
eee
eee
u
7
Cache
Miss
~
Protected-Mode
Clocks
14/3/3
2/3/3
10
9
10
9
10
11
8
9
5
5
5
5
2/3
5
2/3
5
2/3
5
2/3
5
u
1
2
1
2
1
2
Table 7-17. Instruction Set (Continued)
Real-Mode
Clocks
Flags
s-
~
2"'
:J
~
'-J
N
01
I
F
T
F
S
F
Z
F
A
F
F
P
F
C
F
m
u
u
u
u
u
u
u
m
Opcode
MUL Unsigned Multiply
Accumulator with RegisterlMemory
Multiplier: Byte
Word
Ooubleword
F [011w] [mod 100 rim]
NEG Negate Integer
F [011w][mod 011 rim]
m
u
u
u
m
m
m
m
NOP No Operation
90
u
u
u
u
u
u
u
NOT Boolean Complement
F [011 w] [mod 010 rim]
u
u
u
u
u
u
0
u
u
u
m
m
OR Boolean OR
Register to Register
Register to Memory
Memory to Register
Immediate to RegisterlMemory
Immediate to Accumulator
0[10dw][11 reg rim]
o [1 OOw] [mod reg rim]
o [101 w] [mod reg rim]
8 [OOOw] [mod 001 r/m]t
o [110w]t
OUT Output to Port
Fixed Port
Variable Port
E [011 w] [port number]
E [111w]
OUTS Output String
~
D
F
Instruction
t =
(I)
0
u
*
-
-
_~J111w]
u
u
u
u
u
u
u
u
u
u
u
Regl
Cache
Hit
3/5
3/5
10/9
m
1/3
u
u
1
u
u
u
1/3
m
m
0
u
u
u
u
1
3
3
1/3
1
Cache
Miss
7
7
Protected-Mode
Clocks
Reg!
Cache
Hit
Cache
Miss
Notes
Real
Mode
Protected
Mode
1
2
1
2
1
2
1
2
7
7
14
3/5
3/5
10/9
14
5
1/3
5
1
5
1/3
5
5
5
5
1
3
3
1/3
1
5
5
5
18
18
18
18
14\34
14\34
14\35
14\35
20
20
14\34
14\34
u
u
9
1
2,9
immediate data
= 8-bit displacement
§ = 16-bit displacement
~ = 32-bit displacement
m = Flag modified
u = Flag unchanged
Notes:
1) Exception 13 fault (general protection) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum CS, OS, ES, FS, or GS segment
limit (FFFFh). Exception 12 fault (stack segment limit violation or not present) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum SS limit.
2) Exception 13 fault occurs if the memory operand in CS, OS, ES, FS, or GS cannot be used due to either a segment limit violation or an access rights violation. If a stack limit
is violated, an exception 12 occurs.
3) This is a protected mode instruction. Attempted execution in real mode will result in exception 6 (invalid opcode).
4) An exception may occur, depending on the value of the operand.
5) LOCK# is asserted during descriptor table accesses.
6) All segment descriptor accesses in the GOT or LOT made by this instruction automatically asserts LOCK# to maintain descriptor integrity in multiprocessor systems.
7) JMP, CALL, INT, RET, and IRET instructions referring to another code segment causes an exception 13, if an applicable privilege rule is violated.
8) The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13 fault occurs.
9) An exception 13 fault occurs if CPL is greater than IOPL.
10) This instruction may be executed in real mode. In real mode, its purpose is primarily to initialize the CPU for protected mode.
11 )An exception 13 fault occurs if CPL is greater than 0 (0 is the most privileged level).
12)Any violation of privilege rules as apply to the selector operand does not cause a Protection exception, rather, the zero flag is cleared.
13) For segment load operations, the CPL, RPL, and OPL must agree with the privolege rules to avoid an exception 13 fault. The segment's descriptor must indicate present or
exception 11 occurs (OS, OS, ES, FS, GS not present). If the SS register is loaded and a stack segment not present is detected, an exception 12 occurs.
s-
(I)
~
?5
2"'
:J
~
"'..J
'"
s-
Table 7-17. Instruction Set (Continued)
CI)
::;-
0'>
Real-Mode
Clocks
Flags
Instruction
Opcode
POP Pop Value off Stack
Register/Memory
Register (short form)
Segment Register (ES, CS, SS, DS)
Segment Register (ES, CS, SS, DS, FS, GS)
8F [mod 000 rim]
5 [1 reg]
[000 sreg2 110]
OF [10 sreg3 001]
POPA Pop All General Registers
61
POPF Pop Stack into Flags
9D
0
0
F
u
Z
F
S
F
u
u
T
F
I
F
u
u
F
A
F
P
F
C
F
u
u
u
u
~
Protected-Mode
Clocks
Reg!
Cache
Hit
Cache
Miss
Regl
Cache
Hit
Cache
Miss
3/5
3
8
8
4/5
4
9
9
3/5
3
8
8
4/5
4
9
9
5::::J
Notes
Real
Mode
Protected
Mode
1
2,6,13
u
u
u
u
u
u
u
u
u
18
18
18
18
1
2
4
5
4
5
1
2,14
m
m
m
m
m
m
m
m
m
,. u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
PREFIX BYTES
Assert Hardware LOCK Prefix
Address Size Prefix
Operand Size Prefix
Segment Override Prefix:
CS
DS
ES
FS
GS
SS
2E
3E
26
64
65
36
PUSH Push Value onto Stack
Register/Memory
Register (short form)
Segment Register (ES, CS, SS, DS)
Segment Register (ES, CS, SS, DS, FS, GS)
Immediate
FF [mod 110 rim]
5 [0 reg]
[000 sreg2 11 0]
OF [10 sreg3 000]
6 [10s0]t
PUSHA Push All General Registers
60
u
u
u
u
u
u
u
u
PUSHF Push Flags Register
9C
u
u
u
u
u
u
u
RCL Rotate Through Carry Left
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
m
u
u
u
u
u
u
D [OOOw] [mod 010 rim]
D [001 w] [mod 010 rim]
C [OOOw] [mod 010 r/m]t
RCR Rotate Through Carry Right
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
D [OOOw] [mod 011 rim]
D [001w] [mod 011 rim]
C [OOOw] [mod 011 r/m]t
9
FO
67
66
m
u
u
u
u
u
u
-'-----
1
2
17
1
2
2
2
1
2
1
2
10
10
10
9/9
9/9
9/9
10
10
10
1
2
10
10
10
9/9
9/9
9/9
10
10
10
2/4
2
2
2
2
4
2
2
2
2
2/4
2
2
2
2
4
2
2
2
2
u
17
17
17
u
u
2
2
u
m
9/9
9/9
9/9
9/9
9/9
9/9
u
-
m
-
-
--
-
-
-
-
-
-
~
Table 7-17.
Instruction Set (Continued)
~
8"'
::J
~
-....J
N
-....J
I
F
T
F
S
F
Z
F
F
A
F
P
F
C
F
Reg!
Cache
Hit
Cache
Miss
Reg!
Cache
Hit
Cache
Miss
Real
Mode
Protected
Mode
REP INS Input String
F26[110w]
u
u
u
u
u
u
u
u
u
20+9n
20+9n
5+9n\
18+9n
5+9n\
19+9n
1
2,9
REP LOOS Load String
F2 A[110w]
u
u
u
u
u
u
u
u
u
4+5n
4+5n
4+5n
4+5n
1
2
REP MOVS Move String
F2 A[010w]
u
u
u
u
u
u
u
u
u
5+4n
5+4n
5+4n
5+4n
1
2
REP OUTS Output String
F26[111w]
u
u
u
u
u
u
u
u
u
20+4n
20+4n
5+4n\
18+4n
5+4n\
19+4n
1
2,9
REP STOS Store String
F2 A[101w]
u
u
u
u
u
u
u
u
u
3+4n
3+4n
3+4n
3+4n
1
2
REPE CMPS Compare String
(Find nonmatch)
F3 A[011w]
m
u
u
u
m
m
m
m
m
5+8n
5+8n
5+8n
5+8n
1
2
REPE SCAS Scan String
(Find non-AUAXlEAX)
F3 A[111w]
m
u
u
u
m
m
m
m
m
4+5n
4+6n
4+5n
4+6n
1
2
REPNE CMPS Compare String
(Find match)
F2 A[011w]
m
u
u
u
m
m
m
m
m
5+8n
5+8n
5+8n
5+8n
1
2
u
u
u
m
m
m
--
-
t =
s-
0
F
Opcode
--
t:t
0
Notes
Instruction
REPNE SCAS Scan String
(Find AUAXlEAX)
CI)
Protected
Mode Clocks
Real-Mode
Clocks
Flags
-
--
-
F2 A[111w]
-
+
-
-
-
--
--
m
----
------
--
m
-
m
--
-
-
4+5n
____
__
4+6n
_1 __ -
----
4+5n
-
---
---
1
4+6n
----
----
-
L-
_
2
-
-
-
immediate data
= 8-bit displacement
§ = 16-bit displacement
~ = 32-bit displacement
m = Flag modified
u = Flag unchanged
Notes:
1) Exception 13 fault (general protection) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum CS, OS, ES, FS, or GS segment
limit (FFFFh). Exception 12 fault (stack segment limit violation or not present) occurs in real mode if an operand reference is made that partially orfully extends beyond the maximum SS limit.
2) Exception 13 fault occurs if the memory operand in CS, OS, ES, FS, or GS cannot be used due to either a segment limit violation or an access rights violation. If a stack limit
is violated, an exception 12 occurs.
3) This is a protected mode instruction. Attempted execution in real mode will result in exception 6 (invalid opcode).
4) An exception may occur, depending on the value of the operand.
5) LOCK# is asserted during descriptor table accesses.
6) All segment descriptor accesses in the GOT or LDT made by this instruction automatically asserts LOCK# to maintain descriptor integrity in multiprocessor systems.
7) JMP, CALL, INT, RET, and IRET instructions referring to another code segment causes an exception 13, if an applicable privilege rule is violated.
8) The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13 fault occurs.
9) An exception 13 fault occurs if CPL is greater than IOPL.
10) This instruction may be executed in real mode. In real mode, its purpose is primarily to initialize the CPU for protected mode.
11) An exception 13 fault occurs if CPL is greater than 0 (0 is the most privileged level).
12)Any violation of privilege rules as apply to the selector operand does not cause a Protection exception, rather, the zero flag is cleared.
13)For segment load operations, the CPL, RPL, and OPL must agree with the privolege rules to avoid an exception 13 fault. The segment's descriptor must indicate present or
exception 11 occurs (OS, OS, ES, FS, GS not present). If the SS register is loaded and a stack segment not present is detected, an exception 12 occurs.
14)The IF bit of the flag register is not updated if CPL is greater than IOPL. The IOPL and VM fields of the flag register are updated only if CPL = O.
s-
CI)
t:t
~
8"'
::J
~
......
-...J
N
s-
Table 7-17. Instruction Set (Continued)
CI)
ex:>
~
Real-Mode
Clocks
Flags
I
F
T
F
S
F
Z
F
D
F
u
u
u
u
u
0
Instruction
RET Return from Subroutine
Within Segment
Within Segment Add Immediate to SP
Intersegment
Intersegment Add Immediate to SP
Protected Mode: Different Privilege Level
Interseg ment
Intersegment Add Immediate to SP
ROL Rotate Left
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
ROR Rotate Right
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
Opcode
F
A
F
P
F
C
F
u
u
u
u
10
10
13
13
C3
C2§
CB
CA§
o [OOOw] [mod 000 rim]
o [001 w] [mod 000 rim]
m
u
u
u
u
u
u
u
m
u
u
u
u
u
u
u
Cache
Miss
13
13
Reg!
Cache
Hit
Cache
Miss
10
10
26
26
26
27
69
69
72
72
\
m
C [OOOw] [mod 000 r/m]t
o [OOOw] [mod 001
o [001 w] [mod 001
Regl
Cache
Hit
Protected-Mode
Clocks
2/4
3/5
2/4
6
7
6
2/4
3/5
2/4
6
7
6
2/4
3/5
2/4
6
7
6
2/4
3/5
2/4
6
7
6
m
rim]
rim]
C [OOOw] [mod 001 r/m]t
?5
g"
::J
Notes
Real
Mode
Protected
Mode
1
2,5,6,7,8
1
2
1
2
RSDC Restore Segment Register and
Descriptor
OF 79 [mod sreg3 rim]
u
u
u
u
u
u
u
u
u
14
14
15
15
RSLDT Restore LDTR and Descriptor
OF 78 [mod 000 rim]
u
u
u
u
u
u
u
u
u
14
14
15
15
RSM Resume from SMM Mode
oFAA
u
u
u
u
u
u
u
u
u
76
76
15
15
15
15
RSTS Restore TSR and Descriptor
OF 70 [mod 000 rim]
u
u
u
u
u
u
u
u
u
14
14
SAHF Store AH in Flags
9E
u
u
u
u
m
m
u
m
m
2
2
SAL Shift Left Arithmetic
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
o [OOOw] [mod 100 rim]
o [001w] [mod 100 rim]
m
u
u
u
m
m
u
m
m
SAR Shift Right Arithmetic
Register/Memory by 1
Register/Memory by CL
Register/Memory by Immediate
C [OOOw] [mod 100 r/m]t
o [OOOw] [mod 111
o [001 w] [mod 111
rim]
rim]
C [OOOw] [mod 111 r/m]t
m
u
u
u
m
m
m
m
2/4
3/5
2/4
6
7
6
2/4
3/5
2/4
6
7
6
2/4
3/5
2/4
6
7
5
2/4
3/5
2/4
6
7
8
m
~
Table 7-17.° Instruction Set (Continued)
Real-Mode
Clocks
Flags
Instruction
Opcode
SBB Integer Subtract with Borrow
Register to Register
Register to Memory
Memory to Register
Immediate to RegisterlMemory
Immediate to Accumulator (short form)
1 [10dw] [11 reg rim]
1 [100w] [mod reg rim]
1 [101w] [mod reg rim]
8 [OOsw] [mod 011 r/mlt
1 [110w]t
SCAS Scan String
A [111w]
SETB/SETNAEISETC Set Byte on Below/
Not Above or Equal/Carry
To RegisterlMemory
SETBEISETNA Set Byte on Below or Equal/
Not Above
To RegisterlMemory
SETEISETZ Set Byte on Equal/Zero Register/
Memory
SETUSETNGE Set Byte on Less/
Not Greater or Equal
To RegisterlMemory
s-
CI)
~
~
g.
:J
~
""-I
N
select
set ARR4 SMM base address upper bits
write value
index ARR4 SMM base address bits <15-12>
and 4 bits for SMM size
set SMM lower address bits and SMM size
write value
SMM Programmer's Guide
A-11
SMM Instruction Summary and Macros
A.7 SMM Instruction Summary and Macros
The TI486SXL(C) microprocessor responds to seven instructions when it is in
SM mode that are not standard instructions. The seven instructions include:
o
o
o
o
Two that save and restore a segment register and its descriptor
Two that save and restore the task register
Two that save and restore the LDT register
One that exits SM mode
The instructions that save and restore registers are needed because the CPU
saves a minimum amount of information in the SM header (for speed). If one
or more of the segment registers in the SM interrupt handler needs to be modified, the previous values need to be preserved as they are not automatically
saved in the header. The instructions that save and restore segment registers
are provided for this purpose. Similarly, the instructions that save and restore
the Task register and LDT register allow creation of an SM interrupt handler
that enters protected mode and acts as a task dispatcher.
The seven SM instructions summarized in Table A-5 are valid only when CPL
is 0 and either:
A-12
o
The SMAC, SMI, and SM4 bits are set and a valid SMM region is defined
(the SMM size defined to be greater than 0).
o
The SMI# pin is driven low by the CPU. (The CPU drives SMI# low after
it recognizes the SMI interrupt and continues to drive it low until RSM is
executed. See Figure A-1 page A-5.)
SMM Instruction Summary and Macros
Table A-S. SMM Instruction Set with Clock Counts
Instruction Mnemonic Opcode
Clocks Description
rsdc
rsCseg
OF 79
14
Restores a segment register from
an a~-bit memory location. t
rsldt
rstJdt
OF 78
14
Restores the local-descriptortable register from an aD-bit
memory location. t
rsts
rsCtr
OF7D
14
Restores the task register from an
aD-bit memory location.t
svdc
OF7a
22
Saves a segment register at an
aD-bit memory location.:j:
svldt
OF7A
22
Saves the local-descriptor-table
register at an aD-bit memory location.:j:
svts
OF7C
22
Saves the task register at an
aD-bit memory location.:j:
OFAA
5a
Restores the state of the CPU
from the data saved in the header
at the top of SM memory (the
header is created by the processor when it recognizes an SMI).
This instruction takes the processor out of 8M mode and returns it
to the task that was executing
when the 8MI occurred.
rsm
exiCsm
t The restore includes the descriptor information that is not visible to applications.
:j: The save includes the descriptor information that is not visible to applications.
The values in the second column in Table A-5, titled Mnemonic, are arbitrary
since there is no current assembler support for the SM instructions. That
means that the code will probably be generated manually. In generating the
code other arbitrary names may be preferred. The names shown in the first
column of Table A-5 are the instruction names that have been added to the
TI486SXL(C) instruction set. The mnemonics are a bit more descriptive and
are used in the example macros, Example A-3. These examples for generating SM instruction code have been rewritten from earlier versions.
The third column in Table A-5 provides the basic opcode for the SM instructions. In addition to these basic codes, the first six SM instructions listed can
be prefixed with a segment override and/or an address size override, and they
require a mod rim byte and a memory offset.
The include file shown in Example A-3 contains some macros that will be useful within an SM interrupt handler. These macros implement versions of the
seven special 8M instructions shown in Table A-5. These macros can be used
as is, or modified to suit the particular application.
SMM Programmer's Guide
A-13
SMM Instruction Summary and Macros
Macros That Implement the Special SM Instructions
Example A-3.
COMMENT
A
File: SM.MAC
Copyright (c) 1994 Texas Instruments, Incorporated
This include file defines a set of macros for generating System Management (SM)
mode instruction opcodes, since no assembler directly supports these SM
instructions.
There are six SM instructions that are used to save and restore registers that
are not automatically saved when SM mode is entered, and one instruction for
exiting from SM mode. These instructions support many addressing modes, but
the macros in this file only implement one mode--a 16-bit memory reference
(within the code segment as a CS: override is also used). These macros could
be made much more complex to allow other addressing modes, but the additional
complexity wouldn't provide much useful benefit.
Each of the macros that implements a register save or restore takes as a
parameter an offset in the code segment where the register should be saved to
or restored from. The two macros that save and restore segment registers also
take the name of a segment register as a parameter.
Here is a small portion of code that shows how the macros in this file are used:
«««< BEGIN EXAMPLE CODE »»»>
• CODE
smi_entrYJ>oint:
A-14
sav_seg
sav_seg
sav_seg
sav_seg
sav_seg
sav_Idt
sav_tr
mov
mov
old_ds,ds
old_es,es
old_fs,fs
old_gs,gs
old_ss,ss
old_Idt
old_tr
dword ptr cs:old_eax,eax
cs:old_ebx,ebx
rst_seg
rst_seg
rst_seg
rst_seg
ds, old_ds
es,old_es
fs,old_fs
gs,old_gs
Save segment registers
Save LDTR and TR
Save other registers
Restore segment registers
SMM Instruction Summary and Macros
old_ds
old_es
old fs
old_gs
old ss
old tr
old ldt
old eax
old ebx
rst_seg
rst - ldt
rst- tr
mov
mov
exit- sm
ss, old_ss
old_ ldt
old_tr
eax,dword ptr cs:old_eax
ebx,dword ptr cs:old_ebx
dt
dt
dt
dt
dt
dt
dt
dd
dd
?
?
?
?
?
?
?
?
?
Restore LDTR and TR
Restore other registers
Exit SM interrupt handler
10 bytes in code segment
«««< END EXAMPLE CODE »»»>
NOTE: The location at addr must be 10 bytes in size and it must reside
within the code segment. It should be defined as:
iaddr
dt
?
sav_seg MACRO
SMMac
ENDM
addr, reg
sav_seg, addr, reg, 78h
Save one of the segment registers
rst_seg MACRO
SMMac
ENDM
reg, addr
rst_seg, addr, reg, 79h
Restore one of the segment registers
sav_ldt MACRO
SMMac
ENDM
addr
sav_ldt, addr, ldt, 7Ah
Save the LDT register
rst_ldt MACRO
SMMac
ENDM
addr
rst_ldt, addr, ldt, 7Bh
Restore the LDT register
sav_ts
MACRO
SMMac
ENDM
addr
sav_ts, addr, ts, 7Ch
Save the Task register
rst_ts
MACRO
SMMac
addr
rst_ts, addr, ts, 7Dh
Restore the Task register
SMM Programmer's Guide
A-15
SMM Instruction Summary and Macros
ENOM
exit_smMACRO
OB
Exit from SM mode
OOFh, OAAh
ENOM
SMMac
MACRO
mname, addr, reg, op
; CS: override and SM instruction opcode
db
2Eh
db
OFh, op
; mod rim byte
,
ifidni
db
OOEh
,
elseifidni
db
01Eh
,
elseifidni
db
026h
,
elseifidni
db
02Eh
,
elseifidni
db
016h
,
elseifidni
db
006h
elseifidni
,
db
006h
,
elseifidni
db
006h
else
ECHO ERROR in
ECHO Register
ECHO Register
ECHO or LOT
• ERR
endif
; 16-bit displacement
dw
offset addr
EN OM
A-16
macro :
parameter unknown:
parameter must be either CS, OS, ES, FS, GS, SS, TS,
SMI Handler Example
A.S SMI Handler Example
This section contains fragments of typical coding found in 8MI handlers.
Example A-4.
Typical Coding Found In 8MI Handlers
5MBASE= OC8000H
SMSIZE= 2
SMEND = SMSIZE SHL (SMSIZE-l)
; base address of SMM space
; SMM space size is 8k bytes
;works for most cases
INCLUDE SM.MAC
.MODEL SMALL
.386P
. CODE
;see Section Example A-3, page A-14
COMMENT "Execution begins here in real mode, with CS defined at the 5MBASE and EIP=O
public smi_start
smi_start:
jmp
$skipdata
EAXsave
dd
DSsave
dt
DStemp
db
$skipdata:
mov
sav_seg
rst_seg
;skip data area, makes it easy for
; assembler
?
?
Offh, Offh, 0,0,0,92h,8fh,0,0,0
;4gig present segment
dword ptr cS:[EAXsave],eax; save EAX
[DSsave], ds
save DS
ds,[DStemp]
; setDS
COMMENT "We need to extend the limits of DS so that we don't get a fault when we use it to access low memory. It may be not present with a limit of 0, and these values won't be
changed when we set it using a real mode load.
;Determine Why Are We In The SMI Handler
COMMENT "chipset/Core logic unique instructions will follow. The chipset will be used to determine what caused the SMM interrupt to occur. The BIOS could also "jump" to this point
in the SMM region.
Decision Tree:
a)
If timer, go to timer_expired
b)
If port i/o occurred to a trapped location, go to port_io_caused
c)
If the cpu was turned off, go to cpu_turned_off
; timer_expired;
SMM Programmer's Guide
A-17
8MI Handler Example
COMMENT A
A chipset timer has expired. Unique code would appear to determine which timer. Depending on the purpose of the timer the handler could;
1)
2)
3)
4)
5)
Reduce the clock frequency
Execute a halt instruction and enter suspend mode
Turn current off to the CPU
Turn off a peripheral device
Reset the timer and increment a counter
reduce clock:
COMMENT A
To go to a lower CPU current requirement the CPU clock can be reduced. The CPU clock
can be reduced from its current setting to a lower value. That value could be zero.
Since the CPU is a static device and will maintain the state of all its registers in
the absence of a clock input there is no state saving requirement. It is assumed that
by writing to the chipset it will reduce or zero the clock. If the clock is stopped
then the next instruction to be executed will be one in this SMI handler immediately
following the point where the chipset turned the clock off.
jmp
end_timer:
execute halt:
COMMENT A
To go to a lower CPU current consumption the SMI handler will now execute a HLT
instruction. The HLT instruction will put the CPU into a low power sleep mode until a
non-SMI interrupt occurs. Interrupt(s) will need to be enabled to permit the interrupt
to wake-up the CPU. A common choice would be the keyboard interrupt. A flag would need
to be set in main memory to indicate that the SMI handler should be jumped into or SMI
created, to permit it to restore the state/context of the CPU, prior to the halt for
servicing the interrupt. The interrupt in low memory must point to the BIOS handler
for the return to be made to the SMI handler. An interrupt handler in SMM space could
also service the interrupt rather than a BIOS routine.
;[ Alternatively the chipset could pull the SUSP# CPU pin low to enter
;[ suspend mode. The chipset would have to pull SUSP# high to exit]
;[ suspend mode. ]
:To be sure that BIOS will get control on intr
;check for keyboard interrupt vector pointing to BIOS
;if not BIOS, save existing and set to BIOS vector or jump to can_not_halt
;Set a flag in main memory indicating SMI HALT executed
;If an SMM space interrupt handler is used then IDTR and/or the vector
;would need to be updated to the SMM space routine.
mov ax, 0
point to bottom segment
mov ds, ax
; ds segment is now in main memory
mov [485], 1
; set BIOS flag in main memory
;
hlt
; last instruction executed here
;
nop
;CPU state will not be correct at interrupt
A-18
SMI Handler Example
set bit in main memory to indicate to the BIOS that SMI handler
turned power off to CPU and CPU state should be restored by
the SMI handler
mov ax, 0
mov ds, ax
mov [485], 1
point to bottom segment
ds segment is now in main memory
set BIOS flag in memory
(save entire CPU state. See Restore CPU state label)
(chipset specific instructions to be executed to remove power to
cpu)
jmp end_timer
turn_off-peripheral:
chipset specific instructions to turn off peripheral and enable
chipset 1/0 trapping of the devices io range or enable timer
to allow polling of peripheral requirements.
jmp end_timer
reset_timer:
chipset specific instructions to be executed to reset a timer and
possibly increment a counter to maintain number to time out occurred
for a particular device.
jmp end timer
jmp done
port io caused:
COMMENT "The SMM support for 1/0 being interrupted provides information that permits the restarting of the 1/0 instruction without investigating the actual code where the
instruction is located.
Many things can be done at this point beyond turning on a powered down peripheral. The
CPU clock could now be speeded up in anticipation of heavy CPU processing requirements, timers could be reset, etc.
;** Restart the interrupted instruction
eax,dword ptr [SMEND+SMI_PREVIOUSIP]
mov
dword ptr [SMEND+SMI_NEXTIP],eax
mov
al,byte ptr cs:[SMEND+SMI_BITS]
mov
;test for REP instruction
;rep instruction?
bt
al,2
; (result to Carry)
ecx,O
;if so, increment ecx
adc
;test bit 1 to see
test
al,1 shl 1
;if an OUTS or INS
jnz
SMM Programmer's Guide
A-19
8MI Handler Example
COMMENT . .
** A port read (INx) instruction caused the chipset to generate an SMI instruction. Restore EDI saved by SMI microcode.
edi, dword ptr cs:[SMEND+SMI_EDIESI]
common!
mov
jmp
out_instr:
COMMENT . .
** A port write (OUTx) instruction caused the chipset to generate an SMI
instruction. Restore ESI saved by SMI microcode.
mov
common!:
jmp
esi, dword ptr cs:[SMEND+SMI_EDIESI]
done
COMMENT . .
This handler turned off the current to the cpu. Before it did, the handler set a bit
in main memory or battery-backed-up CMOS indicating that this event happened. At reset, BIOS will determine that this was the case and "jump" into the SMI handler. SMI
handler will then restore the entire state/context of the CPU prior to current being
removed. The bit in main memory would also be cleared indicating that the SMI handler
had removed current.
mov
mov
mov
mov
mov
A-20
ax, 0
ds, ax
[485] , 0
ax, cs
ds, ax
point to bottom segment
ds segment is now in main memory
clear BIOS flag in main memory
restore ds to SMM area
SMI Handler Example
{Restore Complete CPU State}
eax
ebx
ecx
edx
edi
esi
ebp
esp
cs
iuse rst _seg
ds
iuse rst_seg
ss
;use rst_seg
es
iuse rst_seg
fs
;use rst_seg
gs
;use rst _seg
ldtr
gdtr
idtr
tr
eflags
crO
cr2
cr3
drO
drl
dr2
dr3
dr6
dr7
ccrO
ccrl
ccr2
Save the configuration registers with index C3h through FFh
for future product compatibility
arrl
arr2
arr3
arr4
jmp done
done:
mov
rst_seg
exit_sm
eax,cs:[EAXsave]
ds,[DSsave]
return
SMM Programmer's Guide
A-21
Loading SMM Memory With an SMM Program from Main Memory
A.9 Loading SMM Memory With an SMM Program From Main Memory
To load SMM memory with an SMI interrupt handler it is important that the SMI
interrupt does not occur before the handler is ready to accept it. This can be
done by not having SMAC = 0 and SMI = 1 (in the CCR1 register) before the
SMI handler is installed. It is necessary to set SM4 = 1 (in the CCR1 register)
and ARR4 with appropriate values before using the SMM memory. To load
SMM memory with a program it is first necessary to enable SMM with the exception of the SMI# pin by setting SMAC. (See Section A.6, Enabling SMM,
page A-11.) The SMM region is then mapped over main memory at the same
location. This is done by the generation of SMADS# for memory access for the
SMI. A REP MOV instruction can then be used to transfer the program to the
location. Then, turn off SMAC to activate potential SMls.
Example A-S.
• MODEL
8MI Handler Routine
MEDIUM
• STACK
MACROS
iodlay_ macro
jcxz
jcxz
enclm
$+2
$+2
segcs_ macro
db
enclm
02Eh
Short delay for 1/0 operations
CS: override prefix
include SM.MAC
See Example A-3 page A-14
• CODE
=============================================================================
S M I
HAN D L E R R 0 UTI N E
=============================================================================
When an SM interrupt occurs, the code segment base is set to the SM area
start as defined in ARR4, and the IP is set to O. This means the first SM
handler instruction must be at offset O--that is why this loader program
begins with the SM handler code. The offsets referenced in the SMI portion
of this program will be correct in SM mode as well.
A-22
Loading SMM Memory With an SMM Program from Main Memory
smi_code_start:
Save DS, ES, TS, LDT, AX, and ex (only AX and ex are used by the handler--the
other registers are only saved to show how the macros are used).
sav_seg
sav_seg
sav_tr
sav_Idt
mov
mov
old_ds, ds
old_es, es
old_tr
old_Idt
dword ptr cs:old_eax, eax
dword ptr cs:old_ecx, ecx
The main handler code goes here •.• The code below simply writes a down
count to port 80--your code will be much more complex and useful.
; Write port 80 values
mov
aI, OFFh
out
mov
loop
dec
jnz
80h, al
cx, 8FFFh
$
al
dec loop
decloop:
Delay
Restore registers saved at start of handler, then exit from SM mode.
rst_seg
rst _ seg
rst - tr
rst - ldt
mov
mov
exit sm
ds, old ds
es, old es
old- tr
old- ldt
eax, dword ptr cs:old eax
ecx, dword ptr cs:old ecx
Exit SM mode--resume the interrupted
program
smi- code- end:
The locations below are for saving registers that are used in the SM! routine
but are not automatically saved when an SM interrupt occurs. Some of the
registers saved below are not actually used by the code in this example, but
they are saved/restored just to demonstrate how the 8M macros shown earlier
are used.
SMM Programmer's Guide
A-23
Loading SMM Memory With an SMM Program from Main Memory
old_ds
old_es
old_tr
old_Idt
old_eax
old_ecx
dt
dt
dt
dt
dd
dd
?
?
?
?
?
?
========================================~============= =======================
PRO C E D U RES
USE D
B Y
THE
LOA D E R
=============================================================================
=============================================================================
Read a value from a register in AL via I/O ports 22 and 23. Return the value
in AL.
=============================================================================
near
out
22h, al
iodlay_
in
aI, 23h
ret
=============================================================================
Write the value in AH to a register in AL via I/O ports 22 and 23.
============================.=================================================
w22 23 proc
near
-
22h, al
out
iodlay_
mov
aI, ah
23h, al
out
ret
w22 - 23
endp
LOADER
E N TRY
POI N T
=============================================================================
entry~oint:
Set ARR4 registers for 64K SMM area at OOOAOOOO:
mov
call
mov
call
A-24
ax, OOCDh
w22_23
ax, OACEh
w22_23
ARR4
OOOA05
Loading SMM Memory With an SMM Program from Main Memory
mov
call
ax, 05CFh
w22_23
Set ARR4 control bit in CCRI to make ARR4 == SMM memory. Set SMI enable bit
and SMAC bit to allow non-CS-based data writes to go to the SM area.
mov
call
or
mov
mov
call
al, OClh
r22_23
al, 86h
ah, al
al, OClh
w22 - 23
SM4=1; SMAC
1; SMI
1
Copy SMI code to AOOO:OOOO
xor
mov
mov
mov
mov
mov
ax,
si,
di,
ax,
es,
ex,
ax
ax
SMI code starts at offset o of this CS
ax
and offset 0 of SM memory too.
OAOOOh
SM memory segment
ax
offset smi _code_end; Number of bytes of SM handler
code
segcs_
rep
movsb
Copy from EXE memory space to SM mem
The SM handler is now in place.
Disable access to SM memory leaving the SMI
bit set, so that SM interrupts can now occur.
mov
call
and
mov
mov
call
al,
r22 al,
ah,
al,
w22 -
OClh
23
OFBh
al
OClh
23
SMAC
0
Exit to DOS
mov
int
END
ax, 04cOOh
21h
entry-point
SMM Programmer's Guide
A-25
Detection of a TI Microprocessor
A.10 Detection of a TI Microprocessor
It is possible, with a small amount of code, to detect if the CPU is a TI microprocessor and if the CPU is the TI486SXL(C) family or a TI486xLC/E family. The
following assembler code accomplishes this task.
Example A-6.
Detection of a TI Microprocessor
~Purpose:
~To
~To
To detect if the CPU is Texas Instruments microprocessor, and then
determine if it is a TI486SXLC Family.
detect if Texas Instruments:
The undefined flags of the TI microprocessor remain unchanged
following a divide. An Intel part will modify some of the
undefined flags. Check by saving the flags, do a divide, and~
then compare the new flags with the old flags.
detect if TI486SXLC Family:
The cache test registers in the TI486SXLC Family differ from the
TI486xLCE due to the difference in cache size. Bit 9 in TR4 is
used to determine if the processor is of the TI486SXLC Family by
seeing if it can be toggled.
The code that follows is a procedure that returns the CPU detected
in AX .
• MODEL SMALL
.486P
~Values that code will return in AX:
CPU_Not TI
EQU
0
CPU_TI486xLCE EQU
1
CPU_TI486SXLC EQU
2
TR5_Write
TR5_Read
CR
LF
EQU
EQU
EQU
EQU
. CODE
DetectCPU
StartDetect:
PROC
1
2
OAh
ODh
~NOTE:
This procedure returns a value in AX.
Value in BX is destroyed and not saved.
Value in top-half of EAX is destroyed.
CLI
AreWeTI486:
~Assume
A-26
MOV
CMP
that CPU is at least a 386 CPU.
AX,
0
~ set flags to known value
AX,
AX
PUSHF
POP
MOV
AX
flags_before,
MOV
MOV
MOV
DIV
AX, dividend
DX,
0
BX,
divisor
BX
~save
old flags
AX
setup for DIV instruction
Detection of a TI Microprocessor
isave new flags
PUSHF
POP
MOV
AX
flags_after, AX
MOV
AND
MOV
AND
AX,
AX,
BX,
BX,
CMP
JNZ
AX, BX
NotTI
flags_mask
flags_before
flags_mask
flags_after
iisolate bits we are interested in and compare
iflags same before and after?
inO - don't have TI CPU
WeAreTI486:
iNow check to see if CPU is TI486xLCE or TI486SXLC
MOV
MOV
MOV
EAX, 0200h
TR4, EAX
EAX, TR5_Write
MOV
MOV
MOV
MOV
AND
CMP
JNE
TR5, EAX
EAX. TR5 Read
TR5, EAX
EAX, TR4
EAX, 0200h
EAX, 0200h
FoundTI486SXLC
iattempt to set bit 9 of TR4
imust do write,
ithen read operation on test registers
iread TR4 back
iisolate bit 9
idid it stay set?
ino - found TI486SXLC
FoundTI486xLCE:
iCPU is a TI486xLCE
MOV
AX, CPU_TI486xLCE
JMP
Done
FoundTI486SXLC:
iCPU is TI486SXLC
MOV
AX, CPU_TI486SXLC
JMP
Done
NotTI:
iCPU is not a TI486
MOV
AX, CPU_NotTI
Done
JMP
Done:
ileave return value in AX
RET
DetectCPU
ENDP
• DATA
flags_before
flags_after
flag_mask
dividend
divisor
result
DW
DW
DW
DW
DW
DW
?
?
08D5h
OFFFFh
4h
0
END
SMM Programmer's Guide
A-27
Detection of SMM Capable Version
A.11 Detection of SMM Capable Version
At power-up/reset the EDX register contains part type and stepping information as shown in Table A-6.
Table A-6. EDX Register Data At Power-Up/Reset
EDX
Stepping
SMM Available
0410h
A
No
0411h
B
Yes
The following technique can be used to identify the stepping of a TI486SXL(C)
microprocessor after the reset information in EDX is lost. The method uses two
functions: the mixed C and assembler function isbO and assembly language
illegal opcode handler interrupt handler ilLop. The function isbO returns a 1
to indicate when a B step part is present, 0 otherwise. The function isbO installs
an illegal opcode handler, ilLop. Then isbO sets up conditions to execute an
SMM segment save instruction, SVDC. If an A step part is present the illegal
opcode handler is invoked. The ilLop process then modifies the return address on the stack to return to the instruction after the SVDC instruction. The
storage location used by the SVDC instruction is then checked to see if it
changed. If it has changed, the part being tested is a B step part. This detection
technique must be run at protection ring O.
Example A-7.
Detection of SMM Capable Version
11**************************************************** ***********************
11********************************* isb.c ***********************************
11**************************************************** ***********************
#define TRUE 1
#defube FALSE 0
int old_off;
int old_seg;
extern ill_op();
11**************************************************** ***********************
Function: isb ()
II
Returns:1 if TI486SXL(C) B step
II
o if TI486SXL(C) A step
II
11**************************************************** ***********************
isb ()
{
int i, b_step;
char mem[ 10];
for (i=O; i<10; mem[i++]=O;
asm
{
.386
extrn _ill_op:near
A-28
Detection of SMM Capable Version
;*********************************************
;****** get present illegal opcode handler
,.*********************************************
push
es
push
bx
mov
ax, 3506h
int
21h
mov
old_seg, es
old_off, bx
mov
pop
bx
pop
es
;*********************************************
;****** install new illegal opcode handler
;*********************************************
push
dx
push
bx
push
ds
mov
ax, 2506h
mov
dx, OFFSET _ill_op
mov
bx, cs
mov
ds, bx
int
21h
pop
ds
pop
bx
pop
dx
;*************************************************************
;****** Set SM4 and SMAC and SMI bit to allow SMM instructions
;*************************************************************
mov
al, Oclh
out
22h, al
in
al, 23h
mov
byte ptr [save_ccrl, al
or
al, 86h
mov
ah, al
mov
al, Oclh
out
22h, al
mov
al, ah
out
23h, al
;*********************************************
;****** Setup nonzero SMM region
;*********************************************
mov
al, Ocfh
out
22h, al
in
al, 23h
mov
byte ptr [save_cf), al
.al, Ocfh
mov
out
22h, al
mov
al, 1
23h, al
out
SMM Programmer's Guide
A-29
Detection of SMM Capable Version
,.*********************************************
;****** Set SMM region to the top of memory to
;****** avoid overlapping with this program
,.*********************************************
mov
out
in
mov
mov
out
in
mov
mov
out
mov
out
mov
out
mov
out
mov
out
in
and
out
aI, Ocdh
22h, al
aI, 23h
byte ptr
aI, Oceh
22h, al
aI, 23h
byte ptr
aI, Ocdh
22h, al
aI, Offh
23h, al
aI, Oceh
22h, al
aI, Oh
23h, al
aI, Ocfh
22h, al
aI, 23h
aI, Ofh
23h, al
;****** flush pre fetch after changing configuration
jmp
$+2
,.*********************************************
;****** Execute SMM instruction sav_seg
,.*********************************************
;sav_seg word ptr mem, ds
Word ptr mem == ss:[bx]
lea
bx, mem
db 36h Ofh 78h Ifh
,.*********************************************
;****** restore configuration registers
,.*********************************************
mov
out
mov
out
mov
out
mov
out
mov
out
mov
out
mov
out
mov
out
A-30
aI, Ocdh
22h, al
aI, byte ptr save_cd
23h, al
aI, Oceh
22h, al
aI, byte ptr save_ce
23h, al
aI, Ocfh
22h, al
al byte ptr save_cf
23h, al
aI, Oclh
22h, al
al byte ptr save_ccrl
23h, al
Detection of SMM Capable Version
,.*********************************************
;****** restore old illegal opcode handler
,.*********************************************
push
dx
push
bx
push
ds
mov
ax,
dx,
mov
mov
bx,
mov
ds,
21h
int
pop
ds
pop
bx
pop
dx
) II isb asm region
2506h
OFFSET old_off
OFFSET old_seg
bx
for (i=O, b_step=FALSE; i<10; ++i)
if (mem[i] 1= 0)
{
b_step
break;
TRUE;
}
return (b_step);
} II isb ()
;********************** bad_op.asm ***********************
public _ill_op
assumecs:_TEXT
_TEXT segment byte public 'CODE'
_ill_op proc near
pop
ax
add
ax, 5
push ax
iret
_ill_op endp
TEXT ends
end
SMM Programmer's Guide
A-31
Format of Data Used by SVDCIRSDC Instructions
A.12 Format of Data Used by SVDC/RSDC Instructions
The SVDC/RSDC instructions should be used to change limits and read/write
access privilege levels of the application and system segment descriptor registers, see Table 2-7 (page 2-22), before they are used by SMM code. The
instructions use a 10 byte area composed of two major portions of the system
address register set, see Figure 2-7 (page 2-17), value/contents, and the nonprogrammer-visible internal descriptor that has the format shown in
Example A-B. Example A-9 (page A-33) loads a real-mode system segment
(SS) descriptor and nonprogrammer-visible region values.
System segment-descriptor registers are described in Subsection 2.5.2.2,
Descriptors, page 2-21.
Example A-B.
Internal Descriptor Format
'Segment Register Descriptor <8 bytes>, Segment Register Selector <2 bytes>,
;1)
Segment Register Selector: This is the segment if the segment register
;was loaded in real mode or the selector if the segment register was
;loaded in protected mode. In real mode, this is also equal to the segment
;base divided by 10h and clipped to 16 bits.
dw
,Selector or Segment
;2)
Segment Register Descriptor, which is the actual descriptor if the
;segment was loaded in protected mode, or a pseudo-descriptor if the segment
;register was loaded in real mode.
dw
dw
db
db
db
db
A-32
Limit [15:0] ,
Base [15:0] ,
Base [23: 16 ] ,
, P , DPL , 1 , DscTy[2:0] , A ,
'G , D , r , AVL , Limit [19:16]
, Base [31:24] I
DscTy is descriptor ;type (DT)
Format of Data Used by SVDCIRSDC Instructions
Example A-9.
Load 88 Descriptor Values (Real Mode)
iLoad SS descriptor (nonprogrammer-visible region) values appropriate to iREAL mode.
see Example A-3 page A-14
INCLUDE SM.MAC
old_val
real mode:
dt
dw
dw
db
db
db
db
dw
location to store old ss value
limit
base
0
base
0
lOOlOOllB
i 93h, data segment
G=O, D=O, upper limit=O
0
0
high portion of base
selector/segment
0
sav_seg
rst_seg
mov
mov
[old_val], ss
ss,[real_mode]
ax, cs
ds, ax
?
Offffh
SMM Programmer's Guide
A-33
Altering SMM Code Limits
A.13 Altering SMM Code Limits
When the CPU acknowledges an external SM interrupt and switches into system management mode, the CPU is put into real mode. In section 2.8.5, SMI
Service Routine Execution on page 2-54, it is stated that the code segment
register is loaded with the base and limits defined by the ARR4 register. If the
defined SMM address space is a 16K region, the CS segment limit will be 16K.
This is in contradiction to the normal segment limit of 64K for real mode.
This does not normally cause the programmer any problems, since the CS
register can access any address in the SMM address space. The only time this
can become a problem is if the SMM code jumps to code outside the SMM address space. An example of this might be jumping to a BIOS routine to save
a block of memory to the disk drive. The BIOS routine might expect the CS
code segment limit to be 64K, and might require it to be, depending on the offset of the routine, or any routine it calls. The BIOS procedure might be at offset
38416 of the BIOS segment for example. If, as stated above, our SMM limit
is 16K, then the CPU would generate a segment overrun fault when it attempted to jump to offset 38416 of the BIOS segment.
There are several solutions to this problem. One solution is to never execute
code outside of the SMM space. Another solution is to have an SMM space
of 64K, or larger, so that the CS code segment limit is 64K or more. The third
solution is to change the CS limits while in the SMM code.
When in real mode, the hidden portion of the segment registers are not accessible to the programmer, unlike in protected mode. With the new SMM instruction RSOC, a complete 80-bit segment register and descriptor cache entry can
be read from memory into a segment register, thus changing the segment limits and attributes, even when in real mode. This could be done to make the OS
segment have a 4G limit, enabling real mode SMM code to access all of
memory with a 32-bit offset, without ever leaving real mode. However, the
RSOC instruction will not work with the CS register! The only way to change
the limits of the CS segment is to switch to protected mode, do a far jump to
a segment descriptor that has the desired segment limit and attributes, and
switch back to real mode.
To do this, several things must happen. A GOT with at least one valid entry
must be set up (this entry is a descriptor for the code segment that the intersegment jump is made to). Save the old GDTR register contents (using SGOT),
and the register should be loaded to point to the new table (using LGOT). Save
the old CRO value, and switch into protected mode with paging off. Do an intersegment jump to the code segment in the GOT, thus changing the CS segment
limit. Next, restore the CRO value, which switches back to real mode. Restore
the saved GOTR value.
A-34
Testing/Debugging SMM Code
A.14 Testing/Debugging SMM Code
There are several ways to debug SMM code:
o
Emulation Technology TI486SXLC microprocessor pod with an HP
16500/550 Logic Analyzer
o
o
•
Supports selective trace capture
•
SMM instruction disassembly
Periscope - software only
•
Full screen debugging
•
TSR
•
Single stepping and break points
DOS debug - software only
•
o
Single stepping and break points
Other selected logic analyzers
A.14.1 Software Only Debugging
It is possible to write an SMI handler and debug it as a TSR. Use a debugger
that can set break points at any address in memory. Use the following code
sequence as a model of how to build the SMI handler as a TSR. This code sequence also contains a section that loads the CS nonprogrammer-visible section to change the limit. This is required so that a protection error does not occur when code is executed outside of the SMM region. It is assumed that ADS#
and SMADS# from the CPU are ORed together by the chipset or external logic.
Also, the chipset should support programmable SMM locations.
This code marks the SMI handler address in the user interrupt INT 66 location
(0:198h). This is done so that the programmer can determine the location of
the SMM region and set break points.
The debugger is able to set a code break point outside of the SM I handler using
INT 3 only. This is because the debug control register DR? is set to the reset
value upon entry to the SMI handler. This causes break conditions in DRO-3
to be disabled. Debug registers can be used if set after entry to the SMI handler
and DRO-3 are saved.
Using a TSR to debug SMI has some limitations:
o
o
Other code could overwrite the region.
Jumps or call~ must be to known offsets.
SMM Programmer's Guide
A-35
Testing/Debugging SMM Code
A.14.2 Software Debugging Example
The following is an example that can be used forthe first step in debugging 8MI
code:
Example A-1 o. Debugging 8MI Code
.MODEL SMALL
. STACK
.386P
INCLUDE SM.MAC
RD_WR EQU
EX_RD EQU
12h
1Ah
;read/write
;execute/readable
COMMENT "This is an example of SMI code which can exist below the 1 MByte boundary. It must be
before the 1 MByte boundary because it uses the value in the cs register in order to
form fixups based on its location as well as for the jump to return to real mode •
. CODE
srni_handler:
jmp
db
stacksmilabel
$over
100 dup (?)
;pass data area for assembler
;our smi handler gdt
gdt
ADDR
LIMT
g_big
dq
o
;null
0
100000h
= $
gdt
dw
(LIMT-l and Offffh)
dw
(ADDR and Offffh)
db
«ADDR SHR 16) and Offh)
db
RD_WR OR (0 SHL 5) OR (1 SHL 7)
db
«(LIMT-1) SHR 16) AND Of h) OR (0 SHL 6) OR (1 SHL 7)
db
«ADDR SHR 24) and Offh)
g_code = $-gdt
ADDR
0
LIMT = 100000h
dw
(LIMT-l and Offffh)
dw
(ADDR and Offffh)
db
«ADDR SHR 16) and Offh)
db
EX_ RD OR (0 SHL 5) OR (1 SHL 7)
db
«(LIMT-1) SHR 16) AND Of h) OR (0 SHL 6) OR (1 SHL 7)
db
«ADDR SHR 24) and Offh)
A-36
Testing/Debugging SMM Code
GDTSIZE = ($-gdt)
csareadb
dsareadb
ssareadb
esareadb
fsareadb
gsareadb
tsareadb
gdtsave df?
gdtnewdw
eaxsave
ebxsave
ecxsave
edxsave
espsave
dd
dd
dd
dd
dd
10
10
10
10
10
10
10
dup
dup
dup
dup
dup
dup
dup
(? )
(? )
(? )
(?)
(? )
(? )
(? )
GDTSIZE - 1
dd ?
; address
?
?
?
?
?
$over:
COMMENT A
The debugger may want to use ss,ds,es,fs,gs. The limits may be shortened if the program had been running in protected mode. We therefore extend the limits of these registers before we enable the debugger.
sav_seg
sav_seg
sav_seg
sav_seg
sav_seg
mov
mov
mov
[ssarea],ss
[dsarea] ,ds
[esarea] ,es
[fsarea],fs
[gsarea],gs
cs: [eaxsave] , eax
cs: [ebxsave] , ebx
cs:[espsave],esp
;save the stack pointer
COMMENT A
Clear VM flag in Eflags (See Section A.14.3).
mov
mov
mov
mov
push
mov
push
push
iretd
esp, offset smistack
ax, cs
ss, ax
eax, 0
eax
eax, cs
eax, offset @F
eax
sgdt
fword ptr cs: [gdtsave]
@@:
SMM Programmer's Guide
A-37
Testing/Debugging SMM Code
COMMENT A
fixup code for smi base
ipatch gdt
mov
eax,cs
shl
eax,4
mov
ebx,offset gdt
add
ebx,eax
mov
dword ptr [gdtnew+2],ebx
ipatch far jump into protected mode
mov
ebx,offset $nextO
add
ebx,eax
mov
dword ptr cs:[patchl],ebx
ipatch far jump back to real mode
mov
word ptr cs:[patch2],cs
isegment of us here
ioffset to here
idefine gdt base
start here
COMMENT A
extend the limits for the code segment
patchl
db
19dt
mov
or
mov
db
db
dd
dw
$nextO: mov
mov
mov
mov
mov
mov
xor
mov
db
dw
patch2 dw
$nextl:
A-38
66h
fword ptr [gdtnew]
eax,crO
al,l
crO,eax
66h
Oeah
?
g_code
bx,g_big
ss,bx
ds,bx
es,bx
fs,bx
gs,bx
al,l
crO,eax
Oeah
offset $nextl
iextend the limits of the data segments
?
ifar jump to set cs and writable bit
;back to real mode
Testing/Debugging SMM Code
COMMENT A
define a valid stack
mov
mov
mov
COMMENT
ax,cs
ss,ax
esp,offset stacksmi
A
****** Insert user specific smi code here & set breakpoints. ******
db
66h
fword ptr cs:[gdtsave]
19dt
rst_seg ss, [ssarea]
rst_seg ds, [dsarea]
rst_seg es, [esarea]
rst_seg fs, [sarea]
rst_seg gs, [gsarea]
mov
eax,dword ptr cs:[eaxsave]
mov
ebx,dword ptr cs:[ebxsave]
mov
esp,dword ptr cs:[espsave]
exit sm
smi handlere:
SMI SIZE = offset smi_handlere - offset smi_handler
Install PROC
i***** Enable SMM Region ******
Don't enable SMI yet because we're not ready for it.
mov
aI, Oclh
iselect CCRl
out
22h,al
in
aI, 23h
iread CCRl
ienable SMADS# and SMM region (not SMI)
or
aI, 80h
mov
ah, al
aI, Oclh
iselect CCRl
mov
out
22h, al
mov
aI, ah
iwrite new CCRl value
out
23h, al
mov
mov
shl
add
add
and
mov
push
eax,offset endresident
ebx,cs
ebx,4
eax,ebx
eax,Offfh
eax,NOT Offfh
ieax
edx,eax
edx
start of smi space
SMM Programmer's Guide
A-39
Testing/Debugging SMM Code
,.****************************************************************************
; * Load 8M! address and size into ARR4
,.******
cd
;******
; ****** Config Reg
; ****** Address
ce
cf
31-28 27-24, 23-20 19-16, 15-12
7-4 3-0
31-28 27-24, 23-20 19-16, 15-12 11-8,
;region 4 1st word
mov
out
mov
shr
out
aI, Ocdh
22h, al
eax, edx
eax, 24
23h, al
mov
out
mov
shr
out
aI, Oceh
22h, al
eax, edx
eax, 16
23h, al
;region 4 2nd word
mov
out
mov
shr
and
or
out
aI, Ocfh
22h, al
eax, edx
eax, 8
aI, OfOh
aI, 1
23h, al
;region 4 3rd word
;get smi handler address
;move address <31~24> to al
; [7-0]=>smbase[31-24]
;get smi handler address
;move address <23-16> to al
; [7-0]=>smbase[23-16]
;get smi handler address
;move address <15-12> to al
;clear bottom nibble
;select 4KB 8M! size
; and [3-0]=>smsize
,.****************************************************************************
pop
mov
add
mov
shl
sub
she
push
shr
mov
mov
mov
mov
int
pop
A-40
edx
eax,edx
edx,1000h
ebx,es
ebx,4
edx,ebx
edx,4
dx
eax,4
es,ax
ds,ax
dx,O
ax, 2566h
21h
dx
;start of smi area
;reserve 4k for smi handler
;current psp
;bytes to reserve
;paragraphs to reserve in dx
;paragraph of smi handler
;save for later
;always starts at 0
;int 66h vector at O:198h
;tsr address
Testing/Debugging SMM Code
;move the code to the smi area
mov
aI, Oclh
;select CCRI
22h, al
out
in
aI, 23h
;read CCRI
mov
ah, al
;save old value
aI, Oclh
mov
;select CCRI
out
22h, al
mov
aI, ah
;get old value
or
aI, 04h
;enable SMAC
23h,al
out
;be clean on ah for later
RELOCATE = 0
IF RELOCATE
sub
esi,esi
sub
edi,edi
mov
cx,cs
mov
ds,cx
mov
ecx, (SMI_SIZE+3)/4
rep
movs dword ptr es:[edi],dword ptr ds:[esi]
ELSE
;put the far jump at the start of the smi_area to above code
mov
byte ptr es:[O],Oeah
mov
word ptr ex:[l],offset smi handler
mov
word ptr ex:[3],cs
ENDIF
;restore smi state and enable SMI
mov
aI, Oclh
;select CCRI
out
22h, al
mov
aI, ah
;get old value
or
aI, 02h
;set SMI bit to enable SMI
23h,al
out
;be clean on ah for later
COMMENT "
SMIs may happen at any time now.
idx = offset in this segment to tsr
mov
ax, 3100h
int
21h
Install ENDP
;----end of resident code---endresident
label byte
db
END
2000h
;Request function 31h, error code=O
; Terminate-and-Stay-Resident
dup (?)
Install
,.****************************************************************************
SMM Programmer's Guide
A-41
Testing/Debugging SMM Code
A.14.3 Clearing the VM Flag Bit
The following condition is known to exist:
If the CPU is in V86 mode and is interrupted by an 8MI, the VM bit in the
EFLAG8 register is not cleared as it should be during real-mode operation. Not
clearing this bit can cause protection errors of valid instructions that are being
executed in the 8MI handler. This can be resolved by adding the following code
after saving all used registers:
rst_seg ss, [gdt+g_big]
mov
esp, offset smistack
mov
ax, cs
mov
ss, ax
mov
eax, 0
push
eax
mov
eax, cs
push
eax
mov
eax, offset @F
push
eax
iretd
@@:
change ss limit to 4 Gbytes
create new stack pointer
new stack segment
flags after iretd
segment after iretd
offset after iretd
Note:
See the debugging example in Section A.14, Testing/Debugging SMM Code,
for usage of above code.
A-42
Appendix B
BIOS Modifications Guide
To reap full benefit from the TI486SXL(C) family of microprocessors, the system BIOS should be modified to support the internal registers that control the
on-chip cache, clock doubling, and other features. This appendix serves as a
guide to some of the changes that need to be considered, and includes sample
assembler code for controlling the cache.
There are three considerations that are discussed in relation to the internal
cache registers and clock double enable:
o
Power-up and hard reset
o
Protected-mode to real-mode switching
o
Soft reset- ( CONTROL) (ALT) ( DELETE)
In each case, the state of the CPU cache registers and the clock-double enable
bit must be known to determine when and how to change their values.
Topic
Page
-'
'c~
y
~
,~
~
B~ 1I?iffere.rice$·Bet\Ne~ntbe TI486SlC/aLC:BIO$and:
theJI~:86$~L(ClBI.(jS ".
.
pr~~.PAQ.toRea'-MQ.d~C$WitCh~~r·· •..• .
. .. .. ...::
S~ft~Re~et: .',: ¢(.\Nl~Qli~AtT..I))EE,ETE " •. ~' .•••• ,~; ~.:. ~. ~ •• ,~ ..•~.. '. _.•• ,~.•• ~ ~,;B':4
:rtlr~ing (jhandQ~'t~efrit~rrial C~~h~; ~j'
........
.,~ ~ ~
... '.- • • •
·u~;. ~..;;; ;:. ~"J:l~4:'
8-1
Differences Between the TI486xLCIE BIOS and the TI486SXL(C) BIOS
B.1 Differences Between the TI486SLC/DLC BIOS and the TI486SXL(C) BIOS
The TI486SLC/DLC BIOS requires some modifications to fully support the
new features of the TI486SXL(C) family of microprocessors.
If the BIOS currently tests the internal cache before enabling it, the test routine
will require modification. Due to the larger size of the TI486SXL(C) cache, the
cache test registers have changed from those in the TI486SLC/DLC. (See
Table 2-17 on page 2-36.) It is not necessary to test the TI486SXL(C) cache
prior to enabling it during the boot process.
In addition to changing the cache test registers, the cache organization selection bit has been redefined. In the TI486SLC/DLC, configuration control register 0 (CCRO) bit 6 is used to select between a direct-mapped and a two-way,
set-associative, internal cache organization. For the TI486SXL(C) family, the
cache is always two-way set associative and CCRO bit 6 is defined to enable
clock-doubled mode. BIOS prepared to support the TI486SLC/DLC can allow
the user to select the cache organization, but BIOS prepared for the
TI486SXL(C) should comprehend that the cache-organization selection is not
available.
If the BIOS supports software clock switching, a modification to support clockdoubled feature may be desirable. Switching to high-speed mode should enable bit 6 of CCRO and thus put the CPU in clock-doubled mode. Switching
down the CPU speed should disable bit 6 of CCRO and put the CPU in
nonclock-doubled mode. If the BIOS is APM (advanced power management)
compliant, the use of 1x and 2x modes should be implemented as well.
Note:
When the TI486SXL(C) is in clock-doubled mode, the CLK2 input must not
be scaled or stopped. First, the processor must be placed in nonclockmode; then, the CPU clock speed can be changed.
doubled
,
When the TI486SXL(C) family microprocessors are reset, the cache and the
clock-doubled features are disabled by default.
8-2
Power-Up and Hard Reset / Protected-Mode to Rea/-Mode Switching
B.2 Power-Up and Hard Reset
During power-up and hard reset, the system is booted into the operating system. Due to the reset line to the CPU going active, the internal cache and the
clock-doubled feature are disabled, making the CPU act similar to a 386. If the
cache and the clock-doubled feature are enabled prior to the reset, they must
be turned on at some point before the as is booted. A convenient time may
be during final chipset initialization, understanding that the cache should remain off during memory sizing. Many BlOSs provide the user an option to disable the system cache using the setup screen. Because most user cache-control options are stored in nonvolatile RAM, the flag responses and potentially
other flags should be checked before turning the cache on.
B.3 Protected-Mode to Real-Mode Switching
Protected-mode to real-mode switching can be implemented to handle cases
where the as has been booted, applications are running, and the CPU needs
to be reset from protected to real mode. The object is to switch CPU modes
and jump back into the as or application at some saved return address. When
the CPU is reset, the internal cache and the clock-doubled feature are disabled. Before returning control to the application, the cache and clock doubling
should be turned back on, but only if they were enabled before the reset occurred. This is accomplished by checking the cache-enable flag in the nonvolatile RAM to see if the user enabled caching from the setup screen. However,
if the BIOS allows the user to turn off the cache by a hot-key combination (perhaps as part of speed switching), other checks may need to be performed to
see if the cache should be turned back on.
BIOS Modification Guide
8-3
Soft Reset-CONTROL-ALT-DELETE / Turning the Internal Cache On and Off
8.4 Soft Reset- (CONTROL J ( ALT J ( DELETE
J
The objective of a soft reset is to reset the system and reboot the as, similar
to power-up and hard reset, but a hard reset of the CPU is not generated. Thus,
the CPU's internal cache and clock doubling are not disabled. Since the cache
is not disabled, this can negatively impact memory-sizing code, such as generating memory-size mismatch errors. In this situation, disable the internal
cache and enable it prior to booting if it was enabled by the user in setup.
8.5 Turning the Internal Cache On and Off
When the TI486SXL(C) family of microprocessors internal cache is turned on
or off, the following guidelines should be observed in the order presented:
1) Turn off interrupts-CLI
2)
Turn off cache using Control Register 0 (CRO) bit 30 and flush using
WBINVD
3)
Manipulate cache registers
4)
Turn on cache and flush using WBINVD
5) Turn on interrupts-STI
This sequence ensures that the process is not interrupted until complete and
that no cache coherency issues arise when the cache is turned back on. When
manipulating the cache registers it is a good idea to explicitly set each register
instead of relying on default values.
8-4
Turning the Internal Cache On and Off
Example 8-1.
Turning Internal Cache Off
Some example assembler code for turning the cache off follows:
CacheOut
index, value
AL, index
22h, AL
AL, value
23h, AL
MACRO
MOV
OUT
MOV
OUT
CacheOut ENDM
CLI
MOV
OR
MOV
WBINVD
EAX, CRO
EAX, 40000000h
CRO, EAX
CacheOut
CacheOut
OCOh,
OClh,
OOh
OOh
CacheOut
CacheOut
CacheOut
OC4h,
OC5h,
OC6h,
OOh
OOh
OFh
CacheOut
CacheOut
CacheOut
OC7h,
OC8h,
OC9h,
OOh
OOh
OOh
CacheOut
CacheOut
CacheOut
OCAh,
OCBh,
OCCh,
OOh
OOh
OOh
CacheOut
CacheOut
CacheOut
OCDh,
OCEh,
OCFh,
OOh
OOh
OOh
EX,
4COOh
21h
WBINVD
STI
MOV
INT
set bit 30, turn off cache
for external cache coherency
return to DOS
BIOS Modification Guide
8-5
Turning the Internal Cache On and Off
Example 8-2.
Turning Internal Cache On
Turn on the microprocessor internal cache by modifying some of the register
values as shown. The CacheOut macro definition remains the same:
CLI
MOV
OR
MOV
WBINVD
EAX, CRO
EAX, 40000000h
CRO, EAX
CacheOut
CacheOut
OCOh,
OClh,
23h
OOh
CacheOut
CacheOut
CacheOut
OC4h,
OC5h,
OC6h,
OOh
OOh
OOh
CacheOut
CacheOut
CacheOut
OC7h,
OC8h,
OC9h,
OOh
OOh
OOh
CacheOut
CacheOut
CacheOut
OCAh,
OCBh,
OCCh,
OOh
OOh
OOh
CacheOut
CacheOut
CacheOut
OCDh,
OCEh,
OCFh,
OOh
OOh
OOh
MOV
AND
MOV
WBINVD
STI
MOV
INT
EAX, CRO
EAX, NOT 40000000h
CRO, EAX
clear CD bit
EX,4COOOh
2lh
return to DOS
8-6
set bit 30, turn on cache
for external cache coherency
set bits NCI, NCO, BARB
Appendix C
I
Desi n Considerations and Cache Flush
This appendix provides design considerations, address bit A20 masking, and
general cache invalidation procedures.
Topic
C.1
Page
Besign .Consideratlons'.;.:~ '. ~',' .. ~ ..... ~ .. ~;.. " • ~~ ~~:.: ....... ~ •.'ii .~.C~2:
. Co2
C.3 . General Ciijlle Invallijation '. ~ •... ~ ~ ... ~ ~ •. ~'.o' .... :,~ •• ~ ••' •• "
,0'0 • •
:~
••
G'*4 .
C-1
Design Considerations
C.1 Design Considerations
The following conventions should be employed in connecting the
TI486SXL(C) terminals to the PWB:
D Connect (short) all VCC terminals to the positive supply voltage.
D Connect (short) all VSS (GND) terminals to the system ground.
D For the TI486SXL in the 144-pin package connect (short) both W/R# terminals (terminals 36 and 37) together and connect to W/R# signal source.
D Leave electrically open (unconnected) all NC terminals.
Note:
Connecting orterminating (high or low) any NC terminal(s) can cause unpredictable results or nonperformance of the microprocessor.
The final responsibility for verifying designs incorporating TI486SXL(C) microprocessors rests with the customer originating the motherboard design.
C-2
Address Bit A20 Masking
C.2 Address Bit A20 Masking
The A20M, address bit 20 mask, is an anomaly in PC designs resulting from
the fact that truncated addresses can be generated by an 8086/8088 outside
the physical address range of Oh-FFFFFh. For example, an 8086/8088 system that contains FFFFh in a segment register and OFFFh in an offset register
results in an address of 1OOFFEh that requires 21 bits to address. Since the
8086/8088 has only 20 address bits (AO-A19), the most significant bit of the
resultant address would need to appear on an A20 bit if the 8086/8088 had
one.
Since the 8086/8088 address bus is not wide enough, only the first 20 bits of
the address are seen by the system. Using the address 1OOFFEh, generated
in the previous example, the 8086/8088 system read/write address is performed at location FFEh and not at 1OOFFEh. The 80286 and later microprocessors implement at least 24 address bits and perform the read/write to address location 1OOFFEh. Thus, software applications can produce different results when run on an 8086/8088 system versus an 80286 or later microprocessor system.
Systems that use 80286 or later microprocessors compensated for this anomaly by adding circuits to generate an A20 mask (referred to as the A20 mask
or the A20 gate, or similar). The A20 mask consists of software-controlled logic
that forces a zero on the A20 address line regardless of the actual value of A20.
The software-controlled A20 mask can also instruct the mask to permit the true
value to be passed to the system when required.
It is important to note that the A20 mask logic is external to the processor in
both 80286 and 80386 designs. The processor generates the actual address
but the system logic can be set to ignore or not ignore the A20 pin. Normally,
the A20 pin is ignored when these processors are executing in real mode and
emulating an 8086/8088.
This is an important consideration when replacing an 80386SXlOX device with
a Tl486-type device. The TI486SXL(C) microprocessors implement an internal cache and, if the system is in a state that ignores the A20 address input,
the processor must know so that it can also ignore the A20 address input.
If the A20M bit of configuration control register 0 (CCRO) is set, the
TI486SXL(C) microprocessor knows that the A20M input provides the true value required. However, if the TI486SXL(C) is inserted into a socket designed
for the 80386SXlOX, the TI486SXL(C) A20M pin is placed at a pin location that
is n"ot used by the 80386SXlOX. The system hardware needs to be modified
to provide the A20M connection.
The NCO bit of CCRO is a software-only solution to the A20 mask function.
When set, the TI486SXL(C) microprocessor does not cache the first 64K bytes
of memory above each 1M byte boundary. This solution means that, even if
the value of the A20 address is not known, the processor does not cache data
to the affected addresses.
Design Considerations and Cache Flush
C-3
General Cache Invalidation
C.3 General Cache Invalidation
When the FLUSH bit in configuration control register 0 (CCRO) is set, the
FLUSH# input, when asserted low, invalidates the contents of the
TI486SXL(C) internal cache. This can be used to assure that data stored in the
TI486SXL(C) internal cache does not differ from data stored in system
memory. Additionally, the cache can be invalidated by execution of the
486-compatible invalidate instructions (INVD,WBINVD) or in response to a
hold acknowledge state if the BARB bit in CCRO is set. The method chosen
for invalidating the TI486SXL(C) internal cache can be different, depending on
whether or not the system has a serial secondary cache. Invalidation methods
are described for systems with and without a serial secondary cache.
C.3.1
Systems With No Secondary Cache or With a Parallel Secondary Cache
When the only cache memory in the system is the TI486SXL(C) internal cache,
or when the secondary cache has a parallel (or look-aside) architecture, there
are two general methods of invalidating the cache and maintaining cache coherency.
C.3.1.1 Method 1
Invalidate the TI486SXL(C) cache every time the CPU enters a hold state. By
setting the BARB bit in CCRO, automatic cache flush occurs when the
TI486SXL(C) is placed in a hold state. If the chipset does not support hidden
refresh, very frequent cache invalidation may occur since the CPU is placed
in hold during DRAM refresh cycles that occur approximately every 15 /-1s. If
the chipset supports hidden refresh, this may be an acceptable solution since
the cache is only invalidated during DMA or bus master reads from or writes
to memory.
C.3.1.2 Method 2
Invalidate the TI486SXL(C) internal cache when a DMA or bus master writes
to system memory. The external hardware must drive the TI486SXL(C)
FLUSH# or MEMW#t input when DMA or bus masters are detected writing to
system memory. This can be done using one of the circuits shown in
Figure C-1 or Figure C-2.
Figure C-1 shows the circuitry needed to generate an active-low FLUSH# to
the CPU each time a hold state is entered (defined by HLDA = 1) and memory
write occurs (defined by MEMW# = 0).
Figure C-1. Cache Invalidation for the TI486SXLC and the 132-pin TI486SXL
TI486SXLC and
132-Pin TI486SXL
MEMW#
(from ISA bus)
HLDA
----------------~
(from CPU)
FLUSH#
t MEMW# input is implemented on the 144-pin and 16B-pin TI4B6SXL only.
C-4
General Cache Invalidation
The 144-pin QFP and 168-pin PGA versions of the TI486SXL have the
external hardware shown in Figure C-1 incorporated on chip. Therefore, to maintain cache coherency in these two devices, connect the
MEMW# signal from the ISA bus to the MEMW# input as shown in
Figure C-2.
Figure C-2. Cache Invalidation for the 144- and the 168-Pin TI486SXL
144- and 168-Pin TI486SXL
MEMW#
(ISA)
----I
MEMW#
(Internal pullup)
C.3.2 Systems With a Serial Secondary Cache
In a system with a serial (or look-through) secondary cache, flushing the cache
cannot be accomplished by setting the BARB bit in CCRO. Bus arbitration occurs between the serial cache controller and the system allowing the CPU to
continue executing out of cache.
The secondary cache controller arbitrates the bus among itself and DMA controllers or bus masters and asserts HLDA to the chipset when the bus has been
granted. Each time a DMA or bus master write is detected, the FLUSH# pin
on the TI486SXL(C) must be asserted. The circuit shown in Figure C-3 can
be used. Note that the HLDA signal is generated by the secondary cache controller rather than the CPU. This is the preferred solution since, in many cases
with secondary serial caches, the CPU is not put in hold so it can continue
execution from cache while DMA or bus-master activity is occurring on the system bus.
Figure C-3. FLUSH# Logic With a Serial Secondary Cache
TI486SXL 144- and 168-pin only
~
• _____________________ ..
~,Pin66
,
MEMW#,
'(no connection)
1.-------------- ______ "
MEMW# - - - - (
(From ISA)
)-----1
FLUSH#
HLDA - - - - - - - - '
(From Cache Controller)
Design Considerations and Cache Flush
C-5
C-6
Appendix D
OEM Modifications for 168·Pin CPGA
This appendix describes the potential modifications an OEM needs to imple-\
ment on an existing 486SX/DX motherboard to take advantage of the
TI486SXL 168-pin CPGA. This package offers OEMs added flexibility in implementing solutions that support various 486 CPUs with the same motherboard.
The pinout of the TI486SXL 168-pin CPGA is nearly identical to the Intel™ or
AMDTM 486SX CPGA pinout. The NC pins on the TI486SXL package that
match signal pins on the 486SX have no internal connection and can be left
connected to the 486SX signal pins when the board is configured as a
TI486SXL board. This greatly simplifies the interface for the OEM. The classes
of board designs covered are listed in the topic index below.
The board design requires the use of system logic that supports the Intel/Advanced Micro Devices 486 interface and the TI486SXL interface. Since board
modifications for TI486SXL support are system-logic dependent, the implementation details are left to the board designer.The design examples show
both required and optional jumper connections that can be made if the functions associated with them are needed. None of the optional signals require
termination if not used.
Subsection D.5, Power Planes for 3.3-Vand 3.3-V/5-V Systems Using
TI486SXL or 486DX4 on page D-9, shows a system implementation for
.a 3.3-V system that supports a 5-V ISA and a 3.3-V VL bus and another imple. mentation for a mixed 3.3-V/5-V system that supports a 5-V ISA and a 5-V VL
bus. In both implementations the microprocessor runs at 3.3 V.
The final responsibility for verifying designs incorporating any version of a
TI486SXL microprocessor rests with the customer originating the motherboard design.
Topic
Page
.
:D~1
.
1391l" - - - - - - CLKMUL
o
System Logic Side
1 0 - - - - - BUSY#
S4/VOLOET-------I0 2
3 0 - - - - - VOLOET
Jumper
1-2: TI486SXL
2-3: 4860X4
Function: Burst Mode (Required)
168 CPGA Socket Side
486DX4 Pin No./Name
R16/BLAST#
0-6
1-2: TI486SXL
2-3: 4860X4
Function: Voltage Detect (Required)
168 CPGA Socket Side
486DX4 Pin No./Name
o
Jumper
System Logic Side
10 kQ
1 0------JVV'v-- V SS
20
BLAST#
0 3
(VL slot)
Jumper
1-2: TI486SXL
2-3: 4860X4
Boards Supporting the VL Bus
0.4 Boards Supporting the VL Bus
In order to support the VESA VL bus™ 2.0p Proposal, the following design
guidelines should be considered.
0.4.1
Cache Snooping
In a VL-bus design, it is the function of the local bus controller to resolve
arbitration between the CPU and the VL-bus master. For this architecture, the
CPU can be forced to relenquish the host bus by asserting HOLD. There are
two options for maintaining cache coherence:
D Use the BARB bit in Configuration Control register 0 (CCRO) to flush the
internal cache.
D Use the inverted HLOA output of the CPU to perform a hardware FLUSH#
to the CPU. See Figure 0-3. The FLUSH# pin must be enabled by using
bit 4 of CCRO.
Figure D-3. Hardware Flush
HLOA4-------e----1
CPU
FLUSH#
Note:
Pin names and assigned locations are provided in Chapter 6, Mechanical Specifications.
These methods can be used only if the system logic supports the CPU HOLD
arbitration scheme.
0.4.2 VL-Bus Clock
The VL-bus clock signal is a 1X clock that is in phase with the 486-type CPU
and is driven by either the system logic or the local-bus controller. The VESA
speciification allows for a frequency range of up to 66 MHz and dynamic clock
scaling. The specification limits the low-to-high level skew from the CPU clock
to LCLK as shown in Table 0-1 .
Table D-1. VL -Bus Skew
LCLK Max Frequency
Unit
33
40
50
Max Skew
Unit
3
MHz
2.5
ns
2
Systems that currently support a 1X and a 2X clock source should supply the
2X clock source to the CLK2 input of the TI486SXL and the 1X clock source
to the VL-bus LCLK signal.
Systems that currently support only a 2X clock source can consider the addition of a PLL or clock divider to generate the 1X VL-bus clock.
OEM Modifications for 168-Pin CPGA
0-7
Boards Supporting the VL Bus
0.4.3 VL-Bus Slot 10 Settings
The VL-bus slot 10 settings are shown in Table 0-2.
Table 0-2. VL-Bus Slot 10 Settings
Slot 10
Setting
100
0-8
Comments
TI486SXL Mode
101
0
TI486SXL Mode
102
o or 1
0: Minimum one wait state for writes
1 : Zero wait states for writes
103
o or 1
0: >33 MHz CPU clock speed
1: < 33 MHz CPU clock speed
104
0
Burst transfer not supported
Power Planes for 3-V and 3- V/5- V Systems Using T1486SXL or 486DX
0.5 Power Planes for 3.3-V and 3.3-V/S-V Systems Using TI486SXL or
486DX4
0.5.1
Power Planes for 3.3-V Systems
Figure 0-4 shows the implementation of a 3.3-V system that supports use of
either the TI486SXL or a 4860X4 microprocessor. This implementation yields
a 5-V ISA bus and a 3.3-V VL bus with the microprocessor running at 3.3 V.
Figure D-4. 3.3-V VL-Bus Implementation
Vee
5-V Power Supply
Regulator
= 3.3 V
3.3-V VL Bus
r--Chipset
(3.3-V/5-V
mixed)
3.3-V
SRAMs
DRAMs
I
I
I
I
I
I
IL
---,
I
I
I
VGAlLCD
I
I
VL Slots
I
(optional)
I
_ _ _ _ _ _ _ .J
5-V ISA Bus
r-
I
I
I
I
I
IL
-.
I
I
I
I
I
_ _ _ _ _ _ _ _ ISA
__
_ _ _ _ _ _ _ _ _ .JI
Slots
OEM Modifications for 168-Pin CPGA
D-9
Power Planes for 3- V and 3- V/5- V Systems Using Tl486SXL or 486DX
0.5.2 Power Planes for Mixed 3.3-V/5-V Systems
Figure D-5 shows the implementation of a 3.3-V/5-V system that supports use
of either the TI486SXL or the 486DX4 microprocessor. This implementation
yields a 5-V ISA and and a 5-V VL bus with the mocroprocessor running at
3.3 V.
Figure O-S. Mixed 3.3-V/S-V VL-Bus Implementation
VCC5 = 5 V
5-V Power Supply
Vcc
= 3.3
V
Regulator
5-V VL Bus
r-
5-V
Chipset
5-V
SRAMs
DRAMs
---
-,
I
I
I
I
I Slot 1 Slot 2 I
I
I
I
I
I
VL Slots
I
IL _ _(optional)
_ _ _ _ _ .JI
5-V ISA Bus
--,
~~~~~~,......-l~~~"""""~
I
I
I
I
- - - - - - - - - - - - "---- '-----' 1....-......... I
IL _ _ _ _ _ _ _ _ISA
Slots
I
_ _ _ _ _ _ _ _ _ _ _ .J
0-10
Chipset Support
0.6 Chipset Support
The following list of chipset vendors providing single-chipset solutions that
support both the Intel/AMD and the TI486SXL interface was compiled from information received from the specified chipset vendors. This is a partial list and
is not meant to be all inclusive.
o
o
o
o
o
o
o
o
o
o
o
o
o
o
ACC Microelectronics
Acer Laboratories
EFAR
ETEQ Microsystems
Headland Technology
OPTI
PicoPower Technology
SARC/PC Chip
Silicon Integrated Systems (SIS)
Symphony Laboratories
Tidalwave
UMC
UniChip
Western Digital
OEM Modifications for 168-Pin CPGA
D-11
D-12
Appendix E
Thermal Management in
Microprocessor-Based Systems
The purpose of this paper is to familiarize the reader with basic thermal concepts and the relationship between thermal measurements and the system.
In addition, problems associated with comparing thermal specifications from
different manufacturers are discussed. Finally, corrective activity within
JEDEC is explained in detail. This application report is intended for the casual
scientific reader and the only prerequisite is general engineering knowledge
of semiconductor devices.
Page
Topic
0>..•..• >
•.. ~' .•••.•.. ~ •..... ~'; ..>•.... E·2
E.1
Introduction. '>,' ii • •
E.2
Modes
E;3
Thermal SpecificationsC)flnfe,gtated Circuits .••... ~ ..•••••..••.• E-9
E.4
TIThermal Specification Methodology ••.••.••.• ~ .•••••••' .••..• E-11
E.5
Guidelines •..• >.•••••..••.•••••..•••...• 0...................... E-14
E~7
Current Trends and Th~ory of Correction •• ~ .•..•.•••....•.•.•.. E-15
E.7
Conclusions> •..••........••.•.... ~ ••..•...•••....••.••.....••• E-15
» ..........
of Heat Transfer ; •...••.•..•.•••.•.•••.... >••••••...•.... E..4
E-1
Introduction
E.1
Introduction
Thermal management is considered to be an important factor in both the conception and usage of semiconductor integrated circuits (ICs). Thermal
management is defined as the modes and techniques required to transfer a
powered IC's resultant operating heat to a system thermal heat sink. The thermal management of an IC is normally discussed in terms of that IC's operating
junction temperature (i.e., p-n junction of a diode). There are two main goals
for thermal management.
o
The first is to ensure that the operating junction temperature of the IC does
not exceed the range of functional and maximum temperature limits of that
IC. The functional temperature range of an IC is bounded by the temperatures that allow the IC to meet specified performance requirements. If the
operating junction temperature of an IC is not within the functional temperature range, diminishing system performance and operational errors may
result. The absolute maximum temperature is defined as the temperature
at above which physical damage begins to occur to the IC.
o
The second objective of thermal management is to ensure that the operating temperature of an IC enables the product reliability objectives for a given application to be met. Device failure rates are proportional to IC operating temperatures as shown in Figure E-1.
Figure E-1. Effect of Component Operating Temperature on Component Failure Rate t
eV 1=
10 3
~I~
c
E
~ 1 mAl
500
I
Q)
~
C>
19
g
400
"
Q)
"'0
0
0
300
Q)
"§
u;
..0
200
'" "
~
~~
"
:::J
CJ)
I
">
100
o
o
20
40
60
80
100
120
T J -Junction Temperature- °C
E.2 Modes of Heat Transfer
There are three ways that heat is transferred between points of differing
thermal potential:
o
o
o
conduction
convection
radiation
Conduction, the simplest heat-transfer mechanism, is the transfer of kinetic
energy from a more excited atom or electron to a nearby atom or electron that
is less excited via vibrations and collisions. The ability to conduct heat is dependent on the material. Materials that are dilute by nature (e.g., gases) are
poor heat conductors because of their low density. On the other hand, metals
are good thermal conductors as a result of their inherently high number of free
electrons to encourage collisions. This ability to conduct heat is quantified by
a proportionality constant (k) often referred to as thermal conductivity.
Table E-1 lists some common packaging materials and their associated thermal conductivities.
E-4
Modes of Heat Transfer
Table E-1. Thermal Conductivity of Packaging Materials§, 11
Metals (at 25°C)
Thermal Conductivity, (W/m) (0 C)
Copper
397
Aluminum
238
Lead
34.7
Alloy-42 (common lead-frame material)
10.7
Thermal Conductivity, (W/m) (0 C)
0.0234
Air
Nonmetals
Thermal Conductivity, (W/m) (0 C)
~0.8
Glass
Epoxy glass
~O.89
A second mode of heat transfer is convection, which is heat transfer by the
movement of a heated substance. In the case of natural convection, such
movement is caused by the induced differences in density that result from the
expansion and compression of a gas or liquid subjected to temperature
changes. Another type of convection, forced convection, forces movement of
a cooling medium across a heat source. Often, forced convection is created
by the use of a cooling fan within a system.
A final mode of heat transfer is radiation. Radiated heat transfers occur due
to thermal emission primarily in the infrared spectrum. Radiation is subject to
common-wave phenomena such as reflection. The ability of the surface of a
material to radiate heat is referred to as that surface's emissivity. Possible values for emissivity are from zero to unity, where unity signifies the maximum
thermal radiation at a given temperature.§
E.2.1
Integrated Circuit Thermal Resistance
The thermal resistance of an integrated circuit within a system can be broken
into two major components:
o
o
Internal resistance of the IC, Rei
External resistance of the Ie, Rex
Conventionally, resistances are discussed in more distinct terms. ReJC is defined as the thermal impedance from the silicon die within an integrated circuit
to the package surface, or case of that IC. This thermal path includes the thermal impedances of each of the materials used in packaging the IC, such as
solder, die adhesive, base materials, leads, the case itself, etc. Rei and ReJC
are interchangeable terms because ReJC quantifies only those thermal impedances internal to the package ending at the package leads or package
body surface. Re i and ReJC are functions of the IC package only and are not
significantly affected by the particular system in which an IC is used. The semiconductor manufacturer controls the values of Re i and ReJc,
11 Charles A.
Harper and Frank E. Altoz, Electronic Packaging and Interconnection Handbook,
Mc Graw-HiII, Inc, New York, pp. 2.61-2.62.
§ Raymond A. Serway, Physics for Scientists and Engineers, Saunders College Publishing,
Philadelphia, p. 545.
Thermal Management in Microprocessor-Based Systems
E-5
Modes of Heat Transfer
The thermal impedances that exist between the package case and the system
ambient thermal sink are collectively defined as RaCA, (thermal impedance
from case to ambient air). For a given package size and format, all such thermal impedances are primarily dependent on the particular system in which an
IC is used (PWB thermal conductivity, presence of forced convection, etc.).
These impedances are controlled by the user of the IC. Often RaJC and RaCA
are referred to together as RaJA.
RaJA can be qualitatively described as the thermal impedances between, and
including, a heat-sourcing silicon die and the system ambient thermal heat
sink.lf#
To demonstrate the relative size of RaJC and RaCA, Table E-2 displays various values for each of their respective percentages of the corresponding value
of RaJA at 0 cubic feet per minute (cfm) airflow. All entries listed come from various data sheets of several manufacturers of 486-class microprocessors. Notice that RaJC accounts for a maximum of 15 percent of RaJA. For all QFP
packages listed, the average share of RaJC is 9.6 percent. For the PGA package, 15 percent of RaJA is RaJc. As previously mentioned, the semiconductor
manufacturer controls the value of RaJC through various process parameters.
Therefore, at maximum, RaJC accounts for approximately 1/8th of the RaJA
value for packages listed. Stated differently, RaCA (or the system), accounts
for approximately 7/8ths of the total thermal resistance within a system.
Table E-2. Thermal Performance of Various 486-Class Microprocessors
Package
QFP
PGA
Number of Pins
RSJC,
eCIW)
Metal
100
Plastic
100
Ceramic
132
Material
Percent of ReJA
ReCA,
eCIW)
Percent of ReJA
2
8.7
21
91.3
4
11.1
32
88.9
3
15.0
17
85.0
The system in which an integrated circuit is used is quite significant in the RaJA
value for that IC. As stated, at least 7/8ths of the thermal impedance from the
silicon die to ambient air is due to the system. Significant effort is concentrated
on thermally optimizing the system in order to improve the thermal performance of the ICs within.
It is important to understand that such effort is exerted by the IC user. There
are several user-controlled system factors that contribute to the thermal resistance of an IC:
o
o
o
PWB thermal conductivity
Proximity/density of the ICs on a PWB
Airflow
~ Charles A. Harper and Frank E. Altoz, Electronic Packaging and Interconnection Handbook,
Mc Graw-Hill, Inc, New York, pp. 2.61-2.62.
# Jack Belani and B.J. Shanber, "Impact of Packaging Materials on Semiconductor Thermal
Management", Third Conference of Electronic Packaging: Materials and Processes &Corrosion
in Microelectronics, Minneapolis, Minnesota, April 28-30, 1987, pp. 113-115, 118.
E-6
Modes of Heat Transfer
E.2.2
PWB Conductivity
The thermal conductivity of a PWB is determined by the individual thermal conductivities of materials that comprise the PWB. PWBs are non homogenous
and normally consist of a base-laminate material, such as epoxy glass, and
various amounts of other materials, such as traces or planes made of copper.
The thermal conductivity of the laminate varies little between commonly used
PWB laminates (thermal conductivity of epoxy glass is about 0.89). Since the
thermal conductivities of commonly used routing metals are much higher than
that of the PWB laminate (see Table E-1 [page E-5], aluminum: 238, copper:
397), the thermal conductivity of a PWB is proportional to the amount of metal
in the PWB.
Table E-3 shows the thermal conductivities of several PWBs made from FR-4,
a type of epoxy glass. The boards vary by the number of signal layers and the
number of ground layers, or essentially, the copper volume. As copper volume
increases from 0 to 6.9 percent, thermal conductivity (W/m) (OC) increases by
a factor of 90 or almost two orders of magnitude. This is a result of the higher
thermal conductivity of copper compared to epoxy glass. The thermal conductivity of the PWB is proportional to the signal and ground metal content of a
PWB. The area and thickness of metal on lower levels of a PWB, under the
footprint of an IC, affects the thermal performance of that particular IC.II
Table E-3. Thermal Conductivity of PWBs With Various Amounts of Copper
Board Type and
Layers
Signal-Layer
Trace Widtht
Ground-Layer
Trace Widtht
Copper
Volume, (%)
Thermal Conductivity,
(W/m)(OC)
FR-4
a
0.3
FR-42 layer
35 11m
1.0
3.7
FR-44 layer
35 11m
35 11m
3.5
13.6
35 11m
70 11m
6.9
26.9
FR-44 layer
t Trace thickness is 2 flm.
Table E-4 compares two types of PWBs with identical 1~O-pin QFP devices
mounted on each board, and each board uses identical minimum-metal, signal-routing traces to complete the signal-interconnection layer. The singlesided PWB contains no metal on the opposite side of the board. The two-layer
PWB has a solid-copper ground plane on the opposite side. All measurements
are taken with no airflow present. The value of R8JA for the IC is improved by
9 percent by the addition of a copper ground plane (a resulting increase of 55
percent in copper content). When metal is present on lower levels of a PWB
within the projected footprint of an IC, the thermal performance of that IC is improved due to a lower value of R8JA-
II Ake Malhammer, Ph.D, "Heat Dissipation Limits for Components Cooled by the PCB Surface",
International Electronics Packaging Conference, San Diego, California, September 15-1B,
1991, pp. 307-30B.
Thermal Management in Microprocessor-Based Systems
E-7
Modes of Heat Transfer
Table E-4. ReJA Versus Board Type
Board Type
Single sided
36.0
Two sided
32.8
Figure E-4. Metal Within Projected Footprint of Integrated Circuit
PWB
I
If metal is in this area, the thermal
performance of the Ie improves.
I
~
E.2.3
Projected Footprint
\
\
~
Proximity of Integrated Circuit on Board
The location of an integrated circuit on a PWB can make a significant difference in the junction temperature of that device. In an ideal design, those ICs
with the lowest heat dissipation are located in the center of a PWB, and those
ICs with the highest heat dissipation are at the edges of the PWB. A concept
known as the territory surface method associates an area of PWB required to
sink the heat flow from a given IC. Often, in the case of surface-mount packaging, an IC's territory is violated by either other IC's territories or the edge of the
PWB. In either case, thermal performance is hindered in all involved ICs. It is
important to understand that not only the proximity of an IC on a PWB but also
its relative location on the board has significant effects on thermal performance.lI*
E.2.4 Airflow
In a typical system, heat dissipated by natural convection is a significant portion of overall heat dissipation. When forced convection is present within a system, the amount of heat dissipation increases in proportion to the rate of flow
of the convection. Higher rates of forced convection result in lower values of
RaJA·
In Table E-5, values of RaJA are listed for a 1~O-pin QFP mounted on a singlesided board in varying amounts of forced convection. As airflow (forced convection) increases from a rate of 0 cfm to 600 cfm, RaJA is decreased by a factor of 2.4. It can be stated that the RaJA value of an IC in a system is inversely
proportional to the presence/amount of forced convection (airflow).
II Ake Malhammer, Ph.D, "Heat Dissipation Limits for Components Cooled by the PCB Surface",
International Electronics Packaging Conference, San Diego, California, September 15-1B,
1991, pp. 307-30B.
*M.M. Hussein, D.J. Nelson, and A. Elshahiu-Riad, "Thermal Interconnection of Semiconductor
Devices on Copper-Clad Ceramic Substrates", 7th IEEE SEMI-THERM Symposium, August
1991, pp.121-122.
E-8
Modes of Heat Transfer / Thermal Specifications of Integrated Circuits
Table E-S. ReJA Versus Airflow
t
Airflow (cfmt)
ReJA
o
36
100
32
200
26
400
19
600
15
cfm = cubic feet per minute
E.3 Thermal Specifications of Integrated Circuits
Manufacturers normally publish detailed specifications of ICs that contain a
thermal portion, or a thermal specification. Manufacturer's thermal specifications differ in many ways, but most thermal specifications publish the range of
allowable package case temperatures in order to ensure that a device is functional (those case temperatures at which the range of functional junction temperatures are not exceeded). In addition, many manufacturers include some
of the following variables:
o
o
o
RaJC
RaJA at various airflows
Maximum ambient air temperature, TA, at various airflows.
As previously stated, many thermal variables are system dependent. In order
to compare ICs on the basis of their published thermal specifications, it is necessary to have knowledge of the system in which such specifications were
measured. Recall that 7/8ths of the thermal resistance of an IC, RaJA, is due
to elements other than that IC. In addition, measurement techniques can affect
thermal resistance values. In general, there are three factors that contribute
to the inability to compare different manufacturers' thermal specifications:
o
o
o
E.3.1
System dependence of RaJA and RaCA
Technique/location for measurement of TA
Definition of Q or P.D
System Dependence of RaJA and RacA
There is presently no industry accepted standard system used for measuring
thermal resistances. Consequently, systems used to measure thermal specifications vary widely between manufacturers with respect to thermal performance. For similar ICs built by different manufacturers, thermal specifications
are often misleading due to the use of differing thermal systems.
o [7]James A. Andrews, "Package Thermal Resistance Model Dependency on Equipment
Design", IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Volume
II, Number 4, December 1988, pp. 536-537.
Thermal Management in Microprocessor-Based Systems
E-9
Thermal Specifications of Integrated Circuits
As stated previously, there are several approaches to publishing thermal specifications: worst case, best case, and somewhere between these two points.
As a result, you need to be cautious when making decisions based on systemdependent thermal resistances such as RSJA and RSCA' If information concerning the system is omitted from a thermal specification, values for RSJA and
RSCA should be disregarded for the purpose of comparison.
E.3.2 Measurement of TA
Recall equation E-2 for thermal impedance, repeated here as equation E-4:
R
S
=
L\T
E-4
0
where L\T is the difference in temperature between a transistor junction and
some reference point. The choice of reference point and its temperature with
respect to the junction is of great importance to the precision of thermal impedance. Holding the junction temperature constant as the reference point's temperature is increased makes the calculated thermal impedance smaller. Most
manufacturers choose the local ambient-air temperature within the system enclosure as the reference point. However, because the local air temperature is
likely to be subject to natural convection and a resulting nonuniformity of temperature, the reference point must be well defined to avoid inaccuracy. When
comparing thermal specifications, the reference point used to calculate thermal impedance has significant effect on the value of thermal impedance. If no
information is included concerning the reference point, absolute comparisons
of thermal specifications must be made cautiously.
E.3.3
Definition of Q
The rate at which energy is converted from electrical energy into heat energy
is known as power (P). P is defined by equation E-5:
P = VCC
x ICC
E-5
For the purpose of thermal-impedance calculations, some manufacturers use
a relationship that describes the typical power dissipation, equation E-6:
= VCC(t) x
P
ICC(t)
E-6
Other manufacturers use the maximum amount of power dissipated, equation
E-7:
P = VCC(m)
x ICC(m)
E-7
where (t) denotes a typical value and (m) is a maximum value. Neither method
is incorrect, but typical power dissipation is significantly lower than maximum
power dissipation in most circumstances. As a result, thermal impedances calculated using typical power dissipation are lower than those thermal impedances calculated using maximum power dissipation. This is because of impedance's inverse relationship with power dissipation or 0, as shown in equation
E-8:
R
S
E-10
= L\T
0
E-8
Thermal Specifications of Integrated Circuits / TI Thermal Specification Methodology
When examining thermal specifications, it is important to know the manufacturer's definition of power dissipation. Often, the equation for power dissipation
is included in either the section pertaining to electrical characteristics or the
thermal specification's definition of variables. If not, use caution when comparing such specifications.
E.4 TI Thermal Specification Methodology
Some manufacturers publish thermal specifications according to typical system conditions in which the IC will be used. Other manufacturers publish thermal specifications for absolute worst-case conditions. Other manufacturers'
thermal specifications are applicable for conditions somewhere between
these two points. In order to ensure the reliability of Texas Instruments microprocessor devices, the thermal specifications are published in accordance
with a realistic worst-case scenario. This means that the data is measured in
a conservative manner, but not so conservative as to hinder its usefulness
when designing microprocessor-based systems incorporating TI devices. The
following paragraphs provide a detailed explanation of how TI obtains thermal
data and the reasons for using such methods.
A thermal test die is mounted in the package to be tested and the package is
mounted on a test board consisting of 0.062 inch thick FR-4 material with oneounce copper etch. The 100-pin QFP (package of the TI486SXLC microprocessor) is soldered to a single-sided test board using matching footprints and
minimal circuit-trace density required to interconnect the device electrically to
the board. The 132-pin ceramic PGA (package of the TI486SXL microprocessor) is inserted in a socket that is soldered to the same test board. As discussed previously, PWB thermal conductivity has a significant effect on the
RSJA value of a device and is proportional to the amount of metal in the PWB
within the projected footprint of the device. It is important to recognize that the
test PWB described above has a minimum amount of routing metal and is
single layer. PWB conductivity is minimized, and the experimentally determined value for RSJA is maximized.
To measure still-air RSJA, the package to be tested and board on which it is
mounted are placed horizontally in a container that has a volume of one cubic
foot of air. Power is supplied to a transistor on the die, and after a thirty-minute
stabilization period, the temperature of the air (T1) and the base-emitter voltage (VBE 1) of the transistor are recorded. Power is supplied to an array of transistors on the die to cause an increase in junction temperature and the baseemitter voltage (VBE2) of the powered transistor is recorded. The package
and board are placed in an oven and the temperature is raised to 90° C, T2 and
another measurement of base-emitter voltage (VBE3) is recorded. Still-air
RSJA can be calculated by substituting the measured variables (T1 , T2, VBE 1,
and VBE3) into equations E-9 and E-10:
- (VBE1-VBE3)
s Iope (T2-T1)
E-9
R
E-10
- (VBE1 - VBE2)
SJA slope
Thermal Management in Microprocessor-Based Systems
E-11
TI Thermal Specification Methodology
For the purpose of measuring RSJC, the package and board are placed in a
bath of moving fluorinert FC-77. After a thirty-minute stabilization period, the
temperature of the fluorinert is recorded (T1) and the voltage across a powered transistor on the test die is measured from base to emitter (VBE1). Power
is then applied to an array of resistors on the test die to produce a subsequent
increase in junction temperature. The voltage across the same transistor from
base to emitter (VBE2) is recorded. The package and board are placed in an
oven at 90° C (T2) and the voltage across the powered transistor is measured
from base to emitter, VBE3. Note that at this point, the resistors are no longer
powered. Once VBE1, VBE2, VBE3, T1, and T2 are known, these values are
substituted into equations E-11 and E-12 to find a value for RSJC. RSJC is independent of the system so system information has been omitted from this explanation. However, the test die that is used within the package must be consistent in size and power dissipation with the actual application die. An example of plotting thermal data is shown in Figure E-S.
- (VBE1-VBE3)
s Iope (T2-T1)
R
E-11
_ (VBE1 - VBE2)
slope
E-12
SJC -
Figure E-S. Plotting Die Thermal Data
VBE1
~
VBE2
VBE3
o
Ambient
~
25
90
T1
T2
Power
Oven
TJ-Junction Temperature of Test Die-oC
To measure RSJA versus airflow, the test package and mounting board are
placed vertically in a calibrated wind tunnel as shown in Figure E-6. A temperature probe and anemometer-type airflow probe are located towards the front
end of the tunnel. A fan is mounted at the rear of the tunnel. Its airflow is directed away from the wind tunnel to induct air from the front of the tunnel to
the rear. At various controlled rates of airflow, the voltage is measured across
a powered transistor on the test die (VBE1). The temperature in the tube is recorded as T1. An array of resistors on the test die is powered to cause an increase of temperature across the die. The voltage is again measured across
E-12
TI Thermal Specification Methodology
the same transistor (VBE2). The device is removed from the wind tunnel,
placed in an oven at 90° C (T2), and only the transistor is powered. The voltage
from base to emitter on the transistor is measured (VBE3). As in the procedure
for RSJC, the experimental values are substituted into equations E-9 and
E-10 (page E-11 ) to find the value for the slope and RSJA for a specific airflow.
Figure E-6. Wind Tunnel Schematic Diagram
Device Test Board
Temperature and
Anemometer-Type
Airflow Probe
>
AirflOW>
Fan
Wind Tunnel Cross-Section is 6 in by 6 in.
~ 5 in ---I~I.I--- 24 in -~:I
.....
~--------------------------78in--------------------------~
(Dimensions are approximate.)
The procedures described above are relatively consistent across the industry
with the exception of the test-board specifications and the measurement location of T1. In the test-board specification the thermal conductivity is of great
importance to the experimentally determined value of RSJA. As shown in
Table E-3 (page E-7), a 4-layer FR-4 PWB is approximately 89 times as thermally conductive as a single layer PWB with no copper. It is not uncommon to
find 8 or more layers in a microprocessor PWB. TI uses a single-sided test
board with only one ounce of copper etch as opposed to a typical application
multilayer PWB with a much higher content of copper etch and consequently,
better thermal conductivity.
The RSJA values reported by TI should be viewed as worst-case versus typical
for an application. The ambient temperature location is measured and is not
affected by an increase in operational case temperature as would occur in a
typical closed-system-case application. Such a measurement of ambient temperature allows for a greater difference or delta between the junction temperature and the measurement reference point and, as a result, a higher value of
RSJA. When comparing RSJA values from Texas Instruments with other
manufacturers, it is important to understand the test conditions of each before
drawing conclusions regarding which unit offers the best thermal performance.
Thermal Management in Microprocessor-Based Systems
E-13
Guidelines / Current Trends and Theory of Correction
E.S Guidelines
Because of the possibility of disparity in generating thermal specifications, it
is often difficult to compare similar parts produced by different manufacturers.
To ensure the validity of a comparison between the thermal specifications of
several devices, these guidelines should be followed:
o
Ensure that the system is the same for all devices to be included in the
comparison. If the system is not the same, only consider values for ReJc,
ReCA and ReJA values should be disregarded because oftheir system dependence.#
o
Disregard from the comparison those devices whose thermal impedances
were obtained using different reference points. Remember that ~T decreases as the reference temperature increases (holding the junction temperature constant), and that thermal impedance is proportional to ~T. An
increase in ~T (or a decrease in the measured reference temperature)
causes a resulting increase in the calculated thermal impedance.
o
Include only those devices with like definitions for power dissipation. Higher values for P result in lower values of calculated thermal impedance.
Typical power dissipation (the product of typical V CC and typical ICC) is significantly lower than maximum power dissipation (the product of maximum VCC and maximum ICC)'
E.6 Current Trends and Theory of Correction
The dilemma concerning thermal specifications and the incompatibilities between manufacturers has not gone unnoticed. The JEDEC JC-15 committee
has developed objectives for standardizing electrical and thermal modeling
and measurements for IC packages and interconnects. A task force, designated JC-15.1 , was originated to accomplish two of the above goals by the following actions:
o
o
Propose a standard board for device thermal-resistance measurements
Provide a standard measurement to which actual thermal-modeling measurements can be compared
Companies often use varying systems and measuring techniques for the purpose of obtaining thermal-resistance measurements of ICs. To cope with
these variances, JEDEC JC-15.1 is proposing a board layout to standardize
thermal-resistance measurements. The proposed board (3" by 4.5") ~contains
only the device to be characterized with a minimum amount of metal. If widely
accepted within the semiconductor industry, such a board definition could provide improved validity when comparing integrated-circuit thermal specifications.
# Jack Belani and B.J. Shanber, "Impact of Packaging Materials on Semiconductor Thermal
Management", Third Conference of Electronic Packaging: Materials and Processes &Corrosion
in Microelectronics, Minneapolis, Minnesota, April 28-30, 1987, pp. 113-115, 118.
E-14
Conclusions
E.7 Conclusions
In summary, the thermal impedance of an integrated circuit within a system is
divided into two components: Rei and Rex or ReJC and ReCA' ReJC or Rei account for only about 118th of the total thermal resistance of an IC within a system. ReCA or Rex is responsible for 7/8ths of the total thermal resistance. The
total thermal resistance of an IC within a system, often referred to as ReJA, is
significantly dependent on the system's thermal performance. The system
thermal performance can be attributed to several factors:
o
o
Proximity of ICs on the PWB and total component density of the PWB
o
Presence andlor amount of forced convection
PWB thermal conductivity
Thermal specifications of ICs include one or more of the following variables
versus airflow: ReJC, ReJA, and TA(m)' ReJA is dependent on the system. To
make a valid comparison of multiple manufacturers' thermal specifications for
similar parts, thermal specifications must meet the following guidelines:
o
Identical systems (Le., PWB thermal conductivity, airflow)
o
o
Similar reference points for thermal-impedance calculation
Like definitions of P
Because of the current problems surrounding thermal specification comparisons, JEDEC has provided a task force, JC-1S.1 , to develop and maintain a
standard-PWB definition for the purpose of measuring thermal resistances to
be included in thermal specifications. Until such a method is adopted industry
wide, the discussed guildelines should be followed to assure valid thermalspecification comparisons.
Thermal Management in Microprocessor-Based Systems
E-15
E-16
Appendix F
Ordering Information
F.1
Part Number Components
Components of the TI486SXL( C) family of microprocessor part numbers are
diagrammed in the following example.
EXAMPLE: - - -..~.TX486SXLC
B
-
V
25
GA
I
Device Name:
SXLCB = 16-bit I/O
SXLB = 32-bit I/O
SXLC2 and SXL2 are clock doubled
Device Revision level: _ _ _ _ _ _ _- . . 1
Supply Voltage:
0=5 V
V = 3.3 V
G = 3.3 V with 5-V-tolerant inputs
Speed:
25 = 25 MHz
33 = 33 MHz
40 = 40 MHz
50 = 50 MHz
Package Type:
HBN = 144-Pin Ceramic Quad Flat Package
GA = Ceramic Pin Grid Array (S-GA = 132 pins for the TI486SXL family)
PJF = Thermally Enhanced 100-Pin Plastic Quad Flat Package
PCE = Themally Enhanced 144-Pin Plastic Quad Flat Package
F-1
Part Numbers for Microprocessors Offered
F.2
Part Numbers for Microprocessors Offered
Table F-1 lists the complete part number for each version of the TI486SXL microprocessors offered, and Table F-2 lists the part number for each version
of the TI486SLC/DLC microprocessors .offered. The tables provide a short description consisting of the supply voltage, performance capabilities, and the
mechanical package for each device part number.
Table F-1. TI486SXLC and TI486SXL Part Numbers
Speed (MHz)
Device Part Number
Supply Voltage (V)
Core
Bus
TX486SXLCB-V25-PJF
3.3
25
25
TX486SXLCB-040- PJ F
5
40
40,20t
Package
1~O-pin TEP plastic
QFP
TX486SXLC2B-050-P J F
5
50
25
TX486SXLB-040S-GA
5
40
40,20t
TX486SXL2B-050S-GA
5
50
25
TX486SXLB-040-PCE
5
40
40,20t
144-pin TEP plastic
QFP
TX486SXL-G40-HBN
3.3-V, 5-V tolerant
40
40,20t
TX486SXL2-G50-HBN
3.3-V, 5-V tolerant
50
25
144-pin ceramic
QFP
TX486SXLB-040-H BN
5
40
40,20t
TX486SXL2B-050-H BN
5
50
25
TX486SXL-G40-GA
3.3-V, 5-V tolerant
40
40,20t
TX486SXL2-G50-GA
3.3-V, 5-V tolerant
50
25
TX486SXLB-V40-GA
3.3
40
40,20t
TX486SXL2B-V50-GA
3.3
50
25
TX486SXLB-040-GA
5
40
40,20t
TX486SXL2B-050-GA
5
50
25
132-pin PGA
168-pin PGA
t These microprocessors can be operated as nonclock-doubled 40 MHz or clock-doubled 20/40 MHz.
F-2
Part Numbers for Microprocessors Offered
Table F-2. TI486SLCIE and TI486DLCIE Part Numbers
Supply Voltage
(V)
Speed (MHz)
TI486SLC/E-033C-P J F
5
33
TI486SLC/E-V25C-PJF
3.3
25
TI486SLC/E-040C-PJ F
5
40
TI486DLC/E-033C-GA
5
33
TI486DLC/E-040C-GA
5
40
Device Part Number
TI486DLC/E-033C-PCE
5
33
TI486DLC/E-040C-PCE
5
40
Package
1~O-pin TEP plastic
QFP
132-pin ceramic PGA
144-pin TEP plastic
QFP
Ordering Information
F-3
F-4
Appendix G
Glossary
2-way set associative: In a 2-way set associative cache, an index identifies
two lines of data (i.e., only two members of a set may exist in cache at
a given time). This design provides significant performance improvement in comparison to direct mapped caches as measured by the hit ratio. (See set associativity.)
A20M:
When bit 2 of CCRO is true, the A20M# pin is enabled.
Note:
The A20M# pin is an anomoly occurring in PC designs as a result of the fact
that truncated addresses can be generated by an 8086/8088 outside the
physical address range.
A:
AC:
Accessed/nonAccessed bit. Segment descriptor bit 8.
The Alignment-Check enable flag verifies that computer-word bits are
aligned with respect to significance.
address: Each byte of memory is assigned a specific address space. The
amount of addressable memory space depends on the width of the CPU
address bus. The TI486SXLC has a 24-bit address bus, and the
TI486SXL has a 32-bit address bus.
AF:
AM:
The Auxiliary carry Flag is set when an operation results in a carry out
of ( addition) or borrow into ( subtraction) bit position 3. Otherwise it is
cleared.
Alignment-check Mask bit. CRO bit 18.
ARR1 through ARR4: Address Region registers 1 through 4 define the
location and size of the memory regions associated with the internal
cache. These registers are unique to the TI486SXL(C) microprocessors.
asserted:
When a signal is asserted, it is logically true.
G-1
Glossary
AVaiLable bit. Segment Selector register bit 20.
AVL:
bandwidth:
Bandwidth is how much information can be transferred during
a period of time. As an example, video, which requires a maximum bandwidth of 80 megabytes per second (MBps), takes advantage of the 132
MBps transfer rate provided by the VESA-VL or PCI bus.
BARB:
When bit 5 of CCRO is set (high), the BARB bit enables flushing of
the internal cache when a hold state is entered.
base:
The base is the beginning of some segments (extra data, code, or
data segments) or the beginning address provided in some registers
(CC3, GOTR, IDTR, or SO).
BIOS:
The Basic Input Output System is a set of routines that contain detailed instructions for activating computer and peripheral devices. The
BIOS is normally implemented in nonvolatile memory.
bit:
A bit is the fundamental unit of computer memory. A bit can be a 1 or a
o. A byte is made up of eight bits.
breakpoint:
A breakpoint can be embedded within a program to temporarily
stop execution so that machine status may be determined.
byte:
A byte is made up of eight bits and basically represents one character
of information.
C/O:
Expand segment upper limit or lower limit bit. Segment descriptor bit
10.
cache:
A cache is a small, high-speed memory used to provide a temporary
storage location for data most likely to be requested by the CPU. This allows for quick access of data and improved CPU performance (Le., zero
wait states).
cacheable:
A memory location is cacheable if the system allows data at this
location to reside in the cache.
cache addressing:
Cache addressing is performed by dividing the physical
address into an index field, a tag field, and a byte select field. A valid field
indicates whether the cached data at that physical address is currently
valid.
cache (data) coherency:
Data coherence is necessary when a system has
multiple memories. If several memories contain the same data word, modifying that data word in one memory causes the data to be incoherent
with the data stored in the other memories. Therefore, the other memories that have a copy of that same data word must either update or invalidate their copy. If this is not done, data remains inconsistent or incoherent.
G-2
Glossary
cache flush: Cache flush is a method used to maintain cache consistency
in which all locations with dirty bits are written to main memory. Then, the
cache contents are cleared (flushed).
cache hit: A cache hit is said to occur when data being requested by the
CPU resides in cache.
cache miss: A cache miss is said to occur when data being requested by
the CPU does not reside in cache.
cache tag address: The cache tag address contains the high-order bits of
the physical address of the associated data stored in the cache.
CCRO, CCR1: Configuration Control register 0 enables certain functions
associated with cache control, suspend mode, and the clock-doubled
mode. Configuration Control register 1 is used to set up internal cache
operation and system-management mode. These registers are unique
to the TI486SXL(C) microprocessors.
Cache Disable bit. CRO bit 30.
CD:
CF:
The Carry Flag is set when an operation results in a carry out of ( addition) or borrow into ( subtraction) the most significant bit. Otherwise it is
cleared.
CKO:
Enable Clock Doubled. CCRO bit 6.
clock doubled: When the microprocessor is in clock-doubled mode, the internal core is operating at the CLK2 frequency while the external bus interface remains at half the CLK2 frequency.
clock scaling: The TI486SXL(C) microprocessor family supports dynamic
clock scaling that enables the CLK2 input to be scaled up or down.
clock speed: Clock speed is the speed at which the CPU operates, typically
measured in megahertz (MHz).
CISC: A Complex Instruction Set Computers is a type of computer architecture that requires multiple clock cycles per instruction but offers many
specialized instructions for programmers.
conventional memory: The DOS memory which occupies the addresses
between 0 and 640 KB and is available to the user or software programs.
coprocessor: A coprocessor is an external processor that can be operated
in parallel with the CPU to relieve the CPU loading. The TI486SXL(C) microprocessors are designed to interface to a coprocessor.
CPGA: A Ceramic Pin Grid Array package consists of ceramic substrates to
hermetically enclose the IC and an interconnection scheme that presents male leads extending from the bottom of the package.
CPL: The Current Privilege Level is the privilege level of the current operation.
CPU: The Central Processing Unit is the execution unit of the microprocessor. It consists of control, shift, adder, multiplier, and limit units and a register file.
Glossary
G-3
Glossary
CRO, CR2, CR3:
Control register 0 contains system control flags and indicates the general state of the CPU. The lower 16 bits are referred to as
the machine status word. When paging is enabled and a page fault is
generated, Control register 2 retains the 32-bit linear address of the address that caused a fault. Control register 3 contains the 20-bit base address of the page directory.
CS:
D:
In real and virtual-8086 operating modes, the Code Segment register
holds a 16-bit segment base. In protected mode, the Code Segment register holds a segment selector.
Defaultlength bit for operands and addresses. Segment descriptor bit 22.
deasserted:
When a signal is deasserted, it is logically false (not true).
descriptor:
A segment descriptor is a data structure that defines a segment's base, limit and attributes.
DF:
The Direction Flag, when cleared, causes string instructions to autoincrement (default) the appropriate Index registers ( ESI and/or EDI).
Setting OF causes auto-decrement of the Index registers.
direct mapped cache:
A direct mapped cache is the simplest form of set
associative cache architecture, one-way set associative. In a direct
mapped cache, an index identifies only one line of data (i.e., only one
member of a set may exist in cache at a given time). Therefore, only one
address comparison is required to determine if the requested word is in
the cache.
direct memory access (DMA):
Direct memory access allows data to be
transferred between a device and memory without the constant control
of the CPU. DMA permits two operations to be executed simultaneously.
As an example, the CPU can access the cache while DMA allows a peripheral to access the main memory.
disk drive controller:
When the microprocessor requests information or a
software application, a copy of it is transferred from storage (disk drive,
floppy drive, or CD-ROM) into RAM by the disk drive controller.
displacement:
Displacement is a value, of up to 32 bits in length, that is supplied as part of the instruction. The displacement is used as the address
in direct address mode and is added to based, index, scaled index,
based index with displacement, and based scaled index with displacement address modes.
DNA:
Device Not Available fault.
DOS memory: DOS memory is limited to 1 MB of memory unless using applications that take advantage of extended or expanded memory.
DP:
G-4
Displacement
Glossary
DPL:
Descriptor Privilege Level field. Gate or segment descriptor bits
14-13.
DRAM: Dynamic Random Access Memory are volatile memory chips that
use capacitors to store information as an electrical charge. They offer
high density at a low cost, but they must be refreshed frequently which
makes them relatively slow.
drive controller board:
See disk drive controller.
DRO through DR7: Debug registers Othrough 7 contain memory addresses
and breakpoints used to support debugging of the microprocessor.
DS:
In real and virtual-BOB6 operating modes, the Data Segment register
holds a 16-bit segment base. In protected mode, the Data Segment register holds a segment selector.
DT:
Descriptor Type bit. Segment Selector register bit 12.
DTE:
The Directory Table Entry is selected from the directory table by the ten
most-significant bits of the linear address and contains the starting address of the second-level page table.
DTI:
The Directory Table Index acts as a 32-bit master index to up to 1K individual second-level page tables.
E:
Application descriptor bit. Segment descriptor bit 11.
EAX, ESX, ECX, EDX, ESI, EDI, ESP, ESP:
register set.
The ExtendedGeneral Purpose
EFLAGS: The Extended Flag Word register contains status information and
controls certain operations on the microprocessor. The lower 16 bits of
this register are referred to as the Flag register.
EGA:
EIP:
Enhanced Graphics Adapter is a video standard for IBM-compatible
PCs named after a particular video adapter that was the standard for the
IBM PC-AT.
The (extended) Instruction Pointer register contains the offset into the
current code segment of the next instruction to be executed.
EPROM: Electrically Programmable Read-Only Memory is a permanent
memory used for items such as the BIOS instructions which occupy the
reserved address space in DOS systems. EPROM access times tend to
be long, but, being non-volatile, they are used primarily for initialization.
If higher performance is required, the EPROM contents can be copied
to DRAM memory. This technique is called shadowing.
EM:
EPL:
EMulate processor extension. CRO bit 2.
The Effective Privilege Level protects memory from being accessed by
privilege levels that are lower than the descriptor privilege level.
Glossary
G-5
Glossary
The Extra Segment register is the destination of STOS, MOVS, REP
STOS, and REP MOVS instructions. Special segment override prefix ES
allows the use of this additional Segment register.
ES:
expanded memory:
Borrows addresses from reserved DOS memory to
point to additional memory as a means of getting around the 1 MB DOS
memory limit.
extended memory:
Used by software applications, such as Windows or
OS/2, to get around the 1 MB DOS memory limit.
far jump:
A far jump is ajump whose destination is in another code segment.
fast IDE:
Fast IDE provides data transfer of 16-bit wide data at speeds of up
to 13 MBps.
flash memory:
Flash memory cards are designed for program storage, can
be used in floppy and solid-state applications, and are ideal for applications that require frequent updates.
float:
A condition during which all 3-state bidirectional and output terminals
are placed in a high-impedance state to electrically isolate the microprocessor from the system.
flush:
Flushing the cache invalidates the entire contents of the cache
memory.
footprint compatible:
A device packaged to be compatible for installation
in existing boards/systems.
FPU:
A Floating Point Unit is used to accelerate the computation of floatingpoint arithmetic. If a PC does not have an FPU, the CPU emulates floating-point instructions which takes more time to execute.
FS:
Additional Data Segment register. Special segment override prefix of FS
allows the use of this additional Segment register.
fully associative:
Fully associative is the most flexible type of cache placement policy. There is no single relationship between all of the addresses.
The cache has to store the entire address of each block of words and
compare its address with each of those in the cache until itfinds a match.
G:
GO:
Limit Granularity bit. Segment descriptor bit 23.
When set, the Global Disable bit denies access to the Debug register.
GOT: The Global Descriptor Table is part of the selector mechanism and
contains segment descriptors that are used when the TI bit in the Segment Selector register is set to zero.
G-6
Glossary
GOTR: The Global Descriptor Table register holds a 32-bit base address and
16-bit limit for the global-descriptor table.
graphic accelerators: Graphic accelerators have special circuitry which
speeds up image processing. The CPU sends commands to the accelerator which executes them rather than having the CPU manipulating and
sending data to the adapters. Objects are drawn on the screen rather
than being transferred pixel by pixel. This reduces the amount of data
that is transferred across the processor bus.
graphic adapter: A graphic adapter translates the instructions from the
CPU into information that the PC monitor can understand. Graphic
adapters before and including VGA rely on the CPU to perform operations that manipulate the display image. Advanced adapters, that handle
more data, have circuitry to speed up image processing directly on the
graphic adapter card.
graphic coprocessor: A graphic coprocessor is fully programmable making it more flexible than a graphic adapter.
graphics mode: Graphics mode is a video mode that divides images into
thousands of dots, or pixels, to create text and detailed images.
GUI:
Graphical Users Interface is a feature of some software applications
that permits the user to interact with the computer by using icons and
small graphics rather than by using text and commands.
green PC: A green PC is an environmentally correct PC that reduces power
consumption (currently by as much as 800/0 when compared to current
models). This guideline resulted from the Environmental Protection
Agency's Star program.
GS:
Additional Data Segment register. Special segment override prefix of
GS allows the use of this additional Segment register.
III
hard drive controller:
See disk drive controller.
hot insertion (or hot swapping): Plugging or unplugging PC cards without
disrupting the host system's operation. Typical associated with PCMCIA.
D
IDE:
lOT:
Integrated Device Electronics
The Interrupt Descriptor Table is an array of up to 256 8-byte interrupt
descriptors, each of which points to an interrupt service routine.
IOTR: The Interrupt Descriptor Table register holds a 32-bit base address
and 16-bit limit for the interrupt-descriptor table.
IF:
When the Interrupt Flag is set, maskable interrupts ( INTR input pin) are
acknowledged and serviced by the CPU.
Glossary
G-7
Glossary
index:
An index is a reference or initial value.
instruction: An instruction is a machine-language command to the CPU.
The TI486SXL(C) instructions are described in detail in Chapter 7,
Instruction Set.
instruction set: The instruction set consists of machine-language instructions that the architecture of the TI486SXL(C) CPU can execute.
integrated device electronics: The IDE interface is based on the ISA bus,
using the set of registers and commands originally used by the IBM AT.
This interface is the current favorite among most disk drive makers for
hard disks because they are inexpensive and have a low command overhead. Drives using IDE interfaces integrate the controller and drive in
one, making them more efficient than older drives. Therefore IDE drives
and controllers do not need to translate commands from your PC. IDE
provides data transfer of 8-bit wide data at speeds of up to 5 MBps. Fast
IDE provides data transfer of 16-bitwide data at speeds of upto 13 MBps.
INTR: An Interrupt is a signal generated by external hardware that changes
the normal sequential flow of a program by transferring program control
to a selected service routine.
10PL: The Input/Output Privilege Level indicates the maximum current privilege level (CPL) permitted to execute liD instructions and indicates the
maximum CPL allowing alteration of the IF bit.
1/0:
Input/Output
1/0 bus (peripheral or system bus):
The liD bus is used to communicate
with the various liD or peripheral devices being used. Using this bus
avoids loading down the time-critical local or processor bus with the I/O
or peripheral devices.
1/0 Controller:
Most liD devices have a controller that acts as its supervisor
and interfaces with the CPU. The controller can be either built into the
system board or on a separate adapter that is plugged into the system
bus. Some controllers have their own special-purpose processors and
some even have their own memory.
1/0 device interface:
The liD device or peripheral interface is an essential
part of any PC as it supports the communication between the CPU and
the device or peripheral.
1/0 mapped:
The simplest architecture uses I/O mapped devices. liD devices are mapped into the programmed liD address space. Address decoding is easier since fewer address lines must be decoded.
KEN:
G-8
When bit 3 of CCRO is true, the KEN# pin is enabled.
Glossary
II
LOT:
The Local Descriptor Table is part of the selector mechanism and contains segment descriptors that are used when the TI bit in the Segment
Selector register is set to one.
LOTR: The Local Descriptor Table register holds a 16-bit selector for the local-descriptor table.
A limit defines the maximum range.
limit:
line:
A line is the fixed unit of information transfer between cache and main
memory.
line size: Line size refers to the amount of information in a line and is defined
as a number of bytes. Line size is one of the parameters that most strongly affects cache performance as it represents the amount of data the
cache must retrieve during each cache line replacement (every cache
miss).
linear address: In real mode, the offset address is added to the product of
the segment register multiplied by sixteen to produce the linear address.
This linear address is the physical address.
In protected mode, the offset address is added to the base address to
produce the linear address. If paging is disabled, the linear address is the
physical address. If paging is enabled, the linear address is translated
by the paging mechanism into the physical address.
local bus: The local bus connects peripherals directly to the CPU and is designed to transmit 32-bit data at the speed of a PC's processor. Two local
bus standards are VESA-VL and PCI.
locality: Locality refers to the fact that programs usually address memory
in the neighborhood of recently accessed locations.
LRU:
The Least-Recently Used bit indicates which of the cache two-way
sets was more recently accessed.
iii
math coprocessor:
See FPU.
MBps:
Mega Bytes Per Second
Mbps:
Mega Bits Per Second
memory mapped: I/O devices can be mapped into physical memory addresses. Even though more addresses must be decoded with this interface, memory-mapped devices can be accessed using CPU instructions
allowing for more efficient code. Memory mapping also offers more flexibility in protection than I/O mapping through memory management since
a device can be inaccessible/fully accessible or visible but protected.
Very few peripherals use memory-mapped ports except for video cards.
Glossary
G-9
Glossary
MMAC: Main Memory Access. A memory access stores or retrieves data to
or from main memory.
modem: A modem translates (MODulates) computer signals into tones and
translates (DEModulates) tones back into computer signals.
monochrome:
MP:
A video mode that uses only one color in varying intensities.
Monitor Processor extension bit. CRO bit 1.
multithreading: Multithreading is a software technique that allows an application to split tasks into subtasks, or threads, for improved speed and
efficiency. This feature is supported by Windows NT as a way of speeding up Windows and reducing the chances of a system crash.
m
NCO:
Non-Cacheable O. NCO is bit 0 in the Configuration Control register o.
When set, this bit sets the first 64K bytes at each 1M-byte boundary as
noncacheable.
NC1:
Non-Cacheable 1. NC1 is bit 1 in the Configuration Control register o.
When set, this bit sets sets 640K-byte to 1M-byte memory region as noncacheable.
NC (Terminal designator):
negated:
NMI:
Make No external Connection.
Logically false, not true.
The NonMaskable Interrupt is a rising-edge-sensitive input that, when
asserted, causes the processor to suspend execution of the current
instruction stream and begin execution of an NMI interrupt service routine.
noncacheable memory: In noncacheable memory systems, all shared
memory locations are considered noncacheable. Access too the shared
memory is never copied to the cache, and the cache never receives stale
data.
nonprogrammer visible: Nonprogrammer visible pertains to the contents
(data, address components, and current states) of registers and stored
data that cannot be accessed, trapped, or retrieved.
nonvolatile memory: A nonvolatile memory, like ROM and EPROM, is a
memory in which the data content is maintained whether the power supply is connected or not.
G-10
NT:
The Nested Taskflag, while executing in protected mode, indicates that
the execution of the current task is nested within another task.
OA:
Offset Address. The offset address is the result of an offset calculation.
Base address, index address, scale factor, and displacement are the
components used, in various combinations, to calculate the offset address.
Glossary
OF: The Overflow Flag is set if the operation resulted in a carry or borrow into
the sign bit of the result but did not result in a carry or borrow out of the
high-order bit. It is also set if the operation resulted in a carry or borrow
out of the high-order bit but did not result in a carry or borrow into the sign
bit of the result.
opcode: The physical implementation of an instruction in machine-readable
code.
os:
P:
An Operating System is a master control program that supervises the
functions and components of a computer system.
A Prefix bit in a prefix byte.
or
Present bit. Gate or segment descriptor bit 15.
paging: Paging is a memory management technique that provides direct access to small portions of stored data within a large segment of virtual
memory space. Paging is very useful in minimizing the amount of physical space required to service active routines.
parallel port: A parallel port is used mostly by the computer to send out data
to be printed. A parallel port moves data in bytes (8-bits wide) or words
(16-bits or 32-bits wide) depending on the application.
parity bit:
The eighth bit or extra bit that is used to help detect errors.
PCO:
The Page-level Cache Disable bit is located in Test register 7. This bit
corresponds to the PCD bit of a page-table entry.
PCI:
The Peripheral Component Interconnect standard is a board-level
local-bus implementation for high-end PC applications. PCI is a fully independent bus that requires a PCI bridge to establish communication
with the CPU bus. PCI is fully independent from the CPU and the CPU
timing and PCI can be used with non-X86 systems. PCI multiplexes addresses and data to reduce the number of required pins. Each card is
uniquely identified by a special code allowing for autoconfiguration.
PCMCIA: The Personal Computer Memory Card International Association
peripheral bus standard provides a way for the portable computer user
to expand the memory, storage, communication, and other capabilities
that are common to the desktop PC user. There are several types of
PCMCIA cards: DRAM, flash memory, hard-disk drives, LANs, and modems. The cards can be plugged into the expansion slot without opening
the computer.
POBR: The Page-Directory Base register is located in Control register 3.
The register contains the 20-bit base address of the page directory.
PE:
Protected mode Enable bit. CRO bit O.
peripheral bus:
See I/O bus.
Glossary
G-11
Glossary
peripherals: Peripherals are the external devices such as printers, fax
machines, modems, and etc.
peripheral interface: The I/O device or peripheral interface is an essential
part of any PC since it supports the communication between the CPU
and the peripherals.
PF:
The Parity Flag is set when the low-order 8 bits of the operation result
contain an even number of ones. Otherwise it is cleared.
PFO:
The Page-Frame Offset is part of the paging mechanism. The physical
page frame data is selected by the first 12 bits of the linear address.
PG:
PaGing enable bit. CRG bit 31.
PGA:
A Pin Grid Array package consists of substrates to hermetically enclose the IC and an interconnection scheme that presents male leads extending from the bottom of the package.
physical address: When paging is disabled the 32-bit linear address is the
physical address. When paging is enabled it translates the linear address into a physical address. The physical address appears on the pins
of the CPU.
pipelined addressing: Pipelined addressing allows bus cycles to be overlapped, increasing the amount of time available for the memory or I/O device to respond. The NA# input to the CPU controls address pipelining.
pipelining: A series of suboperation stages, like fetching, decoding, execution, and address translation. Pipelining results in a continuous execution rate of one instruction per clock cycle.
pixel: The smallest information building block of an on-screen image. On a
color monitor, each pixel is made up of one or more triads. Resolution is
usually expressed in the number of pixels making up the width and height
of a complete on-screen image.
PL:
The Privilege Level implements a protection scheme. The values for
privilege levels are 0 to 3. Level 0 is the most privileged and 3 the least
privileged.
PLL:
Phase-Locked Loop. In the TI486SXL(C) microprocessor, a PLL is
used to implement clock synchronization.
posted write: In a write-through cache, read cycles are accelerated but
write cycles are not. Through the use of a write buffer, write cycles can
also be accelerated. The process of buffering or storing address and
data in a write buffer is referred to as a posted write or buffered write.
power management: A feature of some CPUs that shuts down parts of the
computer not being used to save power.
G-12
Glossary
PQFP: The Plastic Quad Flat Package consists of a metal substrate, IC, and
interconnection scheme that presents leads extending from the four
sides of the plastic encapsulated package. The leads are formed, using
a double break, to create a planar foot on each lead that supports the
package body above the seating plane. The thermally enhanced package includes a metal plate or slug near the mounting surface that enhances heat dissipation.
prefix:
Prefix bytes can be placed in front of an instruction to override segment defaults, change operand and/or address-size attributes, assert
LOCK#, and repeat string instructions.
privilege level:
In the protected mode, privilege levels control the use of
privileged instructions, I/O instructions, and access to segments and
segment descriptors.
programmer visible:
Programmer visible pertains to the contents (data,
address components, and current states) of registers and stored data
that can be accessed, trapped, or retrieved.
protected mode:
The microprocessor is in protected mode when the PE bit
of Control register 0 is set. In protected mode, the enhanced memory
management capabilities, which include segmentation and paging, are
available. Code has one of four privilege levels, with some processor
instructions restricted to the most-privileged code.
PTE: The Page Table Entry, selected from the page table by bits 21-12 of
the linear address, contains the base address of the desired page frame.
PTI: The Page Table Index acts as a 32-bit master index to up to 1K individual page frames.
PWT: The Page-level cache Write Through bit in Test register 7 enables or
disables this cache function. This register bit corresponds to the PWT bit
of a page-table entry.
m
QFP:
R:
A Quad Flat Package consists of a substrate, IC, and interconnection
scheme encapsulated in plastic or enclosed with metal that presents
leads extending from the four sides of the package. The leads are
formed, using a double break, to create a planar foot on each lead that
supports the package body above the seating plane. There is a metal
and a plastic version of this package type.
Opcode or register bit.
RIW:
Read/Write.
or
Readable/Writable or nonreadable/nonwritable bit. Segment descriptor
bit 9.
Glossary
G-13
Glossary
real memory: The memory that actually exists in the PC, or memory that is
not borrowed from an external source.
real mode: The TI486SXL(C) powers up or resets to real mode. In real
mode, conditions are established that make the microprocessor backward compatible with 8086/8088 microprocessors. No hardware protection is provided for segment access or use and there is no privileged
code.
RF:
The Resume Flag is used in conjunction with Debug register breakpoints. It is checked at instruction boundaries before breakpoint exception processing. If set, any debug fault is ignored on the next instruction.
RISC: A Reduced Instruction Set Computerarchitecture is a type of computer that executes instructions in one clock cycle by limiting the number of
instructions that are available.
ROM: A Read Only Memory is a permanent, unchangeable memory used
in the PC to accomplish system startup. It stores the BIOS programs
needed to perform diagnostics and instruct the computer in various operations. When using DOS, the contents of the ROM are placed in reserved memory.
RPL:
The Requested Privilege Level field. Segment Selector register bits
1-0.
scale factor: The Scale Factor is a factor (1, 2, 4, or 8) by which the index
address is multiplied when the offset mechanism calculates the offset address.
SCSI: The Small Computer System Interface offers hard disk data transfer
rates of up to 10 MBps.
segmentation: Segmentation is a memory management technique that
permits application-specific segmentation to improve the efficiency of
memory space utilization.
serial port: A serial port is a communication path based on a standard convention of transmitting two-way asynchronous serial data. A serial port
moves data one bit at a time and can be half duplex (one direction at a
time) or full duplex (both directions simultaneously).
serialization: Serialization takes byte-wide data as input and provides serial
bits in a stream as output.
set associativity: Set associative is a type of cache placement policy that
has more than one set of direct mapped caches operating in parallel. For
each cache index there are several block locations allowed. The block
can be placed in and retrieved from any set. This type of cache performs
more efficiently than a direct mapped cache, but it needs a wider tag field
and additional logic to determine which set should receive the data.
G-14
Glossary
SF:
Scale Factor
or
The Sign Flag is set equal to the high-order bit of the operation result ( 0
indicates positive, 1 indicates negative).
shadowing: Shadowing is a technique used to improve system performance by copying the contents of ROMs or EPROMs into DRAM to
achieve faster access.
s-i-b byte:
This byte includes the Ss, Index, and Base fields
SIMM: A Single In-Line Memory Module is a packaging technique for
memory modules.
SM4:
System Management access region 4, sometimes called Address Region register 4. SMM memory space is defined by assigning address region 4 to SMM memory space.
SMAC: In normal mode, SMADS# address strobes are generated instead
of ADS# for System-management Memory Accesses.
SMI:
A System Management Interrupt causes the microprocessor to enter
the system management mode that allows various subsystems of the
computer to be powered down under certain conditions. The systemmanagement interrupt has a higher priority than any other interrupt, including NMI.
SMM: The System Management Mode is a power management feature that
allows various subsystems of the computer to be powered down when
not in use to conserve power.
snooping: Snooping is a method used to maintain cache consistency. The
cache controller monitors the bus lines to detect any shared locations
that are written by another processor. When a common cache location
is found, it is invalidated and cache consistency is maintained.
SS:
The Stack Segment register contains segment selectors that index into
tables located in memory. These tables hold the base address for each
segment as well as other information related to memory addressing.
SRAM: A Static Random Access Memory is a high performance storage medium that does not require refresh.
SUS:
The SUSpend bit in Configuration Control register 0 enables or disables the SUSP# and SUSPA# pins that control entry into the suspend
mode.
system bus:
See liD bus.
o
T:
Opcode bit.
Glossary
G-15
Glossary
T1:
T1 P:
The first clock of a non-pipelined bus cycle.
The first clock of a pipelined bus cycle.
T2:
Subsequent clocks of a nonpipelined bus cycle. NA# has not been
sampled asserted.
T21:
Subsequent clocks of a pipelined bus cycle. NA# has been sampled asserted.
T2P:
Subsequent clocks of a pipelined bus cycle. NA# has been sampled asserted.
tag:
A tag is a directory that records what data is currently being stored in
a cache.
TEP:
The Thermally Enhanced Plastic package includes a metal plate or
slug near the mounting surface that enhances heat dissipation.
text mode:
A video mode that divides the screen into character positions.
TF:
Once the Trap enable Flag is set, a single-step interrupt occurs after the
next instruction completes execution. TF is cleared by the single-step interrupt.
Th:
A hold acknowledge state.
TI:
Table Indicator bit. Segment Selector register bit 2.
Ti:
A bus Idle state.
TLB:
The Translation Look-Aside Buffer is an on-chip, four-way, setassociative, 32-entry page-table cache. This buffer contains the most recently accessed pages which reduces the average time required to make
virtual memory references.
TR:
The Task register holds a 16-bit selector for the current task-state segment (TSS) table. The TR is loaded and stored using the LTR and STR
instructions, respectively.
TR3 through TR7:
G-16
Test registers 3 through 7.
Glossary
transfer rate:
Transfer rate is the rate at which data is moved from one component to another and is usually measured in megabits per second
(Mbps) or megabytes per second (MBps). Some examples follow.
System Buses
Local Buses
Hard Disk Drives
Networks
ISA
1 to 4 MBps
32-Bit VESA-VL
132 MBps
IDE
4 MBps
Ethernet
10 Mbps
EISA
33 MBps
PCI
132 MBps
SCSI
5 MBps
Token Ring
4 or 16 Mbps
MCA
32 MBps
TS:
Task Switched bit. CRO bit 3.
TSR: The Task State registers are the TSRs that are saved and restored using the SVTS and RSTC instructions, respectively.
TSS:
During task switching, the processor saves the current CPU state in the
Task State Segment table before starting a new task.
type:
Segment Type field. Gate or segment descriptor bits 11-8.
1m
U/S:
The UserlSupervisorattribute is used in conjunction with the write/read
attribute to implement protection atthe page level. When set (user), the
page. is accessible at all privilege levels. When clear (supervisor), the
page is accessible only when CPL :::; 2.
I!I
VS6:
Virtual8086
VESA: The Video Equipment Standards Association VL-bus is a straightforward expansion of the 486 host bus, meaning that it uses the 486 data,
address, and control signals directly. A few more lines are added to allow
bus mastering and other functions.
VGA:
Video Graphics Array is the most popular color graphics system for
IBM-compatible computers today.
virtual-SOS6 mode:
When the Virtual-8086 Mode flag is set in protected
mode, the microprocessor switches to virtual-8086 operation, handling
segment loads as the 8086 does.
virtual memory:
Virtual memory is similar to expanded memory in that it
temporarily borrows space from an external memory source, such as
hard disk, to simulate a large amount of memory. Up to 64 terabytes of
virtual memory can be addressed in 386- and 486-based systems.
VM:
The Virtual-8086 Mode flag.
volatile memory:
A memory in which the data content is lost when the power supply is disconnected.
Glossary
G-17
Glossary
VRAM: Video Random Access Memories have been used by designers of
high-resolution graphics and imaging systems to enhance system performance and display more colors at higher resolutions.
wait state: The number of clock cycles the CPU has to wait for other operations to complete before continuing with its operations.
way:
Way is used to define the organization of a cache. A cache with a way 1
and a way 2 is a 2-way cache.
WP1, WP2, WP3: The Write Protected access regions 1 through 3 bits, located in the Configuration Control register 1, define write protection and
cacheability for 3 regions of memory space. The starting address and
block size for each region is mapped in the Address Region registers 1
through 3.
WP:
Write Protect bit. CRO bit 16.
write-back: Write-back is an approach used to update the main memory.
The CPU writes data into the cache and sets a dirty bit indicating that a
word has been written into the cache but not into the main memory. The
cache data is written back into the main memory at a later time and the
dirty bit is cleared. Write-back accesses memory less than a writethrough cache, but its cache control logic is more complex.
write protected: Write protected is an attribute applied to segments to ensure that the requestor privilege level is sufficient to perform a write to
that segment.
write-through cache: Write-through is an approach to update the main
memory. The data is written to the main memory while it is is written to
cache, or immediately afterwards. The main memory always contains
valid data, and blocks in cache can be overwritten without data loss, and
the hardware implementation remains relatively simple.
ZF:
G-18
The Zero Flag is set if the operation result is zero. Otherwise it is cleared.
Index
3.3-V operation 1-19
3.3-V15-V operation 1-19
accumulator
initial value
2-3 to 2-4
additional-data-segment-selector registers
abort exceptions 2-45
absolute maximum ratings 5-4
ac characteristics. See timing
accessing
address space 2-9
application register set 2-10
configuration registers 2-9,2-26
coprocessor liD
Tl486SXL 4-4
Tl486SXLC 3-4
coprocessor liD ports 2-8
data/liD during SMI service routine 2-54
debug registers 2-31
directory-table entry 2-42
during protection 2-57
gate descriptors 2-59
global-descriptor-table register 2-19
liD address space 2-9
I/O privilege required 2-58
local-descriptor-table register 2-19
main memory 2-26
main memory overlapping SMM 2-28 A-5
memory address space 2-37
numeric coprocessor liD. See accessing coprocessor liD
page-table entry 2-42
privilege requirements 2-57
SMM
defined space 2-28
memory 2-28
memory space 2-54
stack-pointer register 2-11
task register 2-23
2-12
address
I/O space 2-9
memory space 2-37
offset mechanism 2-37
real mode memory 2-37
setting size 7-4
address bit-20 masking
TI486SXL 4-45
TI486SXLC 3-38
2-54
C-3
address bus description
TI486SXL 4-4
TI486SXLC 3-4
address spaces
coprocessor communication space 2-8
liD address space 2-8
memory address space 2-8, 2-37
physical memory space 2-8, 2-39
ranges 2-8, 2-26
address-region registers 2-30
initial value 2-3 to 2-4
addressing
data registers 2-11
index and pointer registers 2-11
main memory
at the same address as SMM code A-9
modes 2-38
modes (memory) 2-38
paging mechanism 2-40
pOinter and index registers 2-11
real mode 2-38
segment and selector 2-39
using nonpipelined bus cycles
Tl486SXL 4-23
Tl486SXLC 3-20
Index-1
Index
addressing (continued)
using pipelined bus cycles
Tl486SXL 4-27
Tl486SXLC 3-24
while in virtual 8086 mode 2-60
airflow measurement setup
for thermal characteristics 6-20
alignment-check enable 2-19
flag 2-15
altering SMM code limits
in system-management mode A-34
application register set 2-10
flag word 2-14
general-purpose registers 2-11
data 2-11
pointer and index registers 2-11
segment registers and selectors 2-12
instruction pointer 2-14
overview 2-10
pointer and index 2-11
segment registers 2-12
selector (segment) 2-12
auxiliary-carry flag 2-15
base register 2-11
base register
initial value 2-3 to 2-4
base-pointer register 2-11
initial value 2-3 to 2-4
based addressing modes 2-38
810S modifications 8-1
differences of TI486xLC/E and TI486SXUC 8-2
power-on and hard reset 8-3
protected-mode to real-mode switching 8-3
soft reset 8-4
turning on and off the internal cache 8-4
bit A20M masking C-3
bit definitions
configuration control registers 0 and 1 2-27
control register 0 (eRO) 2-19
debug registers DR6 and DR7 2-32
directory and page table 2-42
error codes 2-48
flag register 2-14
gate descriptors 2-23
page table and directory 2-42
segment descriptors 2-22
test registers
_ TR3 to TR5 2-36
TR6 and TR7 2-34
block diagra.m
TI486SXL 1-10
TI486SXLC 1-6
Index-2
block sizes
address-region registers
2-30
breakpoint address
setting 2-31
bus
address
Tl486SXL 4-4
Tl486SXLC 3-4
data
Tl486SXL 4-6
TI486SXLC 3-6
nonpipelined states
Tl486SXL 4-26
Tl486SXLC 3-23
operation
Tl486SXL 4-22
Tl486SXLC 3-19
pipelined states
TI486SXL 4-31
Tl486SXLC 3-28
state transitions
Tl486SXL 4-33
Tl486SXLC 3-30
states
Tl486SXL 4-23, 4-27
Tl486SXLC 3-20, 3-24
bus cycle
definition
Tl486SXL 4-16
Tl486SXLC 3-13
halt and shutdown
Tl486SXL 4-39
Tl486SXLC 3-33
initiating and maintaining nonpipelined
Tl486SXL 4-26
Tl486SXLC 3-23
initiating and maintaining pipelined
Tl486SXL 4-31
Tl486SXLC 3-28
interrupt acknowledge
Tl486SXL 4-37
Tl486SXLC 3-31
locked
Tl486SXL 4-37
Tl486SXLC 3-31
nonpipelined addressing
Tl486SXL 4-23
Tl486SXLC 3-20
pipelined addressing
Tl486SXL 4-27
Tl486SXLC 3-24
types
Tl486SXL 4-16, 4-22
Tl486SXLC 3-13,3-19
using bus-size input
Tl486SXL 4-34
Index
bus operation and functional timing
TI486SXL 4-22
TI486SXLC 3-19
byte enable outputs
description
Tl486SXL 4-5, 4-14
Tl486SXLC 3-5
generating A 1-AO
Tl486SXL 4-14
line definitions
TI486SXL 4-13
write duplication
Tl486SXL 4-14
clock-doubled mode 1-18
disabling 2-27
enabling 2-27
entering
Tl486SXL 4-17
Tl486SXLC 3-14
using software control
Tl486SXL 4-16
Tl486SXLC 3-13
code fetch
first after reset
Tl486SXL 4-21
Tl486SXLC 3-18
code-segment register 2-12
initial value 2-3 to 2-4
cache
example code
for turning off 8-5
for turning on 8-6
fills
Tl486SXL 4-42
TI486SXLC 3-36
flush enabling 2-27
flushing C-4
TI486SXL 4-44
Tl486SXLC 3-37
initialization 2-2
invalidation C-4
on chip 1-17
test registers 2-35
cacheability
disabling 2-28
enabling 2-28
calculation
effective address 2-37
offset address 2-37
protected-mode address 2-39
real-mode address 2-38
call gates
2-59
carry flag
2-15
clearing the VM bit
A-42
clock
scaling sequence
TI486SXL 4-17
Tl486SXLC 3-14
stopping the input
Tl486SXL 4-53
TI486SXLC 3-47
synchronization
Tl486SXL 4-20
Tl486SXLC 3-17
clock-count summary
abbreviations 7-13
assumptions 7-13
comparison
of SMM features
A-4
configuration registers 2-26
liD address
locations 2-9
space access 2-8
configuration-control registers 2-26
bit definitions 2-27 to 2-30
configuration-control registers
initial values 2-3 to 2-4
control registers 2-18
bit definitions 2-18
machine status word (MSW) 2-18
page-directory base register 2-18
page-fault linear address 2-18
coprocessor
busy
Tl486SXL 4-5
Tl486SXLC 3-5
communication space 2-8
error
Tl486SXL 4-6
TI486SXLC 3-6
liD access address lines
Tl486SXL 4-4
Tl486SXLC 3-4
interface
Tl486SXL 4-49
TI486SXLC 3-42
count register
2-11
count register
initial value
2-3 to 2-4
CPU states related to system-management
mode 2-55
cross reference
terminal assignments
to 486SX, DX, DX4 (168-pin PGA)
6-12
Index-3
Index
m
d field
for instructions 7-6
data bus
description
T1486SXL 4-6
T1486SXLC 3-6
data registers 2-11
initial values 2-3 to 2-4
data-segment register 2-12
initial value 2-3 to 2-4
dc electrical characteristics 5-7, 5-12
3.3-volt devices 5-9
T1486SXLC- V25 5-9
T1486SXL2- V50 5-11
T1486SXL -V40 5-10
3.3-voltl5-volt-tolerant devices 5-7
T1486SXL -G40 5-7
T1486SXL2-G50 5-8
5-volt devices
T1486SXL2-050 5-15
T1486SXL -040 5-14
T1486SXLC2-050 5-13
T1486SXLC-040 5-12
debug breakpoint conditions
setting 2-32
debug registers 2-31
initial value 2-3 to 2-4
debugging
SMI code using software A-36
testing SMM code A-35
decoupling 5-2
default
operand size
real versus protected modes 2-5
default segment override 7-4
defining
address region size
T1486SXL 2-30
T1486SXLC 2-29
nancacheable block size
T1486SXL 2-30
T1486SXLC 2-29
SMM memory region size
T1486SXL 2-30
T1486SXLC 2-29
definitions
bus cycle
T1486SXL 4-16
T1486SXLC 3-13
configuration-control register 0 bits 2-27
configuration-control register 1 bits 2-28
control register 0 bits 2-19
CRO-register bits 2-19
debug register DR6 and DR7 bits 2-32
Index-4
definitions (continued)
directory and page table register bits 2-42
error code bits 2-48
flags 2-15
gate-descriptor register bits 2-23
page table and directory register bits 2-42
segment-descriptor register bits 2-22
test register bits for TR3-TR5 2-36
test register bits for TR6 and TR7 2-34
description
address bus
T1486SXL 4-4
T1486SXLC 3-4
bus cycle
T1486SXL 4-22
T1486SXLC 3-19
byte enable outputs
T1486SXL 4-5, 4-14
T1486SXLC 3-5
data bus
T1486SXL 4-6
T1486SXLC 3-6
descriptor type
setting 2-22
descriptor-table registers and descriptors 2-19
global descriptor table register 2-20
global-descriptor table 2-40
interrupt description table register 2-20
local-descriptor table 2-40
design considerations C-2
destination-index register 2-11
initial value 2-3 to 2-4
detection
of a TI microprocessor A-26
of SMM capable version A-28
differences between
TI486SXL(C) family and TI486SLC/DLC
family 1-16
TI486SXLC series and TI486SXL series 1-15
direct addressing mode 2-38
direction flag 2-15
directory and page table entry
bit definitions 2-42
directory table 2-41
disabling
(ignore) A20M pin 2-27, C-3
(ignore) SMI input 2-28
(masking) alignment check 2-19
cache 2-19
cacheability 2-28
clock doubled 2-27, 8-2
using software
TI486SXL 4-16
TI486SXLC 3-13
FLUSH# pin 2-27
interrupts INTR 2-43
KEN# pin 2-27
Index
main memory access MMAC
A-9
disabling (continued)
maskable interrupts INTR 2-15
paging 2-2
protected mode (8086-class CPU)
SMM pins 2-28
suspend pins 2-27
write protection 2-28
displacement addressing modes
OX support
OX4 support
2-38
0-5
0-6
EAX register
value after self test
Tl486SXL 4-21
Tl486SXLC 3-18
eee field
for instructions
entering
clock-doubled mode
Tl486SXL 4-17
Tl486SXLC 3-14
float mode
Tl486SXL 4-55
Tl486SXLC 3-48
hold-acknowledge state
Tl486SXL 4-46
Tl486SXLC 3-39
virtual-8086 mode 2-61
error codes 2-48
bit definitions 2-48
format 2-48
effective address
calculation 2-37
setting length 2-22
EFLAGS register
A-11
error
coprocessor
Tl486SXL 4-6
Tl486SXLC 3-6
7-11
2-14, 2-15
electrical connections
decoupling 5-2
ground 5-2
NC designated terminals
power 5-2
pullup/pulldown resistors
unused inputs 5-3
2-19
enabling (continued)
SMM A-11
memory space 2-28
pins 2-28
suspend pins 2-27
system-management mode
write protection 2-28
5-3
5-2
enabling
A20M pin 2-27, C-3
alignment check 2-19
cache 2-19
cache flush 2-27
cacheability 2-28
clock doubled 2-27, 8-2
using software
TI486SXL 4-16
TI486SXLC 3-13
FLUSH# pin 2-27
interrupts INTR 2-43
KEN# pin 2-27
locked hardware signal 7-4
main memory access MMAC A-9
maskable interrupts 2-15
paging 2-19
protected mode 2-19
segment default override 7-4
SMI# pin
Tl486SXL 2-30
Tl486SXLC 2-29
example
altering SMM code limits A-34
clearing VM bit
after saving registers A-42
code
for turning cache off 8-5
for turning cache on 8-6
debugging SMI code A-36
detection
of a TI microprocessor A-26
of SMM capable version A-28
enabling SMM A-11
enabling/disabling clock doubling
Tl486SXL 4-16
Tl486SXLC 3-13
format of data used by SVOC/RSOC A-32
loading SMM memory with SMI interrupt
handler A-22
SMI handler A-17
exceptions 2-44
abort 2-45
fault 2-44
invalid opcode 2-7
priorities 2-47
processing 2-43
real mode 2-47
trap 2-44
exceptions and interrupts
exceptions in real mode
execution pipeline
2-43
2-47
1-17
Index-5
Index
exiting
clock-doubled mode
T1486SXL 4-17
T1486SXLC 3-14
float mode
T1486SXL 4-55
T1486SXLC 3-48
hold acknowledge state
T1486SXL 4-46
T1486SXLC 3-39
SMI handler A-9
virtual-8086 mode 2-61
extra-segment-selector register
2-12
extra-segment registers
initial values 2-3 to 2-4
fault exceptions
2-44
field
address displacement format
base 7-9
d 7-6
eee 7-11
flags 7-12
immediate data format 7-2
index 7-10
mod 7-9
mod rim 7-7
mod rim format 7-2
opcode 7-5
opcode format 7-2
prefix bytes 7-4
prefix format 7-2
reg 7-6
s-i-b format 7-2
sreg2 7-10
sreg3 7-11
ss 7-10
w 7-5
7-2
fills, cache
TI486SXL 4-42
TI486SXLC 3-36
first code fetch, after reset
TI486SXL 4-21
TI486SXLC 3-18
flags
abbreviations used in instruction set list 7-12
actions based on instruction 7-12
alignment check 2-15
auxiliary carry 2-15,7-12
carry 2-15, 7-12
definitions 2-15
direction 2-15,7-12
Index-6
flags (continued)
1/0 privilege level 2-15
interrupt enable 2-15, 7-12
nested task 2-15
overflow 2-15, 7-12
parity 2-15,7-12
resume 2-15
sign 2-15,7-12
trap enable 2-15, 7-12
virtual 8086 mode 2-15
zero 2-15,7-12
flag-word register 2-14
bit definitions 2-15
initial value 2-3 to 2-4
float
TI486SXL 4-55
TI486SXLC 3-48
float delay
TI486SXL 5-34
TI486SXLC 5-31
flow diagram
system management and suspend 2-56
system-management mode execution 2-51
FLUSH# pin
disabling 2-27
enabling 2-27
flushing
cache
T1486SXL 4-44
T1486SXLC 3-37
cache (internal) 2-27, C-4
instruction-decode queue 2-59
internal pipeline 2-2
translation look-aside buffer 2-42
format
error codes 2-48
for instructions 7-2
format of data used by SVDC/RSDC instructions, in
system-management mode A-32
functional block diagram
TI486SXL 1-1 0
TI486SXLC 1-6
functional timing
entering and exiting float
T1486SXL 4-55
T1486SXLC 3-48
fastest
nonpipelined read cycles
TI486SXL 4-23
TI486SXLC 3-20
pipelined read cycles
TI486SXL 4-28
TI486SXLC 3-25
fastest transition to pipelined address following
idle bus state
T1486SXL 4-31
T1486SXLC 3-28
Index
functional timing (continued)
HALT-initiated suspend mode
T14868XL 4-53
T14868XLC 3-46
liD trap
T1486SXL 4-51
T1486SXLC 3-44
interrupt-acknowledge cycles
T14868XL 4-38
T14868XLC 3-32
masking A20 using A20M during burst of bus
cycles
T14868XL 4-45
T14868XLC 3-38
nonpipeliined, cache fills using KEN#,
TI486SXLC 3-36
nonpipelined
bus cycles using 8816#
TI486SXL 4-35
cache fills using KEN#
TI486SXL 4-42
cache fills using KEN# and 8816#
TI486SXL 4-43
halt cycle
TI486SXL 4-40
TI486SXLC 3-34
read and write cycles
TI486SXL 4-24
TI486SXLC 3-21
wait states
TI486SXL 4-25
TI486SXLC 3-22
pipelined
cache fills using KEN#
TI486SXL 4-44
TI486SXLC 3-37
shutdown cycle
TI486SXL 4-41
TI486SXLC 3-35
wait states
TI486SXL 4-29
TI486SXLC 3-26
requesting hold
from active nonpipelined bus
TI486SXL 4-48
TI486SXLC 3-41
from active pipelined bus
TI486SXL 4-49
TI486SXLC 3-42
from bus-idle state
TI486SXL 4-47
TI486SXLC 3-40
SMI#pin
T14868XL 4-50
T14868XLC 3-43
functional timing (continued)
stopping CLK2 during suspend mode
T14868XL 4-54
T14868XLC 3-47
SUSP#-initiated suspend mode
T1486SXL 4-52
T1486SXLC 3-45
transitioning to pipelined address during burst of
bus cycles
T1486SXL 4-32
T1486SXLC 3-29
functional timing and bus operation
TI486SXL 4-22
TI486SXLC 3-19
m
gate descriptors 2-22
bit definitions 2-23
gates 2-59
call 2-59
interrupt 2-59
task 2-59
trap 2-59
general cache invalidation C-4
general-purpose registers 2-11
data 2-11
index and pointer 2-11
pointer and index 2-11
base pointer 2-11
destination index 2-11
source index 2-11
stack pointer 2-11
generating A1-AO
as a function of byte enables
T1486SXL 4-14
global-descriptor table 2-40
register 2-20
granularity
setting limit 2-22
ground electrical connections 5-2
m
halt bus cycles
TI486SXL 4-39
TI486SXLC 3-33
halt and shutdown 2-57
HALT-initiated suspend mode
TI486SXL 4-53
TI486SXLC 3-46
Index-7
Index
hardware considerations
address bit A20M C-3
address strobes A-5
cache invalidation C-4
chipset REAOY#, A-5
connecting terminals C-2
modifications for 168-pin CPGA 0-1
SMI# pin timing A-5
SMM pins A-5
header
SMM memory space 2-50
HLOA valid delay timing
TI486SXL 5-34
TI486SXLC 5-31
hold acknowledge signal states
TI486SXL 4-15
TI486SXLC 3-12
hold acknowledge state
entering
Tl486SXL 4-46
Tl486SXLC 3-39
exiting
Tl486SXL 4-46
Tl486SXLC 3-39
requesting from idle bus
Tl486SXL 4-46
Tl486SXLC 3-39
requesting from nonpipelined bus
Tl486SXL 4-46
Tl486SXLC 3-39
requesting from pipelined bus
Tl486SXL 4-46
Tl486SXLC 3-39
initial value
accumulator 2-3 to 2-4
address-region registers 2-3 to 2-4
base register 2-3 to 2-4
base-pointer register 2-3 to 2-4
code-segment register 2-3 to 2-4
configuration-control registers 2-3 to 2-4
count register 2-3 to 2-4
data register 2-3 to 2-4
data-segment register 2-3 to 2-4
debug register 2-3 to 2-4
destination-index register 2-3 to 2-4
extra-segment registers 2-3 to 2-4
flag-word register 2-3 to 2-4
instruction-pointer register 2-3 to 2-4
interrupt-descriptor-table register 2-3 to 2-4
machine-status-word register 2-3 to 2-4
source-index register 2-3 to 2-4
stack-pointer register 2-3 to 2-4
stack-segment register 2-3 to 2-4
D
initiating and maintaining pipelined bus cycles
TI486SXL 4-31
TI486SXLC 3-28
I/O
address space 2-8, 2-9
configuration register access 2-8
floating
Tl486SXL 4-55
Tl486SXLC 3-48
privilege level flag 2-15
privilege levels 2-58
trapping
Tl486SXL 4-51
Tl486SXLC 3-44
implementation
system-management mode A-5
index addressing modes 2-38
index field
for instructions 7-10
indirect addressing mode 2-38
Index-8
initialization 2-2
protected mode
2-59
initiating
protected mode 2-59
self test
TI486SXL 4-20
Tl486SXLC 3-17
suspend mode
Tl486SXL 4-52
Tl486SXLC 3-45
initiating and maintaining nonpipelined bus cycles
TI486SXL 4-26
TI486SXLC 3-23
initiating suspend mode
TI486SXL 4-53
TI486SXLC 3-46
input clock, stopping
TI486SXL 4-53
TI486SXLC 3-47
input/output signals
TI486SXL 4-2
TI486SXLC 3-2
instruction
locked hardware signal 7-4
override segment default 7-4
repeat following string 7-4
instruction decode queue
instruction format
7-2
2-59
Index
instruction set
clock counts 7-13
clock-count summary 7-13
encoding 7-13
flags 7-12
flags affected 7-13
instruction fields
d field 7-6
eee field 7-11
index field 7-10
mod and base fields 7-9
mod and rim field 7-7
opcode field 7-5
prefixes 7-4
reg field 7-6
sreg2 field 7-10
sreg3 field 7-11
ss field 7-10
w field 7-5
listing of all 7-14 to 7-33
lock prefix 2-7
names of instructions 7-13
overview 2-6
system-management mode 2-52, A-13
types of operations 2-6
instruction summary
system-management mode A-12
instruction types 2-7, 7-2
instruction-pointer register 2-14
initial value 2-3 to 2-4
internal clock synchronization
TI486SXL 4-20
TI486SXLC 3-17
interrupt acknowledge bus cycles
TI486SXL 4-37
TI486SXLC 3-31
interrupt gates 2-59
interrupt handling
virtual-8086 mode 2-60
interrupt vectors 2-45
assignments 2-46
interrupt-descriptor table 2-45
interrupt-enable flag 2-15
interrupt-descriptor-table register
initial value 2-3 to 2-4
interrupts
descriptor table register 2-20
gate descriptors 2-23
maskable 2-43
non maskable 2-43
system management
Tl486SXL 4-50
Tl486SXLC 3-43
interrupts and exceptions 2-43
priorities 2-46
intersegment transfers 2-59
invalid-opcode exception
invalidation
cache C-4
2-7
KEN# pin
disabling 2-27
enabling 2-27
I!I
leaving virtual-8086 mode 2-61
list, instruction set 7-14 to 7-33
loading SMM memory from main memory
system-management mode A-22
local-descriptor table 2-40
register 2-20
lock hardware signal
setting 7-4
lock prefix 2-7, 7-4
locked bus cycles
TI486SXL 4-37
TI486SXLC 3-31
logic symbol
TI486SXL 1-11 to 1-12
TI486SXLC 1-7
machine-status-word register
control register 0 2-18
initial value 2-3 to 2-4
maskable interrupts 2-43
enabling 2-15
masking
See also disabling
alignment check 2-19
bit A20M address C-3
interrupts INTR 2-43
measurement points for ac characteristics 5-16 to 5-19, 5-29 to 5-34
memory address space 2-8
offset mechanism 2-37
real-mode memory addressing 2-38
system-management mode 2-54
memory addressing 2-8, 2-37
during virtual-8086 mode 2-60
memory space header
SMM 2-50
system-management mode 2-52
mixed 3.3-V/5-Voperation 1-19
Index-9
Index
nonpipelined (continued)
bus states
Tl486SXL 4-23
Tl486SXLC 3-20
halt cycle
Tl486SXL 4-39
Tl486SXLC 3-33
read and write cycles
Tl486SXL 4-24
Tl486SXLC 3-21
wait states
Tl486SXL 4-25
Tl486SXLC 3-22
numeric coprocessor. See coprocessor
mixed systems
3-V systems 0-9
3-V15- V systems 0-10
using TI486SXL 0-9
mod and base fields
for instructions 7-9
mod and rim field
for instructions
7-7
mode
3.3-Voperation 1-19
clock doubled 1-18
entering clock doubled
Tl486SXL 4-17
Tl486SXLC 3-14
halt 2-57
I/O float
Tl486SXL 4-55
Tl486SXLC 3-48
memory addressing 2-38
mixed 3.3-V/5-V operation 1-19
power management 1-18
Tl486SXL 4-18
TI486SXLC 3-15
protected 2-12
protection 2-57
real 2-12
real versus protected 2-5
segment registers 2-12
shutdown 2-57
static operations 1-18
stopping the input clock
Tl486SXL 4-53
TI486SXLC 3-47
suspend 1-18
Tl486SXL 4-52, 4-53
See a/so suspend request
3-45, 3-46
See a/so suspend request
Tl486SXLC
system management 1-18, 2-49
Tl486SXL 4-50
TI486SXLC 3-43
virtual 8086 2-60
m
NC designated terminals
nested-task flag
5-3
2-15
non maskable interrupts 2-43
noncacheable boundaries, setting
nonpipelined
addressing bus cycles
Tl486SXL 4-23
Tl486SXLC 3-20
bus cycles using bus size input
Tl486SXL 4-34
Index-10
OEM modifications for 168-pin CPGA 0-1
chipset support 0-11
offset
address calculation 2-37
mechanism 2-37
on-chip cache 1-17
opcode field
for instructions 7-5
operands
default size
real versus protected modes 2-5
length and location 2-6
overview 2-6
setting length 2-22
setting size 7-4
types 2-6
operations
system-management mode 2-50
ordering information
part number components F-1
overflow flag 2-15
override
segment default 7-4
overview
system-management mode 1-18, A-2
TI486SXL series 1-9
TI486SXLC series 1-5
2-27
package dimensions
TI486SXL 132-pin PGA
TI486SXL 168-pin PGA
TI486SXL ceramic QFP
TI486SXL plastic QFP
TI486SXLC plastic QFP
page frame 2-41
page table 2-41
6-14
6-17
6-16
6-15
6-13
Index
page-directory base register
control register 3 2-1 8
page-fault linear address
control register 2 2-18
paging initialization
2-2
paging mechanism
directory table 2-41
page frame 2-41
page table 2-41
parameter definitions
for thermal characteristics
parity flag
6-20
2-15
part numbers offered
TI486DLC F-3
TI486SLC F-3
TI486SXL F-2
TI486SXLC F-2
physical memory space 2-8
real mode versus protected mode
2-5
pin assignments
TI486SXL
132-pin PGA 6-6
144-pin QFP 6-8
168-pin PGA 6-11
cross reference to 486SX, OX,OX4
TI486SXLC 6-3
pin functions
TI486SXL 4-4 to 4-11
TI486SXLC 3-4 to 3-11
pipeline
for execution 1-17
initialization 2-2
Ii]
pipelined
addressing bus cycles
Tl486SXL 4-27
Tl486SXLC 3-24
bus cycles using bus size input
Tl486SXL 4-35
bus states
Tl486SXL 4-27
Tl486SXLC 3-24
read and write cycles
Tl486SXL 4-28
Tl486SXLC 3-25
shutdown
Tl486SXL 4-41
Tl486SXLC 3-35
wait states
Tl486SXL 4-29
Tl486SXLC 3-26
pointer and index registers
power electrical connections
6-12
power management 1-18
features
system-management mode A-3
TI486SXL 4-18, 4-52
TI486SXLC 3-15, 3-45
power-on and hard reset
810S modifications 8-3
prefix lock 2-7
prefixes
for instruction set 7-4
priorities
interrupts and exceptions 2-46
privilege levels 2-57
1/0 2-58
real versus protected mode 2-5
transfer 2-58
intersegment 2-59
task switches 2-59
privilege-level flag 2-14
1/0 2-15
processor initialization 2-2
protected mode 2-57
address calculation 2-39
initialization and transition 2-59
to real-mode switching
810S modifications 8-3
protected mode versus real mode 2-5
protection
during virtual-8086 mode 2-60
gates 2-59
initialization 2-59
pullup/pulldown resistors 5-2
2-11
5-2
ranges
address space 2-8
read and write cycles
nonpipelined
Tl486SXL 4-24
Tl486SXLC 3-21
pipelined
Tl486SXL 4-28
Tl486SXLC 3-25
real mode
address calculation 2-38
exceptions 2-47
memory addressing 2-38
real mode versus protected mode 2-5
recommended operating conditions 5-5
3.3-volt devices 5-6
3.3-voltl5-volt-tolerant TI486SXL-G devices
5-volt devices 5-6
reducing the clock frequency
system-management mode A-3
5-5
Index-11
Index
reg field
for instructions
7-6
registers
accumulator 2-11
initial value 2-3 to 2-4
additional data segment 2-12
address region 2-29 to 2-30
initial value 2-3 to 2-4
base 2-11
initial value 2-3 to 2-4
base pointer 2-11
initial value 2-3 to 2-4
code segment 2-12
initial value 2-3 to 2-4
configuration control 2-26
initial value 2-3 to 2-4
count 2-11
initial value 2-3 to 2-4
data 2-11
initial value 2-3 to 2-4
data segment 2-12
initial value 2-3 to 2-4
debug 2-31
initial value 2-3 to 2-4
destination index 2-11
initial value 2-3 to 2-4
EFLAGS 2-14
extra segment 2-12
initial value 2-3 to 2-4
flag word 2-14
initial value 2-3 to 2-4
general purpose 2-11
data registers 2-11
pointer and index 2-11
instruction pointer 2-14
initial value 2-3 to 2-4
interrupt-descriptor table 2-20
initial value 2-3 to 2-4
machine-status word 2-14
initial value 2-3 to 2-4
segment selector 2-13
additional data 2-12
code 2-12
data 2-12
extra segment 2-12
selection rules 2-13
stack 2-12
source index 2-11
initial value 2-3 to 2-4
stack pointer 2-11
initial value 2-3 to 2-4
stack segment 2-12
initial value 2-3 to 2-4
Index-12
register sets
application registers 2-7
overview 2-7
system registers 2-16
repeat string instruction 7-4
reset
processor initialization 2-2
signal states
TI486SXL 4-15
TI486SXLC 3-12
soft 8-4
timing
T1486SXL 4-20
T1486SXLC 3-17
RESET setup and hold timing 5-29
restore
LDTR and descriptor
system-management mode A-13
register and descriptor
system-management mode A-13
TSR and descriptor
system-management mode A-13
resume
flag 2-15
from suspend
T1486SXL 4-18
T1486SXLC 3-15
normal mode
from system-management mode A-13
revision ID 2-3 to 2-4
save
LDTR and descriptor
system-management mode A-13
register and descriptor
system-management mode A-13
TSR and descriptor
system-management mode A-13
scaled addressing modes 2-38
scaling clock 3-14, 4-17
segment
descriptor register
bit definitions 2-22
descriptors
system and application 2-21
register selection rules 2-13
setting limit 2-22
size 2-5
segment default, override 7-4
segment registers, types 2-12
selector mechanism 2-39
Index
self test
clock-cycle count 2-2
EAX register after completion
Tl486SXL 4-21
Tl486SXLC 3-18
initiating
Tl486SXL 4-20
Tl486SXLC 3-17
sequence, clock scaling
TI486SXL 4-17
TI486SXLC 3-14
setting
address region size
Tl486SXL 2-30
Tl486SXLC 2-29
address size 7-4
breakpoint address 2-31
debug breakpoint conditions 2-32
descriptor type 2-22
granularity 2-22
length of effective addresses 2-22
setting (continued)
length of operands 2-22
lock hardware signal 7-4
noncacheable boundaries 2-27
operand size 7-4
segment limit 2-22
setup and hold timing
TI486SXL 5-32
TI486SXLC 5-29
shutdown and halt
soft reset
810S modifications
A-4
8-4
software
debugging 8MI code A-36
software considerations
addressing SMM code A-9
exiting the 8MI handler A-9
memory space header (SMM)
2-57
2-15
sreg2 field
for instructions
sreg3 field
for instructions
ss field
for instructions
7-10
7-11
7-10
stack-pointer register 2-11
initial value 2-3 to 2-4
static operation
stopping the input clock
TI486SXL 4-53
TI486SXLC 3-47
size
operanq default
real versus protected modes 2-5
segment 2-5
setting address 7-4
setting operand 7-4
SUSP-initiated suspend mode
TI486SXL 4-52
TI486SXLC 3-45
2-54
2-12
states
bus
Tl486SXL 4-23, 4-27
Tl486SXLC 3-20, 3-24
bus transitions
Tl486SXL 4-33
Tl486SXLC 3-30
hold acknowledge
Tl486SXL 4-46
Tl486SXLC 3-39
signal summary
TI486SXL 4-3
TI486SXLC 3-3
SMI handler
example
system-management mode A-17
exiting A-9
A-35
source-index register 2-11
initial value 2-3 to 2-4
signal states
during reset and hold acknowledge
TI486SXL 4-15
Tl486SXLC 3-12
during suspend mode
Tl486SXL 4-19
Tl486SXLC 3-16
SMI service routine execution
A-7
software control for clock doubling
TI486SXL 4-16
TI486SXLC 3-13
software only debugging of SMM code
stack-segment-selector register
stack-segment register
initial value 2-3 to 2-4
shutdown, bus cycles
TI486SXL 4-39
TI486SXLC 3-33
sign flag
SMM
feature comparison
pins
disabling 2-28
enabling 2-28
1-18
suspend acknowledge
TI486SXL 4-18
TI4868XLC 3-15
suspend mode 1-18
during system-management mode
HALT initiated
Tl486SXL 4-53
Tl486SXLC 3-46
2-55
Index-13
Index
suspend mode (continued)
initiating
TJ486SXL 4-52, 4-53
TJ486SXLC 3-45, 3-46
signal states during
TJ486SXL 4-19
TJ486SXLC 3-16
stopping the input clock
TJ486SXL 4-53
TJ486SXLC 3-47
SUSP initiated
TJ486SXL 4-52
TJ486SXLC 3-45
system-management mode
TJ486SXL
system-management mode (continued)
feature comparison A-4
flow diagram 2-51
format of data used by SVOC/RSOC instructions A-32
implementation A-5
software considerations. See
instructions 2-52
instruction summary A-12
restore
LDTR and descriptor A-13
register and descriptor A-13
TSR and descriptor A-13
A-3
resume normal mode A-13
save
See suspend request
LDTR and descriptor A-13
register and descriptor A-13
TSR and descriptor A-13
TJ486SXLC
See suspend request
suspend pins
disabling 2-27
enabling 2-27
introduction 2-49
loading SMM memory from main memory
memory space 2-54
memory space header 2-51 , A-8
operations 2-50
overview 1-18, A-2
power management features A-3
reducing the clock frequency A-3
suspend mode A-3
programming guide
altering SMM code limits A-34
clearing the VM bit A-42
detection
suspend request
TI486SXL 4-18
TI486SXLC 3-15
SX support
0-2
symbol
TI486SXL 1-11 to 1-12
TI486SXLC 1-7
system management interrupt
TI486SXL 4-50
TI486SXLC 3-43
of SMM capable version A-28
of TI microprocessor A-26
system register set 2-16
address-region registers 2-30
block sizes 2-30
cache-test registers 2-35
configuration registers 2-26
configuration-control register a
bit definitions
enabling SMM A-11
format of data used by SVDC/RSDC instructions A-32
hardware considerations A-5
address strobes A-5
chipset READY#, A-6
SMI# pin timing A-5
SMM pins A-5
2-27
configuration-control register 1
bit definitions
2-28
control registers
bit definitions 2-19
CRO, CR2, CR3 2-18
debug registers (OR7-0) 2-31
descriptor-table registers, descriptors
overview 2-16
system-address registers 2-19
task register 2-23
test registers 2-33
system-address registers
2-19
system-management mode
altering SMM code limits A-34
CPU states 2-55
detection
of a TI microprocessor A-26
of SMM capable version A-28
enabling A-11
Index-14
A-22
2-19
implementation A-2
instruction summary A-12
introduction A-2
loading SMM memory from main
memory A-22
overview A-2
reducing the clock frequency A-3
SMI handler example A-17
software considerations
addressing SMM code A-9
execution details A-9
exiting the SMI handler A-9
memory space header A-7 to A-8
suspend mode A-3
testing/debugging SMM code A-35
SMI handler example A-17
SMI service routing execution 2-54
Index
system-management mode (continued)
suspend mode 2-55
suspended-mode flow diagram 2-56
testing/debugging SMM code A-35
TI486SXL 4-50
TI486SXLC 3-43
timing (continued)
ac characteristics (continued)
3.3-volt devices 5-22
T1486SXL2-V50 5-24
T1486SXL-V40 5-23
TI486SXLC-V25 5-22
5-volt devices
5-25
T1486SXL2-050 5-28
T1486SXL-040 5-27
T1486SXLC2-050 5-26
T1486SXLC-040 5-25
D
task gates 2-59
descriptors 2-22
task register
task switches
2-23
2-59
terminal assignments
TI486SXL
132-pin PGA 6-6
144-pin QFP 6-8
168-pin PGA 6-11
168-pin cross reference to 486SX, OX,
OX4 6-12
TI486SXLC 6-3
terminal functions
TI486SXL 4-4 to 4-11
TI486SXLC 3-4 to 3-11
test registers
2-33
testing/debugging SMM code
system-management mode
A-35
thermal characteristics 6-18
parameter definitions 6-20
thermal management
conclusions E-15
airflow measurement setup 6-20
current trends and theory of correction E-14
guidelines E-14
introduction
junction temperature E-3
power E-3
thermal impedance E-3
methodology for TI specifications E-11
modes of heat transfer E-4
airflow E-8
integrated circuit thermal resistance E-5
proximity of integrated circuit on board E-8
PWB conductivity E-7
thermal specifications of integrated circuit E-9
definition of Q E-10
measurement of ambient temperature E-10
system dependence of junction-to and case-to
ambient temperature E-9
timing
See also functional timing
ac characteristics 5-19
3.3-voltl5-volt-tolerant devices
TI486SXL -G40 5-20
T1486SXL2-G50 5-21
CLK2 measurement points 5-19
clock synchronization
Tl486SXL 4-20
Tl486SXLC 3-17
float delay
Tl486SXL 5-34
Tl486SXLC 5-31
functional
Tl486SXL 4-22
Tl486SXLC 3-19
HLDA valid delay timing
Tl486SXL 5-34
Tl486SXLC 5-31
input signal setup and hold
Tl486SXL 5-32
Tl486SXLC 5-29
measurement points 5-16 to 5-19, 5-29 to 5-34
Tl486SXL 5-18
Tl486SXLC 5-17
output signal valid delay
Tl486SXL 5-33
Tl486SXLC 5-30
reset
Tl486SXL 4-20
Tl486SXLC 3-17
RESET setup and hold timing 5-29
write cycle hold timing
Tl486SXL 5-34
Tl486SXLC 5-31
write cycle valid delay timing
Tl486SXL 5-33
Tl486SXLC 5-30
TLB-test registers
transfer privilege levels
2-58
transitions, bus states
TI486SXL 4-33
TI486SXLC 3-30
translation look-aside buffer 2-42
trap exceptions
2-44
trap gates 2-59
trap-enable flag
5-20
2-33
2-15
trapping I/O
TI486SXL 4-51
TI486SXLC 3-44
turning the internal cache on and off
B-4
Index-15
Index
type of bus cycle
TI486SXL 4-16, 4-22
TI486SXLC 3-13, 3-19
m
unused inputs
5-3
valid delay timing
TI486SXL 5-33
TI486SXLC 5-30
vector assignments for interrupts
vectors
interrupt-descriptor table
interrupts 2-45
2-45
virtual-8086 mode 2-60
entering and leaving 2-61
flag 2-15
interrupt handling 2-60
memory addressing 2-60
protection 2-60
VL bus
cache snooping 0-7
clock and clock skew 0-7
10 settings 0-8
support 0-7
Index-16
2-46
wfield
for instructions 7-5
wait states
nonpipelined
Tl486SXL 4-25
Tl486SXLC 3-22
pipelined
Tl486SXL 4-29
Tl486SXLC 3-26
write and read cycles
nonpipelined
Tl486SXL 4-24
Tl486SXLC 3-21
pipelined
Tl486SXL 4-28
Tl486SXLC 3-25
write cycle
hold timing
Tl486SXL 5-34
Tl486SXLC 5-31
valid delay timing
TI486SXL 5-33
Tl486SXLC 5-30
write duplication
as a function of byte enables
write protection
disabling 2-28
enabling 2-28
zero flag
2-15
TI486SXL 4-14
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~TEXAS
INSTRUMENTS
A0294
©1994 Texas Instruments Incorporated
Printed in U.S.A.
TI486SXLC and TI486SXL
Microprocessors Reference Guide
•
TEXAS
INSTRUMENTS
lUlU l
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IT'
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Addendum
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This addendum to the TI486SXLC and TI486SXL Microprocessors Reference
Guide (SRZU006D) provides updated information for the electrical, mechanical, and thermal specifications and ordering information of subject microprocessors. Power supply requirements of the 486-compatible microprocessors
offered are shown in Table A-1.
Table A-1. Application Classifications
Family
Dash
Number
Supply Voltages
TI486SXL(C)2
-oxxt
Vee
TI486SXL( C)2
-GXX
Vee = 3.3,
VeC(5) = 3.3 V to 5 V
5-volt-tolerant inputs for
mixed 3-V/5-V systems
TI486SXL(C)2
-VXX
Vce= 3.3 V
3-V systems
Note:
=5 V
Application
5-V systems
2 indicates clock-doubled versions. Single-clock versions are also offered (Le., SXL-040).
XX = Frequency of operation (25, 40, or 50 MHz)
A complete listing of the microprocessors offered is shown in Table F-1 on addendum page 24.
A chapter-by-chapter synopsis of the changes follows.
Chapter 5 Electrical Specifications
Locations of the updated data in Chapter 5 are referenced by paragraph number and subject.
5.3
Recommended Operating Conditions
The TI486SXL( C) 5-V microprocessors are intended for use in environments
where the maximum case temperature is below 100°C for the 100-pin and
144-pin quad flat packages (QFPs), 85°C for the 132-pin and 168-pin ceramic
pin grid arrays (CPGAs), and 75°C for the 144-and 168-pin TI486SXL2-G66.
Achieving this case temperature may require a heat sink fin and/or appropriate
airflow. For updated data see Section 6.3, Thermal Characteristics, starting on
page 20 of this addendum.
Tables 5-4 through 5-6, showing the recommended operating conditions,
supersede the corresponding tables in the TI486SXLC and Tl486SXL Microprocessors Reference Guide. Changes are indicated by revision bars on the
left.
SRZU017 (For use with SRZU006D)
Addendum-1
Addendum
:: :=. ,c.• ;:m,mu
5.4.1
I.... ;::
::.:.:::U.a.:.•... unm, . . :... 5.. Q U .::.:.::m'-'=.~:Q!:.:.:::: ... :
UU·:.:.:RR.~:.
3.3-Volt Microprocessors With S-Volt-Tolerant Inputs
DC electrical characteristics for three new 5-V-tolerant input, 3.3-V micropro:Cessors, the TI496SXL2-G66, .TI486SXLC-G40, and TI486SXLC2-G50,
have been added with new Tables 5-8A, 5-88, and 5-8C. Revision bars are
omitted as all the material is new.
5.5
AC Characteristics
The TI486SXL(C) ac specifications have been updated and are included in
Tables 5-17 through 5-25. These tables supersede the corresponding tables
in the TI486SXLC and TI486SXL Microprocessor Reference Guide. Revision
bars are omitted as most of the setup, hold, and delay times have changed.
AC specifications for the added 5-V-tolerant input, 3.3-V devices,
TI496SXL2-G66, TI486SXLC-G40, and TI486SXLC2-G50, have been added with new Tables 5-18A, 5-188, and 5-18C.
Chapter 6 Mechanical Specifications
Locations of the updated data in Chapter 6 are referenced by paragraph number and subject.
6.3
Thermal Characteristics
The TI486SXL(C) family thermal characteristics are included in Tables 6-10
through 6-14. These tables contain the same data as the corresponding
tables in the TI486SXLC and Tl486SXL Microprocessors Reference Guide.
They are presented here for your convenience.
A new Table 6-10A has been a~ded to provide thermal data for the 100-pin
ceramic quad flat package (CQFP). Revision bars are omitted as all the material is new.
Appendix F Ordering Information
Locations of the updated data in Appendix Fare refe'renced by paragraph
number and subject.
F.2
Part Numbers for Microprocessors Offered
Table F-1 has been updated to show the availability of the TI486SXLC in the
small-form-factor, 100-pin CQFP. The new offering includes a 40-MHz or
40/20-MHz version and a 50-MHz clock-doubled version. Also added is the
availability of the TI486SXL2-G66. A complete listing of the microprocessors
offered is shown in Table F-1 on addendum page 24. The added microprocessors are indicated by a revision bar· on the left side of the table.
Addendum-2
_ _ _ _ _ _ _........_
........._ _........_ _ _ _ _
:::::~_::::_::::
___
:~:
Recommended Operating........:Conditions
..
W ...,.;.:.»»»"H.....:..N»"......H ...hW,.;.Y...hY......
""::::_::':_:.'_:~
...:«««-»»~:-:«««*'
h»»~h:*»»:O;'»»
5.3 Recommended Operating Conditions
Recommended operating conditions provide specific values for power supply
and input voltages, required input threshold ranges, output drive currents
available for system interfacing, and operating levels for clamp currents and
case temperature.
5.3.1
3.3-Volt Microprocessors With 5-Volt-Tolerant Inputs
Table 5-4 presents the recommended ope'rating conditions for the
TI486SXL-G 3.3-V microprocessors with 5-V-tolerant inputs.
I
During power up and power down conditions, the 3.3-V Vee terminals and the
5-V VeC(5) terminal should be ramped simultaneously because the 3.3-V Vee
voltage should not exceed the 5-V VeC(5) voltage by more than 1 V or the device may not initialize correctly. Conversely, the 5-V VCe(5) can exceed the
3.3-V Vce by up to 2.25 V.
Table 5-4. TI486SXL-G Recommended Operating Conditions
Min
Max
Unit
With respect to VSS
See Note 1
3
3.6
V
With respect to VSS,
See Note 1
3.2
3.6
V
With respect to V SS,
See Note 2
3
5.25
V
2
VCC(5)+0.3
V
-0.3
0.6
V
-0.3
0.5
V
VCC-0.3
VCC(5)+0.3
VCC
Supply voltage
VCC
Supply voltage
TI486SXL2-G66 (only)
VCC(5)
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VIL(C)
CLK2low-level input voltage
VIH(C)
CLK2 high-level input voltage
IOH
High -level output current
VOH = VOHmin
IOL
Low-level output current
VOL=VOLmax
flock
Phase -locked loop frequency
lock range
With respect to CLK2 frequency
mA
5
mA
32
50
MHz
85
TI486SXL in 144-pin QFP
a
a
a
TI486SXL2-G66 in 144-pin
QFP or 168-pin PGA
a
75
TI486SXLC in 1OO-pin QFP
(T1486SXL in 168-pin PGA
TC
Notes:
Case temperature
Power
applied,
V
-2
85
85
°C
1) VCC should be no more than 1 V greater than VCC(5) during power up or the device may not initialize correctly.
2) VCC(5) should be connected to the3.3-V supply in a3.3-V-only system. In mixed systems (3.3/5 V) VCC(5) should
be connected to the 5-V supply.
Replaces original page
5-5
Addendum-3
Recommended Operating Conditions
QC
5.3.2
:
3.3-Volt Microprocessors
Table 5-5 presents the recommended operating conditions for the
TI486SXLC-V and TI486SXL-V 3.3-V microprocessors.
Table 5-5. TI486SXLC-Vand TI486SXL-V Recommended Operating Conditions
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VIL(C)
CLK2 low-level input voltage
VIH_(C)
CLK2 high -level input voltage
IOH
High-level output current
VOH= VOHmin
IOL
Low-level output current
VOL=VOLmax
flock
Phase -locked loop frequency
lock range
With respect to CLK 2 frequency
TC
5.3.3
With respect to VSS
Case temperature
Power
applied
Min
Max
Unit
3
3.6
V
2
VCC+0.3
V
-0.3
0.6
V
-0.3
0.5
V
VCC-0.3
VCC+0.3
V
-2
rnA
5
rnA
32
50
MHz
0
85
1T1486SXL in 168-pin PGA
0
85
TI486SXL in 144-pin QFP
0
85
TI486SXLC in 100-pin
QFP
°c
5-Volt Microprocessors
Table 5-6 presents the recommended operating conditions for the
TI486SXLC and TI486SXL 5-V microprocessors.
Table 5-6. TI486SXLC and TI486SXL Recommended Operating Conditions
Min
Max
Unit
4.75
5.25
V
VCC
Supply voltage
VIH
High-level input voltage
2
VCC+0.3
V
VIL
Low-level input voltage
-0.3
0.8
V
VIL(C)
CLK2 low-level input voltage
-0.3
0.8
V
VIH_(C)
CLK2 high -level input voltage
3.7
VCC+0.3
V
IOH
High-level output current
VOH=VOHmin
-1
rnA
IOL
Low-level output current
VOL= VOLmax
5
rnA
flock
Phase -locked loop frequency
lock range
With respect to CLK2 frequency
32
50
MHz
TI486SXLC in 100-pin
QFP
0
100
TI486SXL in 132- and
168-pin PGA
0
85
TI486SXL in 144-pin
QFP
a
100
TC
Case temperature
Replaces original page 5-6
Addendum-4
With respect to VSS
Power
applied
°C
__
5.4.1
DC Electrical Specifications
:..,.'..,.
. . a_a
.
.."..,..."..,................................._ _"""""'_::_'_ _- '_ _ _
""::;:-:-»»'''''~.:.::;_H_~:;
...
t_~:»Wh»»'~'««
.••.
.::,'
420
'.'
Cc
Notes:
See Note 4
o MHz, Suspended/CLK2 stopped,
23
0.1
mA
1
mA
See Note 5
10
pF
fc = 1 MHz,
See Note 5
12
pF
fc = 1 MHz,
See Note 5
20
pF
See Note 4
1) Applicable for all input terminals except those with an internal pullup resistor. See Table 5-1.
2) PEREQ has an internal pulldown resistor.
3) Applicable for all inputs that have an internal pullup resistor. See Table 5-1.
4) All inputs at 0 or VCC. All inputs held static (except CLK2 as indicated). All outputs unloaded (static lOUT = 0 mA).
5) Not 100% tested
New page 5-8A
ADVANCE INFORMATION concerns new products In the sampling or
preproduction phase of development Characteristic data and other
specHlcetions are subject to change without notice.
Addendum-5
DC Electrical Specifications
_ _.:_.
:._a::VAf"'~h»:-»»»'»:_.::.:.:_.:':.::_.'
__
: :....
:,
.W'~:--~«
_ _ _ _'_.na_naWh.»!
: ... :.:.m
Table 5-88. TI486SXLC-G40 Electrical Characteristics at Recommended Operating
Conditions (Typical Values are at Vee = 3.3 \I, and 1A = 25°C)
TI486SXLC-G40
Parameter
VOL
Test Conditions
Low-level output voltage
Min
IOL= 3 mA
Max
Unit
0.4
V
2.4
IOH=-1 mA
VOH
High-level output voltage
II
Input current (leakage)
VIN = 0, VIN ~ VCC,
See Note 1
IIH
High-level input current at
PEREQ
VIN = 2.4,
See Note 2
IlL
Low-level input current
VIL = 0.45 V,
See Note 3
IOH =-0.2 rnA
V
VCC-O.4
ICC
Supply current (Active mode)
20 MHz (CLK2 = 40 MHz)
ICC(SM)
Supply current
(Suspend mode)
20 MHz
(CLK2 = 40 MHz),
ICC(SS)
Standby supply current
Ci
Input capacitance
Co
Cc
Notes:
Typ
See Note 4
o MHz, Suspended/CLK2 stopped,
See Note 4
N-
~';;~~~:~;7:jfY
<::;lt~!~ ::",' 300
±15
J.IA
200
J.IA
-400
J.IA
400
rnA
15
0.1
rnA
1
rnA
10
pF
fc = 1 MHz,
See Note 5
Output or 1/0 capacitance
fc = 1 MHz,
See Note 5
12
pF
Input capacitance on CLK2
fc = 1 MHz,
See Note 5
20
pF
1) Applicable for all input terminals except those with an internal pull up resistor. See Table 5-1 .
2) PEREQ has an internal pulldown resistor.
3) Applicable for all inputs that have an internal pullup resistor. See Table 5-1.
4) All inputs at 0 orVCC. All inputs held static (except CLK2 as indicated). All outputs unloaded (static lOUT = 0 rnA).
5) Not 100% tested
ADVANCE INFORMATION concerns new products In 1I1e sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Addendum-6
New page 5-88
.......____. . . . . . . . __. . . . __. . . . . . . . ___. . . . . . . . ___...............
..
DC Electrical Specifications
.....
, ........
, .....
_=a_~~ m:""':_;m_~:_u""'
VAV~
::
:~
:C:ClQ:VU.....-»»w.(o'.w.-w,.
Table 5-8C.
T14868XLC2-G50 Electrical Characteristics at Recommended Operating
Conditions (Typical Values are at Vee = 3.3 V, and 1A = 25°C)
T1486SXLC2-G50
VOL
Low-level output voltage
VOH
High-level output voltage
II
Input current (leakage)
IIH
High-level input current at
PEREQ
VIN = 2.4,
Low-level input current
VIL = 0.45 V,
IlL
Min
Test Conditions
Parameter
IOL=3mA
IOH =-0.2 rnA
VIN = 0, VIN ~ VCC,
Max
Unit
0.4
V
2.4
IOH =-1 rnA
V
VCC-O.4
See Note 1
'., .""t~:::" 17
~::::it" 20
I':' .5
ns
ns
14.5
17
ns
4
3
ns
5-11
5-11
8
5
ns
REAOY# setup time
REAOY# hold time
5-11
5-11
7
3
ns
t21
t22
031-00 read data setup time
031 - 00 read data hold time
5-11
5-11
5
3
ns
t23
t24
HOLO setup time
HOLO hold time
5-11
5-11
7
2
ns
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
5
2
ns
t27
t27a
t28
t28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-11
5-11
5-11
5-11
5
5
5
5
ns
t29
t30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
Note 4
Note 4
5-11
5-11
5
3
ns
t31
Clock-doubled PLL lock time
Note 6
t32
t33
MEMW# setup time
MEMW# hold time
Notes:
Notes 5, 7
20
5-11
5
5
Ils
ns
1)
2)
3)
4)
Input clock can be stopped; therefore, minimum CLK2 frequency is 0 MHz.
These parameters are not tested. Theyare determined by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) Oelay time from setting CKO in CCRO to entering clock-doubled mode
7) MEMW# is available on the 144-pin QFP and i68-pin PGA only.
Replaces original page 5-20
Addendum-8
ADVANCE INFORMATION concerns new products In the sampling or
preproduction phase of development Characteristic data and other
specifications are subject to change without notice.
::_,_ _ _ _,.....Q:.....
m.:....:......
: :........"'"""
..
"..m,..,m:,..,~w,..,m:_a!:_.
_ _ _ _ _ _....._.L_!.l....
:.:.:.:."":
... _:
......,.....
" l"", _ _
_:~~_:H~:
AC Characteristics
"""""; ::_.:::_.:C:.:"".
;.::"""':,:.::_:.::_:::.:....
w:~"
...
;: _ _ _"""
aa_.m=_u.=u~_.:m_:m
=w.<:
Table 5-18 covers the 3.3-V, 50-MHz TI486SXL2-G50.
Table 5-18.
AC Characteristics for TI486SXL2-G50, Vee = 3 V to 3.6 \I,
Vee(5) = 4.75 V to 5.25 V or 3 V to 3.6 \I, Tc = 0 to 85°C
Test
Conditions
T1486SXL2·G50
Symbol
Parameter
t1
t2a
t2b
t3a
t3b
t4
t5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
5-4
5-4
5-4
5-4
5-4
5-4
5-4
20
7
4
7
5
t6
t6a
t7
A31 - A2 valid delay
SMI# valid delay
A31 - A2 float delay
CL=50pF
CL = 50 pF
Note 3
5-12,5-15
5-12,5-15
5-15
1
1.5
3
17
30
30
ns
t8
t9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
CL = 50 pF
Note 3
5-12,5-15
5-15
1
3
17
30
ns
t10
t10a
AOS#, O/C#, MIIO#, W/R# valid delay
SMAOS# valid delay
CL = 50 pF
CL= 50 pF
5-12,5-15
5-12,5-15
1.5
1.5
17
17
ns
t11
t11a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
Note 3
Note 3
5-15
5-15
t12
t12a
t13
031-00 write data, SUSPA# valid delay
031 - 00 write data hold time
031-00 write data, SUSPA# float delay
CL=50pF
Note 5
Note 3
5-12,5-13
5-14
5-15
.~;~
3
1.5 ..,.,
,¥§
1."
,.
3 .:............
':';' " 22
..
t14
HLOA valid delay
CL=50pF
5-15
1.5
t15
t16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
5-11
5-11
5
3
ns
t17
t18
BS 16 setup time
BS16 hold time
5-11
5-11
8
5
ns
t19
t20
REAOY# setup time
REAOY# hold time
5-11
5-11
9
4
ns
t21
t22
031 - 00 read data setup time
031 - 00 read data hold time
5-11
5-11
7
5
ns
t23
t24
HaLO setup time
HaLO hold time
5-11
5-11
9
3.5
ns
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
8
3
ns
t27
t27a
t28
t28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-11
5-11
5-11
5-11
6
6
6
6
ns
t29
t30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
Note 4
Note 4
5-11
5-11
6
5
ns
t31
Clock-doubled PLL lock time
Note 6
t32
t33
MEMW# setup time
MEMW# hold time
Notes 5, 7
Figures
CLK2 clock-doubled frequency range
Min
Max
Unit
32
50
MHz
ns
7
7
3~
ns
ns
~:
..•.
Notes:
22
20
5-11
5
5
ns
,""S
ns
1)
2)
3)
4)
Input clock can be stopped; therefore, minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are determined by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) Oelay time from setting CKO in CCRO to entering clock-doubled mode
7) MEMW# is available on the 144-pin QFP and 168-pin PGA only.
ADVANCE INFORMATION concems new products In the sampling or
preproduction phase of development Characteristic data and other
speclnCltlons er. subject to change without notice.
Replaces original page 5-21
Addendum-9
AC Characteristics
Table 5-18A covers the 3.3-V, 66-MHz TI486SXL2C-G66.
Table 5-18A. AC Characteristics for TI486SXL2-G66, Vec = 3.2 V to 3.6 \I,
VCC(5) = 4.75 V to 5.25 V or 3.2 V to 3.6 \I, TC = 0 to 75°C
Parameter
Symbol
T1486SXL2·G66
Test
Conditions
Figures
CLK2 clock-doubled frequency range
Min
Max
Unit
32
66
MHz
t1
t2a
t2b
t3a
t3b
t4
t5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
5-4
5-4
5-4
5-4
5-4
5-4
5-4
15
7
4
7
5
t6
t6a
t7
A31 - A2 valid delay
SMI# valid delay
A31-A2 float delay
CL=50pF
CL=50pF
Note 3
5-12,5-15
5-12,5-15
5-15
1
1.5
3
15
15
20
ns
t8
t9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
CL = 50 pF
Note 3
5-12,5-15
5-15
1
3
15
20
ns
t10
t10a
ADS#, D/C#, MIIO#, W/R# valid delay
SMADS# valid delay
CL=50pF
CL = 50 pF
5-12,5-15
5-12,5-15
1.5
1.5
15
15
ns
t11
t11a
ADS#, D/C#, Mil 0#, W/R# float delay
SMADS# float delay
Note 3
Note 3
5-15
5-15
·~~:~~fo
ns
ns
7
7
3
3 ,:~{
....
t12
t12a
t13
D31-DO write data, SUSPA# valid delay
D31 - DO write data hold time
D31-DO write data, SUSPA# float delay
CL= 50 pF
Note 5
Note 3
t14
HLDA valid delay
CL = 50 pF
t15
t16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
t17
t18
BS16 setup time
BS 16 hold time
t19
t20
5-12,5-13
5-14
5-15
k··
I.):'='<,
24
l~
ns
;;i~
20
5-15
1.5
20
5-11
5-11
5
3
ns
5-11
5-11
8
5
ns
READY# setup time
READY# hold time
5-11
5-11
9
4
ns
t21
t22
D31-DO read data setup time
D31 - DO read data hold time
5-11
5-11
7
5
ns
t23
t24
HOLD setup time
HOLD hold time
5-11
5-11
9
3.5
ns
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
8
3
ns
t27
t27a
t28
t28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-11
5-11
5-11
5-11
6
6
6
6
ns
t29
t30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
Note 4
Note 4
5-11
5-11
6
5
ns
t31
Clock-doubled PLL lock time
Note 6
t32
t33
MEMW# setup time
MEMW# hold time
Notes 5, 7
20
5-11
5
5
J.lS
ns
Input clock can be stopped; therefore, minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are determined by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) Delay time from setting CKD in CCRO to entering clock-doubled mode
7) MEMW# is available on the 144-pin QFP and 168-pin PGA only.
ADVANCE INFORMATION concerns new products In the sampling or
New page 5-21 A
preproduction phase of development Characteristic data and either
Notes:
1)
2)
3)
4)
ns
specifications are subject to change without notlca.
Addendum-10
AC Characteristics
Table 5-188 covers the 3.3-V, 40-MHz or 40/20-MHz TI486SXLC-G40.
Table 5-188. AC Characteristics for TI486SXLC-G40, Vce = 3 V to 3.6 \I, Te
Symbol
Parameter
= 0 to 85°C
TI486SXLC· G40
Test
Conditions
Figures
Min
32
CLK2 clock-doubled frequency range
Max
Unit
40
MHz
t1
t2a
t2b
t3a
t3b
t4
t5
CLK2 period (clock-doubled period)
CLK2 high time (clock-doubled high time)
CLK2 high time (clock-doubled high time)
CLK2 low time (clock-doubled low time)
CLK2 low time (clock-doubled low time)
CLK2 fall time (clock-doubled fall time)
CLK2 rise time (clock-doubled rise time)
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
5.:4
5-4
5-4
5-4
5-4
5-4
5-4
t6
t6a
t7
A23-A 1 valid delay
SMI# valid delay
A23-A 1 float delay
CL = 50 pF
CL = 50 pF
Note 3
5-12,5-15
5-12,5-15
5-15
1
1.5
3
15.5
12.5
17
ns
t8
t9
BHE#, BLE#, LOCK# valid delay
BHE#, BLE#, LOCK# float delay
CL = 50 pF
Note 3
5-12,5-15
5-15
1
3
12.5
17
ns
t10
t10a
AOS#, O/C#, MIIO#, W/R# valid delay
SMAOS# valid delay
CL = 50 pF
CL = 50 pF
5-12,5-15
5-12,5-15
1.5
1.5
12.5
12.5
ns
t11
t11a
AOS#, O/C#, MIIO#, W/R# float delay
SMAOS# float delay
Note 3
Note 3
5-15
5-;15
t12
t12a
t13
015-00 write data, SUSPA# valid delay
015-00 write data hold time
015-00 write data, SUSPA# float delay
CL = 50 pF
Note 5
Note 3,6
5-12,5-13
5-14
5-15
17
.,.;~ ;,~><,;.;;~+" 17
1. .:::~~~~.; ;~;:~:~t'" 20
<. ,~. :$:;
t~~;'
14.5
CL
12.5 (25)
5 (8)
3.25 (5)
5 (8)
3.25 (6)
ns
4 (8)
4 (8)
3
3
ns
ns
t14
HLOA valid delay
5-15
<:~~f::5
t15
t16
NA#, SUSP#, FLUSH#, KEN#, A20M# setup time
NA#, SUSP#, FLUSH#, KEN#, A20M# hold time
5-11
5-11
4
3
ns
t19
t20
REAOY# setup time
REAOY# hold time
5-11
5-11
7
3
ns
t21
t22
015 - DO read data setup time
015-00 read data hold time
5-11
5-11
5
3
ns
t23
t24
HOLD setup time
HOLD hold time
5-11
5-11
7
2
ns
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
5
2
ns
t27
t27a
t28
t28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-11
5-11
5-11
5-11
5
5
5
5
ns
t29
t30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
Note 4
Note 4
5-11
5-11
5
3
ns
Clock-doubled PLL lock time
Note 7
t31
Notes:
= 50 pF
17
20
ns
J.1S
Input clock can be stopped; therefore, minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are determined by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold-acknowledge state.
7) Delay time from setting CKO in CCRO to entering clock-doubled mode
1)
2)
3)
4)
ADVANCE INFORMATION concerns new products In the sampling or
preproduction phase of development Characteristic data and other
speclftcatlons are subject to change without notice.
New page 5-21 B
Addendum-11
AC Characteristics
Table 5-18C covers the 3.3-V, 50-MHz TI486SXL2C-G50.
Table 5-18C. AC Characteristics for TI486SXLC2-G50, Vee = 3 V to 3.6 V,
Te = Oto 85°C
Symbol
Parameter
T1486SXLC2-G50
Test
Conditions
Figures
CLK2 clock-doubled frequency range
Min
Max
Unit
32
50
MHz
t1
t2a
t2b
t3a
t3b
t4
t5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
5-4
5-4
5-4
5-4
5-4
5-4
5-4
20
7
4
7
5
t6
t6a
t7
A23-A1 valid delay
SMI# valid delay
A23-A1 float delay
CL =50 pF
CL = 50 pF
Note 3
5-12,5-15
5-12,5-15
5-15
1
1.5
3
17
30
30
t8
t9
BHE#, BLE#, LOCK# valid delay
BHE#, BLE#, LOCK# float delay
CL=50pF
Note 3
5-12,5-15
5-15
1
3
30
t10
t10a
ADS#, D/C#, M/IO#, W/R# valid delay
SMADS# valid delay
CL = 50 pF
CL =50 pF
5-12,5-15
5-12,5-15
1.5
1.5
17
t11
t11 a
ADS#, D/C#, M/IO#, W/R# float delay
SMADS# float delay
Note 3
Note 3
5-15
5-15
3
3
.; ~;~:~~;;:~JjS
t12
t12a
t13
D15-DO write data, SUSPA#valid delay
D15- DO write data hold time
D15- DO write data, SUSPA# float delay
CL =50 pF
Note 5
Note 3,6
5-12,5-13
5-14
5-15
t14
HLDA valid delay
CL = 50 pF
t15
t16
NA#, SUSP#, FLUSH#, KEN#, A20M# setup time
NA#, SUSP#, FLUSH#, KEN#, A20M# hold time
5-11
5-11
5
3
ns
t19
t20
READY# setup time
READY# hold time
5-11
5-11
9
4
ns
t21
t22
D15- DO read data setup time
D15-DO read data hold time
5-11
5-11
7
5
ns
t23
t24
HOLD setup time
HOLD hold time
5-11
5-11
3.5
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
8
3
ns
t27
t27a
t28
t28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-11
5-11
5-11
5-11
6
6
6
6
ns
t29
t30
PEREa, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
Note 4
Note 4
5-11
5-11
6
5
ns
t31
Clock-doubled PLL lock time
Note 7
Notes:
5-15
ns
7
7
17
17
~~
y·S
~~:lP·
ns
ns
ns
ns
23
ns
22
22
9
ns
ns
20
!ls
1)
2)
3)
4)
Input clock can be stopped; therefore, minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are determined by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold-acknowledge state.
7) Delay time from setting CKD in CCRO to entering clock-doubled mode
ADVANCE INFORMATION concerns new products In the sampling or
preproduction phase of development Characteristic data and other
specifications are subject to change without notice.
Addendum-12
New page 5-21 C
AC Characteristics
5.5.3.2 AC Data for 3.3-Volt Microprocessors
Table 5-19 covers the 3.3-V, 25-MHz TI486SXLC-V25.
Table 5-19. AC Characteristics for T14868XLC- V25, Vee
=3
V to 3.6 \I, Te
= 0 to 85°C
TI486SXLC· V25
Parameter
Test
Conditions
Figures
t1
t2a
t2b
t3a
t3b
t4
t5
CLK2
CLK2
CLK2
CLK2
CLK2
CLK2
CLK2
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
5-4
5-4
5-4
5-4
5-4
5-4
5-4
20
7
4
7
5
t6
t6a
t7
A23-A1 valid delay
SMI# valid delay
A23-A 1 float delay
CL = 50 pF
CL = 50 pF
Note 3
5-7,5-10
5-7,5-10
5-10
1
1.5
4
21
30
30
ns
t8
t9
BHE#, BLE#, LOCK# valid delay
BHE#, BLE#, LOCK# float delay
CL = 50 pF
Note 3
5-7,5-10
5-10
1
4
18
30
ns
t10
t10a
AOS#, O/C#, MIIO#, W/R# valid delay
SMAOS# valid delay
CL = 50 pF
CL = 50 pF
5-7,5-10
5-7,5-10
1.5
1.5
19
,,': i;~::> f";f,),g
ns
t11
t11 a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
Note 3
Note 3
5-10
5-10
: : ~ ;~;~} :;;:S:~"" ~g
ns
t12
t12a
t13
015-00 write data, SUSPA# valid delay
015-00 write data hold time
015-00 write data, SUSPA# float delay
CL = 50 pF
Note 5
Notes 3,6
5-7,5-8
5-9
5-10
t14
HLOA valid delay
CL = 50 pF
t15
NA#, SUSP#, FLUSH#, KEN#, A20M# setup
time
NA#, SUSP#, FLUSH#, KEN#, A20M# hold
time
Symbol
t16
period
high time
high time
low time
low time
fall time
rise time
Min
Max
Unit
11S
7
7
..
":
,~~~~~"~
27
ns
4
22
5-10
2
22
5-6
5
5-6
3.5
ns
ns
t19
t20
REAOY# setup time
REAOY# hold time
5-6
5-6
9
4
ns
t21
t22
015-00 read data setup time
015-00 read data hold time
5-6
5-6
7
5
ns
t23
t24
HOLD setup time
HOLD hold time
5-6
5-6
9
3.5
ns
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
8
3
ns
t27
t27a
t28
t28a
NMI,INTR setup time
SMI# setup time
NMI,INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-6
5-6
5-6
5-6
6
6
6
6
ns
t29
t30
PEREQ, ERROR#, BUSY# setup time
PEREa, ERROR#, BUSY# hold time
Note 4
Note 4
5-6
5-6
6
5
ns
Notes:
1)
2)
3)
4)
Input clock can be stopped; therefore, minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are determined by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold-acknowledge state.
Replaces original page 5-22
ADVANCE INFORMATION concerns new products In the sampling or
preproduction phase of development. Characteristic data and other
speclflcadons are subject to change without notice.
Addendum-13
AC Characteristics
Table 5-20 covers the
3.3-V, 40-MHz or 40/20-MHz TI486SXL-V40.
'.
Table 5-20.
Symbol
AC Characteristics for T1486SXL-V40, Vee
Parameter
Test
Conditions
= 3 V to 3. 6 V,
Te
= 0 to 85°C
T1486SXL-V40
Figures
CLK2 clock-cloubled
frequency range
Min
Max
Unit
40
MHz
32
t1
t2a
t2b
t3a
t3b
t4
t5
CLK2 period (clock-doubled period)
CLK2 high time (clock-doubled high time)
CLK2 high time (clock-doubled high time)
CLK2 low time (clock-doubled low time)
CLK2 low time (clock-doubled low time) .
CLK2 fall time (clock-doubled fall time)
CLK2 rise time (clock-doubled rise time)
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
5-4
5-4
5-4
5-4
5-4
5-4
5-4
12.5 (25)
5 (8)
3.25 (5)
5 (8)
3.25 (6)
t6
t6a
t7
A31 - A2 valid delay
SMI# valid delay
A31-A2 float delay
CL= 50 pF
CL= 50 pF
Note 3
5-12,5-15
5-12,5-15
5-15
1
1.5
3
15.5
12.5
17
ns
t8
t9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
CL=50pF
Note 3
5-12,5-15
5-15
1
3
12.5
17
ns
t10
t10a
ADS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
CL=50pF
CL= 50 pF
5-12,5-15
5-12,5-15
1.5
1.5
12.5
12.5
ns
t11
t11a
ADS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
Note 3
Note 3
5-15
5-15
. 17
r~~&>~7
ns
t12
t12a
t13
031-00 write data, SUSPA# valid delay
031 - DO write data hold time
031-00 write data, SUSPA# float delay
CL=50pF
Note 5
Note 3
5-12,5-13
5-14
5-15
20
ns
CL = 50 pF
14.5
17
ns
ns
4 (8)
4 (8)
),. '1
3
t'
'>
t14
HLOA valid delay
5-15
".~
'<:~r5
t15
t16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
5-11
5-11
4
3
ns
t17
t18
BS 16 setup time
BS 16 hold time
5-11
5-11
8
2
ns
t19
t20
REAOY# setup time
REAOY# hold time
5-11
5-11
7
3
ns
t21
t22
031-00 read data setup time
031-00 read data hold time
5-11
5-11
5
3
ns
t23
t24
HOLD setup time
HOLD hold time
5-11
5-11
7
2
ns
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
5
2
ns
t27
t27a
t28
t28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-11
5-11
5-11
5-11
5
5
5
5
ns
t29
t30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
Note 4
Note 4
5-11
5-11
5
3
ns
t31
Clock-doubled PLL lock time
Note 6
t32
t33
MEMW# setup time
MEMW# hold time
5-11
5
5
Notes:
Notes 5, 7
20
!JS
ns
1)
2)
3)
4)
Input clock can be stopped; therefore, minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are determined by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) Delay time from setting CKO in CCRD to entering clock-doubled mode
7) MEMW# is available on the 144-pin QFP and 168-pin PGA only.
ADVANCE INFORMATION concerns new products In the sampling or
preproduction phase of development. Characteristic data and other
speclftcatlons are subject to change without notice.
Addendum-14
Replaces original page 5-23
AC Characteristics
Table 5-21 covers the 3.3-V, 50-MHz TI486SXL2-V50.
Table 5-21. AC Characteristics for TI486SXL2-V50, Vee
Te = 0 to 85°C
Symbol
Parameter
Test
Conditions
= 3 V to 3.6 V,
T1486SXL2-V50
Figures
CLK2 clock-doubled frequency range
Min
Max
Unit
32
50
MHz
t1
t2a
t2b
t3a
t3b
t4
t5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
Note 1
Note 2
Note 2
Note 2·
Note 2
Note 2
Note 2
5-4
5-4
5-4
5-4
5-4
5-4
5-4
20
7
4
7
5
t6
t6a
t7
A31-A2 valid delay
SMI# valid delay
A31-A2 float delay
CL = 50 pF
CL= 50 pF
Note 3
5-12,5-15
5-12,5-15
5-15
1
1.5
3
17
30
30
ns
t8
t9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
CL = 50 pF
Note 3
5-12,5-15
5-15
1
3
17
30
ns
t10
t10a
ADS#, D/C#, MIIO#, W/R# valid delay
SMADS# valid delay
CL = 50 pF
CL= 50 pF
5-12,5-15
5-12,5-15
1.5
1.5
17
17
ns
t11
t11a
ADS#, D/C#, MIIO#, W/R# float delay
SMADS# float delay
Note 3
Note 3
5-15
5-15
t12
t12a
t13
031-00 write data, SUSPA# valid delay
031-00 write data hold time
031-00 write data, SUSP,A# float delay
CL = 50 pF
Note 5
Note 3
5-12,5-13
5-14
5-15
x.~ ::)~~{~g
~~?,:~:>' 23
......... v
1;J:~~;~
~l <~»:-::~.
t14
HLDA valid delay
CL=50pF
5-15
'Y.5
t15
t16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
5-11
5-11
5
3
ns
t17
t18
BS 16 setup time
BS 16 hold time
5-11
5-11
8
5
ns
t19
t20
REAOY# setup time
READY# hold time
5-11
5-11
9
4
ns
t21
t22
031-DO read data setup time"
031 - DO read data hold time
5-11
5-11
7
5
ns
t23
t24
HOLD setup time
HOLD hold time
5-11
5-11
9
3.5
ns
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
8
3
ns
t27
t27a
t28
t28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-11
5-11
5-11
5-11
6
6
6
6
ns
t29
t30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
Note 4
Note 4
5-11
5-11
6
5
ns
t31
Clock-doubled PLL lock time
Note 6
t32
MEMW# setup time
MEMW# hold time
t33
Notes:
Notes 5, 7
ns
7
7
3
3
~
~.
.::~;,~:w'
5-11
..
Input clock can be stopped; therefore, minimum CLK2 frequency IS 0 MHz .
ns
22
22
20
5
5
ns
ns
""S
ns
1)
2) These parameters are not tested. They are determined by design characterization.
3) Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
4) These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) Delay time from setting CKD in CCRO to entering clock-doubled mode
7) MEMW# is available on the 144-pin QFP and 168-pin PGA only.
Replaces original page 5-24
ADVANCE INFORMATION concerns new products In the sampling or
preproduction phase of development Characteristic data and other
speclflcallons are subject to change without notice.
Addendum-15
AC Characteristics
5.5.3.3 A C Data for 5· Volt Microprocessors
Table 5-22 covers the 5-V, 40-MHz or 40/20-MHz TI486SXLC-040.
Table 5-22. AC Characteristics for TI486SXLC-040, Vee
Te = 0 to 100°C
Symbol
Parameter
= 4.75 V to 5.25 \I,
TI486SXLC-040
Test
Conditions
Figures
Min
32
CLK2 clock-doubled frequency range
Max
Unit
40
MHz
t1
t2a
t2b
t3a
t3b
t4
t5
CLK2 period (clock-doubled period)
CLK2 high time (clock-doubled high time)
CLK2 high time (clock-doubled high time)
CLK2 low time (clock-doubled low time)
CLK2 low time (clock-doubled low time)
CLK2 fall time (clock-doubled fall time)
CLK2 rise time (clock-doubled rise time)
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
5-4
5-4
5-4
5-4
5-4
5-4
5-4
t6
t6a
t7
A23-A1 valid delay
SMI# valid delay
A23-A1 float delay
CL = 50 pF
CL=50pF
Note 3
5-7,5-10
5-7,5-10
5-10
1.5
1.5
3
15
12.5
17
ns
t8
t9
BHE#, BLE#, LOCK# valid delay
BHE#, BLE#, LOCK# float delay
CL=50pF
Note 3
5-7,5-10
5-10
1.5
3
12.5
17
ns
t10
t10a
AOS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
CL = 50 pF
CL=50pF
5-7,5-10
5-7,5-10
1.5
1.5
12.5
12.5
ns
t11
t11 a
AOS#, O/C#, M/IO#, W/R# float delay
SMAOS# float delay
Note 3
Note 3
5-10
5-10
3
3
17
17
ns
t12
t12a
t13
015- DO write data, SUSPA# valid delay
015-00 write data hold time
015- DO write data, SUSPA# float delay
CL = 50 pF
Note 5
Notes 3,6
5-7,5-8
5-9
5-10
2
2
3
20
14.5
t14
HLOA valid delay
CL = 50 pF
5-10
2
17
t15
t16
NA#, SUSP#, FLUSH#, KEN#, A20M# setup time
NA#, SUSP#, FLUSH#, KEN#, A20M# hold time
5-6
5-6
4
3
ns
t19
t20
REAOY# setup time
REAOY# hold time
5-6
5-6
7
3
ns
t21
t22
015- DO read data setup time
015- DO read data hold time
5-6
5-6
5
3
ns
t23
t24
HOLD setup time
HOLD hold time
5-6
5-6
7
2
ns
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
5
2
ns
t27
t27a
t28
t28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-6
5-6
5-6
5-6
5
5
5
5
ns
t29
t30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
Note 4
Note 4
5-6
5-6
5
3
ns
Clock-doubled PLL lock time
Note 7
t31
Notes:
12.5 (25)
5 (8)
3.25 (5)
5 (8)
3.25 (6)
ns
4 (8)
4 (8)
ns
20
ns
!1S
1)
2)
3)
4)
Input clock can be stopped; therefore, minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are determined by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold-acknowledge state.
7) Delay time from setting CKO in CCRO to entering clock-doubled mode
Replaces original page 5-25
Addendum-16
AC Characteristics
Table 5-23 covers the 5-V, 50-MHz TI486SXLC2-050.
Table 5-23.
Symbol
AC Characteristics for TI486SXLC2-050, Vee
Te = 0 to 100°C
Parameter
= 4.75 V to 5.25 \/,
T1486SXLC2-050
Test
Conditions
Figures
CLK2 clock-cfoubled frequency range
Min
Max
Unit
32
50
MHz
t1
t2a
t2b
t3a
t3b
t4
t5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
5-4
5-4
5-4
5-4
5-4
5-4
5-4
20
7
4
7
5
t6
t6a
t7
A23-A1 valid delay
SMI# valid delay
A23-A 1 float delay
CL=50pF
CL = 50 pF
Note 3
5-7,5-10
5-7,5-10
5-10
1.5
1.5
3
17
30
30
ns
t8
t9
BHE#, BLE#, LOCK# valid delay
BHE#, BLE#, LOCK# float delay
CL = 50 pF
Note 3
5-7,5-10
5-10
1.5
3
17
30
ns
t10
t10a
AOS#, O/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
CL=50pF
CL = 50 pF
5-7,5-10
5-7,5-10
1.5
1.5
17
17
ns
t11
AOS#, O/C#, MIIO#, W/R# float delay
SMAOS# float delay
Note 3
Note 3
5-10
5-10
3
3
30
30
ns
015-00 write data, SUSPA# valid delay
015-00 write data hold time
015-00 write data, SUSPA# float delay
CL = 50 pF
Note 5
Notes 3,6
5-7,5-8
5-9
5-10
2
2
3
23
22
CL = 50 pF
22
t11a
t12
t12a
t13
ns
7
7
ns
t14
HLOA valid delay
5-10
2
t15
t16
NA#, SUSP#, FLUSH#, KEN#, A20M# setup time
NA#, SUSP#, FLUSH#, KEN#, A20M# hold time
5-6
5-6
5
3
ns
t19
t20
REAOY# setup time
REAOY# hold time
5-6
5-6
9
4
ns
t21
t22
015-00 read data setup time
015-00 read data hold time
5-6
5-6
7
5
ns
t23
t24
HaLO setup time
HaLO hold time
5-6
5-6
3.5
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
8
3
ns
t27
t27a
t28
t28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-6
5-6
5-6
5-6
6
6
6
6
ns
t29
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
Note 4
Note 4
5-6
5-6
6
5
ns
Clock-doubled PLL lock time
Note 7
t30
t31
Notes:
9
ns
ns
20
~s
1)
2)
3)
4)
Input clock can be stopped; therefore, minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are determined by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) SUSPA# floats only in response to activation of FLT#. SUSPA# does not float during a hold-acknowledge state.
7) Oelay time from setting CKO in CCRO to entering clock-doubled mode
Replaces original page 5-26
Addendum-17
AC Characteristics
Table 5-24 covers the 5-V, 40-MHz or 40/20-MHz TI486SXL-040.
Table 5-24. AC Characteristics for T1486SXL-040, Vee = 4.75 V to 5.25 \I,
(for Te see Table 5-6)
Symbol
Parameter
Test
Conditions
TI486SXL-040
Figures
CLK2 clock-doubled frequency range
t1
t2a
t2b
t3a
t3b
t4
t5
CLK2
CLK2
CLK2
CLK2
CLK2
CLK2
CLK2
t6
t6a
t7
period (clock-doubled period)
high time (clock-doubled high time)
high time (clock-doubled high time)
low time (clock-doubled low time)
low time (clock-doubled low time)
fall time (clock-doubled fall time)
rise time (clock-doubled rise time)
Min
32
Max
Unit
40
MHz
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
5-4
5-4
5-4
5-4
5-4
5-4
5-4
A31-A2 valid delay
SMI# valid delay
A31-A2 float delay
CL =50 pF
CL= 50 pF
Note 3
5-12,5-15
5-12,5-15
5-15
1.5
1.5
3
15
12.5
17
ns
t8
t9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
CL = 50 pF
Note 3
5-12,5-15
5-15
1.5
3
12.5
17
ns
t10
t10a
AOS#, 0/C#, M/IO#, W/R# valid delay
SMAOS# valid delay
CL = 50 pF
CL= 50 pF
5-12,5-15
5-12,5-15
1.5
1.5
12.5
12.5
ns
t11
t11a
AOS#, 0/C#, M/IO#, W/R# float delay
SMAOS# float delay
Note 3
Note 3
5-15
5-15
3
3
17
17
ns
t12
t12a
t13
031-00 write data, SUSPA# valid delay
031 - 00 write data hold time
031-00 write data, SUSPA# float delay
CL= 50 pF
Note 5
Note 3
5-12,5-13
5-14
5-15
2
2
3
20
14.5
t14
HLOA valid delay
CL= 50 pF
5-15
2
17
t15
t16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
5-11
5-11
4
3
ns
t17
t18
BS16 setup time
BS16 hold time
5-11
5-11
8
5
ns
t19
t20
REAOY# setup time
REAOY# hold time
5-11
5-11
7
3
ns
t21
t22
031 - 00 read data setup time
031-00 read data hold time
5-11
5-11
5
3
ns
t23
t24
HaLO setup time
HaLO hold time
5-11
5-11
7
2
ns
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
5
2
ns
t27
t27a
t28
t28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-11
5-11
5-11
5-11
5
5
5
5
ns
t29
t30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
Note 4
Note 4
5-11
5-11
5
3
ns
t31
Clock-doubled PLL lock time
Note 6
t32
t33
MEMW# setup time
MEMW# hold time
5-11
5
5
Notes:
Notes 5,7
12.5 (25)
5 (8)
3.25 (5)
5 (8)
3.25 (6)
ns
4 (8)
4 (8)
ns
20
ns
!AS
ns
1)
2)
3)
4)
Input clock can be stopped; therefore, minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are determined by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) Oelay time from setting CKO in CCRO to entering clock-doubled mode
7) MEMW# is available on the 144-pin QFP and 168-pin PGA only.
Replaces original page 5-27
Addendum-18
AC Characteristics
Table 5-25 covers the 5-V 50-MHz T1486SXL2-050
Table 5-25. AC Characteristics for T1486SXL2-050, Vee
(for Te see Table 5-6)
Symbol
Parameter
Test
Conditions
= 4.75 V to 5.25 \I,
T1486SXL2-050
Figures
CLK2 clock-doubled frequency range
Min
Max
Unit
32
50
MHz
t1
t2a
t2b
t3a
t3b
t4
t5
CLK2 period
CLK2 high time
CLK2 high time
CLK2 low time
CLK2 low time
CLK2 fall time
CLK2 rise time
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
5-4
5-4
5-4
5-4
5-4
5-4
5-4
20
7
4
7
5
t6
t6a
t7
A31 - A2 valid delay
SMI# valid delay
A31-A2 float delay
CL = 50 pF
CL = 50 pF
Note 3
5-12,5-15
5-12,5-15
5-15
1.5
1.5
3
17
30
30
ns
t8
t9
BE3# - BEO#, LOCK# valid delay
BE3# - BEO#, LOCK# float delay
CL = 50 pF
Note 3
5-12,5-15
5-15
1.5
3
17
30
ns
t10
t10a
ADS#, D/C#, M/IO#, W/R# valid delay
SMADS# valid delay
CL= 50 pF
CL = 50 pF
5-12,5-15
5-12,5-15
1.5
1.5
17
17
ns
t11
t11 a
ADS#, D/C#, M/IO#, W/R# float delay
SMADS# float delay
Note 3
Note 3
5-15
5-15
3
3
30
30
ns
t12
t12a
t13
D31 - DO write data, SUSPA# valid delay
D31 - DO write data hold time
D31- DO write data, SUSPA# float delay
CL = 50 pF
Note 5
Note 3
5-12,5-13
5-14
5-15
2
2
3
23
t14
HLDA valid delay
CL=50pF
5-15
2
22
t15
t16
A20M#, FLUSH#, KEN#, NA#, SUSP# setup time
A20M#, FLUSH#, KEN#, NA#, SUSP# hold time
5-11
5-11
5
3
ns
t17
t18
BS 16 setup time
BS 16 hold time
5-11
5-11
8
5
ns
t19
t20
READY# setup time
READY# hold time
5-11
5-11
9
4
ns
t21
t22
D31 - DO read data setup time
D31-DO read data hold time
5-11
5-11
7
5
ns
t23
t24
HOLD setup time
HOLD hold time
5-11
5-11
9
3.5
ns
t25
t26
RESET setup time
RESET hold time
Note 5
5-5
5-5
8
3
ns
t27
t27a
t28
t28a
NMI, INTR setup time
SMI# setup time
NMI, INTR hold time
SMI# hold time
Note 4
Note 4
Note 4
Note 4
5-11
5-11
5-11
5-11
6
6
6
6
ns
t29
t30
PEREQ, ERROR#, BUSY# setup time
PEREQ, ERROR#, BUSY# hold time
Note 4
Note 4
5-11
5-11
6
5
ns
t31
Clock-doubled PLL lock time
Note 6
t32
t33
MEMW# setup time
MEMW# hold time
Notes:
Notes 5, 7
ns
7
7
ns
22
20
5-11
5
5
ns
""s
ns
1)
2)
3)
4)
Input clock can be stopped; therefore, minimum CLK2 frequency is 0 MHz.
These parameters are not tested. They are determined by design characterization.
Float condition occurs when maximum output current becomes less than II in magnitude. Float is not 100% tested.
These inputs are allowed to be asynchronous to CLK2. The setup and hold specifications are given for testing purposes, to assure recognition within a specific CLK2 period.
5) Not 100% tested
6) Delay time from setting CKD in CCRO to entering clock-doubled mode
7) MEMW# is available on the 144-pin QFP and 168-pin PGA only.
Replaces original page 5-28
Addendum-19
Thermal Characteristics
6.3 Thermal Characteristics
The junction-to-ambient (typical) values vary for individual applications depending on factors relating to how the device is mounted and the surrounding
environment such as:
o
Circuit trace density of the printed circuit board (PCB) and/or the presence
or absence of ground or power planes internal to the PCB that affect the
ability of the board to conduct heat away from the device
o
o
Whether the device is soldered to the PCB or is inserted into a socket
Orientation of the PCB that the device is mounted on and the proximity of
adjacent PCBs or system enclosure features that impede natural convection air circulation around the device
o
Ambient air temperature in close proximity to the device and the proximity
of other high-power devices in the system
o
Presence of airflow over the device and the attachment of an external heat
sink as indicated by the data in Tables 6-10 and 6-12.
For the 100-pin and 144-pin QFPs, the values shown for thermal resistance
in Tables 6-10 and 6-12 with a heatsink are examples of the estimated improvement in thermal performance.
Note:
The final responsibility for verifying designs incorporating any version of a TI
microprocessor rests with the customer originating the design. Recommended case temperature extremes are specified in Tables 5-4, 5-5, and
5-6.
Table 6-10.
TI486SXLC 1~O-Pin PQFP Thermal Resistance and Airflow
Thermal Resistance (OC/W)
TI486SXLC 100-Pin PQFP
Without Heatsink
Airflow (FtlMin)
With Heatsinkt
RaJC
RaJA
R!;)JA
o
2
36
32
600
2
15
12
t Round, omnidirectional heatsink. Dimensions are approximately 1.125 in diameter by 0.42 in
high.
Replaces original page 6-18
Addendum-20
ADVANCE INFORMATION concerns new products In the sampling or
preproduction phase of development. Characteristic dati and other
specifications are subJect to change without notice.
Thermal Characteristics
_ _ _ _ _ _ _ _·~_~:m_:;.._ .. _u:._.a:.~_J:.::'_.l:Q:g",_.::.o_lQ:Q.~_
.......,_;;.:_;m_.:::':':_:W::_ _
!.l_:nQ~
....
m.""K:.:."":.:.;"".."".:m....
c._.
U....
:;-:Q _''''''~:1:.:....
a:.:»»:a.:»».:.;:.l''''.:.l:»»!a:_.:m»»:;c~c_:Q:n_a:.:._l.:.:.:.ern:.:.:.:.ern~.:.:ern.:.:.:."":.:.::ernl.:.,...:.m;"".m:ern::.Kern:.>':."::»....
,ern._
Table 6-10A.
.....
TI486SXLC 1~O-Pin CQFP Thermal Resistance and Airflow
Thermal Resistance caCIW)
TI486SXLC 100-Pin CQFPt
Airflow (FtlMin)
RaJC
RaJA
Jt;~~;:<:.J.~~~:·
o
.~>.~~::;;1~:J~!$
------------------+-------~~~------r-----~
100
200
t Thermal resistance values shown are based on measurements made on similar ceramic PGA
packages.
Table 6-11.
TI486SXL 132-Pin CPGA Thermal Resistance and Airflow
Thermal Resistance (OC/W)
TI486SXL 132-Pin CPGAt:
Airflow (FtlMin)
o
100
------------------+-------
RaJC
RaJA
3
20
,,::~~~~{30-~
200
400
600
3
9
:t: Thermal resistance values shown are based on measurements made on similar ceramic PGA
packages.
Table 6-12.
TI486SXL 144-Pin PQFP Thermal Resistance and Airflow
Thermal Resistance caC/W)
TI486SXL 144-Pin PQFP§
Without Heatsink
Airflow (FtlMin)
o
With Heatsink§
RaJC
RaJA
RaJA
2
25
18
2 . f ~ii~~;~i;~i>'21
100
---------------~------~
...
200
2
14
400
600
19
2
12
6
§ Thermal resistance values shown are based on measurements made on similar 28-mm QFP
packages.
~ Pin-Fin heatsink. Dimensions are approximately 1.2 in long, by 1.3 in wide, by 0.49 in high.
ADVANCE INFORMATION concerns new products In the sampling or
preproduction phase of development Characteristic data and other
specifications are subject to change wlihout noUce.
Replaces original page 6-19
Addendum-21
Thermal Characteristics
Table 6-13. TI486SXL 144-Pin CQFP Thermal Resistance and Airflow
Thermal Resistance COC/W)
TI486SXL 144-Pin CQFPt
Airflow (FtlMin)
o
100
200
t Thermal resistance values shown are based on measurements made on similar ceramic QFP
packages.
Table 6-14.
TI486SXL 168-Pin CPGA Thermal Resistance and Airflow
Thermal Resistance COC/W)
168-Pin CPGA Package:t:
Airflow (FtlMin)
o
RaJC
RaJA
3
18
100
200
400
3
600
3
8
:t: Thermal resistance values shown are based on measurements made on similar ceramic PGA
packages.
6.3.1
Airflow Measurement Setup
The wind tunnel used for airflow measurements is represented schematically
in Figure 6-12.
Figure 6-12. Wind Tunnel Schematic Diagram
Device test board
Temperature and
anemometer-type
airflow probe
>
AirflOW>
Fan
Wind tunnel cross-section is 6 in by 6 in.
(Dimensions are approximate.)
~--------------------------78
~5 in ~14
24 in
in---------------------------.
Typically, the devices undergoing thermal test are mounted on a test board
consisting of 0.062 in thick FR4 printed circuit board material with one-ounce
Replaces original page 6-20
Addendum-22
ADVANCE INFORMATION concerns new products In the sampling or
preproduction phase of development. Charectarlstlc data and other
specifications are aublect to change without notice.
Thermal Characteristics
copper etch. Surface-mount devices are soldered to the test board using
matching footprints with minimal circuit trace density required to electrically interconnect the device to the board. PGA devices are typically inserted in a
socket that is soldered to the test board.
6.3.2
Thermal Parameter Definitions
The maximum die temperature (TJmax) and the maximum ambient temperature (TAmax) can be calculated using the following equations:
TJmax = TC + (Pmax x RaJC)
TAmax = TJ - (Pmax x RaJA))
where:
TJmax = Maximum average junction temperature (OC)
TC = Case temperature at top center of package (OC)
Pmax = Maximum device power dissipation (W)
RaJC = Junction-to-case thermal resistance (OC/W)
TAmax = Maximum ambient temperature (OC)
TJ = Average junction temperature (OC)
RajA = Junction-to-ambient thermal resistance (OC/W)
Values for RaJC and RaJA are given in Tables 6-10 through 6-14 for various
airflows.
Replaces original page 6-21
Addendum-23
Part Numbers for Microprocessors Offered
t.~
~;
.. :Q:Q:Q:QQ
•
U .. ; ..:.
H
;:U:Q. l '
:Q
U
~
Jm
.11
F.2 Part Numbers for Microprocessors Offered
Table F-1 lists the complete part number for each version of the TI486SXL microprocessors offered, and Table F-2 lists the part number for each version
of the TI486SLC/DLC microprocessors offered. The tables provide a short description consisting of the supply voltage, performance capabilities, and the
mechanical package for each device part number.
Table F-1. TI486SXLC and TI486SXL Part Numbers
Speed (MHz)
Device Part Number
Supply Voltage (V)
Core
Bus
TX486SXLCB-V25-PJF
3.3
25
25
TX486SXLCB-040-PJF
5
40
40,20 t
TX486SXLC2B-050-PJF
5
50
25
(TX486SXLC-G40-WN
3.3 (5-V tolerant)
40
40,20t
(TX486SXL2C-G50-WN
3.3 (5-V tolerant)
50
25
TX486SXLB-040S-GA
5
40
40,20t
TX486SXL2B-050S-GA
5
50
25
TX486SXLB-040-PCE
5
40
40,20t
TX486SXL-G40-HBN
3.3 (5-V tolerant)
40
40,20 t
TX486SXl2-G50-HBN
3.3 (5-V tolerant)
50
25
TX486SXl2-G50-HBN
3.3 (5-V tolerant)
66
33
TX486SXLB-040-HBN
5
40
40,20 t
TX486SXl2B-050-HBN
5
50
25
TX486SXL-G40-GA
3.3 (5-V tolerant)
40
40,20t
TX486SXl2-G50-GA
3.3 (5-V tolerant)
50
25
(TX486SXl2-G66-GA
3.3 (5-V tolerant)
66
33
TX486SXLB-V40-GA
3.3
40
40,20t
TX486SXl2B-V50-GA
3.3
50
25
TX486SXLB-040-GA
5
40
40,20 t
TX486SXl2B-050-GA
5
50
25
Package
1OO-pin TE p:j: plastic QFP
100-pin ceramic
QFP
132-pin PGA
144-pin TEP plastic
QFP
144-pin ceramic
QFP
168-pin PGA
t These microprocessors can be operated as nonclock-doubled 40 MHz or clock-doubled 20/40 MHz.
:j: Thermally enhanced package
Replaces original page F-2
Addendum-24
NOTES
NOTES
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with Tl's standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
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Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright © 1994, Texas Instruments Incorporated
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North American Authorized Distributors
COMMERCIAL
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For Distributors outside North America, contact your local Sales OffIce.
A11M
Important Notice: Texas Instruments (TI) reserves the right to make changes to or to
discontinue any product or service identified in this publication without notice. TI
advises its customers to obtain the latest version of the relevant information to verify,
before placing orders, that the information being relied upon is current.
Please be advised that TI warrants its semiconductor products and related software to
the specifications applicable at the time of sale in accordance with Tl's standard
warranty. TI assumes no liability for applications aSSistance, software performance, or
third-party product information, or for infringement of patents or services described in this
publication. TI assumes no responsibility for customers' applications or product designs.
~TEXAS
INSTRUMENTS
© 1994 Texas Instruments Incorporated
Printed in the U.S.A.
"TEXAS
INSTRUMENTS
Printed in U.S.A.
1094-IP
SRZU006D
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