1995_Atmel_Microcontroller_Data_Book 1995 Atmel Microcontroller Data Book
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~ n- D o n o z -I D o r MICROCONTROLLER OATA BOOK r m D o o 0 -I ~ o -I m~ m II m .. 0 lD 0 lD III " AlmEl Atmel Corporation Microcontroller Data Book October 1995 is the registered trademark of Atmel Corporation 2125 O'Nel Drive, San Jose, CA 95131 Important Notice Atmel guarantees that its circuits will be free from defects of material and workmanship under normal use and service, and that these circuits will perform to current specifications in accordance with, and subject to, the Company's standard warranty which is detailed in Atmel's Purchasing Order Acknowledgment. Atmel reserves the right to change devices or specifications detailed in this data book at any time without notice, and assumes no responsibility for any errors within this document. Atmel does not make any commitment to update this information. Atmel assumes no responsibility for the use of any circuits described in this data book, nor does the Company assume responsibility for the functioning of undescribed features or parameters. In the absence of a written agreement to the contrary, Atmel assumes no liability with respect to the use of semiconductor devices described in this data book for applications assistance, customers' product design or infringement of patents or copy(ights of third parties. Atmel's products are not authorized for use as critical components in life support devices or systems and the use as such implies that user bears all risk of such use. lf Atmel is an approved vendor on a Standard Military Drawing (SMD), the Atmel similar part number speCification is compliant with the SMD. Trademarks or registered trademarks used in this document may be the property of others. © Atmel Corporation 1995 Printed on recycled paper. Overview Atmel's AT89 Series of Flash Microcontrollers With the Flash memory-based microcontrollers from Atmel, you can achieve safe, easy reconfigurability in any 80C51-based product. With reconfigurability, you can make every product on your line exactly what your customers want. Benefits • Flash memorychange operating code in seconds and shorten development cycle • 8OC51 socket compatibledirect replacement (use existing code) with 40/44-pin devices • Static state clock modesaves power • Stock just one partmake many model options in a flash, JIT • Zero scrap due to rnisprogrammingevery device is reprogrammable • Accelerate final testsubstitute test vectors for operating code in assembly • Make changes remotelyincrease customer satisfaction Each device on the Flash microcontroller family consists of all the core features plus some additional features. A feature comparison of all the Atmel microcontrollers is shown in the table below. The Atmel Family of Flash Microcontrollers Bytes Flash Program MemorY Bvtes Data Memorv Bvtes On Board EEPROM JlO Pins 16-Bit Timer/Counters UART IInterrnnt Sources Power Down and Idle Mode Low Voltal!e Oneration Securitv Lock Bits SPI Serial Interface Watchdol! Timer Dual Data Pointer Internpt Recovery from Power Down AT89C51 AT89lV51 AT89C52 AT89lV52 AT89C2051 AT89C1051 AT89S8252 4K 4K 8K 8K 2K IK 8K 128 RAM 128 RAM 256 RAM 256 RAM 128 RAM 64 RAM 32 2 X 16 X 32 2 X 6 X X 3 32 3 X 8 X 32 3 X 15 2 X 6 X X 2 15 1 256 RAM 12K EEPROM 32 3 X 3 3 8 X X 3 3 X X 2 9 X X 3 X X Ix X Atme! Corporation designs, manufactures, and markets high quality and high performance CMOS memory, logic and analog integrated circuits. Founded in 1984, the Company serves the manufacturers of computation, communications and instrumentation equipment in commercial, industrial and military environments. Atmel's broad line of products provide customers with a variety of solutions to their memory and logic applications. Atmel offers high-density, high-speed memory and logic standard products as well as custom gate arrays. Atmel guarantees quality and reliability by fabricating all products- no matter what their intended application- to meet or exceed the specifications of Military Standard 883. Whether you are new to programmable logic or an experienced user, Atmel is committed to your success. If you have any questions or would like to place an order, please contact your local Atmel sales office as listed in the back of this data book, or contact Atmel's corporate headquarters. Atmel Corporation 2125 O'Nel Drive San Jose, CA 95131 PHONE: (408) 441-0311 FAX: (408) 436-4300 FAX-ON-DEMAND: U.S. (1-800) 29-ATMEL (292-8635) International (1-408) 441-0732 Atmel BBS: (408) 436-4309 We thank you for considering Atme! semiconductors. Overview _ _ _ _ _ _ _ _ _ _ _ _ _ _ Table of Contents Section 1 Microcontroller Product Information Product Selection Guide .................................................................................................. 1-3 Ordering Information ........................................................................................................ 1-5 Section 2 General Architecture Architectural Overview ..................................................................................................... 2-3 Memory Organization ....................................................................................................... 2-21 ATS9 Series Hardware Description .................................................................................. 2-39 Instruction Set .................................................................................................................. 2-71 Section 3 Microcontroller Data Sheets ATS9C1051 ............ S-bit 1K Low Voltage Flash Microcontroller in 20-pin package ......... 3-3 ATS9C2051 ............ S-bit 2K Low Voltage Flash Microcontroller in 20-pin package ......... 3-17 ATS9C51 ................ S-bit 4K Flash Microcontroller ........................................................... 3-33 ATS9LV51 .............. S-bit 4K Low Voltage Flash Microcontroller ...................................... 3-49 ATS9C52 ................ S-bit SK Flash Microcontroller ........................................................... 3-65 ATS9LV52 .............. S-bit SK Low Voltage Flash Microcontroller ...................................... 3-S7 ATS9SS252 ............ S-bit SK Downloadable Flash Microcontroller ................................... 3-109 Section 4 Microcontroller Application Notes Using a Personal Computer to Program the ATS9C51 IC52/L V51 IL V521C 1051 IC2051 .. 4-3 ATS9C51 In-Circuit Programming .................................................................................... 4-9 Controlling FPGA Configuration with a Flash-Based Microcontroller ............................... 4-21 Programming Atmel's Family of Flash Memories ............................................................. 4-29 Analog-to-Digital Conversion Utilizing the ATS9CX051 Microcontrollers ......................... 4-33 Interfacing AT24CXX Serial EEPROMS with ATS9CX051 Microcontrollers .................... 4-39 Interfacing AT93CXX Serial EEPROMS with ATS9CX051 Microcontrollers ............ :....... 4-41 Section 5 Programmer Support/Development Tools Microcontroller Programmer Support ............................................................................... 5-3 Microcontroller Third Party Tool Vendors ......................................................................... 5-9 ATS9 Series Development Tools Support ........................................................................ 5-17 ATABX051 ....................................................................................................................... 5-25 Section 6 Microcontroller Cross-Reference Microcontroller Cross-Reference Guide .......................................................................... 6-3 Section 7 Package Outlines Package Drawings ........................................................................................................... 7-3 Section 8 Miscellaneous Atmel Product Line Guide ................................................................................................ 8-3 Atmel Sales Offices .......................................................................................................... 8-9 Atmel North American Distributors ................................................................................... 8-11 Atmel North American Representatives ........................................................................... 8-17 Atmellnternational Representatives ................................................................................ 8-19 ii Microcontroller Product Information General Architecture Microcontroller Data Sheets Microcontroller Application Notes Programmer Support/Development Tools Microcontroller Cross-Reference Package Outlines Miscellaneous Information Contents Section 1 Microcontroller Product Information Product Selection Guide .................................................................................................. 1-3 Ordering Information ........................................................................................................ 1-5 1-1 1·2 Microcontroller Selection Guide Microcontroller Part Number ATB9C1051 ATB9C2051 ATB9C51 ATB9LV51 ATB9C52 ATB9LV52 ATB9SB252 Memory Size 1KxB 2KxB 4KxB 4KxB BKxB BKxB BKxB Description 2.7-Volt, B0C31 Microcontroller with 1 Kbyte Flash, 20-Pin Package 2.7-Volt, BOC31 Microcontroller with 2 Kbytes Flash, 20-Pin Package BOC31 Microcontroller with 4 Kbytes Flash 2.7-Volt, BOC31 Microcontroller with 4 Kbytes Flash BOC32 Microcontroller with B Kbytes Flash 2.7-Volt, BOC32 Microcontroller with B Kbytes Flash BOC32, Downloadable Microcontroller with B Kbytes Flash, 2K EEPROM Availability Now Now Now Now Now Now Now OSl1A 1-3 1-4 Microcontroller Selection Guide Ordering Information Explanation of Atmel's Part Number Code All Atmel part numbers begin with the prefix" AT". The next four to nine digits are the part number. In addition, Atmel parts can be ordered in particular speeds, in specific packages, for particular temperature ranges and with the option of 883~ level B military compliance. All Atmel Microcontrollers use 12 volt programming voltage if ordered as a standard part. However, the Atmel AT89C51 and AT89C52 can be special ordered as 5-volt programmable devices. If this option is desired the part must be ordered with a -5 at the end of the ordering code (AT89C5X-XXXX-5). The available options for each part are listed at the back of its data sheet in its "Ordering Information" table. These options are designated by the following suffixes placed at the end of the Atmel part number, in the order given: Prefix AT Ordering Information Device· Suffix 89CXXX x X xx Processing Blank = Standard = MIL-STD-883, Class B Fully Compliant 1883 Temperature Range C I A M = Commercial = Industrial = Automotive =Military Package D J L P S Q A W = Cerdip Plastic J-Lead Chip Carrier Leadless Chip Carrier Plastic DIP SOIC PQFP TQFP Die Speed 12 = 12MHz 16 = 16MHz 20 = 20MHz 24 24 MHz = 9 = FLASH Here is an example Atmel part number: Atmel Part Number Speed Package Type Temperature Range Processing 0512A 1-5 Product Index Part Number Description MCUs Pins Package VCC Speed Temperature Flash Page AT89C1051-12PC AT89C1051-12SC AT89C105H2PI AT89C1051-12SI AT89C1051-24PC AT89C1051-24SC AT89C1051-24PI AT89C1051-24SI AT89C2051-12PC AT89C2051-12SC AT89C2051-12PI AT89C2051-12SI AT89C2051-24PC AT89C2051-24SC AT89C2051-24PI AT89C2051-24SI AT89C51-12AC AT89CS1-12JC AT89C51-12PC AT89C51-12QC AT89CS1-12AI AT89C51-12JI AT89C51-12PI AT89C51-12QI AT89C51-12AA AT89C51-12JA AT89C51-12PA AT89C51-12QA AT89C51-12DM AT89C51-12LM AT89C51-12DM/883 AT89C51-12LM/883 AT89C51-16AC AT89C51-16JC AT89C51-16PC AT89C51-16QC AT89C51-16AI AT89C51-16JI AT89C51-16PI AT89C51-16QI AT89CS1-16AA AT89C51-16JA AT89C51-16PA AT89C51-16QA AT89C51-20AC AT89C51-20JC AT89C51-20PC AT89C51-20QC 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 44 44 40 44 44 44 40 44 44 44 40 44 40 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 PDIP SOIC PDIP SOIC PDIP SOIC PDIP SOIC PDIP SOIC PDIP SOIC PDIP SOIC PDIP SOIC TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP CERDIP LCC CERDIP LCC TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP 3V 3V 3V 3V 5V 5V 5V 5V 3V 3V 3V 3V SV 5V 5V 5V 5V 5V 5V 5V SV 5V SV 5V 5V SV 5V 5V SV 5V 5V 5V 5V 5V SV 5V SV 5V 5V 5V 5V SV 5V 5V 5V 5V 5V 5V 12 MHz 12 MHz 12 MHz 12 MHz 24 MHz 24 MHz 24 MHz 24 MHz 12 MHz 12 MHz 12 MHz 12 MHz 24 MHz 24 MHz 24 MHz 24 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz 20. MHz 20 MHz 20 MHz 20 MHz Commercial Commercial Industrial Industrial Commercial. Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Automotive Automotive Automotive Automotive Military Military Military Military Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Automotive Automotive Automotive Automotive Commercial Commercial Commercial 'Commercial .. lK 1K 1K 1K 1K 1K 1K 1K 2K 2K 2K 2K 2K 2K 2K 2K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 3-3 3-3 3-3 3-3 3-3 3-3 3-3 3-3 3-17 3-17 3-17 3-17 3-17 3-17 3-17 3-17 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 1·6 Ordering Information Ordering Information Product Index (continued) Part Number Description MCUs Pins Package VCC Speed Temperature Flash Page ATB9C51-20AI ATB9C51-20JI ATB9C51-20PI ATS9C51-2OQI ATS9C51-24AC ATS9C51-24JC ATS9C51-24PC ATS9C51-24QC ATS9C51-24AI ATS9C51-24JI ATS9C51-24PI ATS9C51-24QI ATS9LV51-12AC ATB9LV51-12JC ATS9LV51-12PC ATS9LV51-12QC ATS9C52-12AC ATS9C52-12JC ATB9C52-12PC ATS9C52-12QC ATS9C52-12AI ATS9C52-12JI ATS9C52-12PI ATS9C52-12QI ATS9C52-12AA ATB9C52-12JA ATB9C52-12PA AT89C52-12QA ATS9C52-12DM ATS9C52-12LM ATS9C52-12DM/SS3 ATS9C52-12LM/SS3 ATB9C52-16AC ATB9C52-16JC ATB9C52-16PC ATB9C52-16QC ATB9C52-16AI ATB9C52-16JI ATS9C52-16PI ATS9C52-16QI ATS9C52-16AA ATS9C52-16JA ATS9C52-16PA ATB9C52-16QA ATS9C52-20AC ATS9C52-20JC ATS9C52-20PC ATS9C52-20QC 44 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 40 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP CERDIP LCC CERDIP LCC TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 3V 3V 3V 3V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12MHz 12 MHz 12 MHz 12MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16MHz 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16MHz 20 MHz 20 MHz 20 MHz 20 MHz Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Automotive Automotive Automotive Automotive Military Military Military Military Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Automotive Automotive Automotive Automotive Commercial Commercial Commercial Commercial 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K SK SK SK SK SK SK SK SK SK SK SK SK SK SK SK BK BK BK BK BK BK BK BK SK BK SK BK BK SK BK BK BK 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-33 3-49 3-49 3-49 3-49 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 1-7 AlmEL Product Index (continued) Part Number Description MCUs Pins Package VCC Speed Temperature Flash ATB9C52-20AI ATB9C52-20JI ATB9C52-20PI ATB9C52-20QI ATB9C52-24AC ATB9C52-24JC ATB9C52-24PC ATB9C52-24QC ATB9C52-24AI ATB9C52-24JI ATB9C52-24PI ATB9C52-24QI ATB9LV52-12AC ATB9LV52-12JC ATB9LV52-12PC ATB9LV52-12QC ATB9SB252-12AC ATB9SB252-12JC ATB9SB252-12PC ATB9SB252-12QC ATB9SB252-12AI ATB9SB252-12JI ATB9SB252-12PI ATB9SB252-12QI ATB9SB252-24AC ATB9SB252-24JC ATB9SB252-24PC ATB9SB252-240C ATB9SB252-24AI ATB9SB252-24JI ATB9SB252-24PI ATB9SB252-24QI 44 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 44 44 40 44 TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TQFP PLCC PDIP PQFP TOFP PLCC PDIP PQFP TOFP PLCC PDIP PQFP 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 5V 5V 5V 5V 5V 5V 5V 5V 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 12 MHz 12 MHz 12MHz 12 MHz 12MHz 12 MHz 12MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK BK 1·8 Ordering Information Page 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-65 3-B7 3-B7 3-B7 3-B7 3-109 3-109 3-109 3-109 3-109 3-109 3-109 3-109 3-109 3-109 3-109 3-109 3-109 3-109 . 3-109 3-109 Microcontroller Product Information General Architecture Microcontroller Data Sheets Microcontroller Application Notes Programmer Support/Development Tools Microcontroller Cross-Reference Package Outlines Miscellaneous Information Contents Section 2 General Architecture Architectural Overview ..................................................................................................... 2-3 Memory Organization ....................................................................................................... 2-21 AT89 Series Hardware Description .................................................................................. 2-39 Instruction Set .................................................................................................................. 2-71 2-1 • 2-2 Architectural Overview Features • • • • • • • • • • • • 8-Bit CPU Optimized for Control Applications Extensive Boolean Processing Capabilities (Single-Bit Logic) On-Chip Flash Program Memory On-Chip Data RAM Bidirectional and Individually Addressable 110 Lines Multiple 16-Bit Timer/Counters Full Duplex UART Multiple SourceNector/Priority Interrupt Structure On-Chip Clock Oscillator On-Chip EEPROM (AT89S series) SPI Serial Bus Interface (AT89S Series) Watchdog Timer (AT89S Series) Flash Microcontroller Architectural Overview The basic architectural structure of this AT89C51 core is shown in Figure 1. Block Diagram Figure 1. Block Diagram of the AT89C core EXTERNAl INTERRUPTS ETC. ON-CHIP FLASH = = } COUNTER INPUTS TXD RXD PO P2 P1 P3 ~ ADDRESS/DIU"A For more information on the individual devices and features, refer to the Hardware Descriptions and Data Sheets of the specific device. 0497A 2-3 • Figure 2. Block Diagram of the AT89S core External Interrupts SPISeriai Interface Counter Inputs TXD ~ P2 RXD P3 Address/Data Figure 3. AT89C511LV51 and AT89C521LV52 Memory Structure PROGRAM MEMORY (READ ONLy) DATA MEMORY (READIWRITE) ----------------------------~ I FFFFH: , - - - - , FFFFH: EXTERNAL FFH: EA= 0 EXTERNAL EA= 1 INTERNAL 00'--_--' PSEN 2-4 Architectural Overview I I I I I Architectural Overview Reduced Power Modes Program Memory To exploit the power savings available in CMOS circuitry, Atmel's Flash microcontrollers have two software-invoked reduced power modes. • Idle Mode. The CPU is turned off while the RAM and other on-chip peripherals continue operating. In this mode, current draw is reduced to about 15 percent of the current drawn when the device is fully active. • Power Down Mode. All on-chip activities are suspended, while the on-chip RAM continues to hold its data. In this mode, the device typically draws less than 15 ~, and can be as low as 0.6 fLA. In addition, these devices are designed using static logic, which does not require continuous clocking. That is, the clock frequency can be slowed or even stopped while waiting for an internal event. Figure 4 shows a map of the lower part of the program memory. After reset, the CPU begins execution from location OOOOH. As shown in Figure 4, each interrupt is assigned a fixed location in program memory. The interrupt causes the CPU to jump to that location, where it executes the service routine. External Interrupt 0, for example, is assigned to location 0003H. If External Interrupt 0 is used, its service routine must begin at location 0OO3H. If the interrupt is not used, its service location is available as general purpose program memory. Figure 4. Program Memory (OO33H) Memory Organization Timer 2 Logical Separation of Program and Data Memory Timer 1 All Atrnel Flash microcontrollers have separate address spaces for program and data memory, as shown in Figure 3. The logical separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which can be more quickly stored and manipulated by an 8-bit CPU. Nevertheless, I6-bit data memory addresses can also be generated through the DPTR register. Program memory can only be read. There can be up to 64K bytes of directly addressable program memory. The read strobe for external program memory is the Program Store Enable signal (PSEN). Data memory occupies a separate address space from program memory. Up to 64K bytes of external memory can be directly addressed in the external data memory space. The CPU generates read and write signals, RD and WR, during external data memory accesses. External program memory and external data memory can be combined by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external program/data memory. 002BH SeriaJPort 0023H INTERRUPT 001BH LOCATIONS ExIemallnterrupt 1 0013H Timer 0 OOOBH Extemallnterrupt 0 L...._--I =:I 8 BYTES 0003H OOOOH The interrupt service locations are spaced at 8-byte intervals: 0003H for External Interrupt 0, OOOBH for Timer 0, 0013H for External Interrupt 1, OOIBH for Timer 1, and so on. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a jump instruction to skip over subsequent interruptlocations, if other interrupts are in use. The lowest addresses of program memory can be either in the on-chip Flash or in an external memory. To make this selection, strap the External Access (EA )pin to either Vee or GND. For example, in the AT89C51 with 4K bytes of on-chip Flash, if the EA pin is strapped to Vee, program fetches to addresses OOOOH through OFFFH are directed to the internal Flash. Program fetches to addresses l000H through FFFFH are directed to external memory. In the AT89C52 (8K bytes Flash), EA =Vee selects addresses OOOOH through IFFFH to be internal and addresses 2000H through FFFFH to be external. If the EA pin is strapped to GND, all program fetches are directed to external memory. The read strobe to external memory, PSEN, is used for all external program fetches. Internal program fetches do not activate PSEN. The hardware configuration for external program execution is shown in Figure 5. Note that 16 I/O lines (Ports 0 and 2) are 2-5 • Figure S. Executing from External Program Memory ATB9 EXTERNAL PROGRAM MEMORY PO II'-~------~ INSTR. You can assign up to 64Kbytes of external data memory. External data memory addresses can be either I or 2 bytes wide. Onebyte addresses are often used in conjunction with one or more other I/O lines to page the RAM, as shown in Figure 6. Two~ byte addresses can also be used, in which case tJie high address byte is emitted at Port 2. Figure 7. Internal Data Memory FFH P2 1-_ _ _ _LA_:rC_H _ _ _"'} '00, UPPER 128 PSEN 1 - - - - - - - - - - ,.. OE ~~ '------' dedicated to bus functions during external program memory fetches. Port 0 (PO in Figure 5) serves as a multiplexed address/data bus. It emits the 19W byte of the Program Counter (PCL) as an address and then goes into a float state while waiting for the arrival of the code. byte from the program memory. During the time that the low byte of the Program Counter is valid on PO, the signal ALE (Address Latch Enable) clocks this byte into an address latch. Meanwhile, Port 2 (P2 in Figure 5) emits the high byte of the Program Counter (PCH). Then PSEN strobes the external memory, and the microcontroller reads the code byte. Program memory addresses are always 16 bits wide, even though the actual amount of program memory used may be less than 64K bytes. External program execution sacrifices two of the 8-bit ports, PO and P2, to the function of addressing the program memory. Data Memory The right half of Figure 3 shows the internal and external data memory spaces available on Atrnel's Flash microcontrollers. ~----------..------~ ,, , ,,' ACCESSIBLE BY INDIRECT ADDRESSING ONLY 1------+-..-------' ACCESSIBLE BY DIRECT AND INDIRECT ADDRESSING LOWER 128 J-_ STATUS PORTS AND CONTROL BITS -TIMERS -REGISTERS - STACK POINTER _ ACCUMULATOR _(ETC.) Figure 8. The Lower 128 Bytes of Internal RAM 7FH 2FH BANK 20H 11{ 10{ 01 { MEMORY K:=:::;~=====~ DATA 00 { I BIT-ADDRESSABLE SPACE (B IT ADDRESSES 0·7F) SELECT~ EXTERNAL DATA 2·6 SPECIAL FUNCTION REGISTERS Internal data memory addresses are always 1 byte wide, which implies an address space of only 256 bytes. However, the addressing modes for internal RAM can in fact accommodate 384 bytes. Direct addresses higher than 7FH access one memory space, and indirect addresses higher than 7FH access a different memory space. Thus, Figure 7 shows the Upper 128 and SFR space occupying the same block of addresses, 80H through FFH, alth~lUgh they are physically separate entities. Figure 6. Accessing external data memory. If the program memory is internal, the other bits of P2 are available as I/O. OE . BOH Internal data memory is shown in Figure 7. The memory space is divided into three blocks, which are generally referred to as the Lower 128, the Upper 128, and SFR space. BITS IN PSW We ~ 01.-_ _ _ _.-1 Figure 6 shows a hardware configuration for accessing up to 2K bytes of external RAM. In this case, the CPU executes from internal Flash. Port 0 serves as a multiplexed address/data bus to the RAM, and 3 lines of Port 2 are used to page the RAM. The CPU generates RD and WR signals as needed during external RAM accesses. FWJE.Ji BITS FFH ACCESSIBLE BY DIRECT ADDRESSING 1FH 1BH 17H 4 BANKS OF lOH 8 REGISTERS RO-R7 OFH OBH 07H 0 - RESET VALUE OF STACK POINTER Figure 8 shows how the lower 128 bytes of RAM are mapped. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as RO through R7. Two bits in the Program Status Word (PSW) select which register bank is in use. This architecture allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing. Architectural Overview Architectural Overview The next 16 bytes above the register banks form a block of bitaddressable memory space. The microcontroller instruction set includes a wide selection of single-bit instructions, and these instructions can directly address the 128 bits in this area. These bit addresses are OOH through 7FH. All ofthe bytes in the Lower 128 can be accessed by either direct or indirect addressing. The Upper 128 (Figure 8) can only be accessed by indirect addressing. The Upper 128 bytes of RAM are only in the devices with 256 bytes of RAM. Figure 10 gives a brief look at the Special Function Register (SFR) space. SFRs include Port latches, timers, peripheral controls, etc. These registers can only be accessed by direct addressing. In general, all Atmel microcontrollers have the same SFRs at the same addresses in SFR space as the AT89C51 and other compatible microcontrollers. However, upgrades to the AT89C51 have additional SFRs. Sixteen addresses in SFR space are both byte- and bit-addressable. The bit-addressable SFRs are those whose address ends in OOOB. The bit addresses in this area are 80H through FFH. Figure 9. The Upper 128 Bytes of Internal RAM 8yte address 8itaddress 7F Figure 10. SFR Space 8yte address 8itaddress FF FO F71 F61 F51 F4/ F31F2/ F1/ FO 8 EO E7 E6 E5 E4 E3 E2 E1 EO ACC 00 07 06 05 04 0302 PSW 00 88 8C B8 BA 89 B8 IP 80 B7 B6 85 B4 B3 B2 B1 BO P3 A8 AF/- /-/AC/A8IAA/A9/A8 IE AO A71A6 LA5LA4jA3jA2jA11AO P2 99 98 not bH addressable 9F 9E 90 9C 98 9A 99 98 S8UF SCON 90 97 98 95 94 93 92 91 90 P1 80 8C 88 8A 89 88 87 not bit addressable not bit addressable not .t aaaressab e not bH addressable not bit addressable 8F/8E /sOL8CL8818A189188 not bit addressable THI THO TL1 TLO TMOO TCON PCON 83 82 81 80 not bit addressable not bit addressable not bit addressable 87 86 85 84 83 82 81 80 OPH OPL SP PO • Special Function Registers General purpose RAM 30 2F 2E 20 2C 28 2A 29 28 27 26 25 24 23 22 21 20 1F 18 17 10 OF 08 07 00 7F 7E 77 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 OE 06 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 OF 07 70 75 60 65 50 55 40 45 30 35 20 25 10 15 00 05 7C 74 6C 64 5C 54 4C 44 3C 78 73 68 63 58 53 48 43 38 34 33 2C 24 1C 14 OC 04 28 23 18 13 08 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 OA 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 8ank3 8ank2 8ank 1 Oelault register bank lor RO-R7 RAM 2·7 Figure 11. PSW (Program Status Word) Register in Atrnel Flash Microcontrollers PSW 7 CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ALU OPERANDS PSW 0 PARITY OF ACCUMULATOR SET BY HARDWARE TO 1 IF IT CONTAINS AN ODD NUMBER OF ls, OTHERWISE IT IS RESET TO 0 PSW 6 AUXILIARY CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERANDS PSW 1 USER DEFINABLE FLAG PSW 5 - - - - - - ' GENERAL PURPOSE STATUS FLAG PSW2 OVERFLOW FLAG SET BY ARITHMETIC OPERATIONS PSW 4 _ _ _ _ _---' REGISTER BANK SELECT BIT 1 PSW3 REGISTER BANK SELECT BIT 0 The Instruction Set Addressing Modes All members of the Atrnel microcontroller family execute the same instruction set. This instruction set is optimized for 8-bit control applications and it provides a variety of fast addressing modes for accessing the internal RAM to facilitate byte operations on small data structures. The instruction set provides extensive support for I-bit variables as a separate data type, allowing direct bit manipulation in control and logic systems that require Boolean processing. The addressing modes in the Flash microcontroller instruction set are as follows. The following overview of the instruction set gives a brief description of how certain instructions can be used. Program Status Word Direct Addressing In direct addressing, the operand is specified by an 8-bit address field in the instruction. Only internal data RAM and SFRs can be directly addressed. Indirect Addressing In indirect addressing, the instruction specifies a register that contains the address of the operand. Both internal and external RAM can be indirectly addressed. The Program Status Word (PSW) contains status bits that reflect the current state of the CPU. The PSW, shown in Figure !1, resides in SFR space. The PSW contains the Carry bit, the Auxiliary Carry (for BCD operations), the two-register bank select bits, the Overflow flag, a Parity bit, and two user-definable status flags. The address register for 8-bit addresses can be either the Stack Pointer or RO or R 1 of t,he selected register bank. The address register for 16-bit addresses can be only the 16-bit data pointer register, DPTR. The Carry bit, in addition to serving as a Carry bit in arithmetic operations, also serves as the "Accumulator" for a number of Boolean operations. The register banks, which contain registers RO through R7, can be accessed by instructions whose opcodes carry a 3-bit register specification. Instructions that access the registers this way make efficient use of code, since this mode eliminates an address byte. When the instruction is executed, one of the eight registers in the selected bank is accessed. One of four banks is selected at execution time by the two bank select bits in the PSW. The bits RSO and RS I select one of the four register banks shown in Figure 8. A number of instructions refer to these RAM locations as RO through R7. The status of the RSO and RSI bits at execution time determines which of the four banks is selected. The Parity bit reflects the number of Is in the Accumulator: P = I if the Accumulator contains an odd number of Is, and P =0 if the Accumulator contains an even number of Is. Thus, the number of Is in the Accumulator plus P is always even. Two bits in the PSW are uncommitted and can be used as general purpose status flags. 2-8 Register Instructions Register-Specific Instructions Some instructions are specific to a certain register. For example, some instructions always operate on the Accumulator, so no address byte is needed to point to it. In these cases, the opcode itself points to the correct register. Instructions that refer to the Accumulator as A assemble as Accumulator-specific opcodes. Architectural Overview Architectural Overview Immediate Constants The value of a constant can follow the opcode in program memory. For example, MOVA,#IOO loads the Accumulator with the decimal number 100. The same number could be specified in hex digits as 64H. Indexed Addressing Program memory can only be accessed via indexed addressing. This addressing mode is intended for reading look-up tables in program memory. A 16-bit base register (either DPTR or the Program Counter) points to the base of the table, and the Accumulator is set up with the table entry number. The address of the table entry in program memory is formed by adding the Accumulator data to the base pointer. Another type of indexed addressing is used in the "case jump" instruction. In this case the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data. Arithmetic Instructions The menu of arithmetic instructions is listed in Table I. The table indicates the addressing modes that can be used with each instruction to access theoperand. For example, the ADD A, instruction can be written as follows. ADD ADD ADD ADD A,7FH A,@RO A,R7 A, #127 (direct addressing) (indirect addressing) (register addressing) (immediate constant) The execution times listed in Table 1 assume a 12 MHz clock frequency. All of the arithmetic instructions execute in 1 Ils except the INC DPTR instruction, which takes 2 Ils, and the Multiply and Divide instructions, which take 4 Ils. Note that any byte in the internal data memory space can be incremented or decremented without using the Accumulator. The INC DPTR instruction operates on the 16-bit Data Pointer. The Data Pointer generates 16-bit addresses for external memory, so the ability to be incremented in one 16-bit operation is a useful feature. The MUL AB instruction multiplies the Accumulator by the data in the B register and puts the 16-bit product into the concatenated B and Accumulator registers. The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8-bit quotient in the Accumulator and the 8-bit remainder in the B register. Note: DIY AB is less useful in arithmetic "divide" routines than in radix conversions and programmable shift operations. In shift operations, dividing a number by 2n shifts its n bits to the right. Using DIY AB to perform the division completes the shift in 41ls and leaves the B register holding the bits that were shifted out. The DA A instruction is for BCD arithmetic operations. In BCD arithmetic, ADD and ADDC instructions should always be followed by a DA A operation, to ensure that the result is also in BCD. Note that DA A will not convert a binary number to BCD. The DA A operation produces a meaningful result only as the second step in the addition of two BCD bytes. Table 1. A List of Atrnel Microcontroller Arithmetic Instructions Addressing Modes Dir Ind Reg Imm Execution Time (Ils) A = A + X X X X 1 ADDCA, A = A + + e X X X X 1 SUBBA, A = A - - e X X X X 1 Mnemonic ADD A, Operation INC A A=A+1 INC = + 1 INC DPTR Accumulator only X X X DPTR = DPTR + 1 Data Pointer only DEC A A=A-1 Accumulator only DEC = - 1 X X X 1 1 2 1 1 MUL AB B:A=BxA ACC and B only 4 DIV AB A= Int [AlB] B= Mod [AlB) ACe and B only 4 DA A Decimal Adjust Accumulator only 1 2-9 Table 2. Logical Instructions Mnemonic ANL Addressing Modes Operation A, A = A .AND. Dir Ind Reg Imm Execution Time (I1S) X X X X 1 ANL ,A = .AND. A X 1 ANL , #data = .AND. #data X 2 ORL A, A = A .OR. X ORL ,A = .OR. A X 1 ORL • #data = .OR. #data X 2 XRL A, A = A .XOR. X XRL ,A = .XOR. A X XRL , #data = .XOR. #data X X X X X X X 1 1 1 2 CRL A A=OOH Accumulator only 1 CPL A A= .NOT. A Accumulator only 1 RL Rotate ACC Left 1 bit Accumulator only 1 RLC A Rotate Left through Carry Accumulator only 1 RR Rotate ACC Right 1 bit Accumulator only 1 Rotate Right through Carry Accumulator only 1 Swap Nibbles in A Accumulator only 1 A A RRC A SWAPA Logical Instructions Table 2 shows the Atme! Flash microcontroller logical instructions. The instructions that perform Boolean operations (AND, OR, Exclusive OR, NOT) on bytes operate on a bit-by-bit basis. That is, if the Accumulator contains OOIIOIOlB and contains OlOIOOIIB, then ANL A, leaves the Accumulator holding 00010001B. The Rotate instructions (RL A, RLC A, etc.) shift the Accumulator 1 bit to the left or right. For a left rotation, the MSB rolls into the LSB position. For a right rotation, the Least Significant Bit (LSB) rolls into the Most Significant Bit (MSB) position. The SWAP A instruction interchanges the high and low nibbles within the Accumulator. This exchange is useful in BCD manipulations. For example, if the Accumulator contains a binary number that is known to be less than 100, the following code can quickly convert it to BCD. Table 2 also lists the addressing modes that can be used to access the operand. Thus, the ANL A, instruction may take any of the following forms. ANL ANL ANL ANL A,7FH A,@Rl A,R6 A, # 53H (direct addressing) (indirect addressing) (register addressing) (immediate constant) All of the logical instructions that are Accumulator-specific execute in I I1s (using a 12 MHz clock). The others take 211s. Note that Boolean operations can be performed on any byte in the lower 128 internal data memory space or the SFR space using direct addressing, without using the Accumulator. The XRL , #data instruction, for example, offers a quick and easy way to invert port bits, as in the following example. XRL PI,#OFFH If the operation is in response to an interrupt, not using the Accumulator saves the time required to stack it in the service routine. 2-10 MOV DIV SWAP ADD B,# 10 AB A A,B Dividing the number by 10 leaves the tens digit in the low nibble of the Accumulator, and the ones digit in the B register. The Data Transfers Internal Ram Table 3 shows the menu of instructions and associated addressing modes that are available for moving data within the internal memory spaces. With a 12 MHz clock, all of these instructions execute in either 1 or 2 I1s. The MOV , instruction allows data to be transferred between any two internal RAM or SFR locations without going through the Accumulator. Architectural Overview Architectural Overview Table 3. Data Transfer Instructions that Access Internal Data Memory Space Mnemonic Addressing Modes Operation MOV A, A= Execution Dir Ind Reg Imm Time(~s) X X X X 1 X 2 X 2 MOV ,A =A X X X MOV , = X X X 1 MOV DPTR, #data16 DPTR = 16-bit immediate constant. PUSH INC SP: MOV "@SP", X 2 POP MOV , "@SP"; DEC SP X 2 XCH A, ACC and exchange data X XCHDA,@Ri ACC and @Ri exchange low nibbles Note that in all Atmel Flash microcontroller devices, the stack resides in on-chip RAM and grows upwards. The PUSH instruction first increments the Stack Pointer (SP), then copies the byte into the stack. PUSH and POP use only direct addressing to identify the byte being saved or restored, but the stack itself is accessed by indirect addressing using the SP register. This means the stack can go into the Upper 128, if they are implemented, but not into SFR space. In devices that do not implement the Upper 128, if the SP points to the Upper 128, PUSHed bytes are lost, and POPped bytes are indeterminate. The Data Transfer instructions include a 16-bit MOV that can initialize the Data Pointer (DPTR) for look-up tables in program memory or for l6-bit external data memory accesses. The XCH A, instruction exchanges the data in the Accumulator and the addressed byte. The XCHD A,@Ri instruction is similar, but only the low nibbles are exchanged. Figure 12. Shifting a BCD Number Two Digits to the Right 2A 28 2C 2D 2E ACC MOV A,2EH 00 12 34 56 78 MOV 2EH,2DH 00 12 34 56 56 56 MOV 2DH,2CH 00 12 34 34 MOV 2CH,2BH 00 12 12 34 56 MOV 2BH,#0 00 00 12 34 56 78 78 78 78 78 X X X 1 1 To see how XCH and XCHD can facilitate data manipulations, consider the problem of shifting an 8-digit BCD number two digits to the right. Figure 12 compares how direct MOVs and XCH instructions can do this operation. The contents of the registers that hold the BCD number and the content of the Accumulator are shown along side each instruction to indicate their status after the instruction executes. After the routine executes, the Accumulator contains the two digits that were shifted to the right. Using direct MOVs requires 14 code bytes and 9~s of execution time (under a 12 MHz clock). Using XCHs for the same operation requires less code and executes almost twice as fast. To right-shift by an odd number of digits, a one-digit shift must be executed. Figure \3 shows a sample of code that right-shifts a BCD number one digit, using the XCHD instruction. In this example, pointers R I and RO point to the two bytes containing the last four BCD digits. Then a loop leaves the last byte, location 2EH, holding the last two digits of the shifted number. The pointers are decremented, and the loop is repeated for location2DH. Note: The CJNE instruction (Compare and Jump if Not Equal) is a loop control that will be described later. The loop is executed from LOOP to CJNE for RI =2EH, 2DH, 2CH and 2BH. At that point, the digit that was originally shifted out on the right has propagated to location 2AH. Since that location should be left with Os, the lost digit is moved to the Accumulator. (a) Using direct MOVs: 14 bytes, 9 ~s 2A 2B 2C 2D 2E ACC 78 78 00 34 78 CLR A 00 12 34 56 XCH A,2BH 00 00 34 56 XCH A,2CH 00 00 12 56 XCH A,2DH 00 00 12 34 78 78 XCH A,2EH 00 00 12 34 56 12 56 (b) Using XCHs: 9 bytes, 5 ~s 2·11 Figure 13. Shifting a BCD Number One Digit to the Right 2A 2B 2C 20 2E ACC MOVR1,#2EH 00 12 34 56 78 XX MOVRO,#2DH 00 12 34 56 78 XX 00 12 34 56 78 78 loop for R1 XCHDA,@RO 00 12 34 58 78 76 SWAP A 00 12 34 58 78 67 MOV@R1,A 00 12 34 58 67 67 DECR1 00 12 34 58 67 67 DECRO 00 12 34 58 67 67 00 12 38 45 67 45 00 18 23 45 67 23 08 01 23 45 67 01 CJNE R1,#2AH,LOOP loop for R1 loop for R1 =2DH: =2CH: =2BH: CLRA XCHA,2AH I 08 1 01 1231451671 00 00 01 23 45 67 08 External Ram Table 4 lists the Data Transfer instructions that access external data memory. Only indirect addressing can be ,used. Either a one-byte address, @Ri, where Ri can be either RO or Rl of the selected register bank, or a two-byte address, @DPTR, can be used. The disadvantage of using 16-bit addresses when only a few Kbytes of external RAM are involved i~ that 16-bit addresses use all 8 bits of Port 2 as address bus. On the other hand, 8-bit addresses allow a few Kbytes of RAM to be used without sacrificing all of Port 2, as shown in Figure 6. All of these instructions execute in 211s with a 12 MHz clock. Table 4. Data Transfer Instructions that Access External Data Memory Address Width Mnemonic Operation Execution Time (I1S) 8 bits MOVXA,@Ri Read external RAM@Ri 2 8 bits MOVX@Ri,A Write external RAM @Ri 2 16 bits MOVXA, @DPTR Read external RAM @DPTR 2 MOVX @DPTR,A Write external RAM @DPTR 16 bits 2-12 Mnemonic =2EH: LOOP:MOVA,@R1 loop for R1 Table 5. Lookup Table Read Instructions Operation Execution Time (I1S) MOVC A,@A + DPTR Read Pgm Memory at (A+DPTR) 2 MOVCA,@A+PC Read Pgm Memory at (A+PC) 2 Note that in all external Data RAM accesses, the Accumulator is always either the destination or source of the data. The read and write strobes to external RAM are activated only during the execution of a MOVX instruction. Normally these signals are inactive, and if they are not going to be used at all, their pins are available as extra 110 lines. Lookup Tables Table 5 shows the two instructions that are available for reading lookup tables in program memory. Since these instructions access only program memory, the lookup tables can only be read, not updated. The mnemonic for "move constant" is MOVC. If the table access is to external program memory, then the read strobe is PSEN. The first MOVC instruction in Table 5 can accommodate a table of up to 256 entries, numbered 0 through 255. The number ofthe desired entry is loaded into the Accumulator, and the Data Pointer is set up to point to beginning of the table. Then the following instruction copies the desired table entry into the Accumulator. MOVCA,@A+DPTR The other MOVC instruction works the same way, except the Program Counter (PC) is the table base, and the table is accessed through a subroutine. First, the number of the desired entry is loaded into the Accumulator, and the following subroutine is called. MOVA,ENTRY_NUMBER CALL TABLE The subroutine TABLE would look like the following example. MOVCA,@A+PC TABLE: RET The table itself immediately follows the RET (return) instruction in program memory. This type of table can have up to 255 entries, numbered 1 through 255. Number 0 can not be used, because at the time the MOVC instruction is executed, the PC contains the address of the RET instruction. An entry numbered owould be the RET opcode itself. 2 Architectural Overview Architectural Overview Boolean Instructions Atmel's Flash microcontrollers contain a complete Boolean (single-bit) processor. The internal RAM contains 128 addressable bits, and the SFR space can support up to 128 other addressable bits. All of the port lines are bit-addressable, and each one can be treated as a separate single-bit port. The instructions that access these bits are not just conditional branches, but a complete menu of move, set, clear, complement, OR, and AND instructions. These kinds of bit operations are not easily obtained in other architectures with any amount of byte-oriented software. Table 6. Boolean Instructions Mnemonic Operation Execution Time (ILS) ANL C,bi! C = C .AND. bit ANL C,/bit C = C .AND .. NOT.bit 2 ORL C,bi! C=C .OR. bit 2 ORL C,/bit C = C .OR. .NOT. bit 2 MOV C,bit C=bit 1 MOV bit,C bit=C 2 CLR C C=O 1 CLR bit bit=O 1 SETBC C= 1 1 SETB bit bit = 1 1 CPL C C=.NOT. C 1 2 CPL bit bit = .NOT. bit 1 rei Jump if C = 1 2 JC JNC rei Jump if C= 0 2 JB bit,rel Jump if bit = 1 2 JNB bit, rei Jump if bit = 0 2 JBC bit,rel Jump if bit = 1; CLR bit 2 The instruction set for the Boolean processor is shown in Table 6. All bit accesses are by direct addressing. Bit addresses DOH through 7FH are in the Lower 128, and bit addresses 80H through FFH are in SFR space. The following example shows how easily an internal flag can be moved to a port pin. MOV C,FLAG MOV Pl.O,C In this example, FLAG is the name of any addressable bit in the Lower 128 or SFR space. An 110 line (the LSB of Port I, in this case) is set or cleared depending on whether the flag bit is 1 or The Boolean instruction set includes ANL and ORL, but not the XRL (Exclusive OR) operation. Implementing XRL in software is simple. Suppose, for example, that an application requires the Exclusive OR of two bits. C =bit! XRL. bit2 The software to do this operation could be as follows. MOVC,bit! JNB bit2,OVER CPLC OVER (continue) First, bit! is moved to the Carry. If bit2 =0, then C now contains the correct result. That is, bitl XRL. bit2 = bill if bit2 =o. On the other hand, if bit2 = I, C now contains the complement of the correct result. C CARRY need only be inverted (CPL C) to complete the operation. This code uses the JNB instruction, one of a series of bit-test instructions which execute a jump if the addressed bit is set (JC, JB, JBC) or if the addressed bit is not set (JNC, JNB). In the above case, bit2 is being tested, and if bit2 = 0, the CPL C instruction is jumped over. If the addressed bit is set, JBC executes the jump and also clears the bit. Thus, a flag can be tested and cleared in one operation. All the PSW bits are directly addressable, so the Parity bit, or the general purpose flags, for example, are also available to the bittest instructions. Relative Offset The destination address for these jumps is specified to the assembler by a label or by an actual address in program memory. However, the destination address assembles to a relative offset byte. This is a signed (two's complement) offset byte that is added to the PC in two's complement arithmetic if the jump is executed. The range of the jump is therefore -128 to +127 program memory bytes relative to the first byte following the instruction. Jump Instructions Table 7 shows the list of unconditional jumps. Table 7. Unconditional Jumps in Flash Microcontrollers Mnemonic Operation E~ecu~~) Time s Jump to addr 2 Jump to A+DPTR 2 CALL addr Call subroutine at addr 2 RET Return from subroutine 2 JMP addr JMP @A+DPTR O. RETI Return from interrupt 2 The Carry bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit instructions that refer to the Carry bit as C assemble as Carry-specific instructions (CLR C, etc). The Carry bit also has a direct address, since it resides in the PSW register, which is bit-addressable. Nap No operation 1 2·13 Table 8. Conditional Jumps in Flash Microcontrollers Mnemonic Addressing Modes Operation Dir Ind Reg Imm Execution Time(J.Ls) JZ rei Jump if A= 0 Accumulator only 2 JNZ rei Jump if A¢O Accumulator only 2 DJNZ , rei Decrement and jump if not zero X CJNE A, ,rei Jump if A ¢ X CJNE ,#data,rel Jump if ¢ #data Table 7 lists a single IMP addr instruction, but in fact there are three--SJMP, LIMP and AIMP-which differ in the format of the destination address. IMP is a generic mnemonic that can be used if the programmer does not care which way the jump is encoded. The SIMP instruction encodes the destination address as a relative offset, as described above. The instruction is 2 bytes long, consisting of the opcode and the relative offset byte. The jump distance is limited to a range of -128 to + 127 bytes, relative to the instruction following the SIMP. The UMP instruction encodes the destination address as a 16bit constant. The instruction is 3 bytes long, consisting of the opcode and two address bytes. The destination address can be anywhere in the 64K program memory space. The AJMP instruction encodes the destination address as an 11bit constant. The instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the II address bits, followed by another byte containing the low 8 bits of the destination address. When the instruction is executed, these II bits are simply substituted for the low II bits in the PC. The high 5 bits stay the same. Hence, the destination has to be within the same 2K block as the instruction following the AIMP. In all cases, the programmer specifies the destination address to the assembler the same way: as a label or as a 16-bit constant. The assembler puts the destination address into the correct format for the given instruction. If the format required by the instruction does not support the distance to the specified destination address, a "Destination out of range" message is written into the List file. The IMP @A+DPTR instruction supports case jumps. The destination address is computed at execution time as the sum of the 16-bit DPTR register and the Accumulator. Typically, DPTR is set up with the address of a jump table, and the Accumulator is given an index to the table. In a 5-way branch, for example, an integer 0 through 4 is loaded into the Accumulator. The code to be executed might be as follows. MOV MOV RL IMP 2-14 DPTR,#JUMP_TABLE A,INDEX_NUMBER A @A+DPTR X 2 X X X 2 2 The RL A instruction converts the index number (0 through 4) to an even number in the range 0 through 8, because each entry in the jump table is 2 bytes long, as shown in the following example. JUMP_TABLE: CASE_O AIMP CASE_I AJMP AIMP CASE_2 CASE_3 AIMP CASE_4 AIMP Table 8 shows a single CALL addr instruction, but there are two CALL instructions-LCALL and ACALL-which differ in the format in which the subroutine address is given to the CPU. CALL is a generic mnemonic that can be used if the programmer does not care which way the address is encoded. The LCALL instruction uses the 16-bit address format, and the subroutine can be anywhere in the 64K program memory space. The ACALL instruction uses the II-bit format, and the subroutine must be in the same 2K block as the instruction following the ACALL. In any case, the programmer specifies the subroutine address to the assembler the same way: asa label or as a 16-bit constant. The assembler puts the address into the correct format for the given instructions. Subroutines should end with a RET instruction, which returns execution to the instruction following the CALL. RETI is used to return from an interrupt service routine. The only difference between RET and RETI is that RETI tells the interrupt control system that the interrupt in progress is finished. If no interrupt is in progress at the time RETI is executed, then the RETI is functionally identical to RET. Table 8 shows the list of conditional jumps available. All of these jumps specify the destination address by the relative offset method and so are limited to a jump distance of -128 to +127 bytes from the instruction following the conditional jump instruction. However, the user specifies to the assembler the actual destination address the same way as the other jumps: as a label or a 16-bit constant. There is no 0 bit in the PSW. The JZ and JNZ instructions test the Accumulator data for that condition. Architectural Overview Architectural Overview The DJNZ instruction (Decrement and Jump if Not Zero) is for loop control. To execute a loop N times, load a counter byte with N and terminate the loop with a DJNZ to the beginning of the loop, as shown below for N = 10. MOV COUNTER,#IO LOOP: (begin loop) Figure ISa. Oscillator Connections C2 XTAL2 o * * * Cl XTALI (end loop) COUNTER,LOOP DJNZ (continue) The CJNE instruction (Compare and Jump if Not Equal) can also be used for loop control, as shown in Figure 13. Two bytes are specified in the operand field of the instruction. The jump is executed only if the two bytes are not equal. In the example of Figure 13, the two bytes were the data in RI and the constant 2AH. The initial data in RI was 2EH. Every time the loop was executed, R I was decremented, and the looping continued until the RI data reached 2AH. Another application of this instruction is in "greater than, less than" comparisons. The two bytes in the operand field are taken as unsigned integers. If the first is less than the second, then the Carry bit is set (I). If the first is greater than or equal to the second, then the Carry bit is cleared. GND Figure ISb. External Clock Drive Configuration NC EXTERNAL OSCILLATOR SIGNAL XTAL2 ----I XTALI GND CPU Timing All Atmel Flash microcontrollers have an on-chip oscillator, which can be used as the clock source for the CPU. To use the on-chip oscillator, connect a crystal or ceramic resonator between the XTALI and XTAL2 pins of the microcontroller, and connect the capacitors to ground as shown in Figure 14. Examples of how to drive the clock with an external oscillator are shown in Figure 15b. The internal clock generator defines the sequence of states that make up the microcontroller machine cycle. Figure 14. Using the On-Chip Oscillator FlASH MICROCONTROlLEA r-'......-~XTAL2 L...,....--t--tXTALI GND Machine Cycles A machine cycle consists of a sequence of 6 states, numbered S I through S6. Each state time lasts for two oscillator periods. Thus, a machine cycle lasts 12 oscillator periods or I J.ls if the oscillator frequency is 12 MHz. Each state is divided into a Phase I half and a Phase 2 half. Figure 16 shows the fetch/execute sequences in states and phases for various kinds of instructions. Normally two program fetches are generated during each machine cycle, even if the instruction being executed does not require it. If the instruction being executed does not need more code bytes, the CPU ignores the extra fetch, and the Program Counter is not incremented. Execution of a one-cycle instruction (Figure 16A and B) begins during State 1 of the machine cycle, when the opcode is latched into the Instruction Register. A second fetch occurs during S4 of the same machine cycle. Execution is complete at the end of State 6 of this machine cycle. The MOVX instructions take two machine cycles to execute. No program fetch is generated during the second cycle of a MOVX 2-15 instruction. This is the only time program fetches are skipped. The fetch/execute sequence for MOVX instructions is shown in Figure 16(D). If an access to external data memory occurs, as shown in Figure The fetch/execute sequences are the same whether the program memory is internal or external to the chip. Execution times do not depend on whether the program memory is internal or external. A data memory bus cycle takes twice as much time as a program memory bus cycle. Figure 17 shows the relative timing of the addresses being emitted at Ports 0 and 2 and of ALE and PSEN. ALE latches the low address byte from PO into the address latch. Figure 17 shows the signals and timing involved in program fetches when the program memory is external. If program memory is external, the program memory read strobe PSEN is normally activated twice per machine cycle, as shown in Figure 17(A). When the CPU is executing from internal program memory, PSEN is not activated, and program addresses are not emitted. However, ALE continues to be activated twice per machine cycle and is therefore available as a clock output signal. Note, however, that one ALE is skipped during the execution of the MOVX instruction. 17(B), two PSENs are skipped, because the address and data bus are being used for the data memory access. Figure 16. State Sequences in Atrnel Flash Microcontrollers OSC. (XTAL2) I ~I~I~IMI~I~I~I~I~IMI~I~I~I ~~~~~~~~~~~~~~~~~~~~~~~~~~ I ALE l<-_-+.....JIl<-__.....J1l n : 1lL-----T----Ir- I I I READ NEXT I OPCODE : (DISCARD) I £ READ NEXT OPCODE AGAIN ~~--~~~~~~~ I I (A) 1-byte, 1-cycle Instruction, e.g., INC A : READ OPCODE I : I I £ +:--,,---,--,--.,..-..r.......,.---,----i-: _ I (6) 2-byte, 1-cycle Instruction, e.g., ADD A, #data I I READ OPCODE I _READ NEXT OPCODE I READ NEXT OPCODE (DISCARD) I I I (C) 1-byte, 2-cycle Instruction, e.g., INC DPTR I I I I I I (D) MOVX (1-byte, 2-cYcle) I I I 2-16 DATA ACCESS EXTERNAL MEMORY Architectural Overview Architectural Overview Figure 17. Bus Cycles Executing from External Program Memory t I ONE MACHINE CYCLE j ONE MACHINE CYCLE ~I~I~IMI~I~ ~I~I~IMI~I~ ALE P5EN RD (A) WITHOUT A MOVX. P2 PO tPClOUT VALID t PClOUT VALID j.-- CYCLE 1 I 51 I52 IS3 I MI~ I56 t PClOUT VALID CYClE2 51 t PClOUT VALID t PClOUT VALID ~ I52 I53 IMI55 I~ I ALE P5EN RD (6) WITH A P2 DPH OUT OR P2 OUT X: PCH OUT MOVX. I )-----< PO t PClOUT VALID t IN PClOUT VALID AIIOEL t PClOUT VALID 2·17 Interrupt Structure The AT89C51 core provides 5 interrupt sources: 2 external interrupts, 2 timer interrupts, and the serial port interrupt. What follows is an overview of the interrupt structure for the A T89C51. Other Atrnel Flash microcontrollers have additional interrupt sources and vectors. Refer to the data sheets on other devices for further information on their interrupts. Interrupt Enables Each of the interrupt sources can be individually enabled or disabled by setting or clearing the Interrupt Enable (IE) bit in the SFR. This register also contains a global disable bit, which can be cleared to disable all interrupts at orice. Figure 18 shows the IE register for the AT89C51. In operation, all the interrupt flags are latched into the interrupt control system during State 5 of every machine cycle. The samples are polled during the following machine cycle. If the flag for an enabled interrupt is found to be set (I), the interrupt system generates an LCALL to the appropriate location in program memory, unless some other condition blocks the interrupt. Several conditi.ons can block an interrupt, including an interrupt of equal or higher priority level already in progress. Figure 19. IP (Interrupt Priority) Register in the AT89C51 (MSB) Priority bit Priority bit Figure 18. Interrupt Enable (IE) Register in the AT89C51 (MSB) Symbol (lSB) 1~1-1-1~lml~I~I~1 Enable bit = a disables n. EA Position IE.S reserved.* IE.4 Serial Port interrupt enable bn. Timer I overflow interrupt enable bit. ETI 1E.3 EXI IE.2 External Interrupt I enable bit. ETa IE.I Timer a Overflow Interrupt enable bit. EXO IE.O External Interrupt a enable bit. 'These reserved bits are used in other Almel microcontrollers. Interrupt Priorities Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing the Interrupt Priority (IP) bit in the SFR. Figure 19 shows the IP register in the AT89C51. A low-priority interrupt can be interrupted by a high-priority interrupt but not by another low-priority interrupt. A high-priority interrupt can not be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level the polling sequence determines a second priority structure. Function reserved" IP.6 reserved* IP.5 reserved· PS IP.4 Serial Port interrupt priority bit. PTI IP.3 Timer I interrupt priority bit. PXI IP.2 External interrupt I priority bit. PTa IP.I Timer a interrupt priority bit. PXO IP.O External interrupt a priority bit. 'These reserved bits are used in other Almel microcontrollers. The hardware-generated LCALL pushes the contents of the Program Counter onto the stack and reloads the PC with the beginning address of the service routine. As previously noted (Figure 4), the service routine for each interrupt begins at a fixed location. Only the Program Counter is automatically pushed onto the stack, not the PSW or any other register. Because only the PC is automatically saved, the programmer can decide how much time to spend saving other registers. This enhances the interrupt response time, albeit at the expense of increasing the programmer's burden of responsibility. As a result, many interrupt functions that are typical in control applications-toggling a port pin, reloading a timer, or unloading a serial buffer, for example-can often be completed in less time than it takes other architectures to begin them. Simulating a Third Priority Level in Software Some applications require more than the two priority levels that are provided by on-chip hardware in Atmel Flash microcontrollers. In these cases, relatively simple software can be written to produce the same effect as a third priority level. First, interrupts that require higher priority than I are assigned to priority I in the IP register. The service routines for priority I Figure 20 shows how the IE and IP registers and the polling sequence work to determine which (if any) interrupt will be serviced. 2-18 Position reserved.* IE.6 ES Function Disables all interrupts. If ~ = 0, no interrupt will be acknowledged. If ~ = I, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. IE.7 =I assigns high priority. =a assigns low priority. IP.7 Enable bit = I enables the interrupt. Symbol (lSB) 1- 1- 1 Architectural Overview Architectural Overview interrupts that are supposed to be interruptible by priority 2 interrupts are written to include the following code. PUSH MOV CALL IE IE, # MASK LABEL ******* (execute service routine) POpping IE restores the original enable byte. Then, a normal RET (rather than another RETI) is used to terminate the service routine. The additional software adds 10 ~s (at 12 MHz) to priority 1 interrupts. ******* POP IE LABEL: As soon as any priority 1 interrupt is acknowledged, the IE register is redefined to disable all but priority 2 interrupts. Then, a CALL to LABEL executes the RET! instruction, which clears the priority 1 interrupt-in-progress flip-flop. At this point, any enabled priority I interrupt can be serviced, but only priority 2 interrupts are enabled. RET RET! Figure 20. A T89 Interrupt Control System IPREGISTER INTO HIGH PRIORITY INTERRUPT 0-0;< TFO INTl . ,,, ,, TFl O---or( Rl Tl O--ot< 0--cY.< • TF2 EXF2 INTERRUPT POLLING SEQUENCE GLOBAL ENABLE LOW PRIORITY INTERRUPT INDIVIDUAL INTERRUPT ENABLES * Only on AT89C521AT89LV521AT89S8252 2-19 2-20 Architectural Overview Memory Organization The information presented in this chapter is collected from the Microcontroller Architectural Overview, AT89C51, AT89LV51, AT89C52, AT89LV52, AT89C2051, and AT89C105l data sheets of this book. The material has been selected and rearranged to form a quick and convenient reference for the programmers of Atmel's microcontroller family of devices. This guide pertains specifically to the AT89C51, AT89LV51, AT89C52, and AT89LV52. Memory Organization Program Memory The AT89C Microcontroller has separate address spaces for program memory and data memory. The program memory can be up to 64 Kbytes long. The lower addresses may reside onchip. Figure 1 shows a map of the AT89C5l program memory, and Figure 2 shows a map of the AT89C52 program memory. The AT89C10511205l do not have off-board memory expansion. Figure 1. AT89C5l Program Memory FFFF Flash Microcontroller Memory Organization FFFF 60KBYTES EXTERNAL 64KBYTES EXTERNAL ---OR_ 1000 ...._ _ _ _ _ _ _ _... AND OFFF 4KBYTES INTERNAL OOOO~ _ _ _ _ _ _ _ _'" 0000 '--_ _ _ _ _ _ _--1 Figure 2. AT89C52 Program Memory FFFF FFFF 56KBYTES EXTERNAL 84 KBYTES EXTERNAL ---OR_ ~oo '--_ _ _ _ _ _ _ ~ AND 1FFF 8KBYTES INTERNAL 0000'--_ _ _ _ _ _ _--' 0000 '--_ _ _ _ _ _ _........ 0498A 2-21 Data Memory The AT89C can directly address up to 64 Kbytes of'data mem- ' ory external to the chip. The MOVX instruction accesses the external data memory. (Refer to the Instruction Set section in this chapter for a detailed description of instructions). The AT89C51 has 128 bytes of on-chip RAM (256 bytes in the AT89C52) plus a number of Special Function Registers (SFRs). The lower 128 bytes of RAM can be accessed either by direct addressing (MOV data addr) or by indirect addressing (MOV @Ri). Figure 3 shows the AT89C51 and the AT89C52 data memory organization. Figure 3a. The AT89C5 1 Data Memory FFFF INTERNAL FF 64 KBYTES EXTERNAL SFRs DIRECT ADDRESSING ONLY 80 7F AND DIRECT AND INDIRECT ADDRESSING 0000 00 Figure 3b. The AT89C52 Data Memory INTERNAL ! FF FFFF SFRs DIRECT ADDRESSING ONLY 80HTOFFH FF I INDIRECT ADDRESSING ONLY 80 7F 64 KBYTES EXTERNAL _ 80 -AND DIRECT AND INDIRECT ADDRESSING 0000 00 2-22 Memory Organization' Memory Organization Indirect Address Area In Figure 3b, the SFRs and the indirect address RAM have the same addresses (80H through OFFH). Nevertheless, they are two separate areas and are accessed in two different ways. For example, the following instruction writes OAAH to Port 0, which is one of the SFRs. MOY 80H, # OAAH The following instruction writes OBBH in location 80H of the data RAM. MOY RO,#80H MOY @ RO, # OBBH Thus, after executing both of these instructions, Port 0 contains OAAH, and location SOH of the RAM contains OBBH. The stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space in devices that implement 256 bytes of internal RAM. Direct and Indirect Address Area The 128 bytes of RAM that can be accessed by both direct and indirect addressing can be divided into 3 segments as described in this section and as shown in Figure 4. 1. Register Banks 0-3: Locations 0 through IFH (32 bytes). Reset default is to register bank O. To use the other register banks, the user must select them in the software. Each register bank contains eight I-byte registers, 0 through 7. Reset initializes the Stack Pointer to location 07H. The Stack Pointer is then incremented once to start from location OSH, which is the first register (RO) of the second register bank. Thus, in order to use more than one register bank, the SP should be initialized to a different location of the RAM that is not used for data storage (that is, a higher part of the RAM). 2. Bit Addressable Area: 16 bytes have been assigned for this segment, 20H through 2FH. Each of the 128 bits of this segment can be directly addressed (0 through 7FH). These bits can be referred to in two ways. One way is to refer to their addresses, that is, 0 to 7FH. The other way is with reference to bytes 20H to 2FH. Thus, bits 0 through 7 can also be referred to as bits 20.0 through 20.7, and bits S through FH are the same as 21.0 through 21.7, and so on. Each of the 16 bytes in this segment can also be addressed as a byte. 3. Scratch Pad Area: Bytes 30H through 7FH are available to the user as data RAM. However, if the stack pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction. Figure 4. 12S Bytes of Directly and Indirectly Addressable RAM 11+4------- 8 Bytes -------+l~1 78 7F 70 77 68 6F 60 67 58 SF 50 57 48 4F SCRATCH PAD AREA 40 47 38 3F 30 37 ... 7F 28 20 0 ... 2F 27 BIT ADDRESSABLE SEGMENT 18 3 10 2 17 REGISTER 08 1 OF BANKS 00 0 07 1F 2-23 Special Function Registers Table I contains a list of all the SFRs and their addresses. All of the SFRs that are byte- and bit-addressable are located on the first column of the diagram in Figure 5. Table 1. Special Function Registers Symbol Name Address *ACC *B *PSW SP DPTR DPL DPH *PO *P1 *P2 *P3 *IP *IE TMOD *TCON *+T2CON +T2MOD THO TLO TH1 TL1 +TH2 +TL2 +RCAP2H +RCAP2L 'SCON SBUF PCON Accumulator B Register Program Status Word Stack Pointer Data Pointer 2 Bytes Low Byte High Byte Port 0 Port 1 Port 2 Port 3 Interrupt Priority Control Interrupt Enable Control Timer/Counter Mode Control Timer/Counter Control Timer/Counter 2 Control Timer/Counter 2 Mode Control Timer/Counter 0 High Byte Timer/Counter 0 Low Byte Timer/Counter 1 High Byte Timer/Counter 1 Low Byte Timer/Counter 2 High Byte Timer/Counter 2 Low Byte TIC 2 Capture Reg. High Byte TIC 2 Capture Reg. Low Byte Serial Control Serial Data Buffer Power Control OEOH OFOH ODOH 81H * = Bit addressable + = AT89C52 only 2-24 Memory Organization 82H 83H 80H 90H OAOH OBOH OB8H OA8H. 89H 88H OC8H OC9H 8CH 8AH 8DH 8BH OCDH OCCH OCBH OCAH 98H 99H 87H Memory Organization Contents of the SFRs Just After Power-On or a Reset Table 2. Contents of the SFRs after power-on or a hardware reset Register Value in Binary "ACC "B "PSW SP DPTR DPH DPL "PO "P1 "P2 "P3 "IP 00000000 00000000 00000000 00000111 "IE TMOD +T2MOD "TCON "+T2CON THO TLO TH1 TL1 +TH2 +TL2 +RCAP2H +RRAP2L "SCON SBUF PCON 00000000 00000000 11111111 11111111 11111111 11111111 BOC51 XXXOOOOO, BOC52 XXOOOOOO BOC51 OXXOOOOO, BOC52 OXOOOOOO 00000000 XXXXXXOO 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Indeterminate CMOS OXXXOOOO x =Undefined * =Bit Addressable + = AT89C52 only 2-25 Special Function Register Map Figure S. SFR Memory Map 8 Bytes F8 FO FF B F7 E8 EO EF ACC E7 D8 DF DO PSW" C8 T2CON*+ D7 T2MOD+ RCAP2L+ RCAP2H+ TL2+ TH2+ CF C7 CO B8 BF IP" BO P3 B7 A8 IE" AF AO P2 98 SCON" 90 P1 88 TCON" TMOD* TLO TL1 80 PO SP DPL DPH A7 9F SBUF 97 t Bit Addressable * SFRs converting mode or control bits + AT89C52 only 2-26 Memory Organization THO 8F TH1 PCON* 87 Memory Organization SFRs whose bits are assigned for various functions are listed in this section. For more detailed information, refer to the Microcontroller Architectural Overview chapter of this book. PSW: Program Status Word (Bit Addressable) CY AC FO RS1 RSO CY PSW.7 AC PSW.6 Auxiliary carry flag. FO PSW.S Flag 0 available to the user for general purpose. RSI PSWA Register Bank selector bit 1 (see note 1). RSO PSW.3 Register Bank selector bit 0 (see note 1). OV PSW.2 Overflow flag. PSW.l User definable flag. P P OV Carry flag. Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of 1 bits in the accumulator. 1. The values of RSO and RS I select the corresponding register bank. PSW.O Note: RS1 RSO Register Bank Address 0 0 0 OOH-07H 08H-OFH 0 1 1 1 0 2 10H-17H 1 1 3 18H-1 FH PCON: Power Control Register (Not Bit Addressable) I SMOO I SMOD GFO GF1 PO IOL Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD Serial Port is used in modes 1,2, or 3. Not implemented, reserved for future use. =1, the baud rate is doubled when the * Not implemented, reserved for future use." Not implemented, reserved for future use. • GFI General purpose flag bit. GFO General purpose flag bit. PD Power Down bit. Setting this bit activates Power Down operation in the AT89CSI. IDL Idle Mode bit. Setting this bit activates Idle Mode operation in the AT89CSI. If Is are written to PD and IDL at the same time, PD takes precedence. * User software should not write Is to reserved bits. These bits may be used in future microcontrollers to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be I. 2·27 Interrupts In order to use any of the interrupts in the Flash microcontroller, take the following three S1;eps. 1. Set the EA (enable all) bit in the IE register to 1. 2. Set the corresponding individual interrupt enable bit in the IE register to 1. 3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt. See the following table. Interrupt Source Vector Address lEO 0OO3H TFO OOOBH IE1 0013H TF1 001BH R1 & T1 0023H TF2 & EXF2* 002BH • AT89C52 only. In addition, for external interrupts, pins INTO and INTI (P3.2 and P3.3) must be set to 1, and depending on whether the interrupt is to be level or transition activated, bits ITO or ITI in the TCON register may need to be set to 1. ITx ITx = 0 level activated = I transition activated IE: Interrupt Enable Register (Bit Addressable) If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled. EA ET2 ES ET1 EX1 ETO = EXO Disables all interrupts. If EA 0, no interrupt is acknowledged. If EA is individually enabled or disabled by setting or clearing its enable bit. =1, each interrupt source EA IE.? 1E.6 Not implemented, reserved for future use.* ET2 1E.5 Enables or disables the Timer 2 overflow or capture interrupt (AT89C52 only). ES 1E.4 Enables or disables the serial port interrupt. ETI 1E.3 Enables or disables the Timer I overflow interrupt. EXI 1E.2 Enables or disables External Interrupt l. ETO IE. 1 Enables or disables the Timer 0 overflow interrupt. EXO IE.O Enables or disables External Interrupt 0 . • User software should not write I s to reserved bits. These bits may be used in future Flash microcontrollers to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be I. 2-28 Memory Organization Memory Organization Assigning Higher Priority to One or More Interrupts In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1. While an interrupt service is in progress, it cannot be interrupted by an interrupt of the same or lower priority. Priority Within Level The only purpose of priority within a level is to resolve simultaneous requests of the same priority level. From high to low, interrupt sources are listed below. lEO TFO IEI TFI RI or TI TF20rEXF2 IP: Interrupt Priority Register (Bit Addressable) If the bit is 0, the corresponding interrupt has a lower priority. If the bit is 1, the corresponding interrupt has a higher priority. PT2 PS PT1 PX1 PTO PXO IP.7 Not implemented, reserved for future use. * IP.6 Not implemented, reserved for future use. * PT2 PS IP.5 Defines the Timer 2 interrupt priority level (AT89C52 only). IP.4 Defines the Serial Port interrupt priority level. PTI IP.3 Defines the Timer I interrupt priority level. PXI PTO IP.2 IP. I Defines the Timer 0 interrupt priority level. PXO IP.O Defines the External Interrupt 0 priority level. • Defines External Interrupt I priority level. User software should not write I s to reserved bits. These bits may be used in future Flash microcontrollers to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. AIIDEL 2-29 TCON: Timer/Counter Control Register (Bit Addressable) TF1 TR1 TFO 1Fl TCON.7 TRO IE1 IT1 lEO ITO Timer 1 overflow flag. Set by hardware when the Timer/Counter 1 overflows. Cleared by hardware as the processor vectors to the interrupt service routine. TRI TCON.6 Timer 1 run control bit. Sei/cleared by software to turn Timer/Counter ION/OFF. 1FO TCON.5 Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hardware as the processor vectors to the service routine. TRO lEI TCON.4 Timer 0 run control bit. Sei/cleared by software to turn Timer/Counter 0 ON/OFF .. TCON.3 External Interrupt 1 edge flag. Set by hardware when the External Interrupt edge is detected. Cleared by hardware when the interrupt is processed. IT! TCON.2 Interrupt 1 type control bit. Sei/cleared by software to specify falling edgel10w level triggered External Interrupt. lEO TCON.l External Interrupt 0 edge flag. Set by hardware when External Interrupt edge detected. Cleared by hardware when interrupt is processed. ITO TCON.O Interrupt 0 type control bit. Sei/cleared by software to specify falling edge/low level triggered External Interrupt. TMOD: Timer/Counter Mode Control Register (Not Bit Addressable) I Timer 1 GATE GATE cff I CIT M1 MO I Timer 0 GATE I CIT M1 MO When TRx (in TCON) is set and GATE =I, TIMERlCOUNTERx runs only while the INTx pin is high (hardware control). When GATE =0, TIMERlCOUNTERx will run only while TRx =1 (software control). Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin). Ml Mode selector bit (note 1). MO NOTEl: Mode selector bit (note 1). M1 MO Operating Mode 0 0 0 13-bit Timer 0 1 1 16-bit Timer/Counter 1 0 2 8-bit Auto-Reload Timer/Counter 1 1 3 Split Timer Mode: (Timer 0) TLO is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits, THO is an 8-bit Timer and is controlled by Timer 1 control bits. 1 1 3 (Timer 1) Timer/Counter 1 stopped. 2-30 Memory Organization Memory Organization Timer Set-Up Tables 3 through 6 give TMOD values that can be used to set up Timer 0 in different modes. It is assumed that only one timer is used at a time. If Timers 0 and 1 must run simultaneously in any mode, the value in TMOD for Timer 0 must be ORed with the value shown for Timer 1 (Tables 5 and 6). For example, if Timer 0 must run in mode I GATE (external control), and Timer.1 must run in mode 2 COUNTER, then the value that must be loaded into TMOD is 69H (09H from Table 3 ORed with 60H from Table 6). Moreover, it is assumed that the user is not ready at this point to turn the timers on and will do so at another point in the program by setting bit TRx (in TCON) to 1. Timer/Counter 0 Table 3. Timer/Counter 0 Used as a Timer TMOD MODE TIMER 0 FUNCTION a 13-bit Timer OOH 1 16-bit Timer 01H 09H 2 8-bit Auto-Reload 02H OAH 3 two 8-bit Timers 03H aSH INTERNAL EXTERNAL CONTROL (NOTE 1) CONTROL (NOTE 2) 08H Table 4. Timer/Counter 0 Used as a Counter TMOD MODE TIMER 0 FUNCTION a 13-bit Timer 04H OCH 1 16-bit Timer 05H ODH 2 8-bit Auto-Reload 06H OEH 3 one 8-bit Counter 07H OFH NOTES: INTERNAL EXTERNAL CONTROL (NOTE 1) CONTROL (NOTE 2) 1. The Timer is turned ON/OFF by setting/clearing bit 'fRO in the software. 2. The Timer is turned ON/OFF by the I to 0 transition on INTO (p3.2) when 'fRO = 1 (hardware control). 2-31 Timer/Counter 1 Table S. Timer/Counter 1 Used as a Timer TMOD MODE TIMER 1 FUNCTION 0 l3-bitTimer OOH 80H 1 lS-bit Timer 10H 90H 2 8-bit Auto-Reload 20H AOH 3 does not run 30H BOH INTERNAL EXTERNAL CONTROL (NOTE 1) CONTROL (NOTE 2) Table 6. Timer/Counter 1 Used as a Counter TMOD MODE COUNTER 1 FUNCTION 0 l3-bit Timer 40H COH 1 lS-bit Timer SOH DOH 2 8-bit Auto-Reload SOH EOH 3 not available - - NOTES: 2-32 INTERNAL EXTERNAL CONTROL (NOTE 1) CONTROL (NOTE 2) 1. The Timer is turned ON/OFF by setting/clearing bit TRI in the software. 2. The TImer is turned ON/OFF by the I to 0 transition on INTI (P3.3) wen TRI = I (hardware control). Memory Organization Memory Organization T2CON: Timer/Counter 2 Control Register (Bit Addressable) AT89C52 Only I TF2 TF2 I EXF2 I RCLK I TCLK I EXEN2 I TR2 CIT2 ICP/RL2 I TICON.7 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when either RCLK 1 or CLK 1 TICON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on TIEX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 causes the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. TICON.5 Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK 0 causes Timer 1 overflow to be used for the receive clock. = EXF2 RCLK = • = 'ILCK TICON.4 Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK 0 causes Timer I overflows to be used for the transmit clock. EXEN2 TICON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of negative transition on T2EX if Timer 2 is not being used to clock the Serial Port. EXEN2 0 causes Timer 2 to ignore events at T2EX. = = TR2 TICON.2 Software START/STOP control for Timer 2. A logic 1 starts the Timer. Crf2 T2CON.l Timer or Counter select. CP/RL2 TICON.O CapturelReload flag. When set, captures occur on negative transitions at TIEX if EXEN2 = 1. When cleared, auto-reloads occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the Timer is forced to auto-reload on Timer 2 overflow. 0= Internal Timer. 1 = External Event Counter (triggered by falling edge). T2MOD: Timer 2 Mode Control Register T2MOD Address = OC9H Reset Value = XXXX XXOOB Not Bit Addressable T20E Bit 7 6 5 4 Symbol - 3 I 2 DCEN o Function Not implemented, reserved for future use T20E Timer 2 Output Enable bit DCEN When set, this bit allows Timer 2 to be configured as an up/down counter. AIIDEL 2-33 Timer/Counter 2 Set-Up Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set separately to turn the Timer on. Table 7. Timer/Counter 2 Used as a Timer T2CON MODE INTERNAL CONTROL (NOTE 1) EXTERNAL CONTROL (NOTE 2) 16-bit Auto-Reload OOH 08H 16-bit Capture 01H 09H Baud rate generator receive and transmit same baud rate 34H 36H receive only 24H 26H transmit only 14H 16H Table 8. Timer/Counter 2 Used as a Counter TMOD MODE INTERNAL CONTROL (NOTE 1) EXTERNAL CONTROL (NOTE 2) 16-bit Auto Reload 02H OAH 16-bit Capture 03H OBH NOTES: 2-34 I.CapturelReload occurs only on Timer/Counter overflow. 2.CapturelReload occurs on Timer/Counter overflow and a I to 0 transition on TIEX (PI.!) pin except when Timer 2 is used in the baud rate generating mode. Memory Organization Memory Organization SCON: Serial Port Control Register (Bit Addressable) I SMO I I SM1 SM2 I REN I TBB RBB TI RI SMO SCaN. 7 SMI SCaN. 6 Serial Port mode specifer. (NOTE !). Serial Port mode specifer. (NOTE I). SM2 SCaN. 5 Enables the mUltiprocessor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI is not activated if the received ninth data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI is not activated if a valid stop bit was not received. In mode 0, SM2 should be 0. (See Table 9). REN SCaN. 4 Set/Cleared by software to EnablelDisable reception. TB8 SCaN. 3 The ninth bit that is transmitted in modes 2 and 3. Set/Cleared by software. RB8 SCaN. 2 In modes 2 and 3, is the ninth data bit that was received. In mode 1, if SM2 was received. In mode 0, RB8 is not used. TI SCaN. I Transmit interrupt flag. Set by hardware at the end of the eighth bit time in mode 0 or at the beginning of the stop bit in the other modes. Must be cleared by software. RI SCaN. =0, RB8 is the stop bit that ° ° Receive interrupt flag. Set by hardware at the end of the eighth bit time in mode or halfway through the stop bit time in the other modes (except see SM2). Must be cleared by software. NOTE!: SMO SM1 Mode Description Baud Rate a a a SHIFT REGISTER Fosc'/12 0 1 1 B-Bit UART Variable 1 a 2 9-Bit UART Fosc./64 OR Fosc./32 1 1 3 9-Bit UART Variable Table 9. Serial Port Set-Up MODE SCON SM2 VARIATION 0 10H Single Processor 1 50H Environment 2 90H (SM2=O) 3 DOH a NA Multiprocessor 1 70H Environment 2 BaH (SM2 = 1) 3 FOH AIIIEL 2-35 AIIOEL Generating Baud Rates Serial Port in Mode 0 Using Timer/Counter 2 to Generate Baud Rates Mode 0 has a fixed baud rate, which is 1112 of the oscillator frequency. To run the serial port in this mode, none of the Timer/Counters need to be set up. Only the SCON register needs to be defined. For this purpose, Timer 2 must be used in the baud rate generating mode. Refer to Timer 2 Setup Table in this chapter. If Timer 2 is clocked through pin T2 (PI.O) the baud rate given by the following equation. B dR t au ae B dR t _ OscFreq au ae 12 If it is being clocked internally the baud rate is given by the following equation. Serial Port in Mode 1 Mode I has a variable baud rate. The baud rate can be generated by either Timer I or Timer 2 (AT89C52 only). Using Timer/Counter 1 to Generate Baud Rates Baud Rate = Freq. = 32Kx x12Oscillator x [256 - (THI)l If SMOD = 0, then K = I. If SMOD = I, then K =2. (SMOD is the PeON register). The user usually knows the baud rate but needs to know the reload value for THI. Therefore, the equation to calculate THI can be written as follows. THI = 256 _ K x Osc Freq. 384 x baud rate THI must be an integer value. Rounding offTHI to the nearest integer may not produce the desired baud rate. In this case, the user may have to choose another crystal frequency. See Baud Rate table. Since the PCON register is not bit addressable, one way to set the bit is logical ~Ring the PCON register (that is, ORL PCON, # 80H). The address of PC ON is 87H. 2-36 Osc Freg. 32 x [65536 - (RCAP2H, RCAP2Wl To obtain the reload value for RCAP2H and RCAP2L the previous equation can be rewritten as follows. For this purpose, Timer I is used in mode 2 (Auto-Reload). Refer to the Timer Setup section of this chapter. Baud Rate Rate = Timer 2 Overflow 16 RCAP2H, RCAP2L = 65536 _ Osc Freg. 32 x BaudRate Serial Port in Mode 2 The baud rate is fixed in this mode and is 1132 or 1164 of the oscillator frequency, depending on the value of the SMOD bit in the PeON register. In this mode, none of the Timers is used, and the clock comes from the internal phase 2 clock. SMOD =I, Baud Rate =1132 Osc Freq. SMOD = 0, Baud Rate = 1164 Osc Freq. To set the SMOD bit, use ORL PeON is 87H. PCON, # 80H. The address of Serial Port in Mode 3 The baud rate in mode 3 is variable and sets up exactly the same as in mode 1. Memory Organization Memory Organization Baud Rate Table Crystal Frequency 7.3728 MHz 8MHz 11.0592 MHz 12.00 MHz EO 600 651 900 976 1,200 1,302 FO 1,200 1.302 1,800 1,953 2,400 2,604 F8 2,400 2,604 3,600 3,906 4,800 5,208 F9 2,743 2,976 8,229 4,464 5,486 5,952 FA 3,200 3,472 9,600 5,208 6,400 6,944 FF 19,200 20,833 57,600 62,500 14.75156 MHz 16.00 MHz TH1 41,666 Table 10. Baud Rate Summary Baud Rate Crystal Frequency SMOD TH1 Reload Value Actual Baud Rate 9600 12.000 MHz 1 ·7 (F9H) 8923 7% 2400 12.000 MHz 0 -13 (F3H) 2404 0.16% 0.16% Error 1200 12.000 MHz 0 -26 (E6H) 1202 19200 11.059 MHz 1 -3 (FDH) 19200 0 9600 11.059 MHz 0 -3 (FDH) 9600 0 2400 11.059 MHz 0 -12 (F4H) 2400 0 1200 11.059 MHz 0 -24 (E8H) 1200 0 NOTE: Due to rounding, there is a slight error in the resulting baud rate. Generally, a 5% error is tolerable using asynchronous (start/stop) communications. Exact baud rates are possible using an 11.059 MHz crystal. The table above summarizes the THI reload values for the most common baud rates, using a 12.000 MHz or 11.059 MHz crystal. 2-37 2·38 Memory Organization AT89 Series Hardware Description Introduction This chapter presents a comprehensive description of the on-chip hardware features of Atmel's Flash-based microcontrollers. Included in this description are the following items. • The port drivers and how they function both as ports and, for Ports 0 and 2, in bus operations • The Timer/Counters • The Serial Interface • The Interrupt System • AT89 Series Hardware Description • Reset • The Reduced Power Modes and Low Power Idle The devices under consideration are listed in Table I. Figure 1 shows a functional block diagram of the A T89C51 and AT89C52. Table 1. Atmel's Flash Microcontrollers Device Name Program Memory Data Memory Bytes 16·bit Timers Technology AT89C1051 1K Flash 64 RAM 1 CMOS AT89C2051 2K Flash 128 RAM 2 CMOS AT89C51 4K Flash 128 RAM 2 CMOS AT89C52 8K Flash 256 RAM 3 CMOS 8K Flash 256 RAM 2KEEPROM 3 CMOS AT89S8252 Special Function Registers A map of the on-chip memory area called Special Function Register (SFR) space is shown in Figure 2. SFRs marked by parentheses are resident in the A T89C52 but not in the AT89C51. 0499A AIIDEL 2·39 Figure 1. AT89C51 and AT89C52 Flash-Based Microcontroller Architectural Block Diagram PO.O-PO.7 P2.o-P2.7 ------------------------, ~ ,ij~~~ I ~ "I I Vss I I I ~ I I I I I I I I SOON lHO THOS8UF TMOD TCON TlO THI n2" RCAP2H' IE IP INTERRUPT. SERIAL PORT AND TIMER BLOCKS I I I I I I AlE Eli I I I I RST I I I I I I I I I I ~I PI.o-P1.7 2-40 AT89 Series Hardware Description P3.0-P3.7 'Reslden1ln AT89C52 only. AT89 Series Hardware Description Figure 2. SFR Map. ( ... ) Indicates Resident in ATS9C52, not in ATS9C5J. 8 Bv\es F8 FO E8 EO 08 DO C8 CO B8 BO A8 AO 98 90 88 80 B ACC PSW (T2CON) (T2MOO) IP P3 IE P2 SCON P1 TCON PO (RCAP2L) (RCAP2H) (TL2) (TH2) THO TH1 SBUF TMOO SP TLO OPL TL1 OPH Not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses in general return random data, and write accesses have no effect. User software should not write Is to these unimplemented locations, since they may be used in future microcontrollers to invoke new features. In that case, the reset or inactive values of the new bits will always be 0, and their active values will be 1. The functions of the SFRs are outlined in the following sections. Accumulator ACC is the Accumulator register. The mnemonics for Accumulator-specific instructions, however, refer to the Accumulator simply as A. B Register The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register. Program Status Word The PSW register contains program status information, as detailed in Figure 3. PCON FF F7 EF E7 OF 07 CF C7 BF B7 AF A7 9F 97 8F 87 Data Pointer The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent S-bit registers. Ports OTo3 PO, PI, P2, and P3 are the SFR latches of Ports 0, I, 2, and 3, respectively. Serial Data Buffer The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register. When data is moved to SBUF, it goes to the transmit buffer, where it is held for serial transmission. (Moving a byte to SBUF initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer. Timer Registers Register pairs (THO, TLO), (THI, TLI), and (TH2, TL2) are the 16-bit Counter registers for Timer/Counters 0, I, and 2, respectively. Stack Pointer Capture Registers The Stack Pointer Register is S bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location OSH. The register pair (RCAP2H, RCAP2L) are the Capture registers for the Timer 2 Capture Mode. In this mode, in response to a transition at the ATS9C52' s TIEX pin, TH2 and TL2 are copied into RCAP2H and RCAP2L. Timer 2 also has a 16-bit auto-reload mode, and RCAP2H and RCAP2L hold the reload value for this mode. 2-41 • AIIOEL Control Registers Special Function Registers IP, IE, TMOD, TCON, TICON, T2MOD, SCON, and PCON contain control and status bits for the interrupt system, the Timer/Counters, and the serial port. They are described in later sections of this chapter. Figure 3. PSW: Program Status Word Register (MSB) CY Symbol (LSB) RSl FO AC Position Name and Significance CY AC FO PSW.7 PSW.6 PSW.5 RS! RSO PSW.4 PSW.3 Carryllag. AuXiliary Carry flag. (For BCD operations.) Flag 0 (Available to the user lor general purposes.) Register bank select control bits 1 and O. Set/cleared by software to determine working register bank (see Note). RSO Symbol OV P P OV Position Name and Significance PSW.2 PSW.l PSW.O Overflow flag. User definable Ilag. Parity flag. Set/cleared by hardware each instruction cycle to indicate an add/even number of 1 bits in the Accumulator, that is, even parity. NOTE: The contents 01 (RS1, RSO) enable the working register banks as follows: (O.O)-Bank O(OOH-07H) (O.l)-Bank 1(OBH-OFH) (1.0)-Bank 2(10H-17H) (1. I)-Bank 3(IBH-l FH) Figure 4. AT89C51 and AT89C52 Port Bit Latches and YO Buffers *See Figure 5 for details of the internal pullup. ADDR/DATA READ READ LATCH LATCH INT. BUS INT. BUS WRITE TO WRITE TO LATCH LATCH READ PIN READ PIN A. PORTO BIT ADDR ALTERNATE OUTPUT FUNCllON CONTROL vee READ READ LATCH LATCH INT. BUS INT.BUS WAITE TO WRITE TO LATCH LATCH READ PIN B. PORT 1 BIT READ C. PORT 2 BIT PIN D. PORT 3 BIT 2-42 AT89 Series Hardware Description AT89 Series Hardware Description Port Structures and Operation All four ports in the AT89C5 I and AT89C52 are bidirectional. Each consists of a latch (Special Function Registers PO through P3), an output driver, and an input buffer. The output drivers of Ports 0 and 2, and the input buffers of Port 0, are used in accesses to external memory. In this application, Port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise the Port 2 pins continue to emit the P2 SFR content. All the Port 3 pins, and two Port I pins (in the AT89C52) are multifunctional. They are not only port pins, but also provide the special features listed in the following table. Port Pin Alternate Function ·P1.0 T2 (Timer/Counter 2 extemal input) ·P1.1 T2EX (Timer/Counter 2 Capture/Reload trigger) P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INTO (external interrupt) P3.3 INT1 (external interrupt) P3.4 TO (Timer/Counter 0 external input) P3.5 T1 (Timer/Counter 1 extemal input) P3.6 WR (external data memory write strobe) P3.7 RD (extemal data memory read strobe) ·PI.O and Pl.I serve these alternate functions only on the AT89C52. The alternate functions can only be activated if the corresponding bit latch in the port SFR contains a I. Otherwise the port pin is stuck at O. 110 Configurations Figure 4 shows a functional diagram of a typical bit latch and I/O buffer in each of the four ports. The bit latch (one bit in the port's SFR) is represented as a Type D flip-flop, which clocks a value from the internal bus in response to a "write to latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a ''read latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read pin" signal from the CPU. Some instructions that read a port activate the "read latch" signal, and others activate the "read pin" signal. As shown in Figure 4, the output drivers of Ports 0 and 2 can be switched to an internal ADDR and ADDRIDATAbus by an internal CONTROL signal for use in external memory accesses. During external memory accesses, the P2 SFR remains unchanged, but Is are written to the PO SFR. If a P3 bit latch contains a I, then the output level is controlled by the alternate output function signal, as shown in Figure 4. The actual P3.x pin level is always available to the pin's alternate input function. Ports I, 2, and 3 have internal pull ups. Port 0 has open drain outputs. Each I/O line can be used independently as an input or an output. (Ports 0 and 2 may not be used as general purpose I/O when being used as the ADDRIDATA BUS). To be used as an input, the port bit latch must contain a I, which turns off the output driver FET. Then, for Ports 1,2, and 3, the pin is pulled high by the internal pullup but can be pulled low by an external source. Port 0 has no internal pullups. The PET pullup in the PO output driver (see Figure 4) is used only when the Port emits Is during external memory accesses. Otherwise, the PET pullup is off. Consequently, PO lines that are used as output port lines are open drain. Writing a 1 to the bit latch leaves both PET outputs off, so the pin floats. In this condition, it can be used a high-impedance input. Because Ports I, 2, and 3 have fixed internal pullups, they are sometimes called quasi-bidirectional ports. When configured as inputs, they pull high and source current (IlL) when externally pulled low. Port 0, on the other hand, is considered truly bidirectional, because it floats when configured as an input. The reset function writes Is to all the port latches in the AT89C51 and AT89C52. If a 0 is subsequently written to a port latch, the latch can be reconfigured as an input if a I is written to it. Writing to a Port When an instruction changes a port latch value, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are sampled by their output buffers only during Phase I of any clock period. (During Phase 2, the output buffer holds the value sampled during the previous Phase I). Consequently, the new value in the port latch does not actually appear at the output pin until the next Phase I, which is at S IPI of the next machine cycle. See Figure 39 in the Internal Timing section. If the change requires a O-to-I transition in Port I, 2, or 3, an additional pullup is turned on during SIPl and SIP2 of the cycle in which the. transition occurs to increase the transition speed. The extra pullup can source about 100 times the current that the normal pullup can. The internal pullups are field-effect transistors, not linear resistors. The pullup arrangements are shown in Figure 5. 2-43 2 Figure S. Ports 1 and 3 Internal Pullup Configurations. Port 2 is similar except that it holds the strong pullup on while emitting Is that are address bits. (See text, "Accessing External Memory".) Vcc Vcc Vcc Q C>--.---------~--------~~~ FROM PORT LATCH INPUT <':':r---<>~ DATA READ PORT PIN pFET1 is turned on for 2 osc. periods after Q makes a O-to-1 transition. During this time, pFET1 also turns on pFET3 through the inverter to form a latch which holds the 1. pFET2 is also on. The pullup consists of three pFETs. An n-channel FET (nFET) turns on when a logical 1 is applied to its gate, and turns off when a logical 0 is applied to its gate. A p-channel FET (pFET) is the opposite: it is on when its gate sees a 0 and off when its gate sees a 1. The pFETl transistor in Figure 5 is turned on for 2 oscillator periods after a O-to-I transition in the port latch. While pFETl is on, it turns on pFET3 (a weak pullup) through the inverter. This inverter and pFETI form a latch that holds the 1. If the pin emits a I, a negative glitch on the pin from some external source can turn off pFET3, causing the pin to go into a float state. pFET2 is a very weak pullup which is on whenever the nFET is off, in traditional CMOS style. pFET2 is only about 1110 the strength of pFET3. Its function is to restore a 1 to the pin in the event the pin lost a 1 in a glitch. Port Loading and Interfacing The output buffers of Ports 1, 2, and 3 can each drive 4 LS TTL inputs. CMOS pins can be driven by open-collector and opendrain outputs, but O-to-I transitions will not be fast. An input 0 turns off pullup pFET3, leaving only the very weak pullup pFET2 to drive the transition. In external bus mode, Port 0 output buffers can drive 8 LS TTL inputs. As port pins, they require external pullups to drive any inputs. Read-Modify-Write Feature Some instructions that read a port read the latch and others read the pin. Read-modify-write instructions read the latch rather than the pin, and these instructions read a value, possibly change it, and then rewrite it to the latch. When the destination operand 2-44 is a port, or a port bit, the read-modify-write instructions given in the following table read the latch rather than the pin. Mnemonic Instruction Example ANL Logical AND ANL Pl, A ORL Logical OR ORLP2,A XRL Logical EX"()R XRL P3, A JBC Jump if bit =1 and clear bit JBC P1.1, LABEL CPL Complement bit, CPL P3.0 INC Increment INCP2 DEC Decrement DECP2 DJNZ Decrement and jump if not zero DJNZ P3, LABEL MOV, PX.Y,C Move carry bit to bit Y of Port X CLRPX.Y Clear bit Y of Port X SETBPX.Y Set bit Y of Port X The last three instructions in this list are read-modify-write instructions, because they read all 8 bits of the port byte, modify the addressed bit, then write the new byte back to the latch. Read-modify-write instructions are directed to the latch rather than the pin in order to avoid misinterpreting the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a 1 is written to the bit, the transistor is Al89 Series Hardware Description AT89 Series Hardware Description turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a O. Reading the latch rather than the pin will return the correct value of 1. Accessing External Memory Accesses to external memory are either to program memory or to data memory. Accesses to external program memory use the PSEN (program store enable) signal as the read strobe. Accesses to external data memory use RD or WR (alternate functions of P3.7 and P3.6) to strobe the memory. Refer to Figures 36 through 38 in the Internal Timing section for more information. Fetches from external progam memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOYX @DPTR) or an 8-bit address (MOYX @Ri). Whenever a 16-bit address is used, the high byte of the address comes out on Port 2, where it is held for the duration of the read or write cycle. Note that the Port 2 drivers use the strong pull ups during the entire time that they emit address bits that are Is (during the execution of a MOYX @DPTR instruction.) During this time, the Port 2 latch (the Special Function Register) does not have to contain Is, and the contents of the Port 2 SFR are not modified. If the external memory cycle is not immediately followed by another external memory cycle, the undisturbed contents of the Port 2 SFR reappear in the next cycle. Ifan 8-bit address is used (MOYX @Ri), the contents of the Port 2 SFR remain at the Port 2 pins throughout the external memory cycle, which facilitates paging. In any case, the low byte of the address is time-multiplexed with the data byte on Port O. The ADDRIDATA signal drives both PETs in the Port 0 output buffers. Thus, in this application the Port 0 pins are not open-drain outputs and do not require external pullups. The Address Latche Enable (ALE) signal should be used to capture the address byte into an external latch. The address byte is valid at the negative transition of ALE. Then, in a write cycle, the data byte to be written appears on Port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at Port ojust before the read strobe is deactivated. During any access to external memory, the CPU writes OFFH to the Port 0 latch (the Special Function Register), thus obliterating any information in the Port 0 SFR. If the user writes to Port 0 during an external memory fetch, the incoming code byte is corrupted. Therefore, do not write to Port 0 if external program memory is used. External program memory is accessed under the following two conditions. I) When the EA signal is active; or 2) When the program counter (PC) contains a number larger than OFFFH (lFFFH for the AT89CS2). When the CPU is executing out of external program memory, all 8 bits of Port 2 are dedicated to an output function and may not be used for general purpose VO. During external program fetches, they output the high byte of the PC. During this time, the Port 2 drivers use the strong pullups to emit PC bits that are Is. Timer/Counters The AT89CSI has two 16-bit Timer/Counter registers: Timer 0 and Timer I. The AT89CS2 has these two Timer/Counters, and in addition Timer 2. All three can be configured to operate either as Timers or event Counters. As a Timer, the register is incremented every machine cycle. Thus, the register counts machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1112 of the oscillator frequency. As a Counter, the register is incremented in response to a I-to-O transition at its corresponding external input pin, TO, TI, or (in the AT89CS2) TI. The external input is sampled during SSP2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3PI of the cycle following the one in which the transition was detected. Since 2 machine cycles (24 oscillator periods) are required to recognize a I-to-O transition, the maximum count rate is 1124 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but it should be held for at least one full machine cycle to ensure that a given level is sampled at least once before it changes. In addition to the Timer or Counter functions, Timer 0 and Timer I have four operating modes: (13 bit timer, 16 bit timer, 8 bit auto-reload, split timer). Timer 2 in the AT89CS2 has three modes of operation: Capture, Auto-Reload, and baud rate generator. Timer 0 and Timer 1 Timer/Counters I and 0 are present in both the AT89C51 and A T89CS2. The Timer or Counter function is selected by control bits cff in the Special Function Register TMOD (Figure 6). These two Timer/Counters have four operating modes, which are selected by bit pairs (MI, MO) in TMOD. Modes 0, I, and 2 are the same for both Timer/Counters, but Mode 3 is different. The four modes are described in the following sections. Mode 0 Both Timers in Mode 0 are 8-bit Counters with a divide-by-32 prescaler. Figure 7 shows the Mode 0 operation as it applies to Timer 1. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all Is to all Os, it sets the Timer interrupt flag TFI. The counted input is enabled to the Timer when TRI = I and either GATE 0 or INTI = 1. Setting GATE I allows the Timer to be controlled by external input INTI, to facilitate pulse width measurements. TRI is a control bit in the Special Function Register TCON (Figure 8). GATE is inTMOD. = = The 13-bit register consists of all 8 bits of THland the lower 5 bits of TL1. The upper 3 bits of TLI are indeterminate and should be ignored. Setting the run flag (TRI) does not clear the registers. Mode 0 operation is the same for Timer 0 as for Timer I, except that TRO, TFO and INTO replace the corresponding Timer I signals in Figure 7. There are two different GATE bits, one for Timer I (TMOD.7) and one for Timer 0 (TMOD.3). 2-45 • Figure 6. TMOD: Timer/Counter Mode Control Register (MSB) GATE (lSB) crr Ml MO err GATE Gatinll..2Q!ltrol when set. Timer/Counter x is enabled only while INTx pin is high and TAx oontrol pin Is set. When cleared, Timer x is enabled whenever TAx oontrol bit is set. TImer 0 gate bit ciT Timer or Counter Selector cleared for Timer operation (input from intemal system clock). Set for Counter operation (input from Tx input pin). TimerOMl Ml Mode bit 1 MO Mode bit 0 Timer 0 counterltimer select bit M1 MO Mode Operating Mode o o l3-bitTimer Mode. 8-bit Timer/Counter THz with Tlx as 5-bit prescaler. l6-bit Timer Mode. l6-bit Timer/Counters THx and Tlx are cascaded; there is no prescaler. o 2 8-bit Auto Aeload. 8-bit auto-reload Timer/Counter THx holds a value which is to be reloaded into TLx each time it overflows. 3 Split Timer Mode. (Timer 0) TlO is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. THO is an 8-bit timer only controlled by Timer 1 oontrol bits. 3 (Timer 1) Timer/Counter 1 stopped. TimerSFR Purpose Address Bit-Addressable TCON Control 88H Yes TMOO Mode 89H No TlO Timer 0 low-byte BAH No Tll Timer 1 low-byte BBH No THO Timer 0 high-byte BCH No THl Timer 1 high-byte BOH No T2CON" Timer 2 control CBH Yes T2MOO' Timer 2 Mode C9H No ACAP2l' Timer 2 low-byte capture CAH No ACAP2H' Timer 2 high-byte capture CBH No TL2' Timer 2 low-byte CCH No TH2' Timer 2 high-byte COH No *AT8952 only 2-46 b~ Timer 0 MO bit o o MO Timer 0 Timer 1 GATE Ml AT89 Series Hardware Description AT89 Series Hardware Description Figure 7. Timer/Counter I Mode 0: 13-Bit Counter INTERRUPT • INT1 PIN Figure 8. Timer/Counter I Mode I: 16-Bit Counter Timer Clock ______ ~·l . ___ __ (8T_L_1 Bits) ~____T_H_1__~------~.~ (8 Bits) ~ Overflow Flag Mode 1 Mode 3 Mode I is the same as Mode 0, except that the Timer register is run with all 16 bits. The clock is applied to the combined high and low timer registers (11.. IffH I). As clock pulses are received, the timer counts up: OOOOH, OOOIH, 0002H, etc. An overflow occurs on the FFFFH-to-OOOOH overflow flag. The timer continues to count The overflow flag is the TFI bit in TCON that is read or written by software. See Figure 8. Timer I in Mode 3 simply holds its count. The effect is the same as setting TR I =O. Timer 0 in Mode 3 establishes 11..0 and THO as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 10. 11..0 uses the Timer 0 control bits: clf, GAlE, TRO, INTO, and TFO. THO is locked into a timer function (counting machine cycles) and over the use ofTRI and TFI from Timer I. Thus, THO now controls the Timer I interrupt Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89C51 can appear to have three Timer/Counters, and an AT89C52, can appear to have four. When Timer 0 is in Mode 3, Timer I can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer I can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt. Mode 2 Mode 2 configures the Timer register as an 8-bit Counter ('ILl) with automatic reload, as shown in Figure 9. Overflow from 11..1 not only sets TFI, but also reloads 11..1 with the contents of THI, which is preset by software. The reload leaves THI unchanged. Mode 2 operation is the same for Timer/Counter O. Figure 9. Timer/Counter I Mode 2: 8-Bit Auto-Reload INTERRUPT 2-47 Figure 10. Timer/Counter 0 Mode 3: Two 8-Bit Counters E J - - - - a - - . l / 1 210SC 1/1210SC - - - - - - , INTERRUPT TO PIN - - - - - - ' TRO----" GATE INTO PIN 1/121 0SC ---------+-%'-+--+I INTERRUPT TRI Figure 11. TCON: Timer/Counter Control Register (MSB) TFI (LSB) I TRI I TFO I TRO I lEI I ITI I lEO I I ITO Symbol Position Name and Significance TFI TCON.7 Timer 1 overflow Ilag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. TRI TCON.6 Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off. TFO TCON.5 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. TRO TCON.4 Timer 0 run control bit. Set/cleared by software to tum Timer/Counter on/off. lEI TCON,3 Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. ITI TCON.2 Interrupt I type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. lEO TCON.I Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. ITO TCON.O Interrupt 0 type control bit. Set/cleared by software to specify falling edgellow level triggered external interrupts. Timer 2 Table 2. Timer 2 Operation Modes Timer 2 is a 16-bit Timer/Counter present only in the AT89C52. This is a powerful addition to the other two just discussed. Five extra special function registers are added to accommodate Timer 2 which are: the timer registers, TL2 and TH2, the timer control register, T2CON, and the capture registers, RCAP2L and RCAP2H. Like Timers 0 and 1, it can operate either as a timer or as an event counter, depending on the value of bit CIT2 in the Special Function Register TICON (Figure 12). Timer 2 has three operating modes: capture, auto-reload, and baud rate generator, which are selected by bits in TICON, as shown in Table 2. 2-48 RCLK+TCLK CPIRL2 TR2 Mode 0 0 1 16-bit AutoReload 0 1 1 16-bit Capture 1 X 1 Baud Rate Generator X X 0 (off) AT89 Series Hardware Description AT89 Series Hardware Description Figure 12. T2CON Timer/Counter 2 Control Register (MSB) TF2 (LSB) I EXF2 I RCLK I TCLK I EXEN2 I TR2 I I CfT2 CP/RL2 Symbol Position Name and Significance TF2 T2CON.7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. RCLK T2CON.5 Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in Modes 1, 3 and Timer 1 provides transmit baud rate. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. TCLK T2CON.4 Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in Modes 1, 3 and Timer 1 provides transmit baud rate. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 0 causes Timer 2 to ignore events at T2EX. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. Cm T2CON.l Timer or counter select. (Timer 2) o = Internal timer (OSC/12) 1 = External event counter (falling edge trtggered). CP/RL2 T2CON.O Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto·reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto·reload on Timer 2 overflow. I • = In the Capture Mode, the EXEN2 bit in T2CON selects two options. If EXEN2 =0, then Timer 2 is a 16-bit timer or counter whose overflow sets bit JF2, the Timer 2 overflow bit, which can be used to generate an interrupt. IfEXEN2 =1, then Timer 2 performs the same way, but a I-to-O transition at external input T2EX also causes the current value in the Timer 2 registers, 1L2 and TH2, to be captured into the RCAP2L and RCAP2H registers, respectively. (RCAP2L and RCAP2H are new Special Function Registers in the AT89CS2.) In addition, the transition at T2EX sets the EXF2 bit in T2CON, and EXF2, like 1F2, can generate an interrupt. The Capture Mode is illustrated in Figure 13. In the auto-reload mode, the EXEN2 bit in T2CON also selects two options. If EXEN2 = 0, then when Timer 2 rolls over it sets 1F2 and also reloads the Timer 2 registers with the 16-bit value in the RCAP2L and RCAP2H registers, which are preset by software. If EXEN2 = 1, then Timer 2 performs the same way, but a l-to-O transition at external input T2EX also triggers the 16-bit reload and sets EXF2. The baud rate generator mode is selected by RCLK = 1 and/or TCLK =1. This mode is described in conjunction with the serial port. (Figure 17) Serial Interface The serial port is full duplex, which means it can transmit and receive simultaneously. It is also receive-buffered, which means it can begin receiving a second byte before a previously received byte has been read from the receive register. (However, if the first byte still has not been read when reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in the following four modes. Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. The baud rate is fixed at 1112 the oscillator frequency. The auto-reload mode is illustrated in Figure 14. 2-49 Figure 13. Timer 2 In Capture Mode TIMER 2 INTERRUPT EXEN2 Mode 1: 10 bits are transmitted (through TXD) or received (through RXD); a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCaN. The baud rate is variable. Mode 2: 11 bits are transmitted (through TXD) or received (through RXD); a start bit (0), 8 data bits (LSB first), a programmable ninth data bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in SCaN) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) can be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCaN, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. Mode 3: 11 bits are transmitted (through TXD) or received (through RXD); a start bit (0), 8 data bits (LSB first), a programmable ninth data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except the baud rate, which is variable in Mode 3. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI 0 and REN 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. = = The following example shows how to use the serial interrupt for mUltiprocessor communications. When the master processor must transmit a block of data to one of several slaves, it first sends out an address byte that identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave is interrupted by a data byte. An address byte, however, interrupts all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave clears its SM2 bit and prepares to receive the data bytes that follows. The slaves that are not addressed set their SM2 bits and ignore the data bytes. SM2 has no effect in Mode 0 but can be used to check the validity of the stop bit in Mode 1. In a Mode 1 reception, if SM2 =1, the receive interrupt is not activated unless a valid stop bit is received. Serial Port Control Register The serial port control and status register is the Special Function Register SCaN, shown in Figure 15 .. This register contains the mode selection bits, the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits and RI). Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communicatiol)s. In these modes, 9 data bits are received, followed by a stop bit. The ninth bit goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt is activated only ifRB8 = 1. This feature is enabled by setting bit SM2 in SCON. 2-50 Al89 Series Hardware Description eTl AT89 Series Hardware Description Figure 14. Timer 2 in Auto-Reload Mode TIMER 2 INTERRUPT EXEN2 Figure 15. SCON: Serial Port Control Register (MSB) SMa (LSB) I SMt I SM2 I REN I TBS I RBS I TI I RI I Position Symbol Name and Significance SCON.7 SMa Serial port mode bit a (see table below). SCON.6 SMI Serial port mode bit 1 (see table below). SCON.5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RBS) is a. In Mode I, if SM2 = 1, then RI will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0. SCON.4 REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. SCON.3 TBS The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software. SCON.2 RBS In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. SCON.1 TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. SCON.a RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. Where SMO, SM1 specify the serial port mode, as follows: SMt Mode Description Baud Rate °° ° 1 0 0 t 2 shift register 8-bitUART 9-bitUART 1 t 3 9-bitUART fixed (f05c.l12) variable (set by timer) fixed (f05c.l64 or f05c.l32) variable (set by timer) SMO t AIIDEL 2-51 • j Baud Rates The baud rate in Mode 0 is fixed as shown in the following equation. _ Oscillator Frequency M d 0 B dR a e au ate 12 Figure 16lists commonly used baud rates and how they can be obtained from Timer 1. The baud rate in Mode 2 depends on the value of the SMOD bit in Special Function Register PCON. If SMOD = 0 (the value on reset), the baud rate is 1164 of the oscillator frequency. IfSMOD = I, the baud rate is 1/32 of the oscillator frequency, as shown in the following equation. Mode 2 BaudRate SMOD 2 =~ Programmers can achieve very low baud rates with Timer 1 by leaving the Timer I interrupt enabled, configuring the Timer to run as a 16-bit timer (high nibble ofTMOD = OooIB), and using the Timer I interrupt to do a 16-bit software reload. x (Oscillator Frequency In the AT89C51, the Timer 1 overflow rate determines the baud rates in Modes 1 and 3. In the AT89C52, these baud rates can be determined by Timer I, by Timer 2, or by both (one for transmit and the other for receive). Using Timer 1 to Generate Baud Rates When Timer 1 is the baud rate generator, the baud rates in Modes I and 3 are determined by the Timer 1 overflow rate and the value of SMOD according to the following equation. Modes 1,3 2SMOD . Baud Rate = x (TImer I Overflow Rate) -n The Timer I interrupt should be disabled in this application. The Timer itself can be configured for either timer or counter operation in any of its 3 running modes. In the most typical applications, it is configured for timer operation in auto-reload mode (high nibble of TMOD =OOlOB). In this case, the baud rate is given by the the following formula. Modes 1,3 2SMOD x Oscillator Frequency Baud Rate = 32 12x [256 - (THI)l Using Timer 2 to Generate Baud Rates In the AT89C52, setting TCLK and/or RCLK in nCON selects Timer 2 as the baud rate generator (Figure II). Under these conditions, the baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 17. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 reloads the Timer 2 registers with the 16-bit value in the RCAP2H and RCAP2L registers, which are preset by software. In this case, the baud rates in Modes I and 3 are determined by the Timer 2 overflow rate according to the following equation. Rate M a des, I 3 B au d Rate = Timer 2 Overflow 16 Timer 2 can be configured for either timer or counter operation. In the most typical applications, it is configured for timer operation (Cm = 0). Normally, a timer increments every machine cycle (thus at 1/12 the oscillator frequency), but timer operation is a different for Timer 2 when it is used as a baud rate generator. As a baud rate generator, Timer 2 increments every state time (thus at 112 the oscillator frequency). In this case, the baud rate is given by the following formula. Modes I, 3 Baud Rate = 32x Oscillator Frequency [65536 - (RCAP2H, RCAP2L)l where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Figure 16. Commonly Used Baud Rates Generated by Timer 1 Timer 1 Baud Rate fose SMOD err Mode Reload Value Mode 0 Max: 1 MHz 12 MHz X X X X Mode 2 Max: 375K 12 MHz 1 X X X Modes 1, 3: 62.5K 12 MHz 1 0 2 FFH 19.2K 11.059 MHz 1 0 2 FDH 2-52 9.6K 11.059 MHz 0 0 2 FDH 4.8K 11.059 MHz 0 0 2 FAH 2.4K 11.059 MHz 0 0 2 F4H 1.2K 11.059 MHz 0 0 2 E8H 137.5 11.986 MHz 0 0 2 1DH 110 6 MHz 0 0 2 72H 110 12 MHz 0 0 1 FEEBH AT89 Series Hardware Description AT89 Series Hardware Description Figure 17. Timer 2 in Baud Rate Generator Mode llMER1 OVERfLOW • RXClOCK lXClOCK llMER2 INTERAUPT T2EXPIN ElCE!II2 t NOTE: AVAlLABIUlY OF ADomONAL EXTERNAL INTERRUPT Figure 17 shows Timer 2 as a baud rate generator. This figure is valid only if RCLK + TCLK = 1 in TICON. A rollover in TH2 does not set TF2 and does not generate an interrupt. Therefore, the Timer 2 interrupt does not have to he disabled when Timer 2 is in the baud rate generator mode. If EXEN2 is set, a I-to-O transition in TIEX sets EXF2 but does not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is used as a baud rate generator, TIEX can be used as an extra external interrupt. = When Timer 2 is running (TR2 1) as a timer in the baud rate generator mode, programmers should not read from or write to TH2 or TL2. Under these conditions, Timer 2 is incremented every state time, and the results of a read or write may not be accurate. The RCAP registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. Tum Timer 2 off (clear TR2) before accessing the Timer 2 or RCAP registers, in this case. SEND transfers the output of the shift register to the alternate output function line of P3.0, and also transfers SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S I, and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift register are shifted one position to the right. As data bits shift out to the right, Os come in from the left. When the MSB of the data byte is at the output position of the shift register, the I that was initially loaded into the ninth position is just to the left of the MSB, and all positions to the left of that contain Os. This condition flags the TX Control block to do one last shift, then deactivate SEND and set TI. Both of these actions occur at SIPl of the tenth machine cycle after "write to SBUF." = = Reception is initiated by the condition REN 1 and Rl O. At S6P2 of the next machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next clock phase. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. The baud rate is fixed at 1112 the oscillator frequency. Figure 18 shows a simplified functional diagram of the serial port in Mode 0 and associated timing. RECEIVE enables SHIFT CLOCK to the alternate output function line ofP3.,. SHIFT CLOCK makes transitions at S3Pl and S6PI of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted one position to the left. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF' signal at S6P2 also loads a 1 into the ninth position of the transmit shift register and tells the TX Control block to begin a transmission. The internal timing is such that one full machine cycle will elapse between "write to SBUF' and activation of SEND. As data bits come in from the right, Is shift out to the left. When the 0 that was initially loaded into the right-most position arrives at the left-most position in the shift register, it flags the RX Control block to do one last shift and load SBUF. At SIPI of the 10th machine cycle after the write to sCaN that cleared RI, RECEIVE is cleared and RI is set. More About Mode 0 2·53 '.:.'" Figure 18. Serial Port Mode 0 WRI~ -_>---~1'---...-::_ _~;....-_--. II---rlf--- SBUF S6 RXD PS.OALT OlJTPUT FUNCTION ---1_---.. TXD P3.1 ALT OlJTPlJT FUNCTION '-----~ RX CLOCK REN--r--.... Ai --LJ--+j START RECEIVE RXCONTROL ~----~~~~-r~ RXD P3.0ALT INPUT FUNCTION AT89C51 INTERNAL BUS ALE ~WRITE TO SBUF SEND S6P2 L-- I S~HI~R~~~=;~n~~~n~~~n~~n~~~n~~~n~~~n~~~~==== RXD (OA fA 001) \ I TXD (SHIR CLOCK) t S6P1 tssP1 _______ __ ________ T~I ~ ________________ TRANSMIT ~~ --Il WRITE TO SCON (CLEAR RQ RTlL__ ~~ __ ~ ________ ~ ____________________ ~r---~ RECEIVE S~H~IR~~~_ _~nL__~nL__~nL__~nL_~~L__~nL__~~ RXD (DATA IN) ~~~~~~Jl6 27 =-=-=-=:-=-:-=-=~. TXD (SHIR CLOCK) 2-54 S5P2 AT89 Series Hardware Description •_ __ RECEIVE AT89 Series Hardware Description Figure 19. Serial Port Mode 1. TCLK, RCLK and Timer 2 are Present In the AT89C52 Only. TIMER 1 OVERFLOW TIMER 2 OVERFLOW • WRITE TO--~----~~----f __ r---~~~----l---lr~~ ~~ SBUF TXD TCI.K RXD TX CLOCK ---1JWAITE TO SBUF }- - - - - - - , SEND DATA "'S1P1 I SHIFT ~ STOP BIT I o ~m~ ________________________________________________ B ~r--- 2-55 More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (I). On receive, the stop bit goes into RB8 in SCON. In the AT89CS 1, the baud rate is determined by the Timer 1 overflow rate. In the AT89CS2 the baud rate is determined either by the Timer 1 overflow rate, the Timer 2 overflow rate, or both. In this case, one Timer is for transmit, and the other is for receive. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether or not the above conditions are met, the unit continues looking for a I-to-O transition in RXD. Figure 19 shows a simplified functional diagram of the serial port in Mode 1 and associated timings for transmit and receive. Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable ninth data bit, and a stop bit (1). On transmit, the ninth data bit (TB8) can be assigned the value of 0 or 1. On receive, the ninth data bit goes into RB8 in SCON. The baud rate is programmable to either 1132 or 1164 of the oscillator frequency in Mode 2. Mode 3 rnay have a variable baud rate generated from either Timer I or 2, depending on the state of TCLK and RCLK. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads a 1 into the ninth bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at SIPI of the machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal. The transmission begins when SEND is activated, which puts the start bit at TXD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, Os are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, the I that was initially loaded into the ninth position is just to the left of the MSB, and all positions to the left of that contain Os. This condition flags the TX Control unit to do one last shift, then deactivate SEND and set TI. This occurs at the tenth divide-by-16 rollover after "write to SBUF." Reception is initiated by a I-to-O transition detected at RXD. For this purpose, RXD is sampled at a rate of 16 times the established baud rate. When a transition is detected, the divide-by-16 counter is immediately reset, and IFFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the seventh, eighth, and ninth counter states of each bit time, the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done to reject noise. In order to reject false bits, if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another I-to-O transition. If the start bit is valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds. As data bits come in from the right, Is shift out to the left. When the start bit arrives at the leftmost position in the shift register, (which is a 9-bit register in mode I), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the following conditions are met at the time the final shift pulse is generated. More About Modes 2 and 3 Figures 20 and 21 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode I. The transmit portion differs from Mode I only in the ninth bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads TB8 into the ninth bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S IPI of the machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal. The transmission begins when SEND is activated, which puts the start bit at TXD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that. The first shift clocks a I (the stop bit) into the ninth bit position of the shift register. Thereafter, only Os are clocked in. Thus, as data bits shift out to the right, Os are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain Os. This condition flags the TX Control unit to do one last shift, then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after "write to SBUF." Reception is initiated by a I-to-O transition detected at RXD. For this purpose, RXD is sampled at a rate of 16 times the established baud rate. When a transition is detected, the divide-by-16 counter is immediately reset, and IFFH is written to the input shift register. I)RI=Oand 2) Either SM2 = 0, or the received stop bit = I 2-56 AT89 Series Hardware Description AT89 Series Hardware Description Figure 20. Serial Port Mode 2 TO~~---'------~I'---r~----~~----l-__-r~~__~~ • TXD PHASE 2 CLOCK (1/2 fosc) MODE 2 (SMOD IS PCON. 7) RXD 1)( ClOCK ---1JWRITE TO SBUF - - - - , mill DATA .... S1P1 I SHIFT TXD ] START BIT STOPBITGEN }BIT ~R~I ________________________________________________ ~r--- 2-57 Figure 21. Serial Port Mode 3. TCLK, RCLK, and Timer 2 are Present in AT89C52 only TIMER 1 TIMER 2 OVERFLOW OVERFLOW WRITE TO--~----~~--~ r---~~~--~---lr-\---~~ SBUF TXD TCLK· RI LOAO- SBUF SHIFT - - - - - - - - - - - , 1FFH RXD TJ( CLOCK --1JWRITE TO SBUF - - - , SEND DATA ""S1P1 I SHIFT BIT ~------------------------------------------~,-- 2-58 AT89 Series Hardware Description AT89 Series Hardware Description At the seventh, eighth and ninth counter states of each bit time, the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another I-to-O transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds. Figure 22. Interrupt Sources INTO As data bits come in from the right, Is shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the following conditions are met at the time the final shift pulse is generated: wo----------------~~ INTERRUPT SOURCES W1 ----------------~~ I)RI=O,and 2) Either SM2 = 0 or the received 9th data bit = I If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received ninth data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit continues looking for a I-to-O transition at the RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, orR!. W2~ EXF2~"" (AT89C52 ONLy) All of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated and pending interrupts can be canceled in software. Interrupts The AT89C51 provides 5 interrupt sources: two external interrupts, two timer interrupts, and a serial port interrupt. The AT89C52 provides 6 with the extra timer. These are shown in Figure 22. The External Interrupts INTO and INTI can each be either levelactivated or transition-activated, depending on bits ITO and ITI in Register TCON. The flags that actually generate these interrupts are the lEO and lEI bits in TCON. When the service routine is vectored to, hardware clears the flag that generated an external interrupt only if the interrupt was transition-activated. If the interrupt was level-activated, then the external requesting source (rather than the on-chip hardware) controls the request flag. The Timer 0 and Timer I Interrupts are generated by TFO and TFI, which are set by a rollover in their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is generated, the on-chip hardware clears the flag that generated it when the service routine is vectored to. The Serial Port Interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine normally must determine whether RI or TI generated the interrupt, and the bit must be cleared in software. In the AT89C52, the Timer 2 Interrupt is generated by the logic cal OR of TF2 and EXF2. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether TF2 or EXF2 generated the interrupt, and the bit must be cleared in software. Figure 23. IE: Interrupt Enable Register (LSB) IET2 I ES IET1 IEX1 IETO IEXO I Enable bit = 1 enables the interrupt. Enable bit = 0 disables it. Symbol Position Function EA IE.7 Global enable/disable. disables all interrupts. If EA = 0, no interrupt will be 1, each interrupt acknowledged. If EA source is individually enabled or disabled by setting or clearing its enable bit. = ET2 1E.6 Undefined/reserved. IE.5 Timer 2 interrupt enable bit. (AT89C52) ES IE.4 Serial Port interrupt enable bit. ET1 1E.3 Timer 1 interrupt enable bit. EX1 IE.2 External Interrupt 1 enable bit. ETO IE.1 Timer 0 interrupt enable bit. EXO IE.O External interrupt 0 enable bit. User software should never write 1s to unimplemented bits, since they may be used in future AT89 Series products. 2-59 Figure 24. IP: Interrupt Priority Register (MSB) 1- 1Priority bit assigns priority. (LSB) 1~1~lml~I~I~1 = 1 high Priority bit = 0 assigns low priority. Symbol Position be interrupted by a high-priority interrupt but not by another low-priority interrupt. A high-priority interrupt can not be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously. the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence, as follows. Function 1. 2. 3. IP.7 reserved IP.6 reserved PT2 IP.5 Timer 2 interrupt priority bit. PS IP.4 Serial Port interrupt priority bn. Timer 1 interrupt priority bit. PT1 IP.3 PX1 IP.2 External Interrupt 1 priority bit. PTO IP.1 Timer 0 interrupt priority bit. PXO IP.O External interrupt 0 priority bit. User software should never write 1s to unimplemented bits. since they may be used in future products. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE (interrupt enable) at address OA8H. As well as individual enable bits for each interrupt source. there is a global enable/disable bit that is cleared to disable all interrupts or set to turn on interrupts (see Figure 23). Figure 23 shows that bit position IE.6 is unimplemented. In the AT89C51. bit position IE.5 is also unimplemented. User software should not write Is to these bit positions. since they may be used in future microcontrollers. Priority Level Structure Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in Special Function Register IP (interrupt priority) at address OB8H (Figure 24). IP is cleared after a system reset to place all interrupts at the lower priority level by default. A low-priority interrupt can Source IEO TFO lEI Priority Within Level (highest) 4. TFI 5. RI+TI (lowest) 6. 1F2+EXF2 Note that the "priority within level" structure is only used to resolve simultaneous requests of the same priority level. The IP register contains a number of unimplemented bits. IP.7 and IP.6 are vacant in the AT89C52, and in the AT89C51 these bits and IP.5 are vacant. User software should not write Is to these bit positions, since they may be used in future products. How Interrupts Are Handled The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. The AT89C52 Timer 2 interrupt cycle is different, as described in the Response Time Section. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware generated LCALL is not blocked by any of the following conditions. I. An interrupt of equal or higher priority level is already in progress. 2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress. 3. The instruction in progress is RETI or any write to the IE or IP registers. Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress will be completed before vectoring to Figure 25. Interrupt Response Timing Diagram INTERRUPT GOES ACTIVE INTERRUPT LATCHED INTERRUPTS ARE POLLED LONG CALL TO INTERRUPT VECTOR ADDRESS INTERRUPT ROUTINE This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP. 2-60 ATS9 Series Hardware Description AT89 Series Hardware Description any service routine. Condition 3 ensures that if the instruction in progress is RET! or any access to IE or IP, then at least one more instruction will be executed before any interrupt is vectored to. The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. If an active interrupt flag is not being serviced because of one of the above conditions and is not still active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new. The polling cycle/LCALL sequence is illustrated in Figure 25. Note that if an interrupt of higher priority level goes active prior to S5P2 of the machine cycle labeled C3 in Figure 25, then in accordance with the above rules it will be serviced during C5 and C6, without any instruction of the lower priority routine having been executed. Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases it does not. It never clears the Serial Port or Timer 2 flags. This must be done in the user's software. The processor clears an external interrupt flag (lEO or IEI) only ifit was transition-activated. The hardware-generated LCALL pushes the contents of the Program Counter onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being serviced, as shown in the following table. Interrupt Source ExtemalO lEO Vector Address 0OO3H Timer 0 TFO OOOBH Extemall lEI 0013H Timer 1 TFI 00lBH Serial Port RlorTI 0023H Timer 2 TF2orEXF2 002BH System Reset RST OOOOH NOTE: When vectoring to an interrupt the flag that caused the interrupt is automatically cleared by hardware. The exceptions are RI and 11 for serial port interrupts, and TF2 and EXF2 for Timer 2 interrupts. Since there are two possible sources for each of these interrupts, it is not practical for the CPU to clear the interrupt flag. These bits must be tested in the ISR to detennine the source of the interrupt, and then the interrupting flag is cleared by software. Execution proceeds from that location until the RET! instruction is encountered. The RET! instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Execution of the interrupted program continues from where it left off. Note that a simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress. Interrupt Flag Bits Interrupt Flag SFR Register and Bit Position External 0 lEO TCON.l Extemall lEI TCON.3 Timer 1 TFI TCON.7 Timer 0 TFO TCON.5 Serial port TI SCON.l Serial port RI SCON.O Timer 2 TF2 T2CON.7 (AT89C52) Timer 2 EXF2 T2CON.6 (AT89C52) When an interrupt is accepted the following action occurs: 1. The current instruction completes operation. 2. The PC is saved on the stack. 3. The current interrupt status is saved internally. 4. Interrupts are blocked at the level of the interrupts. 5. The PC is loaded with the vector address of the ISR (interrupt service routine). 6. The ISR executes. The ISR executes and takes action in response to the interrupt. The ISR finishes with RET! (return from interrupt) instruction. This retrieves the old value of the PC from the stack and restores the old interrupt status. Execution of the main program continues where it left off. External Interrupts The external sources can be programmed to be level-activated or transition-activated by setting or clearing bit ITI or ITO in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx I, external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit lEx then requests the interrupt. = Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. If the external interrupt is transitionactivated, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle to ensure that the transition is seen so that interrupt request flag lEx will be set. IEx will be automatically cleared by the CPU when the service routine is called. If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then the external source must deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. 2·61 Response Time The INTO and INTI levels are inverted and latched into the interrupt flags lEO and lEI at SSP2 of every machine cycle. Similarly, the Timer 2 flag EXF2 and the Serial Port flags RI and TI are set at SSP2. The values are not actually polled by the circuitry until the next machine cycle. The Timer 0 and Timer I flags, 1F0 and 1FI, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag TF2 is set at S2P2 and is polled in the same cycle in which the timer overflows. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapsed between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 25 shows interrupt response timings. A longer response time results if the request is blocked by one of the 3 previously listed conditions. If an interrupt of equal or higher priority level is already in progress, the additional wait time depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles, since the longest instructions (MUL and DIV) are only 4 cycles long. If the instruction in progress is RETI or an access to IE or !P, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is MUL orDIV). Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 9 cycles. Single-Step Operation The AT89CSI interrupt structure allows single-step execution with very little software overhead. As previously noted, an interrupt request will not be serviced while an interrupt of equal priority level is still in progress, nor will it be serviced after RETI until at least one other instruction has been executed. Thus, once an interrupt routine has been entered, it cannot be re-entered until at least one instruction of the interrupted program is executed. One way to use this feature for single-stop operation is to program one of the external interrupts (for example, INTO) to be level-activated. The service routine for the interrupt will terminate with the following code. JNB P3.2,$ ;Wait Here TilIlNTO Goes High JB P3.2,$ ;Now Wait Here Till it Goes Low RETI ;Go Back and Execute One Instruction If the INTO pin, which is also the P3.2 pin, is held normally low, the CPU will go right into the External Interrupt 0 routine and stay there until INTO is pulsed (from low to high to low). Then it will execute RETI, go back to the task program, execute one instruction, and immediately reenter the External Interrupt 0 routine to await the next pulsing of P3.2. One step of the task program is executed each time P3.2 is pulsed. Reset The reset input is the RST pin, which is the input to a Schmitt Trigger. A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. The CPU responds by generating an internal reset, with the timing shown in Figure 26. The external reset signal is asynchronous to the internal clock. The RST pin is sampled during State 5 Phase 2 of every machine cycle. The port pins will maintain their current activities for 19 oscillator periods after a logic I has been sampled at the RST pin; that is, for 19 to 31 oscillator periods after the external reset signal has been applied to the RST pin. While the RST pin is high, ALE and PSEN are weakly pulled high. After RST is pulled low, it will take I to 2 machine cycles for ALE and PSEN to start clocking. For this reason, other devices can Iiot be synchronized to the internal timings of the AT89CS1. Driving the ALE and PSEN pins to 0 while reset is active could cause the device to go into an indeterminate state. The internal reset algorithm writes Os to all the SFRs except the port latches, the Stack Pointer, and SBUF. The port latches are initialized to FFH, the Stack Pointer to 07H, and SBUF is indeterminate. Table 3 lists the SFRs and their reset values. The internal RAM is not affected by reset. On power-up the RAM content is indeterminate. Note: There is no internal pulldown reset pin on NMOS devices, unlike that of Atmel's CMOS microcontroller devices. 2·62 AT89 Series Hardware Description AT89 Series Hardware Description Figure 26. Reset Timing ----+I ~ 12 OSC. PERIODS I~I~I~I~I~I~I~I~I Sl RST: 11111111111:h-' I S2 I S3 I S4 I S5 I S6 I Sl I S2 I S3 I S4 I r ....,J SAMPLe: RST INTERNAL RESET SIGNAL I SAMFLE RST . ALE: PsEN: po: I ; . - - 11 OSC. PERIODS -"~"":41------ Power-On Reset I 19 OSC. PERIODS -----+!~: Figure 27. Power-On Reset Circuit For CMOS devices, the external resistor can be removed because the RST pin has an internal pulldown. The capacitor value can then be reduced to I IiF in Figure 27. Vcc When power is turned on, the circuit holds the RST pin high for an amount of time that depends on the capacitor value and the rate at which it charges. To ensure a valid reset, the RST pin must be held high long enough to allow the oscillator to start up plus two machine cycles. Vee AT89C51 RST On power-up, Vee should rise within approximately 10 ms. The oscillator start-up time depends on the oscillator frequency. For a 10 MHz crystal, the start-up time is typically I ms. For a I MHz crystal, the start-up time is typically 10 ms. With the given circuit, reducing Vee quickly to 0 causes the RST pin voltage to momentarily fall below 0 V. However, this voltage is internally limited and will not harm the device. Note: The port pins will be in a random state until the oscillator has started and the internal reset algorithm has written I s to them. Powering up the device without a valid reset could cause the CPU to start executing instructions from an indeterminate location. This is because the SFRs, specifically the Program Counter, may not get properly initialized. 8.2Kn Power-Saving Modes of Operation The Atmel Microcontrollers have two power-reducing modes, Idle and Power Down. The input through which backup power is supplied during these operations is Vee. Figure 28 shows the internal circuitry which implements these features. In the Idle mode (IDL I), the oscillator continues to run and the Interrupt, Serial Port, and Timer blocks continue to be clocked, but the clock signal is gated off to the CPU. In Power Down (PD I), the oscillator is frozen. The Idle and Power Down modes are activated by setting bits in Special Function Register peON. The address of this register is 87H. Figure 29 details its contents. AlmEl = = 2-63 Table 3. Reset Values of the SFRs SFRName PC ACC B PSW SP DPTR PO·P3 IP (AT89C51) IP (AT89C52) IE (AT89C51) IE (AT89C52) TMOD T2MOD (AT89C52) TCON T2CON (AT89C52) THO TLO THI TL1 TH2 (AT89C52) TL2 (AT89C52) RCAP2H (AT89C52) RCAP2L (AT89C52) SCON SBUF PCON (CHMOS) Reset Value OOOOH OOH OOH OOH 07H OOOOH FFH XXXOOOOOB XXOOOOOOB OXXOOOOOB OXOOOOOOB OOH XXXXXXOOB OOH OOH OOH OOH OOH OOH OOH OOH OOH OOH OOH Indeterminate OXXXOOOOB Idle Mode An instruction that sets PCON.O is the last instruction executed before the Idle mode begins. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the Interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.O to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RET! the next instruction to be executed will be the one following the instruction that put the device into Idle. The flag bits GFO and GFI can be used to indicate whether an interrupt occurred during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset must be held active for only two machine cycles (24 oscillator periods) to complete the reset. 2-64 The signal at the RST pin clears the IDL bit directly and asynchronously. At this time, the CPU resumes program execution from where it left off; that is, at the instruction following the one that invoked the Idle Mode. As shown in Figure 26, two or three machine cycles of program execution may take place before the internal reset algorithm takes control. On-chip hardware inhibits access to the internal RAM during this time, but access to the port pins is not inhibited. To eliminate the possibility of unexpected outputs at the port pins, the instruction following the one that invokes Idle should not write to a port pin or to external data RAM. Figure 28. Idle and Power-Down Hardware ~D~ ~ XTAL2 XTAL 1 Figure 29. PCON Power Control Register (LSB) (MSB) I GFI I GFO I PO IIDL I ISMODI Symbol Position Function SMOD PCON.7 Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rate, and the Serial Port is used in modes I, 2, or 3. PCON.6 (Reserved) PCON.5 . (Reserved) PCON.4 (Reserved) GFI PCON.3 General-purpose flag bit. GFO PCON.2 General-purpose flag bit. PO PCON.l Power Down bit. Setting this bit activates power down operation. IDL PCON.O Idle mode bit. Setting this bit activates idle mode operation. " 1s are written to PO and IDL at the same time, PO takes precedence. The reset value of PCON is (OXXXOOO). User software should never write 1s to unimplemented bits, since they may be used in future products. AT89 Series Hardware Description AT89 Series Hardware Description Table 4. Flash AT89C51 and AT89C52 Device Name Flash Bytes CktType VPP ATB9C51 4K CMOS 12 V 6 seconds ATB9C52 BK CMOS 12V 12 seconds Power Down Mode An instruction that sets PCON 1 is the last instruction executed before Power Down mode begins. In the Power Down mode, the on-chip oscillator stops. With the clock frozen, all functions are stopped, but the on-chip RAM and Special Function Registers are held. The port pins output the values held by their respective SFRs. ALE and PSEN output lows. The only exit from Power Down for the AT89CC51 is a hardware reset. Reset redefines all the SFRs but does not change the on-chip RAM. In the Power Down mode of operation, Vee can be reduced to as low as 2V. However, Vee must not be reduced before the Power Down mode is invoked, and Vee must be restored to its normal operating level before the Power Down mode is terminated. The reset that terminates Power Down also frees the oscillator. The reset should not be activated before Vee is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (normally less than 10 msec). Programming The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. A list of programming companies that support Atmel's products can be found on the Atmel Bulletin Board and in the Microcontroller Programmer Support section of this Data Book. To access the bulletin board, dial 408-436-4309. Time Required to Program Entire Array TheAT89C51/52 programs at VPP =12 V using one 100-msec PROG pulse per byte programmed. This results in a programming time of approximately 1.5 msec per byte, for a total programming time of6 sec for the 4 Kbyte device and 12 sec for the 8Kbyte device. Detailed procedures for programming and verifying each device are given in the data sheets. Program Memory Locks In some microcontroller applications, the program memory must be secure from software piracy. Atmel has responded to this need by implementing a program memory locking scheme in all of its devices. While it is impossible for anyone to guarantee absolute security against all levels of technological sophistication, the program memory locks present a substantial harrier against illegal readout of protected software. The procedure for programming the lock bits is detailed in the data sheets. Table 5 lists the Lock Bits and their corresponding effects on the microcontroller. Erasing the Flash also erases the Lock Bits, returning the microcontroller to full functionality. 2-65 Table 5. Program Lock Bits and Their Features Program Lock Bits Mode LB1 LB2 LB3 Protection Type 1 U U U No program lock features enabled. 2 p U U MOVC instructions executed fmm external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled. 3 p P U Same as 2, also verify is disabled. 4 p P P Same as 3, also external execution is disabled. P = Programmed U = Unprogrammed Any other combination of the;Lock Bits is not defined. Table 6. Program Protection Device Lock Bits AT89C51 AT89C52 AT89C2051 AT89C1051 LB1,LB2,LB3 LB1,LB2,LB3 LB1,LB2 LB1,LB2 While the device is in ONCE mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. A reset restores normal operation. On-Chip Oscillators The crystal specifications and capacitance values (C I and C2 in Figure 30) are not critical. 30 pF can be used in these positions at any frequency with good quality crystals. A ceramic resonator can be used in place of the crystal in cost-sensitive applications. When a ceramic resonator is used, C I and C2 are normally selected to be of somewhat higher values, typically, 47 pF. The manufacturer of the ceramic resonator should be consulted for recommendations on the values of these capacitors. In general, crystals used with these devices typically have the following specifications. ESR (Equivalent Series Resistance) see Figure 31 Co (Shunt Capacitance) 7.0 pF max. CL (Load Capacitance) 30pF+3pF Drive Level ImW Frequency, tolerance and temperature range are determined by the system requirements. Figure 30. Using the On-Chip Oscillator VCC TO INTERNAL TIMINGCKTS When Lock Bit I is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly. XTAL2---~....,--- QUART CRYSTAL OR CERAMIC RESONATOR oNce™ Mode The ONCE ("on-circuit emulation") mode facilitates testing and debugging of systems using the device without requiring the device to be removed from the circuit. The ONCE mode is invoked by taking the following steps. Figure 31. ESR versus Frequency I. Pull ALE low while the device is in reset and PSEN is high; 500 2. Hold ALE low as RST is deactivated. (J) '::;0'" .5 a: In 400 300 200 100 12 16 CRYSTAL FREQUENCY in MHz 2-66 AlB9 Series Hardware Description AT89 Series Hardware Description The on-chip oscillator circuitry shown in Figure 32, consists of a single stage linear inverter intended for use as a crystal-controlled, positive reactance oscillator. To drive the parts with an external clock source, apply the external clock signal to XTALl, and leave XTAL2 floating, as shown in Figure 33. Figure 32. On-Chip Oscillator Circuitry for the AT89C5l VCC TO INTERNAL TIMINGCKTS 01 4000 Rt XTAL1 XTAL2 r 02 Note: In Atmel's CMOS microcontrollers the Oscillator Specification differs from that in NMOS versions. 2-67 Figure 33. Using an External Clock Source Internal Timing AT89 NC EXTERNAL OSCILLATOR SIGNAL XTAL2 ~---lXTALl CMOS GATE Figures 34 through 37 show the various strobe and port signals being clocked internally. The figures do not show rise and fall times of the signals, nor do they show propagation delays between the XTAL signal and events at other pins. Rise and fall times are dependent on the external loading that each pin must drive. They are often taken to be about 10 ns, measured between 0.8 V and 2.0 V. Propagation delays are different for different pins. For a given pin the delays vary with pin loading, temperature, V cc, and manufacturing lot. If the XTAL waveform is taken as the timing reference, propagation delays may vary from 25 to 125 ns. The AC Timings section of the data sheets do not reference any timing to the XTAL waveform. Rather, they relate the critical edges of control and input signals to each other. The timings published in the data sheet include the effects of propagation delays under the specified test conditions. 2-68 AT89 Series Hardware Description AT89 Series Hardware Description Figure 34. External Program Memory Fetches I I STATE 1 STATE 21 STATE 31 STATE 41 STATE 51 STATE 61 STATE 11 STATE 21 P11P2 P11P2 P11P2 P11P2 P11P2 P11P2 P11P2 P11P2 • XTAL: ALE: PSEN: PO: P2: PCHOUT PCHOUT PCHOUT Figure 35. External Data Memory Read Cycle I STATE 41 STATE 51 STATE 61STATE 11 STATE 21 STATE 31 STATE 41 STATE 51 P11P2 P11P2 P11P2 P1iP2 P11P2 P11P2 P1iP2 P11P2 XTAL: ALE: RD: po: P2: PCHOR P2SFR 2-69 Figure 36. External Data Memory Write Cycle I ~E~~E~~E~~ElIS~21~E~S~~S~~ Pl1p21pl1p21pl1p21plIP2 Pl1p2 Pl1p21pl1p21pl1p21 XTAL: ALE: WR: po: P2: ----f! DP~3f PCLOUTIF PROGRAM MEMORY §SEXTERNAL RI ! PCHOR P2SFR ~~! DATA OUT ~ PCHOR P2SFR DPH OR P2 SFR OUT Figure 37. Port Operation STATE 41 STATE 51STATE SISTATE 1 ISTATE 21 STATE 31 STATE 41 STATE 51 I Pl1p2 Pl1p2 Pl1p2 Pl1p2 Pl1p2 Pl1p2 Pl1p2 Pl1p2 XTAL: ~ INPUTS SAMPLED: MOV PORT, SRC: ~ ~ po, PI, P2, P3 ~ PO, PI, P2, P3 ~RST ~RST NEW DATA OLD DATA SERIAL PORT SHIFT CLOCK (MODE 0) ---+-I 2-70 ~ RXD PIN SAMPLED RXD SAMPLED AT89 Series Hardware Description ---+-I ~ Instruction Set Microcontroller Instruction Set For interrupt response time information, refer to the hardware description chapter. Instructions that Affect Flag Settings(1) Instruction Flag Instruction Flag C OV AC C ADD X X X CLRC 0 ADDC X X X CPLC X SUBB X X X ANL C,bit X MUL 0 X ANL C,ibit X DIV 0 X ORLC,bit X DA X ORLC, bit X RRC X MOVC,bit X RLC X CJNE X SETBC 1 Note OV AC Instruction Set 1. Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or bits in the PSW) also affect !Jag settings. The Instruction Set and Addressing Modes Rn Register R7-RO of the currently selected Register Bank. direct B-blt intemal data location's address. This could be an Internal Data RAM location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (12B-255)]. @RI B-bit intemal data RAM location (0-255) addressed indirectly through register Rl or RD. #data B-bit constant included in instruction. #data 16 16-blt constant included in instruction. addr16 16-bit destination address. Used by lCAll and WMP. A branch can be anywhere within the 64 Kbyte Program Memory address space. addr 11 ll-bit destination address. Used by ACAll and AJMP. The branch will be within the same 2 Kbyte page of program memory as the first byte of the following instruction. rei Signed (two's complement) B-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. bit Direct Addressed bit in Intemal Data RAM or Special Function Register. OS09A 2-71 Instruction Set Summary 0 1 2 3 4 S 6 NOP JB bit, rei [3B,2C] JNB 0 JBC bit,rel [3B,2Cl [:bit, re~1 3B,2C JC rei [2B,2C] JNC rei [2B,2C] JZ rei [2B 2C] 7 JNZ rei [2B,2C] 1 AJMP (PO) [2B,2C] ACALL (PO) [2B,2C] AJMP (P1) [2B 2C] ACALL (P1) [2B 2C] AJMP (P2) [2B 2C] ACALL (P2) [2B,2C] AJMP (P3) [2B,2C] ACALL (P3) [2B,2C] 2 LJMP addr16 [3B,2C] LCALL addr16 [3B 2C] RET [2C] RETI [2C] ANL dir,A [2B] XRL dir, a [2B] ORL C,bit [2B,2C] 3 RR A RRC A RL A RLC A ORL dir,A [2B] ORL dir, #data [3B 2C] ANL dir, #data [3B 2C] XRL dir, #data [3B 2C] JMP @A+DPTR [2C] 4 INC A DEC A ADD A, #data '[2BI ADDC A, #data '[2Bl ORL A, #data '[2B] ANL A, #data '[2BI XRL A, #data '[2B] MOV A, #data '[2B] S INC dir [2B] DEC dir [2B] ADD A,dir [2B] ADDC A,dir [2B] ORL A,dir [2B] ANL A,dir [2B] XRL A,dir [2B] MOV dir, #data [3B,2C] 6 INC @RO DEC @RO ADD A,@RO AD DC A,@RO ORL A,@RO ANL A,@RO XRL A,@RO MOV @RO, @data [2B] 7 INC @R1 DEC @R1 ADD A,@R1 AD DC A,@R1 ORL A,@R1 ANL A,@R1 XRL A,@R1 8 INC RO DEC RO ADD A,RO ADDC A,RO ORL A,RO ANL A,RO XRL A,RO 9 INC R1 DEC R1 ADD A, R1 ADDC A,R1 ORL A, R1 ANL A,R1 XRL A,R1 MOV R1, #data [2Bl A INC R2 DEC R2 ADD A,R2 ADDC A,R2 ORL A,R2 ANL A,R2 XRL A,R2 MOV R2, #data [2B] B INC R3 DEC R3 ADD A,R3 ADDC A,R3 ORL A,R3 ANL A,R3 XRL A,R3 MOV R3, #data [2B] C INC R4 DEC R4 ADD A,R4 ADDC A,R4 ORL A,R4 ANL A,R4 XRL A,R4 MOV R4, #data [2B] D INC RS DEC RS ADD A,RS ADDC A,RS ORL A,R5 ANL A,RS XRL A,R5 MOV RS, #data [2BI E INC R6 DEC R6 ADD A,R6 ADDC A,R6 ORL A,R6 ANL A,R6 XRL A,R6 MOV R6, #data [2B] F INC R7 DEC R7 ADD A,R7 ADDC A,R7 ORL A,R7 ANL A,R7 XRL A,R7 MOV R7, #data [2B] Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/l cycle 2·72 Instruction Set MOV @R1,#data [2BI MOV RO, #data [2B] Instruction Set Instruction Set Summary (Continued) 8 9 A B C 0 E F 0 SJMP REL [2B,2C] MOV DPTR,# data 1S [3B,2C] ORL C, ibi1 [2B,2C] ANL C,ibi1 [2B,2C] PUSH dir [2B,2C] POP dir [2B,2C] MOVXA, @DPTR [2C] MOVX @DPTR,A [2C] 1 AJMP (P4) [2B,2C] ACALL (P4) [2B,2C] AJMP (PS) [2B,2C] ACALL (PS) [2B,2C] AJMP (P6) [2B,2C] ACALL (PS) [2B,2C] AJMP (P7) [2B,2C] ACALL (P7) [2B,2C] 2 ANL C, bit [2B,2C] MOV bit, C [2B,2C] MOV C, bit [2B] CPL bit [2B] CLR bit [2B] SETB bit [2B] MOVX A,@RO [2C] MOVX wRO,A [2C] 3 MOVCA, @A+PC [2C] MOVCA, @A+DPTR [2C] INC DPTR [2C] CPL C CLR C SETB C MOVX A,@RI [2C] MOVX @RI,A [2C] 4 DIV AB [2B,4C] SUBB A, #data [2B] MUL AB [4C] CJNEA, #data, rei [38,2C] SWAP A DA A CLR A CPL A S MOV dir, dir [3B,2C] SUBB A,dir [2B] CJNE A,dir, rei [3B,2C] XCH A,dir [2B] DJNZ dir, rei [3B,2C] MOV A,dir [2B] MOV dir,A [2B] S MOV dir, @RO [2B,2C] SUBB A,@RO MOV @RO,dir [2B,2C] CJNE @RO,#data, rei [3B,2C] XCH A,@RO XCHD A,@RO MOV A,@RO MOV @RO,A 7 MOV dir,@R1 [2B,2C] SUBB A,@R1 MOV @R1,dir [2B,2C] CJNE @R1,#data, rei [3B,2C] XCH A,@R1 XCHD A,@R1 MOV A,@R1 MOV @R1,A 8 MOV dir, RO [2B,2C] SUBB A,RO MOV RO,dir [28,2C] CJNE RO, #data, rei [3B,2C] XCH A,RO DJNZ RO, rei [2B,2C] MOV A,RO MOV RO,A 9 MOV dir, R1 [2B,2C] SUBB A,R1 MOV R1,dir [2B,2C] CJNE R1, #data, rei [3B,2C] XCH A,R1 DJNZ R1, rei [2B,2C] MOV A,R1 MOV R1,A A MOV dir, R2 [2B,2C] SUBB A,R2 MOV R2,dir [2B,2C] CJNE R2, IIdata, rei [3B,2C] XCH A,R2 DJNZ R2, rei [2B,2C] MOV A,R2 MOV R2,A B MOV dir, R3 [2B,2C] SUBB A,R3 MOV R3,dir [2B,2C] CJNE R3, #data, rei [3B,2C] XCH A,R3 DJNZ R3, rei [2B,2C] MOV A,R3 MOV R3,A C MOV dir, R4 [2B,2C] SUBB A,R4 MOV R4,dir [2B,2C] CJNE R4, #data, rei [3B,2C] XCH A,R4 DJNZ R4, rei [2B,2C] MOV A,R4 MOV R4,A 0 MOV dir, RS [2B,2C] SUBB A,RS MOV RS,dir [2B,2C] CJNE RS, #data, rei [3B,2C] XCH A,RS DJNZ RS, rei [2B,2C] MOV A,RS MOV RS,A E MOV dir, RS [2B,2C] SUBB A,RS MOV RS, dir [2B,2C] CJNE RS, #data, rei [3B,2C] XCH A,RS DJNZ RS, rei [2B,2C] MOV A,R6 MOV RS.A F MOV dir, R7 [2B,2C] SUBB A,R7 MOV R7,dir [2B,2C] CJNE R7, #data, rei [3B,2C] XCH A,R7 DJNZ R7, rei [2B,2C] MOV A.R7 MOV R7.A Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = I byte/l cycle AlmEl 2-73 AlmEl Table 1. AT89 Instruction Set Summary(l) Mnemonic Description Byte Oscillator Period ARITHMETIC OPERATIONS A,Rn Add register 10 Accumulator 1 12 ADD A,direct Add direct byte to Accumulator 2 12 A,@Ri ADD A,#data ADDC A,Rn Add indirect RAM to Accumulator 1 12 Add immediate data to Accumulator 2 12 Add register to Accumulator with Carry 1 1 24 MUL AB Multiply A & B 1 48 DIV AB Divide A by B 1 48 DA A Decimal Adjust Accumulator 1 12 LOGICAL OPERATIONS 12 ANL A,direct AND direct byte to Accumulator 2 12 ANL A,@Ri AND indirect RAM to Accumulator 1 12 ANL A,#data AND immediate data to Accumulator 2 12 ANL direct,A AN D Accumulator to direct byte 2 12 ANL direct,#data AND immediate data to direct byte 3 24 ORL A,Rn OR register to Accumulator 1 12 ORL A,direct OR direct byte to Accumulator 2 12 ORL A,@Ri OR indirect RAM to Accumulator 1 12 ORL A,#data OR immediate data to Accumulator 2 12 ORL direct,A OR Accumulator to direct byte 2 12 12 ORL direct,#data OR immediate data to direct byte 3 24 XRL A,Rn Exclusive-OR register to Accumulator 1 12 XRL A,direct Exclusive-OR direct byte to Accumulator 2 12 XRL A,@Ri Exclusive-OR indirect RAM to Accumulator 1 12 XRL A,#data Exclusive-OR immediate data to Accumulator 2 12 AD DC A,@Ri Add indirect RAM to Accumulator with Carry 1 12 ADDC A,#data Add immediate data to Ace with Carry 2 12 SUBB A,Rn Subtract Register from Ace with borrow 1 12 SUBB A,direct Subtract direct byte from Ace with borrow 2 12 SUBB A,@Ri Subtract indirect RAMfromACC with borrow 1 12 SUBB A,#data Subtract immediate data from Ace with borrow 2 12 Increment Accumulator 1 INC Rn Increment register 1 12 INC direct Increment direct byte 2 12 INC @Ri Increment direct RAM 1 12 DEC A Decrement Accumulator 1 12 DEC Rn Decrement Register 1 12 DEC direct Decrement direct byte 2 12 DEC @Ri Decrement indirect RAM 1 12 Instruction Set Increment Data Pointer 1 12 l. All mnemonics copyrighted © Intel Corp., 1980. DPTR AND Register to Accumulator 2 2-74 Oscillator Period A,Rn Add direct byte to Accumulator with Carry Note: INC 12 A,direct A Byte ANL ADDC INC Description ARITHMETIC OPERATIONS (continued) ADD ADD Mnemonic Instruction Set Table I, AT89 Instruction Set Summary (continued) Mnemonic Description Byte Oscillator Period LOGICAL OPERATIONS (continued) direct,A Exclusive,OR Accumulator to direct byte 2 12 XRL direct,#data Exclusive-OR immediate data to direct byte 3 24 CLR A Clear Accumulator 1 12 CPL A Complement Accumulator 1 12 RL A Rotate Accumulator Left 1 12 RLC A Rotate Accumulator Left through the Carry 1 RR A Rotate Accumulator Right RRC A Oscillator Period direct,@Ri Move indirect RAM to direct byte 2 24 MOV direct,#data Move immediate data to direct byte 3 24 MOV @Ri,A Move Accumulator to indirect RAM 1 12 MOV @Ri,direct Move direct byte to indirect RAM 2 24 MOV @Ri,#data Move immediate data to indirect RAM 2 12 12 MOV DPTR,#data16 Load Data Pointer with a 16-bit constant 3 24 1 12 MOVC A,@A+DPTR 1 24 Rotate Accumulator Right through the Carry 1 12 Move Code byte relative to DPTR toAcc MOVC A,@A+PC 1 24 Swap nibbles within the Accumulator 1 Move Code byte relative to PC to Acc MOVX A,@Ri Move External RAM (B-bit addr) toAcc 1 24 MOVX A,@DPTR Move Exemal RAM (16-bit addr) toAcc 1 24 MOVX @Ri,A Move Acc to External RAM (Bbitaddr) 1 24 MOVX @DPTR,A Move Aceto External RAM (16bitaddr) 1 24 PUSH direct Push direct byte onto stack 2 24 12 MOV A,Rn Move register to Accumulator 1 12 MOV A,direct Move direct byte to Accumulator 2 12 MOV A,@Ri Move indirect RAM to Accumulator 1 12 Move immediate data to Accumulator 2 A,#data Byte MOV DATA TRANSFER MOV Description DATA TRANSFER (continued) XRL SWAP A Mnemonic 12 MOV Rn,A Move Accumulator to register 1 12 POP direct Pop direct byte from stack 2 24 MOV Rn,direct Move direct byte to register 2 24 XCH A,Rn Exchange register with Accumulator 1 12 MOV Rn,#data Move immediate data to register 2 12 XCH A,direct 2 12 MOV direct,A Move Accumulator to direct byte 2 12 Exchange direct byte with Accumulator XCH A,@Ri 12 direct,Rn Move register to direct byte 2 24 Exchange indirect RAM with Accumulator 1 MOV MOV direct, direct Move direct byte to direct 3 24 XCHD A,@Ri Exchange loworder Digit indirect RAM with Acc 1 12 AlmEL 2-75 Table 1. A T89 Instruction Set Summary (continued) Mnemonic Description Byte Oscillator Period BOOLEAN VARIABLE MANIPULATION C Clear Carry 1 12 CLR bit Clear direct bit 2 12 SETB C Set Carry 1 12 SETB bit Set direct bit 2 12 CPL C Complement Carry 1 12 CPL bit Complement direct bit 2 12 ANL C,bit AN D direct billo CARRY 2 24 ANL C,ibit AND complement of direct bit to Carry 2 24 ORL C,bit OR direct bit to Carry 2 24 ORL C,ibit OR complement of direct bit to Carry 2 24 MOV C,bit Move direct bit to Carry 2 12 MOV bit,C Move Carry to direct bit 2 24 JC rei Jump if Carry is set 2 24 JNC rei Jump if Carry not set 2 24 JB bit,rel Jump if direct Bit is set 3 24 JNB bit,rel Jump if direct Bit is Not set 3 24 JBC bit,rel Jump if direct Bit is set & clear bit 3 24 PROGRAM BRANCHING ACALL addr11 Absolute Subroutine Call 2 24 LCALL addr16 Long Subroutine Call 3 24 RET Return from Subroutine 1 24 RETI Return from interrupt 1 24 AJMP addr11 Absolu1e Jump 2 24 LJMP addr16 Long Jump 3 24 SJMP rei Short Jump (relative addr) 2 24 Instruction Set Description Byte Oscillator Period PROGRAM BRANCHING (continued) CLR 2-76 Mnemonic JMP @A+DPTR Jump indirect relative to the DPTR 1 24 JZ rei Jump if Accumulator is Zero 2 24 JNZ rei Jump if Accumulator is Not Zero 2 24 CJNE A,direct,rel Compare direct byte to Ace and Jump if Not Equal 3 24 CJNE A,#data,rel Compare immediate to Acc and Jump if Not Equal 3 24 CJNE Rn,#data,rel Compare immediate to register and Jump if Not Equal 3 24 CJNE @Ri,#data,rel Compare immediate to indirect and Jump if Not Equal 3 24 DJNZ Rn,rel Decrement register and Jump if Not Zero 2 24 DJNZ direct, rei Decrement direct byte and Jump if Not Zero 3 24 No Operation 1 12 NOP Instruction Set Table 2. Instruction Opcodes in Hexadecimal Order Hex Code Number of Bytes Mnemonic Hex Code Operands Number of Bytes Mnemonic Operands 00 1 NOP 22 1 01 2 AJMP code addr 23 1 RET RL A 02 3 LJMP code addr 24 2 ADD A,#data 03 1 RR A 25 2 ADD A,data addr 04 1 INC A 26 1 ADD A,@RO 05 2 INC dataaddr 27 1 ADD A,@R1 06 1 INC @RO 28 1 ADD A,RO 07 1 INC @R1 29 1 ADD A,R1 08 1 INC RO 2A 1 ADD A,R2 09 1 INC R1 2B 1 ADD A,R3 OA 1 INC R2 2C 1 ADD A,R4 OB 1 INC R3 2D 1 ADD A,R5 OC 1 INC R4 2E 1 ADD A,R6 OD 1 INC R5 2F 1 ADD A,R7 OE 1 INC R6 30 3 JNB bit addr,code addr code addr OF 1 INC R7 31 2 ACALL 10 3 JBC bit addr, code addr 32 1 RETI 11 2 ACALL code addr 33 1 RLC A 12 3 LCALL code addr 34 2 AD DC A,#data 13 1 RRC A 35 2 AD DC A,data addr 14 1 DEC A 36 1 AD DC A,@RO 15 2 DEC dataaddr 37 1 AD DC A,@R1 16 1 DEC @RO 38 1 AD DC A,RO 17 1 DEC @R1 39 1 AD DC A,R1 18 1 DEC RO 3A 1 AD DC A,R2 19 1 DEC R1 3B 1 AD DC A,R3 1A 1 DEC R2 3C 1 ADDC A,R4 A,R5 1B 1 DEC R3 3D 1 AD DC 1C 1 DEC R4 3E 1 ADDC A,R6 1D 1 DEC R5 3F 1 AD DC A,R7 1E 1 DEC R6 40 2 JC code addr 1F 1 DEC R7 20 3 JB bit addr,code addr 21 2 AJMP code addr 2-77 AIDIEL Table 2. Instruction Opcodes in Hexadecimal Order (continued) Hex Code Number of Bytes Mnemonic Hex Code Operands Number of Bytes Mnemonic Operands 41 2 AJMP codeaddr 60 2 JZ code addr 42 2 ORL dataaddr,A 61 2 AJMP code addr 43 3 ORL data addr,lIdata 62 2 XRL 44 2 ORL A,lIdata 63 3 XRL 45 2 ORL A,dataaddr 64 2 XRL A,#data 46 1 ORL A,@RO 65 2 XRL A,data addr 47 1 ORL A,@Rl 66 1 XRL A,@RO 48 1 ORL A,RO 67 1 XRL A,@Rl 49 1 ORL A,Rl 68 1 XRL A,RO 4A 1 ORL A,R2 69 1 XRL A,Rl 48 1 ORL A,R3 6A 1 XRL A,R2 4C 1 ORL A,R4 68 1 XRL A,R3 40 1 ORL A,R5 6C 1 XRL A,R4 4E 1 ORL A,R6 60 1 XRL A,R5 A,R6 I .. dataaddr,A data addr,lIdata 4F 1 ORL A,R7 6E 1 XRL 50 2 JNC code addr 6F 1 XRL A,R7 70 2 JNZ code addr 51 2 ACALL code addr 52 2 ANL dataaddr,A 71 2 ACALL code addr 53 3 ANL data addr,lIdata 72 2 ORL C,bitaddr 54 2 ANL A,#data 73 1 JMP @A+OPTR 55 2 ANL A, dataaddr 74 2 MOV A,#data 56 1 ANL A,@RO 75 3 MOV data addr,lIdata 57 1 ANL A,@Rl 76 2 MOV @RO,lIdata 58 1 ANL A,RO 77 2 MOV @Rl,lIdata 59 1 ANL A,Rl 78 2 MOV RO,lIdata 5A 1 ANL A,R2 79 2 MOV Rl,#data 58 1 ANL A,R3 7A 2 MOV R2,#data 5C 1 ANL A,R4 78 2 MOV R3,#data 50 1 ANL A,R5 7C 2 MOV R4,#data 5E 1 ANL A,R6 70 2 MOV R5,lIdata 5F 1 ANL A,R7 7E 2 MOV R6,lIdata 2-78 Instruction Set Instruction Set Table 2, Instruction Opcodes in Hexadecimal Order (continued) Hex Code Number of Bytes Mnemonic Hex Code Operands Number of Bytes Mnemonic Operands 7F 2 MOV R7,#data AD 2 ORL C,Ibitaddr 80 2 SJMP code addr 81 2 AJMP codeaddr A1 2 AJMP code addr A2 2 MOV C,bit addr 82 2 ANL 83 1 MOVC C,bHaddr A3 1 INC OPTR A,@A+PC A4 1 MUL AB 84 1 OIV AB AS 8S 3 MOV data addr,data addr A6 2 MOV @RO,data addr 86 2 MOV data addr,@RO A7 2 MOV @R1,data addr 87 2 MOV data addr,@Rl A8 2 MOV RO,data addr 88 2 MOV data addr,RO A9 2 MOV R1,data addr 89 2 MOV data addr,R1 AA 2 MOV R2,data addr 8A 2 MOV data addr,R2 AB 2 MOV R3,data addr 8B 2 MOV data addr,R3 AC 2 MOV R4,data addr reserved BC 2 MOV data addr, R4 AD 2 MOV RS,data addr 80 2 MOV data addr,RS AE 2 MOV R6,data addr 8E 2 MOV data addr, R6 AF 2 MOV R7,data addr 8F 2 MOV data addr,R7 BO 2 ANL C,/bit addr 90 3 MOV OPTR,#data B1 2 ACALL code addr 91 2 ACALL code addr B2 2 CPL bitaddr 92 2 MOV bitaddr,C B3 1 CPL C B4 3 CJNE A,#data,code addr B5 3 CJNE A,data addr,code addr B6 3 CJNE @RO,#data,code addr B7 3 CJNE @R1,#data,code addr B8 3 CJNE RO,#data,code addr 93 1 MOVC A,@A+OPTR 94 2 SUBB A,#data 9S 2 SUBB A,dataaddr 96 1 SUBB A,@RO 97 1 SUBB A,@R1 98 1 SUBB A,RO 99 1 SUBB A,R1 9A 1 SUBB A,R2 9B 1 SUBB B9 3 CJNE R1,#data,code addr BA 3 CJNE R2,#data,code addr BB 3 CJNE R3,#data,code addr A,R3 9C 1 SUBB A,R4 90 1 SUBB A,RS 9E 1 SUBB A,R6 9F 1 SUBB A,R7 BC 3 CJNE R4,#data,code addr BO 3 CJNE RS,#data,code addr BE 3 CJNE R6,#data,code addr BF 3 CJNE R7,#data,code addr 2-79 • Table 2. Instruction Opcodes in Hexadecimal Order (continued) Hex Code Number of Bytes CO 2 Mnemonic Hex Code Operands PUSH dalaaddr Number of Bytes 'Mnemonic EO 1 MOVX Operands A,@OPTA C1 2 AJMP codeaddr E1 2 AJMP code addr C2 2 CLA biladdr E2 1 MOVX A,@AO C3 1 CLA C E3 1 MOVX A,@A1 C4 1 SWAP A E4 1 CLA A C5 2 XCH A,dataaddr E5 2 MOV A,data addr CS 1 XCH A,@AO E6 1 MOV A,@AO C7 1 XCH A,@A1 E7 1 MOV A,@A1 C8 1 XCH A,AO E8 1 MOV A,AO C9 1 XCH A,A1 E9 1 MOV A,A1 CA 1 XCH A,A2 EA 1 MOV A,A2 CB 1 XCH A,A3 EB 1 MOV A,A3 CC 1 XCH A,A4 EC 1 MOV A,A4 CO 1 XCH A,A5 ED 1 MOV A,A5 CE 1 XCH A,AS EE 1 MOV A,AS CF 1 XCH A,A7 EF 1 MOV A,A7 00 2 POP dalaaddr FO 1 MOVX @OPTA,A 01 2 ACALL code addr F1 2 ACALL code addr 02 2 SETB biladdr F2 1 MOVX @AO,A 03 1 SETB C F3 1 MOVX @A1,A 04 1 OA A F4 1 CPL A 05 3 OJNZ dala addr,code addr F5 2 MOV dataaddr,A FS 1 MOV @AO,A F7 1 MOV @A1,A F8 1 MOV AO,A OS 1 XCHO A,@AO 07 1 XCHO A,@A1 08 2 OJNZ AO,code addr 09 2 OJNZ A1,code addr OA 2 OJNZ 2 OJNZ A3,code addr DC 2 OJNZ A4,code addr 00 2 OJNZ A5,code addr DE 2 OJNZ AS,code addr 2·80 2 DJNZ Instruction Set 1 MOV A1,A 1 MOV A2,A FB 1 MOV A3,A FC 1 MOV A4,A FO 1 MOV A5,A FE 1 MOV A6,A FF 1 MOV A7,A A2,code addr DB OF F9 FA A7,code addr Instruction Set Instruction Definitions ACALL addr11 Function: Absolute Call Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the l6-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, opcode bits 7 through 5, and the second byte of the instruction. The subroutine called must therefore start within the same 2 K block of the program memory as the first byte of the instruction following ACALL. No flags are affected. Example: Initially SP equals 07H. The label SUBRTN is at program memory location 0345 H. After executing the following instruction, ACALL SUBRTN at location 0123H, SP contains 09H, internal RAM locations OSH and 09H will contain 25H and OlH, respectively, and the PC contains 0345H. Bytes: 2 Cycles: 2 Encoding: a-1-0-a-9-a-8--,.--0--0--0----., '-1 Operation: ACALL (PC) +- (PC) + 2 (SP) +- (SP) + 1 ((SP)) +- (PC7-0) (SP) +- (SP) + 1 ((SP)) +- (PC15-B) (PC1O-0) +- page address 2-81 • ADD A, Function: Add Description: ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otl:1erwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a c~y-out of bit 7 but not bit 6; otherwise, OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate. Example: The Accumulator holds OC3H (llOOOOllB), and register 0 holds OAAH (IOlOlOlOB). The following instruction, ADD A,RO leaves 6DH (OllOllOIB) in the Accumulator with the AC flag cleared and both the carry flag and OV set to I. ADD A,Rn Bytes: Cycles: Encoding: I0 0 0 Operation: ADD (A) ~ (A) + (Rn) ADD A,direct Bytes: 2 Cycles: Encoding: I0 0 0 Operation: ADD (A) ~ (A) + (direct) 2-82 Instruction Set 0 0 direct address Instruction Set ADD A,@Ri Bytes: Cycles: Encoding: I0 0 0 0 • Operation: ADD (A) ~ (A) + ((Ri)) ADD A,#data Bytes: 2 Cycles: Encoding: I0 0 0 0 0 0 immediate data Operation: ADD (A) ~ (A) + #data AD DC A, Function: Add with Carry Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate. Example: The Accumulator holds OC3H (11000011B) and register 0 holds OAAH (1OIOIOIOB) with the carry flag set. The following instruction, ADDC A,RO leaves 6EH (011011 lOB) in the Accumulator with AC cleared and both the Carry flag and OV set to 1. AlmEl 2-83 AIIOEL ADDC A,Rn Bytes: Cycles: Encoding: I0 0 r I Operation: AD DC (A) ~ (A) + (C) + (Rn) ADDC A,direct Bytes: 2 Cycles: Encoding: I 0 0 0 0 I direct address I immediate data Operation: AD DC (A) ~ (A) + (C) + (direct) ADDC A,@Ri Bytes: Cycles: Encoding: I 0 0 0 Operation: AD DC (A) ~ (A) + (C) + ((Ri)) AD DC A,#data Bytes: 2 Cycles: Encoding: I 0 0 0 Operation: ADDC (A) 2-84 ~ (A) + (C) + #data Instruction Set 0 0 I Instruction Set AJMP addr11 Function: Absolute Jump Description: AIMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing tbe PC twice), opcode bits 7 through 5, and tbe second byte of the instruction. The destination must therfore be within the same 2 K block of program memory as the first byte of the instruction following AJMP. Example: The label JMPADR is at program memory location 0I23H. The following instruction, AIMP JMPADR is at location 0345H and loads the PC witb 0123H. Bytes: 2 Cycles: 2 Encoding: [a10 89 a8 0 000 Operation: AJMP (PC) ~ (PC) + 2 (PC10-0) ~ page address ANL , Function: Logical-AND for byte variables Description: ANL performs the bitwise logical-AND operation between the variables indicated and stores tbe results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, tbe source can use register, direct, register-indirect, or immediate addressing; when tbe destination is a direct address, tbe source can be tbe Accumulator or immediate data. Note: When tbis instruction is used to modify an output port, the value used as the original port data will be read from tbe output data latch, not tbe input pins. Example: If the Accumulator holds OC3H (lIOOOOIlB), and register 0 holds 55H (OlOlOlOIB), then the following instruction, ANL A,RO leaves 41H (OIOOOOOlB) in the Accumulator. When the destination is a directly addressed byte, tbis instruction clears combinations of bits in any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in tbe Accumulator at run-time. The following instruction, ANL Pl,#OlIlOOllB clears bits 7, 3, and 2 of output port 1. AlmEl 2-85 AlmEL ANL A,Rn Bytes: Cycles: Encoding: I0 r I 0 1 I 0 0 0 Operation: ANL (A) ~ (A) /\ (Rn) ANL A,direct Bytes: 2 Cycles: Encoding: I0 0 1 I0 direct address Operation: ANL (A) ~ (A) /\ (direct) ANL A,@RI Bytes: Cycles: Encoding: I0 0 0 Operation: ANL (A) ~ (A) /\ ((Ri)) ANL A,#data Bytes: 2 Cycles: Encoding: I0 0 1 I0 immediate data Operation: ANL (A) ~ (A) /\ #data ANL direct,A Bytes: 2 Cycles: Encoding: I Operation: ANL (direct) 2·86 0 0 ~ 0 (direct) /\ (A) Instruction Set 0 oI direct address Instruction Set ANL direct,#data Bytes: 3 Cycles: 2 direct address Encoding: I'--O_ _ _O _ _-L_O__O _ _ _----' immediate data • Operation: ANL (direct) ANL ~ (direct) /\ #data C, Function: Logical-AND for bit variables Description: If the Boolean value ofthe source bit is a logical 0, then ANL C clears the carry flag; otherwise, this instruction leaves the carry flag in its current state. A slash ( I ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Only direct addressing is allowed for the source operand. Example: Set the carry flag if, and only if, PI.O = 1, ACC.7 = 1, and OV = 0: MOV C,PI.O ;LOAD CARRY WTIH INPUT PIN STATE ANL C,ACC.7 ;AND CARRY WITH ACCUM. BIT 7 ANL C,/OV ;AND WITH INVERSE OF OVERFLOW FLAG ANL C,bit Bytes: 2 Cycles: 2 Encoding: 1 1 Operation: ANL (C) ~ ° ° ° ° ° bit address ° (C) /\ (bit) ANL C,lbit Bytes: 2 Cycles: 2 '-°__ Encoding: 11....-1_ _0_ _ _ _ °--' bit address 0_ _ 0__ Operation: ANL (C)~(C)/\ I (bit) 2-87 CJNE , , rei Function: Compare and Jump if Not Equal. Description: CJNE compares the magnitudes of the first two operands and branches if their values are not equal. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of is less than the unsigned integer value of ; otherwise, the carry is cleared. Neither operand is affected. The first two operands allow four addressing mode combinations: the Accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant. Example: The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence, CJNE R7, # 60H, NOT_EQ = R7 60H. IFR7 <60H. R7 >60H. JC sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this instruction determines whether R7 is greater or less than 60H. If the data being presented to Port I is also 34H, then the following instruction, WAIT: CJNE A, PI,WAIT clears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal the data read from PI. (If some other value was being input on PI, the program loops at this point until the PI data changes to 34H.) CJNE A,direct,rel Bytes: 3 Cycles: 2 Encoding: I1 0 o o Operation: (PC) <-- (PC) + 3 IF (A) < > (direc~ THEN (PC) <-- (PC) + relative offset IF (A) < (direct) THEN (C) <-- 1 ELSE (C) <-- 0 2-88 Instruction Set 1 I direct address reI. address Instruction Set CJNE A,#data,rel Bytes: 3 Cycles: 2 Encoding: LI_1__0_ _ _-----"_o___o__o-' Operation: (PC) f- immediate data reI. address • (PC) + 3 IF (A) < > data THEN (PC) f- (PC) + relative offset IF (A) < data THEN (C) f-1 ELSE (C) f-O CJNE Rn,#data,rel Bytes: 3 Cycles: 2 Encoding: LI_1__0_ _ _-----"_ _ _ _ _ _r-'1 Operation: (PC) f- immediate data reI. address (PC) + 3 IF (Rn) < > data THEN (PC) f- (PC) + relative offset IF (Rn) < data THEN (C) f-1 ELSE (C) f- ° CJNE @Ri,data,rel Bytes: 3 Cycles: 2 Encoding: 1L--1__0_ _ _----L_o_____--.J immediate data I reI. address Operation: (PC) f- (PC) + 3 IF ((Ri)) < > data THEN (PC) f- (PC) + relative offset IF ((Ri)) < data THEN (C) f-l ELSE (C) f-O 2-89 CLR A Function: Clear Accumulator Description: CLR A clears the Accumulator (all bits set to 0). No flags are affected Example: The Accumulator contains 5CH (010111ooB). The following instruction, CLR A leaves the Accumulator set to ooH (oooooooOB). Bytes: Cycles: Encoding: LI_1_____0---'-_o____o__o----' Operation: CLR (A)~O CLR bit Function: Clear bit Description: CLR bit Clears the indicated bit (reset to 0). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit. Example: Port 1 has previously been written with 5DH (010111OlB). The following instruction, CLR Pl.2 leaves the port set to 59H (01011OOlB). CLR C Bytes: Cycles: Encoding: I1 ° ° 0 0 0 ° ° ° Operation: CLR (C)~O CLR bit Bytes: 2 Cycles: Encoding: I1 Operation: CLR (bit)~O 2~90 Instruction Set 0 bit address Instruction Set CPL A Function: Complement Accumulator Description: CPLA logically complements each bit of the Accumulator (one's complement). Bits which previously contained a 1 are changed to a 0 and vice-versa. No flags are affected. Example: The Accumulator contains 5CH (01011100B). The following instruction, CPL • A leaves the Accumulator set to OA3H (IOIOOOIIB). Bytes: Cycles: Encoding: 1L-1__________-L_O_______O___O~ Operation: CPL (A)~ I (A) CPL bit Function: Complement bit Description: CPL bit complements the bit variable specified. A bit that had been a 1 is changed to 0 and vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit. Note: When this instruction is used to modify an output pin, the value used as the original data is read from the output data latch, not the input pin. Example: Port 1 has previously been written with 5BH (0101 IIOIB). The following instruction sequence, CPL Pl.l CPL P1.2 leaves the port set to 5BH (0101 101 IB). CPL C Bytes: Cycles: Encoding: I1 ~ o __________ o__________ 0 ~L- ~ Operation: CPL (C)~I (C) 2-91 CPL bit Bytes: 2 Cycles: Encoding: 1'-_1__0_ _ _ _-'--0__0_ _ _ _0-' Operation: CPL (bit) f- I bit address (bit) DA A Function: Decimal-adjust Accumulator for Addition Description: DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If Accumulator bits 3 through 0 are greater than nine (xxxx 101O-xxxx 111I), or if the AC flag is one, six is added to the Accumulator producing the proper BCD digit in the low-order nibble. This internal addition sets the carry flag if a carry-out of the low-order four-bit field propagates through all high-order bits, but it does not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order bits now exceed nine (lOIOxxxx-llllxxxx), these high-order bits are incremented by six, producing the prop~r BCD digit in the high-order nibble. Again, this sets the carry flag if there is a carry-out of the high-order bits, but does not clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing mUltiple precision decimal addition. OV is not affected. All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal conversion by adding OOH, 06H, 6OH, or 66H to the Accumulator, depending on initial Accumulator and PSW conditions. Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DA A apply to decimal subtraction. 2·92 Instruction Set Instruction Set Example: The Accumulator holds the value 56H (01010110B), representing the packed BCD digits of the decimal number 56. Register 3 contains the value 67H (0110011IB), representing the packed BCD digits of the decimal number 67. The carry flag is set. The following instruction sequence ADDC DA A,R3 A first performs a standard two's-complement binary addition, resulting in the value OBEH (10111110) in the Accumulator. The carry and auxiliary carry flags are cleared. The Decimal Adjust instruction then alters the Accumulator to the value 24H (00100100B), indicating the packed BCD digits of the decimal number 24, the low-order two digits of the decimal sum of 56, 67, and the carry-in. The carry flag is set by the Decimal Adjust instruction, indicating that a decimal overflow occurred. The true sum of 56,67, and I is 124. BCD variables can be incremented or decremented by adding OIH or 99H. If the Accumulator initially holds 30H (representing the digits of 30 decimal), then the following instruction sequence, ADD DA A,#99H A leaves the carry set and 29H in the Accumulator, since 30 + 99 interpreted to mean 30 - 1 = 29. =129. The low-order byte of the sum can be Bytes: Cycles: Encoding: I O~ L _1_______ 0 ____L-0_______ O___ Operation: DA -contents of Accumulator are BCD IF [[(A3-a) > 9] V [(AC) = 1]] THEN (A3-a) f- (A3-a) + 6 AND IF [[(A7-4) > 9] V [(C) 1]] = THEN (A7-4) f- (A7-4) +6 2-93 • DEC byte Function: Decrement Description: DEC byte decrements the variable indicated by 1. An original value of OOH underflows to OFFH. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Register 0 contains 7FH (OIIIIIIIB). Internal RAM locations 7EH and 7FH contain OOH and 40H, respectively. The following instruction sequence, DEC DEC DEC @RO RO @RO leaves register 0 set to 7EH and internal RAM locations 7EH and 7FH set to OFFH and 3FH. DEC A Bytes: Cycles: Encoding: LI_o__o__o__1----'--I_o____o__o--'1 Operation: DEC (A) <-- (A) - 1 DEC Rn Bytes: Cycles: Encoding: LI_o__o __o__- L___________r~1 Operation: DEC (Rn) <-- (Rn) - 1 2-94 Instruction Set Instruction Set DEC direct Bytes: 2 Cycles: Encoding: I° ° ° Operation: DEC (direct) f-- ° ° direct address • (direct) - 1 DEC @Ri Bytes: Cycles: Encoding: I° Operation: DEC ((Ri)) ° ° f-- ° ((Ri)) - 1 DIV AB Function: Divide Description: DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B. The Accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags are cleared. Exception: if B had originally contained ~OH. the values returned in the Accumulator and B-register are undefined and the overflow flag are set. The carry flag is cleared in any case. Example: The Accumulator contains 251 (OFBH or 1111101lB) and B contains 18 (12H or 0001 00 lOB). The following instruction. DIV AB leaves 13 in the Accumulator (ODH or 0OOO110lB) and the value 17 (11H or 00010001 B) in B. since 251 = (13 X 18) + 17. Carry and OV are both cleared. Bytes: Cycles: 4 Encoding: 1L-...1_ _O__O__O--'-_0_ _ _ _ 0 __ 0.....J Operation: DIV (A)15-8 (8)7-0 f-- (A)/(B) 2-95 DJNZ , Function: Decrement and Jump if Not Zero Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of OOH underflows to OFFH. No flags are affected. The branch destination is computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. The location decremented may be a register or directly addressed byte. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins Example: Internal RAM locations 40H, 50H, and 60H contain the values OIH, 70H, and 15H, respectively. The following instruction sequence, 40H,LABEL_I 50H,LABEL_2 60H,LABEL_3 DJNZ DJNZ DJNZ causes ajump to the instruction at label LABEL_2 with the values OOH, 6FH, and ISH in the three RAM locations. The first jump was not taken because the result was zero. This instruction provides a simple way to execute a program loop a given number of times or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The following instruction sequence, MOV CPL DJNZ TOGGLE: R2,#8 PI.7 R2,TOGGLE toggles PI. 7 eight times, causing four output pulses to appear at bit 7 of output Port I. Each pulse lasts three machine cycles; two for DJNZ and one to alter the pin. DJNZ Rn,rel Bytes: 2 Cycles: 2 Encoding: I1 0 Operation: DJNZ (PC) ~ (PC) + 2 (Rn) ~ (Rn) - 1 IF (Rn) > 0 or (Rn) < 0 THEN (PC) ~ (PC) + rei 2-96 Instruction Set reI. address Instruction Set DJNZ direct,rel Bytes: 3 Cycles: 2 Encoding: I1 0 0 direct address 0 rei. address I • Operation: DJNZ (PC) ~ (PC) + 2 (direct) ~ (direct) - 1 IF (direct) > 0 or (direct) < 0 THEN (PC) ~ (PC) + rei INC Function: Increment Description: INC increments the indicated variable by I. An original value ofOFFH overflows to OOH. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Register 0 contains 7EH (OIIIIIIIOB). Internal RAM locations 7EH and 7FH contain OFFH and 40H, respectively. The following instruction sequence, @RO RO @RO INC INC INC leaves register 0 set to 7FH and internal RAM locations 7EH and 7FH holding DOH and 41H, respectively. INC A Bytes: Cycles: Encoding: I0 0 0 0 0 o 0 Operation: INC (A)~ (A) + 1 2-97 INC Rn Bytes: Cycles: Encoding: I° Operation: INC (Rn) ° ° ° (Rn) + 1 f- INC direct Bytes: 2 Cycles: Encoding: I° ° ° ° ° Operation: INC (direct) f- o direct address (direct) + 1 INC @Ri Bytes: Cycles: Encoding: I0 Operation: INC ((Ri)) ° f- 0 ° ° ((Ri)) + 1 INC DPTR Function: Increment Data Pointer Description: INC DPTR increments the l6-bit data pointer by I. A l6-bit increment (modulo 2 16) is performed, and an overflow of the low-order byte of the data pointer (DPL) from OFFH to OOH increments the high-order byte (DPH). No flags are affected. This is the only l6-bit register which can be incremented. Example: Registers DPH and DPL contain 12H and OFEH, respectively. The following instruction sequence, INC INC INC DPTR DPTR DPTR changes DPH and DPL to 13H and OIH. Bytes: Cycles: 2 Encoding: I _1__0____0-'-_0__0_ _ _---' L Operation: INC (DPTR) 2-98 f- (DPTR) + 1 Instruction Set Instruction Set JB blt,rel Function: Jump if Bit set Description: If the indicated bit is a one, JB jump to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. Example: The data present at input port I is I I 00 10 lOB. The Accumulator holds 56 (010101 lOB). The following instruction sequence, JB JB P1.2,LABELI ACC. 2,LABEL2 causes program execution to branch to the instruction at label LABEL2. Bytes: 3 Cycles: 2 Encoding: LI_O__O ____ 0-L_O__O __ O__O--' bit address reI. address I Operation: JB (PC) ~ (PC) + 3 IF (bit) = 1 THEN (PC) ~ (PC) + rei JBC bit,rel Function: Jump if Bit is set and Clear bit Description: If the indicated bit is one, JBC branches to the address indicated; otherwise, it proceeds with the next instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected. Note: When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin. Example: The Accumulator holds 56H (010101 JOB). The following instruction sequence, JBC JBC ACC.3,LABELI ACC.2,LABEL2 causes program execution to continue at the instruction identified by the label LABEL2, with the Accumulator modified to 52H (OIOIOOIOB). 2-99 • Bytes: 3 Cycles: 2 Encoding: I0 0 o 0 0 0 0 bit address reI. address Operation: JBC (PC) ~ (PC) + 3 IF (bit) = 1 THEN (bit)~O (PC) ~ (PC) Hel JC rei Function: Jump if Carry is set Description: If the carry flag is set, JC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected. Example: The carry flag is cleared. The following instruction sequence, JC CPL JC LABELl C LABEL 2 sets the carry and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: I...I_o~___o__o--,-_O__O __O__O-, Operation: JC (PC) ~ (PC) + 2 IF (C) = 1 THEN (PC) ~ (PC) + rei 2·100 Instruction Set reI. address Instruction Set JMP @A+DPTR Function: Jump indirect Description: JMP @A+DPTR adds the eight-bit unsigned contents of the Accumulator with the 16-bit data pointer and loads the resulting sum to the program counter. This is the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 2 16); a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are affected. Example: An even number from 0 to 6 is in the Accumulator. The following sequence of instructions branches to one of four AJMP instructions in a jump table starting at JMP_TBL. MOV JMP AJMP AJMP AJMP AJMP DPTR, # JMP_TBL @A+DPTR LABELO LABELl LABEL2 LABEL3 If the Accumulator equals 04H when starting this sequence, execution jumps to label LABEL2. Because AJMP is a 2-byte instruction, the jump instructions start at every other address. Bytes: Cycles: 2 1_0_____-'-_0__0___---' Encoding: .... Operation: JMP (PC) ~ (A) + (DPTR) AIIOEL 2-101 • ... ' AlmEl ' JNB bit,rel Function: Jump if Bit Not set Description: If the indicated bit isa 0, JNB branches to th.e indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the Pc'to the first byte of the next instruction. The bit tested is not modified. No flags . . are affected. Example: The data present atinput port 1 is 1 100 10 lOB. The Accumulator holds 56H (Ol0l0110B). The following instruction sequence, JNB JNB . P1.3,LABELl ACC.3,LABEL2 causes program execution to continue at the instruction at label LABEL2. Bytes: 3 Cycles: 2 Encoding: IL-0__O_ _ _ _"--O__O_ _O__O-' bit address reI. address Operation: JNB (PC) +- (PC) + 3 IF ° (bit) = THEN (PC) +- (PC) +rel JNC rei Function: Jump if Carry not set Description: If the carry flag is a 0, JNC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signal relative-displacement in the second instruction byte to the pc, after incrementing the PC twice to point to the next instruction. The carry flag is not modified. Example: The carry flag is set. The fol1owing instruction sequence, JNC LABELl CPL C JNC LABEL2 clears the carry and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: LI_O____O_ _.l-0__O _ _O__O--' Operation: JNC (PC) +- (PC) + 2 IF (C)=O THEN (PC) +- (PC) Hel 2-102 Instruction Set reI. address Instruction Set JNZ rei Function: Jump if Accumulator Not Zero Description: If any bit of the Accumulator is a one, JNZ branches to the indicated address; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected. • Example: The Accumulator originally holds OOH. The following instruction sequence, LABELl A LABEL2 JNZ INC JNZ sets the Accumulator to OIH and continues at label LABEL2. Bytes: 2 Cycles: 2 Encoding: LI_o_____-'-_o__o__o__o--' Operation: JNZ (PC) f- (PC) + 2 IF (A);t THEN (PC) ° f- reI. address (PC) + rei JZ rei Function: Jump if Accumulator Zero Description If all bits of the Accumulator are 0, JZ branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected. Example: The Accumulator originally contains OIH. The following instruction sequence, JZ LABELl DEC A JZ LABEL2 changes the Accumulator to DOH and causes program execution to continue at the instruction identified by the label LABEL2. Bytes: 2 Cycles: 2 Encoding: LI_o_____o--'_o__o__o__o--' Operation: JZ (PC) f- (PC) + 2 IF (A) THEN (PC) ° = f- rei. address (PC) + rei AIIDEL 2-103 LCALL addr16 Function: Long call Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the l6-bit result onto the stack (low byte first). incrementing the Stack Pointer by two. The high-order and low-order bytes of the PC are then loaded. respectively. with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 64K-byte program memory address space. No flags are affected. Example: Initially the Stack Pointer equals 07H. The label SUBRTN is assigned to program memory location 1234H. After executing the instruction. LCALL SUBRTN at location 0123H. the Stack Pointer will contain 09H. internal RAM locations OSH and 09H will contain 26H and OIH. and the PC will contain l234H. Bytes: 3 Cycles: 2 Encoding: I0 0 o 0 0 o addr1S-addrB addr7-addrO Operation: LCALL (PC) ~ (PC) + 3 (SP) ~ (SP) + 1 «SP)) ~ (PC7-0) (SP) ~ (SP) + 1 «SP)) ~ (PC15-B) (PC) ~ addr15-o LJMP addr16 Function: Long Jump Description: LIMP causes an unconditional branch to the indicated address. by loading the high-order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full64K program memory address space. No flags are affected. Example: The label JMPADR is assigned to the instruction at program memory location l234H. The instruction. LJMP JMPADR at location Ol23H will load the program counter with l234H. Bytes: 3 Cycles: 2 Encoding: I0 0 0 0 Operation: LJMP (PC) ~ addr15-o 2·104 Instruction Set 0 0 o addr1S-addrB addr7-addrO Instruction Set MOV , Function: Move byte variable Description: The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected. This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes are allowed. Example: Internal RAM location 30H holds 40H. The value of RAM location 40H is IOH. The data present at input port 1 is llOOIOIOB (OCAH). Mav MaV Mav MaV MaV MaV RO,#30H A,@RO Rl,A B,@RI @RI,PI P2,Pl ;RO <=30H ;A< =40H ;RI <=40H ;B <= IOH ;RAM (40H) < = OCAH ;P2 #OCAH leaves the value 30H in register 0, 40H in both the Accumulator and register I, IOH in register B, and OCAH (lIOOIOIOB) both in RAM location 40H and output on port 2. MOV A,Rn Bytes: Cycles: Encoding: I1 o Operation: MOV (A)~(Rn) "MOV A,direct Bytes: 2 Cycles: Encoding: I1 o 0 o direct address Operation: MOV (A) ~ (direct) " MOV A,ACC is not a valid Instruction. 2-105 • MOV A,@Ri Bytes: Cycles: Encoding: 11 0 0 Operation: MOV (A) f- «Ri» MOV A,#data Bytes: 2 Cycles: Encoding: 10 0 0 0 immediate data Operation: MOV (A) f- #data MOV Rn,A Bytes: Cycles: Encoding: 11 r I r I direct addr. r I immediate data Operation: MOV (Rn) f- (A) MOV Rn,direct Bytes: 2 Cycles: 2 Encoding: I1 0 0 Operation: MOV (Rn) f- (direct) MOV Rn,#data Bytes: 2 Cycles: Encoding: I0 Operation: MOV (Rn) f- #data 2-106 Instruction Set Instruction Set MOV direct,A Bytes: 2 Cycles: Encoding: Operation: I1 0 0 direct address • MOV (direct) (- (A) MOV direct,Rn Bytes: 2 Cycles: 2 Encoding: Operation: I1 0 0 0 r I direct address MOV (direct) (- (Rn) MOV direct,direct Bytes: 3 Cycles: 2 Encoding: Operation: I1 0 0 0 0 0 dir. addr. (scr) dir. addr. (dest) MOV (direct) (- (direct) MOV direct,@Ri Bytes: 2 Cycles: 2 Encoding: Operation: I1 0 0 0 direct addr. 0 MOV (direct) (- ((Ri)) MOV direct,#data Bytes: 3 Cycles: 2 Encoding: Operation: I0 0 0 direct address immediate data MOV (direct) (- #data 2-107 MOV @Ri,A Bytes: Cycles: Encoding: I1 0 Operation: MOV ((Ri)) f-- (A) MOV @Ri,direct Bytes: 2 Cycles: 2 Encoding: I1 0 0 0 direct addr. 0 immediate data Operation: MOV ((Ri)) f-- (direct) MOV @Ri,#data Bytes: 2 Cycles: Encoding: I0 Operation: MOV ((Ri)) f-- #data MOV , Function: Move bit data Description: MOV , copies the Boolean variable indicated by the second operand into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected. Example: The carry flag is originally set. The data present at input Port 3 is 11000lOlB. The data previously written to output Port 1 is 35H (OOllOlOlB). MOV MOV MOV P1.3,C C,P3.3 P1.2,C leaves the carry cleared and changes Port 1 to 39H (OOllIOOlB). 2-108 Instruction Set Instruction Set MOV C,bit Bytes: 2 Cycles: Encoding: I1 0 000 o bit address o o bit address Operation: Mav (C) +- (bit) MOV bit,C Bytes: 2 Cycles: 2 Encoding: I1 0 0 0 Operation: MaV (bit) +- (C) MOV DPTR,#data16 Function: Load Data Pointer with a l6-bit constant Description: MOV DPTR,#data16 loads the Data Pointer with the l6-bit constant indicated. The l6-bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the lower-order byte. No flags are affected. This is the only instruction which moves 16 bits of data at once. Example: The instruction, MOV DPTR, # l234H loads the value l234H into the Data Pointer: DPH holds l2H, and DPL holds 34H. Bytes: 3 Cycles: 2 Encoding: I1 0 0 o 0 0 0 immed. data15-8 immed. data7-0 Operation: MaV (DPT!3l +- #data15-0 DPH U DPL +- #data15-8 0 #data7-0 2-109 MOVC A,@A+ Function: Move Code byte Description: The MOVC instructions load the Accumulator with a code byte or constant from program memory. The address of the byte fetched is the sum of the original unsigned 8-bit Accumulator contents and the contents of a 16-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is perfonned so a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are affected. Example: A value between 0 and 3 is in the Accumulator. The following instructions will translate the value in the Accumulator to one of four values defined by the DB (define byte) directive. REL_PC: INC A MOVC A,@A+PC RET DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the Accumulator equal to 01H, it returns with 77H in the Accumulator. The INC A before the MOVC instruction is needed to "get around" the RET instruction above the table. If several bytes of code separate the MOVC from the table, the corresponding number is added to the Accumulator instead. MOVC A,@A+DPTR Bytes: Cycles: 2 Encoding: LI_1__0_ _0 _ _-'--0__0_ _ _---' Operation: MOVC (A) ~ «A) + (DPTR)) MOVC A,@A+PC Bytes: Cycles: 2 ° ° Encoding: 1L -_ 1 _ _ _ _ _ _ _ _ _0_ _L -_ 0 _ _0_ _ _ _ _ _ _ Operation: MOVC (PC) ~ (PC) + 1 (A) ~ «A) + (PC)) 2-110 Instruction Set ~ Instruction Set MOVX , Function: Move External Description: The MOVX instructions transfer data between the Accumulator and a byte of external data memory, which is why "X" is appended to MOV. There are two types of instructions, differing in whether they provide an S-bit or 16-bit indirect address to the external data RAM. In the first type, the contents of RO or RI in the current register bank provide an S-bit address multiplexed with data on PO. Eight bits are sufficient for external I/O expansion decoding or for a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output higher-order address bits. These pins are controlled by an output instruction preceding the MOVX. In the second type of MOVX instruction, the Data Pointer generates a 16-bit address. P2 outputs the high-order eight address bits (the contents of DPH), while PO mUltiplexes the low-order eight bits (DPL) with data. The P2 Special Function Register retains its previous contents, while the P2 output buffers emit the contents of DPH. This form of MOVX is faster and more efficient when accessing very large data arrays (up to 64K bytes), since no additional instructions are needed to set up the output ports. It is possible to use both MOVX types in some situations. A large RAM array with its high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to output high-order address bits to P2, followed by a MOVX instruction using RO or R I. Example: An external 256 byte RAM using multiplexed address/data lines is connected to the 8051 Port O. Port 3 provides control lines for the external RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and I contain 12H and 34H. Location 34H of the external RAM holds the value 56H. The instruction sequence, MOVX A,@RI MOVX @RO,A copies the value 56H into both the Accumulator and external RAM location 12H. 2-111 MOVX A,@Ri Bytes: Cycles: 2 Encoding: I1 0 0 0 0 0 0 0 0 0 0 Operation: MOVX (A)~((Ri)) MOVX A,@DPTR Bytes: Cycles: 2 Encoding: I1 0 0 0 o Operation: MOVX (A) ~ ((DPTR)) MOVX @RI,A Bytes: Cycles: 2 Encoding: I1 Operation: MOVX ((Ri)) ~ (A) MOVX @DPTR,A Bytes: Cycles: 2 Encoding: I1 Operation: MOVX (DPTR)~(A) 2·112 Instruction Set I Instruction Set MUL AB Function: Multiply Description: MUL AB multiplies the unsigned 8-bit integers in the Accumulator and register B. The low-order byte of the 16-bit product is left in the Accumulator, and the high-order byte in B. If the product is greater than 255 (OFFH), the overflow flag is set; otherwise it is cleared. The carry flag is always cleared. Example: Originally the Accumulator holds the value 80 (50H). Register B holds the value 160 (OAOH). The instruction, MUL AB will give the product 12,800 (3200H), so B is changed to 32H (oollooIOB) and the Accumulator is cleared. The overflow flag is set, carry is cleared. Bytes: Cycles: 4 Encoding: '--1__o_ _ _ _o~_0_ _ _ _o__o__'1 Operation: MUL (A)7-o ~ (A) X (8) (8)15-8 NOP Function: No Operation Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected. Example: A low-going output pulse on bit 7 of Port 2 must last exactly 5 cycles. A simple SETB/CLR sequence generates a one-cycle pulse, so four additional cycles must be inserted. This may be done (assuming no interrupts are enabled) with the following instruction sequence, CLR NOP NOP NOP NOP SETB P2.7 P2.7 Bytes: Cycles: Encoding: I0 0 0 0 0 0 0 0 Operation: NOP (PC) ~ (PC) + 1 2-113 AlmEL ORL Function: Logical-OR for byte variables Description: ORL performs the bitwise logical-OR operation between the indicated variables, storing the results in the des- tination byte. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins. Example: If the Accumulator holds OC3H (l 100001 IB) and RO holds 55H (OlOIOIOlB) then the following instruction, ORL A,RO leaves the Accumulator holding the value OD7H (lIOlOlllB). When the destination is a directly addressed byte, the instruction can set combinations of bits in any'RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be either a constant data value in the instruction or a variable computed in the Accumulator at run-time. The instruction, ORL PI ,#00 llOO lOB sets bits 5, 4, and 1 of output Port 1. ORL A,Rn Bytes: Cycles: Encoding: I0 0 0 Operation: ORL (A)~(A)V (Rn) ORL A,direct Bytes: 2 Cycles: Encoding: I0 0 0 Operation: ORL (A) 2-114 ~ (A) V (direct) Instruction Set 0 0 direct address Instruction Set ORL A,@RI Bytes: Cycles: Encoding: I0 0 0 0 Operation: ORL (A) ~ (A) Y((Ri)) ORL A,#data Bytes: 2 Cycles: Encoding: I0 0 0 0 0 0 immediate data 0 direct address Operation: ORL (A) ~ (A) V #data ORL direct,A Bytes: 2 Cycles: Encoding: I0 0 0 0 0 Operation: ORL (direct) ~ (direct) V (A) ORL dlrect,#data Bytes: 3 Cycles: 2 Encoding: I0 Operation: ORL (direct) 0 ~ 0 0 0 direct addr. II immediate data (direct) V #data 2-115 ORL C, Function: Logical-OR for bit variables Description: Set the carry flag if the Boolean value is a logical I; leave the carry in its current state otherwise. A slash (I) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Example: Set the carry flag if and only if Pl.O =I, ACe. 7 =I, or OV =0; ORL MOV C,P1.0 ;LOAD CARRY wrrn INPUT PIN PIO ORL C,ACC.7 ;OR CARRY WITH TIffi ACC. BIT 7 ORL C,IOV ;OR CARRY WITIl TIlE INVERSE OF OV. C,bit Bytes: 2 Cycles: 2 Encoding: 1 ° Operation: ORL (C) f- (C) V (bit) ORL 0 ° ° bit address C,Ibit Bytes: 2 Cycles: 2 Encoding: L..1_1__0_ _ _ _0--'-_0__0_ _0__0---' Operation: ORL (C) f- (C) V (bit) 2-116 Instruction Set bit address Instruction Set POP direct Function: Pop from stack. Description: The contents of the internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected. Example: The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through 32H contain the values 20H, 23H, and OIH, respectively. The following instruction sequence, POP DPH POP DPL leaves the Stack Pointer equal to the value 30H and sets the Data Pointer to 0123H. At this point, the following instruction, POP SP leaves the Stack Pointer set to 20H. In this special case, the Stack Pointer was decremented to 2FH before being loaded with the value popped (20H). Bytes: 2 Cycles: 2 Encoding: IL-1___O _ _--'-_o__o __o__o.. . .J direct address Operation: POP (direct) f- «SP)) (SP) f- (SP) - 1 PUSH direct Function: Push onto stack Description: The Stack Pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected. Example: On entering an interrupt routine, the Stack Pointer contains 09H. The Data Pointer holds the value 0123H. The following instruction sequence, PUSH DPL PUSH DPH leaves the Stack Pointer set to OBH and stores 23H and OIH in internal RAM locations OAH and OBH, respectively. Bytes: 2 Cycles: 2 Encoding: L...I_1____ 0 __o--'-_o__o __o__o--' direct address Operation: PUSH (SP) f- (SP) + 1 «SP)) f- (direct) 2-117 RET Function: Return from subroutine Description: RET pops the high- and low-order bytes of the PC successively from the stack, decrementing the Stack Pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected. Example: The Stack Pointer originally contains the value OBH. Internal RAM locations OAH and OBH contain the values 23H and OIH, respectively. The following instruction, RET leaves the Stack Pointer equal to the value 09H. Program execution continues at location 0123H. Bytes: Cycles: 2 Encoding: LI_o__o____0-L_O__o___~O--..J Operation: RET (PC15-a) ~ «SP)) (SP) ~ (SP) - 1 (PC7-0) r «SP)) (SP) ~ (SP) - 1 RETI Function: Return from interrupt Description: RET! pops the high- and low-order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The Stack Pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt status. Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower- or same-level interrupt was pending when the RETI instruction is e~ecuted, that one instruction is executed before the pending interrupt is processed. Example: The Stack Pointer originally contains the value OBH. An interrupt was detected during the instruction ending at location 0122H. Internal RAM locations OAH and OBH contain the values 23H and OIH, respectively. The following instruction, RET! leaves the Stack Pointer equal to 09H and returns program execution to location 0123H. Bytes: Cycles: 2 Encoding: LI_O__O ____.J......0__O _ _ _ _O--' Operation: RETI (PC15-a) ~ «SP)) (SP) ~ (SP) - 1 (PC7-0) r «SP)) (SP) ~ (SP) - 1 2-118 Instruction Set Instruction Set RL A Function: Rotate Accumulator Left Description: The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit are affected. ° position. No flags Example: The Accumulator holds the value OC5H (I lOOOIOIB). The following instruction, RL A leaves the Accumulator holding the value 8BH (lOOOlOlIB) with the carry unaffected. Bytes: Cycles: Encoding: LI_o__o____o---'-_o__o___---' Operation: RL (An + 1) ~ (An) n =0-6 (AO) ~ (A7) RLC A Function: Rotate Accumulator Left through the Carry flag Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit position. No other flags are affected. ° Example: The Accumulator holds the value OC5H(IIOOOIOIB), and the carry is zero. The following instruction, RLC A leaves the Accumulator holding the value 8BH (IOOOIOIOB) with the carry set. Bytes: Cycles: ____"--0__0_ _ _---' Encoding: 1'--0__o Operation: RLC (An + 1) ~ (An) n = 0 - 6 (AO)~(C) (C)~(A7) 2-119 RR A Function: Rotate Accumulator Right Description: The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. Example: The Accumulator holds the value OC5H (ll000101B). The following instruction, RR A leaves the Accumulator holding the value OE2H (111OOOlOB) with the carry unaffected. Bytes: Cycles: Encoding: I0 0 0 0 I0 0 Operation: RR (An) ~ (An + 1) n = 0 - 6 (A7) ~ (AO) RRC A Function: Rotate Accumulator Right through Carry flag Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry nag; the original value of the carry flag moves into the bit 7 position. No other nags are affected. Example: The Accumulator holds the value OC5H (1lO00lOlB), the carry is zero. The following instruction, RRC A leaves the Accumulator holding the value 62 (OllOoolOB) with the carry set. Bytes: Cycles: Encoding: I0 0 0 o Operation: RRC (An) ~ (An + 1) n = 0 - 6 (A7)~(C) (C)~(AO) 2·120 Instruction Set 0 Instruction Set SETB Function: Set Bit Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected. Example: The carry flag is cleared. Output Port I has been written with the value 34H (OOIIOIOOB). The following instructions, SETB C SETB Pl.O sets the carry flag to 1 and changes the data output on Port 1 to 35H (OOIIOIOIB). SETB C Bytes: Cycles: Encoding: I 1 0 o 0 0 o 0 Operation: SETB (C) f-1 SETB bit Bytes: 2 Cycles: Encoding: I 1 o bit address Operation: SETB (bit) f-1 AIIDEL 2·121 SJMP rei Function: Short Jump Description: Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction 127 bytes following it. Example: The label RELADR is assigned to an instruction at program memory location 0123H. The following instruction, SJMP RELADR assembles into location 0100H. After the instruction is executed, the PC contains the value 0123H. (Note: Under the above conditions the instruction following SIMP is at 102H. Therefore, the displacement byte of the instruction is the relative offset (OI23H-0102H) = 21H. Put another way, an SIMP with a displacement of OFEH is a one-instruction infinite loop.) Bytes: 2 Cycles: 2 Encoding: LI_1__0__0__o-'._o__o__o__o--, Operation: SJMP (PC) f-- (PC) + 2 (PC) f-- (PC) + rei 2-122 Instruction Set reI. address Instruction Set SUBB A, Function: Subtract with borrow Description: SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7 and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple-precision subtraction, so the carry is subtracted from the Accumulator along with the source operand.) AC is set if a borrow is needed for bit 3 and cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. When subtracting signed integers, OV indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number. The source operand allows four addressing modes: register, direct, register-indirect, or immediate. Example: The Accumulator holds OC9H (I 100 100 lB), register 2 holds 54H (01010100B), and the carry flag is set. The instruction, SUBB A,R2 will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared but OV set. Notice that OC9H minus 54H is 75H. The difference between this and the above result is due to the carry (borrow) flag being set before the operation. If the state of the carry is not known before starting a single or mUltiple-precision subtraction, it should be explicitly cleared by CLR C instruction. SUBB A,Rn Bytes: Cycles: Encoding: I1 0 0 Operation: SUBB (A) f- (A) - (C) - (Rn) AIIOEL 2-123 SUBB A,direct Bytes: 2 Cycles: Encoding: Operation: I 1 0 0 0 direct address 0 SUBB (A) +- (A) - (C) - (direct) SUBB A,@Ri Bytes: Cycles: Encoding: I Operation: SUBB 1 0 0 0 (A) +- (A) - (C) - ((Ri» SUBB A,#data Bytes: 2 Cycles: Encoding: Operation: I 1 0 0 0 0 0 immediate data SUBB (A) +- (A) - (C) - #data SWAP A Function: Swap nibbles within the Accumulator Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator (bits 3 through 0 and bits 7 through 4). The operation can also be thought of as a 4-bit rotate instruction. No flags are affected. Example: The Accumulator holds the value OC5H (110001OlB). The instruction, SWAP A leaves the Accumulator holding the value 5CH (01011100B). Bytes: Cycles: Encoding: I1 000 o 0 ~----------~~----------~ Operation: SWAP (A3-0) ~ (A7-4) 2-124 Instruction Set Instruction Set XCH A, Function: Exchange Accumulator with byte variable Description: XCH'loads the Accumulator with the contents of the indicated variable, at the same time writing the original Accumulator contents to the indicated variable. The source/destination operand can use register, direct, or register-indirect addressing. Example: RO contains the address 20H. The Accumulator holds the value 3FH (OOllllllB). Internal RAM location 20H holds the value 75H (Oll10101B). The following instruction, XCH A,@RO leaves RAM location 20H holding the values 3FH (OO111lllB) and 75H (01 110101B) in the accumulator. XCH A,Rn Bytes: Cycles: Encoding: Operation: I1 0 0 r I XCH (A) f:? «An) XCH A,direct Bytes: 2 Cycles: Encoding: Operation: I1 0 0 0 0 0 0 direct address XCH (A) f:? (direct) XCH A,@Ri Bytes: Cycles: Encoding: Operation: I1 0 XCH (A) f:? «Ai)) 2-125 XCHD A,@RI Function: Exchange Digit Description: XCHD exchanges the low-order nibble of the Accumulator (bits 3 through 0), generally representing a hexadecimal or BCD digit, with that of the internal RAM location indirectly add~ssed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected. Example: RO contains the address 20H. The Accumulator holds the value 36H (001 101 lOB). Internal RAM location 20H holds the value 75H (0111010IB). The following instruction, XCHD A,@RO leaves RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in the Accumulator. Bytes: Cycles: Encoding: _1_______ 0 ____ LI ~0__________~ Operation: XCHD (As-o) ~ «Ri3-0)) XRL , Function: Logical Exclusive-OR for byte variables Description: XRL performs the bitwise logical Exclusive-OR operation between the indicated variables, storing the results in the destination. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. (Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins.) Example: If the Accumulator holds OC3H (110000llB) and register 0 holds OAAH (10101010B) then the instruction, XRL A,RO leaves the Accumulator holding the value 69H (0110100IB). When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the Accumulator at run-time. The following instruction, XRL Pl,#OOI1000lB complements bits 5, 4, and 0 of output Port 1. 2-126 Instruction Set Instruction Set XRL A,Rn Bytes: Cycles: Encoding: I0 0 r I Operation: XRL (A) ~ (A) lJ. (Rn) XRL A,direct Bytes: 2 Cycles: Encoding: I0 0 0 0 direct address Operation: XRL (A) ~ (A) lJ. (direct) XRL A,@Ri Bytes: Cycles: Encoding: I0 0 0 Operation: XRL (A) ~ (A) lJ. ((Ri)) XRL A,#data Bytes: 2 Cycles: Encoding: I0 0 0 0 0 immediate data 0 direct address Operation: XRL (A) ~ (A) lJ. #data XRL direct,A Bytes: 2 Cycles: Encoding: I0 0 0 0 Operation: XRL (direct) ~ (direct) lJ. (A) 2·127 XRL direct,#data Bytes: 3 Cycles: 2 Encoding: 1'--0_ _ _ _ _ 0-'-_0_ _ 0_ _ _-' Operation: XRL (direct) 2-128 ~ (direct) ¥ #data Instruction Set direct address 1 1 immediate data Microcontroller Product Information General Architecture Microcontroller Application Notes Programmer Support/Development Tools Microcontroller Cross-Reference Package Outlines Miscellaneous Information AlmEl - - - - - - Contents Section 3 Microcontroller Data Sheets AT89C1051 ............ 8-bit 1K Low Voltage Flash Microcontroller in 20-pin package ......... 3-3 AT89C2051 ............ 8-bit 2K Low Voltage Flash Microcontroller in 20-pin package ......... 3-17 AT89C51 ................ 8-bit 4K Flash Microcontroller ........................................................... 3-33 AT89LV51 .............. 8-bit 4K Low Voltage Flash Microcontroller ...................................... 3-49 AT89C52 ................ 8-bit 8K Flash Microcontroller ........................................................... 3-65 AT89LV52 .............. 8-bit 8K Low Voltage Flash Microcontroller ...................................... 3-87 AT89S8252 ............ 8-bit 8K Downloadable Flash Microcontroller ................................... 3-109 • 3-1 3·2 AT89C1051 Features • • • • • • • • • • • • Compatible with MCS-51TM Products 1 Kbyte of Reprogrammable Flash Memory Endurance: 1,000 WriteJErase Cycles 2.7 V to 6 V Operating Range Fully Static Operation: 0 Hz to 24 MHz Two-Level Program Memory Lock 64 bytes SRAM 15 Programmable 1/0 Lines One 16-Bit Timer/Counter Three Interrupt Sources Direct LED Drive Outputs On-Chip Analog Comparator Low Power Idle and Power Down Modes 8-Bit Microcontroller with 1 Kbyte Flash Description The AT89ClOS1 is a low-voltage, high-perfonnance CMOS 8-bit microcomputer with 1 Kbyte of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel's high density nonvolatile memory technology and is compatible with the industry standard MCS-SFM instruction set and pinout. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89ClOS1 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89ClOS1 provides the following standard features: 1 Kbyte of Flash, 64 bytes of RAM, IS UO lines, one 16-bit timer/counter, a three vector two-level interrupt architecture, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89ClOS1 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Configuration PDIP/SOIC RST P3.0 P3.l XTAL2 XTALl (INTO) P3.2 (INT1) P3.3 (TO) P3.4 P3.S GND ....:..::.._ _~. vee P1.7 P1.6 Pl.S Pl.4 P1.3 P1.2 P1.l (AIN1) Pl.0 (AI NO) P3.7 0366C 3-3 • Block Diagram r - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -,;. - - - - - - - - - - - - - - - - - - -- v~ ,, INTERRUPT, AND TIMER BLOCKS RST TIMING AND CONTROL Pl.0-Pl.7 3-4 AT89C1051 P3.0-P3.S P3.7 --- AT89C1051 Pin Description Oscillator Characteristics Vee XTALl and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure I. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTALl is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divideby-two flip- flop, but minimum and maximum voltage high and low time specifications must be observed. Supply voltage. GND Ground. Port 1 Port 1 is an 8-bit bidirectional 110 port. Port pins PI.2 to P1.7 provide internal pullups. PI.O and Pl.1 require external pullups. P1.0 and Pl.l also serve as the positive input (AINO) and the negative input (AINl), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 20 rnA and can drive LED displays directly. When Is are written to Port 1 pins, they can be used as inputs. When pins P1.2 to PI.7 are used as inputs and are externally pulled low, they will source current (IlL) because of the internal pullups. Figure 1. Oscillator Connections • C2 Port 1 also receives code data during Flash programming and program verification. I Port 3 Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional 110 pins with internal pullups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose 110 pin. The Port 3 output buffers can sink 20 rnA. When Is are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. C1 Y XTAL2 XTAL1 GND Port 3 also serves the functions of various special features of the AT89C1051 as listed below: Port Pin P3.2 P3.3 P3.4 Alternate Functions Notes: C 1, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators INTO (external interrupt 0) INT1 (external interrupt 1) TO (timer 0 external input) Port 3 also receives some control signals for Flash programming and programming verification. Figure 2. External Clock Drive Configuration NC XTAl2 RST Reset input. All 110 pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device. Each machine cycle takes 12 oscillator or clock cycles. EXTERNAL OSCILLATOR - - - - I SIGNAL XTAL1 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. GND XTAl2 Output from the inverting oscillator amplifier. 3-5 Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in the table below. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write Is to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be O. Table 1• AT89C1051 SFR Map and Reset Values OF8H OFOH OFFH B 00000000 OF7H OE8H OEOH OEFH ACC 00000000 OE7H 008H OOOH OOFH PSW 00000000 007H OC8H OCFH OCOH OC7H IP OB8H XXXOOOOO P3 OBOH 11111111 IE OA8H OXXOOOOO OAOH 98H P1 90H 11111111 TCON 88H 00000000 80H 3·6 OBFH OB7H OAFH OA7H 9FH 97H TMOD 00000000 SP 00000111 TLO 00000000 OPL 00000000 AT89C1051 THO 00000000 OPH 00000000 8FH PCON OXXXOOOO 87H AT89C1051 Restrictions on Certain Instructions TheAT89C lOS 1 is an economical and cost-effective member of AtmeI's growing family of microcontrollers. It contains 1 Kbyte of flash program memory. It is fully compatible with the MCS-Sl architecture, and can be programmed using the MCSSI instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 1K for the AT89C lOS 1. This should be the responsibility of the software programmer. For example, LJMP 3FEH would be a valid instruction for the AT89ClOSI (with lK of memory), whereas LJMP 410H would not. 1. Branching instructions: LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR For applications involving interrupts the normal interrupt service routine address locations of the 80CSI family architecture have been preserved. 2. MOVX-related instructions, Data Memory: The AT89ClOSI contains 64 bytes of internal data memory. Thus, in the AT89CI0Sl the stack depth is limited to 64 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX [ ... J instructions should be included in the program. A typical 80CSI assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used corr~spondingly. These unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations OOH to 3FFH for the 89CI0S1). Violating the physical space limits may cause unknown program behavior. CJNE [... J, DJNZ [ ... J, JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional branching instructions the same rule above applies. Again, violating the memory boundaries may cause erratic execution. 3·7 • Program Memory Lock Bits Programming The Flash On the chip are two lock bits. which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: The AT89C1051 is shipped with the 1 Kbyte of on-chip PEROM code memory array in the erased state (i.e., contents = FFH) and ready to be programmed. The code memory array is programmed one byte at a time. Once the array is programmed, Lock Bit Protection Modes(1) LB1 LB2 U U No program lock features. Internal Address Counter: The AT89CI051 contains an internal PEROM address counter which is always reset to OOOH on the rising edge ofRST and is advanced by applying a positive going pulse to pin XTALl. Programming Algorithm: To program the AT89C105 1, the following sequence is recommended. 1. Power-up sequence: Apply power between Vee and GND pins Set RST and XTALI to GND With all other pins floating, wait for greater than 10 milliseconds Program Lock Bits 1 Protection Type 2 p U Further programming 01 the Flash is disabled. 3 p P Same as mode 2, also verify is disabled. Note: I. The Lock Bits can only be erased with the Chip Erase operation 2. Set pin RST to 'H' Set pin P3.2 to 'H' Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. PI.O and PI.I should be set to '0' ifno external pullups are used, or set to '1' if external pull ups are used. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power Down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before Vee is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. PI.O and Pl.1 should be setto '0' if no external pullups are used, or set to '1' if external pullups are used. 3-8 to re-program any non-blank byte, the entire memory array needs to be erased electrically. AT89C1051 3. Apply the appropriate combination of 'H' or 'L' logic levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations shown in the PEROM Programming Modes table. To Program and Verify the Array: 4. Apply data for Code byte at location OOOH to PI.O to P1.7. 5. Raise RST to 12V to enable programming. 6. Pulse P3.2 once to program a byte in the PEROM array or the lock bits. The byte-write cycle is self-timed and typically takes 1.2 ms. 7. To verify the programmed data, lower RST from 12V to logic 'H' level and set pins P3.3 to P3.7 to the appropiate levels. Output data can be read at the port PI pins. 8. To program a byte at the next address location, pulse XTAL I pin once to advance the internal address counter. Apply new data to the port PI pins. 9. Repeat steps 5 through 8, changing data and advancing the address counter for the entire I Kbyte array or until the end of the object file is reached. 10. Power-off sequence: setXTALI to 'L' set RST to 'L' Float all other 110 pins Turn Vcc power off AT89C1051 Data Polling: The ATS9C1051 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The Progress of byte programming can also be monitored by the RDYIBSY output signal. Pin P3.1 is pulled low after P3.2 goes High during programming to indicate BUSY. P3.1 is pulled High again when programming is done to indicate READY. Program Verify: If lock bits LB I and LB2 have not been programmed code data can be read back via the data lines for verification: 1. Reset the internal address counter to OOOH by bringing RST from 'L' to 'H'. 2. Apply the appropriate control signals for Read Code data and read the output data at the port PI pins.' The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire PEROM array (1 Kbyte) and the two Lock Bits are erased electrically by using the proper combination of control signals and by holding P3.2 low for 10 ms. The code array is written with all "I "s in the Chip Erase operation and must be executed before any non-blank memory byte can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations OOOH, OOIH, and 002H, except that P3.5 and P3.7 must be pulled to a logic low. The values returned are as follows. (OOOH) (OOIH) = IEH indicates manufactured by Atmel =IlH indicates S9C1051 Programming Interface Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion. 3. Pulse pin XTALI once to advance the internal address counter. 4. Read the next code data byte at the port PI pins. All major programming vendors offer worldwide support for the Atrnel microcontroller series. Please contact your local programming vendor for the appropriate software revision. 5. Repeat steps 3 and 4 until the entire array is read. Flash Programming Modes P3.21 Mode RST PROG P3.3 P3.4 P3.S P3.7 Write Code Data(1,3) 12V \...J L H H H Read Code Data(1) H H L L H H Bit -1 12V \...J H H H H Bit - 2 12V \...J H H L L 12V V H L L L L L L L Write Lock Chip Erase Read Signature Byte Notes: H 2) H I. The internal PEROM address counter is reset to OOOH on the rising edge of RST and is advanced by a positive pulse at 2. Chip Erase requires a 10 ms PROG pulse. __ 3. P3.l is pulled Low during programming to indicate RDYIBSY. XTALI pin. 3·9 • Figure 3. Programming the Flash Memory Figure 4. Verifying the Flash Memory SV RDY/BSY P3.1 Vee 'PROG P3.2 Pl Vee PGM DATA JL TO INCREMENT ADDRESS COUNTER P3.S P3.4 P3.S P3.7 P3,7 XTALl PGM DATA Pl P3.3 SEE FLASH PROGRAMMING MODES TABLE PM P3.2 V'H P3.3 SEE FLASH PROGRAMMING MODES TABLE SV AT89C1051 AT89C1051 RST V,wYPp XTAL 1 GND RST GND Flash Programming and Verification Characteristics TA = 21°C to 27°C, VCC = 5.0± 10% Symbol Parameter Min Max Units Vpp Programming Enable Voltage 11.5 12.5 V Ipp Programming Enable Current 250 ~A tOVGL Data Setup to PROG Low 1.0 ~s tGHOX Data Hold After PROG 1.0 ~s tEHSH P3.4 (ENABLE) High to Vpp 1.0 ~s tSHGL Vpp Setup to PROG Low 10 ~s tGHSL Vpp Hold After PROG 10 tGLGH PROGWidth 1 tELQV ENABLE Low to Data Valid tEHQZ Data Float After ENABLE tGHBL PROG High to BUSY Low 50 ns twc Byte Write Cycle Time 2.0 ms 0 ~s 110 ~s 1.0 ~s 1.0 ~s tBHIH RDY/BSY to Increment Clock Delay 1.0 ~s tlHIL Increment Clock High' 200 ns 3-10 AT89C1051 AT89C1051 Flash Programming and Verification Waveforms PORT 1 P3.2 (PROG) RST (Vpp) P3.4 (ENABLE) P3._1_ (RDY/BSy) • READY -tIHIH ~ XTAL1 (INCREMENT ADDRESS) tBHIH -------------------------------------- Absolute Maximum Ratings· Operating Temperature ................... -55°C to +125°C Storage Temperature ...................... -65°C to + 150°C Voltage on Any Pin with Respect to Ground ................... -1.0 V to +7.0 V 'NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage ............................ 6.6 V DC Output Current ....................................... 25.0 mA 3-11 D.C. Characteristics TA = -40°C to 85°C, Vee = 2.7 V to 6.0 V (unless otherwise noted) Symbol Parameter VIL Input Low Voltage VIH Input High Voltage Condition (Except XTAL 1, RST) VIHl Input High Voltage (XTAL1, RST) VOL Output Low Voltage(l) (Ports 1, 3) IOL = 20 rnA, Vee = 5 V IOL = 10 rnA, Vee = 2.7 V VOH Output High Voltage (Ports 1,3) IOH = -80 ~A, Vee = 5 V ± 10% Min Max -0.5 0.2 Vee-0.1 V 0.2 Vee+0.9 Vee+0.5 V 0.7 Vee Vee+0.5 V 0.50 V Units 2.4 V IOH = -30 ~A 0.75 Vee V IOH = -12 ~A 0.9 Vee V IlL Logical 0 Input Current (Ports 1, 2, 3) VIN = 0.45 V -50 ~ ITL Logical 1 to 0 Transition Current (Ports 1, 2, 3) VIN=2 V -750 ~A III Input Leakage Current (Port P1.0, P1.1) o a..Il.Q.Q. 27 2S 2S 24 (AD') (ADS) (ADS) (AD7) P2.7 (A1S) P2.6 (A14) P2.S (A13) (RXD) (TXO) (iN'fO) (INT1) (TO) ------ ...... "': ~ ~ '""; '=! 0 ~ '""; t'! ~ .................. 0 0 0 0 0 0 " - a.. a..a..a..a..z > a.. a.. a.. a.. P1.5 P1.6 Pt.7 AST P3.0 NC P3.1 P3.2 P3.3 P3.4 (T1) P3.S 1 4. PO.4 (AD4) PO.S (AD5) PO.6 (AD6) PO.7 (AD7) EAIVPP NC ALE/PROG PSEN ll619202l222324252627ia9 P2.7 (A15) P2.e (A14) P2.5 (A13) 0265E 3-33 AlmlL Block Diagram PO.O - PO.7 P2.0 - P2.7 , Vee - - ,: , D ':' ,,, ,, , , , , ,, , ,, ,, INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSEN AlEJPROG EA I VPf' RST TIMING AND CONTROL P1.0 - P1.7 3·34 AT89C51 P3.0 - P3.7 AT89C51 Description (Continued) designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description Vee Supply voltage. GND Ground. pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (hI.) because of the pullups. Port 3 also serves the functions of various special features of the ATS9C51 as listed below: Port Pin RXD (serial input port) P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 TXD (serial output port) INTO (extenal interrupt 0) INT1 (extenal interrupt 1) TO (timer 0 extenal input) T1 (timer 1 external input) WR (extenal data memory write strobe) RD (external data memory read strobe) P3.7 PortO Alternate Functions P3.0 Port 0 is an 8-bit open drain bidirectional YO port. As an output port each pin can sink eight TIL inputs. When I s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 3 also receives some control signals for Flash programming and programming verification. Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode PO has internal pullups. Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program verification. Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. Port 1 In normal operation ALE is emitted at a constant rate of 116 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. Port I is an S-bit bidirectional YO port with internal pull ups. The Port 1 output buffers can sink/source four TIL inputs. When Is are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (III.) because of the internal pullups. Port I also receives the low-order address bytes during Flash programming and program verification. RST ALE/PROG If desired, ALE operation can be disabled by setting bit 0 of SFR location SEH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcrontroller is in external execution mode: Port 2 PSEN Port 2 is an S-bit bidirectional YO port with internal pull ups. The Port 2 output buffers can sink/source four TIL inputs. When Is are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IlL) because of the internal pullups. Program Store Enable is the read strobe to external program memory. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting Is. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bidirectional YO port with internal pull ups. The Port 3 output buffers can sink/source four TIL inputs. When Is are written to Port 3 pins they are pulled high by the internal When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EAlVpp External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to Vcc for internal program executions. This pin also receives the 12-volt programming enable voltage (Vpp) during Flash programming, for parts that require 12-volt VPP. AIIDEL (continued) 3·35 Pin Description Power Down Mode (Continued) XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down isa hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before Vee is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Oscillator Characteristics XTALI and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTALI is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-bytwo flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Figure 1. Oscillator Connections C2 XTAL2 o C1 XTAL1 Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. GND Notes: Cl, C2 =30 pI> ± 10 pF for Crystals 40 pF ± 10 pF for Ceramic Resonators = Figure 2. External Clock Drive Configuration XTAL2 NC EXTERNAL OSCILLATOR - - - - I SIGNAL XTAL1 GND Status of External Pins During Idle and Power Down Mode Program Memory ALE PSEN PORTO PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data 3-36 AT89C51 AT89C51 Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: When lock bit I is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Lock Bit Protection Modes Program Lock Bits LB1 LB2 LB3 1 U U U No program lock features. Protection Type 2 p U U MOVC instructions executed from externalJllilgram memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled. 3 p P U Same as mode 2, also verify is disabled. 4 p P P Same as mode 3, also external execution is disabled. Programming the Flash The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (Vee) program enable signal. The low voltage programming mode provides a convenient way to program the AT89C5l inside the user's system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. = The AT89C51 is shipped with either the high-voltage or lowvoltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table. Vpp=12V Top-Side Mark Signature Vpp= 5 V AT89C51 xxxx AT89C51 xxxx-5 VVWW vvww (030H)=1EH (031 H)=51 H (032H)=FFH (030H)=1EH (031H)=51H (032H)=05H The A T89C51 code memory array is programmed byte-by-byte in either programming mode. To program any non-blank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps. I. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise ENVpp to 12 V for the high-voltage programming mode. 5. Pulse ALEIPROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDYIBSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB 1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALEIPROG low for \0 ms. The code array is written with all "1 "s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 3-37 Programming Interface 031H, and 03ZH, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion. = (030H) lEH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (03ZH) FFH indicates lZ V programming (03ZH) = 05H indicates 5 V programming = All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. Flash Programming Modes ALE! EAJ PROG Vpp P2.6 P2.7 P3.6 P3.7 H/12V(1) L H H H H H L L H H L 'cJ H/12V H H H H H L 'cJ Hl12V H H L L H L 'cJ H/12V H L H L Chip Erase H L 'cJ H/12V H L L L Read Signature Byte H L H H L L L L Mode RST PSEN Write Code Data H L 'cJ Read Code Data H L Bit -1 H Bit - 2 Bit - 3 Write Lock Notes: 3-38 (2) I. The signature by1e at location 032H designates whether Vpp 12 V orVpp= 5 V should be used to enable programming. = AT89C51 2. Chip Erase requires a 10 ms PROG pulse. AT89C51 Figure 3. Programming the Flash Figure 4. Verifying the Flash +5V +5V AT89C51 AT89C51 Vee Pl P2.0· P2.3 ADDR. OOOOH/OFFFH PGM DATA PO P2.7 ALE PROG P2.0- P2.3 PO P2.7 SEE FLASH PROGRAMMING MODES TABLE P3.6 ALE P3.6 V'H P3.7 P3.7 XTAL2 V,~pp EA 4-24 MHz 4-24 MHz D D XTAL 1 GND Vee P2.6 P2.6 SEE FLASH PROGRAMMING MODES TABLE Pl RST V'H PSEN XTAL2 EA XTAL 1 RST GND V'H PSEN ,. - Flash Programming and Verification Characteristics =5.0 ± 10% TA =21°C to 27°C, VCC Symbol Vpp(l) Parameter Min Max Programming Enable Voltage 11.5 12.5 V Ipp(l) Programming Enable Current 1.0 mA 24 MHz 1ltCLCL Oscillator Frequency tAVGL Address Setup to PROG Low 48tCLCL tGHAX Address Hold After PROG 48tCLCL tDVGL Data Setup to PROG Low 48tCLCL tGHDX Data Hold After PROG 48tCLCL tEHSH P2.7 (ENABLE) High to Vpp 48tCLCL tSHGL tGHSL(l) Vpp Setup to PROG Low 10 Vpp Hold After PROG 10 tGLGH PROG Width 1 tAVQV Address to Data Valid tELOV ENABLE Low to Data Valid tEHQV Data Float After ENABLE tGHBL PROG High to BUSY Low twc Note: Byte Write Cycle Time 1. Only used in l2-volt programming mode. 4 Units ~s ~s 110 ~s 48tCLCL 48tCLCL 0 48tCLCL 1.0 ~s 2.0 ms 3-39 Flash Programming and Verification Waveforms - High Voltage Mode PROGRAMMING ADDRESS P1.0 - P1.7 P2.0 - P2.3 VERIFICATION PORTO ALE/PROG EAlVpp ~ (ENABLE) P3~ READY (RDY/BSY) Flash Programming and Verification Waveforms - Low Voltage Mode P1.0 - P1.7 P2.0 - P2.3 PROGRAMMING VERIFICATION ADDRESS ----------~====1A~D~D~R~ES~S~====i PORTO DATA OUT ALE/PROG _______ EAlVpp LOGIC 1 ~9~!~Q __________________ _ ~ (ENABLE) P3~ READY (RDYIBSY) 3-40 AT89C51 AT89C51 Absolute Maximum Ratings* "NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature ................... -55°C to + 125°C Storage Temperature ...................... -65°C to + 150°C Voltage on Any Pin with Respect to Ground ................... -1.0 V to +7.0 V Maximum Operating Voltage ............................ 6.6 V DC Output Curren!.. ..................................... 15.0 mA D.C. Characteristics TA = -40°C to 85°C, Vee = 5.0 V ± 20% (unless otherwise noted) Symbol Parameter Condition Min Max Units VIL Input Low Voltage (Except EA) -0.5 0.2 Vee-0.1 V VIL1 Input Low Voltage (EA) -0.5 0.2 Vee-0.3 V VIH Input High Voltage (Except XTAL 1, RST) 0.2 Vee+0.9 Vee+0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7 Vee Vee+0.5 V VOL Output Low Voltage(1) (Ports 1,2,3) IOl= 1.6 mA 0.45 V VOL1 Output Low Voltage(1) (Port 0, ALE, PSEN) IOl=3.2 mA 0.45 V VOH Output High Volta~ (Ports 1,2,3, ALE, PSEN) Output High Voltage (Port 0 in External Bus Mode) VOH1 IOH = -60 1lA, Vee = 5 V ± 10% 2.4 V IOH = -25 ~IA 0.75 Vee V IOH = -10 JlA 0.9 Vee V 2.4 V IOH = -300 JlA 0.75 Vee V IOH = -80 IlA 0.9 Vee V IOH = -800 JlA, Vee = 5 V ± 10% ill Logical 0 Input Current (Ports 1,2,3) VIN = 0.45 V -50 JlA III Logical 1 to 0 Transition Current (Ports 1,2,3) VIN = 2V -650 JlA III Input Leakage Current (Port 0, EA) 0.45 < VIN < Vee ±10 JlA RRST Reset Pulldown Resistor 300 Kn CIO Pin Capacitance Power Supply Current 10 pF Active Mode, 12 MHz 20 mA 5 mA Vee=6 V 100 IlA Vee=3V 40 JlA Idle Mode, 12 MHz Icc Power Down Mode(2) Notes: 50 Test Freq. = 1 MHz, TA = 25°C 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: lOrnA Maximum IOL per B-bit port: Port 0:26 rnA Ports 1,2, 3:!5 rnA Maximum total IOL for all output pins:7! rnA 2. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. Minimum VCC for Power Down is 2 V. 3-41 A.C. Characteristics (Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN other outputs =80 pF) =100 pF; Load Capacitance for all External Program and Data Memory Characteristics 12 MHz Oscillator 16 to 24 MHz Oscillator Symbol Parameter 1/tCLCL Oscillator Frequency tLHLL ALE Pulse Width 127 2tCLCL-40 ns tAVLL Address Valid to ALE Low 28 tCLCL-13 ns tLLAX Address Hold After ALE Low 48 tLLlV ALE Low to Valid Instruction In tLLPL ALE Low to PSEN Low 43 tCLCL-13 tPLPH PSEN Pulse Width 205 3tCLCL-20 tPLIV PSEN Low to Valid Instruction In tPXIX Input Instruction Hold After PSEN tPXIZ Input Instruction Float After PSEN tPXAV PSEN to Address Valid tAVIV Address to Valid Instruction In Min Max Min Max Units 0 24 MHz 4tCLCL-65 145 0 75 ns tCLCL-8 5tCLCL-55 ns 10 10 ns PSEN Low to Address Float 400 6tCLCL-100 twLWH WR Pulse Width 400 6tCLCL-100 Data Hold After RD ns 312 RD Pulse Width RD Low to Valid Data In ns ns tCLCL-10 tRLRH tRHDX ns 0 59 ns ns 3tCLCL-45 tpLAZ tRLDV ns tCLCL-20 233 252 0 ns ns 5tCLCL-90 ns ns 0 tRHDZ Data Float After RD 97 2tCLCL-28 ns tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns 9tCLCL-165 ns tAVDV Address to Valid Data In tLLWL ALE Low to RD or WR Low 200 585 tAVWL Address to RD or WR Low 203 300 3tcLCL-50 3tCLCL+50 ns 4tCLCL-75 ns ns tovwx Data Valid to WR Transition 23 tCLCL-20 tOVWH Data Valid to WR High 433 7tCLCL-120 ns tWHOX Data Hold After WR 33 tCLCL-20 ns tRLAZ RD Low to Address Float tWHLH RD or WR High to ALE High 3-42 AT89C51 0 43 123 tCLCL-20 0 ns tCLCL+25 ns AT89C51 External Program Memory Read Cycle ALE PSEN ~-~l---+----+I tlLlv r---t--+----'"'~ ~---+I IpLiv tpLAZ AO-A7 PORTO AS-A15 PORT 2 AS-A15 External Data Memory Read Cycle ALE RD INSTR IN PORTO ~---- IAVDV PORT 2 P2.0 - P2.7 OR AS - A15 FROM DPH AS - A15 FROM PCH 3-43 External Data Memory Cycle ALE INSTR IN PORTO ~-----~~L ----~ P2.0 - P2.7 OR A8 - A15 FROM DPH PORT 2 A8 - A15 FROM PCH External Clock Drive Waveforms tCHCX 0.45 V External Clock Drive Symbol Parameter Min Max Units l/tClCl Oscillator Frequency 24 MHz tClCl Clock Period tCHCX High Time tClCX Low Time 0 41.6 15 15 tClCH Rise Time tCHCl Fall Time 3·44 ns ns ns 20 20 AT89C51 ns ns AT89C51 Serial Port Timing: Shift Register Mode Test Conditions (VCC = 5.0 V ± 20%; Load Capacitance = 80 pF) 12 MHzOsc Variable Oscillator Symbol Parameter Min Min tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL !!s tQVXH Output Data Setup to Clock Rising Edge 700 1OtCLCL-133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-33 ns tXHDX Input Data Hold After Clock Rising Edge 0 0 tXHDV Clock Rising Edge to Input Data Valid Max Max Units ns 1OtCLCL-133 700 ns • Shift Register Mode Timing Waveforms INSTRUCTION o 2 3 4 5 6 7 8 ALE CLOCK ,WRITE TO SBU~ .- OUTPUT DATA , CLEARRI , ... SETRlt INPUT DATA AC Testing Input/Output Waveforms (I) Float Waveforms (I) V OL-O.1 0.2 Vcc + 0.9 V TEST POINTS VLOAO -----< Note: 1. AC Inputs during testing are driven at Vee - 0.5 V for a logic I and 0.45 V for a logic O. Timing measurements are made at VIH min. for a logic I and VIL max. for a logicO. liming Reference Points V OL+O.1 0.45 V Note: V V 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a I ()() mV change from the loaded VoWVoLieveloccurs. 3-45 Ordering Information Speed Power (MHz) Supply 12 SV±20% S V±10% 16 20 24 SV±20% SV±20% SV±20% Ordering Code Package AT89CS1-12AC AT89CS1-12JC AT89CS1-12PC AT89CS1-120C. 44A 44J 40P6 440 Commercial (O°C to 70°C) AT89CS1-12AI AT89CS1-12JI AT89CS1-12PI AT89CS1:1201 44A 44J 40P6 440 Industrial (-40°C to 8S0C) AT89CS1-12AA AT89CS1-12JA AT89CS1-12PA . AT89CS1-120A 44A 44J 40P6 440 Automotive (-40°C to 12S°C) AT89CS1-120M AT89CS1-12LM 4006 44L Military (-SSOC to 12S°C) AT89CS1-120M/883 AT89CS1-12LM/883 4006 44L Military/883C Class B, Fully Compliant (-SSOC to 12S0C) AT89CS1-16AC . AT89CS1-16JC AT89CS1-16PC· AT89CS1-160C 44A 44J 40P6 440 Commercial (O°C to 70°C) AT89CS1~16AI AT89CS1-16JI AT89CS1-16PI AT89CS1-1601 44A 44J 40P6 440 Industrial (-40°C to 8S0C) AT89CS1-16AA AT89CS1-16JA AT89CS1-16PA AT89CS1-160A 44A 44J 40P6 440 Automotive (-40°C to 12S°C) AT89CS1 "20AC AT89CS1-20JC AT89CS1-20PC AT89CS1-200C 44A 44J 40P6 440 Commercial (O°C to 70°C) AT89CS1-20AI AT89CS1-20JI AT89CS1-20PI AT89CS1-2001 44A 44J 40P6 440 Industrial (-40°C to 8S0C) AT89CS1-24AC AT89CS1-24JC AT89CS1-24PC AT89CSt-240C 44A 44J 44P6 440 Commercial (O°C to 70°C) AT89CSH!4AI AT89CS1-24JI AT89CS1"24PI AT89CS1-2401 44A 44J 44P6 440 Industrial (-40°C to 8S0C) Operation Range AT89C5t _ _ _ _ _ _ _ _ _ _ __ 3-46 AT89C51 Ordering Information Package Type 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 4006 40 Lead, 0.600" Wide, Non-Windowed, Ceramic Duallnline Package (Cerdip) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 44L 44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 40P6 44Q 40 Lead, 0.600" Wide, Plastic Duallnline Package (PDIP) 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP) • 3-47 3-48 AT89C51 _ _..._ _ _ _ _ _ _ __ AT89LV51 Features • • • • • • • • • • • Compatible with MCS-S1TM Products 4 Kbytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles 2.7 V to 6 V Operating Range Fully Static Operation: 0 Hz to 12 MHz Three-Level Program Memory Lock 128 x 8-Bit Internal RAM 32 Programmable 110 Lines Two 16-Bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low Power Idle and Power Down Modes 8-Bit Microcontroller with 4 Kbytes Flash Description The AT89LVSl is a low-voltage, high-performance CMOS 8-bit microcomputer with 4 Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel's high density nonvolatile memory technology and is compatible with the industry standard MCS-Sl ™ instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89LVSl is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89LVSl provides the following standard features: 4 Kbytes of Flash, 128 bytes of RAM, 32 YO lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89LVSl is (continued) Pin Configurations PDIP vee P1.0 P1.1 P1.2 P1.3 pO.a (ADO) PO.1 (AD1) PO.2 (AD2) PO.3 (AD3) pa.4 (AD4) P1.4 P1.5 P1.6 P1.7 AST PO.S (ADS) PO.6 (AD6) PO.7 (AD7) EAtVPP (AX D) P3.a CTXO) P3.1 (INTO) P3.2 (INT1) P3.3 (TO) paA eT1) P3.S (WA) P3.6 (RIl) P3.7 XTAL2 ALE/PROG PSEN P2.7 CA1S) P2.e P2.S P2.4 P2.3 P2.2 P2.1 P2.C XTAL1 POFPfTOFP GND (A14) (A13) (A12) (A11) (A10) (AS) (AB) O_NC"J INDEX ococ ~~~.5. ci ci ~ ci PLCC 8 "'- r!a.-,:-a.!..J..!,a.\-,a...,a.~ZL±>-!-a.lJ..!-:a.!-,-a..l.!a.:!---, CORNER :: : ~ :; :; 0 444342414°393837363534 P1.5 P1.6 P1.7 AST (AXO) P3.a Ne (TXO) (INTO) (INn) (TO) (n) P3.1 P3.2 P3.3 P3.4 P3.S 33 32 31 30 2. 28 27 26 25 24 23 PO.4 (AD4) PO.5 (ADS) PO.6 (AD6) PO,7 (AD7) EAIVPP Ne ALE/PROG PSEN P2.7 (A1S) P2.6 (A14) P2.S (A13) POA (AD4) PO.S (ADS) PO.6 (AD6) PO.7 (AD7) EAIVPP P1.S P1.6 P1.7 AST (RXD) P3.0 Ne (TXD) P3.1 (IN''fi:i) P3.2 (iNT1) P3.3 (TO) P3.4 (n) P3.S Ne 15 16 'iB 1920212223242526272~9 ALE/PROG PSEN P2.7 (A1S) P2.6 (A14) P2.S (A13) 0303C AlmEl 3-49 Block Diagram po.o· PO.7 P2.o· P2.7 ,.. ---- .------- --- --- ------- -------Vee ---..,: GND ,, , P INTERRUPT. SERIAL PORT, AND TIMER BLOCKS PSEN ALEJPROG EA I Vpp RST TIMING AND CONTROL ,,, , , ,, , , , ,, , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _.1 P1.0· P1.7 3-50 AT89LV51 P3.0· P3.7 AT89LV51 Description (Continued) designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description Vee Supply voltage. GND Ground. PortO are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IlL) because of the pullups. Port 3 also serves the functions of various special features of the AT89LV51 as listed below: Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.S P3.6 P3.7 Alternate Functions RXD (serial input port) TXD (serial output port) INTO (extenal interrupt 0) INT1 (extenal interrupt 1) TO (timer 0 extenal input) T1 (timer 1 external input) WR (extenal data memory write strobe) RD (external data memory read strobe) Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TIL inputs. When Is are written to port 0 pins, the pins can be used as high-impedance inputs. Port 3 also receives some control signals for Flash programming and programming verification. Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode PO has internal pullups. Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TIL inputs. When Is are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (bL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and program verification. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TIL inputs. When Is are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IlL) because of the internal pullups. Port '2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting Is. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TIL inputs. When Is RST AlElPROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 116 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. PSEN Program Store Enable is the read strobe to external program memory. When the AT89LV51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EAlVpp External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to Vee for internal program executions. This pin also receives the 12-volt programming enable voltage (Vpp) during Flash programming, when 12-volt programming is selected. XTAll Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAl2 Output from the inverting oscillator amplifier. 3-51 • Oscillator Characteristics XTALI and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTALI is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-bytwo flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Figure 1. Oscillator Connections C2 XTAL2 D XTAL1 Idle Mode GND In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Notes: CI, C2 = 30 pF± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators Figure 2. External Clock Drive Configuration NC XTAL2 Power Down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before Vee is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. EXTERNAL OSCILLATOR - - - - I SIGNAL 1.. XTAL1 GND Status of External Pins During Idle and Power Down Mode Program Memory ALE PSEN PORTO PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data 3-52 AT89LV51 AT89LV51 Program Memory lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. lock Bit Protection Modes(1) Program Lock Bits 1 LB1 LB2 LB3 U U U Protection Type No program lock features. MOVe instructions executed from external.Q[9gram memory are disabled from 2 p U U fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled. 3 p p P P U P Same as mode 2, also verify is disabled. 4 Note: Same as mode 3, also external execution is disabled. I. The lock bits can only be erased with the chip erase operation. Programming the Flash The AT89LV51 is normally shipped with the on-chip Flash memory array in the erased state (i.e. contents=FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (5-volt) program enable signal. The low voltage programming mode provides a convenient way to program the AT89LV51 inside the user's system while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The AT89LV51 is shipped with either the High-Voltage or Low-Voltage programming mode enabled. The respective topside marking and device signature codes are listed below: Top-Side Mark Vpp=12V AT89LV51 xxxx YYWW. Signature (030H)=1EH (031 H)=61 H (032H)=FFH Data Polling: The AT89LVSl features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on PO.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. ReadylBnsy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY . Vpp=5 V AT89LV51 xxxx-5 . www (030H)=1EH (031 H)=61 H (032H)=05H The AT89LV51 code memory array is programmed byte-bybyte in either programming mode. To program any non-blank byte in the on-chip PEROM Code Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89LVSI, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89LVSI, the following sequence should be followed: I. 2. 3. 4. array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through S changing the address and data for the entire array or until the end of the object file is reached. Input the desired memory location on the address lines. Input the appropriate data byte on the data lines. Activate the correct combination of control signals. Raise EANpp to 12-V if in the high-voltage programming mode. S. Pulse ALEJPROG once to program a byte in the Flash Program Verify: If lock bits LBI and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array and the lock bits are erased electrically by using the proper combination of control signals and by holding ALEJPROG low for IO ms. The code array is written with all "I "s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values returned are: (030H) = lEH indicates manufactured by Atmel (03IH) = 61H indicates 89LVSI (032H) = FFH (High-Voltage) or OSH (Low-Voltage) programming mode AlmEl 3-53 • Programming Interface Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. Flash Programming Modes Mode ALE! EAI PROG Vpp P2.6 P2.7 P3.6 P3.7 H/12V(1) L H H H H L L H H H/12V H H H H '---.r H/12V H H L L L '---.r H/12V H L H L H L '---.r H/12V H L L L H L H L L L L RST PSEN Write Code Data H L Read Code Data H L Bit - 1 H L '---.r Bit- 2 H L Bit-3 H Chip Erase Read Signature Byte Write Lock Notes: H (2) 1. The signature byte at location 032H designates whether Vpp = 12 V or Vpp= 5 V should be used to enable programming. 3-54 '---.r AT89LV51 H 2. Chip Erase requires a 10 ms PROG pulse. AT89LV51 Figure 3. Programming the Flash Figure 4. Verifying the Flash +5V +5V AT89LV51 AT89LV51 AO·A7 ADDR. OOOOHlOFFFH Vee Pl P2.0 - P2.3 PGM DATA PO P2.6 SEE FLASH PROGRAMMING MODES TABLE Vee P2.0 - P2.3 PO P2.6 P2.7 ALE PROG P2.7 SEE FLASH PROGRAMMING MODES TABLE P3.6 ALE P3.6 P3.7 V,H P3.7 XTAL2 EA XTAL 1 RST GND Pl V,t!lJpp XTAL2 EA VIH XTAL 1 RST PSEN GND V,H PSEN - =- Flash Programming and Verification Characteristics =5.0 ± 10% TA =21°C to 27°C, VCC Symbol Vpp(l) Parameter Min Max Programming Enable Voltage 11.5 12.5 V Ipp(l) Programming Enable Current 25 IlA MHz 1/tCLCL Oscillator Frequency tAVGL Address Setup to PROG Low 48tCLCL tGHAX Address Hold After PROG 48tCLCL . tOVGL Data Setup to PROG Low 48tCLCL 4 12 tGHOX Data Hold After PROG 48tCLCL tEHSH P2.7 (ENABLE) High to Vpp 48tCLCL tSHGL tGHSL(l) Vpp Setup to PROG Low 10 Vpp Hold After PROG 10 tGLGH PROG Width 1 tAvOV Address to Data Valid tELOV ENABLE Low to Data Valid tEHOV Data Float After ENABLE tGHBL PROG High to BUSY Low 1.0 twc Byte Write Cycle Time 2.0 Note: Units Ils IlS 110 Ils 48tCLCL 48tCLCL 0 48tCLCL Ils ms I. Only used in 12-volt programming mode. 3-55 • Flash Programming and Verification Waveforms - High Voltage Mode PROGRAMMING ADDRESS P1.0 - P1.7 . P2.0 - P2.3 VERIFICATION ADDRESS PORTO DATA OUT ALE/PROG ~ (ENABLE) P3.4 READY (RDY/BSY) Flash Programming and Verification Waveforms - Low Voltage Mode PROGRAMMING ADDRESS P1.0-P1.7 P2.0 - P2.3 VERIFICATION ADDRESS PORTO DATA OUT tGHAX ALEIPROG _______ LOGIC 1 __________________ _ ENVpp ~9~!~Q P2.7 (ENABLE) tGHBL . P3.4 READY (RDY/BSY) a-56 AT89 LV51 AT89LV51 Absolute Maximum Ratings· Operating Temperature ................... -55°C to + 125°C Storage Temperature ...................... -65°C to + 150°C Voltage on Any Pin with Respect to Ground ................... -1.0 V to +7.0 V 'NOTICE: Stresses beyond those listed under '"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage ............................ 6.6 V DC Output Current... ................•................... 15.0 mA D.C. Characteristics TA = -40°C to 85°C, Vee = 2.7 V to 6.0 V (unless otherwise noted) Symbol Parameter Condition Min Max Units (Except EA) -0.5 0.2 Vee-0.1 V -0.5 0.2 Vee-0.3 V 0.2 Vee+0.9 Vee+0.5 V 0.7 Vee Vee+0.5 V = 1.6 mA 0.45 V IOL=3.2 mA 0.45 V VIL Input Low Voltage VIL1 Input Low Voltage (EA) VIH Input High Voltage (Except XTAL 1, RST) VIH1 Input High Voltage (XTAL1, RST) VOL Output Low Voltage(1) (Ports 1,2,3) IOL VOL1 Output Low Voltage(1) (Port 0, ALE, PSEN) VOH Output High Volta~ (Ports 1,2,3, ALE, PSEN) Output High Voltage (Port 0 in External Bus Mode) VOH1 2.4 V IOH = -20 !LA 0.75 Vee V IOH = -10 !LA 0.9 Vee V 2.4 V IOH = -300 /LA 0.75 Vee V IOH =-80 !LA 0.9 Vee V IOH = -60 /LA, Vee = 5 V ± 10% IOH = -800 /LA, Vee = 5 V ± 10% ilL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45 V ITL Logical 1 to 0 Transition Current (Ports 1,2,3) III Input Leakage Current (PortO, EA) RRST Reset Pulldown Resistor CIO Pin Capacitance Power Supply Current Icc Power Down Mode(2) Notes: -50 !LA VIN=2V -650 /LA 0.45 < VIN < Vee ±10 IlA 300 KQ 50 Test Freq. = 1 MHz, TA = 25°C Active Mode, 12 MHz, Vee = 6 V/3 V 10 pF 20/5.5 mA Idle Mode, 12 MHz, Vee = 6 V/3 V 5/1 mA Vee=6V 100 /LA Vee=3 V 20 /LA I. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 rnA Maximum IOL per 8-bit port: Port 0:26 rnA Ports 1,2,3:15 rnA Maximum total IOL for all output pins:71 rnA 2. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. Minimum vee for Power Down is 2 V. 3·57 ·JL A.C. Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN other outputs =80 pF. =100 pF; load capacitance for all External Program and Data Memory Characteristics 12 MHz Oscillator Symbol Parameter Min Max Variable Oscillator Min Max Units 0 12 MHz 1/tCLCL Oscillator Frequency tLHLL ALE Pulse Width 127 2tCLCL-40 ns tAVLL Address Valid to ALE Low 28 tCLCL-25 ns tLLAX Address Hold After ALE Low 48 tCLCL-25 tLLlv ALE Low to Valid Instruction In tLLPL ALE Low to PSEN Low tPLPH PSEN Pulse Width tPLIV PSEN Low to Valid Instruction In tPXIX Input Instruction Hold After PSEN tPXIZ Input Instruction Float After PSEN tPXAV PSEN to Address Valid tAVIV Address to Valid Instruction In 312 5tCLCL-80 ns tpLAZ PSEN Low to Address Float 10 10 ns tRLRH RD Pulse Width 400 6tCLCL-100 twLWH WR Pulse Width 400 6tCLCL-100 tRLDV RD Low to Valid Data In tRHDX Data Hold After RD tRHDZ Data Float After RD 97 2tCLCL-28 ns tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns tAVDV Address to Valid Data In 585 9tCLCL-165 ns tLLwL ALE Low to RD or WR Low 200 tAVWL Address to RD or WR Low 203 tovwx Data Valid to WR Transition tOVWH Data Valid to WR High twHOX Data Hold After WR 33 tCLCL-25 tRLAZ RD Low to Address Float twHLH RD or WR High to ALE High 3·58 AT89LV51 233 43 ns 4tcLCL-65 205 ns 3tCLCL-45 145 0 3tCLCL-60 75 tCLCL-25 0 ns ns 5tCLCL-90 3tCLCL-50 ns ns 0 300 ns ns tCLcL-8 252 ns ns 0 59 ns ns tCLcL-25 3tCLCL+50 ns 4tCLCL-75 ns 23 tCLCL-30 ns 433 7tCLCL-120 ns 0 43 123 tCLCL-25 ns 0 ns tCLCL+25 ns I.. · _ _ _ _ _ _ _ _ _ _ _ _ _ _ AT89LV51 External Program Memory Read Cycle ALE 14--~J----t---+I tLLIV 14---.1 tpLiV tPLAZ AO-A7 PORTO 14---- tAVIV AO-A7 ---+I • AS-A15 AS - A15 PORT 2 External Data Memory Read Cycle ALE tWHLH AO - A7 FROM PCl PORTO INSTR IN 1 4 - - - - tAVWL - - - - + I 1+----PORT 2 tAVDV ----+I P2.0 - P2.7 OR AS - A15 FROM DPH AS - A15 FROM PCH 3-59 External Data Memory Cycle ALE WR INSTR IN PORTO P2.0 - P2.7 OR A8 - A15 FROM DPH PORT 2 A8 - A15 FROM PCH External Clock Drive Waveforms 0.45 V ~------ tCLCL External Clock Drive TA = _40°C to 85°C Min Symbol Parameter Vee = 2.7 V VCC= 3.0 V Max VCC= 3.3 V VCC= 2.7 V VCC= 3.0V VCC= 3.3 V Units 12 16 20 MHz 1/tCLCl Oscillator Frequency 0 0 0 tClCl Clock Period 83.3 62.5 50 ns tCHCX High Time 20 15 10 ns tCLCX Low Time 20 15 10 tClCH Rise Time 20 15 10 ns tCHCL Fall Time 20 15 10 ns 3-S0 AT89LV51 ns AT89LV51 Serial Port Timing: Shift Register Mode Test Conditions (VCC = 2.7 V to 6 V; load Capacitance = 80 pF) 12MHzOsc Variable Oscillator Symbol Parameter Min Min tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL tOVXH Output Data Setup to Clock Rising Edge 700 1OtCLCL-133 J.1s ns tXHOX Output Data Hold After Clock Rising Edge 50 2tCLCL-117 ns tXHDX Input Data Hold After Clock Rising Edge 0 0 tXHDV Clock Rising Edge to Input Data Valid Max Max ns 10tClCL-133 700 Units ns • Shift Register Mode Timing Waveforms INSTRUCTION ALE CLOCK ,WRITE TO SBUF, + OUTPUT DATA , CLEARRI , ... INPUT DATA AC Testing Input/Output Waveforms (1) Float Waveforms (I) Vcc -0.5V V OL -o· 1V vLOAD ----< Timing Reference Points 0.45 V Note: I. AC Inputs during testing are driven at 2.4 V for a logic "I" and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "I" and 0.8 V for a logic "0." Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VoWVOLleveloccurs. 3-61 AlmEL AT89LV51 ICC (mA) 24~ TYPICAL ICC (ACTIVE) at 2SoC ____~__~____~____~____~__- - . vee=6.0V 20+-____~--~----_+--~~----~_=~ 16+-____~--~----_+--~~----~--~ O+-----r---~----_+----_r----~--~ o 4 12 16 20 24 8 F (MHz) AT89LV51 TYPICAL ICC (IDLE) at 2SoC ICC (mA) 4.8 vee =6.0V 4.0 3.2 2.4 1.6 0.8 0.0 0 4 8 12 16 20 24 F (MHz) 3·62 AT89LV51 _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AT89LV51 AT89LV51 TYPICAL ICCvs. VOLTAGE - POWER DOWN (85°C) 20~----------~--------~----------~ I 15T-----------r---------~----~~--~ C C10T-----------r---~~--~----------~ • J.l A5-+-------....,..,.=-------r-----------+----------~ OT-----------r---------~----------~ 3.0V 4.0V 5.0V 6.0V Vee VOLTAGE 3-63 Ordering Information Speed Power (MHz) Supply 12 2.7Vt06 V Ordering Code Package AT89LV51-12AC AT89LV51-12JC AT89LV51-12PC AT89LV51-120C 44A 44J 40P6 440 Ordering Information Package Type 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600" Wide, Plastic Duallnline Package (PDIP) 44Q 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP) 3-64 AT89LV51 Operation Range Commercial (OCC to 70 CC) AT89C52 Features • • • • • • • • • • Compatible with MCS-51 ™Products a Kbytes of In-System Reprogrammable Flash Memory Endurance: 1,000 WriteiErase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-Level Program Memory Lock 256 x a-Bit Internal RAM 32 Programmable 110 Lines Three 16-Bit Timer/Counters Eight Interrupt Sources Programmable Serial Channel Low Power Idle and Power Down Modes Description The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8 Kbytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel's high density nonvolatile memory technology and is compatible with the industry standard 80C5l and 80C52 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. 8-Bit Microcontroller with 8 Kbytes Flash The AT89C52 provides the following standard features: 8 Kbytes of Flash, 256 bytes of RAM, 32110 lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C52 is (continued) PDIP/Cerdip Pin Configurations vee (T2) P1.0 (T2 EX) P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (iNfO) PS.2 (lNT1) P3.3 (TO) P3.4 PO.D (ADO) PO.l (AD1) PO.2 (AD2) PO.3 (AD3) PO.4 (A04) PO.S (ADS) PO.S (ADS) PO.7 (AD7) EA/VPP Al.E/PROG PSEN P2.7 (A1S) P2.6 (A14) P2.S (A13) P2.4 (A12) P2.3 (All) P2.2 (Al0) P2.1 (A9) P2.0 (AS) (Tl) P3.5 (WIl) P3.6 (AD) P3.7 XTAL2 POFPITOFP f.1 O~(\II.") NN !::.!::. INDEX CORNER XTAll GND .t":I(\I .... O 0000 ~:5.:5.~ OO .... ~ 10 11 1213141516171819202122 co"'" (\I'" 000'" :: : ~ 33 32 31 30 2. 28 27 26 25 2. 23 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INTO) P3.2 (INT1) P3.3 ..... (',1'" :!.:!.:!.~ INDEX CORNER 444342414°393837363534 P1.6 (T1) P3.S 0 0000 c..a.a.o..a..z>a.a.a.c. P1.S (TO) P3., PLCC/LCC C\lt") "':"':"':"';"':000000 PO.4 (A04) PO.5 (AD5) PO.6 (AD6) PO.7 (AD7) EANPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.S (A13) P1.5 ~ :::: () g ci ~ ~ ci c..c..c..c..c..Z>c..c..c..c.. 1 43 P1.6 P1.7 AST (RXD) P3.0 Ne (TXD) P3.1 (iNfO) P3.2 (INT1) P3.3 (TO) P3.4 (T1) P3.S liB 192021222324252S27l89 POA (AD4) PO.5 (AD5) PO.S (ADS) PO.7 (AD7) EAIVPP NC ALE/PAOG PSEN P2.7 (A1S) P2.6 (A14) P2.5 (A13) (\I "' ..... ~~~S~~~~~~~ I~I~X . . . . . x .~~§'~~ . . . . . :5.::.::. 03I3E 3-65 • Block Diagram PO.O - PO.7 P2.0 - P2.7 Vee ----,: ,, GND : Ii ': , ,,, , ,, , ,, ,,, , INTERRUPT, SERIAL PORT, AND l1MER BLOCKS PSEN ALEJPROG EA IV.. RST l1:~G CONTROL INSTRUCllON REGISTER I+--.L...-r--"----I-----'L--T"--....J--~ P1.0 - P1.7 3-66 AT89C52 P3.0 - P3.7 AT89C52 Description (Continued) designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset. Vee Supply voltage. GND Ground. Port 0 is an 8-bit open drain bidirectional 110 port. As an output port, each pin can sink eight TIL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, PO has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull ups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional 110 port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When Is are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IlL) because of the internal pull ups. In addition, Pl.O and Pl.l can be configured to be the timer/counter 2 external count input (Pl.0!f2) and the timer/counter 2 trigger input (Pl.lIT2EX), respectively, as shown in the following table. P1.1 Port 3 Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. PortO P1.0 Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 is an 8-bit bidirectional 110 port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When Is are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Pin Description Port Pin memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull ups when emitting Is. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Functions RXD (serial input port) TXD (serial output port) INTO (external interrupt 0) INT1 (external interrupt 1) TO (timer 0 external input) T1 (timer 1 external input) WR (extemal data memory write strobe) RD (external data memory read strobe) Port 3 also receives some control signals for Flash programming and programming verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALEIPROG Alternate Functions Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. T2 (external count input to Timer/Counter 2), clock-out T2EX (Timer/Counter 2 capture/reload trigger and direction control) In normal operation, ALE is emitted at a constant rate of 116 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. Port 1 also receives the low-order address bytes during Flash programming and program verification. Port 2 Port 2 is an 8-bit bidirectional 110 port with internal pullups. The Port 2 output buffers can sink/source four TIL inputs. When Is are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IlL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcrontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to ex(continued) ternal data memory. AllDEl 3-67 • Pin Description Special Function Registers (Continued) EANpp External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that iflock bit I is programmed, EA will be internally latched on reset. EA should be strapped to Vee for internal program executions. This pin also receives the l2-volt programming enable voltage (Vpp) during Flash programming when 12-volt programming is selected. XTALI Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write Is to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always beO. Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOn (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. (continued) Output from the inverting oscillator amplifier. Table 1 A T89C52 SFR M ap and Reset V al ues OFSH OFOH OFFH B 00000000 OF7H OESH OEOH OEFH ACC 00000000 OE7H OOSH OOOH OCSH OOFH PSW 00000000 T2CON 00000000 007H T2MOO XXXXXXOO RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 OCFH OCOH OC7H IP XXOOOOOO P3 OBOH 11111111 IE OASH OXOOOOOO P2 OAOH 11111111 SCON SBUF 9SH 00000000 XXXXXXXX P1 90H 11111111 TCON TMOO TLO SSH 00000000 00000000 00000000 PO SP OPL SOH 11111111 00000111 00000000 OBFH OBSH 3·68 AT89C52 OB7H OAFH OA7H 9FH 97H TL1 00000000 OPH 00000000 THO 00000000 TH1 00000000 SFH PCON OXXXOOOO S7H AT89C52 Table 2. T2CON-Timer/Counter 2 Control Register T2CON Address =OC8H Reset Value =0000 OOOOB Bit Addressable Bit Symbol Function TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK 1 or TCLK 1. EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK causes Timer 1 overflow to be used for the receive clock. TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK causes Timer 1 overflows to be used for the transmit clock. EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative causes Timer 2 transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 to ignore events at T2EX. = = =a =a =a =1 starts the timer. = a for timer function. CIT2 = 1 for external event TR2 Start/Stop control for Timer 2. TR2 cm Timer or counter select for Timer 2. CIT2 counter (falling edge triggered). CPIRL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 1. CPfRL2 = causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 1. When either RCLK or TCLK 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. = a = = Special Function Registers (Continued) Interrupt Registers The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the W register. Data Memory The A T89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location OAOH (which is P2). MOV OAOH, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where RO contains OAOH, accesses the data byte at address OAOH, rather than P2 (whose address is OAOH). MOV @RO, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space. 3·69 • Timer 0 and 1 Capture Mode Timer 0 and Timer 1 in the AT89CS2 operate the same way as Timer 0 and Timer 1 in the AT89CSI. In the capture mode, two options are selected by bit EXEN2 in TICON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit 1F2 in TICON. This bit can then be used to generate an interrupt. If EXEN2 = I, Timer 2 performs the same operation, but a I-to-O transition at external input TIEX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in TICON to be set. The EXF2 bit, like 1F2, can generate an interrupt. The capture mode is illustrated in Figure 1. Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit cm in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in TICON, as shown in Table 3. Timer 2 consists of two 8-bit registers, 11:12 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1112 of the oscillator frequency. In the Counter function, the register is incremented in response to a I-to-O transition at its corresponding external input pin, TI. In this function, the external input is sampled during SSP2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3PI of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a I-to-O transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. Table 3. Timer 2 Operating Modes RCLK+TCLK CPIRL2 TR2 MODE 0 0 1 16-Bit Auto-Reload 0 1 1 16-Bit Capture 1 X 1 Baud Rate Generator X X 0 (Oft) Auto-Reload (Up or Down Counter) Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the TIEX pin. Figure 2 shows Timer 2 automatically counting up when DCEN =O. In this mode, two options are selected by bit EXEN2 in TICON. If EXEN2 = 0, Timer 2 counts up to OFFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in RCAP2H and RCAP2L are preset by software. If EXEN2 = I, a 16-bit reload can be triggered either by an overflow or by a I-to-O transition at external input TIEX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. A logic I at TIEX makes Timer 2 count up. The timer will overflow at OFFFFH and set the 1F2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, 11:12 and TL2, respectively. (continued) Figure 1. Timer 2 in Capture Mode Df-------'! CfT2 = 1 T2PIN T2EX PIN 3-70 AT89C52 _ _ _ _ _ _ _ _ _ _ __ AT89C52 Auto-Reload (Up or Down Counter) (Continued) A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and 11..2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes OFFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. Figure 2. Timer 2 Auto Reload Mode (DCEN =0) OVERFLOW TR2 Dr-------.Jj CfT2 = 1 TIMER 2 INTERRUPT T2PIN T2EX PIN Table 4. T2MOD-Timer 2 Mode Control Register T2MOD Address =OC9H Reset Value =XXXX XXOOB Not Bit Addressable Bit I~ Symbol I~ I~ I~ 13 I~ Function - Not implemented, reserved for future use. 1'20E Timer 2 Output Enable bit. DCEN When set, this bit allows Timer 2 to be configured as an up/down counter. AlmEL 3-71 • Figure 3. Timer 2 Auto Reload Mode (DCEN = 1) (DOWN COUNTING RELOAD VALUE) 0---1crn TOGGLE = 1 T2 PIN (UP COUNTING RELOAD VALUE) COUNT DIRECTION 1=UP O=DOWN T2EX PIN Figure 4. Timer 2 in Baud Rate Generator Mode TIMER 1 OVERFLOW "1" NOTE: OSC. FREQ. IS DIVIDED BY 2. NOT 12 ········SMOD1 Ol-------'!crn = 1 T2 PIN TRANSITION DETECTOR T2EXPIN~ ~ I, :, ~I ~' :.. . CONTROL EXEN2 AT89C52 . ~, EXF2 IL-----. r TIMER 2 INTERRUPT AT89C52 Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in TICON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer I is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 4. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TII2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes I and 3 are determined by Timer 2's overflow rate according to the following equation. Modesl and 3 Baud Rates = Timer 2 O~~rflow Rate The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (Cpm = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1112 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 112 the oscillator frequency). The baud rate formula is given below. Modesl and 3 Baud Rate Oscillator Frequency 32 x [65536 - (RCAP2H, RCAP2L)] where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK = I in T2CON. Note that a rollover in TII2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a I-to-O transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TII2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = \) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Figure 5. Timer 2 in Clock-Out Mode Pl.D (T2) T20E (T2MOD.l) ________ ~ (T:dx) TRANSITION DETECTOR 0-----11----<1>--+-1---+l~1 EXF2 I--_ _.. ~ TIMER 2 INTERRUPT EXEN2 3·73 3 Programmable Clock Out A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regular 110 pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit CIT2 (TICON.I) must be cleared and bit TIOE (T2MOD.I) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation. Clock-Out Frequency = Oscillator Frequency 4 x [65536 - (RCAP2H, RCAP2L)] Table 5. Interrupt Enable (IE) Register Enable Bit Enable Bit Symbol =1 enables the interrupt. =0 disables the interrupt. Position EA 1E.7 Function Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. - 1E.6 Reserved. In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. ETI 1E.5 Timer 2 interrupt enable bit. ES lEA Serial Port interrupt enable bit. ETl 1E.3 Timer 1 interrupt enable bit. EXI 1E.2 External interrupt 1 enable bit. ETO IE.J Timer 0 interrupt enable bit. UART EXO IE.O External interrupt 0 enable bit. The UART in the AT89C52 operates the same way as the UART in the AT89C51. User software should never write 1s to unimplemented bits, because they may be used in future AT89 products. Figure 6. Interrupt Sources Interrupts The AT89C52 has a total of six interrupt vectors: two external interrupts (INTO and INTI), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 6. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 5 shows that bit position 1E.6 is unimplemented. In the AT89C51, bit position 1E.5 is also unimplemented. User software should not write Is to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TFO and TFI, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows. INTO TFO------------------------------.~ INTl TFl n RI TF2 EXF2 3·74 AT89C52 ~ D D ~ ~ AT89C52 Figure 7. Oscillator Connections Oscillator Characteristics XTALl and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTALI is driven, as shown in Figure 8. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-bytwo flip-flop, but minimum and maximum voltage high and low time specifications must be observed. C2 \I XTAL2 " Cl \I XTALl " GND Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory. • Notes: Cl, C2 = 30 pF ± 10 pF for Crystals =40 pF ± 10 pF for Ceramic Resonators Figure 8. External Clock Drive Configuration XTAL2 NC Power Down Mode In the power down mode, the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before Vee is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. EXTERNAL OSCILLATOR - - - - - I SIGNAL XTALl GND Status of External Pins During Idle and Power Down Mode Program Memory ALE PSEN PORTO PORT1 PORT2 PORT3 Idle Internal 1 Data Data Data Data Idle External 1 1 1 Float Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data 3-75 Program Memory Lock Bits The AT89C52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table. When lock bit I is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly. Lock Bit Protection Modes Program Lock Bits LB1 LB2 LB3 1 U U U No program lock features. 2 p U U MOVC instructions executed from external.Jllilgram memory are disabled from fetching code bytes from intemal memory, EA is sampled and latched on reset, and further programming of the Flash memory is disabled. 3 p p P U Same as mode 2, but verify is also disabled. P P Same as mode 3, but extemal execution is also disabled. 4 Protection Type Programming the Flash The AT89C52 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents =FFH) and ready to be programmed. The programming interface accepts either a high-voltage (l2-volt) or a low-voltage (Vee) program enable signal. The low voltage programming mode provides a convenient way to program the AT89C52 inside the user's system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The AT89C52 is shipped with either the high-voltage or lowvoltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table. Top-Side Mark Signature Vpp=12V AT89C52 xxxx yyww (030H)=1EH (031H)=52H (032H)=FFH Vpp=5V AT89C52 xxxx-5 yyww (030H)=1EH (031H}=52H (032H)=05H The AT89C52 code memory array is programmed byte-by-byte in either programming mode. To program any non-blank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89C52, the address, data and control signals should be set up according to the Flash programming mode table and Figures 9 and 10. To program the AT89C52, take the following steps. 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 3-76 AT89C52 4. Raise EANpp to 12 V for the high-voltage programming mode. 5. Pulse ALEJPROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C52 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read ofthe last byte written will result in the complement of the written data on PO.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDYIBSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB 1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALEJPROG low for 10 ms. The code array is written with allIs. The chip erase operation must be executed before the code memory can be reprogrammed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, (continued) AT89C52 Programming the Flash (Continued) Programming Interface Every code byte in the Flash array can be written, and the entire array can be erased, by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion. 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. = = (030H) lEH indicates manufactured by Atmel (03lH) 52H indicates 89C52 (032H) = FFH indicates 12 V programming (032H) = 05H indicates 5 V programming All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. Flash Programming Modes ALE! EAl RST PSEN PROG Vpp P2.6 P2.7 P3.6 P3.7 Write Code Data H L \..f H/12V(1) L H H H Read Code Data H L H H L L H H Bit -1 H L \..f HI12V H H H H Bit - 2 H L \..f H/12V H H L L Bit - 3 H L \..f HI12V H L H L Chip Erase H L \..f H/12V H L L L Read Signature Byte H L H H L L L L Mode Write Lock Notes: (2) I. The signature byte at location 032H designates whether Vpp = 12 V or Vpp = 5 V should be used to enable programming. 2. Chip Erase requires a 10 ms PROG pulse. 3-n • Figure 10. Verifying the Flash Memory Figure 9. Programming the Flash Memory +5V +5V AT89C52 AT89C52 Vee P1 P2.0- P2.4 PGM DATA PO P2.7 ALE P3.6 PO ALE P3.6 V'H P3.7 XTAL2 EA XTAL1 RST GND P2.0 - P2.4 P2.7 SEE FLASH PROGRAMMING MODES TABLE PROG P3.7 '---"'----cf-l Vee P2.6 P2.6 SEE FLASH PROGRAMMING MODES TABLE P1 XTAL2 V,t/Vpp '---"'---l--l XTAL1 GND PSEN EA RST PSEN =: =: Flash Programming and Verification Characteristics TA =21°C to 27°C, Vcc =5.0 ± 10% Symbol Vpp(1) Parameter Min Max Programming Enable Voltage 11.5 12.5 V Ipp(1) Programming Enable Current 1.0 mA 24 MHz 1/tCLCL Oscillator Frequency tAVGL Address Setup to PROG Low 48tCLCL 4 tGHAX Address Hold After PROG 48tCLcL tDVGL Data Setup to PROG Low 48tCLCL tGHDX Data Hold After PROG 48tCLCL tEHSH P2.7 (ENABLE) High to Vpp 48tCLCL tSHGL tGHSL(1) Vpp Setup to PROG Low 10 Vpp Hold After PROG 10 tGLGH PROGWidth 1 tAVOV Address to Data Valid tELOV ENABLE Low to Data Valid tEHOV Data Float After ENABLE tGHBL PROG High to BUSY Low 1.0 twc Byte Write Cycle Time 2.0 Note: 3-78 I. Only used in 12-volt programming mode. AT89C52 Units ~s ~s 110 ~s 48tCLCL 48tCLcL 0 48tCLCL Ils ms _--1111!111---------- AT89C52 Flash Programming and Verification Waveforms - High Voltage MOde PROGRAMMING ADDRESS P1.0 - P1.7 P2.0 - P2.4 VERIFICATION ADDRESS IAVQV PORTO DATA OUT IGHAX ALE/PROG IGHSL EAlVpp LOGIC 1 _______ 1Q9lG.O --------- --------- ------------ • IEHQZ IELQV ~ (ENABLE) IGHBL P3L (RDY/BSY) READY Flash Programming and Verification Waveforms - Low Voltage Mode P1.0 - P1.7 P2.0 - P2.4 VERIFICATION ADDRESS PROGRAMMING ADDRESS PORTO DATA OUT ALEIPROG EAlV pp P2.7 (ENABLE) P3.4 (RDY/BSY) _______ LOGIC 1 1Q~!G.Q __________________ _ IEHQZ IELQV READY 3-79 Absolute M~ximum ~atings* Operating Temperature ......... ;......... -55°C to +125°C Storage Temperature ...................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ................... -1.0 V to +7.0 V 'NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage ............................ 6.6 V DC Output Current.. ..................................... 15.0 mA D.C. Characteristics The values shown in this table are valid for TA = -40°C to 85°C and Vee = 5.0 V ± 20%, unless otherwise noted. Symbol Parameter Condition Min Max Vil Input Low Voltage (Except EA) -0.5 0.2 Vee-0.1 Units V Vill Input Low Voltage (EA) -0.5 0.2 Vee-0.3 V 0.2Vee+0.9 Vee+0.5 V 0.7 Vee Vee+0.5 V VIH Input High Voltage (Except XTAL 1, RST) VIHl Input High Voltage (XTAL1, RSn VOL Output Low Voltage(1) (Ports 1,2,3) IOl= 1.6 mA 0.45 V VOll Output Low Voltage(l) (Port 0, ALE, PSEN) IOl=3.2 mA 0.45 V VOH Output High Volta9!l(Ports 1,2,3, ALE, PSEN) IOH = -60 JJA, Vee = 5 V ± 10% 2.4 V IOH = -2511A 0.75 Vee V JJA 0.9 Vee V 2.4 V IOH = -10 Output High Voltage (Port 0 in External Bus Mode) VOHl IOH = -800 1iA, Vee = 5 V ± 10% IOH = -300 I1A 0.75 Vee V IOH = -80 I1A 0.9 Vee V III Logical 0 Input Current (Ports 1,2,3) VIN = 0.45 V -50 JJA ITl Logical 1 to 0 Transition Current (Ports 1,2,3) VIN=2V -650 JJA III Input Leakage Current (PortO, EA) 0.45 < VIN < Vee ±10 I1A RRST Reset Pulldown Resistor 300 KO CIO Pin Capacitance Power Supply Current Icc Power Down Mode(2) Notes: 3·S0 50 Test Freq. = 1 MHz, T A = 25°C 10 pF Active Mode, 12 MHz 25 mA Idle Mode, 12 MHz 6.5 mA Vee=6 V 100 Vee=3 V 40 JJA JJA 1. Under steady state (non-transieni) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 rnA Maximum IOL per g-bit port: Port 0:26 rnA Ports 1,2,3:15 rnA Maximum total IOL for all output pins:71 rnA AT89C52 If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum Vee for Power Down is 2 V. AT89C52 A.C. Characteristics Under operating conditions, load capacitance for Port 0, ALElPAOG, and PSEN other outputs =80 pF. =100 pF; load capacitance for all External Program and Data Memory Characteristics Symbol Parameter 12 MHz Oscillator Variable Oscillator Min Min 0 .Max Max 24 Units 1ltCLCL Oscillator Frequency tLHLL ALE Pulse Width 127 2tCLCL-40 tAVLL Address Valid to ALE Low 28 tCLCL-13 ns tLLAX Address Hold After ALE Low 48 tCLCL-20 ns tLLlV ALE Low to Valid Instruction In tLLPL ALE Low to PSEN Low 43 tPLPH PSEN Pulse Width 205 tPLIV PSEN Low to Valid Instruction In tPXIX Input Instruction Hold After PSEN tPXIZ Input Instruction Float After PSEN tPXAV PSEN to Address Valid tAVIV Address to Valid Instruction In 312 5tCLCL-55 ns tPLAZ PSEN Low to Address Float 10 10 ns tRLRH AD Pulse Width 400 6tCLCL-100 tWLWH WA Pulse Width 400 6tCLCL-100 tRLDV AD Low to Valid Data In tRHDX Data Hold After AD 233 ns 4tCLCL-65 ns 3tCLCL-20 0 3tCLCL-45 75 tCLCL-10 0 ns ns tCLCL-8 252 ns ns 0 59 ns ns tCLCL-13 145 MHz ns ns 5tCLCL-90 ns ns 0 tRHDZ Data Float After AD 97 2tCLCL-28 ns tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns tAVDV Address to Valid Data In 585 9tCLCL-165 ns tLLWL ALE Low to AD or WA Low 200 3tCLCL+50 ns tAVWL Address to AD or WA Low 203 4tCLCL-75 ns tovwx Data Valid to WA Transition 23 tCLCL-20 ns tOVWH Data Valid to WA High 433 7tCLCL-120 ns twHOX Data Hold After WA 33 tCLCL-20 ns tRLAZ AD Low to Address Float twHLH AD or WA High to ALE High 300 3tCLCL-50 0 43 123 tCLCL-20 0 ns tCLCL+25 ns 3·81 External Program Memory Read Cycle ALE 1+---+foIf---+-----+I tLUV 1+-------+/ tpuv AO-A7 PORTO AS -A15 AS-A15 PORT 2 External Data Memory Read Cycle ALE tWHLH PORTO AO - A7 FROM RI OR DPl AO - A7 FROM PCl INSTR IN I+----~VWL----~ 1 + - - - - tAVDV - - - - - - + I PORT 2 3-82 P2.0 - P2.7 OR AS - A15 FROM DPH AS - A15 FROM PCH AT89C52 _ _ _ _ _ _ _..._ _ __ AT89C52 External Data Memory Cycle ALE tWHLH WR AD - A7 FROM RI OR DPl PORTO ~--- PORT 2 tAVWL DATA OUT AD - A7 FROM PCl • INSTR IN --~ P2.D - P2.7 OR A8 - A15 FROM DPH AS - A15 FROM PCH External Clock Drive Waveforms tCHCX tCHCL 0.45 V lcLCL External Clock Drive Symbol Parameter Min Max Units 1/tCLCL Oscillator Frequency 0 24 MHz tCLCL Clock Period 41.6 ns tCHCX High Time 15 ns tClCX Low Time 15 tClCH Rise Time 20 ns tCHCl Fall Time 20 ns ns AIIOEL 3-83 Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for Vcc = 5.0 V ± 20% and Load Capacitance = 80 pF. 12 MHzOsc Variable Oscillator Symbol Parameter Min Min txLXL Serial Port Clock Cycle Time 1.0 12tCLCL toVXH Output Data Setup to Clock Rising Edge 700 1OtCLCL-133 Ils ns tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-33 ns tXHDX Input Data Hold After Clock Rising Edge 0 0 tXHDV Clock Rising Edge to Input Data Valid Max Max Units ns 700 1OtCLCL-133 ns Shift Register Mode Timing Waveforms INSTRUCTION ALE o 2 4 3 5 7 6 8 CLOCK ., ,WRITE TO SBUIf OUTPUT DATA , CLEAR RI , .. INPUT DATA AC Testing Input/Output Waveforms (1) Float Waveforms (1) V OL·O.1 V Timing Reference Points 0.45 V Note: 3·84 1. AC Inputs during testing are driven at Vee - 0.5 V for a logic I and 0.45 V for a logic O. Timing measurements are made at VIH min. for a logic I and VIL max. for a logic O. AT89C52 Note: 1. For timing purposes, a port pin is no longer floating when, 1000mV change from load voltage occurs. A port pin begins to float when a 100-mV change from the loaded VoW\' oLievel occurs. _ _ _ _ _ _ _ _ _ _ _ _ _ _ AT89C52 Ordering Information Speed Power (MHz) Supply 12 5V±20% 5 V± 10% 16 5V±20% Ordering Code Package AT89C52-12AC AT89C52-12JC AT89C52-12PC AT89C52-120C 44A 44J 40P6 440 Commercial (O°C to 70°C) AT89C52-12AI AT89C52-12JI AT89C52-12PI AT89C52-1201 44A 44J 40P6 44Q Industrial (-40°C to 85°C) AT89C52-12AA AT89C52-12JA AT89C52-12PA AT89C52-120A 44A 44J 40P6 440 Automotive (-40°C to 125°C) AT89C52-120M AT89C52-12LM 4006 44L Military (-55°C to 125°C) AT89C52-120M/883 AT89C52-12LM/883 4006 44L Military/883C Class B, Fully Compliant (-55°C to 125°C) AT89C52-16AC AT89C52-16JC AT89C52-16PC AT89C52-160C 44A 44J 40P6 440 Commercial (O°C to 70°C) AT89C52-16AI AT89C52-16JI AT89C52-16PI AT89C52-1601 44A 44J 40P6 440 Industrial (-40°C to 85°C) 44A Automotive (-40°C to 125°C) AT89C52-16AA AT89C52-16JA AT89C52-1SPA AT89C52-1S0A 20 24 5V±20% 5V±20% 44J Operation Range 40PS 440 AT89C52-20AC AT89C52-20JC AT89C52-20PC AT89C52-200C 44A 44J 40PS 440 Commercial (O°C to 70°C) AT89C52-20AI AT89C52-20JI AT89C52-20PI AT89C52-2001 44A 44J 40P6 440 Industrial (-40°C to 85°C) AT89C52-24AC AT89C52-24JC AT89C52-24PC AT89C52-240C 44A 44J 44P6 440 Commercial (O°C to 70°C) AT89C52-24AI AT89C52-24JI AT89C52-24PI AT89C52-2401 44A 44J 44P6 440 Industrial (-40°C to 85°C) 3·85 Package Type 44A 4006 44J 44L 40P6 44Q 3-86 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 40 Lead, 0.600" Wide, Non-Windowed, Ceramic Duallnline Package (Cerdip) 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 40 Lead, 0.600" Wide, Plastic Dual In line Package (PDIP) 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP) AT89C52 AT89 LV52 Features • • • • • • • • • • • Compatible with MCS-51 ™Products a Kbytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 12 MHz Three-Level Program Memory Lock 256 x a-Bit Internal RAM 32 Programmable VO Lines Three 16-Bit Timer/Counters Eight Interrupt Sources Programmable Serial Channel Low Power Idle and Power Down Modes 2.7 V to 6 V Operating Range 8-Bit Microcontroller with 8 Kbytes Flash Description The AT89LV52 is a low-voltage, high-performance CMOS 8-bit microcomputer with 8 Kbytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel's high density nonvolatile memory technology and is compatible with the industry standard 80C5l and 80C52 instruction set and pinout. The on-chip Flash aUows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89LV52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89LV52 operates at 2.7 volts up to 6.0 volts. The AT89LV52 provides the foUowing standard features: 8 Kbytes of Flash, 256 bytes of RAM, 32 110 lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a (continued) PDIP/Cerdip Pin Configurations vee (T2) P1.0 (T2 EX) P1.1 P1.2 P1.3 PO.D (ADO) PO.l PO.2 PO.3 PO.4 PO.S P1.4 P1.5 P1.6 Pl.7 RST PO.6 (ADS) ~7 (AD7) (RXO) pa.a EA/VPP (rXD) P3.1 (INTO) P3.2 (i1ii'F1) pa.3 (Tl) pa.s AlEfPROG PSEN P2.7 (A1S) P2.S (A14) P2.S (A13) (WR) P3.S P2.4 (A12) (110) P3.7 P2.3 (All) (TO) P3,4 XTAL2 XTALl POFPITOFP ~ NN t.t. P1.5 P1.6 (RXD) (TXD) (INTO) (INT1) (TO) (T1) P1.7 AST P3.0 NC P3.1 P3.2 P3.3 P3.4 P3.5 o~ (AD') (AD2) (AD3) (AD4) (ADS) P2.2 (A1O) P2.1 (A9) GND ~ P2.D (AS) PLCC/LCC '''' :!." ~~ 30 PO.4 PO.S PO.6 PO.7 2. EAIVPP 33 32 31 2. 27 26 25 2. 23 (AD4) (ADS) (AD6) (AD7) Ne AlE/PROG PSEN P2.7 (A1S) P2.6 (A14) P2.5 (A13) P1.5 PDA (AD4) P1.6 P1.7 RST (RXO) P3.0 PO.6 (AD6) PO.7 (AD7) EAIVPP PO.S (ADS) 11 Ne Ne (TXD) P3.1 (fNTI.i) P3.2 (tNT1) P3.3 (TO) P3.4 30 (T1) P3.S 1[a192021222324252627ia9 ALE/PROG PSEN P2.7 (A1S) P2.6 (A14) P2.5 (A13) 03758 3-87 • Block Diagram PD.D - PO.7 P2.D· P2.7 .. --------------------------------Vee .. GND • -- --- - - --- ---.: P PSEN EA I Vpp T~~G CONTROL INSTRUCTION REGISTER ~--L--r--''----_+--~-...._---'--~ RST P1.D - P1.7 3-88 ·· ·· ·· ··· ·· · · INTERRUPT, SERIAL PORT, AND TIMER BLOCKS ALE/PROG -- --- - - --- -- ------ .. AT89 LV52 P3.D· P3.7 AT89 LV52 Description (Continued) full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89LV52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset. Pin Description Vee Supply voltage. GND Ground. PortO Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When Is are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, PO has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull ups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When Is are written to Port 1 pins, they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IlL) because of the internal pullups. In addition, P1.0 and Pl.l can be configured to be the timer/counter 2 external count input (P1.01T2) and the timer/counter 2 trigger input (Pl.l1T2EX), respectively, as shown in the following table. Port Pin P1.0 P1.1 memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TIL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IlL) because of the pullups. Port 3 also serves the functions of various special features of the AT89LV51, as shown in the following table. Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Functions RXD (serial input port) TXD (serial output port) INTO (external interrupt 0) INT1 (external interrupt 1) TO (timer 0 external input) T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) Port 3 also receives some control signals for Flash programming and programming verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. Alternate Functions ALEIPROG Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. T2 (external count input to Timer/Counter 2), clock-out T2EX (Timer/Counter 2 capture/reload triQQer and direction control) In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. Port 1 also receives the low-order address bytes during Flash programming and program verification. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When Is are written to Port 2 pins, they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVe instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcrontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT89LV52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. (continued) 3-89 • Pin Description (Continued) Special Function Registers EANpp A map of the on-chip memory area called tbe Special Function Register (SFR) space is shown in Table 1. External Access Enable. EA must be strapped to GND in order to enable tbe device to fetch code from external program memory location~ starting at OOOOH up to FFFFH. Note, however, tbat if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to Vee for internal program executions. This pin also receives tbe 12-volt programming enable voltage (Vpp) during Flash programming when 12-volt programming is selected. XTALI Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Note tbat not all of tbe addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to tbese addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write Is to tbese unlisted locations, since they may be used in future products to invoke new features. In tbat case, the reset or inactive values of the new bits will always be O. Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and TIMOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) are tbe CapturelReload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. (continued) Output from tbe inverting oscillator amplifier. Table 1• A T89LV52 SFR M apan dReset Val ues OF8H OFOH OFFH B 00000000 OF7H OE8H OEOH OEFH ACC 00000000 OE7H ODFH OD8H ODOH PSW 00000000 OC8H T2CON 00000000 OD7H T2MOD XXXXXXOO RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 OCFH OC7H OCOH OB8H IP XXOOOOOO OBFH OBOH P3 11111111 OB7H OA8H IE OXOOOOOO OAFH OAOH P2 11111111 OA7H 98H SCON 00000000 90H P1 11111111 88H TCON 00000000 TMOD 00000000 TLO 00000000 TL1 00000000 80H PO 11111111 SP 00000111 DPL 00000000 DPH 00000000 3-90 SBUF XXXXXXXX 9FH 97H AT89LV52 THO 00000000 TH1 00000000 8FH PCON OXXXOOOO 87H AT89 LV52 Table 2. T2CON-Timer/Counter 2 Control Register Reset Value T2CON Address = OC8H =0000 OOOOB Bit Addressable Bit Symbol Function TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK 1 or TCLK 1. EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1. When Timer 2 interrupt is enabled, EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN 1). = = = = = RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK 0 causes Timer 1 overflow to be used for the receive clock. TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 0 causes Timer 2 to ignore events at T2EX. = = = =1 starts the timer. =0 for timer function. CIT2 = 1 for external event TR2 Start/Stop control for Timer 2. TR2 CIT2 Timer or counter select for Timer 2. CIT2 counter (falling edge triggered). CPIRL2 Capture/Reload select. CP/RL2 1 causes captures to occur on negative transitions at T2EX if EXEN2 1. CP/RL2 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 1. When either RCLK or TCLK 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. = = = = = Special Function Registers (Continued) Interrupt Registers The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. Data Memory The A T89LV52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH. the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location OAOH (which is P2). MOV OAOH, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where RO contains OAOH, accesses the data byte at address OAOH, rather than P2 (whose address is OAOH). MOV @RO,#data Note that s~ck operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available stack space. as 3-91 II AlmEL Timer 0 and 1 Capture Mode Timer 0 and Timer 1 in the AT89LV52 operate the same way as Timer 0 and Timer 1 in the AT89LV51. In the capture mode, two options are selected by bit EXEN2 in TICON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an· interrupt. If EXEN2 = I, Timer 2 performs the same operation, but a I-to-O transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at TIEX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure I. Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter: The type of operation is selected by bit CIT2 in the SFR TICON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1112 of the oscillator frequency. In the Counter function, the register is incremented in response to a I-to-O transition at its corresponding external input pin, TI. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3PI ofthe cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a I-to-O transition, the maximum count rate is 1124 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. Table 3. Timer 2 Operating Modes RCLK+TCLK CPIRL2 TR2 MODE 0 16-Bit Auto-Reload 0 I 0 I 1 16-Bit Capture 1 X 1 Baud Rate Generator X X 0 (Oft) Figure 1. Timer 2 in Capture Mode Ol-------'! CfT2 =1 T2PIN T2EX PIN 3-92 AT89 LV52 AutO-Reload (Up or Down Counter) Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR TIMOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the TIEX pin. Figure 2 shows Timer 2 automatically counting up when DCEN = O. In this mode, two options are selected by bit EXEN2 in TICON. If EXEN2 =0, Timer 2 counts up to OFFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to. be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in RCAP2H and RCAP2L are preset by software. If EXEN2 = I, a 16-bit reload can be triggered either by an overflow or by a I-to-O transition at external input TIEX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt ifenabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2I;lX makes Timer 2 count up. The timer will overflow at OFFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. (continued) AT89LV52 Auto-Reload (Up or Down Counter) (Continued) A logic 0 at T2EX makes Timer 2 count down. The timer underflows when 1H2 and 1L2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the 1F2 bit and causes OFFFFH to be reloaded into tbe timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. Figure 2. Timer 2 Auto Reload Mode (DCEN =0) OVERFLOW TR2 Df----------.J1 CfT2 = 1 TIMER 2 INTERRUPT T2PIN T2EX PIN Table 4. T2MOD-Timer 2 Mode Control Register T2MOD Address =OC9H Reset Value =XXXX XXOOB Not Bit Addressable Bit I~ Svmbol I~ I~ I~ I~ I~ Function - Not implemented, reserved for future use. T20E Timer 2 Output Enable bit. DCEN When set, this bit allows Timer 2 to be configured as an up/down counter. AIIDEL 3-93 • Figure 3. Timer 2 Auto Reload Mode (DCEN = 1) (DOWN COUNTING RELOAD VALUE) 0----1cm TOGGLE = 1 T2 PIN (UP COUNTING RELOAD VALUE) COUNT DIRECTION 1=UP Q=DOWN T2EX PIN Figure 4. Timer 2 in Baud Rate Generator Mode TIMER 1 OVERFLOW "1" NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 ···············SMOD1 crr2=O Ol------'jCm = 1 T2PIN TRANSITION DETECTOR T2EX PIN 0--1 ~ .: . I· .~I I~ ~., . CoNTROL EXEN2 3-94 AT89LV52 EXF2 TIMER2 I~"INTERRUPT AT89LV52 Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in TICON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 4. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes I and 3 are determined by Timer 2' s overflow rate according to the following equation. Rate M o d es I an d 3 Bau d R ates= Timer2 Overflow 16 The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CPIT2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1112 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 112 the oscillator frequency). The baud rate formula is given below. Modesl and 3 Baud Rate Oscillator Frequency 32 x [65536 - (RCAP2H, RCAP2L)] where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK = I in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a l-to-O transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = I) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Figure 5. Timer 2 in Clock-Out Mode P1.0 (T2) T20E (T2MOD.1) ---------, TRANSITION "--- DETECTOR TIMER 2 INTERRUPT EXEN2 AlmEl 3-95 II AIIOEL Programmable Clock Out Table 5. Interrupt Enable (IE) Register A 50% duty cycle clock can be programmed to come out on Pl.O, as shown in Figure 5. This pin, besides being a regular 1/0 pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 3 MHz at a 12 MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit CIT2 (TICON.I) must be cleared and bit T20E (TIMOD.l) must be set. Bit TR2 (T2CON.2) starts and stops the timer .. (LSB) (MSB) Enable Bit Symbol Position EA IE.7 The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation. Cl k 0 tF oc - u requency =4 =1 enables the interrupt. Enable Bit = 0 disables the interrupt. Oscillator Frequency x. [65536 _ (RCAP2H, RCAP2L)] Function Disables all interrupts. If EA =0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or . clearing its enable bit. - IE.6 Reserved. In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. ETI IE.S Timer 2 interrupt enable bit. ES IE.4 Serial Port interrupt enable bit. ETl IE.3 Timer 1 interrupt enable bit. EXI IE.2 External interrupt 1 enable bit. ETO IE.! Timer 0 interrupt enable bit. UART EXO IE.O External interrupt 0 enable bit. The UART in the AT89LV52 operates the same way as the UART in the AT89LV51. User software should never write 1s to unimplemented bits, because they may be used in future ATa9 products. Interrupts The AT89LV52 has a total of six interrupt vectors: two external interrupts (INTO and INTI ), three timer interrupts (Timers 0, I, and 2), and the serial port interrupt. These interrupts are all shown in Figure 6. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89LV51, bit position IE.5 is also unimplemented. User software should not write I s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TFO and TFI, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows. INTO ~o----------------------------~ INT1 TF1 ----------------------------~ ~ ----------~r=:>~-----------. E~~ ----------~r=:>~-----------.. Figure 6. Interrupt Sources 3-96 AT89LV52 AT89 LV52 Figure 7. Oscillator Connections Oscillator Characteristics XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTALl is driven, as shown in Figure 8. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-bytwo flip-flop, but minimum and maximum voltage high and low time specifications must be observed. C2 I XTAL2 I D XTAL1 GND Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during·this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory. • Notes: C I, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators Figure 8. External Clock Drive Configuration XTAL2 NC Power Down Mode In the power down mode, the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before Vee is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. EXTERNAL OSCILLATOR - - - - - I SIGNAL XTAL1 GND Status of External Pins During Idle and Power Down Mode Program Memory ALE PSEN PORTO PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data 3·97 Program Memory Lock Bits The AT89LV52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table. When lock bit I is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly. Lock Bit Protection Modes Program Lock Bits LB1 LB2 LB3 U U U 1 Protection Type No program lock features. Move instructions executed from external.Qf9gram memory are disabled from p U U fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash memory is disabled. 3 p P U Same as mode 2, but verify is also disabled. 4 p P P Same as mode 3, but external execution is also disabled. 2 Programming the Flash The AT89LV52 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents FFH) and ready to be programmed. The programming interface accepts either a high-voltage (l2-volt) or a low-voltage (Vee) program enable signal. The low voltage programming mode provides a convenient way to program the AT89LV52 inside the user's system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. = The AT89LV52 is shipped with either the high-voltage or lowvoltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table. Top-Side Mark Signature Vpp=12V AT89LV52 xxxx yyww Vpp=5 V AT89LV52 xxxx-5 yyww (030H)=1EH (030H)=1EH (031H)=62H (032H)=FFH (031H)=62H (032H)=05H The AT89LV52 code memory array is programmed byte-bybyte in either programming mode. To program any non-blank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89LV52, the address, data and control signals should be set up according to the Flash programming mode table and Figures 9 and 10. To program the AT89LV52, take the following steps. 1. Input the desired memory location on the address Jines. 2. Input the appropriate data byte on the data Jines. 3·98 AT89 LV52 3. Activate the correct combination of control signals. 4. Raise EANpp to 12 V for the high-voltage programming mode. 5. Pulse ALEIPROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps I through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89LV52 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on PO.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. ReadylBusy: The progress of byte programming can also be monitored by the RDYIBSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LBI and LB2 have not been programmed, the programmed code data can be read back via the address and data Jines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALEIPROG low for 10 ms. The code array is written with allIs. The chip erase operation must be executed before the code memory can be reprogrammed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, (continued) AT89LV52 Programming the Flash (Continued) Programming Interface 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. Every code byte in the Flash array can be written, and the entire array can be erased, by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion. (030H) (031H) (032H) (032H) = lEH indicates manufactured by Atmel =52H indicates 89LV52 =FFH indicates 12 V programming = OSH indicates 5 V programming All major programming vendors offer worldwide support for the Atrnel microcontroller series. Please contact your local programming vendor for the appropriate software revision. Flash Programming Modes Mode RST PSEN Write Code Data H L Read Code Data H L Bit-1 H L Bit- 2 H L Bit - 3 H L Chip Erase H L Read Signature Byte H L Write Lock Notes: I. The signature byte at location 032H designates whether Vpp = 12 V or Vpp = 5 V should be used to enable ALE! EAI PROG Vpp P2.6 P2.7 P3.6 P3.7 H/12V(1) L H H H H H L L H H ~ H/12V H H H H H/12V H H L L H/12V H L H L H/12V H L L L H L L L L ~ (2) ~ ~ ~ H 2. Chip Erase requires a 10 ms PROG pUlse. programming. 3-99 • Figure 9. Programming the Flash Memory Figure 10. Verifying the Flash Memory +5V +5V AT89LV52 AT89LV52 Pl vee P2.0 - P2.4 P1 PGM DATA PO P2.0 - P2,4 PO P2.6 P2.6 SEE FLASH PROGRAMMING MODES TABLE vCC P2.? ALE P2.? SEE FLASH PROGRAMMING MODES TABLE PROG P3.6 ALE P3.6 V,H P3.? P3.? XTAL2 EA XTAL 1 RST V,.!Vpp XTAL2 V'H XTAL1 EA 4-12 MHz D GND PSEN - GND V,H RST PSEN - - Flash Programming and Verification Characteristics TA = 21°C to 27°C, VCC = 5.0 ± 10% Symbol Vpp(l) Parameter Min Max Programming Enable Voltage 11.5 12.5 V Ipp(1) Programming Enable Current 25 ItA 12 MHz 1/tCLCL Oscillator Frequency tAVGL Address Setup to PROG Low 48tCLCL tGHAX Address Hold After PROG 48tCLCL tDVGL Data Setup to PROG Low 48tCLCL tGHDX Data Hold After PROG 48tCLCL tEHSH P2.7 (ENABLE) High to Vpp 48tCLCL tSHGL tGHSL(1) Vpp Setup to PROG Low 10 Vpp Hold After PROG 10 tGLGH PROG Width 1 tAVQV Address to Data Valid tELQV ENABLE Low to Data Valid tEHQV Data Float After ENABLE tGHBL PROG High to BUSY Low 1.0 ~s twc Byte Write Cycle Time 2.0 ms Note: 3-100 I. Only used in 12-volt programming mode. AT89LV52 4 Units ~s ~s 110 ~s 48tCLCL 48tCLCL 0 48tCLCL AT89 LV52 Flash Programming and Verification Waveforms - High Voltage Mode PROGRAMMING ADDRESS P1.0 - P1.7 P2.0 - P2.4 VERIFICATION tAVOV PORTO DATA OUT tAVGL tGHAX ALEIPROG tSHGL tGHSL LOGIC 1 EA/Vpp _______ 19g1Q.O - - - - - - - - - --------- ------------ • tEHOZ tELOV P2.7 (ENABLE) tGHBL P3.4 (RDY/BSY) READY Flash Programming and Verification Waveforms - Low Voltage Mode P1.0 - P1.7 P2.0 - P2.4 PROGRAMMING ADDRESS VERIFICATION ADDRESS PORTO DATA OUT ALEIPROG EA/Vpp LLLLLLLLLLLL4_____________ _ LOGIC 1 _______ ~9~1Q.Q __________________ _ ~ (ENABLE) P3L (RDY/BSY) AIIDEL 3-101 Absolute Maximum Ratings· "NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature ................... -55°C to +125°C Storage Temperature ...................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ................... -1.0 V to +7.0 V Maximum Operating Voltage ............................ 6.6 V DC Output Current ....................................... 15.0 rnA D.C. Characteristics The values shown in this table are valid for TA = -40°C to 85°C and Vee = 5.0 V ± 20%, unless otherwise noted. Symbol Parameter Condition Min Max VIL Input Low Voltage (Except EA) -0.5 0.2 Vee-0.1 V VIL1 Input Low Voltage (EA) -0.5 0.2Vee-0.3 V VIH Input High Voltage (Except XTAL1, RST) 0.2 Vee+0.9 Vee+0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7 Vee Vee+0.5 V VOL Output Low Voltage(1) (Ports 1,2,3) IOL= 1.6mA 0.45 V VOLl Output Low Voltage(1) (Port 0, ALE, PSEN) IOL=3.2 rnA 0.45 V VOH Output High Volta~ (Ports 1,2,3, ALE, PSEN) Output High Voltage (Port 0 in External Bus Mode) VOH1 IOH = -60 ~A, Vee = 5 V± 10% Units 2.4 V IOH = -25 ~A 0.75 Vee V IOH = -10 ~A 0.9 Vee V 2.4 V IOH = -800 ~A, Vee = 5 V ± 10% IOH = -300 ~A IOH=-80~ 0.75 Vee V 0.9 Vee V ilL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45 V -50 ~ ITL Logical 1 to 0 Transition Current (Ports 1,2,3) VIN= 2V -650 ~ ILl Input Leakage Current (PortO, EA) 0.45 < VIN < Vee ±10 ~A 300 Kn RRST Reset Pulldown Resistor CIO Pin Capacitance Power Supply Current Icc Power Down Mode(2) Notes: 3-102 50 Test Freq. = 1 MHz, TA = 25°C 10 pF Active Mode, 12 MHz 25 rnA Idle Mode, 12 MHz 6.5 rnA Vee=6V 100 ~ Vee=3V 40 ~ I. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: \0 rnA Maximum IOL per 8-bit port: Port 0:26 rnA Ports 1,2, 3:15 rnA Maximum total IOL for all output pins:71 rnA AT89 LV52 IfIOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum Vee for Power Down is 2 V. AT89 LV52 A.C. Characteristics Under operating conditions, load capacitance for Port 0, ALEIPROG, and PSEN = 100 pF; load capacitance for all other outputs =80 pF. External Program and Data Memory Characteristics 12 MHz Oscillator Variable Oscillator Min Min Max Units 0 12 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tLHLL ALE Pulse Width 127 2tCLCL-40 ns tAVLL Address Valid to ALE Low 28 tCLCL-25 ns tLLAX Address Hold After ALE Low 48 tCLCL-25 tLUv ALE Low to Valid Instruction In tLLPL ALE Low to PSEN Low 43 tCLCL-25 tPLPH PSEN Pulse Width 205 3tCLCL-45 tPLIV PSEN Low to Valid Instruction In tPXIX Input Instruction Hold After PSEN tPXIZ Input Instruction Float After PSEN tPXAV PSEN to Address Valid tAVIV Address to Valid Instruction In Max 233 145 0 ns 4tCLCL-65 ns ns 3tCLCL-60 59 tCLCL-25 ns ns tCLCL-8 312 ns ns 0 75 ns 5tCLCL-80 ns 10 ns tPLAZ PSEN Low to Address Float tRLRH RD Pulse Width 400 6tCLCL-100 twLWH WR Pulse Width 400 6tCLCL-100 tRLDV RD Low to Valid Data In tRHDX Data Hold After RD tRHDZ Data Float After RD 97 2tCLCL-28 ns tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns tAVDV Address to Valid Data In 585 9tCLCL-165 ns tLLWL ALE Low to RD or WR Low 200 3tCLCL+50 ns tAvwL Address to RD or WR Low 203 4tCLCL-75 ns tovwx Data Valid to WR Transition 23 tCLCL-30 ns tOVWH Data Valid to WR High 433 7tCLCL-120 ns tWHOX Data Hold After WR 33 tCLCL-25 ns tRLAZ RD Low to Address Float tWHLH RD or WR High to ALE High 10 252 0 ns 5tCLCL-90 300 3tCLCL-50 123 tCLCL-25 ns ns 0 0 43 ns 0 ns tCLCL+25 ns 3-103 • AlmEL External Program Memory Read Cycle ALE 14--~r--+--~ tLLlV r----t----~~,~----~t~v tP\..AZ .AO - A7 PORTO 14---- AO-A7 t AVIV --~ AS - A15 PORT 2 AS-A15 External Data Memory Read Cycle ALE INSTR IN PORTO 1+---- PORT 2 3-104 tAVDV -----~ P2.0 - P2.7 OR AS - A15 FROM DPH AS -A15 FROM PCH AT89LV52 _ _ _ _ _ _ _ _ _ _ __ AT89LV52 External Data Memory Cycle ALE tWHLH AO - A7 FROM PCL PORTO • INSTR IN 1 4 - - - - tAVWL - - - . I PORT 2 AS - A15 FROM PCH P2.0 - P2.7 OR AS - A15 FROM DPH External Clock Drive Waveforms tCHCX tcHCL 0.45 V tcLCL External Clock Drive Symbol Parameter Min Max Units 1/tClCl Oscillator Frequency 0 12 MHz tClCl Clock Period 83.3 ns tCHCX High Time 20 ns tClCX Low Time 20 tClCH Rise Time 20 ns tCHCl Fall Time 20 ns ns 3-105 AIIOEL Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for Vcc =5.0 V ± 20% and Load Capacitance =80 pF. Variable Oscillator 12 MHzOsc Parameter Symbol Max Min Min Max Units tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL tOVXH Output Data Setup to Clock Rising Edge 700 1OtCLCL-133 ns tXHOX Output Data Hold After Clock Rising Edge 50 2tCLCL-33 ns tXHDX Input Data Hold After Clock Rising Edge 0 tXHDV Clock Rising Edge to Input Data Valid ILs 0 ns 700 1OtCLCL -133 ns Shift Register Mode Timing Waveforms INSTRUCTION ALE o 2 4 3 5 6 7 8 CLOCK ,WRITE TO SBUFf ... OUTPUT DATA , CLEARRI , t SETRlt INPUT DATA AC Testing Input/Output Waveforms (I) Float Waveforms (I) V OL .().1 V VLOAO-tO.1 V VLOAO ----< Timing Reference Points 0.45 V Note: 3-106 I. AC Inputs during testing are driven at Vee - 0.5 V for a logic I and 0.45 V for a logic O. Timing measurements are made at VIH min. for a logic I and VIL max. for a logic O. AT89 LV52 Note: 1. For timing purposes, a port pin is no longer floating when a 100-mV change from load voltage occurs. A port pin begins to float when a lOO-mV change from the loaded VOw'VOL level occurs. _ _ _ _ _ _ _ _ _ _ _ _ _ _ AT89LV52 AT89 LV52 ICC (rnA) TYPICAL ICC (ACTIVE) at 2SoC 24~----~--~----~----~----~--__. VCC=6.0V 20+-----r---~----_+----~----1__=~ 16+-____~--~----_+~~~----~--~ 12+-----~~~----_+--~~~--1_--~ II 8+-----~~~----_+----~----1_--~ O+-----T---~----_+----_r----~--~ 4 o 8 12 16 20 24 F (MHz) AT89 LV52 TYPICAL ICC (IDLE) at 2SoC ICC (rnA) 4.8 VCC=6.0V 4.0 3.2 2.4 1.6 0.8 0.0 0 4 8 12 16 20 24. F (MHz) 3·107 Almll AT89 LV52 TYPICAL ICC vs. VOLTAGE - POWER DOWN (85°C) 20.-------------~--------------~------------~ I 15+-------------r_----------_1-----=~~--~ C C10+-------------r-----~~--~------------~ 11 A 5+------=~~--r_----------_1------------~ O+---------------+---------------~------------~ 3.0V 4.0V 5.0V 6.0V Vee VOLTAGE Ordering Information Speed Power (MHz) Supply 12 2.7Vt06V Ordering Code Package AT89LV52-12AC AT89LV52-12JC AT89LV52-12PC AT89LV52-120C 44A 44J 40P6 440 Package Type 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 4006 40 Lead, 0.600" Wide, Non-Windowed, Ceramic Duallnline Package (Cerdip) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PtCC) 44L 44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44Q 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP) 3-108 AT89 LV52 Operation Range Commercial (O°C to 70°C) AT89S8252 Features • • • • • • • • • • • • • • • Compatible with MCS-51 ™ Products 8 Kbytes of In-System Reprogrammable Downloadable Flash Memory SPI Serial Interface for Program Downloading Endurance: 1,000 WritelErase Cycles 2 Kbytes EEPROM Endurance: 100,000 WritelErase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-Level Program Memory Lock 256 x 8-Bit Internal RAM 32 Programmable I/O Lines Three 16-Bit Timer/Counters Nine Interrupt Sources Programmable UART Serial Channel SPI Serial Interface Low Power Idle and Power Down Modes Interrupt Recovery From Power Down Programmable Watchdog Timer Dual Data Pointer 8-Bit Microcontroller with 8 Kbytes Downloadable Flash • Advance Information Description The AT89S8252 is a low-power, high-performance CMOS 8-bit microcomputer with 8 Kbytes of Downloadable Flash programmable and erasable read only memory and 2 Kbytes of EEPROM. The device is manufactured using Atmel's high density nonvolatile memory technology and is compatible with the industry standard 8OC51 instruction set and pinout. The on-chip Downloadable Flash allows the program memory to be reprogrammed in-system through an SP! serial interface or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Downloadable Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89S8252 provides the following standard features: 8 Kbytes of Downloadable Flash, 2 Kbytes extended endurance EEPROM, 256 bytes of RAM, 32 YO lines, programmable watchdog timer, two Data Pointers, three 16-bit timer/counters, a seven-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8252 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The Downloadable Flash can be changed a single byte at a time and is accessible through the SP! serial interface. Holding RESET active forces the SPI bus into a slave input mode and allows the program memory to be Written-from or Read-to unless Lock Bit 3 has been activated. 0401 A 3-109 Pin Configurations PDIP/Cerdip PLCC/LCC )( (T2) P1.0 (T2 EX) P1.1 P1.2 P1.3 ('88) P1.4 (MOSI) P1.6 (MISO) P1.8 ISCK) P1.7 RST (RXD) P3.0 (ADO) (ADt) (1.02) (ADS) PO.4 (1.04) PO.S (ADS) PO.8 (ADa) PO.7 CAD7) EA/VPP ITXD) P3.1 P3.2 P3.3 P3.4 P3,5 (WRT P3.6 (RD) P3.7 XTAl2 XTAL1 GND W NN VCC PO.O PO.1 PO.2 PO.3 !:.t. (MOSI) P1.5 (MISO) P1.8 ISCK) P1.7 RST ALE/PROG (INTO') (1NTf) (TO) In) -cc:..:...._ _--'- (RXO) P3.0 NC (TXD) P3.1 IINTOT P3.2 (IN""fff P3.3 (TO) P3.4 (T1) P3.5 PSEN P2.7 (A1S) P2.6 (A14) P2.S (AU) P2.4 (AU) P2.3 (Att) P2.2 (A1O) P2.1 IA9) P2.0 (AB) PQFPITQFP ~ NN t.t. ISCK) P1.7 RST (RXO) P3.0 NC (rXD) P3.1 I'SEN (IN""i'Of P3.2 3-110 ~~~~ PO.4 (AD4) PO.S (ADS) PO.8 (1.08) PO.7 (AD7) EA/VPP NC ALE/PROG (M081) P1.5 (MISO) P1.8 (INTi) P3.3 (TO) P3.4 (T1) P3.5 a.-C\lIO COOC 10 11 P2.7 (A16) P2.8 (1.14) P2.5 (AU) AT89S8252 PO.4 (1.D4) PO.5 (AD5) PO.S (ADS) PO.7 (AD7) EA/VPP NC AlEiP'ROG PSni P2.7 (A15) P2.S (A14) P2.5 (AU) AT89S8252 Block Diagram PO.O· PO.7 P2.0 • P2.7 Vee : ~, GND Ii -= I • INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSEN ALEJPROG EA I Vpp RST P3.0 • P3.7 P1.0 • P3.7 3-111 Ordering Information Speed Power (MHz) Supply 12 2.7V± 10% 24 5V±20% Ordering Code Package AT89S8252-12AC AT89S8252-12JC AT89S8252-12PC AT89S8252-12QC 44A 44J 40P6 44Q Commercial (O°C to 70°C) A T89S8252-12AI AT89S8252-12JI AT89S8252-12PI AT89S8252-12QI 44A 44J 40P6 44Q Industrial (-40°C to 85°C) AT89S8252-24AC AT89S8252-24JC AT89S8252-24PC AT89S8252-24QC 44A 44J 40P6 44Q Commercial (O°C to 70°C) AT89S8252-24AI AT89S8252-24JI AT89S8252-24P I AT89S8252-24QI 44A 44J 40P6 44Q Industrial (-40°C to 85°C) Package Type 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600" Wide, Plastic Duallnline Package (PDIP) 44Q 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP) 3-112 AT89S8252 Operation Range Microcontroller Product Information General Architecture Microcontroller Data Sheets Microcontroller Application Notes II "~~"tJ;:\£'fh"~:~~';q;z:;~:"::':it"f~~f;"'~~;:;,.9.V':.;":::C,:'''?':';:'''~;;'~~~,,,,,,"~{."':.J;bw,~"::i:'0i1'"~{:i""".'·>.t:..,":7-~:~'.~.;;:;"&:<,,:;~'''''"~~':"~~'';::"!, Programmer Support/Development Tools Microcontroller Cross-Reference Package Outlines Miscellaneous Information Contents Section 4 Microcontroller Application Notes Using a Personal Computer to Program the AT89C51/C521LV51/LV52/C1051/C2051 .. 4-3 AT89C51 In-Circuit Programming .................................................................................... 4-9 Controlling FPGA Configuration with a Flash-Based Microcontroller. .............................. 4-21 Programming Atmel's Family of Flash Memories ............................................................. 4-29 Analog-to-Digital Conversion Utilizing the AT89CX051 Microcontrollers ......................... 4-33 Interfacing AT24CXX Serial EEPROMS with AT89CX051 Microcontrollers .................... 4-39 Interfacing AT93CXX Serial EEPROMS with AT89CX051 Microcontrollers .................... 4-41 • AllDEl 4-1 4-2 Microcontroller Using a Personal Computer to Program the AT89C51 IC521LV51 ILV521C1 051/C2051 Introduction This application note describes a personal computer-based programmer for the AT89C511C521LV511LV52/C 10511C2051 Flash-based Microcontrollers. The programmer supports all flash memory microcontroller functions, including code read, code write, chip erase, signature read, and lock bit write. When used with the AT89C511C521 LV511LV52, code write, chip erase, and lock bit write may be performed at either five or twelve volts, as required by the device. Devices sporting a "-5" suffix are intended for operation at five volts, while devices lacking the suffix operate at the standard twelve volts. The programmer connects to an IBM PCcompatible host computer through one of the host's parallel ports. Required operating voltages are produced by an integral power supply and external, wall-mounted transfornler. Software Software for the programmer is available by downloading it from the Atrnel BBS at 408436-4309. The programmer is controlled by software running on the host. The AT89C511C52 and C 105 I1C2051 have dedicated control programs, which were written in Microsoft C. Programs dedicated to the AT89LV51ILV52 do not exist; these devices are supported by the programs for the AT89C511C52, respectively. In the text below, all references to the AT89C5I1C52 may be assumed to apply to the AT89LV511LV52 as well. All programmer control programs are invoked from the DOS command line by entering the program name followed by "LPTl" or "LPT2" to specify parallel port one or two, respectively. If the parallel port is not specified, the program will respond with an error message. The control programs are menu-driven, and provide the following functions: Chip Erase Clear code memory to all ones. The successful operation of this function is not automatically verified. 8-Bit Microcontroller with Flash Application Note Program from File Write the contents of the specified file into device memory. The user is prompted for the file name, which may require path and extension. The file is expected to contain binary data; hex files are not accepted. The first byte in the file is programmed into the first location in the device. Successive bytes are programmed into successive locations until the last location in the device has been programmed or until the data in the file has been exhausted. Programming occurs regardless of the existing contents of device memory; a blank check is not automatically performed. After programming, the contents of device memory are not automatically verified against the file data. Each programmed location in the device receives the maximum programming time specified in the data sheet. This is done because timing is enforced by software; the programming status information provided by DATA* polling and RDYIBSY* is not utilized. The control program provides no visual indication that programming is in progress. The main menu is redisplayed when programming is complete. • Verify against File Compare the contents of code memory against the contents of the specified file. The user is prompted for the file name, which may require path and extension. 0285D 4-3 The file is expected to contain binary data; hex files are not accepted. The first byte in the file is compared to the first location in the device. Successive bytes are compared to successive locations until the last location in the device has been compared or until the data in the file has been exhausted. Locations which fail to compare are displayed by address, with the expected and actual byte contents. If there are no compare failures, nothing is displayed. Save to File Copy the contents of device memory to the specified file. The user is prompted for the file name, which may require path and extension. The number of bytes in the resulting file is the same as the number of memory locations in the device. Blank Check Verify that the contents of device memory are all ones. Only pass or fail is reported; the addresses and contents of failing locations are not displayed. Read Signature Read and display the contents of the signature bytes. The number of signature bytes and their expected contents varies between devices. Refer to the device data sheet for additional information. Write Lock Bit 1 Write Lock Bit 2 Write Lock Bit 3 Set the indicated lock bit. Note that the AT89CI0511C2051 contain only two lock bits, while the AT89C51ILV51 and AT89C521LV52 contain three lock bits. The state of the lock bits cannot be verified by direct observation. Exit Quit the programmer control program. System Dependency The control programs for the AT89C51 and AT89C52 come in two flavors: host system-dependent and host system-independent. System-dependency results from the use of software timing loops to enforce required delays, the duration of which will vary between host systems running at different speeds. The code provided was tested on an 80386-based system running at 33 MHz, and may require modification for use on other systems. This method was chosen for its simplicity. Host system-independence is achieved by using the Programmable Interval Timer embedded in the system hardware to enforce time delays independent of system speed. The timer is reconfigured when the control program is invoked and restored to its original state before the program terminates. In order to guarantee that the program is not exited before the timer configuration is restored, the CTRL-C and CTRL-BREAK keys are disabled. This means that the program cannot be aborted except by specifying the exit option at the main menu or by rebooting the system. The timer control code is provided as an 8086 assembly language module, whiCh is linked with the compiled control pro- 4·4 Microcontroller gram. The granularity of the timer is 0.838 microseconds, but the minimum practical delay is system- and software-dependent. The timer code ensures that the delay produced will not be of shorter duration than requested. The control programs provided for the AT89C 10511C2051 are system independent. Programmer The programmer circuitry (see Figures 1 and 2) consists of the host interface and switchable power supplies. The signal sequencing and timing required for programming is generated by the host under software control. A 40-pin ZIF socket is provided for programming the AT89C511C52; the 20-pin ZIF socket accommodates the AT89C1051/C2051. Note that the power and ground connections and bypass capacitors required by the TTL devices are not shown on the schematic. Power for the programmer circuitry and the AT89C51/C521 C 10511C2051 is provided by a fixed five volt supply. A second supply provides either five or twelve volts, selectable, for use during programming. The addition of a transistor to the output of the variable supply provides a third level, ground, for use when programming the AT89CI051/C2051. The resistor values utilized in the variable power supply circuit were determined using the equations presented in the LM317 voltage regulator data sheet. Power supply ramp rates are accommodated by the host software. For 5 V-Vpp programming, the devices must be ordered from the factory as an AT89CXXX-5 (not available with the AT89C105112051). The programmer is connected to the host with a 25-conductor ribbon cable. To minimize the effect on signal integrity, the length of the cable should be as short as possible, preferably not exceeding three feet. Parallel Interface The original parallel interface provided by IBM was probably not intended to support bidirectional data transfers. However, due to the way in which the interface was implemented, bidirectional transfers are possible. Over the years, many products have appeared which exploit this capability. Unfortunately, many system and interface card manufacturers have not faithfully cloned the IBM design, resulting in bus contention when the peripheral attempts to drive return data into the interface. Usually the peripheral drivers can overpower the interface drivers and the peripheral works, though this is not considered a good design practice. Most parallel interfaces are now implemented in a single chip, such as the 82C411 or 16C452. These chips allow their output drivers to be disabled under software control, providing true bidirectional operation. The programmer software automatically enables bidirectional operation when used with parallel interfaces utilizing the 82C411, 16C452, or similar chips. Note that these chips also possess a mode control pin which must be at the correct level to enable the directional control feature. As a result, parallel interfaces utilizing these chips cannot be assumed to be bidirectional. Microcontroller If the programmer writes devices, but fails to verify, or the signal levels at the interface don't meet TIL specifications, the parallel interface may be incompatible with the programmer. A design is provided (see Figure 1) for a parallel interface which supports bidirectional operation and is compatible with the programmer. This design is simple, requiring only six les. The interface can be strapped to appear as LPTI (addresses 378-37F hex) or LPT2 (278-27F hex) and will be recognized by the POST when the host system is powered up. Due to its simplicity, the parallel interface cannot be used as a printer interface. • 4-5 Figure 1. AT89C Series Programmer Interface ~ 1lL /~-+ U2 r-01(i119 02 02 18 4 03 Q3 17 D4 04 15 os 05 14 06 08 13 8 07 07 12 08 11 CLK '70"" ~ di: A4 'ffHcffi4 aE 9 -A. vr, T '", I .~. 7 5 4 3 2 G 74 A5 as 4 ..E... ,--!< oc V3 1 -1- ~ c:t: 2h02 02 1~ 4 D3 03 5 D4 Q4 6 05 as 1 D6 06 07 07 9 08 12 STROBE. F 1 14 2 5 3 16 4 17 :3E F2 as 11 02 0--1< N 3 18 6 1 7 5 8 VCC 9 Ii' 7 10 23 11 24 12 ~F VO A ~ 1 .i:7i ASPECT ATX.ASX NOTE: 'ATX.ASX.' is the filename of the compiled ASPECT script to be associated with External Protocol 1. Convert the absolute object file 'TEST.ABS' to the hex file 'TEST.HEX': OH TEST.ABS TO TEST. HEX The resulting file, 'TEST.HEX' is ready to be uploaded. NOTE: ASMSI is version 2.3; RLSI is version 3.1; OH is version 1.1. Uploading a Hex File Run Procomm Plus and use the proper dialing directory entry to dial the remote station. After the connection with the remote station is established, press the 'PgUp' key and select 'I' (External Protocol 1) from the menu of upload protocols. This will execute the ASPECT script associated with External Protocol 1. When prompted, enter the name of the file to be uploaded, including the extension and path, if required. When the upload is complete, press ALT-H to hang up and ALT-X to exit Procomm Plus and return to DOS. Save the changes and exit the Setup utility. 4-13 • Figure 1. AT89C51 Moving Display Application Example U2 DO 01 02 03 04 05 D6 VCC .---If---"4-1 ~ .---t-lf--t--''- 3504 PO.' 3405 PO.s 33 06 PO.8 .. 07 PO.7 XI X2 RST P2.0 ~ P2.1 ~ P2.2 P2.a P2.' 125 A4 , P2.S P2.8 P2.7 : 28 A7, P3.0IRXD PalmeD pa.3I1I'lTf PS.4/TO PS.5/T1 I~:' Pf.D P1.t P1.S 01 3 03 S 05 7 6 0 07 • J • 10 '"";;;;Sip I::: PS.2IIl'Ifii Pl.2 P1.3 P1.4 r-- .00 PSEN ALElPROG P1.S ps.eiWR P1.7 P3.71RO Note: 0.1 uF bypass caps on alIICs. ~ 1. 17 ~ ~ AT89C51 P2.7 P2.8 A11:0 ~ SHlJTON# ;<-:-~ .0-- ~ 0-- t-it- 0-0-0-- vee t-'f~ T ~ I-F- + e8 ~ 10/6.3 ,. ,.• 7 0-0-- r,tt-J- • IS ~ 4-16 I I I. 1 DTE U9 2 V+ C1+ 8 v- el- ~ ~,. TX DTR AX 05R C2+ C2- "7 la 8 noUT T20UT R"N R2IN - The colon is the record header. The record length field consists of two hex digits, and represents the number of entries in the data field. OH outputs records containing 16 or fewer data field entries. The load address field consists of four hex digits, and indicates the absolute address at which the data in the data field is to be loaded. The record type field consists of two hex digits, which are always zero in data records. The data field contains from one to 16 pairs of hex digits. The last two hex digits are a checksum on the record length, load address, record type, and data fields. The sum of the binary equivalents of these fields and the checksum itself is zero. Each record in the file is tenninated by a carriage return and line feed. A type one record marks the end of the file. The record always contains the following value: ' :0000000 I FF' . II AlmEl 4-19 4-20 Microcontroller _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ M icrocontroller Controlling FPGA Configuration with a Flash-Based Microcontroller Introduction SRAM-based FPGAs like the Atmel AT6000 series come more and more into use because of the many advantages they offer. Their reconfigurability allows the user to implement more gates in his application than the FPGA actually has, simply by loading the gates as needed into the FPGA. This is also called "Cache Logic TM ." For an efficient use of cache logic, the FPGA must meet the following requirements: partial reconfigurability, a fast reconfiguration process and full architectural symmetry. The FPGA can control and change its configuration itself, but this can also be done in a very elegant way by a microcontroller. After the configuration process or in-between two configuration cycles it can be used for other purposes and is not lost for the application. The different options for space-saving realization, design protection or for fast, flexible reconfiguration are shown in this application note. The microcontroller used here is the Atrnel AT89C51 which is fully compatible to the industry standard i8031. 8-Bit Microcontroller with Flash Configuration Data Transfer between the FPGA and the Microcontroller The amount of information that makes up the configuration information for the FPGA is called a bitstream. It is a file stored somewhere. in a memory section. Figure 1 shows how this bitstream is structured: The bitstream begins with a token, the preamble, which indicates the beginning of the header section that contains global information concerning the whole configuration cycle. This is followed by the configuration information for the core cells and by the I/O configuration. The postamble indicates the end of the bitstream. These data are simply some data bytes that are sent one after another to the FPGA as a text file is sent to a printer. This is done in a serial or parallel fashion by implementing a transfer protocol that is not much different from the transfer protocol of a printer port. Application Note • The connections between an FPGA and a microcontroller for serial data transport are Figure 1. Bitstream Structure ~ Preamble Cells lIDs Postamble AT6005: 8 Kbyte I: AT6002: 2.6 Kbyte :1 0508A AIIDEL 4-21 Figure 2. Connecting an Atmel FPGA with the AT89C51. MO 11 h I-' M1 75 I-' M2 74 ~ DO 31 CCLK 32 ICON 33 ICS 43 -.L -~Vcc LJ Reboot ~ h I-' '- 33 ~ 34 ~ I-' 35 h I-' ~ ~ ICSOUT 35 :J IERR 38 ~ ~ ~ L- ICHECK 37 ~ ~ ~ '- 36 Port 0 37 38 39 FPGA (PLCC84) AT89C51 Figure 3. FPGA Reset Timing MO,1,2 a xxx xxx ICON ... ICS ICCLK JUlJlJ1J h-r1-rU II0s Reboot Time 30ns 2 clock cycles shown in Figure 2. Only 7 lines are used enabling full control of the configuration cycle. The microcontroller can force a complete reset of the whole FPGA by applying the mode 0 to the mode control lines. The state entered by the FPGA is the same state it will enter after power-up. All YOs are in tristate mode. The exact timing is shown in Figure 3. After triggering the reboot cycle, the FPGA will pull the ICON line to low. The microcontroller can check this line and detect the end of the cycle. 4-22 Microcontroller After a reboot cycle ICS and ICON are held high for two clock cycles. The microcontroller can then select an FPGA through the ICS line for configuration and start the configuration cycle by pulling ICON low. With each clock pulse on the CCLK line one bit of the bitstream transfers to the FPGA. The first transferred bit is the LSB of the preamble, the last transferred bit is the MSB of the postamble. To ensure the correct function of the internal state machine of the FPGA, 24 clock pulses are applied before and after a configuration cycle, for correctly entering the standby state between two configurations. These clock pulses are applied before ICON is pulled low and after ICON goes high. Microcontroller Figure 4. FPGA Configuration Cycle Timing MO,1,2 3 ~ ~ ICON /CS /CCLK DO Figure 5. Parallel Data Transfer MO 11 M1 75 74 M2 ~ ~ ~ ~ -c::J-------e Vee II -, ~ ~ Reboot --:L 31,30,29, 28,27,24, 23,22 32 00 .. 07 CCLK ~ ~ Port 1 34 ICON 33 /CS h 43 r-' ~ 35 ~ 36 ~ P ~ /CSOUT 35 /ERR 38 38 /CHECK 37 39 ~ FPGA Port ° 37 AT89C51 With the transition from low to high the FPGA indicates that the configuration cycle has ended. The exact timing is shown in Figure4. This is the configuration mode 3 that is, used for configuring several cascaded FPGAs. In this case all lines are brought to all FPGAs in parallel, except for the ICS lines. These connect to the ICSOUT pins of the preceding FPGAs in the chain. Only one bitstream that contains several configurations is needed to serve all FPGAs. The postambles are replaced by preambles to separate them. When the first FPGA in the chain sees a new preamble instead of a postamble, it will activate ist ICSOUT pin. The next FPGA in the chain is ready to accept the new configuration information, and so on. Another possibility is to connect all/CS lines to the microcontroller so that it can select the next FPGA to be configured. All other lines are brought to all FPGAs in parallel. In this case normal bitstreams are sufficient, not the special bitstream that is explicitly generated and contains several preambles as described above. If an error occurs during configuration, the microcontroller can detect this through the /ERR line. When the error is detected from the FPGA, e.g., an invalid preamble, this line will be pulled low to indicate the error to the microcontroller. When using several FPGAs the error lines can all be connected since this is an open collector output that can be WIRE-OR'ed. The microcontroller asserts the ICHECK line to determine whether the FPGA AIIDEL 4-23 is reconfigured. It also compares the bitstream it receives with the information that is already stored in the configuration memory within the FPGA. In the case of a difference the !ERR line is asserted. stored. In this case only two chips make up the whole system which saves board space. The configuration data is also protected by the lock bits of the controller preventing it from being reverse-engineered. If only reconfiguration of the FPGA without wanting error detection, the number of lines are reduced to three. ICS is tied to GND so that the FPGA is always selected. The microcontroller only has to provide the signals ICON, the configuration clock CCLK, and the data line. This solution uses the least board space. With parallel data transfer, as shown in Figure 5, 8 data lines instead of one are used to transfer one data byte instead of one data bit per clock cycle. The configuration time is therefore much shorter. For these data lines, the normal data bus of the microcontroller is used, and the data transfer is controlled through the IWR signal of the controller. Reconfiguration of the FPGA is just like writing to an external RAM. For a system where reconfiguration of the FPGA makes part of the regular system function this might be the most flexible solution. In this mode 6 as illustrated in the data book several FPGAs are cascaded as well. In this case, all lines except for ICS are brought to all FPGAs in parallel. ICS is connected to ICSOUT of the preceding FPGA in the chain to configure several FPGAs with one bitstream. The microcontroller can control the ICS pins to select the FPGA to be reconfigured as in a memory-mapped approach. The exact timing is shown in Figure 6. Another possibility is to store the data in a parallel flash or EPROM memory that is handled by the microcontroller. If a flash memory is used, the configurations are changed through the serial link of the microcontroller simply by downloading a new configuration into the flash memory. Depending on the size of the memory, many configurations are stored in the system. For example, for a 5000 gate FPGA, the AT6005, requires only 8 Kbytes of configuration data. The address space of an AT89C51 controller is 64 Kbytes of data memory. This amounts to eight full configurations (or 40000 gates) or, more partial configurations where the bitstream is much smaller depending on how much is changed in a cycle. Options for Storing Configuration Data For storing the configuration data within the system there are different possibilities, each having its advantages and disadvantages. The first possibility consists of using the internal memory of a controller to store the configuration information. At first glance this might look like a waste but it offers distinctive advantages that enable certain applications. The microcontroller AT89C51 has an internal memory of 4 Kbytes, so that a full configuration of the AT6002 and an additional 1.4 Kbytes of program are Figure 6. FPGA Select Timing MO,1,2 ICON ICS 6 ~ ~ ICCLK 00 .. 7 4·24 Microcontroller The software controlling the FPGA configuration resides within the internal memory of the microcontroller and only needs to know the start address of the bitstreams. It can detect the end itself by searching for the postamble. Another possibility might be a control program that after power-up searches the whole data memory for preambles (for bitstreams). Then the controller receives the command to download the second configuration into the third FPGA by its serial interface, and downloads this configuration into the FPGA, and so on. To control this approach, careful system planning is necessary in order not to destroy a working function. When using parallel memories instead of serial memories, the configuration is done very fast. Serial memories are more spaceefficient, but slower. In space-sensitive applications they can be a solution. There are serial memories that are connected to an FPGA directly. They allow only one configuration, and they are costly. When using a microcontroller, standard serial memories are used that are cheaper and store more than one configuration. For example, if an AT24C64 serial memory with 12C bus interface is used, more than 3 full configurations for the AT6002 is stored. Microcontroller Software Examples Provided that a configuration cycle has finished with the FPGA releasing the ICON line, a subroutine for transferring a configuration bitstream to a FPGA is relatively simple. In the case of parallel data transfer it is seen as the following: config: loopl: MOV DPTR, #200H MOVX A, @DPTR MOV P1, A SETB PO.5 CLR PO. 5 INC DPTR JNB PO.1, error JNB PO.4, loopl RET error: do something. jstart address bitstream ,load byte of bitstream joutput at port 1 ,one clock pulse high ,clock low ;next byte ;ERR is low? iif CON is low, continue ;configuration finished . In the case of serial data transfer a byte of the bitstream has to be converted from parallel to serial, but this is done with ROTATE instructions: RRC MOV RRC MOV RRC MOV A P1.6, C A P1.6, C A P1.6, C ;first bit to carry ; output carry as data bit jsecond bit to carry joutput carry as data bit ; third bit to carry ioutput carry as data bit A similar approach is applied in the case of a serial memory containing the configuration bitstreams. The microcontroller assembles them to a byte. When configuring in serial mode, this bit is handed over directly to the FPGA. When storing several configurations in the address space of a microcontroller, it is complicated and error-prone to change the start addresses of the bitstreams within the microcontroller program. Another possibility is shown in the following code example: a table of 8 start addresses is created and the microcontroller searches the address space for bitstreams. Each time he finds a beginning, the start address is stored in the table. With this approach several configurations are stored at variable locations. In this example it is assumed that every bitstream begins with the preamble and the control register content is 00 hex (this is the second byte of the bitstream). This program is simply to show the principles applying. It is also assumed that an AT89C51 with 4 Kbytes internal memory is used and the bitstreams are stored starting with address 1024 (0400 hex). CONTABLE NUM_CONFIG PREAMBLE POSTAMBLE CONTROLREG detect: loopl: db 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 ,space for 8 l6-bit pointers :number of configuration db EQU #10110010B EQU #01001101B EQU #OOOOOOOOB ,adjust to desired value ° MOV DPTR, #0400H MOV RO, NUM_CONFIG MOV A, @DPTR INC DPTR MOV R1, DPH CJNE R1, #10H, contl ;start searching at 0400 ;actual config address is held in RO ,load byte inext byte ;load high byte DPTR ,continue, if address below #1000H (that is, ;#4096D for a 89C51 that has 4KB of internal AJMP overrun ,else stop searching (end of memory) ; memory) contl: CJNE A, PREAMBLE, 100p1 ipreamble found? MOV MOV INC MOV MOV INC ,save DPTR low byte A, DPL, @RO, A RO A, DPH @RO, A RO ,save DPTR high byte inext pointer location AIIDEL 4-25 • loop2: cont2: loop3: MOV A, @DPTR INC DPTR MOV RI, DPH CJNE RI, #IOH, cont2 AJMP overrun CJNE A, CONTROLREG, loop2 MOV A, @DPTR INC DPTR CJNE A, POSTAMBLE, loop3 INC DPTR ;continue searching ;next byte ;test end of memory MOV RI, DPH ;text end of memory ;control reg found? ;yes, continue ;next byte ;postamble found? ;continue searching CJNE RI, #IOH, cont3 AJMP overrun overrun AJMP loopl ;for preamble RET iend of subroutine When it is known how many configurations are stored in the memory and where they are, they can be transferred to the FPGA. for example, through commands received with the serial interface of the microcontroller. A similar program can be written for storing the configuration data in serial memories, but here the bits have to be assembled to bytes first in order to search for the preamble. 4·26 Microcontroller Microcontroller Encryption and Security SRAM-based FPGAs always receive their configuration from the outside. Besides all advantages this offers, e.g., reconfigurability or testability, there can be problems with security and protection of the design. When the configuration is stored in a serial or parallel memory that is read directly by the FPGA, this memory can be copied. In this case no protection is available. The problem is only half as difficult as it seems because simply copying the configuration is not the whole job. This can only be used to copy the system, but the logic function of the FPGA is very difficult to deduce from the bitstream. The relation between a certain bit in the bitstream and the function it controls is very difficult to determine. Therefore, the circuit realized with the FPGA is very difficult to reverse-engineer. When using a microcontroller to configure the FPGA, additional security mechanisms are implemented. The bitstream can be encrypted before storing it in the system memory so that the microcontroller decrypts the bitstream before sending it to the FPGA. The key is hidden within the microcontroller or with external means, e.g., a smartcard or identification number. Even with very basic operations a high degree of security is reached. For example, if all bits of the bitstream are inverted the configuration bitstream is useless for the FPGA. Another way is to exchange some bytes with others through a table. This is a very easy and therefore fast operation that will slightly slow down the configuration process and will result in a high level of protection. Using the option indicated above (storing the configuration information within the internal memory of the controller) has other advantages. With the lock bits of the controller access to the memory can be inhibited even when the microcontroller is put on a programmer. With the chip-erase function of the Atrnel microcontrollers, the whole memory array can be erased in 10ms when the part of the system is accessed, e.g., by opening the case or entering a wrong identification number three times. This also works when the configuration is not stored within the microcontroller, but only the key number is stored. There are still weak points in the system. These are made up by the data and control lines between the FPGA and the microcontroller. They are sampled with a logic analyzer and the configuration information is extracted from the timing diagram. This is difficult, but not impossible. One needs to know the parts that are used in the system; the right key or identification number, and a running system for analyzing it. Only then the configuration for one given moment is known. It does not infer that the system can be copied. If partial reconfiguration is used, the design can be partitioned in two or more parts. The major part is transferred unencrypted and some few cells of central importance are transferred at another point of time or from the outside. A system that changes itself frequently is much harder to copy or reverse-engineer. Other tricks such as custom-marking the FPGA (so it is thought to be an ASIC), additional power and ground pins help to disguise the identity of the used part. By implementing all these methods, the process of copying the design is complicated, but there is no absolute security. Conclusion The following table shows the different options for parallel or serial configurations in conjunction with parallel or serial configuration storage. The given configuration times are for full configuration of an AT6005 without encryption. An A T89C51 microcontroller with a clock frequency of 24 MHz is used. For assessing the necessary board space, it was assumed that the microcontrollers are used with QFP packages and the memories are used in SOIC or TSOP packages. Connection to FPGA Serial Serial Parallel Parallel Extemal Memory Serial Parallel Serial Parallel Space Requirements 199mm2 329mm2 199mm" ~i2!)rnftl" Configuration Time 93ms 61ms 61ms 30ms The space requirements are mainly determined by the chosen memory. It is difficult to assess the board space required by parallel or serial wiring. Either one will be determined by application requirements, that is, fast reconfiguration or small space. Configuration time is more dependent on the connection between the controller and the FPGA; the memory connection is not as important. It is obvious that controlling the configuration of FPGAs with the help of microcontrollers is implemented very easily. When a controller is already in use within the system, only one additional port is required, and some space in the flash memory that might already be in the system as well. Flexibility in the design is increased and additional features can easily be implemented. 4-27 • 4-28 Microcontroller M icrocontroller Programming Atmel's Family Of Flash Memories Flash Introduction Atmel offers a diverse family of Flash Memory devices ranging in density from 256 K to 4 Mbits. These devices read and program with a single voltage supply. The nominal supply voltage is 5 V for the AT29Cxxx, 3.3 V for the "low voltage" AT29LVxxx, and 3 V for the "Battery-Voltage™" AT29BVxxx Flash family. The entire Flash family is designed to allow users to have one common programming algorithm for all three Flash voltage families. Therefore, upgrading from one density to another and from a higher voltage to a lower voltage device is simplified. This application note describes the design benefits of Atmel's Flash architecture as well as how the device 10 feature is used to adjust for varying densities and supply voltages. In addition, Atme!' s Software Data Protection (SOP) feature, which prevents inadvertent writes, is described. An example is given to illustrate the ease with which the programming software can be written to accommodate four different 4 Mbit Flash devices, the AT29C040, AT29LV040, AT29C040A, and AT29LV040A. Hardware and software have been developed to demonstrate the relevant design issues. The demo uses an AT89C5! Flashbased microcontroller (which has the same pinout and instruction set as an 80C5!) as the host processor and a "C" language program for the software. The software automatically adjusts the amount of time required for programming the varying voltage versions of the 4 Mbit Flash devices in addition to accommodating for their different sector sizes. The AT89C51, a member of Atmel's growing family of Flash microcontroller devices, features 4 Kbytes of in-system reprogrammabie Flash memory (see Atme! application note "AT89C5! In-Circuit Programming" for additional information). Current and future versions of Atmel's microcontroller family incorporate from as little as 1 Kbytes of Flash memory to as much as 128 Kbytes, providing many density options for different applications. Other versions will also in- . elude special architectures such as a combination of Flash and parallel EEPROM memory on board. Application Note Programming Flash Devices Unlike Atmel's Flash Memories, previous generations of Flash memories had large kilobyte sectors and required that an entire sector be erased prior to programming. Generally, the sector erase cycle time was hundreds or thousands of milliseconds and could be as long as 30 seconds for the entire memory array. In addition, a separate high voltage supply was required for a write and erase operation. Atmel's Flash family has simplified usage by having only one supply voltage, reducing the sector size, having the programming similar to an SRAM write operation, and decreasing significantly the total programming time. Small sector sizes reduce the amount·of system resources necessary for programming. When only a few bytes in a Flash memory need to be altered, a RAM image of the Flash sector must be created. The RAM must then be altered with the new data, and the image transferred back into the Flash device. Because Atmel' s Flash devices have small sector sizes (from 64 to 512 bytes, depending on the memory density), the RAM requirements are much less than those of large sector Flash devices. The latter generally have 4 K to 128 Kbyte sector sizes. A second advantage of Atmel's Flash is that an entire sector can be updated during a single program operation, instead of the byteby-byte programming of previous generation Flash memories. This saves significant programming time when updating an entire sector, especially when comparing Atmel's small sector devices with large sector devices. In addition, Atmel' s devices do not require a sector erase prior to writing, thus AIIIEL • 0510A 4·29 saving additional programming time. The maximum sector prograpt time is 10 ms and 20 ms for the AT29Cxxx and AT29LVxxx/AT29BVxxx families respectively. AT29C040 and AT29C040A Architecture The AT29C040 provides operation similar to a byte-wide SRAM. The device has eight data lines and 19 address lines. The familiar three input control lines are also present (CE, OE, WE). Read operations are identical to an SRAM, but write operations are somewhat different due to the write cycle time (twe) requirements of all Flash memories. Flash write operations take several milliseconds to complete, compared to the nanosecond writes of SRAM devices. It should be noted that Atmel's Flash Memories require only a write operation; the erase operation is automatically performed internally in the device. Data is loaded into the AT29C040 one sector at a time, with each sector consisting of 512 bytes. The sector chosen for modification is defined by the upper order address bits (A9-A1B). The entire sector must be loaded during the write operation. Any byte not loaded during the sector load will contain FFH after the write operation has completed. Address lines AO through AB define the location of the bytes within a sector. All data must be loaded into the same sector (A9 through AlB must remain constant) and can be randomly loaded within that sector. The AT29C040A is identical to the AT29C040 except for the sector size and the Device ID Code (the Device ID Code is described later). The AT29C040A has a 256 byte sector (instead of a 512 byte sector) which is defined by address lines AB through AlB; the bytes within the sector are determined by address lines AO through A7. Software Data Protection (SOP) One concern of systems designers when using nonvolatile programmable memories is the possibility of inadvertent write operations that can be caused by noise or by power-up and powerdown sequences. Atrne1' s Flash memories provide a feature called Software Data Protection (SDP) that addresses this issue. The user can enable SDP upon receipt of the device from Atrnel, and its usage is highly recommended. Data can be written into a sector with or without SDP enabled. However, once SDP has been enabled, the device requires that all subsequent write operations perform a series of "dummy" write operations before loading the chosen sector with data. The "dummy" writes consist of loading three known data values into three predefined addresses. This three-byte sequence preceding a write operation virtually eliminates the chance of inadvertent write operations. The sequence is described below. I. Load Data AAH into Address 05555H 2. Load Data 55H into Address 02AAAH 3. Load Data AOH into Address 05555H 4. Load desired sector with data 5. Pause twe (device write cycle time) 6. The device is returned to standard operating mode 4·30 Micrcontroller If SDP is enabled, any attempt to write to the device without the three-byte command sequence will start a write cycle. However, no data will actually be written to the device, and during this "write" cycle time (twe), valid data cannot be read from the Flash. Product and Manufacturer 10 Atmel's Flash memory devices allow the user to access both device and manufacturer information. This feature allows a system to determine exactly which Flash memory is being used. Once this is known, the host system can choose different algorithms for write operations in order to accommodate for differences in device density , Vee requirements, sector size, and required write cycle time. Product and manufacturer ID information is determined with the Software Product Identification procedure, which is similar to the Software Data Protection sequence. The sequence is described below. 1. Load Data AAH into Address 05555H 2. Load Data 55H into Address 02AAAH 3. Load Data 90H into Address 05555H 4. Pause twe (device write cycle time) 5. Relld Address OOOOOH Data read is the Manufacturer Code 6. Read Address OOOOlH Data read is the Device ID Code 7. Load Data AAH into Address 05555H B. Load Data 55H into Address 02AAAH 9. Load Data FOH into Address 05555H 10. Pause twe (device write cycle time) 11. The device is returned to standard operating mode The following table uses the 4 Mb Flash as an example to illustrate the pertinent device information than can be determined once the Device ID Code is known. SECTOR SIZE DEVICE ID AT29C040 AT29C040A 5B AT29LV040 AT29LV040A C4 3.3V+ 0.3V 256 bytes 20ms AT29BV040 3B 3.0V± 10% 512 bytes 20ms AT29BV040A C4 3.0V± 10% 256 bytes 20ms Vee 5.0V+10% twe 512 bytes 10ms A4 5.0V+10% 3B 3.3V± 0.3V 256 bytes 10ms 512 bytes 20ms Microcontroller Hardware Description The demo hardware consists of a 12 MHz AT89C51 Flashbased microcontroller with 4 Kbytes of on-board Flash memory. The internal AT89C51 Flash memory is used for boot code, and the external 8K x 8 SRAM and the AT29C040 are mapped as data memory. The AT29C040 is also mapped as program memory to facilitate off-chip program execution. The AT89C51 can only access a maximum of 64 Kbytes of data memory space, while the AT29C040 has 512 Kbytes of storage capacity. To solve this size mismatch, the AT29C040 is bank switched into the AT89C51 data memory map in 8 Kbyte blocks. The bank switching is performed with six general purpose I/O port bits on the AT89C51. The system address map is shown below. System Address Map AT89C51 Microcontroller 0000-IFFF Internal program memory 8 K x 8 Static RAM 2000-3FFF Data memory AT29C040 Flash 4000-5FFF Program and data memory Software Description The software (available from Atme!'s BBS 408-436-4309) demonstrates how the Device ID Code can be used to allow a single program to work with different Atmel Flash memories. The program uses Atme!'s 4 Mb Flash (AT29C040, AT29LV040, AT29C040A, and AT29LV040A) as an example, but the software can be easily adapted to accommodate other device densities. In order to program the determine which Flash plished by first putting Identification mode by Flash memory, the software must first device is being used. This is accomthe device into the Software Product executing a lhree-byte command se- quence (described in the "Product and Manufacturer ID" section of this application note). The program subsequently reads the Device ID Code and executes another three-byte command sequence to return the Flash to the standard operating mode. Using the Device ID Code, the program then determines the appropriate sector size and write cycle time (twe) for the particular 4 Mb Flash being used. To demonstrate a sector write, the program proceeds to load the SRAM with "dummy" data. After the data has been loaded, the program transfers the data from the SRAM to a predefined sector (within one of the mapped 8 Kbyte blocks) of the 4 Mb Flash. After pausing the required write cycle time (twe), the sector that was just written is transferred back to the SRAM buffer. Summary Atme!' s Flash Memories are designed to allow all densities and device configurations to be programmed using the same programming algorithm. The user has to simply determine the Device ID Code and set the appropriate sector size and write cycle time. This operation need only be performed once provided the sector size and write cycle information is saved. If only one density or configuration will ever be used, then reading of the Device ID Code can be eliminated, and the sector size and write cycle information can be predefined in the software. As demonstrated, programming Atmel's Flash is a simple process, similar to loading an SRAM. Architectural and circuit features within the devices minimize software and system overhead while simplifying programming procedures. Atmel's Flash Memories require only about one-tenth of the typical software, buffer memory, and performance overhead of previous generation Flash, thus providing substantial system cost savings. 4-31 II ~ Atmel AT29C040DA Demo Circuit s: c:r 0 01. 34567 ri o ~ ... P+ 2!f~ ~ -= .---- vec ~,~ I 13 OC vec o-llCLK 12 MHz 19 PO.O PO.l X1 PQ.2 ---.I.IL X2 PO.4 PO.S i r;::::= PO,B PO.7 RESET Pl.D P2.0 P2.1 P2.2 P2.3 P2.4 P2.S P2.B P2.7 P1.1 P1.2 P1.3 lID WI! INTO INT1 TO T1 1 = ~ ILE/P TXD RXD P1.7 1. 111 1 • A 10 17 A A 111111 8765 II PE ~~ C m v e c f 1 131 -= YO Y1 Y2 "" g~ Hs o-l vaB:j H ~ ~~ P- 74HCT138 Note: If the Flash is to be used as external program memory, then pin 31 (EN Vpp) of the AT89C51 cannot be connected to ground. AI---*- ~i H ~ Da H • 8 A 8 S 27 4 CE2 ~vec 8Kx8SRAM 1 4 AT8ge51 2 ~f ~ PSEN P 1.4 P1.5 P 1.6 A 07 ,. 08 OS 04 oa 02 Q1 aD 07 D8 DS D4 oa 02 01 PO.3 9 < 10K ") ~ EA/VP AO A1 A. Aa A4 AS A6 A7 A8 A9 A10 A11 A1' r-w 18 .-----f.,---l!L AD A1 A. Aa A4 AS A6 A7 A8 A9 A10 A11 A12 A1. A14 A1S A18 A17 A18 DO D1 D. Da D4 DS D8 D7 i AT29C040 M icrocontroller Analog-to-Digital Conversion Utilizing the AT89CX051 Microcontrollers The Atmel AT89C1051 and AT89C2051 microcontrollers feature on-chip Flash, low pin count, wide operating voltage range and an integral analog comparator. This application note describes two low-cost analog-todigital conversion techniques which utilize the analog comparator in the AT89C 1051 and AT89C2051 microcontrollers. RC Analog-to-Digital Converter This conversion method offers an extremely low component count at the expense of accuracy and conversion time. In the example presented below, resolution is better than 50 millivolts, accuracy is somewhat less than a tenth of a Volt and conversion time is seven milliseconds or less. As shown in Figure 1, the RC analog-todigital conversion method requires only two resistors and a capacitor in addition to the AT89CX051 microcontroller. A microcontroller output (pin 11), which swings from approximately ground to Vee, alternately charges and discharges the capacitor connected to the non-inverting input of the internal comparator (pin 12). The microcontroller measures the time required for the voltage on the capacitor to match the unknown voltage applied to the inverting input of the internal comparator (pin 13). The unknown voltage is a function of the measured time. The HP5082-7300 LED displays shown in Figure I are not required for the conversion, but are utilized by the software to implement a simple two-digit voltmeter. The result of the analog-to-digital conversion is displayed in volts and tenths of a volt on the two displays. The voltmeter application does not utilize the full resolution of the RC conversion software, but serves to demonstrate the method as well as providing a tool for debug. The waveform for a typical capacitor charge/discharge cycle is shown in Figure 2. The discharge portion of the curve is identical to the charge portion rotated about the line Ve = Ved2. The equations and discussion below apply to the charge portion of the cycle, except where indicated. The voltage on the capacitor as a function of time is given by the exponential equation: Ve =Vee (l-e -tiRe) (1) a-Bit M icrocontroller with Flash Application Note where Ve is the voltage on the capacitor at time t, Vee is the supply voltage and RC is the product of the values of the resistor and capacitor. Note that voltage is expressed in Volts, time in seconds, resistance in Ohms and capacitance in Farads. The product RC is also known as the "time constant" of the network and affects the shape of the waveform. The waveform is steepest when capacitor charging or discharging begins and flattens with time. II The first problem with the RC conversion method is the difficulty of solving the exponential equation without utilizing floating point calculations and transcendental functions. On a compressed time scale, the exponential curve appears straight over much of its length, suggesting that it might be approximated by a line. This scheme fails due to the continuous variation in slope over the length of the curve, which produces significant error. It also does not address the problem where the curve rolls off severely near the asymptote at Vee. The microcontroller need not solve the exponential equation in real time if a lookup table is used to map pre-calculated values to each sampled time interval. This scheme allows the data to be encoded and formatted as required by the application while simplifying the conversion software. Symmetries in the data may be exploited to reduce the size of the table. 0524A AIIDEL 4-33 Figure 1. Two-Digit Voltmeter vee .1 ?- Unknown !Vi("': VoI1agoln ~ 1OUF I B.2K H 1 4 .l 30pF RST X2 D T >--j~F 12MH. 5 ~ -+ ~ P3.0/RXO P3.1(TXO P3.2/iNTO -----.!. P3.4!T0 P3.5/T1 -+ ~ vee Xl ,---1L +Pl.0 -Pl.l Pl.2 Pl.3 Pl.4 Pl.5 Pl.6 Pl.7 P3.3~NTI P3.7 1 1: vee J t- 15 16 17 18 19 B 1 2 3 ~ AT89CX051 5 5.1 K R ~7 297K 1% T V The second problem with the RC conversion method is the substantial error which results from variations in component values. Figure 3 shows an exaggerated view of the variation in the voltage on the capacitor due to variations in the values of the resistor and capacitor. As shown in the figure, the variation in the voltage on the capacitor decreases as the voltage on the capacitor decreases. The symmetry of the capacitor charge/discharge cycle can be exploited to reduce the effect of variations in component values on conversion accuracy. This is done by utilizing the charge portion of the cycle to measure voltages less than Ved2 and the discharge portion to measure voltages greater than Ved2. The worst case error is reduced to the error at Ved2. Before component values can be assigned, the time interval at which the comparator output is to be sampled must be determined. The sample interval should be as short as possible to maximize converter resolution and ·minimize conversion time. The sample interval is limited by the time required to execute the requisite code, which is determined by the clock rate of the microcontroller. In the voltmeter application, the microcontroller operates with a 12 MHz clock, resulting in a sample interval of five microseconds. The time constant (RC) affects the shape of the capacitor charge/discharge waveform. The value of the time constant must be chosen so that the steepest parts of the waveform are resolvable to the desired resolution. The steepest part of the charge portion of the waveform occurs near the origin, while the 4-34 Microcontroller 8 1 2 3 00 01 D2 D3 .............i. OP 5 [j) 00 01 02 D3 OP [j) HP6OII2·7300 HP6OII2·7300 UNITS TENTHS C 2nF 5% steepest part of the discharge portion occurs near Vce. Due to the symmetry of the waveform, the same time constant may be used for measurements made on either portion of the waveform. Figure 4 shows an expanded view of the relationship between voltage and sample time near the origin. In the figure, eN is the desired voltage resolution of the converter and 6.t is the sample interval determined previously. The curve labeled 'Ve' represents the voltage on the capacitor, which appears linear at this scale. In the figure, the slope of the curve is ideal, causing sampling to occur near the center of the voltage intervals. The slope of the curve may be less than shown, but may not be greater, or resolution will be lost. Note that the first sample is offset from the origin by 112 6.t to center the sample in the first voltage interval. To obtain the minimum value of the time constant which will produce the required slope at the first sample, solve Equation 1 forRC: RC =-tlln(l-VdVec) (2) Then set 6.V to the minimum desired resolution (O.05-volt), 6.t to the sample interval determined previously (five microseconds), and calculate RC at the first sample point, where Ve = 112 6.V and t = 112 6.t: RminCmin = (-1I2)6.t In[1-(1/2(6.V»Neel =4.99.10-4 In[1-(1I2)(O.05)Neel Microcontroller The product of the values of Rand C must not be less than the calculated minimum time constant. Utilizing a resistor with a one percent tolerance and a capacitor with a five percent tolerance: (Rnom-l%)(Cnom-5%) >=4.99.10-4 . In the voltmeter application, the selected values of Rand C are 267 kilohms and 2 nanofarads, respectively, ielding a minimum time constant of approximately 5.02.10- . An additional constraint is placed on the value of R. Referring again to Figure I, note the 5.1 kilohm pullup resistor connected to pin 11 of the microcontroller. This resistor is present to supplement the microcontroller's weak internal pullup, but has the detrimental effect of changing the time constant of the RC network during the charge portion of the capacitor charge/discharge cycle. This produces an asymmetry in the charge/discharge waveform, which contributes to conversion error. To minimize the effect of differences in the capacitor charge and discharge paths, the value of R should be chosen to be much greater than the value of the pullup resistor. In the voltmeter application, the selected value of R is 267 kilohms, which exceeds the value of the pullup resistor by more than an order of magnitude. Figure 2. Typical Capacitor Charge/Discharge Cycle Vee of the waveform, the determined value applies to both the charge and discharge portions of the cycle. Solving Equation I for time yields: (3) t = -RC.ln(I-Vc/Vcc). Assuming a resolution of 0.05 Volt, the desired capacitor voltage is: Vc = Vcc-(1I2)(0.05) = Vcc-0.025. From Equation 3: tmax = -RmaxCmax.ln(1-(Vcc-0.025)Ncc) -(Rnom+ 1%)(Cnom+5% )In(O.025Ncc) -(1.01)(267.103)(1.05)(2.1O-9)ln(0.025/5.0);: 3 ms. The minimum number of samples required in the measurement loop is determined by calculating the time required for the voltage on the capacitor to reach Vcd2 and dividing the result by the sample interval. The maximum value of the time constant is used in the calculation, since the voltage on the capacitor rises slower when the values of the resistor and capacitor are large. Due to the symmetry of the capacitor charge/discharge waveform, the determined sample count may be used for measurements made during either portion of the cycle. • Figure 3. Capacitor Voltage Variation as a Function of RC Variation Vce __ Vcmax -t-----,,+'- - -- - - - RC Rein - - - Rc:,"ax Vc-t----~--,~ Vernin -t---T-~<-::-I"'-- The time constant (RC), which is a function of the desired converter resolution, determines the duration of the capacitor charge/discharge cycle. The more time required for the capacitor to charge .and discharge, the greater the number of samples required in the measurement loop and the greater the number of entries in the lookup table. From Equation 3: tmax = -RmaxCmax.ln(1-(1I2)Vcc/Vcc) -(Rnom+ 1%)(Cnom+5% )In(1I2) -(1.01 )(267.1 03)(1.05)(2.1 0-9)ln(1I2) _ 393 !!s. The time required for the capacitor to charge and discharge is approximated by calculating the maximum time for the voltage on the capacitor to rise to within one half of the smallest resolvable voltage interval from the asymptote. For the charge portion of the waveform, the asymptote is at Vee. Due to the symmetry The minimum number of samples for half the cycle is: tmaxl ilt = (393.10-6)/(5.10-6) = 79. To maximize accuracy, voltages from zero to Vcd2 are measured during the charge portion of the capacitor charge/discharge cycle and voltages from Vcc to Vcd2 are measured during the 4-35 discharge portion of the cycle. As a result, the total number of entries in the table is twice the number of samples calculated previously for each half cycle. voltages, increasing in the first half, decreasing in the second, tracks the voltage on the capacitor and defines the ordering of the table entries. The lookup table contains application-specific values corresponding to the calculated voltage at each sample. For each half cycle, the Nth entry in the table corresponds to the voltage at t = (N-l) .1.t, where .1.t is the sample interval determined previously. For the charge half cycle, the voltage at each sample is calculated by solving Equation 1 for the time elapsed since the capacitor began to charge. For the discharge half cycle, the voltage at each sample is calculated by solving the following equation for the time elapsed since the capacitor began to discharge: Vc = Vcc.e-tlRC (4) N=O N=1 Figure 4. The Relationship between Voltage and Sample Time near the Origin N=O N= 1 Sample Sample The size and contents of the table may vary from application to application depending on the sample interval and conversion resolution. As the resolution increases, the number of entries in the table grows. In the voltmeter application, with resolution equal to 0.05 Volt, the lookup table contains 158 entries, which is twice the number of samples per half cycle calculated above. Voltages corresponding to samples taken during the charge half cycle are calculated by replacing 't' with 'N .1.t' in Equation 1, where N represents the sample number (0-78). By setting .1.t equal to the sample interval of 5 microseconds, R to 267 kilohms, C to 2 nanofarads, and Vcc to 5.00-volts, Equation 1 becomes: V = 5(1-e-N (.0093633». Voltages corresponding to samples taken during the discharge half cycle are calculated by replacing 'I' with 'N .1.1' in Equation 4, where N represents the sample number (0-78). Using the same values as for the charge half cycle, Equation 4 becomes: V = 5.e-N(.0093633) ). An abbreviated list of the voltages calculated for the capacitor charge/discharge cycle is shown below. The ordering of the 4-36 Microcontroller N=74 N=75 N=76 N=77 N=78 V=O.OOO V=0.047 V= 2.499 V= 2.523 V=2.546 V=2.569 V= 2.591 V=5.000 V=4.953 N=74 V=2.501 N=75 V= 2.477 V= 2.454 N=76 V= 2.431 N=77 V=2.409 N=78 As shown by the list, the number of samples in each half cycle is greater than required to reach the midrange value of 2.500 Volts. This allows for "fast" cycles which overshoot the nominal midrange value before the last sample is taken in each half cycle. Note that the difference between the calculated voltages at samples N=O and N=1 is within the desired resolution of 0.050-volt, but the difference in voltage between adjacent samples decreases as N increases. This reflects the non-linear relationship between voltage and time in the circuit. The calculated voltages shown in the list are not entered into the lookup table, but are used to determine the values of the table entries. In the voltmeter application, the calculated voltages are rounded to tenths of a volt and the result stored in the table in packed-BCD form, two digits per byte. Example: the table entry corresponding to 2.523-volts is 25 hex, which displays as 2.5-volts. The voltmeter prototype demonstrated accuracy of +/- one count (0.1 Volt), but accuracy of somewhat less than a tenth of a Volt is about the best that can be expected from the RC analog-to-digital conversion method. Even using precision components, variations in component values may contribute an error of +/- 0.104-volt, as shown below. To calculate the worst case error at Vc = 2.5-volts, first determine the corresponding t at the nominal values ofR and C using Equation 3: t = -RnomCnom.ln(I-VclVcd = -RnomCnom.ln(1-2.5/5.0) = -RnomCnom.ln(O.5). Microcontroller Successive Approximation Analog-to-Digital Converter Substitute for t in Equation 1 to get minimum Vc: Vcmin Vcc (l_e- tl(RmaxCmax» V cc (l_e(RnOm Cnom/Rmax cmax)ln(O.S» = = = 5 (l_e1n(O.S)/(1.01 0 This conversion method offers good resolution and accuracy and a short conversion time at the expense of increased componentcount. 1.0S» Successive approximation (SA) ADCs incorporate a digital-toanalog converter (DAC), a comparator and a successive approximation register (SAR). The SAR controls the conversion by performing a search for the binary code which, when fed to the DAC, will produce an output matching the voltage to be converted. The comparator compares the DAC output to the unknown voltage and returns the result to the SAR. = 2.399 V Again, for maximum Vc: V cmax = V cc (l_e-tl(Rmin Cmin» V cc (I-e(Rnom CnomiRmin Cmin)ln(O.S» = = 5 (l_e1n(0.5)/(O.99 0 0.9S» =2.607 V The results show a variation of 0.208-volts at 2.5-volts, or a worst case error of +/- O.I04-volts. The worst case conversion error may be further reduced by utilizing components with tighter tolerances. Conversion accuracy and linearity are also affected by the characteristics of the capacitor. The capacitor used in the voltmeter prototype is a polystyrene film type, which not only provides good accuracy, but minimizes error due to dielectric absorption and other effects. The SAR begins the search with the most significant DAC bit, which controls the widest output variation, and moves toward the least significant bit, causing the DAC output to "zero in" on the unknown value. The result of the trial is the binary code corresponding to the unknown value. In an eight-bit SA converter, only eight iterations are required to find the correct binary code, resulting in relatively fast conversions. In this application (Figure 5), an A T89CX051 microcontroller with an integral analog comparator performs the SAR function in software, reducing the component count. The DAC selected Error sources which have not been examined include: comparafor the application is an MC1408-8, eight-bit, current output tor limitations; asymmetries between the charge and discharge type chosen for its low cost. Seven- and six-bit versions are portions of the cycle; failure of the voltage on the capacitor to available as the MC1408-7 and MC1408-6, respectively. The reach ground or V cc; variations in V cc. The contributions to MC1408 series is guaranteed accurate to within +/- 112 LSB at conversion error made by these sources can be expected to in25 degrees C at a full scale output current of 1.992 milliamps. crease error to somewhat more than the value due to component The relative accuracy of the MC1408-8 is better than 0.19%, tolerances alone. assuring eight-bit monotonicity and linearity. The DAC has an output settling time of 300 nanoseconds. FigureS. Successive Approximation Analog-to-Digital Converter +15 ~--.----~~ o 2.SK Ro '" 2.5K ". vee ,. ~-I~--~---~x' 30pF lF355B .. L----..l1 RST 12MHz P3.DIRXO PS.1fTXO PS.2/lNTO 11 +Pl.0 -Pl.1 AB vee A7 P1.2 P3.3/1tm P3.4(TO P3.6{T' Pl.3 15 P1A 18 P1.5 Pl.8 17 18 pS.7 Pl.7 19 MC1408-8 AS All A4 AS ""A' VR+ AT89CX051 'OUT VR- vee RANGE COMP 4 -4- 10 ,. Rref 1.24K '" 4-37 II AlmEl The DAC contains binary-weighted, current-steering switches which scale an input current by the applied binary code. The input current is derived from an LM336-2.5 precision voltage reference and a series resistor. The scaled current output is converted to a voltage by an LF355B operational amplifier wired as a current-to-voltage (IN) converter. The LF355B op amp was selected for the IN converter because of its low input offset voltage and high output slew rate. The voltage output of the IN converter is fed into the AT89CX05l comparator, where it is compared to the unknown voltage. When the programmed voltage exceeds the unknown voltage the output of the comparator goes high, which is detected by software. A second op amp, wired as a non-inverting, unity gain buffer may be inserted between the unknown voltage source and the input to the AT89CX051 comparator to provide isolation. The LM336-2.5 reference provides a nomina12.490-volt output (Vref). The actual voltage may vary from 2.390-volts to 2.590-volts. The reference voltage and temperature coefficient may be trimmed using the method indicated in the LM336-2.5 data sheet. The nominal value of the current reference resistor (Rref) connected to pin 14 of the DAC is 1240 Ohms, yielding a reference current (Iref) of 2.490 V 11240 Ohms (VreflRref) = 2.008 milliamps. The eight-bit binary code applied to the DAC scales Iref by from 01256 to 2551256, resulting in a current output (10) of from zero (Iref.01256) to 2.000 milliamps (Iref .2551256) full scale. Note that the sign of the DAC output current is opposite the sign of the reference (input) current. The output voltage is determined by multiplying the DAC output current (10) by the value of the IN converter gain resistor (Ro). Nominal full scale output voltage is 2.000 mA.2500 Ohms (10 F.S .• Ro) = 5.000-volts. The circuit does not provide adjustments for offset or gain. Offset voltage adjustments should not be required, due to the low offset voltage specification of the LF355B op amp. If the offset voltage must be adjusted, add the offset trim circuit shown in the LF355B data sheet. The gain may be changed by changing the value of the IN converter gain resistor (Ro). The resistor connected to the non-inverting input of the op amp should be of the same value as the gain resistor for input bias current balancing. The 1240 Ohm resistor connected to pin 15 of the DAC and the 2500 Ohm resistor connected to pin three of 4-38 M icrocontroller the op amp may be eliminated with only a slight decrease in performance. The MC1408-8 DAC requires power supplies of +5.0-volts and -5.0 to -15-volts; +1- 5.0-volt supplies were selected to minimize power consumption. The LF355B op amp requires bipolar supplies between +1-5.0-volts and +1-15-volts. -5.0-volts was selected for the negative rail for compatibility with the DAC, but may be replaced with -15-volts, if desired. The positive supply was chosen to be +15-volts to allow the limited output swing of the op amp to reach the five Volt upper input limit of the comparator. The speed of the A-to-D conversion is limited by the DAC output settling time, the slew rate and settling time of the op amp, the response time and slew rate of the comparator and the time required to execute the successive approximation algorithm. The DAC output settling time and the comparator response time are negligible compared to op amp delays and the time required to execute the SA algorithm, and so may be ignored. The maximum voltage step input to the op amp is five volts, which requires one microsecond to slew and four microseconds to settle (see the LF355B data sheet). This delay is accommodated in the software; consult the listing for additional information. With a 12 MHz processor clock and the resulting one microsecond instruction cycle, an eight-bit conversion can be performed in under 300 microseconds. The unknown input voltage must be held constant for the duration of the conversion. Obvious disadvantages to the successive approximation analogto-digital converter presented here are the need for bipolar power supplies and the large number of microcontroller I/O pins required to control the DAC. The + 15-volt supply could be eliminated by replacing the LF355B op amp with a single supply, five Volt, furrctional equivalent with outputs that swing rail-to-rail. The number of microcontroller I/O pins required to control the DAC could be reduced somewhat by substituting a seven or six bit DAC. The parallel input DAC could be replaced with a (more expensive) serial input DAC. Alternately, logic could be added to accept serial data from the microcontroller and present parallel data to the DAC. The software for this application may be obtained by downloading from Alme!'s BBS: (408) 436-4309. Consult the comment block at the beginning of the source code file for detailed information on features and operation. Microcontroller Interfacing AT24CXX Serial EEPROMs with AT89CX051 Microcontrollers Serial memory devices offer significant advantages over parallel devices in applications where lower data transfer rates are acceptable. In addition to requiring less board space, serial devices allow microcontroller 110 pins to be conserved. This is especially valuable when adding external memory to low pin count microcontrollers such as the Atrnel AT89C1051 and AT89C2051. hard-wired to a unique address. In the figure, the first device recognizes address zero (AO, AI, A2 tied low), while the eighth recognizes address seven (AO, A 1, A2 tied high). Not all members of the AT24CXX family recognize all three address inputs, limiting the number of some devices which may be present to less than eight. The exact number of devices of each type which may share the bus is shown in Table 1. This application note presents a suite of software routines which may be incorporated into a user's application to allow an AT89CX051 microcontroller to read and write AT24CXX serial EEPROMs. The software supports all members of the AT24CXX family, and may easily be modified for compatibility with any of the Atrnel 8051-code compatible microcontrollers. 8-Bit Microcontroller with Flash Application Note Bidirectional Data Transfer Protocol I The Bidirectional Data Transfer Protocol utilized by the AT24CXX family allows a number of compatible devices to share a common two-wire bus. The bus consists of a serial clock (SCL) line and a serial data (SDA) line. The clock is generated by the bus master and data is transmitted serially on the data line, most significant bit first, synchronized to the clock. The protocol supports bidirectional data transfers in eight-bit bytes. Hardware A typical interconnection between an AT89CX051 microcontroller and an AT24CXX serial EEPROM is shown in Figure 1. As indicated in the figure, up to eight members of the A T24CXX family may share the bus, utilizing the same two microcontroller 110 pins. Each device on the bus must have its address inputs (AO, A 1, A2) In this application, the microcontroller serves as the bus master, initiating all data transfers and generating the clock which regulates the flow of data. The serial devices Table 1. Atrnel's Two-Wire Serial EEPROM Family Device Size (Bytes) Page Size (Bytes) Max Per Bus Addresses Used AT24C01 1K 8 1 None AT24C01A 1K 8 8 AO,A1,A2 AT24C02 2K 8 8 AO,A1,A2 AT24C04 4K 16 4 A1,A2 AT24C08 8K 16 2 A2 AT24C16 16 K 16 1 None AT24C164 16 K 16 8 AO,A1,A2 AT24C32 32K 32 8 AO,A1,A2 AT24C64 64K 32 8 AO,A1,A2 0507A AIIDEL 4-39 Figure 1. Typical Circuit Cinfiguration vcc 1'O"F vee RST X2 5.1 K 5.1 K D x, 30pF 12MHz P3.0/RXD +P1.Q PS.1fTXD P3.21iNfO -P1.1 P3.3/im'1 P3.4rro P3.sfn 11 P3.7 P1.2 P1.3 P1.4 P1.S Pl.S Pl.7 '2 '3 ,. ,.'5 ,.,. 17 vee AT89CX051 Device 0 present on the bus are considered slaves, accepting or sending data in response to orders from the master. The bus master initiates a data transfer by generating a start condition on the bus. This is followed by transmission of a byte containing the device address of the intended recipient. The device address consists of a four-bit fixed portion and a three-bit programmable portion. The fixed portion must match the value hard-wired into the slave, while the programmable portion allows the master to select between a maximum of eight slaves of similar type on the bus. AT24CXX serial EEPROMs respond to device addresses with a fixed portion equal to '1010' and a programmable portion matching the address inputs (AD, AI, A2). Not all members of the AT24CXX family examine all three address inputs; Table I shows which of the three address inputs are valid for each member of the family. The eighth bit in the device address byte specifies a write or read operation. After the eighth bit is transmitted, the master releases the data line and generates a ninth clock. If a slave has recognized the transmitted device address, it will respond to the ninth clock by generating an acknowledge condition on the data line. 4-40 Microcontroller Device 7 A slave which is busy when addressed may not generate an acknowledge. This is true for the AT24CXX when a write operation is in progress. Following receipt of the slave's address acknowledgment, the master continues with the data transfer. If a write operation has been ordered, the master transmits the remaining data, with the slave acknowledging receipt of each byte. If the master has ordered a read operation, it releases the data line and clocks in data sent by the slave. After each byte is received, the master generates an acknowledge condition on the bus. The acknowledge is omitted following receipt of the last byte. The master terminates all operations by generating a stop condition on the bus. The master may also abort a data transfer at any time by generating a stop condition. Refer to the AT24CXX family data sheets for detailed information on AT24CXX device operation and ·Bidirectional Data Transfer Protocol bus timing. The software for this application may be obtained by downloading from Atmel's BBS: (408) 436-4309. Consult the comment block at the beginning of the source code file for detailed information on features and operation. Microcontroller Interfacing AT93CXX Serial EEPROMs with AT89CX051 Microcontrollers Serial memory devices offer significant advantages over parallel devices in applications where lower data transfer rates are acceptable. In addition to requiring less board space, serial devices allow microcontroller I/O pins to be conserved. This is especially valuable when adding external memory to low pin count microcontrollers such as the Atmel AT89C 105 1 and AT89C2051. This appplication note presents a suite of software routines which may be incorporated into a user's application to allow AT89CX051 microcontrollers to read and write AT93CXX serial EEPROMs. All seven AT93CXX device functions are supported: read, write, write all, erase, erase all, erase/write enable and erase/write disable. The routines are general purpose, supporting both eight-bit and sixteen-bit accesses to all members of the 93CXX family. In addition, both three-wire and four-wire configurations are supported. The AT93CXX may be connected to the AT89CX051 microcontroller in either a three-wire (Figure I) or four-wire (Figure 2) configuration. In the three-wire configuration, the EEPROM serial data in (01) and serial data out (DO) pins are both connected to the same microcontroller I/O pin, thereby saving a pin. This is possible because the microcontroller I/O pins can be dynamically reprogrammed as input or output. 8-Bit Microcontroller with Flash Application Note Note the strapping of the AT93CXX ORG pins shown in Figure 1 and Figure 2. The ORG (internal organization) pin selects eight-bit data when grounded and sixteenbit data when floating or tied to Vcc. The ORG pin connections shown in the figures are for illustration only; eight-bit or sixteenbit data may be selected in either the threewire or four-wire configuration. • The software for this application may be obtained by downloading from Atmel's BBS: (408) 436-4309. Consult the comment block at the beginning of the source code file for detailed information on features and operation. Figure 1. Three-Wire Configuration vee .110 uF L-.----!..J AST I--~-----''-i X2 D Xl 11 P3.O/RXD P3.1fTXO +P1.0 -P1.1 P3.2Ji'Nrn P1.2 P1.3 P1.4 P3.3IfNfl P3.4rrO P3.5/T1 P1.5 P3.7 P1.7 P1.6 ,.,. ,. 4 17 18 AT89CX051 0490A 4-41 Figure 2. Typical Circuit Configuration vee ..1 10UF RST 4 X2 0 5 30pF 12 MHz X1 P3.0IRXD P3.1fTXD P3.2/INTO P3.311NT1 P3.4fTO P3.5{T1 11 P3.7 +P1.0 -P1.1 P1.2 P1.3 P1.4 P1.5 P1.S Pl.7 AT89CX051 4-42 Microcontroller vee 1 es J--:;;,.....-----~2, SK 3 ,01 1-7.,.....-------7 4 De 7 ORG ""S,,--_-, DO AT93CXX Microcontroller Product Information General Architecture Microcontroller Data Sheets Microcontroller Application Notes Programmer Support/Development Tools .• ~~~~~~;:"''jiZn~",. Microcontroller Cross-Reference Package Outlines Miscellaneous Information Contents Section 5 Programmer Support/Development Tools Microcontroller Programmer Support ............................................................................... 5-3 Microcontroller Third Party Tool Vendors ......................................................................... 5-9 AT89 Series Development Tools Support ........................................................................ 5-17 ATABX051 ....................................................................................................................... 5-25 II 5-1 5-2 Programmer Support Programming Vendors Atmel Corporation works closely with major suppliers of programming equipment that support our family of Flash microcontrollers. Atmel has a program in place which certifies the programming vendors, and a complete list can be found on our Bulletin Board at (408) 436-4309. This list will be updated frequently to reflect additional support. The following is a list of vendors that currently offer support for the Atmel Flash based microcontroller family. If a vendor of your choice does not appear on this list, please contact Atmel at (408) 436-4295, to enroll them in Atmel' s certification program. M icrocontroller Programmer Support • 0515A 5-3 Programmer ACD I Address Telephone & Fax LartyWood Tel: 206-868-9444 Fax: 206-688-9444 ~~:::o~~rt~"ts~~g~~ St. JihengHa Product Marketing Jeff Chen Business Manager Advantech Tel: 011-868-2-218-4567 Fax: 011-886-2-218-8478 BBS: 011-886-2-218-5434 Programmer Model #'s Software Revision # Product PC-UPROG from Advantech CM3000 trom Logical Dovices Vl.83 V2.2 Vl.0 Vl.0 AT89C51 AT89C52 AT89Cl051 AT89C2051 986Ofrom American Reliance MI680 from Minato OMPRO-II from Dataman Labtool-48 4F No.1 06-3, Ming-Chuan Road ~~:~~:Ti~~w~~ RO.C. Osamu Kasama Advantest I Advin Systems :;k~~~a~~it~~~~~;~~~~n WingHui VP Engineering 1050-L East Duane Avenue Sunnyvale, Califomia 94086 Allen Systems 2346 Brandon Road Columbus Ohio 43221 Tel: 011-81-493-56-4433 Fax: 011-81-493-57-1092 R4945 VorHoo Tel: 408-243-7000 Fax: 408-736-2503 Sales: 800-627-2456 BBS: 408-737-9200 PILOT-U40 PILOT-U84 PILOT-145 PILOT-V32 Tel: 614-488-7122 Ando Yoshihiro Homma 4-19-7 Kamata, Ohta-Ku Tokyo 144, Japan 7617 Standish Place Rockvillo, Maryiand 20655 USA Michael Healey Managing Director Plassoy Technological Park LLmerick Ireland Satom Mikuni 1-1-2 Manpukuji, Asou-ku, Kawasaki Kanaaawa 215 JaDan B&C Microsystems AT89C51 AT89C52 AT89C2051 AT89Cl051 AT89C51 9860 Electronics Aval Corp 10.75 10.8tC PB-51111 American Reliance Ashling Micro Systems Inc. AT89C51 Cesar Hemandez Application Engineer 750 North Pastoria Avenue Tol: 011-81-3-3733-1151 Fax: 011-81-3-3739-7363 AF9705 AF981 0 AF9704 AF9780 USA Tel: 301-294-3365 Fax: 301-294-3359 AT89C51 Tol: 011-44-1489-577516 Fax: 011-353-61334477 EMAIL: ashling@iol.ie CTP51 4.6.3 AT89C51 AT89C52 Tel: 011-81-44-952-1322 Fax: 011-81-44-952-1332 PECKER-50 Tel: 408-730-5511 Fax: 408-730-5521 BBS: 408-730-2317 PROTEUS (single device) 3.7K 3.7P AT89C51 AT89C52 Tel: 713-688-2620 Fax: 713-688-0920 Tel: 800-225-2102 Oliverx520 BBS: 713-688-9283 up to 14.4 KBPS BP-1200l40 EP-1140 BPII48 2.26 3.03 3.05b 3.08 AT89C51 AT89C52 AT89C2051 AT89Cl051 Tel: 407-994-3520 Fax: 407-994-3615 EZWriter AT89C51 SUDowale. CA 94086 BP Microsystems Tracy Wilson Bill Cates Oliver Lazares PuarmaMul1hy Manager of Software Support 1000 N. Post Oak RD., Su~e 225 Houston, Texas 77055-7237 Bytek Joe Martiello 543 North West 77th Street Bocaraton, Florida 33487-1323 I CEIBO Leor Weinstein Victor Waiman Tel: 011-972-9-555-387 Fax: 011-972-9-553-297 Merkazim Bldg, Ind Zone 5 Maksit Herzelia, 46120, Israel Roly Schwartzman 7 Edgostone Ct. Florissant, MO 63033 CEIBOGmbH Menachem Kimron Rheinstr. 32 Tel: 314-830-4089 Fax: 314-630-4083 AT89C51 Multitrk 4000 ~~~:t~ ~ggg MP-51 ET-PIC4ooo ET-PIC 12000 (gang programmer) ET-PIC 5000 ET-PIC 1000 ET-SEPROG ET-PIC 51 2.26 4.14 1.68 AT89C51 AT89C52 AT89C2051 AT89Cl051 3.07 2.1 1.01 Tel: 0049-6151-27505 Fax: 0049-6151-28540 0-64283 Darmstadt Germon Celectronic Klaus Leistner Volker Czmok Tel: 011-030-413-6075 Fax: 011-030-49-913-6098 Nordlichtrasse 63-65 0-13405 Berlin, Germany 5·4 Programmer Support Promlcron 1000 5.61 AT89C51 AT89C52 Programmer Support Programmer Address Telephone & Fax Programmer Model #'s Software Product Revision # Data VOCorp Vac/av Klimsa Keith Miller (Mgr Mfg interface) Mike Durham (Mfg interface) P.O. Box 97946 10525 Willows Rd NE Redmond. Washington 98073-9746 Susan Kuenster Corporate Communications Dataman Programmers, LTD Gary Comer Technical Support Manager Station Road Maiden Newton Technical Assistance 800-247-5700 Service 800-735-6070 Sales 800- 332-8246 Susan: 206-867-6B84 Fax: 206-869-7423 Mfg: 206-867-6841 Mike: 206-867-6841 BBS: 206-882-3211 KeepCurrent:206-881-3465 EMail: Durham@mailgwy.DataIO.COM at CCGATE UNISTE sfte 48 UNISTE pinsite UNISTE46HS 2900 (no 5V support) 3900 UNISITE chipsite Auto site 2500 Chip Lab-48 PSX500 PSXlooo Tel: 011-44-0-1300-320719 Fax: 011-44-0-1300-321012 BBS: 011-4-4-0-1300-321095 Modem:V.34N.FCN.32bis 54 S4 MCS-51 (module) Tel: 709-832-8818 Fax: 708-653-9087 PROMA-3 Tel: 011-44-489-579-799 Fax: 011-44-189-577-518 Tel: 408-734-8184 Fax: 406-734-8185 4.3 4.7 AT89C51 AT89C52 3.4 2.4 3.0 3.3 3.3 4.9 4.9 1.20 1.21 AT89C51 AT89C52 AT89C2051 AT89Cl051 AT89C51 AT89C52 6oo0APS K2.07 AT89C51 ALLMAX ALLMAXPLUS PROMAX 1.6 2.0 2.1 AT89C51 AT89C52 AT89C2051 Tel: 801-488-2825 Fax: 801-484-9285 XOSI Programmer 1.0 AT89C2051 AT89Cl051 Tel: 011-0221-7602252 Fax: 011-0221-766923 PROM8952 3.0 3.0 AT89C2051 AT89Cl051 Tel: 408-982-0660 x118 Fax: 408-982-0664 BBS: 408-982-9044 ET-PIC 12000 ET-PIC 10000 ET-PIC4000 8.69 2.3 3.0 AT89C51 AT89C52 AT89C2051 AT89Cl051 ~~~~e~1~~d~~rset. DT2 OAE Datatech Int. Inc. DanHo ON319 Stanley St. Winfield. IL 60190 P.O. Box 549 Villa Park IL 60181 Julian Hartridge Elan Digital Systems Limited Device Support Engineer Little Park Farm Rd. Segensworth West Fareham Hants PolS 5SJ UK Electronic John Kim Engineering Tools 544 Weddell Dr.. Ste. 6 Sunnyvale. CA 94089 gsh Systemtechnik Postiach 600511 181025 Munchen Electronix Corp. Jason Clinger 900 South 300 West Salt Lake Citv. Utah 84115 EHA- Elekronlk Walter Hack/ander ~~~~S~:~17 Emulation Don Krenn Technology 2344 Walsh Ave .. Bldg F Santa Clara. CA 95051 Tel: 089-8343047 Fax: 089-8340446 ~~:!~~~~S~~~~~ to DIP Ertec Hr. Nickel Am Pestalozzining 24 Tel: 011-49-9131-77000 Fax: 011-49-9131-110010 91058 Ertanoen GTEK.lnc. Cal Edmonds RAM# 1916 399 Highway 90 Bay St: Louis. MS 39520 Hi-La System Grason Kirk Research Co., 4F. No.2. Sec. 5 .. Ming-Shen E. Rd. Tai ei Taiwan ROC LTD Hi Tools Inc. U/af Pfeiffer 2055 Gateway Place. Suite 400 lian,Jose.l;A 951 10,' ICE Technology Sheila Boakes Managing Director - Commercial John Lamb Technical Support AT89C51 Tel: 601-467-8048 Fax: 601-467-0935 Tel: 011-886-2-764021 5fi633931 Fax: 011-886-2-756640317601559 Internet: 101400.1555@ ALL03A 3.30 ALL07+ PAC-DIP 40 3.33 comnutserve.com AT89C51 AT89C52 AT89C2051 AT89Cl051 Tel: 408-481-9486 Fax: 408-441-9486 Tel: 011-44-01226-767404 Fax: 011-44-01226-3704.34 BBS: 011-44-01226-761181 Micromaster 1000/1 OOOE Tel: 408-942-1001 Fax: 408-942-1051 Tel: 011-49-08131-25083 Fax: 011-49-08131-14024 BBS: 011-49-8131-1687 Email: 100632.42@ 3.07 3.07 AT89C51 AT89C52 AT89Cl051 AT89C2051 Eprom 1 (single device) M4016 (gang programmer) 2.64 2.74 AT89C51 AT89C52 iUP8000 SEPROG 2.5 5.44 AT89C51 AT89C52 AT89Cl051 AT89C2051 Micromaster l V Unit 4, Penistone Court Station Buildings Penistone. S. Yorks ,ire 530 6HG UK International Microsystems Inc, iSYSTEMS The Tool Company Mason Tom Peter A. Schadel President 521 Valley Way LMilDitas. Califomi 95035 Hr. Gerd Punsmann Einsteinstrasse 5 85221 Dachau Gennany compuserve.com AlmEl 5-5 • Programmer Address Talaphone & Fax Programmer Modal Leap Electronic Co. 6F, No 4, Lane 609, Sec. 5 Chung Hsin Rd. San Chung City Tel: 011-02-999-1860 Fax: 011-02-999-0015 "s Softwara Ravislon. Product Leap-Ul Leaper-5 3.12 1.20 AT89C52 AT89C51 Tel: 201-808-8990 Fax: 201-808-8786 CLK-31oo (wi 875X adapter) Tel: 600-331-7766 Tel: 305-428-6868 Fax: 305-428-1811 BBS: 305-428-8014 ALLPRO-88 ALLPRO-881XR ALLPRO-40 GANGPRO-8 GANGPRO-SII CM3000 Chipmaster 2000 4.55 4.95 4.99 4.98 ver2.4 AT89C51 AT89C52 AT69Cl051 AT89C2051 AT89C51 AT69C52 AT89C2051 AT89Cl051 ;~e~:~~:2!~~~~e7'O'C' Link Instruments Bill Lam Sales Manager 369 Passaic Ave., Suite 100 Fainield N.J. 07004 Logical Devices David Mot 264 South West 12th Ave. Deeriield Beach, Florida 33442 Bill HalV Software Engineer Jeff Williams eonor Mcaleer 130 Capital Drive, Su"e A Golden, Colorado 80401 Logicai Systems Lynn Burl 430 FLEX-700 UNIVERSAL TUP-400 UNIVERSAL 4 GANG MODULE TUP-51F (PDlP) TUP-51F-PL (PLCC) 3.29 PGM51.EXE 3.33 AT89C51 4.22 3.35 AT89C2051 AT89Cl051 SUPERPROII 2.1 2.01 2.2 2.2A AT89C51 AT89C52 AT89C2051 AT89Cl 051 AT89C52 Tel: 305-570-558880 Fax: 305-428-1811 ~~~~i~~hB~~~ryF~~~a 33442 Xeltek Joo Nam Kim 2563 Ryder St. Santa Clara, CA 95051 Tel: 408-524-1929 Fax: 408-245-7084 BBS: 409-245-7082 5-7 II 5·8 Programmer Support Tool Vendors Third Party Tool Vendors Atmel Corporation works closely with many "third-party" vendors who provide support tools for our wide variety of 80C51 based microcontroller derivatives. The following is a non-inclusive list of some of the vendors that offer support for the Atmel AT89C series microcontroller family. Any system that supports an 80C51-based microcontroller will be compatible with the Atmel AT89C series of microcontrollers. Microcontroller Third Party Tool Vendors • 0514A 5-9 AlmEL Table 1. Third Party Tool Vendors I C~ntact ~ Nllme. I Address Phone/Fax Product Name ~&~~ . . . . . . u" oj,. ALLEN SYSTEMS John Allen Tel: 612-488-7122 2346 Brandon Road Columbus, OH 43221 AMERICAN ARIUM Jeff Acampora; Tel: 714-731-1661 14281 Chambers Road, Tustin, CA 92680 Tel: 011-49-806190940 BBS: 011-49'8061377190 Fax: 011-49-806137298 Westend Strasse - 4 83043 Bad Aibling, Germany Tel: 011-353-61-33-4466 Fax: 011-353-61-334477 Email: ashling@iol.ie Tel: 011-49-082021276 Fax: 011-49-082028745 Plassey Technological Park, Limerick, Ireland :ti~~es& APPLIWARE ELEKRONIK GmbH Hr. Heinrich Bals ASHLING MICROSYSTEMS, LTD Michael Healy BRENDES DATENTECHNIK Hr. Dr. Brendes BVG ELECTRONIC Hr. Montanus Tel: 49-531-506499 Fax: 49-531-506499 Tel: 49-8106-5794 Fax: 49-8106-33921 Little Byte-Sl/ PB-51/11 A1CE51 80S1-based Single board compU1er ,,~, "'.~,~ Debugger/ C-Ccmpiler/ Programmer Development Kits/Eval BoardsIModules Emulator/Software Waldstrbe 18 86510 Baindlkirch, Germany Lebacher Strasse 122 Emulator I ~~~~~;aunSChWWeig, 'D. I 85598 <'. Baldh~;;;:Germany CACTUS LOGIC Joel Lagerquist Tel: 800-847-1998 ) North Venedo Ave., Pasedena. CA 911 07 CIEBO Hr. Kimron Tel: 49-6151-27505 Fax: 49-6151-28540 Rhein 64283 Darmstadt, Germany Emulator/Software I Tel: 61' CEIBOITD CMXCompany Mark Moran Tel: 508-872-7675 Fax: 508-620-6828 I Tel: DEEMAX ," ~, 11 5 Grant SI. Ste. C Framingham, MA 01701 STIMGATE Soft Emulator-new productivity tool for embedded processors I Taiwan DR. KROHN & STILLER Mr. Maihoefner Dr. Krohn Tel: 49-89-61-00-0012 Ottobrunner Strasse 28, Tel: 49-89-61-00-0011 D-82008 Unterhaching, Fax: 49-89-61-00-0099 IGermany E8 Emulator/Software EMBEDDED SYSTEM PRODUCTS, INC Ron Hodge Rhonda Warzecha Tel: 713-728-9688 Tel: 800-525-4302 Fax: 713-728-1049 Email: Sales@esphou.com RTXC RTXCio RTXCfile RTXCnet Multitasking O.S. Input/Output Subsystem DOS compatible file system Real-time Networking 11501 Chimney Rock, Houston, TX 77035-2900 ~r~~C:~ TCP/IP Don Krenn EMULATION TECHNOLOGY INC. Tel: 800-995-4381 Fax: 408-982-0664 ENGELMANN & SCHRADER Tel: 49-05148-286 Fax: 49-05148-853 HI-LO S!~TE_~S I CO., LTD Tel: 886-2-7640215 5-10 Tool Vendors 2344 Walsh Ave. Bldg. F Santa Clara, CA 95051 I ~:51 'Eid'i;;'g~;;:~G;'many Taiwan Emulator/Software Emulator/Software ~evice Tool Vendors Table 1. Third Party Tool Vendors (continued) Phone/Fax Address HITEX Mr. Otterstaetter SYSTEMENTWICKLUNG Hr. Christoph GmbH Company Contact Name Tel: 49-721-9628-181 Fax: 49-721-9628140 Greschbach Strasse 12, D-76229 Karlsruhe, Germany Emulator HUNTSVILLE MICROSYSTEMS, INC Jim Bell Tel: 205-881-6005 Fax: 205-882-6701 3322 South Memorial Parkway, Bldg. 500, Huntsville, AL 35801 Emulator/Software iSYSTEMS Hr. Punsmann Tel: 49-08131-25083 Fax: 49-08131-14024 Einstein Strasse 5, 85221 Dachau Emulator/Software IWASAKI ELECTRONICS CO, LTD Tel: 81-3-863-3025 Japan KONTRON Tel: 49-08165-77444 Fax: 49-08165-77128 Oskar-von-Miller-Strasse 85386 Eching, Germany LAUTERBACH DATENTECHNIK Tel: 49-08104-889430 Fax: 49-08104-894349 Fichten Strasse 27 85649 Hofolding, Germany Emulator LINDNER ELECTRONICS, INC Tel: 603-523-9005 PO Box 68, Canaan, NH 03741 Programmer for the AT89C51 MANDENO GRANVILLE Jim Granville Tel: 64-9-6300-558 128 Grange Rd, Mt. Eden 3, Aukland, New Zealand METALINK CORP Jack Blankenship Tel: 602-926-0797 325 East Elliot Rd., Suite 23, Chandler, AZ 85225 Tel: 49-8091-2046 Fax: 49-8091-2386 Westring2 85614 Kirchseeon, Germany Tel: 886-2-88-11791 Taiwan MICROTEK INTERNATIONAL Kevin Jagla Tel: 503-645-7333 x449 3300 NorthWest 2, 11th Terrace, Hillburough, OR 97124 MIDTECH COMPUTING DEVICES John Dybowski Tel: 203-684-2442 Fax: 203-684-2443 45 Monson Road Stafford Springs, CT NOHAUCORP Bill Matsumoto Tel: 408-866-1820 51 East Campbell Ave., Suite 144, Campbell, CA 95008 MICRO TIME NOHAU DANMARK Tel: 43-44-60-10 Fax: 43-44-60-20 NOHAU ELEKRONIK GmbH GERMANY Tel: 49-7043-40247 Fax: 49-7043-40521 NOHAU UK LTD Tel: 0962-733-140 Fax: 0962-735-408 NOHAU ELEKTRONIK SWEDEN Tel: 040-92-24-25 Fax: 040-96-81-61 ORION INSTRUMENTS RAINSONNANCE RHOMBUS Product Name ICEP2051 Description Development station for the AT89C2051 Emulator 2051 Design Center AT89C2051 development system Emulator Goethe Strasse 4 75433 Maulbronn Ken Schoggins: Tel: 415-327-8800 Fax: 415-327-9881 180 Independent Drive, Menlo Park, CA 94025 c/o Macrotom Tel: 011-49-89-42080 Stahlgruberring 2 81804 Munchen, Germany Roth Tel: 011-49-81441536 Fax: 011-49-81441535 Wald Strasse 16 82284 Grafrath, Germany Tel: 803-676-0012 Fax: 803-676-0015 P.O. Box 871 Mauldin, SC 29662 AIIDEL Emulator Emulator/Software 2051-PD AT89C2051 Development System 5-11 • AIIDEL Table 1. Third Party Tool Vendors (continued) Company Contact Name Phone/Fax Address Product Name Description SIGNUM SYSTEMS Jerry Lewandowski Tel: 805-371-4608 Fax: 805-371-4610 171 East Thousand Oaks Blvd., Suite #202, Thousand Oaks, CA 91360 USP-51 Emulator Base Unit, 20 Mhz, 128K memory, 32K '80 Trace Buffer Donald Mull Tel: 510-353-1616 Fax: 510-353-1618 200 Brown Rd. #28 Fremont, CA 94539 Bonacker Tel: 49-7244-94012 Fax: 49-7244-92128 POD-51 Probe for 8XC51/52, 80C31/32, AT89C51 David Freemire Tel: 415-493-6700 Fax: 415-493-4648 777 Califomia Ave., Palo Alto, CA 94304 Mr. Kohno Tel: 813-33487001 Fax: 813-3348-2446 NS Bldg., 2-4-1, Nishi-Shinjuku, Tokyo, Japan IP2813R Emulator Hr. Santen Tel: 49-721-377044 Fax: 49-721-377241 Postfach 2928 76016 Karlsruhe, Germany Tel: 886-2-7660206 Taiwan C/O Innotron Tel: 49-20240526 Fax: 49-20240522 Nesselberg Strasse 1 42349 Wuppertal, Germany U. S. SOFTWARE Don Dunstan Tel: 503-641-8446 Tel: 800-356-7097 Fax: 503-644-2413 4215 Northern West Science Park Drive Portland, OR 97229 TRANSFERTECH Hr. Pogrzeba Tel: 49-531-890255 Fax: 49-531-890355 Cynaksring 9a 38118 Braunschweig, Germany FCM-8051 Emulator Fuzzy-SW UNILAB Buddy Baker Tel: 514-630-4600 Fax: 514-630-4680 235 Place Frantenac Pointe-Claire, PO, Canada H9R4Z7 UNILAB 8051 Development System VAIL SILICON TOOLS Product Marketing: Gabby Green Tel: 305-570-5580 Fax: 305-428-1811 692 South Military Trail, Deerfield Beach, FL 33442 WHYMON Hr. Brugger Tel: 49-0041-41852212 Fax: 49-0041-4185238 CH-5734 Reinach, Germany SOPHIA SYSTEMS AND TECHNOLOGY/ Sales Dept SUNSHINE ~' HEWLETT- PACKARD TEKTRONIX, INC 5-12 .. ; ... Rohrackerweg 11 76297 Stutensee, Germany .. John Marshall PME Tel: 800-447-3282 Tel: 719-590-5985 Fax: 719-590-5054 1900 Garden of the Gods Road, CSO CO 80901; PO Box 2197, CSO CO 80901-2197 Hr. Walkamm Tel: 49-07031-146513 Fax: 49-07031-146429 Schickard Strasse 2 71004 Boblingen, Germany Chuck Small Product Marketing Engineer Tel: 719-590-2006 Fax: 719-590-5054 1900 Garden olthe Gods Road, CSO CO 80901; PO Box 2197, CSO CO 80901-2197 Steve Hass; Technical Support Center Tel: 800-426-2200 Fax: 503-690-3959 18700 Northwest Walker Rd., Bldg. 94 Dock, Aloha, OR 97006 Tool Vendors Emulator/Software Emulator Emulator/Software .. , ,. .f' ~:'" HP1660 Family HPI6500 HPE24158 HP647886 Emulator/Software Logic Analyzer Frame for 8051 Logic Analyzer Family80C51 Preprocessor Tool Vendors Table 1. Third Party Tool Vendors (continued) Company Contact Name 'IV " " ~ Phone/Fax "';f;i0";:-!O: lr~;;,;'I' ~:,,' ';',,' Address ,,'1i;,~ Product Name Description !ijji:',';; ,:~r.,;,:~~"!¥;:\";;:;':0';;','''''':;,,;\ ,;~;;i;;i;:'::;:;;,<:;;}:",) ;"; : 2500 A.D. SOFTWARE Vicky Beske Tel: 800-843-8144 Fax: 719-395-8206 Tel: 719-395-8683 109 Brookdale Ave., Buena Vista, CO 81211 8051C Compiler CCompiler Includes: macro cross assembler, linker, librarian, high level simulator/ debugger and object libraries APPLIWARE Hr. Heinrich Bals Tel: 011-49-806190940 BBS: 011-49-8061377190 Fax: 011-49-806137298 Westend Strasse - 4 83043 Bad Aibling, Germany WORKS-51 WORKS PLUS-51 Integrated Devlopment Environment (IDE), HLL Debugger, CCompiler, Macro assembler, Simulator complete development packs ARCHIMEDES SOFTWARE Timothy Hang Tel: 800-338-1453 Tel: 206-822-6300 Fax: 206-822-8632 303 Park Place Center SuiteG Kirkland, WA 98033 C-8051PC 5.0 C-Cross Compiler kit for the MCS-51 family Sim8051 PC 5.0 Simulator/debugger for the MCS-51 family AvCase II 8051 Development pkg includes: C compiler Macro assembler, source level simulator, remote monitor debugger AvocetC CCompiler/ assembler AVA51 Macro Assembler AVS51 C Source level simulator AVSIM51 Assembly level simulator AVOCET SYSTEMS, INC Tony Taylor BSOITASKING Shailui Gargeya Tel: 800-448-8500 Tel: 207-236-9055 Fax: 207-236-6713 P.O. Box 490 120 Union St., Rockport, MA 04856 Tel: 800-458-8276 128 Technology Center P.O. Box 9184 Waltham, MA 02254-9164 CCompiler Tel: 617-320-9400 Norfolk Place, 333 Elm St., Dedham, MA 02026-4530 Software Tel: 49-7152-979910 Fax: 49-7152-9799120 Steinbeis Strasse 4 71229 Leonberg, Germany BINAR TECHNOLOGY Bob Oleksiak Tel: 508-369-9556 Fax: 508-369-9549 463 Autumm Lane, Carlisle, MA01741; PO Box 541, Carlisle, MA 01741 BYTE-BOSINTEGRATED SYSTEMS Craig Rand Tel: 800-788-7288 Fax: 714-851-2267 451 Zuni Drive, Delmar, CA 92014 • Multitasking O.S. 5-13 Table 1. Third Party Tool Vendors (continued) Company Contact Name Phone/Fax Address Product Name Description CHIP TOOLS, INC Ken Anderson Tel: 905-274-6244 Fax: 905-891-2715 1232 Stavebank Rd., Mississauga, Ontario, Canada, L5G2V2 ChipView-SI Simulator/ ROM Debugger CIMETRICS TECHNOLOGY ConrayWharff Tel: 617-350-7550 Fax: 617-350-7552 55 Temple Place Boston, MA 02111-1300 9-Bit Solution Network RS-485 ToolslHW/SW CMXCOMPANY Charles Behrmann President Tel: 508-872-7675 Fax: 508-620-6828 5 Grant SI. Ste C Framingham, MA 01701 CMX-RTX CMX-TINY+ CMX-TINY RealTime Multitasking O.S. Tel: 818-244-4600 Fax: 818-244-4246 3447 Ocean View Blvd., Glendale, CA 91208 DRUMLIN Software Functional Libraries DUNFIELD DEVELOPMENT SYSTEMS Dave Dunfield Tel: 613-256-5820 Fax: 613-256-5821 BBS: 613-256-6289 P.O. Bcx 31044 Nepan, OntariO, Canada K2B 8S8 EMULATION TECHNOLOGY Robert Diaz Tel: 408-982-0660 Fax: 408- 982-0664 2344 Walsh Ave, Bldg. F, Santa Clara, CA 95051 Adapters EMBEDDED SYSTEM PRODUCT Ron Hodge Tel: 713-728-9688 Fax: 713-728-1049 11501 Chimney Rock, Houston, TX 77035-2900 R.T. Kemal! Operating System EDI Milos Kregoheck Tel: 702-735-4997 Fax: 702-735-8339 FORTH, INC Steve Agarwal Tel: 800-55-FORTH Fax: 310-318-7130 111 North Sepulveda Blvd., Manhattan Beach, CA90266 Chip Forth Compiler/ Multi-Tasking Kemel FRANKLIN SOFTWARE, INC. Rhett D. Rowan General Manager Tel: 408-296-8051 Fax: 408-296-8061 BBS: 408-296-8060 24HR Info: 408-2968056 Sales: 800-880-8051 CompuServe: 75442,1423 Internet: fsinfo@fsinc.com 888 Saratoga Ave., Suite #2, San Jose, CA 95129 ASI Macro assembler, complete kit with editor, linker, librarian, and include files. C compiler kit Developers kit Professional Developers kit Real Time Executive Nadin Sahehayed Tel: 415-765-5500 Fax: 415-765-5503 One Maritime Plaza San FranciSCO, CA 94111 ICC8051 IAR C-Cross Compiler Michael Ohman Tel: 011-4618-167800 Fax: 011-4618-167838 P.O. Box 23051 S-750 23 Uppsala, Sweden C58051 C-SPY Simulater/Debugger Windows based CCompiler for 8051 IARSYSTEMS EMILY52 Simulator/Emulator CCompiler Socket Adaptor C51 DK51 PK51 RTX-51 Embedded work bench INFORM SOFTWARE CORP Woongkee Min Tel: 708-866-1838 Fax: 708-866-1839 1840 Oak Ave., Evenston, IL 60201 INTERMETRICS MICROSYSTEMS SOFTWARE Marty Stolz Technical Support Scott Tatiel Marketing V.P. Tel: 617·661-0072 Fax: 617-868-2843 Fax: 617-868-2518 733 Concord Ave., Cambridge, MA 02138 IOTA SYSTEMS Steve Motts Tel: 702-831-6302 Fax: 702-831-4629 924 Incline Way, Suite N, Incline Villiage, NV 89450 ITIPOMONA Bob Poirier Tel: 909-469-2912 Fax: 909-629-3317 1500 East 9th Street, Pomona, CA 91766-3835 Adapters KEIL ELEKTRONIK Tel: 49-89-465057 Fax: 49-89-468162 Bretonischeer Ring 15 85630 Grasbrunn, Germany Software KEIL SOFTWARE Tel: 214-735-8052 Fax: 214-735-8055 16990 Dallas Parkway Suite 120 Dallas, TX 75248 KYLE SYNOPSIS LOGIC MODELING 5-14 Technical Support Tel: 800-445-1888 Fax: 503- 690- 6906 Tool Vendors FuzzySIW Development White Smiths Compiler/Assembler/L inkerlProgrammer Utilities Germany CCompiler 19500 Northwest Gibbs Dr., Beaverton, OR 97006 Device Simulation Model for 8051 Tool Vendors Table 1. Third Party Tool Vendors (continued) Company Contact Name Phone/Fax Address MOL Labs( NEW MICROS, INC); interpreter requires 3rdtimer Ray Lavender Tel: 614-431-2675 Fax: 614-431-2675 1073 Limberlost Ct, Colombus, OH 43235 MICRO VIEW Andrew Tel: 408-356-4221 NEW MICROS Joe Getz Tel: 214-339-2204 Fax: 214-339-1585 1601 Chalk Hill Rd., Dallas, TX 75212 PRODUCTION LANGUAGES CORP (PLC) JD Hancock Joshua Kuanfung Tel: 817-599-8363 Tel: 800-525-6289 Fax: 817-599-5098 Internet: plcorp@aol.com P.O. Box 109 200 Cochran Rd., Weatherford, TX 76086 QUANTASM CORP Mike Schmit Tel: 800-765-8086 Fax: 408-2447268 19672 Stevens Creek Blvd., Suite 397, Cupertino, CA 95014 REICHMANN MICROC OMPUTER Hr. Reichmann Tel: 49-7141-71042 Fax: 49-7141-75312 Planck Strasse 3 71691 Freiberg, Germany 3M Bob Soshay Tel: 800-225-5373 Fax: 1-800- 325-5329 6801 River Place Blvd., Austin, TX 78726-9000 Electronic Products U.S. SOFTWARE Don Dunstan Tel: 800-356-7097 Tel: 503-641-8446 Fax: 503-644-2413 4215 Northerwest Science Park Drive, Portland, OR 97229 Product Name Description SIW Debugger/ Code Analyzer Evaluation Board COMPASS/51 Assembly Language Flowcharter HTC-51 Peter Aske Voice: 506-849-8952 Fax: 506-847-0681 9 Westminster Drive, Quispamsls, NB Canada E2E 2V4 WICKENHAUSER Jurgen Wickenhauser Tel: 49-721-98849-0 Fax: 49-721-886807 Rastatter Strasse 144 76199 Karlsruhe, Germany ANSI-C Development package: C compiler, Macro Assembler, Remote Monitor Debugger, Library Source, Tools Sockets SuperTask Real-time OS and associated tools USNET Real-time networking including TCP/IP protocols USFiles UNIVERSAL CROSS ASSEMBLERS Macro Assembler/Linker/Obj ecVLibrarianlANSI Ccompiler, Source Level Debugger/Simulator, ROM moniter, IDE Online Documentation, Programmer's Editer. DOS compatibile file system GOFAST Single and double precision floating point library Cross-32 Meta-Assembler DOS or Windows assembler Software 5-.15 • 5~16 Tool Vendors ________________ Tools Support 8051 Family In-Circuit Emulator The EMUL51™_PC is a high perfonnance in-circuit emulator specifically designed to provide an optimal environment for 8051 family microcontroller hardware an¥Joftware development. The EMUL51 -PC consists of a board which plugs directly into the IBM PCIXT/AT bus. An optional Trace board features advanced trace functioning with sophisticated trigger capabilities. The POD, which plugs into the target system, is connected to the emulator board with a 5 ft. ribbon cable for operating range flexibility. Optionally, an RS-232 box can be used which communicates with the PC at up to 115K baud. Yet another ~tion, the LanICE, allows the EMUL51 -PC t run on workstations such as SUN or HP. The World's Most Popular 8051 Emulator The emulator was designed to be plugged into a full size PC/AT style slot. The optional trace needs a second slot. These same boards can also be supplied in an "RS-232 box" which communicates with the PC over a standard COM port. To use the EMUL51™_pc on XWindows workstations such as SUN or HP, the Nohau LanICE is availagble. Because LanICE uses a high speed (10 Mbitlsecond) local area network, not only can it be placed far away from the workstation but it maintains the relatively high code loading speed of the Nohau emulators plugged into your PC on your desk top. LanICE also supports personal computers on a network. AT89 Series Development Tools Support Real Time Trace Since its introduction 1986, Nohau has delivered over 10,000 EMUL51TM_PC emulators. Each emulator is often used in several projects where different 8051 derivatives are needed. Only a change of the probe is required when a new derivative needs emulation support. Choice of Different User Interfaces Hosted on PCs and Workstations TM Early in the evolution of the EMUL51 PC's user interface, it became clear that each customer has different opinions of how they would like the interface to work and what features were important to them. One of the three main user interface choices for the EMUL51™_PC is Microsoft Windows 3.x. The other two are ChipView's Borland keypress compatible and Nohau's original pull-down/command line version. The EMUL51™-PC offers trace features not found in other emulators. The trace buffer can record up to 256K bus cycles with 64 bits of data. The trace can be operated "on-the-fly" which means that it can be viewed, programmed and retriggered without disturbing program execution. With the trace setup menu you can define what events are to be stored in the trace buffer. The real-time trace can be stopped (triggered) at a selected event or after a combination of multiple events. For additional infonnation please contact: Nohau Corporation 51 E. Campbell Avenue Campbell, CA 95008 TEL: 408-866-1820 FAX: 408-378-7869 0516A 5-17 Figure 1. BMULSI 2051 Design Center Mid-Tech's AT89C20S1 Design Center includes everything you need to take your design from simulation, through target degugging, to standalone operation. Specifically designed to support Atrnel's 20-pin processor family, the 2051 Design Center delivers features and capabilities normally found only in much more expensive development systems. Figure 2. A T89C20S1 Design Center Target Debugger Board with Build-in Flash Programmer AT89C2051 Family Simulator, Target System Debugger, and Assembler Operating under control of a "windowed" PC control program, a high speed serial link provides nearly instantaneous communication to the target system. The result is a friendly, truly interactive, development environment. A ZIP programming site and resident flash algorithms provide full programming support for the AT89ClOS1 and AT89C20SI. The simulator runs stand-alone on a PC and also lets you include the target's physical 110 lines, timers, serial port, etc. in your simulation. The target system debugger gives you complete control over the system under develoopment and features a user interface identical to that of the simulator. 5-18 Tools Support Tools Support Features Include: • Single-step, multi-step, animate, and high-speed execution modes. • Simultaneous on-screen displays of program disassembly, data memory, and CPU registers. • Full screen editors for CPU registers, special function registers, data and program memories. • Multiple breakpoints are transparent to the user program. • Serial I/O may be displayed in a window on the PC or can be redirected to the target system. • Prototyping Board and AT89C2051 Included • The 2051 Design Center includes an AT89C2051 prototyping board with built-in power supply and large pad-per-hole prototyping area, AT89C2051 processor included. • Priced at $299.95 for the full-up system. For additional information please contact: Mid-Tech Computing Devices P.O. Box 218 Stafford, CT 06075 TEL: 203-684-2442 IceP2051 Emulator/ReProgrammer The IceP2051 Emulator I ReProgrammer is a complete development station for the Atrnel Flash AT89C1051 and AT89C2051 microcontrollers. It is a full speed, RAM based ICE, intended for full product developments. Unlike other systems, IceP2051 does not rely on PC Simulation, nor require you to erase/program a chip with each iteration. The Edit Assemble Debug loop takes just a few seconds. When your code is tested/optimised, the programmer can be used for your volume production. If you are using the older OTP technology, or a single sourced uC core, there are cross migration tools to assist porting your code. Figure 3. IceP2051 Emulator I ReProgrammer The DbgX51 debugger has a multi, scalable window display, and fast 'text editor' style operation. To change any location, just place the cursor, and edit. Multiple breakpoints, and Step, Skip, GotoHere debug commands are supported. This example shows DbgX51 I IceP025 I running the optional Modula-2 compiler - code illustrated is the multi i2c library. Dbg2051.ZIP - Demo ofIceP2051 Debugger. Env2051.ZIP - Demo of IceP2051 environment. IceP205I.ZIP - Both of the above, full system demo. 5-19 Figure 4. Modula-2 compiler - code File Asaemble Edit View Bre.k/run Optlona 110 = = = = = = Programcode = = = = = = = = = = = = = = = = j l (* user centrals R/W with LSB 01 Add.... (*SetAdd.... ·) (* write Dala to I2c RAM .) (0039) IF StartJ2c(P8583_Wr) THEN (003F) SendJ2c(40H); (0043) SendJ2c(lO_Value); (0047) INC(IO_Volue); (0049) SendJ2c(lO_Valua); (-) END; (004D) StopJ2c; (* WIlle to naxl RAM Iocallon, Autol DbgX51 v4.86b (c) 1994 Mandeno Granville Elec!ronlcs Reglalars ==========:!J dl.....Mbly PC 0000 CAORROl P PSW CO 11000000 SP 26 r8:2680 A '.'00 00000000 00 00000000 B DP 0000:01 24 FF 0039 7A AO OO3B31OA 003D500E OO3F7A40 004111 B8 OO43AA22 MOV ACALL JNC MOV ACALL MOV Ini. dala R2,#AO 010A 004D R2,#40 OOB8 R2,22 08: OC: 12: 18: lE: 24: 09 8F 14 00 FF 9F 00 00 5D 00 9F F8 7F SE 7F FF CF 5F EO IF 7F F8 DF 7E 9F F8 2F 4F 00 6F SE 80 28 3A 83 00 Sfr89C20S1 90 BO 88 89 Pl P3 TCON TMOD FF FF 00 00 11111111 b "111111 b 00000000 b 00000000 CHKl2C Cleared Buller Pl.7 Pl.6 TFl GATEl TRl C/T1 Pl.5 Pl.4 TO TFO T1 Ml TRO MO -> OFFH,. Downloaded HEX Pl.3 INTl IEl IT1 GATEO Pl.z INTO Pl.l 1XD lEO ITO C/TO Ml Pl.0 RXD MO READY IceP2051 • Full ICE + ReProgrammer for the Atmel Flash 20-Pin variants ( 40.44 With adaptor) • Source level Debug, and Mixed language Source debug, allowing .ASM.,C, Modula-2 source codes to be mixed • Real Time, RAM based, Emulation (including the Analog Comparitor ) • Chip Prog step is NOT part of the development loop • Full screen Debug, 'Borland' style interface, Multi Windowed, direct editing • Full SFR symbolic BYTE.BIT display, for rapid learning Timer Uart Interrupt debug • Complete package - Assembler / Linker / Debugger / Editor included • Optional adaptors for SOL20, and DIP40IPLCC44 • Special cross platform migration support included and added to Assembler Programmer Features • FAST RAM based production programmer - 1.2Sec I KByte, , (Erase.Vfy.Secure included!) • Single Key, Erase Program Verify Secure of AT89C1051 , AT89C2051, AT89C51, AT89C52 Atmel Flash microcontrollers • Chips programmed counter • Mis-socket and incorrect part detection • Mechanically supported SOL adaptor • Smart program algorithm, for fastest possible pgm cycle times 5-20 Tools Support For additional information please contact: Mandeno GranvilJe Electronics Ltd: 80x51 Tools Specialists. 128 Grange Rd Auckland 3 New Zealand TEL: 64-9 -6300-558 FAX: 64-9-6301-720 Tools Support 2051-PD Programmer Downloader & I/O Simulator Features • Fast, Simple, Download & Run - No Change In Characteristics - No Loss of Features The 2051-PD offers the simplicity and speed you need for developing small programs. From the simple Command Line to seeing the results of an Intel hex file running on the Target typically takes less than 6 secs. And that includes checksum verification. In addition, the 2051-PD follows two ideals needed for a smooth transition to stand-alone operation: • It preserves the true characteristics and special features of the 89C2051 microcontroller • It allows the code to run in the same memory locations as needed for the stand-alone Target system. It is PC hosted through a RS232 port, and in turn it runs the Target board through its microcontroller socket. By taking advantage of the 2051' s flash memory and ease of re-programming, this arrangement offers the speed and convenience of a ROM Emulator even though working with an internal memory device. In addition, once the download is complete, a Command Line Option allows the same PC port to be automatically switched to the Target for its own use. This is especially useful if the Target board does not require an RS232 interface yet one is desired to assist in the actual development, or production testing. Another valuable use for this existing connection to the PC, is with the optional 'Dunfield Developments' Simulator Package. This fast PC Simulator (150,000 instr/sec with 386125) can optionally pass all I/O related instructions to the Target's 2051 for execution. This allows running the application code in a crashproof PC environment, with all register and memory data readily available, yet still seeing the interaction with the actual Target HIW. The Dunfield S/W package also includes an Assembler, and a Monitor Debugger intended for larger memory versions of the 51. The Simulator on its own is sufficient reason for purchasing this option. The 2051-PD comes complete with its own S/W for programming and downloading a 6 ft. 9 pin PC serial cable, a 9-25 pin adapter, Target flat cable, and power supply for shipments to the U.S. and Canada. Figure 5. 2051-PD AlmEL 5-21 • Terminology definitions for the 2051-PD: Technical Programmer: The programming and verifying of the internal Flash memory and the setting of lock bits • Measures 4" x 3" Downloader: The loading and running of code at full speed on an identical uC connected through the Target socket 110 Simulator: As for the Downloader, but with the code restricted to those instructions that operate on the uC port pins. All other instructions are simulated by the PC. The I/O code will always execute at less than full speed. Requires the optional Dunfield Simulator Package • Accepts 13-20VDC or lO-lSVAC • 3 pin oscillator socket for Xtals or ClResonators • RS232 includes RTS (from PC) & CTS (to PC) • Green Status LED signals PowerUp, Run, Program • Red LEDs indicate To/From PC • CmdlLine options LB1I2, COM#, ConnPt, Vrfy, ChkS, Color Proto/Evaluation Boards for the 2051 " h"mg Feat ures 2051 0"ISfmguis Evaluate Using Relative to other 51s P1 Analog Comparator P2 X 20mA sink capability X X X X X X Relative to other <=20 Pin uCs , On board UART Multiplication & Division Both the 20S1-Pl & P2 demonstrate a 1 capacitor 3 resistor AID convertor using the analog comparator built into the AT89C20Sl. Also included are a RS-232 interface, a prototype area with screw terminals, and a precision 3 terminal voltage regulator. Additionally, the 20S1-P2 demonstrates the 20rnA sink capability of the A T89C20S1 with a high intensity 4 digit display using only 6 I/O pins and consuming only 2% CPU time at IlMHz clock speed. 5-22 Tools Support For additional information please contact: Rhombus P.O. Box 871 Mauldin, SC 29662 TEL: 803-676-0012 FAX: 803-676-0015 Tools Support Figure 6. ProtolEvaluation Boards for the 2051 SCE-51 SingleChip Emulation Features Why SingleChip? • Creates ROMIRAM Emulator for 51 family single-chip micro-controllers • Gain 18 more I/O pins • High MHz without concern for timing • Additional memory space available for debug S/W • Reduce baord size • Works with all 51 family variants • Increase reliability • No loss of specialized functions • Secure proprietary code • Figure 7. SCE-51 5·23 AlmEL Until now, low cost development tools such as ROM Emulators and srw Debuggers, could only be used with 51 Family Microprocessors that were operating in expanded mode and using external memory. That has now changed thatks to SCE-51. SCE-51 is a 2.4" by 3.2" assembly that plugs directly into the Single-Chip Micro-ControIIer socket and creates a 32K ROMIRAM Emulator. The extra memory provides sufficient space for both the Application code and Debug srw. At the same time, SCE-51 maintains the availability of the 18 extra Port pins created by Single-Chip operation. Those two important functions give SCE-51 the most valuable features of a Single-Chip 'ICE', but at a fraction of its cost. Another plus when compared to an 'ICE' is that one device covers all 40/44 pin variants of the 51 Family. And all specialized functions of each variant are retained. Simply instaII a PLCC version of the specific 51 to be emulated into SCE-51 and select a PLCC or DIP adapter to suit the Target socket. Thanks to SCE-51 you no longer pay a premium for Single-Chip development, and no longer need volume production to share those costs. Make your next application Single-Chip with the help of SCE-5l. Technical • Access time = 15 ns + SRAM access (optional 10 ns) • TTL and CMOS compatible • Quiet 4 layer PCB • Powered by Single-Chip Socket (100 mA at 5 V 25 MHz) • Includes cable plus choice of 40 DIP or 44 PLCC adapter • InstaIIed height 3.5" Width 2.4" • Connects to PC printer port • Supports Intel HEX file fornlat • Command line loader with memory map options Note: The 18 Port Pins normally allocated to expanded memory will be restricted to byte wide Read & Write operations during Emulation. For additional information please contact: Rhombus P.O. Box 871 Mauldin, SC 29662 TEL: 803-676-0012 FAX: 803-676-0015 SOIC to DIP Programming Adapter for AT89C105112051 The programming adapter will convert the 20-pin SOlC down to a 20-pin DIP. It is a universal adapter which works on any programmer. This adapter can be ordered as part number AS-20-2001S-6 from Emulation Technology. For emulation purposes an adapter is available which enables usage of a 20-pin DIP to a 20-pin SOlC footprint. The surface mount adapter can be ordered as AS-DIP.3-020-5003-1. 5-24 Tools Support For additional information please contact: Emulation Technology 2344 Walsh Ave, Bldg. F Santa Clara, CA 95051 TEL: 408-982-0660 FAX: 408-982-0664 BBS: 408-982-9044 ATABX051 Features • • • Compatible with 4D-pin MCS-51TM sockets Compatible with in-circuit-emulators with 4D-pin sockets 32 Programmable I/O Lines or 15 Programmable I/O Lines Description(1) Atmel's 20- to 40-pin adapter board is for use in designing A T89C 10SlIAT89C20SI systems. The ATABXOSI maps the pins on the 20-pin device to the corresponding pin locations in a 40-pin 80CSI footprint. Customers can use this board to adapt existing in-circuit-emulators for use in AT89C1OSlIAT89C20SI designs (note that a comparator must also be added for fuJI emulation) or to plug in 40-pin 80CSI devices into 20-pin A T89C1OSlIA T89C20SI sockets. In addition, the board can be used to adapt the 20-pin footprint to an existing 40-pin socket. M icrocontroller Two Way Adaptor Board Pin Configurations PDIP/SOIC 2D-Pin PDIP/Cerdip 40-Pin vee RST vee (3) (T2) P1.0 (3)(T2EX) P1.1 (21\~~~~ =~:~ :~:~ P1.2 PO.l (A01) XTAL2 XTAL1 (INTO) P3.2 (INT1) P3.3 P1.5 P1.4 P1.3 P1.2 (21:i~~ =~:: =~:~ :~:~~~ P1.3 Pt.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 PO.2 (A02) PO.3 (AD3) PO.4 ("04) PO.S (AD5) PO.6 (AD6) PO.7 (A07) ENVPP (TXO) PS.1 (fN'ITl) PS.2 ALE/PAOG (21 GND "-;..;...-_ _~r P3.7 (INT1) (TO) (n) (WR) PS.3 P3.4 PSEN P2.7 (A15) P2.6 (A14) P3.5 P2.5 (A13) PS.6 P2.4 (A12) OW) PS.7 P2.3 (Al1) XTAL2 XTAL 1 GND --...:"'--_ _• Notes: pO.a (ADO) P2.2 (A10) P2.1 (A9) P2.0 (ABI 1. This adapter cannot be used with programmers for programming purposes. Although the pins are defined the same in operation mode, the pin definitions and algorithms are different from the AT89C5l in programming mode. 2. Pins (RxD) P3.0, (ThD) P3.I, and (TI) P3.5 are AT89C2051 pins only, but not for AT89C105 1. 3. Pins (T2) PI.O and (T2EX) Pl.1 are AT89C52 pins only. 0376B 5-25 ABX051 Two Way Adapter Board 1.10" -----I 2.10" Board Characteristics I. Holes: .040 Diameter; Plated 2. Material: .063 Thick FR4; IOZ Copper 3. Finish: SMOBC 4. Soldermask both sides per artwork Ordering Information Contact the lead Atmel Sales Representative for availability and ordering information. 5-26 ATABX051 Microcontroller Product Information General Architecture Microcontroller Data Sheets Microcontroller Application Notes Programmer Support/Development Tools Microcontroller Cross-Reference Package Outlines Miscellaneous Information AlmEL - - - - - - _ _ _ _ _ _ _ _ _ _ _ _ _ _ Contents Section 6 Microcontroller Cross-Reference Microcontroller Cross-Reference Guide .......................................................................... 6-3 • 6-1 6-2 Microcontroller Cross-Reference Guide Microcontroller Abbreviated Cross-Reference Guide Intel PART NUMBER i80C31 no program store i80C51 4 Kbvtes of ROM & 128 bytes 4 Kbytes of EPROM & 128 RAM 8 Kbvtes of ROM & 256 bytes 8 Kbytes of EPROM & 256 RAM iS7C51 i80C52 iS7C52 PACKAGE Atmel MCS-51 AT89C51 4 Kbytes of FLASH & 128 bytes of RAM of RAM AT89C51 bytes of ATS9C51 4 Kbvtes of FLASH & 128 bytes of RAM of RAM AT89C52 bytes of AT89C52 8 Kbvtes of FLASH & 256 bytes of RAM CERDIP D CERDIP P PDIP PLCC POFP P J 0 PDIP PLCC POFO PhilipslSignetics PCx80C31 SC80C31 PCx80C51 SC80C51 SC87C51 P80C32 P80C52 P87C52 S83C752 S87C752 S83C751 S87C751 S83C750 S87C750 Atmel o bytes of ROM & 128 bytes of RAM o bytes of ROM & 128 bytes of RAM AT89C51 AT89C51 4 Kbytes of FLASH & 128 bytes of RAM 4 Kbvtes of ROM & 128 bytes of RAM 4 Kb'll~s of ROM&128 bytes of RAM 4 Kbytes of EPROM & 128 bytes of RAM bytes of ROM & 256 bytes of RAM 8 Kbvtes of ROM & 256 bytes of RAM 8 Kbytes of EPROM & 256 bytes of RAM 2 Kbvtes of ROM & 64 bytes of RAM 2 Kbvtes of EPROM & 64 bytes of RAM 2 Kbvtes of ROM & 64 bytes of RAM 2 Kbvtes of EPROM & 64 bytes of RAM 1 Kbvte of ROM & 64 bytes of RAM 1 Kbvte of EPROM & 64 bytes of RAM AT89C51 AT89C51 4 Kbvtes of FLASH & 128 bytes of RAM 4 Kbvtes of FLASH & 128 bYles of RAM AT89C51 4 Kbytes of FLASH & 128 bytes of RAM AT89C52 AT89C52 8 Kbvtes of FLASH & 256 Mes of RAM 8 Kbvtes of FLASH & 256 bytes of RAM AT89C52 8 Kbytes of FLASH & 256 bytes of RAM AT89C2051' AT89C2051' AT89C2051' AT89C2051' AT89C1051' AT89C1051' 2 Kbvtes of FLASH & 128 bytes of RAM 2 Kbvtes of FLASH & 128 bytes of RAM 2 Kbvtes of FLASH & 128 bytes of RAM 2 Kbvtes of FLASH & 128 bytes of RAM 1 Kbvte of FLASH & 64 bytes of RAM 1 Kbvte of FLASH & 64 bytes of RAM o PACKAGE F N A K B CERDIP PDIP PLCC LCC POFO AMD PART 8751 NUMBER 87C51 87C52T2 PACKAGE 8 Kbytes of FLASH & 256 bytes of RAM D N S PART NUMBER 4 Kbytes of FLASH & 128 bytes of RAM 4 Kbytes of FLASH & 128 bytes of RAM S SOIC (89C2051 only) D P CERDIP PDIP PLCC LCC POFO J L 0 Atmel 4 Kbytes of EPROM & 128 bytes of AT89C51 RAM 4 Kbytes of EPROM & 128 bytes of AT89C51 RAM 8 Kbytes of EPROM & 256 bytes of AT89C52 RAM 4 Kbytes of FLASH & 128 bytes of RAM 4 Kbytes of FLASH & 128 bytes of RAM 8 Kbytes of FLASH & 256 bytes of RAM D CERDIP D CERDIP· P PDIP PLCC LCC P PDIP PLCC LCC J L J L • Indicates Atmel similar function and not direct replacement/socket compatible 0517A 6-3 • AlmEL Microcontroller Abbreviated Cross-Reference Guide (continued) Siemens PART NUMBER 4 Kby1es of ROM & 128 by1es of RAM AT89C51 4 Kby1es of FLASH & 128 by1es of RAM SAB8031 o by1es of ROM & 128 by1es of RAM AT89C51 4 Kby1es of FLASH & 128 by1es of RAM ISAB8052 SAB8032 SABC501-1R SABC501-L PACKAGE Atmel SAB8051 8 Kbvtes of ROM & 256 bytes of RAM AT89C52 bytes of ROM & 256 bytes of RAM AT89C52 8 Kbvtes of ROM & 256 bytes of RAM AT89C52 bytes of ROM & 256 bytes of RAM AT89C52 o o PACKAGE POIP P POIP N PLCC J PLCC of of of of RAM RAM RAM RAM AT89C51 4 Kby1es of FLASH & 128 by1es of RAM 80C51 4 Kby1es of ROM & 128 by1es of RAM AT89C51 4 Kby1es of FLASH & 128 by1es of RAM 80C32 80C52 o bytes of ROM & 256 bytes of RAM AT89C52 8 Kbvtes of ROM & 256 bytes of RAM IAT89C52 8 Kbvtes of FLASH & 256 bytes of RAM Kbvtes of FL ASH & 256 bytes of RAM 0 CEROIP 0 CEROIP P S R POIP PLCC LCC PQFQ TQFP P POIP PLCC LCC PQFQ TQFP OS5000FP OS5001FP OS5000 OS5000T OS2250 OS2250T J L Q A Atmel o by1es of ROM & 128 by1es of RAM o by1es of ROM & 128 by1es of RAM 18 8 8 8 Kbvtes of Kbvtes of Kbvtes of Kbvtes of ROM ROM ROM ROM & & & & 256 256 256 256 bytes bytes bytes bytes of of of of RAM RAM RAM RAM Microchip AT89C51 4 Kby1es of FLASH & 128 by1es of RAM AT89C51 4 Kby1es of FLASH & 128 by1es of RAM AT89C52 AT89C52 AT89C52 AT89C52 8 8 8 8 Kbvtes of FLASH Kbvtes of FLASH Kbvtes of FLASH Kbvtes of FLASH & & & & 256 256 256 256 bytes bytes bytes bytes of of of of RAM RAM RAM RAM Atmel PIC16C54 512 by1es EPROM & 32 by1es of RAM AT89C2051* 2 Kbytes of FLASH & 128 by1es of RAM PIC16C54A 512 by1es EPROM & 32 by1es of RAM AT89C2051* 2 Kby1es of FLASH & 128 by1es of RAM PIC16LC54AA PIC16CR57A PIC16CLR57A PIC16C55 PIC16C56 PIC16C57 PIC16C71 PIC16LC71 PIC16C84 PIC16LC84 512 bytes EPROM & 32 bytes of RAM 512 bytes EPROM & 32 bytes of RAM 512 bytes EPROM & 32 bytes of RAM 512 bytes EPROM & 32 bvtesof RAM 1 Kbvte EPROM & 32 bytes of RAM 2 Kbvtes EPROM & 80 bytes of RAM 512 bytes EPROM & 32 bvtes of RAM 512 bytes EPROM & 32 bytes of RAM 512 bytes EPROM & 32 bytes of RAM 512 bytes EPROM & 32 bytes of RAM AT89C2051* AT89C2051* AT89C2051* AT89C2051* AT89C2051* AT89C2051* AT89C2051* AT89C2051* AT89C2051* AT89C2051* 2 2 2 2 2 2 2 2 2 2 JW CEROIP S SOIC P SP S S SS POIP .3POIP DIE SOIC SSOP P W POIP DIE * Indicates Atmel similar function and not direct replacement/socket compatible 6-4 bytes bytes bytes bYles Atmel Dallas PACKAGE 256 256 256 256 o by1es of ROM & 128 by1es of RAM T PART NUMBER & & & & 80C31 V PART NUMBER Kbvtes of FLASH Kbvtes of FLASH Kbvtes of FLASH KbYles of FLASH P Matra PART NUMBER 8 8 8 8 Microcontroller Cross-Reference Guide Kbvtes of FLASH Kbvtes of FLASH Kbvtes of FLASH Kbvtes of FLASH Kbvtes of FLASH Kbvtes of FLASH Kbvtes of FLASH Kbvtes of FLASH Kbvtes of FLASH Kbvtes of FLASH & & & & & & & & & & 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes of of of of of of of of of of RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM Microcontroller Cross-Reference Guide Microcontroller Abbreviated Cross-Reference Guide (continued) Zilo~ PART NUMBER Atmel Z86C08 2 Kbytes of ROM & 124 bytes of RAM AT89C2051· 2 Kbytes of FLASH & 128 bytes of RAM Z86E08 2 Kbytes of ROM & 124 bytes of RAM AT89C2051· 2 Kbytes of FLASH & 128 bytes of RAM Z86C09 Z86C19 Z86E09 Z86C17 Z86L06 Z86L29 Z86C06 Z86E09 Z86C08 Z86E08 Z86C30 Z86E30 Z86C40 Z86E40 2 Kbvtes of ROM & 124 bytes of RAM 2 Kbvtes of ROM & 124 bytes of RAM 2 Kbvtes of ROM & 124 bytes of RAM 2 Kbvtes of ROM & 124 bytes of RAM 1 Kbyte of ROM & 124 Qytes of RAM 6 Kbvtes of ROM & 124 bytes of RAM 1 Kbvte of ROM & 124 bytes of RAM 1 Kbvte of ROM & 124 bytes of RAM 2 Kbvtes of ROM & 124 bytes of RAM 2 Kbvtes of ROM & 124 bytes of RAM 4 Kbvtes of ROM & 236 bytes of RAM 4 Kbvtes of ROM & 236 bytes of RAM 4 Kbvtes of ROM & 236 bytes of RAM 4 Kbvtes of ROM & 236 bytes of RAM 2 2 2 2 1 2 1 1 2 2 2 2 2 2 AT89C2051· AT89C2051· AT89C2051· AT89C2051· AT89Cl051· AT89C2051· AT89Cl051· AT89Cl051· AT89C2051· AT89C2051· AT89C2051· AT89C2051· AT89C2051· AT89C2051· Kbvtes of FLASH & 128 bytes of RAM Kbvtes of FLASH & 128 bytes of RAM Kbvtes of FLASH & 128 bytes of RAM Kbvtes of FLASH & 128 bytes of RAM Kbyte of FLASH & 64 bytes of RAM Kbvtes of FLASH & 128 bytes of RAM Kbvte of FLASH & 64 bytes of RAM Kbvte of FLASH & 64 bytes of RAM Kbvtes of FLASH & 128 bytes of RAM Kbvtes of FLASH & 128 bytes of RAM Kbvtes of FLASH & 128 bytes of RAM Kbvtes of FLASH & 128 bytes of RAM Kbvtes of FLASH & 128 bytes of RAM Kbvtes of FLASH & 128 bytes of RAM • * Indicates Atmel similar function and not direct replacement/socket compatible 6-5 AlmEL AT89C51 Microcontroller Detailed Cross-Reference Guide AMD EPROM Atmel PB031AH-1B DB031AH-1B NB031AH-1B PB031AH-15 DB031AH-15 NB031AH-15 PB031AH DB031AH NB031AH IDB031AHB DB751H RB751H IDB751H IDB751HB PBOC51BH DBOC51BH NBOC51BH PBOC51BH-1 DBOC51BH-1 NBOC51BH-1 PBOC31BH DBOC31BH NBOC31BH PBOC31BH-1 DBOC31BH-1 NBOC31BH-1 ATB9C51-20PC ATB9C51-20DC ATB9C51-20JC ATB9C51-20PC ATB9C51-20DC ATB9C51-20JC ATB9C51-20PC ATB9C51-20DC ATB9C51-20JC ATB9C51-20DI ATB9C51-20DC ATB9C51-20JC ATB9C51-20DI ATB9C51-20DI ATB9C51-20PC ATB9C51-20DC ATB9C51-20JC ATB9C51-20PC ATB9C51-20DC ATB9C51-20JC ATB9C51-20PC ATB9C51-20DC ATB9C51-20JC ATB9C51-20PC ATB9C51-20DC ATB9C51-20JC B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICRO CONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER Intel UVEPROM Atmel FLASH Part Description DB7C51 DB7C51-2 TDB7C51 DB7C51-1 DB7C51-20 ATB9C51-20PC ATB9C51-20PC ATB9C51-20PI ATB9C51-20PC ATS9C51-20PC B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER S BIT MICROCONTROLLER S BIT MICROCONTROLLER 4 4 4 4 4 KB KB KB KB KB ATS9C51-20JC ATS9C51-20JC AT89C51-20PC ATS9C51-20PC ATS9C51-20QC ATS9C51-20QC ATS9C51-20JI ATS9C51-20PI ATS9C51-20JC AT89C51-20PC AT89C51-20QC ATB9C51-20JC ATS9C51-20PC ATS9C51-20QC S BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER S BIT MICROCONTROLLER S BIT MICROCONTROLLER S BIT MICROCONTROLLER S BIT MICROCONTROLLER S BIT MICROCONTROLLER S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ATS9C51-20JC ATS9C51-20JC ATS9C51-20PC ATS9C51-20PC ATS9C51-20QC ATS9C51-20QC ATB9C51-20JI ATB9C51-20PI ATB9C51-20JC ATB9C51-20PC ATB9C51-20QC ATB9C51-20JI ATB9C51-20PI S BIT MICROCONTROLLER S BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER S BIT MICROCONTROLLER S BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 4 4 4 4 4 4 4 4 4 4 4 4 4 Part Description Speed Pka Temp 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz PDIP CERDIP PLCC PDIP CERDIP PLCC PDIP CERDIP PLCC CERDIP CERDIP PLCC CERDIP CERDIP PDIP CERDIP PLCC PDIP CERDIP PLCC PDIP CERDIP PLCC PDIP CERDIP PLCC COM COM COM COM COM Speed PkJ.l Temp FLASH FLASH FLASH FLASH FLASH 20 20 20 20 20 MHz MHz MHz MHz MHz PDIP PDIP PDIP PDIP PDIP COM COM IND COM COM KB KB KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20 20 20 20 20 20 20 20 20 20 20 20 20 20 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz PLCC PLCC PDIP PDIP PQFP PQFP PLCC PDIP PLCC PDIP PQFP PLCC PDIP PQFP COM COM COM COM COM COM IND IND COM COM COM COM COM COM KB KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz PLCC PLCC PDIP PDIP PQFP PQFP PLCC PDIP PLCC PDIP PQFP PLCC PDIP COM COM COM COM COM COM IND IND COM COM COM IND IND FLASH 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH ICOM COM COM COM IND COM COM IND IND COM COM COM COM COM COM COM COM COM COM COM COM OTP NB7C51 NS7C51-2 P87C51 P87C51-2 SB7C51 SS7C51-2 TNS7C51 TPS7C51 N87C51-1 PS7C51-1 SS7C51-1 NB7C51-20 PS7C51-20 SB7C51-20 MROM NSOC51BH NSOC51BH-2 PSOC51BH PBOC51BH-2 SBOC51BH SSOC51BH-2 TNOC51BH TPBOC51BH NBOC51BH-1 PBOC51BH-1 SBOC51BH-1 TNBOC51 BH-1 TPBOC51 BH-1 6-6 Microcontroller Cross-Reference Guide Microcontroller Cross-Reference Guide AT89C51 Microcontroller Detailed Cross-Reference Guide (continued) Matra ROM Atmel FLASH Part Descriotion APBOC51F-1 A P BOC51 F-S APBOC51 F ASBOC51F-1 ASBOC51F-S AS BOC51 F ATBOC51F-1 ATBOC51F-S ATBOC51 F AVBOC51F-1 AVBOC51 F-S A V BOC51 F I P BOC51 F -25 IPBOC51F-1 IP80C51F-L IP80C51F-L IP80C51F-S I PBOC51 F I S BOC51 F -25 ISBOC51F-1 ISBOC51F-L ISBOC51F-L ISBOC51F-S I SBOC51 F IT BOC51 F -25 ITBOC51F-1 IT BOC51 F-L IT 80C51 F-L IT 80C51 F-S IT80C51 F I V BOC51 F -25 IV80C51F-1 IV80C51 F-L IV80C51 F-L I V BOC51 F-S IV80C51 F M 080C51 F -MB M 080C51 F -MB M R 80C51 F -MB M R 80C51 F -MB P 80C51 F -25 P 80C51 F-1 P 80C51 F-L P BOC51 F-L P 80C51 F-S P 80C51 F S 80C51 F -25 S 80C51 F-1 S 80C51 F-L S 80C51 F-L S 80C51 F-S S 80C51 F T 80C51 F -25 T BOC51 F-1 T BOC51 F-L T 80C51 F-L T 80C51 F-S T 80C51 F V 80C51 F -25 V 80C51 F-1 V 80C51 F-L V BOC51 F-L V BOC51 F-S V 80C51 F AT89C51-20PA AT89C51-20PA ATB9C51-20PA ATB9C51-20JA ATB9C51-20JA ATB9C51-20JA ATB9C51-20AA ATB9C51-20AA ATB9C51-20AA AT89C51-200A ATB9C51-200A ATB9C51-200A ATB9C51-24PI ATB9C51-20PI ATB9LV51-16PI AT89LV51-20PI AT89C51-20PI ATB9C51-20PI ATB9C51-24JI ATB9C51-20JI ATB9LV51-16JI ATB9LV51-20JI AT89C51-20JI AT89C51-20JI ATB9C51-24AI ATB9C51-20AI AT89LV51-16AI ATB9LV51-20AI ATB9C51-20AI AT89C51-20AI AT89C51-2401 ATB9C51-2001 AT89LV51-1601 AT89LV51-2001 AT89C51-2001 ATB9C51-2001 AT89C51-200M 1883 AT89C51-200M 1883 AT89C51-20LM 1883 AT89C51-20LM 1883 AT89C51-24PC AT89C51-20PC AT89L V51-16PC AT89LV51-20PC AT89C51-20PC AT89C51-20PC AT89C51-24JC AT89C51-20JC AT89LV51-16JC AT89LV51-20JC AT89C51-20JC AT89C51-20JC AT89C51-24AC AT89C51-20AC AT89LV51-16AC ATB9LV51-20AC AT89C51-20AC AT89C51-20AC AT89C51-240C AT89C51-200C AT89LV51-160C AT89LV51-200C AT89C51-200C AT89C51-200C 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER 3 V. B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V. 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V. 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER AlmEl 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH Soeed Pka Temo 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz POIP POIP POIP PLCC PLCC PLCC TOFP TOFP TOFP POFP POFP POFP POIP POIP POIP POIP POIP POIP PLCC PLCC PLCC PLCC PLCC PLCC TOFP TOFP TOFP TOFP TOFP TOFP POFP POFP POFP POFP POFP POFP CEROlP CEROIP LCC LCC POIP POIP POIP POIP POIP POIP PLCC PLCC PLCC PLCC PLCC PLCC TOFP TOFP TOFP TOFP TOFP TOFP POFP POFP POFP POFP POFP POFP AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO MIL MIL MIL MIL COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM 6-7 • AlmEl AT89C51 Microcontroller Detailed Cross-Reference Guide (continued) Matra Atrnel Part Description A P 80C51 -1 A P80C51 -S A P80C51 AS80C51 -1 AS 80C51 -S AS 80C51 AT 80C51 -1 A T80C51 -S A T80C51 A V 80C51 -1 A V80C51 -S A V 80C51 P 80C51 -25 P 80C51 -1 P 80C51 -L P 80C51 -L P 80C51 -S P 80C51 S 80C51 -25 S 80C51 -1 S 80C51 -L S 80C51 -L S 80C51 -S S 80C51 T 80C51 -25 T 80C51 -1 T 80C51 -L T 80C51 -L T 80C51 -S T 80C51 V 80C51 -25 V 80C51 -1 V 80C51 -L V 80C51 -L V 80C51 -S V 80C51 M D80C51 -MB M D 80C51 -MB M R 80C51 -MB M R 80C51 -MB P 80C51 -25 P 80C51 -1 P 80C51 -L P 80C51 -L P 80C51 -S P 80C51 S 80C51 -25 S 80C51 -1 S 80C51 -L S 80C51 -L S 80C51 -S S 80C51 T 80C51 -25 T 80C51 -1 T 80C51 -L T 80C51 -L T 80C51 -S T 80C51 V 80C51 -25 V 80C51 -1 V 80C51 -L V 80C51 -L V 80C51 -S V 80C51 AT89C51-20PA AT89C51-20PA AT89C51-20PA AT89C51-20JA AT89C51-2OJA AT89C51-20JA AT89C51-20AA AT89C51-20AA AT89C51-20AA AT89C51-200A AT89C51-200A AT89C51-200A AT89C51-24PI AT89C51-20PI AT89LV51-16PI AT89LV51-20PI AT89C51-20PI AT89C51-20PI AT89C51-24JI AT89C51-20JI AT89LV51-16JI AT89LV51-20JI AT89C51-20JI AT89C51-20JI AT89C51-24AI AT89C51-20AI AT89LV51-16AI AT89LV51-20AI AT89C51-20AI AT89C51-20AI AT89C51-2401 AT89C51-2001 AT89LV51-1601 AT89LV51-2001 AT89C51-2001 AT89C51-2001 AT89C51-20DM 1883 AT89C51-20DM 1883 AT89C51-20LM 1883 AT89C51-20LM 1883 AT89C51-24PC AT89C51-20PC AT89LV51-16PC AT89LV51-20PC AT89C51-20PC AT89C51-20PC AT89C51-24JC AT89C51-20JC AT89LV51-16JC AT89LV51-20JC AT89C51-20JC AT89C51-20JC AT89C51-24AC AT89C51-20AC AT89LV51-16AC AT89LV51-20AC AT89C51-20AC AT89C51-20AC AT89C51-240C AT89C51-200C AT89LV51-160C AT89LV51-200C AT89C51-200C AT89C51-200C 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V,8 BIT MICROCONTROLLER 3 V,8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V,8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 6-8 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH Microcontroller Cross-Reference Guide Sneed Pkn Ternn 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz PDIP PDIP PDIP PLCC PLCC PLCC TOFP TOFP TOFP POFP POFP POFP PDIP PDIP PDIP PDIP PDIP PDIP PLCC PLCC PLCC PLCC PLCC PLCC TOFP TOFP TOFP TOFP TOFP TOFP POFP POFP POFP POFP POFP POFP CERDIP CERDIP LCC LCC PDIP PDIP PDIP PDIP PDIP PDIP PLCC PLCC PLCC PLCC PLCC PLCC TOFP TOFP TOFP TOFP TOFP TOFP POFP POFP POFP POFP POFP POFP AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND MIL MIL MIL MIL COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM Microcontroller Cross-Reference Guide AT89C51 Microcontroller Detailed Cross-Reference Guide (continued) Philips UVEPROM Atmel FLASH Part Description SC87C510CK44 SC87C510CF40 SC87C51 ACK44 SC87C51 ACF40 SC87C510GK44 SC87C510GF40 SC87C51 AGK44 SC87C51AGF40 SC87C510PK44 SC87C510PF40 AT89C51-20JC AT89C51-20PC AT89C51-20JI AT89C51-20PI AT89C51-20JC AT89C51-20PC AT89C51-20JI AT89C51-20PI AT89C51-24JC AT89C51-24PC 8 8 8 8 8 8 8 8 8 8 AT89C51-20JC AT89C51-20PC AT89C51-20QC AT89C51-20JI AT89C51-20PI AT89C51-20JC AT89C51-20PC AT89C51-20QC AT89C51-20JI AT89C51-20PI AT89C51-24JC AT89C51-24PC ATB9C51-24QC 8 8 8 8 8 8 8 8 8 8 8 8 ATB9C51-20JC ATB9C51-20PC AT89C51-20QC AT89C51-20JI AT89C51-2oPI AT89C51-20JC AT89C51-2oPC AT89C51-2oQC AT89C51-20JI AT89C51-20PI AT89C51-24JC AT89C51-24PC AT89C51-24QC 8 8 8 8 8 8 8 8 8 8 8 8 ATB9C51-2oJC AT89C51-20PC AT89C51-20QC AT89C51-20JC AT89C51-20PC ATB9C51-20QC AT89C51-20JI AT89C51-20PI AT89C51-20QI AT89C51-16JA AT89C5H6PA AT89C51-24JC AT89C51-24PC AT89C51-24QC Speed Pka Temn BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER 4 4 4 4 4 4 4 4 4 4 KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20 MHz 20MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 24 MHz PLCC PDIP PLCC PDIP PLCC PDIP PLCC PDIP PLCC PDIP COM COM IND IND COM COM IND IND COM COM BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER B BIT MICROCONTROLLER 4 4 4 4 4 4 4 4 4 4 4 4 4 KB KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20MHz 20 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz PLCC PDIP PQFP PLCC PDIP PLCC PDIP PQFP PLCC PDIP PLCC PDIP PQFP COM COM COM IND IND COM COM COM IND IND COM COM COM B BIT MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER 4 4 4 4 4 4 4 4 4 4 4 4 4 KB KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz PLCC PDIP PQFP PLCC PDIP PLCC PDIP POFP PLCC PDIP PLCC PDIP POFP COM COM COM IND IND COM IND IND IND IND COM COM COM BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 4 4 4 4 4 4 4 4 4 4 4 4 4 4 KB KB KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20 20 20 20 20 20 20 20 20 20 20 20 24 24 PLCC PDIP POFP PLCC PDIP POFP PLCC PLCC PQFP PLCC PDIP PLCC PDIP POFP COM COM COM COM COM COM IND IND IND AUTO AUTO COM COM COM OTP SC87C510CA44 SC87C510CN40 SC87C510CB44 SC87C510CA44 SC87C510CN40 SC87C510GA44 SC87C510GN40 SC87C510GB44 SC87C51AGA44 SC87C51AGN40 SC87C51CPA44 SC87C510CPN40 SCB7C510CPB44 MROM SCBOC51 BOCA44 SCBOC51 BOCN40 SC80C51 BoCB44 SC80C51 BOCA44 SC80C51 BOCN40 SC80C51 BoCGA44 SC80C51 BOCGN40 SC80C51 BOCGB44 SC80C51 BOCGA44 SC80C51 BOCGN40 SC80C51 BOCPA44 SC8oC51 BOCPN40 SC80C51 BOCPB44 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT MROM PCB8051 BH-2WP PCB8051 BH-2P PCB8051 BH-2H PCB8051 BH-3WP PCB8051 BH-3P PCB8051BH-3H PCB8051 BH-3WP PCB8051 BH-3P PCB8051 BH-3H PCB8051 BH-3WP PCB8051BH-3P PCB8051BH-4WP PCB8051BH-4P PCB8051 BH-4H 8 8 8 8 8 AlmEl MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 6-9 • AT89C51 Microcontroller Detailed Cross-Reference Guide (continued) Philios UVEPROM Atmel FLASH Part Descriotion SCB7C510CK44 SC87C510CF40 SC87C51 ACK44 SC87C51 ACF40 SC87C510GK44 SCB7C510GF40 SC87C51 AGK44 SCB7C51 AGF40 SCB7C510PK44 SCB7C510PF40 ATB9C51-20JC AT89C51-20PC AT89C51-20JI AT89C51-20PI AT89C51-20JC ATB9C51-20PC AT89C51-20JI AT89C51-20PI AT89C51-24JC AT89C51-24PC 8 8 8 8 8 8 8 8 8 8 BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER 4 4 4 4 4 4 4 4 4 4 KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH Soeed Pka Temo 20 20 20 20 20 20 20 20 24 24 PLCC PDIP PLCC PDIP PLCC PDIP PLCC PDIP PLCC PDIP COM COM IND IND COM COM IND IND COM COM Soeed Pka Temp 20 20 20 20 20 20 20 PDIP PDIP PDIP PDIP PLCC PLCC PLCC COM COM COM COM COM COM COM MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Siemens Atmel ROM/ROMless FLASH Part Descriotion SABB051A-P SABB031A-P SABB051 A-16-P SABB031 A-16-P SAB8051A-N SAB8051 A-16-N SAB8031A-16-N SABB051A-12-P-T 40/85 SABB051 A-1 O-P-T 40/110 SAB8031A-12-P-T 40lB5 SAB8051 A-1 O-P-T AT89C51-20PC ATB9C51-20PC ATB9C51-20PC AT89C51-20PC AT89C51-20JC AT89C51-20JC AT89C51-20JC B BIT B BIT 8 BIT 8 BIT 8 BIT 8 BIT 8 BIT ATB9C51-20PI 8 BIT MICROCONTROLLER 4 KB FLASH 20 MHz PDIP IND AT89C51-20PA 8 BIT MICROCONTROLLER 4 KB FLASH 20 MHz PDIP AUTO AT89C51-20PI 8 BIT MICROCONTROLLER 4 KB FLASH 20 MHz PDIP IND AT89C51-20PA 8 BIT MICROCONTROLLER 4 KB FLASH 20 MHz PDIP AUTO 40/110 6-10 MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER 4 4 4 4 4 4 4 KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH Microcontroller Cross-Reference Guide MHz MHz MHz MHz MHz MHz MHz Microcontroller Cross-Reference Guide AT89C52 Microcontroller Detailed Cross-Reference Guide AMD EPROM Atmel FLASH Part Description DB7C52T2 R87C52T2 PB7C52T2 N87C52T2 ID87C52T2 IR87C52T2 IP87C52T2 IN87C52T2 D87C52T2-1 R87C52T2-1 P87C52T2-1 N87C52T2-1 ID87C52T2-1 IR87C52T2-1 IP87C52T2-1 IN87C52T2-1 P87C32T2-1 N87C32T2-1 IP87C32T2-1 IN87C32T2-1 ATB9C52-20DC AT89C52-20LC AT89C52-20PC ATB9C52-20JC AT89C52-20DI AT89C52-20Ll AT89C52-20PI AT89C52-20JI AT89C52-20DC AT89C52-20LC AT89C52-20JC AT89C52-20DC AT89C52-20DI AT89C52-20Ll AT89C52-20DI AT89C52-20JI AT89C52-20PC AT89C52-20JC AT89C52-20PI AT89C52-20JI B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER Intel MROM Atmel FLASH Part Descriotion P8052AH D8052AH N8052AH P8032AH D8032AH N8032AH AT89C52-20PC AT89C52-20DC AT89C52-20JC AT89C52-20PI AT89C52-20DC AT89C52-20JC 8 8 8 8 8 8 AT89C52-20PC AT89C52-20DC AT89C52-20JC AT89C52-20LC AT89C52-20DI AT89C52-20PI AT89C52-20DI AT89C52-20DC AT89C52-20JC AT89C52-20PC AT89C52-20QC AT89C52-20PI AT89C52-20DI AT89C52-20JI AT89C52-20PI AT89C52-20DI AT89C52-20JI AT89C52-20PC AT89C52-20QC AT89C52-20JC AT89C52-20PI AT89C52-20JI AT89C52-20PI AT89C52-20JI AT89C52-20PC AT89C52-20QC AT89C52-20JC AT89C52-20PI ATB9C52-20JI AT89C52-20PI AT89C52-20JI AT89C52-20DC 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH Soeed Pka Temo 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20MHz 20 MHz CERDIP LCC PDIP PLCC CERDIP LCC PDIP PLCC CERDIP LCC PLCC CERDIP CERDIP LCC CERDIP PLCC PDIP PLCC PDIP PLCC COM COM COM COM IND IND IND IND COM COM COM COM IND IND IND IND COM COM IND IND Soeed Pko Tem ... BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER 8 8 8 8 8 8 KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH 20 20 20 20 20 20 MHz MHz MHz MHz MHz MHz PDIP CERDIP PLCC PDIP CERDIP PLCC COM COM COM IND COM COM BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz PDIP CERDIP PLCC LCC CERDIP PDIP CERDIP CERDIP PLCC PDIP PQFP PDIP CERDIP PLCC PDIP CERDIP PLCC PDIP PQFP PLCC PDIP PLCC PDIP PLCC PDIP PQFP PLCC PDIP PLCC PDIP PLCC CERDIP COM COM COM COM IND IND IND COM COM COM COM IND IND IND IND IND IND COM COM COM IND IND IND IND COM COM COM IND IND IND IND COM EPROM P8752BH D8752BH N8752BH R8752BH TD8752BH QP8752BH LD8752BH D87C52 N87C52 P87C52 S87C52 TP87C52 TD87C52 TN87C52 LP87C52 LD87C52 LN87C52 P80C52 S80C52 N80C52 TP80C52 TN80C52 LP80C52 LN80C52 PBOC32 S80C32 N80C32 TP80C32 TN80C32 LP80C32 LNBOC32 D87C52-20 AlmEl 6-11 AT89C52 Microcontroller Detailed Cross-Reference Guide (continued) Intel Atmel Part Description N87C52-20 P87C52-20 S87C52-20 P8OC52-20 S80C52-20 N80C52-20 P8OC32-20 S8OC32-20 N80C32-20 AT89C52-20JC AT89C52-20PC AT89C52-20QC AT89C52-20PC AT89C52-20QC AT89C52-2OJC AT89C52-20PC AT89C52-20QC AT89C52-2OJC 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER Matra ROM Atmel FLASH Part Description A P 80C52 F-1 A P80C52 F-S A P 80C52 F AS 80C52 F-1 AS 80C52 F-S AS 80C52 F AT 80C52 F-1 AT80C52 F-S AT 80C52 F AV 80C52 F-1 AV 80C52 F-S AV80C52 F P 80C52 F -25 P 80C52 F-1 P 80C52 F-L P 80C52 F-L P 80C52 F-S P 80C52 F S 8OC52 F -25 S 80C52 F-1 S 80C52 F-L S 80C52 F-L S80C52 F-S S 80C52 F T 80C52 F -25 IT 80C52 F-1 IT 80C52 F-L IT 80C52 F-L IT 80C52 F-S IT 80C52 F AT89C52-20PA AT89C52-20PA AT89C52-20PA AT89C52-20JA AT89C52-20JA AT89C52-20JA AT89C52-20AA AT89C52-20AA AT89C52'20AA AT89C52-20QA AT89C52-20QA AT89C52-20QA AT89C52-24PI AT89C52-20PI AT89LV52-16PI AT89LV52-20PI AT89C52-20PI AT89C52-20PI AT89C52-24J1 AT89C52-2OJI AT89LV52-16J1 AT89LV52-2OJ I AT89C52-2OJI AT89C52-2OJI AT89C52-24AI AT89C52-20AI AT89LV52-16AI ATT89LV52-20AI AT89C52-20AI AT89C52-20AI 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V. 8 BIT MICROCONTROLLER 3 V.8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V. 8 BIT MICROCONTROLLER 3 V.8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V. 8 BIT MICROCONTROLLER 3 V. 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 I V 80C52 F -25 AT89C52-24QI I V 80C52 F-1 I V 80C52 F-L I V80C52 F-L I V 80C52 F-S I V 80C52 F M 0 80C52 F -MB M 0 80C52 F -MB M R 80C52 F -MB M R 80C52 F -MB P 80C52 F -25 P 80C52 F-1 P 80C52 F-L P8OC52 F-L P80C52 F-S P80C52 F S 80C52 F -25 S 80C52 F-1 S 80C52 F-L S 80C52 F-L AT89C52-2OQI AT89LV52-16QI AT89LV52-20QI AT89C52-20QI AT89C52-20QI AT89C52-20DM 1883 AT89C52-20DM 1883 AT89C52-20LM 1883 AT89C52-20LM 1883 AT89C52-24PC AT89C52-20PC AT89LV52-16PC AT89LV52-20PC AT89C52-20PC AT89C52-20PC AT89C52-24JC AT89C52-20JC AT89LV52-16JC AT89LV52-20JC 6-12 Speed Pka Temp 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz PLCC PDIP PQFP PDIP PQFP PLCC PDIP PQFP PLCC COM COM COM COM COM COM COM COM COM Speed Pka Temp KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND 8 BIT MICROCONTROLLER 8 KB FLASH 24 MHz 8 BIT MICROCONTROLLER 3 V. 8 BIT MICROCONTROLLER 3 V.8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V.8 BIT MICROCONTROLLER 3 V. 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V. 8 BIT MICROCONTROLLER 3 V 8 BIT MICROCONTROLLER 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz PDIP PDIP PDIP PLCC PLCC PLCC TQFP TQFP TQFP PQFP PQFP PQFP PDIP PDIP PDIP PDIP PDIP PDIP PLCC PLCC PLCC PLCC PLCC PLCC TQFP TQFP TQFP TQFP TQFP TQFP PQFPQ FP PQFP PQFP PQFP PQFP PQFP CERDIP CERDIP LCC LCC PDIP PDIP PDIP PDIP PDIP PDIP PLCC PLCC PLCC PLCC 8 8 8 8 8 8 8 8 8 KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH KB FLASH KB FLASH KBFLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH Microcontroller Cross-Reference Guide IND IND IND IND IND IND MIL MIL MIL MIL COM COM COM COM COM COM COM COM COM COM Microcontroller Cross-Reference Guide AT89C52 Microcontroller Detailed Cross-Reference Guide (continued) Matra Atmel Part Descriotion S 80C52 F-S S 80C52 F T 80C52 F -25 T 80C52 F 1 T 80C52 F-L T 80C52 F-L T 80C52 F-S T 80C52 F V 80C52 F -25 V 80C52 F-1 V 80C52 F-L V 80C52 F-L V 80C52 F-S V 80C52 F A P 80C52-1 A P 80C52-S A P 80C52 AS 80C52-1 AS 80C52-S AS 80C52 AT 80C52-1 AT 80C52-S AT 80C52 A V 80C52-1 A V 80C52-S A V 80C52 I P 80C52 -25 I P 80C52-1 I P 80C52-L I P 80C52-L P 80C52-S P 80C52 S 80C52 -25 S 80C52-1 S 80C52-L S 80C52-L S 80C52-S S 80C52 T 80C52 -25 T 80C52-1 T 80C52-L T 80C52-L T 80C52-S T 80C52 V 80C52 -25 V 80C52-1 V 80C52-L V 80C52-L V 80C52-S V 80C52 M D 80C52 -MB M D 80C52 -MB M R 80C52 -MB M R 80C52 -MB P 80C52 -25 P 80C52-1 P 80C52-L P SOC52-L P 80C52-S P 80C52 S 80C52 -25 S 80C52-1 S 80C52-L S 80C52-L S 80C52-S AT89C52-20JC AT89C52-20JC AT89C52-24AC AT89C52-20AC AT89LV52-16AC AT89L V52-20AC AT89C52-20AC AT89C52-20AC AT89CS2-24QC AT89CS2-20QC AT89LV52-16QC AT89LV52-20QC AT89C52-20QC AT89C52-20QC AT89C52-20PA AT89C52-20PA AT89C52-20PA AT89C52-20JA ATR9C52-20JA AT89C52-20JA AT89C52-20AA AT89C52-20AA AT89C52-20AA AT89C52-20QA AT89C52-20QA AT89C52-20QA AT89C52-24PI AT89C52-20PI AT89LV52-16PI AT89LV52-20PI AT89C52-20Pi AT89C52-20PI AT89C52-24JI AT89C52-20JI AT89LV52-16JI AT89LV52-20JI AT89C52-20JI AT89C52-20JI AT89C52-24AI AT89C52-20AI AT89LV52-16AI AT89LV52-20AI AT89C52-20AI AT89C52-20AI AT89C52-24QI AT89C52-20QI AT89LV52-16QI AT89LV52-20QI AT89C52-20QI AT89C52-20QI AT89C52-20DM /883 AT89C52-20DM /883 AT89C52-20LM /883 AT89C52-20LM /883 AT89C52-24PC AT89C52-20PC ATS9LV52-16PC AT89LV52-20PC AT89C52-20PC ATS9C52-20PC AT89C52-24JC AT89C52-20JC AT89LV52-16JC AT89LV52-20JC AT89C52-20JC 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V,8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V,8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER AlmEl 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH Soeed Pka Temo 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz PLCC PLCC TQFP TQFP TQFP TQFP TQFP TQFP PQFP PQFP PQFP PQFP PQFP PQFP PDIP PDIP PDIP PLCC PLCC PLCC TQFP TQFP TQFP PQFP PQFP PQFP PDIP PDIP PDIP PDIP PDIP PDIP PLCC PLCC PLCC PLCC PLCC PLCC TQFP TQFP TQFP TQFP TQFP TQFP PQFP PQFP PQFP PQFP PQFP PQFP CERDIP CERDIP LCC LCC PDIP PDIP PDIP PDIP PDIP PDIP PLCC PLCC PLCC PLCC PLCC COM COM COM COM COM COM COM COM COM COM COM COM COM COM AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND IND MIL MIL MIL MIL COM COM COM COM COM COM COM COM COM COM COM 6-13 II AT89C52 Microcontroller Detailed Cross-Reference Guide (continued) Matra Atmel Part Descriotion S 80C52 T 80C52 -25 T 80C52-1 T 80C52-L T 80C52-L T BOC52-S T BOC52 V 80C52 -25 V 8OC52-1 V 8oC52-L V 8oC52-L V80C52 -S V 8OC52 AT89C52-20JC AT89C52-24AC AT89C52-20AC AT89LV52-16AC ATB9LV52-20AC ATB9C52-20AC ATB9C52-20AC AT89C52-240C ATB9C52-200C ATB9LV52-16QC AT89LV52-200C AT89C52-200C AT89C52-200C 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER AT89C52-2oPA AT89C52-20PA AT89C52-2oPA AT89C52-2OJA AT89C52-2OJA AT89C52-2OJA AT89C52-2oAA AT89C52-20AA AT89C52-20AA AT89C52-200A AT89C52-200A ATB9C52-200A ATB9C52-24PI ATB9C52-2oPI ATB9LV52-16PI ATB9L V52-2oPI ATB9C52-20PI AT89C52-2oPI ATB9C52-24J1 AT89C52-20JI AT89LV52-16JI AT89LV52-2OJI ATB9C52-20JI ATB9C52-2OJI ATB9C52-24AI AT89C52-2oAI AT89LV52-16AI AT89LV52-20AI ATB9C52-2oAI AT89C52-2oAI ATB9C52-2401 ATB9C52-2001 AT89LV52-1601 ATB9LV52-2001 AT89C52-2001 AT89C52-2001 AT89C52-200M 18B3 ATB9C52-200M 1883 AT89C52-20LM 18B3 AT89C52-20LM 1883 AT89C52-24PC AT89C52-20PC AT89LV52-16PC ATB9LV52-20PC AT89C52-20PC ATB9C52-20PC ATB9C52-24JC AT89C52-20JC ATB9L V52-16JC ATB9LV52-20JC ATB9C52-20JC 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER 3 V,8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER B BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER 3 V, B BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 50eed Pka Temo FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz PLCC TOFP TOFP TOFP TOFP TOFP TOFP POFP POFP POFP POFP POFP POFP COM COM COM COM COM COM COM COM COM COM COM COM COM 8 KB FLASH 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz POIP POIP POIP PLCC PLCC PLCC TOFP TOFP TOFP POFP POFP POFP POIP POIP POIP POIP POIP POIP PLCC PLCC PLCC PLCC PLCC PLCC TOFP TOFP TOFP TOFP TOFP TOFP POFP POFP POFP POFP POFP POFP CEROIP CERDIP LCC LCC PDIP PDIP POIP PDIP PDIP PDIP PLCC PLCC PLCC PLCC PLCC AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO MIL MIL MIL MIL COM COM COM COM COM COM COM COM COM COM COM 8 8 8 8 B B 8 8 8 8 8 8 8 KB KB KB KB KB KB KB KB KB KB KB KB KB ROMless A P aOC32 F-1 A P BOC32 F-S A P BOC32 F AS BOC32F-1 AS BoC32 F-S A SBOC32 F ATBOC32F-1 AT80C32 F-S ATBOC32 F AV8oC32 F-1 AV8oC32 F-S AV8oC32 F P 80C32 F -25 P 80C32 F-1 P 80C32 F-L P 80C32 F-L P 80C32 F-S P BOC32 F S BOC32 F -25 S BOC32 F-1 S BOC32 F-L S BOC32 F-L S BOC32 F-S S BOC32 F T 80C32 F -25 IT 8OC32 F-1 IT 80C32 F-L IT BOC32 F-L IT 80C32 F-S IT BOC32 F I V 80C32 F -25 I V 80C32 F-1 I V 80C32 F-L I V 80C32 F-L I V 80C32 F-S I V 80C32 F M D 80C32 F -MB M D BOC32 F -MB M R 80C32 F -MB M R 80C32 F -MB P 80C32 F -25 P 80C32 F-1 P 80C32 F-L P BOC32 F-L P BOC32 F-S P BOC32 F S BOC32 F -25 S BOC32 F-1 S BOC32 F-L S BOC32 F-L S80C32 F-S 6-14 B KB FLASH B 8 8 8 B B B B B B B B B B B B 8 8 8 B 8 B B 8 8 8 8 8 8 8 B 8 8 B 8 B B 8 8 8 B B B B B 8 B 8 B KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH Microcontroller Cross-Reference Guide Microcontroller Cross-Reference Guide AT89C52 Microcontroller Detailed Cross-Reference Guide (continued) Matra Atmel Part DescriDtion S 80C32 F T 80C32 F -25 T 80C32 F-1 T 80C32 F-L T SOC32 F-L T 80C32 F-S T 80C32 F V SOC32 F -25 V SOC32 F-1 V 80C32 F-L V SOC32 F-L V SOC32 F-S V SOC32 F A P 80C32-1 A P SOC32-S A P SOC32 AS SOC32-1 AS 80C32-S AS SOC32 AT SOC32-1 AT SOC32-S AT 80C32 A V 80C32-1 A V 80C32-S A V SOC32 I P SOC32 -25 I P 80C32-1 I P 80C32-L I P 80C32-L I P SOC32-S I P SOC32 IS 80C32 -25 IS 80C32-1 IS SOC32-L IS 80C32-L IS 80C32-S IS SOC32 IT 80C32 -25 IT 80C32-1 IT 80C32-L IT SOC32-L IT SOC32-S IT 80C32 I V 80C32 -25 I V 80C32-1 I V SOC32-L I V 80C32-L I V 80C32-S I V 80C32 M 0 80C32 -MB M 0 80C32 -MB M R 80C32 -MB M R 80C32 -MB P 80C32 -25 P 80C32-1 P 80C32-L P 80C32-L P 80C32-S P 80C32 S 80C32 -25 S 80C32-1 S 80C32-L S 80C32-L S 80C32-S S 80C32 AT89C52-20JC AT89C52-24AC AT89C52-20AC AT89L V52-16AC AT89LV52-20AC ATS9C52-20AC AT89C52-20AC AT89C52-24QC AT89C52-20QC ATS9LV52-16QC AT89LV52-20QC AT89C52-20QC AT89C52-20QC ATS9C52-20PA AT89C52-20PA AT89C52-20PA ATS9C52-20JA AT89C52-20JA ATS9C52-20JA AT89C52-20AA AT89C52-20AA AT89C52-20AA AT89C52-20QA ATS9C52-20QA AT89C52-20QA AT89C52-24PI AT89C52-20PI ATS9L V52-16PI AT89LV52-20PI ATS9C52-20PI ATS9C52-20PI ATS9C52-24JI AT89C52-20JI ATS9LV52-16JI ATS9L V52-20JI ATS9C52-20JI ATS9C52-20JI AT89C52-24AI ATS9C52-20AI ATS9LV52-16AI AT89L V52-20AI ATS9C52-20AI ATS9C52-20AI AT89C52-24QI AT89C52-20QI AT89LV52-16QI AT89L V52-20QI AT89C52-20QI AT89C52-20QI ATS9C52-200M /883 AT89C52-200M /883 AT89C52-20LM /883 AT89C52-20LM /883 AT89C52-24PC AT89C52-20PC AT89LV52-16PC AT89L V52-20PC AT89C52-20PC AT89C52-20PC AT89C52-24JC AT89C52-20JC AT89LV52-16JC AT89LV52-20JC AT89C52-20JC AT89C52-20JC 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V,8 BIT MICROCONTROLLER 3 V, S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V,8 BIT MICROCONTROLLER 3 V, S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, S BIT MICROCONTROLLER 3 V, S BIT MICROCONTROLLER S BIT MICROCONTROLLER S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, S BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER S BIT MICROCONTROLLER S BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 8 8 8 S S S 8 S S 8 8 8 8 S 8 8 S S S 8 8 8 8 8 S 8 8 S 8 8 S S 8 S S S 8 8 8 S S 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH KB FLASH 8Deed Pkn TemD 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16 MHz 20 MHz 20 MHz 20 MHz PLCC TQFP TQFP TQFP TQFP TQFP TQFP PQFP PQFP PQFP PQFP PQFP PQFP POIP POIP POIP PLCC PLCC PLCC TQFP TQFP TQFP PQFP PQFP PQFP POIP POIP POIP POIP POIP POIP PLCC PLCC PLCC PLCC PLCC PLCC TQFP TQFP TQFP TQFP TQFP TQFP PQFP PQFP PQFP PQFP PQFP PQFP CEROIP CEROIP LCC LCC POIP POIP POIP POIP POIP POIP PLCC PLCC PLCC PLCC PLCC PLCC COM COM COM COM COM COM COM COM COM COM COM COM COM AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO INO MIL MIL MIL MIL COM COM COM COM COM COM COM COM COM COM COM COM 6-15 AlmEL AT89C52 Microcontroller Detailed Cross-Reference Guide (continued) Matra Atmel Part DescriDtion T 80C32 -25 T 8OC32-1 T8OC32-L T 80C32-L T8OC32-S T80C32 V 80C32 -25 V 80C32-1 V80C32 -L V 80C32-L V80C32 -S V 80C32 AT89C52-24AC AT89C52-20AC AT89LV52-16AC AT89LV52-20AC AT89C52-20AC AT89C52-20AC AT89C52-240C AT89C52-200C AT89LV52-160C AT89LV52-200C AT89C52-200C AT89C52-200C 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 3 V, 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER 8 BIT MICROCONTROLLER SDeed Pka TemD 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz 24 MHz 20 MHz 16MHz 20 MHz 20 MHz 20 MHz TOFP TOFP TOFP TOFP TOFP TOFP POFP POFP PQFP POFP POFP POFP COM COM COM COM COM COM COM COM COM COM COM COM Phil~s Atmel FLASH Part Description ROM less Speed Pka Temp P80C32 EBPN P80C32 EBAA P80C32 EBBB P80C32 EFPN P80C32 EFAA P80C32 EFBB P80C321 BPN P80C321 BAA P80C321 FPN P80C321 FAA AT89C52-20PC AT89C52-2OJC AT89C52-200C AT89C52-20PI AT89C52-20JI AT89C52-24PC AT89C52-24JC AT89C52-24OC AT89C52-24PI AT89C52-24JI 8 8 8 8 8 8 8 8 8 8 BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER 8 8 8 8 8 8 8 8 8 8 KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz POIP PLCC POFP POIP PLCC POIP PLCC POFP POIP PLCC COM COM COM INO INO COM COM COM INO INO AT89C52-20PC AT89C52-2OJC AT89C52-200C AT89C52-20PI AT89C52-2OJI AT89C52-24PC AT89C52-24JC AT89C52-240C AT89C52-24PI AT89C52-24J1 8 8 8 8 8 8 8 8 8 8 BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER 8 8 8 8 8 8 8 8 8 8 KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz POIP PLCC POFP POIP PLCC POIP PLCC POFP POIP PLCC COM COM COM INO INO COM COM COM INO INO AT89C52-20PC AT89C52-2OJC AT89C52-200C AT89C52-20PI AT89C52-2OJI AT89C52-24PC AT89C52-24JC AT89C52-240C AT89C52-24PI AT89C52-24J1 AT89C52-200C AT89C52-20LC AT89C52-2001 AT89C52-20Ll AT89C52-240C AT89C52-24LC AT89C52-2401 AT89C52-24L1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 20 MHz 20 MHz 20 MHz 20 MHz 24 MHz 24 MHz 24 MHz 24 MHz POIP PLCC POFP POIP PLCC POIP PLCC PQFP POIP PLCC CEROIP LCC CEROIP LCC CEROIP LCC CEROIP LCC COM COM COM INO INO COM COM COM INO INO COM COM INO INO COM COM INO INO AT89C52-20PC AT89C52-2OJC AT89C52-20PI AT89C52-20PC AT89C52-2OJC AT89C52-20PC AT89C52-2OJC AT89C52-20PC 8 8 8 8 8 8 8 8 BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER 8 8 8 8 8 8 8 8 KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz POIP PLCC POIP POIP PLCC POIP PLCC POIP COM COM INO COM COM COM COM COM 8 8 8 8 8 8 8 8 8 8 8 8 KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH ROM P80C52 P80C52 P80C52 P80C52 P80C52 P80C52 P80C52 P80C52 P80C52 P80C52 EBPN EBAA EBBB EFPN EFAA EFBB BPN BAA FPN FAA EPROM P87C52 EBPN P87C52 EBAA P87C52 EBBB P87C52 EFPN P87C52 EFAA P87C52 EFBB P87C52BPN P87C52BAA P87C52 FPN P87C52 FAA P87C52 EBFFA P87C52 EBLKA P87C52 EFFFA P87C52 EFLKA P87C521 BFFA P87C521 BLKA P87C521 FFFA P87C521 FLKA ROMlROMless SAB 8032B-P SAB8032B-N SAB 8032B -P-T40/48 SAB 8032B -16-P SAB 8032B -16-N SAB 8032B -20-P SAB 8032B -20-N SAB 8052B-P 6-16 Microcontroller Cross-Reference Guide Microcontroller Cross-Reference Guide AT89C2051(1) Microcontroller Detailed Cross-Reference Guide Soeed Pka Temo FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 16 MHz 16 MHz 16 MHz PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP SOIC SOIC SOIC SOIC SOIC PDIP PDIP COM IND COM IND COM IND COM IND COM IND COM IND AUTO AUTO AUTO KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 16 MHz 16 MHz 16 MHz PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP SOIC PDIP PDIP COM IND COM IND COM IND COM IND AUTO AUTO AUTO 2 2 2 2 2 2 2 2 2 2 2 2 KB KB KB KB KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 24 24 24 24 24 24 24 24 24 24 24 24 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP SOIC SOIC SOIC SOIC COM IND COM IND COM IND COM IND COM IND COM IND 2 2 2 2 2 2 2 2 KB KB KB KB KB KB KB KB FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH 24 24 24 24 24 24 24 24 MHz MHz MHz MHz MHz MHz MHz MHz PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP COM IND COM IND COM IND COM IND Philios/Sianetics Atmel FLASH EPROM Part Descriotion S87C752-1 F28 S87C752-2F28 S87C752-4F28 S87C752-5F28 S87C752-1 N28 S87C752-2N28 S87C752-4N28 S87C752-5N28 S87C752-1 A28 S87C752-2A28 S87C752-4A28 S87C752-5A28 S87C752-6A28 S87C752-6F28 S87C752-6N28 AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI AT89C2051-24SC AT89C2051-24SI AT89C2051-24SC AT89C2051-24SI AT89C2051-16SA AT89C2051-16PA AT89C2051-16PA 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI AT89C2051-16SA AT89C2051-16PA AT89C2051-16PA 8 8 8 8 8 8 8 8 8 8 8 BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER 2 2 2 2 2 2 2 2 2 2 2 BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT MICROCONTROLLER BIT BIT BIT BIT BIT BIT BIT BIT ROM S83C752-1 N28 S83C752-2N28 S83C752-4N28 S83C752-5N28 S83C752-1 A28 S83C752-2A28 S83C752-4A28 S83C752-5A28 S83C752-6A28 S83C752-6F28 S83C752-6N28 EPROM FLASH S87C751-1 F24 S87C751-2F24 S87C751-4F24 S87C751-5F24 S87C751-1N24 S87C751-2N24 S87C751-4N24 S87C751-5N24 S87C751-1 A28 S87C751-2A28 S87C751-4A28 S87C751-5A28 AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI AT89C2051-24SC AT89C2051-24SI AT89C2051-24SC AT89C2051-24SI 8 18 8 8 8 8 8 8 8 8 8 8 AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI AT89C2051-24PC AT89C2051-24PI 8 8 8 8 8 8 8 8 ROM S83C751-1N24 S83C751-2N24 S83C751-4N24 S83C751-5N24 S83C751-1A28 S83C751-2A28 S83C751-4A28 S83C751-5A28 MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER MICROCONTROLLER AlmEl 6-17 6-18 Microcontroller Cross-Reference Guide Microcontroller Product Information General Architecture Microcontroller Data Sheets Microcontroller Application Notes Programmer Support/Development Tools Microcontroller Cross-Reference Miscellaneous Information · AlmEl - - - - - - _ _ _ _ _ _ _ _ _ _ _ _ _ _ Contents Section 7 Package Outlines Package Drawings ........................................................................................................... 7-3 • AIIDEl. 7-1 AlmEL 7-2 Packages Each Atmel data sheet includes an Ordering Information Section which specifies the package types available. This section provides size specifications and outlines for all package types.(1) Package Description 44A 44 Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) .............................................................................. 7-4 40D6 40 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip) ................................................... 7-4 441 44 Lead, Plastic I-Leaded Chip Carrier (PLCC) ........................................... 7-4 44L 44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) ................. 7-4 40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) .......................... 7-5 20P3 20 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) .......................... 7-5 44Q 44 Lead, Plastic Gull Wing Quad Flat Package (PQFP) ............................... 7-5 20S 20 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) ................. 7-5 See Page Package Drawings I Note: 1. Dimensions shown do not include lead plating or mold flash. AIIDEL OS02A 7-3 44A, 44 Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Inches and (Millimeters) 40D6, 40 Lead, 0.600" Wide, Non-Windowed, Cermic Dual Inline Package (Cerdip) Dimensions in Inches and (Millimeters) MIL-STD-1835 D-5 CONFIG A L 2.09(53.1~ 00 u·r -:L'M 2 04 . (51.8) PlNIID- L J 0.BO(0.031)B (f 7' 0.3010.012) ! f 0.1710.007) 0.40(0.016) l 10.10(0.39~ 9.9010.386) I I--- 1.900 148.26) REF .570 (14.5) --.l.098 (2.49) I- --I ---I r- MAX. I I .005 \:ll~~) .22~72) s~~ mwww~~ 'Wt~2) I JL .200(5.~8 r- .125(3.18 r 1.20(0.047) MAX ---.--l 0.1310.005)~.n ~mmm~~ I 0 L 0.7510.029) 0.1010.0~ t I-- .110(2.79) .090 (2.29) I: .590 (15.01, I. JEDEC OUTLINE MO-047 AC 0 15REF c:J~-" .015 !.381LF .008 .203)- 44J, 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) I :: --=hI ff!= 0.5010.020) 0.05{0.OO2) .015(.381) .023(.584) .014 (.356) 065(165) ·040 (1·02) .. .620 (l5.~ a 1 .700 117.8) MAl( 44L, 44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) Dimensions in Inches and (Millimeters)* MIL-STD-1835 C-5 .640(16.3~1 [ ~.~1-j .045(1.14)X30.45 ~'::'ot~il". \0 '1)TII:~:\:l:: .0321.813U .650 (16. ) ~. f .050 (1.27)1VP lJ~211.53 lU·:!::·:F rg .026 1. 6 6 O ) . L L I I . .500(12.7)REFSQ ~~O 116.0) LtF1, .6r:I6~ *~ .~5 \2.41 .051.91) .120 (3 05) .09012.29) .180(4.57) .165(4.19) I . - -( I ~40) .045I1.14Y-- Ll !!. .600 112.71 BSC INDEX CORNER ~5,).45 • .015 (.38ff .012 (.30 IUS .OO71.17tr' L~1.029(.737) i .021 (.533) ~ .040 (1.02) X 4s (3X) .050 (1.27) .500 (12.7) REF I-L .gs5(2.16) • 65 (1.65) 'Ceramic lid standard unless specified. 7-4 Packages .08512.16) .Oag(2.03) .05 11.50) PIN 1 lfj:~~!::el MAX{3X) .108 (2.74) -1~ LB_~:~e·O) ~~ ~~-...f.0221.559)X45 t .013 l r Packages 40P6, 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) 20P3, 20 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) ,0- -00I--- L ~.07 \S2.6~ 1'",'1 ~" _.04 S1.8:" ooo=r~imi .530(13.5) -.-l I f--- f- .090 (2.29) I I .OOS UI~~) -I -----J 1.900 148.261 R" .22~S9) SEATING PlANE ~ JL ,065 (l,65) .041 (1.04) ,110 (2.79) ,090 (2.29) f-- I ,.- j! I r-- .06S(1.65) ,01S(,381) ,022(.559) ,014 (,3S6) III --I ---j ,900122,861 ,210 (5,33) ,090 (2,29) MAX, ~1w~Wt JL '150(3~8 I ~ I ,005 (.127) " ,015 (,381) MIN ,022 (,559) ,014 (,356 ,115 (2.9 J.lQJY9) ,070 (1.781 ,045 (l ,131 :090 (2:291 ,630 (l6.~ ,S90 (1S,Ol., I i----I '~g5 (8,26) I I ' 0 (7,621 )~ fSREF ,....-=---j cj.-/ ,012 (.30S1_ ,OOB (,203) II-- MAX. [W ~W=t ~~ .'ml~rifd' , I- 1'060(26'~ ~ ;;::j .-/ f5REF .690 (l7,S) I ,610 (1S.5)1 .014 (,356.L ,008 (,203), I. . 1.430 (10,92) MAX 'Controllin dimension: millime! s 44Q, 44 Lead, Plastic Gull Wing Quad Flat Package (PQFP) Dimensions in Inches and (Millimeters) 208, 20 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOle) Dimensions in Inches and (Millimeters) I- ,020 (,508~ ,013 (,330) " PINllD QOU 1.7) ---'-:lO) ~ j 0 --I ~.- ,291 (7,39) ,393 (9,98) ,050 (1,271 BSe r-'~~M 1 J---.1 10,1010,39~ 0,17(0,007) ~ 0,13(0,00S} ~J !0 ~ L. 9,90(O,386) r . 2,45(O.096} MAX m~~~ --r:! • ,105 (2,67) ,092 (2,34) ,012 (.30sil ,003 (,076) m~mm~~ 0,95(0,037) 0.65(0.025} [ 0,25{0,Q10} MIN LjJff(===BII\,~ T~ REF HI-=T .013 (,330) ,009(,229) ,035(0,889 ,015 (,381) 7-5 7-6 Packages - - - - - - - - - - - - - - Microcontroller Product Information General Architecture Microcontroller Data Sheets Microcontroller Application Notes Programmer Support/Development Tools Microcontroller Cross-Reference Package Outlines Miscellaneous Information Contents Section 8 Miscellaneous Atmel Atmel Atmel Atmel Atmel Product Line Guide ................................................................................................ 8-3 Sales Offices .......................................................................................................... 8-9 North American Distributors ................................................................................... 8-11 North American Representatives ........................................................................... 8-17 International Representatives ................................................................................ 8-19 II 8·1 8-2 Atmel Product Line Guide Programmable Logic Devices Part Number Packages Description Speeds Availability Flash-Based ATF16VBB ATF16VBBQ,BQL ATF16V8C ATF16V8CZ ATF20V8B ATF20V8BQ,BQL ATF22Vl0B ATF22Vl0BL,BQ,BQL ATF22Vl0BL,BQ,BQL ATF1500,L 7.5-25 ns 10-25 ns 5-7ns 10-15ns 7.5-25 ns 10-25 ns 7.5-25 ns 10-25 ns 10-25 ns 7.5-15 ns B FFs, B 1/0 Pins, Standard Power B FFs, 8 1/0 Pins, Quarter Power, Low Power 8 FFs, 8 1/0 Pins, Standard Power 8 FFs, 8 1/0 Pins, Zero Power 8 FFs, 8 1/0 Pins, Standard Power 8 FFs, 8 1/0 Pins, Quarter Power, Low Power 10 FFs, 10 1/0 Pins, Standard Power 10 FFs, 10110 Pins, Quarter Power, Low Power 10 FFs, 10110 Pins, Quarter Power, Low Power 32 FFs, 32 1/0 Pins, Standard Power, Low Power Now Now 4Q-95 4Q-95 Now Now Now Now Now Now 20-Pin 20-Pin 24-Pin, 28-Pin 24-Pin, 28-Pin 40-Pin, 44-Pin 10-15 ns 15-25 ns 20-30 ns 10-15 ns 15-20 ns 8 FFs, 8 110 Pins, Low Voltage 8 FFs, 8 110 Pins, Low Voltage, Zero Power 10 FFs, 10 110 Pins, Standard & Low Power 20 FFs, 10 110 Pins, Standard & Low Power 48 FFs, 24 110 Pins, Standard & Low Power 4Q-95 4Q-95 24-Pin, 28-Pin 24-Pin, 28-Pin 24-Pin, 28-Pin 24-Pin, 28-Pin 24-Pin, 28-Pin 40-Pin, 44-Pin 15-30 ns 7.5-10 ns 20-30 ns 7.5-25 ns 15-25 ns 25-35 ns 12-20 ns 20-25 ns 25-35 ns 25-35 ns 10 FFs, 10 110 Pins, Standard & Low Power 10 FFs, 10 110 Pins, Standard Power 20 FFs, 10 110 Pins, Standard & Low Power 20 FFs, 10 110 Pins, Standard & Low Power 20 FFs, 10 110 Pins, Quarter Power, Low Power 48 FFs, 24 110 Pins, Standard & Low Power 48 FFs, 24 110 Pins, Standard & Low Power 48 FFs, 24 110 Pins, Quarter Power, Low Power 128 FFs, 52 110 Pins, Standard & Low Power 128 FFs, 52 110 Pins, Standard & Low Power Now Now Now Now 4Q95 Now Now Now Now Now 24-Pin, 24-Pin, 24-Pin, 24-Pin, 24-Pin, 20-Pin 20-Pin 20-Pin 20-Pin 28-Pin 28-Pin 28-Pin 28-Pin 28-Pin 44-Pin LowVollage ATF16LV8C ATF16LV8CZ AT22LV10,L ATLV750B,BL ATLV2500B,BL Now 4Q-95 4Q-95 5-Voll, EPROM-Based AT22Vl0,L AT22Vl0B ATV750,L ATV750B,BL ATV750BQ,BQL ATV2500H,L ATV2500B,BL ATV2500BQ,BQL ATV5000,L ATV5100,L 44-Pin 40-Pin, 44-Pin 68-Pin 68-Pin Cache Logic™FPGAs Part Number AT6002 AT6003 AT6005 AT6010 Registers Usable Gates Frequency 1.024 1,600 3,136 6,400 2K-4K 3K-6K 5K-l0K 10K-20K 250 MHz 250 MHz 250 MHz 250 MHz 96 110 Pins, 5V, Very Low Power 120 110 Pins, 5V, Very Low Power 108 110 Pins, 5V, Very Low Power 204110 Pins, 5V, Very Low Power Description Now Now Now Now Availability 1.024 1,600 3,136 6,400 2K-4K 3K-6K 5K-l0K 10K-20K 250 MHz 250 MHz 250 MHz 250 MHz 96110 Pins, 3V, Very Low Power 120110 Pins, 3V, Very Low Power 108110 Pins, 3V, Very Low Power 204110 Pins, 3V, Very Low Power 4Q-95 4Q-95 Now lQ-96 DeSCription Availability Low Voltage AT6002LV AT6003LV AT6005LV AT6010LV FPGA Serial Configuration E2 PROMS Part Number AT17C65 AT17C128· AT17C256 Memory Size 65,536 x 1 131,072 xl 262,144 x 1 65K FPGA Configuration E2PROM 128K FPGA Configuration E2PROM 256K FPGA Configuration E2PROM Now Now 4Q-95 II 050lA AlmEl 8-3 System Serial Configuration E2 PROMS art Number Memory Size AT34C64 AT34CI28 AT34C256 65,536 x 1 131,072 x 1 262,144 x 1 Descnptlon 64K System Configuration E2PROM 128K System Configuration E2 PROM 256K System Configuration E2PROM Availability 40-95 40-95 10-96 Gate Arrays Part Number Gates ATL60 Series ATL80 Series 4K1120K 2K-600K ATLV Series 2K-35K Description 0.6-Micron CMOS Gate Array, 3.3-Volt & 5.D-Volt Operation, 16 Versions with Various Pin & Gate Counts 0.8-Micron CMOS Gate Array, 3.3-Volt & 5.0-Volt Operation, 12 Versions with Various Pin & Gate Counts 1.0-Micron CMOS Gate Array, 1.0-Volt & 3.3-Volt Operation, 8 Unde~ayers with Various Pin & Gate Counts Availability Now Now Now Logic Part Number AT40281 AT40283 AT40285 AT40391B AT40392 AT40410 AT40493 AT40495 Speeds 16-40 MHz 16-33 MHz 16-40 MHz 25-40 MHz 25-50 MHz 25-50 MHz 25-50 MHz 25-50 MHz • , Descripllon 80386SX PC/AT Core Logic Controller, with Posted-Write Cache 80386SX PC/AT Core Logic Controller 80386SXl486SLC/486SLC2 PCIAT Core Logic Controller 80386DX PC/AT System & Cache Controller 80386DX PC/AT Memory Controller ISAlPCINL PC/AT Core Logic Chipset 80486 PCIAT System & Cache Controller 80486 PCIAT System & Cache Controller Availability Now Now Now Now Now Now Now Now Secure Memory ICs Part Number AT88SC10l AT88SC102 AT88SC103 AT88SC200 RFIDASICs 8-4 Memory Size 1024 x 1 1024 x 1 1536 x 1 2048 x 1 Up to 16Kx 1 Description E2PROM E2PROM E2PROM E2PROM 1K Serial with Security, 1 Memory Zone, 1024 Bits lK Serial with Security, 2 Memory Zones, 512 Bits Each lK Serial with Security, 3 Memory Zones, 512 Bits Each with Gate Array 2K Serial Analog, Digital & Memory on Single-Chip ASIC Atmel Product Line Guide Availability Now Now Now Now Now Atmel Product Line Guide Flash PEROMs Organization Part Number Battery-Vottage™ Speeds DescriptIOn Availability (2.7V to 3.6V) AT29BV010A AT29BV020 AT29BV040A 128Kx 8 256K x 8 512K x 8 200-350 ns 250-350 ns 250-350 ns 1-Mbit. 2.7-Volt Read and 2.7-Volt Write Flash PEROM 2-Mbit, 2.7-Volt Read and 2.7-Volt Write Flash PEROM 4-Mbit, 2.7-Volt Read and 2.7-Volt Write Flash PEROM Now 32Kx 8 64Kx8 128K x 8 64Kx 16 256K x 8 512K x 8 150-250 ns 200-250 ns 200-250 ns 150-250 ns 200-250 ns 200-250 ns 256K, 3-Volt Read and 3-Volt Write Flash PEROM 512K, 3-Volt Read and 3-Volt Write Flash PEROM 1-Mbit, 3-Volt Read and 3-Volt Write Flash PEROM 1-Mbit, 3-Volt Read and 3-Volt Write Flash PEROM 2-Mbit, 3-Volt Read and 3-Volt Write Flash PEROM 4-Mbit, 3-Volt Read and 3-Volt Write Flash PEROM Now Now Now Now Now Now 32Kx8 32Kx 8 64Kx8 64K x 16 128K x 8 256Kx 8 512Kx 8 70-250 ns 70-250 ns 70-200 ns 70-200 ns 70-200 ns 100-200 ns 120-250 ns 256K, 5-Volt Read and 5-Volt Write Flash PEROM 256K, 5-Volt Read and 5-Volt Wilte Flash PEROM 512K, 5-Volt Read and 5-Volt Wilte Flash PEROM 1-Mbit, 5-Volt Read and 5-Volt Write Flash PEROM 1-Mbit, 5-Volt Read and 5-Volt Write Flash PEROM 2-Mbit, 5-Volt Read and 5-Volt Write Flash PEROM 4-Mbit, 5-Volt Read and 5-Volt Write Flash PEROM Now Now Now Now Now Now Now Now Now Low Voltage (3V to 3.6V) AT29LV256 AT29LV512 AT29LV010A AT29LV1024 AT29LV020 AT29LV040A Standard Voltage (5V) AT29C256 AT29C257 AT29C512 AT29C1024 AT29C010A AT29C020 AT29C040A Part Number AT24C01 AT24C21 AT24C01A AT24C02 AT24C04 AT24C08 AT24C16 AT24C164 AT24C32 AT24C64 AT25C01 OrganizatIOn 128x8 128x8 128x8 256x8 512x8 1024 x8 2048 x8 2048 x8 4096 x 8 8192 x 8 128 x8 256 x8 512 x8 128x8 256 x8 512x8 64 x 16/128 x 8 64x 16 128x16/256x8 AT25C02 AT25C04 AT25010 AT25020 AT25040 AT93C46 AT93C46A AT93C56 AT93C57 AT93C66 AT59C11 AT59C22 128x16/256x8 256 x 16/512x8 64x16/128x8 128x 16/256x8 AT59C13 256x16/512x8 V 1.8,2.5,2.7,5.0 V 2.5 - 5.0 V 1.8, 2.5, 2.7, 5.0 V 1.8,2.5,2.7,5.0 V 1.8,2.5,2.7,5.0 V 1.8,2.5,2.7,5.0 V 1.8, 2.5, 2.7, 5.0 V 1.8,2.5,2.7,5.0 V 1.8,2.5,2.7, 5.0 V 1.8,2.5,2.7,5.0 V 1.8, 2.7, 5.0 V 1.8, 2.7, 5.0 V 1.8, 2.7, 5.0 V 1.8,2.7,5.0 V 1.8,2.7,5.0 V 1.8,2.7,5.0 V 1.8,2.5,2.7,5.0 V 1.8,2.5,2.7,5.0 V 2.5,2.7,5.0 V 2.5, 2.7, 5.0 V 2.5, 2.7, 5.0 V 2.5,2.7,5.0 V 2.5,2.7,5.0 V 2.5,2.7,5.0 V Description 1K, 2-Wire Bus Serial E2PROM, Non-Cascadable 1K, 2-Wire Bus Serial E2 PROM, Dual Mode, Plug & Play Operation 1K, 2-Wire Bus Serial E2PROM 2K, 2-Wire Bus Serial E2 PROM 4K, 2-Wire Bus Serial E2 PROM 8K, 2-Wire Bus Serial E2 PROM 16K, 2-Wire Bus Serial E2 PROM 16K, 2-Wire Bus Serial E2 PROM with Cascadable Feature 32K, 2-Wire Bus Serial E2 PROM with Cascadable Feature 64K, 2-Wire Bus Serial E2 PROM with Cascadable Feature 1K, SPI Bus Serial E2 PROM, Supports SPI Mode 1 2K, SPI Bus Serial E2 PROM, Supports SPI Mode 1 4K, SPI Bus Serial E2 PROM, Supports SPI Mode 1 1K, SPI Bus Serial E2 PROM, Supports SPI Mode 0 and 3 2K, SPI Bus Serial E2 PROM, Supports SPI Mode 0 and 3 4K, SPI Bus Serial E2 PROM, Supports SPI Mode 0 and 3 1K, 3-Wire Bus Serial E2 PROM 1K, 3-Wire Bus Serial E2 PROM 2K, 3-Wire Bus Serial E2 PROM 2K, 3-Wire Bus Serial E2 PROM with Special Address 4K, 3-Wire Bus Serial E2 PROM 1K, 4-Wire Bus Serial E2 PROM 2K, 4-Wire Bus Serial E2 PROM 4K, 4-Wire Bus Serial E2 PROM Availability Now Now Now Now Now Now Now Now Now Now Consult Factory Consult Factory Consult Factory Now Now Now Now Now Now Now Now Now Now Now II AIIDEL 8-5 Part Number Organization Description Speeds Availability High Speed AT2SHC64B AT2SHC256 AT2SHC256E AT2SHC256F SKxS 32Kx S 32Kx S 32K xS 55-120 ns 70-120 ns 70-120 ns 70-120 ns 64K E2PROM with 64-Byte Page, Software Data Protection 256K E2PROM with 64-Byte Page & Software Data Protection 256K E2PROM with Extended Endurance, Standard & Low Power 256K E2PROM with Fast Write, Standard & Low Power Now Now Now Now Battery-Voltage™ (2.7V to 3.6V) AT2SBV16 AT2SBV64 2KxS 8KxS 250-300 ns 16K E2PROM, 2.7-Volt 300 ns 64K E2PROM, 2.7-Volt Now Now 200-300 ns 64K E2PROM with 64-Byte Page & Software Data Protection, 3.0·Volt 200-300 ns 256K E2PROM with 64-Byte Page & Software Data Protection, 3.0-Volt 200-250 ns 1-Mbit E2PROM with 12S-Byte Page & Software Data Protection, 3.0-Volt Now Now Now 150-250 ns 16K E2PROM 150-250 ns 16K E2PROM 150-250 ns 16K E2PROM 150-250 ns 16K E2PROM 120-350 ns 64K E2PROM 120-350 ns 64K E2PROM with Ready/Busy Now Now Now with Ready/Busy & Extended Endurance & Fast Write Now with Extended Endurance & Fast Write Now Now Now Low Voltage (3.0V to 3.6V) AT2SLV64B AT2SLV256 AT2SLV010 8Kx S 32KxS 12SK x S Standard Voltage (5V) AT2SC16 AT2SC16E AT2SC17 2Kx S 2Kx S 2Kx 8 AT28C17E 2Kx8 AT28C64 AT2SC64E AT2SC64X 8K x 8 SKxS SKx8 AT2SC64B AT2SC256 AT2SC256E AT2SC256F AT2SC010 AT28C010E SKx 8 32Kx 8 32Kx S 32Kx8 128K x 8 128K x 8 AT28C040 512K x 8 with Extended Endurance & Fast Write 150-450 ns 64K E2PROM without Ready-Busy 64K E2PROM with 64-Byte Page & Software Data Protection 256K E2PROM with 64-Byte Page & Software Data Protection 256K E2PROM with Extended Endurance 256K E2PROM with Fast Write & Software Data Protection 1-Mbit E2PROM with 128-Byte Page & Software Data Protection 1-Mbit E2PROM with 128-Byte Page & Extended Endurance & Software Data Protection 150-250 ns 4-Mbit E2PROM with 256-Byte Page & Software Data Protection 150-250 ns 150-350 ns 150-350 ns 150-350 ns 120-250 ns 120-250 ns Now Now Now Now Now Now Now Flash Memory Cards Part Number AT5FC001 AT5FC002 AT5FC004 AT5FC008 8-6 Organization 1 Mbyte 2 Mbyte 4 Mbyte 8 Mbyte V 5.0V 5.0 V 5.0 V 5.0 V Description PCMCIA PCMCIA PCMCIA PCMCIA Atmel Product Line Guide Compatible Compatible Compatible Compatible Flash Flash Flash Flash Memory Memory Memory Memory Card Card Card Card Availability Now Now Now Now Atmel Product Line Guide EPROMs Part Number Organization Speeds Description Availability Battery-Voltage TM (2.7V) AT27BV010 AT27BV020 AT27BV040 l-Mbit, 2.7-Voltto 3.6-Volt EPROM 2-Mbit, 2.7-Volllo 3.6-Voll EPROM 4-Mbil, 2.7-Vol! 10 3.6-Voll EPROM Now Now Now 150-250 ns 150-250 ns 150-250 ns 150-250 ns 150-300 ns 200·300 ns 200-300 ns 250-300 ns 256K 3-Vol! EPROM 512K 3-Vol! EPROM l-Mbi!, 3-Vol! EPROM 1-Mbil, 3-Vol! EPROM 2-Mbi!, 3-Vol! EPROM 4-Mbil, 3-Voll EPROM 4·Mbil, 3-Voll EPROM 8-Mbil, 3-Voll EPROM Now Now Now Now Now Now Now 40-96 256KEPROM 512KEPROM 1-Mbi! EPROM 1-Mbi! EPROM, Standard & Low Power 2-Mbi! EPROM 4-Mbi! EPROM 4-Mbil EPROM 8-Mbi! EPROM Now Now 128Kx 8 256Kx 8 512Kx 8 90·150 ns 120-150 ns 32Kx 8 64Kx8 64K x 16 128K x 8 256Kx 8 256K x 16 512Kx 8 1024Kx8 32Kx8 64Kx8 150ns Low Voltage (3 to 5.5V) AT27LV256R AT27LV512R AT27LV1024 AT27LV010 AT27LV020 AT27LV4096 AT27LV040 AT27LV080 Standard Voltage (5V) AT27C256R AT27C512R AT27Cl024 AT27C010,L AT27C020 AT27C4096 64Kx 16 128K x 8 256Kx8 256Kx 16 45-200 ns 45-200 ns 55-200 ns 45-200 ns 70-200 ns 85-200 ns AT27C040 AT27C080 512Kx8 1024Kx8 80·200 ns 100-200ns Now Now Now Now Now Now II AIIDEL 8-7 8-8 Atmel Product Line Guide Atmel Sales Offices North American Sales Offices International Sales Offices JAPAN NORTHWEST UNITED KINGDOM 2125 O'Nel Drive San Jose, CA 95131 TEL (408) 436-4270 FAX (408) 436-4314 Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GUI53YL England TEL (44) 1276-686677 FAX (44) 1276-686697 Atmel Japan K.K. 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Dundee Road, Suite 310 Palatine,IL 60067-8319 TEL (708) 202-1900 FAX (708) 202-1985 MILGRAY/KANSAS CITY 6400 Glenwood, Suite 313 Overland Park, KS 66202 TEL (913) 236-8800 FAX (913) 384-6825 Maryland ALL AMERICAN 14636 Rothged Drive Rockville, MD 20850 TEL (800) 426-0420 FAX (301) 251-8574 MARSHALL INDUSTRIES 9130B Guilford Road Columbia, MD 21046-1803 TEL (301) 470-2800 FAX (301) 622-0451 MILGRAYIWASHINGTON 6460 Dobbin Road, Suite D Columbia, MD 21045 TEL (410) 730-6119 FAX (410) 730-8940 PIONEER STANDARD ELECTRONICS 9100 Gaither Road Gaithersburg, MD 20877 TEL (301) 921-0660 FAX (301) 921-4255 15810 Gaither Road Gaithersburg, MD 20877 TEL (301) 921-3822 FAX (301) 921-3858 Massachusetts ALL AMERICAN 19A Crosby Drive Bedford, MA 01730 TEL (617) 275-8888 FAX (617) 275-1982 ARROW/SCHWEBER ELECTRONICS 25 Upton Drive Wilmington, MA 01887 TEL (508) 658-0900 FAX (508) 694-1754 INSIGHT ELECTRONICS 55 Cambridge Street, Suite 301 Burlington, MA 01803 TEL (617) 270-9400 FAX (617) 270-3279 II 8·13 AIIDIL MARSHALL INDUSTRIES 33 Upton Drive Wilmington, MA 01887 TEL (508) 658-0810 FAX (508) 658-7608 MILGRAY/NEW ENGLAND Ballardvale Park 187 Ballardvale Street Wilmington, MA 01887 TEL (508) 657-5900 FAX (508) 658-7989 PIONEER STANDARD ELECTRONICS 44 Hartwell Avenue Lexington, MA 02173 TEL (617) 861-9200 FAX (617) 863-1547 ZEUS ELECTRONICS 25 Upton Drive Wilmington, MA 01887 TEL (508) 658-4776 (800) 52-HI-REL FAX (508) 694-2199 Michigan ARROW SCHWEBER ELECTRONICS 44720 Helm Street Plymouth, MI 48170 TEL (313) 455-0850 FAX (313) 455-6656 MARSHALL INDUSTRIES 31067 Schoolcraft Livonia, MI 48150 TEL (313) 525-5850 FAX (313) 525-5855 PIONEER STANDARD ELECTRONICS 4467 Byron Center Avenue Wyoming, MI 49509 TEL (616) 534-6074 FAX (616) 534-3922 44190 Plymouth Oaks Drive Plymouth, MI 48270 TEL (313) 416-2157 FAX (313) 416-2415 Minnesota 10120 A West 76th Street Eden Prairie, MN 55344 TEL (612) 946-4800 INSIGHT ELECTRONICS 5353 Gamble Drive Suite 330 SI. Louis Park, MN 55416 TEL (612) 525-9999 FAX (612) 525-9998 MILGRAY/DELAWARE VALLEY 523 Fellowship Road Suite 275 Mt. Laurel, NJ 08054 TEL (609) 778-1300 FAX (609) 778-7669 MARSHALL INDUSTRIES 14800 28th Avenue, North Suite 175 Minneapolis, MN 55447 TEL (612) 559-2211 FAX (612) 559-8321 MILGRAY/NEW JERSEY 3799 Route 46 East Suite 303 Parsippany, NJ 07054 TEL (201) 335-\766 FAX (201) 335-2110 PIONEER STANDARD ELECTRONICS 7625 Golden Triangle Eden Prairie, MN 55344 TEL (612) 944-3355 FAX (612) 944-3794 Missouri PIONEER STANDARD ELECTRONICS 14A Madison Road Fairfield, NJ 07006 TEL (201) 575-3510 FAX (201) 575-3454 ARROW/SCHWEBER ELECTRONICS New York 2380 Schuetz Road St. Louis, MO 63146 TEL (314) 567-6888 FAX (314) 567-1164 ALL AMERICAN SEMICONDUCTOR 275B Marcus Boulevard Hauppauge, NY 11788 TEL (516) 981-3935 FAX (516) 434-9394 MARSHALL INDUSTRIES 514 Earthcity Expressway Suite 131 Earthcity, MO 63045 TEL (314) 770-1749 FAX (314) 770-1486 PIONEER STANDARD ELECTRONICS III West Port Plaza Suite 625 SI. Louis, MO 63146 TEL (314) 542-3077 FAX (314) 542-3078 New Jersey ARROW/SCHWEBER ELECTRONICS 43 Route 46 East Pine Brook, NJ 07058 TEL (20 I) 227-7880 FAX (201) 227-2064 ALL AMERICAN SEMICONDUCTOR 7716 Golden Triangle Drive Eden Prairie, MN 55344 TEL (612) 944-2151 FAX (612) 944-9803 4 East Stow Road, Unit 11 Marlton, NJ 08053 TEL (609) 596-8000 FAX (609) 596-9632 ARROW/SCHWEBER ELECTRONICS MARSHALL INDUSTRIES 10100 Viking Drive, Suite 100 Eden Prairie, MN 55344 TEL (612) 941-5280 FAX (612) 941-9405 101 Fairfield Road Fairfield, NJ 07004 TEL (201) 882-0320 FAX (201) 882-0095 8-14 158 Gaither Drive MI. Laurel, NJ 08054 TEL (609) 234-9100 FAX (609) 778-1819 North American Distributors ARROW/SCHWEBER ELECTRONICS 120 Commerce Street Hauppauge, NY 11788 TEL (516) 231-1000 FAX (516) 231-1072 3375 Brighton-Henrielts Townline Road Rochester, NY 14623 TEL (716) 427-0300 FAX (716) 427-0735 MARSHALL INDUSTRIES 100 Marshall Drive Endicott, NY 13760 TEL (607) 785-2345 FAX (607) 785-5546 1250 Scottsville Road Rochester, NY 14624 TEL (716) 235-7620 FAX (716) 235-0052 3505 Veterans Memorial Highway Suite L. Ronkonkoma, NY 11779 TEL (516) 737-9300 FAX (516) 737 9580 North American Distributors MILGRAY/NEW YORK PIONEER STANDARD ELECTRONICS 77 Schmitt Boulevard Farmingdale, NY 11735 TEL (516) 391-3000 FAX (516) 420-0685 2200 Gateway Center Blvd. Suite 215 Morrisville, NC 27560 TEL (919) 460-1530 FAX (919) 460-1540 MILGRAY/UPSTATE NEW YORK One Corporate Place, Suite 200 1170 Pittsford Victor Road Pittsford, NY 14534 TEL (716) 381-9700 FAX (716) 381-9495 PIONEER STANDARD ELECTRONICS 1249 Upper Front, Suite 201 Binghamton, NY 13901 TEL (607) 722-9300 FAX (607) 722-9562 840 Fairport Park Fairport, NY 14450 TEL (716) 381-7070 FAX (716) 381-5955 One Penn Plaza #2032 New York, NY 10119 TEL (212) 631-4700 FAX (212) 971-0374 60 Crossways Park West Woodbury, NY 11797 TEL (516) 921-8700 FAX (516) 921-2143 ZEUS ELECTRONICS 100 Midland Avenue Port Chester, NY 10573 TEL (914) 937-7400 (800) 52-HI-REL FAX (914) 937-2553 North Carolina ARROW/SCHWEBER ELECTRONICS ARROW/SCHWEBER ELECTRONICS 12111 E. 51st Street, Suite 101 Tulsa, OK 74146 TEL (918) 252-7537 FAX (918) 254-0917 8200 Washington Village Dr. Suite A Centerville, OH 45458 TEL (513) 435-5563 FAX (513) 435-2049 6573 E Cochran Road Solon, OH 44139 TEL (216) 248-3990 FAX (216) 248-1106 INSIGHT ELECTRONICS 9700 Rockside Road Suite 105 Valley View, OH 44125 TEL (216) 487-2522 FAX (216) 487-3412 MARSHALL INDUSTRIES· 30700 Bainbridge Road, Unit A Solon,OH 44139 TEL (216) 248-1788 FAX (216) 248-2312 3520 Park Center Drive Dayton,OH 45414 TEL (513) 898-4480 FAX (513) 898-9363 MILGRAY/CLEVELAND 6155 Rockside Road, Suite 206 Cleveland,OH 44131 TEL (216) 447-1520 FAX (216) 447-1761 ARROW/SCHWEBER ELECTRONICS PIONEER STANDARD ELECTRONICS 2385 Edison Blvd. Twinsburg, OH 44087 TEL (216) 487-5500 FAX (216) 487-0256 MARSHALL INDUSTRIES 4800 East 131st Street C1eveland,OH 44105 TEL (216) 587-3600 FAX (216) 587-3906 MILGRAY/RALEIGH 2925 Huntieigh Drive Suite 101 Raleigh,NC 27604 TEL (919) 790-8094 FAX (919) 872-8851 Oklahoma Ohio 5240 Greens Dairy Road Raleigh, NC 27604 TEL (919) 876-3132 FAX (919) 878-9517 5224 Greens Dairy Road Raleigh, NC 27604 TEL (919) 878-9882 FAX (919) 872-2431 100 Old. Wilson Bridge Road Suite 105 Worthington,OH 43085 TEL (614) 848-4854 FAX (614) 848-4889 4433 Interpoint Boulevard Dayton, OH 45424 TEL (513) 236-9900 FAX (513) 236-8133 PIONEER STANDARD ELECTRONICS 9717 E. 42nd Street, Suite 105 Tulsa, OK 74146 TEL (918) 665-7840 FAX (918) 665-1891 Oregon ALMACIARROW ELECTRONICS 1885 N.W. 169th Place Beaverton, OR 97006 TEL (503) 629-8090 FAX (503) 645-0611 ALL AMERICANIPORTLAND 1815 N.W. 169th Place Suite 6025 Beaverton, OR 97006 TEL (800) 531-3334 FAX (503) 531-3695 INSIGHT ELECTRONICS 8705 S.W. Nimbus Avenue Suite 200 Beaverton, OR 97005 TEL (503) 644-3300 FAX (503) 641-4530 MARSHALL INDUSTRIES 9705 S.W. Gemini Drive Beaverton, OR 97005 TEL (503) 644-5050 FAX (503) 646-8256 MILGRAY/OREGON 8705 S.W. Nimbus Ave., Suite 260 Beaverton, OR 97008 TEL (503) 626-4040 FAX (503) 641-0650 PIONEER TECHNOLOGIES GROUP 8905 Southwest Nimbus Suite 160 Beaverton, OR 97008 TEL 503-626-7300 FAX 503-626-5300 8-15 II Pennsylvania ARROW/SCHWEBER ELECTRONICS 2681 Mosside Blvd., Suite 204 Monroeville, PA 15146 TEL (412) 856-9490 FAX (412) 856-9507 PIONEER STANDARD ELECTRONICS 500 Enterprise Road Horsham, PA 19044 TEL (215) 674-4000 FAX (215) 674-3107 259 Kappa Dri ve Pittsburgh, PA 15238 TEL (412) 782-2300 FAX (412) 963-8255 Tennessee 19416 Park Row, Suite 190 Westgate Center, Bldg. B Houston, TX 77084 TEL (713) 647-6868 FAX (713) 492-8722 INSIGHT ELECTRONICS, INC. 1778 Plano Road, Suite 320 Richardson, TX 75081 TEL (214) 783-0800 FAX (214) 680-2402 11500 Metric Boulevard Suite 215 Austin, TX 78758 TEL (512) 719-3090 FAX (512) 719-3091 3865 South Perkins Road Memphis, TN 38118 10777 Westheimer, Suite 1100 Houston, TX 77042 TEL (713) 260-9614 FAX (713) 260-9602 Texas MARSHALL INDUSTRIES ALL AMERICAN SEMICONDUCTOR 8504 Cross Park Drive Austin, TX 79764 TEL (512) 837-1991' FAX (512) 832-9810 ARROW ELECTRONICS 11210 Steeplecrest, Suite 206 Houston, TX 77065 TEL (713) 955-1993 FAX (713) 955-2215 ALL AMERICAN/DALLAS 1771 International Parkway Suite 101 Richardson, TX 75081 TEL (800) 541-1435 FAX (214) 437-0353 AMIGA SALES & MARKETING C/O JAN DEVICES 12342 Hunters Chase Blvd. Suite 3127 Austin, TX 78729 TEL (818) 757-2005 FAX (818) 708-7436 ARROW/SCHWEBER ELECTRONICS Braker Center III, Bldg. MI 11500 Metric Blvd., Suite 160 Austin, TX 78758 TEL (512) 835-4180 FAX (512) 832-9875 3220 Commander Drive Carrollton, TX 75006 TEL (214) 380-6464 FAX (214) 248-7208 Corporate Square Tech Center III 1551 North Glenville Drive Richardson, TX 75081 TEL (214) 705-0600 FAX (214) 705-0675 10681 Haddington Drive Suite 160 Houston, TX 77043 TEL (713) 467-1666 FAX (713) 467-9805 1826-D Kramer Lane Austin, TX 78758 TEL (512) 835-4000 FAX (512) 835-9829 13765 Beta Road Dallas, TX 75244 TEL (214) 386-7300 FAX (214) 490-6419 10530 Rockley Road Houston, TX 77099 TEL (713) 495-4700 FAX (713) 495-5642 8200 Interstate 10 West Suite 705 San Antonio, TX 78230 TEL (512) 377-3440 FAX (512) 378-3626 ZEUS ELECTRONICS 3220 Commander Drive Carrollton, TX 75006 TEL (214) 380-4330 (800) 52-HI-REL FAX (214) 447-2222 Utah ARROW/SCHWEBER ELECTRONICS 1946 W. Parkway Blvd. Salt Lake City, UT 84119 TEL (801) 973-6913 FAX (801) 972-0200 ALL AMERICAN/UTAH 4455 South 700 East Suite 301 Salt Lake City, UT 84107 TEL (800) 682-8313 FAX (801) 261-3885 MILGRAY/AUSTIN 11824 Jollyville Road Suite 103 Austin, TX 78759 TEL (512) 331-9961 FAX (512) 331-1070 INSIGHT ELECTRONICS 545 East 4500 South Suite EII0 Salt Lake City, UT 84107 TEL 801-288-9043 FAX 801-288-9195 MILGRAYIDALLAS 16610 North Oallas Parkway Suite 1300 Dallas, TX 75248 TEL (214) 248-1603 FAX (214) 248-0218 MILGRAY/HOUSTON 12919 S.W. Freeway, Suite 130 Stafford, TX 77477 TEL (713) 240-5360 FAX (713) 240-5404 8-16 PIONEER STANDARD ELECTRONICS North American Distributors MARSHALL INDUSTRIES 2355 S. 1070 West, Suite D Salt Lake City, UT 84119 TEL (801) 973-2288 FAX (801) 973-2296 MILGRAYIUTAH 310 E. 4500 South, Suite 110 Murray, UT 84107 TEL (801) 261-2999 FAX (801) 261-0880 North American Distributors Washington ALMAC/ARROW ELECTRONICS 14360 S.E. Eastgate Way Bellevue, W A 98007 TEL (206) 643-9992 FAX (206) 649-9709 INSIGHT ELECTRONICS 12002 115th Avenue N.E. Kirkland, W A 98034 TEL (206) 820-8100 FAX (206) 821-2976 MARSHALL INDUSTRIES 11715 N. Creek Parkway South Suite 112 Bothell, WA 98011 TEL (206) 466-5747 FAX (206) 486-6964 PIONEER STANDARD ELECTRONICS 2800 156th Avenue SE, Suite 100 Bellevue, W A 98007 TEL (206) 644-7500 FAX (206) 644-7300 Wisconsin 8544 Baxter Place Burnaby, BC, Canada V5A4T8 TEL (604) 421-2333 FAX (604) 421-5030 36 Antares Drive, Unit lOa Nepean, Ontario, Canada K2E7W5 TEL (613) 226-6903 FAX (613) 723-2018 1093 Meyerside Dri ve Mississauga, Ontario, Canada L5TI M4 TEL (905) 670-7769 FAX (905) 670-7781 MARSHALL INDUSTRIES 148 Brunswick Boulevard Pointe Claire, Quebec H9R 5P9 Canada TEL (514) 694-8142 FAX (514) 694-6989 6285 Northam Dr. Mississauga, Ontario L4 V I X5 Canada TEL (905) 465-1771 FAX (905) 612-1988 223 Colonnade Road, Unit 12 Nepean, Ontario K2E 7K3 Canada TEL (613) 226-8840 FAX (613) 226-63S2 10711 Cambie Road, Suite 170 Richmond, B.C. V6X 3GS Canada TEL (604) 273-SS75 FAX (604) 273·2413 Place Iberville IV 2954 Blvd. Laurier, Suite 100 Ste-Foy, Quebec GIV 4T2 Canada TEL (418) 654-1077 FAX (418) 654·2958 520 McCaffrey Street Ville St. Laurent, Quebec H4T INI Canada TEL (514) 737·9700 FAX (SI4) 737-S212 ARROW/SCHWEBER ELECTRONICS 200 North Patrick Blvd. Brookfield, WI 53045 TEL (414) 792-0150 FAX (414) 192-0156 INSIGHT ELECTRONICS 10855 West Potter Road Suite 14 Wauwatosa, WI 53222 TEL (414) 258-5338 FAX (414) 258-5360 MARSHALL INDUSTRIES Crossroads Corporate Center I 20900 Swenson Drive, Suite 150 Waukesha, WI 53186 TEL (414) 797-8400 FAX (414) 797-8270 PIONEER STANDARD ELECTRONICS 120 Bishops Way, Suite 163 Brookfield, WI 53005 TEL (414) 784-3480 FAX (414) 784-8207 Canada ARROW/SCHWEBER ELECTRONICS 1100 St. Regis Blvd. Dorval, Quebec, Canada H9P2T5 TEL (514) 421-7411 FAX (514) 421-7430 MILGRAY/TORONTO 2783 Thamesgate Drive Mississauga, Ontario L4T IG5 Canada TEL (905) 678-0958 FAX (905) 678-1213 MILGRAY/MONTREAL 6600 Trans Canada, Suite 209 Pointe Claire, Quebec H9R-4S2 Canada TEL (514) 426-5900 FAX (514) 426-5836 PIONEER STANDARD ELECTRONICS 5601212-31 Avenue NE Calgary, Alberta T2E 7S8 Canada TEL (403) 291-1988 FAX (403) 291-0740 148 York Street, Suite 209 London, Ontario N6A IA9 Canada TEL (519) 672-4666 FAX (519) 672-3528 341S American Drive Mississauga, Ontario L4V I T6 Canada TEL (90S) 40S-8300 FAX (90S) 405-6425 II 8-17 8-18 North American Distributors North American Representatives Alabama Florida ELECTRONIC MARKETING ASSOC. 7501 S. Memorial Parkway Suite 106 Huntsville, AL 35802 TEL (205) 880-8050 FAX (205) 880-8054 COMPONENT DESIGN MARKETING 800 Corporate Drive, Suite 230 Ft. Lauderdale, FL 33334 TEL (305) 492-1160 FAX (305) 492-1167 Arizona COMPASS MARKETING 1180 I North Tatum Boulevard Suite 101 Phoenix, AZ 85028 TEL (602) 996-0635 FAX (602) 996-0586 California PROMERGE SALES, INC. 100 Century Center Court Suite 710 San Jose, CA 95112 TEL (408) 467-0600 FAX (408) 467-0610 PROLINE TECHNOLOGIES P.O. Box 1326 Healdsburg, CA 95448 TEL (707) 431-2937 FAX (707) 431-1809 HARPER & STRONG 2798 Junipero Avenue Signal Hill, CA 90806 TEL (310) 424-3030 FAX (310) 424-6622 SiLICON TECHNiCAL SALES, INC. 140 Lomas Santa Fe Drive Suite 203 Solana Beach, CA 92075 TEL (619) 793-3330 FAX (619) 793-4188 Colorado THORSON ROCKY MOUNTAIN 7108 D South Alton Way, Suite A Englewood, CO 80112 TEL (303) 773-6300 FAX (303) 773-6302 Connecticut DELTA-CONN TECHNICAL SALES One Prestige Drive, 2nd Floor Suite 206 Meriden, CT 06450 TEL (203) 634-8558 FAX (203) 238-1240 1900 S.W. 85th Avenue North Lauderdale, FL 33068 TEL (305) 726-5444 FAX (305) 726-5155 2318 Stag Run Boulevard Clearwater, FL 34625 TEL (813) 725-4894 FAX (813) 796-7252 7616 Southland Boulevard Suite 103 Orlando, FL 32809 TEL (407) 240-3903 FAX (407) 240-4305 4502 West Elm Street Tampa, FL 33614 TEL (813) 886-9721 FAX (813) 888-7816 Calle Hucar 38 (Bajos) BO Sabanetas Mercedita 00715 Puerto Rico TEL (809) 844-3840 FAX (809) 844-3915 Georgia ELECTRONIC MARKETING ASSOC. 5855 Jimmy Carter Blvd. Suite 190 Norcross, GA 30071 TEL (404) 448-1215 FAX (404) 446-9363 Iowa DY-TRONIX, INC. 23 Twixt Town Road N.E. Cedar Rapids, IA 52402 TEL (319) 377-8275 FAX (319) 377-9163 Illinois PHASE II MARKETING 2220 Hicks Road, Suite 206 Rolling Meadows, IL 60008 TEL (708) 577-9401 FAX (708) 577-9491 Indiana CORRAO MARSH, INC. 6211 Stoney Creek Drive Fort Wayne, IN 46825 TEL (219) 482-2725 FAX (219) 484-7491 3063 West U.S. 40 Greenfield, IN 46140 TEL (317) 462-4446 FAX (317) 462-6568 MILLENNIUM TECHNICAL SALES 6640 Broadway Street Indianapolis, IN 46220 TEL (317) 257-0828 FAX (317) 257-0837 Kansas DY-TRONIX, INC. 5001 College Boulevard, Suite 106 Leawood, KS 66211 TEL (913) 339-6333 FAX (913) 339-9449 1999 Amidon, Suite 322 Wichita, KS 67203 TEL (316) 838-0884 FAX (316) 838-2645 Maryland AVTEK ASSOCIATES, INC. 10632 Little Patuxent Parkway, Suite 220 Columbia, MD 21044 TEL (410) 740-5100 FAX (410) 740-5103 Massachusetts CTC ASSOCIATES, INC. 12 Southwest Park Westwood, MA 02090 TEL (617) 320-1818 FAX (617) 320·8282 Michigan TRILOGY MARKETING, INC. 691 N. Squirrel Road, Suite 110 Auburn Hills, MI 48326 TEL (810) 377-4900 FAX (810) 377-4906 Minnesota PSI 8000 Town Line Avenue S. Suite 206 Bloomington, MN 55438 TEL (612) 944-8545 FAX (612) 944-6249 Missouri DY-TRONIX, INC. 3407 Bridgeland Drive Bridgeton, MO 63044 TEL (314) 291-4777 FAX (314) 291-3861 II 0409C 8-19 Nevada PROLINE TECHNOLOGIES P.O. Box 1326 Healdsburg, CA 95448 TEL (707) 431-2937 FAX (707) 431-1809 New Jersey NORTH EAST COMPONENTS 19 Spear Road, Suite 205 Ramsey, NJ 07446 TEL (201) 825-0233 FAX (201) 934-1310 6519 Wilson Mills Road Mayfield Village, OH 44143 TEL (216) 461-3500 FAX (216) 461-1335 Oklahoma QUAD STATE SALES & MARKETING 110 W. Commercial Street Suite 210 Broken Arrow, OK 74013 TEL (918) 258-7723 FAX (918) 258-7653 Oregon TRITEK SALES, INC. I Mall Drive, Suite 410 Cherry Hill, NJ 08002 TEL (609) 667-0200 FAX (609) 667-8741 ELECTRONIC SOURCES, INC. 6850 SW 105th, Suite B Beaverton, OR 97008 TEL (503) 627-0838 FAX (503) 627-0238 Wisconsin PHASE II MARKETING 205 Bishop's Way Suite 220 Brookfield, WI 53005 TEL (414) 797-9986 FAX (414) 797-9935 Canada CLARK-HURMAN ASSOCIATES 78 Donegani, Suite 200 Pointe Claire, Quebec H9R 2V4 Canada TEL (514) 426-0453 FAX (514) 426-0455 New Mexico Pennsylvania 308 Palladium Drive, Suite 200 Kanata, Ontario K2V IAI Canada TEL (613) 599-5626 FAX (613) 599-5707 COMPASS MARKETING 4100 Osuna Road, Suite 109 Albuquerque, NM 87109 TEL (505) 344-9990 FAX (505) 345-4848 MILLENNIUM TECHNICAL SALES 505 Bayberry Lane Inperial, PA 15126 TEL (412) 695-7661 FAX (412) 695-7870 16 Regan Road, Units 39, 40, 41 Brampton, Ontario L7A 1CI Canada TEL (905) 840-6066 FAX (905) 840-6091 New York Texas QUAD STATE SALES & MARKETING 8310 Capital of Texas Hwy, North Suite 365 Austin, TX 78731 TEL (512) 346-7002 FAX (512) 346-3601 EMPIRE TECHNICAL ASSOC. 29 Fennell Street, Suite A Skaneateles, NY 13152 TEL (315) 685-5703 FAX (315) 685-5979 349 West Commercial Street Suite 2920 E. Rochester, NY 14445 TEL (716) 381-8500 FAX (716) 381-0911 North Carolina ELECTRONIC MARKETING ASSOC. 6600 Six Forks Road, Suite 201 Raleigh, NC 27615 TEL (919) 847-8800 FAX (919) 848-1787 9407 King Falls Dr. Charlotte, NC 28210 TEL (704) 544-9948 FAX (704) 544-9941 Ohio MILLENNIUM TECHNICAL SALES 3165 Linwood Road Cincinnati, OH 45208 TEL (513) 871-2424 FAX (513) 871-2524 6631 Commerce Parkway Suite K Dublin,OH 43017 TEL (614) 793-9545 FAX (614) 793-0256 8·20 12160 Abrams Road, Suite 406 Dallas, TX 75243 TEL (214) 669-8567 FAX (214) 669-8834 \0565 Katy Fwy, Suite 212 Houston, TX 77024 TEL (713) 467-7749 FAX (713) 467-5942 Utah THORSON ROCKY MOUNTAIN 5505 South 900 East Suite 140 Salt Lake City, UT 84117 TEL (801) 264-9665 FAX (801) 264-9881 Washington ELECTRONiC SOURCES, INC. 1603 116th Ave, N.E., Suite 115 Bellevue, WA 98004 TEL (206) 451-3500 FAX (206) 451-1038 North American Representatives International Representatives Greece Australia Denmark GEC ELECTRONICS DIVISION MER-ELAIS MICRELEC LTD. 38 South Street Rydalmere, N.S.W. 2116 Australia TEL (61) 2898-7422 FAX (61) 2638-1798 Ved Klaedebo 18 Post Boks 219 DK-2970 Horsholm Denmark TEL (45) 42-571000 FAX (45) 42-572299 339 Thivon Street GR 12244 Aegaleo Athens, Greece TEL (30) 1-5395042-4 FAX (30) 1-5390269 CODICO Finland TLG ELECTRONICS, LTD. Muhlgasse 86-88 A-2380 Perchtoldsdorfl A Austria TEL (43) 1-863-3050 FAX (43) 1-863-0598 OY BEXAB FINN-CRIMP AB P.O. Box 51 SF-02631 Espoo Finland TEL (358) 0-61352690 FAX (358) 0-61352655 Room 1404, Hang Shing Bldg. 363-373, Nathan Road Yanumatei, Kowloon Hong Kong TEL (852) 2388-7613 FAX (852) 2783-0198 WES TECH ELECTRONICS, LTD. Austria Belgium France ALCOM ELECTRONICS BV MICRO PUISSANCE Singel3 2550 Kontich Belgium TEL (32) 3-4583033 FAX (32) 3-4583126 Immeuble Femto 1 Avenue de Norvege Z.A. de Courtaboeuf B.P. 79 91943 Les Viis Cedex France TEL (33) 1-69071211 FAX (33) 1-69076712 Brazil COLGIL, INC. Rua Marques de Itu, 306, Conj. 94 CEP 01223-000 Sao Paulo Brazil TEL (55) 11-223-6954 FAX (55) 11-223-4989 Headquarters New York United States TEL (212) 832-1340 FAX (212) 826-3623 Tucuman 1567, Officina 14 Buenos Aires Argentina TEL (54) 1-46-2128 FAX (54) 1-46-1128 HASTEC Rua Ferreira Do Alentecj, 90/92 CEP 04728 Sao Paulo Brazil TEL (55) 11-522-1799 FAX (55) 11-522-5366 Bulgaria CODICO Blvd. Bulgaria 86 I Apt. 9 BG 5500 Lovetsch Bulgaria TEL (359) 68-44812 FAX (359) 68-44812 Hong Kong Room 160 I, Star Centre 433-451, Castle Peak Road Kwai Chung, N.T. Hong Kong TEL (852) 2418-9818 FAX (852) 2429-2355 Hungary CODICOKFT NEWTEK 8 Rue De L'Estrerel Silic 583 94663 Rungis Cedex France TEL (33) 1-46872200 FAX (33) 1-46878049 Germany INELTEK GMBH Hauptstrasse 45 89522 Heidenhiem Germany TEL (49) 7321-93850 FAX (49) 7321-938595 INELTEK MinE Stehnweg 2 63500 Seligenstadt Germany TEL (49) 6182-5066 FAX (49) 6182-65953 Ostrom Vtca 23-25 1015 Budapest TEL (36) 1-156-63-30 FAX (36) 1-156-43-76 India ORIOLE SERVICES Post Box No. 9275 5 Kurla Industrial Estate Ghatkopar, Bombay 400 086 India TEL (022) 5119940 FAX (022) 5115810 Ireland ZEC SERVICES Valleymount Blessington Co. Wicklow Ireland TEL (353) 456-4259 FAX (353) 467-4075 Israel INELTEK MURNAU Am Fugsee 21 82418 Murnau-Riedhausen Germany TEL (49) 8841-47775 FAX (49) 8841-2660 INELTEK NORD Billstrasse 30 20539 Hamburg 26 Germany TEL (49) 78942-274 FAX (49) 78942-220 ISAMTEK LTD. 53 Herzel Street P.O. Box 13902 Netanya 42-137 Israel TEL (972) 9-826445 FAX (972) 9-826447 I 04108 8-21 Italy UNI ELECTRONICS, INC. APEX ELECTRONICS LTD. LASI ELETTRONICA S.P.A. P.O. Box 68, Sumitomo Bldg. 2-6-1 Nishi Shinjukn Shinjuku-ku Tokyo 163 Japan TEL (81) 3-3347-8878 FAX (81) 3-3347-8808 175 Vivian Street Wellington, New Zealand TEL (64) 4-3853404 FAX (64) 4-3853483 Viale Fulvio Testi 280 20126 Milano Italy TEL (39) 2-66101370 FAX (39) 2-66101385 NEWTEK ITALIA SPA Via Tonoli 1 20145 Milano Italy TEL (39) 2-33105308 FAX (39) 2-33103694 Japan Osaka Branch 5-13-9, Mitejima Nishi Yodogawa-ku Osaka 555 Japan TEL (81) 6-473-8429 FAX (81) 6-473-5513 MCMJAPAN LTD. Korea Santower Bldg. 2-11-22, Sangenjyaya Setagaya- Ku, Tokyo 154 Japan TEL (81) 3-3487-8477 FAX (81) 3-3487-8825 1& C MICROSYSTEMS CO. LTD Tachikawa Sales Office Tachikawa Center Bldg. 2-22-20, Akebono Cho Tachikawa Tokyo 190 Japan TEL (81) 425-22-8600 FAX (81) 425-23-8603 TAKACHIHO KOHEKI CO., LTD. 1-2-8, Yotsuya Shinjuku-Ku Tokyo 160 Japan TEL (81) 3-3355-6696 FAX (81) 3-3357-5034 Fukoku Seimei Bldg. 2-4, Komatsubara-Cho Kita-Ku, Osaka 530 Japan TEL (81) 6-313-0671 FAX (81) 6-313-3380 RYOYO ELECTRO CORP. Konwa Bldg., 1-12-22 Tsukiji, Chuo-Ku Tokyo 104 Japan TEL (81) 3-3546-5011 FAX (81) 3-3546-5044 Osaka Branch Nissin Syokuhin Bldg., 4-1-1 Nishi Nakajima, Yodogawa-ku Osaka 532 Japan TEL (81) 6-301-1221 FAX (81) 6-302-1002 8-22 801, 8th Floor, Bethel Building 324-1, Yang Jae-Dong Seocho-Ku Seoul, Korea TEL (82) 2-577-9131 FAX (82) 2-577-9130 SHINHWA CORPORATION 2F, The Christian Literature, Society of Korea Bldg. 169-1, Samsung-Dong, Kangnam-Ku Seoul, Korea TEL (82) 2-554-6431 FAX (82) 2-554-7649 UNIQUEST KOREA Suite 1110, Daejong Bldg. 143-48, Samsung-Dong, Kangnam-Ku Seoul, Korea TEL (82) 2-562-8805 FAX (82) 2-562-6646 Mexico ADELSA Club Cuieacalli #66 CTO Cronistas Zona Azul CD Satelite Naucalpan De Juarez C.P. 53100 EDO de Mexico Mexico TEL (525) 374-0981 FAX (525) 374-0997 GEC ELECTRONICS 5 Reliable Way Penrose Auckland New Zealand TEL (64) 9-526-0107 FAX (64) 9-525-7923 Norway NC NORDCOMP AS PO Box 190 2020 Skedsmokorset Norway TEL (47) 63-879330 FAX (47) 63-879000 Poland CODICO UI Bora Komorowskiego 6117 86-300 Grudziadz Poland TEL (48) 51-23223 FAX (48) 51-23223 Portugal ANATRONIC-PORTUGAL S.A. Rua Padre Antonio Vieira, Nil. 31-B Povoa De Santo Adriao - 2675 Odivelas Portugal TEL (351) 1-9376267 FAX (351) 1-9371834 Romania CODiCO BD Decebal NR II BLS 14 sc 2, Apt. 41, Sect. 3 Bucharest TEL (40) 1-3210431 FAX (40) 1-3210431 Singapore NUCLEUS ELECTRONICS PTE LTD. 6001 Beach Road #18-03 Golden Mile Tower Singapore 0719 TEL (65)297-6883 FAX (65) 297-6882 ALCOM ELECTRONICS BV SINGASOF COMPUTERS PTE., LTD. Essebaan I 2908 LG Capelle Aan Den Yssel Netherlands TEL (31) 10-4519533 FAX (31)10-4586482 2 Kallang Pudding Road #09-04 Mactech Industrial Bldg. Singapore 1334 TEL (65) 747-3012 FAX (65) 747-5279 Netherlands New Zealand International Representatives International Representatives South Africa ADVANCED SEMICONDUCTOR DEVICES (PTY), LTD. P.O. Box 3853 Rivonia 2128 South Africa TEL (27) 11-444-2333 FAX (27) 11-444-1706 APPLIED COMPONENT TECHNOLOGY CORP. 8F, No. 233-1 Pao Chiao Road Hsin Tien City Taipei Hsien Taiwan, R.O.C. TEL (886) 2-917-0858 FAX (886) 2-917-1895 Spain ANATRONIC S.A. AVDA. De Valladolid, 27 28008 Madrid Spain TEL (34) 1-542-44-55 FAX (34) 1-559-69-75 NEOLEC INTERNATIONAL INC. 3F, Jen Jen Bldg No. 29, Jen Ai Road, Sec. 3, Taipei 106 Taiwan, R.O.C. TEL (886) 2-778-8716 FAX (886) 2-778-6076 Bailen, 176. Entresuelo Ill. 08037 Barcelona Spain TEL (34) 3-458-19-06 FAX (34) 3-458-71-28 PRINCETON TECHNOLOGY CORP. 2F, No. 233-1. Bao Chiao Road Hsin Tien, Taipei Hsien Taiwan, R.O.C. TEL (886) 2-917-8856 FAX (886) 2-917-3836 Las Mercedes 25 3l!, Dpto. I 48930 Las Arenas-Vizcaya Spain TEL (34) 4-463-60-66 FAX (34) 4-463-42-35 Sweden KELTECH COMPONENTS AS Box 505 Kemistvagen 10 A S-18325 Taby Sweden TEL (46) 86308590 FAX (46) 87562143 Switzerland ANATECAG Sumpfstrasse 7 CH 6300 ZUG Switzerland TEL (41) 42-412441 FAX (41) 42-413124 Taiwan ALLREACH ENTERPRISE CO., LTD. 6F, No. 50-I, Sec. I Hsin Sheng South Road Taipei, Taiwan RO.C. TEL (886) 2-321-4229 FAX (886) 2-321-5849 PRONTO ELECTRONIC SYSTEMS, LTD. City Gate House 399-425 Eastern Ave. Gants Hill liford, Essex 192 6LR England TEL (44) 81-554-6222 FAX (44) 81-518-3222 TOPTREND TECHNOLOGIES CORP. 8F, No. 669, Sec. 5 Chung Hsiao East Road Taipei, Taiwan R.O.C. TEL (886) 2-769-6220 FAX (886) 2-769-6228 Thailand SEMIKON COMPANY, LTD. 4F, Room 406, Phansak Bldg. Phetburi Road 13811 Rajthevee, Bangkok, 10400 Thailand TEL (662) 215-0760 FAX (662) 215-6857 Turkey AZTECH ELECTRONIK, LTD. Kaptanpasa Sok No. 25/2 06700 G.O.P. Ankara, Turkey TEL (90) 312-447-0384 FAX (90) 312-447-0387 United Kingdom GO TECHNIK, LTD. Tudor House 24 High Street Twyford, Berks RGIO 9AG England TEL (44) 734-342277 FAX (44) 734-342896 • 8-23 8·24 International Representatives ATMEL HEAOGUARTERS 2125 O 'Nel Drive San Jose, CA 95131 TEL (408 ) 441 -0311 FAX (408 ) 436-4300 ATME L COLORAOO SPRINGS OPERATION .. 1150 E. Cheyenne Mountain Boulevard Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (7[9) 540-1759 AlmEl c~ Prim ed on recycled paper © A,mel Corpor1l'ion 1995 05ZZA-l0/95/30M
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