1995_Crystal_Semiconductor_Data_Acquisition_Databook 1995 Crystal Semiconductor Data Acquisition Databook

User Manual: 1995_Crystal_Semiconductor_Data_Acquisition_Databook

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MODEL INDEX
CS2180AIB ................... .4-15
CS3310 ............................. 3-7
CS4110111 ...................... 3-21
CS4112 ........................... 3-22
CS4215 ........................... 3-23
CS4216 ........................... 3-24
CS4225 ........................... 3-25
CS4231A ........................ 3-26
CS4232 ........................... 3-27
CS4248 ........................... 3-29
CS4303 ............................. 3-8
CS4328 ............................. 3-9
CS4329 ........................... 3-10
CS4330/113 ..................... 3-11
CS4920A ........................ 3-19
CS4921 ........................... 3-20
CS5012A114116 ................ 2-7
CS5030/31 ...................... 2-55
CS5032 ........................... 2-81
CS5101A12A ................ 2-113
CS5126 ......................... 2-159
CS5317 ......................... 2-189
CS5321 ......................... 2-219
CS5322/23 .................... 2-245
CS5324 ......................... 2-283
CS5330 ........................... 3-12
CS5336/8/9 ..................... 3-13
CS5389 ........................... 3-14
CS5390 ........................... 3-15
CS5412 ......................... 2-315
CS5480 ......................... 2-345
CS5481 ......................... 2-355
CS5490 ......................... 2-365

CS5501103 .................... 2-367
CS5504 ......................... 2-421
CS5505/6n18 ............... 2-451
CS5509 ......................... 2-489
CS5516120 .................... 2-519
CS5542 ......................... 2-559
CS5543 ......................... 2-561
CS61304A ...................... 4-16
CS61305A ...................... 4-17
CS61535/35A ................. 4-18
CS61574A175 ................. 4-19
CS61577 ......................... 4-20
CS61584 ......................... 4-21
CXT6176/8192 ............... 4-22
CS6400 ............................. 4-7
CS6401 ............................. 4-8
CS6450 ........................... 4-11
CS6453 ........................... 4-12
CS7870175 .................... 2-563
CS8130 ............................. 4-6
CS83C92A1C ................. 4-13
CS8401A12A .................. 3-16
CS841 1112 ...................... 3-17
CS8425 ........................... 3-18
CS8900 ........................... 4-14
CS8905C ........................ 3-30
CS9233 ........................... 3-31
CDBCAPTURE ........... 2-597
CWDRGNTT ................. 3-36
CWECAXB ...................... 4-9
CWMNLG ..................... 3-37
DIAGNOSTICS ............. 3-35
DRIVERS ....................... 3-34

DADB9.0

---------------------Crystal Semiconductor Corporation
Data Acquisition Products
Data Book

March 1995

This publication neither states nor implies any warranty of any kind, including, but not limited to, implied warrants of merchantability or
fitness for a particular application. Crystal assumes no responsibility for the use of any circuitry other than the circuitry in a Crystal product.
No circuit patent licenses are implied.
The information in this publication is believed to be accurate in all respects at the time of publication but is subject to change without
notice. Crystal assumes no responsibility for elTors and omissions, and disclaims responsibility for any consequences resulting from the use
of information included herein. Additionally, Crystal assumes no responsibility for the functioning of undescribed features or parameters.

© CopYright 1995 Crystal Semiconductor Corporation. ALL RIGHTS RESERVED.
LIFE SUPPORT AND NUCLEAR POLICY
CRYSTAL SEMICONDUCTOR PRODUcrS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRrITEN CONSENT OF CRYSTAL
SEMICONDUcrOR.
Life Support Systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with
instructions provided can be reasonably expected to result in personal injury or death. Users contemplating applications of Crystal Semiconductor products in Life Support Systems are requested to contact Crystal Semiconductor factory headquarters to establish suitable terms and
conditions for these applications. Crystal Semiconductor's warranty is limited to replacement of defective components and does not cover
injury to persons or property or other consequential damages.
Examples of devices considered to be life support devices are neonatal oxygen analyzers, nerve stimulators (whether used for anesthesia,
pain relief, or other purposes), autotransfusion devices, blood pumps, defibrillators, arrhythmia detectors and alarms, pacemakers, hemodialysis systems, peritoneal dialysis systems, neonatal ventilator incubators, ventilators for both adults and infants, anesthesia ventilators, and
infusion pumps, as well as other devices designated as "critical" by the FDA. The above are examples only and are not intended to be
conclusive or exclusive of any other life support device.
Examples of nuclear facility applications are applications in (a) a nuclear reactor, or (b) any device designed or used in connection with the
handling, processing, packaging, preparation, utilization, fabricating, alloying, storing, or disposal of fissionable material or waste products
thereof.

1

---------------------TRADEMARKS
Crystal Semiconductor Corporation has made every effort to supply trademark information about
company names, products, and services mentioned in this book. Trademarks indicated below are derived from various sources.

"e"

(stylized) is a registered trademark of Crystal Semiconductor Corporation.

CRYSTAL, SMART Analog, Crystal Clear, and CrystalWare are trademarks of Crystal
Semiconductor Corporation.
Other trademarks in this book belong to their respective companies.

PATENTS
Products in this book may be covered by one or more of the following patents. Additional patents
are pending.

USA
4,709,225;
4,941,156;
5,087,914;
5,187,390;
5,248,970;
5,376,936

4,746,899;
4,943,807;
5,088,107;
5,196,850;
5,257,026;

4,748,418;
4,988,954;
5,111,451;
5,198,782;
5,258,758;

4,804,863;
5,012,244;
5,117,200;
5,208,597;
5,268,651;

4,805,198;
5,039,989;
5,121,080;
5,212,659;
5,274,375;

4,849,662;
5,055,846;
5,140,279;
5,220,483;
5,319,319;

4,851,841;
5,061,925;
5,150,386;
5,239,210;
5,319,370;

4,918,454;
5,068,660;
5,157,395;
5,245,344;
5,339,067;

4,939,516;
5,079,550;
5,172,115;
5,247,210;
5,351,050;

GERMANY
P3642070.0; P3733682.7; P3736735.8; P3737279.3; P3933552.6; P4002871.2; P4200745.3;
P4202180.4
GREAT BRITAIN
2184621;2195848;2198305;2198306;2223879;2232547;2247370;2252459; 2252829;2253754;
2253756;2254504;2261561

FRANCE
8617487; 8713769; 8715552; 8715553
JAPAN
1684670; 1736807; 1747931;4-25778

2

-_..__.._-_.
_............
...-

DATA ACQUISITION DATA BOOK CONTENTS

GENERAL INFORMATION
DATA ACQUISITION
General Purpose
Industrial Measurement
Seismic
High Speed

•
•

AUDIO PRODUCTS
Consumer/Professional
Broadcast
Multimedia
COMMUNICATIONS PRODUCTS
Infrared Transceiver
Echo Cancellers
Communications Codecs
EthernetlCheapernet
Telecom

-•
•

APPLICATION NOTES
APPENDICES
Product Category Levels
Reliability Calculation Methods
Package Mechanical Drawings
Standard Military Drawings
SALES OFFICES

3

i

I

..,....- ....
.......
.....
..,_ ......
..,..,~.

4

CONTENTS

1. GENERAL INFORMATION
- Company Information and Part Numbering Convention
- Quality and Reliability Infonnation

1-3
1-5

2. DATA ACQUISITION PRODUCTS
- Introduction, Contents and User's Guide
- CS5012A14/6 16, 14, & 12-Bit, Self-Calibrating AID Converters
- CDB5012A14/6 Evaluation Board for CS5012A14/6
NEW - CS5030/l 12-Bit, 500 kHz, Sampling AID Converters
NEW - CS5032 12-Bit, 500 kHz, Sampling AID Converters
- CDB5030/l/2 Evaluation Board for CS5030/l12
- CS5101A12A 16-Bit, 100 kHzl20 kHz AID Converters
- CDB5101A12A Evaluation Board for CS5101A12A
- CS5126 16-Bit, Stereo AID Converter for Digital Audio
- CDB5126 16-Bit, Stereo AID Converter for Digital Audio
- CS5317 16-Bit, 20 kHz Oversampling AID Converter
- CDB5317 Evaluation Board for CS5317
NEW - CS5321 High Dynamic Range Delta-Sigma Modulator
- CDB5321 Evaluation Board for CS5321
- CS5322/3 24-Bit Variable Bandwidth AID Converter
- CDB5322/3 Evaluation Board for CS5322/3
- CS5324 120 dB, 500 Hz Oversampling AID Converter
- CDB5324 Evaluation Board for CS5324
- CS5412 12-Bit, 1MHz Self-Calibrating AID Converter
- CDB5412 Evaluation Board for CS5412
NEW - CS5480 10-Bit, 40 MHz, AID Converter
NEW - CS5481 10-Bit, 10 MHz, AID Converter
NEW - CS5490 12-Bit, 20 MHz, AID Converter
- CS550113 Low-Cost, 16 & 20-Bit Measurement AID Converter
- CDB550113 Evaluation Board for CS550113
NEW - CS5504 Low Power, 20-Bit AID Converter
- CDB5504 Evaluation Board for CS5504
- CS5505/617/8 Very Low Power, 16-Bit and 20-Bit AID Converters
- CDB5505/617 18 Evaluation Board for CS5505/617 18
NEW - CS5509 Single Supply, 16-BitAID Converter
- CDB5509 Evaluation Board for CS5509
- CS5516120 16-Bitl20-Bit Bridge Transducer AID Converters
- CDB5516120 Evaluation Board for CS5516120
NEW - CS5542 Dual Channel Current-Input Modulator .
NEW - CS5543 8-Channel Digital Decimation Filter
NEW - CS787015 12-Bit, 100 kHz Sampling AID Converter
- CDB787015 Evaluation Board for CS787015
- CDBCAPTURE Evaluation Board

2-1
2-7
2-48
2-55
2-81
2-104
2-113
2-149
2-159
2-178
2-189
2-212
2-219
2-233
2-245
2-272
2-283
2-305
2-315
2-335
2-345
2-355
2-365
2-367
2-407
2-421
2-444
2-451
2-482
2-489
2-511
2-519
2-549
2-559
2-561
2-563
2-588
2-597

. ..,-- ._.

_

3.

4.

tIa'. . . .tIa'tIa'_ •
• •tIa'tIa' • • •_

AUDIO CONVERSION PRODUCTS
- Chapter Introduction
ConsumerlProfessional
- CS3310 Stereo Digital Volume Control
- CS4303 Digital to Analog Converter
- CS4328 Digital to Analog Converter .
NEW - CS4329 Digital to Analog Converter .
NEW - CS43301113 Digital to Analog Converter
NEW - CS5330 Analog to Digital Converter .
- CS5336/8/9 Analog to Digital Converter
NEW - CS5389 Analog to Digital Converter .
NEW - CS5390 Analog to Digital Converter .
- CS8401N02A Digital Audio Transmitter
- CS8411112 Digital Audio Receiver
- CS8425 A-LAN Transceiver
Broadcast
NEW - CS4920/CS4920A Multi-Standard Audio Decoder-DAC
NEW - CS4921 MPEG 1 & MPEG 2 Audio Decoder-DAC .
Multimedia
- CS4110Il Wavetable Sample ROMs for Music Synthesis
- CS4112 Wavetable Sample ROM for Music Synthesis
- CS4215 Multimedia Audio CODEC
- CS4216 Stereo Audio CODEC
- CS4225 Digital Audio Conversion System
- CS4231A Enhanced PC Bus Interface CODEC
NEW - CS4232 Games Compatible Plug-and-Play Audio System
- CRD4232-1 Low-Cost Reference Design
- CS4248 PC Bus Interface CODEC
- CS8905C Programmable Effects Processor
NEW - CS9233 Integrated Wavetable Synthesizer
- CRD9233-1 Wavetable/Audio Reference Design
- CRD9233-2 GMiGS Music Synthesizer Daughtercard
- DRIVERS Software
- DIAGNOSTICS Software
- CWDRGNTT Software
- CWMNLG Software
COMMUNICATION PRODUCTS
- Chapter Introduction
Infrared Transceiver
NEW - CS8130 Infrared Transceiver
Echo Cancellers
NEW - CS6400 Echo Cancelling Codec
NEW - CS6401 Programmable Echo Canceller

CONTENTS

3-2
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
3-37
4-1
4-6
4-7
4-8
5

....-......
--_-...
._.
_._-_
NEW
NEW

NEW

NEW
NEW

NEW
NEW

5.

6

CONTENTS

- CWECAXB Executable Code for the CS6401
- CDB6401 Evaluation Board
Communication Codecs
- CS6450 TDMA Cellular Baseband CODEC
- CS6453 Modem Analog Front-End
EthernetlCheapernet
- CS83C92NC Ethernet Transceiver
• CS8900 Ethernet Controller
Telecom
- CS2180AIB TI FramerfTransceiver
- CS61304A TIIEI Line Interface .
- CS61305A TIIEI Line Interface .
- CS61535/35A TIIEI Line Interface
- CS61574A175 TIIEI Line Interface
- CS61577 TIIEI Line Interface
- CS61584 Dual Low Power TIIEI Line Interface
- CXT6176/8192 Pullable Quartz Crystals .

APPLICATION NOTES
- Layout and Design Rules for Data Converters and Other Mixed Signal Devices
- Delta-Sigma AID Conversion Technique Overview .
NEW - The CS5504 Family Characteristics .
NEW - CS5516 and CS5520: Overcoming Errors in Bridge Transducer Measurement
NEW - A Collection of Bridge Transducer Digitizer Circuits
NEW - CS5516 and CS5520: Answers to Application Questions
NEW - Precision Temperature Measurement using RTDs (Resistance Temperature
Detectors) with the CS5516 and CS5520 Bridge Transducer AID Converters
NEW - Infrared: A New Standard in Industry
NEW - Using The Capture Evaluation System
NEW - Using The CDBCAPTURE System With Embedded AID Converters
NEW - CDB5504 Capture Interface
NEW - CDB5509 Capture Interface
NEW - Noise Histogram Analysis
NEW - Clock Options for AID Converters
NEW - Switched-Capacitor AID Converter Input Structures
- Voltage References for the CS5012NCS5014/CS5016/CS5101NCS5102N
CS5126 Series of AID Converters
- Buffer Amplifiers for the CS5012NCS5014/CS5016/CS5101NCS5102N
CS5126 Series of AID Converters
- A Collection of Application Hints for the CS501X Series of AID Converters

4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
5-3
5-7
5-17
5-19
5-25
5-53
5-67
5-71
5-73
5-81
5-89
5-91
5-93
5-105
5-109
5-115
5-127
5-151

-------~--~-----------

CONTENTS

6. APPENDICES
- Contents
- Product Category Levels
- Reliability Methods
- Package Outlines
- Standard Military Drawings

6-2
6-3
6-4
6-11
6-23

7. SALES OFFICES
- Crystal Area Sales Offices
- United States Representatives
- United States Distributors
- Canada Representatives
- Europe Sales Offices
- Europe Representatives
- Far East Representatives
- Japan Sales Office
- Japan Distributors

7-3
7-3
7-7
7-9
7-9
7-9
7-11
7-12
7-12

7

..,.,,.,_..
.,.,_
......
..-- ...,."

~

DATA ACQUISITION DATA BOOK CONTENTS

.ij9Ii9;M'ili4.';I&f!i;t",~
&I

DATA ACQUISITION
General Purpose
Industrial Measurement
Seismic
High Speed
AUDIO PRODUCTS
ConsumerlProfessional
Broadcast
Multimedia
COMMUNICATIONS PRODUCTS
Infrared Transceiver
Echo Cancellers
Communications Codecs
EthernetlCheapernet
Telecom

•

APPLICATION NOTES

III

APPENDICES
Product Category Levels
Reliability Calculation Methods
Package Mechanical Drawings
Standard Military Drawings

•

SALES OFFICES

1-1

i

.. _--.......-.-.
....
~-

~~-

~~

GENERAL INFORMATJON

CONTENTS

1-2

Company Information and Part Numbering Convention

1-3

Quality and Reliability Information

1-5

----------------------

COMPANY INFORMATION

COMPANY INFORMATION
Crystal's proprietary SMART AnaloglM design technique, incorporating analog and digital circuitry in
monolithic CMOS devices, represents a powerful new technology in the semiconductor industry. This
innovative approach to design eliminates many of the sources of inconsistent performance in traditional
analog circuitry.
Maximum system performance is built-in from initial research on end-user requirements through product definition. Product quality and reliability is designed into the device architecture and is further
assured through rigorous standards for fabrication, assembly and testing. Crystal's part numbering
scheme is as follows:

II

CSLXXXX - TPNNH/R

V

L

DEVICE REVISION: DOES NOT APPEAR HERE ON PACKAGE MARK.
REVISION IS COVERED IN DATE CODE STAMP.
USED ONLY FOR ORDERINGITRACKING.

SPECIAL HANDLING ,ALPHA ONLY

A-COMMERCIAL HIGH-REL
B-MILITARY 883B REV. C PROCESSING

ELECTRICAL OR SPEED SPECIFICATION. (OPTIONAL) UP TO 2
NUMERIC DIGITS. NO ALPHA CHARACTERS. SEE DATA SHEET
PACKAGE CODE -REQUIRED ,ALPHA CHARACTER ONLY,NO NUMERICS
P = PLASTIC DIP
S= 0.3" SOIC
C = CERAMIC SIDEBRAZE
E= CERAMIC LCC
0= CERDIP
J= J-LEAD CERAMIC CHIP CARRIER
L = PLASTIC LEADED CHIP CARRIER,J LEAD
G= GULLWING CERAMIC CHIP CARRIER
U= UNPACKAGED DIE
Q= PLASTIC QUAD FLATPACK

TEMPERATURE SPECIFICATION - REQUIRED,ALPHA CHARACTER ONLY
SIGNAL CONDITIONING/COMMUNICATION:
C= O'C to 70'C
1= -40'C to 85'C
M = -55'C to 125'C
TEMPERATURE/ACCURACY - REQUIRED,ALPHA CHARACTER ONLY
DATA ACQUISITION:
TEMPERATURE
ACCURACY
BETTER
BEST
GOOD
O'C to 70'C
K
L
J
-40'C to 85'C
B
C
A
-55'C to 125'C
U
T
S

UP TO FOUR ALPHANUMERIC DIGITS COMPRISE REMAINDER OF BASIC PART NUMBER
CRYSTAL PRODUCT LINE (PROPRIETARY PARTS; SECOND·SOURCE PARTS HAVE EXCEPTIONS):
3 = DATA ACQ. SUPPORT CIRCUITS
42 = CODECS
43 = D/A CONVERTERS
5 = AID CONVERTERS
6 = TELECOMMUNICATIONS
7 = SIGNAL CONDITIONING
8 = DATACOMMUNICATIONS
CRYSTAL SEMICONDUCTOR
"CS" = ALL CRYSTAL PRODUCTS;EXCEPT FOR
"CXT' = QUARTZ CRYSTALS
"COB' = EVALUATION BOARD
"CX" = CUSTOM PRODUCTS

REV5

1-3

.._--.-..---._.
...-.

_-

COMPANY INFORMATION

In addition to the part number, all Crystal parts have a second line of marking, which can be decoded as
follows:

U

(FAT)LLRYYWW(RF)

I

wL

~

R>-.vOES'O",ro, -""''' ' "

I"'" '" '''''O,,~

DEVICE REVISION LEVEL· SECOND DIE (DUAL DIE PKGS ONLY)

ASSEMBLY DATE CODE

DEVICE REVISION LEVEL

LOT IDENTIFICATION
TEST SITE DESIGNATOR
ASSEMBLY SITE DESIGNATOR

}
NOT USED ON SMALL PACKAGES

FOUNDRY DESIGNATOR

LOT CODE IDENTIFIER • TWO DIGIT ALPHA CHARACTER.
IDENTIFIER SEQUENCE WILL BEGIN WITH
AA,AB,AC, ETC. EACH LOT WILL RECEIVE
A UNIQUE IDENTIFIER REGARDLESS OF
DEVICE OR START DATE. SEQUENCE
BEGINS AGAIN WITH AA WHEN ZZ HAS
BEEN UTILIZED.

COMPANY BACKGROUND
Crystal Semiconductor Corporation was founded in 1984 with the goal of supplying the industry with
high-performance, mixed analog/digital CMOS circuits. In 1991, Crystal became a wholly owned subsidiary of Cirrus Logic.
To meet its objectives, Crystal recruited a staff of renowned CMOS analog design engineers, a scarce
resource in the industry, and teamed them with designers trained in system architecture development.
By coupling this design staff with highly qualified application and test engineers and seasoned management, Crystal has achieved several industry firsts. Systems designers now benefit from the performance
and cost savings of Crystal breakthroughs such as self-calibrating ADCs, monolithic T1 interfaces and
the industry's first implementations of "delta sigma" oversampling A-to-D converters.
Headquartered in Austin, Texas, Crystal sells its products worldwide through a network of manufacturer's representatives. Crystal's entire marketing and sales organization is committed to providing quality products and reliable, rapid service.

1-4

.-_
._._
..--__.._-_.
...

QUALITY AND RELIABILITY INFORMATION

QUALITY AND RELIABILITY INFORMATION
Crystal Semiconductor is committed at every
level of the company to the highest possible
standards of quality and reliability in its products. This commitment is evident in all phases of
operations: initial product definition, design, fabrication, assembly, test, qualification and customer service. Product quality and reliability are
active concerns of each Crystal employee. Quality is ingrained in every operation throughout the
product life cycle. Some of the key operations
are discussed below.

In Product Definition
To ensure maximum system performance,
Crystal works with users to identify and quantify
the parameters, including quality and reliability
issues, that best serve customer needs. Quality
and reliability become part of the design goals,
along with electrical performance and cost.

In Design
Conservative CMOS design rules are the basis
for all current Crystal products. In addition, extensive use is made of proven standard cells to
drastically reduce the possibility of design errors.
Each pin in every SMART Analog product is designed to meet ESD levels of at least 2500V
when tested per MIL STD 883C, Method 3015.
Each pin is also designed to withstand more than
200mA of DC latch-up current.
Crystal SMART Analog design architectures
provide quality and reliability comparable to
leading digital devices and memories. This is far
superior to traditional analog ICs and hybrids.
Designs which use digital error correction
achieve stable performance over time and temperature by taking advantage of digital controls
that are insensitive to parametric analog problems such as leakages and shifts in threshold
voltage. Using Crystal devices, designers have
Q&R1

fewer error sources to consider. The result is a
less complicated, more reliable system.

In Fabrication and Assembly
Crystal ensures reliable delivery of quality parts
by accessing established foundries in multiple
locations worldwide. Each fabrication facility is
qualified by Crystal. Assembly is performed
both domestically and offshore under carefully
documented and well-controlled conditions.
Wafer fabrication and assembly processes
undergo in-line quality inspections. Wafers are
inspected optically to guidelines based on MIL
STD 883C, Method 2010. Each die is electrically tested using proprietary test circuits that
verify key parameters. Following assembly,
packages are subjected to a variety of mechanical inspections to verify integrity and insure high
quality. (For example, x-ray inspection is one of
the standard production tests.)

In Test
In a break from traditional analog components,
Crystal's SMART Analog products include basic
test capabilities designed into each chip. Crystal's in-process quality assurance program uses
this designed-in testability to monitor and track
the performance and quality of these complex
circuits. Finished packaged components are
tested 100 percent electrically, over temperature
where critical parameters are involved. With
these extensive quality programs, Crystal guarantees outgoing electrical quality levels on all
data sheet specifications to a 0.065 percent AQL
level over the full specified temperature range.
Throughout the assembly and test phases, traceability to the original wafer lot is carefully maintained.

..

-___

.._-_.
. ..--_
.....,.

..,

QUALITY AND RELIABILITY INFORMATION

In Product Qualification
Before any Crystal product is released to production and shipped in volume, it must undergo
a thorough qualification program. Crystal has
separate qualification criteria to address both
long-term reliability and infant mortality so that
the sources of failure are identified and eliminated. Crystal uses military specifications as the
guidelines for reliability tests, methods and procedures. (See Qualification Criteria Table)
To ensure reliability of the design and processes, full
qualification requires that three non-consecutive lots
are used during the qualification program. Fabrication and assembly facilities are audited every six
months and routinely monitored. Any major design
or process changes are re-qualified.
These steps guarantee that Crystal products
maintain the high standards of reliability designed-in from the start.
In Customer Service
Compliance with purchasing requirements is
ensured through the use of Crystal's
computerized system "Compass" (Crystal Online Marketing, Production, and Sales System).
This processing system ensures that all orders
are entered correctly, scheduled properly, produced according to schedule, and shipped with
zero discrepancies.
All systems and procedures at Crystal
Semiconductor are aimed at continuously
improving the quality and reliability of our products and services to meet the needs of our customers.
Crystal's philosophy on quality is to anticipate
problems and develop systems and controls to
alleviate possible problems. It is a well stated
fact by Juran and Deming, two of the nation's
foremost experts on quality, that 85% of all quality problems are system related and 15% are
1-6

worker related. Therefore, Crystal devotes its
major quality efforts toward preventing system
related quality problems.
Crystal has a very aggressive audit program in
place. Monthly internal audits are performed to
insure compliance to the extensive documentation of instructions and criteria for testing and
inspection. Semi-annual vendor audits are performed on the assembly and fabrication foundries. Vendor audits insure the adequacy and
compliance of specifications, product flow,
training, process controls and cleanliness. All
internal and external audits have provisions for
ratings and a system for corrective action
requirements. These frequent audits by assembly,
fabrication and quality engineers maximize
system quality compliance.
As an added measure of continued high quality
from assembly and fabrication foundries, thorough incoming inspections are performed. Wafer
level optical inspection is based upon guidelines
of MIL STD 883C, METHOD 2010. Test die or
scribe line monitors are electrically tested to verify compliance to key process parameters based
upon design rule specifications. These electrical
parameters include threshold voltages, breakdown
voltages, material resistance, and contact resistance. Assembly packaging inspection includes
external visual, marking permanency, solderability, x-ray, hermeticity, die shear, wirepull and internal visual.
Preventive measures are very much in force in
the final test area. Equipment calibration and
preventive maintenance procedures are strictly
adhered to. Handling procedures for Electrostatic
Discharge are in place throughout the test areas.
Non-conforming material is segregated until disposition by a material review board. There are
controlled procedures for releasing new test programs and new test equipment to the production
environment. In summary, Crystal Semiconductor is committed to meet the quality requirements of its customers.
Q&R1

..--------------------

QUALITY AND RELIABILITY INFORMATION

Qualification Criteria Table
Production Production
Quality Performance
Outgoing Quality (elec./Vis-mech/ship.)
Fault Coverage (Digital)
Datasheet Test Coverage (Digital)
Datasheet Test Coverage (Analog)
ESD - Human Body Model
ESD - Machine Model
Latchup - Power Supply1
Latchup - 1/0 1
Reliability Performance
Infant Mortality (48hrs@125°C or equivl
Early Life (168hrs@125°C or 1yr. equivi
Operating Life (1000hrs@125°C or 10yr, equivi
Moisture Performance
Moisture Resistance - THB (plastic pkgs)
Autoclave (plastic pkgs)

; Crystal Spec.
Datasheet
Datasheet
MIL 3015
MIL3015
JEDEC 17

.~.E[)EG .17..

........

Level I

1000

500

nla

nla

100%
100%
1500

100%
100%
2000

100
95%
100%
100%
4000
300
Vcc+50%

--

--

Vcc+1V
+50

Vcc+50%
+100

1/161'

500

±200

DPM

%
%
%
V
V
V
mA

1000
300

DPM
FITS
FITS

'"

; JEDEC 22B

500/5%

1k15%

1k13%

hrs/%LTPD per lot5

;. J~[)E.C.?i2.B . .L-""96"'/!<5°.!.!Yo'-------'1"'4"'41,,5'-''Yc''-o_--'1'''44I3='-'°Ic''-o...J hrs/%LTPD per

Product Integrity
Design Rule and LVS Checks
Design for Reliability & Packaging
Product Characterization
Test guardbands

.., ...

Q&R1

Level II

... ~I)., .1.09?. '--....:5~0:.::c0_ _--'3::..:0~0'--_--'-10::..:0'----'

. . , . ..

Notes: 1.
2.
3.
4.
5.

Level III

...
MIL 1005
MIL 1005

Mechanical Performance
Temp Cycle (plastic pkgs)
Thermal Shock (plastic pkgs)
Temp Cycle wI Hermeticity (hermetic pkgs)
Thermal Shock wI Hermeticity (hermetic pkgs)
Soak &VPR (surface mount plastic pkgs)
Xray
Dimensions
Solderability
Lead Integrity & Lead Pull
Mark Permanency

Construction Analysis
Wafer cross section & topo
SEM metallization
Package

World
Class

MIL 1010
MIL 1011
MIL1010/14
; MIL 1011/14
; Crystal Spec.
; Crystal Spec.
MIL 2016
MIL 2003
MIL 2004
.... ~!L?q1? ..

500/5%
200/5%
500/5%
200/5%
3/5%

1k15%

500/5%
1k15%

500/5%
3/3%

1k13%
1k13%
1k13%
1k13%

3/1%

2.50%
2.50%
2.50%
2.50%
2.50%

2.50%
2.50%
2.50%
2.50%
2.50%

0.65%
0.65%
0.65%
0.65%
0.65%

yes
yes
limited
some

yes
yes
full
100%

yes
yes
statistical
100%

yes
yes
yes

yes
yes
yes

yes
yes
yes

#cy/%LTPD per
#cy/%LTPD per
#cyfOIoLTPD per
#cyfO/oLTPD per
#cyfOIoLTPD per
%AQL per lot5
%AQL per lot5
%AQL per lot5
%AQL per lot5
%AQL per lot5

lo~
lot5
lot5
lot5
lot5
lot5

.

. ..
; Crystal Spec.
; Crystal Spec.
; Crystal Spec.

; .C;:ry~t!l! .l?P~~, .
.,',.,.,""',

..

; Crystal Spec.
MIL 2018
; .C;:m.taJl?p~,

at High Temperatures (exc. Lev.lV)
Point Estimate
55°C, 0.7eV, 60%UCL
#acceptln
LTPD and AGL criteria in table above apply to each lot tested.
CUM LTPD and AQL numbers are also required for Level II:
Individual Lot
Cum Lot ReQuirement
5% LTPD
3% LTPD
3% LTPD
1% LTPD
1.0% AQL
2.5% AQL

1-7

_........._.-........
..__..
..,..,

• Notes.

1-8

..,-_
__

.--.._--.
...-.
....

DATA ACQUISITION DATA BOOK CONTENTS

•

GENERAL INFORMATION
DATA ACQUISITION
General Purpose
Industrial Measurement
Seismic
High Speed

2

III:

AUDIO PRODUCTS
Consumer/Professional
Broadcast
Multimedia

•

COMMUNICATIONS PRODUCTS
Infrared Transceiver
Echo Cancellers
Communications Codecs
EthernetlCheapernet
Telecom
APPLICATION NOTES

III

APPENDICES
Product Category Levels
Reliability Calculation Methods
Package Mechanical Drawings
Standard Military Drawings

III

•

SALES OFFICES

2-1

.-_ -_-_

.... ....
........
.......,..,
~

DATA ACQUISITION PRODUCTS

GENERAL PURPOSE AID CONVERTERS
CS531716-bit Voice Band ADC
The CSS317 is well suited for a wide range of voiceband applications, from sprechrecognition to passive
sonar. An on-chip PWClock generator makes the
part perfect for high-performance moderns. The device features a 20 kHz word rate, a 10kHz bandwidth, 84 dB dynamic range and 80 dB THO.

CS5012A, CS5014, CS5016 SAR Family
The CSS012A, CSS0l4 and CSS0l6 converters have
12, 14 & 16 bits of resolution respectively, with conversion times of 7 f.lS to 16 f.lS. On-chip self-calibration
ensures that linearity, offset and full-scale errors remain within specification, with no missing codes.

CS5102A 16-bit 20 kHz Low Power ADC
The CSS102A is a low power version of the
CSS101A. Requiring only 44 mW from ±5 V supplies, along with a 1 mW power down mode, the
CSS102A is ideal for battery powered applications.

SDecifications
Resolution (bits)
Application
Throuahout (kHz)

CS5317

CS5012A
CS5014
CS5016

CS5030, CS5031, CS5032 12-bit 500kHz ADCs
The CSS03011 feature a 1 ppmrC on-chip reference. This yields a 12-bit ADC which has a total
unadjusted error (including reference error) of
<±a.S LSB over the military temperature range.
The CSS032 is a low cost version with a 60
ppmrC reference.

CS7870, CS7875 12-bit 100 kHz Sampling ADC
The CS7870 and CS787S are complete monolithic
CMOS ADCs providing 100 kHz throughput.
Conversion results are available in either 12-bit
parallel, two 8-bit bytes, or serial data. The
CS7870 has a ±3V analog input range while the
CS787S accepts input signals from OV to +SV.
CS5102A

CS5101A
CS5126

CS5030
CS5031
CS5032

CS7870
CS7875

16

12114116

16

16

12

12

Modem

GP

GP

GP

GP

GP

20

100156150
7/14116
.0061.0021

20

100

500

100

40

8

2

10

.0015%

.0015%

.25 LSB

0.25 LSB
0.5

Conversion Time (115)
Integral

CS5101A, CS5126 16-bit 100 kHz ADC
The CSS101A is a 16-bit ADC capable of converting in 8 JlS, yielding sample rates of 100kHz.
A 2~channel analog input mux is included. The
CSS126 is a low-cost version of the CSS10lA, intended for signal processing applications.

Non~Linearity

.001%

Differential (±LSB)
Non·Linearitv

NMC

0.25/0.25/
NMC

NMC

NMC

0.5

No Missin!! Codes

16

12114116

16

16

12

12

.007

.0081.003/
.001

.001

.001

.01

.01

80

73183192

92

92

72

72

84

73183192

92

92

72

73

Total Hannonic
Distortion (%)
Signal·to·Noise
I plus Distortion -(dB)

Dvnamic Ran!!e (dB)
Power Needed (mW)
Conversion Method

220

150

44

280

Delta
Si!!ma

Succ.
Approx.

Succ.
Approx.

Succ.
Approx.

or

or

or
or

./
./

Power Down Mode
On-Chip Sample
and Hold
On-Chip V. Ref

85
Succ.
. j\l'l'rox.

88
Succ.
_.A.pj)rox .

or

./

or
or
or

or
or
or

or

or

Dvnamicallv Tested

./

./

./

or

./

./

Temperature Range

Com
Ind

Com
Ind
Mil

Com
Ind
Mil

Com
Ind
Mil

Ind
Mil

Ind
Mil

Statically Tested

Number of Pins (DIP)
Packages

18

40

28

DIP
SOIC

DIP
PLCC
LCC

DIP
PLCC
LCC

NMC - No MISSing Codes

2-2

28
DIP
PLCC
LCC
GP - General Purpose

24

24

DIP
SOIC

DIP
PLCC

_.-_..---__.._-...
._.-.

DATA ACQUISITION PRODUCTS

INDUSTRIAL MEASUREMENT AND SEISMIC
AID CONVERTERS

chip software programmable instrumentation amplifier, choice of AC or DC bridge excitation,
software selectable reference and signal demodulation.

CS5501, CS5503 16/20-hit DC Measurement ADC
The CS5501 and CS5503 feature an on-chip, 6pole, low-pass filter, with adjustable corner frequencies from 0.1 Hz to 10 Hz. The ADC's
achieve linearity errors of 0.0007%, with no missing codes. A highly flexible serial interface, along
with 25 mW power consumption, all in a 20 pin
package, make the parts ideal for weigh scale and
process control applications.

CS5321, CS5322, CS5323, CS5324
24-hit Variable Bandwidth ADC
The CS5321 or CS5323 modulator, combined with
the CS5322 digital filter, offers >120 dB dynamic
range in the DC to 500 Hz frequency band. Seven
different filter comer frequencies and output update
rates are offered, allowing the ADC to be optimized
for different types of seismic measurements. The
CS5324 includes a modulator and the first stage of
digital filtering, allowing users to implement their
own final filter stage.

CS550415/6n1819 1, 2 & 4-channel, 16/20-hit DC
Measurement ADC
Very low power consumption of 1.7 mW, along
with an optional I, 2, or 4-channel input mux,
make this part ideal for process control and hand
held meter applications. These ADC's are available in 16 or 20 bit versions.

CS5542, CS5543, 22-hit, 8-channel Data Acquisition System
The CS5542 is a 2-channel, 5th order delta-sigma
modulator intended for direct digitization of transducer
currents. The CS5543 is an 8-channel digital FIR filter. Up to four CS5542's may be connected with one
CS5543 to fonn an 8-channel data acquisition system.
The output word rate is 1000 Hz per channel.

CS5516, CS5520 16/20-hit Bridge Transducer ADC
The CS5516 and CS5520 are complete solutions for
digitizing low level signals from strain gauges, load
cells and pressure transducers. The devices offer an onCS5504
CS5505
CS5506

CS5507
CS5508
CS5509

Specifications

CS5501
CS5503

Input Bandwidth

10 Hz

10 Hz

12 Hz

500 Hz

Resolution (bits)

16/20

16/20

16/20

24

22

Seismic

DC Measurement

Application
Throughput (kHz)

CS5516
CS5520

DC Measurement

CS5321
CS5322

CS5323
CS5324

CS5542
CS5543
250/500 Hz

4

100/200Hz

60Hz

1KHz

Integral Non·Linearity

.0007%

.0015%

.0007%

.001%

Differential (±LSB)
Non-Linearity

0.125/
NMC

0.125

0.5

Total Harmonic
Distortion (%)

Conversion Method

0.5

.0003

Dynamic Range (dB)
Power Needed(mW)

NMC

25

3

120

113

40

150

80/75
Delta
Siqma

Delta

Delta

Delta

Si~ma

Si~ma

Si rna

Delta
Siqma

.(

.(

.(

.(

.(

.(

.(

.(

.(

.(

Power Down Mode
On-Chip Sample
and Hold
On-Chip V. Ref
On-ChigFiltering

.(

.(

.(

.(

.(

Ind, Mil

Ind

Ind

Ind

Ind

20

20/24

24

28

28144

DIP
SOIC

DIP
sale

PLCC

PLCC

Temperature Ranq€
Number of Pins (DIP)
Packages

.(

DIP
SOIC
NMC - No MISSing Codes

2-3

_-_

.... -..
.-........
.............

DATA ACQUISITION PRODUCTS

IDGH SPEED AID CONVERTERS
CS5412 12-bit 1 MHz ADC
Using a 2-step flash approach, the CS5412
achieves 12-bit performance at a 1 MHz sample
rate. Self calibration ensures accuracy over time
and the military temperature range. Available in
both DIP and J-lead LCC packages, with on-chip
S/H, the IC offers a very compact ADC solution.

CS5490 12-bit 20MHz ADC
The CS5490 is a 12-bit sampling ADC capable of
20 Msps conversion rates. Digital inputs are
CMOS and TTL compatible, and the digital outputs are CMOS compatible. Output data is available in offset binary format.
CDBCAPTURE SYSTEM

Data Capture and Interface Board for a PC
CS5480, CS5481 10-bit 40/20 MHz ADC
The CS5480 is a monolithic CMOS lO-bit sampling ADC capable of 40 Msps conversion rates.
The CS5481 is a lO-bit sampling ADC capable of
20 Msps conversion rates. Digital inputs are
CMOS and TTL compatible, and the digital outputs are CMOS compatible. Output data is available in offset binary format.

The CAPTURE interface board is a development
tool that can be easily interface to Crystal Semiconductor Evaluation boards. Application software,
developed with Lab Windows, adjusts the CAPTURE interface board for the appropriate signal timing and polarity, coding format and number of bits.

Specifications

CS5412

CS5480

CS5481

CS5490

Inout Bandwidlh

4 MHz

200 MHz

200 MHz

200 MHz

12

10

10

12

Application

Resolution (bits)

GP Fast

High Soeed

High Soeed

High S~eed

Throughout

1 MHz

40 MHz

20 MHz

20 MHz

1

1

1

1

0.9

0.5

0.5

0.5

Integral Non-Linearity (±LSB)
Differential Non-Linearity (tLSB)

12

10

10

12

-78 dB

-54 dB

-54 dB

-63 dB

Signal-to-Noise plus Distortion (dB)

70

58

58

62

Dynamic Range (dB)

70

62

62

70

No Missing Codes
Total Harmonic Distortion

Power Needed (mW)
Conversion Method
On-Chip Sample and Hold

750

375

225

225

2-Step
Flash

Pipeline

Pipeline

Pipeline

.r
.r

.r
.r

.r
.r
Ind

.r

On-Chip V. Ref
Temperature Range

Com
Ind
Mil

Ind

Ind

Number of Pins

40/44

28

28

44

PLCC

PLCC

PLCC

Packages

2-4

DIP
JLCC
NMC - No MISSing Codes

GP - General PUipose

_........--..
...............
...........

~

DATA ACQUISITION PRODUCTS

DATA ACQUISITION PRODUCTS

NEW
NEW

NEW

NEW
NEW
NEW
NEW

NEW

NEW
NEW

NEW

- Introduction, Contents and User's Guide
- CS5012A14/6 16, 14, & 12-Bit, Self-Calibrating AID Converters
- CDB5012A14/6 Evaluation Board for CS5012A14/6
- CS5030/l 12-Bit, 500 kHz, Sampling AID Converters
- CS5032 12-Bit, 500 kHz, Sampling AID Converters
- CDB5030/112 Evaluation Board for CS5032
- CS5101A12A 16-Bit, 100 kHZ/20 kHz AID Converters
- CDB5101A12A Evaluation Board for CS5101A12A
- CS5126 16-Bit, Stereo AID Converter for Digital Audio
- CDB5126 16-Bit, Stereo AID Converter for Digital Audio
- CS5317 16-Bit, 20 kHz Oversampling AID Converter
- CDB5317 Evaluation Board for CS5317 .
- CS5321 High Dynamic Range Delta-Sigma Modulator
- CDB5321 Evaluation Board for CS5321 .
- CS5322/3 24-Bit Variable Bandwidth AID Converter
- CDB5322/3 Evaluation Board for CS5322/3
- CS5324 120 dB, 500 Hz Oversampling AID Converter
- CDB5324 Evaluation Board for CS5324 .
- CS5412 12-Bit, 1MHz Self-Calibrating AID Converter
- CDB5412 Evaluation Board for CS5412
- CS5480 10-Bit, 40 MHz, AID Converter
- CS5481 lO-Bit, 20 MHz, AID Converter
- CS5490 12-Bit, 20 MHz, AID Converter
- CS550113 Low-Cost, 16 & 20-Bit Measurement AID Converter
- CDB5501/3 Evaluation Board for CS550113
- CS5504 Low Power, 20-Bit AID Converter .
- CDB5504 Evaluation Board for CS5504 .
- CS5505/6/7/8 Very Low Power, 16-Bit and 20-Bit AID Converters
- CDB5505/617/8 Evaluation Board for CS5505/617/8
- CS5509 Single Supply, 16-Bit AID Converter
- CDB5509 Evaluation Board for CS5509 .
- CS5516120 16-Bitl20-Bit Bridge Transducer AID Converters
- CDB5516120 Evaluation Board for CS5516120
- CS5542 Dual Channel Current-Input Modulator .
- CS5543 8-Channel Digital Decimation Filter
- CS7870/5 12-Bit, 100 kHz Sampling AID Converter
- CDB7870 Evaluation Board for CS7870/5
- CDBCAPTURE Evaluation Board

;~~

2-48
2-55
2-81
2-104
2-113
2-149
2-159
2-178
2-189
2-212
2-219
2-233
2-245
2-272
2-283
2-305
2-315
2-335
2-345
2-355
2-365
2-367
2-407
2-421
2-444

2-451
2-482
2-489
2-511
2-519
2-549
2-559
2-561
2-563
2-588
2-597

2-5

~,,'
~

. ____

-.- ..
....
...
..........
~--

DATA ACQUISITION PRODUCTS

• Notes·

2-6

""" .
."""............

~ ~.
••~

.",

~ • • J8fJ8f

CS5016 CS5014 CS5012A

•

Semiconductor Corporation

16, 14 & 12-8it, Self-Calibrating AID Converters
Features

General Description
The CSS012A114/16 are 12, 14 and 16-bit monolithic
analog to digital converters with conversion times of
7.2I1S, 14.2Sl1s and 16.2Sl1s. Unique self-calibration circuitry insures excellent linearity and differential nonlinearity, with no missing codes. Offset and full scale
errors are kept within 1/2 LSB (CSS012A/14) and
1 LSB (CSS016), eliminating the need for calibration.
Unipolar and bipolar input ranges are digitally selectable.

• Monolithic CMOS AID Converters
Microprocessor Compatible
Parallel and Serial Output
Inherent Track/Hold Input
• True 12, 14 and 16-Bit Precision
• Conversion Times:
CS5016 16.251ls
CS5014 14.25 Ils
CS5012A 7.20IlS
• Self Calibration Maintains Accuracy
Over Time and Temperature

The pin compatible CSS012A114/16 consist of a DAC,
conversion and calibration microcontroller, oscillator,
comparator, microprocessor compatible 3-state 1/0,
and calibration circuitry. The input track-and-hold, inherent to the devices' sampling architecture, acquires
the input signal after each conversion using a fast
slewing on-chip buffer amplifier. This allows throughput
rates up to 100 kHz (CSS012A), S6 kHz (CSS014) and
SO kHz (CSS016).

• Low Power Dissipation: 150 mW

An evaluation board (CDB5012/14/16) is available
which allows fast evaluation of ADC performance.

• Low Distortion

ORDERING INFORMATION: Pages 2-4S, 2-46, & 2-47

HOLD

CS

RD

AO

BP/UP RST

BW INTRLV CAL

EOT

EOC

SCLK SDATA
2
3

ClKIN

4

20

5
6

REFBUF

29

7
8

VREF

28

9
12
13

AIN

CHARGE
REDISTRIBUTION
DAC

26

14
15
16

17

AGND

18
19
25
VA+

30
VA-

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

11
VD+

36

VD-

10

31

DGND

TST

DO (lSB) CS5016
D1
D2 (lSB) CS5014
D3
D4 (lSB) CS5012A
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15 (MSB)

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '9S
DS14F6

2-7

.... ...
. ....,,-._...,.
~

~~..,

..,

CSS012A

~..,

CS5012A ANALOG CHARACTERISTICS (TA =TMIN to TMAX; VA+, VD+ =5V;
VA-, VD-

=-5V; VREF =2.5V to 4.5V; felk =6.4 MHz for -7,4 MHz for -12; Analog Source Impedance =200n)
CS5012A-K
Parameter"

Min

Typ

Max

CS5012A-B
Min

o to +70

Specified Temperature Range

Typ

Max

-40 to +85

CS5012-T
Min

Typ

Max

Units

-55 to +125

°C
LSB12
ALSB12

Accuracy
Linearity Error
Drift

(Note 1)
(Note 2)

±1/4
±1/8

±1/2

±1/4 ±1/2
±1/8

±1/4
±1/8

Differential Linearity
Drift

(Note 1)
(Note 2)

±1/4 ±1/2
±1/32

±1/4 ±1/2
±1/32

±1/4 ±1/2 LSB12
ALSB12
±1/32

Full Scale Error
Drift

(Note 1)
(Note 2)

±1/4 ±1/2
±1/16

±1/4 ±1/2
±1/16

±1/4
±1/8

Unipolar Offset
Drift

(Note 1)
(Note 2)

±1/4 ±1/2
±1/16

±1/4 ±1/2
±1/16

±1/4 ±1/2 LSB12
ALSB12
±1/16

Bipolar Offset
Drift

(Note 1)
(Note 2)

±1/4 ±1/2
±1/16

±1/4 ±1/2
±1/16

±1/4 ±1/2 LSB12
ALSB12
±1/16

Bipolar Negative Full-Scale Error(Note 1)
(Note 2)
Drift

±1/4 ±1/2
±1/16

±1/4 ±1/2
±1/16

±1/4 ±1/2 LSB12
ALSB12
±1/16

Total Unadjusted Error
Drift

±1/4
±1/4

±1/4
±1/4

±1/4
±1/4

LSB12
ALSB12

92
88

dB
dB

0.008

%

73
13

dB
dB

45
90

I1Vrms
I1V rms

(Note 1)
(Note 2)

±1/2

±1/2

LSB12
ALSB12

Dynamic Performance (Bipolar Mode)
Peak Harmonic or
Spurious Noise
Full Scale, 1 kHz Input
Full Scale, 12 kHz Input

(Note 1)
84
84

84
84

0.008

Total Harmonic Distortion
Signal-to-Noise Ratio
1 kHz, 0 dB Input
1 kHz, -60 dB Input

(Note 1)

Noise
Unipolar Mode
Bipolar Mode

(Note 3)

Notes:

92
88

72

73
13
45
90

92
88

84
84

0.008
72

73
13
45
90

72

1. Applies after calibration at any temperature within the specified temperature range.

2. Total drift over specified temperature range since calibration at power-up at 25°C
3. Wideband noise aliased into the baseband. Referred to the input.
• Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.

2-8

DS14F6

.... ...
. .,.,-_
.....-..
....
~

~~

CS5012A

~~

CS5012A ANALOG CHARACTERISTICS (continued)
CS5012A-K
Parameter*

Min

Typ

Max

o to +70

Specified Temperature Range

CS5012A-8
Min

Typ

Max

-40 to +85

CS5012-T
Min

Typ

Max

Units

-55 to +125

°C

Analog Input

Aperture Time

25

25

25

ns

Aperture Jitter

100

100

100

ps

Input Capacitance
Unipolar Mode CS5012
CS5012A
Bipolar Mode CS5012
CS5012A

(Note 4)
275
103
165
72

375
137
220
96

275
103
165
72

375
137
220
96

275
103
165
72

375
137
220
96

pF
pF
pF
pF

Conversion & Throughput

Conversion Time
Acquisition Time
Throughput

-7
(Notes 5 and 6)
-12
-7
-12

(Note 6)

-7
-12

(Note 6) 100
62.5

7.2
12.25
2.5
3.0

7.2
12.25

2.8
3.75

2.5
3.0

~s

2.8
3.75

100
62.5

12.25

~s

3.75

~s

~s

3.0

kHz
kHz

62.5

Power Supplies

DC Power Supply Currents
IA+
IA(CS5012)
10+
(CS5012A)
10+
10-

(Note 7)
12
-12
3
6
-3

Power Dissipation

(Note 7)

Power Supply Rejection
Positive Supplies
Negative Supplies

(Note 8)

Notes:

DS14F6

150
84
84

19
-19
6
7.5
-6

12
-12
3
6
-3

19
-19
6
7.5
-6

12
-12
3
-3

-6

mA
mA
mA
mA
mA

250

150

250

150

250

mW

84
84

84
84

19
-19
6

dB
dB

4. Applies only in track mode. When converting or calibrating, input capacitance will not exceed 15 pF.
5. Measured from falling transition on HOLD to falling transition on EOC.
6. Conversion, acquisition, and throughput times depend on ClKIN, sampling, and calibration conditions.
The numbers shown assume sampling and conversion is synchronized with the CS5012A114/16 's
conversion clock, interleave calibrate is disabled, and operation is from the full-rated, external clock.
Refer to the section Conversion TimeIThroughput for a detailed discussion of conversion timing.
7. All outputs unloaded. All inputs CMOS levels.
8. With 300 mV pop, 1 kHz ripple applied to each analog supply separately in bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 13 shows a plot of typical power supply
rejection versus frequency.

2-9

......,.., ...
.-....,--._..
..,-~

~

CSS014

~

CS5014 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD- = -5V; VREF = 4.5V; eLKIN = 4 MHz for -14,2 MHz for -28; Analog Source Impedance = 2000)
CS5014-K

Parameter*

Min

Typ

CS5014-B

Max

Min

o to +70

Specified Temperature Range

Typ

CS5014-S, T

Max

Min

Typ

Max

Units

-40 to +85

-55 to +125

°e

±1/4

±1/4
±1/2
±1/8

LSB14
LSB14
aLSB14

Accuracy

Linearity Error

K,B, T
S

Drift

(Note 1)

±1/4

±1/2

±1/2

±1/2
±1.5

(Note 2)

±1/8

±1/8

Differential Linearity
Drift

(Note 1)
(Note 2)

±1/4 ±1/2
±1/32

±1/4 ±1/2
±1/32

±1/4 ±1/2 LSB14
aLSB14
±1/32

Full Scale Error
Drift

(Note 1)
(Note 2)

±1/2
±1/4

±1/2
±1/4

±1

±1/2
±1/2

(Note 1)

±1/4 ±3/4

±1/4

±3/4

(Note 2)

±1/4

±1/4

±1/4 ±3/4 LSB14
LSB14
±1
aLSB14
±1/2

(Note 1)

±1/4

±3/4

±1/4

(Note 2)

±1/4

Unipolar Offset

K,B, T
S

Drift
Bipolar Offset

K,B, T
S

Drift

Bipolar Negative Full-Scale Error(Note 1)
K,B, T
S
(Note 2)
Drift
Total Unadjusted Error
Drift

±3/4

±1/4
±1/2

±1

LSB14
aLSB14

±3/4
±1

LSB14
LSB14
aLSB14

±1
±1.5

±1/2

±1/4

±1/4

±1/2

LSB14
LSB14
aLSB14

±1
±1/2

±1
±1

±1
±1

LSB14
aLSB14

98

dB
dB
dB
dB

±1/2

(Note 1)
(Note 2)

±1

±1

±1/2

±1

±1/2

Dynamic Performance (Bipolar Mode)

Peak Harmonic or
Spurious Noise
Full Scale, 1 kHz Input
Full Scale, 12 kHz Input

(Note 1)
K,B, T
S
K, B, T
S

94

98

94

98

84

87

84

87

0.003

Total Harmonic Distortion
Signal-to-Noise Ratio
1 kHz, 0 dB Input

(Notes 1 and 9)
K, B, T
S

1 kHz, -60 dB Input
Noise
Unipolar Mode
Bipolar Mode
Notes:

82

84

94
85
84
80

0.003
82

84

82
80

87
0.003

0/0

84

dB
dB
dB

23

23

23

45
90

45
90

45
90

(Note 3)

IlVrms
IlVrms
9. A detailed plot of S/(N+D) vs. input amplitude appears in Figure 26 for the eS5014 and Figure 28
for the eS5016 .

• Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.
2-10

DS14F6

-. ....,__..w.._.
.......~-

~~

CSS014

~-

CS5014 ANALOG CHARACTERISTICS (continued)
CS5014-K

Parameter*

Min

Specified Temperature Range

Typ

CS5014-B

Max

Min

Typ

CS5014-S, T

Max

Min

Typ

Max

Units

o to +70

-40 to +85

-55 to +125

DC

25

25

25

ns

100

100

100

ps

Analog Input
Aperture Time
Aperture Jitter
Input Capacitance
Unipolar Mode
Bipolar Mode

(Note 4)
275
165

375
220

275
165

375
220

275
165

375
220

pF
pF

14.25
28.5

I1S
I1s

3.75
5.25

I1s
I1s

Conversion & Throughput
Conversion Time

-14 (Notes 5 and 6)
-28

Acquisition Time

-14
-28

(Note 6)

Throughput

-14
-28

(Note 6) 55.6
27.7

14.25
28.5
3.0
4.5

14.25
28.5

3.75
5.25

3.0
4.5

3.75
5.25

55.6
27.7

3.0
4.5
55.6
27.7

kHz
kHz

Power Supplies
DC Power Supply Currents
IA+
IA10+
10-

(Note 7)

Power Dissipation

(Note 7)

Power Supply Rejection
Positive Supplies
Negative Supplies

(Note 8)

DS14F6

9
-9
3
-3

19
-19
6
-6

9
-9
3
-3

19
-19
6
-6

9
-9
3
-3

19
-19
6
-6

mA
mA
mA
mA

120

250

120.

250

120

250

mW

84
84

84
84

84
84

dB
dB

2-11

•

. .......

... .

.
.., ...........,
~

~~~

~~

CSS016

=

=

CS5016 ANALOG CHARACTERISTICS (TA TMIN to TMAX; VA+, VD+ 5V;
VA-, VD- = -5V; VREF = 4.5V; CLKIN = 4 MHz for -16,2 MHz for -32; Analog Source Impedance == 2000;
Synchronous Sampling.)
CS5016-J, K
Parameter*

Min

Typ

Max

CS5016-A, B
Min

o to +70

Specified Temperature Range

Typ

Max

-40 to +85

CS5016-S, T
Min

Typ

Max

Units
DC

-55 to +125

Accuracy
Linearity Error

J, A, S

(Note 1)

0.002 0.003
0.001 0.0015

K,B, T
Drift

(Note 2)

Differential Linearity
Full Scale Error

(Note 10)

J, A, S

0.002 0.003
0.001 0.0015

±1/4

±1/4

16

(Note 1)

0.002 0.0076 %FS
0.001 0.0015 %FS
±1/4
8LSB16

16

16

Bits

±2
±2
±1

±3
±3

±1
±1
±1

±2
±3/2

±1
±1
±1

±3
±3

±1
±1

±2
±3/2

±1
±1
±2

±2
±2

±1
±1

(Note 2)

±1
±1
±1

Bipolar Negative Full-Scale Error(Note 1)
J, A, S
K,B, T
Drift
(Note 2)

±2
±2
±1

±3
±3

±2
±2
±2

±3
±3

K,B, T
Drift
Unipolar Offset

(Note 2)

J, A, S

(Note 1)

K,B, T
Drift
Bipolar Offset

(Note 2)

J, A, S

(Note 1)

K, B, T
Drift

±2
±2

±3
±3

±2
±2

±1

±4
±3

LSB16
LSB16
8LSB16

±4
±3

LSB16
LSB16
8LSB16

±4

LSB16
LSB16
8LSB16

±2

±2
±2

±2

±2

LSB16
LSB16
8LSB16

100
104
88
91

dB
dB
dB
dB

0.002
0.001

%
%

90
92
30
32

dB
dB
dB
dB

35
70

J.lVrms
J.lVrms

±2
±2

±5
±3

Dynamic Performance (Bipolar Mode)
Peak Harmonic or
Spurious Noise
Full Scale, 1 kHz Input
Full Scale, 12 kHz Input
Total Harmonic Distortion
Full Scale, 1 kHz Input

(Note 1)

J, A,
K,B,
J, A,
K, B,

S 96
T 100
S 85
T 85

J, A, S
K,B, T

Signal-to-Noise Ratio
1 kHz, 0 dB Input

(Notes 1 and 9)
J, A, S
K, B, T
J, A, S
1 kHz, -60 dB Input
K,B, T

Noise
Unipolar Mode
Bipolar Mode

100
104
88
91

96
100
85
85

0.002
0.001
87
90

90
92
30
32

100
104
88
91

92
100
82
85

0.002
0.001
87
90

90
92
30
32

84
90

(Note 3)
35
70

35
70

Notes: 10. Minimum resolution for which no missing codes is guaranteed
• Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.

2-12

DS14F6

.. ........,..
. ...,.,-_
~.-

..,

~~..,

CS5016

~~

CS5016 ANALOG CHARACTERISTICS (continued)
CS5016-J, K

Parameter*

Min

Typ

Max

o to +70

Specified Temperature Range

CS5016-A, B

Min

Typ

Max

-40 to +85

CS5016-S, T

Min

Typ

Max

-55 to +125

Units
°C

Analog Input
Aperture Time

25

25

25

ns

Aperture Jitter

100

100

100

ps

Input Capacitance
Unipolar Mode
Bipolar Mode

(Note 4)
275
165

375
220

275
165

375
220

275
165

375
220

pF
pF

16.25
32.5

JLs
JLS

3.75
5.25

JLs
JLs

Conversion & Throughput
Conversion Time

-16 (Notes 5 and 6)
-32

Acquisition Time

-16
-32

(Note 6)

Throughput

-16
-32

(Note 6)

16.25
32.5
3.0
4.5

16.25
32.5

3.75
5.25

3.0
4.5

3.75
5.25

50
26.5

50
26.5

3.0
4.5

kHz
kHz

50
26.5

Power Supplies
DC Power Supply Currents
IA+
IA10+
10-

(Note 7)

Power Dissipation

(Note 7)

Power Supply Rejection
Positive Supplies
Negative Supplies

(Note 8)

DS14F6

9
-9
3
-3

19
-19
6
-6

9
-9
3
-3

19
-19
6
-6

9
-9
3
-3

19
-19
6
-6

mA
mA
mA
mA

120

250

120

250

120

250

mW

84
84

84
84

84
84

dB
dB

2-13

....
... ..-...
._.
~~

..,

~

~~

CS5012A, CS5014, CSS016

..."

~~

SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%;
VA-, VD-

=-5V ±10%; Inputs:

logic 0

=OV, logic 1 =VD+; CL =50 pF, BW =VD+)

Parameter

Symbol

CS5012A ClKIN Frequency:
. Internally Generated:
Externally Supplied:
CS5014/5016 ClKIN Frequency:
Internally Generated:
Externally Supplied:

Min

Typ

1.75
100 kHz
100 kHz

-

6.4
4.0·

1.75
1
100 kHz
100 kHz

-

-

fcLK
-7
-12
fCLK
-14,
-28,
-14,
-28,

-16
-32
-16
-32

ClKIN Duty Cycle

40

Rise Times:
Fall Times:

Any Digital Input
Any Digital Output

trise

Any Digital Input
Any Digital Output

tfall

HOLD Pulse Width
Conversion Time:

Units

-

MHz
MHz
MHz

-

MHz
MHz
MHz
MHz

-

4
2

60

%

-

1.0

20

-

!is
ns

-

1.0

-

!is
ns

-

20

-

tc

ns

-

53/fcLK+235
61lfCLK+235
69/fcLK+235

ns
ns
ns

-

40

100

ns

4/fcLK-20

-

-

ns

10
10

-

ns
ns

thpw

1/fcLK+50

CS5012A
CS5014
CS5016

tc

49/fcLK+50
57lfCLK
65/fcLK

tdd
(Note 11)

tepw

Data Delay Time
EOC Pulse Width

-

Max

Set Up Times:

CAL, INTRlV to CS low
AO to CS and RD low

tcs
tas

20
20

Hold Times:

CS or RD High to AO Invalid
CS High to CAL, INTRlV Invalid

tah
tch

50
50

30
30

-

ns
ns

Access Times:

CS low to Data Valid

A,B,J,K
S, T
A,B,J,K
S, T

tea

90
115
90
90

120
150
120
150

ns
ns
ns
ns

Output Float Delay:
K, B
CS or RD. High to Output Hi-Z
T

ttd

-

90
90

110
140

ns
ns

-

21fcLK
21fcLK

-

-

ns
ns

21fcLK-50

21fcLK

-

ns

2/fcLK-100
tsh
2/fCLK
Notes: 11. EOC remains low 4 ClKIN cycles if CS and RD are held low. Otherwise, It returns high
within 4 ClKIN cycles from the start of a data read operation or a conversion cycle.

ns

RD low to Data Valid

Serial Clock

Pulse Width low
Pulse Width High

Set Up Times:

SDATA to SClK Rising

Hold Times:

2-14

SClK Rising to SDATA

tra

tpwl
tpwh
1$s

-

DS14F6

..__...
.... _.
_. ...........
__
-.-

CS5012A,CS5014,CS5016
Irise

Ifall

90%

90%

10%

•

10%

Rise and Fall Times

tpwl
SCLK

SDATA

Serial Output Timing

I+-- Ica -----'\

CS

I<-- Ira -----RD

/
- - lah

las-o

AO

00-015

r

Hi-Z

tfd
Hi-Z

------f--------~-------~
tcs----J

CAL, INTRLV

-------0

Ich

Read and Calibration Control Timing

HOLD

IC-------jt,>f 1 : : : : : . 3

55

- - - - - - --

,~~-~--+--,-4---~----t---+--~--~P---T--~
o

20

40

60
Is/2

80

100
Is

120

140

160

180

200

Input Frequency (kHz)

Figure 25. CS5012A High Frequency Input Performance
DS14F6

2-33

_._

...............
...... .
...............

CS5012A,CS5014,CSS01$

tOO dB ,----:----:----:---:-----,------,-------,

1
BOdB

1

1

1

OdB

1

- - - - - -

_ L _1_ -1 _ --L _ L

------

Sempling Rat.: 56 kHz
- - - - - - - - - - - - FuIiSeale:9Vp-p

-2OdB

- - - - - - - - - - - - s/(N+D):24.1dB

1

C

60 dB

+

Z

'iii 40 dB
20 dB

I

1

- I- -1- --f 1

- r

1

1

1

-40dB

+
Signal
Amplitude
Relative to
Full Scale

1

-1- -r-

1

1

1

1

----

-SOdB

-BOdB
-100dB

-12OdB

de~lkHZ
Input Frequency

Figure 27. CS5014 FFT plot with 1 kHz
-60 dB Input

Figure 26. CS5014 S/(N+D) vs. Input Amplitude
(9Vp-p Full-Scale Input)
tOOdB ,--_ _ _-,-----_ _ _-,--_ _ _ _ _--,

OdB

1
BOdB

z+

'iii 40 dB
20 dB

1

1

_ L _1_ -1 _ --L _
1

C60dB

1

1

1

- I- -1- --f 1

- r

1

1

+ t-

24kHz

1

1

1

- - - - - - - - - - - - - - - - - - - - - - -

Sampling Rate: 50kHz
FuIiScale:9Vp-p

- - - - - - - - - - - -

s/(N+D): 9.BdB

-40dB

Input
-Frequen

-I--r
1 - 1 -I'- - - - - -1

-2OdS

lE..kHz

-6OdS

Signal
Amplitude

-BOdB

Relative to
Full Scale

-100dS
-120dB
de

~1

25kHz - - '

kHz

Input Frequency

Figure 28. CS5016 S/(N+D) vs. Input Amplitude
(9Vp-p Full-Scale Input)

Signal to Noise + Distortion vs Signal Level
As illustrated in Figures 26 - 29, the CS5014/16's
on-chip self-calibration provides very accurate bit
weights which yield no degradation in quantization noise with low-level input signals. In fact,
quantization noise remains below the noise floor
in the CS5016, which dictates the converter's signal-to-noise performance.

CS5016 Noise Considerations
All analog circuitry in the CS5016 is wideband in
order to achieve fast conversions and high
throughput. Wideband noise in the CS5016 integrates to 35 flV rms in unipolar mode (70 flV rms
in bipolar mode). This is approximately 112 LSB

2-34

Figure 29. CS5016 FFT plot with 1 kHz
-80 dB Input

rms with a 4.5V reference in both modes. Figure
30 shows a histogram plot of output code occurrences obtained from 5000 samples taken from a
CS5016 in the bipolar mode. Hexadecimal code
80CD was arbitrarily selected and the analog input was set close to code center. With a noiseless
converter, code 80CD would always appear. The
histogram plot of the CS5016 has a "bell" shape
with all codes other than· 80CD due to internal
noise.
In a sampled data system all information about the
analog input applied to the sample/hold appears in
the baseband from de to one-half the sampling rate.
This includes high-frequency components which
alias into the baseband. Low-pass (anti-alias) filters

DS14F6

.. .

..,..,..,
. -*'--_._.
....
..,.., .....
..,~

CS5012A,CS5014,CS5016

Count

5000

~ CS5016

4000

3000

formed on the charge trapped on the capacitor array at the moment the HOLD command is given.
The charge on the array is ideally related to the
analog input voltage by Qin = -Vin X Ctot as
shown in Figure 2. Any deviation from this ideal
relationship will result in conversion errors even
if the conversion process proceeds flawlessly.

2000

1000

BOCA

BOCB

BOCC

BOCD

80CE

BOCF

BODO

Code (Hexadecimal)
Counts:

0

11

911

3470

599

9

o

Figure 30. Histogram Plot of 5000 Conversion
Inputs from the CS5016

are therefore used to remove frequency components in the input signal which are above one-half
the sample rate. However, all wideband noise introduced by the CS5016 still aliases into the
baseband. This "white" noise is evenly spread
from de to one-half the sampling rate and integrates to 35 ~V rms in unipolar mode.
Noise can be reduced by sampling at higher than
the desired word rate and averaging multiple
samples for each word. Oversampling spreads the
CS5016's noise over a wider band (for lower
noise density), and averaging applies a low-pass
response which filters noise above the desired
signal bandwidth. In general, the CS5016's noise
performance can be maximized in any application
by always sampling at the maximum specified
rate of 50 kHz (for lowest noise density) and
digitally filtering to the desired signal bandwidth.

CSS014 and CSS016 Sampling Distortion
The ultimate limitation on the CS5014/16's
linearity (and distortion) arises from nonideal
sampling of the' analog input voltage. The calibrated capacitor array used during conversions is
also used to track and hold the analog input signal. The conversion is not performed on the
analog input voltage per se, but is actually per-

DS14F6

At dc, the DAC capacitor array's voltage coefficient dictates the converter's linearity. This
variation in capacitance with respect to applied
signal voltage yields a nonlinear relationship between charge Qin and the analog input voltage
Vin and places a bow or wave in the transfer
function. This is the dominant source of distortion at low input frequencies (Figures 22 and 24).
The ideal relationship between Qin and Vin can
also be distorted at high signal frequencies due to
nonlinearities in the internal MOS switches. Dynamic signals cause ac current to flow through
the switches connecting the capacitor array to the
analog input pin in the track mode. Nonlinear onresistance in the switches causes a nonlinear
voltage drop. This effect worsens with increased
signal frequency as shown in Figures 26 and 28
since the magnitude of the steady state current increases. First noticeable at 1 kHz, this distortion
assumes a linear relationship with input frequency. With signals 20 dB or more below
full-scale, it no longer dominates the converter's
overall S/(N+D) performance (Figures 31-34).
This distortion is strictly an ac sampling phenomenon. If significant energy exists at high
frequencies, the effect can be eliminated using an
external track-and-hold amplifier to allow the array's charge current to decay, thereby eliminating
any voltage drop across the switches. Since the
CS5014116 has a second sampling function onchip, the external track-and-hold can return to the
track mode once the converter's HOLD input
falls. It need only acquire the analog input by the
time the entire conversion cycle finishes.

2-35

.- ..........
.....,,-....
__ .e._.
....,.

CS5012A, CSS014, CSS016

OdB

OdB
~

Sampling Rale: 56 kHz
. . Full Scale: 9V pop

-20dB

-

-

- -

-- -

-2OdB

Signal
Relative to
Full Scale

• • SI(N+D): 64.6 dB
-
EOT must be used. EOT falls 15 ClKIN
cycles after completion of a RESET calibration.

Throughput rate in
loopback mode

The device acquires and converts
a sample in 64 ClKIN cycles for all
ClKIN frequencies when in loopback.

The device acquires and converts in 64
ClKIN cycles for ClKIN=4MHz, but will
require 68 ClKIN cycles at 100kHz throughput. This is due to excess delay on EOT.

Input capacitance
in fine-charge mode

103pF typical, unipolar mode
72pF typical, bipolar mode

275pF typical, unipolar mode
165pF typical, bipolar mode

Calibration time
reset:
interleave:
burst:

Slew Rate
Unipolar
Coarse charge
Fine charge
Bipolar
Coarse charge
Fine charge

20V/us
1.5V/us

5V1us
0.25V/us

40Vlus
3.0V/us

10V/us
0.5V/us

Table 3. Differences Between the CSS012A and CSS012

2-38

DS14F6

.. ..._.-.
-. .. .....
..,

~-

~~~

CS5012A,CS5014,CS5016

~-

CS

CAL

INTRLV

RD

X

X

X

X

X

0

1

X

X

1

0

0

X

X

X

0

X

0

X

X
X
1
X

0
0
0
1

X
X
X
X

1
X
X
X

X
0
0
X

X
X
0

X
X
0

X
X
X

X
X
X

1
X
X

HOLD

•

*

AO

·
··

·
·
1
0

·

·

X
0

RST

0

Function

•

Hold and Start Convert

0

Initiate Burst Calibration

0

Stop Burst Cal and Begin Track

0

Initiate Interleave Calibration

0
0
0
X

Terminate Interleave Cal

X
1
X

Hiah
Reset

Read Output Data
Read Status Reaister
Hiah Imoedance Data Bus
Data Bus

Reset

The status of AD is not critical to the operation specified. However, AD should not be low with
CS and HOLD low, or a software reset will result.

Table 4. CS5012A114/16 Truth Table

+5V
100
Analog O--------;-r-----.----"v
Supply

CS5012A
CS5014
CS5016

Analog
Signal
Source

VV\,--_-=2"-j6 AIN

1=PF~1
0-. VREF
or
±VREF

Voltage

microprocessor
jiScrete logic.
Control
Logic

f-~~r--_ _
2B~VREF
Unused Logic inputs should only
be connected to VD+ or DGND .
• BW and BP/uP should always
be terminated to VD+ or DGND,
or driven by a logic gate.

t For best dynamic
-5V
Analog

S/(N+D) performance.
o-------~--~--I-__J\

Supply

Figure 36. CS5012A114/16 System Connection Diagram

DS14F6

2·39

..

.........
. ....
_.
......
_".....
~

.."

! '-,.

HOLD
CS5016 (LSB) DATA BUS BIT 0
DATA BUS BIT 1
CS5014 (LSB) DATA BUS BIT 2
DATA BUS BIT 3
CS5012 (LSB) DATA BUS BIT 4
DATA BUS BIT 5
DATA BUS BIT 6
DATA BUS BIT 7
DIGITAL GROUND
POSITIVE DIGITAL POWER
DATA BUS BIT 8
DATA BUS BIT 9
DATA BUS BIT 10
DATA BUS BIT 11
DATA BUS BIT 12
DATA BUS BIT 13
DATA BUS BIT 14
(MSB) DATA BUS BIT 15
CLOCK INPUT

07
OGNO
VO+
NC
08
NC
09
010
011
012
013
014
015

CS6012A,CSS014,CS5016

HOLD
DO
01
02
03
04
05
06
07
OGND
VD+
08
09
010
011
012
013
014
015
ClKIN

SOATA
SClK
EOC
EOT
VOCAL
INTRlV
BW
RST
TST
VAREFBUF
VREF
AGNO
AIN
VA+
BP/UP
AO
RO
CS

2
CS5012A
CS5012
CS5014
CS5016

4
5
6

9

21

lop
view
~

13

/
-.-J/

15

~/

CS5012A
CS5012
CS5014
CS5016

14

18

20

22

24

32
31

26

28

"
" '---\ "----

SERIAL OUTPUT
SERIAL CLOCK
END OF CONVERSION
END OF TRACK
NEGATIVE DIGITAL POWER
CALIBRATE
INTERLEAVE
BUS WIDTH SELECT
RESET
TEST
NEGATIVE ANALOG POWER
REFERENCE BUFFER OUTPUT
VOLTAGE REFERENCE
ANALOG GROUND
ANALOG INPUT
POSITIVE ANALOG POWER
BIPOLAR/UNIPOLAR SELECT
READ ADDRESS
READ
CHIP SELECT

SOATA
SClK
EOC
EOT
VOCAL
INTRlV
BW
RST
TST
VANC
REFBUF
VREF
AGNO
AIN
VA+
BP/uP
AO
RO
CS
ClKIN

NOTE: All pin references in this data sheet refer to the 40-pin DIP package numbering.
Use this figure to determine pin numbers for 44-pin package.

2-40

OS14F6

_.-_..--__.._-_
...
._.-.

CSS012A,CS5014,CS5016

PIN DESCRIPTIONS
Power Supply Connections

VD+ - Positive Digital Power, PIN 11.
Positive digital power supply. Nominally +5 volts.
VD- - Negative Digital Power, PIN 36.
Negative digital power supply. Nominally -5 volts.
DGND - Digital Ground, PIN 10.
Digital ground.
VA+ - Positive Analog Power, PIN 25.
Positive analog power supply. Nominally +5 volts.
VA- - Negative Analog Power, PIN 30.
Negative analog power supply. Nominally -5 volts.
AGND - Analog Ground, PIN 27.
Analog ground.
Oscillator

CLKIN - Clock Input, PIN 20.
All conversions and calibrations are timed from a master clock which can either be supplied by
driving this pin with an external clock signal, or can be internally generated by tying this pin to
DGND.

Digital Inputs

HOLD - Hold, PIN 1.
A falling transition on this pin sets the CS5012A114116 to the hold state and initiates a conversion.
This input must remain low at least one CLKIN cycle plus 50 ns.
CS - Chip Select, PIN 21.
When high, the data bus outputs are held in a high impedance state and the input to CAL and
INTRLV are ignored. A falling transition initiates or terminates burst or interleave calibration
(depending on the status of CAL and INTRLV) and a rising transition latches both the CAL and
INTRLV inputs. If RD is low, the data bus is driven as indicated by BW and AO.
RD - Read, PIN 22.
When RD and CS are both low, data is driven onto the data bus. If either signal is high, the data
bus outputs are held in a high impedance state. The data driven onto the bus is determined by BW
andAO.
DS14F6

2-41

_...
...-..
............
....
..,...,

-~

~

CS5012A, CS5014, CS5016

AO - Read Address, PIN 23.
Detennines whether data or status information is placed onto the data bus. When high during the
read operation, converted data is placed onto the data bus; when low, the status register is driven
onto the bus.
BP/uP - Bipolar/Unipolar Input Select, PIN 24.
When high, the device is configured with a bipolar transfer function ranging from -VREF to
+VREF. Encoding is in an offset binary format, with the mid-scale code 100...0000 centered at
AGND. When low, the device is configured for a unipolar transfer function from AGND to VREF.
Unipolar encoding is in straight binary format. Once calibration has been performed, either bipolar
or unipolar mode may be selected without the need to recalibrate.
RST - Reset, PIN 32.
When taken high for at least lOOns, all internal digital logic is reset. Upon being taken low, a full
calibration sequence is initiated.
BW - Bus Width Select, PIN 33.
When hard-wired high, all 12 data bits are driven onto the bus simultaneously during a data read
cycle. When low, the bus is in a byte wide format. On the first read following a conversion, the
eight MSB's are driven onto DO-D7. A second read cycle places the four LSB's with four trailing
zeros on DO-D7. Subsequent reads will toggle the higherllower order byte. Regardless of BW's
status, a read cycle with AO low yields the status information on DO-D7.
INTRLV - Interleave, PIN 34.
When latched low using CS, the device goes into interleave calibration mode. A full calibration
will complete every 2,014 conversions in the CS5012A, and every 72,051 conversions in the
CS5014116. The effective conversion time extends by 20 clock cycles.
CAL - Calibrate, PIN 35. (See Addendum appending this data sheet))
When latched high using CS, burst calibration results. The device cannot perform conversions
during the calibration period which will terminate only once CAL is latched low again.
Calibration picks up where the previous calibration left off, and calibration cycles complete every
58,280 CLKIN cycles in the CS5012A, and every 1,441,020 CLKIN cycles in the CS5014116 . If
the device is converting when a calibration is signaled, it will wait until that conversion completes
before beginning.

Analog Inputs
AIN - Analog Input, PIN 26.
Input range in the unipolar mode is zero volts to VREF. Input range in bipolar mode is -VREF to
+VREF. The output impedance of buffer driving this input should be less than or equ~ to 200 Q.

2-42

DS14F6

-....... ...-..
~

~~,..,

-~~~

CS5012A,CS5014,CS5016

VREF - Voltage Reference, PIN 28.
The analog reference voltage which sets the analog input range. It represents positive full scale for
both bipolar and unipolar operation, and its magnitude sets negative full scale in bipolar mode.
Digital Outputs

DO through D1S - Data Bus Outputs, PINS 2 thm 9, 12 thm 19.
3-state output pins. Enabled by CS and RD, they offer the converter's output in a format
consistent with the state of BW if AO is high. If AO is low, bits DO-D7 offer status register data.
EOT - End Of Track, PIN 37.
If low, indicates that enough time has elapsed since the last conversion for the device to acquire
the analog input signal.
EOC - End Of Conversion, PIN 38.
This output indicates the end of a conversion or calibration cycle. It is high during a conversion
and will fall to a low state upon completion of the conversion cycle indicating valid data is
available at the output. Returns high on the first subsequent read or the start of a new conversion
cycle.
SDATA - Serial Output, PIN 40.
Presents each output data bit after it is determined by the successive approximation algorithm.
Valid on the rising edge of SCLK, data appears MSB first, LSB last, and each bit remains valid
until the next bit appears.
SCLK - Serial Clock Output, PIN 39.
Used to clock converted output data serially from the CS5012A114116. Serial data is stable on the
rising edge of SCLK.
Analog Outputs

REFBUF - Reference Buffer Output, PIN 29.
Reference buffer output. A 0.1 ~ ceramic capacitor must be tied between this pin and VA-.
Miscellaneous

TST - Test, PIN 31.
Allows access to the CS5012A114/16's test functions which are reserved for factory use. Must be
tied to DGND.

DS14F6

2-43

,

til

.......
-....,,------_
.._---~--

CS5012A,CS5014,CS5016

PARAMETER DEFINITIONS
Linearity Error
The deviation of a code from a straight line passing through the endpoints of the transfer
function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 112 LSB
below the first code transition and "full-scale" is a point 112 LSB beyond the code transition to
all ones. The deviation is measured from the middle of each particular code. Units. in %
Full-Scale.
Differential Linearity
Minimum resolution for which no missing codes is guaranteed. Units in bits.
Full Scale Error
The deviation of the last code transition from the ideal (VREF-3/2 LSB's).
Units in LSB's.
Unipolar Offset
The deviation of the first code transition from the ideal (1/2 LSB above AGND) when in
unipolar mode (BPIUP low). Units in LSB's.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100... 000) from the ideal (112 LSB below
AGND) when in bipolar mode (BPIUP high). Units in LSB's.
Bipolar Negative Full-Scale Error
The deviation of the first code transition from the ideal when in bipolar mode (BPIUP high). The
ideal is defined as lying on a straight line which passes through the final and mid-scale code
transitions. Units in LSB's.
Peak Harmonic or Spurious Noise (More accurately, Signal to Peak Harmonic or Spurious Noise)
The ratio of the rms value of the signal to the rrns value of the next largest spectral component
below the Nyquist rate (excepting dc). This component is often an aliased harmonic when the
signal frequency is a significant proportion of the sampling rate. Expressed in decibels.
Total Harmonic Distortion
The ratio of the rms sum of all harmonics to the rms value of the signal. Units in percent.
Signal-to-Noise Ratio
The ratio of the rms value of the signal to the rms sum of all other spectral components below
the Nyquist rate (excepting dc), including distortion components. Expressed in decibels.
Aperture Time
The time required after the hold command for the sampling switch to open fully. Effectively a
sampling delay which can be nulled by advancing the sampling signal. Units in nanoseconds.
Aperture Jitter
The range of variation in the aperture time. Effectively the "sampling window" which ultimately
dictates the maximum input signal slew rate acceptable for a given accuracy. Units in
picoseconds.
NaTE: Temperatures specified define ambient conditions in free-air during test and do not refer to the junction
temperature of the device.

2-44

DS14F6

......
.. .
....,..,-...

•

1IIIl' _ _ •

~

_
~.

CS5012A,CS5014,CS5016

~

CS5012A Ordering Guide
Model
CS5012A-KP12
CS5012A-KP7
CS5012A-KL 12
CS5012A-KL7
CS5012A-BP12
CS5012A-BP7
CS5012A-BL 12
CS5012A-BL7
5962-8967901 QA
5962-8967901 XA

Throughput Conversion Time
63 kHz
12.251ls
100 kHz
7.2O IlS
63 kHz
12.25 !lS
100 kHz
7.20 !lS
63 kHz
12.25 !lS
100 kHz
7.20 !lS
63kHz
12.25 !lS
100 kHz
7.2O lls
63 kHz
12.25 1ls
63 kHz
12.25 !lS

Maximum DNL
±1/2 LSB
±1/2 LSB
±1/2 LSB
±1/2 LSB
±1/2 LSB
±1/2 LSB
±1/2 LSB
±1/2 LSB
±1/2 LSB
±1/2 LSB

Temp. Range
o to 70°C
o to 70°C
o to 70°C
o to 70°C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-55 to +125 °C
-55 to +125 °C

Package
Plastic DIP
Plastic DIP
PLCC
PLCC
Plastic DIP
Plastic DIP
PLCC
PLCC
CerDIP
Ceramic LCC

40-Pin
40-Pin
44-Pin
44-Pin
40-Pin
40-Pin
44·Pin
44-Pin
40-Pin
44-Pin

The CS5012A is recommended for new designs. The following is a list of upgraded part numbers.

DS14F6

Discontinued
Part Number
CS5012-KP24
CS5012-KP12
CS5012-KP7
CS5012-KL24
CS5012-KL 12
CS5012-KL7
CS5012-BD24
CS5012-BD12
CS5012-BD7
CS5012-BL24
CS5012-BL 12
CS5012-BL7

Equivalent
Recommended Device.
CS5012A-KP12
CS5012A-KP12
CS5012A-KP7
CS5012A-KL12
CS5012A-KL 12
CS5012A-KL7
CS5012A-BP12
CS5012A-BP12
CS5012A-BP7
CS5012A-BL12
CS5012A-BL12
CS5012A-BL7

CS5012-TD24B
CS5012-TD12B
CS5012-TE24B
CS5012-TE12B

5962-897901 QA
5962-897901 QA
5962-897901 XA
5962-897901 XA

2-45

.-

...,,_..-_-....---_----------

CS5012A,CS5014,CS5016

CS5014 Ordering Guide
Model
CS5014-KP28
CS5014-KP14
CS5014-KL28
CS5014-KL 14
CS5014-BP28
CS5014-BP14
CS5014-BL28
CS5014-BL 14
CS5014-SD14
CS5014-TD14
CS5014-SE14
CS5014-TE14
5962-8967401QA
5962-8967402QA
5962-8967401 XA
5962-8967402XA

Throughput
28 kHz
56 kHz
28 kHz
56 kHz
28 kHz
56 kHz
28 kHz
56 kHz
56 kHz
56 kHz
56 kHz
56 kHz
56 kHz
56 kHz
56 kHz
56 kHz

Conversion Time
28.50 !is
14.25 J.1s
28.50 !is
14.25 !is
28.50 !is
14.25!is
28.50 !is
14.25 !is
14.25 !is
14.25 !is
14.25 J.1s
14.25 !is
14.25 !is
14.25 !is
14.25 !is
14.25 !is

Linearity
±0.5 LSB
±0.5 LSB
±D.5 LSB
±D.5 LSB
±0.5 LSB
±D.5 LSB
±D.5 LSB
±D.5 LSB
±1.5 LSB
±0.5 LSB
±1.5 LSB
±0.5 LSB
±1.5 LSB
±0.5 LSB
±1.5 LSB
±0.5 LSB

Temp. Range
o to 70°C
o to 70°C
o to 70°C
o to 70°C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C

Package
40-Pin Plastic DIP
40-Pin Plastic DIP
44-Pin PLCC
44-Pin PLCC
40-Pin Plastic DIP
40-Pin Plastic DIP
44-Pin PLCC
44-Pin PLCC
40-Pin CerDIP
40-Pin CerDIP
44-Pin Ceramic LCC
44-Pin Ceramic LCC
40-Pin CerDIP
40-Pin CerDIP
44-Pin Ceramic LCC
44-Pin Ceramic LCC

The following is a list of upgraded part numbers.
Discontinued
Part Number
CS5014-SD14B
CS5014-TD148
CS5014-SE14B
CS5014-TE14B

2-46

Equivalent
Recommended Device
5962-8967401 QA
5962-8967402QA
5962-8967401 XA
5962-8967402XA

DS14F6

.. ...-.-.
-. .. .....
..,~~

~~

~~-

CS5012A, CS5014, CS5016

CSS016 Ordering Guide
Model
CS5016-JP32
CS5016-JP16
CS5016-KP32
CS5016-KP16
CS5016-JL32
CS5016-JL16
CS5016-KL32
CS5016-KL 16
CS5016-AP32
CS5016-AP16
CS5016-BP32
CS5016-BP16
CS5016-AL32
CS5016-AL16
CS5016-BL32
CS5016-BL 16
CS5016-SD16
CS5016-TD16
CS5016-SE16
CS5016-TE16
5962-8967601 QA
5962-8967602QA
5962-8967601 XA
5962-8967602XA

Linearity
.0030%
.0030%
.0015%
.0015%
.0030%
.0030%
.0015%
.0015%
.0030%
.0030%
.0015%
.0015%
.0030%
.0030%
.0015%
.0015%
.0076%
.0015%
.0076%
.0015%
.0076%
.0015%
.0076%
.0015%

Signal to
Noise Ratio
87 dB
87 dB
90 dB
90 dB
87 dB
87 dB
90 dB
90 dB
87 dB
87 dB
90 dB
90 dB
87 dB
87 dB
90 dB
90 dB
87 dB
90dS
87 dB
90 dB
87dS
90dS
87 dB
90 dB

Conversion Time
32.5O l1s
16.25 115
32.5O l1s
16.2511s
32.50115
16.25115
32.5011s
16.25 115
32.5O l1s
16.25 115
32.5O l1s
16.25 11s
32.50 115
16.2511s
32.5011s
16.25 115
16.25115
16.25115
16.25115
16.25 115
16.25 11s
16.25 115
16.25 115
16.25 11s

Temp. Range
o to 70°C
Oto70°C
Oto70°C
o to 70°C
o to 70°C
o to 70°C
o to 70°C
o to 70°C
-40 to +85°C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85°C
-40 to +85 °C
-40 to +85 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C

Package
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin Plastic DIP
44-Pin PLCC
44-Pin PLCC
44-Pin PLCC
44-Pin PLCC
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin Plastic DIP
44-Pin PLCC
44-Pin PLCC
44-Pin PLCC
44-Pin PLCC
40-Pin CerDIP
40-Pin CerDIP
44-Pin Ceramic LCC
44-Pin Ceramic LCC
40-Pin CerDIP
40-Pin CerDIP
44-Pin Ceramic LCC
44-Pin Ceramic LCC

The following is a list of upgraded part numbers.
Discontinued
Part Number
CS5016-SD16B
CS5016-TD16B
CS5016-SE16B
CS5016-TE16B

DS14F6

Equivalent
Recommended Device
5962-8967601 QA
5962-8967602QA
5962-8967601 XA
5962-8967602XA

2-47

•

i

I

..........
.. .........

..,..,..,
..,
Semiconductor Corporation
..,..,~

CDB5012 CDB5012A
CDB5014 CDB5016

.."

Evaluation Board for CS5012, CS5012A, CS5014,
CS5016 ADC's
Features

General Description
The CDB5012/4/6 is an evaluation board that eases the
laboratory characterization of any of the CS5012,
CS5012A, CS5014 and CS5016 AID converters. The
board can be easily reconfigured to simulate any combination of sampling, master clock, calibration, and input
range conditions.

• Compatible with CS5012, CS5012A,
CS5014, CS5016
• PC/J..LP-Compatible Header Connection
16-Bit Parallel Data
End-of-Conversion Output
CS, RD, and AO Control Inputs
• DIP-Switch Selectable:
Unipolar/Bipolar Input Range
Burst & Interleave Calibration Modes
Continuous Conversion
• Adjustable Voltage Reference
• Serial Data and Clock BNC Connections
• Operation from Internally-Generated or
Externally-Supplied Master Clock

The converter's parallel output data are available at a
40 pin strip header allowing easy interfacing to PC's or
microprocessor busses. Output data is also available in
serial form at SCLK and SDATA coaxial BNC connectors.
Evaluation can also be performed over a wide range of
input spans using the on-board reference circuitry. Furthermore, the CDB5012, CDB5012A, CDB5014,
CDB5016 features DIP-switch selectable unipolarlbipolar input ranges and the interleave calibration mode.
Calibration can be initiated at any time by momentarily
depressing a reset pushbutton.
ORDERING INFORMATION: CDB5012, CDB5012A,
CDB5014, CDB5016
DO - 015

AIN

0

-

0

0

CS5012
CS5012A
CS5014
CS5016

HOLD

CLKIN

RESET

~

EOC

--

AO

-

RO

-

CS

AID

i

Converter

VOLTAGE
REFERENCE

Crystal Semiconductor Corporation

R

SCLK

0
0

----.

+5V

P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

H
E
A
0
E
'-

SOATA

I

...... .--

GNO -5V

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
D814DB11

2-48

.............
.............
•

..r_ _ . _ .

COB5012, COB5012A, COB5014, COB5016

Analog Input

The AID converter's internal analog input buffer
requires a source impedance of less than 400 n
at IMHz for stability. Acquisition and throughput
are specified assuming a dc source impedance of
less than 200 n. Infinitely large dc source impedances can be accommodated by adding capacitance (typically lOOOpF) from the analog input to
ground. However, high dc source resistances degrade acquisition time and consequently throughput.

The analog input to the AID converter is supplied
through the BNC coaxial connector labeled AIN.
Analog input polarity is controlled by the first
position switch on the DIP-switch, SW-1. If it is
on, the input is unipolar ranging from GND to
VREF. If the switch is off, the input range is bipolar with the magnitude of the reference voltage
defining both zero- and full-scale (tVREF).

VO+

VAVA+

R10
30
00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
EOC
CS

2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
38
21

SW1-4
25
37 EaT
1 HaLO
39 SCLK
40 SOATA
26 AIN
CS5012
CS5012A 20 CLKIN
CS5014
CS5016

X

R23 (optional)

VO+

R2

~
VA-

CJ+5V

.~,,:,v:....:o_----+--CJ -5V

R1

31 TST
U1

28 VREF
32 RESET
29 REFBUF
C7

24 BP/uP
35 CAL
341NTLV
33 BW

SW1-1

~

~
R6

VO+
VO-

~I--------<~---------"-"

VO+

Figure 1. CDBSOI2, CDBSOI2A, CDBSOI4, CDBS016 Schematic
(Reference Circuitry Appears in Figure 3)

OS140B11

2-49

'

~,;,'
~

. ..-... _.
.............
. . . . . . . . . .'*'-•

COB5012, COB5012A, COB5014, COB5016
OFF

Position 1

Bipolar

Position 2

Burst Cal'

Position 3
Position 4

Normal
Normal

ON
Unipolar
Normal Operation
Interleaved Cal
Continuous Conversion

'NOTE: Use of BURST CAL IS not recommended.

Figure 2. DIP-Switch Definitions

Initiating Conversions

A negative transition on the converter's HOLD
pin places the device's analog input into the hold
mode and initiates a conversion cycle. On the
CDBS012, CDBS012A, CDBS014, CDBS016,
this input can be generated by one of two means.
First, it can be supplied through the BNC coaxial
connector appropriately labeled HOLD. Alternatively, switch position 4 of the DIP-switch can be
placed in the on position, thus looping the converter's EOT output back to HOLD. This results
in continuous conversions at a fraction of the
master clock frequency (see "synchronous operation" in the converter's data sheet).
The AID converter's EOT output is an indicator
of its acquisition status; it falls when the analog
input has been acquired to the specified accuracy.
If an external sampling clock is applied to the
HOLD BNC connector, care must similarly be
taken to obey the converter's acquisition and
maximum sampling rate requirements. A more
detailed discussion of acquisition and throughput
can be found in the converter's data sheet.

The CDBS012, CDBS012A, CDBSOI4,
CDBS016 is shipped from the factory without the
HOLD BNC input terminated for operation with
an external sampling clock. However, location
R23 is reserved for the insertion of a S1 Q resistor to eliminate reflections of the incoming clock
signal.
Voltage Reference Circuitry

The CDBS012, CDBS012A, CDBSOI4,
CDBSOl6 features an adjustable voltage reference which allows characterization over a wide
range of reference voltages. The circuitry consists
of a 2.SV voltage reference (1403) and an adjustable gain block with a discrete output stage (Figure
3). The output stage minimizes the output's headroom requirements allowing the reference voltage to
come within 300mV of the positive supply.
The coarse and fine trim potentiometers are factory calibrated to a reference voltage of 4.SV (a
table of output code values for a reference voltage of 4.5V appears in the CSS012, CSS012A,
CSSOI4, CSS016 data sheets). When calibrating
the reference, the voltage should be measured directly at the VREF input (pin 28) or at the ungrounded lead of decoupling capacitor C9.

Figure 3. Voltage Reference Circuitry
2-50

08140811

._.-.
..........-...
~

~

~

~~-

~~

CDB5012, CDB5012A, CDB5014, CDB5016

Reset/Self-Calibration Modes

OGNO

The NO converter will usually reset itself upon
power-up. Since this function is not guaranteed,
the converter must be reset upon power-up in
system operation. The converter can be reset on
the CDB5012, CDB5012A, CDB5014, CDB5016
board by momentarily depressing push-button
SW-2 thus initiating a full calibration cycle;
1,443,840 master clock cycles later the converter
is ready for normal operation.
The converters also feature two other calibration
modes: burst and interleave. The use of Burst
calibration is not recommended. Interleave can be
initiated by setting switch position 3 to the on
position. In the interleave mode (INTRLV low),
the converter appends one small portion of a calibration cycle (20 master clock cycles) to each
conversion cycle. Thus, a full calibration cycle
completes every 72,192 conversion cycles. The
Interleave calibration mode should not be used
intermittently.
A more detailed discussion of the converters'
calibration modes and capabilities can be found
in their data sheets.

DO
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015

III

EOC

AO

OGNO

RO
CS

Figure 4. Header Pin Definitions

The converter's EOC and data outputs are not
buffered on the CDB5012, CDB5012A,
CDB5014, CDB5016. Therefore, careful attention
should be paid to the load presented by any cabling, especially if the 3-state output buffers are
to be exercised at speed. Twisted ribbon cable is
typically specified at 1OpF/ft, so several feet can
generally be accommodated.

Parallel Output Data/Microprocessor Interface
Serial Output Data

The converter's outputs DO-DI5, its CS, RD, and
AO inputs, and its EOC output are available at
the 40 pin header. The CS and RD inputs are
pulled low through 10 ill resistors placing
the converter in a microprocessor-independent
mode. Control input AO is pulled up, insuring the
converter's output word, rather than the status
register, appears at the header.
The converter's 3-state output buffers and microprocessor interface can be exercised by driving
the CS and/or RD inputs at the header. Similarly,
the converter's 8-bit status register can be obtained on DO-D7 by driving AO low.

05140811

Serial output data is available at the two BNC
connections SCLK and SDATA. Data appears
MSB first, LSB last, and is valid on the rising
edge of SCLK.
Master Clock

The NO converter operates from a master clock
which can either be internally-generated or externally-supplied. For operation with an external
clock, the BNC connector labeled CLKIN
should be driven with a TTL clock signal. The
CDB5012, CDB5012A, CDB5014, CDB5016 is
shipped from the factory with the eLKIN input
2-51

.

..... .
. ..........
.............
~

~~~

terminated by a 51 n resistor to eliminate line
reflections of the incoming clock. If the CLKIN
BNC input is left floating, this resistor pulls the
converter's clock input down to ground, thus activating its internal oscillator.

Decoupling
The CDB5012, CDB5012A, CDB5014,
CDB5016's decoupling scheme was designed to
insure accurate evaluation of the converter's per-

CDB5012, CDB5012A, CDB5014, CDB5016

formance independent of the quality of the power
supplies. Each supply is decoupled at the converter with a 101J.F' electrolytic capacitor to filter
low frequency noise and a 0.11J.F' ceramiccapacitor to handle higher frequencies. The auto-zero~
ing action of the converter's comparator provides
extremely good power supply rejection at low
frequencies. Depending on the quality of the system's power supplies, the decoupling scheme
could be relaxed in actual use.

COMPONENT LIST
Ion resistor
51 n resistor
4.7 n resistor
1 ill resistor
560 n resistor
10 ill resistor
2.43 ill resistor
3.3 ill resistor
240 ill resistor
50 kn potentiometer
50 kn potentiometer
0.068 IJ.F' capacitor
0.1 IJ.F' capacitor
10 IJ.F' capacitor
CS501X1511X AID converter
1403 2.5V reference
OP07 op amp
2N2907A transistor
4 pos. SPST DIP switch
N.O. SPST push-button
20 pin header
bulkhead BNC
red banana jack
black banana jack
green banana jack
1" 4-40 spacer
3/8" 4-40 screw

2-52

Rl,R2
R3
R18
R9, R14
R17
R4, R5, R6, R7, R8, RIO, R11, R12, R13
R19, R20
R16
R21
R15
R22
C14
C1,C3,C5,C7,C9,C10,C12
C2, C4, C6, C8, C11, C13
U1
U2
U3
Q1
SWI
SW2
CONI
CON2, CON3, CON4, CON5, CON6
CON7
CON8
CON9
POST1,POST2,POST3,POST4,POST5,POST6
SC1,SC2,SC3,SC4,SC5,SC6

05140811

_ --_.

.....
....-.
. ......
.....
-..: ...

COB5012, COB5012A, COB5014, COB5016

R23

SM

00

o
o

0
0

00
00

00
00

o

0

o

0

00

o

0

00

o
o

0
0

00

o

0

00

00
00

o

0

DO
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
EOC
AO
RO
CS

U
Cl c = J
C20+

CDB501X
Evaluation Board

I

:
I
.... ,

Rll

I

1234

UI U

c = J + R12 I
C6
R13 I
c=JC7

'U3

R17

,t

c = J C10

I

AIN

@

U2

'II. _ _I c = J
R18
C14

c=J0+
C9
C8

~ ~~ ! ~~~~

R15

I: I R16
I : _I---'----_

0

+OCll

I

.~

06~s:,'
?i!ii\~n[D
D
u
--~!

R19

I

COARSE
~

,
+0
:m3

R8 I
C12 c = J

C5

Pl

8

Ul

, R14

~
~

I

I

IR20

---IR21
R22

AR~;~~: ANEA~

•

.
5• Board Layout
Figure

05140B11

2-53

...,-- .

.................
.............
~

CDB5012, CDB5012A, CDB5014, CDB5016

• Notes·

2·54

DS14DB11

.
........
..,
....
.
.........
~~~

~.

.",

CS5030 CS5031

.",

Semiconductor Corporation

12-8;t, 500kSPS, Sampling AID Converters
Features

General Description
The CS5030, and CS5031 are complete monolithic
CMOS analog-to-digital converters providing 500kSPS
throughput. On-chip calibration circuitry achieves true
12-bit accuracy for the ADC and on-chip reference,
over the full operating temperature range, without external adjustments.

• Monolithic CMOS AID Converter
0.3 J..Ls Track/Hold Amplifier
1.7 J..Ls AID Converter
2.5 V Voltage Reference
Flexible Parallel, Serial and Byte
interface
• 12-Bit ADC and Reference Accuracy
Total Unadjusted Error: 0.5 LSB
Ref Tempco: 1 ppm/DC
• Low Distortion
Signal-to-Noise Ratio: 72.8 dB
Total Harmonic Distortion: 0.01 %
Spurious-Free-Dynamic-Range: -80dBc
• Low Power: 88 mW
VA+

The CS5030/CS5031 have a high speed digital interface with three-state data outputs and standard control
inputs allowing easy interfacing to common microprocessors and digital signal processors.
Conversion
results are available in either 12-bit parallel, two 8-bit
bytes, or serial data.
The CS5030/CS5031 are available in a 24-pin, 0.3"
plastic dual-in-line package (PDIP), Cerdip and small
outline (SOIC) package.
ORDERING INFORMATION: Page 2-77

VADB11/HBEN
DB10/SSTRB

T/H
VIN

12-BIT CHARGE
REDISTRIBUTION
DAC

o--~-->

DB9/SCLK
DB8/SDATA
DB7/l0W

REF OUT

DB6/l0W
DBS/lOW
DB4ILOW
DB3/DB11

ClKIN 0 - - - - - - - e _ _ -

~·_· _ _· _ _ _ GNTROl
BUSY/INT ()..-----~ -------t_INT:~~ACE
FORMAT

____

12

DB2IDB10
DB1/DB9
DBO/DBS

AGND

DGND

CS

RD

CONVST

Preliminary Product Information I This document contains information for a new product. Crystal

Semiconductor reserves the right to modify this product without notice.

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS90PP5
2-55

_.-_..---._.
__.._-...-.

CS5030/CS5031

(VA+ = +5V±5%; VA- = -5V±5%; AGND = DGND = OV;
= 10MHz, unless otherwise specified. TA = TMIN to TMAX)

ANALOG CHARACTERISTICS
ClKIN

B
Parameter*
Specified Temperature Range

Symbol

Min

Typ

T
Max

Min

-40 to +S5

(Note 1)

Typ

Max

-55 to +125

Units
°C

Accuracy
Total Unadjusted Error

(Note 2)

Differential Nonlinearity

TUE
DNl

-

0.5

1.0

-

0.5

Integral Nonlinearity

INl

-

0.25

0.5

Unipolar Offset Error

Vup

0.25

0.5

Bipolar Offset Error

VBP

0.25

0.5

Positive Full Scale Error

(Note 3)

FSEp

Bipolar Negative Full Scale Error

(Note 3)

FSEN

-

Dynamic Performance

(Note 4)

-

0.5

1.0

lSB

-

0.5

lSB

0.25

0.5

lSB

0.25

0.5

lSB

0.25

0.5

LSB

0.25

0.5

lSB

0.25

0.5

LSB

0.25

0.5

0.25

0.5

-

-

71

72.S

-

dB

70

72

-

dB

SNR

71.5

72.S

Signal-to-Noise-and-Distortion

(Note 5)

SINAD

70

72

Total Harmonic Distortion

(Note 6)

THD

-

0.01

-

-

0.Q1

%

Spurious-Free-Dynamic-Range

(Note 6)

SFDR

-

0.01

-

-

-SO

-

0.Q1

-SO

-

-

%
dBc

-SO
-SO

-

-

-

-

-SO
-SO

-

-

dBc
dBc

+2.5
+5

-2.5
0

+2.5
+5

V
V

25

-

-

25

ns

Signal-to-Noise Ratio

Intermodulation Distortion
Second Order
Third Order

(Note 7)
IMD

Analog Input
Input Voltage Range
CS5030
CS5031

VIN

Aperture Delay

tapd

-

Aperture Jitter

tapj

-

1.
2.
3.
4.
5.
6.
7.

-

ps

10
10
Acin
All parameters guaranteed by design, test, and/or characterization.
TUE is measured using the on-chip reference.
Measured with respect to internal reference and includes bipolar offset error.
VIN =±2.5Vpp (CS5030), ... OV to 5V (CS5031).
VIN = 10kHz Sine Wave, fSAMPLE = 500kSPS. Typically 71.5dB for 10kHz~----------------------------­
CONVST

TRACK/HOLD
GOES INTO HOLD

HBEN 1
CS
RD
INT

DATA
SSTRB

uuuuuuuu
SDATA
SERIAL DATA

NOTES: 1. Times tcss1. trpw1. tcsh1. thrs. and thrh are the same for a high byte read as for a low byte read.
2. Continuous SCLK (Dashed ling) when FORMAT ·5V
Noncontinuous when FORMAT = OV

=

Figure 2. Mode 1 Timing Diagram, Byte or Serial Read

DS90PP5

2-59

-----...----------------

CS5030/CS5031

SWITCHING CHARACTERISTICS
AGND

= DGND = OV, (Note 9))

(TA =TMIN to TMAX;VA+

= +5V±5%, VA- = -5V±5%;

B
Parameter

Symbol

Min

Typ

T
Max

Min

-40 to +85

Specified Temperature Range

Typ

Max

-55 to +125

Units
°C

Mode 2 Timing
tconv

-

-

CS Active to RD Active

tcss2

0

-

CS Active to BUSY Active

tcbd

-

75

-

Data Valid to BUSY Rising

tds

50

tcsh2

0

-

50

RD Inactive to CS Inactive

-

Output Float Delay: RD Rising to Hi-Z

tfd2

5

-

50

5

HBEN Low to CS Active

thcs

0

CS Inactive to HBEN HIGH

thch

0

-

-

0

trpw2

60

-

tra2

-

-

75

-

57

-

-

70

tpwh
tpwl

0.4
0.4

0.6
0.6

0.4
0.4

-

0.6
0.6

MCC·
MCC·

tsss

25

-

-

25

-

-

ns

30

ns

25

ns

25

ns

Conversion Time

RD Pulse Width
Data Access Time After RD

(Note 10)

17

-

0

0

0

-

17

MCC·

-

ns

75

ns

-

-

ns

-

ns

-

50

ns

-

ns
ns
ns

Serial Clock Timing
Serial Clock

Pulse Width High
Pulse Width Low

SCLK rising to SSTRB Falling Time (Note 12)

tss

-

-

30

-

SCLK rising to SSTRB Inactive

tssr

10

-

25

10

SCLK rising to SDATA Hold Time

tsh

10

-

25

10

SCLK rising to Data Valid

"MCC

2-60

(Note 13)

= Master Clock Cycles, 1 MCC = tclk.

-

DS90PP5

.._-_
._.-.
_.--..--_...

CS5030/CS5031

RO

BUSY

TRAC~HOL~

GOES INTO HOLD

CS

[

}

I

filii

,~"'

1!ICbd 55
~
------;t=IConv~~ Ifd2

->S~~

Hi-Z
Ids 1,--'----,1
DATA --""-'=-------'-5,\;----('
DATA
OB11-0BO

NOTE: FORMAT = +5V.
Figure 3. Mode 2 Timing Diagram, 12·Bit Parallel Read

-thcs

r-

~ ,~

TRACK/HOLD

!""- GOES INTO HOLD
-->

RD
BUSY
DATA

~,

55

tcss2

..t

tconv
Hi-Z

--> -

tcsh2

55

:

\

I
trpw2

1'------'

tds1

_~t~~
DATA

ltra2 ~ ~d2

-

DATA
DBll-DB8

SSTRB

SCL~
SDATA

NOTES: 1. Times thcs. tcss2. tcsh2 and thch are the same for a high byte read as for a low byte read.
2. Continuous SCLK (Dashed line) when FORMAT = -5V
Noncontinuous when FORMAT = OV
Figure 4. Mode 2 Timing Diagram, Byte or Serial Read

DS90PP5

2·61

----------- -----------

CS5030/CS5031

DIGITAL CHARACTERISTICS (TA = TMIN to TMAX: VA+ = 5V±5%; VA- = -5V±5%)
Parameter

Symbols

Min

Typ

High-level Input Voltage

VIH

3.3

-

Low-level Input Voltage

VIL

-

-

Cin

-

-

-

50

-

15

IlA
pF

Max

Units

Logic Inputs

Input leakage current

lin

Input Capacitance

-

V

0.8

V

50
10

IlA
pF

-

V

0.4

V

Logic Outputs
High-level Output Voltage

(Note 14)

VOH

4.0

Low-level Output Voltage

(Note 15)

VOL

-

OB11-0BO Floating State leakage Current

loz

OB 11-080 Output Capacitance

Cout

Notes: 14. Isource = -40 IlA
15. Isink = 1.6 rnA

5V

~

56kn

DBNl
56kn

IT

DBN

~50PF

50pF

DGNDV

a.) High-Z to V OH

DGND
b.) High-Z to VOL

Figure 5. Load Circuits for Access Time

DBN

I

i~5V
3kn

3kn
DGND

1::
T10PF
V

a.) VOH to High-Z

DBN

T

10pF

VDGND

b.) VOL to High-Z

Figure 6. Load Circuits for Output Float Delay

2-62

DS90PP5

.._-_
.-_
..--_._.
__
...-.

CS5030/CS5031

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = OV.

All voltages with re-

spect to ground)
Parameter

Symbol

Min

Typ

Max

Units

Positive Analog Supply

VA+

4.75

5.0

5.25

V

Negative Analog Supply

VA-

-4.75

-5.0

-5.25

V

-2.5
AGND

-

+2.5
5

Analog Input Voltage

VIN
CS50S0
CS50S1

V

VA-, OV, VA+

FORMAT Input Voltage Range

V

ClKIN Input Voltage Range

0

-

VA+

Other Digital Input Voltage Range

0

-

VA+

V

External Clock Frequency

-

10

-

MHz

External Clock Jitter

-

ps

-

-

80

AGND to DGND Voltage Differential

±10

mV

ABSOLUTE MAXIMUM RATINGS

*

V

(AGND = OV, All voltages with respect to ground)

Parameter

Symbol

Min

Typ

Max

Units

Positive Analog Supply

VA+

-O.S

V

VA-

O.S

-6.0

Analog Input Voltage

VIN

-

6.0

Negative Analog Supply
CS50S0
CS50S1

(VA-)-O.S
(VA-)-O.S

FORMAT Input Voltage Range

(VA-)-O.S

ClKIN Input Voltage Range

(VA-)-O.S

Other Digital Input Voltage Range
REF OUT Current
Digital Output Current
AGND to DGND Voltage Differential

-O.S

-

Operating Temperature Range
CS50S0/50S1-BP/BS
CS50S0/50S1-TO
Storage Temperature Range
lead Solder Temperature (10sec duration)

-40
-55
-65

-

V
V

(VA+)+O.S
(VA+)+O.S

-

(VA+)+O.S

V

(VA+)+O.S

V

(VA+)+O.S

V

10

mA

5

mA

100

mV

+85
+125

DC
DC

+150

EC

+SOO

DC

-

* WARNING: Operation at or beyond these limits may result

In permanent damage to the device.
Normal operation is not guaranteed at these extremes.

NOTE: Temperatures specified define ambient conditions in free-air during test and do not refer to the junction
temperature of the device.

DS90PP5

2-63

•

I

_.-_..--_._.
__.._-_
...-.

CS5030/CS5031

GENERAL DESCRIPTION
The CSS030 and CSS031 are complete 12-bit
SOO kSPS sampling ADCs, utilizing a successive
approximation architecture. Factory calibration
ensures 12-bit conversion accuracy over
industrial and military temperature ranges. The
CSS030 analog input range is ±2.S V (0 V to +S
V for the CSS031), with the output data
provided in parallel, byte or serial formats. The
internal capacitor array DAC acts as an inherent
sample-and-hold, and forms the heart of the
CSS030/CSS031. The on-chip +2.5 V reference
is available at the REFOUT pin. Additionally,
an on-chip 10 MHz clock oscillator can be used
to control converter operations.

OPERATIONAL OVERVIEW
Track-anti-Hold Operation

Track-and-hold operation within the
CSS030/CSS031 is transparent to the user. The
capacitor array DAC acts as the hold capacitor.
During tracking mode all elements of the
capacitor array DAC are switched to the analog

input for charging. The load capacitance of the
entire array during tracking mode is typically S
pF. The input bandwidth of the track-and-hold is
typically 2 MHz. The ADC goes into hold mode
on the rising edge of CONVST.
Capacitor Array DAC Calibration

To achieve 12-bit accuracy from the capacitor
array DAC, the CSS030/CSS031 uses a novel
calibration scheme. Each bit capacitor consists of
several capacitors that are trimmed to optimize
the overall bit weighting with an internal
resolution of 14-bits, resulting in nearly ideal
differential and integral linearity.
The calibration coefficients for the capacitive bit
weights are stored in an on-chip EEPROM
during the factory calibration. When the
converter is subsequently powered-up these
coefficients are applied to the capacitor array
DAC. The low temperature coefficient of the
capacitor array easily maintains 12-bit accuracy
over the full temperature range.

To 12·bit
ADC

I

Bandgap
Reference

l

Trim

I

DAC

1

Voltage
Reference
Output

1
I Temperature
Die
II
Sensor

~

,-----.

IS·blt
6EADC

f--+

EEPROM
64x23

Stable
Reference
for
Factory
Calibration

Figure 7. Reference Temperature Control Block

2-64

DS90PP5

----------- -----------

CS5030/CS5031

Reference Calibration

The CSS030/CSS031 employs an internal
reference calibration circuit to maintain less than
200 IlV of error. A first order corrected low-drift
band-gap reference is the foundation of the
reference trim block (Figure 7). This reference
is combined with an on-chip temperature sensor
and an EEPROM-based look-up table to provide
unmatched reference accuracy.
During normal operation of the device, a 16-bit
delta-sigma (Li-~) ADC independently monitors
the chip's temperature every 800 ms. As the
temperature varies a segment of the EEPROM is
selected based on the Li-~ converter's output
word. The EEPROM output is used to control
the trim DAC which compensates the bandgap
reference voltage. This trim circuit maintains the
output reference voltage to the ADC and REF
OUT pin to within ±200 IlV of 2.5 V over the
full temperature range.
During factory calibration the 16-bit Li-~
converter takes measurements at several
temperature points to establish a profile of the
bandgap reference temperature drift (Figure 8).
At each temperature point the Li-~ converter
calculates the error voltage between a stable
external 2.S V reference and the actual bandgap
reference voltage. Additionally, the Li-~
converter also measures the absolute temperature
of the chip (from an on-chip sensor) as well as
it's own offset and gain errors. All of these
results are uniquely stored in the device
EEPROM to be accessed during final test.
During final test the four 16-bit words associated
with each temperature point are read by the
tester. The test system performs a trapezoidal
approximation in software for each of the
temperature segments. Digital words
representing temperature, slope and intercept are
then downloaded from the test system back into
the EEPROM on the chip (Figure 9).
DS90PP5

•

Vactual

Vref

E
Videalt--_ _-'-_-'fr--_-'--_ _- - L _
~-----r--~--~----_+~Temp

Figure 8. Untrimmed Reference Voltage versus
Temperature

YN-1=mN-1 x+bN-1
Y1=m1x+b1
Y2=m2x+b2

\.

V actual

V ref

E1
E2
EN
Videalt--------'---'fr----'--------'--L-----~---'fr----+_----_+-.Temp

Figure 9. Slopes and Intercepts are Calculated for the
Intermediate Temperatures

Figure 10. The Adjusted Reference Error is Within
20011V of2.5V
2-65

i

i~

------------.----------

CS5030/CS5031

When the converter is in normal operation, the
on-chip bandgap reference trim circuit is
trimmed over temperature. Depending on the
temperature of the chip, the Ll-L converter
selects the appropriate temperature segment
stored in EEPROM. Using the corresponding
slope and intercept data for the temperature in
question, the appropriate correction factor is
provided by the trim DAC to maintain the output
voltage reference error within ±200 IlV of the
ideal 2.5 V (Figure 10).
The reference voltage is available at the REF
OUT pin and is capable of sourcing 500 IlA to
peripheral devices. This pin must be decoupled
with a parallel combination of a + 10 J.LF
tantalum capacitor and a 0.1 J.LF ceramic
capacitor to AGND.
Full accuracy of the reference is achieved within
1.1 sec of power-up, after the trim circuitry has
completed the calibration of the reference.

Analog Input
The CS5030 provides a ±2.5 V analog input
voltage range, 0 V to +5 V for the CS5031.The
equivalent analog input circuit is illustrated in
Figure 11 (shown in track mode); During hold
mode the input impedance to the device is
typically 10 Mil, and the various elements of the
capacitor array DAC are connected to either
AGND or VREF. In switching back from hold
mode to track mode, some elements in the
capacitor array must be charged by the analog
input. For the CS5030, the worst case charging
current occurs when the analog input changes
from +2.5 V to -2.5 V. For the CS5031, the
worst transition occures from +5 V to 0 V input
changes.
To ensure that the capacitor array DAC has
settled to within 0.25 LSB during the allowed
acquisition time, the external source resistance
should be less than 4 ill.

15kn

5pF
Package
Capacitance

AGND

r

1kn

VIN

5

VREF

\~
PFT

Capacitor
Array

~ c>-~~rator

Figure 11. Analog Input Model.

2-66

DS90PP5

----------- -----------

CS5030/CS5031

Output Coding
The digital output coding ...

CS5030 Input
+2.5V
OV
-2.5V
CS5031 Input
+5V
+2.5V
OV

2's Complement Output
0111 1111 1111
0000 0000 0000
1000 0000 0000
Binary OutDut
1111 1111 1111
0111 1111 1111
0000 0000 0000

Simple quantization noise is a direct result of the
finite LSB size, which is itself related to the
number of digital output bits. Quantization noise
places a hard limit on SNR for a 12-bit ADC
according to the following equation.
SNRMAXQuantization = (S.02dB)(# of Bits) + 1.7SdB
... SNRMAXQuantization = 74 dB
Although SNR
can never be better than the theoretical limit, it
can certainly be worse. Jitter between the
CONVST clock and the analog input signal is
often one of the largest contributors to decreased
SNR, particularly as frequencies increase.

High-Speed System Clock
The CS5030/CS5031 employs a high-speed
clock (typically 10 MHz) to control internal
operations. This high-speed clock can be
generated internally with the on-chip oscillator,
or it can be supplied from an external CMOS
source. Connecting a CMOS clock signal to the
CLKIN pin allows the converter to operate from
an external clock. Alternatively, connecting the
CLKIN pin to VA- activates the internal clock
oscillator.
External Clock ....... CLKIN = External Clock Source
Internal Clock ........ CLKIN =VA-

CONVERT Clock Considerations
When digitizing time varying signals, it is
possible to create additional noise sources over
and above those resulting from quantization
noise and thermal noise. This is particularly true
when high-speed conversion rates, or
high-frequency analog input frequencies are
involved. Special care must be taken to see that
CONVST clock jitter does not undermine
high-speed signal processing applications by
introducing noise into the conversion process.
DS90PP5

To be considered insignificant, noise related to
jitter (SNRMAXjitter) should be at least 12 dB
below the other dominant noise sources, such as
quantization noise (SNRMAXQuantization). The
12 dB target is somewhat arbitrary, but yields
less than 4 % additional noise. In terms of the
CS5030/CS5031, a 250 kHz analog input signal
requires less than 80 ps of jitter between the
CONVST clock and the analog input signal to
achieve full performance. The use of low-jitter
CONVST clock source is the most common
means of reducing the effects of jitter. Lower
conversion rates and lower analog input
frequencies are significantly less sensitive to
jitter effects.
2
SNR MAX =..,jrS-NR--M-A-X-jj-tte-r"i2-+-S-NR--M-A-X-Q-u-an-ti-za-ti-on--"-

Vpeak
]
SNR MAXjitter (dB) =20Log [ 2 f ..
n IN J1tter RMS

jitter RMS

=."j clock jitter RMS 2+ analog jitter RMS 2

2-67

___-_

.. ......
.-_
. ..,..
....,--

..,

CS5030/CS5031

DigUalOu~utFonna~

The CS5030/CS5031 provides three digital
output formats. These include 12-bit parallel,
two 8-bit bytes, and a serial output mode. The
output data format is controlled by the level
applied to the FORMAT pin. All three of the
digital output formats can be used with either of
the convert start timing modes ... Mode 1 and
Mode 2, which are described in the next two
section.
FORMAT

+VA
GND

-VA

DiJritai Outputs
12-Bit Parallel
Bvte' Serial wlNon-Continuous SCLK
Byte' Serial/Continuous SCLK

+SV

+

10/.1F~

Figure 12 shows the schematic for the
CS5030/CS5031 in 12-bit parallel mode. The
twelve bits of data are output simultaneously on
DB 111(MSB) through DBO (LSB).
In byte mode, two 8-bit read operations (four
leading zeros with 4 data bits ... plus 8 more data
bits) are required to collect the data as shown in
figure 13. In byte mode, the DB lllHBEN pin
defers to the HBEN function, selecting the high
or low byte of data to be read from the ADC.
The lower eight bits of data are placed on the
data bus when HBEN is held low. To access the
four MSBs of data, HBEN must be held high.
The 4 MSBs of the 12-bit data word are right

~0.1/.1F

17

22

19

VA+
FORMAT

+2.SV
10/.1F

REF OUT
18
AGND

CS5030
or
CS5031

24
CS
RD

--Analog
Source

Analog
Signal
Conditioning

BUSY/I NT

20

Control
logic

23

CONVST

VIN

DBO
12

2

12

DB11
DGND
VA-

ClKIN

-SV

Figure 12. System Connec:tion Diagram: Parallel Data Format

2·68

DS90PP5

___-_

.. ...-.
-.-..--_._.

CS5030/CS5031

justified with zeros in the upper nibble of the
high byte.

been clocked out on the SDATA line. Serial data
operation is identical for MODE 1 and MODE 2
timing control (see next two sections). For serial
operation, OV on the FORMAT pin causes the
serial clock to run only when data is being
clocked out of the device; SCLK goes high after
data transmission is completed. If the FORMAT
is connected to -VA, the SCLK output will run
continuously, independent of data transmission.

In serial mode, DB8/SDATA, DB9/SCLK and
DB 10/SSTRB defer to their serial functions. The
serial strobe pin SSTRB provides a framing
signal for serial data. Serial data is available at
the SDATA pin when SSTRB falls low. SSTRB
falls low within three clock cycles of CONVST.
A total of sixteen bits (four leading zeros and
twelve data bits starting with the MSB) are
clocked out on the SDATA pin on the rising edge
of SCLK. The data bits become valid no more
than tss after the rising edge of SCLK. SSTRB
goes low during data transmission and
automatically returns high when the LSB has

+5V

~O.1IlF

10IlF+~

1 17

19

VA+

REF OUT
18

CS5030
or
Analog
Source

---

Analog
Signal
Conditioning

CS5031

~

S1 = B

CS
RD
--BUSY/INT
---

24

O.1IlF

=f

+2. 5V
10llF

9

1
2
23

Control
logic

CONVST

r
S1 = A

VIN

AGND

*

12

DB11IHBEN

DGND

~~
B

;

DBOIDB8

Serial cl ock operates only
during data transmission.
Serial cl ock runs continuously
independent of data transmission
A S1 22

4

DB7/l0W
--

DB101SSTRB
DB91SClK
FORMAT
VA121

DB8/SDATA
ClKIN

8

Data
Processor

5

;

6

Serial
Data
Interface

7

3
1

-5V
1OllF.l
+

. l O.1IlF

I Source
Clock I

Figure 13. System Connection Diagram: Serial and Byte Data format

DS90PP5

2-69

•

-_.._-_.

~==~:=::.

CS5030/CS503.1

MODE 1 . Operation

A data read operation performed at the end of
conversion will read all twelve bits of data at the
same time.

The rising edge of CONVST is used to put the
device into hold mode and initiate a conversion.
At the end of conversion the device returns to
it's tracking mode. MODE 1 timing is primarily
used in DSP type applications where precise
control of CONVST timing is required.

MODE 1 - Byte Read
Figure 15 shows the MODE 1 timing diagram
for byte operation. At the end of conversion
when !NT goes low, either the low byte or the
high byte of data can be read, depending on the
status of HBEN. Bringing CS and RD low
allows data to be read from the ADC and also
resets !NT high.

Conversion begins on the rising edge of
CONVST provided that CS is high. The
BUSYIINT line performs the !NT function and
can be used to interrupt the microprocessor. !NT
is normally high and goes low at the end of
conversion. The ADC returns to track mode
when INT goes low. Bringing CS and RD low
allows data to be read from the ADC, and also
resets INT high. CONVST must be high when
CS and RD are brought low for the ADC to
operate correctly in this mode. Data cannot be
read during a conversion cycle because the
output data latches are disabled while a
conversion is in progress.

MODE 1 - Serial Read
The MODE 1 timing diagram for serial operation
is shown in figure 16. Conversion begins on the
rising edge of CONVST, and data is clocked out
on SDATA immediately upon the falling edge of
SSTRB. The data is output as four leading
zeroes followed by the twelve data bits with the
MSB first. The first zero should be latched into
the external receiving circuitry on the first falling
edge of SCLK after SSTRB goes low. A total of
sixteen falling SCLK edges will latch all sixteen
bits of output data. SSTRB automatically returns
high after the last bit of data has been clocked
out of the device.

MODE 1 - 12-Bit Parallel Read
Figure 14 shows the MODE 1 timing diagram
for 12-bit parallel operation (FORMAT = +VA).

C-O-N-V-S-T

-----u=:J-------------------------------Hold mode.
Conversion begins

INT
End of conversion
Acquisition begins
CS

---"'=J-.lLJ--

INT is reset on falling edge of CS and RD

t

CS must be high when CONVST
goes low for conversion to occur
RD

I

I

I DATA

~

Data relinquished
Databits automatically three-state '-----' after RD goes high
during a conversion

~

DATA

Figure 14. Mode 1 Timing Diagram, 12·bit Parallel Read

2-70

DS90PP5

----------- ----------CONVST

CS5030/CS5031

~

r"Holdmode.

L r - Conversion begins
End of conversion
r'j I. Acquisition begins --~~ INT is reset on falling edge of CS and RD

INT

,

CS

CS must be high when CONVST
goes low for conversion to occur
RD
Data bits automatically three-state'-----'
during a conversion ~
DATA
LOW BYTE DATA 1

HIGH BYTE DATA 1

NOTE: 1. In the above diagram HBEN is exercised to read the low byte first (DB7-DBO) and then the high byte
(OB11-0B8). To change the order in which the bytes are read, simply invert the HBEN signal shown
above.
Figure 15. Mode 1 Timing Diagram, Byte Read

~~"m~

CONVST ~
Acq.uisition
begins

f'
Lli

1

2

16

3

II

LI

SDATA

))

Conversion begms

SCLK

SSTRB

"

LI

I
I
I
I
I

JlITi

('I

1

cl'J

('I

FOUR LEADING ZEROS

1DB11 1DB10 1 DB9

I:: 1

DBa

1

Figure 16. Mode 1 Timing Diagram· Serial Read

DS90PP5

2-71

.._-_
_.-_..--_
_...-..

CS5030/CS5031

MODE 2 Operation

data before the conversion cycle has been
completed.

Mode 2 operation allows the ADC conversion to
be initiated by a read operation from a f,lc. The
BUSY signal can be used in this mode to halt
f,lC operations by placing the f,lC in a WAIT state
until the conversion is complete. This avoids
having to handle interrupts and timing delays,
assuring that the conversion cycle is complete
before any attempted data read.
In this mode, CONVST must be held
permanently low. Bringing CS low (while HBEN
is low) puts the device into hold mode and
initiates a conversion. The BUSYIINT pin defers
to the BUSY function such that BUSY goes low
at the start of conversion and returns high at the
end of conversion.

MODE 2 - 12-Bit Parallel Read
The MODE 2 timing diagrams for the parallel
data output format are shown in figure 17. This
mode of operation forces the f,lC into a WAIT
state until the conversion has been completed. It
removes the risk of inadvertently reading invalid

MODE 2 - Byte Read
Figure 18 shows the timing diagram for byte
operation in MODE 2. Since HBEN must be low
to initiate a conversion, the lower byte of data
will be accessed first during the two-byte read
operation. This is followed by a second byte
read operation (with HBEN high) to complete
the data transfer.
MODE 2 - Serial Read
The timing diagram for MODE 2 serial operation
is shown in figure 19. The device goes into hold
mode on the falling edge of CS and conversion
begins when BUSY goes low. The data is
clocked out similarly as for MODE 1 serial
operation. Upon clocking of the final data bit
BUSY returns high indicating end of conversion.

hard wire low for

CoNVST----------------------~~rJ--M-O-D-E-2-o~p-e-ra-t-io-n-------

Lt=__H_O_L_D_M_O_D_E__~,»)~________~1

CS
RD

BUSY

Conversion
begins

End of conversion
Acquisition begins

Data bits automatically three-state
DATA ~d~u~ri~n£g~co~n~ve~r~s~io~n~_____~~L-~~~J_______ DATA
Figure 17. Mode 2 Timing Diagram, 12·bit Parallel Read

2-72

DS90PP5

.._-_
.-_
__
...-..
_
......__
...

CS5030/CS5031

'§,

CONVST

hard wire low for MODE 2 operation

=-~---- tcbd + tconv
Figure 20. Stand-Alone Operation

Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your

2-74

Layout considerations

The CS5030/CS5031 is a high-speed component
which requires adherence to standard
high-frequency printed circuit board layout
techniques to maintain optimum performance.
These include proper supply decoupling,
minimum length circuit traces, and physical
separation of digital and analog components and
circuit traces. See the CDB5032 evaluation
board data sheet for more details.

DS90PP5

.-_
_
..--_._.
__.._-_
...-.

CS5030/CS5031

PIN DESCRIPTIONS

,.
i:

READ
RD
BUSYIINTERRUPT
BUSYIINT
CLOCK INPUT
ClKIN
DB11/HIGH BYTE ENABLE DB11/HBEN
DB10/SERIAL STROBE DB10/SSTRB
DB9/SERIAL CLOCK
DB9/SClK
DBB/SERIAL DATA DB8ISDATA
DATA OUT
DB7/l0W
DATA OUT
DBS/lOW
DATA OUT
DBS/lOW
DATA OUT
DB4/l0W
DIGITAL GROUND
DGND

CS
CONVST
FORMAT
VAAIN
REF OUT
AGND
VA+
DBO/DBS
DB1/DB9
DB2IDB10
DB3/DB11

CHIP SELECT
CONVERT START
DATA OUTPUT FORMAT
NEGATIVE ANALOG SUPPLY
ANALOG INPUT
VOLTAGE REF OUT
ANALOG GROUND
POSITIVE ANALOG SUPPLY
DATA OUT
DATA OUT
DATA OUT
DATA OUT

Pinout applies to both DIP and SOIC packages.

Power Supply Connections

VA+ - Positive Supply, PIN 17.
+SV±S%.

VA- - Negative Supply, PIN 21.
-SV±S%.

DGND - Digital Ground, PIN 12.
Ground reference for digital circuitry.
AGND - Analog Ground, PIN 18.
Ground reference for track-and-hold, reference and DAC.
Oscillator

CLKIN - Clock Input, PIN 3.
An external 10 MHz (CMOS compatible) clock is applied at this pin. Connecting this pin to
VA- enables the internal clock oscillator.
Digital Inputs

CS - Chip Select, PIN 24.
Active low logic input. The device is selected when this input is active. With CONVST tied
low, a new conversion is initiated when CS goes low.

DS90PPS

2-75

_.-_..--_.-.
__.._-_
...-.

CS5030/CS5031

RD - Read, PIN t.
Active low logic input. This input is used in conjunction with CS low to enable the data
outputs.
FORMAT - Output Mode Selection, PIN 22.
Defines the output data format and serial clock format. With FORMAT at +Sv, the output data
format is 12-bit parallel only. With FORMAT at Ov, either byte or serial data is available and
SCLK is not continuous. With FORMAT at -Sv, byte or serial data is again available but SCLK
is now continuous.
CONVST - Convert Start, PIN 23.
A low to high transition on this input puts the track-and-hold into its hold mode and starts
conversion. This input is asynchronous to the CLKIN and independent of CS and RD.
Digital Outputs

BUSYIINT - BusylInterrupt, PIN 2.
Active low logic output indicating converter status. See timing diagrams.
DBtlJBBEN - Data Bit l1/Higb Byte Enable, PIN 4.
The function of this pin is dependent on the state of the FORMAT input (see above). When
12-bit parallel data is selected, this pin provides the DBll output. When byte data is selected,
this pin becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN
is low, DB7ILOW to DBOIDB8 become DB7 to DBO. With HBEN high, DB7ILOW to
DBOIDB8 are used for the upper byte of data (see Table 1).
DBtO/SSTRB - Data Bit to/Serial Strobe, PIN S.
The function of this pin is dependent on the state of the FORMAT input (see above). When
12-bit parallel data is selected, this pin provides the DB 10 output. If FORMAT is at either OV
or -SV, SSTRB provides a strobe or framing pulse for the serial data.
DB9/SCLK - Data Bit 9/Serial Clock, PIN 6.
The function of this pin is dependent on the state of the FORMAT input (see above). When
12-bit parallel data is selected, this pin provides the DB9 output. SCLK is the gated serial clock
output derived from the internal or external ADC clock. If FORMAT is at -SV, then SCLK runs
continuously. If FORMAT is at OV, then SCLK goes high after serial transmission is complete.
DB8/SDATA - Data Bit 8/Serial Data, PIN 7.
The function of this pin is dependent on the state of the FORMAT input (see above). When
12-bit parallel data is selected, this pin provides the DB8 output. SDATA is used with SCLK
and SSTRB for serial data transfer. Serial data is valid on the falling edge of SCLK while
SSTRB is low.

2-76

DS90PP5

.._-_
.-_
_
..--_._.
__
...-.

CS5030/CS5031

DB7ILOW, DB6ILOW, DBSILOW, DB4ILOW - Three-state data outputs, PINS 8, 9, 10, 11.
The outputs of these pins are controlled by CS and RD. Their function depends on the
FORMAT and HBEN inputs. With FORMAT high, they are always DB7-DB4. With FORMAT
low or -SV, their function is controlled by HBEN (see Table 1).
DB3IDB11, DB2IDBI0, DBIIDB9, DBOIDB8 - Three-state data outputs, PINS 13, 14, 15, 16.
The outputs of these pins are controlled by CS and RD. Their function depends on the
FORMAT and HBEN inputs. With FORMAT high, they are always DB3-DBO. With FORMAT
low or -SV, their function is controlled by HBEN (see Table 1).
HBEN

DB7/LOW DBS/LOW DBS/LOW DB4/LOW DB3/DB11 DB2IDB10 DB1/DB9

HIGH

LOW

LOW

LOW

DB?

DB6

DBO/DBB

LOW

LOW

DB11/(MSB)

DB10

DB9

DB8

DB5

DB4

DB3

DB2

DB1

DBO/(LSB)

Table 1. Output Data for Byte Interfacing

Analog Output
REF OUT - Voltage Reference Output, PIN 19.
The internal 2.SV reference is provided at this pin. The external load capability is SOOIlA.
This pin should be decoupled to AGND with a +lOIlF tantalum and a O.IIlF ceramic capacitor.
The REF OUT voltage has a settling time of approximately 1.1 sec.

Analog Input
VIN - Analog Input, PIN 20.
The analog input range for the CSS030 is ±2.SV, and unipolar 0 to +SV for the CSS031.

Ordering Guide
Model Number

Throughput
(kSPS)

Input
Range (V)

Total Unadjusted
Error (LSB)

Temp.
Range ("C)

Package

CS5030-BP
CS5030-BS
CS5030-TD

500
500
500

±2.5
±2.5
±2.5

1

-40 to +85
-40 to +85
-55 to +125

24-Pin 0.3" PDIP
24-Pin 0.3" SOIC
24-Pin 0.3" CERDIP

CS5031-BP
CS5031-BS
CS5031-TD

500
500
500

OV to +5
OV to +5
OV to +5

-40 to +85
-40 to +85
-55 to +125

24-Pin 0.3" PDIP
24-Pin 0.3" SOIC
24-Pin 0.3" CERDIP

DS90PPS

2-77

i

•

---------.,------------

CS5030/CS5031

PARAMETER DEFINITIONS
Total Unadjusted Error - TUE
Total Unadjusted Error includes offset, gain, linearity, and reference errors.
REF OUT Tempco
REF OUT Tempco is the worst case slope that is calculated from the change in reference value
at +25°C to the value at TMIN or TMAX
i.e. REF OUT Tempco = (Vref @ 25°C - Vref @ TMAX)/(TMAX - 25°C) or
REF OUT Tempco = (Vref@ 25°C - Vref @ TMIN)/(25°C - TMIN).
Differential Nonlinearity - DNL
The deviation of a code's width from the ideal width. Units in LSBs.
Positive Full-Scale Error - FSEp
The deviation of the last code transition from the ideal (VREF-3/2LSB's). Units in LSB's.
Unipolar Offset (CS5031) - Vup
The deviation of the first code transition from the ideal (1/2 LSB above AGND). Units in
LSB's.
Bipolar Offset (CS5030) - VBP
The deviation of the mid-scale transition (111...111 to 000... 000) from the ideal (112 LSB below
AGND). Units in LSB's.
Bipolar Negative Full-Scale Error (CS5030) - FSEN
The deviation of the first code transition from the ideal. The ideal is defined as lying on a
straight line which passes through the final and mid-scale code transitions. Units in LSB's.
Spurious-Free-Dynamic-Range - SFDR
The ratio of the rms value of the signal, to the rms value of the next largest spectral component
(excepting dc). This component is often an aliased harmonic. Units in percent and dBc
(decibels relative to the carrier).
Total Harmonic Distortion - THD
The ratio of the rrns sum of the significant (2ND thru 5'IH) harmonics, to the rms value of the
signal. Units in percent.
Signal-to-Noise Ratio (sin) - SNR
The ratio of the rms value of the signal, to the rrns sum of all other spectral components
(excepting dc and distortion). Expressed in decibels.
Signal-to-Noise-and-Distortion (sI[n+dJ) - SINAD
The ratio of the rms value of the signal, to the rms sum of all other spectral components
(excepting dc), including distortion components. Expressed in decibels.
2-78

DS90PP5

----------- -----------

CS5030/CS5031

Intermodulation Distortion - IMD
The ratio of the nns value of the larger of the two test frequencies, which are each 6dB down
from full-scale, to the nns value of the largest 2ND order and 3RD order intennodulation
components. Units in decibels relative to carrier.
Aperture Delay Time - tapd
The time required after the CONVST goes low, for the sampling switch to open fully.
Effectively a sampling delay which can be nulled by advancing the sampling signal. Unit in
nanoseconds.
Aperture Jitter - tapj
The range of variation in the aperture time. Effectively the "sampling window" which
ultimately dictates the maximum input signal slew rate acceptable for a given accuracy.

To ensure that jitter does not affect the quantized signal quality, the jitter induced noise
(SNRMAXjitter) must be at least 12dB below other substantial noise sources, such as quantization
noise, see Clock Considerations. Units in picoseconds.
SNR MAXjitter (dB) =20Log [

jitter RMS

DS90PP5

Vpeak

f"
21t IN JItter RMS

]

=."j clock jitter RMS 2+ analog jitter RMS 2

2-79

_

------------------._--

CS5030/CS5031

• Notes·

2-80

DS90PP5

..--....-

_..,..w..,.

~­
~--..,..,
--~
Semiconductor Corporation
_~_

CS5032

12-Bit, 500kSPS, Sampling AID Converter
Features

I

General Description
The CS5032 is a complete monolithic CMOS analogto-digital converter providing 500kSPS throughput. The
part has an internal sample-and-hold, voltage reference, and can operate with an internal or external
clock.

• Monolithic CMOS AID Converter
0.4 I!s Track/Hold Amplifier
1.6 I!s AID Converter
2.5 V Voltage Reference
Parallel, Serial and Byte Interface.
• 12-Bit ADC Linearity Error: 0.5 LSB
• Low Distortion
Signal-to-Noise Ratio: 72.8 dB
Total Harmonic Distortion: 0.01 %
Spurious-Free-Dynamic-Range: -80dBc
• Low Power: 85 mW

The CS5032 has a high-speed digital interface with
three-state data outputs and standard control inputs allowing easy interfacing to common microprocessors
and digital signal processors. Digital output data is
available in either 12-bit parallel, two 8-bit bytes, or serial formats.
The CS5032 is available in a 24-pin, 0.3" plastic dualin-line package (PDIP), Cerdip and small outline
(SOIC) package.

• 60 ppm/DC Reference Drift
ORDERING INFORMATION: Page 2-101

VA+

VA-

DB11/HBEN
DB10iSSTRB
VIN 0----01
DB9/SClK
DBBlSDATA
DB7ILOW

REF OUT

DB6ILOW
DB5ILOW
DB4ILOW
DB3/DBll

ClKIN 0 - - - - - - - - 0 > - - - - , _ _----X_ _
FORMAT

CONTROL

0---------4

and
INTERFACE

BUSynNT Q - - - - - - - - - - - j

12

DB2IDB10
DB1IDB9
DBO/DBB

AGND

DGND

Preliminary Product Information
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

CS

RD

CONVST

IThis ?ocument contains inforr~ation for a. new. product. Crystal

.
Semiconductor reserves the right to mOdify this product Without notice.
Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

,.

MAR '95
DS118PP3
2-81

....
.-..--_._.
_
_-_-_
...-.

CS5032

CHARACTERISTICS(vA+ = +5V±5%; VA- = -5V±5%; AGND = DGND = OV;
= 10MHz, unless otherwise specified. TA = TMIN to TMAX)

ANALOG
ClKIN

B
Parameter

(Note 1) Symbol

Min

Specified Temperature Range

Typ

T
Max

Min

-40 to +S5

Typ

Max

-55 to +125

Units
°C

Accuracy

VSP

-

0.25

0.5

-

0.25

0.5

lSB

Positive Full Scale Error

(Note 2)

FSEp

-

0.25

0.5

-

0.25

0.5

lSB

Bipolar Negative Full Scale Error

(Note 2)

FSEN

-

0.25

0.5

-

0.25

0.5

lSB

Dynamic Performance

(Note 3)

Signal-to-Noise-and-Distortion

(Note 4)

Integral Nonlinearity

INl

Differential Nonlinearity

DNl

Unipolar Offset Error

VUP

Bipolar Zero Error

0.25

0.5

-

-

0.5

-

0.25

0.5

0.25

0.5

lSB

-

0.5

lSB

0:25

0.5

lSB

SINAD

70

72

-

70

72

-

dB

Signal-to-Noise Ratio

SNR

70.5

72.S

-

70.5

72.S

dB

Total Harmonic Distortion

THD

-

-

0,01

-

-

-

0.01

%

0.01

%
dBc

-

dBc
dBc

Spurious-Free-Dynamic-Range

(Note 5)

SFDR

-SO
-SO

-

-SO
Intermodulation Distortion
Second Order
Third Order

(Note 6)

IMD

0,01

-

-80

-

-80
-80

-

-

-

-

+2.5

V

25

ns

-

100

ps

10

pF

-

Analog Input
Input Voltage Range

AIN

-2.5

-

+2.5

-2.5

Aperture Delay

tapd

-

25

Aperture Jitter

tapj

-

Input Capacitance

Acin

-

-

-

Notes:

1.
2.
3.
4.
5.
6.

100
10

All parameters are guaranteed by design, test, and/or characterization.
Measured with respect to internal reference and includes bipolar offset error.
AIN = ±2.5Vpp
AIN = 10kHz Sine Wave, fSAMPLE = 500kSPS. Typically 71.5dB for 10kHz

Ids

I---t Ifd2

/

~-r-

-+,a2

Ifd2

~

SSTRB

Isss
SCLK 2
SDATA

NOTES: 1.Times thes, tcss2, tesh2 and theh are the same for a high byte read as for a low byte read.
2. Continuous SCLK(Dashed line) when FORMAT -5V
Noncontinuous when FORMAT =

av.

=

Figure 4. Mode 2 Timing Diagram, Byte or Serial Read

DS118PP3

2·87

.-_
_
..--_._.
_-.._-_
...-.

CS5032

DIGITAL CHARACTERISTICS

(TA = TMIN to TMA)(: VA+ = +5V±5%; VA-

Parameter

Symbol

Min

VIH

3.3

= -5V±5%)
Typ

Max

Units

Logic Inputs
High-level Input Voltage

V

Low-level Input Voltage

VIL

0.8

V

Input leakage current

lin

50

I1A

Cin

10

pF

Input Capacitance

Logic Outputs
4.0

V

High-level Output Voltage

(Note 13)

VOH

Low-level Output Voltage

(Note 14)

VOL

0.4

V

OB11-0BO Floating State leakage Current

loz

10

I1A

OB 11-0BO Output Capacitance

Cout

15

pF

Notes:

DBN

=

13. Isource -40IlA
14. Isink = 1.6 mA

---41J----I+-~56kn

T

50pF

DGND ~
a.) High-Z to V OH

DBN

t:n
T

50pF

~DGND
b.) High-Z to V OL

Figure S. Load Circuits for Access Time

2-88

DBN

---41J----I+-3ka

T10pF

DGND ~
a.) V OH to High-Z

DB

Nf~
T

10pF

~DGND
b.) VOL

to High-Z

Figure 6. Load Circuits for Output Float Delay

DS118PP3

,.-_..--_._.
__.._-_.
......

..,

CS5032

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = OV.

All voltages with

respect to ground)
Parameter

Symbol

Min

Typ

Max

Units

Positive Analog Supply

VA+

4.75

5.0

5.25

V

Negative Analog Supply

VA-

4.75

5.0

5.25

V

Analog Input Voltage

Ain

-2.5

+2.5

V

FORMAT Input Voltage Range

VA-, OV, VA+

CLKIN Input Voltage Range

0

Other Digital Input Voltage Ranges

0

V
VA+
VA+

External Clock Frequency

10

V
V
MHz

External Clock Jitter

65

ps

AGND to DGND Voltage Differential

10

mV

ABSOLUTE MAXIMUM RATINGS (AGND =OV, All voltages with
Parameter

Symbol

Min

Positive Analog Supply

VA+

Negative Analog Supply

VA-

Analog Input Voltage

Ain

respect to ground)
Typ

Max

Units

-0.3

6.0

V

0.3

6.0

V

(VA-)-0.3

(VA+)+O.3

V

FORMAT Input Voltage Range

(VA-)-0.3

(VA+)+O.3

V

CLKIN Input Voltage Range

(VA-)-0.3

(VA+)+O.3

V

Other Digital Input Voltage Ranges

(VA-)-0.3

(VA+)+O.3

V

10

rnA

REF OUT Current
Sustained Digital Output Current

5

rnA

100

mV

-40
-55

+85
+125

°C

-65

+150

°C

+300

°C

AGND to DGND Voltage Differential
Operating Temperature Range
CS5032-BP/BS
CS5032-TO
Storage Temperature Range
Lead Solder Temperature

* WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes

DS118PP3

2-89

•

i

I.

_-_

.. ...-.
-.-..---._.
__
GENERAL DESCRIPTION
The CS5032 is a complete 12-bit 500 kSPS sampling ADC utilizing a successive approximation
architecture. Factory calibration ensures 12-bit
conversion accuracy over industrial and military
temperature ranges. The analog input range is
±2.5 V, with the output data provided in parallel,
byte or serial formats. The internal capacitor array DAC acts as an inherent sample-and-hold,
and forms the heart of the CS5032. The on-chip
+2.5 V reference is available at the REFOUT
pin. Additionally, an on-chip 10 MHz clock oscillator can be used to control converter
operations.

CS5032
applied to the capacitor array DAC. The low
temperature coefficient of the capacitor array
easily maintains 12-bit accuracy over the full
temperature range without'recalibration.
Reference Operation

The reference voltage is available at the REF
OUT pin and is capable of sourcing 500 JlA. to
peripheral devices. This pin must be decoupled
with a parallel combination of a + 10 JlF' tantalum capacitor and a 0.1 JlF' ceramic capacitor.
The reference voltage is calibrated on power-up,
with full accuracy achieved after 1.1 sec.
Analog Input

OPERATIONAL OVERVIEW
Track-and-Hold Operation

Track-and-hold operation within the CS5032 is
transparent to the user. The capacitor array DAC
acts as the hold capacitor. During tracking mode
all elements of the capacitor array DAC are
switched to the analog input for charging. The
load capacitance of the entire array during tracking mode is typically 5 pF. The input bandwidth
of the track-and-hold is typically 2 MHz. The
ADC goes into hold mode on the rising edge of
CONVST.
Capacitor A"ay DAC Calibration

To achieve 12-bit accuracy from the capacitor array DAC, the CS5032 uses a novel calibration
scheme. Each bit capacitor consists of several
capacitors that are trimmed to optimize the overall bit weighting with an internal resolution of
14-bits, resulting in nearly ideal differential and
integral linearity.
The calibration coefficients for the capacitive bit
weights are stored in an on-chip EEPROM during the factory calibration. When the converter is
subsequently powered-up these coefficients are
2-90

The CS5032 provides a ±2.5 V analog input
voltage range. The equivalent analog input circuit is illustrated in Figure 7 (shown in track
mode). During hold mode the input impedance
to the device is typically 10 MO, and the various
elements of the capacitor array DAC are connected to either AGND or VREF. In switching
back from hold mode to track mode, some elements in the capacitor array must be charged by
the analog input. For the CS5032, the worst case
charging current occurs when the analog input
changes from +2.5 V to -2.5 V.

1 kn

~A~IN~__~~.-__~~~

r

VREF

~

15kn

CapacHor
Array

rrator
AGNrD~______~______~

Figure 7. Analog Input Model.

To ensure that the capacitor array DAC has settled to within 0.25 LSB during the allowed
acquisition time, the external source resistance
should be less than 4 ill.
DS118PP3

--------.,-- ----------Output Coding

SNRMAXQuantization = (6.02dB)(# of Bits) + 1.76dB

The digital output coding is 2's complement.
Input Level
+2.5 V
OV
-2.5 V

2's Complement Output
0111 1111 1111
0000 0000 0000
1000 0000 0000

High-Speed System Clock
The CS5032 employs a high-speed clock (typically 10 MHz) to control internal operations.
This high-speed clock can be generated internally with the on-chip oscillator, or it can be
supplied from an external CMOS source. Connecting a CMOS clock signal to the CLKIN pin
allows the converter to operate from an external
clock. Alternatively, connecting the CLKIN pin
to VA- activates the internal clock oscillator.
External Clock..... CLKIN - External Clock Source
Internal Clock. .....CLKIN - VA-

CONVERT Clock Considerations
When digitizing time varying signals, it is possible to create additional noise sources over and
above those resulting from quantization noise
and thermal noise. This is particularly true when
high-speed conversion rates, or high-frequency
analog input frequencies are involved. Special
care must be taken to see that CONVST clock
jitter does not undermine high-speed signal processing applications by introducing noise into the
conversion process.
Simple quantization noise is a direct result of the
finite LSB size, which is itself related to the
number of digital output bits. Quantization
noise places a hard limit on SNR for a 12-Bit
ADC according to the following equation.

DS118PP3

CS5032

... SNRMAXQuantization = 74 dB

Although SNR can never be better than the theoretical limit, it can certainly be worse. Jitter
between the CONVST clock and the analog input signal is often one of the largest contributors
to decreased SNR, particularly as frequencies increase.
To be considered insignificant, noise related to
jitter (SNRMAXjitter) should be at least 12 dB below the other dominant noise sources, such as
quantization noise (SNRMAXQuantization). The
12 dB target is somewhat arbitrary, but yield less
than 4 % additional noise. In terms of the
CS5032, a 250 kHz analog input signal requires
less than 80 ps of jitter between the CONVST
clock and the analog input signal to achieve full
performance. The use of low-jitter CONVST
clock source is the most common means of reducing the effects of jitter. Lower conversion
rates and lower analog input frequencies are significantly less sensitive to jitter effects.

Digital Output Formats
The CS5032 provides three digital output formats. These include 12-bit parallel, two 8-bit
bytes, and a serial output mode. The output data
SNRMAX

=..J SNR MAXjitter 2+ SNRMAXQuantization 2

SNRMAXjitter (dB)

jitteIRMS

=20LOg[

.~
]
21tfJN J1ttefRMS

=..J clock j itteIRMS 2+ analog jitter RMS 2

2-91

.._-_
.-_..__
...-.
~--.-.

CS5032

format is controlled by .the level applied to the
FORMAT pin. All three of the digital output
formats can be· used with either of the convert
start timing modes ... Mode 1 and Mode 2,
which are· described in the next two sections.

FORMAT
+VA
GND
-VA

In byte mode, tWQ 8-bit read operations (four
leading zeros with 4 data bits ... plus 8 more
data bits) are required to collect the data as
shown in Figure 9. In byte mode, the
DB IllHBEN pin defers to the HBEN function,
selecting the high or low byte of data to be read
from the ADC. The lower eight bits of data are
placed on the data bus when HBEN is held low.
To access the four MSBs of data, HBEN must be
held high. The 4 MSBs of the 12-bit data word
are right justified with zeros in the upper nibble
of the high byte.

Die:ital Outputs
12-Bit Parallel
Bvte· Serial wlNon-Continuous SCLK
Byte; Serial w/Continuous SCLK

Figure 8 shows the schematic for the CS5032 in
12-bit parallel mode. The twelve bits of data are
output simultaneously on DBll1(MSB) through
DBO (LSB).

+5V

+
10llF ~

In serial mode, DB8/SDATA, DB9/SCLK and
DB lO/SSTRB defer to their serial functions. The
serial strobe pin SSTRB provides a framing sig-

~ O.1IlF

17
19

VDD

22
1218/ClK

REF OUT
18

+3V
10llF

AGND
CS5032

24
CS
RD

---Analog
Source

Analog
Signal
Conditioning

BUSY/INT
20

Control
logic

23

CONVST

VIN

DBO
12

2

12

DB11
DGND
VSS

ClK

-5V

Figure 8. System Connection Diagram: Parallel Data Format

2-92

DS118PP3

._.-.
.-_
_
..--__.._-_
...

CS5032

nal for serial data. Serial data is available at the
SDATA pin when SSTRB falls low. SSTRB
falls low within three clock cycles of CONVST.
A total of sixteen bits (four leading zeros and
twelve data bits starting with the MSB) are
clocked out on the SDATA pin on the rising edge
of SCLK. The data bits become valid no more
than tss after the rising edge of SCLK. SSTRB
goes low during data transmission and automatically returns high when the LSB has been
clocked out on the SDATA line. For serial op-

+5V

10j.1F+~

eration, OV on the FORMAT pin causes the serial clock to run only when data is being clocked
out of the device; SCLK goes high after data
transmission is completed. If the FORMAT is
connected to -VA, the SCLK output will run
continuously, independent of data transmission.
Serial data operation is identical for MODE 1
and MODE 2 timing control (see next two sections).

~0.1j.1F

117

19

VDD

REF OUT
AGND

CS5032

-

+3V
18 *0.1j.1F=¥ 10j.1F
247

CS

Analog
Source

S1
S1

=A
=B

--

Analog
Signal
Conditioning

-20

r

VIN

B

10j.1F ..L
+

..L 0.1j.1F

23

1
Control
logic

CONVST

DGND

4

_t

DBO/DB8
DB7/l0W
--

DB10/SSTRB
DB9/SClK

-

1218/ClK
VSS
121

-5V

---

DB11IHBEN

Serial cl ock operates only
during data transmission.
Serial cl ock runs continuously
indepen dent of data transmission

~~

2

BUSYIINT

12

A S1 22

RD
----

8

Data
Processor

:

5

6
7

Serial
Data
Interface

DB8/SDATA
ClK
l3

I Source
Clock I

Figure 9. System Connection Diagram: Serial and Byte Data format

DS118PP3

2-93

~
~

___-_

.... ...-..
.- --_
....

CS5032

MODE 1 Operation

conversion will read all twelve bits of data at the
same time.

The rising edge of CONVST signal is used to
put the device into hold mode and initiate a conversion. At the end of conversion the device
returns to it's tracking .mode. MODE 1 timing is
primarily used in DSP type applications where
precise control of CONVST timing is required.

MODE 1 - Byte Read
Figure 11 shows the MODE 1 timing diagram
for byte operation. At the end of conversion
when !NT goes low, either the low byte or the
high byte of data can be read, depending on the
status of HBEN. Bringing CS and RD low allows data to be read from the ADC and also
resets !NT high.

Conversion begins on the rising edge of
CONVST provided that CS is high. The
BUSYIINT line performs the INT function and
can be used to interrupt the microprocessor. INT
is normally high and goes low at the end of conversion. The ADC returns to track mode when
INT goes low. Bringing CS and RD low allows
data to be read from the ADC, and also resets
!NT high. CONVST must be high when CS and
RD are brought low for the ADC to operate correctly in this mode. Data cannot be read during a
conversion cycle because the output data latches
are disabled while a conversion is in progress.

MODE 1 - Serial Read
The MODE 1 timing diagram for serial operation
is shown in Figure 12. Conversion begins on the
rising edge of CONVST, and data is clocked out
on SDATA immediately upon the falling edge of
SSTRB. The data is output as four leading zeroes followed by the twelve data bits with the
MSB first. The first zero should be latched into
the external receiving circuitry on the first falling
edge of SCLK after SSTRB goes low. A total of
sixteen falling SCLK edges will latch all sixteen
bits of output data. SSTRB automatically returns
high after the last bit of data has been clocked
out of the device.

MODE 1 - 12-Bit Parallel Read
Figure 10 shows the MODE 1 timing diagram
for 12-bit parallel operation (FORMAT = +VA).
A data read operation performed at the end of

CONVST~) Hold mode.
Conversion begins
INT

conversion--()-~~LJ- INT is reset on falling edge of CS and RD

End of
Acquisition begins

(C

CS

t

)J

CS must be high when CONVST
goes low for conversion to occur
((

])

RD

I

Databits automatically three-state
during a conversion

~

I

Data relinquished
after RD goes high

'I-D-A-T-A-~

DATA
Figure 10. Mode 1 Timing Diagram, 12-bit Parallel Read
2-94

DS118PP3

...-..
_.-_.........
__.._-_

CS5032

CONVST ~

,.

~SrH-o-ld-m--od-e-.------------------------------

~ Conversion begins

;

e>jLJ- INT
-- is reset on falling edge of CS
- and -RD

INT

End of conversion
Acquisition begins - - - - - . j

((

))

t

CS

CS must be high when CONVST
goes low for conversion to occur
RD

e>f)

I I

Data relinquished

Data bits automatically three-state'-------' after RD goes high
during a conversion ~)

S~

DATA

l/

DATA

+

I I
I

~

DATA

LOW BYTE DATA 1
HIGH BYTE DATA 1
NOTES: 1. In the above diagram HBEN is exercised to read the low byte first (DB7-DBO) and
then the high byte (DB11-0B8). To change the order in which the bytes are read,
simply invert the HBEN signal shown above.

Figure 11. Mode 1 Timing Diagram, Byte Read

CONVST

Acq~isition

--1

I

((

~

begms
SCLK

I

I

LJ LJ
SSTRB

SDATA

I
II

f>
UJ
I
I
I
I
I

1

))

Hold mode.
Conversion begins
4

5

6

7

e>i
((
))

(>i FOUR LEADING ZEROS

I I I I:: I
DB11

DB10

DB9

DBO

Figure 12. Mode 1 Timing Diagram - Serial Read

DS118PP3

2-95

.._-_.
.-_..-...-

~

~--.-.

CS5032

MODE 2 Operation

Mode 2 operation allows the ADC conversion to
be initiated by a read operation from a Jlc. The
BUSY signal can be used in this mode to halt
JlC operations by placing the JlC in a WAIT state
until the conversion is complete. This avoids
having to handle interrupts and timing delays, assuring that the conversion cycle is complete
before any attempted data read.
In this mode, CONVST must be held permanently low. Bringing CS low (while HBEN is
low) puts the device into hold mode and initiates
a conversion. The BUSYIINT pin defers to the
BUSY function such that BUSY goes low at the
start of conversion and returns high at the end of
conversion.
MODE 2 • 12·Bit Parallel Read
The MODE 2 timing diagrams for the parallel
data output format are shown in Figure 13. This
mode of operation forces the JlC into a WAIT

state until the conversion has been completed. It
removes the risk of inadvertently reading invalid
data before the conversion cycle has been completed.
MODE 2 • Byte Read
Figure 14 shows the timing diagram for byte operation in MODE 2. Since HBEN must be low to
initiate a conversion, the lower byte of data will
be accessed first during the two-byte read operation. This is followed by a second byte read
operation (with HBEN high) to complete the
data transfer.
MODE 2 • Serial Read
The timing diagram for MODE 2 serial operation
is shown in Figure 15. The device goes into hold
mode on the falling edge of CS and conversion
begins when BUSY goes low. The data is
clocked out similarly as for MODE 1 serial operation. Upon clocking of the final data bit
BUSY returns high indicating end of conversion.

hard wire low for

CoNVST----------------------~c~h~M-O--D-E-2-o~p-e-ra-t-io-n------CS

t-HOLD MODE

Ii)
"

RD

BUSY

Conversion
begins

=1

"---------------'cc",,----------

End of conversion
Acquisition begins

Data bits automatically three-state

DATA

~d~U~ri~ng~CO~n~v~e~rs~io~n~_____~~·~c~h~--~1

DATA

Figure 13. Mode 2 Timing Diagram, 12-bit Parallel Read

2·96

DS118PP3

----------------------

CS5032
hard wire low for MODE 2 operation

CONVST

-I

'-£LLL_LLLLL4-_---<~~,---------¥'~~

HBEN

[9i~i9i£;J

~L_H_O_LD_M~~~JD-E------~~~----~I

CS
RD
-

I

'h

Co,:version ::::J
begins
. ~s------l

BUSY

11<-'_ _- ' -

,--End of conversion
Acquisition begins

Data bits automatically three-state
during conversion
,)~r-D-A-TA--Ir-----II DATA 1-1_ _ __

DATA

LOW BYTE
DATA

HIGH BYTE
DATA

Figure 14. Mode 2 Timing Diagram, Byte Read

HBEN

~~~_ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~S~S--~----li~~D~oun'~t~C~a~r~u~

CONVST _ _ _ _+-~:=L-_h_ar_d_w_i_re_l_o_w_f_or_M_O_D_E_2~op~e_r_m_io_n_ _ _~S~S--~--------CS
RD

BUSY

SCLK

~ Hold mode
I
I

Ch

+---

Conversion begins

End of conversion
Acquisition begjns

6

7

=j

J1J

I I I I
LI

LI

I I
LI

I
I

SSTRB

SDATA
1 FOUR LEADING ZERosl DB111 DB101 DB91 ,::::1

Figure 15. Mode 2 Timing Diagram, Serial Read

DS118PP3

2-97

--------..,-- -----------

CS5032

STAND·ALONE OPERATION

Power Supplies, AGND, and DGND

The CS5032 supports stand-alone conversion
when used in MODE 2 parallel interface operation as shown in Figure 16. Conversion is
initiated by pulse to the CS input of the ADC.
The duration of the pulse must be longer than
the ADC conversion time. The BUSY output
drives the RD input and data is latched on the
rising edge of BUSY to an external latch.

Figure 8 illustrates the recommended power supply decoupling scheme with a 0.1 J.IF ceramic
and a + 10 J.IF tantalum capacitor for both the
VA+ and the VA- pins. The capacitors should be
located as close as practical to the supply pins.
AGND is the power supply current return, and is
also the preferred ground reference for the decoupling capacitors .

• tcs

-1

r-

~
EN

es
BUSY
CS5032

LATCH

RO

Typically a low-impedance ground plane is used
around and under the ADC, with connections to
both AGND and DGND. If a split ground is
used, DGND is the ground reference for any
digital circuits that follow the CS5032. When
split grounds are used, the AGND to DGND
voltage differential should be kept below
±10 mV for best operation.

OB11
OBO
• t cs > tcbd + tconv

Figure 16. Stand-Alone Operation

Schematic &Layout Review Service

If the power supply voltage is dropped below

3 V, the ADC may need to be reset by switching
power off and then back on .
Layout considerations

The CS5032 is a high-speed component which
requires adherence to standard high-frequency
printed circuit board layout techniques to maintain optimum performance. These include
proper supply decoupling, minimum length circuit traces, and physical separation of digital and
analog components and circuit traces. See the
CDB5032 evaluation board data sheet for more
details.

Confirm Optimum
Schematic & Layout
Before Building Your

2·98

DS118PP3

_.-_..--_.-.
__.._-_
...-.

CS5032

PIN DESCRIPTIONS

READ
BUSY/INTERRUPT
BusvnNT
CLOCK INPUT
ClKIN
DB11/HIGH BYTE ENABLE DBlllHBEN
DB10/SERIAL STROBE DB101SSTRB
DB9/SERIAL CLOCK
DB91SClK
DBB/SERIAL DATA DB8ISDATA
DB7/l0W
DATA OUT
DATA OUT
DB6/l0W
DATA OUT
DBS/lOW
DATA OUT
DB4/l0W
DIGITAL GROUND
DGND

CS
CONVST
FORMAT
VAAIN
REF OUT
AGND
VA+
DBOIDB8
DB1IDB9
DB2IDB10
DB3IDBll

CHIP SELECT
CONVERT START
DATA OUTPUT FORMAT
NEGATIVE ANALOG SUPPLY
ANALOG INPUT
VOLTAGE REF OUT
ANALOG GROUND
POSITIVE ANALOG SUPPLY
DATA OUT
DATA OUT
DATA OUT
DATA OUT

Pinout applies to both DIP and SOIC packages.

Power Supply Connections

VA+ - Positive Supply, PIN 17.
+SV±S%.
VA- - Negative Supply, PIN 21.
-SV±5%.
DGND - Digital Ground, PIN 12.
Ground reference for digital circuitry.
AGND - Analog Ground, PIN 18.
Ground reference for track-and-hold, reference and DAC.
Oscillator

CLKIN - Clock Input, PIN 3.
An external lOMHz (CMOS compatible) clock is applied at this pin. Connecting this pin to VAenables the internal clock oscillator.
Digital Inputs

CS - Chip Select, PIN 24.
Active low logic input. The device is selected when this input is active. With CONVST tied
low, a new conversion is initiated when CS goes low.

DSl18PP3

2-99

•

i

.._-_
_.-_..--_._.
__
...-.

CS5032

RD - Read, PIN 1.
Active low logic input. This input is used in conjunction with CS low to enable the data
outputs.
FORMAT - Output Mode Selection, PIN 22.
Defines the output data format and serial clock format. With FORMAT at +5V, the output data
format is 12-bit parallel only. With FORMAT at OV, either byte or serial data is available and
SCLK is not continuous. With FORMAT at -Sv, byte or serial data is again available but SCLK
is now continuous.
CONVST - Convert Start, PIN 23.
A low to high transition on this input puts the track-and-hold into its hold mode and starts
conversion. This input is asynchronous to the CLKIN and independent of CS and RD.
Digital Outputs

BUSYIINT - BusylInterrupt, PIN 2.
Active low logic output indicating converter status. See timing diagrams.
DBlllHBEN - Data Bit lllHigb Byte Enable, PIN 4.
The function of this pin is dependent on the state of the FORMAT input (see above). When
12-bit parallel data is selected, this pin provides the DB 11 output. When byte data is selected,
this pin becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN
is low, DB7ILOW to DBOIDB8 become DB7 to DBO. With HBEN high, DB7ILOW to
DBOIDB8 are used for the upper byte of data (see Table 1).
DBlO/SSTRB - Data Bit lO/Seriai Strobe, PIN 5.
The function of this pin is dependent on the state of the FORMAT input (see above). When
12-bit parallel data is selected, this pin provides the DB 10 output. If FORMAT is at either OV
or -SV, SSTRB provides a strobe or framing pulse for serial data.
DB9/SCLK - Data Bit 9/Serial Clock, PIN 6.
The function of this pin is dependent on the state of the FORMAT input (see above). When
12-bit parallel data is selected, this pin provides the DB9 output. SCLK is the gated serial clock
output derived from the internal or external ADC clock. If FORMAT is at -SV, then SCLK runs
continuously. If FORMAT is at Ov, then SCLK goes high after serial transmission is complete.
DB8/SDATA - Data Bit 8/Serial Data, PIN 7.
The function of this pin is dependent on the state of the FORMAT input (see above). When
12-bit parallel data is selected, this pin provides the DB8 output. SDATA is used with SCLK
and SSTRB for serial data transfer. Serial data is valid on the falling edge of SCLK while
SSTRB is low.

2·100

DS118PP3

----------------------

CS5032

DB7ILOW, DB6ILOW, DBSILOW, DB4ILOW - Three-sta~ data outputs, PINS 8, 9, 10, 11.
The outputs of these pins are controlled by CS and RD. Their function depends on the
FORMAT and HBEN inputs. With FORMAT high, they are always DB7-DB4. With FORMAT
low or -Sv, their function is controlled by HBEN (see Table 1).
DB3IDB11, DB2IDBI0, DBIIDB9, DBOIDB8 - Three-state data outputs, PINS 13, 14, IS, 16.
The outputs of these pins are controlled by CS and RD. Their function depends on the
FORMAT and HBEN inputs. With FORMAT high, they are always DB3-DBO. With FORMAT
low or -SV, their function is controlled by HBEN (see Table 1).
HBEN

DB7ILOW DB6/LOW DBS/LOW DB4/LOW DB3IDB11 DB2IDB10 DB1/DB9

DBOIDB8

HIGH

lOW

lOW

lOW

lOW

DB11/(MSB)

DB10

DB9

DB8

lOW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DBO/(lSB)

Table 1. Output Data for Byte Interfacing
Analog Output
REF OUT - Voltage Reference Output, PIN 19.
The internal 2.SV reference is provided at this pin. The external load capability is SOO~A.
This pin should be decoupled to AGND with a +lO~F tantalum and a O.1~F ceramic capacitor.
The REF OUT voltage has a settling time of approximately 1.1 sec.
Analog Input
AIN - Analog Input, PIN 20.
The analog input range for the CSS032 is ±2.5Y.

Ordering Guide
Model Number

Throughput
(kSPS)

Input
Range (V)

Linearity
Error (LSB)

Temp.
Range (Oe)

Package

CS5032-BP
CS5032-BS
CS5032-TD

500
500
500

±2.5
±2.5
±2.5

±D.5
±D.5
±D.5

-40 to +85
-40 to +85
-55 to +125

24-Pin 0.3" PDIP
24-Pin 0.3" SOIC
24-Pin 0.3" CERDIP

DS118PP3

2-101

..-t.
~

----------------------

CS5032

PARAMETER DEFINITIONS
Integral Non-Linearity Error - INL
The deviation of a code from a straight line passing through the endpoints of the transfer
function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 112
LSB below the first code transition and "full-scale" is a point 112 LSB .beyond the code
transition to all ones. The deviation is measured from the middle of each particular code.
REF OUT Tempco
REF OUT Tempco is the worst case slope that is calculated from the change in reference value
at +25°C to the value at TMIN or TMAX
i.e. REF OUT Tempco = (Vref @ 25°C - Vref @ TMAX)/(TMAX - 25°C) or
REF OUT Tempco = (Vref @ 25°C - Vref @ TMIN)/(25°C - TMIN).
Differential Nonlinearity - DNL
The deviation of a code's width from the ideal. Units in LSBs.
Full-Scale Error - FSEp
The deviation of the last code transition from the ideal (VREF-3/2 LSB's). Units in LSB's.
Bipolar Offset - VBP
The deviation of the mid-scale transition (011 ... 111 to 100... 000) from the ideal (1/2 LSB below
AGND). Units in LSB's.
Bipolar Negative Full-Scale Error - FSEN
The deviation of the first code transition from the ideal. The ideal is defined as lying on a
straight line which passes through the final and mid-scale code transitions. Units in LSB's.
Spurious-Free-Dynamic-Range - SFDR
The ratio of the rms value of the signal, to the rms value of the next largest spectral component
( excepting de). This component is often an aliased harmonic. Units in percent and dBc
(decibels relative to the carrier).
Total Harmonic Distortion - TUD
The ratio of the rms sum of the significant (2nd thru 5th) harmonics, to the rms value of the
signal. Units in percent.
Signal-to-Noise-and-Distortion (sin) - SNR
The ratio of the rms value of the signal, to the rms sum of all other spectral components
(excepting de and distortion terms). Expressed in decibels.
Signal-to-Noise-and-Distortion (sI[n+d]) - SINAD
The ratio of the rms value of the signal, to the rms sum of all other spectral components
(excepting de), including distortion components. Expressed in decibels.

2-102

DS118PP3

----------------------

CS5032

Intermodulation Distortion - IMD
The ratio of the nTIS value of the larger of the two test frequencies, which are each 6dB down
from full-scale, to the rms value of the largest 2 nd order and 3rd order intermodulation
component. Units in decibles relative to carrier.
Aperture Delay Time - tapd
The time required, after the converter goes into hold mode, for the sampling switch to open
fully. Effectively a sampling delay which can be nulled by advancing the sampling signal.
Unit in nanoseconds.
Aperture Jitter - tapj
The range of variation in the aperture time. Effectively the "sampling window" which
ultimately dictates the maximum input signal slew rate acceptable for a given accuracy.
SNRMAXjitter (dB)

=20Log [ 21tfIN J..ItterRMS
1
]

jittefRMS = -V clock j itterRMS 2 + analog jitter RMS

2

To ensure that jitter does not affect the quantized signal quality, the jitter induced noise
(SNRMAXjitter) must be at least 12dB below other substantial noise sources, such as quantization
noise, see Clock Considerations. Units in picoseconds.

DS118PP3

2-103

_

..............
.............
•

.w~

.. ..... .

ICDB5030 CDB5031 CDB5032I

Semiconductor Corporation

EvaluatianBaards far CS5030, CS5031 & CS5032
Features

General Description

• Throughput rates up to 500kHz.

The CDB5030/31/32 Evaluation Boards allow fast
evaluation of the CS5030, CS5031 & CS5032 12-bit,
500kHz, sampling AID Converters.

• Operation with on-board or off-board
clocks.

The board provides a convenient platform for easy circuit development and evaluation. A versatile tool that
can simplify design and reduce the design cycle resulting in a quicker time to market.

• Buffered serial data, 12-bit parallel word,
or two a-bit bytes

Analog input is via a BNC connector. Buffered digital
outputs are available from the ADC in serial, 12-bit parallel word, or two a-bit bytes formats.

• Digital and Analog Patch Areas

Ordering Information
• CS5030
CS5031
CS5032

±2.5V input
OV to +5V input
±2.5V input

CDB5030 Evaluation Board with CS5030-BP Installed
CDB5031 Evaluation Board with CS5031-BP Installed
CDB5032 Evaluation Board with CS5032-BP Installed

ANALOG
PATCH
AREA

VOLTAGE PROTECTION

DIGITAL
PATCH
AREA

DIGITAL
ELECTRONICS
VA+

VA-

AIN

DB11IHBEN
DB10/SSTRB
DB9/SCLK
DB8ISDATA
DB7ILOW
DB6ILOW
DB5ILOW
DB4ILOW
DB3IDB11
DB2IDB10
CONVST
DB1/DB9
DBO/DBS

CLOCK AND
CONVERSION START
CIRCUITRY

CONVST

cs
RD

...J

wa:
:::lw

CS

~~
«W

RD

Do-D11

1l.J:

FORMAT
JUMPER

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

SSTRB
SCLK
SDATA

---

FORMAT

BUSYIINT

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

BUSY

MAR '95
DS90DB3
2-104

-

......-....
............
......

~

~

."

CDB5030, CDB5031, CDB5032

Introduction

least one individual decoupling capacitor is provided for each Ie.

The CDB5030, CDB5031, and CDB5032 evaluation boards provide a tool for testing and
designing with the CS5030/1/2 series of AID
Converters. The boards are configured for operation from ±5V analog and +5V digital power
supplies. A BNC connector is provided for the
analog input signal. An on-board jumper selects
the output data and serial clock formats. Parallel
and serial connectors provide an interface to the
digital logic.
Power Supplies
Figure 1 shows the power supply arrangements.
±5V is required to operate the ADC and analog
portion of the board. Zener diodes are provided
for over-voltage protection. A separate +5V digital supply is required for the digital logic. At

Analog Input Circuit

I

The analog input signal is brought on the evaluation board via the BNC connector J8 (figure 2).
Diodes D 1 and D2 provide protection against
over voltage. R4 and C13 make a low pass filter,
whose corner frequency is 318 kHz. Notice that
no external trim components are required. R6 is
a 10 ill terminating resister which provides a
load for the signal source. R6 can be changed to
match the analog input source impedance if required. The footprint is large enough to
accommodate a 50 n, 0.5 W resistor.

+5VA

AGND
I--~I----------------------«

-5VA

+5V

Z3

lN6267
6.Bv

GND

Figure 1. Power Supplies

DS90DB3

.-

2-105

--_-__.

.-....,.....
.........,.

~

CDB5030, CDB5031, CDB5032

+SVA

2

01

BAT85
J8

R4

AIN
02

BAT85

AGND

AGND

-SVA

Figure 2. Analog Input Circuit

Clock and Conversion

Figure 3 shows the on-board clock and conversion control circuitry. The evaluation board is
designed to run off the on-board 10 MHz oscillator (U4). The ADC can also operate from an
internal clock oscillator, by connecting the
CLKIN pin to -5VA. Test points are provided to
easily implement the internal oscillator.
The CONVST signal on the evaluation board is
derived from the on-board 10 MHz clock oscillator. The 10 MHz is divided by 20, providing a
500 kHz· signal. External signals can be used by
breaking the CONVST jumper at the test points
and attaching the external signal at pin 6 of connector J4.
Digital Output Data

The CS5030/31132 ADCs support three digital
output data formats. These include 12-bit parallel, 8-bit byte, and serial interface formats.
Several of the ADC output pins have dual roles
or modes of operation (see the CS5030/31 or
CS5032 data sheets). The position of the "FORMAT" jumper determines which output format is
active, with all three formats available through
2-106

the 40-pin header 14. Serial output data is also
available through the 1O-pin header 13.
12-Bit Parallel Operation
Selecting the "+" position for the "FORMAT"
jumper places the board in 12-bit parallel mode.
All parallel output signals are buffered by Ul
and U3, and are available on header J4 (figure
4). The rising edge of the BUSY signal, available on pin-40 of 14, can be used to latch the
12-bit parallel data into subsequent digital circuitry.
8-Bit Byte Operation
Selecting the "0" or the "-" position for the
"FORMAT" jumper places the board in 8-bit
byte mode. The data is available on DO to D7 of
header J4 in two separate read operations. The
lower byte is read with HBEN low. The four
more significant bits are read with HBEN high.
The high byte word includes four leading zeros
(D4 to D7) to fill out the remaining four significant bits from the ADC. All byte output signals
are buffered by Ul and U3.
Serial Operation
Selecting the "0" or the "-" position for the
"FORMAT" jumper also places the board in seDS90DB3

............
...--_._.-.
.........
~

.-

CDB5030, CDB5031, CDB5032

rial mode. In the "-" position, the serial clock
SCLK operates continuously; in the "0" jumper
position, the serial clock SCLK is active only
when the ADC is outputting serial data. The rising edge of SCLK can be used to latch serial
data into subsequent circuitry. The serial data
and control lines are available on 13, and the
DATA8 (SDATA), DATA9(SCLK), and DATAI0
(SSTRB) lines of J4. All serial output signals
are buffered by U1.
Convert Start Operation
MODE 1 Operation
The CONVST signal is used to put the ADC into
hold mode and initiate a conversion. At the end
of the conversion, the ADC returns to its tracking mode. Conversion begins on the rising edge
of the CONVST, provided that CS is high (note
that external pull-up resistors on CS and RD default both to logic high if no external logic signal
is present for these pins on the J4 header). The

BUSY line on J4, which goes low when the output data becomes available, can be used as a
microprocessor interrupt. Bringing CS and RD
low allows data to be read from the ADC and
also resets BUSY high. CONVST must be high
when CS and RD are brought low in this mode.
Data cannot be read during the conversion cycle
because the ADC output latches are disabled
during this process.
MODE 2 Operation
In this mode, CONVST is held permanently low
(Break CONVST jumper at the test points and
add jumper between CONST_BUF and
CONVST. Ground the HOLD signal J4-6).
Bringing CS low (while HBEN is low) through
the J4 header, puts the ADC into hold mode and
initiates a conversion. The BUSY line on J4
goes low at the start of the conversion and returns high at the end of conversion.

FORMAT JUMPER

+

o

+5Y

12-bit
8-bit b
FORMAT .JUMPER

+

o

S+.....-~--C::>FORIIAT

.---------------------4!i)--4!j---C)CLKIN

-5Y"~

+'Y

eNO

/CONYST _BUF D-----@ ~~C) /CONYST

74HC390

GNO

/CONVST JUMPER

Figure 3. Clock and Convert Start Circuitry
DS90DB3

2-107

~
.,...

....I))
g

o

REF _OUT

te

lOOK

J!:11

+5VA

r---~---------t----~IBIAGNO
21 VSS

AGND
-5VA



AlN

eLKIN

C

/eDNVST [
FDRMAT [

~

I

Cf

REF _OUT

AGND AGNO

OA1A11

~

DAT~06

l!

OA1A05

m
lB

083/0811 1

082/0810

g:ri~m

1

1~

L

16

Rilok
esa.-'-

OA

on

orr

IlUsy/iNT

~i~D~A~T~AO~3§3

Yl
YO
Y2
Y3
Y4
Y51:j;t:==:::l

CS5030
A/D Converter

~~

'---~
74HC541

+5V

A07

74HC541
U3

OGND
GND

J4

11~~~~~~~~~~~~~~~i

?+5V

CJ--

DATA"

AGNO

081D/SSTR8
089/SCLK
D8B/SOATA
D87!LOW
D86/LOW 10
D811/H8EN 11

gmt8=

~VIN

19

tom

7

,& ~ri~T ~~r
U2
17 VDO

..

J3

U68
FORMAT

,,
...1=....i'·,,
,=,...:

HDR20X2

\;;!
OATA[OO,II]

u·--+-~\I

/CONVST _BUF

o
c

10K

~

9

o

C
ID

CII.

...B
o
~

CD

o

C

~

C
ID

Figure 4. ADC Connections and Digital Output

~

.. _..
. ..,.....
.............
~-

~~-

CDB5030, CDB5031, CDB5032

14

9
III!
mmT

000
cue

i

I

Dzi

-0

BAm II I

De

DZ

D1 •

DO(l58)

U4

J8

OSCILLATOR

AIN

DI
DI
D7
D5
D4
D3

U2

., .~" ,i1§OO;BUs

D11(11Sa)
D1D

I
r-

&,,':;;IT.1fL
SEMICONDUCTOR CORPORATION

Figure 5. CDB5030/CDB5031/CDB5032 Component Layout

DS90DB3

2-109

..,.... ._..
....
..,.., .....

.

..,..,~

~--

CDBS030, CDBS031, CDBS032

••••••
•••••••
•••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
•••

Figure 6. Top Ground Plane Layer (NOT TO SCALE)

2-110

DS90DB3

.. ...
. ..,.,-.-...,.
~~

..,

~~-

CDB5030, CDB5031, CDB5032

~~

••••
•••••
•••••
•••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••

Figure 7. Bottom Trace Layer (NOT TO SCALE)

DS90DB3

2-111

..
_-

....
. ... ._.
..............
~.-

~~

CDB5030, CDB5031, CDB5032

• Notes·

2-112

DS90DB3

........... ..
. ..........
~

~

~

~~

ICS5101A CS5102A I

~

Semiconductor Corporation

16..8it, 100 kHzl20 kHz AID Converters
Features

General Description

• Monolithic CMOS AID Converters
Inherent Sampling Architecture
2-Channel Input Multiplexer
Flexible Serial Output Port

The CS5101A and CS5102A are 16-bit monolithic
CMOS analog-to-digital converters capable of 100 kHz
(5101A) and 20 kHz (5102A) throughput. The
CS5102A's low power consumption of 44 mW, coupled
with a power down mode, makes it particularly suitable
for battery powered operation.
.

• Ultra-Low Distortion
S/(N+D): 92 dB
THD: 0.001%

On-chip self-calibration circuitry achieves nonlinearity
of ±0.001% of FS and guarantees 16-bit no missing
codes over the entire specified temperature range. Superior linearity also leads to 92 dB S/(N+D) with
harmonics below -100 dB. Offset and full-scale errors
are minimized during the calibration cycle, eliminating
the need for external trimming.

• Conversion Time
CS5101A: 8/ls
CS5102A: 40 /ls
• Linearity Error: ± 0.001 % FS
Guaranteed No Missing Codes

The CS5101A and CS5102A each consist of a 2-channel input multiplexer, DAC, conversion and calibration
microcontroller, clock generator, comparator, and serial
communications port. The inherent sampling architecture of the device eliminates the need for an external
track and hold amplifier.

• Self-Calibration Maintains Accuracy
Over Time and Temperature
• Low Power Consumption
CS5101A: 320 mW
CS5102A: 44 mW
Power-down Mode: < 1 mW

The converters' 16-bit data is output in serial form with
either binary or 2's complement coding. Three output
timing modes are available for easy interfacing to microcontrollers and shift registers. Unipolar and bipolar
input ranges are digitally selectable.

• Evaluation Board Available

ORDERING INFORMATION: Page 2-148
BP/UP
TRK1
SSH/SDL
TRK2
CRS/FIN

SCLK

TEST

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

25

23

6

VA+

VA-

DGND

27

SCKMOD

18

OUTMOD

7
VD-

VD+

Copyright © Crystal Semiconductor Corporation 1995
(All Rights ReseNed)

MAR '95
DS45F2
2-113

_
..--__.._-_
.....
._..
.-_

CS5101A

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ =5V; VA-, VD- = -5V;
VREF = 4.5V; Full-Scale Input Sinewave, 1 kHz; CLKIN = 4 MHz for -16,8 MHz.for -8; fs = 50 kHz for -16,
100 kHz for -8; Bipolar Mode; FRN Mode; AIN1 and AIN2 tied'together, each channel tested separately; Analog
Source Impedance = 50 n with 1000 pF to AGND unless otherwise specified)
CS5101A-J,K
Parameter·

Min

Specified Temperature Range
Accuracy
Linearity Error
-J,A,S
(Note
-K,B,T
Drift
(Note
(Notes 3
Differential Linearity
-J,A,S
(Note
Full Scale Error
-K,B,T
(Note
Drift
Unipolar Offset

-J,A,S
-K,B,T
Drift

Bipolar Offset

-J,A,S
-K,B,T
Drift

Typ

Max

CS5101 A-A,B
Min

o to +70
1)

-

2)
4)
1)

16

2)

(Note 1)
(Note 2)
(Note 1)
(Note 2)

Bipolar Negative Full-Scale Error
-J,A,S
(Note 1)
-K,B,T
Drift
(Note 2)

Dynamic Performance (Bipolar Mode)
Peak Harmonic or Spurious Noise (Note 1)
1 kHz Input
-J,A,S
-K,B,T
12 kHz Input
-J,A,S
-KBT
Total Harmonic Distortion -J,A,S
-KBT
(Note 1)
Signal-to-Noise Ratio
OdB Input
-J,A,S
-K,B,T
-60 dB Input
-J,A,S
-KBT
Noise
(Note 5)
Unipolar Mode
Bipolar Mode

-

-

16

-

±4
±3
-

-

±1
±1
±2

±5
±3

LSB
LSB
dLSB

100,
102
88
91
0.002
0.001

-

94
98
83
85

100
102
88
91
0.002
0.001

-

dB
dB
dB
dB
%
%

90
92
30
32

-

dB
dB
dB
dB

35
70

-

-

96
98
85
85

-

87
90

-

90
92
30
32

-

-

90
92
30
32

-

35
70

-

35
70

87
90

-

-

-

-

-

±1
±1
+1

100
102
88
91
0.002
0.001

-

-

-

96
98
85
85

-

-

0.002 0.004 %FS
0.001 0.003 %FS
+ 1/2
dLSB
Bits
LSB
±2
±5
LSB
±2
±4
+2
- dLSB
LSB
±2
±5
LSB
±2
±4
dLSB
+2
LSB
±2
±5
LSB
±2
±3
dLSB
+2

-

±4
±3

-

°C

±4
±3

±1
±1
+1

-

-

-

Units

±1
±1
+1
±2
±2
±1
±2
±2
+2

-

-

±5
±3

Max

-

-

-

-

±5
±4

Typ

-

±4
±3

-

Min

-55 to +125

0.002 0.003
0.001 0.002
± 1/4

±1
±1
+1
±2
±2
+1
±2
±2
+1

-

Max

-40 to +85

0.002 0.003
0.001 0.002
± 1/4

-

Typ

CS5101A-S,T

-

±5
±4

-

±5
±3

-

16

-

-

-

-

87
90

-

-

-

-

-

-

-

-

-

-

J.l.Vrms
ILVrms

Notes:

1. Applies after calibration at any temperature within the specified temperature range. At temp
2. Total drift over specified temperature range after calibration at power-up at 25°C.
3. Minimum resolution for which no missing codes is guaranteed over the specified temperature range.
4. Clock speeds of less than 1.0 MHz, at temperatures >100°C will degrade DNL performance.
5. Wideband noise aliased into the baseband. Referred to the input.
100°C will degrade DNL performance.

'Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet).

Specifications are subject to change without notice.

DS45F2

2-117

•

_._.......__......._-_
..._.-.
..,

CS5102A

ANALOG CHARACTERISTICS

(continued)
eS5102A -J,K

eS5102A -A,B

eS5102A -S,T

Symbol Min Typ Max Min Typ Max Min Typ Max Units

Pai'ameter*

-

Specified Temperature Range

o to +70

40 to +85

-55 to +125

°C

Analog Input
Aperture Time
Aperture Jitter
Input Capacitance

(Note 6)
Unipolar Mode
Bipolar Mode

-

-

30

-

-

30

-

-

-

-

100

100

-

-

320
200

425
265

-

320
200

425
265

-

40.625

-

-

20

-

40.625

9.375

-

2.4
-2.4
2.5
-1.5

3.5
-3.5
3.5
-2.5

-

-

44
1

-

30

-

ns

100

ps

-

-

320
200

425
265

pF
pF

-

-

40.625

Ils

9.375

-

9.375

IlS

-

20

-

-

kHz

3.5
-3:5
3.5
-2.5

-

2.4
-2.4
2.5
-1.5

3.5
-3.5
3.5
-2.5

rnA

-

2.4
-2.4
2.5
-1.5

65

-

-

44
1

65

-

44
1

65

mW
mW

-

-

84
84

-

84
84

-

dB
dB

-

Conversion & Throughput
Conversion Time

(Note 19)

Acquisition Time

(Note 20)

ta

-

Throughput

(Note 21)

flp

20

Power Supply Current
(Note 22)
Positive Analog
Negative Analog
(SLEEP High)
Positive Digital
Negative Digital

IA+
IAID+
ID-

(Notes 11, 22)
(SLEEP High)
(SLEEP low)

Pdo
Pds

Power Supply Rejection:
(Note 23)
Positive Supplies
Negative Supplies

PSR
PSR

tc

Power Supplies

Power Consumption

-

-

84
84

-

-

-

-

-

-

mA
mA
mA

Notes: 19. Conversion time scales directly to the master clock speed. The times shown are for synchronous,
internalloopback (FRN mode). In PDT, RBT, and SSC modes, asynchronous delay between the falling
edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will
not exceed 1 master clock cycle + 140 ns.
20. The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 j.lS of fine charge.
FRN mode allows 9 clock cycles for fine charge which provides for the minimum 5.625 IlS with an 1.6 MHz
clock, however; in PDT, RBT, or SSC modes, at clock frequencies less than 1.6 MHz, fine charge may
be less than 9 clock cycles.
21. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions
affecting acquisition and conversion times, as described above.
22. All outputs unloaded. All inputs at VD+ or DGND. See table below for power dissipation vs. clock frequency.
23. With 300 mV pop, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 23 shows a plot of typical power supply
rej~ction versus frequency.
Typ. Power (mW) elKIN (MHz)
34
0.8
1.0
37
39
1.2
1.4
41
44
1.6
2-118

DS45F2

___
......
_-.
_.....--...
._.

CS5102A

SWITCHING CHARACTERISTICS (TA = TMIN to T.MAX;
VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Inputs: logic 0 = OV, logic 1 = VD+;

CL

= 50 pF)

Symbol

Min

Typ

Max

Units

tclk

0.5

-

10

/-!s

ClKIN low Time

tclkl

200

-

-

ns

ClKIN High Time

tclkh

200

-

-

ns

fxtal

0.9

1.6

2.0

MHz

Parameter
ClKIN Period

Crystal Frequency

(Note 18,24)

(Note 24, 25)

-

-

20

-

ms

RST Pulse Width

trst

150

-

-

ns

RST to STBY Falling

tdrrs

100

-

ns

2,882,040

-

tclk

80

-

ns

-

68tclk+260

ns

SLEEP Rising to Oscillator Stable

(Note 26)

CH1/2 Edge to TRK1, TRK2 Rising

(Note 27)

tdrsh1

CH1/2 Edge to TRK1, TRK2 Falling

(Note 27)

tdfsh4

HOLD to SSH Falling

(Note 28)

tdfsh2

-

HOLD to TRK1, TRK2, Falling

(Note 28)

tdfsh1

66tclk

-

68tclk+260

ns

HOLD to TRK1, TRK2, SSH Rising

(Note 28)

tdrsh

-

120

-

ns

HOLD Pulse Width

(Note 29)

thold

1tclk+20

-

63tclk

ns

HOLD to CH1/2 Edge

(Note 28)

tdhlri

15

-

64tclk

ns

HOLD Falling to ClKIN Falling

(Note 29)

thcf

55

-

1tclk+ 10

ns

RST Rising to STBY Rising

Note:

teal

60

ns

24. Minimum ClKIN period is 0.625 /-!s in FRN mode (20 kHz sample rate). At temperatures >+85 °C,
and with clock frequencies <1.6 MHz, analog performance may be degraded.
25. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency
is 1.6 MHz in FRN mode (20 kHz sample rate).
26. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 MQ parallel resistor (see Figure 8).
27. These times are for FRN mode.
28. SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge
occurs after HOLD rises to 64 tclk after HOLD has fallen. These times are for PDT and RBT modes.
29. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must
be latched by a falling edge of ClKIN. Conversion will begin on the next rising edge of ClKIN
after HOLD is latched. If HOLD is operated synchronous to ClKIN, the HOLD pulse width may be as
narrow as 150 ns for all ClKIN frequencies if ClKIN falls 55 ns after HOLD falls. This
ensures that the HOLD pulse will meet the minimum specification for thcf.

DS45F2

2-119

-

_..............
..__ .....
.-.
...,..,-

CS5101A CS5102A

STBY

Reset and Calibration Timing

CH1/2

==x~----------~x==

SSH/SDl~

1

____' _ -J

HOLD \'-----_ _- - ' /

-I

lC:tdrsh1

TRK1 ,TRK2 -+J~
T-R-K-1 ,T-R-K-2

lttdfSh2

1

--r:4-----~t
tdfsh4

__ __ -.I

------

'ctdrsh

SSH,TRK1 ,TRK2~
TRK1,TRK2

~4------.l~

:

tdfsh1

IL

h. PDT, RBT Mode

a. FRNMode

Control Output Timing

- - - -1- -.1.---CH1/2

~I1______ _
::::;j

HOLD

~tdhlri

L." - .,I

I
ClKIN
HOLD

I

-------r\=\:\1-'-----_

thold

Channel Selection Timing

2·120

Start Conversion Timing

DS45F2

-. ....,--.. ....-.-.
~-

..,~-

CS5t01A CS5102A

~..,

SWITCHING CHARACTERISTICS (Continued)
Parameter

Symbol

Min

Typ

Max

Units

SCLK Input Pulse Period

tsclk

200

SCLK Input Pulse Width Low

tsclkl

50

tsclkh

50

-

ns

SCLK Input Pulse Width High

-

tdss

-

100

150

ns

140

230

ns

65

125

ns

2tclk
2tclk

PDT and RBT Modes

SCLK Input Falling to SDATA Valid
HOLD Falling to SDATA Valid
TRK1, TRK2 Falling to SDATA Valid

FRN and

PDT Mode

tdhs

(Note 30)

tdts

ns
ns

sse Modes

-

tslkh

-

SDATA Valid Before Rising SCLK

tss

2tclk-100

-

SDATA Valid After Rising SCLK

tsh

2tclk-100

-

-

2tclk

-

ns

-

2tclk
2tclk

2tclk+165
2tclk+200

ns
ns

SCLK Output Pulse Width Low

tslkl

SCLK Output Pulse Width High

SDL Falling to 1st Rising SCLK

trsclk

-

tclk
tclk

-

ns

-

ns

Last Rising SCLK to SDL Rising

CS5101A
CS5102A

trsdl
trsdl

HOLD Falling to 1st Falling SCLK

CS5101A
CS5102A

this
this

6tclk
6tclk

-

Stclk+165
Stclk+200

ns
ns

tchfs

-

7tclk

-

tclk

CH1/2 Edge to 1st Falling SCLK
Note:

30. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then
SDATA is valid tdss time after the next falling SCLK.

DIGITAL CHARACTERISTICS (TA= Tmin to Tmax;

VA+, VD+ = 5V± 10%; VA-,

VD- = -5V ± 10%)

Parameter
Calibration Memory Retention
Power Supply Voltage VA+ and VD+

(Note 31)

High-Level Input Voltage

Symbol

Min

Typ

Max

Units

VMR

2.0

-

-

V

VIH

2.0

-

-

V

-

O.S

V

-

V

0.4

V
IlA
pF

VIL

-

High-Level Output Voltage

(Note 32)

VOH

(VD+)-1.0

Low-Level Output Voltage

lOUT = 1.6 mA

VOL

-

lin

-

-

10

Cout

-

9

-

Low-Level Input Voltage

Input Leakage Current
Digital Output Pin Capacitance

Notes: 31. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be
allowed to go positive. AIN1, AIN2 or VREF must not be greater than VA+ or VD+.
This parameter is guaranteed by characterization.
32. lOUT = -100!lA. This specification guarantees TTL compatibility (VOH = 2.4V @ lout = -40 !lA).

DS45F2

2-121

_.-..........___-.........-.

CS5101A CS5102A

HOLD~
I~

/

IS~----------~
CH1/2----y - - -1- - - - - - - - - - - - - - - - - - - - - - - -

-

-

-

"'

ISI-----------

1

I~II
---J

SSH/SDL

Irsc;!!s.J\ '-------~----------\
Isclkl Isclkh
I~

SCLK

SDATA

~I~

~I

~ . .-.-nlsClk

1

Id~~

=1:__

U

~ldSS

IJSlkl
SCLK------------.I

~dl

VI .

I
~IShT>____y

1

Iss ~

SDATA _ _ _ _-----'X

a. SCLK input (RBT and PDT mode)

MSB

~~

LSB

b. SCLK output (SSC and FRN modes)

Serial Data Timing

HOLD

~

TRK1'TRK2~

IdhsL--~~

SDATA

SCLK

X· MSB

SDATA

~

-----'I

\L__________

MSB

I!/~L- MSB-1

_ _ _ __

SCLK

a. Pipelined Data Transmission (PDT)

b. Register Burst Transmission (RBT) Mode

Data Transmission Timing

2-122

DS45F2

._.-.
_.-_.....,-__.._-_
...

CS5101A CS5102A

RECOMMENDED OPERATING CONDITIONS
Parameter
DC Power Supplies:

Positive Digital
Negative Digital
Positive Analog
Negative Analog

Analog Reference Voltage
Analog Input Voltage:

(AGND, DGND = OV, see Note 33)

Symbol

Min

Typ

Max

Units

VD+
VDVA+
VA-

4.5
-4.5
4.5
-4.5

5.0
-5.0
5.0
-5.0

VA+
-5.5
5.5
-5.5

V
V
V
V

VREF

2.5

4.5

(VA+)-0.5

V

VAIN
VAIN

AGND
-VREF

-

-

VREF
VREF

V
V

(Note 34)
Unipolar
Bipolar

Notes: 33. All voltages with respect to ground.
34. The CS5101A and CS5102A can accept input voltages up to the analog supplies (VA+ and VA-). They
will produce an output of all 1's for inputs above VREF and all O's for inputs below AGND in unipolar
mode and -VREF in bipolar mode, with binary coding (CODE = low).

ABSOLUTE MAXIMUM RATINGS*

(AGND, DGND = OV, all voltages with respect to ground)

Parameter

Symbol

Min

Typ

Max

Units

VD+
VDVA+
VA-

-0.3
0.3
-0.3
0.3

6.0
-6.0
6.0
-6.0

V
V
V
V

lin

-

-

±10

mA

VINA

(VA-)-0.3

-

(VA+)+0.3

V

VIND

-0.3

V

Ambient Operating Temperature

TA

-55

125

°C

Storage Temperature

Tstg

-65

150

°C

Ambient Operating Temperature

TA

-55

-

(VA+)+0.3

125

°C

Storage Temperature

Tstg

-65

-

150

°C

DC Power Supplies:

Positive Digital
Negative Digital
Positive Analog
Negative Analog

Input Current, Any Pin Except Supplies
Analog Input Voltage

(AIN and VREF pins)

Digital Input Voltage

(Note 35)

(Note 36)

Notes: 35. In addition, VD+ must not be greater than (VA+) +0.3V
36. Transient currents of up to 100 mA will not cause SCR latch-up.
·WARNING: Operation beyond these limits may result in permanent damage to the device.

DS45F2

2-123

•

..................
..,-- ._..............

CS5101A CS5102A

GENERAL DESCRIPTION
The CS5101A and CS5102A are 2-channel, 16bit AID converters. The devices include an
inherent sample/hold and an on-chip analog
switch for 2-channel operation. Both channels
can thus be sampled and converted at rates up to
50 kHz each (CS5101A) or 10 kHz each
(CS5102A). Alternatively, each of the devices can
be operated as a single channel ADC operating at
100 kHz (CS5101A) or 20 kHz (CS5102A).
Both the CS5101A and CS5102A can be configured to accept either unipolar or bipolar input
ranges, and data is output serially in either binary
or 2's complement coding. The devices can be
configured in 3 different output modes, as well as
an internal, synchronous loopback mode. The
CS510 1A and CS5102A provide coarse
charge/fine charge control, to allow accurate
tracking of high-slew signals.

THEORY OF OPERATION
The CS5101A and CS5102A implement the successive approximation algorithm using a charge
redistribution architecture. Instead of the traditional resistor network, the DAC is an array of
binary-weighted capacitors. All capacitors in the
array share a common node at the comparator's

input. As shown in Figure 1; their other terminals
are capable of being connected to AGND, VREF,
or AIN (1 or 2). When the device is not calibrating or converting, all capacitors are tied to AIN.
Switch S 1 is closed and the charge on the array,
tracks the input signal.
When the conversion command is issued, switch
S 1 opens. This traps the charge on the comparator side of the capacitor array and creates a
floating node at the comparator's input. The conversion algorithm operates on this fixed charge,
and the signal at the analog input pin is ignored.
In effect, the entire DAC capacitor array serves as
analog memory during conversion much like a
hold capacitor in a sample/hold amplifier.
The conversion consists of manipulating the free
plates of the capacitor array to VREF and AGND
to form a capacitive divider. Since the charge at
the floating node remains fixed, the voltage at
that point depends on the proportion of capacitance tied to VREF versus AGND. The
successive-approximation algorithm is used to
find the proportion of capacitance, which when
connected to the reference will drive the voltage
at the floating node to zero. That binary fraction
of capacitance represents the converter's digital
output.

AIN~ine

~o-ars-e~~~$=~~V~S~S=!~tEI==~6~61
VREF~ine

~

Coarse

AGND~ine

~oarse

cl
Bil15
MSB

c/21 c/41 • C.,f3~,7681
Bil14

Ctot

C/32,768i

S1

Bil13

=C + C/2 + C/4 + C/8 + ...

C/32,768

Figure 1. Coarse Charge Input Buffers and Charge Redistribution DAC
2-124

DS45F2

---------------------Calibration
The ability of the CS5101A or the CS5102A to
convert accurately to 16-bits clearly depends on
the accuracy of its comparator and DAC. Each
device utilizes an "auto-zeroing" scheme to null
errors introduced by the comparator. All offsets
are stored on the capacitor array while in the
track mode and are effectively subtracted from
the input signal when a conversion is initiated.
Auto-zeroing enhances power supply rejection at
frequencies well below the conversion rate.
To achieve 16-bit accuracy from the DAC, the
CS5101A and CS5102A use a novel self-calibration scheme. Each bit capacitor shown in
Figure 1 actually consists of several capacitors in
parallel which can be manipulated to adjust the
overall bit weight. An on-chip micro controller
precisely adjusts each capacitor with a resolution
of 18 bits.
The CS5101A and CS5102A should be reset
upon power-up, thus initiating a calibration cycle.
The device then stores its calibration coefficients
in on-chip SRAM. When the CS5101A and
CS5102A are in power-down mode (SLEEP
low), they retain the calibration coefficients in
memory, and need not be recalibrated when normal operation is resumed.

CS5101A CS5102A
the track mode. After allowing a short time for
acquisition, the device will be ready for another
conversion.
In contrast to systems with separate track-andholds and AID converters, a sampling clock can
simply be connected to the HOLD input. The
duty cycle of this clock is not critical. The HOLD
input is latched internally by the master clock, so
it need only remain low for 1Ifclk + 20 ns, but no
longer than the minimum conversion time minus
two master clocks or an additional conversion cycle will be initiated with inadequate time for
acquisition. In Free Run mode, SCKMOD =
OUTMOD = 0, the device will convert at a rate
of CLKIN/80, and the HOLD input is ignored.
As with any high-resolution A-to-D system, it is
recommended that sampling is synchronized to
the master system clock in order to minimize the
effects of clock feedthrough. However, the
CS5101A and CS5102A may be operated entirely asynchronous to the master clock if
necessary.

Tracking the Input

Initiating Conversions

Upon completing a conversion cycle the
CS5101A and CS5102A immediately return to
the track mode. The CH1/2 pin directly controls
the input switch, and therefore directly determines which channel will be tracked. Ideally, the
CH 112 pin should be switched during the conversion cycle, thereby nullifying the input mux
switching time, and guaranteeing a stable input ~
the start of acquisition. If, however, the CH1I2
control is changed during the acquisition phase,
adequate coarse charge and fine charge time must
be allowed before initiating conversion.

A falling transition on the HOLD pin places the
input in the hold mode and initiates a conversion
cycle. The charge is trapped on the capacitor array the instant HOLD goes low. The device will
complete conversion of the sample within 66
master clock cycles, then automatically return to

When the CS5101A or the CS5102A enters
tracking mode, it uses an internal input buffer
amplifier to provide the bulk of the charge on the
capacitor array (coarse-charge), thereby reducing
the current load on the external analog circuitry.
Coarse-charge is internally initiated for 6 clock

OPERATION OVERVIEW
Monolithic design and inherent sampling architecture make the CS5101A and CS5102A
extremely easy to use.

DS45F2

2-125

--------.,-- ----------cycles at the end of every conversion. The buffer
amplifier is then bypassed, and the capacitor array is directly connected to the input. This is
referred to as fine-charge, during which the
charge on the array is allowed to accurately settle
to the input voltage (see Figure 10).
With a full scale input step, the coarse-charge input buffer of the CS5101A will charge the
capacitor array within 1% in 650 ns. The converter timing allows 6 clock cycles for coarse
charge settling time. When the CS5101A
switches to fine-charge mode, its slew rate is
somewhat reduced. In fine-charge, the CS5101A
can slew at 2 V/lls in unipolar mode. In bipolar
mode, only half the capacitor array is connected
to the analog input, so the CS5101A can slew at
4V/lls.
With a full scale input step, the coarse-charge input buffer of the CS5102A will charge the
capacitor array within 1% in 3.75 Ils. The converter timing allows 6 clock cycles for coarse
charge settling time. When in fine-charge mode,
the CS5102A can slew at 0.4 V/lls in unipolar
mode; and at 0.8 V/lls in bipolar mode.
Acquisition of fast slewing signals can be hastened if the voltage change occurs during or
immediately following the conversion cycle. For
instance, in multiple channel applications (using
either the device's internal channel selector or an
external MUX), channel selection should occur
while the CS5101A or the CS5102A is converting. Multiplexer switching and settling time is
thereby removed from the overall throughput
equation.
If the input signal changes drastically during the
acquisition period (such as changing the signal
source), the device should be in coarse-charge for
an adequate period following the change. The
CS5101A and CS5102A can be forced into
coarse-charge by bringing CRSIFIN high. The
buffer amplifier is engaged when CRSIFIN is
2-126

CS5101A CS5102A
high, and may be switched in any number of
times during tracking. If CRSIFIN is held low,
the CS5101A and CS5102A will only coarsecharge for the first 6 clock cycles following a
conversion, and will stay in fine-charge until
HOLD goes low. To get an accurate sample using
the CS5101A, at least 750 ns of coarse-charge,
followed by 1.125 Ils of fine-charge is required
before initiating a conversion. If coarse charge is
not invoked, then up to 25 Ils should be allowed
after a step change input for· proper acquisition.
To get an accurate sample using the CS5102A, at
least 3.75 Ils of coarse-charge, followed by
5.625 Ils of fine-charge is required before initiating a conversion (see Figure 2). If coarse charge
is not invoked, then up to 125 Ils should be allowed after a step change input for proper
acquisition. The CRSIFIN pin must be low prior
to HOLD becoming active and be held low during conversion.
Master Clock

The CS510IA and CS5102A can operate either
from an externally-supplied master clock, or from
their own crystal oscillator (with a crystal). To
enable the internal crystal oscillator, simply tie a
crystal across the XOUT and CLKIN pins and
add 2 capacitors and a resistor, as shown on the
system connection diagram in Figure 8.
Calibration and conversion times directly scale to
the master clock frequency. The CS5101A-8 can
operate with clock or crystal frequencies up to
9.216 MHz (8.0 MHz in FRN mode). This allows
maximum throughput of up to 50 kHz per channel in dual-channel operation, or 100 kHz in a
single channel configuration. The CS51OIA-16
can accept a maximum clock speed of 4 MHz,
with corresponding throughput of 50 kHz. The
CS5102A can operate with clock or crystal frequencies up to 2.0 MHz (1.6 MHz in FRN mode). This
allows maximum throughput of up to 10 kHz per
channel in dual-channel operation, or 20 kHz in a
single channel configuration. For 16 bit performance
DS45F2

_-.
---_...
._.
_..............
.....

CS5101A CS5102A

CLKIN
Min: 750 ns*

0- - - . j
11+

3. 75 1J.S**1

CRS/FIN

1
114-0- -__I 6 elk

Min:1.1251J.S*1
0- - - - . . . ,
5.625 IJ.s** 14-1

Internal
Status

Fine Chg.
~2elk

TRK1 or ------'----i
l~.__________________________~
TRK2

HOLD
* Applies to 5101A
** Applies to 5102A

Figure 2. Coarse-Charge/Fine-Charge Control

a 1.6 MHz clock is recommended. This 1.6 MHz
clock yields a maximum throughput of 20 kHz in
a single channel configuration.

Asynchronous Sampling Considerations
When HOLD goes low, the analog sample is captured immediately. The HOLD signal is latched
by the next falling edge of CLKIN, and conversion then starts on the subsequent rising edge. If
HOLD is asynchronous to CLKIN, then there
will be a 1.5 CLKIN cycle uncertainty as to when
conversion starts. Considering the CS5101A with an
8 MHz CLKIN, with a 100 kHz HOLD signal, then
this 1.5 CLKIN uncertainty will result in a 1.5
CLKIN period possible reduction in fine charge time
for the next conversion.
Unipolar Input Offset
TWo's
Binary Complement
Voltage
>(VREF-1.5 LSBI FFFF

Bipolar Input
Voltage

7FFF

>(VREF-1.5 LSB)

VREF-1.5 LSB

FFFF
FFFE

7FFF
7FFE

VREF-1.5 LSB

VREF/2-0.5 LSB

8000
7FFF

0000
FFFF

-0.5 LSB

+0.5 LSB

0001
0000

8001
8000

-VREF+0.5 LSB

«+0.5 LSB)

0000

8000

«-VREF+0.5 LSB)

Table 1. Output Coding
DS45F2

This reduced fine charge time will be less than
the minimum specification. If the CLKIN frequency is increased slightly (for example, to
8.192 MHz) then sufficient fine charge time will
always occur. The maximum frequency for
CLKIN is specified at 9.216 MHz; it is recommended that for asynchronous operation at
100 kHz, CLKIN should be between 8.192 MHz
and 9.216 MHz.

Analog Input Range/Coding Format
The reference voltage directly defines the input
voltage range in both the unipolar and bipolar
configurations. In the unipolar configuration
(BPIUP low), the first code transition occurs 0.5
LSB above AGND, and the final code transition
occurs 1.5 LSB's below VREF. In the bipolar
configuration (BP/uP high), the first code transition occurs 0.5 LSB above -VREF and the last
transition occurs 1.5 LSB's below +VREF.
The CS5101A and CS5102A can output data in
either 2's complement, or binary format. If the
CODE pin is high, the output is in 2's complement format with a range of -32,768 to +32,767.
If the CODE pin is low, the output is in binary
format with a range of 0 to +65,535. See Table 1
for output coding.
2-127

_.-........
__.......-__.-.
..,

CS510tA CS5102A

MODE
PDT
RBT

SCKMOD

OUTMOD

SCLK

CH1t2

HOLD

1

1

Input

Input

Input

1

0

Input

Input

Input

sse

0

1

Output

Input

Input

FRN

0

0

Output

Output

X

Table 2. Serial Output Modes

Output Mode Control

The CS5101A and CS5102A can be configured
in three different output modes, as well as an internal, synchronous loop-back mode. This allows
great flexibility for design into a wide variety of
systems. The operating mode is selected by setting the states of the SCKMOD and OUTMOD
pins. In all modes, data is output on SDATA,
starting with the MSB. Each subsequent data bit
is updated on the falling edge of SCLK.
When SCKMOD is high, SCLK is an input, allowing the data to be clocked out with an
external serial clock at rates up to 5 MHz. Additional clock edges after #16 will clock out logic
'1 's on SDATA. Tying SCKMOD low reconfigures SCLK as an output, and the converter clocks

out each bit as it's determined during the conversion process, at a rate of 1/4 the master clock
speed. Table 2 shows an overview of the different
states of SCKMOD and OUTMOD, and the corresponding output modes.
Pipelined Data Transmission (PDT)

PDT mode is selected by tying both SCKMOD
and OUTMOD high. In PDT mode, the SCLK
pin is an input. Data is registered during conversion, and output during the following conversion
cycle. HOLD must be brought low, initiating another conversion, before data from the previous
conversion is available on SDATA. If all the data
has not been clocked out before the next falling
edge of HOLD, the old data will be lost
(Figure 3).

ClKIN(i)
HOLD (i)
CH1i2(i)
Internal
Status
SClK(i)

Converting Ch. 2

Converting Ch. 1

Tracking Ch. 2

1ILflJu
~~LJ
~LI
~r-DO-(C-h-.1-)-------:~--0-O(-C-h.-2)------:~015

SOATA(O)] 015
SSH/SOl

Tracking Ch. 1

(OU

TRK1(o)

-TRK2(o) J

X 014

~

~
~~

~l

~
~~

~

~
~~

~~

~-·~I
~

Figure 3. Pipelined Data Transmission Mode (PDT)
2-128

DS45F2

___-

.-........-- ..........
....

CS5101A CS5102A

o
4
// 64
68
"0'"

ClKIN(i)
HOLD (i)

Status
SClK(i)

/'/

0

4

,,64

68

72

,/

0

"a:;'"
0
'
_~~1IlJUUUUlJUUUU~
1
~
lid]))
~~
~

q]))

1

~

m

CH1/2 (i)

Internal

72

~

\\\~]\

~___

-'-1..L_

Converting Ch. 1

Tracking Ch. 2

=~==~~~=;--;::;--;:::;-~~:::;-;?fr::;-;:::;-;~-;::===~==:::;-;:::;-;~:;-;::;-;:;~~~-;:::;-~;::==
o
a:;

rumruuu~~

~---~

SDATA (0) - ; = = = =
SSH/SDl (0) J

:--------

TRK1 (0)

-----,

X:S~~~a~

~

~

I

~

~

I

------~~

a:;

TRK2 (0) J

~~--~

Figure 4. Registered Burst Transmission Mode (RBT)

Internal
Status
SClK(o)

Converting Ch. 2

Tracking Ch. 1

====~-;:=::;-~~~~--;:::====~====;-~=:;~~~~;--;:::::Tr=ac=k=in=g=Ch=.=2~~==
~n&

LJ~

LJ

\~~

~

~~

-------,1

~

0~--~

SDATA(O) _ _ _ _~ DO (Ch.2)
SSHlSDl (0)

~

0

..

~~~~-~a:;

a:;-E~
~

~~--~

~~

1

~J

TRK1(0)

o

~

TRK2(o)J

---~-----.-;~

~ ~

0------:

~

~

Figure 5. Synchronous Self-Clocking Mode (SSC)

oI
ClKIN (i)
CH1/2(0)

4
I

78
I

I

~

64

6869

I

I

I

72
I

76
I

0
I

4
I

78
I

I

nJlJUUlJUlfUUUUUlf
J
~

I~~:u~

'J

~

64
I

6869
I

I

72
I

76
I

Tracking Ch. 1

Converting Ch. 1

I

~JUlJ1flJUUUUUU1UUU1JlfUUUlJl

~

Converting Ch. 2

0

I
Tracking Ch. 2

SClK(O)~~~
SDATA(o)
~~ DO (Ch. 2)
~-=D~O-,-,(C:.:.:h,,--.1,-,-)_ _ _ __
I·

SSH/SDl(o)
TRK1 (0)

TRK2 (0)

J.

~
~~

~

~--~~
1
~====::..-----~~
I
1

Figure 6. Free Run Mode (FRN)
DS45F2

2-129

. ..,..... _.

..,. . . .* - . . , _•
,..,• •* - * - • • •,..,

Registered Burst Transmission (RET)

RBT mode is selected by tying SCKMOD high,
and OUTMOD low. As in PDT mode, SCLK is
an input, however data is available immediately
following conversion, and may be clocked out the
moment TRKI or TRK2 falls. The falling edge of
HOW clears the output buffer, so any unread
data will be lost. A new conversion may be initiated before all the data has been clocked out if
the unread data bits are not important (Figure 4).

CS5101A CS5102A
cycles after the last rising edge of SCLK. This
signal frames the 16 data bits and is useful for
interfacing to shift registers (e.g. 74HC595) or to
DSP serial ports.

SYSTEM DESIGN WITH THE CS5101A
AND CS5102A
Figure 7 shows a general system connection diagram for the CS5101A and CS5102A.

Synchronous Self-Clocking (SSC)

Digital Circuit Connections

SSC mode is selected by tying SCKMOD low,
and OUTMOD high. In SSC mode, SCLK is an
output, and will clock out each bit of the data as
it's being converted. SCLK will remain high between conversions, and run at a rate of 1/4 the
master clock speed for 16 low pulses during conversion (Figure 5).

When TTL loads are utilized the potential for
crosstalk between digital and analog sections of
the system is increased. This crosstalk is due to
high digital supply and signal currents arising
from the TTL drive current required of each digital output. Connecting CMOS logic to the digital
outputs is recommended. Suitable logic families
include 4000B, 74HC, 74AC, 74ACT: and
74HCT.

The SSHlSDL goes low coincident with the first
falling edge of SCLK, and returns high 2 CLKIN
cycles after the last rising edge of SCLK. This
signal frames the 16 data bits and is useful for
interfacing to shift registers (e.g. 74HC595) or to
DSP serial ports.
Free Run (FRN)

Free Run is the internal, synchronous loopback
mode. FRN mode is selected by tying SCKMOD
and OUTMOD low. SCLK is an output, and operates exactly the same as in the SSC mode. In
Free Run mode, the converter initiates a new conversion every 80 master clock cycles, and
alternates between channel 1 and channel 2.
HOLD is disabled, and should be tied to either
VD+ or DGND. CHlt2 is an output, and will
change at the start of each new conversion cycle,
indicating which channel will be tracked after the
current conversion is finished (Figure 6).
The SSHlSDL goes low coincident with the first
falling edge of SCLK, and returns high 2 CLKIN
2-130

System Initialization

Upon power up, the CS5101A and CS5102A
must be reset to guarantee a consistent starting
condition and initially calibrate the device. Due
to each device's low power dissipation and low
temperature drift, no warm-up time is required
before reset to accommodate any self-heating effects. However, the .voltage reference input
should have stabilized to within 0.25% of its final
value before RST rises to guarantee an accurate
calibration. Later, the CS5101A and CS5102A
may be reset at any time to initiate a single full
calibration.
When RST is brought low all internal logic
clears. When RST returns high on the CS5101A,
a calibration cycle begins which takes 11,528,160
master clock cycles to complete (approximately
1.4 seconds with an 8 MHz master clock). The
calibration cycle on the CS5102A takes
2,882,040 master clock cycles to complete (apDS45F2

.. ...
._.-.
-. ..--~-

~~-

CS5101A CS5102A

~~

10
+5VA ~'------1>---'--'WVv-.-.--.-------,

25

26

-

7

TST VD+

VA+

XOUT f---'-4---<~~---,
VD+
18 OUTMOD
SCKMOD
Mode Control
BP/UP
CODE
CS5101A
OR

VREF

XTAL & C1 Table

Logic

CS5102A
CS5101A

Voltage Reference

FRN

AGND

XTAL

C1, C2

8.0 MHz

10 pF

PDT, RBT,
8.192 MHz
SSC
50
1 nF

Analog
Sources

19

7

• For best dynamic

S/(N+D) performance.

7

SSH/SDL

NPO

L _ _ _J--v5W°I{'--'±-:-:::~241
1 nF

AIN1

CS5102A
FRN

1.6MHz

30 pF

PDT, RBT,
SSC

1.6MHz
or
2.0 MHz

30 pF

AIN2

NPO

21

REFBUF
VA·

VD·

23
·5VA

10 pF

10

Unused Logic inputs should
be tied to VD+ or DGND.

Figure 7. CS5101AlCS510ZA System Connection Diagram

proximately 1.8 seconds with a 1.6 MHz master
clock). The CS5101A's and CS5102A's STBY
output remains low throughout the calibration sequence, and a rising transition indicates the
device is ready for normal operation. While calibrating, the CS510lA and CS5102A will ignore
changes on the HOLD input.
To perform the reset function, a simple power-on
reset circuit can be built using a resistor and capacitor as shown in Figure 8. The resistor should
be less than or equal to 10 ill. The system power
DS45F2

supplies, voltage reference, and clock should all
be established prior RST rising.
Single-Channel Operation

The CS510lA and CS5102A can alternatively b~
used to sample one channel by tying the CH1I2
input high or low. The unused AIN pin should be
tied to the analog input signal or to AGND. (If
operating in free run mode, AINI and AIN2 must
be tied to the same source, as CHIli: is reconfigured as an output.)
2-131

_.-_..--_
__..-_.....-..

CS51 01 A CS5102A

CS5101A
+5V

---.-~~~~~-

VD+

CS5102A

R
L-~~~~__

OR

RST

Figure 8. Power-up Reset Circuit

ANALOG CIRCUIT CONNECTIONS
Most popular successive approximation NO converters generate dynamic loads at their analog
connections. The CS5101A and CS5102A internally buffer all analog inputs (AIN1, AIN2,
VREF, and AGND) to ease the demands placed
on external circuitry. However, accurate system
operation still requires careful attention to details
at the design stage regarding source impedances
as well as grounding and decoupling schemes.
Reference Considerations

An application note titled "Voltage References for
the CS50lX Series of AID Converters" is available for the CS5101A and CS5102A. In addition to
working through a reference circuit design example,
it offers several built-and-tested reference circuits.
During conversion, each capacitor of the calibrated capacitor array is switched between VREF
and AGND in a manner determined by the successive-approximation algorithm. The charging
and discharging of the array results in a current
load at the reference. The CS 51 0 1A and
CS5102A each include an internal buffer amplifier to minimize the external reference circuit's
drive requirement and preserve the reference's integrity. Whenever the array is switched during
conversion, the buffer is used to coarse-charge the
array thereby providing the bulk of the necessary
charge. The appropriate array capacitors are then
2-132

switched to the unbuffered VREF pin to avoid
any errors due to offsets and/or noise in the buffer.
The external reference circuitry need only provide the residual charge required to fully charge
the array after coarse-charging from the buffer.
This creates an ac current load as the CS5101A
and CS5102A sequence through conversions. The
reference circuitry must have a low enough output impedance to drive the requisite current
without changing its output voltage significantly.
As the analog input signal varies, the switching
sequence of the internal capacitor array changes.
The current load on the external reference circuitry thus varies in response with the analog
input. Therefore, the external reference must not
exhibit significant peaking in its output impedance characteristic at signal frequencies or their
harmonics.
A large capacitor connected between VREF and
A<3ND can provide sufficiently low output impedance at the high end of the frequency
spectrum, while almost all precision references
exhibit extremely low output impedance at dc.
The presence of large capacitors on the output of
some voltage references, however, may cause
peaking in the output impedance at intermediate
frequencies. Care should be exercised to ensure
that significant peaking does not exist or that
some form of compensation is provided to eliminate the effect.
The magnitude of the current load on the external
reference circuitry will scale to the master clock
frequency. At the full-rated 9.216 MHz clock
(CS5101A), the reference must supply a maximum load current of 20!lA peak-to-peak (21lA
typical). An output impedance of 2 Q will therefore yield a maximum error of 40 1lY. At the
full-rated 2.0 MHz clock (CS5102A), the reference must supply a maximum load current of
5 !lA peak-to-peak (0.5 !lA typical). An output
impedance of 2 Q will therefore yield a maxiDS45F2

_-.
...........
---_...
._.
_
....

CS5101A CS5102A

...ill
1/1

::::!.

g

w

.~

+200

-

+100
0
·100

.c

U

23 VA.

CS5101A

ii

·200

OR

!

-300

CS5102A
·5V

E

4ooL-~--------~------~--------~

8 MHz Clock 0.25
2.0 MHz Clock 1.0

R

0.5
2.0

0.75
3.0

1.0
4.0

Acquisition Time (us)

Figure 9. Reference Connections

Figure 10. Charge Settling Time
(8 and 2.0 MHz Clocks)

mum error of 10.0 1lV. With a 4.5 V reference and
LSB size of 138 IlV this would insure approximately 1114 LSB accuracy. A 1O!1F capacitor
exhibits an impedance of less than 2 Q at frequencies greater than 16 kHz. A high-quality
tantalum capacitor in parallel with a smaller ceramic capacitor is recommended.

recommended. This allows 0.5V headroom for
the internal reference buffer. Also, the buffer enlists the aid of an external 0.1 !1F ceramic
capacitor which must be tied between its output,
REFBUF, and the negative analog supply, VA-.
For more information on references, consult "Application Note: Voltage References for the
CS501X Series of AID Converters".

Peaking in the reference's output impedance can
occur because of capacitive loading at its output.
Any peaking that might occur can be reduced by
placing a small resistor in series with the capacitors. The equation in Figure 9 can be used to help
calculate the optimum value of R for a particular
reference. The term "fpeak" is the frequency of
the peak in the output impedance of the reference
before the resistor is added.
The CS5101A and CS5102A can operate with a
wide range of reference voltages, but signal-tonoise performance is maximized by using as
wide a signal range as possible. The recommended reference voltage is 4.5 volts. The
CS5101A and CS5102A can actually accept reference voltages up to the positive analog supply.
However, the buffer's offset may increase as the
reference voltage approaches VA+ thereby increasing external drive requirements at VREF. A
4.5V reference is the maximum reference voltage
DS45F2

Analog Input Connection
The analog input terminal functions similarly to
the VREF input after each conversion when
switching into the track mode. During the first
six master clock cycles in the track mode, the
buffered version of the analog input is used for
coarse-charging the capacitor array. An additional
period is required for fine-charging directly from
AIN to obtain the specified accuracy. Figure 10
shows this operation. During coarse-charge the
charge on the capacitor array first settles to the
buffered version of the analog input. This voltage
may be offset from the actual input voltage. During fine-charge, the charge then settles to the
accurate unbuffered version.
Fine-charge settling is specified as a maximum of
1.125 IlS (CS5101A) or 5.625 IlS (CS5102A) for
an analog source impedance of less than 50 Q. In
2·133

-. ....,--.. ...._....~-

~~

~-

addition, the comparator requires a source impedance of less than 400 n around 2 MHz for
stability. The source impedance can be effectively
reduced at high frequencies by adding capacitance from AIN to ground (typically 200 pF).
However, high dc source resistances will increase
the input's RC time constant and extend the necessary acquisition time. For more information on
input amplifiers, consult the application note:
Buffer Amplifiers for the CS50lX Series of AID
Converters.
SLEEP Mode Operation
The CSS101A and CSS102A include a SLEEP
pin. When SLEEP is active (low) each device
will dissipate very low power to retain its calibration memory when the device is not sampling. It
does not require calibration after SLEEP is made
inactive (high). When coming out of SLEEP,
sampling can begin as soon as the oscillator starts
(time will depend on the particular oscillator
components) and the REFBUF capacitor is
charged (which takes about 3 ms for the
CSS101A, SO ms for the CSS102A). To achieve
minimum start-up time, use,an external clock and
leave the voltage reference powered-up. Connect
a resistor (2 kn) between pins 20 and 21 to keep
the REFBUF capacitor charged. Conversion can
then begin as soon as the NO circuitry has stabilized and performed a track cycle.
To retain calibration memory while SLEEP is active (low) VA+ and VD+ must be maintained at
greater than 2.0V. VA- and VD- can be allowed to
go to 0 volts. The voltages into VA- and VDcannot just be "shut-off' as these pins cannot be
allowed to float to potentials greater than
AGNDIDGND. If the supply voltages to VA- and
VD- are removed, use a transistor switch to short
these to the power supply ground while in
SLEEP mode.

2-134

CS5101A CS5102A
Grounding and Power Supply Decoupling
The CSSI0lA and CSSl02A use the analog
ground connection, AGND, only as a reference
voltage. No dc power currents flow through the
AGND connection, and it is completely independent of DGND. However, any noise riding on
the AGND input relative to the system's analog
ground will induce conversion errors. Therefore,
both the analog input and reference voltage
should be referred to the AGND pin, which
should be used as the entire system's analog
ground reference.
The digital and analog supplies are isolated
within the CSSlOlA and CSS102A and are
pinned out separately to minimize coupling between the analog and digital sections of the chip.
All four supplies should be decoupled to their respective grounds using 0.1 !!F' ceramic capacitors.
If significant low-frequency noise is present on
the supplies, tantalum capacitors are recommended in parallel with the 0.1 !!F' capacitors.
The positive digital power supply of the
CSS10lA and CSS102A must never exceed the
positive analog supply by more than a diode drop
or the CSS10lA and CSS102A could experience
permanent damage. If the two supplies are derived from separate sources, care must be taken
that the analog supply comes up first at powerup. The system connection diagram (Figure 7)
shows a decoupling scheme which allows the
CSS10lA and CSS102A to be powered from a
single set of ± SV rails. The positive digital supply is derived from the analog supply through a
IOn resistor to avoid the analog supply dropping
below the digital supply. If this scheme is utilized, care must be taken to insure that any digital
load currents (which flow through the 10 n resistors) do not cause the magnitude of digital
supplies to drop below the analog supplies by
more than O.S volts. Digital supplies must always
remain above the minimum specification.

DS45F2

----------- ----------As with any high-precision AID converter, the
CS5101A and CS5102A require careful attention
to grounding and layout arrangements. However,
no unique layout issues must be addressed to
properly apply the devices. The CDB5101A
evaluation board is available for the CS5101A,
and the CDB5102A evaluation board is available
for the CS5102A. The availability of these boards
avoids the need to design, build, and debug a
high-precision PC board to initially characterize
the part. Each board comes with a socketed
CS5101A or CS5102A, and can be reconfigured
to simulate any combination of sampling, calibration, master clock, and analog input range
conditions.

CS5101A AND CS5102A PERFORMANCE
Differential Nonlinearity

The self-calibration scheme utilized in the
CS5101A and CS5102A features a calibration
resolution of 114 LSB, or 18-bits. This ideally
yields DNL of ±1I4 LSB, with code widths ranging from 3/4 to 5/4 LSB's.
Traditional laser trimmed ADC's have significant
differential nonlinearities. Appearing as wide and
narrow codes, DNL often causes entire sections
of the transfer function to be missing. Although
their affect is minor on S/(N+D) with high amplitude signals, DNL errors dominate performance
with low-level signals. For instance, a signal 80
dB below full-scale will slew past only 6 or 7
codes. Half of those codes could be missing with
a conventional 16-bit ADC which achieves only
14-bit DNL.
The most common source of DNL errors in conventional ADC's is bit weight errors. These can
arise due to accuracy limitations in factory trim
stations, thermal or physical stresses after calibration, and/or drifts due to aging or temperature
variations in the field. Bit-weight errors have a
drastic effect on a converter's ac performance.
DS45F2

CS5101A CS5102A
They can be analyzed as step functions superimposed on the input signal. Since bits (and their
errors) switch in and out throughout the transfer
curve, their effect is signal dependent. That is,
harmonic and intermodulation distortion, as well
as noise, can vary with different input conditions.
Differential nonlinearities in successive-approximation ADC's also arise due to dynamic errors in
the comparator. Such errors can dominate if the
converter's throughput/sampling rate is too high.
The comparator will not be allowed sufficient
time to settle during each bit decision in the successive-approximation algorithm. The worst-case
codes for dynamic errors are the major transitions
(1/2 FS; 1/4, 3/4 FS; etc.). Since DNL effects are
most critical with low-level signals, the codes
around mid-scale (112 FS) are most important.
Yet those codes are worst-case for dynamic DNL
errors!
With all linearity calibration performed on-chip
to 18-bits, the CS5101A and CS5102A maintain
accurate bit weights. DNL errors are dominated
by residual calibration errors of ±1I4 LSB rather
than dynamic errors in the comparator. Furthermore, all DNL effects on S/(N+D) are buried by
white broadband noise. (See Figures 17 and 19).
Figure 11 illustrates the DNL histogram plot of a
typical CS5101A at 25°C. Figure 12 illustrates
the DNL of the CS5101A at 138°C ambient after
calibration at 25°C ambient. Figures 13 and 14
illustrate the DNL of the CS5102A at 25°C and
138°C ambient, respectively. A histogram test is a
statistical method of deriving an AID converter's
differential nonlinearity. A ramp is input to the
AID and a large number of samples are taken to
insure a high confidence level in the test's result.
The number of occurrences for each code is
monitored and stored. A perfect AID converter
would have all codes of equal size and therefore
equal numbers of occurrences. In the histogram
test a code with the average number of occurrences will be considered ideal (DNL = 0). A
2-135

•

I

I

-

..
--~------ -----------

CS51 01 A CS5102A

+1

+112

iii'

~

...J

Z
C -112

-1

Figure 11. CS5101A DNL Plot; Ambient Temperature at 25°C
+1

+112

iii'

~

...J

Z

C -112
-1

32,768

Codes

Figure 12. CS5101A DNL Plot; Ambient Temperature at 138°C

+1

+112

iii'

~

o

...J

Z
C -112

-1

Figure 13. CS5102A DNL Plot; Ambient Temperature at 25°C
+1

+112

iii'

~

...J

Z

C -112
-1

Figure 14. CS5102A DNL Plot; Ambient Temperature at 138°C

2-136

DS45F2

.. ...
._.-.
-. ..,.,-~-

~~-

CS5101A CS5102A

~-

...J

C

.r::

aJ

w

28- - - - - - - - - - - - - - - - - - - - - - - - 25248

# of Missing Codes: 0

24- - - - - - - - - - - - - - - - - - - -

Total # of
Codes Analyzed: 65534

26- - - - - - - - - - - - - - - - - - - - - - - - -

Z

22- - - - - - - - - - - - - - - - - - - -

en

20- - - - - - - - - - - - -

gj

lJl

16 _________________ 1?5!0_

"C

:::l

.r::

.~ ~

8~
15 iii
.0
E
:::l
Z

18- - - - - - - - - - - - - - - - - - --

14- - - - - - - - - - - - - - - -12- - - - - - - - - - - - - - - -10- - - - - - - - - - - - - - - - 8- - - - - - - - - - - - - - - - -

6- - - - - - - - - - - - - -

175

41

5

2

-0.65 -0.55 -0.45 -0.35 -0.25 -0.15 -0.05 0 0.05 0.15 0.25 0.35 0.45 0.55 0.65

DNL Error in LSB

Figure 15. CS5101A DNL Error Distribution
~~--------------------------------------------.

31047

...J

Total # of
Codes Analyzed: 65534

aJ

25 - - - - - - - - - - - - - - - - - - -

w

=~
.§
~
gj

# of Missing Codes: 0

30 - - - - - - - - . -

Z
C
.r::

20 - . - - - - - - . - - - - - - - - - -

8 l15 ________________
U)

16047

'0

iii

.0

10 - - - - - - - - - - - - - - - -

E
:::l

Z

5 -

o
-0.45

DNL Error in LSB

Figure 16. CS5102A DNL Error Distribution

code with more or less occurrences than average
will appear as a DNL of greater or less than zero
LSB. A missing code has zero occurrences, and
will appear as a DNL of -1 LSB.

tolerance than the DNL plots in Figures 11 and
13 appear to indicate.

Figures 15 and 16 illustrate the code width distribution of the DNL plots shown in Figures 11 and
13 respectively. The DNL error distribution plots
indicate that the CS5101A and CS5102A calibrate the majority of their codes to tighter

In the factory, the CS5101A and CS5102A are
tested using Fast Fourier Transform (FFf) techniques to analyze the converters' dynamic
performance. A pure sinewave is applied to the
device, and a "time record" of 1024 samples is

DS45F2

FFT Tests and Windowing

2-137

----------- ----------captured and processed. The FFf algorithm analyzes the spectral content of the digital waveform
and distributes its energy among 512 "frequency
bins." Assuming an ideal sinewave, distribution
of energy in bins outside of the fundamental and
dc can only be due to quantization effects and
errors in the CS5101A and CS5102A.
If sampling is not synchronized to the input sinewave, it is highly unlikely that the time record
will contain an integer number of periods of the
input signal. However, the FFf assumes that the
signal is periodic, and will calculate the spectrum
of a signal that appears to have large discontinuities, thereby yielding a severely distorted
spectrum. To avoid this problem, the time record
is multiplied by a window function prior to performing the FFf. The window function smoothly
forces the endpoints of the time record to zero,
thereby removing the discontinuities. The effect
of the window in the frequency-domain is to convolute the spectrum of the window with that of
the actual input.
The quality of the window used for harmonic
analysis is typically judged by its highest sidelobe level. A five term window is used in FFf
testing of the CS5101A and CS5102A. This windowing algorithm attenuates the side-lobes to
below the noise floor. Artifacts of windowing are
discarded from the signal-to-noise calculation using the assumption that quantization noise is
white. Averaging the FFf results from ten time
records filters the spectral variability that can
arise from capturing finite time records without
disturbing the total energy outside the fundamental. All harmonics are visible in the plots. For
more information on FFT's and windowing refer
to: F.J. HARRIS, "On the use of windows for
harmonic analysis with the Discrete Fourier
Transform", Proc. IEEE, Vol. 66, No.1, Jan
1978, pp.51-83. This is available on request from
Crystal Semiconductor.
As illustrated in Figure 17, the CS5101A typically provides about 92 dB S/(N+D) and
2-138

CS5101A CS5102A
0.001 % THD at 25°C. Figure 18 illustrates only
minor degradation in performance when the ambient temperature is raised to 138°C. Figure 19
and 20 illustrate that the CS5102A typically
yields >92 dB S/(N+D) and 0.001% THD even
with a large change in ambient temperature. Unlike conventional successive-approximation
ADC's, the signal-to-noise and dynamic range of
the CS5101A and CS5102A are not limited by
differential nonlinearities (DNL) caused by calibration errors. Rather, the dominant noise source
is broadband thermal noise which aliases into the
baseband. This white broadband noise also appears as an idle channel noise of 112 LSB (rms).
Sampling Distortion
Like most discrete sample/hold amplifier designs,
the inherent sample/hold of the CS5101A and
CS5102A exhibits a frequency-dependent distortion due to nonideal sampling of the analog input
voltage. The calibrated capacitor array used during conversions is also used to track and hold the
analog input signal. The conversion is not performed on the analog input voltage per se, but is
actually performed on the charge trapped on the
capacitor array at the moment the HOLD command is given. The charge on the array ideally
assumes a linear relationship to the analog input
voltage. Any deviation from this linear relationship will result in conversion errors even if the
conversion process proceeds flawlessly.
At dc, the DAC capacitor array's voltage coefficient dictates the converter's linearity. This
variation in capacitance with respect to applied
signal voltage yields a nonlinear relationship between the charge on the array and the analog
input voltage and places a bow or wave in the
transfer function. This is the dominant source of
distortion at low input frequencies (Figures 17,18,19, and 20).
The ideal relationship between the charge on the
array and the input voltage can also be distorted
DS45F2

-----.",----- -------.",
--.",

CS5101A CS5102A

o,-------------------------~

0
-10
-20
-30
Signal Level -40
ReleliveTo
-50
Full Scale
-60
(dB)
-70
-80
-90
-100
-110
-120
-130

- - - - - - - - - - -S/(N+D): 91.71 dB
- - - - - - - - - - -SID: 101.6 dB

-10
-20
-30
Signal Level
Relative to
Full Scale
(dB)

-:
-80
-70
-80

- - - - - - - - - - - - - - - - - - - - - - - -

-90
-100
-110
-120

50

dc

50

Input Frequency (kHz)

Input Frequency (kHz)

Figure 17. CS5101A FFT (SSC Mode, 1-Channel)

Figure 18. CS5101A FFT (SSC Mode, 1-Channel)

o~------------------------~

Signal Level
Reletive To
Full Scale
(dB)

- - - S/(N+D): 91.06 dB
- - - - - - - - - - SID: 100.5 dB
----------___________ TA = 138°C
- - - - - - -

-10

- - - - - - - - - - -

-20
-30

- - - - - - - - - - -----------

S/(N+D): 92.01 dB
SID: 101.8 dB

o,-------------------------~

-10

- - - - - - - - - - -

-20

- - - - - - - - - - -

S/(N+D): 92.00dB
SID: 101.6 dB

:: : : : : : : : : : : : TA = 138°C

-40
-50

Signal Level -50
Relalivelo
-60
Full Scale
(dB)
-70

-60
-70

-80

-80
-90
-100

- - - - - - - - - - - - - - - - - - - - - -

-90
-100

-.1: -,I. - - - -".~ - - - -..i. :.- - -..: - -120 j • •I111I1~••~IiI"*,.II.
-130
-

-110

10

dc
Input Frequency (kHz)

:~~~1I"M;I.~-.llIi.ao.-I-.~.-'.6..-M"~"'-.-.~..l-lla..-I-.-.-I111-.-I--.-~-~-I:.~-130,1
dc

10
Input Frequency (kHz)

Figure 19. CS5102A FFT (SSC Mode, 1-Channel)

Figure 20_ CS5102A FFT (SSC Mode, 1-Channel)

at high signal frequencies due to nonlinearities in
the internal MOS switches. Dynamic signals
cause ac current to flow through the switches
connecting the capacitor array to the analog input
pin in the track mode. Nonlinear on-resistance in
the switches causes a nonlinear voltage drop.
This effect worsens with increased signal frequency and slew rate. This distortion is negligible
at signal levels below -10 dB of full-scale.

puts are often considered individual, static snapshots in time with no uncertainty or noise. In
reality, the result of each conversion depends on
the analog input level and the instantaneous value
of noise sources in the ADC. If sequential samples from the ADC are treated as a "waveform",
simple filtering can be implemented in software
to improve noise performance with minimal processing overhead.

Noise

All analog circuitry in the CS5101A and
CS5102A is wideband in order to achieve fast
conversions and high throughput. Wideband noise
in the CS5101A and CS5102A integrates to 35
IlV rms in unipolar mode (70 IlV rms in bipolar
mode). This is approximately 112 LSB rms with a
4.5V reference in both modes. Figure 21 shows a

An AID converter's noise can be described like
that of any other analog component. However,
the converter's output is in digital form so any
filtering of its noise must be performed in the
digital domain. Digitized samples of analog inDS45F2

2-139

.. .. ....-.

•~.-r _ _
._.
~~-

...,

CS5101A CS5102A

~-

Count
8192

Count
8192

6144

6144
mlml Noiseless

wm

. . Noiseless
mMl Converter

Converter

4096

4096

~ CS5101A
2048

2048

7FFB
Counts:

~ CS5102A

0

7FFC 7FFD 7FFE 7FFF 8000 I 8001 I
Code (Hexadecimal)
0
989
6359
844
0
0

7FFD 7FFE
Counts:

0

5

8002

8003

5

0

Figure 21. 5101A Histogram Plot of 8192 Conversion
Inputs

Figure 22. 5102A Histogram Plot of 8192 Conversion
Inputs

histogram plot of output code occurrences obtained from 8192 samples taken from a CS5101A
in the bipolar mode. Hexadecimal code 7FFE
was arbitrarily selected and the analog input was
set close to code center. With a noiseless converter, code 7FFE would always appear. The
histogram plot· of the device has a "bell" shape
with all codes other than 7FFE due to internal
noise. Figure 22 illustrates the noise histogram of
the CS5102A.

averaging multiple samples for each word. Oversampling spreads the device's noise over a wider
band (for lower noise density), and averaging applies a low-pass response which filters noise
above the desired signal bandwidth. In general,
the device's noise performance can be maximized
in any application by always sampling at the
maximum specified rate of 100 kHz (CS5101A)
or 20 kHz (CS5102A) (for lowest noise density)
and digitally filtering to the desired signal bandwidth.

In a sampled data system all information about

the analog input applied to the samplelhold appears in the baseband from dc to one-half the
sampling rate. This includes high-frequency components which alias into the baseband. Low-pass
(anti-alias) filters are therefore used to remove
frequency components in the input signal which
are above one-half the sample rate. However, all
wideband noise introduced by the CS5101A and
CS5102A still aliases into the baseband. This
"white" noise is evenly spread from dc to onehalf the sampling rate and integrates to 35 J.lV rms
in unipolar mode.
Noise in the digital domain can be reduced by
sampling at higher than the desired word rate and
2-140

Aperture Jitter
Track-and-hold amplifiers commonly exhibit two
types of aperture jitter. The first, more appropriately termed "aperture window", is an input
voltage dependent variation in the aperture delay.
Its signal-dependency causes distortion at high
frequencies. The proprietary architecture of the
CS5101A and CS5102A avoids applying the input voltage across a sampling switch, thus
avoiding any "aperture window" effects. The second type of aperture jitter, due to component
noise, assumes a random nature. With only
100 ps peak-to-peak aperture jitter, the CS510lA
and CS5102A can process full-scale signals up to
DS45F2

.

,..,... .,.,....
....
.....
,..,..
..._....
~

CS51 01 A CS5102A

90
80

iii'
'tJ
'C'70

""

o

:g

~

'" ...

.~60

a:
~50
c.
:J

~ 40

~

~ r--",

~ 30

D.

20

I'
1 kHz

10 kHz
100 kHz
1 MHz
Power Supply Ripple Frequency

Figure 23. Power Supply Rejection

112 the throughput frequency without significant
errors due to aperture jitter.

CS5101AlCS5102A Improvements Over Earlier CS510l/CS5102

Power Supply Rejection

The CS5101NCS5102A are improved versions
of the earlier CS51 0 1ICS51 02 devices. Primary
improvements are:

The power supply rejection performance of the
CS5101A and CS5102A is enhanced by the onchip self-calibration and an "auto-zero" process.
Drifts in power supply voltages at frequencies
less than the calibration rate have negligible effect on the device's accuracy. This is because the
CS5101A and CS5102A adjust their offset to
within a small fraction of an LSB during calibration. Above the calibration frequency the
excellent power supply rejection of the internal
amplifiers is augmented by an auto-zero process.
Any offsets are stored on the capacitor array and
are effectively subtracted once conversion is initiated. Figure 23 shows power supply rejection of
the CS5101A and CS5102A in the bipolar mode
with the analog input grounded and a 300 mV pP ripple applied to each supply. Power supply
rejection improves by 6 dB in the unipolar mode.

I) Improved DNL at high temperature
(>70°C)
2) Improved input slew rate, yielding improved full scale settling between
conversions.
3) Modifying the previous SSH pin to
SSH/SDL (Simultaneous Sample Hold/Serial Data Latch). The SSH/SDL new
function provides a logic signal which
frames the 16 data bits in SSC and FRN
serial modes. This signal is ideal for easy
interface to serial to parallel shift registers
(74HC595) and to DSP serial ports.
Table 3 summarizes all the improvements.

DS45F2

2-141

---..........-.-.
.......--~

CS5101A CS5102A

~

Function
Better DNl
Faster Fine Charge
Slew Rate
(Vll1s)

CS5101A1CS5102A

CS51 01/CS51 02

No missing codes at +125 °C

Some missed codes at + 125°C

CS5101A CS5102A

CS5101

CS51 02

Unipolar/Fine

2

0.4

Unipolar/Fine

1.3

0.1

Bipolar/Fine

4

0.8

Bipolar/Fine

2.6

0.2

Improved Serial
Interface

Has serial data latch
signal (SSH/SDl).

Does not have serial data
latch (SDl) signal.

ClKIN Rate

CS5101A maximum
ClKIN is 9.216 MHz
CS5102A maximum
ClKIN is 2.0 MHz

CS5101 maximum
ClKIN is 8.0 MHz
CS51 02 maximum
ClKIN is 1.6 MHz

Code and
BP/uP Pin
Function

Independent setting of 2's
complement or offset binary
coding (CODE) and bipolar or
unipolar input range (BP/UP)

Selecting unipolar input range
forces offset binary operation,
independent of the CODE pin state

CRS/FIN Pin

Can be high or low
during calibration

CRSIFIN must be held
low during calibration

Table 3. CS5101AlCS5102A Improvements over CS5101lCS5102

Schematic &Layout Review Service
Confirm Optimum
Schematic &Layout
Before Building Your

2-142

DS45F2

_.-_..--__..__....-....-

CS5101A CS5102A

PIN DESCRIPTIONS

VD-

NEGATIVE DIGITAL POWER
RESET & INITIATE CALIBRATION
MASTER CLOCK INPUT
CRYSTAL OUTPUT

RST
ClKIN
XOUT

SLEEP (LOW POWER) MODE
SLEEP
SCKMOD SERIAL CLOCK MODE SELECT
TEST
TEST
POSITIVE ANALOG POWER
VA+

STANDBY (CALIBRATING)
DIGITAL GROUND

STBY
DGND

AIN2
VA-

POSITIVE DIGITAL POWER
TRACKING CHANNEL 1
TRACKING CHANNEL 2
COARSE/FINE CHARGE CONTROL

VD+
TRK1
TRK2
CRS/FIN

AGND
REFBUF

CHANNEL 2 ANALOG INPUT
NEGATIVE ANALOG POWER
ANALOG GROUND
REFERENCE BUFFER

VOLTAGE REFERENCE
CHANNEL 1 ANALOG INPUT
OUTMOD OUTPUT MODE SELECT
BP/UP
BIPOLAR/UNIPOLAR SELECT
BINARY/2's COMPLEMENT SELECT
CODE
SDATA
SERIAL DATA OUTPUT
VREF
AIN1

SIMULTANEOUS SA-I/ SERIAL DATA LATCH SSHlSDl
HOLD & CONVERT
HOLD
INPUT CHANNEL SELECT
SERIAL DATA CLOCK

til

CH1/2
SClK

VDRST
ClKIN
XOUT
STBY
DGND
VD+

~~
~

5
6

4

3

2

9

28 27 26 25 ; ; -

CS5101A

24

or

23

~

SLEEP
SCKMOD
TEST
VA+
AIN2
VA-

TRK1

AGND

TRK2

REFBUF

CRs/FIN

VREF

SSHlSDl

AIN1

HOLD

OUTMOD

CH1i2

BP/uP

SClK

CODE
SDATA

DS45F2

2-143

.... ........._- ...
._.
~

...,

~~

~-

CS5101A CS5102A

Power Supply Connections

VD+ - Positive Digital Power, PIN 7.
Positive digital power supply. Nominally +5 volts.
VD- - Negative Digital Power, PIN 1.
Negative digital power supply. Nominally -5 volts.
DGND - Digital Ground, PIN 6.
Digital ground [reference].
VA+ - Positive Analog Power, PIN 25.
Positive analog power supply. Nominally +5 volts.
VA- - Negative Analog Power, PIN 23.
Negative analog power supply. Nominally -5 volts.
AGND - Analog Ground, PIN 22.
Analog ground reference.
Oscillator

CLKIN - Clock Input, PIN 3.
All conversions and calibrations are timed from a master clock which can be externally supplied
by driving CLKIN [this input TTL-compatible, CMOS recommended].
XOUT - Crystal Output, PIN 4.
The master clock can be generated by tying a crystal across the CLKIN and XOUT pins. If an
external clock is used, XOUT must be left floating.
Digital Inputs

HOLD - Hold, PIN 12.
A falling transition on this pin sets the CS5101A or CS5102A to the hold state and initiates a
conversion. This input must remain low for at least lItclk + 20 ns. When operating in Free Run
Mode, HOLD is disabled, and should be tied to DGND or VD+.
CRSIFIN - Coarse Charge/Fine Charge Control, PIN 10.
When brought high during acquisition time, CRSIFIN forces the CS5101A or CS5102A into
coarse charge state. This engages the internal buffer amplifier to track the analog input and
charges the capacitor array much faster, thereby allowing the CS5101A or CS5102A to track
high slewing signals. In order to get an accurate sample, the last coarse charge period before
initiating a conversion (bringing HOLD low) must be longer than 0.75 f.ls (CS5101A) or
3.75 f.ls (CS5102A). Similarly, the fine charge period immediately prior to conversion must be
at least 1.125 f.ls (CS5101A) or 5.625 f.ls (CS5102A). The CRSIFIN pin must be low during
conversion time. For normal operation, CRSIFIN should be tied low, in which case the
CS5101A or CS5102A will automatically enter coarse charge for 6 clock cycles immediately
after the end of conversion.
2-144

DS45F2

__

_.. ...
....-.
--.
....--.......

CS5101A CS5102A

CH1J2 - LeftIRight Input Channel Select, PIN 13.
Status at the end of a conversion cycle determines which analog input channel will be acquired
for the next conversion cycle. When in Free Run Mode, CH1I2 is an output, and will indicate
which channel is being sampled during the current acquisition phase.
=-==

SLEEP - Sleep, PIN 28.
When brought low causes the CS5101A or CS5102A to enter a power-down state. All
calibration coefficients are retained in memory, so no recalibration is needed after returning to
the normal operating mode. If using the internal crystal oscillator, time must be allowed after
SLEEP returns high for the crystal oscillator to stabilize. SLEEP should be tied high for normal
operation.
CODE - 2's Complement/Binary Coding Select, PIN 16.
Determines whether output data appears in 2's complement or binary format. If high, 2's
complement; if low, binary.

BPIUP - BipolarlUnipolar Input Range Select, PIN 17.
When low, the CS5101A or CS5102A accepts a unipolar input range from AGND to VREF.
When high, the CS5101A or CS5102A accepts bipolar inputs from -VREF to +VREF.
SCKMOD - Serial Clock Mode Select, PIN 27.
When high, the SCLK pin is an input; when low, it is an output. Used in conjunction with
OUTMOD to'select one of 4 output modes described in Table 2.
OUTMOD - Output Mode Select, PIN 18.
The status of SCKMOD and OUTMOD determine which of four output modes is utilized. The
four modes are ,described in Table 2.
SCLK - Serial Clock, PIN 14.
Serial data changes status on a falling edge of this input, and is valid on a rising edge. When
SCKMOD is high SCLK acts as an input. When SCKMOD is low the CS5101A or CS5102A
generates its own serial clock at one-fourth the master clock frequency and SCLK is an output.
RST - Reset, PIN 2.
When taken low, all internal digital logic is reset. Upon returning high, a full calibration
sequence is initiated which takes 11,528,160 CLKIN cycles (CS5101A) or 2,882,040 CLKIN
cycles (CS5102A) to complete. During calibration, the HOLD input will be ignored. The
CS5101A or CS5102A must be reset at power-up for calibration, however; calibration is
maintained during SLEEP mode, and need not be repeated when resuming normal operation.
Analog Inputs

AIN1, AIN2 - Channell and 2 Analog Inputs, PINS 19 and 24.
Analog input connections for the left and right input channels.
VREF - Voltage Reference, PIN 20.
The analog reference voltage which sets the analog input range. In unipolar mode VREF sets
full-scale; in bipolar mode its magnitude sets both positive and negative full-scale.
DS45F2

2-145

,.

-____-_

.. .....
._..
. --....

CS5101A CS5102A

Digital Outputs

STBY - Standby (Calibrating), PIN 5.
Indicates calibration status after reset. Remains low throughout the calibration sequence and
returns high upon completion.
SDATA - Serial Output, PIN 15.
Presents each output data bit on a falling edge of SCLK. Data is valid to be latched on the
rising edge of SCLK.
SSWSDL - Simultaneous Sample/Hold I Serial Data Latch, PIN 11.
Used to control an external sample/hold amplifier to achieve simultaneous sampling between
channels. In FRN and SSC modes (SCLK is an output), this signal provides a convenient latch
signal which forms the 16 data bits. This can be used to control external serial to parallel
latches, or to control the serial port in a DSP.
TRIO, TRK2 - Tracking Channell, Tracking Channel 2, PINS 8 and 9.
Falls low at the end of a conversion cycle, indicating the acquisition phase for the
corresponding channel. The TRKI or TRK2 pin will return high at the beginning of conversion
for that channel.
Analog Outputs

REFBUF - Reference Buffer Output, PIN 21.
Reference buffer output. A 0.1 JlF ceramic capacitor must be tied between this pin and VA-.
Miscellaneous

TEST - Test, PIN 26.
Allows access to the CS5l0lA's and the CS5102A's test functions which are reserved for
factory use. Must be tied to VD+.

2-146

DS45F2

.-_
._.-.
_
..--__.._-_
...

CS5101A CS5102A

PARAMETER DEFINITIONS
Linearity Error
The deviation of a code from a straight line passing through the endpoints of the transfer
function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 112
LSB below the first code transition and "full-scale" is a point 112 LSB beyond the code
transition to all ones. The deviation is measured from the middle of each particular code. Units
in % Full-Scale.
Differential Linearity
Minimum resolution for which no missing codes is guaranteed. Units in bits.
Full Scale Error
The deviation of the last code transition from the ideal (VREF-3/2 LSB's). Units in LSB's.
Unipolar Offset
The deviation of the first code transition from the ideal (112 LSB above AGND) when in
unipolar mode (BPIUP low). Units in LSB's.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100... 000) from the ideal (112 LSB below
AGND) when in bipolar mode (BPIUP high). Units in LSB's.
Bipolar Negative Full-Scale Error
The deviation of the first code transition from the ideal when in bipolar mode (BPIUP high).
The ideal is defined as lying on a straight line which passes through the final and mid-scale
code transitions. Units in LSB's.
Signal to Peak Harmonic or Noise
The ratio of the fIllS value of the signal to the fIllS value of the next largest spectral component
below the Nyquist rate (excepting de). This component is often an aliased harmonic when the
signal frequency is a significant proportion of the sampling rate. Expressed in decibels.
Total Harmonic Distortion
The ratio of the fIllS sum of all harmonics to the fIllS value of the signal. Units in percent.
Signal-to-(Noise + Distortion)
The ratio of the fIllS value of the signal to the rms sum of all other spectral components below
the Nyquist rate (excepting de), including distortion components. Expressed in decibels.
Aperture Time
The time required after the hold command for the sampling switch to open fully. Effectively a
sampling delay which can be nulled by advancing the sampling signal. Units in nanoseconds.
Aperture Jitter
The range of variation in the aperture time. Effectively the "sampling window" which ultimately
dictates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds.

DS45F2

2-147

--ii,'
.,...

.. ...-..
-. ..-.........
~~

-~...,

CS5101A CS5102A

~-

CS51 01 A Ordering Guide
Model
Conversion Time
CS5101A-JP8
8.13 J.ls
CS51 01 A-KP8
8.13 J.lS
CS5101A-JP16
16.25 J.ls
CS5101A-JL8
8.13 J.ls
CS5101A-KL8
8.13 J.ls
CS51 01 A-JL 16
16.25 J.ls
CS5101A-AP8
8.13 J.ls
CS5101A-BP8
8.13 J.ls
CS5101A-AL8
8.13 J.ls
CS5101A-BL8
8.13 J.ls
CS5101A-SD8
8.13 J.ls
CS5101A-TD8
8.13 J.ls
CS5101A-SE8
8.13 J.ls
CS5101A-TE8
8.13 J.ls
5962-9169101MXA
8.13 J.ls
5962-9169102MXA
8.13 J.ls
5962-9169101M3A
8.13 J.ls
5962-9169102M3A
8.13 J.ls

Throughput
100 kHz
100 kHz
50 kHz
100 kHz
100 kHz
50 kHz
100 kHz
100 kHz
100 kHz
100 kHz
100 kHz
100 kHz
100 kHz
100 kHz
100 kHz
100 kHz
100 kHz
100 kHz
Discontinued
Part Number
CS5101A-SD8B
CS5101A-TD8B
CS5101A-SE8B
CS5101A-TE8B

Linearity
0.003%
0.002%
0.003%
0.003%
0.002%
0.003%
0.003%
0.002%
0.003%
0.002%
0.004%
0.003%
0.004%
0.003%
0.004%
0.003%
0.004%
0.003%

Temperature
Oto70°C
o to 70°C
o to 70°C
Oto70°C
o to 70°C
Oto70°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
-55 to 125°C
-55 to 125°C
-55 to 125°C
-55 to 125°C
-55 to 125°C
-55 to 125°C
-55 to 125°C
-55 to 125°C

Package
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin PLCC
28-Pin PLCC
28-Pin PLCC
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin PLCC
28-Pin PLCC
28-Pin CerDIP
28-Pin CerDIP
28-Pin LCC
28-Pin LCC
28-Pin CerDIP
28-Pin CerDIP
28-Pin LCC
28-Pin LCC

Equivalent
Recommended Device
5962-9169101 MXA
5962-9169102MXA
5962-9169101 M3A
5962-9169102M3A

CS5102A Ordering Guide
Model
Conversion Time
CS5102A-JP
40 J.ls
CS5102A-KP
40 J.LS
CS5102A-JL
40 J.ls
CS5102A-KL
40 J.LS
CS5102A-AP
40 J.ls
CS5102A-BP
40 J.ls
CS5102A-AL
40 J.ls
CS5102A-BL
40 J.LS
CS5102A-SD
40 J.LS
CS5102A-TD
40 J.ls
CS5102A-SE
40 J.lS
CS5102A-TE
40 J.ls
5962-9169201MXA
40 J.ls
5962-9169202MXA
40 J.ls
5962-9169201 M3A
40 J.ls
5962-9169202M3A
40 J.ls

Throughput
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
20 kHz
Discontinued
Part Number
CS5102A-SDB
CS5102A-TDB
CS5102A-SEB
CS5102A-TEB

2-148

Linearity
0.003%
0.0015%
0.003%
0.0015%
0.003%
0.0015%
0.003%
0.0015%
0.004%
0.002%
0.004%
0.002%
0.004%
0.002%
0.004%
0.002%

Temperature
o to 70°C
o to 70°C
o to 70°C
Oto70°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
-40 to 85°C
-55 to 125°C
-55 to 125°C
-55 to 125°C
-55 to 125°C
-55 to 125°C
-55 to 125°C
-55 to 125°C
-55 to 125°C

Package
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin PLCC
28-Pin PLCC
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin PLCC
28-Pin PLCC
28-Pin CerDIP
28-Pin CerDIP
28-Pin LCC
28-Pin LCC
28-Pin CerDIP
28-Pin CerDlP
28-Pin LCC
28-Pin LCC

Equivalent
Recommended Device
5962-9169201 MXA
5962-9169202MXA
5962-9169201 M3A
5962-9169202M3A
DS45F2

..
.. ...

~~

•

~~~.

~~

•

I CDB51 01A151 02A I

•
..,
Semiconductor Corporation

."

1IIIIr., •

~

Evaluation Board for CS5101A & CS5102A

,

Features

General Description

• Serial to Parallel Conversion

The CDB5101A15102A Evaluation Board allows fast
evaluation of the CS5101A and CS5102A 2-Channel,
16-bit Analog-Io-Digital Converters.

• Adjustable Voltage Reference

Analog inputs are via BNC connectors. Digital outputs
are available both directly from the ADC in serial form,
and in 16 bit parallel form.

• ±5 V

An adjustable monolithic voltage reference is included.

Regulators

Ordering Information

• Digital and Analog Patch Areas

OV

-15V

l

Analog
Patch
Area

CDB5101A
CDB5102A

+15V

1 1

VA+ VA-

VD-

~ REFBUF

Input
Buffers
AIN2

r--.
r--.

I--------~

I----~

Vl

Digital
Patch
Area

+

VD+
XOUT~

Reference 1-----.... VREF

VA-

+5V

r r 1 I

I ±5V Regulators I G-ND
AGND~
~D

Voltage

AIN1

OV

ClKIN

r-----=r- --------i.
!Ol EXT
ClKIN
~o

H-O-l-D~-----------------~·S:D_) HOLD

AIN1
AIN2

CS5101A
or
CS5102A

Serial
Output
Buffers

CODE
-

BP/UP
Mode
Select I--------~ SCKMOD
Switches I------~ OUTMOD
I------~ SLEEP

1---"'I~----+i CH1/CH2

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

SSH/SDLt--t-t----~

Serial
to
SClK 14-----t--....----+I Parallel
SDATAr--------+I Conversion

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS45DB3
2-149

~
1

_.-_..--__.._-_
...
._.-.

CDB5101A15102A

Power Supplies
the AINI and AIN2 pins on the converter should
be shorted together. Then the amplifier circuitry
for the unused channel should be disconnected.
For example, if only Analog Input one is used
(in FRN mode) as the input, short the AINI and
AIN2 pins of the converter and remove RlS and
C1S.

Figure 1 shows the, power supply arrangements.
The analog section of the board is powered by
± 12/15 volts, which is regulated down to ± SV
for the ADC. A separate +SV digital supply is
required to power the discrete logic.

Analog Input
If you do not want to use the on-board amplifiers, connect your signal to TP27 for channel 1
and TP32 for channel 2. Use TP28 and TP31 to
break: the connection to the output of the onboard buffers. Your own buffer amplifiers may be
installed in the 2 analog patch areas. For critical
2 channel applications, keep the signal path for
the 2 channels identical.

The CSSlOIA102A converters have a two-channel multiplexer input. Separate amplifiers (see
Figure 2) are provided on the evaluation board to
drive each input independently. If the converter
is used in FRN mode, the multiplexer "pingpongs" between channels. If only one signal is to
be digitized in FRN mode at full speed,

78L05

+15V
+12115V

~~--~~--~~-IN

U7

TP - VA+

OUT·~~~--~--~

COM

AGND

F
COM

-12115V

IN
-15V

U8 OUT
79L05

TP - VA-

TP+5V
+5V
Logic

DGND
TPGND

Figure 1. Power Supplies

2-150

DS45DB3

----------------------

CDB5101A15102A

I
Input

R17

Unipolar OV to +4.5V
Bipolar -4.5V to +4.5V

+15V

.

+
.11lF

2.0k

BIll

~
11lF

C30

TP29 TP28 TP27

R14
50
NPO lnF

'Amplifiers U9 and Ul0
have gain of +1, as
resistors R18 and R21
are left off the board.

-15V

C32

.11lF

C33

11lF
+

C38

11lF
+

-15V

C16

C37

ANALOG
INPUT2 1.Ok

AINl
Fig. 4

C15 lnF

F

R15

0
R28

TP30 TP31 TP32

NPO
AIN2
Fig. 4

50

Figure 2. Input Buffer Circuit.
~V
Rl
2k

~ 'Cl15 IlF

2~

IN

U6

R25

TP77

3 + 7
OUT·~6~~~~,~~~~--~

LT1019-4.5
TRIM
GND

1k
R2
25k

2 0P27

1O'1]'W -,

Ull

C42

R23

0.D1 IlF

47 k

C44

C43

22

C2 +

VREF
Fig. 4

1O'P'·' '
R24
1k
O.lIlF

~C41
-15V

Figure 3. Voltage Reference
DS45DB3

2-151

_.-_..---__.._-_
....
._.-.

CDB5101 Al5102A

Voltage Reference

ternal clock, cut Jumper JOO and drive a CMOS
level compatible clock into the CLKIN BNC
connector. R30 is an optional 50n terminating
resistor if a pulse generator is used.

Figure 3 shows the LTI019-4.5 voltage reference,
which is buffered and filtered to reduce output
impedance and noise.

Sampling Clock (HOLD) Generation
Master Clock
The evaluation board is shipped in FRN mode,
which requires no externally generated HOLD
signal. Alternate modes may be selected using
DIP switch 3 and 4 (See Table 2). An external

Figure 4 shows the local connections to the
CS5101A or CS5102A. The appropriate crystal
components are installed at the factory, which
utilize the on-chip oscillator. For use with an ex-

VD+

10
R4

~.1f.1F
25
---+--+--=-1

YO

AI

Yl

A2

Y2

4

Fig. 4 SSI-VSDL
Fig. 4 CH1/CH2
Fig. 4

SCLK

6
10

>--.-+--1----1 A3

Y3

A4

Y4

12

14
Fig. 6 SLATCH

AS

Y5

74HC365

- 1 SDATA

I SCLK
I SSI-VSDL

3
5

I

7

9

J12

HDR5D

11
13

-

.-----t-'--.J_ J CHlICH2

J13
CHlICH2
Direction

C47

66
R32

HDR10D

Figure S. Serial Output Buffers

DS45DB3

2-153

. "..

_-_
_.-_..__.......
... ..
..,_

.."

CDB51 01A151 02A
~,CS

+51'l
C27 --L
0.1ILF *

10

~<8>Y
Q H I-'------+------t-~__:_:..../,
7

RST
12
11

~<8>x

16

: D15 (MSB)

LatchClK

Q G~----_+----~~~'..../,
6
:014

ShiftClK

Q F ~----_+------i~~..../,
5

D13

Q E f-'-----+------t-r----o--,-'
4

D12

U4
74HC595
14 DATA IN

Q O~----_+------ir----or---...../
3

011

2
QC P-----+------t-t=o,.,..../,
t=o
QB 1

D10
D9

P=>.

Q A 15
GND
J-8

y13

D8

\/\

OE

TPOO
JP2 40way
header

C29--L
10
16
0.1 ILF* r--cR=-=S=TO'----'-=--

reV:
QHt-7-r---------~~

L----9~OATAOUT

re
QGt-6-r---------~~
re D5
QFt-5-r---------~~

US

r.o

74HC595
1 Shift ClK
SClK >-0+-_*_----'1'-'-1
Fi9· 4
2 latch ClK
+-_ _--.-_-'1"'1
SOATA>-o+-_ _-+-_-'1'-'-j4 DATA IN
Fig. 4
OE
GNO

04

~
Q Df"3'---+---------r---'--'
2
~
QCr=---+---------j---'--'

03

+~Vl

3 Cl U3
'-----------4

5V

8

+(

1 JP4

':;:R16
~ 10k

~~
3
:14

Fig.4TRK2~

BOTH

Fig. 4 TRK1 ~ ~ CH2
, l- ~I
CH1
HDR80

D2

~ D1
QBr1-+---------~--'
DO (lSB)
QA~15~----------~==~~
~ DACK~ _ : ORDY

l£ D

Fig. 5

D6

Q Er4-r---------t--"~

1 2 6 .4 114

SLATCH ____--T-POo-,a0

D7

TPOO

Qis?~

-k-J

+5Vl

Q6

'}R10

~~12

9

U2

11

U2

13

{10k
TPOO

10
+5V

10~
Q~

11 S

,----'c
12'1> ClK

~~

~

74RC7fu-4
4
6

SSH/SDl)-_ _ _ _~_----"" U2
Fig. 4
5

Figure 6. Serial to Parallel Converter
2-154

DS45DB3

_-_..__.._-_
...-.
•

.w _ _ . _ .

CDB5101A15102A

nCI1
I

z

W
D-

O

0

I

CODE

OPEN

CLOSE

2's Complement

Binary

HHI 021

BP/UP

[HI 3 I

OUTMOD

Selects Serial Port

SCKMOD

Mode. See Table 2.

I

Unipolar

0

[H 41
I

Bipolar

0

IHHI 051

SLEEP

HHI 061

CH1/CH2'

Normal Mode

Sleep Mode

AIN1

AIN2

'SW6 is not active when the converter is operating in the FRN mode.

Table 1. DIP Switch Selections

CS51 01 AlCS51 02A
Output Mode

SCKMOD
(SW4)

OUTMOD
(SW3)

CLOSE

CLOSE

(FRN) Free Run

CLOSE

OPEN

(SSC) Synchronous Self Clocking

OPEN

CLOSE

(RBT) Registered Burst Transmission

OPEN
NOTE: CLOSED

=

OPEN
(PDT) Pipelined Data Transmission
LOW 0; OPEN HIGH 1.

=

=

=

Table 2. Output Mode Selections

DIP Switches
Tables I and 2 show the DIP switch settings.

Miscellaneous Hints on Using the Evaluation
Board
Always depress the reset button after powering
up the board. The CS510lA & CS5102A are self
calibrating ADC's which require a reset to initiate the internal calibration procedure.
DS45DB3

Crystal Semiconductor has software, available on
request, which allows the evaluation board to be
connected to a Metrabyte PIOl2 parallel I/O
card (which uses an Intel 8255 PIO chip), which
is plugged into an liM PC or compatible computer. The software is assembly language drivers
to read the data from the board. Also included is
source code, in Fortran, of an FFT routine.

2-155

(II)

--+-~WJiv-......-o

1 nFCOGI
ceramic _

50 k

1 nF COG
ceramic

f

I

V,,+_-,\1AMMr-___ 1 M
Notes:
121 k

Offset

ADJ

Vout

1) In B and offset adjust are optional.

V-

...

10
+15 V o-----IWV'v~-I--I- - - - O V+
1 J.1F

+

2) Offset adjustment range is
± 10 mV with values shown.

0.01 J.1F

ta~~a~m T._~T;-c_e_ra_m_i_c--,

I1+ II

1J.1F
tantalum
35 V ~

0.01 J.1F
ceramic

l

-15 V o-----IWV'v~--....-----<----o V10

Figure 2. Example Input Buffer Circuit (not provided on the CDB5126 evaluation board)

+15V

2
IN

OUTf-=6----<~

U2

LT1019-5 TRIM 5
G=N'rCD;o-_--" CW
4

Rl
25 k

22

L

U1

TP1

CS5126

L - -_ _

TP4~~---e----j

R5
1k

C4
~O.lIlF

-15V

Figure 3. Voltage Reference

2-180

DS32DB5

....-- ... .
.-...,,--_._.
--~

~

CDB5126

~

A 5 volt reference can be used provided the supplies to the ADC are elevated to ± 5.3 volts. This
can be done by inserting 22 Q resistors in series
with the regulator (U4 and U5) common leads.

BNC connector. Rl5 is an optional 75 Q terminating resistor for the external clock BNC.

Master Clock

The CS5126 requires an external 24.576 MHz
clock for a 96 kHz sample rate. A 24.576 MHz
clock oscillator module (U6) is provided. An external clock can also be selected by PI, via a

+5Vl
P9
U8, U9 U7 09 Output

U6

EXT

I 11,

'NCO

ClKI~

R15

,0_

1

TP15

-'0

3 ClKIN
0---.-_+----"1

R23
1k

7
VD+

VA+

HOLD

75

SClK

12
14
13

4 NC
TP10

U1
CS5126

RST r=2'---_ _~
C13
0.1 IlF

DGND 6

C9

20 VREF

C9

22 AGND

TST2~1~8-------r-~~-T--1
TST4r2~7-------r-~~--1

R8
47k

T-S-Tl~1~7-------r-~~
CODE~1=6-------r-~
SlEEpr2~8------~
STBY 5

TP2

+5Vl

TP9

I}-O-oc>-o-<~1-=-j9 AINl

SSHl 10 '--TP-a- P8
SSH2 11
SDATA 15

a·way DIP switch
SWl thruswa

TP5
TP14
--U8,pin14

-5VA ---_---+---J\MfIr-----4~_.

Figure 4. ADC Connections
DS32DB5

2-181

----------- -----------

CDB5126

Sampling Clock Generation Logic
The CS5126 requires an external serial clock to
clock out the data. The CDB5126 board has the
logic necessary to generate the master clock,
HOLD, LlR, and SCLK to allow fast evaluation
of the ADC. In most systems, these timing signals will be available from the main timing
section, typically generated by a logic array of
some variety. HOLD may be brought in externally via a
BNC, optionally terminated by R29. SCLK and
LlR select may be brought in externally via test
points and removing jumpers.
Figure 5 shows the on-board clock generation circuitry. U7 (74HC4040) produces binary divided
ratios of the 24.576 MHz master clock. Q4 generates a 1.5 MHz clock, which is used for SCLK.
Q8 generates a 96 kHz clock, used for HOLD,
and Q9 generates a 48 kHz clock, optionally used

R16

pA

Serial to Parallel Conversion
Figure 6 shows the serial to parallel conversion
circuit. Two 74HC595 shift registerllatches connected in series with SDATA assemble 16-bit,
parallel words, clocked by SCLK. As discussed
above, the outputs are latched inside the
74HC595 at the end of each 16-bit word. The
outputs are brought out to a 40-way header (P5).
Only low capacitance, twisted pair, ribbon cable
should be used.

R19
47 k

P4

47 k

to toggle LIR select. This set of clocks causes the
CS5126 to continuously convert, generating a
continuous stream of serial data bits. To correctly
identify the last bit of each word, U12 produces a
pulse only when Q4, Q5, Q6, Q7, Q8, and optionally Q9 are all high. This state is latched by
UlOA to prevent any glitches, and the resulting
signal (attached to TPI8) is used to latch the U8U9 shift registers.

R16, p.5
47 k

C31
R16, p.3

4

Q 12

+5Vl
-]..929

4 J
)0-_ _-""-1

]!i.l ~F
Q1 9

15 Qll

Q27

+5Vl

U7

11

11

Q3 6

1

Q4F5~V~*+~~---------Sui!

Q5~70

Q6 p2____-----"

H-oo<:>-,-I°"1ClK

8

2

R28

12Q9

11 RST

U10A
74HC73 Q 13
K
3

16 =

1 Q12

14 Ql0

~.I~F

;!
I

Q7 r4------~

Q81L__~ _ _~

~
;'I.~

"----------'

PI
(ClKIN)

P2
(HOLD)

P3

U8, U9
ShiftClK

U8,U9
latch ClK

Figure 5. Timing Generator
2-182

DS32DB5

_.-.......__........
...-..
..,

--~

CDB5126
+5Vl

~C3

R 31 ~
47 k ~

11
12

P7

16

f-----:o

QG 6

~

014

latch ClK

QF 5

~

013

QE 4

f-----:o

012

Qo 3

~

011

Qc 2

~

010

Qs 1

~

09

Q A 15

~

08

QG 6

R 30
47 k

~

, 05

QE 4

f--'O

: 04

2

Qs 1

tIL

: 03
,02

~

, 01

~ OACK:

~
R16, p.7
47 k

+5Vl

>---'0

0

: 00 (lSS)

Q A 15

OATAIN
RST

07

,06

f--,{)

Qc

Shift ClK

~

5

Qo 3

latch ClK

I'

40 way
header

~

QH 7
QF

--

~

P5

13
DE
~l~ OATADUT
~
16
U8
"""::""=i=C5 8
74HC595
0-J,-

14

v-

Shift ClK

9

SOATA(U1)

~

015 (MSS)

OATAIN
DE
13

11

v-

~

8

12

P6, : ,-----0 - : CS
, -

QH 7

U9
74HC595

G

~

~ 0.111F

10
RST
P9,P3

=

R22
47 k

~

-

:OROY

-

-

~ R16, p.6
47 k

R1.,p,tl:'9,'
74HCOO U11

=

+5Vl

6

6

47k

a:,i

P11
TP 18 0----0--;0

'0'

P12
TRKl (U1)
TRKR (U1)

74HCOO

~6

! TP~

- - -0

7

K

J
5,>

RST

U10S
74HC73

_8

Q

17

o-P!3,
,-0 O-,~
1'-0 o-:~

2~

3'

0-:---'
0;________

4~

0-'----

Figure 6. Serial to Parallel Converter
DS32DB5

2-183

..............
,.,....... _..
.........
~

~

CDB5126

~

J1

-

J2

-

Joins analog ground to digital ground on the board.
Joins LT1 019-5 reference directly to the VREF pin on the ADC. Before doing this, break the connection
between R3 and the ADC VREF pin by using a twist drill to remove the central feedthrough. This option
allows evaluation of different reference configurations.
Connects an external clock to CLKIN on the ADC.

J4

Table 1. Solder Link Options

P1

0

*

1

- Select external clock via BNC connector
-

P2

* o-

P3

*

P4

*

P6

*

P7

* o-

P8

*

Select on-board generated HOLD.
1 - Select external HOLD via BNC connector.
Connect SCLK to on-board shift registers.

UR select pin high, selecting the left channel only.
1 - Drive UR select at 48 kHz from the on-board timing generator.
2 - Pull UR select pin low, selecting the right channel only.

0- Pull

Connect the OE pins of the shift registers to ground. Permanently enables the 3-state output buffers.
Connects the on-board Data Ready signal to the shift registers.
1 - Connects the NAND gate outputs (U11, pin 11) to the shift registers.

1
2
3
4

P9
P10

Select on-board clock generated by U6.

*
*

- Connects the un-latched on-board Data Ready signal to P5.
-

-

Connects TRKL and TRKR ANDED together to P5. This signal can be used as an "End of Convert"
indicator.
Connects TRKL to P5.
Connects TRKR to P5.
Connects the on-board. generated SCLK to the rest of the on-board circuitry.

0

-

Causes the on-board Data Ready generating circuit to flag data ready every conversion.
1 - Causes the on-board Data Ready generating circuit to flag data ready every left conversion. P4 must
be in position 1 for this to work.
2
Causes the on-board Data Ready generating circuit to flag data ready every right conversion. P4 must
be in position 1 for this to work.

-

P11

P12

*

0

*
*

- Connects TRKL & TRKR to U10B, the handshake flip-flop.

1 - Connects the on-board data ready signal to U10B.

-

Allows selection of the DRDY signals for alternate channels.
1 - Connects the TRKL & TRKR to U11, pin 13.

0

Factory default state for CS5126

Table 2. Shorting Plug Selectable Options

2-184

DS32DB5

.....-._.
.....
. ......
.....
......
~

~~

CDB5126

~~

Test Points

UlOB (74HC73) is used as a handshake flip-flop
with the computer system attached to the evaluation board. The board brings DRDY low. The
computer reads the data and then sets DACK momentarily high. This resets UlOB for the next
word. This handshake can be disabled by setting
P8 jumper to position 1.
DIP Switches

Figure 7 and Table 3 shows the DIP switch selectable options.

Table 4 is a list of the test points provided on the
Evaluation Board.
CS5126
TP1

VAEF

TP2

AINA

TP3

AINl

TP4

AGND

TP5

SSH2

TP6

SSH1

TP7

TAKR

TP8
SLEEP mode

TP9
set at logic "1" for CS5126

set at logic "1" for CS5126

TAKl
--

STBY

TP10

NC

TP11

UR

TP12

SClK
--

Output Encoding

I

No Connect
(use, option)

OPEN
Logic "0"

TP13

HOLD

TP14

SDATA

TP15

ClKIN

TP16

DGND

TP17

TRKl + TAKA

TP18

latch Clock for the 74HC595
shift registers

=ON =CLOSED I Logic "1" =OFF =OPEN
Table 4. CDB5126 Test Points

Figure 7. DIP switch configuration

Switch

Loaic

1

0
1

234
0
1

5
6

Mode
SLEEP mode
Normal mode
set to "1" for CS5126
Offset binary output code
2's complement output code
Unconnected. Available for
user's applications

Table 3. DIP Switch Selection Options

DS32DB5

2·185

-

I.

----------------------

CDB5126

Miscellaneous Hints on Using the Evaluation
Board
Always hit the reset button after powering-up the
board. The CS5126 is self calibrating and require
the reset signal to initiate the calibration procedure.

CDBCAPTURE Interface
Figure 8 illustrates the CDBCAPTURE interface
that can be constructed in the digital patch area.
A 2-row, 10 pin stake header is wired as shown.

P4 controls the ADC input mux. This is used to
set the mux to be continuously connected to one
channel, or to be toggling between two channels.
This is very useful for evaluating overs amp led vs.
regular sampling digital audio.
PIO controls the Data Ready pulses from the onboard logic. To cause every data sample to be
read, select option O. If you wish to read only
every alternate sample, then select option 1 or 2,
depending on whether you wish to read every left
channel value, or every right channel value. This
is useful for evaluating the part with a test system
which does not separate alternate values .

.................._----------,
Circuit Board
(Top View)

(GND-Digital Patch) GND 0

0

+5V

(+5VL - Digital Patch)

GND 0

0

+5V

(+5VL - Digital Patch)

GND 0

0

FRAME (DRDY - P8)

GND 0

0

SCLK (SCLK - U9-11)

GND 0

0

SDATA (SDATA - U8-14)

Figure 8. CDBCAPTURE Header Signal Pattern
2-186

DS32DB5

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CDB5126

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• Notes·

2-188

DS32DB5

.............
............
.,,--- ....

CS5317

,."

Semiconductor Corporation

16-8it, 20 kHz Oversampling AID Converter
Features

General Description

• Complete Voiceband DSP Front-End
16-Bit AID Converter
Internal Track & Hold Amplifier
On-Chip Voltage Reference
Linear-Phase Digital Filter
• On-Chip PLL for Simplified Output
Phase Locking in Modem Applications
• 84 dB Dynamic Range
.80 dB Total Harmonic Distortion
• Output Word Rates up to 20 kHz

The CS5317 is an ideal analog front-end for voiceband
signal processing applications such as high-performance modems, passive sonar, and voice recognition
systems. It includes a 1S-bit AID converter with an internal track & hold amplifier, a voltage reference, and a
linear-phase digital filter.
An on-chip phase-lock loop (Pll) circuit simplifies the
CS5317's use in applications where the output word
rate must be locked to an extemal sampling signal.
The CS5317 uses delta-sigma modulation to achieve
1S-bit output word rates up to 20 kHz. The delta-sigma
technique utilizes oversampling followed by a digital filtering and decimation process. The combination of
oversampling and digital filtering greatly eases antialias
requirements. Thus, the CS5317 offers 84 dB dynamic
range and 80 dB THO and signal bandwidths up to 10
kHz at a fraction of the cost of hybrid and discrete solutions.

• DSP-Compatible Serial Interface

The CS5317's advanced CMOS construction provides
low power consumption of 220 mW and the inherent
reliability of monolithic devices.

• Low Power Dissipation: 220 mW

ORDERING INFORMATION:

Page 2-208

RST

DOE

VCOIN

REFBUF

12

PHDT

MODE

ClKIN

VOLTAGE
REFERENCE

CLKOUT
COMPARATOR

NC

DATA

384th Order
DECIMATION
FILTER

AIN
13
14
VA+

VA-

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760

(512) 445 7222 FAX 512445 7581

15
AGND

DOUT

2

10

4

VD+

VD-

DGND

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS27F4
2-189

.... .....
. ..,--._..
.....
~

~~~

CS5317

~~

ANALOG CHARACTERISTICS (TA =TMIN - TMAX; VA+,
ClKIN

VD+ = 5V ±10%; VA-, VD- = -5V ±10%;
= 4.9152 MHz in ClKOR mode,; 1kHz Input Sinewave; with 1.2 k.Q, .01 J..lF antialiasing filter.)

Parameter"

Min

Typ

Max

Units

16

o to 70
-

-

Bits

78

84
80

-

84

-

dB

72

Specified Temperature Range
Resolution

°c

Dynamic Performance
(Note 1)

Dynamic Rnage
Total Harmonic Distortion
Signal to Intermodulation Distorition

dB
dB

dcAccuracy

-

±OA

lSB

-

-

Positive Full-Scale Error

±150

-

mV

Positive Full-Scale Drift

-

±500

J..lVloC

±50

-

Differential Nonlinearity

(Note2)

Bipolar Offset Error
Bipolar Offset Drift

±10

mV
J..lV/oC

Filter Characteristics
Absolute Group Delay

(Note 3)

78.125

-

-

J..ls

Passband Frequency

(Note 4)

-

5

-

kHz

-

80

-

k.Q

±2.75

-

-

V

-

220

300

mW

Input Characteristics
AC Input Impedance

(1kHz)

Analog Input Full Scale Signal level

Power Supplies
Power Dissipation
Notes:

(Note5)

1. Measured over the full 0 to 9.6kHz band with a -20dB input and extrapolated to full-scale. Since this
includes energy in the stopband above 5kHz, additional post-filtering at the CS5317's output can
typically achieve 88dB dynamic range by improving rejection above 5kHz. This can be increased to
90dB by bandlimiting the output to 2.5kHz.
2. No missing codes is guaranteed by design.
3. Group delay is constant with respect to input analog frequency; that is, the digital FIR filter has
linear phase. Group delay is determined by the formula Dgrp = 384/ClKIN in ClKOR mode, or
1921ClKOUT in any mode.
4. The digital filter's frequency response scales with the master clock. Its -3dB pOint is determined by
f-3dB = ClKIN/977.3 in ClKOR mode, or ClKOUT/488.65 in any mode.
5. All outputs unloaded. All inputs CMOS levels .

• Refer to the Parameter Definitions section after the Pin Description section.

2-190

DS27F4

_.........-...........
_...-..
~---

CS5317

ANALOG CHARACTERISTICS (continued)
Parameter
Power Supply Rejection

VA+
VAVD+
VD-

Min

Typ

Max

Units

-

60
45
60
55

-

dB
dB
dB
dB

(Note 6)

-

o to 70

Specified Temperature Range

°C

Phase-Lock Loop Characteristics
VCO Gain Constant, Ko

(Note 7)

-4

-10

-30

MradNs

1.28

-

5.12

MHz

Phase Detector Gain Control, Kd

-3

-8

-12

JiAlrad

Phase Detector Prop. Delay

-

VCO Operating Frequency

Notes:

(Note 8)
50
100
6. With 300mV p-p, 1kHz ripple applied to each supply separately.
7. Over 1.28 MHz to 5.12 MHz VCO output range, where VCO frequency = 2· CLKOUT.
8. Delay from an input edge to the phase detector to a response at the PHDT output pin.

ns

DIGITAL CHARACTERISTICS (TA = TMIN - TMAX; VA+, VD+ = 5V±10%; VA-, VD- = -5V±10%)
All measurements performed under static conditions.
Parameter

Symbol

Min

Typ

High-Level Input Voltage

VIH

2.0

-

-

V

Low-Level Input Voltage

VIL

-

0.8

V

VOH

(VD+}-1.0V

-

-

V

VOL

-

-

0.4

V

-

-

10

JiA

±10

9

-

JiA
pF

High-Level Output Voltage
Low-Level Output Voltage

(Note 9)
lOUT = 1.6mA

Input Leakage Current

lin

3-State Leakage Current

loz

Digital Output Pin Capacitance

Cout

Note:

Max

Units

9. lout=-100JiA. This specification guarantees the ability to drive one TTL load (VoH=2.4V @ lout=-40JiA.).

RECOMMENDED OPERATING CONDITIONS (DGND, AGND = OV, see Note 10.)
Parameter
DC Power Supplies:

Positive Digital
Negative Digital
Positive Analog
Negative Analog

Master Clock Frequency
Note: 10. All voltages with respect to ground.

Symbol

Min

Typ

Max

Units

VD+
VDVA+
VA-

4.5
-4.5
4.5
-4.5

5.0
-5.0
5.0
-5.0

5.5
-5.5
5.5
-5.5

V
V
V
V

folk

0.01

-

5.12

MHz

Specifications are subject to change without notice.
DS27F4

2-191

.. ...
. .,,-.......
....
~-

~~-

CS5317

~~

SWITCHING CHARACTERISTICS (TA = TMIN-TMAX;
Parameter
Master Clock Frequency:

CL=50 pF; VD+

Symbol

Min

'= 5V±10%; VD- = -5V±10%)
Typ

Max

Units

-

-

20
10
5.12

kHz
kHz
MHz

-

20

kHz

ClKIN
ClKG1 Mode
ClKG2 Mode
ClKOR Mode

fclkg1
fclkg2
fclkor

Output Word Rate:

DOUT

fdout

-

Rise Times:

Any Digital Input
Any Digital Output

trisein
triseout

-

20
15

1000
20

ns
ns

Fall Times:

Any Digital Input
Any Digital Output

tfallin
tfallout

-

20
15

1000
20

ns
ns

tpwl1
tpwh1
tpwl1
tpwh1

200
200
45
45

-

-

ns
ns
ns
ns

tpwr

400

tsu1
tsu2

40
40

-

tphl1
tphl2
tplh1
tplh2
tplh3
tplh4
tplh5
tplhB

-

ClKIN Duty Cycle
ClKG1 and CKlG2 Modes
ClKOR Mode

Pulse Width low
Pulse Width High
Pulse Width low
Pulse Width High

RST Pulse Width low
Set Up Times:

RST High to ClKIN High
ClKIN High to RST High

Propagation Delays:
DOE Falling to Data Valid
ClKIN Rising to DOUT Falling
DOE Rising to Hi-Z Output
ClKOUT Rising to DOUT Falling
ClKOUT Rising to DOUT Rising
ClKOUT Rising to Data Valid
ClKIN Rising to ClKOUT Falling
ClKIN Rising to ClKOUT Rising

(Note 11)

(Note 12)
(Note 12)

-

-

-

-

-

150

-

80
60
60
100
200
200

1

ns
ns
ns

-

ns
ClKOUT
cycles
ns
ns
ns
ns
ns

Notes: 11. ClKIN only pertains to ClKG1 and ClKG2 modes.
12. Only valid in ClKOR mode.

ABSOLUTE MAXIMUM RATINGS (DGND, AGND = OV,
Parameter
DC Power Supplies:

Positive Digital
Negative Digital
Positive Analog
Negative Analog

all voltages with repect to groung)

Symbol

Min

Max

Units

VD+
VDVA+
VA-

-0.3
0.3
-0.3
0.3

(VA+) + 0.3
-6.0
6.0
-6.0

V
V
V
V

lin

-

±10

mA

Analog Input Voltage (AIN and VREF pins)

VINA

(VA-) - 0.3

(VA+) + 0.3

V

Digital Input Voltage

VIND

-0.3

(VD+) + 0.3

V

TA

-55

125

°c
°c

Input Current, Any Pin Except Supplies

Ambient Operating Temperature

(Note 13)

Storage Temperature
-65
150
Tstg
Notes: 13. Transient currents up to 100mA will not cause SCR latch-up.
WARNING:Operating this device at or beyond these extremes may result in permanent damage to the device.
Normal operation of the part is not guaranteed at these extremes.

2-192

DS27F4

.... ...
. ..-.-.-..

,..,
,..,,..,.., ,..,,..,
..,

CS5317

risein~fallin

r

2.0V

2.4V

0.8 V

0.4V

Rise and Fall Times

ClKIN

J

t pwh1

tpwl1

l _ _-----l}eLKIN Timing

ClKIN
(Note 14)

ClKOUT
t plh1

DOUT

DATA

DOE
(Note 15)

Serial Output Timing
ClKIN

ClKOUT

DOUT

s ---t pwr

Reset Timing

Notes: 14. ClKIN only pertains to ClKG1 and ClKG2 modes.
15. If DOE is brought high during serial data transfer, ClKOUT, DOUT, and DATA will immediately
3-state and the rest of the serial data is lost.
16. RST must be held high except in the clock override (ClKOR) mode where it can be used to align
the phases of all internal clocks.

DS27F4

2-193

_.

..,..... .
...........
.........
"..

~

GENERAL DESCRIPTION

The CS5317 functions as a complete data conversion subsystem for voiceband signal processing.
The AID converter, sample/hold, voltage reference, and much of the antialiasing filtering are
performed on-chip. The CS5317's serial interface
offers its 16-bit, 2's complement output in a format
which
easily
interfaces
with
industry-standard micro's and DSP's.
The CS5317 also includes a phase-locked loop
that simplifies the converter's application in systems which require sampling to be locked to an
external signal source. The CS5317 continuously
samples its analog input at a rate set by an external clock source. On-chip digital filtering, an
integral part of the delta-sigma ADC, processes
the data and updates the 16-bit output register at
up to 20 kHz. The CS5317 can be read at any rate
up to 20kHz.
The CS5317 is a CS5316 with an on-chip sampling clock generator. As such, it replaces the
CS5316 and should be considered for all new designs. In addition, a CS5316 look-alike mode is
included, allowing a CS5317 to be dropped into a
CS5316 socket.

THEORY OF OPERATION

The CS5317 utilizes the delta-sigma technique of
executing low-cost, high-resolution AID conversions. A delta-sigma AID converter consists of
two basic blocks: an analog modulator and a digital filter.
Conversion

The analog modulator consists of a I-bit AID converter (that is, a comparator) embedded in an
analog negative feedback loop with high openloop gain. The modulator samples and converts
the analog input at a rate well above the bandwidth of interest (2.5 MHz for the CS5317). The
2-194

CS5317

~

modulator's I-bit output conveys information in
the form of duty cycle. The digital filter then
processes the I-bit signal and extracts a high
resolution output at a much lower rate (that is,
16-bits at a 20 kHz word rate with a 5 kHz input
bandwidth).
An elementary example of a delta-sigma AID
converter is a conventional voltage-to-frequency
converter and counter. The VFC's I-bit output
conveys information in the form of frequency (or
duty-cycle), which is then filtered (averaged) by
the counter for higher resolution. In comparison,
the CS5317 uses a more sophisticated multi-order
modulator and more powerful FIR filtering to extract higher word rates, much lower noise, and
more useful system-level filtering.
Filtering

At the system level, the CS5317's digital filter
can be modeled exactly like an analog filter with
a few minor differences. First, digital filtering resides behind the AID conversion and can thus
reject noise injected during the conversion process (i.e. power supply ripple, voltage reference
noise, or noise in the ADC itself). Analog filtering
cannot.
Also, since digital filtering resides behind the AID
converter, noise riding unfiltered on a near-fullscale input could potentially saturate the ADC. In
contrast, analog filtering removes the noise before
it ever reaches the converter. To address this issue,
the CS5317's analog modulator and digital filter
reserve headroom such that the device can process signals with lOOmV "excursions" above
full-scale and still output accurately converted
and filtered data. Filtered input signals above fullscale still result in an output of all ones.
An Application Note called "Delta Sigma Overview" contains more details on delta-sigma
conversion and digital filtering.

DS27F4

___
......
._.-.
-.....--...
",."

CS5317

SYSTEM DESIGN WITH THE CS5317
Like a tracking ADC, the CS5317 continuously
samples and converts, always tracking the analog
input signal and updating its output register at a
20 kHz rate. The device can be read at any rate to
create any system-level sampling rate desired up
to 20kHz.

Clocking
Oversampling is a critical function in delta-sigma
NO conversion. Although system-level output
sample rates typically remain between 7kHz and
20kHz in voiceband applications, the CS5317 actually samples and converts the analog input at
rates up to 2.56 MHz. This internal sampling rate
is typically set by a master clock which is on the
order of several megahertz. See Table1 for a complete description of the clock relationships in the
various CS5317 operating modes.

+5V
Analog

Some systems such as echo-canceling modems,
though, require the output sampling rate to be
locked to a sampling signal which is 20 kHz or
below. For this reason the CS5317 includes an
on-chip phase-lock loop (PLL) which can generate its requisite 5.12 MHz master clock from a
20 kHz sampling signal.
The CS5317 features two modes of operation
which utilize the internal PLL. The first, termed
Clock Generation 1 (CLKGl), accepts a sampling
clock up to 20 kHz at the CLKIN pin and internally generates the requisite 5.12 MHz clock. The
CS5317 then processes samples updating its output register at the rate defined at CLKIN,
typically 20 kHz. For a 20 kHz clock input the
digital filter's 3 dB comer is set at 5.239 kHz, so
CLKGI provides a factor of 2X oversampling at
the system level (20 kHz is twice the minimum
possible sampling frequency needed to reconstruct a 5 kHz input). The CLKGl mode is
initiated by tying the MODE input to +5V.

10n

0----,---.,-------,-----"\ V ' v - , - - - - - - - - - - 1 : - - - - ,

Supply
VA+

MODE ~ VD- (clock override mode I CLKOR)
~ VD+ (clock gen. mode/CLKG1)
CS5317

----=:L (clock gen. mode I CLKG2)

Analog
AIN
± 2.75V

Signal
Source

18

VCOIN

PHDT

~'~r----r----r--=-I

-5V
Analog

AGND

o---4---~---~'-.JV

Supply

Figure 1. System Connection Diagram with Example PLL Components

DS27F4

2-195

-.
...............-.
...............

..,,--

Mode
Pin
OV

CS5317
Output Word
Rate Provides
System-level 2X
RESET Oversampling
HIGH
NO

Symbol
CLKG2
Clock
CLKG2
Gen. 2
CLKG2
YES
HIGH
CLKG1
+5V
Clock
CLKG1
Gen. 1
CLKG1
CLKOR
-5V
SYNC
YES
Clock
CLKOR
Override
CLKOR
CS5316
YES
CS5316 FSYNC LOW
• tdcD
- Delay from CLKIN rising to DOUT falling =
Mode

ClKOUT

ClKIN
(kHz)
7.2
9.6
10.0 (max)
14.4
19.2
20.0 (max)
3686.4
4915.2
5120.0 (max)
5120.0 (max)
1 CLKOUT cycle

DOUT

fsln

fsout

F

(MHz)
1.8432
2.4576
2.56
1.8432
2.4576
2.56
1.8432
2.4576
2.56
2.56

(kHz)
7.2
9.6
10.0
14.4
19.2
20.0
14.4
19.2
20.0
20.0

(kHz)
14.4
19.2
20.0
14.4
19.2
20.0
14.4
19.2
20.0
20.0

tdeO*
(ns)
542.5
406.9
390.6
542.5
406.9
390.6
N/A
N/A
N/A
N/A

Table 1. Mode Comparisons

The second PLL mode is termed Clock Generation 2 (CLKG2) which generates its 5.12 MHz
clock from a IO kHz external sampling signal.
Again, output samples are available at the system
sampling rate set by CLKIN, typically 10 kHz.
For the full-rated 10 kHz clock CLKG2 still sets
the filter's 3 dB point at 5 kHz. Therefore,
CLKG2 provides no oversampling beyond the
Nyquist requirement at the system level
(10 kHz: 5 kHz) and its internal digital filter provides little anti-aliasing value. The CLKG2 mode
is initiated by grounding the MODE pin.
The CS5317 features a third operating mode
called Clock Override (CLKOR). Initiated by tying the MODE pin to -5V, CLKOR allows the
5.12 MHz master clock to be driven directly into
the CLKIN pin. The CS5317 then processes samples updating its output register at fcJkin/256.
Since all clocking is generated internally, the
CLKOR mode includes a Reset capability which
allows the output samples of mUltiple CS5317's
to be synchronized.
The CS5317 also has a CS5316 compatible
mode, selected by tying RST low, and using
MODE (pin 7) as the FSYNC pin. See the
CS5316 data sheet for detailed timing information.
2-196

Analog Design Considerations

DC Characteristics
The CS5317 was designed for signal processing.
Its analog modulator uses CMOS amplifiers reSUlting in offset and gain errors which drift over
temperature. If the CS5317 is being considered
for low-frequency « 10 Hz) measurement applications, Crystal Semiconductor recommends the
CS5501, a low-cost, d.c. accurate, delta-sigma
ADC featuring excellent 60 Hz rejection and a
system-level calibration capability.
. The Analog Input Range and Coding Format

The input range of the CS5317 is nominally ± 3V,
with ± 250 mV possible gain error. Because of
this gain error, analog input levels should be kept
below ± 2.75V. The converter's serial output appears MSB-first in 2's complement format.
Antialiasing Considerations

In applying the CS5317, aliasing occurs during
both the initial sampling of the analog input at fSin
(-2.5 MHz) and during the digital decimation
process to the 16-bit output sample rate, f sout •

DS27F4

..................
.... _._
...........
..,

CS5317

Initial Sampling
The CSS317 samples the analog input, AIN, at
one-half the master clock frequency (-2.S MHz
max). The input sampling frequency, fSin , appears
at CLKOUT regardless of whether the master
clock is generated on-chip (CLKG 1 and CLKG2
modes) or driven directly into the CSS317
(CLKOR mode). The digital filter then processes
the input signal at the input sample rate.
Like any sampled-data filter, though, the digital
filter's passband spectrum repeats around integer
multiples of the sample rate, fSin• That is, when
the CSS317 is operating at its full-rated speed any

I

Mag H(eim )

I (dB)

-2.74 dB

o

noise within ± S kHz bands around 2.5 MHz, S
MHz, 7.5 MHz, etc. will pass unfiltered and alias
into the baseband. Such noise can only be filtered
by analog filtering before the signal is sampled.
Since the signal is heavily oversampled (2.S
MHz: S kHz, or SOO: 1), a single-pole passive
RC filter can be used as shown in Figure 2.

I~put
Signal

~AIN
1.2 K

~

O.Q1IlF

Note: Any nonlinearities contributed by this filter
will be encoded as distortion by the CSS317.
Therefore a low distortion, high frequency capacitor such as COG-ceramic is recommended.
Figure 2. Anti-alias Filter

-40

-80

o .25 F.5 F
0
'0

I(

3
sin(1287t/ T)J 1 =
128sir(1t/T)

N

J:

N

J:

F
N

J:

-"

-"

-"

I/)

0

0

N

2F
N

J:

3F
N

J:

-"

-"

...r

co

0

0

Magnitude where: T= 111sin
Isin = input sampling frequency = CLKOUT frequency for all modes
CLKIN/2 in CLKOR mode
CLKIN*128 in CLKG1 mode
CLKIN*256 in CLKG2 mode
F
Isinl128 for all modes
input frequency
I
Isin/128 = output data rate for CLKOR & CLKG1 = F
Isout
Isinl256 = output data rate for CLKG2 = F/2
Isout

Examples:

For Isin = 2.56 MHz at I
For Isin = 2.56 MHz at I

5 kHz: Magnitude is -2.74 dB
10kHz: Magnitude is -11.8 dB

Figure 3. CS5317 Low-Pass Filter Response

DS27F4

2-197

tIIIl.

...,......-- .......
..,..,~

~

..,~-

CS5317

Decimation

noise from the modulator. This will typically increase the converter's dynamic range to 88 dB.
Further bandlimiting the digital output to fsou/8
(2.5 kHz at full speed) will typically increase dynamic range to 90 dB.

Aliasing effects due to decimation are identical in
the CLKOR and CLKG 1 modes. Aliasing is different in the CLKG2 mode due to the difference
in output sample rates (10 kHz vs. 20 kHz) and
thus will be discussed separately.

Aliasing in the CLKG2 Mode

Aliasing effects in the CLKG2 mode can be modeled exactly as those in the CLKG 1 mode with
the output decimated by two (from 20 kHz to 10
kHz). This is most easily achieved by ignoring
every other sample. In the CLKG2 mode the ratio
of the output sampling rate to the filter's -3 dB
point is two, with no oversampling beyond the
demands of the Nyquist criterion. Without the
ability to roll-off substantially before fSou/2, the
on-chip digital filter's antialiasing value is diminished.

Aliasing in the CLKOR and CLKGl Modes

The delta-sigma modulator output is fed into the
digital low-pass filter at the input sampling rate,
fSin . The filter's frequency response is shown in
Figure 3. In the process of filtering the digitized
signal the filter decimates the sampling rate by
128 (that is, fSout = fSi.!128). In its most elementary form, decimation simply involves ignoring or selectively reading -a fraction of the available
samples.
In the process of decimation the output of the
digital filter is effectively resampled at fSout' the
output word rate, which has aliasing implications.
Residual signals after filtering at multiples of fSout
will alias into the baseband. For example, an input tone at 28 kHz will be attenuated by 39.9 dB.
If fSout =20 kHz, the residual tone will alias into
the baseband and appear at 8 kHz in the output
spectrum.

The CLKG2 mode should therefore be used only
when the output data rate must be minimized due
to communication and/or storage reasons. In addition, adequate analog filtering must be provided
prior to the AID converter.
Digital Design Considerations

The CS5317 presents its 16-bit serial output
MSB-first in 2's complement format. The converter's serial interface was designed to easily
interface to a wide variety of micro's and DSP's.
Appendix A offers several hardware interfaces to
industry-standard processors.

If the input signal contains a large amount of out-

of-band energy, additional analog and/or digital
anti alias filtering may be required. If digital postfiltering is used to augment the CS5317's
rejection above fSou/4 (that is, above 5 kHz), the
filtering will also reject residual quantization

f out

I"

~I

DOUT ----~1____~________________________________~r ~~

)~

CLKOUT
DATA

____

115 114 113112 111 110

I

9

I

8

I7 I

6

MSB

I

5

I

4

I

3

I

2

I

1

" 115 114

I

LSB

(sign bit)
Figure 4. Data Output

2-198

DS27F4

-._

..,......,..,..,.
......
.
....
..,.., .....
Data Output Characteristics & Coding Format
As shown in Figure 4, the CS5317 outputs its 16bit data word in a serial burst. The data appears at
the DATA pin on the rising edge of the same
CLKOUT cycle in which DOUT falls. Data
changes on the rising edge of CLKOUT, and can
be latched on the falling edge. The CLKOUT rate
is set by the CLKIN input (fclkin/2 in the CLKOR
mode· fclkin*128 in the CLKG1 mode; and
fclkin;256 in the CLKG2 mode). DOUT returns
high after the last bit is transmitted. After transmitting the sixteen data bits, DATA will remain
high until DOUT falls again, initiating the next
data output cycle.
A 3-state capability is available for bus-oriented
applications. The 3-state control input is termed
Data Output Enable, DOE, and is asynchronous
with respect to the rest of the CS5317. If DOE is
taken high at any time, even during a data burst,
the DATA, DOUT and CLKOUT pins go to a
high impedance state. Any data which would be
output while DOE is high is lost.
Power Supplies

Since the AID converter's output is digitally filtered in the CS5317, the device is more forgiving
and requires less attention than conventional 16bit AID converters to grounding and layout
arrangements. Still, care must be taken at the design and layout stages to apply the device
properly. The CS5317 provides separate analog
and digital power supply connections to isolate
digital noise from its analog circuitry. Each supply pin should be decoupled to its respective
ground, AGND or DGND. Decoupling should be
accomplished with 0.1 flF ceramic capacitors. If
significant low frequency noise is present in the
supplies, 10 flF tantalum capacitors are recommended in parallel with the 0.1 J.lF capacitors.
The positive digital power supply of the CS5317
must never exceed the positive analog supply by
more than a diode drop or the chip could be perDS27F4

CS5317

manently damaged. If the two supplies are derived from separate sources, care must be taken
that the analog supply comes up first at power-up.
Figure 1 shows a decoupling scheme which allows the CS5317 to be powered from a single set
of ± 5V rails. The digital supplies are derived
from the analog supplies through 10 Q resistors
to prevent the analog supply from dropping below
the digital supply.
PLL Characteristics
A phase-locked loop is included on the CS5317
and is used to generate the requisite high frequency AID sampling clock. A functional
diagram of the PLL is shown in Figure 5. The
PLL consists of a phase detector, a filter, a VCO
(voltage-controlled oscillator), and a counter/divider. The phase detector inputs are CLKIN (91)
and a sub-multiple of the VCO output signal (92).
The inputs to the phase detector are positive-edge
triggered and therefore the duty cycle of the
CLKIN signal is not significant. With this type of
phase detector, the lock range of the PLL is equal
to the capture range and is independent of the low
pass filter. The output of the phase detector is input to an external low pass filter. The filter
characteristics are used to determine the transient
response of the loop. The output voltage from the
filter functions as the input control voltage to the
VCO. The output of the VCO is then divided in
frequency to provide an input to the phase detector. The clock divider ratio is a function of the
PLL mode which has been selected.
Phase Detector Gain (Kd)
A properly designed and operating phase-locked
loop can be described using steady state linear
analysis. Once in frequency lock, any phase difference between the two inputs to the phase
detector cause a current output from the detector
during the phase error. While either the +50 IlA
or the -50 IlA current source may be turned on,
the average current flow is:
2-199

~,'"

E".-

.._..........
.......
..............

_

CS5317

the phase detector. The binary counter/divider ratio sets the ratio of the VCO frequency to the
CLKIN frequency. As illustrated in Figure 5, the.
VCO output is always divided by two to yield the
CLKOUT signal which is identical in frequency
to the delta-sigma modulator sampling clock.
The CLKOUT signal is then further divided by
either 128 in the CLKG 1 mode or by 256 in the
CLKG2 mode. When the divide by two stage is
included, the divider ratio (N) for the PLL in the
CLKG 1 mode is effectively 256. In the CLKG2
mode the divider ratio (N) is 512.

ioulavg = Kd(91-92) "" (-50/J.Al21t) (91-Eh)
where 91 is the phase of INl, 92 is the phase of
IN2 and Kd is the phase detector gain. The factor
21t comes from averaging the current over a full
CLKIN cycle. Kd is in units of micro-amperes/radian.
VCO Gain (Ko)

The output frequency from the VCO ranges from
1.28 MHz to 5.12 MHz. The frequency is a function of the control voltage input to the VCO. The
VCO has a negative gain factor, meaning that as
the control voltage increases more positively the
output frequency decreases. The :gain factor units
are Megaradians per Volt per .Second. This is
equivalent to 21t Megahertz per volt. Changes in
output frequency are given by:

Loop Transfer Function

As the phase-locked loop is a closed loop system,
an equation can be determined which describes its
closed loop response. Using the gain factors for
the phase detector and the VCO, the filter arrangement and the counter/divider constant N,
analysis will yield the following equation which
describes the transfer function of the PLL:

ilOlvco =Ko ilVCOin TKo is typo -lOMrad/Vs.]
CounterlDivider Ratio

KoKdR
KoKd
N
s+ NC

The CS5317 PLL Iilultiplies the CLKIN rate by
an integer value .. To set the multiplication rate, a
counter/divider chain is used to divide the VCO
output frequency to develop a clock whose frequency is compared to the CLKIN frequency in
+5V
Kd

e---'--i IN1

O--____

ClKlN

= -8 IJAIrad
DOWN

Iso
'f

Phase/Frequency
Detect logic
IN2

UP

I
IIA I

2

s +

~

~ =f= C

I

I C:2
I PHDT

R

VCOIN

f50""l - - _. -

KoKdR
KoKd
N
s+ NC

I External RC
I
I

I
I
Ko = -10 MradN.s

Delta-Sigma
Sampling Clock
(ClKOUT)

J

-sv

Conversion Output Rate Same Frequency as DOUT

Internal Sync for Digital Filter

Figure 5. PLL Functional Diagram
2-200

DS27F4

.. ...
......-..
-. ..--_
~-

~~

CS5317

~~

This equation may be rewritten such that its elements
correspond
with
the
following
characteristic form in which the damping factor,
~, and the natural frequency, COn , are evident:
2~COns + COn

82

The equations used to describe the PLL and the
3 dB bandwidth are valid only if the frequency of
CLKIN is approximately 20 times greater than
the 3 dB comer frequency of the control loop.
Filter Components

2

8t = s2 + 2~COns + COn 2
Both the natural frequency and the damping factor are particularly important in determining the
transient response of the phase-locked loop when
sUbjected to a step input of phase or frequency. A
family of curves are illustrated in Figure 6 that
indicate the overshoot and stability of the loop as
a function of the damping factor. Each response is
plotted as a function of the normalized time, COn t.
For a given ~ and lock time, t, the COn required
can be determined. Altematively, phase lock controlloop bandwidth may be a specified parameter.
In some systems it may be desirable to reduce the
-3dB bandwidth of the PLL control loop to reduce the effects of jitter in the phase of the input
clock. The 3 dB bandwidth of the PLL control
loop is defined by the following equation:

Using the equations which describe the transfer
function of the PLL system, the following external filter component equations can be determined:
C _ KoKd
- NCOn 2
N
R = 2~COn KoKd

The gain factors (Ko, Kd) are specified in the
Analog Characteristics table. In the event the system calls for very low bandwidth, hence a
corresponding reduction in loop gain, the phase
detector gain factor Kd can be reduced. A large
series resistor (Rl) can be inserted between the
output of the detector and the filter. Then the
50 IlA current sources will saturate to the supplies
and yield the following gain factor:

-5V
Kd",-2nRl
02 normalized to 01
4

1;= 0.5

1.3

I:::::'fo ~ ~

1.2

1.1

0.8

0.7
0.6
0.5
0.4

3

1;=0.6

2

r (/!J.fY/

If//I&

I

1;=0.9

·1
-2

1;= 1.0

-3

1;= 1.5

-4

~

."

0.2

1;= 10.0

-9

-10
2345678

Oln t.

Figure 6a. 82 Unit Step Response

9

10

10

['\

1\

\\ h\'\
.'1 \\\ ~\ 1\
l\' \\

-8

0.0

'\

III I I

I;

Lm l\\

-7

0.1

~ f;:::---..
~ ,'\
~~
~\\\

I

\\
l@ 1\1\

-6

1;=3.0

DS27F4

l\

-5

1;';'2.0

0.3

o

&~

0

1;=0.8

1;= 10.0

1111

I; =0.5

1

1;=0.7

1.0
0.9

/;=0.5

1\ 1\ i\'
0.1

10

roIOln

Figure 6b. Second Order PLL Frequency Response
2-201

..-I!
~

..........-.._.
.....~

.",

~~

~
~~

In some applications addition~ filtering may be
useful to eliminate any jitter associated with the
discrete current pulses from the phase detector.
In this case a capacitor whose value is no more
than 0.1 C can be placed across the RC filter network (C2 in Figure 5).

CS5317

To calculate values for the resistor R and capacitor C of the filter, we must first derive a value for
ron. Using the general rule that the sample clock
should be at least 20 times higher frequency than
the 3dB bandwidth of the PLL control loop:
CLKIN ;;::: 20 ro3dB

Filter Design Example
The following is a step by step example of how to
derive the loop filter components. The CS5317
NO sampling clock is to be derived from a 9600
Hz clock source. The application requires the signal passband of the CS5317 to be 4 kHz. The
on-chip digital filter of the CS5317 has a 3 dB
passband of CLKOUT/488.65 (see Note 4 in the
data sheet specifications tables). The 4 kHz passband requirement dictates that the sample clock
(CLKOUT) of the CS5317 be a minimum of
4000 X 488.65 = 1.954 MHz. This requires the
VCO to run at 3.908 MHz. The 3.908 MHz rate is
407 times greater than the 9600 Hz PLL input
clock. Therefore the CS5317 must be set up in
mode CLKG2 with N = 512. lfthe CLKGl mode
were used (N =256), too narrow of a signal bandwidth through the NO would result.
Once the operating mode has been determined
from the system requirements, a value for the
damping factor must be chosen. Figure 6 illustrates the dynamic aspects of the system with a
given damping factor. Damping factor is generally chosen to be between 0.5 and 2.0. The choice
of 0.5 will result in an overshoot of 30 % to a step
response whereas the choice of 2.0 will result in
an overshoot of less than 5 %. For example purposes, let us use a damping factor of 1.0.
So, let us begin with the following variables:
Ko =- 10 Mradians/volt.sec
Kd =- 8 IlNradian
N= 512
~ =1.0

2-202

where CLKIN = 9600 Hz = 21t 9600 radians/sec.
So: ro3dB = 21t 9600120 = 3016 radians/sec.
Knowing ro3dB and the damping factor of 1.0, we
can calculate the natural frequency, ron, of the
control loop:

ron = Ol3dB~2~2 + I + ~(2~2 + 1)2 + 1
ron = 3016 ~2(1)2 + 1 + ~(2(1)2 + 1)2 + 1
ron = 1215

Usec

Once the natural frequency, ron , is determined,
values for R and C for the loop filter can be calculated:
R = 2~OlnNlKoKd
R =2(1)(1215 lis) 512/(-lOMradlv.s.)(-8 IlNrad)
R = 15552 viA = 15.55 kil.

Use R = 15 kil.

C

=KoKdlNron2

C

=(-10 Mradlv.s)(- 81lNrad)/512 (1215 lIs)2

C =105.8 x 10 -9 A.s/v

=105 nP.

Use 0.1 j.lF.

The above example assumed typical values for
Ko and Kd. Your application may require a worst
case analysis which includes the minimum or
maximum values. Table 2 shows some other example situations and R and C values.
DS27F4

.-...... ...
.....-..
~

~~

~--

CS5317

~~

ClKIN

ClKOUT

(Hz)

Mode

N

(MHz)

1:

roadB

7200
9600
14400
19200

CLKG2
CLKG2
CLKG1
CLKG1

512
512
256
256

1.8432
2.4576
1.8432
2.4576

1.0
1.0
1.0
1.0

2262
3016
4524
6032

ron
911
1215
1822
2430

R * (k.Q\
11.6
15.5
11.6
15.5

C * (nF\

187
106
94
52

• The values for Rand C are as calculated using the described method. Component tolerances have
not been allowed for. Notice that Ko and Kd can vary over a wide range, so using tight tolerances
for Rand C is not justified. Use the nearest conveniently available value.

Table 2 Example PLL Loop Filter Rand C values

CS5317 PERFORMANCE
The CS5317 features 100% tested dynamic performance. The following section is included to
illustrate the test method used for the CS5317.

FFT Tests and Windowing
The CS5317 is tested using Fast Fourier Transform (FFT) techniques to analyze the converter's
dynamic performance. A pure sine wave is applied to the CS5317 and a "time record" of 1024
samples is captured and processed. The FFT algorithm analyzes the spectral content of the digital
waveform and distributes its energy among 512
"frequency bins". Assuming an ideal sinewave,
distribution of energy in bins outside of the fundamental and dc can only be due to quantization
effects and errors in the CS5317.
If sampling is not synchronized to the input sine-

wave it is highly unlikely that the time record will
contain an exact integer number of periods of the
input signal. However, the FFT assumes that the
signal is periodic, and will calculate the spectrum
of a signal that appears to have large discontinuities, thereby yielding a severely distorted
spectrum. To avoid this problem, the time record
is multiplied by a window function prior to performing the FFT. The window function smoothly
forces the endpoints of the time record to zero,
removing the discontinuities. The effect of the
"window" in the frequency domain is to convolute the spectrum of the window with that of the
actual input.
DS27F4

The quality of the window used for harmonic
analysis is typically judged by its highest sidelobe level. The Blackman-Harris window used to
test the CS5317 has a maximum side-lobe level of
-92 dB.
Figure 7 shows an FFT plot of a typical CS5317
with a 1 kHz sinewave input generated by an "ultra-pure" sine wave generator and the output
multiplied by a Blackman-Harris window. Artifacts of windowing are discarded from the
signal-to-noise calculation using the assumption
that quantization noise is white. All FFT plots in
this data sheet were derived by averaging the FFT
results from ten time records. This filters the
spectral variability that can arise from capturing
finite time records, without disturbing the total
energy outside the fundamental. All harmonics
and the -92 dB side-lobes from the BlackmanHarris window are therefore clearly visible in the
plots.
OdB
·20dB

- - - - - - - - - - Sampling Rate: 19.2 kHz
- - - - - - - Full Scale:
± 2.75 V
__________ Sl(N+D):81.39dB

·40dB
·6QdB
Signal

Amplitude
Relative to
Full Scale

·8OdS
·1QOdB
·120dS

Input Frequency

Figure 7. CS5317 Dynamic Performance

2-203

..............
.,,--_._.
..............

CS5317

Full - scale signal - to - noise - plus - distortion
[S/(N+D)] is calculated as the ratio of the rms
power of the fundamental to the sum of the rms
power of the FFf's other frequency bins, which
include both noise and distortion. For the
CS5317, signal-to-noise-plus-distortion is shown
to be better than 81 dB for an input frequency
range of 0 to 9.6 kHz (fs/2).

OdB
- - - - - - - - -

S/I,M,D,:B4,7dB

·2OdB
-4OdB
-aOdB

Signal
Amplitude
Relative to
Full Scale

·BOdB

·10OdB
·12OdB

Harmonic distortion characteristics of the CS5317
are excellent at 80 dB full scale signal to THD
(typical), as are intermodulation distortion characteristics, shown in Figure 8. Intermodulation
distortion results from the' modulation distortion
of two or more input frequencies by a non-linear
transfer function.

de BOO

9600

1450
Input Frequency (Hz)

Figure 8. CS5317 Intermodulation Distortion

The plot below illustrates the typical DNL performance of the CS5317, and clearly shows the
part easily achieves no missing codes.

DNLTest
Figure 9 shows a plot of the typical differential
non-linearity (DNL) of the CS5317. This test is
done by taking a large number of conversion results, and counting the occurrences of each code.
A perfect AID converter would have all codes of
equal size and therefore equal numbers of occurrences. In the DNL test, a code with the average
number of occurrences is considered ideal and
plotted as DNL = 0 LSB. A code with more or
less occurrences than average will appear as a
DNL of greater than or less than zero. A missing
code has zero occurrences, and will appear as a
DNL of -1 LSB.

Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your

+1

+1/2

iii'

en

o

d-

-l

Z

o

.112

·1

0

32,768

65.535

Codes

Figure 9. CS5317 DNL Plot
2-204

DS27F4

_...................
_-...-..
.-

.."

PIN DESCRIPTIONS

CS5317
(Pin numbers refer to the IS-pin DIP package)

18 pin DIP Pinout
POSITIVE ANALOG POWER
VA+
POSITIVE DIGITAL POWER
VD+
DATA OUTPUT ENABLE
DOE
DIGITAL GROUND
DGND
SERIAL CLOCK OUTPUT CLKOUT
SERIAL DATA OUTPUT
DATA
CLOCKING MODE SELECT
MODE
DATA OUTPUT READY
DOUT
CLOCK INPUT
ClKIN

•
VCOIN
PHDT
RST
AGND
VANC
REFBUF
AIN
VD-

VCOINPUT
PHASE DETECT
RESET
ANALOG GROUND
NEGATIVE ANALOG POWER
NO CONNECT
POSITIVE REFERENCE BUFFER
ANALOG INPUT
NEGATIVE DIGITAL POWER

20 pin SOIC pinout
POSITIVE ANALOG POWER
VA+
POSITIVE DIGITAL POWER
VD+
DATA OUTPUT ENABLE
DOE
DIGITAL GROUND DGND
NO CONNECT
NC
SERIAL CLOCK OUTPUT ClKOUT
SERIAL DATA OUTPUT
DATA
CLOCKING MODE SELECT MODE
DATA OUTPUT READY
DOUT
CLOCK INPUT ClKIN

VCOIN
PHDT
RST
AGND
NC
NC
VAREFBUF
AIN
VD-

VCOINPUT
PHASE DETECT
RESET
ANALOG GROUND
NO CONNECT
NO CONNECT
NEGATIVE ANALOG POWER
POSITIVE REFERENCE BUFFER
ANALOG INPUT
NEGATIVE DIGITAL POWER

Power Supplies
VD+ - Positive Digital Power, PIN 2.
Positive digital supply voltage. Nominally 5 volts.
VD- - Negative Digital Power, PIN 10.
Negative digital supply voltage. Nominally -5 volts.
DGND - Digital Ground, PIN 4.
Digital ground reference.
VA+ - Positive Analog Power, PIN 1.
Positive analog supply voltage. Nominally 5 volts.
VA- - Negative Analog Power, PIN 14.
Negative analog supply voltage. Nominally -5 volts.
AGND - Analog Ground, PIN 15.
Analog ground reference.
PLUClock Generator
CLKIN - Clock Input, PIN 9.
Clock input for both clock generation modes and the clock override mode (see MODE).
DS27F4

2-205

.- .........
....,,-._..
.............

CS5317

MODE - Mode Set, PIN 7.
Detennines the internal clocking mode utilized by the CSS317. Connect to +SV to select
CLKG 1 mode. Connect to DGND to select CLKG2 mode. Connect to -SV to select CLKOR
mode. This pin becomes equivalent to FSYNC in the CSZS316 compatible mode.

VCOIN - VCO Input, PIN 18.
This pin is typically connected to PHDT. A capacitor and resistor in series connected between
VA+ and this pin sets the filter response of the on-chip phase locked loop.

PHDT - Phase Detect, PIN 17.
This pin is typically connected to VCOIN. A capacitor and resistor in series connected between
VA+ and this pin sets the filter response of the on-chip phase locked loop.

Inputs
AIN - Analog Input, PIN 11.
DOE - Data Output Enable, PIN 3.
Three-state control for serial output interface. When low, DATA, DOUT, and CLKOUT are
active. When high, they are in a high impedance state.

RST - Sample Clock Reset,. PIN 16.
Sets phase of CLKOUT. Functions only in the clock override mode, CLKOR. Used to
synchronize the output samples of multiple CSS317's. Must be kept high in CLKG 1 or CLKG2
modes. Also, tying this pin low, with MODE not tied to - SY, will place the CSS317 into
CSZS316 compatible mode.

Outputs
DOUT - Data Output Flag, PIN 8.
The falling edge indicates the start of serial data output on the DATA pin. The rising edge
indicates the end of serial data output.

DATA - Data Output, PIN 6.
Serial data output pin. Converted data is clocked out on this pin by the rising edge of CLKOUT.
Data is sent MSB first in two's complement fonnat.

CLKOUT - Data Output Clock, PIN 5.
Serial data output clock. Data is clocked out on the rising edge of this pin. The falling edge
should be used to latch data. Since CLKOUT is a free running clock, DOUT can be used to
indicate valid data.

REFBUF - Positive Voltage Reference Noise Buffer, PIN 12.
Used to attenuate noise on the internal positive voltage reference. Must be connected to the
analog ground through a O.l~ ceramic capacitor.

2-206

DS27F4

_. ...,-__.. ....-.-.
""'.- ""''''''-

CS5317

PARAMETER DEFINITIONS
Resolution - The number of different output codes possible. Expressed as N, where 2N is the number
of available output codes.
Dynamic Range - The ratio of the largest allowable input signal to the noise floor.
Total Harmonic Distortion - The ratio of the rms sum of all harmonics to the rms value of the largest
allowable input signal. Units in dB's.
Signal to Intermodulation Distortion - The ratio of the rms sum of two input signals to the rms sum
of all discernible intermodulation and harmonic distortion products.
Linearity Error - The deviation of a code from a straight line passing through the endpoints of the
transfer function after zero- and full-scale errors have been accounted for. "Zero-scale" is a
point 112 LSB below the first code transition and "full-scale" is a point 1/2 LSB beyond the
code transition to all ones. The deviation is measured from the middle of each particular code.
Units in %FS.
Differential Nonlinearity - The deviation of a code's width from the ideal width. Units in LSB's.
Positive Full Scale Error - The deviation of the last code transition from the ideal, (VREF - 3/2 LSB).
Units in mY.
Positive Full Scale Drift - The drift in effective, positive, full-scale input voltage with temperature.
Negative Full Scale Error - The deviation of the first code transition from the ideal, (-VREF + 112
LSB). Units in mY.
Negative Full Scale Drift - The drift in effective, negative, full-scale input voltage with temperature.
Bipolar Offset - The deviation of the mid-scale transition from the ideal. The ideal is defined as the
middle transition lying on a straight line between actual positive full-scale and actual negative
full-scale.
Bipolar Offset Drift - The drift in the bipolar offset error with temperature.
Absolute Group Delay - The delay through the filter section of the part.
Passband Frequency - The upper -3 dB frequency of the CS5317.

DS27F4

2-207

_

- ......._.
..,.
............
..,,-...

..,

CS5317

ORDERING GUIDE
Model Number
eS5317-KP
eS5317-KS

2-208

Temperature Range

o
o

to 70 0 e
to 70 0 e

Package
18 Pin Plastic DIP
20 Pin Plastic sOle

DS27F4

.. ......-. ...,,--_.-.
~-

~~

CS5317

~~

APPENDIX A

Figure Al shows one method of converting the
serial output of the CS53I7 into I6-bit, parallel
words. The associated timing is also shown.

APPLICATIONS

CS5317
DATA

A

'"'"
~

81

:J:

....
....

82

PA
PB

DO

Pc

D2

Po
PE
PF
PG

D3

PH

<4-i

D1

D4
D5
D6
D7

Data

Bus

OE1

+5V
C8

OE1 PA
PB

A

'"'"
~

:J:

I:!

81
82

D

SET

D8
D9

Pc
Po
PE
PF
PG

D10

PH

D15

Q

D11
D12
D13
D14

- - - - - - - - - - - - - - -

D

INT:

Q~-----------------D INT'
, On!Y needed for level sensitive interrupt. driven systems.. _ _ _ _ _

CLKOUT

UULJU···

DOUT

DATA

~

... ~

(M8B)
INT
INT Cleared when data read
(CS goes low)

Figure A1. CSS317-to-Parallel Data Bus Interface

DS27F4

2-209

,

fill

.

....
...,..,,--_._.
.............
..,..,~

CS5317

Figure A2 shows the interconnection and timing
details for connecting a CS5317 to a NEC
J.lPD7730 DSP chip,

Figure A3 shows the interconnection and timing
details for connecting a CS531 T to a Motorola
DSP 56000,

CS5317
Status Register (SR)
Bit Mnemonic Setting Meaning
SCI
0
External Clock
9
7,6
SDLI
1,0 16 bit data
SIF
0
MSB First
3

IlPD77230

CLKOUT r - - - SICK
-DOUT r - - - SIEN
DATA r - - - SI

CLKOUT

DOUT
DATA

13---~

'-----_ _n _ _-----''-----_

(MSB)

Figure A2. CS5317-to-NEC IlPD77230 Serial Interface

SSI Control Reg. A
CRA (X:FFEC)
WL1 = 1 } 16 b't
WLO=O
IS

SYNC ASYNC
SCO
CLKOUT SCK
SC2
SC1
PINS DOUT
0
GCK
0
r::o
0,8'
SYN
1
0
CIlw
a:u. FSL
0
0
-u.
0 .. SCKD
0
!::><
c:
0r::o SCD2
0
0a:
0
SCD1
0
00
en
SCDO
0
-

-

~

CS5317
CLKOUT
DOUT
DATA

DSP56000

K>-

SCK, SCO
SC2, SC1
SRD

-

CLKOUT

DOUT

DATA

,,_1_3_---

'-----_---'L-_ _ _

~

Figure A3. CS5317-to-Motorola DSP56000 Serial Interface
2-210

DS27F4

. ...".,-- ...
...-.
*-'. . . . .~~-•

...,

CS5317

~~

Figure A4 shows the interconnection and timing
details for connecting a CS5317 to a WE DSP16
DSP chip.
Serial 110 Control Register (SIOC)
Field Value Meaning
1
MSB
MSB input first
ILD
ILD is an input
0
ICK
0
ICK is an input
ILEN
0
16 bit input data

Figure A5 shows the interconnection and timing
details for connecting a CS5317 with TMS32020
and TMS320C25 DSP chips.

CS5317

DSP16

CLKOUT f------1~-1

ICK

DOUT 1 - - + - - - - - - - - - 1 ILD
DATA

13

•••

DI

2

Figure A4. CS5317·to·WE DSP16 Serial Interface

TMS32020
CS5317

TMS320C25

TMS32020 Status Register (ST1):

=0 (16 bit data)

CLKOUT

TMS320C25 Status Register (ST1):
FO 0 (16 bit data)

DOUT

FSR

DATA

DR

FO

--

=

FSM

=1 (Frame Sync used)

CLKR

CLKOUT

DOUT

DATA

13

2

(MSB)

Figure A5. CS5317·to·TMS32020ffMS320C25 Serial Interface

DS27F4

2·211

........
-..........
.....
.......
~

~~

CDB5317

Semiconductor Corporation

CDS5317 Evaluation Soard
Features

General Description

• Easy to Use Digitallnteriace
Para"el 16 Bits With Clock
Serial Output With Clock

The CDB5317 Evaluation Board is designed to allow the
user to quickly evaluate performance of the CS5317
Delta-Sigma Analogcto-Digital Converter. All that is required to use this board is an external power supply, a
signal source, a clock source, and an ability to read
either serial or parallel 16 bit data words.

• Multiple Operating Modes
Including Two PLL Modes
• IDC Header used to access Para"el
Data, Serial Data, and Clock Input and
Output

AIN

ClKIN

~

r,-;

ORDERING INFORMATION: CDB5317

Vl

+5V GND -5V

~
ClKIN

ClKOUT

J

CS5317

I

I DATA

J SERIAL TO PARAllEL
CONVERTER

1

I

--

DRDY
DACK

IDCHEADER

1

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

,

00-015

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS27DB3

2-212

.-_
..--_._.
__.._-_
...-.
GENERAL DESCRIPTION
The CDB5317 Evaluation Board is a stand-alone
environment for easy lab evaluation of the
CS5317 Delta-Sigma Analog-to-Digital Converter.
Included on the board is a serial-to-parallel converter. The user can access output data in either
parallel or serial form. When supplied with the
necessary +5 V and -5 V power supplies, a
CLKIN signal, and an analog signal source, the
CDB5317 will provide converted data at the 40
pin header.
SUGGESTED EVALUATION METHOD
An efficient evaluation of the CS5317 using the
CDB5317 may be accomplished as described below.
The following equipment will be required for the
evaluation:
• The CDB5317 Evaluation Board.
• A power supply capable of supplying +5V and
-5V.

• A clock source as the CLKIN signal of the
CS53 17.
• A spectrally pure sine wave generator such as
the Krohn-Hite Model 4400A "Ultra-Low Distortion Oscillator" .
• A PC equipped with a digital data acquisition
board such as the Metrabyte Model PIOl2 "24 Bit
Parallel Digital I/O Interface".
• A software routine to collect the data and perform a Fast Fourier Transform (FFT).
The evaluation board includes filter components
for the on-chip phase locked loop. The components are adequate for testing if the CLKIN signal
has little or no phase-jitter. If the CDB5317 board
is being tested as part of a system which generates
a CLKIN which contains jitter, the PLL filter
components may need to be optimized for your
system (see the CS5317 data sheet).

CDB5317

Set-up for evaluation is straightforward. First decide the operating mode and place the jumper on
the board for the proper selection. Then decide
whether the filter components for the phase
locked loop are adequate or whether they should
be changed for your evaluation. The PLL will
lock on a steady clock input with the filter as it is.
Connect the necessary 5 V (CMOS compatible)
CLKIN signal for the application. Use the sinewave generator to supply the analog signal to the
CDB5317. Apply the analog input and CLKIN
signals only when the evaluation board is powered
up. Converted data will then appear at the header
on the CDB5317. The header should be connected
to the digital data acquisition board in the PC
through an IDC 40 pin connector and cable. The
software routine should collect the data from the
CDB5317 and run a standard 1024 point Fast
Fourier Transform (FFT). Such an analysis results
in a plot similar to Figure 1. This plot resulted
from using a 1kHz input signal and a BlackmanHarris window for the FFT.
The signal to noise and signal to total harmonic
distortion characteristics of the CS5317 may be
easily measured in this way. The signal to total
harmonic distortion value for a particular input is
the ratio of the RMS value of the input signal and
the sum of the RMS values of the harmonics
shown in the diagram. The dynamic range of the
CS5317 can be measured by reducing the input
OdB , - - - - - - - . - - - - - - - - - - - - - - - - - ,
- - - - - - - - - Sampling Rate: 19.2 kHz
-20dB
- - - - - - - - - Full Scale: ± 2.75 V
_ _ _ _ _ _
_ _ S/(N+D): Bl.39 dB
-40dB
Signal
Amplitude

~~llr~~:I~O

-60dB
-BOdB
-100dB
-12OdB

Input Frequency

Figure 1. FFT Plot Example
DS27DB3

2-213

,
. ' ,..

--------,.,-- -----------

CDB5317,

amplitude so that distortion products become negligible. This allows an accurate measurement of
the noise floor.

are supplied on the board to connect the +5, -5,
and ground power lines. A good quality low ripple, low noise supply will give the best
performance. The +5 V supply can also be used
for VL and should be connected between the VL
board jack and the power supply, as opposed to
connecting the VL jack straight to the +5V jack.
The +5V jack is the positive power source for the
CS5317 IC whereas the VL jack supplies power
to all the digital ICs. Care should be taken that
noise is not coupled between VL and +5V; however, supply noise is generally not a problem with
the CS5317 since the on-chip decimation filter
will remove any interference outside of its passband. The +5 and -5 V supply lines are filtered on

More complex analysis such as intermodulation
distortion measurements can be accomplished
with the addition of another sine-wave generator.

CIRCUIT DESCRIPTION
Figure 2 illustrates the CS5317 AID converter IC
circuit connections. The chip operates off of ±5Y.
These voltages are supplied from a power source
external to the evaluation board. Binding posts

TP6

R7
10

TP10

+5V~~~~~~~----~~~~----~'-VVv-~----~~--~~~
6.8v

ClKIN~

R2
200

TP8

17
PHDT
18
VCOIN
9

DOE
8
DOUT t---=-*---------jf- DOUT (fig. 3)
5
ClKOUT t---=------'-o-C>-o-If- ClKOUT (fig. 3)
t---=------.....-----o-C>-o-If- DATA (fig. 3)

elKIN

R1*
51
AIN

11

10 k
AIN

12 REFBUF

VA-

-5V,

@__--+____.....__--4-________r----------~1"'4~
* Remove for logic gate CLKIN source

R8
10

Figure 2. Analog-to-Digital Converter

2-214

DS27DB3

.._-_.-_..--_._.
__
...-.

CDB5317

the board and then connected to the VA+ and VAsupply pins of the chip. The +5 V and -5V are
then connected by means of ten Q resistors to the
VD+ and VD- pins respectively. Capacitive filtering is provided on all supply pins of the chip. In
addition there is a 0.1 J1F filter capacitor connected from the REFBUF pin of the chip to the
VA- supply pin.

to the phase detector of the on-chip phase locked
loop of the CS5317.

To properly operate, the CS5317 chip requires an
external (5 V CMOS compatible) clock. A BNC
connector labeled CLKIN is provided to connect
the off-board clock signal to the board. The
CLKIN signal is also available on the 40 pin
header connector. The CLKIN signal is one input

, - - - - - - - - - - - - - - - - - - - - - - - - DOUT2
(fig. 6)

us

:J
C1

C10
0.1 !iF
TP2

:::r: 0.1 !iF

2
3

DOUT
(fig. 2)

':>o.=.t'*-----'~

D U4 Q
74HC74

0------- DRDY

CL

(fig. 6)

Q

7

CLKOUT ~4
UNUSED GATES

~1--~-S------6--~>-------------------

(fig. 2)

CLKOUT
(fig. 6)

VL

L-______________________
DATA
(fig. 2)

--,nJ> 10 i 9

L

_~
~

CLKOUT2
(fig. 6)
DATA 1
(fig. 6)
DATA
(fig. 6)

Figure 3. Buffers and Parallel Handshake Flip-Flop

DS27DB3

-i

Header connector P2 (see Figure 2) is provided to
allow mode selection for the CS5317 chip. The
mode selection works together with the CLKIN
signal to set the sample rate and the output word
rate of the CS5317. See the CS5317 data sheet
for details on mode selection. Two of the available modes (CLKG 1 and CLKG2) utilize the
on-chip phase locked loop to step up the CLKIN
frequency to obtain the necessary sample rate
clock for the AID converter. Another mode (the
CLKOR mode) does not use the on-chip PLL but
instead drives the sample function directly. The

2-215

L

._.-.
_.-_..--_-.._-_
...

CDB5317

CLKOUT
DATA

115

I 14

113 112 111 110

I9 IB I7 I6 I5 I4 I3 I2 I 1 I0

DOUT~~------------------------------------~
Note: For a complete description of serial timing see the CS5317 Data Sheet

Figure 4 Serial Data Timing

two modes which use the phase locked loop will
require appropriate low pass filter components on
the Evaluation Board. The low pass filter components help determine the PLL control loop
response, including its bandwidth and stability
and therefore directly affect the transient response
of the PLL control loop. Appropriate filter components should be installed if a particular dynamic
response to changes of the CLKIN signal is desired.
The filter components which are installed on the
board have been chosen for the following parameters: MODE: CLKG2; CLKIN: 7,200; N=512;
damping factor: 1.0; Control loop -3 dB bandwidth: 2262 radians/second. These parameters
yield R as 10 k Q and C as 0.22 IJF for the filter
components.

Serial Data
Shffting Out

The analog signal to be digitized is input to the
AlN BNC connector. The digital output words
from the CS5317 are buffered by HEX inverters
as shown in Figure 3. The buffered versions of
the CLKOUT and DATA signals are available on
the header connector PI in Figure 6. The serial
data signals out of the CS5317 are illustrated in
Figure 4. If remote control of the DOE line is
desired, the trace on the PC Board can be opened
and a wire connection can be soldered to the DOE
input line. Remote control of the RST line of the
CS5317 is also available if desired.
Figures 5 and 6 illustrate the serial to parallel shift
registers including timing information. The DATA
output signal from the CS5317 is input to the data
input of the shift register. An inverted version of
the CLKOUT signal is used to clock the DATA
into the shift registers. The two 8-bit shift register
ICs also include output latches. The rising edge

Serial Data
Shifting out

Parallel Data (00·015) Valid

Parallel Data Valid

( \ (~_ _ _ _ _ _ _ _~A~_ _ _ _ _~\ ( \ (_------~"---

DATA

- - - - -mmmrn - - - - - - - - - - - - - - - - - - - - - - - - ]]]]]]]]]]J

LJ

DOUT

DRDY

DACK

---- ----- -- ----

i

I

____-_-_-_-_-_-_-_-_-_-_-_-_-_-_'___----'n ---------------:
~

Figure 5. Parallel Data Timing

2-216

DS27DB3

_-_

-_..--..
.
._
._.
-- ...-

CDB5317

of the DOUT signal from the CS5317 is used to
latch the data once it is input to the shift registers.
The rising edge of DOUT is also used to toggle
the DRDY flip flop (see Figure 3). The flip flop
is used to signal a remote device whenever new

data is latched into the output registers. The
DRDY flip flop is reset whenever DACK occurs.
A component layout of the CDB5317 board is illustrated in Figure 7.

CLKIN
(fig. 2)
CLKOUT2
(fig. 3)
VL

TP4

.

P1

- - -

, CLKIN

~C2

l

ra

, CLKOUT
TO.1I!F
16

RST

DATA1 (fig. 3)

OH
74HC595

TP5

OG
OF

U2

OE
12 LATCH CLK

00
OC

11 SHIFTCLK

~

DIN

OB

OA
GND OE

8~

6

, 014

5

, 013

4

, 012

3

, 011

2

, 010

1

, 09

15

, 08

T13

~= R3
10k

~C3

9

, 015

7

VL

'--

, DATA

1

[10" 16 TO.1I!F
RST
OH r2- r----DOUT
OG
74HC595

U3
DOUT2
(fig. 3)

12

CLKOUT
(fig. 3)
DATA
(fig. 2)

11 SHIFTCLK

LATCHCLK

14 DIN

OF
OE

6

5
4

00 3
OC 2
OB

1

OA

15

~8

L

11 :

~J

_ _ DACK~
_DACK

GND

DRDY

DACK
(fig. 3)

DRD~~
(fig. 3)

Figure 6.

DS27DB3

2-217

~,~,
~

----------------------

CDB5317

elKIN
TPI

DGNIl

AGND

R8

Clg-CI

-5V

Or
Or=

CIS

TP9

RII

CI4

II

1

1
1
1

RIO

I1

1 f CRYSTAL
1 S*mlconductor COrporatIon
1
SMART Ana/og@

1
1
FILTER
1
l.,£o!!!,C!!!E.!rr'L 1

~II
II

1
1
1

'0 '

+5V

03

'~

". 1

R9

--I

17

CDB5317
EvaluatIon BbardJ

AIN

Figure 7. Bird's Eye View

2-218

DS27DB3

.......
....... ,...
..............
~

~

ICS5321 I

Semiconductor Corporation

High Dynamic Range Delta-Sigma Modulator
Features

Description
The CS5321 is a high dynamic range, fourth-order
delta-sigma modulator intended for geophysical and
sonar applications. Used in combination with the
CS5322 digital FIR filter, a unique high resolution AID
system results.

• Delta-Sigma Architecture
- Fourth-Order Modulator
- Variable Sample Rate
- Internal Track-and-Hold Amplifier

The CS5321 provides an oversampled serial bit stream
at 256 kbits per second (HBR=1) and 128 kbits per
second (HBR=O) operating with a clock rate of 1.024
MHz.

• Clock Jitter Tolerant Architecture
• Dynamic Range
- 121 dB @ 411 Hz Bandwidth
- 118 dB @ 822 Hz Bandwidth

The monolithic CMOS design of the CS5321 insures
high reliability while minimizing power dissipation.
The CS5321 can be operated in two power modes. In
Normal mode (LPWR=O) power dissipation is 55 mW.
In Low Power mode (LPWR=1) power dissipation is 30
mW.

• Signal-to-Distortion: 115 dB
• Input Range: ± 4.5V
• Improved offset drift, gain drift, and
clock jitter immunity over CS5323

ORDERING INFORMATION:
CS5321-BL

Vdd1

V ss1 AGND

Vdd2

-55°C to +85°C

28-pin PLCC

V ss2 DGND
Digital

LPWR

Control

OFST
MFLG

AINR
AIN+
AIN-

S
HBR
Clock
Generation

MCLK
MSYNC

~~--------~~MDATA

D/A

~----------~

MDATA

VREF+ 0 - - - - - - - - - - - - - '
VREF-

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS88F3

2-219

. .......

........

.., ..,........
~

~~

~~

CS5321

ANALOG CHARACTERISTICS (TA = TMIN to TMA)(; Vss1, Vss2 = -5V;

Vdd1, Vdd2 = 5V; GND=OV;
MClK=1.024 MHz; HBR=Vdd; LPWR=O; Device is connected as shown in Figure 3, the System Connection Diagram; unless otherwise specified. (Note 1»

Symbol

Parameter*
Specified Temperature Range

Min

Typ

Max

Units

-55

-

+85

°c

-

103
118
121
124
127
129
130

-

dB
dB
dB
dB
dB
dB
dB

-

dB
dB
dB
dB
dB
dB
dB

Dynamic Performance
Dynamic Range
HBR = 1:
OFST =1

HBR = 0:
OFST = 1

Signal-to-Distortion:

Intermodulation Distortion

fo
fo
fo
fo
fo
fo
fo

=
=
=
=
=
=
=

(Note 1)
4000 Hz
2000 Hz
1000 Hz
500 Hz
250 Hz
125 Hz
62.5 Hz

fo
fo
fo
fo
fo
fo
fo

=
=
=
=
=
=
=

2000 Hz
1000 Hz
500 Hz
250 Hz
125 Hz
62.5 Hz
31.25 Hz

DR

-

116

-

-

99
118
121
124
127
129
130

100
110

115
120

IMD

-

110

-

-

MCLK = 1.024 MHz (Note 2)
HBR = 1
HBR =0

SDR

(Note 3)

-

dB
dB
dB

dcAccuracy
(Note 4)

FSE

-

TCFS

-

1

(Notes 4,5)

5

ppmrC

Offset

(Note 4)

VZSE

-

10

Offset after Calibration

(Note 6)

±100

Offset Calibration Range

(Note 7)

100

-

%F.S.

TCZSE

-

-

60

-

J..lVloC

Full Scale Error
Full Scale Drift

Offset Drift
Notes:

(Note 4,5)

%
mV
J..lV

1. fo = CS5322 output word rate. Refer to the CS53221CS5323 data sheet for details on the CS5322
FIR Filter.
2. Tested with full scale input signal of 50 Hz; fOWR = 500 Hz; OFST = 0 or OFST = 1.
3. Tested with input signals of 30 Hz and 50 Hz, each 6 dB down from full scale fOWR = 1000 Hz.
4. Specification is for the parameter over the specified temperature range and is for the CS5321 device
only (VREF=+4.5V). It does not include the effects of external components, OFST = O.
5. Drift specifications are guaranteed by design and/or characterization.
6. The offset after calibration specification applies to the effective offset voltage for a ± 4.5 volt input to the
CS5321 modulator, but is relative to the output digital codes from the CS5322 after ORCAl and
USEOR have been made active.
7. The CS5322 offset calibration is performed digitally and includes ± full scale (± 4.5 volts into CS5321).
Calibration of offsets greater than ±5% of full scale will begin to subtract from the dynamic range.

* Refer to Parameter Definitions (immediateIY,foliowing pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.

2-220

DS88F3

.. .....
.-._..
_
..--__
--~

CS5321

ANALOG CHARACTERISTICS (Continued)
Parameter·

Symbol

Specified Temperature Range

Min

Typ

Max

Units

-55

-

+85

°C

-

1500

Hz

Input Characteristics
Input Signal Frequencies

(Note 8)

BW

dc

Input Voltage Range

(Note 9)

VIN

-4.5

Input Overrange Voltage Tolerance

(Note 9)

lavR

-

I

+4.5

V

5

%F.S.

-

5.5
5.5
3.0
3.0

7.5
7.5
4.5
4.5

mA
mA
mA
mA

PON
POL

-

55
30

75
45

mW
mW

Po

-

2

-

mW

PSR

-

60

-

dB

Power Supplies
DC Power Supply Currents

(Note 10)
Positive Supplies
Negative Supplies
LPWR = 1 Positive Supplies
Negative Supplies

-

LPWR = 0

Power Consumption

(Note 10)
Normal Operating Mode (Note 11)
Lower Power Mode (Note 12)

Power Down
Power Supply Rejection
Notes:

(dc to 128 kHz)(Notes 13, 14)

-

8. The upper bandwidth limit is determined by the CS5322 digital filter.
9. This input voltage range is for the configuration depicted in Figure 3, the System Connection Diagram,
and applies to signal from dc to f3 Hz. Refer to CS5322 Filter Characteristics for the values of f3.
10. All outputs unloaded. All logic inputs forced to Vdd or GND respectively.
11. LPWR=O
12. The CS5321 power dissipation can be reduced under the following conditions:
a) LPWR=1; MCLK=512kHz, HBR=1
b) LPWR=1; MCLK=1.024MHz, HBR=O
13. Tested with a 100 mVp-p sine wave applied separately to each supply.
14. Refer to the CS53221CS5323 Data Sheet for values of the Filter Characteristics of the CS5322.

• Refer to Parameter Definitions (immediately following pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.

DS88F3

filii

2-221

..,-- ---..
..--------_-----_

CS5321

SWITCHING CHARACTERISTICS (TA= Tmin to Tmax; Vdd1, Vdd2 = 5V±5%;
Vss1, Vss2 = -5V±5%; Inputs: Logic 0 = OV Logic 1 = V+; CL = 50 pF (Note 15»
Parameter
(Note 16)

MCLK Frequency

Symbol

Min

Typ

Max

Units

fc

0.250

1.024

1.2

MHz

40

-

60

%
ps

50

300
100
200
100
200

-

ns

255

ns

300

ns

MCLK Duty Cycle
Rise Times:

Any Digital Input
Any Digital Output

(Note 17)

trisein
triseout

Fall Times:

Any Digital Input
Any Digital Output

(Note 17)

tfallin
tfallout

-

MSYNC Setup Time to MCLK rising

tmss

20

MSYNC Hold Time after MCLK rising

tmsh

20

-

MCLK rising to Valid MFLG

tmfh

MCLK rising to Valid MDATA

tmdv

-

140
170

MCLK Jitter (In-band)

50

-

ns
ns
ns
ns
ns

Notes: 15. Guaranteed by design, characterization, or test.
16. If MCLK is removed, the CS5321 will enter a power down state.
17. Excludes MCLK input, MCLK should be driven with a signal having rise/fall times of 25ns or faster.

4.0V

4.6V

1.0V

0.4 V

Rise and Fall Times

MCLK

MSYNC

tmdv
VALID DATA

MDATA

tmfh
MFLG

CS5321 Interface Timing, HBR=l

2-222

DS88F3

.. ...
._.-.
-•. ...".,-~-

~~~

CS5321

~-

DIGITAL CHARACTERISTICS (TA = T min to T max; Vddl = Vdd2 = 5V±5%; GND = OV;
measurements performed under static conditions)
Parameter

Symbol

Min

Typ

Max

Units

High-Level Input Drive Voltage

(Note 18)

VIH

(Vdd)-0.6

-

-

V

Low-Level Input Drive Voltage

(Note 18)

VIL

-

-

1.0

V

VOH

(Vdd)-0.3

-

-

V

High-Level Output Voltage

lOUT = -40

!lA

(Note 19)

Low-Level Output Voltage

lOUT = +40 ~A

(Note 19)

VOL

-

Input Leakage Current

ILKG

-

Digital Input Capacitance

CIN

-

0.3

V

±10

!lA

-

pF

9

Digital Output Capacitance
9
COUT
Notes: 18. Device is intended to be driven with CMOS logic levels.
19. Device is intended to be interfaced to CMOS logic. Resistive loads are not recommended on
these pins.

pF

RECOMMENDED OPERATING CONDITIONS (GND=OV, see Note 20)
Parameter

Symbol
Positive Vddl, Vdd2
Negative Vssl, Vss2

DC Supply:
Ambient Operating Temperature

TA

Min

Typ

Max

Units

4.75
-4.75

5.0
-5.0

5.25
-5.25

V
V

-55

-

+85

°C

Notes: 20. All voltages with respect to ground.

ABSOLUTE MAXIMUM RATINGS
Parameter

Symbol

DC Supply:

Positive Vddl, Vdd2
Negative Vssl, Vss2

Input Current, Any Pin Except Supplies

(Note 21)

Min

Max

Units

-0.3
+0.3

6.0
-6.0

V
V

±10

rnA

25

rnA

1

W

Output Current

lout

Total Power (all suppUes and outputs)

Pt

-

VIND

-0.3

(Vdd)+0.3

V

-65

150

°C

Digital Input Voltage
Storage Temperature

lin

Tstg
Notes: 21. Transient currents of up to 100 rnA will not cause SCR latch up.
·WARNING:

DS88F3

Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

2·223

•

,

. -

..,....
...
... ..,..,.....
._.
....
..,..,
~

C~3.21

GENERAL DESCRIPTION

The CS5321 utilizes a fourth-order oversampling
architecture to achieve high resolution ND conversion. The modulator consists of a 1-bit AID
converter embedded in a negative feedback loop.
The modulator provides an oversampled serial
bit stream at 256 kbits per second (HBR=I) and
128 kbits per second (HBR=O) operating with a
clock rate of 1.024 MHz.

The CS5321 is a fourth-order CMOS monolithic
analog modulator designed specifically for very
high resolution measurement of signals between
dc and 1500 Hz. Configuring the CS5321 with
the CS5322 FIR filter results in a high resolution
ND converter system that performs sampling
and AID conversion with dynamic range exceeding 120 dB (Refer to the CS5322/CS5323 data
sheet for specific details on the CS5322).

The CS5321 offers improved performance, lower
power consumption, and greater tolerance to
clock jitter than the CS5323.

+5V
Analog
Supply

+5V
Digital
Supply

21
VD+

DGND
SID

25
24

SOD
LPWR
HBR

5
VREF+
+68~F

VREF·

MFLG

-----4020

AINR

1

I

___

AIN·

J

Logic

CS

25

5

24

6

20

7

18

10

-

RIW

MSYNC

MDATA

Test
Data

Serial
Data
Interface

27
RSEL

--

MCLK

23

ERROR
12
CSEL

CS5322
11

1
28
22

MFLG

CS5321
17

26

DRDY

MDATA

MDATA

8

COG

LS~T~

AIN+

I

26

SCLK

MCLK

10

0.1~

Control

MSYNC

6

TANT.

27

TDATA

14 GND7

13
PWDN
Hardware

13 GND6
12 GND5
11 GND4
7
GND3
4
GND2

·5V
Analog
Supply

1O~F~+

GND8

Control

15
CLKIN

16
GND9

SYNC

19
GND10

+5V
Digital
Supply

Unused logic
inputs must be
connected to
DGNDorVD+

Figure 1. System Connection Diagram

2-224

DS88F3

.....
.......
._.
.. ...
.,

~

.,.,

~--

.-

Analog Input

The CS5321 NO converter uses a switched capacitor architecture for its signal and voltage
reference inputs. The signal input uses three
pins; AINR, AIN+, and AIN-. The AIN- pin acts
as the return pin for the AINR and AIN+ pins.
The AINR pin is a switched capacitor "rough
charge" input for the AIN+ pin. The input impedance for the rough charge pin (AINR) is lIfC
where f is the two times the modulator sampling
clock rate and C is the internal sampling capacitor (about 40 pF). Using a 1.024 MHz master
clock (HBR =1) yields an input impedance of
about 11(512 kHz)X(4OpF) or about 50 kohms.
Internal to the chip the rough charge input precharges the sampling capacitor used on the AIN+
input, therefore the effective input impedance on
the AIN+ pin is orders of magnitude above the
impedance seen on the AINR pin.
The analog input structure inside the VREF+ pin
is very similar to the AINR pin but includes additional circuitry whose operating current can
change over temperature and from device to device. Therefore, if gain accuracy is important, the
VREF+ pin should be driven from a low source
impedance. The current demand of the VREF+
pin will produce a voltage drop of approximately
45 mV across the 200 ohm source resistor of
Figure 2-A with MCLK = 1.024 MHz, HBR = 1,
and temperature = 25°C.
When the CS5321 modulator is operated with a
4.5 V reference it will accept a 9 V pop input
signal, but modulator loop stability can be adversely affected by high frequency out-of-band
signals. Therefore, input signals must be bandlimited by an input filter. The -3 dB comer of
the input filter must be equal to the modulator
sampling clock divided by 64. The modulator
sampling clock is MCLKJ4 when HBR = 1 or
MCLKJ8 when HBR =0. With MCLK =1.024
MHz, HBR = 1, the modulator sampling clock is
256 kHz which requires an input filter with a -3
dB comer of 4 kHz. The bandlimiting may be
DS88F3

CS5321

accomplished in an amplifier stage ahead of the
CS5321 modulator or with the RC input filter at
the AIN+ and AINR input pins. The RC filter at
the AIN+ and AINR pins is recommended to reduce the "charge kick" that the driving amplifier
sees as the switched capacitor sampling is performed.
Figure 1 illustrates the CS5321! CS5322 system
connections. The input components on AINR
and AIN+ should be identical values for optimum performance. In choosing the components
the capacitor should be a minimum of 0.1 uF
(COG dielectric ceramic preferred). For minimum board space, the RC components on the
AINR input can be removed, but this will force
the driving amplifier to source the full dynamic
charging current of the AINR input. This can increase distortion in the driving amplifier and
reduce system performance. In choosing the RC
filter components, increasing C and minimizing
R is preferred. Increasing C reduces the instantaneous voltage change on the pin, but may require
paralleling capacitors to maintain smaller size
(the recommended 0.1 ~F COG ceramic capacitor is larger than other similar-valued capacitors
with different dielectrics). Larger resistor values
will increase the voltage drop across the resistor
as the recharging current charges the switched
capacitor input.

The OFST Pin
The CS5321 modulator can produce "idle tones"
which occur in the passband when the input signal is steady state dc signal within about ±SO
mV of bipolar zero. In the CS5321 these tones
are about 135 dB down from full scale. The user
can force these idle tones "out-of-band" by adding 100 mV of dc offset to the signal at the AIN
input. Alternately, if the user circuitry has a low
offset voltage such that the input signal is within
±50mV of bipolar zero when no AC signal is
present, the OFST pin on the CS5321 can be activated. When OFST = 1, +100 mV of input
2-225

•

.. ...
.... ,.,-._.
.....
~-

~~

CS5321

~~

+910
15V

10n

r-----------------

IA

~n

I
I
I ~ To VREF+

I Sc
VVv
~ 1.
I )
0.1 1lt:.L
illS IlF
I
~ ~
I
SL.....----------------I
IB
+91015V
I
IIS~..JV\rr~-1V\,'Ir_____j

To VREF+

I
I

I

LT1007

Figure 2. 4.5 Volt Reference with two filter options (see text)

referred offset will be added internal to the
CS5321 and guarantee that any idle tones present will lie out-of-band. The user should be
certain that when OFST is active (OFST =1) that
the offset voltage generated by the user circuitry
does not negate the offset added by the OFST
pin.
Input Range and Overrange Conditions
The analog input is applied to the AIN+ and
AINR pins with the AIN- pin connected to
GND. The input is fully differential but for
proper operation the AIN- pin must remain at
GND potential.
The analog input span is defined by the voltage
applied between the VREF+ and VREF- input
pins. See the Voltage Reference section of this
data sheet for voltage reference requirements.
The modulator is a fourth order delta-sigma and
is therefore conditionally stable. The modulator
may go into an oscillatory condition if the analog input is overranged. Input signals which
exceed either plus or minus full scale by more
than 5 % can introduce instability in the modulator. If an unstable condition is detected, the
modulator will be reduced to a first order system
until. loop stability is achieved. If this occurs the
MFLG pin will transition from a low to a high
which will result in an error bit being set in the
2-226

CS5322. The input signal must be reduced to
within the full scale range of the converter for at
least 32 MCLK cycles for the modulator to recover from this error condition.
Voltage Reference
The CS5321 is designed to operate with a voltage reference in the range of 4.0 to 4.5 volts.
The voltage reference is applied to the VREF+
pin with the VREF- pin connected to the GND.
A 4.5 V reference will result in the best SIN performance but most 4.5V references require a
power supply voltage greater than 5.0 V for operation. A 4.0 V reference can be used for those
applications which must operate from only 5.0 V
supplies, but will yield a SIN slightly lower (1-2
dB) than when using a 4.5 V reference. The voltage reference should be designed to yield less
than 2 IlV rms of noise in band at the VREF+
pin of the CS5321. The CS5322 filter selection
will determine the bandwidth over which the
voltage reference noise will affect the
CS5321/CS5322 dynamic range.
For a 4.5 V reference, the LT1019-4.5 voltage
reference yields low enough noise if the output
is filtered with a low pass RC filter as shown in
Figure 2-A. The filter in Figure 2-A is acceptable for most spectral measurement applications,
but a buffered version with lower source impedDS88F3

........
_-.
...............
._.
.-

.,,~-

CS5321

~

ance (Figure 2-B) may be preferred for dc-measurement applications.
Due to its dynamic (switched-capacitor) input
the input impedance of the +VREF pin of the
CS5321 will change any time MCLK or HBR is
changed. Therefore the current required from the
voltage reference will change any time MCLK or
HBR is changed. This can affect gain accuracy
due to the high source impedance of the filter
resistor in Figure 2-A. If gain error is to be minimized, especially when MCLK or HBR is
changed, the voltage reference should have lower
output impedance. The buffer of Figure 2-B offers lower output impedance and will exhibit
better system gain stability.
Clock Source

For proper operation, the CS5321 must be provided with a CMOS-compatible clock on the
MCLK pin. The MCLK for the CS5321 is usually provided by the CS5322 filter. MCLK is
usually 1.024 MHz to set the seven selectable
output word rates from the CS5322. The MCLK
frequency can be as low as 250 kHz and as high
as 1.2 MHz. The choice of clock frequency can
affect performance; see the Performance section
of the data sheet. The clock must have less than
300 ps jitter to maintain data sheet performance
from the device. The CS5321 is equipped with
loss of clock detection circuitry which will cause
the CS5321 to enter a powered-down state if the
MCLK is removed or reduced to a very low frequency. The HBR pin on the CS5321 modifies
the sampling clock rate of the modulator. When
HBR=l, the modulator sampling clock will be at
MCLKl4; with HBR =0 the modulator sampling
clock will be at MCLKl8. The chip set will exhibit about 3 dB less SIN performance when the
HBR pin is changed from a logic "1" to a logic
"0" for the same output word rate from the
CS5322.

DS88F3

Low Power Mode

The CS5321 includes a low power operating
mode (LPWR =1). hen operated with
LPWR = 1, the CS5321 modulator sampling
clock must be restricted to rates of 128 kHz or
less. Operating in low power mode with modulator sample rates greater than 128 kHz will
greatly degrade performance.
Digital Interface and Data Format

The MCLK signal (normally 1.024 MHz) is divided by four, or by eight inside the CS5321 to
generate the modulator oversampling clock. The
HBR pin determines whether the clock divider
inside the CS5321 divides by four (HBR =1) or
by eight (HBR =0). The modulator outputs a
ones density bit stream from its MDATA and
MDATA pins proportional to the analog input
signal, but at a bit rate determined by the modulator oversampling clock. For proper
synchronization of the bitstream, the CS5321
must be furnished with an MSYNC signal prior
to data conversion. The MSYNC signal, generated by the CS5322, resets the MCLK
counter-divider in the CS5321 to the correct
phase so that the bitstream can be properly sampled by the CS5322 digital filter.
When operated with the CS5322 digital filter the
output codes from the CS53211CS5322 will
range from approximately decimal -5,242,880 to
+5,242879 for an input to the CS5321 of ±4.5 V.
Table 1 illustrates the output coding for various
input signal amplitudes. Note that with a signal
input defined as a full scale signal (4.5 V with
VREF+ =4.5V) the CS5321/CS5322 chip does
not output a full scale digital code of 8,388,607
but is scaled to a lower value to allow some
overrange capability. Input signals can exceed
the defined full scale by up to 5% and still be
converted properly.

2-227

-

I

......- ......
=:.

~==~:
Modulator
Input Signal

CS5321
CS5322 Filter
Output Code

HEX
> (+VREF + 5%)

Decimal

Error Flag Possible

"" (+VREF + 5%)

53FFFF(H)

+5505023

+VREF

4FFFFF(H)

+5242879

OV

OOOOOO(H)

0

-VREF

BOOOOO(H)

-5242880

"" - (+VREF + 5%)

ACOOOO(H)

-5505024

> - (+VREF + 5%)

0
________ Dynamic Range = 122.0 dB
-20
HBR= 1
-40
OFST=O
LPWR=O
-60
·80
·100
·120
·140
·160
·180
0

Error Flag Possible

Table 1. Output Coding for the CS5321
and CS5322 combination.

Performance
Figure 3, 4 and 5 illustrate the spectral performance of the CS53211CS5322 when operating
from a 1.024 MHz master clock. Ten 1024 point
FFTs were averaged to produce the plots.

500
Figure 3. 1024 Point FFT Plot with
-20 dB, 100 Hz Input, ten averages

o ,----------------------------,
·20
-40
-60
-80
-100 - - - - - -

SID = 116.0 dB
SIN = 118.4 dB
SIN+D =114.2 dB
HBR= 1
OFST=O
LPWR=O

·120 - - - - - -

Figure 3 illustrates the chip set with a 100Hz,
-20 dB input signal. The sample rate was set at 1
kHz. Dynamic range is 122 dB.

·140 ·160

.180

o
The dynamic range calculated by the test software is reduced somewhat in Figures 4 and 5
because of jitter in the signal test oscillator. Jitter
in the 100 Hz signal source is interpreted by the
signal processing software to be increased noise.
The choice of master clock frequency will affect
performance. The CS5321 will exhibit the best
Signal! Distortion performance with slower
modulator sampling clock rates as slower sample
rates allow more time for amplifier settling.
For lowest offset drift, the CS5321 should be operated with MCLK = 1.024 MHz and HBR =1.
Slower modulator sampling clock rates will exhibit more offset drift. Changing MCLKto 512
kHz (HBR =1) or changing HBR to zero
(MCLK =1.024 MHz) will cause the drift rate to
double. Offset drift is not linear over temperature
2-228

500
Figure 4.1024 Point FFT Plot with
Full Scale Input, 100 Hz, ten averages

0
·20
-40
·60

SID = 122.7 dB
SIN = 117.1 dB
S/N+D = 116.4 dB
HBR=O
OFST=O
LPWR=O

·80
·100
·120
·140
·160
·180

500

0
Figure 5. 1024 Point FFT Plot with
Full Scale Input, 100 Hz, ten averages

DS88F3

..............
......
.........

.- -~-

so it is difficult to specify an exact drift rate.
Offset drift characteristics vary from part to part
and will vary as the power supply voltages vary.
Therefore, if the CS5321 is to be used in precision dc measurement applications where offset
drift is to be minimized, the power supplies
should be well regulated. The CS5321 will exhibit about 6 ppmrC of offset drift with MCLK
= 1 and HBR =1.
Gain drift of the CS5321 itself is about 5
ppmrC and is not affected by either modulator
sample rate or by power supply variation.

CS5321

passband between dc and the comer frequency
of the digital filter.
Power Supply Rejection Ratio

,.

The PSRR of the CS5321 is frequency dependent. The CS5322 digital filter attenuation will aid
in rejection of power supply noise for frequencies above the comer frequency setting of the
CS5322. For frequencies between dc and the
comer frequency of the digital filter, the PSRR is
nearly constant at about 60 dB.
Board Layout Considerations

Power Supply Considerations
The system connection diagram, Figure 1, illustrates the recommended power supply
arrangements. There are two positive power supply pins for the CS5321 and two negative power
supply pins. Power must be supplied to all four
pins and each of the supply pins should be decoupled with a 0.1 uP capacitor to the nearest
ground pin on the device.
When used with the CS5322 digital filter, the
maximum voltage differential between the positive supplies of the CS5321 and the positive
digital supply of the CS5322 must be less than
0.25 V. Operation beyond this constraint may result in loss of analog performance in the
CS5321! CS5322 system performance.
Many seismic or sonar systems are battery powered, and utilize dc-dc converters to generate the
necessary supply voltages for the system. To
minimize the effects of power supply interference, it is desirable to operate the dc-dc
converter at a frequency which is rejected by the
digital filter, or locked to the modulator sample
clock rate.

All of the 0.1 J.IF filter capacitors on the power
supplies, AIN+, and AINR, should be placed
very close to the chip and connect to the nearest
ground pin on the device. The capacitors between VREF+ and VREF- should be located as
close to the chip as possible.
The 0.1 J.IF capacitors on the AIN+ and AINR
pins should be placed with their leads on the
same axis, not side-by-side. If these capacitors
are placed side-by-side their electric fields can
interact and cause increased distortion.
The chip should be surrounded with a ground
plane. Trace fill should be used around the analog input components. See the Layout and
Design Rules for Data Converters application
note in the Data Book.

Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout

A synchronous dc-dc converter, whose operating
frequency is derived from the 1.024 MHz clock
used to drive the CS5322, will minimize the potential for "beat frequencies" appearing in the
DS88F3

2-229

..................
..,.......
...............

CS5321

GROUND
POSITIVE POWER ONE
NEGATIVE POWER ONE
GROUND

G:::
Vss1

~ ~OFST

LPWR

OFFSET
LOW POWER MODE

GND2~~
/ ?HBR
HIGH BIT RATE
~"l
('~ MSYNC MODULATOR SYNC
VREF- ~
9
~MFLG MODULATOR FLAG

VOLTAGE REFERENCE VREF+
VOLTAGE REFERENCE
GROUND
NEGATIVE ANALOG INPUT
POSITIVE ANALOG INPUT

5

GND3 ~
AIN- AIN+ ---./
/

4

3

2

2827 26 25

6
7

CS5321

24
23

,r-GND11 GROUND

8

TOP
VIEW

22

-Vdd2

9
10

21 " - Vss2
20 \

<\-

POSITIVE POWER TWO
NEGATIVE POWER TWO

GROUND

AINR --.1/
GND4.-1

GROUND

GND5

MDATA MODULATOR DATA

GROUND

GND6

MDATA MODULATOR DATA

GROUND

GND7

GND9

GROUND

GND8

GROUND

ANALOG INPUT ROUGH

11

19
12 13 14 15 16 17 18

MCLK CLOCK INPUT
LGND10 GROUND

CS5321 PIN DESCRIPTIONS
Power Supplies

Vddl - Positive Power One, PIN 2
Positive supply voltage. Nominally +5 Volts.
Vdd2 - Positive Power 1\vo, PIN 22
Positive supply voltage. Nominally +5 Volts.

Vssl - Negative Power One, PIN 3
Negative supply voltage. Nominally -5 Volts.
Vss2 - Negative Power 1\vo, PIN "21
Negative supply voltage. Nominally -5 Volts.
GNDI through GND11 - Ground, PINS 1, 4, 7, 11, 12, 13, 14, 15, 16, 19, 23.
Ground reference.

Analog Inputs
AIN+ - Positive Analog Input, PIN 9
Nominally ± 4.5V
AIN- - Negative Analog Input, PIN 8
This pin is tied to ground.
2-230

DS88F3

.... ...
. ...,,-.-.-.
~

.-

.

~~-

~~

CS5321

AINR - Analog Input Rough, PIN 10
Allows a non-linear current to bypass the main external anti-aliasing filter which if allowed to
happen, would cause harmonic distortion in the modulator. Please refer to the System
Connection Diagram and the Analog Input and Voltage Reference section of the data sheet for
recommended use of this pin.
VREF+ - Positive Voltage Reference Input, PIN 5
This pin accepts an external +4.5V voltage reference.
VREF - - Negative Voltage Reference Input, PIN 6
This pin is tied to ground.
Digital Inputs
MCLK - Clock Input, PIN 20
A CMOS-compatible clock input to this pin (nominally 1.024 MHz) provides the necessary
clock for operation of the modulator, digital filter and data output portions of the NO converter.
MSYNC - Modulator Sync, PIN 25
A transition from a low to high level on this input will re-initialize the CS5321. MSYNC resets
a divider-counter to align the MDATA output bit stream from the CS5321 with the timing inside
the CS5322.
OFST - Offset, PIN 28
When high, adds approximately 100mV of input referred offset to guarantee that any zero input
limit cycles are out of band if present. When low, zero offset is added.
LPWR - Low Power Mode, PIN 27
The CS5321 power dissipation can be reduced from its nominal value of 60 mW to 30 mW
under the following conditions:
LPWR=l; MCLK ~ 512 kHz, HBR=l; or
LPWR=l; MCLK ~ 1.024 MHz, HBR=O
HBR - High Bit Rate, Pin 26
Selects either %MCLK (HBR=l) or YsMCLK (HBR=O) for the modulator sampling clock.
Digital Outputs
MDATA - Modulator Data Output, PIN 18
Data will be presented in a one-bit serial data stream at a bit rate of 256 kHz (HBR=l) or
128 kHz (HBR=O) with MCLK operating at 1.024MHz.
MDATA - Modulator Data Output, PIN 17
Inverse of the MDATA output.

DS88F3

2-231

-I
I

I

. ...........-...,.
~

.., ..,..,

~~~

~~

CS5321

MFLG - Modulator Flag, PIN 24
A transition from a low to high level signals that the CS5321 modulator is unstable due to an
over-range on the analog input.

PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full-scale (rms) signal to the broadband (rms) noise signal. Broadband noise is
measured with the input grounded within the bandwidth of 1 Hz to foWR/2 Hz. Units in db.

Signal-to-Distortion
The ratio of the full-scale (rms) signal to the rms sum of all harmonics up to 1000 Hz. Units in
dB.

Intermodulation Distortion
The ratio of the rms sum of the two test frequencies (30 and 50 Hz) which are each 6dB down
from full-scale to the rms sum of all intermodulation components within the bandwidth of dc to
1000 Hz. Units in dB.

Full Scale Error
The ratio of the difference between the value of the voltage reference and analog input voltage
to the full-scale span (two times the voltage reference value). The ratio is calculated after the
effects of offset and the external bias components are removed and the analog input voltage is
adjusted. Measurement of this parameter uses the circuit configuration illustrated in the System
Connection Diagram. Units in %.

Full Scale Drift
The change in the Full Scale value with temperature. Units in ppml°C

Offset
The difference between the analog ground and the analog voltage necessary to yield an output
code from the CS53211CS5322 of OOOOOO(H). Measurement of this parameter uses the circuit
configuration illustrated in the System Connection Diagram. Units in m V.

Offset Drift
The change in the Offset value with temperature. Measurement of this parameter uses the
circuit configuration illustrated in the System Connection Diagram. Units in ~V/oC

2·232

DS88F3

. .... ,. ....
i-'~ • • ~~~ •

. . . . . .i - ' •

CDB5321

....

Semiconductor Corporation

Evaluation Board for CS5321 & CS5322
Features

General Description

• DI P switch control of all CS5322 logic
pins
• Header control of all CS5322 logic pins

The CDB5321 is an evaluation board that allows laboratory characterization of the CS5321/CS5322 AID
converter chip-set. The chip-set supports seven different
selectable word rates: 4 kHz, 2 kHz, 1 kHz, 500 Hz
250 Hz, 125 Hz and 62.5 Hz. Input to the board is
9 volts peak-to-peak. Output is via header connections
to the CS5322 serial interface.

• Supports manual operation of RESET
and SYNC
ORDERING INFORMATION: CDB5321

SYNC

-=r::.-

0--

CS5322

Reference
CS5321
i------IVREF+
Circuitry
MSYNC

AIN+

Headers
+5V

MSYNC

8

MCLK

RESET

MDATA

0--

-=r::.-

+5V

MFLG

AINR

9

2.048 MHz
Oscillatorl

DIP Switch
Selections

Divider
+5V Analog
+5V
Regulator

+15V

+5VDigital

-5V Analog

1

AGND

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

-5V
Regulator

-15V

11

DGND

+5V

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS88DB2

2·233

_-_-_

.. ...-.
-.-..--_._.

CDB5321

U6

+15V
3

+15V
+ 47J.1F

02

lC12

IN

7SL05

O.1J.1F

t 13

+5VA
+5VA

OUT

O.1J.1F
lC14

R2
2K

US
OUT 6

t7 t11

~--

-15V

03

I VREF
To
I (4.5 V) Figure 2
10KI
R161
I
OPTIONAL

LT1019
4.5V
51
GNO TRIM I
4

+

-15 V

i--

-5VA

U9

47J.1F

2
IN
O.1J.1F

79L05

3

-5VA

OUT

GNO

1N6276l16 lC17

~1S

+5V
6.SV
P6KE

+

01
OGNOO-~~----~----~--~

Figure 1. Power Supplies

2-234

DS88DB2

-......._._-.
............
--_

CDB5321

OVERVIEW

-15V inputs are regulated down to provide +5V
and -5V supplies necessary for the CS5321
modulator. Figure 1 also illustrates the LT1019
4.5V reference used with the CS5321 modulator.

The CDB5321 evaluation board requires three
separate power supplies for proper operation.
Figure 1 illustrates the power supply connections. The required power supply input voltages
consist of +5V, +15V, and -15Y. The CS5322 filter and logic support devices on the board
operate from the +5V supply. The +15V and

Figure 2 illustrates the CS5321 modulator circuitry, including the analog BNC input for the
test signal source. Most often switch selections
on S5 are set to HBR=l, LPWR=O, and

+5 VA

~

~

C22
0.1 f.LF

R6

5

VREF
From
Figure 1.

VREF+

OFST

VREF-

LPWR
HBR

200

8

I

Rl- -

-

-

S5

V2+

Vl+

AIN-

MCLK
9 AIN+
MSYNC

I

MDATA
10 AINR

C15 I
NPO
0.1 f.LFI
I
~e':.£S5321 Dat~~ ..J

::&

4

13
14

OFST
LPWR
HBR

AGNDl
AGND2
AGND3
AGND4
AGND5
AGND6
AGND7
Vl-

-5 VA

R8
lOOk

R9
lOOk

U2
CS5321

7
11
12

28
27
26
R7
lOOk

l

I

C27
0.1 f.LF

~

22

2

3

20

MSYNC

16

MDATA

MFLG

24

MDATA

17

DGNDl
DGND2
DGND3
DGND4

MCLK

25

To
Figure 4.

MFLG
• MDATA

23
19
16
15

V221

@ TEST POINT
C40
f.LF

~0.1

Figure 2. CS5321 Modulator Input Circuitry.
DS88DB2

2-235

~."

_

._.-.
_.-_.....____.._-_
...

CDB5321

74HC74

10
+5V

10
+5V

r

Q 9
U5B

8

*2.048 MHz
exceeds the
specified clock
frequency for
the CS5321

ClKl4 (512 kHz)
ClKl2 (1.024 MHz)
ClK (2.048 MHz)"
ClKIN (To Figure 4)

Figure 3. Oscillator I Divider

OFST=1. Figure 3 illustrates the 2.048 MHz oscillator and dual D flip flop clock divider. Note
that both the oscillator and the divider are separately decoupled from the +5V supply to reduce
clock jitter which can be introduced from noisy
supplies. Jumper J4 should be set in the CLKl2
position to source 1.024 MHz to the CS5322
chip for normal operation. If operation from
512 kHz clock is desired, the J4 jumper should
be changed to the CLKl4 position. The board
can be tested at 512 kHz without modification.
The digital interface pins to the CS5322 filter
chip are all available on the header connectors
11, J2, and 13 as shown in Figures 4, 5, and 6.
Note that one row of pins on each of the headers
is ground. It is advised that any connections
made to control lines be done with twisted pair
ribbon cable; with each twisted pair containing
one signal and one ground connection. This
minimizes radiated noise.

2-236 .

CAUTION!

Caution is advised when interfacing the evaluation board to any circuitry powered from
another source. For example, when interfacing
to a computer I/O card be sure that the evaluation board and the computer are both powered
up before connecting to the evaluation board
headers. Always disconnect header connections
when powering down the board but not the computer. Failure to follow this advice may cause
damage to either the computer I/O or to the
CS5322, because the computer outputs try to
power the CDB5321 board.

DS88DB2

c

I

C
(From

en

ic

Ire 3)

,--.

CLKIN
~l1lF

ID
I\)

8

C9n
9

-;1

LJ

--:lQ.lIlF

:f1

VD1+ DGND VD2+ DGND
CLKIN
§.

To

MSYNC

SOD
SCLK
DRDY

7

MCLK

+5V

IlI

O.1IlF

3 U3B 4

.'L

MDATA

47k
SIPS

MFLG

CS5322
Ul

25
SID
23
ERROR
27~
RSEL
1

CS
RiW

SYNC

JP13
SCLK

r!L
o 0

Figure
2

~

--::::r::::~

?-

~I SOD

~I

~..ol

SID
ERR
RSEL

cs
RIW

e

l 1-0..0

.6WYNC
100~1
R13

4

.J.='-

RST
TDATA
~..c CSEL

to-';:

12

f-O.;:

13~

HIS

~..c PWDN

14
16
17
18
15~
19

V.
V

SYNC

+oj

11~

~
J,,--,

SClK
SID
ERROR
RSEL
CS

.-4L

+5VD

5K

f-O.;: DECC
1-oJ' DECB

r:o...a

I-op

1-0-",1

DECA
USEOR
ORCAL

=--.J

lOOk
USEOR
ORCAL

SW4~ R14

~

(~

-,L

~T +5V

'----+0 '

o
c

;"

m
en
~

-0'

V,

1-<"

~,

/n

Vo-

~

~

,=1,....

'~'"
" RiW

r:o..c

28~

2

....
=••
..'.".....;

DRDY

+5V

~O.l

~

RESET
TDATA
CSE1.
HIS
PWDN
DECC
DECB
DECA
USEOR
ORCAl

RDY
To
OD Figure
SCLK
5,6

TP

=

U3A 2

24
26
22

t------

~

~

r-.!
1

3

--.

...

'DATA

Figure 4. CSS322 Filter Interface

......

1-

._.-.
_.-_....__.._-...

CDB5321

ABC Output Word Rate
000
62.5
Selection
100
125
via hardware 010
250
pins
110
500
001
1000
1 01
2000
011
4000

DECA
USEOR

ORCAl

SID

ERR

ON"

Do not use offset register

OFF

Use offset register

ON"

Disable offset register calibration

OFF

Enable offset register calibration

ON

Sets SID to logic 0

DECB

PWDN

OFF" Allows pull-up on SID line
ON

ON

ON"

Normal Operation

OFF

Power down active

ON

Selects configuration register for
operating mode

OFF"

Select hardware pins for operating
mode

ON"

Selects MDATA from modulator

OFF

Selects TDATA as filter input

ON"

Sets TDATA input to logiC 0

OFF

Enables TDATA from J1 header

Sets ERR to logic 0

OFF" Allows CS5322 ERROR output
RSEl

DECC

His

Select status register

OFF" Select conversion data register
CS

RIW

ON*

Chip select active

OFF

Chip select inactive

ON

CSEl

Enables write mode via SID pin

TDATA

OFF* Enables read mode via SOD pin
OFF = OPEN = 1
*Default to use Figure 6 interface.

OFF = OPEN = 1
"Default to use Figure 6 interface.

Table 1. S3 DIP Switch Selections

Table 2. S4 DIP switch selections
10

+5V - - - - < r - - - - - ' \ / V I r - - 1 r - - - - - - - - - - ,
R4
+

JP6
+5V
+5V

DRDY

From
Figure
4

SCLK

SOD

U3, U4 = 74HC04

~
- - --L.-u3c:

~

-~-~--

~

~
=
U3F
~
=
U3D
~ ~

9~ 8 ~

~
Figure 5. Serial Latch Interface on CDB5321 (Rev B) board
2-238

DS88DB2

----------- -----------

CDB5321

Figures 5 and 6 illustrate the logic used to drive
connections at header JP6 (Rev. B Board) or J2
(Rev. C Board).
The Rev. C evaluation board can directly interface to the CDBCAPTURE board through
connector J2. A D-type Flip-Flop must be added
in the patch area of the Rev. B evaluation board
to enable it to interface to the CDBCAPTURE
board. The CDBCAPTURE can be used to perform FFT analysis and noise histograms.
Tables 1 and 2 illustrate the DIP switch positions
of switches S3 and S4. The switch positions with
asterisks indicate preferred settings for driving
the interface on the CDBCAPTURE system.
The CS5322 filter should be set up for hardware
mode (HiS on switch S4 open). DIP switch S4
can then be used to select the desired output
word rate. After the selection on the DECA,
DECB, and DECC positions of the S4 DIP
switch, the S2 RESET switch must be activated,
followed by the S 1 SYNC switch (unless these

signals are controlled via the J1 and J3 header
signals).
Figure 7 illustrates the component layout of the
board while figures 8 and 9 illustrate the board
layout (not to scale).

Using the Evaluation Board
Connect the appropriate power supplies to the
binding posts of the board. Twist the +5V digital supply lead with the digital ground lead from
the board to the supply. Also twist the supply
leads for the analog voltages. Use a high quality
power supply which is low in noise and line frequency(50/60 Hz) interference.
Power up the supplies. Then connect a coaxial
cable from the analog BNC to the signal source.
Note that the performance of the AID converter
chip set will exceed the capability of most signal
generators, with respect to noise, distortion, and
line frequency interference.

10
+5V----+---------~r~,--~~------------------------,

10 J.1F

DRDYD

~C5

J2

+5

.-____
From
Figure 4

-":~'~TL_ _ r _1Q- -' ~:~
5

7
SCLK

4

+5

+5V
+5V
13Q I

DRDYD
'-----t-+-----f

SCLK

SOD

+5 10

U1074HC74

SOD

U474HC04

Figure 6. Serial Latch Interface on CDB5321 (Rev C) board.
DS88DB2

2-239

.",

--------,.,-- -----------

CDB5321

Once power has been applied to the board, connect the ribbon cable to the appropriate headers
(11, J2, andlor 13). The reset and the sync signals to the CS5322 must be applied before
normal operation can commence. This can be
done by using the S2 RESET switch and the S1
SYNC switch or by interfacing to these signals
via the 11 and 13 headers.

2-240

DS88DB2

~

GO
GO

",i-i
.1:

C

~

o

E======DGHO:3I.+5V~
~
~y

~

~;-I
(")

g

i....a

02

-~ ...
RSTQ

D
rJl

~

r
t""

~

a

iS'

I

>!B8~'S-fii!!

lDATA

CDB5321

:!

,

I

L

~,

OO~O

03

+5VA

.-

~C12

-15VA ~
-5VA

'.mi...d"do' Co,_at

RIO
D:~·
!
~ 0
= C~
1~ n 0D~~~;
~ 0·"9 ~ {Joo- .....

~
=,
R4

I

DRD
In

iiRiiY6

~

~LK

C3l

•

L S3 M

R25

Q
m
~
0c::J-

.....
=.-

I
II II II
I
~.81J ~p~C17

': ?
=
'__
IS4

o

0GG

JPl

1m!

W

o

.."'t,

C~

c"':> l"-'[i
111ft

D

c::J-

LPRW

is

+~~~~
+15VA
-15VA

6

AGHD

c::J-

I FR?

O

86

IN

g

0
~r.=D ~
U8

...2

o

R/W
a

lJ U
RP2

CLK

U3

J4

10

1

R9

§L_ }IB

R2

o

o

o

m
en

Co)

N

~

....~

1-

_.-_..__.._-_
...-.
~--.-.

CDB5321

Figure 8. CDB5321 (Rev. C) Component Side Layer (Not to Scale)

2-242

DS88DB2

----------- -----------

CDB5321

,

fill

Figure 9. CDB5321 (Rev. C) Solder Side Layer (Not to Scale)

DS88DB2

2·243

.._-_
_.-_...-r-_._.
_...-.

CDB5321

-Notes-

2-244

DS88DB2

. .........
J81~ • •J81"~ •

. . . . . .J81 •

....

CS5322 CS5323

Semiconductor Corporation

24-Bit Variable Bandwidth AID Converter
Features

General Description
The CS5323 analog modulator and the CS5322 digital
filter function together as a unique high resolution AID
converter intended for geophysical and other applications which require high dynamic range. The
CS5323/CS5322 combination performs sampling, AID
conversion, and anti-alias filtering.

• Monolithic CMOS AID Converter
• Dynamic Range
- 130dB @ 25 Hz Bandwidth
- 120dB @ 411 Hz Bandwidth
• Delta-Sigma Architecture
- Variable Oversampling: 64X to 4096X
- .Internal Track-and-Hold Amplifier
• Flexible Filter Chip
- Hardware or Software Selectable
Options
- Seven Selectable Filter Corner (-3d B)
Frequencies: 25, 51,102,205,411,
824 and 1650 Hz

< 100mW

• Low Power Dissipation:

The pair use Delta-Sigma modulation to produce highly
accurate conversions. The CS5323 oversamples, virtually eliminating the need for external anti-alias filters.
The CS5322 linear-phase FIR digital filter decimates
the output to anyone of seven selectable update periods: 16, 8, 4, 2, 1, 0.5 and 0.25 milliseconds. Data is
output from the digital filter in a 24-bit serial format.
The CMOS design of the CS5322/CS5323 achieves
high reliability while minimizing power dissipation.

ORDERING INFORMATION
CS5322-KL 0 to +70 °C
CS5322-BL -40 to +85 °C
CS5323-KL 0 to +70 °C
CS5323-BL -40 to +85 °C

CS5323
VA1+
IREF

VA2+

28-pin
28-pin
28-pin
28-pin

PLCC
PLCC
PLCC
PLCC

CS5322

VA1-

1

VA2-

VD+

SYNC CLKIN CS

RIW

RESET
MSYNC -

1

RSEL
SCLK
SID

MFLG

INT

SOD

SUM

MCLK

Analog
Modulator

SFF

MDATA -

ERROR

Digital
Filter

DRDY
ORCAL

VD+

DECA

DGND

DECB

CSEL
DECC
VD+

VD-

DGND

AGND1

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

AGND2

HIS TDATA PWDN

USEOR DGND

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS70F1

2-245

.. ..,.......,
. ...........
.......
~-

..,

~~

CS5323

(TA =TMIN to TMAX; VA-, VD- = -5V; VA+, VD+ = 5V; AGND
ClKIN = 1.024 MHz; Device connected as shown in Figure 16; logic 1 = VD+, logic 0 = OV;
unless otherwise specified~)

ANALOG CHARACTERISTICS

CS5323-K
Parameter*

Symbol

Specified Temperature Range

= OV;

CS5323-B

Min

Typ

Max

Min

Typ

Max

Units

.0

-

+70

-40

-

+85

°c

-

103
118
121
124
127
129
130

-

-

-

-

116

103
118
121
124
127
129
130

dB
dB
dB
dB
dB
dB
dB

Dynamic Performance
Dynamic Range
ClKIN = 1.024 MHz:

ClKIN

= 512 kHz:

Signal-to-Distortion:

Intermodulation Distortion

(Note 1)

fa
fa
fa
fa
fa
fa
fa

= 4000 Hz
= 2000 Hz
= 1000 Hz
= 500 Hz
= 250 Hz
= 125 Hz
= 62.5 Hz

fa
fa
fa
fa
fa
fa
fa

= 2000 Hz
= 1000 Hz
= 500 Hz
= 250 Hz
= 125 Hz
= 62.5 Hz
= 31.25 Hz

DR

116
-

-

(Note 2)
ClKIN = 1.024MHz
ClKIN = 512 kHz

SDR

(Note 3)

IMD

99
121
125
127
130
132
133

-

-

-

-

-

-

-

-

-

-

-

-

100

110

-

100

-

110
120

-

-

99
121
125
127
130
132
133

-

dB
dB
dB
dB
dB
dB
dB

110
120

-

dB
dB

110

-

dB

dcAccuracy
Full Scale Error
Full Scale Drift

(Note 4)

FSE

-

-

4

-

4

TCFS

-

-

(Notes 4, 5)

0.005

-

0.005

-

%
%/oC

VZSE

-

-

250

mV

±100

-

-

100

-

I1V
%F.S.

-

500

-

I1V/oC

Offset

(Note 4)

-

-

250

Offset after Calibration

(Note 6)

-

±100

Offset Calibration Range

(Note 7)

-

100

-

-

500

-

Offset 0 rift
Notes:

(Notes 4, 5)

TCZSE

1.
2.
3.
4.

fo = CS5322 output word rate. Refer to CS5322 Filter Characteristics for details.
Tested with full scale input Signal of 50 Hz; fo = 500 Hz.
Tested with input signals of 30 Hz and 50 Hz, each 6 dB down from full scale fo = 500 Hz.
Specification is for the parameter over the specified temperature range and is for the CS5323 device
only (I REF = 1 mA). It does not include the effects of extemal components.
5. Drift specifications are guaranteed by design and characterization.
6. The offset after calibration specification applies to the effective offset voltage for a ±10 volt input to the
CS5323 modulator, but is relative to the output digital codes from the CS5322 after ORCAl and
USEOR have been made active.
7. The CS5322 offset calibration is performed digitally and includes ± full scale (±10 volts into CS5323).
Calibration of offsets greater than ±10% of full scale will begin to subtract from the dynamic range.
* Refer to Parameter Definitions (immediately following pin descriptions at the end of this data sheet).
SpeCifications are subject to change without notice.
2·246

DS70F1

--

. ..----.. ...._..

~

--~

CS5323

."

ANALOG CHARACTERISTICS

(TA = TMIN to TMAX; VA-, VD- = -5V; VA+, VD+ = 5V; AGND = OV;
ClKIN = 1.024 MHz; Device connected as shown in Figure 16; logic 1 = VD+, logic 0 = OV;
unless otherwise specified.)
CS5323-K
Parameter*

Symbol

Specified Temperature Range

Min

Typ

0

-

CS5323·B
Max

Min

Typ

Max

Units

+70

-40

-

+85

°C

1500

Hz

+10.0

V

10

%F.S.

Input Characteristics
Input Signal Frequencies

(Note 8)

BW

dc

-

1500

dc

Input Voltage Range

(Note 9)

VIN

-10.0

+10.0

-10.0

Input Overrange Voltage

(Note 9)

IOVR

-

-

10

-

-

-

7.0
8.4

10.0
10.0

-

7.0
8.4

10.0
10.0

mA
mA

-

77

100
10

-

77

0.Q1

100
10

mW
mW

Power Supplies
DC Power Supply Currents
(Note 10)
Positive Supplies (IA+ and ID+)
Negative Supplies (IA- and ID-)
Power Consumption

(Note 10)
PWDN low
PWDN High

PON
Pos

-

0.Q1

PSR
(Notes 11, 12)
(dc to f1 Hz):
60
60
dB
VA+
dB
VA45
45
45
45
dB
VD+
dB
VD40
40
(f1 Hz to 128 kHz):
60
60
dB
VA+
60
dB
VA60
60
60
dB
VD+
dB
60
60
VDThe upper bandwidth limit is determined by the CS5322 digital filter.
This input voltage range is for the configuration shown in Figure 16, the System Connection Diagram,
and applies to signal from dc to f3 Hz. Refer to CS5322 Filter Characteristics for the values of f3.
All outputs unloaded. All logic inputs forced to VA+ or GND respectively. Power down mode power
consumption is with the signal source and the voltage reference source either grounded or floating.
Tested with a 100 mVp-p sine wave applied separately to each supply (VA1 and VA2 are
considered as one input for this test).
Refer to CS5322 Filter Characteristics table for the values of f1.

Power Supply Rejection

-

-

8.

Notes:

9.
10.
11.
12.

* Refer to Parameter Definitions (immediately following pin descriptions at the end of this data sheet).

DS70F1

2·247

_.

...........
....... .,..
.........

~

CS5322

~

FILTER CHARACTERISTICS (TA = Tmin to Tmax; VD+ = 5V; GND = OV; elKIN = 1.024 MHz;
transfer function shown in Figure 2; unless otherwise specified.)
Output Word Rate Passband Passband Flatness -3dB Freq.
f1 (Hz)
f2 (Hz)
fo (Hz)
RPB (dB)
1652.5
4000
1500
0.2
824.3
2000
750
0.04
411.9
1000
375
0.08
500
187.5
0.1
205.9
0.1
102.9
250
93.8
125
46.9
0.1
51.5
25.7
62.5
23.4
0.1
Note: 13. GSB = -130 dB for all Output Word Rates.

dB

0.20
0.16
iii' 0.12
:!:!. 0.08
ell
-g 0.04
'2 0.00
0 .04
-0.08
-0.12
-0.16
-0.20

O~--------T-~-----'­

-3
1

1

1

GSB

1

1

1

1

-

-

-

I -1-1-<------'1 1 1
1 1 1
fl

0.20
0.16
iii' 0.12
::g. 0.08
-gell 0.04
'20.00
:f-0.04
-0.08
-0.12
-0.16
-0.20

-gell

'---

-------

'-

~

"\
\
\

o

12.5

25
37.5
Frequency (Hz)

50

Figure 3. CS5322 Digital Filter Passband Ripple
fo = 125 Hz

2-248

7.25
14.5
29
58
116
232
464

r------ ~

........

~

"\
\

\

o

6.25

12.5
18.75
Frequency (Hz)

25

31.25

Figure 2. CS5322 Digital Filter. Passband Ripple
fo = 62.5 Hz

0.20
0.16
iii' 0.12
::g. 0.08
'---

2000
1000
500
250
125
62.5
31.25

f2 f3

Figure 1. CS5322 Filter Response

0.04
'20.00
:f-0.04
-0.08
-0.12
-0.16
-0.20

Group Delay
(ms)

i-

1

-130 -

Stopband
f3 (Hz) (Note 13)

62.5

'--""

r------------

'-

~

\
\

\

o

25

50
75
Frequency (Hz)

100

125

Figure 4. CS5322 Digital Filter Passband Ripple
fo=250 Hz
DS70F1

. ............-..
.....
..,

~

~~"".,

CS5322

."

~~

0.20
0.16
iii'0.12
~008
CD
•
-g 0.04

0.20
0.16
iii'0.12
"tl
-; 0.08
-g 0.04

~O.OO

~-0.04
-0.08
-0.12
-0.16
-0.20

---- r--------

~O.OO

~

'-

o

100

50

"-....---.

~-0.04

'---

-0.08
-0.12
-0.16
-0.20

\

150

200

250

'-- '---,

o

100

Figure S. CSS322 Digital Filter Passband Ripple
Co = SOO Hz

0.20
0.16
iii'0.12

~0.08

~0.08

-g

0.04
0.00
0 .04
-0.08
-0.12
-0.16
-0.20

o

200

400

----

:2 0.00

M

600

1000

800

~-0.04
:;-0.08
-0.12
-0.16
-0.20

Frequency (Hz)

Figure 7. CSS322 Digital Filter Passband Ripple
Co = 2000 Hz

i~
j

V

::l

1-

400

500

v

~ 0.04

--....

300

Figure 6. CSS322 Digital Filter Passband Ripple
Co = 1000 Hz

0.20
0.16
iii' 0.12

'2

200

Frequency (Hz)

Frequency (Hz)

CD

~

~

o

V--

/'

f-/

400

800

1200

1600

2000

Frequency (Hz)

Figure 8. CSS322 Digital Filter Passband Ripple
Co = 4000 Hz

'5.206.250 - , - - - - - - - - - - - - - - - - - - . ,

·5.206.250 - , - - - - - - - - - - - - - - - - - - ,
-5.208.328

·5.212.500

-5.212.500

·5.218.750

-5.218.750

l~

·5.225.000

I

·5.231.250

Q

- - - -{ -

- - - - - - - - -

-5.243.750

- - - - - - - - - - - - - - - - - - - - - - - - - -

- -

-

- - - - -

-5,237.500

-

.5.250.000 -'-_-'-_-'-_-'--_-'--_L--_L--_'----.J
22

29

36

43

50

Time (t of Output Words)

Figure 9. CS5322 Impulse Response, Co = 62.S Hz

DS70F1

-5,231,250

·5.240.723

·5.237.500

15

-5,225.000

57

-5.243.750
.5.250.000 -'-_-'-_-'-_-'--_-'--_-'--_-'----_L----'
H
~
~
36
43
~
~
Time (t of Output Words)

Figure 10. CS5322 Impulse Response, Co = 1000 Hz

2·249

.. ..._...,.
. ......
....
..,

~.-

~~---

CS5322

~..,

POWER SUPPLY

(TA

= 25°C; VD+ = 5V; ClKIN = 1.024 MHz)
CS5322-K

Parameter*
Specified Temperature Range

CS5322-B

Min

Typ

Max

Min

Typ

Max

0

-

+70

-40

-

+85

°C

Units

Power Supply Current:

ID+

(Note 10)

-

2.2

4

-

2.2

4

mA

Power Dissipation:

(Note 10)
PWDN low
PWDN High

-

-

11
0.6

20
2.5

-

11
0.6

20
2.5

mW
mW

-

SWITCHING CHARACTERISTICS (TA = Tmin to Tmax; VD+ = 5V±5%; DGND = OV;
Inputs: logic 0 = OV logic 1 = VD+; CL

= 50 pF (Note 14»

Parameter
ClKIN Frequency

Symbol

Min

Typ

Max

Units

fc

0.512

1.024

1.1

MHz

40

-

60

%

100
100

ns
ns

100
100

ns
ns

-

25

ns

-

ns

-

-

ns

50

ns

50

ns

-

ns

ClKIN Duty Cycle
Rise Times:

Any Digital Input
Any Digital Output

trise

Fall Times:

Any Digital Input
Any Digital Output

tfall

-

50

50

Serial Port Read TiminR
DRDY to Data Valid

tddv

-

RSEl Setup Time before Data Valid

trss

50

Read Setup Before CS Active

trsc

20

Read Active to Data Valid

trdv

SClK rising to New SOD bit
SClK Pulse Width High

trdd
trph

30

SClK Pulse Width low

trpl

30

-

SClK Period

trsp

100

SClK falling to DRDY falling

trs!

CS High to Output Hi-Z

trch

-

Read Hold Time after CS Inactive

trhc

20

Read Select Setup to SClK falling

trds

20

-

-

ns

-

50

ns

20

ns

-

ns

-

ns

-

-

ns

-

ns

Serial Port Write Timing
Write Setup Before CS Active

twsc

20

SClK Pulse Width low

twpl

30

SClK Pulse Width High'

twph

30

SClK Period

twsp

100

Write Setup Time to First SClK falling

twws

20

Data Setup Time to First SClK falling

twds

20

Write Select Hold Time after SClK falling

twwh

20

Write Hold Time after CS Inactive

twhc

20

DATA Hold Time after SClK falling
Note: 14. Guaranteed by design, characterization and/or test.

twdh

20

2-250

-

-

-

-

-

ns
ns
ns
ns
ns
ns
ns
ns

DS70F1

. ....,............._..
.."

~

.."..,,~

..".."

CS5322

~

RSEL

~trst

DRDY

RIW

CS

SOD

MSB

MSB-1

SCLK

SERIAL PORT READ TIMING (R/W = 1, CS = 0, RSEL = 1
• DRDY Does not toggle if reading status, RSEL = 0)

CS

IL------~------J:t-

RIW

twwh

SCLK

SID

~-----'x'-_--'

LSB

'!If.lJ1

SERIAL PORT WRITE TIMING

Figure 11. CS5322 Serial Port

DS70F1

2-251

..............
..........,.
...........

CS5322

SWITCHING CHARACTERISTICS (continued)
Parameter

Symbol

Min

Typ

Max

SYNC Setup Time to ClKIN rising

tss

20

SYNC Hold Time after ClKIN rising

tsh

20

TDATA Setup Time to ClKIN rising after SYNC

tlds

-

TDATA Hold Time after ClKIN rising

tldh

-

150

ORCAl Setup Time to ClKIN rising

tos

20

-

ORCAl Hold Time after ClKIN rising

toh

20

Units

Test Data (TDATA) Timing

20

-

-

ns
ns
ns
ns
ns

-

ns

-

ns

DRDYTiming
ClKIN rising to DRDY falling

tdf

ClKIN falling to DRDY rising

tdr

ClKIN rising to ERROR change

tee

-

RESET Setup Time to ClKIN rising

trs

20

RESET Hold Time after ClKIN rising

trh

20

SYNC Setup Time to ClKIN rising

tss

20

SYNC Hold Time after ClKIN rising

tsh

20

140
150
140

-

ns
ns

RESET Timing

-

-

-

ns

-

ns

-

ns

-

ns

ClKIN

SYNC

ORCAl

lSYNC'

TDATA

FilTER
SAMPLES
DATA

t

t

* Note: Internal timing signal generated in the CS5322

Figure 12. TDATA Setup/Hold Timing

2·252

DS70F1

...............
.. ... -....

.., ~

.",.",

..,

CLKIN

SYNC

LSYNC"

DRDY

CS5322

JlJ\JlJ

n
n
~

ERROR

~
%
%
%
%
~
%
%
%
%
~
%

?

%
%
%
%
;::
f.
~

"Note: For overwrite case, DRDY will remain high.

Figure 13. DRDY Timing

ClKIN

RESET

I

tsh

~

SYNC

Figure 14. RESET Timing

DS70F1

2-253

...............
..,.. - ._.
..............

CS5322

SWITCHING CHARACTERISTICS (continued)
Parameter

MClK Frequency

Symbol

Min

Typ

Max

Units

fc

0.512
40

1.024

1.1

MHz

50
-

60

%

100
200

ns
ns

50

100
200

ns
ns

-

ns

-

ns

(Note 15)

MClK Duty Cycle
Rise Times:

Any Digital Input
Any Digital Output

(Note 16)

trise

Fall Times:

Any Digital Input
Any Digital Output

(Note 16)

!tall

-

tss
tsh

20
20

-

ClKIN edge to MClK edge

tmss

-

30

MClK rising to Valid MDATA

tmsh

SYNC Setup Time to ClKIN rising
SYNC Hold Time after ClKIN rising

-

50

-

ns
ns

MSYNC Delay from MClK rising
(Note 17)
90
tmsd
Notes: 15. If MClK is removed, the device will enter the power down mode.
16. Excludes MClK input. MClK should be driven with a signal having rise and fall times of
25 ns or faster.
17. Only the rising edge of MSYNC relative to MClK is used to synchronize the device. MSYNC
can return low at any time as long as it remains high for at least one MClK cycle.

ns

elKIN
tss

SYNC

lSYNC'

-.J

~

tsh

~ \\~ill\~~~
~
~

J.-tmss

MClK
tmsd

MSYNC

MDATA

FilTER
SAMPLES
DATA
MFlG

VALID DATA
____________
---'. _Et

msh

_

t
_ _ _ _ _------'1

VALID DATA

t

L

• Internal timing signal generated in the CS5322

Figure 15. CS53221CS5323 Interface Timing
2-254

DS70F1

.-____-

....
..... .. ......
._.
~---

CS5322

DIGITAL CHARACTERISTICS (TA = Tmin to T max; VD+ = 5.0V±5%; GND = OV;

measurements

performed under static conditions)
Parameter

Symbol

Min

Typ

Max

Units

High-Level Input Drive Voltage

VIH

(VD+)-0.3

-

V

Low-Level Input Drive Voltage

VIL

-

-

0.3

V

-

V

1.0

V

-

V

0.4
0.4

V
V

+10

I1A

±10

!lA

-

pF

High-Level Input Threshold

(Note 18)

Low-Level Input Threshold
High-Level Output Voltage

(VD+)-1.0

-

(Note 18)
lOUT = -4OI1A

Low-Level Output Voltage

(Note 19)

VOH

(Note 19)
CS5322
CS5323

VOL

lOUT = + 1.6mA
lOUT = +4OI1A
All pins except MFLG, SOD

Input Leakage Current

ILKG

Three-State Leakage Current

loz

Digital Input Capacitance

CIN

Digital Output Capacitance

(VD+)-0.6

-

9

9
COUT
Notes: 18. Device is intended to be driven with CMOS logic levels.
19. Device is intended to be interfaced to CMOS logic. Resistive loads are not recommended on
these pins.

RECOMMENDED OPERATING CONDITIONS (Voltages with
Parameter

pF

respect to GND = OV)

Symbol

Min

Typ

Max

Units

VA+
VAVD+
VD-

4.75
-4.75
4.75
-4.75

5.0
-5.0
5.0
-5.0

5.25
-5.25
5.25
-5.25

V
V
V
V

(Note 20)

DC Supply:
Positive Analog
Negative Analog
Positive Digital
Negative Digital

0
TA
+70
°C
-40
°C
TA
+85
Notes: 20. The maximum voltage differential between the Positive Supply of the CS5323 and the Positive Digital
Supply of the CS5322 must be less than 0.25V.
Ambient Operating Temperature

-KL
-BL

ABSOLUTE MAXIMUM RATINGS* (Voltages with
Parameter

respect to GND = OV)

Symbol

Min

Typ

Max

Units

VA+
VAVD+
VD-

-0.3
0.3
-0.3
0.3

-

6.0
-6.0
(VA+)+0.3
-6.0

V
V
V
V

lin

-

-

±10

mA

VIND
VIND

-0.3
-0.3

-

(VD+)+0.3
(VA+)+0.3

V
V

150

°C

(Note 20)

DC Supply:
Positive Analog
Negative Analog
Positive Digital
Negative Digital
Input Current, Any Pin Except Supplies
Digital Input Voltage

CS5322
CS5323

(Note 21)

-65
Storage Temperature
Tstg
Notes: 21. Transient currents of up to 100 mA will not cause SCR latch up.
'WARNING:

DS70F1

-

Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

2-255

_..................
........
__ .... _.-

CS53221CS5323

GENERAL DESCRIPTION

The CS5322 is a monolithic digital Finite impulse Response (FIR) filter with programmable
decimation. The CS5323 is a monolithic CMOS
AID converter designed specifically for very
high resolution measurement of signals between
dc and 1500 Hz. The CS5322 and CS5323 are
intended to be used together to form a unique
high resolution AID system.
The CS5323 utilizes a fourth order oversampling
architecture to achieve high resolution AID conversion. The modulator consists of a I-bit AID
converter embedded in a negative feedback loop.
The first stage of the fourth order modulator uses
discrete components external to the chip to
maximize signal to noise. The modulator provides an oversampled serial bit stream at 256
Kbits per second (CLKIN = 1.024 MHz) to the
CS5322 FIR decimation filter.

The CS5322 provides the digital anti-alias filter
for the CS5323 modulator output. The CS5322
consists of: A multi-stage FIR filter, four registers (status, data, offset, and configuration), a
flexible serial input and output port, and a 2channel input data multiplexer that selects data
from the CS5323 (MDATA) or user test data
(TDATA). The CS5322 decimates (64X to
4096X) the output to any of seven selectable update periods: 16, 8, 4, 2, 1, 0.5 and 0.25
milliseconds. Data is output from the digital filter in a 24-bit serial format. Figure 16 illustrates
the CS5322 Block Diagram.

CS5323 Signal Input and Current Reference

The CS5323 uses a number of external discrete
components to achieve maximum rated performance. Figure 17 illustrates the recommended
circuit configuration for the current reference
and signal input components.
TDATA

SID
CSEl
PWDN
ORCAl
USEOR
DECC
DECB
DECA

~
~

~
~
~
~

>----------,--J

His >------>j

::=:

I

DATA MUX

CONRG REGI

~

CONFIG MUX

1
r---

r

cs

r----o
RiW r----o
MFlG r----o

I
FIR1

~

SClK
ClKIN
RESET f----J
SYNC f----J

DRDY
ERROR
MSYNC
MClK

MDATA

CONTROL

I+-

FIR2

I
FIR3

~

f---

I
DATA REG

STATUS REG

I
BIT SELECT

BIT SELECT

I
RSEl

MUX

I

~
SOD

Figure 16. CS5322 Block Diagram
2-256

DS70F1

..,......,..,..,.
.
....
..,.., .....

.

-~-

CS53221CS5323

The CS5323 is designed to use a current reference of 1 rnA into the IREF pin. A current
reference rather than a voltage reference was
chosen to achieve better noise performance. For
optimum performance the dc source impedance
at the lREF pin should be approximately 10 kO.
This calls for a 10 volt reference source driving
the 10 kO (R6 + R7) resistor to achieve the desired 1 rnA current source. The IREF input sets
the full scale gain of the NO converter.
A current source 114 the size of the IREF input
current must be sourced into the integrator summing junction at the SUM pin. This requires a
40 kO resistance (14 + R5) be placed from the
10 volt reference to the SUM pin.
+5V

The 1 rnA IREF current and the 250 IlA sources
have capacitive filtering to aid in reducing the
broadband current noise from the voltage reference. These capacitors should be of qUality
construction. Particular attention should be paid
to leakage current variation over the desired operating temperature, as this leakage will affect
the system gain.
The signal input pin (SUM) of the CS5323 is the
summing junction of the input integrator stage.
This integrator is designed to use an external input resistor (RI) and integrating capacitor (CI).
In addition, a capacitor (C2) is required at this
node for proper compensation of the integrator.
The size of the input resistor (R 1) is determined

10n

Analog >-----4~~--=-,.---::,_____---A/iNv-__,_---_____,
Supply

+5V

·5V

Digital )--_---1 f-----.---,
Supply

+5V

Analog
Supply

Digital )--4---11--+----,
Supply

• C 1
C 1

Unused logic
inputs must be
connected to

DGNDorVD+

=2.7nF lor ClKIN =1.024MHz
=5.6nF lor ClKIN =512kHz

Figure 17. System Connection Diagram
DS70F1

2-257

I

. . . . . .,'
_

_-..-

... .. .......
......
~

~

by the magnitude of the signal current. With a
maximum input voltage onto the resistor, the integrator input current must be set equal to
approximately 0.15 the current value injected
into the IREF pin. With almA IREF current,
the full scale signal current should be about 150
~A. Additionally, to minimize current noise into
the summing junction, the value of the effective
input resistor should be above 8 ill. Using the
64.9 k,Q resistor for Rl sets the full scale input
voltage onto the integrating resistor to a value
near 10 volts. The input signal then spans
20 Vp-p.
The integrator resistor and capacitor combination
should yield a frequency (f=1I(21tRICl)) between 850 and 950 Hz to achieve maximum
performance. This results in a capacitor value of
2.7 nF. The capacitor should be chosen to minimize leakage, dielectric absorption, and the
voltage coefficient of capacitance. High quality
film capacitors may be acceptable in many applications.
The signal into the SFF pin (Signal Feedforward) of the CS5323 bypasses the input stage of
the input integrator and improves distortion performance in the passband. The resistor (R2)
used at this input should be identical in value
and performance characteristics to that of the resistor on the input of the SUM pin (Rl).
Although the CS5323 (Figure 17) input is designed to accept 20 Vp-p, modulator loop
stability can be adversely affected by high frequency out-of-band signals. Therefore, input
signals above 8 kHz should be at least 6 dB below full scale to prevent oscillation in the
modulator loop and to ensure proper conversion
data.

2-258

CS5322iCS5323

RESET Operation

The RESET pin puts the CS5322 into a known
initialized state. RESET is recognized on the
next CLKIN rising edge after the RESET pin has
been brought high (RESET= 1). All internal
logic is initialized when RESET is active.
Normal device operation begins on the second
CLKIN rising edge after RESET is brought low.
The CS5322 will remain in an idle state, not performing convolutions, until triggered by a SYNC
event.
A RESET operation clears memory, sets the data
output register, offset register, and status flags to
all zeroes, and sets the configuration register to
the the state of the corresponding hardware pins
(PWDN, ORCAL, DECC, DECB, DECA,
USEOR, and CSEL). The reset state is entered
on power on, independent of the RESET pin. If
RESET is low, the first CLKIN will exit the
power on reset state.

Power-down Operation

The PWDN pin puts the CS5322 into the powerdown state. The power-down state is entered on
the first CLKIN rising edge after the PWDN pin
is brought high. While in the power-down state,
the MCLK and MSYNC signals to the CS5323
analog modulator are held low. The loss of the
MCLK signal to the modulator causes it to
power-down. The signals on the MDATA and
MFLG pins are ignored. The serial interface of
the CS5322 remains active allowing read and
write operations. Information in the data register, offset register, configuration register, and
convolution data memory are maintained during
power-down. The internal controller requires 64
clock cycles after PWDN is asserted before
CLKIN stops.

DS70F1

. .. ..

......-

.., .,.,.... _.
~.-

~~

~~

CS53221CS5323

The CS5322 exits the power-down state on the
first CLKIN rising edge after the PWDN pin is
brought low. The CS5322 then enters an idle
state until triggered by a SYNC event.

selects between conversion data (data register) or
status information (status register). The selected
serial bit stream is output on the SOD (Serial
Output Data) pin.

To avoid possible high current states while in
the power down state, the following conditions
apply:

On read select, SCLK can either be high or low,
the first bit appears on the SOD pin and should
be latched on the falling edge of SCLK. After
the first SCLK falling edge, each SCLK rising
edge shifts out a new bit. Status reads are 16
bits, and data reads are 24 bits. Both streams are
supplied as MSB first, LSB last.

1. CLKIN must be active for at least 64 clock cycles after PWDN entry.
2. CSEL and TDATA must not both be asserted
high.

SYNC Operation
The SYNC pin is used to start convolutions and
synchronize the CS5322 and CS5323 to an external sampling source or timing reference. The
SYNC event is recognized on the first CLKIN
rising edge after the SYNC pin goes high.
SYNC may remain high indefinitely. Only the
sequence of SYNC rising followed by CLKIN
rising generates a SYNC event.
The SYNC event aligns the output sample and
causes the filter to begin convolutions. The first
SYNC event causes an immediate DRDY provided DRDY is low. Subsequent data ready
events will occur at a rate determined by the
decimation rate inputs DECC, DECB, and
DECA. Multiple SYNC events can be applied
with no effect on operation if they are perfectly
timed according to the decimation rate. Any
SYNC event not in step with the decimation rate
will cause a re-alignment and loss of data.

In the event more SCLK pulses are supplied than
necessary to clock out the requested information,
trailing zeroes will be output for data reads and
trailing LSB's for status reads. If the read operation is terminated before all the bits are read, the
internal bit pointer is reset to the MSB so that a
re-read will give the same data as the first read,
with one exception. The status error flags are
cleared on read and will not be available on a
re-read.
The status error flags must be read before entering the powerdown state. If an error has occurred
before entering powerdown and the status bit
(ERROR) has not been read, the status bits (ERROR, OVERWRITE, MFLG, ACCI and ACC2)
may not be cleared on status reads. Upon exiting
the powerdown state and entering normal operation, the user may be flagged that an error is still
present.
The SOD pin floats when read operation is deactivated (RIW=I, CS=I). This enables the SID
and SOD pins to be tied together to form a bi-directional serial data bus. There is an internal
nominal lOOkQ pull-up resistor on the SOD pin.

Serial Read Operation

Serial read is used to obtain status or conversion
data. The CS, RIW, SCLK, RSEL, and SOD
pins control the read operation. The serial read
operation is activated when CS goes low (CS=O)
with the RIW pin high (RIW=I). The RSEL pin
DS70F1

2-259

I

•

.....
,..,,..,....
.,..,..,-,.
.-.
....
,..,,.., .....

CS53221CS5323

Serial Write Operation

Offset Calibration Operation

Serial write is used to write data to the configuration register. The CS, RIW, SCLK and SID
pins control the serial write operation. The serial
write operation is· activated when CS goes low
(CS=O) with RIW pin low (RIW=O).

The offset calibration routine computes the offset
produced by the CS5323 modulator and stores
this value in the offset register. The USEOR pin
or bit determines if the offset register data is to
be used to correct output words.

Serial input data on the SID pin is sampled on
the falling edge of SCLK. The input bits are
stored in a temporary buffer until either the write
operation is terminated or 8 bits have been received. The data is then parallel loaded into the
configuration register. If fewer than 8 bits are input before the write termination, the other bits
may be indeterminate.

After power is applied to the chip set the
CS5322 must be RESET. To begin an offset calibration, the CS5323 analog input must represent
the offset value. Then in software mode (HIS =
0) the ORCAL bit must be toggled from a low to
a high. In hardware mode the ORCAL pin must
be toggled low for at least one CLKIN cycle,
then taken high (except when ORCAL = 1 and
the CS5322 is RESET as this toggles the ORCAL internally). After ORCAL has been
toggled, the SYNC signal must be applied to the
CS5322. The filter settles on the input value in
56 output words. The output word rate is determined by the state of the the decimation rate
control pins, DECC, DECB, and DECA. On the
57th output word, the CS5322 issues the ORCALD status flag, outputs the offset data sample,
and internally loads the offset register. During
calibration, the offset register value is not used.

Note that a write will occur when CS = 0 and
RIW = 0 even if SCLK is not toggled. Failure to
clock in data with the appropriate number of
SCLKs can leave the configuration register in an
indeterminate condition.
The serial bit stream is received MSB first, LSB
last. The order of the input control data is
PWDN first, followed by ORCAL, USEOR,
CSEL, Reserved, DECC, DECB, and DECA
The configuration data bits are defined in Table 1. The configuration data controls device
operation when only in the software mode, i.e.,
the HIS pin is low (HlS=O). The· Reserved configuration data bit must always· be written low.
Input
Bit #
1 (MSB)

2
3
4

5
6
7

8 (lSB)

Equivalent
Hardware Function
PWDN
ORCAl
USEOR
CSEl
Reserved
DECC
DECB
DECA

If USEOR is high (USEOR=I), subsequent sam-

ples will have the offset subtracted from the
output. The state of USEOR must remain high
for the complete duration of the convolution cyDescription
Standby mode
Self-offset calibration
Use Offset Register
Channel Select
Factory use only
Filter BW selection
Filter BW selection
Filter BW selection

Table 1. Configuration Data Bits

2-260

DS70F1

...-..
.......
..,-- ...
....
~

~

~

~

CS53221CS5323

~

Output
Bit #
1 (MSB)
2
3
4
5
6
7

8
9
10
11
12
13
14
15
16

Function
ERROR
OVERWRITE Error
MFlG Error
ACC1 Error
ACC2 Error
DRDY
1SYNC
ORCAlD
PWDN
ORCAl
USEOR
CSEl
Reserved
DECC
DECB
DECA

Description
Detects one of the errors below
Overwrite Error
Modulator Flag Error
Accumulator 1 Error
Accumulator 2 Error
Data Ready
First sample after SYNC
Offset calibration done
Standby mode
Self-offset calibration
Use Offset Register
Channel Select
Factory use only
Bandwidth Selection Status
Bandwidth Selection Status
Bandwidth Selection Status

-

Table 2. Status Data (from the SOD Pin)

cleo If USEOR is low (USEOR=O), the output
word is not corrected, but the offset register retains its value for later use. The results of the
last calibration will be held in the offset register
until the end of a new calibration, or until the
CS5322 is reset using the RESET pin. USEOR
does not alter the offset register value, only its
usage.
To restart a calibration, ORCAL and SYNC must
be taken low for at least one CLKIN cycle. ORCAL must then be taken high. The calibration
will restart on the next SYNC event. If the ORCAL pin remains in a high state, only a single
calibration will start on the first SYNC signal.

Status Bits
The Status Register is a 16-bit register which allows the user to read the flags and configuration
settings of the CS5322. Table 2 documents the
data bits of the Status Register.

The ERROR bit is active high whenever any of
the four error bits are set due to a fault condition. The ERROR output has a nominal lOOKQ
internal pull-up resistor.
The OVERWRITE bit is set when new conversion data is ready to be loaded into the data
register, but the previous data was not completely read out. This can occur on either of two
conditions: a read operation is in progress or a
read operation was started, then aborted, and not
completed. These two conditions are data read
attempts. The attempt is identified by the first
SCLK low edge (MSB read) of a data register
read. If a data register read is not attempted, the
CS5322 assumes that data is not wanted and
does not assert OVERWRITE, and the old data
is over-written by the new data. On an OVERWRITE condition, the old partially read data is
preserved, and the new data word is lost.
Status reads have no effect on OVERWRITE assert operations. The OVERWRITE bit is cleared
on a status register read or RESET.

The ERROR flag, ERROR, is the OR'ed result
of OVERWRITE, MFLG, ACC1, and ACC2.
DS70F1

2-261

..........._.--.
......-_
.....
_
~
..,

The MFLG error bit reflects the CS5323 MFLG
signal. Any high level on the CS5322 MFLG
pin will set the MFLG status bit. The bit is
cleared on a status register read or RESET operation, only if the MFLG pin on the CS5322
has returned low. A internal nominal 100Kn
pull-down resistor is on the MFLG pin.
The accumulator error bits, ACC1 and ACC2,
indicate that an underflow or overflow has occurred in the FIR1 filter for ACC1, or the FIR2
and FIR3 filters for ACC2. Both errors are
cleared on a status read, provided the error conditions are no longer present. In normal
operation the ACC1 error will only occur when
the input data stream to FIR1 is aliI's for more
than 32 bits. The ACC2 error cannot occur in
normal operation.
The DRDY bit reflects the state of the DRDY
pin. DRDY rising edge indicates that a new data
word has been loaded into the data register and
is available for reading. DRDY will fall after the
SCLK falling edge that reads the data register
LSB. If no data read attempt is made, DRDY
will pulse low for 112 CLKIN cycle, providing a
positive edge on the new data availability. In the
OVERWRITE case, DRDY remains high because new data is not loaded at the normal end
of conversion time.
The lSYNC status bit provides an indication of
the filter group delay. It goes high on the second
output sample after SYNC and is valid for only
that sample. For repetitive SYNC operations,
SYNC must run at one fourth the output word
rate or slower to avoid interfering with the
lSYNC operation. With these slower repetitive
SYNC's or non-periodic SYNC's separated by at
least three output words, lSYNC will occur on
the second output sample after SYNc.

2-262

CS53221CS5323

ORCALD indicates that calibration of the offset
register is complete and the offset sample is
available in the output register. This flag is high
only during that sample and is otherwise low.
The remaining eight status bits (PWDN, ORCAL, USEOR, CSEL, Reserved, DECC,
DECB, AND DECA) provide configuration
readback for the user. These bits echo the control source for the CS5322 such that in the
hardware mode (His=1), they follow the corresponding input pins. In host mode (WS=O) they
follow the corresponding configuration bits.
A brief explanation of the eight bits are as follows:
PWDN - When high, indicates that the CS5322
is in the power-down state.
ORCAL - When high, indicates a potential calibration start.
USEOR - When high, indicates the Offset Register is used. During calibration, this bit will read
zero indicating the offset register is not being
used during calibration.
CSEL - When high, TDATA is selected as the
filter source. When low, the MDATA output signal from the CS5323 is selected as the input
source to the filter.
Reserved - Always reads low.
DECC, DECB, and DECA - Indicate the decimation rate of the filter and are defined in
Table 3.

DS70F1

_

...,..,..........
-._..
.............

CS53221CS5323

DECC

DECB

DECA

Output Word Rate (Hz)

Clocks Filter Output

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

62.5
125
250
500
1000
2000
4000

16384
8192
4096
2048
1024
512
256

Reserved

-

Table 3. Bandwidth Selection: Truth Table

Digital Output and Data Format

Performance

For proper operation the CS5322 must be provided with a CMOS-compatible clock into the
CLKIN pin. The normal operating frequency is
1.024 MHz. This clock determines the input
sample rate. The sample rate is CLKIN/4 while
the output word rate is determined by the status
of the DECC, DECB, and DECA input pins or
configuration bits; depending whether in the
hardware mode or host mode.

The CS5322123 AID converter is intended for
use in seismic and passive sonar applications.
These applications require particularly high dynamic range capability. The CS5322/23 offers
high dynamic range without compromising spectral purity. The CS5322123 typically achieves
120 dB of dynamic range, while maintaining signal/distortion at 110 dB.

The CS5322 computes a serial 24-bit output
word in two's complement format. The output
codes range from decimal -5242880 to
+5242879 for a ±10V sine wave input into the
CS5323 modulator as shown in Table 4.

Modulator
Input Signal
approx. +16Vt
approx. +11 V
approx. +10V

OV

t

Digital Filter Output Code
Decimal
HEX

7FEFFF
57FFFF
4FFFFF
000000
800000
AOOOOO
800000

apJ:lrox. -10V
approx. -11 V
approx. -16Vt
This is an overrange condition

+8384511
+5767167
+5242879
0
-5242880
-5767168
-8388608

Table 4. Output Coding for the CS5322
and CS5323 combination

DS70F1

An AID converter system using the CS5322/23
AID converter as its core was tested using Fast
Fourier Transform techniques. Data was collected from the CS5322/23 serially via a UART
interface to a PC-compatible computer. The output from the CS5322 was submitted to a
windowing algorithm and then to the FFT algorithm. Figure 18 illustrates the performance of
the CS5322123 when tested with a full scale
100 Hz signal for the 2 ms filter selection. The
CS5322123 exhibits some second harmonic but
no third harmonic. The test frequency of 100 Hz
was selected, as this was the center frequency of
a bandpass filter constructed to reject harmonics
and line frequencies present at the output of the
signal generator. Figure 19 illustrates the performance of the CS5322123 (100 Hz input
signal) for the 1 ms filter selection. Note that the
performance of the CS5322123 will generally exceed the capability of most available sine wave
test generators for frequencies between
2-500 Hz. The excess noise is due to the signal
source.
2-263

...--_--_...---_----------

CS53221CS5323

Power Supply Rejection Ratio
0
_20

1- - - - - - - - -

-40

- - - - - - - - -

: : : : : ::

I

: ::

Signal
-60
Amplitude
Relative to -80
Full Scale
(dB)
-100

- - -

-120
-140
-160
-180

0
Input Frequency (Hz)

250

Figure 18. 1024 Point FFT Plot with
Full Scale Input, 100 Hz.

The power supply rejection ratio of the CS5323
is frequency dependent. The rejection for frequencies between dc and fl Hz (CLKIN=1.024
MHz) is nearly constant. Above fl Hz, the
CS5322 digital filter will aid in rejecting interference until the frequencies near CLKINI21.3
(above 48 kHz for CLKIN=1.024 MHz). Power
supply interference above this frequency may
cause noise to be modulated into the passband
(dc to fl Hz), degrading the performance of the
AID.

Power Supply Considerations
-40

- : : : : : : : : :I

-60
Signal
Amplitude -80
Relative to
Full Scale -100
(dB)
-120

: : : : : : : : : :I

-140
-160
Input Frequency (Hz)

500

Figure 19. 1024 Point FFT Plot with
Full Scale Input, 100 Hz.

Clock Source Considerations
To obtain maximum performance from the
CS5322/CS5323 chip set requires a CLKIN signal with a very low level of clock jitter, i.e., less
than 10 picoseconds of jitter. A well designed
crystal-based clock is preferred_ The clock oscillator should have a well-regulated supply, with
local bypass capacitors at the oscillator. The
output from the oscillator should pass through as
few logic gates or counter-divider stages as possible_ Excess clock jitter will reduce the
signal/noise performance of the AID converter.

The system connection diagram, Figure 17, illustrates the recommended power supply
arrangements. The CS5323 has two positive
analog supply pins and two negative analog supply pins. Multiple pins are used to minimize the
possibility of noise coupling on the chip. All six
power supply pins should be decoupled to their
respective grounds, with a 0.1 IlF capacitor located near the device. The digital supplies are
decoupled from the analog supplies with a 100.
resistors to minimize the effects of digital noise
in the converter.
The positive digital power supply of the CS5323
must never exceed either positive analog supply
by more than a diode drop, or the CS5323 could
experience permanent damage_ If separate supplies are used for the analog and digital sections
of the chip, care must be taken that the analog
supply comes up first at power-up. Additionally,
the power supplies to the CS5323 should be active before the reference current generator
supplies the IREF input current.
The maximum voltage differential between the
positive digital supply of the CS5323 and the
positive digital supply of the CS5322 must be
less than 0.25V. Operation beyond this con-

2-264

DS70F1

.........
_...................
.....
_......
straint may result in loss of analog performance
in the CS5322 and CS5323 chip set.
Many seismic or sonar systems are battery powered, and utilize dc-dc converters to generate the
necessary supply voltages for the system. To
minimize the effects of power supply interference, it is desirable to operate the dc-dc
converter at a frequency which is rejected by the
digital filter.

CS53221CS5323

Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your

t.1
I

To achieve maximum performance, the dc-dc
converter operating frequency should be located
below 48 kHz (see Power Supply Rejection). A
synchronous dc-dc converter, whose operating
frequency is derived from the 1.024 MHz clock
used to drive the CS5322, will minimize the potential for "beat frequencies" appearing in the dc
to f1 Hz passband.

DS70F1

i

2·265

.........
...,_..
....,..,..,..,
..,..,~

CS5322

~

CHIP SELECT

CS

FRAME SYNC

SYNC

CLOCK INPUT CLKIN
RESET RESET

~
RIW
~ ~ RSEl

~~
/ /
SClK
MODULATOR SYNC MSYNC ~"l
( ~ SID
MODULATOR FLAG MFlG ~
9
SOD
5

MODULATOR CLOCK
POSITIVE DIGITAL POWER
DIGITAL GROUND

MClK ~

4

3

2

28 27 26 25 ; ; -

6
7

CS5322

VD+ -

8

DGND ~

TOP
VIEW

9

/

MODULATOR DATA MDATA ---./~.
TEST DATA TDATA

10
11

24
23

REGISTER SELECT
SERIAL CLOCK
SERIAL INPUT DATA
SERIAL OUTPUT DATA

r - ERROR ERROR FLAG

22 -

DRDY

DATA READY

21 ' 20 \

VD+

POSITIVE DIGITAL POWER

19
12 13 14 15 16 17 18

READIWRITE

~.
' - DGND

DIGITAL GROUND

ORCAl OFFSET CALIBRATION

CSEl

DECA

DECIMATION RATE CONTROL

His

DECB

DECIMATION RATE CONTROL

POWER DOWN PWDN

DECC

DECIMATION RATE CONTROL

CHANNEL SELECT
HARDWARE/SOFTWARE MODE

USEOR USE OFFSET REGISTER

CS5322 PIN DESCRIPTIONS
Power Supplies

VD+ - Positive Digital Power, PIN 8,21
Positive digital supply voltage. Nominally +5 volts.
DGND - Digital Ground, PIN 9,20
Digital ground reference.
Digital Outputs

MCLK - Modulator Clock Output, PIN 7
A CMOS-compatible clock output (nominally 1.024 MHz) that provides the necessary clock for
operation of the modulator.
MSYNC - Modulator Sync, PIN 5
The transition from a low to high level on this output will re-initialize the CS5323.
ERROR· Error Flag, PIN 23
This signal is the output of an open pull-up NOR gate with a nominal 100 ill pull-up resistor
to which the error status data (OVERWRITE error, MFLG error, ACCI error and ACC2 error)
are inputs. When low, it notifies the host processor that an error condition exists. The ERROR
signal can be wire OR'd together with other filters' outputs. The value of the internal pull-up
resistor is 100 ill.
2·266

DS70F1

_...........
.........
- ..._.-.
..,

~

CS5322

DRDY - Data Ready, PIN 22
When high, data is ready to be shifted out of the serial port data register.
SOD - Serial Output Data, PIN 24
The output coding is 2's complement with the data bits presented MSB first, LSB last. Data
changes on the rising edge of SCLK. An internal nominal 100 kn pull-up resistor is included.
Digital Inputs

MDATA - Modulator Data, PIN 10
Data will be presented in a one-bit serial data stream at a bit rate of 256 KHz;
(CLKIN = 1.024 MHz).
TDATA - Test Data, PIN 11
Input for user test data.
MFLG - Modulator Flag, PIN 6
A transition from a low to high level signals that the CS5323 modulator is unstable due to an
over-range on the analog input. A Status Bit will be set in the digital filter indicating an error
condition. An internal nominal 100 kn pull-down resistor included on the input pin.
RESET - Filter Reset, PIN 4
Performs a hard reset on the chip, all registers and accumulators are cleared. All signals to the
device are locked out except CLKIN. The error flags in the Status Register are set to zero and
the Data Register and Offset Register are set to zero. The configuration register is set to the
values of the corresponding input pins. SYNC must be applied to resume convolutions after
RESET deasserts.
CLKIN - Clock Input, PIN 3
A CMOS-Compatible clock input to this pin (nominally 1.024 MHz) provides the necessary
clock for operation the modulator and filter.
SYNC - Frame Sync, PIN 2
Conversion synchronization input. This signal synchronizes the start of the filter convolution.
More than one SYNC signal can occur with no effect on filter performance, providing the
SYNC signals are perfectly timed at intervals equal to the output sample period.
CSEL - Channel Select, PIN 12
When high, information on the TDATA pin is presented to the digital filter. A low causes data
on the MDATA input to be presented to the digital filter.
PWDN - Powerdown, PIN 14
Powers down the filter when taken high. Convolution cycles in the digital filter and the MCLK
signal are stopped. The registers maintain their data and the serial port remains active. SYNC
must be applied to resume convolutions after PWDN deasserts.

DS70F1

2-267

-

I

.

...-.........
...............
.",~_._.

CS5322

DECA - Decimation Rate Control, PIN 18
See Table 3.
DECB - Decimation Rate Control, PIN 17
See Table 3.
DECC - Decimation Rate Control, PIN 16
See Table 3.

HIS - Hardware/Software Mode Select, PIN 13
When high, the device pins control device operation; when low, the value entered by a prior
configuration write controls device operation.
CS - Chip Select, PIN 1
When high, all signal activity on the SID, RIW and SCLK pins is ignored. The DRDY and
ERROR signals indicate the status of the chip's internal operation.
RIW - Read/Write, PIN 28
Used in conjunction with CS such that when both signals are low, the filter inputs data from
the SID pin on the falling edge of SCLK If CS is low and RIW is high, the filter outputs data
on the SOD pin on the rising edge of SCLK RIW low floats the SOD pin allowing SID and
SOD to be tied together, forming a bidirectional serial data bus.
SCLK - Serial Clock, PIN 26
Clock signal generated by host processor to either input data on the SID input pin, or output
data on the SOD output pin. For write, data must be valid on the SID pin on the falling edge of
SCLK Data changes on the SOD pin on the rising edge of SCLK
SID - Serial Data Input, PIN 25
Data bits are presented MSB first, LSB last. Data is latched on the falling edge of SCLK
RSEL - Register Select, PIN 27
Selects conversion data when high, or status data when low.
USEOR - Use Offset Register, PIN 15
Use offset register value to correct output words when high. Output words will not be offset
corrected when low.
ORCAL - Offset Register Calibrate, PIN 19
Initiates an offset calibration cycle when SYNC goes high after ORCAL has been toggled from
low to high. The offset value is output on the 57th word following SYNC. Subsequent words
will have their offset correction controlled by USEOR.

2-268

DS70F1

.

.....,.,-.......
. ....
.....
~

.,~~

CSS323

TEST

TST

TEST

TST

NC

NO CONNECTION

TEST

TST

NC

NO CONNECTION

CURRENT INPUT REFERENCE

IREF

NC

NO CONNECTION

NEGATIVE ANALOG POWER
POSITIVE ANALOG POWER

MODULATOR FLAG
VA1+ ~
INT -

INTEGRATOR OUTPUT
SIGNAL SUMMATION NODE

SUM ~
/

SIGNAL FEEDFORWARD

SFF .J~.

ANALOG GROUND AGND2

6
7

CS5323

24
23

8

TOP

22

~ VD·

NEGATIVE DIGITAL POWER

-VD+

POSITIVE DIGITAL POWER

VIEW
9
10

21 " 20 \

DGND

DIGITAL GROUND

11

19

MCLK

CLOCK INPUT

12 13 14 15 18 17 18

' C
' - .

MDATA DATA OUTPUT

POSITIVE ANALOG POWER

VA2+

NC

NO CONNECTION

NEGATIVE ANALOG POWER

VA2·

NC

NO CONNECTION

NO CONNECTION

NC

NC

NO CONNECTION

NC

NO CONNECTION

CS5323 PIN DESCRIPTIONS

Power Supplies
VA1+, VA2+ - Positive Analog Power, PINS 7, 12
Positive analog supply voltage. Nominally +5 Volts.
VAl·, VA2· - Negative Analog Power, PINS 6, 13
Negative analog supply voltage. Nominally ·5 Volts.
AGND1, AGND2 - Analog Ground, PINS 5, 11
Analog ground reference.
VD+ - Positive Digital Power, PIN 22
Positive digital supply voltage. Nominally +5 Volts.
VD· - Negative Digital Power, PIN 23
Negative digital supply voltage. Nominally -5 Volts.
DGND - Digital Ground, PIN 21
Digital ground reference.

DS70F1

2·269

•

i

._._.-......__..-_-'*-•
...
..,

CS5323

Analog Inputs

IREF - Current Input Reference Node, PIN 4
This node accepts a 1 rnA reference current to set the signal gain of the AID converter.
SFF - Signal Feedforward, PIN 10
The input signal is fed forward around the integrator input stage by· means of this input pin.
This maximizes· signal performance.
SUM - Signal Summation node, PIN 9
This is the input integrator virtual ground summing junction. The external integrator input
resistor and integrating capacitor are connected to this node, along with a 250 IlA bias current
network.
INT - Integrator Output, PIN 8
Output pin of the input integrator stage. The external integrating capacitor is connected to this
pin for proper operation.
Digital Inputs

MCLK - Clock Input, PIN 20
A CMOS-compatible clock input to this pin (nominally 1.024 MHz) provides the necessary
clock for operation of the modulator, digital filter and data output portions of the AID converter.
MSYNC - Modulator Sync, PIN 25
A transition from a low to high level on this input will re-initialize the CS5323. MSYNC resets
a divide-by-four counter to align the output bit stream from the CS5323 for proper input to the
CS5322.
Digital Outputs

MDATA - Modulator Data Output, PIN 19
Data will be presented in a one-bit serial data stream at a bit rate of 256 kHz.
MFLG - Modulator Flag, PIN 24
A transition from a low to high level signals that the CS5323 modulator is unstable due to an
over-range on the analog input. A Status Bit will be set in the digital filter indicating an error
condition.
Miscellaneous

TST - Test, PINS 1,2,3
Reserved for production test facility. Should be tied to DGND for normal operation.
NC - No Connection, PINS 14,15,16,17,18,26,27,28
No internal connection. Tie to ground for optimum operation.

2-270

DS70F1

_.-_..--__.._-_
...
._.-.

CS5323

PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full-scale (rms) signal to the broadband (rms) noise signal. Broadband noise is
measured with the input grounded within the bandwidth of 1 Hz to f3 Hz. Units in dB.
Signal-to-Distortion
The ratio of the full-scale (rms) signal to the rms sum of all harmonics up to f3 Hz. Units in
dB.
Intermodulation Distortion
The ratio of the rms sum of the two test frequencies (50 and 70 Hz) which are each 6 dB down
from full-scale to the rms sum of all intermodulation components within the the bandwidth of
dc to f3 Hz. Units in dB.
Full Scale Error
The ratio of the difference between the value of the voltage reference and analog input voltage
to the full scale span (two times the voltage reference value). This ratio is calculated after the
effects of offset and the external bias components are removed and the analog input voltage is
adjusted. Measurement of this parameter uses the circuitry illustrated in the System Connection
Diagram. Units in %.
Full Scale Drift
The change in the Full Scale value with temperature. Units in %fOC.
Offset

The difference between the analog ground and the analog voltage necessary to yield an output
code from the CS5323/22 of OOOOOO(H). Measurement of this parameter uses the circuit
configuration illustrated in the System Connection Diagram. Units in mV.
Offset Drift
The change in the Offset value with temperature. Measurement of this parameter uses the
circuit configuration illustrated in the System Connection Diagram. Units in ~V/oC.

DS70F1

2-271

.......

r".-

................ .
~

~~~
~.
~~
."

."

CDB5323

Semiconductor Corporation

Evaluation Board for CS5323 & CS5322
Features

General Description

• DIP switch control of all CS5322 logic
pins
• Header control of all CS5322 logic pins

The CDB5323 is an evaluation board that allows laboratory characterization of the CS53221CS5323 AID
converter chip-set. The chip-set supports seven different
selectable word rates: 4 kHz, 2 kHz, 1 kHz, 500 Hz
250 Hz, 125 Hz and 62.5 Hz. Input to the board is 20
volts peak-to-peak. Output is via header connections to
the CS5322 serial interface.

• Supports manual operation of RESET
and SYNC
ORDERING INFORMATION: CDB5323

SYNC

-=r:..

Headers

0-- +5V

CS5323

Reference
Circuitry

IREF

CS5322

MSYNC

MSYNC

MCLK

MCLK

9

2.048 MHz
Oscillatorl
Divider

DIP Switch
Selections

-5V Analo

+5V Di ital

-5V
Regulator

+5V
Regulator

+15V

-=r:..

MFLG

SFF

+5VAnal

RESET
0--+5V

MDATA
SUM

9

AGND

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

-15V

DGND

+5V

Copyright© Crystal Semiconductor Corporation 1995
(All Rights RBSsrved)

MAR '95
DS70DB5
2·272

. ......-...
.......

.., ......
~

~~

CDB5323

~~

+15V

+15

+5VA

G - - - . - - - . - - - -______-----4~-___1IN

+ 47~F

Tt

LM78L05
ACZ OUT f---------+5VA
GND
O.1~F

D2
1N6276A ~C12

JC14

2 IN
O.1~F

LT1021
10V

VREF
To
(+10V) Figure 2

OUT 6
10K
R16

GND
4

J11

-15V
-15

1:

47~F

D3
1N6276A

C16

-5VA
IN
O.1~F

LM79L05
ACZ OUT

-5VA
O.1~F

GND

JC17

J18

10~F

1

C19

+5V
6.8V

P6KE + 47~F
D1

DGND

C3

C4

G-----

'-

27
1
28
2

I-VS
PWDN
DECC
DECB
DECA
USEOR
ORCAl

100~1 6W

,'"
,'=
.....

=-,"
'.'=
'...

ERROR
RS§:

t-O./'

Sk

+5VD

~
.f.oy

<",

~:

V,
C~ V,

RJW '--"-

Figure 4. CS5322 Filter Interface

RST
TDATA

.0./0 CS_El
.0./0 I-VS

~
.0./0
~
V

15
19

~

Fl1W
SYNC

.Jc

YNC

~

4
11
12
13
14
16
17
18

~
USEOR
ORCAl
SID

DRDY
SOD
SClK
SID
ERROR
RSEl

f.O/' CS

f.o>
R13

RST
TDATA
CSEl

~C

ClK

1

~ 23

CS5322

Figure
5

J6

25
ERROR
RSEl
CS

To

S00
SClK

TI'

1U3A23U3B4

47k
SIPS

MFlG

0ROY

~ rY
I'

3

MDATA

,\----+

=-

~

100k
~R14

PWDN
DECC
DECB
DECA
USEOR
ORCAl

~T+SVn

'--- ~"
L-.~~

,"
,"

,"
,"

~

TDATA

~

_........
...--.-..
......
- .....

CDB5323

DECA
USEOR

ORCAl

SID

ON"

Do not use offset register

OFF

Use offset register

ON"

Disable offset register calibration

OFF

Enable offset register calibration

ON

Sets SID to logic 0

DECB

DECC

PWDN

OFF" Allows pull-up on SID line
ON

ERR

ON

ON"

-

Power down active

ON

Selects configuration register for
operating mode

OFF"

Select hardware pins for operating
mode

ON"

Selects MDATA from modulator

HIS

Select status register

OFF" Select conversion data register
CS

ON"

Chip select active

OFF

Chip select inactive

OFF

Selects TDATA as filter input

Enables write mode via SID pin

ON"

Sets TDATA input to logic 0

OFF

Enables TDATA from J1 header

ON

RIW

Normal Operation

OFF

Sets ERR to logic 0

OFF" Allows CS5322 ERROR output
RSEl

ABC Output Word Rate
000
62.5
Selection
1 00
125
via hardware 010
250
pins
110
500
001
1000
1 01
2000
01 1
4000

CSEl

TDATA

OFF" Enables read mode via SOD pin
OFF = OPEN = 1
"Default to use Figure 6 interface.

OFF = OPEN = 1
"Default to use Figure 6 interface.

Table 1. S3 DIP Switch Selections

Table 2. S4 DIP switch selections

+SVD

--_-_>---..l\jV'v-------<~------__,

T

0.1
C3S

R4

+

lOIlF

Tcs

J2

+sv
+sv
DRDY

To
Figure
4

SOD
SCLK

Figure 5. Serial Latch Interface
DS70DB5

2-277

-

i

.. ......-..
. ............
~~

~

~~

C06S323

~~

Figure 5 illustrates the logic used to drive connections at header J2.
By using the signals at header J2, the evaluation
board can be set up to output its conversion
words into three 74HC595 serial to parallel registers. This provides 24-bit parallel data. Figure 6
illustrates the circuitry which can be interfaced
to the J2 connections to provide an isolated digital interface to three 74HC595 registers (the
circuitry of Figure 6 is not provided on the
board). Signals from connector J2 (+5 volts,
GND, SCLK, SOD, and DRDY) are interfaced
to the GNDI side of the opto-isolated interface.
The 74HC595 registers require SCLK rising to
latch data bits and DRDY rising to parallel latch
data. Jumpers must be placed to select the proper
phase of these signals as the CS5322 provides
data bits to be latched by the falling edge of
SCLK and causes DRDY to fall when the last
data bit is clocked out. A flip-flop is used to delay DRDY by one-half SCLK cycle before it is
used to latch the parallel latch. Jumper J6 (CLK)
is used to connect the 1.024 MHz clock as the
SCLK signal to clock serial data from the chip.
A second isolated +5 volts should be provided to
the GND2 side of the interface. Opto-isolation
eliminates any ground loop between the board
and the computer interface.

Using the Evaluation Board

Connect the appropriate power supplies to the
binding posts of the board. Twist the +5V digital supply lead with the digital ground lead from
the board to the supply. Also twist the supply
leads for the analog voltages. Use a high quality
power supply which is low in noise and line frequency(50/60 Hz) interference.
Power up the supplies. Then connect a coaxial
cable from the analog BNC to the signal source.
Note that the performance of the AID converter
chip set will exceed the capability of most signal
generators, especially with respect to noise and
line frequency interference.
Once power has been applied to the board, connect the ribbon cable to the appropriate headers
(11, J2, and/or 13). The reset and the sync signals to the CS5322 must be applied before
normal operation can commence. This can be
done by using the S2 RESET switch and the S 1
SYNC switch or by interfacing to these signals
via the 11 and 13 headers.

The CS5322 filter should be set up for hardware
mode (HIS on switch S4 open). DIP switch S4
can then be used to select the desired output
word rate. After the selection on the DECA,
DECB, and DECC positions of the S4 DIP
switch, the S2 RESET switch must be activated,
followed by the S 1 SYNC switch (unless these
signals are controlled via the 11 and 13 header
signals).
Figure 7 illustrates the component layout of the
board while figures 8 and 9 illustrate the board
layout (not to scale).

2-278

DS70DB5

,=,.,
'."....,
",
=.,

c
en

II

..

74HC595
0.11J.F

74HC74

J2

I -,101J.F

L-

GND1

. GND2

10

QG

GND

QF

SKClK

QD

SClK

QC

LATCH
ClK

QS
QA

QE

11

4

2
D

VCC
8

+5V
+5

QH

:!-

12

Q

+5V

DIN

3 Cl

14
9

+5vl
16

DOUT
VCC

+5V

8
10

~"'~=
22 pF

~ffI

~

I

~-b
.
-

+5V

3

JJ

12

4

,~;;. at ,:,A:l"" ~,~1 NC:

"" ,"

8

\\.

D19

.....

D18
D17
D16

13

QH

GND

QF

-SKClK

QE
QD

SClK

QC

LATCH
ClK

D21
D20

OE

QG

11

D23(MSS)
D22

QS
QA

CS
D15
D14
D13
D12
D11
D10
D9
D8

47 k
-1')1/

74HC14

U1. U2. U3 = HCPl-2300

QJ
11

A

Cl

= +5

Q

13

!8

Power
'Supply
w"'oo ..
GND

~

16
+5V

:~
6.8 V

8
10

47 IJ.F

QH
VCC

0.11J.F

=

+5V

+5 14
,-1+%10

12

11
12

QG

GND

QF

SKClK

QD

SClK

QC

QE

LATCH
ClK
DIN
14

~I

......

QS
QA
OE

D6
D5
D4
D3
D2
D1
DO
(lSS)

13

I

12en
I

Figure 6_ Suggested Opto-coupled Interface Between AID and Serial-to-parallel Registers (Not Provided)

(lJ

I.

O:J
w
I\)
w

III

m

~
Q

~

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0

AGND

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so

PCS
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O
us

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o

'-15V

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...GND

i~~~~~~
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'15V

n~ (-)(.)(-)
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RI

U

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o

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SOD

!;l
=:I
~

U

"
q,~~"u
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,,' o

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=-,
!-=
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0

UI

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~

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c==:ri
::: U

D

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CDB5323
.

Jl"valuat~on Board

AIN

CRYSTAL

Somlconduc!or Corporo! Ion

SMART Anolog@

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i
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......._....
. ....
....
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CDB5323

~

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...................
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~::::::::::::~_./

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Figure 8. CDB5323 Solder Trace Layer (Not to Scale)

DS70DB5

2-281

I

..........,.., ...
._..
..,

~

..,..,..,

~--

CDB5323

~

Figure 9. CDB5323 Ground Plane Layer (Not to Scale)

2·282

DS70DB5

... ..-......
~~

~

~~

~

."."

~

CS5324

Semiconductor Corporation

120 dB, 500 Hz Oversampling AID Converter
Features

General Description
The CS5324 analog to digital converter is a unique,
very high resolution AID converter intended for geophysical and sonar applications. It is a complete analog
front end to a Digital Signal Processor and provides
the DSP with a low distortion digital input suitable for
precision signal analysis. The CS5324 performs sampling, AID conversion, and anti-alias filtering.

• Monolithic CMOS AID converter
• 120dB Dynamic Range
• dc-500 Hz Bandwidth

The CS5324 uses delta-sigma modulation to produce
highly accurate conversions. The device oversamples
at 256X, virtually eliminating the need for external antialiasing filters. An on-chip linear-phase FIR digital filter
decimates the output to a 32 kHz output word rate.
Data is transmitted to the DSP as two, 8-bit bytes. An
additional FIR filter in the DSP further decimates the
signal to achieve 120 dB dynamic range over 500 Hz
bandwidth with signal-to-distortion of 110 dB.

• 110 dB Total Harmonic Distortion
• Internal Track-and-Hold Amplifier
• Delta-Sigma Architecture
-256X Oversampling
-Linear Phase Digital Filter
-Output Word Rate 32 kHz

The CMOS design of the CS5324 ensures high reliability and power dissipation of less than 180 mW.

• Low Power Dissipation: 150 mW

ORDERING INFORMATION:
CS5324-Bl -40° to +85°C 28-pin PlCC

• Evaluation Board Available

VA1+ VA2.+

7

INT
SUM

VA1-

VA2.-

6

13

12

AGND1 AGND2
5

11

VD+

VD-

DGND

22

23

21

8

9

ANALOG MODULATOR

4
IREF

10
SFF

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

28
FSYNC

FIR 1

15
PWON

14

3

2

~

1

20

~
~
~

D2

~
~

D5

DO
D1

1~ D3

D4

~ 06
~ 07

TST TSA TSB TSC ClKIN

Copyright © C/}'Sta/ Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
OS36F1
2-283

-____-_

.. .....
. ..,--._..
....

CS5324

ANALOG CHARACTERISTICS (TA= Tmin to Tmax; VA-=-5V; VA+= 5V; AGND=OV;
CLKIN=1.024 MHz Device is connected as shown in Figure 1, the System Connection Diagram. Output data is
further processed using off-chip filtering described in Appendix 1.)
Parameter*

Min

Typ

Max

Units

-40

-

+85

°C

DR

116

120

100

110
110

-

dB

SDR

Symbol

Specified Temperature Range
Dynamic Performance

Dynamic Range
Signal-to-Distortion

(Note 1)

Intermodulation Distortion

(Note 2)

-

dB
dB

dcAccuracy

Full Scale Error
Full Scale Drift
Offset
Offset Drift

(Note 3)

-

-

2

%

(Note 3, 4)

-

0.003

0.006

%/oC

(Note 3)

-

-

250

mV

(Note 3, 4)

-

500

750

fl,V1°C

-

500

Hz

+10.0

V

-

12.5
14.5

18
18

mA
mA

150
5

180
10

mW
mW

-

55
45
48
38

-

dB
dB
dB
dB

Input Characteristics

Input Signal Frequencies

(Note 5)

BW

dc

Input Voltage Range

(Note 6)

Yin

-10.0

Power Supplies

(Note 7)

DC Power Supply Currents
Positive Supplies
Negative Supplies
Power Dissipation
PWDN Low
PWDN High
Power Supply Rejection
(dc to 500 Hz)

(Note 7)

VA+
VAVD+
VD-

(Note 8)

-

dB
(Note 9)
60
VA+
dB
VA60
dB
50
VD+
55
dB
VDNotes: 1. Tested with full scale Input signal of 50 Hz.
2. Tested with input signals of 50 Hz and 90 Hz, each 6 dB down from full scale.
3. Specification is for the parameter over the specified temperature range and is for the CS5324 device
only. It does not include the effects of external components.
4. Drift specifications are guaranteed by design and characterization.
5. The upper bandwidth limit is determined by the off-Chip digital filter.
6. This input voltage range is for the configuration depicted in Figure 1, the System Connection Diagram.
7. All outputs unloaded. All logic inputs forced to VA+ or GND.
8. Tested with a 100 mVp-p 120 Hz sine wave applied separately to each supply (VA1 and VA2 are
considered as one input for this test).
9. Tested with a 100 mVp-p 120 kHz sine wave applied separately to each supply (VA1 and VA2 are
considered as one input for this test) .
• Refer to Parameter Definitions (immediately following pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.
(500 Hz to 128 kHz)

2-284

-

DS36F1

_. .............._..

..,.., ..,..,_
..,..,
.,

CS5324

SWITCHING CHARACTERISTICS (TA= Tmin to Tmax; VA+,VD+=5V±5%; VA-,

VD- =-5V±5%;

Inputs: logic 0 = OV logic 1 = VD+; CL=50pF. See Note 10.)
Parameter

ClKIN Frequency

(Note 11)

Symbol

Min

Typ

Max

Units

fe

0.9

1.024

1.1

MHz

40

-

60

%

5

ps

50

1.0
200

!.L s
ns

-

1.0
200

!.Ls
ns
ns
ns

ClKIN Duty Cycle

-

ClKIN Jitter
Rise Times:

Any Digital Input
Any Digital Output

(Note 12)

hise

Fall Times:

Any Digital Input
Any Digital Output

(Note 12)

tlall

-

-

50

-

FSYNC Rising to ClKIN Falling Edge

tIe

150

-

-

Output Data Delay: ClKIN Rising to Valid Data

tdd

200

250

Output Float Delay: ClKIN Rising to Hi-Z

tId

-

150

250

ClKIN Rising Edge to FSYNC Rising

Notes: 10.
11.
12.
13.

(Note 13)

tel

70

ns

ns
Guaranteed by design, characterization and/or test.
If ClKIN is removed the device will enter the power down mode.
Excludes ClKIN input. ClKIN should be driven with a signal having rise and fall times of 25ns or faster.
Only the rising edge of FSYNC relative to ClKIN is used to synchronize the device. FSYNC can return
low at any time as long as it remains high for at least one ClKIN cycle.

DIGITAL CHARACTERISTICS (TA= Tmin to Tmax; VA+,VD+ = 5V±5%; VA-,VD- = -5V±5%)
All measurements below are performed under static conditions.
Symbol

Min

Typ

High-level Input Voltage

VIH

{VD+)-1.0V

low-level Input Voltage

VIL

-

-

±10

!.LA

-

±10

!.LA

-

pF

Parameter

High-level Output Voltage

lOUT = -600 !.LA (Note 14)

VOH

{VD+)-O.4V

low-level Output Voltage

lOUT = 800 !.LA

(Note 14)

VOL

-

Input leakage Current

ILKG

Tri-State leakage Current

loz

Digital Output Pin Capacitance

Max

Units

-

V

1.0

V

-

V

0.4

V

9
COUT
Notes: 14. The device is designed for low current output drive to minimize induced noise. CMOS
interfacing is highly recommended.

ClKIN

~

tdd

-1 LVW

FSYNC

DO-D7

Hi-Z

t

tet

I

~

ttc
High Byte

low Byte

ttd
Hi-Z

Digital Timing Relationships
DS36F1

2-285

-

I,:
I

.. ...
.....,..
-. ..--_
~-

~~~

CS5324

~~

RECOMMENDED OPERATING CONDITIONS

(DGND=OV; AGND=OV. All voltages meas-

ured with respect to ground.)
Parameter

Symbol

Min

Typ

Max

Units

VA+
VAVD+
VD-

4.75
-4.75
4.75
-4.75

5.0
-5.0
5.0
-5.0

5.25
-5.25
5.25
-5.25

V
V
V
V

DC Supply
Positive Analog
Negative Analog
Positive Digital
Negative Digital

ABSOLUTE MAXIMUM RATINGS

(DGND=OV; AGND=OV. All voltages measured with respect

to ground.)
Parameter

DC Supply

Positive Digital
Negative Digital
Positive Analog
Negative Analog

Input Current, Any Pin Except supplies
Digital Input Voltage
Ambient Operating Temperature
Storage Temperature
Note:

(Note 15)

Symbol

Min

Max

Units

VD+
VDVA+
VA-

-0.3
0.3
-0.3
0.3

(VA+)+0.3
-6.0
6.0
-6.0

V
V
V
V

lin

-

±10

rnA

VIND

-0.3

(VA+)+0.3

V

TA

-55

125

°C

-65

150

°C

Tstg
15. Transient currents up to 100 rnA will not cause SCR latch-up.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

2-286

DS36F1

........_.-.
......
_...............
.-

~

General Description
The CS5324 is a monolithic CMOS AID converter designed specifically for very high
resolution measurement of signals between dc
and 500 Hz. The device consists of a fourth-order
delta-sigma modulator followed by an on-chip
digital decimation filter.
The modulator of the CS5324 samples the analog
input signal at a 256X oversampling rate. This
high oversampling rate, along with subsequent
digital filtering, enables the CS5324 to achieve a
dynamic range which exceeds 120dB. To achieve
optimum performance, the CS5324 uses off-chip
circuitry to develop the reference and operating
currents necessary to set the gain and offset of
the modulator portion of the AID converter. Discrete components are also used for the first stage
integrator input resistor and integration capacitor.
The CS5324 performs conversions continuously
and outputs twelve data bits for further data decimation by an off-chip digital filter. A separate
DSP chip can be utilized to perform the off-chip
filtering. A single DSP chip can perform the filter
function for several CS5324 devices. For this reason, the CS5324 was designed to output its data
in a simple time-division multiplexing (TDM)
format. This TDM architecture allows up to eight
CS5324 devices to share the same data bus.

Theory of Operation
The CS5324 utilizes a fourth order oversampling
delta-sigma architecture to achieve high-resolution AID conversion. The converter consists of an
analog modulator, along with an on-chip digital
decimation filter. The modulator consists of a
I-bit AID converter embedded in a negative feedback loop. The first stage of the fourth order
modulator uses discrete components external to
the chip to maximize signal performance relative
to noise.

DS36F1

CS5324

The modulator samples at 256 kHz
(CLKIN = 1.024 MHz) which is 256X overs ampiing above two times the maximum signal
frequency of 500 Hz. The modulator output is
followed by a decimate by 8, fourth-order
(sinx)/x filter. The result from this filter is a 12bit word which is output from the chip at a 32
kHz rate. The 12-bit data is then further filtered
by means of an off-chip digital filter. The off-chip
filter can be implemented by either a DSP chip or
an ASIC designed for this purpose. The exact
characteristics of the on-chip filter and some recommended off-chip digital filters are discussed
under the Filter Characteristics section of the data
sheet. Upon reduction with the off-chip filtering,
the data results in resolution which exceeds 20bits. The final result yields a dynamic range
exceeding 120 dB.
The architecture of the CS5324 was chosen to
maximize performance. The input integrator uses
off-chip discrete components. The chip is designed to use a current-source type reference,
rather than a voltage source to minimize noise. In
addition, the amount of on-chip digital filtering is
minimized to reduce the possibility of the digital
noise of the filter coupling into the analog sections of the chip. Configuring the chip to use
additional off-chip digital filtering also allows the
user maximum flexibility in implementing a filter
appropriate to his system requirements.

Signal Input and Current Reference
The CS5324 uses a number of external discrete
components to achieve maximum performance.
Figure I illustrates the recommended circuit configuration for the current reference components
and for the signal input components.
The CS5324 is designed to use a current reference of 2 mA into the IREF pin. A current
reference rather than a voltage reference was chosen to achieve better noise performance. For
optimum performance the dc source impedance at
2-287

~,;i,'

I'.-.

..............
..,-- ._.
..............

(;55324

tor summing junction at the SUM pin. This re.
quires a 20 ill resistance (R4+R5) be placed from
the 10 V reference to the SUM pin.

the IREF pin should be approximately 5 ill. This
calls for a 10 volt source driving the 5 ill
(R6+R7) resistor to achieve the desired 2 rnA current source. The IREF input sets the full scale
gain of the AID converter.

Both the 2 rnA lREF current and the 500 /lA
sources have capacitive filtering to aid in reducing the broadband current noise from the voltage
reference. These capacitors should be of quality
construction. Particular attention should be paid

To properly bias the input integrator to a midrange
operating point, a current source 114 the size of the
IREF input current must be sourced into the integra+5V
Analog

100
>-----.~...._-----_._--'w\j\~.._-----...._-____,

Supply

+
10~F~
VA1+
.-_-._5=-J AGND1

22
VD+

DGND e=2-'.-1----l___- - '

TSA 3
TSB

1.1 kO

+10V
VREF

IREF

Control
Logic

TSC

CS5324
8 INT

l500~
DO
01

02

Off- chip
Digital
Filter
System

~

L-_J\f\A~_ _ _ _ _ _ _ _ _~1~0 SFF

32.4 kO
.-_-----._--'-1"-13 VA2-

0.1

~F

.---_._--'-1-'-11 AGND2

-5V
Analog > - - - - - - 4 - - - - - - -____~NIf'v--+_---___,
Supply

0.1

Unused logic inputs
must be connected
to DGND or VD+

~F~

Figure 1. System Connection Diagram

2-288

DS36F1

_-_
_. .....__-.......
...-..
-.-

CS5324

to leakage current variation over the desired operating temperature, as this leakage will affect the
system gain.
The signal input pin (SUM) of the CS5324 is the
summing junction of the input integrator stage.
This integrator is designed to use an external input resistor (RI) and integrating capacitor (Cl). In
addition, a capacitor (C2) is required at this node
for proper phase compensation. The size of the
input resistor (Rl) is determined by the magnitude of the signal current. With a maximum input
voltage into the resistor, the integrator input current must be set equal to approximately 0.15 the
current value injected into the IREF pin. With a 2
rnA IREF current, the full scale signal current
should be about 300 1lA. Additionally, to minimize current noise into the summing junction, the
value of the effective input resistance should be
above 8 kil. Using a 32.4 kil resistor for Rl sets
the full scale input voltage into the integrating resistor to a value near 10 volts. The input signal
then spans 20 Vpop.
Once the integrator input resistor is chosen, the
integrator capacitor can be determined. The resistor and capacitor combination should yield a
frequency (f= 1I(21t RICI» between 800 and
900 Hz to achieve maximum performance. This
yields a capacitor value near 5.6 nE The capacitor should be chosen for minimum leakage,
minimum dielectric absorption, and minimum
voltage coefficient of capacitance. While a teflon
foilwrap capacitor is preferred, high quality film
capacitors may be acceptable in many applications.

The CS5324 has a second signal input pin called
the Signal Feedforward (SFF) pin. The signal
into this pin bypasses the input stage of the input
integrator, improving signal performance in the
passband. The resistor (R2) used at this input
should be identical in value and performance
characteristics to the input resistor (RI).
Digital Output and Data Format
For proper operation the CS5324 must be provided with a CMOS-compatible clock into the
CLKIN pin. The normal operating frequency is
1.024 MHz. This clock determines the input sample rate and the output word rate of the converter.
The sample rate is CLKIN/4 while the output
word rate is at CLKIN/32.
The CS5324 will compute a 12-bit output word
at a 32 kHz rate (CLKIN = 1.024 MHz). The
data is output from Data Output pins D7-DO in
the form of two eight bit bytes. The first byte is
the high order byte with the MSB in the D7 position. The second 8-bit byte is the low order byte,
and includes three status bits and an unused bit.
The data is in two's complement format. Figure 2
illustrates the format of the output data.
For 12-bit two's complement data the codes
range from -2048 to +2047. The output codes
from the CS5324 will range from approximately
-1280 to +1280 for a full scale sine wave input
into the converter as shown in Table 1. There
may be typically ±50 codes of noise (p-p) on the
data in the 12-bit data output. Off-chip digital filtering is required to achieve the full dynamic
range capability of the CS5324.

HiB~e ~~~~~~r-~~~~~--~~~~~~~-+~~~
LoB~eL-~~~~~~~-L~~~~__~~__L-~~~~~

Data is 2's complement with B11 as sign bit

Figure 2. Output Data Format
DS36F1

2-289

,.
l'

. ......-...
._.-.
....
~

~~~

~

CS5324

~~

Input Signal

Output Code

approx. + 16V

0111

1111

+F.S. - 1.S LSB (approx. +10V)

0101

0000 0000

OV

0000 0000 0000

-F.S. + O.S LSB (approx. -10V)

1011 0000 0000

approx. -16V

1000 0000 0000

1111

Notes: 1. Output codes from the on-chip digital filter
will typically exhibit ±SO LSB's of noise (p-p).
2. Table depicts output codes for circuit
configuration of Figure 1.

Table 1. Output Coding

Status Bits
Three status bits are output from the CS5324.
The three status bits are overflow, underflow, and
oscillation reset. The overflow and underflow
status bits indicate whenever the digital filter accumulator results in an overflow or underflow
condition. With the present on-chip digital filter,
the underflow condition will never occur. The
overflow bit will go high indicating an accumulator overflow only if the input signal to the
converter exceeds positive full scale by approximately 1.6X. Upon overflow, the accumulator
will contain the value +2047 (or 2048 after underflow). The oscillation reset status bit indicates
that output data may be in error. An oscillation
detection circuit monitors the modulator loop to
see if it is operating within its stable operating
range. If the modulator is operating outside its
normal operating range the output data may be
corrupted. The ORST status bit may go high as a
result of power-up, or, if the input signal exceeds
the specified full scale input value. If ORST does
occur, it will remain high for a total of four update cycles (of 32 kHz) to the output port; while
the modulator and the digital filter are reset. Once
ORST goes back low, output data will not be
valid until the modulator and the digital filter(s)
settle.
2-290

Initialization and Output Data Sequencing
The CS5324 updates its output register at a
32 kHz rate (CLKIN = 1.024 MHz). Between updates 32 CLKIN cycles occur; The CS5324 is
designed such that eight data output time slots
occur during these 32 CLKIN cycles. Each time
slot lasts for 4 CLKIN cycles. The CS5324 is designed to allow eight devices to share the same
8-bit data bus when each device is set-up to output its data in an individual time slot. The exact
time the CS5324 will output data is determined
by the TSA, TSB, TSC, and FSYNC inputs.
After power is applied to the deVices, the FSYNC
input must be brought high. When FSYNC is
brought high (within the required timing specifications), each chip will be assigned to a data
output time slot according to the logic levels of
its TSA, TSB, and TSC inputs. Table 2 tabulates
the decoding of these inputs.
If all theCS5324s in the system are initialized
with the same FSYNC signal, they will all compute filter results in phase with each other and
update their output registers at the same time.
Only the time slot in which the data is output
from the devices is different.
The FSYNC signal used to initialize the CS5324
need only be activated once after power up. In
some systems, it may be preferable to have this
TSA

TSB

TSC

Time Slot

0

0

0

TSO

0

0

1

TS1

0

1

0

TS2

0

1

1

TS3

1

0

0

TS4

1

0

1

TSS

1

1

0

TS6

1

1

1

TS7

Table 2. Time - Slot Decoding
DS36F1

.._-_
_.--..__.....
...-.
,..,

.-.

CS5324

signal occur every 32 CLKIN cycles. Only the
occurrence of the rising edge of FSYNC is significant in determining the system initialization.
Figure 3 illustrates a system configuration using
multiple CS5324s interfaced to the same DSP
chip.

..

CS5324
ClKIN

~

,-------' FSYNC

TSATSB TSC

0

0

I

0

CS5324

Four cycles of CLKIN occur during each time
slot. During the time slot designated for a
CS5324 to output its data, the high-order byte
will be output for the first two CLKIN cycles of
the time slot. The second byte will be output during the last two CLKIN cycles of the period.

ClKIN

f------+

0

While the on-chip filter is fixed in its characteristics, the off-chip filter will be defined by the
system requirements of the particular application.
A low pass filter specification to be used with the
DS36F1

8~

DSP

0

•

1

•
•

CS5324
ClKIN

----.

FSYNC

f--*

TSATSB TSC
ClKIN

The CS5324 utilizes a fourth-order delta-sigma
modulator which has superb linearity. The full capability of the AID conversion block can be
obtained with an appropriate digital filter. Many
applications, (seismic applications in particular)
require the AID conversion function to accurately
reproduce the pulse shape of the input signal
waveform, not just the spectral content. To accurately digitize the shape of the input signal
requires a linear phase response in the signal
processing system. Any non-linearities in the
phase response of the signal processing system
will corrupt the true waveshape information. For
this reason, the design of the digital filtering to
be used with the CS5324 should include particular attention to the phase characteristics of the
filter function.

I

TSATSB TSC

If four or less CS5324's share the same data bus,
it is preferable to use alternate time slots
(i.e. TSO, TS2, TS4, TS6) to minimize the possibility of bus contention problems. Slight timing
differences between chips may result in timing
overlap if adjacent time slots are used.

Filter Characteristics

8

FSYNC

FSYNC

Figure 3. Multiple CS5324 to DSP Interface.

CS5324 will include the following parameters:
Passband ripple (or flatness); group delay or
phase characteristics; transition band roll off; stop
band rejection; and filter complexity. All of these
parameters are interrelated in any given filter design. There is no one particular solution to be
used with the CS5324.
The CS5324 samples the input signal at 256 kHz
(CLKIN = 1.024 MHz). With a signal bandwidth
of 500 Hz, the output data rate from the AID system (including the off-chip digital filtering) need
only be 1 kHz to adequately represent the input
signal. For this reason, it is desirable to decimate
the 256 kHz sample rate to 1 kHz. To accomplish
this while also providing the necessary low-pass
filtering, three stages of filtering are utilized. The
first of these is the on-chip filter. This filter is a
decimate-by-8 function, and reduces the output
word rate from the CS5324 chip to 32 kHz. Two
additional filtering stages are to be implemented
off-chip with either a DSP, a dedicated ASIC, or
another computing device. The first off-chip stage
2-291

.. ...-....
. ....
....
~-

~~~

.."

CS5324

~-

1+14-------------321ClKN

ClKIN

FSYNC

TSO

OUTPUT
TS1

OUTPUT

~I

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J----------------------'lf)('r-)- - - - - - - - - - - - - - - - - - - - -

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~H~I-~Z~____________~

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Note:

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Up to eight AID converters can share the same digital output bus as long as each converter is
assigned to put out its data in a different time slot with respect to all other converters on the bus.
Figure 4. Data Output Sequence for Multiple CS5324s.

is a decimate-by-8 function, which reduces the
output word rate to 4 kHz. The last stage will be
a decimate-by-4 function,. which will reduce the
word rate to 1 kHz. The filter stages are designed
so that the first filter has zeroes in its transfer
function, such that it rejects the aliased components, due to the first decimate-by-8. The second
stage has zeroes such that it rejects the aliased
components due to the second decimate-by-8.
Neither the on-chip filter, nor the first off-chip
stage fI!ally affect the passband, but instead, these
two stages reduce the output data rate, while at
the same time providing anti-alias filtering. The
third stage provides the low-pass filteringfunction.

Hz bands is 147 dB. The data output from the
on-chip filter has been described in the Data Output and Data Format section above. Data is
output at a 32 kHz rate.

0.00

~

-20.00

iIi'

-40.00

CI)

-60.00

~
"0

:E

is.

-80.00

\

\

~

\

(

E -100.00

c(

\

\ /

/"'\

-120.00

~

\ /

\

96.00

12 .00

\ I

\

-140.00
-160.00

The CS5324 includes an on-chip 29th-order linear phase FIR (finite-impulse-response) filter and
decimator. The response of this filter is illustrated
in Figure 5. The filter coefficients are listed in
Table 3. The filter performs a fourth-order sinc
function, and has a monotonic rolloff in the passband. Attenuation at 500Hz is 0.0137 dB. The
minimum attenuation in the (n x 32 kHz) +/-500
2-292

-180.00
-200.00
0.00

32.00

64.00
Frequency [kHz)

Figure 5. On-chip Filter Response

DS36F1

.-___-_-_

._..
.... ..... .....
~

CS5324

28

X(z) =

L h(n+1) z-n
n=O

Coefficient
h(1) = h(29l
h(2) = h(28)
h(3l - h(27l
h(4) = h(26)
h(5l = h(25l
h(6) = h(24)
h(7l - h(23l
h(8) = h(22)
h(9l - h(21l
h(10) = h{2Q)
h(11l = h(19l
h(12) = h(16)
h(13l = h(17l
h(14) - h(16)
h(15)

Value
1.00
4.00
10.00
20.00
35.00
56.00
84.00
120.00
161.00
204.00
246.00
284.00
315.00
336.00
344.00

Table 3. On-chip Filter Coefficients

The two proposed off-chip filter stages are as follows: The first off-chip stage is a 43rd-order
modified sinc FIR filter. Its coefficients are listed
in Appendix 1, along with a plot of its transfer
function. Attenuation at 500 Hz (CLKIN = 1.024
MHz) is 1.47 dB. The minimum attenuation in
the (n x 4 kHz) +1- 500 Hz bands is 132 dB.
The second off-chip filter stage is a 301st-order
FIR filter that performs the necessary low-pass
function, with less than 0.00016 dB ripple in the
dc-400 Hz band. Attenuation in the region from
500 Hz to 2 kHz is typically greater than 130 dB.
The coefficients for the second off-chip filter
stage are listed in Appendix 1, along with a plot
of its transfer function. An alternate final stage
filter is also listed in Appendix 1. It is a 201st-order FIR filter and allows more passband ripple
(0.07 dB).

CS5324 Performance
The CS5324 AID converter is intended for use in
seismic and passive sonar applications. These applications require particularly high dynamic range
capability. The CS5324 offers high dynamic
range without compromising spectral purity. The
CS5324 typically achieves 120 dB of dynamic
range, while maintaining signal/distortion at
110 dB.
An AID converter system using the CS5324 AID
converter as its core was tested using Fast Fourier
Transform techniques. The CS5324 was connected using the components as shown in the
system connection diagram, Figure 1. Data was
collected from the CS5324 with the use of a parallel 1/0 card in a PC-compatible computer.
Software was used to implement the two stage
digital filtering function. The output from the
digital filtering software was submitted to a windowing algorithm and then to the FFT algorithm.
Figure 6 illustrates the performance of the
CS5324 when tested with a full scale 113 Hz signal. The CS5324 exhibits some second harmonic
but no third harmonic. The test frequency of
113 Hz was selected, as this was the center frequency of a bandpass filter, constructed to reject
harmonics and line frequencies present at the output of the signal generator. Note that the
performance of the CS5324 will generally exceed
the capability of most available sine wave test
generators for frequencies between 2-500 Hz, as
is the case in Figure 6. The excess noise, in this
case, is due to the signal source. Figure 7 illustrates the performance of the CS5324 with a -60
dB 100 Hz input signal. The CS5324 is capable
of converting with minimal intermodu1ation distortion as depicted in Figure 8.

If more ripple or less stop band rejection is ac-

ceptable, the off-chip filter complexity can be
reduced. The filter examples given have been illustrated only as possible filters which can be
utilized with the CS5324 to achieve quality performance from the AID.
DS36F1

2-293

_.

. ....,................
~

~

~~

~~

:CS5324

~

Clock Source Considerations

Power Supply Considerations

To obtain maximum performance from the
CS5324 requires a CLKIN signal which has a
low level of clock jitter, i.e., less than 5 picoseconds of jitter. A well-designed crystal-based clock
is preferred. The clock oscillator should have a
well-regulated supply, with local bypass capacitors at the oscillator. The output from the
oscillator should pass through as few logic gates
or counter-divider stages as possible, as these can
add jitter. Excess clock jitter will reduce the
signal/noise performance of the AID converter.

The system connection diagram, Figure 1, illustrates the recommended power supply
arrangements. The CS5324 has two positive analog supply pins and two negative analog supply
pins. Multiple pins are used to minimize the possibility of noise coupling on the chip. All six
power supply pins should be decoupled to their
respective grounds, with a 0.1 uF capacitor located near the device. The digital supplies are
decoupled from the analog supplies with 10 ohm
resistors to minimize the effects of digital noise
in the converter.

Power Supply Rejection Ratio

The positive digital power supply of the CS5324
must never exceed either positive analog supply
by more than a diode drop, or the CS5324 could
experience permanent damage. If separate supplies are used for the analog and digital sections
of the chip, care must be taken that the analog
supply comes up first at power-up. Additionally,
the power supplies to the CS5324 should be active before the reference current generator
supplies the IREF input current. For proper startup, the CLKIN signal should be active before
IREF is applied. The recommended filter capacitors, which filter the reference currents, will aid

The power supply noise rejection of the CS5324
is frequency dependent. The rejection for frequencies between dc and 500 Hz
(CLKIN=1.024 MHz) is nearly constant. Above
500 Hz, the off-chip digital filter will aid in rejecting interference until the frequency of the
interference approaches frequencies near
CLKIN/21.3
(above
48
kHz
for
CLKIN=1.024 MHz). Power supply interference
above this frequency may cause noise to be
modulated into the passband (dc to 500 Hz), degrading the performance of the AID.

OdB

OdB
_ Avgs:10

-20dB

SJ(N+D): 110.0 dB
SIN: 115.2 dB
SID: 11i.adB

-

-

- -

-

Dynamic Range: 120.6 dB

Avgs: 50

-

-40dB

-4OdB
-SOdB

-aOdB
Signal
Amplitude -SOdB
Relative to
Full Scale -IOOdB

Signal
Amplitude

-SOdB

Relative to -IOOdB
Full Scale

-120dB

-120dB

-140dB

-140dB
-ISOdB

-ISOdB
de

Input Frequency

(Hz)

Figure 6. 1024 Point FFT Plot with
Full Scale Input, 113 Hz.
2-294

_ _ _

-2OdB

500

de

Input Frequency

(Hz)

500

Figure 7. 1024 Point FFT Plot with
-60 dB Input, 100 Hz.
DS36F1

--- ..._
_...........
.........
-..

CS5324

O,----,~n-----------------_.

- - - - - - - - - -SIN: 116 dB

- - - - - - - - - -SID: 110 dB

A - 40 Hz Intermodulation Distortion Term
B-100 Hz Fundamental at 6 dB down
C - 140 Hz Fundamental at 6 dB down
D - 200 Hz Second Order Distortion Term
E - 240 Hz Intermodulation Distortion Term
F - 280 Hz Second Order Distortion Term

Signal
Amplitude
Relative to
Full Scale
(dB)

Note: SIN noise degradation is due to input
signal source.

dc

100

200

300

400

500

Input Frequency (Hz)

Figure 8. 1024 Point FFT Plot of Intermodulation Products.

in accomplishing these requirements. Use of
good ground plane layout is recommended to
achieve maximum performance.
Many seismic or sonar systems are battery powered, and utilize dc-dc converters to generate the
necessary supply voltages for the system. To
minimize the effects of power supply interference, it is desirable to operate the dc-dc converter
at a frequency which is rejected by the digital filtering in the NO converter. To achieve maximum
benefit of the digital filter in the NO, the dc-dc
operating frequency should be located below
48 kHz (see Power Supply Rejection). A synchronous dc-dc converter, whose operating
frequency is derived from the 1.024 MHz clock
used to drive the CS5324, will minimize the potential for "beat frequencies" appearing in the dc
to 500 Hz passband.

DS36F1

Schematic &Layout Review Service
Confirm Optimum
Schematic &Layout
Before Building Your

2-295

___-_

.. ........
.--.........
.....

CS5324

TIME SLOT C

TSC

TIME SLOT B

TSB

~
FSYNC FRAME SYNC
TIME SLOT A
TSA ~
~ 07 DATA BUS OUTPUT
IREF ~~
~ 06 DATA BUS OUTPUT
CURRENT INPUT REFERENCE
05
DATA BUS OUTPUT
ANALOG GROUND AGN01 ~'l
NEGATIVE ANALOG POWER
POSITIVE ANALOG POWER

VA1-

INTEGRATOR OUTPUT
SIGNAL SUMMATION NODE

~

VA1+ -----.......
INT SUM

...J
/

SIGNAL FEEDFORWARD

SFF ---.I~.

ANALOG GROUND AGN02

5

4

3

2

9

28 27 26 25 ; ; -

6

24
23

7

D4

~ VO-

DATA BUS OUTPUT
NEGATIVE DIGITAL POWER

8

TOP

22 -

VO+

POSITIVE DIGITAL POWER

9
10

VIEW

21 "----20 \

OGNO

DIGITAL GROUND

11

19
12 13 14 15 16 17 16

~.
'----

CLKIN CLOCK INPUT
D3

DATA BUS OUTPUT

POSITIVE ANALOG POWER

VA2+

D2

DATA BUS OUTPUT

NEGATIVE ANALOG POWER

VA2-

01

DATA BUS OUTPUT

TEST

TST

DO

DATA BUS OUTPUT

PWON POWER DOWN INPUT

PIN DESCRIPTIONS
Power Supplies

VA1+, VA2+ - Positive Analog Power, PINS 7, 12
Positive analog supply voltage. Nominally +5 volts.
VA1-, VA2- - Negative Analog Power, PINS 6, 13
Negative analog supply voltage. Nominally -5 volts.
AGND1, AGND2 - Analog Ground, PINS 5, 11
Analog ground reference.
VD+ - Positive Digital Power, PIN 22
Positive digital supply voltage. Nominally +5 volts.
VD- - Negative Digital Power, PIN 23
Negative digital supply voltage. Nominally -5 volts.
DGND - Digital Ground, PIN 21
Digital ground reference.

2-296

OS36F1

.. ...
......_.
-. ..,..,-~-

~~

~~

CS5324

Analog Inputs

IREF - Current Input Reference Node, PIN 4
This node accepts a 2 rnA reference current to set the signal gain of the NO converter.
SFF - Signal Feedforward, PIN 10
The input signal is fed forward around the integrator input stage by means of this input pin.
This maximizes signal performance.
SUM - Signal Summation node, PIN 9
This is the input integrator virtual ground summing junction. The external integrator input
resistor and integrating capacitor are connected to this node, along with a 500 uA bias current
network.
INT - Integrator Output, PIN 8
Output pin of the input integrator stage. The external integrating capacitor is connected to this
pin for proper operation.
Digital Inputs

CLKIN - Clock Input, PIN 20
A CMOS-compatible clock input to this pin (nominally 1.024 MHz) provides the necessary
clock for operation of the modulator, digital filter and data output portions of the NO converter.
PWDN - Power Down Input, PIN 15
When connected to +5 V (VD+) the CS5324 will enter a low-power state. For normal operation
this pin should be tied to DGND.
TSA - Time Slot A, PIN 3
See TSC below.
TSB - Time Slot B, PIN 2
See TSC below.
TSC - Time Slot C, PINI
The TSC input along with TSA and TSB select one of eight possible time periods in which
data is output from the CS5324 in a time-multiplexed architecture. Table 2 indicates the
decoding of the TSA, TSB, and TSC inputs.
FSYNC - Frame Sync, PIN 28
A transition from a low to high level on this input will re-initialize the CS5324. The digital
filter will be initialized and the time-slot counter will be set to zero.

D536F1

2-297

....... .....
..............
.........

-"'-'

-'

CSS324

DO through D7 - Data Bus Outputs, PINS 16-19,24-27
3-state output pins. Data will be presented out of these pins in the form of two eight-bit bytes
during a time slot selected by the TSA, TSB and TSC inputs. The high-order byte with eight
data bits will be presented first followed by a second eight-bit byte, which consists of the four
low-order data bits, three status bits, and one unused bit.
Miscellaneous

TST - Test, PIN 14
Reserved for production test facility. Should be tied to DGND for normal operation.

PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full-scale (rms) signal to the broadband noise signal. Broadband noise is
measured with the input grounded within the bandwidth of dc to 500 Hz. Units in dB.
Signal-to-Distortion
The ratio of the full-scale (rms) signal to the rms sum of all harmonics up to 500 Hz. Units in
dB.
Intermodulation Distortion
The ratio of the rms sum of the two test frequencies (100 and 140 Hz) which are each 6 dB
down from full-scale to the rms sum of all intermodulation components within the the
bandwidth of dc to 500 Hz. Units in dB.
Full Scale Error
The ratio of the difference between the value of the voltage reference and analog input voltage
to the full scale span (two times the voltage reference value). This ratio is calculated after the
effects of offset and the external bias components are removed and the analog input voltage is
adjusted to yield a code value of 1280 out of the CS5324. Measurement of this parameter uses
the circuitry illustrated in the System Connection Diagram. Units in %.
Full Scale Drift
The change in the Full Scale value with temperature. Units in %/°e.
Offset
The difference between the analog ground and the analog voltage necessary to yield an output
code from the CS5324 of OO(H). Measurement of this parameter uses the circuit configuration
illustrated in the System Connection Diagram. Units in mV.

Offset Drift
The change in the Offset value with temperature. Units in

2-298

/lvre.
DS36F1

.... ...
.....-.
-. ....,--~

~~

CS5324

~~

Appendix 1.

ripple illustrated in Figure A1.3. Table A1.2 lists
the coefficients for this filter.

Off-chip Filter Stages

An alternative second stage filter is also included. It has fewer coefficients, and therefore,
is less complex than the previous second stage
filter. The magnitude plot of the alternative filter
is illustrated in Figure AI.4 with an expanded
view of the passband ripple in Figure Al.5. Note
that this low-pass function has slightly less outof-band rejection and somewhat higher passband
ripple. The filter coefficients for the alternative
final stage are listed in Table Al.3.

Two stages of off-chip filtering are recommended for use with the CS5324. The first stage
is a decimate-by-8 modified-sine filter with 43
coefficients. Its magnitude response is illustrated
in Figure Al.l. Table AU lists its coefficients.
The second filter stage is a 301st-order low-pass
filter. Its magnitude plot is illustrated in Figure Al.2 with an expanded view of the passband

0.00 --,-..-:-_ _ _ _ _ _ _ _ _ _._ _ _ _ _ _ _ _ _ _ _ _,

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6.00

8.00

10.00

12.00

14.00

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Frequency [kHz]

h( 1 )
h( 2 )
h( 3 )
h( 4 )
h( 5 )
h( 6 )
h( 7 )
h( 8 )
h( 9 )
h(10)
h(11)

Figure AI.I. First Stage Off-chip Filter h(43 )
1623
h(12)
h(42)
5137
h(13)
h(41 )
12950
h(14)
h(40)
28499
h(15)
h(39 )
55210
h(16)
h(38)
99783
h(17)
h(37)
169332
h(18)
h(36)
272838
h(19)
h(35)
414146
h(20)
h(34)
604491
h(21)
h(33)
847470
h(22)

Magnitude Plot
h(32 )
1143595
h(31 )
1494661
h(30)
1889251
h(29)
2315005
h(28)
2752059
h(27)
3185947
h(26)
3584677
h(25)
3926472
h(24)
4191616
h(23)
4354400
4410541

Table A1.I. First Stage Off-chip Filter - 43 Coefficients
DS36F1

2-299

,.

..................
...... . _.
...............

CS5324

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200.00 400.00 600.00

800.00 1000.00 1200.00 1400.00 1600.00 1800.00 2000.00

Frequency [Hz]
Figure Al.2. Second Stage OtT-chip Filter - Magnitude Plot

2-300

DS36F1

-.......__
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=
=
=
=
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=
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h{ 1 )
h(301)
h(300)
h{ 2)
h(299)
h{ 3)
h( 4)
h(298)
h( 5)
h(297)
h{ 6)
h(296)
h(295)
h{ 7)
h{ 8) = h(294)
h(293)
h( 9)
h( 10) h(292)
h( 11) h(291)
h( 12) h(290)
h( 13) h(289)
h( 14) h(288)
h( 15) h(287)
h( 16) h(286)
h{ 17) = h(285)
h( 18) h(284)
h( 19) h(283)
h{ 20) h(282)
h( 21) h(281)
h( 22) h(280)
h{ 23) h(279)
h{ 24) h(278)
h{ 25) = h(277) =
h{ 26) h(276)
h( 27) h(275)
h( 28) = h(274)
h( 29) h(273) =
h( 30) = h(272) =
h( 31) h(271) =
h{ 32) h(270) =
h{ 33) h(269)
h( 34) = h(268) =
h( 35) h(267)
h( 36) h(266)
h( 37) = h(265) =
h( 38) = h(264)
h( 39) h(263)
h( 40) = h(262) =
h( 41) h(261)
h{ 42) = h(260) =
h( 43) = h(259) =
h{ 44) = h(258) =
h( 45) h(257)
h( 46) h(256)
h{ 47) = h(255) =
h( 48) h(254)
h( 49) = h(253) =
h( 50) = h(252) =
h( 51) h(251)

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

=
=
=
=
=
=
=
=
=
=

=
=
=

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=
=
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=
=

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=
=

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4
6
4
-6
-28
-58
-85
-93
-68
-7
75
146
166
108
-23
-185
-302
-300
-144
130
414
565
467
106
-399
-826
-935
-594
127
947
1468
1359
538
-725
-1882
-2320
-1673
-56
1898
3264
3239
1580
-1168
-3814
-5004
-3886
-631
3478
6517
6784
3702

CS5324

=
=
=
=
=
=
=
=
=
=
=

=
=
=
=

h{ 52) h(250)
h{ 53) h(249)
h( 54) h(248)
h{ 55) h(247)
h{ 56) h(246) =
h( 57) h(245)
h( 58) h(244)
h( 59) h(243)
h( 60) h(242) =
h( 61) h(241) =
h( 62) h(240) =
h( 63) = h(239)
h( 64) h(238)
h( 65) h(237)
h{ 66) h(236)
h{ 67) h(235)
h( 68) = h(234)
h{ 69) = h(233)
h{ 70) = h(232)
h( 71) = h(231)
h{ 72) = h(230) =
h( 73) = h(229) =
h( 74) = h(228) =
h{ 75) = h(227) =
h( 76) = h(226) =
h{ 77) = h(225) =
h( 78) h(224) =
h( 79) = h(223) =
h( 80) = h(222) =
h( 81) = h(221) =
h( 82) h(220) =
h( 83) = h(219) =
h( 84) = h(218) =
h{ 85) = h(217) =
h{ 86) h(216) =
h( 87) = h(215) =
h{ 88) = h(214) =
h{ 89) = h(213) =
h{ 90) = h(212) =
h( 91) = h(211) =
h( 92) = h(210) =
h{ 93) h(209) =
h( 94) h(208)
h( 95) = h(207) =
h{ 96) = h(206) =
h{ 97) = h(205) =
h{ 98) h(204)
h{ 99) h(203) =
h(100) h(202)
h(101) h(201)
h(102) = h(200) =

=
=
=
=

=
=
=

=
=
=
=
=
=
=
=
=

=
=
=

=
=

=

=
=
=
=

=
=
=

-1711
-7104
-9771
-7963
-1918
5964
12013
12943
7567
-2315
-12399
-17689
-14905
-4360
9720
20798
22983
14065
-2922
-20553
-30166
-26027
-8537
15226
34244
38558
24349
-3468
-32689
-49042
-43038
-15194
23126
54160
61841
39925
-3894
-50321
-76781
-68222
-25304
34332
83049
95832
62860
-4158
-75642
-116939
-104877
-40254
50253

=
=
=
=
=

=
=
=
=

=

=

h(103) h(199)
124723
h(104) h(198)
145121
h(105) h(197)
96333
h(106) = h(196)
-4251
h(107) h(195) = -112209
h(108) h(194) = -175323
h(109) = h(193) = -158449
h(110) h(192)
-62339
h(111) = h(191) = 73359
h(112) = h(190) = 185878
h(113) = h(189)
217891
h(114) = h(188) = 146090
h(115) h(187) = -4196
-166796
h(116) h(186)
-263179
h(117) h(185)
-239689
h(118) = h(184)
h(119) = h(183) = -96169
h(120) = h(182)
108776
h(121) h(181) = 280687
h(122) h(180) = 331861
224879
h(123) = h(179)
h(124) = h(178) = -4045
h(125) = h(177) = -255205
h(126) = h(176) = -407467
h(127) = h(175) = -375114
-153475
h(128) = h(174)
h(129) = h(173) = 169870
h(130) = h(172) = 447384
h(131) h(171) = 536503
h(132) = h(170) = 369619
h(133) = h(169) = -3865
h(134) h(168) = -426733
h(135) = h(167) = -696076
h(136) = h(166) = -655325
h(137) = h(165) = -276498
h(138) = h(164)
307141
h(139) = h(163) = 839720
h(140) = h(162) = 1044525
h(141) = h(161) = 751372
-3724
h(142) = h(160) =
h(143) = h(159) = -953887
h(144) = h(158) = -1671933
h(145) = h(157) = -1718209
h(146) = h(156) = -813868
h(147) = h(155) = 1027355
h(148) = h(154) = 3464481
h(149) h(153) = 5912858
h(150) = h(152) = 7722306
h(151) = h(151) = 8388608

=

=
=
=
=
=

=
=
=
=
=

=

=
=

=

=

Table A1.2. Second Stage Off-chip Filter - 301 Coefficients
DS36F1

2-301

l1li

........
.....,_....
_.-.
...........

CS5324

1.6E-04
1.3E-04

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0.00
50.00 100.00 150.00 200.00 250.00 300.00 350.00 400.00 450.00 500.00

Frequericy [Hz]
Figure A 1_3. Second Stage Off-chip Filter - Passband Ripple Plot

2-302

DS36F1

-_

_-.-.......
__.......
...-..

...,

h( 1) = h(201) =
h( 2) = h(200) =
h( 3) = h(199) =
h( 4) = h(198) =
h( 5) = h(197) =
h( 6) = h(196) =
h( 7) = h(195) =
h( 8) = h(194) =
h( 9) = h(193) =
h( 10) = h(192) =
h( 11) = h(191) =
h( 12) = h(190) =
h( 13) = h(189) =
h( 14) ='h(188) =
h( 15) = h(187) =
h( 16) = h(186) =
h( 17) = h(185) =
h( 18) = h(184) =
h( 19) = h(183) =
h( 20) = h(182) =
h( 21) = h(181) =
h( 22) = h(180) =
h( 23) = h(179) =
h( 24) = h(178) =
h( 25) = h(177) =
h( 26) = h(176) =
h( 27) = h(175) =
h( 28) = h(174) =
h( 29) = h(173) =
h( 30) = h(172) =
h( 31) = h(171) =
h( 32) = h(170) =
h( 33) = h(169) =
h( 34) = h(168) =

-68
-266
-681
-1350
-2192
-2938
-3124
-2181
366
4634
10142
15743
19809
20712
17462
10292
889
-7915
-13029
-12292
-5542
4957
15066
20225
17383
6584
-8560
-21921
-27236
-20930
-4177
16903
33304
36843

CS5324
h(
h(
h(
h(
h(
h(
h(
h(
h(
h(
h(
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h(
h(
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51)
52)
53)
54)
55)
56)
57)
58)
59)
60)
61)
62)
63)
64)
65)
66)
67)
68)

= h(167) =
= h(166) =
= h(165) =
= h(164) =
= h(163) =
= h(162) =
= h(161) =
= h(160) =
= h(159) =
= h(158) =
= h(157) =
= h(156) =
= h(155) =
= h(154) =
= h(153) =
= h(152) =
= h(151) =
= h(150) =
= h(149) =
= h(148) =
= h(147) =
= h(146) =
= h(145) =
= h(144) =
= h(143) =
= h(142) =
= h(141) =
= h(140) =
= h(139) =
= h(138) =
= h(137) =
= h(136) =
= h(135) =
= h(134) =

24059
-1482
-29822
-48300
-47054
-24000
13122
49003
66874
56133
18103
-33025
-75161
-87623
-60982
-2877
63451
108121
107776
57300
-25620
-106083
-146288
-122895
-39611
71441
161525
186220
126698
1412
-138356
-228840
-222225
-110815

h( 69) = h(133) = 64893
h( 70) = h(132) = 229769
h( 71) = h(131) = 305309
h( 72) = h(130) = 245984
h( 73) = h(129) = 64260
h( 74) = h(128) = -168625
h( 75) = h(127) = -349221
h( 76) = h(126) = -386474
h( 77) = h(125) = -245727
h( 78) = h(124) = 28395
h( 79) = h(123) = 323264
h( 80) = h(122) = 502448
h( 81) = h(121) = 466350
h( 82) = h(120) = 203318
h( 83) = h(119) = -193406
h( 84) = h(118) = -554902
h(85) = h(117) = -704448
h( 86) = h(116) = -538246
h(87)=h(115)= -84243
h(88)=h(114)= 490248
h( 89) = h(113) = 932553
h( 90) = h(112) = 1005109
h(91)=h(111)= 595458
h( 92) = h(11 0) = -209660
h( 93) = h(109) = -1121850
h( 94) = h(108) = -1730461
h( 95) = h(107) = -1642084
h( 96) = h(106) = -632318
h( 97) = h(105) = 1247052
h( 98) = h(104) = 3649798
h( 99) = h(103) = 6019586
h(100) = h(102) = 7753188
h(1 01) = h(1 01) = 8388608

Table A 1.3. Alternate Second Stage Off-chip Filter - 201 Coefficients

DS36F1

2-303

•

I

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. _...,.

..,
.., .......

~..,~

CS5324

~~

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-180.00
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0.00

200.00

400.00

600.00

800.00 1000.00 1200.00 1400.00 1600.00 1800.00 2000.00

Frequency [Hz]
Figure A 1.4 Alternate Second Stage Off-chip Filter - Magnitude Plot
0.10 -,-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---,

0.08

-- ---,

- - - - - - - ,

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0.04

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0.00
-0.02
-0.04
-0.06
-0.08
-0.10

+---t-----t-----t----t-----t----j----j------1'------j-----j

0.00

50.00

100.00

150.00

200.00

250.00

300.00

350.00 400.00

450.00

500.00

Frequency [Hz]
Figure At.S Alternate Second Stage Off-chip Filter - Passband Ripple Plot
2-304

DS36F1

......
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Semiconductor Corporation

CDB5324

Evaluation Board for CS5324
Features

III

General Description

I

The CDB5324 is an evaluation board that allows the
laboratory characterization of the CS5324 AID converter.
The CS5324 is a 120dB dynamic range, 500Hz bandwidth ADC intended for seismic applications. The board

• PC/J..lP-compatible Header Connection
16 Bit Parallel Data
Three-State Output
Data Ready Signal

supports ±10 volt analog input signals and generates the
timing signals which format the output data from the
CS5324 into a single 16-bit parallel word.

• Analog/Digital Patch Areas
ORDERING INFORMATION: CDB5324

• Analog BNC Input Connector

Reference
Circuitry

IREF

0--

Reset

DO
CS5324

+5V

.I..

2

ClKIN
FSYNC

Timing
Generator

8

I
D7

SUM
16-Bit
Register

SFF

+5V Analog

-5V Analog

+5V
Regulator

-5V
Regulator

+15V

AGND

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760

(512) 445 7222 Fax: (512) 445 7581

-15V

Header

+5V Digital

DGND

+5V

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS36DB1
2-305

----------------------

COB5324

Power Supplies and Voltage Reference

provide the +SV and -SV supplies necessary for
the CSS324. Also included in Figure 1 is a startup circuit which allows a power-down signal to
tum off both the CSS324 and the supply current
to the LTC1021 voltage reference. An RC delay is
added as part of the start-up circuitry to insure the
the +SV digital supply is present before the
LTC 1021 voltage reference is turned on. The
FSYNC and CLKIN signals to the CSS324 must

The CDBS324 evaluation board requires three
separate input voltages for proper operation. Figure 1 illustrates the power supply connections.
The required power supply input voltages consist
of +Sv, + lSV, and -lSy' The +SV input supplies
power to the digital logic portion of the board.
The + lSV and -lSV inputs are regulated down to
TP9
0----<_-...---...-- +5VD

+5V

P6KE
CR2

=
+15V

~~-----_~_-' 4 MHz Clock

OSC
Module
4MHz

To Fig. 3

7

10
+5VD -'\i'V\r-.---.-------,
+5VD
14
12

4

10
S

D

Q 9

2
3

11 C L

- 8
R Q

Note: This circuitry is
added in the digital
patch area.

S
D

Q

CL

5

6
Q

R

1 MHz clock
to Fig. 5

13

7
--

74HC74
+5VD
14
Reset

+5VD

2

D

10

S Q 5
12
S
9
r----ID
Q
11

3 CL
10 k

+5VD

4

Q

6

CL
Q

R

8

13
--

FSYNC _ _ _ _ _ _ _ _ _----'
From Fig. 3

+5V
74HC74

Figure 2. Clock OscillatorlDivider
DS36DB1

2-307

•

I

_.-_..--_._.
__.._-_
...-.

CDB5324

will reduce the signal-to-noise capability of the
device.

sure that the other timing signals derived from the
74HC590 outputs have the proper phase relationship to the 1 MHz clock in the CS5324.

Note that both the oscillator and the dual D flipflop used to divide the oscillator output are
individually decoupled from the +5V logic supply.
The second dual D flip-flop pair are used to synchronize the 1 MHz from the dual D divider to be
in phase with the 1 MHz out of the 74HC590
counter. This synchronization is necessary to in+5VD
From
Fig 2,
4MHz
Clock

Reset
To insure synchronization of the 1 MHz clock to
the CS5324 with the other clock signals in the
system, the reset button in the digital patch area of
the board must be activated after power is applied
to the system.

0.1 ~F

~

TP15

FSYNC
To Fig. 2, 5

CCK
RCK

U5

CCLR

WORD
+5VD

74HC590

~~F
'"___ _ _-.
I -.l . .
WORD

CCKEN

C7 ~
15

2

3

4

5

6

To U4, pin 5

7

Q 9

12
11 +5V
D

1 74HC74

6

1 CL

14

TPB

5
4 74HC30
3
2
1

U7

Q6

U7 Q

B

13
+5VD
TP6
LBL,
To Fig. 6

U1
'----------'----1jJ

2

HBL,
To Fig. 6
WORD
From U7, pin 5

C4

Figure 3. Timing Generator
2-308

DS36DB1

.-_
_
..--_._.
__.._-_
...-.

CDB5324

Timing Generator

Figure 3 illustrates the logic circuitry which generates the timing signals used to latch the data
coming out of the CS5324 NO converter. The
outputs from the 74HC590 counter are used to
generate FSYNC, HBL (High Byte Latch), LBL
(Low Byte Latch), and WORD. Figure 4 illustrates the timing relationships of these signals.
CS5324 AID Converter

The connections to the CS5324 chip are illustrated in Figure 5. The analog and digital supply
voltages are all decoupled close to the device. Included in the schematic are the discrete

FSYNC

1

components used to develop the reference current
and signal current inputs to the device. The AIN
BNC is the signal input to the evaluation board.
The input range is set for 20 volts p-p. Data from
the CS5324 is output as two 8-bit bytes. These
two bytes are latched into the output registers of
Figure 6.
Output Registers/Header Connector

Data from the CS5324 NO converter is latched
into the two 74HC574 octal flip-flops by the HBL
and LBL latch signals generated by the timing
generator. The outputs of the 74HC574's are then
connected to the 40-pin header Connector. Figure 7 identifies the pins on the 40-pin header.

32 ClKIN Cycles

lJLJL

1.0 MHz
ClKIN

tI

HBl

WORD

-\

HI BYTE

X

I

fh

tI

lBl
CS5324
DATA
OUTPUT

.~

lO BYTE

r

{,c,

f'ugh the ADC rather than IllS).
SAMPLE
N

HOLD

The CS5412 also uses a second track-and-hold
amplifier (termed TIH2 in Figure 3) to pipeline
the converter's acquisition time. As shown in Figure 3, TIH2 holds the output from TIHJ valid for
the second flash conversion, Flash 2. This allows
TIHI to release and acquire the analog input signal during the second flash conversion, allowing
another Hold & Convert command to be issued
even before the completion of Flash 2.

DIGITAL CIRCUIT CONNECTIONS
In addition to master clock and sampling connections which set the converter's timing, the
CS5412 offers an Overrange output, 3-state output buffers, and flexible control interface. The
CS5412 can therefore connect directly to a microprocessor's data and control busses or can be
operated in a stand-alone mode.
Master Clock

The CS5412 operates from a master clock reference which must be supplied in the form of either
a crystal or external clock. A crystal can be tied
across the CLKIN and XIN pins, or alternatively,
the CS5412 can be synchronized to the external
system by driving CLKIN with a CMOS-compatible clock (XIN left floating). If the master clock
is shut off while the CS5412 is powered up, an internal oscillator will start-up to keep all internal
SAMPLE

Nt

*

SAMPLE
N+4

*

DRDY

00-011

DATA N-1 VALID

DATA N VALID

DATA N+1 VALID

DATA N+2 VALID

Figure 2. Pipelined Conversion Cycles
2-322

DS2F3

------------ -----------

CS5412

10-1.----- CONVERSION

HOLD &
CONVERT
(HOLD)

TRACK/HOLD
TlHl

L

N+l--------01

-

FLASH 1-----.1

I

HOLD

1

ACQUIREAIN

10-- FLASH 2------.1
TRA~~2HOLD_ _ /

I,-----_+--_~

ACQUIRE T /Hl \'---_ _ _H_O_LD_ _~j

\'---_ _ _ _ _ _

~/

DECODER L-------.:
SETTLING"
-I

DATA READY
(DRDY) ----~

\

DATA
(Do-D11)

1

X

~

/

/

1

1

DATA

N-l VALID

X

}

DATA N VALID

X

Figure 3. Pipelined Acquisition and Settling Times.

dynamic logic refreshed. This internal oscillator
should not be used for conversions. Clock cycles
can be selectively skipped at any time, but the
clock's average frequency should never drop below the device's minimum specification (see
Switching Characteristics).
Sampling/lnitiating Conversions
There are two methods of controlling the
CS5412's sampling/conversion timing. First, the
CS5412 has a HOLD input which, on a falling
edge, places the input track-and-hold amplifier in
the hold state and initiates a conversion cycle.
The CS5412 also features a Continuous Convert
mode (CCNV and HOLD high) in which hold
commands are internally generated every eight
master clock cycles. The sampling/throughput
rate is therefore controlled by adjusting the master clock frequency and there is no need to generate a sampling clock.
When CCNV is brought high with the proper relationship to CLKIN (shown in the timing diagrams), the next falling clock edge defines
state O.

DS2F3

Lower sampling rates can be created in the Continuous Convert mode by running the CS5412 at
full throughput and decimating the output, selectively reading only a fraction of the available
samples. Variable sampling rates can be implemented in this manner using a programmable divider on the DRDY output. When operating in
the Continuous Convert mode, attention should
be paid to jitter on the master clock, since jitter
will directly affect sampling purity.
If the phase of sampling must be precisely controlled, the HOLD input must be used since the
hold signal is internally-generated in the Continuous Convert mode. A falling edge on HOLD
places the internal track-and-hold amplifier in the
hold state and signals a conversion cycle to begin
on the next falling edge of the master clock. The
HOLD input was designed for minimum aperture
jitter and therefore requires CMOS-compatible
logic levels (not TTL-compatible).
Due to the CS5412's refreshing the 64 reference
levels in the background, HOLD commands must
be synchronized to the master clock and can only
occur at intervals of 8 master clock cycles. The
first HOLD command after the start of a reset or
calibration cycle defines state 0 in the CS5412's
2-323

-____-_

.-..........
....
.......

CS5412

timing circuitry (see Figure 4). The sampling signal applied to HOLD must adhere to frequencies
of fcuJ8N such that subsequent HOLD commands will always fall between state 7 and state
O. If the sampling clock changes phase and a
HOLD command occurs before state 7 or after
state 0 the CS5412 may be thrown out of calibration, and 4288 clock cycles must be allowed for
the converter to complete two full background refresh cycles. Likewise, conversion data should be
considered invalid for 4288 clock cycles following the first HOLD command after the end of
calibration to insure specified accuracy. If a normal, periodic, HOLD signal is applied during the
entire calibration period, the data will be valid
immediately after calibration, i.e. when OVRNG
goes low.

Conversion Time/Throughput

In the Continuous Convert mode, throughput will
proceed at one-eighth the master clock frequency
and the delay through the CS5412 will be ten
master clock cycles. When hold commands are
generated externally at the HOLD pin, the analog
input is held immediately as the HOLD input
falls and the conversion cycle begins on the. next
falling edge of the master clock. The CS5412's
conversion time will range from 10 to 11 clock
cycles depending on the phase relationship of the
HOLD signal to the master clock (see Figure 4).
Throughput can still proceed at fcud8 independent
of the conversion time. The pipelined overlap between conversion cycles will range from to 2 to 3
clock cycles.

Most often the sampling signal applied to HOLD
can be derived from the master clock. In these
cases, the master clock is divided by 8, 16, 24,
32, etc. If sampling must be locked to some external clock source, a phase-locked loop can be
used to generate a master clock signal for CLKIN
from the sampling signal.· In this instance jitter on
the HOLD input will directly affect sampling purity; however, the CS5412 will tolerate significant
jitter on the master clock without loss of accuracy
(assuming the HOLD/CLKIN phase specifications are met).

Reset

Upon power-up, the CS5412 must be reset to
guarantee a consistent starting condition and initially calibrate the device. A falling edge on the
RST pin clears internal logic and a rising edge
initiates a calibration cycle which takes 6,052,445
master clock cycles to complete. The RST input
must remain low for at least 2 master clock cycles to be considered valid. A simple power-up reset circuit can be constructed by tying a capacitor
from RST to DGND and a resistor from RST to
VD+.

x

8/0

X

9/1

10/2

11/3

12/4

13 /5

14/6

15n

16/0

17/1

18/2

19/3

ClKIN

~

L
I.

1

1

HOLD

\

00

\
Tconv

DRDY

L

~

ACCEPTABLE
HOLD PERIOD

1

\

fill

ACCEPTABLE
HOLD PERIOD

~

·1

(
1

I

~

Figure 4. Hold I Conversion Timing.
2-324

DS2F3

.. ...
...,-,..,-..........
.....
~..,

CS5412

..,~

Due to the CS5412's modest power dissipation
and low temperature drift, no warm-up time is
needed before reset to accommodate any selfheating effects. However, the voltage references
(VREF+ and VREF-) should have stabilized to
within their specified accuracies. The CS5412
can be reset later at any time during operation to
initiate calibration. Reset overrides all other functions. If reset, the CS5412 will clear and initiate a
new calibration cycle mid-conversion or mid-calibration.
Overrange

The CS5412 will flag an overrange input at the
OVRNG' pin whenever the sampled analog input
exceeds either the positive or negative reference
voltage. If the sampled input exceeds VREF+,
OVRNG will go high as DRDY falls, and all
ones will be loaded into the output buffers. Similarly, if the analog input is below VREF-,
OVRNG will go high as all zeroes are loaded
into the output buffers. OVRNG should be
latched on the rising edge of DRDY. The internal
reference voltages are not affected by excursions
of AIN outside the external reference voltages up
to the supply voltages.

CCNV HOLD CAL

RD------------IRD
ADDR VALID -----;
CS5412

AN
Address :
Bus
•
A1

CS

AO - - - - - - - - - - - - 1 CAL

Figure 5. Microprocessor Controlled Operation.

Thirteen clock cycles after RST or CAL transitions, OVRNG goes high. The OVRNG output
remains high throughout a reset/calibration sequence and will return low after its completion. It
can therefore be used to generate an interrupt indicating the CS5412 has completed calibration
and is ready for operation.
Microprocessor Controlled Operation

The CS5412 features 3-state output buffers and a
control interface which allow the device to connect directly to a microprocessor's data and control busses. Strobing both CS and RD low enables the CS5412's 3-state output buffers with the
converter's 12-bit output word. As shown in Figure 5, a decoded address is normally applied to

CS

RD

RST

Function

0

0

X

X

0

1

Read Output Data

*

1

X

X

*

1

High Impedance Data Bus

1

X

X

X

X

1

High Impedance Data Bus

*

X

1

X

*

1

Continuous Convert Mode

*

X

0

~

*

1

Hold and Start Convert

X

X

X

X

X

S

Start Reset

0

X

X

X

~.

X

Start Reset

* Not critical to the operation specified. However, CS should
not be low with CAL transitioning low or a software reset will result.
Table 1. CS5412 Truth Table.
DS2F3

2-325

_.

.- .........
............
.......

..,

..,

CS, and the RD input is derived from read and
strobe signals from the microprocessor's control
bus. The Data Ready (DRDY) output can be used
to generate an interrupt or drive a DMA controller to dump the CS5412's output directly into
memory after each conversion. The DRDY output
falls as new data is being loaded into the output
buffers. Data should be latched on the rising edge
of DRDY which occurs three master clock cycles
after it falls.
The CS5412 internally buffers its output data, so
data can be read while the device is tracking or
converting the next sample. Therefore, retrieving
the converter's digital output requires no reduction in ADC throughput. The CS5412 should be
synchronized to the digital system via CLKIN to
avoid potential errors due to enabling the 3-state
output buffers while the part is converting. Using
TTL loads also increases the potential for crosstalk between the digital and analog portions of
the system. This crosstalk is due to high digital
supply and signal currents arising from the TTL
drive current required of each digital output. Connecting CMOS logic to the CS54l2's digital outputs is recommended. Suitable logic families include 4OOOB, 74HC, 74AC, 74ACT, and 74HCT.

Initiating Calibration
In addition to the hardware reset, the CS5412
features a software calibration capability. Whenever CAL transitions low with CS low, or CS
transitions high with CAL high, a calibration cycle will be initiated which is equivalent to the reset function. As shown in Figure 5, line AO from
the address bus can be connected to the CAL input when operating under microprocessor control.
A read cycle from the CS5412's base address
with AO low will therefore retrieve output data
while a read or write cycle with AO high will initiate calibration. The CAL input is level sensitive, and like RST, CAL overrides all other functions. Software-initiated calibrations can thus be
used in lieu of a hardware reset at power-up.
2-326

CS5412

Stand-Alone Operation
The CS5412 can be operated in a stand-alone
mode independent of intelligent control. In this
mode, CS and RD are hard-wired low, permanently enabling the 3-state output buffers. A freerunning condition is established when CAL is
tied low, and HOLD is continually strobed low or
CCNY is held high. The CSS412's DRDY output
can be used to externally latch the output data if
desired. The DRDY output will strobe low for
three master clock cycles after each conversion.
Data will typically be unstable for 40ns after
DRDY falls, so it should be latched on the rising
edge of DRDY. This results in a total delay of 13
master clock cycles through the CS5412.

ANALOG CIRCUIT CONNECTIONS
Like most 2-step flash AID converters with internal track-and-hold amplifiers, the CS5412 offers
a trivial load at its analog input compared to successive-approximation and single-step flash AID
converters. The reference connections similarly
present high impedance loads. However, accurate
system operation still requires careful attention to
details at the design stage regarding source impedances as well as grounding and decoupling
schemes.

Analog Input and Reference Connections
The CS5412's analog input range is defined by
the voltages applied to the VREF- and VREF+
pins. The analog input (AIN) is referenced only
to these reference voltages and is completely independent of the analog ground pins. The first
code transition ideally occurs 1 LSB above
VREF- and the last transition occurs 1 LSB below VREF+. The CS5412 can operate with a fullscale reference as low as 2.0V p-p, but signal-tonoise performance is maximized by using the full
specified range of 3V p-p. Unipolar input ranges
are achieved by tying VREF- to the system's analog ground and applying the reference voltage to
VREF+. Bipolar input ranges are achieved by apDS2F3

...........
_......_-.
._
---._.

CS5412

I
i

plying positive and negative voltages of equal
magnitude to VREF+ and VREF- respectively. In
this configuration, coding is in offset-binary format.
The CS5412's analog input (AIN) pin looks directly into the noninverting terminal of the trackand-hold amplifier resulting in over 10Mn input
impedance and less than lOpF input capacitance.
The reference voltages at the +VREF and -VREF
inputs are dynamically sampled. This pulsed
charge load requires each of the reference inputs
to be decoupled with a O.lIlF ceramic capacitor
in parallel with a 3.3~ tantalum capacitor. The
tantalum capacitors should be chosen to maintain
3.3IlF minimum capacitance over the operating
temperature range. To maintain DC accuracy the
reference(s) should have an output impedance of
less than 5n at DC.

Grounding and Power Supply Decoupling

The CS5412 uses the analog ground connections,
AGND 1 and AGND2, only as stable, low impedance sources. No dc power currents flow through
these connections, and they are completely independent of AIN and DGND. Still, AGND 1 and
AGND2 should be tied to the system's analog
ground. The CS5412's analog input is referenced
only to VREF+ and VREF-. Therefore, the analog input and reference voltages should be referred to the same ground potential (not necessarily AGND) which should be used as the entire
system's analog ground. The optimal grounding
configuration for the CS5412 utilizes one ground
plane under the CS5412. Peripheral analog and
digital circuitry should be partitioned on the circuit board and separate ground planes mayor
may not be used.
The digital and analog supplies are isolated
within the CS5412 and are pinned out separately
to minimize coupling between the analog and
DS2F3

digital sections of the chip. The analog supplies
also have multiple connections which minimize
lead inductances and power separate portions of
the converter's analog circuitry. The decoupling
scheme shown in the System Connection Diagram in Figure 9 provides optimal decoupling
between the CS5412's digital circuitry and the
various analog sections of the chip. Ceramic capacitors are acceptable for all decoupling, and
they should be placed as close to the supply pins
as possible. If significant low-frequency noise is
present on the supplies, 10IlF tantalum capacitors
are recommended in parallel with O.lIlF ceramic
capacitors on the ±5V rails.
The positive digital power supply (VD+) should
never exceed the positive analog supplies (VA2+ or
VA5+) or the CS5412 could experience permanent
damage. If the two supplies are derived from
separate sources, care should be taken that the
analog supply comes up first at. power-up. The
System Connection Diagram in Figure 8 shows a
decoupling scheme which allows the CS5412 to
be powered from a single set of ±5V rails. The
positive digital supply is derived from the analog
supplies though a IOn resistor to avoid the analog supply dropping below the digital supply. If
this scheme is used, care must be taken to insure
that any digital load currents (which flow through
the IOn resistors) do not cause the magnitude of
the digital supplies to drop below their minimum
specification of 4.75V. The positive supplies
must be active and stable prior to applying the
negative supplies. The positive supplies should
remain active and stable when the negative supply is removed at power-down.

The CDB5412 evaluation board is available for
the CS5412, which eliminates the need to design,
build, and debug a high-precision PC board to initially characterize the part. The board comes
with a socketed CS5412 and can be quickly reconfigured to simulate any combination of sampling, calibration, and master clock conditions.

2-327

,.
I

~i
I

i

...............
...........
.........

..,

CS5412

.",

Performance

Two types of performance test results are presented here. With FFf based tests, a pure sine
wave is input to the CS5412, and an FFf analysis is performed on the output data. Figure 6
shows the resulting plot with a 100 kHz input
sine. Notice the absence of any harmonic distortion and the overall Signal to (Noise + Distortion)
value of 70.3 dB.
Figure 7 shows the FFT plot when two sine
waves are simultaneously applied to the input.
Notice the lack of sum and difference products,
indicating very good linearity.

ferential Non Linearity (DNL) and is expressed
as a deviation from the ideal (in LSB), with 0
being perfect. Figure 8 shows the CS5412's excellent DNL performance with most codes being
within ± 0.1 LSB of perfect.
OdB
- - - - - - - - - - - - _ _ _ _ _ _ _

-20dB

Sampling Rate: 1 MHz
FuIlScale:3Vp-p
s/(N+D): 70.3 dB

-4OdB
-6OdB

Signal
Amplitude
Relative to
Full Scale

-8OdB
-10OdB
-12OdB

A second test looks for variation in the code
width of the CS5412, as the input moves from
-Full Scale to +Full Scale. This is called the Dif-

de

100

500

Input Frequency (kHz)

Figure 6. Typical CSS412 FFT Performance
_ _ _ _ _ _ _ _ _ Sampling Rate: 1MHz

Schematic &Layout Review Service

Full Seele: 3Vp-p

-20
-40

Confirm Optimum
Schematic & Layout
Before Building Your

Signal
Level
Relative to
Full Scale
(dB)
-80

-eo

-100
-120
Input Frequency (kHz)

Figure 7. Intermodulation Distortion Performance
+1
+1/2

CD
en

d

0

...J

Z

Cl .1/2
·1

0

2048

4095

Codes
Figure 8. Typical CSS412 Differential Non-Linearity Plot
2-328

DS2F3

.... ...-.
-.............
~

•

~~-

CS5412

~~

+SV
Analog
Supply
C3

10n

1V

C1

C1

T

10n

31
VD+

29

VA2+

ClKIN

VA3+

XIN

T

32

C1

8
VA1+

T

-

Clock
Source
(Optional)

28
3

CS5412

CCNY

VAS+

T

DO-D11
VA4+
CS
RD

20
19

-Analog
Signal
Source

C2

HOLD
CAL

AIN

DRDY
OVRNG

18

Control
logic

21
40

VREF+
Voltage
C3
Reference
Generator
T6

RST

2

VREFAGND1
AGND2
VA3-

DGND

10n

TST1
TST2

VA2-

16
17

VD-

VA1-

30
-SV
Analog
Supply

C3
T

t

T

C1

*VA2+ and V AS+ must be externally connected.

Cl
C2
C3

C2

- O.OllJF ceramic
- O.01~F in parallel with O.1~F ceramic
- O.l~F ceramic in parallel with 3.3 ~F tantalum

Figure 9. System Connection Diagram.

DS2F3

2-329

II
i

....
----_-.. ........
....
--~

CS5412

~

PIN DESCRIPTIONS

HOLD

HOlO

OVRNG

OVERRANGE

RESET
CONTINUOUS CONVERT

RST
CCNY

011

DATA BUS BIT 11

010

DATA BUS BIT 10

AGN01

ANALOG GROUND
NEGATIVE VOLTAGE REFERENCE

AIN
VREF-

POSITIVE VOLTAGE REFERENCE

VREF+

POSITIVE ANALOG POWER
NEGATIVE ANALOG POWER

VA1+
VA1-

ANALOG GROUND

AGND2

POSITIVE ANALOG POWER

VA2+

ANALOG INPUT

D9
08
07
06
OGNO
VAS+

DATA BUS BIT 9
DATA BUS BIT 8
DATA BUS BIT 7
DATA BUS BIT 6
DIGITAL GROUND
POSITIVE ANALOG POWER

VO+
VO-

NEGATIVE DIGITAL POWER

POSITIVE DIGITAL POWER

POSITIVE ANALOG POWER

VA3+

ClKlN

CLOCK INPUT

NEGATIVE ANALOG POWER

VA2-

XIN

CRYSTAL IN

NEGATIVE ANALOG POWER

VA3-

OS

DATA BUS BIT 5

POSITIVE ANALOG POWER

VA4+

04

DATA BUS BIT 4
DATA BUS BIT 3

TEST

TST1

D3

TEST

TST2

D2

DATA BUS BIT 2

CAL

01

DATA BUS BIT 1

RO

DO

DATA BUS BIT 0

CS

DROY

DATA READY

CALIBRATE
READ
CHIP SELECT

NC
HOlO

OVRNG
011
010

09
08

07
06

40

VA1-

~

AGN02 ________
NC - -

~

:~

lop
vlow

12

VA2+ ~ 13
VA3+ ~ ::
VA2- ---../ /
VA3-

C55412

'----

"J" Package

31

:::-

\ "---

17

18

20

22

24

26

28

OGNO
VA5+
VO+

NC
VOClKIN
XIN
05

04
03

02
01
00

CS

2-330

OROY
NC

OS2F3

......
...,.......
.........

..,

-_

~

..,

CS5412

Power Supply Connections

VD+ - Positive Digital Power, PIN 31.
Positive digital supply voltage. Nominally +5 volts.

-

VD- - Negative Digital Power, PIN 30.
Negative digital supply voltage. Nominally -5 volts.
DGND - Digital Ground, PIN 33.
Digital ground reference.
VA+ - Positive Analog Power, PINS 8, 11, 12, 15, 32.
Positive analog supply voltage. Nominally +5 volts. Positive supplies must be active and stable
prior to application of the negative supplies. Positive supplies must remain active and stable
until negative supplies have been removed during power-down.
VA- - Negative Analog Power, PINS 9, 13, 14.
Negative analog supply voltage. Nominally -5 volts.
AGND - Analog Ground, PIN 4, 10.
Analog ground reference.
Oscillator

CLKIN; XIN - Clock In, PIN 29; Crystal In, PIN 28.
Used to generate the internal master clock. A crystal can be tied across the two pins or an
external CMOS-compatible clock can be driven into CLKIN if XIN is left floating.
Digital Inputs

HOLD - Hold Input, PIN 1.
A negative transition on HOLD puts the track-and-hold amplifier into the hold state and
initiates the conversion sequence. Conversions must be synchronized with the master clock at
fcuo8N where N = 1,2,3. The HOLD input is CMOS-compatible.
CCNV - Continuous Convert, PIN 3.
When held high throughput will proceed at 1/8th the master clock frequency. The HOLD pin
can be high or low but must not transition.
CS - Chip Select, PIN 20.
Activates the RD and CAL inputs. When CS is high, these inputs have no effect and the data
bus (DO through Dll) is held in a high impedance state.
RD - Read, PIN 19.
When held low with CS also low, enables DO-Dll.
Note: Pin numbers are for the DIP package.
DS2F3

2-331

_.......-.-..,.
............
---

CS5412

~

RST - Reset, PIN 2.
When RST transitions from low to high a full calibration is started 13 master clock cycles later
indicated by OVRNG going high. OVRNG will return low when calibration is finished.
Calibration takes 6,052,445 master clock cycles.
CAL - Calibrate, PIN 18.
Same as RST except it it logically inverted and enabled by CS going low .
Analog Inputs

VREF+ - Positive Voltage Reference, PIN 7.
Represents positive full scale voltage. Typically + l.5V with respect to AGND (bipolar system)
or +3V with respect to AGND and VREF- (unipolar system).
VREF- - Negative Voltage Reference, PIN 6.
Represents negative full scale voltage. Typically -1.5V with respect to AGND (bipolar system)
or tied to AGND (unipolar system).
AIN - Analog Input, PIN 5.
Analog input to the track-and-hold amplifier.
Digital Outputs

OVRNG - Overrange, PIN 40.
Goes high if the sampled analog input voltage exceeds VREF+ or VREF-. OVRNG also goes
high during calibration cycles and can therefore be used to indicate end of calibration.
DRDY - Data Ready, PIN 21.
Falls when new data is becoming available at the outputs. Returns high three master clock
cycles later. Data should be retrieved on the rising edge of DRDY.
Digital Input/Outputs

DO through Dll - Data Bus, PINS 22 thm 27,34 thm 39.
Three-state data bus where D 11 is the MSB and DO is the LSB. The output coding is binary for
unipolar and offset binary for bipolar.
Miscellaneous Pins

TST1 - Test, PIN 16.
Reserved for factory use. Must be tied to DGND for proper device operation.
TST2 - Test, PIN 17.
Reserved for factory use. Must be tied to DGND for proper device operation.
Note: Pin numbers are for the DIP package.
DS2F3

-----_
..------------ ---

CS5412

DEFINITIONS
Peak Harmonic or Spurious Noise (More accurately, Signal to Peak Harmonic or Spurious Noise) The ratio of the rms value of the signal to the rms value of the next largest spectral component below
the Nyquist rate (excepting dc). This component is often an aliased harmonic when the signal frequency is a significant proportion of the sampling rate. Expressed in decibels.
Total Harmonic Distortion - Ratio of the rms sum of all harmonics to the rms value of of the signal.
Units in percent.
Signal-to-(Noise plus Distortion) - Ratio of the rms value of the signal to the rms sum of all other
spectral components below the Nyquist rate (excepting dc). Expressed in decibels.
Linearity Error - The deviation of the worst code width center, out of all 4096 codes, from a straight
line. The straight line is determined by using a least squares fit algorithm from the measured points.
Units in LSB's.
Differential Nonlinearity - The deviation of a code's width from the ideal width. Units in LSB's.
Full Scale Error - The deviation of the last code transition from the ideal (VREF+ - 1 LSB).
Units in LSB's.
Offset Error - The deviation of the first code transition from the ideal (VREF- + 1 LSB).
Units in LSB's.
Aperture Time - The time required after the hold command is issued for the sampling switch to open
fully. Effectively a sampling delay which can be nulled by advancing the sampling signal. Units in
nanoseconds.
Aperture Jitter - The range of variation in the aperture time. Effectively a "sampling window" which
ultimately dictates the maximum input slew rate acceptable for a given accuracy. Units in picoseconds.

DS2F3

2-333

.......
....,............_....
~

~

CS5412

~~

Ordering Guide
Model
CS5412-JC1
CS5412-JJ1
CS5412-KC1
CS5412-KJ1
CS5412-AC1
CS5412-BC1
CS5412-SC1
CS5412-TC1
5962-9095702MQA
5962-9095701 MQA
5962-9095702MXA
5962-9095701 MXA

Convert
Rate
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz
1 MHz

SINAD
65
65
68
68
65
68
65
68
65
68
65
68

dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

Linearity
Error

± 2.0 LSB
± 2.0 LSB
± 1.0 LSB
± 1.0 LSB
± 2.0 LSB
± 1.0 LSB
± 3.0 LSB
± 2.0 LSB
± 3.0 LSB
± 2.0 LSB
± 3.0 LSB
±2.0 LSB

Temp Range
Oto70°C
o to 70°C
o to 70°C
Oto70°C
-40 to +85 °C
-40 to +85 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C

Package
40-Pin
44-Pin
40-Pin
44-Pin
40-Pin
40-Pin
40-Pin
40-Pin
40-Pin
40-Pin
44-Pin
44-Pin

Ceramic SB DIP
J Lead CLCC
Ceramic SB DIP
J Lead CLCC
Ceramic SB DIP
Ceramic SB DIP
Ceramic SB DIP
Ceramic SB DIP
Ceramic SB DIP
Ceramic SB DIP
J Lead CLCC
J Lead CLCC

The following is a list of upgraded part numbers.
Discontinued
Part Number
CS5412-SC1B
CS5412-TC1B
CS5412-SJ1B
CS5412-TJ1B

2-334

Equivalent
Recommended Device
5962-9095702MQA
5962-9095701 MQA
5962-9095702MXA
5962-9095701 MXA

DS2F3

........
.
.......,-....
.
.....
~

~

~~

CDB5412

Semiconductor Corporation

CS5412 Evaluation Board
Features

General Description
The CDB5412 is a completed, tested evaluation board
for the CS5412 12-bit high-speed analog to digital converter. It includes a CS5412 and all of the components
necessary to quickly and thoroughly verify the converter's performance under a wide variety of operating
conditions.

• Throughout Rates to 1MHz
• Jumper Selectable
Unipolar/Bipolar Input Range
Continuous Conversion

On-board circuitry includes voltage references and clock
circuitry, plus data buffers, so that the user need only
supply power and an input signal to exercise the
CS5412.

• Buffered 12-Bit Data
• Optional Phase-Locked-Loop to
Synchronize to Sampling Signal
• Adjustable Voltage Reference
• PC/uP-Compatible Header Connection

An on-board phase-locked-loop may be used to simulate systems that have a periodic sample clock not
synchronized to a system clock, or where a clock 8
times the sampling clock is not available.

GND

+5V

CDB5412

ORDERING INFORMATION:

-5V

I 1 I
AIN

HOLD

@

•

@

1

RD

CCNV

Crystal Semiconductor Corporation

--

BCS
-

BRD
BCCNV

H
E
A
D
E
R

RST
'----

•

I
I

POSITIVE
+VREF
REFERENCE

P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

~

1\'-

6DO-BJ..!11
BDR
v

OVRNG

1
I

U
F
F
E
R

-

IOptional
I
Pll
ClKIN

~

DR
CS

CS5412

r,-,

,"-'

DO-D11

-VREF

I NEGATIVE

J

I REFERENCE

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS2DB3

2·335

-____-_

.. ...-.
-. ..--_._.
GENERAL DESCRIPTION
The CDB5412 Evaluation Boardis a stand~alone
environment for easy lab evaluation of the
CS5412 High-Speed Analog-to~Digital Converter.
Positive and negative references are included on
the board and can be configured for ±1.5 volt
bipolar or 0-to-3 volt unipolar operation. The
digital output of theCSS412 is buffered and series
terminated allowing the board to drive
twisted-pair ribbon cable. The CDB5412 also
includes an optional phase-locked-loop (PLL) that
will generate the requisite master clock given a
periodic sample clock. When supplied with the
necessary +5 volt and. -5 volt power supplies and
an analog signal source, the CDB5412 will
provide converted data at the 40 pin header.
The CDBS412 is designed to allow easy and
thorough evaluation of the performance of the
CS5412. The CDB5412 is a four layer board with
one signal layer, two power planes, and a ground
plane; the decoupling scheme is designed to
insure accurate evaluation of the converter's
performance for a wide variance in the quality of
the power supplies.
The CDB5412 can also be used as a performance
benchmark when designing your own system, and
for ideas on appropriate layout schemes.
Before starting an evaluation, we strongly recommend reviewing the CSS412 data sheet. A
thorough understanding of the CS5412 will make
it easier to quickly and fully evaluate the part.

Suggested Evaluation Method
One efficient method of dynamically evaluating
the CS5412 using the CDB5412 is to connect
AIN to a spectrally pure sine wave and collecting
a consecutive number of samples. FFf analysis
can then be done on the samples to produce
signal-to-noise and signal-to-distortion ratios.
2·336

CDB5412

Equipment needed consist of the following:
• CDB5412 Evaluation Board
• Good split power supply capable of supplying
+5V and -Sv,
• A spectrally pure sine wave generator such as
the Krohn-Hite Model 4400A "Ultra-Low
Distortion Oscillator"
• High-speed data storage
• ComputerlPC capable of acquiring data from
high-speed data storage
• A software routine to perform a Fast Fourier
Transform (FFT)

The sine-wave generator supplies the analog signal, AIN, to the CDB5412. Converted data will
appear at the header since the board is, by default,
in the continuous convert mode.
The header is connected to the high-speed storage.
This storage can consist of FIFO's, or static RAM
and counters, or a logic analyzer with the ability
to transfer data to a computer or Pc. If FIFO's or
static RAMs are employed, and a PC is the host
computer, a data acquisition board such as the
Metrabyte Model PI0l2 "24 Bit Parallel Digital
I/O Interface" can be used to transfer the data to
the PC. If the input signal is not synchronized
with the sample frequency so that an integer
number of periods is acquired, the data must be
windowed to avoid end point discontinuities. We
use the Blackman-Harris window which forces
the endpoints to zero. An FFf analysis on the
resulting data will yield spectral information on
the converter. Figure 1 graphically illustrates the
results of such analysis. For Figure 1, 1024
consecutive samples were taken with the
CDB5412 sampling a 100kHz sine wave input at
1 MHz. The samples were modified by the
Blackman-Harris window before FFf analysis.

052083

.._-_
.-_
_
..--_._.
__
...-.

CDB5412

OdB
-2OdB

- - - - - - -

Sampling Rate: 1 MHz

- - - - - - _ _ _ _ _ _ _

Full Scale: 3Vp-p
s/(N+D): 70.3 dB

BOARD DESCRIPTION

MODES

-'OdB

Continuous Convert

-BOdB

Signal
Amplitude

-BOdB

The default mode for the CDB5412 is continuous
convert (CCNV) active with the PLL inactive.
Therefore, the CS5412 is always converting and
the HOLD signal is not used. The part can be
taken out of continuous convert mode in one of
two ways, either by placing a strap jumper on J6
or by driving BCCNV at the stake header low.
Once out of continuous convert mode, the HOLD
signal must be driven. HOLD is described in
greater detail in the "Inputs" section.

Relative to

Full Scale

-l00dB
-120dB

de

100

500

Input Frequency (kHz)

Figure 1. Typical CS5412 FFT Performance

References:
F.J_ HARRIS, "On the Use of Windows for
Harmonic Analysis with the Discrete Fourier
Transfer", Proc_ IEEE, VoL 66, No_ 1, Jan_ 1978.
pp_ 51-83 _

UnipolarlBipolar

The CDB5412 board is factory calibrated for
bipolar mode (AIN = ±1.5 Vpeak). In bipolar
mode, strap jumpers are placed on 13 and J5 (both
marked with a "B") which are located in the
Negative Reference, Figure 2, and the Positive
Reference, Figure 3.

G.D. BERGLAND & M.T. DOLAN, "Fast
Fourier Transform Algorithms", Programs for
Digital Signal Processing, IEEE Press:
0-87942-127-4, Section 1.2.

R32
1k
2
U2
LM336

R40
6.04 k

1

47 k
+5V

R44
R42
20k

C32
TO.1ILF
--

4.02 k

R35
1.78 k

3

C30
O.lILF

I-

-

-5V

C38
10 ILF=.E

6

U4
OP07

+
4

--

I

C3l
O.1ILF

--

-5V

Figure 2. Negative Reference
DS2DB3

2-337

_-_

.. ...
._.-.
-•-_
..--__

CDB5412

+5V

+5V
C35
TO.1I'F

C33
IO.1I'F

R36
1.78k

--

7
3

R39
4.02 k

+

I

R43
20k

C39
1O l'F

=
6

OP07

2

=
-5V

2
U3
LM336

+U5

R41
6.04k

1

C16

R48

+VREF

Figure 3. Positive Reference

To operate the board in unipolar mode (AIN =
AGND to +3 Vpeak), move the strap jumpers to
12 and J4 (both marked with a "U"). The positive
reference pot, R43, must be calibrated to
+3.000 volts at +VREF (pin 7) of the CS5412
converter.
When receiving a new board, Crystal recommends that the reference voltages, +VREF and
-VREF, be verified before operation. The pots located in their respective reference section may be
+5V

+5V

0

tweaked to calibrate the voltage level which
should be measured at the CS5412 converter.
Calibration

Since the Reset switch provides a means to
calibrate the part, the CAL pin is hard-wired to
ground through jumper 11. The reset signal is also
available at the stake header and can be driven by
any source that can drive a 1 ill resistor
connected to +5 volts (see Figure 5).
R3
VO+

l-----~-_--_~

'T'C13
-.L 0.011'F
R2

02

VA4+

0.11'F

GNO 0
--

+
C42
681'F

01

-5V

C28
0.11'F

0 l-----~--------~
-5V

/\~------~-I>

VA3-

10

R4
VO10

Figure 4. Power Supply
2-338

DS2DB3

.-_
_
..---._.
__.._-_
...-.

CDB5412

Figure 4 depicts power supply decoupling for the
CDB5412, along with decoupling for the digital
supplies and the isolated analog supplies, both of
which are low-pass filtered to prevent noise from
coupling into the analog supplies. Since the digital
supply is derived from the analog supply, the
digital supply is guaranteed to be less than or
equal to the analog supply as specified in the
CS5412 data sheet.

INPUTS
Power Supplies

A split supply should be used to generate +5 volts
and -5 volts. These should be connected to their
respective banana jacks on the board. A good
quality low ripple, low noise supply will give the
best performance.

+5V

Header
OVRNG

Cl ClKIN

RST:
+5V

--

C6,C8,C12 =O.OlILF

--

VREFVA4+
VO+
VREF+

HalO
HalO

R12 0

'VV'v .
R11

2
RST
VA5+
VA1+
VA2+
VA3+

--

40
OVRNG
29
Ul ClKIN
28
XIN
10
AGN02 33
AGNOl
OGNO 16
TSTl 17
TST2 9
VREFVA1- 13
VA2- 14
VA4+
VA3- 30
VO+
VoVREF+
39
011 38
010 37
09
CS5412 08 36
07 35
34
06
05 27
04 26
HalO
03 25
24
02
23
01
00 22
21
OROY
20
CS
RO 19
3

ClKIN

- - 'VV'v R13

VAVA3VO011
010
09
--D08
07
06
05
-D04
03
02
01
DOO
OROY
CS
RO
CCNV

--

Figure 5. 5412 Flash AID Converter

DS2DB3

2-339

-

I

.._-_
.-_
.-.-.
_
..--_...

CDB5412

Analog In -AIN

used for parallel termination but must be left open
for the crystal to oscillate (factory setting).
CLKIN can also be generated by the on-board
PLL. The PLL, when active, will generate a
CLKIN frequency eight times the frequency of
the HOLD signal. For more information on the
PLL, see the "Phase-Locked- Loop" section.

The factory setting for AIN is a shorting wire in
R12 and an NPO capacitor, C3, to ground. If the
input signal is noisy, the shorting wire should be
replaced with an appropriate resistor to low-pass
filter the input noise.
In addition to the input filtering capability, Rll is
available for impedance matching. If the source
driving AIN has low impedance, an appropriate
termination resistor should be soldered in Rll.
(see Figure 5.)

Hold -HOLD

As described in the Continuous Convert section,
the CDB5412 is factory set not to use the HOLD
input. Driving the HOLD input while the CS5412
is in the continuous convert mode will give erratic
results. To use the HOLD signal, the CCNY
signal must be driven low by placing a strap
jumper on 16 or by driving the BCCNV signal at
the stake header low. As described in the CS5412
data sheet, the HOLD signal must be modulo
eight and synchronized to the master clock,
CLKIN.

Clock -CLKIN

The CDB5412 has an 8.0000 MHz crystal
installed at the factory which generates a sample
frequency of 1 MHz. If another sample frequency
is desired, either replace the crystal or remove the
crystal from its socket and use the CLKIN BNC
to generate other II1aster clock frequencies. R14
provides series termination of 51 n. R13 may be
+5V

+5V

+5V
0.1!lF
Vdd

16

+8~6~______________~
3

4

R55
47k

T

-=-

14

Serial In
Compln
13
PC2 out
R1

VCOout
5
Reset J-1'--'1-+______~--.----""I
INH
74HC4040
74HC4046
R46
47k
R29
U8
U9 Clock 10
1k
-=6
VCOin
C1A
C1
151lF
7
NPO
C1 B
8
8 GND
Vss

HOLD

-=-

11
R37
2.2k

R30
1k

-=9

R28
301
C25 TO.1!lF

-=CLKIN

Figure 6. Phase-Locked-Loop
2-340

DS2DB3

----------- ----------Since HOLD must not be left floating, the factory
configuration is a shorting wire in RlO (series
termination) and a 47k n resistor (R9) to ground.
This configuration ties HOLD to ground (through
R9) and provides fairly high impedance when
driving HOLD externally.
If the signal source used to drive HOLD is low

impedance, R9 should be replaced with the
appropriate resistor. RIO can provide series
termination.
Phase-Locked-Loop - (PLL)

The CDB5412 contains an optional PhaseLocked-Loop (PLL) which can be used by systems containing a periodic sampling clock,
HOLD, but no master clock, CLKIN. The PLL
generates a clock eight times the frequency of
HOLD and the PLL drives the CLKIN pin.
The schematic for the PLL is shown in Figure 6.
Shorting jumpers on 18 and 110 (both marked
"OUT") disable the PLL (factory setting). To enable the PLL move the jumpers from 18 and 11 0
to 17 and 19 (both marked "IN"). Since the
CLKIN pin is driven by the PLL, the on-board
crystal should be removed and the CLKIN BNC
must not be driven or loaded by an external
source.

CDB5412
OUTPUTS

The 12 data bits output from the CS5412 are
buffered as shown in Figures 7 and 8, which
minimize loading of the converters outputs. Series
resistors are then used to minimize ringing when
connected to twisted-pair ribbon cable. The
+5 volt supply for the buffers is derived from the
analog supply using the same low-pass RC
network used on the digital supplies of the
CS5412.
Three of the signals at the stake header are inputs
to the board (Figure 8). BCS and BRD are pulled
down to ground through a resistor allowing the
CS5412 to continually output data as soon as it
becomes available. The third input is a buffered
continuous convert signal, BCCNY. By default
this signal is pulled up to +5 volts through a resistor, which configures the CS5412 to convert at
one eighth the master clock frequency. (The
HOLD BNC must not be driven in this mode.)
The 20 stake header pins opposite the signal
names are all tied to ground. Signals with a "B"
prefix indicate buffered signals. The "X" and "Y"
pins are unused and allow customization of the
CDB5412 evaluation board.
Figure 9 illustrates the CDB5412 board layout to
help in locating components.

The PLL will not work with a sampling signal,
HOLD, that is not periodic. The PLL is designed
to work with a HOLD signal range of 300 kHz to
1 MHz. To redesign the PLL for other frequencies
see the National Semiconductor 74HC4046 PLL
Data Sheet.

DS2DB3

2-341

I

III

-___

.._--. ..--_._.
...-.

CDB5412

+5V

+5V
R5
10

2

3

4

5

6

011

7

8

9

R49
10 47 k
1
DIR Vee
2 A1

-18

B1

Header

17

BD11:

4 A3
D9C=~----~~-+~~--~--~

16

BD10:

08

15

BD9 :

14

BD8 :

13

BD7 '

12

BD6 '

3 A2

010

B2

05

B3
5 A4
B4
6
U6
A5 74HCT245 B5
7 A6
B6
8 A7
B7

04

9 A8

07
06

B8

GND

8D5 '

11

BD4,

Figure 7. Upper Buffer
+5V
R6
10

R51
47k
1
20
DIR Vee
2
A1
3

D3
D2

R23- R27=75

--

--

A2

B2

A3

B3

A4

B4

Header
: BD3

16

: BD2

15

: BD1
: BOO

CS

U7
14
A5 74HCT245 B5
7
13 B6
A6
8
12 B7
A7

RD

11 B8

4

D1

5

DO

6

DR
CCNV

A8

: BDR
: BCCNV
: BCS

9

: BRD

GNO OE
10

19
R53
47 k

+5V
R52
47 k

l'

J6

~~l:

SIP247k

Figure 8. Lower Buffer
2-342

DS2DB3

----------------------

CDB5412

HOLD

-

elKIN

RSS
r--------------------'D
"~:~h::;t D 1~~"'D'" 61
CRY S TAL

J781H

I

CPTICNAL A..L

I

'-E_V_O_I_U_O_~-I-oI-n-Na-o-rdJ LJ.~ l,~O___ ~;,CJ~~

D

~==~~

BNI R":'a
RBI

~R!~ __ :

::~l-c-~:---1-t

UI

R"

CIIB
CS

I ~
lUI!

CS
C7

OJa

. R7

:

ICSO

I

~D

~

II
I
I
I

L ____

CSI
C31
~~~L~~~~~~

IRe'--_ _~
I
I

"10

111m

....

I-+---I::~

~t:====~:~:
rRei

~~~

0YRI«l
8011
8010

BD9
BD8

'-'-_ _---'Ree

Cta

r-r---,

0

1

OVRIfl

"':~DUS ~~===C:I7: ;: -I~ !~

CI2
CIS

r-"'C8......._.......
RI C9

:~'~ITI"~CS.IDo
I

.

'" ',. :'- ;:. .-..

IRSI~ 0111

aND

m

~~BS

CR

rI - - - - -R4f- - - - - - - - - - - -OUI
-"j2'1

--I--

XT

R!3

Re4
'--_ _ _---'

RIS
RIIi
RI?

upe

I

.

_____ J

O~

O· O·

I

II:::

WO~O"'0~
-5V

GND

+5V

Figure 9. CDB5412 Board Layout

DS2DB3

2-343

I

.._-_
_.-_..--_._.
__
...-.

CDB5412

eNotese

2·344

DS2DB3

... .. .....

...
.
..,
Semiconductor Corporation
~. . . ."""""" 1!6111 •
.",

~

~~

CS5480

I

10-8il/40 MHz AID Converter
Features

General Description

• Monolithic 40 MSPS CMOS ADC
On-chip Track/Hold
On-chip Voltage Reference
+5V Power Supply Only

The CS5480 is a monolithic 10-bit sampling analog-todigital converter capable of 40 MSPS conversion rate.
To achieve high throughput, the CS5480 uses a fully
pipelined architecture. Unique self-calibration circuitry
ensures excellent linearity with no missing codes over
the entire operating temperature range.

• Dynamic performance (fin=3.58MHz)
SNR: 56 dB
THD: 63 dB
SFDR: 68-dB

Digital inputs are CMOS and TTL compatible. Digital
outputs are CMOS compatible. The analog input can
be driven by either a differential 2.4 Vp-p signal, or a
1.2 Vp-p single-ended signal. Output data is available
in offset binary format.
The CS5480 advanced CMOS construction provides
low power consumption and the inherent reliability of
monolithic devices.

• Analog Input Range:
Single-ended Input: 1.2Vp-p
Differential Input: 2.4Vp-p

For more information contact
C stal Semiconductor

• Low Power: 375 mW

VA+

AGND

VD+

DGND

CAL

MUX

VDR+

AIN+

DB9

AIN-

DBO
DRGND
ClK
CALIBRATION
& CONTROL
lOGIC

REF

CREF

VCM

Product Preview
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

VREF+

VREF-

CAL

document contains information for a new product. Crystal
IThis
Semiconductor reserves the right to modify this product without notice.
Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS164PP3
2-345

•

.. ...-..
...,-..__
......

.., ~

..,..,~

..,

CS5480
7

ANALOG CAARACTERISTICS (TA=TMIN to TMAX; VA+, VD+,

VDR1+, VDR2+ = 5.0V;
AGND=DGND=DRGND1=DR<;3ND2=OV; CLK=40MHz; DIF=VD+; REF=+1.2V; CL <10pF)
Parameter*

Symbol

Min

Typ

Max

-40

-

+85

°c

RES

10

-

-

Bits

Specified Temperature Range
Resolution

Units

Accuracy
Linearity Error

(Note 1)

INL

-

. ±1

-

LSB

Differential Linearity Error

(Note 1)

DNL

-

± 1/2 .

LSB

No Missing Codes

(Note 1)

NMC

10

-

-

Offset Error

(Note 1)

Vas

Full Scale Error

(Note 1)

FSE

DC Power Supply Currents

(Note 2)

IA+
ID+
IDR+

Power Dissipation

(Note 2)

Power Supply Rejection Ratio

(Note 3)

-

Bits

±1

-

:%FS

-

-

TBD
TBD
TBD

TBD
TBD
TBD

mA
mA
mA

PD

-

375

500

mW

PSRR

-

70

-

dB

-

-

1.2
2.4

V p•p

-

pF

BW

-

10
200

-

40

-

MHz

CMR

REF

0.6

1.2

1.3

V

RL

-

1

-

k.Q

±5

LSB

Power Supplies

Analog Input
Input Voltage Range

Single-ended Input
Differential Input

Input Capacitance

AIN
CIN

Analog Bandwidth
Common Mode Rejection

-

vp-p

dB

Reference Input
Input Range
Input Impedance
Notes:

1. Applies after calibration at the temperature of interest
2. CL=10pF typical.
3. fin=1kHz

• Refer to the Specification Definitions immediately following the Pin Description section.

Specifications are subject to change without notice.
2-346

DS164PP3

...........
---- ._..
.........
~

~

CS5480

~

ANALOG CHARACTERISTICS (Continued)
Parameter*

Symbol

Min

Typ

Max

Units

-

57
56
54

-

-

dB
dB
dB

-

-63
-63
-60

-

dB
dB
dB

-

9.3
9.0
8.7

-

Bits
Bits
Bits

-

58
56
54

-

dB
dB
dB

-

68

-

dBc

1

-

-

71
68
60

Dynamic Performance
Signal-to-(Noise plus Distortion)
fin
fin
fin
Total Harmonic Distortion

= 1.24 MHz
= 3.58 MHz
= 10.3 MHz

fin
fin
fin

= 1.24 MHz
= 3.58 MHz
= 10.3 MHz

fin
fin
fin

= 1.24 MHz
= 3.58 MHz
= 10.3 MHz

fin
fin
fin

= 1.24 MHz
= 3.58 MHz
= 10.3 MHz

Effective Number of Bits

Signal-to-Noise

(Note 1)

(Note 1)

(Note 1)

(Note 1)

SINAD

THD

ENOB

SNR

-

Spurious Free Dynamic Range

(Note 1)

SFDR

Differential Phase

(Note 1)

DP

Differential Gain
Intermodulation Distortion
2nd Harmonic Distortion
fin
fin
fin
3rd Harmonic Distortion
fin
fin
fin

= 1.24 MHz
= 3.58 MHz
= 10.3 MHz
= 1.24 MHz
= 3.58 MHz
= 10.3 MHz

(Note 1)

DG

(Notes 1, 4)

IMD

(Note 1)

-

(Note 1)

Overvoltage Recovery Time
Note:

tovr

1
60

-

-

71
68
63

-

25

0

%
dB

-

dB
dB
dB

-

dB
dB
dB

-

ns

4. Tested with input signals of 1MHz and 1.05MHz.

• Refer to the Specitication Definitions immediately following the Pin Description section.

Specifications are subject to change without notice.

DS164PP3

2-347

...............
.. _....
.........

.., ..,

·CS5480

~

DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+, VDR1+, VDR2+ = 5V± 5%;
AGND=DGND=DRGND1=DRGND2=OV, Measurements performed under static conditions.)
Parameter

Symbol

Min

Typ

Max

Units

VIH

2.0

-

V

Low-Level Input Voltage

VIL

-

-

0.8

V

High-Level Output Voltage

VOH

{VD+)-0.3

-

-

V

Low-Level Output Voltage

VOL

0.4

V

Input Leakage Current

ILKG

-

+10

!lA

Digital Input Capacitance

CIN

-

-

pF

High-Level Input Voltage

Digital Output Capacitance

COUT

RECOMMENDED OPERATING CONDITIONS

10
10

pF

(AGND, DGND, DRGND1, DRGND2 = OV,

all voltages with respect to ground.)
Parameter
DC Power Supplies:

Positive Analog
Positive Digital
Positive Driver
Single-ended
Differential

Analog Input Voltage
Reference Voltage

ABSOLUTE MAXIMUM RATINGS

Symbol

Min

Typ

Max

Units

VA+
VD+
VDR+

4.75
4.75
4.75

5.0
5.0
5.0

5.25
5.25
5.25

V
V
V

AIN

-

-

1.2
2.4

Vp-p

REF

0.6

1.2

1.3

V

Vp-p

(AGND, DGND,DRGND1,DRGND2 = OV, all voltages with re-

spect to ground.)
Symbol

Min

Typ

Max

Units

VD+
VDR+
VA+

-0.3
-0.3
-0.3

-

6.0
6.0
6.0

V
V
V

lin

-

±10

rnA

lout

±25

rnA

Analog Input Voltage (AIN and VREF pins)

VINA

{VA-)-0.3

Digital Input Voltage

VINL

-0.3

Ambient Operating Temperature

TA

-55

Storage Temperature

Tstg

-65

Parameter
DC Power Supplies

Input Current, Any Pin Except Supplies

Positive Digital
Positive Driver
Positive Analog
(Note 5)

Output Current
Power Dissipation (Total)

Notes:

(Note 6)

-

-

1

W

{VA+)+0.3

V

{VL+)+0.3

V

125

°C

150

°C

5. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a
power supply pin is ± 50mA
6. Total power dissipation, including all input currents and output currents.

WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

2-348

DS164PP3

....-._.-.
.....
_. .........
~

~~-

CS5480

SWITCHING CHARACTERISTICS

(TA = TMIN to TMAX; VA+, VD+, VDR1+, VDR2+ = 5V± 5%;
Input levels: logic 0 = OV, logic 1 = Vl+; CL <10pF
Parameter

Symbol

Conversion Rate

1/tconv

Min

Typ

Max

Units

2

-

40

MHz

60

%

-

ClK
ClKs

-

pSrms

Clock Duty Cycle

40

Acquisition Time

tacq

Pipeline Delay

tpd

Aperture Delay

tapd

10

Aperture Jitter

tapi

Output Delay

tod

-

ClK falling to CAL falling

tsc

2

-

-

ClKs

Start of Calibration to end of calibration

teal

-

800,000

-

ClKs

1
11

3
5

ns
ns

CLK
VD+

~~,~
:J 10 pF
Figure 1. Load Circuit for timing tests

tcAL------>I
STATE _ _---'S:...:T'-'-AN:..::D:..:B;..:.y_ _--"I'-_...:.C'-"Al:::;IB:..:.R.::..A"-TI...:.O'-'-N_JI'-''-''-'-=-=--

Figure 2. Calibration Timing

N

Analog
Input

N+l

ClK

DBO-DB9

Figure 3. Timing Diagram

DS164PP3

2-349

...............
--- .....
.............

CS5480

PIN DESCRIPTIONS·
POSITIVE~IGITAL

SUPPLY

DIGITAL GROUND
CALIBRATE
CLOCK INPUT

OG~ ~ ~~:; ~~~~::~;(MSB)

DIFFERENTIAL INPUT MODE

DIF \

POSITIVE ANALOG INPUT

AIN+ --\,
AIN- ~

NEGATIVE ANALOG INPUT

3

2

VCM -

8

VOLTAGE REFERENCE

VREF+ ~

9

VOLTAGE REFERENCE

VREFCREF -.!

r
/

~

28 Z7

26 25

6
7

VREF COMMON MODE

VREF BYPASS CAPACITOR

4

24
28

CS5480

---./10
- /
13 14

15

"

DATA BIT 5

r- VDR2+

POSITIVE DRIVER POWER

-

DRGND2 OUTPUT DRIVER GROUND

21

"-

DRGND1 OUTPUT DRIVER GROUND

19
12

DATA BIT 6

DB5

22

20~

11

DB6

17 "

\ -

VDR1 +

L DB4

POSITIVE DRIVER POWER
DATA BIT 4

REFERENCE INPUT/OUTPUT

REF

DB3

DATA BIT 3

ANALOG GROUND

AGND

DB2

DATA BIT 2

POSITIVE ANALOG POWER

VA+

DB1

DATA BIT 1

DBO

DATA BIT 0 (LSB)

Power Supply Connections

VA+ - Positive Analog Power, PIN 14
Positive analog supply voltage. Nominally +5 volts.
VD+ • Positive Digital Power, PIN 1
Positive digital supply voltage. Nominally +5 volts.
VDR1+, VDR2+ - Positive Output Driver Power, PINS 20, 23
Positive output driver supply voltage. Nominally +5 volts.
AGND - Analog Ground, PIN 13
Analog ground reference.
DGND· Digital Ground, PIN 2
Digital ground reference.
DRGND1, DRGND2 - Output Driver Ground, PINS 21, 22
Output Driver ground reference.
Analog Inputs

AIN+, AIN·· Analog Input, PINS 6,7
AIN+ is the positive analog input signal to the differential input of the TIH amplifier. AIN- is
the negative analog input signal to the differential input of the TIH amplifier. AIN- is normally
tied to VCM for single-ended operation.
2·350

DS164PP3

_....... ...._......,

..,..,

_..,

~~-

CS5480

Reference Connections

VCM - Voltage Reference Common Mode, PIN 8
Signal common, nominally 2.5 volts.
VREF+ - Positive Voltage Reference, PIN 9
Positive full-scale voltage, nominally 3.1 volts.
VREF- - Negative Voltage Reference, PIN 10
Negative full-scale voltage, nominally 1.9 volts.
CREF - Voltage Reference Bypass Capacitor, PIN 11
Internal voltage reference must be bypassed with a O.l~ capacitor in parallel with a lOOOpF
ceramic chip capacitor to analog ground. No other external connection allowed.
REF - Reference Input/Output, PIN 12
Internal voltage reference output, or optional external voltage reference input.
respect to AGND represents the full-scale input range. Nominally 1.2 volts.

Taken with

Digital Inputs

CAL - Calibrate, PIN 3
Calibration command. If brought low for 1 clock cycle or more, the CS5480 will reset and
initiate an internal calibration. Calibrates for differential input signal (DIF=1) and single-ended
input (DIF=O). Any spurious glitch on this pin may inadvertently place the chip in the
calibration mode.
DIF - Differential Input Mode, PIN 5
With the DIF pin low, the device is configured for single-ended operation. With the DIF pin
high, the device is configured for differential input operation.
Digital Outputs

DBO through DB9 - Data Bus Outputs, PINS 15-19,24-28
Data Bit 0 (LSB) through Data Bit 9 (MSB).
Clock Generator

CLK - Clock Input, PIN 4
A CMOS compatible clock must be input to the CLK pin to serve as the master clock for the
device. A master clock must be present at all times to ensure proper operation of the device.

DS164PP3

2-351

...........
._..
...,..,.,., .....
~

~

CS5480

DEFINITIONS
Linearity Error - INL
The deviation of a code from a straight line passing through the endpoints of the transfer
function after zero and gain errors have been accounted for. "Zero-scale" is a point 112 LSB
below the first code transition and "full-scale" is a point 112 LSB beyond the code transition to
all ones. The deviation is measured from the middle of each particular code. Units in LSB's.
Differential Nonlinearity Error - DNL
The minimum resolution for which no missing codes is guaranteed. Units in LSB's.
Offset Error - VOS
The deviation of the first code transition from the ideal (VREF- + lLSB). Units in LSB's.
Fnll Scale Error - FSE
The deviation of the last code transition from the ideal (VREF- - lLSB). Units in LSB's.
Signal-to-Noise - SNR
The ratio of the rms value of the signal, to the rms sum of all other spectral components
(excepting de and distortion terms). Expressed in decibels (dB).
Signal-to- (Noise plus Distortion) - SINAD
The ratio of the rms value of the signal, to the rms sum of all other spectral components
(excepting de), including distortion components. Expressed in decibels (dB).
Total Harmonic Distortion - THD
The ratio of the rms sum of the significant (2nd through Sth) harmonics, to the rms value of the
signal. Expressedin decibels (dB) or percent (%).
Intermodulation Distortion - IMD
The ratio of the rms value of the larger of the two test frequencies, which are each 6dB down
from full-scale, to the rms value of the largest 2nd order and 3rd order intermodulation
component. Expressed in decibels (dB).
Effective Number of Bits - ENOB
A measure of ac linearity and is calculated from: ENOB = [(SNR - 1.76)/6.02]
Spurious Free Dynamic Range - SFDR
The ratio of the rms value of the signal, to the rms value of the next largest spectral component
(excepting de). This component is often an aliased harmonic. Units in percent (%) and
decibels relative to the carrier (dBc).
Differential Phase - DP
The difference in the output phase of a small high frequency sine wave at two stated levels of a
low frequency signal on which it is superimposed. Units in degrees.
2-352

DS164PP3

---- ._...,.
...........
.............

CS5480

Differential Gain· DG
The difference between the output amplitudes of a small high frequency sine wave at two stated
levels of a low frequency signal on which it is superimposed. Units in percent (%).
Overvoltage Recovery Time· tovr
The time required for the ADC to recover to full accuracy after an analog signal 150% of full
scale is reduced to 50% of the full-scale value. Units in nanoseconds.
Aperture Delay· tapd
The time delay between the falling edge and the actual start of the HOLD mode in a Track and
Hold function. Units in nanoseconds.
Aperature Jitter . tapj
The range of variation in the aperature time. Effectively a "sampling window" which ultimately
dictates the maximum input slew rate acceptable for a given accuarcy. Units in picoseconds.
Pipeline Delay . tpd
The number of clock cycles between the initiation of the conversion process and the associated
output data bit being available. Expressed in clock cycles.
Full Power Bandwidth
The input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB
for a full-scale input.

DS164PP3

2-353

.. ....... ..-.,.,.,.,
.....
~~

~

_.

~~

C$S480

• Notes.

2-354

DS164PP3

.
...,....,...........
.
...
~

~~~

.."

~~

CS5481

Semiconductor Corporation

10-Bit, 20 MHz AID Converter

fill

Features

General Description

• Monolithic 20 MSPS CMOS ADC
On-chip Track/Hold
On-chip Voltage Reference
+5V Power Supply Only

The CS5481 is a monolithic 10-bit sampling analog-todigital converter capable of 20 MSPS conversion rate.
To achieve high throughput, the CS5481 uses a fully
pipelined architecture. Unique self-calibration circuitry
ensures excellent linearity with no missing codes over
the entire operating temperature range.

• Dynamic Performance (fin= 1.24 MHz):
SNR: 58 dB
THD: 63 dB
SINAD: 57 dB

Digital inputs are CMOS and TTL compatible. Digital
outputs are CMOS compatible. The analog input can
be driven by either a differential 2.4 Vp-p signal, or a
1.2 Vp-p single-ended signal. Output data is available
in offset binary format.
The CS5481 advanced CMOS construction provides
low power consumption and the inherent reliability of
monolithic devices.

• CMOS Outputs
• Analog Input Range:
Single-ended Input: 1.2Vp-p
Differential Input: 2.4Vp-p

For more information contact
C stal Semiconductor

• Low Power: 200 mW
AGND

VA+

VD+

DGND

CAL

MUX

VDR+

AIN+

DB9

AIN-

DBO
DRGND
ClK
CALIBRATION
& CONTROL
lOGIC

REF

CREF

VCM

Product Preview
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

VREF+

I

VREF-

~----4DIF

CAL

This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Copyright © Crystal Semiconductor Corporation. 1995
(All Rights Reserved)

MAR '95
DS179PP1
2-355

-

......
............
.-...
-.-..

~

~

CS5481

~

ANALOG CHARACTERISTICS (TA=TMIN to TMAX; VA+, VD+, VDR1+, VDR2+ = 5.0V:
AGND=DGND=DRGND1=DRGND2=OV; CLK=20MHz; DIF::VD+; REF=+1.2V; CL < 10pF)
Parameter*

Symbol

Resolution

Min

Typ

Max

Units

-40

-

+85

°C

RES

10

-

-

Bits

±1

-

LSB

± 1/2

Specified Temperature Range

Accuracy
Linearity Error

(Note 1)

INL

Differential Linearity

(Note 1)

DNL

-

No Missing Codes

(Note 1)

NMC

10

-

Bits

(Note 1)

Vos

-

-

Offset Error

±5

LSB

Full Scale Error

(Note 1)

FSE

-

±1

-

%FS

(Note 2)

IA+
10+
IDR+

-

-

TBD
TBD
TBD

TBD
TBD
TBD

mA
mA
mA

LSB

Power Supplies
DC Power Supply Currents

Power Dissipation

(Note 2)

Po

200

mW

(Note 3)

PSRR

-

TBD

Power Supply Rejection Ratio

70

-

dB

AIN

-

Analog Input
Input Voltage Range

Single-ended Input
Differential Input

Input Capacitance
Analog Bandwidth
Common Mode Rejection

-

1.2
2.4

Vp-p

CIN

-

10

-

pF

vp-p

BW

-

200

-

40

-

MHz

CMR

REF

0.6

1.2

1.3

V

RL

-

1

-

kQ

dB

Reference Input
Input Range
Input Impedance
Notes:

1. Applies after calibration at the temperature of interest
2. CL=10pF typical.
3. fin=1kHz

* Refer to the Specification Definitions immediately following the Pin Description section.

Specifications are subject to change without notice.

2-356

DS179PP1

_.-.......__....._-_
..._.-.
."

CS5481

ANALOG CHARACTERISTICS (Continued)
Parameter*

Symbol

Min

Typ

Max

Units

-

-

57
56

-

dB
dB

-

63
63

-

dB
dB

-

9.2
9.0

-

58
56

Dynamic Performance

Signal-to-(Noise plus Distortion)
fin = 1.24 MHz
fin = 3.58 MHz

(Note 1)

Harmonic Distortion

(Note 1)

SINAD

THO

fin = 1.24 MHz
fin = 3.58 MHz
Effective Number of Bits

(Note 1)

ENOB

fin = 1.24 MHz
fin = 3.58 MHz
Signal-to-Noise

(Note 1)

SNR

fin = 1.24 MHz
fin = 3.58 MHz
Spurious Free Dynamic Range

(Note 1)

SFDR

Differential Phase

(Note 1)

DP

Differential Gain
Intermodulation Distortion

Bits
Bits
dB
dB

1

-

1

-

%

-

dB

68

(Note 1)

DG

-

(Notes 1, 4)

IMD

-

60

tovr

-

100

Overvoltage Recovery Time
Note:

-

-

dBc
0

ns

4. Tested with input signals of 1MHz and 1.05MHz.

• Refer to the Specitication Definitions immediately following the Pin Description section.

Specitfications are subject to change without notice.
DS179PP1

2-357

-

CSS481·

DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+,~VDR1+, vDR2+ = 5V± 5%;
AGND=DGND=DR~ND1=DRGND2=OV, Measurements performed under static conditions.)

Parameter

Symbol

Min

Typ

Max

Units

VIH

2.0

-

-

V

0.8

V

-

V

-

0.4

V

-

± 10

jlA

10

-

pF

10

-

pF

High-Level Input Voltage
Low-Level Input Voltage

VIL

-

High-Level Output Voltage

VOH

(VD+)-0.3

Low-Level Output Voltage.

VOL

-

Input Leakage Current

ILKG

Digital Input Capacitance

CIN

Digital Output Capacitance

COUT

RECOMMENDED OPERATING CONDITIONS

(AGND, DGND, DRGND1, DRGND2 = OV,

all voltages with respect to ground.)
Parameter
DC Power Supplies

Positive Analog
Positive Digital
Positive Driver
Single-ended
Differential

Analog Input Voltage
Reference Voltage

Symbol

Min

Typ

Max

Units

VA+
VD+
VDR+

4.75
4.75
4.75

5.0
5.0
5.0

5.25
5.25
5.25

V
V
V

-

-

-

1.2
2.4

Vp-p
vp-p

0.6

1.2

1.3

V

AIN
REF

ABSOLUTE MAXIMUM RATINGS

(AGND, DGND,DRGND1,DRGND2 = OV, all voltages with re-

spect to ground.)
Symbol

Min

Typ

Max

Units

VD+
VDR+
VA+

-0.3
-0.3
-0.3

-

6.0
6.0
6.0

V
V
V

lin

-

±10

mA

lout

±25

mA

Analog Input Voltage (AIN and VREF pins)

VINA

(VA-)-0.3

Digital Input Voltage

VINL

Ambient Operating Temperature
Storage Temperature

Parameter
DC Power Supplies

Input Current, Any Pin ExceptSupplies

Positive Digital
Positive Driver
Positive Analog
(Note 5)

Output Current
Power Dissipation (Total)

Note:

(Note 6)

-

500

mW

(VA+)+0.3

V

-0.3

-

(VL+)+0.3

V

TA

-55

-

125

°C

Tstg

-65

-

150

°C

5. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a
power supply pin is ± SOmA
6. Total power dissipation, including all input currents and output curents.

WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

2-358

DS179PP1

._.-.
_.-_....__.._-_
...
~-

CS5481

SWITCHING CHARACTERISTICS
Input levels: logic 0

(TA = TMIN to TMA)G VA+, VD+, VDR1+, VDR2+ = 5V± 5%;

= OV, logic 1 = Vl+; CL <10pF)
Parameter

Symbol

Conversion Rate

Min

Typ

Max

Units

2

-

20

MHz

40

60

0/0

tacq

-

1

ClK

11

10

-

1/teonv

Clock Duty Cycle
Acquisition Time
Pipeline Delay

tpd

Aperture Delay

tapd

Aperture Jitter

tapj

-

Output Delay

tod

-

ClK falling to CAL falling

tsc

2

-

Start of Calibration to end of calibration

teal

-

800,000

3
5

ClKs
ns
pSrms
ns
ClKs
ClKs

ClK
VD+

~o--l~

:J 10pF

Figure 1. Load Circuit for timing tests

STATE

Figure 2. Calibration Timing

N

Analog
Input

N+l

ClK

OBO- OB9

Figure 3. Timing Diagram

DS179PP1

2·359

......._.-.
............
---,.
~

.",

CS5481

.",

PIN DESCRIPTIONS
POSITIVE DIGITAL SUPPLY
DIGITAL GROUND
CALIBRATE

DGV:~

;. ~ ~~:~

CLOCK INPUT
DIFFERENTIAL INPUT MODE
POSITIVE ANALOG INPUT

AIN+

VREF COMMON MODE
VOLTAGE REFERENCE
VREF BYPASS CAPACITOR

~

AIN- ~

NEGATIVE ANALOG INPUT
VOLTAGE REFERENCE

~DB'

5

4

3

2

~

28 V

'" 25

6

VCM
VREF+ ---../ 9
~10
VREF- ~ / 11
CREF ~

24

CS5481

22

;;-

DB5

r- VDR2+

DATA BIT 9 (MSB)

~~~~:~:
DATA BIT 5
POSITIVE DRIVER POWER

DRGND2 OUTPUT DRIVER GROUND

-

DRGND1 OUTPUT DRIVER GROUND
20"- VDR1+
POSITIVE DRIVER POWER
12" 14 15 16 17

21

"--

19

\

16

~

'-

DB4

DATA BIT 4

REFERENCE INPUT/OUTPUT

REF

DB3

DATA BIT 3

ANALOG GROUND

AGND

DB2

DATA BIT 2

POSITIVE ANALOG POWER

VA+

DB1

DATA BIT 1

DBO

DATA BIT 0 (LSB)

Power Supply Connections

VA+ - Positive Analog Power, PIN 14
Positive analog supply voltage. Nominally +5 volts.
VD+ - Positive Digital Power, PIN 1
Positive digital supply voltage. Nominally +5 volts.
VDR1 +, VDR2+ - Positive Output Driver Power, PINS 20, 23
Positive output driver supply voltage. Nominally +5 volts.
AGND - Analog Ground, PIN 13
Analog ground reference.
DGND - Digital Ground, PIN 2
Digital ground reference.
DRGND1, DRGND2 - Output Driver Ground, PINS 21, 22
Output Driver ground reference.
Analog Inputs

AIN+, AIN- - Analog Input, PINS 6, 7
AIN+ is the positive analog input signal to the differential input of the TIH amplifier. AIN- is
the negative analog input signal to the differential input of the TIH amplifier. AIN- is normally
tied to VCM for single-ended operation.
DS179PP1

2-360

..................
.......
.....
- ..._.

..,

.."

CS5481

Reference Connections

VCM - Voltage Reference Common Mode, PIN 8
Signal common, nominally 2.5 volts.

fill

VREF+ - Positive Voltage Reference, PIN 9
Positive full-scale voltage, nominally 3.1 volts.

I

VREF- - Negative Voltage Reference, PIN 10
Negative full-scale voltage, nominally 1.9 volts.
CREF - Voltage Reference Bypass Capacitor, PIN 11
Internal voltage reference must be bypassed with a O.ljlF capacitor in parallel with a 1000pF
ceramic chip capacitor to analog ground. No other external connections allowed.
REF - Reference Input/Output, PIN 12
Internal voltage reference output, or optional external voltage reference input.
respect to AGND represents the full-scale input range. Nominally 1.2 volts.

Taken with

Digital Inputs

CAL - Calibrate, PIN 3
Calibration command. If brought low for 1 clock cycle or more, the CS5481 will reset and
initiate an internal calibration. Calibrates for differential input signal (DIF= I) or single-ended
input (DIF=O). Any spurious glitch on this pin may inadvertently place the chip in the
calibration mode.
DIF - Differential Input Mode, PIN 5
With the DIF pin low, the device is configured for single-ended operation. With the DIF pin
high, the device is configured for differential input operation.
Digital Outputs

DBO through DB9 - Data Bus Outputs, PINS 15-19, 24-28
Data Bit 0 (LSB) through Data Bit 9 (MSB).
Clock Generator

CLK - Clock Input, PIN 4
A CMOS compatible clock must be input to the CLK pin to serve as the master clock for the
device. A master clock must be present at all times to insure proper operation of the device.

2-361

DS179PP1

------.._-------------

CS5481

DEFINITIONS
Linearity Error - INL
The deviation of a code from a straight line passing through the endpoints of the transfer
function after zero and gain errors have been accounted for. "Zero-scale" is a point 112 LSB
below the first code transition and "full-scale" is a point 112 LSB beyond the code transition to
all ones. The deviation is measured from the middle of each particular code. Units in LSB's.
Differential Nonlinearity - DNL
The minimum resolution for which no missing codes is guaranteed. Units in LSB's.
Offset Error - Vos
The deviation of the first code transition from the ideal (VREF- + lLSB). Units in LSB's.
Full Scale Error - FSE
The deviation of the last code transition from the ideal (VREF- - lLSB). Units in LSB's.
Signal-to-Noise - SNR
The ratio of the rms value of the signal, to the rms sum of all other spectral components
(excepting dc and distortion terms). Expressed in decibels (dB).
Signal-to- (Noise plus Distortion) - SINAD
The ratio of the rms value of the signal, to the rms sum of all other spectral components below
the Nyquist rate (excepting dc), including distortion components. Expressed in decibels (dB).
Total Harmonic Distortion - THD
The ratio of the rms sum of the significant (2 nd through 5th ) harmonics to the rms value of the
signal. Expressed in decibels (dB) or percent (%).
Intermodulation Distortion - IMD
The ratio of the rms value of the larger of the two test fre~uencies, which are 6dB down from
full-scale, to the rms value of the largest 2nd order and 3f order intermodulation components.
Expressed in decibels (dB).
Effective Number of Bits - ENOB
A measure of ac linearity and is calculated from: ENOB

= [(SNR - 1.76)/6.02]

Spurious-Free-Dynamic-Range - SFDR
The ratio of the rms value of the signal, to the rms value of the next largest spectral component
(excepting dc). This component is often an aliased harmonic. Units in percent (%) and
decibels relative to the carrier (dBc).
Differential Phase - DP
The difference in the output phase of a small high frequency sine wave at two stated levels of a
low frequency signal on which it is superimposed. Units in degrees.
DS179PP1

2-362

-_
..
__
....
...._- ...
•

..w _ _ . _ .

..,

CS5481

Differential Gain - DG
The difference between the output amplitudes of a small high frequency sine wave at two stated
levels of a low frequency signal on which it is superimposed. Units in percent (%).
Over voltage Recovery Time - tovr
The time required for the ADC to recover to full accuracy after an analog signal 150% of full
scale is reduced to 50% of the full-scale value. Units in nanoseconds.
Aperture Delay - tapd
The time delay between the falling edge and the actual start of the HOLD mode in a Track and
Hold function. Units in nanoseconds.
Aperture Jitter - tapj
The range of variation in the aperture time. Effectively a "sampling window" which ultimately
dictates the maximum input slew rate acceptable for a given accuracy. Units in picoseconds.
Pipeline Delay - tpd
The number of clock cycles between the initiation of the conversion process and the associated
output data bit being available. Expressed in clock cycles.
Full Power Bandwidth
The input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB
for a full-scale input.

2-363

DS179PP1

-

I"

_.--....,-__.._-_
...
.-.-.

CS5481

• Notes.

DS179PP1

2-364

..........
.... ..
..............
~

~~

CS5490

Semiconductor Corporation

12-8it, 20 MHz AID Converter
Features

General Description

• Monolithic 20 MSPS CMOS ADC
On-chip Track/Hold
On-chip Voltage Reference
+5V Power Supply Only

The CS5490 is a monolithic 12-bit sampling analog-todigital converter capable of 20 MSPS conversion rate.
To achieve high throughput, the CS5490 uses a fully
pipelined architecture. Unique self-calibration circuitry
ensures excellent linearity with no missing codes over
the entire operating temperature range.

• Dynamic Performance (fin=4.97MHz):
SNR: 62 dB
THO: 66 dB
SFDR: 70 dB

Digital inputs are CMOS and TTL compatible. Digital
outputs are CMOS compatible. The analog input can
be driven by either a differential 2.4 Vp-p signal, or a
1.2 Vp-p single-ended signal. Output data is available
in offset binary format.
The CS5490 advanced CMOS construction provides
low power consumption and the inherent reliability of
monolithic devices.

• Analog Input Range:
Single-ended Input: 1.2Vp-p
Differential Input: 2.4Vp-p

For more information contact
C stal Semiconductor

• Low Power: 225 mW

VA+

AGND

VD+

DGND

VDR+
AIN+

DB11

AIN-

DBO

DRGND
CLK
!+----4DIF

REF

CREF

VCM

Product Preview

VREF+

VREF-

CAL

document contains information for a new product. Crystal
IThis
Semiconductor reserves the right to modify this product without notice.

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS165PP1
2-365

........ ..,..
...............
..........
~

~

..,

CS5490

• Notes.

2-366

DS165PP1

......
...............
.., ........
~~~

CS5501 CS5503

Semiconductor Corporation

Low-Cost, 16 & 20-Bit Measurement AID Converter
Features

General Description
The CS5501 and CS5503 are low-cost CMOS AID converters ideal for measuring low-frequency signals
representing physical, chemical, and biological processes. They utilize charge-balance techniques to
achieve 16-bit (CS5501) and 20-bit (CS5503) performance with up to 4kHz word rates at very low cost.

• Monolithic CMOS ADC with Filtering
6-Pole, Low-Pass Gaussian Filter
• Up to 4kHz Output Word Rates
• On Chip Self-Calibration Circuitry
- Linearity Error: ±O.0003%
- Differential Nonlinearity:
CS5501: 16-Bit No Missing Codes
(DNL ±1/8LSB)
CS5503: 20-Bit No Missing Codes
• System Calibration Capability

The converters continuously sample at a rate set by the
user in the form of either a CMOS clock or a crystal.
On-chip digital filtering processes the data and updates
the output register at up to a 4kHz rate. The converters'
low-pass, 6-pole Gaussian response filter is designed to
allow corner frequency settings from .1 Hz to 10Hz in
the CS5501 and .5Hz to 10Hz in the CS5503. Thus,
each converter rejects 50Hz and 60Hz line frequencies
as well as any noise at spurious frequencies.
The CS5501 and CS5503 include on-chip self-calibration circuitry which can be initiated at any time or
temperature to insure offset and full-scale errors of typically less than 1/2 LSB for the CS5501 and less than
4LSB for the CS5503. The devices can also be applied
in system calibration schemes to null offset and gain
errors in the input channel.

• Flexible Serial Communications Port
- IlC-Compatible Formats
3-State Data' and Clock Outputs
- UART Format (CS5501 only)

• Low Power Consumption: 25mW
- 10llW Sleep Mode for Portable
Applications

Each device's serial port offers two general purpose
modes of operation for direct interface to shift registers
or synchronous serial ports of industry-standard microcontrollers. In addition, the CS5501's serial port offers a
third, UART-compatible mode of asynchronous communication.

• Evaluation Boards Available

ORDERING INFORMATION:

• Pin-Selectable Unipolar/Bipolar Ranges

BP/UP SLEEP
12

SC1

Page 2-400

SC2

11
CAL

---

VREF
AIN

10
6-Pole Gaussian
low-Pass Digital Filter

9

I

14 VA+

I
I

15 VD+

--- )

AGND

8

DGND

5

7
6

VA-

VDSDATA

ClKOUT ClKIN

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760

(512) 445 7222 FAX: 512 445 7581

DRDY

CS

MODE

SClK

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS31F2
2-367

•

_.-_..--_._.
__.._-_
...-.

CS5501/CS5503·

INDEX
~
Analog Characteristic
Dynamic Characteristics
Digital Characteristics .
Absolute Maximum Ratings
Recommended Operating Conditions
Switching Characterisitcs
Timing Relationships .
General Description
The Delta-Sigma Conversion Method
Overview of the CS5501 .
Serial Interface Logic .
Synchronous Self-Clocking Mode
Synchronus External Clocking Mode
Asynchronous Communication Mode
Linearity Performance
Understanding Converter Calibration .
Initiating Calibration .
Some Additional Points on Using The
System Calibration Modes
Underrange andOverrange Considerations
System Synchronization
Analog Input Impedance Considerations
Amilog Input Drift Considerations
Filtering
Anti~Alias Considerations .
Voltage Reference Connection
Power Supplies and Grounding
Power-Up and Initialization
Sleep Mode
Battery Backed-Up Calibrations
Output Loading Considerations
Pinout
Pin Descriptions
Specification Definitions
Ordering Guide
Appendix A: Applications
68HCIl1CS5501 Serial Interface
COPS/CS5501 Interface
Serial Timing Example - COPS
MeS51 (8051)/CS5501 Serial Interface
MCS51(8051)1CS5501 UARTInterface
TMS70X2/CS5501 Serial Interface
2·368

~

2-369
2-372
2-373
2-373
2-374
2-374
2-375
2-378
2-378
2-379
2-380
2-380
2-382
2-382
2-383
2-384
2-386
·2-387
2-387
2-388
2-388
2-389
2-390
2-391
2-392
2-392
2-394
2-394
2-394
2-395
2-396
2-396
2-399
2-400
2-401
2-403
2-403
2-404
2-405
2-405
2-406
DS31F2

----------- -----------

CS5501/CS5503

CS5501 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD- = -5V; VREF = 2.5V; CLKIN = 4.096MHz; Bipolar Mode; MODE = +5V; Rsource = 7500 with a 1nF
to AGND at AIN (see Note 1); Digital Inputs: Logic 0 = GND; Logic 1 = VD+; unless otherwise specified.)
CS5501-A, B, C
Parameter"

Min

Specified Temperature Range

Typ

CS5501-S, T

Max

Min

-40 to +85

Typ

Max

-55 to +125

Units
°C

Accuracy
-A, S
-B, T
-C

Linearity Error

-

Full Scale Error

(Note 2)

-

Full Scale Drift

(Note 3)

-

Unipolar Offset

(Note 2)

Unipolar Offset Drift

(Note 3)

Differential Nonlinearity

TMIN to TMAX

0.0015
0.0007
0.0003

0.003
0.0015
0.0012

-

±1/8

±1/2

±0.13

±0.5

±1.2

-

-

±0.25

±1

±4.2

-

±0.25

±1

±2.1

-

±D.5

±2

±D.6

-

Bipolar Offset

(Note 2)

Bipolar Offset Drift

(Note 3)

-

Bipolar Negative Full Scale Error

(Note 2)

-

Bipolar Negative Full Scale Drift

(Note 3)

-

-

0.0007

0.003
0.0015

±%FS
±%FS
±%FS

±1/8

±1/2

LSB16

±0.13

±0.5

LSB16

±2.3

-

LSB16

±0.25

±1

LSB16

+3.0
-25.0

-

LSB16

-

±D.25

±1

LSB16

+1.5
-12.5

-

LSB16

-

±D.5

±2

LSB16

±1.2

-

LSB16

1/10
LSBrms
1/10
Noise (Referred to Output)
Notes: 1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the
master clock frequency. Both source resistance and shunt capacitance are therefore critical in
determining the CS5501 's source impedance requirements. For more information refer the text section
Analog Input Impedance Considerations.
2. Applies after calibration at the temperature of interest.
3. Total drift over the specified temperature range since calibration at power-up at 25°C (see Figure 11).
This is guaranteed by deSign and lor characterization. Recalibration at any temperature will remove
these errors.

!LV
10

Bipolar Mode
Unipolar Mode
%FS
ppm FS
LSB's
%FS ppm FS LSB's
0.26

0.0004

4

0.13

0.0002

19

0.50

0.0008

8

0.26

0.0004

4

38

1.00

0.0015

15

0.50

0.0008

8

76

2.00

0.0030

30

1.00

0.0015

15

2.00

0.0030

30

152

4.00

0.0061

61

2

CS5501 Unit Conversion Factors, VREF = 2.5V
• Refer to the Specification Definitions immediately fOllowing the Pin Description Section.
DS31F2

2-369

-

----------- -----------

CS5501/CS5503

CS5503 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD- = -5V; VREF = 2.5V; CLKIN = 4.096MHz; Bipolar Mode; MODE = +5V; Rsource = 750n with a 1nF
to AGND at AIN (see Note 1): unless otherwise specified.)
CS5503-A, B, C
Parameter*

Min

Specified Temperature Range

Typ

CS5503-S, T

Max

Min

-40 to +85

Typ

Max

Units

DC

-55 to +125

Accuracy
-A, S
-B, T
-C

-

0.003
0.0015
0.0012

-

0.0007

0.003
TBD

-

0.0015
0.0007
0.0003

±%FS
±%FS
±%FS

TMIN to TMAX

-

20

-

-

20

-

Bits

±4

±16

-

±4

±16

LSB20

±19

-

-

±37

-

LSB20

±4

±16

-

±4

±16

LSB20

±67

-

-

+48
-400

-

LSB20

Linearity Error

Differential Nonlinearity
(Not Missing Codes)

-

Full Scale Error

(Note 2)

Full Scale Error Drift

(Note 3)

Unipolar Offset

(Note 2)

Unipolar Offset Drift

(Note 3)

-

Bipolar Offset

(Note 2)

-

±4

±16

-

±4

±16

LSB20

Bipolar Offset Drift

(Note 3)

-

±34

-

-

+24
-200

-

LSB20

Bipolar Negative Full Scale Error

(Note 2)

-

±8

±32

-

±8

±32-

LSB20

Bipolar Negative Full Scale Drift

(Note 3)

-

±10

±20

1.6

-

1.6

-

LSB20

-

-

-

Noise (Referred to Output)

LSBrms
(20)

Bipolar Mode
Unipolar Mode
%FS
ppm Fs LSB's
%FS
ppm FS
IlV LSB's
0.596 0.25 0.0000238 0.24
0.13 0.0000119 0.12
1.192

0.50 0.0000477 0.47

0.26

0.0000238

0.24

2.384

1.00 0.0000954 0.95

0.50

0.0000477

0.47

4.768

2.00 0.0001907

1.91

1.00

0.0000954

0.95

9.537 4.0000.0003814 3.81

2.00

0.0001907

1.91

CS5503 Unit Conversion Factors, VREF = 2.5V

* Refer to the Specification Definitions immediately following the Pin Description Section.

2-370

DS31F2

---------------_ ar _ _ _ _ _

CS5501/CS5503

ANALOG CHARACTERISTICS (Continued)
CS550113-A, B, C
Parameter*

CS550113-S, T

Min

Typ

Max

Min

Typ

Max

Units

-

2
2
1
0.03

3.2
3.2
1.5
0.1

-

2
2
1
0.03

3.2
3.2
1.5
0.1

mA
mA
mA
mA

-

25
10

40
20

-

25
10

40
40

mW
JlW

-

70
75

-

-

-

70
75

-

dB
dB

-

-

Power Supplies
DC Power Supply Currents
IA+
IA10+
10Power Dissipatio_n_ _
SLEEP High
SLEEP Low

-

(Note 4)

(Note 4)

Power Supply Rejection
Positive Supplies
Negative Supplies

(Note 5)

-

-

-

Analog Input
Analog Input Range
Unipolar

o to +2.5

o to +2.5

Bipolar
Input Capacitance
DC Bias Current

(Note 1)

-

±2.5

-

20

-

1

V

±2.5

-

20

-

pF

1

-

nA

V

System Calibration Specifications
Positive Full Scale Calibration Range

VREF+0.1

VREF+0.1

Positive Full Scale Input Overrange

VREF+0.1

VREF+0.1

V

Negative Full Scale Input Overrange

-(VREF+0.1 )

-(VREF+0.1 )

V

-(VREF +0.1)
-40%VREF to +40%VREF

-(VREF +0.1)
-40%VREF to +40%VREF

V
V

SO%
VREF

SO%
VREF

Maximum Offset
Calibration Range
Unipolar Mode
Bipolar Mode
Input Span
Notes:

V

(Notes 6, 7)

(Note S)

2VREF
+0.2

2VREF
+0.2

V
4. All outputs unloaded.
5. 0.1 Hz to 10Hz. PSRR at 60 Hz will exceed 120 dB due to the benefit of the digital filter.
6. In unipolar mode the offset can have a negative value (-VREF) such that the unipolar mode can mimic
bipolar mode operation.
7. The specifications for Input Overrange and for Input Span apply additional constraints on the offset
calibration range.
S. For Unipolar mode, Input Span is the difference between full scale and zero scale. For Bipolar mode,
Input Span is the difference between positive and negative full scale points. When using less than
the maximum input span, the span range may be placed anywhere within the range of ±(VREF + 0.1).

Specifications are subject to change without notice.

DS31F2

2-371

----------------------

CS5501/CS5503

DYNAMIC CHARACTERISTICS
Parameter

Symbol

Ratio

Sampling Frequency

fs

ClKIN/256

Output Update Rate

fout

ClKIN /1024

f.3d8

Filter Corner Frequency
Settling Time to

ts

±0.0007% FS (FS Step)

Units

ClKIN /409,600

Hz
Hz
Hz

506,aaO/ClKIN

s

-20
[!l

~ -40
CI)

~

J

-60

'5 -80

~

o

-100'
-120
-140 +----j-----t---j-t-t-H-t-j---j--+-t-+fft-t+--l'--t~~___t_t_rt_t_1
100
1
10
1000
Frequency in Hz

Frequency Response

x
x

jl

S1,2

=-1.4667 ±j1.8199

S3,4

= -1.7559 ±j1.0008

S5,6

= -1.8746 ±jO.32276

x
-0"

-2

·1

x
x

-jl

x

·j2

S-Domain Pole/Zero Plot (Continuous-Time Representation)
H(x) = [1 + O.694x2 + O.241x4 + O.0557x6 + O.OO9664x 8 + O.OO134x lO + 0.000155x12r"2
where x =f/f-3dB, f.3dB =CLKIN/409,600, and f is the frequency of interest.

Continuous-Time Representation of 6-Pole Gaussian Filter

2-372

DS31F2

.-_
._.-.
_
..--__.._-_
...

CS5501/CS5503

DIGITAL CHARACTERISTICS (TA = Tmin to Tmax; VA+, VD+ = 5V ± 10%; VA-,
Parameter

VD- = -5V ± 10%)

Symbol

Min

Typ

Max

Units

Calibration Memory Retention
Power Supply Voltage (VD+ and VA+)

VMR

2.0

-

-

V

-

-

V

-

0.8

V

-

1.5

V

-

V

0.4

V

10

!LA

±10

!LA

9

-

pF

High-level Input Voltage All Except ClKIN

VIH

2.0

High-level Input Voltage ClKIN

VIH

3.5

low-level Input Voltage All Except ClKIN

VIL
VIL

-

VOH

(VD+)-1.0V

VOL

-

Input leakage Current

lin

-

3-State leakage Current

10Z

low-level Input Voltage ClKIN
High-level Output Voltage

(Note 9)

low-level Output Voltage

lout=1.6mA

Digital Output Pin Capacitance
Notes:

Cout

-

V

9. lout = -100!lA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ lout = -40 !LA).

ABSOLUTE MAXIMUM RATINGS
Parameter

DC Power Supplies:

Positive Digital
Negative Digital
Positive Analog
Negative Analog

Input Current, Any Pin Except Supplies (Notes 10, 11)
Analog Input Voltage (AIN and VREF pins)

Symbol

Min

Max

Units

VD+
VDVA+
VA-

-0.3
0.3
-0.3
0.3

(VA+)+0.3
-6.0
6.0
-6.0

V
V
V
V

lin

-

±10

mA

VINA

(VA-)-0.3

(VA+)+0.3

V

(VA+)+0.3

VI NO

-0.3

Ambient Operating Temperature

TA

-55

125

V
Co

Storage Temperature

Tstg

-65

150

Co

Digital Input Voltage

Notes: 10. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.
11. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ± 50 mAo

DS31F2

2-373

-

----------.----._--_.-

CS5501/CS5503

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = OV)
Parameter
DC Power Supplies:

Positive Digital
Negative Digital
Positive Analog
Negative Analog

Analog Reference Voltage
Analog Input Voltage:

Symbol

Min

Typ

Max

Units

VD+
VDVA+
VA-

4.S
-4.S
4.S
-4.S

S.O
-S.O
S.O
-S.O

VA+
-S.S
S.S
-S.S

V
V
V
V

VREF

1.0

2.S

3.0

V

VAIN
VAIN

AGND
-VREF

-

VREF
VREF

V
V

(Note 13)
Unipolar
Bipolar

(Note 12)

Notes: 12. All voltages with respect to ground.
13. The CSSS01 and CSSS03 can accept input voltages up to the analog supplies (VA+ and VA-). They
will accurately convert and filter signals with noise excursions up to 100mV beyond IVREFI.
After filtering, the devices will output all 1's for any input above VREF and all O's for any input below
AGND in unipolar mode and -VREF in bipolar mode.

SWITCHING CHARACTERISTICS (TA = Tmin to Tmax;

ClKIN=4.096 MHz; VA+, VD+ = SV±10%;
VA-, VD- = -SV ± 10%; Input levels: logic 0 = OV, logic 1 = VD+; Cl = SO pF; unless otherwise specified.)
Symbol

Parameter
Master Clock Frequency:

-,

Internal Gate Oscillator
ClKIN
(See Table 1)
Externally Supplied:
(Note 14)
Maximum
ClKIN
Minimum
(Note 1S) ClKIN

ClKIN Duty Cycle
Rise Times:
Fall Times:
Set Up Times:
Hold Time:

Any Digital Input
Any Digital Output

(Note 16)

trise
trise

Any Digital Input
Any Digital Output

(Note 16)

tlall
tlall

SC1, SC2 to CAL low
SLEEP High to ClKIN High (Note 17)
SC1, SC2 hold after CAL falls

Min

Typ

Max

Units

200

4096

SOOO

kHz

-

-

SOOO

200

40

-

kHz
kHz

20

-

80

%

-

1.0

I1s
ns

-

1.0

I1s
ns

-

-

20

-

20

tscs
tsls

100
1

tsch

100

-

-

ns
I1s
ns

Notes: 14. ClKIN must be supplied whenever the CSSS01 or CSSS03 is not in SLEEP mode. If no clock is
present when not in SLEEP mode, the device can draw higher current than specified
and possibly become uncalibrated.
1S. The CSSS01/CSSS03 is production tested at 4.096 MHz. It is guaranteed by characterization
to operate at 200 kHz.
16. Specified using 10% and 90% points on waveform of interest.
17. In order to synchronize several CSSS01's or CSSS03's together using the SLEEP pin,
this specification must be met.

2-374

DS31F2

----------- -----------

CS5501/CS5503

SWITCHING CHARACTERISTICS (continued) (TA = Tmin to T max; VA+, VD+
VA-, VD- = -5V ± 10%; Input Levels: Logic 0 = OV, Logic 1 = VD+; Cl = 50 pF)
Parameter

Symbol

Min

= 5V ± 10%;

Typ

Max

Units

SSC Mode (Mode = VD+)
Access Time

CS Low to SDATA Out

tcsd1

3/CLKIN

-

-

ns

SDATA Delay Time

SCLK Falling to New SDATA bit

tdd1

-

25

100

ns

SClK Delay Time
(at 4.096 MHz)

SDATA MSB bit to SCLK Rising

ted1

250

380

-

ns

Serial Clock
(Out)

Pulse Width High (at 4.096 MHz)
Pulse Width Low

tph1
tpl1

-

240
730

300
790

ns

Output Float Delay

SCLK Rising to Hi-Z

tld2

-

l/CLKIN
+ 100

l/CLKIN
+ 200

ns

Output Float Delay

CS High to Output Hi-Z (Note 18)

tld1

-

-

4/CLKIN
+200

ns

fsclk

dc

MHz

50
180

-

4.2

tph2
tpl2

-

ns

160

ns

-

SEC Mode (Mode = DGND)
Serial Clock (In)
Serial Clock (In)

Pulse Width High
Pulse Width Low

Access Time

CS Low to Data Valid

(Note 19)

tcsd2

-

80

Maximum Data Delay Time

(Note 20)
SCLK Falling to New SDATA bit

tdd2

-

75

150

ns

CS High to Output Hi-Z

tld3

-

-

250

ns

Output Float Delay

100
200
ns
SCLK Falling to Output Hi-Z
Output Float Delay
tld4
Notes: 18. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete
the current data bit and then go to hi.9bJ!:!!pedance.
__
19. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 4 clock cycles. The propagation delay time may be as great as 4 CLKIN cycles plus 160 ns.
To guarantee proper clocking of SDATA when usinJ!ilsychronous CS, SCLK(i) should not be taken
high sooner than 4 CLKIN cycles plus 160ns after CS goes low.
20. SDATA transitions on the falling edge of SCLK(i).

CAL
SC1, SC2

r~1,;;-~
VALID

Calibration Control Timing

DS31F2

ClKIN

SLEEP

--=:p:

Sleep Mode Timing for
Synchronization

CS
SDATA

--tr

Output Float Delay
SSC Mode (Note 19)

2·375

------------.----------

CS5501/CS5503

ClKIN
CS

1=

SDATA

Hi-Z

SClK (0)

Hi-Z

t csd1

tcd1

SSC MODE Timing Relationships

DRDY ~~--~----------------~Irl------------------CS
---1~________________~lrl__~_______ y
tcsd2 j'
t
tld3. ~rSDATA
B01
Hi-Z

·--C=J~~~:d~B2=1=E

SClK (i)

7 JPI,-~~-_-..,--~:'::"L-J-Hi_Z

tph2

CS
SDATA

tcs:j'---

t----------1II-I----------

Hi-Z

--c=j=~~:~:2=1:=E ~SB01 ~ :r-~X~---=l=SB=----t_ Hi-Z

SClK (i)
tph2

SEC MODE Timing Relationships

2-376

DS31F2

----------------------

CS5501/CS5503

SWITCHING CHARACTERISTICS (continued) (TA = Tmin to Tmax;
= 5V± 10%; VA-, VD- = -5V± 10%; Input Levels: Logic 0 = OV, Logic 1 = VD+;

VA+, VD+

Parameter

AC Mode (Mode

CL

= 50 pF)

Symbol

Min

Typ

Max

Units

fselk

dc

-

4.2

MHz

tph3
tpl3

50
180

-

-

ns
ns

tess

-

20

40

ns

90

180

ns

=VD-) CS5501 only

Serial Clock (In)
Serial Clock (In)

Pulse Width High
Pulse Width Low

Set-up Time

CS Low to SCLK Falling

Maximum Data Delay Time SCLK Fall to New SDATA bit

tdd3

-

100
CS High to Output Hi-Z (Note 21)
200
Output Float Delay
ns
tfd5
Notes: 21. If CS is returned high after an ii-bit data packet is started, the SDATA output will continue to output
data until the end of the second stop bit. At that time the SDATA output will go to high impedance.

DRDY

~~----------------~I~I__________~I

CS

SCLK(i)

SDATA

High Byte

Low Byte

AC MODE Timing Relationships (CS5501 only)

DS31F2

..
I

2-377

___-_

.. ...-.
-.-_
..---_._.
GENERAL DESCRIPTION
The CS550l/CS5503 are monolithic CMOS AID
converters designed specifically for high resolution measurement of low-frequency signals. Each
device consists of a charge-balance converter (16Bit for the CS5501, 20-Bit for the CS5503),
calibration microcontroller with on-chip SRAM,
and serial communications port.
The CS5501lCS5503 AID converters perform
conversions continuously and update their output
ports after every conversion (unless the serial port
is active). Conversions are performed and the serial port is updated independent of external
control. Both devices are capable of measuring
either unipolar or bipolar input signals, and calibration cycles may be initiated at any time to
ensure measurement accuracy.
The CS5501lCS5503 perform conversions at a
rate determined by the master clock signal. The
master clock can be set by an external clock or
with a crystal connected to the pins of the on~chip
gate oscillator. The master clock frequency determines:
1. The sample rate of the analog input signal.
2. The comer frequency of the on-chip digital
filter.
3. The output update rate of the serial output port.
The CS5501/CS5503 design includes several selfcalibration modes and several serial port interface
modes to offer users maximum system design
flexiblity.
The Delta-Sigma Conversion Method
The CS550l/CS5503 AID converters use chargebalance techniques to achieve low cost, high
resolution measurements. A charge-balance AID
converter consists of two basic blocks: an analog
modulator and a digital filter. An elementary example of a charge-balance AID converter is a
conventional voltage-to-frequency converter and
counter. The VFC's I-bit output conveys informa2·378

CS5501/CS5503
tion in the form of frequency (or duty cycle),
which is then filtered (averaged) by the counter
for higher resolution.

Figure 1. Charge Balance (Delta·Sigma) AID Converter

The analog modulator of the CS550l/CS5503 is a
multi-order delta-sigma modulator. The modulator
consists of a I-bit AID converter (that is, a comparator) embedded in an analog feedback loop
with high open loop gain (see Figure 1). The
modulator samples and converts the input at a rate
well above the bandwidth of interest. The I-bit
output of the comparator is sampled at intervals
based on the clock rate of the part and this information (either a 1 or 0) is conveyed to the digital
filter. The digital filter is much more sophisticated
than a simple counter. The filter on the chip has a
6-pole low pass Gaussian response which rolls off
at 120 dB/decade (36 dB/octave). The comer frequency of the digital filter scales with the master
clock frequency. In comparison, VFC's and dual
slope converters offer (sin x)/x filtering for high
frequency rejection (see Figure 2 for a comparison
of the characteristics of these two filter types).
When operating from a 1 MHz master clock the
digital filter in the CS5501/CS5503 offers better
than 120 dB rejection of 50 and 60 Hz line frequencies and does not require any type of line
synchronization to achieve this rejection. It should
be noted that the CS5501lCS5503 will update its
output port almost at 1000 times per second when
operating from the 1 MHz clock. This is a much
higher update rate (typically by a factor of at least
50 times) than either VFCs or dual-slope converters can offer.
For a more detailed discussion on the delta-sigma
modulator see the Application note "Delta-Sigma
DS31F2

.._-.-_
._.-.
_
..--__
...

CS5501/CS5503
O~~--------------------------'

-20

iil

iil

::s!. -40

::s!. -40

"'

"'

"0

ClKIN =4 MHz

"0

.'.a~"

.'.a"

Cl

~ -60

:2 -60

: ClKIN = 2 MHz
-80

...... .

-80

-100 '---'-__'---'-__L..........L_ _L.....-'-_ _L.....-'----'

o

20

40
60
Frequency (Hz)

80

a. Averaging (Integrating) Filter Response (tavg

100

ClKIN=1 MHz
-100 +-----..,.......---'-..,.......----..,.......--"-.---t---..............j
o
20
40
60
80
100
Frequency (Hz)

= 100 illS)

b. 6-Pole Gaussian Filter Response

Figure 2. Filter Responses

NO Conversion Technique Overview" in the ap-

plication note section of the data book. The
application note discusses the delta-sigma modulator and some aspects of digital filtering.

OVERVIEW

As shown in the block diagram on the front page
of the data sheet, the CS5501lCS5503 can be segmented into five circuit functions. The heart of the
chip is the charge balance NO converter (l6-bit
for the CS5501, 20-bit for the CS5503). The converter and all of the other circuit functions on the
chip must be driven by a clock signal from the
clock generator. The serial interface logic outputs
the converted data. The calibration microcontroller
along with the calibration SRAM (static RAM),
supervises the device calibration. Each segment of
the chip has control lines associated with it. The
function of each of the pins is described in the pin
description section of the data sheet.

Clock Generator
The CS5501lCS5503 both include gates which
can be connected as a crystal oscillator to provide
the master clock signal for the chip. Alternatively,
an external (CMOS compatible) clock can be input to the CLKIN pin as the master clock for the
device. Figure 3 illustrates a simple model of the
on-chip gate oscillator. The gate has a typical
transconductance of 1500 /-Lmho. The gate model
includes 10 pf capacitors at the input and output
pins. These capacitances include the typical stray
capacitance of the pins of the device. The on-chip
R1 =500kQ

9 = 1500 umho
m

-.~~-j

V C1*

01---~-----1
Y1

C2*7

* See Table 1

Figure 3. On-chip Gate Oscillator Model
DS31F2

2-379

CS5501/CS5503

gate oscillator is designed to properly operate
without additional loading capacitors when using
a 4.096 MHz (or 4 MHz) crystal. If other crystal
frequencies or if ceramic resonators are used,
loading capacitors may be necessary for reliable
operation of the oscillator. Table 1 illustrates some
typical capacitor values to be used with selected
resonating elements.
Resonators

C1

C2

200kHz

330pF

470pF

455kHz

100pF

l00pF

1.0 MHz

50pF

50pF

2.0 MHz

20pF

20pF

30pF

Ceramic

Crystals
2.000 MHz

30pF

3.579 MHz

20pF

20pF

4.096 MHz

None

None

Table 1. Resonator Loading Capacitors

CLKOUT (pin 2) can be used to drive one external CMOS gate for system clock requirements. In
this case, the external gate capacitance must be
taken into account when choosing the value of
C2.
Caution: A clock signal should always be present
whenever the SLEEP is inactive (SLEEP =VD+).
If no clock is provided to the part when not in
SLEEP, the part may draw excess current and
possibly even lose its calibration data. This is because the device is built using dynamic logic.
Serial Interface Logic

The CS5501 serial data output can operate in any
one of the following three different serial interface
modes depending upon the MODE pin selection:
SSC (Synchronous Self-Clocking) mode;
MODE pin tied to VD+ (+5V).
SEC (Synchronous External Clocking) mode;
MODE pin tied to DGND.
2-380

and AC (Asynchronous Communication) mode;
CS55010nly
MODE pin tied to VD- (-5V)
The CS5503 can only operate in the first two
modes, SEC and SSe.
Synchronous Self-Clocking Mode

When operated in the SSC mode (MODE pin tied
to VD+), the CS5501/CS5503 furnish both serial
output data (SDATA) and an internally-generated
serial clock (SCLK). Internal timing for the SSC
mode is illustrated in Figure 4. Figure 5 shows
detailed SSC mode timing for both the
CS550l/CS5503. A filter cycle occurs every 1024
cycles of CLKIN. During each filter cycle, the
status of CS is polled at eight specific times during the cycle. If CS is low when it is polled, the
CS5501/CS5503 begin clocking the data bits out,
MSB first, at a SCLK output rate of CLKIN/4.
Once transmission is complete, DRDY rises and
both SDATA and SCLK outputs go into a high
impedance state. A filter cycle begins each time
DRDY falls. If the CS line is not active, DRDY
will return high 1020 clock cycles after it falls.
Four clock cycles later DRDY will fall to signal
that the serial port has been updated with new
data and that a new filter cycle has begun. The
first CS polling during a filter cycle occurs 76
clock cycles after DRDY falls (the rising edge of
CLKIN on which DRDY falls is considered clock
cycle number one). Subsequent pollings of CS occur at intervals of 128 clock cycles thereafter (76,
204, 332, etc.). The CS signal is polled at the beginning of each of eight data output windows
which occur in a filter cycle. To transmit data during anyone of the eight output windows, CS must
be low at least three CLKIN cycles before it is
polled. If CS does not meet this set-up time, data
will not be transmitted during the window time.
Furthermore, CS is not latched internally and
therefore must be held low during the entire data
transmission to obtain all of the data bits.

DS31F2

----------------------

CS5501/CS5503

~---------- fout=1024/CLKIN
~-------Note1--------------------~
4--- 64/CLKIN
~,~
64/CLKIN------+;

Internal
Status

Analog Time 0

X'

Digital Time 0

Analog Time 1

X

Digital Time1

~ 76/CLKIN-------..:'-_

-I
DRDY (0) .

':

\

)

~t;-

CS Polled

~~-----I~~

CS (i)
CS5501
SCLK (0)

Hi-Z

CS5501
SDATA (0)

Hi-Z

CS5503
SCLK (0)

Hi-Z

..

CS5503
SDATA (0)

Hi-Z

,

Hi-Z

~------\~~Hi-Z

JlIIImIITh
CillIJmmrmjJfD)

Hi-Z
Hi-Z

~~
~r--

Note: 1. There are 16 analog and digital settling periods per filter cycle (4 are shown). Data can be output in the
SSC mode in only 1 of the 8 digital time periods in each filter cycle.

Figure 4. Internal Timing

U1J ... _

ClKIN (i)

1+76 ClKIN cycles-.J

L··· - - - - - - - - - - - - -

=. .

DRDY(o)
CS (i)

--~-----'-------

SDATA(o)
SClK (0)

:::::::W··· :::8i~~:::::::n

~

...

·CS5501
··CS5503

Figure 5. Synchronous Self-Clocking (SSC) Mode Timing

The eighth output window time overlaps the time
in which the serial output port is to be updated. If
the CS is recognized as being low when it is
polled for the eighth window time, data will be
output as normal, but the serial port will not be
updated with new data until the next serial port
update time. Under these conditions, the serial
port will experience an update rate of only 2 kHz
DS31F2

(CLKIN = 4.096 MHz) instead of the normal
4 kHz serial port update rate.
Upon completion of transmission of all the data
bits, the SCLK and SDATA outputs will go to a
high impedance state even with CS held low. In
the event that CS is taken high before all data bits
are output, the SDATA and SCLK outputs will
2-381

----------------------

CS5501/CS5503

complete the current data bit output and go to a
high impedance state when SCLK goes low.

This insures that CS will be recognized and the
MSB bit will become stable before the SCLK
transitions positive to latch the MSB data bit.

Synchronous External Clocking Mode
When operated in the SEC mode (MODE pin tied
to DGND), the CS5501lCS5503 outputs the data
in its serial port at a rate determined by an external clock which is input into the SCLK pin. In
this mode the output port will be updated every
1024 CLKIN cycles. DRDY will go low when
new data is loaded into the output port. If CS is
not active, DRDY will return positive 1020
CLKIN cycles later and remain so for four
CLKIN cycles. If CS is taken low it will be recognized immediately unless it occurs while
DRDY is high for the four clock cycles. As soon
as CS is recognized, the SDATA output will come
out of its high-impedance state and present the
MSB data bit. The MSB data bit will remain present until a falling edge of SCLK occurs to
advance the output to the MSB-l bit. If the CS
and external SCLK are operated asynchronously
to CLKIN, errors can result in the output data unless certain precautions are taken. If CS is
activated asynchronously, it may occur during the
four clock cycles when DRDY is high and therefore not be recognized immediately. To be certain
that data misread errors will not result if CS occurs at this time, the SCLK input should not
transition high to latch the MSB until four
CLKIN cycles plus 160 ns after CS is taken low.
DRDY (0)

~L

When SCLK returns low the serial port will present the MSB-l data bit on its output.
Subsequent cycles of SCLK will advance the data
output. When all data bits are clocked out, DRDY
will then go high and the SDATA output will go
into a high impedance state. If the CS input goes
low and all of the data bits are not clocked out of
the port, filter cycles will continue to occur but
the output serial port will not be updated with
new data (DRDY will remain low). If CS is taken
high at any time, the SDATA output pin will go to
a high impedance state. If any of the data bits in
the serial port have not been clocked out, they
will remain available until DRDY returns high for
four clock cycles. After this DRDY will fall and
the port will be updated with a new 16-bit word
in the CS5501 or 20-bit word in the CS5503. It
is acceptable to clock out less than all possible
data bits if CS is returned high to allow the port
to be updated. Figure 6 illustrates the serial port
timing in the SEC mode.

Asynchronous Communication Mode (CS5501
Only)
In the CS5501, the AC mode is activated when
the MODE pin is tied to VD- (-5 V). When operating in the AC mode the CS5501 is designed to

_ _ _ _ _ __

CS(i)

SCLK(i)

SDATA (0)

i::::8iE#:i:UiH""
• CS5501
•• CS5503

Figure 6. Synchronous External-Clocking (SEC) Mode Timing
2-382

DS31F2

---------------------provide data output in UART compatible format.
The baud rate of the SDATA output will be determined by the rate of the SCLK input. The data
which is output of the SDATA pin will be formatted such that it will contain two 11 bit data
packets. Each packet includes one start bit, eight
data bits, and two stop bits. The packet which carries the most-significant-byte data will be output
first, with its Isb being the first data bit output
after the start bit.
In this mode, DRDY will occur every 1024 clock
cycles. If the serial port is not outputting a data
byte, DRDY will return high after 1020 clock cycles and remain high for 4 clock cycles. DRDY
will then go low to indicate that an update to the
serial output port with a new 16 bit word has occurred. To initiate a transmission from the port the
CS line must be taken low. Then SCLK, which is
an input in this mode, must transition from a high
to a low to latch the state of CS internal to the
CS5501. Once CS is recognized and latched as a
low, the port will begin to output data. Figure 7
details the timing for this output. CS can be returned high before the end of the II-bit
transmission and the transmission will continue
until the second stop bit of the first II-bit packet
is output. The SDATA output will go into a high
impedance state after the second stop bit is output.
To obtain the second II-bit packet CS must again
be brought low before DRDY goes high or the
second II-bit data packet will be overwritten with

SCLK(i)

DRDY(o)

r1JlJlJUL ...

CS5501/CS5503

a serial port update. For the second II-bit packet,
CS need only to go low for 50 ns; it need not be
latched by a falling edge of SCLK. Alternately, . '
the CS line can be taken low and held low u n t i l ,
both II-bit data packets are output. This is the
preferred method of control as it will prevent losing the second II-bit data packet if the port is
updated. Some serial data rates can be quite slow
compared to the rate at which the CS550I can update its output port. A slow data rate will leave
only a short period of time to start the second 11bit packet if CS is returned high momentarily. If
CS is held low continuously (CS hard-wired to
DGND), the serial port will be updated only after
all 22 bits have been clocked out of the port.
Upon the completion of a transmission of the two
II-bit data packets the SDATA output will go into
a high impedance state. If at any time during
transmission the CS is taken back high, the current II-bit data packet will continue to be output.
At the end of the second stop bit of the data
packet, the SDATA output will go into a high impedance state.
Linearity Performance

The CS5501lCS5503 delta-sigma converters are
like conventional charge-balance converters in that
they have no source of nonmonotonicity. The devices therefore have no missing codes in their
transfer functions. See Figure 8 for a plot of the

... ~

l'------___

CS (i) _--'-...._-L-----

SDATA (0) ="",,"=-==-:~~L-=-=--'L-

Figure 7. CS5501 Asynchronous (UART) Mode Timing

DS31F2

2-383

----------- ----------+1

II

I

I

I

I

I

I

I

I

I

CS5501/CS5503
I

I

I

I I

I

I

I I

I

I

I

I

I

I I

I

I

I

I

I

I

I

I

I

I

I

I

I

~~--------------------------

Codes

Figure 8. CS5501 Differential Nonlinearity Plot

excellent differential linearity achieved by the
CS5501. The CS5501lCS5503 also have excellent
integral linearity, which is accomplished with a
well-designed charge-balance architecture. Each
device also achieves low input drift through the
use of chopper-stabilized techniques in its input
stage. To assure that the CS5501lCS5503 achieves
excellent performance over time and temperature,
it uses digital calibration techniques to minimize
offset and gain errors to typically within ±112
LSB at 16 bits in the CS5501 and ±4 LSB at 20
bits in the CS5503.
Converter Calibration

The CS5501lCS5503 offer both self-calibration
and system level calibration capability. To understand the calibration features, a basic
comprehension of the internal workings of the
converter are helpful. As mentioned previously in
this data sheet, the converter consists of two sections. First is the analog modulator which is a
delta-sigma type charge-balance converter. This is
followed by a digital filter. The filter circuitry is
actually an arithmetic logic unit (ALU) whose architecture and instructions execute the filter
function. The modulator (explained in more detail in the applications note "Delta-Sigma
Conversion Technique Overview") uses the VREF
voltage connected to pin 10 to determine the magnitude of the voltages used in its feedback DAC.
The modulator accepts an analog signal at its input and produces a data stream of l's and O's as
its output. This data stream value can change
2-384

(from 1 to 0 or vice versa) every 256 CLKIN cycles. As the input voltage increases the ratio of
l's to O's out of the modulator increases proportionally. The l's density of the data stream out of
the modulator therefore provides a digital representation of the analog input signal where the l's
density is defined as the ratio of the number of l's
to the number of O's out of the modulator for a
given period of time. The l's density output of the
modulator is also a function of the voltage on the
VREF pin. If the voltage on the VREF pin increases in value (say, due to temperature drift), and
the analog input voltage into the modulator remains
constant, the 1's density output of the modulator will
decrease (less l's will occur). The analog input into
the modulator which is necessary to produce a given
binary output code from the converter is ratiometric
to the voltage on the VREF pin. This means that if
VREF increases by one per cent, the analog signal
on AIN must also increase by one per cent to maintain the same binary output code from the converter.
For a complete calibration to occur, the calibration
microcontroller inside the device needs to record
the data stream l's density out of the modulator
for two different input conditions. First, a "zero
scale" point must be presented to the modulator.
Then a "full scale" point must be presented to the
modulator. In unipolar self-cal mode the zero
scale point is AGND and the full scale point is the
voltage on the VREF pin. The calibration microcontroller then remembers the l's density out of
the modulator for each of these points and calculates a slope factor (LSB/~V). This slope factor
DS31F2

-_ _-_

.........
.-..--- ...

CS5501/CS5503

~

represents the gain slope for the input to output
transfer function of the converter. In unipolar
mode the calibration microcontroller determines
the slope factor by dividing the span between the
zero point and the full scale joint by the total
resolution of the converter (2 1 for the CS5501,
resulting in 65,536 segments or 220 for the
CS5503, resulting in 1,048,578 segments). In bipolar mode the calibration microcontroller divides
the span between the zero point and the full scale
point into 524,288 segments for the CS5503 and
32,768 segments for the CS5501. It then extends
the measurement range 524,288 segments for the
CS5503, 32,768 segments for the CS5501, below
the zero scale point to achieve bipolar measurement capability. In either unipolar or bipolar
modes the calculated slope factor is saved and
later used to calculate the binary output code
when an analog signal is present at the AIN pin
during measurement conversions.

Figure 9). System calibration performs the same
slope factor calculations as self-cal but uses voltage values presented by the system to the AIN pin
for the zero scale point and for the full scale
point. Table 2 depicts the calibration modes available. Two system calibration modes are listed.
The first mode offers system level calibration for
system offset and for system gain. This is a
two-step calibration. The zero scale point (system
offset) must be presented to the converter first.
The voltage that represents zero scale point must
be input to the converter before the calibration
step is initiated and must remain stable until the
step is complete. The DRDY output from the
converter will signal when the step is complete by
going low. Mter the zero scale point is calibrated,
the voltage representing the full scale point is input to the converter and the second calibration
step is initiated. Again the voltage must remain
stable throughout the calibration step.

System calibration allows the AID converter to
compensate for system gain and offset errors (see

This two-step calibration mode offers another calibration feature. After a two-step calibration

VREF sys ,-----,
Signal
Conditioning
Circuitry

Analog

Transducer

MUX

CS5501
SClK
CS5503
SDATA
CAL SC1 SC2

AD A1

'--------1

ClK
DATA
~C

I/O 1

'--------11/02
I/O 3
'----------------------11/04
'----------1

'-----------------------1

I/O 5

Figure 9. System Calibration

•

CAL

SC1

SC2

Cal Type

ZSCal

FSCal

Sequence

Calibration Time

~

0

0

Self-Cal

AGND

VREF

One Step

3,145,655/fclk

~

1

1

-

1st Step

1,052,599/fc lk

~

0

1

System Offset
& System Gain

AIN

-

AIN

2nd Step

1,068,813lfclk

~

1

0

System Offset

AIN

VREF

One Step

2,117,389/fclk

DRDY remains high throughout the calibration sequence. In Self-Cal mode (SC1 and SC2 low) DRDY
falls once the CS5501 or CS5503 has settled to the analog input. In all other modes DRDY falls
immediately after the calibration term has been determined.

Table 2. Calibration Control
DS31F2

2-385

. ' ,"

.._-_
_
.-_
..--__
...
.-.-.
sequence (system offset and system gain) has
been properly performed, additional offset calibrations can be performed by themselves to
reposition the gain slope (the slope factor is not
changed) to adjust its zero reference point to the
new system zero reference value.
A second system calibration mode is available
which uses an input voltage for the zero scale
calibration point, but uses the VREF voltage as
the full scale calibration point.
Whenever a system calibration mode is used,
there are limits to the amount of offset and to the
amount of span which can be accommodated.
The range of input span which can be accommodated in either unipolar or bipolar mode is
restricted to not less than 80% of the voltage on
VREF and not more than 200% of (VREF +
0.1) V. The amount of offset which can be calibrated depends upon whether unipolar or bipolar
mode is being used. In unipolar mode the system
calibration modes can handle offsets as positive as
20% of VREF (this is restricted by the minimum
span requirement of 80% VREF) or as negative as
-(VREF + 0.1) V. This capability enables the
unipolar mode of the CS550l/CS5503 to be calibrated to mimic bipolar mode operation.
In the bipolar mode the system offset calibration
range is restricted to a maximum of ±40% of
VREF. It should be noted that the span restrictions
limit the amount of offset which can be calibrated.
The span range of the converter in bipolar mode
extends an equidistance (+ and -) from the voltage
used for the zero scale point. When the zero scale
point is calibrated it must not cause either of the
two endpoints of the bipolar transfer function to
exceed the positive or the negative input overrange points (+(VREF+O.l) V or - (VREF+
0.1) V). If the span range is set to a minimum
(80% VREF) the offset voltage can move ±40%
VREF without causing the end points of the transfer function to exceed the overrange points.
Altematively, if the span range is set to 200% of
2-386

CS5501/CS5503
VREF, the input offset cannot move more than
+0.1 or - 0.1 V before an endpoint of the transfer
function exceeds the input overrange limit.
Initiating Calibration

Table 2 illustrates the calibration modes available
in the CS5501lCS5503. Not shown in the table is
the function of the BP/uP pin which determines
whether the converter is calibrated to measure bipolar or unipolar signals. A calibration step is
initiated by bringing the CAL pin (l3) high for at
least 4 CLKIN cycles to reset the part and then
bringing CAL low. The states of SCI (pin 4) and
SC2 (pin 17) along with the BP/uP (pin 12) will
determine the type of calibration to be performed.
The SCI and SC2 inputs are latched when CAL
goes low. The BP/uP input is not latched and
therefore must remain in a fixed state throughout
the calibration and measurement cycles. Any time
the state of the BP/uP pin is changed, a new calibration cycle must be performed to enable the
CS5501lCS5503 to properly function in the new
mode.
When a calibration step is initiated, the DRDY
signal will go high and remain high until the step
is finished. Table 2 illustrates the number of
clock cycles each calibration requires. Once a
calibration step is initiated it must finish before a
new calibration step can be executed. In the two
step system calibration mode, the offset calibration step must be initiated before initiating the
gain calibration step.
When a self-cal is completed DRDY falls and the
output port is updated with a data word that represents the analog input signal at the AIN pin.
When a system calibration step is completed,
DRDY will fall and the output port will be updated with the appropriate data value (zero scale
point, or full scale point). In the system calibration mode, the digital filter must settle before the
output code will represent the value of the analog
input signal.
DS31F2

----------- -----------

CS5501/CS5503
1LSB

Cal Mode

Zero Scale

Gain Factor

Unipolar

Bipolar

CS5501

CS5503

CS5501

CS5503

VREF
1,048,526

2VREF
65,536

2VREF
1,048,526

SGAIN-SOFF
1,048,526

2(SGAIN-SOFF)
65,536

2(SGAIN-SOFF)
1,048,526

Self-Cal

AGND

VREF

VREF
65,536

System Cal

SOFF

SGAIN

SGAIN-SOFF
65,536

Table 3. Output Code Size After Calibration
Input Voltage, Unipolar Mode

Input Voltage, Bipolar Mode
Output Codes (Hex)

System-Cal

Self-Cal

CS5501

>(SGAIN - 1.5 LSB)

>(VREF • 1.5 LSB)
VREF - 1.5 LSB

SGAIN - 1.5 LSB

{SGAIN - SOFF)12 - 0.5 LSB VREF/2 - 0.5 LSB

CS5503

Self-Cal

System Cal

FFFF

FFFFF

>(VREF • 1.5 LSB)

>(SGAIN - 1.5 LSB)

FFFF
FFFE

FFFFF
FFFFE

VREF - 1.5 LSB

SGAIN - 1.5 LSB

8000
7FFF

80000
7FFFF

AGND - 0.5 LSB

SOFF -0.5 LSB

00001
00000

-VREF+ 0.5 LSB

-SGAIN + 2S0FF + 0.5 LSB

00000

<(-VREF+0.5 LSB)

<(-SGAIN+2S0FF+0.5 LSB)

SOFF + 0.5 LSB

AGND + 0.5 LSB

0001
0000

<(SOFF + 0.5 LSB)

<(AGND+0.5 LSB)

0000

Table 4. Output Coding

Tables 3 and 4 indicate the output code size and
output coding of the CS5501/CS5503 in its various modes. The calibration equations which
represent the CS550l/CS5503 transfer function
are shown in Figure 10.

DOUT = Slope (AIN - Unipolar Offset) + 0.5 LSB
a. Unipolar Calibration

CS5501
DOUT = Slope (AIN - Bipolar Offset) + 2 15 + 0.5 LSB16
CS5503
DOUT = Slope(AIN - Bipolar Offset) + 2 19 + 0.5 LSB20
b. Bipolar Calibration

Figure 10. Calibration Equations

DS31F2

Underrange And Overrange Considerations

The input signal range of the CS5501lCS5503
will be determined by the mode in which the part
is calibrated. Table 4 indicates the input signal
range in the various modes of operation. If the
input signal exceeds the full scale point the converter will output all ones. If the signal is less
than the zero scale point (in unipolar) or more
negative in magnitude than minus the full scale
point (in bipolar) it will output all zeroes.
Note that the modulator-filter combination in the
chip CS5501lCS5503 is designed to accurately
convert and filter input signals with noise excursions which extend up to 100 mV below the
analog value which produces all zeros out or
above the analog value which produces all ones
out. Overrange noise excursions greater than
100 mVmay increase output noise.
All pins of the CS5501lCS5503 include diodes
which clamp the input signals to within the positive and negative supplies. If a signal on any pin
(including AIN) exceeds the supply voltage (either
2-387

----------------------

CS5501/CS5503

+ or -) a clamp diode will be forward-biased. Under these fault conditions the CS5501lCS5503
might be damaged. Under normal operating conditions (with the power supplies established), the
device will survive transient currents through the
clamp diodes up to 100 rnA and continuous currents up to lOrnA. The drive current into the AIN
pin should be limited to a safe value if an overvoltage condition is likely to occur. See the
application note "Buffer Amplifiers for the
CS501X Series of AID Converters" for further
discussion on the clamp diode input structure and
on current limiting circuits.

System Synchronization
If more than one CS5501lCS5503 is included in a

system which is operating from a common clock,
all of the devices can be synchronized to sample
and output at exactly the same time. This can be
accomplished in either of two ways. First, a single
CAL signal can be issued to all the
CS5501/CS5503's in the system. To insure synchronization on the same clock signal the CAL
signal should go low on the falling edge of
CLKIN. Or second, a common SLEEP control
signal can be issued. If the SLEEP signal goes
positive with the appropriate set up time to
CLKIN, all parts will be synchronized on the
same clock cycle.

Analog Input Impedance Considerations
The analog input of the CS5501lCS5503 can be
modeled as illustrated in Figure 11. A 20 pF capacitor is used to dynamically sample the input
signal. Every 64 CLKIN cycles the switch alternately connects the capacitor to. the output of the
buffer and then directly to the AIN pin. Whenever the sample capacitor is switched from the
output of the buffer to the AIN pin, a small packet
of charge (a dynamic demand of current) will be
required from the input source to settle the voltage
on the sample capacitor to its final value. The
voltage at the output of the buffer may differ up to
100 mV from the actual input voltage due to the
2·388

AIN

G'------.J
VosS;100 mv
AGND~------------~-

Figure 11. Analog Input Model

offset voltage of the buffer. Timing allows 64 cycles of master clock (CLKIN) for the voltage on
the sample capacitor to settle to its final value.
The equation which defines settling time is:

Where Ve is the final settled value, Vmax is the
maximum error voltage value of the input signal,
R is the value of the input source resistance, C is
the 20 pF sample capacitor plus the value of any
stray or additional capacitance at the input pin.
The value of t is equal to 64/CLKIN.
Vmax occurs the instance when the sample capacitor is switched from the buffer output to the AIN
pin. Prior to the switch, AIN has an error estimated as being less than or equal to Ve. Vmax is
equal to the prior error (Ve) plus the additional
error from the buffer offset. The estimate for Vmax
is:
Vrnax =Ve+lOOmV__...:2=.:0p=F__
(2OpF+CEXT)

Where CEXT is the combination of any external or
stray capacitance.
From the equation which defines settling time, an
equation for the maximum acceptable source resistance is derived

DS31F2

----------------------

CS5501/CS5503

equation which defines settling time, an equation
for the maximum acceptable source resistance is
derived
Rs max =

-64
CLKIN(2OpF+CEXf) In [

Ve
Ve + 20pF(100mv)
(20pF+CmIT)

This equation assumes that the offset voltage of
the buffer is 100 m V, which is the worst case.
The value of Ve is the maximum error voltage
which is acceptable.
For a maximum error voltage (Ve) of 10 J!V in
the CS5501 (1I4LSB at 16-bits) and 600 nV in
the CS5503 (1/4LSB at 20-bits), the above equation indicates that when operating from a
4.096 MHz CLKIN, source resistances up to
84 ill in the CS5501 or 64 ill in the CS5503 are
acceptable in the absence of external capacitance
(CEXT
0). If higher input source resistances
are desired the master clock rate can be reduced
to yield a longer settling time for the 64 cycle period.

=

10
5

160
. . '- - - '- - - '- - - '- - -' - - -' - . -' - - , - -

80
ID

~

~

.5 0

o

~ -5

-80

~

-160

~

~

i

~

-10

,

,

,

- - - - - - - - - - - - -

-

~
() -15
-20
-55

.5

~

t

~

1

Gain drift within the converter depends predominately upon the temperature tracking of internal
capacitors. Gain drift is not affected by leakage
currents, therefore gain drift is significantly less
than comparable offset errors due to temperature
increases. The typical gain drift over the specified
temperature range is less than 2.5 LSBs for the
CS5501 and less than 40 LSBs for the CS5503 .

-240 ()

-35

-15

5
25
45
65
85
Temperature in De9. C.

105

-320
125

Figure 12. Typical Self-Cal Bipolar Offset vs. Temperature After Calibration at 2S °C

Analog Input Drift Considerations
The CS5501lCS5503 analog input uses chopperstabilization techniques to minimize input offset
DS31F2

drift. Charge injection in the analog switches and
leakage currents at the sampling node are the primary sources of offset voltage drift in the
converter. Figure 12 indicates the typical offset
drift due to temperature changes experienced after
calibration at 25°C. Drift is relatively flat up to
about 75°C. Above 75 °C leakage current becomes the dominant source of offset drift.
Leakage currents approximately double with each
10 °C of temperature increase. Therefore the offset drift due to leakage current increases as the
temperature increases. The value of the voltage on
the sample capacitor is updated at a rate determined by the master clock, therefore the amount
of offset drift which occurs will be proportional to
the elapsed time between samples. In conclusion,
the offset drift increases with temperature and is
inversely proportional to the CLKIN rate. To
minimize offset drift with increased temperature,
higher CLKIN rates are desirable. At temperatures
above 100°C, a CLKIN rate above 1 MHz is recommended. The effects of offset drift due to
temperature changes can be eliminated by recalibrating the CS5501lCS5503 whenever the
temperature has changed.

Measurement errors due to offset drift or gain
drift can be eliminated at any time by recalibrating the converter. Using the system calibration
mode can also minimize offset and gain errors in
the signal conditioning circuitry.
The
CS5501/CS5503 can be recalibrated at any temperature to remove the effects of these errors.
Linearity and differential non linearity are not significantly affected by temperature changes.
2-389

•

._.-.
_.-_....,-__.._-_
...

CS5501/CS5503

Filtering

At the system level, the digital filter in the
CS550 l/CS5503 can be modeled exactly like an
analog filter with a few minor differences. Digital filtering resides behind the AID conversion
and can thus reject noise injected during the
conversion process (i.e. power supply ripple,
voltage reference noise, or noise in the ADC itself). Analog filtering cannot.
Also, since digital filtering resides behind the
AID converter, noise riding unfiltered on a
near-full-scale input could potentially overrange the ADC. In contrast, analog filtering
removes the noise before it ever reaches the
converter. To address this issue, the
CS550l/CS5503 each contain an analog modulator and digital filter which reserve headroom
such that the device can process signals with
100mV "excursions" above full-scale and still
output accurately converted and filtered data.
Filtered input signals above full-scale still result
in an output of all ones.
The digital filter's corner frequency occurs at
CLKIN/409,600, where CLKIN is the master
clock frequency. With a 4.096MHz clock, the
1.1

I

I

I

0.9

~0.7
0.6

/

.~0.5

~

/V

/

1.0000100

?

1.0000075

See (b) for
expanded view

/

0.3

/

0.2
0.1

~

Cl

.s

irn 0.9999975

/

o

50

100

I

Vertical scale normalized

~

I

to input jtep sl,e

-

"I'-- ~
\ 0.99999850

'-..

0.9999950
0.9999925

-

r--- Settling response Is monotonica:r r--f- increasing from zero to here, an

0.9999900

-

then exhibits one overshoot and
f- oni UnderShoot is shoin.

I

r---

0.9999875
150

200

250

300

350

400

450

Filter Cycles (1024 ClKIN cycles)

(a) Settling Time Due to Input Step Change

2-390

( ~

1.0000025

~ 1.0000000

./

0.0

/,1.00000381

1;' 1.0000050

I

0.4

The digital filter (rather than the analog modulator) dominates the converters' settling for
step-function inputs. Figure 13 illustrates the settling characteristics of the filter. The vertical axis
is normalized to the input step size. The horizontal axis is in filter cycles. With a full scale input
step (2.5 V in unipolar mode) the output will exhibit an overshoot of about 0.25 LSB16 in the
CS5501 and 4 LSB20 in the CS5503.

1.0000125

/.

0.8

~

Both 'the CS5501/CS5503 employ internal digi~
tal filtering which creates a 6-pole Gaussian
relationship. With the corner frequency set at
10Hz for minimized settling time, the
CS5501lCS5503 offer approximately 55dB rejection at 60Hz to signals coming into either
the AIN or VREF pins. With a 5Hz cut-off,
60Hz rejection increases to more than 90dB.

I

Vertical scale normalized
to Inpl t step Ize

1.0

filter corner is at 10Hz and the output register is
updated at a 4kHz rate. CLKIN frequency can be
reduced with a proportional reduction in the filter
comer frequency and in the update rate to the output register. A plot of the filter response is shown
in the specification tables section of this data
sheet.

500

500

530

560

590

620

650

6BO

710

740

Filter Cycles (1024 ClKIN cycles)

(b) Expanded Version of (a)

DS31F2

_.-_..--_._.
__..--_
...-.

CS5501/CS5503

Anti-Alias Considerations

Post Filtering

The digital filter in the CS5501lCS5503 does not
provide rejection around integer multiples of the
oversampling rate [(N*CLKIN)/256, where
N = 1,2,3, ... ]. That is, with a 4.096 MHz master
clock the noise on the analog input signal within
the narrow ±1O Hz bands around the 16 kHz,
32 kHz, 48 kHz, etc., passes unfiltered to the digital output. Most broadband noise will be very
well filtered because the CS5501lCS5503 use a
very high oversampling ratio of 800 (16 kHz:
2x10 Hz). Broadband noise is reduced by:

Post filtering is useful to enhance the noise performance of the CS5503. With a constant input
voltage the output codes from the CS5503 will
exhibit some variation due to noise. The CS5503
has typically 1.6 LSB20 rms noise in its output
codes. Additional variation in the output codes
can arise due to noise from the input signal source
and from the voltage reference. Post filtering
(digital averaging) will be necessary to achieve
less than 1 LSB p-p noise at the 20-bit level. The
CS5503 has peak noise less than the 18-bit level
without additional filtering if care is exercised in
the design of the voltage reference and the input
signal condition circuitry. Noise in the bandwidth
from dc to 10 Hz on both the AIN and VREF
inputs should be minimized to ensure maximum
performance. As the amount of noise will be
highly system dependent, a specific recommendation for post filtering for all applications cannot be
stated. The following guidelines are helpful. Realize that the digital filter in the CS5503, like any
other low pass filter, acts as an information storage unit. The filter retains past information for a
period of time even after the input signal has
changed. The implication of this is that immediately sequential 20-bit updates to the serial port
contain highly correlated information. To most efficiently post filter the CS5503 output data,
uncorrelated samples should be used. Samples
which have sufficiently reduced correlation can be
obtained if the CS5503 is allowed to execute 200
filter cycles between each subsequent data word
collected for post filtering.

eout

=ein --12f-3dBlfs

eout = 0.035 ein

where !!in and eOn! are rms noise terms referred to
the input. Since f3dB equals CLKIN/409,600 and
fs equals CLKINI256, the digital filter reduces
white, broadband noise by 96.5% independent of
the CLKIN frequency. For example, a typical operational amplifier's 50llV rms noise would be
reduced to 1.751lV rms (0.035 LSB's rms at the
16-bit level in the CS5501 and 0.4 LSB's rms at
the 20-bit level in the CS5503).
Simple high frequency analog filtering in the signal conditioning circuitry can aid in removing
energy at multiples of the sampling rate.
Bits of
Output
Accuracy

Filter
Cycles

ClKIN
Cycles

9
10
11
12
13
14
15
16
17
18
19
20

340
356
389
435
459
475
486
495
500
504
506
507

348,160
364,544
398,336
445,440
470,016
486,400
497,664
506,880
512,000
516,096
518,144
519,168

Table 5. Settling Time of the 6 Pole Low Pass Filter in
the CS5501 to 112 LSB Accuracy with a Full Scale
Step Input
DS31F2

The character of the noise in the data will influence the post filtering requirements. As a general
rule, averaging N uncorrelated data samples will
reduce noise by 1I...JN. While this rule assumes
that the noise is white (which is true for the
CS5503 but not true for all real system signals
between dc and 10Hz), it does offer a starting
point for developing a post filtering algorithm for
removing the noise from the data. The algorithm
2-391

Ell

.

.

-_ _-_

..
.
.-..--_._.
_- ...will have to be empirically tested to see if it meets
the system requirements. It is recommended that
any testing include input signals across the entire
input span of the converter as the signal level will
affect the amount of noise from the reference input which is transferred to the output data.

CS5501/CS5503

band-gap references are available which can supply 2.5 V for use with the CS550l/CS5503.
Many of these devices are not specified for noise,
especially in the 0.1 to 10 Hz bandwidth. Some
of these devices may exhibit noise characteristics
which degrade the performance of the
CS5501lCS5503.

Voltage Reference
Power Supplies And Grounding
The voltage reference applied to the VREF input
pin defines the analog input range of the
CS5501lCS5503. The preferred reference is 2.5V,
but the device can typically accept references
from IV to 3V. Input signals which exceed 2.6V
(+ or -) can cause some linearity degradation. Figure 14 illustrates the voltage reference connections
to the CS5501lCS5503.
CS5501
CS5503
+5V --lI>-----+!VA+
For Example

LT1019 -2.5

~-=-----'-->oJVREF

t------1AGND

Figure 14. Voltage Reference Connections

The circuitry inside the VREF pin is identical to
that as seen at the AIN pin. The sample capacitor
(see Figure 12) requires packets of charge from
the extemal reference just as the AIN pin does.
Therefore the same settling time requirements apply. Most reference IC's can handle this dynamic
load requirement without inducing errors. They
exhibit sufficiently low output impedance and
wide enough bandwidth to settle to within the
necessary accuracy in the requisite 64 CLKIN cycles.
Noise from the reference is filtered by the digital
filter, but the reference should be chosen to minimize noise below 10 Hz. The CS5501/CS5503
typically exhibit 0.1 LSB rms and 1.6 LSB rms
noise respectively. This specification assumes a
clean reference voltage. Many monolithic
2-392

The CS5501/CS5503 use the analog ground connection, AGND, as a measurement reference node.
It carries no power supply current. The AGND
pin should be used as the reference node for both
the analog input signal and for the reference voltage which is input into the VREF pin.
The analog and digital supply inputs are pinned
out separately to minimize coupling between the
analog and digital sections of the chip. To
achieve maximum performance, all four supplies
for the CS5501lCS5503 should be decoupled to
their respective grounds using 0.1 JlF capacitors.
This is illustrated in the System Connection Diagram, Figure 15, at the beginning of this data
sheet.
As CMOS devices, the CS5501lCS5503 require
that the positive analog supply voltage always be
greater than or equal to the positive digital supply
voltage. If the voltage on the positive digital supply should ever become greater than the voltage
on the positive analog supply, diode junctions in
the CMOS structure which are normally reversebiased will become forward-biased. This may
cause the part to draw high currents and experience permanent damage. The connections shown
in Figure 15 eliminate this possibility.
To ensure reliable operation, be certain that power
is applied to the part before signals at AIN, VREF,
or the logic input pins are present. If current is
supplied into any pin before the chip is poweredup, latch-up may result. As a system, it is
desirable to power the CS5501lCS5503, the voltDS31F2

...-..
_.-_....__.._-_
...

CS5501/CS5503

10n

0.1~~

+5V
Analog
Supply

~

VA+
13
4

Calibration
Control

17

An alog
Si gnal
Source

0 - VREF
or

Bipolar!
Unipolar
Input Select

5V
An alog
Su pply

9

0.0047~O
~

±VR EF

+5V
An alog
Su pply

12

200n*

Voltage
Reference

+2.5V

0.1

CAL

ClKIN

SCl

ClKOUT

SC2

SLEEP
CS5501
CS5503

BP/uP

~F

_L-

T

MODE
SClK

AIN

SDATA
DRDY

10
VREF

CS
AGND

~

VA17 10n

• Recommended to
reduce high
frequency noise

--::::r::-

VD+

8

1

-

0.1~~
)15

114

DGND
VD-

r

3
--:L--

~

Optional
Clock
Source

11

Sleep Mode
Control

1

Output
Mode Select

19
Serial
Data
Interface

20
18

Control
logic

16
5

0.1~~

T

1

Unused logic Inputs
must be connected
toO GND orVD+

l
Figure 15. Typical Connection Diagram

age reference, and the analog signal conditioning
circuitry from the same primary source. If separate supplies are used, it is recommended that the
CS5501/CS5503 be powered up first. If a common power source is used for the analog signal
conditioning circuitry as well as the AID converter, this power source should be applied before
application of power to the digital logic supply.
The CS5501lCS5503 exhibit good power supply
rejection for frequencies within the passband (dc
to 10 Hz). Any small offset or gain error caused
by long term drift of the power supplies can be
removed by recalibration. Above 10 Hz the digiDS31F2

tal filter will provide additional rejection. When
the benefits of the digital filter are added to the
regular power supply rejection the effects of line
frequency variations (60 Hz) on the power supplies will be reduced greater than 120 dB. If the
supply voltages for the CS5501/CS5503 are generated with a dc-dc converter the operating
frequency of the dc-dc converter should not operate at the sampling frequency of the
CS5501/CS5503 or at integer multiples thereof.
At these frequencies the digital filter will not aid
in power supply rejection. See Anti-Alias Considerations section of this data sheet.

2-393

,

-___

.._--. ..-_._.
...-.

CS5501/CS5503

The recommended system connection diagram for
the CS5501/CS5503 is illustrated in Figure 15.
Note that any digital logic inputs which are to be
unused should be tied to either DGND or the
VD+ as appropriate. They should not be left floating; nor should they be tied to some other logic
supply voltage in the system.
Power-Up and Initialization

Upon power-up, a calibration cycle must be initiated at the CAL pin to insure a consistent starting
condition and to initially calibrate the device. The
CAL pin must be strobed high for a minimum of
4 clock cycles. The falling edge will initiate a
calibration cycle. A simple power-on reset circuit
can be built using a resistor and capacitor (see
Figure 16). The resistor and capacitor values
should allow for clock or oscillator startup time,
and the voltage reference stabilization time.

reading will occur after a rising edge on SLEEP
occurs.
Battery Backed-Up Calibrations

The CS5501/CS5503 use SRAM to store calibration information. The contents of the SRAM will
be lost whenever power is removed from the chip.
Figure 17 shows a battery back-up scheme that
can be used to retain the calibration memory during system down time and/or protect it against
intermittent power loss. Note that upon loss of
power, the SLEEP input goes low, reducing power
consumption to just 10 1lW. Lithium cells of 3.6
V are available which average 1750 rnA-hours before they drop below the typical 2 V
memory-retention specification of the
CS550l/CS5503.

+5V

CS5501
CAL

R

SC2
t--------'- SC1

Figure 16. Power-On Reset Circuitry
(Self-Calibration Only)

Due to the devices' low power dissipation and low
temperature drift, no warm-up time is required to
accommodate any self-heating effects.
Sleep Mode

The CS5501lCS5503 include a sleep mode
(SLEEP = DGND) which shuts down the internal
analog and digital circuitry reducing power consumption to less than 10 IlW. All calibration
coefficients are retained in memory such that no
time is required after "awakening" for recalibration. Still, the CS550l/CS5503 will require time
for the digital filter to settle before an accurate
2-394

Figure 17. Example Calibration Memory Battery
Back-Up Circuit

When SLEEP is active (SLEEP = DGND), both
VD+ and VA+ must remain powered to no less
than 2 V to retain calibration memory. The VDand VA- voltages can be reduced to 0 V but must
not be allowed to go above ground potential. The
negative supply must exhibit low source impedance in the powered-down state as the current into
the VA+ pin flows out the VA- pin. (AGND is
only a reference node. No power supply current
flows in or out of AGND.) Care should be taken
DS31F2

----------------------

CS5501/CS5503

to ensure that logic inputs are maintained at either
VD+ ar DGND potential when SLEEP is low.
Note that battery life could be shortened if the
+5 V supply drops slowly during power-down. As
the supply drops below the battery voltage but not
yet below the logic threshold of the SLEEP pin,
the battery will be supplying the CS5501lCS5503
at full power (typically 3 rnA). Faster transitions
at SLEEP can be triggered using a resistive divider or a simple resistor network to generate the
SLEEP input from the +5 V supply.

Schematic &Layout Review Service
Confirm Optimum
Schematic &Layout
Before Building Your

Output Loading Considerations
To maximize performance of the CS5501/
CS5503, the output drive currents from the digital
output lines should be minimized. It is recommended that CMOS logic gates (4000B, 74HC,
etc.) be used to provide minimum loading. If it is
necessary to drive an opto-isolator the outputs of
the CS5501/CS5503 should be buffered. An easy
means of driving the LED of an opto-isolator is to
use a 2N7000 or 2N7002 low cost FET.

DS31F2

2-395

-

--.J.".

_.-_..--__.._-_
....
...-..

CS5501/CS5503

PIN DESCRIPTIONS
SERIAL INTERFACE MODE SELECT
CLOCK OUT
CLOCK IN
SYSTEM CALIBRATION 1
DIGITAL GROUND
NEGATIVE DIGITAL POWER
NEGATIVE ANALOG POWER
ANALOG GROUND
ANALOG IN
VOLTAGE REFERENOE

MODE
CLKOUT
CLKIN
SC1
DGND
VDVAAGND
AIN
VREF

1- '-" 20
2

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

SDATA
·SCLK
DRDY
SC2
CS
VD+
VA+
CAL
BP/uP
SLEEP

SERIAL DATA OUTPUT
SERIAL CLOCK INPUT/OUTPUT
DATA READY
SYSTEM CALIBRATION 2
CHIP SELECT
POSITIVE DIGITAL POWER
POSITIVE ANALOG POWER
CALIBRATE
BIPOLAR/UNIPOLAR SELECT
SLEEP

* Pinout applies to both DIP and SOlC packages
Clock Generator

CLKIN; CLKOUT -Clock In; Clock Out, Pins 3 and 2.
A gate inside the CS5501lCS5503 is connected to these pins and can be used with a crystal or
ceramic resonator to provide the master clock for the device. Alternatively, an external (CMOS
compatible) clock can be input to the CLKIN pin as the master clock for the device. When not
in SLEEP mode, a master clock (CLKIN) should be present at all times.
Serial Output I/O

MODE -Serial Interface Mode Select, Pin 1.
Selects the operating mode of the serial port. If tied to VD- (-5V), the CS550l will operate in
the DART-compatible AC mode for Asynchronous Communication. The SCLK pin will operate
as an input to set the data rate, and data will transmit formatted with one start and two stop bits.
If MODE is tied to DGND, the CS5501lCS5503 will operate in the SEC (Synchronous
External-Clocking) mode, with the SCLK pin operating as an input and the output appearing
MSB-first. If MODE is tied to VD+ (+5V), the CS5501lCS5503 will operate in its SSC
(Synchronous Self-Clocking) mode, with SCLK providing a serial clock output of CLKIN/4
(25% duty-cycle).
DRDY -Data Ready, Pin 18.
DRDY goes low every 1024 cycles of CLKIN to indicate that new data has been placed in the
output port. DRDY goes high when all the serial port data is clocked out, when the serial port is
being updated with new data, when a calibration is in progress, or when SLEEP is low.
CS -Chip Select, Pin 16.
An input which can be enabled by an external device to gain control over the serial port of the
CS5501lCS5503.

2-396

DS31F2

_.-_..--__.._-_
...
._.-.

CS5501/CS5503

SDATA -Serial Data Output, Pin 20.
Data from the serial port will be output from this pin at a rate determined by SCLK and in a
format determined by the MODE pin. It furnishes a high impedance output state when not
transmitting data.
SCLK -Serial Clock Input/Output, Pin 19.
A clock signal at this pin determines the output rate of the data from the SDATA pin. The
MODE pin determines whether the SCLK signal is an input or output. SCLK may provide a
high impedance output when data is not being output from the SDATA pin.
Calibration Control Inputs

SCI; SC2 -System Calibration 1 and 2, Pins 4 and 17.
Control inputs to the CS550l/CS5503's calibration microcontroller for calibration. The state of
SCI and SC2 determine which of the calibration modes is selected for operation (see Table 2).
BP/uP -Bipolar/unipolar Select, Pin 12.
Determines whether the CS550I/CS5503 will be calibrated to measure bipolar (BP/uP = VD+)
or ~olar (BP/uP = DGND) input signals. Recalibration is necessary whenever the state of
BP/uP is changed.
CAL -Calibrate, Pin 13.
If brought high for 4 clock cycles or more, the CS5501lCS5503 will reset and upon returning
Iowa full calibration cycle will begin. The state of SCI, SC2, and BP/uP when CAL is brought
low determines the type and length of calibration cycle initiated (see Table 2). Also, a single
CAL signal can be used to strobe the CAL pins high on several CS5501lCS5503's to
synchronize their operation. Any spurious glitch on this pin may inadvertently place the chip in
Calibration mode.
Other Control Input

SLEEP -Sleep, Pin 11.
When brought low, the CS5501lCS5503 will enter a low-power state. When brought high again,
the CS5501lCS5503 will resume operation without the need to recalibrate. Mter SLEEP goes
high again, the device's output will settle to within +0.0007% of the analog input value within
1.3/f-3dB, where f-3dB is the passband frequency. The SLEEP input can also be used to
synchronize sampling and the output updates of several CS550l/CS5503's.
Analog Inputs

VREF -Voltage Reference, Pin 10.
Analog reference voltage input.
AIN -Analog Input, Pin 9.

DS31F2

2-397

------------ ...---------

CS5501/CS5503

Power Supply Connections

VD+ ·Positive Digital Power, Pin 15.
Positive digital supply voltage. Nominally +5 volts.
VD· ·Negative Digital Power, Pin 6.
Negative digital supply voltage. Nominally -5 volts.
DGND ·Digital Ground, Pin 5.
Digital ground.
VA+ ·Positive Analog Power, Pin 14.
Positive analog supply voltage. Nominally +5 volts.
VA· ·Negative Analog Power, Pin 7.
Negative analog supply voltage. Nominally -5 volts.
AGND ·Analog Ground, Pin 8.
Analog ground.

2·398

DS31F2

----------------------

CS5501/CS5503

SPECIFICATION DEFINITIONS
Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the AID
Converter transfer function. One endpoint is located 112 LSB below the first code transition
and the other endpoint is located I12 LSB beyond the code transition to all ones. Units in
percent of full-scale.
Differential Linearity
The deviation of a code's width from the ideal width. Units in LSB's.
Full-Scale Error
The deviation of the last code transition from the ideal (VREF-3/2 LSB's). Units in LSBs.
Unipolar Offset
The deviation of the first code transition from the ideal (112 LSB above AGND) when in
unipolar mode (BP/uP low). Units in LSBs.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100... 000) from the ideal (112 LSB below
AGND) when in bipolar mode (BP/uP high). Units in LSBs.
Bipolar Negative Full-Scale Error
The deviation of the first code transition from the ideal when in bipolar mode (BP/uP high).
The Ideal is defined as lying on a straight line which passes through the final and mid-scale
code transitions. Units in LSBs.
Positive Full-Scale Input Overrange
The absolute maximum positive voltage allowed for either accurate system calibration or
accurate conversions. Units in volts.
Negative Full-Scale Input Overrange
The absolute maximum negative voltage allowed for either accurate system calibration or
accurate conversions. Units in volts.
Offset Calibration Range
The CS5501lCS5503 calibrate their offset to the voltage applied to the AIN pin when in system
calibration mode. The first code transition defines Unipolar Offset when BP/uP is low and the
mid-scale transition defines Bipolar Offset when BP/uP is high. The Offset Calibration Range
specification indicates the range of voltages applied to AIN that the CS5501 or CS5503 can
accept and still calibrate offset accurately. Units in volts.
Input Span
The voltages applied to the AIN pin in system-calibration schemes define the CS5501lCS5503
analog input range. The Input Span specification indicates the minimum and maximum input
spans from zero-scale to full-scale in unipolar, or from positive full scale to negative full scale
in bipolar, that the CS5501/CS5503 can accept and still calibrate gain accurately. Units in
volts.
DS31F2

2-399

. '
.

_.-_..--_.-.
__.._-_
....-.

CS5501/CS5503

Ordering Guide
Model Number
CS5501-AS
CS5501-BS
CS5501-AP
CS5501-BP
CS5501-CP
CS5501-SD
CS5501-TO

CS5503-AS
CS5503-BS
CS5503-AP
CS5503-BP
CS5503-CP
CS5503-SD
CS5503-TD

2-400

No. of Bits
16
16
16
16
16
16
16

20
20
20
20
20
20
20

Linearity Error (Max)
0.003%
0.0015%
0.003%
0.0015%
0.0012%
0.003%
0.0015%

0.003%
0.0015%
0.003%
0.0015%
0.0012%
0.003%
0.0015%

Temperature Range
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-55 to +125°C
-55 to +125°C

20
20
20
20
20
20
20

Package
Lead SOIC
Lead SOIC
Pin Plastic DIP
Pin Plastic DIP
Pin Plastic DIP
Pin Cerdip
Pin Cerdip

-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-55 to + 125°C
-55 to + 125°C

20
20
20
20
20
20
20

Lead SOIC
Lead SOIC
Pin Plastic DIP
Pin Plastic DIP
Pin Plastic DIP
Pin Cerdip
Pin Cerdip

DS31F2

.-_
._.-.
_
..--__.._-...

CS5501/CS5503

APPENDIX A: APPLICATIONS

turns high as the last bit shifts out. Therefore, the
DRDY pin can be polled for a rising transition
directly, or it can be latched as a level-sensitive
interrupt.

Parallel Interface

Figures Al and A2 show two serial-to-parallel
conversion circuits for interfacing the CS5501 in
its SSC mode to 16- and 8-bit systems respectively. Each circuit includes an optional
74HCT74 flip-flop to latch DRDY and generate a
level-sensitive interrupt.

With the CS input tied low the CS5501 will shift
out every available sample (4kHz word rate with
a 4MHz master clock). Lower output rates (and
interrupt rates) can be generated by dividing
down the DRDY output and applying it to CS.

Both circuits require that the parallel read process
be synchronized to the CS5501's operation. That
is, the system must not try to enable the registers'
parallel output while they are accepting serial
data from the CS55010 The CS5501's DRDY
falls just prior to serial data transmission and re-

Totally asynchronous interfaces can be created
using a Shift Data control signal from the system
which enables the CS5501's CS input and/or the
shift registers' Sl inputs. The DRDY output can
then be used to disable serial data transmission
once an output word has been fully registered.

CS5501
CS5503

+~v

~

SDATA

A

SCLK

~

PA
PB

MODE
0>
0>

CS
DRDY

Sl
S2

'"0

I-

...r-J:

DO
Dl

Pc
PD

D2

PE
PF

D4

PG

D6

R

D7

OE1 H

D3
D5

.----------------~~---------_a

A

OEl
0>
0>

Sl
S2

~
J:

...r-OE2

D8
PA
PB - - D9
Pc
PD

Dl0

[----_._-

D12

PG

D14

PH

D15

D13

D
1

-

1

~

Q

--------r::> I NT

1
1

J:

1

1

------_._--

SET

1

Dll

PE
PF

cs

-

1

;:!:

Q

1

-lRES-ET

1_ _ _ _ _ _ _ _

1

Only needed for
1
inff>rrtJ{JI c1t'!ve12. sy~e~ J

DRDY
(For polling)

' - - - - - - - - - - - - - - - - - - - - - - - - - - - - -.....- - - - - - - - . - - -.. _ . _ ' . _ - ' - - - - D

Figure Al. 16-bit Parallel Interface
DS31F2

2·401

.,

----------------------

CS5501/CS5503

In such asynchronous configurations the CS5501

is operated much like a successive-approximation
converter with a Convert signal and a subsequent
read cycle.
If it is required to latch the 16-bit data, then 2
74HC595 8-bit "shift register with latch" parts
may be used instead of 74HC299's.

own serial clock. The routine also sets the
CS5501 into a known state.
For each interface, a second subroutine is also
provided which will collect one complete 16-bit
output word from the CS5501. Figure A5 illustrates the detailed timing throughout the
subroutine for one particular interface - the COPS
family interface of Figure A4.

Serial Interfaces

Figures A3 to A8 offer both the hardware and
software interfaces to several industry-standard
microcontrollers using the CS5501's SEC and AC
output modes. In each instance a system initialization routine is provided which configures the
controller's I/O ports to accept the CS5501's serial data and clock outputs and/or generate its

+l5V

g~::~

i

+5V

+5V

5DATA

*

MODE

5CLK

~~~__~
'"

C5

>---

~
x:

51

r

Po D:::.
4 -----,
PE 1-"'-'-------,

j:!R~

~ 52
-

DO
A D1
PB D2
Pc D3
p

A

F

R~
G
QH
R~
OE2 OE1 H

~ ~--~~H-H-H-----------------~-------GC5
A~~-----+~~~+-----------------~-------oAO

OE2 OE1

PA DB
PB D9

'----A

'"'"t;
N

=

>---

S1

~ 52

::t:

j:!

D10
D11
Po
PE D12
PF D13
PG D14
D15

Pc

PH

..-

DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7

-

-- ----

1
1

~D

1
1
1
1
~

.13

SET

Q---C>

--I
INT

1

x:

r--

1

j:!

1

Q

RESET

1

Only needed fo r
interrupt driven

f---- f----

1

~t~SJ

L-------------------------------------*-------------~DRDY

(For polling)

Figure A2. 8-Bit Parallel Interface
2-402

DS31F2

.._-_
.-._.-.
_
..--_...

CS5501/CS5503

Initial Code:
CS5501
CS5503

r

CS

MODE SCLK
SDATA

68HC11
PA6
SCK

v

SS

MISO

L1

SPINIT: PSHA
LDAA
STAA
LDAA
STAA
LDAA

PORTA
; CS = 1, inactive; deselect CS5501
#$10
SPCR
; Disable serial port
#%xx0110xx ; SS-input, SCK-output,
; MOSI-output, MISO-input
STAA DDRD
; Data direction register for port D
LDAA #$50
; Enable serial port, CMOS outputs,
; master, highest clock rate (int. clk/2)
STAA SPCR
LDAA SPSR
: Bogus read to clr port and SPIF flag
LDAA SPDR
; Restore A
PULA
RTS

(68HC05)

Figure A3. 68HCll/CS5501 Serial Interface

Notes:
1. CSSSOI in Synchronous External Clocking mode.
2. Using 68HCll's SPI port. (Can use SCI and
CSSSOl's Asynchronous mode.)
3. Maximum bit rate is LOS Mbps.

1.
2.
3.
4.
S.

PA6 used as CS.
68HCll in single-chip mode.
Receive data via polling.
Normal equates for peripheral registers.
Data returned in register D.

CS5501
CS5503 CS

r

MODE SCLK
SDATA

Code to get word of data:
SP_IN:

WAIT1:

Assumptions:

COPS 444
GO

SK

; Store temporary copy of A

#"lox1 xxxxxx ; Bit 6 = 1, all others are don't cares

WAIT2:

LDAA
STAA
STAA
LDAA
BPL
LDAA
STAA
LDAB
BPL
LDAB
STAB
LDAB
RTS

#%xOxxxxxx
PORTA
SPDR
SPSR
WAIT1
SPDR
SPDR
SPSR
WAIT2
#%x1xxxxxx
PORTA
SPDR

: CS = 1, inactive; deselect CS5501
; Put least significant byte in B

Initial Code:
SPINIT: OGI
RC
XAS

15

=

; CS 1, inactive; deselect CS5501
; Reset carry, used in nex1
; instruction to turn SK off

Code to get word of data:

DI

SP_IN:

LBI

0,12

(All COPS)
SC

Figure A4. COPS/CS5501 Interface

Notes:
1. CSSSOI in Synchronous External Clocking mode.
2. COPS 444 max baud = 62.S kbps. (Others = SOO kbps)
3. See timing diagram for detailed timing.

Assumptions:
1. GO used as CS.
2. Register 0 (upper four nibbles) used to store 16-bit word.

DS31F2

: CS = 0, active; select CS5501
; Put data in serial port to start elk
; Get port status
; If SPIF (MSB) 0, no data yet, wait
; Put most significant byte in A
; Start serial port for second byte
; Get port status
; If SPIF (MSB) 0, no data yet, wait

OGI
LEI
XAS
NOP
NOP
GETNIB: NOP
XAS
XIS
JP
RC
XAS
OGI
RET

14
0

; Point to start of data
; storage location
; Set carry - enables SK in
; ~S instruction
; CS 0, active; select CS5501
; Shift register mode, SO = 0
; Start clocking serial port

=

: Wait for (first) M.S. nibble

GETNIB

15

: Get nibble of data from SIO
; Put nibble in memory, inc. pointer,
; if overflow, jump around this ins!.
; Reset carry - disables SK in XAS
; instruction
; ~us read - stops SK
; CS 1, inactive; deselect CS5501

=

2-403

•

_.-_..---__.._-_
...
._.-.
Instruction

CS5501/CS5503

IG~r:r I

SC I OGI I LEI I XAS I NOP I NOP

r~6~P:1

XAS I XIS I

SYNC
(COPS internal)

CS(GO)
Shift in ___

A-SIO
I

SCLK(SK)

--------------------------~

SYNC
(COPS internal)
CS(GO) ______________________________________________
A-SIO

A-SIO

I

I

SCLK(SK)

DATA (SI)

60

skip

~
Instruction

I XAS I XIS

IG~tLPI

RC I XAS I OGI I RET I

SYNC
(COPS internal)

CS(GO)

----------------------------~

A-SIO
I

SCLK(SK)

Figure AS. Serial Timing Example· COPS
2-404

DS31F2

----------------------

CS5501/CS5503

CS5501

8051

DRDY

r-.
-

-

MODE

I
i

c-----------------""

CS
SCLK
DATA
SPINIT:

INT1

CS

P1.1

SCLK

P1.2

SDATA

P1.3

Figure A6. MCS51 (8051) ICS5501 Serial Interface

Notes:
1. CS5501 in Synchronous External Clocking mode.
2. Interrupt driven 110 on 8051 (For polling, connect
DRDY to another port pin).

Assumptions:
1. INTl external interrupt used.
2. Register bank I, R6, R7 used to store data word,
R7 MSbyte.
3. EA enabled elsewhere.

EQU
EQU
EQU
CLR
SETS
SETS
SETS
CLR
SETS

P1.1
Pl.2
Pl.3
EXI
ITI
DATA
CS
SCLK
EXI

Disable INTI
Set INT1 for falling edge triggered
Set DATA to be input pin
CS = 1; deselect CS5501
SCLK low
Enable INT1 interrupt

Code to get word of data:
ORG 0003H
LJMP GETWD
GETWD: PUSH PSW
PUSH A
MOV PSW,#08
MOV R6,#8
CLR
CS
MSSYTE:SETS SCLK
MOV C,DATA
CLR
SCLK
RLC
A
DJNZ R6,MSSYTE
MOV R7,A
MOV R6,#8
LSSYTE: SETS SCLK
MOV C,DATA
CLR
SCLK
RLC
A
DJNZ R6,LSSYTE
MOV R6,A
SETS CS
POP A
POP
PSW
RETI

; Interrupt vector
; Save temp. copy
; Save temp. copy
; Set register bank 1 active
; number of bits in a byte
; CS = 0; select CS5501
; Toggle SCLK high
; Put bit of data into carry bit
; Toggle SCLK low; next data bit
; Shift DATA bit into A register
; Dec. R6, if not 0, get another bit
; Put MSbyte into R7
; Reset R6 to number of bits in byte
; Toggle SCLK high
; Put bit of data into carry bit
; Toggle SCLK low; next data bit
; Shift DATA bit into A register
; Dec. R6, if not 0, get another bit
; Put LSbyte into R6
; CS =1; deselect CS5501
; Restore original value
; Restore original value

SCLK

OSC
P1.2

(Assumptions cant.)
3. Word received put in A (ACC) and B registers,
A = MSbyte.
4. No error checking done.
5. Equates used for peripheral names.

SDATA

RXD

Initial Code:

CS5501

MODE

8051

-5V

Figure A7. MCS51 (8051) ICS5501 UART Interface

Notes:
1. CS5501 in Asynchronous (UART-like) mode.
2. 8051 in mode 2, with OSC = 12 MHz,
max baud = 375 kbps.

Assumptions:
1. P1.2 (port I, bit 2) used as CS.
2. Using serial port mode 2, Baud rate = OSC/32.

DS31F2

Initial Code:

SPINIT: SETS SMOD
; Set SMOD = I, baud = OSC/32
SETS Pl.2
; CS = 1, inactive
MOV SCON,#1001000S
; Enable serial port mode 2,
; receiver enabled, transmitter disabled
CLR
ES
; Disable serial port interrupts (polling)
RET

Code to get word of data:
CLR
JNS
CLR
MOV
JNS
CLR
MOV
SETS
RET

P1.2
RI,$
RI
A,SSUF
RI,$
RI
S,SSUF
P1.2

CS = 0, active; select CS5501
Wait for first byte
Put most significant byte in A
wait for second byte
Put least significant byte in S
CS = I, inactive; deselect CS5501

2-405

.-_
_
..--_.-.
__.._-_
...-.
CS5501

TMS70X2
-

CS

r

MODE SCLK
SDATA

-5V

CS5501/CS5503

AO
SCLK
RXD
(TMS70CX2)

Figure AS. TMS70X2ICS5501 Serial Interface

Initial Code:
SPINIT: DINT
MOVP
MOVP
MOVP
MOVP
MOVP
MOVP
MOVP
MOVP

%l,ADDR
; A port is o!1.lPut
%l,APORT ; AO = 1, (CS is inactive)
%O,P17
;
%>10,SCTLO; Resets port errors
% ?x1 x011 01,SMODE ; Set port for Isosync,
%?00x1110x,SCTLO ;
8 bits, no parity
%07,T3DATA ; Max baud rate
% ?01 OOOOOO,SCTL1 ; No multiprocessor;
;
prescale = 4
MOVP %O,IOCNT1 ; Disable INT4 - will poll port
PUSH A
; Store original
MOVP RXBUF,A
; Bogus read to clr receiver port flag
; Restore original
POP A
EINT
RET

Notes:
1. CSS501 in Asynchronous (UART-like) mode.
2. TMS70X2 in Isosynchronous mode.
3. TMS70X2 with 8 MHz master clock has max
baud =1.0 Mbps.

Assumptions:
1.
2.
3.
4.
S.

AO used as CS.
Receive data via polling.
Word received put in A and B upon return, A = MS byte.
No error checking done.
Normal equates for peripheral registers.

2-406

Code to get word of data:
SP_IN:
WAIT1
WAIT2

MOVP
BTJZP
MOVP
BTJZP
MOVP
MOVP
RET

%O,APORT ; CS active, select CS5501
%2,SSTAT,WAIT1
; Wait to receive first byte
RXBUF,A
; Put most significant byte in reg. A
%2,SSTAT,WAIT2
; Wait to receive second byte
RXBUF,B
; Put least significant byte in reg. B
%l,APORT ; CS inactive, deselect CS5501

DS31F2

.
...,....,....
......
.
..,.., ...,.,
..,~~

~

CDB5501/CDB5503

Semiconductor Corporation

I

CS5501/CS5503 Evaluation Board
Features

General Description

• Operation with on-board clock
generator, on-board crystal, or an
off-board clock source.

The CDB5501/CDB5503 is an evaluation board designed for maximum flexibility when evaluating the
CS5501/CS5503 AID converters. The board can easily
be configured to evaluate all the features of the
CS5501/CS5503, including changes in master clock
rate, calibration modes, output decimation rates, and interface modes.

• DIP switch selectable or micro port
controllable:
Unipolar/Bipolar input range
Sleep Mode
All Cal Modes
• On-board Decimation Counter

The evaluation board interfaces with most microcontrollers and allows full control of the features of the
CS5501 or CS5503. DIP switch selectable control is
also available in the event a microcontroller is not used.
The evaluation board also offers computer data interfaces including RS-232 and parallel port outputs for
evaluating the CS5501.

• Multiple Data Output Interface Options:
RS-232 (CS5501)
Parallel Port (CS5501)
Micro Port (CS5501 & CS5503)

All calibration modes are selectable including Self-Cal,
System Offset Cal, and System Offset and System
Gain Cal. A calibration can be initiated at any time by
pressing the CAL pushbutton switch.
ORDERING INFORMATION:

elKIN

!:

CS55011
CS5503

CDB5501 or CDB5503

'0

Parallel
Port

'0

AIN

RS-232
Port
+SGND-S

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

....
(J.)

Micro
Port

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

m
(J.)

:r:

....
(J.)
m
(J.)

:r:
0

..c
:::l

en

MAR '95
DS31DB3
2-407

-

-------~------------INTRODUCTION
The CDB550l/CDB5503 evaluation board provides maximum flexibility for controlling and
interfacing to the CS550l/CS5503 AID converters. The CS5501 or the CS5503 require a minimal
amount of external circuitry. The devices can operate with a crystal (or ceramic resonator) and a
voltage reference.
The evaluation board includes several clock
source options, a 2.5 volt trimmable reference,
and circuitry to support several data interface
schemes. The board operates from +5 and -5 volt
power supplies.

CDB5501/CDB5503

(1200, 2400, 4800, etc.) when the CDB5501
evaluation board is configured to provide RS-232
data output. If a different operating frequency for
the CS5501lCS5503 is desired, three options exist. First, a BNC input is provided to allow an
external CMOS (+5V) compatible clock to be
used. Second, the crystal (Yl) in the on-board
gate oscillator can be changed. Or, third, the onchip oscillator of the CS550l/CS5503 can be used
with a crystal connected in the Y2 position.
2. 5 Volt Reference
A 2.5 volt (LTlOl9CN8-2.5) reference is provided
on the board. Potentiometer R9 allows the initial
value of the reference to be accurately trimmed.

Evaluation Board Overview
Decimation Counter

The CDB5501lCDB5503 evaluation board includes extensive support circuitry to aid
evaluation of the CS550l/CS5503. The support
circuitry includes the following sections:
1) A clock generator which has an on-board
oscillator and counter divider IC.
2) A 2.5 volt trimmable voltage reference.
3) A Decimation Counter.
4) A parallel output port (for CS5501 only).
5) An RS-232 interface (for CS5501 only).

The CS550l/CS5503 updates its internal output
register with a l6-bit word every 1024 clock cycles of the master clock. Each time the output
register is updated the DRDY line goes low. Although output data is updated at a high rate it may
be desirable in certain applications to activate the
CS to read the data at a much lower rate. A decimation counter is provided on the board for this
purpose. The counter reduces the rate at which
the CS line of the CS550l is activated by only
allowing CS to occur at a sub-multiple of the
DRDYrate.

6) A micro port (for CS5501 or CS5503).
7) DIP switch and CAL pushbutton.
Clock Generator

The CS550l/CS5503 can operate off its on-chip
oscillator or an off-chip clock source. The evaluation board includes a 4.9152 MHz gate oscillator
and counter-divider chain as the primary clock
source for the CS550l/CS5503. The counter-divider outputs offer several jumper-selectable
frequencies as clock inputs to the
CS550l/CS5503. The 4.9152 MHz crystal frequency was chosen to allow the counter-divider
chain to also provide the common serial data rates
2-408

Parallel Output Port (for CS5501 only)

The output data from the CS550l/CS5503 is in
serial form. Some applications may require the
data to be read in parallel format. Therefore the
evaluation board includes two 8-bit shift registers
with three-state outputs. Data from the CS550l is
shifted into the registers and then read out in
16-bit parallel fashion. The parallel port comes set
up for 16-bit parallel output but can be reconfigured to provide two 8-bit reads. The parallel port
supports the CS5501 only, since the CS5503 outputs 20-bit words.

DS31DB3

.._-_
.-_
._.-.
_
..--__
...

CDB5501/CDB5503

RS-232 Port (for CS5501 only)

Jumper Selections

The CS5501 has a data output mode in which it
fonnats the data to be DART compatible; each serial output byte is preceded by a start bit and
tenninated with two stop bits. Serial data in this
fonnat is commonly transferred using the RS-232
data interface. Therefore the evaluation board includes an RS-232 driver and output connector.
The CS5503 does not provide this output mode.

The evaluation board has many jumper selectable
options. This table describes the jumper selections
available.
PI

Selects between the on-board 4.9152 MHz
oscillator (INT) or an external (EXT) clock
source as the input to the clock generator!
divider chain.

P2 Allows any of the counter/divider output
clock rates to be selected as the input clock
to the CS5501lCS5503.

Micro Port
The CS5501/CS5503 was designed to be compatible with many micro-controllers. Therefore the
evaluation board provides access to all of the data
output pins and the control pins of the
CS5501lCS5503 on header connectors.

P3

DIP Switch and CAL Pushbutton

Allows selection of baud rate clocks when
the CS5501 is in the DART compatible mode.
When using the on-board 4.9152 MHz standard baud rates between 1200 and 19,200 are
available.

P4 Selects the divide ratio of the Decimation
Counter.

Although all of the control lines to the
CS5501/CS5503 are available on header connectors at the edge of the board, it is preferable to not
require software control of all of these pins.
Therefore DIP switch control is provided on some
of these control lines. The CAL input to the
CS5501/CS5503 is made available at a header pin
for remote control, but pushbutton control of CAL
is also provided.

P5 Selects one of the three available output data
modes of the CS5501 or one of two available
output data modes of the CS5503.
P9 Enables the output of the Decimation
Counter to control the CS line of the
CS5501lCS5503.
Pll

Connects the baud clock from the on-board
clock divider as the input to the SCLK pin
of the CS5501/CS5503.

v+

Rl
10M

TP3

1

r-~~

v+

1~Ic5

U2

i 4.9152 MHz
+------l 0fv1

-LCl
30 pF

r

TP2

R3
COl
200
~1---4-------'W\~-

CLKIN

74HC4040

8

IO.l ~F

T:--T~--Tc-T:-::-T~T:-::-ir=--"~ c

PT-------------~o-···-·o ~- O~---O : P3

-O-------o---------------o----o----o

N= 0

1

23 4 5
Master Clock

6 7
TP5

8

9 1011 12
Baud Clock
~ BRCLK (fig. 2)
CLKIN (fig. 2)

Figure 1. Clock Generator
DS31DB3

2-409

----------- -----------

CDB5501/CDB5503

Clock Options
Several clock source options are available. These
include:
1) an external clock (+5 V CMOS-Compatible);
2) an on-board 4.9152 MHz crystal oscillator
with a 2n divider (n = 1, 2, ... 7);
3) a 4.096 MHz crystal.

Connector PI allows jumper selection of either an
external clock or the on-board 4.9152 MHz crystal oscillator (See Figure 1 for schematic) as the
clock source for the CLKIN signal on pin 3 of the
CS5501lCS5503 (shown in Figure 2).
If the EXT position is selected, a CMOS-compatible clock signal (5 volt supply) should be input
to the BNC connector labeled CLKIN. If the INT
position is selected the 4.9152 MHz oscillator output is input to counter/divider IC U2. In either

CLKIN
(fig. 1)

'>0-----"""'"6,0

5 SO

U4

, CS55011

SCLK
(fig. 3)

, CS5503

SCLKI-'19"-4--O-O--+--.----~___"I

1'7

>'''-----------;;'C8,

v+
~ob2k

SCO

RN 3.5
47 k

MODEI-'1--+--_""~r

f-'1-"-2..........- - 1d"
11U

P11'"·~'

'gSCI

(seNc

MODE: SSC SECAC'

BRCLK
(fig. 1)

• AC Mode available only in CS5501

Figure 2. Decimati!)n Counter I Microport

2-410

OS31083

.-_
_
..--_._.
__.._-_
...-.

CDB5501/CDB5503

Data Output from the CS5501lCS5503
P-1
INT ClK
EXT ClK

ClKIN Source to CS5501/CS5503
On-Board 4.9152 MHz OSC
+5 CMOS ClKIN BNC

ClKIN Rate Selection (ClKl2 n) with INT ClK on P1 selected.
ClK = 4.9152 MHz

P-2
0
1
2
3
4
5
6
7

ClKIN Rate
4.9152 MHz
2.4576 MHz
1.2288 MHz
614.4 kHz
307.2 kHz
153.6 kHz+
76.8 kHz+
38.4 kHz' +

• Exceeds ClKIN Specifications of CS5501.

+ Exceeds ClKIN specifications of CS5503.

Table 1. Clock Generator

case, the counter divides the input clock by 2n
where n = 0, 1, ... 7. Any of the binary sub-multiples of the counter input clock can be input to the
CS5501/CS5503 by jumper selection on connector P2.
The CS5501lCS5503 contains its own on-chip oscillator which needs only an external crystal to
function. Ceramic resonators can be used as well
although ceramic resonators and low frequency
crystals will require loading capacitors for proper
operation.
To test the oscillator of the CS5501lCS5503 with
a crystal (Y2) a jumper wire near crystal Y2 must
be opened and another jumper wire soldered into
the appropriate holes provided to connect the
crystal to the chip. Additional holes are provided
on the board for loading capacitors.

The CS5501 has three available data output
modes (The CS5503 has two available data output
modes). The operating mode of the part is determined by the input voltage level to the MODE
(pin 1) pin of the device. Once a mode is selected,
four other pins on the device are involved in data
output. The first of these is the DRDY pin (pin
18). It is an output from the chip which signals
whenever a new data word is available in the internal output register of the CS5501lCS5503. Data
can then be read from the register, but only when
the CS pin (pin 16) is low.
When CS is low, data bits are output in serial
form on the SDATA pin (pin 20). In the Synchronous Self-Clocking mode of the CS5501lCS5503,
the chip provides an output data clock from the
SCLK pin (pin 19). This output clock is synchronous with the output data and can be used to
clock the data into an external register.
In Synchronous External-Clocking and Asynchronous Communications modes of the CS5501, the
SCLK pin is an input for an external clock which
determines the rate at which data bits appear at
the SDATA output pin. In the CS5503, only synchronous external-clocking mode is available.
The signals necessary for reading data from the
CS5501lCS5503 are all available on connector
PIO as shown in Figure 2.

P-5
SSC
SEC
AC'

Data Output Mode
Synchronous Self-Clockina
Synchronous External-Clocking
Asvnchronous Communications

* Available in CS5501 only.

Table 2. Data Output Mode

DS31DB3

2-411

-

CDB5501/CDB5503

CS550IlCS5503 Data Output Mode Selection
Connector P5 (see Figure 2) allows jumper selection of anyone of the three data output modes.
These modes are:
1) SSC (Synchronous Self-Clocking);
2) SEC (Synchronous External Clocking);
3) AC (Asynchronous Communication).
(AC mode is available only in the CS5501)
SSC (Synchronous Self-Clocking) Mode
The SSC mode is designed for interface to those
microcontrollers which allow external clocking of
their serial inputs. The SSC mode also allows
easy connection to serial-to-parallel conversion
circuitry.
In the SSC mode serial data and serial clock are
output from the CS5501lCS5503 whenever the
CS line is activated. As illustrated in Figure 2, all
of the signals are available at connector PIO. If
the CS signal is to be controlled remotely the
jumper on P9 should be placed in the NC (No
Connection) position. This removes the~ecima­
tion Counter output from controlling the CS line.
Data Output Interface: Parallel Port (for
CS5501 evaluation only).
Whenever the CS5501 is operated in the SSC
mode the 16-bit output data is clocked into two
8-bit shift registers. The registers have three-state
parallel outputs which are available at P7 (see
Figure 3). A flip-flop (U8A) is used to signal the
remote reading device whenever the registers are
updated. The PDR (parallel Data Ready) signal
from the flip-flop is available on P7. The Q-bar
output from the flip-flop locks out any further updates to the registers until their data is read and a
DACK (Data ACKnowledge) signal is received
from the remote device.
Activation of the CS line determines the rate at
which the CS5501 will attempt to update the output shift registers. Data will be shifted into the
2-412

registers only if a DACK signal has occurred
since the last update.
The CS line can be controlled remotely at PIO or
by the output of the Decimation Counter. If CS is
controlled remotely, the Decimation divide jumper
on P4 should be placed in the "0" position. This
insures that the DCS signal will occur at the same
rate CS is activated. The positive going edge of
DCS toggles the U8A flip-flop which signals an
update to the parallel port.
The parallel registers are set up to be read in 16bit parallel fashion but can be configured to be
read separately as two 8-bit bytes on an 8-bit bus.
To configure the board for byte-wide reads, the
byte-wide jumpers must be soldered in place. In
addition, for proper "one byte at a time" address
selection, a connection on the circuit board needs
to be opened and a jumper wire soldered in the
proper place to determine which register is to be
read when AO is a "1" and vice versa. See Figure
3 for schematic details. The evaluation board
component layout diagram, Figure 7, indicates the
location of the byte-wide jumpers and AO address
selection jumpers.
After data is read from the registers a DACK
(Data Acknowledge) signal is required from the
off-board controller to reset flip-flop U8A. This
enables the registers to accept data input once
again.
The DRB and CSB signals on connector PIO
should be used to monitor and control the CS5501
output to the serial to parallel conversion registers.
Be aware that an arbitrarily timed DACK signal
may cause the output data registers to be enabled in the middle of an output word if the CS
signal to the CS5501 is not properly sequenced.
This will result in incorrect data in the output
registers.
If the Decimation Counter is used to control the
output of the CS5501 (Jumper on P9 in the DC
position), the CSB signal on PIO can be moniDS31DB3

----------------------

CDB5501/CDB5503
V+
-,

-

RN 3.4
47 k

TP18

~52~
U6
~

'{~

6 (0;3 1 TP17

C14

I~
20

013
012
011
010
09
D8
'~

-- , J

'{~

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0.1 flF -= =20
Vee U9
PH
74HCT299
.1- 51
PG
9 R5T
PF
IL QA
PE
L - - 1L QH
PO
12 ClK
PC

50ATA
(fig. 2)

~+

OC5
(fig. 2)

--

- -

:Byte Wi de
,Jumpe rs

-

P7
/~,

16

07

4
15

06
05

5

D4

14

03

6
13
18 A
PB
11
7
H
PA
OEl OE2 52 GNO
RN1.4
_!AI
2 13 ~10

02
01
00
OACK

'c

POR

~~k

C22

O. lflF T_

V+

AO
015
)J: 014

-

16
74HCT299 PH 4
~ 51
PG
9 R5T
PF 15
!L QA
PE 5
14
lL QH
PO
12 I>ClK
PC 6
13
18 A
PB
PA 7
. - ~H
OEl OE2 52 GNO
2j3M. 10

5ClK

o '

--'--

Vee Ul0

(fig. 2)

PC5
R 18
100 k

--

•

~_~~a_der

~O

~
-

4

14
5

j~19

Q~
U8A
3 74HC74
Cl
oeL-R
17 yl

12

74HCT04
U6 13

f

RN 3.2
47 k

Figure 3. 16-Bit Parallel Port
DS31DB3

2-413

---------------_ aw _ _ _ __

CDB5501/CDB5503

tored to signal when data into the output registers
is complete (DCS returns high). The DACK signal is not needed in this mode and the lockout
signal to the the S 1 inputs of registers U9 and
UIO may be disabled by removing the connection
on the circuit board. A place is provided on the
board for this purpose. A pull-up resistor is provided on the S 1 inputs of the registers if the
connection is opened.

ready bar) signal on PIO indicates to the microcontroller when data from the CS5501lCS5503 is
available. Clock from the microcontroller is input
into SCI (serial clock input) and data output from
the CS5501lCS5503 is presented to the SD (serial
data) pin of the PI0 connector. Note that the
jumpers on connectors P9 and Pll must be in the
NC (no connection) position to allow the microcontroller full control over the signals on PIO.

SEC (Synchronous External Clocking) Mode

AC (Asynchronous Communication) Mode
(for CS5501 evaluation only)

The SEC mode enables the CS5501lCS5503 to be
directly interfaced to microcontrollers which output a clock signal to synchronously input serial
data to an input port. The CS5501/CS5503 will
output its serial data at the rate determined by the
clock from the microcontroller.
Connector PIO allows a microcontroller access to
the CS5501lCS5503 signal lines which are necessary to operate in the SEC mode.
The CSB (chip select bar CS) signal allows the
micro controller to control when the
CS5501/CS5503 is to output data. The DRB (data

Baud Rate Clock Divider (CLKl2") with INT CLK on P1 selected.
CLK = 4.9152 MHz

P-3
8
9
10
11
12

Baud Rate ClK Divider
19.2 kHz
9.6 kHz
4.8 kHz
2.4 kHz
1.2 kHz

On-Board Baud Rate Clock Input to CS5501/CS5503 SCLK Input.

P-11
NC
BC

SClK Input to CS5501/CS5503
No Connection
Baud Clock

Thble 3. On-Board Baud Rate Generator

2-414

The AC mode enables the CS5501 to output data
in a UART-compatible format. Data is output as
two characters consisting of one start bit, eight
data bits, and two stop bits each.
The output data rate can be set by a clock input to
the SCI input at connector PIO (see Figure 2).
The jumper on Pll must be in the NC position.
Alternatively an output data bit rate can be selected as a sub-multiple of the external CLKIN
signal to the board or as a sub-multiple of the onboard 4.9152 MHz oscillator. Counter IC U2
divides its input by 2n where n = 8, 9, .. .12. One
of these outputs can be jumper selected at connector P3 (see Figure 1). For example, if the 4.9152
MHz oscillator is selected as the input to IC U2
then a 1200 baud rate clock can be selected with
the jumper at n = 12. Table 3 indicates the baud
rates available at connector P3 when the 4.9152
MHz oscillator is used. If the on-board baud clock
is to be used, the jumper on connector Pll should
be in the BC (Baud Clock) position.
Data Output Interface: RS-232 (for CS5501
evaluation only).

The RS232 port is depicted in Figure 4. Sub-D
connector P6 along with interface IC Ull provides the necessary circuitry to connect the
CS5501 to an RS-232 input of a computer. For
proper operation the AC (Asynchronous Communication) data output mode must be selected. In
addition, an appropriate baud clock needs to be
DS31DB3

-------------------~-

CDB5501/CDB5503
P6

SDATA (fig. 2)

3

-------'--'-j

__
RN1.5
DRDY (fig. 2) --o-~>------'-=i

5

DATA

CTS

DSR

DCD

RTS

11

DTR

3

5

6

B

Each time a data word is available for output
from the CS5501lCS5503, the DRDY line goes
low, provided the output port was previously
emptied. If the DRDY line is directly tied to the
CS input of the CS5501/CS5503, the converter
will output data every time a data word is presented to the output pin. In some applications it is
desirable to reduce the output word rate. The rate

4

20

7

NC

Sub-D
25 pin

Figure 4. RS·232 Port

input to the CS5501. See AC (Asynchronous
Communication) mode mentioned earlier for an
explanation of the baud rate clock generator and
the data format of the output data in the AC
mode.
The DRDY output from the CS5501 signals the
CTS (Clear To Send) line of the RS-232 interface
when data is available. The Decimation Counter
can be used to determine how frequently output
data is to be transmitted.
The RS-232 interface on the evaluation card is
functionally adequate but it is not compliant with
the EIA RS-232 standard. When the MC145406
RS-232 receiver/driver chip is operated off of ± 5
volt supplies rather than ± 6 volts (see the
MC145406 data sheet for details) its driver output
swing is reduced below the EIA specified limits.
In practical applications this signal swing limitation only reduces the length of cable the circuit is
capable of driving.
DS31DB3

DECIMATION COUNTER

Decimation Counter Accumulates 2n+1 DRDY Pulses Before CS is
Enabled.

P-4

2"+1

0
1
2
3
4
5
6

2
4
8
16
32
64
128
256
512
1024
2048
4096

7

8
9
10
11

P-9
NC
DC

DC Output to CS
No Connection
Decimation Counter

Table 4. Decimation Counter Control

can be reduced by lowering the rate at which the
CS line to the chip is enabled. The
CDB5501lCDB5503 evaluation board uses a
counter, IC U3 for this purpose. It is known as a
decimation counter (see Figure 2). The outputs of
the counter are available at connector P4. The
counter accumulates 2n+ 1 counts (n = 0, 2, ... 11)
at which time the selected output enables the CS
input to the CS5501lCS5503 (if the jumper in P9
is in the DC, Decimation Counter, position). The
2-415

-

_.-_..--_._.
__.._-_
...-.
Switch
SW1-1

CDB5501/CDB5503

ON
SC2=0

OFF
SC2=1

SW1-2
SW1-3

SC1 =0

SC1 =1

UNIPOLAR

BIPOLAR

SW1-4

SLEEP

AWAKE

CAL

SC1

SC2

Cal.TYpe

ZSCal

FSCal

Sequence

""""-

0

0

Self-Cal

AGND

VREF

One Step

1
0

1
1

System Offset
/l. System Gain

AIN

-

AIN

1st Step
2nd Step

1

0

SYStem Offset

AIN

VREF

One Stee

Table 5. DIP Switch Selections

Table 6. Calibration Mode Table

"D" input to flip-flop U8B is enabled to a "1" at
the same time CS goes low. When DRDY returns
high flip-flop U8B is toggled and resets the
counter back to zero which terminates the CS enable. The counter then accumulates counts until
the selected output activates CS low once again.
DIP Switch Selections/Calibration Initiation
Several control pins of the CS5501lCS5503 can
be level activated by DIP switch selection, or by
microcontroller at P8, as shown in Figure 5. DIP
switch SW1 selections are depicted in Tables 5
and 6. The CAL pushbutton is used to initiate a
calibration cycle in accordance with DIP switch
positions 1 and 2. The CAL pushbutton should be

activated any time power is ftrst applied to the
board or any time the conversion mode (BPIUP)
is changed on the DIP switch. Remote control of
the CAL signal is available on connector P8. Connector P8 also allows access to the DIP switch
functions by a microcomputer/microcontroller.
The DIP switches should be placed in the off position if off-board control of the signals on
connector P8 is implemented.
Voltage Reference
The evaluation board includes a 2.5 volt reference. Potentiometer R9 can be used to trim the
reference output to a precise value.
Analog Input Range: Unipolar Mode

U4

CS55011
CS5503
CAL 13

SC2
17

SC1
4

BPIUP
12

SLEEP
11

SW2

V+w~-+--~-+---'-+--~

t\i

Analog Input Range: Bipolar Mode

~
SWI

The value of the reference voltage sets the analog
input signal range, In unipolar mode the analog
input range extends from AGND to VREF. If the
analog input goes above VREF the converter will
output all "l's". If the input goes below AGND,
the CS5501/CS5503 will output all "O's".

~."r.

---£ --~ ---:'t:

v+

WARNING: Some evaluation boards were produced with the
SCI and SC2 labels reversed on the silkscreen

The analog signal input range in the bipolar mode
is set by the reference to be from +VREF to VREF. If the input signal goes above +VREF, the
CS5501lCS5503 will output all "l's". Input signals below -VREF cause the output data to be all
"O's".

Figure 5. DIP Switch I Header Control Pin Selection

2·416

DS31DB3

.-_
_
..--_._.
__.._-_
...-.

CDB5501/CDB5503

Analog Input: Ove"ange Precautions

limited to ± 10 rnA as the analog input of the chip
is internally diode clamped to both supplies. Excess current into the pin can damage the device.
On the evaluation board, resistor R16 (see Figure
6) does provide some current limiting in the event
of an overrange signal which exceeds the supply
voltage.

In normal operation the value of the reference
voltage determines the range of the analog input
signal. Under abnormal conditions the analog signal can extend to be equal to the VA+ and VAsupply voltages. In the event the signal exceeds
these supply voltages the input current should be

R4
10

V+

+

14

]120
lOIlF
-

VA+
CS55011
CS5503

R6
10

U4
C6
~
O.lILF
+SV
TP14

-

01
6.B

-

TP13
GNO

-

10

VOUT 6
US
RB
LT1019-2.S
1M
R9
TRIM S
t SO k
GNO
CW
4

VREF

TP1S

-

9 AIN
02
6.B
TP12

7 VAR7
10

-SV
RS
10

V-

+

~17
lOIlF

C21
0.0047 I,!
X7RI

6 VO-

CB

C9

~l1lF

~l1lF
-

-

AIN

Figure 6. Voltage Reference I Analog Input

DS31DB3

2·417

.._-_
_.-_..--_._.
__
...-.
Oscilloscope Monitoring of SDATA
The output data from either the CS5501 or the
CS5503 can be observed on a dual trace oscilloscope with the following hook-up. Set the
evaluation board to operate in the SSC mode.
Connect scope probes to TP9 (SCLK) and TPIO
(SDATA). Use a third probe connected to TP8
(DRDY) to provide the external trigger input to
the scope (use falling edge of DRDY to trigger).
With proper horizontal sweep, the SDATA output
bits from the NO converter can be observed.
Note that if the input voltage to the CS5501 is
adjusted to a mid-code value, the converter will
remain stable on the same output code. This illustrates the low noise level of the CS5501. The
CS5503 will exhibit a few LSB's of noise in its
observed output in agreement with its noise specifications.

2-418

CDB5501/CDB5503

Evaluation Board Component Layout and
Design Considerations
Figure 7 is a reproduction of the silkscreen component placement of the PC board.
The evaluation board includes design features to
insure proper performance from the AID converter
chip. Separate analog and digital ground planes
have been used on the board to insure good noise
immunity to digital system noise.
Decoupling networks (R6, C7, and R7, C9 in Figure 6) have been used to eliminate the possibility
of noise on the power supplies on the digital section from affecting the analog part of the AID
converter chip.
The RC network (RIO, C16 and C19) on the
output of the LTI019-2.5 reference may not be
needed in all applications. It has been included to
insure the best noise performance from the reference.

DS31DB3

----------- ----------I

CDB5501/CDB5503

D i;io

ClK I N

I

TP2 R3

(IFTIcmL)

6 10OCLP:O~'iJ'~D~i[J"'
os IECI"'~
C3
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I
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I

--~----+5V~--R~----I-

YI

10 I
9 I

RI C2

~

Rei

TP3

I

IRlll

TPI. . .__
I 0=-,I D

~~4 P21

DI

I~
-5~~" ~
I

P5

R7
~

TPI~~
TP8

D nCI~~
TPI4I

lE
R8

R9

II

9
TRIM

- - - - - - - - - - - - -

D

~I: -

AIN

CD85501

L

Evaluatian Ebard

~~sI
R6

TPtS C6
TPI6

U4

I

T[]

AGND

I

1

~~FEL Pffi~9
18

D~ ___________:

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CAL:

AD.uf'ER8

5

6

UIO

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AO

I

+8 -9

11.1
I--~

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P7

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~

:0 iOc:OEO:SO 0 D~ i
C

[21

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I C14c::J

TP7~C7

101~

RIO'

(JCt2

TP19:

CB'-----J I

2.5V REFEREfICE

I
I

1.I3

c::J

(J;
~D
~~C.!.8~~
AGND

P41i~

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0 I
MASTER CLOCK r - - - - - 1_______

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SMART Ana log@

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TP6

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Figure 7. CDB5501/CDB5503 Component Layout

DS31DB3

2-419

.._-_
.-_.._..-.-.
_
...
~--

CDB5501/CDB5503

• Notes·

2·420

DS31DB3

.
...,....,..........
.
.....,
~

~~~

~~

CS5504

Semiconductor Corporation

Low Power, 20-Bit AID Converter
Features

General Description

• Delta-Sigma AID Converter
- 20-bit No Missing Codes
- linearity Error: ±0.0007%FS

The CS5504 is a 2-channel, fully differential 20-bit, serial-output CMOS AID converter. The CS5504 uses
charge-balanced (delta-sigma) techniques to provide a
low cost, high resolution measurement at output word
rates up to 200 samples per second.

• 2 Differential Inputs
- Pin Selectable Unipolar/Bipolar
Ranges
- Common Mode Rejection
105 dB @ dc
120 dB @ 50,60 Hz

The on-chip digital filter offers superior line rejection at
50Hz and 60Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Hz.).
The CS5504 has on-chip self-calibration circuitry which
can be initiated at any time or temperature to ensure
minimum offset and full-scale errors.
Low power, high resolution and small package size
make the CS5504 an ideal solution for loop-powered
transmitters, panel meters, weigh scales and batterypowered instruments.

• Either 5V or 3.3V Digital Interface
• On-chip Self-Calibration Circuitry

ORDERING INFORMATION:
CS5504-BP
-40°C to +85°C
CS5504-BS
-40°C to +85°C

• Output Update Rates up to 200/second
• Low Power Consumption: 4.4 mW

VREF+
12

VREF13

VA+

VA-

DGND

VD+

14

15

16

17

20-pin PDIP
20-pin SOIC

2
AIN1+ (~
AIN1- eJQ.
AIN2+
AIN2-

AO

~

-

M
U
X

~T

---.
---.

18

Serial
Interface
Logic

4th-Order
Delta-sigma
Modulator

-------

19
20

Digital
Filter

~

T

I

Calibration
SRAM

I.

I

Calibration IlC

Crystal Semiconductor Corporation

7

SCLK
SDATA
DRDY

CAL
BP/UP

OSC

1

3
CONV

P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

4

CS

15

*6

XIN

XOUT

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS126F1

2-421

•

,

.....
.....-..
_.-......
_-___...

CS5504

ANALOG CHARACTERISTICS (TA = TMIN to TMAX;

VA+ = 5V±10%; VA- = -5V± 10%; VD+ =
3.3V ± 5%; VREF+ = 2.5V, VREF- = OV; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kQ with a 10nF to GND
at AIN.) (Notes 1, 2)
Parameter"

Min

Specified Temperature Range

Typ

Max

Units

DC

-40 to +85

Accuracy

-

Linearity Error

0.0007

0.0015

±%FS

(No Missing Codes)

20

-

Bits

(Note 3)

-

-

Full Scale Error

±4

±32

LSB

Full Scale Drift

(Note 4)

-

±8

-

LSB

Unipolar Offset

(Note 3)

±32

LSB

(Note 4)

-

±8

Unipolar Offset Drift

±8

-

LSB

Bipolar Offset

(Note 3)

±4

±16

LSB

Bipolar Offset Drift

(Note 4)

±4

-

LSB

2.6

-

LSBrms

o to +2.5

-

Differential Nonlinearity

Noise (Referred to Output)

-

Analog Input

Analog Input Range:
Common Mode Rejection:

Unipolar
Bipolar
dc
50,60- Hz

(Note 5)

(Note 2)

Off Channel Isolation
Input Capacitance
(Note 1)

DC Bias Current

-

±2.5
105

V
V
dB
dB

120

-

-

120

-

5

-

600

~

-

465
425
40

-

~A
~A

-

4.4

6.0

mW

15

dB
pF
nA

Power Supplies

DC Power Supply Currents:

Power Dissipation

ITotal
IAnalog
IDigital
(Note 6)

-

-

-

80
dB
Power Supply Rejection
Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5504's source
impedance requirements. Refer to the text section Analog Input Impedance Considerations.
2. Specifications guaranteed by design, characterization and/or test.
3. Applies after calibration at the temperature of interest.
4. Total drift over the specified temperature range since calibration at power-up at 25 DC
5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and
VA- supply Voltages.
6. All outputs unloaded. All inputs CMOS levels.
" Refer to the Specification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.

2-422

DS126F1

.-_
_
...",--._.
__.._-_
...-.

CS5504

DYNAMIC CHARACTERISTICS
Parameter

Symbol

Modulator Sampling Frequency
Output Update Rate (CONV

Hz

fs

fcllJ2
fclk/1622

Hz

f-3dB

fclW1928

Hz

ts

1/fout

s

Settling Time to 1/2 LSB (FS Step)

5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX;

Units

fout

= 1)

Filter Corner Frequency

Ratio

VA+, VD+

= SV± 10%; VA- = -SV ± 10%;

DGND = 0.) (Notes 2, 7)
Parameter

Symbol

Min

Typ

Max

Units

XIN
All Pins Except XIN

VIH
VIH

3.S
2.0

-

V
V

XIN
All Pins Except XIN

VIL
VIL

-

-

1.S
0.8

V
V

VOH

(VD+)-1.0

V

-

-

-

VOL

0.4

V

Input Leakage Current

lin

-

±1

±10

Il A

3-State Leakage Current

loz

-

-

±10

9

-

IlA
pF

High-Level Input Voltage:
Low-Level Input Voltage:
High-Level Output Voltage
Low-Level Output Voltage

(Note 8)
lout = 1.6 mA

Cout
7. All measurements are performed under static conditions.
8. lout = -100 1lA. This guarantees the ability to drive one TTL load. (VOH

Digital Output Pin Capacitance
Notes:

3.3V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX;
= -SV ±10%; GND = OV.) (Notes 2, 7)

= 2.4V

@ lout

= -40 IlA).

= SV± 10%; VD+ = 3.3V ± S%;

VA+

VA-

Parameter

Symbol

Min

Typ

Max

Units

-

-

-

V
V

0.3VD+
0.16VD+

V
V

-

V

0.3

V

High-Level Input Voltage:

XIN
All Pins Except XIN

VIH
VIH

0.7VD+
0.6VD+

Low-Level Input Voltage:

XIN
All Pins Except XIN

VIL
VIL

-

High-Level Output Voltage

lout = -400 IlA

VOH

(VD+)-0.3

VOL

Input Leakage Current

lin

-

±1

±10

Il A

3-State Leakage Current

loz

-

-

±10

Digital Output Pin Capacitance

Cout

-

9

-

Il A
pF

Low-Level Output Voltage

DS126F1

lout = 400 IlA

2-423

.. ...
......-..
-. ....,-.~~

~~

CS5504

~~

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMA)G
VA-

= -5V ± 10%;

Input Levels: Logic 0

= OV, Logic 1 = VD+;

Parameter
Master Clock Frequency

Internal Oscillator
External Clock

VA+, vD+ = 5V ± 10%;
CL = 50 pF.) (Note 2)
.

Symbol

Min

Typ

Max

Units

XIN
felk

30.0
30

32.768

-

53.0
330

kHz
kHz

40

-

60

%

1.0

50

-

IlS
ns

-

Master Clock Duty Cycle
Rise Times:
Fall Times:

Any Digital Input
Any Digital Output

(Note 9)

Any Digital Input
Any Digital Output

(Note 9)

trise
tlall

-

1.0

20

-

Ils
ns

10

-

ms

500

-

ms

-

ns

Start-Up
(Note 10)

tres

= 32.768 kHz (Note 11)

tosu

(Note 12)

twup

-

(Note 13)

tccw

100

Power-On Reset Period
Oscillator Start-up Time

XTAL

Wake-up Period

1800lfelk

s

Calibration
CONY and CAL High to Start of Calibration

tsel

-

-

2/felk+200

ns

Start of Calibration to End of Calibration

teal

-

3246lfelk

-

s

CONY Pulse Width (CAL=1)

Conversion
Set Up Time

AO to CONY High

tsae

50

-

-

ns

Hold Time

AO after CONY High

thea

100

tepw

100

-

ns

CONY Pulse Width
CONY High to Start of Conversion

tsen

-

2Ifelk+200

ns

BP/UP stable prior to DRDY falling

tbus

82/felk

BP/UP stable after DRDY falls

tbuh

0

-

ns

(Note 14)

te~n

-

1624lfclk

-

Set Up Time
Hold Time

Start of Conversion to End of Conversion
Notes:

2-424

ns
s

S

9. Specified using 10% and 90% pOints on waveform of interest.
10. An internal power-on-reset is activated whenever power is applied to the device.
11. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
12. The wake-up period begins once the oscillator starts; or when using an external fclk, after the
power-on reset time elapses.
13. Calibration can also be initiated by pulsing CAL high while CONV=1.
14. Conversion time will be 1622/felk if CONY remains high continuously.

DS126F1

___
..........
_......--...-..

CS5504

3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+=5V±10%;
5%; VA- = -5V ± 10%; Input Levels: Logic 0 = OV. Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Master Clock Frequency

Internal Oscillator
External Clock

Symbol

Min

Typ

Max

Units

XIN
felk

30.0
30

32.768

53.0
330

kHz
kHz

60

%

1.0

~s

Master Clock Duty Cycle

40

Rise Times:
Fall Times:

Any Digital Input
Any Digital Output

(Note 9)

Any Digital Input
Any Digital Output

(Note 9)

VD+=3.3V±

trise
ball

-

-

50

-

-

1.0

20

-

ns
~s

ns

Start-Up
Power-On Reset Period

(Note 10)

tras

Oscillator Start-up Time

XTAL = 32.768 kHz (Note 11)

tosu

(Note 12)

twup

-

(Note 13)

Wake-up Period

10

-

ms

500

-

ms

1800/felk

-

s

-

-

ns

21felk+200

ns

3246/felk

-

s

-

ns

-

ns

2/felk+200

ns

-

ns

Calibration
CONY Pulse Width (CAL=1)

tcew

100

CONY and CAL High to Start of Calibration

tscl

Start of Calibration to End of Calibration

teal

-

Conversion

tsen

-

tbus

82/felk

-

BP/UP stable after DRDY falls

tbuh

0

-

(Note 14)

teon

-

1624lfelk

Set Up Time

AO to CONY High

tsae

50

Hold Time

AO after CONY High

thea

100

tepw

100

CONY Pulse Widh
CONY High to Start of Conversion
Set Up Time
Huld Time

BP/UP stable prior to DRDY falling

Star! of Conversion to End of Conversion

DS126F1

ns

s
s

2-425

___-_

.-....,....
........-..

.."

.."

CS5504

XIN
XIN/2
CAL

CONY

------",

STATE

Standby
Figure 1. Calibration Timing (Not to Scale)

XIN
XIN/2

AO _ _ _.JL_~~~_ _~~-+_ _ _ _ _ _~:_ _ _ _ _ _ _ ___

CONY _______________-".

DRDY
BPIUP

---------~~~~~==~---~

STATE _ _ _ _ _S~ta_n_d_by~_ _ _ _ _~L-------~~------"~--~
i'

Figure 2. Conversion Timing (Not to Scale)

2-426

DS126F1

.._-_
.-._.-.
_
..--__
...

CS5504

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;
VA-

= -SV ± 10%;

Input Levels: Logic 0

= OV,

Logic 1

= VD+;

Parameter
Serial Clock
Serial Clock

Pulse Width High
Pulse Width Low

VA+, VD+
(Note 2)

= 5V± 10%;

Symbol

Min

Typ

Max

Units

fsclk

0

-

2.S

MHz

= SO pF.)

CL

tph
tpl

200
200

-

-

ns
ns

-

60

200

ns

CS Low to data valid (Note 1S)

tcsd

Maximum Delay Time:

(Note 16)
SCLK falling to new SDATA bit

tdd

-

1S0

310

ns

tfd1
tfd2

-

60
160

1S0
300

ns
ns

CS high to output Hi-Z (Note 17)
SCLK falling to Hi-Z

-

Notes: 1S. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To
guarantee proper clocking of SDATA when using asynchronous CS, SCLK should not be taken high
sooner than 2/fclk + 200 ns after CS goes low.
16. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.
17. If CS is retumed high before all data bits are output, the SDATA output will complete the current data
bit and then go to high impedance.

3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;
S%; VA-

= -SV ± 10%;

Input Levels: Logic 0

= OV,

Logic 1

= VD+;

Parameter
Serial Clock
Serial Clock

Pulse Width High
Pulse Width Low

CL

VA+

= SO pF.)

= sv ± 10%; VD+
(Note 2)

= 3.3V ±

Symbol

Min

Typ

Max

Units

fsclk

0

-

1.2S

MHz

tph
tpl

200
200

-

-

-

ns
ns

Access Time:

CS Low to data valid (Note 1S)

tcsd

-

100

200

ns

Maximum Delay Time:

(Note 16)
SCLK falling to new SDATA bit

tdd

-

400

600

ns

70
320

1S0
SOO

ns
ns

Output Float Delay:

DS126F1

CS high to output Hi-Z (Note 17)
SCLK falling to Hi-Z

tfd1
tfd2

-

il','1'
,

Access Time:

Output Float Delay:

_

2-427

. ..,-- ._.

*-'. . . . . .*-',..•
_ • •*-'. . . . .-

\~------------------------------------

DRDY
CS

SDATA(o) Hi-Z

CS5504

__

tc_sd_~_---1E

"_

MSB

---'x

MSS-.

J--_t_

fd_1_ _ _ _ __

SCLK(i)

\~------------~r_----------------~I
tcsd

~L-;C:-----------C C - - - - - - - - - - - - - - - + - -

SDATA(o) Hi-Z - - - - - - {'L-_ _ _

~L--~~\----J

SCLK(i)

Figure 3. Timing Relationships; Serial Data Read (Not to Scale)

2-428

DS126F1

-. .............._.-.
.,

~

~~-

CS5504

..,~

RECOMMENDED OPERATING CONDITIONS (DGND = OV)
Parameter
DC Power Supplies:
Positive Digital
(VA+) - (VA-)
Positive Analog
Negative Analog

Symbol

Min

Typ

Max

Units

VD+
Vdiff
VA+
VA-

3.15
4.5
4.5
0

5.0
10
5.0
-5.0

5.5
11
11
-5.5

V
V
V
V

1.0

2.5

3.6

V

0
-«VREF+)-(VREF-))

-

(VREF+)-(VREF-)
(VREF+)-(VREF-)

V
V

Analog Reference Voltage
(VREF+)(Note 19) (VREF-)
Analog Input Voltage: (Note 20)
Unipolar
Bipolar

(Note 18)

VAIN
VAIN

Notes: 18. All voltages with respect to ground.
19. The CS5504 can be operated with a reference voltage as low as 100 mV; but with a
corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference
may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-.
20. The CS5504 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar mode
the CS5504 will output all1's if the dc input magnitude «AIN+)-(AIN-)) exceeds «VREF+)-(VREF-))
and will output all O's if the input becomes more negative than 0 Volts. In bipolar mode the CS5504
will output all 1's if the dc input magnitude «AIN+)-(AIN-)) exceeds «VREF+)-(VREF-)) and will output
all O's if the input becomes more negative in magnitude than -«VREF+)-(VREF-)).

ABSOLUTE MAXIMUM RATINGS·
Parameter
DC Power Supplies:

Digital Ground
Positive Digital
Positive Analog
Negative Analog

Input Current, Any Pin Except Supplies

(Note 21)
(Note 22)

(Notes 23, 24)

Output Current
Power Dissipation (Total)
Analog Input Voltage

Symbol

Min

Typ

Max

Units

DGND
VD+
VA+
VA-

-0.3
-0.3
-0.3
+0.3

-

-

(VD+)-0.3
6.0 or VA+
12
-6.0

V
V
V
V

lin

-

-

±10

rnA

lout

-

-

±25

rnA

-

-

500

mW

(VA+)+0.3

V

(Note 25)
AIN and VREF pins

Digital Input Voltage
Ambient Operating Temperature

VINA

(VA-)-0.3

VIND

-0.3

TA

-40

(VD+)+0.3

V

85

°C

-

-65
150
Storage Temperature
°C
Tstg
..
Notes: 21. No pin should go more positive than (VA+)+0.3V .
22. VD+ must always be less than (VA+) +0.3V, and can never exceed +6.0 V.
23. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.
24. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ± 50 rnA.
25. Total power dissipation, including all input currents and output currents.

* WARNING:

DS126F1

Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

2-429

-

..-. ....
_...........
.........
~

~

..,.

GENERAL DESCRIPTION

The CS5504 is a low power, 20-bit, monolithic
CMOS AID converter designed specifically for
measurement of dc signals. The CS5504 includes a delta-sigma charge-balance converter, a
voltage reference, a calibration micro controller
with SRAM, a digital filter and a serial interface.
The CS5504 is optimized to operate from a
32.768 kHz crystal but can be driven by an external clock whose frequency is between 30 kHz
and 330 kHz. When the digital filter is operated
with a 32.768 kHz clock, the filter has zeros precisely at 50 and 60 Hz line frequencies and
multiples thereof.
TheCS5504 uses a "start convert" command to
latch the input channel selection and to start a
convolution cycle on the digital filter. Once the
filter cycle is completed, the output port is updated. When operated with a 32.768 kHz clock
the ADC converts and updates its output port at
20 samples/sec. The output port operates in a
synchronous externally-clocked interface format.

THEORY OF OPERATION

Basic Converter Operation

The CS5504 AID converter has three operating
states. These are stand-by, calibration, and conversion. When power is first applied, an internal
power-on reset delay of about 10 ms resets all of
the logic in the device. The oscillator must then
begin oscillating before the device can be considered functional. After the power-on reset is
applied, the device enters the wake-up period for
1800 clock cycles after clock is present. This allows the delta-sigma modulator and other
circuitry (which are operating wIth very low currents) to reach a stable bias condition prior to
entering into either the calibration or conversion
states. During the 1800 cycle wake-up period,
the device can accept an input command. Execu2-430

CS5504

tion of this command will not occur until the
complete wake-up period elapses. If no command is given, the device enters the standby
state.
Calibration

After the initial application of power, the
CS5504 must enter the calibration state prior to
performing accurate conversions. During calibration, the chip executes a two-step process. The
device first performs an offset calibration and
then follows this with a gain calibration. The
two calibration steps determine the zero reference point and the full scale reference point of
the converter's transfer function. From these
points it calibrates the zero point and a gain
slope to be used to properly scale the output
digital codes when doing conversions.
The calibration state is entered whenever the
CAL and CONY pins are high at the same time.
The state of the CAL and CONY pins at poweron are recognized as commands, but will not be
executed until the end of the 1800 clock cycle
wake-up period.
If CAL and CONY become active (high) during
the 1800 clock cycle wake-up time, the converter
will wait until the wake-up period elapses before
executing the calibration. If the wake-up time
has elapsed, the converter will be in the standby
mode waiting for instruction and will enter the
calibration cycle immediately if CAL and CONY
become active. The calibration lasts for 3246
clock cycles. Calibration coefficients are then
retained in the SRAM (static RAM) for use during conversion.
The states of AO and BPIUP are ignored during
calibration but should remain stable throughout
the calibration period to minimize noise.
When conversions are performed in unipolar
mode or in bipolar mode, the converter uses the
same calibration factors to compute the digital
DS126F1

. ..............._...,.

.., ..,. " . "
~

~~-

CS5504

output code. The only difference is that in bipolar mode the on-chip microcontroller offsets the
computed output word by a code value of
8000H. This means that the bipolar measurement range is not calibrated from full scale
positive to full scale negative. Instead it is calibrated from the bipolar zero scale point to full
scale positive. The slope factor is then extended
below bipolar zero to accommodate the negative
input signals. The converter can be used to convert both unipolar and bipolar signals by
changing the BP/uP pin. Recalibration is not required when switching between unipolar and
bipolar modes.

Conversion

At the end of the calibration cycle, the on-chip
micro controller checks the logic state of the
CONY signal. If the CONY input is low the device will enter the standby mode where it waits
for further instruction. If the CONY signal is
high at the end of the calibration cycle, the converter will enter the conversion state and perform
a conversion on the input channel. The CAL signal can be returned low any time after calibration
is initiated. CONY can also be returned low, but
it should never be taken low and then taken back
high until the calibration period has ended and
the converter is in the standby state. If CONY is
taken low and then high again with CAL high
while the converter is calibrating, the device will
interrupt the current calibration cycle and start a
new one. If CAL is taken low and CONY is
taken low and then high during calibration, the
calibration cycle will continue as the conversion
command is disregarded. The state of BPIUP is
not important during calibrations.

AO

If an "end of calibration" signal is desired, pulse

the CAL signal high while leaving the CONY
signal high continuously. Once the calibration is
completed, a conversion will be performed. At
the end of the conversion, DRDY will fall to indicate the first valid conversion after the
calibration has been completed.

The conversion state can be entered at the end of
the calibration cycle, or whenever the converter
is idle in the standby mode. If CONY is taken
high to initiate a calibration cycle ( CAL also
high), and remains high until the calibration cycle is completed (CAL is taken low after CONY
transitions high), the converter will begin a conversion upon completion of the calibration
period. The device will perform a conversion on
the input channel selected by AO when CONY
transitions high. Table I indicates the multiplexer channel selection truth table.
Channel Addressed
AIN1
1
AIN2
Table 1. Multiplexer Truth Table

0

The AO input is latched internal to the CS5504
when CONY rises. AO has internal pull-down
circuits which default the multiplexer to channel
AINI.
The BP/uP pin is not a latched input. The
BP/uP pin controls how the output word from
the digital filter is processed. In bipolar mode the
output word computed by the digital filter is offset by 80000H (see Understanding Converter
Calibration). BP/uP can be changed after a conversion is started as long as it is stable for 82
clock cycles of the conversion period prior to
DRDY falling. If one wishes to intermix measurement of bipolar and unipolar signals on
various input channels, it is best to switch the
BP/uP pin immediately after DRDY falls and
leave BP/uP stable until DRDY falls again.
The digital filter in the CS5504 has a Finite Impulse Response and is designed to settle to full
accuracy in one conversion time.
If CONY is left high, the CS5504 will perform

continuous conversions. The conversion time will
be 1622 clock cycles. If conversion is initiated
DS126F1

2-431

,.
I

....,..,_.
...,-.,.,-_._.
....
..,.., .....
from the standby state, there may be up to two
XIN clock cycles of uncertainty as to when conversion actually begins. This is because the
internal logic operates at one half the external
clock rate and the exact phase of the internal
clock may be 1800 out of phase relative to the
XIN clock. When a new conversion is initiated
from the standby state, it will take up to two
XIN clock cycles to begin. Actual conversion
will use 1624 clock cycles before DRDY goes
low to indicate that the serial port has been updated. See the Serial Interface Logic section of
the data sheet for information on reading data
from the serial port.
In the event the AID conversion command
(CONV going positive) is issued during the conversion state, the current conversion will be
terminated and a new conversion will be initiated.

Voltage Reference
The CS5504 uses a differential voltage reference
input. The positive input is VREF+ and the
negative input is VREF-. The voltage between
VREF+ and VREF- can range from 1 volt minimum to 3.6 volts maximum. The gain slope will
track changes in the reference without recalibration, accommodating ratiometric applications.

CS5504

as the maximum signal magnitude stays within
the supply voltages.
The AID converter is intended to measure dc or
low frequency inputs. It is designed to yield accurate conversions even with noise exceeding the
input voltage range as long as the spectral components of this noise will be filtered out by the
digital filter. For example, with a 3.0 volt reference in unipolar mode, the converter will
accurately convert an input dc signal up to
3.0 volts with up to 15% overrange for 60 Hz
noise. A 3.0 volt dc signal could have a 60 Hz
component which is 0.5 volts above the maximum input of 3.0 (3.5 volts peak; 3.0 volts dc
plus 0.5 volts peak noise) and still accurately
convert the input signal (XIN = 32.768 kHz).
This assumes that the signal plus noise amplitude stays within the supply voltages.
The CS5504 converters output data in binary format when converting unipolar signals and in
offset binary format when converting bipolar signals. Table 2 outlines the output coding for both
unipolar and bipolar measurement modes.
Unipolar Input
Voltage

Output
Codes

Bipolar Input
Voltage

>(VREF - 1.5 LSB)

FFFFF
FFFFF

>(VREF - 1.5 LSB)

VREF - 1.5 LSB

--

VREF- 1.5 LSB

FFFFE

Analog Input Range

80000

The analog input range is set by the magnitude
of the voltage between the VREF+ and VREFpins. In unipolar mode the input range will
equal the magnitude of the voltage reference. In
bipolar mode the input voltage range will equate
to plus and minus the magnitude of the voltage
reference. While the voltage reference can be as
great as 3.6 volts, its common mode voltage can
be any value as long as the reference inputs
VREF+ and VREF- stay within the supply voltages for the AID. The differential input voltage
can also have any common mode value as long
2-432

VREF/2 - 0.5 LSB

--

-0.5 LSB

7FFFF
00001
+ 0.5 LSB

--

-VREF + 0.5 LSB

00000
«+ 0.5 LSB)

00000

«VREF + 0.5 LSB)

Note: Table excludes common mode voltage on the
signal and reference inputs.

Table 2. Output Coding

DS126F1

.._-.-.......
..---...

CS5504

~

Converter Performance
The CS5504 AID converter has excellent linearity performance. Calibration minimizes the
errors in offset and gain. The CS5504 device
has no missing code performance to 20-bits.
The converter achieves Common Mode Rejection
(CMR) at dc of 105 dB typical, and CMR at 50
and 60 Hz of 120 dB typical.
The CS5504 can experience some drift as temperature changes. The CS5504 uses
chopper-stabilized techniques to minimize drift.
Measurement errors due to offset or gain drift
can be eliminated at any time by recalibrating
the converter.

Analog Input Impedance Considerations
The analog input of the CS5504 can be modeled
as illustrated in Figure 4 (the model ignores the
multiplexer switch resistance). Capacitors (15 pF
each) are used to dynamically sample each of the
inputs (AIN+ and AIN-). Every half XIN cycle
the switch alternately connects the capacitor to
the output of the buffer and then directly to the
AIN pin. Whenever the sample capacitor is
switched from the output of the buffer to the
AIN pin, a small packet of charge (a dynamic
demand of current) is required from the input
source to settle the voltage of the sample capaci-

AIN- o-------.----~

15 pF
Internal
}
Bias
Voltage'
15 pF

tor to its final value. The voltage on the output
of the buffer may differ up to 100 m V from the
actual input voltage due to the offset voltage of
the buffer. Timing allows one half of a XIN
clock cycle for the voltage on the sample capacitor to settle to its final value.
An equation for the maximum acceptable source
resistance is derived.

Rsmax

-I[

V

2XIN (I5pF + CEXT) In V + I5p;IOOmV)
e

1

(l5pF + CEXT )

This equation assumes that the offset voltage of
the buffer is 100 m V, which is the worst case.
The value of Ve is the maximum error voltage
which is acceptable. CEXT is the combination of
any external or stray capacitance.
For a maximum error voltage (Ve) of 600 nV in
the CS5504 (l/4LSB at 20-bits), the above equation indicates that when operating from a
32.768 kHz XIN, source resistances up to 84 ill
in the CS5504 are acceptable in the absence of
external capacitance (CEXT =0).
The VREF+ and VREF- inputs have nearly the
same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input impedance applies to the voltage reference inputs as
well.

Digital Filter Characteristics
The digital filter in the CS5504 is the combination of a comb filter and a low pass filter. The
comb filter has zeros in its transfer function
which are optimally placed to reject line interference frequencies (50 and 60 Hz and their
multiples) when the CSS504 is clocked at

Figure 4. Analog Input Model
DS126F1

2·433

i

~,,:,

r.IIII

.

""'_"'".."'"""''''''
...
....
.._.
..,,~-

..

CS5504

~

0
- ; - -: - -: - -: - -: X1' = 32.768kHz- :- : X2. = 330.qOkHz :

-20

Frequency
(Hz)

Notch
Depth
(dB)

50
60
100
120
150
180
200
240

125.6
126.7
145.7
136.0
118.4
132.9
102.5
108.4

-40

in

, ,

~ -60

- -,-

c
0

i::J

-80

fii -100

:i -120

~

:

:

, ,

-140

X1
X2

;

-, - , - , - -' - -, - -' - -' - -' - - '- - '- - '- - '- ,
' : XIN=32.768kHZ:
' ,
0
0

Frequency
(Hz)
50±1%
60+1%
100±1%
120±1%
150±1%
180±1%
200±1%
240±1%

Minimum
Attenuation
(dB)

55.5
58.4
62.2
68.4
74.9
87.9
94.0
104.4

40
80
120
160
200
240
402.83805.661208.51611.32014.22416.9

Frequency (Hz)

Figure 5. Filter Magnitude Plot to 260 Hz

Table 3. Filter Notch Attenuation (XIN = 32.768 kHz)
1 8 0 . - - - - - - -__-------~

-20
-40

- - ,- -

Flatness - , Frequency dB
1
-0.010
2
-0.041
3

c

i~

-60

4
5

-80

-120

-0.093 .
-0.166 ~ __ : ___ : __ ; __

~

__ : __

7

-0.259,
-0.374 '
-0.510 : - -:- - -: - - ~ - - : - -:- -

8

-0.667,

10
17

-0.846' _ - ,'- - -' - - : - - , - - ,'- -1.047
, XIN 32.768 kHz '
·3.093,

6

! -100

, - - ,- - -, - - - '
'
: - -: - - -: - - ~ - - : - -:-

=

-, - - -, - - ,- - - ,- - -, - - • - - ,- - - ,- - -

-140 +-----t---r------I--r-r----t---t----t---r-------I
o 5 10 15 20 25 30 35 40 45 50
Frequency (Hz)

I
j

-

--

-

-------------------

90

-

- '.

-

_' -

-

.' -

-

~

-

- '.

-

_, -

-

.' -

-

-

_, -

-

.'

-

~

-

-

-

_, -

-

.' -

_!

•

I

,

I

I

,

,

,

,

,

I

,

,

,

"

,

,

!

-

I

- - - -

I.

_

_

-

I.

_

_

45

~

a.

135

0

-

_' -

-

'.

-45
-90
XIN = 32.768 kHz
-135
-180 +-----t----.-->-----+--+----+--+-----+---+---1
o 5 10 15 20 25 30 35 40 45 50
Frequency (Hz)

Figure 6. Filter Magnitude Plot to 50 Hz

Figure 7. Filter Phase Plot to 50 Hz

32.768 kHz_ Figures 5, 6 and 7 illustrate the
magnitude and phase characteristics of the filter.
Figure 5 illustrates the filter attenuation from dc
to 260 Hz. At exactly 50, 60, 100, and 120 Hz
the filter provides over 120 dB of rejection. Table 3 indicates the filter attenuation for each of
the potential line interference frequencies when
the converter is operating with a 32.768 kHz
clock. The converter yields excellent attenuation

of these interference frequencies even if the fundamental line frequency should vary ± 1% from
its specified frequency.
The -3dB comer frequency of the filter when operating from a
32.768 kHz clock is 17 Hz. Figure 7 illustrates
that the phase characteristics of the filter are precisely linear phase.

2-434

DS126F1

......._-...
._.
-.-_..__
~

~

If the CS5504 is operated at a clock rate other

than 32.768 kHz, the filter characteristics, including the comb filter zeros, will scale with the
operating clock frequency. Therefore, optimum
rejection of line frequency interference will occur with the CS5504 running at 32.768 kHz.
Anti-Alias Considerations for Spectral
Measurement Applications

Input frequencies greater than one half the output word rate (CONV = 1) may be aliased by the
converter. To prevent this, input signals should
be limited in frequency to no greater than one
half the output word rate of the converter (when
CONY =1). Frequencies close to the modulator
sample rate (XINI2) and multiples thereof may
also be aliased. If the signal source includes
spectral components above one half the output
word rate (when CONY = 1) these components
should be removed by means of low-pass filtering prior to the AID input to prevent aliasing.
Spectral components greater than one half the
output word rate on the VREF inputs (VREF+
and VREF-) may also be aliased. Filtering of the
reference voltage to remove these spectral components from the reference voltage is desirable.
Crystal Oscillator

The CS5504 is designed to be operated using a
32.768 kHz "tuning fork" type crystal. One end
of the crystal should be connected to the XIN
input. The other end should be attached to
XOUT. Short lead lengths should be used to
minimize stray capacitance.
Over the industrial temperature range (-40 to
+85 0c) the on-chip gate oscillator will oscillate
with other crystals in the range of 30 kHz to 53
kHz. The chip will operate with external clock
frequencies from 30 kHz to 330 kHz over the industrial temperature range. The 32.768 kHz
crystal is normally specified as a time-keeping
crystal with tight specifications for both initial
DS126F1

CS5504

frequency and for drift over temperature. To
maintain excellent frequency stability, these crystals are specified only over limited operating
temperature ranges (i.e. -10 °C to +60 0c) by the
manufacturers. Applications of these crystals
with the CS5504 does not require tight initial
tolerance or low tempco drift. Therefore, a lower
cost crystal with looser initial tolerance and tempco will generally be adequate for use with the
CS5504. Also check with the manufacturer about
wide temperature range application of their
standard crystals. Generally, even those crystals
specified for limited temperature range will operate over much larger ranges if frequency stability
over temperature is not a requirement. The frequency stability can be as bad as ±3000 ppm
over the operating temperature range and still be
typically better than the line frequency (50 Hz or
60 Hz) stability over cycle-to-cycle during the
course of a day.
Serial Interface Logic

The digital filter in the CS5504 takes 1624 clock
cycles to compute an output word once a conversion begins. At the end of the conversion cycle,
the filter will attempt to update the serial port.
Two clock cycles prior to the update DRDY will
go high. When DRDY goes high just prior to a
port update it checks t~ee if the port is either
empty or unselected (CS = 1). If the port is
empty or un selected, the digital filter will update
the port with a new output word. When new data
is put into the port DRDY will go low.
Reading Serial Data

SDATA is the output pin for the serial data.
When CS goes low after new data becomes
available (DRDY goes low), the SDATA pin
comes out of Hi-Z with the MSB data bit present. SCLK is the input pin for the serial clock.
If the MSB data bit is on the SDATA pin, the
first rising edge of SCLK enables the shifting
mechanism. This allows the falling edges of
2-435

......

~

..,..,
...
.-..,.........
__
...
..,.., ...SCLK to. shift subsequent data bits out of the
port. Note that if the MSB data bit is output and
the SCLK signal is high, the first falling edge of
SCLK will be ignored because the shifting
mechanism has not become activated. After the
first rising edge of SCLK, each subsequent falling edge will shift out the serial data. Once the
LSB is present,· the falling edge of SCLK will
cause the SDATA output to go to Hi-Z and
DRDY to return high. The serial port register
will be updated with a new data word upon the
completion of another conversion if the serial
port has been emptied, or if the CS is inactive
(high).
CS can be operated asynchronously to the
DRDY signal. The DRDY signal need not be
monitored as long as the CS signal is taken low
for at least two XIN clock cycles plus 200 ns
prior to SCLK being toggled. This ensures that
CS has gained control over the serial port.

Power Supplies and Grounding
The analog and digital supply pins to the
CS5504 are brought out on separate pins to
minimize noise coupling between the analog and
digital sections of the chip. Note that there is no
analog ground pin. No analog ground pin is required because the inputs for measurement and
for the voltage reference are differential and require no ground. In the digital section of the
chip the supply current flows into the VD+ pin
and out of the DGND pin. As a CMOS device,
the CS5504 requires that the supply voltage on
the VA+ pin always be more positive than the
voltage on any other pin of the device. If this
requirement is not met, the device can latch-up
or be damaged. In all circumstances the VA+
voltage must remain more positive than the VD+
or DGND pins; VD+ must remain more positive
than the DGND pin.

CS5504

=

VA+ = +SV to +10V, VA- ov,
VA+ = +sv,
VA- = -sv.
VA+ = +SV,
VA- = OV to -sv,

VD+= +SV
VD+ = +SV
VD+ = +3.3V

The CS5504 cannot be operated with a 3.3V
digital supply if VA+ is greater than +5.5v'
Figure 8 illustrates the System Connection Diagram for the CS5504 using a single +5V supply.
Note that all supply pins are bypassed with
0.1 /IF capacitors and that the VD+ digital supply is derived from the VA+ supply.
Figure 9 illustrates the CS5504 using dual supplies of +5 and -5V.
Figure 10 illustrates the CS5504 using dual supplies of + lOV analog and +5V digital.
When using separate supplies for VA+ and VD+,
VA+ must be established first. VD+ should
never become more positive than VA+ under any
operating condition. Remember to investigate
transient power-up conditions, when one power
supply may have a faster rise time.

The following power supply options are possible:
2-436

DS126F1

..............
..,,-- ._...
.........

CS5504

~

100
O~------------~-.---------~~~V'V~~~------.

+5V
Analog

0.1 jl.F

Supply

~

Calibration
Control

"I _

_
O~
14
VA+

f-_-,-4~CAL
XIN

Bipolar!
Unipolar
Input Select

7

-

I----~BPIUP

XOUT

cis

- -

Optional
Clock
Source

~ 32.768 kHz

SCLK ~1=-B____--1

0 -______________----'1-=-0~AIN1-

SDATA

o----------9~AIN2+
0 -______________----'1-'-1~AIN2-

DRDY
'Unused analog inputs should
be tied to signal ground

CS

r-----~+l-------------J1~2~VREF+
Voltage
Reference

~-

CS5504

o----------=-8~AIN1+
Analog'
Signal
Sources

T

17
VD+

AO

r-------------'1-=-3~VREF.

CONY

VA-

1

15

DGND

Serial
Data
Interface

19

20
2
Control
Logic

1
3

16

l

-=-

Unused Logic
inputs must be
connected to
VD+orDGND

Figure 8. CS5504 System Connection Diagram Using Single Supply

DS126F1

2~437

_..........
..............
..,-._..

..,

CS5504

~

10n
A.
V'

+5V
Analog
Supply

14

17

VA+
Calibration
Control

VD+

r----4~CAL
XIN

Bipolar!
Unipolar
Input Select

-

XOUT

9
11

SCLK

AIN1+
AIN1-

SDATA

AIN2+
AIN2-

DRDY

'Unused analog inputs should
be tied to signal ground

-f?

Analog
Supply

CS
12
13

-

O~

T

Optional
Clock
Source

I

~ 32.768 kHz

CS5504

10

Analog'
Signal
Sources

Voltage
Reference

ck

I
7

f--~BP!UP

8

+

h- --

VREF+

AO

VREF-

CONY

VA15
1

DGND

18

19

Serial
Data
Interface

20
2
1

Control
Logic

3
16
Unused Logic
inputs must be
connected to
VD+orDGND

Figure 9. CSSS04 System Connection Diagram Using Dual Supplies

2-438

DS126F1

.........
.......
_.-.
_............
.-

.",

CS5504

Note: VD+ should never be more positive than VA+

O~

+10V
Analog
Supply

O~
114

~
4

Calibration
Control

117

VA+

VD+

CAL
XIN

Bipolarl
Unipolar
Input Select

7

BP/UP

XOUT

10

Analog'
Signal
Sources

9
11

SCLK

AIN1+
AIN1-

SDATA

AIN2+
AIN2-

DRDY

'Unused analog inputs should
be tied to signal ground

-

Optional
Clock
Source

~--

~ 32.768 kHz

I

CS5504
8

+
Voltage
Reference

~

+5V
Digital
Supply

CS
12
13

VREF+

AO

VREF-

CONY

VA-

1

15

DGND

18
Serial
Data
Interface

19

20

2
Control
Logic

1
3
16

I

=

Unused Logic
inputs must be
connected to
VD+or DGND

Figure 10. CS5504 System Connection Diagram Using Dual Supply,
+10V Analog, +5V Digital

Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your

DS126F1

2-439

...............
._.
.........

.., ~---

CS5504

."

PIN DESCRIPTIONS*
MULTIPLEXER SELECTION INPUT

AO

DRDY

DATA READY

CHIP SELECT

CS

SDATA

SERIAL DATA OUTPUT

CONVERT

CONV

SCLK

SERIAL CLOCK INPUT

CALIBRATE

CAL

CRYSTAL IN

XIN

VD+

POSITIVE DIGITAL POWER

DGND

DIGITAL GROUND

CRYSTAL OUT

XOUT

VA-

NEGATIVE ANALOG POWER

BIPOLAR/UNIPOLAR

BPIUP

VA+

POSITIVE ANALOG POWER

DIFFERENTIAL ANALOG INPUT

AIN1+

VREF-

VOLTAGE REFERENCE INPUT

DIFFERENTIAL ANALOG INPUT

AIN2+

VREF+

VOLTAGE REFERENCE INPUT

DIFFERENTIAL ANALOG INPUT

AIN1-

AIN2-

DIFFERENTIAL ANALOG INPUT

'Pinout applies to both PDIP and SOIC

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 5, 6.
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).
Serial Output 110

CS - Chip Select, Pin 2.
This input allows an external device to access the serial port.
DRDY - Data Ready, Pin 20.
Data Ready goes 10'Y at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).
SDATA - Serial Data Output, Pin 19.
SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK. Data is output MSB first and advances to the next data bit on the falling
edges of SCLK. SDATA will be in a high impedance state when not transmitting data.
SCLK - Serial Clock Input, Pin 18.
A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin
must not be allowed to float.
2-440

DS126F1

..... -_-...
._.
-.-......__
..,

CS5504

Control Input Pins
CAL - Calibrate, Pin 4.
When taken high the same time that the CONY pin is taken high the converter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.

.,
I

CONY - Convert, Pin 3.
The CONY pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If CONY
is held high (CAL low) the converter will do continuous conversions.
BP/uP - Bipolar/Unipolar, Pin 7.
The BP/uP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.

AO

-~ultJplexer Selection Input, Pin 1.

Selects the input channel for conversion. AO=O=AINl. AO is latched when CONY transitions
from low to high. This input has a pull-down resistor internal to the chip.

Measurement and Reference Inputs
AINl+, AIN2+, AINI-, AIN2- - Differential Analog Inputs, Pins 8, 9,10,11.
Analog differential inputs to the delta-sigma modulator.
VREF +, VREF - - Differential Voltage Reference Inputs, Pins 12, 13.
A differential voltage reference on these pins operates as the voltage reference for the converter.
The voltage between these pins can be any voltage between 1.0 and 3.6 volts.

Power Supply Connections
VA+ - Positive Analog Power, Pin 14.
Positive analog supply voltage. Nominally +5 volts.
VA- - Negative Analog Power, Pin 15.
Negative analog supply voltage. Nominally -5volts.
VD+ - Positive Digital Power, Pin 17.
Positive digital supply voltage. Nominally +5 volts or +3.3 volts.
DGND - Digital Ground, Pin 16.
Digital Ground.

DS126F1

2-441

...............
..,-- ._.
.............

CS5504

SPECIFICATION DEFINITIONS
Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the AID
Converter transfer function. One endpoint is located 112 LSB below the first code transition
and the other endpoint is located 112 LSB beyond the code transition to all ones. Units in
percent of full-scale.
Differential Nonlinearity
The deviation of a code's width from the ideal width. Units in LSBs.
Full Scale Error
The deviation of the last code transition from the ideal [{ (VREF+) - (VREF-)} are in LSBs.

3;z LSB]. Units

Unipolar Offset
The deviation of the first code transition from the ideal (1;2 LSB above the voltage on the AINpin.) when in unipolar mode (BP/uP low). Units are in LSBs.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100... 000) from the ideal (1;2 LSB below
the voltage on the AIN- pin.) when in bipolar mode (BPIUP high). Units are in LSBs

2-442

DS126F1

......,
... .. ...
._.
~.-

~

~~

~--~~

CS5504

APPENDIX
The following companies provide 32.768 kHz crystals in many package varieties and temperature
ranges.
Fox Electronics
5570 Enterprise Parkway
Fort Meyers, FL 33905
(813) 693-0099
Micro Crystal Division / SMH
702 West Algonquin Road
Arlington Heights, IL 60005
(708) 806-1485
SaRonix
4010 Transport Street
Palo Alto, California 94303
(415) 856-6900
Statek
512 North Main
Orange, California 92668
(714) 639-7810
IQD Ltd.
North Street
Crewkerne
Somerset TA18 7AK
England
0146077155

Taiwan X'tal Corp.
5F. No. 16, Sec 2, Chung Yang S. RD.
Reitou, Taipei, Taiwan R. o. C.
Tel: 02-894-1202
Fax: 02-895-6207
Interquip Limited
241F Million Fortune Industrial Centre

34-36 Chai Wan Kok Street, Tsuen Wan N T
Tel: 4135515
Fax: 4137053
S& T Enterprises, Ltd.
Rm404 Blk B
Sea View Estate
North Point, Hong Kong
Tel: 5784921
Fax: 8073126
Mr. Darren Mcleod
Hy-Q International Pty. Ltd.
12 Rosella Road,
FRANKSON,3199
Victoria, Australia
Tel: 61-3-783 9611
Fax: 61-3-783 9703

Mr. Pierre Hersberger
MicrocrystallDIV. ETA S.A.
Schild-Rust-Strasse 17
Grenchen CH-2540
Switzerland
065530557

DS126F1

2-443

.. ....,..
...,...........
~~

~~~

~~

CDB5504

Semiconductor Corporation

Evaluation Board for CS5504 AID Converter
Features

General Description

• Operation with on-board 32.768 kHz

The COB5504 is a circuit board designed to provide
quick evaluation of the C85504 AlO converter.

crystal or off-board clock source

The board provides buffered digital signals, an onboard precision voltage reference, options for using an
external clock, and a momentary switch to initiate calibration.

• DIP Switch Selectable:
BP/UP mode; Channel selection

• On-board precision voltage reference

• Access to all digital control pins

ORDERING INFORMATION:

C85504

B
U

F
F
E
R

8

COB5504

H

E
A

o
E
R

ClKIN

=~

VREF

+5V GND -5V
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760

(512) 445 7222 FAX; (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
081260B1

2-444

___-_

.. ..._.-.
.-_
..-......

.."

CDB5504

Introduction
The CDB5504 evaluation board provides a quick
means of testing the CSSS04 AID converter. The
CS5S04 converter require a minimal amount of
external circuitry. The evaluation board comes
configured with the AID converter chip operating from a 32.768 kHz crystal and with an
off-chip precision 2.5 volt reference. The board
provides access to all ofthe digital interface pins
of the CSSS04 chip.
The board is configured for operation from +5
and -S volt power supplies, but can be operated
from a single +5 volt supply if the -SV binding
post is shorted to the GND binding post.

Evaluation Board Overview
The board provides a complete means of making
the CS5504 AID converter chip function. The
user must provide a means of taking the output
data from the board in serial format and using it
in his system.
Figure 1 illustrates the schematic for the board.
The board comes configured for the AID converter chip to operate from the 32.768 kHz
watch crystal. A BNC connector for an external
clock is provided on the board. To connect the
external BNC source to the converter chip, a circuit trace must be cut. Then a jumper must be
inserted in the proper holes to connect the XIN
pin of the converter to the input line from the
BNC. The BNC input is terminated with a son
resistor. Remove this resistor if driving from a
logic gate. See the schematic in Figure 1.
The board comes with the AID converter VREF+
and VREF- pins hard-wired to the 2.S volt
bandgap voltage reference IC on the board.
All of the control pins of the CSSS04 are available at the 11 header connector. Buffer ICs U2
and U3 are used to buffer the converter for interOS126081

face to off-board circuits. The buffers are used
on the evaluation board only because the exact
loading and off-board circuitry is unknown.
Most applications will not require the buffer ICs
for proper operation.
To put the board in operation, select either bipolar or unipolar mode with DIP switch S2. Then
press the CAL pushbutton after the board is
powered up. This initiates calibration of the converter which is required before measurements
can be taken.
To select an input, one of two channels, use DIP
switch S2 to select the input for AO (see Table 1). Once AO is selected, the CONY switch
(S2-3) must be switched on (closed) and then
open to cause the CONY signal to transition low
to high. This latches the AO channel selection
into the converter. With CONY high (S2-3 open)
the converter will convert continuously.
Figure 3 illustrates the CABS504 adapter board.
The CABSS04 translates a CS550S pinout to a
CSS504 pinout.
Figures 4 and S illustrate the evaluation board
layout while Figure 6 illustrates the component
placement (silkscreen) of the evaluation board.

AO

Channel Addressed

0

AIN1
AIN2

1

Table 1. Multiplexer Truth Table

2-445

i

+5f-11M.'

:1<':70.1 I1F
~

+sl
+SV

(tjJ

,

•

•

•

6

VA+

•

CAL

.-S

II'

Rll
lOOk

VD+

DGND

lA

-SV©

•

+S

r-----+ AGND
GND (())

lfu~' II

..-

T 'M

•

14

•

"'7

II'

R17
,..--JIM--j VD+

\lnL

R27
lK

47k

12
~VREF+

161 _ !~. ~lOnF 13
ct:: 020 I VREF-

CS

12

l;

"d

AO

I'

•

°c

~10nF

U1

C85504

_ 0

0

_36

AIN2- ~__

AIN2+

)~__

AIN1-

~~<

AIN1+

~_.

l;'

--r

"1 AIN2-

• 91

AIN2+

• lUI

AIN1-

, • 81

AIN1+

SDATA

SClK

1'-",
1'U. ..

'~I

.-51

6P/UP~
Jl
U2 74HC40SO
U3 74HC125
Al

AO

I

ClKIN

I

I~I~~~

(')

C

OJ

Note: Buffers not required for general applications.

...c
~
...

~

(J)

C
ID

~
o

Figure 1. ADC Connections

.. .....
...
. ..__
._.
....
~.-

~~

CDB5504

~~

AO

OROY

CS

SOATA

CONY
CAL
XIN

l1li

SCLK
VO+
OGNO

XOUT

VA·

BP/UP

VA+

AIN1+

VREF·

AIN2+

VREF+

AIN1·

AIN2·

Figure 2. CS5504 Pin Layout

Figure 3. CAB5504 Adapter Board

OS1260B1

2-447

....,..,,,,..
...,-..,..,
...-..
.....
...

--_

CDB5504

Figure 4. Top Ground Plane Layer (NOT TO SCALE)

2-448

05126081

_____

....
. .... .....
._.
....
-~-

CDB5504

••••••••••

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Figure 5. Bottom Trace Layer (NOT TO SCALE)

D5126D81

••
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% •

•

•
2-449

,..

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c
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CRYSTAL

CCDB5504

SMART An%g@

Evaluation cx,ard

f'\~.
J..VCC~-========______________________
______-========
~ "" lJ;c;: ;~"" ~NO." ~~~O=======
___
Saml conductor Corporat Ion

Eo<

00

TPI4

R27

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CB
AU

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.............
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.............

CS5505
CS5507

Semiconductor Corporation

CS5506
CS5508

Very Low Power, 16-8;' and 20-8;' AID Converters
Features

General Description
The CSS50S/6/7/8 are a family of low power CMOS
AID converters which are ideal for measuring lowfrequency signals representing physical, chemical,
and biological processes.

• Very Low Power Consumption
Single supply +5V operation: 1.7 mW
Dual supply ±5V operation: 3.2 mW

The CS5507/8 have single-channel differential analog and reference inputs while the CSSSOS/6 have
four pseudo-differential analog input channels. The
CS5S0S/7 have a 16-bit output word. The CSSS06/8
have a 20-bit output word. The CSSSOS/6/7/8 sample upon command up to 100 output updates per
second.

• Offers superior performance to VFCs
and multi-slope integrating ADCs
• Differential Inputs
Single Channel (CS5507/8) and
Four-Channel (CS5505/S)
pseudo-differential versions

The on-chip digital filter offers superior line rejection
at 50 and 60Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Hz.).

• Either 5V or 3.3V Digital Interface

The CS5505/6/7/8 include on-chip self-calibration
Circuitry which can be initiated at any time or temperature to ensure minimum offset and full-scale
errors.

• Linearity Error:
±O.0015% FS (1S-bit CS5505/7)
±O.0007% FS (20-bit CS550S/8)

The CS5S0S/6/7/8 serial port offers two generalpurpose modes for the direct interface to shift
registers or synchronous serial ports of industrystandard microcontrollers.

• Output update rates up to 100/second
• Flexible Serial Port
• Pin-Selectable Unipolar/Bipolar Ranges

VREFOUT

16

I Voltage Reference

•

14
15

VREF+
VREFAIN1+ ~
AIN2+ ~Q.
AIN3+ ~
AIN4+ ~
AIN-

M
U
X

r--f-----

Differential
4th order
delta-sigma
modulator

VA+ VA-

VD+ DGND

17

20

18

---

19

Page 2-480

Serial
Interface
Logic

2
23
21
22

CS
DRDY
SCLK
SDATA

ICalibration I

Digital
Filter

SRAM
;
7

M/SLP
7
CAL
1----- Calibration ILC :=t:

r---11.

BP/UP

T
1 24

AO A1

I

ORDERING INFORMATION:

13
CONV
CS5505 (16-bit) and CS5506 (20-bit) Shown

IOSC
6
15
XIN XOUT

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '9S
DSS9F4
2-451

,..,--

...- .........
.....
.............

CS5505/snts

ANALOG CHARACTERISTICS (TA =TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10o/~; VD+ =
3.3V ± 5%; VREF+ = 2.5V(extemal); VREF- = OV; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kn with a 10nF
to AGND at AIN; Analog input channel AIN1 +; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)
CS5505n-A
Parameter*

Min

Specified Temperature Range

Typ

CS5507-S
Max

Min

-40 to +85

Typ

Units

Max

-55 to +125

°C

Accuracy
Linearity Error

-

Differential Nonlinearity

-

Full Scale Error

(Note 3)

Full Scale Drift

(Note 4)

Unipolar Offset

(Note 3)

Unipolar Offset Drift

(Note 4)

Bipolar Offset

(Note 3)

Bipolar Offset Drift

(Note 4)

0.003

-

0.0015

0.003

±%FS

±O.25

±O.5

±O.25

±O.5

LSB16

±O.25

±2

±O.5

±2

LSB16

±O.5

-

±2

-

LSB16

±1

±4

LSB16

±1

-

LSB16

±2

LSB16

-

-

Noise (Referred to Output)
Notes:

0.0015

±O.5

±2

±0.5

-

-

±O.25

±1

-

±O.5

±O.25

-

-

±O.5

-

LSB16

0.16

-

-

0.16

-

LSBrmS16

1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the
master clock frequency. Both source resistance and shunt capacitance are therefore critical in
determining the CS5505/6n/8's source impedance requirements. For more information refer to the
text section Analog Input Impedance Considerations.
2. Specifications guaranteed by design, characterization and/or test.
3. Applies after calibration at the temperature of interest.
4. Total drift over the specified temperature range since calibration at power-up at 25°C.
Recalibration at any temperature will remove these errors.

Unipolar Mode

Bipolar Mode

mV

LSB's

%FS

ppm FS

LSB's

% FS

ppm FS

10

0.26

0.0004

4

0.13

0.0002

2

19

0.50

0.0008

8

0.26

0.0004

4

38

1.00

0.0015

15

0.50

0.0008

8

76

2.00

0.0030

30

1.00

0.0015

15

152

4.00

0.0061

61

2.00

0.0030

30

VREF = 2.5V

csssosn; 16-Bit Unit Conversion Factors

• Refer to the Specification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.
2-452

DS59F4

CS5505/SnlS

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+
3.3V ± 5%; VREF+ = 2.5V (extemal); VREF- = OV; felK = 32.768kHz; Bipolar Mode; Rsource = 1kQ with a
10nF to AGND at AIN; Analog input channel AIN1 +; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)
CS5508-S

CS5506/8-B

Min

Parameter"

Specified Temperature Range

Typ

=

Max

Min

-40 to +85

Typ

Max

Units

-55 to +125

°C

Accuracy

Linearity Error
Differential Nonlinearity
(No Missing Codes)
Full Scale Error

(Note 3)

Full Scale Drift

(Note 4)

Unipolar Offset

(Note 3)

Unipolar Offset Drift

(Note 4)

Bipolar Offset

(Note 3)

Bipolar Offset Drift

(Note 4)

-

0.0007

0.0015

-

0.0015

0.003

20

-

-

20

-

-

-

±4

±32

±8

-

±8

±32

±8

-

-

±4

±16

-

±4

-

-

-

Noise (Referred to Output)

2.6

Unipolar Mode

mV

LSB's

0.596

0.25

1.192
2.384
4.768

0.50
1.00

9.537

2.00
4.00

% FS
0.0000238
0.0000477
0.0000954
0.0001907
0.0003814

±%FS
Bits

±8

±32

LSB20

±32

-

LSB20

±16

±64

LSB20

±16

-

LSB20

±8

±32

LSB20

±8

-

LSB20

2.6

-

LSBrmS20

Bipolar Mode

ppm FS

lSB's

% FS

0.24

0.13
0.26

0.0000119

0.12
0.24

0.47
0.95

0.50

0.0000238
0.0000477

1.91
3.81

1.00
2.00

0.0000954
0.0001907

ppm FS

0.47
0.95
1.91

VREF = 2.5V

CS5506J8; 20-Bit Unit Conversion Factors

DYNAMIC CHARACTERISTICS
Parameter

Modulator Sampling Frequency
Output Update Rate (CONV = 1)
Filter Comer Frequency
Settling Time to 1/2 LSB (FS Step)

DS59F4

Symbol

Ratio

Units

fs

fClld2

Hz

fout
f-3dB

fclld1622
fclkl1928

Hz
Hz

Is

1/fout

s

2-453

-

,

....
-.-..-...,.,.-.-.
....
-.-. ...

CS5505/6nJS

ANALOG CHARACTERISTICS (TA =TMIN to TMAX; VA+ = 5V± 10%; VA- = -5V ± 10%; VD+
3.3V ± 5%; VREF+ = 2.5V (external); VREF- = OV; felK = 32.768kHz; Bipolar Mode; Rsource = 1kn with a
10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)
CS5505n-A
CS550618-8
Parameter*

Min

Specified Temperature Range

Typ

=

CS5507/8-S
Max

Min

Typ

Max

Units

-40 to +85

-55 to +125

°C

o to +2.5

o to +2.5

±2.5

±2.5

Volts
Volts

Analog Input

Analog Input Range:
(VAIN+)-(VAIN-)

Unipolar
Bipolar
(Note 5)

Common Mode Rejection:

de
50, 60 Hz (Note 6)

Off Channel Isolation
Input Capacitance
(Note 1)

DC Bias Current

-

105

120

-

-

120
15
5

-

120

-

-

-

120

-

-

dB
dB

(VA+)-2.5

-

Volts

-

4.0

%

60

-

ppm/oC
mVNolt

105

15
5

dB
pF
nA

Voltage Reference (Output)

VREFOUT Voltage

-

(VA+)-2.5

-

VREFOUT Voltage Tolerance

-

-

4.0

VREFOUT Voltage Temperature Coefficient

-

60

VREFOUT Line Regulation

-

1.5

-

-

VREFOUT Output Voltage Noise
0.1 to 10 Hz

-

50

-

-

50

-

IlVp-p

-

-

3
50

-

-

3
50

IlA
IlA

-

340
300
40

450

-

340
300
40

450

-

IlA
IlA
IlA

-

3.2
5

4.5
10

3.2
10

4.5
25

mW
IlW

80
80

-

-

80
80

-

dB
dB

VREFOUT:

Source Current
Sink Current

1.5

Power Supplies

DC Power Supply Currents:

Power Dissipation:

ITotal
IAnalog
IDigital

(Note 7)
SLEEP inactive
SLEEP active

Power Supply Rejection: Positive Supplies
Negative Supplies
Notes:

2-454

-

-

-

5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and
VA- supply voltages.
6. XIN = 32.768 kHz. Guaranteed by design and I or characterization.
7. All outputs unloaded. All inputs CMOS levels. SLEEP mode controlled by M/SLP pin.
SLEEP active = M/SLP pin at (VD+)/2 input level.

DS59F4

.

............_.
.............

.

~

~--

CS5505/6n18

5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX;

VA+VD+ = 5V ± 10%; VA-= -5V ± 10%;
DGND = 0.) All measurements below are performed under static conditions. (Note 2)

Symbol

Min

Typ

Max

Units

XIN
M/SLP
All Pins Except XIN and M/SLP

VIH
VIH
VIH

3.5
0.9VD+
2.0

-

V
V
V

XIN
M/SLP
All Pins Except XIN and M/SLP

VIL
VIL
VIL

-

-

-

-

V
V
V

Parameter
High-Level Input Voltage:

-

-

1.5
0.1VD+
0.8

M/SLP SLEEP Active Threshold

(Note 8)

VSLP

0.45VD+

0.5VD+

0.55VD+

V

High-Level Output Voltage

(Note 9)

VOH

(VD+)-1.0

-

-

V

VOL

-

-

0.4

V

Input Leakage Current

lin

-

1

10

itA

3-State Leakage Current

loz

-

±10

itA

Digital Output Pin Capacitance

Cout

-

9

-

pF

Low-Level Input Voltage:

Low Level Output Voltage

Notes:

lout = 1.6 mA

8. Under normal operation this pin should be tied to VD+ or DGND. Anytime the voltage on the M/SLP
pin enters the SLEEP active threshold range the device will enter the power down condition. Returning
to the active state requires elapse of the power-on reset period, the oscillator to start-up, and elapse
of the wake-up period.
9. lout = -100 ItA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ lout = -40 itA).

3.3V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V±10%; VD+ = 3.3V±5%;
VA-= -5V ± 10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2)
Parameter
High-Level Input Voltage:

XIN
M/SLP
All Pins Except XIN and M/SLP

Low-Level Input Voltage:

XIN
M/SLP
All Pins Except XIN and M/SLP

M/SLP SLEEP Active Threshold

(Note 8)

Symbol

Min

Typ

Max

Units

VIH
VIH
VIH

0.7VD+
0.9VD+
0.6VD+

-

-

-

-

V
V
V

VIL
VIL
VIL

-

-

0.3VD+
0.1VD+
0.16VD+

V
V
V

VSLP

0.43VD+ 0.45VD+ 0.47VD+

V

VOH

(VD+)-0.3

-

-

-

V

VOL

-

-

0.3

V

Input Leakage Current

lin

-

1

10

itA

3-State Leakage Current

IOZ

-

±10

itA

Digital Output Pin Capacitance

Cout

-

9

-

pF

High-Level Output Voltage
Low Level Output Voltage

DS59F4

ItA
lout = 400 ItA
lout = -400

2-455

.i

I

.. ..._.-.
.-....,.....
~.-

~~~

CS5505/~m8

~~

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;

VA+, VD+ = 5V ± 10%;
VA- = -5V ± 10%; Input Levels: Logic 0 = OV, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Internal Oscillator:

Master Clock Frequency:

-A,B
-S

External Clock:

Symbol

Min

Typ

Max

Units

XIN
or
felk

30.0
30.0
30

32.768
32.768

53.0
34.0
163

kHz
kHz
kHz

60

%

Master Clock Duty Cycle

40

Rise Times:
Fall Times:

Any Digital Input
Any Digital Output

(Note 10)

Any Digital Input
Any Digital Output

(Note 10)

trise
tlall

-

-

-

1.0

50

-

Ils
ns

-

1.0

20

-

Ils
ns

10

Start-Up
(Note 11)

tres
tesu

-

500

-

ms

(Note 12)
(Note 13)

twup

-

1800/felk

-

s

(Note 14)

tecw

100

-

ns

CONV and CAL High to Start of Calibration

tsel

21felk+200

ns

Start of Calibration to End of Calibration

teal

-

3246/felk

-

s

Power-On Reset Period
Oscillator Start-up Time

XTAL=32.768 kHz

Wake-up Period

ms

Calibration
CONV Pulse Width (CAL = 1)

Conversion
Set Up Time

AO, A 1 to CONV High

tsae

50

-

-

ns

Hold Time

AO, A 1 after CONV High

thea

100

-

-

ns

CONV Pulse Width

tepw

100

-

-

ns

CONV High to Start of Conversion

tsen

-

-

2!felk+200

ns

Set Up Time

BP/UP stable prior to DRDY falling

tbus

821felk

tbuh

0

teen

-

1624/felk

-

s

BP/UP stable after DRDY falls

-

Hold Time

Start of Conversion to End of Conversion

(Note 15)

ns
s

Notes: 10. Specified using 10% and 90% points on waveform of interest.
11. An internal power-on-reset is activated whenever power is applied to the device, or when coming out
of a SLEEP state.
12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
13. The wake-up period begins once the oscillator starts;
or when using an external fclk, after the power-on reset time elapses.
14. Calibration can also be initiated by pulsing CAL high while CONV=1.
15. Conversion time will be 16221fc lk if CONV remains high continuously.

2·456

DS59F4

...............
...... _............
.."

CS5505/SnJS

3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX VA+ = 5V ± 10%;
VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = OV, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Master Clock Frequency:

-A,B
-S

Internal Oscillator:
External Clock:

Symbol

Min

Typ

Max

Units

XIN
or
fclk

30.0
30.0
30

32.768
32.768

53.0
34.0
163

kHz
kHz
kHz

40

Master Clock Duty Cycle
Rise Times:
Fall Times:

Any Digital Input
Any Digital Output

(Note 10)

Any Digital Input
Any Digital Output

(Note 10)

trise
tfall

-

60

%

1.0

Ils
ns

-

50

-

-

-

1.0

20

-

Ils
ns

10

-

ms

-

ms

Start-Up
Power-On Reset Period
Oscillator Start-up Time

XTAL=32.768 kHz

Wake-up Period

(Note 11)

tres

-

(Note 12)

tosu

-

500

(Note 13)

twup

-

1800/fclk

(Note 14)

s

Calibration
tccw

100

-

-

ns

CONY and CAL High to Start of Calibration

tsel

-

2Ifclk+200

ns

Start of Calibration to End of Calibration

tcal

-

3246/fclk

-

s

tsac

50

-

-

ns

CONY Pulse Width (CAL = 1)

Conversion
Set Up Time

AO, A1 to CONY High

Hold Time

AO, A 1 after CONY High

CONY Pulse Width

Hold Time

-

-

ns

100

-

-

ns

2Ifclk+200

ns

-

ns

tscn

-

-

tbus

82lfclk

BP/UP stable after DRDY falls

tbuh

0

-

teon

-

1624lfclk

Start of Conversion to End of Conversion

DS59F4

100

BP/UP stable prior to DRDY falling

CONY High to Start of Conversion
Set Up Time

thca
tcpw

(Note 15)

s

s

2-457

CS5505/sn/8

XIN
XIN/2

CAL
CONV

-------',

---1of+----'l~ teal

STATE _______S~t=an~d=b~y______.L_____~~~----~C=a=lib~m-t=io-n--------------'IL-=S=ta_n=db~y~
Figure 1. Calibration Timing (Not to Scale)

XIN
XIN/2

AO,A1
CONV

DRDY
BP/UP

STATE

Standby

Conversion

~

Standby

Figure 2. Conversion Timing (Not to Scale)

2-458

DS59F4

.... ...
. --._.-.
....
~

~~~

CS5505/6nt8

~-

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX;

VA+, VD+ = 5V ± 10%;
VA- = -5V ± 10%; Input Levels: Logic 0 = OV, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter

Symbol

Min

CS Low to SDATA out (DRDY = low)
DRDY falling to MSB (CS = low)

tcsd1
tdfd

SDATA Delay Time:

SCLK falling to next SDATA bit

tdd1

SCLK Delay Time

SDATA MSB bit to SCLK rising

tcd1

Serial Clock (Out)

Pulse Width High
Pulse Width Low

tph1
tpl1

CS high to output Hi-Z (Note 16)
SCLK rising to SDATA Hi-Z

tfd1
tfd2

-

Typ

Max

Units

2/fclk

2/fclk
3/fclk

ns
ns

80

250

ns

1/fclk

-

ns
ns
ns

2/fclk
-

ns
ns

sse Mode (MlSLP = VD+)

Access Time:

Output Float Delay:

1/fclk
1/fclk

1/fclk

SEe Mode (MlSLP = DGND)

fsclk

0

MHz

tph2
tpl2

200
200

-

2.5

Pulse Width High
Pulse Width Low

-

ns
ns

CS Low to data valid (Note 17)

tcsd2

-

60

200

ns

(Note 18)
SCLK falling to new SDATA bit

tdd2

150

310

ns

CS high to output Hi-Z (Note 16)
SCLK falling to SDATA Hi-Z

tfd3
tfd4

-

60
160

150
300

ns
ns

Serial Clock (In)
Serial Clock (In)
Access Time:
Maximum Delay time:
Output Float Delay:

Notes: 16. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the
__
current data bit and then go to high impedance.
17. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To
guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high
sooner than 2 fclk + 200 ns after CS goes low.
18. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.

DS59F4

2-459

..,.
..............
..,-- ._.
...........
..,

..,

CS5505l6l7/8

3.3V SWITCHING CHARACTERISTICS (TA = TMINto TMAX

VA+ = 5V± 10%; VD+ = 3.3V±
5%; VA- = -5V ± 10%; Input Levels: Logic 0 = OV, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter

Symbol

Min

= low)
= low)

tcsd1
tdfd

-

Typ

Max

Units

sse Mode {MlSLP = VD+J
Access Time:

CS Low to SDATA out (DRDY
DRDY falling to MSB (CS

-

2/fclk

21fclk .
3/fclk

ns
ns

SDATA Delay Time:

SCLK falling to next SDATA bit

tdd1

-

265

400

ns

SCLK Delay Time

SDATA MSB bit to SCLK rising

tcd1

-

1/fclk

ns

Serial Clock (Out)

Pulse Width High
Pulse Width Low

tph1
tpl1

CS high to output Hi-Z (Note 16)
SCLK rising to SDATA Hi-Z

Output Float Delay:

1/fclk
1/fclk

tfd1
tld2

-

-

-

2Ifclk

1/fclk

-

ns
ns

fsclk

0

1.25

MHz

Pulse Width High
Pulse Width Low

tph2
tpl2

200
200

-

-

-

ns
ns

CS Low to data valid (Note 17)

tcsd2

-

100

200

ns

(Note 18)
SCLK falling to new SDATA bit

tdd2

400

600

ns

CS high to output Hi-Z (Note 16)
SCLK falling to SDATA Hi-Z

tld3
tld4

-

70
320

150
500

ns
ns

ns
ns

SEe Mode {MlSLP = DGNDJ
Serial Clock (In)
Serial Clock (In)
Access Time:
Maximum Delay time:
Output Float Delay:

2~460

-

DS59F4

.. ...
._.-.
-. ..---,.
-~

~--

CS5505/SnJS

~~

XIN

~n n

~ LJ LJn LJn LJn L
~

/\J'U~%z

z

XIN/21LJ1

~rJm

CONV~Uli~~~________________~I~
~

-

~

CS
STATE

~

Standby

~

~

tcsd1

~

~-c-o-nv-e-r-Si-o-n-'·'--4-----S-ta-n-d-b-y---~~~_~c~o~nv~e~~=i=on~__
~

DRDY
SCLK(o)
SDATA(o)

~

~

~

Hi-Z-----;;~O--------_______1

~

;~
~
~
~
t
Hi-Z---~t-------{:::J~C!~~O==~f!.
t-

STATE (CONV held

~

~

~
z
~

~

LSB+1

X

LSB

Hi-Z
Hi-Z

~

hi~conve~ion1

Conve~ion2

~

~

Figure 3. Timing Relationships; SSC Mode (Not to Scale)

DRDY

\~------------------------------------

CS
SDATA(o) Hi-Z

tcsd2

~~---'EC:-------=--=--=--=----,-r----------~~:\~-Jr-t_fd_3_______
LJ-

--------I(

MSB

MSB-2

SCLK(i)

DRDY
CS
SDATA(o) Hi-Z

\~

____________~~------------~r--

_~t':CS~d"'2'_~~~_-_-~-;----M-iB---~--t---,-~-Si-3_-11

SCLK(i)

Figure 4. Timing Relationships; SEC Mode (Not to Scale)

DS59F4

2-461

.. ...
.....,
. ....__
._.
~.-

..,

~~

CS5505/617/8

~~

RECOMMENDED OPERATING CONDITIONS (DGND = OV)

(Note 19)

Parameter

Symbol

Min

Typ

Max

Units

DC Power Supplies: Positive Digital
(VA+)-(VA-)
Positive Analog
Negative Analog

VD+
Vdiff
VA+
VA-

3.15
4.5
4.5
0

5.0
10
5.0
-5.0

5.5
11
11
-5.5

V
V
V
V

1.0

2.5

3.6

V

0
-«VREF+)-(VREF-»

-

-

(VREF+)-(VREF-)
+«VREF+)-(VREF-»

V
V

Analog Reference Voltage (Note 20) (VREF+)-(VREF-)
Analog Input Voltage:
(Note 21)
Unipolar
Bipolar

VAIN
VAIN

Notes: 19. All voltages with respect to ground.
20. The CS5505/6f7/8 can be operated with a reference voltage as low as 100 mY; but with a
corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference
may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-.
21. The CS5505/6f7/8 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar
mode the CS5505/6f7/8 will output all1's if the dc input magnitude «AIN+)-(AIN-» exceeds
«VREF+)-(VREF-» and will output all O's if the input becomes more negative than 0 Volts.
In bipolar mode the CS5505/6f7/8 will output all1's if the dc input magnitude «AIN+)-(AIN-» exceeds
«VREF+)-(VREF-» and will output all O's if the input becomes more negative in magnitude than
-«VREF+)-(VREF-».

ABSOLUTE MAXIMUM RATINGS·
Parameter
DC Power Supplies:

Digital Ground
Positive Digital
Positive Analog
Negative Analog
(VA+)-(VA-)
(VA+)-(VD+)

Input Current, Any Pin Except Supplies
Analog Input Voltage
Digital Input Voltage

Storage Temperature
Notes: 22.
23.
24.
25.

(Notes 24, 25)

AIN and VREF pins

Ambient Operating Temperature

(Note 22)
(Note 23)

Symbol

Min

DGND
VD+
VA+
VAVdiff1
Vdiff2

-0.3
-0.3
-0.3
+0.3
-0.3
-0.3

lin

-

VINA

(VA-)-0.3

VIND

-0.3

TA

-55

Typ

Max

Units

-

(VD+)-0.3
6.0 or VA+
12.0
-6.0
12.0
12.0

V
V
V
V
V
V

±10

mA

(VA+)+0.3

V

-

-

(VD+)+0.3

V

125

°C

-

150
-65
Tstg
°C
..
No pin should go more positive than (VA+)+0.3V.
VD+ must always be less than (VA+)+0.3 V,and can never exceed 6.0V.
Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.
Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ± 50 mAo

• WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

2-462

DS59F4

_. .......... .... _.-.
..,-

..,..,~

..,..,

GENERAL DESCRIPTION

The CSSSOS/617/8 are very low power monolithic CMOS AID converters designed
specifically for measurement of dc signals. The
CSSSOSI7 are 16-bit converters (a four channel
and a single channel version). The CSSS06/8 are
20-bit converters (a four channel and a single
channel version). Each of the devices includes a
delta-sigma charge-balance converter, a voltage
reference, a calibration microcontroller with
SRAM, a digital filter and a serial interface. The
CSSSOS and CSSS06 include a four channel
pseudo-differential (all four channels have the
same reference measurement node) multiplexer.
The CSSSOS/61718 include an on-chip reference
but can also utilize an off-chip reference for precision applications. The CSSSOS/617/8 can be
used to measure either unipolar or bipolar signals. The devices use self-calibration to insure
excellent offset and gain accuracy.
The CSSSOS/617/8 are optimized to operate from
a 32.768 kHz crystal but can be driven by an
external clock whose frequency is between
30 kHz and 163 kHz. When the digital filter is
operated with a 32.768 kHz clock, the filter has
zeros precisely at SO and 60 Hz line frequencies
and mUltiples thereof.
The CSSSOS/617/8 use a "start convert" command to latch the input channel selection and to
start a convolution cycle on the digital filter.
Once the filter cycle is completed, the output
port is updated. When operated with a
32.768 kHz clock the ADC converts and updates
its output port at 20 samples/sec. The throughput
rate per channel is the output update rate divided
by the number of channels being multiplexed. The output port includes a serial
interface with two modes of operation.
The CSSSOS/617/8 can operate from dual polarity
power supplies (+S and oS), from a single +S
volt supply, or with + 10 volts on the analog and
DS59F4

CS5505/61718

+S on the digital. They can also operate with
dual polarity (+S and oS), or from a single +S
volt supply on the analog and + 3.3 on the digital.
THEORY OF OPERATION FOR THE
CS5505/617/8

The front page of this data sheet illustrates the
block diagram of the CSSSOS/6.
Basic Converter Operation

The CSSSOS/617/8 AID converters have four operating states. These are start-up, calibration,
conversion and sleep. When power is first applied, the device enters the start-up state. The
first step is a power-on reset delay of about
10 ms which resets all of the logic in the device.
To proceed with start-up, the oscillator must then
begin oscillating. Mter the power-on reset the
device enters the wake-up period for 1800 clock
cycles after clock is present. This allows the
delta-sigma modulator and other circuitry (which
are operating with very low currents) to reach a
stable bias condition prior to entering into either
the calibration or conversion states. During the
1800 cycle wake-up period, the device can accept an input command. Execution of this
command will not occur until the complete
wake-up period elapses. If no command is given,
the device enters the standby mode.
Calibration

After the initial application of power, the
CSSSOS/617/8 must enter the calibration state
prior to performing accurate conversions. During
calibration, the chip executes a two-step process.
The device first performs an offset calibration
and then follows this with a gain calibration.
The two calibration steps determine the zero reference point and the full scale reference point of
the converter's transfer function. From these
points it calibrates the zero point and a gain
2-463

.

~

,....
............
........ .....
...............
slope to be used to properly scale the output
digital codes when doing conversions.
The calibration state is entered whenever the
CAL and CONY pins are high at the same time.
The state of the CAL and CONV pins at poweron and when coming out of sleep are recognized
as commands, but will not be executed until the
end of the 1800 clock cycle wake-up period.
Note that any time CONY transitions from low
to high, the multiplexer inputs AO and Al are
latched internal to the CS5505 and CS5506 devices. These latched inputs select the analog
input channel which will be used once conversion commences.
If CAL and CONY become active (high) during
the 1800 clock cycle wake-up time, the converter
will wait until the wake-up period elapses before
executing the calibration. If the wake-up time
has elapsed, the converter will be in the standby
mode waiting for instruction and will enter the
calibration cycle immediately. The calibration
lasts for 3246 clock cycles. Calibration coefficients are then retained in the SRAM (static
RAM) for use during conversion.
At the end of the calibration cycle, the on-chip
microcontroller checks the logic state of the
CONY signal. If the CONV input is low the device will enter the standby mode where it waits
for further instruction. If the CONY signal is
high at the end of the calibration cycle, the converter will enter the conversion state and perform
a conversion on the input channel which was selected when CONY transitioned from low to
high. The CAL signal can be returned low any
time after calibration is initiated. CONY can also
be returned low, but it should never be taken low
and then taken back high until the calibration period has ended and the converter is in the
standby state. If CONY is taken low and then
high again with CAL high while the converter is
calibrating, the device will interrupt the current
calibration cycle and start a new one. If CAL is
taken low and CONY is taken low and then high
2-464

CS5S0S/6I718

during calibration, the calibration cycle will continue as the conversion command is disregarded.
The states of AO, Al and BPIUP are not important during calibrations.
If an "end of calibration" signal is desired, pulse
the CAL signal high while leaving the CONY
signal high continuously. Once the calibration is
completed,a conversion will be performed. At
the end of the conversion, DRDY will fall to indicate the first valid conversion after the
calibration has been completed.

See Understanding Converter Calibration for details on how the converter calibrates its transfer
function.
Conversion

The conversion state can be entered at the end of
the calibration cycle, or whenever the converter
is idle in the standby mode. If CONY is taken
high to initiate a calibration cycle ( CAL also
high), and remains high until the calibration cycle is completed (CAL is taken low after CONY
transitions high), the converter will begin a conversion upon completion of the calibration
period. The device will perform a conversion on
the input channel selected by the AO and Al inputs when CONV· transitioned high; Table I
indicates the multiplexer channel selection truth
table for AO and AI.
A1

AO

Channel addressed

0

0

AIN1

0

1

AIN2

1

0

AIN3

1

1

AIN4

Table 1. Multiplexer Truth Table

The AO and Al inputs are latched internal to the
4-channel devices (CS5505/6) when CONY
rises. AO and Al have internal pull-down circuits
which default the multiplexer to channel AINI.
DS59F4

__..--,...

....
. --- ...
.-.
-~

."

The BP/uP pin is not a latched input. The
BP/uP pin controls how the output word from
the digital filter is processed. In bipolar mode the
output word computed by the digital filter is offset by 8000H in the 16-bit CS5505n or 80000H
in 20-bit CS5506/8 (see Understanding Converter Calibration). BP/uP can be changed after
a conversion is started as long as it is stable for
82 clock cycles of the conversion period prior to
DRDY falling. If one wishes to intermix measurement of bipolar and unipolar signals on
various input channels, it is best to switch the
BP/uP pin immediately after DRDY falls and
leave BP/uP stable until DRDY falls again. If
the converter is beginning a conversion starting
from the standby state, BP/uP can be changed at
the same time as AO and AI.
The digital filter in the CS550516n18 has a Finite Impulse Response and is designed to settle
to full accuracy in one conversion time. Therefore, the multiplexer can be changed at the
conversion rate.
If CONY is left high, the CS550516n18 will per-

form continuous conversions on one channel.
The conversion time will be 1622 clock cycles.
If conversion is initiated from the standby state,
there may be up to two XIN clock cycles of uncertainty as to when conversion actually begins.
This is because the internal logic operates at one
half the external clock rate and the exact phase
of the internal clock may be 1800 out of phase
relative to the XIN clock. When a new conversion is initiated from the standby state, it will
take up to two XIN clock cycles to begin. Actual
conversion will use 1624 clock cycles before
DRDY goes low to indicate that the serial port
has been updated. See the Serial Interface Logic
section of the data sheet for information on reading data from the serial port.
In the event the AID conversion command
.(CONV going positive) is issued during the conversion state, the current conversion will be
DS59F4

CS5505/sn18

terminated and a new conversion will be initiated.
Voltage Reference

The CS550516/7/8 uses a differential voltage reference input. The positive input is VREF+ and
the negative input is VREF-. The voltage between VREF+ and VREF- can range from 1 volt
minimum to 3.6 volts maximum. The gain slope
will track changes in the reference without recalibration, accommodating ratiometric
applications.
The CS550516n/8 include an on-chip voltage
reference which outputs 2.5 volts on the VREFOUT pin. This voltage is referenced to the VA+
pin and will track changes relative to VA+. The
VREFOUT output requires a 0.1 J.lF capacitor
connected between VREFOUT and VA+ for stability. When using the internal reference, the
VREFOUT signal should be connected to the
VREF- input and the VREF+ pin should be connected to the VA+ supply. The internal voltage
reference is capable of sourcing 3 J.lA maximum
and sinking 50 J.lA maximum. If a more precise
reference voltage is required, an external voltage
reference should be used. If an external voltage
reference is used, the VREFOUT pin of the internal reference should be connected directly to
VA-. It cannot be left open unless the 0.1 J.lF capacitor is in place for stability.
CS550516n18
+VA

T

LT1019,
REF43
or
LM368

VA+
2.5V

VREF+
:

VREF-VA

V

r-

VREFOUT
VA,

Figure 5. External Reference Connections

2-465

-

.....,.-..........
,.. ._..
...............

CS55051617/B

ages for the AID. The differential input voltage
can also have any common mode value as long
as the maximum signal magnitude stays within
the supply voltages.

CSSS05N7/8
+VA-.---..-1

·VA

VA·

Figure 6. Internal Reference Connections

External reference voltages can range from 1.0
volt minimum to 3.6 volts maximum. The common mode voltage range of the external
reference can allow the reference to lie at any
voltage between the VA+ and VA- supply rails.
Figures 5 and 6 illustrate how the CS550516/7/8
converters are connected for external and for internal voltage reference use, respectively.

Analog Input Range
The analog input range is set by the magnitude
of the voltage between the VREF+ and VREFpins. In unipolar mode the input range will equal
the magnitude of the voltage reference. In bipolar mode the input voltage range will equate to
plus and minus the magnitude of the voltage reference. While the voltage reference can be as
great as 3.6 volts, its common mode voltage can
be any value as long as the reference inputs
VREF+ and VREF- stay within the supply volt-

The AID converter is intended to measure dc or
low frequency inputs. It is designed to yield accurate conversions even with noise exceeding the
input voltage range as long as the spectral components of this noise will be filtered out by the
digital filter. For example, with a 3.0 volt reference in unipolar mode, the converter will
accurately convert an input dc signal up to
3.0 volts with up to 15% overrange for 60 Hz
noise. A 3.0 volt dc signal could have a 60 Hz
component which is 0.5 volts above the maximum input of 3.0 (3.5 volts peak; 3.0 volts dc
plus 0.5 volts peak noise) and still accurately
convert the input signal (XIN = 32.768 kHz).
This assumes that the signal plus noise amplitude stays within the supply voltages.
The CS550516/718 converters output data inbinary format when converting unipolar signals
and in offset binary format when converting bipolar signals. Table 2 outlines the output coding
for the 16-bit CS5505/7 and the 20-bit CS5506/8
in both unipolar and bipolar measurement
modes.

CS5505 and CS5507 (16 Bit)

CS5506 and CS5508 (20 Bit)

Unipolar Input
Voltage

Output
Codes

Bipolar Input
Voltage

Unipolar Input
Voltage

Output
Codes

Bipolar Input
Voltage

>(VREF - 1.5 LSB)

FFFF

>(VREF - 1.5 LSB)

>(VREF - 1.5 LSB)

FFFFF

>(VREF - 1.5 LSB)

VREF - 1.5 LSB

FFFF
FFFE

VREF - 1.5 LSB

VREF - 1.5 LSB

FFFFF
FFFFE

VREF - 1.5 LSB

VREF/2 - 0.5 LSB

8000
7FFF

-0.5 LSB

VREF/2 - 0.5 LSB

80000
7FFFF

-0.5 LSB

+0.5 LSB

0001
0000

-VREF + 0.5 LSB

+0.5 LSB

00001
00000

-VREF + 0.5 LSB

«+0.5 LSB)

0000

«-VREF + 0.5 LSB)

«+0.5 LSB)

00000

«-VREF + 0.5 LSB)

Note: VREF

= (VREF+) - (VREF-); Table excludes common mode voltage on the signal and reference inputs.
Table 2. Output Coding

2-466

DS59F4

...........
--_ ....- .
.............

CS5505/617/8

Understanding Converter Calibration

Calibration can be perfonned at any time. A calibration sequence will minimize offset errors and
set the gain slope scale factor. The delta-sigma
modulator in the converter is a differential modulator. To calibrate out offset error, the converter
internally connects the modulator differential inputs to an internal VREF- voltage and measures
the 1's density output from the modulator. It
stores the digital code representation for this 1's
density in SRAM and remembers this code as
being the zero scale point for the AID conversion. The converter then connects the negative
modulator differential input to the VREF- input
and the positive modulator differential input to
the VREF+ voltage. The 1's density output from
the modulator is then recorded. The converter
uses the digital representation of this 1's density
along with the digital code for the zero scale
point and calculates a gain scale factor. The gain
scale factor is stored in SRAM and used for calculating the proper output codes during
conversions.
The states of AO, Al and BP/uP are ignored during calibration but should remain stable
throughout the calibration period to minimize
noise.
When conversions are performed in unipolar
mode or in bipolar mode, the converter uses the
same calibration factors to compute the digital
output code. The only difference is that in bipolar mode the on-chip microcontroller offsets the
computed output word by a code value of 8000H

(16-bit) or 80000H (20-bit) and multiplies the
LSB size by two. This means that the bipolar
measurement range is not calibrated from full
scale positive to full scale negative. Instead it is
calibrated from the bipolar zero scale point to
full scale positive. The slope factor is then extended below bipolar zero to accommodate the
negative input signals. The converter can be used
to convert both unipolar and bipolar signals by
changing the BP/uP pin. Recalibration is not required when switching between unipolar and
bipolar modes.
Converter Performance

The CSSSOS/61718 AID converters have excellent
linearity perfonnance. Calibration minimizes the
errors in offset and gain. The CSSSOS17 devices
have no missing code perfonnance to 16-bits.
The CSSS06/8 devices have no missing code
performance to 20-bits. Figure 7 illustrates the
DNL of the 16-bit CSSSOS. The converters
achieve Common Mode Rejection (CMR) at dc
of lOS dB typical, and CMR at 50 and 60 Hz of
120 dB typical.
The CSSSOS/61718 can experience some drift as
temperature changes. The CSSSOS/617 18 use
chopper-stabilized techniques to minimize drift.
Measurement errors due to offset or gain drift
can be eliminated at any time by recalibrating
the converter.

+112

1iJ
U)
d.
-'

z

0 .112

·1

32,768

Codes

Figure 7. CSSSOS Differential Nonlinearity plot.
DS59F4

2-467

~.'.
~

. -.. -.

...............
...
.............
~

CS5505/sn/8

Analog Input Impedance Considerations

The analog input of the CS5505/6n18 can be
modeled as illustrated in Figure 8 (the model ignores the multiplexer switch resistance).
Capacitors (15 pF each) are used to dynamically
sample each of the inputs (AIN+ and AIN-).
Every half XIN cycle the switch alternately connects the capacitor to the output of the buffer
and then directly to the AIN pin. Whenever the
sample capacitor is switched from the output of
the buffer to the AIN pin, a small packet of
charge (a dynamic demand of current) is required from the input source to settle the voltage
of the sample capacitor to its final value. The
voltage on the output of the buffer may differ up
to 100mV from the actual input voltage due to
the offset voltage of the buffer. Timing allows
one half of a XIN clock cycle .for the voltage on
the sample capacitor to settle to its final value.
The equation Which defines the settling time is:

Where Ve is the final settled value, Vmax is the
maximum error voltage value of the input signal,
R is the value of the input source resistance, C is
the 15 pF sample capacitor plus the value of any
stray or additional capacitance at the input pin.
The value of t is equal to 1/(2XIN).

CSSSOS/6nJS

AIN+ O - - - - - - . - - - - - - D . ,

l
AIN-

15 pF
,ntema,
Bias
"
Voltage, '
15 pF "

.-

Vmax occurs the instant the sample capacitor is
switched from the buffer output to the AIN pin.
Prior to switching, AIN has an error estimated as
being less than or equal to Ve. Vmax is equal to
the prior error (Ve) plus the additional error
from the buffer offset. The estimate for Vmax is:
.

. 15pF

Vmax=Ve+ lOOmV (15pF+CEXT)

Where CEXT is the combination of any external
or stray capacitance.
From the settling time equation, an equation for
the maximum acceptable source resistance is derived.

Rs max =

-1[
V
2XIN (l5pF+CEJIT) In V + l5P;(lOOmV)
e
(15pF + CEXT)

1

This equation assumes that the offset voltage of
the buffer is 100mV, which is the worst case.
The value of Ve is the maximum error voltage
which is acceptable. .
For a maximum error voltage (Ve) of 10 flY in
the CS5505 (1I4LSB at 16-bits) and 600 nV in
the CS5506 (1/4LSB at 20-bits), the above equation indicates that when operating from a
32.768 kHz XIN, source resistances up to
110 ill in the CS5505 or 84 ill in the CS5506
are acceptable in the absence of external capacitance (CEXT = 0). If higher input source
resistances are desired the master clock rate can
be reduced to yield a longer settling time.
The VREF+ and VREF- inputs have nearly the
same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input impedance applies to the voltage reference inputs as
well.

Figure 8. Analog Input Model
2-468

DS59F4

.. ...-..
-. .. .......
~~

~~-

..,

CS5505/6171S

~~

Digital Filter Characteristics

The digital filter in the CSSSOSI61718 is the combination of a comb filter and a low pass filter.
The comb filter has zeros in its transfer function
which are optimally placed to reject line interference frequencies (SO and 60 Hz and their
multiples) when the CSSSOSI61718 is clocked at
32.768 kHz. Figures 9, 10 and 11 illustrate the
magnitude and phase characteristics of the filter.
0.,.....,,----------------,
-20

- ; - -: - -: - -: - -: Xl'= 32.768kHz. :- .
, X2 = 163.00kHz '
-, - -, - -,' -, - -, - ',- -,- - ,- - ,- - ,- -

-40

iii'
~

-60

-

j"

-

- .,-

I

c

'iiio

-

-80

- - - - - I

---- -- -

"

, . ,

Figure 9 illustrates the filter attenuation from dc
to 260 Hz. At exactly SO, 60, 100, and 120 Hz
the filter provides over 120 dB of rejection. Table 3 indicates the filter attenuation for each of
the potential line interference frequencies when
the converter is operating with a 32.768 kHz
clock. The converter yields excellent attenuation
of these interference frequencies even if the fundamental line frequency should vary ±1 % from
its specified frequency. The -3 dB corner frequency of the filter when operating from a
32.768 kHz clock is 17 Hz. Figure 11 illustrates
that the phase characteristics of the filter are precisely linear phase.
Frequency
(Hz)

Notch
Depth

50
60
100
120
150
180
200
240

125.6
126.7
145.7
136.0
118.4
132.9
102.5
108.4

(dB)

-

:::J

!c -100

,

I

"

"

.-. ---·------n--I

-120

-

.:

I

-

-

-

-

-

.:

"

"

"

I

"

• • :.

"

-

-

.:.
I

I

:.

-

I

Frequency Minimum
(Hz)
Attenuation

I
,

' "

-140
: XIN = 32.768 kHz:
-160 +----j--j-----t----t-r----t---j----t---t---tr----r--t--I
Xl
0
40
80
120
160
200
240
X2
0
198.97397.95596.92795.10993.871193.85

(dB)

55.5
58.4
62.2
68.4
74.9
87.9
94.0
104.4

50±1%
60±1%
100+1%
120±1%
150±1%
180±1%
200±1%
240+1%

Frequency (Hz)

Figure 9. Filter Magnitude Plot to 260 Hz

=32.768 kHz)

Table 3. Filter Notch Attenuation (XIN

180.------~~-------_,

iD

,Frequency dB '
1
·0.010 '
2
·0.041 :·0.093 '
4
-0.166 '__

-40

~

IS

!Iii
~

135

Flatness - - ,.. - - ,- - -, - - ... -

-20

-60

5
6

-80

7
8

-100
10
17

-120

,

I

-0.259 ,
-0.374 '
-0.510: - -:- - -: - -0.667 ,
-0.846' .
-1.047,
-3.093 ,

j

- - : - -:- -

,

I

,

,

,

I

I

- - - - - - - - - - - - - - - - - -

45

~

~

,

- - - - - - - - - - -

90

0
-45

IL

-90

XIN = 32.768 kHz '

XIN = 32.768 kHz
-135

-140 +----t---t----t---j---t---t--r-------t---t----1

o

5

10

15

20

25

30

35

40

Frequency (Hz)

Figure 10. Filter Magnitude Plot to 50 Hz
DS59F4

45

50

o

5

10

15

20

25

30

35

40

45

50

Frequency (Hz)

Figure 11. Filter Phase Plot to 50 Hz
2-469

..
,

.........-...._..
~

...,

~

~~~

~~

..,

CS5S0S/6nJS

If the CS550516n/8 is operated at a clock rate
other than 32.768 kHz, the filter characteristics,
including the comb filter zeros, will scale with
the operating clock frequency. Therefore, optimum rejection of line frequency interference will
occur with the CS55051617 18 running at
32.768 kHz. The CS550516n18 can be used with
external clock rates from 30 kHz to 163 kHz.

should be removed by means of low-pass filtering prior to the AID input to prevent aliasing.
Spectral components greater than one half the
output word rate on the VREF inputs (VREF+
and VREF-) may also be aliased. Filtering of the
reference voltage to remove these spectral components from the reference voltage is. desirable.
Crystal Oscillator

Anti-Alias Considerations for Spectral
Measurement Applications

The CS550516n /8 is designed to be operated using a 32.768 kHz "tuning fork" type crystal. One
end of the crystal should be connected to the
XIN input. The other end should be attached to
XOUT. Short lead lengths should be used to
minimize stray capacitance. Figure 12 illustrates
the gate oscillator, and a simplified version of
the control logic used on the chip.

Input frequencies greater than one half the output word rate (CONV = 1) may be aliased by the
converter. To prevent this, input signals should
be limited in frequency to no greater than one
half the output word rate of the converter (when
CONY =1). Frequencies close to the modulator
sample rate (XIN/2) and multiples thereof may
also be aliased. If the signal source includes
spectral components above one half the output
word rate (when CONY = 1) these components

Over the industrial temperature range (-40 to
+85 0c) the on-chip gate oscillator will oscillate
with other crystals in the range of 30 kHz to

CS5505I6
AO

Channel AO

D Q
CLK

A1

Input
Mux
Decoder

D Q

1

0

2

0

A1
0

3

0

4

1

CLK
S Q

CONV

R

R
S Q

CAL
10MQ

D Q
CLK

Start
Conversion

D Q Start
Calibration
CLK

R
Q
T

Modulator
Sample
Clock

XOUT
XIN
"-----101----'
XTL=32.768 kHz

Figure 12. Gate Oscillator and Control Logic

2·470

DS59F4

.. .....
. ..,.,.......
~.-

-'

~~-

~~

-'

53 kHz. Over the military temperature range (-55
to + 125 QC) the on-chip gate oscillator is designed to work only with a 32.768 kHz crystal.
The chip will operate with external clock frequencies from 30 kHz to 163 kHz over all
temperature ranges. The 32.768 kHz crystal is
normally specified as a time-keeping crystal with
tight specifications for both initial frequency and
for drift over temperature. To maintain excellent
frequency stability, these crystals are specified
only over limited operating temperature ranges
(Le. -10 to +60 QC) by the manufacturers. Applications of these crystals with the CS5505/617/8
do not require tight initial tolerance or low
tempco drift. Therefore, a lower cost crystal with
looser initial tolerance and tempco will generally
be adequate for use with the CS5505/61718 converters. Also check with the manufacturer about
wide temperature range application of their
standard crystals. Generally, even those crystals
specified for limited temperature range will operate over much larger ranges if frequency stability
over temperature is not a requirement. The frequency stability can be as bad as ±3000 ppm
over the operating temperature range and still be
typically better than the line frequency (50 or
60 Hz) stability over cycle to cycle during the
course of a day. There are crystals available for
operation over the military temperature range (55 to +125 QC). See the Appendix for suppliers
of 32.768 kHz crystals.
Serial Interface Logic
The digital filter in the CS5505/617/8 takes 1624
clock cycles to compute an output word once a
conversion begins. At the end of the conversion
cycle, the filter will attempt to update the serial
port. Two clock cycles prior to the update DRDY
will go high. When DRDY goes high just prior
to a port update it checks to see if the port is
either empty or un selected (CS = 1). If the port
is empty or unselected, the digital filter will update the port with a new output word. When new
data is put into the port DRDY will go low.
DS59F4

CS5505/6nta

Data can be read from the serial port in either of
two modes. The M/SLP pin determines which
serial mode is selected. Serial port mode selection is as follows:
SSC (Synchronous Self-Clocking) mode;
MlSLP = VD+, or SEC (Synchronous External
Clocking) mode; MlSLP = DGND. Timing diagrams which illustrate the SSC and SEC timing
are in the tables section of this data sheet.
Synchronous Self-Clocking Mode
The serial port operates in the SSC mode when
the MlSLP pin is connected to the VD+ pin on
the part. In SSC mode the CS5505/617 18 furnishes both the serial output data (SDATA) and
the serial clock (SCLK). When the serial port is
updated at the end of a conversion, DRDY falls.
If CS is low, the SDATA and SCLK pins will
come out of the high impedance state two XIN
clock cycles after DRDY falls. The MSB data
bit will be presented for two cycles of XIN
clock. The SCLK signal will rise in the middle
of the MSB data bit. When SCLK then returns
low the (MSB - 1) bit will appear. Subsequent
data bits will be output on each falling edge of
SCLK until the LSB data bit is output. After the
LSB data bit is output, the SCLK will fall at
which time both the SDATA and SCLK outputs
will return to the high impedance output state.
DRDY will return high at this time.
If CS is taken low after DRDY falls, the MSB

data bit will appear within two XIN clock cycles
after CS is taken low. CS need not be held low
for the entire data output. If CS is returned high
during a data bit the port will complete the output of that bit and then go into the Hi-Z state.
The port can be reselected any time prior to the
completion of the next conversion (DRDY falling) to allow the remaining data bits to be
output.

2-471

•

----------- ----------Synchronous External-Clocking Mode
The serial port operates in the SEC mode when
the M/SLP pin is connected to the DGND pin.
SDATA is the output pin for the serial data.
When CS goes low after new data becomes
available (DRDY goes low), the SDATA pin
comes out of Hi-Z with the MSB data bit present. SCLK is the input pin for the serial clock
in the SEC mode. If the MSB data bit is on the
SDATA pin, the first rising edge of SCLK enables the shifting mechanism. This allows the
falling edges of SCLK to shift subsequent data
bits out of the port. Note that if the MSB data
bit is output and the SCLK signal is high, the
first falling edge of SCLK will be ignored because the shifting mechanism has not become
activated. After the first rising edge of SCLK,
each subsequent falling edge will shift out the
serial data. Once the LSB is present, the falling
edge of SCLK will cause the SDATA output to
go to Hi-Z and DRDY to return high. The serial
port register will be updated with a new data
word upon the completion of another conversion
if the serial port has been emptied, or if the CS
is inactive (high).

CS550516/7/8

converter must go through a wake-up sequence
prior to conversions being initiated. This wakeup sequence includes the 10 msec. (typ.)
power-on-reset delay, the start-up of the oscillator (unless an external clock is used), and the
1800 clock cycle wake-up delay after the clock
begins. When coming out of the sleep condition,
the converter will latch the AO and Al inputs.
Figure 13 illustrates how to use a gate and resistors to bias the M/SLP pin into the SLEEP
threshold region when using the converter in the
SSC mode. To use the SEC mode return resistor
RI to DGND instead of the supply. When in the
SEC mode configuration the CS5505/61718 will
enter the SLEEP threshold when the logic control input is a logic I (VD+). Note that large
resistors can be used to conserve power while in
sleep. The input leakage of the pin is typically
less than I f..lA even at 125°C, although the
worst case specification tables indicate a leakage
of 10 f..lA maximum.
VD+*

1%
CS5505/6nta

CS can be operated asynchronously to the
DRDY signal. The DRDY signal need not be
monitored as long as the CS signal is taken low
for at least two XIN clock cycles plus 200 ns
prior to SCLK being toggled. This ensures· that
CS has gained control over the serial port.

Control
Input

=

Ir--+---j M/SLP
499k

'1' SSC Mode
'0' = SLEEP

1%

0.01!J.F

T

* Tie R1 to DGND for SEC mode; control input
logic inverts.

Sleep Mode
The CS5505/6/7 18 devices offer two methods of
putting the device into a SLEEP condition to
conserve power. Calibration words will be retained in SRAM during either sleep condition.
The M/SLP pin can be put into the SLEEP
threshold to lower the operating power used by
the device to about 1% of nominal. Alternately,
the clock into the XIN pin can be stopped. This
will lower the power consumed by the converter
to about 30% of nominal. In both cases, the
2-472

R1

=499k, VD+ =5V; ~ =590k, \b + =3.3V
Figure 13. Sleep Threshold Control

Power Supplies and Grounding
The analog and digital supply pins to the
CS5505/6/718 are brought out on separate pins to
minimize noise coupling between the analog and
digital sections of the chip. Note that there is no
analog ground pin. No analog ground pin is required because the inputs for measurement and
DS59F4

__

......,..,"""
...,--._..
....
.....

CS5505/617/8

for the voltage reference are differential and require no ground. In the digital section of the
chip the supply current flows into the VD+ pin
and out of the DGND pin. As a CMOS device,
the CSSSOS/617/8 requires that the supply voltage on the VA+ pin always be more positive than
the voltage on any other pin of the device. If this
requirement is not met, the device can latch-up
or be damaged. In all circumstances the VA+
voltage must remain more positive than the VD+
or DGND pins; VD+ must remain more positive
than the DGND pin.

The following power supply options are possible:
VA+ = +SV to +10V, VA- = ov,
VA+ = +sv,
VA- = -sv,
VA- = OV to -SV,
VA+ =+sv,

VD+ = +SV
VD+ = +SV
VD+ = +3.3V

The CSSSOS/617/8 cannot be operated with a
3.3V digital supply if VA+ is greater than +S.5y.
Figure 14 illustrates the System Connection Diagram for the CSSSOS/6 using a single +SV
supply. Note that all supply pins are bypassed
10n
A.

O~

+SV
Analog
Supply

O~
17

~

20
VD+

VA+

XIN
Calibration
Control
Bipolarl
Unipolar
Inout Select

4

8

-=c
S

Il-=
6

CAL

XOUT

-

BP/UP

M/SLP

~32.768kHz
7

CS5505/6

9
10
12
13

Analog·
Signal ~
Sources 0
Signal
Ground

11
·Unused analog inputs
should be tied to AIN-14
+

Voltage
Reference

-

15

~

AIN1+
AIN2+
AIN3+
AIN4+

SCLK
SDATA

AIN-

DRDY

-

CS
VREF+

AO
A1

VREF-

CON V

VREFOUT
DGND
VA181

Optional
Clock
Source

Sleep Mode
Control
and
Output Mode
Select

21

Serial
Data
Interface

22
23
2
1
24

Control
Logic

3
19

l

Unused Logic
inputs must be
connected to
VD+ or DGND.

Note: To use the internal 2.5 volt reference see Figure 6.
Figure 14. CSSSOS/6 System Connection Diagram Using External Reference, Single Supply
DS59F4

2-473

i

•

I

I

_. ........_-._.
..........,

..,..,

..,..,

CS5505/6nta

with 0.1 JlF capacitors and that the VD+ digital
supply is derived from the VA+ supply.

When using separate supplies for VA+ and VD+,
VA+ must be established first. VD+ should
never become more positive than VA+ under any
operating condition. Remember to investigate
transient power-up conditions, when one power
supply may have a faster rise time.

Figure 15 illustrates the CS5505/6 using dual
supplies of +5 and -5V.
Figure 16 illustrates the CS5505/6 using dual
supplies of +10V analog and +5V digital.

10(1

''l/lNv

O~

+5V
Analog
Supply

17

~

VA+

VD+
XIN

Calibration
Control
Bipolar!
Unipolar
Inout Select

4

8

oJk

20

--=r=-

5

Optional
Clock
Source

h--=
6

CAL

XOUT

-

BP/UP

M!SLP

~2.768kHZ
7

Sleep Mode
Control
and
Output Mode
Select

CS5505/6
Analog·
Signal
Sources
Signal
Ground

9
10
12
13

U

11
·Unused analog inputs
should be tied to AIN-14
+

Voltage
Reference

~
-SV
Analog
Supply

15

-

AIN1+
AIN2+
AIN3+
AIN4+

SCLK
SDATA

AIN-

DRDY
-

CS
VREF+

AO
A1

VREF-

CONV

16

.--- VREFOUT
0Jk:

T

DGND

VA18
1

21

Serial
Data
Interface

22
23
2
1
24

Control
Logic

3
19

-1
-

Unused Logic
inputs must be
connected to
VD+ or DGND.

Note: To use the internal 2.5 volt reference see Figure 6.
Figure 15. CS5505/6 System Connection Diagram Using External Reference, Dual Supplies

2-474

DS59F4

...............
..,..... -.
.............
+10V
Analog
Supply

CS5505/6n18

0Jk=

O~

17 (2)

~

VA+

+5V
Analog
Supply

---::r-

20
VD+

Optional
Clock
Source

5
XIN ~--Calibration
Control
Bipolarl
Unipolar
Inout Select

4

8

XOUT ~
32.768 kHz

CAL
-

BP/UP

M/SLP

7

Sleep Mode
Control
and
Output Mode
Select

CS5505/6

9
10
12
13

Analog*
Signal ~
Sources

11
*Unused analog inputs
should be tied to AIN14
+
Voltage
(1 )
Reference
15

Signal
Ground

-

- 16

AIN1+
AIN2+
AIN3+
AIN4+

SCLK
SDATA
--

AIN-

DRDY
-

CS
VREF+

AO
A1

VREF-

CONV

VREFOUT
DGND
VA-

21

Serial
Data
Interface

22
23
2
1
24

Control
Logic

3
19

181

-

Unused Logic
inputs must be
connected to
VD+or DGND.

Note: (1) To use the internal 2.5 volt reference see Figure 6.
(2) VD+ must never exceed VA+. Examine power-up conditions.
Figure 16. CS5505/6 System Connection Diagram Using External Reference,
Dual Supply, +10V Analog, +5V Digital

Schematic &Layout Review Service
Confirm Optimum
Schematic &Layout
Before Building Your

DS59F4

2-475

.........
..._........
.............
."

CS5505/6n1S

PIN CONNECTIONS*
CS5505/6
MULTIPLEXER SELECTION INPUT

AO

CHIP SELECT
CONVERT
CALIBRATE
CRYSTAL IN
CRYSTAL OUT

A1

MULTIPLEXER SELECTION INPUT

DRDY

DATA READY

SDATA

SERIAL DATA OUTPUT

SCLK

SERIAL CLOCK INPUT/OUTPUT

VD+

POSITIVE DIGITAL POWER

DGND

DIGITAL GROUND

SERIAL MODEl SLEEP

MlSLP

7

VA-

NEGATIVE ANALOG POWER

BIPOLAR/UNIPOLAR

BP/UP

8

VA+

POSITIVE ANALOG POWER

DIFFERENTIAL ANALOG INPUT

VREFOUT VOLTAGE REFERENCE OUTPUT

DIFFERENTIAL ANALOG INPUT

A1N2+

VREF-

VOLTAGE REFERENCE INPUT

DIFFERENTIAL ANALOG RETURN

AIN-

VREF+

VOLTAGE REFERENCE INPUT

DIFFERENTIAL ANALOG INPUT

AIN3+

AIN4+

DIFFERENTIAL ANALOG INPUT

CS550718

CHIP SELECT

CS

CONVERT

CONY

DRDY

DATA READY

SDATA

SERIAL DATA OUTPUT

SCLK

SERIAL CLOCK INPUT/OUTPUT

VD+

POSITIVE DIGITAL POWER

CALIBRATE

CAL

CRYSTAL IN

XIN

CRYSTAL OUT

XOUT

DGND

DIGITAL GROUND

SERIAL MODEl SLEEP

MlSLP

VA-

NEGATIVE ANALOG POWER

BIPOLAR/UNIPOLAR

BP/uP

VA+

POSITIVE ANALOG POWER

DIFFERENTIAL ANALOG INPUT

AIN+

NO CONNECTION

NC

VREF-

VOLTAGE REFERENCE INPUT

DIFFERENTIAL ANALOG INPUT

AIN-

VREF+

VOLTAGE REFERENCE INPUT

VREFOUT VOLTAGE REFERENCE OUTPUT

'Pinout applies to both DIP and SOIC

2-476

DS59F4

..--""".
__

.-~ ...
...-.
....
-~-

CS5505/6n1S

PIN DESCRIPTIONS
Pin numbers for four channel devices are in parentheses.

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 4 (5) and 5 (6).
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).
Serial Output 110

MlSLP - Serial Interface Mode Selectl Sleep, Pin 6 (7).
Dual function pin which selects the operating mode of the serial port and provides a very low
power sleep function. When MlSLP is tied to the VD+ pin the serial port will operate in the
Synchronous Self-Clocking (SSC) mode. When MlSLP is tied to the DGND pin the serial port
will operate in the Synchronous External Clocking (SEC) mode. When the MlSLP pin is tied
half way between VD+ and DGND the chip will enter into a very low powered sleep mode in
which its calibration data will be maintained.
CS - Chip Select, Pin 1 (2).
This input allows an external device to access the serial port.
DRDY - Data Ready, Pin 20 (23)
Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).
SDATA - Serial Data Output, Pin 19 (22).
SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK and in a format determined by the MlSLP pin. Data is output MSB first
and advances to the next data bit on the falling edges of SCLK. SDATA will be in a high
impedance state when not transmitting data.
SCLK - Serial Clock InputlOutput, Pin 18 (21).
A clock signal on this pin determines the output rate of the data from the SDATA pin. The
M/SLP pin determines whether SCLK is an input or and output. When used as an input, it must
not be allowed to float.

DS59F4

2-477

.. .....
. ...,.,
.......
~,."

~~~

~

~

.CS5505/61718

Control Input Pins
CAL - Calibrate, Pin 3 (4).
When taken high the same time that the CONY pin is taken high the converter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.
CONY - Convert, Pin 2 (3).
The CONY pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. CONY
latches the multiplexer selection when it transitions from low to high on the multiple channel
devices. If CONY is held high (CAL low) the converter will do continuous conversions.
AO, Al - Multiplexer Selection Inputs, Pins (1, 24).
AO and At select the input channel for conversion on the multi-channel input devices. AO and
At are latched when CONY transitions from low to high. These two inputs have pull-down
resistors internal to the chip.
BP/uP - Bipolar/unipolar, Pin 7 (8).
The BPIUP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.

Measurement and Reference Inputs
AIN+, AIN-, (AINl+, AIN2+, AIN3+, AIN4+, AIN-) - Differential Analog Inputs, Pins 8, 10 (9,
10, 12, 13, 11).
AIN- in the CSSSOS/6 is a common measurement node for AINI +, AIN2+, AIN3+ and AIN4+.
VREF+, VREF- - Differential Voltage Reference Inputs, Pins 11, 12 (14, 15).
A differential voltage reference on these pins operates as the voltage reference for the converter.
The voltage between these pins can be any voltage between 1.0 and 3.6 volts.

Voltage Reference
VREFOUT - Voltage Reference Output, Pin 13 (16).
The on-chip voltage reference is output from this pin. The voltage reference has a nominal
magnitude of 2.S volts and is referenced to the VA+ pin on the converter.

Power Supply Connections
VA+ - Positive Analog Power, Pin 14 (17).
Positive analog supply voltage. Nominally +S volts.
VA- - Negative Analog Power, Pin 15 (18).
Negative analog supply voltage. Nominally -S volts when using dual polarity supplies; or 0
volts (tied to system analog ground) when using single supply operation.

2-478

DS59F4

_-_

.... ......
.--.........
......
-

CS5505/6ms

VD+ - Positive Digital Power, Pin 17 (20).
Positive digital supply voltage. Nominally +5 volts or 3.3 volts.
DGND - Digital Ground, Pin 16 (19).
Digital Ground.
Other
NC - No Connection, Pin 9.
Pin should be left floating.

SPECIFICATION DEFINITIONS

Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the AID
Converter transfer function. One endpoint is located 112 LSB below the first code transition
and the other endpoint is located 112 LSB beyond the code transition to all ones. Units in
percent of full-scale.
Differential Nonlinearity
The deviation of a code's width from the ideal width. Units in LSBs.
Full Scale Error
The deviation of the last code transition from the ideal [( (VREF+) - (VREF-)} - % LSB]. Units
are in LSBs.
Unipolar Offset
The deviation of the first code transition from the ideal e/2 LSB above the voltage on the AINpin.) when in unipolar mode (BP/uP low). Units are in LSBs.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100... 000) from the ideal (1;2 LSB below
the voltage on the AIN- pin.) when in bipolar mode (BP/uP high). Units are in LSBs

DS59F4

2-479

.............
....... _.
.........

•

~

CS5505/61718

~

Ordering Guide
Model
Number

# of
Channels

Resolution

Linearity
Error

Temperature
Range eC)

Package Type

CS5505-AP
CS5505-AS

4
4

1S-Bits
1S-Bits

0.0030%
0.0030%

-40 to +85
-40 to +85

24-pin 0.3" Plastic DIP
24-pin 0.3" SOIC

CS550S-BP
CS550S-BS

4
4

20-Bits
20-Bits

0.0015%
0.0015%

-40 to +85
-40 to +85

24-pin 0.3" Plastic DIP
24-pin 0.3" SOIC

CS5507-AP
CS5507-AS
CS5507-SD

1
1
1

1S-Bits
1S-Bits
1S-Bits

0.0030%
0.0030%
0.0030%

-40 to +85
-40 to +85
-55 to +125

20-pin 0.3" Plastic DIP
20-pin 0.3" SOIC
20-pin 0.3" CerDIP

20-Bits
20-Bits
20-Bits

0.0015%
0.0015%
0.0030%

-40 to +85
-40 to +85
-55 to +125

20-pin 0.3" Plastic DIP
20-pin 0.3" SOIC
20-pin 0.3" CerDIP

CS5508-BP
CS5508-BS
CS5508-SD

2-480

DS59F4

.... ..,..........._.
....
~

~~

~~

CS5505/6nJ8

APPENDIX
The following companies provide 32.768 kHz crystals in many package varieties and temperature
ranges.
Fox Electronics
5570 Enterprise Parkway
Fort Meyers, FL 33905
(813) 693-0099
Micro Crystal Division / SMH
702 West Algonquin Road
Arlington Heights, IL 60005
(708) 806-1485
SaRonix
4010 Transport Street
Palo Alto, California 94303
(415) 856-6900
Statek
512 North Main
Orange, California 92668
(714) 639-7810
IQD Ltd.
North Street
Crewkerne
Somerset TA18 7 AK
England
0146077155

I

1111

Taiwan X'tal Corp.
5F. No. 16, Sec 2, Chung Yang S. RD.
Reitou, Taipei, Taiwan R. O. C.
Tel: 02-894-1202
Fax: 02-895-6207
Interquip Limited
241F Million Fortune Industrial Centre
34-36 Chai Wan Kok Street, Tsuen Wan N T
Tel: 4135515
Fax: 4137053
S& T Enterprises, Ltd.
Rm 404 Blk B
Sea View Estate
North Point, Hong Kong
Tel: 5784921
Fax: 8073126
Mr. Darren Mcleod
Hy-Q International Pty. Ltd.
12 Rosella Road,
FRANKSON,3199
Victoria, Australia
Tel: 61-3-783 9611
Fax: 61-3-783 9703

Mr. Pierre Hersberger
Microcrysta1/DIV. ETA S.A.
Schild-Rust-Strasse 17
Grenchen CH-2540
Switzerland
065530557

DS59F4

2-481

............
.............
. ..a . . . . . .~ •

CDB5505 CDB5506
CDB5507 CDB5508

Semiconductor Corporation

Evaluation Board for CSSSOSI6nl8 Series of ADC's
General De-scription

Features

The CDBSSOS/SSOS/SS07/SS0S is a circuit board designed to provide quick evaluation of the CSSSOS/SniS
series of AID converters. The board can be configured
to evaluate the CSSSOS/SniS in either SSC (Synchronous
Self-Clocking)
or
SEC
(Synchronous
External-Clocking) serial port mode.

• Operation with on-board 32.768 kHz
crystal or off-board clock source
• Jumper selectable:
sse mode; SEe mode; Sleep

The board allows access to all. of the digital interface
pins of the CSSSOS/SniS Chip.

• DIP Switch Selectable:
BP/OP mode; AD, & A 1 channel
selection
• On-board precision voltage reference
• Access to all digital control pins

ORDERING INFORMATION
CDBSSOS

• On-board patch area

CDBSS07

CDBSSOS
CDBSSOS

AIN4+

CS5505/6ma

B

AIN3+

U
F
F

AIN2+

E
R
S

H

E
A
0

E
R

AIN1+
AIN-

elKIN

=~w

BP/UP

9 AIN1+

vvv CA

AIN_~vv~---:

I

11'\11'1-

R14

S I

IVU~

14'K

H

r-..J

U2 74HC4050
U3 74HC125
v

I I

I I

~A1

-:~-I-

...L:

Sj"Yl

L--.1k lJ sse

~I=~

m
en
en
0
en
en
en
0

e

AO

CLKIN(~

0
C

CI1

CONY

en

Iijl BPtUP

0

:::!
CI1

en

II
til

I\)

.ao
0

F
gure 1. ADC Connections

_.-_..--__.._-_
...-..

CDB5505/5506/5507/5508
I

AO

1

CS

~
3/2

CS5507/8
19/22

DRDY

CONY

SDATA

CAL

4/3

18/21

SCLK

XIN

5/4

17/20

VD+

XOUT

6/5

16/19

DGND

MlSLP

7/6

15/18

VA-

CS5505/6 24

BU/uP

817

14117

VA+

AIN1+

9/8

13/16

VREFOUT

10/9

12115

VREF-

11/10

11/14

VREF+

AIN2+INC
AINAIN3+

12

13

i

A1

-

AIN4+

Figure 2. CS5505/6 andCS5507/8.Pin Layouts

CONY signal to transition low to high. This
latches the AO and Al channel selection into the
converter. With CONY high (S2-3 open) the
converter will convert continuously.
Figures 3 and 4 illustrate the evaluation board
layout while Figure 5 illustrates the component
placement (silkscreen) of the evaluation board.

DS59DB2

2-485

i

I
!

CDB5505/5506/5507/5508

Figure 3. Top Ground Plane Layer (NOT TO SCALE)

2-486

DS59DB2

-____-_

.. ...-..
-. ..--_

CDB5505/5506/5507/5508

••••••••••

..

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I

•••••••••••

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............
••••••••••••

•••••••••••·I-------:~;;===!=;;=~..,
Figure 4. Bottom Trace Layer (NOT TO SCALE)

DS59DB2

•
•

e e
e e
•

•
2-487

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VREF - 1.5 LSB

VREF - 1.5 LSB

8000

VREF/2 - 0.5 LSB

TFFF

+0.5 LSB

0001
0000

-VREF +0.5 LSB

«+0.5 LSB)

0000

«-VREF +0.5 LSB)

-0.5 LSB

Note: Table excludes common mode voltage on the
signal and reference inputs.
Table 1. Output Coding

component which is O.S volts above the maximum input of 3.0 (3.5 volts peak; 3.0 volts dc
plus 0.5 volts peak noise) and still accurately
convert the input signal (XIN = 32.768 kHz).
This assumes that the signal plus noise amplitude stays within the supply voltages.
The CSSS09 converters output data in binary
format when converting unipolar signals and in
offset binary format when converting bipolar signals. Table 1 outlines the output coding for both
unipolar and bipolar measurement modes.
Converter Performance
The CSSS09 AID converter has excellent linearity performance. Calibration minimizes the
errors in offset and gain. The CSSS09 device
has no missing code performance to 16-bits.
Figure 4 illustrates the DNL of the CSSS09. The
converter achieves Common Mode Rejection
(CMR) at dc of lOS dB typical, and CMR at SO
and 60 Hz of 120 dB typical.
The CSSS09 can experience some drift as temperature changes. The CSSS09 uSeS
chopper-stabilized techniques to minimize drift.
Measurement errors due to offset or gain drift
can be eliminated at any time by recalibrating
the converter.

DS125F1

-___

.._--. ..--_._.
...-.
+1:

CS5509

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o

32.75e

55.535

Codes

Figure 4. CS5509 Differential Nonlinearity plot.

Analog Input Impedance Considerations
The analog input of the CS5509 can be modeled
as illustrated in Figure 5. Capacitors (15 pF
each) are used to dynamically sample each of the
inputs (AIN+ and AIN-). Every half XIN cycle
the switch alternately connects the capacitor to
the output of the buffer and then directly to the
AIN pin. Whenever the sample capacitor is
switched from the output of the buffer to the
AIN pin, a small packet of charge (a dynamic
demand of current) is required from the input
source to settle the voltage of the sample capacitor to its final value. The voltage on the output
of the buffer may differ up to 100 mV from the
actual input voltage due to the offset voltage of
the buffer. Timing allows one half of a XIN
clock cycle for the voltage on the sample capacitor to settle to its final value.

AIN+ 0 - - - - - - . - - - - - - 0 "
15 pF

IAIN- 0 - - - - - - . - - - - - - 0 "

Intemal
Bias
Voltage'
15 pF

An equation for the maximum acceptable source
resistance is derived.
-1
V

RSmax=

2XIN (l5pF + CEXT)ln V +
e

15P;(100m~

1

(15pF + CEXT

This equation assumes that the offset voltage of
the buffer is 100 mV, which is the worst case.
The value of Ve is the maximum error voltage
which is acceptable. CEXT is the combination of
any external or stray capacitance.
For a maximum error voltage (Ve) of 10 J!V in
the CS5509 (l/4LSB at 16-bits), the above equation indicates that when operating from a
32.768 kHz XIN, source resistances up to
110 kQ are acceptable in the absence of external
capacitance (CEXT =0).
The VREF+ and VREF- inputs have nearly the
same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input impedance applies to the voltage reference inputs as
well.

Figure 5. Analog Input Model

DS125F1

2-501

.-_
_
..--_._.
__.._-_
...-.

CS5509

O~~--------------------------.
,

-20

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=32.768kHz
=330.00kHz

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Frequency
(Hz)

Notch
Depth
(dB)

Frequency
(Hz)

Minimum
Attenuation
(dB)

50

125.6

50±1%

55.5

60

126.7

60±1%

58.4

100

145.7

100±1%

62.2

120

136.0

120±1%

68.4

150

118.4

150±1%

74.9

180

132.9

180±1%

87.9

200

102.5

200±1%

94.0

240

108.4

240±1%

104.4

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-140

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0
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40
80
120
160
200
240
402.83 805.66 1208.5 1611.3 2014.2 2416.9
Frequency (Hz)

Table 2. Filter Notch Attenuation (XIN = 32.768 kHz)

Figure 6. Filter Magnitude Plot to 260 Hz

180
-20

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o

5

10

15

20

25

30

35

40

45

50

Frequency (Hz)

Figure 7. Filter Maguitude Plot to 50 Hz

Digital Filter Characteristics

The digital filter in the CS5509 is the combination of a comb filter and a low pass filter. The
comb filter has zeros in its transfer function
which are optimally placed to reject line interference frequencies (50 and 60 Hz and their
multiples) when the CS5509 is clocked at
32.768 kHz. Figures 6, 7 and 8 illustrate the
magnitude and phase characteristics of the filter.
2-502

~

,Frequency dB '
1
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5

10

15

20

25

30

35

40

45

50

Frequency (Hz)

Figure 8. Filter Phase Plot to SO Hz

Figure 6 illustrates the filter attenuation from dc
to 260 Hz. At exactly 50, 60, 100, and 120 Hz
the filter provides over 120 dB of rejection. Table 2 indicates the filter attenuation for each of
the potential line interference frequencies when
the converter is operating with a 32.768 kHz
clock. The converter yields excellent attenuation
of these interference frequencies even if the fundamental line frequency should vary ± 1% from
DS125F1

.._-_
_.-_..--_._.
__
...-.
its specified frequency. The -3dB corner frequency of the filter when operating from a
32.768 kHz clock is 17 Hz. Figure 8 illustrates
that the phase characteristics of the filter are precisely linear phase.
If the CS5509 is operated at a clock rate other

than 32.768 kHz, the filter characteristics, including the comb filter zeros, will scale with the
operating clock frequency. Therefore, optimum
rejection of line frequency interference will occur with the CS5509 running at 32.768 kHz.
Anti-Alias Considerations for Spectral
Measurement Applications

Input frequencies greater than one half the output word rate (CONV = 1) may be aliased by the
converter. To prevent this, input signals should
be limited in frequency to no greater than one
half the output word rate of the converter (when
CONY =1). Frequencies close to the modulator
sample rate (XIN/2) and multiples thereof may
also be aliased. If the signal source includes
spectral components above one half the output
word rate (when CONY = 1) these components
should be removed by means of low-pass filtering prior to the AID input to prevent aliasing.
Spectral components greater than one half the
output word rate on the VREF inputs (VREF+
and VREF-) may also be aliased. Filtering of the
reference voltage to remove these spectral components from the reference voltage is desirable.
Crystal Oscillator

The CS5509 is designed to be operated using a
32.768 kHz "tuning fork" type crystal. One end
of the crystal should be connected to the XIN
input. The other end should be attached to
XOUT. Short lead lengths should be used to
minimize stray capacitance.

CS5509

with other crystals in the range of 30 kHz to 53
kHz. The chip will operate with external clock
frequencies from 30 kHz to 330 kHz over the industrial temperature range. The 32.768 kHz
crystal is normally specified as a time-keeping
crystal with tight specifications for both initial
frequency and for drift over temperature. To
maintain excellent frequency stability, these crystals are specified only over limited operating
temperature ranges (i.e. -10°C to +60 0c) by the
manufacturers. Applications of these crystals
with the CS5509 does not require tight initial
tolerance or low tempco drift. Therefore, a lower
cost crystal with looser initial tolerance and tempco will generally be adequate for use with the
CS5509. Also check with the manufacturer about
wide temperature range application of their
standard crystals. Generally, even those crystals
specified for limited temperature range will operate over much larger ranges if frequency stability
over temperature is not a requirement. The frequency stability can be as bad as ±3000 ppm
over the operating temperature range and still be
typically better than the line frequency (50 Hz or
60 Hz) stability over cycle-to-cycle during the
course of a day.
Serial Interface Logic

The digital filter in the CS5509 takes 1624 clock
cycles to compute an output word once a conversion begins. At the end of the conversion
cycle, the filter will attempt to update the serial
port. Two clock cycles prior to the update
DRDY will go high. When DRDY goes high
just prior to a port update it checks to see if the
port is either empty or un selected (CS = 1). If
the port is empty or unse1ected, the digital filter
will update the port with a new output word.
When new data is put into the port DRDY will
go low.

Over the industrial temperature range (-40 to
+85 0c) the on-chip gate oscillator will oscillate
DS125F1

2-503

.....
---

-____-_

.. ...-.
-. ..--_._.
Reading Serial Data
SDATA is the output pin for the serial data.
When CS goes low after new data becomes
available (DRDY goes low), the SDATA pin
comes out of Hi-Z with the MSB data bit present. SCLK is the input pin for the serial clock.
If the MSB data bit is on the SDATA pin, the
first rising edge of SCLK enables the shifting
mechanism. This allows the falling edges of
SCLK to shift subsequent data bits out of the
port. Note that if the MSB data bit is output and
the SCLK signal is high, the first falling edge of
SCLK will be ignored because the shifting
mechanism has not become activated. After the
first rising edge of SCLK, each subsequent falling edge will shift out the serial data. Once the
LSB is present, the falling edge of SCLK will
cause the SDATA output to go to Hi-Z and
DRDY to return high. The. serial port register
will be updated with a new data word upon the
completion of another conversion if the serial
port has been emptied, or if the CS is inactive
(high).

CS5509

VD+ or GND pins; VD+ must remain more
positive than the GND pin.
Figure 9a illustrates the System Connection Diagram for the CS5509. Note that all supply pins
are bypassed with 0.1 flF capacitors and that the
VD+ digital supply is derived from the VA+ supply. Figure 9b illustrates the CS5509 operating
from a +5Vanalog supply and +3.3V digital
supply.
When using separate supplies for VA+ and VD+,
VA+ must be established first. VD+ should
never become more positive than VA+ under any
operating condition. Remember to investigate
transient power-up conditions, when one power
supply may have a faster rise time.

CS can be operated asynchronously to the
DRDY signal. The DRDY signal need not be
monitored as long as the CS .signal is taken low
for at least two XIN clock cycles plus 200 ns
prior to SCLK being toggled. This ensures that
CS has gained control over the serial port.
Power Supplies and Grounding
The analog and digital supply pins to the
CS5509 are brought out on separate pins to
minimize noise coupling between the analog and
digital sections of the chip. In the digital section
of the chip the supply current flows into the
VD+ pin and out of the GND pin. As a CMOS
device, the CS5509 requires that the supply voltage on the VA+ pin always be more positive
than the voltage on any other pin of the device.
If this requirement is not met, the device can
latch-up or be damaged. In all circumstances the
VA+ voltage must remain more positive than the
2-504

Schematic &Layout Review Service
Conflnn Optimum
Schematic & Layout
Before Building Your

DS125F1

--------..,-- -----------

CS5509

+5V
Analog
Supply

11
VA+
Optional
Clock
Source

13
VD+

4
- - - ,--:-.. XIN

SCLK

;=b;

95

I ~14~_.f~;;-;;!1
~
Serial

_ _~
SDATA 1--15

32.768 kHz- XOUT

Data
Interface

CS5509
Analog o-_ _ _ _ _ _ _-=--7~ AIN+
Signal

8

AIN-

CS~1_--;

CONV~2-----i
3
CALI4--=------i
+f---------"-9-.t VREF+
Voltage
Reference
10
-I----------'-~ VREF-

BP/UPI4--"-6-----i

Control
Logie

DRDY 1--1_6_ _~
GND

112

.---------------------------~

Figure 9a. System Connection Diagram Using a Single Supply

DS125F1

2-505

i

i

_.-_....,-__.._-_
...-.
.~.

CS5509

Note: VD+ must never be more positive than VA+
r----___._--Q

o~

+5V
Analog
Supply
Optional
Clock
Source

11

13

VA+

VD+

4
... .,-:-. XIN

~

+3.3V to +5V
Digital
Supply

1 ~14~__~~~~
SCLK 1+
Serial

*T5

SDATA f----1_5_--.t

32.768 kHz~ XOUT

Data
Interface

CS5509

Analog ~o-_ _ _ _ _ _ _ _-,-7~ AIN+
Signal

8

AINCS 1+-1_ _-1
CONV 1+-=-2_ _-1
3 _ _-1
CAL 14-

+f----_ _ _ _ _ _...:9~ VREF+
Voltage
Reference

10

-f------~--'-~

BP/UP 14---"'-.6_ _-1

Control
Logic

DRDY f----1..:..6_ _~

VREFGND

112

.--------------~

Figure 9b. System Connection Diagram Using Split Supplies

2-506

DS125F1

-____-_

.. ...-.
-. ..--_._.

CS5509

PIN DESCRIPTIONS*
CHIP SELECT

CS

CONVERT

CONY

CALIBRATE

CAL

CRYSTAL IN

XIN

DRDY

DATA READY

SDATA

SERIAL DATA OUTPUT

SCLK

SERIAL CLOCK INPUT

VD+

POSITIVE DIGITAL POWER

-

CRYSTAL OUT

XOUT

GND

GROUND

BIPOLAR/UNIPOLAR

BP/uP

VA+

POSITIVE ANALOG POWER

DIFFERENTIAL ANALOG INPUT

AIN+

VREF-

VOLTAGE REFERENCE INPUT

DIFFERENTIAL ANALOG INPUT

AIN-

VREF+

VOLTAGE REFERENCE INPUT

·Pinout applies to both PDIP and SOIC

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 4, 5.
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).
Serial Output I/O

CS - Chip Select, Pin 1.
This input allows an external device to access the serial port.
DRDY - Data Ready, Pin 16.
Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high· after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).
SDATA - Serial Data Output, Pin 15.
SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK. Data is output MSB first and advances to the next data bit on the falling
edges of SCLK. SDATA will be in a high impedance state when not transmitting data.
SCLK - Serial Clock Input, Pin 14.
A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin
must not be allowed to float.

DS125F1

2-507

----------------------

CS5509.

Control Input Pins

CAL - Calibrate, Pin 3.
When taken high the same time that the CONV pin is taken high the converter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.
CONY - Convert, Pin 2.
The CONY pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If CONY
is held high (CAL low) the converter will do continuous conversions.
BPIUP - BipolarlUoipolar, Pin 6.
The BP/uP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.
Measurement and Reference Inputs

AIN+, AIN- - Differential Analog Inputs, Pins 7, 8.
Analog differential inputs to the delta-sigma modulator.
VREF+, VREF- - Differential Voltage Reference Inputs, Pins 9, 10.
A differential voltage reference on these pins operates as the voltage reference for the converter.
The voltage between these pins can be any voltage between 1.0 and 3.6 volts.
Power Supply Connections

VA+ - Positive Analog Power, Pin 11.
Positive analog supply voltage. Nominally +5 volts.
VD+ - Positive Digital Power, Pin 13.
Positive digital supply voltage. Nominally +5 volts or +3.3 volts.
GND - Ground, Pin 12.
Ground.

2-508

DS125F1

----------------------

CS5509

SPECIFICATION DEFINITIONS
Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the NO
Converter transfer function. One endpoint is located 112 LSB below the first code transition
and the other endpoint is located 112 LSB beyond the code transition to all ones. Units in
percent of full-scale.
Differential Nonlinearity
The deviation of a code's width from the ideal width. Units in LSBs.
Full Scale Error
The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} are in LSBs.

% LSB]. Units

Unipolar Offset
The deviation of the first code transition from the ideal (h LSB above the voltage on the AINpin.) when in unipolar mode (BP/uP low). Units are in LSBs.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100... 000) from the ideal (1;2 LSB below
the voltage on the AIN- pin.) when in bipolar mode (BPIUP high). Units are in LSBs

DS125F1

2-509

-I

--------..,-- -----------

CS5509

APPENDIX
The following companies provide 32.768 kHz crystals in many package varieties and temperature
ranges.
Fox Electronics
5570 Enterprise Parkway
Fort Meyers, FL 33905
(813) 693-0099
Micro Crystal Division / SMH
702 West Algonquin Road
Arlington Heights, IL 60005
(708) 806-1485
SaRonix
4010 Transport Street
Palo Alto, California 94303
(415) 856-6900
Statek
512 North Main
Orange, California 92668
(714) 639-7810
IQD Ltd.
North Street
Crewkerne
Somerset TA18 7AK
England
0146077155

Taiwan X'tal Corp.
5F. No. 16, Sec 2, Chung Yang S. RD.
Reitou, Taipei, Taiwan R. O. C.
Tel: 02-894-1202
Fax: 02-895-6207
Interquip Limited
241F Million Fortune Industrial Centre
34-36 Chai Wan Kok Street, Tsuen Wan N T
Tel: 4135515
Fax: 4137053
S& T Enterprises, Ltd.
Rm404 BlkB
Sea View Estate
North Point, Hong Kong
Tel: 5784921
Fax: 8073126
Mr. Darren Mcleod
Hy-Q International Pty. Ltd.
12 Rosella Road,
FRANKSON,3199
Victoria, Australia
Tel: 61-3-783 9611
Fax: 61-3-783 9703

Mr. Pierre Hersberger
MicrocrystallDIY. ETA S.A.
Schild-Rust-Strasse 17
Grenchen CH-2540
Switzerland
065530557

2-510

DS125F1

..........
..............
.., ........
~

CDB5509

Semiconductor Corporation

Evaluation Board for the CS5509 AID Converter
Features

General Description
The COB5509 is a circuit board designed to provide
quick evaluation of the C85509 AID converter.

• Operation with on-board 32.768 kHz
crystal or off-board clock source

The board provides buffered digital signals, an onboard precision voltage reference, options for using an
external clock, and a momentary switch to initiate calibration.

• DIP Switch Selectable:
BP/UP mode

• On-board precision voltage reference

• Access to all digital control pins
ORDERING INFORMATION: COB5509

B
U
CS5509

F
F
E
R

S

+5V

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

H
E
A

o
E

R

GND

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
081250B1
2-511

_'ii.

DIll

....,..,..,
._..
...,.---....
..,.., .....

CDB5509

Introduction
The CDBSS09 evaluation board provides a quick
means of testing the CSSS09 AID converter. The
CSSS09 converter requires a minimal amount of
external circuitry. The evaluation board comes
configured with the AID converter chip operating
from a 32.768 kHz crystal and with an off-chip
precision 2.S volt reference. The board provides
access to all of the digital interface pins of the
CSSS09 chip.

Evaluation Board Overview
The board provides a complete means of making
the CSSS09 NO converter chip function. The
user must provide a means of taking the output
data from the board in serial format and using it
in his system.

applications will not require the buffer ICs for
proper operation.
To put the board in operation, select either bipolar or unipolar mode with DIP switch S2. Then
press the CAL pushbutton after the board is
powered up. This initiates calibration of the converter which is required before measurements
can be taken. With CONY high (S2-3 open) the
converter will convert continuously. Figure 3 il~
lustrates the CABSS09 adapter board. The
CABS509 translates a CSSSOS pinout to a
CSS509 pinout.
Figures 4 and S illustrate the evaluation board
layout while Figure 6 illustrates the component
placement (silkscreen) of the evaluation board.

Figure 1 illustrates the schematic for the board.
The board comes configured for the NO converter chip to operate from the 32.768 kHz
watch crystal. A BNC connector for an external
clock is provided on the board. To connect the
external BNC source to the converter chip, a circuit trace must be cut. Then a jumper must be
inserted in the proper holes to connect the XIN
pin of the converter to the input line from the
BNC. The BNC input is terminated with a son
resistor. Remove this resistor if driving from a
logic gate. See the schematic in Figure .1.
The board comes with the AID converter VREF+
and VREF- pins hard-wired to the 2.S volt
bandgap voltage reference IC on the board.
All of the control pins of the CSSS09 are available at the 11 header connector. Buffer ICs U2
and U3 are used to buffer the converter for interface to off-board circuits. The buffers are used
on the evaluation board only because the exact
loading and off-board circuitry is unknown. Most
2-512

DS125D81

c

....rn
I\)

en

+5

C

10

m
....
+5V

((j)iI--.-,- - - - 1 > - - r - - - - .+5
-

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V

+51

1<:~' II •

T 'VV'v

RII
lOOk

,------o-.AGND
GND

(1j)

•

,

6

DGND

VD+

VA+

CAL 13

II

r

VREF+

csl· •

··C

+5

Ul
CS5509

Extemal
VREF

_0

0

DRDYI·W,

3B

··1
SDATA

SClKO

SClKI

BP/UP

AIN+

AIN~

flI-~
~
R31
lOOk

R12
lOOk

1
I-,;.~
T

R4

TP6

7

CI5
TPI5
~
O.OlI1F

R13

~
=

ClKIN

R3

50

U2 74HC4050

81 AIN-

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CONY
CAL
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XOUT

OROY
SOATA
SCLK
VO+
GNO
VA+
VREFVREF+

BP/uP

AIN+
AIN-

Figure 2. CS5509 Pin Layout

(Top View)

Figure 3. CAB5509 Adapter Board

2-514

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The CS5516 and CS5520 sample at a rate set by the
user in the form of either an external CMOS clock or a
crystal. On-chip digital filtering provides rejection of all
frequencies above 12Hz for a 4.096 MHz clock.

• System Calibration Capability with
calibration read/write option
• 3, 4 or 5 wire Serial Communications
Port
• Low Power Consumption: 40mW
10j..lW Standby Mode for Portable
applications

The CS5516 and CS5520 include system calibration to
null offset and gain errors in the input channel. The
digital values associated with the system calibration
can be written to, or read from, the calibration RAM
locations at any time via the serial communications
port. The 4-bit DC offset D/A converter, in conjunction
with digital correction, is initially used to zero the input
offset value.
ORDERING INFORMATION:

AIN+
AIN-

VA+

VA-

AGND1

AGND2

3

4

5

8

MDRV+

Gain
Block
1,2,4,8

IN1

MDRV-

VD+

VD-

DGND

20

21

19

OUT1

2·Channel
Delta·Sigma
Modulator

>---,---+--........- - - - - 0 1 IN2

Page 2-547

2-Channel
FIR
Filter

OUT2

___ I
f--~1=8-o¢ SOD

BX1

17

BX2

XIN

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 : Fax (512) 445 7581

XOUT

SMODE SCLK

SID

DRDY

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS74F1
2-519

----------- -----------

CS5516

ANALOG CHARACTERISTICS (TA = TMIN to TMA)G VA+, VD+, MDRV+ = 5V; VA-, VD- = -5V;
VREF= 2.5V(external differential voltage across VREF+ and VREF-); fCLK = 4.9152 MHz;
AC Excitation 300 Hz; Gain = 25; Bipolar Mode; Rsource = 300n with a 4.7nF to AGND at AIN (see Note 1);
unless otherwise specified.)
Parameter"

Min

Specified Temperature Range

Typ

Max

-40 to +85

Units

°C

Accuracy

Unipolar Offset

(Note 2)

-

Bipolar Offset

(Note 2)

-

±1

±2

-

±0.005

-

Linearity Error
Differential Nonlinearity
Unipolar Gain Error

(Note 2)

Bipolar Gain Error

(Note 2)

Unipolar/Bipolar Gain Drift

Offset Drift
Noise (Referred to Input)

Notes:

Gain = 25
Gain = 50
Gain = 100
Gain = 200

(25
(25
(25
(25

x
x
x
x

1)
2)
4)
8)

0.0015

0.003

±%FS

±0.25

±0.5

LSB16

±8

±31

ppm

±8

±31

ppm

±1

-

ppml"C

±1

±2

LSB16
LSB16

250
200
150
150

-

-

-

IlV/oC
nVrms
nVrms
nVrms
nVrms

1. The AIN and VREF pins present a very high Input resistance at dc and a minor dynamic load which
scales to the master clock frequency. Both source resistance and shunt capacitance are therefore
critical in determining the source impedance requirements of the CS5516 and CS5520 at these pins.
2. Applies after system calibration at the temperature of interest.

IlV
0.4
0.76
1.52
3.04
6.08

LSB's
0.26
0.50
1.00
2.00
4.00

Unipolar Mode
% FS
0.0004
0.0008
0.0015
0.0030
0.0061
VREF = 2.5V

ppm FS
4
8
15
30
61

LSB's
0.13
0.26
0.50
1.00
2.00

Bipolar Mode
% FS
0.0002
0.0004
0.0008
0.0015
0.0030
PGA gain = 1

ppm FS
2
4
8
15
30

CS5516; 16-Bit Unit Conversion Factors

* Refer to the SpeCification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.

2-520

DS74F1

----------------------

CS5520

I

ANALOG CHARACTERISTICS (continued)

I

Parameter·

Min

Specified Temperature Range

Typ

Max

-40 to +85

Units

°C

Accuracy

-

0.0007

0.0015

+%FS

20

-

-

Bits

Linearity Error
Differential Nonlinearity

(No Missing Codes)

Unipolar Gain Error

(Note 2)

-

±4

±24

ppm

Bipolar Gain Error

(Note 2)

-

±4

±24

ppm

-

Unipolar/Bipolar Gain Drift

±1

-

ppml°C

±4

±8

LSB20

±4

±8

LSB20

Unipolar Offset

(Note 2)

Bipolar Offset

(Note 2)

-

±O.005

(25
(25
(25
(25

-

250
200
150
150

Offset Drift
Noise (Referred to Input)

IlV
0.025
0.047
0.095
0.190
0.380

LSB's
0.26
0.50
1.00
2.00
4.00

Gain = 25
Gain = 50
Gain = 100
Gain = 200

Unipolar Mode
%FS

0.0000238
0.0000477
0.0000954
0.0001907
0.0003814
VREF = 2.5V

ppm FS
0.25
0.50
1.0
2.0
4.0

x
x
x
x

1)
2)
4)
8)

LSB's
0.13
0.26
0.50
1.00
2.00

Bipolar Mode
%FS
0.0000119
0.0000238
0.0000477
0.0000954
0.0001907
PGA gain = 1

-

IlV/o C

-

nVrms
nVrms
nVrms
nVrms

-

ppm FS
0.125
0.25
0.50
1.0
2.0

CS5520; 20-Bit Unit Conversion Factors

* Refer to the Specification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.
DS74F1

2-521

.I

_.--..--_._.
__.._-_
...-.

CS5516, CS5520

ANALOG CHARACTERISTICS (continued)
Parameter

Min

Specified Temperature Range

Typ

Max

Units

-40 to +85

°C

12.5, 25, 50, 100
±12.5, ±25, ±50, ±100

mV
mV

-

dB
dB

Analog Input
Analog Input Range

Unipolar
Bipolar

Common Mode Rejection

dc
50,60 Hz

Input Capacitance
Input Bias Current

(Note 1)

-

-

165
200

5
100

pF
pA

Instrumentation Amplifier
Bandwidth

-

200

Unity Gain Bandwidth

-

5

Output Slew Rate

-

XIN/128

-

-

±1

-

%

-

±5

-

%

(Note 6)

2.0

2.5

3.8

V

dc
50,60 Hz

-

60
200

-

dB

Gain

Noise @ 10 Hz BW
Power Supply Rejection @ 50/60 Hz

(Note 3)

Common Mode Range

(Note 4)

Chopping Frequency

25

1.5
100
120
±3

kHz
MHz
V/llsec

nVrms
dB
V
Hz

Programmable Gain Amplifier
(Note 5)

Gain Tracking

4·Bit Offset Trim DAC
Accuracy

Voltage Reference Input
Range
Common Mode Rejection:
Input Capacitance
Input Bias' Current
Notes:

2·522

..

(Note 1)

15
10

pF
nA

3. ThIs Includes the on-chIp dIgItal filtering.
4. The maximum magnitude of the differential input voltage, Vdiff(in) is determined by the following:
Vdiff(in) < 300 mV - IVcm/12.5 I and should never exceed300mV.
Vcm is the common mode voltage which is applied to the instrumentation amplifier inputs.
The above equation should be used to calculate the allowable common mode voltage for a given
differential voltage applied to the first gain stage inputs. This limit ensures
that the instrumentation amplifier does not saturate.
5. Gain tracking accuracy can be significantly improved by uploading a calibrated gain word to the
gain register for each PGA gain selection.
6. The common mode voltage on the Voltage Reference Input, plus the reference range,
[(VREF+) - (VREF-)]/2, must not exceed ±3 volts.

DS74F1

.-_
_
..---._.
__.._-_
...-.

CS5516, CS5520

ANALOG CHARACTERISTICS (continued)
Parameter

Min

Typ

Max

Units

Modulator Differential Voltage Reference
Nominal Output Voltage

-

3.75

Initial Output Voltage Tolerance

-

±100

-

100

(4.75V < VA < 5.25V)

Output Voltage Noise

0.1 to 15 Hz

-

10

-

Output Current Drive:

Source Current
Sink Current

-

-

20
20

I1A

-

2.7
-2.7
1.5
-0.6

3.5
-3.5
2.2
-O.B

mA
mA
mA
mA

37.5
10

-

mW
I1W

Temperature Coefficient
Line Regulation

0.5

V
mV
ppm/DC
mVN
I1Vp-p

j.lA

Power Supplies
DC Power Supply Currents

IA+
IAID+
ID-

Power Dissipation:

Power Supply Rejection:

(Note 7)
Normal Operation
Standby Mode
dc
dc

-

-

-

100
95

-

-

dB
dB

(Note B)
Unipolar Mode
Bipolar Mode

O.BT
O.BT

-

1.2T
1.2T

V
V

(Note B)
Unipolar Mode
Bipolar Mode

-2T
-2T

-

-

+2T
+2T

V
V

Positive Supplies
Negative Supplies

System Calibration Specifications
Positive Full Scale Calibration Range

Maximum Ratiometric Offset Calibration Range

Differential Input Voltage Range

Notes:

(Notes 4, B, 9, 10)
Unipolar Mode
Bipolar

Voffset + (1.2T)
Voffset ± (1.2T)

V
V

7. All outputs unloaded. All inputs CMOS levels.
B. T=VREF/(Gx25), where T is the full scale span, where VREF is the differential voltage across
VREF+ and VREF- in volts, and G is the gain setting of the second gain block. G can be set
to 1, 2, 4, B. This sets the overall gain to 25, 50, 100, 200. The gain can then be fine tuned by
using the calibration of the full scale point.
9. When calibrated.
10. Voffset is the offset corrected by the offset calibration routine. Voffset may be as large as 2T.

DS74F1

..
I

2-523

i

_.-_..--__.._-_
...
._.-.

CS5516, CS5520

DYNAMIC CHARACTERISTICS
Symbol

Ratio

Units

AIN and VREF Input Sampling Frequency

Parameter

fis

fcllJ128

Hz

Modulator Sampling Frequency

fs

fcrkl2S6

Hz

fout

fcrkl81 ,920

Hz

f·3dB

fcrkl341 ,334

Hz

ts

6/fout

s

Output Update Rate
Filter Corner Frequency
Settling Time to ±0.0007%

(FS Step)

DIGITAL CHARACTERISTICS (TA= TMrN to TMAX; VA+, VD+ = SV±S%; VA·, VD· = ·SV±S%;
DGND = 0) All measurements below are performed under static conditions.
Symbol

Min

Typ

Max

Units

High·Level Input Voltage:

XIN
All Pins Except XIN

VrH
VrH

4.S
2.0

.

.

-

-

V
V

Low-Level Input Voltage

XIN
All Pins Except XIN

VrL
VrL

-

O.S
0.8

V
V

High-Level Output Voltage

(Note 11)

VOH

(VD+)-1.0

Low-Level Output Voltage

lout = 1.6mA

VOL

1

10

-

~

±10

!lA

9

-

pF

Parameter

Input Leakage Current

lin

3-State Leakage Current

loz

Digital Output Pin Capacitance

Cout

-

-

V

0.4

V

Notes: 11. lout = -100!lA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ lout = -40 !lA).

2-524

DS74F1

.._-_
.-_
_
..--_._.
__
...-.

CS5516, CS5520

RECOMMENDED OPERATING CONDITIONS (AGND,
Parameter
DC Power Supplies:

Positive Digital
Negative Digital
Positive Analog
Negative Analog

Differential Analog Reference Voltage
Analog Input Voltage:

DGND = OV, see Note 12.)

Symbol

Min

Typ

Max

Units

VD+
VDVA+
VA-

4.5
-4.5
4.5
-4.5

5.0
-5.0
5.0
-5.0

5.5
-5.5
5.5
-5.5

V
V
V
V

(VREF+) - (VREF-)

2.0

2.5

3.8

V

VAIN
VAIN

0
-T

-

+T
+T

V
V

(Note 13)
Unipolar
Bipolar

Notes: 12. All voltages with respect to ground.
13. The CS5516 and CS5520 can accept input voltages up to +T in unipolar mode and -T to +T in bipolar
mode where T =VREF/(Gx25). G is the gain setting at the second gain block. When the inputs exceed
these values, the CS5516 and CS5520 will output positive full scale for any input above T, and
negative full scale for inputs below AGND in unipolar and -T in bipolar mode. This applies when the
analog input does not exceed ±2T overrange.

ABSOLUTE MAXIMUM RATINGS*

(AGND, DGND = OV, all voltages with respect to ground.)

Parameter
DC Power Supplies:

Positive Digital
Negative Digital
Positive Analog
Negative Analog

Input Current, Any Pin Except Supplies
Analog Input Voltage

(Notes 15, 16)

AIN and VREF pins

Digital Input Voltage
Ambient Operating Temperature

(Note 14)

Symbol

Min

Typ

Max

Units

VD+
VDVA+
VA-

-0.3
-0.3
-0.3
+0.3

-

(VA+)+0.3
-5.5
5.5
-5.5

V
V
V
V

lin

-

±10

rnA

VINA

(VA-)-0.3

VIND

-0.3

TA

-55

-

(VA+)+0.3

V

(VD+)+0.3

V

125

°C

-

Storage Temperature
-65
150
Tstg
°C
..
Notes: 14. No pm should go more positive than (VA+)+0.3V. VD+ must always be less than (VA+)+O.3 V,and
can never exceed 6.0V.
15. Applies to all pins including continuous overvoltage conditions at the analog input pins.
16. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ± 50 rnA .
• WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

DS74F1

2·525

--------..,-- -------_._-

CS5516, CS5520

CS
SID

SCLK

SID Write Timing (Not to Scale)

DRDY

\L--____________::___--11

CS~ ________________~~--~;SOD

~t71 _ _

-1

MSB fMSB-1

.f= t8

X~_~XL--_-----'

SCLK
SOD Read Timing (Not to Scale)

DRDY

SOD

IL-________________________________

--;L____

~~

I

~~--------~

----'I'------''------''------'L--~~

F";{~

SCLK

'i.

SOD Read Timing with CS = 0 (Not to Scale)

CS
SCLK

"-

IL-~--------~~~---------+~I

lrL

CS with Continuous SCLK (Not to Scale)

2-526

DS74F1

----------------------

CS5516, CS5520

SWITCHING CHARACTERISTICS
VA-, VD-

= -5V±5%;

Input Levels: Logic 0

,

(TA = TMIN to TMAX; VA+, VD+ = 5V ± 5%;
CL = 50 pF)

= OV, Logic 1 = VD+;

Parameter

Master Clock Frequency: Internal Oscillator I External Clock

Symbol

Min

Typ

Max

Units

XIN

1.0

4.096

5.0

MHz

40

-

60

%

1.0

Jls
ns

-

1.0

50

-

Jls
ns

-

ms

Master Clock Duty Cycle
Rise Times
Fall Times

Any Digital Input
Any Digital Output

(Note 18)

Any Digital Input
Any Digital Output

(Note 18)

trise
tfall

-

50

-

Startup

-

100

tost
tres

11XIN

-

SCLK

-

MHz

200
200

-

2.4

tl
t2

-

ns
ns

CS Enable to Valid Latch Clock

t3

150

-

ns

Data Set-up Time prior to SCLK rising

4

50

-

ts

50

-

SCLK Falling Prior to CS Disable

ts

50

-

-

ns

Data Hold Time After SCLK Rising

150

ns

170

ns

200

ns

150

ns

150

ns

-

ns

-

ns

Power-on Reset Period
Oscillator Start-up Time

tpor
XTAL = 4.9152 MHz (Note 19)

RST Pulse Width

60

ms
ns

Serial Port Timing
Serial Clock Frequency
Serial Clock

Pulse Width High
Pulse Width Low

-

SID Write Timing

ns
ns

SOD Read Timing
CS to Data Valid

t7

-

SCLK Falling to New Data Bit

ts

-

hl

-

CS Disable Hold Time

h2

50

-

CS Enable Set-up Time

t13

150

-

CS Enable Hold Time

t14

50

-

SCLK Falling to SOD Hi-Z
DRDY Falling to Valid Data
CS Rising to SOD Hi-Z

t9
(CS = 0)

ho

ns

ns
150
hs
Notes: 18. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
19. Oscillator start-up time varies with crystal parameters. This specification does not apply when using
an external clock source.
CS Disable Set-up Time

DS74F1

2-527

.._-_
-.-_..__
...-.
.",--.~.

CS5516, CS5520

GENERAL DESCRIPTION
coarse offset trimming, circuitry for generation
and demodulation of AC (actually switched DC)
bridge excitation, and a serial port. The CS5516
outputs 16-bit words; the CS5520 outputs 20-bit
words.

The CS5516 and CS5520 are monolithic CMOS
AID converters which include an instrumentation
amplifier input, an on-chip programmable gain
amplifier, and a DAC for offset trimming. While
the devices are optimized for ratiometric measurement of Wheatstone bridge applications, they
can be used for general purpose low-level signal
measurement.

The CS5516120 devices can measure either
unipolar or bipolar signals. Self-calibration is
utilized to maximize performance of the measurement system. To better understand the
capabilities of the CS5516/20, it is helpful to examine some of the error sources in bridge
measurement systems.

Each of the devices includes a two-channel differential delta-sigma modulator (the signal
measurement input and the reference input are
digitized independently before a digital output
word is computed), a calibration microcontroller,
a two-channel digital filter, a programmable instrumentation amplifier block, a 4-bit DAC for
+5V
Analog
Supply

100
0.1 IlF
VA+
MDRV-

VD+
XOUT

MDRV+
12
Excitation Supply
Synch. Signals

11

BX1

CS5516
BX2 CS5520
SCLK

9

VREF+

SOD
SID

10
6
7
5

Optional
Clock
Source

XIN

VREFAIN+
AIN-

SMODE
DRDY
RST

16
18
17
24

Serial
Data
Interface

15
13
14

Control
Logic

Unused logic inputs
must be connected
to DGND or VD+
-5V
Analog
Supply

Figure 1. System Connection Diagram: AC Excitation Mode Using External Excitation

2-528

DS74F1

.-_
_
..--_._.
__.._-_
...-.

CS5516, CS5520

THEORY OF OPERATION
After the programmable gain block, the output
of a 4-bit DAC is combined with the input signal. The DAC can be used to add or subtract
offset from the analog input signal. Offsets as
large as ±200 % of full scale can be trimmed
from the input signal.

The front page of this data sheet illustrates the
block diagram of the CS5516 and CS5520 AID
converter. The device includes an instrumentation amplifier with a fixed gain of 25. This
chopper-stabilized instrumentation amplifier is
followed by a programmable gain stage with
gain settings of 1, 2, 4, and 8. The sensitivity of
the input is a function of the programmable gain
setting and of the reference voltage connected
between the VREF+ and VREF- pins of the device. The full scale of the converter is VREF/( G
x 25) in unipolar, or ±VREF/(G x 25) in bipolar,
where VREF is the reference voltage between
the VREF+ and VREF- pins, G is the gain setting of the programmable gain amplifier, and 25
is the gain of the instrumentation amplifier.

The CS5516 and CS5520 are optimized to perform ratiometric measurement of bridge-type
transducers. The devices support de bridge excitation or two modes of ac (switched dc) bridge
excitation. In the switched-de modes of operation the converter fully demodulates both the
reference voltage and the analog input signal
from the bridge.

10 '1

+5V
Analog
Supply
1 p.F

2

VA+
MDRV-

VD+
23
XOUT

MDRV+

Optional
Clock
Source

XIN
CS5516
CS5520
SCLK
VREF+

SOD
SID

+
VREFAIN+
AIN-

SMODE
DRDY
RST
CS

Unused logic inputs
must be connected
to DGND or VD+

16
18
17
24

Serial
Data
Interface

15
13
14

Control
Logic

DGND

-5V
Analog
Supply

Figure 2. System Connection Diagram: DC Excitation Mode (EXC bit =0), Fl

DS74F1

=FO =O.
2-529

_-_._.-.
.-_
..--_........

CS5516, CS5520

Command Register

BIT

07

06

05

04

1.

RSB2

RSB1

RSBO

NAME

07

07

RSB2-0

Register Select Bit

RIW

ReadlWrite

02
01
DO

02
01
DO

03
R/W

VALUE
1
000
001
010
011
100
101
110
111
0
1
0
0
0

02

01

DO

o

o

o

FUNCTION
Must always be logic 1
Selects Register to be Read or Written per RIW bit
CONVERSION DATA (read only)
CONFIGURATION
GAIN
OAC
RATIOMETRIC OFFSET
NON-RATIOMETRIC OFFSET - AIN
NON-RATIOMETRIC OFFSET - VREF
NOT USED
Write to the register selected by the RSB2-0 bits
Read from the reaister selected bv the RSB2-0 bits
Not Used
Not Used
Not Used

Table 1. CS5516 and CS5520 Commands

The CS5516/20 includes a microcontroller which
manages operation of the chip. Included in the
microcontroller are eight different registers associated with the operation of the device. An 8-bit
command register is used to interpret instructions
received via the serial port. When power is applied, and the device has beenteset, the serial
port is initialized into the cOIIl1,1land mode. In
this mode it is waiting to receive an 8-bit command via its serial port. The ftrst 8 bits into the
serial port are placed into the command register.
Table 1 lists all the valid command words for
reading from or writing to internal registers of
the converter. Once a valid 8-bit command word
has been received and decoded, the serial port
goes into data mode. In data mode the next 24
serial clock pulses shift data either into or out of
the serial port. When writing data to the port, the
data may immediately follow the command
word. When reading data from the port, the user
must pause after clocking in the 8-bit command
word to allow the microcontroller time to decode
the command word, access the appropriate regis2-530

ter to be read, and present its 24-bit word to the
port. The microcontroller will signal when the
24-bit read data is available by causing the
DRDY pin to go low.
The user must write or read the full 24-bit word
except in the case of reading conversion data. In
read data conversion mode, the user may read
less than 24 bits if CS is then made inactive
(CS = 1). CS going inactive releases user control
over the port and allows new data updates to the
port.
The user can instruct the on-chip microcontroller
, to perform certain operations via the conftguration register. Whenever a new word is written to
the 24-bit conftguration register, the microcontroller then decodes the word and executes the
conftguration register instructions. Table 2 illustrates the bits of the conftguration register. The
bits in the configuration register will be discussed in various sections of this data sheet.
DS74F1

.....
.-..---._.
_
___-_
...-.

CS5516, CS5520

Configuration Register
Register
Reset (RJ

023
DAC3
0

022
DAC2
0

021
DAC1
0

011

010
EC
0

09
09

Register
Reset (RJ

A/S
0

BIT
OAC3

NAME
OAC Sign Bit

OAC2-0

OAC Bits

EXC

Excitation:

Internal
External

F1-FO

Select Frequency

016

016

G1-GO

Select PGA Gain

UIB

0

020
DACO
0
08
08
0

019
0

018
F1
0

017
FO
0

016
016
0

015
G1
0

014
GO
0

013
UlB
0

012
012
0

07
CC3
0

06
CC2
0

05
CC1
0

04
CCO
0

03
03
0

02
02
0

01
01
0

00
RF
0

I EXC

VALUE

FUNCTION

0
1
000
001
010
011
100
101
110
111

Rl

0
1

R

00
01
10
11
0
00
10
01
11
0
1
0

R

012

Select UnipolarlBipolar Mode
012

AlS

Awake/Sleep

EC

Execute Calibration

09

09

0

08
CC3-CCO

08
Calibration Control Bits

0

03

03

0000
1000
0100
0010
0001
0

02

02

0

01

02

0

RF

Reset Filter

0
1

0
1
0
1

Add Offset
Subtract Offset

This bit is read onll

R

R
R

R
R
R
R

R
R
R

R
R
R
R

25% Offset
50% Offset
75% Offset
100% Offset
These bits are read onll
125% Offset
150% Offset
175% Offset
BX1 and BX2 outputs are determined by bits F1 and FO
BX1 is an input which determines the phase of the
demodulation clock and the BX2 output
Excitation on BX1 & BX2 is dc. BX1=0 V. BX2=+5 V
Excitation Frequency on BX1 & BX2 is XIN/8192 Hz
Excitation Frequency on BX1 & BX2 is XINl16384 Hz
Excitation Freauencv on BX1 & BX2 is XIN/4096 Hz
Must always be logic 0
Gain = 1 (X25)
Gain = 2 (X25)
Gain = 4 (X25)
Gain = 8 (X25t
Bipolar Measurement Mode
Unipolar Measurement Mode
Must always be logic 0
Awake Mode
Sleep Mode
Calibration not active
Perform calibration selected by CC3-CCO bits. EC bit
must be written back to "0" after calibration is completed
Must always be logic 0
Must always be logic 0
No calibration to be performed
Calibrate non-ratiometric offset, VREF
Calibrate non-ratiometric offset, AIN
Calibrate ratiometric offset, AIN
Calibrate gain, AIN
Must always be logic 0
Must always be logic 0
Must always be logic 0
Normal operation
Reset Filter

Notes: 1.Reset State
2.A write to these bits does not change the register bit values. These bits are just a mirror of the OAC register contents.

Table 2. Configuration Register
DS74F1

2-531

,.
I

-.-_..--_.-.
__.._-_
...-.

CS5516, CS5520

System Initialization

CALIBRATION

Whenever power is applied to the
CS5516/CS5520 AID converters, the devices
must be reset to a known condition before proper
operation can occur. The internal reset is applied
after power is established and lasts for approximately 100 ms. The RST pin can also be used to
establish a reset condition. The reset signal
should remain low for at least one XIN clock
cycle to ensure adequate reset time. It is recommended that the RST pin be used to reset the
converter if the power supplies rise very slowly
or with poor startup characteristics. The RST
signal can be generated by a microcontroller output, or by use of an R-C circuit.

After the CS5516120 is reset, the device is functional and can perform measurements without
being calibrated. The converter will utilize the
initialized values of the calibration registers to
calculate output.words.

The reset function initializes the configuration
register and all five of the calibration registers;
and places the microcontroller in command
mode ready to accept a command from the serial
port. Whenever the device is reset the DRDY pin
will be set to a logic 1 and the on-chip registers
are initialized to the following states:
Configuration
Calibration registers:
DAC
Gain
AIN Ratiometric Offset
AIN Non-ratiometric Offset
VREF Non-ratiometric Offset

OOOOOO{H)
OOOOOO{H)
800000{H)
OOOOOO{H)
OOOOOO{H)
OOOOOO{H)

The converter uses the two outputs (AIN &
VREF) of the dual channel converter along with
the contents of the calibration registers to compute the conversion data word. The following
equation indicates the computation.
RO=R4 [[ DAIN-Rl ] -R3]
DVREP-R2

Where RO is the output data, DAIN and DVREF
are the digital output words from the AIN and
VREF digital filter channels, and Rl, R2, R3
and R4 are the contents of the following calibration registers:
Rl = AIN non-ratiometric offset
R2 =VREF non-ratiometric offset
R3 =AIN ratiometric offset
R4 =Gain
The computed output word,RO, is a two's complement number.
Calibration minimizes the errors in the converted
output data. If calibration has not been performed, the measurements will include offset and
gain errors of the entire system.
The converter may be calibrated each time it is
powered up, or calibration words from a previous calibration may be uploaded into the
appropriate calibration registers from some type
of E 2PROM by the system microcontroller.
The converter uses five different registers to
store specific calibration information. Each of
the calibration registers stores information pertinent to correcting a specific source of error
associated with either the converter or with the
input transducer and its wiring. The method by

2-532

DS74F1

----------------------

CS5516, CS5520

Conti ~uration Register
EC
1
1
1
1
1
0

CC3
1
0
0
0
1
X

CC2
0
1
0
0
1
X

CC1
0
0
1
0
0
X

CCO
0
0
0
1
0
X

5R5Y remains high through calibration sequence.

CAL Type

Calibration Time

VREF Non-ratiometric Offset
AIN Non-ratiometric Offset
AIN Ratiometric Offset
AIN System Gain
VREF & AIN Non-ratiometric Offset
End Calibration

573 440/felk
573 440/fclk
2 211 840/fclk
573,440/felk
573,440/fclk

-

In all modes, DRDY falls immediately upon completion of the calibration

sequence.

Table 3. CS55161CS5520 Calibration Control

which calibration is initiated is common to each
of the calibration registers. The configuration
register controls the execution of the calibration
process. Bits CC3--CCO in the configuration
register determine which type of calibration will
be performed and which of the five calibration
registers will be affected. On the falling edge of
the 24th SCLK, the configuration word will be
latched into the configuration register and the selected calibration will be executed. . The time
required to perform a calibration is listed in Table 3. The DRDY pin will remain a logic 1
during calibration, and will go low when the
calibration step is completed.
The serial port should not be accessed while a
calibration is in progress. The EC bit of the configuration register remains a logic 1 until it is
overwritten by a new configuration word (EC =
0). Consequently, if EC is left active, any write
(the falling edge of the 24th SCLK) to any register inside the converter will cause a re-execution
of the calibration sequence. This occurs because
the internal microcontroller executes the contents
of the configuration register every time the 24th
SCLK falls after writing a 24-bit word to any
internal register. To be certain that calibrations
will not be re-executed each time a new word is
written or read via the serial port, the EC bit of
the configuration register must be written back to
a logic 0 after the final calibration step has been
completed.
The CC3--CCO bits of the configuration register
determine the type of calibration to be perDS74F1

formed. The calibration steps should be performed in the following sequence. If the user
determines that non-ratiometric offset calibration is important, the non-ratiometric offset
errors of the VREF and AIN input channels
should be calibrated first. Then the ratiometric
offset of the AIN channel should be calibrated.
And finally, the AIN channel gain should be calibrated.
Non-ratiometric Errors

To calibrate out the VREF and AIN
non-ratiometric errors, the input channels to the
VREF path into the converter and the AIN path
into the converter must be grounded (this may
occur at the pins of the IC, or at the bridge excitation as shown in Figure 3.). Then the EC, CC2
and CC3 bits of the configuration register must
be set to logic 1. The converter will then perform a non-ratiometric calibration and place the
BX1 f - - - - - /
BX2

CS5516
CS5520
VREF+ H---"
VREF- 1---1-----"
AIN+

AIN-

~-~==j------'

'Note: The bridge can be grounded w~h a
relay or with jumpers to perform
non-ratiometnc calibration.

Figure 3. Non-ratiometric System Calibration using
Internal Excitation

2-533

.,

_..--..--__.._-_
...
._.-.
proper 24 bit calibration words in the VREF and
AIN non-ratiometric registers. Note that the two
non-ratiometric offsets can be calibrated simultaneously or independently, but they must be
calibrated prior to the other calibration steps if
non-ratiometric offset calibration is to be used. If
the effects of the non-ratiometric errors are not
significant enough to affect the user application,
they can be left uncalibrated (after a reset, the
non-ratiometric offset registers will contain
OOOOOO(H».

CS5516, CS5520

to signal the completion of this calibration step,
the EC bit of the configuration register must be
set back to logic 0 to terminate the calibration
mode.

Limitations in Calibration Range

Gain

There are five calibration registers in the converter. There are two non-ratiometri~ offset
calibration registers, one for the AIN input and
one for the VREF input; one 4-bit offset trim
DAC; one ratiometric offset calibration register
for the AIN input; and one gain calibration register. After the non-ratiometric offsets are
calibrated, an LSB in either of the 24-bit non-ratiometric calibration registers represents 2- 23
proportion of an internally-scaled MDRV
(Modulator Differential Reference Voltage). At
the MDRV+ and MDRV- pins, the MDRV has a
nominal value of 3.75 volts. This voltage is internally scaled to a nominal 2.5 volts (never less
than 2.4 volts) for use with the non-ratiometric
calibration. The two non-ratiometric calibration
words are stored in 2's complement form with
one count equal to slightly less than 300 nV at
the input of the internal AID converter. For the
AIN channel this will be scaled down by the
gain of the instrumentation amplifier (X25) and
the PGA gain. For a PGA gain = 1, one count of
a non-ratiometric register will represent slightly
less than 12 nV. Non-ratiometric offset at the
VREF input cannot exceed ± 2.4 volts to be
within calibration range of the converter. Non-ratiometric offset to be calibrated by the AIN
channel cannot exceed ± 2.4 volts divided by the
channel gain. With a PGA gain = 1, the maximum non-ratiometric offset which can be
calibrated on the AIN channel cannot exceed
± 96 mv'

After the AIN ratio metric offset has been calibrated, the next step is to perform a gain
calibration. Gain calibration is performed with
"full scale" weight on the scale platform. The EC
and CCO bits of the configuration register are set
to logic 1. The gain calibration of the AIN channel is the final calibration step. After DRDY falls

When the ratiometric offset is calibrated, the 4bit DAC coarsely trims offset from the analog
signal. The ratiometric offset which remains is
finely trimmed after the signal has been converted; using the contents of the ratiometric
offset register for digital correction. The DAC

Ratiom~tric

Offset

Once the non-ratiometric errors have been calibrated, the ratiometric offset error of the AIN
channel should be calibrated next. To perform
this calibration step, a reference voltage must be
applied to the VREF+ and VREF- pins. Then,
place "zero" weight on the scale platform. This
will result in an offset voltage into the converter
which will represent the offset of the bridge, the
wiring, and the AIN input of the converter itself.
A configuration word with the EC and CC1 bits
set to logic 1 is then written into the configuration register. During the ratiometric offset
calibration of AIN the microcontroller first uses
a successive approximation algorithm to compute
the correct values for the DAC3-DACO bits of
the DAC register. This accommodates any large
offsets on the AIN input signal. . Once the four
DAC bits are computed, this amount of offset is
removed from the input signal. The microcontroller then computes the appropriate 24 bit
number to place in the AIN ratiometric offset
register to calibrate out the remaining offset not
removed by the DAC.

2-534

DS74F1

-___

.._--. ..--_._.
...-.
bits can be manipulated by the user to add or
subtract offset up to 200 percent of the nominal
input signal. The AIN ratiometric offset register
can be manipulated to add or subtract offset
equal to the maximum differential input signal
into the X25 amplifier. An LSB in the ratiometric offset register represents 2- 23 proportion of
the voltage input across the VREF+ and VREFpins at the internal input to the AIN channel AID
converter. This will be scaled down by the AIN
channel gain when calculated relative to the instrumentation amplifier input. For example, with
a VREF = 2.5 V, the PGA gain = 1, one count of
the ratiometric offset register would represent
a,bout 12 nV at the instrumentation amplifier input. The proportion remains ratiometric even if
the VREF voltage should change. The 24-bit register content is stored in 2's complement form.
Manipulation of the DAC or ratiometric offset
register allows the user to shift the transfer function to allow for load cell creep or load cell zero
drift.
The gain calibration is performed last. The contents of the gain register spans from 2- 23 to 2 as
shown in Table 4. After gain calibration has been
performed, the numeric value in the gain register
should not exceed the range of 0.8 to 1.2. The
gain calibration range is ± 20 % of the nominal
value of 1.0. The nominal value of 1.0 is for an
input span dictated by the VREF voltage, the
PGA gain, and the X25 instrumentation gain.
The converter may operate with gain slope factors from 0.5 to 2.0 (decimal), but when the
slope exceeds 1.2 the converter output code computation may lack adequate resolution and result
in missing codes in the transfer function. Internal
circuitry may saturate for large signals which
would calibrate to a gain factor less than 0.8.

DS74F1

CS5516, CS5520

In a typical weigh scale application, the
CS5516/CS5520 will be calibrated in combination with a load cell at the factory. Once
calibrated, the calibration words are off-loaded
from the converter and stored in E2PROM.
When powered-up in the field the calibration
words are up-loaded into the appropriate registers. This is viable because the AIN and VREF
input to the converter are "chopper-stabilized"
and maintain excellent stability when subjected
to changes in temperature.
Programmable Gain Amplifier

The programmable gain amplifier inside the
CS5516/20 offers gains of 1, 2, 4, and 8. This is

in addition to the fixed gain of x 25 in the input
instrumentation amplifier. The gain tracking of
the PGA is about one percent between ranges.
The user can remove this error by performing a
gain calibration at the factory with a full scale
signal on each range. The gain calibration word
for each gain range can be off-loaded into
E2PROM and uploaded into the gain register
whenever a new gain setting is selected for the
PGA. Gain stability over temperature for the
converter itself is approximately 1 pprnl°C when
the device is used ratiometrically.
Serial Interface Modes

The CS5516!20 support either 5, 4 or 3 pin serial interfacing. The SMODE pin sets the
operating mode of the serial interface. With
SMODE = 0, the device assumes the user is operating with either a 5 or 4 wire interface. The
five wire mode includes SOD, SID, SCLK,
DRDY, and CS. In the four wire mode, CS is
connected to DGND as a logic O. The user
would then interface to the SOD, SID, SCLK,
and DRDY pins.

2-535

.,
,
,

----------------------

CS5516, CS5520

AIN and VREF Non-Ratiometric Offset Registers
MSB
2° I
0

Register
Reset (R)

2-1

2-2

2-3

2-4

2-5

0

0

0

0

0

II

2-18

2-19

2-20

2-21

2-22

LSB
2-23

0

0

0

0

0

0

013

One LSB represents 2-23 proportion of the internal MORV (~2.5 Volts)

DAC Register
023
IDAC3
0

Register
Reset (R)

022
DAC2
0

021
DAC1
0

010
EC
0

09
09
0

011

AIS

Register
Reset (R)

0

BIT
OAC3

NAME
OAC Sign Bit

OAC2-0

OAC Bits

020
019
DACO I EXC
0
0

018
F1
0

017
FO
0

016
016
0

015
G1
0

014
GO
0

UIB
0

012
012
0

07
CC3
0

06
CC2
0

05
CC1
0

04
CCO
0

03
03
0

02
02
0

01
01
0

00
RF
0

08
08
0

VALUE
Rl
0
1
000
R
001
010
011
100
101
110
111
0
R

Bits
019 to DO

FUNCTION
Add Offset
Subtract Offset
25% Offset
50% Offset
75% Offset
100% Offset
125% Offset
150% Offset
175% Offset
These bits mirror the
Configuration Register

read onll

Note: 1. Reset State
2. A write to these bits does not change the register bit values.

AIN Ratiometric Offset Register
Register
Reset (R)

I

MSB
2° I

0

2-1

0

I

2-2

0

I

2-3

2-5

0

o

II

LSB
2-18 I 2-19 I 2-20 I 2-21 I 2-22 I 2-23
000000

One LSB represents 2-23 proportion of the voltage [«VREF+) • (VREF-»/GAIN) where GAIN = 25 X PGA Gain

GAIN Register
Register
Reset (R)

LSB

MSB
2°

2-1

2-3

1

0

o

The gain register span from 0 to (2_2-23 ). After Reset the MSB=1, all other bits are O.

Table 4. Calibration Registers

2-536

DS74F1

.-_
._.-.
_
..--__.._-_
...
Reading a register in the converter requires a
command word to be written to the SID pin.
For example, to read the conversion data register,
the following command sequence should be performed. First, the command word 88(H) would
be issued to the port. In the 5 wire interface
mode, this would involve activating CS low, followed by 8 SCLKs (note that SCLK must
always start low and transition from low to high
to latch the transmit data, and then back low
again) to input the 8-bit command word. CS
must be low for the serial port to recognize
SCLKs during a write or a read, but it is actually
the first rising SCLK during command time that
gives the user control over the port. After writing
the command word, the user must pause and
wait until the CS5520 presents the selected register data to the serial port. The DRDY signal will
fall when the data is available. When reading the
conversion data register, it may take up to
112,000 XIN clock cycles for DRDY to fall after
the 88(H) command word is recognized. See
Figure 4 for an illustration of command and data
word timing.
The conversion data register is actually the accumulator of the post-processor which computes
the output data. At the end of each filter convolution cycle, the internal microcontroller checks
to see if a read conversion data register command has been interpreted. If so, it transfers the
accumulator result to the serial port.
Whenever registers other than the conversion
data register are read, the DRDY pin will fall
within 256 XIN clock cycles (62.5 Jls with
XIN = 4.096 MHz) after the command word is
recognized. When DRDY falls, 24 SCLKs are
then issued to the port to read the 24-bit output
data word. DRDY will return high after all 24
bits have been clocked out. The SOD pin will be
in a Hi-Z state whenever CS is high, or after all
24 output data bits have been clocked out of the
port.

DS74F1

CS5516, CS5520

The CS5516/20 is designed such that it can output conversion data words continuously, without
issuing a new command word prior to each data
read. Under the following circumstances, continuous conversion data can be read from the
port after issuing only one 88(H) command
word. Once the command to read the conversion
data register is issued, DRDY must be allowed to
go low, after which 24 SCLKs are issued to read
the data. This will cause DRDY to return high.
The converter will continue to output conversion
words at the update rate as long as a different
command word is not started prior to DRDY
falling again. The user is not required to read
every output word to remain in the continuous
update mode. DRDY will toggle high, and then
low as each new output word becomes available.
If a command word is issued immediately after a
data word is read, the converter will end the read
conversion mode. Figure 5 illustrates the continuous data mode.
The user should perform all data reads and command writes within 51,000 XIN clock cycles
after DRDY falls to avoid ambiguity as to who
controls the serial port.
If SMODE = 1 (tied to VD+), the interface operates as a 3 wire interface using only SOD, SID,
and SCLK. In the 3 wire mode CS must be tied
to DGND. DRDY operates normally but is not
used. Instead, the DRDY signal modifies the behavior of the SOD signal, allowing it to signal to
the user when data is available. To read data
from the converter requires a command word to
be written to the SID pin. The SOD output is
normally high (never Hi-Z). When output data
is available, the SOD signal will go low. The
user would then issue 8 SCLKs to the SCLK pin
to clear this data ready signal. On the falling
edge of the 8th SCLK the SOD pin will present
the first bit of the 24-bit output word. 24 SCLKs
are then issued to read the data. Then SOD will
go high. SID should remain low whenever the
SID pin is not being written. When reading
2-537

~

~

--------- ... -----------~

CS5516, CS5520

\\

r

I~

L-----------------------------------------~I~----------~

Innnnn

SCLK

~UUUUf--

"~
"" ""I

SID
Command TIme
8 SCLKs

Data Time
24 SCLKs
SID Write

SCLK

SID

DRDY

SOD

---------------------------------1
SOD Read (4 or 5 Wire)

SCLK

SID

SOD

8 SCLKs Clear DRDY

SOD Read (3 Wire)

Data Time
24 SCLKs

Command
was 88(H)

Figure 4. Command and Data Word Timing
*See text for td time.

2-538

DS74F1

___-_

.. ...-.
-.-_
..--_._.

CS5516, CS5520

SOD, SCLK cannot be continuous but must
burst one clock cycle per bit.
The continuous read conversion data mode is
also functional in the 3-wire interface mode. Issue one 88(H) command word to the converter.
Then wait for SOD to go low. Issue 8 SCLKs to
clear the data ready function. The MSB data bit
will then appear on the SOD pin. Issue 24
SCLKs to read the conversion word. At the falling edge of the 24th SCLK SOD will return
high. SOD will go low at the next DRDY falling
time to indicate a new conversion word. Eight
SCLKs must again be issued to clear the data
ready function before clocking out the data conversion word. The SOD pin will continue to
toggle low each time a word is available even if
the conversion data is not read. To terminate the
continuous conversion mode, input an 8-bit command word immediately after reading a
conversion word.
The user should perform all data reads and command writes within 51,000 XIN clock cycles
after SOD falls to avoid ambiguity as to who
controls the serial port.
Serial Port Initialization
If for any reason the off-chip microcontroller

fails to know whether the serial port of the

CS5516/20 is in data mode or command mode,
the following initialization procedure can be issued to the port to force the CS5516/20 into the
command mode. Write 128 or more 1's to the
SID pin. Then issue a single 0 to the SID pin.
The port will then be initialized into the command mode and will be waiting for an 8-bit
command word.

Bridge Excitation Options
The CS5516/CS5520 NO converters are optimized for Wheatstone bridge applications. The
converters support either de or ac (switched dc)
bridge excitation.
DC Bridge Excitation

The CS5516/CS5520 can be configured for de
bridge excitation in either of two ways. The
EXC bit of the configuration register can be set
for either internal or for external excitation. If
set to internally-controlled mode (EXC = 0), the
Fl and FO bits must be set to logic Os. In this
condition, the bridge can be excited from a dc
supply with a resistor divider to develop the appropriate reference voltage for the VREF+ and
VREF- pins. Note that the bridge excitation
should not be applied prior to the
CS55l6/CS5520 being powered-up. With EXC,
Fl, and FO set to logic 0, the BX1 output will be

Port Access Period
Valid 51,000
XIN Clock C cles

Cs\
~
~
SCLK~
~
~

~

----fIlf-----+-----~

~

L-.

8 SCLKs

24 SCLKs

SID

8 Data Bitsl

~

DRDY

-------j~

~

~

SOD

-------j~1l!

81,920 XIN
Clock C cles

I~

I

~

~!
if1!

r1l!

~

1~1-ruL
~
~
~
~____
24 SCLKs

I
I
I r~

I

~

~

10

1l!

I

1l!

~

~

24 Data Bits

!!

~

~

~

~

~
24 Data Bits

Figure S. Continuous Read Conversion Data Mode (4 or 5 Wire)
DS74F1

2-539

~.""
~

_
..---.-.
__.._-_
...-.
.-_

CS5516, CS5520

logic 0 (0 volts) and the BX2 output will be a
logic 1 (+5 volts).
A second method for configuring the converter
for dc excitation is by setting EXC = 1, and pulling up BX1 (pin 12) to VD+ (pin 20) through a
resistor. This sets the converter for use with external excitation which uses the BX1 pin as
an input to set the excitation frequency. With
BX1 = VD+, the external excitation frequency is
zero, or dc.

The converter is capable of demodulating this
clocked excitation. But only if the signals into
the AIN+ and VREF+ pins of the converter are
in phase with the demodulation clock inside the
converter (see Figure 7). The non-overlapping
clock signals from BX1 and BX2 are CMOS
level outputs (0 to VD+ volts) and are capable of
driving one TTL load. A buffer amplifier MUST
be used to drive the bridge.
Whenever the internal mode is used for dynamic
bridge excitation the signals are non-overlapping.

AC Bridge Excitation
AC bridge excitation involves using a clock signal to generate a square wave which repetitively
reverses the excitation polarity on the bridge. To
excite the bridge dynamically requires some type
of bridge driver external to the CS5516/CS5520
converter. This driver is driven by a square wave
clock. The source of this clock depends upon
whether the converter is set for internal excitation or for external excitation. Figure 6 illustrates
a sample bridge drive circuit when operating in
the internal AC excitation mode.
Using internal excitation involves setting the
EXC bit of the configuration register to 0, and
+SV

BX2

-SVJlJl +5V
7 EXC+
-SV

5

EXC-

Il I
U U

~

+SV
-SV

'------,---' MICREL
MIC4428or
MIC442S
-SV

Figure 6. Sample AC Bridge Driver

setting the Fl and FO bits to select the excitation
frequency for the bridge. In this mode the excitation frequency is a sub-multiple of the XIN
clock frequency. The excitation clock is output
from the BX 1 and BX2 pins of the converter in
the form of a two-phase non-overlapping clock.
2-540

BXl (Out)

If--------il
td-.l

BX2 (Out)

Demod Clock
(Internal)

~

-.--J
~

->I

L

I.-td

1'--__-----'1

L-_----li

Note: The signals from the bridge into AIN+ and
VREF+ of the converter must be in phase
with the demodulation clock.
td is 1 cycle of XIN clock.

Figure 7. Internal Excitation Clock Phasing

The non-overlapping time is one XIN clock cycle.
The converter can also be configured to provide
dynamic bridge excitation when operating in the
external-controlled bridge excitation mode. With
the EXC bit of the configuration register set to
logic 1, the BX1 pin becomes an input which
determines the bridge excitation frequency and
phase. BXl should be near 50% duty cycle. The
user can select the excitation frequency with the
following restrictions. The excitation frequency
must be synchronous with the XIN frequency of
the converter and must be chosen using the following equation:
Fexc = (N X XIN)/81 ,920
where N is an integer and lies in the range including 1 to 160. Fexc is the desired bridge
excitation frequency. Other asynchronous frequencies are possible but may introduce a jitter
component in the BX output signals. It is deDS74F1

----------------------

CS5516, CS5520

sirable not to choose an excitation frequency
where interference components are present, such
as 50 Hz or 60 Hz or their harmonics. The XIN
frequency can be divided down using a counter
IC external to the AID converter. Fexc would be
input to the BXl pin of the converter to synchronize the internal operations of the amplifiers and
synchronous detection circuitry and to generate a
clock output from the BX2 pin. The BX2 output
is then used to drive the bridge amplifier with a
signal of proper phase for detection by the converter. Figure 8 indicates the necessary phase of
the signals to ensure proper demodulation.

excitation, one should limit any input filtering
resistors on AIN to below I kil. Values greater
than this will degrade noise performance of the
converter. In ac excitation applications, any filtering must be broadband enough that the
switched dc excitation signal can settle within 10
Jlsecs. Failure to meet this settling requirement
will affect measurement accuracy. Figure 9 illustrates acceptable filter components for ac
excitation. If only differential filtering is required, a single capacitor can be placed between
AIN+ and AIN- (and VREF+ and VREF-) in
place of two capacitors to ground.

Whenever the dynamic excitation clock output
from either the BXl and BX2 pins (during internal excitation) or from the BX2 pin (during

Voltage Reference Considerations

BX1 (In)

~

7.Sk
EXC+ ----1VVIr----..-~>------I VREF+

I

Sk

-.\ j+-tdd
BX2 (Out)

DemodClock
(Intemal)

~

I

~

I

Note: The signals from the bridge Into AIN+ and
VREF+ of the converter must be in phase
with the demodulation clock.
tdd :;;64IXIN

Figure 8. External Excitation Clock Phasing

external excitation) changes states, the converter
waits 64 XIN cycles before sampling the AIN
and VREF signal inputs. The delay allows some
time for the signal to settle from the modulation
event.
Input Filtering
Some load cells are located a distance from the
input to the converter. Under these conditions,
separate twisted pair cabling is recommended for
the excitation drive to the bridge, the excitation
sense leads (if used), and for the AIN±lAINsignal leads. If the AIN+/AIN- leads to the converter and the VREF+IVREF- leads to the
converter are filtered, care should be exercised in
the choice of components. With either dc or ac
DS74F1

7.Sk
EXC· J\M---tO---_--'-----! VREF- CS5516

300
AIN+ --'WI,---~>------I AIN+

or
CS5520

h47flF
AIN-

0.0047 flF

--'lMr--~----'----I

AIN-

Figure 9. AIN and VREF Input Filter Components

The CS5516120 include an on-chip voltage reference which is output on the MDRV- and
referenced from the MDRV+ pin. The converter
is designed to be operated as a ratiometric measurement device. The 2-channel delta-sigma
converter uses the internal MDVR (Modulator
Differential Voltage Reference) as its reference.
Since the MDVR is used for converting both the
AIN and VREF signals at the same time, the absolute value of the MDVR and its tempco are
not important when the CS55 16/20 is used in the
ratiometric measurement mode. The voltage reference output, MDVR-, should be decoupled
using a 1 JlF capacitor which is connected to the
MDRV+ supply line. Voltage reference decoupIing is shown on the system connection
diagrams.

2-541

till
.
..

_
..--_.-.
__.._-....-.
.-_
If absolute measurements are to be made by the
CS5516/20, then a precision reference should be

input into the VREF+ and VREF- terminals.
Clock Generator

The CS5516/20 includes a gate which can be
connected as a crystal oscillator to provide the
master clock to run the chip. Alternatively, an
external (CMOS compatible) clock can be input
into the XIN pin. Figure 10 illustrates a simple
model for the on-chip gate oscillator. The onchip oscillator is·· designed to typically operate
with crystal frequencies between 4.0 and 5.0
MHz without additional loading capacitors. If
other crystal frequencies, or if ceramic resonators
are used, additional loading capacitance may be
necessary.

CS5516, CS5520

(XIN = 4.9152 MHz) but other XIN frequencies
can be used. The filter transfer function will
scale proportionally. Figure 11 shows the transfer
function of the filter when operated at three different frequencies. With a 3.579 MHz XIN, the
filter offers greater than 90 dB rejection of both
50 and 60 Hz.
The output word rate of the converter scales with
o~~--------------------------.

I

·40

~
~

.. ,.

-- --- --

- - - - - - - - - - " (1) XIN = 3.579 MHz
. , . . , . . ,. . , . (2) XIN = 4.096 MHz . .
, (3) XIN 4.915 MHz
,

I

I

I

:

:

:

:

. - - -

·20

,

I

I

,

=

·60

-

·80
~
g'.100

,
I

- -

,

,

,

,

--- --

-

,

,

,

,

,

,

,

,

----- ---

- - -

::;:

·120

The XOUT pin can be used to drive one CMOS
gate for system clock requirements. Be sure to

·140
·160 +--r---r--r---r--r---r--r--+--+--'1
o 21.8 43.7
87.3
131.0
174.7
218.5
o 25 50
100
150
200
250
o 30 60
120
180
240
300
Input Frequency (Hz)

Figure 11. Filter Maguitude Response
180
150

XIN = 4.096 MHz

120

External XT AL

Figure 10. On-Chip Gate Oscillator Model

include the gate's input capacitance and stray capacitance as part of the loading capacitance for
the resonating element.

..,

90

!!

30

"go

60

:!:!.

0

fd"

·30

.<=

a. ·60
·90

Digital Filter

·120

The CS5516/20 is optimized to operate with clock
frequencies of 4.096 MHz or 4.9152 MHz. These
result in the filter having a 3dB bandwidth of 12
Hz or 15 Hz, with output word rates of 50 or
60Hz. The rejection at 50Hz ± 3Hz is 70 dB minimum with a 4.096 MHz clock. Similar rejection is
obtained at 60 Hz with a 4.9152 MHz clock.

·180

The digital filter has a deep notch in its transfer
function at 50 Hz (XIN = 4.096 MHz) or 60 Hz
2-542

·150
0

5

10

15

20

25

30

35

40

45

50

Input Frequency (Hz)

Figure 12. Filter Phase Response.

the XIN clock rate and is set by the ratio of
XIN/81,920; or 50 Hz for XIN = 4.096 MHz. If
very narrow signal bandwidths, such as 3 Hz, are
desired, averaging of the output words is recommended.
DS74F1

.._-.-_
._.-.
_
..--__
...

CS5516, CS5520

The digital filter computes a new output data
word every 81,920 XIN clock cycles. If the input experiences a large change in amplitude, the
PGA gain is changed, or the DAC calibration
registers are changed, it may take up to six filter
cycles (81,920 X 6 clock cycles) for the filter to
compute an output word which is fully settled to
the input signal.
Output Coding

The CS5516/20 converters output data in binary
format when operating in unipolar mode and in
two's complement when operating in bipolar
mode. Table 5 illustrates the output coding for
the converters. Note that when reading conversion data from the converter the data word is
output MSB or sign bit first. Falling edges on
SCLK advance the data word to the next lower
bit.

Under normal operating conditions, the flag bits
will be zeroes. The flag bits will be set to all
ones whenever an overrange condition exists.
Under large overrange conditions where the input signal exceeds the nominal full scale input
by approximately two times (for example:
50 mV input when the nominal full scale input is
set-up for 25 mV), the converter may be unable
to compute a proper output code. In this condition flag bits will be set to all 1s but the
conversion data may be a value other than full
scale plus or minus.
After the converter is first powered-up, a RST is
issued, or the device comes out of the SLEEP
mode, the first conversion data read may
erroneously have its error flag bits set to "1".
Synchronizing Multiple Converters

The output conversion words from both the
CS5516 and the CS5520 are 24 bits long. The
CS5516 has 16 data bits followed by 8 flag bits
(all identical). The CS5520 has 20 data bits followed by 4 flag bits (all identical). To read the
conversion data, including the error flag information will require at least 17 SCLKs for the
CS5516 and at least 21 SCLKs for the CS5520.

Multiple converters can be made to output their
conversion words at the same time if they are
operated from the same clock signal at XIN. To
synchronize multiple converters requires that
they all have their RF bit of the configuration
register written to a logic I and then back to O.
The filters will be allowed to start convolutions
after the falling edge of the 24th SCLK used to
write the RF bit to the configuration register.

Unipolar Input Offset
Bipolar Input
Two's
Binary
Voltage
Complement
Voltage
>(VFS-1.5 LSB) FFFF >(VFS-1.5 LSB)
7FFF
FFFF
7FFF
--- ..----..
VFS-1.5 LSB
VFS-1.5 LSB
FFFF
7FFE
0000
8000
---....
-----0.5 LSB
VFS/2-0.5 LSB
7FFF
FFFF
0001
8001
-- ... _..
......-..
+0.5 LSB
-VFS+0.5 LSB
0000
8000
8000
«+0.5 LSB)
0000 «-VFS+0.5 LSB)

Unipolar Input Offset
Bipolar Input
TWo's
Voltage
Complement
Voltage
BinaiY
>(VFS-1.5 LSB) FFFFF >(VFS-1.5 LSB)
7FFFF
FFFFF
7FFFF
VFS-1.5 LSB
----VFS-1.5 LSB
----FFFFE
7FFFE
80000
00000
--------VFS/2-0.5 LSB
-0.5 LSB
7FFFF
FFFFF
00001
80001
---------VFS+0.5 LSB
+0.5 LSB
00000
80000
«+0.5 LSB)
00000 <(-VFS+0.5 LSB)
80000

CS5516 Output Coding

CS5520 Output Coding

Note: VFS in the table equals the full scale voltage between +VREF/(G x 25) and ground for unipolar mode; and
between ±VREF/(G x 25) for bipolar mode. The signal input to the AID section of the converter has been
amplified by the instrumentation amplifier (x25) and the PGA gain, G (1, 2, 4, or 8). See text about error

Table 5. Output Coding for tbe CS5516/20 Converters.
DS74F1

2-543

~.
~

.-_
..--_-.._-_...._.-.
The filter will start a new convolution on the
next rising edge of the XIN clock after the 24th
SCLK falls.

CS5516, CS5520

140r-----------------------~

120 ....................................................

............................................................ .

100 .............................................

Sleep Mode
The CS5516120 configuration register has an A1S
bit which allows the users to put the device in a
sleep condition to lower quiescent power. Upon
reset the A1S bit device is set to a logic 0 which
places the device in the 'awake' condition. Writing a 1 to the A1S bit will shutdown most of the
chip, including the oscillator. It is desirable to
use the following sequence when coming out of
sleep. Write a logic 0 to the A1S bit of the configuration register. In the same configuration
word write a logic 1 to the RF bit of the configuration register. Then wait until it is certain that
the oscillator has started. After the oscillator has
started or a clock present on the XIN pin, set the
RF bit back to O. The user should then wait at
least 6 output word update periods before expecting a valid output data word.

80 ................................... .

60
40

20

o

··.~.I·.
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2

.1."::
3 4 5 6 7 8

Figure 13. CS5520 Noise Histogram.

Noise Performance
Typical noise performance for the converter is
listed in the specification tables for each PGA
gain. Figure 13 illustrates a noise histogram for
1000 output conversions from the CS5520. The
data for the histogram was collected using the
CDB5520 evaluation board; with VREF at 2.5
volts, PGA = 4, bipolar mode. The data shows
the standard deviation of the data set is 3.2
LSBs. One LSB is equivalent to [VREF X 2(bipolar)]/ [Inst amp gain X PGA gain X number of
codes] or (2.5 X 2)/ (25 X 4 X 2E20) = 47.7
nV. One standard deviation is equivalent to rms
if the data is Normal or Gaussian. The rms noise
presented by the plot is 153 nV, which is in good
agreement with the typical noise specification of
150 nV for a PGA gain of 4.

Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your

Applications

See the Application Notes section of the databook.

2·544

DS74F1

.-_
_
..--_._.
__.._-_
...-.

CS5516, CS5520

PIN DESCRIPTIONS

Modulator Ditt. Voltage Ref +
Modulator Ditt. Voltage Ref Positive Analog Power
Negative Analog Power
Analog Ground One
Analog In +
Analog In Analog Ground Two
Voltage Ref In +
Voltage Ref In Bridge Excite 2
Bridge Excite 1

MDRV+
MDRVVA+
VAAGND1
AIN+
AINAGND2
VREF+
VREFBX2
BX1

SMODE
XOUT
XIN
VDVD+
DGND
SOD
SID
SCLK
DRDY
CS
RST

Serial Interface Mode
Crystal Out
Crystal In
Negative Digital Power
Positive Digital Power
Digital Ground
Serial Output Data
Serial Input Data
Serial Clock Input
Data Ready
Chip Select
Reset

Power Supply Connections

VD+ - Positive Digital Power, PIN 20.
Positive digital supply voltage. Nominally +5 volts.
VD- - Negative Digital Power, PIN 21.
Negative digital supply voltage. Nominally -5 volts.
DGND - Digital Ground, PIN 19.
Digital ground.
VA+ - Positive Analog Power, PIN 3.
Positive analog supply voltage. Nominally +5 volts.
VA- - Negative Analog Power, PIN 4.
Negative analog supply voltage. Nominally -5 volts.
AGND1, AGND2 - Analog Ground, PINS 5, 8.
Analog ground.
Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 22, 23
An internal gate is connected to these pins enabling the use of either a crystal or a ceramic
resonator to provide the master clock for the device. Alternatively, an external (CMOS
compatible) clock can be input to the XIN pin as the master clock for the device.

DS74F1

2-545

....._-..---...-..
....

-_

CS5516, CS5520

Digital Inputs
RST - Reset, PIN 13.
Reset pin initializes all calibration registers to a known condition and places the serial port into
the command mode.
CS - Chip Select, PIN 14.
An input which can be enabled by an external device to gain control over the serial port. When
this pin is high, SOD is in a high impedance state if SMODE =O.
SCLK - Serial Data Clock, PIN 16.
A clock signal at this pin determines the output rate of the data from the SOD pin and the input
data rate on the SID pin.
SID - Serial Input Data, PIN 17.
This pin is used for inputting command and configuration words or inputting calibration words.
Data is input at a rate determined by SCLK. SID is in a don't care state when no data is being
clocked in.
SMODE - Serial Interface Mode, PIN 24.
Selects the operating mode of the serial port. When low the serial port operates in the 5 or 4
wire interface mode. When high the chip will enter the 3 wire interface mode.

Analog Inputs
AIN+ and AIN- - Analog. Inputs, PINS 6, 7.
The analog input signals from the transducer. These are true differential inputs.
VREF+ and VREF - - Voltage Reference Inputs, PINS 9,10.
These are the differential analog reference voltage inputs.
MDRV+ - Modulator Differential Voltage Reference, PIN 1.
Positive terminal of the internal differential voltage reference which can be tied to the positive
supply (VA+) or ground (AGND).
MDRV- - Modulator Differential Voltage Reference, PIN 2.
This is the -3.75V modulator differential voltage reference output and can be used to generate
an analog reference. Note this is with reference to the MDRV+ pin.

2-546

DS74F1

.._-_
.-_
_
..--_._.
_...-.

CS5516, CS5520

Digital Outputs

BXl and BX2 - AC Bridge Excitation Signals, PINS 12, 11.
These can be buffered to drive the transducer or used as synchronizing signals for a transducer
drive circuit. BXl and BX2 are 0 to +5V signals.
DRDY - Data Ready, PIN 15.
DRDY goes low every 81,920 cycles of XIN (when in read conversion data mode) to indicate
that new data has been placed in the output port. DRDY goes high when all the serial port data
is clocked out, when the serial port is being updated with new data, when a calibration is in
progress, or when the device is in SLEEP.
SOD - Serial Output Data, PIN 18.
Data from the serial port will be output from this pin at a rate determined by SCLK . The data
will either be conversion data, or, calibration values, dependent upon the command word that
has been previously input on the SID pin. The SOD pin furnishes a high impedance output state
when not transmitting data (SMODE = 0).

ORDERING GUIDE
Model Number

Linearity Error (Max)

eS5516-AP
eS5516-AS
eS5520-BP
eS5520-BS

0.003%
0.003%
0.0015%
0.0015%

DS74F1

Temperature Range

-40 o e
-40 o e
-40 o e
-40 o e

to
to
to
to

+85°e
+85°e
+85°e
+85°e

Package
24-pin 0.3" Plastic DIP
24-pin 0.3" sOle
24-pin 0.3" Plastic DIP
24-pin 0.3" sOle

2-547

----------------------

CS5516, CS5520

SPECIFICATION DEFINITIONS
Linearity Error
The deviation of a code from a straight line which extends between two fixed points on the NO
converter transfer function. In unipolar mode, the straight line extends from one point located
1/2 LSB below the fIrst code transition, one count above all zeros; to the second point located
V2 LSB beyond the code transition to all ones. In bipolar mode, the straight line extends from
one point located 1/2 LSB beyond the code transition to all ones, passing through a point
liz LSB below code 8000(R) (16-bit); 80000(R) (20-bit); extending to beyond negative full
scale. Units are in percent of full-scale.
Differential Nonlinearity
The deviation of a code's width from the ideal width. Units in LSBs.
Full Scale Error
The deviation of the last code transition form the ideal [{(VREF+)-(VREF-)}-3jz LSB]. Units
are in LSBs.
Unipolar Offset
The deviation of the first code transition from the ideal (V2 LSB above AGND) when in
unipolar mode (BP/uP low). Units are in LSBs.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100... 000) from the ideal (V2 LSB below
AGND) when in bipolar mode (BP/uP high). Units are in LSBs.

2-548

DS74F1

..
.. ...

~~

~~~.

CDB5516 CDB5520

..,
.,
Semiconductor Corporation
•

1I!IIIIItr . . . . . ..
."."

CS5516 & CS5520 ADC Evaluation Board
General Description

Features

The CDB5516 and CDB5520 provide quick and easy
evaluation of the CS5516 and CS5520 bridge
transducer AID converters. Direct connection of the
bridge to the evaluation board is provided.

• On-board microcontroller
• RS232 Serial Communications
with host PC

The board also contains a microcontroller, with firmware which allows the board to be controlled via simple
serial commands, using the RS232 communications
port of a PC.

• Supports either AC or DC bridge drive
• On-board bridge driver
• Supports ratiometric or absolute
measurements

ORDERING INFORMATION: CDB5516 or CDB5520

• Evaluation software included

-5V

OV

OV

+5V

+5V

! !

Load
Cell
AIN+

RS232
Driver/
Receiver

CS5516
CS5520

AINVREF+

SCLK
SID
SOD

Microcontroller

RS232
Connector

VREFBridge
Excitation
BX1
BX2

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS74DB3
2-549

_.--...............
__.._-_
...-..

CDB5516/CDB5520

Introduction

Evaluation Board Overview

The CDB5516/20 evaluation board provides a
means of testing the CS5516 and CS5520 bridge
transducer NO converters. The board is designed to be interfaced to a PC-compatible
computer via an RS-232 port. Software is supplied with the board which provides control of
all registers in the CS5516 or the CS5520.

Figure 1 illustrates the schematic of the bridge
driver and NO converter portion of the circuit
board. The converter operates from a 4 MHz
crystal. This results in the converter outputting
conversion words at a 50 Hz rate. The board
comes configured to be interfaced to a bridge
transducer via the 6-pin transducer terminal
block. The sense lines on the transducer terminal block provide the reference voltage for the
converter.

The board is configured to be operated from +5
and -5 volt power supplies. A bridge transducer
or a bridge transducer simulator is required if the
board is to be evaluated in the ratiometric operating mode.

+syA
o

~

o

,J,. 5
Pl

3

10k
R14
10k
R15

C21
+

la.lu1'

R12

I

I--

BX2

BXl
CS5516120
XIN

301

SIG-

SENSE-

11

110 uF

-JA

SENSE+

301

6

..L C18

E~

T

4 .7nF
C19

AIN+

EXC-

7.Sk
R7

f-

5.0k
R6

7.Sk
REF+
REF-

~

I]
L.J

+5VA

R4
301

E6

0-

2Af<>

0-

C~700F

AINVREF+

10 VREF-

=i= 4.7nF C1S

301

14

.~

C14 ~ LT1019O.l"F
2.5V

~

-SVA

so
R8

=f~.l"F
C29

f

~Cll

lOOk
R16

=

~4.000

OSCLK
SMODE
SOD
To

SID

Figure 2

SCLK
DRDY

cs
RST

VD-

VA-

R3
d::

22

MHZ

~

R5

2

!3T
XOUT 23
24
SMODE
18
SOD
17
SID
16
SCLK
15
DRDY
- 14
CS
13
RST
19
DGNDjP=

AGND2

,....Mf

10k
R17

CB

12

AGNDl

7

9
:::h47OpF

d::O.l1'F

"I

5

Rll
EXC+

)1

3
111'F 2
20
VA+ MDRV+ MDRV- VD+

R13

~

SIG+

0.1~C7 3t--1T1~H~'

~o~.lOOk ~

~~C20
4

EXC
-'"",

+5VA

TP061 0

EXC

0

EXC GN 0
@:£IfOi 0

Rl
10

Ql

~F5=21

fOi

@:£I~

MICREL
MIC4428

For absolute measurements, the user can connect
either an external reference voltage (up to 3.8
volts) to the reference terminal block or connect
the on-board 2.5 volt LT1019 reference as the
voltage reference for the converter.

R2

211

r;l1'F
Cl0

I

10

~O.l"F
AGND

DGND

-

-

: IJl

II-I~I>-~ Q

~

~o
en

C

CI)

C

~

W

8:::!

Figure 1. Bridge Driver and AID Converter

2-550

DS74DB3

.-_
_
..--_._.
__.._-...-.

CDB5516/CDB5520

. bridge driver, composed of a Siliconix TP0610
transistor and a Micrel MIC4428 dual CMOS
driver, is provided which allows the BX2 output
from the CS5516 or CS5520 to provide either dc
or ac excitation to the bridge.
The digital interface pins of the AID converter
connect to the microcontroller, or alternatively,
these connections can be cut, or the on-board
microcontroller can be removed, and the user's
own rnicrocontroller can be interfaced to 11
header connector.
Figure 2 illustrates the Motorola 68HC705C8
microcontroller which reads or writes data into
the AID converter and coinmunicates with the

PC-compatible computer via the RS-232 interface. The microcontroller derives its 4 MHz
clock from the AID converter clock. The microcontroller is configured to communicate over the
RS-232 link at 4800 baud, no parity, 8-bit data,
and 1 stop bit. A Motorola MC145407 RS-232
interface chip is used to send and recieve data to
the PC-compatible computer via the 25-pin SubD connector.
Table 1 lists the commands sent to the microcontroller to write to or to read from the registers in
the AID converter. If software other than that
provided with the evaluation board is used, the
format of the data transmitted over the RS232
line is as follow: Write commands are com+SVD

+SVD----------.-~----~--------__.

1Ol1F
C2S
10k

10k
R2

40
VDD
3 Vpp
2 IRQ

RESET
U2
29
68HC70SC8 PDO

1Ol1F
C28 +
T111Fl RXD
= C24 =

19
Vee
3
C2-

C1-

C2+

C1+

18

C27

20 + 1Ol1F

R28
10k
RI

16

S

TXD

1S

6

RXD

14

7

RTS

13

8

CTS

9

DTR

10

DSR

22
2

TXD

38 OSC2
OSCLK 39 OSC1
SMODE 10 PA1
SOD 31 PD2
From
SID 32 PD3
Figure 1
33
SCLK
PD4
36
PD7
DRDY
11 PAO
CS
9
RST
PA2
PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

10k
--"'- RESET

PD1

30

3

+SVD

D2
PA3
PA4
PAS
PA6
PA7

Vss
20

PCO
PC1
PC2
PC3
PC4
PCS
PC6
PC7

DCD
U4
MC145407
GND

4
S
20
6
8
7

Sub-D
2SPin

Figure 2. Microcontroller and RS·232 Interface
DS74DB3

2·551

.....
~.

_.-_..__.._-_
....-...
~--.-

CDB5516/CDB5520

Register

Read

Conversion Data Register

50(H)

Configuration Register

51(H)

DAC Register

53(H)

D3(H)

Gain Register

52(H)

D2(H)

Write

D1(H)

AIN Ratiometric Offset Register

54(H)

D4(H)

AIN Nonratiometric Offset Register

55(H)

D5(H)

VREF Nonratiometric Offset Register

56(H)

D6(H)

Table 1. Microcontroller commands via RS-232

posed of one byte for command which is transmitted with its LSB first. The command is
followed by three data bytes which make up the
24-bit word to be written to the selected register
of the NO converter. The three bytes are transmitted lowest order byte first (bits 7 - 0) with the
LSB of the byte transmitted first.
Figure 3 illustrates the power supply connections
to the evaluation board. Voltages of +5 and -5
analog and +5 digital are required.

Using the Evaluation Board
Prior to using the board to evaluate the CS5516
or CS5520 NO converter, a good understanding
of the full potential of the converter is necessary.
It is recommended that the CS5516/CS5520 device data sheet be thoroughly read prior to
attempting to use the evaluation board.
The CS5516 or CS5520 bridge transducer NO
converter actually contains two NO converters.

I

+SV
+1
Z1

C3

-SV

The span of the AIN input signal is determined
by a combination of the instrumentation amplifier gain (X25), the programmable gain amplifier
(PGA) gain, the magnitude of the voltage between the VREF+ and VREF- input pins, and the
calibration words for gain and' offset. For exam+S

+SVD

+SVA

C4

AGNDo-~--~----~---

Z2

One of the converters is used to convert the
VREF voltage input, and .the other is used to
convert the AIN signal input. Both converters
utilize an on-chip voltage reference to perform
conversions of their respective inputs. Since
both converters use the same reference they track
one another. The digital processing logic of the
NO converter depends on the presence of both
signals to properly compute a digital output
word. If the evaluation board is configured for
bridge measurement, and no bridge (load cell or
simulator) is connected to the bridge transducer
terminal block, the converter will output a code
of zero because no reference voltage is present
between the VREF+ and VREF- pins.

Z3

DGND

o-*---~----<

____~

C2
o-~--~----~--_

Figure 3. Power Supplies

2-552

DS74DB3

----------------------

CDB5516/CDB5520

pIe, the board comes with a set of precision resistors which divide the excitation supply
(nominally 10 volts total) down to 2.5 volts between the VREF+ and VREF- input pins. This
sets the nominal full scale voltage into the AID
converter. The input span of the instrumentation
amplifier can be calculated to by knowing the
PGA gain setting, and that the gain of the instrumentation amplifier is X25. If the PGA is set
for a gain of 8, then the input span to the instrumentation amplifier will be 2.5 volts (VREF+ VREF-) divided by 8 X 25, or 2.5/(200) = 12.5
millivolt nominal in unipolar mode. The device
can be then calibrated with an input voltage
which is as low as 20% less than nominal or up
to 20% greater than nominal. Therefore, with
this VREF+ - VREF- voltage (2.5 volts) and a
PGA gain of 8 the input span can be calibrated
to handle a span from a low of 10 mV to a high
of 15 mY. To modify the input span the user can
either change the PGA gain or modify the resistor divider on the bridge sense voltage to yield
an appropriate value in the range of 2.0 to 3.8
volts. This makes the AID converter quite flex-

+

Figure 4. 4-Wire Bridge Connections

DS74DB3

ible in handling load cells with different output
levels. Whenever configured as a bridge
transducer device, the CS5516 or the CS5520
AID converter operates in ratiometric measurement mode. Figures 4 and 5 illustrate how to
connect 4-wire and 6-wire bridge transducers to
the board.
Alternatively, the CS5516 or CS5520 can be
configured for absolute measurement if a precision reference voltage is supplied between the
VREF+ and VREF- pins of the AID converter.
The board can be modified to accept a reference
into the voltage reference terminal block; or the
on-board LT1Ol9-2.5 volt reference can be used
as the reference voltage for the AID converter.
To use either of these inputs will require that
jumper wires be soldered in either lA-lB to select the external voltage reference input, or
2A-2B to select the on-board LTl019-2.5. Figure 6 illustrates the connection of an external
voltage reference to the evaluation board for absolute voltage measurement applications. To
achieve an accurate reference voltage resistor R6

SIG+

SIG+

SIG -

SIG -

SENSE +

SENSE +

SENSE -

+

SENSE -

EXC+

EXC+

EXC -

EXC -

Figure 5. 6-Wire Bridge Connections

2-553

.'!';:

----------- -----------

CDB5516/CDB5520

must be removed from between the +VREF and
-VREF pins. It may be desirable to also remove
R5, R7, C16, and C17 in some applications.

MIC4428 driver should be returned to the EXC
position.
After the non-ratio metric calibration steps are
performed, the AIN ratiometric offset is then
calibrated. With "zero weight" on the load cell,
the converter is instructed via the configuration
register to perform the AIN ratiometric offset
calibration step. Finally, with "full scale weight"
on the load cell, the converter is instructed to
perform the gain calibration step.

Calibrating the AID Converter
As explained in the CS5516/CS5520 data sheet,
the order in which the calibration steps are performed are important. If one chooses to use the
non-ratiometric calibration capabilities of the
converter, the non-ratiometric errors of the VREF
and AIN channels should be calibrated first. The
non-ratiometric calibration steps can be performed at the same time. Before the nonratiometric offset calibration is initiated, the
bridge should be grounded. This can be achieved
on the evaluation board by moving the two
jumpers at the output of the MIC4428 driver to
the GND position (see Figure 1). The converter
is then instructed via the configuration register
bits to perform the non-ratiometric calibration
steps. Once the non-ratiometric calibrations are
completed, jumpers at the output of the

The converter is then ready to perform conversions.

Software
The evaluation board comes with software and a
RS-232 cable to interface the board to a RS-232
port of a PC-compatible computer. The software
diskette contains a README. TXT file which
explains its operation.

CS5516
CS5520

Remove R6 from between
+VREF and -VREF

Precision
Voltage
Reference
2.0 to 3.8
Volts

+

REF+

301

I

f----~--I

14.7 nF

-

REF-

3~A1

vv

+VREF
VREF

,-----j---([--(T-t-------i -

1B

00
o 0

CDB5516 or CDB5520

Figure 6. Using Off-board Voltage Reference

2-554

DS74DB3

.-_
...-..
_
..--_
__.._-_

CDB5516/CDB5520

Figure 7 illustrates the software supplied with
the CDB5516/CDB5520 evaluation board. The
software allows the user to manipulate the registers of the converter and perform calibrations
and conversions. It decodes the status of the configuration register and indicates the gain register
scale factor. The software enables the user to
collect data to a file, average samples and compute the average and standard deviation of the
samples which have been collected.

-

Figure 7. Screen for the CDB5516/CDB5520 Evaluation Board Software

DS74DB3

2-555

i

....

.....•••,:,
=••

[OJ

-5V

+5V

0,0·0
c2~d€) AG~
I

i

II I II·
zz

I

~
~

00

i

.....
="

RESET

d

pc~

:=r~re
m5

REf+n

?C

[OJ

AGND

~O~ ~
R2°1

] iT
~

rL1h

I---

0

t--

GND
0""

~

m
n
Wd;l

:io=.
l2:QIo

UJ

CRYSTAL
.~'1U·!I·

~~g

IJI

Semiconductor Corporation

SMART Analog

CDB5520
Evaluation Board

o
-PJ-

g

C
III
en
en
.....
~

o

C
en
en

III
I\\)

o

c

~

c

~

.._-_
.-_
_
..---._.
_...-.

CDB5516/CDB5520

•

Figure 9. CDB5520 Top Ground Plane

DS74DB3

2-557

.-_
..--_._.
__.._-_
...-.

CDB5516/CDB5520

Figure 10. CDBSS20 Solder Side Trace Layer

2-558

DS74DB3

.. .....
............
..
~~

~~~

~.

CS5542

.,,~

Semiconductor Corporation

22-Bit, 2-Channel, Current-Input Modulator
Features

General Description

• Delta-Sigma Architecture:
- 5th Order Modulator
- Variable Sample Rate
- 22-Bit Resolution

The CS5542 is a 22-Bit, 2-channel, 5th -order deltasigma modulator intended for direct digitization of
transducer currents. Up to four CS5542's may be connected together along with one CS5543 (8-channel
decimation filter) to form an 8-channel data acquisition
system. The CS5542 output word rate is 1000Hz per
channel.

• dc Accuracy (fsw = 250 Hz):
- Integral Linearity: ± 0.001 %FS
- Differential Linearity: ± 0.5 LSB's
- Input Offset Noise: 1.8 pARMS

Potential applications for the CS5542 are environmental
monitoring,
process
control
systems
(temperature measurement), color sensing, light measurement and control, and chemical analyzers.
The CMOS design of the CS5542 achieves high reliability while minimizing power dissipation. The device
is supplied in a 28-pin PLCC package.

• Pin selectable input range:
- IFS = ± 806 nA
- IFS = ± 1228 nA

For more information contact
C stal Semiconductor

• Low Power: 80mW
VA+

VA-

GNDL

VD+

DGND
+--- CAPSIZE

REFGNDL
INL

ITEST

1'
1-r .
_

'{-----~p__-~

5th Order
Delta-Sigma Modulator

+--- PDN
+--- MCLK
+--- FSYNC

r----.
~-

&

I

ITEST
__MUX

5

~

-~-L-----

-

DIGITAL
CONTROL
LOGIC

----~

CAL1
CALO

----. - . MDATA3

5th Order
Delta-Sigma Modulator
Right Channel
--~

INR

-4--

-4-

CALIBRATION

Left c;annel
BIAS
I
LREGULATOR

~~

- . MDATA1
- -. MDATAO

-

04---

REFGNDR

,..~~~-~

~

VREF+

VREF-

Product Preview
Crystal Semiconductor Corporation
P.o. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

GNDR

MDATA2

SELO

T2
T1
TO

SEL 1

This document contains information for a new product. Crystal

I Semiconductor reserves the right to modify this product without notice.
Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS109PP2

2-559

-,.,---,.,,.,-.,,-- -----,.,-----

CS5542

• Notes·

2.560

DS109PP2

.... ...
...,........
.........
~

~~

CS5543

~~

Semiconductor Corporation

8-Channel Digital Decimation Filter
Features

General Description

• 8-Channel Digital FI R Filter

• Self-calibration of Noise, Offset and
Gain

The CS5543 is a monolithic CMOS, 8-channel digital
FIR filter designed to be used with four CS5542 (2channel, 22-Bit modulator) to form an 8-channel data
acquisition system. The CS5543 has four I/Ocontrol
modes: normal operation, read/write calibration registers, tri-stating output pins, and test pattern generation.
JTAG Boundary-scan capability is available in the
CS5543 to facilitate self-test at the system level.

• JTAG Boundary-Scan Capability

The CS5543 is supplied in a 44-pin PLCC package.

• Pipelined Output Data Transmission
Rates up to 9.6MHz

> 120dB

• Stop-band Attenuation:

• Serial Digital Interface

For more information contact
C staJ Semiconductor

• Low Power: 75mW
VD1+ GND1

CAPSIZE
MClK
FSYNC
PDN
T[2:0]

VD2+ GND2 VD3+

GND3

DTEST[2:0]

Rsr

Control/Sequencing

CAl[1:0]

ClK
FEGAIN
OE
DATSEl [3:0]

TCK
TMS
TDI
TDO ..,.-----j'----

MDATA[3:0]

DATAIN [3:0]

DATClK
FRAME

Product Preview

Serial I/O

DATAOUT [3:0]

document contains information for a new product. Crystal
IThis
Semiconductor reserves the right to modify this product without notice.

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS181PP3
2-561

.._-_
--_..__
...-.
•

1IIr _ _ . _ .

CS5543

• Notes.

2-562

DS181PP3

....
...........
.............
~

~~~.

I CS7870

Semiconductor Corporation

CS7875

I

12-Bit, 100 kHz, Sampling AID Converters
Features

General Description
The CS7870 and CS7875 are complete monolithic
CMOS analog-to-digital converters providing 100kHz
throughput. The capacitive DAC has been calibrated
at the factory to ensure 12-bit performance.

• Monolithic CMOS AID Converter
2 /ls Track/Hold Amplifier
8 /ls AID Converter
3 V Voltage Reference
Internal Clock
Parallel, Serial and Byte Outputs

The CS7870/CS7875 have a high speed digital interface with three-state data outputs and standard control
inputs allowing easy interfacing to common microprocessors and digital signal processors.
Conversion
results are available in either 12-bit parallel, two 8-bit
bytes, or serial data.

• 12-Bit ADC and Reference Accuracy
Linearity: 0.5 LSB
SINAD: 72 dB

The CS7870/CS7875 are available in a 24-pin, 0.3"
plastic dual-in-line package (PDIP) or Cerdip. The
CS7870 and CS7875 are also available in a 28-pin
PLCC package.

• Input Ranges
±3 V for CS7870
o to +5 V for CS7875

The CS7870/CS7875 are pin compatible replacements
for the AD787017875 with equal or better performance.

• Low Power: 88 mW

ORDERING INFORMATION: Page 2-585

VDD

vss
DB11/HBEN
DB10/SSTRB

VIN

DB9/SClK

REF OUT 0+----,--------1

DB8ISDATA
DB7/l0W
DB6IlOW
DBSILOW
DB4ILOW
DB3/DB11

ClK

DB2IDB10
121B/ClK 0 - - - - - - - - - - < 1
BUS~NT~------~

'-.----..----.-'
AGND

DB1IDB9
DBOIDB8

DGND

Preliminary Product Information IThis ~ocument contains infon~ation for a. new. product. Crystal

.
Semiconductor reserves the nght to modify thiS product Without notice.

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760

(512) 445 7222 Fax: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights ReseNed)

MAR '95
DS180PP4
2-563

...._............
................
~

..... -.

CS7870/CS7875

ANALOG CHARACTERISTICS

(Voo = +5V±5%; VSS = -5V±5%; AGND = DGND = OV;
ClK = 2.5 MHz; unless otherwise specified. TA =TMIN to TMAX)
.

B
Parameter;'

Symbol

Specified Temperature Range

(Note 1)

Dynamic Performance

(Note 2)

Signal-to-Noise-and-Distortion

(Note 3)

Signal-to-Noise Ratio

Min

Typ

S
Max

Min

-40 to +85

Typ

Max

Units

°c

-55 to +125

-

72.8

-

-

dB

73

-

72.8

SNR

73

dB

-

-80

-

-80

-

-

dBc

SINAD

Total Harmonic Distortion

(Note 4)

THD

-80

-

Spurious-Free-Dynamic-Range

(Note 4)

SFDR

-80

-

Intermodulation Distortion
Second Order Terms
Third Order Terms

(Note 5)

IMD
-80
-80

-

-

-80
-80

-

-

-

dBc
dBc

INl

-

0.25

0.5

0.25

0.5

lSB

dB

Accuracy
DNl

-

-

0.5

Unipolar Offset Error

(CS7875)

VOSu

0.5

1.0

Bipolar Zero Error

(CS7870)

VOSB

-

0.5

1.0

-

0.5

1.0

-

0.5

-3
0

-

Integral Nonlinearity
Differential Nonlinearity

(Note 6)

FSEp

Biploar Negative Full Scale Error
(Note 6)
(CS7870)

FSEN

Positive Full Scale Error

-

0.5

lSB

0.5

1.0

lSB

0.5

1.0.

lSB

-

0.5

1.0

lSB

1.0

-

0.5

1.0

lSB

3
5

-3
0

-

3
5

V
V

500

-

500

!LA

-

ns

Analog Input
Input Voltage Range

(CS7870)
(CS7875)

VIN

Input Current
Aperture Delay

tapd

Aperture Jitter

tapj

Notes:

1.
2.
3.
4.
5.
6.

-

25
100

-

-

25
100

ps

All parameters guaranteed by design, test, and/or characterization.
VIN = ±3Vpp for CS7870, and OV to +5V for CS7875.
VIN = 10kHz Sine Wave, fSAMPLE = 100kHz. Typically 71.5dB for 10kHz~~

________

~,

DB11-DBO

1218/CLK =+5V.

Note:

Figure 1. Mode 1 Timing Diagram, 12-Bit Parallel Read

TRACK/HOLD
GOES INTO HOLD

~&i9EE~

12

RD

I~

INT

DATA

Iconv

_____--'-____'-'.H'-'i-Z=--________________-',"'__-'----____---j'-----_~ ~-------_«
DB7-DBO

DATA

>--

DB11-DB8

SERIAL DATA

Notes:

1. Times t2. t3. 4. t8. and t9 are the same for a high byte read as for a low byte read.
2. Continuous SCLK (Dashed line) when 12/8/CLK = -5V
Noncontinuous when 12/8/CLK = OV
External 2kn pull-up resistor.
3. External 4.7kn pull-up resistor.

Figure 2. Mode 1 Timing Diagram, Byte or Serial Read

DS180PP4

2-567

. ....,..........
.....
~

~

~~~

~~

CS7870/CS7875

~

SWITCHING CHARACTERISTICS

(Continued)

B
Parameter

Symbol

Min

Typ

S
Max

Min

-40 to +85

Specified Temperature Range

Typ

Max

-55 to +125

Units
°C

Mode 2 Timing
Conversion Time
CS to RD Setup Time

tconv

-

hs

60

-

20

-

20

MCC·

-

-

-

60

-

-

ns

-

120

ns
ns

-

-

ns

50

ns
ns

-

-

ns

70

ns

-

0.6
0.6

MCC·
MCC·

-

ns

150
100
100

ns

CS to Busy Delay

t1a

-

-

120

-

Data Setup Time

h7

-

-

CS to RD Hold Time

t1B

-

-

ta

200
0
5
0
0
60

200
0
5
0
0
75

ta

-

Output Float Delay RD Rising to Hi-Z (Note

10)

t7

HBEN to CS Setup Time

t19

HBEN to CS Hold Time

t20

RD Pulse Width
Data Access Time after RD

(Note 9)

-

50

-

-

57

-

0.6
0.6

0.4
0.4
100

ns

Serial Clock Timing
Pulse Width High
Pulse Width Low

tpwh
tpwl

11)
12)

t10

0.4
0.4
100

h2

-

SCLK rising to SSTRB

h3

Bus relinquish time after SCLK

h4

20
10

Serial Clock
SCLK to SSTRB Falling Time

(Note

SCLK rising to Valid Data

(Note

·MCC

2-568

= Master Clock Cycles,

1 MCC

= tclk

-

135
100
100

20
10

-

-

ns
ns

DS180PP4

.- ......
--.
.....,-._.
...........

CS7870/CS7875

TRACK/HOL~=-

CS

RD

GOES INTO HOLD

I"

J ~II

1

»

r-" '%.=~:::f1

BUSY

'to

I,

117 1,----'-----.1

--'»'>-__-r

DATA _ _H_i-_Z_ _ _ _ _

DATA
DB11-DBO

Note:

12/8/CLK = +5V.

Figure 3. Mode 2 Timing Diagram, 12-Bit Parallel Read

l·mEN

1

1r; ft

""~y-~--hl
I'----------.-c----,--~~

LEADING
ZEROS

/

Ito

teonv

_ (

SDATA 3

\

J

DATA

116 H 17 ~

>-------~

r-~D=B=7~-D=B=O~_ _ _ _ _ _~D=B~1~1-=D=BS~_ _

~ si, ~r-r-11-:~1-3.,~:~~~~~~~~~~~_
~5~

SERIAL DATA

Notes:

1. Times h5. hs. hg. and t20 are the same for a high byte read as for a low byte read.
2. Continuous SCLK (Dashed line) when 12/8/CLK = -5V
Noncontinuous when 1218/CLK = OV
External 2kn pull-up resistor.
3. External 4.7kn pull-up resistor.

Figure 4. Mode 2 Timing Diagram, Byte or Serial Read

DS180PP4

.2-569

......................
..,-- ._..............

CS7870/CS7875

."

DIGITAL CHARACTERISTICS (TA = TMIN to TMA)(:
Parameter

VDD = 5V±5%;Vss = -5V±5%)

Symbol

Min

Typ

Max

Units

High-Level Input Voltage

VIH

3.3

V

VIL

Input Leakage Current

lin

Input Capacitance

Cin

-

-

-

Low-Level Input Voltage

Logic Inputs
0.8

V

50
10

J.1A
pF

Logic Outputs
High-Level Output Voltage

(Note 13)

VOH

4.0

Low-Level Output Voltage

(Note 14)

VOL

-

-

OB11-0BO Floating State Leakage Current

loz

OB11-0BO Output Capacitance

Cout

-

-

-

V

0.4

V

50

J.LA

15

pF

Notes: 13. ISOURCE = -40 J.1A
14. ISINK= 1.6 mA

l:::n

±;

DBN

DBN

~50PF

T

V

DGND

a.)

High·Z to VOH

50PF

b.)

DGND

High-Z to VOL

Figure 5. Load Circuits for Access Time

l::

DBN

.

I~ IloF
~P
DGND

a.) VOH

to High·Z

DBN

±;
J

IOpF

DGND

b.) VOL to High-Z

Figure 6. Load Circuits for Output Float. Delay

2-570

DS180PP4

...
....... .....
._.
..,

..,..,

..,..,

..,~-

.."

CS7870/CS7875

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = OV.

All voltages with

respect to ground)

Parameter
Positive Analog Supply
Negative Analog Supply
Analog Input Voltage

CS7870
CS7875

Symbol

Min

Typ

Max

Units

VA+

4.75

5.0

5.25

V

VA-

-4.75

-5.0

-5.25

V

VIN
VIN

-3
0

-

+3
+5

V
V

1218/ClK Input Voltage Range

VA-, OV, VA+

V

ClKIN Input Voltage Range

0

-

VA+

V

Other Digital Input Voltage Ranges

0

-

VA+

V

AGND to DGND Voltage Differential

-

-

10

mV

Eternal Clock Frequency

-

2.5

-

MHz

ABSOLUTE MAXIMUM RATINGS

(AGND

= OV, All voltages with respect to ground)

Parameter

Symbol

Min

Typ

Max

Units

VA+

-0.3

6.0

V

12/8/ClK Input Voltage Range

(VA-)-0.3

-

ClKIN Input Voltage Range

(VA-)-0.3

-

-0.3

-

Positive Analog Supply
Negative Analog Supply
Analog Input Voltage

..

Other Digital Input Voltage Ranges

lead Solder Temperature

(VA-)-0.3

-

Sustained Digital Output Current
AGND to DGND Voltage Differential

Storage Temperature Range

0.3

VIN

-

REF OUT Current

Operating Temperature Range

VA-

CS7870175-BPlBl
CS7870175-SD

-40
-55
-65

-

-6.0

V

(VA+)+0.3

V

(VA+)+0.3

V

(VA+)+0.3

V

(VA+)+0.3

V

10

mA

5

mA

100
+85
+125

mV
DC
DC

+150

DC

+300

DC

-

• WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
NOTE:

DS180PP4

Temperatures specified define ambient conditions in free-air during test and do not refer to the
junction temperature of the device.

2-571

_-

..................
.. ._.
...............

CS7870/CS7875

GENERAL DESCRIPTION

Capacitor Array DAC Calibration

The CS7870 and CS7875 are complete 12-bit
100 kSPS sampling ADCs, utilizing a successive
approximation architecture. Factory calibration
ensures 12-bit conversion accuracy over industrial and military temperature ranges. The
CS7870 analog input range is ±3 V (0 V to +5 V
for the CS7875), with the output data provided
in parallel, byte or serial formats. The internal
capacitor array DAC acts as an inherent sampleand-hold, and forms the heart of the
CS7870/CS7875. The on-chip +3 V reference is
available at the REFOUT pin. An on-board 2.5
MHz clock oscillator is also available.

To achieve 12-bit accuracy from the capacitor array DAC, the CS7870/CS7875 uses a novel
calibration scheme. Each bit capacitor consists of
several capacitors that are trimmed to optimize
the overall bit weighting with an internal resolution of 14-bits, resulting in nearly ideal
differential and integral linearity.

OPERATIONAL OVERVIEW
Track-and-Hold Operation

Track-and-hold operation within the
CS7870/CS7875 is transparent to the user. The
capacitor array DAC acts as the hold capacitor.
During tracking mode all elements of the capacitor array DAC are switched to the analog input
for charging. The load capacitance of the entire
array during tracking mode is typically 5 pF. The
input bandwidth of the track-and-hold is typically 2 MHz. The ADC goes into hold mode on
the rising edge of CONVST.

2-572

The calibration coefficients for the capacitive bit
weights are stored in an on-chip EEPROM during the factory calibration. When the converter is
subsequently powered-up these coefficients are
applied to the capacitor array DAC. With the
DAC calibration provided automatically on
power-up, it is unnecessary to calibrate the DAC
before using the converter. Additionally, the low
temperature coefficient of the capacitor array
easily maintains 12-bit accuracy over the full
temperature range without recalibration.
Reference Operation

The reference voltage is available at the REF
OUT pin and is capable of sourcing 500 J.1A to
peripheral devices. This pin should normally be
left open. If used, it can be directly decoupled
to AGND with up to 50 pF of capacitance, or
through a 200 n resistor to a + 10 J.1F tantalum
capacitor. The reference voltage is calibrated on
power-up, with full accuracy achieved after
1.1 sec.

DS180PP4

..............
..,...... _.
............
...,

CS7870/CS7875

Analog Input

Output Coding
i

The CS7870 provides a ±3 V analog input voltage range (0 V to +5 V for the CS7875). The
equivalent analog input circuit is illustrated in
Figure 7 (shown in track mode). During hold
mode the input impedance to the device is typically 10 MO, and the various elements of the
capacitor array DAC are connected to either
AGND or VREF. In switching back from hold
mode to track mode, some elements in the capacitor array must be charged by the analog
input. For the CS7870, the worst case charging
current occurs when the analog input changes
from +3V to -3V (+5V to OV for the CS7875).

The digital output coding ...
CS7870 Input

+3V
OV
-3V

2'8 Complement OutDut
0111
1111
1111
0000
0000
0000
1000
0000
0000
Binary Output

CS7875 Input

+5V
+2.5V
OV

1111
111
0000

1111
1111
0000

1111
1111
0000

High-Speed System Clock

To ensure that the capacitor array DAC has settled to within 0.25 LSB during the allowed
acquisition time, the source resistance should be
less than 4 ill.

[VREF

lkn

VIN

15kn

~~

J

5 pF
Package
Capacitance

Capacitor
Array

~rator

AGND

The CS7870/CS7875 employs a high-speed
clock (typically 2.5 MHz) to control internal operations. This high-speed clock can be generated
internally with the on-board oscillator, or it can
be supplied from an external CMOS source.
Connecting a CMOS clock signal to the CLKIN
pin allows the converter to operate from an external clock. Alternatively, connecting the
CLKIN pin to VA- activates the internal clock
oscillator.
External Clock..... ClKIN - External Clock Source
Internal Clock ... ClKIN = VA-

Figure 7. Analog Input Model (Track Mode).

DS180PP4

2-573

•

............
..........,...
.............

CS7870/CS7875

Digital Output Formats

12181CLK
Digital Outputs
12-Bit Parallel
+VA
GND
Byte' Serial w/Non-Continuous SClK
~VA
Byte; Serial/Continuous SCLK

The CS7870/CS7875 provides three digital output formats. These include 12-bit parallel, two
8-bit bytes, and serial modes. The output data
format is controlled by the level applied to the
I2/S/CLK pin.

In byte mode, two 8-bit read operations (four
leading zeros with 4 data bits ... plus 8 more
data bits) are required to collect the data as
shown in Figure 9. In byte mode, the
DB Il11ffiEN pin defers to the HBEN function,
selecting the high or low byte of data to be read
from the ADC. The lower eight bits of data are
placed on the data bus when HBEN is held low.
To acce&s the four MSBs of data, HBEN must be
held high. The 4 MSBs of the 12-bit data word
are right justified with zeros in the upper nibble
of the high byte.

Figure 8 shows the schematic for the
CS7870/CS7875. in I2-bit parallel mode. The
twelve bits of data are output simultaneously on
DB 111(MSB) through DBO (LSB) ..

+5V

+

10J.lF~

~ O.1J.lF

17
19

VDD

22
12/8/ClK

REF OUT
18
AGND

CS7870
CS7875

24
CS
RD

----

Analog
Source

Analog
Signal
Conditioning

BUSYIINT
20

Control
logic

23

CONVST

VIN

DBO
12

2

12

DB11
DGND
VSS

ClK

-5V

Figure 8. System Connection Diagram: Parallel Data Format
2-574

DS180PP4

_.-......__
...-..
--_-_

CS7870/CS7875

In serial mode, DB8/SDATA, DB9/SCLK and
DB 10/SSTRB defer to their serial functions. The
serial strobe pin SSTRB provides a framing signal for serial data. Serial data is available at the
SDATA pin when SSTRB falls low. SSTRB falls
low within three clock cycles of CONVST. A total of sixteen bits (four leading zeros and twelve
data bits starting with the MSB) are clocked out
on the SDATA pin on the rising edge of SCLK.
The data bits become valid no more than t12 after the rising edge of SCLK. SSTRB goes low
during data transmission and automatically re+5V

10J.lF+~

turns high when the LSB has been clocked out
on the SDATA line. Serial data operation is identical for MODE 1 and MODE 2 timing control
(see next two sections). For serial operation, OV
on the 12is/CLK pin causes the serial clock to
run only when data is being clocked out of the
device; SCLK goes high after data transmission
is completed. If the 12/8/CLK is connected to VA, the SCLK output will run continuously,
independent of data transmission.

l
:&
0.1J.lF

117
VDD

REF OUT
AGND

CS7870
CS7875
Analog
Source

0--

Analog
Signal
Conditioning

20

-

- 18

-

CS
-

RD

----

VIN

19

BUSY/INT

24
1
2

Control
logic

23

CONVST
12

~
S1
S1

=A
=B

DB11/HBEN

DGND

rA>B

DB7/l0W

--

DB10/SSTRB
DB9/SClK

-

12/8/ClK
VSS
121

-5V'

10J.lF l
+

lO.1J.lF

;

DBO/DB8

Serial cl ock operates only
during data transmission.
Serial cl ock runs continuously
independent of data transmission
A S1 22

4

DB8/SDATA
ClK

8

~

./

Data
Processor

5

;

6

Serial
Data
Interface

7

3
1

I Source
Clock I

Figure 9. System Connection Diagram: Serial and Byte Data format

DS180PP4

2-575

~.
~

_.

. ..,.,.....
.............
-~

~~

~

CS7870/CS7875

~

MODE 1 Operation

conversion will read all twelve bits 'ofdata at the
same time.

The CONVST signal is used to put the device
into hold mode and initiate a conversion. At the
end of conversion the device returns to it's tracking mode. MODE 1 timing is primarily used in
DSP type applications where precise control of
CONVST timing is required.
Conversion begins on the rIsmg edge ·of
CONVST provided that CS is high. The
BUSYIINT line performs the INT function and
can be used to interrupt the microprocessor. INT
is normally high and goes low at the end of conversion. The ADC begins to acquire the analog
input when !NT goes low. Bringing CS and RD
low allows data to be read from the ADC, and
also resets !NT high. CONVST must be high
when CS and RD are brought low for the ADC
to operate correctly in this mode. Data cannot be
read during a conversion cycle because the output data latches are disabled while a conversion
is in progress.

MODE 1· 12·Bit Parallel Read
Figure 10 shows the MODE 1 timing diagram
for 12-bit parallel operation (12is/CLK = +VA).
A data read operation performed at the end of
-~.
(
CONVST
)

INT

CS

End of conversion
Acquisition begins

t

MODE 1 • Serial Read
The MODE 1 timing diagram for serial operation
is shown in Figure 12. Conversion begins on the
falling edge of CONVST, and data is clocked
out on SDATA immediately upon the falling
edge of SSTRB. The data is output as four leading zeroes followed by the twelve data bits with
the MSB first. The first zero should be latched
into the external receiving circuitry on the first
falling edge of SCLK after SSTRB goes low. A
total of sixteen falling SCLK edges will latch all
sixteen bits of output data. SSTRB automatically
returns high after the last bit of data has been
clocked out of the device.

Hold mode.
Conversion begins

'
==L

CS must be high when CONVST
goes low for C(lnversion to occur
RD

MODE 1 • Byte Read
Figure 11 shows the MODE 1 timing diagram
for byte operation. At the end of conversion
when INT goes low, -either the low byte or the
high byte of data can be read, depending on the
status of HBEN. Bringing CS and RD low allows data to be read from the ADC and also
resets INT high.

INT is reset on falling edge of CS and RD

LJ
LJ

' <'
Data relinquished
DatabilS automatically three-state
after RD goes high
~/
during a conversion ~
DATA ---------<.c,~
~~--------Figure 10. Mode 1 Timing Diagram, 12·bit Parallel Read

2·576

DS180PP4

_--_--

.-..,.....
... .......
....
CONVST

CS7870/CS7875

~

rSHoldmode.

LJ-- Conversion begins

C'ju:..- .
INT is reset on falling edge of CS and RD

INT

End of conversion
Acquisition begins -----"*I

«

t
CS must be high when CONVST
))

CS

goes low for conversion to occur
RD

J

1/

Data bits automatically three-state'-------'
during a conversion ~J

S~

DATA

DATA

ft

I

RD

h' h'-====:::'.~
goes Ig

V

I

DATA

LOW BYTE DATA 1

Note:

I

I Data r~nquished I

I

C,C

I

'---H-IG--'H BYTE DATA 1

1. In the above diagram HBEN is exercised to read the low byte first (DB7-DBO) and then the
high byte (OB11-088). To change the order in which the bytes are read, simply invert the
HBEN Signal shown above.

Figure 11. Mode 1 Timing Diagram, Byte Read

Ir-

I

CONVST
Acq.uisition - - ,
beginS
L.------i
SCLK

1

1

LJ
SSTRB

1

1

LJ

1

1

2

3

4

5

6

7

~J

: C'I
1

SDATA

f

I'

'§)
Hold mode.
Conversion begins

'----------------------------~

- - - - - - . , - :-'-,C'I

FOUR LEADING ZEROS

IDB11 IDB10 I

Figure 12. Mode 1 Timing Diagram - Serial Read

OS180PP4

2-577

...............
...... .-..,
.........

CS7870/CS7875

~

MODE 2 Operation

Mode 2 operation allows the ADC conversion to
be initiated by a read operation from a Jlc. The
BUSY signal can be used in this mode to halt
JlC operations by placing the JlC in a WAIT state
until the conversion is complete. This avoids
having to handling interrupts and timing delays ,
assuring that the conversion cycle is complete
before any attempted data read.
In this mode, CONVST must be held permanently low. Bringing CS low (while HBEN is
low) puts the device into hold mode and initiates
a conversion. The BUSY/INT pin defers to the
BUSY function such that BUSY goes low at the
start of conversion and returns high at the end of
conversion.

MODE 2 • Byte Read
Figure 14 shows the timing diagram for byte operation in MODE 2. Since HBEN must be low to
initiate a conversion, the lower byte of data will
be accessed first during the two-byte read operation. This is followed by a second byte read
operation (with HBEN high) to complete the
data transfer.
MODE 2 • Serial Read
The timing diagram for MODE 2 serial operation
is shown in Figure 15. The device goes into hold
mode on the falling edge of CS and conversion
begins when BUSY goes low. The data is
clocked out similarly as for MODE 1 serial operation. Upon clocking of the final data bit
BUSY returns high indicating end of conversion.

MODE 2 • 12·Bit Parallel Read
The MODE· 2 timing diagrams for the parallel
data output format are shown in Figure 13. This
mode of operation forces the JlC into a WAIT
state until the conversion has been completed. It
removes the risk of inadvertently reading invalid
data before the conversion cycle has been completed.
hard wire low for

CoNVST----------------------~(nh--M-O-D-._E_2_0_p_e_m_ti_o_n_______

r-= HOLD MODE

CS

RD
'§J

BUSY

Conversion
begins

Data bits automatically three-state
DATA __d_u_rin--'g<-c_o_n_v_er_s_io_n______"-=,.---'&-J(,,cc,)____~

End of conversion
Acquisition begins

DATA

Figure 13 Mode 2 Timing Diagram, 12·bit Parallel Read

2·578

DS180PP4

-. ..--_ ......-.
~~ • •~~iIIII•

CS7870/CS7875

~~

'h

CONVST
HBEN

hard wire low for MODE 2 operation

:LLLU_~------- tcbd + t cony

Figure 16. Stand-Alone Operation

Schematic &Layout Review Service

If the power supply voltage is dropped below 3V,

the ADC may need to be reset by switching
power off and then back on.
Layout considerations

The CS7870/CS7875 is a high-speed component
which requires adherence to standard high-frequency printed circuit board layout techniques to
maintain optimum performance. These include
proper supply decoupling, minimum length circuit traces, and physical separation of digital and
analog components and circuit traces. See the
CDB7870175 evaluation board data sheet for
more details.

Confirm Optimum
Schematic & Layout
Before Building Your

2-580

DS180PP4

... -...
._._...............
..__
...,

CS7S70/cS7S75

PIN DESCRIPTIONS
READ
RD
BUSY/INTERRUPT
BUSY/INT
CLOCK INPUT
ClKIN
DB11/HIGH BYTE ENABLE DB11/HBEN
DB10/SERIAL STROBE DB10/SSTRB
DB9/SClK
DB9/SERIAL CLOCK
DBS/SERIAL DATA DB8/SDATA
DATA OUT
DB7/lOW
DATA OUT
DB6/l0W
DATA OUT
DBS/lOW
DATA OUT
DB4/l0W
DGND
DIGITAL GROUND

CS
CONVST
12181ClK
Vss
VIN
REF OUT
AGND
Voo
DBO/DB8
DB1/DB9
DB2IDB10
DB3/DB11

CHIP SELECT
CONVERT START
DATA OUTPUT FORMAT
NEGATIVE ANALOG SUPPLY
ANALOG INPUT
VOLTAGE REF OUT
ANALOG GROUND
POSITIVE ANALOG SUPPLY
DATA OUT
DATA OUT
DATA OUT
DATA OUT

28-Pin Plastic and Ceramic DIPs

BUSV.: ~

~:NVST

DBl1~~~: ~ (~- ::eLK
DB1 OISSTRB

~

DB9/SClK ~
NC I
DB7/LOW ~.
/

DB6/LOW ~

4

3

2

9

28 27 26 25 ; ; -

6
7

8

DB8ISDATA ~
-

5

24
23

~::w

9
10

22

~ REF OUT
NC

-

21 "--20 \

11

19
12 13 14 15 16 17 18

VIN

.L
\--

AGND
VDD

L DBO/DBS

DBS/lOW

DB1IDB9

DB4ILOW

DB2IDB10

DGND

DB3IDB11
-NC

28-Pin PLCC

DS180PP4

2-581

.,

..............
.........
.........

-'

-'

CS7870/CS7875

Power Supply Connections

VDD - Positive Supply, PIN 17.
+SV±5%.
Vss - Negative Supply, PIN 21.
-SV±S%.
DGND - Digital Ground, PIN 12.
Ground reference for digital circuitry.
AGND - Analog Ground, PIN 18.
Ground reference for track-and~hold, reference and DAC.
Oscillator

CLK - Clock Input, PIN 3.
An external 2.5MHz (CMOS compatible) clock is applied at this pin. Connecting this pin to
Vss enables the internal clock oscillator.
Digital Inputs

CS - Chip Select, PIN 24.
Active low logic input. The device is selected when this input is active. With CONVST tied
low, a new conversion is initiated when CS goes low.
RD - Read, PIN 1.
Active low logic input. This input is used in conjunction with CS low to enable the data
outputs.
1218/CLK - Output Mode Selection, PIN 22.
_
Defines the output data format and seri~ clock format. With 12/8/CLK at +SV, the output data
format is 12-bit parallel only. With 12/8/CLK at OV, either byte or sedal data is available and
SCLK is not continuous. With 12/s/CLK at -SV, byte or serial data is again available but SCLK
is now continuous.
CONVST - Convert Start, PIN 23.
A low to high transition on this input puts the track-and-hold into i~hold mode and starts
conversion. This input is asynchronous to the CLK and independent of CS and RD.
Digital Outputs

BUSYIINT - BusylInterrupt, PIN 2.
Active low logic output indicating converter status. See timing diagrams.

2-582

DS180PP4

,...
............
.....,.. ..,.
.........

..,

..,

CS7870/CS7875

DB11IHBEN - Data Bit 11lHigb Byte Enable, PIN 4.
The function of this pin is dependent on the state of the 12is/CLK input. When 12-bit parallel
data is selected, this pin provides the DB 11 output. When byte data is selected, this pin
becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN is low,
DB7ILOW to DBOIDB8 become DB7 to DBO. With HBEN high, DB7ILOW to DBOIDB8 are
used for the upper byte of data (see Table 1).
DBI0/SSTRB - Data Bit 10/Serial Strobe, PIN 5.
The function of this pin is dependent on the state of the 12ig/CLK input. When 12-bit parallel
data is selected, this pin provides the DB 10 output. SSTRB provides a strobe or framing pulse
for serial data.

DB9ISCLK - Data Bit 9/Serial Clock, PIN 6.
The function of this pin is dependent on the state of the 12is/CLK input. When 12-bit parallel
data is selected, this pin provides the DB9 outpl!!. SCLK is the gated serial clock output derived
from the internal or external ADC clock. If 12/8/CLK is at -5V, then SCLK runs continuously.
If 12is/CLK is at Ov, then SCLK goes high after serial transmission is complete.
DB8/SDATA - Data Bit 8/Serial Data, PIN 7.
_
The function of this pin is dependent on the state of the 12/8/CLK input. When 12-bit parallel
data is selected, this pin provides the DB8 output. SDATA is used with SCLK and SSTRB for
serial data transfer. Serial data is valid on the falling edge of SCLl< while SSTRB is low.
DB7ILOW, DB6ILOW, DB5ILOW, DB4ILOW - Three-state data outputs, PINS 8,9,10,11.
The outputs of these pins are controlled by CS and RD. Their function depends on the
12/8/CLK and HBEN inputs. With 12/8/CLK high, they are always DB7-DB4. With 12/8/CLK
low or -5V, their function is controlled by HBEN (see Table 1).
DB3IDB11, DB2IDBI0, DBIIDB9, DBOIDB8 - Three-state data outputs, PINS 13, 14, 15, 16.
The outputs of these pins are controlled by CS and RD. Their function depends on the
12/8/CLK and HBEN inputs. With 12/8/CLK high, they are always DB3-DBO. With 12/8/CLK
low or -5V, their function is controlled by HBEN (see Table 1).
HBEN
HIGH
LOW

DB7ILOW
LOW
DB7

DB6ILOW
LOW
DB6

DB5/LOW
LOW
DB5

DB4JLOW
LOW
DB4

DB3/DB11
DB11/(MSB)
DB3

DB2IDB10
DB10
DB2

DB1IDB9
DB9
DB1

DBO/DBB
DB8
DBOI(LSBt

Table 1. Output Data for Byte Interfacing

DS180PP4

2-583

-

j

_......
...,...........
.....
-..._....

CS7870/CS7875

Analog Output
REF OUT - Voltage Reference Output, PIN 19.
The internal +3V reference is provided at this pin. The external load capability is 500IlA. This
pin sbould be left open. If used, it can be directly decoupled to AGND with up to 50pF, or
through a 200n resistor to a +lOIlF tantalum and O.lIlF ceramic capacitors. REF OUT settling
time is approximately 1.1 sec.

Analog Input
VIN - Analog Input, PIN 20.
The analog input range for the CS7870 is ±3V, ... OV to +5V for the CS7875.

2-584

DS180PP4

_. ......__-- ......
......~

~~

CS7870/CS7875

Ordering Information
Model

Temp
(DC)

Tempco
(ppm/DC)

SINAD
(dB)

INL
(LSB)

-40/85
-40/85
-55/125

60
60
60

72
72
72

0.5
0.5
0.5

24-pin 0.3" PDIP
28-pin PLCC
24-pin 0.3" CerDIP

-40/85
-40/85
-55/125

60
60
60

72
72
72

0.5
0.5
0.5

24-pin 0.3" PDIP
28-pin PLCC
24-pin 0.3" CerDIP

Package

=

VIN Range ±3V
CS7870-BP
CS7870-BL
CS7870-SD
VIN Range

=OV to +5V

CS7875-BP
CS7875-BL
CS7875-TD

Cross Reference List
Crystal
Semiconductor

Analog
Devices

VIN =±3V
CS7870-BP
CS7870-BL
CS7870-SD

AD7870JN, AD7870KN
AD7870JP, AD7870KP
AD7870AQ, AD7870BQ, AD7870SQ

VIN = OV to +5V
CS7875-BP
CS7875-BL
CS7875-TD

DS180PP4

AD7875KN
AD7875KP
AD7875BQ, AD7875TQ

2-585

--

...............
..,.......
.............

CS7870/CS7875

PARAMETER DEFINITIONS
REF OUT Tempco
REF OUT Tempco is the worst case slope that is calculated from the change in reference value
at +25°C to the value at TMIN or TMAX
i.e. REF OUT Tempco =(Vref @ 25°C - Vref @ TMAX)/(TMAX - 25°C) or
REF OUT Tempco = (Vref @ 25°C - Vref @ TMIN)/(25°C - TMIN).
Differential Linearity
The deviation of a code's width from ideal. Units in LSBs.
Integral Non-Linearity Error - INL
The deviation of a code from a straight line passing through the endpoints of the transfer
function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 112
LSB below the first code transition and "full-scale" is a point 112 LSB beyond the code
transition to all ones. The deviation is measured from the middle of each particular code.
FuU-Scale Error - FSEp
The deviation of the last code transition from the ideal (VREF-3/2 LSB's). Units in LSB's.
Unipolar Offset (CS7875) - VUP
The deviation of the first code transition from the ideal (112 LSB above AGND) when in. Units
in LSB's.
Bipolar Offset (CS7870) - VBP
The deviation of the mid-scale transition (011...111 to 100... 000) from the ideal (1/2 LSB below
AGND). Units in LSB's.
Bipolar Negative Full-Scale Error (CS7870) - FSEN
The deviation of the first code transition from the ideal. The ideal is defined as lying on a
straight line which passes through the final and mid-scale code transitions. Units in LSB's.
Spurious-Free-Dynamic-Range - SFDR
The ratio of the rms value of the signal, to the rms value of the next largest spectral component
( excepting de). This component is often an aliased harmonic when the signal frequency is a
significant proportion of the sampling rate. Units dBc (decibels relative to the carrier).
Total Harmonic Distortion - THD
The ratio of the rms sum of the significant harmonics (2 nd thru 5th ), to the rms value of the
signal. Units in decibels.
Signal-to-Noise Ratio (sin) - SNR
The ratio of the rms value of the signal, to the rms sum of all other spectral components below
the Nyquist rate (excepting de and distortion terms). Expressed in decibels

2-586

DS180PP4

..................
..... -._............

~

CS7870/CS7875

Signal-to-Noise-and-Distortion (s/[n+d)) - SINAD
The ratio of the rms value of the signal, to the rms sum of all other spectral components below
the Nyquist rate (excepting de), including distortion components. Expressed in decibels
Intermodulation Distortion - IMD
The ratio of the rms value of the larger of two test frequencies, which are each 6dB down from
full-scale, to the rms value of the largest 2nd and 3rd order intermodulation components. Units
in decibels relative to carrier.
Aperture Delay Time - tapd
The time required after CONVST goes high for the sampling switch to open fully. Effectively
a sampling delay which can be nulled by advancing the sampling signal. Units in nanoseconds.
Aperture Jitter - tapj
The range of variation in the aperture time. Effectively the "sampling window" which
ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. Units
in picoseconds.

DS180PP4

2-587

CDB7870
CDB7875

' - ' . . . .18'18'~.

1.==~I=1.
Semiconductor Corporation

Evaluation Board for CS7870 & CS7875
Features

General Description

• Throughput rates up to 100kHz.

The COB7870/5 Evaluation Boards allow fast evaluation of the C87870 & C87875 12-bit, 100kHz,
sampling AID Converters.
.

• Operation with on-board or off-board
clocks.

The board provides a convenient platform for easy circuit development and evaluation. A versatile tool that
can simplify design and reduce the design cycle resulting in a quicker time to market.

• Buffered serial data, 12-bit parallel
word, or two 8-bit bytes

Analog input is via a BNC connector. Buffered digital
outputs are available from the AOC in serial, 12-bit parallel word, or two 8-bit bytes formats.

• Digital and Analog Patch Areas

ORDERING INFORMATION
COB7870 Evaluation Board w.ith C87870-BP Installed
COB7875 Evaluation Board with C87875-BP Installed

• CS7870 ±3V input
CS7875 OV to +5V input

ANALOG
PATCH
AREA

VOLTAGE PROTECTION

DIGITAL
PATCH
AREA

DIGITAL
ELECTRONICS
VA+

VA-

AIN

DB11/HBEN
DB10/SSTRB
DB9/SClK
DBB/SDATA
ClKIN
DB7ILOW
DB6ILOW
DB5/l0W
DB4ILOW
DB3/DB11
DB2IDB10
CONVST
DB1/DB9
DBO/DBB

CLOCK AND
CONVERSION START
CIRCUITRY

CONVST

...!

~ffi
cs ;to

RD

CS

a: US

RD

;tJ:
FORMAT
JUMPER

Crystal SemicondL{ctor Cqrporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

SSTRB
SClK
SDATA

DO-D11
---

FORMAT

BUSYIINT

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

BUSY

MAR '95
081800B1

2-588

_.......__...-.......-..
..,

..,..,~

~

CDB7870, CDB7875

Introduction

least one individual decoupling capacitor is
provided for each IC.

The CDB7870 and CDB7875 evaluation boards
provide a tool for testing and designing with the
CS787015 series of AID Converters. The boards
are configured for operation from ±5V analog
and +5V digital power supplies. A BNC
connector is provided for the analog input signal.
An on-board jumper selects the output data and
serial clock formats.
Parallel and serial
connectors provide an interface to the digital
logic.
Power Supplies
Figure 1 shows the power supply arrangements.
±5V is required to operate the ADC and analog
portion of the board. Zener diodes are provided
for over-voltage protection. A separate +5V
digital supply is required for the digital logic. At

Analog Input Circuit

I

The analog input signal is brought on the
evaluation board via the BNC connector J8.
Diodes D 1 and D2 provide protection against
over voltage. R4 and C13 make a low pass filter,
whose comer frequency is 80 kHz. Notice that
no external trim components are required. R6 is
a 10 kn terminating resister which provides a
load for the signal source. R6 can be changed to
match the analog input source impedance if
required. The footprint is large enough to
accommodate a 50 n, 0.5 W resistor.

+5VA

AGND
r-~~~--------~-----+--------------~-5VA

+5V

Z3

lN6267
6.8v

GND

Figure 1. Power Supplies
D5180D81

~

2-589

.. ...
. ....,,-.....,..
~-

..,

.

~~-

CDB7870, CDB7875

~~

+SVA

01

BATBS

JB
AIN

200

02

BATBS

AGND

AGND

-SVA

Figure 2. Analog Input Circuit

Clock and Conversion

Figure 3 shows the on-board clock and
conversion control circuitry. The evaluation
board is designed to run off the on-board
2.5MHz oscillator (U4). The ADC can also
operate from an internal clock oscillator, by
connecting the CLKIN pin to -5VA. Test points
are provided to easily implement the internal
oscillator.
The CONVST signal on the evaluation board is
derived from the on-board 2.5MHz clock
oscillator. The 2.5MHz is divided by 25,
providing a 100 kHz signal. External signals can
be used by breaking the CONVST jumper at the
test points and attaching the external signal at
pin 6 of connector 14.
Digital Output Data

The CS7870/5 ADCs support three digital output
data formats. These include 12-bit parallel, 8-bit
byte, and serial interface formats. Several of the
ADC output pins have dual roles or modes of
operation (see the CS7870/5 data sheets). The
position of the "FORMAT" jumper determines

2-590

which output format is active, with all three
formats available through the 40-pin header 14.
Serial output data is also available through the
IO-pin header 13.
12-Bit Parallel Operation
Selecting the "+" position for the "FORMAT"
jumper places the board in 12-bit parallel mode.
AlI parallel output signals are buffered by UI
and U3, and are available on header 14 (Figure
4). The rising edge of the BUSY signal,
available on pin-40 of 14, can be used to latch
the 12-bit parallel data into subsequent digital
circuitry.
8-Bit Byte Operation
Selecting the "0" or the "-" pOSItIon for the
"FORMAT" jumper places the board in 8-bit
byte mode. The data is available on DO to D7 of
header 14 in two separate read operations. The
lower byte is read with HBEN low. The four
more significant bits are read with HBEN high.
The high byte word includes four leading zeros
(D4 to D7) to fill out the remaining four
significant bits from the ADC. AlI byte output
signals are buffered by UI and U3.

OS180081

....
.-..--._...,.
_-_-...

..,

CDB7870, CDB7875

Serial Operation
Selecting the "0" or the "-" position for the
"FORMAT" jumper also places the board in
serial mode. In the "-" position, the serial clock
SCLK operates continuously; in the "0" jumper
position, the serial clock SCLK is active only
when the ADC is outputting serial data. The
rising edge of SCLK can be used to latch serial
data into subsequent circuitry. The serial data
and control lines are available on 13, and the
DATA8
(SDATA), DATA9(SCLK), and
DATAlO (SSTRB) lines of 14. All serial output
signals are buffered by U1.
Convert Start Operation
MODE 1 Operation
The CONVST signal is used to put the ADC
into hold mode and initiate a conversion. At the
end of the conversion, the ADC returns to its
tracking mode. Conversion begins on the rising
edge of the CONVST, provided that CS is high

(note that external pull-up resistors on CS and
RD default both to logic high if no external logic
signal is present for these pins on the 14 header).
The BUSY line on 14, which goes low when the
output data becomes available, can be used as a
microprocessor interrupt. Bringing CS and RD
low allows data to be read from the ADC and
also resets BUSY high. CONVST must be high
when CS and RD are brought low in this mode.
Data cannot be read during the conversion cycle
because the ADC output latches are disabled
during this process.
MODE 2 Operation
In this mode, CONVST is held permanently low
(Break CONVST jumper at the test points and
add jumper between CONST_BUF and
CONVST_._Ground the HOLD signal 14-6).
Bringing CS low (while HBEN is low) through
the 14 header, puts the ADC into hold mode and
initiates a conversion. The BUSY line on 14
goes low at the start of the conversion and
returns high at the end of conversion.

FORMAT JUMPER

+
0

-

+5V

12-bit parallel mode
a-bit byte or serial (16 bit SCLK)
a-bit byte or serial (continuous SCLK)
FORMA T JUMPER

+

o
®+~----6.--c:> FORMAT

.------------------....,EiHfii}---'--:>CLKIN

-5VA»--€)

+5V

/CONVST
74HC390
GND

/CONVST JUMPER

Figure 3. Clock and Convert Start Circuitry
D5180DB1

2-591

.....Ii
~

~

en

IS

''',i'·

+5V

c;
Rl

.1=
."

~

1

4.7K
R2

,

FORMAT

'VV

2

lOOK

~

OATAll

Cr

REF _OUT

or

~~~ Wf-"

<

C94, TANT
10uF
TANT
10uF

Cll!

-5V An

OJ.. X7R•
Cl0
l uF

"T·
,1.. X7R

C'4T- '

elK NLJ
/eONVS r

I



,B

VOO

REF _OUT

AGNO

UF? VSS

'¥>

N LJ

L1L

20

0

~

,

....
=,"....

CJ-

OATA11

Ul

, orr
~ ~on

J4

GND..2.. AD

;
OB,o/55 B 6
DB9/5eLK 7
OBB/SDA TA r8'
DB7/LOW 9
DBS/LOW 1li

t:s

2

4.7K

YO
Y'
Y2
Y3
Y4

4 A'
A2
A3
A4
AS
9 A6
A7

OB3/DB1'
OB2/0Bl0 ,
DB'/DB9 ,
DBO/DBB

12 DGND

-

AGND

OBlI/H¥~N

g~VST
~ '2/S/eLK

GNO

~

AGHO AGND

J3

~F-..L
-O.5V
~-

R3

gmt8: 1"

VIN

~..J.

FORMA r~

,vvv-

cn

~ ~~~T ~~r

U2
;VA

®1 1
• CB

I

74He368

2

V
'~
2K

USB

~5A

*' '".Uno

Y5 "

~~

'8

OAT.ll

OATA06

"

DATA05

1-';-II-

t=

P,

les

,,

,.JlAm

,
1

74He541
U3

-J1::tm

1
RD o.

~ 0'

BU5Y/iNi

- GND

I

AID Converter

m
RIO

R9

r;::::

r-

AD
A'
A2
A3

A4
AS

AS
A7

IiY3

Y4
Y5
YS
Y7

74He54'

~
~

OATA03

YO

OA All1.
OATAGO

1

"-I

-=-

Ii:

·/DROY

HO'R20X2

GNO
OATA[OO,")

.2

.5Vo-~
10K

~ /CONVST _BUF

RB

UAAA 2
10K

o
c

j

o
~
....
co

o

C
III

....

c

Figure 4. ADC Connections and Digital Output

~

,.,,.,-.
._.-.,.,......
,.,,., ...
-~-

CDB7870, CDB7875

J4

i!§

116

000

~

i

i

D11{IISB)
DIO
DI
DI
D7

DI
D5
D4
D3
D2
Dl
DD(LS8)

-0
AIN

£'.6JJiST.;;L
SEMICONDUCTOR CORPORATIDN

Figure 5. CDB7870/CDB7875 Component Layout

05180081

2-593

__

...,.,...-.
.....
..,_..,......
....

CDB7.870, CDB7875

••••••
•••••••
•••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
•••

• • • • • • AT,a=;:;r.""",-::r,

Figure 6; Top Ground Plane Layer (NOT TO SCALE)

2-594

08180081

.. ...
...-..
......-'-'~

~

'-''-'~

~-

CDB7870, CDB7875

•••••
•••••
•••••
•••••
••••
••••
••••
••••
••••
••••
••••
••••
••••
••••

Figure 7. Bottom Trace Layer (NOT TO SCALE)

D5180D81

2-595

-___

.._-"""
...-..
. ..",-_
....

CDB7870

• Notes·

2·596

DS109PP2

.. .........
. ...,.......
."."

~~

~

I COaCAPTURE I

~~

Semiconductor Corporation

Data Capture and Interface Board for a PC
General Description

Features

The CAPTURE interface board is a development tool
that interfaces a Crystal Semiconductor analog to digital converter to a PC-compatible computer. Digital data
is collected in a high speed digital FIFO, then transferred to the PC over a serial COM port. Evaluation
software is included to analyze the data and demonstrate the analog to digital converter's performance.

• Measurement Tool used for the
evaluation of Crystal Semiconductor
Analog to Digital Converters.

• Easy interface to a PC Compatible
computer.

• LabWindows® based evaluation
software for data analysis.

• Includes time domain, FFT, and noise
distribution histograms.

• Can be used to evaluate the ADC in
your equipment.

The CAPTURE interface board is designed to be easily
interfaced to Crystal Semiconductor Evaluation boards.
Application software is loaded via the PC's serial COM
port. The software adjusts the CAPTURE interface
board for the appropriate signal timing and polarity,
coding format and number of bits, thus allowing the
same hardware to be used with a variety of Crystal
Semiconductor ADCs.
Evaluation software is included with the CAPTURE interface board. The software is developed with
LabWindows, a software development system for instrument control, data acquisition, and analysis
applications. The evaluation software permits time domain, frequency domain and histogram analysis.

ORDERING INFORMATION: CDBCAPTURE

Power
Supply \

+5 V Power
Supply
Evaluation
Software

Signal
Source

RS232 Cable

Crystal
Evaluation
Board
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

CDBCAPTURE

IBM Compatible PC
(AT or Better)

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
DS124F2
2-597

----------------

-.r _ _ _ __

COBCAPTURE

OVERVIEW
The CAPTURE interface board captures a block
of A/D converter output data, which is then
transferred to the PC. The CAPTURE board
buffers the high speed digital data in a FIFO and
transfers the data to the PC via the COM port.
Figure 1 is a functional block diagram which
illustrates the data acquisition process.
The setup for the CAPTURE board is simple. A
serial cable is connected from the evaluation
board to the CAPTURE board.. An RS232 cable
is connected from the CAPTURE board to a PC
COM port. A +5V power supply is required.
Upon reset, the microcontroller (IlC) on the
CAPTURE board begins executing boot code
from its internal EPROM. The boot code
monitors the IlC's serial port for application
software from the PC and stores the application
software in SRAM. The application software is
specific for the type of ND converter being
used. When the transfer is complete, the IlC
executes program code out of the SRAM and
turns on the LED.
With the IlC running the application software,
the data collection process can begin. The
collection process is started by a command sent
from the PC to the CAPTURE board. When the
collection command is received, the CAPTURE
board synchronizes itself to the FRAME signal
and begins capturing data from the ADC. The
serial cable signals are optically isolated for
optimum noise isolation. Data is stored in a

serial FIFO. The writing to the FIFO is
controlled by the IlC and Counter/Control
circuit.
The CAPTURE board collects one channel of
data from the ADC. When the data sample set
has been collected and stored in the serial FIFO,
the IlC reads the data out of the FIFO and
converts the format to 2's complement if
required. The data in 2's complement format is
then transferred to the PC via the RS232 cable
connected the PC's COMM port.
The evaluation software developed with
LabWindows ® performs post processing of the
digitized signal (source code included). Time
plots, FFT analysis and noise analysis are
included. The software operates upon sample
sets as large as 8192. For more sophisticated
analysis, the LabWindows® development system
can be purchased from National Instruments
(512-794-0100).
CS5012A
CS5014
CS5016
CS5030
CS5031
CS5032
CS5101A

CS5102A
CS5126
CS5317
CS5322
CS5326
CS5327
CS5328

CS5329
CS5336
CS5338
CS5339
CS5345
CS5349
CS5389

CS5390
CS5501
CS5503
CS5504
CS5505
CS5506
CS5507

CS5508
CS5509
CS7870
CS7875

Crystal Parts Supported by Capture Board
*Future products will be added with software updates.
Packaging List:

SDATA

CDBCAPTURE Interface Board
Serial Cable
EIA232 Cable (RS232)
3.5" 1.44 MB Software Diskette
RS232
CABLE

SCLK
FRAME
5V DC
GND

o

+5V DC

0

GND

Figure 1. Functional Block Diagram
2-598

DS124F2

.-_
_
..---._.
__.._-_
...-.

CDBCAPTURE

III

Figure 2. Main Menu

Figure 3. TIme Domain Analysis
DS124F2

2-599

----------- -----------

COBCAPTURE

Figure 4. Frequency Domain Analysis

Fignre 5. Histogram Analysis

2-600

DS124F2

.. ..._......,
. ..,..,......
~-

~

~~

~~

DATA ACQUISITION DATA BOOK CONTENTS

GENERAL INFORMATION
DATA ACQUISITION
General Purpose
Industrial Measurement
Seismic
High Speed
AUDIO PRODUCTS
Consumer/Professional
Broadcast
Multimedia

3

COMMUNICATIONS PRODUCTS
Infrared Transceiver
Echo Cancellers
Communications Codecs
EthernetlCheapernet
Telecom

III

APPLICATION NOTES

III
III

APPENDICES
Product Category Levels
Reliability Calculation Methods
Package Mechanical Drawings
Standard Military Drawings

•

SALES OFFICES

3·1

.... . .. ..
-. ............
..,

..,..,-

..,..,

~

CONSUMERIPROFESSIONAL

AUDIO PRODUCTS
flexible digital interface makes with CD player
circuitry, DAT recorders and DSP's.

CS3310 Volume Control
CS4329 20-bit D/A converter
The CS3310 is a stereo analog volume control, allowing volume level adjustment from -9S.SdB to
+31.SdB in O.SdB steps. The volume level is
changed via a simple serial digital control bus,
which is cascadeable for multiple parts. Low
glitch circuit design ensures no "zipper" noise during volume changes. Exceptionally low THD and
noise allow use in consumer and professional applications.
CS4303 Digital to Analog Converter
The CS4303 is an all digital I.e. containing an 8X
interpolation filter and overall 64X oversampling
delta-sigma modulator. Addition of an external
analog reconstruction filter yields 107 dB dynamic
range with superb low level linearity.
CS4328 Digital to Analog Converter
The CS4328 is the industry's first complete stereo
digital-to-analog output system. This 18-bit stereo
D/A converter uses Crystal's well established
oversampling converter techniques.
The CS4328 includes the major system elements
of 8X interpolation filter, 64X delta-sigma modulator, I-bit D/A converter and a 124 dB signal-tonoise ratio analog anti-imaging filter, all in one
packaged, tested, solution. The device features
patented delta-sigma architectures to maintain excellent distortion performance, even at low signal
levels. The output anti-imaging filters are the first
to be based on a mixed linear/switched capacitor
architecture. This approach is particularly insensitive to clock jitter and allows the benefit of scaling the bandwidth proportionally to the system
master clock. The CS4328 is therefore adjustable
for both audio and voice band applications. The
3-2

The CS4329 is a complete stereo digital-to-analog
conversion system. The device includes interpolation, l28X delta-sigma modulation, I-bit D/A
conversion, and a switched-capacitor analog low
pass filter. The on-chip switched capacitor filter
provides a high tolerance to clock jitter. The divice also features de-emphasis for 32kHz,
44. 1kHz, and 48kHz, and independent hardware
muting for the left and right output channels. This
complete D/A system is offered in a 20-pin DIP
and 20-pin SSOP package.
CS4330/113 Digital to Analog Converter

Packaged in an 8 pin SOIC, the CS4330 is the
world's smallest stereo audio DAe. This l8-bit
complete digital-to-analog output system contains
interpolation filters, l28X oversampling deltasigma modulators, I-bit D/A converters, and analog filtering. De-emphasis is also included for CD
applications.
CS5330 Low Power AID Converter
The CSS330 is a single chip, l8-bit, stereo AID
converter requiring only l2SmW of power from a
single +SV supply. The part features two l28x
oversampling delta-sigma modulators, two digital
decimation filters and a voltage reference in an
8 pin SOIC package.
CS5336/8/9 Delta-Sigma Audio AID Converters

This new class of device features 64X overs ampIing, using a delta-sigma architecture with resolutions of 16 or 18-bits. Output word rates can be
from I kHz to SO kHz. These stereo parts have 2
sample and holds, dual delta-sigma modulators,

.._-_
_.-_..__.....
..._.-.
,."

AUDIO PRODUCTS

two anti-aliasing and decimation filters, and a
voltage reference, all in a 28-pin package. Performance measurements include 95 dB dynamic
range in stereo mode, up to 100 dB in mono
mode, along with 0.0015% THD.
CS5389 & CS5390 Professional Audio Analog
to Digital Converters
The CS5389 offers dual differential inputs, with a
special modulator design to yield a dynamic range
of 107 dB. Excellent noise rejection and low idle
tones yield a superbly performing AID Converter.
The CS5390 is pin compatible with the CS5389,
and offers increased dynamic range (112 dB) and
20-bit output data words.
CS8401A, CS8402A
Transmitters

AESIEBU

&

SIPDIF

The CS8401A & CS8402A accept digital audio in
many standard formats and generate an AESIEBU
or SIPDIF compatible data stream. The CS8401A
is software programmable for mode and for chan-

nel status and user data. The CS8402A is pin programmable.
CS8411, CS8412 AES/EBU and S/PDIF Receivers
The CS8411 and CS8412 digital audio receivers
accept AESIEBU or SIPDIF signals and generate
digital audio in many standard formats. A low jitter PLL recovers a clean clock for system use.
The CS8411 is software readable for channel
status and user data. The CS8412 is pin programmable
CS8425 A-LAN - Audio Local Area Network
Transceiver
The CS8425 is an SIPDIF transceiver with onchip low jitter PLL. A ring of CS8425 devices
forms an Audio Local Area Network, where user
data bits may be used for system messages between nodes. Intended for automotive applications, the device finds use wherever audio and
some additional low bandwidth information needs
to be communicated between multiple devices.

Audio NO Converter Comparison Table
Device
Number of Bits
Dynamic Ranoe (dB)
SOIC Packaae
Filter Passband (kHz)
Filter Transition Band (kHz)
Stop Band Attenuation (dB)
Overranoe Tao Bits
LeIVRight Tag Bits
Master Clockino Mode
SCLK active edge
Master Clock Frequency (CFs)
Power Supply Voltages (V)
Operation < 30 kHz
Power Consumption mW

CS533011
18
94

CS5336
16
95

CS5338
16
95

CS5339
16
95

CS5389
18
107

CS5390
20
112

,/

,/

,/

,/

-

-

0-21.7
21.7-28
-80

0-20
20-26
-80

0-22
22-28
-80

0-22
22-28
-80

0-22
22-28
-80

0-22
22-28
-100

-

,/

,/

,/

,/

,/

-

-

,/

,/

,/

,/
,/

,/

,/

,l.
256/384/512

i

i
256/384

,l.
256/384

,l.
256/384

+3 or +5

256/384
±5

,l.
2561384

+5

+5

±5

+5

,/

,/

,/

,/

,/

,/

125

400

400

400

550

550

All frequencies are with an output word rate of 48 kHz

3-3

. __-

..... ..... ......
-~
~

--~
.~.

BROADCAST
CS4920A Multi-Standard Audio Decoder-DAC

AUDIO PRODUCTS

output level. The device requires only a +5V supply, and has a low power standby m.ode. Both
digital audio and control information is communicated over a serial bus.

The CS4920A combines a 12.2MIPS DSP with a
stereo 16-bit Digital to Analog converter. In addition, a decompressed linear PCM coded digital
output is available in industry standard SIPDIF
format. An on-chip PLL allows very flexible
clocking. DSP code for MPEG 1& 2 decompression algorithms is provided. Targetted at TV set
top audio decoder applications, this device is useful in any application where low-cost audio decompression is required. Hardware data flow con~
trol and synchronization circuitry simplify the interface of the CS4920A to a video circuit.

Intended for automotive and surround sound applications, the CS4225 includes two 16-bit ADCs
and four 16-bit DACs. The analog inputs have
leveladjustrnent and the analog outputs include an
output level attenuator. The device has many
clocking modes, including using the on-chip PLL
for locking onto an audio sample rate clock. The
CS4225 runs from +5V and has a low power
standby mode.

CS4921 MPEG 1 & 2 Audio Decoder-DAC

CS4231A PC ISA Bus Multimedia Audio Codec

The CS4921 provides all of the functional blocks
of the CS4920A. However, the CS4921 is ROM
coded to support MPEG and does not support user
programmability.

The CS4231A is a single chip with 2 16-bit NO
converters, 2 16-bit D/A converters, adjustable input gain, and adjustable output level. Also included is ADPCM compression and decompression, MPC compatible mixer, timer register for
audio/visual synchronization and 16 samples deep
FIFOs for record and playback. The devices require only a +5V supply, and have a low power
standby mode. Both digital audio and control information is communicated over a parallel bus
which meets the PC-ISA bus standard.

MULTIMEDIA
CS4215 Serial Interface Audio Codec

The CS4215 is a single 44 pin PLCC package
containing 2 16-bit NO converters, 2 16-bit D/A
converters, adjustable input gain, and adjustable
output level. Also included is a microphone preamplifier, stereo headphone driver, crystal oscillators and a mono monitoring output. The device
requires only a +5V supply, and has a low power
standby mode. Both digital audio and control in~
formation is communicated over a serial bus.
CS4216 Serial Interface Audio Codec

The CS4216 is a single 44 pin PLCC package
containing 2 16-bit NO converters, 2 16-bit D/A
converters, adjustable input gain, and adjustable
3-4

CS4225 Two ADC, Four DAC Codec

CS4232 ffigh-Integration Multimedia Audio

The CS4232 is a single chip audio codec and controller which provides compatibility with ISA
Plug-and-Play, Windows Sound System™,
SoundBlaster™, and SoundBlaster Pro games.
The CS4243 incorporates a direct music synthesizer interface, CD-ROM interface and joystick interface with a MPD-401 compatible MIDI DART;
all Plug-and-Play configurable and controlled
through the CS4332. Additional features include
an MPC Level II compliant mixer, hardware and
software based management, full duplex opera-

..

.-...... .
........
.........
..,

..,

_
~.

tion, a serial audio data port and 24mA bus drive
capability. Available in lOO-pin PQFP and TQFP
packages.
CS4248 PC ISA Bus Multimedia Audio Codec
The CS4248 is a single chip with 2 16-bit NO
converters, 2 16-bit D/A converters, adjustable input gain, and adjustable output level. The device
requires only a +5V supply, and has a low po,,:,"er
standby mode. Both digital audio and control lllformation is communicated over a parallel bus
which meets the PC-ISA bus standard.
CS9233 Wavetable Music Synthesizer and
CS8905 Digital Effects Processor
The CS9233 is a music synthesis device capable
of generating 32 simultaneous notes using high
quality wavetable synthesis algorithms. The
CS9233 integrates a specialized RISC-based signal processor core with a CISC-based microcon-

AUDIO PRODUCTS

troller and interface logic to provide a low chip
count solution. The only external components required for a complete synthesis system are one
Program ROM, one SRAM, one PCM Sample
ROM, and the CS4331 18-bit stereo oversampled
DAC. Program ROM code and Sample ROMs
for General MIDI (GM) and General Synthesizer
(GS) solutions are available from Crystal. Digital
reverb, chorus, and flange effects can be added by
including the CS8905 effects processor and one
SRAM device.
Software
To support the multimedia codec family, a wide
range of software is available. Windows and NT
drivers are available for the CS423lA and
CS4248 multimedia codecs. A comprehensive diagnostics package assists in the debug of boards.
In addition, voice recognition and text-to-speech
synthesis software demonstrates some of the capabilities of an audio equipped Pc.

3·5

•

. ..............
..........
~

-_

~~

.., ..,

AUDIO PRODUCTS

CONSUMERlPROFESSiONAL

NEW
NEW
NEW
NEW
NEW

-

CS3310 Stereo Digital Volume Control
CS4303 Digital to Analog Converter
CS4328 Digital to Analog Converter
CS4329 Digital to Analog Converter
CS4330/113 Digital to Analog Converter
CS5330 Analog to Digital Converter
CS5336/8/9 Analog to Digital Converter
CS5389 Analog to Digital Converter
CS5390 Analog to Digital Converter
CS8401N02A Digital Audio Transmitter
CS8411112 Digital Audio Receiver
CS8425 A-LAN Transceiver

3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18

BROADCAST
NEW - CS4920A Multi-Standard Audio Decoder-DAC
NEW - CS4921 MPEG 1 & MPEG 2 Audio Decoder-DAC

."

3-19
3-20

MULTIMEDIA
- CS4110 Wavetable Sample ROMs for Music Synthesis
- CS4112 Wavetable Sample ROM for Music Synthesis
- CS4215 Multimedia Audio CODEC
- CS4216 Stereo Audio CODEC "
- CS4225 Digital Audio Conversion System
- CS4231A Enhanced PC Bus Interface CODEC
NEW - CS4232 Games Compatible Plug-and-Play Audio System
- CRD4232-1 Low-Cost Reference Design
- CS4248 PC Bus Interface CODEC "
- CS8905C Programmable Effects Processor "
NEW - CS9233 Integrated Wavetable Synthesizer "
- CRD9233-1 Wavetable/Audio Reference Design
- CRD9233-2 GM/GS Music Synthesizer Daughtercard
- DRIVERS Software "
- DIAGNOSTICS Software
- CWDRGNTT Software
- CWMNLG Software

3-6

3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
3-37

....
..........

.. ...

.",

~

..,..,~.

CS331 0

~

.",.",

Semiconductor Corporation

Stereo Digital Volume Control
General Description

Features

The CS3310 is a complete stereo digital volume control
designed specifically for audio systems. It features a
16-bit serial interface that controls two independent, low
distortion audio channels.

• Complete Digital Volume Control
2 IndependentChann~s
Serial Control
0.5 dB Step Size

The CS3310 includes an array of well-matched resistors
and a low noise active output stage that is capable of
driving a 600 n load. A total adjustable range of 127 dB,

• Wide Adjustable Range
-95.5 dB Attenuation
+31.5 dB Gain

in 0.5 dB steps, is achieved through 95.5 dB of attenuation and 31.5 dB of gain.
The simple 3-wire interface provides daisy-chaining of
multiple CS3310's for multi-channel audio systems.

• Low Distortion & Noise
0.001 % THD+N
116 dB Dynamic Range

The device operates from ±5V supplies and has an input/output voltage range of ±3.75V.

• Noise Free Level Transitions

For more information see the
1994 Audio Data Book

• Channel-to-Channel Crosstalk
Better Than 110 dB

AINL 0:-=16'----.__--1

14

8

AGNDL

AOUTL

MUTE

ZCEN

15
10

2

AGNDR
Serial to
Parallel

3

CS
SDATAI

7

SDATAO

6

SCLK

Register

AINR

'>--*-_ _ _ _ _1:...:.1.c

9

AOUTR

0-"-*---1
12
VA+

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

5
VA·

VD+

DGND

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

NOV '93
DS82PP2

3"7

.',',',

..
.
. ....,..........
.
...

.."

I CS4303 I

."."

~

~'-'

~

Semiconductor Corporation

107 dB, DIA Converter for Digital Audio
Features

General Description

• Stereo Delta-Sigma DfA converter
8x Interpolation Filter
64x Delta-Sigma DAC
• Single +5V Operation

The CS4303 is a high performance delta-sigma D/A
converter for digital audio systems which require wide
dynamic range. The CS4303 includes 8x interpolation
and a 64x oversampled delta-sigma modulator that
outputs a 1-bit signal to an external analog low pass
filter. The 1's density of the 1-bit signal is proportional
to the digital input.

• Adjustable System sampling Rates
The CS4303 has a configurable input serial port that
including 32 kHz, 44.1 kHz and 48 kHz provides four interface formats. The master clock rate
• 107 dB Dynamic Range Over the
Audio Bandwidth

can be either 256 or 384 times the input word rate,
supporting various audio environments.

• ±O.0002 dB Passband Ripple
For more information see the
1994 Audio Data Book

• Flexible Serial Input Port
Supports Multiple Input Formats
16 or 18 Bit Input Words

LRCK BICK

SDATAI

DIF1 DIFO

22
VD1

AGND2
AGND1

DGND1

VA3
DOR+
DORDOL+
DOLAGND3
VA1

DZF

VA2

MUTE

RST TST1

TST2

XTI XTO CKS SCKO

DGND2

VD2

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

AUG '93
DS81PP2
3-8

.......
.. .....
.. .....

.,.,~.

CS4328

~..,

,."

.."

."

Semiconductor Corporation

18-Bit, Stereo DIA Converter for Digital Audio
General Description

Features
• Complete Stereo DAC System
8x Interpolation Filter
64x Delta-Sigma DAC
Analog Post Filter
• Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz
• 120 dB Signal-ta-Noise Ratio

The CS4328 is a complete stereo digital-to-analog output system. In addition to the traditional D/A function,
the CS4328 includes an 8x digital interpolation filter followed by a 64x oversampled delta-sigma modulator.
The modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This
architecture allows for infinite adjustment of sample
rate between 1 kHz and 50 kHz while maintaining linear phase response simply by changing the master
clock frequency.
The CS4328 also includes an extremely flexible serial
port utilizing two select pins to support four different
interface modes.

• Low Clock Jitter Sensitivity
• Completely Filtered Line-Level Outputs
Linear Phase Filtering
Zero Phase Error Between Channels
No External Components Needed

The master clock can be either 256 or 384 times the
input word rate, supporting various audio environments.

• Flexible Serial Interface for Either 16
or 18 bit Input Data

DIFO

DIF1

VD+

DGND

For more information see the
1994 Audio Data Book

AGND1

VA·

LRCK
BICK
SDATAI

VA+

1---------<..:'=.0 -VREF

AOUTL

TST
RST
AOUTR
AGND2
AGND3

CALO

CMPI

XTI XTO CKS ACKO

ACKI

CALI

CMPO

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

OCT '93
DS62F3
3-9

_I

.. .. .....,.

•~IIIIW __ •~~~
....
.."

CS4329

~~

Semiconductor Corporation

I

20-Bit, Stereo DIA Converter for Digital Audio
Features

General Description
The CS4329 is a complete stereo digital-to-analog output system. In addition to the traditional D/A function,
the CS4329 includes a digital interpolation filter followed by an 128X oversampled delta-sigma modulator.
The modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This
architecture allows for infinite adjustment of sample
rate between 1 and 50 kHz while maintaining linear
phase response simply by changing the master clock
frequency.

• 20-Bit Resolution
• Complete Stereo DAC System
128X Interpolation Filter
Delta-Sigma DAC
Analog Post Filter
• Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz

The CS4329 also includes an extremely flexible serial
port utilizing node select pins to support multiple interface modes.

• 105 dB Dynamic Range
• Low Clock Jitter Sensitivity
• Filtered Line-Level Outputs
Linear Phase Filtering
Zero Phase Error Between Channels

The master clock can be either 256, 384, or 512 times
the input word rate, supporting various audio environments.

• Flexible Serial Interface for Either 16,
18 or 20 bit Input Data
• Digital De-emphasis for 32kHz,
44.1 kHz & 48kHz
DIFO DIF1 DIF2

~
LRCK
SCLK
SDATA

~

f---

~

~

Serial Input
Interface

DEMO DEM1

~
~

f---t

~
Interpolator

De-emphasis

Delta-Sigma
Modulator

i

r-.

Delta-Sigma
Modulator

j
DGND

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

VD+

~

~
Interpolator

VA+

MCLK

Voltage Reference

-

~
DAC

~
DAC

t

-

Analog
Low-Pass
Filter

f---t

Analog
Low-Pass
Filter

--

AOUTL+
AOUTL-

--

AOUTR+

~ AOUTR-

i
AGND

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

DEC '94
DS153PP1
3-10

..... .. ...
......
~~

~~~.

ICS4330 CS4331 CS4333I

~--~~
Semiconductor Corporation

8-Pin Stereo DIA Converter for Digital Audio
Features

General Description
The CS4330, CS4331 and CS4333 are complete, stereo
digital-to-analog
output systems
including
interpolation, 1-bit D/A conversion and output analog
filtering in an a-pin package. These devices differ in
the serial interface format used to input audio data.
The CS4330, CS4331 and CS4333 are based on
delta-sigma modulation where the modulator output
controls the reference voltage input to an ultra-linear
analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 1 kHz and
50 kHz while maintaining linear phase response simply
by changing the master clock frequency.

• Complete Stereo DAC System:
Interpolation, DIA, Output Analog
Filtering
• 18-Bit Resolution
• 94 dB Dynamic Range
.0.003% THD

• Low Clock Jitter Sensitivity
• Single +3V or +5V Power Supply
• Completely Filtered Line Level Outputs
Linear Phase Filtering
• On-Chip Digital De-emphasis

The CS4330, CS4331 and CS4333 contain on-chip
digital de-emphasis, operate from a single +3V or +5V
power supply and consume only 50 mW of power with
a 3V power supply. These features make them ideal
for portable CD players and other portable playback
systems.

DEM/SCLKlCONFIG

AGND

VA+
7

LRCK

3
SDATAI
AOUTL

Analog
Low-Pass
Filter

AOUTR
5

MCLK

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

Jan '95
DS136PP1
3-11

..""''''''... ..
. ........
....
~

~

.,

~~

CS5330 CS5331I

."

Semiconductor Corporation

8-Pin, Stereo· AID Converter for Digital Audio
Features

General Description
The CS5330/CS5331 are a complete stereo analog-todigital converter which performs anti-alias filtering,
sampling and analog-to-digital conversion generating
18-bit values for both left and right inputs in serial form.
The output word rate can be up to 50 kHz per channel.

•

Single +3 V or +5 V Power Supply

•

18 Bit Resolution

•

94 dB Dynamic Range

•

Linear Phase Digital Anti-Alias Filtering
0.05dB Passband Ripple
80dB Stopband Rejection

•

Low Power Dissipation: 50 mW
Power-Down Mode for Portable
Applications

•

Complete CMOS Stereo AID System
Delta-Sigma AID Converters
Digital Anti-Alias Filtering
StH Circuitry and Voltage Reference

•

The CS5330/5331 operate from a single +3V or +5V
supply and requires only 70 mW for normal operation,
making it ideal for battery-powered applications.
The ADC uses delta-sigma modulation with 128X oversampling, followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The linear-phase digital filter has a passband to
21.7 kHz, 0.05 dB passband ripple and >80 dB stopband rejection. The device also contains a high pass
filter to remove DC offsets.
The device is available in a 0.208" wide 8-pin SOIC
surface mount package.

Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz

MCLK

Voltage Reference

SCLK

LIR

I

SDATA

AINL
Digital Decimation
Filter

Digital Decimation
Filter

AINR

High
Pass
Filter

AGND

VA+

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights ReseNed)

JAN '95
DS138PP1
3-12

.. ..,..
...,...........
.., ......
~

I CS5336 CS5338 CS5339I

..,..,~

Semiconductor Corporation

16-8it, Stereo AID Converters for Digital Audio
Features

General Description

• Complete CMOS Stereo AID System
Delta-Sigma AID Converters
Digital Anti-Alias Filtering
StH Circuitry and Voltage Reference

The CS5336, CS5338 & CS5339 are complete analogto-digital converters for stereo digital audio systems.
They perform sampling, analog-to-digital conversion and
anti-aliasing filtering, generating 16-bit values for both
left and right inputs in serial form. The output word rate
can be up to 50 kHz per channel.

• Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz
• Low Noise and Distortion
>90 dB St(N+D)

The ADCs use delta-sigma modulation with 64X oversampling, followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.

• Internal 64X Oversampling

The CS5336 & CS5338 have an SCLK which clocks out
data on rising edges. TheCS5339 has an SCLK which
clocks out data on falling edges.

• Linear Phase Digital Anti-Alias Filtering
0.01 dB Passband Ripple
80dB Stopband Rejection

The CS5336 has a filter passband of dc to 22kHz. The
CS5338 & CS5339 have a filter passband of dc to 24
kHz. The filters have linear phase, 0.01 dB passband
ripple, and >80 dB stopband rejection.

• Low Power Dissipation: 400 mW
Power-Down Mode for Portable
Applications

The ADC's are housed in a 0.6" wide 28-pin plastic DIP,
and also in a 0.3" wide 28-pin SOIC surface mount
package. Extended temperature range versions of the
CS5336 are also available.

• Evaluation Board Available

For more information see the
1994 Audio Data Book
OClKD

IClKD

FSYNC SClK

LJR

VREF

SDATA
CMODE
SMODE

AINl
ZEROl

Digital Decimation
Filter
,11
TST

AINR

Digital Decimation
FiRer

ZEROR

NC

AGND

NC

VA+

VA-

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760

(512) 445 7222 FAX: (512) 445 7581

Vl+

lGND

DCAl DPD

VD+

DGND

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

AUG '93
DS23F1

3-13

.",

.......
............
~~~

I

CS5389

. . . . J!IItI . . . . .. .

Semiconductor Corporation

18-Bit, Stereo AID Converter for Digital Audio
Features

General Description

• Complete CMOS Stereo AID System
Delta-Sigma AID Converters
Digital Anti-Alias Filtering
StH Circuitry and Voltage Reference

The CS5389 is a complete analog-to-digital converter for
stereo digital audio systems. It performs sampling, ana"
log-to-digital conversion
and
anti-alias
filtering,
generating 18-bit values for both left and right inputs in
serial form. The output word rate can be up to 50 kHz
per channel.

• Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz

The CS5389 uses 5th-order, delta-sigma modulation
with 64X oversampling followed by digital filtering and
decimation, which removes the need for an external antialias filter. The ADC uses a differential architecture
which provides excellent noise rejection.

• 107 dB Dynamic Range (A-Weighted)
• Low Noise and Distortion
100 dB THD + N

The CS5389 has a filter passband of dc to 24kHz. The
filters have linear phase, 0.01 dB passband ripple, and
>80 dB stopband rejection.

• Intemal 64X Oversampling
• Linear Phase Digital Anti-Alias Filtering

The CS5389 is targeted for the most demanding
professional audio systems requiring wide dynamic
range and low noise and distortion.

• Low Power Dissipation: 550 mW
Power-Down Mode

For more information see the
1994 Audio Data Book

• Evaluation Board Available
IClKA

APD

ACAl

OClKD

FSYNC

IClKD

VREF+
VREF-

SClK

UR

SDATA
Serial Output Interlace

CMODE
SMODE

AINlAINl+

Digital Decimation
Filter
r - - - , Comparator

Digital Decimation
Filter

AINRAINR+

AGND

24
VA+

VA-

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

Vl+

lGND

DCAl

DPD

VD+

DGND

Copyright © Crystal Semiconductor Corporation 1995
(All Rights ReseNed)

SEPT '93
DS87PP2

3-14

.. .. .......
..............
."."

~

CS5390

,.,..,~

Semiconductor Corporation

20-Bit, Stereo AID Converter for Digital Audio
Features

General Description
The CSS390 is a complete analog-to-digital converter for
stereo digital audio systems. It performs sampling, analog-to-digital
conversion
and
anti-alias
filtering,
generating 20-bit values for both left and right inputs in
serial form. The output word rate can be up to SO kHz
per channel.

• 112 dB Dynamic Range (A-Weighted)
•

THO + N better than -103dB

• Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz

The CSS390 uses Sth-order, delta-sigma modulation
with 64X oversampling followed by digital filtering and
decimation, which rElr:noves the need for an external antialias filter. The ADC uses a differential architecture
which provides excellent noise rejection.

• Complete CMOS Stereo AID System
Delta-Sigma AID Converters
Digital Anti-Alias Filtering
S/H Circuitry and Voltage Reference

The CSS390 has a filter passband of dc to 21.7kHz. The
filters have linear phase, O.OOS dB passband ripple, and
>100 dB stopband rejection.

• Internal 64X Oversampling
• Linear Phase Digital Anti-Alias Filtering
> 1OOdB StopBand Attenuation
0.005dB Passband Ripple

The CSS390 is targeted for the highest performance
professional audio systems requiring wide dynamic
range, negligible distortion and low noise. Pin compatibility with the CSS389 allows a simple upgrade path
without hardware changes.

• Low Power Dissipation: 550 mW
Power-Down Mode
• Pin Compatible with CS5389

For more information see the
1994 Audio Data Book

• Evaluation Board Available
IClKA

APD

ACAl

OClKD

IClKD

FSYNC

SClK

uR

VREF+
VREF-

SDATA
CMODE
SMODE

AINlAINl+

Digital Decimation
Filter

AINR-

Digital Decimation
Filter

AINR+

AGND

VA+

VA-

Vl+

lGND DCAl

DPD

VD+

DGND

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760

(512) 445 7222 FAX: (512) 445 7581

Copyright © Crystal Semiconductor Corpor;;ltion 1995
(All Rights Reserved)

JAN '9S
DS10SPP2
3-15

i

~,';

-=--r

. ..........,.
...........
. . . . . . . .J8!f~ •

CS8401 A CS8402A

Semiconductor Corporation

I

Digital Audio Interface Transmitter
Features

General Description

• Monolithic Digital Audio Interface
Transmitter
• Supports: AES/EBU, IEC 958,
S/PDIF, & EIAJ CP-340
Professional and Consumer Formats
•
•
•
•
•

Host Mode and Stand Alone Modes
Generates CRC Codes and Parity Bits
On-Chip RS422 Line Driver
Configurable Buffer Memory (CS8401 A)
Transparent Mode Allows Direct
Connection of CS8402A and CS8412
or CS8401 A and CS8411 A

The CS8401/2A are monolithic CMOS devices which
encode and transmit audio data according to the
AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340 interface
standards. The CS8401/2A accept audio and digital
data, which is then multiplexed, encoded and driven
onto a cable. The audio serial port is double buffered
and capable of supporting a wide variety of formats.
The CS8401A has a configurable internal buffer memory, loaded via a parallel port, which may be used to
buffer channel status, auxiliary data, and/or user data.
The CS8402A multiplexes the channel, user, and validity data directly from serial input pins with dedicated
input pins for the most important channel status bits.

For more information see the
1994 Audio Data Book
MCK

CS8401A
15

15

6

SCK

Audio

7

FSYNC

CS

14
16

RDIWR

,

A4·AO

........

D7·DO

5

Configurable

...

Buffer
Memory

' ....

~

B

M2

CS8402A

SCK

1

6

23

122

Serial Port

8

SDATA

Ml

L---.

c
U

V

10
11

rL

t Prescaler

t

~
MUX

~
RS422 Driver

U

TXP

17
TXN

MO

MCK

RST

+5

121

~ 16

Audio

7

FSYNC

r-

Serial Port

B

SDATA

Registers

Ii

J

20

TXP

RS422 Driver

MUX

r+

17

TXN

7

9
15
Dedicated Channel

CBl

24
TRNPT

Status Bits

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760

(512) 445 7222 FAX: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

NOV '93

DS60F1
3-16

.. ..-

_~..w..,,.
_ .. _
--~~

CS8411 CS8412I

~--~~---~
Semiconductor Corporation

Digital Audio Interface Receiver
Features

General Description:
The CS8411 /12 are monolithic CMOS devices which receive and decode audio data according to the
AES/EBU, IEC 958, SIPDIF, & EIAJ CP-340 interface
standards. The CS8411/12 receive data from a transmission line, recover the clock and synchronization
signals, and de-multiplex the audio and digital data. Differential or single ended inputs can be decoded.

• Monolithic CMOS Receiver
• Low-Jitter, On-Chip Clock Recovery
256xFs Output Clock Provided
• Supports: AES/EBU, IEC 958,
S/PDIF, & EIAJ CP-340
Professional and Consumer Formats

The CS8411 has a configurable internal buffer memory,
read via a parallel port, which may be used to buffer
channel status, auxiliary data, and/or user data.

• Extensive Error Reporting
Repeat Last Sample on Error Option

The CS8412 de-multiplexes the channel, user, and validity data directly to serial output pins with dedicated
output pins for the most important channel status bits.

• On-Chip RS422 Line Receiver

For more information see the
1994 Audio Data Book

• Configurable Buffer Memory (CS8411)
VD+

DGND

VA+

CS8411

FllT

AGND

MCK

20

22

8

SDATA
SCK
FSYNC
A4IFCK

RXP

4

Clock & Data
Recovery

RXN

A3·AO

8
D7·DO
Memory

CS
RDIWR

VD+

DGND

VA+

8

CS8412

FllT

AGND

20

22

21

ERF
MCK

INT
M3 M2 M1 MO

19
SDATA

Audio
Serial Port
RXP

SCK
FSYNC

Clock & Data
Recovery

RXN

C

U
VERF
15

13

CS121
FCK

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

SEl

COl Cal Cbl Cel
EO E1
E2 FO

Cd!
F1

Cel
F2

ERF

CBl

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

NOV '93
DS61PP4
3-17

-

......... .....,.
~

~~~.

CS8425

~~

~

~~

Semiconductor Corporation

A-LAN - Audio Local Area Network Transceiver
Features

General Description
The A-LAN chip is a monolithic CMOS circuit that implements the physical layer of an Audio Local Area
Network. The A-LAN allows numerous pieces of audio
equipment such as CD players, digital equalizers, digital tape decks, DACs, amps, etc. to be connected in a
ring topology, sharing audio data from a designated
source. Control and configuration messages are
passed between nodes via a unique application of the
user channel.

• Monolithic Digital Audio Transceiver for
Point-to-Point Transmission of Audio Data
• Supports D2B OPTICAL
• User Channel Used for Communication of
System Messages Between Nodes
• gonfigurable Interface Port Supports SPI,
I C BUs®, Parallel Interface, or the
CS8425 Operates as Stand-alone Unit

Audio data is transmitted using the format specified by
IEC-958, and can be generated by anyone of multiple
nodes on the A-LAN. External drivers and receivers
are required for interface to the transmission media.

• Supports Large Number of Nodes per
Network

For more information see the
1994 Audio Data Book

• Also Applicable as General Purpose
IEC-958 Digital Audio Transceiver
FlT

Ml-o
M2=O

RX

'I

XTO

Ii

Clock
Data
Recovery

XTI

RMCK

1

1

Clock Manager

----<

RFSY RCBl RBCK RSDAO

j-

~

~

Mux

I

NV\

INT

I-

r---

I----

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

I
l

Receive
Common
Channel

I

Transmit
Common
Channel

I

TMCK

REPRESENTS
PARALLEL
INTERFACE

Letch

Interrupt
Control

r
Transmit
Timing

WR

Address

DGND

TX

RCBIT
AO-A7/DO-D7
ALE
RD

T
T I

Control &
Status
Registers
16*8
Transmit
buffer
16*8

REMPH

I - - RlBIT

1

AGND

RESET

r--

Receive Audio Port

Receive
Buffers
1'16*8

V+A

VERF

Transmit Audio Port

~
}[

1 1 1 1 1 1
TFSY

TBCK
TCBl

RUBIT

TUBIT
TV
TEMPH

TSDA1
TSDA2

TSDAO

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

AUG '93
DS93PP3
3-18

. .........
..........,.
..,

I CS4920A I

"'~ ••"'I8f1~ •

Semiconductor Corporation

Multi-Standard Audio Decoder - DAC
Features

General Description
The CS4920A is a complete audio subsystem on a
chip. The CS4920A is based on a programmable DSP
core and is intended to support a wide variety of digital
signal processing applications which include decoding
compressed digital audio. Serial audio data broadcast
on networks such as cable TV, direct broadcast satellite TV, or the telephone system can be decompressed
and converted to standard analog or digital signals.

• General Purpose Digital Signal
Processor Optimized for Audio
-24 Bit Fixed Point
-48 Bit Accumulator
-12.2 MIPS @ 48kHz Sample Rate
• On-Chip Functional Blocks Include:
-CD Quality D/A Converter
-Programmable PLL Clock Multiplier
-AES/EBU - S/PDIF Compatible
Digital AudioTransmitter
-Audio Serial Input Port
-Serial Control Port

Both industry standard and proprietary DSP algorithms
can be supported. Software which performs industry
standard MPEG layers 1 and 2 with support for 48,
44.1, 32, 24, 22.05, and 16kHz sampling and a complete set of software development tools are available.
These include an assembler, simulator, and debugger.

• Applications Include:
-Audio Decompression
-MPEG1 & 2 Layers I, II for:
Elementary Streams
MPEG1 Packets
MPEG2 PES

PC based software drivers for Windows and DOS are
available.

• Standard 44 pin PLCC Package

VD1-VD4

I

PIO

I

I

SCK/SCL SDAlCDOUT CDIN CS REO

I

!

1

--

I

I

1 1

Serial Control Port (SPI or 12c)

"--0

RESET

>-----+

XF
SCRCLK
BOOT

Serial
Audio
Port

"--0
"--0

--->
--->

Stereo
DAC

----->

FSYNC
SCLK
SDATA

VA+

-

-

DSP

AES/EBU - SIPDIF
Transmitter

=-'1

~

SCAlPCR
Counter

r----+
I

I

I

I

DGND1-DGND4

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

r

MONO
AOUTL
AOUTR

TX

PLL
+
Clock Manager

T

T

T

~

FLT CLKIN EXTCKALTCLKCLKOUT

I I
AGND

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

DEC '94
DS113PPO
3-19

_i

.
...,....,..........
.
...
~

I CS4921 I

~~~

~.,

~

Semiconductor Corporation

MPEG1,2 Audio Decoder -DAC
Features

General Description
The CS4921 is a complete audio subsystem on a chip.
This device decompresses the ISO MPEG Layers I
and II audio streams with all compliant bit rates and
sample rates (including half sample rates). The resulting audio samples are sent to the on-chip 16 bit stereo
DAC and optionally to the AES·EBU • S/PDIF output.
The internal resolution of the decompressed audio is in
excess of 18 bits. This resolution may be realized
through the 24 bit architecture of the S/PDIF interface.

• Fully integrated ISO MPEG audio
subsystem
• Supports MPEG Elementary Streams,
MPEG1 Packets, MPEG2 PES, and
PCM Audio Passthru
• Decompresses Mono, Dual mono,
Stereo, Joint stereo
• Supports all samples rates and bit rates
• On-Chip Functional Blocks Include:
-CD Quality DfA Converter
-Programmable PLL Clock Multiplier
-AESfEBU - SfPDIF Compatible
Digital AudioTransmitter
-Audio Serial Input Port
-Serial Control Port

The Clock Manager is a programmable PLL which is
used to generate the oversample clock for the Delta
.Sigma DACs. Through this architecture, the CS4921
supports 48kHz, 44.1 kHz, 32kHz, 24kHz, 22.05kHz,
and 16kHz sample rates by reading the MPEG audio
stream information and programming the PLL for the
proper operation. This eliminates the requirement for
external oscillators for data conversion. PCM sample
rates as low as 7kHz are also supported.

• Standard 44 pin PLeC Package
• Pin Compatible with CS4920A

VD1-VD4

FSYNC
SClK
SDATA

Xf:
SCRClK

SCKlSCl SDAlCDOUT CDIN CS REO

MPEG 1 &2
layers I,ll
and PCM
Processor

Serial
Audio
Port

SCAlPCR
Counter

~

DGND1-DGND4

VA+

Stereo
DAC

AES/EBU • SIPDIF
Transmitter

PLL
+
Clock Manager

FlT ClKIN EXTCKAlTClKClKOUT

AGND

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

DEC '94
DS113PPO
3-20.

....,.......
.. .
................
~

CS4110
CS4111

~~~

Semiconductor Corporation

Wavetable Sample ROMs for Music Synthesis
Features

General Description
The CS4110 and CS4111 16-Mbit Read Only Memories (ROMs), contain PCM waveform data used by the
Crystal family of wavetable music synthesizers, the
CS9203 & CS9233 devices, to produce high fidelity
music and special effects. Used with the apprpriate
firmware, full General MIDI (GM) compliancy and Roland General Synthesis compatibility (as implemented
in the Sound CanvasTM) is acheived.

• General MIDI compliant melodic
instrument and percussion sets
• Sound Canvas™ compatible drum
kits, special effects and instruments
• Upgradeable PCM sample set:
- CS4110, General MIDI plus extras
- CS4111, optional GS upgrade
- combined, full Sound Canvas set
• PCM data for nearly 400 sounds (225
instrument sounds, 120 percussion
sounds and 48 special effects)
• Compressed data, static, low-power
CMOS operation, TTL-compatible 1/0

>->--

>:-

Row
Decoder
Driver

,-------l

(A-l)A19

-

Column

~ t---< Decoder
i- t---< Driver ~
l - l----<

I

The base sample set is the CS411 0; the CS4111 is an
optional upgrade/expansion. Combined the devices
contain 32-Mbits of PCM data. Proprietary compression and data reduction techniques were used to
minimize storage requirements.
The CS4110 and CS4111 offer a power-down mode
controlled by the Chip Enable CE input.

For more information contact
our sales re resentative Cha ter

ROM Array

GENERAL

mliJl

III· ..... ·111

INSTRUMENT

Column Select
Circuitry

IWr-f;
-+1>-"
v

CE
OE

BHE

V

r-------'O

~

Control
Logic

~

-:--

nr---t>I
'.J',Y-

vry..

~t~

Crystal Semiconductor Corporation

ag

-v-p- 09
§~

I"

P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

00
01
02
03

010
011
012
013
014
015

Copyright © Crystal Semiconductor Corporation 1995
(All Rights ReseNed)

OCT '94
DS140PP1
3-21

.. ... ..
...,..........
~~

~~~

CS4112I

~

.",.",

Semiconductor Corporation

Wavetable Sample ROM for Music Synthesis
Features

General Description
The CS4112 Read Only Memory (ROM), organized 1M
x 8bits, contains PCM waveform data used by the
CS9203/CS9233 family of wavetable music synthesizers and associated firmware to provide complete
General MIDI (GM) compliant and Roland General
Synthesis (GS) compatible instrument sound sets.

• General MIDI compliant melodic
instrument and percussion sets

™

• Sound Canvas
compatible drum kits
and special effects sounds
• Compressed data may be used to
generate up to 343 sounds (190
instrument sounds, 107 percussion
sounds and 46 special effects)

Proprietary compression and data reduction techniques
were used to minimize stored data. When combined
with Crystal's high-quality music synthesis algorithms
(implemented in the CS9203/CS9233 devices) high
fidelity music and special effects result.

• Low-power operation:
Operating current: 15 rnA (max.)
Standby current: 100 J...lA (max.)

The CS4112 offers a power-down mode controlled by
the Chip Enable CE input.

• Static CMOS operation,
TTL-compatible I/O

CE

{--

OE

r---

CONTROL
LOGIC

r------'

r-------'

1

I

:

r----r--- V-DECODER
r------o
r---

·

WAO-WA19

·
··
··

r--

OUTPUT
BUFFERS

X-DECODER

·

/-

II-

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 4622723

···
··
··
I
:

i

··
r----

}

WDO-WD7

GENERAL

mliJl
INSTRUMENT

V-SELECT

PCM
SAMPLE
MEMORV

r------'

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

OCT '94
DS177PP1

3-22

""'....
...
..........
..,.."'""'" ...
~~

CS4215

."

Semiconductor Corporation

16-8it Multimedia Audio Codec
Features

General Description

• Sample Frequencies from 4 kHz to 50 kHz
16-bit Linear, a-bit Linear,
or A-Law
• Audio
Data Coding
• Programmable Gain for Analog Inputs
Attenuation for Analog
• Programmable
Outputs
• On-chip Oscillators
• +5V Power Supply
• Microphone and Line Level Analog Inputs
• Headphone, Speaker, and Line Outputs
• On-chip Anti-Aliasing/Smoothing Filters
• Serial Digital Interface

The CS4215 is a single-chip, stereo, CMOS multimedia
codec
that
supports
CD-quality
music,
FM radio-quality music, telephone-quality speech, and
modems. The analog-to-digital and digital-to-analog
converters are 64xoversampled delta-sigma converters
with on-chip filters which adapt to the sample frequency selected.

~-Law,

The +5V only power requirement makes the CS4215
ideal for use in workstations and personal computers.
Integration of microphone and line level inputs, input
and output gain setting, along with headphone and
monitor speaker driver, results in a very small footprint.

For more information see the
1994 Audio Data Book

CMOUT
UNL

1--.-----+1 unsigned ,---------<00

UNR

11-law
A-law

MINL

,-----~-O

SCLK

,-------->0 FSYNC

MINR
SDIN

SDOUT

, - - - - - Q TSIN

r------Ls;,~~~;rt--L-~~~~---~ TSOUT

CLKIN
CLKOUT

,--------->0 VREF
MOUn

XTLllN

8

XTL10UT
XTL21N
XTL20UT

MOUT2

unsigned

LOUTR

11-law

LOUTL
HEADC

PIOO
PIOl

HEADR

DIG
RESET
PDN

HEADL

VAl

VA2

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

VOl

VD2

AGNDl

AGND2 DGNDl

DGND2

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

SEPT '93
DS76F2
3-23

_".l~.

,i

..
.
. ..,.,..,.......
.....
,-,-.'

.."

,-,,-,

CS4216

'-''-'

Semiconductor Corporation

16-8it Stereo Audio Codec
Features

General Description

• CMOS Stereo Audio Input/Output System
Delta-Sigma AID Converters
Delta-Sigma D/A Converters
Input Anti-Aliasing and Output
Smoothing Filters
Programmable Input Gain and
Output Attenuation
• Sample Frequencies of 4 kHz to 50 kHz
• CD Quality Noise and Distortion
< 0.01 %THD

The CS4216 Stereo Audio Codec is a monolithic
CMOS device for computer multimedia, automotive,
and portable audio applications. It performs AID and
D/A conversion, filtering, and level setting, creating 4
audio inputs and 2 audio outputs for a digital computer
system. The digital interfaces of left and right channels
are multiplexed into a single serial data bus with word
rates up to 50 kHz per channel. Up to 4 CS4216 devices can be attached to a single hardware bus.
Both the ADCs and the DACs use delta-sigma modulation with 64X oversampling. The ADCs include a digital
decimation filter which eliminates the need for external
anti-aliasing filters. The DACs include output smoothing
filters on-chip.

• Internal 64X Oversampling
• Low Power Dissipation: 80 mA
1 mA Power-Down Mode

For more information see the
1994 Audio Data Book

RESET
--'

PDN

0:0
Wo:

lOUT

3:1OZ

a.8
ROUT

SMODE3

D01
MF5: D02/1 NT
MF2:D03lF2ICDIN
MF1 :D04/F1/CDOUT
DI1
MF6:DI2IF1
MF3:DI3IF3/CClK
MF4:DI4IMAlCCS

SMODE2
SMODE1
SDIN
SDOUT
SClK

REFGND
REFBYP
REFBUF

SSYNC

LlN1
LlN2

MF7:SFS1/F2
MF8:SFS2IF3

RIN1
RIN2

ClKIN

VD

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX: (512) 445 7581

VA

DGND

AGND

Copyright © Crystal Semicondutor Corporation 1995
(All Rights Reserved)

Oct '93
DS83F2
3-24

..

...........
.,
.... ...
~.-

.".,,~.

~

CS4225

,."

Semiconductor Corporation

Digital Audio Conversion System
Features

Description
The CS4225 is a single-chip, stereo analog-to-digital
and quad digital-to-analog converter using delta-sigma
conversion techniques. Applications include CD-quality
music, FM radio quality music, telephone-quality
speech. Four D/A converters make the CS4225 ideal
for surround sound and automotive applications.

• Stereo 16-bit AID Converters
• Quad 16-bit D/A Converters
• Sample Rates From 4kHz to 50kHz

• > 100 dB DAC Signal-to-Noise Ratio

The CS4225 is supplied in a 44-pin plastic package
with J-Ieads (PLCC).

• Variable Bandwidth Auxiliary 12-bit AID
• Programmable Input Gain & Output
Attenuation
• +5V Power Supply
• On-chip Anti-aliasing and Output Smoothing Filters

For more information see the
1994 Audio Data Book

• Error Correction and De-Emphasis

SCUCCLKlIFO AD2ICDINfCKF1

SDAlCDOUTfCKFO AD3ICSfIF1 VREF CMOUT

VD+ VA+

DEM

HIS
RST·PDN
LRCK

f-------.a

AOUT2

f-------.a

AOUT3

SCLK
SDIN1
SDIN2

1 - - - - - 0 0 0 AOUT4

SDOUT1

ISO/ADO,
1r===jr=~=J"-L===:;r===j- .----+--+--{j IS1fAD1
AIN1L
AIN1R

SDOUT2
DIFfHOLD

AIN2L
AIN2R

AINAUX

~~

OVL

____-6__
CLKOUT

~-6

______

XTI XTO

~

FILT

__

~~

__

~

____6 -__

-£~

______

(512) 445 7222 FAX: (512) 445 7581

~AGND2

CL CR DATAUX LRCKAUX SCLKAUX AGND1 DGND

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760

AIN3L
AIN3R

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

NOV '93
DS86PP8

3-25

-

... ....
...........

......
.".,,~.
..,,.

CS4231A

~

Semiconductor Corporation

Parallel Interface, Multimedia Audio Codec
Features

General Description

• Windows Sound System™
Compatible Codec
• ADPCM Compression/Decompression
• Extensive Software Support
• MPC Level 2 Compatible Mixer
• Dual DMA Registers support Full
Duplex Operation
• On-Chip FIFOs for higher performance

The CS4231 A includes stereo 16-bit audio converters
and complete on-chip filtering for record and playback
of 16-bit audio data. In addition, analog mixing and
programmable gain and attenuation are included to
provide a complete audio subsystem. A selectable serial port can pass audio data to and from DSPs or
ASICs. High-performance software drivers for various
operating systems are available that support all the
CS4231A features including full duplex transfers. The
CS4231A is a pin compatible upgrade to the CS4231
and CS4248.

• Selectable Serial Audio Data Port
• Pin Compatible with CS4231/CS4248
VD1

VD2

VD3

VD4 SDOUT SDIN SCLK FSYNC VREF

VREFI

LFILT RFILT

VA1 VA2

LMIC
RMIC
t < - - - < r - - - 4 LLINE
t<--~r---4 RLiNE
t<-""----r-r---4 LAUX1
H-t----r-r---4 RAUX1

Linear
W1aw
A·law
ADPCM

FIFO

16
Samples
RD
WR

PDRQ

MOUT

j-t==='-~~~~
DGND1

DGND2

DGND3I41718

TEST

Crystal Semiconductor Corporation
P.o. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

XTAL11

XTAL10

XTAL21

XTAL20

MIN

AGND1

LAUX2
RAUX2

AGND2

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '94
DS139PP1
3-26

....
......... ...
.....
~

~

CS4232

~-~
."
Semiconductor Corporation

"""

Games Compatible Plug-and-Play Audio System
•

Com~atible with Sound Blaster™, Sound Blaster
ProT ,and Windows Sound System™

•

Fully Plug and Play Compatible

•

Industry Leading Delta-Sigma Data Converters

•

ADPCM, ~-Law & A-Law
Compression/Decompression

•

Dual DMA Support w/FIFOs, Full Duplex Operation

•

MPC Level-2 Compatible Mixer

•

Joystick Port and MPU-401 Compatible MIDI
Interface

•

Optional CD-ROM Interface

•

External FM and Wave Table Synthesizer Support

•

Serial Audio Data Port

•

24 mA TTL Bus Drive Capability

•

Software Programmable Power Management

•

16-Bit Address Decode Support

•

CS4231/CS4248 Register Compatible

General Description
The CS4232 is a single chip multimedia audio system
controller and codec that provides compatibility with
ISA Plug and Play, the Microsoft Windows Sound System, and will run software written to the Sound Blaster
and Sound Blaster Pro interfaces. The CS4232 integrates an advanced industry-standard Delta-Sigma
high-percodec with extended signal processing in
formance mixed-signal design. The CS4232 also
contains expansive mixing capabilities, an MPU-401
UART, joystick logic, and interfaces for a music synthesizer and a CD-ROM.

a:

r---~r=~~;;~~~~~~~~~~4r~--~::==::====:JLMIC
I+-l=~-----MUler-o
A<1:0>
FIFOs

IRQ

io------¢

Linear
11·law
A·law

LLiNE

i o - - - - - - ¢ RLiNE
Mux

io--..,-----¢ LAUXl
Jo--.-f-----¢ RAUXl

DBDIR
DBEN

i5S
RD

WR

Parallel
Bus
Interface

DIG

ATTN

'---------'--~ .... :}_--j-----4-~

FIFOs

LOUT

Linear
wlaw
A·law

'l--I---+------'\l ROUT

DGNDl

DGND2

DGND3I4I718

XTALll

XTAL10

XTAL21

XTAL20

'-----~;;;;-"]o-------¢

LAUX2

io--~

RAUX2

AGNDl

AGND2

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760

(512) 445 7222 Fax: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

NOV '93
DS106PP3
3-29

........
.
.. ....,

~

•

I CS8905C I

~

. . __ Wi . . ..

~

~~

Semiconductor Corporation

GS Format Compliant Musical Effects Processor
Features

General Description

• Upgrades the CS9233 Wavetable
Syntheiszer with Effects
• Reverb, Chorus, Flange, etc.
• Improves subjective quality of music
• Full Roland GS format compliant
• 2x performance of original CS890S
• Stereo 16-bit digital audio output
returned to CS9233 for mixing
• On-chip Algorithm and Parameter
RAM, permits field upgrades
• 68 pin PLCC or 80-pin TQFP packages

The CS8905C is a high performance programmable
signal processor, specially designed as a digital effects
processing engine for music and sound generation applications. With the appropriate firmware, full General
MIDI (GM) and General Synthesis (GS) compliant musical effects processing is possible. The Roland GS
format has become the defacto world-wide standard for
controlling effects processing in a MIDI environment.
With effects, the subjective quality of music improves
greatly. The CS8905C features 19-bit internal data
paths, a 19-bit two's complement adder, a 12 x 12
two's complement multiplier, two 24-bit accumulators
and a 32-bit output shift register, operating at a clock
frequency of 64MHz. Complete refernce designs together with the CS9233 Integrated Wavetable
Synthesizer are available.

ALG r - - -

slot

GNO

VCC

RESET

ALGZ
FSH
SYNC
WAD·
WA19

WOO·
WD11

wcs
WOE

WWE

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 4622723

00·
07

AO·
A2

CS
RO

INT

X1 CKOUT
X2

CLBO OABO WSBO

WR

Copyright@ Crystal Semiconductor Corporation 1995
(All Rights Reserved)

FEB '95
DS178PP1
3-30

.. ... .
.......,.......
~~

~.",~.

~~

CS9233

.."

Semiconductor Corporation

Integrated Wavetable Music Synthesizer
Features

General Description

• Integrated synthesizer combines a
RISC-based DSP and a flexible CISC
micro-controller on a single chip

The CS9233 is a highly integrated music synthesizer
circuit designed for PC multimedia, musical instrument,
Karaoke, arcade game and set-top applications. Interface logic is included on-chip for glueless connections
to external memory, DAC circuitry and an optional effects processor.

• 32-note polyphony, 32-part
multi-timbral at 31.25kHz output rate
• Dos Games compatible synthesis

When the CS9233 is combined with PCM sample data
and associated firmware, full General MIDI (GM), Roland General Synthesis (GS), Microsoft Windows, and
MPC level 2 compliancy is acheived (including recommendations for enhanced multi-timbral synthesizers).

• 18-bit audio output directly supports
the 96 dB CS4331 Stereo DAC
• Glueless interface to external
ROM/DRAM for PCM samples
• Direct support for the optional CS8905
Programmable Effects Processor

In addition to standard serial MIDI I/O, a parallel ISAbus interface has been provided, permitting emulation
of the common register sets (e.g. MPU-401 UART
mode) needed for DOS games compatibility.

• Independent control of reverb and
chorus send levels for each voice

For more information contact
our sales re resentative Cha ter 7

...!:::::-+

MIDI IN
MI DIOUT
PO

INTERNAL
WAVEFORM
ROM

CONFIG REG
AO·A18
D(}'D7

f--AD f - - R
-OMOE
f--WR f - - EXTIO
PAO·PA2
POO·PD7
PWR

l'RD
PCSO
PCS1
IROO
IR01
LFT

ADDRESS
& DATA
DE·MUX

r------

---

-

~

~
~

'---

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

WOE
RAS
CAS

iJROE

32 MHz
64 MHz

PLL

16MHz
OSC.

mliJl
·'I@tl;liM""·

ORWE

~

f-16 MHz
Xtal

ENHANCED
CS9203
MUSIC
SYNTHESIZER
CORE

8·BIT
f-MICRO·
CONTROLLER

PARALLEL
HOST
INTERFACE
&
FIFO

,------

GENERAL

WAO·WA22
WDO·WD11

8 MHz
CS8905
EFFECTS PROCESSOR
INTERFACE

I

r§
MIXER

DAAD
DAMD
DACLK
DABD
DAFD
CLBD
WSBD

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JAN '95
DS167PP2
3-31

-=--

~ •.

...........
...,....,..,
.....
... .
'-'

~.

'-' '-'

CRD9233-1

."

Semiconductor Corporation

Wavetable Synthesizer wi 16-bit Audio
Features

General Description

• General MIDI compliant, GS compatible
(totals 343: instruments; variations;
drum sets and special effects sounds)
DRAM support for down-Ioadable fonts
• AdLib™ , SoundBlaster Pro™,
Windows Sound System™, MT-32 and
Roland Sound Canvas™ compatible.
MPC2 compliant, Windows '95 ready
• Extensive feature list:
Joystick/MIDI Interface
PC Speaker liD
Line/Headphone Driver
Microphone Preamp
Phantom Power Support
CDROM:IDE, Panasonic, Sony, Mitsumi

The CRD9233-1 Reference Design features outstanding sound-quality, high-compatibility and low-cost. The
reference design integrates a fully General MIDI (GM)
compliant, General Synthesis (GS) format compatible
wavetable music synthesizer with an MPC2 compliant,
Ad Lib, MT-32, Sound Blaster Pro and Windows Sound
System compatible CD-quality audio design.
The board is a half size ISA-bus PC adapter, based on
the CS9233 Integrated Wavetable and Algorithmic
Music Synthesizer, the CS4112 CrystalClear™
Wavetable 8Mbit PCM sample ROM, the CS4331 18bit Delta-Sigma DAC, and the CS4232 Plug-and-Play
Games Compatible Multimedia Audio Sub-system.
The manufacturing kit includes: schematics; board layouts; bill of materials; user's manual; softWare technical
manual; DOS utility software; Windows 3.1 driver object code (Win '95, NT & OS/2 in development);
volume & mixing control applets; recorder/player applet, synthesizer control applet; MIDI drivers; etc.

JOYSTICK
&

MIDIIJO

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 4622723

Copyright © Crystal Semiconductor Corporation 1995
(All Rights ReseIVed)

FEB. '95
DS167RD1B1

3-32

.
. ............
....
.
...

ICRD9233-2 I

~

-'

."..,

~~

.."

Semiconductor Corporation

GSIGM Music Synthesizer Daughtercard
• Professional quality General MIDI
music synthesis for the Multimedia PC
• Low-cost im~lementations with
WaveBlaster M compatible connector
• 32-note polyphony, 16-part multitimbral, 31.25 kHz output sample rate
• Supports Roland GS bank select and
GS envelope and filter controls

General Description
The CRD9233-2 is a low-cost wavetable synthesizer
daughtercards based on the CS9233 Integrated
Wavetable Synthesizer IC. This General MIDI synthesizer is implemented as a daughter card subsystem for
a Personal Computer audio adapter (sound card). The
host interface connector and pin-out is compatible with
the Creative Labs Sound Blaster 16™ and Wave Blaster™ products. The CRD9233-2 plugs directly onto a
host sound card, such as the Sound Blaster 16; Sound
Galaxy NX Pro 16, AudioWave Platinum 16, or the
CRD4231 reference design, to provide professional
quality MIDI music synthesis in the PC environment.
The exceptional sound quality of this design makes it
an ideal choice for business multimedia, education, entertainment, computer games, or music composition
applications.

• 343 quality instrument sounds, w GS
special effects and drum kits
• Complete manufacturing kits available

GENERAL

mlill

Mllij'iJl1M'II-

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 4622723

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

FEB '95
CRD177PP2
3-33

. '

~

.. ... .
. .. ......
~~

~

~~~.

.."
."..,

I DRIVERS I

."

Semiconductor Corporation .

CS4231A and CS4232 Device Drivers
Features

General Description

• Support wave audio capture, playback
under Windows 3.1 & NT

• Highly optimized code for maximum
throughput, minimum CPU utilization

• Input & Output volume/mixing control

• Support ADPCM compression &
decompression

• Full Duplex audio capture & playback

• Complete with installation routines,
documentation, etc.

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

Crystal offers complete wave driver support for
the Microsoft Windows 3.1 & NT environments.
CS4231A and CS4232 drivers support full duplex
operation -- i.e. simultaneous capture and
playback. Full duplex permits voice recognition to
control multimedia playback. Control panel
applets are provided supporting all features of
the Crystal codec devices. Functions include: 1)
Input control panel used to select audio source
and individually set the gain level, turn dither
on/off, and visually monitor recording levels with
a VU meter; 2) Output control panel used to
control volume, mixer levels and loopback
monitoring; 3) Recorder applet used to capture
and playback .WAV files, at various sample
frequencies, with compression &
de-compression (ADPCM, ULaw & ALaw). The
recorder is an OLE server.
All source code was developed in-house. Object
code is provided without licensing fees directly
by Crystal. Sample copies are available.

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JAN '95
DS132PP1
3-34

...,.,.......
...,....,......

I DIAGNOSTICS I

~~

~~

~

Semiconductor Corporation

Multimedia Audio Codec Diagnostic Software
Features

General Description

• Development and manufacturing test
support for the CS4248, CS4231A, &
CS4232

• Control over every feature & function automated board test features

• Measure Codec performance without
need of an external signal source

• Record and playback. WAV files in the
DOS environment

• Real-time FFT, time and frequencyresponse plots

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

The diagnostics program for the Crystal codecs assists in every phase of PC audio sUb-system design.
From initial board bring-up and functional testing to factory test and field service, the diagnostics provide
in-depth information to the engineer regarding audio
performance and function.
Detailed reporting capabilities aid in both burn-in and
board debug. The diagnostics support communication
through input and output files, as well as DOS exit
codes, allowing it to be spawned by another program
and return meaningful results. A system-level diagnosticslfactory test system could thus use the program
while retaining its' own user interface routines.
The diagnostics run under DOS, and are controlled by
a command line interface optimized for minimum keystrokes. Sample 'C' source code is available detailing
how to call the routines from inside a host program.

All source code was developed in-house by Crystal.
Object code is provided to OEMs without charge.
Sample copies are available.

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JAN '95
DS131PP1
3-35

....,~
~~.

.....
.....
....
.............
~

~~~.

ICWDRGNTT I

~

Semiconductor Corporation

Talk-7 To Voice Recognition from Dragon Systems
Features

General Description
Talk~To

• World's foremost voice recognition

• Supports popular Windows apps.

• Hands free command & control in the
Windows 3.1 environment

• Reduces typing for data entry

• Speaker independent - also supports
regional dialects through training

is a powerful and flexible voice recognition
package for the Microsoft Windows 3.1 environment.
Voice recognition enhances productivity by allowing users to enter simple voice commands, instead of
complicated keystrokes or multiple mouse movements,
to choose menu and control options. Voice recognition
redefines the human/computer interface, making it truly
intuitive. Talk~To is highly speaker independent, yet
may be quickly trained to support an individual's
speaking style, thus handling regional or foreign accents.
Crystal Semiconductor has a strategiC relationship with
Dragon Systems to allow OEMs to integrate voice recognition capabilities into their products. Crystal licenses
the products directly to OEMs.
Sample copies are available free of charge; license
fees for production are volume dependent.

• Supports 64 active commands; context
sensitive for unlimited recognition

Product Preview
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

document contains information for a new product. Crystal
IThis
Semiconductor reserves the right to modify this product without notice.
Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

NOV. '93
DS130PP1
3-36

.. .. ......
..............
.-

ICWMNLG I

~~~

~~-

Semiconductor Corporation

First Byte's Monologue for Windows
Features

General Description

• Monologue Text-To-Speech synthesis
software from First Byte.

• Industry leading text-to-speech

• Allows Windows applications to speak

• Permits efficient proof-reading of text
and numerical data

Monologue increases productivity in the business environment, allowing users to add speech capabilities to
any Windows (or DOS) application. Any pronounceable
combination of letters and numbers will be spoken
clearly. No voice recording or speech training is necessary. Customizable speech parameters permit control
of volume, pitch and speed. An exception dictionary al_
lows the user to save preffered pronounciations o f "
words and abbreviations.
Crystal Semiconductor has a strategic relationship with
First Byte to allow OEMs to integrate speech capabilities into their products. Crystal licenses the products
directly to OEMs.
Sample copies are available free of charge; license
fees for production are volume dependent.

• Multilingual: French, German, Spanish
and American available now; Italian,
British and Japanese in development

• Transfer data through clipboard or
direct DLUDDE link

Monologue

16-bit
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

NOV. '93
OS133PP1
3-37

CWMNLG

• Notes.

AN31REV2

3-38

-_..__.._-_.
_.............
...-

DATA ACQUISITION DATA BOOK CONTENTS

GENERAL INFORMATION

II

DATA ACQUISITION
General Purpose
Industrial Measurement
Seismic
High Speed

II

AUDIO PRODUCTS
Consumer/Professional
Broadcast
Multimedia
COMMUNICATIONS PRODUCTS
Infrared Transceiver
Echo Cancellers
Communications Codecs
EthernetlCheapernet
Telecom

4

III

APPLICATION NOTES

a

APPENDICES
Product Category Levels
Reliability Calculation Methods
Package Mechanical Drawings
Standard Military Drawings

II

SALES OFFICES

4-1

-____-__.

.. .....
. --.. .
....

COMMUNICATIONS PRODUCTS

INFRARED TRANSCEIVER

CS6453 Alternate Voice/data Codec

CS8130 IrDA Transceiver

The CS6453 supports high-performance modems, and
provides a voiceband interface between a DSP and a
direct access arrangement.

The CS8130 Multi-Standard Infrared Transceiver adds
an IR port to a standard UART, and implements the
IrDA (Infrared Data Association) physical-layer. Other
standards supported are lIP-SIR, ASK and TV remote.
The computer data port is standard UART TxD and
RxD compatible, and operates from 1200 to 115200
baud. The CS8130 uses an external PIN diode and
transmit LED.

ECHO CANCELLERS
CS6400 Echo Cancelling Codec
The CS6400 is a low-cost voiceband echo cancellation
product with integrated codec and program ROM. The
CS6400 which can be used in full-duplex speakerphones, cellular phones, base stations, personal digital
assistants, video-teleconferencing and long-distance
telephone lines. This circuit contains an embedded, lowcost, application-specific DSP, and can cancel up to 64
ms of acoustic or network echo.
CS6401 Programmable Echo Canceller
The CS6401 is a general-purpose voiceband echo cancellation product. This circuit contains an embedded,
low-cost, application-specific DSP, and can cancel up to
64 ms of acoustic or network echo. The program code
is loaded from an external ROM, allowing Crystal to
tailor functionality for specific applications.

COMMUNICATION CODECS
Crystal Semiconductor offers a broad variety of technology for processing voiceband and radio baseband signals. The CS645x series of products are representative
of Crystal's ability to apply its delta-sigma converter
technology to specific communication applications.
Crystal will develop custom codec circuits for high-volume applications.
CS6450 I&Q Baseband Codec for IS-54
The CS6450 supports CDPD and TDMA cellular
phones, and provides a baseband interface between a
DSP and a radio module.

4-2

ETHERNET/CHEAPERNET
CS83C92 Ethernet Transceiver
Crystal is the first company to bring the benefits of lowpower CMOS technology to EthernetlCheapernet transceivers. The CS83C92C uses up to 40 percent less
power than the DP8392A and DP8392B. This translates into increased reliability and compatibility with
surface-mount technology. The CS83C92C is the first
Ethernet transceiver that is fully compliant with
ISOIIEEE 802.3
CS8900 Ethernet Controller
The CS8900 is a low-cost Ethernet LAN Controller optimized for ISA PC motherboards. Its highly-integrated
design results in the industry's smallest~footprint solution. The small footprint results from the 14mm by
14mm 100-pin TQFP package, and through the elimination of external components. The CS8900 includes onchip RAM, lOBASE-T transmit and receive filters, and
a no-glue ISA-Bus interface with 24 rnA drivers. In addition to saving cost and board space, the internal filters
simplify the task of achieving FCC Part 15 Class B certification.
Crystal provides a complete set of certified CS8900
drivers for all major operating systems and network operating systems. Motherboard applications are further
supported by the following leadership performance-oriented features: advanced power management, full-duplex operation, Stream Transfer™, and DMA-antoswitch. The CS8900's patented PacketPageTM architecture automatically adapts to changing network traffic
patterns and available. system resources. The result is
increased system efficiency and minimized CPU overhead.

....
.-..--._.-.
_
___-_
...
TELECOM
T1 Framer
Crystal Semiconductor's CS2180B Tl Framer is a perfect companion to our T1 line interface ICs. This device
handles encoding and decoding of all Tl frame formats
(SF, SLC-96 and TlDM and ESF). Serial interface and
control registers make it simple to configure from a microprocessor, including per-channel control options.
Packages available include 40-pin DIP or 44-lead
PLCC.
While maintaining 100% compatibility, Crystal has improved on industry-standard 2180 designs:
• Support of SLC-96 & TlDM formats
• Compliance with 1R-TSY-000191 AIS detection
criteria
• Compliance with Bellcore Loss-of-Carrier detection
criteria
• Buffered serial data interface, eliminating need for
sm to be valid for both edges of SCLK
• Industrial temperature operating range
Crystal also manufactures a CS2180A framer.

Tl, El and ISDN Primary Rate Line Interface
Circuits
Crystal Semiconductor offers a broad family of lowpower CMOS PCM line interface circuits, with each device optimized for a unique. system application. Since
introducing the industry's first Tl (1.544 MHz) and E1
(2.048 MHz) line interface circuits (the CS61534 and
CS61544), Crystal has shipped more CMOS PCM line
interface ICs than any other vendor worldwide. Crystal
Semiconductor's leadership continues with the best-inclass transmitter return loss, short-circuit current limiting, pulse shapes, jitter attenuation, jitter tolerance and
low power consumption. The CS61304A, CS61305A,
and CS61577 are upgraded devices for existing designs.
The CS61535A, CS61574A, CS61575 and CS61584 are
recommended for use in new designs.

COMMUNICATIONS PRODUCTS
CS61535A: Enhanced transmit-side jitter attenuator
supports SONET VT1.5 and VT2, and other high speed
transmission systems such as digital microwave radio
and M13 multiplexers.
CS61574A: Receive-side jitter attenuation supports line
cards in synchronous switching systems (such as central
offices, PBXs and 0/1 digital cross connects).
CS61575: Receive-side jitter attenuation with extended
FIFO length supports loop-timing in AT&T 62411
compatible customer-premises equipment.
CS61584: The industry's first 3.3V or 5V, dual Line
Interface Unit. Intended for high-density line cards.
Fully software configurable between Tl and El rates
with no changes required to external components.
CS61304A and CS61305A: These ICs' low-impedance
transmit drivers allow the ICs to be used in boards currently employing the LXT304A or LXT305A. Advantages over the LXT304/5A include lower power consumption, optional internal B8ZS/AMIlHDB3 coder and
receive AIS detection.
CS61577: A 100% drop-in replacement for the
CS61574 which uses the same transformers. Enhancements include transmitter short-circuit current limiting,
driver immunity to reflected pulses, lower power consumption, optional B8ZS/AMIIHDB3 coder, and software selection between 750 and 1200 El output options. The CS61577 also replaces the LXT300Z

Quartz Crystals
To complement our family of TlIEI Line Interface circuits, Crystal Semiconductor supplies pullable quartz
crystals. The CXT6176 (for Tl applications) and the
CXT8192 (for E1 applications) are designed for 100%
compatibility with Crystal's line interface units and jitter attenuators.

4-3

_..........
.
......--_
...
.
.....

.."

COMMUNICATIONS PRODUCT~

~..,

Table 1: Line Interface Units

Product

CS61535A

CS61574A

CS61575

CS61584

Number of
Channels

1

1

1

2

Power Supply

5V

5V

5V

3.3Vof5V

Transmitter Matches
Impedance of Line?

yes

yes

yes

yes

Transmitter
Short-circuit Current
Limiting?

yes

yes

yes

yes

Location of
Jitter Attenuator

Transmit

Receive

Receive

Programmable
(xmit, rcvr, none)

Jitter Attenuator
FIFO length

32 bits

32 bits

192 bits

64 bits

Control Modes

Serial & hardware

Serial & hardware

Serial & hardware

Serial, parallel &
hardware

100% software
switchable between
Tl &El

-

-

-

yes

Optional B8ZS,
HDB3, AMI Coder

yes

yes

yes

yes

Package
JTAG

4-4

28-pin PDIP & PLCC 28-pin PDIP & PLCC 28-pin PDIP & PLCC

-

-

-

64-pin TQFP &
68-pinPLCC
yes

_..........
.-..............
-..._-..
~

COMMUNICATIONS PRODUCTS

CONTENTS
INFRARED TRANSCEIVER
- CS8130 Infrared Transceiver

4-6

ECHO CANCELLERS
- CS6400 Echo Cancelling Codec
- CS6401 Programmable Echo Canceller
- CWECAXB Executable Code for the CS6401
- CDB6401 Evaluation Board

4-7
4-8
4-9
4-10

COMMUNICATION CODECS
- CS6450 TDMA Cellular Baseband CODEC
- CS6453 Modem Analog Front-End

4-11
4-12

ETHERNET/CHEAPERNET
- CS83C92A1C Ethernet Transceiver
- CS8900 Ethernet Controller .

4-13
4-14

TELECOM
-

CS2180AIB TI Framerffransceiver
CS61304A TIIEI Line Interface
CS61305A TIIEI Line Interface
CS61535/35A TIIEI Line Interface
CS61574A175 TIIEI Line Interface
CS61577 TIIEI Line Interface .
CS61584 TIIEI Line Interface .
CXT6176/8192 Pullable Quartz Crystals

4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22

See the 1994 Crystal Communication Data Book
for the complete data sheets on the above products

4-5

..

"""........
..........
..,
.....
~.

CS8130·

.,,~

Semiconductor Corporation

I

Multi-Standard Infrared Transceiver
Features

General Description

• Adds IR port to standard UART
• IrDA, HPSIR, ASK (CW) & TV remote
compatible
• 1200bps to 11Skbps data rate
• Programmable Tx LED power
• Programmable Rx threshold level

The CS8130 is an infrared transceiver integrated circuit. The receive channel includes on-chip high gain
PIN diode amplifier, IrDA, HPSIR, ASK & TV remote
compatible decoder, and data pulse stretcher. The
transmit path includes IrDA, HPSIR, ASK & TV remote
compatible encoder, and LED driver. The computer
data portis standard UART TxD and RxD compatible,
and operates from 1200 to 115200 baud.
External PIN diode and transmit LED are required. A
control mode is provided to allow easy UART programming of different modes.

• Power down modes
The CS8130 operates from power supplies of +2.7V to
+5.5V.

• Direct, no modulation, mode
• Tiny Sx7mm 20 pin SSOP package

For more information see the
1994 Communication Data Book

• +2.7V to +S.SV supply

+Supply

+Supply

VA+
12

B

11
13

RESET
RXD
RxD

16

FORMIBSY

14

TXD

15

ole

10

PWRDN

CTS

DTR

LED2C

9

XTALIN XTALOUT

STANDARD
UART
TxD

20
CLKFR

DGND

o

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JUN '94
DS134PP2
4-6

..... ..........
~~

~..,~.

."..,

~~

·CS6400

~

Semiconductor Corporation

Echo-Cancelling Codec
Features

General Description
The CS6400 is an application-specific digital signal
processor optimized for acoustic echo and noise cancellation applications.
A high-quality codec is
integrated with the processor to provide a complete,
low-cost echo-cancellation solution.

• Applicable in:
- Digital-Cellular Hands-Free Phones
- Analog-Cellular Hands-Free Phones
- Office Speaker Phones
- Desktop & Video Teleconferencing
- Network/Base Stations

The CS6400 is a fully independent processor that requires no signal processing support to implement its
cancellation functions.
Volume control, mute, and
sleep functions are also provided.

• Echo Cancellation
- Up to 60 dB ERLE
- 512 Tap (64 ms at 8 kHz Fs)
- Split Mode For Two ECs
- Cascadable For Longer Response

The on-chip AID and DIA converters employ over-sampling technology, which eliminates the need for
complex extemal anti-aliasing and reconstruction filters,
further reducing system cost.
The CS6400 has a zero glue-logic serial interface that
is compatible with most DSPs. Clock and sync lines
control the transfer of serial data via the separate serial
data-in and data-out pins. Both 1S-bit audio data and
controVstatus information may be multiplexed on this
serial channel usin a steerin bit.

• Zero-Glue Serial Data/Control Interface
• On-Chip Codec
- < 1% THD, 8Q Load On Output
- > 70 dB S/(N+D) on Input
- 0-3600 Hz Bandwidth at 8 kHz Fs
- 0-7200 Hz Bandwidth at 16 kHz Fs

DVDDO-+1

For more information see the
1994 Communication Data Book

TMODEO

CMASTER
CONFIGl
CONFIG2
CONFIG3
GPINO
GPIN1
GPIN2
RATE_SEl
SDI_A
SDI_B
SFRAME
SMASTER
SSENSE
SSYNC
UALAW
SClK
SDO_1
SDO_2
GPOUTO
GPOUT1
SYNCOUT

TMODE1

AVDD

Test
RESET

DSP

Analog I/O

- - - - - - - - - - - - - -

PVDD
SPKROUTP
SPKROUTN
PGNDO
PGND1

MICIN

- - - - - - - - - - - - - - -

VCM

Pll + Clock Manager

DGNDO®l

VREF

ClK_SEl ClKIN ClKOUT SCLICRATEO SClK..RATEl AGNDOCB>l

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581

JUNE '94
Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

DS80PP1
4-7

. '

~'

...._....
.
.........
.
...
~

I CS6401 I

~~~

~~

~

Semiconductor Corporation

Programmable Echo Canceller
Features

General Description

• For All Echo Canceller Applications
- Digital Cellular Network Equipment
- Analog Cellular Hands Free
- Digital Cellular Hands Free
- Office Speaker Phones
- Desktop Teleconferencing
- Long Distance Network Equipment

The CS6401 is a digital signal processor optimized for
acoustic and/or network echo cancellation algorithms.
The CS6401 implements all the adaptive filtering and
control algorithms needed for high quality echo cancellation for a variety of applications. Crystal has
developed the echo cancellation algorithms, and provides the DSP object code with the evaluation board.
Custom algorithm development services are available
from Crystal.
The CS6401 contains four main blocks:
• 16 MIPS, 16-Bit Programmable DSP
• 512-tap Adaptive FIR Filter Hardware
Accelerator
• Data 1-0 Serial Interface
• Boot/Control Interface

• Echo Cancellation
- 8 kHz Sampling Rate
- 512 tap (64 ms)
- Split Mode for Two ECs
(total taps = 512)

For more information see the
1994 Communication Data Book
VOO VSS

t t
6

B17-B10

BSEL

8011-B01

800

~

RESET

XTALI

+7

h

I

9

1

XTALO

CLKO

tlO

_t12

114 i 1 5 p

l

J

Oscillator

!
1

J

SSI1
59
58
6C1.

BooV

16-Blt

Control

OSP

61

Adaptive

Serial

Filter
Co-Processor

Interface

53
50

54
55

~.

~ 18~21

BIE1

Test

!

1

~

~

TESTI TESTOTESTM TCLKEN

BIE2

BOE

Ijll~
16

15

SMOOE1 SMOOEO

164
SCLKM

1
SYNCM

-

~

-

:S001
: SSI1

, SYNC1
, SYNC01

-

-- --

- -

, SOlN2
,S002

, SSI2

,SYNC2
: SYNC02
SCLK

]2
SYNCP

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 Fax: (512) 445-7581

--

-

: SOl1

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAY '94
DS98PP1

4-8

.. .......

r~··""~·

CWECAXB

..,~

~.~

~

Semiconductor Corporation

I

CS6401 Echo-Canceller Code
.,., ..... .0.

FEATURES

OVERVIEW
The CWECAXB version of application code for the
CS6401 Programmable Echo-Canceller is optimized for
acoustic echo-cancellation applications in noisy environments.

e 30dB of ERLE
e Input high pass filters (HPF)
(-3dB@300Hz) for noise reduction and
offset removal
e Pre-emphasis (PE) filter for
convergence speed and ERLE
improvement
e Half-duplex mode on startup and for
fall-back in adverse conditions
~.".

Version CWECAXB of the echo-canceller code contains advanced features:
• Support of hands-free audio at both ends of a communication link
• Support of a half-duplex fall-back mode
• Greater immunity to near-end noise
Version CWECAXB also provides the user some
measure of customizability with modifiable threshold
constants.

For more information see the
1994 Communication Data Book

eCustomizability

Suppressor
Half-Duplexer

Crystal Semiconductor Corporation
P.O,Box 17847, Austin, TX 78760
(512) 445-7222 Fax: (512) 445-7581

ec_error
,
normed_ec_beta '

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JUNE '94
DS157PP1
4-9

....
.
..,..
.....
•

~
~~.,'
IIIW . . . . . . ..

I·CDB6401 I

~~

Semiconductor Corporation

CS6401 Evaluation Board
Features

General Description
The CDB6401 allows an end-user to quickly integrate
the CS6401 echo-canceller into a system and evaluate
its performance. The board comes with a microcontroller and software to enable flexible setup and
evaluation. Evaluation requires a +5V power supply
and a Windows-capable personal computer with an
available RS232 serial port. Connections· for analog
audio sources are provided on the board.

• On Board Microcontroller
• RS232 Serial Communications with
Host PC
• High Quality Stereo Codec

Also included is the CS4216 stereo audio codec which
performs the data acquisition for' the echo-canceller
and which has such features as programmable gain
and attenuation, clipping detectors, and a wide range
of selectable sample rates.

• Microphone Pre-amplifiers
• Line Input Buffers

For more information see the
1994 Communication Data Book

• Analog and Digital Patch Area
+5VA

AGND DGND

Analog
Patch
Area

+5VD

H

r---~--,

r--~----

Micro
Controller
RS232
FE IN LINE

RS232

Driverl
NE IN LINE

Receiver

Connector

Digital
Patch
Area

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 Fax: (512) 445-7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAY '94
DS98DB1
4-10

.....
.... ...
~

~~~.

• .."..,. .....
~~

CS6450

~

Semiconductor Corporation

TDMAIAMPS /&Q Baseband Codec
Features

General Description

• Transmit 1&0 Interface
Two D/A converters: 10-bit, 194.4 kHz
sample rate
• Receive 1&0 Interface
Two range-scaling AID converters:
18-bit resolution, 97.2 kHz sample rate,
1O-bit outputs
• Single +5V power supply; optional 3V digital
1-0 pins
• Three 8-bit auxiliary D/A converters
for control

The CS6450 is a monolithic 15 kHz bandwidth I&Q
baseband codec designed for use in AMPS and TDMA
applications. The baseband codec provides the interfaces between a digital baseband subsystem and an
analog radio subsystem. On the digital side, the codec
interfaces to a digital sub-system through a parallel
port. The codec includes 10-bit Delta-Sigma DAC's
and ADC's for the I and Q signals. Three low speed
8-bit D/A converters can be used to control, for example, for frequency and gain of the radio sub-system.
The baseband codec has efficient power management
features, including the ability to power down individual
transmit, receive and control channels.

For more information see the
1994 Communication Data Book

• Receive I & 0 offset error correction

'-""
~'"

!

RESET

soc

GS[O:2]

ClK
2
Rxl+
Rxl-

RJW

cs

RxQ+
RxQ·

ANAD[O:9]

Txl+
Txl-

NA[O:2]

2
TxQ+
TxQNSTRB
CDACl
CDAC2

CDAC3

Reference
2
REFOUT

VREFP

VREFN

VDDIO

DGND

VDD

VA

AGND

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 Fax: (512) 445-7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JUN '94
DS128PP1
4-11

.........
. ....,..,
... .
~

~~~.

~

~~

CS6453

~

Semiconductor Corporation

Modem and Audio Analog Front End
Features

General Description
The CS6453 is a high-resolution analog-to-digital and
digital-to-analog converter for V.fast, V.32bis, V.32 and
other high performance modems.

• Complete Voiceband DSP Front-End
24-Bit AID Converter
18-Bit DfA Converter

The CS6453 also supports telephone emulation. In
telephone emulation, the CS6453 and external DSP
collectively implement both modem and telephone set
capabilities. This allows an end-user to connect a
handset to the "modem" card, and alternatively use the
telephone connection for voice and data.

• Minimum 84 dB Dynamic Range and
80 dB Signal-to-Distortion (at full scale)
• Supports telephone emulation

The CS6453 has 5 kHz bandwidth for modem and
telephone applications, and 10kHz bandwidth for business audio applications. The business audio capability
allows the modem to playback and input audio files.

• Supports business audio
• On-chip speaker driver for modem
monitoring

The CS6453 also supports the digital speaker signal of
the PCMCIA interface standard. The modem can transfer the modem monitor signal via PCMCIA to the
system speaker.

• Supports PCMCIA digital speaker
signal

For more information see the
1994 Communication Data Book

• 3.0 to 5.5V power supply range

AFECLK
MIC+
MIC·
RX+
RX·

2

2
2

EAR+
EAR·

I
Receive
I
I
I
I

ANALOG
DELTA·SIGMA
MODULATOR

3rd order
IIR
FILTER

RXENA

;;! I

gt51

DSPKR

...J« -

SPKR+
SPKR-

(!)~I

RXDATA

LOCAL DIGITAL
LOOPBACK

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

~gl

SPKOFF

~ I
I DI~~~;Z~~~L

ST+
ST·

2nd ORDER

CAPACITOR
FILTERS

TX+
TX·

MODULATOR

-

I

RXSTR

I
I
I

TXDATA

I

TXENA

ZERO ORDER HOLD
& 2nd ORDER
IIR FILTER

I
I
I

TEST1

VD+ DGND RESET

TXSTR

I Transmit
TXOFF

TXV+

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581

TXGND

TESTO

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

SEP '94
DS110PP6
4·12

..
.. ...

............
~~

~

~..,~.

.,,~

CS83C92A
CS83C92C

~

Semiconductor Corporation

Coaxial Transceiver Interface
Features

General Description

• Implemented in High Voltage, Low
Power CMOS
• Compatible with National's DP8392A
• CS83C92C is Compliant With
ISOIIEEE 802.3 10BaseS (Ethernet)
and 10Base2 (Cheapernet)
• All Transceiver Functions Integrated
Except Signal and Power Isolation
• Squelch Circuitry Rejects Noise
• CD Heartbeat Externally Selectable
Allowing Operation with IEEE 802.3
Compatible Repeaters
• Receive & Transmit Mode Collision
Detection
• Standard 16-pin DIP Package & 28 pin
PLCC

The CS83C92 Ethemet Transceiver interfaces an Ethemet or Cheapemet Local Area Network (LAN) to a
LAN Adapter board, and may be located up to 50 meters from the station equipment. The Transceiver
operates with the Crystal LAN components CS8005
Ethemet Data Link Controller and the CS8023A Manchester Code Converter. The CS83C92A is fully
compatible with the DP8392A but the CS83C92A is
built in CMOS technology (hence the 83"C"92). The
CS83C92C is a higher performance grade which is
compliant with IEEE 802.3 specifications.
For Ethemet applications, the CS83C92 is mounted on
the COAX cable, and connects to the station equipment via an AUI cable. In a Cheapemet network, the
CS83C92 is usually mounted on the LAN adapter card
in the station equipment where it connects to the thin
COAX through a BNC connector.

For more information see the
1994 Communication Data Book

COAX

1k

TXO

LINE DRIVER
GND

'-----_ _-{

r--"-----f.t------1--+-----~TX+ TRANSMIT

L __~___~:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;t::==::====jTXVEE

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 Fax: (512) 445-7581

PAIR

DTEINTERFACE

Copyright © Crystal Semicondutor Corporation 1995
(All Rights Reserved)

OCT '93
DS79F3
4-13

.':

. ...
...,.,..
...,.. ......
..,..,

~~
.

ICS8900 I

~

~~

Semiconductor Corporation

Highly-Integrated ISA Ethernet Control/er
Features

Description

•

The CS8900 is a low-cost Ethemet LAN Controller optimized for Industry Standard Architecture (ISA) Personal Computers. Its highly-integrated design eliminates the need for costly extemal components required
by other Ethemet controllers. The CS8900 includes
on-chip RAM, 10BASE-T transmit and receive filters,
and a direct ISA-Bus interface with 24 mA Drivers.

•
•
•
•
•
•

•

•
•
•
•
•

Single-Chip IEEE 802.3 Ethemet Controller with
Direct ISA-Bus Interface
Efficient PacketPage™ Architecture Operates in 1/0
and Memory Space, and as DMA Slave
Full Duplex Operation
On-Chip RAM Buffers Transmit & Receive Frames
1OBASE-T Port with Analog Filters, Provides:
- Automatic Polarity Detection and Correction
AUI Port for 10BASE2, 10BASES and 10BASE-F
Programmable Transmit Features:
- Automatic Re-transmition on Collision
- Automatic Padding and CRC Generation
Programmable Receive Features:
- StreamTransfer™ for Reduced CPU Overhead
- Auto-Switch Between DMA and On-Chip Memory
- Early Interrupts for Frame Pre-Processing
- Automatic Rejection of Erroneous Packets
EEPROM Support for Jumpel1ess Configuration
Boot PROM Support for Diskless Systems
Boundary Scan and Loopback Test
LED Drivers for Link Status and LAN Activity
Standby and Suspend Sleep Modes

In addition to high integration, the CS8900 offers a
broad range of performance features and configuration
options. Its unique PacketPage architecture automatically adapts to changing network traffic pattems and
available system resources. The result is increased
system efficiency and minimized CPU overhead.
The CS8900 is available in a thin 100-pin TQFP package ideally suited for small form-factor, cost-sensitive
Ethemet applications, such as desktop and portable
motherboards and adapters. With the CS8900, system
engineers can design a complete Ethemet circuit that
occupies less than 1.S square inches (10 sq cm) of
board space.

For more information see the
1994 Communication Data Book
20 MHz
XTAL

I
r-'-_ _,CS8900 ISA Ethernet Controller

EEPROM
Control

I
S

A

10BASE-T
RX Filters &
Receiver

RAM

Encoder!
Decoder
&
PLL

ISA
Bus
Logic

Memory
Manager

802.3
MAC
Engine

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 Fax: (512) 445-7581

10BASE-T
TX Filters &
Transmitter

¢=trEl~T
==>~II~==>

AUI
Transmitter

==> ~II~ ==>--

AUI
Collision
AUI
Receiver

<== ~II~
<== ~II~

------<==-:

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

Attachment
Unit
Interface
(AUI)

October '94
DS1S0PP1

4-14

.. ........
.. ....
..............
~

."

CS2180B
CS2180A

..".."

Semiconductor Corporation

T1 Transceivers
Features

General Description
The CS2180A and CS2180B are monolithic CMOS devices which encode and decode T1 framing formats.
The devices support bit-seven and B8ZS zero suppression, and bit-robbed signaling. Clear channel mode can
be selected on a per channel basis.

• Monolithic T1 Framing Device
• Both Transceivers support SF(D4®)
and ESF framing formats
• CS2180B also supports SLC-96® and
T1 DM framing formats
• CS2180B has updated AIS and Carrier
Loss detection criteria

The serial interface has been enhanced to allow the
CS2180A and CS2180B to share a chip select signal
and register address space with the CS61535A,
CS61574A and CS61575 PCM Line Interface ICs.

Applications
• T1 Line Cards
• ISDN Primary Rate Line Cards
For more information see the
1994 Communication Data Book

• CS2180B is Pin Compatible with
CS2180A, DS2180A and DS2180
TFSYNC

TMSYNC

TSER

TABCO

TCLK
TLCLK

7

~~~=:~~~~-r----~----------------~1
6

TSIGSEL
TMO
TCHCLK
TSIGFR

TLiNK

TPOS

10

TNEG

INT

40

CS

20

Serial

SCLK

Registers

In1eriace

SOl

VOO
VSS
RST

SOO

TEST

SPS

RLOS
RBV

RSER

RCL

RABCO

RPOS

RLiNK

RNEG

RLCLK
RSIGFR
RSIGSEL
RCHCLK

24

RMSYNC

RFSYNC

Crystal Semiconductor Corporation
P.D. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581

RYEL

RFER
RCLK

RBL (CS2180B-IL only)

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAY'94
DS44F6

4-15

.. .........
............

I.CS61304A·,,1

~
~

~

Semiconductor Corporation

T1/E1 Line Interface
Features

General Description
The CS61304A combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61304A is a pin-compatible replacement for the
lXT304A.
The receiver uses a digital Delay-locked-loop which is
continuously calibrated from a crystal reference to provide excellent stability and jitter tolerance. The
CS61304A has a receiver jitter attenuator optimized for
T1 CPE applications subject to AT&T 62411 and E1
ISDN PRI applications. The transmitter features internal pulse shaping and a low impedance output stage
allowing the use of external resistors for transmitter impedance matching.

• Provides Analog Transmission Line
Interface for T1 and E1 Applications
• Provides Line Driver, Jitter Attenuator
and Clock Recovery Functions
• Fully Compliant with AT&T 62411
Stratum 4, Type II Jitter Requirements
• Low Power Consumption

Applications

• B8ZS/HDB3/AMI Encoder/Decoder

•

Primary Rate ISDN NetworklTermination Equipment

•

Channel Service Units

For more information see the
1994 Communication Data Book

• 50 rnA Transmitter Short-Circuit
Current Limiting
( ) = Pin Function in Host Mode
[ ] = Pin Function in Extended Hardware Mode

TCLK
TPOS
[TDATA]
TNEG
[TCODE]
RCLK
RPOS
[RDATA]
RNEG
[BPV]

-

~
2-.
,±...

.!-

I-

-t-

f-

-

R
E

I~

4-

B
A
C
K

r:-

~28

r--.

CONTROL

PULSE
SHAPER

+14

-

P
B
A

I

~"

/

SIGNAL
QUALITY
MONITOR

~
~

1

RLOOP XTALIN XTALOUT ACLKI
(CS)

Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581

27
LLOOP
(SCLK)

121
LOS

2d
RV+

13
16

19
20
17

~

DRIVER
MONITOR

L--

10

+15

>

LINE RECEIVER
CLOCK &
DATA
RECOVERY

'-~O

9

TV+

UN' ~'V'R

/'

I~

JITTER
.ATTENUATOR

TGND

123 ~24 125

I

1

LI

~L .P .-

(CLKE) (INn (SDI) (SDO)
TAOS LENO LEN1 LEN2

01_
lC

TI
EI

4-

~5

L

f- ~r

AMI,
B8ZS,
HDB3,
CODER

MODE

2d

~

r----D+

TTIP
TRING

RTIP

RRING
MTIP
[RCODE]
MRING
[PCS]
DPM
[AIS]

RGND

Copyright © Crystal Semicondutor Corporation 1995
(All Rights ReseN¢)

APR '94
DS156PP1

4-16

..............
... .

~
~~~.
~
~
."."

.,

CS61305A

Semiconductor Corporation

T1/E1 Line Interface
Features

General Description

'. Provides Analog Transmission Line
Interface for T1 and E1 Applications
• Provides Line Driver, Jitter Attenuator
and Clock Recovery Functions
• Transmit Side Jitter Attenuation
Starting at 6 Hz, with> 300 UI of Jitter
Tolerance
• B8ZS/HDB3/AMI Encoders/Decoders
• Compatible with SONET, M13 , CCITT
G.742, and Other Asynchronous Muxes
• 50 rnA Transmitter Short-Circuit
Current Limiting

The CS61305A combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61305A is a pin-compatible replacement for the
LXT305A in most applications.
The CS61305A provides a transmitter jitter attenuator
making it ideal for use in asynchronous multiplexor
systems with gapped transmit clocks. The transmitter
features internal pulse shaping and a low impedance
output stage allowing the use of external resistors for
transmitter impedance matching. The receiver uses a
digital Delay-Locked-Loop clock and data recovery circuit which is continuously calibrated from a crystal
reference to provide excellent stability and jitter tolerance.

Applications
•

InterfaCing network transmission equipment such as
SONET multiplexor and M13 to a DSX-1 cross connect.

•

Interfacing customer premises equipment to a CSU.

For more information see the
1994 Communication Data Book
[ ] = Pin Function in Extended Hardware Mode
() = Pin Function in Host Mode
XTALIN XTALOUT

9
TCLK
TPOS
[TDATA]
TNEG
[TCODE]
RCLK
RPOS
[RDATA)
RNEG
[BPV)

(CLKE) (INT) (SDI) (SDO)
MODE TAOS LEND LEN1 LEN2

JITTER
ATTENUATOR

~_--,,16'.oTRING

LINE DRIVER
LINE RECEIVER
,
19 RTIP

Bazs,
HDB3
CODER

TV+

CONTROL

AMI.

a

TGND

5

CLOCK &
DATA
RECOVERY

RRING
MTIP
[RCODE)
MRING
[PCS]
DPM

LOOP
BACK

L ___~~~~______---6!-~~_~_~===~J[AIS)
RLOOP LLOOP
(CS) (SCLK)

Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581

ACLKI LOS

RV+

Copyright © Crystal Semicondutor Corporation 1995
(All Rights ReseNed)

JUNE '94
DS157PP1
4-17

.......... .....

CS61535A
CS61535

~~
.".,,~
~
~
~~

..,

Semiconductor Corporation

T1/E1 Line Interface
Features

General Description

• Provides Analog PCM Line Interface
for T1 and E1 Applications

The CS61535A and CS61535 combine the complete
analog transmit and receive line interface for -T1 or E1
applications in a low power, 28-pin device operating
from a +5V supply. The CS61535A provides additional
features and higher performance than the CS61535.

• Provides Line Driver, and Data and
Clock Recovery Functions

Both devices feature a transmitter jitter attenuator making them ideal for use in asynchronous multipl'exor
systems with gapped transmit clocks. The CS61535A
provides a matched, constant impedance output stage
to insure signal quality on mismatched, poorly terminated lines.

• Transmit Side Jitter Attenuation
Starting at 6 Hz, with> 300 UI of Jitter
Tolerance

Both ICs use a digital Delay-Locked-Loop clock and
data recovery circuit which is continuously calibrated
from a crystal reference to provide excellent stability
and jitter tolerance.

• Low Power Consumption
(typically 175 mW)

Applications
• B8ZS/HDB3/AMI Encoders/Decoders

•

Interfacing network transmission eguiprnent such as
SONET multiplexor and M13 to a DSX-1 cross connect.
Interfacing customer premises equipment to a CSU.
Interfacing to E1 links.

• 14 dB of Transmitter Return Loss
•
•

• Compatible with SONET, M13 , CCITT
G.742, and Other Asynchronous
Muxes

[] =Pin Function in Extended Hardware Mode
() =Pin Function in Host Mode
XTALIN
TCLK ~
TPOS ~
[TDATA]
AMI,
TNEG
B8ZS,
[TCODE]
HDB3
RCLK ~
CODER

f.-o
f.-o

~
~

11

I
I

r-i.

RPOS
[RDATA]
RNEG
[BPV]

.

4-

~

~

19
i-

IiI
I
L

XTALOUT

For more information see the
1994 Communication Data Book

(CLKE) (INT) (SDI) (SDO)
MODE TAOS LEND LENl LEN2

Is

110

JITTER
ATTENUATOR

1 28

---0

CONTROL
---0

126

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581

I SHAPER
PULSE

CLOCK &
DATA
RECOVERY

I
127

124

TV+

114

--

1 15
13

"-

>16
/'

TTIP
TRING

LINE DRIVER
LINE RECEIVER

LOOP
BACK

RLOOP LLOOP
(CS) (SCLK)

T23

TGND

T25

1

SIGNAL
QUALITY
MONITOR

~2

ACLKI LOS

/

~

~~~

r-

~
DRIVER
MONITOR

~
[J1..

'tl

t2

RTIP
RRING
MTIP
[RCODE]
MRING
[PCS]
DPM
[AIS]

RV+ RGND

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

APR '94
DS40F1

4·18

..........
..............
..-.....

CS61574A
CS61575

~

~

Semiconductor Corporation

T1/E1 Line Interface
Features

General Description
The CS61574A and CS61575 combine the complete
analog transmit and receive line interface for T1 or E1
applications in a low power, 28-pin device operating
from a +5V supply. Both devices support processorbased or stand-alone operation and interface with
industry standard T1 and E1 framers.
The receiver uses a digital Delay-Locked-Loop which is
continuously calibrated from a crystal reference to provide excellent stability and jitter tolerance. The
CS61574A has a receiver jitter attenuator optimized for
minimum delay in switching and transmission applications, while the CS61575 attenuator is optimized for
CPE applications subject to AT&T 62411 requirements.
The transmitter features internal pulse shaping and a
matched, constant impedance output stage to insure
signal quality on mismatched, poorly terminated lines.

• Provides Analog Transmission Line
Interface for T1 and E1 Applications
• Provides Line Driver, Jitter Attenuator
and Clock Recovery Functions
• Fully Compliant with AT&T 62411
Stratum 4 Jitter Requirements
• Low Power Consumption
(typically 175 mW)

Applications
•

Interfacing Network Equipment such as DACS and
Channel Banks to a DSX-1 Cross Connect

•

Interfacing Customer Premises Equipment to a
CSU

•

Buildin Channel Service Units

• B8ZS/HDB3/AMI Encoder/Decoder
• 14 dB of Transmitter Return Loss

For more information see the
1994 Communication Data Book
( ) = Pin Function in Host Mode

[]=Pin Function in Extended Hardware Mode
2 .
TCLK ,..::....
TPOS
[TDATA]
TNEG
[TCODE]
RCLK
RPOS
[RDATA]
RNEG
[BPV]

2-.

-

f--+

R
E

---. ~I--

t'l-

EI
AMI,
B8ZS,
LI
HDB3,
CODER +--

~L

+-- P
B
A
C
K

~

?

~5

L

(CLKE) (INn (SDI) (SDO)
TAOS LENO LEN1 LEN2

~ 28

01___
lC

I~

TI

~

MODE

1---

CONTROL

123 ~24 125

I

4-

JITTER
ATTENUATOR

4-~

0

4-

P
B
A

.,14

PULSE
SHAPER

f------+

V

/

CLOCK &
DATA
RECOVERY

I

~~

SIGNAL
QUALITY
MONITOR

~
~
DRIVER
MONITOR

L--

9

10

1

RLOOP XTALIN XTALOUT ACLKI
(CS)

Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581

27
LLOOP
(SCLK)

121
LOS

.,15

>

LINE RECEIVER

I~

TV+

LINE ~'VER

1
4-

TGND

2d
RV+

2d

13
16

19

-

20
17

~

~

TTIP
TRING

RTIP

RRING
MTIP
[RCODE]
MRING
[PCS]
DPM
[AIS]

RGND

Copyright © Crystal Semicondutor Corporation 1995
(All Rights ReseNed)

JUN'94
DS154F1
4-19

_'

.
. ....,..,......
.
....,
~-

~

~~~

[ CS6t577

~~

Semiconductor Corporation

T1/E1 Line Interface
General Description

Features

The CS61577 is a drop-in replacement for the
CS61574, and combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61577 supports processor-based or standalone operation and interfaces with industry standard
T1 and E1 framers.
The receiver uses a digital Delay-locked-loop which is
continuously calibrated from a crystal reference to provide excellent stability and jitter tolerance. The receiver
includes a jitter attenuator optimized for minimum delay
in switching and transmission applications. The transmitter provides internal pulse shaping to insure
compliance with T1 and E1 pulse template specifications.

• Provides Analog Transmission Line
Interface for T1 and E1 Applications
• Drop-in Replacement for CS61574 with
the Following Enhancements:
- Lower Power Consumption
- Transmitter Short-Circuit
Current Limiting
- Greater Transmitter Immunity
to Line Reflections

Applications

- Software Selection Between 750 and
1200 E 1 Output Options

•

Interfacing Network Equipment such as DACS and
Channel Banks to a DSX-1 Cross Connect

•

Building Channel Service Units

- Internally Controlled E1 Pulse Width

For more information see the
1994 Communication Data Book

- B8ZS/HD.B3/AMI Encoder/Decoder

() =Pin Function in Host Mode
[]=Pin Function in Extended Hardware Mode
TCLK
TPOS
rrDATA]
TNEG
rrCODE]
RCLK
RPOS
[RDATA]
RNEG
[BPV]

f--+

~

'l-

L

AMI,
B8ZS,
HDB3,
CODER

lC

I~

TI
EI

~

CONTROL

JITTER

~ ATTENUATOR

4-

TV+

+14

+15
13

I

PULSE
SHAPER

r---- ~

LINE RECEIVER

/

CLOCK &
DATA
RECOVERY

P
B
A

I

~I"

SIGNAL
QUALITY
MONITOR

~
~
DRIVER
MONITOR

~

9

10

1

RLOOP XTALIN XTALOUT ACLKI
(CS)

Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581

TTIP
16

TRING

V

4-~ 0

~

~

123 ~24 125

TGND

LlNE~IVER

I~

.- gL ~
P
B
A
C
K

-

~28

I

LI

.-

~5

(CLKE) (INT) (SOl) (SDO)
TAOS LENO LEN1 LEN2

0_

r- ~r

2-.
~

-

R
E

~

MODE

27
LLOOP
(SCLI<)

121
LOS

211
RV+

22

1

19

RTIP

20

RRING

~

~
~

MTIP
[RCODE]
MRING
[PCS]
DPM
[AIS]

RGND

Copyright © Crystal SemiconQutor Corporation 1995
(All Rights Reserved)

MAR '94
DS155PP1
4-20

....
...........
.. ...
~

I CS61584

~~~.

~

..,~

~

Semiconductor Corporation

Dual Low Power T1/E1 Line Interface
Features

General Description

CS61584 is a universal line interface for T1/E1
• Provides Dual Analog PCM Line Interface The
applications, designed for high-volume cards where low
for short-haul, T1 ana E1 applications
power, high density and universal operation is required.
One board design can support all T11E1 modes. Only
the frequency of the reference clock input must change
as software selects between T1 and E1.

• 3.3 Volt and 5 Volt Versions
• Low Power Consumption
(typically 160 mW per Line Interface)
• Operating mode fully software configurable; same external components can be
used for all modes. No external quartz
crystal is required.
• User-customizable·pulse shapes
• Support of JTAG boundary scan

Serial Port
Parallel Port
Hardware Mode

The CS61584 is a low-power CMOS device available
in 3.3 Volt and 5 Volt versions.
Transmitted pulse shapes are software-customizable,
allowing non-standard line loads or protection circuits
to be supported. Control is via either a serial port, parallel port or individual control lines.

For more information see the
1994 Communication Data Book

cs

IPOL
PIS
INT
SCLK
SDO
SOl
SPOL
IPOL
piS
CS
INT RD(DS) ADO
ADI
A02
AD3
AD4
ADS
ADS
AD7 ALE(AS) WR(RIW) BTS
CLKE ATTENO ATTENI RLOOP LLOOPI LLOOP2 TAOSI TAOS2 CONOI CON02 CONI I CONI2 CON21 CON22 CON31 CON32

TTIPI

TCLKI
(TDATAI) TPOSI

TRINGI

(AISI) TNEGI
RCLKI
RTIPI
(RDATA I) RPOSI
RRINGI

(BPVI) RNEGI

TTIP2

TCLK2
(TDATAI) TPOS2

TRING2

(AISI) TNEG2
RCLK2
RTIP2
(RDATAI) RPOS2
RRING2

(BPVI) RNEG2

RESET
MODE

REFCLK

XTALOUT

IXCLK

Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581

TV+ TGND RV+ RGND DV+ DGND AV+ AGND BGREF POI PD2 LOSI LOS2
SAD4 SADS SADS SAD7
POI PD2 LOSI LOS2

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

Serial Port
Parallel Port

Hardware Mode

SEPT '94
DS114PP1
4-21

....... .....

CXT6176
CXT8192

~
~~~
.",~~
~
."

..,..,
Semiconductor Corporation

Pullable Quartz Crystals
Features

Description
Crystal Semiconductor's line interface and jitter attenuator IC's require unique performance specifi~tions for
the crystals. The CXT6176 and CXT8192 are built to
meet Crystal's specifications for T1 and PCM-30 applications respectively.

• Complements CS61534, CS61535,
GS61535A j CS61544, CS61574,
CS61574A, and CS61575 PCM Line
Interface integrated circuits and
CS61600 PCM Jitter Attenuator.

For more information see the
1994 Communication Data Book

0

CXT6176

,---------1

CXT8t92

r---------------,

I

L

CMOS OSCILLATOR CIRCUIT MODEL

I

C 100d

I
I
I

______________ J

Crystal Line Interface or Jitter Attenualor I.C.

Crystal Semiconductor Corporation
P.o. Box 17847, Austin, TX 78760
(512) 445-7222 FAX; (512) 445-7581

Copyright © Crystal Semicondutor Corporation 1995
(All Rights ReseNed)

SEP '92
DS39F2
4-22

_...__.. ......-.
..,_ ..,..,_.
..,~-

DATA ACQUISITION DATA BOOK CONTENTS

•

GENERAL INFORMATION

Ell

DATA ACQUISITION
General Purpose
Industrial Measurement
Seismic
High Speed
AUDIO PRODUCTS
Consumer/Professional
Broadcast
Multimedia

III

COMMUNICATIONS PRODUCTS
Infrared Transceiver
Echo Cancellers
Communications Codecs
EthernetlCheapernet
Telecom

II

APPLICATION NOTES

5

APPENDICES
Product Category Levels
Reliability Calculation Methods
Package Mechanical Drawings
Standard Military Drawings
SALES OFFICES

5-1

----------- -----------

APPLICATION NOTES

CONTENTS
AN18

Layout and Design Rules for Data Converters and Other Mixed Signal Devices

5-3

AN10

Delta-Sigma AID Conversion Technique Overview

5-7

NEW AN35

The CS5504 Family Characteristics

5-17

NEW AN36

CS5516 and CS5520: Overcoming Errors in Bridge Transducer Measurement

5-19

NEW AN31

A Collection of Bridge Transducer Digitizer Circuits

5-25

NEW AN32

CS5516 and CS5520: Answers to Application Questions

5-53

NEW AN28

Precision Temperature Measurement using RIDs (Resistance Temperature
Detectors) with the CS5516 and CS5520 Bridge Transducer AID Converters

5-67

NEW AN47

Infrared: A New Standard in Industry

5-71

NEW AN38

Using The Capture Evaluation System

5-73

NEW AN44

Using The CDBCAPTURE System With Embedded AID Converters

5-81

NEW AN45

CDB5504 Capture Interface

5-89

NEW AN46

CDB5509 Capture Interface

5-91

NEW AN37

Noise Histogram Analysis

5-93

NEW AN33

Clock Options for ND Converters

5-105

NEW AN30

Switched-Capacitor ND Converter Input Structures

5-109

Voltage References for the CS5012NCS5014/CS5016/CS5101NCS5102N
CS5126 Series of AID Converters

5-115

Buffer Amplifiers for the CS5012NCS5014/CS5016/CS5101NCS5102N
CS5126 Series of AID Converters

5-127

A Collection of Application Hints for the CS501X Series of AID Converters

5-151

AN4

AN6

AN8

Information in these application notes is believed to be accurate and reliable. However, Crystal Semiconductor
Corporation assumes no responsibility for the use of any circuits described. No representation is made that the
interconnection of these circuits will infringe on existing patent rights.

5-2

. ....,..,..........
~~

~

~~

.,~

~.
~

AN18

Semiconductor Corporation

Application Note
Layout and Design Rules for Data Converters
and Other Mixed Signal Devices
by
Ron Knapp & Steven Harris

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445 7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

FEB '95
AN18REV5
5-3

----------------------

Layout Design Rules

Here is a list of guidelines for optimum printed circuit board layout for Crystal ADC's, DAC's,
and codecs. Use these pages as a checklist during and after layout by checking the boxes
when each line item is OK. Remember, Crystal offers a free schematic and layout review
service. Try hard to use this service lKllim< building your first prototype board. Comments
or additional items are very welcome ..

D

1)

Partition the board with all analog components grouped together in one area and all
digital compone~ts in the other. Common power supply related components should be
centrally located.

D

2)

Have separate analog and digital ground planes on the same layer, with the digital
components over the digital ground plane, and the analog components, including the analog
power regulators, over the analog ground plane. The split between planes should be >1/8".

D

3)

Mixed signal components, including the data converters, should bridge the partition in the
ground plane with only analog pins in the analog area, and only digital pins in the digital
area. Rotating the data converter can often make this task easier. Look at the evaluation
board data sheet to see where the split should be located.
For our serial codecs, the device should be placed over the analog ground plane, positioned
next to the ground plane split. The digital pins should be next to the split, with the digital
traces crossing directly over into the digital region of the board. The analog ground pins
and digital ground pins should be connected with zero impedence (same ground plane). See
the CS4215 and CS4216, CDB4215 and CDB4216 data sheets for examples.

D

4)

Analog and digital ground planes should only be connected at one point (in most cases).
Have vias available in the board to allow alternative connection points.

D

5)

Regions between analog signal traces should be filled with copper, which should be
electrically attached to the analog ground plane. Regions between digital signal traces
should be filled with copper, which should be electrically attached to the digital ground plane.
These regions should D.Qt be left floating, which only make the interference worse. Using
ground plane fill has been shown to reduce digital to analog coupling by up to 30 dB.

D

6)

The analog to digital ground plane connection should be near to the power supply, or near
to the power supply connections to the board, or near to the data converter. In the case of
multiple converters, leave jumper options at each converter.

D

7)

Analog power and analog signal traces should be over the analog ground plane.

D
D

8)

Digital power and digital signal traces should be over the digital ground plane.

9)

Keep digital signal traces, especially the clock, as far away from analog input and voltage
reference pins as possible.

D

10) Bypassing and decoupling capacitors should be close to the IC pins, or positioned for the
shortest connection to pins with wide traces to reduce impedance (for example, between
pins 1 and 28 at the top end of the IC package in the case of the VREF decoupling capacitors
for the CS5326 family, the CS5336 family and the CS4328).

5-4

AN18REV5

----------------------

Layout Design Rules

D

11) If both large electrolytic and small ceramic capacitors are recommended, make the small
ceramic capacitor closest to the IC pins. For multi-layer pc boards, make the connections
to the converter and to the capacitors on the same layer (this avoids the additional
impedence of vias).

D

12) All filtering capacitors in the signal path should be NPOICOG dielectric. BXDGR
dielectric is OK for DC voltages where voltage coefficient is not a factor.

D

13) All resistors in the signal path or on the voltage reference should be metal film. Carbon
resistors are OK for DC voltages and the power supply path where voltage coefficient,
temperature coefficient or noise are not a factor. Avoid wire wound resistors and
potentiometers.

D

14) Avoid multiple crystal oscillators or asynchronous clocks. Best results are obtained when
all circuits are synchronous to the AID or DIA sampling clock.

D

IS) When using converters with DSP IC's, operate everything from one crystal using
dividers if necessary.

D

16) In systems requiring multiple crystals for selectable sampling frequencies, enable only one
at a time. Shut off all other oscillators by removing power. Make sure other oscillators
are off either with an active crowbar on V cc or ~ high impedance switch. Often
the leakage from a transistor or FET which is not completely off is sufficient for the
oscillator to produce a low level output frequency.

D

17) When using DC-DC switching regulators, synchronize the switching frequency to the AID
if possible. This applies to CMOS chopper amplifiers as well.

D

18) Avoid connecting the clock source oscillator to the converter sampling clock input through
analog multiplexers, PAL's, gate arrays, opto-couplers or circuits which can cause jitter.

D

19) Locate the crystal or oscillator close to the converter. Avoid overshoot and undershoot on
the master clock for the converter. This is particularly important for the CSS326 family,
where the master clock (CLKIN) goes directly into the analog modulator die.

D

20) Use buffers for digital signals directly to or from the converter to connectors which
go off the board.

D

21) In the case of piggy-back boards, or boards which plug into a slot adjacent to other
boards, consider the circuits which will be above or below the converter as sources
of interference. A mu-metal screen may be required.

D

22) For delta sigma converters, make sure that potential interfering clocks are not in
sensitive frequency regions. Sensitive regions are defined as ± passband either
side of multiples of the input sample rate. Two examples are : a) for a CSS336
operating at 48 kHz word rate, the frequencies to avoid are (N X 3.072MHz) ±24 kHz.
b) for a CSSSOI with a 4 MHz crystal, the frequencies to avoid are
(N X 16 kHz) ± 10 Hz. Frequencies which are synchronous to the input sample rate
will not cause problems, since they will be converted to dc, and calibrated out.

AN18REV5

5-5

-

,

i'

_-_....
.---.....

_

o

Layout Design Rules

• •_ - • • • 1IIIf'

23) For boards with more than 2 layers, do not overlap analog related and digital related
planes. Do not have a plane which crosses the split between the analog ground plane
region and the digital ground plane region.

D

24) For CS5326, CS5336 & CS5349 families, supply VD+ to the device via a separate
trace connected to where the +5V digital supply enters the board. Connect no other logic
to this trace. Alternatively, provide a 10 J.IH inductor in series with VD+, near to the ADC.

D

25) For boards with both AID converters and DIA converters, provide a means for testing each
function separately. Possible methods include providing a header to allow access to the
digital data paths, and allowing for easy attachment of a CS8402 and CS8412 AESIEBU
transmitter and receiver parts.

D

26) Terminate unused op-amps in dual and quad packs by grounding the + input and
connecting the - input to the output.

D

27) Digital control lines which must cross into the analog region should be as short as
possible and should be mostly static. For example, digital gain and analog mux control
lines.

D
D

28) The pins of DIP or SOIC packages should not have ground plane in between adjacent pins.

D

30) Do not surround the analog region with digital components. Do not surround the digital
region with the analog region

29) In systems using a delta-sigma converter, then avoid the use of clocks (particularly the serial
bit clock) at half the frequency of the input sample rate. If this frequency interferes with
the voltage reference, then tones can occur.

Schematic &Layout Review Service
Confirm Optimum
Schematic & Layout

5-6

AN18REV5

. ..,.,..,"'"......
... .
~~

~

~~~.

~

AN10

."

Semiconductor Corporation

Application Note
Delta Sigma AID Conversion Technique Overview
a. Analog Input Spectrum

L . -.- ._5kHz

2.5MHz
fs

f -3dB

b. Modulator Digital Output Spectrum
Shaped
Quantization

Spectrum Repeats at
Oversampling Rate

2.5MHz

5kHz

--

c. Digital Filter Response
No Noise Rejection
at Integer Multiples
of Oversampling Rate

2.5MHz

5kHz

d. Digital Filter Output Spectrum
(Before Decimation)
Spectrum of Interest

5kHz

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 TWX: 910-874-1352

2.5MHz

Copyright© Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JAN '89
AN10REV1
5-7

- ........_
--_.-.
_...............
-.
SECTION A
OVERVIEW: DELTA-SIGMA MODULATION

Although developed over two decades ago, deltasigma modulation has only recently achieved
commercial implementation. The technique utilizes oversampling and digital filtering to achieve
high performance in both AID conversion and filtering at low cost. The advent of commercial
delta-sigma converters is due in most part to recent advances in mixed analog-digital VLSI
technology. Precision analog circuitry can now be
integrated on the same chip with powerful digital
filters.

Figure AI. Delta-Sigma ADC

In a delta-sigma ADC, the same digital filter used
in the AID conversion process can perform
system-level filtering with performance unachievable in analog form. Therefore, the first
commercial delta-sigma converters have been
targeted at applications demanding high-performance filtering (high-end modems, digital audio,
geophysical exploration, etc).
This application note uses the CS5317 voice
band AID converter for examples. See the end of
this application note for implementation details
for the CS5317, CS5501, CS5326 AID converters.

Delta-Sigma Techniques,

embedded in an, analog negative feedback loop
with high open loop gain. The modulator loop
oversamplesand processes the analog input at a
rate much higher than the bandwidth of interest.
The modulator's output provides small packages
of information (that is, I-bit) at ,a very high rate
and in a format that the digital filter can process
to extract higher resolution (such as 16-bits) at a
lower rate.
The delta-sigma converter's basic operation can
be analyzed in either the time domain, or (more
conventionally) in the frequency domain.
Time-Domain Analysis

The basic operation of a delta-sigma modulator
can be understood more intuitively by demonstration. A simple, first-order modulator (that is, a
conventional voltage-to-frequency converter) is
shown in Figure A2. (Note: a modulator's order
indicates the number of orders of analog filtering
- or integration - in the loop). Full-scale inputs
are ± I V and three nodes are labeled VI, V2, and
V3. The output of the comparator, node V3, is the
output of the loop and is also converted by the
I-bit DAC into plus or minus full-scale (+1 V or
-IV).
At the differential amplifier, the + 1V or -1 V is
subtracted from the analog input voltage. The result, the voltage at node VI, is input to the
integrator. The integrator acts as an analog accumulator; ie. the input voltage at node V 1 is added
to the voltage on node V2 which becomes the
new voltage on node V2. Node V2 is then com-

Digital
OUIput

Fundamentals

Dmerential

Integrator

"

CompanltOr

AmpIHIer
+1.

A delta-sigma ADC consists of two basic blocks:
an analog modulator and a digital filter (see Figure AI). The fundamental principle behind the
modulator is that of a single-bit AID converter
5·8

?
-1v

DAC

'
I

Figure A2. 1st.order Delta·Sigma Modulator
AN10REV1

----------------------

Delta-Sigma Techniques

pared to ground. If it is greater than ground, node
V3 becomes +IV; if it is less than ground, V3
becomes -1 V, Each operation occurs once during
each clock cycle.
In the example shown in Table AI, all nodes are
initially set to zero, and the analog input voltage
is assumed to be 0.6v' Since all nodes are identical in clock cycles two and seven, the period
defined by. cycles two to six will repeat if the
analog input remains unchanged. The average
value of modulator outputs (at node V3) during
that period, 0.6, yields a numerical representation
of the analog input.

Clock
Period

V1

V2

V3

0
1
2
3
4
5
6
7
8

0
0.6
·0.4
·0.4
1.6
-0.4
-0.4
-0.4
-0.4

0
0.6
0.2
·0.2
1.4
1.0
0.6
0.2
-0.2

0
1_
1
-1
1
1
1_
1
-1

Period
Avg

0.6

Table Al. Modulator Walk-Through

With conventional voltage-to-frequency converters a digital counter is used to extract the
information in the VFC's I-bit output. Pulses are
counted over a specified period, effectively creating a digital averaging (or integrating) filter. The
final count represents the average analog input
value during the integrating period.
Advanced delta-sigma converters use higher-order
modulators and more powerful digital filters. For
example, the CS5317 uses a second-order modulator. The pattern of transitions in its I-bit output
provides more useful information regarding
higher resolution at higher frequencies.
AN10REV1

However, a more sophisticated digital filter than a
counter is needed to interpret that information. A
digital FIR filter is basically a roIling, weighted
average of consecutive samples (see Appendix
B). An averaging filter weights all samples
equally. By applying a more sophisticated
weighting function to the I-bit signal, a digital
FIR filter can assemble an N-bit output (with 2N
possible values) without having to wait for 2N
samples.
The Charge-Balance Name

Delta-sigma ADC's are also known by other
names - sigma delta and charge-balance are two
examples. The Charge-Balance name derives
from the fact that the modulator tries to balance
the analog input with the DAC's output in the
negative feedback loop. The charge injected onto
the integrator's capacitor from sampling the analog input (see Figure A2) is therefore balanced by
the charge injected by the DAC's output. Modulators have been implemented in both
switched-capacitor and continuous-time form.
Frequency-Domain Analysis

Since filtering plays a key role in a delta-sigma
ADC, it is easier to understand the converter's
operation by analyzing it in the frequency domain.
Overview

An AID converter's resolution determines its dynamic range (or signal-to-noise ratio).
Conversely, one can improve a converter's signalto-noise ratio and thereby increase its
effective resolution. The fundamental concept
behind delta-sigma converters is to perform a
simple, low-resolution AID conversion and reduce the resulting "quantization noise" (without
affecting the frequency band of interest) using
analog and digital filtering.

5-9

_
..--__.._-_
...
.-_
.-.-.
Quantization Noise

The comparator in the delta-sigma modulator
loop plays the role of a I-bit NO converter. Any
NO converter can represent a continuous analog
input by one of only a finite number of codes,
giving rise to an uncertainty, or quantization error, of up to ± 112 LSB. For a consecutive
sequence of samples in a waveform, these quantization effects can be modeled as a random noise
source under conditions commonly encountered
in signal processing applications. (These conditions hold true for delta-sigma modulators). The
rms value of the noise source relative to a fullscale input can be shown to equal - (6.02 N +
1.76) dB, for an N-bit resolution converter. Since
this error "signal" is totally random (or uncorrelated with the input) it can be assumed to be
white, with its energy spread uniformly over the
band from dc to one-half the sampling rate.
As a 1-bit ADC, the comparator in a delta-sigma
modulator offers (an almost comical) 7.78 dB
signal-to-noise ratio. However, the input signal is
grossly oversampled (2.5 MHz in the CS5317),
thus spreading the quantization noise over a wide
bandwidth (1.25 MHz). The noise density in the
bandwidth of interest (5 kHz) is therefore reduced.

Delta-Sigma Techniques

Dout = Q(n) - H(f) Dout
Q(n)
Dout = 1 + H(f)
The quantization noise at the output is reduced
by the open-loop gain of the integrator. At low
frequency, the integrator is designed for high
open-loop gain, so that quantization noise is reduced. As shown in Figure A4b, the integrator
effectively pushes the quantization noise out of
the bandwidth of interest and into higher frequencies. Digital lowpass filtering then removes the
quantization noise at the higher frequencies without affecting the low-frequency spectrum of
interest.
The spectral characteristics of the analog loop filtering dictates the delta-sigma converter's
resolutionlbandwidth ratio. Higher-order integrators improve noise shaping and allow for higher
resolutions at wider bandwidths. The CS5317
uses a second-order modulator for superior noise
shaping.
Q(n)

Vin~H(f)

~
~

Dout

Figure A3. Analog Modulator Model

Noise Shaping
Digital Filtering

Analog filtering is used in the modulator loop to
further reduce noise density in the frequency
band of interest by shaping the quantization noise
spectrum. The spectrum of the input signal,
meanwhile, remains unaltered. Figure A3 shows a
modulator loop with analog and digital circuit
differences ignored. The comparator is simply
shown as a (quantization) noise source, and the
analog filtering, which is simply an integrator, assumes the filter response H(f). If the analog input
equals zero, then

The spectral characteristics of the back-end digital filtering also affects the delta-sigma
converter's resolutionlbandwidth ratio. Faster rolloff and greater stopband rejection reduces
residual quantization noise. Section B offers a detailed explanation of the theory behind digital
filtering.
Anti-Alias Requirements

As shown in Figure A4, the input and digital filtering spectrum of any ADC repeats around
integer multiples of its sampling rate. A delta5-10

AN10REV1

_.-_..--_._.
__.._-_
...-.

Delta-Sigma Techniques

sigma ADC thus does not provide noise rejection
in the region around integer multiples of the sampling rate (± 5 kHz around 2.5 MHz, 5 MHz, 7.5
MHz... ). If noise exists in the system in these
narrow bands, analog filtering is needed to remove it at the converter's input otherwise it will
alias and pass unfiltered to the converter's output.

Since delta-sigma ADC's are grossly oversampled, anti-alias filtering requirements are often
trivial. For instance, the CS5317 provides a factor
of 500 of oversampling (2.5 MHzl5 kHz). A single-pole, passive RC filter at the CS5317's input
is therefore sufficient in most applications.

Decimation
a. Analog Input Spectrum

L.
5kHz

2.5MHz

1-3dB

1s

b. Modulator Digital Output Spectrum
Shaped
Quantization

Spectrum Repeats at
Oversampling Rate

Even though the delta-sigma ADC oversamples
and processes analog samples at a frequency well
above the bandwidth of interest, it will generally
offer its high-resolution output at a much-lower
system sampling rate. Any reduction in sampling
rate is termed decimation. The output can be further decimated at the system level by selectively
reading a fraction of the available samples (for
instance, every tenth sample). Independent of the
decimation ratio, the converter's noise performance (and effective resolution) remains
unchanged.

Conversion Accuracy/Performance
2.5MHz

5kHz
c. Digital Filter Response
No Noise Rejection
at Integer Multiples
01 Oversampling Rate

2.5MHz

5kHz

d. Digital Filter Output Spectrum

Like integrating ADC's and VIP converters, a
delta-sigma ADC does not contain any source of
nonmonotonicity and thereby offers "theoretically
perfect" DNL with no missing codes. The ADC
in the modulator is simply a comparator, and the
DAC is the positive and negative voltage references. No precision ratio matching is needed as
in other medium- or high-speed NO conversion
techniques such as successive-approximation.
Useful resolution is limited only by residual
quantization noise which, in tum, is determined
by coarse analog and high-performance digital
filteririg.

(Belore Decimation)
Spectrum 01 Interest

5kHz

2.5MHz

Linearity error is limited only by imperfections in
the input sample/hold. The CS5317 achieves typical nonlinearity of just ± 0.003 % through the use
of high-quality on-chip silicon dioxide capacitors
with low capacitor voltage coefficient.

Figure A4. Delta·Sigma Spectral Analysis
(Using frequencies taken from the CS5317 AID
Converter)
AN10REV1

5·11

-____-_

.. ....
. 1(IIIIf'-.....
..
....

Delta-Sigma Techniques

SECTIONB

Sampled-Data Theory

OVERVIEW: DIGITAL FILTERING

A fundamental phenomenon in sampled-data systems is an effect called "aliasing." Basically, once
an analog signal is sampled, its frequency components are no longer uniquely distinguishable.
Figure. B la shows a special case called "dc aliasing." If a signal is sampled precisely at its
fundamental frequency, it will always be sampled
at the same point on the waveform. It thus becomes indistinguishable from a dc input.
Likewise, a signal at twice the sampling frequency (or any integer multiple of fs) would
appear as dc as well. Figure BIb illustrates a
more general case of aliasing. Again, two signals
at different frequencies become indistinguishable
once sampled.

A conventi6naJanalog filter implements a mathematical equation using. reactive components
(capacitors and inductors). A digital filter can implement the same filter equation using two
fundamental arithmetic operations: multiplication
and addition (or accumulation). A digital filter
considers a consecutive sequence of digitized
samples a "waveform." It analyzes the relationship between samples, processes the data, and
outputs an adjusted waveform.
Digital filters offer ideal stability, repeatability,
and potentially perfect performance (linear phase,
etc.). Digital filters also remain impervious to environmental conditions, thus providing superior
reliability over time and temperature. The major
difference compared to analog filters, though, is
that digital filters operate on a signal in sampled
form.

The effect of aliasing in the frequency domain is
illustrated in Figure B2. The baseband spectrum
(dc to one-half the sampling rate) also "appears"
around integer multiples of the sampling rate,
and vice-versa. In signal processing applications,

Volls

Time

Is
f = f s (sampling frequency)

a. Continuous-Time Input Spectrum

a. dc Aliasing
Volls

Is/2

Is

h. Sampled-Data Spectrum
f = (N + 1) f s IN

h. General Aliasing

Figure B1. Aliasing in Sampled-Data Systems
5-12

Figure B2. Sampled-Data Spectrum
AN10REV1

_.-_..--__.._-_
...
._.-.
anti-alias filtering is used to bandlimit the analog
signal before it is sampled. This removes out-ofband components which could be mistaken for
important information in the band of interest.

Delta-Sigma Techniques
be achieved by increasing integration time. The
trade-off is bandwidth.

O~----

Aliasing is critical in digital filtering. A digital
filter is incapable of distinguishing signals in its
passband from signals aliasing from around its
sampling frequency. Its passband spectrum therefore repeats around integer multiples of the
sampling frequency. Take for instance the case of
dc aliasing shown in Figure Bla. A digital lowpass filter would treat the signal at fs as a dc
input and pass it with no attenuation. Similarly, if
the filter would attenuate the lower-frequency signal in Figure BIb by 10 dB, the higher-frequency
signal would receive the same 10 dB of attenuation. The higher-frequency signals in both cases
could be selectively filtered only by analog antialias filtering before the signal is sampled.

m

__- - - -__- - - -__- - - -__- - - ,

-40

- - - - - - -

-60

- - - - - - -

- -

- - - - - - -

- -

- - - - -

-BO

- - - - - - -

- -

- - - - - - -

- -

- - - - -

:E.

t~

-100 '-----'---'---'---'---'---'---'---'---'-----'
o
2fsIN
4f,IN
61s /N
BlslN
1Of,/N
Frequency (Hz)

Sampling rates are usually set high enough that
analog anti-alias requirements become trivial (or
perhaps eliminated). Higher oversampling ratios
offer greater bandwidth to roll off between the
passband and sampling frequency. Noise in the
digital domain can be analyzed just as it is in the
analog domain. Limiting a system's bandwidth
will reduce noise and improve dynamic range.
Digital Filtering

The most popular digital filtering technique is averaging. A sequence of digital samples are simply
collected and averaged to produce an output. This
reduces noise by limiting the effective noise
bandwidth. Averaging yields a (sin x)/x (or sinc)
filter response as shown in Figure B3. The zeroes
of infinite rejection (at fsIN, 2fslN, 3fsIN, etc.)
can be strategically placed by selecting fs and the
number of samples averaged, N, to average over
an integral number of periods of critical frequencies (50 Hz, 60 Hz, etc.). Of course, this same
principle lies at the heart of integrating ADC's,
but the averaging is done in analog form. In both
cases greater dynamic range (or resolution) can
AN10REV1

Figure B3. Averaging Filter Response

FIR Filters

Averaging is an elementary example of FIR, or
Finite Impulse Response, digital filtering. Finite
Impulse Response indicates that the filter considers only a finite number of inputs to calculate
each output. The number of samples determines
the impulse response duration. For example, a filter which averages ten samples has an impulse
response duration of ten. Longer durations indicate more information is considered for each
calculation, resulting in a more powerful filter response.
A digital filter's impulse response is what determines its filter function. It is basically a
weighting function applied to the sequence of
samples being considered. The averaging filter is
an elementary example of an FIR filter because it
uses equal weighting (weight = lIN where N =
# samples). More sophisticated impulse responses
extract the information contained in the relation5-13

-,

.-_
_
..--_._.
_-.._-....-.

Delta-Sigma Techniques

ship between samples. Averaging filters ignore
this infonnation.

Figure B4 illustrates how an FIR filter actually
implements the impulse response. The two basic
operations are multiplication (indicated by (8))
and addition - or accumulation - (indicated by l:).
Filter coefficients 3u to ll:! represent the impulse
response. The three unit delay elements insure
that each output is calculated using the current
input sample and the three previous samples. The
filter's input, x(n), and output, yen), are digital
words of any length. (For the CS5317, x(n) is
I-bit and yen) is 16-bits). Each digital output requires one complete convolution. For the
4th -order filter shown in Figure B4, one convolution consists of four multiplications and the
accumulation of the four products.
FIR filters are often described in tenns of taps.
This terminology hails back to analog transversal
filters, which' were basically analog implementations of the filter in Figure B4. The analog delay
elements were tenned taps. The number of taps
indicated the filter's impulse duration. The longer
the duration, the more powerful the filter.
Decimation

Digital filters often operate with input sampling
rates well above the bandwidth of' interest. This
serves to minimize analog anti-alias filtering requirements. The filter's output rate, however, is

generally dropped to a more manageable system
sampling rate. Any reduction in sampling rate is
tenned decimation.
To illustrate the decimation process lets return to
averaging. A filter which collects ten samples and
then averages them to produce one output decimates by ten. That is, for an input rate of fs, the
output rate is fsl10. Alternatively, one could use a
"rolling average." For each input sample received,
an output would be calculated using that sample
and the nine previous samples. The sampling rate
would therefore remain at fs with no decimation.
The 4th-order FIR filter in Figure B5 exhibits the
same filter response as that in Figure B4, but
decimates by a factor of four. In this case, only
one multiplication is perfonned per input cycle.
Without any delay elements, the accumulator
needs four input cycles to complete one convolution. Output samples are therefore produced at
fsf4. Decimation clearly relaxes computational
complexity.
Decimation does not affect overall signal-to-noise
or dynamic range. For this reason, one can decimate the CS5317's 20 kHz output (by selectively
reading a fraction of the available samples) without affecting the converter's noise. However, a
digital signal is nonnally not decimated if additional filtering is to be used to increase dynamic
range (and resolution). All noise energy in a sampled signal lies between dc and one-half the

---------<\
x(n) '>---~

Circulating
Address
Generator

[::>

y(n) = A

L

>$til

i=O

Figure B4. 4th_order FIR Filter
5-14

a 1 Coefficient
ROM

y(n)

N·l
Unit Delay Elements

aO

Figure B5. 4th_order FIR Filter with 4X Decimation
AN10REV1

---------------------sampling rate. Lower sampling rates therefore exhibit larger noise densities in the bandwidth of
interest for a given amount of noise energy due to
aliasing.

Delta-Sigma Techniques
computational complexity. Therefore, IIR filters
generally operate with lower sampling rates.
The CS5317 Voice-band AID Converter
Implementation

FIR Characteristics
The only source of inaccuracy in digital filters is
rounding errors due to finite word lengths in the
computations. If properly designed, a digital filter
will not induce linearity, offset, or gain errors.
Aside from their simplicity, FIR filters' most
popular characteristic is their ability to implement
perfectly linear phase filters. The effect of every
input sample on the output is always seen afixed
number of cycles later. This processing delay
from input to output is termed the filter's group
delay, and can be shown to equal one-half the
impulse response duration.
Unfortunately, FIR filters can only implement zeroes, no poles. Roll-off is therefore limited. Of
course, this limitation can be overcome by cascading FIR filters to produce an extraordinarily
long impulse duration. (Fortunately stability is
not an issue with FIR filters). The trade-off,
though, is an extraordinarily long group delay.

IIR Filters
Infinite Impulse Response filters, on the other
hand, can implement zeroes and poles to achieve
high roll-off. Unlike FIR filters, which use previous inputs to calculate an output, IIR filters
also utilize historical output information to calculate each new output. In this manner, IIR filters
can implement mathematical filter equations with
variables in the denominator (that is, poles).
The only drawback to IIR filters is their computational complexity. Since their computations use
historical information on their past outputs, each
output must be calculated. That is, unlike FIR filters an IIR filter cannot decimate to reduce
AN10REV1

The CSS317 uses overs amp ling, decimation, and
FIR filtering to implement its digital filter. The
CSS317 samples its analog input at 2.5 MHz (for
a full-rated S MHz master clock). This high oversampling ratio of SOO: 1 (2.S MHz sampling/S
kHz bandwidth) reduces external analog anti-alias
requirements.
The FIR filter decimates the sampling rate from
2.S MHz to 20 kHz to reduce computational complexity. The filter features an impulse response
duration of 384 X 2.S MHz and a decimation ratio
of 128 (2.S MHz:20 kHz). Since the filter does
not decimate by 384 as shown in Figure BS, multiple convolutions must be in process
concurrently. To achieve this, the CSS317 uses
three accumulators working from a single 384word coefficient memory. The three convolutions
are spaced to begin and end 128 samples apart.
Thus, a new 16-bit output sample becomes available every 128 input samples (for a decimation
ratio of 128) whereas each 16-bit output is calculated using 384 input samples (for an impulse
response duration of 384).
The CS5501 dc Measurement AID Converter
Implementation
The CSSSOI uses oversampling, decimation, and
both FIR and IIR filtering to implement its 6-pole
Gaussian filter. The CSSSOI samples its analog
input at 16kHz (for a full-rated 4.096MHz master
clock). This high oversampling ratio of 1600:1
(16kHz sampling/10Hz bandwidth) reduces and
most often eliminates external analog anti-alias
requirements.
The FIR filter is used to decimate the sampling
rate from 16kHz to 4kHz to reduce computational complexity in the subsequent IIR filter. The
5-15

•

....
_._..--___-_
...
._.-.
FIR filter response is not especially critical. Its
only goal is to reject energy within ±lOHz bands
around integer multiples of 4kHz, the IIR filter's
sampling rate.
The IIR filter is needed to implement the poles in
the 6th-order Gaussian filter and achieve high
roll-off of 120dB/decade. Its baseband filter characteristics are shown on page 4. Note that the
filter's entire frequency response can be scaled by
adjusting the master clock. The converter's sampling rate simply scales accordingly. With its
cut-off frequency set at 10Hz (4.096MHz master
clock) for maximized settling, the CS5501 offers
55dB rejection at 60Hz. With a 5Hz cut-off,
though, 60Hz rejection increases to greater than
90dB. Master clocks as low as 40.96kHz are acceptable, yielding cut-off frequencies as low as
O.1Hz.

Delta-Sigma Techniques

of a half-band filter for FIR3. Data is truncated to
16 bits at the output, and this operation is the major noise contributor in *e system.
FIR!, FlR2, and FIR3 also combine to provide
antialiasing filtering. All analog input frequencies
from 26kHz to 3046kHz are attenuated by at
least 86dB. Phase response is precisely linear.

The CS5326 Digital Audio AID Converter
Implementation

Linear-phase finite-impulse-response (FIR) filters
are used for decimation. The I-bit, 3.072 MHz
outputs of the modulators are decimated in steps
of 8, 4, and 2 to yield 16-bit, 48kHz results.
The decimation strategy includes two stages,
FlRl and FIR2, whose primary responsibility is
attenuation of quantization noise prior to decimation and aliasing. Modulator out-of-band
quantization noise spectral density is very high.
FIRI and FIR2 use 17 and 18-bit coefficients to
attenuate this noise, and out-of-band input sig~
nals, into the converter noise floor. Filter orders
are 27 and 30, respectively.
A third stage, FIR3, performs passband shaping
and out-of-band signal attenuation. Passband frequency response errors introduced by the
modulator, FIR 1, and FIR2 are corrected by
FIR3. Overall filter passband ripple is thus reduced to ±o.OOldB from dc to 22kHz. The
passband compensation function prevents the use
5-16

AN10REV1

........--- ...
.......,..
~

.",.",

AN35

~~

Semiconductor Corporation

Application Note
The CS5504 Family Characteristics
The CS5504/5/6n18/9 are a series of NO
converters all derived from a high performance
M: architecture. The CS5504 family members
are based on a core architecture including both
an analog modulator and a digital filter, with
only subtle differences between the individual
products. The digital filter has been optimized
to attenuate ac line interference (50/60 Hz and
their harmonics) when the devices are operated
from a low-cost 32.768kHz crystal.
The use of a low-cost 32.768kHz clock provides
20 samples per second from the family. The
CS5505/6nJ8 can achieve up to 100
samples/second with a 163kHz system clock,
while the CS5504/9 can achieve up to 200
sampleslsecond when operated from it's
maximum input clock of 330 kHz. In achieving
higher conversion rates, the CS5504 requires
slightly higher operating currents than the
CS5505/6n18. The CS5509 achieves the same
high conversion rate as the CS5504 with lower
power consumption, but pays a slight penalty in
linearity.
Max.
Resolution #Channels Speed3
21
20-bits
200
CS5504
16-bits
42
100
CS5505
20-bits
42
100
CS5506
11
CS5507
16-bits
100
11
CS550S
20-bits
100
11
16-bits
200
CS5509
Notes:

Linearity4
(Typical)
0.0007%
0.0015%
0.0007%
0.0015%
0.0007%
0.0015%

Table
summarizes the similarities
differences of the CS5504 family.

and

The CS5504/9 come in smaller packages than
the CS5505/6n 18, however, the CS5505/6n 18
have more functionality and flexibility. The
CS5505/6n 18 offer a sleep function, an on-chip
voltage
reference,
and
multiple
serial
communication modes.
Table 2 shows the CS5504 family's wide array
of power supply options. Note: the CS5509 is
single supply, however, the VA+ supply for all
devices must always be the most positive
operating voltage under all operating conditions,
including start-up.

CS5504151
6mS
CS5509

VA+
+5 to +10V
+5V
+5V
+5V
+5V

VAOV
o to -5V
o to -5V

-

VD+
+5V
+5V
+3.3V
+5V
+3.3V

Table 2. Power Supply Arrangements

Sleep Power
No
4.4 mW
3mW
Yes
3mW
Yes
Yes
3mW
3mW
Yes
No
1.7mW

On-chip
VREF
No
Yes
Yes
Yes
Yes
No

Serial Port
Pin Count
Modes5
SEC
20
SEC,SSC
24
SEC,SSC
24
SEC,SSC
20
SEC,SSC
20
SEC
16

Table 1. CS5504 Family Characteristics
1. Fully-differential
2. Pseudo-differential
3. CS5509 is production tested at 330 kHz (200 samples/second)
All others are production tested at 32.768 kHz for the best 50/60 Hz rejection.
4. These linearity specifications are based on a 20Hz output rate using a 32.768kHz crystal.
5. SEC is synchronous external clocking of the data out while SSC is synchronous self-clocking.

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX 445-7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JAN '95
AN35REV2
5-17

.

"

l

_-.
...........
..,--- ._.
.........

CS5504
Famiry CI\a,ract~rlstics
.
.

~

~

• Notes·

5-18

AN31REV2

.... ...
.......,-.......
~

..,..,~

AN36

~~

Semiconductor Corporation

Application Note

CS5516 and CS5520: Overcoming Errors in Bridge
Transducer Measurement

The CS5516 and CS5520 Bridge Transducer
AID converters address many of the common
error sources encountered when digitizing bridge
transducers.
This application note describes
many of these error sources and explains how to
minimize their effects. Many of the features of
the CS5516 and CS5520 which allow for the
control of these error sources are also discussed.
Some of the content of this application note was
originally a portion of the CS5516 and CS5520
data sheet and was titled" Enemies of the Strain
Gauge".
Strain gages are sensing devices which change
resistance when subjected to mechanical stress.
The amount of stress to which the gage is
exposed is usually limited to minimize possible
damage to the gage due to overstress. A strain
gage is a passive electrical device. Most often
gages are configured in a Wheatstone bridge
configuration to enhance their sensitivity while
minimizing the effects of drift. The bridge may
be excited with either a voltage or a current.
Excitation is supplied through connecting leads
to the bridge. The connecting leads will include
resistances (Rpl and Rp2) as shown in Figure 1.
These resistances will affect the gain of the
bridge:

Rp1
VEXC+

VEXC-

Figure 1. Four·Wire Bridge

When a bridge connected gage set is included as
part of a mechanical assembly (often called a
load cell), a connecting cable is often included.
Manufacturers will include the errors due to Rpl
and Rp2 in the specification for the load cell
assembly.
Rp1
VEXC+
VREF+ (sense)
~----=-:,----+

AIN+
AIN-

Y---------+

VREF- (sense)
VEXC-

Rp2

. AIN+-AINAv =----''---'''.~----=-:=-:.-

VEXC+ - VEXC-

Crystal Semiconductor Corporation
P.O. Box 17847. Austin, TX 78760
(512) 445·7222 FAX 445-7581

Figure 2. Six·Wire Bridge

Copyright © Crystal Semiconductor Corporation 1995
(All Rights ReseNed)

SEPT '94
AN36REV1

5·19

___
........
_-.
. _.
_............
...

C55516/20: Overcoming Errors in Bridge Transducer Measur~ment

A six-wire bridge, as shown in Figure 2, allows
for force and sense (Kelvin connection) leads to .
measure the excitation directly at the bridge.
This allows all errors due to Rpl and Rp2 to be
removed if a ratiometric measurement system (as
provided by the CS5516 and CS5520) is
employed.

to accommodate load cell zero drift or load cell
creep.

Bridge Offsets

Of critical importance when removing offset is
for the DAC output to remain ratiometric to the
voltage reference if the voltage reference should
change. The CS5516 and CS5520 converters are
designed to perform ratiometric; non-reference
sensitive offset removal.

It is common for bridge configured load cells to

50/60 Hz Pickup

have a zero offset specified to be as great as
±1O% of the full scale output signal. In a typical
digitizer this offset must be "trimmed out" by
adjusting a potentiometer.
This may be
necessary to reduce the portion of the dynamic
range of the measurement system which is
consumed by the offset of the load cell. In some
weighing systems, another source of offset
which may consume dynamic range is the pan
weight; sometimes called the tare weight. Prior
to making a weighing, an empty pan is placed
on the scale. Then a zero or tare button is
activated and signals the digitizer to remove the
offset produced by the empty container. After
the offset due to the pan weight is removed, the
actual item to be measured is then added to the
pan. Pan weight can consume a large portion of
the dynamic range of the digitizer depending
upon the method by which it is removed from
the measurement.
The CS5516 and CS5520 converters include a
4-bit offset trim DAC. The. DAC allows the
removal of up to ±200% of the selected range's
full scale before the signal is digitized. This
avoids the loss of resolution in the digitizer
caused by load cell or pan weight offsets. The
converters also include a ratiometric offset
calibration register which can be calibrated or
manipulated to add or subtract offsets from the
digital output words after conversion has been
performed. This allows the transfer function of
the converter to be offset (either plus or minus)

It is common in some weighing applications for

the load cell to be located some distance from
the digitizer. The load cell leads can become
exposed to radiated noise caused by line
interference at 50 or 60 Hz. Twisted pair
interconnections should always be used· on the
AIN+, AIN- and VREF+, VREF- pairs to
minimize 50/60 Hz pickup. Nonetheless, some
amount of line interference is inevitable.
The line interference may enter into the AID
converter circuitry by either the AIN signal input
or the VREF input (Line interference may also
appear on the power supply leads, in which the
power supply rejection of the AID converter is
an important issue, but in this discussion the
focus is on the interference picked up by the
transducer leads).
When line interference enters the AIN and
VREF inputs of a traditional AID converter, the
interference will most likely introduce errors into
the output words of the converter.
To
understand why, assume that 60 Hz interference
enters into the converter by means of both the
AIN and VREF inputs. The AIN signal is:
AIN+ - AIN- = VIN + bcos(27t60t)
Assuming the input and reference paths are well
matched, the VREF input would be:
VREF+ - VREF- = VREF+ bcos(27t60t)

5-20

AN36REV1

-____-_.

.. ......
. ........
....
.."

CS5516/20: Overcoming Errors in Bridge Transducer Measurement

The AID converter computes the ratio:

26-27 counts error in a 20-bit AID converter; or
1.66 counts error in a 16 bit AID converter.

AIN
VREF
The dc component of the AID output is obtained
by averaging the ratio of AINNREF over a 60
Hz period of T = 16.7 msec. The AIN and
VREF inputs include the interference component
bcos(21t60t) as shown in the previous equations:

Note that the error when interference is present
will be zero only if AIN = VREF, that is only if
the AIN signal is a full scale input with the same
magnitude (including line interference) as on the
VREF input. This measurement condition is
unlikely to occur.

1 fT AIN+ - AIN- d 1 VIN - VREF
t - +--F=i<=~~
T 0 VREF+ - VREF- -YV~EF _ b 2

We see that line interference can cause
measurement errors. Interference into only the
voltage reference input can introduce similar
errors into the converter.

To develop a feel for this result, let's define
some real input conditions as an example.
Assume a typical converter has a full scale span
of 2.5 volts (VREF = 2.5) and the input signal
AIN is 0.6 volts. The converter would output a
digital code which states that the input is a ratio
of 0.6/2.5 or 0.240 of full scale. If there is no
line interference on the AIN and VREF inputs,
that is b = 0, (no interference pickup), the output
result from the equation above is AINNREF=
0.6/2.5, or 0.240 as desired. If the interference
is not zero, that is, bO, (let's say the line
interference has a magnitude of 10 mY, that is
0.010) the output result will include an error
caused by the interference. The result will be:

The CS5516 and CS5520 converters minimize
errors due to line interference because the AIN
and VREF inputs to the converter are actual
independent AID converters which use a
common voltage reference which is internal to
the converter chip. Each of the two signals
(AIN and VREF) are converted and processed
by independent digital filters before the
With an
AINNREF ratio is computed.
appropriate choice of operating clock frequency
for the converter, the digital filters remove 50
and 60 Hz (and their harmonics).
The
robustness of the conversion output is
significantly enhanced when operating in harsh
50/60 Hz environments.

-

1

VIN- VREF
+ .yV~EF- b 2

1+

Non-Ratiometric Errors

0.6 - 2.5
-Y2.5 2 - 0.010 2

or
0.6 - 2.5
939
1 + 2.499980 = 0.2399
we take
0.9999745

If

the

ratio

0.2399939/0.240

=

The result is 25.5 ppm less than it would have
been, had the measurement not included the
interference. 25.5 ppm is equivalent to about
AN36REV1

A variety of offset sources can introduce errors
into the measurement which do not scale with
the excitation voltage; hence the name
non-ratiometric errors. Amplifier offset voltages
and parasitic thermocouples are two common
non-ratiometric offsets. The measurement errors
which can be caused by non-ratiometric offsets
will be examined more closely and then parasitic
thermocouples will be discussed more
thoroughly.
The first offset to be considered is shown as
Vas in Figure 3. The ADC output is given by:
5-21

.- ......_
.
.......
........
.., ... .

."

."

."

.CS5516/20: Overcoming Errors in Bridge Traflsducer Measurement

VIN
Vos
DOUT=--=Av+-VREF
VREF

" " - - - - - + VREF+

The sensitivity of DOUT to changes in the
excitation voltage will be termed S 1:
S1 = oDOUT VREF =
-Vos
OVREF DOUT AVVREF+ Vos
Some practical values illustrate the significance
of this equation. Suppose the sensitivity of the
load cell is 2 mVN (AV = 0.002) and the
excitation supply (VREF) is 10 V. Assume that
Vos = 20 IlV and that it is a non-ratiometric
offset generated by a parasitic thermocouple or
by the offset of a precision amplifier. This
yields a sensitivity S1 =0.001. Sensitivity factor
S1 is a measure of the sensitivity of the
converter output code DOUT to changes in the
excitation supply. The excitation supply may
drift due to temperature changes or due to
limited line and load regulation. A typical
regulator may change 1% over changing line,
load, and temperature changes. With S1 = 0.001
a typical 1% change in the excitation supply will
cause a 0.0001 % change, or a 10 ppm change in
DOUT. This lOppm error is in addition to the
\ error introduced by the 20 IlV offset itself. This
10 ppm error is significant, being 10 counts in a
20-bit converter or 2/3 count in a 16-bit
converter.
The above equation suggest three methods of
reducing Vos-induced errors:
1) Buy a gauge with a large Av.
2) Use a large excitation voltage (VREF).
3) Measure Vos and calibrate it out.
The CS5516 and CS5520 converters include the
features necessary to calibrate out nonratiometric offsets. Calibration is only effective
if the non-ratiometric offsets are stable after
being calibrated. The converters also support ac

5·22

~-----

VREF-

Figure 3. Yos Offset
VOR

A:------1II!---------=---"<----+

VREF+

AIN+

) t - - - - + AIN-

V S2

_ - - - - - _ _ + VREFFigure 4. YOR Offset

bridge excitation which removes the effects of
non-ratiometric offsets (more on this later).
A second non-ratiometric error is shown as VOR
in Figure 4. Its sensitivity is given by:
S2 = ODOUT VREF
OVREFDOUT

- VOR
VREF - VOR

Not surprisingly, in this case increasing Av
doesn't help.
Sensitivities S 1 and S2 simply confirm that,
when non-ratiometric errors are present, the AID
converter output will vary as the excitation
voltage changes. A zero tempco, zero aging,
excitation supply with perfect line and load
regulation can reduce this variation, but one
major advantage of a ratiometric measurement
system should be that a precise, stable reference
is not necessary.
Again the non-ratiometric calibration capabilities
of the CS5516 and CS5520 can remove the
adverse effect of VOR.
AN36REV1

_....,_.. ....-...-.

..,..,_.

..,..,

CS5516/20: Overcoming Errors in Bridge Tra'n$dLfcer'Measurement

Thermocouples

With ac excitation, the desired signal flips in
polarity as the excitation voltage flips. The
analog input becomes ·a square wave at the
excitation frequency as 'the excitation voltage
flips. Vos ddesn't flip. When--+

¥----~--+

VREF+

AIN+
AIN-

VREF-

-5V

Figure 6. Leakage Effects Offset

Conclusion
This application note has presented some of the
errors encountered in bridge transducer
digitizers, and has indicated how the CS5516
and CS5520 AID converters can overcome these
errors.

5·24

AN36REV1

.... ...
...,.......
......,..
~

~~~

AN31

~~

Semiconductor Corporation

Application Note
A Collection of Bridge Transducer Digitizer Circuits
by
Jerome Johnston

Introduction

Bridge Transducers

Bridge
transducers
are
common
in
instrumentation. This application note illustrates
some bridge transducer digitizer circuits which
use the CS5504/5/6n18/9 AID converters and the
CS5516120 AID converters.

Bridge transducers are manufactured with
various
technologies.
The
strain-sensing
elements which make up the bridge may be
made of diffused silicon, bonded silicon bars,
deposited thin film, or bonded foil materials.
The choice of technology will determine the
performance of the transducer, including the
sensitivity, the linearity, and the thermal
stability. Silicon-based gages have good linearity
with sensitivities between 3 mVN and
20 mVN, but tend to exhibit more drift as
temperature changes. Metal foil or thin film
gages have good linearity with sensitivities
between 1 mVN and 4 mVN. Precision bridge
transducers include some type of temperature
compensation as part of the bridge.

The CS5504/5/6n18 converters can be operated
with a variety of power supply arrangements;
including operating from a single +5 V supply;
operating from +5 and -5 analog supplies with
+3.3 V or +5 V on the digital supply; or
operating with an analog supply from +5 to
+ 11 V and a digital supply of +5 V.
The CS5509 can operate with +5 Von its analog
and digital supplies; or with +5 V analog and
+3.3 V digital.
The CS5516 and CS5520 are AID converters
optimized for bridge transducer applications and
are designed to operate from +5 and -5 V
supplies. Several circuits which utilize these
ADCs will be presented.
The application note is divided into two sections:
1. DC-excited bridge circuits.
2. AC-excited bridge circuits with a discussion
of the benefits of AC excitation.

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX 445-7581

Most bridge circuits are excited with a dc
voltage, 10 volts being very common. With 10 V
excitation, the full scale signals from the various
transducers, can be as low as 10mV to as high
as several hundred millivolts. When digitizing
these signals to high resolution· (for discussion in
this application note, high resolution means
greater than 10,000 counts), one count can
represent a very small voltage. It can be difficult
to amplify and digitize these low level bridge
transducer signals. Measurement performance
can be hindered by such things as amplifier

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MARCH '95
AN31REV4

5-25

01

_

.......... .

. ..,--- ._.
.............

Bridge Transducer Digitizer Circuits

offset drift, amplifier noise (both thermal and
1/t), amplifier finite open loop gain, and
parasitic thermocouples. Parasitic thermocouples
are introduced any time two dissimilar metals
are connected. For example, using tin-lead solder
to solder a wire to a copper PC trace can
introduce an unwanted thermocouple junction
which changes as much as 3 /lVrC when
subjected to temperature gradients.

DC-EXCITED BRIDGE CIRCUITS
CS5507,8,9 Bridge Transducer Operating
From a Single +5 V Supply, or with the
Analog Supply at +5 V and Digital Supply at
+3.3 V
Figure 1 illustrates the low cost CS5509 16-bit
converter operating from +5 V. The AID can
operate in either unipolar or bipolar mode and
yields 20 conversions/second when running from
a low cost 32.768 kHz crystal. When operated at
32.768 kHz the digital filter in the converter
notches out 50 and 60 Hz line interference.

This application note will introduce some AID
converter circuits which illustrate a number of
application ideas to the design engineer who
uses bridge transducers. In the AC-excited
bridge section, a number of design ideas will be
introduced which offer very good solutions to
some of the problems encountered in low level
bridge measurement.

The LTCI051 dual chopper amplifier is used as
the bridge amplifier. Bandwidth is limited to
about 3.8 Hz by the lOOk and 0.47 /IF feedback

+S
,

+3.3 V

~0.1
5.23k

SOO
10k

'

Optional
Gain
Trim 9
~3.2S

VA+

XIN

VREF+

XOUT
VREF·
CAL
CONV

>-__

100

7
~W\r_---I AIN+
100k

CS

32.768kHz
S=

3
2
1

CS5509
16 bits

System
Microcontroller

1k
931

~0.1

VD+

V

10

Sk

VD+can be
+5Vor +3.3V

13

16
0.1

DRDY
15
SDATA

5k

BP/UP

100k

SCLK

A1N·

6
14

100

20 Conversions/sec.

GND
12

Figure 1. CS5507,8,9 Bridge Transducer Operating from a Single +5 V Supply, or with the Analog Supply at +5 V
and Digital Supply at +3.3 V.

5-26

AN31REV4

.._-_
.-_..-...-..

~

~--

Bridge Transducer Digitizer Circuits
+5

elements of the amplifier stage. Note that an
instrumentation amplifier is not needed because
the AID input is fully differential. The dual
amplifier functions as a differential in,
differential out amplifier. the circuit yields
about 9000 noise-free counts when measuring
unipolar signals. Averaging 10 samples increases
this to about 28,500 noise-free counts.
"Noise-free counts" means full scale signal
divided by six times the rms noise. Noise-free
counts is good figure of merit for comparing
AID converters used in dc measurement
applications. There is more discussion on this
topic at the end of the application note.
The circuit illustrated uses a 3 mVN transducer
excited with +5 V for a full scale transducer
output of 15 mY. The transducer output is
amplified with a gain of about 216 to yield
3.25 V full scale. A dual stage amplifier, as
shown in Figure 2 may be preferred to minimize
errors due to limited loop gain. The AID is
operated in bipolar mode to achieve more
IlVILSB. The reference voltage for the converter
is derived from the +5 V excitation voltage. The
measurement remains ratiometric should the
+5 V excitation change.
Figure 1 includes potentiometers for offset and
gain adjustment, as do a number of other circuits
in this application note. Many system designers
prefer to eliminate potentiometers and do all
offset and gain correction in software. To

20k

20k

Figure 2. Dual Stage Amplifier

achieve this in some of the circuits may require
changes to gain stages or voltage references, but
potentiometers are shown for all the engineers
who are more comfortable with screwdrivers
than software.
The CS5509 in Figure 1 can run as fast as 200
conversions per second if operated with a
330kHz external clock. Figure 3 shows an RC
gate oscillator which can produce stable
frequencies, or a CMOS 555 timer can be used.
The gate oscillator can be operated from either a
+5 or +3.3 V supply and maintains fairly good
frequency stability over temperature.

+3.3 to +5

output

f

Rl

R2

C

162kHz

10k

3.4k

330pF

200kHz

B.2k

2.7k

330pF

330kHz

5k

1.6k

330pF

c
Figure 3. Temperature-Stable Gate Oscillator for +5 or +3.3 Volts.
AN31REV4

5-27

_
(

.._.........
...............
•

1116r_ •

• _.

Bridge Transducer Digitizer Circuits

All of the converters (CS5504-09) can be
operated with a single +5 V supply_ All of the
converters can also be operated with +5 V
analog supply and +3.3 V on the digital supply_
If this dual supply arrangement is used, the
digital supply should be derived from the analog
supply to ensure proper operation. Under all
conditions, including start-up, the voltage on the
VA+ pin must be the more positive than any
other pin on the device to ensure proper
substrate biasing of the chip.

automotive-type battery being COmmon. The
CS550415161718 devices can be operated with
higher supply voltage on the analog portion of
the chip than on the digital portion (Note: the
CS5509 is an exception and is specified with an
analog supply of +5 V only). The analog supply
(VA+) must always be the most positive voltage
on the chip to ensure proper operation. Figure 4
illustrates the CS5507 operating from + 10 V on
the analog and +5 V on the digital. The bridge is
excited with the + 10 V and resistors are used to
divide this excitation supply to obtain a
ratiometric voltage reference of about 3.33 V for
the converter. The circuit is designed to operate
with the AID in bipolar mode to yield more
J.l.V/count. The AID is set-up for an input span of
± 3.33 V. A 200k pull down resistor forces a

CS550718 with +10 V Analog Supply and
+S V Digital Supply
It is common for many weigh scales to be

operated

from

batteries

with

a

12

V

+10

20k
lk

Optional
Gain
Trim

VA+
11

VD+

VREF+
+5

= 3.33 V

10k

VREF-

CS

12
DRDY
+10

SCLK

100

18

8
AIN+

CS5507
CS5508
16 or
20 bits

75k

453

20

SDATA

19
System
Microcontroller

2
CONY
M/SLP

0.047

6
7

BP/UP
CAL

75k
10

+5

AIN100
3500 Bridge
2mVN

100 Conversions/sec

13

VREFOUT
VA-

3

XIN
DGND

Figure 4. CS5507/8 with +10V Analog Supply and +5 V Digital Supply.
5-28

AN31REV4

-........
.............
--._.-.

Bridge Transducer Digitizer Circuits

."

negative offset into the amplifier and the zero
trim is used to finely adjust this offset. With zero
weight on the scale, the zero trim is adjusted to
yield -30,000 counts if the CS5507 16-bit AID is
used or to -500,000 counts if a 20-bit CS5508 is
used. With full scale weight on the scale the gain
trim is adjusted for +30,000 counts in the
CS5507 or +500,000 counts in the CS5508
(Note that the CS5507 and CS5508 are pin
compatible). This leaves some counts for both
zero underflow and for overrange. The amplifier
components set the bandwidth to 45 Hz. With
the 45 Hz bandwidth, the circuit exhibits about
50,000 noise-free counts. With an external 162
kHz clock, the converter can operate at 100

conversions per second. If 20 conversion words
from the CS5508 are averaged, the circuit will
yield more than 200,000 noise-free counts. A
limitation of this circuit is that the bipolar
amplifiers can exhibit significant offset drift as
the temperature changes. There are several
circuits in this application note which will show
how to overcome offset drift.
CS5505/6 Operating From ± 5 V Supplies

The CS5504/5/617 18 converters (not the CS5509)
can be operated with ±5 V on the analog section
of the converter, and with either +5 V or +3.3 V
on the digital section.

+5
10
+5

~0.1

17

20
VD+

VA+
7.5k

14

XIN

VREF+

XOUT

~2.5V

15

VREFCAL

+5

CONY

:&0.1

9

AIN1+

0.1~

CS

CS5505
CS5506
16 or
20 bits

5

32.768kHz

6 =

4
3
2

AO
A1

24

System
Microcontroller

23
DRDY
SDATA
BP/UP
SCLK

AIN4+

M/SLP

AIN20 Conversions/sec

VA-

VREFOUT

22
8
21

7

DGND
19

Figure 5. CS5505/6 Operating from ± 5V Snpplies.
AN31REV4

5-29

-

....
. ....,-."., .._.
.. .
."

~

."."..,

Bridge Transducer,Digitizer Circuits

."

Figure 5 illustrates an application which uses an
instrumentation amplifier to amplify and convert
the
differential
bridge
signal
to
a
ground-referenced signal for the converter. Full
scale for the converter is set by the divider
resistors which determine the voltage reference
input to the VREF+/- pins of the converter. The
reference voltage in the figure is set to 2.5 V.
The bridge sensitivity is 2 mVN so the full

scale bridge output is 20 mY. This is amplified
by the 100 gain of the instrumentation amplifier
to obtain 2.0 V into the converter. The converter
can be operated in either unipolar or bipolar
mode. Up to four load cells, each with its own
amplifier, can be input to the CS5506. The
measurement assumes the voltage reference will
remain ratiometric across all four load cells.
CS5507 Switched-Bridge Low-power
Digitizer with +10 V Excitation
Some applications call for reduced operating
power. One method of significantly reducing the
power consumption is to apply the supply
voltage to the bridge transducer only when a
+10

Figure 6. CSSS07 Switched-Bridge Low-power Digitizer with +10 Volt Excitation.
5-30

AN31REV4

. .......

......

.., ..,....... _...,
~

~~

~~

Bridge Transducer Digitizer Circuits

measurement is required. Figure 6 illustrates an
example circuit in which the power to the bridge
transducer is switched on only when a
measurement is desired.

is powered for only 20 msec. for a reading each
second. If even lower off power is desired, the
supply to the LTl013 can also be switched along
with the bridge excitation.

The circuit as shown is optimized for a + 10 V
analog supply. The circuit can be modified
(optimized) to operate from any analog supply
from 11 V to 6.5 V (assuming the +5 V
regulator needs 1.5 V of input/output
differential) by changing the resistor values
which determine the voltage reference to the
converter and by changing the gain resistors in
the amplifier to compensate for the change in the
bridge output signal. The circuit shown
illustrates a 2 mVN transducer outputting
20 mV full-scale. A gain of 166 amplifies this to
3.32 V into the NO. The full-scale of the NO is
set at 3.33 V by dividing down the excitation
voltage.

CS5509 Switched-Bridge Low-power
Digitizer with +5 V Excitation

In the power arrangement shown, the CS5507

NO uses about 4 mW. The converter is clocked
from an external gate oscillator clock (162 kHz)
to yield a conversion time of 10 msec. When
power is applied to the bridge, a delay must
occur to allow the signal to settle before a valid
conversion can be performed. Settling time to 16
bits after power is applied to the bridge takes
about 3.3 msec. The microcontroller can use an
internal timer to time about 4 msec. to allow for
the delay or the microcontroller can perform a
dummy conversion in the converter to allow for
settling time. When the dummy conversion is
finished (10 msec. later) the conversion data is
discarded and a second conversion is then
performed to make a valid measurement. After
the second conversion is complete (DRDY falls
the second time) power to the bridge is
deactivated and the conversion word is clocked
out of the converter's serial port.
Power consumed by the
the power dissipated in
power consumption in the
by a factor of at least fifty
AN31REV4

transducer dominates
the circuit. Average
bridge can be reduced
«6 mW) if the bridge

The circuit in Figure 7 is similar to the previous
one, but operates from a single +5 V. The circuit
shows a load cell with 3 mVN sensitivity. A
2 mVN transducer can be used if additional gain
is added; or the voltage reference into the
converter can be lowered to 1.67 V with some
minor increase in noise. Average power
consumption in the load cell is only 1.5 mW for
one reading per second.
CS5516/CS5520 Using DC Bridge Excitation

The CS5516 (16-bit) and CS5520 (20-bit) NO
converters are designed for bridge measurement
applications. They include an instrumentation
amplifier with X25 gain, a PGA (programmable
gain amplifier) with gains of 1, 2, 4, and 8, and
a four bit DAC which can trim out offset up to
± 200% of the full scale signal magnitude. The
input span can be adjusted by changing either
the magnitude of the voltage at the VREF pins
of the converter or by changing the PGA gain.
In the circuit shown in Figure 8, the bridge is

excited with ± 5 volts. Resistors Rl, R2, and R3
divide the excitation voltage to give a 2.5 V
reference signal into the VREF pins. The input
span at the AIN pins of the converter is
determined by dividing the voltage at the VREF
pins by the PGA gain and the X25
instrumentation amplifier gain. For example,
with 2.5 V into the VREF pins, and the PGA set
to a gain of 8, the input span at the AIN pins is
2.5/(8 X 25) = 12.5 mV in unipolar mode or
± 12.5 mV in bipolar mode. The converter offers
several calibration features to remove offset and
to calibrate the gain slope, The input span of
5-31

.,.4

~I

....

+5
'\./

+5

0.1~

+-'---10
100k

:>

¢

TP0610L

~0.1
+5
11

021

10k

f----I

_~_----"

AA

13

VA+

~_~ _ _ ~

VD+
XIN

9

VREF+

Optional
Gain
Trim

+5

"

/

,':....i'·",
:.,.....

10 1 VREF-

~0.1

CAL 1 3
7

I

AIN+

CONV 12

cs

CS5509
16 bits

BP/UP

0.0471
DRDY
SDATA
SCLK

8

1

AIN-

6
16

System
Microcontroller

15
14

H
ii1

::s
111

a.

01, 02 Siliconix
2N7000

1 Conversion

GND
1 12

=20 msec

.----J 101

Ii

I~...

~.

100k

~I

m

<

""

v

(")

'V'

1-'ia
c

Figure 7. CS5509 Switched-Bridge Low-power Digitizer with +5 Volt Excitation.

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if

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.
.., ...........,
~

~~

~

12.5 mV (considered the nominal value for this
particular selection of PGA gain and VREF
voltage) can be gain calibrated for input signals
from 20 % less than or 20 % greater than the
nominal 12.5 mV value. In other words, the gain
can be calibrated with an input as low as 10 mV
or as high as 15 mV when the nominal value is
set for 12.5 mY. The nominal input can be
changed by changing the PGA gain or by
changing the divider resistors for the excitation
voltage. The converter can accept a VREF input
voltage of any value between 2.0 to 3.8 V.
The CS5516 and CS5520 can be operated on
any clock frequency from 1.0 MHz to 5.0 MHz.
the digital filter will give greater than 90 dB of
attenuation to 50 and 60 Hz line interference if
the input clock is 4.096 mHz or less. With a
4.096 MHz clock into the converter it will
output conversion words at a 50 Hz rate. For
optimal filtering it is desirable to average output
words from the converter. If ten output words
are averaged, the noise bandwidth is reduced to
about 2.5 Hz.

Bridge Transducer Digitizer Circuits

performance when used in a high resolution
bridge digitizer. Another limitation of a chopper
amplifier is that it corrects only its own offset
errors and does not correct offsets or parasitic
thermocouples external to itself, including those
created when its own package leads connect to
the circuit card traces.
There are several other approaches to chopping
the signal which can be used to enhance
performance. Circuits will illustrate a number of
these approaches. Some chop the signal after it
is output from the bridge. Others actua).ly switch
the polarity to the bridge itself. Either method
can be used to remove amplifier offsets and
parasitic thermocouple effects. Switching the
bridge has the advantage that it enables any
nonratiometric offset of the bridge to be
removed. But caution is advised; some silicon
gages can be damaged if the excitation supply is
reversed. Check with the gage manufacturer to
determine if a silicon gage bridge can be used
with AC excitation.

The CS5516 and CS5520 support either dc or ac
bridge excitation.

Switching the bridge may not be practical in
applications which have very long cables due to
the large cable capacitance.

AC-EXCITED OR CHOPPED SIGNAL
BRIDGE CIRCUITS

Bridge with Digital Offset Correction and
Kelvin Reference Sensing.

When
measuring
low
level
signals,
measurement performance can be enhanced if
the signal is "chopped". Chopper amplifiers are
commonly used to minimize amplifier offset
drift. The disadvantage of chopper amplifiers is
that they are generally manufactured using
CMOS technology and have higher thermal
noise than bipolar amplifiers. Chopper amplifiers
have low offset drift and the lIf noise of the
amplifier tends to be averaged out due to
chopping. Still, CMOS integrated circuit chopper
amplifiers tend to have noise performance
45
nVI~
to
somewhere
between
250 nVI~. This noise limits the measurement

One method of getting the lower noise of bipolar
amplifiers and achieve good offset stability is to
use digital offset correction. Figure 9 illustrates a
circuit in which the input of the amplifier stage
is periodically shorted and the offset measured
with the AID. The digital code is then used to
correct readings from the converter when the
signal is being measured. The schematic shows
only the circuitry for one channel (the CS5504
has two input channels). Only one half of the
DG303 is used per channel. LTlOO7 op amps are
used for their low noise; but a dual LTI013 or
quad LTl014 could be used if higher noise is
acceptable. The LTI013 and LTl014 are capable
of measuring signals with an input range which

5-34

AN31REV4

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~I

lOOk

O.I~

':1

35 7k
.

I I

lOOk

+10.

100

Wv

6

1

03
f

1/2
OG303

I I

.... / \

V-

149.9k

B

I AIN1+

$604

CS5504
20 bits

-.L 0.005

INI
B

I

I

BP/UP

7

SCLK

18

SOATA 119

v-.6

I

f49.9k

Wv

1

10

I AIN1-

D~~

100

+10V
Circuitry for
Channel 2

9·

AIN2+

CS

2

System
Microcontroller

I:D

::::!.
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ca

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11, AIN2CONY

SIG1-

,

0.005
+10

6

, - - - + - - - - SIG1+

,

....
="....

=f

1

0.005
(?l I T10m

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13

0.1

+10
31'-..Y7

I

330 kHz
OSC

~ VREF-

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01

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=3.6V

~AA

''',

i'·
.1:
."

1

-L

VA-

AO

OGNO

3

-I

DJ

iic.
c

\-----SIG2+
200 Conversions/sec before
averaging and offset removal

\ - - - - - SIG2-

.cfa
ca·
r.
(')

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c

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Figure 9. Bridge with Digital Offset Correction and Kelvin Reference Sensing.

UI

1-

if

-.......
......_
............
....

.., .,

includes the negative supply rail. One
application for this may be for measuring a
temperature compensating resistor in series with
the bridge (see inset in Figure 9).
The converter. in Figure 9 is set up in bipolar
mode (use bipolar mode even if you want
unipolar measurements as the bipolar setup
provides less noise per code and allows for
negative tempco drift of the zero reference point)
and runs at 200 conversions a second. To correct
offset and measurements on both channels, the
following measurement sequence was used:
Select the DG303 to short the inputs to both
channel one and channel two. Use AO on the
converter to select channel one. Perform one
conversion and discard the data to allow for
settling. Perform a second conversion and keep
the offset code for channel one. Change AO to
opposite state and measure the offset code for
channel two.
Switch the DG303 on both
channels to measure the input signal and set AO
to measure channel one. Perform one dummy
conversion and discard the data. Then perform a
second conversion and keep the reading.
Correct this reading with the offset reading taken
for the same channel. Then change AO and read
channel two and correct it for offset. Each
channel takes four conversions per result, so for
two channels, outputs are available at 25 per
second. A running average of 12 corrected
words is recommended to improve noise
performance. With 12 words averaged, the
performance is greater than 150,000 noise-free
counts with two updates per second for each
channel.

Bridge Transducer Digitizer Circuits

The voltage reference input to the ND converter
is buffered to reduce loading by the Kelvin sense
leads. If the voltage reference Kelvin sensing
lines are long, 50 and 60 Hz line interference
may be picked up. The voltage reference input to
the CS5504/5/6nt8/9 should' be filtered to
prevent line interference if the devices are
operated at a clock frequency other than
32.768 kHz.
Bridge with Signal Chopping Using CS5504

The load cell is often the dominant cost factor in
many weighing systems. A lower cost load cell
can be achieved by leaving out the temperature
compensation gages and reducing testing during
manufacturing. As long as the load cell
temperature drift is repeatable, the entire system
can be compensated with software in a
microcontroller. In this type of system, a
temperature sensor is usually embedded inside
the load cell. The entire system is then
characterized
over
temperature.
A
microcontroller reads the load cell and its
temperature and uses a look-up table to correct
the load cell output for drift over temperature.
Figure 10 illustrates an example.
The circuit uses the CS5504 two channel fully
differential ND configured to convert at 200
samples per second. The analog portion of the
ND and the bridge are operated from +10 volts.
The voltage reference for the ND is developed
from the bridge excitation. Channel two of the
converter measures the output of a thermistor
mounted in the load cell housing. The thermistor
is excited with the same voltage as the bridge.

If the circuit in Figure 9 is used at higher

temperatures, one DG303 should be used for
each amplifier stage with a switch (always on)
included in the negative lead of the bridge
circuit. With this configuration, the errors due to
leakage currents and the on resistance of the
switches will be more balanced on both the plus
and minus leads of the bridge.
5-36

The output of the bridge is amplified by a buffer
amplifier composed of two LT1007s. The
CS5504 is operated in bipolar mode with
± 524,000 counts. A DG303 analog switch is
used to reverse the polarity of the signal into the
amplifier
upon
command
from
the
microcontroller. A convert (CONV) command is
AN31REV4

?Z

+10

....
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+5

:rI

!:2

~.,

~

VO+
VREF+
'M

5
XIN

10k ::!;,.36V

330 kHz
OSC

VREF-

V

20k
RT

+10

~ :h~rmistor mounted

13

.....

91 AIN2+
CAL ' 4

InsIde load cell

,..,
,....i'·".:,
II,

14

7

V+

11
+10

+

"

0114

51S1

100

BPIlP

AIN2-

81

6

AIN1+

CS5504
20 bits

SCLK

118

49.9k
04112

131S4

SOATA

604

0.005 I
OROY

0313

2153

6
02 111

()()

20

0.005
+10

1°IS2

19

l

-I

1

1
49

:
100

INl ~16'----'-_ _ _ _- - - - t

10

CS

I AIN1-

2

.a:
aJ

~
CONY 13

VA-

System
Microcontroller

AO

DGND

-I

ii1
:::J

III

Q.

C

...g

OG303
IN219
GNO

o

cQ

V"'50 Conversions/sec before
averaging and chopped signal

i'...
o~.
c

~

Figure 10_ Bridge with Signal Chopping Using CS5504.

I

i

..,--- ._._...............
..........
issued to the converter only after the DG303
switch has been switched to one position long
enough for the buffer amplifier to have settled
on the signal. With the DG303 in one position,
the output of the amplifier will result in a
positive voltage into the converter; when
switched to the other position the output of the
amplifier will be negative into the converter.
The negative reading is then subtracted from the
positive reading and then divided by
two[(+answer - (-answer)]/2. The result will be a
reading of the load cell signal with the offset of
the amplifier removed. For example, let us
assume the circuitry has +332 counts of offset
and the signal from the bridge (the bridge itself
has no offset for illustration purposes) should be
4700 counts. The reading from the converter
with a positive input signal will be 5032 counts;
the reading with the signal reversed will be
-4368 counts. [5032 - (-4368)]/2 = 4700 counts,
which is the answer with the offset averaged out.
Note that dividing by two is really unnecessary
as the number (9400) is representative of the
signal magnitude. The converter can sample at
200 samples per second; performing a
conversion every 5 msec. The converter has two
channels but needs not to measure the
temperature
channel
very
often.
The
measurement sequence for channel one is
follows: Switch the DG303 to condition one
(switches 1 and 2 are on, switches 3 and 4 are
off); perform a conversion but throw the data
away as this conversion time is used to allow the
amplifier to settle (the circuit shown takes less
than 4 msec. to settle). Then perform a second
conversion and keep the data. Switch the DG303
to condition two (switches 3 and 4 are on, 1 and
2 are off); perform a conversion but throwaway
the data to allow for settling. Then perform a
second conversion, subtract the negative answer
from the previous positive one (from switch
condition one) and divide the answer by two (if
you need the actual answer). Since it will take
four conversion cycles to obtain one averaged
answer, the converter will be able to update at a
50 Hz rate (assuming the temperature channel is
5·38

Bridge Transducer Digitizer Circuits

not being read). The effects of noise in the
output data can be reduced if words are
averaged. An average of 20 of the final readings
will result in a noise reduction of 4.4 times.
Converting in this fashion will result in a
converter with greater than 150,000 noise-free
counts, and an update rate of about two and a
half times per second. Chopping the signal
lowers the input drift in the amplifier to about
125 nV peak-to-peak under slowly varying
temperature conditions.
Switched Bridge with CSSS04 Using +10 V
Analog Supply

The previous circuit achieved offset stability by
chopping the bridge output. In the circuit in
Figure 11 the polarity of the excitation voltage to
the bridge is periodically reversed. Channel one
of the CS5504 is used to measure the amplified
signal from the bridge. The second channel of
the converter is used to measure the magnitude
of the bridge excitation. The bridge excitation is
measured because the driver exhibits some
change in drive output over temperature. The
measurement sequence is as follows. For
notation let the bridge excitation be in position
one when the top of the bridge is +10 V (the
actual voltage will be about 9.5 to 9.8 V
depending upon the driver source impedance).
When switched to this position, the
microcontroller pauses for a short delay (1 msec
. or so) before performing a conversion on
channel two to ensure that the circuit has settled.
Once the conversion is performed on channel
two, the data is saved. Then the AO line to the
converter is switched to select channel one. The
amplifier has settled during the time the
conversion was performed on channel two. A
conversion is performed on channel one and the
data is saved. Then the bridge excitation is
flipped to position two ( the top of the bridge is
grounded). After a 1 msec delay a conversion is
performed on channel two; the negative answer
is subtracted from the previously collected
positive answer from channel two. Then AO on
AN31REV4

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....

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VREF+
XIN

330 kHz
OSC

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t

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1 AIN2+
CALH
_

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100
8

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49.9k

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20 bits

SCLK

SDATA
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Transducer

604

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DRDY

6

1

1

49~
10

0.1

y

20

System
Microcontrolier

m

AIN1-

:::!.
CONV

VA-

2

19

2

+10

40· Conversions/sec
before averaging

118

CS

100

1

.7

BP/UP

I AIN2-

+

Ii'!,I....,.
'.

- 1

AO

DGND

I.

1.-

13

Q,

~

-t

iil::J
1/1

Q,

c

...2

+110

c

cC'

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~.

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MIC4428
or
MIC4425

o

~.

c

~
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Figure 11. Switched Bridge with CS5504 Using +10 Volt Analog Supply

I

;:

_.....
......_.
_..,.
............
.."

Bridge Transducer Digitizer Circuits

".,

the converter is flipped and a conversion is
performed on channel one of the converter. The
negative answer for channel one is then
subtracted from the previous positive reading
from channel one.
The resultant readings from each channel can be
averaged to reduce the effects of noise. Then the
readings from the two channels are ratioed. The
channel two data represents the value of the
excitation on the bridge. Channel one data
represents the output signal from the bridge as a
proportion of the bridge voltage. By ratioing the
data (AIN1/AIN2) any drift in the bridge

excitation voltage (such as those caused by
changes in the driver output impedance) is
compensated.
The circuit can read both channels and calculate
a final answer for the bridge signal in less than
25 msec.; which means an output word can be
calculated at a rate of 40 times per second. If 20
output words are averaged the circuit will yield
better than 100,000 noise-free counts with the
offset drift of the digitizer being less than 50 nV
over time.

+5

+5

VREF+
XIN
VREF13

.2k

9

1k

CAL

500
2k

AIN2+

=3.33V

1k

7

11

BP/UP

AIN2-

>::-""T~----'iN\r-""T--I AIN1+

CS5504
20 bits

18
SCLK

SDATA

19

2mVN
Transducer

0.005
DRDY

-

CS
10

40 Conversions/sec
before averaging

2

CONV
VA-

2k

System
Mlcrocontroller

AIN1-

100
+5
-5

20

AO

DGND

15

10k
0.1

+ 10

T-5
MIC4428

-5

Figure 12. Switched Bridge with CS5504 Using ± 5 Volt Analog Supplies.
5-40

AN31REV4

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"...,
4.096 MHz

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MIC4428

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....

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R3

R2

;

t

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:t:

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- ~

CS5516
CS5520
16 or
20 bits
-- -------- -~ ---- --

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Filter

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D.

ca
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-t
iil
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10
50 Conversionslsec before averaging

~0.1

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C

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Figure 13. CDBSSl6120 Evaluation Board Circuit.

I

i

_-

..,.... ....
...
....... ....

..,..,~.

.."

~

.."

Switched Bridge with CS5504 Using ± 5 V
Analog Supplies

This circuit in Figure 12 is basically identical to
the previous circuit, but is configured to run
from ± 5 V on the analog supplies.
CDB5516/20 Evaluation Boar:d Circuit

The CDB5516 and CDB5520 evaluation boards
use the circuit in Figure 13. The CS5516 (16-bit)
and CS5520 (20-bit) converters are optimized
for bridge measurement applications. The
evaluation board comes with software which
runs on a PC-compatible c;omputer. The
evaluation board includes a microcontroller
which communicates with the PC ~ia the RS-232
serial port. The software allows the' user to read
and. write all of, the .registers inside the
<;:S5~16/20 convertet, perform conversions, save
conversion data to a file, and perform some
noise statistics on the captured data.
The: CS5516 and CS5520 support both
dc-excited bridges and ac-exCited bridges.
Figure 14 illustrates the benefit of AC excitation ..
In one of the plots in Figure 14, the CS5520
converter was set up for a bipolar input span of
± 12.5 mV and dc bridge excitation.
Conversions were performed with a zero input
signal from the bridge and data wa,s ~ollected for
a one hour time interval. One LSB of the
CS5520 was equivalent to about 25 nV. The data
collected indicates that over the one hour period
the average value of the data drifted as much as
1.25 J.lV, or about 50 counts. The drift is due to
parasitic thermocouples in the components or
wiring of the board. The evaluation board was
open to the air. The data illustrates that the
cycling of the air conditioner induced thermal
gradients across the circuitry, changing the
voltage effects of the parasitic thermocouples in
the circuitry. The second plot in Figure 14
illustrates the stability of the data when the
converter is set up for the same operating
5-42

;,~.~.

• .,.

'

'

,
(1(.:,',:,. . . ,"

.

Bridge Transducer Digitizer Circtlits '

conditions, but with ac bridge excitation. The
plot illustrates the normal thermal noise of the
circuit but the average value remains stable over
time.
The CS5516 (l6-bit) and CS5520 (20-bit) NO
converters include an instrumentation amplifier
with X25 gain, a PGA (programmable gain
amplifier) with gains of 1, 2,4, and 8, and a four
bit DAC which can trim out offset up to ± 200%
of the full scale signal magnitude. The input
span can be adjusted by «hanging either the
magnitude of the voltage at the VREF pins of
the converter or by changing the PGA gain.
In the circuit shown in Figure 13, the bridge is

excited with a 1 kHz square wave from the
MIC4428 (or the Micrel MIC4425) driver. The
driver outputs about ± 5 V. The 1 kHz drive
signal is output from the BX2 pin of the
CS5520. Control bits in a configuration register
inside the chip have been set to select internal ac
excitation with a frequency of 1 kHz (XIN =
4.096 MHz). The converter is designed to
perform synchronous detection on the AIN and
VREF input signals when operated in the ac
excitation mode. This means that the converter
measures the signal which is of the same
frequency and phase as the excitation clock
coming from the BX2 pin.
ReSistors Rl, R2, and R3 divide the excitation
voltage to give a 2.5 V reference signal into the
VREF pins. The input span at the AIN pins of
the converter is determine.d by dividing the
'voltage at the VREF pins by the PGA gain and
the X25 instrumentation amplifier gain. For
example, with 2.5 V into the VREF pins, and the
PGA set to a gain ,of 8, the input span at the
AIN pins is 2.5/(8 X 25) = 12.5 mV in unipolar
mode or ± 12.5 mV in bipolar mode. The
converter offers several calibration features to
remove offset and to adapt the gain. The
nominal input span of 12.5 mV can be gain
calibrated for input signals within ± 20% of
AN31REV4

.. ......
. --. ...
.....
~.-

~~

~~

Nanovolts

..,.

Bridge Transducer Digitizer Circuits

DC Excitation
Time Domain Data

Nanovolts

1250

AC Excitation
Time Domain Data

1250

- -:- - -: - - ~ - -:- - -: - -:-11 LSB =25 nV I
- -.- -.- - -.- - -. - -.- '------;-,---;--'

1000
750

~

1000

- -: - - -:- -

750

- -,- - -, - - r - -,- - ., - - ,-

I

,

- -: - - -;. <-I1LSB = 25 nV

I

I

I

500

500

250

250

0

0

·250

·250

·500

·500

·750

·750

-

-'-

-

-' -

-

'.

-

_,-

-

-'

-

-

'.

·1000

·1000

-

-,-

-

-,

-

,-

-

-,-

-

",

-

-

I·

-

I-

I

-

-

.'.

-

..!

-

-

'-

-

-,-

-

-,

-

-

j

--

-

·1250

·1250
0.00

1.00

0.50
time (hours)

0.00

0.50
time (hours)

1.00

Figure 14. DC Versus AC Excitation.

nominal. In other words, the gain can be
calibrated for an input as low as 10 mV or as
high as 15 mV when the nominal value is set for
12.5 mV. The nominal input can be changed tly
changing the PGA gain or by changing the
divider resistors for the excitation voltage. The
converter can accept a VREF input voltage of
any value between 2.0 to 3.8 V. The CS5516
and CS5520 can be operated on any clock
frequency from 1.0 MHz to 5.0 MHz. The
digital filter will give greater than 90 dB of
attenuation to 50 and 60 Hz line interference if
the input clock is 4.096 rnHz or less. With a
4.096 MHz clock into the converter it will
output conversion words at a 50 Hz rate. For
optimal filtering it is desirable to average output
words from the converter. If ten output words
are averaged, the noise bandwidth is reduced to
about 2.5 Hz.

oscillator frequency on the chip and is output
from the BXl and BX2 pins. In the external
excitation mode (selected by setting a bit in the
configuration register of the converter), a square
wave whose frequency is a sub-multiple of the
XIN frequency to the converter (see the
CS5516/20 data sheet for details) is input into
the BXl pin of the converter.

CS5516 with External 25 Hz AC Excitation

When using the CS5516 or CS5520 in the ac
excitation mode, the AIN and VREF signals into
the converter are sampled 64 XIN clock cycles
after the excitation signal is switched. When the
square wave excitation changes polarity, the
circuitry, including the bridge, the load cell
cable, and any filtering components must settle
to at least 5 per cent accuracy within the 64 XIN
clock cycles after the switching edge. This can
be a limiting factor in using square wave ac
excitation, especially with long cables which
have a large capacitance.

The CS5516 and CS5520 support two ac bridge
excitation modes; internal and external. In the
internal excitation mode, the excitation clock is
derived internal to the converter from the

The excitation frequency can be lowered to
XIN/(lO X 214) if output words from the
converter are averaged over several conversion
cycles. For example, with a 4.096 MHz clock, a

AN31REV4

5-43

..

...,-.,-.-..
....
..,""" .....
..,..,~

Bridge Transducer Digitizer Circuits

decade divider (74HC4017) can be followed by
a binary 214 divider (74HC4020) to yield a
25 Hz excitation frequency. The converter will
output conversion words at a 50 Hz rate, or two
output words for each one cycle of the bridge
excitation. The 25 Hz excitation reduces the
switching frequency of the bridge so the circuit
spends more time . measuring . and less time
settling. This will improve measurement
performance, but multiple output words (an even
number of them) must be averaged to ensure

equal samples for both polarities of the
excitation clock.
Figure 15 illustrates this
circuit. Note that the details on connecting the
clock divider chips have not been shown to
simplify the schematic.
CSSS16/CSSS20 with AC-Excitation
Controlled by a Microcontroller
If the load cell cables are very long, the
capacitance may be so large that the circuit
cannot settle .and yield an accurate result with
the 25 Hz circuit. Another option exist. Rather
than use the counters in Figure 15 to control the
BXl signal and the drive polarity, one can use a
microcontroller output line. With the converter
set up in the external excitation mode, the
microcontroller can control the polarity of the
4.096 MHz

+10

+5

XIN
MICREL
MIC4428

25Hz

7

BX1
Bridge
Sync

BX2

5

CS5516
CS5520
~~_~r.~O_~i~~ _~________ _

See Text
for another
control option.

VREF-

301

+

'--_ _---'Ac::I:.:N+-'-¢------->I +
AIN301

25X

Gain
Block
1,2.4,8

~ 4.7nF

25 Conversions/sec averaging required

Figure 15. CS5516 with External 25 Hz AC Excitation.
5-44

AN31REV4

.... ......,..... ...........
~

...,

~~

~~

excitation. In external excitation mode, the BX1
pin of the converter is an input and is used to
determine the polarity of the excitation. The
phase of the signal at BX 1 controls the phase of
the internal detection circuitry. Each time the
polarity of the excitation is changed, the
converter needs six conversion word periods for
the internal digital filter to accurately settle on
the input signal. To yield a proper result, the
sixth conversion word for each of the excitation
phases will need to be averaged together. For
optimum throughput, the excitation polarity
should be changed when the DRDY signal falls.
The on-chip calibration features may not be
usable directly when operating in this manner,
but the user microcontroller can manipulate the
gain and offset registers in the converter to
optimize the the offset and gain adjustments for
optimum operation. If the bridge polarity is
reversed every six conversion words, an output
result can be computed every twelve filter
cycles. This will yield an effective conversion
update rate of about four updates per second
(XIN =4.096 MHz).

CS5516 or CS5520 and a 1 mVIV
AC·Excited Load Cell
Metal film or metal foil strain gages are
generally configured to yield a sensitivity of
2 mVN or 3 mVN from a load cell. A load cell
may be used at 112 or 1/3 its rated capacity to
allow it to have greater overload capacity. A
designer may trade sensitivity for overload
capability. For example, using a 2 mVN load
cell at 112 capacity yields a 1 mVN sensitivity,
but with greater ruggedness. The lower
sensitivity results in less output signal for a
given excitation. The usable portion of the
output signal may be further reduced because the
load cell may be part of a system where the pan
weight consumes a good portion of the signal
span of the load cell output. For example, a scale
designed to weigh 10 Kg (22 lbs.) may have a
pan weight which weighs 5 Kg. (11 lbs.) and
therefore the pan weight consumes half of the
AN31REV4

Bridge Transducer Digitizer Circuits

signal span out of the load cell. The application
may require protection against high impact, such
as when the items being weighed are dropped on
the scale. A 2 mVN load cell may be derated
which results in lower output sensitivity
(1 mVN or so) to allow greater impact capacity
for the load cell.
Figure 16 illustrates such an application. The
signal to measured from the bridge is only 5 mV
over the measurement range (the pan weight
consumes 5 mV of the load cell span). The
of
the
offset
calibration
capability
CS55l6/CS5520 converter can readily remove
the offset due to the pan weight. If the converter
was configured to measure the 5 mV signal
without the additional buffer amplifier, the 5 mV
signal would only use part of the converter's
span. For example, if the VREF voltage is
reduced to 2.0 V and the PGA gain inside the
converter is set to 8, the input span expected by
the converter would be 2.0/(25 X 8} = 10 mY.
To calibrate the converter with only a 5 mV
signal would force the gain register to a value
outside the recommended range (1.2 to 0.8).
This situation can be overcome by using an
external buffer amplifier made up of two OP-27
op amps. The VREF voltage for the converter is
set to 3.33 V by using three equal resistors for
Rl, R2, and R3. The PGA gain is set to 1 which
makes the input sensitivity at the AIN pins of
the converter to be 3.33/(25 X 1} = 133 mY. The
buffer amplifies the usable portion of the load
cell output signal (5 mV) by a gain of 26 to
yield an input to the converter of 130 mY.
Stability of the gain resistors is important but
tight initial tolerance is not needed as the gain
calibration feature of the CS5516/CS5520 can
accommodate up to ± 20% gain scaling. AC
excitation removes the offset of the OP-27s.
The circuit is operated with the load cell excited
with a 1 kHz bridge drive frequency. When
operating in bipolar mode, the CS5516 converter
will yield about 27,000 noise-free counts over
5-45

_,'

t

''',=••
'·1""....,

0)

4.096 MHz

+5

MICREL
MIC4428

,=.,

....

7
5

.,.

-

.

CS5516
CS5520
16 or 20 bits

I

SMODE
SOD

-

SID

'">

IIN2

serial~

OUT2

Interface

2
Channel
FIR
Filter

2-Channel
Delta-Sigma
Modulator

OP-27

R5:;> 200
R6

INI

AIN-

OUTI

__
DRDY

(See Text)

CS
RST

DGND

<:: 2.5k

POST
PROCESSOR

...a:

-1:11
CD

CD

301

VA+I

-5

MDRV+

MDRV-

-I

VD+

iii~

+5

In

Q.

0.1~

10

~0.1

50 Conversions/sec before averaging

C

...n
CD

C

ii'
~

N

...CD
Q
c:J
c

)0

Z

Co)
~

XI

~

Figure 16. CSSS16 or CSSS20 and a 1 mVIV AC-Excited Load Cell.

if

_... .. ...._.-.
..,_ ..,..,_
..,..,

~--

the 5 mV span at a fifty samples per second
update rate. The CS5520 should be used if
higher resolution is desired at the 50 Hz update
rate. Averaging 25 samples will yield an output
with an effective 135,000 noise-free counts at
two updates per second; this on a 5 mV signal
span. The AIN ratiometric calibration register
inside the converter can be used to add or
subtract offset from the signal and give some
counts for zero weight underflow (if used in
unipolar mode) or some counts for full scale
overrange (if bipolar mode is used). Averaging
as many as fifty output words may be desirable
in some applications where mechanical vibration
is a problem.

CS5520 and an AC-Excited 1.9 mVN Weigh
Platform
Figure 17 illustrates another very high resolution
digitizer. A GSE model 4444 "floating beam"
platform is used as the weigh bridge. The model
4444 has a full scale capacity of 100 pounds and
a sensitivity of 1.9 mV/V. The full-scale output
signal from the bridge is (1.9 mV/v) X 9.5 volts
excitation or about 18 mY. The 18 mV output
signal is amplified by two LTI115 amplifiers
configured as a high input impedance buffer
amplifier with a fixed gain of 8. When the 18
mV signal is amplified by 8 it yields an input
signal to the converter slightly above the
nominal value determined by the voltage
reference. The calibration features of the CS5520
enable it to accommodate input spans which are
as much as 20 % above or 20 % below the
nominal value set by the reference voltage.
Vishay resistors (R4-R6) are used in the buffer
amplifier to maintain a stable gain over
temperature. The LT1115 was chosen for its low
noise while sustaining a loop gain greater than
one million. With a X8 closed loop gain, an
open loop gain of 138 dB must be maintained.
The operational amplifier must maintain its high
open loop gain with reduced supply voltages (±5
V) and with environmental temperature changes.
AN31REV4

Bridge Transducer Digitizer Circuits

A loop gain greater than one million ensures that
gain stability will be dictated by the gain-setting
resistors and not by limited loop gain. Offset
voltage, offset drift, bias current, and bias
current drift are unimportant when ac excitation
is used as these errors are modulated out-of-band
and filtered out by the digital filter inside the
CS5520. Thermal noise at the excitation
frequency remains as the limitation to achieving
high dynamic range. Although the LT1115 is a
very low noise amplifier, the noise in the
digitizer circuit is actually dominated by noise
referred to the buffer amplifier's input from the
ND. (Note that a lower cost amplifier such as
the LTl007 can be used with only a minor
increase (5%) in peak-to-peak noise). The effects
of the thermal noise can be reduced by averaging
output conversion words. With the digitizer
using the LTl115s for optimum performance,
you can capture output conversion words from
the digitizer and examine the noise content in the
50 Hz conversion words. You should capture at
least 1000 conversion words from the CS5520 to
have a large enough sample to minimize
statistical uncertainty. The input to the digitizer
should be held at a stable value while the
conversion words are captured. Once the
samples are captured, a frequency distribution of
the samples is computed and plotted.
Spreadsheets such as Lotus or Quattro can be
used to compute and plot the frequency
distribution of the data. Figure 18 illustrates the
histogram of 1000 50 Hz output samples from
the digitizer of Figure 17. The histogram
illustrates that the 50 Hz output words from the
converter have a peak-to-peak noise amplitude
which is less than 6 LSBs (least significant bits)
99% of the time. The noise in the output codes
has a Gaussian characteristic and therefore
averaging can be used to reduce its value.
Averaging samples which include Gaussian
noise will reduce the noise amplitude in
proportion to the square root of the number of
samples which are averaged together. The post
processor computes an average of 50 CS5520
output words to yield a post-filtered output word
5-47

.':

If'
~

''',

=,.
4.096 MHz

+5

Y

....

MICREL
MIC4428

7

CS5520
20 bits
1'-

-

I

SMODE

.-

SOD
SID

VREF+~+

GSE 4444
Floating Beam
Platform

VREF-

lX

'>

IIN2

2-Channel
Delta-Sigma
Modulator

301

Serial

OUT2

Interface

~
SCLK
DRDY

POST
PROCESSOR
(See Text)

CS

Channel
FIR
Filter

RST

350'
LT1t15
or
LT1007

R5 :;; 100'

AIN-

INl

OUTl

DGND

111m
...

c:

(Q

CD

301

MDRV+

MDRV-

...-I
III

VD+

::I
til

• VISHAY Sl 02K Series Resistors

Il.
C

10

;;,.s:

0.1

50 Conversions/sec before averaging

n

...CD
C

cc'
;::;:
iii"

...CD

0
:::0"
n

:J>

z

....

c

Co)

:II

m

~

;::;:

Figure 17. CS5520 and an AC-Excited 1.9 mVN Weigh Platform.

,

"~I
""
.....
="

til

.... ...
.....,
. ....,,-._.
~

..,

~~

Bridge Transducer Digitizer Circuits

~~

400,--------------------==---------------------,
1000 Conversions
1a =1.07 LSB
Average =0.035 LSB
300

en
w
u

249

Output word - - - - - - rate =50/second

Z



200

U
U

o
100

4

1

O~'---==~~~~-=~~

-4

-3

-2
-1
0
1
2
OUTPUT CODE (1 LSB =34.3 nV)

3

4

Figure 18. Noise Histogram of 1000 Conversions.

2.0

~--------------------------------------------~

1 LSB = 34.3 nV

-

1.0

•

U)

CO

CJ)

....J

W

CJ)

0.0

5z
-1.0

-2.0

+------------,------------j

0.0

0.5

1.0

TIME (hour)
Figure 19. Digitizer Stability Over One Hour.

AN31REV4

5-49

I

__ _

..--_
.-.-,.,.....
....
......

Bridge Transducer Digitizer Circuits

rate of 1/second. Averaging 50 words reduces
the noise by ...J5Q, or by a factor of 7.07. Since
the standard deviation, or rms value of the noise
illustrated in Figure 18 is 1.07 LSB, the rms
output noise in the post-filtered samples will be
1.0717.07 = 0.151 LSB rms. You can use the
rule of thumb that peak to peak noise is
approximately 6 to 6.6 times greater than the
rms value to predict the peak-to-peak noise in
the post-processed output words. This. results in
a peak- to-peak noise in the post-filtered output
words of less than ±1 LSB for greater than
99.9% of the post-filtered output words.

this configuration the digitizer can accurately
digitize an overrange signal, even up to 195% of
full scale.

To illustrate the dc stability and noise of the
post-filtered output words over time, the 1 Hz
post-filtered output words were collected for a
period of one hour. Note that for this test the
input to the bridge amplifier was removed from
the load cell and tied to ground through two 350
ohm resistors. This eliminates the load cell's
sensitivity to vibration when studying the
digitizer input noise characteristics.

Digitizer Noise And Averaging

Figure 19 illustrates the peak-to-peak noise of
the digitizer over a one hour period. The plot
indicates that the drift and noise are less than
±1 LSB for more than 99.9% of the output
samples over the hour long period. This is
superb performance and illustrates the benefit of .
synchronous detection. Figure 18 and Figure 19
indicate that the 50 Hz output data from the
converter can averaged to yield a 1 Hz update
rate which is stable to 1 count in ±524,000 when
the converter is set up for bipolar mode. The
CS5520 includes a DAC and a ratiometric offset
register which can be used to offset the span in a
negative direction by 500,000 counts. This
allows the weigh scale to have 24,000 counts of
underrange to accommodate any zero drift or
creep in the load cell. The measurement span for
the 18 mV load cell output would be over
524,287 counts, but above this would be another
500,000 counts which would allow the digitizer
to accurately measure overranged weights. In

Investigating the noise performance of the
digitizer should begin in the design phase.
Analysis should yield an estimate of the amount
of noise in the circuit. This discussion will not
focus on the analysis but will instead be limited
to evaluating the noise in the digitizer circuit.

5-50

The GSE 4444 platform has mechanical stops
which activate at approximately 120% of
capacity, so the synchronous detection weigher
will yield a noise-free 19-bit measurement, with
a 20% overrange capacity. If the digitizer was
used with a tension-compression load cell such
as the BLH Electronics model LPT,. the digitizer
would yield better than ±500,000 noise-free
counts.

As illustrated in the previous example circuit, it
is good practice to evaluate the performance of a
prototype digitizer. While many measures of
performance should be investigated (linearity,
stability over temperature, etc.), one of the
primary factors which limits measurement
resolution is noise in the digitizer circuit itself.

One simple method of evaluating digitizer noise
is to "ground" the input and collect enough
samples to evaluate the noise statistically.
"Grounding" the input involves connecting the
signal + and signal - leads of the digitizer input
amplifier to a quiet node which has a voltage
equivalent to the common mode output of the
bridge to be measured. In a system with load cell
excitation of +5 V and -5 V the inputs can be
tied to ground. If the load cell is excited with a
single supply ( for example, +5 V or +10 V), a
quiet source with a common mode voltage
compatible with the input of the amplifier should
be generated. For example, if the circuit runs on
AN31REV4

... .. ...
._.-.
~~~..,~-

..,

~~

a single +5 V supply, use two 100 ohm resistors
connected in series between +5 V and ground.
Then connect the input of the digitizer circuit to
the 2.5 V node of the resistor pair. While a load
cell simulator may be used in many
circumstances, this can be a source of some
problems. Some simulators exhibit lIf noise
which can adversely affect the data output from
a high resolution digitizer. And some simulators
may not work well with the circuits which use
ac-excitation. This is because some simulators
use switches which rectify the ac excitation
signal; therefore the actual signal to be measured
is corrupted. This can result in greater noise than
expected as well as a dc offset error.
The biggest difficulty in evaluating the noise
performance of a circuit is that some means of
getting the data out of the digitizer and into a
computer must be designed into the circuit. For
the CS5504/516n18/9 devices this can be
accomplished by making the SCLK, SDATA
and DRDY signals available on a header. The
CDBCAPTURE system from Crystal has a
standard 10 pin (two rows of 5 pins) stake
header
which
can
interface
to
the
CS5504/516n18/9 products and capture data from
these converters. Alternatively, a designer may
include some other type of interface in his
system to port data to a PC-compatible computer
via the serial or parallel port.
Once an interface is available, it is a matter
collecting enough conversion words to perform
meaningful statistical analysis on the data. The
CDBCAPTURE system enables the user to
capture data from the CS5504/516n18/9 and to
produce noise histograms. The CS5516 and
CS5520
are
not supported with the
CDBCAPTURE system, but the CDB5516 or
CDB5520 evaluation boards can be configured

AN31REV4

Bridge Transducer Digitizer Circuits

to collect data from these chips. Once data has
been collected into a file on a computer,
spreadsheets such as Quattro, Lotus, or Excel
can be used to analyze the data using a
frequency distribution function and statistical
functions. The data should also be plotted as
shown in Figure 18 to give the user an indication
that the data actually follows a Gaussian
(Normal) distribution. Thermal noise will have a
"bell-shaped" histogram. If the data words
represent thermal noise, one standard deviation
is equivalent to the rms noise; while 99.9% of all
the data should fall within ± 3.3 standard
deviations of the mean. Therefore the peak-to-peak
noise is approximately 6.6 times the rms noise.
When performing statistical analysis on a
digitizer's output, at least 500 to 1000 conversion
words should be included to lower statistical
uncertainty to an acceptable level.
Once the rms noise is known (by calculating the
standard deviation of the data set), averaging can
be used to improve system resolution if it has
been confirmed that the noise follows a Gaussian
distribution. Data may not follow a Gaussian
distribution because it includes interference due
to dc-dc converters or to clock coupling which is
picked-up by the sensitive analog circuitry. In
this case averaging output words may be
deceptive.
Averaging
will
reduce
the
peak-to-peak noise but the mean can be
adversely affected by the interference which is
included with the signal.
One additional noise test is to measure noise
over the entire input span of the converter. If
noise increases with higher signal amplitudes, it
suggests the voltage reference input to the
converter is excessively noisy.

5-51

--

.. ...
. ..,--.......
....
~-

~~,..

~~

Bridge Transducer Digitizer Circuits

Aliasing Considerations

The circuits depicted in figures 5, 6, 7, 9, 10, 11
and 12 use the CS5504/516nJSI9 as a sampling
converter whose input is not bandlimited. This is
acceptable if the bridge output signal is a static
(dc) signal. If the bridge output includes ac
signals with frequencies above the effective
nyquist rate of the sampler, aliasing may occur.
This can degrade performance.
Conclusion

The circuits in this application note were
designed, constructed, and tested with the intent
of illustrating a wide variety of bridge digitizer
solutions.
The circuits demonstrate various
power supply arrangements and various levels of
measurement resolution; all with the intent of
helping designers understand the flexibility of
the AID converters which have been used.

5-52

AN31REV4

......
.
.... .....
. " ..
"
•. "1IIIJr _ _
.~
..

AN32

."."

Semiconductor Corporation

Application Note
CS5516 and CS5520: Answers to
Application Questions
by
Jerome Johnston

What determines the inpnt span for the
converter?
The input span of the CS5516/CS5520 AIN
input signal is determined by a combination of
the instrumentation amplifier gain (X25), the
programmable amplifier gain setting (1,2,4 or 8),
and the magnitude of the voltage between the
VREF+ and VREF- pins. The voltage into the
VREF pins can range from 2.0 to 3.8 volts and
is determined by the resistor divider ratio
selection of the resistor network which divides
down the bridge excitation voltage.
The
CDB5516 and CDB5520 evaluation boards
come with resistors which divide the excitation
supply (nominally 10 volts total) down to 2.5
volts between the VREF+ and VREF- input pins.
This 2.5 volt reference input is divided by the
PGA gain setting and by the X25
instrumentation amplifier gain to determine the
nominal full scale input span to the converter.
For example, if the PGA gain is set for a gain of
8, then the input span to the instrumentation
amplifier will be 2.5 volts (VREF+ - VREF-)
divided by 8 X 25, or 2.5/(200) :::; 12.5 mV
nominal in unipolar mode, or ± 12.5 mV
nominal in bipolar mode. The specified
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX 445-7581

calibration range is ± 20 % of nominal, therefore
the device can be gain calibrated to handle a full
scale input from a low of 10mV (20% below
12.5 mY) or to a high of 15 mV (20% greater
than the 12.5 mV nominal). To modify the input
span, the user can either change the PGA gain
setting or modify the resistor divider ratio on the
bridge sense voltage which determines the
VREF input voltage.
What happens if the full scale span is greater
or less than the nominal full scale span by
more than ± 20 %?
The calibration range of the gain register spans
from 2- 23 to 2.0 in decimal, and the converter
can calibrate with inputs as great as ± 50% of
the nominal value, but missing codes can occur
in the output transfer function if the calibration
range is extended. The intent of the ± 20 %
calibration range specification is to insure proper
code computation with no missing codes in the
output transfer function, and that the analog
signal does not saturate any portion of the signal
path inside the device (see later discussion on
the block diagram model of the converter).

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JAN '95
AN32REV4
5-53

.. ...
.-..--._.-.
~.-

~~~

~~

The resistor values shown in the data sheet
for the excitation divider are too low in value
and may cause gain error due to excessive
loading of the excitation signal when used
with remote transducers. How large can
these resistors be?
The original data sheet showed the VREF
divider resistors as 750 and 500 ohms. The
current data sheet indicates these as 7500 and
5000 ohms if the associated filter capacitor is
reduced to 470 pF. The AIN and VREF inputs to
the converter are both switched-capacitor inputs.
The RC-time constant associated with the inputs
on the VREF+ and VREF- pins, and on the
AIN+ and AIN- pins, should be such that the
capacitor sampler settles to full accuracy in a
saplpling period. Figure 1 illustrates a simplified
model of each of the pins for VREF+, VREF-,
AIN+ and AIN-. The input has a dynamic
current requirement based upon charging a
sampling capacitor. The input current is a
function of the sampling capacitor, the sampling
clock, and the offset of the buffer. The offset of
the buffer will not exceed 25 mV over the -55 to
+125°C temperature range. Using this model,
one can determine the value of the dynamic
current and the effective input resistance. The
model can be also be used to compute the errors
contributed by external source impedances.

Answers to Application Questions

current when the converter is operated with XIN
=4.096MHz.
in = Voifcs = (25mV)(4.096MHz)(0.5pF) = 52nA

The application note Switched-Capacitor AID
Converter Input Structures explains the input
current effects of the sampled capacitor circuit.

Can you provide an example of how the sense
lines from a transducer can be buffered to
reduce the loading effect of the reference
divider resistors?
The sense lines from the bridge can be buffered
as shown in figure 2 or figure 3. The drift in the
amplifier offset is referenced to the VREF
voltage, not to the input span of the converter
and therefore will have a negligible effect on
gain accuracy.
+15

VREF+
CS5516

CS5520
VREF-

For example, the input current required by the
AIN+ pin should be about 52nA plus leakage
Figure 2. Using Op Amps to Buffer Sense Lines.
~---+---1+

>----'-----,-------------oiIN2

2-Channel
FIR
Filter

OUT2

-------<-----1
BXl

SOD

BX2

SID

XIN

XOUT

SMODE SCLK

Figure 4. AID Block Diagram Indicating Signal Path Limitations.
AN32REV4

5-55

..........,..
......,.-.....
...............
~

Answers to Application Questions

How does the XIN clock frequency affect the
tilter bandwidth?
The CS5516/CS5520 can be operated with any
crystal between 1.0 MHz and 5.0 MHz with
corresponding changes· in the digital filter. The
digital filter inside the converter is optimized to
provide a very deep attenuation notch (-140 dB)
at 50 Hz when using a 4.096 MHz crystal or a
very deep filter notch at 60 Hz when operated
from a 4.9152 MHz crystal. The device can be
operated at other frequencies and still attain very
good rejection (90 dB) attenuation at both 50
and 60 Hz. Figure 5 illustrates the magnitude
plot of the digital filter. Note that the entire filter
transfer function scales with a change in clock
frequency. At frequencies above the first notch
frequency, the out-of-band attenuation will be at
least 90 dB for frequencies above the filter
cut-off but below the modulator sampling
frequency (XIN/256).

What is recommended if I need narrower
bandwidth than provided by the on-chip
digital tilter?
The CS5516/CS5520 were designed to give high
update rate (50 Hz with XIN =4.096 MHz) with
a 25 Hz usable bandwidth. The filter is designed
to settle in less than six output words when the
input changes in a transient manner. It is
desirable in many weighing applications that the
circuit have very low bandwidth (typically 1 to 4
Hz) to eliminate scale resonances and vibration.
To accomplish this type of bandwidth with the
CS5516/CS5520, the user should average several
output words. Averaging 10 output words (XIN
= 4.096 MHz) will result in a -3 dB filter
bandwidth of about 2.5 Hz. This filtering was
not included on the chip because many weigh
scale designers prefer to design their own
"adaptive" filter which can settle fast when the
input signal changes in a transient manner, but
implement more attenuation as the signal begins

0
·20
,
. - - -' - ,

-40

,
,
,
,
(1)XIN = 3.579 MHz
- '- - - - -, - - - - '- - - - " - - - - (2) XIN = 4.096 MHz
,
,
,
,
(3) XIN =4.915 MHz

ill ·60

:!:..

'"

"'C

~

·80

.:::

C>

as

::::;: ·100

·120
·140
·160
0
0
0

21.8
25
30

43.7
50
60

87.3
131.0
100
150
120
180
Input Frequency (Hz)

174.7
200

240

218.5
250
300

Figure 5. Filter Response at Various XIN Frequencies.

5-56

AN32REV4

,.,,.,....
.,.,..,....
.......
....
,.,,.,
....,
to settle. To accomplish this, use the 50 Hz
update directly when the data suggest that the
input signal is changing at a rapid rate (weight
has just been placed on the scale). Then switch
to averaging once the signal has settled to within
a specified error band; typically some band
slightly greater than the peak-to-peak noise of
the signal. The exact requirements of the
adaptive filter function will be dictated by the
application; particularly the mechanical response
of the weighing system.
The CDB5516 and CDB5520 evaluation boards
include software which allows the user to read.
and write all registers in the converters, collect
conversion data, perform averaging, save data to
a file, and compute the standard deviation (one
standard deviation is equivalent to the rms noise
for gaussian type noise). The evaluation board
may be of assistance in evaluating the amount of
averaging to perform in your circuit.

Should I use a series or parallel type crystal?
Either crystal will work. Series or parallel
designates the electrical configuration in which
the crystal was calibrated. The CS5516/CS5520
converter uses a parallel configuration (Pierce
oscillator). If a series crystal is used, it will
oscillate reliably but its frequency will be
slightly different than that of a parallel cut
crystal (typically within 0.03% of the same
frequency).

The converter seems to lock up or not
respond to calibration instructions. Any
suggestions?
When the device or the serial port is reset, the
port is waiting for a command. Inside the port,
there is a pointer register which counts SCLKs
to keep track of whether the information being
moved through the port is to be interpreted as a
command or as calibration register data. After
the converter is reset, the pointer will count the
first 8 SCLKs and accept the data bits associated
AN32REV4

Answers to Application Questions

with these as a command. The pointer then
counts the next 24 SCLKs and interprets the data
bits associated with these as register data. The
SCLKs must start low, transition high, and then
return low to be counted properly. Problems can
arise if the CS is released (returned high) before
the falling edge of the last SCLK. The pointer
will get confused and begin recognizing the bits
of the commands words as data bits or vice
versa. So watch your SCLKs.
When the CS5516/CS5520 is interfaced to a
microcontroller, it is sometimes difficult to
discern whether the converter is actually
receiving commands. A simple way to assess
whether the interface is working properly, is to
reset the converter and then to transmit one
88(H) command (read conversion data) to the
serial port. Do not attempt to read the data
output, instead, use your oscilloscope to see if
DRDY (pin 15) starts toggling. DRDY should
start toggling if the interface is working
properly.
When the converter is put in the read conversion
data mode, it will output a conversion data word
to its serial port register every 81,920 XIN clock
cycles. Therefore, 81,920 XIN clock cycles
elapse between DRDY falling, but the user must
read the conversion data within 51,000 XIN
clock cycles after DRDY falls. After the 51,000
XIN period, the converter is using its internal
bus to perform calculations and to move data
between registers. If a read is attempted during
this time, the internal data bus can experience
contention, which can cause the bus to lock up.

When reading the conversion data I get aU
zeroes no matter what the analog signal is.
Please explain why.
Check your voltage reference between pins 9
and 10 (VREF+ and VREF-). If this voltage is
zero, the converter will compute all zeros for the
output conversion data. Remember an AID
converter computes a digital word which
5-57

_

_
.
...........
..,
.....
_.
...,.....

.."

.."

represents the ratio of the input signal to the
voltage reference. If the voltage reference is
zero the output will be zero.

The conversion data out of the converter
changes as the input signal changes, but is
never correct. Any suggestions?
When the converter is configured for external
bridge excitation, the BXl input pin determines
the phase of the internal detection circuitry for
the AIN and the VREF input signals. For
external dc excitation, the BXl pin should be
pulled up to +5 volts through a 10 k resistor to
insure the proper phase of the input signals.
If ac excitation is used, be certain that the phase
of the signals into the VREF and AIN pins is in
phase with the BX2 signal. If either of the
signals is not in phase with the BX2 signal the
converter will not' compute correct conversion
data.

Is calibration required to use the converter?
Must
non-ratiometric
calibration
be
performed?

Answers to Application Questions

calibration, ratiometric offset calibration, and
gain calibration. The converter can perform
conversion without any calibration being
performed. Just because the calibration feature
is available does not mean the feature must be
used. The user's application should dictate if
calibration should be used to remove specific
errors. It may be quite acceptable in a given
application to not use the non-ratiometric
calibration features of the converter. The user
can evaluate the magnitude of the error source
and its effects on the resulting conversion data
by either analysis or by empirical investigation.
The application note Overcoming Errors in
Bridge Measurement discusses the various error
sources and their contribution to the final error
in the output data. Often the user can use the
CDB5520 evaluation board to investigate these
errors. The CDB5520 comes with PC-compatible
software which allows the user to perform
calibrations and read all of the registers in the
converter. Once the calibrations are performed,
the magnitudes of the numbers in the registers
indicate an estimate of the magnitudes of the
errors which have been calibrated.

How often do I need to recalibrate?
When the CS5516/CS5520 is reset, the registers
are set to known values. If the signal to be
measured by the converter is within the nominal
range, the converter can perform conversions
without the need for calibrations. Some users
apply their own calibration scheme using
software and registers in their microcontroller.
After being reset, the CS5516/CS5520 will
convert on the signal being measured. The only
limitation of not using the converter's calibration
functions is that the errors in the system remain
present. This may be acceptable if the errors are
insignificant to the measurement or if the errors
are removed by some other means, such as
software in the user microcontroller.
The CS5516/CS5520 offers a complete set of
calibration features; non-ratiometric offset
5-58

To answer this question one must ask: 1) What
accuracy is required from the AID converter? 2)
What effects will temperature changes have upon
the entire circuit, including components outside
the AID? Once power is applied to the converter,
it will take about a minute for the chip to reach
thermal equilibrium. It is best if calibration is
performed after the chip has reached this stable
operating temperature.
A higher accuracy measurement requirement will
generally require calibration to occur more often,
because, after the initial calibration has been
performed, the converter is subject to some drift
if the operating temperature changes. Typical
offset drift (± 0.005 J..lVfOC) and gain drift (1
ppm/DC) are given in the data sheet tables. The
AN32REV4

. .",--- ....
~" • •I8f1I8f1I111111 •

Answers to Application Questions

. . ,• •18f118f1 . . .. .

observed drift in the application circuit may be
considerably
greater
due
to
parasitic
thermocouple effects and. gain drift caused by
the limited tempco tracking of the VREF divider
resistors. Once an estimate of drift is determined
for the entire application circuit (drift will
usually be dominated by error sources external
to the converter), one can assess how this will
affect measurement accuracy as temperature
changes. Once the amount of drift is known, it
can be determined if a new calibration is
required. Using AC-excitation removes the
effects of parasitic thermocouples and offset
drifts and therefore will require less recalibration
as the operating temperature changes.
The CS5516/CS5520 has been subjected to 1000
hour burn-in at 125°C to investigate the effects
of aging. The converter was tested with a full
scale signal using AC excitation mode with
maximum PGA gain and maximum DAC offset.
The devices showed drift over the test period of
about 10 ppm, but it was inconclusive how much
of the drift was attributable to the converter. The
laboratory measurement equipment has limited
stability over the 1000 hours also (6 1/2 digit
voltmeters are only guaranteed to 10-20 ppm
drift over a 90 day period at room temperature).

Explain
the
difference
non-ratiometric and ratiometric.

between

Load cells are ratiometric devices, meaning that
their output signal is proportional to their
excitation voltage. For example, if the excitation
voltage increases by three per cent, then the
output signal from the load cell will also
increase by three per cent. A ratiometric offset is
an offset, such as the offset of the load cell,
which changes proportionally to the load cell
excitation voltage. A non-ratiometric offset is
one which does not change proportionally with
changes in the load cell excitation voltage. The
offset of an operational amplifier which
amplifies the bridge signal is non-ratiometric; if
the bridge excitation changes, the offset does not
AN32REV4

change in proportion to it. Non-ratiometric
offsets become an issue if the magnitude of the
bridge excitation voltage changes due to drift.

What do the numbers in the calibration
registers actually mean?
There are two non-ratiometric offset calibration
registers, one for the AIN input and one for the
VREF input; one 4-bit offset trim DAC; one
ratiometric offset calibration register for the AIN
input; and one gain calibration register. When
the calibrations are performed, they should be
performed in the following sequence:
The
non-ratiometric offsets should be calibrated first
(if you choose to calibrate them); then the
ratiometric offset; followed by gain calibration.
When the non-ratiometric offsets are calibrated,
an LSB in the 24-bit digital calibration words
represents 2-23 proportion of an internally-scaled
MDRV (Modulator Differential Reference
Voltage). At the MDRV+ and MDRV- pins, the
MDRV has a nominal value of 3.75 volts. This
voltage is internally scaled to a nominal 2.5 volts
for use with the non-ratiometric calibration. The
24-bit calibration word is stored in 2's
complement form with one count equal to
approximately 300 nV at the input of the internal
AID converter. For the AIN channel this will be
scaled down by the gain of the instrumentation
amplifier (X25) and the PGA gain. For a PGA
gain = 1, one count will represent about 12 nV.
Non-ratiometric offset to be calibrated by the
VREF channel cannot exceed approximately ± 2.5
volts. Non-ratiometric offset to be calibrated by
the AIN channel cannot exceed approximately
± 2.5 volts divided by the channel gain. With a
PGA gain = 1, the maximum non-ratiometric
offset which can be calibrated on the AIN
channel cannot exceed approximately ± 100 mY.

When the ratiometric offset is calibrated, the
4-bit DAC coarsely trims offset from the analog
5-59

_

..............
..... ....
.............
signal. The remaining ratiometric offset in the
AIN channel is trimmed after the signal is
converted using the digital word from the
ratiometric offset register. The DAC allows the
user to add or subtract offset up to 200 per cent
of the nominal input signal. The AIN ratiometric
offset register can be used to add or subtract
offset equal to the nominal full sr.:ale input signal
into the X25 amplifier. An LSB in the
ratiometric offset register represents .2-23
proportion of the voltage input across the
VREF+ and VREF- pins at the internal input to
the AIN channel AID converter. This will be
scaled down by the AIN channel gain when
calculated relative to the instrumentation
amplifier input. For example, with a VREF =2.5
V, and a PGA gain = 1, one count of the
ratiometric offset register would represent about
12 nV at the instrumentation amplifier input.
The proportion remains ratiometric even if the
VREF voltage should change. The 24-bit register
content is stored in 2' s complement form.
All calibration registers can be read or written by
the user. This allows the contents of the
calibration registers to be read and stored in
EEprom; or to be modified by the user. This is
useful in the case of the ratiometric offset
register as it allows the user to add or subtract
small offsets from the transfer function after the
calibration has been performed. This allows the
user to shift the transfer function to allow for
load cell creep or load cell zero shifting "below
zero" when the converter is measuring in
unipolar mode. It also allows the gain register to
be modified as will be discussed in the next
question.
The gain calibration is performed last. The
.regIster
.
contents 0 f the gam
spans f rom 2- 23 to
2. After gain calibration has been performed, the
numeric value in the gain register should not
exceed
the
range
of
0.8
to
1.2
(decimal)[666666H to 999999H]. The gain
calibration range is ± 20 % of the nominal value
5-60

Answers to Application Questions

of 1.0. The nominal value of 1.0 is for an input
span dictated by the VREF voltage, the PGA
gain and the X25 instrumentation gain (see the
previous discussion on setting the input span to
the converter). The converter may operate,
subject to internal amplifier saturation (discussed
later) with gain slope factors from 0.5 to 2.0
(decimal) but when the slope exceeds 1.2 the
converter output code computation may lack
adequate resolution, giving results which may
include missing codes.
How can the gain be calibrated if a full scale
signal is not available?
Some scale manufacturers desire to calibrate
gain using some weight other than full scale. For
example, a truck scale may have a capacity of
100,000 lbs (45,400 Kg.). Who wants to carry
around that much weight to calibrate the scale?
Calibrating the scale with 10 per cent of full
scale capacity isn't a simple task.
The CS5516 or CS5520 can be gain calibrated
with some input signal other than full scale.
Assume one wants to calibrate using an input
which is 10 per cent of full scale capacity. The
normal gain calibration procedure cannot be
used.
Instead, the user can increment or
decrement the gain register until the converter
arrives at the. correct value, or the correction
factor can be calculated. For example, when the
converter is reset, the gain calibration word is
1.0. If a weight representing ten per cent of full
scale reads three per cent less than it should, the
value in the gain register can be scaled up by
three per cent. Gain accuracy can be improved if
output words are averaged while using this
technique.
Caution is advised in using a calibration weight
less than full scale. If the transfer function of
the the load cell happens to have a major
nonlinearity at the point at which calibration is
being performed, this will cause the rest of the
transfer function to be incorrect. Be certain you
AN32REV4

..... .....
...
. ..,--.-.
....
~

~~

~~

understand the particular linearity characteristics
of the load cell you are using.

The calibration word is not exactly the same
each time I calibrate with the same input
conditions. Why is this?
The calibration word is calculated using output
words from the converter which include the
thermal noise. Therefore the resulting calibration
words can be affected by this peak-to-peak
noise. This can be overcome by calibrating
several times in succession using the same input
conditions and averaging the results with an
external microcontroller. The averaged answer is
then written back into the calibration register.
The calibration word will typically have the
same magnitude of peak-to-peak noise that is
seen in the output conversion data. By
investigating the magnitude of this noise, one
can determine how many calibration words to be
averaged. Remember that Gaussian noise is
reduced by the ...IN when N samples are
averaged.

Is a different calibration required for each
PGA gain setting?
The PGA gain steps will have some tracking
error, typically 1 per cent or so. The PGA
actually uses different capacitor values to set the
PGA gain. These capacitors have a ratio error
due to processing which determines the gain
error of the PGA gain steps. Calibrations of
non-ratiometric offset for AIN, ratiometric
offset, and gain should be performed with the
PGA gain (1, 2, 4, or 8) set to the range which is
going to be used in the application. If the PGA
is going to be changed during measurements,
calibration words should be performed and saved
in EEprom for each PGA gain setting.
Therefore, to achieve good gain tracking when
the PGA gain is changed, a gain calibration
should be performed with each PGA gain
AN32REV4

Answers to Application Questions

selection. The following calibration method is
preferred by some designers as it requires only
one user adjustment for the input signal.
Assume the converter is being gain calibrated
with a 2.5 volt VREF. With the PGA gain set to
8, the full-scale input would be 12.5 mY. Input
the signal intended for full scale ( 12.5 mV
± 20%) and calibrate the gain with the PGA set
to 8.
Save the gain calibration word. Then
without changing the input signal, change the
PGA gain to 4. Ideally the converter should
output a half scale code. The actual output code
may be lower or higher. Increment or decrement
the gain register until the resulting conversion
code is half scale. Calculate the offset required
to modify the gain register when changing the
PGA from a gain of 8 to a gain of 4. Save this
offset word and use it to modify to gain register
when PGA gain is changed from 8 to 4. Next,
reload the gain register with the calibration word
determined with the PGA gain of 8 and change
the PGA gain to 2. The converter should output
a code of one quarter of full scale. Increment or
decrement the gain register to yield the correct
output code. Calculate the offset required to
modify the gain register when the PGA is
switched from 8 to 2. Save this offset for future
use. Reload the gain register with the gain word
for a PGA gain of 8 and change the PGA gain to . ' , '
1. This time the output code should be one
eighth of full scale. Modify the gain register and
save the offset as done in the previous
calibration steps. While this example calls for
saving the register offsets, one can choose to
save the gain words themselves. This will
depend upon the algorithm you choose to use in
your microcontroller. The advantage of this
calibration method is that it removes the error
associated with the user adjusting the input
signal to a new value. The method can be very
accurate if some averaging of the output
conversion words is performed during the
calibration sequence as this removes uncertainty
due to the thermal noise in the system.

5-61

..........-...........
..,

~

..,..,.,..

..,..,

~

Why is ac
excitation?

Answers to Application Questions

excitation

better

than

dc

The CSSS16/CSSS20 converters are designed for
bridge transducer signals. Bridge transducers
output low level signals which can be adversely
affected by amplifier offsets, amplifier bias
current effects, noise (both thermal and lIf), and
parasitic thermocouples. Parasitic thermocouples
exist in normal circuit wiring. Junctions such as
tin-lead solder and copper PC board trace can
introduce thermocouple effects of 3-4 ~V1°C if
thermal gradients exist across the circuit. In a
dc-excited bridge circuit, there is no way to
discern between the actual low level signal being
generated by the bridge and the error signals
introduced by amplifier offsets, amplifier bias
current effects, lIf noise, and parasitic
thermocouples unless some method is used to
separate the actual signal from these error
sources. One method of separating the signal
from the error sources is to use an ac-excited
bridge system.
When the CSSS 16/CS5520 are configured for
ac-excited bridge measurement; the converter

measures the signal which is of the same phase
and frequency as the excitation frequency. The
CS5516/CS5520 converter actually use a
polarity-switched square wave whose frequency
is normally a sub-multiple of the XIN clock
frequency to the converter.
Figure 6 illustrates the benefits of ac excitation
versus dc excitation. In one of the plots in
Figure 6, the CS5520 converter was configured
to measure a bipolar signal with an input span of
± 12.5 mV with dc excitation. Conversions were
performed with a zero input signal from the
bridge and data was collected for a one hour
time interval. One LSB (least significant bit) of
the CS5520 was equivalent to about 25
nanovolts. The data collected indicates that over
the one hour period the average value of the data
drifted as much as 1.3 microvolt, or about 50
counts. The CDB5520 evaluation board was
used for collecting the data and the drift was
attributed to parasitic thermocouples in the
components or the wiring of the board. The
board was used in open air and the data
illustrates the effects of thermal gradients
introduced by the cycling of the air conditioner
system. The second plot in Figure 6 illustrates
the stability of the conversion system when the
converter is set up for the same operating

DC Excitation
Time Domain Data

Nanovotts

1250

AC Excitation
Time Domain Data

,-:<- ;- -~ll~sB~25n~l-

1000

,

750

'-

'-

- ' '------'-

- : - -; - -; - -; - - ;- - ~ 11 ~SB ~ 25 n~ 1_

~

__ , __ , __ , __

,_ _

!..

L ._ _ _- ' . _

SOO
250
0
·250
·500
-7SO
·1000
-1250
0.00

0,50
time (hours)

1.00

O,SO
time (hours)

1.00

Figure 6. Stability Over One Hour using DC and AC Excitation.

5-62

AN32REV4

_.
...._- ._.
_...........
.........
.."

conditions, but with ac bridge excitation. The
plot illustrates the normal thermal noise of the
circuit but the average value remains stable over
time.

Are there disadvantages to ac-excitation?
The ac-excited bridge circuit must include some
type of driver circuitry which can add some
additional cost ( The combination of a transistor
and the MIC4428 is below $3.00 at 100 piece
quantities (1994)).
Another disadvantage is
that service technicians must be educated about
ac excitation; that troubleshooting with a dc
meter isn't adequate; although the system can be
configured for dc operation for basic
troubleshooting tasks.
One must be cautious when using ac-excitation
if the load cell uses a cable with a large
capacitance. Since the converter uses a switched
square wave to excite the bridge, the cable
capacitance may adversely affect measurement
accuracy if the square wave excitation signal
does not settle adequately. The converter is
designed to begin sampling the square wave
signal at a time interval of 64 XIN clock cycles
after the excitation signal changes polarity. The
square wave should have settled to within ± 5%
of its final value in the 64 XIN clock cycle
period to ensure measurement accuracy. Note
that this settling requirement must also be met
by any filtering elements used in front of the
converter on the AIN or the VREF signal inputs.
For very long cables, the CS5516/CS5520 can
be configured .for
a switched bridge
measurement configuration by setting the
converter for dc excitation mode to measure
bipolar signals and having the external
rnicrocontroller control the bridge polarity.
When the polarity of the bridge excitation is
changed, the external rnicrocontroller then waits
for
at
least
six output words
(the
CS5516/CS5520 can take up to six filter cycles
AN32REV4

Answers to Application Questions

to settle whenever the input signal changes in a
transient manner) from the converter before
taking a final reading. By averaging a reading
for one polarity of excitation with a reading with
the opposite polarity of bridge excitation, the
errors due to parasitic thermocouples can be
averaged out. If this configuration is used, the
normal calibration sequence for offset and gain
would have to be modified. An algorithm to
calibrate the offset and gain registers could be
developed by the user.

BXl and BX2 outputs are used for ac
excitation. What logic level is output from
these pins if theac excitation is stopped?
What are the logic outputs of BXl and BX2 if
the converter is put to sleep?
Internal excitation with the FI-FO bits of the
configuration register equal 0 sets BX2 = +5V,
BXl = OV. If external excitation is used, BXl
will always control the BX2 output. In sleep
BXl = +5V and BX2 = OV.

Explain the noise
CS5516/CS5520.

performance

of

the

The data sheet gives a typical noise specification
for the CS5516/CS5520 at each gain when
operating in bipolar mode with a VREF voltage
of 2.5 volts. When operating in this mode one
LSB of the converter is equal to (2 X 2.5)/(Gain
X 220). For example, with a gain of 200 (8 X25)
the noise specification is 150 nV rms. With a
gain of 200, one LSB in the CS5520 converter
(bipolar mode) is equivalent to about 23.8 nY,
so the rms noise would be equivalent to 150
nV/23.8 nV or 6.3 counts. A rule of thumb says
that peak-to-peak noise is 6 to 6.6 times greater
than rrns, so the peak-to-peak noise would be
about 38 to 41 counts when operating in this
mode. This calculation can be verified by
capturing 1000 (the statistical uncertainty is
reduced if a large number of samples are
collected) conversion words into a file and
computing the standard deviation of the data.
5-63

.:

.. .

...,-....... . _.
.............
.,..,~

One standard deviation is equivalent to the rms
noise if the data follows a Normal or Gaussian
distribution. It is useful to plot a histogram of
the data to verify that it has a Gaussian
characteristic. The noise in the converter itself is
Gaussian so the user can average output words
to reduce the effects of noise. Averaging N
samples reduces the noise in the averaged output
words by the ~.
The CDB5516 and CDB5520 evaluation boards
include software which allows the user to read
and write all registers in the converters, collect
conversion data, perform averaging, save data to
a file, and compute the standard deviation of a
group of output conversion words. The
evaluation board and its software may be able to
assist in evaluating the noise of the converter in
your system.

Answers to Application Questions

vibration. If the noise is still too high, try
grounding the AIN+ and AIN- pins of the
converter right at the converter itself and
perform the test again. The input components to
the converter may be picking up high frequency
radiated noise from some digital circuitry on the
board.
If the noise histogram plot does not appear to be

Gaussian, suspect radiated interference from
digital circuitry or from a dc-dc converter.
When testing for noise, be sure to ground the
input signal leads to the signal ground; do NOT
use a load cell simulator. See the next item.
Is a load cell simulator a good test tool for
evaluating the CS5516 and CS5520?
It is helpful to know what limitations can exist if

My application circuit appears to have an
excessive amount of noise. How do I
determine the cause?
If the results from your circuit exceed the

expected value (usually a computed estimate for
the circuit based on sound engineering analysis),
some steps can be taken to help determine the
source of the excess noise. The first step is to
remove the load cell from the circuit and ground
the input signal leads as shown in figure 7.
With the input grounded, collect at least 1000
samples (to remove statistical uncertainty) and
perform a histogram analysis on the data. Figure
8 illustrates an example of a noise histogram
which has been performed on data using Quattro
which shows the "shape" of the data (Gaussian).
Calculate the standard deviation of the data (one
standard deviation is equivalent to the rms noise
for gaussian type noise). The load cell has been
disconnected so that the noise performance of
the digitizer can be assessed by itself. If the
converter is "quiet" with the input grounded, it
suggest that noise is getting onto the cable or
that the load cell is possibly sensitive to
5-64

you are using a load cell simulator in place of an
actual load cell. If you are trying to use the
CS5520 to digitize a 10 to 20 mV signal to 20
bits, the output codes can drift around due to
what is apparently Iff noise in the simulator. A
way to test this is to use two 348 ohm 1% metal
film resistors tied from the AIN+ and AINinputs of the CS5520 to the signal ground.
Examine to see if the drift remains when the
simulator is disconnected and the signal source
is signal ground.
A second problem which can be encountered
when using a load cell simulator· is that some
simulators will not work well with AC
excitation. It seems that the switch contacts in
some simulators are made of materials which
rectify the signal and therefore cause errors in
the bridge output signal. Use a totally resistive
bridge with no switches if you encounter this
type of problem.
What benefit does an evaluation board offer?
The CDB5516 and CDB5520 evaluation boards
save time and money over prototyping. The
AN32REV4

»z

~
::u

m

:f

4.096 MHz

CS5516
CS5520
M

Rl
+5
V

_

_

~

__

•

_

VREF+

~470PF VREF-

R3
R2

__ ,

2.5k

'->

IIN2

~470PF

~

301

301

2
Channel
FIR
Filter

OUT!

~ 4.7 nF

J
~

2-Channel
Delta-Sigma
Modulator

. • . . INI

AIN--

OUT2

r

~ "·1

'( :t
0.1;;

MDRV+t

MOer+

1
10

Figure 7. Ground Input Leads for Troubleshooting Noise.

I

-~------­
...,-- -----------

Answers to Application Questions

preassembled and tested boards come with a
serial cable to connect to a PC-compatible
computer and include software which allows the
user to manipulate the registers inside the
CS5516 or CS5520.
Calibrations can be
performed and conversion data can be collected.
The evaluation boards support dc or ac
excitation of a bridge transducer (not supplied)
which is connected to a terminal block on the
circuit board.

converter first gets reset. If the circuit is
configured for external dc excitation mode, cut
the trace and use internal dc excitation; or pull
up the pin with a resistor pull-up.

The MIC4428 and MIC4425 devices are used
in applications with the CS5516/CS5520.
What is the address of the company that
makes these devices?
Micrel, Inc., 1849 Fortune Drive, San Jose, CA,
95131. (408) 944-0800, FAX (408) 944-0970.

The CDB5520 includes a CS5520; the CDB5516
includes a CS5516. Other than the converter
which is socketed on the board, the evaluation
boards are identical. Therefore, the board can be
used to evaluate either converter chip. The
software includes a menu selection for the type
of converter (CS5516 or CS5520) to be tested.

The data sheet states that the converter uses
about 3 rnA of current. Mine draws about 30
rnA. Any explanation for this?
Check your BXl pin. One of the schematics in
the first data sheet had this pin tied to +5 volts
directly. It must be pulled up through a resistor
as the BXl pin has a low logic output when the
140.-------------------------------,
120 .................................................... ..

............................................................

100 ............................................

.......................................................

80 ...................................... ..

60

.......................................

40 .......................

-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8

Figure 8. Example Noise Histogram for CS5520 Output Codecs
VREF 2.5V, PGA 4, Bipolar mode.

=

5-66

=

AN32REV4

..........
...........
......,........
~.

AN28

Semiconductor Corporation

Application Note
Precision Temperature Measurement using RTDs
(Resistance Temperature Detectors) with the CS5516 and
CS5520 Bridge Transducer AID Converters
by
Jerome Johnston
The CS5516/CS5520 bridge-measurement AID
converters can be configured for precise
measurement of resistance using a ratiometric
resistance measurement technique.

DC·Excited RTD Digitizer
Figure 1 illustrates the CS5516 16-bit AID
converter used as a digitizer for a platinum RTD.
The RTD is excited with a 250 IlA current
generated by the LM334 programmable current
source. The IN457 diode offers some first order
temperature compensation to the current source,
but the exact value and temperature coefficient
of the current source isn't important because the
current is used in a ratiometric measurement
configuration.
The current is used to develop both the voltage
reference (2.5 V across Rl) for the AID and the
signal voltage across the RTD. The initial
accuracy of the reference resistor is not critical
because the CS5516 offers gain calibration
capability, but reference resistor Rl must have
low temperature coefficient. The temperature
drift of the reference resistor will affect the
accuracy of the ratiometric measurement. A
Vishay S 102K resistor is recommended for the

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 Fax: (512) 445-7581

reference
resistor
to
measurement accuracy.

achieve

optimal

The offset and gain accuracy of the circuit are
ensured by self-calibration. Offset is calibrated
with OQ connected in place of the RTD. Full
scale is then calibrated with a known resistance
whose value is ideally 400.00Q connected in
place of the RTD. Once the AID is calibrated,
the RTD resistance is measured as a proportion
of the 400Q. The range of resistance which can
be measured is 0-400Q. This range represents a
temperature range of below -200°C to greater
than +800 °C when using a 100Q platinum
RTD. The resistance over the 400Q span can be
measured to an accuracy better than 0.025Q.
Linearization
of
the
RTD
and
resistance-to-temperature conversion is then
performed in the system microcontroller.
Accuracy of the temperature measurement will
depend on the RTD and its associated
linearization algorithm.

AC·Excited RTD Digitizer
Synchronous detection techniques can greatly
enhance measurement accuracy.
In a
synchronous detection system, the sensor is
excited with a fixed frequency square wave. The

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

MAR '95
AN28REV2

5-67

•

. .. ...
._..,.
....
~-

~~~

~-~..,

Precision Temperature Measurement

+5V
'Any crys18l3.579-4.9152 MHz

LM334

BX1

SMODE

BX2

sell<

1N457

DRDY
VREF+
Serial
Interface

3.01 k ~ 470 pF VREF.
3.01 k ~ 470 pF

OS
RST

Sys1em
Micro
Controller

SID
Pla1inum ___~ )~_ _---'l30v...1--1~_-,A""IN~+~
RTD
1000

301

~ 4.7 nF

SOD

AIN.

~4.7nF

·200 10 +600

~

Figure I, CS5516/20 RTD Digitizer· DC Excitation

detection system measures only the information
which is of the same phase and frequency as the
excitation frequency. This measurement method
eliminates the dc errors introduced by parasitic
thermocouples which lie between the sensor and
the detection circuitry.
Figure 2 illustrates an RTD measurement system
in which the RTD is excited with a
switched-polarity current source. Resistor values
are illustrated for two different current options.
Less self-heating of the RTD occurs with lower
excitation current.
The majority of RTD
measurement systems use a 1 rnA direct current
(dc) for excitation. The 1 rnA current is chosen
to produce a large enough output signal so that
parasitic thermocouple errors are not a
significant portion of the signal to be measured,
but parasitic thermocouples will limit accuracy.
The proposed ac-excited RTD digitizer uses only
100 J.LA excitation current. Using a 100 J.LA
current for excitation will result in an output
signal only one tenth of that produced by a 1
rnA excitation but the self-heating effects of the
5·68

RTD will be one hundred times less. Less signal
output from the RID is acceptable when
synchronous detection is used because error
voltages due to parasitic thermocouples are of no
consequence.
The switched-polarity dc current source is
developed by operational amplifiers UIA and
VIB.
The CS5520 is configured for
internally-controlled AC excitation.
The
CS5520 is programmed to output a 1kHz square
wave (XIN = 4.096 MHz) from its BX2 pin.
Capacitor C 1 is used to convert the output signal
from 0-5 V logic to ±2.5 volts, which is then
converted by the voltage-to-current converter to
output either ±loo J.LA or ±4oo J.LA depending
upon the selection of resistors.
The
switched-polarity excitation current is then used
to develop the reference voltage for the
converter across resistor R7 and used to excite
the RID. A four wire Kelvin-connected RTD is
used to maximize measurement accuracy.
Reference resistor R7 will set the gain stability

AN28REV2

.. ...
.... --._.
....
~-

~~

Precision Temperature Measurement

~~

Rl
R2
R3
R4
R5
RS
R7
Cl
PGA

Wl.LA

~

lOOk
lOOk
lOOk
lOOk
24.9k
75k
28.0k
lOWF
4

24.9k
24.9k
24.9k
24.9k
AS
S.34k
18.7k r------'M--_=:_;
S.98k
l00!tF
1
1=

~

+5V
"Any crys1a13.579-4.9152 MHz

SMODE
SCLK
DRDY

~~~---------=~~

Serial
Interface

CS
RST

System
Micro
Controller

SID
SOD

-5V

'PGA = 1 for 400 ~A
4forl00~A

Figure 2. CS5516120 RTD Digitizer - AC Excitation

of the measurement and therefore a Vishay-type
S 102K series resistor is highly recommended.
Note that the values indicated for the R7 reference
resistor are the nominal suggested values. The
converter has gain calibration capability capable
of adjusting gain for gain spans re 20 % of
nominal. Therefore resistor R7 could be changed
up to re 15% of its stated value and still leave 5%
of the gain calibration range capability available.
For example, R7 could be set to 30 K (100 rnA)
or to 7.5 K (400 rnA) to utilize more acceptable
precision resistor values. The initial accuracy of
R7 is not that important if gain calibration is used.
Stability over temperature is the most important
parameter for R7.
Resistors of 1% tolerance and 100 ppm tempco
can be used in the voltage-to-current converter
and not affect system accuracy. The resistance
measurement is performed using ratiometric
techniques, therefore the exact value of the drive
current is not critical. Wirewound resistors
should not be used in the switched-polarity
current generator or for resistor R7.
AN28REV2

When using 100 J.lA excitation, the PGA
(Programmable Gain Amplifier) inside the
CS5520 is set to a gain of 4. The internal
instrumentation amplifier is fixed at 25; therefore
the input span is nominally set to 28 mV ( (100
J.lA X 28.0 k)/ (4 x 25) = 28 mY). The zero of
the transfer function can be calibrated using a
zero ohm resistor in place of the RTD. Gain
calibration can be performed using a 300n
resistor in place of the RTD. The resistance
span will support temperature measurement over
a temperature range of -200 °C to +550 0c. If
higher temperatures need to be measured, that is,
higher resistance than 300n, the gain calibration
can be performed using a 600n resistor with the
PGA set to a gain of 2.
Linearization
of
the
RTD
and
resistance-to-temperature conversion is performed
in the system microcontroller. Accuracy of the
temperature measurement will depend on the RTD
and its associated linearization algorithm.

5-69

.-

~J

_- _

...........
.... ._..
.............

Precision Temperature Measurement

• Notes.

5·70

AN28REV2

.... ......
............
~

~~
~

..,

AN47

Semiconductor Corporation

Application Note
Infrared: A New Standard in Industry
by
Brent Wilson
A new communications standard has been
developed for infrared data links.
This
standard's purpose is to facilitate universal
connectivity in portable computing. The fact
that the technology which supports the standard
is low cost will serve as a catalyst for its
incorporation into instrumentation and industrial
data collection applications.
The increasing use of small portable digital
devices like notebook PCs, personal digital
assistants (PDAs) and digital handheld
organizers generated a compelling need to
develop a cheap wireless interface to enable
these devices to communicate with each other.
Toward that end, a standards group calling
themselves the Infrared Data Association (IrDA)
assembled in June of 1993.
Formed from
companies representing the very backbone of
infrared
and
computer
technologies,
Hewlett-Packard, IBM, Sharp, Apple, Cirrus
Logic (Crystal Semiconductor is a subsidiary of
Cirrus Logic), and others, the IrDA published its
first set of standards (Physical Layer, Link
Access Layer, Link Management Layer, and
Transport Layer) in June of 1994, just one year
after its first assembly.
Soon after,
manufacturers of notebook and desktop PCs,
PDAs, printers, infrared pods, and other digital
equipment began implementing this infrared
technology into their next-generation systems.
Why use wireless IR (infrared)?

The primary purpose is to achieve connectivity
between devices without the inconvenience and

the cost of a cabled system. Many systems
which currently use a cable to achieve a serial
data connection (typically RS-232) between devices
can be readily adapted to use an IR link. The
wireless link is most appropriate where the data link
needs to be established only momentarily and only
for a short distance (one to three meters). This
facilitates portability. Wireless IR (per the IrDA
standard) offers. line-of-sight communications with
very few regulatory issues (no FCC requirements
like wireless RF).
What does the IrDA standard offer?
Using the IrDA protocol ensures interoperability
with PCs, PDAs, and other digital IR equipment.
Since the goal of the standard is to support
portability, the data coding scheme is designed
to minimize IR power-per-bit consumption. This
maximizes battery life in portable systems. The
IrDA standard supports an IR link of up to one
meter in distance (three meters optional) between
devices. The transmission distance is limited to
minimize power consumption in the transmitter,
again to maximize battery life. The IrDA standard
supports point-to-point and point-to-multipoint
architectures with baud rates of 2400, 9600, 19.2k,
38.4k, 57.6k and 115.2k. CRC-style error detection
and frame-based error correction is also supported.
What IR solution does Crystal offer?
The CS8130 is a multi-standard infrared
transceiver. The device supports several infrared
communication
formats;
including
IrDA
(HP-SIR), Sharp ASK (Amplitude Shift Keying),

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX 445-7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

FEB '95
AN47REV3

5-71

_

...............
...-.
.........

..., .,,-,.

Infrared: A New Standard

and TV remote.
The chip is designed to
interface to a standard DART or RS-232-like
interface as shown in figure 1. The transmitter
portion of the device contains LED drivers with
programmable output power.
The receiver
portion of the chip includes a high-gain PIN
diode receiver amplifier with programmable
sensitivity. The transceiver runs on any supply
from +2.7V to +5.5V with the digital interface
designed to maintain TTL-compatible thresholds
at all supply voltages. The CS8130 is available
in a tiny 5 X 7 mm 20-pin SSOP package and
operates over the industrial temperature range of
-40°C to +85°C.
The IrDA standard enhances connectivity in the
portable computer environment. What are some
other applications for short range wireless IR?

additional LEDs to achieve longer distances).
Currently, there are a multitude of hand-held
devices which store data for later transfer or
accept operator-generated data to be input to a
host computer: handheld terminals, barcode
readers, remote data loggers, handheld
datalogging multimeters, inventory checkers,
process control calibrators, home automation and
control, and keyless burglar alarm entry systems.
What support does Crystal offer for wireless IR?

The CDB8130 evaluation kit is available from
Crystal. It comes with software necessary to
link two PC-compatible computers using two
CS8130 circuits.
Where do I get a copy of the IrDA standard?

The CS8130 can readily be adapted to
applications which now use an RS-232 cable of
2 meters or less (The transmit drive can be
increased with external transistor drivers and

The Infrared Data Association is located at P.O.
Box 3883, Walnut Creek, California, 94598.
Phone: 510-943-6546 Fax: 510-934-5241

100

0.1I'F~
VD+
12

9

19 EXTCLK

Baud Rate
Generator

BPV22NF

--z.-

17 XTALIN
CJ

6864 MHz

18 XTALOUT

UART
HSDL·4220
-t--~---,----< +3V

CS8130

a?3

&.

~

Data/Control
Decoder

5.20

11

RESET

13 RXD
16 FORMIBSY
14 TXD
15 Die
10 PWRDN

20

RTS
RXD
CTS
TXD
DTR

I SE~~CT I

DGND

Figure 1. CS8130 Infared Transceiver Interface

5·72

AN47REV3

.......
......,.
. .......
....
~-

~
~

~

AN38

Semiconductor Corporation

Application Note

Using The Capture Evaluation System
By John Lis

The CAPTURE interface board is a development
tool that interfaces a Crystal Semiconductor analog to digital converter to a PC-compatible
computer. It is software adaptable to be used
with a variety of Crystal Semiconductor ADCs.
When operating, digital data is collected from
the analog to digital converter, then transferred
to the PC over a serial COM port. Once the data
is in the PC, evaluation software is included to
analyze the data and display the analog to digital
converter's performance. The evaluation software permits time domain, frequency domain
and noise histogram analysis.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581

The Crystal Semiconductor evaluation equipment is very easy to setup and use, and it will
actually expedite system design and development. Setup time for the CDBCAPTURE
evaluation system using a Crystal Semiconductor
evaluation board is less than one hour. This includes clearing a work area, reading the
instructions, and troubleshooting minor problems. Using the evaluation board, the
performance of the analog to digital converter
can be verified against data sheet specifications.
As development continues, the evaluation system
can then be used to measure system performance

Copyright © Crystal Semiconductor Corporation 1995
(All Rights ReseNed)

NOV '94
AN38REV1
5-73

_.-_..--__.._-_
...
.-.-.

Using The Capture Evaluation System

and isolate noise sources. Later on, the evaluation software can be modified for production
test.

• Carefully check all the power cables

INITIAL SETUP:

• Carefully check all the signal cables

Setup of the CAPTURE evaluation system is
very easy. The setup begins with installing the
CAPTURE Evaluation software on the Pc. Next
the power and signal cables are connected to the
CAPTURE board, evaluation board, PC, signal
generator and power supplies. With the setup
complete, evaluation and test can begin.

• Verify the appropriate COM port

Before installing the CAPTURE software on the
PC, read the INSTALL.DOC file on the
CDBCAPTURE Evaluation software diskette.
This file contains instructions on software installation. After the software installation is complete,
read the README.DOC file in the PC's CAPTURE directory. The README.DOC file
contains valuable information concerning hardware requirements, setup, evaluation board
configuration, software operation, PC setup, and
special notes.

CDBCAPTURE EVALUATION SOFTWARE:

The PC used for the CAPTURE evaluation system has to be a PC AT, PS/2 or compatible with
at least four megabytes of Extended Memory. If
the CAPTURE evaluation system does not operate properly upon setup, investigate the
following items:
• Availability and configuration of Extended
Memory on the PC (4 meg, VCPI compatible)
• Sufficient amount of disk space available on
the PC (4 meg required)
• CONFIG.SYS proper modification
(see README.DOC)
• EMM386 the only memory manager
• Run "CAPTURE -config" to adjust PC
hardware
5-74

• Power supply voltage and current levels

• Possible hardware conflict among PC add-in
circuit boards
• Evaluation board jumpers and DIP switch
settings

Execution of the evaluation software begins by
typing "CAPTURE". The screen shown
in Figure 1 is displayed, prompting the user to
select a part number and interface method. This
is done from "SETUP" on the menu bar. Note
that "SETUP" and "QUIT" are the only options
available on this screen. With the evaluation
software running, select the appropriate part
number and capture board COM port by pointing
and clicking on "SETUP". This procedure will
download configuration software to the
CDBCAPTURE circuit board via the COM port.
When the "SETUP" is properly configured, the
"TEST" option becomes enabled, permitting
Time Domain, FFT and Noise Histogram tests.
The first test to perform is TIME DOMAIN,
found under the "TEST" menu bar. The time domain test is used to verify proper operation and
adjust the signal from the generator to the evaluation board. A sinusoid input signal is used, with
its frequency adjusted to about 1 percent of the
analog to digital converter's output word rate.
The "COLLECT" button is pressed, and data is
collected. A sine wave should be observed if
everything is working. The amplitude is adjusted
until it is near full scale. Figure 2 shows a near
full scale signal for a CS510lA analog to digital
converter. Exceeding full scale will cause the
signal to clip and distort.
AN38REV1

......
.......
--_...._.-.
~

.",

.",

Using The Capture Evaluation System

Figure 1

.'
Figure 2.
AN38REV1

5-75

. ...............
....
~-

~--

-.~.

Using The Capture Evaluation System

~~

With the amplitude of the input signal set to the
desired value, the analog to digital converter can
be tested in the frequency domain. Exit the
"TIME DOMAIN" test and select the "FREQUENCY DOMAIN" test from the "TEST"
menu bar. Adjust the frequency of the sinusoidal
input to about 5 percent of the analog to digital
converter's output rate. Figure 3 is an FFT of a
5kHz signal input to a CS5101A.

The graph and statistics shown in Figure 3 are
calculated from a sample set of data. These calculated values have an uncertainty that depends
upon the variance of the sampled population.
This uncertainty can be reduced by averaging
multiple independent data sets. Figure 4 is an average of 25 FFTs and its uncertainty is five times
less than the FFT in Figure 3. Notice how the
noise floor at -120dB is much smoother.

In Figure 3, the Signal to Noise Ratio (SIN) is
92.884 dB, this translates to 15.14 effective bits.
The Signal to Distortion Ratio (SID) of 95.146
dB is equivalent to 0.00175% Total Harmonic
Distortion. These numbers reflect the performance of the entire system including the analog to
digital converter, input filters, op-amps, and signal source.

1024 sample points of data were used in the
FFTs shown in Figures 3 and 4. This translates
to a frequency bin width of 50 Hz (Sample Rate!
Number of Samples =51200 Hz/1024). Collecting more samples (2048, 4096, 8192) for the
FFT increases the frequency resolution. Figure 5
is a plot of an 8192 sample FFT averaged 25
times. Here the bin width decreased to 6.25 Hz,
thus improving the resolution.

Figure 3.

5-76

AN38REV1

. ............
....
...-..
..,

~

~~~

Using The Capture Evaluation System

~~

Figure 4.

Figure 5.

AN38REV1

5-77

.. .
....,..--_
...,..., ....
...,...,~

.""

.."

Ideally, the signal to noise numbers in Figures 4
and 5 should match. However, the increased
number of samples in Figure 5 has revealed new
information. Notice that the base of the fundamental signal in Figure 5 is slightly smeared.
This suggests jitter in either the signal source or
sample clock. Also notice how the decrease in
bin width from 50Hz to 6.25Hz reduced the spot
noise floor by 9dBfrom -120dB to -129dB.
Each doubling of the sample size yields a 3dB
reduction in spot noise. Now more coherent
noise sources are noticeable and knowledge of
the frequency content can aid in isolating the
source and improving performance. These noise
sources were below the noise floor in Figure 4
and unnoticeable.
Increasing the number of samples from 1024 to
8192 doesn't reduce the uncertainty, so 25 FFTs
are averaged for Figure 5. The additional information contained in the larger sample size goes
toward higher frequency resolution. The number
of averages used depends upon the amount of
uncertainty acceptable and time available.
An analog to digital converter can also be tested
with a DC signal. For this test, exit the "FREQUENCY DOMAIN" test and select
"HISTOGRAM" test from the "TEST" menu bar.
Histograms are used in the static testing of DC
input signals. Here the input signal stays constant, and an ideal analog to digital converter
would output only one code. Deviations from the
ideal output are used to measure system performance.

Using The Capture Evaluation System

The SID DEV from the histogram test in Figure
6 indicates that the system rmsnoise increases
by 4.7 microvolts when a signal source is included with the analog to digital converter.
The information presented in Figure 6 is again
calculated from sampled data. Thus, there is uncertainty associated with each calculated value.
This uncertainty is reduced by increasing the
sample size of data. The sample size for the histogram in Figure 6 is 8192.
SUMMARY:
The CDBCAPTURE evaluation system is a
valuable computer-aided engineering tool which
assists in product development and evaluation.
The CDBCAPTURE can quantify component
and system performance. Histograms are available to measure the DC accuracy. From the
histogram's statistics, the offset, gain error, and
noise values can be estimated. FFTs are used
with a sinusoidal input signal to measure dynamic performance. The FFT statistics estimate
linearity and noise. Quantifying performance
aids in system integration. This information can
be used to identify noise sources and isolate performance issues to individual components. The
result is a quicker time to market and reduced
development costs.

Figure 6 is a Histogram of a CS5101A with its
input grounded. The MEAN suggests that the
analog to digital converter has an offset of -0.69
LSB. For a reference of 4.5 volts, and operating
in bipolar mode, the offset translates to -94.8 microvolts. The standard deviation (STD DEV) is a
measure of rms noise. Figure 6 has an STD DEV
of 0.49 LSB which translates to 67.3 microvolts
of rms noise. From Figure 4, the -120dB noise
floor translates to 72 microvolts rms of noise.
5-78

AN38REV1

..,-- --...--.------_----_...

Using The Capture Evaluation System

Figure 6.

AN38REV1

5-79

...-.
-.
...-.....-- .....
......

_

Using The Capture Evaluation System

• Notes.

5-80

AN38REV1

..... ....
.""".........
~~~

..,
Semiconductor Corporation

AN44
Application Note

USING THE CDBCAPTURE SYSTEM
WITH EMBEDDED AID CONVERTERS
by
John Lis

INTRODUCTION
The CDBCAPTURE system can be used to
collect data from embedded Analog to Digital
Converters (ADCs). Thus system performance of
the analog front end can be measured, analyzed
and quantified. By analyzing the measured
performance, noise sources can be identified,
isolated, and corrective actions taken. Here
CDBCAPTURE is used as an engineering tool,
reducing development time during system test
and integration. Another application could be
using CDBCAPTURE in production for testing
finished products and verifying system
performance.

CDBCAPTURE
The CAPTURE interface board is a development
tool that interfaces a Crystal Semiconductor
ADC to a PC compatible computer. Digital data
from the ADC is collected in a high speed
digital FIFO, then transmitted to the PC over a
serial COM port. Evaluation software is included
to analyze the data and demonstrate the ADC's
performance. The entire system consists of a
CAPTURE interface board, serial cable, RS232
cable, and software.
The software included with the CDBCAPTURE
system
quantifies
static
and
dynamic
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX 445-7581

performance of ADC systems. Static testing
includes Histogramming and calculation of the
mean, standard deviation and variance. Dynamic
testing includes Fast Fourier Transforms and
analysis of the power spectrum. Here Signal to
Noise Ratio (SNR), Signal to Noise plus
Distortion (SINAD) , Signal to Distortion Ratio
(SDR), and Signal to Peak Noise (SPN) figures
are calculated. Time domain plots are available
to visualize signals in the time domain and
confirm operation.

CDBCAPTURE WITH EMBEDDED ADCs
The CDBCAPTURE circuit board is designed to
directly
interface
with
most
Crystal
Semiconductor ADC evaluation boards. This
permits a quick and easy method to quantify and
verify the ADC's performance. However, it is
often desirable to measure the ADC's
performance in the actual system or to measure
the overall system performance. To collect data
from an embedded ADC, a special serial cable
needs to be designed. This. cable incorporates the
digital interface circuitry which exists on the
evaluation board. This cable is connected to the
appropriate signals on the ADC.
To collect data from an embedded ADC, the
digital interface circuitry on the evaluation board
needs to be incorporated on a modified serial

Copyright © Crystal Semiconductor Corporation 1995
(All Rights ReseNed)

FEB '95
AN44REV2

5-81

•

I

.._
-...
..._.--.
.......
...,--

..., ~

Using The COSCapture System with Embedded AID Converters

cable. Figure I is a block diagram illustrating the
process. On the top of Figure 1, the evaluation
board CDBXXXX contains digital interface
circuitry which translates signals from the ADC
to three standard serial signals named FRAME,
SCLK and SDATA. The timing and format of
these signals vary from device type to device
type.
In an embedded ADC application, the digital
interface circuit, between the ADC and the
CDBCPATURE circuit card, should be
implemented on a small card attached to the
serial cable as shown at the bottom of Figure 1.
The appropriate digital input signals need to be
identified. A method to connect to these signals
from the embedded system to the cable is then

implemented. The connection scheme varies for
each application and is easy to implement.
The schematic for the digital interface circuitry
is provided with the evaluation board data sheet.
Locate the serial interface connector containing
the signals: +5 V, GND, FRAME, SCLK, and
SDATA on the schematic. Working from this
connector, back to the ADC, identify the
circuitry required to create the serial signals.
This circuitry is implemented on a separate
circuit board, attached to a 10 conductor ribbon
cable with an IDC socket for its CDBCAPTURE
interface. The ADC interface can be any
connector scheme that is easy to implement.
Possible alternatives include stake headers, test
clips, circular connectors,or "D' style connectors.

CDBXXXX EVALUATION BOARD

~A>-<

~ D

C

-

;:::=

>--

INTERFACE
CIRCUIT

5V
GND
FRAME
SCLK
SDATA

EMBEDDED ADC

A
D
C
'--

CDBCAPTURE

<

MODIFIED
SERIAL RIBBON
CABLE
INTERFACE
CIRCUIT

CDBCAPTURE

§:::::

~

Figure 1. CDBCAPTURE INTERFACE

5-82

AN44REV2

_-.
...... . _.
..............
_
...........

Using The CDBCapture System with Embedded AID Converters

CS5508 EXAMPLE
The following example uses a CS5508 to
illustrate the process of designing a modified
serial cable. By examining the schematic for the
CDB5508 evaluation board, the digital interface
circuitry is identified. The schematic for the
CDB5508 evaluation board is provided in Figure
1 of the CDB5505/6n18 data sheet. The digital
interface portion is shown in Figure 2 below.
Resistors R23, R24 and R25 are not required if
the CS is always active. Also, V3B is always

active when using the CAPTURE board, thus it
can be changed to a general purpose buffer such
as V2.
Figure 3 shows the schematic for the modified
cable derived from Figure 2. The DRDY, SCLK
and SDATA signals are buffered to create the
serial cable signals for the CAPTURE board.
Five volt power is obtained from the embedded
system and filtered by Rl and Cl before it is
provided to the CAPTURE board. C2 is a bypass
capacitor for VI.

R22

+5

10

+5

+5

Ul
C55505
C55506
C55507
OR
C55508

DRDY

SDATA

SCLK

DRDY

16

SCLK
SDATA

15

14

Figure 2. CDB5508 Evaluation Board Schematic for the Digital Interface

RIBBON CABLE
(use twisted pairs for lengths> 2 ft.)

Rl

+5V
Cl
10uF

GND
DRDY

Ol-------'~

/"

+5

/"

+5
DRDY

seLK
SDATA

SCLK

O---~~'--1

SDATA

Figure 3. Modified Serial Cable Implementation of the Digital Interface

AN44REV2

5-83

.._-_
._.-.
_.-_..--_...

Using The CDBCapture System with Embedded AID Converters

Figure 4 shows how the hardware can be
implemented. The digital interface circuitry is
built upon a small circuit board. A ribbon cable
with a 10 circuit IDC socket is used for the
CDBCAPTURE interface. Separate ground wires
should be used for each signal return, and
twisted pair ribbon cable used for lengths greater
than two feet. The embedded interface uses color
coded test clips. The test clips provide a means
of interfacing an ADC without any special
connectors designed in the system. However this
method requires a little more setup time, since

the appropriate signals need to be located on the
circuit board.
CS5102A EXAMPLE
The CS5102A is used in the second example of
an embedded application. The methodology for
the cable design is the same as that in the first
example using the CS5508. The digital interface
circuitry is obtained from the CDB5101Al5102A
evaluation board data sheet. This information is
contained in the evaluation board's data sheet

TEST CLIPS
INTERFACE CIRCUIT

10 CIRCUIT
IDCSOCKET

'-RIBBON CABLE

Figure 4. Construction of the Modified Serial Cable
+5V
C47

C48~ uF

U12

+

T1
OE1
15
2

SDATA
SCLK

6

OE2

A2

Y2

--0

7

--0

3
13

I +5V
I SLATCH
I SCLK
I SDATA

HDR10D

A5
TPOO

CS5101A
or
CS5102A

SDATA
SCLK

~y

AO

Y5

____l!1__ _

JP5

:::0 - I +5V
10

YO
14

10 uF

+5V

74HC365

---~
------~

+5V

SDATA
SCLK

SSHfSDL- SSHfSDL

HDR8D

6

TRK1 -------- TRK1

~_TRK2 -------- TRK2

SSHfSDL>---------------~5

Figure 5. CDB5102A Evaluation Board Schematic for the Digital Interface
5-84

AN44REV2

.....
........
..... _...
........
....
.."

Using The CDBCapture System with Embedded AID Converters

..".."

Figures 4, 5 and 6. The digital interface circuitry
for the CS5102A is show in Figure 5.
Figure 6 is the way the digital circuitry is
implemented on the modified serial cable.

example, the embedded system is designed with
a test connector. The modified serial cable is
built with a connector which mates to the system
test connector. The test connector provides a
convenient and reliable means of interfacing the
ADC.

Figure 7 is the hardware implementation of the
modified serial cable shown in Figure 6. In this

P1

R3

+5V

10

GND

+ C3
JiOflF

+5V

CABt..E
<- _RIBBON
_ IorIonQll1O.21t.)

74HC74
10 _U3B

11 S

P2
+5V

0 9

+5V

SLATCH
SCLK
SDATA
SSHlSDL

+5V

SCLK

4

U3A

3

S a

5

SDATA

Figure 6. Modified Serial Cable Implementation of the Digital Interface

10 CIRCUIT

INTERFACE CIRCUIT

IDCSOCKET

TEST CONNECTOR

RIBBON CABLE

Figure 7. Construction of the Modified Serial Cable
AN44REV2

5-85

____

...
.-.... .....
._.
....
~--

Using The CDBCapture System with Embedded AID Converters

Testing An Embedded ADC
System performance can be measured by
interfacing the embedded ADC. The previous
sections described the hardware modification
required to interface a· Crystal Semiconductor
ADC with the CAPTURE board. Figures 8, 9,
and 10 are the results of using the histogram test
on a CS5101A in an embedded system.
Figure 8 is a histogram of a CS5101A operating
in the bipolar mode with the analog input pin
grounded right at the package. Data book
performance is expected, if proper design
practices have been used in developing the
circuit and layout. In Figure 8, the mean is -0.69
counts, which is well within the typical
specification of two counts for the bipolar offset.
The standard deviation is 0.49 counts. This
translates to 67 uVRMS (0.49 x 9 voltsI2 16 ). The
CS5101A data sheet specifies 70 uVRMS
typical.
A buffer op-amp is integrated in the system and
a data set is collected and displayed in Figure 9.
Both the mean and standard deviation numbers
changed with the addition of the op-amp. The
op-amp added 0.66 counts to the offset or
91 uV. The RMS noise increased to 0.63 counts
or 87 uV.

Figure 8. Histogram of a CS5101A with the Input
Grounded

Figure 9. Histogram of a CS5101A with a Buffer Op-Amp .

Figure 10 shows the histogram for the ADC,
buffer op-amp, and signal source. The signal
source output is set at zero volts. The histogram
statistics indicate an offset of 1.59 counts or 218
uV and the RMS noise is at 218 uV. Note, that
as more components are added to the system, the
offset changes and the noise increases. These
changes can be used to isolate and identify
problems.

Figure 10. Histogram of a CS5101A with a Signal Source

5-86

AN44REV2

----------- -----------

Using The CDBCapture System with Embedded AID Converters

CONCLUSION

The CDBCAPTURE system is designed to
easily connect to most Crystal Semiconductor
ADC evaluation boards. Digital circuitry is
included on the evaluation boards to implement
a standard serial data bus. The CAPTURE board
is software reconfigurable to adjust for different
ADCs and future products. The CDBCAPTURE
system permits easy transfer of digital data to a
PC for analysis.
Many times it is desirable to collect data from
the ADC while it is operating inside a complete
acquisition system. In this case, the digital
interface circuitry for the CAPTURE board is
implemented outside the system on a modified
cable. The electrical system has to provide the
appropriate interconnect scheme, using either
connectors or test points to clip onto.
The modified serial cable allows the user to
measure performance of the ADC while it is
embedded in an electrical system. The ADC as
well as the system performance can be measured
and quantified. This information is used to
isolate problems and investigate how certain
subsystems interact with each other.

AN44REV2

5-87

...........
........._.

.,. ..,.....

_.

~

Using The CDBCapture System with Embedded AID Converters

• Notes.

5-88

AN44REV2

.
...........
..,..,
..
.."""......,
~
~.

AN45

"."

Semiconductor Corporation

Application Note
CDB5504 Capture Interface
by

John Lis

The CDB5504 evaluation board requires a
simple modification to interface with the
CAPTURE board. The CAPTURE board
requires an SCLK input signal to collect data.
However, the SCLK pin on the CS5504 is a
digital input only. For the CDB5504 to interface
with the CAPTURE board, an SCLK signal
needs to be created.
One possible solution is to derive the SCLK
from the XOUT signal. The frequency of the
XOUT pin is within the specifications for the
SCLK signal and the serial port can accept a
continuous clock. The CAPTURE board is
designed to ignore extra clock signals on the
SCLK line when using a continuous serial clock.
Using XOUT as the SCLK input signal is a
simple modification of the evaluation board. It is
easy to implement, requmng no extra
components. The following steps describe the
modifications.

Next the 74HCl25 buffer needs to be modified.
U3-3 is isolated from the circuit, so there aren't
two devices driving the SCLK node. Finally
U3-8 is isolated, allowing U3B to be active and
able to drive the SCLK output signal to the
CAPTURE board. Figure I is a schematic for
the modified evaluation board.
The following
modifications.

check

list

summarizes

the

o REMOVE R25
o JUMPER Ul-6 to UI-18
o ISOLATE U3-3
o ISOLATE U3-8

The source of the SCLK signal is the XOUT pin
on the CS5504. Install a jumper on the CS5504
from UI-6 to UI-18. (Make sure that
adjustments are made for the CAB5504 adapter
board. Ui-18 translates to UI-21 on the bottom
of the evaluation board.) The lOOk resistor R25
needs to be removed to reduce the load upon
XOUT.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX 445-7581

Copyright© Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JAN '95
AN45REV1

5-89

IIIIODIFICATlONS TO THE CDB5504 FOR INTERFACING TO CDBCAPTURE

~

o

-t5
DROY

-t51-----L
GNO tt5l

•

,

6

DGNO
CCJi.N

'15J ..

010

....
p_.
'."......"

,
I ,....
.. .....

es

• -5
VREF-

AD
A1

U1

CS5504
DROY

Exlerral

VREF

-0

0

_38
SDA.TA

TP3

~ 111 Ali'a-

_ -"At;;

SQ.KO

TP4

~

.:. -Ai.i\.

~

.:. -AJJ:.,

•

9 1 AlN2+

SCLKI'Vp. l

."IIJ3i:l:::~~

~D'

,

•

1

III
SQ.KI

TP5 10
~ 1 AlN1-

•

1.011

BPIUP
BPiUp~

8 AlN1+

Ic
0

OJ

en
en

~1l3
-

Q.KI N

:I>

0
01:0

50

R2

,,__,_
. 0

BPlUP

l'It:te:

Ferrofe R25
Isolate lJ3.3
IsoIa:e lJ3.8
Jurrper U1-8 to U1-18

z01:0

en

:II

!;2
....

Figure 1. Schematic of CDB5504 Modified for the CAPTURE Interface

.. t'
'i
c
iii

3'

CD

in

CD

.
.......,.,......
.
...
~~

..,..,~

..,~

."

AN46

Semiconductor Corporation

Application Note
CDB5509 Capture Interface
by
John Lis

The CDB5509 evaluation board requires a
simple modification to interface with the
CAPTURE board. The CAPTURE board
requires an SCLK input signal to collect data.
However, the SCLK pin on the CS5509 is a
digital input only. For the CDB5509 to interface
with the CAPTURE board, an SCLK signal
needs to be created.
One possible solution is to derive the SCLK
from the XOUT signal. The frequency of the
XOUT pin is within the specifications for the
SCLK signal and the serial port can accept a
continuous clock. The CAPTURE board is
designed to ignore extra clock signals on the
SCLK line when using a continuous serial clock.
Using XOUT as the SCLK input signal is a
simple modification of the evaluation board. It is
easy to implement, requmng no extra
components. The following steps describe the
modifications.

Next the 74HC125 buffer needs to be modified.
U3-3 is isolated from the circuit, so there aren't
two devices driving the SCLK node. Finally
U3-8 is isolated, allowing U3B to be active and
able to drive the SCLK output signal to the
CAPTURE board. Figure 1 is a schematic for
the modified evaluation board.
The following
modifications.

check

list

summarizes

the

o REMOVE R25
o JUMPER Ul-5 to UI-14
o ISOLATE U3-3
o ISOLATE U3-8

The source of the SCLK signal is the XOUT pin
on the CS5509. Install a jumper on the CS5509
from Ul-5 to Ul-14. (Make sure that
adjustments are made for the CAB5509 adapter
board. Ul-5 translates to Ul-6 and Ul-14
translates to Ul-21 on the bottom of the
evaluation board.) The lOOk resistor R25 needs
to be removed to reduce the load upon XOUT.
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX 445-7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JAN '95
AN46REV1

5-91

MODIFICATIONS TO THE CDB5609 FOR INTERFACNG TO CDBCAPTURE

~

-16
-16
CRO(

-I8V

, ,
a 1>---,>----<1>----

Gl\Da"

..

•

+6

...6

-161-,15;0;::;-------

VC7Q1uF

.AGO

T Wv

DGND

t

1:

• II

SCLK

.-----..--

SClO.TA

COL

caw
_.~_

... _

i-i,
.1:

..,
....

\O!-

VA<-

....

.....
="

9,

~vV""""Ci9' \IRS'+-

1!W' 10
=C20
v 1!W'

,~

-16
In

CS5509

\/REF

a

~

3B

SClO.TA

s:t.IC

s:::u

~

c

ii1

~

I

....,..,.......,..
. ....,..,..,
.......
..,~

AN37

"",

Semiconductor Corporation

Application Note
Noise Histogram Analysis
by John lis

NOISELESS, IDEAL CONVERTER

~
OFFSET ERROR
RMSNOISE

HISTOGRAM OF SAMPLES

I~(----------Cry$tai Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581

/

PROBABILITY DISTRIBUTION
FUNCTION

PEAK-TO-: NOISE - - - - -

->

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JAN '95
AN37REV1

5-93

.... ..._..
. ........

..,
..,..,..,
..., ..,..,
...,
INTRODUCTION

Many Analog-to-Digital Converters (ADC) are
used to measure the level or magnitude of static
signals. Applications include the measurement of
weight, pressure, and temperature. These applications involve low-level signals which require
high resolution and accuracy. An example is a
weigh-scale that can handle up to a 5 kilogram
load and yet resolve the measurement to 10 milligrams. The ratio of maximum load to lowest
resolvable unit is five hundred thousand to one.
This requires the weigh-scale's ADC to digitize a
load cell's signal with a resolution of 500,000
counts.
When working with high resolution ADCs, an
understanding of the error and noise associated
with the conversion process is required. The goal
for this application note is to show how histogram analysis is used to quantify static
performance. Sample sets of data are collected
and used to measure noise and offset. Statistical
techniques are used to determine the "goodness"
and confidence interval associated with the estimates. Averaging is addressed as a means of
decreasing uncertainty and improving resolution.
In an ideal situation, the output of an ADC
would be exact with no offset error, gain error,
nor noise. However, the actual output from the
ADC includes error and noise. Static testing
methods can be used to evaluate the ADC's performance. A dc signal is applied to the ADC's
input and the digital output words are collected.
The signal's level is adjusted to measure offset
and gain errors associated with deviations in the
slope and intercept of the ADC's transfer function. Noise is measured as the variability of the
output for a constant input.
Statistical techniques can be used to acquire performance measurements, assess the effects of
noise, as well as compensate for the noise. An
ADC's output varies for a constant input due to
noise. The noise is defined by a Probability Den5-94

Noise Histogram Analysis

sity Function (PDF), which represents the probability of discrete events. Statistical parameters
can be calculated from the PDF. The PDF's
shape describes the certainty of the ADC's output and its noise characteristics.
Noise histogram analysis assumes that the noise
is random with a Gaussian distribution. This
means that the noise amplitude at a given instant
is uncorrelated with the output amplitude at any
other instant. A sample set of random noise produces a normal distribution which is used to
estimate the PDF. If the noise is not random and
does not have a normal distribution, the following histogram analysis would not apply.
Examples of non-Gaussian noise include lIf
noise, clock coupling, switching power supply
noise, and power line interference.
The ensuing sections discuss noise histogram
analysis and the estimation of unknown parameters. The discussion addresses sampling
requirements, statistics, and performance tradeoffs. Statistical methods are used to determine
"goodness" and confidence intervals of parameters estimated from sampled data. Goodness
relates to how well the sample set parameters
correlate to the actual system. Averaging is discussed as a method of reducing uncertainty and
improving resolution. This paper will lead to an
understanding of sampling issues and the tradeoffs that can be made to improve performance
and the consequences of the various choices
among sample size, confidence level, and
throughput.
NOISE HISTOGRAM DESCRIPTION

Usually the PDF describing the ADC noise is not
specified. The PDF can be estimated by static
testing. This estimated PDF is actually a histogram plot of the occurrences of a random
variable versus the individual variations. For an
ADC, the random variable is the resulting digital
codes, so the frequency at which each code occurs is plotted against each discrete code.
AN37REV1

-__-_-

.. .....
...
. --.-.
....

Noise Histogram Analysis

In a noiseless ADC, the output code for a specific input voltage will always be the same value.
The histogram plot for a noiseless converter is
shown in Figure 1. If noise sources are present
in the ADC, the histogram plot of the output
codes contains more than one value. Figure 2 is
a histogram plot of an ADC with internal noise.
The histogram suggests that the output for a single input can be one of eleven possible codes.

Figure 1. Histogram for a Noiseless ADC

Electrical noise resulting from random effects
forms a Gaussian or normal distribution, which
is a bell-shaped curve called a normal curve. The
Gaussian PDF is continuous and completely determined with the specification of a mean (11)
and variance (02). The Gaussian PDF is defined
by the following equation:

p(x) =

n

Figure 2. Histogram for an ADC with Noise

Figure 3. Histogram and Estimated PDF

AN37REV1

=

n

~21t cr
1

e - (x-Il)'l2a2

for the actual PDF.

Other values for n scale the PDF to fit a sample
set. The data presented in Figure 2 can be used
to estimate the PDF. Figure 3 plots the histogram
of an ADC with noise along with its estimated
PDF. The mean and variance were estimated
from the sample set of data. From these PDF parameters, the ADC's performance can be
quantified. The mean is the expected or average
value. It is used to measure offset errors. The
variance describes the variability of the distribution about the mean. It is used as a measurement
of uncertainty or noise. The square root of the
variance is called the standard deviation (0), and
it is a measure of the effective or rms noise. The
peak-to-peak noise can be determined from the
rms noise value.
The Gaussian PDF can not be used to measure
all types of noise. When using a normal or
Gaussian distribution to estimate the PDF, the
noise must be random. Figure 4 illustrates a histogram of non-random noise. Notice that the
5·95

•

.._-.....-.
--_.._•

.-r _ _ . . ..

Noise Histogram Analysis

[00" I

8

ONe.

RESUenNG
HISTOGRAM

f=>A
[J => ~

i

VOLTAGE

'POOR" DNL

~

8
~

..J

(3

Ci

J

);ARROW
DISTORTSCODE
THE
TSTRIBUTION

VOLTAGE

Figure 4. Non-random Noise Histogram

Figure 5. DNL Effects on a Noise Histogram

histogram distribution does not possess the familiar bell-shape. This histogram is possibly the
result of 60 Hz line interference or other type of
sinusoidal noise. The PDF resembles that of a
sine wave, which has a "cusp-shaped" distribution.

negative seven to positive five. Since the digital
codes vary by more then one count, the system
noise exceeds quantization error causing an uncertainty associated with the output. The range
of code variations requires the histogram to contain at least thirteen discrete ranges or cells.
Table 1 lists the number of occurrences of the
fifteen cells used to create the histogram.

Figure 5 is another example of a PDF not having
a Gaussian shape. Here, the reason is due to the
ADC's poor differential nonlinearity (DNL).
Poor DNL results in uneven code widths, which
skew the distribution. Delta-Sigma and self-calibrating ADCs possess good DNL specifications.
Good DNL is very important for applications
which use averaging to improve resolution.
The histogram must possess a bell-shape distribution or the estimated Gaussian PDF will not
correlate to the actual system. It is good practice
to view the noise distribution and verify that random noise is being analyzed. If the noise is not
random, the Gaussian PDF equation can not be
used to model the histogram.
EXAMPLE
Figure 6 is a noise histogram of .a 20-bit ADC
with a grounded analog input, and ± 2.5 volt input range. For an ideal, noise free system, the
expected output would always be zero. However,
the experimental 1024-sample set ranges from
5-96

A PDF can be estimated by using statistical
functions to characterize sampled data. Assuming
the system noise is Gaussian, the noise can be
measured by collecting a set of n samples from a
normal population with mean (f..L) and variance
(j2) and calculating the sample mean (X) and
sample variance (S2).

x

n

1
n

I, Xi
i

=1

n

i= 1

n-l

AN37REV1

_-_
....
_.-......__
..._.-.
..,

Noise Histogram Analysis

24B.-____________________H~I~S~T~O~G=RA~M~____________________~

18B~----------------------

12B~-------------------

SB-r--------------

B+--...--....L-8

-7

-S

-5

-4

-3

-2

-1

1

2

3

4

5

S

Figure 6. Noise Histogram for a 20-bit ADC

CELL
Occurrences
Table 1. Data for Histogram in Figure 6
-

2

2

X aI)d S are estimators for the system J.L and 0' .
This information is used to create a mathematical model of the system's PDF. From the sample
set of data used to create Figure 6, X = -0.98
and S2 = 3.96. The PDF for Figure 6 can be
modeled by substituting n, X, and S2 into the
scaled Gaussian PDF equation.

Figure 7 overlays the estimated PDF over the
histogram of 1024 samples shown in Figure 6.
Notice that the PDF and histogram are highly
correlated and the estimated PDF seems to be a
good model of the actual system.

Substituting X for J.L, S for 0', and S2 for 0'2.

The sample mean in Figure 7 is -0.98 counts. A
perfect ADC, operating in the same mode with
its input grounded, has a mean of zero. Such a
mean deviation from ideal is called an offset. In
terms of voltage, the ADC's Zero Offset in
Figure 7 is -0.98 counts or -4.67 J.LV

(x)

=

P

AN37REV1

1024
e - (x+O.98)'l(2
1.99

~21C

* 3.96)

Continuing with the assumption that the data in
Figure 7 has a normal distribution, the performance of the ADC can be quantified using the
measurements based on estimates for the mean
and standard deviation.

5-97

I

I

~

....-.........
-.....-..
.............
.."

Noise Histogram Analysis

240.-__________________~H~IS~T~O~G=RA~M~______________~----~

X = -0.98
S = 1.99
S2= 3.96

180+-------------------~

120-~-----------------

60+-------------

o-l==--;=::::I~L
-8

-7

-6

-5

-4

-3

-2

-1

o

1

2

3

4

5

6

Figure 7. Histogram and Estimated PDF

(1 count = 5 volts 1220)) . The Full Scale Error is
measured in a similar manner, by calculating a
mean for a full-scale input signal.

56.93 llV peak-to-peak. Since these values are
calculated from sampled data, a degree of uncertainty is associated with the estimated
performance.

The PDF's shape, which is used in noise calculations, is defined by. the sample variance or its
positive square root called the sample standard
deviation (S). The standard deviation of a noise
distribution is a measure of the rms or effective
noise. In Figure 7, the rms noise is 1.99 counts
or 9.49 llV. Additionally, the peak-to-peak noise
can be calculated by using the standard deviation. Peak-to-peak noise is defined as the interval
which contains six standard deviations. For a
normal distribution, this interval represents
99.6% of the occurances. In Figure 7, the peakto-peak noise is 11.94 counts or 56.93 llV.

Using statistics, confidence intervals can be calculated for the estimated performance values.
First a confidence interval for (52 is described.
The accuracy of the model derived from sampled
data depends upon how well the sample set resembles the actual system. The sample
distribution alone is not useful in determining
how well the sample variance correlates to the
actual variance. However, a confidence interval
can be obtained from the sample data. If the degrees of freedom (v) and the actual system
variance (~) are included with S2, then the ran-

CONFIDENCE INTERVAL ESTIMATE

dom variable [(n-l)~/i] has a chi-squared
distribution with v degrees of freedom, where
v = n-l for n number of samples.

In the preceding section, the performance of an
ADC was quantified from a sample set of data.
For the data in Figure 7, the offset is calculated
at -4.67 llV, and the noise at 9.49 llV rms and
5-98

2

S2

X =(n-l)(52
AN37REV1

_........
-..,...-..
-............

Noise Histogram Analysis

By treating the variance as a chi-squared variable, the variance PDF becomes a function of the
degrees of freedom. Now the chi-squared distribution can be used to determine the accuracy of
S2 and state (12 as a confidence interval.
Chi-squared percentiles can be obtained from
statistics tables. Statistic tables may not be available for large sample sizes. Fortunately, as the
number of samples or degrees of freedom increases, a chi-squared distribution approaches a
normal distribution. A good approximation of a
chi-squared percentile, X2(a.;v), in terms of a
standard normal percentile [z(a.)] is given by:

x2 (a ; v) '" 0.5 ( z(a)+-V2v-I)2

,v> 100

From these numbers, it can be stated that X2 has
a 0.5% possibility of being less than 909.37 and
99.5% possibility of being less than 1142.26.
Combining these two conditions, X2 has a 99%
possibility of being greater than 909.37 and less
than 1142.26.
Finally, a 99% confidence interval for (12 is obtained by substituting (n-l) S2/ri for l. Here the
values n = 1024 and S2 = 3.96 are used to further illustrate Figure 7.
909.37 < X2 < 1142.26
909.37 < (n-I) i/,/ and (n-I) ilr/ < 1142.26
2

82

S2

2

In the above formula, £is a function of a = area
under the left tail of the standard normal curve
and v = degrees of freedom.

(1 < (n-I) 909.37 and (n-I) 1142.26 < (1

For example, a 99% confidence interval is determined for X2 when n=1024:

The calculated sample variance (S2) is 3.96
LSB 2s. There is a 99% confidence that the actual
system variance «(12) is between 3.55 and 4.45
LSB 2s. The uncertainty associated with 3.96 is
less than a half LSB 2 (4.45 - 3.96 = 0.49). That
is to say the maximum error is 0.49, with 99%
confidence.

Covering 99% of the total area leaves 1% uncovered, which is divided equally between the left
and right tails. Thus the desired percentiles are
a = 0.005 and a = 0.995. From a table for a
Normal Distribution curve, the corresponding
percentile points z(a) are -2.575 and 2.575 respectively. Thus 99% of the area under the
standard Normal Distribution lies between -2.575
and 2.575.
Substituting values for

z(a) and

v

in the

x2(a;v) formula, a range of X2 values is calcu-

lated.

x2 (0.005 ; 1023)

= 909.37

x2 (0.995 ; 1023)

= 1142.26

AN37REV1

3.55 < (12 < 4.45

If the confidence intcrval or uncertainty is unac-

ceptable, adjustments can be made. Notice that
the interval width is effected by two variables
z( a) and n. The interval width can be reduced by
either increasing the sample set size or tolerating
more uncertainty.
The following calculations using peak-to-peak
noise show how z(a) and n affect the confidence
interval. Peak-to-peak noise is the uncertainty associated with a single sample. Above, the 99%
confidence interval was calculated for the variance. In Figure 7, the estimated variance is
between 3.55 and 4.45 with 99% confidence.
5-99

I

~\
_

-

.

..........
.....,--.............
~

Noise Histogram Analysis

Confidence

Number of
Samples

Ot

z(Ot)

X2

cr'2- Range

99%

1024
1024

99%

2048

95%

2048

z(0.005) = -2.575
z(0.995) = 2.575
z(0.025) = -1.96
z(0.975} = 1.96
z(0.005) = -2.575
z(0.995) = 2.575
z(0.025) = -1.96
z(0.975) = 1.96

909.37
1142.26
935.79
1113.06
1885.08
2214.55
1923.03
2173.81

3.55 < cr'2- < 4.45

95%

0.005
0.995
0.025
0.975
0.005
0.995
0.025
0.975

3.64 < CJ2 < 4.33
3.66 < cr'2- < 4.30
3.73 < cr'2- < 4.22

Peak-toPeak
Noise Ranoa
11.30 to
12.66
11.45 to
12.49
11.48 to
12.44
11.59 to
12.33

Table 2. Degree of Confidence and Sample Size Effects on the Confidence Interval

This interval can be translated for peak-to-peak
noise:
peak-to-peak noise =30- + 30- =606 '1/3.55 < peak-to-peak noise < 6 '1/4.45
11.30 < peak-to-peak noise < 12.66
(99% Confidence Interval)
The width of this confidence interval is 12.66 11.30 = 1.36 counts. If the confidence is relaxed
to 95%, 2 (a;v) is recalculated using a = 0.025
and a = 0.975. This results in the confidence
interval width for peak-to-peak noise being reduced by 0.32 counts:

x

11.45 < peak-to-peak noise < 12.49
(95% Confidence Interval)
If the set is increased to 2048 samples and the

x

sample variance remains at 3.96, 2(a;v) is recalculated using v = 2047 and the 99%
confidence interval becomes:
11.48 < peak-to-peak noise < 12.44
(99% Confidence Interval)
The original 99% confidence interval is reduced
from 1.36 to 0.96 counts by increasing the sample set. As seen, thousands of samples may be
required to reduce the peak-to-peak noise confi5-100

dence interval to an acceptable width. The size
of the sample set depends upon system capabilities and performance requirements. Large data
sets are affected by memory size and processing
capabilities of the data collection equipment, and
ADC throughput. Table 2 indicates how the degree of confidence and number of samples affect
the confidence interval.

AVERAGING
Once the ADC noise has been characterized, the
effect of averaging can be analyzed. When samples are collected, the average or sample mean
(,X) is an estimator of the population mean (J..l).
X is likely to estimate J..l very closely when the
sample size is large.
Again a confidence interval describes how
closely X estimates J..l, and the sample size governs the width of the interval. The distribution of
2

X is Gaussian with a mean J..l and variance~.
n

In

the case where the ADC output is not Gaussian,
the distribution of X will approach the above
gaussian distribution as n gets large, by the
Central Limit Theorem. The confidence interval
for J..l is:

AN37REV1

.- ..........
...............
..,,-._..

~

Noise Histogram Analysis

~

-

0"

-

X - z(a.)...r,; < ~ < X + z(a.)

0"

...r,;

where a is set by the confidence interval.
Note that z(a.) 0" is the peak noise and 2 z(a.) 0" is
the peak-to-peak noise value. Restated, the actual
mean differs from the sample mean by a range
of the peak-to-peak noise divided by the square
root of the number of samples. Thus averaging
multiple samples reduces the error by Y-./n.
II

,..

=X- +- peak-noise
...r,;

The peak-to-peak noise of the sample set for
Figure 7 is 11.94 counts. If one sample is taken,
the 99.6% confidence interval is 11.94 counts or
± 5.97 counts. If all 1024 samples are averaged,
the actual population mean is between -1.17 and
-0.79 with a 99.6% confidence. The uncertainty
is reduced to ± 0.19 counts. Note that the quantization error for an ideal ADC produces an error
of ± 0.5 counts. Averaging 1024 samples improves this noisy 20-bit ADC's accuracy to better
than 21 bits!
As shown above, averaging can reduce the effects of Gaussian distributed noise as well as
quantization error. However, the tradeoff is in reduced throughput. To get the confidence interval
to less than one count, ...r,; has to be greater than
the peak-to-peak noise. For the sample set of
data plotted in Figure 7, 143 samples ( 11.942)
need to be acquired and averaged. Over 36,496
samples are required to create a 24-bit ADC with
less than one count of peak-to-peak noise (reduce the uncertainty of a 20-bit converter to

AN37REV1

±1I32 counts). This would reduce a 100kHz,
ADC to an effective throughput of 2.74 Hz. Averaging sacrifices throughput for improved
resolution and reduced uncertainty.
CONCLUSION

Statistical methods are available to measure the
performance of an ADC. The testing involves inputting a noise free, accurate DC signal to the
ADC and collecting a sample set of data points.
The sample set is used to calculate estimators for
the mean and standard deviation. More statistics
are used to decide the "goodness" and confidence level associated with the estimates.
Averaging was introduced for reducing uncertainty and improving resolution. However,
averaging reduces the ADC's effective throughput. Figure 8 illustrates the tradeoff between
reducing uncertainty and lowering the effective
throughput.
The same methods used to measure an ADC's
performance can be used to measure the performance of an entire system which includes
additional components containing multiple noise
sources and offsets. During system integration or
production test, tests can be performed as subsystems are added. This can be used to measure
the performance of individual subsystems or isolate problems to a subsystem or component. The
results can then be used with compensation techniques to improve system performance or to
determine corrective actions.

5-101

.-......_
............
......
-...
~

.-

Noise Histogram Analysis

TABLE OF VARIABLES

Area=1-cx

Il

mean
standard deviation
c? variance
p(x) probability density function
(J

sample mean
sample standard deviation
sample variance

o

-Zc

Zc

PDF for a Gaussian random variable. The area 1 - a; is the confidence inlelval

Area=1-cx

chi-squared variable
number of samples
degrees of freedom.
area under the normalized curve
standard normal distribution

o

x2a
PDF for a Chi-Square variable. The area 1 - a; is the confidence interval

Effects of Averaging Multiple Samples
100~~------------------------------------,

10

---------------------------

-------------

~
:;

a.

.c

=

-----------------------------------------

:::I

~

0.1

---------------------------------------

0.01 +----+----+----+----+----+----+----+----+---+-----------j
20
40
60
80
100
o
Reduction in Uncertainty (0/0)

Figure 8. Tradeoff between Uncertainty and throughput

5-102

AN37REV1

. ___

.._.. ...
.........
....
.,,~-

Noise Histogram Analysis

REFERENCES
[1] John Neter, William Wasserman, & G.A.
Whitmore, "Applied Statistics" Allyn and Bacon,
Inc.
[2] Ronald E. Walpole & Raymond H. Myers,
"Probability and Statistics for Engineers and Scientists", Macmillan Publishing Co., Inc, New
York,1978.
[3] Richard H. Williams, "Electrical Engineering
Probability", West Publishing Company.
[4] Ferrel G. Strernler, "Introduction to Communications Systems",Addison-Wesley Publishing
Company, Inc. 1982.

lIIIi

AN37REV1

5-103

....._.-.
..... __. .........
..,,-

..,,_

Noise Histogram Analysis

• Notes.

5-104

AN37REV1

...
.
...,...,..,......
.
...
~~

."."

.,,~

AN33

."

Semiconductor Corporation

Application Note
Clock Options for AID Converters
by
Jerome Johnston

give instructions regarding the size of any
extemalloading capacitors.

Most NO converters require a clock source for
operation. Some converters, such as the
CS5101A, CS5102A, CS5501/3, and the
CS5504/5/617/8/9 include an on-chip gate
oscillator as shown in Figure 1. A
Pierce-oscillator architecture is commonly used.
It is constructed with either on-chip loading
capacitors (C2 and C3 in Figure 1) or it may
require off-chip loading capacitors (C4 and C5)
depending upon the crystal frequency. The data
sheet for the particular NO converter should

System applications may require the NO
converter clock to drive other circuits; or the
measurement system may require two or or more
NO converters to be driven from the same
clock. It is always preferable for one common
clock to be used for the entire system. With one
system clock, any interference will be
synchronous and will generally be less severe.

On-chip gate oscillator

+5
XIN

crystal model

74HCT14
~{

~5

~s

~:-----------------:~
Figure 1. Using 74HCT14 Gate to Buffer Oscillator Output

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 Fax: (512) 445-7581

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

AUG '94
AN33REV1

5-105

.......,..,• .....
•..,..r..,
• _ ..
....
..,..,~

Clock Options for AID Converters

To drive external circuitry from the on-chip
oscillator of an AID converter use the XOUT or
CLKOUT pin. Although the on-chip oscillator is
shown as an inverter gate, this does not mean
that it can drive external circuitry very well. The
gate oscillator circuit is optimized for low gain
to facilitate building a stable oscillator; and the
circuit may be optimized to minimize power
dissipation in the oscillator. For example, the
on-chip oscillator of the CSSS04/S/6n18/9
devices uses only 10 !JA of supply current. It is
therefore necessary to buffer the oscillator output
with a high impedance gate input such as CMOS
logic. The CSSS04/S/6n18/9 devices work well
with a 74HCTl4-type gate. The HCT threshold
is required as the oscillator output oscillates
between 0 - 2.S volts. The external gate should
be located very near to the XOUT pin of the
converter to minimize stray capacitance. The
same technique can be used with the
CSSlOIA102A and CSSSOI/03 converters.
When using external loading capacitors (C4 and
CS in Figure 1) and an external gate to buffer
the oscillator output, the value of CS should be

lowered by the estimated input capacitance of
the CMOS gate input and any additional stray
capacitance. For example, the oscillator by itself
may call for CS to be 30 pF. But if the oscillator
output is driving an external CMOS gate, the
gate input may have S-IO pF of input
capacitance and there may be 1-4 pF of stray
capacitance. Under these conditions the value of
CS should be lowered, say to 22 pF, so that the
total capacitance seen at the output of the
on-chip gate oscillator is maintained near 30 pF.
Some applications may use a central oscillator
which is then distributed as shown in Figure 2.
The oscillator may use a logic gate, a clock
module, or an oscillator chip such as the Harris
HA72lO. Buffers are then used to drive the
system circuitry. To minimize clock jitter, the
power supply to the oscillator, whether it be a
gate or a module, should be decoupled with an
RC filter to keep any noise on the power supply
from reaching the oscillator.

+5V

~74H~rU04~
74HC04
Figure 2. External Oscillator using Buffers for Distributed Clock

5-106

AN33REV1

_- ...-.
-..................
.....__
Working with gate oscillators can present some
difficulties. For example, just looking at the
output with a scope probe loads the oscillator
with the probe capacitance. This can change the
oscillator frequency, the signal amplitude, or
even cause the oscillator to quit oscillating. Use
a low capacitance or active probe if possible. A
series resistance can be added between the
circuit and a standard probe to minimize the
effects of the scope capacitance as shown in
figure 3. Choose R to be 5-10 times greater than
the impedance of the output loading capacitor (at
the frequency of oscillation).
Customers have asked whether the on-chip gate
oscillators used in Crystal AIDs call for series or
parallel-type crystals. The only difference
between series and parallel-type crystals is the
method by which their fundamental frequency is
calibrated. The frequency at which series crystals

Clock Options for AID Converters

are calibrated to oscillate is a function of the
crystal's internal inductance (LI) and its internal
series capacitance (CI) of figure 4. These
resonate in series to produce zero phase shift
through the crystal network. Series-mode
oscillators use non-inverting amplifiers.
Parallel-mode crystals are calibrated using the
crystal's internal inductance and its internal
parallel capacitance in parallel with external
loading capacitors.
Parallel-mode oscillators
require an inverting amplifier which contributes
180 degrees phase shift along with the 180
degrees phase shift contributed by the network
composed of the crystal and the loading
capacitors.
All of the converter chips mentioned in this
application note use parallel-mode oscillators,
but either series or parallel mode crystals will

scope probe

Figure 3. Isolate Scope Probe Capacitance to prevent Oscillator Loading.

AN33REV1

5-107

.... ..._....
. ........
....
~

~~,..,

Clock Options for Alb Converters

~~

oscillate. When using a series-mode crystal in
parallel mode, its oscillation frequency may be
off a small percentage, never more than 0.5%.
This will not cause problems unless the clock is
used for time-keeping purposes.

parallel crystal may be specified as 8.000 MHz
(20 pF); meaning that the crystal will oscillate at
exactly 8.000 MHz if loaded with exactly 20 pF.
This would require C2 and C3 of figure 5 to be
2 X 20 pF (39 pF typical). This is because the
capacitors are series-connected, which divides
the effective capacitance.

Parallel resonant crystals always require a
specified load capacitance. For example, a

f-

1
- 21rVLICI

crystal model
~

•

-

-

-

-

-

-

L1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

.f_

R1

Figure 4. Series Resonant Crystal Oscillator.

f=..L "';_1_ + _1_
21t LICI LICT

.. cry's~al. r:n.odel.
L1

CT= C0+ _C..:...2_X_C..:...3

C2+C3

R1

Figure S. Parallel Resonant Crystal Oscillator.

5-108

AN33REV1

......
..............
..........
~~~

AN30

Semiconductor Corporation

Application Note
Switched-Capacitor AID Converter Input Structures
by
Jerome Johnston

CMOS has become popular as the technology
for many modem AID converters. CMOS offers
good analog switches, good capacitors (although
size is limited), and high digital logic density.
These features have been combined to achieve a
number of different AID converter architectures.
Many SAR-type (Successive Approximation
Register ) CMOS AID converters utilize ratioweighted capacitors, all controlled by analog
switches and digital logic, to achieve conversion.
Delta-sigma converters use analog switches and
small capacitors for sampling. Conversion in a
CMOS delta-sigma AID converter is performed
using a switched-capacitor comparator which
samples at a much higher speed than the bandwidth of the signal to be converted. The
comparator then presents a stream of ones and
zeros to be processed to the digital filter portion
of the chip. High CMOS logic density allows
the digital filter to be orders of magnitude more
complex than an analog filter while being driftfree and exactly repeatable from chip to chip.
The analog input of most CMOS AID converters
is constructed with analog switches and capacitors. Figures 1, 2, and 3 illustrate input structures
commonly found in CMOS or BiCMOS AID circuits. These three structures are common to
capacitive-type SAR converters and to deltasigma converters.
Figure 1 illustrates an unbuffered capacitive
sampler. The size of the sampling capacitor and
the frequency of the switch closure will deterCrystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 462-2723

Figure 1. Unbuffered Capacitive Sampler

III
i

Figure 2. Unbuffered Capacitive Sampler
with Resistor Input

~ fine

-.l

Figure 3. Coarse Charge Buffered Capacitive Sampler

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

JAN '95
AN30REV1

5-109

-. .. .. ...._.-.
-..,.,

~.-

~~-

~~

mine the severity of the dynamic load seen by
the driving amplifier.
Figure 2 illustrates a capacitive sampler with an
input resistor added. Input resistors are used in
some AID converters to divide down the input
signal; for example, reducing flO volts down to
±2.5 volts. The signal reduction allows the circuitry internal to the converter to be powered
from ±5 volts and still handle high level input
signals. The resistors may introduce gain errors
over temperature because of their limited tempco
tracking. One bit at 16 bits is only about 15
ppm. The closest tempco tracking of the best resistor technologies is about 2 ppm/0C,
Some converters may use a single resistor at the
input. The resistor reduces the transient current
impulse seen by the external driving amplifier.
The resistor also enables the external drive amplifier to see a resistive load instead of a more
capacitive load. This improves the amplifier
phase margin and reduces the possibility of ringing. The resistor enables the transient load current
from the sampler to be spread over time due to the
RC time constant of the circuit. A series resistance
is usually acceptable in 12-bit designs, but it can
hinder performance in fast 16-bit converters. The
settling time of the RC network can limit the speed
at which the converter can operate properly or reduce the settling accuracy of the sampler.
Figure 3 illustrates a coarse charge (also called
rough charge) buffered capacitive sampler. The
on-chip coarse charge buffer reduces the dynamic current demanded from the signal source
because the coarse charge buffer precharges the
sampling capacitor to a voltage nearly equal to
the input signal.
The input structures in Figure 1 and 3 are most
common. To understand the drive requirements
of these two circuits, the input current required
by the unbuffered sampler will be examined and
its effective input resistance will be determined.

5-110

Switch-Capacitor AID Converter Input Structures

Then it will be compared to the input current
and effective input resistance of the coarse
charge buffered sampler.
In Figure 1 the sampling capacitor, C is switched
at a fixed frequency, f. The capacitor transfers a
specific amount of charge each time the capacitor is switched. This charge is furnished by the
signal source outside of the chip.
The size of the sampling capacitor and the frequency at which it is switched will determine the
input current, and therefore, the effective input
resistance of the sampler. Using the fundamental
equations:
i =.9..
t

q=cV

The instantaneous current is equivalent to the
char ge per unit time and char ge is equivalent to
the product of the capacitance and voltage, an
equation which defines the input current to the
unbuffered sampler (figure I )can bedeveloped:
i=C dV
dt
i

=C(VO -

VI)/ ~t =C(VO - Vr)f

Rearranging the equation, the effective input resistance can be shown to be:

From this equation it can be seen that the effective input resistance is inversely proportional to
the sampling clock frequency. This indicates that
if this sampler is part of an AID converter which
can operate over a wide range of clock frequencies, that as the device is operated at higher
frequencies the input resistance goes down. This
results in higher input current. Errors can be introduced because of the source impedance of the

AN30REV1

_- .

.... ...
. --.......
....
.."

.."..,,~

Switch-Capacitor AID Converter Input Structures

external driving circuitry. Circuit behavior
should be fully evaluated at whatever clock rate
the circuit is going to be operated.
The coarse charge buffered sampler is shown in
Figure 3. When the coarse switch is on (fine is
off), the buffer coarse charges the capacitor to a
voltage approximately equal to the input source
voltage VI. The advantage of the buffer is that
the majority of the charging current needed to
charge C is supplied by the coarse charge buffer
and not by the signal source. This greatly reduces the current demand from the source
outside the chip. The actual voltage output from
the buffer will include whatever offset voltage
exists in the buffer. When the coarse switch is
off and the fine switch is on, the signal source
will supply the current necessary to charge the
sampling capacitor to its final value.
From the circuit the following equation can be
derived for the input current:
i = Vas/(lIfC) = fC Vas

where lIfC is the effective resistance of the
switched capacitor circuit.
The equation indicates that the input current is
independent of the input voltage and is a constant current which is a function of the sampling
capacitor, the operating frequency, and the offset
voltage of the buffer. Note that the polarity of
the input current is affected by the polarity of the
coarse charge buffer's offset voltage.

__

AIN

It is easy to see the advantage of a buffered sam-

pler over an unbuffered sampler. In the buffered
version of the sampling circuit, the signal source
must furnish only enough charge to compensate
for the offset of the buffer; whereas in the unbuffered sampling circuit (Figure 1), the signal
source must furnish all of the charge necessary
to charge the sampling capacitor.
This discussion has assumed that the sampling
capacitor in each of the sampling circuits is fully
discharged each time it is connected to the output circuit. Sometimes the output circuit is
designed in such a way that it leaves the sampling capacitor charged at some particular
voltage. This will affect the amount of charge
that the unbuffered sampling circuit requires
from the signal source.
The behavior of these sampling circuits will be
affected if additional components are added between the outside driving amplifier and the input
to the sampler. Two possible situations will be
examined. First, the effect of adding a series resistance between the external drive amplifier and
the AID input will be investigated. Then the effect of adding a series resistor and a filter
capacitor between the driving amplifier and the
AID input will be examined.

Effects. of an External Resistor
Using the circuit illustrated in Figure 4, the behavior of the coarse charge buffered sampler will
be examined with a resistor added between the
output of the external signal source and the input
2

~ VV\~-'--~~----~~~

1
Vi =0 -=-

T

"V

iD

..

,·c

~ Stray = 0

Vos 1

81

.

~

~-r=- "6
rCs
'V

Figure 4. Buffered Sampler with
External Source Resistance.

AN30REV1

5-111

.. .. .

......,..,
__ ._.
....
..,~

..,..,~.

Switch-Capacitor AID Converter Input Stru.ctures

~

AIN
2
.-~~~~--o-~------~~~

.

~

~1-1::_- "b

Vos 1 81

:&Cs

Figure 5. Buffered Sampler with External RC Filter.

to the sampler (Similar equations could be developed for the unbuffered sampler, but will not be
done here). Assume that the input voltage VI = 0
(the result will be the same for any constant input signal as the offset of the buffer is what
dictates the charge requirement to settle the sampling capacitor to its final value). When the
switch is in position 1, the sampling capacitor is
charged to the voltage at the output of the internal buffer. Assume the offset of the buffer is
such that the voltage on the sampling capacitor
is a positive value, which will be called Vos.
When switch S I changes to position 2, the voltage on the sampling capacitor discharges to zero
through the external source resistance (and the
resistance of the switch if its value is significant
relative to RF).
The internal sampling circuit will settle to full
accuracy in the time that switch S I is in position
2 if the external source resistance (Rp) is sufficiently low. The time available for settling is a
function of the clock running the sampler. The
sampler is usually connected to the input pin for
one half clock cycle of the master clock. If the
external resistance is too large, the sampling capacitor will be left with an error voltage when
the sample time ends.
If the time that switch S 1 is in position 2 is one
half of a clock cycle, the voltage on Cs will discharge exponentially through source resistance
Rp for tl2 where t is the period of one full clock
cycle. The maximum source resistance for a
given error voltage VE is:

5-112 .

t

Va = Vas e'2/RpCs
In(VE)_ -Y2
Vas -RpCs

In(VaS)=~
VE
RpCs
RPmax -

I

(vas)

2fCsin VE

Effects of an External RC Filter
The case with an RC-filter placed at the input of
the sampler will now be examined. Figure 5 illustrates this case.
The circuit will be analyzed with VI =0 (the result will be the same for any constant input
signal as the offset of the buffer is what dictates
the charge requirement to settle the sampling capacitor to its final value). When the switch is in
position I, the sampling capacitor is charged to
the voltage at the output of the buffer. Assume
the offset of the buffer is such that the voltage
on the sampling capacitor is positive value called
Vos. When at steady state
VCs = Vas S I is in position 1.
VCs = VCp S I is in position 2.

AN30REV1

_. ...,--_
__.. ...-..
-~

--~

The charge transfer rate from Cs to Cp during
each clock cycle is
L\q=Cs(Vas- VCF)

Since i = L\q , ics = Cs (Vas -VCF) and : = f ;
Llt
L\t
ut
Therefore ks = fCF(VOS - VCF)
In the steady state condition,
ks = iD
Therefore

where VCF is the error voltage VE.
Therefore, for a given error voltage the maximum Rp should not exceed
Rp<

VE
fCS(VOS - VE)

The equation applies only if
1
f » RC

An external RC filter in front of the sampler
lowers the bandwidth of the circuit and therefore
reduces input noise. It also acts to isolate the
transient current demand of the sampler from the
external drive amplifier by allowing the sampler
to draw its transient current out of the filter capacitor. This greatly reduces the transient current
seen by the drive amplifier. Therefore, the amplifier is less likely to ring or overshoot due to the
transient load. Adding an external RC filter can
be detrimental if it has an excessively long time
constant. This can cause the source resistance of
the filter to introduce an offset error.

AN30REV1

Switch-Capacitor AID Converter Input Structures

When an external amplifier drives either the unbuffered, or the buffered sampler directly, the
amplifier may have difficulty with the transient
load conditions. The transient load may cause
the amplifier to exhibit ringing or oscillation.
The behavior of the amplifier may vary as the
signal amplitude changes; with the most common problems occurring with signals near zero
crossover. A common symptom is for a user of a
high speed AfD converter to suspect the converter of having a nonlinearity or of having
missing codes in its transfer function; but the actual problem is that the driving amplifier is
ringing and failing to settle at the proper signal
level before the sample capacitor captures the
signal. Some amplifiers will have more difficulty
than others. An amplifier which exhibits peaking
in its closed loop response will generally have
more problems. To minimize the possibility of
ringing, choose an amplifier which has gain rolloff which is linear for at least one decade of
frequency above the frequency where the closed
loop gain intersects with the open loop gain response. The amplifier circuit should be chosen or
designed to achieve low output impedance at the
sampling frequency of the capacitive sampler. A
wideband amplifier with good drive current capability works best with a high speed AfD. The
transient load seen by any amplifier can be reduced if an RC filter is added between the
output of the operational amplifier and the input
to the switched-capacitor sampler. The values for
the resistor and capacitor are usually recommended by the AfD manufacturer. Making the
time constant too large can reduce settling accuracy or produce an offset error in the circuit.
Other Circumstances Which Alter Input
Behavior

Various AfD converter input structures have been
discussed. It has been shown that the input seen
by the external driver depends upon the size of
the sampling capacitor, the sampling frequency,
and whether or not the input is coarse charge
buffered. The effect of an external source resis5-113

.~

,

-... .... .... _......
~-

-~

~~

~~

tance and the effect of an external RC filter have
been discussed.
There are additional circumstances which can affect the input impedance. From the equation for
the switched capacitor input impedance
(R = lIfC) it is readily understood that the dynamic load will change if the clock frequency to
the sampler is changed. There are several conditions in which this can occur. The most common
condition is that the master clock to the converter is modified. An example of this occurs in
some applications of the CS5501lCS5503 converters. The CS550l/CS5503 converters include
a low pass digital filter which has a -3 dB comer
frequency of 10Hz when operated with a master
clock frequency of 4.096 MHz. If the clock frequency to the converter is lowered the comer
frequency is reduced proportionately. Some
measurement systems allow the user to select a
slower converter clock to reduce the noise band
width of the converter. This allows the converter
bandwidth to be optimized for the noise conditions in the circuit. This change in clock rate will
change the behavior of the input of the converter. This change in dynamic behavior can
interact with the external driving circuitry and
introduce errors in the measurement.

Switch-Capacitor AID Converter Input Structures

of the capacitor sampler. Either of these will alter the converter's input impedance if the gain
change is performed at the input stage of the
converter. The CS5516 and CS5520 include a
PGA, but it is placed after an input instrumentation amplifier. The instrumentation amplifier
input impedance remains constant when the PGA
gain is changed. Products from other vendors
modify the input stage to accomplish gain
changes and therefore alter the input impedance
of the converter.
This application note has discussed the drive requirements of CMOS AID converters. While the
discussion has been applied to the input for the
signal to be converted, realize that this discussion can apply to the voltage reference input pins
of the converter as well.

Input impedance can also change due to sampling clock changes which occur in converters
that allow the user to modify the output word
rate of the converter. Some first generation audio
codecs would change the sample clock of the input stage whenever a different word rate was
selected. Newer codecs keep the input stage
sampling clock constant when the output word
rate is changed.
Another example of the converter's input impedance being affected, can occur in instrumentation
converters which include a PGA (Programmable
Gain Amplifier) stage as part of the input stage
of the converter. These converters allow the gain
to be modified by changing the size of the sampling capacitor, or by modifying the sample rate
5-114

AN30REV1

..
.
...,........
..,
......
.
.. ......,
~

AN4

~

Semiconductor Corporation

Application Note
Voltage References for the CS5012A / CS5014 /
CS5016/ CS5101A1 CS5102A / CS5126
Series of AID Converters
by
Bruce Del Signore & Steven Harris
+5V

10n

Analog O - - - - - + - - - -__-----A
Supply

BP/UP

Analog
Signal
Source

Signal
Conditioning

ClKIN
AIN
SDATA
SClK

AID

CONVERTER

V+

Clock
Source

00-015

Serial
Data
Interface

-

Data
Processor

EOC
VREF

EaT
HOLD
CAL
INTRlV
CS

Control

RD
AO
RESET
TST
DGND
VO-

-5V
Analog o----------------<>---------*"---v
Supply

Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 462-2723

l T
JULY '94

Copyright © Crystal Semiconductor Corporation 1995
(All Rights Reserved)

AN4REV5
5-115

.- ..........
...........
.............

Voltage References forSAR-type AID Converters

INTRODUCTION
This application note discusses voltage references
for use with Crystal Semiconductor's successive
approximation series of AID converters. Reference design considerations, a design example and
suggested reference circuits are explained in detail.

positive temperature coefficient. At some specific
current level, these two effects cancel each other
and the temperature coefficient of the zener breakdown voltage is zero. As the ambient temperature
changes, one of the breakdown mechanisms becomes dominant and the the reverse-biased diode
voltage will exhibit a temperature coefficient.
Bandgap Reference

Voltage references provide accurate voltages for
use in data acquisition systems in order to establish a basis for conversion. In a data acquisition
system, the value of the reference sets the gain of
the AID stage since the digital output corresponds
to the ratio of the analog input signal to the reference voltage.

In static applications, information is contained in
the signal amplitude, therefore the absolute value
of the reference voltage is important. In many
signal processing applications, information is
contained in the frequency and phase of the signal. Here, absolute value is not as important as
the stability of the reference voltage during conversion.

The second major type of reference is the
bandgap reference. This reference uses the baseemitter voltage (Vbe) of a bipolar transistor as a
basis for operation. The Vbe has a negative temperature coefficient (-2mVfOC). This negative
temperature coefficient is balanced by a voltage
with a positive temperature coefficient of the
same magnitude. This voltage is usually obtained
by using the difference of two Vbe'S of transistors
operating at different current densities. When
both voltages are scaled and summed together,
the result is a voltage which is less sensitive to
temperature. The headroom required for bias and
support circuitry is only a few volts over the output voltage.

Zener-diode Reference

Reference SpecifICations

There are two major varieties of voltage references. The first is the zener-diode based reference
which uses a reverse-biased zener diode operated
in its breakdown region. Most reference zeners
breakdown at voltages between 6.0 and 7.0V,
which limits the minimum supply voltage necessary for operation. When the diode is supplied
with a constant current, it has a constant voltage
drop. Zener references use a zener diode and an
integrated feedback amplifier which provides
constant current, gain, and buffering for the zener
diode.

Voltage references have six important specifications. These are absolute accuracy, temperature
coefficient, long-term reference drift, power supply sensitivity, output impedance, and output
noise.

Zener diodes exhibit two types of breakdown.
The first is zener breakdown which has a negative temperature coefficient and is dominant at
low current levels. The second, avalanche breakdown, occurs at higher current levels and has a
5-116

Absolute or untrimmed accuracy is the difference
between the actual output voltage and the ideal
output voltage. It is specified in millivolts.
Temperature coefficient describes the drift in the
output voltage with temperature. Since this drift
is nonlinear, curve fitting is often used for all
temperatures between those actually tested. Voltage references are available with temperature coefficients as low as I ppmfOC. Inexpensive references are available with 10 to 50 ppmfOC drift
AN4REV5

.._-_
......
-.-_..__
........
..,

Voltage References for SAR-type AID Converters

the reference. The ADC's include an internal
buffer amplifier to minimize the external reference circuit's drive requirement and preserve the
reference's integrity. Whenever the array is
switched during conversion, the buffer is used to
pre-charge the array thereby providing the bulk
of the necessary charge. This buffer enlists the
aid of an external O.IJ..lF ceramic capacitor which
must be tied between its output, REFBUF, and
the negative analog supply, VA-. The appropriate
array capacitors are then switched to the unbuffered VREF pin to avoid any errors due to offsets
and/or noise in the buffer. The external reference
circuitry need only provide the residual charge required to fully charge the array after pre-charging
from the internal buffer. This creates an ac current
load as the ADC sequences through conversions.
The reference circuitry must have a low enough
output impedance to provide the requisite current
without changing its output voltage significantly.
As the analog input signal varies, the switching
sequence of the internal capacitor array changes.
The current load on the external reference circuitry thus varies in response with the analog input. Also with CS5012,4,6 converters, bits are
converted at a IMHz rate with a full speed
(4MHz) clock. The reference must settle within
one microsecond so that it will be accurate before
the next bit is converted. Signal amplitude dependent loading and conversion settling time require the output impedance of the reference to remain low from dc to at least IMHz in order to
ensure good converter performance..

P~lk

The CS5012,4,6 series of converters can operate
with a wide range of reference voltages, but signal-to-noise performance is maximized by using
as wide a signal range as possible. All
CS5012,4,6 converters can actually accept reference voltages up to the positive analog supply.
However, the internal buffer's offset may increase
as the reference voltage approaches VA+. This increases external drive requirements at VREF. Allowing 250mV headroom for the internal reference buffer is recommended. If the supplies are
regulated specifically for the converter, 5.0 volt
references may be used if the supply voltages for
the ADC are kept between ± 5.25 and ± 5.5 volts.
The magnitude of the current load presented to
the external reference circuitry by the ADC's will
vary with the master clock frequency. At full
speed (4MHz clock), the ADC's require maximum load currents of 10J..lA peak-to-peak (lJ..lA
peak-to-peak typical). The voltage reference must
supply this current and maintain adequate voltage
regulation. The load currents scale proportionately with the master clock frequency. Slower
clocks can be used to relax maximum output impedance specification of the reference.
When driving multiple AID converters from the
same reference circuit, load currents will scale
proportionally to the number of converters. Distribute the required decoupling components such
that each ADC is locally decoupled.
A reference with a maximum output impedance
of 2 Q will yield a maximum error of 20J..lV. This
reference could drive aCS50 16 (LSB=69J..lV with

4MHz

2MHz

1MHz

500kHz

CS5012

(Vref=4.5V)

CS5012

(Vref=2.5V)

27
15

54
30

108
60

216
120

CS5014

(Vref=4.5V)

7

14

28

56

(Vref=4.5V)

2

4

8

16

CS5016

All units
in ohms

Table 1. - Maximum Output Impedauce for'" 1/4 LSB Reference Deviation
5-118

AN4REV5

_-_
-- -

.-........__ ...
.....

~

Voltage References for SAR-type AID Converters

The unity gain bandwidth of an op-amp (fo) , is
the frequency at which the open loop gain goes
to unity. If the total phase shift reaches -180 degrees before fo is reached the op-amp will become unstable. The closed loop frequency response peaks at fo. As the total open loop phase
shift at fo approaches -180 degrees, the closed
loop peak at fo approaches infinity. The point of
critical damping is the point where the peaking is
precisely zero. Any phase shift less than this results in no peaking, and phase shift greater than
this results in increased peaking.
Any peaking that might occur can be reduced by
placing a small resistor in series with the capacitors (Figure 2). This resistor adds a left-halfplane-zero (LHPZ) to the open loop characteristic
of the op-amp. This zero increases the gain by
20dB per decade, and adds a +90 degree phase
shift. The resulting reduction in total phase shift
at fo reduces peaking in the closed loop characteristic. The equation in Figure 2 can be used to
help calculate the optimum value of R for a particular reference. The term "fpeak" is the frequency of the peak in the output impedance of
the reference before the resistor is added.
1000 r - - - - , - - - - - , - - - - - r - - - - - - . - - - - - ,

100

(j)

::;;

J:

Q.
w

()

z

10

«c

w

Q.

~
I::J
Q.

I::J

0

0.1

0.Q1

10

100

lK

10K

lOOK

FREQUENCY (Hz)

Figure 3.• Output Impedance Curves for LTI019·5
5-120

Design Example

Figure 3 shows the output impedance characteristic of an LT1019-S reference trimmed to
4.Sv' The three curves represent impedances of
the stand-alone reference, the reference with a
10IlF tantalum and a O.lIlF ceramic capacitor
added in parallel to the output, and the reference
with the capacitors and a 2.2 n resistor in series
with them (See Figure 2). Without loading, the
reference impedance rises above 100 n at SOkHz.
Adding the capacitors, peaking can be seen, but
the maximum impedance is about 13 n at 4kHz.
As shown in Table 1, 13 n is sufficient for use
with the 12-bit converters and for the 14 and 16bit converters with slow master clocks. With the
addition of the 2.2 n resistor, the peak is reduced
to 6 n and the impedance approaches 2.2 n at
high frequencies.
Suggested Voltage Reference Circuits

Nine reference circuits were characterized for use
with the eSS012, eSS014, eSS016, eSS101,
eSS102, eS5126 family of successive-approximation NO converters. Important reference
specifications such as output Impedance and drift
were measured for all references using standard
test techniques. In addition, a Fast-Fourier Transform (FFT) test was performed to characterize
the total dynamic performance of each reference
circuit while driving a eSS016 converter. The
same eSS016 was used for all tests yielding results which allow the comparison between different references. A summary of performance can be
seen in the table at the end of this application
note. During the FFT test, a pure sine wave is
applied to the eSS016 and a "time record" of
1024 samples is captured and processed. The
FFT algorithm analyzes the spectral content of
the waveform and distributes its energy among
512 "frequency bins". Distribution of energy in
bins outside of the fundamental and dc can be
attributed to errors in the NO converter's performance, the reference, or the input sine wave.
AN4REV5

_.-_.........
__.._-_
..._.-.

Voltage' References for SAR-type AID Converters

LT1019-2.5
+7.5.

~

+2.5V

OUT~--~------~--~----+

+15V

6

0'-----1 IN

C2

C1

2

Reference Type
Untrimmed Accuracy
Max Impedance
Total Output Drift
PSRR (SOHz to SOOHz)
Long Term Stability
Output Noise (dc to 1MHz)

GND

4
C1: 10~F tantalum
C2: 0.1 ~F ceramic

S I (N+D) (100Hz)
S I (N+D) (1 kHz)

R2: 2.40 1%

Bandgap
1.2SmV

4.0Q @ S.8KHz
Sppm I DC
90dB

100~V

p-p
87dS
89dS

Figure 6. LTl019-2.5 Reference
+5.0V

LT1021-5
+10

OUT~-r-----r--T----r---+

~ +15V
O'---jIN

6

Total Output Drift

2
TRIM 1-------....--,
GND
5
4

C1: 1O~F tantalum
C2: 0.1~F .ceramic

VRE104

R1: 27kn 1%
R2: 2.20 1%
R3: 50kO Low Drift Pot

+15V

+4.5V

13

O---+PS

GND ~---.--,
7
REFGND

10~F
0.1~F

tantalum
ceramic

Reference Type
Untrimmed Accuracy

3ppm I DC
86dB
15ppm I 1000hr
60iJ.V p-p
gOdS
90dB
Zener

Max Impedance
Total Output Drift

0.5ppm I DC

S I (N+D) (100Hz)
S I (N+D) (1 kHz)

R2: 1.9601%

Zener
2.SmV
3.8Q @ S.OKHz

SOOl-LV
2.SQ· @ 20KHz

PSRR (SOHz to SOOHz)
Long Term Stability
Total Output Noise

6
C1:
C2:

PSRR (SOHz to 500Hz)
Long Term Stability
Output Noise

S I (N+D) (100Hz)
S I (N+D) (1 kHz)
Figure 7. LTI021 Reference

OUT~-----------r--~~--·

11

Reference Type
Untrimmed Accuracy
Max Impedance

100dB
6ppm I 1000hr
80iJ.V p-p
90dB
90dB

Figure 8. VREI04 Reference
r--------------=-6------,

V-

"C"'1;1P--

c(

20

o
10 2

10 4

10 3

10 5

10 6 :_ - --

-20 _ _ _' _ _ _ ~ _ _ lr~~~!!_n~y (~z~ _ _' _ _ _ _: _ _ _ _: _ _ _ _: _ _

-wdjddd
I

- - - - - -

-

I

- - -

-- -

•....•....•.

,

- - -

,

,

-- ---------- -- -

- -

--

-

Figure 2. Bode plot illustrating the relationship of Avo, 13, 1/13, and Avo13

Feedback and the Operational Amplifier Bode
Plot
The feedback parameters which have been discussed can be depicted graphically on a Bode
plot. Figure 2 depicts the relationship between
open-loop gain, the feedback attenuation factor,
noise gain, and loop gain as a function of frequency for the noninverting circuit.
The Bode diagram shows a typical plot of the
open-loop gain characteristic of an operational
amplifier. At very low frequencies a typical operational amplifier may have a dc open-loop gain,
(Avo) near 100 dB. A large number of amplifiers
use dominant pole frequency compensation
which simplifies the compensation requirements
AN6REV5

for the user. The dominant pole, located between
0.1 and 100 Hz on various amplifiers, causes the
open-loop gain characteristic (A) to decrease in
magnitude at a 20 dB/decade rate as the frequency is increased. In Figure 2 the logarithm of
the feedback attenuation factor (P) is shown to be
negative as it is a reduction in signal amplitude.
The loop gain, the product of AP, (or Avop at
dc), is depicted in the figure as the sum ( +100
dB plus -40 dB = 60 dB at very low frequency)
of the open-loop gain and the feedback attenuation factor, or the difference (+ 100 dB - ( +40
dB) = 60 dB) between the open-loop gain and
the noise gain (l/P). From the figure, one can observe that as frequency increases, the loop gain
(AP) decreases for a set value of p. To obtain a
greater amount of loop gain at higher frequencies
5-131

III

_-__.

.-......
............
__

.., ..,

ADC Input Buffers

A2

A1 =A2

Figure 3A. Inverting:
Gain of-1

Closed Loop
Signal Gain
Feedback
Attenuation
Factor

-R2 [

{ACL=m

Rl
Rl+R2

Closed Loop
Corner
Frequency

Figure 3C. Noninverting:
Gain of +1

1 1 AcL=1[1+[1~l]
1 1 ACL= [R1+R2l[
1+[}~l
R1 1+[1~l
R
2R

13=--=-=0.5

Loop Gain

Noise Gain

Figure 3B. Noninverting:
Nonunity Gain

Rl
13 = Rl+R2

13=1

Avo 13

1
1
-=-=2
13 0.5

t: _

fu
c- IACLI + 1
1

note: IACLI =13-1

1
13

1
-= 1
13

fu
fc =fu

[*]

Closed Loop
Gain Stability

MCL MOL [ 1 ]
ACL = AOL 1 + Af3

Closed Loop
Distortion and
Nonlinearity

THU::L = THDoL[ 1 +lA f3]

Closed Loop
Output
Impedance

ZcL = ZOL [_1- ]
1 + Af3

Figure 3. Basic Circuit Configurations
5-132

AN6REV5

---- ----------_ _ _ _ _ _iIIIIII_

a designer must either increase the open-loop
gain of the amplifier or increase the feedback factor, P (decrease the noise gain). Remember that
both the open-loop gain and the feedback attenuation factor are not constant, but instead are
functions of frequency. Therefore the value of
the loop gain is a function of frequency as well.
The quantity of loop gain at the operating frequency is the key measure of how closely an
amplifier configuration approaches the ideal.

Amplifier Configurations and Feedback

Figure 3 provides an overview of the inverting
and non inverting voltage amplifier configurations. General equations for various parameters
of the configurations are given with special emphasis on the unity gain configuration. Signal
gain is set by the choice of resistors, but the gain
error (assuming perfectly accurate resistors) is a
function of the loop gain in the error multiplier
term as previously stated in our discussion on
feedback. The unity gain noninverting amplifier
is just a special case of choosing the value of resistor Rl as being infinite and R2 being zero.
Notice that the feedback attenuation factor, p, as
derived for both circuits yields the same equation:
Rl
Rl+R2
Equation 5

but for the unity gain inverting amplifier this results in a value of 0.5 whereas the unity gain
noninverting amplifier results in a P of 1. These
unequal values of P between the two unity-gain
configurations yield further differences between
the inverting and non inverting circuits. Loop
gain for the unity-gain inverting circuit is half
that of the noninverting unity-gain circuit. This
results in the inverting circuit being more easily
compensated for stability, but also yields greater
AN6REV5

ADC Input Buffers

errors in those parameters where loop gain is a
factor. More will be said about these parameters
later.
Reduced P for the inverting configuration results
in greater noise gain (lIP). Error sources such as
offset and noise are amplified by the noise gain
and therefore the unity-gain inverting amplifier is
more adversely affected by these error sources.
Another negative factor of the unity-gain inverting stage is that its signal bandwidth is half that
of the noninverting circuit with identical amplifiers. This bandwidth reduction is because
bandwidth is a function of the noise gain, not the
signal gain. Be aware of this fact when using
low gain inverting stages.
The magnitude of the loop gain in a circuit affects many parameters in both the inverting and
noninverting configurations. Closed loop gain
stability is improved by increased loop gain as
indicated in the equation:
MCL MOL [ 1 ]
ACL = AOL 1 +A~
Equation 6

The effects of changes in the open-loop gain
(such as a reduction due to increased temperature) are reduced proportionally to the amount of
loop gain. Open loop distortion and nonlinearity
are reduced by increased loop gain. This reduction in total harmonic distortion as indicated in
the equation:

THDcL = THlX>L [ 1 +1AP ]

Equation 7

5-133

_
'.'

.................
----...
...-.
.....

ADC Input Buffers

~

The output impedance of a voltage amplifier is
reduced with feedback as indicated in the equation:
ZCL= ZOL [ 1

}A~]

Equation 8
The input impedance of both amplifier configurations benefit from increased loop gain. Although
increased loop gain is desirable in both circuit
configurations the effect of feedback on the two
configurations is different.
The noninverting amplifier utilizes voltage ratio
feedback which increases the differential input
impedance seen by the input signal. But the differential input impedance of the amplifier is
shunted by the common mode input impedance
of the amplifier. Because the common mode impedance cannot be increased by the use of
feedback it is usually the limiting factor in increasing the input impedance.
The inverting amplifier configuration uses transadmittance feedback which decreases the
impedance at the summing node of the input and
feedback resistors. This decrease in impedance
improves the virtual ground characteristic of the
amplifier. In the inverting configuration the effect
of a good virtual ground enables the effective
value of the input impedance seen by the signal
source to be set by the input resistor.
In both configurations the improvements to the
respective impedances depend on the magnitude
of loop gain. As the magnitude of loop gain generally decreases with increased frequency, all of
the parameters normally improved by loop gain
tend to degrade as the signal frequency increases.
All real-world amplifiers have finite open loop
gain and finite bandwidth, both of which affect
the amount of loop gain available to a designer. A
designer must make a prudent choice of amplifier
5-134

and of the circuit configuration to minimize the
errors due to loop gain limitations.

Some Other Error Sources
There are many sources of error in a given amplifier configuration. As already discussed, limited
loop gain is a source of gain error which can affect DC accuracy. In addition to the DC gain
error, there are the various offset errors which are
contributed dependent upon the characteristics of
the chosen amplifier. Sources of offset errors are
the input offset voltage of the amplifier, the input
bias and the input offset currents of the amplifier,
limited power supply rejection and limited common-mode rejection.
Which of these errors is dominant will depend
upon the choice of amplifier and its application
configuration. It is a routine procedure to calculate the contribution of each source of error and
this should be done as a matter of course. A few
comments on each of these sources of error is
appropriate.
All amplifiers have input offset voltage and input
bias currents which result in errors in signal
measurement. The input bias currents flow
through the resistances on the (+) and (-) leads of
the amplifier and produce an offset voltage error
at each input. These offset voltages, and the voltage offset of the amplifier itself, are then
amplified by the circuit to produce an error in the
output signal. To reduce the errors due to the
bias currents the standard practice has been to
balance the value of resistance at the inverting
and noninverting inputs to an amplifier. The purpose of making these two resistances equal has
been to enable the bias currents at both inputs to
produce equivalent values of offset voltage which
could then be rejected by the common mode capability of the amplifier. This practice is an
acceptable method of reducing. error due to the
bias currents and is recommended except with
AN6REV5

--------..,.... ----------modern amplifier designs which have internal
bias current compensation circuitry. The bias
current compensation circuitry tends to reduce
the bias currents an order of magnitude or more,
to the extent that they are reduced to the same
order of magnitude as the amplifier's input offset
currents. Adding a resistor to one input to achieve
equal resistances at the two inputs of these types
of amplifiers is not recommended. The added resistance is not effective in reducing the error due
to the bias currents, but it will add another source
of thermal noise.
.
Initial offset errors as well as gain errors generally can be reduced to zero with initial system
calibration adjustments at room temperature. The
effects of temperature-induced offset drift and
gain drift remain unless a method of ongoing correction or recalibration is used to remove these
effects. This correction may be accomplished
with a computer after the analog signals are digitized and is recommended when maximum
accuracy of measurement is demanded.
Even if the effects of temperature-induced offset
errors are removed from the final data by software, it remains desirable to examine the total
errors at each gain stage throughout the system.
Voltage offsets due to temperature drift can be removed in software, but may still consume a
significant portion of the dynamic range available
to the signal. This is especially true in 16-bit
converter systems with wide temperature range
requirements such as required by some military
specifications (-55 to +125 ° C).
Limited power supply rejection and limited common mode rejection are two more sources of
errors. Most commercially-available amplifiers
are designed such that the offset voltages induced
by power supply variations or common-mode
signals are very small; but these errors can be
significant when amplifying very low level signals with high gain. It is therefore recommended

AN6REV5

ADC Input Buffers

to examine the error contribution of each of these
sources.
Figure 4a shows an inverting amplifier circuit.
The operational amplifier and the circuit components have been chosen for illustration purposes.
The errors in the circuit due to the various amplifier parameters will be examined: Not included
are those errors due to the signal source impedance (the impedance is assumed to be zero),
output loading (which reduces open loop gain),
resistor tolerance and temperature coefficient, and
component long term drift effects.
A table in Figure 4a contains a selected subset of
specifications for a "generic" OP-27C. No specific manufacturer is implied. The subset of data
is for the total error band of the stated parameters
over the -55° to + 125°C temperature range.
Manufacturers do not always specify temperature
drift coefficients in their component data sheets.
Instead, the specification sheets contain a table of
data for the amplifier at room temperature (25°
C) along with a table showing the total error
band of the various parameters over a stated temperature span (say 55° to 125° C). Usually the
specification data tables are supplemented by
supporting graphs which indicate typical drift
characteristics for the various parameters. These
graphs can be very informative. For example,
graphs in the manufacturer's data sheets (see the
Precision Monolithics or the Linear Technology
data book) for the OP-27 indicate that input bias
currents and input offset currents show much
more drift at temperatures approaching -55° C
than at temperatures above 25° C. Another graph
indicates that the direction of the input offset
voltage drift in the OP-27 is unpredictable.
The normal procedure to calculate the error contribution of each of the operational amplifier drift
parameters is to multiply the rate of drift times
the temperature span over which the circuit is to
be subjected. These errors due to drift are then
added to the initial errors of each of the parame5-135

_

.. .

......,.., .....
~~

•

~~~

1IIIIr.-" •

•

_.

ADC Input Buffers

Generic OP-27 Specifications
Total Error Band for _55° to +125°C Temperature
Span
+15V

1Ypical

Input Offset Voltage VIOat

• Assumed to be zero.

R2Rl = 1.667 ill
Rl+R2

Re=
Ideal Signal Gain =

-R2

Rt

=-5

Rl
1
Feedback Attenuation Factor ~ = RJ+R2 = 6
Noise Gain =
Closed Loop Bandwidth fc

=

1

13 =6

J=1.33 MHz

6
IAcL\fu+ 1 [8- x610-

Worst
Case
300/lV

Input Bias Currentt

IBat

Large Signal
Open Loop Gain

Ao

Power Supply
Rejection Ratio

P.S.R.R.

Common Mode
Rejection Ratio

C.M.R.R. 1.6 x 10-6 VN 20 x 10-6 VN
(116 dB)
(94 dB)

±35nA

±150nA

800 x 103 VN 300 x 103 VN

4x 1O-6 VN
(l08 dB)

51 x 1O-6 VN
(86 dB)

Bias currents are usually of one polarity. Bias currents of
both polarities indicate the use of bias current cancellation circuitry in the input stage.

t

Figure 4a. OP-27 Circuit and Total Error Band Specifications

Gain

Input
Qffset Voltage

Input
Bias Current

P.S.R.

+

+

2~VlO

[lJ

~Vsup ~

C.M.R.
+

~VlO

[lJ

~VCM ~

Noise
+ Noise

+ (±300xlO-6)(6) + (±150xlO-9)(2xI03)(5) + (2)(51xlO-6)(looxlO- 3)(6) + (= 0) + Noise

Vo=

-.99998 Vi

±·61.2xlO-6 V

± 1.8xl0-3 V

±=O

+ Noise

Worst Case Error % Full Scale Output;
0.002%

+ 0.040%

+ 0.033%

+ 0.00136

+=0%

+ Noise

; Based upon: 4.5 V FSO; 100 mV power supply change on each supply.
Figure 4b. Total Error Band Calculations
5-136

AN6REV5

..------_
--- ----------ters at the ambient operating temperature. Because amplifier manufacturers specify total error
band rather than drift rates, the method of computing the error contribution of each parameter
must be modified. The equation in Figure 4b illustrates the errors calculated using the total error
band specifications on the OP-27C in Figure 4a.
The calculations indicate the relative contribution
of each source of error in the worst case with the
exception of noise, which is yet to be discussed.
As can be seen from the numbers, real world amplifiers can contribute significant errors in a hig.h
precision data acquisition system due to theIr
non-ideal characteristics.

Noise and its Effects on Measurement
Noise can have a significant detrimental effect in
high precision data acquisition systems. Although
one can encounter many different sources of
noise and of interference in system design, only
certain noises made by the components themselves will be discussed here. Thermal noise, also
called Johnson noise, is fundamental to all components. The thermal noise in a resistor can be
calculated by use of the formula:
en =...J (4kTBR)
Equation 9
where k = 1.38 x 10-23 Joules/ degree K
(Boltzman's constant), T = Absolute temperature
of the resistor, B = the effective "brick wall"
Bandwidth over which the noise is to be measured, in Hz, R = Resistance value.
The amount of noise generated by a resistor can
be made easier to calculate by remembering that
the amount of noise generated by a 1 kn resistor
in a 1 Hz bandwidth is 4 nV rms. The amount of
noise per ...JHz generated by any other valued resistor can be computed from this normalized
value:
AN6REV5

ADC Input Buffers

4nV _~
er = ...J (Hz)Yiidi
Equation 10
This noise value assumes a one Hz bandwidth.
The noise within a wider bandwidth can be computed by:
- 4nV
er - ...J (Hz)

-V lkQ
R B

Equation 11
Components other than resistors generate thermal
noise. The OP-27 monolithic amplifier is classified by its manufacturers as a low noise
amplifier. It is optimized for low voltage noise
and requires low source impedances to achieve
good noise performance. A plot of the OP-27
noise voltage and noise current characteristics is
given in the manufacturer's data sheet. Th~ amplifier's noise is uniform across the hIgher
frequencies, but increases at frequencies approaching DC. This increase is called flicker
noise, or l/f noise.
A thermal noise model of the circuit of Figure 4a
is shown in Figure 5. Five noise sources are
shown in the model. The amplifier has a voltage
noise source en and two current noise sources;
one associated with each input of the amplifier.
Each of the amplifier current noise sources will
generate a corresponding noise voltage which is a
function of the impedance seen by the current
noise source. In addition to the voltage and current noise sources, each of the resistors has a
noise voltage source associated with it. The
amount of noise contributed at the input of the
amplifier by the each of the resistor noise sources
is reduced by the loading of the other resistor.
For example, consider noise source eR2 as having
resistor R2 as its source impedance with resistor
R1 acting as the load. The noise seen at the input of the amplifier from source eR2 will be only
5-137

.'"

..............
..........
.........

ADC Input Buffers

."

."

Effective Amplifier Bandwidth
OP-27 typical unity gain frequency
circuit bandwidth

=

fu

I AcLI+l

=

= 8 MHz
8x106

5+1

= 1.33 MHz

effective noise bandwidth
B = (1.33x106)(1.57) t = 2.1 MHz

Noiseless
Amplifier

t The effective noise bandwidth of a single pole, lowpass
filter is 1.57 times greater than the 3 dB corner frequency.

Noise Model of Amplifier in Figure 4a.

Noise Sources of the Model
Amplifier Noise Voltage

en max (fo = 1 kHz) 25°C

Amplifier Noise Current

in max (fo = 1 kHz) 25°C = 0.6 pN...[Hz

eRl

=

4.5nV~2k
"Hz

eR2

=

}

From data sheet
specifications

5.65nV

:../HZ

1k

4.5 nV~ 10 k
1k

:../HZ

=

=4.5 nV/...[Hz

=

12.6 nV

:../HZ

Equivalent Input Referred Noise (Thermal)

et =

6.8 nV

:../HZ
Total Output Noise (Thermal)

1

1/6 = 591lVrms
Peak Noise will be much greater.

Figure 5. Noise Calculations

5-138

AN6REV5

---------_. _..--------that portion of its output which is developed
across resistor R1 (assuming the input impedance
of the op amp is very high). The noise generated
by eRI is reduced by the loading of resistor R2.
The amount of noise generated at the input of the
amplifier by each of the sources is tabulated in
Figure 5. The two current sources each have the
same value of current noise. Using the values of
the noise sources, the effective input-referred
voltage noise of the circuit has been calculated.
It must be remembered that the noise sources are
uncorrelated and therefore add in root-meansquare fashion. This equivalent noise source then
represents the total input referred thermal noise.
To obtain the value of the noise at the output of
the amplifier which will be input to the AID converter, the input referred noise is amplified by the
noise gain of the amplifier while at the same time
taking into consideration the effective noise
bandwidth of the circuit.
Arriving at a value for the noise bandwidth of the
OP-27 circuit is not as obvious as it might seem.
If the noise gain of the circuit in Figure 4a is
used to compute the 3 dB signal bandwidth the
result will be 1.33 MHz. The effective noise
bandwidth of a single pole filter is actually 1.57
times greater than the 3 dB corner frequency.
But, above 1.33 MHz the OP-27 gain-phase characteristics are not those of a single pole system,
but are more complex. The internal gain-phase
compensation of the OP-27 will actually cause
gain peaking in the circuit of Figure 4a. The
gain peaking will occur at the point where the
closed loop gain and open loop gain crossover.
Also, at frequencies approaching the unity-gaincrossover of the OP-27, the amplifier gain will
differ from the roll off of a single pole filter. The
effects of the gain peaking and the complex gainphase characteristics of the OP-27 above the 3
dB corner frequency make an accurate estimate
of the resultant noise difficult. One can use the
single pole filter characteristics and can approximate the noise bandwidth of the circuit as being
1.57 times the 1.33 MHz corner frequency (2.1
MHz), but the resultant noise calculation using
AN6REV5

Ace Input Buffers
this bandwidth will yield only a coarse approximation of the actual noise .
Using the assumption that the approximation is
adequate, the noise at the output of amplifier has
been calculated as shown in Figure 5. The calculated value is the amount of thermal noise in rms
volts.
Thermal noise is both white and Gaussian.
"White" describes the noise as having equal spectral density at all frequencies. "Gaussian" defines
the probability density function which describes
the amplitude characteristics of the noise. Gaussian noise follows the Normal Distribution.
Therefore, once the rms value of the noise has
been determined, the probability of occurrence of
any value greater than a particular amplitude can
be determined. The peak (+ and -) noise associated with a stated probability of occurrence is
indicated in the following table:

Probability of
Having a higher
Amplitude Occurrence
10%
1%
0.1 %
.001 %

Peak to Peak
Amplitude

3.29
5.15
6.58
7.78

x RMS
x RMS
x RMS
x RMS

Since the peak noise can adversely affect AID
measurements it should be investigated by both
analysis and measurement.
Minimization of thermal noise in system design
is accomplished with the application of three design principles. First, it is good practice to use
the lowest resistor values possible (this assumes a
voltage amplifier system) limited only by the
constraints necessary to meet other system requirements. Second, choose an appropriate
amplifier. Some amplifiers, such as the popular
5-139

....
.-.......
_...
........,.
--_-

ADC Input Buffers

~

LM324, do not include noise specifications in
their data sheet. If low noise is a system requirement, amplifiers which have no noise
specifications are not likely to be an appropriate
choice. Also, choose an amplifier which is optimized to work with the source impedance
requirements of the system. Bipolar-input amplifiers are generally optimized to work with low
impedances as they have lower voltage noise
than current noise while PET-input amplifiers are
generally optimized for high impedances due to
their lower current noise. The optimum choice of
amplifier will depend not only on the amplifier,
but its associated gain elements and circuit configuration. Analysis of the various possible
configurations is necessary to disclose which will
be optimum to meet design requirements. Third,
one of the easiest ways to reduce the effects of
noise is to restrict the bandwidth. System bandwidth should be restricted to only that amount
necessary to meet system requirements. This
should be done as a matter of good practice.

lated, but can be more, due to other noise sources
which have not been accounted for. For a more
thorough discussion of noise as it applies to amplifier design see references 2 through 6 listed at
the end of this application note.

Settling Time
Amplifier circuits have limitations which restrict
just how quickly they can produce an accurate
output signal at the application of a step change
of the input signal. For small changes in signal
amplitude, the ability of the amplifier to respond
is dependent upon its 3 dB upper corner frequency. If the amplifier gain-phase characteristics
approximate a single pole response above the 3
dB frequency the output signal will asymptotically approach a steady state output value V s as
defined by the equation:
Vo(t)=V s [ l-e(2)J
1c

While only the effects of thermal noise have been
discussed be aware of other noise sources (see
the reference material at the end of this application note). Note that in the circuit of Figure 4a
the effects of the lIf noise were not investigated.
If the system requirements demand the lowest
noise possible the effects of the lIf noise needs to
be examined. The example calculations on thermal noise were done at room temperature. An
increase in temperature to 125° C will result in
about 1.3 dB greater noise.
Last of all, the calculated answers are only theoretical estimates. The calculations provide a
theoretical minimum value but the final determinant of design should be in the evaluation of total
system function and/or measurement of the actual
amount of noise in the system. Remember that
the value of the noise calculated provides only a
reference point for the minimum amount of noise
in the circuit; the actual amount present will
never be less than the theoretical amount calcu5-140

Equation 12
Where the time constant, 'tc, is given as a function of the comer frequency:
1

'tc=--

21tf c

Equation 13
Settling time is defined as the elapsed time from
when the input step voltage is applied until the
output signal reaches and stays within a given error band of a steady state value.
If the input step change is large, the slew rate
limit of the amplifier will restrict the speed at
which its output can change. The limit at which
an amplifier can slew is a function of how fast it
can charge or discharge its compensation capacitor. The maximum frequency of a given
AN6REV5

. ......
......._.-.
~

.."

~

~~~

Ace Input Buffers

~~

amplitude that can be faithfully reproduced by an
amplifier with a stated slew rate is defined by the
equation:

Which can be simplified to the following:
t

=..:...(1_+_N...:....)..:...(0_.1....!..1)
f

SR
f max = - 21tVp

Equation 14
where Vp is the peak: output voltage.
When large changes of signal at the input occur,
the settling time of the amplifier will be a combination of initial delay, slew rate limited
excursion, and small signal settling time as indicated in Figure 6. Note that the small signal
settling illustrated in Figure 6 is not that of a single pole system, but is instead representative of
an actual wideband amplifier.
A first order approximation of settling time can
be estimated for a circuit under the following
conditions. First, the signal must not cause the
amplifier to enter slew rate limiting. Second, the
3 dB comer frequency of the amplifier must be
known and it's roll-off must be at 20dB/decade
for at least a decade of frequency above the 3 dB
comer frequency. Under these conditions the following equation yields a good approximation to
the settling time:

Equation 17
Settlip.g time is not readily predicted in other circumstances. It varies with signal amplitude and
is as much dependent upon the circuit configuration and circuit components (including things like
stray capacitance) as it is upon the amplifier characteristics. An assessment of circuit settling time
is often best be obtained from observation of the
circuit under applicable conditions.

1

OVERSHOOT

FIN! ENTRY INTo ERROR BAND

____
+F.S.

-

ERROR BAND

~_ ~~AL~LU~

_

L

I'--.,/'"-I-------r

o io---SETlllNG ---oj

TIME

TIME

Figure 6.

n. THE CS5016 FAMILY AID CONVERTER
Equation 15
where f is the 3dB frequency. To settle to 112
LSB at N bits (N = 16 in a 16-bit NO) the equation can be written as:

1_

t = __

21tf

In

12N - 0.5 - 11

The analog input pin (AJN) of the CS5016 series
converter acts as a load to the buffer amplifier
output. A good understanding of the internal
workings of this pin on the converter will help in
the design of an appropriate buffer amplifier.

2N

Equation 16
AN6REV5

INPUT STRUCTURE

Figure 7a depicts a simplified circuit diagram of
the circuitry internal to the NO converter as seen
from the AIN pin. From the metal pin of the
5-141

...,...,....
....,.............
.....,

.., ,.,...,...,

ADC Input Buffers

VA-

CA in Unipolar Mode
Ch

=

CAl 2 in Bipolar Mode

Figure 7a CS5016 Family Analog Signal Input Model

package a bond wire connec,ts to the semiconductor chip. Clamp diodes on the chip connect to
both of the supplies. Under abnormal conditions,
excess signal amplitude may forward bias the diodes. The diodes protect the chip from voltage
breakdown. Unless the current under such fault
conditions is limited, the diodes may short out or
the bonding wire may "blow its fuse". The current should be limited to under one hundred rnA
transient or under 10 rnA steady state to eliminate
any possibility of damage. Methods of limiting
input current to the AID converter are discussed
below. Once the input signal travels beyond the
protection circuitry, it sees a buffer amplifier AI,
CMOS switches SI, S2, and S3, a hold capacitor
Ch, and transconductance amplifiers G 1 and G2.
To accomplish a complete conversion cycle, the
states of the CMOS switches are altered. These
state changes cause the effective load at the AIN
pin to change dynamically during the three different phases of the conversion cycle. These three
phases are called coarse-charge, fine-charge and
conversion. An understanding of the function of
each of these three phases will explain :the reasons for the dynamic change in loading. The
conversion phase begins with the activation of
the hold command (HOLD goes low).
When hold is activated, the "sample capacitor" of
the track-and-hold section of the converter immediately traps a charge on the sample capacitor
5-142

which is representative of the input signal. The
binary representation of the value of the charge
is then determined. The number of master clock
cycles necessary for this determination to occur is
a function of the number of bits of the converter
and the particular mode of operation (loopback or
asynchronous). The occurrence of the EOC (end
of conversion) signal indicates that the conversion time is complete. The converter must then
acquire a new sample of the input signal for the
next conversion. The coarse-charge and finecharge times accomplish this. First to occur
is the coarse-charge phase. A buffered version of the analog input signal is first
connected to the sample capacitor. The input
impedance of the buffer is very high and
therefore does not load the input signal
source. The output of the buffer is connected
via switches S2 and S3 to the sample capacitor (switch S 1 is open). The buffer (Figure
7a, AI) furnishes the majority of the current
necessary to charge the capacitor toward the
new voltage value. The buffer therefore reduces the transient current demand from
the signal source if the input signal has
changed from the value previously stored
on the sample capacitor. The sample capacitor is connected to the output of the
buffer for six cycles of the master clock
(CLKIN) frequency. At the end of the six
cycles the coarse-charge phase is complete.
AN6REV5

_..........
........._
...
•

...r. . . . . ..

Ace Input Buffers

The sample capacitor is then directly connected
to the analog input signal for the fine-charge
phase (Switches S 1 and S3 are closed, S2 is
opened). Immediately before being connected for
the fine-charge phase, the voltage on the sample
capacitor may still differ slightly from the analog
input value. This is due to the offset voltage of
the buffer amplifier (AI). This offset voltage is
typically 50 mV but may be up to 150 mV in the
worst case. At the beginning of the fine-charge
phase a small transient demand of current from
the external signal source may occur as the capacitor charges to its final value. The fine-charge
phase will last until the hold command becomes
active again. In loopback mode the fine-charge
phase lasts nine master clock cycles until the end
of track (EOT) signal reactivates the hold command. When the hold command is activated
asynchronously, the fine-charge phase should last
a minimum of nine master clock cycles and may
continue indefinitely until the hold command is
activated.
Simplified models of the impedances seen by the
analog input signal are depicted in Figures 7b
and 7c. For the conversion and coarse-charge
phases, the impedance seen at the AIN pin is the
input impedance of the buffer AI. This impedance is approximately 100 Mn. shunted by 15 pF.
When in the coarse-charge phase the sample ca-

AIN

R1

Figure 7b. Simplified Input Model During
Coarse-charge I Conversion

pacitor is charged by the buffer (AI) output. The
speed at which the voltage on the sample capacitor can track the input signal is limited to the rate
at which the buffer output current can charge the
capacitor. The slew rate of the buffer is 5 V/fls
when the converter is in unipolar mode and 10
V/fls when in the bipolar mode. The reason for
the difference is that the sample capacitor in bipolar mode is only half the value of that in
unipolar mode.
The simplified model of the impedance seen in
fine-charge is that of Figure 7c. Resistor Rl is
the effective resistances of the S 1 and S3 CMOS
analog switches of Figure 7a. The sample capacitor consists of C2, whereas capacitor C 1 and
CS are stray capacitance. G 1 is a transconductance amplifier with an effective input resistance
of about 35 n. at DC. The slew rate in the finecharge mode is limited to the rate at which the
output current of the transconductance amplifier

C2

~-~--l

AIN

100 ohm

o-----~

r~

I

C1 +C2+CS

.--

Unipolar
Bipolar

C1
C2
CS
R1
170 pF 170p F 20pF 100 ohm
85pF 85pF 30pF 100 ohm
--

Gin
35 ohm
35 ohm

Figure 7c Simplified Input Model During Fine-charge.

AN6REV5

5-143

..--.-_--_
.,,--- ---

_ _ _ _If8I _ _ _ _

ADC Input Buffers

G 1 can charge capacitor C2. In unipolar mode
the slew rate is 0.2S V/lls. In bipolar mode when
the capacitance of C2 is less, the slew rate increases to 0.5 VIllS. Acquisition of fast slewing
signals (step functions) can be hastened if the
step occurs during the conversion cycle or during
the coarse-charge cycle since at these times the
slew rate of the converter input is faster. It
should be noted that in fine-charge, any external
impedance on the AIN pin becomes part of the
total network and will contribute to the settling
time response characteristics.
Also, Figure 7a shows that when switches Sl and
S3 are turned on (S2 is off) in the fine-charge
phase, the source impedance of the external circuitry connected to the AIN pin actually becomes
part of the feedback network of amplifier G 1.
The external circuitry should offer an impedance
less than 400 n at frequencies greater than
2 MHz or amplifier G 1 may oscillate.
The input circuitry of the analog front end of the
AID converter uses CMOS analog switches
which are similar to analog switches available in
individual integrated circuits. The resistances of
the CMOS switches, such as shown in Figure 7c,
exhibit non-linear effects with changes in signal
amplitude and frequency. These dynamic
changes in switch characteristics are a source of
distortion at high frequencies.

III. EXAMPLE BUFFER CIRCUITS
Buffer Circuit Test Method
Several example buffer circuits have been constructed and tested. Evaluation was restricted to
dynamic testing at room temperature (2S C).
The testing was performed using a CDBS016
evaluation board connected to an IBM compatible computer via a 16-bit parallel 1/0 card.
Signal processing software developed at Crystal
was used to evaluate the data. The signal source
0

5-144

was a Khron-Hite 4400A Low Distortion Oscillator modified to produce low broadband noise per
the article in Reference 1 (Reprints available
from Crystal upon request). The oscillator was
adjusted to the appropriate full-scale value for
each circuit. A frequency of I.S kHz was chosen
as the test frequency.
The output data from the AID converter was
processed to yield three indicators of dynamic
performance. These are:
1) S/(N+D): The ratio of the rmsvalue of the
signal to the rms sum of all other spectral components below the Nyquist rate (except DC),
including distortion components.
2) SID: The ratio of the rms signal value to the
ratio of the rms sum of all harmonics.
3) SIPN: The ratio of the rms signal value to the
rms value of the next largest spectral component
below the Nyquist rate (except DC).

Benefits of an RC Isolation Network
All of the example circuits show an RC network
coupling the output of the buffer to the input of
the AID converter. The 200 n resistor and 1 hF
capacitor network is recommended for the
CSS012A, CSSOI4, CSS016, and CSSI26. The
200 n resistor should be replaced with SO n for
the CSS101A and CSSI02A. The RC filter enhances circuit operation in four ways. First, the
network reduces the amount of broadband noise.
Second, it decouples the input capacitance of the
AID converter from the amplifier. This reduces
the possibility of the amplifier having stability
problems driving a capacitive load. Third, the circuit isolates the output of the amplifier from the
high frequency pulsed charge effects of the sampling front end of the AID converter. And finally,
the passive network offers a well-behaved low
source impedance to the internal transconducAN6REV5

-........
.....
. _.-.
_............

. ADC Input Buffers

+
+5
o.1 T T 1.0

JlF V

VJlF

3 + 7 MAX410

2

4

6
1 nFT
NPO V

Gain

1

Input

1.5kHz,±3.5Vpk

VREF

3.5V

S(N+D)

90.54 dB

SID

100.1 dB

S/PN

104.7 dB

'----->-------.-- -5
Figure 8. MAX410 Noninverting Amplifier

tance amplifier, satisfying its stability needs. The
component values are chosen to have a time constant of 200 ns to provide appropriate settling
time when the converter (16 bits) is sampling at
50 kHz. The NPO dielectric characteristic minimizes the effect of voltage coefficient of
capacitance which can adversely affect performance at the 16-bit level. Other dielectrics may be
adequate while some may result in non-linear Capacitance with signal level and therefore
introduce distortion. Empirical testing may be
necessary to insure whether a given dielectric is
adequate for a particular application.

± 5 Volt Supply Op Amp Circuits
The first example circuit is a unity gain buffer
circuit shown in Figure 8. The MAX410 op amp
is designed for operation from ± 5 V power supplies. The input common mode range of the
amplifier is specified as ± 3.5 V, therefore the reference voltage for the AID converter was set to
use +3.5 V as its full scale reference value. The
circuit yields quite good results when the reduced
signal level is considered.

AN6REV5

The second circuit, Figure 9, configures the
MAX410 in the inverting mode. The minimum
output voltage swing for the MAX410 is specified as ± 3.6 V (2 ill load) with a typical range
of ± 3.7 v. A 3.5 volt reference was used for the
AID converter. Performance was good using the
3.5 volt reference.

± 15 Volt Supply Op Amp Circuits

I

I

Most precision operational amplifiers are specified for operation 'from ± 15 V supplies. Figure
10 shows an OP-27 used to reduce signal levels
of ± 10 V to ± 4.5 V. The performance is excellent. Figure 11 then shows the OP-27 in the
non-inverting configuration.
The performance levels being achieved with the
OP-27 result from operating the amplifier well
within its specifications for input range and output amplitude capability. The Signetics NE5534A
worked equally well in both circuit configurations (Figures 10 and 11). Note that low value
resistors are used to minimize the component
noise in the circuits.

5-145

III

I

I

.......,.", .......
...,...........
..,..,~

ADe Input Buffers

.."

4.02k
.--.------411---- +5
0.1 T ;-1.0
IlF V v llF
200
1nF T

Gain

-1

Input

1.5kHz,±3.5 Vpk

VREF

3.5V

S/{N+D)

90.1 dB

SID

97.7 dB

S/PN

102.0 dB

NPOV

Figure 9. MAX410 Inverting Amplifier

If an OP-27 type amplifier is used, the inverting
circuit is preferred for signal processing applications. This is because some brands of OP-27
amplifiers exhibit much higher distortion at frequenCies above 10KHz or so when used in the
non-inverting configuration. It may be that the
internal bias current cancellation circuitry does
not track the input stage well when subjected to
the rapidly-varying (high frequency) common
mode voltages such as those experienced by the
positive gain configuration.

Achieving ± 4.5 Volt Output with ± 5 Volt
Supplies
Some designs may require that the entire system
operate from ±5V, but achieve the full dynamic
range of the AID converter when using a 4.5 V
reference. The Signetics NE5534A op amp,
known to be excellent for audio use, can be combined with a discrete transistor output stage to
yield excellent results when using only ± 5 V
supplies. Figure 12 illustrates the NE5534A in
the inverting configuration, reducing a ± 10 V
signal to ± 4.5 V. The OP-27 (without the external compensation capacitor) yielded similar noise

5-146

and distortion results but had slightly slower rise
time when tested with a transient input.
An Instrumentation Amplifier Circuit
Some systems require an instrumentation amplifier front end. One instrumentation amplifier was
tested; the AD625C from Analog Devices. The
data sheet specifies a maximum nonlinearity of
0.001 %. Although the device may have good
static linearity, its dynamic performance was well
below 16-bit performance. The AD625C, shown
in Figure 13, was tested with two different gains.
The instrumentation amplifier was tested with a
gain of one, and then with a gain of nine. The
gain of nine configuration is with the 5 kO resistor connected to pins 2 and 15. The data indicates
that the part actually has greater distortion (indicative of greater nonlinearity) in the lower gain
configuration.
Signal Limiting Circuits
When utilizing op iunps with ± 15 V supplies to
drive AID converters with ± 5 V supplies it is
possible under certain input conditions for the
AN6REV5

."..,_._.
_..................
.....
_...-

Ace Input Buffers
2.26k

r---.--.-+15
+
T

0.1 T

1.0

IJ.F '\/" '\/" IJ.F

7
200

6
L-~-'--·15

i+

1nF T
NPO'\/"

Gain

·0.45

Input

1.5kHz,±1OVpk

VREF

4.5V

S(N+D)

91.8 dB

SID

100.5 dB

S/PN

102.6 dB

1.0

'\/" IJ.F
Figure 10. OP·27 Inverting Amplifier

amplifier output voltage to attempt to exceed the
supply rails of the converter. As described previously, the converter has protection diodes at the
analog input and therefore will clamp the voltage
whenever the signal forward biases the diodes. If
high current amplifiers are used, excess current
from the amplifier may damage the converter. If
excess current is a possibility, then the voltage
swing of the amplifier must be limited so as to
not exceed the supplies of the converter; or some
means of current-limiting must be used. Many
amplifiers have current limiting circuitry as part
of their output stage and will limit their output
current if a fault condition exists. Even though
the amplifier may protect itself in this manner it

may not be desirable from a system performance
point-of-view. System measurement accuracy
can be degraded due to offset and gain errors
which occur as a result of amplifier self-heating.
Several approaches to amplifier output limiting
can be used. Zener or diode bounding circuits
can be used. Some bounding/clamping circuits
reduce the circuit gain by reducing the effective
feedback resistance when an overvoltage signal
exists. Others limit the signal by shunting it to
ground when it exceeds the desired amplitude.
Reference 6 documents some of these circuits
and discusses their strengths and weaknesses.

--~'

.-------+
0.1

+

1.0

IJ.F:& :&IJ.F

15
Gain

+2.5

Input

1.5 kHz, ±1.8 Vpk

VREF
S(N+D)

4.5V
90.7 dB

SID

98.0 dB

S/PN

102.3 dB

1k

Figure 11. 0P27 Noninverting Amplifier

AN6REV5

~.'.

5-147

.. ...
. ......__
.......
~~

..,

~~"""'

ADC Input Buffers

~~

56pF
4.99k

Gain

-0.45

Input

1.5 kHz, ±10Vpk

VREF
11.0 k

S(N+D)

200

1nF

~NPO

4.5 V
91.7 dB

SID

99.7 dB

S/PN

103.3 dB

Figure 12_ Op Amp with Transistor Buffer Stage

Voltage Clamping via the Compensation Pin
Figure 14 indicates a simple means of clamping
available on some op amps. lllustrated is a Harris
HA-2600 with diodes connected to its compensation pin (8). The ± 5 V supplies of the AID
converter provide the clamp voltage reference
values for the diodes. The output stage of the
HA-2600 has unity voltage gain but high current
gain. The signal on pin 8 of the amplifier is a
low current signal of identical amplitude to the
output signal. Limiting of the output signal swing
c---_____- +

0.1

is accomplished by clamping the signal at pin 8
to the desired level. Even if the on voltage of the
clamp diodes on the op amp exceed the on voltage
of the clamp diodes inside the NO, the 200 n resistor will limit the current to an acceptable level.

A Novel Method to Aid Current Limiting
Another method of protecting the NO converter
from excess signal conditions is illustrated in Figures 15 and 16. The circuits make use of

15
Gain

+ 1.0

I1F:& :& Ilf'

Input
VREF

9
<>--------'-1 +

L
1.5 kHz, +4.5 Vpk
4.5 V

S/(N+D)

73.1 dB

SID

81.5 dB"

S/PN

83.7 dB"

" Primarily 2nd harmonic
AD625C
7

20 k

Gain

9"

Input

1.5 kHz, +0.5 Vpk

VREF

16

-15
1.0

~I1F

4.5V

S/(N+D)

74.1 dB

SID

87.3 dB

S/PN

84.7 dB

" 5 K resistor connected

Figure 13. Instrumentation Amplifier

5-148

AN6REV5

.................
..,-- ....
.................

ADC Input Buffers

3.46k

4.32 k

r----.-"'- + 15
1.0 + 0.1
/!F:& :&/!F
1N4148
7
+5
2
-5

HA2600

Gain

-0.8

Input

1.5 kHz,+5.6Vpk

VREF

;,8~-".6_+--,\2NV00Ir--o_ _
T47
pF

'V

T
'V

S/(N+D)
-

max
4 MHz

ClKIN
CS5012
CS5014
CS5016
AID Converter
~

1

EOT

-

CCD orPIN
DIODE ARRAY

I

~

V

16

"
/

--

HOLD

EOC

I

DATA

TOSYSTEM
~

CS
RD
AO

AIN

DIFFAMP

Figure 1. Sample· Logic Jams Converter into High Slew Rate Mode

5.. 152

AN8REV4

-----------------.-----

CS501X APPLICATION HINTS

DARK

DARK

LlGHT1

LlGHT2

AIN

f4----I

t H ----..J

I
HOLD

RST
EOC

Q

-----I;~

I

-----------,~~r---------~---,~7.,--------

~'--------------.~r------------------

FINE CHARGE

~L_ _ _ _ _ _ _ _~I

LI________~

COARSE CHARGE

t H= >15 ClKIN CYCLES

Figure 2. Extending Coarse Charge Time Allows Tracking of Dark to Light Transition

end of a conversion and the beginning of a
coarse charge time. EOC falling toggles the flipflop, causing its Q output to go low. This jams
the NAND gate output high which locks the converter into the coarse charge mode until the
timing generator circuitry resets the flip-flop.

+5V
,-------,

2X
OSCILLATOR

J

ClKIN

Q

K Q

EOT

Figure 2 illustrates the timing of the various signals of the circuit in Figure 1. CCD or PIN
diode array outputs exhibit step changes in their
signal levels as each array element is selected for
output. After each conversion the converter is
stopped in the coarse charge mode until the video
output signal from a particular element of the
sensor array is stable. The clock to the AID converter is then restarted. The converter then
proceeds through the coarse and fine charge
times and awaits a HOLD signal. If the EaT
output of the converter is tied to the HOLD conversion will begin as soon as the track time is
complete.

HOLD
+5V

CS501X
Q

J

Q

K

+5V
EOC

START CONVERT

LI

DATA READY

4--------'

Figure 3.Coarse Charge Jamming with
"StartConvert" Control

AN8REV4

While this coarse charge jamming circuit is designed to operate with the CS501X series of
converters, note that the CS510 1 AID converter
offers a CRSIFIN (coarse/fine) pin as an input to
allow user control of the tracking mode.

Creating a Single "Track, Hold, and Convert"
Command
The coarse charge jamming circuitry of Figure
is altered to allow a single control line to initiate
a sample and convert sequence. First, the EDT
output from the converter must be directly tied to
5-153

-

,

.._-_
...-..
_.-_..--_
__
....
HOLD input. This connection will enable the
converter to initiate a conversion upon completion of 9 clock cycles of fine charge (the
minimum fine charge time necessary for adequate
settling).
At the end of each conversion the EOC signal
will toggle the flip-flop and lock the converter in
coarse charge. The converter will track the input
signal in the coarse charge mode until the "start
convert" input resets the flip-flop to restart the
clock. With EOT tied to HOLD the converter
will proceed through coarse charge, fine charge,
and conversion at which time it will stop and
await another "start convert" command. Data in
the output port will remain available until a new
start convert command is issued, bilt due to internal logic, the port cannot be read in the
byte-wide (BW = 0) mode.
Figure 3 illustrates an example of the "start convert" circuitry using a dual J-K flip-flop. Note
that the input clock is twice that required by the
converter and that the low time of "start convert"
pulse should be less than the conversion time of
the converter. The "start convert" signal should
be held low during calibration.

CS501 X APPLICATION HINTS

of the AID converters such that the reset signal
goes low on a falling edge of the master clock
(CLKIN) to each converter. A common HOLD
command can then be connected to all of the
converters to initiate simultaneous sampling. Or,
if the synchronous loopback mode of sampling is
desired, the EOT output from one of the converters can be input to the HOLD inputs of all of the
converters.
When several converters are galvanically isolated
from the digital processing system, synchronazation is useful. The data is passed across the
isolation barrier in serial form. If several converters are in the system, normally both SDATA
and SCLK signals from each converter are
passed across the isolation barrier. However, if
the converters are synchronized, the SDATA outputs of several converters can be clocked into
serial to parallel registers on the digital side by
sending a single SCLK signal across the barrier.

+5V

Synchronizing Multiple CS501X Series AID
Converters

Simultaneous sampling of several channels is
often required. For example, in measurements of
the outputs of three-axis magnetometers or threeaxis inclinometers it is desireable that all three
signals be simultaneously sampled and then converted. Because the CS501X converters offer
very good repeatibility from part to part they can
yield very good channel to channel measurement
correlation even though each channel is converting with its own AID converter.

---L

74HC14

74HC73 or 74HC107

CS501X
RST
. - - - - - - - I - - - i ClKIN
.---t---i HOLD

CS501X
OSCILLATOR
'----------+-_e__-'---j

HOLD --+-______-'--'---1 HOLD

I I I

Figure 4 illustrates how multiple CS501X series
converters can be synchronized, allowing simultaneous sampling. The circuit uses a flip-flop to
synchronize a reset (RST) signal common to all
5-154

RST
ClKIN

.. .. ..

o
o
o

Figure 4. Controlled Reset for Synchronizatoin of
Multiple Converters
AN8REV4

----------------------

CS501X APPLICATION HINTS

± SV Input Signal Range Operation

LM78L05AC

+12V
-----4>--~V

Some system specifications may require signal
levels of ± 5 V. Operating the CS501X series of
AID converters with ± 5 V signals requires a 5 V
reference and therefore the supplies have to be
raised. The supplies should be adjusted to output
'Voltages in the range from 5.3 to 5.5 volts. The
positive and negative supplies should be of equal
magnitude and the system connections recommended in the AID converter data sheet should
be maintained.
An easy means of achieving the proper supply
voltages is to use LM317L and LM337L regulators. These devices are acceptable as the power
requirements of the AID converter are very low.
See Figure 5 for the appropriate resistor values to
set the regulator voltages. An alternative is to use
LM78L05AC and LM79L05AC regulators with
adjustment resistors to increase their output voltages. This is illustrated in Figure 6.

GND

+

200

20

oV___*-______-+-__________*-____

V IN

+5.5 V (VA+)

V OUT
ADJ

+ 11lF
120

O.lIlF
412

OV--~~------~---------~~~~

AGND

412
+- 11lF

O.lIlF

120
ADJ

V IN

V OUT
LM337L

20

+
GND
-----e>----j

vIN

V OUT f--- 1 indicates wearout and ~ < 1 indicates a
declining failure rate. To use Weibull statistics,
failures that occur during operating life stresses
are used to produce values of R(t). Failure times
and R(t) values can be combined to estimate a
and ~. We first take the natural logarithm of both
sides of equation (8).

6-8

In

[lnR~t)] = ~ In(t)

- In(a)

(10)

This last equation is now in the form of a linear
function. Using linear regression techniques or
Weibull plotting paper we obtain the Weibull
shape and scale parameter. Some semiconductor
manufacturers perform a bum-in screening on devices to insure that the end customer receives a
population of devices that have minimal infant
mortality and are from the useful life period of the
reliability "bathtub" curve. It is very important to
include this data for the entire lifetime of the device to obtain an accurate curve fit for obtaining
a and~.
Once the parameters a and 13 for the Weibull distribution are known we utilize R(t) to calculate
FITS. Crystal uses a 10 year lifetime in its FIT
calculations and typically uses a 48 hour bum-in
at 125°C hence:
tlO = 10 yrs =87,600 hours
tl =48 hours
The number of devices that will fail in the ten
year lifetime following bum-in is given by:
N

=D [R(tI) - R(tI + tIo)]

(11)

where D is the total number of devices stressed.
The number of device-hours accumulated in 10
years can be estimated by counting the devices
surviving after 10 years.
DR

~

D • R(tHho) • tlO

(12)

REL3

......_....
............
.....

.., .,.,

~

~

RELIABILITY METHODS

Using equation (2) for expressed failures in FITS
we obtain the equation below for a Weibull distribution
9 D [ R(h) - R(tl + tlO)]
FITS ~ 10 D. R(h + tlO) • (tlO)

109 [ R(h) - R (h+tlO)]
R(tl+ hO) • (tlO)
(13)

The above equation applies only at the stress temperature. In order to apply the equation to the
desired use temperature we factor in the acceleration factors, Fa, from the Arrhenius relationship as
it relates to time in the reliability function. Therefore in equation (12) above we replace R(h + tlO)
by R(h + haIFa). Note that the device lifetime tlO
is still 10 years but the reliability function must
have the acceleration factor considered for derating to use temperature. Using composite Crystal
data through the second quarter of 1993, yields a
failure rate at 25°C of 8.7 FITS.
This failure rate is a more accurate measure of
Crystal reliability than that provided by the constant failure rate model of equation (5).
Reliability evaluations involve only samples of an
entire population of devices. Therefore a confidence level, (CL), should be placed on the
average failure rate. At any time a sample is
stressed from a population there exists a finite
chance of failures. If many separate samples were
stressed from the same population and failure
rates plotted, a normal distribution of failure rates
would occur. Therefore, valid statistical methods
for a normal distribution should be used to determine the desired CL. Confidence levels for
reliability analysis are expressed in upper confidence levels (UCL) , typically at 60% or 90%
depending on the criticality of the device's application. The total sample size stressed is critical in
defining the UCL. Therefore rather large sample
REL3

sizes must be stressed to more accurately demonstrate the true failure rate. A larger spread
will
exist between the 60% and 90% UCL distribution
for smaller sample sizes due to the greater probability that the sample stressed was not
representative of the entire population.
Environmental stresses, such as autoclave, temperature cycling, thermal shock, storage life and
85°C/85%R.H., usually have their actual results
reported, due to the lack of widely recognized
derating models. These stresses are experiments
in which a given device will either pass or fail.
Test results can be expressed as a simple failure
rate - the number of failing devices divided by the
total number of devices. However, the true failure
rate is usually very small, so often there will be
no failures observed. Instead of reporting an observed failure rate of zero, a confidence bound on
the true failure rate is determined. Crystal uses a
90% confidence level in a standard formula to determine the test results for environmental stresses.

FR=

x2 (2f+2)
2n

(14)

The failure rate, FR, is computed by finding an
upper bound confidence interval from a standard
chi-squared table and dividing it by 2n, where n is
the number of parts in the test, and f is the number of failures observed. X2(2f+2) is the right
endpoint of the interval starting at zero which
spans 90% of the area under the chi-squared curve
with 2f+2 degrees of freedom. This formula results from a Poisson approximation to the
Binomial distribution, which is appropriate when
the Binomial distribution is heavily skewed towards zero. A chi-squared value arises as an easy
way to compute Poisson probabilities. This calculation agrees with the widely accepted lot

6-9

-

.. ..-.
...
...,..,,..,
....
,..,- ,..,,..,

~

-~-

tolerance percent defective, LTPD, plans that are
based on 90 % upper confidence.
Of course it is not satisfactory to have accurate
methods on reporting failure rates without having
programs and methods in place to continuously
improve the reliability of the product. Crystal uses
methodologies in every level of the company to
provide the highest possible quality and reliability
standards of its products.

RELIABILITY METHODS

For further information on a summary of Crystal's
methods of insuring high quality and reliability
standards see the Quality and Reliability information in section 1 of this data book, or contact
Crystal's Reliability and Quality Assurance Department at the factory.

In summary Crystal Semiconductor uses conservative models that are accepted throughout the
semiconductor industry to detennine the reliability
of its devices and has active programs in place to
continuously improve the quality and reliability of
its devices.

6-10

REL3

-----------------------

MECHANICAL DATA

MECHANICAL DATA

40 pin
Ceramic
Side-Brazed
DIP

DIM
A
Al
8

81
C
D
El
e
el
L
oc

16 pin
CerDIP

PLANE

L

DIM
A
A1
B
B1
C
D
E1
e1
eA
L

NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.13mm (0.005") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
~

MD46

MILLIMETERS
MIN
NOM
MAX
3.18
3.81
4.45
1.02
1.27
1.52
0.46
0.58
0.38
0.76
1.14
1.52
0.20
0.25
0.30
50.29 50.80
51.56
14.75
15.11
15.49
15.11
15.49
15.88
2.41
2.54
2.67

3.18
0"

4.45
15"

MILLIMETERS
MIN NOM MAX
3.81
5.08
1.02
0.51
0.38
0.46 0.53
1.78
1.40
0.20
0.25 0.30
19.05 19.30 19.94

6.10
2.41
7.49
2.92
0°

7.24
2.54
7.62
3.81
-

INCHES
NOM
0.150
0.050
0.018
0.045
0.010
2.000
0.580
0.595
0.595
0.610
MIN
0.125
0.040
0.015
0.030
0.008
1.980

0.095
0.125
0"

0.100

.
.

MAX
0.175
0.060
0.023
0.060
0.012
2.030
0.610
0.625
0.105
0.175
15"

INCHES
MIN NOM MAX
0.150 0.200
0.020 0.040
0.015 0.18 0.021
0.055 0.070
0.008 0.010 0.012

0.750 0.760
7.49 0.240 0.285
2.67 0.095 0.100
7.75 0.295 0.300
4.32 0.115 0.150
15°
0°

0.785
0.295
0.105
0.305
0.170
15°

6-11

-

----------- -.----------

MECHANICAL DATA

20 pin

DIM
A
A1
B

CerDiP

NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.13mm (0.005") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.

t~::::::::: :::J

CerDIP

M
!

II

f

L
~

1\
.

C -

I.-BA---I

~

NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.13mm (0.005") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.

6-12

MIN
0.15
0.020
0.015
0.050
0.008
0.940
0.260
0.095
0.295
0.125

MILLIMETERS
MIN NOM MAX
A
3.81 5.08
1.02
A1 0.51 0.38 0.46 0.53
B
1.78
B1 1.27 0,20 0.25 0.30
C
31.24 32.0 32.51
0
E1 12.95 14.73 15.49
81 2.41 2.54 2.67
8A 15.11 15.24 15.37
3.18 3.81 4.32
L
0°
15'

DIM

24 pin

.... '

Bl
C
D
El
e1
eA

MILLIMETERS
MIN NOM MAX
3.81
5.08
0.51
1.02
0.38
0.46 0.53
1.27
1.78
0.20
0.25 0.30
23.88 24.26 24.64
6.60
7.24 7.49
2.41
2.54 2.67
7.49
7.62 7.75
3.18
3.81 4.32
15'
0'

0'

INCHES
NOM MAX
0.200
0.040
0.018 0.021
0.070
0.010 0.012
0.955 0.970
0.285 0.295
0.100 0.105
0.300 0.305
0.150 0.170
15'

MIN
0.150
0.020
0.D15
0.050
0.008
1.230
0.510
0.095
0.595
0.125
0°

INCHES
NOM MAX
0.200
0.040
0.D18 0.021
0.070
0.010 0.012
1.260 1.280
0.580 0.610
0.100 0.105
0.600 0.605
0.150 0.170
15'
-

MD46

----------------------

MECHANICAL DATA

24 pin
Skinny
CerDIP

NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.13mm (0.005") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION 9A TO CENTER OF LEADS WHEN FORMED PARALLEL.

f~::::::::::: :::11

MILLIMETERS

INCHES

MIN
3.81
0.51
0.38
1.27

NOM MAX
0.200
- 0,040
0.018 0.021
0.070

NOM MAX MIN
5.08 0.150
A1
1.02 0.020
0.46 0.53 0.015
8
81
1.78 0.050
C
0.20 0.25 0.30 0.008
D 29.97 32.0 32.51 1.180
5.59 7.11 7.87 0.220
El
el 2.41 2.54 2.67 0.095
eA 7.37 7.62 8.13 0.290
3,18 3.81 4.32 0.125
L
0°
0°
15°

DIM
A

~

MILLIMETERS
DIM
A

28 pin
CerDIP

n
l

.... '

0.51
0.38
81 1.27
0.20
C
D 36.45
El 12.70
2.41
el
eA 15.11
2.92
L
5°
Al
8

\

c I--- e A----i

MIN
4.06

~

0,010 0.012
1.280
0.310
0.105
0.320
0.150 0.170
15°

1.260
0.280
0.100
0.300

INCHES

NOM MAX MIN NOM
5.84 0.160 1.27 0.020 0.46 0.56 0.015 0.018
1.65 0.050 -

0.25
37.08
14.73
2.54
15.24
3,81
-

0.30
37.85
15.37
2.67
15.37
4.06
15°

0.008
1.435
0.500
0.095
0.595
0.115
5°

0.010
1.460
0.580
0.100
0.600
0,150
-

MAX
0.230
0.050
0.022
0.065
0.012
1.490
0.605
0.105
0,605
0,160
15°

NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0,13mm (0.005") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.

MD46

6-13

.....
_.-..--_
___-........

MECHANICAL DATA

f:::: ::::::::::::::::I}'
SEATING
PLANE

MILLIMETERS
MIN NOM MAX
4.06 5.84
0.51 1.27
0.38 0.46 0.56
1.65
1.27 0.20 0.25 0.30
50.29 52.32 52.57
E1 12.70 14.73 15.37
2.41 2.54 2.67
e1
eA 15.11 15.24 15.37
2.92 3.81 4.06
L
15°
5°

40 pin

DIM
A
Ai
B
B.
C
D

CerDIP

1
D
'1----1J~~_ill
A I
.
[AI I L

Bl

----'-' ---Jc---r
el

B

NOTES:

~

INCHES
MIN NOM MAX
0.160
0.230
0.050
0.020 0.015 0.018 0.022
0.050 0.065
0.008 0.010 0.012
1.980 2.060 2.070
0.500 0.580 0.605
0.095 0.100 0.105
0.595 0.600 0.605
0.115 0.150 0.160
15°
5°
-

1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.13mm (0.005") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.

28/44 pin
CLCC

D4/E4

Top View

NO. OF TERMINALS
28

DIM

3.43 0.100 0.120 0.135 2.54 3.05 3.43 0.100 0.120 0.135

A

2.54

3.05

B

0.33

0.46

0.58 0.D13 0.018 0.023 0.33 0.46 0.58 0.013 0.D18 0.023

B1

0.51

0.64

0.81

0.02 0.025 0.032 0.51

0.64 0.81

0.02 0.025 0.032

DIE

12.19 12.46 12.70 0.480 0.490 0.500 17.27 17.53 17.78 0.680 0.690 0.700

D1IEi

11.18 11.43 11.68 0.440 0.450 0.460 16.26 16.51 16.76 0.640 0.650 0.660

D21E2

7.49

D4lE4

10.80 10.92 11.05 0.425 0.430 0.435 15.88 16.00 16.13 0.625 0.630 0.635

·1

6-14

44
MILLIMETERS
INCHES
MILLIMETERS
INCHES
MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX

1.14

7.62

1.27

7.75 0.295 0.300 0.305 12.57 12.70 12.83 0.495 0.500 0.505

1.40 0.045 0.050 0.055 1.14 1.27

1.40 0.045 0.050 0.055

MD46

.-_
_
..--_._.
__.._-_
...-.

MECHANICAL DATA

1 - - - - - 02 - - - - I

Bottom View
Top View

E2

E

1-1'---0
NO. OF TERMINALS

28
MILLIMETERS
DIM

28/44 pin
LCC

44
INCHES

INCHES

MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX

Ai

1.57

1.91

2.49 0.062 0.075 0.098 1.57

1.91

2.49 0.062 0.075 0.098

B

0.51

0.64

0.76 0.020 0.025 0.030 0.51

0.64

0.76 0.020 0.025 0.030

DIE

11.25 11.43 11.73 0.443 0.450 0.462 16.33 16.51 16.81 0.643 0.650 0.662

D2/E2 7.49

7.62

7.75 0.295 0.300 0.305 12.57 12.70 12.83 0.495 0.500 0.505

e

1.14

1.27

1.40 0.045 0.050 0.055 1.14

L

1.14

1.27

1.40 0.045 0.050 0.055 1.14 1.27

1.40 0.045 0.050 0.055

L1

1.91

2.16

2.41 0.075 0.085 0.095 1.91

2.41 0.075 0.085 0.095

16 pin
Plastic DIP

DIM
A
Ai

8
81
C
D
PLANE

MILLIMETERS

L

E1
e1
eA
L

oc

1.27

2.16

1.40 0.045 0.050 0.055

MILLIMETERS
MIN NOM MAX
3.94
5.08
0.51
1.02
0.38 0.46 0.53
0.89
1.27 1.65
0.20 0.25 0.38
18.93 19.43 19.93
6.10 6.35 6.60
2.41
2.54 2.67
7.62
8.25
3.18
3.81
0°
15°

-

-

INCHES
MIN
0.155
0.020
0.Q15
0.035
0.008
0.745
0.240
0.095
0.300
0.125
0°

NOM

0.018
0.050
0.010
0.765
0.250
0.100

-

-

MAX
0.200
0.040
0.021
0.065
0.Q15
0.785
0.260
0.105
0.325
0.150
15°

NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.13mm (0.005") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.

MD46

6-15

-

-____-_

.. .....
. ...-.......
....

MECHANICAL DATA

20 pin
Plastic DIP

DIM
A
A1
B
B1
C
D
E1

e1
eA

NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.

24 pin
Plastic DIP

1
SEATING
PLANE

D

'I

~iiWiWiVJ;-t

B}[n-~-~lrfff~~t~
B

tAl

I

~

L
oc

DIM
A
A1
B
B1
C
D
E1
e1
eA
L

NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION ~ TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.

6-16

oc

MILLIMETERS
INCHES
MIN
NOM MAX
MIN
NOM MAX
3.94
4.57 0.155
0.180
0.51
0.80
1.02 0.020 0.030 0.040
0.38
0.46
0.56 0.Q15 0.018 0.022
1.27
1.52
1.78 0.050 0.060 0.070
0.20
0.25
0.38 0.008 0.010 0.015
24.38 25.40 26.42 0.960 1.000 1.040
6.10
6.35
6.60 0.240 0.250 0.260
2.54
2.67 0.095 0.100 0.105
2.41
8.25 0.300 0.312 0.325
7.62
7.92
3.18
3.30
3.81 0.125 0.130 0.150
O·
O·
15·
15·

-

-

-

-

MILLIMETERS
MIN NOM MAX
3.94 4.32 5.08
0.51
0.76 1.02
0.36 0.46 0.56
1.02 1.27 1.52
0.20 0.25 0.38
31.37 31.75 32.13
13.72 13.97 14.22
2.41
2.54 2.67
15.24
15.87
3.81
3.18
O·
15·

-

-

MIN
0.155
0.020
0.014
0.040
0.008
1.235
0.540
0.095
0.600
0.125

O·

INCHES
NOM
0.170
0.030
0.018
0.050
0.010
1.250
0.550
0.100

-

MAX
0.200
0.040
0.022
0.060
0.Q15
1.265
0.560
0.105
0.625
0.150
15·

MD46

----------------------

MECHANICAL DATA

MILLIMETERS
MIN NOM MAX
3.94 4.32 4.57
0.51 0.76 1.02
0.36 0.46 0.56
1.02 1.27 1.65
0.20 0.25 0.38
31.37 31.75 32.13
6.10 6.35 6.60
2.41 2.54 2.67
7.62
8.25
3.18
3.81
15°
0°

DIM
A
A1
B
81

24 pin
Plastic
Skinny DIP

C

1~- - D - - - - - 1 '1

D
E1
e1
eA
L

-

oc:

NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.

28 pin
Plastic DIP

· ,\
A
f

......

C

\

l--eA----I

DIM
A
A1
8
81

C
D
E1
e1
eA
L
oc

NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.

MD46

MIN
0.155
0.020
0.014
0.040
0.008
1.235
0.240
0.095
0.300
0.125
0°

MILLIMETERS
MIN NOM MAX
3.94 4.32 5.08
0.51 0.76 1.02
0.36 0.46 0.56
1.02 1.27 1.65
0.20 0.25 0.38
36.45 36.83 37.21
13.72 13.97 14.22
2.41 2.54 2.67
15.87
15.24
3.18
3.81
0°
15°

-

INCHES
NOM MAX
0.170 0.180
0.030 0.040
0.Q18 0.022
0.050 0.065
0.010 0.Q15
1.250 1.265
0.250 0.260
0.100 0.105
0.325
- 0.150
15°

-

INCHES
MIN NOM MAX
0.155 0.170 0.200
0.020 0.030 0.040
0.014 0.Q18 0.022
0.040 0.050 0.065
0.008 0.010 0.015
1.435 1.450 1.465
0.540 0.550 0.560
0.095 0.100 0.105
0.600
0.625
0.125
0.150
15°
0°

-

6-17

--------._-.. ------..,---f

MECHANICAL DATA

~::::::::::::::::]}

DIM
A
A1

40 pin
Plastic DIP

B
B1
C
0
E1

e1

NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION SA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION Ei DOES NOT INCLUDE MOLD FLASH.

eA
L
oc

MILLIMETERS
MIN NOM MAX
3.94 4.32 5.08
0.51 0.76 1.02
0.36 0.46 0.56
1.02 1.27 1.65
0.20 0.25 0.38
51.69 52.20 52.71
13.72 13.97 14.22
2.41 2.54 2.67
15.24
15.87
3.81
3.18
150
00
-

MIN
0.155
0.020
0.014
0.040
0.008
2.035
0.540
0.095
0.600
0.125
00

-

INCHES
NOM MAX
0.170 0.200
0.030 0.040
0.Q18 0.022
0.050 0.065
0.010 0.Q15
2.055 2.075
0.550 0.560
0.100 0.105
0.625
0.150
150

-

28/44 pin

PLCC
NO. OF TERMINALS

44

28
MILLIMETERS

E1 E

E~--/--H

DIM

MIN

NOM MAX

A

4.20

4.45

MIN

NOM MAX

MILLIMETERS

MIN

4.57 0.165 0.175 0.180 4.20

NOM MAX
4.45

INCHES

MIN

NOM MAX

4.57 0.165 0.175 0.180

Ai

2.29

2.79

3.04 0.090 0.110 0.120 2.29

2.79

3.04 0.090 0.110 0.120

B

0.33

0.41

0.53 0.013 0.016 0.021 0.33

0.41

0.53 0.013 0.016 0.021

DIE

12.32 12.45 12.57 0.485 0.490 0.495 17.40 17.53 17.65 0.685 0.690 0.695

D1IE1 11.43 11.51 11.58 0.450 0.453 0.456 16.51 16.59 16.66 0.650 0.653 0.656
D2IE2 9.91 10.41 10.92 0.390 0.410 0.430 14.99 15.50 16.00 0.590 0.610 0.630

e

6-18

INCHES

1.19

1.27

1.35 0.047 0.050 0.053 1.19

1.27

1.35 0.047 0.050 0.053

MD46

----------------------

MECHANICAL DATA

68 pin
PLCC
MILLIMETERS

o

DIM

1~·-----------D1--------~~1

A1

D -----------{

B

1---------

A

INCHES

MIN NOM MAX MIN NOM MAX
4.20

4.45

5.08 0.165 0.175 0.200

2.29

2.79

3.30 0.090 0.110 0.130

0.38

0.41

0.53 0.013 0.016 0.021

DIE 25.02 25.15 25.27 0.985
D1/E1 24.13 24.23 24.33 0.950
D2IE2 22.61 23.11 23.62 0.890
1.14 1.27 1.40 0.045
e

0.990 0.995
0.954 0.958
0.910 0.930
0.050 0.055

A

MD46

6-19

------------.----------

MECHANICAL DAtA

1--------0-----------1
1-------01------~

100 pin
TQFP

§o

MILLIMETERS
DIM
A
A1

NOM

-

-

0.00
0.14

0.20

E1

0.40
15.70
13.90
15.70
13.90

0.51
16.00
14.00
16.00
14.00

e

0.077

0.13

L

0.30
0°

0.51

8
C
D

D1
E

oc

6-20

MIN

-

MAX
1.66

MIN

-

0.000
0.006
0.016
0.618
0.547
0.618
0.547

0.26
0.60
16.30
14.10
16.30
14.10

-

INCHES
NOM MAX
- 0.065

-

-

0.008 0.010
0.020 0.024
0.630 0.642
0.551 0.555
0.630 0.642
0.551 0.555

0.177 0.003 0.005 0.007
0.70 0.012 0.020 0.028
12°
0°
- 12°

MD46

_.-_..--_.-.
__.._-_
...-.

MECHANICAL DATA

DIM

8 Pin
SOIC

A

1.78

1.96

2.13

0.070 0.077 0.084

0
1.78
0.33
0.15
5.23
7.67

-

0.25
1.88
0.51
0.25
5.33
8.08

0
0.070
0.013
0.006
0.206
0.302

5.38
1.40

0.204 0.208 0.212
0.045 0.050 0.055
0.019
0.030
0°
8°
-

c
D

E

E1
e
L
oc

pins

16
20

24
28
DIM
A

A1
A2
b

c
0

E

E1
e

MD46

INCHES
MIN NOM MAX

A1
A2
b

SOIC

MILLIMETERS
MIN NOM MAX

5.18
1.14

1.83
0.41
0.20
5.28
7.87
5.30
1.27

0.48
0°

-

0.76
8°

0.072
0.Q16
0.008
0.208
0.310

0.010
0.074
0.020
0.010
0.210
0.318

-

INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
9.91
12.45
14.99
17.53

10.16
12.70
15.24
17.78

10.41
12.95
15.50
18.03

0.390
0.490
0.590
0.690

0.400
0.500
0.600
0.700

0.410
0.510
0.610
0.710

MILLIMETERS
INCHES
MIN NOM MAX MIN NOM MAX
2.41
0.127
2.29

2.54

-

2.41

2.67 0.095 0.100 0.105
0.300 0.005
- 0.012
2.54 0.090 0.095 0.100

0.33 0.46 0.51 0.Q13
0.203 0.280 0.381 0.008
see table above
10.11 10.41 10.67 0.398
7.42 7.49 7.57 0.292

L

1.14
0.41

oc

0°

1.27

- -

-- -

0.018 0.020
0.011 0.015

0.410 0.420
0.295 0.298
1.40 0.040 0.050 0.055
0.89 0.016
- 0.035
0°
8°
8°

-

6-21

•

-------::.==.=
1=::'

MECHANICAL DATA.

11

SSOP Package
Dimensions

E

0

~

TOP VIEW

~'
JL
e

Seating
Plane

L

Et:lID~IEW

MILLIMETERS
INCHES
DIM MIN NOM MAX MIN NOM MAX Note
NOTES:
1. DIMENSIONS D AND E1 ARE REFERENCE DATUMS
AND DO NOT INCLUDE MOLD FLASH OR
PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH
AND ARE MEASURED AT THE PARTING LINE. MOLD
FLASH OR PROTRUSIONS SHALL NOT EXCEED
0.20mmPER SIDE.
2.,DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13mm TOTAL IN EXCESS OF
b DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION
b BY MORE THAN 0.07mm AT LEAST MATERIAL
CONDITION.
3. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 AND 0.2Smm FROM LEAD
TIPS.

6-22

-

-

-

-

2.13
0.084
0.05 0.15 0.25 0.002 0.006 0.010
1.62 1.75 1.88 0.064 0.070 0.074
b 0.22 0.30 0.38 0.009 0.012 0.015 2,3
see other table
D
see other table
1
E 7.40 7.80 8.20 0.291 0.307 0.323
E1 5.00 5.30 5.60 0.197 0.209 0.220 1
e 0.61 0.65 0.69 0.024 0.026 0.027
L 0.63 0.90 1.03 0.025 0.035 0.040

A

A1
A2

N

see other table

see other table

oc

0°

0°

4°

8°

4°

8°

0
N

MILLIMETERS
INCHES
MIN NOM MAX MIN NOM MAX Note

20
28

6.90 7.20 7.50 0.272 0.283 0.295 1
9.90 10.20 10.50 0.390 0.402 0.413 1

MD46

..............
..........
.............

Standard Military Drawings

STANDARD MILITARY DRAWINGS
Crystal Semiconductor manufactures NO converters which meet specifications as defined by DESC
approved Standard Military Drawings. The following cross reference list is provided to assist in the
converter selection process. The SMD (Standard Military Drawing) should be used to determine specifications. Devices are marked with the DESC SMD part number, not with the equivalent Crystal
Semiconductor part number. Consequently, orders can only be accepted for the DESC SMD part number.

Standard Military Drawing Cross Refence
Crystal Part Number

DESC SMD Part Number

CS5012-TDl2B
CS5012-TE12B

5962-8967901 QA
5962-8967901XA

CS5014-SD14B
CS5014-SE14B
CS5014-TD14B
CS50 14-TE 14B

5962-8967401QA
5962-8967401XA
5962-8967402QA
5962-8967402XA

CS5016-SD16B
CS5016-SE16B
CS5016-TD16B
CS5016-TE16B

5962-8967601QA
5962-8967601XA
5962-8967602QA
5962-8967602XA

CS5412-TClB
CS5412-TJlB
CS5412-SCIB
CS5412-SJlB

5962-9095701MQA
5962-9195701MXA
5962-9095702MQA
5962-9095702MXA

CS5101A-SD8B
CS5101A-SE8B
CS5101A-TD8B
CS5101A-TE8B

5962-9169101MXX
5962-9169101M3X
5962-9469102MXX
5962-9169102M3X

CS5102A-SDB
CS5102A-SEB
CS5102A-TDB
CS5102A-TEB

5962-9169201MXX
5962-9169201M3X
5962-9169202MXX
5962-9169202M3X

CS5336-TCB

5962-9469001MXX

6-23

..

""...,....
.....,......
...............
~

Standard Military Drawings

• Notes.

6-24

_

..............
.............
........
..._.-

DATA ACQUISITION DATA BOOK CONTENTS

GENERAL INFORMATION
DATA ACQUISITION
General Purpose
Industrial Measurement
Seismic
High Speed

III

AUDIO PRODUCTS
Consumer/Professional
Broadcast
Multimedia
COMMUNICATIONS PRODUCTS
Infrared Transceiver
Echo Cancellers
Communications Codecs
EthernetlCheapernet
Telecom

a:

APPLICATION NOTES

1111

APPENDICES
Product Category Levels
Reliability Calculation Methods
Package Mechanical Drawings
Standard Military Drawings

I

7-1

-____-_.

.. .....
. ..,-._.
....

SALES OFFICES

CONTENTS

7-2

Crystal Area Sales Offices

7-3

United States Representatives

7-3

United States Distributors

7-7

Canada Representatives

7-9

Europe Sales Offices

7-9

Europe Representatives

7-9

Far East Representatives

7-11

Japan Sales Office

7-12

Japan Distributors

7-12

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._.-.
_
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...

SALES REPRESENTATIVES

UNITED STATES
SALES OFFICES

WESTERN AREA

CENTRAL AREA

EASTERN AREA

Sales Office and
Applications Support:
Crystal Semiconductor Corp.
50 Airport Parkway
San Jose, CA 95110
Ph: 408-437-7743
FAX: 408-437-4943

Crystal Semiconductor Corp.
P.O. Box 17847, 78760
4210 S. Industrial Dr.
Austin, TX 78744
Ph: 512-445-7222
FAX: 512-445-7581

Crystal Semiconductor Corp.
5511 Capital Center Dr., Suite 103
Raleigh, NC 27606
Ph: 919-859-5393
FAX: 919-859-5334
Crystal Semiconductor Corp.
Salem Business Center
68 Stiles Rd., unit H
Salem, NH 03079
Ph: 603-894-5544
FAX: 603-894-5533

Crystal Semiconductor Corp.
27281 Las Ramblas, Suite 200
Mission Viejo, CA 92691
Ph: 714-348-8770
FAX: 714-348-9556

SALES REPRESENTATIVES

ALABAMA

CAUFORNIA

COLORADO

CP&F, Inc.
2317 Starmount Circle
P.O. Box 1424
Huntsville, AL 35807
Ph: 205-536-1506
FAX: 205-551-0558

Earle Associates, Inc.
7585 Ronson Rd., Suite 200
San Diego, CA 92111
Ph: 619-278-5441
FAX: 619-278-5443
Easylink: 62835672

PromoTech
2901 S. Colorado Blvd., Suite A
Denver, CO 80222
Ph: 303-692-8484
FAX: 303-692-8416

ALASKA

Bager Electronics
17220 Newhope St., Suite 209
Fountain Valley, CA 92708
Ph: 714-957-3367
FAX: 714-546-2654

Alpha-Omega Sales Corp.
325 Main St., Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212

Bager Electronics
6324 Varlel Ave., Suite 314
Woodland Hills, CA 91367
Ph: 818-712-0011
FAX: 818-712-0160

DELAWARE

CONNECTICUT
Call Crystal Head Office
Ph: 512-445-7222

ARIZONA
Western High Tech Marketing, Inc.
9414 E. San Salvador, Suite 206
Scottsdale, AZ 85258
Ph: 602-860-2702
FAX: 602-860-2712

ARKANSAS
1L Marketing, Inc.
14850 Quorum Dr., Suite 100
Dallas, TX 75240
Ph: 214-490-9300
FAX: 214-960-6075

NORCOMP, Inc.
1267 Oakmead Parkway
Sunnyvale, CA 94086
Ph: 408-733-7707
FAX: 408-774-1947
NORCOMP, Inc.
8880 Wagon Way
Granite Bay, CA 95746
Ph: 916-791-7776
FAX: 916-791-2223

Nexus Technology Sales, Inc.
200 Lakeside Dr., Suite 236
Horsham,PA 19044
Ph: 215-675-9600
FAX: 215-675-9604

DISTRICT OF COLUMBIA
New Era Sales, Inc.
890 Airport Park Rd., Suite 103
Glen Burnie, MD 21061-2559
Ph: 410-761-4100
FAX: 410-761-2981

7-3

,.'_................
..-- ......
.....
'

SALES REPRESENTATIVE,S

..,

FLORIDA

INDIANA

MARYLAND

CP&F Florida, Inc.
7335 Lake Ellenor Dr.
P.O. Box 593229
Orlando, FL 32809-6219
Ph: 407-855-0843
FAX: 407-851-1464

TMC Electronics
1526 E. Greyhound Pass
Carmel, IN 46032-1036
Ph: 317-844-8462
FAX: 317-573-5472

New Era Sales, Inc.
890 Airport Park Rd., Suite 103
Glen Burnie, MD 21061-2559
Ph: 410-761-4100
FAX: 410-761-2981

TMC Electronics
4630-10 W. Jefferson Blvd.
Ft. Wayne, IN 46804-6800
Ph: 219-432-5553
FAX: 219-432-5555

MASSACHUSETTS

GEORGIA
CP&F Florida, Inc.
2866 Buford Hwy.
Duluth, GA 30136
Ph: 404-497-9404
FAX: 404-497-9412

Call Crystal Head Office
Ph: 512-445-7222

TMC Electronics
1218 Appletree Ln
Kokomo, IN 46902
Ph: 317-459-5152
FAX: 317-457-3822

IDAHO

IOWA

HAWAII

Anderson Associates
270 S. Main St., Suite 108
Bountiful, UT 84010
Ph: 801-292-8991
FAX: 801-298-1503

Stan Clothier Co.
1930 St. Andrews N.E.
Cedar Rapids, IA 52402
Ph: 319-393-1576
FAX: 319-393-7317

lLUNOIS

KANSAS

Micro Sales Inc.
901 W. Hawthorn
Itasca, IL 60143
Ph: 708-285-1000
FAX: 708-285-1008

Stan Clothier Co.
13000 W. 87th St. Parkway, Suite 105
Lenexa, KS 66215
Ph: 913-492-2124
FAX: 913-492-1855

Stan Clothier Co.
3910 Old Hwy. 94 S., Suite 116
St. Charles, MO 63304
Ph: 314-928-8078
FAX: 314-447-5214

KENTUCKY
TMC Electronics
100 Trade St., Suite lA
Lexington, KY 40510-1007
Ph: 606-253-1808
FAX: 606-253-1662

LOUISIANA
1L Marketing, Inc.
14343 Torrey Chase Blvd., Suite 1
Houston, TX 77014
Ph: 713-587-8100
FAX: 713-580-7517

MAINE
Alpha-Omega Sales Corp.
325 Main St., Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212

7-4

Alpha-Omega Sales Corp.
325 Main St., Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212

MICHIGAN
J.MJ. & Associates, Inc.
5075 Cascade Rd. S.E.
Grand Rapids, MI 49546
Ph: 616-285-8887
FAX: 616-285-7633

MINNESOTA
The 1\vist Company
12800 Industrial Park Blvd., Suite 150
Plymouth, MN 55441
Ph: 612-550-0922
FAX: 612-550-0925

MISSISSIPPI
CP&F, Inc.
2317 Starrnount Circle
P.O. Box 1424
Huntsville, AL 35807
Ph: 205-536-1506
FAX: 205-551-0558

MISSOURI
Stan Clothier Co.
3910 Old Hwy. 94 S., Suite 116
St. Charles, MO 63304
Ph: 314-928-8078
FAX: 314-447-5214

MONTANA
PromoTech
2901 S. Colorado Blvd., Suite A
Denver, CO 80222
Ph: 303-692-8484
FAX: 303-692-8416

_
..__ .....
...............
._.
-~-

SALES REPRESENTATIVES

NEBRASKA

NEW YORK

PENNSYLVANIA

Stan Clothier Co.
13000 W. 87th St. Parkway, Suite 105
Lenexa, KS 66215
Ph: 913-492-2124
FAX: 913-492-1855

Nexus Technology Sales
2460 Lemoine Ave.
Fort Lee, NJ 07024
Ph: 201-947-0151
FAX: 201-947-0163

TMC Electronics
One Independence Place
4807 Rockside Rd., Suite 360
Independence,OH 44131
Ph: 216-520-0150
FAX: 216-520-0190

NEVADA

Bob Dean, Inc.
P.O. Box 4568
Ithaca, NY 14852-4568
Ph: 607-257-1111
FAX: 607-257-3678

NORCOMp, Inc.
1267 Oakmead Parkway
Sunnyvale, CA 94086
Ph: 408-733-7707
FAX: 408-774-1947

NEW HAMPSHIRE
Alpha-Omega Sales Corp.
325 Main St., Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212

NEW JERSEY (NORTH)
Nexus Technology Sales
2460 Lemoine Ave.
Fort Lee, N.J. 07024
Ph: 201-947-0151
FAX: 201-947-0163

NEW JERSEY (SOUTH)
Nexus Technology Sales, Inc.
200 Lakeside Dr., Suite 236
Horsham, PA 19044
Ph: 215-675-9600
FAX: 215-675-9604

Bob Dean, Inc.
Hollowbrook Park, Suite 10
15 Myers Corner Rd.
Wappingers Falls, NY 12590
Ph: 914-297-6406
FAX: 914-297-5676

Nexus Technology Sales, Inc.
200 Lakeside Dr., Suite 236
Horsham, PA 19004
Ph: 215-675-9600
FAX: 215-675-9604

RHODE ISLAND
Alpha-Omega Sales Corp.
325 Main St., Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212

NORTH CAROUNA
CPF Atlantic, Inc.
1 Centerview Dr., Suite 306
Greensboro, NC 27407
Ph: 910-852-4498
FAX: 910-852-4556

SOUTH CAROUNA
CPF Atlantic, Inc.
1 Centerview Dr., Suite 306
Greensboro, NC 27407
Ph: 919-852-4498
FAX: 919-852-4556

OHIO
TMCofOhio
9200 Montgomery Rd., Suite llA
Cincinnati, OH 45242
Ph: 513-984-6720
FAX: 513-984-6874
TMC Electronics
One Independence Place
4807 Rockside Rd., Suite 360
Independence,OH 44131
Ph: 216-520-0150
FAX: 216-520-0190

OKLAHOMA
TL Marketing, Inc.
14850 Quorum Dr., Suite 100
Dallas, TX 75240
Ph: 214-490-9300
FAX: 214-960-6075

OREGON

SOUTH DAKOTA
The !Wist Co.
12800 Industrial Park Blvd., Suite 150
Plymouth, MN 55441
Ph: 612-550-0922
FAX: 612-550-0925

TENNESSEE (WEST)
CP&F, Inc.
2317 Starmount Circle
P.O. Box 1424
Huntsville, AL 35807
Ph: 205-536-1506
FAX: 205-551-0558

TENNESSEE (EAST)
CP&F, Florida
2866 Buford Hwy
Duluth, GA 30136
Ph: 404-497-9404
FAX: 404-497-9412

Call Crystal San Jose, CA Office
Ph: 408-437-7743

7·5

.......
.......,
. ....,-._.
~-

...,

~~

SALES REPRESENTATIVES

~

TEXAS

VERMONT

WISCONSIN (S.E.)

TL Marketing, Inc.
8100 Shoal Creek, Suite 250
Austin, TX 78758
Ph: 512-371-7272
FAX: 512-371-0727

Alpha-Omega Sales Corp.
325 Main St., Suite 301
North Reading, MA 01864
Ph: 508-664-1118
FAX: 508-664-3212

Micro Sales, Inc.
210 Regency Court, SuiteL100
Brookfield, WI 53045
Ph: 414-786-1403
FAX: 414-786-1813

TL Marketing, Inc.
14343 Torrey Chase Blvd., Suite 1
Houston, TX 77014
Ph: 713-587-8100
FAX: 713-580-7517
TL Marketing
14850 Quorum Dr., Suite 100
Dallas, TX 75240
Ph: 214-490-9300
FAX: 214-96Qc6075

UTAH
Anderson Associates
270 S. Main St., Suite 108
Bountiful, UT 84010
Ph: 801-292-8991
FAX: 801-298-1503

7-6

VIRGINIA

WISCONSIN (N. w.)

New Era Sales, Inc.
890 Airport Park Rd., Suite 103
Glen Burnie, MD 21061-2559
Ph: 41Qc761-4100
FAX: 410-761-2981

The 'lWist Co.
12800 Industrial Park Blvd., Suite 150
Plymouth, MN 55441
Ph: 612-550-0922
FAX: 612-55Qc0925

WASHINGTON

WYOMING

Call Crystal San Jose, CA Office
Ph: 408-437-7743

PromoTech
2901 S. Colorado Blvd., Suite A
Denver, CO 80222
Ph: 303-692-8484
FAX: 303-692-8416

WEST VIRGINIA
TMC Electronics
7838 Laurel Ave.
Cincinnati, OH 45243-2609
Ph: 513-271-3860
Fax: 513-271-6321

-... .. ...._.-.
~~~~-~~

SALES REPRESENTATIVES

u. S. DISTRIBUTORS
ALABAMA

CALIFORNIA

FLORIDA

Insight Electronics, Inc.
4835 University Square, Suite 19
Huntsville, AL 35816
Ph: 205-830-1222
FAX: 205-830-1225

(Los Angeles)
Insight Electronics
4333 Park Terrace Dr., Suite 101
West Lake Village, CA 91361
(San Fernando Valley)
Ph: 818-707-2101
FAX: 818-707-0321

Nu Horizons Electronics
3421 N.W. 55th St.
Fort Lauderdale, FL 33309
Ph: 305-735-2555
FAX: 305-735-2880

Nu Horizons Electronics
4835 University Square, Suite 10
Huntsville, AL 35816
Ph: 205-722-9330
FAX: 205-722-9348

ARIZONA
Insight Electronics
Tempe,AZ
1515 W. University Dr., Suite 103
Tempe, AZ 85281
Ph: 602-829-1800
Ph: 602-792-1800 (Thcson)
Ph: 505-823-1800 (New Mexico)
FAX: 602-967-2658

(Orange County)
Insight Electronics, Inc.
Two Venture Plaza, Suite 340
Irvine, CA 92718
Ph: 714-727-3291
FAX: 714-727-1804
Insight Electronics
9980 Huennekens
San Diego, CA 92121
Ph: 619-587-1100
FAX: 619-677-3151
Insight Electronics
1295 Oakmead Parkway
Sunnyvale, CA 94086
Ph: 408-720-9222
FAX: 408-720-8390
Nu Horizons Electronics
2070 Ringwood Ave.
San Jose, CA 95131
Ph: 408-434-0800
FAX: 408-434-0935

COLORADO
Insight Electronics
384 Inverness Dr. S., Suite 105
Englewood, CO 80112
Ph: 303-649-1800
FAX: 303-649-1818

Nu Horizons Electronics
600 S. North Lake Blvd., Suite 270
Altamonte Springs, FL 32701
Ph: 407-831-8008
FAX: 407-831-8862
Insight Electronics
600 S. North Lake Blvd., Suite 250
Altamonte Springs, FL 32701
Ph: 407-834-6310
FAX: 407-834-6461
Insight Electronics
621 N.W. 53rd St., Suite 240
Boca Raton, FL 33487
Ph: 407-995-1486
FAX: 407-995-1487
Insight Electronics
13575 58th St. N., Suite 149
Clearwater, FL 34620
Ph: 813-524-8850
FAX: 813-538-4134

GEORGIA
Nu Horizons Electronics
5555 Oakbrook Parkway, Suite 340
Norcross, GA 30093
Ph: 404-416-8666
FAX: 404-416-9060
Insight Electronics, Inc.
3005 Breckinridge, Bldg 210A
Duluth, GA 30136
Ph: 404-717-8566
FAX: 404-717-8588

•
7-7

_...........
._.-.
-......--......

SALES REPRESENTATIVES

~

ILLINOIS

NEW JERSEY

OREGON

Insight Electronics, Inc.
1365 Wiley Rd., Suite 142
Schaumburg, II... 60173
Ph: 708-885-9700
FAX: 708-885-9701

Nu Horizons Electronics
39 U.S. Route 46
Pine Brook, NJ 07058
Ph: 201-882-8300
FAX: 201-882-8398

Insight Electronics
8705 S.W. Numbus, Suite 200
Beaverton, OR 97005
Ph: 503-644-3300
FAX: 503-641-4530

MARYLAND

Nu Horizons Electronics
18000 Horizon Way, Suite 200
Mount Laurel, NJ 08054
Ph: 609-231-0900
FAX: 609-231-9510

Nu Horizons Electronics'
8975 Guilford Rd., Suite 120
Columbia, MD 21046
Ph: 410-995-6330
FAX: 410-995-6332
Insight Electronics, Inc.
6925 Oakland Mills Rd., Suite D
Columbia, MD 21045 .
Ph: 410-381-3131
FAX: 410-381-3141

Insight Electronics, Inc.
2 Eves Dr., Suite 208
Marlton, NJ 08053
Ph: 609-985-5556
FAX: 609-985-5895

NEW YORK
MASSACHUSETTS
Nu Horizons Electronics
19 Corporate Place
107 Audubon Rd., Bldg 1
Wakefield, MA 01880
Ph: 617-246-4442
FAX: 617-246-4462
Insight Electronics
55 Cambridge St., Suite 301
Burlington, MA 01803
Ph: 617-270-9400
FAX: 617-270-3279

MINNESOTA
Insight Electronics
5353 Gamble Dr., Suite 330
St. Louis Park, MN 55416
Ph: 612-525-9999
Fax: 612-525-9998

7-8

Nu Horizons Electronics
6000 New Horizons Blvd.
North Amityville, NY 11701
PH: 516-226-6000
FAX: 516-226-5886
Nu Horizons Electronics
333 Metro Park
Rochester, NY 14623
Ph: 716-292-0777
FAX: 716-292-0750

TEXAS
(Dallas)
Insight Electronics
1778 N. Plano Rd., Suite 320
Richardson, TX 75081
Ph: 214-783-0800 (Richardson)
Ph: 817-338-0800 (Ft. Worth)
FAX: 214-680-2402
Insight Electronics
10777 Westheimer, Suite 1100
Houston, TX 77042
Ph: 713-260-9614
Insight Electronics
11500 Metric Blvd.
Austin, TX 78758
Ph: 512-719-3090
FAX: 512-719-3091
Nu Horizons Electronics
2081 Hutton Dr., Suite 119
Carrollton, TX 75006
Ph: 214-488-2255
FAX: 214-488-2265

OHIO
Nu Horizons Electronics
6200 Sam Center Rd., Suite A15
Solon, OH 44139
Ph: 216-349-2008
FAX: 216-349-2080
Insight Electronics, Inc.
115 E. Aurora Rd., Suite 101
No~field, OH 44067
Ph: 216-467-2522
FAX: 216-0467-3412

WASHINGTON
Insight Electronics
12002 115th Ave. N.E.
Kirkland, WA 98034
Ph: 206-820-8100
FAX: 206-821-2976

_.. .. ......•

..,..,
..,.., ._.

..,~

.r~_

SALES REPRESENTATIVES

CANADA
REPRESENTATIVES

BRITISH COLUMBIA

ONTARIO

QUEBEC

MICROWE Electronics Corp.
5330 Wallace Ave.
Delta, BC
Canada, V4M lAI
Ph: 604-943-5020
FAX: 604-943-8184

InTELaTECH Inc.
5225 Orbitor Dr., Suite 2
Mississauga, Ontario
Canada, lAW 4Y8
Ph: 905-629-0082
FAX: 905-629-1795

InTELaTECH Inc.
6765 Cote De Liesse, Suite 366
St. Laurent, Quebec
Canada, H4T lA7
Ph: 514-343-4877
FAX: 514-343-4355

InTELaTECH Inc.
260 Hearst Way, Suite 248
Kanata, Ontario
Canada, K2L 3Hl
Ph: 613-599-7330
FAX: 613-599-7329

EUROPE
SALES OFFICES
European Sales Office
and Applications Support:

Crystal Semiconductor (UK) Ltd.
Spectrum Point,
279, Farnborough Rd.,
Farnborough,
Hampshire GUl4 7LS,
England
Ph: +44(0)1252372762
FAX: +44(0)1252372763

Crystal Semiconductor
Muhlfelder-Strasse 2
D-82211 Hemching
Germany
Ph: +49(08152)40088
FAX: +49(08152)40077

EUROPEAN DISTRmUTORS

AUSTRIA

BELGIUM & LUXEMBOURG

DENMARK

Eurodis Electronics GmbH
Lamezanstrasse 10
A-1232Wien
Austria
Ph: +43(1)61062-0
(In Austria) (0222)61062-0
FAX: +43(1)61062-151
(In Austria) (0222)61062-151

Alcorn Electronics NYISA
Singel3
2550 Kontich
Belgium
Ph: +32(0345)83033
FAX: +32(0345)83126

Scansupply AfS
Blokken 44
3460 Birkerflld
Denmark
Ph: +45(045)825090
FAX: +45(045)825440
Scansupply AfS
Marselisborg Havnevej 36
8000 Arhus C.
Denmark
Ph: +45(045)825090
FAX: +45(086)127718

7-9

_...... .....
.-..-._.
•.-...,.w
.. •. _ .
.-..-.

SALES REPRESENTATIVES

FINLAND

IRELAND

RUSSIA

Integrated Electronics OyAB
Thrkhaudantie 1
SF-00700 Helsinki
Finland
Ph: +358(0)3513133
FAX: +358(0)3513134

Memec Ireland Ltd.
BlockH
Lock Quay
Clare St.
Limerick, Ireland
Ph: +353(061)411842
FAX: +353(061)411888

PC Center Techno
126 Pervomayskaya St.
Moscow 105203
Russia
Ph: +7(095)4618775
FAX: +7(095)9651020

NewtekS. A.
8, Rue De L'Esterel
Silic 583
94663 Rungis Cedex
France
Ph: +33(01468)72200
FAX: +33(014687)8049

ITALY

Amitron Arrow SA
Albasanz, 75
28037 Madrid
Spain
Ph: +34(1)3043040
FAX: +34(1)3272472

Newtek Sud-Est
4, Rue de l'Europe
ZAC Font-Ratel
38640 CLAIX
France
Ph: +33(076)985601
FAX: +33(076)981604

ISRAEL

FRANCE

SPAIN
Newtek Italia S.P.A.
via Tonoli 1
20145 Milano
Italy
Ph: +39(233)105308
FAX: +39(233)103694

SWEDEN
Telsys
Atidim Industrial Park Bldg 3
Dvora Hanevia St., Neve Sharet,
Tel-Aviv 61431, Israel
Ph: +972(03)492001
TLX: 32392 and 371279
FAX: +972(03)497407

GBTopcomp Electronics
Alstromergatan 22
P.O. Box 12009
10221 Stockholm
Sweden
Ph: +46(086541)080
FAX: +46(086531)251
TLX: 10135

GERMANY
Atlantik Elektronik GmbH
Fraunhoferstrasse, llA
D-82152 Planegg
Germany
Ph: +49(089)857000-0
FAX: +49(089)8573702
TLX: 841-521-5111

NORWAY

SWITZERLAND

NC ScandComp Norway AS
Nils Hansens vei 3
N-0667 Oslo
Norway
Ph: +47(0)22724045
FAX: +47(0)22724059

Metronik GmbH
Leonhardsweg 2
D-82oo8 Unterhaching
Germany
Ph: +49(089)61108-0
FAX: +49(089)61108-161

PORTUGAL

MemotecAG
Gaswerkstrasse 32
P. O. Box
CH-4901 Langenthal
Switzerland
Ph: +41(063)281122
FAX: +41(063)223506
TLX: 845-982550

HOLLAND
Alcorn Electronics BV
Essebaan 1
2900 AI Capelle AID USSEL
Holland
Ph: +31(010)4519533
FAX: +31(010)4586482

7-10

Amitron Arrow Electronica LDA
QTE Grande Lote 20
Alfragide 2700
Amadora
Portugal
Ph: +351(01)4714806
FAX: +351(01)4710802

UNITED KINGDOM
Sequoia Technology Ltd.
Tekelec House
Back Lane
Spencers Wood
Reading, Berks
United Kingdom RG71PD
Ph: +44(0)1734258000
FAX: +44(0)1734258020

-. ..---.. ...._....~-

~~

SALES REPRESENTATIVES

~-

FAR EAST
DISTRIBUTORS

AUSTRALIA

KOREA

TAIWAN

ACD (N.S.w.)
Unit 1, 106 Belmore Rd. Nth.
P. O. Box 402
Riverwood, N. S. W. 2210
Australia
Ph: +61(02)534-6200
TLX: AA121398
FAX: +61(02)534-4910

Cirrus Logic, Korea Co., Ltd.
Rm 1302 SangKyung Bldg., 824-21
YeokSam-Dong,
KangNam-Ku,
Seoul, Korea
Ph: +82(02)565-8561
FAX: +82(02)565-8565

Cirrus Logic International Ltd.
Taiwan Branch
lOF, No.214 Tun Hwa North Rd.
Taipei,
Taiwan R.O.C.
Ph: +886(02)718-4533
FAX: +886(02)718-4526

Hanaro Corp.
Hana Bldg., 122-30 Chungdam-Dong
Gangnam-Ku,
Seoul, Korea 135-100
Youngdong P. O. Box 1588, Seoul
Korea 135-615
Ph: +82(02)516-1144
FAX: +82(02)516-1151
TLX: K26376 HANARO

Morrihan International Corp.
8F-5 No. 57 Fu-Hsing N. Rd.,
Taipei,
Taiwan R. O. C.
Ph: +886(02)752-2200
FAX: +886(02)741-4690
TLX: 20422 MORRIHAN
Taichung Branch
Ph: +886(04)224-6666
FAX: +886(02)741-4690

ACD
Unit 2, 17-19 Melrich Rd.
Bayswater, Victoria, 3153
Australia
Ph: +61(03)762-4244
FAX: +61(03)761-1754
ACD
1048 Beaudesert'Rd.
Coopers Plains, Queensland, 4108
Australia
Ph: +61(07)875-1113
FAX: +61(07)275-3662

HONG KONG
CETLtd.
1108-1112 Metroplaza Tower 2
223 Hing Fong Rd., Kwai Fong
N.T., Hong Kong
Ph: (852)2485-3899
FAX: (852)2485-3802
Cirrus Logic International Ltd.
1203 Park Tower
15 Austin Rd., Tsimshatsui
Kowloon, Hong Kong
Ph: (852)2376-0801
FAX: (852)2375-1202

MALAYSIA
DCP (M) SDN BHD
6th Floor, Wisma Denko
41, Aboo Sitee Lane
10400 Penang
Malaysia
Ph: +6042281860
FAX: +6042281420

SINGAPORE
Dynamar Computer Products, Pte Ltd.
8 Loyang Dr.
Singapore 1750
Ph: +65-542-1878
FAX: +65-542-7188

THAILAND
NEW ZEALAND
ACD
P.O. Box 24-500
Royal Oak
Auckland, New Zealand
Ph: +64(09)636-5984
FAX: +64(09)636-5985

Dynamar Computer Systems
2991119 Visuthanee
1st Floor
Ladprao Rd. SOl 101-103
Kiongchan, Bangkapi
Bangkok 10220
Thailand
Ph: +662-376-0132
FAX: +662-376-0133

•

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SALES REPRESENTATIVES

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JAPAN
SALES OFFICES
Sales Office and
Applications Support:

Cirrus Logic K.K.
Shinjuku Green Tower, Bldg. 26F
6-14-1 Nishi-Shinjuku,
Shinjuku-ku,
Tokyo 160
Japan
Ph: +81(03)3340-9111
FAX: +81(03)3340-9120

DISTRIBUTORS
Intemix, Inc.
Shinjuku Hamada Bldg.,
7-4-7 Nishi-Shinjuku,
Shinjuku-ku,
Tokyo 160
Japan
Ph: +81(03)3369-1105
FAX: +81(03)3363-8486

7-12

Marubun Corp.
Marubun Daiya Bldg.,
8-1 Nihonbashi Odenmacho,
Chuo-ku,
Tokyo 103
Japan
Ph: +81(03)3639-9873
FAX: +81(03)3639-3727
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