1995_Cypress_High Performance_Data_Book 1995 Cypress High Performance Data Book
User Manual: 1995_Cypress_High-Performance_Data_Book
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Cypress
Data Book
SRAMs
Cypress
Data Book
MODULEs
EPROMs
FI F0 s
DUAL PORTs
DATACOM
FCT
LOGIC
CLOCK CHIPs
Cathy Russell
Account Manager
PC CHIPSETs
1995
m--..-II
Marshall Industries
Bay Area
336 Los Coches Street
"'11 ~ 1"'11
Milpitas, CA 95035
(408) 942-4600
(408) 262-1224 Fax
(408) 942-6039 Voice Mail
(408) 994-0839 Pager
Email: crussell@001 .marshall.com
Internet Web site: www.marshall.com
Bow To Use This Book
Overall Organization
Key to Waveform Diagrams
This book has been organized by product type, beginning with Product Information. The products are
next, starting withSRAMs, then Modules, Non-Volatile Memories, FIFOs, Dual-Ports, Data Communications, Bus Interface Products, FCT Logic, Timing Thchnology Products, and PC Chipsets. A section
containing military information is next, followed by
Quality and Reliability aspects, then Thermal Data
and Packages. Within each section, data sheets are arranged in order of part number.
Recommended Search Paths
Th search by:
Use:
Product line
Table of Contents or flip
through the book using the
tabs on the right-hand pages.
Size
The Product Selector Guide
in section 1.
Numeric part number Numeric Device Index following the Table of Contents. The book is also arranged in order of part
number.
Rising edge of signal will
occur during this time.
Falling edge of signal will
occur during this time.
Signal may transition
during this time (don't
care condition).
Signal changes from highimpedance state to valid
logic level during this time.
Signal changes from valid
logic level to high-impedance
state during this time.
Other manufacturer's The Cross Reference Guide
in section 1.
part number
Military part number
The Military Selector Guide
in section 12.
Published May 1995
© Cypress Semiconductor Corporation, 1995. The Information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a maHunction or failure of the product may reasonably be expected to result in significant
injury to the user. The inclusion of Cypress Semiconductor products in life...support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies
Cypress Semiconductor against aU damages.
Table of Contents
Static RAMs (Random Access Memory) (continued)
Device
CY7C197
CY7C199
CY7C1001
CY7C1002
CY7C1006
CY7C1007
CY7C1009
CY7C1014
CY7C1016
CY7C1019
CY7C1021
CY7C1031
CY7CI032
CY7C1088
CY7C1331
CY7C1332
CY7C1335
CY7C1336
CY7C1399
Page Number
Description
256K x 1 Static RAM ........................................................
32Kx 8 Static RAM .........................................................
256K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . ..
256K x 4 Static RAM with Separate I/O .........................................
256K x 4 Static RAM ........................................................
1M x 1 Static RAM ..........................................................
128Kx8StaticRAM ........................................................
256Kx4StaticRAM ........................................................
256K x 4 Static RAM ........................................................
128K x 8 Static RAM ........................................................
64Kx 16 Static RAM ........................................................
64Kx 18 Synchronous Cache RAM ............................................
64Kx 18 Synchronous Cache RAM ............................................
128Kx9StaticRAM ........................................................
64Kx 18 Synchronous Cache 3.3V RAM ........................................
64Kx 18 Synchronous Cache 3.3V RAM ........................................
32Kx 32 Synchronous Cache RAM ............................................
32K x 32 Synchronous Cache RAM ............................................
32Kx 8 3.3V Static RAM .....................................................
Modules
Custom Module Capabilities
Device
CYM1420
CYMI441
CYM1464
CYM1465
CYM1471
CYM1481
CYM1622
CYM1720
CYM1730
CYM1821
CYM1828
CYM1831
CYM1832
CYM1836
CYM1838
CYM1840
CYM1841
CYM1841A
CYMI846
CYM1851
CYM7232
CYM7264
CYM7420
CYM7421
CYM7424
CYM7425
CYM7427
CYM7428
2-208
2-216
2- 227
2-227
2- 234
2-241
2-247
2-254
2-255
2-256
2-257
2-258
2-258
2-270
2-271
2-271
2-283
2- 283
2-286
Page Number
............................................................................ 3-1
Description
128K x 8 Static RAM Module ................................................... 3-5
256K x 8 Static RAM Module ......................'............................ 3-11
512K x 8 Static RAM Module .................................................. 3-16
512K x 8 SRAM Module ........ '; ............................................. 3-22
1024K x 8 SRAM Module ............... ;..................................... 3 - 28
2048K x 8 SRAM Module ..................................................... 3 - 28
64Kx 16 Static RAM Module .................................................. 3-34
32Kx 24 Static RAM Module .................................................. 3-39
64Kx 24 Static RAM Module .................................................. 3-44
16K x 32 Static RAM Module .................................................. 3-49
32K x 32 Static RAM Module .................................................. 3-55
64Kx 32 Static RAM Module .................................................. 3-62
64Kx 32 Static RAM Module .................................................. 3-67
128K x 32 Static RAM Module ................................................. 3-72
128K x 32 Static RAM Module ................................................. 3-77
256K x 32 Static RAM Module ................................................. 3-82
256K x 32 Static RAM Module ................................................. 3 -88
256K x 32 Static RAM Module ................................................. 3 -88
512K x 32 Static RAM Module ................................................. 3-97
1,024K x 32 Static RAM Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-102
DRAM Accelerator Module .................................................. 3 -107
DRAM Accelerator Module .................................................. 3 -107
82420 PClset-Compatible Level II Cache Module ................................ 3 -108
82420 PClset-Compatible Level II Cache Module ................................ 3 -108
128K Cache Module for the Intel ~ 82420EX PClset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-109
256K Cache Module for the Intel 82420EX PCIset ............................... 3-109
82420 PClset-Compatible Level II Cache Module Family .......................... 3-114
82420 PClset-Compatible Level II Cache Module Family. . . . . . . . . . . . . . . . . . . . . . . . .. 3-114
iv
Table of Contents
Page Number
Non-Volatile Memories (continued)
Device
Description
CY7C265
8K x 8 Registered PROM ....................................................
CY7C266
8Kx 8 Power-Switched and Reprogrammable PROM .............................
CY7C269
8K x 8 Registered Diagnostic PROM . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CY7C271
32K x 8 Power-Switched and Reprogrammable PROM ... . . . . . . . . . . . . . . . . . . . . . . . ..
CY7C274
32K x 8 Power-Switched and Reprogrammable PROM . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CY7C271A
32K x 8 Power-Switched and Reprogrammable PROM .... . . . . . . . . . . . . . . . . . . . . . . ..
CY7C276
16K x 16 Reprogrammable PROM ................ '. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CY7C277
32K x 8 Reprogrammable Registered PROM ....................................
CY7C281A
lK x 8 PROM ..............................................................
CY7C282A
lKx8PROM ..............................................................
CY7C287
64K x 8 Reprogrammable Registered PROM ....................................
CY7C291A
2Kx8 Reprogrammable PROM ...............................................
CY7C292A
2Kx8 Reprogrammable PROM ...............................................
CY7C293A
2Kx8 Reprogrammable PROM ...............................................
Non-Volatile Memory Programming Information ............................................................
Page Number
FIFOs
Device
CY7C401
CY7C402
CY7C403
CY7C404
CY7C408A
CY7C409A
CY7C419
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
CY7C432
CY7C433
CY7C4421
CY7C4201
CY7C4211
CY7C4221
CY7C4231
CY7C4241
CY7C4251
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
CY7C439
CY7C441
CY7C443
CY7C451
CY7C453
4-121
4-129
4-136
4-147
4-147
4-148
4-155
4-161
4-168
4-168
4-174
4-180
4-180
4-180
4-189
Description
64 x 4 Cascadable FIFO ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 5 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 4 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 5 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 8 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -12
64 x 9 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -12
256x9CascadableFIFO ...................................................... 5-26
512 x 9 Cascadable FIFO .......... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 26
512 x 9 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 26
lK x 9 Cascadable FIFO ...................................................... 5 - 26
lKx9CascadabieFIFO ...................................................... 5-26
2K x 9 Cascadable FIFO ...................................................... 5 - 26
2K x 9 Cascadable FIFO ...................................................... 5 - 26
4K x 9 Cascadable FIFO ...................................................... 5 - 26
4Kx9CascadabieFIFO ...................................................... 5-26
64 x 9 Synchronous FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -48
256 x 9 Synchronous FIFO ...................................................... 5-48
512 x 9 Synchronous FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-48
lK x 9 Synchronous FIFO ..................................................... 5 -48
2Kx 9 Synchronous FIFO ..................................................... 5-48
4K x 9 Synchronous FIFO ..................................................... 5-48
8K x 9 Synchronous FIFO ..................................................... 5 -48
64 x 18 Synchronous FIFO ..................................................... 5-67
256 x 18 Synchronous FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-67
512 x 18 Synchronous FIFO ......................... ; . . .. . . . . . . . . . . . . . . . . . . . . .. 5~67
lKx 18 Synchronous FIFO .................................................... 5-67
2Kx 18 Synchronous FIFO ..................................................... 5-67
4Kx 18 Synchronous FIFO .................................................... 5-67
BidirectionaI 2Kx9 FIFO ..................................................... 5-86
Clocked 512 x 9 FIFO ........................................................ 5-99
Clocked 2K x 9 FIFO ......................................................... 5 -99
512 x 9 Cascadable Clocked FIFO with Programmable Flags ....................... 5 -115
2K x 9 Cascadable Clocked FIFO with Programmable Flags. . . . . . . . . . . . . . . . . . . . . . .. 5 -115
vi
Table of Contents
;;;- ?cYPRESS
Bus Interface Products
Device
VIC64
VIC068A
VAC068A
CY7C960
CY7C961
CY7C964
Page Number
Description
VMEbus Interface Controller with D64 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-1
VMEbus Interface Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-7
VMEbus Address Controller. . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-16
Slave VMEbus Interface Controller Family ....................................... 8-22
Slave VMEbus Interface Controller Family ....................................... 8-22
Bus Interface Logic Circuit .................................................... 8-27
FCT Logic Products
Page Number
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-1
Device
CY29FCT52T
CY29FCT520T
CY29FCT818T
CY54n4FCT138T
CY54/74FCT157T
CY54n4FCT158T
CY54/74FCT163T
CY54/74FCT191T
CY54/74FCT24OT
CY54/74FCT244T
CY54/74FCT245T
CY54/74FCT257T
CY54/74FCT273T
CY54/74FCT373T
CY54/74FCT573T
CY54/74FCT374T
CY54/74FCT574T
CY54/74FCT377T
CY54/74FCT399T
CY54/74FCT48OT
CY54/74FCT54OT
CY54/74FCT541T
CY54/74FCT543T
CY54/74FCT646T
CY54/74FCT648T
CY54/74FCT652T
CY54/74FCT821T
CY54/74FCT823T
CY54/74FCT825T
CY54/74FCT827T
CY54/74FCT841T
CY54/74FCT224OT
CY54/74FCT2244T
CY54/74FCT2245T
CY54/74FCT2257T
CY54/74FCT2373T
CY54/74FCT2573T
CY54/74FCT2374T
CY54/74FCT2574T
CY54/74FCT2541T
CY54174FCT2543T
Description
8-Bit Registered Transceiver .................................................... 9 - 6
Multi-Level Pipeline Register .................................................. 9-12
Diagnostic Scan Register ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9 -17
1-of-8 Decoder .............................................................. 9-23
Quad 2-Input Multiplexer ..................................................... 9-27
Quad 2-Input Multiplexer ..................................................... 9-27
4-Bit Binary Counter ..........................•.............................. 9-33
4-Bit Up/Down Binary Counter ................................................ 9-38
8-Bit Buffer/Une Driver ...................................................... 9-44
8-Bit Buffer/Line Driver ...................................................... 9 - 44
8-Bit 1tansceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9 - 49
Quad 2-Input Multiplexer ..................................................... 9-54
8-Bit Register ............................................................... 9 - 59
8-Bit Latch .................................................................. 9-64
8-Bit Latch ................................................................... 9-64
8-Bit Register ............................................................... 9 - 69
8-Bit Register ............................................................... 9 - 69
8-Bit Register ............................................................... 9-74
Quad 2-Input Register ........................................................ 9-79
Dual8-Bit Parity Generator/Checker ............................................ 9-84
8-Bit BufferlLine Driver •....................•................................ 9-89
8-Bit Buffer/Line Driver ...................................................... 9-89
8-Bit Latched Registered 1tansceiver ........... , ................................ 9-94
8-Bit Registered 1tansceiver .................................................. 9 -100
8-Bit Registered 1tansceiver .................................................. 9 -100
8-Bit Registered 1tansceiver .................................................. 9 -106
8-Bit Bus Interface Register .................................................. 9 -112
9-Bit Bus Interface Register .................................................. 9-112
lO-Bit Bus Interface Register ................................................. 9-112
lO-Bit Buffer ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-121
lO-Bit Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-126
8-Bit Buffer/Line Driver ..................................................... 9-133
8-Bit Buffer/Line Driver ..................................................... 9-133
8-Bit 1tansceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9 -138
Quad 2-Input Multiplexer .................................................... 9-142
8-Bit Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-146
8-Bit Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-146
8-Bit Register .............................................................. 9 -151
8-Bit Register .............................................................. 9-151
8-Bit Buffer/Line Driver ..................................................... 9-156
8-Bit Latched 1tansceiver .................................................... 9-160
viii
1s~PRESS
Table of Contents
Timing Technology Products (continued)
Page Number
Device
Description
ICD2042A
ICD2051
ICD2053B
ICD2061A
ICD2062B
ICD2063
ICD2093
ICD6233
CY7B991
CY7B992
CY7B9910
CY7B9920
Dual VGA Clock Generator .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-51
Dual Programmable Clock Generator .......................................... 10-56
Programmable Clock Generator ............. : ................................. 10-64
Dual Programmable Graphics Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-71
Dual Programmable ECUITL Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-85
Programmable Graphics Clock Generator ...................................... 10-100
"Super Buffer" Clock Generator ............................................. 10-117
One-Time-Programmable Clock Oscillator ..................................... 10-127
Programmable Skew Clock Buffer (PSCB) ..................................... 10-130
Programmable Skew Clock Buffer (PSCB) ..................................... 10-130
Low Skew Clock Buffer ..................................................... 10-141
10-141
Low Skew Clock Buffer
PCChipsets
Page Number
Device
Description
CY82C597
CY82C599
386/486 Green Chipset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-1
Intelligent PCI Bus Controller ................................................ 11-61
Military Information
Page Number
Military Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-1
Military Product Selector Guide ............................................................................ 12-2
Military Ordering Information ............................................................................. 12-7
Quality and Reliability
Page Number
Quality, Reliability, and Process Flows ...................................................................... 13-1
Tape and Reel Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-16
Packages
Page Number
Thermal Management and Component Reliability ............................................................ 14-1
Package Diagrams ...................................................................................... 14-11
Module Package Diagrams ............................................................................... 14-92
Sales Representatives and Distributors
Direct Sales Offices
North American Sales Representatives
International Sales Representatives
Distributors
x
IT
i:I ~
Numeric Device Index
_"CYPRESS ===============
Device Number
Description
CY54n4FCf825T
CY54/74FCT827f
CY54/74FCT841T
CY6264
CY74FCT162240T
CY74FCf162244T
CY74FCf162245T
CY74FCf162373T
CY74FCf162374T
CY74FCTI6240T
CY74FCTI6244T
CY74FCTI6245T
CY74FCTI62500T
CY74FCT162501 T
CY74FCT162543T
CY74FCT162646T
CY74FCT162652T
CY74FCT162823T
CY74FCf162827f
CY74FCT162841T
CY74FCT162952T
CY74FCf162H244T
CY74FCfI62H245T
CY74FCT162H501T
CY74FCT162H952T
CY74FCf16373T
CY74FCf16374T
CY74FCT16444T
CY74FCT16445T
CY74FCfI6500T
CY74FCf16501T
CY74FCT16543T
CY74FCT16646T
CY74FCTI6652T
CY74FCf16823T
CY74FCf16827f
CY74FCf16841T
CY74FCT16952T
CY7B134
CY7B1342
CY7B135
CY7B138
CY7B139
CY7B144
CY7B145
CY7B8392
CY7B923
CY7B933
CY7B951
CY7B972
CY7B991
CY7B9910
CY7B992
CY7B9920
CY7COO6
CY7C016
CY7C024
lO-Bit Bus Interface Register ................................................. 9-112
10-Bit Buffer .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-121
lO-Bit Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-126
8Kx 8 Static RAM ............................................................ 2-1
16-Bit BufferlLine Driver .................................................... 9-184
16-Bit BufferlLine Driver .................................................... 9-188
16-Bit 1tansceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-193
16-Bit Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-199
16-Bit Register ............................................................. 9-203
16-Bit BufferlLine Driver .................................................... 9-184
16-Bit BufferlLine Driver .................................................... 9-188
16-Bit Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-193
18-Bit Regist'1red 1tansceiver ................................................. 9-207
18-Bit Registered 1tansceiver ................................................. 9-211
16-Bit Latched 1tansceiver ................................................... 9-217
16-Bit Registered 1tansceiver ................................................. 9-223
16-Bit Registered 1tansceiver ................................................. 9-229
18-Bit Register ............................................................. 9-236
2O-Bit Buffer .............................................................. 9-242
2O-Bit Latch ................................................................ 9-247
16-Bit Registered 1tansceiver ................................................. 9-252
16-Bit BufferlLine Driver .................................................... 9-188
16-Bit 1tansceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-193
18-Bit Registered 1tansceiver ................................................. 9-211
16-Bit Registered 1tansceiver ................................................. 9-252
16-Bit Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-199
16-Bit Register ............................................................. 9-203
16-Bit Buffer/Line Driver .................................................... 9-188
16-Bit 1tansceiver ........................................................... 9-193
18-Bit Registered 1tansceiver ................................................. 9-207
18-Bit Registered Transceiver ................................................. 9-211
16-Bit Latched 1tansceiver ................................................... 9-217
16-Bit Registered 1tansceiver ................................................. 9-223
16-Bit Registered 1tansceiver ................................................. 9 - 229
18-Bit Register ............................................................. 9-236
20-Bit Buffer ............................................................... 9-242
2O-Bit Latch ................................................................ 9-247
16-Bit Registered 1tansceiver ................................................. 9-252
4Kx8Dual-PortStaticRAM .................................................. 6-74
4Kx8 Dual-Port Static RAM with Semaphores ................................... 6-74
4Kx 8 Dual-Port Static RAM .................................................. 6-74
4K x 8 Dual-Port Static RAM with Sem, Int, Busy ................................. 6-87
4K x 9 Dual-Port Static RAM with Sem, Int, Busy ................................. 6-87
8Kx8 Dual-Port Static RAM with Sem, Int, Busy ................................ 6-103
8Kx 9 Dual-Port Static RAM with Sem, Int, Busy ................................ 6-103
Ethernet Coax 1tansceiver Interface ............................................ 7.:...67
HOTLink 1tansmitter ......................................................... 7-8
HOTLink Receiver ." ........................................................... 7-8
SST SONET/SDH Serial 1tansceiver ............................................ 7-35
l00BASE-TX/lOBASE-T Fast Ethernet 1tansceiver ................................ 7-66
Programmable Skew Clock Buffer (PSCB) ..................................... 10-130
Low Skew Clock Buffer ..................................................... 10-141
Programmable Skew Clock Buffer (PSCB) ..................................... 10-130
Low Skew Clock Buffer ..................................................... 10-141
16Kx 8 Dual-Port Static RAM with Sem, Int, Busy ................................. 6-1
16K x 9 Dual-Port Static RAM with Sem, Int, Busy ................................. 6-1
4Kx 16 Dual-Port Static RAM with Sem, Int, Busy ................................ 6-18
Page Number
xii
~
'.
Numeric Device Index
_;CYPRESS ================
Page Number
Device Number
Description
CY7C182
CY7C185
CY7C185A
CY7C187
CY7C187A
CY7C188
CY7C191
CY7C192
CY7C193
CY7C194
CY7C195
CY7C196
CY7C197
CY7C199
CY7C225A
CY7C235A
CY7C243
CY7C244
CY7C245A
CY7C251
CY7C254
CY7C261
CY7C263
CY7C264
CY7C265
CY7C266
CY7C269
CY7C271
CY7C271A
CY7C274
CY7C276
CY7C277
CY7C281A
CY7C282A
CY7C287
CY7C291A
CY7C292A
CY7C293A
CY7C401
CY7C402
CY7C403
CY7C404
CY7C408A
CY7C409A
CY7C419
CY7C420
CY7C4201
CY7C4205
CY7C421
CY7C4211
CY7C4215
CY7C4221
CY7C4225
CY7C4231
CY7C4235
CY7C424
CY7C4241
8K x 9 Static RAM .......................................................... 2-142
8Kx8StaticRAM .......................................................... 2-147
8K x 8 Static RAM .......................................................... 2-155
64KxlStaticRAM ......................................................... 2-163
64KxlStaticRAM ......................................................... 2-170
32Kx9StaticRAM .......................................................... 2-178
64Kx 4 Static RAM with Separate I/O .......................................... 2-185
64Kx 4 Static RAM with Separate I/O .......................................... 2-185
32K x 8 Synchronous SRAM ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-193
64Kx4StaticRAM ......................................................... 2-199
64K x 4 Static RAM ......................................................... 2-199
64Kx4StaticRAM ................. ; ....................................... 2-199
256Kx 1 Static RAM ........................................................ 2-208
32Kx 8 Static RAM ......................................................... 2-216
512 x 8 Registered PROM ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-76
lKx 8 Registered PROM ..................................................... 4-83
4K x 8 Reprogrammable PROM. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-90
4K x 8 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-90
2Kx 8 Reprogrammable Registered PROM ...................................... 4-97
16K x 8 Power-Switched and Reprogrammable PROM ..... . . . . . . . . . . . . . . . . . . . . . .. 4-105
16K x 8 Power-Switched and Reprogrammable PROM ..... . . . . . . . . . . . . . . . . . . . . . .. 4-105
8K x 8 Power-Switched and Reprogrammable PROM .... . . . . . . . . . . . . . . . . . . . . . . . .. 4-112
8K x 8 Power-Switched and Reprogrammab\e PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-112
8K x 8 Power-Switched and Reprogrammab\e PROM .... . . . . . . . . . . . . . . . . . . . . . . . .. 4-112
8K x 8 Registered PROM .................................................... 4-121
8K x 8 Power-Switched and Reprogrammab\e PROM ............................. 4-129
8K x 8 Registered Diagnostic PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-136
32K x 8 Power-Switched and Reprogrammab\e PROM ............................ 4-147
32K x 8 Power-Switched and Reprogrammable PROM ... . . . .. . . . . . . . . . . . . . . . . . . .. 4-148
32K x 8 Power-Switched and Reprogrammab\e PROM ............................ 4-147
16K x 16 Reprogrammable PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-155
32K x 8 Reprogrammab\e Registered PROM .................................... 4-161
lKx8PROM .............................................................. 4-168
lK x,8 PROM .............................. ;............................... 4-168
64Kx 8 Reprogrammable Registered PROM ......... '........................... 4-174
2K x 8 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-180
2Kx 8 Reprogrammable PROM ............................................... 4-180
2K x 8 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-180
64 x 4 Cascadable FIFO ....................................................... , 5-1
64 x 5 Cascadable FIFO ....................................................... , 5-1
64 x 4 Cascadable FIFO ....................................................... , 5-1
64 x 5 Cascadable FIFO .. '. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 8 Cascadable FIFO ......................... ; . ; . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-12
64 x 9 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -12
256 x 9 Cascadable FIFO ... . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 26
512x9CascadabieFIFO ...................................................... 5-26
256 x 9 Synchronous FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -48
256 x 18 Synchronous FIFO .................................................... 5-67
512 x 9 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 26
512 x 9 Synchronous FIFO ..................................................... 5-48
512 x 18 Synchronous FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-67
lKx 9 Synchronous FIFO ..................................................... 5-48
lKx 18 Synchronous FIFO .................................................... 5-67
2K x 9 Synchronous FIFO ..................................................... 5 -48
2Kx 18 Synchronous FIFO .................................................... 5-67
lKx9CascadabieFIFO .......................... , ........................... 5-26
4Kx 9 Synchronous FIFO ..... , ............................................... 5-48
xiv
=s
~
Numeric Device Index
~,CYPRESS==================================~
Page Number
Device Number
Description
CYM7421
CYM7424
CYM7425
CYM7427
CYM7428
CYM7432
CYM7450
CYM7451
CYM7490
CYM7491
CYM7492
CYM74A430
CYM74AS50
CYM74AS51
CYM74AS90
CYM74AP54
CYM74S430
CYM74S431
CYM74S550
CYM74S551
CYM74S590
CYM74S591
CYM74SP54
CYM74SP55
CYM9230
CYM9231
CYM9236
CYM9237
CYM9244
CYM9245
CYM9246
CYM9247
ICD2023
ICD2025
ICD2027
ICD2028
ICD2042A
ICD2051
ICD2053B
ICD2061A
ICD2062B
ICD2063
ICD2093
ICD6233
VAC068A
VIC068A
VIC64
82420 PCIset-Compatible Level II Cache Module ................................ 3-108
128K Cache Module for the Intel™ 82420EX PCIset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-109
256K Cache Module for the Intel 82420EX PCIset ,.............................. 3-109
82420 PCIset-Compatible Level II Cache Module Family .......................... 3-114
82420 PCIset-Compatible Level II Cache Module Family. . . . . . . . . . . . . . . . . . . . . . . . .. 3-114
256K Pentium-Compatible Cache Module ...................................... 3-115
128K Cache Module for VLSI VL82C483 Chipset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-118
256K Cache Module for VLSI VL82C483 Chipset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-118
i486™ Level II Cache Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-119
i486 Level II Cache Module .................................................. 3-119
i486 Level II Cache Module .................................................. 3-119
Intel 82430FX PCIset Level II Cache Module ................................... 3-125
OPTi Viper Chipset Level II Cache Module ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 -130
OPTi Viper Chipset Level II Cache Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-130
VLSI 82CS90 Chipset Level II Cache Module ................................... 3-135
Intel 82430NX Chipset Level II Cache Module .................................. 3-120
Intel 82430FX PCIset Level II Cache Module .................................... 3 -125
Intel 82430FX PCIset Level II Cache Module ................................... 3 -125
OPTi Viper Chipset Level II Cache Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-130
OPTi Viper Chipset Level II Cache Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-130
VLSI 82CS90 Chipset Level II Cache Module ................................... 3-135
VLSI 82C590 Chipset Level II Cache Module ................................... 3-135
Intel 82430NX Chipset Level II Cache Module .................................. 3 -120
Intel 82430NX Chipset Level II Cache Module ........... ,...................... 3-120
82420 PCIset-CompatibleLevel II Cache Module ................................ 3-140
82420 PCIset-Compatible Level II Cache Module ............................ ;... 3-140
128K Cache Module for the UMC491 Chipset ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3,141
256K Cache Module for the UMC491 Chipset ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-141
128K Cache Module for the OPTi 802GP Chipset ................................ 3-142
256K Cache Module for the OPTi 802GP Chipset ................................ 3-142
128K Cache Module for the OPTi 802GP Chipset ................................ 3-142
256K Cache Module for the OPTi 802GP Chipset ................................ 3-142
PC Motherboard Clock Generator ............................................. 10-19
Motherboard Clock Generator ................................................ 10-27
PC Motherboard Clock Generator ............................................. 10-33
PC Motherboard Clock Generator ............................................. 10-39
Dual VGA Clock Generator. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-51
Dual Programmable Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-56
Programmable Clock Generator ............................................... 10-64
Dual Programmable Graphics Clock Generator .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-71
Dual Programmable ECI..IITL Clock Generator ................................. 10-85
Programmable Graphics Clock Generator. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-100
"Super Buffer" Clock Generator ........... ;................................. 10-117
One-Time-Programmable Clock Oscillator ..................................... 10-127
VMEbus Address Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-16
VMEbus Interface Controller ................. , ................................. 8-7
VMEbus Interface Controller with D64 Functionality ....... . . . . . . . . . . . . . . . . . . . . . . .. 8-1
xvi
Section Contents
General Product Information
Page Number
Cypress Semiconductor Background ......................................................................... 1-1
Ordering Information ..................................................................................... 1 - 4
Datasheets Available Upon Request ......................................................................... 1-8
Cypress Semiconductor Bulletin Board System (BBS) Announcement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9
Application Notes ....................................................................................... 1-10
Product Selector Guide ................................................................................... 1-12
Product Line Cross Reference ............................................................................. 1-25
ing RoboClock, a programmable skew clock buffer that adjusts
complex timing control signals for a broad range of systems. The
division also offers a broad range of First-In, First-Out (FIFO)
memories, used to communicate data between systems operating
at different frequencies, and Dual-Port Memories, used to distribute data to two different systems simultaneously.
Computation Products Division
This division focuses on the high-volume, high-growth market
surrounding the desktop computer. It is the second of Cypress's
market-oriented divisions. The division includes timing technology products offered through Cypress's IC Designs Subsidiary in
Kirkland, Washington, and a new line of PC chipsets. IC Designs products are used widely in personal computers and disk
drives, and the product line provides Cypress with major inroads
into these growing markets. IC Designs clock oscillators control
the intricate timing of all aspects of a computer system, including
signals for the computer's central processing unit (CPU), keyboard, disk drives, system bus, serial port, and real-time clock.
They replace all of the metal can oscillators. used in the system.
This product line includes QuiXTAL ~ -a programmable metal
can oscillator that replaces individual oscillators used to control
timing signals in virtually every type of electronics equipment.
Cypress's chipset offerings include products for 486-based personal computers, as well as PCI local bus controllers forgraphics
and multimedia desktop applications. Cypress has announced
plans to introduce a low-power, 3.3 volt chipset for the Pentium
P54C, as well as P54C bus controller.
Cypress Facilities
Cypress operates wafer fabrication facilities in California's Silicon Valley (San Jose), Round Rock (Austin), Thxas, and Bloomington, Minnesota. The company's fourth wafer fab, located adjacent to the Bloomington, Minnesota facility, is scheduled to go
on-line in mid-1995. There are additional Cypress Design Centers in Starkville; Mississippi, Colorado Springs, Colorado, and
the United Kingdom, and a PLD software design group in Beaverton, Oregon. The facilities are designed to the most demanding technical and environmental specifications in the industry. At
the Thxas and Minnesota facilities, the entire wafer fabrication
area is specified to be a Class 1 environment. This means that
the ambient air has less than 1 particle of greater than 0.2 microns in diameter per cubic foot of air. Other environmental
considerations are carefully insured: temperature is controlled to
a ±0.1 degree Fahrenheit tolerance; filtered air is completely exchanged more than 10 times each minute throughout the fab;
and critical equipment is situated on isolated slabs to minimize
vibration.
The company has also received IS09OO0 registration, a standard
model of quality assurance that is awarded to companies with
exacting standards of quality management, production, and
inspections.
that we could bring on line quickly. The Cypress search team
scrutinized fifteen manufacturing facilities in five countries and
chose a site managed by Alphatec Electronics Co., Ltd., a privately owned, entrepreneurial company promoted by the Thailand Board of Investment. Cypress Bangkok occupies almost
25,000 square feet-a significant portion of the ·manufacturing
floor space available within the facility. The full facility at Bangkok occupies more than 85,000 square feet on a site that encompasses 25 acres-sufficient room for expansion to a number of
buildings in a campus-like setting.
Manufacturiitg at the site since 1990 with a charter to specialize
in IC packaging, the Alphatec facility has almost a century of
person-years experience working for U.s. semiconductor suppliers. Thoroughly modem, MIL 883-certified, and with fully developed administrative, logistic, and manufacturing systems in
place, the facility has earned an exceptional reputation for hermetic assembly and out-going qUality.
Cypress San Jose maintains complete management control of
Cypress Bangkok's assembly, test, mark, and ship operations
within the facility, thus assuring complete continuity of San
Jose's back-end operations and quality.
Cypress has added Thpe Automated Bonding (TAB) to its package offering. TAB, a surface-mount packaging technology, pro"
vides the densest lead and package footprint available for fully
tested die.
From Cypress's facility in Minnesota, a VME Bus Interface
Products ·group has been in operation since the acquisition of
VTC's fab in 1990. Cypress manufactures VIC and VAC VME
devices on the 0.8 micron CMOS process.
The Cypress motto has ·always been "ouly the best-the best facilities, the best equipment, the best employees ... all striving to
make the best CMOS and BiCMOS products."
Cypress Process Technology
In the last decade, there has been a tremendous need for highperformance semiconductor products manufactured with a balance of SPEED, RELIABILITY, and POWER. Cypress Semiconductor overcame the classically held perceptions that CMOS
was a moderate-performance technology.
Cypress initially introduced a 1.2-micron "N" well technology
with double-layer poly and a single-layer metal. The process
employed lightly doped eXtensions of the heavily doped source
and drain regions for both "N" and "P" channel transistors for
significant improvement in gate delays. Further improvements in
performance, through the use of substrate bias techniques, have
added the benefit of eliminating the input and output latch-up
characteristics associated with older CMOS technologies.
Cypress pushed process development to new limits in the areas
of PROMs (Programmable Read Only Memory) and EPLDs
(Erasable Programmable Logic Devices). Both. PROMs and
EPLDs have existed since the early 1970s in a bipolar process
that employed various fuse technologies and was the ouly viable
high-speed nonvolatile process available. Cypress PROMs and
EPLDs use EPROM technology, which has been in use in MOS
(Metal Oxide Silicon) since the early 1970s. EPROM technology
has traditionally emphasized density while forsaking performance. Through improved technology, Cypress produced the first
high-performance CMOS PROMs and EPLDs, replacing their
bipolar counterparts.
To maintain our leadership position in CMOS technology,
Cypress introduced a sub-micron technology in 1987. This 0.8
micron breakthrough made Cypress's CMOS one of the most
Attention to assembly is equally critical. Cypress manufactures
100 percent of our wafers in the United States, at our front-end
fabrication sites in California (San Jose), Minnesota (Bloomington),
and Thxas (Round Rock). Cypress Thxas, our largest fab, and
Cypress Minnesota, our newest fab, are both Class 1 facilities.
To improve our global competitiveness, we chose to move most
of our back-end assembly, test, and mark operations to a facility
in Thailand. Be assured that Cypress's total quality commitment
extends to the new site-Cypress Bangkok.
The move to Bangkok consummated an intense search by
Cypress for a world-class, environmentally sophisticated facility
1-2
In general, the valid ordering codes for all products (except modules and VMEbus products) follow the format below; e.g.,
CY7C128-45DMB, PALC16R8L-35PC.
RAM, PROM, FIFO, J&p' ECL
PREFIX
r-cY"
CY
CY
CY
DEVICE
SUFFIX
I 7C128 I I -45 D M B I
i7C245
L-35 P C
7C404
-25 D M B
7C9101
-30P C
C= CMOS
L
FAMILY
CMOSSRAM
PROM
FIFO
J.tP
PROCESSING
B =
=
T=
R =
MIL-STD-883C FOR MILITARY PRODUCT
LEVEL 2 PROCESSING FOR COMMERCIAL PRODUCT
SURFACE-MOUNTED DEVICES TO BE TAPE AND REELED
LEVEL 2 PROCESSING ON TAPE AND REELED DEVICES
TEMPERATURE RANGE
C = COMMERCIAL WC TO +70'C)
I = INDUSTRIAL (-40'CTO +85'C)
M= MILITARY (-S5'CTO +125'C)
PACKAGE
A = TIllN QUAD PLSTIC FLATPACK (TQFP)
B = PLASTIC PIN GRID ARRAY (PPOA)
D = CERAMIC DUAL IN-LINE PACKAGE (CERDIP)JBRAZED DIP
E = TAPE AUTOMATED BONDING (TAB)
F = FLATPACK (SOLDER-SEALED FLAT PACKAGE)
G = PIN GRID ARRAY (PGA)
H = WINDOWED LEADED CHIP CARRIER
J = PLASTIC LEADED CHIP CARRIER (PLCC)
K = CERPACK (GLASS-SEALED FLAT PACKAGE)
L = LEADLESS CHIP CARRIER HLCC)
N = PLASTIC QUAD FLATPACK PQFP)
P = PLASTIC DUAL IN-LINE (PD P)
Q = WINDOWED LEADLESS CHIP CARRIER (LCC)
R = WINDOWED PIN GRID ARRAY (PGA)
S = SOIC (GULL WING)
T = WINDOWED CERPACK
U = CERAMIC QUAD FLATPACK (CQFP)
V = SOIC (J LEAD)
W = WINDOWED CERAMIC DUAL IN-LINE PACKAGE (CERDIP)
X = DICE (WAFFLE PACK)
Y = CERAMIC LEADED CHIP CARRIER
SPEED (ns or MHz)
L = LOW-POWER OPTION
A, B, C = REVISION LEVEL
Cypress FSCM #65786
1-4
FeT Octal Products
PREFIX
ICY74FCij
DEVICE
12
3731
SUFFIX
T
t
P
ci
l
PROCESSING
C = -40'CTO +85'C*
C = 0' TO +70' C"
MB = MIL-STD-883B, CLASS B
PACKAGE
D = CERAMIC DUAL IN-LINE PACKAGE (CERDIP)
L = LEADLESS CHIP CARRIER (LCC)
P = PLASTIC DUAL IN-LINE (PDIP)
Q = QSOP
SO = SMALL OUTLINE IC
' - - - - - - - TTL OUTPUT
' - - - - - - - - - SPEED
BLANK = SLOW
A= FAST
B = FASTER
C = VERYFAST
D = FASTEST (SO FAR)
'------------FUNCTION
373 TRANSPARENT LATCH
' - - - - - - - - - - - - - - FAMILY OPTION
BLANK = HIGH DRIVE 64 rnA
2 = 12 rnA DRIVE WITH 250 RESISTOR
' - - - - - - - - - - - - - - - - - TEMPERATURE RANGE
29= MILITARY OR COMMERCIAL
54 = MILITARY TEMP.
74= COMMERCIAL TEMP.
• COMMERCIAL TEMPERATURE IS -40'C TO +85'C FOR "STANDARD" 'w.' AND "B" SPEED
•• COMMERCIAL TEMPERATURE IS O'C TO +70'C FOR "C" SPEED
'
,
1-6
~YPRESS
Datasheets Available Upon Request
Datasheets listed here are not in this catalog but can be obtained from a Cypress Sales Representative.
Static RAMs (Random Access Memory)
Device Number
Description
CY2147
CY2148/CY21lA8/CY2149/CY21LA9
CY6116
4096 x 1 Static R/W RAM
1024 x 4 Static R/W RAM
2048 x 8 Static R/W RAM
2048 x 8 Static R/W RAM
256 x 4 Static R/W RAM Separate 1/0
2048 x 8 Static R/W RAM
4096 x 1 Static RAM
16,384 x 1 Static R/W RAM
4096 x 4 Static RAM
4096 x 4 Static R/W RAM
4096 x 4 Static R/W RAM Separate 1/0
2 x 4096 x 16 Cache RAM
8K x 8 Static RAM
16 x 4 Static R/W RAM
32K x 8 Static R/W RAM
16 x 4 Static R/W RAM
256 x 4 Static R/W RAM
CY6116NCY6117A
CY7C122
CY7C128
CY7C147
CY7C167
CY7C168/CY7C169
CY7C170
CY7C171/CY7C172
CY7C183/CY7C184
CY7C186
CY7C189/CY7C190
CY7C198
CY74S189/CY27LS03/CY27S03/CY27S07
CY93LA22NCY93422/CY93LA22
FlFOs
Device Number
Description
CY3341
64 x 4 Serial Memory FIFO
Logic
Device Number
Description
CY2901C
CY2909/11
CY2910
CY7C901
CY7C909/11
CY7C91O
CMOS 4-Bit Slice
CMOS Microprogram Sequencers
CMOS Microprogram Controller
CMOS 4-Bit Slice
CMOS Microprogram Sequencers
CMOS Microprogram Controller
Modules
Device Number
Description
CYM1466
CYMI611
CYM1830
512K x 8 Static RAM Module
16Kx 16 Static RAM Module
64K x 32 Static RAM Module
1-8
Application Notes
ircYPRESS
Contact a Cypress representative or use the Cypress Bull~tin Board System to get copies. of the application notes listed here.
General Information
I/O Characteristics of Cypress Products
Power Characteristics of Cypress Products
Protection, Decoupling, and Filtering of Cypress CMOS Circuits
System Design Considerations when Using Cypress CMOS
Circuits
Tips for High-Speed Logic Design
Using Decoupling Capacitors
Modules
CYM7232/7264 DRAM Accelerator:
Mixing 5-Volt and 3.3-Volt DRAMs
DRAM Accelerator: Set-Up for Basic Operation
DRAM Configuration and Diagnostics
DRAM Interfacing
Multichip Family of JEDEC ZIP/SIMM Modules
Packages in High-Density Module Designs
ECL and TTL BiCMOS
A New Generation of BiCMOS High-Speed TTL SRAMs
Access Time vs. Load Capacitance for High-Speed TTL SRAMs
BiCMOS TTL & ECL SRAMs Improve High-Performance
Systems
BiCMOS TTL SRAMs Improve R3000 and R3000A Systems
Combining SRAMs Without an External Decoder
Memory and Support for Next-Generation ECL Systems
Noise Considerations in High-Speed Logic Systems
PLCC/CLCC Packaging for High-Speed Parts
Using ECL in Single +5V TTL Systems
SRAMs
Cypress RAM I/O Characteristics
Second-Level Cache and Main Memory Systems for the 80486
Understanding Dual-Port RAMS
Using Dual-Port RAMS Without Arbitration
Using Cypress SRAMs to Implement 386 Cache
Using the CY7C180/181 Cache Thg RAM
Are Your PLDs Metastable?
Bus-Oriented Maskable Interrupt Controller
CMOS PAL Basics
CY7C331 Asynchronous Self-Timed VMEbus Requestor
CY7C344 as a Second-Level Cache Controller for the 80486
CY7C380 Family Quick Power Calculator
Describing State Machines with Wa1p2 VHDL
Design Tips for Advanced Max Users
Designing a Multiprocessor Interrupt Distribution Unit
with MAX
Designing with the CY7C35 and Wa1p2 VHDL Compiler
Designing with FPGAs
DMA Control Using the CY7C342 MAX EPLD
The FLAsH370 Family of CPLDs and Designing with Wa1p2
Implementing a Reframe Controller for the CY7B933 HOTLink
Receiver in a CY7C371 CPLD
FIFO RAM Controller with Programmable Flags
Getting Started Converting .ABL Files to VHDL
Interfacing PROMs and RAMs to DSP Using Cypress
MAX Products
PAL Design Example: A GCR EncoderlDecoder
pASIC380 Power vs. Operating Frequency
PLD-Based Data Path for SCSI-2
State Machine Design Considerations and Methodologies
T2 Framing Circuitry
Thp-Down Design Methodology with VHDL
Using ABEL to Program the Cypress 22V10
Using CUPL with Cypress PLDs
Using Hierarchical VHDL Design
Using LoglIC to Program the CY7C330
Using Scan Mode on pASIC380 for In-Circuit Thsting
Using the CY7C331 as a Waveform Generator
VHDL Techniques for Optimal Design Fitting
Describing State Machines with Wa1p2
PROMs
Designing Custom ALUs and Multipliers with PROMs
Generating PROM Progranuning Files
Interfacing the CY7C276 High-Speed PROM to the AT&T, AD,
Motorola, and TI DSPs
Pinout Compatibility Considerations of SRAMs and PROMs
PLDs
ABEL 4.0/4.1 and the CY7C330, CY7C331, and CY7C332
Abel-HDLvs. IEEE-1076 VHDL
Architectures and Thchnologies for FPGAs
1-10
~YPRESS
Product Selector Guide
Static RAMs
Size
Organization
Pins
Part Number
Speed (ns)
IccIISB
(mA@ns)
Packages
64
16x4-lnverting
16
CY7C189
tAA = 15, 25
55@25
64
16x4-Non-Inverting
16
CY7C190
tAA= 15,25
55@25
L,P
64
16 x 4-lnverting
16
CY74S189
tAA=35
9O@35
D,P
64
16 x 4-lnverting
16
CY27S03A
tAA = 25,35
90@25
D,P
64
16 x 4-Non-Inverting
16
CY27S07A
tAA=25,35
90@25
D,P
lK
256x4
22
CY7C122
tAA = 15,25,35
60@25
D,L,p,S
lK
256x4
24S
CY7CI23
tAA = 7,9,10,12,15
12O@7
L,p,V
lK
256x4
22
CY9122/91L22
tAA = 25,35,45
120@25
P
D,P
lK
256x4
22
CY93422N93L422A
tAA =35,45
80@45
L,P
4K
4Kx l-CS Power-Down
18
CY7C147
tAA = 25,35,45
80/10@35
D,P
4K
4Kx l-CS Power-Down
18
CY2147/21L47
tAA = 35,45,55
125!25@35
D,P
4K
1Kx4-CS Power-Down
18
CY7C148
tAA = 25,35,45
80/1O@35
D,P
4K
lKx4-CS Power-Down
18
CY2148/21L48
tAA = 35,45,55
120/20@35
D,P
4K
lKx4
18
CY7C149
tAA = 25,35,45
80@35
D,L,P
4K
lKx4
18
CY2149/21L49
tAA = 35,45,55
12O@35
D,P
4K
lKx 4-Separate I/O, Reset
248
CY7C150
tAA = 10, 12, 15,25,35
90@12
D,p,8
16K
2Kx B-CS Power-Down
24
CY7C128A
tAA = 15,20,25,35,45,55
90/20@55
D,L,p,V
16K
2KxB-CSPower-Down
24
CY6116A
tAA =20,25,35,45,55
80/20@55
D,L
16K
2Kx B-CS Power-Down
32
CY6117A
tAA = 20,25,35,45,55
80/20@55
L
16K
16Kx l-CS Power-Down
20
CY7C167A
tAA = 15,20,25,35,45
50/15@45
D,P,V
16K
4Kx4-CSPower-Down
20
CY7C168A
tAA = 15,20,25,35,45
70/15@45
D,P,V
16K
4Kx4
20
CY7C169A
tAA = 15,20,25,35,45
70@45
P
16K
4Kx4-0utputEnable
228
CY7C170A
tAA = 15,20,25,35,45
90@45
P,V
16K
4Kx 4-Separate I/O
248
CY7CI71A
tAA = 15,20,25,35,45
90@45
D,L,P,V
16K
4Kx 4-Separate I/O
248
CY7C172A
tAA = 15,20,25,35,45
90@45
D,L,P
64K
8KxB-CS Power-Down
288
CY7C185
tAA = 15,20,25,35
120/20@15
p,V
64K
8KxB-CSPower-Down
28S
CY7C185A
tAA = 15,20,25,35,45
125/40@25
D,L
64K
8KxB-CS Power-Down
28
CY7C186A
tAA = 15,20,25,35,45
125/40@25
D,L
64K
8KxB-CSPower-Down
28
CY7C186
tAA = 20,25,35
120/20@15
P
64K
64Kxl-CSPower-Down
228
CY7C187A
tAA = 15,20,25,35,45
80/40@25
D,L
64K
64Kx l-C8 Power-Down
228
CY7C187
tAA = 15,20,25,35
90/40@15
P,V
64K
16Kx4-C8 Power-Down
228
CY7C164
tAA = 15,20,25,35
115140@15
p,V
64K
16Kx4-0utputEnable
24S
CY7C166
tAA = 15,20,25,35
115/40@15
p,V
64K
16Kx4-Separate 110, 1l-ansparent Write
288
CY7C161
tAA = 15,20,25,35
115/40@15
p,V
64K
16Kx4-Separatel/0
288
CY7C162
tAA = 15,20,25,35
115/40@15
p,V
64K
16Kx4-Separate I/O, 1l-ansparentWrite
28
CY7C161A
tAA = 15,20,25,35,45
l00/40@2O
D,L
64K
16Kx 4-Separate I/O
28
CY7C162A
tAA = 15,20,25,35,45
100/40@2O
D,L
64K
16Kx4-C8Power-Down
22
CY7C164A
tAA = 15,20,25,35,45
100/40@20
D,L
64K
16Kx4-0utputEnable
24
CY7C166A
tAA = 15,20,25,35,45
100/40@20
D,L
12K
8Kx9
28
CY7C182
tAA = 25,35,45,55
140/35@25
P,V;S
256K
32KxB-CSPower-Down
28
CY7C198
tAA = 25, 35, 45
160/35@25
L,P
256K
32KxB-CSPower-Down
28S
CY7C199
tAA = 12, 15,20,25,35,45,
55
170/30@25
D,L,P,V;
Z
256K
256K
32Kx8-CS Power-Down (3.3V)
64Kx4-CSPower-Down
288
24
CY7CI399
CY7C194
tAA = 15,20,25
tAA = 12,15,20,25,35,45
60/25@2O
160/30@25
p,V
D,L,P,V
Note: Please contact a Cypress Representative for product availability.
1-12
.~PRESS
Product Selector Guide
Dual·Port RAMs (continued)
Pins
IcdlsB
(mA@ns)
Speed (ns)
Size
Organization
Pari Number
64K
64K
128K
128K
4Kx 16--Dual-Port, w/Semapb, Busy, Int
4Kxl8-Dual-Port, w/Semapb, Busy, Int
8Kx 16-Dual-Portw/Semaph, Busy, Int
8KxI8-Dual-Portw/Semaph,Busy,lnt
84
84
84
84
CY7C024
CY7C0241
CY7C025
CY7C0251
tAA = 15,25,35
tAA = 15,25,35
tAA = 15, 25, 35
tAA = 15, 25, 35
128K
128K
16Kx8-Dual-Portw/Semaph, Busy, Int
16Kx9-Dual-Portw/Semapb,Busy,lnt
68
68
CY7C006
CY7C016
tAA= 15, 25,35
tAA=15,25,35
Packages
200
200
200
J,A
J,A
J,A
J,A
200
200
J,N
J,N
200
SRAM Modules - Secondary Cache Subsystems
Organization
Size
128K
256K
128K
256K
128K
256K
128K
256K
256K
128K
256K
256K
256K
256K
512K
256K
256K
512K
256K
256K
512K
256K
256K
512K
PClset Secondary Cache
PCIset Secondary Cache
PCIset Secondary Cache
PClse! Secondary Cache
i486 Secondary Cache
i486 Secondary Cache
i486 Secondary Cache
i486 Secondary Cache
i486 Secondary Cache
i486 Secondary Cache
i486 Secondary Cache
Pentium Cache
P54C Cache (Intel ~ Neptune)
P54C Cache (Intel Neptune)
P54C Cache (Intel Neptune)
P54C Cache (Intel Ttiton)
P54C Cache (Intel Ttiton)
P54C Cache (Intel Ttiton)
P54C Cache (OPTi Viper)
P54CCache (OPTi Viper)
P54CCache(OPTiViper)
P54C Cache (VLSI 590)
P54C Cache (VLSI 590)
P54C Cache (VLSI 590)
Pins
112
112
112
112
128
128
112
112
128
112
112
160
160
160
160
160
160
160
160
160
160
160
160
160
Speed (MHz)
Part Number
CYM7420
CYM7421
CYM7424
CYM7425
CYM7450
CYM7451
CYM7427
CYM7428
CYM7491
CYM9236
CYM9237
CYM7432
CYM74AP54
CYM74SP54
CYM74SP55
CYM74A430
CYM74S430
CYM74S431
CYM74A550
CYM74S550
CYM74S551
CYM74A590
CYM74S590
CYM74S591
fmax =33MHz
fmax =33MHz
fmax =33 MHz
fmax =33MHz
fmax =33MHz
fmax =33 MHz
fmax=33MHz
fmax =33 MHz
fmax =33MHz
fmax =33MHz
fmax=33 MHz
fmax =60MHz
fmax=60,66MHz
fmax=60,66MHz
fmax = 60, 66 MHz
50, 60, 66 MHz
50, 60, 66 MHz
50,60, 66 MHz
50, 60, 66 MHz
50, 60, 66 MHz
50, 60, 66 MHz
60, 66 MHz
60, 66 MHz
60, 66 MHz
IcdIsBiIccDR
(mA@ns)
Packages
1100
1200
1000
1600
900
1500
PB
PB
PB
PB
PM
PM
1300
PM
1300
PB
32·Bit Standard SRAM Module Family
Organization
Size
Pins
Speed (ns)
Part Nmnber
IcdIsBilcCDR
(mA@ns)
Packages
512K
16Kx32
64
CYM1821
tAA= 12,15
tAA =20,25,30,35,45
960@12
720@20
PM,PZ
PM,PZ
2M
4M
64Kx32
128Kx32
64
64
CYM1831
CYM1836
720@25
480@20
760@15
PM, PN, PZ
PM,PZ
8M
256Kx32
64
CYM1841
960@25
1120@20
1600@15
PM,PN,PZ
8M
256Kx32 (72-pin Superset)
72
CYM1841AP7
tAA = 15,20,25,30,35,45
tAA = 20,25,30,35,45
tAA= 15
tAA = 25,30,35,45,55
tAA=20
tAA= 15
tAA= 15, 20, 25, 30, 35, 45
960@25
1120@20
1600@15
PM
16M
32M
512Kx32 (72-pin Snperset)
1M x 32 (64-pin Superset)
72
72
CYM1846
CYM1851
tAA=25,30,35
tAA = 25,30,35
800
1250@30
PM,PZ
PM,PN,PZ
Note: Please contact a Cypress Representative for product availability.
1-14
"?cYPRESS
Product Selector Guide
PLDs (continued)
Size
OrgaBization
Pins
IccfIsB
(mA@ns)
Speed (ns)
PartNumber
Packages
PLD24
PLD28
20RA10--Asynchronous
7C330--State Machine
24S
28S
PLD20RAlO
CY7C330
tpOIS/CO = 15/10/15
fMAX., tIS, teo = 66 MH7j3ns/12ns
80
130@50
MHz
D,H,J,L,P,Q,W
D,H,J,L,P,Q,W
PLD28
7C331-Asynchronous,
Registered
28S
CY7C331
tpolS/CO = 20/12/20
120@25ns
D,H,J,L,P,Q,W
PLD28
7C335-UniversaI
Synchronous
28S
CY7C335
fMAXitIS = 100 MHz/2ns,
83MHz/2ns
140
D,H,J,L,P,Q, W
CPLDs
Organization
Size
Pins
Speed (ns)
i'artNnmber
IccfIsB
(mA)
Packages
CY7C344IB
CY7C343IB
tpOIS/CO = 15/9/10, 10/6/5
tPOIS/CO = 20/12/12, 12/8/6
200/150
135/125
D,H,J,p,W
H,J,R
68
CY7C342/B
tpo/s/co = 25/15/14, 12/8/6
250/225
H,J,R
84
CY7C341IB
tpOIS/CO = 25/20/16, 15/lOn
380/360
H,J,R
84,
100
CY7C346IB
tPOIS/CO = 25/15/14, 15/lOn
250/225
H,J,N,R
7C371-32-MacrocellFlash CPLD
44
CY7C371
fMAXits/tco= 143MHz/6.5 ns/6.5 ns
150trBD
J,Y,A
7C372-64-Macrocell Flash CPLD
44
CY7C372
fMAXIts/tco=100MHz/6.5ns/6.5ns
180trBD
J,Y
FLAsH370-84
7C373-64-MacrocellFlash CPLD
84,
100
CY7C373
fMAXits/tco = 100 MHz/6.5 ns/6.5 ns
180trBD
A,J,G,Y
FLASH370-84
7C374-128-MacrocellFlash CPLD
84,
100
CY7C374
fMAXits/teo = 100 MHz/6.5 ns/6.5 ns
300trBD
A,J,G,Y
FLAsH370-160
7C375-128-Macrocell Flash CPLD
160
CY7C375
fMAX/ts/tCO = 100 MHz/6.5 ns/6.5 ns
300trBD A,G,U
FLAsH370-160
7C376-192-Macrocell Flash CPLD
160
CY7C376
fMAX/tS/teo = 83 MH7j1O ns/lO ns
300trBD A,G
FLAsH370- 240
7C377-192-Macrocell Flash CPLD
240
CY7C377
fMAX/ts/teo = 83 MHz/I0 ns/lO ns
300trBD
FLAsH370-160
FLAsH370-240
7C378-256-Macrocell Flash CPLD
7C379-256-Macrocell Flash CPLD
160
240
CY7C378
CY7C379
fMAX/ts/tCO = 83 MHz/1O ns/1O ns
fMAXits/teo = 83 MHz/I0 ns/lO ns
300trBD A,G
300trBD BGA,N,G
MAX28
MAX44
7C344-32 Macrocell
7C343-64 Macrocell
MAX68
7C342-128 Macrocell
MAX84
7C341-192 Macrocell
MAXlOO
7C346-128 Macrocell
FLAsH370-44
FLASH370-44
28S
44
BGA,N,G
FPGAs
Size
Organization
Pins
Part Number
Speed Grade
IccfIsB
(mA)
Packages
pASIC380-1K
CMOS8x12, 1K Gates FPGA
44
CY7C381A
-x, -0, -1,-2
ISB= 10
J
pASIC380-1K
CMOS 8x12, lKGatesFPGA
68,
100
CY7C382A
-X, -0,-1,-2
ISB= 10
A,G,J
pASIC3380-1K3.3V
3.3VCMOS8x12,lKGatesFPGA
44
CY7C3381A
-0,-1
ISB=2
J
pASIC3380-1K3.3V
3.3VCMOS8x12,lKGatesFPGA
68,
100
CY7C3382A
-0,-1
ISB=2
A,J
pASIC380-2K
CMOS 12x16,2KGatesFPGA
68
CY7C383A
-X,-0,-1,-2
ISB= 10
J
pASIC380-2K
CMOS 12x16, 2KGatesFPGA
84,
100
CY7C384A
-X,-0,-1,-2
ISB= 10
A,G,J
pASIC3380-2K3.3V
3.3VCMOSl2x16,2KGatesFPGA
68
CY7C3383A
-0,-1
ISB= 10
J
pASIC3380-2K3.3V
3.3VCMOSl2x16,2KGatesFPGA
84,
100
CY7C3384A
-0,-1
ISB=10
A,J
pASIC380-4K
CMOS 16x24,4KGatesFPGA
84,
100
CY7C385A
-X,-0,-1,-2
ISB= 10
A,J
pASIC380-4K
CMOS 16x24,4KGatesFPGA
144,
160
CY7C386A
-x,-O, -1,-2
ISB= 10
A,G,U
pASIC3380-4K3.3V
3.3VCMOS 16x24,4KGatesFPGA
84,
100
CY7C3385A
-0,-1
ISB= 10
A,J
Note: Please contact a Cypress Representative for product availability.
1-16
Product Selector Guide
.?cYPRESS
EPROMs
Organization
Size
Part Number
Pins
Speed (ns)
IcdlSB
(mA@ns)
100/15 .
Packages
64K
128K
16Kx8--EPROM
16Kx8--EPROM
24
28
CY27C64
CY27C128
tAA = 70,90, 120, 150,200
tAA =45,55,70,90,120,150,200
45/15
D,J,p,W
D,J,p,W
256K
32Kx8--EPROM
28
CY27C256
tAA = 45,55, 70, 90,120,150,200
45/15
D,J,P,W,Z(32-Pin)
256K
32Kx8--EPROM
28S
CY27C256T
lAA = 45, 55, 70, 90, 120, 150,200
45/15
W,Z(28-Pin)
256K
32Kx8--I?PROM
28
CY27H256
lAA = 25,30,35,45,55
50115
D,J,p,W
512K
64Kx8--EPROM
28
CY27C512
lAA = 70,90,120,150,200
40/15
D,J,L,P,Q,W,Z
512K
64Kx8--EPROM
28
CY27H512
lAA = 25, 30, 35, 45, 55, 70
50115
D,H,J,L,P'Q,w,Z
1M
1M
128Kx8--EPROM
128Kx8--EPROM
32
32
CY27COlO
CY27H0l0
lAA = 70,90,120,150,200
lAA=25,30,35,45,55
40/15
50115
D,H,J,L,P,Q, W,Z
D,H,J,L,P,Q,w,Z
FIFOs
Organization
Pins
Part Number
IcdlsB
(mA@ns)
Speed (ns)
Packages
1.2, 2 MHz
5,10,15,25 MHz
10, 15, 25 MHz
45
75
75
18
CY3341
CY7C401
CY7C403
CY7C402
5,10,15,25 MHz
75
D,L,P
D,L,P
64x5-w/OE
18
CY7C404
10, 15, 25 MHz
75
D,L,P
64x8--w/OE and AimoslFiags
288
CY7C408A
15,25, 3S MHz
120
D,L,p,V
64x9-w/AlmosIFiags
288
CY7C409A
15,25,35 MHz
120
D,L,P,V
256x 9-w/HalfFull Flag
28
CY7C419
10,15,20,25,30,40,65
120
D,L,P,V
512x9-w/HalfFuliFiag
28
CY7C420
20, 25,30,40,65
142/30
D,P
512x9-w/HalfFuliFiag
28S
CY7C421
10,15,20,25,30,40,65
142/30
D,J,L,P,V
512 x 9-Clocked
288
CY7C441
14,20,30'
140/30
D,J, L, P, V
512 x 9-Clocked w/Prog. Flags
32
CY7C451
14,20,30'
140/30
D,J,L
512x 18--0ockedw/Prog. Flags
52
CY7C455
14,20,30'
160/40
J,L,N
1Kx9-w/HalfFuliFiag
28
CY7C424
20, 25,30,40,65
142/30
D,P
lKx 9-w/HalfFuli Flag
28S
CY7C425
10,15,20,25,30,40,65
142/30
D,J,L,P,V
lKx 18-Clockedw/Prog. Flags
52
CY7C456
14,20,30'
160/40
J,L,N
64x4
64x4
64x4-w/OE
64x5
16
16
16
D,P
D,L,P
2Kx 9-w/HalfFuli Flag
28
CY7C428
20,25,30,40,65
142/30
D,P
2Kx9-w/HalfFuliFiag
288
CY7C429
10, 15, 20, 25,30,40,65
142/30
D,J,L,P,V
2Kx 9-Bidirectional
28S
CY7C439
25,30,40,65
147/40
D,J,L,P
2K x 9-Clocked
28S
CY7C443
14,20,30'
140/30
D,J,L,p,V
2K x 9-Clocked w/Prog. Flags
32
CY7C453
14,20,30'
140/30
D,J,L
2Kx 18-Clockedw/Prog. Flags
52
CY7C457
14,20,30'
160/40
J,L,N
4Kx9-w/HalfFuliFlag·
28
CY7C432
25,30,40,65
140/25
D,P
4Kx9-w/HalfFuliFiag
28S
CY7C433
10,15,25,30,40,65
140/25
D,J,L,P,V
8Kx 9-w/HalfFullFiag
28
CY7C460
15,25,40
160
D,J,L,P
8Kx 9-w/Prog.Flags
28
CY7C470
15,25,40
160
D,J,L,P
16K x 9-w/HalfFuilFiag
28
CY7C462
15,25,40
160
D,J,L,P
16K x 9-w/Prog. Flags
28
CY7C472
15,25,40
160
D,J,L,P
32K x 9-w/HalfFuilFlag
28
CY7C464
15,25,40
160
D,J,L,P
32K x 9-w/Prog. Flags
28
CY7C474
15,25,40
160
D,J,L,P
64K x 9-Module
28
CYM4208
25,30,40
640/100
HD
128K x 9-Module
28
CYM4209
25,30,40
640/100
HD
64x9
32
CY7C4421
10,15,25,35
50
J,A
Note: Please contact a Cypress Representative for product availability.
1-18
~YPRESS
Product Selector Guide
Communication Products
Description
Pins
Speed (MHz)
Part Number
Packages
Icc(mA)
CY7B923
CY7B933
160-330
160-330
70
130
J,L,S
J,L,S
24
CY7B951
51&155
50
S
16
CY7BS392
10
SO
p'J
Fast Ethernet 100 Base-T4 'ftansceiver
SO
CY7C971
10&100
-
N
HOTlink Evaluation Card
IntegratedATM'ftansceiver
-
CY9266
CY7B955
160-330
51&155
-
C, T,F*
-
N
H01Unk'ftansmitter
HOTI.inkReceiver
28
2S
Serial SONETTransceiver
lO-Base 2/S Ethernet Coax 'ftansceiver
* Interface:
100
C-Coax; T-twisted paIr; F-flber
Timing Technology Products
Application
Motherboard Frequency Synthesizers
Part#
#of
PLLs
#ofOutpnts
Features
Package
7
All PC clocks, 10-S0 MHz, 5V
ICD2025
2
2
3
PC CPU & System clocks, l.S43-100MHz, 5V
16S
ICD2027
2
6
All PC clocks, power-down, 0.76-100 MHz, 5V
20S
ICD202S
3
S
All PC clocks, user-configurable, 0.35 -100 MHz,
5V/3.3V
20S
ICD2023
20S
ICD2093
2
12
Super-Buffer: S skew-controlled CPU clocks, 5V
24S
CY2254
2
14
Pentium 'Iiiton chipset compatible: 4 CPU/6 PCI bufferedclocks,3.3V
2SS
CY2255
2
14
OPTi V~er chipset compatible: 1 early/5 CPU/6 PC!
buffere clocks,3.3V
2SS
CY2257
2
-14
Ali Aladdin chipset compatible: 1 early/5 CPU/6 PCI
buffered clocks, 3.3V
28S
CY2291
3
S
All PC clocks, factory EPROM programmable, 5V/3.3V
20S
ICD2042A
2
3
PCvideo/memory clocks, addressable, 5V
16S
ICD2061A
2
2
PC video/memory clocks, user-programmable, 5V
16S
ICD2062B
2
6
PECL video clock for workstations, 0.5 -165 MHz,5V
20S
ICD2063
2
2
PCvideo/memoryclocks, user-programmable,5V/3.3V
16S
ICD2051
2
5
User-programmable dualPLL, 0.3-120 MHz, 5V
16S
ICD2053B
1
1
User-programmable singlePLL, 0.4-100MHz,5V
SS
QuiXTAL Embedded Crystal Products
ICD6233
1
1
Metal can oscillator package, field programmable
-
Programmable Skew ClockBuffer
(T'TI.Output)
CY7B991
1
S
3 -SO MHz, Programmable Skew (700 ps increments)
J,L
Programmable Skew Clock Buffer
(CMOS Output)
CY7B992
1
S
3 -SO MHz, Programmable Skew (700 ps increments)
J,L
PC Graphics Frequency Synthesizers
GeneralPurpose Programmable Products
PC Chipsets
Description
Single-ch;r. solution for 4S6-based,ra;tems with Green
features. upports SMl/CPU inte ace/cache controll
DRAM controI/lSABus controI/VESA control
Intelligent PCI Bus Bridge Chip. Connects ISABus to the
PCIBus.
Pins
Package
Part Number
160
CYS2C597
N
160
CY82C599
N
Note: Please contact a Cypress Representative for product availability.
1-20
Product Selector Guide
FCTZ-T Octal Logic Products with Resistor (Vcc=5 Volts)
Propagation Delays (ns)
B
A
Standard
Com'll Mil
Com'11 Mil
Com'll Mil
F
Part Number
Organization
Pins
CY54n4FCT224OT
t~~~~~~~~~~~sistor
20
4.3
4.8
5.1
8.0
9.0
D,L,P'Q,SO
CY54n4FCT2244T
8-BitBuffer/Line Driverwith OE
and 25Q Resistor
20
4.1
4.8
5.1
6.5
7.0
D,L,P'Q,SO
CY54n4FCT2245T
8-Bit 1tansceiverwith 00 and 2m
Resistor
20
4.1
4.6
4.9
7.0
7.5
D,L,P'Q,SO
Quad2-~tMultiplexerswith
16
4.3
5.0
5.8
6.0
7.0
D,L,P,Q,SO
CY54n4FCT2257T
OEand
Com'11 Mil
Packages
Q Resistor
CY54n4FCT2373T
8-BitLatchwithOEand25Q
Resistor
20
4.7
5.1
5.2
5.6
8.0
8.5
D,L,P'Q,SO
CY54n4FCT2374T
8-BitRegisterwithOEand25Q
Resistor
20
5.2
6.0
6.5
7.2
10.0
11.0
D,L,P,Q,SO
CY54n4FCT2541T
8-Bit Buffer/Line Driverwith 00,
Flow-Through Pinout and 25Q
Resistor
20
4.1
4.6
4.8
5.1
8.0
9.0
D,L,P,Q,SO
CY54n4FCT2543T
8-Bit Latched 1tansceiverwith 00
and25QResistor
24
5.5
6.1
6.5
7.5
8.5
10.0
D,L,P'Q,SO
CY54n4FCT2573T
8-BitLatchwith OE, FlowThroughPinout and 25Q Resistor
20
4.7
5.1
5.2
5.6
8.0
8.5
D,L,P'Q,SO
CY54n4FCT2574T
8-Bit Registerwith OE, FlowThroughPinout and 25Q Resistor
20
5.2
6.0
6.5
7.2
10.0
11.0
D,L,P,Q,SO
CY54n4FCT2646T
8-Bit Re~stered 1tansceiverwith
OEand QResistor
24
5.4
6.0
6.3
7.7
9.0
11.0
D,L,P'Q,SO
8-Bitlnvertin!lR~tered
24
5.4
6.0
6.3
7.7
9.0
11.0
D,L,P'Q,SO
6.3
7.7
9.0
11.0
D,L,P,Q,SO
8.0
9.0
CY54n4FCT2648T
1tansceiverWlth Eand25Q
Resistor
CY54n4FCT2652T
8-Bit Re~stered 1tansceiverwith
OE and Q Resistor
24
5.4
6.0
CY54n4FCT2827T
IO-BitBufferwith 00 and 25Q Resistor
24
4.4
5.0
5.0
6.5
D,L,P,Q,SO
FCT1616-Bit High Drive Logic Products (Vcc=5 Volts)
Propagation Delays (ns)
Part Number
CY74FCT1624OT
CY74FCT16244T
Organization
Pins
C
B
A
Standard
Com'l
Com'l
Com'l
Com'l
Package
16-Bit Inverting Buffer/Line Driverwith 00
16-Bit Buffer/Line Driverwith OE
48
48
4.3
4.1
4.8
4.8
8.0
6.5
PA,PV
PA,PV
CY74FCT16245T
16-Bit 1tansceiverwith OE
48
4.1
4.6
7.0
PA,PV
CY74FCT16373T
16-BitLatch with OE
48
4.2
5.2
8.0
PA,PV
CY74FCT16374T
16-BitRegisterwithOE
48
5.2
6.5
10.0
PA,PV
ey74FCTl6444T
16-Bit244with Single OE
48
4.1
4.8
6.5
PA,PV
CY74FCTl6445T
16-Bit245withSiugleOEandDIR
48
4.1
4.6
7.0
PA,PV
CY74FCT1650OT
18-Bit Universal Bus 1tansceiver
56
4.6
5.1
CY74FCT~6501T
18-Bit Universal Bus 1tansceiver
56
4.6
5.1
CY74FCT16543T
16-Bit Latched 1tansceiverwith OE
56
5.3
6.5
8.5
PA,PV
CY74FCT16646T
16-Bit Registered 1tansceiverwith OE
56
5.4
6.3
9.0
PA,PV
CY74FCTl6652T
16-Bit Registered 1tansceiverwith OE
56
5.4
6.3
9.0
PA,PV
CY74FCTl6823T
18-Bit Registerwith OE
56
6.0
7.5
10.0
CY74FCT16827T
20-Bit Bufferwith OE
56
4.4
5.0
8.0
PA,PV
CY74FCTl6841T
CY74FCT16952T
2O-Bit LatShwith OE
16-Bit Registered 1tansceiver
56
5.5
56
6.3
6.5
7.5
9.0
10.0
PA,PV
PA,PV
Note: Please contact a Cypress Representative for product availability.
1-22
PA,PV
PA,PV
PA,PV
~YPRESS
Product Selector Guide
FCT2 Octal Logic Products with Resistor (Vcc=5 volts)
Propagation Delays (ns)
C
B
A
Standard
Com'l! Mil
Com'l! Mil
Com'l! Mil
Com'll Mil
Part Number
Organization
Pins
CY54n4FCT224OT
~~~~~;ti~~~~:~~sistor
20
4.3
4.8
5.1
8.0
9.0
D,L,P'Q,SO
CY54/74FCT2244T
8-Bit BufferlLine Driverwith OE
and 25Q Resistor
8-Bit'fransceiverwithDEand25Q
Resistor
2Ead2-~ut Multiplexerswith
and Q Resistor
8-Bit Latchwith OE and 25Q
Resistor
8-Bit Registerwith OE and 25Q
Resistor
8-Bit Buffer/Lioe Driverwith OE,
Flow-ThroughPinoutand25Q
Resistor
8-Bit Latched 'fransceiverwith OE
and 25Q Resistor
8-Bit Latchwith OE, FlowThrough Pioout and 25Q Resistor
8-Bit Registerwith DE, FlowThroughPinout and 25Q Resistor
8-Bit Re~stered 'fransceiverwith
OEand QResistor
8-Bit Invertio!l Rnrtered
'fransceiverwlth
and25Q
Resistor
8-Bit Re~stered 'fransceiverwith
OEand QResistor
10-BitBufferwith OEand 25QRe-
20
4.1
4.8
5.1
6.5
7.0
D,L,P'Q,SO
20
4.1
4.6
4.9
7.0
7.5
D,L,P,Q,SO
16
4.3
5.0
5.8
6.0
7.0
D,L,P'Q,SO
CY54/74FCT2245T
CY54/74FCT2257T
CY54/74FCT2373T
CY54/74FCT2374T
CY54/74FCT2541T
CY54/74FCT2543T
CY54/74FCT2573T
CY54/74FCT2574T
CY54/74FCT2646T
CY54/74FCT2648T
CY54/74FCT2652T
CY54/74FCT2827T
sistor
Packages
20
4.7
5.1
5.2
5.6
8.0
8.5
D,L,P,Q,SO
20
5.2
6.0
6.5
7.2
10.0
11.0
D,L,P,Q,SO
20
4.1
4.6
4.8
5.1
8.0
9.0
D,L,P,Q,SO
24
5.5
6.1
6.5
7.5
8.5
10.0
D,L,P'Q,SO
20
4.7
5.1
5.2
5.6
8.0
8.5
D,L,P'Q,SO
20
6.5
7.2
10.0
11.0
D,L,P,Q,SO
11.0
D,L,P'Q,SO
5.2
6.0
24
5.4
6.0
6.3
7.7
9.0
24
5.4
6.0
6.3
7.7
9.0
11.0
D,L,P,Q,SO
24
5.4
6.0
6.3
7.7
9.0
11.0
D,L,P'Q,SO
24
4.4
5.0
8.0
9.0
S.O
6.5
D,L,P,Q,SO
Notes:
The ahove specifications are for the commercial temperature range of O°C to 70°C. Military temperature range (-55°C to +125°C) product processed
to MIL-STD-883 Revision C is also available for most products. Speed and power selections may vary from those above. Contact your local sales office
for more information.
Commercial grade product is available io plastic, CERDIp, or LCC. Military grade product is available in CERDIp, LCC, or PGA.
Power supplies for most product lines are Vee = SV ± 10%.
22S, 24S, 28S stands for 300 mil. 22-pin, 24-pio, 28-pio, respectively. 28.4 stands for 28-pio 400 mil, 24.4 stands for 24-pin 400 mil.
PLCC, SOJ, and SOIC packages are available on some products.
F, K, and T packages are special order only.
Please contact a Cypress representative for product availability.
MAX and MAX +PLUS are registered trademarks of Altera Corporation. Pentium is a trademark of Intel Corporation.
Package Code:
B = Plastic Pin Grid Array
D = CerDIP
E = Thpe Automated Bond (TAB)
F = Flatpack
G = Pio Grid Array (PGA)
H = Wiodowed Hermetic LCC
J = PLCC
K = Cerpack
L = Leadless Chip Carrier (LCC)
N = Plastic Quad Flatpack
P = Plastic
Q
Q
R
S
T
U
V
W
X
Y
Z
= Windowed LCC
HD = Hermetic DIP (Module)
= QSOP
= Windowed PGA
= SOIC
= Wiodowed Cerpack
= Ceramic Quad Flatpack
= SOJ
= Windowed Cerdip
= DICE
= Ceramic LCC
= TSOP
HG
PA
PD
PM
PN
PS
PV
PZ
SO
Document #: 38-00237-E
Note: Please contact a Cypress Representative for product availability.
1-24
= Ceramic PGA (Module)
TSSOP
Plastic DIP (Module)
Plastic SIMM
Plastic Augled SIMM
= Plastic SIP
= SSOP
,; Plastic ZIP
= SOIC
=
=
=
=
~
~
=s:::-
Product Line Cross Reference
'i.
'CYPRESS
ALTERA
CYPRESS
ALTERA
CYPRESS
5032PC-2
5032PC-15
5032PC-17
5032PC-20
5032PC-25
5064JC
5064JC-1
5064JC-2
5064JI
5064JM
5064LC
5064LC-1
5064LC-2
5128AGC-12
5128AGC-15
5128AGC-20
5128AJC-12
5128AJC-15
5128AJC-20
5128ALC-12
5128ALC-15
5128ALC-20
5128GC
5128GC-1
5128GC-2
5128GM
5128JC
5128JC-1
5128JC-2
5128JI
5128JI-2
5128JM
5128LC
5128LC-I
5128LC-2
5128LI
5128LI-2
5130GC
5130GC-l
5130GC-2
5130GM
5130JC
5130JC-l
5130JC-2
5130JM
5130LC
5130LC-l
5130LC-2
5130LI
5130LI-2
5130QC
5130QC-1
5130QC-2
5130QI
5192AGC-15
5192AGC-20
5192AJC-15
5192AJC-20
5192ALC-1
5192ALC-2
5192GC
5192GC-l
7C344-20PC
7C344-15PC
Call Factory
7C344-20PC
7C344-25PC
7C343-35HC
7C343-25HC
7C343-30HC
7C343-35H1
7C343-35HMB
7C343-35JC
7C343-25JC
7C343-30JC
7C342B-12RC
7C342B-15RC
7C342B-20RC
7C342B-12HC
7C342B-15HC
7C342B-20HC
7C342B-12JC
7C342B-15JC
7C342B-20JC
7C342-35RC
7C342-25RC
7C342-30RC
7C342-35RMB
7C342-35HC
7C342-25HC
7C342-30HC
7C342-35H1
7C342-30HI
7C342-35HMB
7C342-35JC
7C342-25JC
7C342-30JC
7C342-35JI
7C34Z-30HI
7C346-35RC
7C346-25RC
7C346-30RC
7C346-35RM
7C346-35HC
7C346-25HC
7C346-30HC
7C346-35HM
7C346-35JC
7C346-25JC
7C346-30JC
7C346-35JI
7C346-3OJI
7C346-35NC
7C346-25NC
7C346-30NC
7C346-35NI
7C341B-15RC
7C341B-20RC
7C341B-15HC
7C341B-20HC
7C341B-15JC
7C341B-ZOJC
7C341-35RC
7C341-25RC
5192GC-2
5192JC
5192JC-1
5192JC-2
5192JI
5192LC
5192LC-1
5192LC-2
7C341-30RC
7C341-35HC
7C341-25HC
7C341-30HC
7C341-35H1
7C341-35JC
7C341-25JC
7C341-30JC
AMD
PREFIX: Am
PREFIX:SN
SUFFIX:B
SUFFIX:D
SUFFIX:E
SUFFIX:F
SUFFIX:J
SUFFIX:L
SUFFIX:P
27C64-55C
27C64-70C
27C64-90C
27C64-120C
27C64-150C
27C64-200C
27COlO-90C
27COlO-120C
27COIO-150C
27COlO- 200C
27C128-45C
27C128-55C
27C128-70C
27C128-90C
27C128-120C
27C128-150C
27C128-200C
27C256-55C
27C256-70C
27C256-90C
27C256-120C
27C256-150C
27C256-200C
27C512-75C
27C512-90C
27C512 -120C
27C512-150C
27C512-200C
27HOlO-45
27HOlO-55
27HOlO-70
27HOlO-90
27H256-35C
27H256-45C
27H256-45M
27H256-55C
27H256-55M
27H256-70C
27LS291M
27PSI91AC
27PS191AM
27PSl91C
27PS191M
27PS291AC
PREFIX:CY
PREFIX:CY
SUFFIX:B
SUFFIX:W
SUFFIX:Z
SUFFIX:F
SUFFIX:J
SUFFIX:L
SUFFIX:P
7C266-55C
27C64-70C
27C64-90C
27C64-120C
27C64-150C
27C64-200C
27C010-90C
27C010-120C
27COlO-150C
27C010-200C
27C128-45C
27C128-55C
27C128-70C
27CI28-90C+
27C128-120C+
27C128-150C+
27C128-200C+
27C256-55C
27C256-70C+
27C256-90C+
27C256-120C+
27C256-150C+
27C256-200C+
27H512-70C
27H512-90C
27H512-120C
27H512-150C
27H512-200C
27HOlO-45
27HOlO-55
27COlO-70
27COlO-90
27H256-35C
27C256-45C
27C256-45M
27C256-55C
27C256-55M
27C256-70C
7C291A-35M
7C292A-50C
7C292A-50M+
7C292A-50C
7C292A-50M+
7C293A-50C
CYPRESS
AMD
27PS291AM
27PS291C
27PS291M
27S181AC
27S181AM
27S181C
27S181M
27S191AC
27S191AM
27S191C
27S191M
27S191SAC
27S191SAM
27S25AC
27S25AM
27S25C
27S25M
27S25SAC
27S25SAM
27S43AC
27S43C
27S281AC
27S281AM
27S281C
27S281M
27S291AC
27S291AM
27S291C
27S291M
27S291SAC
27S291SAM
27S35AC
27S35AM
27S35C
27S35M
27S45AC
27S45AM
27S45C
27S45M
27S45SAC
27S45SAM
27S49A
27S49AM
27S49C
27S49M
27S49SAC
27S49SAM
2841AC
2841AM
2841C
2841M
7201-25
7201-25R
7201-35
nOI-35R
7201-50
7201-50R
7201-65
7201-65R
7201-80
120l-80R
7202A-15
Note: Unless otherwise noted, product meets all perfoonance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all perfoonance specs but may not meet Icc or ISB
* - meets all perfoonance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t = SOIC only
:j: = 32-pin LCC crosses to the 7C198M
1-26
** - See Austin Semiconductor for military products
CYPRESS
7C293A-50M+
7C293A-50C
7C293A-50M+
7C282A-30C
7C282A-45M
7C282A-45C
7C282A-45M
7C292A-35C
7C292A-50M
7C292A-50C
7C292A-50M
7C292A-25C
7C292A-30M
7C225A-30C
7C225A-35M
7C225A-40C
7C225A-40M
7C225A-25C
7C225A-30M
7C244--45C
7C244-55C
7C281A-30C
7C281A-45M
7C281A-45C
7C281A-45M
7C291A-35C
7C291A-50M
7C291A-50C
7C291A-50M
7C291A-25C
7C291A-30M
7C235A-30C
7C235A-40M
7C235A-40C
7C235A-40M
7C245A-35C
7C245A-45M
7C245A-45C
7C245A-45M
7C245A-25C
7C245A-25M7C264-40C
7C264-55M
7C264-55C
7C264-55M
7C264-25C
7C264-25M
334lC
3341M
3341C
3341M
7C420-25
7C421-25
7C420-30
7C421-30
7C420-40
7C421-40
7C420-65
7C421-65
7C420-65
7C421-65
7C425A-15
Product Line Cross Reference
ANALOGDEV
PREFIX:ADSP
SUFFIX: 883B
SUFFIX:D
SUFFIX:E
SUFFIX:F
SUFFIX:G
CYPRESS
PREFIX:CY
SUFFIX:B
SUFFIX:D
SUFFIX:L
SUFFIX:P
SUFFIX:G
ATMEL
PREFIX: AT
SUFFIX:D
SUFFIX:K
SUFFIX:L
SUFFIX:J
SUFFIX:P
SUFFIX:T
22V10
22VlO-15
27COlO-45C
27COlO-55C
27C010-70C
27CQ10-9OC
27COI0-120C
27COlO-lS0C
27C010-200C
27C512-70C
27C512-90C
27C512-120C
27C512-150C
27C5i2-200C
27C256R-70C
27C256R,,90C
27C256R -120C
27C256R -150C
27C256R - 200C
27HC256R-35C
27HC2S6R-45C
27HC2S6R -55C
27HC2S6R -70C
27HC256R -70M
27HC641-35C
27HC641-45C
27HC641-45M
27HC641-55C
27HC641-55M
27HC641-70C
27HC642-35C
27HC642-4SC
27HC642-45M
27HC642-55C
27HC642-55M
27HC642-70C
CYPRESS
PREFIX:CY
SUFFIX:W
SUFFIX:H
SUFFIX:Q
SUFFIX:J
SUFFIX:P
SUFFIX:Z
PALC22VlO
PALC22VlOB
27H010-45C
27HOlO-55C
27COlO-50C
27COI0-90C
27COlO-I20C
27COlO-15OC
27COI0-200C
27H512-70C
27C512-90C
27C512-12OC
27C512-150C
27C512-200C
27C256-70C
27C256-9OC+
27C256-120C+
27C256-150C+
27C256-200C+
27C256-35C
27C256-45C
27C256-55C
27C256-70C
27C256-70M
7C264-35C
7C264-45C
7C264-45M
7C264-55C
7C264-55M
7C264-70C
7C261-35C
7C261-45C
7C261-45M
7C261-55C
7C261-55M
7C261-55C
AUSTIN
SEMICONDUCTOR
PREFIX:MT
5CI608-25M
5C1608-30M
5C1608-35M
5C2561-25M
5C2S61-35M
5C2561-45M
5C2564-25M
5C2564-35M
CYPRESS
PREFIX:CY
7CI28A-25M
7CI28A-25M
7C128A-35M
7C197-25MB
7C197-35MB
7Cl97-45MB
7C194-25MB
7C194-35MB
AUSTIN
SEMICONDUCTOR
5C2564-45M
5C2568-25M
5C2568-35M
5C2568-45B
5C2568CW-25M
5C2568CW -35M
5C2568CW-45B
5C2568W - 25M
5C2568W-35M
5C2568W-45B
5C6401-20M
5C6401-25M
5C6401-30M
5C6401-35M
5C6404-20M
5C6404-25M
5C6404-30M
5C6404-35M
5C6408-20M
5C6408-25M
SC6408-30M
5C6408-35M
CYPRESS
7C194-45MB
7CI99-25MB
7C199-35MB
7C199-45MB
7C198-25MB
7C198-35MB
7C198-45MB
7C198-25MB
7C198-35MB
7C198-45MB
7C187A-20MB
7C187A-25MB
7C187A-25MB
7C187A-35MB
7C164A-20MB
7C164A-2SMB
7Cl64A-2SMB
7Cl64A-35MB
7C185A-20MB
7C185A-25M
7Cl85A-25MB
7C185A - 35MB
CATALYST
PREFIX: CAT
27HC256-S5L
27HC256-70L
27HC256-90L
27HC256-120L
27HC256l.,1LI - 55
27HC256l.,1LI -70
CYPRESS
PREFIX:CY
27C256-55C+
27C256-70C+
27C256-70C+
27C256-120C+
27C256-55CII
27C256 -70CII
DALLAS
PREFIX:DS
2009
2010
2011
CYPRESS
PREFIX:CY
7C421-25C
7C425-25C
7C429-25C
DENSEPAK
PRPFIX:DPS
6432-45C
6432-55C
CYPRESS
PREFIX:CYM
1830HD-45C
1830HD-55C
EDT
PREFIX: ED
8464C-45
8F32256C
8F3264C
8F8512CXXBC
8F8512LPXXB6C
8F8512PXXB6C
8M3264CXXC6B
8M3264CXXC6C
8M32256CXXC6B
8M32256CXXC6B
8M8512CXXM6C
CYPRESS
PREFIX:CYM
7C194-45
1841PZ
1831PZ
1465fC-XXC
1465LPD-XXC
1465LPD-XXC
M1830HD-XXMB
M1830HD-'XXC
M1840HD-XXMB
M1840HD-XXC
1464PD-XXC
FUJITSU
PREFIX:MB
PREFIX:MBM
SUFFIX:P
SUFFIX:M
SUFFIX:Z
CYPRESS
PREFIX:CY
PREFIX:CY
SUFFIX:F
SUFFIX:P
SUFFIX:D
FUJITSU
2147H-35
2147H-45
2149-45
27CI28 -170C
27Cl28 - 200C
27Cl28 - 250C
27C256A -150C
27C256A -170C
27C256A -200C
7132E
7132E-SK
7132E-W
7132H
7134H-SK
7132L-70
7132Y
7132Y-SK
7138E-55
7138E-W
7138H-45
7138Y-35
7144E
7144E-W
7144H
71A38-25
71A38-35
71C44-35
71C44-45
71C46-45
7226RA!S - 25
7232RA-25
7238RA-20
7238RA-20-W
7238RA-25
7238RA-25-W
8128-10
8128-15
8167-70W
8167A-55
8167A-70
8168-55
8171-55
8171-70
81C67-3S
81C67-45
81C67-55W
81C68-45
81C68-55W
81C71-45
81C71-55
81C74-25
81C74-35
81C74-45
81C75-25
81C75-35
81C78-45
81C78-55
81C81A-35
81C81A-45
81C84A-35
81C84A-4S
81C86-70
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
• = meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t = SOIConly
:j: = 32-pin LeC crosses to the 7C198M
•• = See Anstin Semiconductor for military products
1-28
CYPRESS
2147-35C
2147-45C
2149-45C
27CI28-150C+
27C128-200C+
27C128-200C+
27C256-150C+
27C256-150C+
27C256 - 200C +
7C282A-45C
7C281A-45C
7C282A-45M
7C282A-45C
7C281A-45C
7C281/2A -45C
7C282A-30C
7C281A-30C
7C291/2A - 50C
7C291/2A-50M
7C291/2A-3SC
7C291/2A - 35C
7C264-55C
7C264-55M
7C264-55C
7C291/2A-25C
7C291/2A-35C
7C264-35C
7C264-45C
7C254-4SC
7C225A-25C
7C235A-25C
7C245A-18C
7C245A-i8M
7C245A-25C
7C245A-25M
7C128A-55C
7C128A-55C
7C167A-45M
7C167A-45C
7C167A-45C
7C168A-45C
7C187-45C
7C187-45C
7C167A-35C
7C167A-45C
7C167A-45M
7C168A-45C
7C168A-45M+
7C187-45C
7C187-45C
7C164-25C
7Cl64-3SC+
7C164-45C
7C166-25C
7C166-3SC
7C186-45C
7C186-55C
7C197-35
7Cl97-45
7C194-35
7C194-45
7C192-45C+
Product Line Cross Reference
:'rcYPRESS
lDT
6198SA20B
6198SA25
6198SA25B
6198SA30B
61B298S12
61B298S15
61B298S20
61B298S15B
61B298S20B
7005S35
7805S35
7005S45B
7006S25
7006S35
7015S25
7015S35
7016S25
7016S35
7024S25
7024S35
7025S25
7025S35
7133S25
7133S35
7143S25
7143S35
71V256-15
71V256-20
71V256-25
71024-15
71024-20
71024-20
71024-25
71028-15
71028-20
71028-25
71256SA15
71256SA20
71256SA20B
71256SA25
71256SA30
71256SA30B
71256SA35
71256SA35B
71256SA45
71256SA45B
71257SA25
71257SA25B
71257SA35
71257SA35B
71257SA45
71257SA45B
71257SA55
71258SA25
71258SA25B
71258SA35
71258SA35B
71258SA45
71258SA45B
71281SA25
71281SA25B
71281SA35
CYPRESS
7C166-A20MB
7C166-25C
7CI66-A25MB
7CI66A-25MB
7C195-12C
7C195-15C
7C195-20C
7C195-15MB
7C195-20MB
7B144-25C
7B144-35C
7B144-35MB
7006S25C
7006S35C
7C145-25C
7C145-35C
7C016-25C
7C016-35C
7C024-25C
7C024-35C
7C025-25C
7C025-35C
7C133-25C
7C133-35C
7C143-25C
7C143-35C
7C1399-15C
7C1399-20C
7C1399-25C
7C109A-15C
7C109A-20C
7C109-20C
7C109-25C
7C106A-15C
7C106A-20C
7C106A-25C
7C199-15C
7C199-20C
7C199-20MB
7C198-25C
7C198-25C
7C198-25MB
7C198-35C
7C198-35MB
7CI98-45C,
7C198-45MB
7C197-25C
7C197-25MB
7C197-35C
7C197-35MB
7C197-45C
7C197-45MB
7C197-45C
7C194-25C
7C194-25MB
7C194-35C
7C194-35MB
7C194-45C
7C194-45MB
7C191-25C
7C191-25MB
7C191-35C
lDT
71281SA35B
71281SA45
71281SA45B
71282SA25
71282SA25B
71282SA35
71282SA35B
71282SA45
7130LA25
7130LA25J
7130LA30
7130LA30J
7130LA35
7130LA35B
7130LA35J
7130LA35LB
7130LA45
7130LA45B
7130LA45J
7130LA45LB
7130LA55
7130LA55B
7130LA55J
7130LA55L52B
7130LA70
7130LA70B
7130LA70J
7130LA70LB
7130LA90LB
7130SA25
7130SA25J
7130SA30
7130SA30J
7130SA35
7130SA35B
7130SA35J
7130SA35LB
7130SA45
7130SA45B
7130SA45J
7130SA45LB
7130SA55
7130SA55B
7130SA55J
7130SA55LB
7130SA70
7130SA70B
7130SA70J
7130SA70LB
7130SA90
7130SA90B
7130SA90J
7130SA90LB
7130SAl00
7130SAlOOB
7130SA100LB
71321LA25
71321LA30
71321LA35
71321LA35B
71321LA45
71321LA45B
CYPRESS
7C191-35MB
7C191-45C
7CI91-45MB
7CI92-25C
7C192-25MB
7C192-35C
7CI92-35MB
7C192-45C
7C130-25C
7C131-25JC
7C130-30C
7C131-30JC
7C130-35C
7C130-35MB
7C131-35JC
7C130-35LMB
7C130-45C
7C131-45MB
7C131-45JC
7C130-45LMB
7C130-55C
7C131-55MB
7C131-55JC
7C130-55LMB
7C130-55C
7C131-55MB
7C131-55JC
7C130-55LMB
7C131-55LMB
7C130-25C
7C131-25JC
7C130-25C
7C131-30JC
7C130-35C
7C130-35MB
7C131-35JC
7C131-35LMB
7C130-45C
7C130-45MB
7C131-45JC
7C131-45LMB
7C130-55C
7C130-55M
7C131-55JC
7C131-55LMB
7C130-55C
7C130-55MB
7C131-55JC
7C131-55LMB
7C130-55C
7C130-55MB
7C131-55JC
7C131-55LMB
7C130-55C
7C130-55MB
7C131-55LMB
7C136-25C
7C136-30C
7C136-35C
7C136-35MB
7C136-45C
7C136-45MB
lDT
71321LA55
71321LA55B
71321LA70
71321LA70B
71321LA90
71321LA90B
71321SA25
71321SA30
71321SA35
71321SA35B
71321SA45
71321SA45B
71321SA55
71321SA55B
71321SA70
71321SA70B
71321SA90
71321SA90B
713256-20
713256-25
7132LA25
7132LA30
7132LA35
7132LA35B
7132LA45
7132LA45B
7132LA55
7132LA55B
7132LA70
7132LA70B
7132LA90
7132LA90B
7132LAI00
7132LAI00B
7132LA120B
7132SA25
7132SA30
7132SA35
7132SA35B
7132SA45
7132SA45B
7132SA55
7132SA55B
7132SA70
7132SA70B
7132SA90
7132SA90B
7132SAlOO
7132SAlOOB
7132SA120B
71342S35
71342S35
71342S45B
7134S35
7134S35
7134S35J52
7134S35J52
7134S35L52
7134S35L52
7134S45B
7134S45L52B
7140LA25
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
, = meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t = SOIConly
:j: = 32-pin LCC crosses to the 7C198M
1-30
** == See Austin Semiconductor for military products
CYPRESS
7C136-55C
7C136-55MB
7C136-55C
7C136-55MB
7C136-55C
7C136-55MB
7C136-25C
7C136-30C
7C136-35C
7C136-35MB
7C136-45C
7C136-45MB
7C136-55C
7C136-55MB
7C136-55C
7C136-55MB
7C136-55C
7C136-55MB
7C1399-20C
7C1399-25C
7C132-25C
7C132-30C
7C132-35C
7C132-35MB
7C132-45C
7C132-45MB
7C132-55C'
7C132-55MB
7C132-55C'
7C132-55M*
7C132-55C'
7C132-55M*
7C132-55C'
7C132-55M*
7C132-55M*
7C132-25C
7C132-30C
7C132-35C
7C132-35MB
7C132-45C
7C132-45MB
7C132-55C+
7C132-55MB
7C132-55C+
7C132-55M+
7C132-55C+
7C132-55M+
7C132-55C+
7C132-55M+
7C132-55M+
7C1342-25C
7C1342-35C
7C1342-35MB
7B134-25C
7B134-35C
7B135-25JC
7B135-35JC
7B135-25LC
7B135-35LC
7B134-35MB
7B135-35LMB
7C140-25C
--
Product Line Cross Reference
......... rcYPRESS
IDT
nOOSA50T
nOOSA65T
nOOSA80T
7201LA15
7201LA20
7201LA20T
n01LA25
7201LA25T
7201LA30B
7201LA3OTB
n01LA35
7201LA35T
7201LA40B
7201LA40TB
n01LASO
n01LASOB
7201LA50T
7201LASOTB
n01LA65
n01LA65B
7201LA65T
7201LA65TB
n01LA80
7201LA80B
7201LA120
7201LA120B
n01SA15
7201SA20
n01SA2OT
n01SA25
7201SA25T
7201SA30B
7201SA30TB
7201SA35
7201SA35T
n01SA40B
7201SA40TB
7201SASO
n01SASOB
7201SA50T
7201SA50TB
n01SA65
7201SA65B
n01SA65T
7201SA65TB
7201SASO
7201SASOB
7201SA120
7201SA120B
7202LA15
7202LA20
7202LA20T
7202LA25
7202LA25T
7202LA30B
7202LA30TB
7202LA35
7202LA35T
7202LA40B
7202LA40TB
7202LA50
7202LASOB
CYPRESS
7C419-50
7C419-65
7C419-65
7C421-15
7C420-20C
7C421-20C
7C420-25C
7C421-25C
7C420-30MB
7C421-30MB
7C420-30C+
7C421-30C
7C420-40MB+
7C421-40MB
7C420-40C+
7C420-40MB+
7C421-40C
7C421-40MB
7C420-65C+
7C420-65MB+
7C421-65C
7C421-65MB
7C420-65C+
7C420-65MB+
7C420-65C+
7C420-65MB+
7C421-15
7C420-20C
7C421-20C
7C420-25C
7C421-25C
7C420-30MB
7C421-30MB
7C420-30C
7C421-30C
7C420-40MB
7C421-40MB
7C420-40C
7C420-40MB
7C421-40C
7C421-40MB
7C420-65C
7C420-65MB
7C421-65C
7C421-65MB
7C420-65C
7C420-65MB
7C420-65C
7C420-65MB
7C425-15
7C424-20C
7C425-20C
7C424-25C
7C425-25C
7C424-30MB
7C425-30MB
7C424-30C+
7C425-30C
7C424-40MB+
7C425-40MB
7C424-40C+
7C424-40MB+
IDT
7202LA5OT
7202LA50TB
7202LA65
7202LA65B
7202LA65T
7202LA65TB
n02LA80
7202LA80B
7202LA120
7202LA120B
7202SA15
7202SA20
7202SA2OT
7202SA25
7202SA25T
7202SA30B
7202SA30TB
7202SA35
n02SA35T
7202SA40B
7202SA40TB
7202SASO
7202SASOB
n02SASOT
n02SASOTB
7202SA65
7202SA65B
7202SA65T
n02SA65TB
7202SA80
7202SA80B
n02SA120
7202SA120B
7203L20
7203L20T
7203L25
7203L25B
7203L25T
7203L25TB
7203L30
7203L30T
7203L35B
7203L35TB
7203L40
7203L40T
7203LS5B
7203L55TB
7203L65
7203L65B
7203L65T
7203L65TB
7203L80
7203L80B
7203LSOT
7203LSOTB
7203S20
7203S20T
7203S25
7203S25B
7203S25T
7203S25TB
7203S30
CYPRESS
7C425-40C
7C425-40MB
7C424-65C+
7C424-65MB+
7C425-65C
7C425-65MB
7C424-65C+
7C424-65MB+
7C424-65C+
7C424-65MB+
7C425-15
7C424-20C
7C425-20C
7C424-25C
7C425-25C
7C424-30MB
7C425-30MB
7C424-30C
7C425-30C
7C424-40MB
7C425-40MB
7C424-40C
7C424-40MB
7C425-40C
7C425-40MB
7C424-65C
7C424-65MB
7C425-65C
7C425-65MB
7C424-65C
7C424-65MB
7C424-65C
7C424-65MB
7C428-20C
7C429-20C
7C428-25C
7C42S-25MB
7C429-25C
7C429-25MB
7C42S-30C
7C429-30C
7C428-30MB
7C429-30MB
7C428-40C
7C429-40C
7C428-40MB
7C429-40MB
7C428-65C
7C42S-65MB
7C429-65C
7C429-65MB
7C42S-65C
7C428-65MB
7C429-65C
7C429-65MB
7C428-20C
7C429-20C
7C428-25C
7C42S-25MB
7C429-25C
7C429-25MB
7C42S-30C
IDT
7203S30T
7203S35B
7203S35TB
7203S40
7203S40T
7203S55B
7203S55TB
7203S65
7203S65B
7203S65T
7203S65TB
7203S80
7203S80B
7203SS0T
7203S80TB
7204S25
7204S25T
7204S30
7204S30T
7204S35B
7204S35TB
7204S40
7204S40T
7204S55B
7204S55TB
7204S65
7204S65B
n04S65T
7204S65TB
7204S80B
7204S80TB
7205L20
n05LZ5
n05L30B
7205L30B
7205L35
7205LSO
7205LSOB
7206-15
7206-20
7206-25
72201L15
n201L25
n201L35
72205LB15
72205LB25
72205LB35
72211L15
72211L25
72211L35
72215LB15
72215LB25
72215LB35
72221L15
72221L25
72221L35
72225LB15
72225LB25
72225LB35
72231L15
72231L25
72231L35
Nole: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
=
=
=
=
meets all performance specs but may not meet IcC or ISB
meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
SOIConly
t
:j:
32-pin LCC crosses to the 7C19SM
** ;: See Austin Semiconductor for military products
1-32
+
*
CYPRESS
7C429-30C
7C428-30MB
7C429-30MB
7C428-40C
7C429-40C
7C428-40MB
7C429-40MB
7C428-65C
7C428-65MB
7C429-65C
7C429-65MB
7C428-65C
7C428-65MB
7C429-65C
7C429-65MB
7C432-25C
7C433-25C
7C432-30C
7C433-30C
7C432-30MB
7C433-30MB
7C432-40C
7C433-40C
7C432-40MB
7C433-40MB
7C432-65C
7C432-65MB
7C433-65C
7C433-65MB
7C432-65MB
7C433-65MB
7C460-15C
7C460-25C
7C460-15MB
7C460-25MB
7C460-25C
7C460-40C
7C460-40MB
7C462-15
7C462-20
7C462-25
7C4201-15
7C4201-25
7C4201-35
7C4205-15
7C4205-25
7C4205-35
7C4211-15
7C4211-25
7C4211-35
7C4215-15
7C4215-25
7C4215-35
7C4221-15
7C4221-25
7C4221-35
7C4225-15
7C4225-25
7C4225-35
7C4231-15
7C4231-25
7C4231-35
==:. rcYPRESS
MACRONIX
27C256-55C
27C256-70C
27C256-90C
27C256-12OC
27C256-150C
27C256-200C
27C512-45C
27C512-55C
27C512-7OC
27C512-9OC
27C512-120C
27C512-150C
27C512-ZOOC
CYPRESS
27C256-55C
27C256-70C
27C256-90C
27C256-120C
27C256-150C
27C256-200C
27H512-45C
27H512-55C
27H512-70C
27C512-90C
27C512-120C
27C512-150C
27C512-200C
MICROCmp
SUFFIX:J
SUFFIX:P
SUFFIX:L
27C64-12
27C64-15
27C64-17
27C64-20
27C64-25
27C128-12
27Cl28-15
27Cl28-17
27Cl28-20
27Cl28-25
27C256-IO
27C256-12
27C256-15
27C256-20
27C512-10
27C512-12
27C512-15
27C512-20
27C512-90
27HC256-55
27HC256-70
27HC256-90
CYPRESS
SUFFIX:W
SUFFIX:P
SUFFIX:J
27C64-120C
27C64-150C
27C64-150C
27C64-200C
27C64-200C
CY27Cl28-12OC+
CY27Cl28-150C+
CY27Cl28-150C+
CY27Cl28-200C+
CY27Cl28-200C+
CY27C256-90C+
CY27C256-12OC+
CY27C256-150C+
CY27C256-200C+
27C512-90C
27C512-12OC
27C512-15OC
27C512-200C
27C512-9OC
CY27C256-55C
CY27C256-70C
CY27C256-90C
MICRON"
PREFIX:Mf
58LC64K18B2
5ClOOl-15C
5ClOOl-20C
5ClOOl-25C
5CI008-20C
5ClO08-25C
5CI008-12C
5ClO08-15C
5CI008-20C
5C1601-15
5Cl601-20C
5C1601-25C
5C1601-30
5C1601-35C
5C1604-15
5C1604-20C
5C1604-25C
5C1604-30
5C1604-35C
5Cl605-15
CYPRESS
PREFIX:CY
7C1331
7CI07A-15C
7CI07A-20C
7CI07A-25C
7CI09-20C
7C109-25C
7CI09A-12C
7CI09A-15C
7CI09A-20C
7C167A-15C
7C167A-20C
7C167A-25C
7C167A-25C
7C167A-35C
7C168A-15C
7C168A-20C
7Cl68A-25C
7C168A-25C
7C168A-35C
7C170A-15C
Product Line Cross Reference
MICRON'·
5C1605-2OC
5C1605-25C
5C1605-30
5C1605-35C
5C1608-15
5C1608-20C
5C1608-25C
5C1608-35C
5C2561-12
5C2561-15
5C2561-20
5C2561-25
5C2561-30
5C2561-35
5C2561-45
5C2564-12
5C2564-15
5C2564-20
5C2564-25
5C2564-30
5C2564-35
5C2564-45
5C2565-12
5C2565-15
5C2565~20
5C2565-25
5C2565-30
5C2565-35
5C2565-45
5C2568-12
5C2568-15
5C2568-20
5C2568-25
5C2568-30
5C2568-35
5C2568-45
5C2889-20C
5C2889-25C
5C6404-15
50;404-20
5C6404-25
5C6404-30
5C6404-35
5C6405-15
5C6405-20C
5C6405-25C
5C6405-30
5C6405-35C
5C6408-15
5C6408-20C
5C6408-25C
5C6408-30
5C6408-35C
5LC2568-15
5LC2568-20C
5LC2568-25C
58LC64K18-9
58LC64K18-IO
85Cl664- 30C
85C8128-25
85C8128-35
85C8128-45C
CYPRESS
7C170A-20C
7C170A-25C
7C170A-25C
7C170A-35C
7C128A-15C
7Cl28A-20C
7C128A-25C
7Cl28A-35C
7C197-12
7C197-15
7C197-20
7C197-25C
7C197-25C
7C197-35C
7C197-45C
7C194-12
7C194-15
7C194-20
7C194-25C
7C194-25C
7C194-35C
7C194-45C
7C195-12
7C195-15
7C195-20
7C195-25C
7C195-25C
7C195-35C
7C195-45C
7C199-12
7C199-15
7C199-20
7C199-25C
7C199-25C
7C199-35C
7C199-45C
7C188-20C
7C188-25C
7C164-15C
7Cl64-20C
7C164-25C
7C164-25C
7C164-35C
7C166-15C
7C166-20C
7C166-25C
7C166-25C
7C166-35C
7C185-15C
7Cl85-20C
7C185-25C
7C185-25C
7C185-35C
7C1399-15
7C1399-20C
7C1399-25C
7ClO31-8.5
7CI031-10
1620HD-30C
M1420PD-25C
M1420PD-35C
1423PD-45C
MICRON'·
8S1632Z
8S1632M
8S6432Z
8S6432M
8S25632Z
8S25632M
4S12832Z
4S12832M
CYPRESS
M1821PZ
M1821PM
M1831PZ
M1831PM
M1841PZ
M1841PM
M1836PZ
M1836PM
MITSUBISm
PREFIX:M5L
PREFIX:M5M
SUFFIX:AP
SUFFIX:FP
SUFFIX:K
SUFFIX:P
21C67P-35
21C67P-45
21C67P-55
21C68P-35
21C68P-45
21C68P-55
27C256-85
27C256-100
27C256-120
27C256-150
27C256-170
5165L-70
5165L-l00
5165L-120
5165P-70
5165P-l00
5165P-120
5178P-45
5178P-55
5187P-25
5187P-35
5187P-45
5187P-55
5188P-25
5188P-35
5188P-45
5188P-55
5257J-35
5257J-45
5257P-35
5257P-45
5258J-45
5258P-35
5258P-45
52B79P/J
CYPRESS
PREFIX:CY
PREFIX:CY
SUFFIX:L
SUFFIX:F
SUFFIX: 0
SUFFIX:P
7C167A-35C
7C167A-45C
7C167A-45C
7C168A-35C
7C168A-45C
7C168A-45C
27C256-70C+
27C256-90C+
27C256-120C+
27C256-150C+
27C256-150C+
7C186-55C+
7C186-55C+
7C186-55C+
7C186-55C+
7C186-55C+
7C186-55C+
7C186-45C+
7C186-55C+
7C187-25C
7C187-35C
7C187-45C
7C187-45C
7Cl64-25C
7Cl64-35C
7Cl64-45C
7C164-45C
7C197-35C
7C197-45C
7C197-35C
7C197-45C
7C194-45C
7C194-35C
7C194-45C
7C188
MMl/AMD
CYPRESS
SUFFIX:B
SUFFIX:F
SUFFIX: 0
SUFFIX:L
SUFFIX:P
SUFFIX:B
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-35C
PLD20GlO-40M
SUFFIX: 883B
SUFFIX:F
SUFFIX:J
SUFFIX:L
SUFFIX:N
SUFFIX: SHRP
PALl2LI0C
PAL12L10M
PAL14L8C
PAL14L8M
Note: Unless otherwise noted, product meets all performance specs and is within lO rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
• = meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t = SOIConly
:j: = n-pin LCC crosses to the 7C198M
•• = See Austin Semiconductor for military products
1-34
Product Line Cross Reference
NATIONAL
27C01O-120C
27C01O-150C
27C01O-200C
27C64-1OOC
27C64-120C
27C64-150C
27C64-2OOC
27CI28-12~
27C128-15C
27CI28-20C
27C256-100
27C256-120
27C256-150
27C256-200
27C512-12OC
27C512-15OC
27C512-200C
27P0l0-70C
27POI0-90C
27POI0-I00C
77LS181
77S181
77S181A
77S281
77S281A
77S401
77S401A
77S402
77S402A
77SR181
77SR476
77SR476B
85S07A
87LS181
87S181
87S281
87S281A
87S401
87S401A
87S402
87S402A
87SR181
87SR476
87SR476B
93LA22A
CZ7C53-55
CZ7C53-70
GALZ2V1O-15C
GAL22VI0-2OI
GAL22VlO-20M
GAL22VlO-25C
GAL22V1O-30I
GALZ2VI0-30M
NMF512X9-15
NMF512X9-25
NMF2048X9-20
NMF4096X9A-25
PALI64A2M
PALI6LSA2C
PALI6LSA2M
PAL16LSAC
PAL16LSAM
CYPRESS
27C01O-120C
27C01O-150C
27COI0-200C
27C64-90C
27C64-120C
27C64-150C
27C64-200C
27CI28-120C+
27CI28-150C+
27C128-200C+
27C256-90C+
27C256-120C+
27C256-150C+
27C256-200C+
27C512-120C
27C512-150C
27C512-200C'
27C01O-70C
27COlO-90C
27COlO-90C
7C282A-45M
7C282A-45M
7C282A-45M
7C281A-45M
7C281A-45M
7C401-1OM
7C401-1OM
7C402-10M
7C402-1OM
7C235A-40M
7C225A-40M7C225A-40M7CI28-45C+
7C282A-45C
7C282A-45C
7C281A-45C
7C281A-45C
7C40l-lOC
7C401-15C
7C402-1OC
7C402-15C
7C235-40C
7CZ25A-40C
7CZ25A-3OC
7C122-C
27C256-55C
27C256-70C
PALC22V1OD-15C
PALC22VlOD-15I
PALC22VI0D-15M
PALC22VI0D-25C
PALC22VI0D-25I
PALC22VI0D-25M
7C421A-15
7C421-25
7C429-20
7C433-25
PALC16R4-40M
PALCI6LS-35C
PALCI6LS-40M
PALCI6LS-25C
PALCI6LS-30M
NATIONAL
PAL16LSB2C
PAL16LSB2M
PALI6LSB4C
PALI6LSB4M
PAL16LSBM
PAL16LSC
PAL16LSM
PALI6R4A2C
PAL16R4AC
PAL16R4AM
PAL16R4B2C
PAL16R4B2M
PAL16R4B4C
PAL16R4B4M
PAL16R4BM
PAL16R4C
PAL16R4M
PALI6R6A2C
PALI6R6A2M
PAL16R6AC
PAL16R6AM
PAL16R6B2C
PAL16R6B2M
PAL16R6B4C
PAL16R6B4M
PAL16R6BM
PALI6R6C
PAL16R6M
PAL16R8A2C
PALI6R8A2M
PAL16R8AC
PAL16R8AM
PAL16R8B2C
PAL16R8B2M
PALI6R8B4C
PALI6R8B4M
PAL16R8BM
PAL16R8C
PAL16R8M
PAL20L2C
PAL20LSAC
PALZOLSAM
PALZOLSBC
PALZOLSBM
PAL20LSC
PAL20LSM
PALZOLlOB2C
PALZOLlOB2M
PALZOLlOC
PALZOLlOM
PAL20R4AC
PAL20R4AM
PAL20R4BC
PALZOR4BM
PALZOR4C
PALZOR4M
PALZOR6AC
PALZOR6AM
PAL20R6BC
PALZOR6BM
PALZOR6C
PALZOR6M
CYPRESS
PALCI6LS-25C
PALCI6LS-30M
PALCI6LSL-35C
PALCI6LS-40M
PALCI6LS-20M
PALCI6LS-35C
PALCI6LS-40M
PALCI6R4-35C
PALCI6R4-25C
PALCI6R4-30M
PALCI6R4-25C
PALCI6R4-30M
PALCI6R4L-35C
PALC16R4-40M
PALC16R4-20M
PALCI6R4-35C
PALC16R4-40M
PALCI6R6-35C
PALC16R6-40M
PALCI6R6-25C
PALCI6R6-30M
PALCI6R6-25C
PALC16R6-30M
PALCI6R6L- 35C
PALCI6R6-40M
PALC16R6-20M
PALC16R6-35C
PALCI6R6-40M
PALC16R8-35C
PALCI6R8-40M
PALCI6R8-25C
PALCI6R8-30M
PALCI6R8-25C
PALCI6R8-30M
PALCI6R8L-35C
PALCI6R8-40M
PALCI6R8-20M
PALCI6R8-35C
PALCI6R8-40M
PLDCZOG1O-35C
PLDCZOGlO-25C
PLDCZOGlO-30M
PLDCZOG1O-25C
PLDCZOGlO-30M
PLDCZOGlO-35C
PLDCZOGlO-40M
PLDC2OGI0-25C
PLDCZOGI0-30M
PLDC20GlO-35C
PLDCZOGlO-40M
PLDCZOGlO-25C
PLDCZOG1O-30M
PLDC2OG1O-25C
PLDCZOGlO-30M
PLDCZOGlO-35C
PLDCZOGlO-40M
PLDCZOGlO-25C
PLDCZOGlO-30M
PLDC20GlO-25C
PLDC20GI0-30M
PLDC20GlO- 35C
PLDC20GlO-40M
NATIONAL
PALZOR8AC
PALZOR8AM
PALZOR8BC
PALZOR8BM
PALZOR8C
PALZOR8M
CYPRESS
PLDCZOGlO-25C
PLDCZOGlO-30M
PLDCZOGlO-25C
PLDCZOGlO-30M
PLDC20G1O-35C
PLDC20GlO-40M
NEe
PREFIX:uPD
SUFFIX:C
SUFFIX:D
SUFFIX:K
SUFFIX:L
2147A
2149
2149
2167-2
27HC65-25
27HC65-35
27HC65-45
4311-45
4311-55
43254C-35
43254C-45
4361
4362
4363
43259-20
43259-25
431001-20
431001-25
431004-20
431004-25
431008-15
431008-20
431008-20
CYPRESS
PREFIX:CY
SUFFIX:P
SUFFIX:D
SUFFIX:L
SUFFIX:F
7C147-C
2149-C
7C149-C
7C167A-C
7C263/4-25C
7C263/4-35C
7C263/4-45C
7C167A-45C
7C167A-45C
7C194-35
7C194-45
7C187-C
7C164-C
7C166-C
7CI88-20
7CI88-25
7C107A-20C
7C107A-25C
7C106A-20C
7C106A-25C
7C109A-15
7C109A-20
7CI09-20
OKI
PREFIX:MSM
27128A-12C
27128A-15C
27128A-20C
27256-100
27256-120
27256-150
27256-200
27256H-55
27256H-70
CYPRESS
PREFIX:CY
27CI28-120C+
27CI28-150C+
27CI28-200C+
27C256-90C+
27C256-120C+
27C256-150C+
27C256-200C+
27C256-55C
27C256-7OC
PARADIGM
PREFIX:PDM
41251L
41251LB
41251S
41251SB
41252L
41252LB
41252S
41252SB
41256L
41256LB
41256S
41256SB
CYPRESS
PREFIX:CY
7CI9I-C
7CI9I-MB*
7CI9I-C
7C191-MB
7C192-C
7CI92-MB*
7C192-C
7C192-MB
7C199/8-C*
7CI99/8-MB*
7CI99/8-C
7CI99/8-MB
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
* = meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t = SOIConIy
:j: = 32-pin LCC crosses to the 7C198M
• * = See Austin Senticonductor for military products
1-36
Product Line Cross Reference
:zircYPRESS
SAMSUNG
PREFIX:KM
ISVS7-8
61257A-25
61257A-35
61257A-45
64257A-25
64257A-35
64257A-45
64258B-15
64258B-20
64259B-15
64259B-20
641001-20
681001-20
681002-15
681002-20
68257-12
68257-15
718B514-8
75COlA-15
75COIA-20
75COlA-25
75COlA-35
75COIA-50
75COIA-80
75COlAP-20
75COlAP-25
75COIAP-35
75COlAP-50
75COIAP-80
75C02A-15
75C02A-20
75C02A-25
75C02A-35
75C02A-50
75C02A-80
75C02AP-20
75C02AP-25
75C02AP-35
75C02AP-50
75C02AP-80
75C03A-15
75C03A-20
75C03A-25
75C03A-35
75C03A-50
75C03A-80
75C03AP-20
75C03AP-25
75C03AP-35
75C03AP-50
75C03AP-80
75C102A-20
75C102A-25
75C102A-35
75C102A-80
CYPRESS
PREFIX:CY
7CI031-8.5
7C197-25C
7C197-35C
7C197-45C
7C194-25C
7C194-35C
7C194-45C
7C194-15C
7C194-20C
7C196-15C
7C196-20C
7C106A-'20C
7C109A-20C
7C1009-15C
7CI009-20C
7C199-12C
7C199-15C
7C178-8.5
7C421-15
7C421-20C
7C421-25C
7C421-30C
7C421-40C
7C421-65C
7C420-20C
7C420-25C
7C420-35C
7C420-50C
7C420-80C
7C425-15
7C425-20C
7C425-25C
7C425-30C
7C425-40C
7C425-65C
7C424-20C
7C424-25C
7C424-30C
7C424-40C
7C424-65C
7C429-15C
7C429-20C
7C429-25C
7C429-30C
7C429-40C
7C429-65C
7C428-20C
7C428-25C
7C428-30C
7C428-40C
7C428-65C
7C425-20C
7C425-25C
7C425-25C
7C425-65C
SGS·THOMSON
PREFIX:M
SUFFIX:Fl
SUFFIX:Bl
SUFFIX:Cl
SUFFIX:Nl
CYPRESS
PREFIX:CY
SUFFIX:W
SUFFIX:P
SUFFIX:J
SUFFIX:Z
SGS·THOMSON
27256-150
27256-170
27256-200
27C64A-12
27C64A-15
27C64A-20
27C64A-25
27C64A-30
27C128A-12
27CI28A-15
27CI28A-20
27C256B-80
27C256B-90
27C256B-I00
27C256B-120
27C512-10
27C512-12
27C512-15
27C512-20
27C512-25
27C512-80
27C512-90
27C1001-60X
27C1001-70
27Cl001-90
27Cl00I-120
27Cl001-150
27CI001-200
SHARP
PREFIX:LH
52251-35
52251-45
52252-35
52252-45
522540-25
522540-35
522540-45
52259
54S1-15
5481-25
5481-35
5491-15
5491-25
5491-35
5496-20
5496-35
5496-50
54960-15
54960-20
54960-35
54960-50
5497-20
5497-35
5497-50
54970-15
54970-20
54970-35
54970-50
CYPRESS
27C256-150C
27C256-150C
27C256-200C
27C64-120C
27C64-150C
27C64-200C
27C64-200C
27C64-200C
27CI28-120C+
27CI28-150C+
27CI28- 200C+
27C256-70C+
27C256-90C+
27C256-90C+
27C256-120C+
27C512-90C
27C512-120C
27C512-150C
27C512-200C
27C512-200C
27H512-70C
27C512-90C
27HOlO-55C
27COlO-70C
27COlO-90C
27COlO-120C
27COlO-150C
27COlO':'200C
CYPRESS
PREFIX:CY
7C197-35C
7C197-45C
7C194-35C
7C194-45C
7CI99-25C
7C199-35C
7C199-45C
7C188
7C408A-15C
7C408A-25C
7C40SA-35C
7C409A-15C
7C409A-25C
7C409A-35C
7C420-20C
7C420-30C
7C420-40C
7C421A-15
7C421-20C
7C421-30C
7C421-40C
7C424-20C
7C424-30C
7C424-40C
7C425A-15
7C425-20C
7C425-30C
7C425-40C
SONY
PREFIX:CXK
51256P-35
51256P-45
55464-20
55464-25
58258A-15
58258A-20
58258A-25
59288-20C
59288-25C
CYPRESS
PREFIX:CY
7C197-35
7C197-45
7C194-20C
7C194-25C
7C199-15C
7C199-20C
7C199-25C
7C188-20C
7C18S-25C
TI
CYPRESS
PREFIX:CY
SUFFIX:P
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
SUFFIX:J
SUFFIX:W
SUFFIX:P
SUFFIX:Z
SUFFIX:P
PALC22VI0-25C
PALC22VI0-30M
27COlO-120C
27COlO-150C
27COlO- 200C
27C128-120
27C512-90C
27C512-120C
27C512-150C
27C512-200C
27C128-150
27C128-200
27C256-90C+
27C256-120C+
27C256-150C+
27C256-150C+
27C256-200C+
27PCOI0-120C
27PCOI0-150C
27PCOI0-200C
27C256-90C+
27C256-120C+
27C256-150C+
27C256-150C+
27C256-200C+
27PC512-90C
27PC512-120C
27PC512-150C
27PC512 - 200C
PALI6L8-5C
PAL16L8-7C
PALI6L8-7M
PALI6L8-7C
PAL16LS-lOM
PALI6LS-I0M
PAL16L8-7C
PALI6L8-lOM
PALC16L8-20M
PREFIX:JBP
PREFIX: PAL
PREFIX:SM
PREFIX:SMJ
PREFIX:SN
PREFIX:TBP
PREFIX:TIB
PREFIX:TMS
SUFFIX:FM
SUFFIX:J
SUFFIX:N
SUFFIX: 00
SUFFIX:N
22VlOAC
22VIOAM
27COI0-120
27COI0-150
27COlO-200
27C12S-12
27C512-100
27C512-120
27C512-150
27C512-200
27C/PCI28-15
27C/PCI2S- 20
27C256-1O
27C256-12
27C256-15
27C256-17
27C256-20
27PCOlO-120
27PCOlO-150
27PCOlO - 200
27PC256-10
27PC256-12
27PC256-15
27PC256-17
27PC256-20
27PC512-100
27PC512-120
27PC512-150
27PC512-200
PALI6L8-5C
PAL16L8-7C
PALI6LS-7M
PALI6L8-10C
PAL16L8-lOM
PAL16L8-12M
PAL16L8-15C
PAL16L8-15M
PALI6L8-20M
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ ~ meets all performance specs but may not meet Icc or ISB
* - meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
SOIConly
t
:j:
32·pin LCC crosses to the 7C198M
1-38
** = See Austin Semiconductor for military products
~
~
_!rcYPRESS
WSI
57C64F-55
57C51C-45
57C51C-45M
57C51C-55
57C51C-55M
57C51C-70
57C51C-70M
57C71C-35
57C71C-45
57C71C-55
57C71C-55M
57C71C-70
57C71C-70M
57C128F - 55C
57C128F -70C
57Cl28FB-45
57C128FB-55
57C128FB-70
57C191B-35
57C191B-35M
57C191B-45
57C191B-45M
57C19IB-50M
57C19IB-55
57C19IB-55M
57C191C-25
57C191C-35
57C191C-45
57C191C-45M
57C191C-55
57C191C-55M
57C256F-35
57C256F-45
57C256F-55
57C256F-55M
57C256F-70
57C256F -70M
57C256F-90
57C291B-35
57C291B-35M
57C29IB-45
57C291B-45M
57C291B-50M
57C291B-55
57C29IB-55M
57C291C-25
57C291C-35
57C291C-45
57C291C-45M
57C291C-55
57C291C-55M
Product Line Cross Reference
CYPRESS
7C266-55C
7C251/4-45C
7C251/4-45M
7C251/4-55C
7C251/4-55M
7C251/4-55M
7C251/4-55M
7C271A-35C
7C271A-45C
7C271A-55C
7C271A-55M
7C271A-55M
7C271A-55M
27Cl28-55C+
27Cl28-70C+
27Cl28-45C
27Cl28-55C
27Cl28-70C
7C292A-35C
7C292A-35M
7C292A-35C
7C292A-35M
7C292A-50M
7C292A-5OC
7C292A-50M
7C292A-25C
7C292A-35C
7C292A-35C
7C292A-35M
7C292A-50C
7C292A-50M
27H256-35C
27C256-45C+
27C256-55C+
27C256-55M
27C256-70C+
27C256-70M
27C256-90C+
7C291A-35C
7C291A-35M
7C291A-35C
7C291A-35M
7C291A-50M
7C291A-50C
7C291A-50M
7C291A-25C
7C291A-35C
7C291A-35C
7C291A-35M
7C291A-50C
7C291A-50M
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
• = meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t = SOIConly
:j: = 32-pin LCC crosses to the 7C198M
•• = See Austin Semiconductor for military products
1-40
=:aTcYPRESS
Product Line Cross Reference
FCT Commercial Cross Reference (continued)
CYPRESS
CY74FCT52C
CY74FCT2240A
CY74FCT2244A
CY74FCT2245A
CY74FCT240A
CY74FCT244A
CY74FCT245A
CY74FCT273A
CY74FCT373A
CY74FCT374A
CY74FCT377A
CY74FCT540A
CY74FCT541A
CY74FCT543A
CY74FCT573A
CY74FCT574A
CY74FCT646A
CY74FCT646C
CY74FCT652A
CY74FCT652C
CY74FCT821C,
CY74FCT827C
CY74FCT841C
CYBUS3384
Package
Plastic DIP
SOlC
11
74ABT2952A
SN74ABT2240
SN74ABT2244
SN74ABT2245
SN74ABT240
SN74ABT244
SN74ABT245
SN74ABT273
SN74ABT373
SN74ABT374
SN74ABT377
SN74ABT540
SN74ABT541
SN74ABT543
SN74ABT573
SN74ABT574
SN74ABT646
SN74ABT646A
SN74ABT652
SN74ABT652A
SN74ABT821
SN74ABT827
SN74ABT841
SN74CBT3384
Code
P
SO
N
DW
1-42
~YPRESS
Product Line Cross Reference
Commercial Cross Reference
CYPRESS
CY74FCT16240
CY74FCT16244
CY74FCT16245
CY74FCT16373
CY74FCT16374
CY74FCTl6444
CY74FCTl6445
CY74FCT16500
CY74FCT16501
CY74FCf16543
CY74FCf16646
CY74FCf16652
CY74FCT16823
CY74FCf16827
CY74FCf16841
CY74FCf16952
CY74FCf162240
CY74FCf162244
CY74FCf162245
CY74FCf162373
CY74FCT162374
CY74FCT162444
CY74FCT162445
CY74FCT162500
CY74FCf162501
CY74FCf162543
CY74FCf162646
CY74FCf162652
CY74FCf162823
CY74FCT162827
CY74FCT162841
CY74FCT162952
CY74FCT162H952
CY74FCT162H501
CY74FCT162H244
CY74FCf162H245
CY74FCf162H373
Package
SSOP
TSSOP
Std,A,C
Std,A,C
Std,A,C
Std,A,C
Std,A,C
Std,A,C
Std,A,C
A,C
A,C
Std,A,C
Std,A,C
Std,A,C
A,B,C
A,B,C
A,B,C
A,B,C
Std,A,C
Std,A,C
Std,A,C
Std,A,C
Std,A,C
Std,A,C
Std,A,C
A,C
A,C
Std,A,C
Std,A,C
Std,A,C
A,B,C
A,1l,C
A,B,C
A,B,C
A,B,C
A,C
Std,A,C
Std,A,C
Std,A,C
Code
PV
PA
CYPRESS
CY74FCT16240CT
CY74FCT16244CT
CY74FCT16245CT
CY74FCT16373Cf
CY74FCT16374CT
CY74FCf16500CT
CY74FCf16543CT
CY74FCf162240CT
CY74FCT162244CT
CY74FCT162245Cf
CY74FCT162373
CY74FCT162374
CY74FCf162500CT
Package
SSOP
TSSOP
IDT
IDTI4FCT16240
IDTI4FCT16244
IDTI4FCT16245
IDTI4FCT16373
IDTI4FCf16374
Std,A,C,E
Std,A,C,E
Std,A,C,E
Std,A,C,E
Std,A,C,E
PERICOM
P174FCT16240
PI74FCT16244
P174FCT16245
PI74FCT16373
PI74FCT16374
Std,A,C,D
Std,A,C,D
Std,A,C,D
Std,A,C,D
Std,A,C,D
IDTI4FCf16500
IDTI4FCf16501
IDTI4FCf16543
IDTI4FCTl6646
IDTI4FCT16652
IDT74FCT16823
IDT74FCT16827
IDT74FCf16841
IDT74FCf16952
IDT74FCf162240
IDT74FCT162244
IDT74FCf162245
IDT74FCT162373
IDT74FCT162374
A,C,E
A,C,E
Std,A,C,E
Std,A,C,E
Std,A,C,E
A,B,C,E
A,B,C,E
A,B,C,E
A,B,C,E
Std,A,C,E
Std,A,C,E
Std,A,C,E
Std,A,C,E
Std,A,C,E
PI74FCT16500
PI74FCT16501
PI74FCT16543
PI74FCT16646
PI74FCT16652
P174FCT16823
PI74FCT16827
PI74FCT16841
PI74FCT16952
P174FCT162240
PI74FCT162244
PI74FCT162245
PI74FCT162373
PI74FCT162374
A,C,D
A,C,D
Std,A,C,D
Std,A,C,D
Std,A,C,D
A,B,C
A,B,C
A,B,C
A,B,C,D
Std,A,C,D
Std,A,C,D
Std,A,C,D
Std,A,C,D
Std,A,C,D
IDTI4FCT162500
IDTI4FCT162501
IDTI4FCT162543
IDTI4FCT162646
IDTI4FCT162652
IDTI4FCT162823
IDTI4FCT162827
IDTI4FCT162841
IDTI4FCT162952
IDTI4FCT162H952
IDTI4FCT162H501
IDTI4FCT162H244
IDTI4FCf162H245
IDTI4FCT162H373
A,C,E
A,C,E
Std,A,C,E
Std,A,C,E
Std,A,C,E
A,B,C,E
A,B,C,E
A,B,C,E
A,B,C,E
A,B,C,E
A,C,E
Std,A,C,E
Std,A,C,E
Std,A,C,E
PI74FCT162500
P174FCT162501
PI74FCT162543
PI74FCT162646
PI74FCT162652
PI74FCT16H823
PI74FCT162827
P174FCT162841
PI74FCf162952
A,C,D
A,C,D
Std,A,C,D
Std,A,C,D
Std,A,C,D
A,B,C
A,B,C
A,B,C
A,B,C,D
Package
SSOP
TSSOP
Code
PV
PA
TEXAS INSTRUMENTS
SN74ABT16240
SN74ABT16244A
SN74ABT16245
SN74ABT16373A
SN74ABT16374A
SN74ABT16500B
SN74ABT16543B
SN74ABT162240
SN74ABT162244
SN74ABT162245
Package
SSOP
TSSOP
Code
PV
PA
PIDLLIPS
74ABT16244
74ABT16245
74ABT16373
74ABT16374
74ABT16543
SN74ABT162500
Code
PV
PA
Package
SSOP
TSSOP
Code
DL
DDG
Package
SSOP
TSSOP
Document # 38-00238-C
1-44
Code
PV
Section Contents
Static RAMs (Random Access Memory)
Page Number
Device
Description
CY6264
CY7C101A
CY7CI02A
CY7CI06A
CY7C107A
CY7CI09
CY7tl09A
CY7Cl23
CY7Cl28A
CY7Cl48
CY7C149
CY7C150
CY7C161
CY7C162
CY7C161A
CY7C162A
CY7C164
CY7C166
CY7C164A
CY7C166A
CY7t167A
CY7C168A
CY7ci69A
CY7C170A
CY7CI71A
CY7C172A
CY7C178
CY7C179
CY7C182
CY7C185
CY7C185A
CY7C187
CY7C187A
CY7C188
CY7C191
CY7C192
CY7C193
CY7C194
CY7C195
CY7C196
CY7C197
CY7C199
CY7CI001
CY7Cl002
CY7Cl006
CY7C1007
CY7C1009
CY7C1014
CY7C1016
CY7C1019
CY7C1021
8Kx8StaticRAM ............................................................ 2-1
256K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-7
256Kx4 Static RAM with SeparateI/O ........................................... 2-7
256K x 4 Static RAM ......................................................... 2-15
1M x 1 Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-23
128K x 8 Static RAM ......................................................... 2- 30
128Kx 8 Static RAM ......................................................... 2-36
256x4StaticRAM ........................................................... 2-44
2Kx8StaticRAM ........................................................... 2-50
lKx4StaticRAM ........................................................... 2-57
lK x 4 Static RAM ........................................................... 2-57
lKx 4 Static RAM .................................................... ; ...... 2-64
16K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-72
16K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-72
16K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-80
16Kx 4 Static RAM with Separate I/O ........................................... 2-80
16K x 4 Static RAM .......................................................... 2-88
16Kx 4 Static RAM .......................................................... 2-88
16K x 4 Static RAM .......................................................... 2-95
16Kx 4 Static RAM .......................................................... 2-95
16Kx 1 Static RAM ......................................................... 2-103
4Kx 4 Static RAM .......................................................... 2-110
4Kx4StaticRAM .......................................................... 2-110
4K x 4 Static RAM .......................................................... 2-117
4K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-122
4K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-122
32Kx 18 Synchronous Cache RAM ............................................ 2-130
32K x 18 Synchronous Cache RAM ............................................ 2-130
8Kx9 Static RAM .......................................................... 2-142
8Kx8StaticRAM .......................................................... 2-147
8K x 8 Static RAM .......................................................... 2-155
64Kx 1 Static RAM
2-163
64Kx 1 Static RAM ........................................................ . 2-170
32Kx 9 Static RAM ........................................................ . 2-178
64K x 4 Static RAM with Separate I/O ......................................... . 2-185
64K x 4 Static RAM with Separate I/O ......................................... . 2-185
32K x 8 Synchronous SRAM ................................................. . 2-193
64Kx4StaticRAM ........................................................ . 2-199
64Kx4StaticRAM ........................................................ . 2-199
64Kx 4 Static RAM ........................................................ . 2-199
256K x 1 Static RAM ....................................................... . 2-208
32Kx8StaticRAM ......................................................... 2-216
256K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-227
256Kx4 Static RAM with Separate I/O ......................................... 2-227
256K x 4 Static RAM ........................................................ 2- ~4
IMxlStaticRAM .......................................................... 2-241
128Kx 8 Static RAM ........................................................ 2-247
256K x 4 Static RAM ....................................................... . 2-254
2-255
256K x 4 Static RAM
2-256
128K x 8 Static RAM
2-257
64K x 16 Static RAM
~YPRESS
PRELIMINARY
CY6264
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature .................. -65°C to +150°C
Ambient Thmperature with
Power Applied ....................... -55° C to + 125° C
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ....................... > 2001V
(per MIL-Sl'D-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Supply Voltage to Ground Potential ........ -0.5V to + 7.0V
Range
Commercial
DC Voltage APBlied to Outputs
in High Z State 1] .• ; ..•••...•..• , •.•••••• -O.5V to + 7.0V
DC Input Voltagel1] ..................... -O.5V to +7.0V
Vee
5V ± 10%
Electrical Characteristics Over the Operating Range
los
-300
rnA
ICC
100
rnA
ISB1
20
rnA
ISB2
15
Shaded area contains advanced information.
Capacitance[3]
Parameter
CIN
COuT
Test Conditions
Description
Input Capacitance
Output Capacitance
TA = 25°C, f
Vee = 5.0V
Notes:
1. Minimum voltage is equal to - 3.0V for pulse durations less than 30 ns.
2. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
3.
Max.
7
7
= 1 MHz,
Unit
pF
pF
Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
5V o-___
Rl_48"""'10;.:,
SV
30pF
INCLUDING
JIG AND
SCOPE
SpF
R2
= =
Rl4810
OUTPUT~
OUTPUTo----t---+
2SS0
, (a) Normal Load
3.0V
GND
R2
INCLUDING
JIG AND,
SCOPE (b)
= =
2S50
SSM
90%
0%
SSM
Hlgb-ZLoad
CY6264-3
Equivalent to:
::iL 1e::
ALL INPUT PULSES
THEVENIN EQUIVALENT
OUTPUT "'O_ _ _'M~"".7_0_ _...
o 1.73V
2-2
CY6264-4
41z~YPRESS
Switching Waveforms
Read Cycle No. 1[8,9]
ADDRESS:
PRELIMINARY
€
DATA OUT
*-
IRC
----~
1
lAA
CY6264
PREVIOUS DATA V : ; J x X ) ( ) ( ) K - - - - - - - - D - A - T A - V - A - L - I D - - - - - -
---------------~C~Y~-5
Read Cycle No. 2[10,11]
Ci:1
IRC
~"
/'{:
~"
~~
lACE
.kI
~
IOOE
I--ILZOE-
DATA OUT
HIGH IMPEDANCE
==f
ILZCE
-Ipu
VCC
SUPPLY _ _ _ _ _ _ _
CURRENT
-
.,"
'~~
. . - IHZCE '
DATA VALID
HIGH
IMPEDAN CE
/
_Ipo
~ ICC
50%
50%,
IS8
CY6264-6
Write Cycle No.1 (WE Controlled)[9, 11]
~-----------------------Iwc----------------------~
ADDRESS
i-------------------ISCE1 --------------------<~ ,.,..,~,.,.~.,..,..,..,..."..,.,~,..
Ci:1
~~~---------------Lp~~~~~~~
i-----------IsCE2 ------------------~
~-----------------~w--------------------~....>------- IpWE ---------.I
,-__-------------
1 + - - - ISA - - - - - - - . j
WE----------~----~~~
Iso
DATA IN
DATAIN VALID
IHZWE
-----I
ILZWE
--I
-------------------~--'~LI----H-IG-H--IM-P-E-DA-N-C-E----~Iv~~_~-_-_-_-_-_-_,_
DATA 1/0 _ _ _ _ _ _ _ _ _
DATA UNDEFINED
~
CY6264-7
Notes:
8. Device is continuously selected. DE, CE = VII,. CE2 = VIR.
9. Address valid prior to or coincident with CE transition LOW.
10. WE is HIGH for read cycle.
11. DataI/O is High Z if DE = VIR, CEI
2-4
= VIR, or WE = VIL.
'".
PRELIMINARY
QYPRESS
CY6264
1YPical DC and AC Characteriiltics (continued)
TYPICAL ACCESS TIME CHANGE
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
'vs. OUTPUT LOADING
3.0
.,
2 .5
0
..!!-
fa
i
1.25
30.0
2.0
.s
20.0
1.5
~
15.0
:::
~ 1.0
0.5
0.0
0.0
./
..
1.0
2.0
3.0
~
/
4.0
/
V
V
0.0 0
/
Vee=4.5V TA = 25'C
1 1-
200
400
",
H
X
Input/Output
Mode
X
X
HighZ
OeselectIPower-Down
X
L
X
X
H
H
L
HighZ
QataOut
Deselect
L
L
H
L
X
Data In
Write
L
H
H
H
HighZ
Deselect
Read
Address Designators
Address
Name
Address
Function
600
800 1000
CAPACITANCE (pF)
SUPPLY VOLTAGE (II)
Truth Table
c:E1 C~ WE OE
Jl
c
/
10.0
5.0
5.0
~
25.0
"
Pin
Number
A4
X3
2
AS
X4
3
A6
X5
4
A7
X6
5
A8
X7
6
A9
Y1
AlO
Y4
7
8
All
Y3
9
A12
YO
10
AO
Y2
21
Ai
XO
23
A2
Xl
24
A3
X2
25
Ordering Information
Document #: 38-00425
2-6
NORMALIZED Icc vs. CYCLE TIME
.
Vee = 5.0V
TA = 25'C
Vee = 0.5V
i
z
0·501'=0--~2:::0---3:!:0:---~40
CYCLE FREQUENCY (MHz)
CY7CIOlA
CY7CI02A
PRELIMINARY
_rcYPRESS
Maximum Ratings
(Above which the useful life maybe impaired. For user guidelines,
not tested.) .
Storage Thmperature .................. -65°C to +150°C
Ambient Thmperature with
Power Applied ................ , ...... -55°C to + 125°C
Supply Voltage on Vee Relative to GND[1] . -O.5V to +7.0V
Latch-Up Current ........................... > 200 rnA
Operating Range
Ambient
Temperature
Vee
O°Cto +70°C
5V:± 10%
-55°C to +125°C
5V:± 10%
Range
Commercial
Military[2]
DC Voltage APBlied to Outputs
in High Z State 1] ........ ;......... -0.5V to Vee +0.5V
DC Input VOltagd1] •..••...•..•.... -0.5V to Vee +0.5V
Current into Outputs (LOW) ..................... 20 rnA
Static Discharge Voltage ........................ >2001 V
(per MIL-STD-883, Method 3015)
Notes:
1. VIL (min.) = -2.0V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
Electrical Characteristics Over the Operating Rangd3]
7CIOlA-12
7CI02A-12
Parameter
VOH
VOL
VIH
VIL
IIX
Ioz
los
Icc
ISB1
ISB2
Description
Test Conditions
Min.
Output HIGH
Voltage
Output LOWVoltage
Input HIGH Voltage
Input LOW
Voltagd 1]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[4]
Vee Operating
Supply Current
Vee = Min.,
IOH = -4.0 rnA
Vee = Min., IOL = 8.0 rnA
2.4
GND.$. VI.$. Vee
GND.$. VI.$. Vee,
Output Disabled
Vee = Max., VOUT = GND
Vee = Max.,
lOUT = 0mA,
f = fMAX = litRe
Com'l
Max.
0.4
Min.
Max.
2.4
0.4
Unit
V
0.4
Vee + 0.3
0.8
2.2
-0.3
Vee + 0.3
0.8
2.2
-0.3
Vee + 0.3
0.8
V
V
V
-1
-5
+1
+5
-1
-5
+1
+5
-1
-5
+1
+5
fAA.
fAA.
-300
-300
-300
rnA
165
155
140
rnA
165
150
40
30
40
30
2
2
2
2
50
AutomaticCEPower- Max.Vcc,
Down Current
CE~ Vee - 0.3v,
- CMOS Inputs
VIN ~ Vee - 0.3V
or VIN .$. 0.3v, f=O
2
2-8
Max.
7CIOIA-20
7CI02A-20
2.2
-0.3
Automatic CE
Max. Vee,
Com1
Power-Down Current CE~VIH,
-TIL Inputs
VIN~ VIHor
Mil
VIN.$. VIL, f = fMAX
Mil
Min.
2.4
Mil
Com'l
7CIOIA-lS
7CI02A-lS
rnA
rnA
CY7C101A
CY7CI02A
PRELIMINARY
QPRESS
Switching Characteristics Over the Operating Rangel3, 6J
Parameter
Description
READ CYCLE
Read Cycle Time
tRC
7CIOIA-12
7CI02A-12
Min. Max.
12
tAA
Address to Data Valid
tOHA
Data Hold from Address
Change
3
3
tHZCE
CE LOW to Data Valid
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8J
tpu
CE LOW to Power-Up
0
tACE
tLZCE
7CIOlA-15
7CI02A-15
Min. ~ax.
15
3
12
3
0
0
12
25
15
0
35
ns
10
ns
ns
0
25
20
ns
ns
3
10
Unit
ns
35
3
3
8
7
6
35
3
20
15
3
7CIOIA-35
7CI02A-35
Min. Max.
25
20
15
3
7CIOlA-25
7CI02A-25
Min.· Max.
25
20
12
CE HIGH to Power-Down
tpD
WRITE CYCLE[9J
7CIOlA-20
7CI02A-20
Min. Max.
ns
35
ns
twc
Write Cycle, Time
12
15
20
25
35
ns
tSCE
CE LOW to Write End
10
12
15
20
25
ns
10
12
15
20
25
ns
tHA
Address Set-Up to Write
End
Address Hold from Write
End
0
0
0
0
0
ns
tSA
Address Set-Up to Write
Start
0
0
0
0
0
ns
tpWE
WE Pulse Width
10
12
15
20
25
ns
tSD
Data Set-Up to Write End
7
10
15
20
ns
tHD
Data Hold from Write End
0
8
0
0
0
0
ns
tLZWE
WE HIGH to Low ZI7]
WE LOW to High Z[7,8J
3
3
3
3
3
tAW
tHZWE
tDWE
tDCE
tADV
WE LOW to Data Valid
(7C101A)
CE LOW to Data Valid
(7C101A)
Data Valid to Output Valid
(7C101A)
ns
6
7
8
10
10
ns
12
15
20
25
35
ns
12
15
20
25
35
ns
12
15
20
25
35
ns
Notes:
6. Thst conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of ato 3.0V, and output loading
of the specified IOl)lOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHzCE is less than
tLZCE and tHZWE is less than tLZWE for any given device.
8. tHZCE, and tHZWE are specified with.a load capacitance of 5 pF as in
part (b) of AC Thst Loads. 'Itansition is measured ±500 mV from
steady-state voltage.
9.
2-10
The internal write time ofthe memory is defined by the overlap ofCE
and WE LOW. CE and WE must be LOW to initiate a write, and the
transition of any of these signals can tenninate the write. The input
data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
PRELIMINARY
CY7CIOlA
CY7CI02A
Switching Waveforms (continued)
Write Cycle No.1 (CE Controlled)[9, 14]
IWC
ADDRESS
)C
~
K
ISA
tSCE
.
eE
~
}je'
lAW
IHA---tPWE
WE~~~
////////////m
I
IHD
ISD
~(
DATA IN
DATA OUT
(7Cl02A)
DATA VALID
_IHZCE-
HIGH IMPEDANCE
IADV
t: ILZC~~X
DATA OUT
(7Cl01A)
DATA VALID)
X
X)
Cl01A-8
IOCE
Write Cycle No.2
2001 V
(per MIL-SID-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature[2j
Vee
O°C to +70°C
5V ± 10%
-55°C to +125°C
5V ± 10%
Range
DC Voltage AP8lied to Outputs
in High Z State 1] .••..•.....•....•• -0.5V to Vee +O.5V
DC Input Voltagdlj ................ -0.5V to Vee +0.5V
Current into Outputs (LOW) ..................... 20 rnA
Commercial
Military
Electrical Characteristics Over the Operating Rangd3j
Parameter
Description
VOH
VOL
Vrn
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VIL
IIX
Ioz
Input LOW Voltagdlj
los
Icc
ISBl
ISB2
Input Load Current
Output Leakage Current
Output Short
Circuit Current[4j
Vee Operating
Supply Current
Test Conditions
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
7CI06A-12
7CI06A-15
7CI06A-20
Min.
Min.
Min.
2.4
-0.3
-1
-5
Com'!
Vee = Max.,
lOUT = oInA,
f = fMAX = litRe
Mil
Automatic CE
Power-Down Current
-TIL Inputs
Max. Vee,'CE ~ Vrn,
VIN ~ Vrn or VIN:5. VIL,
f= fMAX
Mil
Automatic CE
Power-Down Current
- CMOS Inputs
rn ~ Vee -
Max.Vcc,
Com'!
0.3y,
VIN ~ Vee - 0.3V
or VIN :5. 0.3y, f=O
Mil
Com'!
Max.
2.4
0.4
2.2
GND < VI < Vee
GND:5. VI:5. Vee,
Output Disab!ed
Vee = Max., VOUT = GND
Max.
Vee
+ 0.3
0.8
+1
+5
0.4
2.2
-0.3
-1
-5
Max.
Unit
0.4
V
V
V
2.4
Vee
+ 0.3
0.8
+1
+5
2.2
-0.3
-1
-5
Vee
+ 0.3
0.8
V
+1
+5
!lA
!lA
-300
-300
-300
rnA
165
155
140
rnA
165
150
40
30
40
30
2
2
2
2
50
2
rnA
rnA
Notes:
1. V Idmin.) = - 2.0V for pulse durations ofless than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
2-16
Not more thao 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
PRELIMINARY
QYPRESS
CY7C106A
Switching Characteristics Over the Operating Rangd3, 6]
Parameter
Description
7CI06A-12
7CI06A-15
7CI06A-20
7CI06A-25
7CI06A-35
Min.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Unit
35
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
. Data Hold from Address Change
12
15
12
3
3
25
20
15
3
35
25
20
3
ns
3
ns
tACE
CE LOW to Data Valid
12
15
20
25
35
ns
tDOE
OE LOW to Data Valid
6
7
8
10
10
ns
tLZOE
em LOW to Low Z
tHZOE
OE HIGH to High Z[7, 8]
tLZCE
CE LOW to Low Z[8]
tHZCE
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Down
0
0
7
6
3
3
8
0
12
15
10
10
8
0
3
10
0
20
ns
0
3
3
7
6
0
0
0
10
0
25
ns
ns
ns
ns
35
ns
WRITE CYCLE[9,1O]
15
20
25
35
ns
10
12
15
20
25
ns
10
12
15
20
25
ns
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tPWE
WE Pulse Width
10
12
15
20
25
ns
tSD
Data Set-Up to Write End
7
8
10
15
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[8]
2
3
3
3
3
ns
tHZWE
WE LOW to High Z[7, 8J
Write Cycle Time
12
tSCE
CE LOW to Write End
tAW
Address Set-Up to Write End
tHA
twc
7
6
8
10
10
ns
Notes:
6.
7.
8.
Thst conditions assume signal transition time of3 ns or less, timing reference levels of l.Sv, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
tHzoE,tHZCE,andlHzWEarespecifiedwithaloadcapacitanceofSpF
as in part (b) of AC Thst Loads. 1tansition is measured ±SOO mV from
steady-state voltage.
At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
The internal write time of the memory is defined by the overlap of<:E
and WE LOW. CE and WE must be LOW to initiate a write, and the
transition of either of these signals can terminate the write. The input
data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No.3 (WE controlled,
0Ii LOW) is the sum of tHZWE and tSD.
9.
2-18
PRELIMINARY
QYPRESS
CY7CI06A
Switching Waveforms (continued)
Write Cycle No.1 (CE Controll~d)[15, 16]
~-------------------------twc--------------------------~
ADDRESS
--+--------------.,.j+------tscE - - - - 1 ...-----+----1«-----------tAW
-----------01+~t~------~O--~~~
DATA I/O
---------------K~-----D-A-T-A-V-AL-I-D---....... )f------Cl0SA-B
Write Cycle No.2 (WE Controlled, OE IDGH During Write)[15,16]
~------------------------twc------------------------~
ADDRESS
~~~~~,~~-------tSCE-----~-----~
~----------------- tAW ---------------------~-
14----tpWE - - - - - - - t
---~----------~~~
,----------------
~---------Iso ----------+Io-.-j
DATAI/O
tHO
DATA VALID
Cl0SA-9
Notes:
15, IfCEgoesHIGHsimultaneouslywith WEgoingIDGH, theoutputre-
16. Data I/O is high impedance if OE = VIH.
mains in a high-impedance state.
2-20
_i/2YPRESS
PRELIMINARY
MILITARY SPECIFICATIONS
G"!ul! A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VILMax.
IIX
1,2,3
..
1,2,3
lciz
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
1,2,3
Switching Characteristics
Parameter
Subgroups
REAQCYCLE
tRC
7,8,9, 10, 11
tAA
7, 8, 9, 10, 11
tOHA
7,8, 9, 10, 11
tACE
7, 8, 9, 10, 11
tDOE
7,8,9, 10, 11
WRITE CYCLE
twc
7,8, 9, 10, 11
tSCE
7,8,9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tPWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
Document #: 38-00230-A
2-22
CY7CI06A
~YPRESS
PRELIMINARY
CY7CI07A
Maximum RatiJ,lgs
(Above which the useful life may be impaired.
not tested.)
Fo~ user guidelines,
Storage Thmperature .................. -65°C to + 150°C
Ambient Thmperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage on Vee Relative to GND[l] . -O.5V to +7.0V
Static Discharge Voltage ........................ > 2001 V
(per MIL-SID-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
DC Voltage APBlied to Outputs
in High Z State 11 .................. -0.5V to Vee +0.5V
DC Input VoltageI1] ................ -O.5V to Vee +0.5V
Corrent into Outputs (LOW) ..................... 20 rnA
Commercial
Military
Ambient
Temperatore[2]
Vee
O°Cto +70°C
5V± 10%
-55°C to + 125°C
5V± 10%
Electrical Characteristics Over the Operating RangeI3]
7CI07A-12
Parameter
VOH
VOL
Description
Output HIGH
Voltage
Output LOW
Voltage
Test Conditions
Min.
Vee = Min., IOH = -4.0 rnA
2.4
Vee = Min., IOL = 8.0 rnA
Input HIGH
Voltage
2.2
VlL
Input LOW
VoitageI 11
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[4]
Vee Operating
Supply Corrent
los
Icc
ISB1
Automatic CE
Power-Down
Corrent
- TfLlnputs
GND < VI < Vee
GND ~ VI~ Vee,
Output Disabled
Vee = Max., VOUT = GND
Vee = Max.,
lOUT = 0mA,
f = fMAX = litRe
Com'l
Max.. Vee,
CE~VIH'
Com'l
VIN~VIRor
VIN~ VIL,
7CI07A-15
Min.
Max.
2.4
0.4
VIR
Ilx
Ioz
Max.
-OJ
Vee+
0.3
0.8
-1
-5
+1
+5
7CI07A-20
Min.
0.4
2.2
Max.
2.4
2.2
Unit
V
0.4
V
V
-OJ
Vee+
0.3
0.8
-0.3
Vee+
0.3
0.8
-1
-5
+1
+5
-1
-5
+1
+5
!lA
!lA
V
-300
-300
-300
rnA
150
135
125
rnA
145
135
40
30
40
30
2
2
2
2
Mil
50
Mil
rnA
f = fMAX
ISB2
Automatic CE
Power-Down
Corrent
- CMOS Inputs
Max. Vee,
CE~ Vee - 0.3v,
VIN ~ Vee - 0.3Vor
VIN ~ 0.3V, f=O
Com'l
Mil
Notes:
1.
2.
VIL(min.) = -2.0V for pulse durations ofless than 20 ns.
TA is the "instant on" case temperature.
2-24
2
rnA
~YPRESS
PRELIMINARY
CY7CI07A
AC Test Loads and Waveforms
~p,
rI"l" ~:" rI"l"
25SQ
INCLUDING _
_
JIG AND
SCOPE
(a)Normal Load
ALL INPUT PULSES
3'OV~
GND
10%
90%
2SSQ
INCLUDING _
_
JIG AND
SCOPE
(b) High-Z Load
~
....
53n5
53n5
107A-4
107A-3
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT ...
o _ _ _1¥.~",,!_Q_ _...
o 1.73V
Switching Characteristics[3. 6] Over the Operating Range
Parameter
Description
READ CYCLE
Read Cycle Time
tRC
7CI07A-12
7CI07A-15
7CI07A-20
7CI07A-25
Min.
Min.
Min.
Min.
12
Address to Data Valid
taRA
Data Hold from Address
Change
3
3
tHZCE
CE LOW to Data Valid
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power-Up
0
tLZCE
Max.
Max.
Max.
7CI07A-35
Min. Max.
Unit
,
tAA
tACE
Max.
20
15
12
3
3
12
15
35
20
0
25
ns
ns
10
10
ns
ns
3
0
0
12
25
3
8
7
ns
35
3
3
3
0
35
25
20
15
3
6
CE HIGH to Power-Down
tPD
WRITE CYCLE[9]
25
20
15
ns
ns
35
ns
twc
Write Cycle Time
12
15
20
25
35
ns
tSCE
CE LOW to Write End
10
12
15
20
25
ns
tAW
Address Set-Up to Write
End
10
12
15
20
25
ns
tRA
Address Hold from Write
End
0
0
0
0
0
ns
tSA
Address Set-Up to Write
Start
0
0
0
0
0
ns
tpWE
WE Pulse Width
10
12
15
20
25
ns
tSD
Data Set-Up to Write End
7
8
10
15
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
3
3
3
3
3
ns
tHZWE
WE LOW to High Z[7, 8]
7
6
Notes:
6. Thst conditions assume signal transition time of3 ns or less, timing reference levels of 1.5\1, input pulse levels ofO to 3.0\1, and output ioading
of the specified IOI)IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHZWE is less than tLZWE for any given device.
8. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in
part (b) of AC Thst Loads. nansition is measured ±500 mV from
steady-state voltage.
9.
2-26
8
10
10
ns
The internal write time of the memory is defined by the overlap ofm
WWandWEWW.CEandWEmustbeWWtoinitiateawrite,and
the transition of any of these signals can terminate the write. The input
data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
~YPRESS
PRELIMINARY
CY7CI07A
Switching Waveforms (continued)
Write Cycle No.1 (CE ControlIed)[14]
twe
:==)(
ADDRESS
)(
!sA
tseE
-:It'
~
tHA-
tAW
tPWE
~~~~f;;.
///////////h
tHO ....
tso
'!!o~
DATA IN
~K
DATA VALID
HIGH IMPEDANCE
DATA OUT
107A-8
Write Cycle No.2 (WE ControlIed)[14]
twe
~ I{
--/
ADDRESS
~
)K
tseE
~
////0 W///&
tHA-
tAW
tsA
tpWE
~~
/'{
tHO ....
tso
'W"
DATA IN
DATA VALID
- tHZWE
::!
)K
f.- tLZWE
:-1
HIGH IMPEDANCE
DATA OUT _______________D_A_T_A_U_N_DE_F_IN_E_D______________J)~--------------~(~
_________
107A-9
Truth Table
CE
WE
H
X
L
L
DOUT
Mode
Power
HighZ
Power-Down
Standby (ISH)
H
Data Out
Read
Active (led
L
HighZ
Write
Active (led
Note:
14. !fCE goes IDGH simultaneouslywith WE going HIGH, the output remains in a high-impedance state.
.
2-28
CY7CI09
128K X 8 Static RAM
Functional Description
Features
• High speed
.,.-tAA = 20 ns
• CMOS for optimum speed/power
• Low active power
-770mW
The CY7C109 is a high-performance
CMOS static RAM organized as 131,072
words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable
(CEl),anactiveIDGHchipena~CEz),
an active LOW output enable (OE), and
three-state drivers. This device has an automatic power-down feature that reduces
power consumption by more than 75%
wj:len deselected.
• Low standby power
-16SmW
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
• Easy mem..!!!l' expansion with CEl>
CE2, and OE options
Writing to the device is accomplished by
takin~ enable one (Clh) and write enable (WE) inputs LOW and chip enable
two (CEz) input IDGH. Data on the eight
110 pins (1100 through 1/07) is then written
into the location specified on the address
pins (Ao through A16).
Reading from the device is accomplished
by taking~hienable one (CEl) and output enable OE) LOW while forcing write
enable (WE and chip enable two (CEz)
HIGH. Under these conditions, the contents of the memory location specified by
the address pins will appear on the I/O
pins.
The eight input/output pins (1100 through
1(07) are placed in a high-impedance state
when the device is deselected (eEl IDGH
or CEz LOW), the outputs are disabled
(DE IDGH), or during a wri~eration
(eEl LOW; CEz IDGH, and WE LOW).
The CY7C109 is available in standard
400-mil-wide DIPs and SOJs.
Pin Configurations
Logic Block Diagram
DIP/SOJ
lbpView
Vee
A,.
CE,
Il'IE
A,.
Ae
Aa
Al1
1/0 0
O"E
A'D
eE,
I/o,
I/o.
I/O.
1/0.
'1...!:2-._.:.:.t' I/o.
1/0 3
109-2
1/0 5
1/0 6
eE,
_.lL
. .r-....
CE,
Il'IE
OE--.Q....J
109-1
Selection Guide
Maximum Access Time (ns)
Maximum 0serating
Current (rnA
.
Maxim~ St)ndby
Current rnA
7CI09-20
20
7CI09-25
25
7CI09-35
35
Commercial
140
135
125
Commercial
30
30
25
2-30
~YPRESS
CY7CI09
AC Test Loads and Waveforms
OUTP~~ ~R1
4800
30pF
R2
~~8~~'FJNG
J.
SCOPE
(a) Normal Load
-=
ALL INPUT PULSES
3.0V - - - - I ...~~----"'""
OUTP~~ T I R4800
1
5pF
~~8~'FJNG
2550
SCOPE
J.
90%.
R2
-=
GND
2550
(b) High-Z Load
109-4
109-3
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT~
1.73V
Switching Characteristics[3, 6] Over the Operating Range
7CI09-20
Min. Max.
Description
Parameter
READ CYCLE
Read Cycle Time
tRC
Address to Data Valid
tAA
7CI09-25
Min. Max.
25
20
35
25
20
3
7CI09-35
Min. Min.
Data Hold from Address Change
tACE
CEl LOW to Data Valid, CE2 HIGH to Data Valid
20
25
35
ns
tDOE
m:l LOW to Data Valid
8
10
15
ns
tLZOE
OE LOW to Low Z
m:l HIGH to High Z[7, 8]
0
tLZCE
CEl LOW to Low Z, CE2 HIGH to Low Z[8]
tHZCE
tpu
CEl HIGH to High Z, CE2 LOW to High Z[7, 8]
0
8
3
5
0
CEl HIGH to Power-Down, CEz LOW to Power-Down
tPD
WRITE CYCLEL9, lUJ
ns
15
0
15
ns
ns
0
25
ns
ns
5
10
20
ns
0
10
8
CEl LOW to Power-Up, CEz HIGH to Power-Up
5
ns
ns
tOHA
tHZOE
5
35
Unit
35
ns
twc
Write Cycle Time
20
25
35
ns
tSCE
CEl LOW to Write End, CEz HIGH to Write End
15
20
ns
tAW
Address Set-Up to Write End
15
20
25
25
tRA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
15
20
25
ns
tSD
Data Set-Up to Write End
10
15
20
ns
tHO
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[8]
3
5
5
tHZWE
WE LOW to High Z[7, 8]
8
Notes:
6. Thst conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5Y, input pulse levels of 0 to 3.0Y, and output loading
of the specified IorJIOH and 30-pF load capacitance.
7. tHZOE, tHzCE, and tHZWE are specified with a load capacitance of 5
pF as in part (b) of AC Thst Loads. 1ransition is measured ±SOO mV
from steady-state voltage.
8. At any given temperature and voltage condition, tHZCE is less than
tlZCE, tHZOE is less than tLZOE, and tHZWE is less than tlZWE for any
given device.
9.
10
ns
ns
15
ns
The internal write time of the memory!!; defm~ the overlap ofi::lh
LOW, CEz HIGH, and WE LOW. eEl and WE must be LOW and
CEz HIGH to initiate a write, and the transition of any ofthese signals
can terminate the write. The input data set-up and hold timing should
be referenced to the leading edge of the signal that terminates the
write.
10. The minimum write cycle time for Write Cycle No. 3 ~ controlled,
OE LOW) is the sum of tHZWE and tSD.
2-32
.~YPRESS
CY7CI09
Switching Waveforms (continued)
Write Cycle No.2 (WE Controlled, OE IDGH During Write)[14, 15J
~---------------------~c--------------------~
ADDRESS'
........~....r................ ~--------tSCE ---------+1
~~"'f"'""L/~--------tSCE ----------I~
j4----..,.------IAW - - - - - - - - - - - . . j4----IPWE-------~
----------------~~~
,----------------
ISO
DATAI/O
DATAIN VALID
109-8
Write Cycle No.3 (WE Controlled, OE WW)[10, 15J.
ADDRESS
cr,
~~-----IPWE------~
----------~~~
DATA 1/0
,----------------
DATA VALID
109-9
2-34
PRELIMINARY
CY7CI09A
128K X 8 Static RAM
Features
Functional Description
• High speed
-tAA = 12ns
• CMOS for optimum speed/power
• Low active power
-1020mW
• Low standby power
-250mW
• 2.0V data retention (optional)
- IOO I1W
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
• Easy mell!!!!Y expansion with CE},
CEl, and OE options
The CY7CI09A is a high~performance
CMOS static RAM organized as 131,072
words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable
(eEl), an active IDGH chip ena~CEz),
an active LOW output enable (0£), and
three-state drivers. This device has an automatic power-down feature that reduces
power consumption by more than 75%
when deselected.
Writing to the device is accomplished by
takine enable one (eEl) and write enable (WE) inputs LOW and chip enable
two (CEz) input HIGH. Data on the eight
I/O pins (I/Oo through I/07) is then written
into the location specified on the address
pins (Ao through AI6).
Reading from the device is accomplished
by takinmc.
hi enable one (eEl) and output enable
LOW while forcing write
enable
and chip enable two (CEz)
IDGH. Under these conditions, the contents of the memory location specified by
the address pins will appear on the I/O
pins.
The eight input/output pins (I/Oo through
1/07) are placed in a high-impedance state
when the device is deselected (CEI HIGH
or CEz LOW), the outputs are disabled
~ IDGH), or during a wri~eration
(CEI LOW, CEz HIGH, and WE LOW).
The CY7CI09A is available in standard
400-mil-wide DIPs and SOJs and aleadless
chip carrier.
Logic Block Diagram
Pin Configurations
LCe
DIP/SOJ
1bpView
A,e
A,.
A"
A,
1/°0
1/0 ,
1/02
As
As
Vee
NC
A,.
A13
A,.
A,.
A12
A,
As
As
As
As
CE,
4
5
As
As
~
1bpView
8
9
A,
As
WE
A"
llE
A,o
GE,
vo,
1/00
I/O.
vo,
vo,
I/O,
VO.
1/03
GND
~
As
A,
A,
Ao
1/00
vo,
1/02
GND
1
2
3
•
5
6
7
8
9
10
11
12
13
1.
15
16
32
31
30
29
28
27
26
25
2.
23
22
21
20
19
18
17
1/0 3
109A-2
109A-3
1/0 4
1/0 5
1/0 6
1/0 7
109A-1
Selection Guide
Maximum Access Time (ns)
MaximumOperating Commercial
Current (rnA)
Military
Commercial
Maximum Standby
Current (rnA)
Military
7CI09A-12
12
185
45
7CI09A-15
15
170
180
40
40
2-36
7CI09A-20
20
155
170
30
30
7CI09A-25
25
145
160
30
30
7CI09A-35
35
140
150
25
25
PRELIMINARY
CY7CI09A
Electrical Characteristics Over the Operating Rangel3] (continued)
7CI09A-25
Parameter
Description
Test Conditions
Min.
VOH
VOL
Vrn
Output HIGH Voltage Vee = Min., IOH = - 4.0 rnA
Output LOW Voltage V cc - Min., IOL - 8.0 rnA
Input HIGH Voltage
VIL
IIX
loz
Input LOW Voltagell]
Input Load Current
Output Leakage
Current
.output Short
Circuit Currentl4]
V ee .openiti~g
Supply Current
Output Disabled
Vee = Max., VOUT = GND
Vee = Max.•
lOUT = ornA,
f = fMAX = litRe
Com'l
Mil
Automatic C]:l
Power-Down
Current
-mlnputs
Max. Vee, CE! ~ Vrn
orCE2~ VIL,
VIN~ Vrnor
VIN ~ VIL, f = fMAX
Automatic CE
Power-Down
Current
- CMOS Inputs
los
lee
ISB!
ISB2
7CI09A-35
Max.
Min.
2.4
0.4
2.2
Max.
Unit
0.4
V
V
V
2.4
2.2
Vcc+
0.3
0.8
+1
+5
!lA
!lA
-300
rnA
145
140
rnA
160
150
Com'l
30
25
Mil
30
25
Max. Veo
Com'l
2
2
CE! ~ V cc - 0.3V,
or CE2 ~ 0.3V,
VIN ~ Vee - 0.3V,
or VIN ~ 0.3V, f=O
Mil
2
2
-0.3
-1
-5
GND~VI~Vee
GND~VI~Vee,
Vee +
0.3
0.8
+1
+5
-0.3
-1
-5
-300
V
rnA
rnA
Capacitance[5]
Parameter
Description
CIN: Addresses
Test Conditions
TA = 25°C, f = 1 MHz,
Input Capacitance
Vee = 5.0V
CIN: Controls
Output Capacitance
GoUT
Max.
Unit
7
pF
10
pF
10
pF
AC Test Loads and Wavefonns
OUTP~~ ~
'n~~:F1
J
INCLUDING
JIG AND
SCOPE
-
1_
OUTP~~ ~
R2
255Q
-
(a) Normal Load
'n,.~:F1
J
INCLUDING
JIG AND
SCOPE
-
1_
ALL INPUT PULSES
3.0V - - - l r 9 Q % = - - - - - "
GND
R2
255Q
THEvENIN EQUIVALENT
OUTPUT~
ns
(b) High-Z Load
10BA-4
Equivalent to:
~3
-
1.73V
Notes:
3.
See the last page of this specification for Group A subgroup testing
information.
4. Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
5. 'Iested initially and after any design or process changes that may affect
these parameters.
2-38
109A-5
~YPRESS
CY7CI09A
PRELIMINARY
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter
VOR
Vee for Retention Data
Commercial
Min. Max.
2.0
Condition.[U]
Description
IecoR
Data Retention Current
teoR[5]
Chip Deselect to Data Retention Time
tR[5]
Operation Recovery Time
Yc.e = VOR = 2.0V,
CEI ~ Vee - O.3Vor
CE250.3V,
VIN ~ Vee - O.3Vor
VIN50.3V
Military
Min.
Max.
2.0
50
70
Unit
V
J.IA
0
0
ns
tRe
tRe
ns
Data Retention Waveform
VCC
Switching Waveforms
Read Cycle No. 1[12. 13]
'G
~
ADDRESS _ _ _ _ _ _
DATA OUT
*-
IRC
1
~~"'
PREVIOUS DATA VALID 9XXX*===============D=A=TA=V=A=L=ID===========
109A-7
Read Cycle No.2 (OE Controlled)[13. 14]
ADDRESS
)<
K
tRC
~I'\..
Il'
~"
-../1{
lACE
)1'\..
/i
tOOE
I---IU:OEHIGH IMPEDANCE
1////
DATA OUT
~
=t
I+-tpu
VCC _ _ _ _ _ _ _
SUPPLY
CURRENT
_IHZCEDATA VALID
.1'-""
ILZCE
I ZOE
-Ipo
50%
HIGH
IMPEDANC E
~ ICC
50%
ISB
109A-B
Notes:
11. No input may exceed Vee +O.sY.
12. Device is continuously selected.lJE, CEI = VIL C~ = VIH.
13. WE is HIGH for read cycle.
14. Address valid prior 10 or coincident with CEI transition LOW and CE2
transition HIGH.
2-40
PRELIMINARY
CY7CI09A
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[lO, 16]
ADDRESS
----------~~~
~----------t~E------------~
~---------------
Iso
DATAI/O
DATA VALID
1(J9A-11
Truth Table
OE WE Input/Output
CEl
CE2
H
X
X
X
L
L
H
L
H
L
H
Power
Mode
X
HighZ
Power-Down
X
X
HighZ
Power-Down
Standby (ISB)
L
H
Data Out
Read
Active (Icd
X
L
Data In
Write
Active (Icd
H
H
HighZ
Selected, Outputs Disabled
Active (Icc)
Standby (ISB)
Ordering Information
Speed
(ns)
12
15
20
Package
Name
Package JYpe
Operatmg
Range
CY7C109A -12PC
P43
32-Lead (400-Mil) Molded DIP
Commercial
CY7C109A -12VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C109A -15PC
P43
32-Lead (400-Mil) Molded DIP
CY7C109A -15VC
V33
32-Lead (400-Mil) Molqed SOJ
CY7C109A -150MB
D44
32-Lead (400-Mil) CerDIP
.CY7C109A-15LMB
L75
32-Pin Leadless Chip carrier
CY7C109A - 20PC
P43
32-Lead (400-Mil) Molded DIP
CY7C109A - 20VC
V33
32-Lead (400-Mil) MoldedSOJ
CY7C109A-20DMB
D44
32-Lead (400-Mil) CerDIP
L75
32-Pin Leadless Chip Carrier
Ordering Code
CY7C109A-20LMB
..
Contact factory for " r;" versIon avaIlabilIty.
2-42
Commercial
Military
Commercial
Military
CY7C123
256 X 4 Static RAM
Features
Functional Description
• 256 x 4 static RAM for control store
in high-speed computers
• CMOS for optimum speed/power
• Highspeed
-7 ns (commercial)
-10 ns (military)
The CY7C123 is a high-performance
CMOS static RAM organized as 256
words by 4 bits. Easy memory expansion is
provided by an active LOW chip select one
(CSl) input, an active HIGH chip select
two (CS2) input, and three-state outputs.
• Lowpower
- 660 mW (commercial)
-825 mW (military)
• Separate inputs and outputs
• 5,volt power supply ± 10% tolerance
both commercial and military
• TTL-compatible inputs and outputs
• 24pins
• 3OO-mil package
Writing to the device is accomplished
when the chip select one (CSl) and Write
enable (WE) inputs are both LOW and
the chip select two input is HIGH. Data
on the four data inputs (Do through D3) is
written into the memory location specified
on the address pins (Ao through A7). The
outputs are preconditioned so that the
write data is present at the outputs when
the write cycle is complete. This precondi-
Logic Block Diagram
tion operation ensures minimum write recovery times by eliminating the "write recovery glitch."
Reading the device is acco2!!Plished bytaking the ~ select one (CSl) and output
enable (Q!D inputs Law, while the write
enable (WE) and chip select two (CS2) inputs remain HIGH. Under these conditions, the contents ofthe memory location
specified on the address pins will appear on
the four output pins (00 through 03).
The output pins remain in high-impedance state when chip select one (CSl) or
output enable (DE) is HIGH, or write enable (WE) or chip select two (CS2) is
LOW.
A die coat is used to insure alpha immunity.
Pin Configuration
CS2
CS1
DIP/SOJ
Top View
A,
WE
Aa
A..
Aa
Aa
m:
Ao
II:
AI
U
00
w
0
C
0,
A2
~
3:
Ao
WE
CS,
OE
Vee
cs"
W
C
Vee
AI
O2
D,
D.
03
03
D.
0
II:
C123-2
A..
A.,
~
A7
Selection Guide
7CI23-7
7CI23-9
Maximum Access Time (ns)
Commercial
Military
7
9
Maximum Operating Current (rnA)
Commercial
120
120
7C123-10
12
15
120
150
2-44
7CI23-15
12
10
Military
7CI23-12
150
150
~YPRESS
CY7C123
AC Test Loads and Waveforms
R14700
5V_--_--,
5V31R14700
OUTPUT----t---+
OUTPUT
R2
R2
20pF
5pF
2240
2240
INCLUDING
INCLUDING
JIG AND ":'
":'
JIG AND ":'
":'
SCOPE
(a) Nonnal Load
SCOPE
(b) HIgh-Z Load
ALL INPUT PULSES
3.0V~
10%
90%
~s
GND< 3ns-
C123-4
C123-3
THEVENIN EQUIVALENT
Equivalent to:
OUTPUT 0.0_ _....tN~....O_ _.Qo 1.62V
Switching Characteristics Over the Operating Range[3]
7Cl23-7
Parameter
Description
READ CYCLE
Read Cycle Time
tRC
Min.
7Cl23-9
Max.
Min.
Max.
9
7
7C123-10
Min. Max.
7C123-12
12
10
7Cl23-15 I
Min. Max. Min. Max.I Unit
15
ns
tAA
Address toData Valid
7
9
10
12
15
ns
tACS
Chip Select to Data Valid
7
Ii
8
8
10
ns
tDOE
O;E WW to Data Valid
7
8
8
8
10
ns
tHzCS
Chip Select to High Z[6, 7]
5
6
6
6.5
8
ns
tHZOE
OE HIGH to High Z[6]
5
6
6
6.5
8
ns
tLZCs
Chip Select to Low Z[7]
2
2
2
2
2
ns
tLZOE
OE
_. LOW to Low Z
2
2
2
2
2
ns
WRITE CYCLE
twc
Write Cycle Time
tHZWE
WEJOW to High Z[6]
7
9
5.5
10
6
12
15
7
6
ns
8
lis
tLZWE.
WE HIGH to Low Z
2
2
2
2
2
ris
tpWE
WE Pulse Width
5
6.5
7
8
11
lis
tSD
Data Set-Up to Write End
5
6
7
8
11
ris
tHD
Data Hold frllm Write End
1
1
1
1
1
ns
tSA
Address Set-Up to Write Start
0.5
1
1
2
2
ns
tHA
A4dress Hold from Write End
1.5
i.5
2
2
2
ns
tscs
CS LOW to Write End
5
6.5
7
8
11
ns
tAW
Address Set-Up to Write End
5.5
1.5
8
10
13
ns
Notes:
6. 'Iransilion is measured at steady-state mGH level - 500 mV or
steady-state LOW level +500 mV on the output from 1.5V level on
the input with load shown in part (b) of AC Thst Loads.
7.
2-46
At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device.
~YPRESS
CY7C123
'JYpicaJ DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NO~EDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.4
III 1.2
ii 1.0
Icc
V
o
~ O.S
~
0.6
V
/'
V
a:
~ 0.4
0.2
4.5
5.0
0.8
~
0.6
0
1.2
w
~
~
M
25
125
AMBIENT TEMPERATURE ('C)
W
r---......
0.9
O.S
4.0
4.5
5.0
----TA= 25'C
5.5
SUPPLY VOLTAGE
j
0
/
M
.2-
~
f!:
--
2.0
SUPPLY VOLTAGE
~
/
V
3.0
4.0
M
0
"
o
5.0
1.0
20
/
10
V
o
o
200
"
4.0
M
./
~ 240
/
Vee = 5.0V
I-
/
3.0
360
~
U
2 180
1i5
~
125
".--
V
2.0
OUTPUT VOLTAGE
::l
25
J.
"" 1.5
1.0
15
'" "
OUTPUTS~CURRENT
TOTAL ACCESS TIME CHANGE
vs. OUTPUT WADING
30
1
_I
Vee =4.5V
TA= 25'C
I
@ 2.0
0.5
~
o
120
60
0.0
1.0
-
'/
/
V
o
AMBIENT TEMPERATURE ('C)
2 .5
O. 0
0.0
1.0
0.6
-55
3.0
~
30
vs. OUTPUT VOLTAGE
./
1.2
O.S
TYPICAL POWER·ON CURRENT
vs. SUPPLY VOLTAGE
Z 1.0
"-
Vee = 5.0V
TA = 25'C
~ 300
Z
6.0
I
45
51
1
0
N
...........
,
NORMALIZED ACCESS TllME
vs. AMBIENT TEMPERATURE
j1.4
1.1
~
75
~ 60
Vee - 5.0V
VIN = 5.0V
1.6
a:
0 1.0
z
0
~
90
::l
-55
1.4
1.3
'Z
~
NORMALIZED ACCESS TllME
vs. SUPPLY VOLTAGE
j
1
u
0.0
6.0
5.5
SUPPLY VOLTAGE
C
0.2 f- ISB
0.0
4.0
~
~ 0.4
z
-
ISB
1.2
.,
~ 1.0
g
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
2.0
Vee = 5.0V _
TA = 25'C
I
I
3.0
4.0 5.0
OUTPUT VOLTAGE
M
NORMALIZED Icc vs. CYCLE TllME
1.1
j
Vee = 5.0V
TA = 25'C
VIN = 0.5V
I
oz
400
600
SOO
CAPACITANCE (pF)
2-48
1000
0,S1'=0--~2::::0---3:!-:0:---~40
CYCLE FREQUENCY (MHz)
CY7C128A
2K X 8 Static RAM
Features
Data on the. eight I/O pins (IlOo through 1/
Functional Description
• Automatic power-down when
deselected
• CMOS for optimum speed/power
• High speed
-15ns
• Low active power
- 440 mW (commercial)
- 550 mW (military)
• Low standby power
-llOmW
• TTL-compatible inputs and outputs
• Capable of withstanding greater than
2001Velectrostatic discharge
• Vmof2.2V
07) is written into the memory location spe-
The CY7C128A is a high-performance
CMOS static .RAM organized as 2048
words by 8 bits. Easy memory expansion is
Jlrovided by an active LOW chip enable
(~, and active LOW output enable (00)
and three-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power consumption by 83%
when deselected.
Writing to the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs are both LOW.
Logic Block Diagram
cified on the address pins (Ao through AiD).
Reading the device is accomplished by tak~hip enable (CE) and output enable
(OE) LOW while write enable (WE) remains HIGH. Under these conditions, the
contents of the memory location specified
on the address pins will appear on the eight
IJOpins.
The I/O pins remain in high-impedance
state when chip enable (CE) or output enable (OE) is HIGH or write enable (WE)
is LOW.
The CY7C128A utiJizes a die coat to ensure alpha immunity.
Pin Configurations
DIP/SOJ
Top View
Vee
As
As
WE
OE
A,o
CE
110,
1/°0
1/0.
1/0,
1/0 0
1/0,
1/0 2
GND
1/0,
110,
110 3
1/02
C128A-2
1/°3
LCC
Top View
1/0 4
ud~
1/0 5
CE
WE
1/0 6
OE
1/07
As
As
As
3 2t1)24~
21
20
19
18
A,
As
1100
110,
As
WE
OE
AlO
CE
17 1/0,
16 110.
10
1112131415
C\lO C")'It
U')
g~ggg
C'28A-1
C128A-3
Selection Guide
Maximum Access Time (ns)
Maximum oserating
Current (rnA
Commercial
Maximum Standby
Current (rnA)
Commercial
7C128A-15
7C128A-20
7C128A-25
7C128A-35
7C128A-45
15
20
25
35
45
120
100
100
100
125
125
100
40/20
20
20
40/20
40
20
Military
40/40
Military
2-50
,
100
20
CY7C128A
CsflEYPRESS
"1~
"1~
AC Test Loads and Waveforms
0""::;: '" II
p'
INCLUDING _
JIGAND SCOPE
2550
ou.:,: '''' II
_
(a) Normal Load
ALL INPUT PULSES
3'OV~
GND
10%
90%
2550
~O%
S5~
INCLUDING _
_
.
JIG AND SCOPE
(b) High·Z Load
~
S5~
C128A-5
C128A-4
Equivalent to:
THEvENIN EQUIVALENT
OUTPUT oo-_-JOl,~",~?,..O_ _.<)o 1.73V
Switching Characteristics Over the Operating Rangd2• 6J
Parameter
Description
7C128A-15
7C128A-20
7C128A-25
7C128A-35
7C128A-45
Min.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
15
15
rn LOW to Low Z[8J
tHZCE
CE HIGH to High Z[7, 8J
tpu
CE LOW to Power· Up
tpD
CE HIGH to Power·Down
25
5
5
15
10
10
3
3
8
5
10
8
8
0
0
0
ns
45
ns
ns
20
12
0
15
ns
15
ns
25
ns
ns
0
20
ns
ns
5
15
20
45
3
5
10
20.
15
15
3
5
ns
5
35
12
3
8
5
35
5
25
20
45
35
25
20
5
OE HIGH to High Z[7J
tLZCE
20
ns
WRITE CYCLE!Yj
twc
Write Cycle Time
15
20
20
25
40
ns
tSCE
rn LOW to Write End
12
15
20
25
30
ns
tAW
Address Set·Up to Write End
12
15
20
25
30
ns
tRA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set·Up to Write Start
0
0
0
0
0
ns
tpWE
WE Pulse Width
12
15
15
20
20
ns
tSD
Data Set·Up to Write End
10
10
10
15
15
ns
tHD
Data Hold from Write End
0
0
0
0
0
tHZWE
WE LOW to High Z[7J
tLzWE
WE HIGH to Low Z
7
7
5
5
Note:
6. Thst conditions assume signal transition time of 5 ns or less, timing ref·
erence levels of l.SV; input pulse levels of 0 to 3.0V; and output load·
ing of the specified IOl}lOH and 30·pF load capacitance.
7. tHZOE. tHZCE, and tHZWE are specified with CL = S pF as in part (b)
of AC Thst Loads. 'lfansition is measured ±SOO m V from steady state
voltage.
8. At any given temperature and voltage condition. tHZCE is less than
tLZCE for any given device.
9.
2-52
7
5
10
5
ns
15
5
ns
ns
The internal write time ofthe memory is defined hy the overlap ofm
LOW and WE LOW. Both signals must be LOW to initiate awrite and
either signal can terminate a write by going HIGH. The data input set·
up and hold timing should be referenced to the rising edge of the sig·
nal that terminates the write.
.~YPRESS
CY7C128A
Switching Waveforms (continued)
Write Cycle No.2
(0: Controll~d)t9, 13, 14]
twe - - - - - - ' - - - - - - - - - ,
~----II---- tseE ---~
---+--------~----~
DATA IN
---------------------
,-----~------
1 + - - 1 - - - - - tso
----<-
DATAIN VALID
tHZWE
:::j
DATA I/O _ _ _ _ _ _ _ _
D_Al_A_U_N..;,D_E_F_IN_E_D_ _ _ _ _ _ _---I>>--H-I-G-H-IM_p_E_b_A_N_e_E_ _ _ _ _ __
C128A-9
Note:
14. IfeE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
'IYpical DC and AC CharacteristiCs
NO~ED SUPPLY CURRENT
vs. AMBffiNT TEMPERATURE
NO~ZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.4
1Jl1.2
6 .
21.0
C
.
~ O.B
::;
.
:!!a:
!it
0.6
lee
V
V
./
V
----1
1.2
III
~ 1.0
c~ 08
.
0
z
0.2
-
ISB
0.4
0.0
4.5
5.0
5.5
BO
~
60
::l
5l
~
40
~ 2:
ISR
-~
6.0
1~
'"
0.0
ACCESS TIME
vs. SUPPLY VOLTAGE
.
2.0
J 1.41----+-----1 !z
11.
~ 1.2
~
1.1
!it
1.0
...........
I"---
0.9
0.8
4.0
4.5
5.0
--
1.01-----::J.,.e:..---~
r--
5.5
SUPPLY VOLTAGE (V)
6.0
!it
40
o
20
~
0~~·~----±25~---~125
AMBIENT TEMPERATURE (Oe)
2-54
/
o1/
0.0
=
=
Vee 5.0V
TA 25°e
V
:.:
Z 60
CiS
!5
V
/
B 80
a:
TA = 25°e
/
~ 100
a:
2
"
4.0
L __
~120
1.3
3.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~ 140
1.6
1.4
"-
OUTPUT VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBffiNT TEMPERATURE
NO~ZED
Vee '=.5.0V
TA = ,25°C)
..............
1.0
AMBIENT TEMPERATURE (Oe)
SUPPLY VOLTAGE (V)
J
~
::l
u
Vee - 5.0V
VIN = 5.0V
0.2
0.0
4.0
!zw 100
~
0.6
0.4
OUTPUT SOURCE CURRENT
~
vs.OUTPUTVOLTAGE
l120
/
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
CY7C128A
t.i;rcYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IJX
1,2,3
loz
1,2,3
Icc
1,2,3
ISB
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
tRC
7,8,9, 10, 11
tAA
7,8,9, 10, 11
taHA
7,8,9, 10, 11
tACE
7,8,9, 10, 11
tOOE
7,8,9, 10, 11
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAw
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tPWE
7, 8, 9, 10, 11
tso
7, 8, 9, 10, 11
tHO
7, 8, 9, 10, 11
Document #: 38-00094-B
2-56
CY7C148
CY7C149
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to +ls0°C
Ambient Temperature with
Power Applied ....................... -55°C to +12SoC
Supply Volt~ge to Ground Potential
(Pm 18 to Pm 9) ........................ -o.sv to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.sV to +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ........................ >2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
Military[1]
Ambient
Temperature
O°Cto +70°C
Vee
5V± 10%
-55°C to + 125°C
5V± 10%
Electrical Characteristics Over the Operating Range[2]
7C148-25
7C149-25
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
Min.
7C148-3S,45
7C149-35,45
Max.
2.4
Vee = Min., IOH = -4.0 rnA
Min.
Max.
2.4
V
VOL
Output LOW Voltage
Vm
Input HIGH Voltage
2.0
6.0
2.0
6.0
VIL
Input LOW Voltage
-3.0
0.8
-3.0
0.8
V
hx
Input Load Current
GNDs VI s Vee
-10
10
-10
10
loz
Output Leakage Current
GND s Vo s Vee Output Disabled
-50
50
-50
50
!lA
!lA
lee
Vee Operating
Supply Current
Max. Vee, CS s VIL,
Output Open
80
rnA
Automatic CS
Power-Down Current
Max. Vee, CS.::::. Vm
Peak Power-On
Current[3]
Max. Vee, CS.::::. Vm
Output Short
Circuit Current[4]
GNDsVosVee
ISB
Ipo
los
0.4
Unit
Vee = Min., IOL = 8.0 rnA
Com'l
90
Mil
7C148
Only
7C148
Only
Com'l
15
V
rnA
10
10
10
15
Mil
Com'l
V
110
Mil
Com'l
0.4
rnA
10
±27s
Mil
±275
rnA
±350
Capacitancef5]
Parameter
Description
CIN
Input capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = S.OV
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
infonnation.
3. A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vcc power-up. Otherwise current will exceed
.
values given (CY7C148 only).
4.
5.
2-58
Max.
Unit
8
pF
8
pF
For test pUIJ?oses, not more than 1 output should be shorted at one
time. DuratIon of the short circuit should not exceed 30 seconds.
Thsted initially and after any design or process changes that may affect these parameters.
CY7C148
CY7C149
1sVEYPRESS
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
)(
~
ADDRESS
tAA
-tOH
DATA OUT
*XX)~
PREVIOUS DATA VALID
DATA VALID
C148-6
Read Cycle No. 2[10, 12]
tRC
"""'\K.
,)f-
tACS
~tHZj
tLZ::I
DATA OUT
HIGH IMPEDANCE
DATA VALID
""
tpu
VCC
SUPPLY
CURRENT
' // /
HIGH
IMPEDANCE
/
~tpo-"'"
- ICC
J ~ 50%
50%'\
' - - I SB
C148-7
Write Cycle No.1 (WE Controlled)
~-----------------------twc ------------------------~
ADDRESS
~----------------tcw ------------------~
~--------------------~w----------------~~--
____~~===~tA~S~===::J~~ 14------ twp
-------.~
, ___________________
tow
DATA-IN VALID
DATA IN
twzj
-J)
DATAOUT _______________D_A_TA
__
U_ND_E_F_IN_E_D______________
tow--l
HIGH IMPEDANCE
1<'"----C148-8
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CS =
12. Address valid prior to or coincident with CS transition LOW.
VIL.
2-60
CY7C148
CY7C149
1Ypical DC and AC Characteristics
TYPICAL POWER-ON CURRENT
vs_ SUPPLY VOLTAGE (7C148)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING
3.0
0
2.5
...!!C
w 2.0
g
TA = 25'C
I-- 1K Q CS PULL-UP
~
::t
RESISTOR TO Vee
~
---- ISCS
---.-j
tSD
DATAIN VALID
DATA IN
tHZWE
--I
~_J~LI--H-IG-H--IM-P-E-DA-N-C-E-----________
/'
DATA I/O _ _____________________________________
DATA UNDEFINED
C150-8
Reset Cycle[13]
~-------------tRRC ----------------------.....,~
ADDRESS
tSAR
14------- lHAR
HIGH
IMPEDANCE
-------~
OUTPUT VALID ZERO
C150-9
Notes:
12, If CS goes HIGH with WE IDGH, the output remains in a highimpedance state.
13. Reset cycJe is defined by the overlap ofRS and CS for the minimum reset pulse width.
2-68
-' ---.....
'"="',
CY7C150
==,.,.~
CYPRESS
Truth Table
Inpnts
CS
WE
OE
RS
H
X
X
X
HighZ
L
H
X
L
HighZ
Reset
L
L
X
H
HighZ
Write
L
H
L
H
0 0 -03
Read
L
X
H
H
HighZ
Output Disable
Outputs
Mode
Not Selected
Ordering Information
Speed
(ns)
10
12
15
25
35
Ordering Code
Package
Name
Package 1Ype
Operating
Range
CY7C150-10PC
P13A
CY7C150-10SC
S13
CY7C150-12PC
P13A
CY7C150-12SC
S13
24-Lead Molded SOIC
CY7CI50-12DMB
D14
24-Lead (300-Mil) CerDIP
CY7C150-15PC
P13A
24-Lead (300-Mil) MoldedDIP Commercial
CY7C150-15SC
S13
24-Lead Molded SOIC
CY7CI50-15DMB
D14
24-Lead (300-Mil) CerDIP
CY7C150-25PC
P13A
24-Lead (300-Mil) Molded DIP Commercial
24-Lead (300-Mil) Molded DIP Commercial
24-Lead Molded SOIC
24-Lead (300-Mil) Molded DIP Commercial
Military
Military
CY7C150-25SC
S13
24-Lead Molded SOIC
CY7C150- 25DMB
D14
24-Lead (300-Mil) CerDIP
Military
CY7C150- 35DMB
D14
24-Lead (300-Mil) CerDIP
Military
2-70
CY7C161
CY7C162
16Kx 4 Static RAM
with Separate I/O
Features
• High speed
-1S-ns
• 'Ihlnsparent write (7C161)
• CMOS for optimum speed/power
• Low active power
-633mW
• Low standby power
-220mW
• TTL compatible inputs and outputs
• Automatic power-down when
deselected
Functional Description
into the memory location specified on the
address pins (Ao through A13).
The CY7C161 and CY7C162 are high-performance CMOS static RAMs organized
as 16,384 by 4 bits with separate I/O. Easy
memory expansion ~rovided by active
LOW chip enables (CEl> CEz) and threestate drivers. They have an automatic power-down feature, reducing the power consumption by 65% when deselected.
Reading the device is accomplished by taking the chip enabl~CEh CEz) LOW
while write enable (WE) remains HIGH.
Under these conditions the contents of the
memory location specified on the address
pins will appear on the four data output
pins.
The output pins stay in a hijll1-impedance
state when write enable (WE) is LOW
~162 only), or one of the chip enables
(CEh CEz) are HIGH.
A die coat is used to ensure alpha immunity.
Writingtothedeviceisaccomplishedwhen
the c~nable (CEh CEz) and write enable (WE) inputs are both LOW Data on
the four input pins (10 through 13) is written
Logic Block Diagram
Pin Configurations
10
DIP
ThpView
r------l====~----
13
00
0,
03
C162·2
C162·1
Selection Guide[!]
Note:
1.
For military specifications, see the CY7C161NCY7C162A datasheet.
2-72
CY7C161
CY7C162
~YPRESS
Electrical Characteristics Over the Operating Range (continued)
7C161-20
7C162-20
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
Vee = Min.,
IOH = -4.0 rnA
VOL
Output LOW Voltage
Vee = Min.,
IOL = 8.0 rnA
Min.
7C16l-2S ,3S
7C162-2S ,3S
Max.
Min.
2.4
Max.
Unit
2.4
0.4
V
0.4
V
V
VIH
Input HIGH Voltage
2.2
Vee
2.2
Vee
VIL
Input LOW Voltagef2]
-0.5
0.8
-0.5
0.8
V
IIX
Input Load Current
GNDs VIS Vee
-5
+5
-5
+5
loz
Output Leakage
Current
GND S VIS Vee,
Output Disabled
-5
+5
-5
+5
!lA
!lA
los
Output Short
Circuit Currentl3]
Vee = Max.,
VOUT= GND
-350
-350
rnA
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
80
70
rnA
ISBI
Automatic -eEl
Power-Down Current
Max. Vee,
40
20
rnA
ISB2
Automatic CEI
Power-Down Current
Max. Vee,
CEI ~ Vee - 0.3\1,
VIN ~ Vee - 0.3Vor
VINsO.3V
20
20
rnA
CEl~ VIH
Min. Duty Cycle = 100%
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
10
pF
10
pF
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
2. Minimum voltage is equal to - 3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
4.
'Iested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
14810
5V
OUTPUTo--_--t
30pF
INCLUDING
JIG AND
5 PF
R2
2550
-=
4810
5V
ALL INPUT PULSES
OUTPUT~-~~-+
-=
INCLUDING
JIG AND
SCOPE (a) Normal Load
r-=
3'OV~
R2
2550
GND
'"
s5ns
-=
~
_5ns
SCOPE (b) High-Z Load
C162-3
Equivalent to:
90%
THEVENIN EQUIVALENT
1670
O U T P U T - - - . . o 1.73V
2-74
C1624
CY7C161
CY7C162
1c~YPRESS
Switching Waveforms[8]
€
Read Cycle No. 1[10, 11]
ADDRESS
--~
DATA OUT
PREVIOUS DATA
V~~;
*----
IRC
1
1M
=-!xxxxx>K===============D=AT=A=V=A=L=ID============
Cl62-5
Read Cycle No. 2[10, 12]
IRC
~~
....
lACE
OE
I--tLZCE
CURRENT
I
IOOE
tLZOE--
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
~
~~
////
-
DATA VALID
.'"
-~
S~
O% CC
HIGH
IMPEDANCE
tHZCE
/
4 - - Ipo
_=jSO%
_tpu
I
ISB
Cl62-6
Write Cycle No.1 (WE Controlloo)[9]
IWC
ADDRESS
~
-.J
~~
K
) (.
IsCE
~
./ ~
tAW
!sA
tPWE
~~
WE
,;'
tHO
Iso
~~
DATA IN
DATAIN VALID
~ILZWE;i
~ tHZWE
DATA OUT
(7CI62)
W///h
tHA-
DATA UNDEFINED
I- loWE
HIGH IMPEDANCE
.-
1'-
/I
-tADV-
DATA OUT
(7CI61)
)V
DATA UNDEFINED
DATA VALID
Cl62-7
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CEI, CEz = VIL.
12. Address valid prior to or coincident with CEl> CE2 transition LOW.
2-76
CY7C161
CY7C162
~YPRESS
'lYPicaJ DC and AC Characteristics (continued)
TYPICAL POWER·ON CURRENT
VS. SUPPLY VOLTAGE
3.0
i
2.5
0
2.0
~
I
30.0
J. 25.0
fil
~
~
:::;: 1.5
0
z 1.0
0.5
1.0
--
2.0
,....,.. ./
20.0
3.0
SUPPLY VOLTAGE
4.0
5.0
M
V
V
200
/
' Address
Name
Function
AS
X3
X4
A6
A7
A8
A9
AIO
All
A12
A13
AO
Al
X5
A3
X6
X7
YO
Yl
Y5
Y4
Y3
Y2
XO
Xl
A4
X2
A2
Vee = 5.0V
TA =25°C
Vee
=O.sv
Vcc=4.SV -
TA
400
=25°C
600
800 1000
CAPACITANCE (pF)
Address Designators
Address
NORMAliZED Icc fl. CYCLE TIME
1.25
/
a:
~ 10.0
5.0
...--
/
"'" 15.0
II:
0.0
0.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
Pin
Number
1
2
3
4
5
6
7
8
9
23
24
25
26
27
2-78
o.5o1'=o-----!2~0---3:=0:--,----:!40
CYCLE FREQUENCY (MHz)
CY7C161A
CY7C162A
16K X 4 Static RAM
with Separate I/O
Features
Functional Description
• High speed
-20nstAA
• CMOS for optimum speed/power
• Transparent write (7C16IA)
• Low active power
-550mW
• Low standby power
-220mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
The CY7C161A and CY7C162A are highperfonnance CMOS static RAMs organizes as 16,384 by 4 bits with separate I/O.
Easy memory expansion iSJ?!?vided by active LOW chip enables (CEl. CEz) and
three-state drivers. They have an automatic power-down feature, reducing the power
consumption by 60% when deselected.
Writing to the device is accomplishedwhen
the c~nable (CEl. eEz) and write enable (WE) inputs are both LOW. Data on
the four input pins (10 through 13) is written
Logic Block Diagram
into the memory location specified on the
address pins (Ao through A13)'
Reading the device is accomplished bytaking the chip enabl~CEl. CEz) LOW
while write enable (WE) remains HIGH.
Under these conditions the contents of the
memory location specified on the address
pins will appear on the four data output
pins.
The output pins stay in hi.!l!!:!mpedance
state when write enable (WE) is LOW
@62A only), or one of the chip enables
(CEl. CEz) are HIGH.
A die coat is used to ensure alpha immunity.
Pin Configurations
r---------------====~J_--- 10
DIP
'lbpView
r-------t===~r_---13
LCC
Vee
'lbpView
"-
0.,
s:<~~<
Aa
Ao
A,
Ao
00
A,
A2
0,
AS
~
~
Aa
~
As
A,o
Al1
A'2
A'3
10
02
I,
03
CE,
UE
13
12
03
02
0,
00
As
A,
As
10
I,
CE,
WE
1314151617
I~ ~1~I~oo
CE2
GND
3 2l1J28~6
4
A'2
25 Al1
6
24 A,o
7
23 As
8 7C182A 22 13
9
21 12
10
20 03
11
19 O2
12
18 0,
's
C161A·3
C161A·2
CE,
CE2
WE
UE
C161A-1
Selection Guide[l]
7C16IA-35
7C162A-35
100
Military
Military
Shaded area contains preliminary information.
Note:
1. Forcommereial specifications, see the CY7Cl61/CY7Cl62 datasheet.
40/20
40/20
30/20
CY7C161A
CY7C162A
~YPRESS
Electrical Characteristics Over the Operating Rangd4] (continued)
7C161A-25
7C162A-25
Parameter
Description
Test Conditions
Min.
VOH
Output IDGH Voltage
Vee = Min.,IOH = -4.0 rnA
VOL
Output wW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input IDGH Voltage
2.2
-0.5
GND.s VI.s Vee
-5
-5
Max.
7C16IA-35
7C162A-35
Min.
VIL
IIX
Input Load Current
loz
Output Leakage Current
GND .s VI.s Vee, Output Disabled
los
Output Short
Circuit Current[5]
Vee = Max., VOUT = GND
lee
Vee Operating
Supply Current
ISBl
ISB2
. Unit
V
0.4
V
Vee
2.2
Vee
V
0.8
-0.5
0.8
V
+5
-5
+5
+5
-5
0.4
Input WW VOltagd2]
Max.
2.4
2.4
+5
ItA
ItA
-350
-350
rnA
Vee = Max., lOUT = 0 rnA Military
100
100
rnA
Automatic CE
Power-Down Current
Max. Vee, CE ~ VIH,
Min. Duty Cycle = 100%
Military
40
30
rnA
Automatic CE
Power-Down Current
Max. Vee,
Military
20
20
rnA
CEl ~ Vee - 0.3V,
VIN ~ Vee - O.3V
or VIN .s 0.3V
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = S.OV
Note.:
4. See the last page of this specification for Group A subgroup testing information.
5. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
6.
Max.
Unit
10
pF
10
pF
Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481Q
5V
OUTPUTo----4~--i
R2
2550
30pF
INCLUDING
JIG AND '::'
SCOPE (a) Normal Load
-=
5V
R1481Q
OUTPUT~
5 pF
R2
2550
INCLUDING
JIG AND
SCOPE (b) High-Z Load
-=
-=
C161A'"
Equivalent to:
THEVENIN EQUIVALENT
1670
OUTPUT ..
o---",~",,---oo 1.73V
2-82
C161A-5
CY7C161A
CY7C162A
'lircYPRESS
Switching Waveforms[8]
Read Cycle No. 1[12, 13]
tRC
)r
ADDRESS
tAA
~tOHA~
DATA OUT
1fxxxxx)r
PREVIOUS DATA VALID
DATA VALID
C161A-6
Read Cycle No. 2[12, 14]
tRC
""""~
tACE
*'
~
HIGH IMPEDANCE
DATA OUT
tLZCE
tHZOE -
I
tOOE
~tLZOE-
II/,
-
.'\.
SUPPLY
CURRENT
_jtSO%
HIGH
IMPEDANCE
~ CC
_tpo
_tpu
VCC
tHZCE ....
DATA VALID
I
50%
IS8
C161A-7
Write Cycle No.1 (WE Controlled)[ll]
twc
ADDRESS
==:)
\.
~~ ~~
////////h ~
tAW
IHA-
!sA
tPWE
~~
~
Iso
)r
DATA IN
I-- IHZWE
DATA OUT
(7C162A)
DATA OUT
(7C161A)
DATA UNDEFINED
tHO
DATAIN VALID
~ lOWE"
I---
'-I
-ItZwE~1V
HIGH IMPEDANCE
II
I"
tAOY-
)
DATA UNDEFINED
DATA VALID
C161A-8
Notes:
12. WE is mGH for read cycle.
13. Device is continuously selected,
mI , CE:! = VIL.
14. Address valid prior to or coincident with
2-84
mJ, CE:! transitio~ Ww.
CY7C161A
CY7C162A
.ircYPRESS
1YPical DC and AC Characteristics (continued)
NO~EDACCESSTDdE
NORMAUZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.3
~
1.2
:::. 1.1
.............
a:
~ 1.0
.............
0.9
0.8
4.0
4.5
5.0
--
TA = 25°C
j
1.4
~
1.2
./
~ 1.0
r-
5.5
SUPPLY VOLTAGE
0.8
6.0
M
25.0
w 2.0
en
.s
20.0
...!!0
~
::!
"""-I/Oo
A,
A2
As
A,
Ao
'-'---CE
"""">---
A"
Aa
As
NC
110.
110,
110,
110.
WE
(OE)
(7C166 ONLy)
OND
WE
Cl64-1
C164-4
Selection Guide[!]
Note:
1. For military specifications, see the CY6Cl64NCY7C166A datasheet.
2-88
CY7C164
CY7C166
~YPRESS
AC Test Loads and Waveforms
OUTP:31R1481Q
OUTP~~31R1481Q
30 pF
5pF
R2
I _
255Q
INCLUDING
JIG AND SCOPE (a) Normal Load
ALL INPUT PULSES
3'OV~
GND
10%
90%
R2
I _
255Q
.s5ns-
INCLUDING
JIG AND SCOPE (b) High.Z Load
~90%.
_5ns
Cl64-6
C164·5
Equivalent to:
THEVENIN EQUIVALENT
167Q
OUTPUT ...
O _ _J·IIII
......._ _-oO 1.73V
Switching Characteristics Over the Operating Rangel6)
Description
Notes:
6. Thst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0Y, and output loading
of the specified IOIJIOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHzCE is less than
tLZCE for any given device. These parameters are gnaranteed by design and not 100% tested.
8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC
Thst Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE
2-90
LOWand'WELOW.BothsignalsmustbeLOWtoinitiateawriteand
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
CY7C164
CY7C166
~YPRESS
Switching Waveforms (continued)
Write Cycle No.2 (eE Controlled)[9, 13, 14)
twc - - - - - - - - - - - - _
--~~------~CE---------~
----r-----------~
;-------+--------
~
DATA IN _ _ _ _ _ _ _ _
DATA I/O _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _H.,;,;I.,;,G,;,,;H.,;,;IM,;,;;P.,;,;E:,:D:;,.A:;,.N.,;,G,:;E_ _ _ _ _ __
Cl64-10
Note:
14. IfCEgoesHIGHsimultaneouslywithWEHIGH,theoutputremaios
io a high-impedance state.
'IYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
1.4
ffi 1.2
lee
Ji 1.0
V
o
I1;l 0.8
:J
~
V
0.6
:/
V
~
~
~
-
ISB
4.5
5.0
5.5
0.4
25
125
AMBIENT TEMPERATURE ('G)
SUPPLY VOLTAGE M
NORMALIZED ACCESS TIME
vs SUPPLY VOLTAGE
)
1.3
)1.4
fil
1.2
0
W
N
N
1. 1
~ 1.0
0.9
0.8
4.0
...........
r---.. -....
t--TA = 25'G
~
4.5
5.0
5.5
SUPPLY VOLTAGE
M
6.0
"-
0.0
1.0
2.0
"
3.0
OUTPUT VOLTAGE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~ 140
~ 120
./
::;
ex: 1.0
-;7
0
z
0.6
Vee = 5.0V
TA= 25'G
NO~EDACCESSTUME
1.2
0.8
~
vs. AMBIENT TEMPERATURE
1.6
1.4
60
~ 2:
ISB
0.0
-55
100
~
80
o
::l
@ 40
Vee - 5.0V
VIN = 5.0V
0.2
6.0
ifi
~
~ 0.6
0.2
~
~
I1;l
z 0.4
ex:
1 120
vs. OUTPUT VOLTAGE
I-
8
C 0.8
gj
0.0
4.0
1.2
III
~ 1.0
OUTPUT SOURCE CURRENT
~
/
i3
~
60
Vee = 5.0V
~
40
o
~
1~
AMBIENT TEMPERATURE ('G)
2-92
4.0
/'
80
Z
iii
f...'"
-~
s:~ 100
"'"
M
II
/
Vee = 5.0V
TA = 25'G
I
I
20
oII
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE
M
4.0
CY7C164
CY7C166
L~YPRESS
Ordering Information
20
Commercial
25
Commercial
35
Commercial
20
Commercial
25
Commercial
35
Commercial
Document #: 38-00032-1
2-94
CY7C164A
CY7C166A
Maximum Ratings
(Above which the useful life may be impaiied. For user guidelines,
not tested.)
Storage Thmperature .................. -6S0Cto +lS0'oC
Ambient Thmperature with
Power Applied ....................... -SSoC to + 12SoC
Supply Voltage to Ground Potential ......... -O.SV to + 7.0V
Output Current into Outputs (Low) ................ 20 mA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 301S)
Latch-up Current ............................. >200 mA
Operating Range
~C Y0Itage Apflied to Outputs
Range
mHighZState ] ........................ -O.SVto +7.0V
DC Input Voitage[2] ...................... -0.5V to + 7.0V
Military[3]
Ambient
Temperature
Vee
-SSoC to + 125°C
SV± 10%
Notes:
2. Minimum voltage is equal to - 3.0V for pulse durations less than
30ns.
3. TA is the "instant on" case temperature.
Electrical Characteristics Over the Operating Range[4]
= Max., VOUT = GND
-350
rnA
100
rnA
VIR
40
rnA
Max. Vee,
CE ~ VIR - O.3V
VIN ~ Vee - O.3Vor
VIN!>. O.3V
20
rnA
lOS
Vee
Icc
Vee = Max.,
lOUT = ornA
ISBl
ISB2
= 100%
2-96
CY7C164A
CY7C166A
~YPRESS
Switching Characteristics Over the Operating Rangel4,8J
Description
Shaded area contains preliminary information.
Notes:
8. Thst conditions assume signal transition time of 5 ns or less, timing ref~
erence levels of 1.SV; input pulse levels of 0 to 3.0V; and output loading of the specified IOrJIOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than
tlZCE for any given device. These parameters are guaranteed by design and not 100% tested.
10. !HzcE and lHzWE are specified with CL = 5 pF as in part (b) in AC Thst
Loads. TIansition is measured ±500 mV from steady-state voltage.
11. The internal write time of the memory is defined by the overlap of CE
LOW and WilLOW. Both signals must be LOW to initiate a write and
eithersignaJ can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
2-98
CY7C164A
CY7C166A
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled)[1l.15. 16]
~----------------------- twe ------------------------~
ADDRESS
----~~----------~eE ----------~
WE
~
14-------------------- tSD
DATA IN
------
80
~
~
Z
Cii
60
'5
40
~
"'"
0.6
-55
a
25
125
AMBIENT TEMPERATURE (OC)
2-100
"-
1.0
2.0
"
3.0
"
4.0
OUTPUT VOLTAGE (V)
U,
Vee = 5.0V
Vee = 5.0V
TA= 25°C
20
< 140
./
::; 1.0
I---
80
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
.s 120
w 1.2
...........
a
g
'5
Vee = 5.0V
VIN = 5.0V
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
100
=>
0.4
0.2 r- ISB
f---
iE
a:
a:
~ 60
a:
SUPPLY VOLTAGE (V)
~
~
0.8
~ 0.6
z
§. 120
f-
~
15
0.0
4.0
1.0
OUTPUT SOURCE CURRENT
vS.OUTPUTVOLTAGE
~
I
20
a II
0.0
/
/
Vee = 5.0V
TA = 25°C
V
J
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
CY7C164A
CY7C166A
dJ?~
.'CYPRESS
Ordering Information
Speed
(ns)
Operating
Range
Ordering Code
~-
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
Parameter
Subgroups
VOL
1,2,3
IRe
7, 8, 9, 10, 11
Vm
1,2,3
1M
7, 8, 9, 10, 11
VILMax.
1,2,3
tOHA
7, 8, 9, 10, 11
IJX
1,2,3
7, 8, 9, 10, 11
Ioz
1,2,3
lACE
IDOE[!?]
READ CYCLE
7, 8, 9, 10, 11
los
1,2,3
WRITE CYCLE
lee
1,2,3
twe
7,8,9, 10, 11
ISB!
1,2,3
tseE
7,8,9, 10, 11
ISBl
1,2,3
tAW
7,8,9,10,11
tHA
7,8, 9, 10, 11
tSA
7,8,9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
Document #: 38-00113-D
Note:
17. 7C166Aonly.
2-102
~YPRESS
CY7C167A
Maximum Ratings
Output Current into Outputs (LOW) .............. 20. rnA
Static Discharge Voltage ........................ >2DDIV
(per MIL-STD-883, Method 3D IS)
Latch-Up CUrrent ........................... >20.0. rnA
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature .................. -65°C to + 150°C
Ambient Thmperature with
Power Applied ....................... -SSoC to +125°C
Supply Volt~ge to Ground Potential
(Pm 20. to Pm 10) ....................... -D.SV to +7.DV
DC Voltage Applied to Outputs
in High Z State ......................... -D.5V to +7.DV
DC Input Voltage ....................... -3.DV to +7.DV
Operating Range
Ambient
Temperature
Vee
DOC to +7D o C
5V ± 10%
-SSoC to + 125°C
SV ± 10%
Range
Commercial
Military[1]
Electrical Characteristics Over the Operating Rangd2]
Parameter
7C167A-15
7C167A-20
7C167A-25
Test Conditions
Min.
Min.
Min.
= Min., IOH = -4.0. rnA
Vee = Min.,
IOL = 12.0. rnA, 8.0. rnA Mil
2 ..4
Description
VOH
Output High Voltage
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
Input Low Voltagd3]
IIX
Input Load Current
GND.!'>.Vj.!'>.Vee
loz
Output Leakage
Current
GND.!'>. Vo.!'>. Vee
Output Disabled
los
Output Short
Circuit Current[4]
Vee
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = 0. rnA
Automatic CE
Power-Down Current[5]
Max. Vee,
CE.2!. VIH
ISB
Vee
Max.
2 ..4
Description
VOH
Output High Voltage
VOL
Output Low Voltage
Vee
2.2
Vee
0..8
-0..5
0..8
V
+10.
-10
+10.
-10.
+10.
-0..5
-10.
-10.
+10.
-10
+10.
ItA
ItA
-3SD
-3SD
-3SD
rnA
90.
80.
80.
60.
70.
rnA
40.
20.
rnA
40.
20.
40.
Com'l
Test Conditions
Min.
= Min., IOH = -4.0. rnA
Vee = Min.,
IOL = 12.0. rnA, 8.0. rnA Mil
2 ..4
Input Low Voltage[3]
IIX
Input Load Current
GND.!'>. VI.!'>. Vee
loz
Output Leakage
Current
GND.!'>.Vo.!'>.Vee
Output Disabled
los
Output Short
Circuit Currentl4]
Vee
lee
V cc Operating
Supply Current
Vee = Max.,
lOUT = 0. rnA
Com'l
Automatic CE
Power-Down Currentl5]
Max. Vee,
CE.2!. VIH
ISB
Max.
7C167A-45
Min.
Max.
Unit
0..4
V
V
2 . .4
0..4
V
2.2
Vee
2.2
Vee
-D.S
-10.
0..8
-0..5
0..8
V
+10
-10
+10
-10.
+10
-10
+10.
ItA
ItA
-3SD
-3SD
rnA
60.
60.
So.
So.
rnA
Mil
Com'l
20.
Mil
20
= Max., VOUT = GND
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. VIL min. = -3.DV for pulse durations less than 3D os.
V
2.2
0..8
+10.
Mil
Input High Voltage
V
Vee
Com'l
VIH
V
0..4
2.2
Mil
VIL
Unit
-0..5
-10.
= Max., VOUT = GND
Vee
Max.
2 . .4
0..4
0..4
7C167A-35
Parameter
Max.
rnA
20.
4. Duration of the short circuit should not exceed 30. seconds.
5. A pull-up resistor to Vee on the eE input is required to keep the device deselected during Vccpower-up, otherwise ISB will exceed values
given.
2-10.4
~YPRESS
CY7C167A
*
Switching Waveforms
~
U
Read Cycle No. d , 12]
tRC - - - - - - . j . . . . . - - _
ADDRESS
,
~
-
DATA OUT
tAA
.
-------t~.!
-------------~-HA----i·+!~x~X~.~---------------------PREVIOUS DATA VALID
DATA VALID
--------------------~~~~~
----------------------------
C167A-5
Read Cycle No. 2[11, 13]
tRC
~~
f-
tACE
I--- tLZCE
DATA OUT
r-- tHZCE -
---to
HIGH IMPEDANCE
L
/L
DATA VALID
!'-"
I---
VCC
SUPPLY
CURRENT
HIGH
IMPEDAN CE
/
I--tpo-
tpu -
/
50%~
50%
r-----I CC
r ' - - - I se
C167A-6
Write Cycle No.1 (WE Controlled)[lD]
twc
ADDRESS
::)(
)(
tSCE
~~ ~,
./ Wffff~
tAw
tSA
WE
tPWE
~C
~~
tHO . .
tso
DATA IN
V////////
tHA-
)(
)(
-1
-I
"'»--------«,,_____
DATAIN VALID
I---
tHZWE
-tLZWE
HIGH IMPEDANCE
DATA I/O _ _ _ _ _ _ _D_A_TA_U_ND_E_F_IN_E_D_ _ _ _ _ _ _
C167A-7
Notes:
11. WE is high for read cycle.
12. Device is continuously selected, CE = VIL.
13. Address valid prior to or coincident with rn transition LOW.
14.
Ifrn goes HIGH simultaneously with WEHIGH, the output remains
in a high-impedance state.
2-106
~YPRESS
CY7C167A
'!ypical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING
30.0,...---,r---,---r--r----,
3.0
J
2.5
::J
I
DATA I/O _______________
ILZWE
HIGH IMPEDANCE
<."-----
--.I
Cl68A 7
Write Cycle No.2
(CS Controlled) [10, 14]
IWC - - - - - - - - - - - - . ,
ADDRESS
CE ______~::::~~::=:~------lscE--------~
DATA IN
r------+-------
-------------, ~/~1F~~~~~~~::~Is~O~::::::::::~~~
DATAIN VALID
_ _ _ _ _ _ _ _ _ _ _ _::::~t~HZW~E~
...J)>-I--------....:.;H:;IG:;;H:..;I:::M:..;PE:::D::::A:N::C:::E~_______
DATA I/O ____________D:....A,;.,T,;.,'A.:U,;.,N::D:E:...:FI:,:N:ED::...._________
-__
-....
Cl68A-8
2-114
CY7C168A
CY7C169A
~YPRESS
Ordering Information
Speed Icc
(ns)
(mA)
15
115
20
25
35
45
90
Ordering Code
20
25
35
Package 1YPe
CY7C168A -15PC
P5
20-Lead (300-Mil) Molded DIP
CY7C168A -15VC
V5
20-Lead Molded SOJ
CY7C168A-20PC
P5
20-Lead (300-Mil) Molded DIP
CY7C168A - 20VC
V5
2O-Lead Molded SOJ
Operating
Range
Commercial
Commercial
CY7C168A-20DMB
D6
20-Lead (300-Mil) CerDIP
Military
70
CY7C168A - 25PC
P5
20-Lead (300-Mil) Molded DIP
Commercial
CY7C168A-25VC
V5
2O-Lead Molded SOJ
80
CY7C168A-25DMB
D6
20-Lead (300-Mil) CerDIP
Military
70
CY7C168A - 35PC
P5
20-Lead (300-Mil) Molded DIP
Commercial
CY7C168A-35VC
V5
20-Lead Molded SOJ
CY7C168A-35DMB
D6
20~Lead
(300-Mil) CerDIP
Military
CY7C168A-45DMB
D6
20-Lead (300-Mil) CerDIP
Military
Ordering Code
Package
Name
70
Speed Icc
(ns) (mA)
15
Package
Name
115
90
70
70
Package 1YPe
CY7C169A -15PC
P5
20-Lead (300-Mil) Molded DIP
CY7C169A -15VC
V5
20-Lead Molded SOJ
CY7C169A - 20PC
P5
20-Lead (300-Mil) Molded DIP
CY7C169A-20VC
V5
20-Lead Molded SOJ
CY7C169A - 25PC
P5
20-Lead (300-Mil) Molded DIP
CY7C169A - 25VC
20-Lead Molded SOJ
CY7C169A - 35PC
V5
P5
CY7C169A-35VC
V5
20-Lead Molded SOJ
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIH
VILMax.
IIX
Ioz
Icc
ISBl[lS]
ISBPS]
20-Lead (300-Mil) Molded DIP
Operating
Range
Commercial
Commercial
Commercial
Commercial
Switching Characteristics
Subgroups
Parameter
1,2,3
READ CYCLE
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
tRC
tM
!aHA
tACE
tRCS
1,2,3
1,2,3
1,2,3
tRCH
WRITE CYCLE
twc
tSCE
tAW
tHA
tSA
tpWE
tSD
tHO
Note:
15. CY7C168A only.
Document #: 38-00095-D
2-116
Subgroups
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7,8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
~YPRESS
CY7C170A
MaXimum Ratings
(Above which the ilsefullife may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ....................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.. .. . . .. .. . .. . . . .. .. . .. .. ... >200 rnA
Storage Thmperature .................. -65°C to +150°C
Ambient Thmperattire with
Power Applied ....................... -55 ° C to + 125°C
Supply Voltage to Ground Potential
(Pin 22 to Pin 21) ....................... -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to + 7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Operating Range
Range
Ambient
Temperature
Vee
Commercial
O°C to +70°C
5V:!: 10%
Militaryfl]
-55°C to +125°C
5V:!: 10%
Electrical Characteristics Over the Operating Rangel2]
7C170A-15
Parameter
Test Conditions
DeSCription
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
dutput Leakage
Current
Output Short
Circuit Current[3]
Vee Operating Supply
Current
VOH
VOL
Vrn
VIL
IIX
Ioz
los
lee
Vee
Vee
Min.
= Min., IOH = -4.0 rnA
= Min., IOL = 8.0 rnA
Max.
2.4
GND~ Vo~ Vee,
Min.
Max.
2.4
0.4
2.2
-3.0
-10
-10
GND~ Vl~ Vee
7C170A-20, 25, 35, 45
Vee
0.8
+10
+10
0.4
2.2
-3.0
-10
-10
= Max., VOUT = GND
I
Vee = Max.
lOUT = ornA
I
V
V
V
V
Vee
0.8
+10
+10
JAA
JAA
-350
-350
rnA
115
90
120
rnA
rnA
Output Disabled
Vee
Unit
Com'l
Mil
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = S.OV
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
information.
3.
4.
= 1 MHz,
Max.
Unit
10
pF
10
pF
Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
OUTP~~31Rl
481Q
30pF
R2 .
255Q
INCLUDING
JIG AND SCOPE (a) Normal Load
I _
OUTP~~31R1481Q
ALL INPUT PULSES
3'0V~
5 pF
R2
255Q
INCLUDING
JIG AND SCOPE (b) Higb.Z Load
I _
GND.$.5 ns'"
C170A-5
C170A-4
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT C)o_ _ _l;v,~.>io.?Q;;:..._-oo 1.73V
2-118
90%
==- ?cYPRESS
CY7C170A
Switching Waveforms (continued)
Read Cycle No. 2[9, 11]
tRC
~
/1{
lACS
~
HIGH IMPEDANCE
DATA OUT
KIHZOE
IOOE-
!.--ILZOE/
/
/
I-IHZCS~
/
HIGH
"IMPEDANC E
DATA VALID
ILZCS
C170A-7
Write Cycle No. 1[8, 12]
ADDRESS
____~====~~=====;~~~---I~E----~,_-------------
WE
Iso
DATA IN
ILZWE~ .
DATA 1/0
--l('"...._~-:.-:.-:.~~~~
HIGH IMPEDANCE
DATA UNDEFINED
C170A-8
Write Cycle No. 2[8, 12, 13]
IWC
ADDRESS _____~::::~~::::::~.------------~CS------------~
CS
,-------+--------
ISO
DAT~NVALID
DATA IN
9'J-____________________________________
E
- -------------------------IH-ZW-DATAI/O
DATA UNDEFINED
HIGH IMPEDANCE
C170A-9
Notes:
11. Data I/O will be high-impedance if OE = VIH.
12. Address valid prior to or coincident with CS" transition LOW,
13. IfCS" goes mGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-120
CY7C171A
CY7C172A
4K X 4 Static RAM
with Separate I/O
Features
• Automatic power-down when
deselected
• CMOS for optimum speed/power
• High speed
-tAA = 15ns
• Transparent write (CY7CI7IA)
• Low active power
-375mW
• Low standby power
-93mW
• TTL-compatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
Functional Description
written into the memory location specified
on the address pins (Ao through Au).
The CY7CI71A and CY7CI72A are highperformance CMOS static RAMs organized as 4096 by 4 bits with separate I/O.
Easy memory expansion is provided by an
active LOW chip enable (CE) and threestate drivers. They have an automatic power-down feature, reducing the power consumption by 77% when deselected.
Reading the device is accomplished by taking chip enable (CE) LOW, while write enable (WE) remains HIGH. Under these
conditions the contents of the memory location specified on the address pins will appear on the four data output pins.
Writing to the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs are both Ww. Data on the
four input/output pins (10 through 13) is
Logic Block Diagram
The o~tput pins remain in a high-impedance state when write enable (WE) is
LOW (7CI72A only), or chip enable is
HIGH.
A die coat is used to insure alpha immunily.
Pin Configurations
DIP/SOJ
ThpView
12
r-------4----<~~--- 13
00
C171A·2
C171A-1
Selection Guide
7C17IA-15
7Cl72A-15
Maximum Access Time (ns)
Maximum 0serating
Current (rnA
I
Commercial
I
Military
7C17IA-20
7Cl72A-20
7C17IA-25
7Cl72A-25
7C17IA-35
7Cl72A-35
7C17IA-45
7Cl72A-45
15
20
25
35
45
115
80
70
70
90
80
70
2-122
70
CY7C171A
CY7Cl72A
-c...~YPRESS
Electrical Characteristics Over the Operating Rangd2] (continued)
7C171A-3S
7C172A-3S
Parameter
VOH
VOL
Vrn
VIL
IIX
loz
los
lee
ISBl
ISB2
Description
Test Conditions
Min.
= Min., IOH = -4.0 rnA
= Min., IOL = 8.0 rnA
2.4
Max.
Output HIGH Voltage
Output LOW Voltage
Input HIGHVoitage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[3]
Vee
V cc
Vee Operating
Supply Current
Vee = Max.
lOUT = o rnA
Com'l
Automatic CE
Power-Down Current
Max. Vee, CE ~ Vrn
Min. Duty Cycle = 100%
Automatic CE
Power-Down Current
Max. Vee,
CE ~ Vrn - 0.3v,
VIN ~ Vee - O.3Vor
VIN.5. O.3V
Com'l
Mil
Com'l
70
70
20
20
20
Mil
20
7C171A-4S
7Cl72A-4S
Min.
0.4
2.2
-3.0
-10
-10
GND AO: _>
CE2, OE options
The CY7C182 is a high-speed CMOS static RAM organized as 8,192 by 9 bits and it
is manufactured using Cypress's high-performance CMOS technology. Access times
as fast as 25 ns are available with maximum
power consumption of only 770 m W.
The CY7C182,which is oriented toward
cache memory applications, features fully
static operation requiring no external
clocks or timing strobes. The automatic
power-down feature reduces the power
consumption by more than 70% when the
circuit is deselected. Easy memory expansion is..1!!!lvided by an active-LOW chip enable (CEl), an active HIGH chip enable
@z), an active-LOW output enable
(OE), and three-state drivers.
An active-LOW write enable signal (WE)
controls the writing/reading operation of
Logic lUock Diagram
the memory. When CEl and WE inputs
are both LOW, data on the nine data inputl
output pins (1/00 through I/Os) is written
into the memory location addressed by the
address present on the address pins (Ao
throughA12).Readingthedeviceisaccomplished by selec~the device and enabling the outputs, (CEl and DE active LOW
and CEz active HIGH), while (WE) remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins
is present on the nine data input/output
pins.
The input/outputpins remain in a high-impedance state unless the chip is selected,
~uts are enabled, and write enable
(WE) is HIGH.
A die coat is used to ensure alpha inlmunity.
Pin Configuration
DIP/SOJ
lbpView
A"
1/0 0
1/0 ,
1/02
1/03
1/04
1/05
1/06
CE,
1/0 7
~
rH-t-2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
DC Voltage ApBlied to Outputs
in High Z State 2] ....................... -O.5V to +7.0V
DC Input Voltage[2] ..................... -O.5V to +7.0V
Vee
5V± 10%
Electrical Characteristics Over the Operatirig Range
los
-300
rnA
ICC
130
rnA
ISB!
40
rnA
ISB2
15
rnA
Shaded areas contain preliminary information.
Notes:
2.
Minimum voltage is equal to - 3.0V for pulse durations less than 30 ns.
3.
2-148
Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
~YPRESS
CY7C185
Switching Characteristics Over the Operating RangdS]
~~5G~WT-~~7cW~1I
Description
Shaded areas contain preliminary information.
Notes:
5."" Thst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels ofO to 3.0V, and output loading
of the specified Iou'IOH and 30-pF load capacitance.
6. tHWE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Thst Loads. 'fransition is measured ±500 mV from steady state
voltage.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
8. The internal write time of the memory is defined by the overlap of CEI
LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going ffiGH. The
data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
2-150
~YPRESS
CY7C185
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled) [10, 12, 13]
ADDRESS
---40--------_ Ie----- tseE1 - - - - - . . I -----1-------40------------/~~--lse~ ---~'~---~~----
______________________
~~~~~~~-~ts~D~==~~~~
DATA IN
DATAjN VALID
--I
DATA I/O _ _ _ _ _ _ _ _D_A_TA_U_N_DE_F_IN_E_D_ _ _ _ _ _ _~j>--H-IG-H-IM-P_E_D_A_N_CE_---«"'_ _ _ __
IHZWE
C185-9
Note:
13. IfCEgoes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
lYpical DC and AC Characteristics
1.4
ill
~
1.2
Icc
1.0
V
C
I!l
i
0.8
NORMALIZED SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
VS. SUPPLY VOLTAGE
V
V
1.2
.. 1----
7
cw
0.2
0.2
ISB
I---
0.0
4.0
4.5
a:
a:
a
N
~ 0.4
0.6
~ 100
~
0.8
:::J 0.6
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) .... , ................... -O.5V to +7.0V
Range
DC Voltage Apglied to Outputs
in High Z State 2J ........................ -O.5V to +7.0V
DC Input Voitagel2J ...................... -O.5V to + 7.0V
Military[3J
Ambient
Temperature
Vee
-55°C to +l25°C
5V± 10%
Electrical Characteristics Over the Operating Rangel4J
Parameter
VOH
Description
Test Conditions
Output HIGH Voltage
Vee = Min.,
IOH= -4.0 rnA
V
Output LOW Voltage
Vee = Min.,
IOL= 8.0mA
V
lee
ISBI
ISB2
135
rnA
Max. Vee, CEI ~ VIH
Min. Duty Cycle = 100%
Military
40
rnA
Max. Vee,
Military
20
rnA
ah ~ Vee -
O.3V
VIN~ Vee -0.3V
orVIN~0.3V
Notes:
2. VIL (min.) = - 3.0V for pulse durations less than 30 ns.
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5.
2-156
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
CY7C185A
.?cYPRESS
Switching Charac~!,!ristics Over the Operating Rangel3,7]
~~~~~~~~~~~~~~~~--~
Description
Notes:
7. Thst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5Y, input pulse levels oro to 3.0Y, and output loading
of the specified IorJIOH and 30-pF load capacitance.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Thst Loads. 1tansition is measured ±500mV from steady-state
voltage.
9.
At any given temperature and voltage condition, tHzCE is less than
tLZCE for any given device.
10. Device is continuously selected. OE, CE = VIL. CEz = VIR.
2-158
~YPRESS
CY7C185A
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled) [13, 14, 15]
ADDRESS
CE:1
---+----------.. 14-----
tSCEl
-----1-----+-----
__-+____________- J 1 4 - - - tSCE2
----I
,----....j-----
\.t;""......---- tSD
~----D-A-I-A-IN-V-A-L-ID------
DATAIN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
DATA 1/0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.,;.H;;,.IG;;.,.H.;",;;,;IM;;,.P.;:E;:,DA.,;.N.,;.C:.:E:....._ _ _ _ _ _~<'_
____
Cl85A-9
Note:
15. IfeE goes HIGH simultaneouslywith WEIDGH, the output remains
in a high-impedance state.
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
ill
1.2
Ji 1.0
Icc
V
o
~ 0.8
~
0.6
V
1.2
7
V
o8 0.8
~ 0.6
a:
~ 0.4
gj
z
0.2
4.5
5.0
5.5
0.4
J.
w
...........
~
0.9
0.8
4.0
125
4.5
5.0
--
SUPPLY VOLTAGE CV)
20
0
0.0
1.0
~
./
0
z
0.8
'"
3.0
"
4.0
OUTPUT VOLTAGE (V)
!z
1.2
0.6
6.0
2.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.4
a: 1.0
r--
5.5
40
<,140
::;;
TA = 25°C
Vcc = 5.0V
TA= 25°C
-.............
.§. 120
0
~ 1.2
~ 1.0
25
1.6
1.3
1.1
~
o
~
60
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
a:
li
::l
g
80
AMBIENT TEMPERATURE (0G)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
~"""
~
::l
U
Vcc - 5.0V
VIN = 5.0V
SUPPLY VOLTAGE (V)
J.
~ 100
~
w
0.0
-55
6.0
1120
I-
0.2 ' - ISB
I--
ISB
0.0
4.0
------
I!l
.!!! 1.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
_
I?'
-~
./
/"
I:I!
aa::
:.:
Z
CiS
Vcc = 5.0V
1~
AMBIENT TEMPERATURE (0G)
2-160
80
V
60
20
/
Vcc = 5.0V
TA = 25°C
I
~ 40
5
o
~
v
100
/
V
o
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
~YPRESS~========================~CY~·~7C~1~85~A
Ordering Information
25
35
45
MILITARY SPECIF1CATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
Switching Characteristics
Parameter
Subgroups
READ CYCLE
VOH
1,2,3
VOL
1,2,3
tRC
7, 8, 9, 10, 11
VIH
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tOHA
7, 8, 9, 10, 11
IIX
1,2,3
tACEl
7, 8, 9, 10, 11
tACE2
7,8,9, 10, 11
tDOE
7, 8, 9, 10, 11
Ioz
1,2,3
los
1,2,3
WRlTECYCLE
Icc
1,2,3
ISBl
1,2,3
twc
7, 8, 9, 10, 11
1,2,3
tSCE!
7, 8, 9, 10, 11
tSCE2
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
ISB2
tHA
7, 8, 9, 10, 11
tSA
7,8,9,10,11
tpWE
7,8, 9, 10, 11
tSD
7,8,9, 10, 11
tHD
7, 8, 9, 10, 11
Document #: 38-00114-B
~YPRESS
CY7C187
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage 'Temperature .................. -65°C to + 150°C
Ambient Thmperature with
Power Applied ....................... -55°C to +125°C
Supply Voltage to Ground Potential
(Pin 22 to-Pin 11) ..................,..... -0.5V to +7.0V
DC Voltage ApBlied to Outputs
in High Z State ] ....................... -O.SV to + 7.0V
DC Input Voltagd2] ..................... -O.SV to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ........................ >2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Ambient
Thmperatnre
Vee
SV± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
VOH
Output HIGII Voltage
VOL
Output LOW Voltage
los
-350
-350
-350
rnA
Icc
90
80
70
rnA
ISB!
40
40
20
rnA
20
20
20
rnA
Max. Vee,
CE.2:. Vee - 0.3v,
VIN.2:. Vee - O.3V
or VIN5 0.3V
ISB2
Capacitance[5]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Thst Conditions
TA = 2SoC, f = 1 MHz,
Vee =5.0V
Max.
10
10
Unit
pF
pF
Notes:
2. VIL (min.) = - 3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted atone time. Duration of the
short circuit should not exceed 30 seconds.
4. A putt-up resistor to Vee on the CE input is required to keep the device deselected during Vee power-up, otherwise ISB witt exceed values
given.
5. Thsted initially and after any design or process changes that may affect
these parameters.
2-164
CY7C187
IzrcYPRESS
Switching Characteristics Over the Operating Range[6] (continued)
7C187-25
Parameters
Min.
Description
Max.
7C187-35
Min.
Max.
Units
35
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
25
35
ns
25
tOHA
Output Hold from Address Change
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[8,9]
tpu
CELOW to Power Up
tPD
WRITE CYCLE[9]
CE HIGH to Power Down
5
5
ns
35
25
5
5
ns
15
10
0
ns
0
ns
ns
20
20
ns
twc
Write Cycle Time
20
25
tSCE
CE LOW to Write End
20
25.
ns
tAW
Address Set-Up to Write End
20
25
ns
lHA
Address Hold from Write End
0
0
ns
lSA
Address Set-Up to Write Start
0
0
ns
tpWE
WE Pulse Width
15
20
ns
tSD
Data Set-Up to Write End
10
15
ns
tHD
Data Hold from Write End
0
0
ns
tLzwE
WE HIGH to LOW
5
tHZWE
WE LOW to High Z[1O]
ns
5
ns
7
10
ns
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
'l~
-:J
tAA
-toHA-4
DATA OUT
PREVIOUS DATA VALID
*XXXXX~ '{
DATA VALID
C187-6
Note:
11. Device is continuously selected, CE = VIL'
2-166
~YPRESS
CY7C187
1Ypical DC and AC Characteristics
NORMAliZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMAliZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
ffi
1.2
Icc
Ji 1.0
c
~ 0.8
:J
~ 0.6
/"
/"
1.2
/
V
~
1.0
8 0.8
C
~
a::
~ 0.4
0.0
4.0
4.5
5.0
SUPPLY VOLTAGE
~
ISB
25
125
J
1.4
cw
1.2
c
~
1.2
N
~~
:J
z
0.9
0.8
4.0
4.5
TA = 25'C
---
5.0
r--
5.5
SUPPLY VOLTAGE
..2-
«
a::
~
1.0
2.0
~
3.0
SUPPLY VOLTAGE
z
/
4.0
M
80
Z
60
~
Vee = 5.0V
g;
~
25
125
30.0
I
oII
5.0
"
4.0
M
-
Vee = 5.0V
TA = 25'C
/
20
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE
4.0
M
NORMAliZED Icc vs. CYCLE TIME
1.25
.,.25.0
/
20.0
/
15.0
/
10.0
5.0
/
V
iii
~ 40
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
i
w 2.0
0.0
aa::
o
fil
C
N
0.0
/
/'
0.6
-55
lJ
2 .5
,/'
~ 100
/
0.8
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
0.5
120
AMBIENT TEMPERATURE ('C)
3.0
:J
1.5
::!i
0 1.0
z
~
z
6.0
3.0
~ 140
1.0
M
2.0
OUTPUT VOLTAGE
~
1.3
"""'"-
1.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.6
..............
0.0
NORMAliZED ACCESS TIME
vs. AMBIENT TEMPERATURE
J
Vee = 5.0V
TA = 25'C
~
""-
12:
AMBIENT TEMPERATURE ('C)
1.4
1.1
::!i
a::
0 1.0
~
::l
M
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
«
80
~ 40
Vee - 5.0V
VIN = 5.0V
0.0
-55
6.0
5.5
a::
~ 60
0.2
I---
ifi 100
0.6
~ 0.4
ISB
~yo
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
I-
u
w
Z
0.2
0
------.. ~
_
200
,-
Vee=4.5V TA = 25'C
V'
V
Vee = 5.0V
TA = 25'C
Vee = 0.5V
,
400
600
800 1000
CAPACITANCE (pF)
2-168
0.501""0--.........2""0----:'-30:------'40
CYCLE FREQUENCY (MHz)
CY7C187A
64Kx 1 Static RAM
Features
Functional Description
• Highspeed
-20ns
• CMOS for optimum speed/power
• Low active power
-495mW
• Low standby power
-220mW
• TtL-compatible inputs and outputs
• Automatic power-down when
deselected
The CY7C187A is a high-performance
CMOS static RAM organized as 65,536
words by 1 bit. Easy memory expansion is
provided by an active LOW chip enable
(CE) and three-state drivers. The
CY7C187A has an automatic power-down
feature, reducing the power consumption
by 55% when deselected.
Writing to the device is accomplishedwhen
the chip enable (CE) and write enable
(WE) inputs are both Law. Data on the
input pin (DI) is written into the memory
Logic Block Diagram
location specified on the address pins (Ao
through A15).
Reading the device is accomplished bytaking the c~nable (CE) Ww, while write
enable (WE) remains HIGH. Under these
conditions, the contents of the memory location specified on the address pins willappear on the data output (DO) pin.
The output pin stays in high-impedance
state when ch~nable (eli) is HIGH or
write enable (WE) is Law.
The CY7C187A utilizes a die coat to insure alpha immunity.
Pin Configurations
DIP
Top View
Vee
A,.
A,.
A"
A'2
A"
A,.
A.,
A.,
A7
DOllT
9
WE
D,N
GND
CE
C187A·2
LCC
Top View
a~;
A2
A,.
A'3
A'2
Al1
A,.
I>"
~
I>"
A,
A7
A.,
A.,
DOUT
I~ ~ Il'JJ
Selection Guide[l]
Shaded area contains preliminary information.
Note:
1. For commercial specifications, see CY7C187 datasheet.
2-170
C187A-3
ei~~
~, CYPRESS
CY7C187A
Electrical Characteristics Over the Operating Rangel4] (continued)
7C187A-25
Parameter
lest Conditions
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagel~J
Input Load Current
Output Leakage Current
Output Short
Circuit Current[5]
Vee Operating
Supply Current
VOH
VOL
VIH
VIL
IJX
loz
los
lee
Vee - Mia., IOH - -4.0 rnA
Vee - Mia" IOL - 8.0 rnA
Min.
2.4
I Mil
2.2
3.0
-5
5
GNDSVI.$.Vee
GND .$. Vo "" Vee, Output Disabled
Vee - Max., VOUT - GND
Vee - Max., lOUT - 0 rnA
ISB!
Automatic CE
Max. Vee, CE .;i VIH
Power-Down Current[6]
ISB2
Automatic CE
Power-Down Currentl6]
Max. Vee, CE~ Vee - 0.3v,
VIN ~ Vee - O.3V or
VIN.$.O.3V
Max.
7C187A-35
Min.
Unit
Max.
2.4
0.4
Vee
0.8
+5
+5
-350
2.2
3.0
-5
5
V
V
V
V
0.4
Vee
0.8
+5
+5
-350
rnA
fAA
fAA
Mil
80
80
iliA
Mil
40
30
rnA
Mil
20
20
rnA
Capacitance[7]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
= 25°C, f = 1 MHz,
Vee = 5.0V
TA
Max.
10
10
Unit
pF
jJF
Note:
7.
'Iested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481Q
R1481Q
5V~ R2
5V
30 pF
I=
ALL INPUT PULSES
OUTPUT~--~~--i
OUTPUT
255Q
INCLUDING
JIG AND
SCOPE (a) Normal Load
=
I
R2
5 PF
255Q
INCLUDING .
JIG AND
SCOPE (b) High-Z Load
= =
C187A-4
Equivalent to:
THEVENIN EQUIVALENT
167Q
OUTPUT~1.73V
2-172
3.0V~
90%
GND
,.;.5 ns
~
,.;.5 ns
C187A-5
~YPRESS
CY7C187A
Switching Waveforms
Read Cycle No. d 12, 13]
tRc
)~
ADDRESS
~
tM
I---toHA~
DATA OUT
*XX) {
PREVIOUS DATA VALID
DATA VALID
C187A-6
Read Cycle No. 2[12, 14]
tRC
~ .....
~
tACE
I--- tHZCE
i LZCE
HIGH IMPEDANCE
DATA OUT
Vee
SUPPLY
CURRENT
_=f50%
'////
"-
DATA VALID
~"""
HIGH
IMPEDANCE
/
I--
-tpu
tpo
5~
0% CC
I
ISB
C1B7A-7
Write Cycle No.1 (WE Controlled)[ll]
twc
ADDRESS
~~
--./
(
tsCE
~~ ~ "-
./Wffffffi V///////
tAW
tSA
/f-
tso
'f
DATA IN
tHO
DATAJN VALID
~tHzwE DATA OUT
tHA-
I - - - tPWE
~~~~
"-
DATA UNDEFINED
~tLZWE;1V
HIGH IMPEDANCE
I"
Cl87A-8
Noles:
12. WE is mGH for read cycle.
13. Device is continuously selected, CE = VIL.
14. Address valid prior to or coincident with CE transition LOW.
2-174
fiircYPRESS
CY7C187A
'J.Ypical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING
3.0
30.0
j 2.5
25.0
fa
N
~
a:
.,-
-
15.0
l!:l
10.0
13
0
z 1.0
0.5
~
0.0
0.0
1.0
2.0
3.0
/
4.0
5.0
5.0
/
/
SUPPLY VOLTAGE M
1 1-
200
400
Address
Function
AO
Al
X3
1
X4
2
A2
X5
A3
X6
X7
Y7
3
4
5
6
A7
A8
Y6
Y2
Y3
7
8
14
A9
AI0
All
Yl
YO
Y4
15
16
17
A12
A13
A14
A15
Y5
XO
Xl
18
A6
X2
Truth Table
CE
WE
600
800 1000
CAPACITANCE (pF)
Address
Name
AS
~
a:
Address Designators
A4
~
Vee=4.5V TA = 25°C
/
0.0 0
Pin
Number
19
20
21
Input/Output
Mode
H
X
HighZ
L
H
Data Out
Read
L
L
Data In
Write
Vee = 5.0V
TA = 25°C
Vee = 0.5V
o
/
~
1.5
.~
/
]: 20.0
2.0
NOI,{MALIZED Icc vs. CYCLE TIME
1.25
DeselectIPower-Down
2-176
oz
0.501-':0-----c2':-::0,-----:!-30::------'40
CYCLE FREQUENCY (MHz)
CY7C188
32K X 9 Static RAM
Features
Functional Description
• High speed
-20ns
The CY7C188 is a high-performance
CMOS static RAM organized as 32,768
words by 9 bits. Easy memory expansion is
provided by an active-LOW chip enable
• Automatic power-down when
deselected
• Low active power
-965mW
• Low standby power
-220mW
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Easy mem~ expansion with CE.,
C~, and OE features
(CEl),anactive-HIGHchipena~CE2)'
an active-LOW output enable (OE), and
three-state drivers. The device has an automatic power-down feature that reduces
power consumption by more than 75%
when deselected.
Writin!l!<> the device is acconlJl!ished by
taking CEl and write enable (WE) inputs
LOW and CE2 input HIGH. Data on the
nine I/O pins (1/00 - I/Os) is then written
into tbe location specified on tbe address
pins (Ao - A14)·
Logic Block Diagram
Reading from the device is accomplished
~aking CE l and DE LOW while forcing
WE and C~ HIGH. Under these conditions, the contents of the memory location
specified bytbe address pins will appear on
tbe I/O pins.
The nine input/output pins (1/00 - I/Os)
are placed in a high-impedance state when
tbe device is deselected (eEl HIGH or
CE2 LOW), the outputs are disabled (OE
HIGH), or during a wri~eration (CEl
LOW, CE2 HIGH, and WE LOW).
The CY7C188 is available in standard
300-mii-wide DIPs and SOJs.
A die coat is used to ensure alpha immunity.
Pin Configuration
DIP/SOJ
ThpView
Vee
A,.
CE,
WE
,..,
A'3
1/°0
AlO
An
I/O,
OE
A12
1/°2
1/°3
CE,
1/00
I/o,
I/O,
1/0 3
GND
'I/O.
I/O,
I/O.
1/0 5
I/O.
1/0 4
1/05
1/°6
CE,
CE2
1/07
WE
OE
1/°8
C168-1
Selection Guide
2-178
C188-2
CY7C188
QPRESS
Capacitance[5]
Parameter
Description
CIN: Addresses
Test Conditions
Unit
6
pF
8
pF
8
pF
TA
CIN: Controls
CoUT
Max.
= 25°C, f = 1 MHz,
Vee = S.OV
Input Capacitance
Output Capacitance
Note:
.
5. Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms[6, 7]
R14810
R14810
OUTP~~31
OUTPUT
5V31
30 pF
INCLUDING
JIG AND
. SCOPE
R2
I _
5pF
2550
-
-
3'OV~
10%
90%
R2
2550
INCLUDING _
JIG AND SCOPE
(a)
Equivalent to:
I
ALL INPUT PULSES
_
C188-3
(b)
THEVENIN EQUIVALENT
1670
OUTPUT 0
... - -....."""'....- _ . 0 0 1.73V
2-180
GND
s3ns ....
~
10%
....
s3ns
C188-4
'~YPRESS
CY7C188
Switching Waveforms
Read Cycle No. 1[11, 12]
ADDRESS
€
--~
DATA OUT
PREVIOUS DATA
*-
IRC
1M
V~~~~ JXX
1
*===============D=A=:rA==VA=L=ID============
Cl88-5
Read Cycle No.2 (Chip-Enable Controlled)[12, 13, 14]
IRC
~'\.
/ftACE
*
~K.
DATA OUT
tOOE
fe--tLZOEHIGH IMPEDANCE
1///
'~~
~tHZCE
DATA VALID
~~"
tLZCE
_tpu
VCC
SUPPLY _ _ _ _ _
CURRENT
I
/
I--tpo
~50%
HIGH
IMPEDANCE
~ CC
I
50%
.
IS8
C188-6
Write Cycle No.1 (WE Controlled)[9, 14, 15, 16]
~-----------------------twc----------------------~
ADDRESS
~------tPWE
WE
----------------~~~
--------"""'*I
,----------------
r;::::::::~t~so~::::::::~!:~~tHO
DATAI/O
DATAIN VALID
C188-7
Noles:
11. Device is continuously selected. QI;;, CE = V!L.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition Ww.
14. TIming parameters are the same for all chip enable signals (eEl and
CE2), so only the timing for CEI is shown.
15. Data I/O is high impedance ifOE: = VIH.
16. lfCE goes HIGH simultaneonslywith WE HIGH, the output remains
in a high-impedance state.
2-182
·~YPRESS
CY7C188
'fruth Thble
CE
WE
OE
H
X
X
HighZ
L
H
L
Data Out
Read
Active (Icc)
L
L
X
Data In
Write
Active (Icc)
L
H
H
HighZ
Deselect, Output Disabled
Active (Icc)
Input/Output
Mode'
Power
DeselectIPower-Down
Standby (ISH)
Ordering Information
Speed
(ns)
20
25
Ordering Code
CY7C188-20PC
CY7C188-20YC
CY7C188-25PC
CY7C188-25YC
.
35
'
"
Package
Name
P31
Y32
P31
Y32
"
CY7C188-35PC
CY7C188-35YC
-
Package 1YPe
32-Lead (300-MiI) Molded DIP
32-Lead (300-MiI) Molded SO]
32-Lead (300-MiI) Molded DIP
32-Lead (300-MiI) Molded SOJ
,
P31
Y32
"
" ,
,,'
'
-
Operating
Range
Commercial
Commercial
, ,
32-Lead (300-MiI) Molded DIP
32-Lead (300-MiI) Molded SOJ
'.
Commercial
,
Shaded areas contam prehmmary mformation.
MILITARY SPECIFICATIONS
Group A Subgroup Thsting
Switching Characteristics
Parameter
DC Characteristics
Subgroups
READ CYCLE
Parameter
Subgroups
tRC
YOH
1,2,3
tAA
7, 8, 9, 10, 11
VOL
1,2,3
tORA
7,8,9, 10, 11
YIH
1,2,3
tACE
7, 8, 9, 10, 11
YILMax.
1,2,3
tDOE
7, 8, 9, 10, 11
IIX
1,2,3
Ioz
1,2,3
twc
7,8, 9, 10, 11
Icc
1,2,3
tSCE
7,8, 9, 10, 11
ISBl
1,2,3
tAW
7,8, 9, 10, 11
ISH2
1,2,3
tRA
7,8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WRITE CYCLE
tSD
7, 8, 9, 10, 11
tHD
7,8,9, 10, 11
Document #: 38-00220-C
2-184
CY7C191
CY7C192
~YPRESS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to +150°C
Ambient 'Thmperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ................... .' ... -O.SV to + 7.0V
DC Voltage Apglied to Outputs
in High Z State 1] .................. -O.5V to Vee + O.5V
DC Input Voltagel1] ................ -O.5V to Vee + O.5V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
Military[2j
Ambient
Thmperature
Vee
O°Cto +70°C
5V± 10%
-55°C to + 125°C
5V± 10%
Electrical Characteristics Over the Operating Range[3]
Shaded area contains preliminary information.
Notes:
1. Minimum voltage is equal to - 2.0V for pulse durations of less than
20ns.
2. TA is the "instant on" case temperature.
3.
4.
See the last page of this specification for Group A subgroup testing information.
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
CY7C191
CY7C192
1lrcYPRESS
Switching Characteristics Over the Operating Rangd3,7j
~7~C~1~91~-~1~S-r~~~~~~~~~~~~~------~--~
7C192-1S
tOHA
ns
tACE
ns
tLZCE
ns
tHZCE
ns
tpu
ns
ns
ns
ns
ns
ns
tHD
3
tLZWE
3
3
ns
3
tHZWE
7
10
11
15
tDWE
15
20
25
30
15
ns
ns
tADV
tDCE
ns
15
Shaded area contains preliminary information,
Notes:
7, Test conditions assume signal transition time of 3 ns or less for -12
and -15 speeds and 5 ns or less for -20 through -45 speeds, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHZWE is less than tLZWE for any given device. These parameters are guaranteed by design and not 100% tested.
20
25
35
45
ns
tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC
Thst Loads. 'fransition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap ofCE
LOW and WIlLOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
9.
CY7C191
CY7C192
Switching Waveforms (continued)
Write Cycle No.2 (CE ControIled)[1o, 14J
~-----------------------Iwc------------------------~
ADDRESS
14--------
lSA ---------.-1000---- tsCE -------.I
__________________________~~~~~-=-=-=-=-=--~IS~D~:::::j~~~
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
(7C192)
DATA VALID
14------ IADV -------~
C191-11
1YPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMAIJZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
~ 1.2
11 1.0
o
Ii;l
I
0.8
0.6
Icc
V
V
1.4
V
V
m
:!!
VIN = 5.0V
TA = 25°C
IS8
0.0
4.0
4.5
I. . . . . .
--
I
I
5.0
5.5
Ii;l
0.8
~
0.6
Icc
~
~
Vee = 5.0V VIN = 5.0V
0.2
25
!5u
80
w
~
60
5
40
(Jl
IS8
0.0
-55
6.0
Z 100
"
~ 0.4
~yo
125
~
o~
f'-......
0.9
0.8
4.0
4.5
--
~
1.4
~
I---
5.5
SUPPLY VOLTAGE
M
6.0
z
1.2
~
~
0.8
0.6
-55
2.0
3.0
"
4.0
M
v
w 100
::<
a: 1.0
0
120
If
«
TA =' 25°e
5.0
1.0
~140
0
.............
0
0.0
OUTPUT VOLTAGE
~
j.
1.3
~ 1.0
~
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.6
1.4
Vcc = 5.0V
TA = 25°C
............
20
NORMAIJZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
I: :
~
AMBIENT TEMPERATURE (Oe)
SUPPLY VOLTAGE M
j.
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
f-
'-.......
11o 1.0
z 0.4
0.2
1.2
~
Vec = 5.0V
25
125
AMBIENT TEMPERATURE (OC)
2-190
a
80
Z
60
~
Cii
~
40
o
20
/
1/
/
oV
0.0
Vcc = 5.0V
TA= 25°C
J
1.0
1
2.0
3.0
OUTPUT VOLTAGE
M
4.0
CY7C191
CY7C192
~YPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7,8,9,10,11
VIH
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
toHA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
Irx
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
1,2,3
Parameter
Subgroups
READ CYCLE
WRITE CYCLE
Document #: 38-00076-J
twe
7,8,9, 10, 11
tSCE
7,8,9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7,8,9,10,11
tpWE
7, 8, 9, 10, 11
tSD
7,8,9,10,11
tHO
tAWE[15]
7,8, 9, 10, 11
tADv[15]
7, 8, 9, 10, 11
Note:
15. CY7C191 only
2-192
7,8,9, 10, 11
~YPRESS
CY7C193
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................... -65°C to +150°C
Ambient Temperature with
Power Applied ........................ -55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................ -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ..................... -O.5V to Vee + O.5V
DC Input Voltage . . . . . . . . . . . . . . . . .. - O.5V to Vee + O.5V
Output Current into Outputs (LOW) ............... 20 rnA
Static Discharge Voltage ........................ >2001V
(per MlL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Range
Cummercial
Ambient
Thmperature
Vee
O°C to +70°C
5V±5%
Electrical Characteristics Over the Operating Range
7C193-20
Pammeter
Description
Thst Conditions
VOR
Output HIGH Voltage
Vee = Min., lOR = -4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input HIGH Voltage
Min.
Max.
Unit
0.4
V
2.2
Vee
+O.3V
V
2.4
V
VIL
Input LOW Voltage
-0.5
0.8
V
IIX
Input Load Current
GND S. VI S. Vcc
-5
+5
loz
Output Leakage Current
GND S. Vos. Vee, Output Disabled
-5
los
Output Short Circuit Currentl1]
Vee = Max., VOUT = GND
lee
Vee Operating Supply Current
Vee = Max., lOUT = 0 rnA, f = fMAX '= litRe
+5
J.IA.
J.IA.
-300
rnA
160
rnA
Capacitance[2]
Pammeter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Thst Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
Unit
8
pF
8
pF
AC Test Loads and Waveforms
R1481Q
R1481Q
5V~
OUTPUT
30 pF
I
INCLUDING _
JIG AND SCOPE
5V~
OUTPUT
R2 255Q
_
-
5 pF
I
INCLUDING _
JIG AND SCOPE
(a) Normal Load
ALL INPUT PULSES
30V
R2 255Q
.
GND
.
~O%
Sl, -
_
-
(b) High-Z Load
~
10%
-
st!
Cl934
Cl93-3
Equivalent to:
THEVENIN EQUIVALENT
16m
OUTPUT ().o- -....N.Io----oO 1.73V
Notes:
1.
Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2. Thsted ioitially and after any design or process changes that may affect
these parameters.
2-194
Ji#~
CY7C193
~ CYPRESS
Switching Waveforms (continued)
Write Cycle
t---~ tcYC - - - I O j
eLK
ADDRESS
DATA
C193·6
OETiming
DATA
High-Z
VALID DATA
(
VALID DATA
tLZOE
f.--tHZOE-
-tOOE-
C193--7
2-196
CY7C193
'JYpical DC and AC Characteristics (continued)
NORMALIZED ACCESS TIME
AMBmNT TEMPERATURE
NO~EDACCESS~E
YS. SUPPLY VOLTAGE
YS.
.s 120
J. 1.4
1; 1.3
.9
1.1
..............
a:
0
z 1.0
............
0.9
0.8
4.0
4.5
-- -
~ 1.2
5.0
5.5
a: 1.0
0
z
0.8
~
0.6
-55
6.0
25
~ 2.0
/
1:!i 15.0
1.5
m
1.0
2.0
----
3.0
./
4.0
SUPPLY VOLTAGE (V)
/
oV
5.0
c 10.0
5.0
V
1/
0.0 0
200
1/
Vee = 5.0V
TA = 25'C
t
20
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED Icc YS. CYCLE TIME
1.25,.---,----,----,
Jl
fill.00
/
()
/
0.0
.....-
1; 20.0
V
60
~ 40
125
25.0
/
80
TYPICAL ACCESS TIME CHANGE
OUTPUT LOADING
t
2.5
O. 0
0.0
Cil
~
30.0
0.5
Z
YS.
3.0
a:
~ 1.0
lo:
AMBIENT TEMPERATURE ('C)
TYPICAL POWER-ON CURRENT.
vs. SUPPLY VOLTAGE
~
Vee = 5.0V
aa:
o
SUPPLY VOLTAGE (V)
i
~
«
::;;
TA= 25'C
/
!z
~ 100
cw
c 1.2
w
~
«
::;;
<" 140
1.6
1.4
OUTPUT SINK CURRENT
OUTPUT VOLTAGE
YS.
~
a:
/
Vee = 4.5V TA = 25'C
400
600
800 1000
CAPACITANCE (pF)
~ 0.751----l---,~=--+_---j
20
30
40
CYCLE FREQUENCY (MHz)
Ordering Information
(ns)
Operating
Range
20
Commercial
Speed
Document #: 38-00254-A
2-198
CY7C194
CY7C195
CY7C196
.rcYPRESS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature .................. -65°C to + 150°C
Ambient Thmperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential ........ -O.5V to +7.0V
DC Voltage ApBlied to Outputs
in High Z State I] .................. -O.5V to Vee + 0.5V
DC Input Voltagel l ] ................ -O.5V to Vee + O.5V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STO-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Range
Commercial
Military[2]
Thmperature
Vee
O°Cto +70°C
5V± 10%
-55°C to + 125°C
5V± 10%
Electrical Characteristics Over the Operating Rangel3]
Shaded area contains preliminary information.
Noles:
1. Minimum voltage is equal to - 2.0V for pulse durations of less than 20
ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group Asubgroup testing information.
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
5. A pull-up resistor to Vcc on the rn input is required to keep the device
deselected during Vcc power-up, otherwise IsB will exceed values given.
4.
2-200
CY7C194
CY7C195
CY7C196
~YPRESS
Switching Characteristics Over the Operating Rangef3, 8]
~7~C~1~~~-~1~5~~~~-r~~~~~~~~------~--~
7C195-15
7Cl96-15
Description
15
20
25
35
flS
7
9
10
16
flS
tHZOE
3
0
tLZOE
3
ns
9
7
flS
tLZCEi>
tLZCEz
flS
tHzCEi>
tHZCE2
flS
tpu
flS
flS
25
35
ns
o
o
ns
o
o
ns
ns
tHD
3
3
tLZWE
7
Shaded area contains preliminary information.
Notes:
8. Thst conditions assume signal transition time of 3 ns or less for -12
and -15 speeds and 5 os or less for - 20 and slower speeds, timing reference levels of 1.5V, input pulse levels ofo to 3.0V, and output loading
of the specified IOlJ10H and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHzWE is less than tLZWE for any given device.
10. tHZOE, tHzCE, and tHzWE are specified with CL = 5 pF as in part (b)
of AC Thst Loads. Transition is measured ±500 mV from steady-state
voltage.
10
o
3
13
o
3
15
o
ns
20
ns
11. The internal write time of the memory is defined by the overlap of CEl
LOW, ~ LOW, and WE LOW. All signals must be LOW to initiate
a write and any signal can terminate a write by going IDGH. The data
input set-up and hold timing should be referenced to the rising edge of
the signal that terminates the write.
2-202
CY7C194
CY7C195
CY7C196
dJl~
:'CYPRESS
Switching Waveforms (continued)
Write Cycle No.2 (WE Controlled, OE IDGH During Write for 7C195 and 7C196 only)[ll, 15, 16]
twe----------------------~
GEl
CE2 (7C196)~~~~~~......----------------....,t."Lt.~::L.CL.CL.CL.LL.
~-----------------~W--------------------~.-
WE ---:....---......;:;,;,..--.......oh,.......,.... ,.1----
14-----
tpWE
- - - - - + I /""_ _ _ _ _ _ _ __
tSD ---------.,j..,~.! tHD
DATA I/0L.~~L~~L~~/t--r'-_ _ _ _~D~A~I~A~V~AL~I~D_ _ _ _~-------C194-12
Write Cycle No.3 (WE Controlled, OE LOW) [16, 17]
ADDRESS
CEl
CE2 (7C196)
~~~~~~"--
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..L..C£.~¥-'::L.C£.~Lt.~
C194-11
1YPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
VS. SUPPLY VOLTAGE
1.4
5l
~
1.2
lee
1.0
V
o
~ 0.8
:J
:1!
rr
0.6
[7
./'
0.2
0.0
4.0
1.2
~
1.0
lee
I.........
5.5
SUPPLY VOLTAGE (V)
6.0
iii 100
'-......
~
::l
()
............
0.6
0.0
-55
80
~ 60
f::::
rr
::l
~ 0.4
0.2
I
5.0
~
I-
..............
~ 0.8
ISB
4.5
~
o
VIN = 5.0V - TA = 25°C
~ 0.4
11.20
1.4
V
OUTPUT SOURCE CURRENT
vs.OUTPUTVOLTAGE
~
Vee = 5.0V VIN = 5.0V
ISB
25
125
AMBIENT TEMPERATURE (0G)
2-204
g
40
!:i
20
o~
0
0.0
1.0
"2.0
Vee = 5.0V
TA = 25°C
'"
3.0
OUTPUT VOLTAGE
'"
M
4.0
CY7C194
CY7C19S
CY7C196
20
25
35
45
20
Commercial
25
35
~~~~~---+--~-+~--~~~~----------~
Shaded areas contain preliminary information.
2-206
Commercial
CY7C197
256K X 1 Static RAM
Features
Functional Description
• Highspeed
-12ns
• CMOS for optimum speed/power
• Low active power
-880mW
• Low standby power
-220mW
• TIL-compatible inputs aud outputs
• Automatic power-down when
deselected
The CY7C197 is a high-performance
CMOS static RAM organized as 256K
words by 1 bit. Easy memory expansion is
provided by an active LOW chip enable
(eE) and three-state drivers. The
CY7C197 has an automatic power-down
feature, reducing the power consumption
by 75% when deselected.
Writing to the device is accomplished when
the chip enable (eE) and write enable
(WE) inputs are both LOW. Data on the
input pin (DIN) is written into the memory
Logic Block Diagram
location specified on the address pins (Ao
through A17)'
Reading the device is accomplished bytaking chi~able (eE) LOW while write enable (WE) remains HIGH. Under these
conditions the contents of the memory location specified on the address pins will appear on the data output (DOUT) pin.
The output pin stays in ash-impedance
state when ch~nable (CE) is HIGH or
write enable (WE) is LOW.
The CY7C197 utilizes a die coat to ensure
alpha immunity.
Pin Configurations
LCe
DIP/SOJ
'lbpView
'lbpView
Uo--
Ao
A'3
A"
A,.
A,e
A"
Ao
A,
Ao
As
A:!
DO
Dour
Vee
A'7
A,e
A,.
A"
A'3
A'2
All
A'0
As
WE
DIN
GND
CE
C197-2
CE
WE
C197-1
Selection Guide
2-208
~<.f-:9<
NC
A:!
A:!
Ae
Ae
A7
As
Dour
NC
3 2l1J28~
4
25
5
6
24
7
23
8
22
9
21
10
20
11
19
12
18
1314151617
NC
A,B
A15
A"
A13
A'2
An
A'0
NC
I~~I~~:
0197-3
.~YPRESS
Electrical Characteristics Over the Operating Rangd3] (continued)
7C197-20
Parameter
Description
Test Conditions
Min.
VOH
Output HIGH Voltage
Vcc = Min., IOH = -4.0 rnA
VOL
Output LOW Voltage
Vee=Min·IIOL=8.0rnA IMil
Input HIGH Voltage
VIL
Input LOW Voltagdlj
Irx
Input Load Current
loz
Min.
Unit
Max.
2.4
2.4
I IOL = 12.0 rnA I Com'l
Vrn
7C197-25, 35, 45
Max.
V
0.4
0.4
V
0.4
0.4
V
V
2.2
Vee
+ O.3V
2.2
Vee
+ 0.3V
-0.5
0.8
-0.5
0.8
V
GND,::;,VI,::;,Vee
-5
+5
-5
+5.
Output Leakage Current
GND .::;, Va.::;, Vee, Output Disabled
-5
+5
-5
los
Output Short
Circuit Current[4]
Vee = Max., VOUT = GND
+5
-300
!lA
!lA
n1A
Icc
Vee Operating
Supply Current
Vee = Max., lOUT = 0 rnA, I Com'l
f = fMAX = lItRe
I Mil
135
95
rnA
150
105
Automatic CE Power Down Max. Vee, CE~ Vrn, VIN ~ Vrnor
Current-TIL Inputs[5]
VIN .::;, VIL, f = fMAX
Automatic CE Power·Down Max. Vee, CE ~ Vee - 0.3v,
Current-CMOS Inputs[5j VIN ~ Vee - O.3V or VIN < O.3V
30
30
rnA
15
15
rnA
ISBl
ISB2
-300
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
Unit
8
pF
10
pF
AC Test Loads and Waveforms[7]
'1: cxn>::,,, '1:
R1 3290
R1 3290
0""':: '" "II
ALL INPUT PULSES
II
2020
2550
INCLUDING _
_ (2550 MIL) INCLUDING _
_ (2550 MIL)
JIG AND JIG AND SCOPE (a) Normal Load
SCOPE (b) Higb.Z Load
~O%
10%
90%
3.0V
GND - - 51,
C197-4
Equivalent 10:
THEvENIN EQUIVALENT
1250
OUTPUT OoO---'¥"•.,.'---(,
cr
A13
1/°0
1/0 7
1/0,
1/0.
1/0.
I/O.
1/0 3
1/02
C199·2
LCC
1/0 3
'lbp View
1/0 4
u~JlI~
1/0 5
1/0 6
As
As
AlO
A"
A12
A13
1/07
C1Q9.1
A,.
I/O,
I/O,
3 2l1J2B~6
4
5
6
25
8
9
10
11
12
22
24
23
7
21
20
19
18
1314151617
~~g'g~
2-216
tv.
1+0
A.
tiE
f>(,
cr
1/0 7
I/O.
C199-3
~YPRESS
CY7C199
Electrical Characteristics Over the Operating Rangd3] (continued)
Pammeter
loz
Description
lest Conditions
Output Leakage Current
lee
ISBl
ISB2
Power-Down CurrentTIL Inputs
Automatic CE
Power-Down CurrentCMOS Inputs
Max. Vee,
CE~ Vee - O.3V
VIN ~ Vee - 0.3V
or VIN .::;, 0.3\1, f = 0
Electrical Characteristics Over the Operating Rangd3] (continued)
7C199-20
Parameter
Description
lest Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
2.4
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input HIGH Voltage
Max.
7Cl99-25
Min.
2.4
0.4
2.2
Max.
7C199-35,4S
Min.
Max.
2.4
0.4
Vee
+O.3V
2.2
Vee
+O.3V
2.2
Unit
V
0.4
V
Vee
+O.3V
V
VIL
Input LOW Voltage
-0.5
0.8
-3.0
0.8
-3.0
0.8
V
IIX
Input Load Current
GND,::;,VI,::;,Vee
-5
+5
-5
+5
-5
+5
loz
Output Leakage Current
GND,::;,VI,::;,Vee,
Output Disabled
-5
+5
-5
+5
-5
+5
fAA
fAA
los
Output Short
Circuit Current[4]
Vee = Max., VOUT = GND
lee
Vee Operating Supply
Current
Vee - Max.,
lOUT = ornA,
f = fMAX = litRe
ISBl
ISB2
Automatic CE
Power-Down CurrentTIL Inputs
Max. Vee, CE ~ VIH,
VIN~ VIH
or VIN .::;, VIL, f = fMAX
Automatic CE
Power-Down CurrentCMOS Inputs
"CE~ Vee - O.3V
-300
-300
-300
rnA
rnA
Com'l
150
150
140
L
100
100
100
Mil
170
150
150
L
130
130
130
30
30
25
15
15
15
L
rnA
Max. Vee,
Com'l
15
15
15
VIN ~ Vee - 0.3Vor
VIN .::;, 0.3\1, f=O
L
500
500
500
fAA
Mil
15
15
15
rnA
L
5
5
5
Note:
4. Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
2-218
rnA
CY7C199
.rcYPRESS
Switching Characteristics Over the Operating Rangd3• 8]
Shaded area contains preliminary information.
Notes:
8. Thst conditions assume signal transition time of3 ns or less for -12 and
-15 speeds and 5 ns or less for - 20 and slower speeds. timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than
tLZCE. tHZOE is less than tLZOE. and tHZWE is less than tLZWE for any
given device.
10. tHWE. tHZCE. and tHzWE are specified with CL = 5 pF as in part (b)
of AC Thst Loads. Thansition is measured ±500 mV from steady-state
voltage.
11. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate awrite and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge ofthe signal
that terminates the write.
12. The minimum write cycle time for write cycle #3 (WE controlled. OE
LOW) is the sum of tHZWE and tSD'
2-220
~YPRESS
CY7C199
Switching Waveforms (continued)
Read Cycle No. 2[14, 15]
CE
IRC
~K.
/'{.
lACE
~
~
IDOE
-tLZOEDATA OUT
HIGH IMPEDANCE
ILZCE
VCC
SUPPLY
CURRENT
!---Ipu
___________
~'~
I
1///
., ."
I--- tHZCE
DATA VALID
HIGH
IMPEDANCE
/
I---tpD
~CC
1'--I
;ft50%
50%
ISB
C199·9
Write Cycle No.1 (WE Controlled)[ll, 16, 17]
~-----------------------IWC----------------------~
ADDRESS
~------------------~W--------------------~~--
WE --'""'--------ri-~~
~------IPWE
---------.I
~--------
~---------~D----------~.-~IHD
DATAI/O
DATAIN VALID
C199·10
Write Cycle No.2 (CE Controlled)[ll, 16, 17]
~------------------------IWC------------------------~
ADDRESS
---+----------------------,
!oo-----ISCE
------I /---------1--------
~--------------------~W--------------------~----
""1-:-------- tSD --------to...
DATA I/O ---------------I 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Supply Voltage on Vee Relative to GND[I] . -O.5V to +7.0V
DC Voltage Apglied to Outputs
in High Z State 1] .........••.•..... -O.5V to Vee + O.5V
DC Input Voltagd 1] ..•....••....... -O.5V to Vee + O.5V
Current into Outputs (LOW) ..................... 20 rnA
Ambient
Temperatnre[Z]
Vee
O°Cto + 70°C
5V ± 10%
-55°C to + 125°C
5V ± 10%
Range
Commercial
Military
Electrical Characteristics Over the Operating Rangd3]
Parameter
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
VOH
VOL
VIH
Input LOW
Voltagd 1]
InputLoadCurrent
Output Leakage
Current
Output Short
Circuit Currentf4]
Vee Operating
Supply Current
VrL
Irx
loz
los
Icc
Aotomatic CE
Power-Down
Current
-TIL Inputs
ISBI
Automatic CE
Power-Down
Current
- CMOS Inputs
ISBZ
7CIOOl-12
7CIOO2-12
7ClOOl-15
7CIOO2-15
7CIOOl-20
7ClOO2-20
7CIOOl-25
7ClOO2-25
Test Conditions
Min.
Min.
Min.
Min.
Vee = Min.,
IOH= -4.0 rnA
Vee = Min., IOL = 8.0 rnA
2.4
Max. Vee,
-0.3
Vee
+0.3
0.8
-1
-5
+1
+5
Com'l
2.2
Max.
2.4
0.4
-0.3
Vee
+0.3
0.8
-1
-5
+1
+5
2.4
0.4
2.2
Max.
2.2
Unit
V
0.4
V
V
V
-0.3
Vee
+0.3
0.8
-0.3
Vee
+0.3
0.8
-1
-5
+1
+5
-1
-5
+1
+5
iJ.A.
iJ.A.
-300
-300
-300
-300
rnA
165
155
140
130
rnA
165
150
140
40
30
30
40
30
30
2
2
2
2
2
2
Mil
Com'l
Max.
2.4
0.4
2.2
GND.s Vr.s Vee
GND.s VI.s Vee,
Output Disabled
Vee = Max.,
VOUT=GND
Vee - Max.,
lOUT = 0mA,
f = fMAX = litRe
Max.
50
rnA
CE~VIH,
VIN ~ VIHor
VIN.s VrL,
f= fMAX
Mil
Max.Vcc,
Com'!
CE~ Vee - 0.3V;
VIN ~ Vee - O.3V Mil
or VIN .s 0.3V; f=O
2
rnA
Capacitance[5]
Parameter
CIN: Addresses
Description
Input Capacitance
CIN: Controls
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
Vee =5.0V
Output Capacitance
Notes:
1. VIL (min.) = - 2.0V for pulse durations ofless than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
2-228
Max.
Unit
7
pF
10
pF
10
pF
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Tested initially and after any design or ptocess changes that may affect
these parameters.
~YPRESS
CY7CIOOl
CY7CI002
PRELIMINARY
Data Retention Characteristics Over the Operating Range (L Version Only)
Commercial
Parameters
Conditions[lO]
Description
VDR
V cc for Retention Data
IeeDR
Data Retention Current
tCDR[5]
Chip Deselect to Data Retention Time
tR[5]
Operation Recovery Time
Min.
Max.
2.0
Vee = VDR = 2.0Y,
CE~ Vee - 0.3Y,
VIN ~ Vee - O.3Vor
VINsO.3V
Military
Min.
Max.
Units
70
J.IA.
2.0
V
50
0
0
ns
tRe
tRe
ns
Data Retention Wavefonn
DATA RETENTION MODE
VCC
4.SV
VDR~2V
f~"-
~~
C1001-5
Switching Wavefonns
Read Cycle No. 1[11, 12]
~
ADDRESS
---DATA OUT
*-
IRC
1
~IOHA~
PREVIOUS DATA VALID
~XX *===============D=A=TA=V=A=L=ID===========
C1001-6
Read Cycle No. 2[12, 13]
ADDRESS
IRC·
~
j
tACE
DATA OUT
-tHZCE-
HIGH IMPEDANCE
J
"-
DATA VALID
'"
IUCE
_tpu
VCC _ _ _ _ _ _ _
SUPPLY
CURRENT
-
1/'//
"':'--tPD
SO%
HIGH
IMPEDAN CE
I
~CC
50%~ISB
C1001-7
Noles:
10. No input may exceed Vee + 0.5V:
11. Device is continuously selected, CE = VIL.
12. WE is HIGH for read eyele.
13. Address valid prior to or coincident with CE transition LOW.
2-230
PRELIMINARY
QPRESS
Truth Table
CE
WE
Power
Mode
00 - 03
H
X
HighZ
Power-Down
Standby (ISB)
L
H
Data Out
Read
Active (Icc)
L
L
HighZ
7Cl002: Standard Write
Active (Icc)
L
L
Input nacking
7ClOOl: nansparent Writef15]
Active (Icc)
Ordenn~
. I n I:iormation
Speed
(ns)
12
15
20
25
Package
Name
Ordering Code
Package 1YPe
Operating
Range
CY7ClOOl-12PC
P31
32-Lead (3OD-Mil) Molded DIP
CY7ClOOl-12VC
V32
32-Lead (300-Mil) Molded SOJ
CY7ClOOl-15PC
P3l
32-Lead (300-Mil) Molded DIP
CY7ClOOl-15VC
V32
32-Lead (300-Mil) Molded SOJ
CY7ClOOl-15DMB
D32
32-Lead (300-MiI) CerDIP
Military
CY7ClOOl-20PC
P31
32-Lead (300-MiI) Molded DIP
Commercial
CY7Cl00l-20VC
V32
32-Lead (300-MiI) Molded SOJ
CY7ClOOl-20DMB
D32
32-Lead (300-MiI) CerDIP
Military
CY7ClOOl-25DC
P3l
32-Lead (300-Mil) Molded DIP
Commercial
CY7CI001-25VC
V32
32-Lead (300-Mil) Molded SOJ
CY7ClOOl-25DMB
D32
32-Lead (300-Mil) CerDIP
..
Commercial
Commercial
Military
Contact factory for "1:' versIOn avaIlabilIty.
Speed
(ns)
12
15
20
25
Package
Name
Ordering Code
Package 1YPe
CY7ClO02-l2PC
P3l
32-Lead (300-Mil) Molded DIP
CY7ClO02-l2VC
V32
32-Lead (300-MiI) Molded SOJ
CY7ClO02-l5PC
P3l
32-Lead (300-Mil) Molded DIP
CY7ClO02-l5VC
V32
32-Lead (300-MiI) Molded SOJ
0r:
ating
nge
Commercial
Commercial
CY7ClO02-l5DMB
032
32-Lead (300-Mil) CerDIP
Military
CY7ClO02-20PC
P31
32-Lead (300-MiI) Molded DIP
Commercial
CY7ClO02-20VC
V32
32-Lead (300-MiI) Molded SOJ
CY7ClO02-20DMB
D32
32-Lead (300-Mil) CerDIP
Military
CY7ClO02-25PC
P3l
32-Lead (300-Mil) Molded DIP
Commercial
CY7ClO02-25VC
V32
32-Lead (300-Mil) Molded SOJ
D32
32-Lead (300-MiI) CerDIP
CY7ClOO2~25DMB
..
Contact factory for "1:' versIOn availabilIty.
Note:
15. Outputs track inputs after specified delay.
2-232
Military
CY7CIOOl
CY7CI002
PRELIMINARY
CY7CI006
256K X 4 Static RAM
Features
Functional Description
• High speed
-tAA= 12ns
• CMOS for optimum speed/power
• Low active power
-910mW
• Low standby power
-275mW
• 2.0V data retention (optional)
- IOO IlW
• Antomatic power-down when
deselected
• TTL-compatible inputs and outputs
The CY7C1006 is a high-performance
CMOS static RAM organized as 262,144
words by 4 bits. Easy memory expansion is
provided by an active LOW chip enable
(CE), an active LOW output enable (OE),
and three-state drivers. The device has an
automatic power-down feature that reduces power consumption by more than
65% when deselected.
Writing to the device is accomplished by
taking chip enable (CE) and write enable
(WE) inputs LOW: Data on the four I/O
pins (1/00 through 1/03) is then written
into the location specified on the address
pins (Ao through A17)'
Logic Block Diagram
Reading from the device is accomplished
by t~ chip enable (CE) and output enable (OE) LOWwhile forcing write enable
(WE) HIGH. Under these conditions, the
contents of the memory location specified
by the address pins will appear on the four
I/O pins.
The four input/output pins (1/00 through
1/03) are placed in a high-impedance state
when the device is deselected (CEHIGH),
the outputs are disabled ~HIGH), or
during a write operation (CE and WE
LOW).
The CY7C1006 is available in standard
300-mil-wide DIPs and SOJs.
Pin Configuration
DIPISOJ
Top View
Ao
vee
A1
A2
A3
~
~
A7
As
A1
A2
As
~
As
A7
As
AAs
a:
W
110 3
0
w
110 2
c
U
~
~
GND
C
~
5
A17
A16
A15
A14
A13
A12
~B
110 3
110 2
1101
~
Cl006-2
110 1
a:
110 0
As
CE
WE
rn:
Cl006-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)
Commercial
Military
Commercial
Military
7CI006-12
12
165
50
2-234
7Cl006-15
15
155
165
40
40
7CI006-20
20
140
150
30
30
7CI006-25
25
130
140
30
30
~VEYPRESS
PRELIMINARY
TI 5n
CY7CI006
AC Test Loads and Waveforms
R1480Q
OUTP~~
30pF
I
j~8~~~NG"::"
ALL INPUT PULSES
R1480Q
R2
OUTP~~
5pF
255Q
I·
j~8~~~NG"::"
-=
SCOPE
3.0V--90%
R2
GND
255Q
"::"
SCOPE
(a) Nonnal Load
(b) High-Z Load
C1000-4
C1006-3
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT~
1.73V
Switching Characteristics Over the Operating Range[3, 6]
Parameter
Description
READ CYCLE
Read Cycle Time
tRC
7ClOO6-12
7ClOO6-15
7CIOO6-20
7ClOO6-25
Min.
Min.
Min.
Min.
Max.
Max.
15
12
Max.
20
Max.
25
ns
25
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
12
15
20
25
ns
tDOE
OE LOW to Data Valid
6
7
8
10
ns
tLZOE
00 LOW to Low Z
tHWE
OE HIGH to High Z[7, 8]
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power-Up
15
12
3
3
0
3
0
3
3
0
0
CE HIGHto Power-Down
tpD
WRITE CYCLE[9, 10]
3
20
ns
ns
10
ns
25
ns
ns
0
0
15
12
ns
10
8
7
6
0
8
ns
ns
3
0
7
6
3
20
Unit
twc
Write Cycle Time
12
15
20
25
ns
tSCE
CE:: LOW to Write End
10
12
15
20
ns
tAW
Address Set-Up to Write End
10
12
15
20
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
10
12
15
20
ns
tSD
Data Set-Up to Write End
7
8
10
15
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE: HIGH to Low Z[8]
3
3
3
3
tHzWE
WE LOW to High Z[7,8]
6
7
8
ns
10
ns
Notes:
6.
7.
8.
Thst conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and outputloading
of the specified IOrJIOH and 30-pF load capacitance.
tHZoE, tHZCE, and tHZWE are specified with aload capacitance of5 pF
as in part (b) of AC Test Loads. ltansition is measured ± 500 m V from
steady-state voltage.
At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHzoE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
9.
The internal write time ofthe memory is defined by the overlap ofm
and WE LOW. CE and WE must be LOW to initiate a write, and the
transition of either of these signals can terminate the write. The input
data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
10.. The minimum write cycle time for Write Cycle No.3 (WE controlled,
DE LOW) is the sum of tHZWE and tSD.
2-236
~YPRESS
PRELIMINARY
CY7CI006
Switching Waveforms (continued)
Write Cycle No.1 (CE Controlled)[15, 16]
~------------------------twc------------------------~~
ADDRESS
---+-----------_i---tscE ----1,.-----+---~------------------~~w------------------~~---
~t~------tso----~~
DATA 110
----------------------IC~-----D-A-T-A-V-AL-I-D----
) 1 - - - -_ _ __
Cl006-8
Write Cycle No.2 (WE Controlled, OE HIGH During Write)[15,16]
~--~-------------------twc----------------------~
ADDRESS
---~----~----~~~
~-----
tPWE ---------.I
,----------------
tso -----------<""--~ tHO
DATA I/O
6.~s..6.~~6.~~II--1\.....----~D~A"[~A~V~A~U~D~---.Jl-------Cl008-9
Notes:
15. IfCEgoesffiGHsimultaneouslywith WEgoingHIGH, the output remains in a high-impedance state.
16. Data I/O is high impedance ifOE = VIH.
2-238
PRELIMINARY
.rcYPRESS
Od
. Intiormaf Ion
r erIllji
Speed
(ns)
12
15
20
25
Package
Name
Ordering Code
Package 1Ype
Operating
Range
CY7C1006-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7C1006-12VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C1006-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C1006-15VC
V21
28-Lead (300-Mil) Molded SOJ
CY7CI006-15DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7Cl006-20PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
Commercial
Commercial
CY7C1006-20VC
V21
28-Lead (300-Mil) Molded SOJ
CY7CI006-20DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7Cl006-25PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7CI006-25VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C1006-25DMB
D22
28-Lead (300-Mil) CerDIP
..
Military
Contact factory for "r;' versIon availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
VOH
1,2,3
Parameter
Subgroups
VOL
1,2,3
tRC
Vrn
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tORA
7,8,9, 10, 11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
Ioz
1,2,3
tDOE
7, 8, 9, 10, 11
Icc
1,2,3
ISB!
1,2,3
twc
ISB2
1,2,3
tSCE
7,8, 9, 10, 11
tAW
7,8,9, 10, 11
tRA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
READ CYCLE
7, 8, 9, 10, 11
WRITE CYCLE
7,8,9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7,8,9, 10, 11
tHD
7,8, 9, 10, 11
Document #: 38-00201- B
2-240
CY7CI006
~YPRESS
PRELIMINARY
CY7CI007
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature .................. -65 ° C to + 150° C
Ambient Thmperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage on Vee Relative to GND[I] . -O.5V to +7.0V
DC Voltage Apglied to Outputs
in High Z State I] .................. -O.5V to Vee + O.5V
DC Input Voltage[1] ................ ·-O.5Vto Vee + O.5V
Current into Outputs (LOW) ..................... 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature[2]
Vee
O°Cto +70°C
5V± 10%
-55°C to +125°C
5V ± 10%
Range
Commercial
Military
Electrical Characteristics Over the Operaling Rangel3]
Parameter
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
VOH
VOL
VIH
Input LOW
Voltagel l ]
Input Load
Current
Output Leakage
Current
Output Short
CircuitCurrent[4]
Vee Operaling
Supply Current
VIL
IIX
loz
los
. Icc
Automatic CE
Power-Down
Current
- TIL Inputs
ISB!
Automatic CE
Power-Down
Current
- CMOS Inputs
ISB2
7ClOO7-12
7ClOO7-15
7ClOO7-20
7ClOO7-25
Test Conditions
Min.
Min.
Min.
Min.
Vee = Min.,loH = - 4.0mA
2.4
Description
Vee = Min., IOL = 8.0 rnA
Max.
2.4
0.4
2.2
Max.
-0.3
Vee
+ 0.3
0.8
GND.$. VI.$. Vee
-1
GND.$. VI.$. Vee,
Output Disabled
-5
2.4
0.4
2.2
Max.
-0.3
Vee
+ 0.3
0.8
+1
-1
+5
-5
0.4
2.2
Max.
2.4
2.2
Unit
V
0.4
V
V
-0.3
Vee
+ 0.3
0.8
-0.3
Vee
+ 0.3
0.8
+1
-1
+1
-1
+1
JAA
+5
-5
+5
-5
+5
JAA
V
Vee = Max., VOUT = GND
-300
-300
-300
-300
rnA
Vee = Max.,
lOUT = OrnA,
f = fMAX = litRe
150
135
125
120
rnA
Mil
145
135
130
Max.. Vee,
Com'l
40
30
30
40
30
30
2
2
2
2
2
2
CE~VIH,
VIN~VIHOr
Com'l
VIN.$. VIL,
f= fMAX
Mil
Max. Vee,
Com'l
CE~ Vee - 0.3Y,
VIN~ Vee-O.3Vor
VIN.$. 0.3Y, f=O
50
2
Mil
rnA
rnA
Capacitance[5]
Parameter
CIN: Addresses
Description
Input Capacitance
CIN: Controls
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Output Capacitance
Max.
Unit
7
pF
10
pF
10
pF
Notes:
1.
VIL (min.) = -2.0V for pulse durations of less than 20 ns.
4.
2. TA is the "instant on" case temperature.
3.
See the last page oftbis specification for Group A subgroup testing information.
5.
2-242
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Thsted initially and after any design or process changes that may affect
these parameters.
'~PRESS
PRELIMINARY
CY7CI007
Data Retention Characteristics Over the Operating Range (L Version Only)
Commercial
Conditions[lO]
Description
Parameter
Min.
Max.
2.0
VDR
Vee for Data Retention
IceDR
Data Retention Current
tCDR[S]
Chip Deselect to Data Retention Time
tR[S]
Operation Recovery Time
Yce - VDR - 2.0V,
CE~ Vee - 0.3v,
VIN ~ Vee - O.3Vor
VINsO.3V
Military
Min.
Max.
Unit
V
2.0
50
70
IlA
0
0
ns
tRe
IRe
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
4.SV
VDR~2V
f~"-
~~
1007-5
Switching Waveforms
Read Cycle No. 1[11, 12]
f==
'L "
1
ADDRESS _ _ _ _ _
DATA OUT
PREVIOUS DATA
V~~;
*-
IRC
'XXX*================D=AT=A=V=A=L=ID============1007-6
Read Cycle No. 2[12, 13)
ADDRESS
-:l
IRC
~~
/
lACE
_ILZCE
HIGH IMPEDANCE
DATA OUT
I"-
_
VCC
SUPPLY
CURRENT
///
Ipu-
/
DATA VALID
"""
--d
HIGH
IMPEDANC E
,/
_lpD _
50%~
50%
ICC
~I S8
1007-7
Notes:
10. No input may exceed Vee + 0.5\1.
11. Device is continuously selected, CE = V IL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
2-244
~YPRESS
PRELIMINARY
Ordering Information
Speed
(ns) .
12
15
20
25
Package
Name
Ordering Code
Package 1YPe
CY7C1OO7 -12PC
P~l
28-Lead (300-MiJ) Molded DIP
CY7C1OO7 -12VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C1OO7 -15PC
P21
28-Lead (3OO-Mil) Molded DIP
CY7C1007 -15VC
V21
28-Lead (300-MiJ) Molded SOJ
Operating
Range
Commercial
Commercial
Ct7C1007 -15DMB
D22
28-Lead (3OO-Mil) CerDIP
Military
CY7C1oo7-20PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C1007 - 20VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C1oo7 - 20DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7C1OO7-25PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C1007-25VC
V21
28-Lead (300-MiJ) Molded SOJ
CY7C1007-25DMB
D22
28-Lead (300-Mil) CerDIP
..
Military
Contact factory for " r.:» versIOn availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
VOH
1,2,3
Parameter
Subgroups
READ CYCLE
VOL
1,2,3
tRC
7,8,9, 10, 11
Vm
1,2,3
tM
7,8, 9, 10, 11
VILMax.
1,2,3
tOHA
7, 8, 9, 10, 11
IIX
1,2,3
tACE
7,8, 9, 10, 11
Ioz
1,2,3
ICC
1,2,3
twc
7, 8, 9, 10, 11
ISBI
1,2,3
tSCE
7,8, 9, 10, 11
ISB2
1,2,3
tAW
7,8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
WRITE CYCLE
Document #: 38-00198-B
2-246
CY7CI007
PRELIMINARY
Q-YPRESS
CY7CI009
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied ........................ -55°C to + 125°C
Supply Voltage on Vee to Relative GND[l] .. -0.5V to +7.0V
DC Voltage ApBlied to Outputs
in High Z State 1] ................... -O.5V to Vee + O.5V
DC Input Voltage(1] ................. -O.5V to Vee + O.5V
Current into Outputs (WW) ...................... 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature[2]
Range
O°Cto +70°C
Vee
5V ± 10%
-55°C to +125°C
SV ± 10%
Commercial
Military
Electrical Characteristics Over the Operating Rangel3]
7C1009-12
Parameter
Description
Output HIGH
Voltage
OutputWW
Voltage
Input HIGH
Voltage
..
VOH
VOL
VIH
VIL
Input LOW
Voltage(1]
IJX
Input Load
Current
Output Leakage
Current
Output Short
Circuit Current[4]
loz
los
Icc
ISB1
ISB2
Test Conditions
Min.
Vee - Min., IOH - -4.0 rnA
2.4
Max.
7ClOO9-1S
7ClOO9-20
7CIOO9-2S
Min.
Min.
Min.
2.2
-0.3
Vee
+ 0.3
0.8
GND.!'>. VI.!'>. Vee
-1
GND.!'>. VI.!'>. Vee,
Output Disabled
Vee - Max., VOUT - GND
-5
Com'l
0.4
2.2
Max.
2.4
2.4
0.4
Vee - Min., IOL - 8.0 rnA
Max.
-0.3
Vee
+0.3
0.8
+1
-1
+5
-5
0.4
2.2
Max.
2.4
2.2
V
0.4
V
V
-0.3
Vee
+ 0.3
0.8
-0.3
Vee
+ 0.3
0.8
+1
-1
+1
-1
+1
tJA
+5
-5
+5
-5
+5
tJA
-300
rnA
rnA
-300
-300
-300
185
170
155
145
180
170
160
40
30
30
40
30
30
2
2
2
2
2
2
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA,
f = fMAX = lItRe
Automatic CE
Power-Down
Current
-ITLInputs
Max. V ee, c::E1~ VIH Com'l
orCEz.!'>. VIL,
VIN~ VIHor
Mil
VIN .!'>. VIL, f = fMAX
45
Automatic CE
Power-Down
Current
- CMOS Inputs
Max.Vro
CE1 ~ V cc - 0.3v,
or CEz .!'>. 0.3v,
VIN ~ Vee - 0.3v,
or VIN .!'>. 0.3V, f=O
Com'l
2
Mil
Mil
Unit
V
rnA
rnA
Capacitance[5]
Parameter
CrN: Address
Description
Input Capacitance
CrN: Controls
CoUT
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Output Capacitance
Notes:
1. VIL (min.) = -2.0V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing
infonnation.
Max.
Unit
7
pF
10
pF
10
pF
4. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
5. 'Iested initially and after any design or process changes that may affect
these parameters.
2-248
CY7CI009
PRELIMINARY
.rcYPRESS
Data Retention Characteristics Over the Operating Range (L Version Only)
Commercial
Parameter
Conditions[ll]
Description
VDR
V CC for Data Retention
Max.
Min.
2.0
ICCDR
Data Retention Current
tCDR[5]
Chip Deselect to Data Retention Time
tR[5]
Operation Recovery Time
t=
_
vcc
4.5V
0
:=~i==
'L "
=t
tRC
DATA RETENTION MODE
Unit
V
50
1 ;:::: V CC - 0.3V or
CE2S 0.3V,
VIN;:::: Vcc - O.3Vor
VINS°.3V
VOR ~ 2V
Max.
2.0
~C=VDR= 2.0V,
Data Retention Waveform
Military
Min.
t-tA
70
0
ns
tRC
ns
_
4.5V
--=-,
Switching Waveforms
Read Cycle No.
d 12, 13]
tRC
1
ADDRESS _______
DATA OUT
PREVIOUS DATA
V~~; 'XXX*:~~~~~~~~~~~~~~D~A~rA~_v-A~L~ID~~~~~~~~~~~_
1009-7
Read Cycle No.2 (OE Controlled)[13, 14J
ADDRESS
)K
)(
IRC
~"
~Il"
~i'\..
~i
AOSP _..r'-~...
AllSC -+----<~
cs ...--~
TIMING
CONTROL
WR-----<~
I~ ~ I~ .r.rl
7 6 5 4 3 2 '1' 52 51 504948 47
lJ
46
0010
0011
OQ12
12
13
14
0013
15
39
DCo
Vssa
VCCQ
OQ'4
16
17
18
38
37
36
Vssa
00,5
19
20
42
41
40
7C1031
7C1032
35
34
21 22 23 24 25 26 27 28 29 30 31 32 33
WI:---L._-.J
~<~<'cf
< R~ >8;1:;;- i
18
0015 - 000
__________~::~==)---::::::::::::::::~r-~-- DP1-D~
De
1031-2
Selection Guide
Pentium is a
Note:
1. DPo and DPI are functionally equivalent to Do,,"
2-258
DC7
DC.
10
11
OP1[1)
44
43
oPa(1]
VCCQ
VSSQ
1031-1
VCCQ
Vssa
DC,
DC,
DC2
VCCQ
DC,
DCo
CY7CI031
CY7CI032
PRELIMINARY
Pin Definitions
Signal Name
lYPe
# of Pins
Description
Vcc
Input
1
VCCQ
GND
Input
4
+ 5V or 3.3V (Outputs)
Input
1
Ground
VSSQ
CLK
Input
4
Ground (Outputs)
Input
Al5 Ao
ADSP
Input
ADSC
Input
WH
Input
WL
Input
ADV
Input
1
16
1
1
1
1
1
1
1
16
2
Input
OE
Input
C;S
Input
DQi5 DQo
Input/Output
DPl DPo
Input/Output
+5VPower
Clock
Address
Address Strobe from Processor
Address Strobe from Cache Controller
Write Enable - High Byte
Write Enable - Low Byte
Advance
Output Enable
Chip Select
Regular Data
Parity Data
Pin Descriptions
Signal
Name
I/O
Input Signals
CLK
AlS-Ao
I
Signal
Name
Description
WH
Clock signal. It is used to capture the address, the
data to be written, and the following control signals: ADSP, ADSC, CS, WH, WL, and ADV. It is
also used to advance the on-chip auto-address-increment logic (when the appropriate control signals have been set).
Sixteen address lines used to select one of 64K
locations. They are captured in an on-chip register
on the rising edge of CLK if ADSP or ADSC is
LOW. The rising edge of the clock also loads the
lower two address lines, A I - Ao, into the on-chip
auto-address-increment logic if ADSP or ADSC is
LOW.
I/O
Description
Write signal for the high-order half of the RAM
array. This signal is sampled by the rising edge of
CLK. If WH is sampled as LOW. i.e .• asserted, the
control logic will perform a self-timed write of
DQl5 - DQs and DPl from the on-chip data register into the selected RAM location. There is one
exception to this. If ADSP, WH, and CS are asserted (LOW) at the rising edge of CLK, the write
signal, WH, is ignored. Note that ADSP has no
effect on WH if CS is HIGH.
Write signal for the low-order half of the RAM
array. This signal is sampled by the rising edge of
CLK. If WL is sampled as LOW, i.e., asserted, the
control logic will perform a self-timed write of
DQ7 - DQo and DPo from the on-chip data register
into the selected RAM location. There is one exception to this. If ADSP, WL, and CS are asserted
(LOW) at the rising edge of CLK, the write signal,
WL, is ignored. Note that ADSP has no effect on
WL if CS is HIGH.
Address strobe from processor. This signal is
sampled at the rising edge of CLK. When this input
andlor ADSC is asserted, Ao--AI5 will be captured
in the on-chip address register. It also allows the
lower two address bits to be loaded into the onchip auto-address-increment logic. If both ADSP
and ADSC are asserted at the rising edge of CLK,
only ADSP will be recognized. The ADSP input
should be connected to the ADS output of the processor. ADSP is ignored when CS is HIGH.
Advance. This signal is sampled by the risirig edge
of CLK. When it is asserted, it automatic.uly increments the 2-bit on-chip auto-address-increment
counter. In the CY7C1032, the address will be incremented linearly. In the CY7Cl031, the address
will be incremented according to the Pentiuml486
burst sequence. This signal is ignored if ADSP or
ADSC is asserted concurrently with CS. Note that
ADSP has no effect on ADV if CS is HIGH.
Address strobe from cache controller. This signal is
sampled at the rising edge of CLK. When this input
andlor ADSP is asserted, Ao--A 15 will be captured
in the on-chip address register. It also allows the
lower two address bits to be loaded into the onchip auto-address-increment logic. The ADSC input should not be connected to the ADS output of
the processor.
Chip select. This signal is sampled by the rising
edge of eLK. If es is HIGH and ADSe is LOW,
the SRAM is deselected. If CS is LOW and ADSe
or ADSP is LOW, a new address is captured by the
address register. If es is HIGH, ADSP is ignored.
2-260
~YPRESS
d#
CY7CI031
CY7CI032
PRELIMINARY
Electrical Characteristics (continued)
Parameter
Description
Test Conditions
los
Output Short Circuit
Current[5]
lee
Vee Operating
Supply Current
ISB!
Shaded areas contain peliminary information
Capacitance[7]
Description
Parameter
CIN: Addresses
Test Conditions
= 2SoC, f Vee = S.OV
Input Capacitance
TA
1 MHz,
.
.
4;5
,"
Com'!
CIN: Other Inputs
Output Capacitance
pF
S
"
COUT
Unit
Max.
Com'!
8
Com'!
.
pF
J
.
pF
Shaded areas contain advanced information
AC Test Loads and Waveforms
OUTPUT~
....
Zo=50Q
....
VCCQ31R1
R =50Q
3.0V
L
5 pF
VL= 1.5V
(a) Normal Load
'ALL INPUT PULSES
OUTPUT
INCLUDING
JIG AND
SCOPE
I-= ,-=
R2
GND
~'---~90%
10%
10% ,90%
~
'
5.3n8'"
...
5.3n8
1031-3
(b)[8] Hign-Z Load
Notes:
5. Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
6. Inputs are disabled, clock is allowed to run at speed.
7. Tested initially and after any design or process changes that may affect
these parameters.
8.
2-262
1031-4
ResistorvaluesforVCCQ=5V are: Rl=1179Q andR2=868Q Resistor values for VCCQ=3.3V are Rl=317Q and R2=348Q
PRELIMINARY
=:'rcYPRESS
CY7CI031
CY7CI032
Switching Waveforms
Single Read[12]
ClK
ADDRESS
ADSJ5(13)
or
7iOSC
WH, W[(14)
DATA OUT
1031-6
Single Write Timing: Write Initiated by ADSP
ClK
DATA)N
DATAOUT ______________~------II----------------t_--------------------------
Notes:
12. DE is LOW throughout this operation.
13. If ADSP is asserted while CS is HIGH, ADSP will be ignored.
14. ADSP has no effect on ADV, WL, and WH ifCS is HIGH.
2-264
.~YPRESS
PRELIMINARY
CY7CI031
CY7CI032
Switching Waveforms (continued)
Output (Controlled by OE)
F~ ~
M>AO: _><_X_X_X_X__
=f______
t_tEO_'
1031-9
Write Burst Timing: Write Initiated by ADSC
2-266
PRELIMINARY
1zV2YPRESS
CY7C1031
CY7C1032
Switching Waveforms (continued)
Output Timing (Controlled by CS)
1031-12
Output Timing (Controlled by WH/ WL.,.:"-_ _ __.
elK
AOSl:: and
Al5SI"
WH, we
DATA OUT
1031-13
Truth Table
Input
CS
H
ADSP
X
ADSC
L
ADV
X
WHorWL
X
CLK
L-+H
H
L
H
H
H
L-+H
Same address as
previous cycle
Read cycle (ADSP ignored)
H
L
H
L
H
L-+H
Incremented burst
address
fead cycle, in burst sequence
ADSP ignored)
H
L
H
H
L
L-+H
Same address as
previous cycle
Write cycle (ADSP ignored)
H
L
H
L
L
L-+H
Incremented burst
address
~e ?'icle, in burst sequence
L
L
X
X
X
L-+H
External
Read cycle, begin burst
L
H
L
X
H
L-+H
External
Read cycle, begin burst
L
H
L
X
L
L-+H
External
Write cycle, begin burst
X
H
H
L
L
L-+H
Incremented burst
address
Write cycle, in burst sequence
X
H
H
L
H
L-+H
Incremented burst
address
Read cycle, in burst sequence
X
H
H
H
L
L-+H
Same address as
previous cycle
Write cycle
X
H
H
H
H
L-+H
Same address as
previous cycle
Read cycle
2-268
Address
N/A
Operation
Chip deseli:cted
(
S ignored)
ADVANCED INFORMATION
CY7CI088
128K X 9 Static RAM
Features
• Highspeed
-tAA = l2ns
• CMOS for optimnm speed/power
• Low active power
-1020mW
• ~w stan.dtiy power
-250mW
• 2.0v"data retention
--'-:lOOIlW
• Available in plastic 32-pin
4OO-mil SOJ
• AJItomatic power-down when
deselected
• Easy mem~ expansion with CEl>
CE2. and
, . OE options
Functional Description
The CY7C1088 is a high-performance
CMOS static RAM organized as 131,072
words by 9 bits. Easy memory expansion is
provided by an active LOW chip enable
(eEl), an active HIGH chip enab~(CEz),
an active LOW output enable (OE), and
three-state drivers. This device has an IIU"
tomatic power-down feature that reduCes
power consumption by more than 75%
when deselected.
Writing to the device is accomplished by
taking~ enable one (eEl) and write enable (WE) inputs LOW and chip enable
two (CEz) input HIGH. Data on the eight
I/O pins (1/00 through 1/07) is then written
Logi~ Biock Diagram
into the location specified on the address
pins (Ao through A16)'
Reading from the device is accomplished
by taking ch~nable one (eEl) and output enab~OE) LOW while forcing write
enable (WE) and chip enable two (CEz)
HIGH. Under these conditions, the contents of the memory location specified by
the address pins will appear on the I/O
pins.
The eight input/output pins (1/00 through
1/07) are placed in a high-in1pedance state
when the device is deselected (CEIHIGH
or CE2 LOW), the outputs are disabled
(Qg HIGH), or during a wri~eration
(CEl LOW,CEz HIGH, and WE LOW).
The CY7C1088 is available in standard
32-pin 400-mil-wide SOJs.
Pin Configuration
SOJ
Top View
Vee
A,.
CE2
I/O.
WE
A7
1/0 1
As
As
1/0 2
As
A'3
6
~
1/0 3
I/O.
I/O.
A2
A,
As
As
Al1
9
OJ:
A,.
Ao
CE,
I/O.
I/O,
1/0 7
1/02
1/0 3
I/O.
I/O.
1/0 4
GND
I/O.
1088-2
I/O.
1/07
1088-1
OJ: - - - < L . J
Selection Guide
Maximum Access Time (NS)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)
7C1088 12 7C1088-l5 7C1088-20 7C1088-25
12
15
20
25
185
170
155
145
180
170
160
30
30
40
45
40
30
30
Commercial
Military
Commercial
Military
Document #: 38-00451
2-270
CY7C1331
CY7C1332
ADVANCED INFORMATION
Functional Description (continued)
Single Read Accesses
Single Write Accesses Initiated by ADSP
A single read access is initiated when the following conditions are
satisfied at clock rise: (1) CS is LOW, (2) ADSP or ADSC is LOW,
and (3) WH and WLare HIGH. The address at Ao through A15 is
stored into the address advancement logic and delivered to the
RAM core. If the output enable (DE) signal is asserted (WW),
data will be available atthe data outputs a maximum of 8.5 ns after
clock rise.
TIns access is initiated when the foll=~ conditions are satisfied at
is Ww. A'DSP-triggered
clock rise: (1) CS is WW and (2)
write cycles are oompleted in two clock periods. The address at Ao
through A15 is loaded into the address register and address advance~ent.logic and delivered to the RAM core. The write signal is ignored
m this cycle because the cache tag or other external logic uses this
clock period to perfonn address comparisons or protection checks. If
the write is allowed to proceed, the write input to the CY7C1331 and
CY7C1332 will be pulled WW before the next clock rise. ADSP is
ignored if CS is mGH.
If WH, WL, or both are LOW at the next clock rise, information
presented at DOo - D015 and DPo - DP1 will be written into the
location specified by the address advancement logic. WL controls
the writing ofDOo - D07 and DPo while WH controls the writing
of DOs - D015 and DP1. Because the CY7C1331 and CY7C1332
are common-I/O devices, the output enable signal (DE) must be
deasserted before data from the CPU is delivered to DOo - D015
andDPo - DP1. As a safety precaution, the appropriate data lines
are three-stated in the cycle where WH, WL, or both are sampled
LOW, regardless of the state of the OE input.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are satisfied at risin~ge of the clock: (1) C~iS LOW, (2) ADSC is
LOW, and (3) WH or WL are LOW. ADS triggered accesses are
completed in a single clock cycle.
The address at Ao through A15 is loaded into the address register and
address advancementlogic and delivered to the RAM core. Infonnation presented at DOo - D015 and DPo - DP1 will be written into
the lcx:a~on specified by the address advancement logic. WL controls
the writing ofDOo - D07 and DPo while WH controls the writing of
DOs - D015 and DP1. Since the CY7C1331 and the CY7C1332
are common-I/O devices, the output enable signal (OB) must be deasserted before data from the cache controller is delivered to the data
lines. As a safety precaution, t~propriate data lines are threestated in the cycle where WH, WL, or both are sampled LOW, regardless of the state of the OE input.
Burst Sequences
The CY7C1331 provides a 2-bit wraparound counter, fed by pins
Ao - Ai> that implements the Intel 80486 and Pentium processor
address burst sequence (see Table 1). Note that the burst sequence
depends on the first burst address.
Table 1. Counter Implementatinn for the Intel
Pentium/80486 Processor's Sequence
Fourth
First
Second
Third
Address
Address
Address
Address
AX+loAx
AX+loAx
Ax + loAx
AX+lo A•
11
00
01
10
01
00
11
10
10
00
01
11
11
10
01
00
The CY7C1332 provides a two-bit wraparound counter, fed by
pins Ao - A h that implements a linear address burst sequence (see
Table 2).
Table 2. Counter Implementation for a Linear Sequence
First
Address
AX+l,Ax
00
01
10
Second
Address
Ax + loA.
01
10
Third
Address
AX+l,Ax
10
Fourth
Address
Ax + l,Ax
11
11
11
00
00
01
00
01
10
11
Application Example
Figure 1 shows a 512-Kbyte secondary cache for a hypothetical
3.3V, 66-MHz Pentium or i486 processor using four CY7C1331
cache RAMs.
r
56-MHz OSC
1--
~
CLK
ClK
ADR
ADR
DATA
DATA
ADl!P
=
PENTIMUM AIlS
OR
1486
r
PROCESSOR
CLK
ADR
CACHE TAG
7Cl331
7ifN
UE
WRw[~
f2 2
= I j'}2'2
~ VWr; ~ ~
I
7ifN DE
ClK
ADR
DATA
ADl!P
CO~b'a.ER
DATA
MATCH
DIRTY
VALID
~
MATCH
DIRTY
VALID
Figure 1. Cache Using Four CY7C1331s
2-272
-
1331-3
INTERFACE TO
MAIN MEMORY
~YPRESS
CY7C1331
CY7C1332
ADVANCED INFORMATION
Pin Descriptions (continued)
Signal
Name
I/O
Signai
Name
I/O
Description
DPl-DPO
' I/O
Two bidirectional data JlO lines. These operate in
exactly the sarne manner as DQ15 - DQo, but are
narned differently because their primary purpose is
to store parity bits" while the DQs' primary purpose is to store ordinary data bits. DPl is an input
to and an output from the high-order half of the
RAM array, while DPo is an input to and an output
from the lower-order half of the RAM array.
Description
OE
Output enable. This signal is an asynchronous input that controls the direction of the data JlO pins.
If OE is asserted (LOW), the data pins are outputs,
and the SRAM can be read (as long as CS was asserted when it was sampled at the beginning of the
cycle). If OE is deasserted (lllGH), the data JlO
pins will be three-stated, functioning as inputs, and
the SRAM can be written.
Bidirectional Signals
DQ1S-DQo I/O Sixteen bidirectional data JlO lines. DQlS - DQ8
are inputs to and outputs from the high-order half
of the RAM array, while J)Q) - DQo are inputs to
and outputs from the low-order half of the RAM
array. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK.
As outputs, they carry the data read from the selected location in the RAM array. The direction of
the data pins is controlled by OE: when OE is high,
the data pins are three-stated and can be used as
inputs; when OE is low, the data pins are driven by
the output buffers and are outputs. DQlS - DQ8
and DQ7 - DQo are also three-stated when WH
and WL, respectively, are sampled LOW at clock
rise.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................... -65°C to +150°C
Ambient Temperature with
Power Applied ........................ -55°C to + 125° C
Supply Voltage on V ce Relative to GND .... -0.5V to + 3.6V
DC Voltage ApBlied to Outputs
in High Z State 2] ................... -0.5V to Vec + O.3V
DC Input Voltage[2] ................. -O.5V to Vee + 0.3V
Current into Outputs (LOW) ...................... 20 rnA
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . .. >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature[3]
Range
Com'l
Mil
O°Cto +70°C
Vcc,VccQ
3.3V ± 0.3V
-55°C to + 125°C
3.3V ± O.3V
Electrical Characteristics Over the Operating Range[4]
Parameter
VOH
VOL
VIH
VIL
Ix
Ioz
los
Icc
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage l2J
Input Load Current
Output Leakage
Current
Output Short Circuit
Curtent[5]
Vee Operating Supply
Current
Test Conditions
Vee - Min., IOH--2.0rnA
Vce - Min., IOL-2.0 rnA
GND:S;VI:S;Vee
GND :S; VI:S; Vee,
Output Disabled
Vee - Max., VOUT - GND
Vee-Max.,
Iout=OmA,
f=fMAX =1/tcye
I Com'l
I Mil
Notes:
2. Minimum voltage equals - 2.0V for pulse durations of less than 20 ns.
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5.
2-274
7C1331-8
7C1332-8
Min.
Max.
2.4
0.4
2.0
Vee
+0.3V
-0.3
0.8
1
+1
5
+5
7CI331-!~
7C1332-10
Min.
Max.
2.4
0.4
2.0
Vee
+0.3V
-0.3
0.8
1
+1
5
+5
7C1331 12
7C1332-12
Min.
Min.
2.4
0.4
2.0
Vee
+O.3V
-0.3
0.8
1
+1
5
+5
Unit
V
V
V
V
IJA
IJA
-300
-300
-300
rnA
200
200
170
rnA
200
Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
CY7C1331
CY7C1332
ADVANCED INFORMATION
Switching Characteristics Over the Operating RangdS]
7C1331-8
7C1332-8
Parameter
Min.
15
Max.
7C1331-10
7C1332-10
Min.
15
Min.
20
tCYC
Description
Clock Cycle Time
tCH
Clock HIGH
5
6
8
ns
tCL
Clock LOW
5
6
8
ns
tAS
Address Set-Up Before CLK Rise
2.5
2.5
2.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
tADS
ADSp, ADSC Set-Up Before CLK Rise
2.5
tADSH
Al)Sp, ADSC Hold After CLK Rise
0.5
twES
WH, WL Set-Up Before CL~ Rise
2.5
tWEH
WH, WL Hold After CLK Rise
tADVS
10
8.5
3
Max.
7CI331-12
7C1332-12
3
Max.
Unit
ns
ns
12
ns
3
ns
2.5
2.5
ns
0.5
0.5
ns
2.5
2.5
ns
0.5
0.5
0.5
ns
ADV Set-Up Before CLK Rise
2.5
2.5
2.5
ns
tADVH
ADV Hold After eLK Rise
0.5
0.5
0.5
ns
tDS
Data Input Set-Up Before CLK Rise
2.5
2.5
2.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
ns
tess
Chip Select Set-Up
2.5
2.5
2.5
ns
tCSH
Chip Select Hold After CLK Rise
0.5
0.5
0.5
tcsoz
Chip Select Sampled to Output High Z[9]
2
6
2
6
2
7
ns
tEOZ
OE HIGH to Output High Z[9]
2
6
2
6
2
7
ns
tEOV
OE LOW to Output Valid
6
ns
tWEOZ
WHorWLSampledLOWto Output High Z[9, 10]
5
6
7
ns
tWEOV
WH or WL Sampled HIGH to Output Valid[lO]
8.5
10
12
ns
5
Notes:
8. Unless otherwise noted, test conditions assume signal transition time
of 3 ns or less, timing reference levels of 1.5\1, input pnlse levels of 0 to
3.0\1, and outputloading ofthe specified IOrJIOH and load capacitance
as shown in (a) and (b) of AC 'Iest Loads.
9.
5
ns
tcsoz, tEOZ, and tWEOZ are specified with a load capacitance of 5 pF
as in part (b) of AC 'Iest Loads. nansition is measured ± 500 mV from
steady-state voltage.
10. At any given voltage and temperature, tWEOZ min. is less than tWEOV
miD.
2-276
7&: ircYPRESS
S~fclt,ng
ADVANCED INFORMATION
CY7C1331
CY7C1332
Waveforms (continued)
Single Write Timing: Write Initiated by ADSC
Burst Read Sequence with Four Accesses
1331-9
2-278
~YPRESS
ADVANCED INFORMATION
CY7C1331
CY7C1332
Switching Waveforms (continued)
Write Burst Timing: Write Initiated by ADSP
1331-12
2-280
~YPRESS
·ADVANCED INFORMATION
Ordering Information
Speed
(ns)
8.5
10
12
Speed
(ns)
8.5
10
12
Ordering Code
Package
Name
Package
1YPe
CY7C1331-8JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C1331-8NC
N52
52-Lead Plastic Quad Flatpack
CY7C1331-lOJC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C1331-10NC
N52
52-Lead Plastic Quad F1atpack
CY7C1331-12JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C1331-12NC
N52
52-Lead Plastic Quad Flatpack
Ordering Code
Package
Name
Package
1Ype
CY7C1332-8JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C1332-8NC
N52
52-Lead Plastic Quad Flatpack
CY7C1332-10JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C1332-lONC
N52
52-Lead Plastic Quad F1atpack
CY7C1332-12JC
J69
52-Lead Plastic Leaded Chip Carrier
N52
52-Lead Plastic Quad F1atpack
CY7C1332-12NC
Document #: 38-00223-B
2-282
Operating
Range
Commercial
Commercial
Commercial
Operating
Range
Commercial
Commercial
Commercial
CY7C1331
CY7C1332
CY7C1335
CY7C1336
ADVANCED INFORMATION
.rcYPRESS
Pin Configuration
Top View
~~~~'~t~~~}d~~~~~~~~
10099 98 97 96 95 94 93 92 91 908988 87868584 8382 81
NC
OQ16
80
79
78
00,7
Vooa
VSSQ
77
76
75
7.
00,8
OQ19
OQ20
73
OQ21
Vooa
VSSQ
DO,.
D023
NC
Voo
NC
72
7'
70
69
88
67
12
'3
,.
15
16
66
65
64
63
82
61
60
59
58
57
56
55
54
53
52
51
Vs.
OQ24
DO,.
Vooa
Vssa
D026
OQ27
DQ28
DQ29
Vssa
VDDQ
OQ30
DOs,
NC
NC
OQ'5
DO,.
VDDQ
Vssa
DO"
DO'2
DO"
DQ10
Vooa
Vasa
DOs
DO,
Vss
NC
Voo
zz
DO,
DO.
Vooa
Vssa
DOs
oa.
DOs
D02
VSSQ
Vooe
DO,
DOo
NC
~~~MM~U~$~~~~~~~Q~~OO
1035-2
~~<~~<~~~~~~~1J~~~~~
Selection Guide
7C1335-7
7C1336-7
Maximum Access Time (ns) (O-pF load)
Maximum Operating Current (rnA)
I Commercial
2-284
7C1335-8
7C1336-8
7C1335-10
7C1336-10
7.0
8.5
10
180
170
160
PRELIMINARY
CY7C1399
32K X 8 3.3V Static RAM
Features
Functional Description
• Single 3.3V power supply
• Ideal for low-voltage cache memory
applications
'The CY7C1399 is a high-perfonnance
3.3V CMOS static RAM organized as
32,768 words by 8 bits. Easy memory e~
pansio~isrovided by an active LOW chip
enable CE) and active LOW output enable ( E) and three-state drivers. 'The device has an automatic power-down feature,
reducing the power consumption by more
than 60% when deselected.
An active LOW write enable signal (WE)
controls the writing/readin~eration of
the memory. When CEl and WE inputs are
both LOW, data on the eight data input/
output pins (1/00 through 1/07) is written
into the memory location addressed by the
• High speed
- 12ns
• Low active power
- 255mW
• Low standby power
- 90mW
• 2_0V data retention
- IO°ftW
• Easy memory expansion with CE and
OE features
• Plastic DIP, SOJ, and TSOP
packaging
Logic Block Diagram
address present on the address pins (Ao
through A14). Reading the device is accomplished by selectin~the device and :nabling the outputs,
and "('j"E active
LOW, while WE remains inactive or
HIGH. Under these conditions, the contents of the location addressed by the infonnation on address pins is present on the
eight data input/output pins.
The input/output pins remain in ahigh-impedance state unless the chip is selected,
outputs are enabled, and write enable
(WE) is HIGH. 'The CY7C1399 is available in standard 300-mil-wide DIP and
SO] packages. A die coat is used to ensure
alpha immunity.
rn
Pin Configurations
n=FrFr~
DIP/SOJ
Top View
Vee
WE
A7
Aa
Aa
1/0 0
1/0,
1/°2
1/°3
A'3
A,.
1/0 0
I/O,
1/0 2
GND
A"
Aa
A2
A,
Of:
""
CE
I/o,
1/0.
1/0,
vo.
Vo,
1/04
C1399·2
1/05
I/Oa
1/07
C1399-,
Selection Guide
2-286
PRELIMINARY
CY7C1399
Electrical Characteristics Over the Operating Range[2] (continued)
7C1399-25
Parameter
Description
Test Conditions
Min.
Max.
VOH
Output HIGH Voltage
Vee = Min., IOH = -2.0 rnA
VOL
Output WW Voltage
Vee = Min., IOL = 2.0 rnA
2.4
VIH
Input mGH Voltage
2.0
Vee
+O.3V
-0.3
-1
-5
7C1399-35
Min.
Unit
Max.
2.4
V
0.4
0.4
V
2.0
Vee
+O.3V
V
0.8
-0.3
0.8
V
+1
-1
+1
+5
-5
+5
!lA
!lA
-300
-300
rnA
45
40
mA
VIL
Input WW Voltagel2]
IIX
Input Load Current
Ioz
Output Leakage Current
GND.$. VI.$. Vee,
Output Disabled
los
Output Short
Circuit Currentl3]
Vee = Max.,
VOUT= GND
lee
Vee Operating
Supply Current
Vee = Max., lOUT = 0 rnA,
f = fMAX = litRe
ISBI
Automatic CE Power-Down Max. Vee, CEI ~ VIH
Current - TIL Inputs
or CE2.$. VIL, VIN ~ VIH or
VIN.$. VIL, f = fMAX
5
5
rnA
ISB2
Automatic CE Power-Down Max. Vee, CEI ~ Vcc 0.3V or
Current - TIL Inputs
CE2.$.0.3V, VIN ~ Vee0.3V or VIN.$. 0.3V, f=O
50
50
!lA
Capacitance[4]
Parameter
Description
Test Conditions
Input Capacitance
CIN: Addresses
TA = 25°C, f = 1 MHz,
Vee = 3.3V
CIN: Controls
Output Capacitance
CoUT
Max.
Unit
5
pF
6
pF
6
pF
AC Test Loads and Waveforms
R1353Q
ALL INPUT PULSES
3.3Vjl
OUTPUT
I
CL
INCLUDING _
JIG AND SCOPE
Equivalent to:
3'0V~
10%
90%
~f9Q
,5;.3ns -
_
-
~
10%
GND
_
,5;.3ns
C1399-4
THEvENIN EQUIVALENT
500Q
OUTPUT 0.0---·.,.
...""·- - - 0 0 1.40V
Note:
4. Thsted initially and after any design or process changes that may affect
these parameters.
2-288
~YPRESS
PRELIMINARY
.
1=
Data Retention Waveform
Vce
3.0V
j--:. !cDR
_
.
CY7C1399
=t .
DA".A RETENTION MODE
VOR ~ 2V
_
.
3.0V
tR
---i
01399·5
Switching Waveforms
Read Cycle No. 1[11, 12J
ADDRESS
-------~
~
DATA OUT
PREVIOUS DATA
*-
tRC
~
V~~: 'XX
1
*===============D=A=TA=V=A=U=D============
C1399-6
Read Cycle No. 2[12, 13J
tRC
-...."
~
tACE
k'I
~~
tOOE
~tLZOE--
DATA OUT
HIGH IMPEDANCE
.///
DATAVAuD
."-"-
tLZCE
}
HIGH
IMPEDAN CE
/
i---tpo
~tpu
VCC
SUPPLY _ _ _ _ _ _ _
CURRENT
'~3
I--- tHZCE
~CC
1'---I
50%
50%
ISB
C1399-7
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
2-290
~
PRELIMINARY
--:rcYPRESS
'fruth Table
CE
WE
OE
H
X
X
HighZ
DeselectIPower-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (Icc)
L
L
L
X
Data In
Write
Active (Icc)
H
H
HighZ
Deselect, Output Disabled
Active (Icc)
Input/Output
Power
Mode
Ordering Information
35
Shaded area contains advanced information.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameter
DC Characteristics
Subgroups
READ CYCLE
Parameter
Subgroups
VOH
1,2,3
tRc
7,8, 9, 10, 11
1,2,3
tAA
7,8, 9, 10, 11
1,2,3
tOHA
7,8,9, 10, 11
1,2,3
tACE
7, 8, 9, 10, 11
1,2,3
tDOE
7,8,9, 10, 11
VOL
Vrn:
VILMax.
hx
WRITE CYCLE
Ioz
1,2,3
Icc
1,2,3
twc
7, 8, 9, 10, 11
ISBI
1,2,3
tSCE
7,8, 9, 10, 11
ISB2
1,2,3
tAW
7, 8, 9, 10, 11
tHA
7,8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
Document #: 38-00222-C
2-292
CY7Cl~99
Section Contents
Page Number
Modules
Custom Module Capabilities
Device
CYM1420
CYM1441
CYM1464
CYM1465
CYM1471
eyM1481
CYM1622
CYMl720
CYM1730
CYM1821
CYM1828
CYMi831
CYM1832
CYM1836
CYM1838
CYM1840
CYM1841
CYM1841A
CYM1816
CYM1851
CYM7232
CYM7264
CYM7420
CYM7421
CYM7424
CYM7425
CYM7127
CYM7428
CYM7432
CYM7450
CYM7451
CYM7490
CYM7491
CYM7492
CYM74AP54
CYM74SP54
CYM74SP55
CYM74A430
CYM74S430
CYM74S431
CYM74A550
CYM74A551
CYM74S550
CYM74S551
CYM74A590
CYM74S590
CY1174S591
CYM9230
CYM9231
CYM9236
CYM9237
............................................................................. 3-1
Description
128Kx 8 Static RAM Module .................................................... 3-5
256K x 8 Siatic RAM Module ................................................... 3-11
512K x 8 Static RAM Mcipule ................................................... 3-16
512Kx8SRAMModuie ....................................................... 3-22
10~Kx8 SRAM Module ...................................................... 3-28
2048K x 8 SRAM Module ...................................................... 3-28
64Kx 16 Static RAM Module ................................................... 3-34
32K~24StaticMMMpdule ................................................... 3-39
64~ x 24 Static RAM Module ................................................... 3-44
16K x 32 Static RAM Module ................................................... 3-49
32Kx 32 Static RAM Module ................................................... 3-55
64Kx 32 Static RAM Module ................................................... 3-62
64Kx32 Static RAM Module ................................................... 3-67
128K x 32 Static RAM Module .................................................. 3-72
128K x 32 Siatic R'\M Module .................................................. 3 -77
256Kx32Sta#c~Module .................................................. 3-82
256Kx 32 Static RAM Module .................................................. 3-88
256Kx 32 Static RAM Module .................................................. 3-88
512K x 32 Static RAM Module ............................. ",.................. 3 -97
1,024K x 32 Static RAM Module .............................. : . . . . . . . . . . . . . . . .. 3 -102
DRAM Accelerator Module". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 -107
DRAM Accelerator Mocjule ................................................... 3 -107
82420 PCIset-Compatible Level II Cache Module ................................. 3-108
82420 FCIset-Compatible Level II Cache Module ................................. 3-108
128J$: Cache Module for the Intel m 82420EX PCIset. .............................. 3-109
256K Cache Module for the Intel 82420EX PCIset ................................ 3 -109
82420 PCIset-Coplpatible Level II Cache Module Family ........................... 3-114
82420 PCIset-Compatible 4:veJ II Cache Module Family ........................... 3-114
256K Pentium m -Coplpatible Cache Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-115
128K Cache Module for VLSI VL82C483 Chip Set ................................ 3-118
256K Cache Module for VLSJ vL82C483 Chip Set ................................ 3-118
i486 m Level II Cache Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-119
i486 Level II Cache Module ................................................... 3-119
1486 Level II Cache Module ................................................... 3-119
Intel 82430NX Chip Set Level II Cache Module .................................. 3 -120
Intel 82430NX Chip Set Level II Cache Module .................................. 3 -120
Intel 8243PNX Chip Set Level II Cache Module .................................. 3-120
Intel 82430FX PCIset Level II Cache Module .................................... 3-125
Intel 82430FX PCIset Level II Cache Module .................................... 3-125
Intel 82430FX PCIset Level II Cache Module .................................... 3-125
OPTi Viper ~ Chip Set Level II Cache Module ................................... 3-130
OPTi Viper Chip Set Level II Cache Module ..................................... 3-130
OPTi Viper Chip Set Level II Cache Module ..................................... 3 -130
OPTi Viper Chip Set Level II Cache Module ..................................... 3 -130
VLSI 82C590 Chip Set Level II Cache Module ................................... 3 -135
VLSI ~2C590 Chip Set Level II Cache Module ................................... 3-135
VLS~ 82C59,P Chip Set LevelII Cache Module ................................... 3-135
8242q PCIset-Compatible Level II Cache Module ................................. 3-140
82420 PCIset-Compatible Level II Cache Module ................................. 3-140
128K Cache Module for the UMC491 Chip Set ................................... 3-141
256K Cache Module for the UMC491 Chip Set ................................... 3-141
~YPRESS
Custom Module Capabilities
VDIP
The VDIP, or vertical dual in-line pin package, is a vertically
mounted module with two rows of pins on loo-mil centers. Row to
row spacing is 100 mils, with pins of the two rows aligned directly
across from one another. The dual row of pins allows a higher connection density than that of the SIP while maintaining 100-mil
minimum spacing between any adjacent pins. VDIP may be either
plastic or ceramic. The VDIP is useful in large pin count devices
where the host board is designed with through-hole design rules.
DIP
The DIP, or dual in-line pin module, is a low-profile package with
excellent mechanical ruggedness. TheceramicDIPisideallysuited
for military applications. Plastic DIPs are often used when a low
vertical profile is required. In some cases, the DIP device is intended to have an identical footprint and similar form factor to
standard integrated circuit components and can provide larger
memory capacity in the same footprint.
PGA
The PGA, orpin grid array, has an array of pins that are perpendicular to the package plane. These pins are arranged in a matrix on a
100-mil grid. Most of the matriX is filled with pins except for a central square that is normally devoid of pins.
QUIP
The QUIP, or quad in-line pin package, is very similar to the DIP
package except that there is a dual row of pins along the package
edge. In-row and row-to-rowpin spacing is 100 mils with pins in adjacent rows aligned directly across form one another. The QUIP is
a low-profile package with excellent mechanical ruggedness, with
the added advantage of higher pin density for the same package
length.
QFP
The QFP, or quad flat pack, is a surface-mounted module. Gull
wing pins extend out from the square package on all four sides and
are formed to be coplanar with the package bottom. Lead pitches
are typically 50 mils or smaller.
Package Summary
Table 1 summarizes the various characteristics of the packages discussed above.
Table 1. Package Types
Package
Type
.Typical Pin
Count
Typical
Height[lj
Board Space
(sq. in.)[3j
MiI[2j
Min.
Max.
Min.
Max.
SIP
24
50
0.5
0.9
N
Vertical orientation. FR4 or
ceramic technology.
Advantages
FSIP
24
50
0.2
0.4
N
Very low profile. Mechanical
stability. FR4 or ceramic tech. nology.
ZIP
24
100
0.5
0.9
N
SIMM
24
100
0.5
0.9
N
Disadvantages
FR4
Cer
Limited pin count.
1.2
0.9
Lower density due to horizontal orientation,
2.7
2.4
Vertical orientation. JEDECstandard pinouts. Pinout compatible with SIMM.
1.2
N/A
Vertical orientation. Socket
mounting. Pinout compatible
with ZIP.
1.2
N/A
VDIP
36
104
0.5
0.95
Y
Vertical orientation.
1.2
0.9
DIP
24
60
0.17
0.37
Y
Low profile. Excellent mechanical ruggedness.
Horizontal orientation.
2.9
2.9
QUIP
48
200
Y
Low profile. Excellent mechanical ruggedness. Incr'eased number of pins.
Horizontal orientation.
2.9
2.9
QFP
68
144
Y
Surface mount. Low profile.
Excellent mechanical ruggedness. Large number of pins in
small area.
Surface-mount technology required. Horizontal orientation. Components on one side
only.
3.1
3.1
PGA
68
144
Y
Large number of pins in thruhole technology. Low profile.
Excellent mechanical ruggedness.
Multilayer boards. Horizontal
orientation. Components on
one side only.
2.9
2.9
Notes:
1. Minimum and maximum height are given in inches.
2. The Mil entry contains a Y(es) or N(0) indicating if the package type
is suitable for military applications.
3.
3-2
Board space roughly quantifies the main board area, in square inches,
taken up by the module When the module contains eight, 28-pin components.
Custom Module Capabilities
1iarcYPRESS
Custom Module Development Flow (continued)
During simulation, several types of analyses are performed. A
function simulation is used to ensure that the module's logic is designed properly. Timing simulation is run to verify that the module
will function when subjected to the worst -case timing delays of the
components. Finally, thermal analysis may be performed to determine the thermal characteristics of the module.
The layout of the module is also netlist driven. An autorouter may
be used, depending on the complexity and density of the module.
Design rule checks are run to ensure that the layout does not violate any electrical or mechanical design rules. Finally, the layout
output is used to generate the module substrate.
The layout output is also used to drive the pick and place equipment. This ensures consistency between design and manufacturing. While the module prototypes are being assembled, the test
program is generated and the test fixture is constructed. Test program generation is largely automated, using as inputs the simulation outputs and pre-defined test program subroutines for common configurations.
Once prototypes 1!ave been generated, the standard release procedure is initiated. this procedure includes steps such as bench testing, module characterization and qualification, and fine tuning of
the test program. Following customer approval of the module, it is
released to production.
Quoting Information
In order to prepare a quotation or proposal, we need as much as
possible of the following information:
• Circuit schematic
• Functional description
• Mechanical dimensions required
• Speed and power requirements
• Prototype and production deadlines
• Production quantity estimates
• An engineering contact to answer questions
Once the above information is received, a budgetary quotation will
typically be provided within one to two weeks.
Fignre 1. Custom Module Flow
3-4
CYM1420
_rcYPRESS
Maximum Ratings
(Above which the useful life may be impaired.)
Output Currel\t into Outputs (LOW) ............... 20 rnA
Storage Thmperature ..., ............... - 65°C to + 150°C
Ambient Thmperature with .. - 10°C to +S5°C(Commerciiil)
Supply Voltage to Ground Poiential ........ - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State,.: ....................... - O.5V to +7.0V
DC Input Voltage ............. ' .......... - 0.5V to +7.0V
Operating Range
Range
Ambient
Thmperature
Vee
Commercial
O°Cto +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameters
Description
Thst Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output Low y'ol~age
V cc = Min., IOL = S.O rnA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
GND~VI~Vee
loz
Output Leakage Current
GND ~ Va ~ Vee, Output Disabled
los
Output Short Circuit CUrrend l , 2]
Vee = Max., VOUT
Icc
Vee Operating Supply CUrrent
ISBl
ISB2
Min.
Max.
Units
2.4
V
0.4
V
2.2
Vee
V
- 0.5
O.S
V
-10
+10
+10
!lA
!lA
-300
rnA
Vee = Max., lOUT = 0 rnA, CS ~ VIL
210
rnA
Automatic CS Power-Down Current[3]
Vee = Max., CS~ VIH,
Min. Duty Cycle = 1()0%
140
rnA
Automatic CS Power-Down Currend3]
Vee = Max., CS ~ Vee - 0.3V;
VIN ~ Vee - O.3V or VIN ~ O.3V
SO
rnA
='
-10
GND
Capacitlmce[2]
Parameters
Test Conditions
Description
Crn
Input Capacitance
CoUT
Output Capacitance
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
Units
35
pF
40
pF
AC Test Loads and Waveforms
R1 4810
R1 4810
OUTP~~ ~
OUTP~~ ~
.~~~:F1
-
INCLUDING
JIG AND
SCOPE
-
1
_
-
R2
2550
.~ ~:F1
-
••
INCLUDING
JIG AND
SCOPE
R2
1
2550
GND
-
1420·3
(b) High-Z Load
(a) Nonnal Load
Equivalent to:
-
ALL INPUT PULSES
3,QV---
1420-4
THEvENIN EQUIVALENT
OUTPUT~
1.73V
Notes:
1. Not more than 1 output should be shorted at one time, Duration of the
short circuit should not exceed 30 seconds.
2. Tested on a sample basis.
3.
3-6
A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
~YPRESS
CYM1420
Switching Characteristics Over the Operating Range (continued)[4]
1420-35
Parameters
Description
Max.
Min.
1420-45
Min.
Max.
1420-55
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Data Hold from Address Change
35
45
35
3
ns
55
45
3
55
ns
ns
3
tACS
CS' LOW to Data Valid
35
45
55
ns
tDoE
OE LOW to Data Valid
18
25
30
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z[5]
CS' HIGH to High Z[5, 6]
3
twc
Write Cycle Time
35
45
55
tscs
CS' LOW to Write End
30
40
45
ns
tAW
Address Set-Up to Write End
30
40
45
ns
tRA
Address Hold from Write End
5
5
5
ns
tSA
Address Set-Up to Write Start
5
5
5
ns
0
0
20
20
5
20
tHZCS
WRITE CYCLE(7]
ns
0
25
ns
25
ns
ns
5
20
ns
tPWE
WE Pulse Width
25
25
30
ns
tso
Data Set-Up to Write End
18
20
25
ns
tHO
Data Hold from Write End
3
5
5
ns
tLZWE
WE HIGH to Low Z
WE LOW to High Z[6]
5
5
5
tHZWE
15
0
0
15
0
ns
25
ns
Switching Waveforms
Read Cycle No. 1[8,9]
'L...
~
AOORESS _ _ _ _ _
DATA OUT
PREVIOUS DATA VALID
tRC
1
~
*-
==ixXX*===============O=A=TA==VA=L=IO===========
1420·5
Notes:
8. WE is HIGH for read cycle.
9.
3-8
Device is continuously selected, CS = VIL and OE= VIL.
~YPRESS
CYM1420
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[7, 11, 12]
ADDRESS
-------tot----tscs
---.1
14--+----ISO - - - - t l o l -
DATA IN
DATA VALID
tHZWE---I
~
__j~~I--H-IG-H--IM-P-E-D-AN-C-E--___________
DATAI/O __________________________________
DATA UNDEFINED
r
1420-8
Note:
12. IfC:Sgoes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
Truth Thble
CS
OE
WE
H
X
X
HighZ
DeselectiPower-Down
L
L
H
Data Out
Read
L
X
L
Data In
Write
L
H
H
HighZ
Deselect
Inputs/Outputs
Mode
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package 1YPe
Operating
Range
20
CYM1420PD-20C
PD05
32-Pin DIP Module
Commercial
25
CYMI420PD-25C
PDOS
32-Pin DIP Module
Commercial
30
CYMI420PD-30C
PD05
32-Pin bIP Module
Commercial
35
CYMI420PD-35C
PD05
32-Pin DIP Module
Commercial
45
CYMI420PD-45C
PD05
32-Pin DIP Module
Commercial
55
CYM1420PD-55C
PDOS
32-Pin DIP Module
Commercial
Document #: 38-M-OOOOI-E
3-10
CYM1441
·;rcYPRESS
Maximum Ratings
Operating Range
(Above which the useful life may be impaired.)
Range
Storage Temperature ................... -55°C to + 125°C
Ambient Thmperature with
Power Applied ......................... -10°C to +85°C
Supply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to + 7.0V
DC Input Vol~age ........................ -O.5V to +7.0V
Commercial
Ambient
Temperature
Vee
O°Cto +70°<;:
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Min.
Test Conditions
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 12.0 rnA
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input Lbw Voltagd 1j
Ilx
Input Load Current
GND.$. VI.$. Vee
loz
Output Leakage Current
GND .$. Vo.$. Vee, Output Disabled
lee
Vee Operating Supply Current
Vee
ISBI
Automatic CS
Power-Down Current
Max. Vee, CS ~ VIH,
Min. Duty Cycle = 100%
ISB2
Automatic CS
Power-Down Current
Max. Vee, CS ~ Vee - 0.2Y,
VIN ~ Vee - 0.2V or VIN .$. 0.2V
Max.
Unit
0.4
V
2.2
Vee
V
-0.5
0.8
V
-80
+80
-50
+50
fAA
fAA
960
rnA
320
rnA
160
rnA
2.4
Vee
= Max., lOUT = 0 rnA, CS.$. VIL
V
Capacitance[2]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = ~.OV
= 1 MHz,
Max.
Unit
60
pF
15
pF
AC Test Loads and Waveforms
. Rl 329(.1
Rl 329(.1
OUTP~~ ~
,~~.~:Fi
INCLUDING
JIG AND
SCOPE
-
R2
1
-
OUTP~~ ~
202(.1
.~ ••~:Fi
INCLUDING
JIG AND
SCOPE
(a) Normal Load
Equivalent to:
ALL INPUT PULSES
-
3.0V ----":...
90%
R2
1
-
202(.1
GND
1441-3
(b) High-Z Load
THEVENIN EQUIVALENT
OUTPUT~
1.9V
Notes:
1. V IN (min.) = - 3.0V for pulse widths less than 20 ns.
55ns
2. Thsted on a sample basis.
3-12
1441-4
..-LYEYPRESS
CYM1441
Switching Waveforms (continued)
Read Cycle No. 2[~' 8]
tRC
~K.
)1
tACS
I--tHZCS-
tLZCS
~//
HIGH IMPEDANCE
DATA OUT
"
DATA VALID
~~"
i---tpo
~lpU
VCC _ _ _ _ _ _ _
SUPPLY
CURRENT
}
HIGH
IMPEDANCE
~ CC
I
50%
50%
-
ISB
1441-6
Write CyCle No.1 (WE Controlled)[5]
twc
ADDRESS
=:)(
I
tscs
~~ ~
_.
tAW
lSA
lHA-
tPWE
-y"
~~
...
DATA IN
Iso
*
tHO
DATA VALID
I--tLZWE~
_IHZWE:1
"
DATA OUT
/V////~ '/"/////
HIGH IMPEDANCE
_~___________D_AT_A_U_N_D_E_F_IN_E_D______________-J»----------------~<~
_________
1441-7
Write Cycle No.2 (CS Controlled)[5, 9]
ADDRESS
- - - - - - - - - . . , . - - - - Iscs -----0;
----r-------------------~
,-------+--------
I - + - - - t s o -----..0;.....
DATA IN
-----------~-------~
DATA VAliD
tHZWE----I
---...1
HIGH IMPEDANCE
-J»--------------------------
DATA OUT _______________D_A_TA__
UN_D_E_F_IN_E_D________________
1441-6
Notes:
8. Address valid prior to or coincident with (;S transition LOW:
9.
3-14
IfCS goes HIGH simuitaneouslywith WE HIGH, the output remains
in a high-impedance state.
CYM1464
512K X 8 Static RAM Module
Features
Functional Description
• High-density 4-megabit SRAM
module
The CYM1464 is a high-performance
4-megabit static RAM module organized
as 512K words by 8 bits. This module is
constructed using four 256K x 4 static
RAMs in SOJ packages mounted on an
epoxy laminate substrate with pins.
Writing to the module is accomplished
when the chip select (CS) and write enable
(WE) inputs are both LOW. Data on the
eight input/output pins (1/00 through
1/07) of the device is written into the
memory location specified on the address
• High-speed CMOS SRAMs
- Access time of 20 ns
• Low active power
-1.93W (max.)
• JEDEC-compatible pinout
• 32-pin, O.Ii-inch-wide DIP package
• TTL-compatible inputs and outputs
• Low profile
- Max. height of 0.34 inches
pins (Ao through A18)' Reading the device
is accomplishe~ taking chip select and
output enable (OE) LOW, while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the
memory location specified on the address
pins (Ao through A18) will appear on the
eight appropriate data input/output pins
(1/00 through 1/07).
The input/output pins remain in ahigh-imc
pedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH.
Logic Block Diagram
Pin Configuration
DIP
ThpView
10F2
DECODER
'----L-.t:::===:::::-L_L_ 1/00 _ I/~
1464-2
1464-1
Selection Guide
1464-20
1464-22
1464-25
1464-30
1464-35
1464-45
Maximum Access Time (ns)
20
22
25
30
35
45
55
Maximum Operating Current (rnA)
350
350
350
300
300
300
300
Maximum Standby Current (rnA)
240
240
240
240
240
240
240
3-16
1464-55
~YPRESS
CYM1464
Switching Characteristics Over the Operating Rangel3]
1464-20
Parameter
Description
Min.
1464-22
Max.
Min.
Max.
1464-25
Min.
Max.
1464-30
Min.
Max.
Unit
READ CYCLE..
22
20
25
30
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
20
22
25
30
ns
tDOE
OE LOW to Data Valid
13
13
15
15
ns
tLZOE
em LOW to Low Z
0
tHZOE
OE HIGH to High Z
0
tLZcs
CS LOW to Low Z
5
tHZCS
CS mGHto High Z[4]
0
20
25
22
5
5
5
0
0
10
5
15
0
5
0
10
0
10
0
0
ns
10
10
15
0
us
ns
0
5
15
us
30
ns
ns
20
ns
WRITE CYCLE[5]
twc
Write Cycle Time
20
22
25
30
ns
tscs
CS LOW to Write End
15
17
20
25
ns
tAW
Address Set-Up to Write End
15
15
20
25
ns
tHA
Address Hold from Write End
3
3
3
3
ns
tSA
Address Set-Up to Write Start
5
5
5
5
ns
tpWE
WE Pulse Width
15
15
15
20
ns
tSD
Data Set-Up to Write End
12
12
15
15
us
tHD
Data Hold from Write End
2
2
2
2
ns
tLZWE
WE HIGH to Low Z
0
tHZWE
WE LOW to High Z[4]
0
Notes:
3. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
4. tHZCS and tHzWE are specified with CL = 5 pF as in part (b) of ACThst
Loads and Waveforms. 'fransition is measured ±500 mV from steadystate voltage.
0
15
15
0
15
ns
15
ns
5. The internal write time of the memory is defined by the overlap of<::S
LOW and WE Law. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
3-18
~YPRESS
CYM1464
Switching Waveforms (continued)
Read Cycle No. 2[6, 8]
CS"
tRC
""""'
~
/flACS
.k
~~
100E
IHZOE-
I
~ILZOE-
I--IHZCS-
HIGH IMPEDANCE
'//
ILZCS
1'-"-"-"-
DATA OUT
DATA VALID
~Ipo
Ipu
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
"
~ CC
I
50%
,50%
ISB
1464-6
Write Cycle No.1 (WE ControlIed)[5]
~------------------------IWC------------------------~
ADDRESS
CS"
~~+" fool------------------scS -----------------~ /-r'7""':""""T,*T"'l""""T~r
~----------------------~w--------------------I
~-------ISA
----------I
~----I~E------~
____
14-+------- tso --------+--DATA VALID
DATA IN
tlZWE
IHZWE::j
DATA 1/0 ______~_______D_AT_A_U_N_D_E_F_IN_E_D______________
_J>
HIGH IMPEDANCE
---I
,<,..;.'- - - 1454-7
Write Cycle No.2 (CS ControlIed)[5. 9]
ADDRESS
-----------4~------~c8-----·1
----~------------------~
,-------+--------
1-+-------180 -------4jo....
DATA IN
DATA VALID
IHZWE----I
"'"""""
DATAI/O _______________D_A_TA__
UN_D_E_F_IN_E_D________________
HIGH IMPEDANCE
-Jy>-------------------------1464-8
Notes:
8. Address valid prior to or coincident with CS transition LOW.
9.
3-20
IfCS goes HIGH simultaneouslywith WEIDGH, the output remains
in a high-impedance state.
CYM1465
SI2K X 8 SRAM Module
Features
• High-density 4-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 70 ns
• Low active power
-605 mW (max.)
• 2V data retention (L Version)
• JEDEC·compatible pinout
• 32-pin, 0.6-inch-wide DIP package
• TTL-compatible inputs and outputs
• Low profile
- Max. height of 0.27 in.
• Small PCB footprint
- 0.98 sq. in.
Functional Description
The CYM1465 is a high-performance
4·megabit static RAM module organized
as 512K words by 8 bits. This module is
constructed using four 128K x 8 RAMs
mounted on a substrate with pins. A decoder is used to interpret the higher-order addresses (A17 and AlB) and to select one of
the four RAMs.
Writing to the module is accomplished
when the chip select (<:8) and write enable
(WE) inputs are both LOW Data on the
eight input/output pins (1/00 through
1/07) of the device is ~ritten into the
memory location specified on thll address
pins (Ao through AlB). Reading the device
is accomplishe>--..:.H,;;,IG;:;H:.:.;,;;IM;,;;P..:E:.;:;D~A;,,;.NC=E=--_ _ _ ___
1465·9
Note:
9.
IfCS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
Truth Table
Inputs
CS
WE
OE
H
X
X
L
H
,L
L
L
L
H
Output
Mode
HighZ
DeselectIPower-Down
Data Out
Read Word
X
Data In
Write Word
H
HighZ
Deselect
3-26
CYM1471
CYM1481
l024K X 8 SRAM Module
2048K x 8 SRAM Module
Features
Functional Description
• High-density 8-/16-megabit SRAM
modules
• High-speed CMOS SRAMs
- Access time of 85 ns
• Low active power
-605 mW (max.), 2M x 8
• Double-sided SMD technology
• TTL-compatible inputs and outputs
• Small footprint SIP
- PCB layout area of 0.72 sq. in.
• 2V data retention (L version)
The CYM1471 and CYM1481 are highperformance 8-megabit and 16-megabit
static RAM modules organized as 1024K
words (1471) or 2048K words (1481) by 8
bits. These modules are constructed from
eight (1471) or sixteen (1481) 128K x 8
SRAMs in plastic surface-mount packages
on an epoxy laminate board witli pins. Onboard decoding selects one of the SRAMs
from the high-order address lines, keeping
the remaining devices in standby mode for
minimum power consumption.
An active LOW write enable signal (WE)
controls the writin~adin~eration of
the memory. When MS and WE inputs are
both LOW, data on the eight data input/
output pins is written into the memory location specified on the address pins. Reading the device is accomplished by selec~
the device and enabling the outputs MS
and OE active LOW while WE remains inactive or HIGH. Onder these conditions,
the content of the location addressed by
the information on the address pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH.
Logic Block Diagram
Pin Configuration
r--------------------------------,
I Ao-A16
I
I
I
OE
I
I
I
I
I
WE
IA
A
I 17- 20
I
II
I
I
I
I
I
I
I
MS
~--
SIP
Top View
I
I
Q~~~~~~~~~~~l!~~~JI
CYM1471
GND
I/O.
A,o
An
I
I
~
A.
A13
A:!o(1481)~
MS(1'7')
...fMS -
A,.
A,.
A12
A,.
As
I/O,
GND
As
A7
As
As
1/07
I/O.
I/O.
A17
B
1/00-1/07 v~
Selection Guide
CYM1471
CYMl481
Maximum Access Time (ns)
85
100
120
85
100
120
Maximum Operating Current (rnA)
95
95
95
110
110
110
Maximum Standby Current (rnA)
32
32
32
64
64
64
3-28
CYM1471
CYM1481
Switching Characteristics Over the Operating Rangd 2J
1471-100
1481-100
1471-85
1481-85
Parameter
Description
Min.
Max.
Min.
1471-120
1481-120
Max.
Min.
Max.
Unit
READ CYCLE
85
100
120
ns
tRe
Read Cycle Time
tAA
Address to Data Valid
tQI-IA
Data Hold from Address Change
tAMS
MS LOW to Data Valid
85
100
120
ns
tDOE
OE LOW to Data Valid
45
50
60
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[3J
tLZMS
MS LOW to Low Z[4J
tHZMS
MS HIGH to High Z[3, 4J
100
85
10
120
5
5
ns
5
30
ns
35
10
ns
10
10
45
10
ns
10
ns
35
30
45
ns
WRITE CYCLE[5J
twe
Write Cycle Time
85
100
120
ns
tSMS
MS LOW to Write End
75
90
100
ns
tAW
Address Set-Up to Write End
75
90
100
ns
tHA
Address Hold from Write End
7
7
7
ns
tSA
Address Set-Up to Write Start
5
5
5
ns
tpwE
WE Pulse Width
65
75
85
ns
tSD
Data Set-Up to Write End
35
40
45
ns
tHD
Data Hold from Write End
5
5
5
tHZWE
WE LOW to High Z[3J
tLZWE
WE HIGH to Low Z
30
ns
35
5
40
5
ns
5
ns
Data Retention Characteristics (L Version Only)
1471-85
Parameter
Description
VDR
Vee for Retention Data
IeeDR
Data Retention Current
teDR[6J
Chip Deselect to Data
Retention Time
tR
Operation Recovery Time
Test Conditions
1471-100
1471-120
1481-85
1481-100
1481-120
Min. Max. Min. Max. Min. Max. Min. Max.
2
YnR =
3.0Y,
MS ~ Vee - 0.2Y,
VIN ~ Vee - O.2V or
VIN ~O.2V
Notes:
2. Thst conditions assume signal transition time of 10 Ils or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading
of 1 TIL load, and 100-pF load capacitance.
3. tHZOE, tHZMS, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Test Loads and Waveforms. Transition is measured ±500 mV
from steady-state voltage.
4. At any given temperature and voltage condition, tHZMS is less than
tLZMS for any given device. These parameters are guaranteed and not
100% tested.
2
2
125
400
2
V
250
800
Unit
ftA
0
0
0
0
ns
5
5
5
5
ns
5.
The internal write time of the memory is defined by the overlap of MS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
6.
Guaranteed, not tested.
3-30
CYM1471
CYM1481
.~YPRESS
Switching Waveforms (continued)
Write Cycle No. 1[5, 10]
twc
ADDRESS
~
~
I(
I
isMS
"'~ ~
""V////b '/"///~
tHA-
tAW
tSA
tPWE
-Jt"
~~~
DATA IN
*
tSD
tHD
DATA VALID
I--tHZWE:1
~tLZWE~
HIGH IMPEDANCE
DATAI/O _______________D_A_TA_U_N_D_E_F_IN_E_D______________-J)~----------------~<~
Write Cycle No. 2[5, 10, 11]
ADDRESS
-------+----IsMS - - - i
DATA IN
Notes:
10. Data 110 is high impedance if OE = VIH.
11. IfMS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
3-32
_________
1471-8
CYM1622
64Kx 16 Static RAM Module
Features
Functional Description
• High-density I-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of IS ns
• Low active power
-2.2W (max.)
• SMD tecbnology
• TTL-compatible inputs and outputs
• Pinout compatible with CYMI611
The CYM1622 is a very high performance
1-megabit static RAM module organized
as 64K words by 16 bits. The module is
constructed using four 64K x 4 static
RAMs mounted onto a vertical substrate
with pins. The pinout of this module is
compatible with another Cypress module
(CYM1611) to maximize system flexibility.
Writing to the. memory module is
accom~lished when the chip select (CS)
and WrIte enable (WE) inputs are both
L?W. Data on the sixteen input/output
pms (1/00 through 1/015) of the device is
• Low profile
- Max. height of .50 in.
• Small PCB footprint
-0.68 sq. in.
Logic Block Diagram
Ao -
written into the memory location specified
on the address pins (Ao through A15).
Reading the device is accomplished by
taking chip select (CS) and output enable
(OE) LOW, while write enable (WE)
remains inactive or HIGH. Under these
conditions, the contents of the memory
location specified on the address pins will
appear on the appropriate data
input/output pins.
The input/output pins remain in a
high-impedance state unless the module is
selected, outputs are enabled, and write
enable (WE) is HIGH.
Pin Configuration
VDIP
ThpView
A15 ----.-------~
1/°0- 1/°15
1622·1
1622·2
Selection Guide
3-34
CYM1622
Switching Characteristics Over the Operating Range[3]
3
tOHA
tDOE
o
3
30
35
45
ns
15
20
25
.30
ns
45
ns
45
ns
25
15
5.
3-36
ns
25
o
25
Notes:
3. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5\1, input pulse levels of 0 to 3.0\1, and output
loading of the specified IOIJIOH and 30-pF load capacitance.
4. tHZCS and tHzwEare specified with CL= 5 pF as in part (b) ofACThst
Loads and Waveforms. Transition is measured ±500 m V from steadystate voltage.
3
3
30
o
35
o
35
30
25
30
40
ns
3
3
3
ns
2
2
2
ns
2
2
2
ns
o
o
o
ns
o
15
o
15
o
20
ns
The internal write time ofthe memory is defined by the overlap ofCS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
~YPRESS
CYM1622
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[5, 9]
ADDRESS
----------~~------tscs----~~
----~------------------~
,-------+--------
WE
I+-+-----ISO ------........
DATA IN
DATA VALID
tHZWE----I
DATA OUT
------------------------...1
HIGH IMPEDANCE
)>--------------
DATA UNDEFINED
1622-8
Note:
9. IfCS l\oes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
1hIth Table
cs
OE WE
Input/output
Mode
X
X
HighZ
L
L
H
Data Out
Read
L
X
L
Data In
Write
L
H
H
HighZ
Deselect
H
Deselect/Power-Down
Ordering Information
Document #: 38-M-OOOOI-D
3-38
CYMl720
.;;rcYPRESS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -55°C to +125°C
Ambient Thmperature with
Power Applied ......................... -10°C to +85°C
Supply Voltage to Ground Potential ......... -O.5V to +7.0V
DC Voltage Applied to Outputs ,
in High Z State .......................... -O.5V to +7;OV
DC Input Voltage ........................ -0.5V to + 7.0V
Operating Range
Range
Commercial
Ambient
Thmperature
Vee
DoC to +70°C
5V± 10%
Electrical Characteristics Over the
ICC
330
rnA
ISBl
60
mA
60
rnA
Capacitance[2]
Parameter
Description
CIN
Input Capacitance
CoUT
Output Capacitance
Thst Conditions
Max.
Unit
35
pF
25
pF
= 25°C, f = 1 MHz,
Vee = 5.0V
TA
Notes:
1. A pull·up resistor to Vee on the CS input is required to keep the de·
vice deselected during V ccpower·up, otherwise ISB will exceed values
given.
2.' Thsted on a sample basis.
AC Test Loads and Waveforms
eo
eo
ALL INPUT PULSES
OUTP~~ ~ OUTP~~ ~
,~~.~:FI
,~ .•~:F1
I 1
_2550
1 1
_2550
INCLUDING
JIG AND
SCOPE
-
-
INCLUDING
JIG AND
SCOPE
(a) Normal Load
Equivalent to:
-
90%
GND
-
1720-3
(b) High.Z Load
THEVENIN EQUIVALENT
OUTPUT~
3.0V---
1,73V
3-40
1720-4
CYMl720
(;;EYPRESS
Switching Waveforms
Read Cycle No. 1[7,8]
~
ADDRESS
'"
------i--L~
DATA OUT
PREVIOUS DATA VALID
*-
IRC
1
'XXX*==============DA=T=A=V=AL=ID==========
1720-5
Read Cycle No. 2[7, 9]
IRC
~~
~
"lACS
{
IHZOE-
lOOE
-tLZOE-
HIGH IMPEDANCE
DATA OUT
ILZCS
-lpU
VCC
-tHZCS-
'L./L
DATA VALID
,-"
HIGH
IMPEDANCE
./
-Ipo
~ ... 50%
--.Jf
~ CC
I
50%
SUPPLY _ _ _ _ _ _
CURRENT
ISB
1720-6
Write Cycle No.1 (WE Contrillled)[6, 10]
IWC
ADDRESS ~
)(
---/
,,~
Iscs
~
V////~ ~/////
lAW
IHA-
!sA
IpWE
~~~
DATA IN
I"
tHO
Iso
*
DATA VALID
-----------------~)
I---IHZWE
DATA I/O
DATA UNDEFINED
•
----------------------------~
Notes:
7_ WE is HIGH for read cycle_
8_ Device is continuously selected, CS = VIL and 00= VIL-
I--ILZWE
HIGH IMPEDANCE---j(,----1720-7
9. Address valid prior to or coincident with CS transition LOW.
10. Data I/O will be high impedance if 00 = VIH.
3-42
CYM1730
PRELIMINARY
64K x 24 Static RAM: Module
Features
Functional Description
• High.density 1.5M SRAM module
• High·speed CMOS SRAMs
- Access time of 25 ns
• 56.pin, 0.5.inch.high ZIP package
• Low active power
-2.SW (max. for tAA '" 25 ns)
• SMD technology
• TTL·compatible inputs and outputs
• Commercial temperature range
• Small PCB footprint
-1.05 sq. in.
The CYM1730 is a high·performance
l.5M static RAM module organized as
64K words by 24 bits. This module is con·
structed using six 32K x 8 static RAMs in
SO] packages mounted onto an epoxy lam·
inate board with pins.
Writing to the device is accomplishedwhen
the chip select (CS) and write enable (WE)
inputs are both LOW: Data on the input/
output pins (VOo through V023) of the device is written into the memory location
specified on the address pins (Ao through
A1S)·
~eading the device is accomplished bytakil!£!he chip select (r:8) and output enable
(OE) LOW while write enable (WE) remainsIDGH. Under these conditions, the
contents of the memory location specified
on the address pins will appear on the input/output pins.
The input/output pins remain in ahigh-impedance state unless the module is selected, outputs are enabled, and write enable is IDGH.
Logic Block Diagram
Ao- A , •
OJ:
WE
Pin Configuration
...
/15
ZIP
ThpView
f-- f - - 32Kx8
SRAM
I
-
10F2
DECODER
rr- r-
-
SRAM
I I
I
L-.
L--
~
8
1/0 ,6 - 1/023
32Kx8
SRAM
1/0 9
1/0"
1/0 ,3
1/0 ,5
NC
OJ:
/8
I/Oa -1/0'5
I
I
T
L--
As
A"
A'3
'-32Kx8
SRAM
~
A7
NC
GND
I I
T
1/02
I/0.
1/0 5
1/07
GND
A,
~
r- ~
1/°0
1/0,
1/°3
32Kx8
SRAM
I
1
f-f-- 32Kx8
T
r- -
Vee
vee
,...-
A'5
32Kx8
SRAM
GND
I I
1/023
1/0 17
1/0,9
1/°21
...
8
1/00 -1/0 7
1730-1
Vee
1/0 6
10
12
14
16
Ao
18
20
22
cs
GND
~
A.
Ae
NC
II0a
1/°10
1/°,2
1/0 ,.
GND
24
28
28
30
32
31
34
38
WE
Aa
A'0
A'2
38
40
42
44
46
48
50
52
54
56
41
A"
GND
1/0 ,6
1/0 ,8
1/°20
1/°22
51
Vee
55
173()"2
Selection Guide
1730-25
1730-30
1730-35
Maximum Access Time (ns)
25
30
35
Maximum Operating Current (rnA)
510
510
510
Maximum Standby Current (mA)
180
180
180
3-44
~YPRESS
PRELIMINARY
CYM1730
Switching Characteristics Over the Operating Range[3J
'.
Parameter
1730-25
Description
Min.
Max.
1730-30
Min.
Max.
1730-35
Min.
Max.
Unit
READ CYCLE
tRe
Read Cycle Time
tAA
Address to Data Valid
tORA
Output Hold from Address Change
tACS
"CS LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
DE LOW to Low Z
tHZOE
qE HIGH to High Z
tLZCs
L:S LOW to Low Z[4J
tHZCS
CS HIGH to High Z[4,5J
25
35
30
25
5
30
5
25
15
3
10
ns
ns
20
.
15
10
35
20
ris
ns
5
15
ns
ns
3
5
5
ns
5
30
12
3
ns
35
15
ns
WRiTE CYCLE[6J
twe
Write Cycle Time
25
30
35
ns
tscs
L:S LOW to Write End
20
25
30
ns
tAW
Address Set-Up to Write End
22
25
30
ns
tRA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Starr
2
2
2
ns
tPWE
WE Pulse Width
20
23
25
ns
tSD
pata Set-Up to Write End
13
15
20
ns
tHD
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z
3
3
5
tHZWE
WE LOW to High Z[5J
0
Notes:
3. Thst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5Y, input pulse levels of 0 to 3.0Y, and output loading
of the specified IOl/IoH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device.
5. tHZOE, tHZCS, and tLZcEare specified with CL = 5 pF as in part (b) of
AC Thst Loads and Waveforms. 'ifansition is measured ±500 mV from
steady-state voltage.
6.
3-46
10
0
10
0
ns
15
ns
The internal write time ofthe memory is defined by the overlap ofCS
LOW and WIlLOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
PRELIMINARY
CYM1730
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[6, 10, 111
------+---- tscs - - - I
----~------------------~
r------~-------
t-+--- Iso - - -......
DATA VALID
IH.ZWE~
--...1
HIGH IMPEDANCE
-J»-------------------------
DATA OUT _______________D_A_TA__
UN_D_E_F_IN_E_D________________
1730-9
Note:
11.
IfCS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
Truth Table
CS
WE
OE
H
X
X
L
H
L
L
L
H
H
Input/Outputs
Mode
HighZ
DeselectIPower-Down
L
Data Out
Read Word
X
Data In
Write Word
HighZ
Deselect
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package lYPe
Operating
Range
25
CYM1730PZ-25C
PZ07
56-Pin ZIP Module
Commercial
30
CYM1730PZ- 30C
PZ07
56-Pin ZIP Module
Commercial
35
CYM1730PZ- 35C
PZ07
56-Pin ZIP Module
Commercial
Document #: 38-M-00049-A
3-48
~YPRESS
CYM1821
Maximum Ratings
Operating Range
(Above which the useful life may be impaired.)
Range
Storage Thmperature ................... -65°C to + ls0°C
Ambient Thmperature with
Power Applied ......................... -10°C to +85°C
Supply Voltage to Ground Potential ......... -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -0.5V to +7.0V
DC Input Voltage ........................ -O.5V to +7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Commercial
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
1821-20
1821-25
1821-35
1821-45
1821-12
1821-15
Parameter
Description
Test Conditions
Max.
Unit
0.4
V
2.2
Vee
V
-0.5
0.8
V
-20
+20
-20
+20
fAA
fAA
-350
-350
rnA
~e
960
720
rnA
Automatic CS
Power-Down Current[2]
Max. Vee, CS ~ VIH,
Min. Duty Cycle = 100%
450
160
rnA
Automatic CS
Power-Down Current[2]
Max. Vee, CSN ~ Vee - 0.3\1,
VlN ~ Vee - O.3V or VlN S. O.3V
160
160
rnA
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Min.
Max.
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
2.2
Vee
VIL
Input LOW Voltage
-0.5
0.8
IIX
Input Load Current
GND S. VI S. Vee
-20
+20
loz
Output Leakage Current
GND S. Vo S. Vce. Output Disabled
-20
+20
los
Output Short Circuit Currentl l ]
Vee
lee
Vee Operating Supply Current
ISBI
ISB2
Vee
Min.
2.4
2.4
0.4
= Max., VOUT = GND
= Max., lOUT = 0 rnA,
S. VIL
V
Capacitance[3]
Parameter
Description
Test Conditions
ClNA
Input Capacitance (ADDR, DE, WE)
CINB
Input Capacitance (CS)
COUT
Output Capacitance
Noles:
1. Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vcc power-up, otherwise ISB will exceed values
given.
.
TA - 25°C, f - 1 MHz,
Vee = 5.0V
3.
3-50
"Iested on a sample basis.
Max.
Unit
70
pF
35
pF
20
pF
~CYPRESS
CYM1821
Switching Characteristics Over the Operating Range (continued)[4]
1821-35
1821-25
Parameter
Description
Min.
Max.
Min.
Max.
1821-45
Min.
Max.
Unit
READ CYCLE
25
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
"CS LOW to Data Valid
25
35
45
ns
tDOE
OE LOW to Data Valid
15
25
30
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
tLZCS
.CS LOW to Low Z[5]
tHZCS
CS HIGH to High Z[5, 6]
tpu
CS LOW to Power-Up
tPD
"CS HIGH to Power-Down
35
3
45
35
25
3
3
3
3
15
5
0
15
0
25
ns
20
ns
20
ns
10
10
ns
0
35
ns
ns
3
20
10
ns
45
ns
45
ns
WRITE CYCLEr?]
twc
Write Cycle Time
25
35
45
ns
tscs
"CS LOW to Write End
20
25
35
ns
tAW
Address Set-Up to Write End
20
25
35
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tpWE
WE Pulse Width
20
25
30
ns
tSD
Data Set-Up to Write End
13
15
20
ns
tHD
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z
3
5
5
tHzWE
WE LOW to High Z[6]
0
3-52
7
0
10
0
ns
15
ns
1l~YPRESS
CYM1821
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[7, 11J
ADDRESS
----------~~~----~cs------~
--~------------------~
,------+-------
~+_-----~D----~~
DATA IN
----------------------~
DATA VALID
tHZWE---I
DATA OUT
---------------------~ I
HIGH IMPEDANCE
)>--------------
DATA UNDEFINED
1821-8
Note:
11.
If'CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
TrutlI Table
CSN WE OE
Inputs/outputs
Mode
X
HighZ
DeselectIPower-Down
H
L
Data Out
Read
L
X
Data In
Write
H
H
HighZ
Deselect
H
X
L
L
L
Ordering Information
S~ed
12
15
20
25
35
45
Package
Name
CYM1821PM -12C
PMOI
Package
1YPe
64-Pin Plastic SIMM Module
CYM1821PZ-12C
PZOI
64-Pin Plastic ZIP Module
Ordering Code
CYMI821P¥'''': 15C
PMOI
64-Pin Plastic SIMM Module
CYMI821PZ-15C
PZOI
64-Pin Plastic ZIP Module
CYM1821PM - 20C
PMOI
64-Pin fhistic SIMM Module
CYMI821PZ-20C
PZOI
64-Pin Plastic ZIP Module
CYM1821PM - 25C
PMOI
64-Pin Plastic SIMM Module
CYMI821PZ.,. 25C
PZOI
64-Pin PlaStic ZIP Module
CYM1821P¥ - 35C
PMOI
64-Pin Plastic SIMM Module
CYMl82lPZ-35C
PZOl
64-Pin Plastic ZIP Module
CYM1821PM -45C
PMOI
~4-Pin
CYMl82lPZ-45C
PZOl
64-Pin Plastic ZIP Module
Plastic SIMM Module
Document #: 38-M-000l5-E
3-54
Operating
Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
~YPRESS
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired.)
CYM1828
Operating Range
Range
Storage Thmperature ................... -65°C to + 150°C
Supply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to +7.0V
DC Input Voltage ........................ -O.5V to +7.0V
Commercial
Military
Ambient
Temperature
Vee
O°Cto +70°C
5V::!: 10%
-55°C to + 125'C
5V::!: 10%
Electrical Characteristics Over the Operating Range
1828
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
Min.
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
GND~ VI~
Vee, Vee
Max.
Unit
2.4
Vee
= Max.
V
0.4
V
2.2
Vee+ O.3
V
-0.3
0.8
V
-20
+20
-20
+20
!lA
!lA
600
rnA
Ioz
Output Leakage Current
GND ~ Vo ~ Vee, Output Disabled
IeCx32
Vee Operating Supply Current
by 32 Mode
Vee
Vee Operating Supply Current
by 16 Mode
Vee - Max., lOUT - 0 rnA,
Vee Operating Supply Current
bySMode
Vee
ISBl
Automatic CS Power-Down
Current[l]
Max. Vee; CS ~ VIH,
Min. Duty Cycle = 100%
200
rnA
ISB2
Automatic es Power-Down
Currentl l ]
Max. Vee; CS ~ Vee - 0.2V;
VIN ~ Vee - 0.2VorVIN~0.2V
100
rnA
IeCxl6
IeCxB
= Max., lOUT = 0 rnA,
es~VIL
LVersion
CS~VIL
400
360
LVersion
230
= Max., lOUT = 0 rnA,
CS~VIL
rnA
240
L Version
rnA
145
Capacitance[2]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
= 25°C, f = 1 MHz,
Vee = 5.0V
TA
Notes:
1.
A pull-up resistor to Vee on the CS ioput is required to keep the device deselected during V ccpower-up, otherwise ISB will exceed values
given.
2.
3-56
'Jested on a sample basis.
Max.
Unit
50
pF
20
pF
PRELIMINARY
.fI2YPRESS
CYM1828
Switching Characteristics Over the Operating Range (continued)[3]
1828-45 '
Parameter
Description
Min.
Max.
1828-70
1828-55
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
45
55
45
70
3
3
ns
70
55
3
ns
ns
tACS
CS LOW to Data Valid
45
55
70
ns
tDOE
OE LOW to Data Valid
25
30
35
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z[4]
0
0
25
3
3
: CS HIGH to High Z[4, S]
tijZCS
WRITE CYCLE[6]
0
30
25
ns
30
ns
30
ns
3
30
ns
twc
Write Cycle Time
45
55
70
ns
tscs
CS LOW to Write End
40
45
55
ns
tAW
Address Set-Up to Write End
40
45
55
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
30
35
45
ns
tSD
Data Set-Up to Write End
25
30
40
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z
0
0
0
tHZWE
WE LOW to High Z[S]
0
30
0
30
0
ns
30
ns
Data Retention Characteristics (L Version Only)
1828
Parameter
Description
Test Conditions
VDR
V CC for Retention Data
CS~ Vcc - 0.2V
ICCDR3
Data Retention Current
tCDR[7]
Chip Deselect to Data Retention Time
CS ~ Vcc - 0.2Y,
VIN ~ Vee - 0.2Vor
VIN.s 0.2Y, VDR = 3.0V
tR[7]
Operation Recovery Time
Note:
7. Guaranteed, not tested.
3-58
Min.
Max.
Unit
320
!LA
2
V
0
ns
tRC
ns
PRELIMINARY
CYM1828
Switching Waveforms (continued)
Write Cycle No.1 (WE ControUed)[6, 11]
Iwe
ADDRESS
~~
j~
Ises
~
.I)/////~ ~/////
-0.~ ~
..
lHA-
lAW
!sA
tpWE
~~~~
WE
Iso
*
DATA IN
IHO
DATA VALID
-tI2WE~
~tHZWE::j
HIGH IMPEDANCE
-J)>----------«"'_____
DATA I/O _ _ _ _ _ _ _ _D_A_TA_U_ND_E_F_IN_E_D_ _ _ _ _ _ _
1828-8
Write Cycle No.2 (CS ControIIed)[6, 11, 12]
ADDRESS
----------~~-----tses---~~
----+-------------------~
,-------+--------
14-+----- Iso --------.jo....
DATA IN
DATA VALID
IHZWE---I
DATA 1/0
-----------------------...1
HIGH IMPEDANCE
)>------...--------
DATA UNDEFINED
1828-9
Notes:
11. Data I/O will be high impedance ifOE ~ VlH.
12. If CSN goes HIGH simultaneously with WEN HIGH, the output remains in a high-impedance state.
3-60
CYM1831
64K X 32 Static RAM Module
Features
Functional Description
• High-density 2-Mbit SRAM modnle
• 32-bit standard footprint supports
densities from 16K x 32 tbrough
IMx32
• High-speed CMOS SRAMs
- Access time of 15 ns
• Low active power
- 5.3W (max.)
• SMD technology
• TTL-compatible inputs and outputs
• Low prolile
- Max. height of .50 in.
• Small PCB footprint
-1.2 sq. in.
The CYM1831 is a high-performance
2-Mbit static RAM module organized as
64K words by 32 bits. This module is constructed from eight 64Kx 4 SRAMs in SOJ
packages mounted on an epoxy laminate
board with pins. Four chip selects (CSt.
CSz, CS3, and CS4) are used to independently enable the four bytes. Reading or
writing can be executed on individual bytes
or any combination of multiple bytes
through proper use of selects.
Writing to each byte is accomplished when
the appropriate chip selects (CSN) and
write enable (WE) inputs are both LOW.
Data on the input/output pins (l/Ox) is
written into the memory location specified
on the address pins (Ao through A15).
Logic Block Diagr!lm
Reading the device is accomplished bytaking the chip selects (CSN) LOW and output enable (OE) LOW while write enable
(WE) remains HIGH. Under these conditions the contents ofthe memory location
specified on the address pins will appear on
the data input/output pins (l/Ox).
The data input/output pins stay in the 1tigI1impedance state when write enable (WE)
is LOW or the appropriate chip selects are
HIGfI.
Tho pins (PDa and PD1) are used to
identify module memory density in applications where alternate versions of the
JEDEC-standard modules can be interchanged.
Pin Configuration ZIP/SIMM
Top View
Ao - A15 -'~16--""'-----------"
PDO - OPEN
PD1 - GND
rgg
1/01
1/02
1/°3
m: -----,-+---------,
~---,-~----------------~
10
12
14
16
18
20
22
24
26
28
30
32
Vee
A7
As
I/~
CS1 ----~t;--~--------------rt~--~
1/0 5
1/°6
I~
I/OB -1/011
A14
CSl
CS2----~t;--~--------------rt~--~
33
34 35
36 37
3B 39
40 41
42 43
44 45
46 47
~a
GND
1/°16
1/0 17
1/0 1B
1/°19
A10
A11
A12
A13
1/°20
CS3----~t;--~--------------rt~--~
CS4----------~--------------------~
11
13
15
17
19
21
23
25
27
29
31
48
50
52
54
56
58
60
62
64
1/0 21
1/°22
1/°23
GND
49
51
53
55
57
59
61
83
GND
PD1
I/OB
1/°9
1/°10
1/°11
Ao
Al
A2
1/012
1/0 13
1/014
1/°15
GND
~2
CS4
NC
OE
1/°24
1/025
1/026
1/°27
As
~
Vee
Ai;
1/0 2B
1/°29
1/°30
1/°31
1831·2
Selection Guide
1831-15
1831-20
1831-25
1831-30
1831-35
15
20
25
30
35
45
Maximum Operating Current (rnA)
1120
960
720
720
720
720
Maximum Standby Currellt (rnA)
160
160
160
160
160
160
Maximum Access Time (ns)
3-62
1831-45
CYM1831
Q:YPRESS
Switching Characteristics Over the Operating Rangd3]
1831-15
Description
Parameter
Min. Max.
1831-20
Min.
1831-25
1831-30
1831-35
1831-45
Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from
Address Change
15
20
3
30
25
15
25
20
3
3
35
30
3
45
35
3
ns
45
ns
3
ns
CS LOW to Data Valid
15
20
25
30
35
45
ns
tOOE
em LOW to Data Valid
8
10
15
20
20
30
ns
tLZOE
OE LOW to Low Z
tACS
tHZOE
em LOW to High Z
tLZCS
CS LOW to Low Z14j
tHZCS
CS HIGH to High Z14, Sj
0
0
0
8
0
0
15
10
0
3
8
6
0
15
3
13
0
20
3
15
ns
20
ns
3
20
ns
20
ns
WRITE CYCLE[6]
twc
Write Cycle Time
15
20
25
30
35
45
ns
tscs
CS LOW to Write End
10
15
20
25
30
40
ns
tAW
Address Set-Up to
Write End
10
15
20
25
30
40
ns
tHA
Address Hold from
Write End
2
2
2
2
2
2
ns
tSA
Address Set-Up to
Write Start
2
2
2
2
2
2
ns
tpWE
WE Pulse Width
10
15
20
25
25
Data Set-Up to Write End
8
12
15
15
20
30
20
ns
tso
tHO
Data Hold from Write End
2
2
2
2
2
2
ns
tLZWE
WE HIGH to Low Z
3
3
3
3
3
3
tHZWE
WE LOW to High Zpj
0
7
0
10
Notes:
3, Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5Y, input pulse levels of 0 to 3,0Y, and output
loading of the specified IOIfloH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device. These parameters are guaranteed by design and not 100% tested.
5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Thst
Loads and Waveforms. 'Iransition is measured ±500 m V from steadystate voltage.
0
6.
7.
8.
13
0
15
0
20
0
n.
ns
20
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both siguals must be LQWto initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the sigual
that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected, CS = VIL and OE= VIL.
Switching Waveforms
Read Cycle No. 1[7,8]
'L'-"'
~
IRC
1
AOORESS _____......
DATA OUT
*---
PREVIOUS DATA VALID 'XXX*===============O=A=TA=V=A=L=IO===========
1831·5
h64
'~YPRESS
CYM1831
Truth Table
OE
Inputs/Outputs
X
HighZ
H
L
Data Out
Read
L
X
Data In
Write
H
H
HighZ
Deselect
CSN WE
H
X
L
L
L
Mode
Deselect!Power-Down
Ordering Information
Speed
15
20
ZS
30
35
45
Ordering Code
Package
Name
Package
'lYpe
CYM1831PM-15C
PMOl
64-Pin Plastic SIMM Module
CYM1831PN -15C
PNOI
64-Pin Plastic Angled SIMM Module
CYM1831PZ-15C
PZOI
64-Pin Plastic ZIP Module
CYM1831PM-20C
PMOI
64-Pin Plastic SIMM Module
CYM1831PN-20C
PNOI
64-Pin Plastic Angled SIMM Module
CYM1831PZ-20C
PZOI
64-Pin Plastic ZIP Module
-CYM1831PM-ZSC
PMOI
64-Pin Plastic SIMM Module
CYM1831PN.,.25C
PNOl
64-Pin Plastic Angled SIMM Module
CYM1831PZ"::ZSC
PZOI
64-Pin Plastic ZIP Module
CYM1831PM -30C
PMOI
64-Pin Plastic SIMM Module
CYM1831PN-30C
PNOI
64-Pin Plastic Angled SIMM Module
CYM1831PZ':"30C
PZOI
64-Pin Plastic ZIP Module
CYM1831PM-35C
PMOI
64-Pin Plastic SIMM Module
CYM1831PN -35C
PNOI
64-Pin Plastic Angled SIMM Module
CYM1831PZ-35C
PZOI
64-Pin Plastic ZIP Module
CYM1831PM -45C
PMOI
64-Pin Plastic SIMM Module
CYM1831PN -45C
PNOI
64-Pin Plastic Angled SIMM Module
CYM1831PZ-45C
PZOI
64-Pin Plastic ZIP Module
Document #: 38-M-00018-E
3-66
Operating
Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
CYM183~
1srcYPRESS
Maximum Ratings
Operating Range
(Above which the us/?fullife may be impaired.)
Range
Storage Thmperature ................... -45°C to +125°C
Anlbient Thmperature with
Power Applied ......................... -l00C to +85°C
Supply Voltage to Ground Potential ......... -O.5V to +7.OV
DC 'Voltage Applied to Outputs
in High Z State .......................... -O.5V to +7.OV
DC Input Voltage ........................ -0.5V to +7.OV
Output Current into Oq~puts (LOW) ............... 20 rnA
Commercial
Ambient
Temperature
Vee
O°C to +70°C
5V± 10%
Electrical Characteristics Over the Operating Range
CYM1832
Parameter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Test Conditions
Min.
= Min.,loH = - 4.0 rnA
Vee = Min., IOL = 8.0 mA
VIL
Input LOW Voltagel l ]
IIX
Input Load Current
GNDsVrsVee
loz
Output Leakage Current
GND s Va s Vee, Output Disabled
Icc
Vee Operating Supply Current
Vee
ISBl
Automatic
Power-Down Current[2]
ISB2
Automatic
Power-Down Currend2]
c:s
c:s
Unit
V
2.2
= Max., lOUT = 0 rnA, C:SN S
Max.
2.4
Vee
0.4
V
Vee
V
-0.5
0.8
V
-20
+20
-100
+100
IJA
IJA
980
rnA
Max. Vee, C:SN.2!. VIH,
Min. Duty Cycle = 100%
240
rnA
Max. Vee, C:SN .2!. V ee ~ 0:2Y,
VIN .2!. V cc - 0.2V or VIN s 0.2V
120
rnA
VIL
Capacitance!3]
Parameter
Test Conditions
Description
CINA
Input Capacitance (Ax, WE)
CINB
Input Capacitance ("CS)
COUT
Output Capacitance
TA = 25°C, f
Vee = 5.0V
Notes:
1. VIL(min.) = -3.0V for pulse widths less than 20 ns.
2. A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vccpower-up, othetwise ISB will exceed vajues
= 1 MHz,
3. 'Iested on a sample basis.
given.
3-68
Max.
Unit
60
pF
25
pF
15
pF
~CYPRESS
CYM1832
Switching Waveforms
Read Cycle No. tl8,9]
~
ADDREss _ _ _ _
DATA OUT
---'l_L~
PREVIOUS DATA VAUD
"'
*-
tRC
1
'XXX*=~============D_A-:r=A=V_A-L=ID==========
M1832·5
Read Cycle No. 2[9, 10]
tRC
~.
/~
K..
tACS
-tHZCS-
tLZCS
HIGH IMPEDANCE
DATA OUT
1/// . /
HIGH
IMPEDANCE
DATA VALID
1"'''-
_tpo __
i---tpU
- ICC
VCC
50%
50%
SUPPLY
CURRENT
~I S6
M1832-6
Write Cycle No.1 (WE Controlled)(7]
twc
ADDRESS
:=)~
tscs
"'~ ~~
/V////~
tSA
tPWE
~
DATA IN
j//////
tHA-
tAW
/
tHO
tso
*
DATA VALID
-tHzwE
j
-tLZWE.~
HIGH IMPEDANCE
DATA OUT _ _ _ _ _ _ _ _ _D_A_TA_UN_D_E_F_IN_E_D_ _ _ _ _ _ _-J)~--------~<~_~---
Noles:
8. Device is continuously selected, CS = VIL.
9. WIi is HIGH for read cycle.
M1832·7
10. Address valid prior to or coincident with CS transition LOW.
3-70
CYM1836
128K X 32 Static RAM Module
• Available in SIMM, ZIP format.
SIMM suitable for vertical or angled
sockets.
Features
• High-density 4-megabit SRAM
module
• 32-bit standard footprint supports
densities from 16K x 32 tbrough
IMx32
Functional Description
The CYM1836 is a high-performance
4-megabit static RAM module organized
as 128K words by 32 bits. This module is
constructed from four 128Kx 8 SRAMs in
SOJ packages mounted on an epoxy laminate board witi!.Fins. Four chip selects
(CSb CS2. CS3. CS4) are used to independently enable the four bytes. Reading or
writing can be executed on individual bytes
or any combination of multiple bytes
through proper use of selects.
• High-speed CMOS SRAMs
- Access time of 15 ns
• Low active power
-2.6W (max.) at 20 ns
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of 0.57 in.
• Small PCB footprint
-0.78 sq. in.
IDGH.
1\vo pins (PDo and PD1) are used to identify module memory density in applications
where alternate versions of the JEDECstandard modules can be interchanged.
Pin Configuration
ZIP/SIMM
Top View
PDo-OPEN
PD,-0PEN
OE
The data input/output pins stay at the highimpedance state when write enable is
LOW or the appropriate chip selects are
Writing to each byte is acco11!E!!shed when
the appr.2E!!ate chip select (CS) and write
enable (WE) inputs are both LOW. Data
Logic Block Diagram
~-A'6
on the input/output pins (I/O) iswritten
into the memory location specified on the
address pins (Ao through A16)'
Reading the device is accomplished bytaking the ~ select (CS) LOW while write
enable (WE) remains HIGH. Under these
conditions, the contents of the memory location specified on the address pins will appear on the data input/output pins (I/O).
PD,
17
1100
110,
110.
I/Ds
WE
Vee
•
1/0 0
A,
-IiCr
A,
As
110.
110.
110.
110,
WE
CS,
•
1/08 -1/0 '5
A,.
CS,
CS2
Cl!a
A,.
•
GND
1/0,8 -1/0 23
11O"
I/O"
110"
1/0,.
CS3
• 1/024 -
A"
A"
A,.
11031
A13
I/a.o
110.,
CS.
1/°22
I/O..
GND
GND
PD,
2
•
I/O,
I/o"
6
8
'0 11
12 13
15
18 17
18 19
20 21
22 23
2. 25
28 27
28 29
30
3'
32
~
33
CS.
,.
34
38
38
40
42
4.
46
46
50
52
54
56
58
60
62
84
1/0 ,0
va"
Ao
A,
As
1/0,2
1/0,3
1/°,4
1/0"
GND
35
NC
37
OE
I/O..
110..
110..
110.,
39
41
43
45
47
49
51
53
55
57
59
61
63
Aa
~
A,
Vee
A,
1/°28
I/O..
I/O,.
I/Ds,
1838-2
Selection Guide
3-72
~YPRESS
IOHA
CYM1836
3
3
3
3
ns
3
lACS
20
25
30
35
45
ns
IDOE
8
8
10
12
15
ns
ILZOE
0
8
IHZOE
ILZCS
0
0
10
3
10
ns
0
12
11
10
3
3
0
3
15
ns
3
18
13
ns
ns
15
18
20
25
ns
o
o
o
o
ns
o
o
o
o
ns
o
o
o
o
o
ns
o
o
o
o
o
ns
lHA
o
8
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
5. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device. These parameters are gnaranteed by design and not 100% tested.
6. tHZCS and tHZWE are specified witb CL = 5 pF as in part (b) of AC Thst
Loads and Waveforms. nansition is measured ±SOO mV from steadystate voltage.
o
7.
10
o
15
o
15
o
18
ns
The internal write time of the memory is defined by the overlap of<::S
LOW and WIlLOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
CYM1836
WrcYPRESS
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[7, 11]
ADDRESS
----------~~----~cs----~~
----~------------------~
,------~-------
~+------~D------~~
DATA IN ----------------------~
DATA VALID
tHZWE--I
~I
HIGH IMPEDANCE
DATA OUT _______________D_A_TA__
UN_D_E_F_IN_E_D________________-J)~-----------------------1836-8
'fruth Table
CSN
WE
OE
H
X
X
HighZ
DeselectlPower-Down
Read
Input/Outputs
Mode
L
H
L
Data Out
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
Ordering Information[12]
25
30
Commercial
35
Commercial
45
Commercial
Notes:
11. IfCS goes HIGH simultaneously with WE HIGH, the output remaius
in a high-impedaoce state.
12. 64-pin SIMM suitable for use in aogled SIMM aplications.
Document #: 38- M -00050- B
3-76
·~YPRESS
PRELIMINARY
CYM1838
Operating Range
MaximuJii Ratings
(Above which the useful life may be impaired.)
Ambient
Temperature
Vee
O°Cto +70°C
SV:t 10%
-SsoC to +12SoC
SV:t 10%
Range
Storage Temperature ............. : ..... -6SoC to +lS00C
Supply.V'Oltalle to Ground Potential .......... -O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State .......... ; ............... -O.SV to + 7.0V
DC Input Voltage .......•................ -O.SV to +7.0V
Commercial
Military
Electrical CharaCteristics Over the Operating Range
1838
Parameter
Min.
Test Conditions
Description
VOR
Output HIGH Vol,age
Vcc = Min., lOR = - 4.0 rnA
VOL
Output LOW Voltage
Vcc = Min., 10L = 8.0 rnA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input LOad Current
loz
Max.
2.4
Unit
V
0.4
V
2.2
6.0
V
-0.3
0.8
V
GND5- VI 5- Vcc, Vcc = Max.
-10
+10
Output Leakage Current
GND 5- Vo 5- Vcc, Output Disabled
-10
+10
t-tA
t-tA
ICCx3Z
V CC Operating Supply Current
by 32 Mode
V CC = Max., lOUT = 0 rnA, CS 5- VIL
720
rnA
ICCxl6
V cc Operating Supply Current
by 16 Mode
Vcc';; Max., lOUT = 0 rnA, CS 5- VIL
480
rnA
ICCx8
V cc Operatirig Supply Current
by8Modll
Vcc = Max., lOUT = 0 rnA, CS 5- VIL
360
rnA
ISBI
Automatic CS Power-Down
Currentl l ]
Max. V cc; CS ~ VIH, Min. Duty Cycle = 100%
240
rnA
ISBZ
Automatic CS Power-Down
Currentl l ]
Max. V cc; CS ~ V cc - 0.2Y,
VIN ~ Vcc - 0.2V or VIN 5- 0.2V
40
rnA
.
Capacitance[2]
Parameter
Description
CIN
Input Capac.ititnce
CQUT
Output Capacitance
Test Conditions
TA = 2SoC, f = 1 MHz,
Vcc= S.OV
Note.:
1. A pull·up resistor to V cc on the CS input is required to keep the de·
vice deselected during Vccpower·up, otherwise ISB will exceed values
given.
2.
Max.
Unit
SO
pF
SO
pF
Thsted on a sample basis.
AC Test Loads aDd Waveforms
R1 4610
ALL INPUT PULSES
R1 4610
OUTP~~ ~R2 OUTP~~ ~
I
30 PF
j~8~'mlNG
SCOPE
255Q
=
=
5 PF
j~8~'mlNG
SCOPE
=
90%
R2
255Q
=
(b) High.Z Load
(a) Normal Load
Equivalent to:
I
3.0V---
THEVENIN EQUIVALENT
OUTPUT~
1.73V
3-78
GND
1~
1838-4
~YPRESS
PRELIMINARY
CYM1838
Switching Waveforms
Read Cycle No. 1[7.8]
1838-5
Read Cycle No. 2[7. 9]
tAC
~,
lACS
~"
):
lDOE
IHZOE-IHZCS-
I
I---ILZOE~
HIGH IMPEDANCE
DATA OUT
ILZCS
/ / /
HIGH
" IMPEDANCE
DATA VALID
I" "-"-
/
1838·6
Write Cycle No.1 (WE Controll~d)[6. 10]
ADDRES.S
=>
"'~
IWC
)~
I
tscs
~~
)'V////~ ~///~
tAW
tHA-
tSA
WE
tPWE
~~
DATA IN
~
tso
*
tHO
DATA VALID
~tHZWE
~ILZWE
")j,....-------~-.\._____
DATA 1/0 _ _ _ _ _ _ _ _D_A_TA_UN_D_E_F_IN_E_D_ _ _ _ _ _ _ _
HIGH IMPEDANCE
1838-7
Notes:
7. WliN is HIGH for read cycle.
8. Device is continuously selected. (;S = VIL and 00= VIL.
9. Address valid prior to or coincident with CS transition LOW.
10. Data I/O will be high impedance if 00 = VIH'
3-80
CYM1840
256K x 32 Static RAM Module
Features
Functional Description
• High-density 8-megabit SRAM
modnle
• High-speed CMOS SRAMs
- Access thne of 20 ns
• Independent byte and word controls
The CYM1840 is a high-performance
8-megabit static RAM module organized
as 256K words by 32 bits. This module is
constructed from eight 256Kx 4 SRAMs in
SOJ packages mounted on an epoxy laminate substrate with ~s. Four chip selects
(CSo, CSlo CS2, and CS3) are used to independentl~able the four bytes. Two write
enables (WEo and WEI) are used to independently write to either the upper or
lower 16-bit word of RAM. Reading or
writing can be executed on individual bytes
or on any combination of multiple bytes
through the proper use of selects and write
enables.
• Low active power
- 6.2W (max.)
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of .350 in.
• Small PCB footprint
-1.8 sq. in.
Logic Block Diagram
Writing to each byte is accom..£!!shed when
the appr~ate chip select (CS) and write
enable (WE) inputs are both LOW. Data
on the input/output pins (IIOx) is written
into the memory location specified on the
address pins (Ao through A17).
Reading the device is accomplished by
taking the chi~lects (CS) LOW, while
write enables (WE) remain HIGH. Under
these conditions the contents of the memory location specified on the address pins
will appear on the data input/output pins
(I/O).
The data input/output pins stay in the~
impedance state when write enables (WE)
are LOW or the appropriate chip selects
are HIGH.
Pin Configuration
DIP
Top View
AO - A17
18
WEo
CSo
CS1
WE1
CS2
Selection Guide
1840-20
1840-25
1840-30
1840-35
1840-45
20
25
30
35
45
55
Maximum Operating Current (rnA)
1120
1120
1120
1120
1120
1120
Maximum Standby Current (rnA)
320
320
320
320
320
320
Maximum Access Time (ns)
3-82
1840-55
CYM1840
lzrcYPRESS
AC Test Loads and Wavefonns
5V
§=1R14810
5V
OUTPUT
TIR1481Q
ALL INPUT PULSES
3.0V - - - ~90~%~----1J
OUTPUT
30 pF
~~8~~~NG ~
~
SCOPE
R2
2550
5 pF
~78~~~NG ~
SCOPE
(a) Normal Load
GND
~5ns
184().3
18404
(b) High-Z Load
THEvENIN EQUIVALENT
Equivalent to:
OUTPUT
~
R2
2550
~
1.90V
Switching Characteristics Over the Operating Range[3J
1840-20
Parameter
Description
Min.
Max.
1840-25
Min.
Max.
1840-30
Min.
Max.
Unit
READ CYCLE
tRe
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACS
CS LOW to Data Valid
tLZes
CS LOW to Low Z[4J
tHZCS
CS HIGH to High Z[4, 5J
tpu
tpD
20
25
5
5
5
5
0
0
30
ns
ns
ns
20
ns
30
ns
0
25
20
ns
5
20
20
ns
30
5
25
20
c::s LOW to Power-Up
c::s HIGH to Power-Down
30
25
20
us
WRITE CYCLE[6J
twe
Write Cycle Time
20
25
30
ns
tses
c::s LOW to Write End
18
20
25
ns
tAW
Address Set-Up to Write End
18
20
25
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tpWE
WE Pulse Width
15
20
25
ns
tSD
Data Set-Up to Write End
13
15
15
us
tHD
Data Hold from Write Eud
2
2
2
ns
tLZWE
WE HIGH to Low Z
0
tHZWE
WE LOW to High Z[5J
0
Notes:
3. 'Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of l.Sv, input pulse levels of 0 to 3.0V, and output
loading of the specified IOlJIOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device.
S. tHZCS andtHzWE are specified with CL = 5 pF as in part (h) ofAC'Thst
Loads and Waveforms. 'fransition is measured ±SOO mV from steadystate voltage.
6.
3-84
0
15
0
0
15
0
us
15
ns
The internal write time of the memory is defined by the overlap ofCS
LOW and WE LOW: Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
CYM1840
Switching Waveforms
Read Cycle No.
d 7,8]
§---tO-HA--tAA----tR-~-,---------*----
ADDRESS----.....
DATA OUT
PREVIOUS DATA VALID
3XXX*~~~~~~~~~~~~~~D~A~I_A-_-VA~L~ID~~~~~~~~~~_
11140-5
Read Cycle No. 2[7,8]
tRC
""""'\
~
tACS
I--tHZCS-
tLZCS
~
HIGH IMPEDANCE
DATA OUT
DATA VALID
I""""
-tpu
VCC _ _ _ _ _ _
SUPPLY
CURRENT
HIGH
IMPEDANCE
//
}
_
I---tpo
~ CC
I
50%
50%
IS8
184~
Write Cycle No.1 (WE Controlled)[6]
twe
ADDRESS
~(
~~
{
tses
~
/V////~ '////~
tAW
tHA-
!sA
WE
DATA IN
tPWE
. .jt"
~~~
tso
*
tHO
DATA VALID
- tHZWE
=!
f--tLZWE~
HIGH IMPEDANCE
DATA OUT _ _ _ _ _ _ _D_A_TA_UN_D_E_F_IN_E_D_ _ _ _ _ _ _J»------~-«~
1840·7
Notes:
7. Device is continuously selected, CS = VIL.
_____
8.
3-86
WE is HIGH for read cycle.
CYM1841
CYM1841A
256K X 32 Static RAM Module
Features
Functional Description
• High-density 8-megabit SRAM
module
• 32-bit standard footprint silpports
densities from 16K x 32 tbrough
IMx32
• High-speed CMOS SRAMs
- Access time of12 ns
The CYM1841/1841A is a high-performance 8-megabit static RAM module organized as 256K words by 32 bits. This
module is constructed from eight 256Kx 4
SRAMs in SOJ packages mounted on an
epoxy laminate board with pins. Four chip
selects (CSl> CS2, CS3, CS"4) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects.
• Low active power
- 5.3W (max.) at 25 ns
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of 0.58 in.
• Available in ZIP, SIMM, and angled
SlMM footprint
• 72-pin SIMM version compatible with
1M x 32 (CVMI851)
Writing to each byte is accom~shed when
the appr~ate chip select (CS) and write
enable (WE) inputs are both LOW. Data
on the input/output pins (I/O) is written
into the memory location specified on the
address pins (1\0 through A17).
Reading the device is accomplished by taking the ~ select (CS) WW while write
enable (WE) remains HIGH. Under these
conditions, the contents of the memory location specified on the address pins will appear on the data input/output pins (I/O).
The data input/output pins stay at the highimpedance state when write enable is
LOW or the appropriate chip selects are
HIGH.
'!Wo pins (PDo and POl) are used to identify module memory density in applications
where alternate versions of .the JEDECstandard modules can be interchanged.
A 72-pinSIMM is offered for compatibility
with the IMx 32 CYM185 1. Thisversionis
socket upgradable to the CYM1851.
Logic Block Diagram
Ao - A17
,18'____
----, r - - - - - - - - - - - - - -,- ,
OE ___
______________________
T1
PDo
PD 1
PD2
PD3
- GND
- GND
- OPEN (72-pin only)
- OPEN (72-pln only)
~----~~---------------,
1/0 0-1/°3
CS1 ---r+;---L--------------ri-r~
1/°8- 1/°11
CS2----+-r+_-~-------~+_~~
CS3-----r+;---L--------------ri-r~
1/028 - 1/031
CS4-----------L--------------------~
1841-1
3-88
~YPRESS
CYM1841
CYM1841A
Electrical Characteristics Over the Operating Range
1120
960
rnA
480
480
rnA
Max. V cc,
~ Vee - 0.2Y,
VIN ~ Vee - 0.2Y,
or VIN:5. 0.2V
16
16
rnA
Max. Vee, CS ~ Vee - 0.2Y,
VIN ~ Vee - 0.2Y,
or V :5. 0.2V
120
120
rnA
ISB!
ISB2
1841
ISB2
1841A
Automatic CS PowerDown Current[!]
Shaded area contains
Capacitance[2]
Parameter
Description
elN
Input Capacitancd3]
COUT
Output Capacitance
Test Conditions
Max.
Unit
= 1 MHz,
70/20
pF
20
pF
TA - 2SoC, f
Vee = S.OV
Note:
1.
A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
2.
3
Thsted on a sample basis.
20 pF on CS, 70 pF all others.
AC Test Loads and Waveforms
R1481Q
R14810
ALL INPUT PULSES
OUTP~~ ~ OUTP~~ ~
.~~.~;Fi 1
.~ ~;Fi 1
~78~~NG -=
-=
~78~~~NG -=
-=
R2
R2
2550
SCOPE
Equivalent to:
(a) Normal Load
3.0V - - - ' - -
••
SCOPE
2550
1841.4
(b) High-Z Load
THEvENIN EQUIVALENT
1670
OUTPUT~
GND
1.73V
3-90
1841·5
CYM1841
CYM1841A
Switching Characteristics Over the Operating Range (continued)[4]
1841-45
1841A-45
1841-35
184IA-35
Parameter
Description
Min.
Max.
Min.
Max.
1841-55
1841A-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
35
45
tORA
Data Hold from Address Change
tACS
CS LOW to Data Valid
35
45
55
ns
tOOE
OE LOW to Data Valid
25
30
35
ns
3
55
45
35
3
0
ns
55
0
ns
ns
3
, tLZOE
OE LOW to Low Z
tHZOE
OE LOW to High Z
tLZCS
CS WW to Low Z[5]
tHZCS
CS HIGH to High Z[5,6]
20
20
20
ns
tpD
CS HIGH to Power-Down
35
45
55
ns
15
0
15
10
10
ns
15
10
ns
ns
WRITE CYCLE[7]
twc
Write Cycle Time
35
45
55
ns
tscs
CS WW to Write End
30
40
50
ns
tAW
Address Set-Up to Write End
30
40
50
ns
tRA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tpWE
WE Pulse Width
30
35
45
ns
tSD
Data Set-Up to Write End
20
25
35
ns
tHO
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z
0
0
0
ns
tHZWE
WE WW to High Z[6]
0
15
0
15
0
15
ns
Notes:
4.
5.
6.
Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IorJIOH and 30-pF load capacitance.
At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device. These parameters are guaranteed by design and not 100% tested.
tHZCS and ltizWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. 'fransition is measured ± 500 mV from steadystate voltage.
7.
3-92
The internal write time ofthe memory is defined by the overlap ofCS
LOW and WIlLOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
CYM1841
CYM1841A
1s'ircYPRESS
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[7, 11]
ADDRESS
!ses
!so
DATA IN
DATA VALID
tHZWE--I
DATA OUT
--------------------~I
HIGH IMPEDANCE
)>--------------
DATA UNDEFINED
1841~9
Note:
11. IfCS goes HIGHsimuitaneouslywith WE HIGH, the output remains
in ~ high-impedance state.
Truth Thble
CS
WE
OE
H
X
X
HighZ
DeselectIPower-Down
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
if
It
HighZ
Deselect
Input/Output
Mode
3-94
CYM1841
CYM1841A
.rcYPRESS
Ordering Information (continued)
Speed
(ns)
45
55
Ordering Code
Package
Name
Package 1Ype
CYMl841PM -45C
PM02
CYM1841P7-45C
PM04
72-Pin Plastic SIMM Module
CYM1841PN -45C
PN02
64-Pin Plastic Angled SIMM Module
CYM1841APM-45C
PM02
64-Pin Plastic SIMM Module
CYMl841AP7 -45C
PM04
72-Pin Plastic SIMM Module
CYMl841APN-45C
PN02
64-Pin Plastic Angled SIMM Module
CYMl841APZ-45C
PZ03
64-Pin Plastic ZIP Module
CYM1841PM-55C
PM02
64-Pin Plastic SIMM Module
CYM1841P7-55C
PM04
72-Pin Plastic SIMM Module
CYM1841PN-55C
PN02
64-Pin Plastic Angled SIMM Module
CYM1841APM-55C
PM02
64-Pin Plastic SIMM Module
CYM1841AP7-55C
PM04
72-Pin Plastic SIMM Module
CYM1841APN -55C
PN02
64-Pin Plastic Angled SIMM Module
CYM1841APZ-55C
PZ03
64-Pin Plastic ZIP Module
64-Pin Plastic SIMM Module
Document#: 38-M-00031-D
3-96
Operating
Range
Commercial
Commercial
~YPRESS
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
CYM1846
DC Input Voltage ........................ -O.5V to +7.0V
Operating Range
Storage Thmperature ................... -55°C to +125°C
Ambient Thmperature with
Power Applied ......................... -100C to +B5°C
Supply Voltage to Ground Potential ......... -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5Vto +Vee
Range
Commercial
Ambient
Tempemture
Vee
O°Cto +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
Pammeter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Ilx
Input Load Current
Test Conditions
Min.
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
Unit
2.4
Vee
2.2
V
0.4
V
Vee +
0.3
V
-0.5
O.B
V
GND~VI~Vee
-10
+10
fAA
-10
+10
(.IA
BOO
mA
Ioz
Output Leakage Current
GND ~ Vo ~ Vee, Output Disabled
Icc
Vee Operating Supply Current
Yce
ISBI
Automatic CS Power-Down Current[11
Max. Vee, CS ~ VIH,
Min. Duty Cycle = 100%
240
rnA
ISB2
Automatic CS Power-Down Currentlll
Max. Vee, CS ~ Vee - 0.2y,
VIN ~ Vee - 0.2Y, or VIN ~ 0.2V
40
mA
= Max., lOUT = 0 rnA,
CSN~VIL
"
Capacitance[2]
Parameter
Description
Test Conditions
CINA
Input Capacitance (WE, OE, Ao-IS)
CINB
Input Capacitance (CS)
COUT
Output Capacitance
TA = 25°C, f - 1 MHz,
Vee = 5.0V
Max.
Unit
40
pF
20
pF
20
pF
Notes:
1.
A pull-up resistor to Vee on the CS input is required to keep the device deselectedduringVccpower-up,otherwise ISBWill exceed values
given.
2.
Thsted on a sample basis.
AC Test Loads and Waveforms
R1 48Hl
ALL INPUT PULSES
R1 4810
OUTP~~ ~ OUTP~~ ~
.~~~:F1 1
.~ ~:F1 1
R2
2550
INCLUDING
JIG AND
SCOPE
-
-
••
INCLUDING
JIG AND
SCOPE
2550
-
1.73V
GND
-
1846-2
(b) High-Z Load
THEvENIN EQUIVALENT
OUTPUT~
90%
R2
(a) Nonnal Load
Equivalent to:
3.0V----
184&3
(arcYPRESS
PRELIMINARY
CYM1846
Switching Waveforms (continued)
Read Cycle No. 2(7, 9J
tRC
~~
/1{
tACS
{
IHZOE-
IOOE
~tHZCS-
-tLZOEHIGH IMPEDANCE
DATA OUT
suP~t~
'/
DATA VALID
'"
tLZCS
!----tpu
______
//
I--tpo
HIGH
IMPEDANCE
~ CC
I
}
50%
50%
ISB
CURRENT
1846·5
Write Cycle No.1 (WE Controlled)[6J
twc
ADDRESS ~~
)~
--./
~~
tscs
~
/5/////~ ~////.!
tAw
tHA-
tSA
tPWE
~~~
DATA IN
/
tso
*
tHO
DATA VALID
----------------~)
I--tHzwE
DATA OUT
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
DATA UNDEFINED
Notes:
7. WE is HIGH for read cycle.
8. Device is continuously selected, C;S = VIL, and OE= VIL.
•
-tLZWE
HIGH IMPEDANCE-1<"---1846-6
9. Address valid prior to or coincident with C;S transition LOW.
3-100
CYM1851
PRELIMINARY
1,024Kx 32 Static RAM Module
F!!~tures
Functional Description
• High-density 32-megabit SRAM
module
• 32-bit Standard Footprint supports
densities from 16K x 32 through
IMx32
• High-speed CMOS SRAMs
- Access time of 25 ns
The CYM1851 is a high-performance
32-megabit static RAM module organized
as 1,024K words by 32 bits. This module
is constructed from eight 1,024K x 4
SRAMs in SO] packages mounted on an
epoxy laminate substrate. Four chip selects are used to independently enable the
four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper
use of selects.
The CYM1851 is designed for use with
standard 72-pin SIMM sockets. The pin-
• Low active power
- 6.6W (max.) at 25 ns
• 72 pins
• Available in ZIP, SIMM, or angled
SIMMformat
Logic Block Diagram
out is downward compatible with the
64-pin JEDEC ZIP/SIMM module family
(CYM1821, CYM1831, CYM1836, and
CYM1841). Thus, a single motherboard
design can be used to accommodate
memory depth ranging from 16K words
(CYMI821)
to
1,024K
words
(CYMI851).
Presence detect pins (PDo - PD3) are used
to identify module memory density in applications where modules with alternate
word depths can be interchanged.
Pin Configuration
ZIP/SIMM
Top View
Ao - A19
OE
WE
PDo PD1 PD2 PD3 -
20
GND
OPEN
GND
OPEN
1/0 0- 1/0 3
NC
PD3
PDo
1/0 0
1/0 1
1/0 2
1/0 3
1/0 4-1/0 7
Vee
~
I/~
CS1
1/08 - 1/0 11
~~
CS3
CS4
I~
CS2
1/020 -1/0 23
1/0 16 -1/0 19
A16
GND
1/0 16
1/0 17
1/0 18
1/019
A10
A11
A12
A13
1/0 20
1/0 21
1/0 22
1/023
GND
A19
NC
CS3
1/0 26 -1/031
1/024 -1/027
CS4
1851·1
Ao
A1
A2
1/012
1/0 13
1/0 14
1/0 15
GND
A15
CS2
1/0 5
1/0 6
1/012 -1/0 15
NC
PD2
GND
PD1
1/0 8
1/09
1/0 10
1/0 11
A17
OJ:
1/024
1/0 25
1/0 26
1/027
~
~
Vee
As
1/0 28
1/0 29
1/0 30
1/0 31
A18
NC
1851~2
Selectiop Guide
1851-25
1851-30
25
30
35
Maximum Operating Current (rnA)
1200
1200
960
Maximum Standby Current (rnA)
480
480
480
Maximum Access Time (ns)
3-102
1851-35
PRELIMINARY
CYM1851
Switching Characteristics Over the Operating Rangd3]
1851-25
Parameter
Description
Min.
Max.
1851-30
Min.
Max.
1851-35
Min.
Max.
Unit
READ CYCLE
25
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Data Hold from Address Change
tACS
c::s LOW to Data Valid
25
30
35
ns
tDOE
OE LOW to Data Valid
15
20
25
ns
tLZOE
00 LOW to Low Z
30
25
5
35
30
5
0
ns
35
5
0
ns
ns
0
ns
tHZOE
OE HIGH to High Z
tLZCS
c::s LOW to Low Z[4]
tHZCS
CS HIGH to High Z[4.5]
12
12
12
ns
tpD
c::s HIGH to Power-Down
25
30
35
ns
12
10
12
10
12
10
ns
ns
WRITE CYCLE[6]
twc
Write Cycle Time
25
30
35
tscs
CS LOW to Write End
20
25
30
ns
tAw
Address Set-Up to Write End
20
25
30
ns
ns
tRA
Address Hold from Write End
3
3
3
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tpWE
WE Pulse Width
20
25
30
ns
tSD
Data Set-Up to Write End
15
15
20
ns
tHD
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z
0
tHZWE
WE LOW to High Z[5]
0
Notes:
3. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5\'; input pulse levels of 0 to 3.0\'; and output
loading of the specified ImJ10H and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZcs is less than
tLZes for any given device. These parameters are guaranteed and not
100% tested.
5. tHZes andtHzWE are specified with CL = 5 pF as in part (b) ofACThst
Loads and Waveforms. 1tansition is measured ±500 m V from steadystate voltage.
6.
0
12
0
0
12
0
ns
12
ns
The internal write time ofthe memory is defined by the overlap oiCS
LOW and WI'lLOw. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
Switching Waveforms
Read Cycle No.
d 7,8]
t=
'L
ADDRESS _ _ _ _ _
DATA OUT
PREVIOUS DATA
.
tRC
1
V:~; 3XXX*==============DA=:r=A=V=AL=ID==========
1851-5
3-104
~YPRESS
PRELIMINARY
CYM1851
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[6, lOJ
ADDRESS
------t----tscs
................................................................................~ !4---tPWE - - - . - / .I'..,...,....,~...,...,.."...,....-?...,...,..r-
WE
14-+---tSD ---",*,'""
DATA IN
DATA OUT
DATA VALID
tHZWE---I
--------------------~I
)>--------------
DATA UNDEFINED
HIGH IMPEDANCE
la5H!
Note:
10.
IfCS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
'lhIth Table
CS
WE
OE
H
X
X
HlghZ
DeselectIPower-Down
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
H
H
HlghZ
Deselect
Inputs/Output
Mode
Ordering Information
Speed
(ns)
Ordering Code
Package
1)pe
25
CYM1851PM - 25C
PM04
72-Pin Plastic SIMM Module
CYM1851PN - 25C
PN04
72-Pin Plastic Angled SIMM Module
30
35
Package 1)pe
CYM1851PZ- 25C
PZ09
72-Pin Plastic ZIP Module
CYM1851PM - 30C
PM04
72-Pin Plastic SIMM Module
CYM1851PN-30C
PN04
72-Pin Plastic Angled SIMM Module
CYM1851PZ-30C
PZ09
72-Pin Plastic ZIP Module
CYM1851PM - 35C
PM04
72-Pin Plastic SIMM Module
CYM1851PN-35C
PN04
72-Pin Plastic Angled SIMM Module
CYM1851PZ-35C
PZ09
72-Pin Plastic ZIP Module
Document #: 38-M-00052-A
3-106
Operating
Range
Commercial
Commercial
Commercial
This is an abbreviated datasheet. Contact a
Cypress representative for complete
specifications_
CYM7420
CYM7421
82420 PClset-Compatible Level II
Cache Modules
Features
• TTL-compatible inputs/outputs
• 128 Kbytes (CYM7420), 256 Kbytes
(CYM7421) cache module organized
as 32K by 32 or 64K by 32
• Thg width of 7/8 bits plus valid bit
• lodependellt dirty bit
• Operates with systems based on the
Intel ~ 82420 core logic
• Zero-wait state operation at 33 Mhz
• Constructed usiog standard asynchronous SRAMs
• 112-pin Bumdy Connector, Part Number CELP2X56SC3Z48
• Single 5V (±5%) power supply
Functional Description
Logic Block Diagram
The CYM7420 module series is a family
of cache memory subsystems for Intel
486-based systems. Each module co~
tains either one or two banks of 32-blt
wide Data SRAM, 8K/32K entries of
7/8-bit tag, and one Valid bit, and a single
bit wide, separate I/O Dirty SRAM.
CYM7420 has 8-bit tags, while CYM7421
support 7-bit tags. The address signals for
the Data and Dirty SRAMs are latched.
The modules are configured as a 112-pin
card-edge memory module.
It is
constructed using standard asynchronous
SRAMs in SOJ packages mounted on a
multilayer epoxy laminate (FR4) substrate. The module dimensions are 3.145
inches long by 1.105 ioches higlt by 0.365
inches thick.
These modules are designed for zero wait
state operation in 486-based systems operatiog at a bus speed of 33 Mhz. They
are designed for compatibility with the Intel 82420 PClset and other chip sets. The
baseline speed grade is built using 12
nanqsecond Thg SRAMs and 20 nanosecond Data SRAMs.
Address Latch
r---
(CYM7421) A[17:4]
(CYM7420) A[16:4] --,r-D
ALE
01-
~~~
LA[17:4] (CYM7421)
LA[16:4] (CYM7420)
- r- LE
DataSRAMs
'---
Data Bank o
~ A[14:2]
A[1:0]
OE
WE
r----- I
I
I
I
IL _ _ _ _ _
WE!3:OJ
0[31:0]
0
CS
WE
WE
PD[4:0]
WE
- - ---,
----- -l---.:r---.:r---J:.-- r -CYM74
210nly I
.-
A[14:2
A[1:0]
OE
- -----
WE
I
I
I
Data Bank 1
_ _ _ .II
Or-
CS
WE
WE
'::f:
--l--r--±-- ----r-'-- A[13:0]
CS
DirtySRAM
Din
DIRTYI
Dout
DIRTYO
WE
'==
A[14:0]
TagNalid SRAM
TAG[7:0]
VALID
CSD
~
CYM742D-1
'---
Sit'
e ec Ion G UI'de
CYM7420PB-20
CYM7421PB 20
Cache Size (KB)
128
256
Data SRAM(ns)
20
20
Dirty SRAM (ns)
15
15
ThgIVaJid SRAM (ns)
12
12
Intells a trademark of Intel CorporatIon.
Document #: 38-M-00065-A
3-108
CYM7424
CYM7425
QYPRESS
Logic Block Diagram CYM7425
Address Latch
74FCT373C
Q
32Kx8
32Kx8
32Kx8
32Kx8
I BANK 01
CI3E - f - - - - i + - - - - - i - - - . j
CWEo -r------t+-----t---f
COEo ~--~~---~--~
m:3
I
L _ _ _ .J
10 ns
CI302
CWE1
COE1
PLD
cso
"CST
CS2
CS3
D
----+--------f
WE
rn:
32KxB
IBANK11
32Kx8
32KxB
32Kx8
32Kx9
! - -_ _ _-'-"1....:..:JLL-_-'-_~
A14
Ao-A13
nNE ---------------~WE
~
Te"S
D
Tag RAMS
1----------
TAG o- TAGa
DE
CVM7424-2
3-110
CYM7424
CYM7425
Pin Descriptions
Name
Description
~-Alg
Cache Address Inputs
CI302, CI3E
Cache Index Address Inputs
Do-D3l
Cache Data Input/Outputs
BEo- BE3
Byte Enable Inputs
CWEo
Bank 0 Write Enable Input
CWEl
Bank 1 Write Enable Input
OOEo
Bank 0 Output Enable
COEl
Bank 1 Output Enable
WIR
WriteIRead Input
ADS
CPU Address Strobe Input
EADS
External Address Strobe Input
TAGo-TAGg
Tag Data Input/Output
fWE
Tag Write Input
TCE
Tag Chip Enable Input
PDo-PDz
Presence Detect Pins
NC
No Connection
Presence Detect Table
PD2
PDl
PDo
CYM7424
NC
vee
NC
CYM7425
NC
NC
Vee
Maximum Ratings
(Above which the useful life may be inlpaired. For user guidelines,
not tested.)
Storage Thmperature ................... -55°C to + 125°C
Ambient Thmperature with
Power Applied .......................... -ooC to + 70°C
Supply Voltage to Ground Potential ......... -O.SV to +7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.SV to + 7.0V
DC Input Voltage ........................ -O.5V to +7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Operating Range
3-112
Range
Commercial
Ambient
Temperature
O°Cto +70°C
Vee
SV±S%
CYM7427
CYM7428
ADVANCED INFORMATION
82420 PCIset-Compatible
Level II Cache Module Family
Features
Func~ional
•
•
•
•
The CYM7427/28 module series is a family of cache memory subsystems for Intel
486-based systems. The CYM7427 (128
Kbytes) contains one memory bank organized as 32K by 32. The CYM7428 (256
Kbytes) coQtains two banks for interleaved operation. In addition, each module ~ontains one 8-bit wide SRAM, supportmg a 7-bit tag and one Valid bit and a
sing~e-bit,. separate I/O SRAM supporting
a Dirty bit. The address signals for the
Data and Dirty SRAMs are latched.
The 7427/28 is configured as a 112-pin
card-edge memory module. It is con-
•
•
•
•
•
Cache size 128 Kbytes or 256 Kbytes
Tag width of 7 bits plus valid bit
Independent dirty bit
Operates with systems based on the
Intel 82420 core logic
Zero-wait state operation at 33 MHz
Constructed using standard asynchronous SRAMs
112-pin Burndy Connector, Part
Number CELP2XS6SC3Z48
Single SV (±5%) power supply
TTL-compatible inputs/outputs
Description
structed using standard asynchronous
SRAMs in SOJ packages mounted on an
epoxy laminate substrate. The module dimensions are 3.145 inches long by 1.105
inches high by 0.365 inches thick.
These modules are designed for zerowait-state operation in 486-based systems
operating at a bus speed of 33 MHz.
They are designed for compatibility with
the Intel 82420 PCIset and other chipsets.
The baselinespeed grade is built using
12-nanosecond Tag SRAMs and 20nanosecond Data SRAMs.
Logic Block Diagram
Address Latch
(CYM7428)
(CYM7427)
A[17:4]
A[16:4]
-PO[4:0]
ALE
LE
Data Bank a
A2-0.A3-0 ~1----l1-I
0[31:0]
=
om
r----I
1
1
1
CYM74287n;;-'1
A2-1.A3-1
~ =t====!j
WE
Data Sank 1
I
1
~-----------~
~ ~r_----~--~--~--~--..J
P " ' L - - - - - - - - - - OIRTYI
f.!D.!!lO!!!ut:...-._ _ _ _ _ _ _ _ OIRTYO
. . ._ _ _ _
~[14:0]
TagNalid SRAM
:::::::::::~i 01----------- ~~I~:O]
7427·1
Selection Guide
CYM7427PB-20
CYM7428PB-20
Cache Size (KB)
128
256
Data SRAM (ns)
20
20
Dirty SRAM (ns)
15
15
Thg/Valid SRAM (ns)
12
12
Document #. 38-M-00077
3-114
=:.
PRELIMINARY
rcYPRESS
Pin Configuration
Dual Read-out SIMM
Top View
GND
GND
062
Dea
Vee
Vee
060
06'
Vee
Vee
Os.
0'7
0 58
GND
NC
0 59
GND
NO
055
053
051
GND
D5'
D52
D50
GND
049
0.7
D••
D45
D44
D42
045
043
GND
GND
D.,
NO
D40
NC
D3•
039
03'
0 3,
D36
D34
GND
033
!la2
GND
0 3,
D30
D28
D26
029
027
D2.
GND
NC
02'
GND
NO
023
021
Vee
019
GND
0"
Vee
015
0'3
GND
Vee
Vee
0"
D.
NO
NO
Vee
0,
D5
Vee
D.
D.
D,
0"
0,
GND
De
Ao-,
Aa NC
GND
DIRTYI
DJRTYO
TAGo
TAG,
Vcc
Vcca
TAG2
TAG.
GND
TAGB
TAGa
TAG5
GND
TAG7
PDo
PD2
PD,
PDa
Vcca
Vee
3-132
74A550- A4-1> AS-I> ~-l
Lower address from chip set for bank1, identical to the bankO addresses
rno,CEI
Chip Enable (same signal)
OEo,OEI
Output Enable (same signal)
~, WEl,}Yfu, ~
Byte Write Enables
CALE
Latch Enable - CYM74A590 only
WE4, WEs , WE6, WE7
PDo-PD2
Presence Detect pins
Do-D63
Data lines from processor
DPO-DP7
Data Parity lines (Optional), CYM74S590 or CYM74S591 only
ADSPO, :ADSPf
Processor Address Strobe, CYM74S590 or CYM74SS91 only
AI5SCO,ADS(';I
Cache Controller Address Strobe, CYM74SS90 or CYM74SS91 only
ADVO,ADVI
Burst Address Advance - CYM74S590 or CYM74SS91 only
CLKO,CLK1,CLK2,CLK3
Clock signals
NC
Signal not connected on module.
Presence Detect Pins
PD2
PDI
PDo
NC
GND
NC
Synchronous - CYM74S590
GND
GND
NC
Synchronous - CYM74S591
GND
GND
GND
Asynchronous - CYM74A590
3-138
CYM74A590
CYM74SS90
CYM74SS91
CYM923 0
CYM9231
This is an abbreviated datasheet. Contact a
Cypress representative for complete
specifications.
82420 PCIset-Compatible Level II
Cache Modules
Features
• TTL-compatible inputs/outputs
• 128K-byte (CYM9230) or 256K-byte
(CYM9231) cache moducle organized
as 32K by 32 or 64K by 32 .
• Tag width of 9 bits plus valid bit
• lodependent dirty Iiit
• Operates with systems based on the
Intel m 82420 core logic
• Zero-wait state operation at 33 Mhz
• Constructed using sandard asynchronous SRAMs
• 112-pin Bumdy Connector, Part Number CELP2X56SC3Z48
• Single 5V (±5%) power supply
Functional Description
Logic Block Diagram
The CYM9230 module series is a family
of cache memory subsystems for Intel
486-based systems.
The CYM9230
(128Kbytes) contains one memory bank
organized as 32K by 32. The CYM9231
(256Kbytes) contains two banks for interleaved operation. In addition, each module contains two SRAMs, supporting a
9-bit tag and valid bit, and a single-bit,
separate I/O SRAM supporting a dirty
bit. The address signals for the Data and
Dirty SRAMs are latched.
These modules are designed for zero wait
state operation in 486-based systems operating at a bus speed of 33 Mhz. They
are designed for compatibility with the Intel 82420 PCIset and other chip sets. The
baseline speed grade is built using 12
nanosecond Thg SRAMs and 20 nanosecond Data SRAMs.
The modules are configured as a ll2-pin
card-edge memory module.
It is
constructed using standard asynchronous
SRAMs in SOJ packages mounted on an
epoxy laminate substrate. The module dimensions are 3.145 inches long by 1.105
inches high by 0.365 inches thick.
Address Latch
r----
(CYM9231) A[17:4]
(CYM9230) A[16:4]
---or
ALE
- r-
D
Q-
LE
'--A2-0,A3-0
LA[17:4] (CYM9231)
LA[16:4] (CYM9230)
,.--~ A[14:2
DataSRAMs
Data Ban kO
A[1:0]
CS
CSO
rn:
OED
WE
D[31:0]
D
WE
WE
WE
r----- - r---- t--..:f.--+---I---.l::--
I
I
I
I
IL
A2-1,A3-1
~ A[14:2
A[1:0]
es
m:
~
0E1
____ _
WE[3:OJ
---,
-CYM9231 only I
I
I
I
Data Bank
_1_ _ .JI
DI-
WE
WE
WE
WE
-- ----- --t---'f---l----{-----
--
r - - DirtySRAM
A[13:0
CS
nin
DIRTYI
Dout
DIRTYO
WE
'----
r-A[14:0]
a CS
a ITE
aWE
TagNalid SRAM
TAG [8: 0]
VALID
D
92301
'----
Selection Guide
CYM9230PB 20
CYM9231PB 20
Cache Size (KB)
128
256
Data SRAM (ns)
20
Dirty SRAM (ns)
Thg/Valid SRAM (ns)
15
12
20
15
Intel IS a trademark of Intel Corporation.
Document #: 38- M -00064-A
3-140
12
~9244,~9245
~9246,~9247
PRELIMINARY
128K;256K Cache Module
Family for the OPTi 802GP Chipset
Features
• TTL-compatible inputs/outputs
• 128 Kbyte (CYM9244 & CYM9246),
256 Kbyte (CYM9245 & CYM9247),
secondary cache modules
• Ideal for Intel ~ 486 systems with the
OPTI 802GP chipset
• Zero-wait-state operations at 33 MHz
• Constructed using cost-effective
CMOS asynchronous SRAMs
• On-board decoupling capacitors offer
improved noise immunity
• 112-position Bumdy Connector, Part
Number CELP2X56SC3Z48
• 5V (:1:5%) power supply
Functional Description
These modules are designed to function
as the secondary Cache in Intel 486-based
systems with the OPTi 802GP chipset.
Each module contains either one or two
banks !'if 32-bit wide data SRAMs, an
8-bit wide tag RAM, and a single-bit dirty
RAMM'ith separate I/O (CYM9246 and
CYM9247 only). The addresses for the
data SRAMs are buffered by an on-board
latch. Asynchronous CMOS SRAMs tire
used to provide a low-cost, low-poWer,
and zero-wait-state solution for CPU
speeds up to 33 MHz. Multiple ground
pins and on-board decoupling capacitors
ensure maximum protection from noise.
Each module interfaces with the rest of
the system via a 112-pin Burndy connector. All components on the cache module
are surface mounted on a multi-layer
epoxy laminate (FR-4) board. The package dimensions are 3.15" x 0.365" x 1.1".
All inputs and outputs of the CYM9244,
CYM9245, CYM9246, and CYM9247
cache modules are TTL compatible and
operate from a single 5V power supply.
The contact pins are plated with 100
micro-inches of nickel covered by 10
micro-inches of gold flash.
---
Address Latch
74FCT373
At,- A17
LAt,- LA17
Q
ALE
BankO
As.o
PDo
PD1
PD2
PD3
PD4
--
-+-__
A2.(J (CYM9244 & CYM92419
6H ____
-t
LA17(CYM9245 & CYM924_T-i_ _ _ _--t___oi
00- 0 31
WEo
OEo
10Kn Vee
As·1
Bank 1
(CYM9245 & CYM9247 only)
DIRTYI
~ -+------------------------------~
DIRTYO
~_r----------------------------~
Vee
~ ---------------------~
~ ---------~----------~
TAGUE
o
TAGO-TAG7
8K x 8 (CYM9244 & CYM9248)
32K x 8 (CYM9245 & CYM9247)
Selection Guide
Cache Size (KB)
Data SRAM (ns)
Dirty SRAM (ns) ,
Tag/Valid SRAM (ns)
9246.1
-,
CYM9244PB-20C
128
20
CYM9245PB-20C
256
20
15
15
Intel is a trademark of Intel Corporation.
3-142
CYM9246PB-20C
128
20
20
15
CYM9247PB-20C
256
20
20
15
~YPRESS
PRELIMINARY
C~9244,~924S
~9246,C~9247
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature .................. -55°C to + 125°C
Ambient Thmperature with
Power Applied .......................... -O°C to +70°C
Supply Voltage to Ground Potential ......... -O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State ............ , ' , , , , , , , . , ... -O.5V to +7.0V
DC Input Voltage ........................ -O.SV to +7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Operating Range
Range
Commercial
Ambient
Temperature
O°Cto +70°C
Vee
5V±S%
Electrical Characteristics Over the Operating Range
CYM9244, CYM9245,
CYM9246,CYM9247
Parameter
Description
Test Conditions
Min.
Max.
Unit
0.4
V
VOH
Output HIGH Voltage
Vcc=Min., IOH=-4.0 rnA
VOL
Output LOW Voltage
V cc=Min., IOL =8.0 rnA
Vrn
Input HIGH Voltage
2.2
Vcc+O.3
V
-0.5
0.8
V
2.4
V
VIL
Input LOW Voltage
Icc
V cc Operating Supply Current
(CYM9244)
V ce=Max., IOUT=O rnA,
f=fMAX=l/tRe
950
rnA
Icc
Vcc Operating Supply Current
(CYM9245)
Vcc=Max., IOUT=O rnA,
f=fMAX=l/tRC
1700
rnA
Icc
V cc Operating Supply Current
(CYM9246)
Vcc=Max., IOUT=O rnA,
f=fMAX=l/tRC
1050
rnA
Icc
V cc Operating Supply Current
(CYM9247)
V cc=Max., IOUT=O rnA,
f=fMAX=l/tRC
1800
rnA
Presence Detect Table
PD4
PD3
PD2
PDl
PDo
NC
NC
NC
NC
GND
CYM9245
NC
NC
NC
GND
NC
CYM9246
GND
NC
NC
NC
GND
CYM9247
GND
NC
NC
GND
NC
CYM9244
AC Test Loads and Waveforms
R1 4800
R1 4BOQ
OUTP~~~
OUTP~~31
50 pF
I
R2 255'-1
INCLUDING _
JIG AND SCOPE
_
-
5 pF
I
ALL INPUT PULSES
3.0V~
10%
90%
R2255'-1
INCLUDING _
JIG AND SCOPE
_
-
SI'=10nS
9246-3
(b)
(a)
Equivalent to:
THEVENIN EQUIVALENT
16m
OUTPUT
GND
0.0--....·"""'_---00 1.73V
3-144
~
10%
S If= IOnS
92464
~
~9244,C~9245
_;CYPRESS' ====;;;;;;PRE=L;;;;;;I;;;;;;M;;;;;;IN;;;;;;~=Y==;;;;;;~=;;;;;;9;;;;;;2;;;;;;4;;;;;;;;6,;;;;;;~=;;;;;;9;;;;;;2;;;;;;4=7
Switching Characteristics (continued)
Description
Parameters
Min.
Max.
Units
22
ns
Data SRAM Write Timing
twc
Write Cycle Timel 1]
tSCE
CS[7:0] LOW to End of Write[1]
tAWl
Address Set-Up to End of Write (A.!-A17)l1]
20
ns
tAW2
Address Set-Up to End of Write (A2-0, A3-0, A3-), No
Latch Path)[l]
15
ns
tRA
Address Hold from End of Write [2]
0
ns
tSA
Address Set-Up to Start of Write [2]
0
ns
tpWE
WE[1:0] Pulse Width[l]
15
ns
tso
Data Set-Up to End of Writel2]
12
ns
tHO
Data Hold from End of Writel2]
0
ns
tLZWE
WE[1:0] LOW to High Z[2]
tHZWE
WE[1:0] HIGH to Low Z[2]
27
ns
12
ns
3
ns
Tag SRAM Write Timing
tTWC
Thg Write Cycle Time l1]
17
ns
tTSCE
TAGCS LOW to End of Thg Write[1]
10
ns
tTAw
Address Set-Up to End ofThg Write [1]
10
ns
tTHA
Address Hold from End of Thg Write [2]
0
ns
tTSA
Address Set-Up to Start of Thg Write [2]
0
ns
tTWPE
TAGWE Pulse Width[lJ
10
ns
tTSO
Thg Set-Up to End of Tag Writel2]
11
ns
tTHO
Thg Hold from End of Tag Writel2]
0
tTLZWE
TAGWE LOW to Thg High Z[2]
tTHZWE
TAGWE HIGH to Thg Low Z[2]
ns
9
ns
3
ns
Dirty SRAM Write Timing (CYM9246 & CYM9247)
towc
Dirty Write Cycle Time[l]
27
ns
toow
DIRTYI Set-Up to End of Dirty Write [lJ
12
ns
tooHW
DIRTYI Hold from End of Dirty Write [1]
0
ns
tDSCE
DIRTYCS LOW to End of Dirty Writel2]
12
ns
tDAW
Address Set-Up to End of Dirty Write [2]
16
ns
tDRA
Address Hold from End of Dirty Write [2]
0
ns
tDSA
Address Set-Up to Start of Dirty Write [2]
0
ns
tOWPE
DIRTYWE Pulse Width[l]
12
tDLZWE
DIRTYWE LOW to DIRTYO pulled HIGH[2J
tDHZWE
DIRTYWE HIGH to DIRTYO Low Z[2]
Notes:
1. Tested initially and after any design or process changes that may affect
these parameters.
ns
9
5
2.
3-146
Parameters goaranteed hy design, not tested.
ns
ns
'.
PRELIMINARY
C~9244,C~9245
C~9246,C~9247
Switching Waveforms (continued)
Data Write Cycle No.1 (WE Controlled)[6, 7, 8]
~-----------------------twc----------------------~
ADDRESS
CSO- 3
~~~~~--------------------------~~~~~~~
~--------------- tAWl/2 - - - - - - - - - - - - - - - - - - - -....-
WEO/l
----~----~----~~~
~------tPWE--------~
,----------------
OEO/1
~-------- Iso --------~.--+I tHo
DATA 1/0
DATAIN VALID
9246·8
Data Write Cycle No.2 (CS[O-3] ControIled)[16, 17,8]
~-----------------------~c------------------------~
ADDRESS
CSO- 3 ----~------------------------~~~----tscE----~~~--------_+---------
DATA I/O
Iso - - - - - -.........
1...... tHO
-----------------------------(k
Noles:
7. Data I/O is high impedance if OEO/l = Vm.
DATAIN VALID
~...______________
Ir
9246-9
8.
3-148
eso - eS3
If
goes HIGH simultaneously with WE HIGH, the output
remains in a high-impedance state.
§J~PRESS
~9244,~924S
~9246,~9247
PRELIMINARY
Switching Waveforms (continued)
Tag Read CycleN.2 [11
~
12]
tTRC
-.....~
"tTCS
"
~
I
tTOE
14-- tTLZOE - -
TAG OUT
HIGH IMPEDANCE
tTHZCE
}
HIGH
IMPEDANC E
./
_tTPD
--tTPU
IlGC
SUt'PLY ________
CURRENT
~~
TAG VALID
''- '\. '\. '\.
tTLZCE
-
~CC
I'--I
50%
50%
ISB
9246-12
Tag Write Cycle No.1 (TAGWE Controlled)[13, 14, 15]
~------------t~c------------~
ADDRESS
i+'-----------------tTAw ----------------------I~-
~-~~------------~~~
~-----tTPWE
~---- tTSD
-----I
~-----------------
----------.j.---toI
TAGI/O
9246-13
Tag Write Cycle Nil. 2 (TAGCS Controlled)[13, 14, 15]
~------------t~c---------------------~
ADDRESS
'fAGC"S
---1------------_
t---tTSCE
-----+-----
- - - - 1 ...
1-----------tTAW.;,..----------I--
"'r:I-------tTSD
------to.
TAG 110 - - - - - - - - - - - - - - - I C ( - - - - - T A - G - ' - N - V A - L - I D - - - - 9246-14
Notes:
12_ Address valid prior to, or coincident with ~ transition LOW.
13_ The internal write time of the memory is defined by the overlap of
TAGCSLOWand'fAGWIlLOW. Both signals must be LOW toinitiate a write and either signal can terminate a write by going HIGH. The
data input set-up and hold tinting should be referenced to the rising
edge of the signal that terntinates the write.
14_ TAG I/O is high impedance if TAGOE = LOW.
3-150
PRELIMINARY
Q-YPRESS
~9244,C~9245
~9246,C~9247
Switching Waveforms (continued)
Dirty Write Cycle No.1 (DIRTYWE ControlIed)[19]
towc
ADDRESS
: )K
~~
)K
tOSCE
~
/~ ~
tOAW
tOHA-
tOSA
-tOWPE
~~~
/'{
toow
~
DIRTYI
_tOHZWE -
DIRTYO
_
DIRTY UNDEFINED
_
tOOHW
~
DATAIN VALID
7"I
_- J
I-- tOLZWE
PULLED UP
9246-18
Dirty Write Cycle No.2 (DIRTYCS ControlIed)[19, 20]
~------------------------towc--------------------------~
ADDRESS
----"'*-----
tOSCE ------------~
toow
DIRTYI
DATAIN VALID
t
DIRTYO
OHZWE
DATA UNDEFINED
==!
PULLED UP
9246·19
Notes:
19. The internal write time of the memory is defined by the overlap of
DIRIYCS WW and DIRtYWE LOW. Both signals msut be WW
to initiate a write and either signal can terminate a write by going
HIGH. The data input set-up and hold timing should be referenced to
the rising edge of the signal that terminates the write.
20. If~ goes HIGH simultaneously with DrRTYWE HIGH, the
output remains in a high-impedance state.
3-152
Section Contents
Non-Volatile Memories
Page Number
Introduction to CMOS Non-Volatile Memories ................................................................ 4-1
Device
Description
CY27C64
8Kx8EPROM ............................................................... 4-3
128K x 8 CMOS EPROM ...................................................... 4-9
CY27COlO
CY27C020
256K x 8 CMOS EPROM ..................................................... 4-16
512Kx 8 CMOS EPROM ..................................................... 4-23
CY27C040
CY27C128
128K (16Kx 8-Bit) CMOS EPROM ............................................. 4-30
32Kx8-Bit CMOS EPROM ................................................... 4-37
CY27C256
CY27C512
64K x 8 CMOS EPROM ...................................................... 4-45
CY27H01O
128K x 8 High-Speed CMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-52
32K x 8 High-Speed CMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-60
CY27H256
64K x 8 High-Speed CMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-68
CY27H512
512 x 8 Registered PROM ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-76
CY7C225A
1K x 8 Registered PROM ..................................................... 4-83
CY7C235A
CY7C243
4Kx 8 Reprogrammable PROM ................................................ 4-90
4K x 8 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-90
CY7C244
CY7C245A
2K x 8 Reprogrammable Registered PROM ...................................... 4-97
16Kx 8 Power-Switched and Reprogrammable PROM ............................ 4-105
CY7C251
16K x 8 Power-Switched and Reprogrammable PROM . . . . . . . . . . .. . . . . . . . . . . . . . . .. 4-105
CY7C254
8K x 8 Power-Switched and Reprogrammable PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-112
CY7C261
8K x 8 Power-Switched and Reprogrammable PROM .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-112
CY7C263
8K x 8 Power-Switched and Reprogrammable PROM .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-112
CY7C264
8K x 8 Registered PROM .................................................... 4-121
CY7C265
8K x 8 Power-Switched and Reprogrammable PROM .......... . . . . . . . . . . . . . . . . . .. 4-129
CY7C266
8Kx 8 Registered Diagnostic PROM ........................................... 4-136
CY7C269
32K x 8 Power-Switched and Reprogrammable PROM, . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-147
CY7C271
32K x 8 Power-Switched and Reprogrammable PROM . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-147
CY7C274
32K x 8 Power-Switched and Reprogrammable PROM ..... . . . . . . . . . . . . . . . . . . . . . .. 4-148
CY7C271A
16K x 16 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-155
CY7C276
32K x 8 Reprogrammable Registered PROM .................................... 4-161
CY7C277
1Kx8PROM .............................................................. 4-168
CY7C281A
1Kx8PROM .............................................................. 4-168
CY7C282A
CY7C287
64K x 8 Reprogrammable Registered PROM .................................... 4-174
CY7C291A
2K x 8 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-180
CY7C292A
2K x 8 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-180
CY7C293A
2K x 8 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-180
Non-Volatile Memory Programming Information ............................................................ 4-189
Introduction to CMOS
Non-Volatile Memories
large variations of power supply voltage, creating erroneous
function or transiellt performance failures.
• All device test loads should be located within 2" of device
outputs.
• Do not leave any inputs disconnected (floating) during any
tests.
• Do not attempt to perform threshold tests under AC conditions. Large amplitude, fast ground current transients normally occur as the device out,Puts discharge the load capacitances. These transients flowmg through the parasitic
inductance between the device ground pin and the test sys-
tern ground can create significant reductions in observable
input noise immunity.
• VOH and VOL are absolute voltages with respect to device
ground pin and include all overshoots due to system and/or
tester noise. Do not attempt to test these values without suitable equipment.
• Capacitance is tested initially and after any design or process
changes that may affect these parameters.
• The CMOS process does not provide a clamp diode. However,
the Cypress 'PROM Products are insensitive to - 3V dc input
levels and -5V undershoot pulses of less than 10 ns (measured at 50%).
Switching Tests
AC Test Loads and Wavefonns
TI
J
R1
R1
5V
OUTPUT
'
CL
~~8~~~NG
-=
SCOPE
R2
ALL INPUT PULSES
OUTP~~TI
5pF
~~8~~~NG
SCOPE
(a) Nonnal Load
J
3.0V--90%
R2
GND
-=
(b) High Z Load
INTRO·1
Equivalent to:
INTRO-2
THEvENIN EQUIVALENT
OUTPUT~VTH
Load circuit (a) is used to test all switching characteristics except
High Z parameters. Load circuit (b) is used to test High Z parameters.,Rl is a resistor connected from the output to Vee and R2 is
connected between the output and ground for testing purposes.
Values of Rl and R2 are given in the individual datasheet for each
product. Speed is measured at 1.5V reference levels except for
delay to output High Z.
Document #: 38-00234-A
4-2
CY27C64.
fl:rcYPRESS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65 ° C to + 150° C
Ambient Thmperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential
(DIP Pin 28 to Pin 14) ................... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5Vto +7.0V
DC Input Voltage ....................... -3.0V to + 7.0V
DC Program Voltage ............................. 13.0V
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
UV Exposure ............................ 7258 Wsec/cm 2
Operating Range
Range
Commercial
Industrial[2]
Ambient
Temperature
O°C to +70°C
Vee
5V ± 10%
-40°C to +85°C
5V± 10%
Military[3]
-55°C to + 125°C
5V± 10%
Electrical Characteristics Over the Operating Rangd4, 5]
Parameter
Description
Test Conditions
Min.
Max.
Unit
0.4
V
VOH
Output HIGH Voltage
Vee = Min., IOH = -4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 16.0 rnA
VIR
Input HIGH Voltage
VIL
Input LOW Voltage
IJX
Input Current
VeD
Input Diode Clamp
Voltage
loz
Output Leakage Current
GNDS VOUTS Vee,
Output Disabled
-10
+10
JAA
los
Output Short
Circuit Currentl6]
Vee = Max., VOUT = GND
-20
-90
rnA
lee
Power Supply Current
Vee = Max., VIN = 2.0V,
lOUT = ornA
f=10MHz
Com'l
80
rnA
Mil
100
V
Chip Enable Inactive,
CE = VIR, lOUT = 0 rnA
Com'l
15
Mil
15
2.0
V
-10
GND S VIN S Vee
Standby Supply Current
ISB
2.4
0.8
V
+10
JAA
Note 5
rnA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = S.OV
Max.
Unit
10
pF
10
pF
Notes:
2.
3.
4.
Contact a Cypress representative regarding industrial temperature
range specification.
TA is the "instant on" case temperature.
See the last page ofthis specification for Group A subgroup testing
5.
6.
information.
4-4
See the "Introduction to CMOS NVMs" section of the Cypress Data
Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
.V&PRESS
CY27C64
Erasure Characteristics
EPROM is exposed to high-intensity UV light for an extended
period ofti'lle.
7258 Wsec/cm2 is the recommended maximum dosage.
Wavelengths of light less than 4000 angstroms begin to erase the
devices in the windowed package. For this reason, an opaque label should be placed over the window if the EPROM is exposed
to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2. For an ultraviolet lamp
with a 12 mW/cm 2 power rating, the exposure time would be approximately 35 minutes. The CY27C64 needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
Programming Modes
Programming support is available from Cypress as well as from a
number of third party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative. Wben programming, select the Cypress
CY7C266 algorithm.
Table 1. Mode Selection
Pin Function[7, 8]
As
A,
AlO
Au
Au
CE
OE
VFY
PGM
LAT
NA
NA
CE
Vpp
D7
Do
Read
As
A9
AlO
Au
A12
VIL
VIL
07
00
Standby
X
X
X
X
X
VIH
X
Three-Stated
Three-Stated
Normal Operation
Mode
Program
As
A9
AlO
Au
A12
VIL
VIH
Program
VIHP
VILP
VILP
VILP
VILP
VILP
Vpp
D7
Do
Program Verify
VILP
VIHP
VILP
VILP
VILP
VILP
Vpp
07
00
Output Disable
Program Inhibit
VIHP
VIHP
VILP
VILP
VILP
VILP
Vpp
Blank Check
VILP
VIHP
VILP
VILP
VILP
VILP
Vpp
Notes:
7.
D7 - Do
X = "don't care" but must not exceed Vee
+ 5%.
8.
PLCC
Top View
<~:l3~~~~
Vpp
NC
NC
As
As
l'GM
~A12
NA
AslA11
vpp
A,jA,
A,/As
A,iAs
LAT
CE
NC
07
D.
Os
D.
O.
00
5
4 3 2t~323130
29
28
27C64
27
7
26
8
25
9
24
10
23
11
22
12
21
13
14151617181920
6
0
'iJF'I
l'GM
NA
NC
Vpp
LAT
cr
07
D.
c~~~O>d'"~
27C64-67
27C64-56
Fignre 1. Programming Pinout
4-6
07
Address As - A 12 must be latched through lines Ao mingmodes.
DIP/CerDIP
Top View
'iJF'I
Three-Stated
00
A4 in Program-
CY27C64
Ordering Information[9]
Speed
(ns)
70
90
120
150
200
Ordering Code
Package
Name
Package 1Ype
CY27C64-70JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27C64-70PC
P15
28-Lead (600-MiI) Molded DIP
CY27C64-70WC
W16
28-Lead (600-MiI) Windowed CerDIP
CY27C64-90JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27C64-90PC
P15
28-Lead (600-MiI) Molded DIP
CY27C64-90WC
W16
28-Lead (600-MiI) Windowed CerDIP
CY27C64-120JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27C64-120PC
P15
28-Lead (600-MiI) Molded DIP
CY27C64-120WC
W16
28-Lead (600-MiI) Windowed CerDIP
CY27C64-150JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27C64-150PC
P15
28-Lead (600-MiI) Molded DIP
CY27C64-150WC
W16
28-Lead (600-MiI) Windowed CerDIP
CY27C64-20OJC
J65
32-Lead Plastic Leaded Chip Carrier
CY27C64- 200PC
P15
28-Lead (600-MiI) Molded DIP
CY27C64-200WC
W16
28-Lead (600-MiI) Windowed CerDIP
Note:
9.
Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIH
VIL
IIX
Ioz
Icc
ISB
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameter
Subgroups
tAA
tOE
tCE
7, 8, 9, 10, 11
7,8,9, 10, 11
7,8,9,10,11
Document #: 38-00448
4-8
Operating
Range
Commercial
Commercial
Commercial
Commercial
Commercial
CY27COIO
ADVANCED INFORMATION
Pin Configurations (continued)
TSOP
ThpView
C010·4
Selection Guide
27COIO-70
27COIO-90
27COIO-120
27COIO-1SO
27COIO-200
Maximum Access Time (ns)
70
90
120
150
200
CE Access Time (ns)
70
90
120
150
200
OE Access Time (ns)
25
30
40
50
60
Com'l
40
40
40
40
40
Mil
50
50
50
50
50
led l ] (rnA)
Power Supply Current
ISB[2J(rnA)
Stand-by Current
Com'l
15
15
15
15
15
Mil
25
25
25
25
25
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to +150°C
Ambient Thmperature with
Power Applied ........................ -55°C to +125°C
Supply Voltage to Ground Potential ......... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to +5.5V
DC Input Voltage ........................ -3.0V to +7.0V
1ransient Input Voltage. . . . . . . . . . . . . . . .. -3.0V for <20 ns
DC Program Voltage .............................. 13.0V
Noles:
L Vee = Max., lOUT = 0 rnA, f=5 MHz.
2. Vee Max., CE VIH.
=
=
UV Erasure .............................. 7258 Wsec/cm 2
Static Discharge Voltage ..................... ,.. >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature
O°Cto +70°C
Vee
5V ± 10%
Industria\[3]
-40°C to +85°C
5V ± 10%
Military[4]
-55°C tp + 125°C
5V ± 10%
Range
Commercial
3.
4.
4-10
Contact a Cypress representative for industrial temperature range
specification.
.
TA is the "instant on" case ~emperature.
CY27COIO
ADVANCED INFORMATION
Switching Characteristics Over the Operating Range
27COIO-70
Parameter
Description
Min.
Max.
27COIO-90
Min.
Max.
27COIO-120
27COIO-150
27COIO-200
Min.
Min.
Min.
Max.
Max.
Max.
Unit
tAA
Address to Output
Valid
70
90
120
150
200
ns
tOE
OE Active to Output
Valid
25
30
40
50
60
ns
tHZOE
OE Inactive to High Z
25
30
40
50
60
ns
tCE
CEActiveto
Output Valid
70
90
120
150
200
ns
30
ns
65
ns
tHZCE
CE Inactive to High Z
tpu
~Active to Power·Up
tpD
CE Inactive to PowerDown
tOH
Output Data Hold
25
0
60
0
30
30
0
0
65
0
30
0
65
65
0
ns
0
0
0
ns
Switching Waveform
ICC
tpD
ADDRB
C010·7
4-12
ADVANCED INFORMATION
CY27COIO
Ordering Information[lOl
Speed
(ns)
70
90
120
150
Ordering Code
. Package 'Jype
CY27COIO-70JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27COlO-70PC
P15
32-Lead (600-Mil) Molded DIP
CY27COIO-70WC
W20
32-Lead (600-Mil) Windowed CerDIP
CY27COIO-70ZC
Z32
32-Lead Thin Small Outline Package
CY27COIO-70DMB
D20
32-Lead (600-Mil) CerDIP
CY27COIO-70LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27COIO-70QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27COIO-70WMB
W20
32-Lead (600-Mil) Windowed CerDIP
CY27COIO-90JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27COIO-90PC
P19
32-Lead (600-Mil) Molded DIP
CY27COlO-90WC
W20
32-Lead (600-Mil) Windowed CerDIP
CY27COlO-90ZC
Z32
32-Lead Thin Small Outline Package
CY27COlO-90DMB
D20
32-Lead (600-Mil) CerDIP
CY27COlO-90LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27COI0-90QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27COlO-90WMB
W20
32-Lead (600-MiI) Windowed CerDIP
CY27COI0-120JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27COIO-120PC
P19
32-Lead (6oo-Mil) Molded DIP
CY27COIO-120WC
W20
32-Lead (600-Mil) Windowed CerDIP
CY27COlO-120ZC
Z32
32-Lead Thin Small Outline Package
CY27COlO-120DMB
D20
32-Lead (600-Mil) CerDIP
CY27COI0-120LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27COI0-120QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27COlO-120WMB
W20
32-Lead (600-Mil) Windowed CerDIP
CY27COI0-150JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27COI0-150PC
P19
32-Lead (6oo-Mil) Molded DIP
W20
32-Lead (600-Mil) Windowed CerDIP
Z32
32-Lead Thin Small Outline Package
CY27COIO-150WC
CY27COIO-150ZC
CY27COIO-150DMB
CY27COIO-150LMB
200
Package
Name
.
D20
32-Lead (600-Mil) CerDIP
L55
32-Pin Rectangular Leadless Chip Carrier
CY27COIO-150QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27COI0-150WMB
W20
32-Lead (600-Mil) Windowed CerDIP
CY27COI0-200JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27COlO- 200PC
P19
32-Lead (600-Mil) Molded DIP
CY27COlO-200WC
W20
32-Lead (600-Mil) Windowed CerDIP
CY27COIO- 200ZC
Z32
32-Lead Thin SmaIl Outline Package
CY27COIO-2ooDMB
D20
32-Lead (6oo-Mil) CerDIP
CY27COIO-200LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27COlO-200QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27COlO-200WMB
W20
32-Lead (600-Mil) Windowed CerDIP
Notes:
10. Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product availability.
4-14
Operating
Range
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
CY27C020
ADVANCED INFORMATION
256K X 8 CMOS EPROM
Features
Functional Description
• CMOS for optimum speed/power
• High speed
- tAA = 70 ns max.
• Low power
-140mWmax.
- Less than 550 "W when deselected
• Byte-wide memory organization
• 100% reprogrammable in the
windowed package
• EPROM technology
• Capable of withstanding >2001V
static discharge
• Available in
-32·pin PLCC
-32·pin TSOP-I
-32·pin, 600-mil plastic or
hermetic DIP
- 32-pin hermetic LCC
The CY27C020 is a high-performance,
2-megabit CMOS EPROM organized in
256 Kbytes. It is available in industry-standard 32-pin, 600-mil DIP, 32-pin LCC and
PLCC, and 32-pin TSOP-J packages. The
CY27C020 is available in windowed and
opaque packages. Windowed packages allow the device to be erased with UV light
for 100% reprogrammability.
The CY27C020 is equipped with a powerdown chip enable (CE) input and output
enable (OE). When CE is deasserted, the
device powers down to a low-power standby mode. The OE pin three-states the outputs without putting the device into standby mode. While CE offers lower power,
OE provides amore rapid transition to and
from three-stated outputs.
Logic Block Diagram
The memory cells utilize proven EPROM
floating-gate technology and byte-wide intelligent programming algorithms. The
EPROM cell requires only 12.75 V for the
supervoltage and low programming current allows for gang programming. The
device allows for each memory location to
be tested 100%, because each location is
written to, erased, and repeatedly exercised prior to encapsulation. Each device
is also tested for AC performance to guarantee that the product will meet DC and
AC specification limits after customer
programming.
The CY27C020 is read by asserting both
the CE and the OE inputs. The contents of
the memory location selected by the address on inputs A17- Ao will appear at the
outputs 07-00.
Pin Configurations
DIP
As--'----.
TopVJew
A,
00
As
As
As
03
O.
O.
4
A'2
A,
0,
As
Vee
l'llM
An
A'B
A,.
0,
PROGRAMMABLE
ARRAY
1
Vpp
A2
A,.
A13
As
As
As
As
OE
A2
A,
CEO
As
As
An
A,o
0,
0,
O.
O.
03
As
00
0,
O2
GND
0,
POWER DOWN
C0202
LCC/PLCC
TopVJew
0,
NIt)a)~gl~ r--.
<.«»
Il.
<:
43 2 L1132313~
A,
As
As
As
As
As
CEO--L---t
OE----;
7
B
9
As
10
11
12
00
13
A,
OUTPUT ENABLE
DECODER
5
6
0
26
27
26
25
24
23
22
21
14151617181920
C0201
.... CIIe (')~ It) co
0 0 zacoc
'"
4-16
A,.
A'3
As
As
~
A,o
ClE
1
0,
C0200
.~YPRESS
ADVANCED INFORMATION
CY27C020
Electrical Characteristics Over the Operating Rangel6, 7]
Parameter
Description
Test Conditions
Min.
-400!JA
VOH
Output HIGH Voltage
Vee = Min., IOH =
VOL
Output LOW Voltage
Vee = Min., IOL = 2.1 rnA
VIH
Input HIGH Level
Guaranteed Input Logical HIGH
Voltage for All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW
Voltage for All Inputs
Max.
Unit
2.4
2.0
V
0.45
V
Vcc+O.5
V
0.8
V
IIX
Input Leakage Current
GNDs VINS Vee
-10
+10
Ioz
Output ~eakage Current
GND s VOUT s Vee,
Output Disable
-10
+10
!JA
!JA
lee
Power Supply Current
Vee=Max.,
IOUT=OrnA,
f=5MHz
Stand-By Current
ISB
&=Max.,
E=VIH
Corn'l
25
rnA
Mil
30
rnA
Corn'l
1
rnA
Mil
1
rnA
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vcc= 5.0V
Notes:
6.' See the last page ofthis specification for Group Asubgroup testing infonnation.
Max.
Unit
10
pF
10
pF
7. See Introduction to CMOS PROMs in this Data Book for general infonnation on testing.
.
AC Test Loads and Waveforms
-90, -120, -150, -200 DEVICES
2.4V----
R22.7KQ
OUTPUT~-~-~-;Cr-~-~~---O 5V
0.45V
DIODES= 1N3064
OR EQUIVALENT
INPUT
OUTPUT
INPUTS ARE DRIVEN AT 2.4V FOR A
LOGIC 1 AND 0.45V FOR A LOGIC O.
-70 DEVICES
3.0V----
CL = 100 pF FOR -90, -120, -150, -200 DEVICES
CL = 30 pF FOR - 70 DEVICES
GND
INPUT
OUTPUT
INPUTS ARE DRIVEN AT 3.0V FOR A
LOGIC 1 AND O.OV FOR A LOGIC O.
C0205
4-18
C0206
~YPRESS
ADVANCED INFORMATION
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase the
CY27C020 in the windowed package. For this reason, an opaque
label should be placed over the window. if the EPROM is exposed
to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2• For an ultraviolet lamp
with a 12 m W/cm2 power rating, the exposure time would be approximately 35 minutes. The CY27C020 needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
CY27C020
EPROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum
dosage.
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Thble 1. Programming Electrical Characteristics
Parameter
Description
Min.
Max.
12.5
13
Unit
V
50
rnA
Vpp
Programming Power Supply
Ipp
Programming Supply Current
VIHP
Programming Input Voltage HIGH
3.0
Vee
V
VILP
Programming Input Voltage LOW
-0.5
0.4
V
Veep
Programming Vee
6.0
6.5
V
Thble 2. Mode Selection
Pin FunctionL~j
OE
PGM
Vpp
Ao
A9
Data
VIL
VIL
X
VIH
07 - 00
VIH
X
VIH
An
An
A9
VIL
A9
HighZ
Vee0.3V
X
X
VIH
X
X
HighZ
Mode
CE
Read
Output Disable
Stand-by (CMOS)
Stand-by (TIL)
VlH
X
X
VlH
X
X
HighZ
Program
VILP
VlHP
VILP
VPP
A9
D7- D O
A9
07- 0 0
HighZ
Note 10
Program Verify
VILP
VILP
VIHP
VPP
Program Inhibit
VILP
VIHP
VIHP
VPP
An
An
An
Signature Read (MFG)
VIL
VIL
X
VIH
VIL
A9
VHV[9j
Signature Read (DEV)
VIL
VIL
X
VIH
VlH
VHV[8j
Note:
8. X can be VIL or VlH.
9. VHV=12V±0.5V
10. To be detennined.
4-20
34H
~YPRESS
.===;;;;;;AD=;;;;;;JI/t;;;;;;N;;;;;;C;;;;;;'E;;;;;;V;;;;;;1;;;;;;N;;;;;;F;;;;;;O;;;;;;'RMA=;;;;;;Tf,;;;;;;O;;;;;;'N===C;;;;;;Y;;;;;;2;;;;;;7C;;;;;;O;;;;;;2=O.
MILITARY SPECIFlCATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VIL
1,2,3
Ilx
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISB
1,2,3
Switching Characteristics
Parameter
Subgroups
tAA
7, 8, 9, 10, 11
tOE
7,8, 9, 10, 11
tCE
7, 8, 9, 10, 11
Document #: 38-00449
4-22
- -~
.'CYPRESS
ADVANCED INFORMATION
CY27C040
Pin Configurations (continued)
TSOP
'Thp View
C04O·4
Selection Guide
27C040-70
27C040-90
27C040-120
27C040-150
27C040-200
Maximum Access Time (ns)
70
90
120
150
200
CE Access Time (ns)
70
90
120
150
200
OE Access Time (ns)
30
35
40
50
60
25
25
25
25
25
30
30
30
30
Ied l ) (rnA)
Power Supply Current
I Com'l
I Mil
ISB[2] (!1A) CMOS
Stand-by Current
100
100
100
100
100
IS8[3) (rnA) TTL
Stand-by Current
1
1
1
1
1
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Temperature with
Power Applied ........................ -55°C to + 125°C
Supply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to +5.5V
DC Input Voltage ........................ -3.0V to +7.0V
Transient Input Voltage. . . . . . . . . . . . . . . .. -3.0V for <20 ns
DC Program Voltage .............................. 13.0V
Notes:
1. vee = Max., lOUT = 0 rnA, f=5 MHz.
2. Vee = Max., CE = Vee :- O.3V to Vee
3. Vee Max., CE Vrn.
=
=
UV Erasure .............................. 7258 Wsec/crn2
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . .. >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature
O°C to +70°C
Vee
5V± 10%
Industrial[4)
-40°C to +85°C
5V± 10%
Military[5)
-55°C to +125°C
5V ± 10%
Range
Commercial
4.
+ LOY.
S.
4-24
Contact a Cypress representative for industrial temperature range
specification.
TA is the "instant on" case temperature.
CY27C040
ADVANCED INFORMATION
Switching Characteristics Over the Operating Range
"
27C04O-70
Parameter
Description
Min.
Max.
27C040-90
Min.
Max.
27C04O-120
27C04O-150
27C040-200
Min.
Min.
Min.
Max.
Max.
Max.
Unit
tAA
Address to Output
Valid
70
90
120
150
200
ns
toE
OE Active to Output
30
35
40
50
60
ns
tHWE
OE Inactive to High Z
25
25
30
30
40
ns
tCE
CEActiveto
Output Valid
70
90
120
150
200
ns
40
ns
Valid
tHZCE
CE Inactive to High Z
tpu
CEActive to Power-Up
tpD
CE Inactive to PowerDown
tOH
Output Data Hold
25
25
0
0
60
0
30
0
65
0
30
0
65
0
0
65
ns
70
0
ns
0
ns
Switching Wavefonn
ICC
tpo
ADDRB
0 0 -07
CQ4O·7
4-26
~YPRESS
ADVANCED INFORMATION
CY27C040
Ordering Information!ll]
Speed
(ns)
70
90
120
Ordering Code
CY27C040-70JC
J65
32-Lead Plastic Leaded Chip Carrier
PI5
32-Lead (600-Mil) Molded DIP
CY27C040-70WC
W20
32-Lead (600-Mil) Windowed CerDIP
CY27C040-70ZC
Z32
32-Lead Thin SmaIl Outline Package
CY27C040-90JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27C040-90PC
P19
32-Lead (600-Mil) Molded DIP
CY27C040-90WC
W20
32-Lead (600-Mil) Windowed CerDIP
CY27C040-90ZC
Z32
32-Lead Thin Small Outline Package
CY27C040-90DMB
D20
32-Lead (600-Mil) CerDIP
CY27C040-90LMB
32-Pin Rectangular Leadless Chip Carrier
CY27C040-90QMB
L55
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27C040-90WMB
W20
32-Lead (600-Mil) Windowed CerDIP
CY27C040-I20JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27C040-I20PC
PI9
32-Lead (600-Mil) Molded DIP
CY27C040-I20WC
CY27C040-I20ZC
W20
Z32
32-Lead Thin Small Outline Package
CY27C040-I20DMB
D20
32-Lead (600-Mil) CerDIP
CY27C040-I20LMB
L55
Q55
32-Pin Rectangular Leadless Chip Carrier
CY27C040-I50JC
W20
J65
32-Lead (600-Mil) Windowed CerDIP
32-Lead Plastic Leaded Chip Carrier
CY27C040-150PC
P19
32-Lead (600-Mil) Molded DIP
CY27C040-150WC
W20
32-Lead (600"Mil) Windowed CerDIP
CY27C040-150ZC
Z32
32-Lead Thin Small Outline Package
CY27C04O-I50DMB
D20
CY27C040-150LMB
32-Lead (600-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
CY27C040-150QMB
L55
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27C040-150WMB
W20
32-Lead (600-Mil) Windowed CerDIP
CY27C040-200JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27C040- 200PC
P19
CY27C040-200WC
CY27C040-200ZC
W20
32-Lead (600-Mil) Molded DIP
32-Lead (600-MiI) Windowed CerDIP
Z32
32-Lead Thin Small Outline Package
CY27C040-200DMB
D20
32-Lead (600-Mil) CerDIP
CY27C040-200LMB
32-Pin Rectangular Leadless Chip Carrier
CY27C040-200QMB
L55
Q55
CY27C040-200WMB
W20
32-Lead (600-Mil) Windowed CerDIP
CY27C040-120WMB
200
Package 'Jype
CY27C040-70PC
CY27C040-I20QMB
150
Package
Name
Operating
Range
Commercial
Commercial
Military
Commercial
32-Lead (600-Mil) Windowed CerDIP
Military
32-Pin Windowed Rectangular Leadless Chip Carrier
32-Pin Windowed Rectangular Leadless Chip Carrier
Notes:
11. Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product availability.
4-28
Commercial
Military
Commercial
Military
CY27C128
128K (16K X 8-Bit) CMOS EPROM
Features
• Wide speed range
- 45 ns to 200 ns (commercial and
military)
• Lowpower
-248 mW (commercial)
-303 mW (military)
• Low standby power
- Less than 83 mW when deselected
• ±10% Power supply tolerance
Functional Description
The CY27C128 is a high-performance
16,384-word by 8-bit CMOS EPROM.
When disabled (CE HIGH), the
CY27C128 automatically powers down
into a low-power stand-by mode. The
CY27C128 is packaged in the industry
standard 600-mil DIP and LCC packages.
The CY27C128 is also available in a CerDIP package equipped with an erasure
window to provide for reprogrammability.
When exposed to UV light, the EPROM
is erased and can be reprogrammed. The
memory cells utilize proven EPROM
floating gate technology and byte-wide intelligent programming algorithms.
The CY27C128 offers the advantage of
lower power and superior performance and
programming yield. The EPROM cell requires only 12.5V for the super voltage,
Logic Block Diagram
and low current requirements allow for
gang programming. The EPROM cells allow each memory location to be tested
100% because each location is written
into, erased, and repeatedly exercised
prior to encapsulation. Each EPROM is
also tested for AC performance to guarantee that after customer programming,
the product will meet both DC and AC
specification limits.
Reading the CY27C128 is accom~hed
~lacing active LOW signals on OE and
CEo The contents of the memory location
addressed by the address lines (Ao - A13)
will become available on the output lines
(00 - 07).
Pin Configurations
0,
ROW
ADDRESS
o.
o.
ADDRESS
DECODER
O.
A12
A,
COWMN
03
l'Glif
3
As
As
Po"
As
Ao
02
O2
GND
A'3
As
A,
Al1
OE
A10
CE
Ao
00
0,
~::::======:J
~ oF >R:5 ~I~.f
Vee
Vpp
A,
ADDRESS
LCC/PLCC [IJ
DlP/Flatpack
8x10F128
MULTIPLEXER
11
0,
0,
O.
O.
03
4 3 2l~323130
As
A.
Po"
As
As
A,
Ao
NC
00
5
6
7
8
9
27C128
0
'0
11
12
13
29
28
27
26
25
24
23
22
21
As
As
Al1
NC
OE
A,o
cr
0,
o.
14151617181920
.....NC::J tt)'2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Thmperature
O°Cto +700C
5V ± 10%
Industrial[4]
-40°C to +85°C
5V± 10%
Military[5]
-55°C to +125°C
5V ± 10%
Range
Commercial
3.
4.
4-46
Vee
Contact a Cypress representative for industrial temperature range
specification.
TA is the "instant on" case temperature.
ADVANCED INFORMATION
CsrcYPRESS
CY27C512
Switching Characteristics Over the Operating Range
27CS12-70
Min.
27CS12-90
27CS12-120
27CS12-1S0
27CS12-200
Min.
Min.
Max.
Unit
tAA
70
90
120
150
200
ns
tOE
OE Active to Output
Valid
25
30
40
50
60
ns
tHZOE
OE Inactive to High Z
25
30
40
50
60
ns
tCE
CEActiveto
Output Valid
70
90
120
150
200
ns
tRZCE
"CE Inactive to High Z
30
ns
tpu
CE Active to Power·Up
tPD
CE Inactive to Power·
Down
tOR
Output Data Hold
Description
Max.
Min.
Min.
Address to Output
Valid
Parameter
25
0
30
0
60
0
Max.
Max.
30
0
0
30
0
0
0
65
65
Max.
65
ns
ns
65
0
0
ns
Switching Waveform
ICC
tpo
ADDRB
C512·7
4-48
ADVANCED INFORMATION
CY27C512
Ordering Information[ll]
Speed
(ns)
70
90
120
150
Ordering Code
Package
Name
Operating
Range
Packa~e 'iYpe
CY27C512-70JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27C512-70PC
: .
.
P15
28-Lead (600-Mil) Molded DIP
CY27C512-70WC
W16
28-Lead (600-Mil) Windowed CerDlP
CY27C512-70ZC
Z28
28-Lead Thin Small Outline Package
CY27C512-70DMB
016
48-Lead (600-Mil) CerDlP
CY27C512-70LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Commercial
Military
CY47C512-7OQMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27C512-70WMB
W16
28-Lead (600-MiI) Windowed CerDlP
CY27C512-90JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27C512~90PC
P15
2S-Lead (600-Mil) Molded DIP
CY27C512-90WC
W16
2S-Lead (600-Mil) Windowed CerDlP
CY27C512-90ZC
Z28
28-Lead Thin Small Outline Package
CY27C512-90DMB
D16
28-Lead (600-Mil) CerDlP_
Commercial
Military
-
CY27C512-90LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27C512-90QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27C512-90WMB
W16
28-Lead (600-Mil) Windowed CerDIP
CY27C512-12OJC
J65
32-Lead Plastic Leaded Chip Carrier
CY27C51Z~ 120PC
P15
28-Lead (600-Mil) Molded DIP
CY27C512-120WC
WI6
28-Lead (600-Mil) WindowedCerDlP
CY27C512-120?C
Z28
28-Lead Thin Small Outline Package
CY27C512-120DMB
016
28-Lead (600-MiJ) CerDlP
CY27C512-120LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27C512-120QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27C5I2-120WMB
W16
28-Lead (600-Mil) Windowed CerDlP
CY27C512-150JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
.
CY27C512-150PC
PI5
28-Lead (600-Mil) Molded DIP
CY27C512-150WC
W16
28-Lead (600-Mil) Windowed CerDlP
CY27C512-150ZC
Z28
28-Lead Thin Small Outline Package
CY27C512-150DMB
D16
28-Lead (600-Mil) CerDlP
CY27C5I2-150Ll,\ffi
L55
Military
--
'32-Pin Rectangular Leadless Chip Carrier
CY27C512-150QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27C512-150WMB
W16
28-Lead (600-Mil) Windowed CerDlP
4-50
Commercial
Military
CY27HOIO
128Kx 8 High-Speed CMOS
EPROM
Features
Functional Description
• CMOS for optimum speed/power
• High speed
-tM = 2S ns max. (commercial)
- tM = 3S ns max. (military)
• Low power
-27SmWmax.
- Less than 8S mW when deselected
• Byte-wide memory organization
• 100% reprogrammable in the
windowed package
• EPROM technology
• Capable of withstanding >2001V
static discharge
• Available in
-32-pin PLCC
-32-pin TSOP-I
-32-pin, 600-mil plastic or
hermetic DIP
- 32-pin hermetic LCC
The CY27HOI0 is a high-performance,
I-megabit CMOS EPROM organized in
128 Kbytes. It is available in industry-standard 32-pin, 600-mil DIP, LCC, PLCC, and
TSOP-I packages. These devices offer
high-density storage combined with
40-MHz performance. The CY27HOI0 is
available in windowed and opaque packages. Windowed packages allow the device
to be erased with UV light for 100% reprogrammability.
The CY27HOI0 is e.9!!!Pped with a powerdown c~nable (~input and output
enable (OE). When CE is deasserted, the
device powers down to a low-power standby mode. The OE pin three-states the outputs without putti~the device into standby mode. While CE offers lower power,
OE provides a more rapid transition to and
from three-stated outputs.
Logic Block Diagram
The memory cells utilize proven EPROM
floating-gate technology and byte-wide intelligent programming algorithms. The
EPROM cell requires only 12.75 V for the
supervoltage and low programming current allows for gang programming. The device allows for each memory location to be
tested 100%, because each location is written to, erased, and repeatedly exercised
prior to encapsulation. Each device is also
tested for AC performance to guarantee
that the product will meet DC and AC
specification limits after customer programming.
The CY27HOlO is read by asserting both
the CE and the 'DE inputs. The contents of
the memory location selected by the address on inputs A 16 - Au will appear at the
outputs 07-00'
Pin Configurations
DIP
Ao
Top View
00
A,
Vee
1'G1i.l
NC
A,.
A13
Ao;.
0,
Ao;.
PROGRAMMABLE
ARRAY
~
As
A,
Aa
ADDRESS
DECODER
O.
~
Al1
Ao;.
A2
A,
OE
A,o
CEO
0,
0,
0,
O.
O.
Ao
"-
0,
AlO
Al1
A'2
Aa
Aa
Aa
o.
Ae
4
A'2
A,
A,
02
O.
00
0,
D2
GND
POWER DOWN
A,.
~~~8: 81~o
01«<»
z
A15
A,.
A,
Ae
Ae
~
"Ao;.
CEO
OE
H01~2
LCC/PLCC
Top View
0,
A,.
OUTPUT ENABLE
DECODER
A,
Ao
00
HOlQ·1
43 2 l 1J 323130
29
5
28
6
7
8
9
10
11
12
13
27
26
25
24
0
23
22
21
Aa
"Al1
OE
A,o
CE
0,
141516171~20
..... (\10 Cf)o:t
II)
co
OOlBO OOO
4-52
A,.
A,.
H01().3
'~YPRESS
CY27HOIO
Electrical Characteristics Over the Operating RangdS, 6J
27H010-25
27H010-30
Parameter
Test Conditions
Min.
Output HIGH
Voltage
Vee = Min., IOH = -4.0 rnA
2.4
VOL
Output LOW Voltage
Vee = Min., IOL = 12.0 rnA
VIH
Input HIGH Level
Guaranteed Input ~ical
HIGH Voltage for
Inputs
VIL
Input LOW Level
Guaranteed Input Logical
LOW Voltage for All Inputs
IJX
Input Leakage
Current
GND.:5. VIN.:5. Vee
-10
+10
-10
+10
Ioz
Output Leakage
Current
GND.:5. Vour.:5. Vee,
Output Disable
-10
+10
-10
+10
Icc
Power Supply Current
Vee=Max.,
Iour=OrnA,
f=lOMHz
Com'l
ISB
Stand-By Current
Yc.e=Max.,
CE =VIH
Com'l
VOH
Description
Max.
27HOI0-35
Min.
0.45
2.0
Max.
2.4
Vee+ O.5
27H010-45
27H010-55
27H010-70
Min.
Max.
V
0.45
2.0
0.8
Unit
2.4
0.45
V
Vee + 0.5
V
0.8
V
-10
+10
J.IA
-10
+10
J.IA
50
50
rnA
85
60
rnA
15
15
rnA
25
25
rnA
Vee + 0.5
2.0
0.8
75
Mil
15
Mil
Capacitance[6J
Parameter
Description
CIN
Input Capacitance
Cour
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
Unit
10
pF
12
pF
Notes:
5. See the last page ofthis specification for Group A subgroup testing information.
6.
See Introduction to CMOS PROMs in this Data Book for general in- .
formation on testing.
AC Test Loads and Waveforms
TI TI
~~oo
OUTP:
30 PF
R2
197Q
I
~~8~~1flNG -=
OUTP~~
-=
SCOPE
5 PF
I
~~8~~1flNG -=
3.0V--90%
R2
1970
GND
-=
SCOPE
(b)
(a)
Equivalent to:
ALL INPUT PULSES
~~oo
H010-5
THEvENIN EQUIVALENT
OUTPUT~
1.91V
4-54
HOlO·6
~YPRESS
CY27HOIO
Erasure Characteristics
Wavelengths of light less than 4000 A begin to erase the
CY27HOlO in the windowed package. For this reason, an opaque
label should be placed over the window if the EPROM is exPosed
to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Afor a minimum dose (UV intensity multiplied by
exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12
mW/cm2 power rating, the exposure time would be apprmq!Dately
35 minutes. The CY27H010 needs to be within 1 inch of the lamp
during erasure. Permanent damage may result if the EPROM is
exposed to higil-intensity UV light for an extended period of time.
7258 Wsec/cm2 is the recommended maximum dosage.
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Programming Electrical Characteristics
Description
Parameter
Min.
Max.
12.5
13
V
50
rnA
3.0
Vee
V
-0.5
0.4
V
6.5
V
Vpp
Programming Power Supply
Ipp
Programming Supply CUrrent
VIHP
Programming Input Voltage HIGH
VILP
Programming Input Voltage LOW
Veep
Programming Vee
6.0
Unit
Table 2. Mode Selection
Pin Functionl7]
Mode
CE
OE
PGM
Vpp
Read
VIL
VIL
X
VIH
A9
Data
A9
A9
07- 00
Output Disable
VIL
VIH
X
VIH
Ao
Ao
Ao
Stand-by
VIH
X
X
VIH
X
X
HighZ
Program
VILP
VIHP
VILP
Vpp
VILP
VILP
VIHP
VPP
Program Inhibit
VILP
VIHP
VIHP
VPP
A9
A9
A9
D7 - Do
Program Verify
Ao
Ao
Ao
Signature Read (MFG)
VIL
VIL
X
VIH
VIL
VHV[8]
34H
VIL
X
VIH
VHV[8]
1DH
Signature Read (DEV)
VIL
VIH
Nole:
7. X can be VIL or VIH.
8. Virv=12V±O.SV
4-56
HighZ
07 - 00
HighZ
CY27HOIO
QPRESS
Ordering Information[9]
Speed
(ns)
25
30
35
45
55
Ordering Code
Packiige
Name
Package lYPe
CY27HOIO-25HC
H65
32-Pin Windowed Leaded Chip Carrier
CY27H01O-25JC
J65
32-Lead Plastic Leaded Chip Carrier
32-Lead Thin Small Outline Package
CY27HOlO- 25ZC
Z32
CY27HOIO- 30HC
H65
32-Pin Windowed Leaded Chip Carrier
CY27H01O-30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27HOlO-30PC
P19
32-Lead (600-Mil) Molded DIP
CY27HOlO-30WC
W20
32-Lead (600-Mil) Windowed CerDIP
CY27H01O- 30ZC
Z32
32-Lead Thin Small Outline Package
CY27HOIO- 35HC
H65
32-Pin Windowed Leaded Chip Carrier
CY27HOlO-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27HOlO-35PC
P19
32-Lead (600-Mil) Molded DIP
CY27HOIO-35WC
W20
32-Lead (600-Mil) Windowed CerDIP
CY27H01O- 35ZC
Z32
32-Lead Thin Small Outline Package
CY27HOIO- 35HMB
H65
32-Pin Windowed Leaded Chip Carrier
CY27HOIO- 35LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27H01O-35QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27HOlO-45HC
H65
32-PinWindowed Leaded Chip Carrier
CY27HOIO-45JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27HOIO-45PC
P19
32-Lead (600-Mil) Molded DIP
CY27H010-45WC
W20
32-Lead (600-Mil) Windowed CerDIP
CY27HOIO-45ZC
Z32
32-Lead Thin Small Outline Package
CY27HOlO-450MB
020
32-Lead (600-Mil) CerDIP
CY27HOlO-45HMB
H65
32-Pin Windowed Leaded Chip Carrier
CY27HQlO-45LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27HChO-45QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27HOlO-45WMB
W20
32-Lead (600-Mil) Windowed CerDIP
CY27HOlO-55HC
H65
32-Pin Windowed Leaded Chip Carrier
CY27HOlO-55JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27HOlO-55PC
P19
32-Lead (600-Mil) Molded DIP
CY27HOIO-55WC
W20
32-Lead (600-Mil) Windowed CerDIP
CY27ij010-55ZC
Z32
32-Lead Thin Small Outline Package
CY27HOlO-550MB
020
32-Lead (600-Mil) CerDIP
CY27HOIO-55HMB
H65
32-Pin Windowed Leaded Chip Carrier
CY27HOlO- 55LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27HOlO-55QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27HOlO-55WMB
W20
32-Lead (600-Mil) Windowed CerDIP
Notes:
9. Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product availability.
4-58
OperatiJtg
Range
Commercial
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
CY27H256
PRELIMINARY
32Kx 8 High-Speed CMOS
EPROM
Features
• CMOS for optimum speed/power
• High speed
-tAA = 25 ns max. (commercial)
- tAA = 35 ns max. (military)
• Low power
-275mWmax.
-Less than 85 mWwhen deselected
• Byte-wide memory organization
• 100% reprogrammable in the
windowed package
• EPROM technology
• Capable of withstanding >2001 V
static discharge
• Available in
- 32-pin PLCC
- 28-pin TSOP-I
-28-pin, 600-mil plastic or
hermetic DIP
- 32-pin hermetic LCC
Functional Description
rapid transition to and from three-stated
outputs.
The CY27H256 is a high-performance,
256K CMOS EPROM organized in 32
Kbytes. It is available in industry-standard
28-pin, 600-mil DIP, 32-pin LCC and
PLCC, and 28-pin TSOP-I packages.
These devices offer high-density storage
combined with40-MHzperformance. The
CY27H256 is available in windowed and
opaque packages. Windowed packages allow the device to be erased with UV light
for 100% reprogrammability.
The memory cells utilize proven EPROM
fioating-gate technology and byte-wide intelligent programming algorithms. The
EPROM cell requires only 12.75 V for the
supervoltage and low programming current allows for gang programming. The device lIilows for each memory location to be
tested 100%, because each location is written to, erased, and repeatedly exercised
prior to encapsulation. Each device is also
tested for AC performance to guarantee
that the product will meet DC and AC
specification limits after customer programming.
The CY27H256 is equipped with a powerdown chip enable «::~) input as wel~an
output enable (OE) mput. When CE is
deasserted, the device powers down to a
low-power stand-by mode. The OE pin
three-states the outputs without putting
the device into stand-by mode. While CE
offers lower power, OE provides a more
Logic Block Diagram
The CY27H256 is read by asserting both
the CE and the OE inputs. The contents of
the memory location selected by the address on inputs A!4 - Ao will appear at the
outputs 07-00'
Pin Configurations
DIP
Top View
Ao
00
Vpp
A,
PROGRAMMABLE
ARRAY
Aa
A"
A;,
A,.
A;,
O2
A;,
A;,
Os
A"
Aa
OE
A2
A,
cr
o.
Ao
Or
A;,
A7
AODRESS
DECODER
As
A,
Os
A,o
A"
A,s
Ag
A"
AlO
o.
00
0,
O2
GND
Os
O.
03
o.
POWER DOWN
A'2
07
A'3
H256-2
LCe/PLCd!]
Top View
ct~~5$i~
A,.
cr---'---I
OE----I
Vee
A'2
A7
0,
A2
OUTPUT ENABLE
DECODER
H256-1
Note:
1. For LCC/PLCC only: Pins 1 and 17 are common and tied to the die at-
tach pad. They should not be used.
4-60
~YPRESS
PRELIMINARY
CY27H2S6
Electrical Characteristics Over the Operating Rangd6, 7]
27H256-25
27H256-30
Parameter
Description
Test Conditions
Min.
2.4
Max.
27H256-35
Min.
Max.
VOR
Output HIGH
Voltage
Vee = Min., lOR = - 4.0 mA
2.4
VOL
Output LOW Voltage
Vee = Min., IOL = 12.0 mA
VIH
Input HIGH Level
Guaranteed Input Logical
HIGH Voltage for All Inputs
VIL
Input LOW Level
Guaranteed InEut Logical
LOW Voltage or All Inputs
IIX
Input Leakage
Current
GND S VIN S Vee
-10
+10
-10
+10
loz
Output Leakage
Current
GNDs VOUTS Vee,
Output Disable
-10
+10
-10
+10
Icc
Power Supply Current
Vee = Max.,
IOUT=OmA,
f=10 MHz
Com'l
ISB
Stand-By Current
Yc.c=Max.,
CE= VIH
Com'l
0.45
2.0
Vee +0.5
27H256-45
27H256-55
27H256-70
Min.
Max.
2.4
V
0.45
2.0
0.8
Unit
0.45
V
Vee+ 0.5
V
0.8
V
-10
+10
!lA
-10
+10
ttA
50
50
mA
85
60
mA
15
15
mA
25
25
mA
Vee+0.5
2.0
0.8
75
Mil
15
Mil
Capacitance[7]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
6. See the last page of this specification for Group A subgroup testing information.
7.
Max.
Unit
10
pF
10
pF
See Introduction to CMOS PROMs in this Data Book for general information on testing.
AC Test Loads and Waveforms
~~oo
OUTP~~ ~
,~~.~:Fl
INCLUDING
JIG AND
SCOPE
-
1
~~oo
R2
OUTP~~ ~
(a) Nonnal Load
Equivalent to:
,~,.~:Fl
197Q
-
INCLUDING
JIG AND
SCOPE
-
ALL INPUT PULSES
3.0V--90%
R2
1
197Q
(b) High-Z Load
H256-5
THEVENIN EQUIVALENT
OUTPUT~
GND
-
1.91V
4-62
H256-6
~~
PRELIMINARY
"CYPRESS
CY27H256
during erasure. Permanent damage may result if the EPROM is
exposed to high-intensity UV light for an extended period of time.
7258 Wsec/cm2 is the recommended maximum dosage.
Erasure Characteristics
Wavelengths of light less than 4000 A begin to erase the
CY27H256 in the windowed package. For this reason, an opaque
label should be placed over the window if the EPROM is exposed
to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 A for a minimum dose (UV intensity multiplied by
exposure time) of 25 Wsec/cm2• For an ultraviolet lamp with a 12
mW/cm2 power rating, the exposure time would be approximately
35 minutes. The CY27H256 needs to be within 1 inch of the lamp
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Programming Electrical Characteristics
Parameter
Description
Min.
Max.
Unit
12.5
13
V
50
rnA
Programming Input Voltage HIGH
3.0
Vee
V
VILP
Programming Input Voltage LOW
-0.5
0.4
V
Veep
Programming Vee
6.0
6.5
V
Vpp
Programming Power Supply
Ipp
Programming Supply Current
VIHP
Table 2. Mode Selection
Pin FunctionlMJ
Mode
CE
OE
VPP
Ao
A9
Data
07 - 00
A9
HighZ
Read
VIL
VIL
VIH
Output Disable
VIL
VIH
VIH
Ao
Ao
A9
Stand-by
VIH
X
VIH
X
X
HighZ
Program
VILP
VIHP
VPP
A9
D7- D O
Program Verify
VIHP
VILP
VPP
A9
07 - 00
Program Inhibit
VIHP
VIHP
VPP
Ao
Ao
Ao
HighZ
Signature Read (MFG)
VIL
VIL
VIH
VIL
A9
VHy[9j
Signature Read (DEV)
VIL
VIL
VIH
VIH
VHy[9j
21H
Notes:
8. X can be YIL or VIH.
9.
4-64
VHv=12±O.SV
34H
~
PRELIMINARY
&rcYPRESS
CY27H256
Ordering Information[lO]
Speed
(ns)
25
30
35
45
55
70
Ordering Code
Package
Name
Package lYpe
CY27H256-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27H256-25ZC
Z28
28-Lead Thin Small Outline Package
CY27H256-30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27H256 - 30PC
P15
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Windowed CerDIP
CY27H256 - 30WC
W16
CY27H256-30ZC
Z28
28-Lead Thin Small Outline Package
CY27H256-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27H256 - 35PC
P15
28-Lead (600-Mil) Molded DIP
CY27H256-35WC
W16
28-Lead (600-Mil) Windowed CerDIP
CY27H256 - 35ZC
Z28
28-Lead Thin Small Outline Package
CY27H256 - 35LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27H256 - 35QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27H256-45JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27H256-45PC
P15
28-Lead (600-Mil) Molded DIP
CY27H256-45WC
W16
28-Lead (600-Mil) Windowed CerDIP
CY27H256-45ZC
Z28
28-Lead Thin Small Outline Package
CY27H256-45DMB
D16
28-Lead (600-Mil) CerDIP
CY27H256-45LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27H256-45QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27H256-45WMB
W16
28-Lead (600-Mil) Windowed CerDIP
CY27H256-55JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27H256-55PC
P15
28-Lead (600-Mil) Molded DIP
CY27H256-55WC
W16
28-Lead (600-Mil) Windowed CerDIP
CY27H256- 55ZC
Z28
28-Lead Thin Small Outline Package
CY27H256-55DMB
D16
28-Lead (600-Mil) CerDIP
CY27H256- 55LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27H256-55QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27H256-55WMB
W16
28-Lead (600-Mil) Windowed CerDIP
CY27H256-7OJC
J65
32-Lead Plastic Leaded Chip Carrier
CY27H256-70PC
P15
28-Lead (600-Mil) Molded DIP
CY27H256-70WC
W16
28-Lead (600-Mil) Windowed CerDIP
CY27H256-70ZC
Z28
28-Lead Thin Small Outline Package
CY27H256-70DMB
D16
28-Lead (600-Mil) CerDIP
CY27H256-70LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27H256-70QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27H256-70WMB
W16
28-Lead (600-Mil) Windowed CerDIP
Note:
10. Most of the abov~ products are available in industrial temperature
range. Contact a Cypress representative for specifications and product availability.
4-66
Operating
Range
Commercial
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
CY27H512
PRELIMINARY
64K X 8 High-Speed CMOS
EPROM
Features
Functional Description
• CMOS for optimum speed/power
• Highspeed
-tAA = 25 ns max. (commercial)
- tAA = 35 ns max. (military)
• Low power
-275mWmax.
- Less than 85 mW when deselected
• Byte-wide memory organization
• 100% reprogrammable in the
windowed package
• EPROM technology
• Capable of withstanding >2001V
static discharge
• Available in
-32-pin PLCC
-28-pin TSOP-I
- 28-pin, 600-mil plastic or
hermetic DIP
- 32-pin hermetic LCC
The CY27H512 is a high-performance,
512K CMOS EPROM organized in 64
Kbytes. It is available in industry-standard
28-pin, 600-mil DIP, 32-pin LCC and
PLCC, and 28-pin TSOP-J packages.
These devices offer high-density storage
combined with 40-MHzperformance. The
CY27H512 is available in windowed and
opaque packages. Windowed packages allow the device to be erased with UV light
for 100% reprogrammability.
The CY27H512 is e~ped with a powerdown ch~nable (CE) input and output
enable (OE). When CE is deasserted, the
device powers down to a low-power standbymode. The OE pin three-states the outputs without putting the device into stand!?Lmode. While CE offers lower power,
OE provides a more rapid transition to and
from three-stated outputs.
Logic Block Diagram
The memory cells utilize proven EPROM
floating-gate technology and byte-wide intelligent programming algorithms. The
EPROM cell requires only 12.75 V for the
supervoltage and low programming current allows for gang programming. The device allows for each memory location to be
tested 100%, because each location is written to, erased, and repeatedly exercised
prior to encapsulation. Each device is also
tested for AC performance to guarantee
that the product will meet DC and AC
specification limits after customer programming.
The CY27H512 is read by asserting both
the CE and the OEinputs. The contents of
the memory location selected by the address on inputs A1S-Ao will appear at the
outputs 07-00.
Pin Configurations
DIP
Ao
Top View
A,
Vee
A,.
IV;.
As
A,.
PROGRAMMABLE
ARRAY
A.,
As
As
As
Al1
(lENpp
A10
As
A,
A,
CE
ADDRESS
DECODER
0,
0,
o.
As
D.
A10
03
Al1
A12
H512-2
POWER DOWN
LCC/PLCC[l]
Top View
A'3
A,.
A,.
As
As
A.,
As
IV;.
A,
OE----I
Ao
OUTPUT ENABLE
DECODER
NC
00
H512-1
5
6
7
6
9
10
11
As
As
0
12
21
13
14151617161920
0" rS'~Ild'd' <5'
(!J
Note:
1.
For LCC/PLCC only: Pins 1 and 17 are common and tied to the die attach pad. They should not be used.
4-68
Al1
NC
DENpp
AlO
CE
0,
0,
H512-3
~YPRESS
PRELIMINARY
CY27H512
Electrical Characteristics Over the Operating Rangd6,7]
27H512-25
27H512-30
Max.
27H512-35
Min.
Max.
Test Conditions
Min.
Output HIGH
Voltage
Vee = Min., IOH = -4.0 mA
2.4
VOL
Output LOW Voltage
Vee = Min., IOL = 12.0 mA
VlH
Input HIGH Level
Guaranteed Input Logical
HIGH Voltage for All Inputs
VIL
Input LOW Level
Guaranteed InKut Logical
LOW Voltage or All Inputs
IIX
Input Leakage
Current
GND ~ VIN ~ Vee
-10
+10
-10
+10
Ioz
Output Leakage
Current
GND~ VOUT~ Vee,
-10
+10
-10
+10
Output Disable
Icc
Power Supply Current
Parameter
VOH
Description
Stand-By Current
ISB
2.4
0.45
2.0
Vee+ 0.5
Com'l
tff=Max.,
=VlH
Corn'l
Min.
Unit
Max.
V
2.4
0.45
2.0
0.8
Vee=Max.,
IOUT=OrnA,
f=lOMHz
27H512-45
27H512-55
27H512-70
Vee+0.5
0.45
V
Vee+0.5
V
0.8
V
-10
+10
iJA
-10
+10
iJA
2.0
0:8
75
Mil
15
Mil
50
50
rnA
85
60
mA
15
15
mA
25
25
mA
Capacitance[7]
Parameter
Description
CIN
Input Capacitance
CoUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee
= 5.0V
Max.
Unit
10
pF
10
pF
Notes:
6. See the lastpage of this specification for Group A subgroup testing information.
AC Test Loads and Waveforms
~~oo
OUTP~~ ~
30 PF
~78~~~NG
r
-=
~~oo
R2
197(.1
OUTP~~
-=
SCOPE
5 PF
~78~~~NG
ALL INPUT PULSES
3.0V - - - ~-----......l
90%
R2
197Q
-=
-=
(b)
H512..s
GND
5.3 ns
SCOPE
(a)
Equivalent to:
TI
r
7. See Introduction to CMOS PROMs in this Data Book for general information on testing.
THEVENIN EQUIVALENT
OUTPUT~
1.91V
4-70
H512-6
~
.=::z.
PRELIMINARY
rcYPRESS
Erasure Characteristics
Wavelengths of light less than 4000 A begin to erase the
CY27H512 in the windowed package. For this reason, an opaque
label should be placed over the window if the EPROM is exposed
to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Afor a minimum dose (UV intensity multiplied by
exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12
mW/cm2 power rating, the exposure time would be approximately
35 minutes. The CY27H512 needs to be within 1 inch of the lamp
CY27H512
during erasure. Permanent damage may result if the EPROM is
exposed to high-intensity UV light for an extended period of time.
7258 Wsec/cm2 is the recommended maximum dosage.
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Programming Electrical Characteristics
Parameter
Description
Vpp
Programming Power Supply
Ipp
Programming Supply Current
Min.
Max.
12.5
13
Unit
V
50
rnA
VaIP
Programming Input Voltage HIGH
3.0
Vee
V
VIIY
Programming Input Voltage LOW
-0.5
0.4
V
Veep
Programming VCC
6.0
6.5
V
Table 2. Mode Selection
Pin Functionl"]
Mode
CE
Read
Output Disable
OE/Vpp
Ao
A9
Data
VIL
VIL
07- 0 0
VIH
Ao
Ao
A9
X
A9
HighZ
X
X
HighZ
A9
D7- D O
A9
07 - 00
HighZ
IFH
VIH
X
Program
VILP
Vpp
Program Verify
VILP
VILP
Program Inhibit
VnIP
Vpp
Ao
Ao
Ao
Signature Read (MFG)
VIL
VIL
VIL
A9
VHV[9j
Signature Read (DEV)
VIL
VIL
VIH
VHV[9j
Stand-by
Note:
8.
X can be VIL or VIH.
9.
4-72
VHv=12±0.5\l.
34H
PRELIMINARY
CY27H512
Ordering Information[lQJ
Speed
(ns)
25
30
35
45
55
Ordering Code
Package
Name
Package 'fYpe
CY27H5I2-25HC
H65
32-Pin Windowed Leaded Chip Carrier
CY27H5I2-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27H5I2-25ZC
Z28
28-Lead Thin Small Outline Package
CY27H5I2-30HC
H65
32-Pin Windowed Leaded Chip Carrier
CY27H5I2-30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27H5I2-30PC
PI5
28-Lead (600-Mil) Molded DIP
CY27H5I2-30WC
WI6
28-Lead (600-Mil) Windowed CerDIP
CY27H5I2-30ZC
Z2~
28-Lead Thin Small Outline Package
CY27H5I2-35HC
H65
32-Pin Windowed Leaded Chip Carrier
CY27H5I2-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27H5I2-35PC
PI5
28-Lead (600-Mil) Molded DIP
CY27H5I2-35WC
WI6
28-Lead (600-Mil) Windowed CerDIP
CY27H5I2-35ZC
Z28
28-Lead Thin Small Outline Package
CY27H5I2-35HMB
H65
32-Pin Windowed Leaded Chip Carrier
CY27H5I2-35LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27H5I2-35QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27H5I2-45HC
H65
32-Pin Windowed Leaded Chip Carrier
CY27H5I2-45JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27H5I2-45PC
PI5
28-Lead (600-Mil) Molded DIP
CY27H5I2-45WC
WI6
28-Lead (600-Mil) Windowed CerDIP
CY27fJ5I2-45ZC
Z28
28-Lead Thin Small Outline Package
CY27H5I2-45DMB
016
28-Lead (600-Mil) CerDIP
CY27H5I2-45HMB
H65
32-Pin Windowed Leaded Chip Carrier
CY27H5I2-45LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27H5I2-45QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27H5I2-45WMB
WI6
28-Lead (600-Mil) Windowed C~rDIP
CY27H5I2-55HC
H65
32-Pin Windowed Leaded Chip Carrier
CY27H5I2-55JC
J65
32-Lead Plastic Leaded Chip Carrier
CY27H5I2-55PC
PI5
28-Lead (600-Mil) Molded DIP
CY27H5I2- 55WC
WI6
28-Lead (600-Mil) Windowed CerDIP
CY27H5I2-55ZC
Z28
28-Lead Thin Small Outline Package
CY27H5I2-55DMB
016
28-Lead (600-Mil) CerDIP
CY27H5I2- 55HMB
H65
32-Pin Windowed Leaded Chip ~arrier
CY27H5I2-55LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY27H5I2-55QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY27H5I2-55WMB
WI6
28-Lead (600-Mil) Windowed CerDIP
Notes:
10. Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product availability.
.
4-74
Operating
Range
Commercial
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
CY7C~25A
512 X 8 Registered PROM
Features
• CMOS for optimum speed/power
• High speed
-18 ns address set-up
- 12 ns clock to output
• Lowpower
-495 mW (commercial)
-660 mW (military)
• Synchronous and asynchronous output enahles
• On-chip edge-triggered registers
• Buttered common PRESET and
CLEAR inputs
• EPROM technology, 100%
programmable
• Slim 300-mil, 24-pin plastic or hermetic DIP, 28-pin LCC, or 28-pin
PLCC
• SV :1::10% Vee, commercial and
military
• TTL-compatihle I/O
• Direct replacement for bipolar
PROMs
• Capable of withstanding greater than
2001V static discharge
Functional Description
The CY7C225Ais a high-performance 512
word by 8 bit electrically programmable
read only memory packaged in a slim
300-mil plastic or hermetic DIP, 28-pin
leadless chip carrier, and 28-pin PLCC.
Logic Block Diagram
Pin Configurations
Vee
A,
O.
ROW
ADDRESS
As
As
PROGRAMMABLE
ARRAY
I'S
0,
As
&-BIT
EDGE·
TRIGGERED
REGISTER
Ae
As
DIP
Top View
0,
AD
A,
The memory cells utilize proven EPROM
floating gate technology and byte-wide intelligent programming algorithms.
The CY7C22SA replaces bipolar devices
and offers the advantages oflower power,
superior performance, and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage and low
current requirements allow for gang programming. The EPROM cells allow for
each memory location to be tested 100%,
as each location is written into, erased,
and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC
performance to guarantee that after customer programming the product will meet
AC specification limits.
ADDRESS
DECODER
0,
0,
E
ern
Es
As
As
A,
CP
As
0,
0,
0,
A,
A,
0,
COLUMN
ADDRESS
0,
0,
0,
GND
0,
0,
As
C225A-2
LCC/PLCC
Top View
00
I'S
.:p.n~Jl~I~
em
CP
4 3 2L~ 282726
25
24
Ae
As
Ao
23
A,
ES
22
21
20
19
As
NC
00
C225A-1
E
10
11
12131415161718
E
=
lOs
CP
NC
0,
O.
o8~~Bo(f
C225A-3
Selection Guide
Minrroum Address Set-Up Time (ns)
Maximum Clock to Output (ns)
I Commercial
Maximum oserating
Current (rnA
I Military
7C225A-18
18
12
90
7C225A-25
25
12
90
120
4-76
7C225A-30
30
15
90
120
7C225A-35
35
20
120
7C225A-40
40
25
90
120
CY7C225A
.?cYPRESS
AC lest Loads and Wavefonns[4]
R12500
I _
R2
1670
INCLUDING
JIG AND SCOPE
-
I
5 PF
INCLUDING _
JIG AND SCOPE
(a) Normal Load
Equivalent to:
ALL INPUT PULSES
OUTP~~31
OUTPUT
5V31
50 pF
R12500
_
-
3.0V3:
R2
1670
C225A-4
GND
5,5n5
1~o;
i-
~
10%
....
5,5n5
C225A-5
(b) High Z Load
THEvENIN EQUIVALENT
1000
OUTPUT 0.0- -......""
...10---00 2.0V
Operating Modes
The CY7C225A incorporates a D-type, master-slave register on
chip, reducing the cost and size of pipelined microprogrammed
systems and applications where accessed PROM data is stored
temporarily in a register. Additional flexibility is provided with
6:chronous ~~SE~ asynchronous (E) output enables and
LEAR and
inputs.
Upon power-up, the synchronous enable (Es) flip-flop will be in
the set condition causing the outputs (00 - 07) to be in the OFF
or high-impedance state. Data is read by applying the memory location to the address inputs (Ao - Ag) and a logic LOW to the
enable (Es) input. The stored data is accessed and loaded into the
master flip-flops of the data register during the address set-up
time. At the next LOW-to-HIGH transition of the clock (CP),
data is transferred to the slave flip-flops, which drive the output
buffers, and the accessed data will appear at the outputs (00 07) provided the asynchronous enable (E) is also Law.
The outputs maLbe disabled at any time by switching the asynchronous enable (E) to a logic HIGH, and may be returned to the
active state by switching the enable to a logic Law.
Regardless of the condition of E, the outputs will go to the OFF
or high-impedance state upon the next positive clock edge after
the synchronous enable (Es) input is switched to a HIGH level. If
the synchronous enable pin is switched to a logic Law, the subsequent positive clock edge will return the output to the active state
ifE is Law. Following a positive clock edge, the address and syn-
chronous enable inputs are free to change since no change in the
output will occur until the next LOW-to-HIGH transition of the
clock. This unique feature allows the CY7C225A decoders and
sense amplifiers to access the next location while previously addressed data remains stable on the outputs.
System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers
available in the market.
The CY7C225A has buffered asynchronous CLEAR and PRESET inputs. Applying a LOW to the PRESET input causes an
immediate load of all ones into the master and slave flip-flops of
the register, independent of all other inputs, including the clock
(CP). Applying a LOW to the CLEAR input, resets the flip-flops
to all zeros. The initialize data will appear at the device outputs
after the outputs are enabled by bringing the asynchronous enable
(E)LOW.
When power is applied, the (internal) synchronous enable flipflop will be in a state such that the outputs will be in the high-impedance state. In order to enable the outputs, a clock must occur
and the Es input pin must be LOW at least a set-up time prior to
the clock LOW-to-HIGH transition. The E input may then be
used to enable the outputs.
4-78
CY7C225A
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Mode Selection
Pin Function[S]
Read or Output Disable
Mode
Other
Read
Output Disable
Output Disable
Clear
Preset
Program
Program Verify
Program Inhibit
Intelligent Program
Blank Check
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
CP
Es
CLR
E
PS
PGM
VFY
Vpp
E
PS
D,- Do
X
VIL
VIH
VIL
VIH
07 - 00
X
VIH
VIH
X
VIH
HighZ
X
X
VIH
VIH
VIH
HighZ
Zeros
X
VIL
VIL
VIL
VIH
X
VIL
VIH
VIL
VIL
Ones
VILP
VIHP
Vpp
VIHP
VIHP
D7- D O
VIHP
VILP
Vpp
VIHP
VIHP
07- 00
VIHP
VIHP
Vpp
VIHP
VUIP
HighZ
VILP
VIHP
Vpp
VIHP
VUIP
D7- D O
VIHP
VILP
Vpp
VIHP
VIHP
Zeros
Note:
8. X = "don't care" but not to exceed Vee ±S%.
DIP
ThpView
A,
A"
LCC/PLCC
ThpView
~
Ao
vpp
~
A,
W"I
l'GM
0,
Ao
~~.tl1Jl~~
Vee
A"
l'S
E
Ao
4 3 2l~ 28272~
~
~
A,
Ao
NC
Do
D.
0,
GND
07- 00
24
23
22
21
20
10
19
11
12131415161718
,... Ne 0
(I)
E
Vpp
'IF'!
l'GI.l
NC
0,
0,
'It to
cCzzccc
0,
0,
0,
(!)
C225A-7
Figure 1. Programming Pinouts
4-80
C225A-8
CY7C22SA
.i!2YPRESS
Ordering Information[9]
Speed
Ordering
Code
Package
1Ype
Package
'JYpe
Operating
Range
CY7C225A -18DC
CY7C225A -l8JC
CY7C225A -18PC
CY7C225A-25DC
CY7C225A-25JC
CY7C225A-25PC
CY7C225A-25DMB
CY7C225A-25LMB
CY7C225A - 30DC
014
J64
P13
D14
J64
P13
014
L64
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (3OO-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
Commercial
D14
J64
P13
014
L64
014
L64
014
J64
P13
014
24-Lead (3OO-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
L64
28-Square Leadl.ess Chip Carrier
(~s)
tSA
teo
18
12
25
12
30
15
35
20
40
25
CY7C225A-30JC
CY7C225A - 30PC
CY7C225A-30DMB
CY7C225A-30LMB
CY7C225A-35DMB
CY7C225A-35LMB
CY7C225A -40DC
CY7C225A-40JC
CY7C225A-40PC
CY7C225A-40DMB
CY7C225A-40LMB
24-Lead (3OO-Mil) Molded DIP
24-Lead (3OO-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (3OO-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
Commercial
Military
Commercial
Military
Military
Commercial
Military
Note:
9. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product avail-
ability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameter
YaH
VOL
VIH
VIL
Ilx
Ioz
Icc
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Document #: 38-00228-C
4-82
Parameter
Subgroups
tSA
tHA
7, 8,9, 10, 11
7,8, 9, 10, 11
tco
tDP
tii,p
7,8, 9, 10, 11
7, 8,9, 10, 11
7, 8, 9, 10, 11
.~YPRESS
CY7C235A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature .................. -65 ° C to + 150° C
Ambient Temperature with
Power Applied ....................... -55°C to +l25°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12for DIP) ................ -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20 for DIP) ......... 13.0V
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Thmperature
Range
Commercial
Industrial[l]
O°Cto +70°C
Vee
5V ±1O%
-40°C to +85°C
5V ±1O%
Military[2]
-55°Cto +125°C
5V ±1O%
Electrical Characteristics Over Operating Rangd3]
Parameter
Description
Thst Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = -4.0 rnA
VIN = VIH or VIL
VOL
Output LOW Voltage
Vee = Min., IOL = 16 rnA
VIN = VIH or VIL
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for
All Inputs[4]
VIL
Input LOW Level
Guaranteed InputLogicalLOWVoltagefor All
Inputs[4]
Max.
Unit
2.4
V
0.4
V
2.0
-10
V
0.8
V
+10
ItA
Ilx
Input Leakage Current
GND.sVIN.sVee
VeD
Input Clamp Diode Voltage
Note 5
loz
Output Leakage Current
GND .s VOUT .s Vee Output Disabled[4]
-10
+10
ItA
los
Output Short Circuit Current
Vee = Max., VOUT = 0.OV[6]
-20
-90
rnA
Icc
Power Supply Current
lOUT = ornA,
Vee = Max.
90
rnA
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming Voltage
VILP
Input LOW Programming Voltage
ICommercial
IMilitary
120
12
13
V
50
rnA
0.4
V
3.0
V
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Thst Conditions
TA = 25°C, f = 1 MHz, Vee =5.0V
Max.
Unit
10
pF
10
pF
Notes:
1.
2.
3.
Contact a Cypress representative for industrial temperature range
specifications.
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
4.
5.
6.
4-84
For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
See Introduction to CMOS PROMs in this Data Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
~YPRESS
CY7C235A
Switching Characteristics Over Operating Rangd3,5]
Description
Parameter
7C235A-25
7C235A-30
7C235A-40
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
tSA
Address Set·Up to Clock HIGH
18
25
30
40
tHA
Address Hold from Clock HIGH
0
0
0
0
teo
Clock HIGH to Valid Output
tpwe
Clock Pulse Width
12
12
15
20
ns
tSES
Es Set-Up to Clock HIGH
10
10
10
15
ns
5
5
5
5
12
12
15
ns
ns
ns
20
tHES
Es Hold from Clock HIGH
tm
Delay from INIT to Valid Output
tRI
INIT Recovery to Clock HIGH
15
20
20
20
tpWI
INIT Pulse Width
15
20
20
25
teos
Inactive to Valid Output from Clock HIGH[7]
15
20
20
25
ns
tHZC
Inactive Output from Clock HIGH(7]
15
20
20
25
ns
tDOE
Valid Output from E LOW
15
20
20
25
ns
Inactive Output from E HIGH
15
20
20
25
ns
tHZE
Note:
7.
7C235A-18
Min.
25
20
25
ns
35
ns
ns
ns
Applies only when the synchronous (Es) function is used.
Switching Waveforms[5]
CP
00 - 0 7
--+-----'l'-+---'U..I)
lODE
E __________-+__~------------------------------JI
C235A-6
4-86
£2;a.
CY7C235A
.""5!!!!Ir;" CYPRESS
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
SUPPLY VOLTAGE
VS.
~
01.4
.2
/
c
w
N 1.2
:J
:RJf
""
Po,.
O.
Au
Ao
=,
A,
Ao
CS,
C243-1
NC
o.
4 3 2L~ 282726
25
24
23
22
2'
20
10
19
11
12131415161718
cr8~~0'~0'
A10
=,
Al1
CS,
NC
07
o.
C243-3
Selection Guide
Maximum Access Time (ns)
I Commercial
Maximum 03erating
Current(mA
I Military
7C243-20
7C244-20
20
100
7C243-25
7C244-25
25
100
120
4-90
7C243-35
7C244-35
35
80
100
7C243-45
7C244-45
45
80
100
7C243-55
7C244-55
55
80
100
CY7C243
CY7C244
AC Test Loads and Waveforms[4J
Test Load for - 20 through - 25 speeds
Rt500Q
Rt500
5V 3 1 ( 6 5 8MIL)
Q
ALL INPUT PULSES
5V 3 l ( 6 5 8MIL)
Q
OUTPUT
3'OV~
OUTPUT
30
pF I
INCLUDING _
JIG AND SCOPE
R2 333Q
(403Q MIL)
_
-
5
pF I
INCLUDING _
JIG AND .,..
SCOPE
J?:::
tO~%
GND
R2 333Q
(403Q MIL)
.$.5ns--
to%
\.-
--
_
-
.$.5ns
C243-5
C243-4
(b) High Z Load
(a) Normal Load
Equivalent to:
THEvENIN EQUIVALENT
RTH 200Q (250Q MIL)
OUTPUT ~ 2.0V (t.9VMIL)
Test Load for - 35 through - 55 speeds
Rt 250Q
Rt 250Q
5V~
OUTPUT
30
pF I
INCLUDING
JIG AND
SCOPE
_
-
OUTPUT.
5V31
R2t67Q
5
_
-
(c) Normal Load
Equivalent to:
PFI
INCLUDING _
JIG AND SCOPE
R2t67Q
_
C243-6
(d) High Z Load
THEVENIN EQUIVALENT
OUTPUT
~
2.0V
Switching Characteristics Over the Operating Rangd2. 3. 4J
7C243-20
7C244-20
Parameter
Description
Min.
Max.
7C243-25
7C244-25
Min.
Max.
Min.
Max.
7C243-55
7C244-55
Max.
Unit
Address to Output Valid
20
25
35
45
55
ns
tHZCS
(Com'l)
Chip Select Inactive to High Z
12
12
20
25
25
ns
tHZCS
(Mil)
Chip Select Inactive to High Z
15
20
25
25
ns
tACS
(Com'l)
Chip SelectActive to Output Valid
12
20
25
25
ns
tACS
(Mil)
Chip Select Active to Output Valid
15
20
25
25
ns
4-92
Min.
7C243-45
7C244-45
tAA
12
Max.
7C243-35
7C244-35
Min.
CY7C243
CY7C244
1Ypical DC and AC Characteristics
NORMALIZED ACCESS TIME
vo. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
VO. AMBIENT TEMPERATURE
NORMAUZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
1.2
w
::e
.13 1.4
.13
C
w
N 1.2
~
::J
<
::e
a:
0
1.0
z
0.8
./
/
V
0.8.L:------,!::-------:-!
-55
25
125
AMBIENT TEMPERATURE (0C)
6.0
5.5
NORMALIZED ACCESS TIME
vs. TEMPERATURE
w
~ 60
1.6
1.2
1
1.0
!z
50
::l
40
~
1.4
ffi
~
z
~
L-----
~ 0.8
0.6
- 55
25
125
o
~
OUTPUT SOURCE CURRENT
vO.VOLTAGE
""I'-...
""" r--..
o
1.0
""
2.0
~
Z
iii
75
!3
50
g;
o 25 V
o
0.0
/
25
~
20
f!i
15
c
10
i:d
5
M
'"
V
/
/'
V
o0
/
200
400
..---
1.00
.13
/'
/
J
1.0
~
Vee = 5.0V
TA = 25°C
I
2.0
'\.
C
ii;I 0.90
/
3.0
OUTPUT VOLTAGE
,
\
0.95
0.85
a:
~ 0.80
0.75
0.70
4.0
o
M
25
I
Vee = 5.5V
TA = 25°C
-50
r--
75
CYCLE PERIOD (ns)
4-94
Vee = 4.5V
TA = 25°C I
I
600 800 1000
CAPACITANCE (pF)
1.05
100
6.0
M
V
NORMALIZED SUPPLY CURRENT
vs. CYCLE PERIOD
~ 175
a
~
4.0
3.0
OUTPUT VOLTAGE
.§. 150
125
5.5
TYPICAL ACCESS TIME CHANGE
vo. OUTPUT LOADING
~
OUTPUT SINK CURRENT
vo.OUTPUTVOLTAGE
a:
5.0
30
AMBIENT TEMPERATURE (OC)
!z
I:!!
4.5
35
30
g 20
!3 10
5
o 0
TA = ~5°C
0.4
4.0
SUPPLY VOLTAGE
.§.
::e
rJ)
'"" 0.6
gs
I
5.0
- --
r-- I--.
~
z
'MAX
4.5
1.0
S0.8
~
SUPPLY VOLTAGE (V)
i=
rJ)
c
gs
TA =25°C
,=
V
0.6
4.0
V
i=
1.1 j---C~-+-----I
100
CY7C243
CY7C244
Ordering Information (continued)[7]
Speed
(ns)
20
25
35
45
55
Ordering Code
CY7C244-20PC
CY7C244 20WC
CY7C244 25PC
CY7C244 25WC
CY7C244 25DMB
CY7C244-25WMB
CY7C244-35PC
CY7C244-35WC
CY7C244-35DMB
CY7C244-35WMB
CY7C244-45PC
CY7C244-45WC
CY7C244-45DMB
CY7C244 45WMB
CY7C244 55PC
CY7C244 55WC
CY7C244 55DMB
CY7C244 55WMB
Package
Name
PH
W12
P11
W12
D12
W12
P11
W12
D12
W12
P11
W12
D12
W12
P11
W12
D12
W12
Package'lYPe
24-Lead (600-Mil) Molded DIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) Molded DIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) Molded DIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) Molded DIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (60P-Mil) Molded DIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Windowed CerDIP
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIH
VIL
IIX
Ioz
Icc
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameter
Subgroups
tAA
7, 8, 9, 10, 11
7,8, 9, 10, 11
tACS
Document #: 38-00360-A
4-96
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
CY7C245A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
storage Thmperature .................. -6SoC to + lS0°C
Ambient Thmperature with
Power Applied ....................... -SSoC to + 12SoC
Supply Volt~ge to Ground Potential
(P~ 24 !o P:n 12) .................... : .. -O.SV to HOV
DC Voltage Applied to Outputs
in High Z State: ........................ -O.SV to + 7.0V
DC Input Voltage ....................... -3.0V to +7.0V
DC ProgramVoltage (Pins 7, 18,20) ................ 13.0V
UV Erasure ............................. 72S8 Wseclcrn2
Static Discharge Voltage ........................ >2001 V
(per MIJ.:'SID-883, Method 301S)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Range
Commercial
IndustrialP]
-40°C to +8SoC
SV ±1O%
Military[2]
-SsoC to + 12SoC
SV±10%
Vee
SV ±10%
O°C to +70°C
Electrical Characteristics Over the Operating Rangel3, 4]
Parameter
Description
Output HIGH
VOH
Voltage
Output LOW
VOL
Voltage
Input HIGH
VIR
Level
Input LOW Level
VIL
Input Leakage
Current
Input Clamp
Diode Voltage
Output Leakage
Current
Output Short
Circuit Current
Power Supply
Current
IIX
VeD
Ioz
los
Icc
Vpp
Ipp
VIRP
VILP
7C245A-15
Test Conditions
Min. Max.
Vee - Min., IOH - -4.0 rnA 2.4
VIN = VIR or VIL
0.4
Vee - Min., IOL -16 rnA
VIN = VIR or VIL
2.0 Vee
Guaranteed Input Logical
HIGH VoltageJor All Inputs
Guaranteed Input Logical
0.8
LOW Voltage for All Inputs
10 +10
GND~ VIN~ Vee
7C245A-18
Min. Max.
2.4
7C245A-25 7C245AL-25
7C245A-35 7C245AL-35
7C245A-45 7C245AL-45
Min. Max. Min. Max. Unit
.2.4
V
2.4
0.4
2.0
Vee
0.4
2.0
0.8
10
Vee
2.0
0.8
0.4
V
Vee
V
0.8
V
+10
10
+10
10
+10
!lA
Note 4
GND$.Vo~V8f
Output Disabled
Vee - Max.,
VOUT =0.OV[6]
ICom'l
Vee - Max.,
IOuT=OmA
IMii
10
+10
-10
+10
10
+10
10
+10
!lA
-20
-90
-20
-90
-20
-90
-20
-90
rnA
rnA
12
90
120
13
60
12
120
120
13
13
V
50
rnA
120
Programming
Supply Voltage
I Programming
Supply Current
Input HIGH
Programming
Voltage
Input LOW
Programming
Voltage
12
13
SO
3.0
SO
3.0
0.4
SO
3.0
0.4
12
3.0
0.4
V
0.4
V
Capacitance[4]
Parameter
CIN
COUT
-
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
TA = 2SoC, f = 1 MHz,
10
Vee = S.OV
10
Notes:
1. Contact a Cypress representative for industrial temperature range
. specifications.
.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Oro,:!!, A subgroup testing in·
formatjon.
4.
5.
6.
4-98
Unit
pF
pF
See the "Introduction to CMOS PROMs" section of the Cypress Data
Book for general information on testing.
For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
~YPRESS
CY7C245A
Operating Modes (continued)
sense amplifiers to access the next location while previously addressed data remains stable on the outputs.
System timing is simplified in that the on-chip edge triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers
available in the market.
The CY7C245A has an asynchronous initialize input (INIT). The
initialize function is useful during power-up and time-out sequences and can facilitate implementation of other sophisticated
functions such as a built-in "jump start" address. When activated,
the initialize control input causes the contents of a user-pro-
grammed 2049th 8-bit word to be loaded into the on-chip register.
Each bit is programmable and the initialize function can be used
to load any desired combination of 1s and Os into the register. In
the unprogrammed state, activating INIT will generate a register
CLEAR (all outputs LOW). If all the bits of the initialize word
are programmed, activating !NIT performs a register PRESET
(all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load of
the programmed initialize word into the master and slave flipflops of the register, independent of all other inputs, including the
clock (CP). The initialize data will appear at the device outputs
after the outputs are enabled by bringing the asynchronous enable
(E) LOW.
Switching Waveforms[4]
-+__
~-A,O ________________________
~~~
____
~--~~~~ao~-----------
CP
C245A-6
Erasure Characteristics
Wavelengths of light less than 4000 A begin to erase the 7C245A.
For this reason, an opaque label should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for
extended periods of time.
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Afor a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm 2. For an ultraviolet lamp
with a 12 mW/cm2 power rating the exposure time would be approximately 35 minutes. The 7C245A needs to be within 1 inch of
the lamp during erasure. Permanent damage may result if the
PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum
dosage.
this section. Programming algorithms can be obtained from any
Cypress representative.
BitMap Data
Programmer Address
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
RAM Data
Decimal
Hex
Contents
0
0
Data
2047
7FF
2048
800
Data
Init Byte
2049
801
Control Byte
Control Byte
4-100
00 Asynchronous output enable (default state)
01 Synchronous output enable
CY7C245A
.;rcYPRESS
1Ypical DC and AC Characteristics
NORMAUZEDSUPPLYCURRENT
vs. AMBIENT TEMPERATURE
NORMAUZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
vs. Vee
i= 1.6
12
1.6
CWCK TO OUTPUT TIME
!:li!
!3
" 1.4
c
UJ
N
ia:
0
1.2
1.0
~~
~ 1.0
()
~
4.5
5.0
SUPPLY VOLTAGE
5.5
AMBIENT TEMPERATURE ('C)
M
UJ
CLOCK TO OUTPUT TIME
:;
vs. TEMPERATURE
i= 1.6
~
~
~
UJ
:;
i= 1.0
a..
O.B
a: 0.6
~
-----
"""
N
:::;
«
:; 0.6
a:
0
0.4
4.0
125
\
" 0.9B
til
TA=25'C
0.96
!5 0.92
z
0.90
0.86
25.0
:!
;:!;
"r--
~ 0.94
:;
o
25
50
75
CLOCK PERIOD (ns)
)~
m
c 10.0
5.0
100
~
:;
1.0
0
5.5
z O.B
/
/
200
M
/
400
600
BOO 1000
125
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~ 175
-150
!z
ll!
a:
i3
100
75
!3
50
o
25
5
~
125
z
1i5
TA = 25'C _
Vee = 4.5V
I~
j
25
AMBIENT TEMPERATURE ('C)
~
CAPACITANCE (pF)
~
0.6
-55
6.0
-
/
15.0
6.0
M
~
UJ
N
I
5.0
l20.0
5.5
1.4
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING
_
5.0
SUPPLY VOLTAGE
a:
30.0
i\.
.9
N
!Vee =5.5V!
I
4.5
4.0
c 1.2
........
TA= 25'C
4.5
TA = 25'C
I:ti
en
i'-...
SUPPLY VOLTAGE
NORMAUZED SUPPLY CURRENT
vs. CWCK PERIOD
1.00
oz
a..
UJ
en
cw O.B
AMBIENT TEMPERATURE ('C)
1.02
~
a: 0.6
:::l
z
25
- 55
c
~ O.B
NORMALIZED SET·UP TIME
vs. TEMPERATURE
I'--.. ...........
f.!.
~
r-- I--
1.6
:::l
9
() 1.0
1.2
NORMAUZED SET·UP TIME
vs. SUPPLY VOLTAGE
1.2
1.4
~ 1.2
~
f----t-----~
°:!l5·'=5-----;2~5-----~125
6.0
1.4
9 1.0
()
0.9
I
0.6
4.0
~
c
a:
TA = 25'C
f=fMAX
/
1.1 p o , ; : - - - - j - - - - - - ;
~
/
/
z
O.B
Jl
/
.9
o/
0.0
/
J
/
/
Vee = 5.0V
TA= 25'C -
I
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
C245A-9
4-102
-:~YPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
Vm
VIL
IIx
Ioz
Icc
Switching Characteristics
Parameter
tSA
tHA
tco
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
CY7C245A
SMD Cross Reference
·SMD
Number
Suff'1X
Cypress
Number
5962-88735
01KX
CY7C245A-45KMB
5962-88735
01LX
.CY7C245A -450MB
5962-88735
013X
CY7C245A -45LMB
5962-88735
02KX
CY7C245A-35KMB
5962-88735
02LX
CY7C245A - 350MB
5962-88735
023X
CY7C245A - 35LMB
5962-887~5
03KX
CY7C245A - 35KMB
5962-88735
03LX
CY7C245A-35DMB
5962-88735
033X
CY7C245A - 25LMB
5962-88735
04KX
CY7C245A-25KMB
5962-88735
04LX
CY7C245A-25DMB
5962-88735
043X
CY7C245A-25LMB
5962-87529
01KX
CY7C245A -451MB
5962-87529
01LX
CY7C245A-45WMB
5962-875~9
013X
CY7C245A-45QMB
5962-87529
02KX
CY7C245A-351MB
5962-87529
02LX
CY7C245A-35WMB
5962-87529
023X
CY7C245A - 35QMB
5962-89815
01LX
CY7C245A-35WMB
5962-89815
01KX
CY7C245A - 35TMB
5962-89815
013X
CY7C245A-35QMB
5962-89815
02LX
CY7C245A -25WMB
5962-89815
02KX
CY7C245A-25TMB
5962-89815
023X
CY7C245A - 25QMB
5962-89815
03LX
CY7C245A-18WMB
5962-89815
03KX
CY7C245A -18TMB
5962-89815
033X
CY7C24~A -18QMB
Document #: 38-00074-0
4-104
CY7C251
CY7C254
~YPRESS
Maximum Ratings
(Above which the useful life may be impaired. For userguidelines,
not tested.)
Storage Temperature .................. -65°C to +150°C
Ambient Thmperature with
Power Applied ....................... -55°C to +125°C
Supply Volt~ge to Ground Potential
(Pin 28 to Pin 14) ....................... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .........•............... -O.5V to +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
DC Program Voltage (Pin 22) ...................... 13.5V
Electrical Characteristics
Static DisCharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 mA
UV Exposure .........................•. 7258 Wsec/cm2
Operating Range
Ambient
lemperature
Ra!Jge
Commercial
Industrial[!]
O°Cto +70°C
Vee
5V:tl0%
-40°C to +85°C
5V:t10%
Military[2]
-55°Cto +125°C
5V:t10%
Over the Operating Ranger3, 4]
7C251-45, 55, 65
7C254-45, 55, 65
Parameter
Description
lest Conditions
Min.
Unit
Max.
VOH
Output HIGH Voltage
Vee = Min., IOH = -4.0 mA
VOL
Output LOW Voltage
Vee = Min., IOL = 16.0 mA
VIH
Input HIGH Level
Guaranteed Input Logical HIGH
Voltage for All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW
Voltage for All Inputs
Ilx
Input Current
GND!'>. VIN!'>. Vee
VCD
Input Diode Clamp Voltage
loz
Output Leakage Current
GND!'>. VOUT ~ Vee, Output Disabled
-40
+40
J.tA.
los
Output Short Circuit Currentf5]
Vee = Max., VOUT = GND
-20
-90
rnA
lee
Power Supply Current
Vee = Max., lOUT = 0 mA
Com'l
100
mA
Mil
120
Com'l
30
Mil
35
ISB
Standb) Supply Current
(7C251
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
2.4
V
0.5
V
2.0
V
-10
0.8
V
+10
J.tA.
Note 4
~e=Max.,
C
1
= VIH, lOUT = 0 mA
12
mA
13
V
50
mA
3.0
V
0.4
V
Capacitance[4]
Parameter
CIN
l.{)UT
Description
Input Capacitance
uutput capacitance
lest Conditions
TA - 25°C, f - 1 MHz,
Vee =5.0V
Noles:
L Contact a Cypress representative regarding industrial temperature
range specification.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
S.
4-106
Max.
10
10
Unit
pF.
pF
See the "Introduction to CMOS PROMs" section of the Cypress Data
Book for general information on testing.
For test purposes, not more thari one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
CY7C251
CY7C254
~YPRESS
Erasure Characteristics
Blankcheck
Wavelengths oflight less than 4000 A begin to erase the 7C251 and
7C254 in the windowed package. For this reason, an opaque label
should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time.
Blankcheck is accomplished by performing a verify cycle (VFY
toggles on each address), sequencing through all memory address
locations, where all the data read will be zeros.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 A for a minimum dose (UV intensity x exposure
time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 m W/cm2
power rating, the exposure time would be approximately 35 minutes. The 7C251 or 7C254 needs to be within 1 inch of the lamp
during erasure. Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended period of time.
7258 Wsec/cm2 is the recommended maximum dosage.
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of this
section. Programming algorithms can be obtained from any
Cypress representative.
Programming Information
Table 1. Mode Selection
Pin Function[8]
Read or Output Disable
Mode
Other
Read
Output Disable
Output Disable
Output Disable
Output Disable
Program
Program Verify
Program Inhibit
Blank Check
Ao
An - Ao
A13 - Ao
A13 - Ao
A13 - Ao
A13 - Ao
-A13 - Ao
A13 - Ao
A13 - Ao
A13 - Ao
A13 -Ao
A13 -
CS3
CS2
CSt
NA
VFY
Vpp
PGM
D, - Do
VIL
Vrn
VIL
VIL
07 - 00
X
X
X
Vrn
HighZ
X
X
Vrn
X
HighZ
X
VIL
X
X
HighZ
Vrn
X
X
X
HighZ
X
Vrnp
Vpp
VILP
D7 - Do
07 - 00
X
VILP
VPP
VUIP
X
Vrnp
VPP
Vrnp
HighZ
X
VILP
VPP
VUIP
07 - 00
Note:
8. X; "don't care" but not to exceed Vee ±S%.
DlP/Flatpack
LCe
Top View
Top View
~:;::~~f
Vee
AlO
Al1
A12
4 3 2L~32313~
5
6
7
8
9
10
28
27
26
25
24
23
11
7C254
22
12
21
13
14151617181920
A,.
!'mil
Vpp
VFY
A,
NA
Ao
D7
D6
Do
D,
D,
D2
GND
D.
D.
0, - 00
CS4
A12
A,.
7C251
!'mil
0
Vpp
VFY
NA
NC
D7
D6
(\100 C")O..,.IO
oz~ozao
C25'-7
Figure 1. Programming Pinout
4-108
C251-8
CY7C25 1
CY7C254
~YPRESS
Ordering Information[9]
Speed
(ns)
45
55
65
Speed
(ns)
45
55
65
Ordering Code
CY7C251-45PC
CY7C251-45WC
CY7C251-45DMB.
CY7C251-45WMB
CY7C251- 55PC
CY7C251-55WC
CY7C251-55DMB
CY7C251- 55LMB
CY7C251-55QMB
Package
Name
P21
W22
D22
W22
P21
W22
D22
L55
Q55
CY7C251- 55WMB
CY7C251-65PC
CY7C251-65WC
CY7C251-65DMB
CY7C251-65LMB
CY7C251- 65QMB
W22
P21
W22
D22
CY7C251-65WMB
W22
Ordering Code
CY7C254-45PC
CY7C254-45WC
CY7C254-45DMB
CY7C254-45WMB
CY7C254-55PC
CY7C254-55WC
CY7C254-55DMB
CY7C254-55QMB
CY7C254-55WMB
L55
Q55
Package
Name
P15
W16
D16
W16
P15
W16
016
Q55
W16
CY7C254-65PC
CY7C254-65WC
P15
W16
CY7C254-65DMB
CY7C254-65QMB
CY7C254-65WMB
016
Q55
W16
Package 'fYpe
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
Military
Commercial
Military
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
Commercial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Windowed CerDIP
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
Package 1)pe
28-Lead (600-MiI) Molded DIP
28-Lead (600-Mil) Wmdowed CerDIP
Operating
Range
Commercial
28-Lead (600-Mil) CerDIP
28-Lead (600-Mil) Windowed CerDIP
Military
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) CerDIP
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) CerDIP
Commercial
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (600-Mil) Windowed CerDIP
Note:
9.
Operating
Range
Commercial
Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
4-110
Military
Commercial
Military
CY7C261
CY7C263/CY7C264
8K X 8 Power-Switched and
Reprogrammable PROM
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
- 20 ns (commercial)
- 25 ns (military)
• Lowpower
- 660 mW (commercial)
-770 mW (military)
• Super low standby power (7C261)
- Less than 220 mW when deselected
- Fast access: 20 ns
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil
packaging available
• 5V ± 10% Vee, commercial and
military
• Capable of withstanding greater than
2001V static discharge
• TTL-compatible I/O
• Direct replacement for bipolar
PROMs
Functional Description
The CY7C261, CY7C263, and CY7C264
are high-performance Si92-word by S-bit
CMOS PROMs. When deselected, the
7C261 automatically powers down into a
low-power standby mode. It is packaged
in a 3OO-mil-wide package. The 7C263
and 7C264 are packaged in 300-mil-wide
and 600-mil-wide packages respectively,
and do not power down when deselected.
The reprogrammable packages are
equipped with an erasure window; when
exposed to UV light, these PROMs are
erased and can then be reprogrammed.
The memory cells utilize proven EPROM
Logic Block Diagram
Pin Configurations
ft2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Thmperature
Range
Commercial
Industrial[l]
O°C to +70°C
Vee
5V±1O%
-40°C to +85°C
5V ±1O%
Military[2]
-55°C to + 125°C
5V ±10%
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
Electrical Characteristics Over the Operating Rangef3]
7C265-15,
25
Parameter
VOR
Description
Output HIGH Voltage
VOL
Output LOW Voltage
Thst Conditions
Vee = Min., lOR = -2.0 rnA
Vee = Min., lOR = -4.0 rnA
Vee - Min., 10L - 8.0 rnA Com']
Vee = Min., 10L = 12.0 rnA
Vee - Min., 10L - 6.0 rnA Mil
Vee = Min., 10L = 8.0 rnA
Vrn
VIL
IIX
loz
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
losl4J
Icc
Output Short Circuit Current Vee
Vee Operating Supply
Vee
Current
Vpp
Ipp
Programming Supply Voltage
ProgrammingSupplyCurrent
Min.
2.4
Max.
= Max., VOUT = GND
= Max., lOUT = 0 rnA
2.4
Unit
V
2.4
V
0.4
0.4
0.4
0.4
-10
-40
Com'l
Mil
12
4-122
7C265-50
0.4
2.0
2.0
GND < VIN < Vee
GND S VOUT s Vee,
Output Disabled
7C265-40
Min. Max. Min. Max.
0.8
+10
+40
90
120
140
13
50
-10
-40
2.0
0.8
+10
+40
-10
-40
90
100
12
13
50
12
0.8
+10
+40
90
80
120
13
50
V
V
!JA
!JA
rnA
rnA
V
rnA
~YPRESS
CY7C265
Switching Characteristics Over the Operating Rangd3, 5]
7C265-15
Parameter
Description
Min.
Max.
7C265-25
Min.
Max.
7C265-40
Min.
Max.
7C265-50
Min.
Max.
Unit
tAS
Address Set-Up to Clock
15
25
40
50
tHA
Address Hold from Clock
0
0
0
0
teo
Clock to Output Valid
tpwe
Clock Pulse Width
12
15
15
20
ns
tSES
Es Set-Up to Clock
(Sync. Enable Only)
12
15
15
15
ns
tlIES
Es Hold from Clock
5
tor
INIT to Output Valid
tRI
INIT Recovery to Clock
12
15
20
25
ns
tpW!
INIT Pulse Width
12
15
25
35
ns
teos
Output Valid from Clock
(Sync. Mode)
12
15
20
25
ns
tHze
Output Inactive from Clock
(Sync. Mode)
12
15
20
25
ns
tDOE
Output Valid from E LOW
(Async. Mode)
12
15
20
25
ns
tHZE
Output Inactive from E HIGH
(Async. Mode)
12
15
20
25
ns
12
15
5
15
5
ns
25
20
5
25
18
ns
ns
ns
35
ns
Switching Waveform
ADDRESS
--------'
SYNCHRONOUS
ENABLE
(PROGRAMMABLE) - - CLOCK
OUTPUT
tOOE
ASYNCHRONOUS INIT
(PROGRAMMABLE)
ASYNCHRONOUS
ENABLE _ _ _ _ _ _J
C265-7
4-124
CY7C265
tz;:rcYPRESS
DIP/Flatpack
LCC/PLCC (Opaque Only)
~:UJi:~~~
432 111 282726
--
25
24
23
22
21
20
A,
I'llM
10
CLK
A,
"'2'3'4'5'6'7,J9
A10
A11
A12
Vpp
NA
'iJF'I
0,
A"
Do
0,
0,
GND
C265-9
C265-8
Figure 1. Programming Pinout
ming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Programming Information
Programming support is available from Cypress as well as from II
number of third-party software vendors. For detailed program-
1:ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NO~ZEDSUPPLYCURRENT
VS.
SUPPLY VOLTAGE
1.6
1.2
Jll.4
./
0
w 1.2
~
::;;
Icc
0
/'
cr: 1.0
z
O.s
/'
1
1•OI----:::..,c-=----I
o
z 0.91-----/------i
/'
0.6
4.0
Jl 1.1~---+------i
TA = 25°C
f= MAX.
4.5
5.0
SUPPLY VOLTAGE
O.s.'=-----:'=------:-!
-55
25
125
6.0
5.5
M
:;
1= 1.4
rn
rn
./
,,/'
w
N 1.0
~
::;;
cr: O.s
0
z
V
0.6
-55
g
20
!3
10
§
""-
30
o
30
!l:!
125
z
ii5
!3
~
~
o
125
AMBIENT TEMPERATURE (0C)
100
/"
75
50
25
o/
0.0
/
u;-
.s
...-
3.0
OUTPUT VOLTAGE
4-126
0
10
~w
Vee = 5.0V
TA = 25°C
2.0
M
2.0
3.0
"
4.0
M
/
../
15
5
4.0
/
25
20
8
/
1.0
1.0
~
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING
150
13
"- i'...
OUTPUT VOLTAGE
~
a:
'~
"
0.0
~175
l<:
./
25
40
35
!z
w
~
50
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
1.6
U
U 1.2
2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
UV Exposure ........................... 7258 Wsec/cm2
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -6S 0 Cto +IS0°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Volt~ge to Ground Potential
(Pm 28 to Pin 14) ....................... -O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.SV to + 7.0V
DC Input Voltage ....................... -3.0V to +7.0V
DC Program Voltage ............................. 13.0V
Operating Range
Ambient
Temperature
Range
Commercial
Industrial[lJ
O°Cto +70°C
Vee
SV ± 10%
-40°C to +8S o C
SV ± 10%
Military[2J
-55°C to + 125°C
SV ± 10%
Electrical Characteristics Over the Operating Rangd3, 4J
7C266-20
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
Vee-Min.,
IOH = -2.0 rnA
Vee
Vee
Com'l
= Min., IOL = 8.0 rnA
= Min., IOL = 6.0 rnA
Input HIGH Voltage
VIL
Input LOW Voltage
IJX
Input Current
VeD
Input Diode
Clamp Voltage
loz
Output Leakage Current
VOL.$. VOUT.$. VOH,
Output Disabled
los
Output Short
Circuit Currentl5J
Vee
lee
Power Supply Current
Vee = Max., VIN
lOUT = ornA
Standby Supply Current
7C266-25
Max.
2.4
Min.
Unit
V
2.4
Com'l
0.4
0.4
V
0.4
Mil
2.0
2.0
0.8
-10
GND.$. VIN.$. Vee
Max.
2.4
Mil
VIH
ISB
Min.
+10
-10
V
0.8
V
+10
!lA
Note 4
= Max., VOUT = GND
= 2.0V;
+40
-40
+40
!lA
-20
-90
-20
-90
rnA
120
rnA
120
Mil
Chip Enable Inactive,
= 0 rnA
CE ~ VIH, lOUT
Notes:
1. Contact a Cypress representative regarding industrial temperature
range specification.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
Com'l
-40
4.
5.
4-130
Com'l
Mil
140
15
15
rnA
15
See the "Introduction to CMOS PROMs" section ofthe Cypress Data
Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
~YPRESS
CY7C266
AC Test Loads and Waveforms
Test Load for - 20 through - 25 speeds
R1 500
R1 500'-1
OUTP~~31(658'-1
MIL)
I
30 pF
INCLUDING _
JIG AND SCOPE
OUTP~~31(658'-1
MIL)
R2 333'-1
(403'-1 MIL)
_
-
I
5 pF
INCLUDING _
JIG AND SCOPE
(a) Nonnal Load
3'OV~
10~%
GND
R2 333'-1
(403'-1 MIL)
.$.5n5
.
~
10%
I-
-
_
-
.$.5n5
C266-5
(b) High Z Load
C266-4
I
Equivalent to:
THEVENIN EQUIVALENT
RTH200'-l
OUTPUT ~ 2500 MIL
Thst Load for - 35 through - 55 speeds
R1 250'-1
R1 2500
OUTP~~31
30
PFI
INCLUDING _
JIG AND SCOPE
OUTP~~31
R2167Q
5
_
-
PFI
INCLUDING _
JIG AND SCOPE
(c) Nonnal Load
Equivalent to:
R2167'-1
_
-
C266-6
(d) HighZLoad
I
THEVENIN EQUIVALENT
OUTPUT
~
2.0V
Switching Characteristics Over the Operating Rangel2, 3, 5]
7C266-20
Parameter
Description
Min.
Max.
7C266-25
Min.
Max.
7C266-3S
Max.
Unit
tAA
20
25
35
45
ns
tHZCE
Chip Enable Inactive
to HighZ
25
30
40
45
ns
tHZDE
Output Enable Inactive
to High Z
12
12
20
25
ns
tADE
Output Enable Active
to Output Valid
12
12
20
25
ns
tACE
Chip Enable Active
to Output Valid
25
30
40
45
ns
taHA
Data Hold from
Address Change
tpu
Chip Enable Active to Power-Up
25
30
40
45
ns
tpD
Chip Enable Inactive to Power-Down
25
30
40
45
ns
3
4-132
Max.
7C266-4S
Address to Output Valid
3
Min.
3
Min.
3
ns
~YPRESS
CY7C266
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMAUZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
" 1.4
.P
Jl1.1 f-~--j------I
C
c
w 1.2
N
o
'~
""'"
00
1.0
r-...
2.0
r-..
3.0
~ 125
/'
100
z
75
~
:: /
oV
0.0
J
1/
1.0
3.0
OUTPUT VOLTAGE
20
V
/
/
10
5
'"
./
V
a0
200
400
~
0.85
a:
0
z 0.80
0.75
0.70
4.0
M
4-134
I
I'\.
"\..
cw 0.90
N
a
Vee = 4.5V
TA = 25'C '1
I
600 BOO 1000
CAPACITANCE (pF)
\
Jl 0.95
:;
Vee = 5.0V
TA = 25'C
I
2.0
25
~
1.05
1.00
6.0
M
/
NORMALIZED SUPPLY CURRENT
vs. CYCLE PERIOD
---
!z
~
4.0
OUTPUT VOLTAGE (V)
5.5
V
15
..........
5.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING
35
OUTPUT SINK CURRENT
vs OUTPUT VOLTAGE
(jj
4.5
SUPPLY VOLTAGE
60
~ 175
-150
a:.::a:
TA = ~5'C
0.4
4.0
OUTPUT SOURCE CURRENT
vS.VOLTAGE
a:
~
~
oz
AMBIENT TEMPERATURE ('C)
1.6
1.0
~
"'" 0.6
M
2001V
static discharge
• Slim 300-mil, 2S-pin plastic or
hermetic DIP
Logic Block Diagram
Functional Description
The CY7C269 is it 8K x 8 registered diagnostic PROM. It is organized as 8,192
words by 8 bits wide, and has both a pipeline output register and an onboard diagnostic shift register. The device features a
programmable initialize byte that may be
loaded into the pipeline register with the
initialize signal. The programmable initialize byte is the 8,193rd byte in the
PROM, and may be programmed to any
desired value.
Pin Configurations
CerDIP/FIatpack
ThpView
Vee
A,
""
As
""""
32
~
AlO
As
A"
A2
MOOE
CLOCK
A,
A'2
ElEs.1
SOl
soo
As
0,
0,
00
o.
0,
O2
GNO
o.
0,
C269-2
SOl
soo
LCClPLee (Opaque Only)
ThpV,ff'
:t!R~!;(.J? Jf Jf
As
MO~
CLOCK
A,
As
00
4 3 2 111 282726
-25
24
23
22
21
10
20
1\213141516171W
A,o
A"
A'2
ElEs,1
SOl
SDO
0,
o8~8rJ(f8
'"
C269-3
C269-'
Selection Guide
Minimum Address Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum Operating Current
(rnA)
I
I
Commercial
Military
7C269-15
15
12
120
140
4-136
7C269-25
25
15
120
140
7C269-40
40
20
100
7C269-50
50
25
80
120
~YPRESS
CY7C269
Electrical Characteristics Over the Operating Rangd3, 4]
Parameter
VOH
Description
Test Conditions
Output HIGH Voltage Vcr; = Min., 10H = -2.0 rnA
VOL
Output LOW Voltage
7C269-15,25
Min. Max.
2.4
Vcr; = Min., 10H = -4.0 rnA
7C269-40
Min. Max.
2.4
2.4
Vee = Min., 10L = 8.0 rnA Com'1
Vee = Min., 10L = 6.0 rnA Mil
V
0.4
0.4
0.4
0.4
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
GNDs VINS Vee
-10
+10
-10
+10
loz
Output Leakage
Current
GND S VOUT S Vee,
Output Disabled
-40
+40
-40
+40
los[5]
Output Short Circuit
CUrrent
90
90
Icr;
Vee Operating Supply Vee = Max., lOUT = 0 rnA Com'l
Current
Mil
120
100
Ipp
Programming Supply
Current
VIHP
Input HIGH
Programming Voltage
VILP
Input LOW
Programming Voltage
2.0
0.4
VIH
Programming Supply
Voltage
Unit
V
V
0.4
Vee = Min., 10L = 12.0 rnA Com'!
Vee = Min., 10L = 8.0 rnA Mil
Vpp
7C269-50
Min. Max.
2.0
0.8
2.0
0.8
-10
-40
13
12
50
3.0
13
12
50
3.0
0.4
V
0.8
V
+10
+40
fAA.
fAA.
90
rnA
80
rnA
120
140
12
V
13
V
50
rnA
3.0
0.4
V
0.4
V
Capacitance[4,6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
3. See the last page of this specification for Group A subgroup testing information.
4. See Introduction to CMOS PROMs in this Data Book for general information on testing.
5.
Max.
Unit
10
pF
10
pF
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
6. 'Iested initially and after any design or process changes that may affect
these parameters.
4-138
~YPRESS
CY7C269
Diagnostic Mode Switching Characteristics Over the Operating Range[3, 4]
Parameter
7C269-15
Min. Max.
20
7C269-25
Min. Max.
25
7C269-40,s0
Min.
Max.
30
tssm
Description
Set-Up SOl to Clock
Com'l
Mil
25
30
35
tHsm
SDI Hold from Clock
Com'l
0
0
0
Mil
0
0
0
tDSDO
tDCL
tDCH
tSM
tHM
tMS
tss
tso
tHO
SDO Delay from Clock
Minimum Clock LOW
Minimum Clock HIGH
Set-Up to Mode Change
Hold from Mode Change
ModetoSDO
SDItoSDO
Data Set-Up to DCLK
Data Hold from DCLK
ns
Com'l
20
25
30
Mil
25
30
40
Com'l
20
25
25
Mil
25
25
25
Com'l
20
25
25
Mil
25
25
25
Com'l
20
25
25
Mil
25
30
30
Com'l
0
0
0
Mil
0
0
0
ns
ns
ns
20
25
25
Mil
25
30
30
Com'l
30
40
40
Mil
35
40
45
20
25
25
Mil
25
30
30
Com'l
10
10
10
Mil
13
13
15
ns
ns
Com'l
Com'l
Unit
ns
ns
ns
us
ns
Switching Waveforms[3, 4]
Pipeline Operation (Mode = 0)
ADDDRESS _ _ _ _ _ _ _J
SYNCHRONOUS
ENABLE
PROGRAMMABLE - - - ,
PCLK/CLOCK
----1--'
OUTPUT
lODE
ASYNCHRONOUS
ENABLE _ _ _ _ _ _J
C269-7
4-140
~YPRESS
CY7C269
BitMap Data
Programmer Address (Hex.)
RAM Data
Decimal
Hex
Contents
0
0
Data
8191
8192
8193
IFFF
2000
2001
Data
Init Byte
Control Byte
LCC/PLCC (Opaque Only)
CerDlP/Flatpack
A7
Vee
Ao
Ao
A,;/Vpp
A"
Aa
Control Byte
00 Asynchronous output enable (default condition)
01 Synchronous output enable
02 Asynchronous initialize
A,
PGM
Vpp
NA
A,
NA
NA
A,
'VFY
Ao
Do
0,
0,
GND
Programming Modes
.l~~<"Jl~~
A,;/Vpp
A,o
A"
A12
Ao
07
0,
0,
0,
0,
...
...
4 3 2j11 282726
--
Aa
~
Do
10
4-142
22
21
20
'VFY
11121314151617113
Vpp
NA
07
c8'~&'d~8
co
C269-10
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
23
A10
A"
A12
25
2.
Figure 1. Programming Pinouts
C269-11
CY7C269
:'rcYPRESS
'J.Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
!
60
zw
50
:::>
40
I-
" 1.4
.l?
0
w 1.2
!:j
«
::;;
Icc
a: 1.0
0
/'
z
0.8
V
~
./
0
(,)
w
~
w
1.0
a:
z
5.0
5.5
«
~
/
a: 0.8 , / '
z
ll:!
125
i3
100
><:
z
1i5
75
'3
50
a:
./
/
~
o
0
-~
125
~
I'-....
"'~
o
0.0
30
'iiJ
.s
/" ~
/
o ,/
AMBIENT TEMPERATURE (0 G)
0
..'3
~w
V
0
Vce = 5.0V
TA = 25°C
1.0
2.0
3.0
4.0
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
1.00
w
0.90
!:j
«::;;
a:
0
z
4.0
I
Vee = 5.5V
TA = 25°C
\
\
0.85
0.80
"
0.75
0.70
o
25
'" ~
50
75
CLOCK PERIOD (ns)
4-144
/'
20
./
15
./
10
V
Vee = 4.5V _
TA = 25°C
!/
200
400
600
800 1000
CAPACITANCE (pF)
1.05
0.95
"
/
25
5
OUTPUT VOLTAGE (II)
"
0
3.0
35
25
.l?
2.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.0
1~
1.0
OUTPUT VOLTAGE (V)
.s 150
1.2
0.6
25
:::>
0
AMBIENT TEMPERATURE (0G)
<" 175
0
w
N 1.0
::::i
.........
:::>
0.8
-55
6.0
1.6
«
::;;
20
"' "-
c.. 10
::;;
i= 1.4
C/l
(,)
:::>
0
~
I-
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
C/l
W
(,)
30
C/l
I-
0.9
SUPPLY VOLTAGE (II)
w
(,)
a:
::;;
TA = 25°C
f=MAX.
4.5
a:
a:
0
V
0.6
4.0
1.1
OUTPUT SOURCE CURRENT
vs OUTPUT VOLTAGE
100
~YPRESS
CY7C269
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VlH
VIL
IIX
Ioz
Icc
ISB
Switching Characteristics
Parameters
Subgroups
tAS
7, 8, 9,
7, 8, 9,
7, 8, 9,
7, 8, 9,
7, 8, 9,
7, 8, 9,
7; 8, 9,
tHA
teo
tpw
tSES
tHES
teas
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
Diagnostic Mode Switching Characteristics
Parameters
Subgro~p's
tSSDI
7, 8, 9,
7,8, 9,
7,8,9,
7, 8, 9,
7, 8, 9,
7, 8, 9,
7, 8, 9,
7, 8, 9,
tHSDI
tDSDO
tDeL
tDCH
tHM
tMS
tss
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
Document #: 38-00069-G
4-146
PRELIMINARY
CY7C271A
32K X 8 Power-Switched and
Reprogrammable PROM
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• llighspeed
-25 ns (commercial)
-35 ns (military)
• Lowpower
-275 mW (commercial)
-330 mW (military)
• Super low standby power
- Less than 85 mW when
deselected
• EPROM technology 100%
programmable
• Slim 300-mil package
• Direct replacement for bipolar
PROMs
• Capable of withstanding >4001V
static discharge
Functional Description
The CY7C271A is a high-performance
32,768-word by 8-bit CMOS PROM.
When disabled (CE HIGH), the 7C271A
automatically powers down into a lowpower stand-by mode. The CY7C271A is
packaged in the 300-mil slim package and
is available in a cerDIP package equipped
with an erasure window to provide for reprogrammability. When exposed to UV
light, the PROM is erased and can be reprogrammed. The memory cells utilize
proven EPROM floating gate technology
and byte-wide intelligent programming algorithms.
The CY7C271A offers the advantages of
lower power, superior performance, and
Logic Block Diagram
programming yield. The EPROM cell requires only 12.5V for the super voltage,
and low current requirements allow for
gang programining. The EPROM cells allow each memory location to be tested
100% because each location is written
into, erased, and repeatedly exercised
prior to encapsulation. Each PROM is
also tested for AC performance to guarantee that after customer programming,
the product will meet DC and AC specification limits.
Reading the 7C271A is accomplished by
~cing active LOW signals on CSI and
CE, and an active HIGH on CS2. The
contents of the memory location addressed by the address lines (An - A14)
will become available on the output lines
(00 - 07).
Pin Configurations
DIPlFlatpack
Po.,
Po.,
0,
Vee
1
A,o
Al1
A,
X
ADDRESS
A,.
A,.
Po.,
Po.,
A,
8x10F128
MULTIPLEXER
6
A14
0,
Ao
CS,
A,
A,
es,
.0,
00
cr
Ao
0,
o.
o.
11
0,
o.
o.
0,
03
GND
LCC/PLCC (Opaque Only)
0,
<:~~~.f.f
Po.,
0,
A,
A,
Ao
Ao
00
A,
cr_-r-,
es,
es, -""'1..._'/r---------------------~
4 3 2 l~3231 3~9
5
6
7
8
28
27
26
25
9
11
NC
12
13
00
24
10
Ao
23
22
21
A12
A,.
A14
Ne
CS,
CS,
CE
0,
o.
14151617181920
C271A-l
.... C\lQU t'l .... U1
oozzooo
co
C271A-3
Selection Guide
7C27IA-25
Maximum Access Time (ns)
Maximum Operating Com'l
Current (rnA)
Military
StandbyCurrent(mA) Com'l
Military
75
7C271A-30
30
75
15
15
25
4-148
7C271A-35
35
50
85
15
7C27IA-45
45
50
60
15
25
25
7C27IA-55
55
50
60
15
25
~YPRESS
PRELIMINARY
CY7C271A
AC Test Loads and Waveforms
R1 5000
6580 MIL
R1 5000
6580 MIL
ALL INPUT PULSES
OUTP~~ ~
OUTP~~ ~ R2 3330 3.0V
.
R2 3330
30 I
4030 MIL
5 I
4030 MIL GND
pF
pF
j~8~~~NG -=
j~8~~~NG -=
-=
SCOPE
-=
SCOPE
(b) High-Z Load
(a) Normal Load
Equivalent to:
5. 5 ns
C271A-4
C271A-5
THEVENIN EQUIVALENT
25~~~IL
OUTPUT
o----vw----<>
2.00V Commercial
1.90V MIL
Switching Characteristics Over the Operating Range[3, 4]
Parameter
Description
7C271A-25
7C27IA-30
7C27IA-35
7C27IA-45
7C271A-55
Min.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Unit
tAA
Address to Output Valid
25
30
35
45
55
ns
tACS
CSl/CS2 Active to
Output Valid
12
15
15
15
20
ns
tACE
CE Active to Output
30
35
35
45
55
ns
tHZCS
CS1/CS2 Inactive to
HighZ
12
15
15
15
20
ns
tHZCE
CE Inactive to High Z
20
ns
tpu
CE Active to Power-Up
tpD
CE Inactive to Power·
Valid
15
12
0
0
30
15
15
0
35
0
0
40
40
ns
50
ns
Down
Output Data Hold
tOH
0
0
0
0
ns
0
Switching Waveform
ICC
tpo
ACTIVE
ADDRB
C271A-6
4-150
=r
PRELIMINARY
rcYPRESS
CY7C271A
'iYpical DC and AC Characteristics
1. 7
1. 6
1.1
\
\
0
61
0.9
N
::::; O.B
0.7
0.6
0.5
0.0
w
:::;:
1.25
"
1.15
~
1.1
" ""-
U
~ 1.05
w
~
1.0
~
0.95
TA=
!5'C
1.4
~
1.3
~
1.2
fa
1.1
II:
oz
5
5.5
I
-100
M
1
/
./
0.9
-100
SUPPLY VOLTAGE (V)
-50
V
!z
100
"-
~
'30..
'3- 20
0.0
0.0
1.0
'~
2.0
~
3.0
4.0
OUTPUT VOLTAGE (V)
4-152
60
100
150
20
5.0
I
/
Vee = 5.0V
TA = 25'C
II
40
o
150
~
Sl-40
()
~
og;
!zw
:J
BO
'3
100
50
.-
iii
OUTPUT SOURCE CURRENT vs.
OUTPUT VOLTAGE
II:
~
z
-100
o
120
:J
AMBIENT TEMPERATURE ('C)
~-BO
:J
U
~-60
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
(Above which the useful life may be impaired. For user guidelines,
not tested.)
.
Storage Temperature ................. - 65 ° C to + 150 ° C
Ambient Thmperature with
Power Applied ....................... -55°C to +125°C
Supply Voltage to Ground Potential ........ -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to + 7.0V
DC Input Voltage ....................... -3.0V to +7.0V
DC Program Voltage ............................. 13.0V
UV Erasure ............................. 7258 Wsec/cm2
Operating Range
Ambient
Temperature
Range
Commercial
Industrial[l]
-40°C to +85°C
5V ±lO%
Military[2]
-55°C to + 125°C
5V ±lO%
Vee
5V±lO%
O°C to +70°C
Electrical Characteristics[3, 4]
CY7C276-25
CY7C276-30
CY7C276-35
Parameter
Test Conditions
Description
Min.
Max.
Unit
0.4
V
Vee
0.8
V
-3.0
-lO
+lO
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
= Min:, IOH = -2.0 rnA
Vee - Min., IOL = 8.0 rnA (6.0 rnA Mil)
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
2.0
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs
IIX
Input Leakage Current
GND.$. VIN.$. Vee
VeD
Input Clamp Diode Voltage
Ioz
Output Leakage Current
Vee = Max., VOL.$. VOUT.$. VOH,
Output Disabled
los
Output Short Circuit Current
Vee - Max., VOUT - O.OVPJ
Icc
Power Supply Current
Vee
2.4
Vee
V
V
-40
+40
!lA
!lA
!lA
-20
-90
rnA
175
rnA
200
rnA
Note 3
I Com'l
IMilitary
= Max., lOUT = 0.0 rnA
Capacitance[3]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature
3. See Introduction to CMOS PROMs in this Data Book for general in-
4.
Max.
10
= 1 MHz,
lO
Unit
pF
pF
See the last page of this specification for Group A subgroup testing information.
5. For test purposes, not more than one output at a time should be
.shorted. Short circuit test duration should not exceed 30 seconds.
formation on testing.
AC Test Loads and Waveforms
R1 SOOQ
ALL INPUT PULSES
R1 SOOQ
OUTP~~~) OUTP~~ ~ ~i3Q
R2
,~~~:Fi
INCLUDING
~gtpNED
-=-
1333Q
-=- ~~~Q
(a) Normal Load
,~,.~:Fi
INCLUDING
~gtPNf
-=-
1-=- (403Q
3.0V---90%
GND
MIL)
C276-3
(b) High Z Load
C276-4
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
200Q (2S0Q MIL)
2.0V (1.9V Mil)
o-----wv----o
4-156
~YPRESS
CY7C276
Architecture Configuration Bits
Programming Information
The CY7C276 has four user-programmable options in addition to
the reprogrammable data array. For detailed programming information contact your local Cypress representative.
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of this
section. Programming algorithms can be obtained from any Cypress representative.
The programmable options determine the active pOlarity for the three
chip selects (~ - CSo) and OE. When these control bits are programmed with a 0 the inputs are active LOW. When these control bits
are programmed with a 1 the inputs are active IDGH.
Table 1•. Control Word for Architecture Configuration
Control Word
Control Option
Bit
OE
Do
O=Default
1 =Programmed
Programmed Level
OE Active LOW
OEActiveIDGH
CSo
Dl2
O=Default
1 =Programmed
CSo Active LOW
CSo Active HIGH
CSI
Dl3
O=Default
1 =Programmed
CSI Active LOW
CSI Active HIGH
CS2
Dl4
O=Default
1 = Programmed
CS2 Active LOW
CS2 Active IDGH
BitMap
Function
Table 2. Program Mode Table
Programmer Address (Hex)
0000
Vpp
PGM
VFY
Do - D15
Program Inhibit
Vpp
VIHP
VIHP
HighZ
Program Enable
Vpp
VILP
VIHP
Data
Program Verify
Vpp
VIHP
VILP
Data
Mode
RAM Data
Data
3FFF
Data
4000
Control Word
Control Word (4000H)
Dl5
Do
X CS2 CSI CSo X X X X X X X X 1 X X OE
Table 3. Configuration Mode Thble
Vpp
PGM
VFY
Az
Program Inhibit
Vpp
VIHP
VIHP
Vpp
HighZ
Progrant Control Word
Vpp
VILP
VIHP
Vpp
Control Word
Verify Control Word
Vpp
VIHP
VILP
Vpp
Control Word
Mode
(¥):!I0~8:~8~I~t~~
c> > > > > D.. > 0
0- c
6 5 4 3 2 ~1~ 44 43 42 41 40
012
0"
010
D.
D.
Vss
Vee
0,
De
Os
0,
9
10
39
38
37
CY7C276
36
0
11
12
13
,.
35
34
33
32
15
31
16
30
17
29
1819202122232.25262728
C')
a a
N
ow en 0 .... C\I
a o>cn<. <. < <.
......
C
CO)
As
Vss
Vss
As
A,
As
As
'I/"
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
lemperature
Range
Commercial
O°Cto +70°C
Vee
5V ±1O%
Industrial[l]
-40°C to +85°C
5V ±10%
Military[2]
-55°C to + 125°C
5V ±1O%
Electrical Characteristics Over the Operating Rangd3, 4]
7C277-30
Parameter
Description
lest Conditions
Min.
= Min., IOH = - 2.0 mA
Vee = Min., IOL = 8.0 rnA
2.4
2.0
Max.
7C277 -40, 50
Min.
Max.
Unit
0.4
V
Vee
V
0.8
V
+10
!lA
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage
for All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage
for All Inputs
IIX
Input Leakage Current
GND S. VIN S. Vee
VeD
Input Clamp Diode Voltage
loz
Output Leakage Current
Os. VOUT s. Vee, Output Disabled[5]
-40
+40
-40
+40
!lA
los
Output Short Circuit Current
Vee
-20
-90
-20
-90
rnA
Icc
Power Supply Current"
= Max., VOUT = 0.0y[6]
Vee = Max., "CS ~ VIH I Commercial
lOUT = ornA
120
mA
Vee
2.4
0.4
Vee
2.0
0.8
-10
+10
-10
Note 4
120
1Military
Vpp
Programm~~
Ipp
Programming Supply Current
VIHP
Input HIGH Programming Voltage
VILP
Input LOW Programming Voltage
V
130
12
Supply Voltage
13
12
50
3.0
V
rnA
3.0
0.4
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
13
50
V
0.4
V
4. See "Introduction to CMOS PROMs" in this Book for general in"
formation on testing.
5. For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4-162
~YPRESS
CY7C277
Architecture Configuration Bits
Architecture Verify D7 - Do
O-DEFAULT
1 =PGMED
O-DEFAULT
D2
1 =PGMED
O-DEFAULT
Do
1 =PGMED
Architecture Bit
ALE
D1
ALEP
IllEs
Function
Input Transparent
Input Latched
ALE - Active HIGH
ALE = Active LOW
Asynchronous Output Enable (E)
Synchronous Output Enable (Es)
BitMap
Programmer Address (Hex.)
RAM Data
0000
Data
7FFF
8000
Data
Control Byte
Architecture Byte (8000)
D7
Do
C7 C6 Cs C4 C3 C2 Cl Co
Timing Diagram (Input Latched)[9]
ALE
1:8
(SYNCH)
CP
00 - 0 7
----'
HZ~__
E8 _________________________________________________t__
t_u_E_____
(ASYNCH)
C277-6
Timing Diagram (Input Transparent)
AD - A14 ______J
, ____________,
,--------------'1 ~=t::_::::;t:=~1 , _______________
1:8
(SYNCH)
CP
00
-
07
________,
,,______J
E8
~SYNCH) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - "
C277-7
Note:
9. ALE is shown with positive polarity.
4-164
~YPRESS
CY7C277
1YPical DC and AC Characteristics
NORMALIZED ACCESS TIME
VS. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMUUJZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
w
1.2
:;
JS
0
UJ
N
~
1.4
0
z
1/
0.6
4.0
V
~
!,i
a:
w
::J
~ 1.0
5.0
C
5.5
AMBIENT TEMPERATURE ('C)
1.6
60
!z
50
~
1.4
;:)
Cf)
ffW
"1"'-"
30
;:)
10
.
g
20
~ 0.8
~
10
0.6
- 55
25
125
o
00
25.0
'iiJ
.s
"'3.0
5.0
"'-
4.0
~ 175
150
M!
125
./
13 100
:.:
z 75
iii
~ 50
~
25
~
/'
/
o1/
0.0
Vcc = 5.0V
TA = 25'C -
I
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4-166
V
V
V
/
TA = 25'C _
VfC = 4 5V
j
200
400
600
800 1000
CAPACITANCE (pF)
OUTPUT SINK CURRENT
vS.OUTPUTVOLTAGE
~
6.0
/
::!
!j
~ 10.0
OUTPUT VOLTAGE (V)
a:
5.5
/
20.0
::( 15.0
~
2.0
1.0
AMBIENT TEMPERATURE ('C)
!z
5.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
I\.
;:) 40
.--
I
4.5
30.0
tl
1.2
1
TA = 25'C
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vS.VOLTAGE
<"
.§.
:;
Iii
0.4
4.0
0!5~5---~2~5~----~125
6.0
NORMALIZED SET-UP TIME
vs. TEMPERATURE
~
«
:; 0.6
a:
0
Z
SUPPLY VOLTAGE (V)
w
0.8
N
~ 0.91----+-----=~~
TA= 25'C
f=fMAX
-
1.0
W
tl
I
4.5
Cf)
Cf)
1-----+-------1
1.1
c
./
a: 1.0
0.8
JS
/
1.2
i=
4.0
CY7C281A
CY7C282A
lKx8PROM
• Capable of withstanding> 2001V
static discharge
Features
• CMOS for optimum speed/power
Functional Description
• High speed
•
•
•
•
•
•
-25 ns (commercial)
- 30 ns (military)
Lowpower
-495 mW (commercial)
- 660 mW (military)
EPROM technology 100%
programmable
Slim 300-mil or standard 600-mil DIP
or 28-pin LCC
SV ±10% Vee. commercial and
military
TTL-compatible I/O
Direct replacement for bipolar
PROMs
The CY7C281A and CY7C282A are
high-performance 1024-word by 8-bit
CMOS PROMs. They are functionally
identical, but are packaged in 3OO-mil and
600-mil-wide packages respectively. The
CY7C281A is also available in a 28-pin
leadless chip carrier. The memory cells
utilize proven EPROM floating-gate
technology and byte-wide intelligent programming algorithms.
The CY7C281A and CY7C282A are
plug-in replacements for bipolar devices
and offer the advantages oflower power,
superior performance, and programming
Logic Block Diagram
yield. The EPROM: cell requires only
12.5V for the super voltage, and low Current requirements allow for gang programming. The EPROM cells allow each
memory location to be tested 100% because each location is written into, erased,
and repeatedly exercised prior to encapsulation. Each PROM is also tested for
AC performance to guarantee that after
customer programming;' the product will
meet DC and AC specification limits.
Reading is accomplished by placing an active LOW signal on CSl and CSz, and active HIGH signals on CS3 and CS4. The
contents of the memory location addressed by the address lines (Ao - A9)
will become available on the output lines
(00 - 07)·
Pin Configurations
DIP
lbpView
07
o.
ROW
DECODER
COLUMN
DECODER
PROGRAMMABLE
ARRAY
Vee
A,;
A,;
A,;
A..
MULTIPLEXER
1-----------..1
A7
0,
""
0,
00
0,
""cs"
CS,
4
A2
A,
Ao
CS3
es,
07
o.
9
0,
0,
03
02
GND
I--------------J
03
C2B1A-2
LCC/PLCC
lbpView
02
""
~Ui
C2B1A-1
C281A-3
Selection Guide
7C28IA-2S
7C282A-2S
Maximum Access Time (ns)
Maximum o~erating
Current (rnA
25
I
I
Commercial
Military
100
4-168
7C28IA-30
7C282A-30
30
100
120
7C28IA-4S
7C282A-4S
45
90
120
CY7C281A
CY7C282A
ttzi?crPRESS
AC Test Loads and Waveforms l4]
OUTP~~31R1
250Q
FI
30 P
INCLUDING _
JIG AND SCOPE
OUTP~~31R1
250Q
R2
167Q
5 PF
INCWDING _
JIG AND SCOPE
_
,
G5::~'
R2
16m
_
-
~
10%
55n8
C2B1A-5
C281A-4
(b) High Z Load
(a) Normal Load
Equivalent to:
I
ALL INPUT PULSES
3 . 0 V 3 1 90%
NO
.
10%
THEVENIN EQUIVALENT
100Q
OUTPUTo.o--""·.""
..._---ClO 2.0V
Switching Characteristics Over the Operating Rangel2,4]
7C281A-25
7C282A-25
Parameter
Description
Min.
7C28IA-30
7C282A-30
Max,
tAA
Address to Output Valid
25
tHZCS
Chip Select Inactive to High Z
15
tACS
Chip Select Active to Output Valid
15
Min.
Max.
30
20
20
7C28IA-45
7C282A-45
Min.
Max.
Unit
45
ns
25
DS
25
DS
Switching Waveforms
AD - As
ADDRESS
~
SElECTED
.Ir\.
SELECTED
~-Jl-<~E1~-
-tAA
00- 07
DATA
DESELECTED
tHzcS
I+---
tACS
C281A-6
4-170
CY7C281A
CY7C282A
1YPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
v•. AMBIENT TEMPERATURE
NORMUUUZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.6
Jl1.4
c
w
~
.1.2
::0
a: 1.0
0
z
0.8
/
0.6
4.0
V
/
«
V
Jl1.1
~
5.0
(J)
(J)
5.5
«
c
~
::::;
1.4
1.0
«
::0
a: 0.8
0
0~5·'::-5----;2!::5------:-:!125
1
60
!zw
50
40
~
w
~
30
~
25
125
"
.s
'""-
1.0
2.0
-
~
3.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~
z
~
iii
./
100
~
50
5
25
oI
0.0
V
II
200
,
Jl 0.98
c
w
0.96
~
::;:
0.94
az
0.92
N
Vee = 5.0V
TA = 25°C
I
/
2.0
3.0
400
a:
0.88
OUTPUT VOLTAGE (V)
I
Vee 5.5V
TA 25°C
=
=
\
"
0.90
4.0
o
25
'"'50
75
CYCLE PERIOD (ns)
4-172
Vee = 4.5V _
TA = 25°C
I
I
600 800 1000
CAPACITANCE (pF)
1.00
I---
V
/
1.0
10.0
5.0
v
V
./
Icc v•• CYCLE PERIOD
,/
75
V
15.0
4.0
1.02
~ 125
a
l!l
'"I"
~ 175
a:
:::
20.0
OUTPUT VOLTAGE (V)
-150
6.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
25.0
AMBIENT TEMPERATURE (OC)
!z
5.5
(i)
10
5o
5.0
SUPPLY VOLTAGE (V)
~
@ 20
z
0.6
I
4.5
30.0
t)
- 55
TA = 25°C
0.4
4.0
OUTPUT SOURCE CURRENT
v•• VOLTAGE
~
:::l
~
i'-.. ~
~
az
AMBIENT TEMPERATURE (0G)
1.6
1.2
0.8
"'" 0.6
6.0
w
t)
t)
c
~
a:
NORMUUUZED ACCESS TIME
vs. TEMPERATURE
w
1.0
~
z
I
4.5
(J)
~
~
TA = 25°C
f= fMAX
~
w
:::;;
F
f----t-------i
SUPPLY VOLTAGE (V)
::0
F
NORMALIZED ACCESS TIME
v•• SUPPLY VOLTAGE
1.2
1.2
100
CY7C287
64K X 8 Reprogrammable
Registered PROM
Features
• Slim 300-mil package
• CMOS for optimum speed/power
• Windowed for reprogrammability
• Capable of withstanding >2001V
static discharge
• High speed
-tSA = 4Sns
-teo = lSns
• Lowpower
-120mA
• On-chip, edge-triggered output
registers
• Programmable synchronous or
asynchronous output enable
• EPROM technology, 100%
programmable
• 5V ±10% Vee, commercial and
military
• TIL-compatible I/O
technology and byte-wide intelligent programming algorithms.
The CY7C287 offers the advantage oflow
power, superior performance, and programming yield. The EPROM cell requires only 12.5V for the Supervoltage and
low current requirements allow for gang
programming. The EPROM cells allow for
each memory location to be 100% tested
with each cell being programmed, erased,
and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC
performance to guarantee that the product
will meetDCandAC specification limits
after customer programming.
Reading the CY7C287 is accome!i~ed by
placing an active LOW signal onElEs. The
contents ofthe memory location addressed
by the address lines (Ao - A1S) will become available on the output lines (00 07) on the next rising of CPO
Functional Description
The CY7C287 is a high-performance 64K
x 8 CMOS PROM. The CY7C287 is
equipped with an output register and an
output enable that can be programmed to
be synchronous (Es) or asynchronous (~).
It is available in a 28-pin, 300-mil package. The address set-up time is 45 ns and
the time from clock HIGH to output valid
is 15 ns.
The CY7C287 is available in a cerDIP
package equipped with an erasure window
to provide reprogrammability. When exposed to UV light, the PROM is erased
and can be reprogrammed. The memory
cells utilize proven EPROM floating-gate
Logic Block Diagram
Pin Configurations
A14 .....
X
A13 .....
A12 .....
CerDIP
ThpVlew
I--I----/::>- 0,
A15 ....
ROW
ADDRESS
512x 1024
PROGRAM·
MABLE
ARRAY
A1t .....
A1Q ....
8x1of128
MULTIPLEXER
B-BIT
EDGETRIGGERED
REGISTER
o.
Os
ADDRESS
DECODER
1.0'"
A, . . .
Al1
A,.
A'3
A14
Af5
CP
Ag
A,
03
Ag . . .
...
""...
A,o
As
1.0
A,
A, . . .
~
Vee
A,
~
Ag . . .
Ag . . .
Ag
1.0
COLUMN
ADDRESS
'---+1>-0.
'----;-\:>- 0,
Y
Ag'"
'----+{)- 0
A, ...
EiEs
""
0,
00
0,
o.
o.
O.
Os
GND
00
C287-3
0
LCC/pLCC
ThpView
EiEs
()o~
JfJi::etj?:z:z
CP
As
~
A,
NC
A.
A,
""
GND
00
;; 3 2,~323130
29
28
7C287
27
7
5
6
B
9
10
11
12
13
0
26
25
24
A,.
A'3
A14
A,s
NC
CP
23
22
EiEs
21
GND
0,
14151617181920
orS'ficM(f(f
co
C287-2
4-174
CY7C287
AC Test Loads and Waveform[4]
R1500Q
R1500Q
1~ o~: '~II1~
ALL INPUT PULSES
OU"':;;': '" p' II
INCLUDING _
JIG AND SCOPE
It::
....
_ (403Q MIL) INCLUDING
(403Q MIL)
JIG AND
C287-5
SCOPE
(a) Normal Load
(b) High Z Load
Equivalent to:
-=
-=
_5ns
C287-4
THEVENIN EQUIVALENT
200Q
OUTPUT 0-0- -....•.,.,
•..._ - - - 0 0 2.0V
250Q
OUTPUT 0-0- -...."N
...-....----oO 1.9V
Military
Commercial
Switching Characteristics Over the Operating Rangel3, 4]
7C287-45
Parameter
Description
Min.
Max.
7C287-55
Min.
Max.
7C287-65
Min.
Max.
Unit
tSA
Address Set-Up to Clock HIGH
45
55
65
tRA
Address H.old from Clock HIGH
0
0
0
teo
Clock HIGH to Output Valid
15
20
25
fiS
tRZE
Output High Z from E
15
20
25
ns
15
20
25
ns
fiS
fiS
tDOE
Output Valid from E
tpwe
Clock Pulse Width
15
20
25
ns
tSEs[6]
Es Set-Up to Clock HIGH
12
15
18
ns
tHEs[6]
Es Hold from Clock HIGH
5
tHZd 6]
Output High Z from CLK/Es
20
25
30
ris
teos[6]
Output Valid from CLKJEs
20
25
30
fiS
Note:
6. Parameters with synchronous Es option.
4-176
ns
10
8
~YPRESS
CY7C287
LCe
DIP
.f<:~~~i
Vee
A'0
A"
A1WA14
A1a1A15
LATCH
6
7C287
i
Vpp
10
11
12
l'GM
VFV
13
D7
0
2f3
E
24
23
22
21
A1VA14
A13iA15
LATCH
Vpp
NC
l'GM
VFV
~D
14151617181920
D.
D.
C287-8
D4
D.
432,1,323130
-29
5
C2f37-7
Figure 1. Programming Pinouts
Architecture Configuration Bits
Architecture
Bit
Architecture Verify
Do
Device
7C287
EiEs
Do
I 0 = Erased
I 1 =PGMED
BitMap
Programmer Address (Hex.)
RAM Data
0000
Data
FFFF
10000
Data
Control Byte
Architecture Byte (10000H)
D7
Do
C7 C6 Cs C4 C3 C2 Cj Co
4-178
Function
Asynchronous Output Enable (Pin 20 =
Synchronous Output Enable (Pin 20 =
m
lis)
CY7C291A
CY7C292A/CY7C293A
2K X 8 Reprogrammable PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• Direct replacement for bipolar
PROMs
• Capable ofwlthstanding >2001V static discharge
Functional Description
• High speed
- 20 ns (commercial)
-25 ns (military)
• Lowpower
- 660 mW (commercial and military)
• Low standby power
-220 mW (commercial and military)
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil
packaging available
• SV ±10% Vee. commercial and
military
• TTL-compatible I/O
The CY7C291A, CY7C292A, and
CY7C293A are high-performance 2Kword by 8-bit CMOS PROMs. They are
functionally identical, but are packaged in
3OO-mil (7C291A, 7C293A) and 600-mil
wide plastic and hermetic DIP packages
(7C292A). The CY7C293Ahas an automatic power down feature which reduces
the power consumption by over 70% when
deselected. The 300-mil ceramic package
may be equipped with an erasure window;
when exposed to UV light the PROM is
erased and can then be reprogrammed.
The memory cells utilize proven EPROM
floating-gate technology and byte-wide intelligent programming algorithms.
Logic Block Diagram
Pin Configurations
Ao
DIP
Top View
0,
A,
A,
As
ROW
ADDRESS
PROGRAM·
MABLE
ARRAY
0,
A.o
05
A,;
A,;
ADDRESS
DECODER
0,
A,
0,
A,;
A,;
The CY7C291A, CY7C292A, and
CY7C293A are plug-in replacements for
bipolar devices and offer the advantages of
lower power, reprogrammability, superior
performance and programming yield. The
EPROM cell requires only 12.5V for the
supervoltage and low current requirements allow for gang programming. The
EPROM cells allow for each memory location to be tested 100%, as each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to guarantee that after customer programming
the product will meet DC and AC specification limits.
Aread is accomJ'lished by placing an active
LOW signal on CSj, and active HIGH signals on CS2 and CS3. The contents of the
memory location addressed by the address
line (Ao - AlO) will become available on
the output lines (00 - 07).
LCC/PLCC (Opaque Only)
Top View
A,
Vee
A,;
A,;
A,;
A,;
A.o
As
CS,
A'0
A,
A,
CS,
CS,
Ao
0,
0,
0,
0,
0,
00
0,
COLUMN
ADDRESS
0,
A10
0,
GND
:n!<~?~/f
A.o
As
As
A,
Ao
NC
00
4 3 2l~ 2827~5
24
23
22
21
20
10
19
11
12131415161718
A'0
CS,
CS,
cs,
NC
0,
0,
ocS''il~80'd'
'"
0,
C291A-3
C291A-2
Window available on
7C291A and 7C293A
only.
00
OS, --'--"'.----...
C~
r---------------------------~
CS,
--l.--/
C291A-1
Selection Guide
Maximum Access Time (ns)
Standard
Maximum 0serating
Current(mA
L
Stand'A Current (rnA)
7C293 Only
Commercial
Military
Commercial
Commercial
Military
7C291A-20
7C292A-20
7C293A-20
20
120
40
4-180
7C29IA-25
7C292A-25
7C293A-25
7C29IAL-2S
7C292AL-25
7C293AL-2S
25
90
120
60
30
40
7C29IA-35
7C292A-35
7C293A-35
7C29IAL-3S
7C292AL-35
7C293AL-3S
35
90
90
60
30
40
7C291A-50
7C292A-50
7C293A-50
7C29IAL-SO
7C292AL-SO
7C293AL-SO
50
90
90
60
30
40
~.~
CY7C291A
CY7C292A/CY7C293A
.
,CYPRESS
================
Electrical Characteristics Over the Operating Range[3. 4] (continued)
7C291AL-35, 50
7C292AL-35,50
7C293AL-35, 50
Test Conditions
Min.
VOR
Output HIGH Voltage
Description
Vee = Min., lOR = -4.0 rnA
2.4
VOL
Output LOW Voltage
Vee = Min., IOL = 16.0 mA
VIR
Input HIGH Voltage
Guaranteed Input Logical
HIGH Voltage for All Inputs
VIL
Input LOW Voltage
Guaranteed Input Logical
LOW Voltage for All Inputs
IIX
Input Load Current
GND.$. VIN.$. Vee
VeD
Input Diode Clamp Voltage
Ioz
Output Leakage Current
GND .$. VOUT .$. Vcc.
Output Disabled
-10
+10
los
lee
Output Short Circuit Current[5]
Vee = Max.• VOUT = GND
Vee = Max.• Commercial
VIN = 2.0V
Military
IOUT=OmA
-20
-90
Parameter
Vee Operating Supply Current
Standby SUPPI) Current
(7C293A Only
ISB
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming Voltage
VILP
Input LOW Programming Voltage
7C291A-35,50
7C292A-35,50
7C293A-35,50
Max.
Min.
0.4
2.0
Unit
0.4
V
V
2.0
0.8
-10
Max.
2.4
0.8
V
+10
!lA
-10
+10
!lA
-20
-90
rnA
90
rnA
-10
+10
V
Note 4
Vee = Max.,
CSl =VIH
60
90
Commercial
30
rnA
30
Military
40
12
13
12
50
13
V
50
rnA
0.4
V
3.0
3.0
0.4
V
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
CoUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
4-182
Max.
Unit
10
pF
10
pF
CY7C291A
CY7C292NCY7C293A
~
== r; CYPRESS
Erasure Characteristics
Wavelengths oflight less than 4000 Angstroms begin to erase these
PROMs. For this reason, an opaque label should be placed over
the window ifthe PROM is exposed to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity x exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12
m W/cm2 powerrating, the exposure time would be approximately
35 minutes.
These PROMs need to be within 1 inch ofthe lamp during erasure.
Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is
the recommended maximum dosage.
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of this
section. Programming algorithms can be obtained from any Cypress representative.
Table 1. Mode Selection
Pin Function[7]
Mode
Read or Output Disable
AlO -
Other
AlO -
Read
AlO -
Output Disabld8]
AlO -
Output Disable
AlO -
Output Disable
AlO -
Program
AlO -
Program Verify
AlO -
Program Inhibit
AlO -
Intelligent Program
AlO -
Blank Check Zeros
AlO -
Au
Au
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
CS3
CS2
CSl
PGM
VFY
Vpp
D7 - Do
VIH
VIH
VIL
07 - 00
X
X
VIH
HighZ
X
VIL
X
HighZ
VIL
X
X
HighZ
VILP
VIHP
Vpp
D7- DO
VIHP
VILP
Vpp
07 - 00
VIHP
VIHP
Vpp
HighZ
VILP
VIHP
Vpp
D7- DO
VIHP
VILP
Vpp
Zeros
07 - 00
Notes:
7.
X: "don't care" but not to exceed Vee +5%.
8.
The power-down mode for tbe CY7C293A is activated by deseJecting
"CS1·
LCC/PLCC (Opaque Only)
Top View
DIP
Top View
:f:tJ(g~u
Vee
Aa
Aa
AlO
Vpp
Ds
D.
0,
D.
GND
~
~;
22
Ao
NC
Do
07
DO
4 3 2 1 11 282726
..
25
A1
VFY
PGfiI
D,
~
10
11
21
20
19
12131415161718
.... Ne 0
(")0::1'
AlO
vpp
VPI
I'GM
NC
0]
De
It)
aczzcaa
co
D3
C291A-8
C291A-7
Figure 1. Programming Pinouts
4-184
CY7C291A
CY7C292NCY7C293A
Ordering Information[91
Speed Icc
(ns) (rnA)
20
120
25
60
90
120
Ordering Code
CY7C291A - 20JC
CY7C291A - 20PC
CY7C291A-20SC
CY7C291A - 20W,C
c:;Y7C29lAL-25JC
CY7C291AL- 25PC
CY7C291AL..,. 25WC
CY7C29~A-25JC
CY7C291A-25PC
CY7C291A - 25SC
CY7C291A-25WC
CY7C291A:'" 25Dj\1B
CY7C291A-25LMB
CY7C2914.,25QMB
CY?C291A-25TM/3
30
35
120
60
90
120
50
60
90
90
I
Package
Name
J64
P13
S13
W14
J64
P13
W14
J64
P13
S13
W14
D14
L64
Q64
T73
.~Y7C291A-25WMB
W14
CY7p91A-~ODMB
D14
L64
Q64
T73
W14
J64
P13
W14
S13
P13
W14
D14
L64
Q64
CY7C291A-30LMB
CY7C291A-30QMB
CY7C291A-30TMB
CY7C291A-30WMB
CY7C291AL-35JC
CYIC291AL- 35PC
CY7C291AL-35WC
CY7C291A-35SC
CY7C291A - 35PC
CY7C291A - 35WC
CY7C291A - 35DMB
CY7C291A-35LMB
CY7C2nA -35QMB
CY7C2'}lA-35TMB
CY7C291A-35WMB
CY7C291AL-50JC
CY7C291AL-50PC
CY7C291AL-50WC
CY7C291A-SOSC
CY7C291A -'-50PC
CY7C291A-50WC.
CY7C291A-50DMB
CY7C291A-50LMB
CY7C291A:'" 50QMB
CY7C291A-50TMB
CY7C291A-50WMB
T73
W~4
J64
P13
W14
S13
P13
W14
D14
L64
Q64
T73
W14
Package lYpe
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOIC
24-Lead (300-Mil) Wmdowl;ld CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28~Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOIC
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin W,indowed Leadless Chip Carrier
24-Lead Windowed Cerpack·
24-Lead (300-MiI) Windowed CerDIP
24-Lead (300-Mil) c;erQIP
28-Square Leadless Chip Carrier
28-Pin Windowed LeadlessChip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip <;arrier
24-Lead (300-~1il) Mqlded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead Molded SOIC
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil),CerDIP
28-Square Leadless Chip Carrier
28-Pi!! Windowed LeadlessChip Carrier
24-Lead Windowed.·Cerpack
24-Leag (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead.(300-Mil} Molded DIP
24:1~ad (300~Mil) Windowed CerDIP
24-Lead Molded SOIC
24,Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
Note:
9.
Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
4-186
Operating
Range
Commercial
Commercial
Military
Military
Commercial
Commercial
Military
Commercial
Commercial
Military
CY7C291A
CY7C292NCY7C293A
=~
,CYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIH
VIL
Ilx
Ioz
Icc
ISB[lO]
1,2,3
Switching Characteristics
Parameter
Subgroups
tAA
tACSl[ll]
tACS2[lO]
7,8,9,10,11
7,8,9, 10, 11
7,8, 9, 10, 11
Notes:
10. 7C293A only.
11. 7C291A and 7C292A only.
Document #: 38-00075-G
SMD Cross Reference
SMD
Number
5962-87650
5962-87650
5962-87650
5962-87650
5962-87650
5962-87650
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
4-188
Cypress
Suffix
01KX
01LX
013X
03KX
03LX
033X
01LX
01KX
013X
02LX
02KX
023X
03LX
03KX
033X
04LX
04KX
043X
02JX
02KX
02LX
023X
03JX
03KX
03LX
033X
04JX
04KX
04LX
043X
Number
CY7C291-50TMB
CY7C291-50WMB
CY7C291- 50QMB
CY7C291 - 35TMB
CY7C291- 35WMB
CY7C291-35QMB
CY7C293A -50WMB
CY7C293A - 50TMB
CY7C293A - 50QMB
CY7C293A - 35WMB
CY7C293A - 35TMB
CY7C293A - 35QMB
CY7C293A - 30WMB
CY7C293A - 30TMB
CY7C293A - 30QMB
CY7C293A - 25WMB
CY7C293A - 25TMB
CY7C293A - 25QMB
CY7C292A -45DMB
CY7C291A -45KMB
CY7C291A -45DMB
CY7C291A -45LMB
CY7C292A-35DMB
CY7C291A - 35KMB
CY7C291A - 35DMB
CY7C291A - 35LMB
CY7C292A-25DMB
CY7C291A-25KMB
CY7C291A-25DMB
CY7C291A - 25LMB
Non-Volatile Memory
Programming Information
QYPRESS
Special Features
Depending on the specific CMOS PROM in question, additional
features that require programming may be available to the designer. 1Wo of these features are a Programmable Initial Byte
and Programmable Synchronous/Asynchronous Enable available
in some of the registered devices. Like programl11ing the array,
these features make use of EPROM cells and are programmed in
a similar manner using supervoltages. The specific timing and
programming requirements are specified in the data sheet of the
device employing the feature. Several Cypress non-volatile memories feature an automatic device identification mode. This
mode is accessed by placing the supervoltage on the A9 address
pin. While Ag is HIGH, taking Ao WW will cause the Cypress
manufacturer ID (34H) to appear on the outputs. Thking Ao
HIGH will cause the device identifier to appear on the outputs.
See the specific datasheet for details.
Programming Support
Programming support for Cypress CMOS PROMs is available on
Cypress's QuickPro II and Impulse 3. Support is also available
from a number of programmer manufacturers, some of which are
listed below. In addition, Cypress offers factory programming for
all of these devices. Parts are programmed and 100% speed
tested to your code to ensure performance. Custom marking is
available also on programmed plastic (OTP) devices. Minimum
quantities apply. Contact a Cypress sales representative for more
information.
Cypress Semiconductor, Inc.
3901 North First St.
San Jose, CA 95134
(408) 943-2600
AVAL Data Corp.
M. K. Bldg. 2F 4-8 Nakaitabashi,
Itabashi - ku
Thkyo, Japan 173
03 (5375)-7321
BP Microsystems
10681 Haddington, Ste. #190
Houston, TX 77043
(800) 225 - 2102
DataI/O
Customer Resource Center
10525 Willows Rd. NE
P.O. Box 97046
Redmond, WA 98073-9746
(800) 247-5700
(206) 881-6444
Logical Devices Inc.
692 South Military 'frail
Deerfield, FL 33442
(305) 428-6868
Minato Electronics
4105, Minami Yamada-cho
Kohoku-ku
Yokohama, Japan 223
(045) 591-5611
SMS Mikrocomputersystem GmbH
1m Grund 15
D-7988 Wangen im AUgeau
BRD
(49) 7522- 5018
SMS Microcomputer
P.O. Box 1348
Lawrence, MA 01842
(508) 683-4659
Stag Microsystems
1600 Wyatt Dr.
Santa Clara, CA 95054
(408) 988-1118
System General
510 S. Park Victoria
Milpitas, CA 95035
(408) 263 -6667
Document #: 38-00235-A
4-190
iJjL
.~
."CYPRESS
F1F9s
Device
CY7C401
CY7C4d2
CY7C403
CY7C404
CY7C408A
CY7C409A
CY7C419
CY7C420
CY7C421
CY7c:::424
CY7C425
CY7C428
CY7C429
CY7C432
CY7C433
CY7C4421
CY7c4201
CY7C4211
CY7C4221
CY7C4231
CY7C4241
CY7C4251
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
CY7C439
CY7C441
CY7C443
CY7C451
CY7C453
CY7C455
CY7C456
CY7C457
CY7C460
CY7C462
CY7C464
CY7C470
CY7C472
CY7C474
Section Contents
Page Number
Description
64 x 4 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ... 5-1
64 x 5 Cascadable FIFO ............... , ................. : . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 4 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 5 Cascadable FIFO ... . .. .. . . . .. .. . .. . . . . .. .. .. .. .. .. .. .. .. . .. .. . . .. .. .. . .. 5-1
64 x 8 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -12
64 x 9 Cascadable FIFO .... .. .. . . . .. .. . .. . . . . .. . . . .. . .. .. . .. .. .. .. .. .. .. . . . ... 5 -12
256 x 9 Cascadable FIFO ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 26
512x9CascadabieFIFO ...................................................... 5-26
512 x 9 Cascadable FIFO ... . .. . . . . .. .. . .. . . . . .. .. .. .. .. .. . .. .. .. . .. . . . . . .. .. .. 5 - 26
5-26
lK x 9 Cascadable FIFO
5-26
lK x 9 Cascadable FIFO
5-26
2K x 9 Cascadable FIFO
5-26
2K x 9 Cascadable FIFO
5-26
4K x 9 Cascadable FIFO
4K x 9 Cascadable FIFO
5-26
64 x 9 Synchronous FIFO ...................................................... 5-48
256 x 9 Synchronous FIFO ........... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -48
512 x 9 Synchronous FIFO ......................... '.' . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -48
lK x 9 Synchronous FIFd ... ;.................................................. 5-48
2Kx 9 Synchronous FIFO ..................................................... 5-48
4Kx 9 Synchronous FIFO ...................................................... 5-48
8Kx 9 Synchronous FIFO ..................................................... 5-48
64 x 18 Synchronous FIFO ..................................................... 5-67
256 x 18 Synchronous FIFO .................................................... 5-67
512 x 18 Synchronous FIFO .................................................... 5-67
lKx 18 Synchronous FIFO .................................................... 5-67
2Kx 18 Synchronous FIFO .................................................... 5-67
4Kx 18 Synchronous FIFO ....................... '............................. 5-67
Bidirectional2K x 9 FIFO ..................................................... 5-86
Clocked 512 x 9 FIFO ........................................................ 5-99
Clocked 2K x 9 FIFO .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-99
512x 9 Cascadable Clocked FIFO with Progl-ammable Flags ....................... 5-115
2K x 9 Cascadable Clocked FIFO with Programmable Flags. . . . . . . . . . . . . . . . . . . . . . .. 5 -115
512 x 18 Cascadable Clocked FIFO with Programmable Flags ...................... 5-138
lK x 18 Cascadable Clocked FIFO with Programmable Flags. . . . . . . . . . . . . . . . . . . . . .. 5 -138
2K x 18 Cascadable Clocked FIFO with Programmable Flags. . . . . . . . . . . . . . . . . . . . . .. 5 -138
Cascadable 8K x 9 FIFO ..................................................... 5 -158
Cascadable 16Kx 9 FIFO .................................................... 5-158
Cascadable 32K x 9 FIFO .................................................... 5 -158
8K x 9 FIFO with Programmable Flags ......................................... 5 -171
16Kx 9 FIFO with Programmable Flags ........................................ 5-171
32K x 9 FIFO with Programmable Flags ........................................ 5 -171
CY7C401/CY7C403
CY7C402/CY7C404
=s.:rcYPRESS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Vbl~e ........................ >2001V
(per MI»STD-883, ethod 3015)
Latch-Up Current ........................... >200 rnA
Stor1lge Temperature .................. -65°C to +150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential ........ -O.SV to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.SV to + 7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Output Current, into Outputs (LOW) .. . . . . . . . . . . .. 20 rnA
Operating Range
Range
Commercial
Military[lj
Ambient
Thmperature
O°Cto +70°C
Vee
SV ±1O%
-SSoC to +125°C
SV ±10%
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)[2j
7C40X": 10, 15, 25
Parameter
Description
Thst Conditions·
VOH
Output HIGH Voltage
Vee = Min.; IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vce = Min., IOL = 8.0 mA
VIR
Input HIGH Voltage
VlL
Input LOW Voltage
IJX
Input Leakage Current
VCD[3j
Input Diode Clamp Voltage[3]
loz
Min.
Max.
Unit
2.4
V
0.4
V
2.0
6.0
V
- 3.0
0.8
V
GND.s. Vl.s. Vcc
-10
+10
IlA
Output Leakage Current
GNb .s. VOUT.s. Vcc, Vcc = 5.5V
Output Disabled (CY7C403 and CY7C404)
- 50
+50
IlA
los
Output Short Circuit Current[4]
Vcc = Max., VOUT = GND
- 90
rnA
Icc
Power Supply Current
I Commercial
75
rnA
I Military
90
rnA
VCC = Max., lOUT = 0 rnA
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
CrN
COUT
Test Conditions
AC Test Loads ~nd Waveforms
5V TIR1437Q.
OUTPUT
INCLUDING
JIG AND
SCOPE
.1.
-
_
-
pF
pF
ALL INPUT PULSES
OUTPUT
272Q
7
Unit
3.0V----
5V TIR1437Q
R2
30 pF
Max.
S
TA = 25°C, f = 1 MHz,
Vcc= 4.SV
90%
R2
5 pF
INCLUDING
JIG AND
SCOPE
(a) Normal Load
.1.
-
GND
272Q
_
-
(b) High-Z Load
C401·7
C401-6
Equivalent to: THEVENIN EOUIVALENT
167Q
OUTPUT
o-----wv----o 1.73V C401-8
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
information.
3. The CMOS process does not provide a clamp diode. However, the
FIFO is insensitive to - 3V dc input levels aod - SV undershoot pulses
oftess than 10 ns (measured at 50% output).
4.
5.
S-2
For test purposes, not more thao one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Thsted initially aod after any design or process chaoges that may affect
these parameters.
~YPRESS
CY7C401/CY7C403
CY7C402/CY7C404
Operational Description
Concept
Unlike traditional FIFOs, these devices are designed using a dualport memory, read and write pointer, and control logic. The read
and write pointers are incremented by the SO and SI respectively.
The availability of an empty space to shift in data is indicated by the
IR signal, while the presence of data at the output is indicated by
the OR signal. The conventional concept of bubble-through is absent. Instead, the delay for input data to appear at the output is the
time required to move a pointer and propagate an OR signal. The
output enable (OE) signal provides the capability to OR tie multi, pie FIFOs together on a common bus.
be aware of a window of time which follows the initial rising edge of
the OR signal, during which time the SO signal is not recognized.
This condition exists only at high-speed operation where more than
one SO may be generated inside the prohibited window. This condition does not inhibit the operation of the FIFO at full-frequency
operation, but rather delays the full 25-MHz operation until after
the window has passed.
There are several implementation techniques for managing the
window so that all SO signals are recognized:
1. The first involves delaying SO operation such that it does not
occur in the critical window. This can be accomplished by causing a fixed delay of 40 ns "iuitiated by the SI signal only when
the FIFO is empty" to inhibit or gate the SO activity. However,
this requires that the SO operation be at least temporarily synchronized with the input SI operation. In synchronous applications this may well be possible and a valid solution.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset (MR)
signal. This causes the FIFO to enter an empty condition signified
by the OR signal being LOW at the same time the IR signal is
HIGH. In this condition, the data outputs (DOo - DOn) will be in
a LOW state.
Shifting Data In
Data is shifted in on the rising edge of the SI signal. This loads input data into the first word location of the FIFO. On the falling
edge of the SI signal, the write pointer is moved to the next word
position and the IR signal goes HIGH, indicating the readiness to
accept new data. If the FIFO is full, the IR will remain LOW until
a word of data is shifted out.
Shifting Data Out
Data is shifted out of the FIFO on the falling edge ofthe SO signal.
This causes the internal read pointer to be advanced to the next
word location. If data is present, valid data will appear on the outputs and the ORsignalwillgo HIGH. Ifdata is not present, the OR
signal will stay LOW indicating the FIFO is empty. Upon the rising
edge of SO, the OR signal goes LOW. The data outputs of the
FIFO should be sampled with edge-sensitive type D flip-flops (or
equivalent), using the SO signal as the clock input to the flip-flop.
Bubble-Through
Tho bubble-through conditions exist. The first is when the device is
empty. After a word is shifted into an empty device, the data propagates to the output. After a delay, the OR flag goes HIGH, indicating valid data at the output.
The second bubble-through condition occurs when the device is
full. Shifting data out creates an empty location that propagates to
the input. After a delay, the IR flag goes HIGH. If the SI signal is
HIGH at this time, data on the input will be shifted in.
Possible Minimum Pulse Width Violation at the Boundary
Conditions
If the handshaking signals IR and OR are not properly used to generate the SI and SO signals, it is possible to violate the minimum
(effective) SI and SO positive pulse widths at the full and empty
boundaries.
When this violation occurs, the operation of the FIFO is unpredictable. It must then be reset, and all data is lost.
2. Another solution not uncommon in synchronous applications
is to only begin shifting data out of the FIFO when it is more
than half full. This is a common method of FIFO application,
as earlier FIFOscould not be operated at maximum frequency
when near full or empty. Although Cypress FIFOs do not have
this limitation, any system designed in this manner will not encounter the window condition described above.
3. The window may also be managed by not allowing the first SO
signal to occur until the window in question has passed. This
can be accomplished by delaying the SO 40 ns from the rising
edge of the initial OR signal. This however involves the requirement that this only occurs on the first occurrence of data
being loaded into the FIFO from an empty condition and
therefore requires the knowledge of IR and SI conditions as
well as SO.
4. Handshaking with the OR signal is a third method of avoiding
the window in question. With this technique the rising edge of
SO, or the fact that SO signal isHIGH,wili cause the OR signal
to go Ww. The SO signal is not taken LOW again, advancing
the internal pointer to the next data, until the OR signal goes
LOW. This ensures that the SO pulse that is initiated in the window will be automatically extended long enough to be recognized.
5. There remains the decision as to what signal will be used to
latch the data from the output of the FIFO into the receiving
source. The leading edge of the SO signal is most appropriate
because data is guaranteed to be stable prior to and after the
SO leading edge for each FIFO. This is a solution for anynumber of FIFOs in parallel.
Any of the above solutions will ensure the correct operation of a
Cypress FIFO at 25 MHz. The specific implementation is left to
the designer and is dependent on the specific application needs.
Application of the 7C403-2517C404-25 at 25 MHz
Application of the CY7C403 or CY7C404 Cypress CMOS FIFOs
requires knowledge of characteristics that are not easily specified
in a datasheet, butwhich are necessary for reliable operation under
all conditions, so we will specify them here.
When an empty FIFO is filled with initial information at maximum
"shift in" SI frequency, followed by immediate shifting out of the
data also at maximum "shift out" SO frequency, the designer must
5-4
CY7C401/CY7C403
CY7C402/CY7C404
rilF7crPRESS
Switching Waveforms (continued)
Bubble Tbrough, Data In To Data Out Diagram
.J/
SHIFT IN _ _ _
SHIFT OUT . . . /
14---OUTPUT READY
DATA OUT
leT
-----+---
---------->k
'------ISOR
----------------~
C401·12
Master Reset Timing Diagram
I---MAsTER RESET
tpMR - - - -
~
.Ill'
10lR
INPUT READY
~
tOOR
~
OUTPUT READY
tOSI
SHIFT IN
}
",,1._-- tLZMR ---~~
DATA OUT
----------------~--------------------
Output Enable Timing Diagram
OUTPUT ENABLE
C401·13
5
_________I~HZ~OE
DATA OUT - - _ _ _ _ _ _ _ _
~
_~~OE={-----------
NOTE 10
C401·14
5-6
~YPRESS
CY7C401/CY7C403
CY7C402/CY7C404
FIFO Expansion(13,14,15, 16,17j
128 x 4 Application[18j
SHIFT IN
INPUT READY
DA,.,,{
51
IR
~
01 0
01 1
01 2
013
"MR
OR
SO
000
001
002
003
OUTPUT READY
SHIFT OUT
} DA"O~
MRG-------~~------------~
0401·16
192 x 12 Application[19j
SHIFT OUT
-
IR
SO
51
OR
000
010
01 1
001
012
002
013 fVfFi00 3
IR
51
01 0
01 1
012
013 fiiII'i
1
)'
COMPOSITE
INPUT READY
SHIFT IN
-
IR
51
01 0
01 1
01 2
013 Iiim
r
IR
51
010
01 1
01 2
013 MR
r
SO
OR
000
001
002
003
SO
OR
000
001
002
003
so
SO
OR
000 '-001 r002 r003 , -
1
IR
SO
51
OR
000
010
01 1
001
012
002
013 fVfFi00 3
1
OR
000
001
002
003
IR
51
01 0
01 1
01 2
013 fiiII'i
IR
SO ~
51
OR
000 r01 0
001 r01 1
002 i 01 2
013 fVfFi00 3 '--
COMPOSITE
OUTPUT READ
L-.r-\
r-L--'
1
so
IR
51
010
01 1
012
013 fiiII'i
OR
000
001
002
003
IR
51
010
01 1
01 2
013 l'iiIFI
so f - -
OR
000 ,001 i 002 i 003 i -
MR
r
~
C401-17
Notes:
13. When the memory is empty, the last word read will remain on the outputs until the master reset is strobed or a new data word bubbles
through to the output. However, OR will remain LOW, indicating data
at the output is not valid.
14. WhentheoutputdatachangesasaresultofapulseonSO,theORsignal always goes LOW before there is any change in output data, and
stays LOW until the new data has appeared on the outputs. Any1ime
OR is HIGH, there is valid, stable data on the outputs.
IS. If SO is held HIGH while the memory is empty and a word is written
into the input, that word will ripple through the memory to the output.
OR 'will go HIGH for one internal cycle 1
20-Pin Square Le,adless Chip Carrier
Package
Name
Package 1YPe
Speed
(MHz)
Pac\qtge
Name
Ordering Code
CY7C404-100C
16-~ad
(300-Mil) ~rDIP
(300-Mil) CerDIP
(300-Mil) CerDIP
Operating
Range
COl]IID.ercial
Military
Commercial
Military
Commercial
Military
Op~rating
D4
18-Lead (300-Mil) CerDIP
18-Lead (300-Mil) Molded DIP
CY7C404-lOPC
P3
CY7C404-100MB
04
18-Lead (300-Mil) CerDIP
CY7C404-lOLMB
L61
20-Piri Square Leadless Chip Carrier
CY7C404-150C
Q4
18-Lead (300-Mil) CerOIP
CY7C404".15PC
18-Lead (300-Mil) Molded DIP
CY7C4Q4-150MB
f3
04
,.
CY1C404-15LMB
L61
20-Pin Square Leadless Chip Carrier
CY7C404-~OC
04
l~~Lead
CY7C404-25PC
P3
lS-Lead (300-Mil) Molded DIP
lS-Lead (300-Mil) CerDIP
(300-Mil) CerDIP
p'7C404-250MB
04
18-Lead (300-Mil) CerDIP
CY7C404-25LMB
L61
20-Pin Square Leadless Chip Carrier
5-10
Rapge
Commercial
Military
CommerCial
Military
Commercial
Military
CY7C408A
CY7C409A
64 X 8 Cascadable FIFO
64 X 9 Cascadable FIFO
Features
• 64 x 8 and 64 x 9 tirst-in tirst-out
(FIFO) buffer memory
• 35-MHz shift in and shift out rates
• Almost Full/Almost Empty and Half
FoIl flags
• Dual-port RAM architecture
• Fast (50-ns) bubble-through
• Independent asynchronous inputs
and outputs
• Output enable (CY7C408A)
• Expandable in word width and FIFO
depth
• 5V ::!:10% supply
• TTL compatible
• Capable of withstanding greater than
2001V electrostatic discharge voltage
• 300-mil, 28-pin DIP
Functional Description
The CY7C408A and CY7C409A are
64-word deep by 8- or 9-bit wide first-in
first-out (FIFO) buffer memories. In
addition
to the industry-standard
handshaking signals, almost full/almost
empty (AFE) and half full (HF) flags are
provided.
APE is HIGH when the FIFO is almost full
or almost empty, otherwise APE is LOW
HF is HIGH when the FIFO is half full,
otherwise HF is LOW
The CY7C408A has an output enable
(OE) function.
The memory accepts 8- or 9-bit parallel
words at its inputs (010 - DIs) under the
control of the shift in (SI) input when the
input ready (IR) control signal is HIGH.
The data is output, in the same order as it
was stored, on the 000 - DOs output pins
under the control of the shift out (SO)
input when the output ready (OR) control
signal is HIGH. If the FIFO is full (IR
LOW), pulses atthe SI input are ignored; if
the FIFO is empty (OR LOW), pulses at
the SO input are ignored.
The IR and OR signals are also used to
connect the FIFOs in parallel to make a
wider word or in series to make a deeper
buffer, or both.
Parallel expansion for wider words is
implemented by logically ANDing the IR
and OR outputs (respectively) of the
individual FIFOs together (Figure 5). The
AND operation insures that all of the
FIFOs are either ready to accept more
data (IR HIGH) or ready to output data
(OR HIGH) and thus compensate for
variations in propagation delay times
between devices.
Serial expansion (cascading) for deeper
buffer memories is accomplished by
connecting the data outputs of the FIFO
closest to the data source (upstream
device) to the data inputs of the following
(downstream) FIFO (Figure 4). In
addition, to insure proper operation, the
SO signal of the upstream FIFO must be
connected to the IR output of the
downstream FIFO and the SI signal of the
downstream FIFO must be connected to
the OR output of the upstream FIFO. In
this serial expansion configuration, the IR
and OR signals are used to pass data
through the FIFOs.
Reading and writing operations are
completely asynchronous, allowing the
FIFO to be used as a buffer between two
digital machines of widely differing
operating frequencies. The high shift in
and shift out rates of these FIFOs, and
their high throughput rate due to the fast
bubblethrough time, which is due to their
dual-port RAM architecture, make them
ideal for high-speed communications and
controllers.
Logic Block Diagram
Pin Configurations
Vee
Mll
AFE
81
WRITE POINTER
AFE
IR
WRITE MULTIPLEXER
HF
HF
IR
D?o
DID
80
81
OR
DID
DOD
01,
DO,
GND
GND
MEMORY
ARRAY
017
(7C409A) 01.
007
01,
01,
DO,
DO. (7C409A)
01.
015
01.
017
DO.
OE(7C409A)
READ MULTIPLEXER
OR
IilI!
READ POINTER
80
DO,
005
DO.
007
UE(7C408A)
DO. (7C409A)
(7C409A) NC
(7C409A) 01.
C409A-3
C408A·1
Ci5~!l:~>8~~
DID
Flag Definitions
01,
GND
HF
L
L
H
H
AFE
H
L
01,
01,
01.
Words Stored
0-8
L
9 - 31
32 - 55
H
56 - 64
Dis
4:3 2L~282726
25
24
23
7C409A
22
7C409A
21
20
19
11
12131415161718
5
6
7
8
9
10
OR
DOD
DO,
GND
DO,
DO,
DO.
ofQ5gCO~tg8CD81O
z@
5-12
C409A·2
CY7C408A
CY7C409A .
Q:YPRESS
Switching Characteristics Over the Operating Rangel3, 6]
Parameter
fo
Description
Operating Frequency
7C40SA-15
7C409A-15
Test
Conditions
Min.
Note 7
Max.
7C408A-25
7C409A-25
Min.
15
Max.
7C408A-35
7C409A-35
Min.
25
Max.
Unit
35
MHz
tpHSI
SI HIGH Time
Note 7
23
11
9
ns
tpLSI
SILOWTime
Note 7
25
24
17
ns
tSSI
Data Set-Up to SI
NoteS
0
0
0
ns
tHSI
Data Hold from SI
NoteS
30
20
12
ns
tOLIR
Delay, SI HIGH to IR LOW
35
21
15
ns
tOHIR
Delay, SI LOW to IR HIGH
40
23
16
ns
tPHSO
SO HIGH Time
Note 7
23
11
9
tpLSO
SO LOW Time
Note 7
25
24
17
tOLOR
Delay, SO HIGH to OR LOW
35
21
15
ns
tOHOR
Delay, SO LOW to OR HIGH
40
23
16
ns
tSOR
Data Set-Up to OR HIGH
0
0
0
tHSO
Data Hold from SO LOW
0
0
0
tBT
Fall-through, Bubble-back Time
10
tSIR
Data Set-Up to IR
Note 9
5
5
5
ns
tHiR
Data Hold from IR
Note 9
30
20
20
ns
tpIR
Input Ready Pulse HIGH
Note 10
6
6
6
ns
tpOR
Output Ready Pulse HIGH
Note 11
6
6
6
tOLZOE
OE LOW to LOW Z (7C40SA)
Note 12
35
30
25
ns
tOHZOE
OE HIGH to HIGH Z (7C40SA)
Note 7
35
30
25
ns
tOHHF
SI LOW to HF HIGH
.65
55
45
ns
tOLHF
SO LOW to HF LOW
65
55
45
ns
tOLAFE
SO or SI LOW to APE LOW
65
55
45
ns
tOHAFE
SO or SI LOW to AFE HIGH
65
55
45
ns
tpMR
tOSI
MR Pulse Width
MR HIGH to SI HIGH
tOOR
MR LOW to OR LOW
55
45
35
ns
tom
MR LOW to IR HIGH
55
45
35
ns
tLZMR
55
45
35
ns
55
45
35
ns
tHF
MR LOW to Output LOW
MR LOW to APE HIGH
MR LOW to HF LOW
55
45
35
ns
tOD
SO LOW to Next Data Out Valid
2S
20
16
ns
tAFE
Note 13
Note.:
6. Thst conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5Y and output loading of the specified ImJIoH and
30-pF load capacitance, as in parts (a) and (b) of ACThst Loads and
Waveforms.
7. lifo ~ (tpHSI + tpLS!), lifo ~ (tpHSO + tpLSO).
8. tSSI and tHSI apply when memory is not full.
9. tSIR and tHIR apply when memory is full, 81 is high and minimum
bubble-through (tBT) conditions exist.
10. At any given operating condition tpIR ~ (tPHSO required).
11. At any given operating condition tpOR ~ (tpHSI required).
65
10
60
10
55
45
35
25
10
10
ns
ns
ns
ns
50
ns
ns
ns
ns
12. tDHZOE and tDLZOE are specified with CL = 5 pF as in part (b) of AC
Thst Loads and Waveforms. tDHZOE transition is measured ±500.mY
from steady-state voltage. tDLWE transition is measured ±100 mY
from steady-state voltage. These parameters are gnaranteed and not
100% tested.
13. All data outputs will be at LOW level after reset goes HIGH until data
is entered into the FIFO.
5-14
CY7C408A
CY7C409A
1s~YPRESS
Switching Waveforms (continued)
Data In Timing Diagram
----------. .~--------- lffo
----------~
~--"'"
SHIFT IN
INPUT READY
DATA IN
AFE
(LOW)
IDHHFf___________
HF
C408A-9
Data Out Timing Diagl"/lm
SHIFT OUT
OUTPUT READY
DATA OUT
HF
AFE
(LOW)
C408A-10
Output Enable (CY7C408A only)
OUTPUT ENABLE
DATA OUT
C408A-11
Notes:
16_ FIFO contains 31 words_
17_ FIFO contains 32 words_
5-16
CY7C408A
CY7C409A
.;rcYPRESS
Switching Waveforms (continued)
Fall-Through, Data In to Data Out Diagram
"'----1'
SHIFT IN
_ _
}---,--"
OUTPUT READY
DATA OUT
- - - - f ~SOR
.
IpOR
_
=1
~
"'"'----
----------------~
C40SA-15
Master &ese~ Timing Diagram
MASTERRESET
f.-~~
IpMR - - -
{
IoIR
I"
INPUT READY
IOOR
~i'..
OUTPUT READY
IOSI
SHIFT IN
}
ILZMR
~
DATA OUT
HF
_IHF
AFE
-IAFE
""~
C408A-16
Note:
21. FIFO is empty.
5-18
CY7C408A
CY7C409A
QYPRESS
Secondly, the frequency at the cascade interface is less than the 35
MHz rate at which the external clocks may operate. Therefore, the
fITst device has its data shifted in faster than it is shifted out, and
eventually this device becomes momentarily full. When this
occurs, the maximum sustainable external clock frequency
changes from 35 MHz to the cascade interface frequency.L28]
When data packets[29] are transmitted, this phenomenon does not
occur unless more than three FIFOs are depth cascaded. For
example, if two FIFOs are cascaded, a packet of 127 (=2 X 63 +
1) words may be shifted in at up to 35 MHz and then the entire
packet may be shifted out at up to 35 MHz.
Cascading the 7C408/9A-35 Above 25 MHz
First, the capacity ofN cascaded FIFOs is decreased from N X 64
to (N X 63) + 1.
If cascaded FlFOs are to be operated with an external clock rate
greater than 25 MHz, the interface IR signal must be inverted
before being fed back to the interface SO pin (Figure 3 ) . Tho things
should be noted when this configuration is implemented.
First. the capacity ofN cascaded FlFOs id decreased from N X 64
to(N X 63)+1.
EMPTY
FULL
64
SHIFT OUT
56
63
55
54
31
32
30
9
1
7
8
...lL
JLSL...
HF
AFE
C408A-1B
Figure 2. Shifting Words Out
,---- ... ------ .... --------_ ..
_-_ ... ------ .. --_ .... -----
A
IRX
..---,,-,IR'---jIR
SOx
SI
OR 1---.-jSI
Six ,--.-jSI
OR 1--_--,
OR 1------tSI
ORx
DOUTX
2
• • •
N
UPSTREAM
DOWNSTREAM-------.
..
C40BA·19
Figure 3. Cascaded Configuration Above 25 MHz
128 X 9 Configuration
HF/AFE
HF/AFE
SHIFTIN_ SI
IR
INPUT READY
DATA IN
----
--
OR
SO
SI
IR
OR
Dlo
DI1
DOo
Dlo
DOo
D01
DI1
DI2
D02
DI2
D01
D02
DI3
DI4
DI5
D03
D04
D05
DI3
DI4
DI6
D06
DI6
DI7
DI8
D07
D08
DI7
DI8
IiiIR
OUTPUT READY
SHIFT OUT
SO
D03
D04
D05
DI5
JM!
~ -----+----------------~
DATA OUT
D06
D07
D08
C40BA-20
Figure 4. Cascaded Configuration at or below 25 MHz[22, 23, 24, 25, 26]
5-20
CY7C408A
CY7C409A
~YPRESS
If data is to be shifted out simultaneously with the data being
shifted in, the concept of ''virtual capacity" is introduced. Virtual
capacity is simply how liuge a packei of data can be shifted in at a
fIXed frequency, e.g., 35 MHz, simultaneously with data being
shifted out at any given frequency. Figure 6 is a graph of packet
sizel30] vs. shift out frequency (£SOx> for two different values of
shift in frequency (fsW when two FIFOs are cascaded.
The exact complement of this occurs if the FIFOs initially contain
data and a high shift out frequency is to be maintained, i.e., a 35
MHz fSOxcan be sustained when reading data packets from devices
cascaded two or three deepJ31] If data is shifted in simultaneously,
Figure 6 applies with fSIx and £SOx interchanged.
400
350
~ 300
ISlx = 30 MHz
o
~250
~
200
I-
150
~if
" ~.
~
~
/
~
ISlx
100
50
o
o
4
= 35 MHz
8 12 16 20 24 28 32 36
OUTPUT RATE
(Isoxl OF BOnOM FIFO (MHz)
C408A-22
Figure 6. Virtual Capacity vs. Output Rate for 'l\vo FIFOs Cascaded Using an Inverter
NOles:
28. Because the data throughput in the cascade interface is dependent on
the inverter delay, it is reconunended that the fastest available inverter
be used.
29. nansmission of data packets assumes that up to the maximum cumulative capacity of the FIFOs is shifted in without simultaneous shift out
clock occurring. The complement of this holds when data is shifted out
as a packet.
30. These are typical packet sizes using an inverter whose delay is 4 ns.
31. Only devices with the same speed grade are specified to cascade together.
5-22
CY7C408A
CY7C409A
.
~YPRESS
.'~
Ordering Information
Frequency
(MlIz)
15
25
35
Frequency
(MHz)
15
25
35
Ordering Code
Package
Name
Package 1)pe
CY7C408A-15PC
P21
28-Lead (300-MiI) Molded DIP
CY7C408A-15VC
V21
28-Lead (300-MiI) Molded SOJ
CY7C408A-15DMB
D22
28-Lead (300-MiI) CerDIP
CY7C408A -15LMB
L64
28-Square Leadless Chip Carrier
CY7C408A-25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C408A-25VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C408A-25DMB
D22
28-Lead (300-Mil) CerDIP
CY7C408A -25LMB
L64
28-Square Leadless Chip Carrier
CY7C408A - 35PC
p21
28-Lead (300-Mil) Molded DIP
CY7C408A-35VC
V21
28-Lead (300-MiI) Molded SOJ
Ordering Code
Package
Name
Package1)~e
CY7C409A -15PC
P21
28-Lead (300-MiI) Molded DIP
CY7C409A-15VC
V21
28-Lead (300-MiI) Molded SOJ
CY7C409A-15DMB
D22
28-Lead (300-MiI) CerDIP
CY7C409A-15LMB
L64
28-Square Leadless Chip Carrier
CY7C409A-25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C409A -25VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C409A-25DMB
022
28-Lead (300-Mil) CerDIP
CY7C409A-25LMB
L64
28-Square Leadless Chip Carrier
CY7C409A-35PC
P21
28-Lead (300-Mil) Molded DIP
CY7C409A - 35VC
V21
28-Lead (300-Mil) Molded SOJ
5-24
Opemting
Range
Commercial
Military
Commercial
Military
Commercial
Opemting
Range
Commercial
Military
Commercial
Military
Commercial
CY7C419/21/25/29/33
256 X 9,512 X 9, 1Kx 9, 2Kx 9,
4Kx 9 Cascadable FIFO
Features
• 256 x 9, S12 x 9, 1,024 x 9, 2048 x 9,
and 4096 x 9 FIFO buffer memory
• Dual-port RAM cell
• Asynchronous read/write
• Hiab-speed 50,0-MHz read/Write
jrufepen!lllnt of~eptb!widtb
• Low operating pOWlr
-Icc! = 3S'1nA '
• Half Full flag in standalone
• Empty and fuU flags
• Retransmit in standalone
• Ewaqdable in ~dth'and depth
• Parallel cascade minimizes
bubble-through
• SV ± 10% supply
• 300-'m1i DIP packaging
• 7x7TQFP
'
• 300-mil SOJ packaging
• TTL compatible
• Three-state outputs
• Pin compatible and functional
eqUivalent to IDT7200, IDT7201,
IDT7202, IDT7203, and IDT7204
Logic Block Diagram
Functional Description
data outputs go to the high-impedance
state when R is HIGH.
The CY7C419, CY7C420/1, CY7C424/5,
CY7C428/9, and CY7C432/3 are first-in
firSt-out (FIFO) memories offered in
600-mil wide and 300-mil wide packages.
They are, respectively, 256, 512, 1,024,
2,048, and 4,096 words by 9-bits wide.
Each FIFO memory is organized such that
the data is read in the same sequential order that it was written. Full and Empty
flags are provided to prevent overrun and
underrun. Three additional pins are also
provided to facilitate unlimited expansion
in width, depth, or both. The depth expansion technique steers the control signals
ITom one device to another in parallel, thus
eliminating the serial addition of propagation delays, so that throughput is not reduced. Data is steered in a similar manner.
A Half Full (RF) output flag is provided
that is valid in the standalone and width expansion configurations. In the depth expansion configuration, this pin provides
the expansion out (XO) information that is
used to tell the next FIFO that it will be activated.
In the standalone and width expansion
configurations, a LOW on the retransmit
(lIT) input causes the FIFOs to retransmit
the data. Read enable (R) and write enable (W) must both be HIGH during retransmit, and then R is used to access the
data.
The CY7C419, CY7C420, CY7C421,
CY7C424,
CY7C425,
CY7C428,
CY7C429, CY7C432, and CY7C433 are
fabricated using an advanced 0.65-micron
P-well CMOS technology. Input ESD protection is greater than 2000V and latch-up
is prevented by careful layout and guard
rings.
The read and write operations may be
asynchronous; each can occur at a rate of
50.0 MHz. The write operation occurs
when the write (VV) signal is LOW. Read
occurs when read (R:) goes Ww. Thenine
Pin Configurations
DATA INPUTS
(Do-Dal
PLCCILCC
DIP
Top View
c(f)oCOI~
02
0,
4
3
Top View
fi: >8 o"
W
vee
,.
D8
D3
D2
D,
Do
D4
D5
D6
D7
2 '1 1
5
6
D.
07
NO
FF
!'[JRT
70419
70421/5/9
70433
IIilI!
EF
00
10
0,
12
13
21
14 151617 181920
XOiAF
d" d"!!!
DATA OUTPUTS
(007 0 ai
IIilI!
'"
~ 10:
0'" r:f'
0420-2
07
O.
XI
FI'
00
0,
02
03
08
GNQ
Fl:/Ai
lim
EF
XO/RF
07
06
05
04
R
!'[JRT
C42O-3
I---t--... ~
0420-1
5-26
CY7C419/21/25/29/33
.rcYPRESS
Electrical Characteristics Over the Operating RangdZ] (continued)
Parameter
Icc
Description
Operating Current
Test Conditions
Vee = Max., Com')
lOUT = ornA
Mil/lnd
f= fMAX
7C419-10
7C419-15
7C421-10
7C421-15
7C425-10
7C425-15
7C429-10
7C429-15
7C419-20
7C420-20
7C421-20
7C424-20
7C425-20
7C428-20
7C429-20
7C433-10
7C433-15
7C433-20
7C419-25
7C420-25
7C421-25
7C424-25
7C425-25
7C428-25
7C429-25
7C432-25
7C433-25
Min. Max. Min. Max. Min. Max. Min. Max. Unit
85
65
55
50
rnA
100
90
80
Icc!
Operating Current
Vee = Max., Com')
lOUT = ornA
F=20MHz
35
35
35
35
rnA
ISB!
Standby Current
AI) Inputs VIHMin.
10
10
10
10
rnA
15
15
15
5
5
5
8
8
8
Power-Down Current
ISB2
Com')
Mil/Ind
AI) Inputs ~ Com')
Vee"'; 0.2V
Mil/Ind
5
rnA
Electrical Characteristics Over the Operating RangdZ] (continued)
7C419-30
7C420-30
7C421-30
7C424-30
7C425-30
7C428-30
7C429-30
7C432-30
7C433-30
Parameter
Description
Max.
Units
35
35
rnA
Mil/Ind
75
70
65
Com')
35
35
35
rnA
Com')
10
10
10
rnA
Mil
15
15
15
Com')
5
5
5
Mil
8
8
8
Min.
Operating Current
Vee = Max.,
lOUT = ornA
f = fMAX
Com')
Icc!
Operating Current
Vee = Max.,
lOUT = ornA
F=20MHz
ISB!
Standby Current
AI) Inputs
VIHMin.
ISBZ
Power-Down Current
AIllnputs~
Vee - 0.2V
7C419-65
7C420-65
7C421-65
7C424-65
7C425-65
7C428-65
7C429-65
7C432-65
7C433-65
40
Test Conditions
Icc
=
7C419-40
7C420-40
7C421-40
7C424-40
7C425-40
7C428-40
7C429-40
7C432-40
7C433-40
Max.
Min.
Max.
Min.
rnA
Capacitance[5]
Parameter
CIN
COUT
Notes:
1.
2.
3
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee
TA is the "instant on" case temperat~re.
See the last page of this specification for Group A subgroup testing information.
VldMin.) = -2.0V for pulse durations ofless than 20 ns.
= 4.5V
4.
5.
5-28
Max.
6
6
Unit
pF
pF
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Thsted initially and after any design or process changes that may affect
these parameters.
~YPRESS
CY7C419/21/25/29/33'
Switching Characteristics Over the Operating Range[6, 7] (continued)
7C419-10
7C419-15
7C421-10
7C421-15
7C42S-10
7C42S-1S
7C429-10
7C429-15
7C433-10
Parameter
tEFL
Description
MRtoEFWW
Min.
Max.
20
7C433-1S
Min.
Max.
25
7C419-20
7C420-20
7C421-20
7C424-20
7C425-20
7C428-20
7C429-20
7C433-20
Min.
Max.
30
7C419-25
.7C420-25
7C421-25
7C424-25
7C425-2S
7C428-2S
7C429-25
7C432-25
7C433-25
MiIi.
Max.
35
Unit
ns
tHFH
MRtoHFHIGH
20
35
ns
MRtoFFHIGH
20
2S
2S
30
tFFH
30
35
ns
tREF
tRFF
Read LOW to EF LOW
10
15
20
25
ns
Read HIGH to FF HIGH
10
15
20
25
ns
tWEF
Write HIGH to EF HIGH
10
15
20
25
ns
tWFF
Write LOW to FJi LOW
10
15
20
25
ns
tWHF
Write LOW to HF LOW
10
15
20
25
ns
tRHF
Read HIGH to HF HIGH
10
15
20
25
ns
tRAE
Effective. Read from Write HIGH
10
15
20
25
tRPE
Effective Read Pulse Width After EF HIGH
tWAF
Effective Write from Read HIGH
tWPF
Effective Write Pulse Width After FF HIGH
tXOL
Expansion Out LOW Delay from Clock
10
15
20
txoH
Expansion Out HIGH Delay from Clock
10
15
20
15
10
10
5-30
15
15
10
2S
20
20
25
2S
20
ns
ns
ns
ns
2S
2S
ns
ns
CY7C419/21/25/29/33
Switching Waveforms
Asynchronous Read and Write
R--~
Qo-Qa------------{
i
w--E~
Do-De
r; Iso
-------1<1<..
~4~/""--)jll------------«
»-----
tHO
DATA VALID
~
DATA VALID
C42O-8
Master Reset
.....- - - - tMRSC[ll] --------~
__________
~~------tpMR ------~----~------------------
C420-9
Half-Full Flag
HALF FULL
HALF FULL
HALF FULL +1
w
/
~
"'
tWHF'"
-
tRHF
~
ItC420-10
Notes:
10. W and R ~ V IH around
the rising edge of MR.
11. tMRSC = tpMR
5-32
+ tRMR.
~YPRESS
CY7C419/21/25/~9/33
Switching Waveforms (coQtinued)
Empty Flag and Read Data F1ow-Throngh Mode
DATA IN
w--+-~
~--~--------------+---'I
DATA OUT
--~--......,-----4~r;~)()(~'''''----C420-14
Full Flag and Write Data Flow-Through Mode
w
~-~~------------~--~
DATAIN
DATA OUT
tHO
--1~----~--~----~~~~~~~-------------
----21
V21
022
L55
A32
J65
P21
V21
Package 'Jype
32-Pin Thiri Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (30d-MiI) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Pin Thin Plastic Quad Flatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip ~arrier
28-Lead (300-Mil) Molded DIP
28-Lead (3OO-Mil) Molded SOJ
Operating
Range
Commercial
Commercial
Industrial
28-Lead (3OO-Mil) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
A32
J65
P21
V21
J65
P21
V21
022
L55
A32
J65
28-Lead (300-Mil) Molded DIP
28-Lead (3OO-Mil) Molded SOr
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-Mil) Mold~d DIP
28:Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
Industrial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (3OO-Mil) CerDIP
Military
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leade~ Chip Carrier
P21
V21
J65
P21
V21
D22
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-~ead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
L55
32-Pin Rectangular Leadless Chip Carrier
J65
P21
V21
022
L55
5-42
Industrial
Military
~YPRESS
CY7C419/21/25/29/33
Ordering Information (continued)
Speed
(ns)
10
Ordering Code
CY7C429-1OAC
CY7C429-10JC
15
CY7C429-1OPC
CY7C429-10VC
CY7C429-15AC
CY7C429-15JC
CY7C429-15PC
CY7C429-15VC
CY7C429-15JI
CY7C429-15PI
CY7C429-15VI
CY7C429-150MB
CY7C429-15LMB
20
CY7C429-20AC
CY7C429-20JC
CY7C429-20PC
CY7C429-20VC
CY7C429-20JI
CY7C429-20PI
CY7C429-20VI
CY7C429-200MB
CY7C429-20LMB
25
CY7C429-25AC
CY7C429-25JC
CY7C429-25PC
CY7C429-25VC
CY7C429-25JI
CY7C429-25PI
CY7C429-25VI
CY7C429-250MB
CY7C429-25LMB
30
CY7C429-30AC
CY7C429-30JC
CY7C429-30PC
CY7C429-30VC
CY7C429-30JI
CY7C429-30PI
CY7C429-30VI
40
CY7C429-300MB
CY7C429-30LMB
CY7C429-40AC
CY7C429-40JC
CY7C429-40PC
CY7C429-40VC
Package
1YPe
A32
J65
P21
V21
A32
J65
P21
V21
Package 1YPe
32-Pin Thin Plastic Quad Flatpack
Operating
Range
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Pin Thin Plastic Quad Flatpack
32-LeadPlastic Leaded Chip Carrier
Commercial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
J65
P21
V21
022
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
L55
A32
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
J65
P21
V21
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
J65
P21
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
V21
022
L55
A32
28-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
J65
P21
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
V21
J65
P21
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
V21
022
28-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
Commercial
32-Pin Thin Plastic Quad Flatpack
L55
A32
J65
P21
V21
J65
P21
V21
022
Industrial
Military
Industrial
Industrial
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
Industrial
J65
P21
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-MiI) Molded DIP
V21
28-Lead (300-Mil) Molded SOJ
L55
A32
5-44
CY7C419/21/25/29/33
.7EYPRESS
Ordering Information (continued)
Speed
(ns)
20
25
30
40
65
Ordering Code
CY7C433-20AC
CY7C433 - 20JC
CY7C433-20PC
CY7C433-20VC
CY7C433-20JI
CY7C433-20PI
CY7C433-20VI
CY7C433 - 200MB
CY7C433-20LMB
CY7C433 - 25AC
CY7C433-25JC
CY7C433-25PC
CY7C433-25VC
CY7C433-25JI
CY7C433 - 25PI
CY7C433-25VI
CY7C433-250MB
CY7C433-25LMB
CY7C433-30AC
CY7C433-30JC
CY7C433-30PC
CY7C433-30VC
CY7C433- 30JI
CY7C433-30PI
CY7C433-30VI
CY7C433-300MB
CY7C433- 30LMB
CY7C433-40AC
CY7C433-40JC
CY7C433-40PC
CY7C433-40VC
CY7C433-40JI
CY7C433-40PI
CY7C433-40VI
CY7C433 -400MB
CY7C433-40LMB
CY7C433-65AC
CY7C433-65JC
CY7C433-65PC
CY7C433-65VC
CY7C433-65JI
CY7C433-65PI
CY7C433-65VI
CY7C433-650MB
CY7C433 -65LMB
Package
Name
A32
J65
P21
V21
J65
P21
V21
022
L55
A32
J65
P21
V21
J65
P21
V21
022
L55
A32
J65
P21
V21
J65
P21
V21
022
L55
A32
J65
P21
V21
J65
P21
V21
022
L55
A32
J65
P21
V21
J65
P21
V21
022
L55
Package type
Operating
Range
Commercial
32-Pin Thin Plastic Quad Fiatpack
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
Industrial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Flatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Fiatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Fiatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Lead (300-Mil) Molded DIP
2S-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Thin Plastic Quad Fiatpack
Commercial
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
Industrial
28-Le\ld (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
5-46
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64/256/512/lK/2K/4K!8Kx 9
Synchronous FIFOs
Features
and
• Low operatiltg power
IcC2
• 64 x 9 (CY7C4421)
• 256 x 9 (CY7C4201)
• 512 x 9 (CY7C4211)
=SOmA
• Output Enable (OE) pin
• 32-pin PLCCtTQFP
Functional Descriptiou.
• lK x 9 (CY7C4221)
• 2K x 9 (CY7C4231)
• 4K x 9 (CY7C4241)
• 8K x 9 (CY7C4251)
• High-speed l00-MHz operation (10 ns
read/write cycle time)
• Pin compatible and functionally
equivalent to IDT72421, 72201, 72211,
72221,72231,72241
• Fully asynchronous and simultaneous read and write operation
• Four status flags: Empty, Full, and
programmable Almost Empty/Almost
Full
• Expandable in widtb
The CY7C42Xl ate high-speed, low-power, fIrst-in fIrst-out (FIFO) memories with
clocked read and write interfaces. All are 9
bits wide. The CY7C42Xlarepin-compatible to IDT722Xl. The CY7C42Xl can be
cascaded to increase FIFO depth. Programmable features include ~most Full/
Almost Empty flags. These FIFOs provide
solutions for a wide variety of data bufferingneeds,includinghigh-speeddataacquisition, multiprocessorinterfaces, and communications buffering.
These FIFOs have 9-bit input and output
ports that are controlled by separate clock
and enable signals. The input port is controlled by a free-running clock (WCLK)
Logic Block Diagram
two
write-enable
(WENT,
pins
WEN2/ID).
When WENT is LOW and WEN2!ill is
HIGH, data is written into the FIFO on
the rising edge of the WCLK signal. While
WENT, WEN2/lD is held active, data is
continually written into the FIFO on each
WCLKcycle. The output portis controlled
in a similar manner by a free-running read
clock (RC~ and two read enable pins
(RENl, R N2).
In addition, the
CY7C42Xl has an output enable pin
«()E). The read (RCLK) and write
(WCLK) clocks may be tied together for
single-clock operation or the two clocks may
be run independently for asynchronous
read/Write applications. Clock frequencies
up to 100 MHz are achievable.
Depth expansion is possible using one enable input for system control, while the
other enable is controlled by expansion
logic to direct the flow of data.
Pin Configuration
PLCC
lbpView
00-.
4 3 2
D,
Do
6
1 3231 30
29
28
PIll'
PIlE
WCLK WEI'ff WEN2Ill!
GND
REi] to 63
64
7C4225 - 1K x 18
0
1 to nP']
(n+ 1) to 512
513 to (1024 -(m+1»
(1024-m)[3'J to 1023
1024
Number of Words in FIFO
7C4205 - 256 x 18
7C4215 - 512 x 18
0
0
1 to nl3~J
1 to nl3~J
(n+1) to 128
129 to (256-(m+ 1»
(256-m)Lj>J to 255
256
(n+1) to 256
257 to (512-(m+1»
(512-m)Lj>] to 511
512
Number of Words in FIFO
7C4235 - 2K x 18
7C4245 - 4K x 18
0
0
1 to nLj·]
1 to nL"]
(n+1) to 1024
1025 to (2048 -(m+ 1»
(2048-m)l3'J to 2047
2048
(n+ 1) to 2048
2049 to (4096 -(m+ 1»
(4096-m)l3'J to 4095
4096
Notes:
37. The same selection sequence applies to reading from the registers.
REN is enabLed and read is performed on the LOW-to-HIGH transition of RCLK.
38. n = Empty Offset (Default Values: CY7C4425 n = 7, CY7C4205 n =
31, CY7C4215 n = 63, CY7C4225nC4235nC4245 n = 127).
39. m = Full Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31,
CY7C4215 n = 63, CY7C4225nC4235nC4245 n = 127).
5-80
H
H
H
H
L
PAF
H
H
H
H
L
L
HF
H
H
H
L
L
L
PAE
L
L
H
H
H
H
EF
L
H
H
H
H
H
FF
H
H
H
H
H
L
PAF
H
H
H
H
L
L
OF
H
H
H
L
L
L
PAE
L
L
H
H
H
H
EF
L
H
H
H
H
H
FF
H
PRELIMINARY
Depth Expansion Configuration
(with Programmable Flags)
3.
The'CY7C42X5 can easily be adapted to applications requiring
more than 64/256/512/1024/2048/4096 words of buffering. Figure
2'shows Depth Expansion using three CY7C42X5s. Maximum
depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First
Load (fL) control input.
2. All other devices mus! have FL in the HIGH state.
4.
5.
6.
7.
CY7C4425/4205/4215
CY7C4225/4235/4245
The Write Expansion Out (WX~) pin of each device must be
tied to the Write Expansion In WXI) pin of the next device.
The Read Expansion Out (RXOl!>in of each device ll1ust be
tied to the Re;ld Expansion In (RX!) pin of the next device.
All Load (ill) pins are tied together.
The Half-Full Flag (HF) is not available in the Depth Expansion Configuration.
EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
lJ
WXO mID
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
Vee
L
FIRST LOAD (f'[)
EF
FF
flAF
-
flAE r - WlU 100
J tRXO
WlJj
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
DATA IN (D)
FIRST LOAD (F[)
Vee
L
FF
DATAOUT(Q)
EF
- m
flAE r-
WXi
RXI
ff
WXO mID
WRITE CLOCK (WCLK)
WRITE ENABLE
(WEN)
READ ENABLE
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
RESET(RS)
LOAD ([[))
FF~
PAF~
READ CLOCK (RCLK)
"
PAF WlU
FIR~T LOAD (F[)
6u+put ~NABLE (DE)
EF
FF
l t
(REN)
roo flAE
~~
~PAE
f
42X525
Figure 2. Block Diagram of 192 x 18/768 x 18/1536 x 18/3072 x 18/12288 x 18 Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
5-82
PRELIMINARY
iircYPRESS
CY7C4425/4205/4215
CY7C4225/4235/4245
Ordering Information (continued)
512 x 18
Speed
(ns)
10
15
25
35
lKx18
Speed
(ns)
10
15
25
35
CY7C4215 -10AC
A65
Package
'IYPe
64-Lead Thin Quad F1atpack
CY7C4215 -lOJC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4215 -10Al
A65
64-Lead Thin Quad F1atpack
CY7C4215 -lOJI
J81
68-Lead Plastic Leaded Chip Carrier
Ordering Code
Package
Name
CY7C4215 -15AC
A65
64-Lead Thin Quad Flatpack
CY7C4215-15JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4215 -15Al
A65
64-Lead Thin Quad Flatpack
CY7C4215 -15JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4215 - 25AC
A65
64-Lead Thin Quad F1atpack
CY7C4215 - 25JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4215 - 25AI
A65
64-Lead Thin Quad F1atpack
CY7C4215 - 25JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4215 - 35AC
A65
64-Lead Thin Quad F1atpack
CY7C4215 - 35JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4215 - 35AI
A65
64-Lead Thin Quad F1atpack
CY7C4215 - 35JI
J81
68-Lead Plastic Leaded Chip Carrier
Package
Name
Package
Ordering Code
'IYPe
CY7C4225-lOAC
A65
64-Lead Thin Quad Flatpack
CY7C4225 -10JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4225 -lOAl
A65
64-Lead Thin Quad F1atpack
CY7C4225 -lOJI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4225 -15AC
A65
64-Lead Thin Quad Flatpack
CY7C4225-15JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4225 -15AI
A65
64-Lead Thin Quad F1atpack
CY7C4225 -15JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4225 - 25AC
A65
64-Lead Thin Quad F1atpack
CY7C4225-25JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4225 - 25AI
A65
64-Lead Thin Quad F1atpack
CY7C4225-25JI
J81
.68-Lead Plastic Leaded Chip Carrier
CY7C4225 - 35AC
A65
64-Lead Thin Quad F1atpack
CY7C4225 - 35JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C4225 - 35Al
A65
64-Lead Thin Quad F1atpack
CY7C4225 - 35JI
J81
68-Lead Plastic Leaded Chip Carrier
5-84
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
CY7C439
Bidirectional 2K x 9 FIFO
Features
Functional Description
• 2048 x 9 FIFO buffer memory
• Bidirectional operation
• High-speed 28.S-MHz asynchronous
reads and writes
• Simple control interface
• Registered and transparent bypass
modes
• Flags indicate Empty, Full, and Half
Full conditions
The CY7C439 is a 2048 x 9 FIFO memory
capable of bidirectional operation. As the
term first-in first-out (FIFO) implies, data
becomes available to the output port in the
same order that it was presented to the input port. There are two pins that indicate
the amount of data contained within the
FIFO block-ElF (Empty/Fnll) and HF
(Half Full). These pins can be decoded to
determine one of four states. Tho 9-bit
data ports are provided. The direction selected for the FIFO determines the input
and output ports. The FIFO direction can
be programmed by the user at ~ time
through the use of the res(t JYin (MR) and
the bypass/direction pin B PA). There
are no control or status registers on the
CY7C439, making the part simple to use
• SV ± 10% supply
• Available in 300-mil DIP, PLCC, LCC,
and SOJ packages
• TTL compatible
while meeting the needs of the majority of
bidirectional FIFO applications.
FIFO read and write operations may occur
simultaneously, and each can occur at up to
28.5 MHz. The port designated as thewrite
port drives its strobe pin (STBX, X = A or
B) LOW to initiate the write operation.
The port designated as the read port drives
its strobe pin LOW to initiate the read operation. Output port pins go to a high-impedance state when the associated strobe
pin is HIGH. All normal FIFO P rations
require the bypass control pin ( :y X, X =
A or B) to remain HIGH.
3p
In addition to the FIFO, two other data
paths are provided; registered bypass and
transparent bypass. Registered bypass can
be considered as a single-word FIFO in the
reverse direction to the main FIFO. The
Logic Block Diagram
Pin Configurations
PLCC/LCC
ThpView
Ao Ao A.,NCAo Ao A,
A,
Ao
BYI'A
GND
lI'II'I!
BOA
So
PORTA . . . .~• •~
Ao-Ao
NC
B,
TRANSPARENT
BYPASS
~Ao
432!1 1 323130
-29
5
28 ~ ElF
6
27 ~ NC
7
28
8
25
70439
9
M1'!
24
10
STBI!
23
11
RI'
22
12
21
Ba
13
14151617181920
~~
828384 NC B5
Be B7
0439-2
DIP
ThpView
FLAG
1-_-i~t-o.!CONTROL
A.,
Ao
Ao
Ao
Ao
A,
Ao
ElF
A,
Ao
BYI'A
STI!A
GND
Vee
M1'!
BI'I'l!
BOA
2048x9
FIFO
STl!!!
RI'
So
B,
B.
0439-1
Ba
B,
B,
B,
Bo
B,
0439-3
Selection Guide
Frequency (MHz)
7C439-2S
28.5
7C439-30
25
7C439-40
20
7C439-65
12.5
25
147
30
140
40
130
115
170
160
145
Maximum Access Time (ns)
Maximum 03erating
Current(mA
I Commercial
I Military
5-86
65
~YPRESS
CY7C439
Electrical Characteristics Over the'Operating Rangel2]
Parameter
VOH
VOL
VIH
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
7C439-25
Min. Max.
2.4
'lest Conditions
Vee = Min.,
10H= -2.0 rnA
Vee = Min., 10L = 8.0 rnA
0.4
Com'l
Mil
I
Input LOW
Voltage
Input Leakage
GND.s VI.s..Vee
Current
Output Leakage
S'fBX~ VIH,
Current
GND.s Vo.s Vee
Com'I[3]
Operating Current Vee = Max.,
lOUT = OmA
Mil[4]
VIL
IIX
loz
lee
ISB!
Standby Current
ISB2
Power·Down
Current
Output Short
Circuit Currend5]
los
7C439-30
Min. Max.
2.4
2.2
Vee
-3.0
7C439-40
Min. Max.
2.4
0.4
7C439-65
Min. Max.
2.4
0.4
Unit
V
0.4
V
0.8
2.2
2.2
-3.0
Vee
Vee
0.8
2.2
2.2
-3.0
Vee
Vee
0.8
2.2
2.2
-3.0
Vee
Vee
0.8
V
V
V
-10
+10
-10
+10
-10
+10
-10
+10
!lA
-10
+10
-10
+10
-10
+10
-10
+10
!lA
115
145
40
45
20
25
-90
rnA
147
All Inputs =
VIHMin.
Com'l
Mil
All Inputs
Com'l
Vee - 0.2V
Mil
Vee = Max., VOUT = GND
40
20
140
170
40
45
20
130
160
40
45
20
25
-90
25
-90
-90
rnA
rnA
rnA
Capacitance[6]
Parameter
Description
Input Capacitance
Output Capacitance
qN
CoUT
Test Conditions
Max.
8
10
TA = 25°C, f = 1 MHz,
Vee = 4.5V
Notes:
2. See the last page of this specification for Group A subgroup testing in-
formation.
3. Icc (commercial} = 115 rnA + [(1 - 12.5) . 2 mAtMHz) for
f~ 12.5 MHz
where r = the larger of the write or read
operating frequency.
Unit
pF
pi<
4.
Icc (military) = 145 rnA + [(1 - 12.5) . 2 mA/MHz) for
5.
where f = the larger of the write or read
operating frequency.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Thsted initially and after any design or process changes that may affect
these parameters.
f~12.5MHz
6.
5V31
5V31
I _
I _
AC Test Loads and Waveform
R1500Q
R1500Q
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
30pF
333Q
INCLUDING
JIG AND SCOPE
-
INCLUDING
JIG AND SCOPE
(a) Normal Load
Equivalent to:
R2
5pF
333Q
-
0439-4
(b) High-Z Load
THEVENIN EQUIVALENT
2000
OUTPUT 00--_."".10--_-00 2V
5-88
0439-5
CY7C439
_;?cYPRESS
Switching Characteristics Over the Operating Rangd2, 7] (continued)
7C439-25
Parameter
Description
Min.
Max.
7C439-30
Min.
Max.
7C439-40
Min.
Max.
7C439-65
Min.
Max.
Unit
tTPO[8,9]
STBX LOW to Data Valid
20
20
30
55
ns
tOL
tESO[8,9]
'fransparent Propagation Delay
20
20
25
30
ns
S1BX LOW to High Z
18
20
25
30
ns
tElID[8,9]
BYPX LOW to High Z
18
2Q
25
30
ns
tEos
STBX HIGH to Low Z
18
20
25
30
ns
tEoB
BYPX HIGH to Low Z
18
20
25
30
tBPW
BYPX fulse Width ('frans.)
25
30
'40
65
ns
tTsp
STBX Pulse Width ('frans.)
20
20
30
55
ns
tBLZ[8,9]
BYPX LOW to Low Z (Read)
10
10
10
10
ns
tBDY
BYPX HIGH to Data Invalid (Read)
3
3
3
3
tWHF
STBX LOW to HF LOW (Write)
35
40
50
80
ns
tRHF
S1BX HIGH to HF HIGH (Read)
35
40
50
80
ns
tRAE
Effective Read from Write HIGH
25
30
35
60
tRPE
Effective Read Pulse Width after ElF
HIGH
tWAF
Effective Write from Reaq HIGH
tWPF
Effective Write Pulse Width after
HIGH
30
25
30
25
ElF
40
ns
65
35
ns
ns
ns
60
ns
25
30
40
65
ns
tBSU
ByPass Data Set-Up Time
15
18
20
30
ns
tBHL
Bypass Data Hold Time
0
0
0
10
ns
Noles:
7. lest conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, and output loading ofthe specified IOrJIoH and
30-pF load capacitanCe as in part (a) of AC Thst Loads, unless otherwise SPecified.
.
8. tDYR, tBD\! tHZR, ITBD, tBHZ, IEBD, tESD, tTSD, tLZR, tHWZ, and tBLZ
use capacitance loading as in part (b) of AC lest Loads.
9.
IHZR, tTBD, tBHZ, tEBD, tESD, and tTSD transition is measured at +500
mV from VOL and - 500 mV from VOH. tDYR and tBDv transition is
measured at the 1.5V level. ILZR, tHWz, and tBLZ transition is measured at ± 100 mV from the steady slate.
Switching Waveforms
Asynchronous Read and Write Timing Diagram
S'mB[101
READ
PORT B
-------1(
~ ~l~~twR
WRITE
PORT A
K
--------l( .
DATA VALID
-----/
~------__«'-__
D_A_T_A_V_A_L1_D_...J>_
-
5-90
C439-6
CY7C439
'-rcYPRESS
Switching Wavefonns (continued)
Last Read to First Write Empty/Full Flag Timing Diagram[ll]
LAST READ
ADDITIONAL WRITES
FIRST WRITE
FIRST READ
ElF
DATA OUT
---<
C439-10
Empty/Full Flag and Read Bubble-Through Mode Timing Diagram[ll]
DATA IN
(PORTA)
ElF
EMPTY
DATA OUT
(PORT B)
DATA VALID
009-11
Empty/Full Flag and Write Bubble-Through Mode Timing Diagram[ll]
ElF
FULL
DATA IN
(PORTA)
DATA OUT
(PORT B)
C439-12
5-92
~YPRESS
CY7C439
Switching Waveforms (continued)
Test Mode Timing Diagram
C439-16
Exception Condition Timing Diagram(14]
~
__________________________
~;I
----------------------~;I
)"
~
f4
f4-
tESD ..
---ill'
~
f4
DATAB
VALID OUTPUT
tEDS •
f4
tEBD ...
'"
tEDB ..
HIGHZ
1/
./
"
Architecture
The CY7C439 consists of a 2048 by 9-bit dual-ported RAM array,
a read pointer, a write pointer, data switching circuitry, buffers, a
bypass register, control Si~nalS (S1BA, STBB, BYPA, BYPB, MR),
and flags (ElF, HF, BDA .
Operation at Power-On
~n
power-up, the FIFO must be reset with a Master Reset
(MR) cycle. During an MR cycle, the user can initialize the device
by choosing the direction of FIFO operation (see Table 1). There is
a minimum LOW period for MR, but no maximum time. The state
ofBYPA is latched internally by the rising edge ofMR and used to
determine the direction of subsequent data operations.
Resetting the FIFO
During the reset condition (see Table 1), the FIFO three-states
the data ports, sets BDA and HF HIGH, ElF LOW, and ignores
the state of BYPA/B and S1BA/B. The bypass registers are initialized to zero. During this time the user is expected to set the direction of the FIFO by driving BYPA HIGH or LOW, and BYPB,
S1BA, and S1BB HIGH. If BYPA is LOW (selecting direction
B>A), the FIFO will then remain in a reset condition until the
user terminates the reset operation by driving BYPA HIGH. If
BYPAis HIGH (selecting direction A> B), the reset condition ter-
VALID OUTPUT
C439-17
minates after the rising edge of MR. The entire reset phase can be
accomplished in one cycle time of tRe.
FIFO Operation
The opration of the FIFO requires only one control pin per port
(S1BX . The user determines the direction of the FIFO data flow
by initiating an MR cycle (see Table 1), which clears the FIFO and
bypass register and sets the data path and control signal multiplexers. The bypass register is configured in the opposite direction to
the FIFO data flow. The FIFO direction can be reversed at any
time by initiating another MR ~cle. Data is written into the FIFO
on the rising edge of the input, TBX, and read from the FIFO by
a low level at the output, S1BX. The two ports are asynchronous
and independent. If the user attempts to read the FIFO when it is
empty, no action takes place (the read pointer is not incremented)
until the other port writes to the FIFO. Then a bubble-through
read takes place, in which the read strobe is generated internally
and the data becomes available at the read port shortly thereafter
if the read strobe (STBX) is still LOW. Similarly, for an attempted
'write operation when the FIFO is full, no internal operation takes
place until the other port performs a read operation, at which time
the bubble-through write is performed ifthe write strobe (STBX)
is still LOW.
5-94
4
CY7C439
?cYPRESS
Table 3. Exception Conditions: Operation Not Defined
Direction
STBA
BYPA
STBB
BYBP
X
0
1
0
0
Data Buses High Impedance
Action
X
1
0
0
0
Data Buses High Impedance
X
0
0
0
0
Data Buses High Impedance
X
0
0
1
0
Data Buses High Impedance
X
0
0
0
1
Data Buses High Impedance
Table 4. Flag Truth Table
ElF
HF
0
1
Empty
1
1
1-1024 Locations Full
1
0
1025-2047 Locations Full
0
0
Full
State
1Ypical DC and AC Characteristics
NO~EDSUPPLYCURRENT
NORMALIZED SUPPLY CURRENT
vs. AMBmNT TEMPERATURE
vs. SUPPLY VOLTAGE
1.4
1.2
./
Jl1.0
0
w
~
«
:::;
0.8
II:
0
z
0.6
V
0.4
4.0
V
...V
'"
0
~
~
II:
V,N = 5.0V
TA = 25°C
4.5
Jl1.2
I
I
5.0
5.5
SUPPLY VOLTAGE
0
-
z
1.0
6.0
1.2
~
II:
1.0
o
~
............... I'-....
~~
0 0.9
z
1.0
0.8
TA= ~5°C
0.7
4.0
0.6
4.5
5.0
SUPPLY VOLTAGE
20
"1"-
10
Vee = 5.0V
TA = 25°C
:::l
g
~
25
125
AMBIENT TEMPERATURE (0C)
o
5.5
M
6.0
"-
"
0
1.0
0.0
2.0
3.0
'"
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
~140
-
;:- 120
z
~ 100
II:
1.2
z
0.8
40
II:
4- 1.4
4-
~
:::l
~
~ 30
1.6
1.3
w 1.1
50
NORMALIZED tA
vs. AMBIENT TEMPERATURE
NORMALIZED tA
vs. SUPPLY VOLTAGE
0
-
Vee = 5.5V
V,N = 5.0V
f=20MHz
M
60
!zw
()
0.8
0.0
-55
l
II:
II:
-
OUTPUT SOURCE CURRENT,
OUTPUT VOLTAGE
VS.
----
-~
~
a
~ iii
80
5
40
Vee = 5.0V
§
1~
v
60
20
o
v
/
l<:
AMBIENT TEMPERATURE (0C)
5-96
/
/
1/
0.0
Vee = 5.0V
TA= 25°C
I
1.0
2.0
3.0
OUTPUT VOLTAGE
M
4.0
=a.
CY7C439
rcYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
Vrn
VILMax.
Irx
lee
ISB!
ISB2
los
loz
Subgroups
1,2,3>
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameters
tRe
tA
tRR
tpR.
tLZR
tDVR
tHZR
twe
tpw
tlf\liz
tWR
tSD
tHD
tMRse
tpMR
tRMR
tRPS
tRPBS
tRPBH
tBDH
tBSR
tEFL
tHFH
tBRS
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
tRAE
tRPE
Subgroups
9,10,11
9; 10, 11
9,10,11
9,10,11
9,10,11
9,10,11
9, tQ, 11
9,10,11
9,10,11
9,10, Ii
9,lq,il
9,10,11
9,10,11
9,10,11
9,10, l1
9,10,11
9,10,11
9,1O,ll
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9, lO, 11
9,10,11
9,10,11
9,10,11
9,10, It
Parameters
tWAF
tWPF
tBSU
tBHL
tBDA
tBDB
tBA
tBHZ
tTSB
tTBS
tTSN
tTSD
tTBN
tTBD
tTPD
tDL
tESD
tEBD
tEDS
tEDB
tBPW
tTSP
tBLZ
tBDV
Subgroups
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
Document #: 38-00126-D
5-98
CY7C441
CY7C443
Selection Guide
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Clock HIGH Time (ns)
Minimum Clock LOW Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
I Commercial
Maximum Current (rnA)
I
Military!lndustrial
7C441-14
7C443-14
71.4
10
14
6.5
6.5
7
0
10
140
7C441-20
7C443-20
50
15
20
9
9
9
0
15
120
7C441-30
7C443-30
33.3
20
30
12
12
12
0
20
100
150
130
110
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55°C to + 125°C
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
DC Input Voltage ...................... - 3.0V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
Range
Commercial
Industrial
Military[lj
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
- 40°C to +85°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Pin Definitions
I/O
Description
Do-s
I
Data Inputs: when the FIFO is not full and ENW is active, CKW (rising edge)
writes data (Do - Ds) into the FIFO's memory
Oo-s
0
Data Outputs: when the FIFO is not empty and ENR is active, CKR (rising edge)
reads data (00 - Os) out of the FIFO's memory
ENW
I
Enable Write: enables the CKW input
ENR
I
Enable Read: enables the CKR input
CKW
I
Write Clock: the rising edge clocks data into the FIFO when ENW is LOW and
updates the Almost Full flag state
CKR
I
Read Clock: the rising edge clocks data out of the FIFO when ENR is LOW and
updates the Almost Empty and Empty flag states
F1
0
Flag 1: is used in conjunction with Flag 2 to decode which state the FIFO is in
(see Table 1)
F2
0
Flag 2: is used in conjunction with Flag 1 to decode which state the FIFO is in
(see Table 1)
MR
I
Master Reset: resets the device to an empty condition
Signal Name
Note:
1. TA is the "instant on" case temperature.
5-100
CY7C441
CY7C443
~YPRESS
Switching Characteristics Over the Operating Rangd2,lOj
7C441-14
7C443-14
Parameter
Description
Min.
Max.
7C441-20
7C443-20
Min.
Max.
7C441-30
7C443-30
Min.
Max.
Unit
tCKW
Write Clock Cycle
14
20
30
tCKR
Read Clock Cycle
14
20
30
ns·
tCKH
Clock HIGH
6.5
9
12
ns
tCKL
tA[llj
Clock LOW
6.5
Data Access Time
tOH
Previous Output Data Hold After Read HIGH
0
0
0
ns
tFH
Previous Flag Hold After Read/Write HIGH
0
0
0
ns
tSD
Data Set-Up
7
9
12
ns
tHD
Data Hold
0
0
0
ns
tSEN
Enable Set-Up
7
9
12
ns
tHEN
Enable Hold
0
0
0
tFD
Flag Delay
tSKEWl[l2j
Opposite Clock After Clock
tSKEwz[l3j
tpMR
9
10
12
ns
20
15
10
ns
ns
20
15
ns
ns
0
ns
20
30
ns
20
30
ns
0
0
0
ns
Data Hold From MR LOW
0
0
0
ns
tMRR
Master Reset Recovery (MR HIGH Set-Up to First
Enabled Write/Read)
14
20
30
ns
tMRF
MR HIGH to Flags Valid
14
20
30
ns
tAMR
MR HIGH to Data Outputs LOW
14
20
30
ns
0
0
Opposite Clock Before Clock
14
Master Reset Pulse Width (MR LOW)
14
tSCMR
Last Valid Clock LOW Set-Up to MR LOW
tOHMR
Notes.
8. CL = 30 pF for all AC parameters.
9. All AC measurements are referenced to 1.Sv.
10. Thst conditions assume signal transition time of 3 ns or less, timing reference levels of 1.SV; and output loading as shown in the ACTest Loads
and Waveforms and capacitance as in note NO TAG, unless otherwise
specified.
11. Access time includes all data outputs switching simultaneously.
12. tSKEWl is the minimum time an opposite clock can occur after a clock
and still be guaranteed not to be included in the current clock cycle (for
purposes offlag update). If the opposite clock occurs less than tSKEWl
after the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. Note: The opposite clock
i~ the signal to which a flag is not synchronized; i.e., CKW is the oppoSIte clock for Empty and Almost Empty flags, CKR is the the opposite
clock for the Almost Full flag. The clock is the signal to which a flag is
synchronized; i.e., CKW is theclockforthe Almost Fullflag, CKR is the
clock for Empty and Almost Empty flags.
13. tSKEW2 is the minimum time an opposite clock can occur before a clock
and still be guaranteed to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEW2
before the clock, the decision ofwhether or not to include the opposite
clockinthe current clock cycle is abritrary. See Note NO TAGfordefinition of clock and opposite clock.
5-102
CY7C441
CY7C443,
Switching Waveforms
(continued)
Read to Empty Timing Diagram[18,19,20]
1 (no change)
COUNT
LATENT CYCLE
CKR
CKW
~
-=LD~W~
+-________ ______-+________4-________
________
~
~
____ __
~
C441-9
Read to Empty Timing Diagram with Free-Running Clocks[18,19,21]
COUNT
LATENT CYCLE
CKR
CKW
C441-10
Notes:
14. ENW or CKW must be inactive while MR is LOW:
15. ENR or CKR must be inactive while MR is LOW:
16. All data outputs (00 _ 8) go LOW as a result of the rising edge ofMR.
17. In this example, 00 _ 8 will remain valid until tOHMR if the first read
shown did not occur or if the read occurred soon enough such that the
valid data was caused by it.
18. "Count" is the number of words in the FIFO.
19. CKR is clock and CKW is opposite clock.
20. R3 updates the flags to the Empty state by bringing F1 LOW: Because
W1 occurs greater than tSKEW! after R3, R3 does not recognize W1
when updating flag status. But because W1 occurs greater thim tSKEW2
before R4, R4 includes W1 in the flag update and therefore updates the
FIFO to the Almost Empty state. It is important to note that R4 is a
lat~cle; i.e., it only updates the flag status, regardless of the state
of ENR. It does not change the count or the FIFO's data outputs.
21. R2 is ignored because the FIFO is empty (count = 0). It is important
to note that R3 is also ignored because W3, the first enabled write after
empty, occurs less than tSKEW2 before R3. Therefore, the FWD still
appears empty when R3 occurs. Because W3 occurs greater than
tSKEW2 before R4, R4 includes W3 in the flag update.
5-104
CY7C441
CY7C443
Switching Waveforms
(continued)
Write to Almost Full Timing Diagram[18,24,25,26,27]
COUNT
2030
[494]
2031
2032
2031
[495]
[496]
[495]
2030
[494]
2031
2032
, 2030'''
~ !~4L ;
, 2001....
~!~L ;
[497]
[498]
2033
[497]
'"2032 ..
~ !~BL!
CKVV
CKR
C441-13
Write to Almost Full Timing Diagram with Free-Running Clotks[18,24,25]
COUNT
2031
[495]
2032
[498]
2031
[495]
2030
2031
[494]
[495]
2032
[496]
2033
1497]
0441-14
Note.:
24. CKW is clock and CKR is opposite clock.
25. Count =2032 indicates Almost FuII for CY7C443 and count =496 indicates Almost FuII for CY7C441. Values for the CY7C44I count are
shown in brackets.
26. The dashed lines show W3 as flag update write rather than an enabled
write because ENW is deasserted.
27. W2 updates tl).e flags to the Almost Full state by bringing FI LOW. Because RI occurs greater than tSKEW! after W2, W2 does not recognize
RI when updating the flag status. W3 includes R2in the flag update because R2 occurs greater than tSKEW2 before W3. Note that W3 does
not have to be enabled to update flags.
28. When making the transition from Almost FuII to Intermediate, the
count must decrease by two (2032.2030; two enabled reads: R2, R3)
before a write (W4) can update flags to Intermediate state.
5-106
CY7C441
CY7C443
~YPRESS
E
CKR
F1
CKW
F2
CKR
INTERNAL LOGIC
PINS
C441-16
Figure 1. Flag Logic Diagram
Flag Operation (continued)
Until the flag update cycle is executed, the synchronous flags do
not show the true state of the FIFO. For example, if 2,040 writes
are performed to an empty CY7C443 without a single read, Fl
and F2 will still exhibit an Empty flag. This is because F2 is
exclusively updated by the CKR, therefore, a single read (flag
update cycle) is necessary to update flags to Almost Full state. It
should be noted that this flag update read does not require ENR
= LOW, so a free-running read clock will initiate the flag update
cycle.
When updating the flags, the CY7C441/443 decide whether ornot
the opposite clock was recognized when a clock updates the flag.
For example, if a write occurs at least tSKEWl after a read when
updating the Empty flag, the write is guar~teed not to be
included when CKR updates the flag. If a wnte occurs at least
tSKEW2 before a read, the write is guaranteed to be included when
CKR updates the flag. If a write occurs within tSKEWl/tSKEW2
after or before CKR, then the decision of whether or not to
include the write when the flag is updated by CKR is arbitrary.
The update cycle for non-boundary flags (Almost Empty, Almost
Full) is different from that used to update the boundary flag
(Empty). Both operations are described below.
Boundary Flag (Empty)
The Empty flag is synchronized to the CKR signal. The Empty
flag can only be updated by a clock pulse on the CKR pin. An
empty FIFO that is written to will be described with an Empty flag
state until a clock pulse is presented on the CKR pin. When
making the transition from Empty to Almost Empty (or Empty to
Intermediate or Empty to Almost Full), a clock cycle on the CKR
is necessary to update the flags to the current state. Such a state
(flags displaying empty even though data has been written to the
FIFO) would require two read cycles to read data out of FIFO.
The first read serves only to update the flags to the Almost Empty,
Intermediate, or Almost Full state, and the second read outputs
the data. This first read cycle is known as the latent or flag update
cycle because it does not affect the data in the FIFO or the count
(number of words in FIFO). It simply deasserts the Empty flag.
The flags are updated regardless of the ENR state. Therefore the
update occurs even when ENR: is deasserted (HIGH) so tha.t a
valid read is not necessary to update the flags to correctly descnbe
the FIFO. With a free-running clock connected to CKR, the flag
updates with each cycle. Table 2 shows sample operations that
update the Empty flag.
Although a Full flag is not supplied externally on the
CY7C441/CY7C443, a Full flag exists internally. The operation of
the FIFO at the Full boundary is analogous to its operation at the
Empty boundary. See the text section "Boundary Flags (Full)" in
the CY7C451/CY7C453 datasheet.
Non-Boundary Flags (Almost Empty, Almost FuJI)
The flag status pins, F 1 and F2, exhibit the Almost Empty status
when both the CY7C441 and the CY7C443 contain 16 words or
less. The Almost Full Flag becomes active wilen the FIFO
contains 16 or less empty locations. The CY7C441 becomes
Almost Full when it contains 496 words. The CY7C443 becomes
Almost Full when it contains 2032 words. The Almost Empty flag
(like tne Empty flag) is synchronous to the CKR signal, whereas
the Almost Full flag is synchronous to the CKW signal.
Non-boundary flags employ flag update cycles similar to the
boundary flag latent cycles in order to update the FIFO state. For
example, if the FIFO just reaches the Almost Empty state (16
words) and then two words are written, a read clock (CKR) will be
required to update the flags to the Intermediate state. However,
unlike the boundary (Empty) flag's update cycle, the state of the
enable pin (ENR in this case) affects the operation. Therefore,
ENR sett~EN) and hold (tHEN) tinles must be met. IfENR is
=LOW) during the latent cycle, the count and data
asserted E
update in addition to FI and F2. IfENR is not active (ENR=I)
during the flag update cycle, only the flag is updated.
The same principles apply for updating the flags when a transition
from the Almost Full to the Intermediate state occurs. If the
CY7C443 just reaches the Almost Full state (2032 words) and
then two words are read, a write clock (C~ will be required to
update the flag to the Intermediate state. If NW is LOW during
the flag Epdate cycle, the count and data update in addition to the
flags. If NW is HIGH, only the flag is updated. Therefore, ENW
set-up (tSEN) and hold (tHEN) tinles must be met. Tables 3 and 4
show examples for a sequence of operations that affect the Almost
Empty and Almost Full flags, respectively.
Width Expansion
The CY7C441/3 can be expanded in width to provide word width
greater than 9 in increments of 9. During width expansion mode,
all control inputs are common. When the FIFO is being read near
5-108
CY7C441
CY7C443
~YPRESS
Table 4. Almost Full Flag Operation Example[30,31]
Status Before Operation
Status After Operation
Number of Number of
Number of Number of
Current
Words in
Words in
Words in
Words in
State of
FIFO
FIFO
Next State
FIFO
FIFO
FIFO
F1 F2 CY7C441
CY7C443
F1 F2 CY7C441 CY7C443
Operation
of FIFO
AF
496
2032
1
495
2031
0
1
Read
AF
0
(ENR=LOW)
AF
495
2031
Read
0
1
494
0
1
AF
2030
(ENR=LOW)
AF
1
494
2030
Write
Intermediate 1
1
494
2030
0
(IiNW=IDGH)
Intermediate
1
1
494
2030
Intermediate
1
1
495
2031
Write
(ENW=LOW)
Write
(ENW=LOW)
5-110
Read
Flag
Update
Intermediate
1
1
495
2031
Write
AF
0
1
496
2032
Write
Notes:
29. Applies to both the CY7C441 and CY7C443 operations.
30. The CY7C441 Almost Full state is represented by 496 or more words.
31. The CY7C443 Almost Full state is represented by 2032 or more words.
Comments
Read
~'franSition
om Intermediate
to Almost
Full)
CY7C441
CY7C443
Ordering Information
Speed
(ns)
14
20
30
Ordering Code
Package
Name
Package 1Ype
CY7C441-14PC
P21
28-Lead (300-Mil) Molded DIP
CY7C441-14JC
J65
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded SOJ
CY7C441-14VC
V21
CY7C441-14PI
P21
28-Lead (300-Mil) Molded DIP
CY7C441-1411
J65
32-Lead Plastic Leaded Chip Carrier
CY7C441-14DMB
D22
28-Lead (300-Mil) CerDIP
CY7C441-14LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C441-20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C441-20JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C441-20VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C441- 20PI
P21
28-Lead (300-Mil) Molded DIP
CY7C441- 2011
J65
32-Lead Plastic Leaded Chip Carrier
CY7C441-20DMB
D22
28-Lead (300-Mil) CerDIP
CY7C441-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C441-30PC
P21
28-Lead (300-Mil) Molded DIP
CY7C441-30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C441-30VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C441-30PI
P21
28-Lead (300-Mil) Molded DIP
CY7C441-301l
J65
32-Lead Plastic Leaded Chip Carrier
CY7C441-30DMB
D22
28-Lead (300-Mil) CerDIP
CY7C441-30LMB
L55
32-Pin Rectangular Leadless Chip Carrier
5-112
Op,erating
Range
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
CY7C441
CY7C443
~YPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
YOL
VIH
VrL
Irx
ICCl
Iccz
ISB
los
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameter
Subgroups
tCKR
9,10,11
9,10,11
9,10, n
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10, IT
9,10,11
9, io, 11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9, lO, 11
9,10,11
9,10,11
9,10,11
ttKW
term
tCKL
tA
tOH
tFH
tSD
tHD
tSEN
tHEN
tHENR
tFD
tSKEWl
tSKEW2
tpMR
tscMR
tOHMR
tMRR
tMRF
tAMR
Document #: 38-00124-F
5-114
~YPRESS
CY7C451
CY7C453
Functional Description (continued)
validinthestandaloneandwidthexpansionconfigurations.Inthe
depth expansion, this pin provides the expansion out (XO) information that is used to signal the next FIFO when it will be activated.
The flags are synchronous, i.e., they change state relative to either
the read clock (CKR) or the write clock (CKW). When entering or
exiting the Empty and Almost Empty states, the flags are updated
exclusively by the CKR. The flags denoting Half Full, Almost Full,
and Full states are updated exclusively by CKw. The synchronous
flag architecture guarantees that the flags maintain their status for
some minimum time.
The CY7C451 and the CY7C453 use center power and ground for
reduced noise. Both configurations are fabricated using an advanced 0.811 N-well CMOS technology. Input ESD protection is
greater than 2001 V, and latch-up is prevented by the use ofreliable
layout techniques, guard rings, and a substrate bias generator.
Selection Guide
7C4S1-14
7C4S3-14
7C4S1-20
7C4S3-20
7C4S1-30
7C4S3-30
Maximum Frequency (MHz)
71.4[1]
50
33.3
Maximum Cascadable Frequency
N/A[2]
50
33.3
10
15
20
Minimum Cycle Time (ns)
14
20
30
Minimum Clock HIGH Time (ns)
6.5
9
12
Minimum Clock LOW Time (ns)
6.5
9
12
Minimum Data or Enable Set-Up (ns)
7
9
12
Minimum Data or Enable Hold (ns)
0
0
0
Maximum Flag Delay (ns)
10
15
20
140
120
100
150
130
110
Maximum Access Time (ns)
Maximum Current (rnA)
I Commercial
I Military/Industrial
Maximum Ratings
(Above which the useful life maybe impaired. For user guidelines,
not tested.)
Storage Thmperature .................. - 65 ° C to + 150 ° C
Ambient Thmperature with
Power Applied ....................... -55°C to +l25°C
Supply Voltage to Ground Potential ........ -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Notes:
1.
2.
71.4-MHz operation is available only in the standalone configuration.
The -14 device cannot be cascaded.
Static Discharge Voltage ........................ > 2001 V
(per MIL-STO-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
Range
Commercial
Industrial
Military[3]
3.
5-116
Ambient
Temperature
DoC to +70°C
5V± 10%
-40°C to +85°C
5V ± 10%
-55°C to + 125°C
5V ± 10%
TA is the "instant on" case temperature.
Vee
~YPRESS
CY7C451
CY7C453
Electrical Characteristics Over the Operating Rangd4]
De~cription
Parameter
7C451-14
7C453-14
Min. Max.
Test Conditions
YaH
Output HIGH Voltage Yee = Min., 10H = - 2.0 rnA
2.4
VOL
YIH[5]
Output LOW Voltage
YIL[5]
Input LOW Voltage
IJX
Input Leakage
Current
Yee= Max.
IOS[6]
Output Short
Circuit Current
Yee = Max., YOUT = GND
-90
10ZL
10ZH
leel[7]
Output OFF, High Z OE~ YIH, Yss < Yo < Yee
Current
2.2
-3.0
Yee
0.8
-10
+10
-10
Yee = Max., lOUT = 0 rnA Com'l
MiVlnd
leei8]
iSB[9]
2.4
0.4
Yee = Min., 10L = 8.0 rnA
Input HIGH Voltage
Operating Current
7C451-20
7C453-20
Min. Max.
2.4
0.4
2.2
Unit
Y
0.4
Y
2.2
-3.0
Yee
0.8
Y
-3.0
Vee
0.8
-10
+10
-10
+10
J.IA
-90
+10
7C451-30
7C453-30
Min. Max.
-10
-90
+10
-10
Y
rnA
+10
J.IA
rnA
140
120
100
150
130
110
rnA
70
70
70
rnA
Operating Current
Yee = Max., lOUT = 0 rnA Com'l
MiVInd
80
80
80
rnA
Standby Current
Yee = Max., lOUT = 0 rnA Com'l
MiVind
30
30
30
rnA
30
30
30
rnA
Capacitance[lO]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Yee= 5.0Y
Max.
10
12
Unit
pF
pF
AC Test Loads and Waveforms[ll, 12, 13, 14, 15]
R1500Q
ALL INPUT PULSES
OUTP~~31
I
CL
INCLUDING _
JIG AND SCOPE
Equivalent to:
3.0V ---=~---~
GND
R2
333Q
_
C451-4
C451-5
THEvENIN EQUIVALENT
200Q
OUTPUT~o-----¥~~'-----oo2V
Notes:
4.
See the last page of this specification for Group A subgroup testing information.
The Y1H and VIL specifications apply for all inputs e~XI and FL.
The XI pin is not a TIL input. It is connected to either XO of the previous device or V55. FL must be connected to either V55 or Vee.
6. Test no more than one output at a time for not more than one second.
7. Input signals switch from OV to 3V with a rise/fall time of 3 ns or less,
clocks and clock enables switch at maximum frequency (fMAX), while
data inputs switch at fMAXi2. Outputs are unloaded.
8. Input signals switch from OV to 3V with a rise/fall time less than 3 ns,
clocks and clock enables switch at 20 MHz, while the data inputs switch
at 10 MHz. Outputs are unloaded.
5.
9.
All inputs signals are connected to Vee. All outputs are unloaded.
Read and write clocks switch at maximum frequency (1MAx).
10. Thsted initially and after any design or process changes that may affect
these parameters.
11. CL = 30 pF for all AC parameters except for 10HZ.
12. CL = 5 pF for 10HZ.
13. All AC measurements are referenced to l.SV except IOE, tOLZ, and
tOHZ.
14. IoE and tOLZ are measured at ± 100 mV from the steady state.
15. tOHZ is measured at +SOO mV from VOLand - SOOmVfrom VOH.
5-118
CY7C451
CY7C453
Switching Waveforms
Write Clock Timing Diagram
CKW
Do - 8
Read Clock Timing Diagram
CKR
00 - 8
0451-7
Master Reset (Default with Free-Running Clocks) Timing Diagram[21, 22, 23, 24]
________""' ""t------
tpMR
- - - - - 1 / ' -_ _ _ _ _ _ _ _ _ _ __
CKW
CKR
00- 8
ALL DATA
OUTPUTS LOW
VALID DATA
C451-8
5-120
CY7C451
CY7C453
i~":z
"CYPRESS
Switching Waveforms
(continued)
Read to Empty Timing Diagram[25, 28; 29]
1 (NO CHANGE)
COUNT
LATENT CYCLE
CKR
CKW
LOW
C451-11
Read to Empty Timing Diagram with Free-Running Clocks[25, 26, 27, 28]
LATENT CYCLE
HIGH
RF
lOW
C451-12
Note.:
25. "Count" is the number of words in the FIFO.
26. TheFIFOisassumedtobeprogrammedwithP>O(Le.,PAFEdoesnot
transition at Empty or Full).
27. R2 is ignored because the FIFO is empty (count = 0). It is impnrtant
to note that R3 is also ignored because W3, the first enabled write after
empty, occurs less than tSKEW2 before R3. Therefore, the FIFO still
appears empty when R3 occurs. Because W3 occurs greater than
tSKEW2 before R4, R4 includes W3 in the flag update.
28. eKR is clock; CKW is opposite clock.
29. R3 updates the flag to the Empty state by asserting ElF. Because WI
occurs greater t))ari tSKEW! after R3, R3 does not recognize WI when
updating flag status. But because WI occurs greater than tSKEW2 bef(jre R4, R4 includes WI in the flag update and, therefore, updates
FIFO to A1mo~t Empty state. It is important to not~ that R4 is a latent
cycle; Le., it only updates the flag status regardless of the state ofENR.
It does not change the count orthe FIFO's data outputs.
5-122
Ii~YPRESS
CY7C451
CY7C453
Switching Waveforms (continued)
Write to Half Full Timing Diagram with Free-Running Clocks[25, 33, 34, 35]
COUNT
1024
[256)
1025
[257)
1024
[256)
1023
1024
[256)
[255)
1025
[257]
1026
[256)
CKW
a-JW
CKR
'---__-.J/
em
RF
ElF
PAFE
HIGH
HIGH
C451-15
Write to Half Full Timing Diagram with Write Flag Update Cycle with Free-Running Clocks[25, 33, 34, 35, 36, 37]
1023 (no change)
[255)
FLAG UPDATE CYCLE
COUNT
CKW
CKR
tF_D~~-----------------tF-D~--------~--tF-D~-----
RF _____
E~
________________________________________________________________
__
HIGH
PAFE_H_IG_H
______________________________________________________________________________________
0451-16
Notes:
33. CKW is clock and CKR is opposite clock.
34. Count = 1,025 indicates Half Full for the CY7C453 and count = 257
indicates Half Full for the CY7C451. Values for CY7C451 count are
shown in brackets.
35. When the FIFO contains 1,024 [256] words, the rising edge of the next
enabled write causes the fIIi to be true (LOW).
36. The flIiwrite flag update ~e does not affect the count because ENW
is HIGH. It only updates HF to HIGH.
37. When making the transition from Half Full to Less Than Half Full, the
count must decrease by two (1,025 .1,023; two enabled reads: R2 and
R3) before a write (W4) can update flags to less than Half Full.
5-124
CY7C451
CY7C453
Switching Waveforms (continued)
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks[25, 30, 33]
1=1 (no change)
FLAG UPDATE CYCLE
COUNT
CKW
Ef'JW
CKR
EJIII'!
ww
RF
HIGH
ElF
IFD1
l"i\FE
C451-19
Write to Full Flag Timing Diagram with Free-Running Clocks[25, 26, 33, 40]
LATENT CYCLE
COUNT
CKW
CKR
ww
~-------------------------------------------------------------C451-20
Note:
40. W2 is ignored because the FIFO is full (count = 2,048 [512]). It is important to note that W3 is also ignored because R3, the first enabled
read after full, occurs less than tSKEW2 before W3. Therefore, the
FIFO still appears full when W3 occurs. Because R3 occurs greater
than tSKEW2 before W4, W4 includes R3 in the flag update.
5-126
CY7C451
CY7C453
Switching Waveforms (continued)
Even Parity Checking[44]
CKW
ENW
;;F---------------------------------------------------------------------1;;
}
CKR
O~PG!'------------------------------~~---------------J5E
00-7:XXXXXXXXXX~
8 LSBs OF
WORDM-1
8LSBs OF
WORDM+2
001-23
Output Enable Timing[45. 46]
CKR
---------------------~/
READ M+1
,"-----------------
LOW
Oo-a
VALID DATA
WORDM
VALID DATA
WORDM+1
001-24
Notes:
44. In this example. the FIFO is assumed to be programmed to check for
even parity.
45. This example assumes that the time from the CKR rising edge to valid
wordM+l ~ tAo
46. IfENR was HIGH around the rising edge of CKR (i.e .• read disabled).
the valid data at the far right would once again be word M instead of
word M+l.
5-128
-~
,
CY7C451
CY7C453
=====",CYPRESS
Boundary and Non-Boundary Flags
Boundary Flags (Empty)
E
The Empty flag is synchronized to the CKR signal (Le., the Empty
flag can only be updated by a clock pulse on the CKR pin). An
empty FIFO that is written to will be described with an Empty flag
state until a rising edge is presented to the CKR pin. When making
the transition from Empty to Almost Empty (or Empty to Less
than or Equal to Half Full), a clock cycle on the CKR is necessary
to update the flags to the current state. In such a state (flags showing Empty even though data has been written to the FIFO), two
read cycles are required to read data out of FIFO. The first read
serves only to update the flags to the Almost Empty or Less than or
Equal to Half Full state, while the second read outputs the data.
This first read cycle is known as the latent or flag update cycle because it does not affect the data in the FIFO or the count (number
of words in FIFO). It sim£lLc!.easserts the Empty flag. The flag is
updated regardless ofthe ENR state. Therefore, the update occurs
even when ENR is unasserted (HIGH), so that a valid read is not
necessary to update the flags to correctly describe the FIFO. In this
example, the write must occur at least tSKEW2 before the flag update cycle in order for the FIFO to guarantee that the write will be
included in the count when CKR updates the flags. When a freerunning clock is connected to CKR, the flag is updated each cycle.
Table 2 shows an example of a sequence of operations that update
the Empty flag.
CKR
E/F
F
CKW
CKR
CKW
"'~~---------------4----~~F
INTERNAL LOGIC
PIN
Boundary Flags (Full)
Figure 1. Flag Logic Diagram
Flag Operation (continued)
Since th~ flags denoting emptiness (Empty, Almost Empty) are
only updated by CKR and the flags signifying fullness (Half Full,
Almost Full, Full) are exclusively updated by CKW, careful attention must be given to the flag operation. The user must be aware
that if a boundary (Empty, Almost Empty, Half Full, Almost Full,
or Full) is crossed due to an operation from a clock that the flag is
not synchronized to (Le., CKW does not affect Empty or Almost
Empty), a flag update cycle is necessary to represent the FIFO's
new state. The signal to which a flag is not synchronized will be referred to as the opposite clock (CKW is opposite clock for Empty
and Almost Empty flags; CKR is the opposite clock for Half Full,
Almost Full, and Full flags). Until a proper flag update cycle is executed, the synchronous flags will not show the new state of the
FIFO.
When updating flags, the CY7C451/453 must make a decision as to
whether or not the opposite clock was recognized when a clock updates the flag. For example (when updating the Empty flag), if a
write occurs at least tSKEWl after a read, the write is guaranteed
not to be included when CKR updates the flag. If a write occurs at
least tSKEW2 before a read, the write is guaranteed to be included
when CKR updates flag. If a write occurs within tSKEWl/tSKEW2 after or before CKR, then the decision of whether or not to include
the write when the flag is updated by CKR is arbitrary.
The update cycle for non-boundary flags (Almost Empty, Half
Full, Almost Full) is different from that used to update the boundary flags (Empty, Full). Both operations are described below.
The Full flag is synchronized to the CKW signal (Le., the Full flag
can only be updated by a clock pnlse on the CKW pin). A full FIFO
that is read will be described with a Full flag until a rising edge is
presented to the CKW pin. When making the transition from Full
to Almost Full (or Full to GreatcrThan Half Full), a clock cycle on
the CKW is necessary to update the flags to the current state. In
such a state (flags showing Full even through data has been read
from the FIFO), two write cycles are required to write data into the
FIFO. The first write serves only to update the flags to the Almost
Full or Greater Than Half Full state, while the second write inputs
the data. This first write cycle is known as the latent or flag update
cycle because it does not affect the data in the FIFO or the count
(number of words in the FIFO). It simply deasserts the Full flag.
The flag is updated regardless of the ENW state. Therefore, the
update occurs even when ENW is deasserted (HIGH), so that a
valid write is not necessary to update the flags to correctly describe
the FIFO. In this example, the read must occur at least tSKEW2 before the flag update cycle in order for the FIFO to guarantee that
the read will be included in the count when CKW updates the flags.
When a free-running clock is connected to CKW, the flag updates
each cycle. Full flag operation is similar to the Empty flag operation described in Table 2.
Non-Bouudary Flags (Almost Empty, H~lf Full, Almost Full)
The CY7C451/453 feature programm;lble Almost Empty and Almost Full flags. Each flag can be programmed a specific distance
from the corresponding boundary flags (Empty or Full). The flags
can be programmed to be activated at the EmjJty or Full boundary,
or at a distance of up to 1008 wOf<)s/locations for the CY7C453
(240 words/locations for the CY7C451) from the Empty/Full
boundary. The programming resolution is 16 words/locations.
When the FIFO contains the number of words or fewer for which
the flags have been programmed, the PAFE flag will be asserted
signifying that the FIFO is Almost Empty. When the FIFO is within that same number of empty locations from being Full, the PAFE
will also be asserted signifying that the FIFO is Almost Full. The
HF flag is decoded to distinguish the states.
5-130
CY7C451
CY7C453
XO of the last device connected to XI of the first device. The first
device has its first load pin (FL) tied to V ss while all other devices
must have this pin tied to V co The first device will be the firslto be
write and read enabled after a master reset.
Proper operation also requires that all cascaded devices have common CKW, CKR, ENW, ENR, Do _ 8, Qo _ 8, and MR pins. When
cascaded, one device at a time will be read enabled so as to avoid
bus contention. By asserting XO when appropriate, the currently
enabled FIFO alerts the next FIFO that it should be enabled. The
next rising edge on CKR puts Qo _ 8 outputs ofthe first device into
a high-impedance state. This occurs regardless of the state ofENR
or the next FIFO's Empty flag. Therefore, if the next FIFO is
empty or undergoing a latent cycle, the Qo _ 8 bus will be in a high-
impedance state until the next device receives its first read which
'
brings its data to the Qo - 8 bus.
Program Write/Read of Cascaded Devices
Programming of cascaded FIFOs is the same as for a single device.
Because the controls of the FIFOs are in parallel when cascaded,
they all get programmed the same. During program mode only
parity is programmed since Almost Full and Almost EmptY flags
are not available when CY7C451/453 are cascaded. Only the "first
device" (FIFO with FL=LOW) will output its program register
contents on Qo - 8 during a program read. Qo _ 8 of all other devices will remain in a high-impedance state to avoid bus contention.
CKW
CKR
i
Ef'IR:
~
-V
•
lU
00- 8
00-8
CKW
CKR
CY7C451/3
OATAIN
,--..
00-8
El'JW
MIl
Ef'IR:
OJ:
ElF
f--
RF
,,-DATA OUT
~Oo -8
PAFE/XO FEl
MR
Vss
a-.=
OJ:
-V
II
lU
"Do - 8
00-8
CKW
CKR
El'JW
Ef'IR:
CY7C451/3
I
HF
ElF Vee
l'iiIR:
~
P
I
OJ:
IWE/XO FE
U
Figure 2. Depth Expansion with CY7C4Sl/3
5-132
J
FU1I
CY7C451
CY7C453
Thble 5. Programmable Almost Full/Almost EmptyOptions - CY7C45lJCY7C453[SO]
05
04
03
02
D1
00
0
0
0
0
0
0
PAFE Active when CY7C4SlJ4S3 is:
Completely Full and Empty.
p[Sl]
0
0
0
0
0
0
1
16 or less locations from Empty/Full (default)
1
0
0
0
0
1
0
32 or less locations from Empty/Full
2
0
0
0
0
1
1
48 or less locations from Empty/Full
3
224 or less locations from Empty/FUll
240 or less locations from Empty/Full
992 or less locations from Empty/FUll
1008 or less locations from Empty/Full
Thble 6. Programmable Parity Options
D8
D7
D6
0
X
X
Parity disabled.
1
0
0
Generate even parity on PG output pin.
1
0
1
Generate odd parity on PG output pin.
1
1
0
Check for even parity. Indicate error on PE output pin.
1
1
1
Check for odd parity. Indicate error on PE output pin.
Condition
Notes:
50. 04 and 05 are don'! care for CY7C451.
51.. Referenced in Table 1.
5-134
~
CY7C451
CY7C453
~~
"f!I!I' CYPRESS
Ordering Information
Speed
(ns)
14
20
30
Speed
(ns)
14
20
30
Ordering Code
Package
Name
Package 'Jype
CY7C451-140C
032
32-Lead (300-Mil) CerDlP
CY7C451-14JC
J65
32-Lead Plastic Leaded Chip Carrier
Operating
Range
Commercial
CY7C451-14JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C451-140MB
032
32-Lead (300-Mil) CerDIP
Military
CY7C451-14LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C451-200C
032
32-Lead (300-Mil) CerDlP
CY7C451-20JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7C451-20Jl
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C451-200MB
032
32-Lead (300-Mil) CerDlP
Military
CY7C451-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C451-300C
032
32-Lead (300-Mil) CerDIP
CY7C451-30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C451-30Jl
032
32-Lead (300-Mil) CerDlP
Industrial
CY7C451-300MB
032
32-Lead (300-Mil) CerDlP
Military
CY7C451-30LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Package
Name
Package
'Jype
Ordering Code
CY7C453-140C
032
32-Lead (300-Mil) CerDlP
CY7C453 -14JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
Operating
Range
Commercial
CY7C453-14J1
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C453-140MB
032
32-Lead (300-Mil) CerDlP
Military
CY7C453-14LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C453-200C
032
32-Lead (300-Mil) CerDlP
CY7C453-2OJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C453-20Jl
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C453-200MB
032
32-Lead (300-Mil) CerDIP
Military
CY7C453-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C453 - 300C
032
32-Lead (300-Mil) CerDIP
CY7C453-30JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
CY7C453- 30n
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C453 - 300MB
032
32-Lead (300-Mil) CerDIP
Military
CY7C453-30LMB
L55
32-Pin Rectangular Leadless Chip Carrier
5-136
CY7C455
CY7C456
CY7C457
512 x 18, lK x 18, and 2K x 18
Cascadable Clocked FIFOs
with Programmable Flags
Features
Functional Description
, 512 x 18 (CY7C455), 1,024 x 18
(CY7C456), 2,048 x 18 ( CY7C457)
FIFO buffer memory
,
• Expandable in width
• Expandable in depth
• High-speed 70-MHz standalone;
SO-MHz casc~ded
• Supports free-running 50% duty ~c1e
clock inputs
• Itmpty; Full, Half Full, and programmable Almost Empty and !bnost Full
status flags '
• Parity generation/checking
" Fully asynchronous and 'simultaneous
read and write operatio!l
• Output ~liable (PE) pin
• Independent read and write enable
pins
'
• Center power and ground pins for reduced noise
• 52-pin PLCC and 52-pin PQFP
• Proprietary 0.8f.1 CMOS technology
• TTL compatible
The CY7C455, CY7C456, and CY7C457
arehigh-speed,low-power,first-infirst-out
(FIFO) memories with clocked read and
write interfaces. All are 18 bits wide. The
CY7C455 has a 512-word memory array,
the CY7C456 has a 1,024-word memory
array, and the CY7C457 has a 2,048-word
memory array. The CY7C455, CY7C456,
and CY7C457 can be cascaded to increase
FIFO depth. Programmable features ioelude Almost Full/Emptyflags and generation/checking of parity. These FIFOs provide solutions for a wide variety of data
buffering neilds, including high-speed data
acquisition, multiprocessor interfaces, and
compmnications buffering.
These FIFOs'have 18-bit input and output
ports that are controlled by separate clock
and enable signals. The ioput port is contrOlled, by a free-ru=>OCk (CKW) and
.
a writ!l enable pio (
When ENW is asserted, data is written
into the FIFO on the rising edge of the
Logic Block Diagram
CKW signal. While ENW is held active,
data is continually written into the FIFO
on each CKW cycle. The output port is
controlled in a similar manner by a freerunning read clock (CKR) imd a read enable pin (ENR).
In addition, the
CY7C455, CY7C456, and CY7C457 have
an' output enable pio (OE). The read
(CKR) ~d write (CKW) clocks may be
tieR together for single-clock operation or
the two clocks may be run independently
for asynchronous readlwrite applications.
Clock frequencies up to 71.4 MHz are
achievable in the standalone configuration, and up to 50 MHz is achievable when
FIFOs are cascaded for depth expansion.
Depth expansion is possible using the cascade input (XI), cascade output (;(0), and
First Load (FL) pins. The XO pin is connected to the XI pin of the next device, and
the XO pin of the last device should be
connected to the XI pin of the first device.
The FL pin of the first device is tied tq V ss.
Pin Configuration
PLCC
ThpView
g
rSor!!r!fo~~ ~~
11r==!....L--"'-RF
ElF
86 gg
7 6 5 4 3 2 ~ 1~ 52 51 50 49 48 47 46
013
9
10
11
45
44
43
014
015
0,.
ENW
12
42
CKW
41
40
017
!'[
D2
8
01
Do
XI
RF
13
14
"ElF
15
39
CKR
KO/I'.lIFE
38
37
36
EI'IR
0,
16
17
18
Q2
19
35
Q16
03
20
34
Q15
L-.--r-...r-- 1'I\FEfl(O
00
l\lR
OE
017/PG2/PE2
21 22 23 24 25 26 27 28 29 30 31 32 33
0455-1
00 _ 7. aolPG1iPE1
09_1 •• 0 17/ PG211'E2
CKR
5-138
0455-2
CY7C455
CY7C456
CY7C457
1£~YPRESS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature .................. -65°C to + 150°C
Ambient Thmperature with
Power Applied ....................... - 55° C to + 125 ° C
Supply Voltage to Ground Potential ........ -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -O.5V to +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
Industrial[2]
Ambient
Temperature
O°Cto +70°C
Vee
5V ± 10%
-40°C to +85°C
5V± 10%
Pin Definitions
Signal Name
I/O
Description
DO-17
I
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (Do _ 17) into the
FIFO's memory. IfMR is asserted at the rising edge of CKw, data is written into the FIFO's programming register. DS, 17 are ignored if the device is configured for parity generation.
00-7
09-16
0
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (00 -7, 09 -16)
out of the FIFO's memory. If MR is active at the rising edge of CKR, data is read from the programming
register.
0s/PGl/PE1
017/PG2/PE2
0
Function varies according to mode:
Parity disabled - same function as 00 - 7 and 09 - 16
Parity enabled, generation - parity generation bit (PG.)
Parity enabled, check - Parity Error Flag (PBx)
ENW
I
Enable Write: Enables the CKW input (for both non-program and program modes).
ENR
I
Enable Read: Enables the CKR input (for both non-program and program modes).
CKW
I
Write Clock: The risin~e clocks data into the FIFO when ENW is LOW; updates Half Full, Almost Full, and
Full flag states. When MR is asserted, CKW writes data into the program register.
CKR
I
Read Clock: The rising e~locks data out of the FIFO when ENR is LOW; updates the Empty and Almost
Empty flag states. When MR is asserted, CKR reads data out of the program register.
HF
0
Half Full Flag: Synchronized to CKW
ElF
0
Empty or Full Flag: E is synchronized to CKR; F is synchronized to CKW
PAFE/XO
0
Dual-Mode Pin:
Not Cascaded - programmable Almost Full is synchronized to CKW; Programmable Almost Empty is synchronized to CKR.
Cascaded - expansion out signal, connected to XI of next device.
XI
I
Expansion-In Pin:
Not Cascaded - XI is tied to Vss.
Cascaded - expansion Input, connected to XO of previous device.
FL
I
First Load Pin:
Cascaded - the first device in the daisy chain will have FL tied to V ss; all other devices will have FL tied to V cc
(Figure 1).
Not Cascaded - tied to V ce.
MR
I
Master Reset: Resets device to empty condition.
Non-Programming Mode: Program register is reset to default condition of no parity and PAFE active at 16 or
less locations from Full/Empty.
Programming Mode: Data present on Do _ S is written into the programmable register on the rising edge of
CKW. Program register contents appear on 00 _ S after the rising edge of CKR.
OE
I
Output Enable for 00 _ 7, 09 - 16, 0s/PGl/PE1 and 017/PG2/PE2 pins.
Note:
2. TA is the "instant on" case temperature.
5-140
CY7C455
CY7C456
CY7C457
~YPRESS
Switching Characteristics Over the Operating Rangd3, 15]
Parameter
Description
7C45X-14
7C45X-20
7C45X-30
Min.
Min.
Min.
Max.
Max.
Max.
Unit
l4
20
30
ns
14
20
30
ns
Clock HIGH
6.5
9
12
ns
6.5
9
12
tcKw
Write Clock Cycle
tCKR
Read Clock Cycle
tCKH
tcKL
Clock LOW
tA
Data Access Time
tOH
Previous Output Data Hold After Read HIGH
0
0
0
ns
tFH
Previous Flag Hold After ReadlWrite HIGH
0
0
0
ns
tSD
Data Set-Up
5
7
9
ns
tHD
Data Hold
1
1
1
ns
tSEN
Enable Set-Up
5
7
9
ns
tHEN
EriableHold
1
1
1
toE
tOLZ[9,16]
OE LOW to Output Data Valid
OE LOW to Output Data in Low Z
tOHZ[9,16]
OE HIGH to Output Data in High Z
10
tpG
Read HIGH to Parity Generation
tpE
Read HIGH to Parity Error Flag
tFD
Flag Delay
tSKEW1[17]
Opposite Clock After Clock
0
0
0
tSKEW2[18]
Opposite Clock Before Clock
14
20
30
ns
tpMR
Master Reset Pulse Width
14
20
30
ns
tSCMR
Last Valid Clock LOW Set-Up to l\1R LOW
0
0
0
ns
tOHMR
Data Hold From MR LOW
0
0
0
ns
tMRR
Master Reset Recovery
(MR HIGH Set-Up to First Enabled Write/Read)
14
20
30
ns
tMRF
MR HIGH to Flags Valid
14
20
30
ns
tAMR
MR HIGH to Data Outputs LOW
14
20
30
ns
tSMRP
Program Mode-MR LOW Set-Up
14
20
30
ns
tHMRP
Program Mode-l\1R LOW Hold
10
15
20
ns
tFfP
Program Mode-Write HIGH to Read HIGH
14
20
30
tAP
Program Mode-Data Access Time
tOHP
Program Mode-Data Hold Time from MR HIGH
10
15
10
15
ns
ns
15
20
ns
10
15
20
ns
10
15
20
ns
10
15
20
ns
0
0
14
0
ns
20
0
(MR LOW)
ns
20
20
0
ns
ns
ns
30
0
ns
ns
Notes:
15. Thst conditions assume signal transition time of 3 ns or less, timing reference levels of l.Sv, and output loading as shown in AC Thst Loads
and Wavefonns and capacitance as in notes 10 and 11, unless othetwise
specified.
.
16. At any given temperatnre and voltage condition, tOLZ is greater than
tOHZ for any given device.
17. tSKEW! is the minimnm time an opposite clock can occur after a clock
and still be gnaranteed not to be included in the current clock cycle (for
purposes offlag update). If the opposite clock occurs less than tSKEW!
after the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. Note: The opposite clock is
the signal to which a flag is not synchronized; i.e., CKW is the opposite
clock for Empty and Almost Empty flags, and CKR is the the opposite
clock for the Almost Full, Half Full, and Full flags. The clock is the sig·
nal to which a flag is synchronized; i.e., CKW is the clock for theHalf
Full, Almost Full, and Full flags, and CKR is the clock for Empty and
Almost Empty flags.
18. tSKEW2is the minimum time an opposite clock can occur before aclock
and still be guaranteed to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEW2
before the clock, the decision of whether arnot to include the opposite
clock in the current clock cycle is arbitrary. See Note 17 for definition
of clock and opposite clock.
5-142
CY7C455
CY7C456
CY7C457
-==:::4:
7 CYPRESS
Switching Waveforms (continued)
Master Reset (Programming Mode) Timing Diagram[21, 22]
CKW
DO-17
CKR
LOW
00-17
ALL DATA
OUTPUTS LOW
VALID DATA
c455-9
Master Reset (Programming Mode with Free-Running Clocks) Timing Diagram[21, 22]
1+-----
tHMRP
CKW
DO -17
CKR
00-17
ALL DATA
---_---/
QUTPUT$LQW
c455-10
Notes:
19. To only perform reset (no programming), the following criteria must
be met: ENW or CKW must be inactive while MR is LOW
20. To only ~rm reset (~o programming), the following criteria must
be met: ENR or CKR must be inactive while MR is LOW.
21. All data outputs (Qo -17) go LOW as a result ofthe rising edge ofMR
aftertAMR'
22. In this example, Qo _ 17 will remain valid until tOHMR if either the first
read shown did not occur or if the read occurred soon enough such that
the valid data was caused by it.
5-144
CY7C455
CY7C456
CY7C457
Switching Waveforms (continued)
Read to Almost Empty Timing Diagram with Free-Running Clocks[23, 26, 28]
COUNT
17
16
17
17
18
16
15
CKR
CKW
HF
HIGH
HIGH
Read to Almost Empty Timing Diagram with Read Flag Update Cycle with Free-Running Clocks[23, 26, 28, 29, 30]
18 (no change)
COUNT
17
16
17
FLAG UPDATE CYCLE
18
17
16
15
CKR
BifR
CKW
ENVY
RF
HIGH
ElF
HIGH
lFO
J5.li.lt
=t
0455-14
Notes:
28. The FIFO in this example is assumed to be programmed to its default
flag values. Almost Empty is 16 words from Empty; Almost Full is 16
locations from Full.
29. R4 only updates the flag status. It does not affect the count because
ENRisHIGH.
.
30. When making the transition from Almost Empty to Intermediate, the
count must increase by two (16 .18; two enabled writes: W2, W3) before a read (R4) can update flags to the Less Than Half Fu!! state.
5-146
CY7C455
CY7C456
CY7C457
vIi~?cYPRESS
Switching Waveforms
(continued)
Write to Almost Full Timing Diagram[23, 28, 31, 36, 37]
COUNT
2030
[1016)
[494)
2031
[1017)
[495)
2032
[1018)
[496)
2031
2030
[1016)
[494)
[1Jlis?
CKW
EJIlW
,
LOW
,
-------------+-------+--------+---4_------~--------4_-------
CKR
LOW
HF
LOW
------------------------------------------------------------HIGH
0455·17
Write to Almost Full Timing Diagram with Free-Running Clocks[23, 28, 31]
COUNT
2031
[1017)
[495)
2032
[1018)
[496)
2031
~017)
495)
2031
[1017)
[495)
2030
[1016)
[494)
2032
[1018)
[49B)
2033
[1019)
[497)
CKW
EJIlW
CKR
EN"FI
RF
LOW
ElF
HIGH
PAFE
tFD1______________________tF_D~-----t-FD-~________
c455-18
Notes:
36. W2 updates the flag to the Almost Full state by asserting PAFE. Be·
cause Rl occurs greater thau tSKEW! after W2, W2 does not recognize
Rl when updating flag status. W3 includes R2 in the flag update be·
cause R2 occurs greater thau tSKEW2 before W3. Note that W3 does
not have to be enabled to update flags.
37. ThedashedlinesshowW3asaflagupdatewriteratherthanauenabied
write because ENW is HIGH.
5-148
CY7C455
CY7C456
CY7C457
~YPRESS
Switching Waveforms (continued)
Even Parity Generation Timing Dlagram[39, 40]
CKR ____________
J5I:1 , (PE21
~
.
ENABLED READ
r-
tpG
"-.. _______-J/
DISABLED READ " ..._ _ _ _ _ __
----I
--------------------~
00-7
PREVIOUS WORD:
NEW WORD:
ODD NUMBER OF 1S
(09 _ 16) __E;;.V,;;E;,,;N;,,;N,;,UM,;,B;,;E;;.R..;O,;,F.,;,lS;...._ _,
;(XXXXy
'
20.00
~
g
5
~
o
W
0.90
a:
0
Z
O.BO L -_ _--'--_ _---'-_ _----'
-55.00
5.00
65.00
125.00
M
1
Vee = 5.0V
1.00 I- TA = 25°C
VIN = 3.0V
0.90
O.BO
0.70
0.60
30.00
AMBIENT TEMPERATURE (0C)
~
0.00
0.00
~
«
::;;
VIN = 3.0V
Vee = 5.0V
f= 71 MHz
I 100.00
10.00
1l
c
60.00
40.00
1.10
1.00 i----F"'_=--t-----j
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
50.00
0.00 "------'----------'
0.00
500.00
1000.00
125.00
1.20 , - - - - , - - - - - - , - - - - ,
1.00
1-----.,"--\------1
5.00 1--/----
1.40 ,-----,---,-----,----,
~
!5Z
i------+--~=---j
'iii"
I~
Vee = 5.0V
TA = 25°C
,
I
1.00
!ZW
2.00
a:
a:
:::>
u
60.00
40.00
5
20.00
""
3.00
§
4.00
OUTPUT VOLTAGE M
45.00
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
80.00
Z
/
/
/
0.00
0.00
/
/
Vee = 5.0V
TA= 25°C
I
1.00
2.00
3.00
OUTPUT VOLTAGE
5-156
/
60.00
FREQUENCY (MHz)
l<:
i'ii
V
/
M
4.00
75.00
CY7C460
CY7C462
CY7C464
Cascadable 8K X 9 FIFO
Cascadable 16Kx 9 FIFO
Cascadable 32K X 9 FIFO
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
data outputs go to the high-impedance
state when R is HIGH.
A Half Full (HF) output flag is provided
that is valid in the standalone (single device) and width expansion configurations.
In the depth expansion configuration, this
pin provides the expansion out (XO) information that is used to tell the next FIFO
that it will be activated.
In the standalone and width expansion
configurations, a LOW on the retransmit
(RT) input causes the FIFOs to retransmit
the data. Read enable (R) and write enable
(W) must both be HIGH during a retransmit cycle, and then R is used to access the
data.
The CY7C460, CY7C462, and CY7C464
are fabricated using an advanced O.Smicron N-well CMOS technology. Input
ESD protection is greater than 2000V and
latch-up is prevented by careful layout,
guard rings, and a substrate bias generator.
Functional· Description
8K x 9 FIFO (CY7C460)
16K x 9 FIFO (CY7C462)
32K x 9 FIFO (CY7C464)
Asynchronous read/write
High-speed 33.3-MHz read/write
independent of depth/width
Low operating power
-Icc = 70 rnA (max.)
Half Full flag in standalone
Empty and Full flags
Retransmit in standalone
Expandable in width and depth
SV ± 10% supply
PLCC, LCC, and 600-mil DIP
packaging
TIL compatible
Three-state outputs
Pin compatible and functionally
equivalent to IDT720S, IDT7206
Logic Block Diagram
The CY7C460, CY7C462, and CY7C464
are respectively, SK, 16K, and 32K words
by 9-bit wide first-in-first-out (FIFO) memories. Each FIFO memory is organized
such that the data is read in the same sequential order that it was written. FuJI and
Empty flags are provided to prevent overrun and underrun. Three additional pins
are also provided to facilitate unlimited expansion in width, depth, or both. The
depth expansion technique steers the control signals from one device to another in
parallel, thus eliminating the serial addition of propagation delays, so that
throughput is not reduced. Data is steered
in a similar manner.
The read and write operations may be
asynchronous; each can occur at a rate of
33.3 MHz. The wtite operation occurs
when the write (W) signal is LOW. Read
occurs when read (R) goes LOW. The nine
Pin Configurations
DATA INPUTS
(Do-Os)
DIP
Top View
PLCC/LCC
Top View
4
02
5
0,
6
Do
7
XI
8
FF
9
Co
10
11
3
2 111 323130
L.
7C460
7C462
70464
29
28
27
0,
0.,
NC
26
F[JRT
25
24
23
MR
El'
12
22
13
21
14 151617181920
d" d" §!
"
l1 10: d' c!'
C461).2
lm/Rl'
Or
a,
W
Vee
08
04
05
03
O2
01
Do
XI
FF
00
01
02
03
Os
GNO
06
07
mAT
MR
Er
lID/RF
07
06
05
04
f!(
C460·3
5-158
CY7C460
CY7C462
CY7C464
.?cYPRESS
Electrical Characteristics Over the Operating Range (continued)[2]
7C460-40
7C462-40
7C464-40
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VIL
Ilx
IoZ
lee
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
R~ VIH,GND~ Vo~ Vee
Vee = Max., lOUT = 0 rnA
ISBI
Standby Current
All Inputs =VIH Min.
Power-Down Current
ISB2
Output Short
Circuit cUrrent[3]
los
Min.
Test Conditions
VOR
VOL
VIH
Min.
2.2
2.2
-10
-10
GND~VI~Vee
Corn'l
MilIInd
Corn'l
Mil/Ind
corn'l
Mil/Ind
Vee - Max., VOUT - GND
Max.
Unit
0.4
V
V
V
0.8
+10
+10
70
!lA
!lA
rnA
25
rnA
30
20
rnA
2.4
0.4
Corn'l
Mil/Ind
All Inputs Vee - O.ZV
Max.
2.4
Vee - Min., lOR - -2.0 rnA
Vee = Min., IOL = 8.0 rnA
7C460-65
7C462-65
7C464-65
2.2
2.2
0.8
+10
+10
70
75
25
30
-10
-10
20
V
25
25
-90
-90
rnA
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
CoUT
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 4.5V
Max.'
10
12
Unit
pF
pF
AC Test Loads and Waveforms
"1" 0""':: '" "1"
0""'::;: "", II
3330
INCLUDING _
_
C460-4
JIG AND SCOPE (a) Normal Load
II
INCLUDING _
JIG AND SCOPE
3330
_
-
C460·5
(b) High-Z Load
THEvENIN EQUIVALENT
2000
OUTPUT Oo--_"N~'___--oO 2V
Equivalent to:
Not.s:
4. lOsted initially and after any design or process changes that may affect
these parameters.
5-160
ALL INPUT PULSES
~s
C460-6
CY7C460
CY7C462
cY7C464
~CYPRESS
Switching Wavefonns[7]
Asynchronous Read and Write
'..
14----
FI --"""",
~-:--;:-{I+---==tPW---'-K='_Dt}=~C~-tH~DtWR~~~~.~
. ::L
::",l.o~
)I-------i<"Do-DB
DATA VALID
tptMRMRSC
Mast~r~set
DATA VALID
.~
I---tEFL~
I--tHFH
~..
C460-7
[9J
FI, WIBJ
RF
.)1)1----
twpw ..
3
tRMR-
x+
f'
~tFFH
~ xxxxxxxxxxxxxxx?
C480-8
Half Full Flag
HALF FULL
HALF FULL +1
iN
RF
/
"-
I-tWHFj
HALF FULL
- tRHF
~
"""
I
Las~ Write
~
C460-9
to First Read Full Flag
LAST WRITE
FI-~------+~
ADDITIONAL
READS
FIRST READ
FIRST WRITE
W---.--..,
f!I'--t--"""'"
C460-10
Note.:
7_ AHIGH-to-LOW transition of either the write or read strobe causes
a HIGH-to-WW transition of the responding flag_ Correspondingly,
~;.?W-tO-HIGH strobe transition causes a LOW-to-HIGH flag transi-
8_
9_
5-162
Wand R = VIH around the rising edge ofMR_
tMRSC = tpMR + tRMR-
CY7C460
CY7C462
CY7C464
.rcYPRESS
Switching Waveforms (continued)
Empty Flag and Read Data Flow-Through Mode
C460-14
Expansion Timing Diagrams
w---"'
lID1(X12l[12]
--------------I=:=j-
C460-15
QO-Q8-----;--------~
Note:
12_ ~sion out of device 1 (XOl) is connected to expansion in of device
2 (XI2)'
5-164
CY7C460
CY7C462
CY7C464
~YPRESS
lxo
w
R
EF
l'F
9,
0
I
I
/
9,,,,-
/-y
1
I
CY7C460
CY7C462
CY7C464
1
9
/
.--
L...1'[
=f>
Vcc
XI
xo
l'OII
EF
l'F
9, "-
7-y
EI\lm
CY7C460
CY7C462
CY7C464
l'[
I------
f--J
XI
XO
I....--
9."
7
lIS
*
l'F
f' -y
'I-"
EF
f---
CY7C460
CY7C462
CY7C464
l'[
-=
XI
.
FIRST DEVICE
C460-17
Figure 1. Depth Expansion
5-166
CY7C460
CY7C462
CY7C464
.ircYPRESS
Ordering Information
Speed
(ns)
15
20
25
40
65
Speed
(ns)
15
20
25
40
65
Ordering Code
CY7C460-15JC
CY7C460-15PC
Package
Name
Package 'Jh!e
Operating
Range
J65
P15
32-Lead Plastic Leaded Chip Carrier
28-Lelfd (600cMil) Molded DIP
Commercial
CY7C460-15JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C460-20DMB
28-Lead (600-Mil) Sidebraze CerD~P
32-Pin Rectangular Leadless Chip Carrier
Military
CY7C460~20LMB
D43
L55
CY7C460-25JC
CY7C460-25PC
J65
P15
32-Lead Plastic Leaded Chip Carrier
28-Lea(j (600-Mil) MOlded DIP
Commercial
CY7C460-25JI
J65
32-Lea(j Plastic Leaded Chip Carrier
Industrial
CY7C460- 25DMB
D43
28-~ad
Military
CY7C460-25LMB
L55
32-fin'Rectangular Leadless Chip Carrier
CY7C460-40JC
CY7C460-40PC
J65
P15
32-~ead
Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Commercial
CY7C460-40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C460-40DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C460-40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C46p-65JC
CY70160-65PC
J65
P15
32-Lead Plastic Leaded Chip Carrier
28~Lead (600-Mil) Molded DIP
Commercial
CY7C460-65JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
(600-Mil) Sidebraze CerDIP
Operating
Range
Commercial
Ordering Code
CY7C462-15JC
Package
Name
J65
CY7C462-15PC
P15
28-Lead (600-Mil) Molded DIP
CY7C462-15JI
J65
32-Lelfd Plastic Leaded Chip Carrier
Industrial
CY7C46:2-20DMB
D43
28-L~ad
Military
CY7C462- 20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C462-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C462-25PC
P15
48-Lead (600-Mil) Molded DIP
CY7C462-25JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C462-25DMB
D43
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C462-25LMB
32-Pin Rectangular Leadless Chip Carrier
CY7C462-40JC
L55
J65
CY7C462-40PC
P15
28-Lead (600-Mil) Molded DIP
Package 'IYPe
32-Lead Plastic Leaded Chip Carrier
32-Le~d
(600-Mil) Sidebraze CerDIP
Plastic Leaded Chip Carrier
Commercial
Commercial
CY7C462-40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C462-40DMB
D4~
28-Lead (600-Mil) Sidebraze CerDIP
Military
CY7C462-40LMB
L55
32-Pin Rect;lDgular Leadless Chip Carrier
CY7C462-65JC
J65
32-Lead Plastic Leaded Chip Carrier
CY70162-65PC
P15
28-Lead (600-Mil) Molded DIP
CY7C4!i2-65JI
~65
32-Lead Plastic 4aded Chip Carrier
5-168
Commercial
Industrial
CY7C460
CY7C462
CY7C464
~CYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIH
VILMax.
IIX
Icc
ISB1
IiJB2
los
Ioz
Switching Characteristics
Parameter
S'!:bgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
tRC
tA
tRR
tpR
tLZR
tDVR
tHZR
twc
tpw
tHWz
tWR
tSD
tHD
tMRSC
tpMR
tRMR
tRPW
twpw
tRTC
tpRT
tRTR
tEFL
tHFH
tFFH
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
tRAE
tRPE
tWAF
tWPF
tXOL
tXOH
Document#:
5-170
Subgroups
9,10, i1
9,10, it
9, W' 11
9, 1~; 11
9,10,11
9,,10,11
~; lQ, 11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
,9,10, it
9,10,11
9,10,11
9,10,11
9,10,11
38-00141-G
CY7C470
CY7C472
CY7C474
W?cYPRESS
Selection Guide
Frequency (MHz)
Maximum Access Time (ns)
Maximum Operating Current (rnA)
I
I
7C470-15
7C472-15
7C474-15
33.3
15
105
Commercial
Military/Industrial
7C470-20
7C472-20
7C474-20
33.3
20
7C470-25
7C472-25
7C474-25
28.5
25
90
95
110
7C470-40
7C472-40
7C474-40
20
40
70
75
Maximum Ratings
Storage Temperature .................. -65°C to + 150°C
Ambient Thmperature with
Power Applied ....................... -55°C to +125°C
Supply Voltage to Ground Potential ........ -O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to +7.0V
DC Input Voltage ....................... -3.0V to +7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . • . . . . .. 1.0W
Output Current, into Outputs (LOW) . ; . . . . . . . . . . .. 20 rnA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
O°C to +70°C
Range
Commercial
Industrial
Military[J]
Vee
5V ± 10%
-40°C to +85°C
5V ± 10%
-55°C to + 125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangd2]
7C470-15
7C472-15
7C474-15
Parameter
VOH
VOL
VIH
VIL
IIX
loz
Icc
ISB!
ISB2
10SI'1
Description
Output HIGH Voltage
Output WW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
Power-Down Current
Output Short Circuit Current
Test Conditions
Vee
Vee
= Min., 10H = -2.0 rnA
= Min., 10L = 8.0 rnA
0.4
GND5VI5 Vee
R:.2:. VIH, GND 5 Va < Vee
Com'l
Vee = Max.,
lOUT = ornA
MiII/lnd
Com'l
All Inputs =
VIHMin.
MiVlnd
Com'l
All Inputs =
Vee - O.2V
MiIJInd
Vee - Max., VOUT - GND
-10
-10
5-172
2.4
2.4
2.2
3.
7C470-25
7C472-25
7C474-25
Min. Max. Min. Max. Min. Max.
Com'l
MiIJInd
Note.:
1. TA is the "instaot on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
7C470-20
7C472-20
7C474-20
2.4
0.4
2.2
2.2
2.2
0.8
+10
+10
105
-10
-10
0.8
+10
+10
110
25
30
20
25
-90
0.4
-90
-10
-10
0.8
+10
+10
90
95
25
30
20
25
-90
Unit
V
V
V
V
JAA
JAA
rnA
rnA
rnA
rnA
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second.
CY7C470
CY7C472
CY7C474
iiiircYPRESS
Switching Characteristics Over the Operating Range15, 6]
7C470-15
7C472-15
7C474-15
Parameter
Description
Min.
7C470-20
7C472-20
7C474-20
Max.
30
Min.
Max.
30
7C470-25
7C472-25
7C474-25
Min.
Max.
35
7C470-40
7C472-40
7C474-40
Min.
Max.
50
Unit
tcy
Cycle Time
tA
Access Time
tRY
Recovery Time
15
10
10
10
ns
tpw
Pulse Width
15
20
25
40
ns
tLZR
Read LOW to Low Z
3
3
3
3
ns
tOyl7]
Valid Data from Read HIGH
3
3
3
3
tHZ!7]
Read HIGH to High Z
15
20
15
15
ns
40
25
18
ns
ns
25
ns
tHWZ
Write HIGH to Low Z
5
5
5
5
tso
Data Set-Up Time
11
12
15
20
ns
tHO
Data Hold Time
0
0
0
0
ns
ns
15
20
25
40
ns
25
30
35
50
ns
HFDelay
25
30
35
50
ns
tAFEO
PAFEDelay
25
30
35
50
ns
tRAE
Effective Read from
Write HIGH
15
20
25
40
ns
tWAF
Effective Write from
Read HIGH
15
20
25
40
ns
tEFD
E/FDelay
tEFL
MRto ElF
tHFo
ww
Notes:
5.
6.
Thst conditions assume signal traosmission time of 5 ns or less, timing
reference levels of 1.5V aod output loading of the specified IOrJIOH
aod 30-pF load capacitance, as in part (a) of AC Thst Load aod Waveforms, unless otherwise specified.
See the last page of this specification for Group A subgroup testing
7.
infonnatiofl.
5-174
tHZR and tDVR use capacitance loading as in part (b) ofAC Test Loads.
tHzR traosition is measured at +500mV from VOLaod -500mVfrom
VOH. tDVR transition is measured at the 1.5V level. tHwz and tLZR
transition is measured at ± 100 mV from the steady state.
CY7C470
CY7C472
CY7C474
a
=:'rcYPRESS
Switching Waveforms (continued)
EiF Flag (Last Write to First Read Full Flag)
W
L·1
R"
EfF
Rl'
FULL-1
FULL
FULL-1
/
\
t=~j-
LOW
7C410-10
EiF Flag (Last Read to First Write Empty Flag)
R
EMPTY +1
w
ElF
t~1
EMPTY
EMPTY +1
/
\
t=~j-
HIGH
7C470-11
Half Full Flag
W
HALF-FULL
HALF-FULL +1
R
RF
HALF-FULL
\
~'~1
Hrnj7C470-12
5-176
CY7C470
CY7C472
CY7C474
~YPRESS
Switching Waveforms (continued)
Mark
Icy
ICY
W.R
~
.. IRV" i - - I p w -
r-- IRV --I
70470-16
Empty Flag and Read Data Flow-Through Mode
DATAIN
w
ElF
DATA OUT
--1r-----------------..;...----------+---,.
---r----'-----t;=::3
----t--------I-~ryV"V"i~r----....
70470-17
5-178
CY7C470
CY7C472
CY7C474
~YPRESS
Table I. Flag Truth Table[!3]
IIF
EiF
JiAFE
1
0
0
Empty
1
1
0
Almost Empty
CY77C470
(8Kx9)
Number of Words in
FIFO
State
1
1
1
Less than Half Full
0
1
1
Greater than Half Full
0
1
0
Almost Full
0
0
0
Full
CY77C472
(16K x 9)
Number of Words in
FIFO
CY77C474
(32Kx9)
Number of Words in
FIFO
0
0
0
1 • (P - 1)
U (P -1)
U(P -1)
P.4096
P.8192
P .16384
4097 • (8192 - P)
8193 • (16384 - P)
16385 • (32768 - P)
(8192 - P+1). 8191
(16384 - P+1). 16383
(32768 - P+1). 32767
8192
16384
32768
Table 2. Programmable Almost FuIlJEmpty Options[14]
D3
D2
DI
DO
0
0
0
0
0
0
0
1
16 or less locations from EmptylFull
16
0
0
1
0
32 or less locations from EmptylFull
32
0
0
1
1
64 or less locations from EmptylFull
64
0
1
0
0
128 or less locations from EmptylFull
128
0
1
0
1
256 or less locations from EmptylFull (default)
256
0
1
1
0
512 or less locations from EmptylFull
512
0
1
1
1
1024 or less locations from EmptylFull
1024
1
0
0
0
2048 or less locations from EmptylFull
2048
1
0
0
1
4098 or less locations from EmptylFull[15]
4098
1
0
1
0
8192 or less locations from EmptylFull[16]
8192
P
PAFE Active when:
256 or less locations from EmptylFull (default)
Notes:
13. See Table 2 for P values.
14. Almost flags default to 256 locations from Empty/Full.
15. Only for CY7C472 and CY7C474.
16. Only for CY7C470.
5-180
256
CY7C470
CY7C472
CY7C474
Ordering Information
Speed
(ns)
15
20
25
40
Speed
(ns)
15
20
25
40
Ordering Code
Package
Name
Package 'JYpe
Operating
Range
CY7C470-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470-15PC
PI5
28-Lead (600-MiI) Molded DIP
CY7C470-I5JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C470-200MB
043
28-Lead (600-MiI) Sidebraze CerDIP
Military
CY7C470-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C470-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470-25PC
P15
28-Lead (600-MiI) Molded DIP
CY7C470-25JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C470-250MB
043
28-Lead (600-MiI) Sidebraze CerDIP
Military
CY7C470-25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C470-40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470-40PC
P15
28-Lead (600-MiI) Molded DIP
CY7C470-40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C470-400MB
043
28-Lead (600-MiI) Sidebraze CerDIP
Military
CY7C470-40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Package
Name
Package 'JYpe
Ordering Code
Commercial
Commercial
Commercial
Operating
Range
Commercial
CY7C472-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C472-15PC
P15
28-Lead (600-MiI) Molded DIP
CY7C472-I5JI
J65
043
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C472- 200MB
28-Lead (600-MiI) Sidebraze CerDIP
Military
CY7C472-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C472-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C472-25PC
P15
28-Lead (600-MiI) Molded DIP
CY7C472-25JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C472-250MB
043
28-Lead (600-MiI) Sidebraze CerDIP
Military
CY7C472-25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C472-40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C472-40PC
P15
28-Lead (600-MiI) Molded DIP
CY7C472-40JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7C472-400MB
043
28-Lead (600-MiI) Sidebraze CerDIP
Military
CY7C472-40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
5-182
Commercial
Commercial
~
=-- -., ~
'CYPRESS
Dual-Port Memories
Device
CY7C006
CY7C016
CY7C024
CY7C0241
CY7C025
CY7C0251
CY7C130
CY7C131
CY7C140
CY7C141
CY7C132
CY7C136
CY7C142
CY7C146
CY7C133
CY7C143
CY7B134
CY7B135
CY7B1342
CY7B138
CY7B139
CY7B144
CY7B145
Section Contents
Page Number
Description
16K x 8 Dual-Port Static RAM with Sem, lnt, Busy ................................. 6-1
16K x 9 Dual-Port Static RAM with Sem, lnt, Busy ................................. 6-1
4K x 16 Dual-Port Static RAM with Sem, lnt, Busy ................................ 6-18
4K x 18 Dual-Port Static RAM with Sem, lnt, Busy ................................ 6-18
8Kx 16 Dual-Port Static RAM with Sem, lnt, Busy ................................ 6-18
8K x 18 Dual-Port Static RAM with Sem, lnt, Busy ................................ 6-18
lK x 8 Dual-Port Static RAM .................................................. 6-37
lK x 8 Dual-Port Static RAM
6-37
lK x 8 Dual-Port Static RAM
6-37
lKx 8 Dual-Port Static RAM
6-37
6-50
2K x 8 Dual-Port Static RAM
2K x 8 Dual-Port Static RAM
6-50
6-50
2K x 8 Dual-Port Static RAM
2Kx 8 Dual-Port Static RAM .................................................. 6-50
2Kx 16 Dual-Port Static RAM ................................................. 6-63
2Kx 16 Dual-Port Static RAM ................................................. 6-63
4Kx 8 Dual-Port Static RAM .................................................. 6-74
4Kx8 Dual-Port Static RAM .................................................. 6-74
4K x 8 Dual-Port Static RAM with Semaphores ................................... 6-74
4K x 8 Dual-Port Static RAM with Sem, lnt, Busy ................................. 6-87
4K x 9 Dual-Port Static RAM with Sem, lnt, Busy ................................. 6-87
8K x 8 Dual-Port Static RAM with Sem, lnt, Busy ................................ 6-103
8K x 9 Dual-Port Static RAM with Sem, lnt, Busy ................................ 6-103
.-=-.
~ -.,~
CY7C006
CY7C016
PRELIMINARY
'CYPRESS
Pin Configurations
68·Pin LCC/PLCC
Top View
~
6
8~1u11~1~1u1()
;::, ::::. Z 0 a: en () Z
l/02L
I/03L
I/04 L
~ ~~~~ ~
..J
« >8 « « « « «a:l « ,Jf
ASl
A.,l
11
A"
A2L
A"
Aol
TNTl
IJOsL
GND
I/OSL
I/0 7l
BUSYL
Vee
GND
18
I/OOR
19
CY7C006/16
GND
51
I/01R
I/02R
MIS
BUSY'R
TNTA
ADA
A'A
Vee
I/0 3R
I/0 4R
A2A
A3A
A.,A
I{GSR
I/OBR
C006-2
64·Pin TQFP
Top View
al~~I~I~ ~ 8 ~ ~ ~ ffi ~ ~ ~ ~
::::.::::.oO:::CI)()c:(>««««««./f 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Nole:
4. Pulse width < 20 ns.
6-4
Range
Commercial
Industrial
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
-40°C to +85°C
5V ± 10%
CY7COO6
CY7C016
PRELIMINARY
Capacitance[7]
Parameter
Thst Conditions
Description
Input Capacitance
Output Capacitance
CIN
COUT
:rt
1
Rl = 8930
RTH = 2500
OUTPUT~
R2 = 3470
C=30pF
I
1
-=
(b) Thevenin Equivalent (Load 1)
R1 = 8930
R2 = 3470
-=
(e) Three-State Delay (Load 3)
COOS-6
c006-5
1
:rl
C = 5 pF
VTH = l.4V
(a) Normal Load (Load 1)
OUTPUT
OUTPUT
1
-=
-=
pF
pF
5V
5V
C = 30 pF
Unit
10
10
TA = 25°C, f = 1 MHz,
Vcc= 5.OV
AC Test Loads and Waveforms
OUTPUT
Max.
C006-7
ALL INPUT PULSES
I
C =30 PF
90%
3'OV~
10%
~
10%
GND
53ns
53ns
Load (Load 2)
C006-9
COO6-8
Switching Characteristics Over the Operating Range!5, 8]
Parameter
READ CYCLE
Description
I
7COO6-15
7C016-15
Min. I Max.
15
7COO6-25
7C016-25
Min. I Max.
25
7COO6-35
7C016-35
Min. I Max.
35
I
7COO6-55
7C016-55
Min. I Max.
55
I
Unit
ns
tRe
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE
CE LOW to Data Valid
15
25
35
55
ns
tDOE
tLZOE[9,1O]
OE LOW to Data Valid
10
13
20
25
ns
tHZOE[9,IO]
OE HIGH to High Z
25
ns
tLZCE[9,1O]
CE LOW to Low Z
tHZCE[9,1O]
CE HIGH to High Z
25
ns
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Down
OE Low to Low Z
15
25
3
3
3
3
3
10
3
3
0
0
15
0
25
9.
ns
3
15
ns
0
35
ns
ns
3
15
15
10
55
3
3
15
3
Notes:
7. Thsted initially and after any design or process changes that may affect
these parameters.
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified ImlloH and 30-pF load capacitance.
35
ns
55
ns
At any given temperature and voltage condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE.
10. Thst conditions used are Load 3.
6-6
1£
i/EYPRESS
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[15, 16]
~~
_ _ _
tRC
ADDRESS
CY7C006
CY7C016
PRELIMINARY
_----'---*_
-:!=OA:::!;XXXX*. ._-_-_-_-_-_-_-_-_-_-_-_-D_A"-:[~A~V_A-L~ID~ ~ ~ ~ ~ ~-=
DATA OUT
coos
10
Read Cycle No.2 (Either Port CE/OE Access)[15, 17, 18]
SEIiif or CE
DATAOUT--~~--_=----------~~~~~~------~~~~~----_+----~~~---ICC
ISB
Read Timing with Port·to-Port Delay
(MIS = L)[19,20]
twc
ADDRESSR
(
)
MATCH
tPWE
RiWR
~
./
~tso
~
DATAINR
ADDRESSL
~
*10
VALID
MATCH
tO~~
)Il'
DATAouTL
)K
VALID
twoo
C006-12
Noles:
15, R/W is HIGH for read cycle.
16. Device is continuously selected CE LOW and OE LOW. This
waveform cannot be used for semaphore reads.
17. Address valid prior to or coincident with CE transition LOW.
=
=
=
=
18. CEL L, SEM H when accessing RAM. CE
accessing semaphores.
19. BUSY = HIGH for the writing port.
20. CEL = "CIlR = LOW.
6-8
=H, SEM =L when
#t_-:::.z
.'CYPRESS
CY7C006
CY7C016
PRELIMINARY
Switching Wavefonns (continued)
Semaphore Read After Write Timing, Either Side[25]
1/°0
DATAouT VALID
R/W
COO6-15
Semaphore Contention[26, 27, 28]
~L-A2L ____________________M_A_J_C_H____________________-J~~___________________
MATCH
SEMR _ _ _ _ _ _ _ _ _ _ _ ~
COO6-16
Notes:
25. CE = HIGH for the duration of the above timing (both write and read
cycle).
26. I/OOR = I/OOL = LOW (request semaphore); CER = CEL = HIGH
27. Semaphores are reset (available to both ports) at cycle start.
28. If tsps is violated, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control the
semaphore.
6-10
1;~YPRESS
PRELIMINARY
CY7COO6
CY7C016
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration) [29]
CEL Valid First:
X
ADDRESSL,R
~"b
GEL
CER
BOSYR
tBLC~
CER Valid FirSt:
X
ADDRESSL,R
GEL
t-l
tBLC~
mm'i'L
c006-l9
X
ADDRESS MATCH
~"b .
CER
X
ADDRESS MATCH
t~'l
C006-20
Busy Timing Diagram No.2 (Address Arbitration)[29]
Left Address Valid First:
tRcortWC
~
ADDRESSL
ADDRESS MATCH
j t!
ADDRESS MISMATCH
_tps-
)Il'
ADDRESSR
i+-tBLA
mm'i'R
-tBHA
- - - - : j _ _=1,-----COO6-2l
1'-1
Right Address Valid First:
tRC ortwc
ADDRESSR
~
ADDRESS MATCH
ADDRESS MISMATCH
_tpsADDRESS L
'W"
--::j~=1,-i'-------{
C006-22
f4-- tBLA
BUSYL
-tBHA
Note:
29. If tps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
30. lHA depends on which enable pin (CEL or RJWLl is deasserted first.
31. tINS or tlNR depends on which enable pin (CEL or RJWLl is asserted
last.
6-12
CY7C006
CY7C016
PRELIMINARY
Architecture
Interrupts
The CY7C006/016 consists of a an array of 16K words of 8/9 bits
each of du~ortRAM cells, I/O and address lines, and control signals (CE, OE, RiW). These control pins permit independent access for reads or writes to any location in memory. Th handle simultaneous writes/reads to the same location, a BUSY pin is provided
on each port. Two interrupt (INT) pins can be utilized for port-toport communication. Tho semaphore (SEM) control E!ns are used
for allocating shared resources. With the MIS pin, the
CY7C006/016 can function as a Master (BUSY pins are outputs)
or as a slave (BUSY pins are inputs). The CY7C006/016 has an automatic power-down feature controlled ELCE. Each port is provided with its own output enable control (OE), which allows data to
be read from the device.
The interrupt flag (INT) permits communications between
ports. When the left port writes to location 3FFE(HEX), the right
port's interrupt flag (OOR) is set. This flag is cleared when the
rls!!!port reads that same location. Setting the left port's interrupt flag
(INTd is accomplished when the right port writes to location
3FFE(HEX). This flag is cleared when the left port reads location
3FFE(HEX). The message at 3F~HE29 is user-defined. See
Table 2 for input requirements for INT. INTR and INTL are pushpull outputs and do not require pull-up resistors to operate.
Busy
Functional Description
Write Operation
D~ must be set
up for a duration of tSD before the rising edge of
R/W in order to guarantee a valid write. A write operation is controlle'!Ey either the OE pin (see Write Cycle No.1 waveform) or
the R/W pin (see Write Cycle No. 2waveform). Datacanbewritten
to the device tHZOJiafter the OE is deasserted or tHzWE after the
falling edge of R/W. Required inputs for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
Table 1. Non-Contending ReadlWrite
Inputs
OE
Outputs
CE
R/W
H
X
X
H
HighZ
Power-Down
H
H
L
L
Data Out
Read Data in
Semaphore
X
H
X
HighZ
I/O Lines Disabled
X
L
Data In
Write to Semaphore
X
H
S
SEM
1/0 0-7
Operation
L
H
L
H
Data Out
Read
L
L
X
H
Data In
Write
L
X
X
L
Illegal Condition
Read Operation
When reading the device, the user must assert both the OE and CE
pins. Data will be available tACE after CE or tDOE after OE are asserted. If the user of the CY7C006/016 wishes to access a semaphore
flag, then the SEM pin must be asserted instead of the CE pin.
The CY7C006/016 provides on-chip arbitration to alleviate simultaneous memory location access (contention). If both ports' CBs
are asserted and an address match occurs within tps of each other
the Busy logic will determine which port has access. If tps is violated, one port will definitely gain permission to the location, but it
is not guaranteed which one. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken LOW. BUSYL and
BUSYR in master mode are push-pull outputs and do not require
pull-up resistors to operate.
Master/Slave
An MIS pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output
ofthe master is connected to the BUSY input of the slave. This will
allow the device to interface to a master device with no external
cOifonents.Writing of slave devices must be delayed until after
the USY input has settled. Otherwise, the slave chip may begin a
write cycle during a contention situation. When presented a HIGH
input, the MIS
allows the device to be used as a master and
therefore the BYline is an output. BUSY can then be used to
send the arbitration outcome to a slave.
Semaphore Operation
gs
The CY7C006/016 provides eight semaphore latches which are
separate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given resource,
it sets a latch by writing a 0 to a semaphore location. The left port
then verifies its success in setting the latch by reading it. Mter
writing to the semaphore, SEM or OE must be deasserted for
tsop before attempting to read the semaphore. The semaphore
value will be available tSWRD + tDOE after the. rising edge of the
semaphore write. If the left port was successful (reads a 0), it assumes control over the shared resource, otherwise (reads a 1) it
assumes the right port has control and continues to poll the semaphore.When the right side has relinquished control of the semaphore (by writing a 1), the left side will succeed in gaining control
of the semaphore. If the left side no longer requires the semaphore, a 1 is written to cancel its request.
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=IDGH)
LeftPort·
Fnnction
Set Left INT
Reset Left INT
R/W
X
CE
OE
X
X
Right Port
INT
X
AoL-13L
X
CE
OE
L
X
AoR-13R
3FFE
INT
L
R/W
L
L
L
3FFE
H
X
L
L
X
X
X
Set Right INT
L
L
X
3FFE
X
X
X
X
X
L
Reset Right INT
X
X
X
X
X
X
L
L
3FFE
H
6-14
PRELIMINARY
Qrdering Information
Sp~ed
(ns)
1~
25
35
55
Speed
(ns)
15
25
35
55
Ordering Code
Package
Name
Package 1YPe
CY7COO6-15AC
A65
64-Lead Thin Quad Flat Package
CY7COO6-15JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7COO6-25AC
A65
64-Lead Thin Quad Flat Package
CY7COO6-25JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7COO6-25AI
A65
64-Lead Thin Quad Flat Package
CY7COO6-25JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7COO6-35AC
A65
64-Lead Thin Quad Flat Package
CY7COO6-35JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7COO6-35AI
A65
64-Lead Thin Quad Flat Package
CY7COO6-35JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7COO6-55AC
A65
64-Lead Thin Quad Flat Package
CY7COO6-55JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7COO6-55AI
A65
64-Lead Thin Quad Flat Package
CY7COO6-55JI
J81
68-Lead Plastic Leaded Chip Carrier
Package
Name
Package type
Ordering Code
CY7COI6-15AC
A80
80-Lead Thin Quad Flat Package
CY7COI6-1S)C
J81
68-Lead Plastic Leaded Chip Carrier
CY7COI6-25AC
A80
80-Lead Thin Quad Flat Package
CY7C016-25JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7CQ16-25AI
A80
80-Lead Thin Quad Flat Package
CY7C016-25JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C016-35AC
A80
80-Lead Thin Quad Flat Package
CY7C016-35JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7COI6-35AI
A80
80-Lead Thin Quad Flat Package
CY7C016.:...35JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7COI6-55AC
ABO
80-Lead Thin Quad Flat Package
CY7C016-55JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C016-55AI
A80
80-Lead Thin Quad Flat Package
CY7C016-55JI
J81
68-Lead Plastic Leaded Chip Carrier
6-16
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
CY7C006
CY7C016
PRELIMINARY
CY7C024/0241
CY7C025/0251
4K X 16/18 and 8K x 16/18 Dual-Port
Static RAM with Sem, Int, Busy
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4K x 16 organization (CY7C024)
4K x 18 organization (CY7C0241)
8K x 16 organization (CY7C025)
8K x 18 organization (CY7C0251)
High-speed access
-15ns
Automatic power-down
Low operating power
-Icc = 150 rnA (typ.)
Expandable data bus to 32/36 bits or
more using Master/Slave chip select
when using more than one device
On chip arbitration logic
Semaphores included to permit software handshaking between ports
INT flag for port-to-port communication
Separate upper byte and lower byte
control
Pin select for Master or Slave
Available in 84-pin PLCC and 100-pin
T FP
• Pin-compatible and functional eqnivalent to IDT7024/IDT7025
Functional Description
The CY7C024/0241 and CY7C025/0251
are low-power CMOS 4K x 16/18 and 8K
x 16/18 dual-port static RAMs. Various arbitration schemes are included on the
CY7C024/0241 and CY7C025/0251 to
handle situations when multiple processors access the same piece of data. Two
ports are provided permitting independent, asynchronous access for reads and
writes to any location in memory. The
CY7C024/0241 and CY7C025/0251 can
be utilized as standalone 16-/18-bit
dual-port static RAMs or multiple devices
can be combined in order to function as a
32-/36-bit or wider master/slave dual-port
static RAM. An M/S pin is provided for
implementing 32-/36-bit or wider memory
applications without the need for separate
master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessordesigns,communications status buffering and
dual-port video/graphics memory.
Each port has independent control pins:
chip enable (CE), read or write enable (R!
W), and output enable (DE). Two flags
~rovided on each port (BUSY and
INT). BUSY signals that the port is trying
to access the same location currently being accesse~ the other port. The interrupt flag (INT) permits communication
between ports or systems by means of a
mail box. The semaphores are used to
pass a flag, or token, from one port to the
other to indicate that a shared resource is
in use. The semaphore logic is comprised
of eight shared latches. Only one side can
control the latch (semaphore) at any time.
Control of a semaphore indicates that a
shared resource is in use. An automatic
power-down feature is controlled independently on each port by a chip select
(CE) pin.
The CY7C024/0241 and CY7C025/0251
are available in 84-pin PLCCs (CY7C024
and CY7C025 only) and lOO-pin Thin
Quad Plastic Flatpack (TQFP).
Logic Block Diagram
~L ~~===a~~-----------------,
AsL
===1=1=;1
AOA
-----l...h~~i~::=:-l:~
1'---'""
1107L
__...J_i....__- .____...J
I/OaL - I/015L
IIOOL -
-----~'_t
I/OOR - I/0 7A
llliSVA[2]
J:IDS'YL[2j
A12R (CY7C025/0251)
(CY7C025/0251) A12L
A11L
A11R
7C024-1
Notes:
1. LB=Lower Byte. UB=Upper Byte.
2.
6-18
BUSY is an output in master mode and an input in slave mode.
L=::Z
~'CYPRESS
CY7C024/0241
CY7C025/0251
PRELIMINARY
Pin Configurations (continued)
lOO·Pin TQFP
Top View
1009998 97 96 95 94939291 90 8988 878685 84 83 82 81 8079 787778
NC
NC
NC
NC
NC
NC
NC
NC
I/0 1Ot.
As,
~,
I/O,1L
I/O,2L
I/O,3L
GND
I/O,4L
VO,5L
Vee
GND
As,
A2'
All
Ao!.
Tm',
iIDS'I,
GND
MIS
1I00R
iIDS'lR
VO,R
Tm'R
I/0 2R
AOR
A'R
A2R
Vee
I/OaR
II0 4R
I/OSR
AsR
~R
NC
NC
NC
NC
rlOaR
NC
NC
NC
NC
7C024-4
10099 98 97 96 9594 93 92 91 908988 8786 8S 84 B3 82 81 8079 78
n
76
75
NC
NC
NC
NC
NC
NC
NC
NC
As,
I/O'0l
~,
As,
I/O '1L
1/0 ,2l
A:!,
All
I/O'3L
GND
Ac,
lI'IT,
1llJSY,
GND
I/O '4L
I/O,5L
Vee
GND
MIS
IIOOR
1I0 1A
IllJSYR
lI'ITR
I/0 2R
AoR
Vee
A'R
A2R
r/OaR
AsR
I/0 4A
1/0 5A
~R
NC
NC
NC
NC
I/OSA
NC
NC
NC
NC
7C024-5
6-20
~
CY7C024/0241
~~ CYPRESS ========P='RE=L=IM=I=N=~=R=Y==CY=7=C=02=5i;;;;;;/O=25=1
Pin Definitions
Left Port
Right Port
Description
Chip Enable
CEL
CER
RiWL
OEL
mR
Output Enable
AoL-A12L
AoR-A12R
Address
I/OOL -I/0 15L
SEML
I/OOR -I/015R
Data Bus Input/Output
SEMR
Semaphore Enable
Upper Byte Select
RiWR
Read/Write Enable
VBL
UBR
LBL
LBR
Lower Byte Select
'iN'fL
'iN'fR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
GND
Power
Ground
Selection Guide
7C024/0241-15
7C025/0251-15
15
7C024/0241-25
7C025/0251-25
25
7C024/0241-35
7C025/0251-35
35
7C024/0241-55
7C025/0251-55
55
Maximum Operating Current (rnA)
280
250
230
220
Maximum Standby Current for ISBl (rnA)
70
60
50
40
Maximum Access Time (ns)
Maximum Ratings
(Above which the useful life may be inlpaired. For user guidelines,
nottested. )
Storage Thmperature ................ -65°C to + 150 00 C
Ambient Thmperature with
.
Power Applied ...................... -55°C to + 125°C
Supply Voltage to Ground Potential. . . . . .. -0.3V to + 7.0V
DC Voltage Applied to Outputs
in High Z State. . . . . . . . . . . . . . . . . . . . . . .. -0.5V to + 7.0V
DC Input Voltagef3] .................... -O.5V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Note:
3. Pulse width < 20 os.
6-22
Range
Commercial
Industrial
Ambient
Temperature
O°C to +70°C
Vee
5V ± 10%
-40°C to +85°C
5V± 10%
Capacitance[5]
Parameter
Description
Input Capacitance
OUtput Capacitance
eIN
CoUT
Test Conditions
TA = 25°C, f = 1 MHz,
Vcc = 5.0V
Max.
10
10
...
pnit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
~
I
C = 30 pF
R1=8930
1
c=30PF I
R2 = 34m
-
--
~
1.
5V ~1=8roo
RTH = 2500
OUTPUT::rI
OUTPUT
7C024·8
C= 5 F
= 1.4V
VTH
-=
P
R2
7C024-9
(a) Normal Load (Load 1)
= 3470
7C024·10
(c) Three-StIlte Delay (Load 3)
(b) Thevenin Equivalent (Load 1)
ALL INPUT PULSES
OUTPU~
I
3'OV~
10
90%
C=30pF
GND
5,3n5-
Load (Load 2)
7C024-11
7C024-12
Switch.ng Characteristics Over the Operating Rangd6]
Parameter
Description
REAl) CYCLE
Read Cycle Time
tRe
Address to Data Valid
tAA
tOHA
tACEl7J
tDOE
tLZOELH,9J
tHZOEL8,~J
tLZCELH,9J
tHzCEL",~J
tpu
tpD
tABEL?J
Notes:
5.
6.
O\1:£ut Hold from
Ad ,ress thange
CE LOW to Data Valid
DE LOW to DatI! Valid
DE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE H~!3H to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byt(l I!nable Access Time
7C024/0241-15
7C025/1!751-15
Min.'
Max.
7C024/0241-25
7C025/0251-25
Min.
Max.
25
15
15
35
25
15
10
3
10
10
15
Thsted initially and after any design or process changes that may
affect these parameters.
Thst conditions assume signal transition time of 3 ns or less, timing reference levels of l.SV; input pulse levels ofO to 3.0V; and output loading
of the specified ImlloH and 30-pF load capacitance.
7.
8.
9.
6-24
25
3
20
25
0
0
25
25
15
15
3
3
0
0
55
25
20
25
35
Unit
ns
ns
ns
3
3
3
55
35
20
15
3
55
..
25
13
3
7C024/0241-55
7C025/0251-55
'Max.
Min.
35
3
3
3
,
7C024/0241-35
7C025/0251-35
Min.
Max.
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
Th access RA~CE=L, pB=L, SEM=H. Th access semaphore,
CE=H and SEM=L. Either condition must be valid for the entire
tSCEtime.
At any given temperature and voltage condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE.
Thst conditions used are Load 3.
~
CY7C024/0241
'§g~YPRESS~~~~~~~~P~nE~L~IM~I~N~~~R~Y~~CY~7~CO~2~5/~02~5~
1
Data Retention Mode
The CY7C024/0241 is designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over temperature. The following rules insure data retention:
1. Chip enable (rn) must be held HIGH during data retention,
within V cc to V cc - 0.2Y.
2.
3.
Timing
..
Data Retention Mode
4.SV
Vee ~ 2.0V
Vee to Vee - 2.0V
7C024·'3
Parameter
ICCDRI
Test Conditions[13]
@VCCDR=2V
Note:
13. CE = Vee, Vin =GND to Vee, TA =25°C. This parameter is guaranteed but not tested.
6-26
rn must be kept between V cc - 0.2V and 70% of V cc during the power-up and power-down transitions.
The RAM can begin operation >tRC after V cc reaches the
minimum operating voltage (4.5 volts).
Switching Waveforms (continued)
Write Cycle No.1:
R/W Controlled Timing[19, 20, 21, 22J
ADDRESS
Cl:[23, 241
DATA OUT
~--------------~---------------4(NOTE26
NOTE 26
tso
DATA IN
--------------------------------1(
7C024-17
Write Cycle No.2: CE Controlled Timing[19, 20, 21, 27J
ADDRESS
twc
=>
)K
tAW
CE'J23, 241
)1'
~
-tsA
-tHA--
tSCE
tso
tHO
1/
DATA IN
/1
I"
Notes:
19, R/W must be HIGH during all address transitions.
20. A write occurs du!'!!!g the overlap (tSCE or tpWE) of a LOW CE or
SEM and a LOW UB or LB.
21. tHA is measured from the earlier ofCE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
22. If DE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tpWE or (tHZWE + tSD) to allow the I/O
drivers to turn off and data to be placed on the bus for the required
tSD. If OE is HIGH during an RfW controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tPWE.
4
=
=
7C024-18
23. To access RAM, CE VIL, S'EM VIH.
24. Th access upper byte, CE = VII., UB = VIL, SEM = VIH'
Th access lower byte, CE = VII.> LB = VIL, S'EM = VIH.
25. 'Itansition is measured ±500 mV from steady state with a 5-pF load
(including scope and jig). This parameter is sampled and not 100%
tested.
26. During this period, the I/O pins are in the output state, and input signals must not be applied.
27. If the CE or SEM LOW transition occurs simultaneously with or after
the R/W LOW transition, the outputs remain in the high-impedance
state.
6-28
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (Mis=IDGH)[32j
twc
K
ADDRESSR
~!(
MATCH
RJWR
tpWE
~
i'
1---1$0
~IL
DATAINR
Ips
ADDRESS L
"IlL
VALID
*HO
I+---.
)Il'
MATCH
:JC
I - - f- tBLA
lIDS'i'L
tBOO_
tO~~
DATAOUTL
)E
Iwoo
7C024·21
Write Timing with Busy Input (M!S=WW)
7C024-22
Note:
32. CEL = CER = LOW.
6-30
i!I!!!!:~
CY7C024/0241
. , CYPRESS =====;;;;;;;;;==P;;;;'RE=L;;;;IM=IN.;;;;'A;;;;R;;;;Y=;;;;CY=7;;;;C;;;;02;;;;5/;;;;O;;;;25=1
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
\WC
ADDRESSL
WRITE FFF (1 FFF CY7C025)
tINS[35]
-----1''---------------------~
Right Side Clears OOR:
XXXXXXXXXXXXXX
ADDRESSR
~
tRC
7C024-27
....
-. . . I.:(1.:.:.F R.:. .:F~.:.:. ~:.:.: ~ ~5:1-)_.~=======
CER
,----------
"
ImR
7C024-28
Right Side Sets INTL:
twc
WRITE FFE (1 FFE CY7C025)
1---
tINS[35]
---~
........._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
7CQ24-29
Left Side Clears INTL:
"'''S''. XXXXXXXXXXZXxx>f. . . (.1"-'F~. ; ;.f. ;.~ ~\C; .; Fg; .; 25.:. .)
GEL
K
R/WL /
OE
L
ImL
/
_*____
/L~I(
~K
' "' "' "' "
~
7C024-30
Notes:
34. tHA depends on which enable pin (eEL or RiWL) is deasserted first.
35. tINS or tINR depends on which enable pin (CEL or RiWL) is asserted
last.
6-32
Table 1. Non-Contending Read/Write
Outputs
Inpllts
CE
R/W
OE
UB
LB
SEM
H
X
X
X
X
H
HighZ
X
X
X
H
H
H
L
L
X
L
H
H
L
L
X
H
L
H
1/0 0-1/0,
1/0 8-1/0 15
Operation
HighZ
Deselected: Power-Down
HighZ
HighZ
Deselected: Power-Down
Data In
HighZ
Write to Upper Byte Only
HighZ
Data In
Write to Lower Byte Only
L
L
X
L
L
H
Data In
Data In
Write to Both Bytes
L
H
L
L
H
H
Data Out
HighZ
Read Upper Byte Only
L
H
L
H
L
H
HighZ
Data Out
Read Lower Byte Only
L
H
L
L
L
H
Data Out
Data Out
Read Both Bytes
X
X
H
X
X
X
HighZ
HighZ
Outputs Disabled
H
H
L
X
X
L
Data Out
Data Out
Read Data in Semaphore
Flag
X
H
L
H
H
L
Data Out
Data Out
Read Data in Semaphore
Flag
H
-.J
X
X
X
L
Data In
Data In
Write DINO into
Semaphore Flag
X
.....r
X
H
H
L
Data In
Data In
Write DINO into
Semaphore Flag
L
X
X
L
X
L
Not Allowed
L
X
X
X
L
L
Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)[36j
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
R/WL
L
X
X
X
CEL
L
X
X
L
Left Port
OEL AoL-llL
X
(l)FFF
X
X
X
X
(l)FFE
L
INTL
X
X
Ll37J
Hl38]
R/WR
X
X
L
X
CER
X
L
L
X
Right Port
OER AoR-llR
X
X
(l)FFF
L
X
(l)FFE
X
X
INTR
Ll3~J
H[J/]
X
X
Table 3. Semaphore Operation Example
Function
No action
Left port writes 0 to semaphore
Right port writes 0 to semaphore
DO-DI5Left
1
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
Notes:
36. AoL-12L and AoR-12R, IFFF/IFFE for the CY7C025.
37. If BUSYR=L, then no change.
0
0
Do-DI5 Right
1
1
1
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
Status
Semaphore free
Left Port has semaphore token
No change. Right side has no write access to
semaphore.
Right port obtains semaphore token
No change. Left port has no write access to
semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
. Semaphore free
Left port has semaphore token
Semaphore free
38. If BUSYL= L, then no change.
6-34
~~
CY7C024/0241
~~YPRESS~~~~~~~~P=nE~L=IM=I=N=~~Y~=C=Y=7=CO=2=~=02=5==1
Ordering Information (continued)
Speed
(ns)
Ordering Code
Package
Name
Package 1:ype
Operating
Range
15
CY7C0241-15AC
AlOO
100-Pin Thin Quad Flat Pack
Commercial
25
CY7C0241-25AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C0241- 25Al
A100
lOO-Pin Thin Quad Flat Pack
Industrial
CY7C0241-35AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C0241-35AI
AlOO
lOO-Pin Thin Quad Flat Pack
Industrial
CY7C0241-55AC
A100
100-Pin Thin Quad Flat Pack
Commercial
CY7C024l-55Al
A100
100-Pin Thin Quad Flat Pack
Industrial
35
55
Speed
(ns)
Ordering Code
Package
Name
Package 1:ype
Operating
Range
15
CY7C0251-15AC
AlOO
lOO-Pin Thin Quad Flat Pack
Commercial
25
CY7C025l-25AC
AlOO
100-Pin Thin Quad Flat Pack
Commercial
CY7C0251-25AI
AlOO
100-Pin Thin Quad Flat Pack
Industrial
CY7C0251-35AC
AlOO
lOO-Pin Thin Quad Flat Pack
Commercial
CY7C0251-35AI
AlOO
lOO-Pin Thin Quad Flat Pack
Industrial
CY7C025l-55AC
AlOO
lOO-Pin Thin Quad Flat Pack
Commercial
CY7C0251-55AI
AlOO
lOO-Pin Thin Quad Flat Pack
Industrial
35
55
Document #: 38-00255-A
6-36
CY7C130/CY7C131
CY7C140/CY7C141
Pin Configurations (continued)
LCC/PLCC
Top View
PQFP
Top View
-'
a:
..sl~~ Iltl~ rt'~{?l~! I~ If ~
7 6 5 4 3 2 ~1; 52 51 504946 47
All
46
~
45
"oL
A.,L
AsL
AsL
10
11
12
13
A71
14
AsL
AgL
VOOL
15
16
17
I/0 1L
I/0 2L
18
19
110"
20
44
43
7C131
7C141
42
41
40
39
38
37
36
OER
AcR
A'R
A2R
"oR
A.,R
ASR
35
34
1I00R
OER
AcR
A'R
A2R
"oL
AsL
A7L
AgL
AgL
A'R
A7R
AsR
AgR
·NC
All
A"
"oL
A.,L
"oR
A.,R
7C131
AsR
7C141
AsR
A7R
AgR
AgR
NC
I/Dol
I/0 1L
I/0 2L
1I00L
21 22 23 24 25 26 27 28 29 30 31 32 33
C13O-3
1I00R
g~gffirli ~ ~ ~l~~~~~
Selection Guide
7C130-25[3]
7C131-25
7C140-25
7C141-25
Maximum Access Time (ns)
Maximum 0serating
Current (rnA
Maximum Standby
Current (rnA)
Com'l/Ind
7C130-30
7C131-30
7C140-30
7C141-30
7C130-35
7C131-35
7C140-35
7C141-35
7C130-55
7P31-55
7C140-55
7C141-55
55
25
30
35
45
170
170
120
90
90
170
120
120
45
35
35
65
45
45
Military
Com'l/Ind
7C130-45
7C131-45
7C140-45
7C141-45
65
65
Military
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
StorageThmperature ................. -65°C to +150 oo C
Ambient Thmperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) ....................... -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... -0.5V to +7.0V
DC Input Voltage ....................... - 3.5V to +7 .OV
Output Current into Outputs (LOW) .............. 20 rnA
Notes:
3. 25-ns version available only in PLCC/PQFP packages.
Static Discharge Voltage ....................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Thmperature
Vee
O°Cto +70°C
5V ± 10%
Industrial
-40°C to +85°C
5V ± 10%
Military[4]
-55°C to + 125°C
5V ± 10%
Range
Commercial
4.
6-38
TA is the "instant on" case temperature
CY7C130/CY7C131
CY7C140/CY7C141
~YPRESS
"1~
AC Test Loads and Waveforms
0"":: ., "II
~:
347Q
INCLUDING _
JIG AND SCOPE
(a)
_
-
,pe
INCLUDING
JIG AND
SCOPE
C130-5
"Ill"
BlJSY
OR
1m
34m
_
-
THEVENIN EQUIVALENT
OUTPUTo
2~OQ
3.0V
o1.40V
~~
_
(b)
C130-6
BUSY Output Load
(CY7C130/CY7C131 ONLy)
ALL INPUT PULSES
Equivalent to:
~-r~m
C130-7
~k
~ CO%
GND.s.
C130-8
C130-9
Switching Characteristics Qver the Operating RangdS, 10)
7CI30-25L'J
7C131-25
7C140-25
7C141-25
Parameter
Description
Min.
Max.
7C130-30
7C131-30
7CI40-30
7C141-30
Min.
Max.
7C130-35
7C131-35
7CI40-35
7C141-35
Min.
Max.
7C130-45
7C131-45
7CI40-45
7C141-45
Min.
Max.
7C130-55
7C131-55
7CI40-55
7C141-55
Min. -Max.
Unit
READ CYCLE
tRC
tAA
Read Cycle Time
Address to Data Valid[ll)
25
tOHA
Data Hold from
Address Change
CE LOW to Data Valid[ll)
0
tACE
tDoE
tLZOE
tHZOE
tLZCE
~
tHA
tSA
tpWE
tSD
tHD
tHZWE
tLzWE
3
CE LOW to Low Z[12, 13)
CE HIGH to HighZ[12, 13)
5
30
20
3
0
Write Cycle Time
25
20
Address Set-Up to Wfite End
20
2
0
15
15
0
Address Hold from Write End
Address Set-Up io Write Start
R!W Pulse Width
Data ~et-Up to Write End
Data Hold from Write End
R/W LOW to High Z[13)
R!W HIGH to
:z(13)
=
ns
ns
ns
25
25
0
0
35
35
ns
ns
ns
ns
35
45
55
ns
40
25
35
35
2
0
25
2
0
25
ns
ns
ns
ns
15
0
15
0
2
0
30
20
40
2
0
30
20
ns
ns
0
0
0
20
15
0
ns
25
5
20
35
55
30
30
30
25
15
Low
20
25
Notes:
10. Thst conditions assume signal trallsition times of S ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading ofthe specified IOlJIOH, and -30-pF load capacitance.
11. AC Thst Conditions use VOH 1.6V and VOL 1.4Y.
12. At any given temperature and volt"l!e condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE.
20
ns
ns
ns
3
5
0
25
45
25
20
15
55
0
3
5
15
CE LOW to Write End
35
20
15
5
55
45
0
3
15
0
45
35
0
0
15
DE LOW to Low Z[12, 13J
DE HIGH to High Z[12, 13J
=
35
30
25
tow to Data Valid[ll J
tHZCE
CE LOW to Power-Up
tpu
CE HIGH to Power-Down
tpD
_.WRITE CYCLE[14j
twc
tSCE
tAW
30
25
0
20
0
25
0
ns
ns
ns
13. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL =
SpF as in part (b) of AC Thst Loads. 'Iransition is measured ±SOO m V
from steady state voltage.
14. The internal write time of the memory is defioed by the overlap of CS
LOW and RiW LOW. Both signals must be low to initiate a write and
either signal can termioate a write by going high. The data input set-up
and hold timiog should be referenced to the risiog edge of the signal
that termioates the write.
6-40
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Read Cycle No. 2[18, 20J
Either Port CEJOE Access
/~
"""""\1\,.
!--tHZCE-
tACE
~
tHZOE
tOOE--
~etLZOE-tLZCE
DATA OUT
ICC
<-// ' / / / /
---
-'>---
DATA VALID
r-
tpu
_tpo
/l
ISB - - - / ' .
Read Cycle No. 3[19]
~-"
Read with BUSY, Master: CY7C130 and CY7C131
tRC
)K
ADDRESSR
)(
ADDRESS MATCH
RiWR
")
tpWE
~
~~
-
ADDRESS L
)1(
tps
VALID
tHO
)~
ADDRESS MATCH
~
-tBHA
l---:tBLA
tBoo-
j~
tO~~
twoo
C130 -12
Write Cycle No.1 (OEThree-StatesDataI/Os - EitherPort)[14,21J
Either Port
~-------------------------twc------------------------~
ADDRESS
::~~~==========~~:C;E==============~::::~
____1:::::::~t~~~:::::::;~~,~~----tPWE------~~--------r_-------tso
DATA VALID
tHZOEa
DOUT
»»»
HIGH IMPEDANCE
C130-13
6-42
CY7C130/CY7C131
CY7C140/CY7C141
~YPRESS
Switching Waveforms (continued)
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First:
tRcortWC
K
ADDRESSL
ADDRESS R
ADDRESS MATCH
ADDRESS MISMATCH
-tps-
)~
--1-----1
~ tBLA
R
IIDSY
-tBHA
C130-17
Right Address Valid First:
tRC ortwc
ADDRESSR
~
ADDRESS MATCH
j
ADDRESS MISMATCH
-tps-
{
ADDRESSL
-
BOS'i'L
tBLA
-
!BHA
C130-18
Busy Timing Diagram No.3
Write with BUSY (Slave: CY7Cl40/CY7C141)
cr
R/W
~~___________________________________
~I+-------
tpWE
-------.Jt
~-tw:
-!_______F"" ~1
C130-19
6-44
1ac
CY7C130/CY7C131
CY7C140/CY7C141
:?cYPRESS
1YpicaJ DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. Mre.IENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
./
3l1.2
3l 1.01----==""I-c:::...----I
lee/
V
.9 0.8
0
w
~ 0.6
II:
0.2
I---
ISB3
0.0
4.0
4.5
5.0
5.5
0.4
::l
g
0.2
ISB3
-55
1.3
j
1.4
6l
1.2
~
1.2
............
II:
~ 1.0
r--....
l5~
TA= 25°C
1
0.8
4.0
4.5
SUPPLY VOLTAGE
6.0 0.6
./
i-'"
M
30.0
2.5
25.0
~
~
:l:
~15.0
1.5
1.0
0.5
0.0
o
.---V
1.0
2.0
3.0
SUPPLY VOLTAGE
1/
4.0
M
~
40
o
20
0.0
5.0
5.0
V
o
'--
/
/
Vee = 5.0V _
TA = 25°C
1.0
I
I
2.0
3.0
4.0
NORMALIZED Icc vs. CYCLE TIME
Vee = 4.5V
TA = 25°C
V,N = O.SV
~
II:
~ 0.751----...,j".~---+-----l
Vee = 4.5V
TA = 25°C
I
_
I
200 400 600 800 1000
CAPACITANCE (pF)
6-46
4.0
t!:J 1.0
/
o
3.0
1.25
.,J;
/
V
'" '"
OUTPUT VOLTAGE (V)
"
o
/
/
oV
125
,-
~10.0
v
80
Cii
Vee = 5.0V
25
:.J
II:
z
/
~ 100
II:
~
'iii'
-S20.0
w 2.0
2.0
v
a
Z 60
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
1.0
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (OC) .
0
0
./
-55
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
;i
o
!z
1.0
0.8
5.5
5.0
0
Vee = 5.0V
TA = 25°C
~
~ 140
~ 120
z
1----.1
0.9
20
""
OUTPUT SINK CURRENT
vs.OUTPUTVOLTAGE
1.6
j
"
25
125
AMBIENT TEMPERATURE (0G)
~
5
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
~
40
I-
6.0 0.6.t:===:t====::::t
1.4
::; 1.1
80
~ 60
Vee = 5.0V
V,N = 5.0V
M
SUPPLY VOLTAGE
100
::l
0
z
ifi
u
w
..:
::;;
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
I-
~
"
V
~
:§. 120
0.501·'::0---::'20:----3::1:0,...------l4O
CYCLE FREQUENCY (MHz)
CY7C130/CY7C131
CY7C140/CY7C141
.~YPRESS
Ordering Information (continued)
Speed
(ns)
30
35
45
55
Speed
(ns)
25
30
35
45
55
Ordering Code
Package
Name
"
Package lYPe
Opemting
Range
(6QO-MiI) Molded DIP
Commercial
P25
4g~Lead
CY7C140-30PI
P25
48-Lead (600-Mil) Molded DIP
CY7Cl40-35PC
P25
48-Lead (600-Mli) Molded DIP
Commercial
CY7C140-351'I
P25
48-Lead (600-MiI) Molded DIP
Industrial
CY7Cl40-35DMB
D26
48-Lead (6qo-MiI) Sidebraze DIP
Milit~ry
CY7C140-45PC
P25
48-Lead (600-Mii) Molded DIP
Commercial
Industrial
CY7C140-30PC
Industrial
CY7Cl40-45PI
P25
48-Lead (600-Iviil) Molded OIP
CY7C140-45DMB
D26
48-Lead (600-MiI) Sidebra;:e DIP
Military
CY7C140- 55PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7Cl40-55PI
P25
48-Lead (600-Mil) Molded DIP
Il)dustrial
CY7C140-55DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
Package
Name
Package lYPe
Opemting
Range
CY7C141-25JC
J69
52-Lead Plastic Lellded Chip Carrier
Commercial
CY7C141-25NC
N52
52-Pin Plastic Quad Flatpack
Ordering Code
CY7C141-25JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-25NI
N52
52-Pin Plastic Quad Flatpack
Industrial
Commercial
CY7C141-30JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-30NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-30JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C141-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C141-35NC
N52
52-Pin Plastic Quad Flatpack
Industrial
CY7C141-35JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-35NI
N52
52-Pin Plastic Quad Flatpack
CY7C141- 35LMB
L69
52-Square Leadless Chip Carrier
Military
CY7Ci41-45JC
J69
52-LeadPlastic Leaded Chip Carrier
Commercial
CY7C141-45NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-45JI
J69
52-Lead Plastic Leaded C;hip Carrier
CY7C141-45NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-45LMB
"
Industrial
L69
52-Square Leadless Chip Carrier
Military
CY7C141-55JC
J69
52-Leitd Plastic Leaded Chip Carrier
Commercial
CY7C141-55NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-55JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-55NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-55LMB
L69
52-Square Leadless Chip Carrier
6-48
Industrial
Military
CY7C132/CY7C136
CY7C142/CY7C146
2K X 8 Dual-Port
Static RAM
Features
• D.8-micron CMOS for optimum speed/
power
• Automatic power-down
• TTL compatible
• Capable of withstanding greater than
2001Velectrostatic discharge
• Fully asyncbronous operation
• Master CY7CI32/CY7CI36 easily expands data bus width to 16 or more
bits using slave CY7CI42/CY7CI46
• BUSY output ~ag on CY7CI32/
CY7CI36; BU Y input on
CY7CI42/CY7C146
• INT flag for port-to-port communication (52-pin LCC/PLCC/PQFP
versions)
Functional Description
The CY7C1321CY7C136/CY7C142 and
CY7C146 are high-speed CMOS 2K by 8
dual-port static RAMS. lWo ports are provided to pennit independent access to any
location in memory. The CY7C1321
CY7C136 can be utilized as either a standalone 8-bit dual-port static RAM or as a
MAS1ER dual-port RAM in conjunction
with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit
or greater word widths. It is the solution to
applications requiring shared or buffered
data such as cache memory for DSp, bitslice, or multiprocessor designs.
Each port has independent control pins;
chip enable (rn), write enable (R/W), and
output enable (aB). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port ~
the 52-pin LCC and PLCCversions. BUS
signflls that the port is trying to access the
same location currently being accessed by
the ot~ort. On the LCC/PLCC versions, INT is an interrupt flag indicating
that data has been placed in a unique location (7FF for the left port and 7FE for the
right port).
An automatic power-down feature is controlled independently on each port by the
chip enable (eE) pins.
The CY7C132/CY7C142 are available in
both 48-pin DIP and 48-pin LCC. The
CY7C136/CY7C146 are available in
52-pin LCC, PLCC, and PQFP..
Logic Block Diagram
~l::~~=r--------,
l:El
OEl~~~~~~~~~=t~
A10L -
Pin Configuration
r----------{]~~~R
CER
OER
....--+.t----
An ---1"4---,
11001. ---t:+-r~
lIOn
BUSYll'l
---+'--1..:::::1
_-....,.-----.1
AsL ---\-.1----,
AoL--~--........J
DIP
Top View
A10R
A7R
rr.;:;~-:I--- I/OOR
L.:.:J--+---
1/07R
L.----r - __ BUSYRI'I
r-::::::-...+--- ASR
L---.J+i--- AoR
l:El
~l
BUSYl
A10L
<:lEl
"ol
A'l
A'l
Aal
~l
Aal
Asl
A7l
AeL
Am.
IIOol
Vee
l:ER
RiWR
BUSYR
A,OR
OER
"oR
A'R
A'R
AaR
~R
AsR
AeR
A7R
AeR
AeR
I/0 1L
I/0 7R
I/O'l
I/Oal
!JOSR
I/04l
I/OSL
1I04R
II0 6L
1I0 2R
liOn
110,"
IIOOR
GND
1I0sR
1/0 3R
C132-2
Noles:
t. CY7C132/CY7C136 (Master): l'i"iJ'SY is open drain output and requires pull-up resistor.
CY7C142/CY7Cl46 (Slave): l'i"iJ'SY is input.
2.
Open drain outputs; pull-up resistor required.
6-50
CY7C132/CY7C136
CY7C142/CY7C146
~YPRESS
Electrical Characteristics Over the Operating RangerS]
7C132-25,30[3]
7C136-25,30
7C142-25,30
7C146-25,30
Parameter
Description
Thst Conditions
Min.
VOH
Output HIGH Voltage Vee = Min., IOH = -4.0 rnA
VOL
Output LOW Voltage
Vrn
Input HIGH Voltage
VIL
Input LOW Voltage
Max.
2.4
7C132-3S
7C136-3S
7C142-35
7Cl46-3S
Min.
7C132-4S, SS
7C136-4S, SS
7C142-45,5S
7C146-4S, SS
Max.
Min.
2.4
Max.
Unit
V
2.4
V
IOL = 4.0 rnA
0.4
0.4
0.4
IOL = 16.0 rnA[6]
0.5
0.5
0.5
2.2
2.2
0.8
2.2
0.8
V
0.8
V
IIX
Input Load Current
GND~VI~Vee
-5
+5
-5
+5
-5
+5
loz
Output Leakage
Current
GND~ Vo~
Vee,
Output Disabled
-5
+5
-5
+5
-5
+5
!-IA
!-IA
los
Output Short
Circuit Current!7l
Vee = Max.,
VOUT= GND
-350
rnA
lee
Vee Operating
Supply Currerit
CE=Vn."
Outputs 0sren,
f= fMAX[
Corn'l
rnA
ISB!
Standby Current
Both Ports,
TTL Inputs
CEL and CER ~ Vrn,
f= fMAX[S]
Corn'l
ISB2
Standby Current
One Port,
TIL Inputs
CELorCER~ Vrn,
Standby Current
Both Ports,
CMOS Inputs
Both Ports CEL and
CER~ Vee - 0.2y,
VIN ~ Vee - O.2Vor
VIN ~ 0.2Y, f = 0
Corn'l
Standby Current
One Port,
CMOS Inputs
One Port CEL or
CER ~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
Corn'l
ISB3
ISB4
-350
-350
170
120
90
170
120
45
35
Mil
65
Mil
Corn'l
115
Active Port Outputs Open,
Mil
f= fMAX[S]
15
Mil
VIN~0.2Y,
Active Port Outputs Open,
f = fMAX[S]
105
Mil
65
45
90
75
115
90
15
15
15
15
85
70
105
85
rnA
rnA
rnA
rnA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Notes:
5. See the last page of this specification for Group A subgroup testing in-
formation.
6.
7.
8.
BUSY and INT pins only.
Duration of the short circuit should not exceed 30 seconds.
At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of litre and using AC Thst Waveforms input levels
ofGNDt03Y.
9. Tested iuitially and after any design or process changes that may affect
these parameters.
10. Thst conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5\1, input pulse levels of 0 to 3.0V and output
loading of the specified IOrJIOH. and 30-pF load capacitance.
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz,
Vee = 5.0V
15
pF
10
pF
11. AC test conditions use VOH = 1.6V and VOL = lAY.
12. At any given temperatore and voltage condition for any given device,
tHzCE is less than tLZCE and tHZOE is less than tLZOE.
13. tLZCEo tLzWE, tHZOE. tLZOE, tHZCE, and tHzWE are tested with CL =
5pF as in part (b) of AC Thst Loads. 'fransition is measured ±500 mV
from steady-state voltage.
14. The internal write time of the memory is defined by the overlap ofCE
LOW and R/W LOW. Both signals must be LOW to initiate a write
and either signal can terminate a write by going HIGH. The data input
setup and hold timing should be referenced to the rising edge of the
signal that terminates the write.
6-52
CY7C132/CY7C136
CY7C142/CY7C146
tzrcYPRESS
Switching Characteristics Over the Operating Rangef5, 10] (continued)
7C132-25L3j
7C136-25
7C142-25
7C146-25
Parameter
Description
Min.
7C132-30
7C136-30
7C142-30
7C146-30
Max.
Min.
Max.
7C132-35
7C136-35
7C142-35
7C146-35
Min.
Max.
7C132-45
7C136-45
7C142-45
7Cl46-45
Min.
Max.
7C132-55
7C136-55
7C142-55
7C146-55
Min.
Max.
Unit
ns
ns
BUSY/INTERRUPT TIMING
tBIA
tBHA
tBLC
tBHC
tps
tWB L1bj
tWH
tBDD
tDDD
tWDD
BUSY LOW from Address Match
BUSY HIGH from
Address Mismatch[15]
20
20
20
25
30
20
20
20
25
30
BUSY LOW from CE LOW
20
20
20
25
30
BiJ'S'Y HIGH from CE HIGHL" j
20
20
20
25
30
Port Set Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to
Read Data Valid
Write Pulse to Data Delay
5
5
5
5
5
0
20
0
0
0
0
30
30
35
35
ns
ns
ns
ns
ns
ns
ns
25
Note
17
30
Note
17
35
Note
17
.45
Note
17
45
Note
17
Note
17
Note
17
Note
17
Note
17
Note
17
ns
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INIERRUPT
Set Time
OE to INTERRUPT
Reset Time[15]
25
25
25
35
45
25
25
25
35
45
25
25
25
35
45
ns
ns
ns
25
25
25
35
45
ns
CE to INTERRUPT
Reset Timef l5 ]
Address to INTERRUPT
Reset Time[15]
25
25
25
35
45
ns
25
25
25
35
45
ns
INTERRUPT TIMING[18]
tWINS
tEINS
tINS
tOINR
tEINR
tINR
Notes:
15. These parameters are measured from the input signal changing, until
the output pin goes to a high-Impedance state.
16. CY7CI42/CY7CI46 only.
17. A write operation on PortA, where Port A has priority, leaves the data
on Port B's outputs undisturbed until one access time after one of the
following:
A. BUSY on Port B goes HIGH.
B. Port B's address toggled.
C. CE for Port B is toggled.
D. R/W for Port B is toggled during valid read.
18.
19.
20.
21.
22.
52-pin LCC/PLCC versions only.
R/W is HIGH for read cycle.
Device is continuously selected, CE = V IL and DE = V IL.
Address valid prior to or coincident with CE transition LOW.
If DE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tpWE or tHZWE + tSD to allow the data I/O
pins to enter high impedance and for data to be placed on the bus for
the required tSD'
23. If the CE LOW transition occurs sImultaneously with or after the R/W
LOW transition, the outputs remain in a high-impedancestate.
Switching Waveforms
Read Cycle No.1 (Either Port-Address Access[19, 20]
ADDRESS
DATA OUT
=f~~
*_-_-
~~,__
PREVIOUS DATAV;$XXX2S..2SJI<._ _ _ _ _ _D_A_TA_VA_L_ID_ _ _ _ __
C132-10
6-54
~
CY7C132/cY7C136
_,-cYPRESS ============;;;;;;;CY;;;;;;;;7C;;;1~42~/CY~7;;;;;;;C;;14~6
Switching Waveforms (continued)
Write Cycle No.2 (RIW Three-States Data I/Os - Either Port) [14. 23]
ADDRESS
----- ~-----------------~C----------------------~ J----tSCE
R/W
______....;;;,:..............,~~~ "'1-------
tpwE
--------101
r---------
+ _______ 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
6-64
Range
Commercial
Industrial
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
-40°C to +85°C
5V ± 10%
CY7C133
CY7C143
~
CYPRESS
""'E5i&"
'1~
AC Test Loads and Waveforms
mIT'~~: '"
P'
II
347Q
INCLUDING _
JIG AND SCOPE
(a)
1~
..",,:;;: '" 'II
INCLUDING
JIG AND
SCOPE
_
C133-3
_
-
BUSY
347Q
_
-
(b)
C133-4
3'0V~
THEVENIN EQUIVALENT
250Q
OUTPUT 0.0--"'1."".---ool.40V
O
GND$,3 n: :
I-=
30
pF
BUSY Output Load
(CY7C133 ONLy)
ALL INPUT PULSES
Equivalent to:
~~~'Q
OR
INT
1E:::
C133-5
10%
90%
_3ns
C133-6
C133-7
Switching Characteristics Over the Operating Range[7J
7C133-25
7C143-25
Parameter
Description
Min.
Max.
7C133-35
7C143-35
Min.
Max.
7C133-55
7Cl43-55
Min.
Max.
Unit
READ CYCLE
25
35
55
tRC
Read Cycle Time
tAA
Address to Data VaJid[8J
tOHA
Data Hold from Address Change
tACE
CE LOW to Data VaJid[8J
25
35
55
ns
tDOE
OE LOW to Data VaJid[8J
20
25
30
ns
tLZOE
OE LOW to Low Z[9, 10J
tHZOE
DE HIGH to High Z[9, 10J
tLZCE
CE LOW to Low Z[9, 10J
tHzCE
CE HIGH to High Z[9, 10J
tpu
CE LOW to Power-Up
tpD
c::E HIGH to Power-Down
25
0
35
0
3
0
3
15
3
5
0
5
0
25
ns
25
20
ns
ns
20
0
ns
ns
25
25
ns
ns
3
20
15
ns
55
ns
WRITE CYCLE[ll J
twc
Write Cycle Time
25
35
55
ns
tSCE
CE LOW to Write End
20
25
40
ns
tAW
Address Set-Up to Write End
20
25
40
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
R/W Pulse Width
20
25
35
ns
tSD
Data Set-Up to Write End
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
tHZWE
R/W LOW to High Z[1OJ
tLZWE
R/W HIGH to Low Z[lOJ
15
0
20
0
Notes:
7. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IOrJIOH. and 30-pF load capacitance.
8. AC Test Conditions use VOH = 1.6V and VOL = 1.4Y.
9. At any given temperature and voltage condition for any given device,
tLZCE is less than tHZCE and tLZOE is less than tHZOE.
ns
20
0
ns
ns
to. tLZCE, tLZWE, lHZOE, tLZOE, tHZCE and tHZWE are tested with CL =
5 pF as in part (b) of AC Test Loads. nansition is measured ±500 mV
from steady state voltage.
11. The internal write time ofthe memory is defined by the overlap of CS
LOW and R/W LOW Both signals must be LOW to initiate a write
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the
signal that terminates the write.
6-66
CY7C133
CY7C143
Switching Waveforms
(continued)
Read Cycle No. 2[18,20]
Either Port CE/OE Access
~I\.
..IV
I-
tACE
~
~
tLZOE--to
tHZCE - -
tHZOE
tOOE-
tLZCE
DATA OUT
ICC
r-/
---
tpu
'/ '/ '/
~
DATA VALID
r-
_tpo
/I
IS6 - - . / .
Read Cycle No. 3[19]
Read with BUSY, Master: CY7C133
tRC
ADDRESSR
)K
tpwE
RJWR
(-
ADDRESSL
)(
ADDRESS MATCH
-
)(
tps
......
VALID
tHO
)(
ADDRESS MATCH
I-.. tBHA
I---tBLA
tBOO -
tO~~
twoo
Note.:
20. Address valid prior to or coincident with CE transition LOW.
6-68
~
0133- 10
CY7C133
CY7C143
Switching Waveforms (continued)
Write Cycle No.2
(R/W Three·States Data IJOs -
Either Port)[20,25]
Either Port
~-------------------twc ------------------------~
ADDRESS
isCE
______~____~~__~~~~---------tpwE
------~~~
_____________________
R/W
DATAoUT
)
)
)
)
)
)
)
)
)
» ) )tH~E~
)
tLZWE
HIGH IMPEDANCE
I_
~"7'""'7("7("7«"7"("7"
C133-14
Busy Timing Diagram No.1 (CE Arbitration)
CEL Valid First:
JX. . _______
--JX. . ________
j~
--J)x(. . _________
ADDRESSL,R _ _ _
A_D_DR_E_S_S_M_A_T_C_H_ _ _ _ _ _ _
CER Valid First:
ADDRESSL,R
____
...._ _ _ _ _ _ _
A_D_DR_E_S_S_M_A_T_C_H_ _ _ _ _ _ _
CEL
BOS'i'L
Note:
25. If the CE LOW transition occilrs simultaneously with or after the
R/W LOW transition, the outputs remain in the high-impedance
state.
6-70
CY7C133
CY7C143
32-Bit Master/Slave Dual-Port Memory Systems
LEFT
RIGHT
MASTER
fw'.-
5V ---.tW-
5V
R!W
R!W
SLAVE
~
tmSY
BUSY
-
Ordering Information
Speed
(n5)
25
35
55
Speed
(n5)
25
35
55
Ordering Code
Package
Name
Package 'fYpe
Operating
Range
CY7C133-25JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C133-25JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
Commercial
CY7C133-35JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7C133- 35JI
J81
68-Lead Plastic Leaded Chip Carrier
industrial
CY7C133 - 55JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C133 - 55JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
Package
Name
Package 'fYpe
Operating
Range
Ordering Code
CY7C143-25JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C143-25JI
J81
68-Lead Plastic Leaded Chip Carr!er
Industrial
CY7C143-35JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C143-35JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7C143-55JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C143-55JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
6-72
C133-17
CY7B134
CY7B135
CY7B1342
4Kx 8 Dual-Port Static RAMs
and 4K x 8 Dual-Port Static RAM with Semaphores
Features
Functional Description
• O.S-micron BiCMOS for high
performance
• High-speed access
-15 ns (commercial)
- 25 ns (military)
• Automatic power-down
• Fully asynchronous operation
• 7B1342 includes semaphores
• 7B134 available in 4S-pin DIP
• 7B135/7B1342 available in 52-pin
LCC/PLCC
The CY7B134, CY7B135, and CY7B1342
are higb-speed BiCMOS 4K x 8 dual-port
static RAMs. The CY7B1342 includes
semaphores that provide a means to allocate portions of the dual-port RAM or
any shared resource. 1Wo ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. Application areas include interprocessor/multiprocessor designs, communications status buffering,
and dual-port video/graphics memory.
Each port has independent control pins:
chiE-enable (CE), read or write enable
(R/W), and output enable (OB). The
CY7B134/135 are suited for those systems
that do not require on-chip arbitration or
are intolerant ofwait states. Therefore, the
user must be aware that simultaneous access to a location is possible. Semaphores
are offered on the CY7B1342 to assist in
arbitrating between ports. The semaphore
logic is comprised of eigbt shared latches.
Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in
use. An automatic power-down feature is
controlled inde~dentlyon each port bya
chip enable (CE) pin or SEM pin
(CY7B1342 only).
The CY7B134 is available in 48-pin DIP.
The CY7B135 and CY7B1342 are available in 52-pin LCC/PLCC.
Logic Block Diagram
~Llr;=~[)~----------I
r - b - - -......
~--------------~
~R
CER
r-----------~j;=--~R
r--;::==+---r---1t----
A11R
A10R
L _ _ _ _J - - L _ J - - - - -
VO'R
V~L ---~~.-rr~-r~~:=-~L~-__~
IIOOl ---......;:-t_J--L_ _ _ _-.J
··
r-------~~----- ~R
MEMORY
!
ARRAY
L ______.Jo~----- AoR
~L ------~_ _ _ _ _~
SEMAPHORE
ARBITRATION
(7B1342 only)
(7B1342ooly)
(7B1342 only)
1342-1
Selection Guide
Maximum Access Time (ns)
Commercial
Maximum 03erating
Current (rnA
Military
Maximum Standby
Commercial
Current (rnA)
Military
7B135-15
7B1342-15
15
260
7B134 20
7B135-20
7B1342-20
20
240
110
100
6-74
7B134-25
7B135-25
7B1342-25
25
220
260
95
100
7B134-35
7B135-35
7B1342-35
35
210
250
90
95
7B134-55
7B135-55
7B1342-55
55
210
250
90
95
CY7B134
CY7B135
CY7B1342
1z=rcYPRESS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. -65°C to +150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Volt~ge to Ground Potential
(Pin 48 to Pin 24) ....................... -O.5V to +7.0V
DC Voltage Applied to Outputs
in High ZState ......................... -O.5V to +7.0V
DC Input Voltagd l ] ..................... -3.0V to +7.0V
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
Ambient
Thmperature
O°C to +70°C
Range
Commercial
Industrial
Militaryl"J
Vee
5V ± 10%
5V ± 10%
5V ± 10%
-40°C to +85°C
-55°C to + 125°C
Electrical Characteristics Over the Operating Range[3]
7B134-20
7B135-20
7B135-15
7B1342-15 -7B1342-20
Parameter
Description
Thst Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = -4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 4.0 rnA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
Ioz
Output Leakage Current
Icc
Operating Current
ISBl
ISBZ
ISB3
ISB4
Max. Min.
2.4
2.2
Com'l
2.2
2.2
-10
+10
-10
+10
-10
+10
-10
+10
!lA
!lA
220
rnA
260
240
260
Standby Current
(One Port TTL Level)
CEL and CER ~ VIH,
f= fMAX[4]
Standby Current
(Both Ports CMOS Levels)
Both Ports CE and CER~ Com'l
Vee - 0.2Y,
VIN ~ Vee - 0.2V
MiVlnd
or VIN S 0.2Y, f = 0[4]
15
One Port CEL or CER ~ Com'l
Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
VIN S 0.2Y, Active
MiVlnd
Port Out~uts,
f= fMAX4]
160
Notes:
1. Pulse width < 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
110
100
6-76
95
rnA
100
165
155
MiVlnd
4.
V
+10
MilJInd
Com'l
V
0.8
-10
CE:L and CER ~ VIH,
Com'l
V
+10
MilJInd
f= fMAX[4]
V
0.4
0.8
Unit
-10
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port CMOS Level)
2.4
0.4
0.8
GND:-S;VI:-S;Vee
Outputs Disabled,
GND:-S;Vo:-S;Vee
Vee = Max.,
lOUT = OmA
Max. Min. Max.
2.4
0.4
7B134-25
7B135-25
7B1342-25
145
rnA
170
15
15
rnA
30
150
140
rnA
160
fMAX = lItRC = All inputs cycling at f = I/tRC (except output enable).
f = 0 means no address or control lines change. This applies only to
inputs at CMOS level standby ISB3'
CY7B134
CY7B135
CY7B1342
.~CYPRESS
-=-t.,
Switching Characteristics Over 'the Operating Rangel7, 8]
7B134-20
78135-20
781342-20
78135-15
781342-15
Parameter
Description
Min.
I Max.
Min.
I Max.
7B134-25
7B135-25
781342-25
Min.
I Max.
7B134-35
78135-35
7B1342-35
Min.
I Max.
7B134-55
78135-55
781342-55
Min.
Max.
Unit
READ CYCLE
20
15
35
55
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
OUTrut Hold From
Ad ress Change
tACE
CE WW to Data Valid
15
20
25
35
tDOE
DE LOW to Data Valid
10
13
15
20
tLZOEl~,
lUj
tHZOEl~,
OE Low to Low Z
lUj
tLZCE19, IUj
OE HIGH to High Z
lUj
CE HIGH to High Z
tHZCEl~,
CE LOW to Low Z
tpu
CE LOW to Power Up
tPD
CE HIGH to Power Down
15
25
20
3
3
3
3
3
10
25
3
3
10
3
13
0
0
3
3
0
3
0
ns
ns
ns
25
0
35
25
ns
ns
25
20
ns
ns
55
25
20
15
20
15
3
15
ns
55
3
3
3
13
35
ns
ns
55
ns
WRITE CYCLE
twc
Write Cycle Time
15
20
25
35
55
ns
tSCE
CE LOW to Write End
15
20
30
50
ns
tAW
Address Set-Up to Write End
12
12
15
20
50
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
Write Pulse Width
0
50
Data Set-Up to Write End
10
20
15
0
25
tSD
0
15
13
ns
tpWE
0
12
2
0
30
2
15
25
ns
tHD
Data Hold from Write End
0
0
0
0
0
tHZWE 1lUj
tLZWEPOj
R/W LOW to High Z
tWDDlll]
Write Pulse to Data Delay
30
40
50
60
70
ns
tDDDlllj
Write Data Valid to Read
Data Valid
25
30
30
35
40
ns
R/W HIGH to Low Z
10
15
13
3
3
3
20
3
ns
ns
25
3
ns
ns
SEMAPHORE TIMING[12]
tsop
SEM FI~date Pulse
(OEor SEM)
10
10
10
15
15
ns
tSWRD
SEM Flag Write to Read Time
5
5
5
5
5
ns
tsps
SEM Flag Contention Window
5
5
5
5
5
ns
Noles:
7. See the last page of this specification for Group A subgroup testing information.
8. Test conditions assume signal transition time of3 ns or less, timing reference levels of I.Sv, input pulse levels of 0 to 3.0V, and output loading
of the specified IorJ10H and 30-pF load capacitance
9. At any given temperature and voltage condition for any given device,
tHzCE is less than tLZCE and tHZOE is less than tLZOE.
10. Thst conditions used are Load 3.
11. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay
wavefonn.
12. Semaphore tinIing applies only to CY7B1342.
6-78
CY7]l134
CY'7B135
CY7B1342
Switching Waveforms (continued)
Write Cy~le No.1: OE Three-States Data I/Os (Either Port) [!?, 18, 19]
~------------------------twc------------------------~
ADDRESS
tSCE
SEM[121
OR~~~~~~~==========~~============~~~;=~~~~~
tAW
~-----------tPWE------------~~
R/W
----~----T_--~I
j;::::: tso
DATAIN
------------------~~
DATA VALID
,-~-------------
.1. tHO;t
~-------
HIGH IMPEDANCE
.1342-12
Notes:
17. The internal write tim~f the memory is defined by the overlap ofc:E
or SEM LOW and R/W LOW. Both signals must be LOW to initiate
a write and either signal can terminate a write by going HIGH. The
data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
18. R/W must be HIGH during all address transactions.
19.
6-80
!f OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tpWE or (tHZWE + tSD) to allow the 110
drivers to turn off and data to ~ placed on the bus for the required
tSD.!fOE is HIGH during a R/W controlled write cycl~ (as in this example), this requirement does not-apply and the wrile pulse can b~ as
short as the spe~ified tpWE'
CY7B134
CY7B13S
CY7B1342
Switching Waveforms (continued)
Timing Diagram of Semaphore Contention (CY7B1342 only) [22, 23, 24J
__________________________
--J><~
___________
1342-15
Note.:
22. IJOOR = IJOOL = LOW (request semaphore); CER = CEL = HIGH.
23. Semaphores are reset (available to both ports) at cycle start.
24. Iftsps is violated, it is guaranteed that only one side will gain access to
the semaphore.
6-82
CY7B134
CY7B135
CY7B1342
'!Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NO~ZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
ISB
ffi 1.2
Jl1.0
o
~
0.8
::::;
.--- ~
~
V
,.....
isz
0.4
z
0.2
0.0
4.0
lee
4.5
5.0
5.5
-
c
20.8 ~ ISB3
~iS
~ 0.6
lee.____
1-
jl1.0
0.4
\
\
1\
\
80
60
en 40
Vee = 5.0V
TA = 25°C
r\
!:>
5 20
25
125
AMBIENT TEMPERATURE (0C)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NO~ZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.10 r---r--,----,-----,
a
o
0.2
0.6
-55
6.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
!zw 120
IE 100
~::l
Vee = 5.0V
VIN = 5.0V
0.6
~
§. 140
o
0
« 100
1.2
o
'
j.
~
1
~ 1.00 I--"d---:::;;;;~-_+-__l
z
o
o
~1.05
1.0
a:
0.95 '----'---'----'-_----'
4.0
4.5
5.0
5.5
6.0
/
V
w
::::;
~0.50
a:
oz
0.0
20.0
.,15.0
;;: 10.0
/
!:i
~
o
5.0
Vee = 4.5V
TA = 25°C
I
o
I
/
1.0
Vee = 5.0V I TA = 25°C
I
I
2.0
3.0
4.0
5.0
OUTPUT VOLTAGE (V)
NO~ZED
Icc vs. CYCLE TIME
1.25
Vee = 5.0V
TA = 25°C
VIN = 0.5V
o 1.01---;---+---+---,1
8
-
~
a:
5.0
V
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
J"-
//
~
..,..
o
~
.s
/
0.25
50
0.0
0!5~5----2~5~---~125
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING
N
70
!:>
TYPICAL POWER-ON CURRENT
VS. SUPPLY VOLTAGE
/
/.
~
5o 60
/
I
80
Cii
AMBIENT TEMPERATURE (0C)
J.
0 0 .75
v-
90
~
a:
I----......j.~----:..j az
SUPPLY VOLTAGE (V)
1.0
!z
5.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
.§..
j.l.lI-----t--~iL-____I
.....
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
~ 0.751---+--+--,..£.j-----I
-
I
200 400 600 800 1000
CAPACITANCE (pF)
6-84
40
50
20
30
CYCLE FREQUENCY (MHz)
CY7B134
CY7B135
CY7B1342.
=1i~YPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIR
VILMax.
IJX
loz
Icc
IsBl
ISB2
ISB3
ISB4
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8, 9, 10, 11
7,8,9, 10, 11
7,8,9, 10, 11
WRITE CYCLE
7,8,9,
7, 8, 9,
7,8, 9,
tAW
7,8, 9,
tHA
7,8,9,
tSA
7,8,9,
tpWE
7,8,9,
tSD
7,8,9,
tHD
SEMAPHORE CYCLE
twc
tSCE
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tsps
Document #: 38 -00161- D
tSOD
tSWRD
6-86
CY7B138
CY7B139
fi;EYPRESS
Pin Configuration
68·Pin LCC/PLCC
ThpView
;m....l
O..J
gg~~~~~~~~~~;~~I~
;:! a~
..J
...J
..J
9 8 7 6 5 4 3 2 1 68 6766 85 64 63 62 61
I/00L
1I00L
1/0 4L
I/OSL
GND
I/0 6L
1I00L
Vee
GND
1I0DA
1I0 1R
I/O'R
10
11
12
13
14
15
16
17
18
19
20
Vee
21
22
I{03R
23
I/0 4R
IroSR
I/OSR
24
25
26
60
58
ASL
A.,L
AsL
57
56
55
54
53
A'L
All
AcL
1mL
BUSYL
52
GND
59
76138/9
Mill
51
50
49
48
47
46
45
44
BOS'i'R
1mR
AcR
A'R
A'R
AsR
A.",
BW~OO~~~~~OOD~~~~~~
a:: Cii' a:~)C:lufO 0 c 0 a:: a:: a:: a:: a::.} a::
g~~
oZZ~Z~;~~~
~
6138-2
Pin Definitions
Left Port
Right Port
Description
I/OOL-7L(8L)
I/O OR-7R(8R)
Data Bus Input/Output
AoL-llL
CEL
AoR-llR
Address Lines
CER
Chip Enable
OEL
OER
Output Enable
RiWL
R/WR
Read/Write Enable
SEML
SEMR
sem~hore Enable. When asserted LOW, allows access to eight semaphores.
The ree least significant bits of the address lines will determine which semaphore to write or read. The I/Oo pin is used when writing to a semaphore.
Semaphores are requested by writing a 0 into the respective location.
INTL
OOR
Interrupt flag. INTL is set when righl£ort writes location FFE and is cleared
when left port reads location FFE. INTR is set when left port writes location
FFF and is cleared when right port reads location FFF.
BUSYL
BUSYR
Busy Flag
MIS
Master or Slave Select
Vee
GND
Ground
Power
Selection Guide
7B138-15
7B139-15
Maximum Access Time (jls)
Maximum 03erating
Current(mA
Maximum Standby
Current for ISBl(mA)
Commercial
7B138-35
7B139-35
7B138-55
7B139-55
15
25
35
55
260
220
210
210
280
250
250
95
90
90
100
95
95
MilitarylIndustrial
Commercial
7B138-25
7B139-25
110
Military/Industrial
6-88
CY7B138
CY7B139
i§z?cYPRESS
Electrical Characteristics Over the Operating RangdS] (continued)
Parameter
VOH
VOL
Vrn
VIL
IIX
loz
Icc
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Test Conditions
Vee = Min., IOH = -4.0 rnA
Vee - Min., IOL - 4.0 rnA
GND.s. VI.s. Vee
Output Disabled, GND .s. Vo .s. VCC
Com'l
Vee = Max.,
lOUT = 0mA,
Mil/Ind
Outputs Disabled
ISBl
Standby Current
(Both Ports TIL Levels)
c:EL and c:ER z Vrn,
f= fMAX[6]
ISB2
Standby Current
(One Port TIL Level)
CEL and CER Z Vrn,
f= fMAX[6]
ISB3
Standby Clirrent
(Both Ports CMOS Levels)
Both Ports
CE and c:ER Z VCC - 0.2V;
VIN Z Vee - 0.2V
or VIN .s. 0.2V; f = 0[6]
Standby Current
(One Port CMOS Level)
ISB4
One Port
CEL or CER Z V CC - 0.2V;
VIN Z Vee - 0.2Vor
VIN .s. 0.2V; Active
Port Outputs, f = fMAX[6]
7B138-35
7B139-35
Min.
Max.
2.4
0.4
2.2
0.8
-10
+10
-10
+10
210
7B138-55
7B139-55
Min.
Max.
2.4
0.4
2.2
0.8
-10
+10
-10
+10
Unit
V
V
V
V
fAA.
fAA.
210
250
250
Com'l
Mil/Iod
Com'l
Mil!Ind
Com'l
90
95
135
160
15
90
95
135
160
15
Mil/Iod
30
30
Com'l
130
130
Mil!Ind
140
140
rnA
rnA
rnA
rnA
rnA
Capacitance[7]
Parameter
Test Conditions
Description
Input Capacitance
Output Capacitance
CIN
COUT
Unit
pF
pF
Max.
10
15
TA = 25°C, f = 1 MHz,
Vee = 5.0V
AC Test Loads and Waveforms
R1=893Q
~
I
OUTPUT
OUTPUT:-rl
-= R2 = 34m
C = 30 pF
R1=893Q
RTH = 250Q
OUTPU
C=30pF
I
-=
(a) Normal Load (Load 1)
(c) Three·State Delay (Load 3)
6138-4
ALL INPUT PULSES
OUTPU~
.J
C=30pF
3'OV~90%
GND
.s3 ns
Load (Load 2)
6138-6
6138-7
Note:
7. Thsted initially and after any design or process changes that may affect
these parameters.
6-90
-= R2 = 34m
VTH = 1.4V
(b) Thevenin Eqnivalent (Load 1)
6138-3
~
I
C = 5 pF
6138-5
~YPRESS
CY7B138
CY7B139
*_____
Switching Waveforms
--*___
Read Cycle No.1 (Either Port Address Access)[14, 15J
tRC
ADDRESS
DATA OUT
_ _
-:!=DA~,:i'XXXXX*'_. _.-_-_-_-_-_-_-_-_-_-_-_-D_A-:t~A~V_A-L~ID~ ~ ~ ~ ~ ~_=
B138-8
Read Cycle No.2 (Either Port CE/OE Access) [14,16, 17J
SEIJI oreE ~,
_IHZCE-
lACE
).
DATA OUT
ICC
-
IHZOE
IDOE-
~ILZOEtLZCE
..,'-///////,
Ipu
-'
DATA VALID
r-
-tPD
/l
ISB - - . / .
~-9
Read Timing with Port-to-Port Delay (MiS = L)[18, 19J
twc
ADDRESSR
{
)(
MATCH
tpwE
~
/
_tSD
DATAINR
ADDRESSL
~(
(
VALID
f
MATCH
tDDD
)(
DATAouTL
)K
VALID
tWDD
B138 - 10
Notes:
14. R/W is HIGH for read eyele.
15. Device is continuously selected CE = LOW and DE = LOW. This
waveform cannot be used for semaphore reads.
16. Address valid prior to or coincident with CE transition LOW.
17. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when
accessing semaphores.
18. BUSY = HIGH for the writing port.
19. CEL CER LOW..
6-92
=
=
~YPRESS
CY7B138
CY7B139
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[24]
1/00
DATAouT VALID
R/W
6138-13
Timing Diagram of Semaphore Contention[25, 26, 27]
~L-A2L ____________________M_A_T_C_H____________________-J~~___________________
MATCH
R/WR
________________-JJ IoC
SbMR ________________________J
~,--------------------------8138-14
Notes:
24. CE = HIGH for the duration of the above timing (both write and read
cycle).
25. IIOoR = IIOOL = LOW (request semaphore); CER = CEL = HIGH
26. Semaphores are reset (available to both ports) at cycle start.
27. If tsps is violated, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control the
semaphore.
6-94
~YPRESS
CY7B138
CY7B139
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[28]
CEL Valid First:
ADDRESSL,R ____-J~~_____________A_D_D_RE_S_S_M_A_T_C_H_______________J~~_ _ _ _ _ _ _ _ _ _ _ __
CER
mJSYR
CER Valid First:
ADDRESSL,R ____-J~~_____________A_D_D_RE_S_S_M_A_T_C_H_______________J~~_ _ _ _ _ _ _ _ _ _ _ __
__
~ . ~-----:--+r_-:----_
--~-'="1 t " ' l - -
8138-18
Busy Timing Diagram No.2 (Address Arbitration)[28]
Left Address Valid First:
tRcortWC
ADDRESSL
)(
ADDRESS MATCH
ADDRESS MISMATCH
_tpsADDRESSR
--------------------::J
-tBLA
BOSYR
I---tBHA
-1,
i'-~
Right Address Valid First:
8138-19
tRC ortwc
ADDRESSR
)(
ADDRESS MATCH
ADDRESS MISMATCH
-tpsADDRESSL
BOSYL
{
_tBLA
I--tBHA
--::1_~
~
_ __
~
Note:
28. If tps is violated, the busy signal will be asserted au one side or the other, but there is no guarantee on which side BUSY will be asserted.
6-96
8138-20
CY7B138
CY7B139
lircYPRESS
Architecture
Master/Slave
The CY7B 138/9 consists of an array of 4K words of 8/9 bits each of
dual-EQEt RAM cells, I/O and address lines, and control signals
(CE, OE, RiW). These control pins pennit independent access for
reads or writes to any location in memory-\,Th handle simultaneous
writes/reads to the same location, a BUS pin is provided on each
port.1Wo interrupt (INT) pins can be utilized for port-to-port communication.1Wo semaphore (SEM) control pins are used for allocating shared resources. With the MIS pin, the CY7B138/9 can
function as a master (BUSY pins are outputs) or as a slave (BUSY
pins are inputs). The CY7B138/9 has an automatic power-down
feature controlled byCB. Each portis provided with its own output
enable control (OE), which allows data to be read from the device.
A MIS pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input ofthe slave. This will
allow the device to interface to a master device with no external
comp~nents. Writing of slave devices must be delayed until after
the B SY input has settled. Otherwise, the slave chip may begin a
write cycle during a contention situation.When presented as a
HIGH input, the M/S ~n allows the device to be used as a master
and therefore the BUS line is an output. BUSY can then be used
to send the arbitration outcome to a slave.
Semaphore Operation
The CY7B138/9 provides eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used
to reserve resources that are shared between the two ports. The
state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a
latch by writing a zero to a semaphore location. The left port then
verifies its success in settin.£.!!le latch by reading it. After writing
to the semaphore, SEM or OE must be deasserted for tsop before
attempting to read the semaphore. The semaphore value will be
available tSWRD + tDOE after the rising edge of the semaphore
write. Ifthe left port was successful (reads a zero),it assumes control over the shared resource, otherwise (reads a one) it assumes
the right port has control and continues to poll the semaphore.When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the a semaphore.!f the left side no longer requires the
semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM pin
functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). Ao-2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access.When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only 1/00 is used. If a zero is written to the left port of an unused semaphore, a one will appear at the
same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). If the left port now relinquishes control by writing a one to
the semaphore, the semaphore will be set to one for both sides.
However, if the right port had requested the semaphore (written a
zero) while the left port had control, the right port would immediatelyown the semaphore as soon as the left port released it. Table
3 shows sample semaphore operations.
When reading a semaphore, all eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the
other port. If both ports attempt to access the semaphore within
tsps of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
Initialization of the semaphore is not automatic and must be reset
during initialization program at power-up. All semaphores on both
sides should have a one written into themn at initialization from
both sides to assure that they will be free when needed.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge of
R/W in order to guarantee a valid write. A write operation is controlley either the OE pin (see Write Cycle No.1 waveform) or
the R/Wpin (see Write Cycle No. 2wavefonn). Data can be written
to the device tHZOE after the OE is deasserted or tHZWE after the
falling edge of R/W. Required inputs for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port f1owthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and CE
pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user of the CY7B138/9 wishes to access a selIl!lPhore
flag, then the SEM pin must be asserted instead of the CB pin.
Interrupts
The interrupt flag (INT) permits communications between
ports. When the left port writes to location FFF, the right port's interrupt flag (lNTR) is set. This flag is cleared when the rig!!!.port
reads that same location. Setting the left port's interrupt flag (!NTLl is
accomplished when the right port writes to location FFE. This flag
is cleared when the left port reads location FFE. The message at
FFF or FFE is user-defined. See Table 2 for input requirements for
INT. INTR and INTLare push-pull outputs and do not require pullup resistors to operate. BUSYL and BUSYR in master mode are
push-pull outputs and do not require pull-up resistors to operate.
Busy
The CY7B138/9 provides on-chip arbitration to alleviate simultaneous memory location access (contention). Ifboth ports' CBs are
asserted and an address match occurs within tps of each other the
Busy logic will detennine which port has access. If tps is violated,
one port will definitely gain permission to the location, but it is
not guaranteed which one. BUSY will be asserted tBLA after an
address match or tBLC after CB is taken LOW.
6-98
~
CY7B138
=============~C~Y~7B;:;;1~39=
.rcYPRESS
1)rpical DC and AC Characteristics
NORMAUZEDSUPPLYCURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
Jll.2
j
1.0
fil
O.S
N
::::;
~ 0.6
""
lee~
~
-"" V
--
ISB3
1.2
J! 1.0 t::=====::jo<;::;::=--J
.2 O.S
::l
o
~
~
~ 0.4
0.2
0.0
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE
6.0
ISB3
0.61-----+-V
""e-e-=-=-5.""'OV:c--
0.8
~
40
0~5~5---~2~5~---~125
o
0
a: 1.0
TA = 25°C
~
SUPPLY VOLTAGE
0
z
O.S
t...--
0.25
0.0
Vee = 5.0V
-
~
I-- V
o1.0
2.0
~ 40
§ /
oV
~
1~
0.0
25.0
SUPPLY VOLTAGE
o
~
~ 15.0
M
Vee = 5. V _
TA = 25°
1.0
2.0
3.0
4.0
5.0
NORMALIZED Ice vs. CYCLE TIME
II
en
i:d
010.0
5.0
/
1.25
~
4.0
5.0
4.0
OUTPUT VOLTAGE M
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING
[?'
5.0
3.0
60
Z
1il
20
S20.0
1/
oz
3.0
/'
aa: so
AMBIENT TEMPERATURE (OC)
I
a:
"- ......
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~ 100
M
IV
2.0
!z
-~
6.0
1.00
~
1.0
f\.
OUTPUT VOLTAGE IY)
30.0
::::;
~0.50
o
Vee = 5.0V
TA = 25°C
«'140
.§. 120
TYPICAL POWER-ON CURRENT
VS. SUPPLY VOLTAGE
J.
0 0.75
\
en
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
«
::;;
5.5
1\
AMBIENT TEMPERATURE (OC)
,1.1.4
0
L1I
N 1.2
::::;
5.0
~
0.21------1-----_1
0.6
4.5
\
L1I
80
1.6
4.0
160
a:
5
0.41-_ _ _-+_V.:JI~N.::=:..:5::.:.0:..:V_ _I
M
1.4
0.9
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
u 120
NORMAUZED ACCESS TIME
vs. SUPPLY VOLTAGE
" .......... t'-....
§. 200
!z~
~::::;
a:
~
o1/
o
V
Vee = 5.0V
TA = 25°C
VIN = 0.5V
~
~ 0.751-----+:",e.~-+--____l
Vee = 4.5V
TA= 25°C
I
_
I
200 400 600 SOO 1000
CAPACITANCE (pF)
6-100
2S
40
CYCLE FREQUENCY (MHz)
66
•
CY7B138
CY7B139
?cYPRESS
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
VOL
1,2,3
tRC
7,8, 9, 10, 11
Vrn
1,2,3
tAA
7,8, 9, 10, 11
VILMax.
1,2,3
tOHA
7, 8, 9, 10, 11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
loz
1,2,3
tOOE
7,8,9, 10, 11
WRITE CYCLE
Icc
1,2,3
ISB!
1,2,3
twc
7,8, 9, 10, 11
ISB2
1,2,3
tscE
7,8, 9, 10, 11
ISB3
1,2,3
tAW
7,8, 9, 10, 11
ISB4
1,2,3
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7,8, 9, 10, 11
tHD
7, 8, 9, 10, 11
BUSY/INTERRUPT TIMING
tBLA
7, 8, 9, 10, 11
tBHA
7, 8, 9, 10, 11
tBLC
7, 8, 9, 10, 11
tBHC
7, 8, 9, 10, 11
tps
7, 8, 9, 10, 11
tINS
7, 8, 9, 10, 11
tINR
7,8, 9, 10, 11
BUSY TIMING
tWB
7,8, 9, 10, 11
tWH
7, 8, 9, 10, 11
tBDD
7, 8, 9, 10, 11
tDDD
7, 8, 9, 10, 11
tWDD
7, 8, 9, 10, 11
Document #: 38-00162-G
6-102
CY7B144
CY7B145
CirCYPRESS
Pin Configurations
)
9 8 7 6 5 4 3 2 1 68 6766 65 64 63 62 61
1/0 2L
I/DsL
I/04L
I/Ost.
GND
1/0 6L
II0 7t.
Vee
GND
I/OOR
IIQ1R
V02R
Vee
I/O'R
I/04A
!/05R
1/06R
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
63
78144/5
52
51
50
49
48
21
22
23
24
25
g6
47
48
45
44
5AoL
A.,L
AoL
AoL
A,L
AcL
IliITL
SOS'i'L
GND
MiS
IlOSYR
IliITR
AcR
A,.
AoR
AoR
A.,R
~~~~~~~~~~U~~~~~~
11:,&
d'~
II:
II:
a::
a:(JO C
II: II: II:
II: II:
II: II: II:
Iwl;;: >!il!fz z" (!J«<
z OJ - o~~J:.i!'.i!'
'" !;10iE~
8144-2
64·PinTQFP
Top View
I/0 2L
A.,L
I/OSl
I/0 4L
I/OSL
GND
AoL
AoL
AoL
VOSL
IliITL
A'L
IlOSYL
I/OrL
vee
GND
CY78144
MiS
GND
VOOA
I/O,.
I/0 2R
Vee
ItOsR
I/O,"
VaSA
13
14
15
ffl
~
~~~~N~~~~re~re~g~~
IlOSYR
IliITR
AcR
A'R
A2R
AoR
A.,R
8144-3
Notes:
3. I/OSR on the CY7B145.
4. IJOSL on the CY7B145.
6-104
CY7B144
CY7B145
Selection Guide
Maximum Access Time (ns)
Maximum 0serating
Current (rnA
Maximum Standby
Current for ISBI (rnA)
Commercial
7B144-15
7B145-15
15
7B144-25
7B145-25
25
7B144-35
7BI45-35
35
7B144-55
7B145-55
55
260
220
210
210
280
250
95
90
100
95
Military
Commercial
110
Military
90
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to +150°C
Ambient Thmperature with
Power Applied ........................ -55°C to +125°C
Supply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to +7.0V
DC Input Voltagef5j ...................... -O.5V to +7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Notes:
• 5. Pulse width < 20 ns.
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Range
Commercial
Ambient
Temperatnre
Vee
O°Cto +70°C
5V± 10%
Industrial
-40°C to +85°C
5V± 10%
Military[6j
-55°C to + 125°C
5V± 10%
6.
6-106
TA is the "instant on" case temperature.
CY7B144
CY7B14S
Capacitance[9]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COVT
Test Conditions
Max.
10
15
TA = 25°C, f = 1 MHz,
Vcc= 5.0V
AC Test Loads and Waveforms
=rl
R1 = 893'-1
RTH = 250'-1
OUTPUT~
OUTPUT
-=
:rl
5V
5V
C = 30 PFI
Unit
pF
pF
R2 = 347Q
C=30pF
J
!
C=5pF I
VTH = 1.4V
-=
(a) Normal Load (Load 1)
OUTPUT
-=
(b) Thevenin Eqnivalent (Load 1)
R1 = 893'-1
R2=347Q
-=
(e) Three-State Delay (Load 3)
8144-6
B144-5
B144-7
ALL INPUT PULSES
OUTPUT~
,JC=30 PF
90%
3'OV~
10%
~
10%
GND
s3ns
s3ns
Load (Load 2)
8144-8
8144-9
Switching Characteristics Over the Operating Rangel?, 10]
Parameter
READ CYCLE
Description
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address
Change
7B144-15
7B145-15
Min.
Max.
7B144-25
7B145-25
Min.
Max.
15
25
15
7BI44-35
7B145-35
Min.
Max.
35
55
35
25
I
Unit
ns
55
3
3
3
3
7BI44-55
7BI45-55
Min.
Max.
ns
ns
tAcE
CE LOW to Data Valid
15
25
35
55
ns
tDOE
tLZOE[ll, 12]
OE LOW to Data Valid
10
15
20
25
ns
OE Low to Low Z
tHZOE[ll, 12]
OE HIGH to High Z
tLZCE[ll, 12]
rn LOW to Low Z
tHZCE[ll, 12]
CE HIGH to High Z
tpu
CE LOW to Power-Up
tpD
rn HIGH to Power-Down
3
3
3
10
15
10
20
3
3
3
15
0
0
15
3
ns
25
ns
3
20
0
25
ns
25
ns
0
35
ns
55
ns
Notes:
9. Thsted initially aod after any design or process chaoges that may affect
these parameters.
10. Thst conditions assume signal traosition time of 3 ns or less, timing reference levels of 1.5V; input pulse levels ofO to 3.0V; and output loading
of the specified ImlloH aod 30-pF load capacitaoce.
11. At any given temperature aod voltage condition for aoy given device,
lJIZCE is less than tLZCE and tHZOE is less than tLZOE.
12. Thst conditions used are Load 3.
6-108
CY7B144
CY7B145
Switching Waveforms
Read Cycle No.1 (Either Port Address Access)[15, 16J
~~
_ _ _
tRC _
ADDRESS
*~
_
~:-v:;t;XXXX*'-""_-_-_-_-_-_-_-_-_-_-_-D~A_T-A~V~A_L-I_D-_-_-_-_-_-_-_-_-_-_-_-
DATA OUT
8144 10
Read Cycle No.2 (Either Port CE/OE Access)[15, 17, 18J
SEMor"CE
DATAOUT----~--------------~~iS~~~------~~~~~----_+------~~---ICC
Iss
Read Timing with Port-to· Port Delay (MiS = L)[19, 20J
twc
ADDRESSR
)~
MATCH
tpWE
~
/
~tso
DATAINR
ADDRESSL
~~
(
*1.
VALID
MATCH
tO~~
)(
DATAouTL
)~
twoo
B144 - 12
Notes:
15. R/W is HIGH for read cycle.
16. Device is continuously selected CE = LOW and OE = LOW. This
waveform cannot be used for semaphore reads.
17. Address valid prior to or coincident with CE transition LOW.
18. c:EL =L, SEM =H when accessing RAM. CE = H, SEM = L when
accessing semaphores.
19. BUSY = HIGH for the writing port.
20. c:EL = CER = LOW.
6-110
CY7B144
CY7B145
.CYPRESS
Switching Waveforms (coritinued)
Semapbbre Read After write Timing; Either Side[25J
1/°0
DATAouT VALID
R/W
---*0---- IOOE
8144-15
Semaphore Contention[26, 27, 28J
~L-A2L ____________________M_A_T_C_H__~________________-J~~___________________
::----E.~MATCH
R/WR
---------------------'
~
"SEI\lR ____________________- ' ~
6144-16
Notes:
25.
cr = HIGH for the duration ofthe above timing (both write and read
cycle).
26. 1I0oR = 1I00L = LOW (request semaphore); CER = CEL = HIGH
27. Semaphores are reset (available to both ports) at cycle start.
28. If tsps is violated, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control the
semaphore.
6-112
CY7B144
CY7B145
QYPRESS
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration) [29]
CEL Valid First:
X
ADDRESSL,R
~"k
"CEL
ct:R
BUS'i'R
tBLC~
CER Valid First:
X
ADDRESSL,R
eEL
t'~1
BUS'i'L
tBLC~
8144-19
X
ADDRESS MATCH
~"k
eER
X
ADDRESS MATCH
t~1
8144-20
Busy Timing Diagram No.2 (Address Arbitration)[29]
Left Address Valid First:
tRC ortwc
(
ADDRESSL
ADDRESS MATCH
) (
ADDRESS MISMATCH
_tps-
)(
ADDRESSR
--1""----1-~taLA
R
-tBHA
8144-21
BlJSY Valid First:
Right Address
tRcortWC
ADDRESSR
)~
ADDRESS MATCH
ADDRESS MISMATCH
i.--tps_
ADDRESSL
)~
--::j~-1I-I4-tBLA
BUS'i'L
~tBHA
~
Note:
29. If tps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
30. tHA depends on which enable pin (CEL or RlWLJ is deasserted first.
8144-22
31. tINS or tINR depends on which enable pin (eEL or RlWLJ is asserted
last.
6-114
CY7B144
CY7B145
=jj iEYPRESS
Architecture
Master/Slave
The CY7B144/5 consists of a an array of 8K words of 8/9 bits each
of du~ort ~M cells, I/O and address lines, and control signals
(CE,OE, R/W). These control pins permit independent access for
reads or writes to any location in memory. Th handle simultaneous
writes/reads to the same location, a BUSY pin is provided on each
port. Tho interrupt (INT) pins can be utilizedforport-to-portcommunication. Tho semaphore (SEM) control pins are used for allocating shared resources. With the M/S" pin, the CY7B144/5 can
function as a Master (BUS"Y pins are outputs) or as a slave (BUSY
pins are inputs). The CY7B144/5 has an automatic power-down
feature controlled by CE. Each port is provided with its own output
enable control (OE), which allows data to be read from the device.
An MIS" pin is provided in order to expand the word width by configuring the device as either a master or a slave. The"Ei'OS"Y output of
the master is connected to the BUSY input ofthe slave. This will
allow the device to interface to a master device with no external
comp~nents.Writing of slave devices must be delayed until after
the B SY input has settled. Otherwise, the slave chip may begin a
write cycle during a contention situation.When presented a HIGH
input, the MIS" pin allows the device to be used as a master and
therefore the BUSY line is an output. BUSY can then be used to
send the arbitration outcome to a slave.
Semaphore Operation
The CY7B144/5 provides eight semaphore latches which are separate from the dual-port memory locations. Semaphores are used
to reserve resources that are shared between the two ports. The
state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a
latch by writing a 0 to a semaphore location. The left port then
verifies its success in setting the latch by reading it. After writing
to the semaphore, SEM or OE must be deasserted for tsop before
attempting to read the semaphore. The semaphore value will be
available tSWRD + tDOE after the rising edge of the semaphore
write. If the left port was successful (reads a 0), it assumes control
over the shared resource, otherwise (reads a 1) it assumes the
right port has control and continues to poll the semaphore. When
the right side has relinquished control of the semaphore (by writing a 1), the left side will succeed in gaining control ofthe semaphore. If the left side no longer requires the semaphore, a 1 is
written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM pin
functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). Ao-2 represents the semaphore
address. OE and RiW are used in the same manner as a normal
memory access.When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only 1/00 is used. If a 0 is written
to the left port of an unused semaphore, a 1 will appear at the same
semaphore address on the right port. That semaphore can now only
be modified by the side showing 0 (the left port in this case). If the
left port now relinquishes control by writing a 1 to the semaphore,
the semaphore will be set to 1 for both sides. However, if the right
port had requested the semaphore (written a 0) while the left port
had control, the right port would immediately own the semaphore
as soon as the leftportreleasedit. Table 3 shows sample semaphore
operations.
When reading a semaphore, all eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the
other port. If both ports attempt to access the semaphore within
tsps of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
Initialization of the semaphore is not automatic and must be reset
during initialization program at power-up. all Semaphores on both
sides should have a one written.into them at initialization from
both sides to assure that they will be free when needed.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge of
R/W in order to guarantee a valid write. A write operation is controlle~y either the OE pin (see Write Cycle No.1 waveform) or
the R/W pin (see Write Cycle No.2 waveform). Data can be written
to the device tHzOE after the OE is deasserted or tHZWE after the
falling edge of R/W. Required inputs for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and CE
pins. Data will be available tACE after CE or tDOE after OE are asserted. If the user of the CY7Bl44/5 wishes to access a semaphore
flag, then the SEM pin must be asserted instead of the CE pin.
Interrupts
The interrupt flag (INT) permits communications between
ports. When the left port writes to location 1FFF, the right port's interrupt flag (IN"TR) is set. This flag is cleared when the ri@!yort
reads that same location. Setting the left port's interrupt flag (INTL) is
accomplished when the right port writes to location 1FFE. This
flag is cleared when the left port reads location 1FFE. The message
at 1FFF or IFFE is user-defined. See Table 2 for input requirements for IN'f. INTRand INTL are push-pull outputs and do not
require pull-up resistors to operate.
Busy
The CY7B144/5 provides on-chip arbitration to alleviate simultaneous memory location access (contention). Ifboth ports' CEs are
asserted and an address match occurs within tps of each other the
Busy logic will determine which port has access. If tps is violated,
one port will definitely gain permission to the location, but it is not
guaranteed which one. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. BUSYLand BUSYR
in master mode are push-pull outputs and do not require pull-up
resistors to operate.
6-116
CY7B144
CY7B145
'!ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NO~ZEDSUPPLYCURRENT
vs. SUPPLY VOLTAGE
1.4
fa
~ 0.6
a:
o
z
,.. ~
0.8
::::i
:[200
I-
15
lee~
ii 1.0
N
1.2
.-
Jll.2
1883
~
o
0.8
::::i
0.6
~
"""'"
oz
0.2
0.0
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
J.
0.21----+------1
NO~ZED ACCESS TIME
vs. AMBIENT TEMPERATURE
w
~
g
!3
\
0
o
1.0
Vee = 5.0V
TA = 25'C
\.
2.0
"-
~
3.0
5.0
4.0
OUTPUT VOLTAGE (V)
1.4
1.3
J.l.4
!z
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
.s 120
o
W
N
~
r-...
.............
a:
~ 1.0
I'-......
0.9
0.8
4.0
~
gj
1.2
1.0
z
-
V--
Vee = 5.0V
Ii!
100
5
80
I<:
Z
60
!3
40
a:
en
o
-55
6.0
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
25
125
AMBIENT TEMPERATURE ('C)
I
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT WADING
0 0 .75
w
N
::J
~0.50
a:
oz
0.25
o
-
V
/
en
5.20.0
:1
~ 15.0
m
010.0
5.0
I----
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
5.0
o
Vee = 5. V_
TA = 25'
'1
1.0
2.0
3.0
4.0
5.0
'NO~ZED
Icc vs. CYCLE TIME
1.25
25.0
I
II
/
OUTPUT VOLTAGE (V)
30.0
g.
/'
20 /
o1/
0.0
~
0.8
0.6
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
1.00
0.0
~
40
o~
2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 mA
Ambient
EeL
TTL
I/O Version Thmperatnre
VEE
Vee
10K
10E
-5.2V ± 5V±
O°Cto
lOKH
5%
5%
+75°C
-4.2Vto 5V±
Commercial lOOK 10lE
O°Cto
-5.46V
5%
+85°C
Range
Commercial
Military
7-2
10K
10KH
10E
-55°C
to +l25°C
case
-5.2V ± 5V±
5%
5%
CYIOE383
CYIOIE383
~
=-- -.~
=-'CYPRESS
Switching Waveforms (continued)
Skew Test (tSKT)
TTLQn-to-TTLQn+m
(0"~--j ._ _
1=_;SV-tSKT=1-
-------------J
~
1.5V
E3B3·10
...
)~50%
50%
--tSKE--
I--tsKE-
Qn+m(ECL)
~I{" 50%
) ( 50%
On+m(ECL)
~tsKE-
--tSKE--
,Table 1. CY101E383 Nominal Voltages Applied in lOOK System
ECL-to-TTL Truth Table
Inputs
Outputs
ECLDn
ECLDn
TTLQn
Open[17]
Open[l7]
L
L
H
L
L
H
H
Supply Pin
Single-Supply
System
Dual-Supply
System
TIL Vee
+S.OV
+S.OV
TILGND
O.OV
O.OV
ECLVee
+S.OV
O.OV
O.OV
-4.5V
ECLVEE
Table 2. CY101E383 Nominal Voltages Applied in 101K System
TTL-tli-ECL Truth Table
Inputs
Outputs
TTLDn
ECLQn
ECLQn
L
L
H
H
E3B3--11
H
L
Nominal Voltages
The cYlOl/lOE383 can be used in dual ±SV or single +SV supply
systems. The supply pins sl;lOuld be connected as shown in Tables 1
and 2. This connection technique involves shifting up all ECL supply pins by sv. When operatirig in single-supply systems, the ECL
termination voltage level must also be shifted up by adding Sv. For
example, if the termination is SO ohms to - 2V in a dual-supplysystern, the single + SV system should have SO ohms to + 3V. If the termination is a thevenin type, then the resistor tied to ground is now
at + SV and the resistor tied to - SV is now at ground potential.
Consideration should be given to the power supply so that adequate bypassing is made to isolate the ECL output switching noise
from the supply. Having separate TIL and ECL + SV supply lines
will help to reduce the noise. Table 3 shows the CYlOE383 nominal
voltages applied in a 10K system.
Supply Pin
Single-Supply
System
Dual.Supply
System
TIL Vee
+S.OV
+S.OV
TILGND
O.OV
O.OV
ECLVee
+S.OV
O.OV
ECLVEE
O.OV
-S.2V
Table 3. CY10E383 Nominal Voltages Applied in 10K System
Supply Pin
Single-Supply
System
Dual-Supply
System
TIL Vee
+S.OV
+S.OV
TILGND
O.OV
O.OV
ECLVee
+S.OV
O.OV
ECLVEE
O.OV
-S.2V
Not.:
17. The EeL inputs will pull to a known logic level ifleft open.
7-6
CY7B923
CY7B933
HOTLink@)
Transmitter/Receiver
Features
Functional Description
•
•
•
•
•
•
•
•
•
•
The CY7B923 HOTLink'!B) Transmitter
and CY7B933 HOTLink Receiver are
point-to-point communications building
blocks that transfer data over high-speed
seriallinks (fiber, coax, and twisted pair) at
160 to 330 Mbits/second. Figure 1 illustrates typical connections to host systems
or controllers.
Eight bits of user data or protocol information are loaded into the HOTLink transmitter and are encoded. Serial data is
shifted out ofthe three differential positive
ECL (PECL) serial ports at the bit rate
(which is 10 times the byte rate).
The HOTLink receiver accepts the serial
bit stream at its differential line receiver inputs and, using a completely integrated
PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. The bit stream is deserialized,
•
•
•
•
•
Fibre Channel compliant
IBM ESCON@ compliant
ATM-compliant
SB/10B-coded or 10-bit unencoded
160- to 330-Mbps data rate
TTL synchronous I/O
No external PLL components
Triple PECL lOOK serial outputs
Dual PECL 100K serial inputs
Low power: 350 mW (Tx),
650 mW (Rx)
Compatible with fiber optic modules,
coaxial cable, and twisted pair media
Built-In Self-Test
Single +5V supply
2S-pin SOIC/PLCC/LCC
0.811 BiCMOS
CY7B923 Transmitter Logic Block Diagram
decoded, and checked fortransmission errors. Recovered bytes are presented in
parallel to the receiving host along with a
byte rate clock.
The 8B/10B encoder/decoder can be
disabled in systems that already encode or
scramble the transmitted data. I/O signals
are available to create a seamless interface
with both asynchronous FIFOs (i.e.,
CY7C42X) and clocked FIFOs (i.e.,
CY7C44X). A Built-In Self-Test pattern
generator and checker allows testing ofthe
transmitter, receiver, and the connecting
link as a part of a system diagnostic check.
HOTLink devices are ideal for a variety of
applications where a parallel interface can
be replaced with a high-speed point-topoint serial link. Applications include
interconnecting workstations, servers,
mass storage, and video transmission
equipment.
CY7B933 Receiver Logic Block Diagram
RF
INA+
NB
INA-
---'h--C~===:::==~
INB (INB+)
Sl (INB-)
so
CLOCK
GENERATOR
REFCLK
------I
MODE
MODE . .
BTSTrn . .
BISTEN
8923-1
sell) (Q a)
8923-2
gu
~a
09
0:
O'C
Output Differential Voltage
VODIFF
Three-Level Input Pins (MODE)
Three-Level Input HIGH
VIHH
Three-Level Input MID
VIMM
Three-Level Input LOW
VILL
Operating CurrentLJ J
Ices
ICCR
IeCT
ICCE
Ices
Iceo
Vee - 1.86
0.6
V
V
Vee
Vee
Vee
Vee - 1.475
0.8
Vee- 0.83
Vcc - 0.83
Vee - 1.62
V
V
V
Vee
Ved2 + 0.5
1.0
V
V
V
Static Operating Current
30
rnA
Receiver Operating Current
1tansmitter Operating Current
ECL Pair Operating Current
Additional Current at 51.84 MHz
50
13
7.0
7.0
rnA
rnA
rnA
rnA
Additional Current LFI-LOW
3
rnA
Vee - 1.0
Ved2-0.5
0.0
Capacitance[6]
Parameter
Description
Input Capacitance
Test Conditions
TA = 25°C, to = 1 MHz, Vee = 5.0V
7-40
CY7B951
.rcYPRESS
Switching Waveforms for the CY7B951 SONET/SDH Serial Transceiver
REFCLK
----c='"~
t--
t~
-=1~
~-,.
TSER±
(RIN±)
TOUT±
(ROUT±)
78951-10
~=~to~o~c===~_--tooc
RCLK+
j4----'--tov -------oi---- tOH
RSER±
78951-11
RIN±
78951-12
Ordering Information
Speed
(ns)
25
Ordering Code
Package
Name
Package 'Jype
Operating
Range
CY7B951-SC
S13
24-Lead (300-Mil) Molded SOIC
Commercial
CY7B951-SI
S13
24-Lead (300-Mil) Molded SOIC
Industrial
Document #: 38-00358-C
7-42
PRELIMINARY
CY7C971
Pin Configuration
SO-Lead Plastic Quad F1atpack
(Top View)
PINl
RX03
RX02
GNOO
RXOl
RXOO
RX_OV
Rx_elK
RJCER
TJLER
VCCS
RX.J)4TJL04GNOS
r><....04+
R>CD4+
vccs
RX_03TJL03GNOS
TX_D3+
R)L03+
VCCS
RJL02-
vcco
TJLCLK
TJLEN
TXOO
TXOl
TX02
TX03
GNOO
Rx....02+
VCCS
TJLD1GNOS
05
r><""01+
COL
CRS
vccs
7C971·2
Maximum Ratings
(Above which the usefullife may be impaired. Foruser guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied ........................ -55°Cto+125°C
Supply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to + 7.0V
DC Input Voltage ........................ -3.0V to +7.0V
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
.
Latch-Up Current ............................ >200 rnA
Operating Range
7-44
Range
Commercial
Ambient
Temperature
O°Cto +70°C
Vee
5V ± 10%
-=,
~YPRESS=========P=nE==Ll=M=IN.=~=R=Y=========CY=7=C=97~1
Pin Descriptions (continued)
Media"Dependent Interface
Name
I/O
TX D1+
Differential
Output
TX:::I?l-
lUCD2-
RX D2+
Differential
Input
TXD3+
TX:::D3-
Differential
Output
Description
'Itansmit Data. TX D1 ± are differential line drivers for data transmission. In lOBASE-T mode
TX_D1± transmit Manchester encoded data with a nominal period of 100 ns. In 100BASE-T4
mode TX_D1 ± transmit 8B6T ternary symbols with a nominal period of 40 ns. TX_D1 ± also participate in the link Integrity function.
Receive Data. RX):?2± are differential line receivers for data reception. In 100-Mb/s mode,
RX_D2± receives 8B6T ternary symbols with a nominal period of 40 ns. In lO-Mb/s mode,
RX_D2± receives Manchester encoded bits with a nominal period of lOOns. RX_D2± alsoparticipates in the Link Integrity function.
Transmit Data. TX D3± are differential line drivers for data transmission. In 100-Mb/s mode,
TX_p~± transmits6Tternary symbols with a nominal period of 40 ns. In 10-Mb/s mode, TX_D3±
are not used.
RX D3+
Differential
Receive Data. RX_D3 ± are differentialline receivers used for data reception. In 100-Mb/s mode,
Input
RX_D3± receives 6T ternary symbols with a nominal period of 40 ns. In 10-Mb/s mode, RX_D3±
RX:::D3are not used.
TX D4+
Differential
1tansmit Data. TX D4± are differential line drivers used for data transmission. In 100-Mb/s
Output
mode, TX_D4± transmits 6T ternary symbols with a nominal period of 40 ns. In 10-Mb/s mode,
TX:::D4TX D4± are no! used.
Receive Data. RX_D4± are differential line receivers used for data reception. In 100-Mb/s mode,
RX D4+
Differenti!!!
RX:::D4Input
RX_D4± receives 6T ternary symbols with a nOlpinal period of 40 ns. In lO-Mb/s mode, RX_D4±
are not used.
.. "
Physical Media Attachment Interface
Description
Name
I/O
MODE
Mode. When MODE is tied HIGH, the transceiver is in normal mode. Received and tranmitted
Input
dllta will move through the PMA and the PCS sublayers. Asserting MODE LOW exposes the
(TTL)
iOOBASE-T4 PMA service interface and disables 10BASE-T. The PCS is bypassed and the binary
coded 6T serial data is presented at the Mil and PMA interface pins.
D5
Input
PMA Input Data. D5 is an input signal to the PMA transmit sublayer when MODE is asserted
LOW..
(TTL)
Q5
Output
(TTL,
Three State)
Control and Status
Name
I/O
RESET
Input
(TfL)
AUTONEG Input
(TTL)
ENT4
Inpllt
(TTL)
ENT
Input
(TTL)
ENTFD
Input
(TTL)
ISODEF
'Input
(1TL)
LOOP
Input
(TTL)
PMA Output Data. Q5 is an out~ut signal from the PMAreceive sublayerwhen MODE is asserted
LqW. Q5 is j1igh-impedence w en RX_EN is HIGH.
Description
Reset. When RESET is asserted LOW, the PHY is placed in the reset state and the transmit and
receive functions are disables. The MIl registers are placed in their default states.
Auto-Negotiation Enable. When asserted HIGH, Auto-Negotation capability is enabled by setting
the Status Register bit 1.3. Auto-Negotation is controlled through the MIl management registers.
When asserted LOW, Auto-Negotation capability is disabled. AUTONEG is sampled on the rising
c;dge of RESET.
Enable 100BASE-T4. ENT4 enables 100BASE-T4 operation by setting the Status Register bit
1.15. WQen ~NT4 is HIGH, bit 1.15 is forced HIGH, enabling 100BASE-T4 operation. When
ENT4 isLO .; bit 1.15 is forced LOW, disabling 100BASE-T4. ENT4 is latched on the rising edge
of RESET.
Enable lOBASE-T. ENT enables lOBASE-T operation by setting the Status Register bit 1.11.
When ENT js HIGH, bit 1.11 is forced HIGH, enabling lOBASE-T operation. When ENT4 is
LOW, bit 1.11 is forced LOW, disabling 10BASE-T. ENT is latched on the rising edge of RESET.
Enable lOBASE-T Full Duplex. ENTFD enables lOBASE-T Full Duplex operation by setting the
Status Register bit 1.12. When ENTFD is HIGH, bit 1.12 is forced HIGH, enabling 10BASE-TFull
Duplex operation. When ENTFD is LOW, bit 1.12 is forced LOW, disabling lOBASE-T Full Duplex. ENTFD is latched on the rising edge of RESET.
Isolate Default. ISODEF determines the default state of Isolate Bit 0.10 in the Control Register.
When ISODEF is HIGH, the default value for 0.10 is 1. When ISODEF is LOW, the default value
for 0.10 is O. ISODEF is latched on the rising edge of RESET.
Loopback Enable. When asserted LOW, the transmitter bit stream is looped back to the receiver
for diagnostic testing. When LOOP is HIGH, the Loopback function is controlled by the Loopback
bit in thi: control register.
7-46
PRELIMINARY
CY7C971
1OBASE-T/100BASE-T4
Transceiver Card
CY7C971
Transceiver
802.3
MAC
Mil
7C971-3
Figure 1. Transceiver Card Block Diagram
Transmit Physical Coding Sublayer (PCS)
CY7C971 Description
IOOBASE-T4
The pes takes nibble-wide data from the Mil and accumulates
them into 8-bit octets in the TXDI and TXD2 registers. The octets
are then encoded using the 8B6T ternary code according to the
802.3 standard. The encoded 8B6T code groups are then loaded in
binary form to the shift registers.
Three shift registers convert the parallel 8B6T code groups to serial form. When the transmitter is active, a shift register is loaded on
every otherTX_CLKcycle. The first 8B6T code group of the frame
is loaded into TX_shiftl. The second group is loaded into
TX shift2 and the third into TX shift3. The 4th group will be
loaded into TX_shiftl. This sequence continues until all of the
8B6T code groups comprising the frame have been transmitted.
At the start of the transmit frame, TX shift2 and TX shift3 will be
loaded with a pad sequence aligned With first 8B6T code group in
TX_shiftl. The pad sequence aides the receiver with clock recovery and pair alignment. The preamble is generated automatically
and follows the pad sequence.
The CY7C971 provides a physical layer interface (PHY) for dual
speed IEEE 802.3 100BASE-T4 and 10BASE-T CSMA/CD local
areanetworks.lOOBASE-T40ffersincreasedperfonnanceoverexisting lOBASE-T networks while maintaining compatibility with
the existing Ethernet Media Access Control (MAC) specification.
The 100BASE-T4 PHY interfaces to 4 pairs of category 3, 4, or 5
cable. The lOOBASE-T4 PHY is comprised of the Physical Coding
Sublayer (PCS), Physical Media Attachment (PMA), Media Independent Interface (MIl), and Media Dependent Interface (MDI).
A typicaI100BASE-T4 transceiver card application is shown in Figure 1.
Transmitter
The transmitter is comprised of the Physical Coding Sublayer
(PCS) and the Physical Media Attachment (PMA). Figure 2 shows
a block diagram of the T4 transmitter.
.....................
-
...............
----
...
T
pes
8B6T
Encoder
1-'6:.:;X~2'-4..-_ _ _ _"l.
7C971-4
Figure 2. T4 Transmitter Block Diagram
7-48
$$
~YPRESS==========P=RE=L=1=M=IN=~=R=Y==========CY=7=C=97=1=
Manchester I-'T""--"'~
Encoder
Link
Integrity
COL_----;
CRS _ - - - - ;
RXD[3:0]
RX_DV
RX C L K _ - - - - - 4 t - - - - - - - - - - - - 1
(2.5 MHz)
7C971·6
Figure 4. lOBASE-T Transmitter & Receiver Block Diagram
Full Duplex
The CY7C971 supports Full Duplex operation in lOBASE-T
mode. lOBASE-T Full Duplex operation is automatically selected
ifAuto-Negotation established 10BASE-TFullDuplexas the highest common operating mode. The lOBASE-T Full Duplex operation can also be selected manually by disabling Auto-Negotation
and clearing the Speed Selection (0.13) bit and setting the Duplex
Mode Bit (O.S) in the MIl Control Register. 10BASE-T Full Duplex mode cannot be enabled through Auto-Negotation or manually uuless the the ENTFD pin is HIGH. The LINKFD pin indicates when lOBASE-T Full Duplex is the selected mode of
operation and the lOBASE-T transceiver is in the Link Pass State.
During full duplex operation, the collision pin (COL) is LOW,
Auto-Polarity Correction
The Auto-Polarity Correction function monitors the received signal polarity on RX_D2± and inverts the received signal internally
if its polarity is inverted. Auto-Polarity Correction is active during
Auto-Negotation and normal operation.
Media Independent Interface (MIl)
The MIl provides a connection between the PHY and the MAC
and between the PHY and the station management (STA) entity.
The MIl is capable of supporting 100- and 10-Mb/s operation.
Data transfer is accomplished over nibble-wide dedicated transmit
and receive channels. When TX EN is asserted HIGH, data on
TXD[3:0j channel is latched into the PHY on the rising edge of
TX_CLK and passed to the PCS. IfTX_ER is asserted HIGH, an
SB6T code violation word will be sent in place of the transmit data.
TX_CLK provides a continuous clock that is sourced from the
PHY.
When recovered data is available from thePCS, the RX_DV signal
is asserted HIGH simultaneously with the first Start of Frame Delimiter (SFD) nibble on RXD[3:0j. The RX_DV signal remains
HIGH continuously through the final recovered nibble of the
frame. If an error is detected in the frame by the PHY, the RX_ER
signal is driven HIGH synchronously with RX_CLK
RX_CLKis a continuous clock that provides a timing reference for
the transfer ofRXD[3:0j, RX_DY, and RX_ERfrom thePHYto
the MAC. RX CLK is sourced from the PHY. While RX DV is
deasserted, R5(CLK will run at the PHY's nominal frequency.
When RX_DVis asserted, the frequency and phase ofRX_CLKis
recovered from the received data. During the transition from nominal to recovered frequency, the period of RX_CLKmay extend by
up to one cycle. RX_ CLK stretching prevents logic failures from
oeeuring in downstream logic while the clock makes it transition.
When a carrier is detected, the CRS signal is asserted HIGH. A
collision is signaled by asserting COL HIGH. CRS is asserted
throughout a collision condition.
Access to the management facilities are provided throughtthe MIl
with the MDC and MDIO pins. These pins provide a serial interface to the management control and status registers. The MOC signal is driven to the PHY from the management station (STA) as a
timing reference for transfer of information on the MOlD signal.
The MDIO signal is a bidirectional signal between the PHY and
the STA. Control information is driven by the STA to the PHY.
Status information is driven from the PHY to the STA.
7-50
PRELIMINARY
CY7C971
Thble 2. MIl Status Register Definition
Status Register (Register 1)
Bit(s)
R/W
Default
Description
1.1514 J
100BASE-T4
1 =100BASE-T4 Able
o = 100BASE-T4 Able
RO
1,0
When set, this bit indicates that
the PHY is 100BASE-T4 capable.
1.14
100BASE-TX Full Duplex
O = 100BASE-TX Full Duplex
Not Supported
RO
0
This bit is always set to zero.
1.13
100BASE-TX Half Duplex
O = 100BASE-TX Half Duplex
Not Supported
RO
0
This bit is always set to zero.
1.1215J
lOBASE-T Full Duplex
1 - lOBASE-T Full Duplex Able
RO
1,0
When set, this bit indicates that
the PHY is lOBASE-T full duplex
capable.
1. 11 16J
10BASE-T Half Duplex
1 - lOBASE-T Half Duplex Able
0= 10BASE-THalfDuplexAble
RO
1,0
When set, this bit indicates that
the PHY is 10BASE-T half duplex
capable.
1.10:6
Reserved
0= Default
RO
0
1.5
Auto-Negotiation
Complete
1 = Auto-Negotiation Complete
0= Auto-Negotiation Incomplete
RO
0
This bit is set when NWAY has
completed the auto negotiation
process.
1.4
Remote Fault
1 = Remote Fault Condition
0= No Remote Fault Condition
RO
0
This bit is set when Auto Negotiation detects a remote fault.
1.31/J
Auto Negotiation Ability
1 = PHY is Able to Perform Auto
Negotiation
RO
1,0
PHY supports Auto-Negotiation.
1.2
Link Status
1 = Link Is Up
RO
0
Link Status indicates that the
PHY is in the Link Pass State.
1.1
Jabber Detect
o = No Jabber Condition
1 - Jabber Condition Detected
RO
LH
0
Jabber Detect indicates that ajabber condition has been detected
for 10BASE-T.
1.0
Extended Capabilities
1 - Extended Register Capable
RO
1
OUI and Auto-Negotiation Extended Registers 2 - 7 are present.
Name
Setting
o = 10BASE-T Full Duplex Able
o = Link Is Down
Detected
Vendor and Prodnct ID Registers
Vendor and Product identification codes are stored in management ID registers 2 and 3. These registers contain the Cypress
Semiconductor Corporation unique identifier and the CY7C971
product and revision number. Table 3 explains the ID registers.
Auto-Negotation Registers
The Auto-Negotation process is managed through the Auto-Negotation registers. Register 4 is the Auto-Negotation Advertisement register. This register contains the 16-bit code word that is
advertised to the remote link partner. Register 5 is the Auto-Negotation Link Partner Ability register for base and next pages. This
register holds the 16-bit code word that the Auto-Negotation function receives from the remote link partner. Register 6 is the AutoNegotation Expansion register and is used to monitor the negotiation process. Register 7 is the Auto-Negotation Next Page
Transmit register. The function of the Auto-Negotation register
bits are defmed in Tables 4 through 7.
Auto-Negotation
Auto-Negotation advertises the capabilities of the PHY by transmitting a sequence of fast link pulses (FLPs) that form a standard
16-bit code word. The advertised code word is contained in the
Auto-Negotation Advertisement register (Register 4). Auto-Negotation receives 16-bit code words and stores them in the AutoNegotation Partner Ability register (Register 5). Once the code
words have been sent and acknowledged, Auto-Negotation selects
the highest common operating mode as the current mode of operation. The highest common mode of operation is determined by the
Priority Resolution Thble specified in the Auto-Negotation standard. When a mode of operation is selected, Auto-Negotation enables the transition to the selected mode's Link Pass state.
TheAuto-Negotation process is controlled and monitored through
the MIl management registers. Auto-Negotation may be disabled
in the MIl control register or by asserting the AUTONEG pin
HIGH.
The Auto-Negotation is capable of transmitting and receiving code
word pages in addition to the base pages. The next page process is
controlled through the MIl registers.
The IEEE Auto-Negotation function provides remote capability
detection and automatic speed selection. Auto-Negotation is fully
compatible with existing lOBASE-T only devices.
Notes:
4. lOOBASE-T4 Default is set by the ENT4 pin.
5. lOBASE-T FD Default is set by the ENTFD pin.
6.
7.
7-52
lOBASE-T HD Default is set by he ENT pin.
Auto-Negotiation Default is set by the AUTONEG pin.
='
. -1
~.
PRELIMINARY
CY7C971
, CYPRESS~======~====
Thble S. MIl Auto·Negotation Link Partner Ability Register Definition
Auto.Negotati~n
Link Partner Ability Register (RegIster 5)
Setting
R/W
Default
Description
1 = Next Page to be 1tansmitted
o = No Next Page
RO
0
When set, this bit indicates the
remote PRY has a Next Page to
send.
1 = Remote Acknowledge
RO
0
When set, this bit indicates that
the remote PRY has acknowl·
edged receipt of a page.
Remote Fault
1 = Fault Indication
0= No Fault
RO
0
When set, this bit indicates that a
fault has ocurred in the remote
PRY.
5.12
Thchnology Ability Field
ReselVed
ReselVed
RO
0
ReselVed.
5.11
Technology Ability Field
ReselVed
ReselVed
RO
0
ReselVed.
5.10
Thchnology Ability Field
ReselVed
ReselVed
RO
0
ReselVed.
RO
0
When set, this bit indicates that
the
remote
PRY
has
100BASE·T4 capability.
Bit(s)
Name
5.15
Remote Next Page
5.14
Remote Acknowledge
5.13
5.9
Thchnol~ Ability
Field
o = No Acknowledge
..,
1 = 100BASE·T4 Able
100BAS ·T4
(j = Not 100BASE·T4 Able
5.8
Technology Ability Field
100BASE·TX FuII Duplex
1 = 100BASE·TX FD Able
o = Not 100BASE·TX FD Able
RO
0
When set, this bit indicates that
the remote PRY has 100BASETX FD capability.
5.7
Thchnology Ability Field
100BASE-TX
o = Not OOBase-TX Able
1 = 100BASE-TX Able
RO
0
When set, this bit indicates that
the remote PRY has 100BASETX capability.
5.6
Thchnology Ability Field
10BASE-T Full Duplex
o = Not 10BASE-T Able
1 - 10BASE-T FD Able
RO
0
When set, this bit indicates that
the remote PRY has 10BASE-T
FD capability.
5.5
Technology Ability Field
10BASE-T
o = Not lOBASE-T Able
1 = 10BASE-T Able
RO
0
When set, this bit indicates that
the remote PRY has 10BASE-T
capability.
5.4:0
Selector Field
Indicates LAN 'JYpe
RO
OOh
This field indicates the type of
LANs being advertised by the remote PRY.
.
7-54
£
i:i~
. , CYPRESS
CY7C971
PRELIMINARY
T4 Receiver
Repeater
.------------------.CRS
T4 Transmitter
Link
LlNKT4 +------1 Integrity
CLKI
7C971·7
Figure S. T4 Transmitter & Receiver PMA Interface and Block Diagram (MODE = WW)
Serial 6T data from the three PMA circuits are transferred over the
PMA interface pins in binary form. The Receiver aligns and converts the line signals to their 6T binary representation and drives
them to the 0[5:0] pins. The transmitter latches the three 6Tsymbol streams on its D[5:0] input pins on the rising edge ofTX_CLK.
The 6T symbols are loaded into the waveshaper DAC and converted to their corresponding ternary waveforms. Table 8 shows the
mapping of binary PMA signals to ternary waveforms.
Thble 8. PMA Binary to Ternary Map[ll]
PMA
QI-0, Q3-2, QS-4
01-0, D3-2, DS-4
Transmitter
Receiver
00
CSO
CSO
10
CS1
CS1
01
CS-1
CS-1
11
CSO
-
The RX_DV signal indicates when the first data symbol after sosb
is present on the 00- 5 PMA interface pins. RX_DV will remain
HIGH throughout the transfer of data symbols across the PMAinterface. RX_DV is LOWwhen there is no carrier present. RX_ER
HIGH indicates a pair alignment error. The RX_EN input pin enables the 00-5, RX DV, and RX ER drivers. RX EN LOW
places the drivers in the high-impedence state.
The transmit PMA interface is synchronous to the CLKI input
clock signal. The TX_EN HIGH causes data on the PMA DO-5
pins to be loaded into the transmit PMA waveshaper on the rising
edge of CLKI. When TX_EN is LOW, the output drivers transmit
the CSO idle symbols.
Applications
The CY7C971 is a flexible physical-layer device that fits into any
Ethernet application including network interface cards, transceiver cards, repeaters, hubs and switches. Figure 6 shows a schematic
ofthe CY7C971 configured for a transceiver card application with
an exposed MIl port.
Notes:
11. CSO is a waveform which conveys the ternary symbol O.
CS1 is a waveform which conveys the ternary symbol 1.
CS -1 is a waveform which conveys the ternary symbol -1.
7-56
diEt?
PRELIMINARY
, CYPRESS=========~~~
CY7C971
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
TTL Pins
VOHT
Output HIGH Voltage
Vee = Min., IOH = -4.0 rnA
VOLT
Output LOW Voltage
Vee = Min., IOL = 4.0 rnA
VIHT
Input HIGH Voltage
VILT
Input LOW Voltage
IlXT
Input Load Current
IOZT
lOST
2.4
V
0.4
V
2.0
6.0
V
-3.0
0.8
V
GND~VI~VCC
-10
+10
Output Leakage Current
GND ~ Vo ~ Vee, Output Disabled
-50
+50
!!A
!!A
Output Short Circuit Current[12j
Vee = Max., VOUT = GND
-350
rnA
Vee = Min., IOL = 12.0 rnA
0.4
V
Open Drain LED Pins
Output LOW Voltage
VOLD
Miscellaneous
IcC!
Vee Operating Supply Current
Vee = Max., lOUT = 0 rnA,
100BASE-T4 transmitting
300
rnA
lee2
Vee Operating Supply Current
Vee = Max., lOUT = 0 rnA,
100BASE-T4 not transmitting
100
rnA
ISB
Power-Down Current
Max. Vee
TBD
rnA
Capacitance[13j
Parameter
Description
CIN
Input Capacitance
CoUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
Unit
5
pF
8
pF
AC Test Loads and Waveforms
4810
481Q
OUTP~~ ~
i
,~~~:F1
INCLUDING
JIG AND
SCOPE
-
OUTP~~ ~
_
-
i
.~ ••~:F1
1255Q
INCLUDING
JIG AND
SCOPE
-
90%
_
1255Q
7C971-9
THEVENIN EQUIVALENT
OUTPUT~
GND
-
(b)
(a)
Equivalent to:
ALL INPUT PULSES
3.0V---
1.73V
Notes:
12. Thsted one output at a time, output shorted for less than one second,
less than 10% duty cycle.
13. Thsted initially and after any design or process changes that may affect
these parameters.
7-58
70971-10
PRELIMINARY
CY7C971
Switching Characteristics Over the Operating Range (continued)
Parameter
Description
Min.
Max.
Unit
lOBASE·T CRS and COL
tCRSH3 LL5j
CRS Assert Latency
CRS Deassert Latency
tCRSL3 Lk4j
Management Timing
tMCPWH
MDC Pulse Width HIGH
25
tMCPWL
MDC Pulse Width LOW
25
fM
MDC Frequency
tMDS
MDIOSet·Up
10
tMDH
MDIOHold
0
tMDO
MDIO Valid from Clock
tMDOH
MDIO Hold froin Clock
tMDHZ
MDC to High Impedance
ns
500
ns
ns
ns
12.5
ns
0
Reset Pulse Width LOW
40
ns
20
ns
5
!-IS
ns
100
tTPMA
PMA Tl"ansmit Latency
tIDS
PMA Tl"ansmit Data Set Up
10
tIDH
PMA Transmit Data Hold
0
tpMACRSH
PMA CRS Assert Latency
110
tpMACRSL
ns
ns
0
Control Input Set-Up
tRS
PMA Interface Timing
MHz
ns
40
MDC to Low Impedance
tMDLZ
Control and Status Timing
tRL
500
40
ns
ns
ns
140
ns
PMA CRS Deassert Latency
650
ns
tpMADATA
Clock Timing
PMA Receiver Data Latency
800
ns
tcpWH
Reference Clock Pulse Width HIGH
16
24
ns
tCPWL
Reference Clock Pulse Width LOW
16
24
fc
Reference Clock Frequency
25 -100ppm
Notes:
23. tCRSH3 is measured from the rising edge 'of the signal on RX_D2 that
meets the lOBASE-T carrier criterion to the rising edge of CRS.
24. tCRSL3 is measured from th eend of the last data symbol on RX_D2 to
the falling edge of CRS.
7-60
25
+ 100 ppm
ns
MHz
*iz~YPRESS~~~~~P;~=L=IM~IN.=~=R=Y~~~~=CY~7C=9=71=
Switching Waveforms (continued)
Mil Receive Port Three State Timing
RHZD
I
I
RV_DVVALID
\\\\
RXD[3:0]
(05-00)
I
"
I
I
DATA VALID
"
""
\
JIll
I
"""
I I
I
70971·13
MIl Carrier Sense and Collision (lOOBASE·T4)
EOC, EOP
14----
tcRSLC1,
tCRSLP1
CRS
TX_ClK
COL
tcOLL1
7C971·14
7-62
hrc
PRELIMINARY
CY7C971
~ ·CYPRESS==========~~
Switching Waveforms (continued)
MIl Carrier Sense and Collision (lOBASE-T) [29]
CRS
_3
1cRSH3
RX_D1±
------_
.......
\XXXXXI
COL
7C971·17
MIl Management Port
MOC
MOIO
7C971-18
Control and Status Pins
AUTONEG
ENT4
ENT
ENTFO
ISOOEF
IRS
7C971·19
Notes:
29. Switching waveforms show CRS and COL timing for a collision that is
started and terminiated by activity on the receive path.
7-64
ADVANCED INFORMATION
CY7B972
lOOBASE-TX/lOBASE-T
Fast Ethernet Transceiver
Features
• Complies with IEEE 802.3u standard
• Four Operating Modes:
-lOOBASE·TX
-lOOBASE·TX Full Duplex
-lOBASE-T
-lOBASE-T Full Duplex
• Media Independent Interface (MIl)
-Three-state receive port
-Serial management port
• Auto-Negotiation
• MLT-3 Transmitter/Receiver for
100BASE-TX
• Cat. 5 twisted-pair adaptive equalizer
for 100BASE-TX
• PMA interface for repeater
applications
• LED status indicators: TX, RX, Link
• Loopback mode for PHY integrity
testing
• 80-pin PQFP
Functional Description
The CY7B972 is a full featured physical
layer transceiver (PHY) device supporting
both 100BASE-TX (Fast Ethernet) and
10BASE-T Local Area Network (LAN)
standards. The CY7B972 complies with
IEEE 802.3 100BASE-TX, lOBASE-T,
Auto-Negotiation and MIl standards.
The CY7B972 interfaces to two pair of
category 5 unshielded twisted-pair cable
or fiber. The Media Independent Interface (MIl) attaches directly to 802.3 Media Access Control (MAC) layer devices.
The CY7B972 performs the Physical
Coding Sublayer (PCS), Physical Media
Attachment (PMA), Physical Layer Sig-
Control and Status
PCS
TX/RX
nalling (PLS), and Media Attachment
Unit (MAU) functions defined in the
802.3 standard for lOOBASE-X and
10BASE-T. Ethernet frames are transferred from the MAC to the CY7B972
over the MIl interface. The data is encoded in the PCS or PLS encoder (4B5B
for 100BASE-TX or Manchester for
lOBASE-T) and then passed to the PMA
or MAU where the serial encoded data is
shifted bitwise on to the twisted pair
media. Collision and Carrier Detect signals are generated by the CY7B972 and
passed to the MAC over the MIL
The CY7B972 PHY uses 802.3 standard
Auto-Negotiation to configure the
twisted-pair link. The CY7B972 also includes a direct interface to the PMA layer
for repeater applications.
Address
1 00 mloO\>::)I:.-f)( ~:x
(4B5B)
Collision
Detect
Carrier
Sense
Clock
Recovery
PLS
Auto
Negotiation
-
Q
:E
MAU
TX/RX
TX/RX
(Manchester)
Clock
LED Drivers
Document #: 38-00453
7-66
789721
at
:z
PRELIMINARY
F;CYPRESS
CY7B8392
Pin Description
Pin Number
16·PinDiP
28·PinPLCC
Pin Name
Description
1
2
2
3
CD+
CD-
AUI Collision Output pins. Differential driver that transmit a 10-MHz
signal during collisIOn events, jabber and CD Heartbeat conditions. Also
referred to as CI port.
3
6
4
12
RX+
RX-
AUI Receive Outpul};ns. Differential driver that outputs the signal receive from the line.
0 referred to as D I port.
7
8
13
14
TX+
TX-
AUI Transmit Input pins. Differential receiver that inputs the signal for
transmission onto the cable.
9
15
HBE
Heartbeat Enable Pin. When this pin is grounded, the heartbeat is enabled. When the pin is connected to VEE, the heartbeat is disabled.
11
12
18
19
RR+
RR-
External Resistor. A 1K 1% resistor should be connected between these
pins to establish proper internal operation current.
14
26
RXI
Receive Input. This pin is connected directly to the coaxial cable.
15
28
TXO
1tansmitter Output. This pin is connected directly (10BASE2 thin wire)
or through a diode to the coaxial cable.
16
1
CDS
Collision Detect Sense. Ground sense connection for the collision detect
circuit. This pin should be connected separately to the shield to prevent
ground drops from altering the receive mode collision detect threshold.
10
16,17
GND
Positive Power Supply Pin.
4,5,13
5-11
20-25
VEE
Negative Power Supply Pin.
CY7B8392 Description
Transmitter
The CY7B8392 transfers Manchester-encoded data from the
AUI port of the DTE (TX + and TX - ) to the coaxial cable. The
output waveform is wave shaped to meet IEEE 802.3 specifications. For Ethernet compatible applications (lOBASE5), an external isolation diode may be added to further reduce the coax
load capacitance.
The AUI squelch circuit prevents signals with less than 15 ns
pulse width or smaller than 175 m V average dc level from reaching the output driver. The squelch Circuit also turns the transmitter off at the end of the packet if the average of the dc level of the
signal stays greater than 175 m V for more than 190 ns.
Receiver
The CY7B8392 receiver transfers the serial data from the coaxial
cable to the DTE via the balanced differential output (RX + and
RX -). The received signal is amplified and equalized by the on
chip equalizer.
The device also contains an internal squelch function that discriminates noise from valid data. A 4-pole Bessel filter is used to
extract the DC level of the received signal. If the DC level of the
received signal is lower than an internally set squelch threshold,
the CY7B8392 receive function will not be activated.
Collision Detection
The collision detection circuit monitors the signal level on the
coax cable. This signal voltage level is compared against the collision voltage threshold V CD. When the measured signal level is
Note:
1. BT = Bit Time = 100 ns.
more negative than V CD, a collision condition is declared by the
CY7B8392 by sending a lO-MHz signal over the CD+/CDpair.
Long Cable Application
The IEJ;E 802.3 standard is designed for 500 meters of Ethernet
cable and 185 meters of thin coax cable (RG58A/U). Th extend
the cable segment to 1000 meters and 300 meters of Ethernet
cable and thin coaxial cable respectively, transmit collision detection mode is required. The disadvantage of the transmit collision
detection mode is that it will detect collision only when the station is transmitting; it will not be able to detect collision of two
far-end stations when it is not transmitting. Note that transmit
mode collision detection is not allowed in repeater applications.
Implementation of transmit mode collision detection with
CY7B8392 is simple. By connecting an external resistor divider
to the CDS pin; R1 to 150 ohms and R2 to 10 Kohms, the device
is now in transmit collision detection mode.
The CY7B8392 utilizes a combination receive and transmit mode
collision detection. When the device is idle it enters into receive
collision detection mode, and when it is transmitting it is in the
transmit collision detection mode.
Heartbeat Thst Function
The Heartbeat Test Function is enabled when the HBE pin is tied
to ground. When enabled, a lO-MHz collision signal is transmitted to the MAC over the CD+/CD- pair after the transmission of a packet for 1O±5BT[11. The Heartbeat function
should be disabled by tying the HBE pin to VEE for repeater
applications.
7-68
PRELIMINARY
CY7B8392
Electrical Characteristics Over the Operating RangdS]
Parameter
Description
VEE
SlIpply Voltage
IEEI
(VEE to 9ND) Non-transmitting
Min.
'!Yp.
Max.
-8.55
-9.0
-9.45
V
-25
-35
mA
-70
-80
mA
IEE2
(VIlE to GND) TIansmitting
IRXI
InplIt Bias Cmrent (RXI pin)
-2
ITDC
TIansmitter OlItPlIt DC Cmrent
37
ITAC
Transmitter AC Cmrent
VCD
Collision Threshold
Vcs
RX,C,D
Unit
25
iJA
41
45
mA
-1.45
-1.53
-1.62
Carrier Sense Threshold
-0.38
-0.45
-0.52
V
Differential OlItPlIt Voltage
±500
±1500
mV
±28
mA
-1
V
-3
V
-300
mV
Voc
Common Mode Voltage[6]
VTS
TIansmitter Squelch Threshold[7]
RRXI
Shunt Resistance-Non-transmitting
100
KQ
TTXO
Shunt Resistance-Transmitting
10
KQ
-175
-225
Capacitance
Parameter
Test Conditions
Descriptioh
'!Yp.
Unit
1.5
pF
InjJut Capacitance
Cx
AC Test Loads and Waveforms
39Q
TXO
TRANSMITTER - - - : }
OUTPUT
25Q
RECEIVER (RX±) - - -.......--:t--'VI......,
COLLISION OUTPUT (CD±)
(a)
(b)
Notes:
5. Thsting is done under test load as defined in AC Test Loads and
Waveforms.
6.
7.
--.--t--.......-'VI,..,....
During idle, Voc is pUlled down to VEE to minimize the power dissipation across the load resistors connected to RX ± and CD ±.
For a minimum pulse width of >40 ns.
7-70
8392-5
=:.
PRELIMINARY
rcYPRESS
CY7B8392
Switching Waveforms (continued)
Transmit Timing
TX+
TX1 4 - - - - tTOFF
-----ij.
r-----~,~<----~4_-----
TXO
OUTPUT
8392-7
Heartbeat Timing
TX+
TX-
lJ1JU
\~-------------------------------14-------
fool-a-----tHON
co+
CO-
8392-8
Collision Timing
OV
INPUT
VCO (min) ~
TORXI -1.75V--~----~"---------'-IL-- -6.BV
~
--I 1-- tcp
-1.2V
_I
r-- tcOFF - - - - ,
r-----~
CO+
CO-
8392-9
Jabber Timing
TX+
TXTXO
CO+
CO-
----------------«X>1>>----8392_'O
Ordering Information
Ordering Code
Package
Name
Package 1YPe
CY7B8392-JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7B8392-PC
PI
I6-Lead (300-MiI) Molded DIP
Document #: 38-00430
7-72
Operating
Range
Commercial
PRELIMINARY
CY9266-T
CY9266-C
CY9266-F
Functional Description
lYPical Applications for the Evaluation Board include:
The HOTLink Evaluation Board (CY9266) is a system development tool that facilitates the design and evaluation of the Cypress
HOTLink transmitter (CY7B923) and receiver (CY7B933) de:
vices. The CY9266 Evaluation Board is offered with three serial
media interface options:CY9266-C (copper), CY9266-F
(fiber), and CY9266-T (twisted pair). The CY9266-C offers a
low cost 1/4" coaxial connection, the CY9266- F interfaces with a
longwave (1300 nm) LED optical transceiver and SC fiberoptics
connector, and the CY9266-T is configured to support shielded
twisted pair or twin axial cable that attaches through a 9-pin D-sub
connector.
The CY9266 accepts data and control commands from the host via
the parallel interface ports (available in three connectors). The
48-pin header connector allows interoperability with the IBM
OLC-266 interface. The two 60-pin connectors are functionally
equivalent. The vertical pin connector is used for probing and
monitoring the appropriate signals, while the edge connector can
be connected to a flat ribbon cable as a direct host communication
interface.
In a typical point-to-point link, the host downloads parallel data to
the CY9266 Evaluation Board. Parallel data can be formatted as
pre-encoded lO-bit patterns or 8-bit data/special characters to be
encoded by the HOTLink transmitter. The data is then encoded
(optionally) and serialized by CY7B923 HOTLink 1tansmitter.
Serial data is then transmitted via coax, twisted pair, or fiber.
In the receive operation, serial data is sent from a remote source
(via copper/fiber/twisted pair) and transferred to the CY7B933
HOTLink receiver. The serialized data is converted to parallel and
then optionally decoded. Parallel data is transferred to the host
system along with various status and synchronizing signals. All I/O
operations are performed between the host and the Evaluation
Board using simple handshakes.
The CY9266 Evaluation Board can also operate in self-diagnostic
mode and indicate errors in the serial transmission stream using a
built-in two-digit, seven-segment LED display.
•
•
•
•
•
•
•
•
•
HOTLink system development
Thlecommunication
Remote data acquisition
Processor-to-disk/peripheral communication
Backplane extender
Point-to-point video/image communications
Point-to-point CPU/server communications
High-speed data switching (TI Multiplier, etc.)
Similar in function to IBM OLC-266 (single channel) and
HP HOLC-0266™
Specification
Board Dimensions
1Wo media types:
CY9266-C
CY9266-F
CY9266-T
Power Supply
Maximum Clock Rate
Maximum Data Rate
Parallel I/O
Serial I/O
3.0" X 4.0" (approx., plus media connector)
Coax connectors--BNC for transmit,
TNC for receive
Fiber optic module, single row or 4 row
modules
1Wisted pair connector, 9-pin D-sub
+5V± 5%
33 MHz
330 Mbps
TTL
Coax or twisted pair (CY9266-ClT) or
Fiber optic with SC connector
(CY9266-F)
Ordering Information
Ordering (::ode
CY9266-C
CY9266-F
Fiber
CY9266-T
1Wisted Pair
CY9266-FX
Fiber w/o optic
module
Document #: 38-00236-A
HOTLink is a trademark of Cypress Semiconductor Corporation.
ESCON is a registered trademark of International Business Machines Corporation.
IBM OLC-266 is a trademark of International Business Machines Corporation.
HP HOLC-0266 is a trademark of Hewlett-Packard Corporation.
7-74
Media 1Ype
Copper
g
--?cYPRESS
Bus Interface Products
Device
VIC64
VIC068A
VAC068A
CY7C960
CY7C961
CY7C964
Section Contents
Page Number
Description
VMEbus Interface Controller with D64 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-1
VMEbus Interface Controller ................................................... 8-7
VMEbus Address Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-16
Slave VMEbus Interface Controller Family ....................................... 8-22
Slave VMEbus Interface Controller Family ....................................... 8-22
Bus Interface Logic Circuit .................................................... 8-27
VIC64
Pin Configurations
Pin Grid Array (PGA)
Bottom View
B
c
D
E
F
GND
IP1.2*
LIACKO*
LIRQ2*
UAQS"
AS!Z1
ASIZll
l.D6
BlP
IPL1*
VCC
URal·
LlR04*
LlRQ6*
ICFSEL*
MWS"
LD2
LOS
OEDLK*
IPLQ*
LAEN
LlR03*
URQ7*
GND
SLSELO*
LD1
L03
LD7
LOCATOA
PIN
LA7
LDO
LD4
lA3
LAS
LAS
IACKlN*
lACK"
AMO
LA2
lA4
GND
GND
AS"
AM1
LA1
LAO
VCC
GND
AM2
AM3
8
CS"
DSACK1*
OS'
VCC
LWORD*
AM4
9
PAS·
LBERR*
RESET"
BERR*
WRITE·
AMS
10
DSACKO"
A/W'
FC1
BR2"
051*
DSO"
11
HALT*
AMC"
LSR·
BBSY*
BR1*
BRO·
12
Ft:2
SIZO
SCON*/D6
BGINO*
BR3·
GND
13
SIZ1
IAESET*
LBG"
ABEN*
A
G
H
SLSEL1*
J
WORD*
L
M
N
p
AO"
A04
vee
OND
IRQ4"
A01
A03
A05
A07
lAOS·
IRQ7*
2
GND
A06
IRQ1*
IRQ2*
IR06·
ACFAlL*
3
lAOS"
VCC
IACKOUT*
4
K
FCIACK*
R
SYSFAIL* SVSAESET' CTACK·
5
6
7
CLK64M
LADI
GND
VCC
GND
vee
DOD
lADO
lEDI
DDIA
LWDENIN
DENO·
006
003
001
GND
BGOurO·
BGIN3*
BGIN1*
BCLR*
14
VCC
LEDO
UWDENIN
SWDEN'"
ISOBE·
007
DOS
004
002
BGOUT3·
BGOUT2'" SYSCLK
GND
15
BGOUT1* BGIN2*
VIC64-1
8-2
'~YPRESS
VIC64
Pin Configurations (continued)
144·Pin Thin Quad Flatpack (TQFP)
Top View
IPLQ*
IPL1*
IPl2*
VCC
LAEN
LIAKO*
LBG"
107
106
105
104
103
102
101
100
99
96
97
96
95
94
93
92
91
90
89
URQ1*
LlRQ2*
LlRQ3*
LlRQ4"
URQ5*
URQ6*
LlR07*
ASIZ1*
ASIZO*
ICFSEL*
9
10
11
12
13
,.
IRQ3*
15
16
17
16
19
20
21
22
23
2.
25
26
27
26
29
30
31
32
33
3.
$
IRQ4*
~
SLSEL1*
GND
SLSELO*
WORD*
FCIACK*
MWB"
A1
GND
A2.
A3
A4
vee
A5
AB
A7
GND
IRQ1*
IR02*
B8
87
86
85
84
63
B2
81
80
79
76
77
76
75
M
n
IRESET'
SCON*/D64
Cl.K64M
ABEN*
LADO
LADI
LEDI
vee
LEDO
DDIR
UWOENIN*
GND
LWOENIN*
DENO·
SWOEN*
ISOBE*
VCC
GND
D07
D06
D05
D04
VCC
D03
D02
D01
DOD
BGOUT3"
GND
BGOUT211'
BGOUT1*
BGOUTO*
SYSCLK
BGIN3*
BGIN2*
~~~~~~~~~~~~~~~~~~~~~fflfflg~~~~$$~mm~~~
VIC64-3
8-4
~~
VIC64··
.'CYPRESS
VIC64 Slave Block 1ransfer
The VIC64 is capable of decoding the address modifier codes to
determine that a slave block transfer is desired. In this mode, the
VIC64 captures the VMEbus address, and latches it into internal
counters. For subsequent cycles, the VIC64 simply increments this
counter for each transfer. The local protocol for slave block transfers can be configured in a full handshake mode by toggling both
PAS" and DS' and expecting DSACKi* to toggle, or in an acceleratedmode in which only DS" toggles andPAS* is asserted throughout the cycle.
For D64 slave block transfers, the SCaN" /D64 signal is asserted to
indicate a D64 transfer is in progress. External logic is required to
de-multiplex the data from the VMEbus address bus for the upper
24 address/data lines. The lower 8 bits are done within the VIC64.
Module-Based DMA 1ransfers
The VIC64 can act as a DMA controller between two local resources. This mode is similar to that of master block transfers with
local DMA, with the exception that the VMEbus is not the source
or destination.
VIC64 Interrupt Generation and Handling Facilities
The VIC64 can generate and hanrlIe a seven-level prioritized interrupt scheme similar to that used by the Motorola 68K processors.
These interrupts include:
• 7 VMEbus interrupts
• 7 local interrupts
• 5 VIC64 error/status interrupts
• 8 interprocessor communication interrupts.
The VIC64 can be configured to act as handler for any of the seven
VMEbus interrupts. The VIC64 can generate the seven VMEbus
interrupts as well as supplying a user-defined status/lD vector. The
local priority level (IPL) for VMEbus interrupts is programmable.
When configured as the system controller, the VIC64 drives the
lACK' daisy chain.
The VIC64 is also capable of generating local interrupts on certain
error or status conditions. These include:
• ACFAIL" asserted
• SYSFAIL' asserted
• Failed master write-post (BERR' asserted)
• Local DMA completion for block transfers
• Arbitration timeout
• VMEbus interrupter interrupt
The VIC64 can also interrupt on the setting of a module or global
switch in the interprocessor communication facilities.
Interprocessor Communication Facilities
The VIC64 includes interprocessor registers and switches that can
be written and read through VMEbus accesses. These are the only
such registers that are directly accessible from the VMEbus.
Included in the interprocessor communication facilities are:
• Four general-purpose 8-bit registers
• Four module switches
• Four global switches
• VIC64 version/revision register (read-only)
• VIC64 reset/halt condition (read-only)
• VIC64 interprocessor communication register semaphores
When set through a VMEbus access, these switches can interrupt a
local resource. The VIC64 includes module switches that are intended for a single module, and global switches which are intended
to be used as a broadcast.
Operating Range
Range
Commercial
The local interrupts can be configured with the following:
•
•
•
•
User-defined local interrupt priority level (IPL)
Option for VI C64 to provide the status/ID vector
Edge or level sensitivity
Polarity (rising/falling edge, active HIGH/LOW)
Ambient
Temperature
Vee
O°C to +70°C
5V±5%
Industrial
-40°C to +85°C
5V ± 10%
Military
-55°C to + 125°C
5V ± 10%
Related Documents
VIC64/CY7C964 Design Notes
VIC068A/VAC068A User's Guide
Ordering Information
Ordering Code
Package
Name
Package 1Ype
Operating
Range
VIC64-AC
A144
144-Lead Thin Quad F1atpack
VIC64-BC
B144
145-Pin Plastic Pin Grid Array
VIC64-GC
VIC64-NC
0145
N160
145-Pin Ceramic Pin Grid Array
160-Lead Plastic Quad Flatpack
VIC64-GI
VIC64-GM
G145
0145
145-Pin Pin Grid Array
Industrial
145-Pin Ceramic Pin Grid Array
Military Thmp. Commercial
VIC64-GM13
0145
145-Pin Ceramic Pin Grid Array
MIL-STD-883
VIC64-UMB
Ul62
160-Lead Ceramic Quad F1atpack
MIL-STD-883
VIC64-UM
Ul62
160-Lead Ceramic Quad F1atpack
Military Thmp. Commercial
Document #: 38-00196-B
8-6
Commercial
=:;!iF
_?cYPRESS
============;;;;;;;VI;;;;;;;C~06;;8A~
Pin Configurations
Pin Grid Array (PGA)
Bottom View
A
B
c
o
E
F
G
H
J
K
L
M
N
p
R
GNO
IPl2"
LlACKO""
URQ2*
URQ5*
ASlZl
ASIZO
SLSEL1*
WORD*
FlACK""
AlJ2
A04
VCC
GNO
IRQ4"
L06
BlT"
IPl1*
VCC
LlRQ1*
LlRQ4*
URQa*
ICFSEL*
MWB*
AlJl
AlJ3
AlJ5
A07
IRoa""
IRQ7t
2
l02
l05
DEDLK*
IPLO*
LAEN
URQ3""
LlRQ7*
GNO
SLSELO*
GNO
AlJ6
IRQ1*
IRQ2*
IROG'"
ACFAlL*
3
LOl
l03
l07
LOCATOR
PIN
IRQ5*
VCC
IACKOUT"
4
LA7
lOO
lD4
LA3
lA5
lAS
IACKIN*
IACK*
AMO
LA2
lA4
GNO
GNO
AS"
AMl
LAl
LAO
VCC
GNO
AM2
AM3
8
CS"
DSACK1*
OS"
VCC
LWORD*
AM4
9
PAS*
LBERR""
RESET'"
BERR""
WRITE*
AM5
10
DSACKO*
R/W"
FCl
BR2*
OSl"
OSO'"
11
HAlT*
RMe*
LBR"
BBSY*
BR1*
BRO·
12
FC2
SIZO
SCON""
ClK64M
SIZl
IRESET"
LADD
LEDI
LBG"
ABEN*
VCC
lEOO
SYSFAIL* ~YSRESET
LAOI
GNO
VCC
GNO
OOIR
LWOENIN*
DENO·
006
UWOENIN
SWOEN*
ISOBE*
007
VCC
003
005
DTACK*
5
6
7
BGOUT1*
BGIN2*
BGINO*
BR3*
GNO
13
001
GNO
BGOUTO·
BGIN3*
BGIN1*
BeLA'"
14
004
002
BGOUT3*
BGOUT2*
SYSClK
GNO
15
000
VIC068A-l
8-8
'iEYPRESS
VIC068A
Pin Configurations (continued)
144-Pin Thin Quad Flatpack (TQFP)
Top View
LBG'
IPLO*
IPL1*
IPL2*
IRESET"
SOON'll
vee
CLK64M
LAEN
ABEN*
UA~O:ill
LADO
LAOI
LEOI
URal'll
URQ2*
LIRQ3*
URQ4*
UAC5'"
URca'"
URQ7*
ASIZ1*
ASIZD*
ICFSEL*
SLSEL1*
GNO
SLSELO'"
WORD'"
FCIACK*
MWB'
A1
GNO
f.2
A'
vee
AS
A6
A7
vce
9
10
11
12
13
LEOO
OOIR
UWDENIN""
GNO
LWDENIN*
bEND'
l'
15
16
17
18
19
20
21
22
SWDEN'"
ISOBE*
vec
GNO
007
006
005
b04
vce
23
2'
25
003
28
002
b01
27
28
000
29
BGOUT3'
GNO
GNO
30
31
32
IRQ1*
33
IRQ2'11t
34
IRQ3'
IRQ4*
~
BG0UT2*
BGOUT1*
BGOUTO""
N
n
~
SVSCLK
BGIN3*
BGIN2*
~~~~;~~~~~~~~~~m~~mm~mm2w~~~m$~mmR~~
Vle068A-3
8-10
'iP~YPRESS============================~TI~C;O~68~A
Theory of Operation
The VIC068A is an interface between a local CPU bus and the
VMEbus. The local bus interface of the VIC068AemuIates Motorola's family of 32-bit CISC processor interfaces. Other processors
can easily be adapted to interface to the VlC068A using the appropriate logic.
Resetting the VIC068A
The VIC068A can be reset by any of three distinct reset conditions:
Internal Reset. This reset is the most common means of resetting
the VI C068A.1t resets select registervalues and all logic within the
device.
System Reset. This reset provides a means of resetting the
VIC068A through the VMEbus backplane. The VlC068A may
also signal a SYSRESET' by writing a configuration register.
Global Reset. This provides a complete reset of the VIC068A. This
reset resets all ofthe VIC068~s configuration registers. This reset
should be used with caution since SYSCLK is not driven while a
global reset is in progress.
All three reset options are implemented in a different manner and
have different effects on the VIC068A configuration registers.
VIC068A VMEbus System Controller
The VIC068A is capable of operating as the VMEbus system controller. It provides VMEbus arbitration functions, including:
• Priority, round-robin, and single-level arbitration schemes
• Driving lACK" Daisy-Chain
• Driving BGiOUT' Daisy-Chain (All four levels)
• Driving SYSCLK output
• VMEbus arbitration timeout timer
The System controller functions are enabled by the SCON' pin of
the VIC068A. When strapped LOW, the VIC068A functions as the
VMEbus system controller.
VIC068A VMEbus Master Cycles
The VIC068A is capable of becoming the VMEbus master in response to a request from local resources. In this situation, the local
resource requests that a VMEbus transfer is desired. The
VIC068A makes a request for the VMEbus. When the VMEbus is
granted to the VIC068A, it then performs the transfer and acknowledges the local resource and the cycle is complete. The
VIC068A is capable of all four VMEbus request levels. The following release modes are supported:
• Release on request (ROR)
• Release when done (RWD)
• Release on clear (ROC)
• Release under RMC' control
• Bus capture and hold (BCAP)
The VIC068A supportsA32, A24, andAl6, aswell as user-defined
address spaces.
Master Write-Posting
The VlC068A is capable of performing master write-posting (bus
decoupling). In this situation, the VIC068A acknowledges the local resource immediately after the request to the VIC068A is
made, thus freeing the local bus. The VIC068A latches the local
data to be written and performs the VMEbus transfer without the
local resource having to wait for VMEbus arbitration.
Indivisible Cycles
Read-modify-write cycles and indivisible multiple-address cycles
(IMACs) are easily performed using the VIC068A. Significant
control is allowed to:
• Requesting the VMEbus on the assertion of RMC" independent of MWB' (this prevents any slave access from interrupting local indivisable cycles)
• Stretching the VMEbus AS*
• Making the above behaviors dependent on the local SIZi signals
Deadlock Condition
If a master operation is attempted when a slave operation to the
same module is in progress, a deadlock condition has occurred.
The VlC068A will signal a deadlock condition by asserting the
DEDLK* signal. This should be used by the local resource requesting the VMEbus to try the transfer after the slave access has
completed.
Self-Access Condition
If the VlC068A, while it is VMEbus master, has a slave select signaled, a self access is said to have occurred. The VIC068A will issue
a BERR', which in turn will cause a LBERR' to be asserted.
VIC068A VMEbus Slave Cycles
The VIC068A is capable of operating as a VMEbus slave controller. The VlC068Acontains a highly programmable environment to
allow for a wide variety of slave configurations. The VlC068A
allows for:
• D32, D16, or D8 configuration
• A32, A24, A16, or user-defined address spaces
• Programmable block transfer support including:
-DMA-type block transfer (PAS' and DSACKi* held
asserted)
-non-DMA-type block transfer (toggle PAS' and
DSACKi*)
- No support for block transfer
• Programmable data acquisition delays
• Programmable PAS' and DS* timing
• Restricted slave accesses (supervisory accesses only)
When a slave access is required, the VlC068A will request the local
bus. When local bus mastership is obtained, the VlC068A will read
or write the data to/from the local resource and assert the
DTACK' signal to complete the transfer.
Slave Write-Posting
The VIC068A is capable of performing a slave write-post operation (bus decoupling). When enabled, the VIC068A latches the
data to be written and acknowledge the VMEbus (asserts
DTACK*) immediately thereafter. This prevents the VMEbus
from having to wait for local bus access.
Address Modifier (AM) Codes
The VlC068Aencodesanddecodes the VMEbusaddress modifier
codes. For VMEbus master accesses, the VIC068A encodes the
appropriate AM codes through the VIC068A FCi and ASIZi signals, as well as the block transfer status. For slave accesses, the
VIC068A decodes the AM codes and checks the slave select control registers to see if the slave request is to be supported with regard to address spaces, supervisory accesses, and block transfers.
The VIC068A also supports user-defined AM codes; that is, the
8-12
L,~
~7 CYPRESS ==============~VI~C;;;;;O;;;;68~A
Buffer Control Signal for Shared Memory Implementation!l]
"'IO.....I--ABEN'
L.::=::j~=;-lADO
D32CPU
D16
SHARED
MEMORY
D32SHARED
MEMORY
SWDEN*
OOIR
LEOI
LDO- LD15
VMEbus
08-015
ISOBE*
o
LOO - L07
VMEbus
VIC
LAO - LA7
DSACK1*
DSACKO* LWORD* - - .
S1Z1
OSO* ~
81ZO
WORD'"
Note:
1. This configuration can support Slave Block 'fransfers and Master and
Slave Write-Post Operation_ This buffer configuration cannot support
block transfers with DMA.
8-14
Doo - 007
VMEbus A01 - A07
081* - - -
VAC068A
VMEbus Address Controller
Features
• Dual UART channels on board
- Double-buffered on transmit,
• Optional companion part to VIC068A
quint-buffered on receive
• Implements master/slave VMEbus
- Baud rate programmable
interface in conjunction with the
• Miscellaneous features
VIC068A
- Pin grid array or quad tlatpack
• Complete VMEbus and I/O DMA
packages
capability for a 32-bit CPU
- Supports unaligned transfers
• Complete local and VMEbus memory
- Programmable DSACKi for local
map decoding
I/O
- Separate segments on local side
available for DRAM, VME subsys- Programmable timer and interrupt
tem bus (VSB), shared resources,
controller
VMEbus, local I/O, and EPROM
- Programmable I/O (PIO)
- Separate segments for the VMEbus • See the VIC068A/VAC068A User's
address decode for slave select 0,
Guide for more information
slave select 1, and interprocessor
communication facilities
Functional Description
- 64-Kbyte resolution for both local
The VMEbus address controller
and VMEbus memory maps
(VAC068A) is a programmable memory
• Supports block transfers over 256
map address controller. In conjunction
byte boundaries
with the VIC068A (VMEbus interlace con- Address counters for both VMEbus troller), the VAC068A maximizes the
A(31-8) and local LA(31-8)
VMEbus interface performance of a master/
.slave module.
- Supports dual-path mode
- Supports implementation ofVSB
interface with DMA capability
The VAC068A contains programmable
registers to allow the user to easily define
memory maps for both the local and VMEbus address regions. The VAC068A also
contains the address counters and handshaking signals to allow easy implementation of block-level transfers over 256-byte
boundaries. Additional features include
dual internal UART channels, redirection
control on the local bus to VSB (VMEsubsystem bus) or shared resource area, data
swapping for unaligned transfers, programmableDSACKi,programmabletimer
and interrupt controller.
The VAC068A connects directly to the
local bus and the VIC068A. VMEbus
address lines A8 through A31 are driven
directly. The VAC068A output drivers
feature patented high-drive outputs and
TTL-compatible inputs.
The VAC068A is available in pin grid array
(with 122 active signals, 22 power and
ground pins, and 1 locator pin) and quad
fiatpack.
Sample Board Design
VACOS8-'
8-16
Oi~YPRESS
VAC068A
Pin Configurations
Pin Grid Array (PGA)
Bottom View
A
B
c
o
E
F
A23
PI0131
IOSEL2*
DDIR
PIOll
LADI
BLT*
A20
A22
SWOEN*'
VAS'
ABEN*
A17
A19
A21
LAOO
LDMACK*
A16
AlB
GND
LOCATOR
PIN
A14
A15
VCC
VCC
A12
A13
GNO
Al0
All
A06
A09
G
H
REFGT*
ICFSEL*
lORD'"
VSBSEl*
SLSELO*
GNO
LBR'
VCC
PI041
J
SLSEL1*
1010
K
L
p
M
lOB
1011
1013
1014
ASIZO
109
1012
WORD'"
FCIACK*
FCO
GNO
1015
ASIZl
CPUCLK
LAEN
R
FCl
PAS'
2
DSACK1*
3
lO19
4
OSACKO'
L021
5
GNO
L016
lO17
6
VCC
LD23
L016
lO20
GNO
lO24
lO22
L025
8
GNO
FC2
RJW'
7
A25
A24
vce
GNO
LD27
L026
9
A27
A26
GNO
vee
L029
LD2B
10
A29
A26
PIOOI
TXOA
DRAMes
LD31
LD30
11
A31
PIOll
RXOA
GNO
EPROMeS
MW8*
12
A30
PI03/
AXOB
PIC7
PI08i
IOSEU'"
GNO
lA29
GNO
vee
PI06/
IOSE13*
PI010
es'
lA31
lA26
lA24
lA22
lA30
PIOl2/
SHACS·
lA2B
lA27
lA25
lA23
PI02/
TXOB
vee
PIOSI
IOSELS'"
PI051
IOWR'"
vee
IOSEl1*
lA21
LA13
lAS
LAll
CACHINHfI
FPUCS*
13
LA17
LA15
LA14
LA12
lAB
RESET'"
14
LA19
lA20
LA18
LA16
LAl0
IOSELO*
15
GNO
VAC068-3
8-18
4Ii~YPRESS~~~~~~~~~~~~~~=v.=~=C=O=68~A
VIC068A1VAC068A on 68030 Board
512j256KX 36 DRAM
r
v
{32
512j256KX36 DRAM
Address
Mux
{'32
Latching Transceivers
Latching Transceivers
II~_C_I
r-r--
Logic
68030
r--
4 JEOEC EPROMS
'---
LAO- LA31
r-FCT
543
=:J
024-031
=:J
0 16-023
'--
r-FCT
543
FCT
245
'--
r
MW8*
WORD""
JtOBE'
--
FCT f0245
r---
VAC068
l
I
Map Decoder
~ ~
DRAM
1/0
I
II
VMLE!aM
Serial
1/0
r-~DOO-D07
SYScu<
VIC068A
Wl,r-
SCON-
r-
..Ei
~~~t:r K
L015 - L08
DDIR
r:~
/..1
, 3
SWDEN*
¢:::::) AMO - AM
~AS.,DSO"
051"", CTACK*,
WRITE*, LWORD·, BERR·
¢:::::) BGilN', BGIOUT',
lIACIKO'
J II
Lalch
&
Counter
Al-A7
lAO-LA7
Channel
tt
~
c
LOO ~ LD7
'--
••
l.:w
~
ASI~U
ASIZl
10(8-15)
t
J
FCT
245
U
f(::::) BAi*,
BBS Y*
lACK"", IACKIN*, IACKOUT*
IRQ1', IRQ7'
ACFAIL'", SYSFAlL*
URQ1'-LlRQ7'
ISOBE'
DDIR
L-r--~
FCT
0 8-015
543
-t--
tt
Slave SlS
Select
DecodE t-SLS
I
A(8-31)
8-20
'--
tL:
~
ICF El'
VACQ68-5
CY7C960
CY7C961
Slave VMEbus Interface
Controller Family
Features
• 80 Mbyte per second block transfer
rates
• All VME64 transactions provided, including A64!D64, A40/MD32
transfers
• Auto Slot ID
• CR/CSR space
• All standard (rev C) VMEbus transactions implemented
• VMEbus Interrupter
• No local CPU required
• Programmable from VMEbus or serialPROM
• DRAM controller, including refresh
•
•
•
•
•
•
On-chip DMA controller (CY7C96l)
Local I/O controller
Flexible VMEbus address scheme
User-configured VMEbus response
64-pin TQFP, lOxlOmm (CY7C960)
lOO-pin TQFP, l4x14mm (CY7C96l)
Functional Description
The CY7C960 Slave VMEbus Interface
Controller provides the board designer
with an integrated, full-featured VME64
interface. This 64-pin device can be programmed to handle every transaction defined in the VME64 specification. The
CY7C961 is based upon the CY7C960:
additional features include Remote Mas-
ter capability whereby the CY7C961 can
be commanded to move data as a VMEbus master. The CY7C961 is packaged in
a lOO-pin outline.
The CY7C960 contains all the circuitry
needed to control large DRAM arrays
and local I/O circuitry without the intervention of a local CPU. There are no registers to read or write, no complex command blocks to be constructed in
memory. The CY7C960 simply fetches its
own configuration parameters during the
power-on reset period. After reset the
CY7C960 responds appropriately to
VMEbus activity and controls local circuitry transparently.
CY7C960 Logic Block Diagram
REGION[2:0]
CY7C864 Controller
AM[5:0]
8Y8RE8ET"
CLK
AS"
080"
081"
OTACK*
WRITE"
LA[7:0]
Chip Select
Output Pattern
Table
C8[2:0]
VME Control
Interface
OBE[3:0]
LACK
'~~
IACK*
IACKIN"
IACKOUT"
Local Address
Controller
VME Interrupt
Interface
~
:::J
DRAM
Controller
Local
Control
Circuit
i~~8
LOEN
PREN
8WOEN
RIW
0960-1
8-22
CY7C960
CY7C961
.~YPRESS
CY7C961 Pin Configuration
10099989796 959493 92 91 90 89 88 8786858483 8281 80 79 787776
LACK
L1RQ
LOEN
LD'
75
74
73
72
csa
7'
vee
70
69
L02
CS'
NC
AM3
REGION3/CS2
AM4
VCC
BERR*
GND
VMECNT
REGION2
68
67
68
65
64
63
62
6'
60
59
LDO
CLK
NC
WRITE*
NC
REGION,
REGIONO
DENIN
LA7
lAS
lAS
L07
lA4
SELECTLM
NC
IRQ""
NC
LAS
LAEN321
GND
AM5
LA2
BBSY·
IIcc
LA,
NC
58
57
68
55
54
53
52
LOS
DENIN'
5'
LAEN
DS1*
NC
LAO
FC'
c9604
Functional Description (continued)
The CY7C960 controls a bridge between the VMEbus and local
DRAM and I/O. Once programmed, the CY7C960 provides ac·
tivities such as DRAM refresh and local I/O handshaking in a
manner that requires no additional local circuitry. The VMEbus
control signals are connected directly to the CY7C960. The
VMEbus address and data signals are connected to companion
address/data transceivers which are controlled by the CY7C960.
The CY7C964 VMEbus Interface Logic Circuit is an ideal companion device: the CY7C964 provides a slice of data and address
logic that has been optimized for VME64 transactions. In addition to providing the specified drive strength and timing for
VME64 transactions, the CY7C964 contains all the circuitry
needed to multiplex the address/data bus for multiplexed VMEbus transactions. It contains counters and latches needed during
BLT operations. And it also contains address comparators which
can be used in the board's Slave Address Decoder. For a 6U or
9U application, four CY7C964 devices are controlled by a single
CY7C960. For 3U applications, the CY7C960 controls two
CY7C9~4 devices and an address latch.
The design of the CY7C960 makes it unnecessary to know the
details of the VMEbus transaction timing and protoco!. The complex VMEbus activities are translated by CY7C960 to simple local cycles involving a few familiar control signals. Similarly, it is
not necessary to understand the operation of the companion device, CY7C964: all control sequences for the part are generated
automatically by the CY7C960 in response to VMEbus or local
activity. If more information is desired, consult the CY7C964
chapter in the VlC64 Design Notes (available separately).
VMEbus transactions supported by the CY7C960 include D8,
016, D32 (inc!. UAT), MD32, D64, A16, A24, A32, A40, A64
single-cycle and block-transfer reads and writes, Read-ModifyWrite cycles (inc!. multiplexed), and Address-only (with or without Handshake). The CY7C960 functions as a VMEbus Interrupter, and supports the new Auto Slot ID standard and CRlCSR
space. The CY7C960 also handles LOCK cycles, although full
LOCK support is not possible within the constraints of the
CY7C960 pinout. Full LOCK support is provided by the
CY7C961.
On the local side, no CPU is needed to program the CY7C960,
nor to manage transactions. All programmable parameters are
initialized through the use of either the VMEbus or a serial
PROM. As the CY7C960 incorporates a reliable power-on reset
circuit, parameters are self-loaded by the device at power-up ot
after a system' reset. If the VMEbus is used to provide parameters, a VMEbus Master provides the programming information
using a protocol, described in the User's Guide, which is compliant with the Auto Slot ID protocol from the new VME64 specification.
To assist in generating the configuration file, a Windows-based
program is available which guides the user through the process of
8-24
CY7C960
CY7C961
~¥PRESS
Related Documents
CY7PJ60 Family User's Guide
Ordering Info~ation
Ordering Code
Package
Name
Package 1Ype
CY7C960-AC
A64
lOxlO mm body Plastic Thin Quad Flat Pack
CY7C960-NC
N65
l4x14 mill body Plastic Quad Flat Pack
Ordering Code
CY7C96l-NC
Package
Name
A100
Package 1»pe
l4x14 mm body Plastic Thin Quad Flat Pack
Document #: 38-002.50
8-26
Operating
Range
Commercial
Operating
Range
Commercial
~YPRESS
CY7C964
Pin Configuration (continued)
68·Pin Cemmic PGA
Bottom View
4
3
2
DENIN1*
LAO
GNO
vee
LAEN
DENIN*
LDO
Vee
LA,
B
0'
W'
LA2
C
A'
02
W2
LA3
D
A2
D3
lD3
GNO
A:l
GNO
lA4
LD4
04
A4
I.A5
L05
D5
AS
LAS
L06
H
D6
AS
LA7
Vee
J
07
Vee
GNO
Vee
K
10
9
8
7
NJ
ABEN"
D64
vee
LCIN*
GNO
GNO
DO
DENO·
BlT·
veiN·
Vee
11
GNO
6
5
A7
LEOI
LADO
VCOMP"
LCOUT*
STROBE'"
GNO
LEDO
LADI
VCOUT"
GNO
MWB"
WS
FC'
L07
A
I
Index Mark
On Top
8-28
E
F
G
L
C964-2
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~'CYPRESS
Section Contents
FCT Logic Products
Page Number
Parameter Measurement Information ........................................................................ 9-1
Device
Description
CY29FCT52T
CY29FCT52OT
CY29FCT818T
8-Bit Registered nansceiver .................................................... 9 - 6
Multi-Level Pipeline Register .................................................. 9-12
Diagnostic Scan Register .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9 - 17
1-of-8 Decoder .............................................................. 9-23
Quad 2-Input Multiplexer ..................................................... 9-27
Quad 2-Input Multiplexer ..................................................... 9-27
4-Bit Binary Counter ......................................................... 9-33
4-Bit UplDown Binary Counter ................................................ 9-38
8-Bit BufferlLine Driver ...................................................... 9-44
8-Bit Buffer/line Driver ...................................................... 9-44
8-Bit nansceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-49
Quad 2-Input Multiplexer ..................................................... 9-54
8-Bit Register ............................................................... 9-59
8-Bit Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-64
8-Bit Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-64
8-Bit Register ............................................................... 9-69
8-Bit Register ............................................................... 9-69
8-Bit Register ............................................................... 9 -74
Quad 2-Input Register ........................................................ 9 -79
Dual 8-Bit Parity Generator/Checker ............................................ 9-84
8-Bit BufferlLine Driver ...................................................... 9-89
8-Bit BufferlLine Driver ...................................................... 9-89
8-Bit Latched Registered nansceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-94
8-Bit Registered Transceiver .................................................. 9-100
8-Bit Registered nansceiver .................................................. 9-100
8-Bit Registered nansceiver .................................................. 9-106
8-Bit Bus Interface Register .................................................. 9-112
9-Bit Bus Interface Register .................................................. 9-112
10-Bit Bus Interface Register ................................................. 9-112
10-Bit Buffer .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-121
10-Bit Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-126
8-Bit BufferlLine Driver ..................................................... 9-133
8-Bit BufferlLine Driver ..................................................... 9-133
8-Bit nansceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-138
Quad 2-Input Multiplexer .................................................... 9-142
8-Bit Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-146
8-Bit Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-146
8-Bit Register .............................................................. 9 -151
8-Bit Register .............................................................. 9 -151
8-Bit BufferlLine Driver ..................................................... 9-156
8-Bit Latched nansceiver .................................................... 9-160
8-Bit Registered nansceiver .................................................. 9-166
8-Bit Registered nansceiver .................................................. 9-166
8-Bit Registered nansceiver .................................................. 9-172
10-Bit Buffer ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9 -179
16-Bit BufferlLine Driver .................................................... 9-184
16-Bit BufferlLine Driver .................................................... 9-184
16-Bit Buffer/Line Driver ................................................ 9-188
16-Bit BufferlLine Driver ................................................ 9-188
16-Bit BufferlLine Driver ................................................ 9-188
CY54n4FCT138T
CY54n4FCT157T
CY54n4FCT158T
CY54n4FCT163T
CY54n4FCT191T
CY54n4FCT24OT
CY54n4FCT244T
CY54n4FCT245T
CY54n4FCT257T
CY54n4FCT273T
CY54n4FCT373T
CY54n4FCT573T
CY54n4FCT374T
CY54n4FCT574T
CY54n4FCT377T
CY54n4FCT399T
CY54/74FCT48OT
CY54n4FCT54OT
CY54n4FCT541T
CY54n4FCT543T
CY54n4FCT646T
CY54n4FCT648T
CY54/74FCT652T
CY54n4FCT821T
CY54n4FCT823T
CY54n4FCT825T
CY54n4FCT827T
CY54n4FCT841 T
CY54n4FCT2240T
CY54n4FCT2244T
CY54n4FCT2245T
CY54/74FCT2257T
CY54n4FCT2373T
CY54n4FCT2573T
CY54n4FCT2374T
CY54n4FCT2574T
CY54n4FCT2541T
CY54n4FCT2543T
CY54n4FCT2646T
CY54n4FCT2648T
CY54n4FCT2652T
CY54n4FCT2827T
CY74FCT1624OT
CY74FCT162240T
CY74FCT16244T
CY74FCT162244T
CY74FCT16444T
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'rcYPRESS
Parameter Measurement Information
Power Specifications
Cypress logic devices do not use a. substrate bias generator. As a
result, the quiescent or standby current is typically a few
microamperes when the voltage at the inputs are either less than
0.2V or greater than V cc-0.2v. On the datasheet this current is
described as Quiescent Power Supply Current, given the symbol
Icc, and specified on a per IC basis. No inputs are switching and
all outputs are open, and if possible, disabled.
When the input signal transitions between the logic levels, both
the p-channel, pull-up transistor and the n-channel pulldown
transistor in the input TTL to CMOS translator are partially
turned on, which creates a low-impedance path between Vee and
ground. On the datasheet this current is described as "Quiescent
Power Supply Current (TTL inputs)," given the symbol ~Iee,
and specified on a per input basis. One input is at VIN=3,4V and
other inputs at either Vee or 0 Volts, and all outputs are open,
and if possible, disabled.
The Dynamic Power Supply Current, given the symbol ICCD, is
not measured directly, but is provided so that the user can
calculate total current. It is specified in rnA per Megahertz at
50% duty cycle, with one input toggling and one output toggling
(enabled) but open (unloaded).
Note that the preceding three currents are specified with the
outputs open. The AC CVf current required to charge and
discharge parasitic capacitances (e.g., other inputs being driven
by the outputs), as well as any DC load currents must be
calculated separately.
Total supply current, Ie, is specified on the data sheet for several
different conditions. The inputs are switched between ground and
either TTL (3,4V) or CMOS (Vee-0.2V) levels with rise and
fall times of 2.5 ns. Slow rise and fall times can cause the dynamic
current to increase, because the input signals are within the
transition region for longer times. A characterization curve of
normalized (led~Iec) currents versus VIN is shown in Figure 14.
Total device current can be estimated by using the following
formula to calculate the total current. This equation implies
calculating the current associated with each input and adding
them up. The same procedure must be followed to calculate the
CVf current required to charge and discharge the load
capacitances.
le=lee+~lcc DH NT+leCD (fcpl2+fn No)
Where:
Icc = Quiescent Current
Icc = Power Supply Current for a
TTL HIGH input (VIN = 3,4 V)
DH = Duty Cycle for TTL inputs
HIGH
NT = Number of TTL inputs at DH
leCD = Dynamic Current caused by an
input transition pair (HLH
orLHL)
fep = Clock frequency for registered
devices, otherwise zero
fo
= Input signal frequency
No = Number of inputs changing at Fn
ESD (Electrostatic Discharge)
Precautions
Large electrical fields can damage the thin gate oxides of MOS
transistors. Special input protection circuits are used at every
input pin of all Cypress products to provide protection against
ESD. This circuitry has been designed to withstand repeated
applications of high voltages without failure or performance
degradation. This is accomplished by preventing the high voltage
(ESD) from reaching the thin gate oxides of the internal
transistors. For a description of the ESD protection circuit and an
explanation of its operation, please see the application note titled
"Input/Output Characteristics of Cypress Circuits" in the Cypress
Applications Handbook.
Precautions should be taken by persons handling CMOS devices.
It is recommended that individuals wear a grounded wrist strap
or ankle strap when handling Cypress FCT-T devices.
9-2
~YPRESS
Parameter Measurement Information
Paran-6
Paran-5
Figure 8. Three-State Output HIGH Enable
and Disable Times
Figure 5. Propagation Delays from Rising-Edge Clock
or Enable
-!w
-
MR
Paran-?
VOUT
Figure 9. Set-Up and Hold Times to Active mGH
Enable or ParaUel Load
\10UT _____t_PL,../"[.
Paran-10
Figure 6. Asynchronous Reset, Active Rising·Edge Clock
or Active LOW Enable
5.0V
4.OV
~
3.0V
I.
~
3.5V
Your
2.0V
I. ~
HIGH Level Notes Margin
~
Transition Area
O.BV
I.
O.5V
:.J
,VOL
II
OV
AC Test
DC Test
VIL = O.BV; VIN = 2.0V:
VOL = O.5V; VOH=2.4V
O.3V
AC HIGH Leval
DC HIGH Level Range
2.4V
r..!
~-
Noise
Immunity
Test
Paran-B
Figure 7. Three-State Output LOW Enable
and Disable Times
Figure 10. Input Sigual Levels
9-4
LOW Level Notes Margin
DC LDW Level Range
AC LQWLeval
Paran-9
CY29FCT52T
8-Bit Registered Transceiver
Features
both directions between two bidirectional
buses. Separate clock, clock enable, and
three-state output enable signals are provided for each register. Both A outputs
and B outputs are guaranteed to sink 64
• Power·off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and
output logic levels
64 mA (Com'I),
• Sink Current
48mA(Mil)
Source Current
32 mA (Com'I),
12mA (Mil)
• Function, pinout, and drive
compatible with FCT, F Logic and
AM2952
• FCT·C speed at 6.3 ns max. (Com'l)
FCT-B speed at 7.5 ns max. (Com'l)
• Reduced VOH (typically 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
Significantly improved noise
characteristics
=
mAo
The outputs are designed with a poweroff disable feature to allow for live insertion of boards.
Functional Description
two
The CY29FCfS2T has
8-bit back-toback registers that store data flowing in
• ESD > 2000V
Logic Block Diagram
Pin Configurations
CPA
....
I
=
""
A,
0,
=
'"
Do CE CP 00
a,
Bo
B,
LCC
ThpView
DIP/SOlC/QSOP
ThpView
""""-
0,
A.
B.
Os
a,
S,
I~ alo.,..~
r:a
coNCO)
m
Ao
D.
A.
B.
1110 9 8 7 6 5
Aa
Aa
Os
as
D.
A7
Dr
CPA
Bs
a.
Bs
07
Br
=
=
GND
NC
CPB
~
00
00 _
a,
0,
a,
D.
a:.
Os
a.
D.
a,
0,
a.
D.
07 CE CP
...
"-
OEA
12
13
14
15
16
17
18
B7[~PVCC
-=t
ED
Be[2
4
Bs
Be
Br
19202122232425
28
27
26
NC
V"
A7
A.
s,~3
B~~4
S,~5
~t
6
B, [ 7
Bo[8
0EIl [ 9
CPA~ 10
2<~~~<,¢<1n
FCT52T-2
~~
GND
11
12
23~A7
22~Aa
PAs
21
2C~Ao
~
19
""18 ~ ""17PA,
16
15
=
b=
FCT52T·3
Dr
I
CPB
=
Function Table[l]
Output Control
Inputs
OE
IntemalQ
Y.Outpnts
Function
Function
H
X
Z
Disable Outputs
Hold Data
L
L
L
H
L
H
Enable Ontputs
D
CP
CE
IntemalQ
X
X
H
NC
L
L
L
H
Load Data
L
H
~
14 P CPB
13
FCT52T-1
S
S
P""
Note:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X
= Don't Care.
9-6
~YPRESS
CY29FCT52t
Electrical Characteristics rver the Operating Range
Parameter
VOH
VOL
Vm
Desc,rlption
Output HIGH Voltage
Outpui WW Voltage
Min.
'lest Conditions
1YPJ51
Max.
Vcc=Min., IOH=-32 inA
Com'l
2.0
Vcc=Min., IOH=-15 rnA
Com'l
2.4
3.3
Vee=Min., IOH=-12 rnA
Mil
2.4
3.3
Vee=Min., IOL=64 rnA
Com'l
0.3
0.55
Vee=Min.,IoL=4SrnA
Mil
0.3
0.55
Input HIGH Voltage
Unit
V
V
V
V
V
2.0
VIL
Input LOW Voltage
VH
Hysteresis[6]
-'
All inputs
VIK
Inplit Clamp Diode Voltage
Vee=Min.,IIN=-1SrnA
II
Input HIGH Current
V
O.S
V
0.2
~0.7
V
-1.2
V
Vee=Max., VIN=Vee
5
±1
1m
Input HIGH Current
Vee=Max., VIN=2.7V
IlL
Input W~ Current
Vee-Max., VIN-0.5V
leiS
Output Short Circuit Currentf7]
Vee=Max., VeiUT=O.OV
IOFF.
Power-Off Disable
Vcc=OV; VOUT=4.5V
-60
':"120
±1
iJA
iJA
iJA
-225
rnA
±1
iJA
Capacitance[6]
'iYpJ5]
Max.
Unit
CIN
Inplit qtpacitance
5
10
pF
COUT
Output Capacitance
9
12
pF
Parameter
Description
Notes:
5. 1YPical values are at Vec=S.OV; TA=+25'C ambient.
6. This parameter is guarailteed but not tested.
7. Not more than one output should be shorted at a time. Duration of
short sj10uld not exceed one second. The use of high-speed test
apparatus andlor sample and hold techniques are preferable in order
9-S
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other. parametric tests. In any sequence of
parameter tests, los tests should be performed last.
Ii/EYPRESS. =============C=Y2=9=FC=T=52=T=
Switching Characteristics Over the Operating Range
29FCT52BT
29FCT52AT
Military
tpZH
tpZL
Military
Commercial
Fi
Description
MinJ12]
Max.
MinJ12]
Max.
MinJ12]
Max.
MinJ12]
Max.
Unit
No.~·3]
Propagation Delay
CPA, CPB to A, B
2.0
11.0
2.0
10.0
2.0
8.0
2.0
7.5
ns
1,5
0E;XutEnable Time
orOEBtoA
1.5
13.0
1.5
10.5
1.5
8.5
1.5
8.0
ns
1,7,8
10.0
1.5
10.0
1.5
8.0
1.5
7.5
ns
1,7,8
Parameter
tpLH
tPHL
Commercial
o
orB
tpHZ
tpLZ
Output Disable
Time
OEA or DEB to A
orB
1.5
ts
Set-UpTime
HIGH or LOW,
A, B to CPA, CPB
2.5
2.5
2.5
2.5
ns
4
tH
Hold Time
HIGH or LOW,
A, B to CPA, CPB
2.0
2.0
1.5
1.5
ns
4
ts
Set-UpTime
HIGH or LOW,
CEA,
to CPA,
CPB
3.0
3.0
3.0
3.0
ns
4
tH
Hold Time
HIGH or LOW,
CEA, CEB to CPA,
CPB
2.0
2.0
2.0
2.0
ns
4
tw
Pulse Width,[6]
HIGH or LOW,
CPAorCPB
3.0
3.0
3.0
3.0
ns
5
om
29FCT52CT
Military
Parameter
Description
Commercial
MinJ12]
Max.
MinJ12]
Max.
Unit
Fili'
No.3]
tPLH
tpHL
Propagation Delay CPA, CPB to A, B
2.0
7.3
2.0
6.3
ns
1,5
tpZH
tpZL
Output Enable Time, OEA or DEB to A or B
1.5
8.0
1.5
7.0
ns
1,7,8
tpHZ
tpHZ
Output Disable Time, OEA or OEB to A or B
1.5
7.5
1.5
6.5
ns
1,7,8
ts
Set-Up Time HIGH or LOW, A, B to CPA, CPB
2.5
2.5
ns
4
tH
Hold Time HIGH or LOW, A, B to CPA, CPB
1.5
1.5
ns
4
ts
Set-Up Time HIGH or LOW, CEA, CEB to CPA, CPB
3.0
3.0
ns
4
tH
Hold Time HIGH or LOW, CEA,
2.0
2.0
ns
4
tw
Pulse Width,[6j HIGH or LOW, CPA or CPB
3.0
3.0
ns
5
om to CPA, CPB
Notes:
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. See "Parameter Measurement Information" in the General Information Section.
9-10
CY29FCT520T
Multi-Level Pipeline Register
64 rnA (Com'I),
32mA(MiI)
32 mA (Com'I),
12mA (Mil)
• Single and dual. pipeline operation
modes
.
• Multiplexed data inputs and outputs
Features
• Sink current
• FUnction, pinout, and drive
compatible with FCT, F Logic, and
Source current
AM29520
• FCT-C speed at 6.0 ns max. (Com'l)
FCT-B speed at 7.5 ns max. (Com'l)
• Reduced VOH(typicaIly = 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly ~proved noise
characteristics
• Power-Off disable feature
• Matched rise and fall times
• FUlly compatible with TTL input and
output logic levels
• ESD > 2000V
Functional Description
The FCTS20T is a multi-level 8-bitcwide
pipeline register. The device consists of
four registers, AI, A2, BI, and B2, which
are configured by the instruction inputs
10, 11 as a single 4-level pipeline or as two
two-level pipelines. The contents of any
register may be read at the multiplexed
output at any time by using the mux-selection controls So and S1.
Logic Block Diagram
The pipeline register is positive edge triggered . and data is shifted by the rising
edge of the clock input. Instruction 1=0
selects the four-level pipeline mode.
Instruction I =I selects the two-level B
pipeline while 1=2 selects the two-level A
pipeline. 1=3 is the HOLD instruction;
no shifting is performed by the clock in
this mode.
In the two-level operation mode, the
FCTS20T data is shifted from level I to
level 2 and new data is loaded into level!.
The outputs are designed with a poweroff disable feature to allow for live insertion of boards.
Pin Configurations
8~ 00- 0 ,
DIP/SOIC/QSOP
Top View
LCC
Top View
INSTRUCTION
121110 9 8 7 6 5 4
0,
ClK
GNO
NC
13
14
15
16
17
18
OE
Y,
YB
MUX So
SEL S1
3
2
1
28
27
26
19 2021 22232425
Vee
10
I,
(f~d~~8c
1_
0- } REGISTER
_
I,
CONTROLS
ClOCK--
So
S,
Do
0,
Do
I,
10
NC
Yo
Y,
02
Y2
03
0,
Vee
So
S,
>IO>~ :'~~.;,;'
FCT520T-3
D.
Y3
Y,
O.
0,
Y.
YB
ClK
GNO
OE
Y,
FCT520T·2
MUX
FCT520T·1
Output Selection Mux Table
Pipeline Instruction Table
1=0
11=0
1=1
10= 0
11"" 0
1=2
10= 1
11= 1
~ ~~
A2
82
Single four-level
0
0
Dual two-Ievel
Inputs
1=3
10=0
0
G
11=1
10=1
0
0
0
G
Hold
9-12
SI
So
Output
I
I
I
Al
A2
BI
B2
0
0
0
I
0
CY29FCT520T
Power Supply Characteristics
'lYP.!4)
Max.
Unit
Icc
Quiescent Power Supply Current
Vee=Max., VINsO.2v,
VIN20 Vee-0.2V
0.1
0.2
rnA
Mee
Quiescent Power Supply Current (TTL
inputs HIGH)
Vee = Max., VIN=3.4V,[7)
fl =0, Outputs Open
0.5
2.0
rnA
IceD
Dynamic Power Supply Current[8)
Vee=Max., One Input Thggling,
50% Duty Cycle, Outputs Open,
OE=GND,
VINsO.2VOrVIN20 Vee-0.2V
0.06
0.12
mAl
MHz
Ie
Total Power Supply Currentf9]
Vee=Max., fo=lO MHz,
50% Duty Cycle, Outputs Open,
One Bit Toggling at fl =5 MHz,
OE=GND,
VINsO.2Vor VIN20Vee-0.2V
0.7
1.4
rnA
Vee=Max., fo=lO MHz,
50% Duty Cycle, Outputs Open,
One Bit Thggling at fl =5 MHz,
OE=GND,
VIN=3.4Vor VIN=GND
1.2
3.4
rnA
Vee=Max., fo=lO MHz,
50% Duty Cycle, Outputs Open,
gjght Bits ThggJing at fl =5 MHz,
OE=GND,
VINsO.2Vor VIN20Vee-0.2V
2.8
5.6[10)
rnA
Vee = Max., fo=10 MHz, 50% Duty Cycle,
Outputs Open,
§jght Bits Toggling at fl =5 MHz,
OE=GND,
VIN=3.4Vor VIN=GND
5.1
14.3[10)
rnA
Parameter
Description
Test Conditions
Notes:
7. Per TIL driven input (VIN=3.4V); all other inputs at Vcc or GND.
8. This parameter is not directly testable, but is derived for use in Thtal
Power Supply calculations.
9. Ic
= IQUIESCENT + IINPUTS + IDYNAMIC
Ic
= Icc+AlCCDRNT+ICCD(foI2 + fINI)
Icc
= Quiescent Current with CMOS input levels
Alcc = Power Supply Current for a TIL HIGH input
(VIN=3.4V)
DR
= Duty Cycle for TIL inputs HIGH
NT
= Number of TIL inputs at DR
ICCD = Dynamic Current caused by an input transition pair
(HLHorLHL)
fa
= Clock frequency for registered devices, otherwise zero
fl
= Input signal frequency
Nl
= Number of inputs changing at f\
All currents are in milliamps and all frequencies are in megahertz.
10. Values for these conditions are examples of the Icc formula. These
limits are gnaranteed but not tested.
9-14
CY29FCTS20T
.7cYPBESS
Ordering Information
Speed
(ns)
6.0
Ordering Code
CY29FCfS20CTPC
P13/13A
CY29FCfS20CfQC
Q13
.
CY29FCf520CfSOC
7.0
Packlige
Name
CY2~FCf520CfDMB
CY2<)FCf520CfLMB
Package '!Ype
24-Lead (300-Mil) Molded DIP
Ope.rating
Range
Commercial
24-Lead (150-Mil) QSOP .
S13
24-Lead (300-Mil) Molded SOIC
D14
24-Lead (300-Mil) CerDIP
L64
28-Square Leadle~s Chip Carrier
P13113A
24-Lead (300-Mil) Molded DIP
Military
~
7.5
CY2')FCT520BTPC
..
CY29FCf520BTQC
8.0
14.0
16.0
Q13
Commercial
24-Lead (150-Mil) QSOP
CY29FCf520BTSOC
S13
24-Lead (30b-Mil) Molded SOIC
CY29Fc;t5~OBTDMB
D14
24-Lead (300-Mil) CerDIP
CY29Pc;t520BTLMB
L64
28-Square Leadless Chip Carrier
CY29FCf520ATPC
P13/13A
24-Lead (300-Mil) Molded DIP
CY29Fct520ATQC
Q13
24-Lead (150-Mil) QSOP
CY29FCf520ATSOC
S13
24-Lead (300-Mil) Molded SOIC
CY29FCfS20AIDMB
D14
24-Lead (300-Mil) CerDIP
CY29FCT520ATLMB
L64
28-Square Leadless Chip Carrier
Document #: 38-00274-A
9-16
Military
Commercial
Military
Function Table[!]
Inputs
Inputs
Shadow
Register
Pipeline
Register
NA
S7
Sot-SOl
Sjt-Sj_!
NA
Pjt-Dj
Load Pipeline Register from Data Input
L
H
SOl
Sjt-Yj
Hold
NA
NA
NA
pit-Sj
Load Shadow Register from Y Output
Hold Shadow Register; D7- Do Output Enabled
Load Pipeline Register from Shadow Register
MODE
SOl
DCLK
PCLK
SDO
L
X
S
X
S7
L
X
X
S
H
H
H
L
H
X
S
S
X
X
X
S
Maximum Ratings[2,3]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied ........................ -65°C to + 135°C
Supply Voltage to Ground Potential ......... -0.5V to +7.0V
DC Input Voltage ........................ -0.5V to + 7.0V
DC Output Voltage ...................... -0.5V to + 7.0V
DC Output Current (Maximum Sink Current/Pin) . . .. 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.5W
Operation
Serial Shift; D7-Do Output Disabled
Static Discharge Voltage ........................ >2001 V
(per MIL-STD-883, Method 3015)
Operating Range
Range
Commercial
Range
CT
Ambient
Thmperature
O°Cto +70°C
Vee
5V±5%
Commercial T,AT,BT
-40°C to +85°C
5V±5%
Military[4]
-55°C to + 125°C
5V ± 10%
All
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Thst Conditions
3.
4.
5.
6.
'lYpJ5]
Max.
Unit
Com'l
2.0
Vee = Min., IOH=-15 rnA
Com'l
2.4
3.3
Vee=Min., IOH=-3 rnA
Mil
2.4
3.3
Vee=Min., IOL=64 rnA
Com'l
0.3
0.55
V
Vee=Mm., IOL=20 rnA
Mil
0.3
0.55
V
0.8
V
V
V
V
V
2.0
VH
Hysteresis[6]
AIl inputs
0.2
VIK
Input Clamp Diode Voltage
Vee=Min., IIN=-18 'rnA
-0.7
II
Input mGH Current
IJH
V
-1.2
V
Vcc=Max., VIN=Vee
5
Input mGH Current
Vcc=Max., VIN=2.7V
±1
IlL
Input LOW Current
Vee=Max., VIN=0.5V
±1
IOZH
Off State HIGH-Level Output
Current
Vee=Max., VOUT=2.7V
10
JAA
JAA
JAA
JAA
IOZL
Off State LOW-Level
Output Current
Vee=Max., VOUT=0.5V
-10
JAA
los
Output Short Circuit Current[7]
Vee=Max., VOUT=O.OV
-225
mA
IOFF
Power-Off Disable
Vee=OV; VOUT=4.5V
±1
JAA
Notes:
1. NA = Not Applicable
2.
Min.
Vee=Min., IOH=-32 rnA
7.
Unless otherwise noted, these limits are over the operating free-air
temperatnre range.
Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
TA is the "instant on" case temperature.
1YJ>ical values are at Vcc=S.Ov, TA=+ZS'C ambient.
This parameter is guaranteed but not tested.
9-18
-60
-120
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus andlor sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a· high output
may raise the chip temperatnre well above normal and thereby cause
invalid readings in other parameters tests. In any sequence of
parameter tests, los tests should be performed last.
Switching Characteristics Over the Operating Range[12]
FCT818T
Military
Parameter
tpD
ts
tH
tpLZ
tpHZ
tpZL
tPZH
tw
Description
MinJ13]
Propagation Delay
PCLKtoY
MODE to SDO
SDItoSDO
DCLKtoSDO
Max.
FCT818AT
Commercial
MinJ13]
Max.
Military
MinJ13]
13
16
16
25
18
18
18
30
Max.
Commercial
MinJ13]
12
18
18
30
Fi
Max.
Unit
Nol4]
9
16
15
25
ns
ns
ns
ns
5
6
3
5
Set-UpTime
DtoPCLK
MODEtoPCLK
YtoDCLK
MODE to DCLK
SDIto DCLK
DCLKtoPCLK
PCLKtoDCLK
10
15
5
12
10
15
45
8
15
5
12
10
15
40
6
15
5
12
10
15
45
4
15
5
12
10
15
40
ns
ns
ns
ns
ns
ns
ns
4
Hold Time
DtoPCLK
MODE to PCLK
YtoDCLK
MODE to DCLK
SDIto DCLK
2
0
5
5
0
2
0
5
2
0
2
0
5
5
0
2
0
5
2
0
ns
ns
ns
ns
ns
4
Output Disable Time
LOW
OEtoY
DCLKtoD
20
45
15
45
20
45
15
45
ns
ns
5
Output Disable Time
HIGH
OEtoY
DCLKtoD
30
90
25
85
30
90
25
80
ns
ns
8
5
Output Enable Time
WW
OEtoY
DCLKtoD
20
35
15
30
20
35
15
25
ns
ns
5
Output Enable Time
HIGH
OEtoY
DCLKtoD
20
30
15
25
20
30
15
25
ns
ns
8
ns
ns
5
5
Pulse Width
PCLK (HIGH and
LOW)
DCLK (HIGH and
WW)
15
25
15
25
Notes:
12. AC Characteristics guaranteed with CL = 50 pF as shown in Figure 1
of the "Parameter Measurement Information" in the General Information Section".
15
25
10
15
7
7
5
13. Minimum limits are guaranteed but not tested on Propagation Delays.
14. See "Parameter Measurement Information" in the General Information Section.
9-20
.~YPRESS =====;;;;;;;;;;;;;========CY;;;;;;2;;;;;;9;;;;;;FC;;;;;;T;;;;;;8;;;;;;18=T
Speed
(ns)
6.0
Ordering Code
7.6
9.0
12.0
13.0
18.0
Package 'Jype
CY29FCT818crPC
P13/13A
CY29FCT818CTQC
Q13
24-Lead (150-Mil) QSOP
S13
24-Lead (300-Mil) Molded SOlC
CY29FCf818CfSOC
7.5
Package
Name
CY29FCT818BTPC
P131l3A
CY29FCT818BTQC
Q13
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Molded DIP
Operating
Range
Commercial
Commercial
24-Lead (150-Mil) QSOP
CY29FCT818BTSOC
S13
24-Lead (300-Mil) Molded SOlC
CY29FCf818CTDMB
D14
24-Lead (300-Mil) CerDIP
CY29FCf818CfLMB
L64
28-Square Leadless Chip Carrier
CY29FCf818ATPC
P13/13A
24-Lead (300-Mil) Molded DIP
CY29FCf818ATQC
Q13
Military
Commercial
24-Lead (150-Mil) QSOP
CY29FCT818ATSOC
S13
24-Lead (300-Mil) Molded SOlC
CY29FCT818BTDMB
D14
24-Lead (300-Mil) CerDIP
CY29FCT818BTLMB
L64
28-Square Leadless Chip Carrier
CY29FCf818ATDMB
014
24-Lead (300-Mil) CerDIP
CY29FCf818ATLMB
L64
28-Square Leadless Chip Carrier
CY29FCf818TPC
P13/13A
24-Lead (300-Mil) Molded DIP
CY29FCf818TQC
Q13
24-Lead (150-Mil) QSOP
CY29FCT818TSOC
S13
24-Lead (300-Mil) Molded SOlC
CY29FCT818TDMB
014
24-Lead (300-Mil) CerDIP
CY29FCT818TLMB
L64
28-Square Leadless Chip Carrier
Document #: 38-00275-A
9-22
Military
Military
Commercial
Military
CY54/74FCT138T
Function Table[!]
Outputs
Inputs
El
E2
E3
Ao
Al
A2
00
01
02
03
04
05
06
07
H
X
X
X
H
X
X
X
L
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
if
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
Maximum Ratings[2, 3]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ >2001 V
(per MIL-STD-883, Method 3015)
Storage Temperature ................... -65°C to + 150°C
Ambient Temperature with
Power Applied ........................ -65°C to + 135°C
Supply Voltage to Ground Potential ......... -0.5V to + 7.0V
DC Input Voltage ........................ -O.5V to + 7.0V
DC Output Voltage ...................... -0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) .... 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.5W
Operating Range
CT
Ambient
Temperature
acCto +70°C
Vee
5V±5%
T,AT
-40°C to +85°C
5V±5%
All
-55°C to + 125°C
5V ± 10%
Range
Commercial
Range
Commercial
Military[4]
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Descriptiou
Output HIGH Voltage
Output LOW Voltage
Min.
Test Conditions
'JYp.!5]
Max.
Unit
Vee=Min.,IoH=-32rnA
Com'l
2.0
Vec=Min., IOH=-15 rnA
Com'l
2.4
3.3
Vcc=Min., IOH=-12 rnA
Mil
2.4
3.3
Vcc=Min.,IoL=64rnA
Com'l
0.3
0.55
V
Vcc=Min., IOL=32 rnA
Mil
0.3
0.55
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[6]
All inputs
VIK
Input Clamp Diode Voltage
Vcc=Min., IJN=-18 rnA
II
Input HIGH Current
Iill
Input HIGH Current
V
V
V
2.0
V
0.8
V
-1.2
V
Vcc=Max., VJN=Vcc
5
Vcc=Max., VJN=2.7V
±1
0.2
IlL
Input LOW Current
Vcc=Max., VJN=0.5V
los
Output Short Circuit Current[7]
Vcc=Max., Vour=O.OV
IOFF
Power-Off Disable
Vce=OV; Vour=4.5V
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care.
2. Unless otherwise noted, these limits are over the operating free-air
temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
4. TA is the "instant on" case temperature.
5. 'JYpical values are at Vcc=S.Ov, TA=+25°C ambient.
6. This parameter is guaranteed but not tested.
7.
9-24
-0.7
-60
-120
V
±1
fAA
fAA
fAA
-225
rnA
±1
fAA
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus andlor sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
CY54/74FCT138T
Switching Characteristics Over the Operating Range
FCT138T
Military
FCT138AT
Commercial
Military
Commercial
MinJll]
Max.
MinJll]
Max.
MinJll]
Max.
MinJll]
Max.
Unit
Fi/t
No. Z]
Delay
1.5
12.0
1.5
9.0
1.5
7.8
1.5
5.8
ns
1,2
tpLH
tpHL
~opa&.ation--pelay
1.5
12.5
1.5
9.0
1.5
8.0
1.5
5.9
ns
1,5
tpLH
tpHL
Propatftion Delay
E3 to
1.5
12.5
1.5
9.0
1.5
8.0
1.5
5.9
ns
1,5
Parameter
tpLH
tpHL
Description
Prop~ation
Ato
El orEz to 0
FCT138CT
Military
Parameter
Description
Commercial
MinJll]
Max.
Min,[uJ
Max.
Unit
Fi/t
No. Z]
tpLH
tpHL
Propagation Delay A to 0
1.5
6.0
1.5
5.0
ns
1,2
tpLH
tpHL
Propagation Delay El or Ez to 0
1.5
6.1
1.5
5.0
ns
1,5
tpLH
tpHL
Propagation Delay E3 to 0
1.5
6.1
1.5
5.0
ns
1,5
Ordering Information
Speed
(ns)
5.0
5.8
6.0
7.8
9.0
12.0
Ordering Code
Package
Name
Package 'fYpe
CY74FCf138CTPC
PI
16-Lead (300-Mil) Molded DIP
CY74FCf138CTQC
Q1
16-Lead (150-Mil) QSOP
CY74FCf138CTSOC
Sl
16-Lead (300-Mil) Molded SOIC
CY74FCf138ATPC
PI
16-Lead (300-Mil) Molded DIP
CY74FCT138ATQC
Q1
16-Lead (ISO-Mil) QSOP
CY74FCT138ATSOC
Sl
16-Lead (300-Mil) Molded SOIC
CY54FCT138CTDMB
D2
16-Lead (300-Mil) CerDIP
CYS4FCT138CTLMB
L61
20-Pin Square Leadless Chip Carrier
CY54FCT138ATDMB
D2
16-Lead (300-Mil) CerDIP
CY54FCT138ATLMB
L61
20-Pin Square Leadless Chip Carrier
CY74FCf138TPC
PI
16-Lead (300-Mil) Molded DIP
CY74FCT138TQC
Q1
16-Lead (150-Mil) QSOP
CY74FCf138TSOC
Sl
16-Lead (300-Mil) Molded SOIC
CY54FCf138TDMB
D2
16-Lead (300-Mil) CerDIP
CY54FCf138TLMB
L61
20-Pin Square Leadless Chip Carrier
Operating
Range
Commercial
Commercial
Military
Military
Commercial
Military
Notes:
11. Minimum limits are guaranteed but not tested on Propagation Delays.
12. See "Parameter Measurement Information" in the General Information Section.
Document #: 38-00297-A
9-26
CY54/74FCT157T
CY54/74FCT158T
.i?cYPRESS
Logic Block Diagram, FCT158T
Pin Configurations
LCC
ThI'View
DIP/SOIC/QSOP
ThpView
.f.~~r.>-(fJl
Vb
GND
NO
Yo
11e
8
9
10
11
12
13
Vee
7 6 5 4
FCTl58T
3
loa
loa
11a
lad
1
S
NO
Va
11d
Vee
lOb
Vd
E
11b
lac
Vb
'1e
20
19
14 1516 1718
E
GND L-C:'--_ _~ Vo
FCT1S7T-5
FCT157T-4
FCT157T-3
Logic Symbol
FCT158T
FCT157T-2
Pin Description
Name
S
Description
Common Select Input
E
Enable Inputs (Active LOW)
10
Data Inputs from Source 0
11
y
Data Inputs from Source 1
y
Inverted Output (FCT158T)
Non-Inverted Output (FCT157T)
Function Table[1]-FCT157T
Function Table[11-FCT158T
Inputs
E
S
H
X
L
L
L
L
H
H
L
L
Outputs
Inputs
Outputs
Io
11
Y
E
S
10
11
Y
X
X
X
L
X
L
H
H
X
L
H
H
H
H
H
X
X
H
L
L
L
L
X
L
H
X
X
X
L
H
L
Note:
L H; HIGH Voltage LeveL L ; LOW Voltage LeveL X ; Don't Care_
9-28
L
L
H
H
L
X
X
H
L
CY54/74FCT157T
CY54/74FCT158T
Power Supply Characteristics
lYpJ5]
Max.
Unit
Vee=Max., VIN,,;0.2Y,
VIN"' Vee-0.2V
0.1
0.2
rnA
Quiescent Power Supply Current (TIL
inputs HIGH)
Vee=Max., VIN=3.4Y,[S]
fl =0, Outputs Open
0.5
2.0
rnA
IceD
Dynamic Power Supply Currentl9]
Vee=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
OE=GND,
VIN,,;0.2Vor VIN"' Vee-0.2V
0.06
0.12
Ie
Total Power Supply Current[lO]
Vee=Max.,
50% Duty Cycle, Outputs Open,
One Input 'Ibggling at fl =10 MHz,
OE=GND,
VIN,,;0.2Vor VIN",Vee-0.2V
0.7
1.4
rnA
Vee=Max.,
50% Duty Cycle, Outputs Open,
One Input 'Ibggling at fl = 10 MHz,
OE=GND,
VIN=3.4Vor VIN=GND
1.0
2.4
rnA
Vee-Max.,
50% Duty Cycle, Outputs Open,
Four Bits Toggling at fl =2.5 MHz,
OE=GND,
VIN"; 0.2V or VIN"' Vee-0.2V
0.7
1.4[11]
mA
Vee=Max.,
50% Duty Cycle, Outputs Open,
Four Bits Toggling at fl =2.5 MHz,
OE=GND,
VIN=3.4Vor VIN=GND
1.7
5.4[11]
rnA
Parameter
Description
Icc
Quiescent Power Supply Current
l1Iee
Test Conditions
Notes:
S. Per TIL driven input (VIN=3.4V); all other inputs at Vcc or GND.
9. This parameter is not directly testable, but is derived for use in Total
Power Supply calculations.
to. Ic
= IQUIESCENT + IINPUTS + IDYNAMIC
Ic
= Icc+81CCDRNT+ICCD(f0J2 + fINI)
Icc
= Quiescent Current with CMOS input levels
81cc = Power Supply Current for a TTL HIGH input
(VIN=3.4V)
DR
= Duty Cycle for TIL inputs HIGH
rnA!
MHz
NT
= Number of TIL inputs at DR
ICeD = Dynamic Current caused by an input transition pair
(HLHor LHL)
fo
= Clock frequency for registered devices, otherwise zero
fl
= Input signal frequency
NI
= Number of inputs changing alfl
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the Icc formula. These
limits are guaranteed but not tested.
9-30
CY54/74FCT157T
CY54/74FCT158T
~
~"CYPRESS
Ordering Infonnation-FCT157T
Speed
(ns)
4.3
5.0
5.0
5.S
6.0
7.0
Ordering Code
Package
Name
Package 1Ype
CY74FCT157CI'PC
P1
16-Lead (300-Mil) Molded DIP
CY74FCT157CfQC
Q1
16-Lead (150-Mil) QSOP
CY74FCT157CTSOC
Sl
16-Lead (300-Mil) Molded SOlC
CY74FCT157ATPC
P1
16-Lead (300-Mil) Molded DIP
CY74FCT157ATQC
Q1
16-Lead (150-Mil) QSOP
CY74FCT157ATSOC
Sl
16-Lead (300-Mil) Molded SOlC
CY54FCf157CTDMB
D2
16-Lead (300-Mil) CerDIP
CY54FCf157CTLMB
L61
20-Pin Square Leadless Chip Carrier
CYS4FCf157ATDMB
D2
16-Lead (300-Mil) CerDIP
CYS4FCf1S7ATLMB
L61
20-Pin Square Leadless Chip Carrier
CY74FCf157TPC
P1
16-Lead (300-Mil) Molded DIP
CY74FCT1S7TQC
Q1
16-Lead (150-Mil) QSOP
CY74FCT157TSOC
S1
16-Lead (300-Mil) Molded SOlC
CY54FCT157TDMB
D2
16-Lead (300-Mil) CerDIP
CY54FCT157TLMB
L61
20-Pin Square Leadless Chip Carrier
Operating
Range
Commercial
Commercial
Military
Military
Commercial
Military
Ordering Infonnation-FCT158T
Speed
(ns)
4.3
5.S
5.5
6.3
6.5
7.5
Ordering Code
Package
Name
Package 1Ype
CY74FCT158CfPC
P1
16-Lead (300-Mil) Molded DIP
CY74FCT15SCTQC
Q1
16-Lead (lSO-Mil) QSOP
CY74FCT1SSCTSOC
Sl
16-Lead (300-Mil) Molded SOlC
CY74FCT15SATPC
P1
16-Lead (300-Mil) Molded DIP
CY74FCT15SATQC
Q1
16-Lead (150-Mil) QSOP
CY74FCT15SATSOC
Sl
16-Lead (300-Mil) Molded SOlC
CYS4FCT1SSCfDMB
D2
16-Lead (300-Mil) CerDIP
CYS4FCT158CTLMB
L61
20-Pin Square Leadless Chip Carrier
CYS4FCT15SATDMB
D2
16-Lead (300-Mil) CerDIP
CYS4FCT158ATLMB
L61
20-Pin Square Leadless Chip Carrier
CY74FCT158TPC
P1
16-Lead (300-Mil) Molded DIP
CY74FCf15STQC
Q1
16-Lead (150-Mil) QSOP
CY74FCT158TSOC
Sl
16-Lead (300-Mil) Molded SOlC
CY54FCT158TDMB
D2
16-Lead (300-Mil) CerDIP
CY54FCT158TLMB
L61
20-Pin Square Leadless Chip Carrier
Document #: 3S-002S8-A
9-32
Operating
Range
Commercial
Commercial
Military
Military
Commercial
Military
CY54/74FCT163T
Function Table[!]
Pin Description
Inpnts
SR
PE
CET
CEP
L
H
H
H
H
X
L
H
H
H
X
X
H
L
X
X
X
H
X
L
Action on the Rising Clock
Edge(s)
Reset (Clear)
Load (Pn-On)
Count (Incremental)
No Charge ~HOld~
No Charge Hold
Name
CEP
Description
Count Enable Parallel Input
CET
Count Enable 1tickle Input
CP
Clock Pulse Input (Active Rising Edge)
SR
Synchronous Reset Input (Active LOW)
P
Parallel Data Inputs
PE
Parallel Enable Input (Active LOW)
0
Flip-Flop Outputs
TC
Terminal Count Output
Maximum Ratings[2,3]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................... -65°C to +150°C
Ambient Temperature with
Power Applied ........................ -65°C to + 135° C
Supply Voltage to Ground Potential ......... -O.5V to +7.0V
DC Input Voltage ........................ -O.5V to +7.0V
DC Output Voltage ...................... -0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) .... 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.5W
Operating Range
Ambient
Temperature
O°C to +70°C
Range
Commercial
Range
CT
Commercial
T,AT
-40°C to +85°C
5V±5%
All
-55°C to +125°C
5V± 10%
Military[4]
Vee
5V±5%
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[6]
Test Conditions
Min.
'lYPJ5]
Max.
Unit
Vec=Min.,loH=-32rnA
Com'l
2.0
Vee=Min., IOH=-15 rnA
Com'l
2.4
3.3
Vee=Min., IOH=-12 rnA
Mil
2.4
3.3
Vee=Min., IOL=64 rnA
Com'l
0.3
0.55
V
Vee=Min., IOL=32 rnA
Mil
0.3
0.55
V
V
V
V
2.0
V
0.8
All inputs
0.2
VIK
Input Clamp Diode Voltage
V ee= Min., IIN= -18 rnA
-1.2
V
II
Input HIGH Current
Vce=Max., VIN=Vee
5
IIH
Input HIGH Current
Vee = Max., VIN=2.7V
±1
IlL
Input LOW Current
Vee=Max., VIN=0.5V
los
Output Short Circuit Current[7]
Vee=Max., VOUT=O.OV
IOFF
Power-Off Disable
Vee=Ov, VOUT=4.5V
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care.
2. Unless otherwise noted, these limits are over the operating free-air
temperature range.
3. Unused inputs must alway.; be connected to an appropriate logic voltage level, preferably either Vcc or ground.
4. TA is the "instant on" case temperature.
5. 1YPical values are at Vcc=S.Ov, TA= +2S'C ambient.
6. This parameter is guaranteed but not tested.
7.
9-34
-0.7
V
V
-60
-120
±1
!lA
!lA
!lA
-225
rnA
±1
!lA
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
I ~YPRESS
CYS4/74FCT163T
Switching Characteristics Over the Operating Range
FCT163T
Military
FCTl63AT
Commercial
Military
Commercial
Description
MinJ12]
Max.
MinJ12]
Max.
MinJ12J
Max.
MinJ12]
Max.
Unit
Fi~
No.3]
tpLH
tpHL
Propagation Delay
CPtoQ
(PE Input HIGH)
2.0
11.5
1.5
11.0
2.0
7.5
1.5
7.2
ns
1,5
tpLH
tpHL
Propagation Delay
CP to TC
(PE Input LOW)
2.0
10.0
1.5
9.5
2.0
6.5
1.5
6.2
ns
1,5
tpLH
tpHL
Propagation Delay
CPtoTC
2.0
16.5
1.5
15.0
2.0
10.8
1.5
9.8
ns
1,5
tpLH
tpHL
Propagation Delay
CETto TC
1.5
9.0
1.5
8.5
1.5
5.9
1.5
5.5
ns
1,5
IS
Set-Up Time,
HIGH or LOW
PtoCP
5.5
4.0
4.5
4.0
ns
4
tH
Hold Time,
HIGH or LOW
PtoCP
2.0
1.5
2.0
1.5
ns
4
tsu
Set-UpTime
HIGH or LOW
PEor SR to CP
13.5
9.5
11.5
9.5
ns
4
tH
Hold Time
HIGH or LOW
PE or SR to CP
1.5
1.5
1.5
1.5
ns
4
tsu
Set-UpTime
HIGH or LOW
CEP or CET to CP
13.0
9.5
11.0
9.5
ns
4
tH
Hold Time
HIGH or LOW
CEP or CET to CP
0
0
0
0
ns
4
tw
Clock Pulse Width
(Load)
HIGH or LOW
5.0
4.0
4.0
4.0
ns
5
tw
Clock Pulse
Width(Count)
HIGH or LOW
8.0
6.0
7.0
6.0
ns
5
Parameter
Notes:
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. See "Parameter Measurement Information" in the General Infonnalion Section.
9-36
CY54/74FCT191T
4-Bit UplDown Binary Counter
Features
• Function, pinout, and drive
compatible with FCT and F logic
• FCT·C speed at 6.2 ns max. (Com'l)
FCT·A speed at 7.8 ns max. (Com'l)
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functions
• Edge.rate control circuitry for
significantly improved noise
characteristics
• Power·off disable feature
• ESD > 2000V
• Matched rise and fall times
• Fnlly compatible with TTL input and
output logic levels
64 rnA (Com'I),
• Sink current
32 rnA (Mil)
32
rnA (Com'I),
Source current
12rnA (Mil)
• Three·State outputs
Functional Description
The FCT191T is a reversible modulo·16
binary counter, featuring synchronous
counting and asynchronous presetting.
The preset allows the FCT191T to be
used in programmable dividers. The
count enable input, terminal count
output, and. ripple clock output make
possible a variety of methods of
implementing multiusage counters. In the
counting modes, state changes are
initiated by the rising edge of the clock.
The outputs are designed with a
power·off disable feature to allow for live
insertion of boards.
Logic Block Diagram
Pin Configurations
LCC
Top View
8@~1~ 8
8
7 6 5 4
0,9
GND
NC
Pa
P2
30,
10
11
12
13
2
1
20
19
P1
NC
Vee
Po
14 1516 17 18
I~ ~li I~ ~
FCT191T-3
DIP/SOIC/QSOP
ThpView
P1
I'!C
TC
00
0,
02
a,
FCT191T-1
Vee
01
Po
00
CP
cr
1m
DID
TC
02
1'[
03
P2
GND '-<..:'-_ _ _9"'" P,
FCT191T-2
Pin Description
Name
CE
Description
Count Enable Input (Active LOW)
CP
Clock Pulse Input (Active Rising Edge)
P
Parallel Data Inputs
PL
Asynchronous Parallel Load Input (Active LOW)
U/D
Up/Down Count Control Input
Q
Flip-Flop Outputs
RC
Ripple Clock Output (Active LOW)
TC
Thrminal Count Output
9-38
~~YPRESS=========================CY==5~~7=4=F=CT=1=9~lT
Power Supply Characteristics
'lest Conditions
'IYpJ6]
Max.
Unit
Icc
Quiescent Power S~pply Current
Vcc=Max., VIN";0.2Y,
VIN",=Vcc-0.2V
0.1
0.2
rnA
I1Icc
Quiescent Power Supply Current ('ITL inputs HIGH)
.
Vcc=Max., VIN=3.4v,[9]
fl =0, Outputs Open
0.5
2.0
rnA
Iceo
Dynamic Power Supply Current[lO]
Vcc=Max., One Bit Thggiing, Preset
Mode, 50% Duty Cycle, Outputs Open,
0.06
0.12
Parameter
Description
mN
MHz
MR~c=SR,
PL=CE= U/D=CP=GND,
VIN"; 0.2V or VIN"'= Vcc-0.2V
Ic
Thtal Power Supply Currend ll ]
Vcc=Max., Preset Mode,
50% Duty Cycle, Outputs Open,
One Bit TQggling at fl =5 MHz,
PL=CE= U/D=CP=GND,
VIN=VCC, VIN=GND
0.4
0.8
rnA
Vcc=Max., Preset Mode,
50% Duty Cycle, Outputs Open,
One Bit Thggling at fl =5 MHz,
VIN=3.4V or VIN=GND
0.7
1.8
rnA
Vcc=Max., Preset Mode,
50% Duty Cycle, Outputs Open,
Four Bits ]?ggling at fl =5 MHz,
PL=CE= U/D=CP=GND,
VIN=VCC, VIN=GND
1.3
2.6[12]
rnA
Vcc=Max., Preset Mode,
50% Duty Cycle, Outputs Open,
Four Bits ]?ggling at fl =5 MHz,
PL=CE=U/D=CP=GND,
VIN=3.4V or VIN=GND
2.3
6.6[12]
rnA
Notes:
9. Per TrL driven input (VIN=3.4V); all other inputs at Vcc or GND.
10. This parameter is not directly testable, but is derived for use in'lbtal
Power Supply calculations.
11. Ic
= IQUIESCENT + IINPUTI + IDYNAMIC
Ic
= Icc+MccDHNT+Icco(fol2 + fINI)
Icc
= Quiescent Current with CMOS input levels
""Icc = Power Supply Current for a TrL HIGH input
(VIN=3.4V)
DH
= Duty Cycle for TrL inputs HIGH
= Number of TIL inputs at DH
= Dynamic Current caused by an input transition pair
(HLHor LHL)
fo
= Clock frequency for registered devices, otherwise zero
fl
= Input signal frequency
NI
= Number of inputs changing at fl
All currents are in milliamps and all frequencies are in megahertz.
12. Values for these conditions are examples of the Icc formula. These
limits are guaranteed but not tested.
9-40
NT
ICCD
~YPRESS~~~~~~~~~~~~~CY~54~/7~4F~C~T~1~91~T
Switching Characteristics Over the Operating Range (continued)
FCT191CT
Military
Description
Parameter
Commercial
MinJ13]
Max.
MinJ13]
Max.
Unit
Fi~
No.4]
tpLH
tpHL
Propagation Delay CP to Q n
1.5
8.4
1.5
6.2
ns
1,5
tpLH
tpHL
Propagation Delay CP to TC
1.5
9.8
1.5
9.4
ns
1,5
tpLH
tPHL
Propagation Delay CP to RC
1.5
7.9
1.5
6.8
ns
1,5
tPLH
tpHL
Propagation Delay CE to RC
1.5
6.4
1.5
6.0
ns
1,5
tPLH
tpHL
Propagation Delay UID to RC
2.5
11.7
1.5
11.0
ns
1,5
tpLH
tpHL
Propagation Delay UID to TC
1.5
6.8
1.5
6.1
ns
1,5
tPLH
tpHL
Propagation Delay Pn to Qn
1.5
8.3
1.5
7.7
ns
1,5
tPLH
tpHL
Propagation Delay PL to Qn
2.0
7.3
2.0
7.2
ns
1,5
tsu
Set-Up Time, HIGH or LOW, P n to PL
4.0
3.5
tH
Hold Time, HIGH or LOW, Pn to PL
1.5
1.0
ns
tsu
Set·Up Time LOW, CE to CP
7.6
7.2
ns
4
tH
Hold Time LOW, CE to CP
0
0
ns
4
tsu
Set-Up Time, HIGH or LOW, UID to CP
8.5
8.0
ns
4
tH
Hold Time, HIGH or LOW, UID to CP
0
0
ns
4
tw
PL Pulse Width LOW
6.0
5.0
ns
5
tw
Clock Pulse Width[6] HIGH or LOW
5.0
4.0
ns
5
tREM
Recovery Time PL to CP
5.0
4.5
ns
6
9-42
4
4
CY54/74FCT240T
CY54/74FCT244T
8-Bit Buffers/Line Drivers
Features
• Function, pinont, and drive
compatible with FCT and F logic
• FCT-C speed at 4.1 ns max. (Com'l)
FCT-A speed at 4.8 ns max. (Com'l)
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functious
• Edge-rate .control circuitry for
significantly improved noise
characteristics
• Power-otT disable feature
• ESD
> 2000V
transmitters/receivers.
The
devices
provide speed and drive capabilities
equivalent to their fastest bipolar logic
counterparts while reducing power
consumption. The input and output
voltage levels allow direct interface with
TTL, NMOS, and CMOS devices without
external components.
The outputs are designed with a
power-off disable feature to allow for live
insertion of boards.
• Matched rise and fall times
• Fully compatible with TTL input and
output logic levels
64 rnA (Com'I),
• Sink current
48 rnA (Mil)
32 rnA (Com'I),
Source current
12 rnA (Mil)
Functional Description
The FCf240T and FCf244T are octal
buffers and line drivers designed to be
employed as memory address drivers,
clock
drivers,
and
bus-oriented
Logic Block Diagram
FCT240T
FCT244T
-"
OE,
v.A
<:lEa
D~-+--~)-~---t--
OlIo
D~
DBo
DA,
DB,
DA,
DB,
OB,
0Aa
D~
DB,
<:lEa
<3-
DBa
o~
N..
....
OB,
llA,
"'.
v
OBo
llA,
D~-4--~~~------
N..
N..
OA,
4
DB,
V
~
v
;,
OB,
O~
DBa
"
FCT240T-1
De"
FCT240T-4
Pin Configurations
DIP/SOICIQSOP
DIP/SOICIQSOP
Top View
LCC
Top View
00, 9
GND 10
DBa 11
0Aa 12
DB, 13
Ol!o
D~
DBa
llA,
OE,
DB,
Vee
llA,
nEa
1415161718
De,
0Aa
DB,
FCT240T·2
FCT24OT-3
9-44
<:lEa
cocoa
OlIo
3
2
1
20
19
Vee
~;;~m<:
<:lEa
8 7 6 5 4
FCT240T
lbpView
Vee
~i~~~
lbpView
LCC
O~
8 7 6 5 4
OB, 9
GND 10
DB, 11
O~ 12
DB, 13
3( OBo
FCT244T
DBo
OA,
2
DAo
1
20
'9
<:lEA
DB,
Vee
OA,
DB,
<:lEa
1415161718
~'l3'l~
O~
""L.:,;'--_.....;.:....... DBa
FCT240T-5
FCT240T·6
CY54/74FCT240T
CY54/74FCT244T
QYPRESS
Capacitance[6]
'lYP. [5]
Max.
Unit
CIN
Input Capacitance
5
10
pF
COUT
Output Capacitance
9
12
pF
Parameter
Description
Power Supply Characteristics
'lYpJ5]
Max.
Unit
Ice
Quiescent Power Supply Current
Vee-Max., VIN,;;0.2V;
VIN '" V ee-0.2V
0.1
0.2
mA
t.Iee
Quiescent Power Supply Current
(TIL inputs)
Vee=Max., VIN=3.4V;[8]
fl =0, Outputs Open
0.5
2.0
mA
IceD
Dynamic Power Supply
Current[9]
Vee = Max., One Input Toggling>-- _
50% Duty Cycle, Outputs Open, OEI =OEz=GND,
VIN,;;0.2Vor VIN'" Vee-0.2V
0.06
0.12
Ie
Thtal Power Supply CurrentflO]
Vee=Max., 50% Duty Cycle,
Outputs Open,
One Bit Thggling at fl = 10 MHz,
OEl=OEz=GND, VIN';;O.2Vor VIN"'Vee-0.2V
0.7
1.4
mA
Vee=Max.,
50% Duty Cycle, Outputs Open,
One Bit Thggling at fl =10 MHz,
OEI =OEz=GND, VIN=3.4V or VIN=GND
1.0
2.4
mA
Vee=Max.,
50% Duty Cycle, Outputs Open,
gjght Bits Thggling at fl =2.5 MHz,
OEl=OEz=GND, VIN';;0.2Vor VIN"'Vee-0.2V
1.3
2.6[11]
mA
Vee-Max.,
50% Duty Cycle, Outputs Open,
gjght Bits Toggling at fl =2.5 MHz,
OEI =0E2=GND, VIN=3.4V or VIN=GND
3.3
10.6[11]
mA
Parameter
Description
Test Conditions
Notes:
8. Per TIL driven input (VIN=3.4V); all other inputs at Vee or GND.
9. This parameter is not directly testable, but is derived for use in Thtal
Power Supply calculations.
10. Ic
= IQUIESCENT + IINPUTS + IDYNAMIC
Ic
= Icc+MccDHNT+IcCD(foI2 + fINI)
lee
= Quiescent Current with CMOS input levels
,',.Icc = Power Supply Current for a TIL HIGH input
(VIN=3.4V)
DH
= Duty Cycle for TIL inputs HIGH
mN
MHz
NT
= Number of TIL inputs at DH
ICCD = Dynamic Current caused by an input transition pair
(HLHorLHL)
to
= Clock frequency for registered devices, otherwise zero
fl
= Input signal frequency
NI
= Number of inputs changing at fl
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the Icc formula. These
limits are gnaranteed but not tested.
9-46
CY54/74FCT240T
CY54/74FCT244T
~
*LrcYPRESS
Ordering Infonnation-FCT240T
4.7
4.8
Commercial
5.1
8.0
Commercial
9.0
Military
Ordering Infonnation-FCT244T
4.6
4.6
5.1
Commercial
6.5
7.0
Document #: 38-00259-A
9-48
CY54/74FCT245T
Maximum Ratings[2, 3)
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Storage Thmperature ................... - 65 ° C to + 1500 C
Ambient Temperature with
Power Applied ........................ -65°C to + 135°C
Supply Voltage to Ground Potential ......... -0.5V to +7.0V
DC Input Voltage ........................ -0.5V to + 7.0V
DC Output Voltage ...................... -0.5V to + 7.0V
DC Output Current (Maximum Sink Current/Pin) .... 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O.5W
Operating Range
Ambient
Temperature
O°C to +70°C
Range
Commercial
Range
CT,DT
Commercial
T,AT
-40°C to +85°C
5V±5%
All
-55°C to + 125°C
5V ± 10%
Military[4)
Vee
5V±5%
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Min.
Test Conditions
'lYPJ5)
Max.
Unit
Vee=Min., IOH=-32 rnA
Com'l
2.0
Vcc=Min., IOH=-15 rnA
Com'l
2.4
3.3
Vcc=Min.,loH=-12mA
Mil
2.4
3.3
V cc=Min., IOL =64 rnA
Com'l
0.3
0.55
V
Vcc=Min.,IoL=48rnA
Mil
0.3
0.55
V
V
V
V
2.0
Vrn
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[6)
All inputs
VIK
Input Clamp Diode Voltage
V cc=Min., lIN = -18 rnA
II
Input HIGH Current
V
0.8
V
0.2
V
-1.2
V
Vcc=Max., VIN=Vcc
5
±1
IIH
Input HIGH Current
Vcc=Max., VIN=2.7V
IlL
Input LOW Current
Vcc=Max., VIN=O.5V
los
Output Short Circuit CurrentP)
Vcc=Max., VOUT=O.OV
IOFF
Power-Off Disable
Vcc=Ov, VouT=4.5V
-0.7
-60
-120
±1
fIA
fIA
fIA
-225
rnA
±1
J-tA
Capacitance[6]
'lYPJ5]
Max.
Unit
CIN
Input Capacitance
5
10
pF
CoUT
Output Capacitance
9
12
pF
Parameter
Description
Notes:
2. Unless otherwise noted, these limits are over the operating free-air
temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vcc or ground.
4. TA is the "instant on" case temperature.
5. Typical values are at Vcc=5.0V, TA=+25"C ambient.
6. This parameter is guaranteed but not tested.
7.
9-50
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques are preferable in order
to minImize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
~YPRESS
CY54/74FCT245T
Switching Characteristics Over the Operating Range
FCT24SAT
FCf24ST
Military
Commercial
Military
Commercial
Fi
Description
MinJ12]
Max.
MinJ12]
Max.
MinJ12]
Max.
MinJ12]
Max.
Unit
No.1\"3]
tpili
tPHL
Propagation Delay
AtoBorBtoA
1.5
7.5
1.5
7.0
1.5
4.9
1.5
4.6
ns
1,3
tPZH
tPZL
Output E.!!able Time
OE or T/R to A or B
1.5
10.0
1.5
9.5
1.5
6.5
1.5
6.2
ns
1,7,8
tpHZ
tpLZ
Output Disable
Time
OE or T/R: to A or B
1.5
10.0
1.5
7.5
1.5
6.0
1.5
5.0
ns
1,7,8
MinJ12]
Max.
MinJ12]
Max.
Unit
Fil\"
No.3]
Parameter
Characteristics Over the
Parameter
Description
tPLH
tpHL
Propagation Delay
AtoBorBtoA
1.5
4.5
1.5
4.1
ns
1,3
tPZH
tpZL
Output Enable Time
OEorT/R: to AorB
1.5
6.2
1.5
5.8
ns
1,7,8
tpHZ
tpLZ
Output D~able Time
OE orT/R toAorB
1.5
5.2
1.5
4.8
ns
1,7,8
Shaded areas contain preliminary
Notes:
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. See "Parameter Measurement Information" in the General Information Section.
9-52
CY54/74FCT257T
Quad 2-Input Multiplexer
• Sink current
Features
• Function, pinout, and drive
compatible with FCT and F logic
• FCT-C speed at 4.3 ns max. (Com'l)
FCT-A speed at 5.0 ns max. (Com'l)
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly improved noise
cbaracteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and
output logic levels
• ESD > 2000V
64 rnA (Com'I),
32 rnA (Mil)
32 rnA (Com'I),
12 rnA (Mil)
Source current
Functional Description
The FCT257T has four identical
two-input multiplexers which select four
bits of data from two sources under the
coutrol of a common data Select input
(S). The 10 inputs are selected when the
Select input is LOW and the 11 inputs are
selected when the Select input is HIGH.
Data appears at the output in true
non-inverted form for the FCT257T.
The FCf257T is a logic implementation
of a four-pole, two position switch where
Logic Block Diagram
I,.
loa
the position of the switch is determined
by the logic levels supplied to the select
input. Outputs are forced to a
high-impedence "OFF" state when the
Output Enable input (DE) is HIGH.
All but one device must be in the
high-impedance state to avoid currents
exceeding the maximum ratings if outputs
are tied together. Design of the Output
Enable signals must ensure that there is
no overlap when outputs of three-state
devices are tied together.
The outputs are designed with a
power-off disable feature to aHow for live
insertion of boards.
Pin Configurations
lOb
10'
10'
I"
I"
s
LCe
DIP/SOIC/QSOP
ThpView
ThpView
B 7 6 5 4
Vb
GND
'9
3
Vee
Va
11c
lOb
Yo
S
NCll
Yd
11d
loa
'0
S
lOa
11a
,NC
12
13
20
19
Vee
OE
14 1516 1718
or:
IOe
11b
IOct
Vb
i1d
GND .....::'--_ _-"'""' Y,
Logic Symbol
loa
FCT257T-3
FCT257T-'
11a
lOb
ilb
Joe
110
IOd
11d
S
OE
Function Table[1]
Pin Description
Name
I
Description
Data Inputs
OE
S
Inputs
Io
11
Y
S
Common Select Input
X
Enable Inputs (Active LOW)
X
X
X
X
OE
L
H
y
Data Outputs
H
L
L
L
L
L
H
X
X
Z
L
H
L
H
H
H
L
L
Output
Note:
1.
9-54
H = HIGH Voltage Level, L = LOW Voltage Level, X = Don't Care,
Z = High impedence (OFF) state
~YPRESS
CY54/74FCT257T
Power Supply Characteristics
Parameter
Description
Thst Conditions
'JYpJ5]
Max.
Unit
Icc
Quiescent Power Supply Current
Vcc=Max., VINsO.2V,
VIN2: Vcc-0.2V
0.1
0.2
rnA
AlcC
Quiescent Power Supply Current (TTL
inputs HIGH)
Vcc=Max., VIN=3.4v,[B]
fl =0, Outputs Open
0.5
2.0
rnA
ICCD
Dynamic Power Supply Currend9]
Vcc=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
OE=GND,
VINsO.2Vor VIN2: Vcc-0.2V
0.06
0.12
Ic
Thtal Power Supply Current[lO]
Vcc=Max.,
50% Duty Cycle, Outputs Open,
One Inputt Toggling at fl = 10 MHz,
OE=GND,
VINsO.2Vor VIN2: Vcc-0.2V
0.7
1.4
rnA
Vcc=M!iX.,
50% Duty Cycle, Outputs Open,
One Input Toggliug at fl = 10 MHz,
OE=GND,
VIN=3.4Vor VIN=GND
1.0
2.4
rnA
Vee-Max.,
50% Duty Cycle, Outputs Open,
Four Bits Thggling at fl =2.5 MBz,
OE=GND,
VINSO.2Vor VIN2:Vcc-0.2V
0.7
1.4[11]
rnA
Vcc=Max.,
50% Duty Cycle, Outputs Open,
Four Bits Thggling at fl =2.5 MHz,
OE=GND,
VIN=3.4Vor VIN=GND
1.7
5.4[11]
rnA
NOles:
8. Per TIL driven input (VIN=3.4V); all other inputs at Vcc or GND.
9. This parameter is not directly testable, but is derived for use in Thtal
Power Supply calculations.
10. Ic
= IQUIESCENT + IINPUTS + IDYNAMIC
Ic
= Icc+AlCCDHNT+ICCO(fo/2 + fINI)
ICC
= Quiescent Current witl\ CMOS input levels
Alcc = Power Supply Current for a TIL HIGH input
(VIN=3AV)
DH
= Duty Cycle for TIL inputs HIGH
mAl
MHz
NT
= Number of TIL inputs at DH
Icco = Dynamic Current caused by an input transition pair
(HLHorLHL)
fo
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
fl
N)
= Number of inputs changing at fl
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of tbe Icc formula. These
limits are guaranteed but not tested.
9-56
~YPRESS
CY54/74FCT257T
Ordering Information
Speed
(ns)
4.3
5.0
5.0
5.8
6.0
7.0
Ordering Code
Package
Name
Package 'JYpe
CY74FCf257CfPC
P1
16-Lead (300-Mil) Molded DIP
CY74FCf257CfQC
Q1
16-Lead (150-Mil) QSOP
CY74FCf257CI'SOC
Sl
16-Lead (300-Mil) Molded SOIC
CY54FCI'257CIDMB
D2
16-Lead (300-Mil) CerDIP
CY54FCf257CI'LMB
L61
20-Pin Square Leadless Chip Carrier
CY74FCf257ATPC
P1
16-Lead (300-Mil) Molded DIP
CY74FCf257ATQC
Q1
16-Lead (ISO-Mil) QSOP
CY74FCf257ATSOC
Sl
16-Lead (300-Mil) Molded sOle
CY54FCf257ATDMB
D2
16-Lead (300-Mil) CerDIP
CY54FCT257ATLMB
L61
20-Pin Square Leadless Chip Carrier
CY74FCT257TPC
PI
16-Lead (300-Mil) Molded DIP
CY74FCf257TQC
Q1
16-Lead (ISO-Mil) QSOP
CY74FCf257TSOC
Sl
16-Lead (300-Mil) Molded SOIC
CY54FCf257TDMB
D2
16-Lead (300-Mil) CerDIP
CY54FCT257TLMB
L61
20-Pin Square Leadless Chip Carrier
Document #: 38-00289-A
9-58
Operating
Range
Commercial
Military
Commercial
Military
Commercial
Military
~YPRESS
CY54/74FCT273T
Maximum Ratings[2,3]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Storage Thmperature ................... -6S 0 Cto +IS0°C
Ambient Thmperature with
Power Applied ........................ -65°C to + 135°C
Supply Voltage to Ground Potential ......... -O.SV to + 7.0V
DC Inp!!t Voltage ........................ -O.5V to + 7.0V
DC Output Voltage ...................... -O.SV to + 7.0V
DC Output Current (Maximum Sink Current/Pin) .... 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O.SW
Operating Range
Range
Commercial
Range
cr
Ambient
Temperatnre
WC to +70°C
Commercial
T,AT
-40°C to +85°C
5V±S%
All
-55°C to + 125°C
SV± 10%
Military[4j
Vee
SV±S%
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
Min.
JYpJ5]
Max.
Unit
Vcc=Min.,IOH=-32rnA
Com'l
2.0
Vcc=Min., IOH=-IS rnA
Com'l
2.4
3.3
Vcc=Min.,IoH=-12mA
Mil
2.4
3.3
Vcc=Min., IOL=64 rnA
Com'l
0.3
0.55
V
Vcc=Min.,loL=32rnA
Mil
0.3
0.55
V
V
V
V
2.0
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[6]
All inputs
0.2
VIK
Input Clamp Diode Voltage
Vcc=Min.,IIN=-18rnA
-0.7
II
Input HIGH Current
IIH
IlL
0.8
V
V
-1.2
V
Vcc=Max., VIN=Vcc
5
Input HIGH Current
Vcc=Max., VlN=2.7V
±1
Input LOW Current
Vcc=Max., VlN=O.5V
los
Output Short Circuit Current[7]
Vcc=Max., VOVT=O.OV
IOFF
Power-Off Disable
Vcc=Ov, VOVT=4.5V
-60
-120
±1
fAA
fAA
fAA
-225
rnA
±1
fAA
Capacitance[6]
JYpJ5]
Max.
Unit
CIN
Input Capacitance
5
10
pF
COUT
Output Capacitance
9
12
pF
Parameter
Description
Notes:
2. Unless otherwise noted, these limits are over the operating free-air
temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
4. TA is the "instant on" case temperature.
S. 1.ypical values are at Vcc=S.Ov, TA = + 25' C ambient.
6. This parameter is guaranteed but not tested.
7.
9-60
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus andlor sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be .performed last.
CY54/74FCT273T
Switching Characteristics Over the Operating Range
FCf273T
Military
FCT273AT
Commercial
Military
Commercial
Description
Min'p2]
Max.
MinJ12]
Max.
MinJ12]
Max.
MinJ12]
Max.
Unit
Filt
No.3]
tpill
tpHL
Propagation Delay
Clock to Output
2.0
15.0
2.0
13.0
2.0
8.3
2.0
7.2
ns
1,5
tpLH
tpHL
~agation
Delay
MR to Output
2.0
15.0
2.0
13.0
2.0
8.3
2.0
7.2
ns
1,6
ts
Set-Up Time HIGH
or LOW D to Clock
3.5
2.0
2.0
2.0
ns
4
tH
Hold Time HIGH or
LOW D to Clock
2.0
1.5
1.5
1.5
ns
4
tw
Clock Pulse Width
HIGH or LOW
7.0
6.0
6.0
6.0
ns
5
tw
MR Pulse Width
LOW
7.0
6.0
6.0
6.0
ns
6
tREc
Recovery Time MR
to Clock
5.0
2.0
2.5
2.0
ns
6
Parameter
FCf273CT
Military
Parameter
Description
Commercial
MinJ12]
Max.
MinJ12]
Max.
Unit
Fi
No.1t3]
tpLH
tpHL
Propagation Delay Clock to Output
2.0
6.5
2.0
5.8
ns
1,5
tpLH
tpHL
Propagation Delay MR to Output
2.0
6.8
2.0
6.1
ns
1,6
4
ts
Set-Up Time HIGH or LOW D to Clock
2.0
2.0
ns
tH
Hold Time HIGH or LOW D to Clock
1.5
1.5
ns
4.
tw·
Clock Pulse Width HIGH or LOW
6.0
6.0
ns
5
tw
MR Pulse Width LOW
6.0
6.0
ns
6
tREC
Recovery Time MR to Clock
2.5
2.0
ns
6
Notes:
12. Minimum limits are guaranteed but nottested on Propagation Delays.
13. See "Parameter Measurement Information" in the General Information Section.
9-62
CY54/74FCT373T
CY54/74FCT573T
8-Bit Latches
Features
• Function, pinout and drive compatible
witb the fastest bipolar logic
• FCr-C speed at 4_2 ns max. (Com'l)
FCT-A speed at 5.2 DS max. (Com'l)
• Reduced VOH (typically = 3.3V)
versions of ~quivalentFCT functions
• Edge-rate control circuitry for
sil!nificantly improved noise
cliaraCteris"cs
• Power-off disable feature
• Matched rise and fall times
• ESD > 2000V
• Fully compatible witb TTL input and
output logic levels
64 mA (Com'I),
• Sink Current
32mA(MiI)
32 mA (Com'I),
Source Current
12mA (Mil)
Functional Description
The FCT373T and FCT573T consist of
eight latches with three-state outputs for
bus organized system applications. When
latch enable (LE) is HIGH, the flip-flops
appear transparent to the data. Data tbat
meets tbe required set-up times are
latched when LE transitions from HIGH
to Ww. Data appears on the bus when
the output enable (GE) is LOW. When
output enable is HIGH, the bus output is
in tbe high impedance state. In this mode,
data may be entered into the latches. The
FCI'573T is identical to FCT373T except
for flow-through pinout, which simplifies
board design.
The outputs are designed with a
power-off disable feature to allow for live
insertion of boards.
Logic Block Diagram
FCT373T·1
Pin Configurations
D1P/SOIC/QSOP
OE
Vee
rf880c
00
7 6 5 4
LE
A.
0_
9
10
11
12
13
Do
00
FCT373T
20
19
OE
Vee
07
1415161718
-~
r!!' 0'" cT r!frS
FCT373T·5
Top View
LCC
Top View
8
03
GND
D1P/SOIC/QSOP
Top View
LCC
Top View
OE
Vee
07
8~ri8~
Do
00
Do
07
~v7v6v54
D,
0,
0,
D.
D,
D2
Do
D3
02
03
UE
D_
O_
Vee
D.
A.
00
D.
o.
D7
GND
0,
LE
a,
o.
02
A.
D2
D.
D3
D7
GND
LE
0,
o.
D,
0,
0,
GND
LE
9
10
11
12
13
3
2
FCT573T 1
20
19
1415161718/
Cf'o" O'2001V
(per MIL-STD-883, Method 3015)
Operating Range
Ambient
Temperature
O°Cto +70°C
Range
Commercial
Range
CT,DT
Commercial
T,AT
-40°C to +85°C
5V±5%
All
-55°C to + 125°C
5V ± 10%
Military[4J
Test Conditions
Min.
lYPJ5J
Vee
5V±5%
Max.
Unit
Vee=Min., IOH=-32 rnA
Com'l
2.0
Vee=Min., IOH=-15 rnA
Com'l
2.4
3.3
Vee=Min., IOH=-12 rnA
Mil
2.4
3.3
Vee=Min., IOL=64 rnA
Com'l
0.3
0.55
V
Vee=Min., IOL=32 rnA
Mil
0.3
0.55
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[6J
All inputs
VIK
Input Clamp Diode Voltage
Vcc=Min., IJN=-18 rnA
II
Input HIGH Current
IIH
Input HIGH Current
IlL
IOZH·
IOZL
V
V
V
2.0
V
0.8
0.2
V
-1.2
V
Vee=Max., VJN=Vee
5
Vee=Max., VJN=2.7V
±1
Input LOW Current
Vce=Max., VJN=O.5V
±1
Off State HIGH-Level Output
Current
Vee = Max., VOUT = 2.7V
10
tJA
tJA
tJA
tJA
Off State LOW-Level
Output Current
Vee = Max., VOUT = O.5V
-10
tJA
los
Output Short Circuit Current(7J
Vee=Max., VOUT=O.OV
-225
rnA
IOFF
Power-Off Disable
±1
tJA
Vee=Ov, VOUT=4.5V
Notes:
1. H = HIGH Voltage Level.
L = WW Voltage Level
X = Don't Care
Z = HIGH Impedance
S = WW-to-HIGH clock transition
2. Unless otherwise noted, these limits are over the operating free-air
temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
4. TA is the "instant on" case temperature.
5.
6.
7.
9-70
-0.7
V
-60
-120
1YPical values are at Vcc=5.0V, TA=+25'C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parameters tests. In any sequence of
parameter tests, los tests should be performed last.
CY54/74FCT374T
CY54/75FCT574T
~YPRESS
Switching Characteristics Over the Operating Rangd 12]
FCT374T/FCTS74T
Military
Parameter
Description
FCT374AT/FCTS74AT
Commercial
Military
Commercial
MinJ13]
Max.
MinJ13]
Max.
MinJ13]
Max.
MinJ13]
Max.
Unit
Fi~
No.4]
tpLH
tpHL
Propagation Delay
Clock to Output
2.0
11.0
2.0
10.0
2.0
7.2
2.0
6.5
ns
1,5
tpZH
tpZL
Output Enable Time
1.5
14.0
1.5
12.5
1.5
7.5
1.5
6.5
ns
1,7,8
tPHZ
tpLZ
Output Disable Time
1.5
8.0
1.5
8.0
1.5
6.5
1.5
5.5
ns
1,7,8
ts
Set-UpTime
HIGH or LOW
DtoCP
2.0
2.0
2.0
2.0
ns
4
tH
Hold time
HIGH or LOW
DtoCP
1.5
1.5
1.5
1.5
ns
4
tw
Clock Pulse
Width[15] HIGH or
LOW
7.0
7.0
6.0
5.0
ns
5
FCT374CT/FCfS74CT
Fi
No.~4]
MinJ13]
Parameter
tpLH
tpHL
Propagation
tpZH
tpZL
Output Enable Time
1.5
Output Disable Time
1.5
Notes:
12. AC Characteristics guaranteed with CL =50 pF as shown in Figure 1 of
the "Parameter Measurement Information" in the General Information Section.
13. Minimum limits are guaranteed but not tested on Propagation Delays.
2.0
5.2
ns
1,5
6.2
1.5
5.5
ns
1,7,8
5.7
1.5
1,7,8
14. See "Parameter Measurement Information" in the General Informa-
tion Section.
15. With one data channel toggling, tW(L) =tw(H) =4.0 ns and
t,=tf=1.0 ns.
9-72
CY54/74FCT377T
8-Bit Register
Features
• Function, pinout and drive compatible
with FCT and F logic
• FCT·C speed at 5.2 ns max. (Com'l)
FCT·A speed at 7.2 ns max. (Com'l)
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functions
• Edge·rate control circuitry for
significantly improved noise
characteristics
• Power·off disable feature
• Matched rise and fall times
• ESD > 2000V
• Fully compatible with TTL input and
output logic levels
64 mA (Com'I),
• Sink current
32mA(MiI)
32 mA (Com'I),
Source current
12mA (Mil)
• Clock Enable for address and data
syuchronization application
• Eight edge· triggered D flip.f1ops
Functional Description
The FCT371f has eight triggered D-type
flip-flops with individual D inputs. The
common buffered clock inputs (CP) loads
all flip-flops simultaneously when the
Clock Enable (CE) is Law. The register
is fully edge-triggered. The state of each
D input, one set-up time before the
LOW-to-HIGH clock transition, is
transferred to the corresponding
flip-flop's a output. The CE input must
be stable only one set-up time prior to the
LOW-to-HIGH clock transition for
predictable operation.
The outputs are designed with a
power-off disable feature to allow for live
insertion of boards.
Logic Block Diagram
0,
00
Pin Configurations
C')
0,
GND
CP
o.
D,
8
07
FCT377T·l
DlP/SOIC/QSOP
Top View
CE
Vee
00
00
07
D7
7 6 5 4
Do
D,
C'II
o.
Logic Symbol
LCC
Top View
t\I .... .-
ceo
o.
0,
9
10
11
12
13
3
2
20
19
Do
D.
CE
a,
o.
a.
Vee
D,
D.
07
Do
D.
00
1415161718
r!!'o"'r!'Cfr!i"
FCT377T-2
0,
a,
GND
CP
CE
a.
FCT3m·4
CP
FCT377T-3
9-74
~YPRESS
CY54/74FCT377T·
Capacitance[6]
'lYPJ5]
Max.
Unit
CIN
Input Capacitance
5
10
pF
COUT
Output Capacitance
9
12
pF
Parameter
Description
Power Supply Characteristics
'J.YpJ5]
Max.
Unit
Icc
Quiescent Power Supply Current
Vee=Max., VIN,,0.2V,
VIN2: Vee-0.2V
0.1
0.2
mA
alec
Quiescent Power Supply Current (TIL
inputs HIGH)
Vee=Max., VIN=3.4v,[8]
fl =0, Outputs Open
0.5
2.0
rnA
IceD
Dynamic Power Supply Current[9]
Vee=Max., One Bit Toggling,
50% Duty Cycle, Outputs Open,
CE=GND,
VIN"O.2VorVIN2: Vee-0.2V
0.06
0.12
Ie
Thtal Power Supply Current[lO]
Vcc=Max., fo=lO MHz,
50% Duty Cycle, Outputs Open,
One Bit Thggling at fl =5 MHz,
CE=GND,
VIN,,0.2Vor VIN2:Vee-0.2V
0.7
1.4
rnA
Vee=Max., fo=lO MHz,
50% Duty Cycle, Outputs Open,
One Bit Toggling at fl =5 MHz,
CE=GND,
VIN=3.4Vor VIN=GND
1.2
3.4
rnA
Vee-Max., fo=10 MHz,
50% Duty Cycle, Outputs Open,
§!ght Bits Thggling at fl =2.5 MHz,
CE=GND,
VIN"O.2Vor VIN2: Vee-0.2V
1.6
3.2[11]
rnA
Vee=Max., fo=10 MHz,
50% Duty Cycle, Outputs Open,
§!ght Bits Toggling at fl =2.5 MHz,
CE=GND,
VIN=3.4Vor VIN=GND
3.9
12.2[11]
rnA
Parameter
Description
'lest Conditions
Notes:
Per TIL driven input (VJN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total
Power Supply calculations.
10. Ie
= IQUIESCENT + IINPUTS + IDYNAMIC
Ie
= Iee+AIeeDHNT+Ieco(fol2 + fINI)
Icc
= Quiescent Current with CMOS input levels
Alec = Power Supply Current for a TIL HIGH input
(VIN=3.4V)
DH
= Duty Cycle for TTL inputs HIGH
8.
= Number of TIL inputs at DH
= Dynamic Current caused by an input transition pair
.
(HLH or LHL)
fo
= Clock frequency for registered devices, otherwise zero
fl
= Input signal frequency
.
= Number of inputs changing at fl
NI
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the Icc formula. These
limits are guaranteed but not tested.
9-76
NT
InN
MHz
ICeD
CY54/74FCT377T
Ordering Information-FCT377T
Speed
(ns)
S.2
S.5
7.2
8.3
13.0
lS.0
Ordering Code
Package
Name
Package 'fYpe
CY74FCf377CTPC
PS
20-Lead (300-Mil) Molded DIP
CY74FCT377CTQC .
QS
20-Lead (lS0-Mil) QSOP
CY74FCT377CTSOC
SS
20-Lead (3OO-Mil) Molded SOIC
CYS4FCT377CTDMB
D6
20-Lead (300-Mil) CerDIP
CYS4FCf377CTLMB
L61
20-Pin Square Leadless Chip Carrier
CY74FCT377ATPC
PS
20-Lead (300-Mil) Molded DIP
CY74FCT377ATQC
QS
20-Lead (lS0-Mil) QSOP
CY74FCT377ATSOC
SS
20-Lead (300-Mil) Molded SOIC
CYS4FCf377ATDMB
D6
20-Lead (300-Mil) CerDIP
CYS4FCT377ATLMB
L61
20-Pin Square Leadless Chip Carrier
CY74FCT377TPC
PS
20-Lead (300-Mil) Molded DIP
CY74FCf377TQC
QS
ZO-Lead (lS0-Mil) QSOP
CY74FCT377TSOC
S5
ZO-Lead (300-Mil) Molded SOIC
CYS4FCT377TDMB
D6
20-Lead (300-Mil) CerDIP
CY54FCT377TLMB
L61
ZO-Pin Square Leadless Chip Carrier
Document #: 38-00279-A
9-78
Operating
Range
Commercial
Military
Commercial
Military
Commercial
Military
CY54/74FCT399T
Maximum Ratings[2, 3]
.
(Above which the useful life may be impaired. For user guidelines,
not tested.)
StQrage Temperature ............ , ...... -65°C to + 150°C
Ambient 'Thmperature with
Power Applied ..... , .................. -65°C to + 135°C
~upply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC lnput Voltage ........................ -0.5Vto +7.0V
Dc::: Output Voltage ............ , ......... -O.5V to + 7.0V
DC Output Curreht (Maximum Sink Current/Pin) .... 120 rnA
Power Dissipation.. .. .. . .. .. . . .. .. . . .. . . .. .. .. . ... O.5W
Electrical Characteristics OVer the Operating RaDge
Parameter
Description
Voil:
VOL
Output mGH Voltage
Output LOW Voltage
Static Discharge Voltage .......•................ >2001V
(per MIL-STD-883, Method 3015)
Operating Range
Ambient
Temperature
O°Cto +70°C
Range
Commercial
Range
Commercial
T,AT
-40°C to +85°C
5V±5%
All
-55°C to +l25°C
5V± 10%
ct
Military[4]
Test Conditions
Min.
" Vee
5V±5%
lYp,!5]
Max.
Unit
Vce=Min.,loH=-32rnA
Com'l
2.0
V
Vee-Min., IOH- -15 rnA
Com'l
2.4
3.3
Vce= Min., IOH= ~ 12 rnA
Mil
2.4
3.3
Vcc=Min., IOL=64 rnA
Com'l
0.3
0.55
V
Vcc=Min., IOL=32 rnA.
Mil
0.3
0.55
V
V
V
2.0
VIH
Input mGH Voltage
VIL
Input LOW Voltage
V
VH
Hysteresis[6]
All inputs
0.2
VIK
Input Clamp Diode Voltage
V cc=Min., IIN= -18 rnA
-0.7
II
Input HIGH Current
lill
Input mGH Current
0.8
V
V
-1.2
V
Vcc=Max., VIN=Vcc
5
Vcc=Max., VIN=2.7V
±1
IlL
Input LOW Current
Vcc=Max., VIN=0.5V
los
Output Short Circuit Current[7]
Vcc=Max., VOUT=O.OV
IOFF
Power-Off Disable
Vcc=Ov, VOUT=4.5V
-60
-120
I
±1
!lA
!lA
!lA
-225
rnA
±1
!lA
Capacita.nce[6]
Patameter
Description
lYp,!5]
Max.
Unit
qN
Input Capacitance
5
10
pF
COUT
Output Capacitance
9
12
pF
Not••:
2. Unless otherwise noted, these limits are over the operating free-air
temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
4. TA is the "instant on" case temperature.
5. 1YJ>icai values are at Vcc=S.OV; TA=+25·C ambient.
6. This parameter is guaranteed but not tested.
7.
9-80
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques is preferable in order to
minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the
chip temperature well above normal and thereby cause invalid
readings in other parametric tests. In any sequence of parameter tests,
los tests should be performed last.
.iI&PRESS
CY54/74FCT399T
Switching Characteristics Over the Operating Range
FCT399T
Military
FCT399AT
Commercial
Military
Commercial
Description
MinJ12]
Max.
MinJ12]
Max.
MinJ12]
Max.
MinJ12]
Max.
Unit
Fill:
No.3]
tpili
tpHL
Propagation Delay
CPtoQ
3.0
11.5
3.0
10.0
2.5
7.5
2.5
7.0
ns
1,5
ts
Set-UpTime
HIGH or LOW
In to CP
4.5
3.5
4.0
3.5
ns
4
tH
Hold Time
HIGH or LOW
In to CP
1.5
1.0
1.0
1.0
ns·
4
ts
Set-UpTime
HIGH or LOW
Sto CP
9.5
8.5
9.0
8.5
ns
4
tH
Hold Time
HIGH or LOW
StoCP
0
0
0
0
ns
4
tw
Clock Pulse Width[6]
HIGH or LOW
7.0
5.0
6.0
5.0
ns
5
Parameter
FCT399CT
Military
Commercial
MinJ12]
Max.
MinJ12]
Max.
Unit
Fill:
No.3]
Propagation Delay CP to Q
2.5
6.6
2.5
6.1
ns
1,5
ts
Set-Up Time, HIGH or LOW; In to CP
4.0
3.5
ns
4
tH
Hold Time, HIGH or LOW; In to CP
1.0
1.0
ns
4
ts
Set-Up Time, HIGH or LOW; S to CP
9.0
8.5
ns
4
tH
Hold Time, HIGH or LOW; S to CP
0
0
ns
4
tw
Clock Pulse Width[6] HIGH or LOW
6.0
5.0
ns
5
Parameter
tpLH
tpHL
Description
Notes:
12. Minimum limits are guaranteed but nottested on Propagation Delays.
13. See "Parameter Measurement Information" in the General Information Section.
9-82
CY54/74FCT480T
Dual 8-Bit Parity Generator/Checker
Features
• Function, pinout and drive compatible
with FCT and F logic
• FCT-A speed at 7.5 ns max. (Com'l)
FCT-B speed at 5.6 ns max. (Com'l)
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly improved uoise
characteristics
• Power-off disable feature
• Matched rise and fall times
• ESD > 2000V
• Fully compatible with TTL input and
output logic levels
64 rnA (Com'I),
• Sink Current
32 rnA (Mil)
32 rnA (Com'I),
Source Current
12rnA (Mil)
• 1\vo 8-bit parity generator/checkers
• Open drain Active LOW parity error
output
• Expandable for larger word widths
Functional Description
The FCT480T is a high-speed dual 8-bit
parity generator/checker. Each parity
generator/checker accepts eight data bits
and one parity bit as inputs, and generates
a sum and parity error output. The
FCT480T can be used in ODD parity
systems. The parity error output is
open-drain, designed for easy expansion
of the word width by a wired-OR
connection of several FCT480T type
devices. Since additional logic is not
needed, the parity generation or checking
times remain the same as for an individual
FCT480T Oevice.
The outputs are designed with a
power-off disable feature to aJlow for live
insertion of boards.
Logic Block Diagram
PAR,
-------------1-..
PAR,
-------------I....J
FCT4BOT-,
Pin Configurations
DIP/SOIC/QSOP
Top View
LCC
Top View
CHK/GEIII
111098765
=, ,.'2
=,
ERROR
GND
NC
PAR2
'5
'6
17
'B
•
3
2
'3
,
C,
6,
A,
NC
2~ Vee
A,
2~ 6,
C\I
Nt)
C\I N
J: C!:J u. ZW
Vee
81
A2
C1
82
D1
C2
E1
F1
D2
E2
G1
F2
Hi
G2
PAR1
H2
CHK/GEIII
PAR,
=,
1920212223 24 25 26
C\I
A1
C\I
PAR,
co
ERROR
L.:'--_'--:..r-
=,
FCT480T-3
FCT.BOT-2
9-84
CY54/74FCT480T
z:u rcYPRESS
Electrical Characteristics Over the Operating Range
Description
Parameter
VOH
Output HIGH Voltage
Test Conditions
Min.
'lYp.l4]
Vcc=Min.,loH=-32mA
Com'l
2.0
Vee=Min., IOH=-15 mA
Com'l
2.4
3.3
Vee=Min.,loH=-12mA
Mil
2.4
3.3
Vee=Min., IOL =64 mA
Com'l
Vcc=Min., IOL =32 mA
Mil
Max.
Unit
V
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[5]
All inputs
0.2
VIK
Input Clamp Diode Voltage
Vee=Min., IIN= -18 mA
-0.7
II
Input HIGH Current
IIH
Input HIGH Current
V
V
0.3
0.55
0.3
0.55
V
V
2.0
V
0.8
V
-1.2
V
Vee=Max., VIN=Vee
5
Vee=Max., VIN=2.7V
±1
V
IlL
Input LOW Current
Vee=Max., VIN=0.5V
±1
IOZH
Off State HIGH-Level Output
Current
Vee = Max., VOUT = 2.7V
10
!lA
!lA
!lA
!lA
IOZL
Off State LOW-Level
Output Current
Vee = Max., VOUT = O.5V
-10
!lA
los
Output Short Circuit Current[6]
Vee=Max., VOUT=O.OV
-225
mA
IOFF
Power-Off Disable
Vee=Ov, VOUT=4.5V
±1
!lA
-60
-120
Capacitance[5]
'lYp.l4]
Max.
Unit
CIN
Input Capacitance
5
10
pF
COUT
Output Capacitance
9
12
pF
Parameter
Description
Notes:
4. Typical values are at Vcc=5.0V, TA=+25°C ambient.
5. This·parameter is guaranteed but not tested.
6. Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques are preferable in order
9-86
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby.cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
~YPRESS
CY54/74FCT480T
Ordering Information
Speed
(n8)
5.6
7.0
7.5
9.5
13.0
17.0
Ordering Code
Package
Name
Package 1YPe
CY74FCT480BTPC
P13/13A
24-Lead (300-Mil) Molded DIP
CY74FCT480BTQC
Q13
24-Lead (lS0-Mil) QSOP
CY74FCT480BTSOC
S13
24-Lead (3OO-Mil) Molded SOlC
CYS4FCT480BTDMB
DI4
24-Lead (300-Mil) CerDIP
CYS4FCT480BTLMB
L64
28-Square Leadless Chip Carrier
CY74FCT480ATPC
P13/13A
24-Lead (300-Mil) Molded DIP
CY74l'CT480ATQC
Q13
24-Lead (lSO-Mil) QSOP
CY74FCT480ATSOC
S13
24-Lead (300-Mil) Molded SOlC
CYS4FCT480ATDMB
D14
24-Lead (300-Mil) CerDIP
CY54FCT480ATLMB
L64
28-Square Leadless Chip Carrier
CY74FCT480TPC
P13/13A
CY74FCT480TQC
Q13
24-Lead (lS0-Mil) QSOP
24-Lead (300-Mil) Molded DIP
CY74FCT480TSOC
S13
24-Lead (3OO-Mil) Molded SOlC
CYS4FCT480TDMB
D14
24-Lead (300-Mil) CerDIP
CYS4FCT480TLMB
L64
28-Square Leadless Chip Carrier
Document#: 38-oo281-A
9-88
Operating
Range
Commercial
Military
Commercial
Military
Commercial
Military
CY54/74FCT540T
CY54/74FCT541T
Function Table FCT540T[1]
Function Table FCT541T[1]
Inputs
Inputs
OEA
OED
D
Output
OEA
OED
D
Output
L
L
H
L
L
H
L
H
H
L
Z
L
L
H
L
H
X
L
H
X
L
L
H
Z
Maximum Ratings[2,3]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ >2001 V
(per MIL·STD·883, Method 3015)
Storage Temperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied ........................ -65°C to + 135°C
Supply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC Input Voltage ........................ -0.5V to + 7.0V
DC Output Voltage ...................... -0.5V to + 7.0V
DC Output Current (Maximum Sink Current/Pin) .... 120 rnA
Power Dissipation. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. O.5W
Operating Range
Ambient
'lemperature
O°Cto +70°C
Range
Commercial
Range
CT,DT
Commercial
T,AT
-40°C to +85°C
5V±5%
All
-55°C to +l25°C
5V ± 10%
Military[4]
Vee
5V±5%
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
'lest Conditions
Min.
'JYpJ5]
Max.
Unit
V
Vcc=Min.,IoH=-32rnA
Com'l
2.0
V cc=Min., IOH= -15 rnA
Com'l
2.4
3.3
Vcc=Min.,IoH=-12rnA
Mil
2.4
3.3
Vcc=Min.,IoL=64rnA
Com'l
0.3
0.55
V
Vcc=Min., IOL=48 mA
Mil
0.3
0.55
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[6]
All inputs
0.2
VIK
Input Clamp Diode Voltage
Vcc=Min., IIN=-18 rnA
-0.7
II
Input HIGH Current
IIH
IlL
IOZH
V
V
2.0
V
0.8
V
V
-1.2
V
Vcc=Max., VIN=Vcc
5
Input HIGH Current
Vcc=Max., VIN=2.7V
±1
Input LOW Current
Vcc=Max., VIN=0.5V
±1
Off State HIGH·Level Output
Current
Vcc=Max., VOUT=2.7V
10
fAA
fAA
fAA
fAA
IOZL
Off State LOW·Level
Output Current
Vcc= Max., VOUT=O.5V
-10
fAA
los
Output Short Circuit Current[7]
Vcc=Max,. VOUT=O.OV
-225
mA
IOFF
Power·Off Disable
V cc=Ov, VOUT=4.5V
±1
fAA
Noles:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedence
2. Unless otherwise noted, these limits are over the operating free·air
temperature range.
3. Unused inputs must always be connected to an appropriate logic volt·
age level, preferably either Vee or ground.
4. TA is the "instant on" case temperature.
-60
-120
5. 1YPical values are at Vcc=5.0V, TA=+ZS'C ambient.
6. This parameter is guaranteed but not tested.
7. Not more than one output should be shorted at a time. Duration of
short shonld not exceed one second. The use of high·speed test
apparatus and/or sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chlp temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parametric tests, lOS tests should be performed last.
9-90
CY54/74FCT540T
CY54/74FCT541T
I ~YPRESS
Switching Characteristics Over the Operating Range
FCTS4OT/FCTS41T
Military
FCTS40AT/FCTS41AT
Commercial
Military
Commercial
Fi~
Description
Min.l 12]
Max.
Min.l 12]
Max.
Min.l 12]
Max.
Min.l 12]
Max.
Unit
No.3]
tpili
tpHL
Propagation Delay
Data to Output
(FCf540)
1.5
9.5
1.5
8.5
1.5
5.1
1.5
4.8
ns
1,2
tpili
tpHL
Propagation Delay
Data to Output
(FCT541)
1.5
9.0
1.5
8.0
1.5
5.1
1.5
4.8
ns
1,3
tpZH
tpZL
Output Enable Time
1.5
10.5
1.5
10.0
1.5
6.5
1.5
6.2
ns
1,7,8
tpHz
tpLZ
Output Disable
Time
1.5
10.0
1.5
9.5
1.5
5.9
1.5
5.6
ns
1,7,8
Parameter
FCTS40CT/FCTS41CT
Parameter
Description
Fi
MinJ12]
Max.
Min.l 12]
Max.
Unit
No.~3]
tpili
tpHL
Propagation Delay
Data to Output (FCf540)
1.5
4.7
1.5
4.1
ns
1,2
tpLH
tpHL
Propagation Delay
Data to Output (FCT541)
1.5
4.6
1.5
4.1
ns
1,3
tpZH
tPZL
Output Enable Time
1.5
6.5
1.5
5.8
ns
1,7,8
tpHZ
tpLZ
Output Disable Time
1.5
5.7
1.5
5.2
ns
1,7,8
Notes:
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. See "Parameter Measurement Information" in tbe General Information section.
9-92
CY54/74FCT543T
8-Bit Latched Registered Transceiver
Features
64 rnA (Com'I),
48 rnA (Mil)
32 rnA (Com'I),
12rnA (Mil)
• Separation controls for data flow in
each direction
• Back to back latches for storage
• Sink current
• Fnnction, pinont, and drive
compatible with FCT and F logic
• FCT-C speed at 5.3 ns max. (Com'l)
FCT-A speed at 6.5 ns max. (Com'l)
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly improved noise
characteristics
• Power-off disable feature
• Matched rise and fall times
• Fnlly compatible with TTL inpnt and
outpnt logic levels
• ESD > 2000V
Source current
Functional Description
The FCTS43T octal latched transceiver
contains two sets of eight D-type latches
with separate latch enable (I:EAB,
LEBA» and output enable (OEAB,
OEBA cOntrols for each set to permit
independent control of inputting and
outputting in either direction of data flow.
For data flow from A to B, for example,
the A-to-B enable (CEAB) input must be
Logic Block Diagram
Functional Block Diagram
r----------,
Detail AI
I
I
I
1
I
I
I
D Q
Ao
LOW in order to enter data from A or to
take data from B, as indicated in the truth
table. With CEAB LOW, a LOW signal
on the A-to-B latch enable (LEAB) input
makes the A-to-B latches transparent; a
subseqXBt LOW-to-HIGH transition of
the LE
signal puts the A latches in the
storage mode and their output no longer
change with the A inputs. With CEAB
and OEAB both LOW, the three-stage B
output buffers are active and reflect the
data present at the output of the A
latches. Control of data from B to A is
similar, but uses "CEAB, I:EAB, and
OEAB inputs.
The outputs are designed with a
power-off disable feature to allow for live
insertion of boards.
Bo
.J
A,
_..r---"'---'---'---..J......._
Ao
Ao
A"
B,
~
~
Detail A x 7
FCT543T·2
B,
Aa
~
A;,
~
Pin Configurations
Lee
£££~<~~<
CEAl!
=
FCT543T·1
DIP/SOIClQSOP
Top View
Top View
0El\B
1:EIlA
0EllA
1110 9 8 7 6 5
A,
CEAl!
GND
NC
0El\B
I:EAB
a,
12
13
14
'5
16
17
18
Ao
4
3
2
0EllA
1:EIlA
26
Vee
,
27
1920 212223 24 25 26
NC
=
Bo
Ao
A,
Ao
Aa
A"
Aa
A;,
A,
FCT543T-3
CEAl!
GND
Vee
=
Bo
B,
B,
B3
B,
B,
~
a,
I:EAB
=
FCT543T-4
9-94
CY54/74FCT543T
arcYPRESS
Electrical CharaCteristics Over the Operating Range
Parameter
VOH
VOL
Thst Conditions
Description
Output HIGH Voltage
Output LOW Voltage
Min.
'JYpJ7]
Max.
Unit
Vcc=Min., IOH= -32 rnA
Com'l
2.0
Vee=Min., IOH=-15 rnA
Com'l
2.4
3.3
V
V
Vee=Min., IOH=-12 rnA
Mil
2.4
3.3
V
Vee=Min., IOL =64 rnA
Com'l
0.3
0.55
V
Vee=Min.,loL=48rnA
Mil
0.3
0.55
V
VIH
Input HIGH Voltage
2.0
VIL
Input LOW Voltage
V
VH
Hysteresis[8]
All inputs
0.2
VIK
Input Clamp Diode Voltage
Vee=Min., IIN=-18 rnA
-0.7
IIH
Input HIGH cUrrent
Vee=Max., VIN=Vee
IIH
Input HIGH Current
Vee=Max., VIN=2.7V
±1
IlL
Input LOW Current
Vee=Max., VIN=0.5V
±1
IOZH
Off State HIGH-Level Output
Current
Vee = Max., VOUT = 2.7V
IOZL
Off State LOW-Level
Output Current
Vee = Max., VOUT = 0.5V
los
Output Short Circuit Currentl9]
Vee=Max., VOUT=O.OV
IOFF
Power-Off Disable
Vee=Ov, VOUT=4.5V
0.8
-60
-120
V
V
-1.2
V
5
10
!LA
!LA
!LA
!LA
-10
!LA
-225
rnA
±1
!LA
Capacitance[8]
'J.yp.[7]
Max.
Unit
CIN
Input Capacitance
5
10
pF
COUT
Output Capacitance
9
12
pF
Parameter
Description
Notes:
7. Typical values are at Vcc=S.ov, TA=+25°C ambient.
8. This parameter is guaranteed but not tested.
9. Not more than one output shouid be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques are preferable io order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
iovalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
9-96
CY54/74FCT543T
Switching Characteristics Over the Operating Range
FCT543T
Military
FCT543AT
Commercial
Military
Commercial
Description
MinJ14]
Max.
MinJ14]
Max.
MinJ14]
Max.
MinJ14]
Max.
Unit
Fi~
No.5]
tpLH
tPilL
Propagation Delay
Transparent Mode A
toBorBtoA
2.0
10.0
2.5
8.5
2.5
7.5
2.5
6.5
ns
1,3
tpLH
tpHL
Propagation Delay
LEBA to A
LEABtoB
2.5
14.0
2.5
12.5
2.5
9.0
2.5
8.0
ns
1,5
tpZH
tpzL
Outp Enable Time
OEB or OEAB to
AorB
CEBA or CEAB to
AorB
2.0
14.0
2.0
12.0
2.0
10.0
2.0
9.0
ns
1,7,8
tpzH
tPZL
Output Disable Time
OEBA or OEAB to
AorB
CEBA or CEAB to
AorB
2.0
13.0
2.0
9.0
2.0
8.5
2.0
7.5
ns
1,7,8
ts
Set-UpTime
HIGH or LOW,
AorBto
LEBA or LEAB
3.0
2.0
2.0
2.0
ns
9
tH
Hold Time
HIGH or LOW,
AorBto
LEBAorLEAB
Pulse Width LOW[6]
LEBAorLEAB
2.0
2.0
2.0
2.0
ns
9
5.0
5.0
5.0
5.0
ns
5
Parameter
tw
Parameter
}!
Fi
MinJ14]
Description
No.n-5]
tpLH
tpHL
Propagation Delay
'fransparent Mode A to B or B to A
2.5
6.1
2.5
5.3
ns
1,3
tpLH
tpHL
Propagation Delay
LEBA to A, LEAB to B
2.5
8.0
2.5
7.0
ns
1,5
tpZH
tpzL
Output Enable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
2.0
9.0
2.0
8.0
ns
1,7,8
tPZH
tPZL
Output Disable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
2.0
7.5
2.0
6.5
ns
1,7,8
ts
Set-Up Time, HIGH or LOW,
A or B to LEBA or LEAB
2.0
2.0
ns
9
2.0
2.0
9
Notes:
14. Minimum limits are guaranteed but not tested on Propagation Delays.
15. See "Parameter Measurement Information" in the General Information Section.
9-98
CY54/74FCT646T
CY54/74FCT648T
8-Bit Registered Transceivers
a
64 mA (Com'I),
48mA(MiI)
32 mA (Com'I),
Source current
12mA(MiI)
• Independent register for A and B
buses
• Three-state output
Features
• Sink current
• Function, pinout and drive compatible
with FCT and F logic
• FCT-C speed at 5.4 ns max. (Com'l)
FCT-A speed at 6.3 ns max. (Com'l)
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly improved noise
characteristics
• Power-otT disable feature
• Matched rise and fall times
• Fully compatible with TTL input and
output logic levels
• ESD > 2000V
The FCT646T and FCT648T consist of a
bus transceiver circuit with three-state,
D-type flip-flops, and control circuitry
arranged for multiplexed transmission of
data ,directly from the input bus or from
the internal registers. Data on the A or B
bus will be clocked into the registers as
the appropriate clock pin goes to a HIGH
Functional Description
Function Block Diagrams
Gi--~
logic level. Enable Control
and
direction pins are provided to control the
transceiver function. In the transceiver
mode, data present at the high-impedance
port may be stored in either the A or B
register, or in both. The select controls
can multiplex stored and real-time
(transparent mode) data. The direction
control determines which bus will receive
data when the enable control is Active
LOW In the isolation mode (enable
Control HIGH), A data may be stored
in the B register andlor B data may be
stored in the A register.
The outputs are designed with a
power-off disable feature to allow for live
insertion of boards.
a
a
Pin Configurations
__
LCCIPLCC
DIP
Top View
Top View
DIRI-~-l.-Je---I------:------I
CPAB
CPSA,------_i_--:----.,---l:>O-------h
SBA,--~----_i_-~
A7
CPAB
SABI---'----+---_i_-D..,...~
As
'C>-,
GND
NC
8,
B7
B,
1110 9 8 1 6 5
12
13
1.
15
16
28
21
17
2B
16
19202122232425
DIR
SAB
CPAB
NC
Vee
CPSA
SSA
FCT646T-2
H-I-;--.
SAB
DIR
A,
Ao
Ao
A"
A;,
A;,
A7
A,
GND
vee
CPBA
SSA
G
B,
e"
B:.
8.
Bs
s"
B7
B,
FCT646T-3
B,
Logic Block Diagram
SAB
DIR
CPSA
SSA
FCT646T ONLY
FCT646T ONLY
TO 7 OTHER CHANNELS
FCT646T-1
FCT646T-4
Pin Description
A
Description
Data Register A Inputs, Data Register B Outputs
Name
B
Data Register B Inputs, Data Register A Outputs
CPAB,CPBA
Clock Pulse Inputs
SAB,SBA
Output Data Source Select Inputs
DIR,a
Output Enable Inputs
9-100
CY54/74FCT646T
CY54/74FCT648T
=:rcYPRESS
Maximum Ratings[4, 5]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Storage Thmperature ................... -65°C to +150°C
Ambient Temperature with
Power Applied ........................ -65°C to + 135°C
Supply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC Input Voltage ........................ -O.5V to +7.0V
DC Output Voltage ...................... -O.5V to + 7.0V
DC Output Current (Maximum Sink Current/Pin) .... 120rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.5W
Operating Range
Electrical Characteristics Over the Operating Range
Parameter
Description
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Ambient
Temperature
O°Cto +70°C
Range
Commercial
Range
CT
Commercial
T,AT
-40°C to +85°C
5V±5%
All
-55°C to + 125°C
5V ± 10%
Military[6]
Test Conditions
Min.
'lYPJ7]
Vee
5V±5%
Max.
Unit
Vcc=Min., IOH=-32 rnA
Com'l
2.0
Vcc=Min., IOH=-15 rnA
Com'l
2.4
3.3
V
Vcc=Min., IOH=-12 rnA
Mil
2.4
3.3
V
Vcc=Min., IOL=64 rnA
Com'l
0.3
0.55
V
Vee=Min., IOL=48 rnA
Mil
0.3
0.55
V
V
VJH
Input HIGH Voltage
2.0
VIL
Input LOW Voltage
V
VH
Hysteresis[8]
All inputs
VIK
Input Clamp Diode Voltage
Vee=Min., IIN=-18 rnA
-1.2
V
II
Input HIGH Current
Vee=Max., VIN=Vee
5
IJH
Input HIGH Current
Vee = Max., VIN=2.7V
±1
IlL
Input LOW Current
Vee=Max., VIN=O.5V
los
Output Short Circuit Current[9]
Vee=Max., VOUT=O.OV
IOFF
Power-Off Disable
0.8
V
0.2
-0.7
-60
-120
Vce=OV; VouT=4.5V
V
±1
iAA
iAA
iAA
-225
rnA
±1
iAA
Capacitance[8]
'lYPJ7]
Max.
Unit
CIN
Input Capacitance
6
10
pF
CoUT
Output Capacitance
8
12
pF
Parameter
Description
Notes:
4. Unless othelWise noted, these limits are over the operating free-air
temperature range.
S. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
6. TA is the "instant on" case temperature.
7. "JYpical values are at Vcc=S.OV, TA=+25°C ambient.
8. This parameter is guaranteed but not tested.
9.
9-102
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample .and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
CY54/74FCT646T
CY54/74FCT648T
Switching Characteristics Over the Operating Range
FCT646T/FCT648T
Military
FCT646AT/FCT648AT
Commercial
Military
Commercial
Description
MinJ14]
Max.
MinJ14]
Max.
MinJ14]
Max.
MinJ14]
Max.
Unit
Fi~
No.5]
tPLH
tpHL
Propagation Delay
Bus to Bus
2.0
11.0
1.5
9.0
2.0
7.7
1.5
6.3
ns
1,3
tPZH
tPZL
Output Enable Time
Enable to Bus and
DIR to An or Bn
2.0
15.0
1.5
14.0
2.0
10.5
1.5
9.8
ns
1,7,8
tpHz
tpLZ
Output Disable
Time
GtoBusand
DIR toBus
2.0
11.0
1.5
9.0
2.0
7.7
1.5
6.3
ns
1,7,8
tpLH
tpHL
Propagation Delay
Clock to Bus
2.0
10.0
1.5
9.0
2.0
7.0
1.5
6.3
ns
1,5
tpLH
tpHL
Propagation Delay
SBAorSAB
toAorB
2.0
12.0
1.5
11.0
2.0
8.4
1.5
7.7
ns
1,5
ts
Set-UpTime
HIGH or LOW,
Busto Clock
4.5
4.0
2.0
2.0
ns
4
tH
Hold Time
HIGH or LOW,
Bus to Clock
2.0
2.0
1.5
1.5
ns
4
tw
Pulse Width,[6]
HIGH or LOW
6.0
6.0
5.0
5.0
ns
5
Parameter
FCT646CT/FCT648CT
Milit~ry
Parameter
Description
Commercial
MinJ14]
Max.
MinJ14]
Max.
Unit
Fi~
No.5]
tpLH
tPHL
Propagation Delay
Bus to Bus
1.5
6.0
1.5
5.4
ns
1,3
tpZH
tpzL
Output Enable Time
Enable to Bus and DIR to An or Bn
1.5
8.9
1.5
7.8
ns
1,7,8
tpHZ
tpLz
Qutput Disable Time
Gto Bus and
DIR toBus
1.5
7.7
1.5
6.3
ns
1,7,8
tpLH
tpHL
Propagation Delay
Clock to Bus
1.5
6.3
1.5
5.7
ns
1,5
tpLH
tpHL
Propagation Delay
SBAor SAB
toAorB
1.5
7.0
1.5
6.2
ns
1,5
ts
Set-Up Time, HIGH or LOW, Bus to Clock
2.0
2.0
ns
4
tH
Hold Time, HIGH or LOW, Bus to Clock
1.5
1.5
ns
4
tw
Pulse Width,[6] HIGH or LOW
5.0
5.0
ns
5
Notes:
14. Minimum limits are guaranteed but not tested on Propagation Delays.
15. See "Parameter Measurement Information" in the General Information Section.
9-104
CY54/74FCT652T
8-Bit Registered Transceiver
Features
• Function, pinout, and drive
compatible with FCT and F logic
• FCT-C speed at 5.4 ns max. (Com'l)
FCT-A speed at 6.3 ns max. (Com'l)
• Reduced VOH (typically 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly improved noise
characteristics
• Power-ofT disable feature
• Matched rise and fall times
• Fully compatible with TTL input and
output logic levels
64 mA (Com'I),
• Sink current
48mA(Mil)
32 mA (Com'I),
Source current
12mA (Mil)
• ESD > 2000V
=
• Independent register for A and B
buses
• Multiplexed real-time and stored data
transfer
Functional Description
The FCT652T consists of bus transceiver
circuits, D-type flip-flops, and control
circuitry arranged for multiplexed
transmission of data directly from the
input bus or from the internal storage
registers. GAB and GBA control pins are
provided to control the transceiver
functions. SAB and SBA control pins are
provided to select either real-time or
stored data transfer. The circuitry used
for select control will eliminate the typical
decoding glitch that occurs in a
multiplexer during the transition between
stored and real-time data. A LOW input
Logic Block Diagram
level selects real-time data and a HIGH
selects stored data.
Data on the A or B data bus, or both, can
be stored in the internal D flip-flops by
LOW-to-HIGH transitions at the
appropriate clock pins (CPAB or CPBA),
regardless of the select or enable control
pins. When SAB and SBA are in the
real-time transfer mode, it is also possible
to store data without using the internal
D-type flip-flops by simultaneously
enabling GAB and lillA. In this
configuration, each output reinforces its
input. Thus, when all other data sources
to the two sets of bus lines are at high
impedance, each set of bus lines will
remain at its last state.
The outputs are designed with a
power-off disable feature to allow for live
insertion of boards.
Pin Configurations
CPBA
G~--~~--------
__________________________
LCC
~
Top View
SBA
SAB
11 109 8 7 6 5
A,
As
CPAB
BREG
12
13
•
3
GND
1.
NC
Ba
a,
15
16
17
B6
181920212223242526
28
27
GAB
SAB
CPAB
NC
Vee
CPBA
SSA
rtlll)aJ"ltrtJ(fJ~ ~ml~
FCT652T-2
DIP{SOIC{QSOP
B,
Top View
CPAB
SAB
Vee
CPBA
GAB
SBA
A,
GSA
B,
~---------------~---------------~
As
As
Ao
As
As
TO 7 OTHER CHANNELS
A,
Be
As
B,
Be
L
FCT652T··1
GND
B,
Bs
B,
Bs
FCT652T·3
9-106
1ii~YPRESS~~~~~~~~~~~~=CY~54~/7=4=FC=T=6=52~T
Maximum Ratings[3,4]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................... -65°C to +150°C
Ambient Thmperature with
Power Applied ........................ -65°C to + 135°C
Supply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC Input Voltage ........................ -O.5V to + 7.0V
DC Output Voltage ...................... -0.5V to + 7.0V
DC Output Current (Maximum Sink Current/Pin) .... 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.5W
Operating Range
Ambient
Temperature
O°Cto +70°C
Range
Commercial
Range
CT,DT
Commercial
T,AT
-40°C to +85°C
5V±5%
All
-55°C to +125°C
5V± 10%
MiJitary[5]
Vee
5V±5%
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Min.
Test Conditions
TypJ6]
Max.
Unit
Vee=Min., IOH=-32 rnA
Com'l
2.0
Vee=Min., IOH=-15 rnA
Com'l
2.4
3.3
Vee = Min., IOH=-12 rnA
Mil
2.4
3.3
V ee=Min., IOL =64 mA
Com'l
0.3
0.55
V
Vee=Min., IOL=48 rnA
Mil
0.3
0.55
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[7]
All inputs
VIK
Input Clamp Diode Voltage
Vee=Min., IIN= -18 rnA
II
Input HIGH Current
IIH
IlL
V
V
V
2.0
V
0.8
V
0.2
-0.7
V
-1.2
V
Vee=Max., VIN=Vee
5
Input HIGH Current
Vee = Max., VIN=2.7V
±1
Input LOW Current
Vee=Max., VIN=0.5V
±1
IOZH
Off State HIGH-Level
Output Current
Vee=Max., VouT=2.7V
10
iJA
iJA
iJA
iJA
IOZL
Off State LOW-Level
Output Current
Vee=Max., VOUT=O.5V
-10
iJA
los
Output Short Circuit Current[S]
Vee=Max., VOUT=O.OV
-225
mA
IOFF
Power-Off Disable
Vee=Ov, VOUT=4.5V
±1
iJA
-60
-120
Capacitance[7]
1YpJ6]
Max.
Unit
CIN
Input Capacitance
5
10
pF
COUT
Output Capacitance
9
12
pF
Parameter
Description
Notes:
3. Unless othelWise noted, these limits are over the operating free-air
temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
5. TA is the "instant on" case temperature.
6. 1YPical values are at Vee=S.Ov, TA=+25"C ambient.
7. This parameter is guaranteed but not tested.
8. Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
9-108
Switching Characteristics[13] Over the Operating Range
FCf652AT
FCT652T
Military
Pa~meter
Description
Commercial
Military
Commercial
MinJ14]
Max.
MinJ14]
Max.
MinJ14]
Max.
MinJ14]
Max.
Unit
Fi5No.5]
tPLH
tpHL
Propagation Delay
Busto Bus
2.0
11.0
1.5
9.0
2.0
7.7
1.5
6.3
ns
1,3
tpzH
tpZL
Output Enable Time
Enable to Bus
2.0
15.0
1.5
14.0
2.0
10.5
1.5
9.8
ns
1,7,8
tpHZ
tpLZ
Outbut Disable Time
Ena Ie to Bus
2.0
11.0
1.5
9.0
2.0
7.7
1.5
6.3
ns
1,7,8
tpLH
tpHL
Propagation Delay
Clock to Bus
2.0
10.0
1.5
9.0
2.0
7.0
1.5
6.3
ns
1,5
tpLH
tpHL
Propagation Delay
SBA or SAB to A or B
2.0
12.0
1.5
11.0
2.0
8.4
1.5
7.7
ns
1,5
ts
Set-UpTime
HIGH or LOW
Busto Clock
4.5
4.0
2.0
2.0
ns
4
tH
Hold Time
HIGH or LOW
Busto Clock
2.0
2.0
1.5
1.5
ns
4
tw
Clock Pulse Width,[16]
HIGH or LOW
6.0
6.0
5.0
5.0
ns
5
Parameter
Description
MinJ14]
Max.
MinJ14]
Max.
Unit
Fi
No.5-5]
tpLH
tpHL
Propagation Delay
Bus to Bus
1.5
6.0
1.5
5.4
ns
1,3
tpZH
tpZL
Output Enable Time Enable to Bus
1.5
8.9
1.5
7.8
ns
1,7,8
tpHZ
tpLZ
Output Disable Time Enable to Bus
1.5
7.7
1.5
6.3
ns
1,7,8
tpLH
tpHL
Propagation Delay
Clock to Bus
1.5
6.3
1.5
5.7
ns
1,5
tpLH
tpHL
Propagation Delay
SBA or SAB to A or B
1.5
7.0
1.5
6.2
ns
1,5
ts
Set-UpTime
HIGH or LOW
Bus to Clock
2.0
2.0
ns
4
tH
Hold Time
HIGH or LOW
Bus to Clock
1.5
1.5
ns
4
5.0
5.0
ns
5
Notes:
13. AC Characteristics guaranteed with CL =50 pF as shown in Figure 1 of
"Parameter Measurement Information" in the General Information
section.
14. Minimum limits are guaranteed but not tested on Propagation Delays.
15. See "Parameter Measurement Information" in the General Informa·
tion Section.
16. With one data channel toggling, tw(L)=tw(H)=4.0 ns and
tr= tf= 1.0 os.
9-110
CY54/74FCT821T
CY54/74FCT823T
CY54/74FCT825T
8-/9-/10-Bit Bus Interface Registers
Features
64 mA (Com'I),
32 mA (Mil)
32 mA (Com'I),
12 mA (Mil)
• High-speed parallel registers with
positive edge-triggered D-type
flip-flops
• Bnffered common clock enable ~
and asynchronous clear input (CLR)
• Sink current
• Function, pinout and drive compatible
with FCT, F, and Am29821/23/25 logic
• FCT-C speed at 6.0 ns max. (Com'l)
FCT-B speed at 7.5 ns max. (Com'l)
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly improved noise
charact~ristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and
output logic levels
• ESD > 2000V
Source current
Functional Description
These bus interface registers are designed
to eliminate the extra packages required
to buffer existing registers and provide
extra data width for wider address/data
paths or buses carrying parity. The
FCT82I T is a buffered, 10-bit wide version ofthe popular FCT374 function. The
FCT823T is a 9-bit wide buffered register
with clock enable (EN) and clear (CLR)
- ideal for parity bus interfacing in
high-performance microprogrammed systems. The FCT825T is an 8-bit buffered
register with all the FCT823T controls
plus multiple enables (DEl> C>Ez, C>E3) to
allow multiuser control of the interface,
e.g., CS, DMA, and RDiWR. They are
ideal for use as an output port requiring
high IorJIOH.
These devices are designed for highcapacitance load drive capability, while
providing low-capacitance bus loading at
both inputs and outputs. Outputs are
designed for low-capacitance bus loading
in the high-impedance state and are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
mill ---.,.+-.,---.,.+-.,--....,.+-~-....,.+-~-....,.+-~-....,.~
Vo
V,
Y,
Note:
1. Not on FCf821.
9-112
V5
Yn-1
CY54/74FCT821T
CY54/74FCT823T
CY54/74FCT825T
.rcYPRESS
Pin Description
Name
I/O
I
D
CLR
I
Description
The D flip-flop data inputs.
When CLR is LOW and DE is LOW; the Q outputs are Law. When CLR is HIGH, data can be
entered into the register.
CP
a
Clock Pulse for the register; enters data into the register on the LOW-to-HIGH transition.
y
a
The register three-state outputs.
EN
I
Clock Enable. When EN is LOW; data on the D input is transferred to the Q output on the
LOW-to-HIGH clock transition. When EN is HIGH, the Q outputs do not change state, regardless of the data or clock input transitions.
DE
I
Output Control. When OE is HIGH, the Y outputs are in the high-impedance state. When DE
is LOW; the TRUE register data is present at the Youtputs.
Function Thble[2]
Inputs
Internal Outputs
OE
CLR
EN
D
H
H
H
H
L
L
L
H
H
L
L
L
X
X
X
X
H
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
L
L
CP
Q
Y
Function
L
H
Z
Z
HighZ
X
X
L
L
Z
L
Clear
X
X
X
X
NC
NC
Z
NC
Hold
L
H
L
H
.r
.r
.r
.r
L
H
L
H
Z
Z
L
H
Load
.r
.r
Maximum Ratings[3,4]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 301S)
Storage Thmperature ................... -6SoC to + 1S0°C
Ambient Temperature with
Power Applied ........................ -6S °C to + 13S0C
Supply Voltage to Ground Potential ......... -O.5V to +7.0V
DC Input Voltage ........................ -O.5V to + 7.0V
DC Output Voltage ...................... -O.5V to + 7.0V
DC Output Current (Maximum Sink Current!Pin) .... 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O.SW
Operating Range
Notes:
2. H =HIGH Voltage Level, L =LOW Voltage Level, X =Don't Care,
NC =No Change,.f =LOW-to-illGHThansition, Z =HIGH Impedanee.
3. Unless otherwise noted, these limits are over the operating free-air
temperature range.
Ambient
Temperature
O°Cto +700C
Range
Commercial
Range
CT
Commercial
AT,BT
-40°C to +8SOC
SV±S%
All
-SsoC to + 125°C
SV ± 10%
Military[5]
Vee
SV ±5%
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
5. TA is the "instant on" case temperature.
9-114
CYS4/74FCT821T
CYS4/74FCT823T
CYS4/74FCT82ST
.;rcYPRESS
Power Supply Characteristics
'lYPJ6]
Max.
Unit
Icc
Quiescent Power Supply Current
Vee=Max., VIN,,0.2V,
VIN2: Vee-0.2V
0.1
0.2
rnA
Alec
Quiescent Power Supply Current
(TIL inputs HIGH)
Vee=Max., VIN=3.4v,[9]
fl =0, Outputs Open
0.5
2.0
rnA
IceD
Dynamic Power Supply
Current[lO]
Vee=Max., One Bit Thggling,
50% Du!}' Cycle, Outputs Open,
OE=EN=GND,
VIN"O.2Vor VIN2:Vee-0.2V
0.06
0.12
Ie
Total Power Supply Currentl11]
Vee-Max., fo=lO MHz,
50% Duty Cycle, Outputs Open,
One Bit Thggling at fl =5 MHz,
OE=EN=GND,
VIN"0.2VorVIN;,,Vcc- 0.2V
0.7
1.4
rnA
Vee-Max., fo=10 MHz,
50% Duty Cycle, Outputs Open,
One Bit Thggling at fl =5 MHz,
OE=EN=GND,
VIN=3.4Vor VIN=GND
1.2
3.4
rnA
Vee=Max., fo= 10 MHz,
50% Duty Cycle, Outputs Open,
~ht Bits Thggling at fl =2.5 MHz,
o =EN=GND,
VIN,,0.2Vor VIN.2:Vee-0.2V
1.6
3.2[11]
rnA
Vee=Max., fo=lO MHz,
50% Duty Cycle, Outputs Open,
£jght Bits Thggling at fl =2.5 MHz,
OE=EN=GND,
VIN=3.4Vor VIN=GND
3.9
12.2[12]
rnA
Parameter
Description
Test Conditions
Notes:
9. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
10. This parameter is not directly testable, but is derived for use in Total
Power Supply calculations.
11. Ic
= IQUIESCENT + IINPUTS + IDYNAMIC
Ic
= Icc+McCDHNT+Icco(f0/2 + fjNj)
Icc
= Quiescent Current with CMOS input levels
dlcc = Power Supply Current for a TTL lllGH input
(VIN=3.4V)
DH
= Duty Cycle for TTL inputs HIGH
= Number of TTL inputs at DH
= Dynamic Current caused by an input transition pair
(HLHor LHL)
fo
= Clock frequency for registered devices, otherwise zero
fj
= Input signal frequency
= Number of inputs changing at fj
Nj
All currents are in milliamps and all frequencies are in megahertz.
12. Values for these conditions are examples of the Icc formula. These
limits are guaranteed but not tested.
9-116
NT
ICCD
ruN
MHz
CY54/74FCT821 T
CY54/74FCT823T
CY54/74FCT825T
~YPRESS
Switching Characteristics Over the Operating Range (continued)
FCfS21CT/FCfS23CT/FCTS2SCT
Military
Par&nl.
Description
Test Load
MinJ13J
Commercial
Max.
MinJ13J
Max.
Unit
Fi~
No. 4J
tpLH
tpHL
Propagation Delay
CPtoY
(OE=LOW)
CL=50pF
RL=500Q
7.0
6.0
ns
1,5
tpLH
tpHL
Propagation Delay
CPtoY
(0E=LOW)[6j
CL=300pF
RL=500Q
13.5
12.5
ns
1,5
tpLH
~agation
CL=50pF
RL=500Q
8.5
8.0
ns
1,5
CLR to Yl
tpZH
tpzL
Output Enable Time
OEtoY
CL=50 pF
RL=500Q
8.0
7.0
ns
1,7,8
tpzH
tpZL
Output Enable Time
OEto y[6j
CL=300pF
RL=500Q
13.5
12.5
ns
1,7,8
tpHZ
tPHL
Output Disable Time
OEto y[6J
CL=5pF
RL=500Q
6.2
6.0
ns
1,7,8
tPHZ
tpHL
Output Disable Time
OEtoY
CL=50pF
RL=500Q
6.5
6.5
ns
1,7,8
tsu
Data toCP
Set-UpTime
3.0
3.0
ns
4
tH
Data toCP
Hold Time
1.5
1.5
ns
4
tsu
Enable EN to CP
Set-UpTime
3.0
3.0
ns
4
0.0
0.0
ns
4
6.0
6.0
ns
6
Delay
CL=50&F
RL=50 Q
tH
Enable EN to CP
Hold Time
tREM
Clear Recovery Time
CLRtoCP
tw
Clock Pulse Width
6.0
6.0
ns
5
tw
CLR Pulse Width LOW
6.0
6.0
ns
5
9-118
CY54/74FCT821 T
CY54/74FCT823T
CY54/74FCT825T
.~YPRESS
Ordering InformatiQn-FCT825T
Speed
(ns)
5.4
6.0
6.3
Ordering Code
9.0
11.0
Package 'JYpe
CY74FCT825CTl'C
P13/l3A
CY74FCT825cTOC
013
24-Lead (150-Mil) QSOP
CY74FCT825CTSOC
S13
24-Lead (300-Mil) Molded SOIC
CY54FCT825CTDMB
D14
24-Lead (300-Mil) CerDIP
CY54FCT825CTLMB
L64
28-Square Leadless Chip Carrier
P13113A
24-Lead (300-Mil) Molded DIP
CY74FCT825BTPC
24-Lead (300-Mil) Molded DIP
013
CY74FCT825BTSOC
S13
24-Lead (300-Mil) Molded SOIC
CY54FCT825BTDMB
D14
24-Lead (300-Mil) CerDIP
CY54FCT825BTLMB
L64
28-Square Leadless Chip Carrier
CY74FCT825ATPC
P13/l3A
24-Lead (300-Mil) Molded DIP
CY74FCT825ATQC
Q13
24-Lead (150-Mil)
CY74FCT825ATSOC
S13
24-Lead (300-Mil) Molded SOIC
CY54FCT825ATDMB
D14
24-Lead (300-Mil) CerDIP
CY54FCT825ATLMB
L64
28-Square Leadless Chip Carrier
Document #: 38-00282-A
9-120
Operating
Range
Commercial
Military
Commercial
asap
24-Lead (150-Mil)
CY74FCT825BTQC
7.7
Package
Name
Military
Commercial
asap
Military
Maximum Ratings[2, 3]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied ........................ -65°C to + 135°C
Supply Voltage to Ground Potential ......... -0.5V to +7.OV
DC Input Voltage ........................ -0.5V to +7.OV
DC Output Voltage ...................... -0.5V to +7.OV
DC Output Current (Maximum Sink Current/Pin) . . .. 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O.5W
Electrical Characteristics Over the Operating Range
Parameter
Description
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Operating Range
Ambient
Temperature
O°Cto +70°C
Range
Commercial
Range
CT
Commercial
AT,BT
-40°C to +85°C
5V±5%
All
-55°C to + 125°C
5V± 10%
Military[4]
Min.
'lest Conditions
Vee=Min.,IoH=-32rnA
Com'l
2.0
1YpJ5]
Vee
5V±5%
Max.
Unit
V
Vee=Min., IOH--15 rnA
Com'l
2.4
3.3
Vee = Min., IOH= -12 rnA
Mil
2.4
3.3
Vee=Min., IOL=64 rnA
Com'l
0.3
0.55
V
Vee=Min., IOL=32 mA
Mil
0.3
0.55
V
0.8
V
V
V
2.0
VH
Hysteresis[6]
All inputs
VIK
InputClamp Diode Voltage
Vee=Min., IIN=-18 rnA
II
Input HIGH Current
1m
Input HIGH Current
IlL
IOZH
IOZL
V
0.2
V
-1.2
V
Vee=Max., VIN=Vee
5
Vee=Max., VIN=2.7V
±1
Input LOW Current
Vee=Max., VIN=O.5V
±1
Off State HIGH-Level Output
Current
Vee = Max., VOUT = 2.7V
10
I1A
I1A
I1A
I1A
Off State LOW-Level
Output Current
Vee = Max., VOUT = O.5V
-10
I1A
-225
rnA
±1
I-tA
los
Output Short Circuit Current[7]
Vcc=Max., VOUT=O.OV
IOFF
Power-Off Disable
Vee=Ov, VouT=4.5V
-0.7
-60
-120
Capacitance[6]
Parameter
Description
1YpJ5]
Max.
Unit
CJN
Input Capacitance
5
10
pF
CoUT
Output Capacitance
9
12
pF
Notes:
2. Unless otherwise noted, these limits are over the operating free-air
temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
4. TA is the "instant on" case temperature.
5. "JYpica1 values are at Vcc=S.OV; TA= +25°C ambient.
6. This parameter is guaranteed but not tested.
7.
9-122
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus andlor sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
Switching Characteristics Over the Operating Rangd 12]
FCT827AT
Military
Parameter
Description
FCT827BT
Commercial
Military
Commercial
Test Load
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Fili:
Max. Unit No.3]
tpLH
tpHL
Propagation Delay
DtoY
CL=50 pF
RL=500Q
1.5
9.0
1.5
8.0
1.5
6.5
1.5
5.0
ns
1,3
tpLH
tpHL
Propawtion Delay
Dtoy6]
CL=300pF
RL=500Q
1.5
17.0
1.5
15.0
1.5
14.0
1.5
13.0
ns
1,3
tpZH
tpZL
OIl: to Y
Output Enable Time
CL=50pF
RL=500Q
1.5
13.0
1.5
12.0
1.5
9.0
1.5
8.0
ns
1,7,8
tPZH
tpZL
OIl: to y[6]
Output Enable Time
CL=300pF
RL=500Q
1.5
25.0
1.5
23.0
1.5
16.0
1.5
15.0
ns
1,7,8
tpHZ
tpHL
OIl: to y[6]
Output Disable Time-
CL=5pF
RL=500Q
1.5
9.0
1.5
9.0
1.5
7.0
1.5
6.0
ns
1,7,8
tpHZ
tPHL
OIl: to Y
Output Disable Time
CL=50pF
RL=500Q
1.5
10.0
1.5
10.0
1.5
8.0
1.5
7.0
ns
1,7,8
FCT827CT
Military
Parameter
Description
Commercial
Fili:
Unit No.3]
Test Load
Min.
Max.
Min.
Max.
CL=50pF
RL=500Q
1.5
5.0
1.5
4.4
ns
1,3
CL=300pF
RL=500Q
1.5
11.0
1.5
10.0
ns
1,3
tpLH
tpHL
Propagation Delay
DtoY
tpLH
tpHL
Dtoy6]
tpZH
tpZL
Output Enable Time
OEtoY
CL=50 pF
RL=500Q
1.5
8.0
1.5
7.0
ns
1,7,8
tpZH
tpZL
OIl: to y[6]
Output Enable Time
CL=300pF
RL=500Q
1.5
15.0
1.5
14.0
ns
1,7,8
tpHZ
tpHL
OIl: to y[6]
Output Disable Time
CL=5pF
RL=500Q
1.5
6.7
1.5
5.7
ns
1,7,8
tpHZ
tpHL
Output Disable Time
OEtoY
CL=5~t
1.5
7.0
1.5
6.0
ns
1,7,8
Propa~ation
Delay
RL=5
Notes:
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. See "Parameter Measurement Information" in the General
Information Section.
9-124
Q
CYS4/74FCT841T
IO-Bit Latch
Features
• Function, pillout and drive compatible
with FCT, F,and AM29841 logic
• FCT-C speed at S.Sns max. (Com'l)
FCT-B speed at 6.Sns max. (Com'l)
• Reduced VOH (typically 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly improved noise
characteristics
• Power-otT disable feature
• Matched rise and fall times
• ESD > 2000V
=
provide extra data width for wider
address/data paths or buses carrying
parity. The FCT841T is a buffered lO-bit
wide version of the FCT373 function.
The
FCT841T
high-performance
interface is designed for high-capacitance
load drive capability while providing
low-capacitance bus loading at both
inputs and outputs. Outputs are designed
for low-capacitance bus loading in the
high impedance state and are designed
with a power-off disable feature to allow
for live insertion of boards.
• Fully compatible with TTL input and
outprit logic levels
64 rnA (Com'I),
• Sink current
32 rnA (Mil)
Source current
32 rnA (Com'I),
12 rnA (Mil)
• High-speed parallel latches
• ButTered common latch enable input
Functional Description
The FCT841T bus interface latch is
designed to eliminate the extra packages
required to buffer existing latches and
Functional Block Diagram
Yo
Y,
Y,
Y,
Y,
Y,
YN-1
YN
FCT841T·1
Logic Block Diagram
DiD
LE
LE
Pin Configurations
o~
LCC/pLCC
Top View
Y
l;r!8~c~88
11 109 87 6 5
D.
D.
GND
OE
NC
FCT841T-2
DIP
Top View
LE
Y.
Y.
12
13
14
15
16
17
4
3
D,
Do
OE
NC
28
27
181920212223242526
Vee
Yo
Y,
~~~~>-¢.,:>~
FCT841T-3
OE
Do
D,
D,
Os
D,
D,
De
D-r
D.
D.
GND
Vee
Yo
Y,
Y,
Y,
Y,
Y,
Y.
Y7
Y.
Y,
LE
FCT841T4
9-126
CY54/74FCT841T
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Thst Conditions
Min.
1YpJ5]
Max.
Unit
Vee=Min., IOH=-32 rnA
Corn'l
2.0
Vee=Min., IOH=-15 rnA
Corn'l
2.4
3.3
V
Vee=Min., IOH= -12 rnA
Mil
2.4
3.3
V
Vee=Min., IOL=64 rnA
Corn'l
0.3
0.55
Vee-Min., IOL-32 rnA
Mil
0.3
0.55
V
V
V
VIH
Input HIGH Voltage
2.0
V
VIL
Input Low Voltagtb
VH
Hysteresis[6]
All inputs
VIK
Input Clamp Diode Voltage
Vee=Min., IIN=-18 rnA
-1.2
V
II
Input HIGH Current
Vcc=Max., VIN=Vee
5
IIH
Input HIGH Current
VCC=Max., VIN=2.7V
±1
IlL
Input LOW Current
Vee=Max., VIN=O.~V
±1
IOZH
Off State HIGH-Level Output
Current
Vee = Max., VOUT = 2.7V
10
iJA
iJA
iJA
iJA
IOZL
Off State LOW-Level
Output Current
Vee = Max., VOUT = O.5V
-10
iJA
los
Output Short Circuit Current[7]
Vcc=Max., VOUT=O.OV
-225
rnA
IOFF
Power-Off Disable
Vcc=Ov, VouT=4.5V
±1
iJA
0.8
V
0.2
-0.7
-60
-120
V
Capacitance[6]
1YpJ5]
Max.
Unit
CIN
Input Capacitan,ce
5
10
pF
COUT
Output Capacitance
9
12
pF
Parameter
Description
Notes:
5. 'JYpical values are at Vce=5.0V, TA=+25°C ambient.
6. This parameter is guaranteed but not tested.
7. Not more than one output shquld be shorted at a time. Duration of
short should not exceed one second. 1')1.e use of high-speed test
apparatus andlor sample and hold techniques are preferable in order
9-128
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
CY54/74FCT841T
IzV2YPRESS
Switching Characteristics Over the Operating Rangd 12]
FCT84IAT
Military
FCT841BT
Commercial
Military
Commercial
Filt
Max. Unit No.3]
lest Load
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Propagation Delay
D1 toY1
(LE = HIGH)
CL=50 pF
RL=500Q
1.5
10.0
1.5
9.0
1.5
7.5
1.5
6.5
ns
1,3
Propagation Delay
D1 tOY1
(LE=HIGH)
CL=300pF
RL=500Q
1.5
15.0
1.5
13.0
1.5
15.0
1.5
13.0
ns
1,3
tsu
Data to LE Set-Up
Time
CL=50pF
RL=500Q
2.5
2.5
2.5
2.5
ns
9
tH
Data to LE Hold
Time
CL=50 pF
RL=500Q
3.0
2.5
2.5
2.5
ns
9
tpili
tpHL
Propagation Delay
LEtoY1
CL=50pF
RL=500Q
1.5
13.0
1.5
12.0
1.5
10.5
1.5
8.0
ns
1,3
Propagation Delay
LEtoY1[6j
CL=300pF
RL=500Q
1.5
20.0
1.5
16.0
1.5
18.0
1.5
15.5
ns
1,3
tw
LE Pulse Width
(HIGH)
CL=50pF
RL=500Q
5.0
ns
5
tPZH
tpZL
Output Enable Time
DE to Y1
CL=50pF
RL=500Q
1.5
13.0
1.5
11.5
1.5
8.5
1.5
8.0
ns
1,7,8
Output Enable Tinle
DE to Y1[6j
CL=300pF
RL=500Q
1.5
25.0
1.5
23.0
1.5
15.0
1.5
14.0
ns
1,7,8
Output DisableTime
OEtoY1[6]
CL=5 pF
RL=500Q
1.5
9.0
1.5
7.0
1.5
6.5
1.5
6.0
ns
1,7,8
Output Disable Tinle
OEtoY1
CL=50pF
RL=500Q
1.5
10.0
1.5
8.0
1.5
7.5
1.5
7.0
ns
1,7,8
Parameter
tpili
tpHL
tpHz
tpLz
Description
4.0
4.0
Notes:
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. See "Parameter Measurement Information" in the General
Information Section.
9-130
4.0
CY54/74FCT841T
QYPRESS
Ordering Information
Speed
(ns)
S.S
6.3
6.5
7.5
9.0
10.0
Ordering Code
Package
Name
Package 'lYPe
CY74FCT841CfPC
P13/13A
. CY74FCT841CTQC
Q13
24-Lead (lS0-Mil) QSOP
CY74FCT841CTSOC
S13
24-Lead (300-Mil) Molded SOIC
CYS4FCf841CTDMB
D14
24-Lead (300-Mil) CerDIP
CYS4FCT841CTLMB
L64
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Molded DIP
CY74FCf841BTPC
P13/13A
CY74FCf841BTQC
Q13
24-Lead (lS0-Mil) QSOP
24-Lead (300-Mil) Molded DIP
CY74FCf841BTSOC
S13
24-Lead (300-Mil) Molded SOIC
CYS4FCT841BTDMB
014
24-Lead (300-Mil) CerDIP
CYS4FCT841BTLMB
L64
28-Square Leadless Chip Carrier
CY74FCf841ATPC
P13/13A
24-Lead (300-Mil) Molded DIP
CY74FCf841ATQC
Q13
24-Lead (lS0-Mil) QSOP
CY74FCf841ATSOC
S13
24-Lead (300-Mil) Molded SOIC
CY54FCT841ATDMB
014
24-Lead (300-Mil) CerDIP
CYS4FCT841ATLMB
L64
28-Square Leadless Chip Carrier
Document #: 38-00273-A
9'-132
Operating
Range
Commercial
Military
Commercial
Military
Commercial
Military
CY54/74FCT2240T
CY54/74FCT2244T
=-~
"CYPRESS
Function Thble FCT2240T[1]
Function Thble FCT2244T[1]
Inputs
Inputs
OEA
OEB
D
Output
OEA
OEB
D
Output
L
L
H.
L
L
H
L
H
H
L
Z
L
L
H
L
L
H
L
H
X
L
H
X
Z
Maximum Ratings[2,3]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . .. >2001V
(per MIL-SID-883, Method 3015)
Storage Thmperature ................... -65°C to + 150°C
Ambient Temperature with
Power Applied ........................ -65°C to + 135°C
Supply Voltage to Ground Potential ......... -O.5V to +7.0V
DC Input Voltage ........................ -0.5V to + 7.0V
DC Output Voltage ...................... -0.5V to + 7.0V
DC Output Current (Maximum Sink Current/Pin) .... 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.5W
Operating Range
Ambient
Thmperature
O°Cto +70°C
Range
Commercial
Range
CT,DT
Commercial
T,AT
-40°Cto +85°C
5V±5%
All
-55°C to +125°C
5V ± 10%
Military[4]
Vee
5V±5%
Electrical Characteristics Over the Operating Range
Parameter
VOH
Min.
'!ypJ5]
Vee= Min., IOH= -15 rnA
Com'l
2.4
3.3
Vee=Min., IOH= -12 rnA
Mil
2.4
3.3
Vee = Min., IOL=12 rnA
Com'l
Thst Conditions
Description
Output HIGH Voltage
0.55
V
25
40
Q
Output Resistance
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[6]
Ail inputs
0.2
VIK
Input Clamp Diode Voltage
Vee=Min., IIN= -18 rnA
-0.7
II
Input HIGH Current
IIH
IlL
Mil
Vee=Min., IOL=12 rnA
Mil
20
V
0.3
ROUT
Com'l
V
0.55
VOL
Vee=Min., IOL=12 rnA
Unit
0.3
Output LOW Voltage
Vee = Min., IOL=12 rnA
Max.
25
V
Q
2.0
V
0.8
V
V
-1.2
V
Vee=Max., VIN=Vee
5
Input HIGH Current
Vee=Max., VIN=2.7V
±1
Input LOW Current
Vee=Max., VIN=O.5V
±1
IOZH
Off State HIGH-Level
Output Current
Vee-Max., VOUT-2.7V
10
!lA
!lA
!lA
!lA
IOZL
Off State WW-Level
Output Current
Vee=Max., VOUT=O.5V
-10
!lA
los
Output Short Circuit Current[7]
Vee=Max., VOUT=O.OV
-225
rnA
IOFF
Power-Off Disable
Vee=OV; VOUT=4.5V
±1
!lA
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care.
2. Unless otherwise noted, these limits are over the operating free-air
temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
4. TA is the "instant on" case temperature.
5. 'JYpical values are at Vcc=S.ov, TA=+25'C ambient.
6. This parameter is guaranteed but not tested.
7.
9-134
-60
-120
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests shonld be performed last.
~CYPRESS
CY54/74FCT2240T
CY54/74FCT2244T
Switching Characteristics FCT2240T Over the Operating Rangd 12]
FCT2240T
Military
FCT2240AT
COmmercial
. Military
Commercial
Description
Min.
Max.
Min.
M;ax.
Min.
Max.
Min.
Max.
Unit
Fifi
No.3]
tpili
tpHL
Propagation Delay
Data to Input
1.5
9.0
1.5
8.0
1.5
5.1
1.5
4.8
ns
1,2
tPZH
tPZL
Output Enable Time
1.5
10.5
1.5
io.o
1.5
6.5
1.5
6.2
ns
1,7,8
tpHZ
tpLZ
Output Disable
Time
1.5
10.0
1.5
9.5
1.5
5.9
1.5
5.6
ns
1,7,8
Par8meter
FCT2240CT
Commercial
Parameter
Description
Min.
Max.
Unit
Fi
No.fi3]
tpili
tpHL
Propagation Delay
Data to Input
1.5
4.1
ns
1,2
tpzH
tPZL
Output Enable Time
1.5
5.8
ns
1,7,8
tpHZ
tpLZ
Output Disable Time
1.5
5.2
ns
1,7,8
Switching Characteristics FCT2244T Over the Operating Range[12]
FCT2244T
Military
FCT2244A
Commerci~l
Military
Commercial
Description
Min.
Max.
Min.
Max.
Min.
Milx.
Min.
Max.
Unit
Fi
No.fi3]
tpLH
tpHL
Propagation Delay
Data to Input
1.5
7.0
1.5
6.5
1.5
5.1
1.5
4.6
ns
1,3
tpZH
tPZL
Output Enable Time
1.5
8.5
1.5
8.0
1.5
6.5
1.5
6.2
ns
1,7,8
tpHZ
tpLZ
Output Disable
Time
1.5
7.5
1.5
7.0
1.5
5.9
1.5
5.6
ns
1,7,8
Unit
Fi
No.fi3]
Parametlir
Parameter
Description
tpili
tpHL
Propagation Delay
Data to Input
ns
1,3
tPZH
tpZL
Output Enable Time
ns
1,7,8
Output Disable Time
ns
1,7,8
Notes:
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. See "Parameter Measurement Information" in the General Information section.
9-136
CY54/74FCT2245T
8-Bit Transceiver
• Sink current
Features
• Function and pinout compatible with
FCT and F logic
• 2S0 output series resistors to reduce
transmission line reflection noise
• FCT·C speed at 4.1 ns max. (Com'l)
FCT·A speed at 4.6 ns max. (Com'l)
• Edge-rate control circuitry for
significantly improved noise
characteristics
• Power·off disable feature
• Fully compatible with TTL input and
output logic levels
• ESD > 2000V
12 mA (Com'I),
12 mA (Mil)
15 mA (Com'I),
12mA (Mil)
Source current
• Three-state outputs
Functional Description
The FCI'2245T contains eight non-inverting, bidirectional buffers with three-state
outputs intended for bus oriented applications. On-chip termination resistors have
been added to the outputs to reduce
system noise caused by reflections. For
this reason, the FCf2245T can be used in
an existing design to replace the
FCT245T. The FCT2245T current sink-
Logic Block Diagram
ing capability is 12 rnA at the A and B
ports.
The Transmit/Receive (TiR) input
determines the direction of data flow
through the bidirectional transceiver.
Transmit (Active HIGH) enables data
from A ports to B ports; receive (Active
LOW) enables data from B ..P2..rts to A
ports. The output enable (OE) input,
when HIGH, disables both the A and B
ports by putting them in a High Z
condition.
The outputs are designed with a
power-off disable feature to allow for live
insertion of boards.
Pin Configurations
T/R
'--"'=-++--=="'I-OE
DIP/SOIC/QSOP
Top View
LCC
Top View
co
It).q.
« «
C')
C\I
Q!!!Y Cycle, Outputs Open,
T/R=OE=GND,
VINS:0.2Vor VIN;,:Vee-0.2V
0.06
0.12
Ie
Thtal Power Supply CurrentLIO]
Vec= Max., 50% Duty Cycle,
Outputs Open,
O~ Bit Toggling at fl =10 MHz,
T/R=OE=GND,
VINs:O.2Vor VIN;,:Vee-0.2V
0.7
1.4
rnA
Vee=Max.,
50% Duty Cycle, Outputs Open,
O~BitTogglingat fl=10MHz,
T/R=OE=GND,
VIN=3.4Vor VIN=GND
1.0
2.4
rnA
Vee=Max.,
50% Duty Cycle, Outputs Open,
Eig!1t Bits Toggling at fl =2.5 MHz,
T/R=OE=GND,
VINs:0.2Vor VIN;': Vee-0.2V
1.3
2.6[11]
rnA
Vcc=Max.,
50% Duty Cycle, Outputs Open,
Eig!lt Bits Toggling at fl =2.5 MHz,
T/R=OE=GND,
VIN=3.4Vor VIN=GND
3.3
10.6[11]
rnA
Parameter
Description
Test Conditions
Notes:
8. Per TIL driven input (VIN=3.4V); all other inputs at Vcc or GND.
9. 1hls parameter is not directly testabLe, but is derived for use in ThtaL
Power Supply calculations.
to. Ic
= IQUIESCENT + IINPUfS + IDYNAMIC
Ic
= Icc+AICCDHNT+ICCD(fol2 + fINI)
Icc
= Quiescent Current with CMOS input levels
dICC = Power Supply Current for a TIL HIGH input
(VIN=3.4V)
DH
= Duty Cycle for TIL inputs HIGH
NT
= Number of TIL inputs at DH
ICCD = Dynamic Current caused by an input transition pair
(HLHor LHL)
fo
= Clock frequency for registered devices, otherwise zero
fl
= Input signal frequency
Nl
= Number of inputs changing atfl
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the Icc formula. These
limits are guaranteed but not tested.
9-140
roN
MHz
CY54/74FCT2257T
Quad 2-Input Multiplexer
• Sink current
Features
• Function and pinont compatible with
FCT and F logic
• 250 output series resistors to rednce
transmission line reflection noise
• FCT-C speed at 4.3 ns max. (Com'l)
FCT-A speed at 5.0 ns max. (Com'l)
• TTL output level versions of
equivalent FCT functions
• Edge-rate control circuitry for
significantly improved noise
characteristics
• Power-off disable feature
• Fully compatible with TTL iuput and
output logic levels
• ESD > 2000V
12 rnA (Com'I),
12 rnA (Mil)
15 rnA (Com'I),
12rnA (Mil)
Source current
• Three-state outputs
Functional Description
The FCTZ257T has four identical
two-input multiplexers that select four
bits of data from two sources under the
control of a common data Select input
(S). The 10 inputs are selected when the
Select input is LOW and the II inputs are
selected when the Select input is HIGH.
Data appears at the output in true
non-inverted form for the FCT2257T.
On-chip termination resistors have been
added to the outputs to reduce system
noise caused by reflections. The
FCT2257T can be used to replace the
FCTZ57T to reduce noise in an existing
design
The FCT2257T is a logic implementation
of a four-pole, two-position switch where
the position of the switch is determined
by the logic levels supplied to the select
input. Outputs are forced to a
high-impedence "OFF" state when the
Output Enable input (OE) is HIGH.
All but one device must be in the
high-impedance state to avoid currents
exceeding the maximum ratings if outputs
are tied together. Design of the output
enable signals must ensure that there is
no overlap when outputs of three-state
devices are tied together.
The outputs are designed with a
power-off disable feature to allow for live
insertion of boards.
Pin Configurations
Logic Block Diagram
lOb
100
s
IOd
LCC
DIP/SOIC/QSOP
Top View
Top View
S
Vee
lOa
OE
loa
11a
10e
S
8 7 6 5 4
Vb
GND
NC
9
10
11
3
Va
'1C
1
NC
lOb
Yo
Yd
i1d
12
13
20
Vee
11b
IOd
19
llE
Vb
11d
1415161718
GND ...,'--_ _~ V,
FCT2257T-3
FCT2257T-2
Va
V,
Vb
FCT2257T-1
Function Tablel1]
Pin Description
Name
I
Description
Data Inputs
S
Common Select Input
OE
Enable Inputs (Active LOW)
y
Data Outputs
Inputs
S
10
11
Y
H
L
L
L
L
X
H
H
L
L
X
X
X
L
H
X
L
H
X
X
Z
L
H
L
H
Notes:
L
9-142
Output
OE
H = HIGH Voltage Level, L = WW Voltage Level, X = Don't Care,
Z = High impedence (OFF) state
Power Supply Characteristics
'JYpJ5J
Max.
Unit
Icc
Quiesceitt Power Supply Current
Vee=Max., VJNsO.2V;
VJN'" Vee-0.2V
0.1
0.2
rnA
il.lee
Quiescent Power Supply Current
(TIL inputs)
Vee-Max., VJN=3.4V;[BJ
fl=O, Outputs Open
0.5
2.0
rnA
IeCD
Dynamic Power Suppiy
Current[9J
Vee=Max:, One Input Toggling,
50% Dpty Cycle, Outputs Open, OE=GND,
VJNsO.2Vor VIN"'VCC-0.2V
0.06
0.12
Ie
Thtal Power Supply Currend lO]
Vec=M\IX., 50% Duty Cycle,
Outputs Open,
.
One Bit Thggling at fl = 10 MHz,
OE=GND,
VINsO.2Vor VIN2:VCC-0.2V
0.7
1.4
rnA
Vee-Max.,
50% Duty Cycie, Ou~uts Open,
One Bit Thggling at 1= 10 MHz,
OE=GND,
VJN=3.4Vor VIN=GND
1.0
2.4
rnA
Vee=Max.,
50% Duty Cycle, Outputs Open,
Four Bits Thggling at fl =2.5 MHz,
OE=GND,
VJNsO.2Vor VJN2:Vee-0.2V
0.7
1.4[11]
rnA
Vee=Max.,
50% Duty Cycle, Outputs
en,
Four Bits Toggling at fl =2. MHz,
OE=GND,
VJN=3.4Vor VJN=GND
1.7
5.4[l1J
rnA
Parameter
Description
lest Conditions
Of
Notes:
8. Per TTI.. driven input (VJN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directJy iestable, but is derived for use in Total
Power Supply calculations.
10. Ie
= IQUIESCENT + IJNPUTS + IDYNAMle
Ie
= Iec+AlCCDHNT+ICCD(fd2 + fINI)
Icc
= Quiescent Current with CMOS input levels
Alee = Power Supply Current for a TTI.. HIGH input
(VIN=3.4V)
DH
= Duty Cycle for TTI.. inputs HIGH
rnA!
MHz
= Numberof TTI.. inputs at iJJI
= Dynamic Current caused by an input transition pair
(HUIor LHL)
fo
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
NI
= Number of inputs changing at fl
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the Icc formula. These
limits are guaranteed but not tested.
9-144
NT
Iccn
CY54/74FCT2373T
CY54/74FCT2573T
8-Bit Latches
Features
• Function and pinout compatible with
the fastest bipolar logic
• 2Sn output series resistors to reduce
transmission line reflection noise
• FCT-C speed at 4.7 ns max. (Com'l)
FCT-A speed at 5.2 ns max. (Com'l)
• Rednced VOH (typically=3.3V) versions of equivalent FCT functions
• Edge-rate control circuitry for significantly improved noise characteristics
• Power-off disable feature
• Matched rise and fall times
• ESD > 2000V
• Fully compatible with TTL input and
output logic levels
• Sink current
12 mA (Com'I),
12mA (Mil)
Source current
15 mA (Com'I),
12 mA (Mil)
Functional Description
The FCT2373T and FCT2573T are 8-bit
high-speed CMOS TTL-compatible buff:
ered .latches with three·state outputs that
are Ideal for driving high-capacitance
loads, such as memory and address buffers. On-chip 2Sn termination resistors
have been added to the outputs to reduce
system noise caused by reflections.
FCT2373T can be used to replace
Logic Symbol
FCT373T, and FCT2573T to replace
FCTS73T to reduce noise in an existing
design.
~hen latch enable (LE) is HIGH, the
flip-flops appear transparent to the data.
Data that meets the required set-up times
are latched when LE transitions from
HIGH to LOW: Data appears on the bus
when the output enable (DE) is LOW:
When output enable is HIGH, the bus
output is in the high impedance state. In
this mode, data can still be entered into
the latches.
The ~)Utputs are designed with a poweroff disable feature to allow for live insertion of boards.
Pin Configurations
DIP/SOIC/QSOP
Top View
LeC
Top View
OE
Vee
0,
D,
00
8
OE
7 6 5 4
03 9
FCT2373T·l
GND
LE
04
D_
10
11
12
13
FCT2373T
3
2
Do
00
,
OE
20
19
14 1516 1718 "
Do
D,
D.
0,
O.
Vee
02
0,
0,
D2
D3
D.
D_
O.
O.
GND
LE
r!f'o"'c'fr!PrS
FCT2373'f.4
FCT2373T-5
LeC
Top View
~~68~
Logic Block Diagram
8 7 6 5 4
D,
GND
9
10
LE
11
0,
12
13
O.
3
2
1
FCT2573T
20
19
D,
Do
OE
Vee
00
14 1516 1718
r!f'o"o"'r5'O"
FCT2373T·6
DIP/SOIC/QSOP
Top View
00
0,
02
o.
06
07
FCT2373Hl
OE
Vee
Do
D,
00
0,
D2
O2
D.
03
D_
O_
D,
O.
O.
De
D,
GND
0,
LE
FCT2373T-7
9-146
CY54/74FCT2373T
CY54/74FCT2573T
(;;EYPRESS
Capacitance[6J
Parameter
Description
Typo [5J
Max.
Unit
CIN
Input Capacitance
6
10
pF
CoUT
Output Capacitance
8
12
pF
Power Supply Characteristics
1YpJ5J
Max.
Unit
Icc
Quiescent Power Supply Current
Vee=Maxo, VIN$002Y,
VIN""Vee- 002V
001
002
rnA
Mee
Quiescent Power Supply Current
(TIL inputs)
Vee=Maxo, VIN=3.4y,[8J
fl =0, Outputs Open
005
200
rnA
IceD
Dynamic Power Supply
Currend9J
Vee= Max., One Input ThggIiogL50% Duty Cycle, Outputs Open, OE=GND,
VIN$0.2Vor VIN"" Vee-O.2V
0.06
0.12
Ie
Total Power Supply CurrendlOJ
Vee=Max., 50% Duty Cycle,
Outputs Open,
One Bit Thggling at fl = 10 MHz,
OE=GND, LE=Vee,
VIN$0.2Vor VIN""Vee-0.2V
0.7
1.4
rnA
Vee=Max.,
50% Duty Cycle, Outputs Open,
One Bit Thggling at fl =10 MHz,
OE=GND, LE=Vee,
VIN=3.4Vor VIN=GND
1.0
2.4
rnA
Vee=Max.,
50% Duty Cycle, Outputs Open,
§jght Bits Toggling at fl =2.5 MHz,
OE=GND, LE=Vee,
VIN$0.2Vor VIN""Vee-0.2V
1.3
2.6[l1J
rnA
Vee=Max.,
50% Duty Cycle, Outputs Open,
~t Bits Toggling at fl =2.5 MHz,
E=GND, LE=Vee
VIN=3.4Vor VIN=GND
3.3
10.6[l1J
rnA
Parameter
Description
Test Conditions
Notes:
8. Per TIL driven input (VIN=3.4V); all other inputs at Vcc or GND.
9. This parameter is not directly testable, but is derived for use in Total
Power Supply calculations.
10. Ic
= IQUIESCENT + IINPlITS + IDYNAMIC
Ic
= Icc+ll.IccDHNT+ICCD(f0/2 + fINI)
Icc
= Quiescent Current with CMOS input levels
Mce = Power Supply Current for a TIL HIGH input
(VIN=3.4V)
DH
= Duty Cycle for TTL inputs HIGH
roN
MHz
NT
= Number of TIL inputs at DH
ICCD = Dynamic Current caused by an input transition pair
(HLHor LHL)
fo
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
fl
NI
= Number of inputs changing at fl
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the Icc formula: These
limits are guaranteed but not tested.
9-148
CY54/74FCT2373T
CY54/74FCT2573T
.iVEYPRESS
Ordering Information
5.1
Military
5.2
Commercial
5.6
Military
8.0
Commercial
8.5
Military
Ordering Information
5.1
Military
5.2
Commercial
5.6
Commercial
8.0
8.5
Document #: 38-00338-A
9-150
CY54/74FCT2374T
CY54/74FCT2574T
Function Table[1]
Inputs
Outputs
D
CP
H
S
L
S
L
L
X
X
H
Z
OE
0
L
H
Maximum Ratings[2, 3]
(Above which the useful life may be impaired, For user guidelines,
not tested,)
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Storage Temperature ................... -65'Cto +150'C
Ambient Temperature with
Power Applied ........................ -65'C to + 135'C
Supply Voltage to Ground Potential ......... -0.5V to +7.0V
DC Input Voltage ........................ -O.5V to +7.0V
DC Output Voltage ...................... -O.5V to + 7.0V
DC Output Current (Maximum Sink Current/Pin) .... 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.5W
Operating Range
Ambient
Temperature
O'Cto +70'C
Range
Commercial
Range
CT,DT
Commercial
T,AT
-40'C to +85'C
SV±5%
All
-55'C to + 125'C
5V ± 10%
Military[4]
Vee
5V±5%
Electrical Characteristics
Parameter
VOH
VOL
RouT
Over the Operating Range
Description
Output HIGH Voltage
Output LOW Voltage
Output Resistance
Min.
'!Yp.l5J
Vee-Min., IOH--15 rnA
Com' I
2.4
3.3
Vee=Min., IOH=-12 rnA
Mil
2.4
3.3
Vee=Min.,IoL=12mA
Com'l
0.3
0.55
V
Vee-Min., IOL-12 rnA
Mil
0.3
0.55
V
Vee=Min., IOL=12 rnA
Com'l
25
40
Q
Vee=Min.,IoL=12mA
Mil
Test Conditions
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresisl 6J
All inputs
VIK
Input Clamp Diode Voltage
Vee-Min., IIN--18 rnA
II
Input HIGH Current
IIH
IlL
20
Max.
Unit
V
V
Q
25
2.0
V
0.8
-1.2
V
Vee=Max., VIN=Vee
5
IlA
Input HIGH Current
Vee=Max., VIN=2.7V
±1
IlA
Input LOW Current
Vee-Max., VIN-0.5V
±1
IOZH
Off State HIGH-Level Output
Current
Vee = Max., VOUT = 2.7V
10
!lA
!lA
IOZL
Off State LOW-Level
Output Current
Vee - Max., VOUT - O.5V
-10
IlA
los
Output Short Circuit Currentl7J
Vee=Max., VOUT=O.OV
-225
rnA
IOFF
Power-Off Disable
Vee=Ov, VOUT-4.5V
±1
IlA
Notes:
1. H = HIGH Voltage Level.
L = LOW Voltage Level
X = Don't Care
Z = HIGH Impedance
S = LOW-to-HIGH clock transition
2. Unless otherwise noted, these limits are over the operating free-air
temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
4. TA is the "instant on" case temperature.
5.
6.
7.
9-152
-0.7
V
V
0.2
-60
-120
'!ypical values are at Vcc=5.0V, TA=+25'C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above nonnal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
CY54/74FCT2374T
CY54/74FCT2574T
~YPRESS
Switching Characteristics Over the Operating Range
FCT2374T/FCT2574T
Military
FCT2374AT/FCT2574AT
Commercial
Military
Commercial
Description
MinJ12]
Max.
MinJ12]
Max.
MlnJ12]
Max.
MinJ12]
Max.
Unit
Fi~
No.3]
tpllI
tpHL
Propagation Delay
Clock to Output
2.0
11.0
2.0
10.0
2.0
7.2
2.0
6.5
ns
1,5
tpZH
tpZL
Output Enable Time
1.5
14.0
1.5
12.5
1.5
7.5
1.5
6.5
ns
1,7,8
tPHZ
tpLZ
Output Disable
Time
1.5
8.0
1.5
8.0
1.5
6.5
1.5
5.5
ns
1,7,8
ts
Set-Up Time,
HIGH or LOW
DtoCP
2.0
2.0
2.0
2.0
ns
4
tH
Hold Time,
HIGH or LOW
DtoCP
1.5
1.5
1.5
1.5
ns
4
tw
Clk Pulse Width
HlGH or LOW
6.0
7.0
6.0
5.0
ns
5
Parameter
Fi
Parameter
No.~3]
Description
tpllI
tpHL
Propagation Delay
Clock to Output
2.0
6.5
2.0
ns
1,5
tPZH
tpZL
Output Enable Time
1.5
6.9
1.5
ns
1,7,8
tpHZ
tpLZ
Output
6.5
1.5
ns
1,7,8
ts
Set-U Time, HIGH or LOW
Dto P
2.0
1.5
ns
4
1.0
1.0
tH
6
Time
Notes:
12. Minimum limits are guaranteed but not tested on Propagation DeJays.
13. See "Parameter Measurement Information" in the General Information section.
9-154
4
CY54/74FCT2541T
8-Bit BufferlLine Driver
Features
• Function and pinout compatible with
FCT and F logic
• FCT-C speed at 4.1 ns max. (Com'l)
FCT-A speed at 4.8 ns max. (Com'l)
• 2SQ output series to reduce
transmission line reflection noise
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly improved noise
characteristics
• Power-off disable feature
• ESD > 2000V
termination resistors have been added to
the outputs to reduce system noise caused
by reflections. The FCf2541T can be
used to replace the FCf541 T to reduce
noise in an existing design. The speed of
the FCT2541T is comparable to bipolar
logic counterparts while reducing power
dissipation. The input and output voltage
levels allow direct interface with TTL,
NMOS, and CMOS devices without
external components.
The outputs are designed with a
power-off disable feature to allow for live
insertion of boards.
• Matched rise and fall times
• Fully compatible with TTL input and
output logic levels
12 rnA (Com'I),
• Sink current
12 rnA (Mil)
Source current
15 rnA (Com'I),
12 rnA (Mil)
• Three-state outputs
Functional Description
The FCT2541 T is an octal buffer and line
driver designed to be employed as a
memory address driver, clock driver, and
bus-oriented transmitter/receiver. On-chip
Logic Block Diagram
Pin Configurations
OEA
OE.
Do
00
D,
0,
D2
02
CD
D3
03
D_
O_
D,
0,
D,
o.
07
07
DIP/SOIC/QSOP
Top View
LCC
Top View
o
LO
OEA
'lit" roC\!
Do
CI 0 0 0
D,
8 7 6 5 4
D7
GND
07
3
2
1
o.
10
11
12
20
0,
13
19
D,
Do
D2
00
0,
D3
02
OEA
Vee
OE.
D_
1415 161718
o"¢o'"
ON O
&
FCT2541T·1
Function Tabid!]
Inputs
OEA
OEB
D
Output
L
L
H
L
L
H
L
H
X
L
H
Z
Note:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedence
9-156
Vee
OE.
Ds
D5
0_
D.
05
07
GNO
0,
07
FCT2541T·2
1z~YPRESS
CY54/74FCT2541T
Power Supply Characteristics
'JYp.l5]
Max.
Unit
Icc
Quiescent Power Supply Current
Vcc=Max., VIN,;;0.2V,
VIN2: Vcc-0.2V
0.1
0.2
rnA
Mcc
Quiescent Power Supply Current
(TIL inputs)
V cc=Max., VIN=3.4V,[8] f1 =0,
Outputs Open
0.5
2.0
rnA
ICCD
Dynamic Power Supply
Current[9]
Vcc=Max., 50%puty Cycle, Outputs Open,
One Bit 'lbggIing,
OEA=OEB=GND, VIN,;;O.2Vor
VIN2: Vcc-0.2V
0.06
0.12
Ic
'lbtal Power Supply Current[lO]
V cc= Max., 50% Duty Cycle, Outputs Open,
One Bit 'lbggling at f1 = 10 MHz,
OEA=OEB=GND,vIN,;;0.2Vor
VIN2: Vcc-0.2V
0.7
1.4
rnA
Vcc=Max., 50% Duty Cycle, Outputs Open,
One Bit'lbggling at £1=10 MHz,
OEA=OEB=GND, VIN=3.4Vor
VIN=GND
1.0
2.4
rnA
V cc= Max., 50% Duty Cycle, Outputs Open,
Bits 'lbggling at £1 =2.5 MHz,
OEA=OEB=GND, VIN,;;0.2Vor
VIN2: Vcc-0.2V
1.3
2.6[11]
rnA
V cc=Max., 50% Duty Cycle, Outputs Open,
§ight Bits 'lbggling at £1 =2.5 MHz,
OEA=OEB=GND, VIN=3.4Vor
VIN=GND
3.3
10.6[11]
rnA
Parameter
Description
Test Conditions
mAl
MHz
~t
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at Vec or GND.
9. This parameter is not directly testable, but is derived for use in 'Ibtal
Power Supply calculations.
10. Ic
= IQUIESCENT + IINPUTS + IDYNAMIC
Ie
= Ice+<1.IeeDHNT+lcco(fol2 + fINI)
Ice
= Quiescent Current with CMOS input levels
Mce = Power Supply Current for a TTL HIGH input
(VIN=3.4V)
DH
= Duty Cycle for TTL inputs HIGH
NT
= Number of TTL inputs at DH
Iccn
= Dynamic Current caused by an input transition pair
(HLHor LHL)
fo
= Clock frequency for registered devices, otherwise zero
fl
= Input signal frequency
NI
= Numberofinputschangingatfl
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the Ice formula. These
limits are guaranteed but not tested.
9-158
CY54/74FCT2543T
8-Bit Latched Transceiver
Features
• Function and pinout compatible with
FCT and F logic
• FCT-C speed at 5.3 ns max. (Com'l)
FCT-A speed at 6.5 ns max. (Com'l)
• 2SW output series resistors to reduce
transmission line reflection noise
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly improved noise
characteristics
• Power-oft' disable feature
• Matched rise and fall times
• Fully compatible with TTL input and
output logic levels
12 rnA (Com'I),
• Sink current
12 rnA (Mil)
15 rnA (Com'I),
Source current
12rnA (Mil)
latches transparent; a subsequent LOWto-HIGH transition of the LEAB signal
puts the A latches in the storage mode
and their output no longer change with
the A inputs. With CEAB and OEAB
both Law, the three-state B output buffers are active and reflect data present at
the output of the A latches. Control of
data from B to A is similar, but uses
CEAB, LEAB, and OEAB inputs. Onchip termination resistors have been added to the outputs to reduce system noise
caused by reflections. The FCT2543T can
be used to replace the FCT543T to reduce noise in an existing design.
The outputs are designed with a poweroff disable feature to allow for live insertion of boards.
• Separation controls for data flow in
each direction
• Back to back latches for storage
• ESD > 2000V
Functional Description
The FCT2543T Octal Latched Thanceiver
contains two sets of eight ~e latches.
Separate Latch EntlE13fAB, LEBA)
and Output Enable a
, OEBA) permits each latch set to have independent
control of inputting and outputting in either direction of data flow. For data flow
from A to B, for example, the A-to-B Enable (CEl'ill) input must be LOW to enter data from A or to take data from B, as
indicated in the truth table. With CEAB
Law, a LOW signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B
Functional Block Diagram
Pin Configurations
LeC
ThpView
r--------------.,
~
I
I
I
DotailA
DQ
I
I
I
I
I
Bo
A,
CEAB
GND
NC
0EJIIj
_.J
A, __~----L--L~-------L~__ B,
~
mEi
B,
12
13
14
15
16
17
18
..
~
~
A4
DotailAx7
~
L
____
NC
1920 2122 23 24 25
(0
28
27
28
Vee
CE!j)\
Bo
to "'="01.")(\1 .....
FCT2543T-2
B,
n ........-
~
0Ell)(
I:EBA
mIDCOZmmm
~
~
111098765
DIP/SOIC/QSOP
Top View
CEAB
FCT2543T-1
I:EBA
Vee
0EBl\
CE!j)\
Bo
~
A,
B,
~
~
~
~
A4
B,
B.
~
~
A,
CEAB
GND
•
B,
=
0EAlI
FCT2543T-3
9-160
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
ROUT
Min.
typJ7J
Vee=Min., IOH=-15 rnA
Com'l
2.4
3.3
V
Vee=Min., IOH=-12 rnA
Mil
2.4
3.3
V
Description
Output HIGH Voltage
Output LOW Voltage
Output Resistance
Vm
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[B]
Thst Conditions
Max.
Unit
Vee=Min., IOL=12 rnA
Com'l
0.3
0.55
V
Vee=Min., IOL=12 rnA
Mil
0.3
0.55
V
Vee=Min., IOL=12 rnA
Com'l
25
40
Q
Vee=Min., IOL=12 rnA
Mil
20
25
Q
2.0
V
0.8
All inputs
0.2
-0.7
V
V
-1.2
V
VIK
Input Clamp Diode Voltage
Vee=Min., IIN=-18 rnA
1m
Input HIGH Current
Vee=Max., VIN=Vcc
5
1m
Input HIGH Current
Vee=Max., VIN=2.7V
±1
IlL
Input LOW Current
Vee=Max., VIN=0.5V
±1
IOZH
Off State HIGH-Level Output
Current
Vee = Max., VOUT = 2.7V
15
!lA
!lA
!lA
!lA
IOZL
Off State WW-Level
Output Current
Vee = Max., VOUT = O.5V
-15
!lA
los
Output Short Circuit Currentl9]
Vee=Max., VOUT=O.OV
-225
rnA
IOFF
Power-Off Disable
Vee=OV; VouT=4.5V
±1
!lA
-60
-120
Capacitance[8]
1YP. [7]
Max.
Unit
CIN
Input Capacitance
5
10
pF
CoUT
Output Capacitance
9
12
pF
Parameter
Description
Thst Conditions
Notes:
7. 1YPical values are at Vcc=S.Ov, TA=+25'C ambient.
8. This parameter is guaranteed but not tested.
9. Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus andlor sample and hold techniques are preferable in order
9-162
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above nonnal and thereby cause
invalid readings in other parametrics tests. In any sequence of
parameter tests, loS tests should be performed last.
=:'~YPRESS~~~~~~~~~~~~=CY=5=4=/7=4F=C=T=25=4~3T
Switching Characteristics Over the Operating Range
FCT2543T
Military
FCT2543AT
Comm~rcial
Military
Commercial
Description
MinJ14]
Max.
MinJ14]
Max.
MioJ14]
Max.
MinJ 141
Max.
Unit
Fili.'
No. 51
tpLH
tpHL
Propagation Delay
llansparent Mode
AtoBorBtoA
2.0
10.0
2.5
8.5
2.5
7.5
2.5
6.5
ns
1,3
tpLH
tpHL
Propration Delay
lEB toA
LEABtoB
2.5
14.0
2.5
12.5
2.5
9.0
2.5
8.0
ns
1,5
tpZH
tpZL
gutput Enable Time
EBAorOEAB
toAorB
CEBA or CEAB to
AorB
2.0
14.0
2.0
12.0
2.0
10.0
2.0
9.0
ns
1,7,8
tPZH
tpZL
Output Disable Time
OEBAorOEAB
toAorB
CEBAor CEAB
toAorB
2.0
13.0
2.0
9.0
2.0
8.5
2.0
7.5
ns
1,7,8
ts
Set-UpTime
HIGH or LOW,
AorBto
LEBA or LEAB
3.0
2.0
2.0
2.0
ns
9
tH
Hold Time
HIGH or LOW,
AorBto
LEBAorLEAB
2.0
2.0
2.0
2.0
ns
9
tw
Pulse Width LOW
LEBAorLEAB
5.0
5.0
5.0
5.0
ns
5
Parameter
Parameter
Description
MinJ14]
Max.
MinJ14]
Fi
No.1i.'5]
tpLH
tPHL
Propagation Delay
llansparent Mode A to B or B to A
2.5
6.1
2.5
5.5
ns
1,3
tpLH
tpHL
Propagation Delay
LEBA to A, LEAB to B
2.5
8.0
2.5
7.0
ns
1,5
tpZH
tPZL
Output
OEBA
CEBA
2.0
9.0
2.0
8.0
ns
1,7,8
tpZH
tpZL
Output Disable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
2.0
7.5
2.0
6.5
ns
1,7,8
ts
Set-Up Time HIGH or LOW,
A or B to lEBA or LEAI3
2.0
2.0
ns
9
2.0
2.0
tH
9
Notes:
14. Minimum limits are guaranteed but not tested on Propagation Delays.
15. See "Parameter Measurement Information" in the General Information Section.
9-164
CY54/74FCT2646T
CY54/74FCT2648T
8-Bit Registered Transceivers
Features
• Function and pinout compatible with
FCT and F logic
• FCT-C speed at 5.4 ns max. (Com'l)
FCT-A speed at 6.3 ns max. (Com'l)
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functions
• 25Q output series resistors to reduce
transmission line reflection noise
• Reduced VOH (typically=3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly improved noise
characteristics
• Power-otT disable feature
• Matched rise and fall times
• ESD> 2000V
• Fully compatible with TTL input and
output logic levels
12 mA (Com'I),
• Sink current
12 mA (Mil)
15 mA (Com'I),
Source current
12mA (Mil)
• Independent register for A and B
buses
• Three-state output
Functional Description
The FCT2646T and FCT2648T consist of
a bus transceiver circuit with three-state,
D-type flip-flops, and control circuitry
arranged for multiplexed transmission of
data directly from the input bus or from
the internal registers. Data on the A or B
bus will be clocked into the registers as
the appropriate clock pin goes to a HIGH
logic level. Enable Control G and
direction pins are provided to control the
transceiver function. On-chip termination
resistors have been added to the outputs
to reduce system noise caused. by
reflections so that the FCT2646T and the
FCT2648T can be used to replace the
FCT646T and the FCT648T, respectively,
in an existing design.
In the transceiver mode, data present at
the high impedance port may be stored in
either the A or B register, or in both.
Select controls can multiplex stored and
real-time (transparent mode) data. The
direction control determines which bus
will receive data when the enable control
G is Active LOW. In the isolation mode
(enable control G HIGH), A data may be
stored in the B register and/or B data may
be stored in the A register.
The outputs are designed with a
power-off disable feature to allow for live
insertion of boards.
Pin Configurations
Functional Block Diagram
Gi-~.......""""
LCC/PLCC
ThpView
DIRI-~---l...J--r------:----------,
DIP
ThpView
C P B A , - - - - - - _ + _ - - - : - - - : - - I ><>------h
CPAB
s~,-_=_----_+_-1
A,
GND
As
12
1.
14
NC
15
DIR
SAB
CPAB
NC
B. 16
S, 17
Be
28
Vee
27
CP~
18 1920 2122 23 24 25 26
S~
FCT2646T-2
H+i-'II'VIr-
Vee
CP~
SAB
1110 9 8 7 6 5
CPAB
SABI---t---+-/
S~
DIR
A,
G
A2
B,
As
As
As
As
B2
A,
B.
8,
As
B,
B,
B,
=
GND . .:::...._ _
B,
Logic Block Diagram
Be
FCT2646T-3
SAB
CIR
CP~
S~
FCT2646T ONLY
FCT2646T ONLY
TO 7 OTHER CHANNELS
G
FCT2646T·1
FCT2646T-4
Pin Description
A
Name
Description
Data Register A Inputs, Data Register B Outputs
B
Data Register B Inputs, Data Register A Outputs
CPAB,CPBA
Clock Pulse Inputs
SAB,SBA
Output Data Source Select Inputs
DIR,G
Output Enable Inputs
9-166
~
CY54/74FCT2646T
_;CYPRESS ============;;;;;CY~5;;;;;;4/;;;;;74;;;F~C;;;;;;T2;;;;6;;;;;;48~T
Maximum Ratings[4,5j
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................... -65°C to + 150°C
Ambient Temperature with
Power Appliea .............. , ......... -65°C to + 135°C
Supply Voltage to Ground potential ......... -O.5V to + 7.0V
DC Input Voltage ........................ -0.5V to + 7.0V
DC Output Voltage ...................... -0.5V to + 7.0V
DC Output Current (Maximum Sink Current/Pin) .... 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O.5W
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Operating Range
Ambient
Temperature
O°Cto +70°C
Range
Commercial
Range
CT
Commercial
T,AT
-40°C to +85°C
5V±5%
All
-55°C to + 125°C
5V ± 10%
Military[6j
Vee
5V±5%
Electrical Characteristics Over the Operating Range
Parameter
Min.
'!YpJ7J
Vee=Min., IOH=-15 rnA
Com'l
2.4
3.3
V
Vee=Min., IOH=-12mA
Mil
2.4
3.3
V
Vee=Min., IOL=12 rnA
Com'l
Description
Output HIGH Voltage
VOH
VOL
Output LOW Voltage
RoUT
Output Resistance
Test Conditions
Vee=Min., IOL=12 rnA
Mil
Vee=Min., IOL=12 rnA
Com'l
Vee=Min., IOL=12 rnA
Mil
20
Max.
Unit
0.3
0.55
V
0.3
0.55
V
25
40
Q
25
Q
2.0
Vlli
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[8]
All inputs
V
0.8
V
V
0.2
VIK
Input Clamp Diode Voltage
Vee=Min., IIN=-18 rnA
-1.2
V
1IH
Input HIGH Current
Vee=Max., VIN=Vee
-0.7
5
IIH
Input HIGH Current
Vee = Max., VIN=2.7V
±1
IlL
Input LOW Current
Vee=Max., VIN=O.5V
los
Output Short Circuit Current[9]
Vee=Max., VOUT=O.OV
IOFF
Power-Off Disable
Vee=Ov, VOUT=4.5V
-60
-120
±1
IJA
IJA
IJA
-225
rnA
±1
IJA
Capacitance[8]
'.
'Jyp. [7J
Max.
Unit
CIN
Input Capacitance
6
10
pF
COUT
Output Capacitance
8
12
pF
Parameter
Description
Notes:
4.
Unless otherwise noted, these limits are over the operating free-air
temperature range.
Unused inputs must alway;. be connected to an appropriate logic voltage level, preferably either Vee or ground.
6. TA is the "instant on" case temperature.
7. 1YPical values are at Vcc=5.0V, TA=+25'C ambient.
8. This parameter is goaranteed but not tested.
9,
5.
9-168
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus andlor sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
~
CY54/74FCT2646T
~~YPRESS========================CY~5~~~74~F~C~T2~6~48~T
Switching Characteristics Over the Operating Range
FCf2646T/FCT2648T
Military
FCT2646AT/FCT2648AT
Commercial
Military
Commercial
Description
MinJ14]
Max.
MinJ14]
Max.
MinJ14]
Max.
MinJ14]
Max.
Unit
Fi~
No.5]
tpLH
tpHL
Propagation Delay
Busto Bus
1.5
11.0
1.5
9.0
1.5
7.7
1.5
6.3
ns
1,3
tpZH
tpZL
Output Enable Time
Enable to Bus and
DIR to An or Bn
1.5
15.0
1.5
14.5
1.5
10.5
1.5
9.8
ns
1,7,8
tpHz
tpLZ
Output Disable
Time
Gto Bus and
DIR to Bus
1.5
11.0
1.5
9.0
1.5
7.7
1.5
6.3
ns
1,7,8
tpLH
tpHL
Propagation Delay
Clock to Bus
1.5
10.0
1.5
9.0
1.5
7.0
1.5
6.3
ns
1,5
tpLH
tpHL
Propagation Delay
SBAor SAB
toAorB
1.5
12.0
1.5
11.0
1.5
8.4
1.5
7.7
ns
1,5
ts
Set-UpTime
HIGH or LOW,
Busto Clock
4.5
4.0
2.0
2.0
ns
4
tH
Hold Time
HIGH or LOW,
Busto Clock
2.0
2.0
1.5
1.5
ns
4
tw
Pulse Width,[6]
HIGH or LOW
6.0
6.0
5.0
5.0
ns
5
Parameter
FCT2646CT/FCT2648CT
Military
Parameter
Description
Commercial
MinJ14]
Max.
MinJ14]
Max.
Unit
Fi~
No.5]
tpLH
tpHL
Propagation Delay
Busto Bus
1.5
6.0
1.5
5.4
ns
1,3
tpZH
tpZL
Output Enable Time
Enable to Bus and DIR to An or Bn
1.5
8.9
1.5
7.8
ns
1,7,8
tpHZ
tpLZ
Qutput Disable Time
G to Bus and DIR to Bus
1.5
7.7
1.5
6.3
ns
1,7,8
tpLH
tpHL
Propagation Delay
Clock to Bus
1.5
6.3
1.5
5.7
ns
1,5
tpLH
tpHL
Propagation Delay
SBA or SAB to A or B
1.5
7.0
1.5
6.2
ns
1,5
4
ts
Set-Up Time HIGH or LOW, Bus to Clock
2.0
2.0
ns
tH
Hold Time HIGH or LOW, Bus to Clock
1.5
1.5
ns
4
tw
Pulse Width,[6] HIGH or LOW
5.0
5.0
ns
5
Notes:
14. Minimum limits are guaraoteed but not tested on Propagation Delays.
15. See "Parameter Measurement Information" in tbe General Information Section.
9-170
CY54/74FCT2652T
8-Bit Registered Transceiver
Features
• Function and pinout compatible with
FCT and F logic
• FCT-C speed at 5.4 ns max. (Com'l)
FCT-A speed at 6.3 ns max. (Com'l)
• 25Q output series resistors to reduce
transmission line reflection noise
• Reduced VOH (typically = 3.3V)
versions of equivalent FCT functions
• Edge-rate control circuitry for
significantly improved noise
characteristics
• Power-oft' disable feature
• Matched rise and fall times
• Fully compatible with TTL input and
output logic levels
12 rnA (Com'I),
• Sink current
12 rnA (Mil)
Source current
15 rnA (Com'I),
12rnA (Mil)
• ESD > 2000V
• Independent register for A and B
buses
• Multiplexed real-time and stored data
transfer
occurs in a multiplexer during transition
between stored and real-time data. A
LOW input level selects real-time data
and a HIGH selects stored data.
Data on the A or B data bus, or both, can
be stored in the internal D flip-flops by
LOW-to-HIGH transitions at the
appropriate clock pins (CPAB or CPBA),
regardless of the select or enable control
pins. When SAB and SBA are in the
real-time transfer mode, it is also possible
to store data without using the internal
D-type flip-flops by simultaneously
enabling GAB and GBA. In this
configuration, each output reinforces its
input. Thus, when all other data sources
to the two sets of bus lines are at high
impedance, each set of bus lines will
remain at its last state.
The outputs are designed with a
power-off disable feature to allow for live
insertion of boards.
Functional Description
The FCf2652T consists of bus transceiver
circuits, D-type flip-flops, and control
circuitry arranged for multiplexed
transmission of data directly from the
input bus or from the internal storage
registers. GAB and GBA control pins are
provided to control the transceiver
functions. SAB and SBA control pins are
provided to select either real-time or
stored data transfer.
On-chip termination resistors are added
to the outputs to reduce system noise
caused by reflections. The FCT2652T can
replace the FCT652T to reduce noise in
an existing design.
The circuitry used for select control will
eliminate the typical decoding glitch that
Logic Block Diagram
Pin Configurations'
LCC
Top View
CPBA
GAB
SBA
A7
BAB--~:~------------------~
Aa
GND
NC
88
~
CPAB
S.
BREG
-,
I
I
I
I
I
I
I
o
I
I
I
I
I
I
I
.J
~----------------v-----------------~
TO 7 OTHER CHANNELS
111098765
12
13
14
15
16
17
28
27
1819202122232425 26
ceo at
GAB
SAB
CPAB
NC
Vee
CPBA
SBA
m~ ~ mNall~
FCT2652T-2
DIP/SOlC/QSOP
Top View
Bj
CPAB
SAB
GAB
Vee
CPBA
SBA
A,
llllA .
Aa
Aa
B2
~
B,
As
B.
Aa
B.
A7
S.
B,
Aa
~
GND
Be
FCT2652T-1
FCT2652T-3
9-172
.~YPRESS
CY54/74FCT2652T
Function Table[l]
Inputs
DataI/O
GAB
GBA
CPAB
CPBA
SAB
SBA
Al thruAs
BI throBs
L
L
H
H
HorL
S
HorL
S
X
X
X
X
Input
Input
X
H
H
HorL
S
X
X[l]
X
X
Input
Input
Un~ecified[2]
S
S
X
X
X
X[l]
Un~ecified[2]
utput
Input
Input
Hold A, Store B
Store B in both registers
X
X
X
L
H
Output
Input
HorL
Real-Time B Data to A Bus
Stored B Data to A Bus
H
S
S
Operation or Function
Isolation
Store A and B Data
utput
Store A, Hold B
Store A in both registers
L
L
X
L
HorL
S
L
L
L
L
X
X
H
H
H
H
X
X
L
H
X
X
Input
Output
HorL
Real-Time A Data to B Bus
Stored A Data to B Bus
H
L
HorL
HorL
H
H
Output
Output
Stored A Data to B Bus
and Stored B Data to A Bus
X
Maximum Ratings[3, 4]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 301S)
Storage Thmperature ................... -65°C to + 150°C
Ambient Thmperature with
Power Applied ........................ -65°C to + 135°C
Supply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC Input Voltage ........................ -O.SV to + 7.0V
DC Output Voltage ...................... -O.SV to +7.0V
DC Output Current (Maximum Sink Current/Pin) .... 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O.SW
Operating Range
Notes:
1. Select control=L: clocks can occur simultaneously.
Select control=H: clocks must be staggered in order to load both
registers. H = HIGH Voltage Level. L = LOW Voltage Level.
X = Don't Care.
2. The data output functions may be enabled or disabled by various
signals at the GAB or GBA inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every
LOW-to-HIGH transition on the clock inputs.
Range
Ambient
Temperature
O°Cto +70°C
Commercial
Range
CT,DT
Commercial
T,AT
-40°C to +8SoC
SV±S%
All
-S5°C to + 125°C
SV ± 10%
MiIitary[5]
Vee
SV±5%
3. Unless otherwise noted, these limits are over the operating free-air
temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
S. TA is the "instant on" case temperature.
9-174
.~YPRESS
CY54/74FCT2652T
Power Supply Characteristics
'iYpJ6]
Max.
Unit
lee
Quiescent Power Supply Current
Vee=Max., VINsO.2V,
VIN;;' Vee-0.2V
0.1
0.2
rnA
Alee
Quiescent Power Supply Current
(TIL inputs HIGH)
Vee=Max., VIN=3.4v,[9]
f1=0, Outputs Open
0.5
2.0
rnA
IeeD
Dynamic Power Supply
Currend lO]
Vee- Max., One Input Toggling,
50% Duty Cycg' Outputs Open,
GAB=GND, BA=GND,
VINsO.2Vor VIN;;' Vee-0.2V
0.06
0.12
Ie
lbtal Power Supply Currend ll ]
Vee= Max., fo= 10 MHz,
50% Duty Cycle, Outputs Open,
One Bit Toggling at f1 =5 MHz,
GAB=GND, GBA=GND,
SAB = CPAB = GND
SBA=Vee,
VINsO.2Vor VIN;;' Vee-0.2V
0.7
1.4
rnA
Vee=Max., fo=lO MHz,
50% Duty Cycle, Outputs Open,
One Bit lbggling at fl =5 MHz,
GAB=GND, GBA=GND,
SAB = CPAB = GND
SBA=Vee,
VIN=3.4Vor VIN=GND
1.2
3.4
rnA
Vee-Max., fo=10 MHz,
50% Duty Cycle, Outputs Open,
Eigltt Bits lbggling at fl =5 MHz,
GAB=GBA=GND,
SAB=CPAB=GND
SBA=Vee,
VINsO.2Vor VIN;;,Vee-0.2V
2.8
5.6[12]
rnA
Vee=Max., 1'0=10 MHz, 50% Duty Cycle,
Outputs Open,
Eight Bits lbggling at fl =5 MHz,
GAB=GBA=GND,
SAB=CPAB=GND
SBA=Vee,
VIN=3.4Vor VIN=GND
5.1
14.6[12)
rnA
Parameter
Description
Test Conditions
Note.:
9. Per TIL driven input (VIN=3.4V); all other inputs at Vecor GND.
10. This parameter is not directly testable, but is derived for use in Thtal
Power Supply calculations.
11. Ic
= IQUIESCENT + IINPUTS + IDYNAMIC
Ic
= Icc+2001 V
(per MIL-STD-883, Method 3015)
Operating Range
CT
Ambient
Temperature
OCCto +70°C
Vee
5V±5%
AT,BT
-40°C to +85°C
5V±5%
All
-55°C to + 125°C
5V ± 10%
Range
Commercial
Range
Commercial
Military[4]
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
Min.
typJ5]
Max.
Unit
Vce=Min., IOH=-15 rnA
Com'l
2.4
3.3
V
Vee=Min., IOH=-12 rnA
Mil
2.4
3.3
V
Vce=Min., IOL=12 rnA
Com'l
0.3
0.55
Vee=Min., IOL=12 rnA
Mil
0.3
0.55
V
Vce=Min., IOL=12 rnA
Com'l
25
40
Q
Vce=Min., IOL=12 rnA
Mil
ROUT
Output Resistance
Vm
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Hysteresis[6]
All inputs
VIK
Input Clamp Diode Voltage
Vce=Min., IIN=-18 rnA
II
Input HIGH Current
1m
Input HIGH Current
IlL
IOZH
20
V
Q
25
2.0
V
0.8
V
0.2
-0.7
V
-1.2
V
Vee=Max., VIN=Vee
5
Vcc=Max., VIN=2.7V
±1
Input LOW Current
Vee=Max., VIN=O.5V
±1
Off State HIGH-Level Output
Current
Vee = Max., VOUT = 2.7V
10
J.IA
J.IA
J.IA
J.IA
IOZL
Off State LOW-Level
Output Current
Vee = Max., VOUT = O.5V
-10
J.IA
los
Output Short Circuit Current[7]
Vee=Max., VOUT=O.OV
-225
rnA
IOFF
Power-Off Disable
Vee=OV; VOUT=4.5V
±I
J.IA
-60
-120
Capacitance[6]
'iYP. [5]
Max.
Unit
CIN
Parameter
Input Capacitance
Description
5
10
pF
COUT
Output Capacitance
9
12
pF
Notes:
2. Unless otherwise noted, these limits are over the operating free-air
temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
4. TA is the "instant on" case temperature.
5. 'lYPical values are at V cc=5.0V, TA = +25"C ambient.
6. This parameter is gnaranteed but not tested.
7.
9-180
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
CY54/74FCT2827T
Switching Characteristics Over the Operating Range
FCT2827BT
FCT2827AT
Military .
Commercial
Military
Commercial
MinJ13] Max. MinJ13] Max. MinJ13] Max. MinJ13] Max. Unit
Fi
No.~2]
Param,
Description
ThstLoad
tpLH
tpHL
Propagation Delay
DtoY
CL=50pF
RL=500Q
1.5
9.0
1.5
8.0
1.5
6.5
1.5
5.0
ns
1,3
tpLH
tpHL
Dtoy6]
CL=300pF
RL=500Q
1.5
17.0
1.5
15.0
1.5
14.0
1.5
13.0
ns
1,3
tpZH
tpzL
Output Enable
Time
OEtoY
CL=50pF
RL=500Q
1.5
13.0
1.5
12.0
1.5
9.0
1.5
8.0
ns
1,7,8
tpZH
tpZL
Output Enable
Time
OEtoy[6]
CL=300pF
RL=500Q
1.5
25.0
1.5
23.0
1.5
16.0
1.5
15.0
ns
1,7,8
tpHZ
tpHL
Output Disable
Time
OEtoy[6]
CL=5 pF
RL=500Q
1.5
10.0
1.5
9.0
1.5
7.0
1.5
6.0
ns
1,7,8
tpHZ
tpHL
Output Disable
Time
OEtoY
CL=50pF
RL=500Q
1.5
10.0
1.5
9.0
1.5
8.0
1.5
7.0
ns
1,7,8
Propa~ation
Delay
FCT2827CT
Military
Param.
Description
tpLH
tpHL
Propagation Delay
DtoY
tpLH
tpHL
Propa~ation
tpZH
tpzL
Thst Load
Commercial
Fi
MinJ13] Max. MinJ13] Max. Unit No.0'2]
CL=50pF
RL=500Q
1.5
5.0
1.5
4.4
ns
1,3
CL=300pF
RL=500Q
1.5
11.0
1.5
10.0
ns
1,3
Output Enable Time
OEtoY
CL=50pF
RL=500Q
1.5
8.0
1.5
7.0
ns
1,7,8
tpZH
tpZL
Output Enable Time
OEtoy[6]
CL=300pF
RL=500Q
1.5
15.0
1.5
14.0
ns
1,7,8
tPHZ
tpHL
Output Disable Time
OEto y[6]
CL=5pF
RL=500Q
1.5
6.7
1.5
5.7
ns
1,7,8
tpHZ
tpHL
Output Disable Time
OEtoY
CL=50pF
RL=500Q
1.5
7.0
1.5
6.0
ns
1,7,8
Dtoy6]
Delay
Notes:
12. See "Parameter Measurement Information" in the General Informa·
tion section.
13. Minimum limits are guaranteed but not tested on Propagation Delays.
9-182
CY74FCT16240T
CY74FCT162240T
16-Bit BufferslLine Drivers
CY74FCT16240T Features:
• 64 rnA sink current (Com'I),
32 rnA source current (Com'l)
Features
• Low power, pin compatible
replacement for ABT functions
• lYPical VOLP (ground bounce)
<1.0V at Vee = sv, TA = 2S'C
• FCI'-C speed at 4.3 ns
• Power-off disable outputs permits live
insertion
• Edge-rate control circuitry for
significantly improved noise
chamcteristit;s
• lYPical output skew < 2S0 ps
• ESD > 2000 V
• TSSOP (19,.6-mil pitch) and SSOP
(2S-mil pitch) Pl!ckages
• Extended commercial range of
-40'C to +SS'C
CY74FCT162240T Features:
• Balanced output drivers: 24 rnA
• Reduced system switching noise
• lYPical VOLP (ground bounce)
.ft.2
2'12
~,
,V,
~2
,'12
GND
3'13
3'1,
aAa
Vee
Vee
.Y,
~,
3A.,
,'12
aAa
2'13
~
.'13
sA.
2Y•
~
,V,
FCT16240·4
FCT16240·2
OE
Description
Three-State Output Enable Inputs (Active LOW)
A
Data Inputs
Y
Three-Slate Outputs
Note:
1.
H = HIGH Voltage Level. L = LOW Voltage Level.
X Don't Care. Z High Impedance.
=
GND
,'13
.'1,
~
.OE
30E
~
FCT1624Q-5
Function Table!!]
Pin Summary
Name
~2
GND
=
9-184
Inputs
Outputs
OE
A
y
L
L
H
L
H
L
H
X
Z
CY74FCT16240T
CY74FCT162240T
~
.,CYPRESS
Capacitance[5] (TA = +25°C, f = 1.0 MHz)
Parameter
Description
Test Conditions
'JYp.l4]
Max.
Unit
CIN
Input Capacitance
VIN = OV
4.5
6.0
pF
COUT
Output Capacitance
VOUT = OV
5.5
8.0
pF
'JYpJ4]
Max.
Unit
5
500
iJA
rnA
Power Supply Characteristics
Parameter
Description
Test Conditions
Icc
Quiescent Power Supply Current
Vcc=Max.
VIN,,0.2Y,
VIN2: Vcc-0.2V
6Icc
Quiescent Power Supply Current
(TTL inputs HIGH)
Vcc=Max.
VIN=3.4V[7]
0.5
1.5
ICCD
Dynamic Power Supply
Current[B]
Vcc=Max., One Input
Toggling, 50% I2!!!Y Cycle,
Outputs Open, OE=GND
VIN=Vcc or
VIN = GND
60
100
Ic
Total Power Supply Current[9]
V cc-Max., fl = 10 MHz,
50% Duty Cycle, Outputs
~en, One Bit Toggling,
E=GND
VIN=Vcc or
VIN = GND
0.6
1.5
rnA
VIN=3.4Vor
VIN=GND
0.9
2.3
rnA
V cc=Max., fl =2.5 MHz,
50% Duty Cycle, Outputs
QQ.en, Sixteen Bits 'Ibggling,
OE=GND
VIN=Vcc or
VIN=GND
2.4
4.5[10]
rnA
VIN=3.4Vor
VIN=GND
6.4
16.5[10]
rnA
iJA/
MHz
Switching Characteristics Over the Operating Range
Parameter
Description
CY74FCT16240T
CY74FCT162240T
CY74FCT16240AT
CY74FCT16240CT
CY74FCT162240AT CY74FCT162240CT
Min.l ll ]
Max.
Min.l ll]
Max.
Min.l ll ]
Max.
Unit
No~2]
F'
tpLH
tpHL
Propagation Delay Data to
Output
1.5
8.0
1.5
4.8
1.5
4.3
ns
1,2
tPZH
tpZL
Output Enable Time
1.5
10.0
1.5
6.2
1.5
5.8
ns
1,7,8
tPHZ
tpLZ
Output Disable Time
1.5
9.5
1.5
5.6
1.5
5.2
ns
1,7,8
tSK(O)
Output Skew[13]
0.5
ns
-
0.5
Notes:
7. Per TTL driven input (VIN~3.4V); all other inputs at V cc or GND.
8. This parameter is not directly testable, but is derived for use in Thtal
.Power Supply calculations.
9. Ic
~ IQUIESCENT + IINPUTS + IDYNAMIC
Ic
~ Icc+AIcCDHNT+ICeo(foI2 + fiN,)
Icc
~ Quiescent Current witb CMOS input levels
Alcc ~ Power Supply Current for a TTL HIGH input
(VIN~3.4V)
DH
NT
Iceo
~
~
~
Duty Cycle for TTL inputs HIGH
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair
(HLHor LHL)
0.5
fO
~ Clock frequency for registered devices, otherwise zero
fl
~ Input signal frequency
NI
= Number of inputs changing at fl
All currents are in milliamps and all frequencies are in megahertz.
10. Values for these conditions are examples of the Icc formula. These
limits are guaranteed but not tested.
11. Minimum limits are guaranteed but not tested on Propagation Delays.
12. See "Parameter Measurement Information" in the General
Information Section.
13. Skew between any two outputs of the same package switching in tbe
same direction. This parameter is guaranteed by design.
9-186
CY74FCT16244T/2244T
CY74FCT16444T/2H244T
16-Bit BufferslLine Drivers
Features
• Low p(lwer, pin-compatible
replacement for ABT functions
• FCT-C speed at 4.1 ns
• Power-off disable outputs permits Jive
insertion
• Edge-rate control circuitry for
significantly improved noise
characteristics
• 1YJIical output skew < 2S0 ps
• ESD > 2000 V
• TSSOP (19.6-mll pitch) and SSOP
(2S-mil pitch) packages
• Extended commercial range of
-40·C to +8S"C
• Vee = SV :!: 10%
CY74FCT16244T Features:
• 64 rnA sink current,
32 rnA source current
• 1Ypical VOLP (ground bounce)
<1.0V at Vee = sv, TA.= 2S·C
• Reduced system switching noise
• 1Ypical VOLP (ground bounce)
---+--- ,Y,
,110
'Y2
aA2 - - - - I
>---+--- ,Y,
,As
,Y,
aA3 - - - - I
>---+--- ,Y,
,Ao
,Y,
,Ao - - - - I
>------ ,Y,
FCT16244"2
FCT1624+1
,llE
,A,
,Y,
,110
GND
,Y,
,Y,
,As
vee
Vee
,Y,
aA,
,1'2
,Ao
GND
aA3
aA4
aA,
aA2
2Y'
2Y'
,Y,
'Y2
.oE
,m::
aA,
2Y'
oA,
Vee
Vee
aA2
2Y2
oA2 - - - - I
>---+--- ,Y,
,Y,
'Y2
oA,
.As
aA3
.As - - - - I
>---+--- ,Y,
GND
2Y,
2Y'
4As - - - - I
> - - - - - - ,Y,
,m::
aA4
GND
- - - - - I >---+--
FCT16244·3
,Y,
FCT162444
9-188
GND
,Y,
,Y,
aA3
aA.
GND
,Y,
,Y,
.As
4As
,m::
FCT16244-5
CY74FCT16244T/2244T
CY74FCT16444T/2H244T
'irI2YPRESS
Electrical Characteristics Over the Operating Range
Parameter
Description
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Input Hysteresis[6J
VIK
Input Clamp Diode Voltage
IIH
Input HIGH Current
Test Conditions
Min.
'lYPJ5J
100
-0.7
V cc=Min., IJN= -18 rnA
Standard
Input LOW Current
Standard
Vcc=Max., VI=VCC
Bus Hold Sustain Current on Bus Hold
Input[7J
V
mV
-1.2
V
±1
fAA
±100
Vcc=Max., VI=GND
±1
Bus Hold
IBBH
IBBL
Unit
V
0.8
Bus Hold
hL
Max.
2.0
±100
Vcc=Min.
I Vr=2.0V
-50
IVI=0.8V
+50
fAA
fAA
fAA
I---
TBD
rnA
Vcc=Max., VOUT=2.7V
±1
fAA
Vcc=Max., VOUT=0.5V
±1
fAA
-200
rnA
-180
rnA
±1
fAA
Max.
Unit
IBHHO
IBHLO
Bus Hold Overdrive Current on Bus Hold
Input[7J
Vcc=Max., VI=1.5V
10ZH
High Impedance Output Current
(Three-State Output pins)
10ZL
High Impedance Output Current
(Three-State Output pins)
los
Short Circuit Current[8J
Vcc=Max., VOUT=GND
-80
10
Output Drive Current[6J
Vcc=Max., VOUT=2.5V
-50
IOFF
Power-Off Disable
Vcc=OV; VOUT:s4.5V
-140
Output Drive Characteristics for CY74FCT16244T, CY74FCT16444T
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Min.
lYpJ5J
Vcc=Min., IOH=-3 rnA
2.5
3.5
V
Vcc=Min., IOH=-15 rnA
2.4
3.5
V
Vcc=Min., IOH=-32mA
2.0
3.0
Test Conditions
V cc=Min., IOL =64 rnA
V
0.2
0.55
V
Output Drive Characteristics for CY74FCT162244T, CY74FCT162H244T
Test Conditions
Min.
'lYPJ5J
Max.
Unit
IODL
Output LOW Currend6J
Vcc=5V; VJN=VIH or VIL, VOUT=l.5V
60
115
150
rnA
10DH
Output HIGH Current[6J
Vcc=5V; VJN=VIH or VIL, VOUT=1.5V
-60
-115
-150
rnA
VOH
Output HIGH Voltage
Vcc=Min., 10H=-24 rnA
2.4
3.3
VOL
Output LOW Voltage
Vcc=Min., IOL=24 rnA
0.55
V
Parameter
Description
Note:
5. TYPical values are at Vcc=5.0V; TA=+25"C ambient.
6. This parameter is guaranteed but not tested.
7. Pins with bus hold are described in Pin Description.
8. Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
9-190
0.3
V
apparatus andlor sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
CY74FCT16244T/2244T
CY74FCT16444T/2H244T
Ordering Information CY74FCT16244
Speed
(n8)
4."1
4.8
6.5
Ordering Code
Package
Name
Package 1YPe
CY74FCT16244CTPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16244CTPVC
048
48-Lead (3OO-Mil) SSOP
CY74FCT16244ATPAC
Z48
48-Lead (240-Mil) TSSPP
CY74FCT16244ATPVC
048
48-Lead (3OO-Mil) SSOP
CY74FCT16244TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16244TPVC
048
48-Lead (300-Mil) SSOP
Operating
Range
Commercial
Commercial
Commercial
Ordering
Information CY74FCT162244
.,
Speed
(n8)
4.1
4.8
6.5
Package
Ordering Code
Na~e
Package 1YPe
CY74FCT162244CTPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162244CTPVC
048
48-Lead (3OO-Mil) SSOP
CY74FCT162244ATPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162244ATPVC
048
48-Lead (300-Mil) SSOP
CY74FCT162244TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162244TPVC
048
48-Lead (3OO-Mil) SSOP
Operating
Range
Commercial
Commercial
Commercial
Ordering Information CY74FCT16444
Speed
(n8)
4.1
4.8
6.5
Ordering Code
Package
Name
Package 1YPe
CY74FCT16444CTPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16444CTPVC
048
48-Lead (300-Mil) SSOP
CY74FCT16444ATPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16444ATPVC
048
48-Lead (300-Mil) SSOP
CY74FCTi6444TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16444TPVC
048
48-Lead (300-Mil) SSOP
Operating
Range
Commercial
Commercial
Commercial
Ordering Information CY74FCT162H244
Speed
(n8)
4.1
4.8
6.5
Ordering Code
Package
Name
Package 1YPe
CY74FCT162H244CTPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162H244CTPVC
048
48-Lead (3OO-Mil) SSOP
CY74FCT162H244ATPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162H244ATPVC
048
48-Lead (300-Mil) SSOP
CY74FCT162H244TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162H244TPVC
048
48-Lead (300-Mil) SSOP
Document #: 38-00396
9-192
Operating
Range
Commercial
Commercial
Commercial
CY74FCT16245T/2245T
CY74FCT16445T/2H245T
fiz!l2YPRESS
Logic Block Diagram CY74FCTl6445T
DIR
or
DIR
B,
e,
A, ~1>-+-f---,
GND
'-----++-~c 1-<'- B,
A2 ~1>-+-t----,
'-----++-~c 1-<'- B2
As
....,.-11>--++----,
Ao
....,.-11>--++----,
TO OTHER 12 CHANNELS
FCT16245-4
4
A,
A2
GND
e,
As
B.
Vee
B,;
B,;
GND
Ao
Vee
9
As
As
e,
GND
A,
B8
Bg
B,.
GND
B11
A,.
GND
A11
B'2
Vee
B'3
B"
GND
A'2
Vee
A'3
A"
GND
B'5
B,.
NC
A'5
A,.
NC
As
As
FCT16245-5
Function Thble[2]
Pin Description
Name
Inputs
Description
OE
Three-State Output Enable Inputs (Active LOW)
DIR
Direction Control
OE
DIR
Outputs
L
L
Bus B Data to Bus A
A
Inputs or Three-State Outputsll ]
L
H
Bus A Data to Bus B
B
Inputs or Three-State OutputsL1]
H
X
High Z State
Maximum Ratings[3, 4]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ............ Com'l -55°C to +12SoC
Ambient Thmperature with
Power Applied ................. Com'l -55°C to +12SoC
DC Input Voltage ........................ -O.SV to +7.0V
DC Output Voltage ...................... -O.SV to + 7.0V
DC Output Current
(Maximum Sink Current/Pin) ............. -60 to + 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Static Discharge Voltage ........................ >2001 V
(per MIL-STD-883, Method 3015)
Operating Range
Range
Commercial
Ambient
Thmperature
Vee
-400C to +8S oC
SV ± 10%
Notes:
1.
2.
On CY74FCT162H245T these pins have bus hold.
H HIGH Voltage Level. L LOW Voltage Level.
X Don't Care. Z High Impedance.
3. Operation beyond the limits set forth may impair the useful life of the
device. Unless otherwise noted, these limits are over the operating
free-air temperature range.
=
=
=
=
4.
9-194
Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
CY74FCT16245T/2245T
CY74FCT16445T/2H245T
QYPRESS
Capacitance[6] (TA = +25"C, f = 1.0 MHz)
'J.YpJ5]
Max.
Unit
CIN
Input Capacitance
VIN - OV
4.5
6.0
pF
COUT
Output Capacitance
VOUT = OV
5.5
8.0
pF
'JYpJ5]
Max.
Unit
5
500
J.tA
rnA
Parameter
Description
Test Conditions
Power Supply Characteristics
Parameter
Description
Test Conditions
Icc
Quiescent Power Supply Current
L\Icc
Quiescent Power Supply Current
(TTL inputs HIGH)
Vcc=Max.
VIN=3.4V[9]
0.5
1.5
ICCD
Dynamic Power Supply
Currentl lO]
Vcc=Max., One Input
Thggling, 50% Duty Cycle,
Outputs Open,
OE=DIR=GND
VIN=Vcc or
VIN=GND
60
100
Ic
Total Power Supply Currentl ll ]
Vcc=Max., fl=lO MHz,
50% Duty Cycle, Outputs
QQ.en, One Bit Toggling,
OE=DIR=GND
VIN=Vcc or
VIN = GND
0.6
1.5
rnA
VIN=3.4Vor
VIN=GND
0.9
2.3
rnA
Vcc=Max., fl=2.5 MHz,
50% Duty Cycle, Outputs
~n, Sixteen Bits Thggling,
OE=DIR=GND
VIN=Vcc or
VIN=GND
2.4
4.5[12]
rnA
VIN= 3.4Vor
VIN=GND
6.4
16.5[12]
rnA
Vcc=Max.
VIN.50.2V,
VIN.~Vcc-0.2V
Noles:
9. Per TTL driven input (VIN=3.4V); all other inputs at Vcc or GND.
10. This parameter is not directly testable, but is derived for use in '!btal
Power Supply calculations.
H. Ic
= IQUIESCENT + IINPurs + IDYNAMIC
Ie
= Icc+MccDHNT+ICCD(foI2 + fINI)
Iec
= Quiescent Current with CMOS input levels
Mcc = Power Supply Current for a TIL HIGH input
(VIN=3.4V)
DH
= Duty Cycle for TTL inputs HIGH
= Number of TIL inputs at DH
= Dynamic Current caused by an input transition pair
(HLH or LHL)
_
fO
= Clock frequency for registered devices, otherwise zero
fl
= Input signal frequency
NI
= Number of inputs changing at fl
All currents are in milliamps and all frequencies are in megahertz.
12. Values for these conditions are examples of the Icc formula. These
liinits are guaranteed but not tested.
9-196
NT
ICCD
iJA/
MHz
CY74FCT16245T/2245T
CY74FCT16445T/2H245T
~YPRESS
Ordering Information CY74FCT16245
Speed
(ns)
4.1
4.5
7.0
Ordering Code
Package
Name
Package Jype
CY74FCf16245CfPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCf16245CfPVC
048
48-Lead (300-Mil) SSOP
CY74FCf16245A'{PAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCf16245ATPVC
048
48-Lead (300-Mil) SSOP
CY74FCf16245TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCf16245TPVC
048
48-Lead (300-Mil) SSOP
Operating
Range
Commercial
Commercial
Commercial
Ordering Information CY74FCT162245
Speed
(ns)
4.1
4.5
7.0
Ordering Code
Package
Name
Package Jype
CY74FCf162245CTPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162245CfPVC
048
48-Lead (300-Mil) SSOP
CY74FCf162245ATPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162245ATPVC
048
48-Lead (300-Mil) SSOP
CY74FCf162245TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162245TPVC
048
48-Lead (300-Mil) SSOP
Operating
Range
Commercial
Commercial
Commercial
Ordering Information CY74FCT16445
Speed
(ns)
4.1
4.5
7.0
Ordering Code
Package
Name
Package Jype
CY74FCT16445CfPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16445CfPVC
048
48-Lead (300-Mil) SSOP
CY74FCf16445ATPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16445ATPVC
048
48-Lead (300-Mil) SSOP
CY74FCf16445TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16445TPVC
048
48-Lead (300-Mil) SSOP
Operating
Range
Commercial
Commercial
Commercial
Ordering Information CY74FCT162H245
Speed
(ns)
4.1
4.5
7.0
Ordering Code
Package
Name
Package Jype
CY74FCT162H245CfPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162H245CfPVC
048
48-Lead (300-Mil) SSOP
CY74FCf162H245ATPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCf162H245ATPVC
048
48-Lead (300-Mil) SSOP
CY74FCf162H245TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCf162H245TPVC
048
48-Lead (300-Mil) SSOP
Document #: 38-00389
9-198
Operating
Range
Commercial
Commercial
Commercial
CY74FCT16373T
CY74FCT162373T
'VEYPRESS
Maximum Ratings[2, 3]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
.
Storage Thmperature ............ Com'l -55°C to +l25°C
Ambient Thmperature with
Power Applied ................. Com'l -55°C to + 125°C
DC Input Voltage ........................ -O.5V to + 7.0V
DC Output Voltage ...................... -O.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin) ............. -60 to +120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. LOW
Static Discharge Voltage ........................ >2001 V
(per MIL:SID-883, Method 3015)
Operating Range
Range
Commercial
AIDbient
Temperature
-40°C to +85°C
Vee
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
'JYpJ4]
Max.
Unit
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Input Hysteresis[5]
VIK
Input Clamp Diode Voltage
Vcc=Min., IIN=-18 rnA
-1.2
V
IIH
Input HIGH Current
Vcc=Max., VI=VCC
±1
IlL
Input LOW Current
Vcc=Max., VI=GND
±1
10ZH
High Impedance Output Current
(Three-State Output pins)
Vcc=Max., VOUT=2.7V
±1
JAA
!iA
JAA
10ZL
High Impedance Output Current
(Three-State Output pins)
Vcc=Max., VOUT=0.5V
±1
JAA
-200
rnA
-180
rnA
±1
JAA
Max.
Unit
2.6
V
0.8
100
-0.7
los
Short Circuit Current!6]
Vcc=Max., VOUT=GND
-80
10
Output Drive Current!6]
Vcc=Max., VouT=2.5V
-50
IOFF
Power-Off Disable
Vcc=Oy, VOUT",4.5V
-140
V
mV
Output Drive Characteristics for CY74FCTl6373T
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Min.
1YpJ4]
VCc=Min., IOH=-3 rnA
2.5
3.5
V
Vcc=Min., IOH=-15 rnA
2.4
3.5
V
Vcc=Min., IOH=-32 rnA
2.0
3.0
Test Conditions
Vcc= Min., IOL =64 rnA
V
0.2
0.55
V
Output Drive Characteristics for CY74FCT162373T
Parameter
Description
Test Conditions
Min.
1Yp,!4]
Max.
Unit
IODL
Output LOW Current[6]
VcC=5Y, VIN=VIH or VIL, VOUT=1.5V
60
115
150
rnA
IODH
Output HIGH Current!6]
Vcc=5Y, VIN=VIH or VIL, VOUT=1.5V
-60
-115
-150
rnA
VOH
Output HIGH Voltage
Vcc=Min.,IoH=-24rnA
2.4
3.3
VOL
Output LOW Voltage
Vcc=Min., IOL=24 rnA
Notes:
2. Operation beyond the limits set forth may impair the useful life of the
device. Unless otherwise noted, these limits are over the operating
free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
4. 1YJlical values are at Vcc=S.Ov, TA=+25'C ambient.
5. This parameter is guaranteed but not tested.
6.
9-200
0.3
V
0.55
V
Not more than one output should be shorted at a time. Duration of
short should n~t exceed on~ second. The use of high-speed test
apparatus and/or sainple and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
CY74FCT16373T
CY74FCT162373T
~YPRESS
Switching Characteristics Over the Operating Range
Parameter
Description
CY74FCTl6373T
CY74FCT162373T
CY74FCTl6373AT CY74FCTHi373CT
CY74FCT162373AT CY74FCT162373CT
MinJll)
Max.
MinJIl)
Max.
MinJIl)
Max.
Unit
Fi~
No.2)
tpLH
tpHL
Propagation Delay
DtoO
1.5
8.0
1.5
5.2
1.5
4.2
ns
1,3
tpLH
tpHL
Propagation Delay
LEtoO
2.0
13.0
2.0
6.7
2.0
5.5
ns
1,5
tPZH
tpZL
Output Enable Time
1.5
12.0
1.5
6.1
1.5
5.5
ns
1,7,8
tpHZ
tpLZ
Output Disable Time
1.5
7.5
1.5
5.5
1.5
5.0
ns
1,7,8
tsu
Set-Up Time HIGH or LOW,
DtoLE
2.0
2.0
2.0
ns
9
tH
Hold Time HIGH or LOW,
DtoLE
1.5
1.5
1.5
ns
9
tw
LE Pulse Width HIGH
6.0
tSK(O)
Output Skew[13)
3.3
0.5
3.3
0.5
0.5
ns
5
ns
-
Ordering Information CY74FCT16373
Speed
(ns)
4.2
5.2
8.0
Ordering Code
Package
Name
Package 'Jype
CY74FCT16373CTPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16373CTPVC
048
48-Lead (300-Mil) SSOP
CY74FCT16373ATPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16373ATPVC
048
48-Lead (300-Mil) SSOP
CY74FCT16373TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16373TPVC
048
48-Lead (300-Mil) SSOP
Operating
Range
Commercial
Commercial
Commercial
Ordering Information CY74FCT162373
Speed
(ns)
4.2
5.2
8.0
Ordering Code
Package
Name
Package 'Jype
CY74FCT162373CTPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162373CTPVC
048
48-Lead (300-Mil) SSOP
CY74FCT162373ATPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162373ATPVC
048
48-Lead (300-Mil) SSOP
CY74FCT162373TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162373TPVC
048
48-Lead (300-Mil) SSOP
Operating
Range
Commercial
Commercial
Commercial
Notes:
11. Minimum limits are guaranteed but nottested on Propagation Delays.
12. See "Parameter Measurement Information" in the General
Information Section.
13. Skew between any two outputs oflbe same package switching in the
same direction. This parameter is guaranteed by desigu.
Document #: 38-00386
9-202
CY74FCT16374T
CY74FCT162374T
~YPRESS
Function Table[l)
Pin Description
Inputs
Outputs
OE
0
Function
X
eLK
L
H
Z
High-Z
X
H
H
Z
L
.r
L
L
H
.r
.r
.r
L
H
H
Z
H
Z
D
L
H
Name
D
Load
Register
Description
Data Inpnts
CLK
Clock Inputs
OE
Three-State Output Enable Inputs (Active LOW)
0
Three-State Outputs
Maximum Ratings[2,3)
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ............ Com'l -55°C to + 125°C
Ambient Temperature with
Power Applied ................. Com'l -55°C to +125°C
DC Input Voltage ........................ -0.5V to +7.0V
DC Output Voltage ...................... -O.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin) ............. -60 to + 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Operating Range
Range
Commercial
Ambient
Temperature
-40°C to +85°C
Vee
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Test Conditions
Description
Min.
'JYpJ4J
Max.
2.0
Unit
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
V
VH
Input Hysteresis[5)
VIK
Input Clamp Diode Voltage
Vee=Min., IIN=-18 rnA
-1.2
V
IIH
Input HIGH Current
Vee-Max., VI-Vee
±1
IlL
Input LOW Current
Vee-Max., VI-GND
±1
Jl.A.
Jl.A.
IOZH
High Impedance Output Current
(Three-State Output pins)
Vee=Max., VouT=2.7V
±1
Jl.A.
IOZL
High Impedance Output Current
(Three-State Output pins)
Vee=Max., VOUT=O.5V
±1
Jl.A.
0.8
100
-0.7
los
Short Circuit Current[6J
Vee=Max., VOUT=GND
-80
10
Output Drive Current[6]
Vee=Max., VouT=2.5V
-50
IOFF
Power-Off Disable
Vee=OV; VOUT54.5V
-140
V
mV
-200
rnA
-180
rnA
±1
Jl.A.
Noles:
1.
H = HIGH Voltage Level. L = LOW Voltage Level.
X = Don't Care. Z = HIGH Impedance. .
.r = LOW-to-HIGH nansition.
2. Operation beyond the limits set forth may impair the useful life of the
device. Unless otherwise noted, these limits are over the operating
free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
4. 1YPical values are at Vcc=5.0V, TA= +25°C ambient.
5. This parameter is guaranteed but not tested.
6. Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
9-204
CY74FCT16374T
CY74FCT162374T
iarcYPRESS
Switching Characteristics Over the Operating Range
Parameter
Description
CY74FCT16374T
CY74FCT162374T
CY74FCT16374AT CY74FCTl6374CT
CY74FCT162374AT CY74FCT162374CT
MinJll]
Max.
MinJll]
Max.
MinJll]
Max.
Unit
Fi
No.n-2]
tPLH
tpHL
Propagation Delay
CLKtoO
2.0
10.0
2.0
6.5
2.0
5.2
ns
1,5
tpZH
tpZL
Output Enable Time
1.5
12.5
1.5
6.5
1.5
5.5
ns
1,7,8
tPHZ
tpLZ
Output Disable Time
1.5
8.0
1.5
5.5
1.5
5.0
ns
1,7,8
tsu
Set-Up Time HIGH or LOW,.
DtoCLK
2.0
2.0
2.0
ns
4
tH
Hold Time HIGH or LOW,
DtoCLK
1.5
1.5
1.5
ns
4
tw
CLK Pulse Width
HIGH or LOW
5.0
5.0
3.3
ns
5
tSK(O)
Output Skew[13]
0.5
0.5
0.5
os
Ordering Information CY74FCTl6374
Speed
(ns)
5.2
6.5
10.0
Ordering Code
Package
Name
Package lYPe
CY74FCT16374CTPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16374CTPVC
048
48-Lead (300-Mil) SSOP
CY74FCT16374ATPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16374ATPVC
048
48-Lead (300-Mil) SSOP
CY74FCT16374TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT16374TPVC
048
48-Lead (300-Mil) SSOP
Operating
Range
Commercial
Commercial
Commercial
Ordering Information CY74FCTl62374
Speed
(ns)
5.2
6.5
10.0
Ordering Code
Package
Name
Package lYPe
CY74FCT162374CTPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162374CTPVC
048
48-Lead (300-Mil) SSOP
CY74FCT162374ATPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162374ATPVC
048
48-Lead (300-Mil) SSOP
CY74FCT162374TPAC
Z48
48-Lead (240-Mil) TSSOP
CY74FCT162374TPVC
048
48-Lead (300-Mil) SSOP
Notes:
11. Minimum limits are guaranteed but not tested on Propagation Delays.
12. See "Parameter Measurement Information" in the General
Information Section.
Operating
Range
Commercial
Commercial
Commercial
13. Skew between any two outputs of the same package switching in the
same direction. This parameter is guaranteed by design.
Document #: 38-00391
9-206
CY74FCT16500T
CY74FCT162500T
ail~
.'CYPRESS
Function Table[l,2]
Pin Summary
Name
OEAB
Description
A-to-B Output Enable Input
OEBA
Inputs
Outputs
,.
OEAB
LEAB
CL~
A
B
B-to-A Output Enable Input (Active LOW)
L
X
X
X
Z
LEAB
A-to-B Latch Enable Input
H
H
X
L
L
LEBA
B-to-A Latch Enable Input
H
H
X
H
H
CLKAB
A-to-B Clock Input (Active LOW)
H
L
"1.
L
L
CLKBA
B-to-A Clock Input (Active LOW)
H
L
"1.
H
H
A
A-to-B Data Inputs or B-to-A Three-State Outputs
H
L
H
X
BP]
B
B-to-A Data Inputs or A-to-B Three-State Outputs
H
L
L
X
B[4]
Maximum Ratings[S, 6]
(Above wpich the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ............ Com'l -Ssoc to +l25°C
Ambient Temperature with
Power Applied ................. Com'l -SsoC to + 12SoC
DC Input Voltage ........................ -O.5V to + 7.0V
DC Output Voltage ...................... -O.5V to + 7.0V
DC Output Current
(Maximum Sink Current/Pin) ............. -60 to + 120 rnA
Power Dissipation ......... , ... , . . . . . . . . . . . . . . . . . .. l.OW
Static Discharge Voltage ........................ >2001 V
(per MIL-STD-883, Method 301S)
Operating Range
Range
Commercial
Ambient
Temperature
-40°C to +8SOC
Vee
SV± 10%
Electrical Characteristics Over the Operating Range
Parameter
Test Conditions
Description
Min.
typJ7J
Max.
2.0
Unit
V
VIR
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Input Hysteresis[8]
VIK
Input Clamp Diode Voltage
Vee=Min., IIN=-18mA
-1.2
V
IIH
Input HIGH Current
Vee-Max., VI-Vee
±1
!lA
IlL
Input LOW Current
Vee-Max., VI-GND.
±1
f.tA
IOZH
High Impedance Output Current
(Three-State Output pins)
Vee=Max., VouT=2.7V
±1
!lA
IOZL
High Impedance Output Current
(Three-State Output pins)
Vee=Max., VOUT=O.SV
±1
!lA
los
Short Circuit Currentl9]
Vee=Max., VOUT=GND
-80
10
Output Drive Current[9]
Vee=Max., VOUT=2.SV
-SO
IOFF
Power-Off Disable
Vcc=Ov, VOUTs4.SV
0.8
100
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care.
Z = HIGH Impedance."1.. = HIGH-to-LOW Thansition.
2. A-to-B data flow is shown, B-to-A data flow is similar but uses OEBA,
LEBA, and CJ::KiiA.
3. Output level before the indicated steady-state input conditions were
established.
4. Output level before the indicated steady-state input conditions were
established, provided that ~ was LOW before LEAB went
LOW.
5. Operation beyond the limits set forth may impair the useful life of the
device. Unless otherwise noted, these limits are over the operating
free~air temperature range.
6.
7.
8.
9.
9-208
-0.7
-140
V
mV
-200
rnA
-180
rnA
±1
!lA
Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
'!Ypical values are at Vcc=S.Ov, TA=+25"C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus andlor sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
CY74FCT16500T
CY74FCT162500T
.rcYPRESS
Switching Characteristics Over the Operating Range
CY74FCT16500AT/ CY74FCT1650OCT/
CY74FCT162500AT CY74FCT162500CT
Parameter
MinJ14]
Description
Max.
MinJ14]
Max.
Unit
Fi~
No.5]
fMAX
C'LKA'B or CLKBA frequency
150
MHz
tpllI
tpHL
Propagation Delay
AtoBorBtoA
1.5
5.1
1.5
4.6
ns
1,3
tpLH
tpHL
Propagation Delay
LEBA to A, LEAB to B
1.5
5.6
1.5
5.3
ns
1,5
tpllI
tpHL
tI?fifation D~
AtoA,
toB
1.5
5.6
1.5
5.3
ns
1,5
tPZH
tPZL
Output Enable Time
OEBA to A, OEAB to B
1.5
6.0
1.5
5.4
ns
1,7,8
tpHz
tpLZ
Output Disable Time
OEBA to A, OEAB to B
1.5
5.6
1.5
5.2
ns
1,7,8
tsu
Set-uC]
Ato L
3.0
3.0
ns
9
tH
Hold Time, HIGH or LOW
A to CLKAB, B to cr::KBA
0
0
ns
9
tsu
Set-Up Time, HIGH or LOW
A to LEAB, B to LEBA
3.0
3.0
ns
4
1.5
1.5
ns
4
Hold Time, HIGH or LOW
AtoLEAB,BroLEBA
1.5
1.5
ns
4
tw
LEAB or LEBA Pulse Width HIGH
3.0
2.5
ns
5
tw
C'LKA'B or a::KBA Pulse Width HIGH or LOW
3.0
3.0
ns
5
tSK(O)
Output Skew[16]
tH
150
m
HIGH or LOW
,BtoCLKBA
IClock HIGH
IClock LOW
0.5
0.5
ns
Ordering Information CY74FCT16500T
Speed
(ns)
4.6
5.1
Ordering Code
Package
Name
Package 'JYpe
CY74FCT16500CTPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCT16500CTPVC
056
56-Lead (300-Mil) SSOP
CY74FCT16500ATPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCT16500ATPVC
056
56-Lead (300-Mil) SSOP
Operating
Range
Commercial
Commercial
Ordering Information CY74FCT162500T
Speed
(ns)
4.6
5.1
Ordering Code
Package
Name
Package 1Ype
CY74FCT162500CTPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162500CTPVC
056
56-Lead (300-Mil) SSOP
CY74FCT162500ATPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162500ATPVC
056
56-Lead (300-Mil) SSOP
Notes:
14. Minimum limits are guaranteed but not tested on Propagation Delays.
15. See "Parameter Measurement Information" in the General
Information Section.
Document #: 38-00381
Operating
Range
Commercial
Commercial
16. Skew between any two outputs of the same package switching in the
9-210
same direction. This parameter is guaranteed by design.
CY74FCT16S01 T
CY74FCT162S01T
CY74FCT162HSOlT
Q-YPRESS
Function Table[2,3]
Pin Description
Name
Inputs
Description
Outputs
OEAB
LEAB
CLKAB
A
B
B-to-A Output Enable Input (Active LOW)
L
X
X
X
Z
LEAB
A-to-B Latch Enable Input
H
H
X
L
L
LEBA
B-to-A Latch Enable Input
H
H
X
H
H
OEAB
A-to-B Output Enable Input
l:'ffil3A
CLKAB A-to-B Clock Input
H
L
.r
L
L
CLKBA B-to-A Clock Input
H
L
.r
H
H
A
A-to-B Data Inputs or B-to-A Three-State
Outputs[l]
H
L
L
X
B[4]
H
L
H
X
B[5]
B
B-to-A Data Inputs or A-to-B Three-State
Outputs[l]
Maximum Ratings[6, 7]
Storage Thmperature ................... -55°C to + 125°C
Ambient Temperature with
Power Applied ........................ -55°C to +125°C
DC Input Voltage ........................ -O.5V to +7.0V
DC Output Voltage ...................... -O.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin) ............. -60 to + 120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Notes:
1. On the 74FCI'162H501 T these pins have bus hold.
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,
LEBA, and CLKBA.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
.r = LOW-to-HIGH nansition
4. Output level before the indicated steady-state input conditions were
established.
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Operating Range
Range
Commercial
5.
6.
Ambient
Temperatore
-40°C to +85°C
Vee
5V± 10%
Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went
LOW.
Operation beyond the limits set forth may impair the useful life of the
device. Unless otherwise noted, these limits are over the operating
free-air temperature range.
7.
9-212
Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
16f./&PRESS
Power Supply Characteristics
Sym.
Min.
'JYpJ8]
Max.
Unit
-
S
SOO
iJA
-
O.S
1.S
rnA
VIN=Vcc or
VIN=GND
-
7S
120
to =lOMHz (CLKAB)
VIN=Vccor
VIN=GND
-
0.8
1.7
OEAB= EBA=Vcc
LEAB = GND, One Bit 1bggling
VIN=3.4Vor
VIN=GND
-
1.3
3.2
to =
VIN=Vccor
VIN=GND
-
3.8
6.5 [16]
OEAB=OEBA=Vcc
LEAB=GND
Eighteen Bits 1bggling
fl =2.5MHz, 50% Duty Cycle
VIN=3.4Vor
VIN = GND
-
8.5
20.8[16]
Test Conditions[12]
Parameter
VIN.~0.2V
VIN.~Vcc-O.2V
Icc
Quiescent Power Supply
Current
Vcc=Max.
AICC
Quiescent Power Supply
Current TIL inputs HIGH
V cc= Max., VIN = 3.4V[13]
ICCD
Dynamic Power Supply
Currentl l4]
Vcc=Max., Outputs Open
OEAB=OEBA=VccorGND
One Input 1bggling, SO% Duty
Cycle
Ic
1btal Power Supply
Current[15]
Vcc=Max., Outputs Open
SO%Du~
fl = SMHz, SO% Duty Cycle
Vcc=Max., Outputs Open
lOMHz (CLKAB)
SO%Du~
Notes:
12. For conditions shown as Max. or Min., use appropriate value specified
under Electrical Characteristics for the applicable device type.
13. Per TIL driven input (VJN=3.4V); all other inputs at V CC or GND.
14. This parameter is not directly testable, but is derived for use in Thtal
Power Supply.
15. Ic
IC
Icc
Mcc
= IQUIESCENT + IINPUTS + IDYNAMIC
= Icc+MccDHNT+lcCD(fol2 + fINI)
= Quiescent Current with CMOS input levels
= Power Supply Current for a TTL HIGH input
(VJN=3.4V)
rnA
= Duty Cycle for TTL inputs HIGH
= Number of TTL inputs at DH
= Dynamic Current caused by an input transition pair
(HLHor LHL)
fo
= Oock frequency for registered devices, otherwise zero
fl
= Input signal frequency
NI
= Number of inputs changing at fl
All currents are in milliamps and all frequencies are in megahertz.
16. Values for these conditions are examples of the Icc formula. These
limits are guaranteed but not tested.
9-214
DH
NT
ICCD
tAN
MHz
CY74FCT16S01T
CY74FCT162S01T
CY74FCT162HSOIT
~YPRESS
Ordering Information CY74FCT16501T
Speed
Package
Name
(ns)
Ordering Code
4.6
CY74FCT16501CfPAC
ZS6
56-Lead (240-Mil) TSSOP
CY74FCT16501CTPVC
056
56-Lead (300-Mil) SSOP
CY74FCT16501ATPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCT16501ATPVC
056
56-Lead (300-Mil) SSOP
5.1
Package 1YPe
Operating
Range
Commercial
Commercial
Ordering Information CY74FCT162501T
Speed
(ns)
Ordering Code
Package
Name
Package 1YPe
4.6
C1r74FCT162501CfPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162501CfPVC
056
56-Lead (300-Mil) SSOP
5.1
CY74FCT162501ATPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162501ATPVC
056
56-Lead (300-Mil) SSOP
Operating
Range
CommerCial
Commercial
Ordering Information CY74FCT162H501T
Speed
(ns)
4.6
5.1
Ordering Code
Package
Name
Package 'tYpe
CY74FCT162H501CfPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162H501CfPVC
056
56-Lead (300-Mil) SSOP
CY74FCT162H501ATPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162H501ATPVC
056
56-Lead (300-Mil) SSOP
Document #: 38-00382
9-216
Operating
Range
Commercial
Commercial
CY74FCT16543T
CY74FCT162543T
~YPRESS
Function Table[!]
Pin Description
Name
OEAB
Description
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
~
A-to-B Enable Input (Active LOW)
CEBA
B-to-A Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input (Active WW)
LEBA
B-to-A Latch Enable Input (Active LOW)
A
A-to-B Data Inputs or B-to-A Three-State
Outputs
B
B-to-A Data Inputs or A-to-B Three-State
Outputs
Latch
Status
Inputs
Output
Buffers
CEAB
'LEAD
OEAB
AtoB
B
H
X
X
Storing
HighZ
X
H
X
Storing
X
X
X
H
X
HighZ
L
L
L
Thansparent
Current A
Inputs
L
H
L
Storing
Previous A
Inputs[2]
Maximum Ratings[3,4]
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ............ Com'l -55°C to +125°C
DC Output Voltage ...................... -O.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin) ............. -60 to +120 rnA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Notes:
1. A-to-B data flow sho
~o-A flow control is the same, except using
CEliA, LEBA, and
B
2. Data prior to I1lAli LOW-to-HIGH 1tansition.
H = HIGH Voltage Level. L = LOW Voltage Level.
X = Don't Care. Z = High Impedance.
OE;
Ambient Thmperature with
Power Applied ................. Com'l -55°C to + 125°C
DC Input Voltage ........................ -O.5V to + 7.0V
Static Discharge Voltage. . . . . . . . . . . . . . . . . . . . . . .. >2001V
(per MIL-STD-883, Method 3015)
3. Operation beyond the limits set forth may i.npair the useful life of the
device. Unless otherwise noted, these limits are over the operating
free-air temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
9-218
CY74FCT16543T
CY74FCT162543T
QPRESS
Power Supply Characteristics
Parameter
'lYpJ8J
Max.
Unit
5
500
!LA
VIN=3.4V[9J
0.5
1.5
mA
Vee=Max., One Input
Thggling, 50% Q!!!Y Cycle,
Outputs Open, OE=GND
VIN=Vee or
VIN=GND
60
100
Vee-Max., fl-10 MHz,
50% Duty Cycle, Outputs
Q2.en, One Bit Thggling,
OE=GND
VIN=Vee or
VIN = GND
0.6
1.5
mA
VIN=3.4Vor
VIN = GND
0.9
2.3
mA
Vee=Max., fl =2.5 MHz,
50% Duty Cycle, Outputs
~en, Sixteen Bits Thggling,
E=GND
VIN=Vee or
VIN=GND
2.4
4.5[12J
mA
VIN=3.4Vor
VIN=GND
6.4
16.5[12J
rnA
Description
Thst Conditions
Icc
Quiescent Power Supply Current
Vee=Max.
VINsO.2V,
VIN"'Vee-0.2V
Alec
Quiescent Power Supply Current
(TIL inputs HIGH)
Vee=Max.
IeCD
Dynamic Power Supply
Current[IOJ
Ie
Thtal Power Supply Current[IlJ
Notes:
9. Per TIL driven input (VIN=3.4V); all other inputs at Vccor GND.
10. This parameter is not directly testable, but is derived for use in Thtal
Power Supply calculations.
11. Ic
= IQUIESCENT + IINPUTS + IDYNAMIC
Ic
= Icc+McCDHNT+ICCD(f0/2 + fINI)
Icc
= Quiescent Cutrent with CMOS input levels
Mcc = Power Supply Current for a TIL HIGH input
(VIN=3.4V)
DH
= Duty Cycle for TIL inputs HIGH
JlA/
MHz
NT
= Number of TIL inputs at DH
ICCD = Dynamic Current caused by an input transition pair
(HLHor LHL)
to
= Clock frequeney for registered devices, otherwise zero
fl
= Input signal frequeney
NI
= Number of inputs changing at fl
All currents are in milliamps and all frequencies are in megahertz.
12. Values for these conditions are examples of the Icc formula. These
limits are gnaranteed but not tested.
9-220
CY74FCT16543T
CY74FCT162543T
-~
.'CYPRESS
Ordering Information CY74FCT16543
Speed
(ns)
5.1
6.5
8.5
Ordering Code
Package
Name
Package 1Ype
CY74FCf16543CfPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCf16543CfPVC
056
56-Lead (300-Mil) SSOP
CY74FCf16543ATPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCT16543ATPVC
056
56-Lead (300-Mil) SSOP
CY74FCT16543TPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCf16543TPVC
056
56-Lead (300-Mil) SSOP
Operating
Range
Commercial
Commercial
Commercial
Ordering Information CY74FCT162543
Speed
(ns)
5.1
6.5
8.5
Ordering Code
Package
Name
Package 1Ype
CY74FCf162543CTPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCf162543CTPVC
056
56-Lead (300-Mil) SSOP
CY74FCf162543ATPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCf162543ATPVC
056
56-Lead (300-Mil) SSOP
CY74FCT162543TPAC
Z56
56-Lead (240-Mil) TSSOP
CY74FCT162543TPVC
056
56-Lead (300-Mil) SSOP
Document #: 38-00388
9-222
Operating
Range
Commercial
Commercial
Commercial
CY74FCT16646T
CY74FCT162646T
~YPRESS
Pin Description
Description
Pin Names
A
Data Register A Inputs
Data Register B Outputs
B
Data Register B Inputs
Data Register A Outputs
CLKAB, CLKBA
Clock Pulse Inputs
SAB,SBA
Output Data Source Select Inputs
DIR
Direction
OE
Output Enable (Active LOW)
Function Thble[l]
Data 110[2]
Inputs
Function
DE
DIR
CLKAB
CLKBA
SAB
SBA
A
B
H
H
X
X
HorL
I
HorL
I.
X
X
Input
Input
X
X
Isolation
Store A and B Data
L
L
L
L
X
X
X
HorL
X
X
L
H
Output
Input
Real Time B Data to A Bus
Stored B Data to A Bus
L
L
H
H
X
HorL
X
X
L
H
X
X
Input
Output
Notes:
1. H = High Voltage Level
2.
L = LOW Voltage Level
X = Don't Care
I = LOW-to-HIGH 'fransition
9-224
Real Time A Data to Bus
Stored A Data to B Bus
The data o'!!!put functions may be enabled or disabled by various signals at the OE or DIR inputs. Data input functions are always enabled,
i.e., data at the bus pinswill be stored on every LOW-to-HIGH transition on the clock inputs.
CY74FCT16646T
CY74FCT162646T
_rcYPRESS
Electrical Characteristics Over the Operating Range
Parameter
Description
Vrn
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Input Hysteresis[6]
Test Conditions
Min.
'JYpJS]
Max.
Unit
2.0
V
0.8
100
V
mV
VIK
Input Clamp Diode Voltage
Vee=Min., IIN=-18 rnA
-1.2
V
Irn
Input HIGH Current
Vee=Max., VI=Vee
-0.7
±1
IlL
Input LOW Current
Vee=Max., VI=GND
±1
10ZH
High Impedance Output
Current (Three-State Output
pins)
Vee=Max., VOUT=2.7V
±1
JlA
JlA
JlA
10ZL
High Impedance Output
Current (Three-State Output
pins)
Vee=Max., VOUT=O.5V
±1
JlA
los
Short Circuit Currend7]
Vee=Max., VOUT=GND
-80
-200
rnA
10
Output Drive Current[7]
Vee = Max., VOUT=2.5V
-50
-180
rnA
10FF
Power-Off Disable
Vee=Ov, VOUTs4.5V
±1
JlA
Max.
Unit
-140
Output Drive Characteristics for CY74FCT16646T
Parameter
Output LOW Voltage
VOL
'JYpJ5]
Vee=Min., IOH=-3 rnA
2.5
3.5
Vee=Min., IOH=-15 rnA
2.4
3.5
V
Vee=Min., 10H= -32 rnA
2.0
3.0
V
Test Conditions
Output HIGH Voltage
VOH
Min.
Description
Vee=Min., 10L=64 rnA
V
0.2
0.55
V
Output Drive Characteristics for CY74FCT162646T
Test Conditions
Min.
'JYpJ5]
Max.
Unit
10DL
Output LOW Current[7]
Vee=5V, VIN=Vrn or VIL, VOUT=1.5V
60
115
150
rnA
IODH
Output HIGH Current[7]
Vee=5V, VIN=Vrn or VIL, VOUT=d.5V
-60
-115
-150
rnA
VOH
Output HIGH Voltage
Vee=Min., 10H=-24 rnA
2.4
3.3
VOL
Output LOW Voltage
Vee=Min., 10L=24 rnA
0.55
V
Parameter
Description
V
0.3
Capacitance (TA = +25'C, f = 1.0 MHz)
Symbol
Description[8]
'JYp.
Max.
Unit
CIN
Input Capacitance
VIN= OV
4.5
6.0
pF
CoUT
Output Capacitance
VOUT=OV
5.5
8.0
pF
Conditions
Notes:
5. Typical values are atVcc=5.0V. TA=+25'C ambient.
6. This parameter is guaranteed but not tested.
7. Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus and/or sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametrics tests. In any sequence of
parameter tests, los tests should be performed last.
B. This parameter is measured at characterization but not tested.
9-226
CY74FCT16646T
CY74FCT162646T
~CYPRESS
Switching Characteristics Over the Operating Range
74FCT16646T
74FCT162646T
Parameter
Description
74FCT16646AT
74FCT162646AT
74FCT16646CT
74FCT162646CT
Fi
Condo
MinJ15]
Max.
MinJ15]
Max.
Min.[15]
Max.
Unit
No.!i."4]
CL=50pF
RL=500n
1.5
9.0
1.5
6.3
1.5
5.4
ns
1,2
tpLH
tpHL
Propagation Delay
Bus to Bus
tpZH
tpzL
Output Enable Time
DIR or OE to Bus
1.5
14.0
1.5
9.8
1.5
7.8
ns
1,7,8
tpHZ
tpLZ
Output Disable Time
DIR or OE to Bus
1.5
9.0
1.5
6.3
1.5
6.3
ns
1,7,8
tpLH
tpHL
Propagation Delay
Clock to Bus
1.5
9.0
1.5
6.3
1.5
5.7
ns
1,5
tPLH
tpHL
Propagation Delay
SBA or SAB to Bus
1.5
11.0
1.5
7.7
1.5
6.2
ns
1,5
tsu
Set-Up Time HIGH or
LOW Bus to Clock
2.0
-
2.0
-
2.0
-
ns
4
tH
Hold Time HIGH or
LOW Bus to Clock
1.5
-
1.5
-
1.5
-
ns
4
tw
Clock Pulse Width
HIGH or LOW
5.0
-
5.0
-
5.0
-
ns
6
tSK(O)
Output Skew[16]
-
0.5
-
0.5
-
0.5
ns
-
Ordering Information CY74FCT16646
Speed
(ns)
5.4
6.3
9.0
Ordering Code
Package
Name
Package 'Jype
CY74FCT16646CTPAC
Z56
48-Lead (240-MiI) TSSOP
CY74FCT16646CTPVC
056
48-Lead (300-MiI) SSOP
CY74FCT16646ATPAC
Z56
48-Lead (240-MiI) TSSOP
CY74FCT16646ATPVC
056
48-Lead (300-MiI) SSOP
CY74FCT16646TPAC
Z56
48-Lead (240-MiI) TSSOP
CY74FCT16646TPVC
056
48-Lead (300-MiI) SSOP
Operating
Range
Commercial
Commercial
Commercial
Ordering Information CY74FCT162646
Speed
(ns)
5.4
6.3
9.0
Ordering Code
Package
Name
Package 1Ype
CY74FCT162646CTPAC
Z56
48-Lead (240-MiI) TSSOP
CY74FCT162646CTPVC
056
48-Lead (300-MiI) SSOP
CY74FCT162646ATPAC
Z56
48-Lead (240-MiI) TSSOP
CY74FCT162646ATPVC
056
48-Lead (300-MiI) SSOP
CY74FCT162646TPAC
Z56
48-Lead (240-MiI) TSSOP
CY74FCT162646TPVC
056
48-Lead (300-MiI) SSOP
Notes:
14. See "Parameter Measurement Information" in the General Information Section.
15. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating
Range
Commercial
Commercial
Commercial
16. Skew any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
Document #: 38-00383
9-228
CY74FCT16652T.
CY74FCT162652T
1;!I2YPRESS
Pin Description
Name
Description
A
Data Register A Inputs
Data Register B Outputs
B
Data Register B Inputs
Data Register A Outputs
CLKAB, CLKBA
Cock Pulse Inputs
SAB,SBA
Output Data Source Select Inputs
OEAB,OEBA
Output Enable Inputs
Function Table[l]
Data 1/0[2]
Inputs
OEAB
OEBA
CLKAB
CLKBA
SAD
SBA
A
B
L
L
H
H
HorL
HorL
X
X
X
X
Input
Input
X
H
H
H
I
X
X[3]
X
X
Input
Input
Unspecified[2]
Output
Store A, Hold B
Store A in Both
Registers
L
L
X
L
HorL
I
I
X
X
X
X[3]
Unspecified[2]
I
Input
Input
Hold A, Store B
Store B in both
Registers
L
L
X
X
X
L
Output
Input
Real Time B Data to A
Bus
Stored B Data to A Bus
Input
Output
Real Time A Data to B
Bus
Stored A Data to B Bus
Output
Output
Stored A Data to B Bus
and
Stored B Data to A Bus
I
I
I
I
HorL
L
L
X
HorL
X
H
H
H
X
X
L
X
H
H
HorL
X
H
X
H
L
HorL
HorL
H
H
Notes:
1. H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Don't Care
I ~LOW-to-HIGH nansition
2. The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always
3.
9-230
Operation or Function
Isolation
Store A and B Data
enabled, i.e., data at the bus pins will be stored on every WW-toHIGH transition on the clock inputs.
Select control ~ L; clocks can occur simultaneously.
Select control ~ H; clocks must be staggered to load both registers.
•
CY74FCT16652T
CY74FCT162652T
?cYPRESS
DC Electrical Characteristics Over the Operating Range
Parameter
lest Conditions[5]
Description
Vrn
Input HIGH Voltage
Guaranteed Logic HIGH Level
VIL
Input LOW Voltage
Guaranteed Logic LOW Level
VH
Input Hysteresis
VII{
Input Clamp Diode Voltage
Vcc= Min., IIN= -18 rnA
Irn
Input HIGH Current[7]
IlL
Input LOW Current[7]
IOZH
Min.
1YPJ6]
Max.
Unit
0.8
V
2.0
V
mV
100
-0.7
-1.2
V
Vcc=Max., VI=VCC
±1
VcC=Max., VI=GND
±1
High Impedance Output(7]
Current (Three-State Output
pins)
Vcc=Max., VOUT=2.7V
±1
!tA
!tA
!tA
10ZL
High Impedance Outputf7]
Current (Three-State Output
pins)
Vcc=Max., VOUT=0.5V
±1
!tA
los
Short Circuit Current
Vcc=Max., VOUT=GND[8]
-80
10
Output Drive Current
VcC=Max., VOUT=2.5V[8]
-50
10FF
Power-Off Disabld7]
Vcc=OY, VOUT",4.5V
-140
-200
rnA
-180
rnA
±1
!tA
Max.
Unit
Output Drive Characteristics for CY74FCT16652T
Parameter
VOH
VOL
Min.
1YPJ6]
Vcc=Min., IOH=-3 rnA
2.5
3.5
Vcc=Min., IOH=-15 rnA
2.4
3.5
V
Vcc=Min., IOH=-32 mA19]
2.0
3.0
V
lest Conditions[5]
Description
Output HIGH Voltage
Output LOW Voltage
Vcc=Min., IOL=64 rnA
V
0.2
0.55
V
1YPJ6]
Max.
Unit
Output Drive Characteristics for CY74FCT162652T
Parameter
lest Conditions[5]
Description
Min.
IODL
Output LOW Current
Vcc=5Y, VIN=VIHorVIL, VOUT=1.5V[8]
60
115
150
rnA
IODH
Output HIGH Current
Vcc=5Y, VIN=VIHor VIL, VOUT=1.5V[8]
-60
-115
-150
rnA
VOH
Output HIGH Voltage
Vcc=Min.,IoH=-24rnA
2.4
3.3
VOL
Output LOW Voltage
Vcc=Min., IOL=24 rnA
V
0.3
0.55
V
Capacitance (TA = +25 C, f = 1.0 MHz)
0
Description[JO]
'iYP·
Max.
Unit
CIN
Input Capacitance
VIN =OV
4.5
6.0
pF
GoUT
Output Capacitance
VOUT = OV
5.5
8.0
pF
Parameter
lest Conditions
Notes:
5. For conditions shown as Max. or Min., use appropriate value specified
under Electrical Characteristics for the applicable device type.
6. TYPical values are at Vcc=5.0V, +25°C ambient.
7. The test limit for this parameter is +5mA at TA=-55°C.
8. Not more than one output should be tested at one time. Duration of
the test should not exceed one second.
9. Duration of the condition cannot exceed one second.
10. This parameter is measured at characterization but not tested.
9-232
~YPRESS
CY74FCT16652T
CY74FCT162652T
Switching Characteristics Over the Operating Range
74FCT16652T
74FCT162652T
Parameter
Description
74FCT16652AT
74FCT162652AT
74FCT16652CT
74FCT162652CT
CondJ17]
MinJ19]
Max.
MinJ19]
Max.
MinJ19]
Max.
Unit
Fifi
No.8]
CL=50 pF
RL=500Q
1.5
9.0
1.5
6.3
1.5
5.4
ns
1,3
tpLH
tpHL
Propagation Delay
Busto Bus
tpZH
tpHL
Output Enable Time
OEAB or OEBA to
Bus
1.5
14.0
1.5
9.8
1.5
7.8
DS
1,7,8
tpHZ
tpLZ
Output Disable Time
OEAB or OEBA to
Bus
1.5
9.0
1.5
6.3
1.5
6.3
DS
1,7,8
tpLH
tpHL
Propagation Delay
Clock to Bus
1.5
9.0
1.5
6.3
1.5
5.7
DS
1,5
tpLH
tpHL
PropagatioD Delay
SBA or SAB to Bus
1.5
11.0
1.5
7.7
1.5
6.2
DS
1,5
tsu
Set-Uptime
HIGH or LOW
Bus to Clock
2.0
-
2.0
-
2.0
-
DS
4
tH
Hold Time
HIGH or LOW
Bus to Clock
1.5
-
1.5
-
1.5
-
DS
4
tw
Clock Pulse Width
HIGH or LOW
5.0
-
5.0
-
5.0
-
DS
5
tSK(O)
Output Skew[20]
-
0.5
-
0.5
-
0.5
DS
Notes:
17. See test circuits and waveforms.
18. See "Parameter Measurement Information" in the General Information Section.
19. Minimum limits are guaranteed, but not tested, on propagation
delays.
20. Skew between any two outputs of the same package switching in the
same direction. This parameter guaranteed by design.
9-234
CY74FCT16823T
CY74FCT162823T
18-Bit Registers
FeatUres
• Low power, pin compatible
replacement for ABT functions
• FCT-C speed at 6.0 ns
• Power-off disable outputs permits live
insertion
• Edge-rate control circuitry for
significantly improved noise
characteristics
• 'l)pical output skew < 2S0 ps
• ESD > 2000 V
• TSSOP (19.6-mil pitch) and SSOP
(2S-mil pitch) packages
• Extended commercial range of
-40'C to +8S'C
• Vee = 5V :!: 10%
CY74FCTl6823T Features:
• 64 mA sink current (Com'I),
32 mA source current (Com'l)
• 'l)pical VOLP (ground bounce)
<1.0V at Vee sv, TA 2S'C
=
=
CY74FCT162823T Features:
• Balanced output drivers: 24 mA
• Reduced system switching noise
• 'l)pical VOLP (ground bounce)
<0.6V at Vee = sv, TA= 2S'C
Functional Description
The CY74FCT16823T
and
the
CY74FCTI62823T 18-bit bus interface
register are designed for use in highspeed, low-power systems needing wide
Logic Block Diagrams
registers and parity. 18-bit operation is
achieved by connecting the control lines
of the two 9-bit registers. Flow-through
pinout and small shrink packaging aids in
simplifying board layout. The outputs are
designed with a. power-off disable feature
to allow live insertion of boards.
The CY74FCT16823T is ideally suited for
driving high-capacitance loads and lowimpedance backplanes.
The CY74FCT162823T has 24-mA balanced output drivers with current limiting
resistors in the outputs. This reduces the
need for external terminating resistors
and provides for minimal undershoot
and redced ground bounce. The
CY74FCT162823T is ideal for driving
transmission lines.
Pin Configuration
ssoprrssop
,~----------------------~
,=---~
'lbpView
>------,
,=
,ClK
1
,CI:REI'I
,~
,CLK - - - - - - - - - - - - - - - - ,
,a,
GND
,CI:REI'I
,0,
GND
,0,
4
,03
>--1--- ,a,
,0,
Vee
,0,
,as
,a.
,Os
,a,
,D.
GND
,0,
,a.
,Do
GND
'------'yr-----~/
FCT16823·1
TO 8 OTHER CHANNELS
~------------------~
,=
,a,
-----~
>---------...,
,CLK - - - - - - - - - - - - - - - - ,
,Oa
,De
,0,
,0,
,03
GND
,0,
,0,
,0,
,0,
GND
,0,
,as
,Os
,00
Vee
,06
Vee
,0,
,Do
GND
,a,
,00
GND
,0.
,De
,llE
>--t--- ,a,
,0,
----f----- 2000 V
• TSSOP (19.6-mil pitch) and SSOP
(2S-mil pitch) packages
• Extended commercial range of
-40"C to +8S"C
• Vee = 5V ± 10%
CY74FCT16827T Features:
• 64 rnA sink current (Com'I),
32 rnA source current (Com'l)
• 'JYpical VOLP (ground bounce)
<1.0V at Vee = sv, TA = 2S"C
CY74FCT162827T Features:
• Balanced output drivers: 24 rnA
• Reduced system switching noise
• 'Jypical VOLP (ground bounce)
<0.6V at Vee = sv, TA= 2S"C
Functional Description
The CY74FCf16827T 20-bit buffer/line
driver and the CY74FCf162827T 20-bit
buffer/line driver provide high-performance bus interface buffering for wide
data/address paths or buses carrying par-
Logic Block Diagrams
ity. These parts can be used as a single
20-bit buffer or two lO-bit buffers. Each
lO-bit buffer has a pair of NANDed OE
for increased flexibility. The outputs are
designed with a power-off disable feature
to allow for live insertion of boards.
The CY74FCT16827T is ideally suited for
driving high-capacitance loads and lowimpedance backplanes.
The CY74FCf162827T has 24-mA balanced output drivers with current-limiting
resistors in the outputs. This reduces the
need for external terminating resistors
and provides for minimal undershoot
and reduced ground bounce.
The
CY74FCT162827T is ideal for driving
transmission lines.
Pin Configuration
ssoprrssop
Top View
,OE,
,OE,----d'~
,OE,,-----oL...J
>--t---,Y,
~------~-v------~/
TO 9 OTHER CHANNELS
FCT16827-1
,OE,
,Y,
,Y,
GND
,Y,
,Y,
vee
,Yo
,Y.
,Y,
GND
,Y.
,Y.
,A,
,As
GND
,As
,Ao
Vee
,As
,As
,A,
GND
,As
,As
1A10
1Y 10
,Y,
,v,
,OE,---- 2001 V
(per MIL-STD-883, Method 3015)
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
'lYpJ5]
Max.
2.0
Unit
VIH
Input HIGH Voltage
Guaranteed Logic HIGH Level
V'L
Input LOW Voltage
Guaranteed Logic LOW Level
V
VH
Input Hysteresis[6]
V'K
Input Clamp Diode Voltage
Vee=Min., IIN=-18 rnA
-1.2
V
IIH
Input HIGH Current
Vee=Max., V,=Vee
:1:1
IlL
Input LOW Current
Vee=Max., VI=GND
:1:1
10ZH
High Impedance Output
Current (Three-State Output
pins)
Vee=Max., VOUT=2.7V
:1:1
J.IA
J.IA
J.IA
10ZL
High Impedance Output
Current (Three-State Output
pins)
Vee=Max., VOUT=0.5V
:1:1
J.IA
los
Short Circuit Current[7]
Vee=Max., VouT=GND
-80
10
Output Drive Current[7]
Vee = Max., VOUT=2.5V
-50
10FF
Power-Off Disable
Vcc=Ov, VOUTs4.5V
0.8
100
Notes:
1. H = HIGH Voltage Level.
L = LOW Voltage Level.
X = Don't Care.
Z = HIGH Impedance.
2. Output level before I.E HIGH-to-LOW Transition.
3. Operation beyond the limits set forth may impair the useful life of the
device. Unless otherwise noted, these limits are over the operating
.
free-air temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either Vee or ground.
5.
6.
7.
9-248
-0.7
-140
V
mV
-200
rnA
-180
rnA
:1:1
J.IA
'iypical values are at Vcc=5.0V, TA=+25'C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus andlor sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
CY74FCT16841T
CY74FCT162841T
&~PRESS
Switching Characteristics Over the Operating Range
Parameter
tpLH
tpHL
tpLH
tPHL
tpHZ
tPZL
tpHZ
tPLZ
Description
Propagation Delay
DtoQ
(LE=HIGH)
Propagation Delay
LEtoQ
Output Enable Time
OEtoQ
Output Disable Time
OEtoQ
tsu
Set-UpTime
HIGH or LOW,
DtoLE
tH
Hold Time
HIGH or LOW,
DtoLE
tw
LE Pulse Width HIGH
tSK(O)
Output Skew[17]
74FCTl684IAT
74FCT16284IAT
74FCT16841BT
74FCT162841BT
74FCf16841CT
74FCT162841CT
Condition[12)
MinJ13)
Max.
MinJ13)
Max.
MinJ13]
Max.
CL=50pF
RL=5000
1.5
9.0
1.5
6.5
1.5
5.5
CL =300 pp[15]
RL=5000
1.5
13.0
1.5
13.0
1.5
13.0
CL-50pF
RL=5000
1.5
12.0
1.5
8.0
1.5
6.4
CL=300pp[15]
RL=5000
1.5
16.0
1.5
15.5
1.5
15.0
CL=50pP
RL=5000
1.5
11.S
1.5
8.0
1.S
6.5
CL =300 pp[15]
RL=5000
I.S
23.0
1.5
14.0
1.5
12.0
CL=Spp[15)
RL=SOOO
I.S
7.0
l.S
6.0
1.5
5.7
CL=50 pP
RL=5000
l.S
8.0
1.5
7.0
l.S
6.0
CL-SO pP
RL=SOOO
2.5
-
2.5
-
2.0
2.S
-
2.5
-
1.5
4.0[16]
-
4.0[16]
-
4.0[16]
-
ns
5
-
O.S
-
0.5
-
0.5
os
-
Notes:
12. See test circuit and waveform.
13. Minimum limits are guaranteed but not tested on Propagation Delays.
14. See "Parameter Measurement Infonnation" in the General
Information Section.
Unit
Fi~.
No.4]
ns
1,5
ns
1,5
ns
1,7,8
ns
1,7,8
-
ns
9
-
ns
9
15. These conditions are guaranteed but not tested.
16. These limits are guaranteed but not tested.
17. Skew between any two outputs of the same package switching in the
same direction. This parameter is guaranteed by desigu.
9-250
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
16-Bit Registered Transceivers
Features
CY74FCT162952T Features:
• Low power, pin-compatible
• Balanced output drivers: 24 rnA
• Reduced system Switching noise
• 'fYpical VOLP (ground bounce)
<:0.6V at Vee = sv, TA= 2S"C
replacement for ABT functions
• FCT-C speed at 6.3 ns
• Power-off disable outputs permits live
insertion
• Edge-rate control circuitry for
significantly improVed noise
cbaracteristics
• 'fYpical output skew < 2S0 ps
• ESD > 2000 V
• TSSOP (19.6-mil pitcb) and SSOP
(2S-mil pitch) packages
• Extended commercial range of
-40"C to +8S"C
• Vee = 5V j: 10%
CY74FCT16952T Features:
• 64 rnA sink current (Com'I),
32 rnA source current (Com'I)
• 'fYpical VOLP (ground bounce)
<1.0V at Vee = sv, TA = 2S"C
CY74FCT162H952T Features:
• Bus hold retains last active state
• Eliminates the need for external
pull-up or pull-down resistors
Functional Description
These 16-bit registered transceivers are
high-speed, low-power devices. 16-bit operation is achieved by connecting the controllines of the two 8-bit registered transceivers together. For data flow from bus
A-to-B, CEAB must be WW to allow
data to be stored when CLKAB transitions from LOW-to-HIGH. The stored
data will be present on the output when
OEAB is Law. Control of data from
B-to-A is similar and is controlled by
using the CEnA, CLKBA, and OEBA inputs. The output buffers are designed
with a power-off disable feature to allow
for live insertion of boards.
The CY74FCT16952T is ideally suited for
driving high-capacitance loads and lowimpedance backplanes.
The CY74FCT162952T has 24-mA balanced output drivers with current-limiting
resistors in the outputs. This reduces the
need for external terminating resistors
and provides for minimal undershoot
and reduced ground bounce.
The
CY74FCT162952T is ideal for driving
transmission lines.
The CY74FCT162H952T is a 24-mA balanced output part that has "bus hold" on
the data inputs. The device retains the input's last state whenever the input goes to
high impedance. This eliminates the need
for pull-up/down resistors and prevents
floating inputs.
Pin Configuration
ssoprrssop
Logic Block Diagrams
1bpView
,=
,=
1CLKAB
,=
,=
GND
,A,
,CLKABI----j
,cLKAB----j
,A2
,B2
Vee
,Ao
,B,
,iI<
,B.
,B.
B GND
2 1 1Ae
. . .--_V_---"J
"
FCT16952·1
TO 7 OTHER CHANNELS
V
'"
FCT16952·2
TO 7 OTHER CHANNELS
,~
,As
,B,
2B,
~
2B2
~
2B3
GND
~
GND
2B•
2As
2As
286
2B,
Vee
Vee
~7
2~
2As
2B,
GND
9-252
GND
,B,
,A7
~,
~
,~
GND
,B,
Vee
,As
FF=t--+-..... ,B,
,OEI!A
,CLKBA
GND
,<:EAl!
2CEllA
,cLKAB
,cLKBA
21lEA1!
20E1!A
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
.~PRESS
Electrical Characteristics Over the Operating Range
Parameter
lest Conditions
Description
VlH
Input HIGH Voltage
VIL
Input LOW Voltage
VH
Input Hysteresis[7]
VIK
Input Clamp Diode Voltage
IlH
Input HIGH Current
Standard
IlL
Input LOW Current
Standard
Min.
'lYPJlO]
Max.
0.8
-0.7
Vcc=Max., VI=VCC
Bus Hold
V
mV
100
V cc=Min., IIN= -18 rnA
Unit
V
2.0
-1.2
V
±1
!AA
±loo
Vcc=Max., VI=GND
±100
!AA
!AA
!AA
TBD
rnA
±1
Bus Hold
IBBH
IBBL
Bus Hold Sustain Current on Bus Hold
Input£8]
Vcc=Min.1 VI=2.0V
-50
I VI=0.8V
+50
IBHHO
IBHLO
Bus Hold Overdrive Current on Bus Hold
Input[7]
Vcc=Max., VI=1.5V
IOZH
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=2.7V
±1
!AA
10ZL
Vcc=Max., VOUT=O.5V
±1
!AA
los
High Impedance Output Current
(Three-State Output pins)
Short Circuit Currentf9]
Vcc=Max., VOUT=GND
-80
10
Output Drive Currentf9]
Vcc=Max., VOUT=2.5V
-50
10FF
Power-Off Disable
Vcc=Ov, VOUTs4.5V
Output Drive Characteristics for CV74FCT16952T
Parameter
Description
lest Conditions
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
-140
-200
rnA
-180
rnA
±1
!AA
Max.
Unit
Min.
1YpJIO]
Vcc=Min., IOH=-3rnA
2.5
3.5
V
Vcc=Min., IOH=~15 rnA
2.4
3.5
V
Vcc=Min., IOH= -32 rnA
2.0
3.0
Vcc=Min., IOL =64 rnA
V
0.2
0.55
V
Output Drive Characteristics for CY74FCT162952T, CY74FCT162H952T
lest Conditions
Min.
'lYPJlO]
Max.
Unit
IODL
Output LOW Current[9]
VCC=5V, VIN=VlH or VIL, Vour=1.5V
60
115
150
rnA
IODH
Output HIGH Currend9]
Vcc=5V, VIN=VIHorVn., VOUT=1.5V
-60
-115
-150
rnA
VOH
Output HIGH Voltage
Vcc=Min., IOH=-24 rnA
2.4
3.3
VOL
Output LOW Voltage
Vcc=Min., IOL=24 rnA
Parameter
Description
V
0.3
0.55
V
Capacitance[7] (TA = +25'C, f = 1.0 MHz)
'lYPJIO]
Max.
Unit
CIN
Input Capacitance
VIN = OV
4.5
6.0
pF
Cour
Output Capacitance
Vour= OV
5.5
8.0
pF
Parameter
Description
lest Conditions
Notes:
7. This parameter is guaranteed but not tested.
8. Pins with bus hold are described in the Pin Description.
9. Not more than one output should be shorted at a time. Duration of
short should not exceed one second. The use of high-speed test
apparatus andlor sample and hold techniques are preferable in order
to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output
may raise the chip temperature well above normal and thereby cause
invalid readings in other parametric tests. In any sequence of
parameter tests, los tests should be performed last.
10. 1YPical values are at Vcc=5.0V, TA=+25'C ambient.
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
Switching Characteristics Over the Operating Range
Pammeter
tpLH
tpHI..
tpZH
tpzL
74FCT169S2AT
74FCT1629S2AT
74FCT162H9S2AT
74FCT169S2BT
74FCT1629S2BT
74FCT162H9S2BT
74FCT169S2CT
74FCT1629S2CT
74FCT162H9S2CT
Description
Conditions[16]
MinJ17]
Max.
MinJ17]
Max.
MinJ17]
Max.
Unit
Fi~
No.8]
Propagation
Delay
CLKAB, CLKBA
toB,A
CL=50pF
RL=500Q
2.0
10.0
2.0
7.5
2.0
6.3
ns
1,5
1.5
10.5
1.5
8.0
1.5
7.0
ns
1,7,8
10.0
1.5
7.5
1.5
6.5
ns
1,7,8
Output Enable
Time
"OiillA, 500 Meg Q) resistance when
switch is OFF
• Performs bidirectional translator
function between 3.3V and 5.0V power
supplies
• CMOS for low power dissipation
• Edge-rate control circuitry for
significantly improved noise
characteristics
• Inputs and outputs interface with
5.0V CMOS, TTL, or 3.3V CMOS
• ESD:>2000V
• Power-otT disable
• Low power version
Functional Description
The CYBUS3384 and CYBUS3L384 are
ten-bit, two-port bidirectional bus
switches that allow one bus to be connected directly to, or isolated from,
another without introducing additional
propagation delay or ground noise. The
input and output voltage levels allow direct interface with TIL and CMOS devices. 1Wo bus enable signals, BEl and
BEz, turn on the upper and lower five
bits, respectively.
Designed with a low resistance of 2D, the
CYBUS3384 and CYBUS3L384 are ideal
for use in VME or other high DC drive
applications.
Logic Block Diagram
The power-off disable feature enables
modules and cards to be either inserted or
withdrawn from operating equipment
without shutting down power. Additionally, they facilitate bidirectional interfacing between 3.3V and 5V systems by
placing a single diode in series with the
5V Vee line and a resistor from pin 24 to
ground.
The CYBUS3384 and CYBUS3L384 are
also suitable for small signal analog application where crosstalk and off isolation
performance of -66 dB at 50 MHz is
required.
.
The CYBUS3L384 is a low-power version
of the CYBUS3384 with a typical Icc of
0.2 !lA.
Pin Configurations
BE,
DlP/SOIC/QSOP
Top View
BE_
Vee
Ao
So
A,
B,
A_
B_
B,
Ao
B,
B7
A7
Pv.
B,
As
B,
Ao
B,
A7
B7
A,
B,
Be
Ao
Ao
Ao
As~B.
BUS33B4·2
BUS3384-1
Description
A
Bus A, Inputs or Outputs
B
Bus B, Inputs or Outputs
BEbBEz
L,;.;:_ _"":;;.J-'
Function Table[l]
Pin Description
Name
B,
Bo
Ao
BE_
Inputs
BEl
H
L
H
L
Bus Switch Enable
BE2
H
H
L
L
BO-4
High-Z
Ao-4
High-Z
Ao-4
BS-9
High-Z
High-Z
AS-9
AS-9
Function
Non-connect
Connect
Connect
Connect
Note:
1. H =HIGH Voltage Level. L =LOW Voltage Level. X =Don't Care.
9-258
CYBUS3384
CYBUS3L384
Capacitance[6]
'lYpJ5]
Max.
Unit
CIN
Input Capacitance
3
4
pF
COUT
Output Capacitance
7
8
pF
Parameter
Description
Power Supply Characteristics
Parameter
Icc
Test Conditions[8]
Description
Quiescent Power Supply Current
LHcc
Quiescent Power Supply Current
(Input HIGH)[9]
IeCD
Dynamic Power Supply Currentl lO]
Ie
Thtal Power Supply Current[ll, 12]
Vee=Max., VINsGND or Vee, f=O
I 3384
I 3L384
Vee-Max., VIN=3.4V, f=O, Per Control Input
Notes:
8. For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
9. Per TIL driven input (VIN=3.4V); A and B pins do not contribute to
Icc. All other inputs at V CC or GND.
10. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency.
The A and B inputs generate no significant AC or DC currents as they
transition. This parameter is not tested but is guaranteed by design.
11. Ic
= IQUIESCENT + IINPUTS + IDYNAMIC
Ic
= Icc+AIcCDHNT+ IceD(fol2 + fIN!)
Ice
= Quiescent Current with CMOS input levels
Max.
Unit
0.1
0.2
rnA
0.2
3.0
!1A
2.0
rnA
0.12
Vee=Max., Control InIut Thggling,
@ 50% Duty Cycle, A B Pins Open
Vee-Max.,
lWo Control Inputs Toggling, @ 50%
Duty Cycle, fl =10 MHz, VIN=3.4V
1YPJ5]
roN
MHz
I 3384
I 3L384
4.6
rnA
4.4
rnA
= Power Supply Current for a TTL HIGH input
(VIN=3.4V)
DH
= Duty Cycle for TTL inputs HIGH
NT
= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair
(Hili or iliL)
fo·
= Clock frequency for registered devices, otherwise zero
f!
= Input signal frequency
= Number of inputs changing at f!
N!
12. Note that· activity on A or B inputs do not contribute to Ic. The
switches merely connect and pass through activity on these pins.
9-260
AIce
CYBUS3384
CYBUS3L384
~YPRESS
As
So
A,
8,
A2
So
As
B3
~
B.
'.0
4.0
....
_--- ....... -
.,;;;------
BE,
As
B,
As
Sa
AT
Br
As
Sa
As
BE2
Sa
,4g
3.0
g
....::J
2.0
~
1.0
D.•
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VIN, Volts
BUS3384-4
BUS3384-3
Figure 1. CYBUS3384
Figure 2. VOUT vs. Volts
Application Information
The CYBUS3384 is a ten-channel bidirectional solid state bus
switch with a "near zero" propagation delay.
The CYBUS3384 is organized into two groups of five N-Channel
MOSFETs. Each group has an independent control input for
output enable (see Figure 1). Because the N-channel MOSFET is
physically symmetric, the device pin can act as' an input or an
output.
The two enable input (BEl and BEz) sense TTL level signals and
drive the gates of the N-channel MOSFETs to Vee. With the
gate at Vee, the output voltage will follow the input voltage up to
Vee minus the threshold voltage. At this point the N-channel
MOSFET begins to tum off, rapidly increasing the effective resistance (RON) such that further increases to input voltage no
longer increase the output voltage (see Figure 2).
When either the input or output of the CYBUS3384 is near zero
volts and the gate is at Vee, the device is fully on, (low resistance) and available to pass large currents in either direction. In
this condition, the CYBUS3384 inputs are directly connected to
the outputs.
The CYBUS3384 provides no signal drive itself. As a result the
rise and falI tiDles of the CYBUS3384 outputs are determined by
the device driving the CYBUS3384 inputs rather than the
CYBUS3384 itself.
The propagation delay contributed by the CYBUS3384 is essentially zero when the N-channel gate is at Vce.
When the device is unpowered, the CYBUS3384 draws no current from the 110 or control inputs, and there is no current path
from the 110 or control to the power pins. There are no back
power or current drain problems when the device is unpowered.
The CYBUS3384 provides an ideal interface between SV and
3.3V components, since the CYBUS3384 provides no signal
drive, the Icc demands are small, limited to AC switching of the
N-channel gates, control circuitry, and a minute amount of 110
leakage. Due to the low current demands of the CYBUS3384, it
is possible to lower the CYBUS3384 Vee from a standard S.OV
supply with a small, inexpensive diode and a resistor to provide a
low-current full-bidirectional signal compatibility between SV
logic family signals and 3.3V logic family signals.
By adding a small, inexpensive diode and a resistor, the
CYBUS3384 Vee supply voltage can be shifted to 4.3V as shown
in Figure 3. SV signals will then be limited to 3.3V as they pass
through the CYBUS3384. 3.3V signals will pass back through
the CYBUS3384 unaltered and provide compatibility with SV
TTL input requirements. Note that the conversion is bedirectional and is limited to 3.3V independent of which side is driven
to SY. The CYBUS3384 could convert SV signals for use on a
3.3V bus of convert a SV bus to signals compatibile with 3.3V
components.
9-262
+5V
BUS3384-5
Figure 3. System with CYBUS3384
as 5V TTL to 3V Converter
CYBUS3384
CYBUS3L384
the bus through the CYBUS3384s and sets the BUSY bit notifying the other bus the SRAM is not available). Processor 1 owns
the bus and may now access the SRAM as needed. When finished, Processor 1 resets the OWN bit releasing the SRAM. The
SRAM access sequence is identical for Processor 2. In this application, the CYBUS3384 saves 10 ns compared to using an
F244 address buffer and an F245 dafa bus transceiver. This, in
turn, allows the use of a slower, more available SRAM, resulting
in lower system cost and power savings.
Selectable Termination Loads
In some applications, it is desirable to vary the characteristic termination impedance as the system configuration changes. This is
a common problem in automatic test equipment applications.
Because of their low ON resistance, miniature relays are often
used to switch termination loads. A single CYBUS3384 can replace as many as 10 such relays resulting in faster switching operation, lower power, and significant cost savings.
Fast Latch
Figures 8 and 9 show variations of a latch having a sub 1-ns propagational delay time using the CYBUS3384 in combination with
other components. This circuit has the advantage of being four
CYBUS3384
I
RAM or Other Logic
CYBUS3384
1
I
I
RAM or Other Logic
I
C1
BUS3384-ll
Figure 9. Latch Variation with Physical Capacitor
to ten times faster than an equivalent implementation using a 373
latch-and with no added noise. Figure 8 relies on the stray capacitance of the bus to maintain data when the CYBUS3384
opens. Assuming 50-pF stray capacitance at room temperature
and a 1 microampere input leakage current, a 1 volt "droop"
from the initial voltage level would take 50 microseconds. Figure
9 shows the addition of a physical capacitor if there is insufficient
stray capacitance. Figure 10 shows an active bus termination capable of sustaining the programmed logic for an indefinite period
oftime in the presence of Vee.
CYBUS3384
I
1--,..------, RAM or Other Logic
FCT244T
Stray Cap. (50 pF)
BUS3384-l2
BUS3384·10
1K
Figure 8. Latch Variation with Stray Capacitance
Figure 10. Active Bus Termination
Document #: 38-00355
9-264
WI"~CYPRESS
L#
Section Contents
Timing Technology Products
Device
CY2254
CY2255
CY2291
ICD2023
ICD2025
ICD2027
ICD2028
ICD2042A
ICD2051
ICD2053B
ICD2061A
ICD2062B
ICD2063
ICD2093
ICD6233
CY7B991
CY7B992
CY7B991O
CY7B9920
Page Number
Description
Pentium m Processor Compatible Clock Synthesizer/Drlver ......................... 10-1
Pentium Processor Compatible Clock Synthesizer/Drlver for OPTi Viper m Chipset. . . .. 10-7
Three-PLL Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-13
PC Motherboard Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-19
Motherboard Clock Generator ................................................ 10-27
PC Motherboard Clock Generator ............................................. 10-33
PC Motherboard Clock Generator ............................................. 10-39
Dual VGA Clock Generator .................................................. 10-51
Dual Programmable Clock Generator .......................................... 10-56
Programmable Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-64
Dual Programmable Graphics Clock Generator .................................. 10-71
Dual Programmable ECI..{f1L Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-85
Programmable Graphics Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-100
"Super Buffer" Clock Generator ............................................. 10-117
One-Time-Programmable Clock Oscillator ..................................... 10-127
Programmable Skew Clock Buffer (PSCB) ..................................... 10-130
Programmable Skew Clock Buffer (PSCB) ..................................... 10-130
Low Skew Clock Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-141
Low Skew Clock Buffer ..................................................... 10-141
~YPRESS
PRELIMINARY
Pin Summary
Name
Number
Description
VDD
1
Digital voltage supply
XTAUN[lj
2
Reference crystal input
XTALOUT[lj
3
Reference crystal feedback
Vss
4
Ground
OE
5
Output Enable, Active HIGH
PCLKO
6
CPU output clock
PCLKI
7
CPU output clock
VDD
8
Digital voltage supply
PCLK2
9
CPU output clock
PCLK3
10
CPU output clock
Vss
11
Ground
SI
12
CPU clock select input, bit 1
SO
13
CPU clock select input, bit 0
VDD
14
Digital voltage supply
BCLKO
15
PCI output clock
BCLKI
16
PCI output clock
Vss
17
Ground
BCLKS
18
PCI output clock
BCLK4
19
PCI output clock
VDD
20
Digital voltage supply
BCLK3
21
PCl output clock
BCLK2
22
PCl output clock
Vss
23
Ground
24 MHz
24
Floppy disk output clock (24 MHz)
12 MHz
25
Keyboard controller clock (12 MHz)
VDD
26
Digital voltage supply
REFI
27
Reference clock output (14.318 MHz)
REFO
28
Reference clock output (14.318 MHz)
Notes:
1. For best accuracy, use a parallel-resonant crystal, assume CLOAD
=
17 pF.
10-2
CY2254
•
CY2254
PRELIMINARY
·rcYPRESS
Electrical Characteristics VDD = 3.3V :t5%, Tc = O°C to +70°C
Parameter
Description
Test Conditions
VIH
High-level Input Voltage
Except Crystal Inputs
VIL
Low-level Input Voltage
Except Crystal Inputs
VOH
High-level Output Voltage
VDD = VDD Min.
VOL
Low-level Output Voltage
Min.
Max.
Unit
O.S
V
2.0
VDD = VDD Min.
IOH = 6mA
PCLK
IOH= 12mA
BCLK,REFO
IOH = 4mA
24, 12 MHz
IOH = SmA
REF1
IOL=6mA
PCLK
IOL = 12mA
BCLK,REFO
IOL= 4mA
24, 12 MHz
IOL- SmA
REF1
V
204
V
004
V
IIH
Input High Current
VIH = VDD - O.5V
-5
+5
IlL
Input Low Current
VIL = O.5V
-5
+5
loz
Output Leakage Current
Three-state
-10
+10
flA
flA
flA
IDD
Power Supply Current
VDD = 30465, VIN = 0 or VDD
90
mA
Min.
Max.
Unit
40%
60%
Switching Characteristics[4]
Parameter
t1
Ontput
All
Name
Description
Output Duty CycletS]
tl = tlA + tIB
t2
PCLK,BCLK
Output Slew Rate
OA-2.4V
13
REF, 24, 12 MHz
Rise Time
OA-2AV
t4
REF, 24, 12 MHz
Fall Time
2A-OAV
ts
PCLK
CPU Skew
CPU-CPU clock skew
t6
BCLK
PCISkew
PCI-PCI clock skew
500
ps
t7
PCLK,BCLK
CPU-PCI Skew
CPU to PCI clock skew (CPU leads)
5
ns
t8
PCLK
Cycle-Cycle Clock Jitter
RMS clock jitter
200
ps
Switching Waveforms
Duty Cycle Timing
1.5V
2254-3
Notes:
4. All parameters specified with outputs fully loaded.
5.
10-4
Duty cycle is measured at l.Sy.
1
1
V/ns
4
ns
4
ns
250
ps
l:rcYPRESS
.========P='RE=L=L=M=IR=~=R=Y====CY=22=5=4
Test Circuit
Voo
26
.1 \IF
1::
Voo
.1 \IF
4
23
8
20
1::
.1 \IF
.1 \IF
1::
.1 \IF
17
11
'-----.---114
1::
OUTPUTSI---..,---.O
1::
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information
Ordering Code
CY2254
Package
Name
S21
Operating
Range
Package 'lYpe
28·PinSOIC
Commercial
Document #: 38-00426
10-6
PRELIMINARY
.1!rcYPRESS
Pin Summary
Name
Number
Description
VDD
XTALINllJ
1
Digital voltage supply
2
Reference crystal input
XTAWUT[1J
3
Reference crystal feedback
GND
4
Ground
OE
5
Output Enable, Active HIGH
CPUCLKO~Z
6
CPU clock output, three-stateable by OE
CPUCLKl_Z
7
CPU clock output, tbree-stateable by OE
VDD
CPUCLK2
8
Digital voltage supply
9
CPU clock output
CPUCLK3
10
CPU clock output
GND
11
Ground
SI
12
CPU clock select input, bit 1
SO
13
CPU clock select input, bit 0
VDD
PCICLKO
14
Digital voltage supply
15
PCl clock output
PClCLKI
16
PCI clock output
GND
17
Ground
PClCLKS
18
PCl clock output
PCICLK4
19
PCl clock output
VDD
PCICLK3
20
Digital voltage supply
21
PCI clock output
PCICLK2
22
PCl clock output
GND
23
Ground
CPUCLK4
24
CPU clock output
ECLK
25
Early clock output, leads CPU clocks by 2 to 5 ns
VDD
REFI
26
Digital voltage supply
27
Reference clock output (14.318 MHz)
REFO
28
Reference clock output (14.318 MHz)
Notes:
1. For best accuracy, use a parallel-resonant crystal, assume CLOAD =
17 pF.
10-8
CY2255
~YPRESS
CY2255
PRELIMINARY
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Test Conditions
HIGH-level Output Voltage
VDD = VDD Min.
WW-level Output Voltage
VDD = VDD Min.
Min.
IOH = 6mA
CPUCLK,
ECLK
IOH = 12mA
PCICLK,
REFO
IOH = 8mA
REF1
IOL=6mA
CPUCLK,
ECLK
IOL = 12mA
PCICLK,
REFO
IOL=8mA
REF1
Max.
2.4
Unit
V
0.4
V
0.8
V
VIH
HIGH-level Input Voltage
Except Crystal Inputs
VIL
WW-level Input Voltage
Except Crystal Inputs
2.0
V
IIH
Input HIGH Current
VIH = VDD - 0.5V
-5
+5
IlL
Input LOW Current
VIL = O.5V
-5
+5
loz
Output Leakage Current
Three-state outputs
-10
+10
iJA·
iJA
iJA
IDD
Power Supply Current
VDD = 3.465, VIN = 0 or VDD
90
mA
Min.
Max.
Unit
40%
60%
Switching Characteristics[4]
Parameter
Output
Description
Name
tl
All
Output Duty Cycle!S]
tl = tlA + tlB
t2
CPUCLK,ECLK,
PCICLK
Output Slew Rate
0.4-2.4V
t3
REFO
Rise Time
20% - 80% OfVDD
2.5
t3
REF1
Rise Time
20% - 80% OfVDD
4
ns
t4
REFO
Fall Time
20% - 80% of VDD
2.5
ns
4
REF1
Fall Time
20% - 80% of VDD
4
ns
ts
CPUCLK
CPU Skew
CPU-CPU clock skew
t6
ECLK, CPUCLK
ECLKSkew
Early-CPU clock skew (ECLK leads)
1
2
V/ns
ns
250
ps
5
ns
t7
PCICLK
PCISkew
PCI-PCI clock skew
500
ps
t8
CPUCLK,
PCICLK
CPU-PCI Skew
CPU to PCI clock skew (CPU leads)
750
ps
t9
CPUCLK
Cycle-Cycle Clock Jitter
Clock jitter
250
ps
Notes:
4. All parameters speCified with outputs fully loaded.
5.
10-10
Duty cycle is measured at 1.5V,
«
PRELIMINARY
rcYPRESS
Switching Wavefonns (continued)
PCI·PCI Clock Skew
PCICLK
PCICLK
2255-7
CPU·PCI Clock Skew
CPUCLK
PCICLK
Test Circuit
Voo
26
.01 !-IF
.01 !-IF .:::c.
Voo
.:::c.
4
23
8
20
.01 !-IF
.01 !-IF.:::c.
.:::c.
17
11
' - - - - - - - - r - - - - i 14
OUTPUTS!----r--O
.01 !-IF .:::c.
GLOAD .:::c.
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information
Ordering Code
CY2255
Package
Name
S21
Package 1Ype
28·Pin sOle
Operating
Range
Commercial
Document #: 38-00442
10-12
CY2255
PRELIMINARY
CY2291
s
p'In ummary
Name
Number
Description
32XOUT
1
32.768 kHz crystal feedback
32K
2
32.768 kHz ouiput (always active ifVBATI is present)
CLKC
3
Configurable clock output C
VDD
4
Voltage supply to I/O
GND
XTALIN[1,2]
5
Gn;lUnd
6
Reference crystal input
XTALOUT[1,2]
7
Reference crystal feedback
XBUF
8
Buffered reference clock output
CLKD
9
Configurable clock output D
CPUCLK
10
CPU frequency clock output
CLKB
11
Configurable clock output B
CLKA
12
Configurable clock output A
FLOPPYCLK
13
Floppy clock output (24 or 32 MHz)
CPU clock select input, bit 0
SO
14
Sl
15
CPU clock select input, bit 1
VDD
16
Analog voltage supply to core
S2!SUSPEND
17
CPU clock select input, bit 2. Optionally enables suspend feature when LOW.
SHUTDOWN/OE
18
Places outputs in three-statd3] condition and shuts down chip when LOW. Optionally, only places
outputs in three-statd3] condition and does not shut down chip when LOW.
VBATI
32XIN
19
Battery supply for 32.768 kHz circuit
20
32.768 kHz crystal input
Operation
The CY2291 is a third-generation Clock Generator, upwardly
compatible with the industry standard ICD2023 and ICD2028.
The CY2291 continues the tradition of these parts by providing a
high level of customizable features to meet the diverse clock
generation needs of modern multi-function motherboards and
other synchronous systems.
The CY2291 prov,ides a highly configurable set of clocks for PC
motherboard applications. Each of the four configurable clock
outputs can be assigned 1 of 30 frequencies in any combination.
Multiple outputs configured for the same frequency will have low
(.$.500 ps) skew, in effect providing on-chip buffering for heavily
loaded signals.
The CY2291 includes two independent power-saving modes for
Green PC or laptop applications. Shutdown mode, controlled by
the SHUTDOWN/OE pin, shuts down all of the active circuitry
on the chip except for the 32 kHz oscillator. The resulting
current draw on the V DD pins is typically less than 10 fAA.
Suspend mode, controlled by the S2/SUSPEND pin, shuts down
a customizable set of outputs andlor PLLs when they are not
needed. In addition to these two modes, most configurations
support disabling unused outputs and PLLs.
The CY2291 can be configured for either 5V or 3.3V operation.
The internal ROM tables use EPROM technology, allowing
Notes:
1. For best accuracy, use a parallel-resonant crystal.
2. Assume CLOAD = 17 pF.
factory configuration for operation at non-standard frequencies.
The reference oscillator has been designed for 10 MHz to 25
MHz crystals, providing additional flexibility. All configurations
are factory programmable, providing short sample and production lead times.
Output Configuration
The CY2291 has five independent frequency sources on chip.
These are the 32 kHz osCillator, the reference oscillator, and
three Phase LOcked Loops (PLLs). Each PLL has a specific
function. The SYSCLK PLL drives the FWPPYCLK output
and provides the fixed frequencies on the configurable outputs.
The CPU PLL responds to the select inputs (SO-S2) to provide
eight user selectable frequencies with smooth slewing between
frequencies.
The Utility PLL is available. to provide
miscellaneous frequencies not provided by the other frequency
sources.
The CY2291 has four fixed frequency outputs (32K, XBUF,
FWPPYCLK, and CPUCLK) and four configurable outputs
(CLKA-CLKD). Each of these configurable outputs has an
identical se,t of 30 output frequency options. The list of
frequency options includes frequencies derived from four of the
five sources on the chip. Please refer to the application note
"Understanding the 2291" for information on configuring the
part.
3. The CYZ291 has weak pull-downs on all outputs (except 32K). Hence,
when a three-state condition is forced on the outputs, the output pins
are pulled LOW.
10-14
PRELIMINARY
CY2291
Switching Characteristics[7J
Parameter
Name
Description
Min.
'Jyp.
Max.
Unit
t1
Output Period
Clock output range, 5V operation
10
(100 MHz)
5000
(200KHz)
ns
t1
Output Period
Clock output range, 3.3V operation
12.5
(80 MHz)
5000
(200 KHz)
ns
Output Duty CyclerSJ
Duty cycle for outputs, defined as t2 +- t1 [9J
t3
Rise time
Output clock rise timd 10J
5
ns
4
Fall time
Output clock fall timd 10J
4
ns
ts
Output Disable Time
Time for output to enter three-state mode
after SHUTDOWN/DE goes LOW
15
ns
t6
Output
Time for output to leave three-state mode
after SHUTDOWN/DE goes HIGH
15
ns
t7
Skew
Skew delay between any identical or related
outputs, as measured @TTL Vth[llJ
0.5
ns
ts
CPUCLKSlew
Frequency transition rate
20.0
MHz!
ms
t9A
Clock Jitter
Peak-to-peak period jitter (t9A max. - t9A
min.) percent of clock period
5
%
t9B
Clock Jitter
Peak-to-peak period jitter (fOUT ~ 16 MHz)
700
ps
t9C
Clock Jitter
±30 jitter (CPUCLK @ ~ 50 MHz)
250
ps
t10
Lock Time
Time for VCO to settle between changes
50
ms
100 (5~
80 (3.3 )
MHz
.AO%
50%
< 0.25
2.0
Slew Limits
<2
5
4
60%
Switching Waveforms
All Outputs Duty Cycle and Rise/Fall Time
OUTPUT
2291-3
Output Three-State Timing[3J
OE
ALL
THREE-STATE
OUTPUTS
2291·4
Note:
7. Guaranteed by design, not 100% tested.
8. XBUF duty cycle depends on XTALIN duty cycle.
9. Measured at IAV.
10. Measured between OAV and 2.4Y.
II. "Related" outputs are defined as having identical sources internally.
Generally they are multiples of each other. Th meet the skew
guarantee, outputs must have identical capacitive loads.
10-16
PRELIMINARY
CY2291
CY2291 CONFIGURATION REQUEST FORM
Customer
Contact..._ _ _ _ __
FAE/Sales, _ _ _ __
Phone #
Fax #
Date
1. OPERATING VOLTAGE (circle one)
3.3V
5.0V
2. INPUT REFERENCE FREQUENCY
Default reference ~ 14.318 MHz. If a different reference
is desired, please enter value between 10 and 25 MHz.
3. PLL FREQUENCIES
Harmonics will result at the outputs if two or more PLLs run at frequencies which are integral multiples of each other.
Note: "Off" is a valid frequency for any PLL.
Select
so
S2S1
CPLL (CPU PLL)
000
001
010
011
100
101
110
111
If suspend option chosen,
then request frequencies
only for S2 ~ 1
shaded areas for Cypress use only
shaded areas for Cypress use only
UPLL (UTILITY PLL)
SPLL (SYSCLK PLU
Default frequency is 96 MHz @
51{ 48 MHz @ 3.3V
4. OUTPUT CONFIGURATION
1. Ref
2. Ref/2
3: Ref/4
4. Ref/8
5.CPLL
Available Output Options
6. CPLIj2
7. CPLIj4
8. CPLIj8
9. UPLL
10. UPLIj2
11. UPLIj4
12. UPLIj8
13. SPLL
14.SPW2
15. SPLIj3
CLKA (select 1-30, oft) ~
CLKB (select 1-30, oft)
CLKC (select 1-30, oft)
CLKD (select 1-30, oft)
16. SPLIj4
17.SPW5
18.SPW6
19. SPLIj8
20. SPLIjlO
21.SPWI2
22. SPLIj13
23. SPLIj20
24. SPLI)24
25. SPLI)26
26. SPLIj40
27. SPLIj48
28. SPLIj52
29. SPLIj96
30. SPLIjl04
CPUCLK (select 5 or oft)
FLOPPYCLK (select 14, 15, 16, or oft)
XBUF (select 1 or oft)
for CLIill, Ref/8 is replaced with Ref/3
5. SHUTDOWN OPTION (circle one)
6. SUSPEND OPTION (circle one)
If Ths, assign resources by circling any of the following:
Suspending a PLL automatically suspends its outputs.
Y
Y
CPLL
UPLL
SPLL
7. FOR CYPRESS / Ie DESIGNS USE ONLY
N
N
XBUF
CPUCLK
FLOPPYCLK
CLKA
CLKB
CLKC
CLKD
~~~~~~
10-18
ICD2023
Logic Block Diagram
VBATT~
32XIN
~
I
32.768 KHz
Oscillator t--------.....,.------~r---..........32XOUT.
~
14.318 MHz
XTALIN
XTALOUT
(Input/rom
14.31818 MHz
Crystal)
S2------~~----,
S1/DATA-........;..i
SO/CLOCK
OE
MODE
-------------------~
f f f
GND
VDD
CPUCLK Output Values (MHz)
20 24 32 40 50 66.6 80
or User Programmable
AVDD
ICD2023·2
10-20
.~YPRESS
ICD2023
CPUCLK Programmable Oscillator: Selection Mode
Table 4. Mux Bits Mo-Ml
CPUCLK offers a programmable output based on two modes of
operation. The first mode uses three select lines to select one of
eight different preset frequencies, while the other mode allows
the user to program any desired frequency between 10 MHz and
80 MHz. The two different modes are controlled by the MODE
signal.
When MODE=1, the select lines can be changed to choose
different frequencies. When this occurs, PLL #2 will immediately
seek the newly selected frequency as shown in the following table.
During the transition period, the CPUCLK output will not glitch.
Divisor
Ml
Mo
0
0
16
0
1
4
1
0
2
1
1
1
S2
SI
SO
(MHz)
Actual Freq.
(MHz)
PPM
Error
0
0
0
20.000
20.0454
2272
0
0
1
24.000
23.9746
1058
The M2 mux bit is used to select which one of the two
Phase-Locked Loops is to be utilized in the CPUCLK output.
Normally, the PLL #2 section (see Logic Block Diagram) is used.
However, if the desired output frequency requires f(vco) to be
set to 48 MHz, then PLL #1 section should be used. This both
reduces power consumption (since only one VCO is activated)
and eliminates the possibility of jitter which can arise when two
VCOs of the sanie frequency beat (heterodyne) against each
other.
0
1
0
32.000
32.0455
1422
Table 5. Mux Bits M2
0
1
1
40.000
40.0909
2272
1
0
0
50.000
49.9923
154
Table 2. CPUCLK Output with MODE=1
Desired Freq.
1
1
1
0
1
1
1
66.667
66.5962
57
0
80.000
80.1818
2272
1
100.00018 J
99.8182
1818
Ml
CPUCLK
0
PLL#2
1
CPUCLK Programmable Oscillator: Serial Mode
When MODE=O, CPUCLK enters its programmable mode.
Signals SO (clock) and Sl (data) become a serial interface,
allowing a 20-bit number to be shifted in. In ICD2023
programmable oscillator (CPUCLK) requires a 2O-bit programming word (W). This word contains 4 fields:
Table 3. Programming Word Bit Fields
-
PLL #1 (48 MHz)
The Index field (I) is used to preset the VCO to an appropriate
range. The value for this field should be should be chosen from
Table 6. (Note that this table is referenced to the VCO frequency
f(vco), rather than to the desired output frequency.)
Table 6. Index Field (I)
I
f(Vco) MHz
0001
40.0-47.5
0010
47.5-52.2
Field
# of Bits
0011
52.2-56.3
Index (1)[9]
4
0100
56.3-61.9
P Counter value (P)
7
0101
61.9-65.0
Mux(M)
3
0110
65.0-68.1
o Counter Value (0)110]
6
0111
68.1-80.0
1111
'ThrnoffVCO
If a signal S2=1 and MODE=O, then the reference frequency
(14.31818 MHz) is multiplexed to the CPUCLK output. This
enables a glitch-free transition to the reference frequency while
the VCO stabilizes.
The frequency of the programmable oscillator f(VCO) is
detennined by these fields as follows:
P'=P-3 0'=0-2
f(VcO)=2 x f(REF) x P/O
where f(REF)=Reference frequency=14.31818 MHz.
The value of f(VCO) should be kept between 40 MHz and
80 MHz. Therefore, for output frequencies below 40 MHz,
f(VCO) must be multiplied up into the required range. The mux
bits allow a post-divide of the higher VCO to bring the output to
those desired values below 40 MHz.
If the desired VCO frequency lies on a boundary in the table (if it
is exactly the upper limit of one entry and the lower limit of the
next) then either index value may be used (since both limits are
tested), but we recommend using the higher one.
Th assist with these calculations, Cypress/IC Designs provides
BitCalc (Part #ICDIBCALC), a Windows m program which
automatically generates the appropriate ptogramming words
from the user's reference input and desired output frequencies, as
well as assembling the program words for such things as control
and power-down registers. Contact your local Cypress representative for more information.
Notes:
8. Duty cycle specs not guaranteed above 80 MHz.
9. MSB (Most Significant Bits).
10. LSB (Least Significant Bits).
10-22
~YPRESS
ICD2023
Electrical Characteristics Over the Operating Range
Parameter
Min.
Max.
VBATI
Backup Battery Voltage
Description
Typical=3.0 Volts
Test Conditions
2.0
5.0
VOH
Output HIGH Voltage
IOH = - 4.0rnA
2.4
IOL= 4.0 rnA
VOL
Output LOW Voltage
VOH-32
32.768 kHz Output HIGH
VOL-32
32.768 kHz Output LOW
VIL
Input LOW Voltage
Except crystal inputs
VIH
Input HIGH Voltage
Except crystal inputs
IIH
Input HIGH Current
VIH = VDD-0.5V
IlL
Input LOW Current
VIL= +0.5V
Unit
V
V
0.4
V
V
V
0.8
2.0
V
10
J.tA.
J.tA.
J.tA.
65.0
rnA
50
J.tA.
150
-250.0
Ioz
Output Leakage Current
(Three-state)
IDD
Supply Current
VDD = Max., fully loaded output, typical = 40[11]
IBATI
Backup Battery Current
VBATI = 3'1, fully loaded output, typical = 8 J.tA.
25
V
Switching Characteristics Over the Operating Rangef l2]
Parameter
Description
Test Conditions
CPUCLK
Clock Output
tl
Ref Frequency
Reference Oscillator nominal value
t2
Duty Cycle
Duty cycle for the outputs defined as t2A+t2B
Min.
Max.
Unit
10
80
MHz
14.318
MHz
40%
60%
t3
Rise Time
Rise time for the outputs into a 25 pF load
4
4
Fall Time
Fall time for the outputs into a 25 pF load
4
ns
ns
ts
Set-UpTime
Delay required after MODE goes LOW prior to
starting the SO clock line
0
ns
t6
Cycle Time
Minimum cycle time for the SO clock
200
ns
t7
Set-UpTime
Time required for the data to be valid prior to the
rising edge of SO/CLOCK
10
ns
t8
Hold Time
Time required for the data to remain valid prior
to the rising edge of SO/CLOCK
5
ns
t9
Clk Unstable
Time CPUCLK remains valid after MODE signal
goes LOW
0
ns
tlO
C1k Stable
Time required for the CPUCLK to become valid
after last SO/clock edge
10
msec
t11
Clk Unstable
Time the output oscillators remain valid after the
SO, Sl or S2 select signals change value
0
ns
tl2
Clk Stable
Time required for the outputs to become valid
after the SO, Sl, or S2 signals change value
10
msec
t13
Three-State
Time for the outputd to go into three-state mode
after OE signal assertion
12
ns
tl4
ClkValid
Time for the outputs to recover from three-state
mode after OE sIgnal goes HIGH
12
ns
,,
Notes:
II. CPUCLK = 66 MHz and inputs at GND or VDD.
12. Input capacitance is typically 10 pF, except for the crystal pads.
10-24
'~YPRESS
ICD2023
Switching Waveforms (continued)
State Timing
SO-S2
(MODE=1) _ _ _- . I
FREQUENCY SELECT DATA CHANGING
'1-_
_ __
OE
CPUCLK,
24.0 MHz,
12.0MHz&
1.8432 MHz
THREE-STATE OUTPUT
[ . - - - - - - - t12
-------1
ICD2023-6
Test Circuit
Voo - - - - I
DEVICE
UNDER
TEST
CLKout
22Q
AVoo -'l/liIr----r
~--f
2.2~F
.:::r::
Tantalum
-=
GND
Ordering Information[13]
Ordering Code
ICD2023
Package
Name
S5
Package 'JYpe
20-PinSOIC
Operating
Range
Commercial[14]
Note:
13. Please contact your local Cypress representative.
14. O"C to +70"C
Document #: 38-00397
Windows is a trademark of Microsoft Corporation.
10-26
~YPRESS
ICD2025
Pin Summary
Name
Number
Description
SYSBUS
1
):luffered 14.31818 MHz crystal output (z)
SYSCLK
2
System clock output (see Table 2)
OE
3
Output Enable three-states output when signal is LO. (pin has internal pull-up)
GND
4
Ground
fREF/
XTALIN[lj
5
Reference Oscillator input for all internal phase-locked loops (nominally from a parallel-resonant
14.31818 MHz crystal). Optionally PC System Bus Clock.
XTALOUTLIJ
6
Oscillator output to a reference crystal.
CO
7
CPUCLK Select signal-Bit 0 (internal pull-up)
SO
8
SYSCLK Clock Select signal-Bit 0 (internal pull-up)
SI
9
SYSCLK Select signal-Bit 1 (internal pull-up)
Cl
10
CPUCLK Select signal-Bit 1 (internal pull-up)
C2
11
CPUCLK Select signal-Bit 2 (internal pull-up)
S2
12
SYSCLK Select signal-Bit 2 (internal pull-up)
VOD
13
+5V to I/O Ring
C3
14
Ci'UCLK Select signal-Bit 3 (internal pull-down)
CPUCLK
15
CPU Clock Output (See CPUCLK Selection Thble)
AVDD
16
+5V to Analog Core
Available Frequencies (MHz)
SYSCLK
CPUCLK
1.843
16.000
3.686
20.000
8.000
25.000
12.000
32.000
18.432
33.333
20.000
40.000
24.000
50.000
32.000
66.667
80.000
100.000
Note:
1. For best accuracy, use a paraIIel·resonant crystal, assume CWAD = 17 pH
10-28
~YPRESS
ICD20Z5
a
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
nottested.)
.
Supply Voltage to Ground Potential ......... -0.5V to +7.0V
DC Input Voltage ................... -O.5V to VDD +0.5V
Storage Thmperature ................... -65°C to + 150°C
Max soldering temperature (10 sec) ................. 260°C
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 125 ° C
Operating Range
Ambient
Thmperature
O°C
s TAMBIENT
S
Voo&AVoo
5V±5%
70°C
Electrical Characteristics Over the Operating Range
ICD2025
Parameter
Description
Thst Conditions
Max.
Min.
Unit
V
VOH
Output HIGH Voltage
IOH= -4.0mA
2.4
VOL
Output LOW Voltage
IOL= 4.0 rnA
VJti
Input HIGH Voltage
Except crystal inputs
VIL
Input LOW Voltage
VVxcept crystal inputs
IqI
Input HIGH Current
VJH = VDD-O.5V
IlL
Input LOW Current
VIL = 0.5V
loz
Output Leakage Current
(Three-state)
10
jAA
IDD
Power Supply CUITent
Inputs @ VDD or GND
60
mA
jADD
Analog Power Supply
Current
6
rnA
0.4
V
2.0
V
0.8
V
150
jAA
-250
jAA
Switching Characteristics Over the Operating Rangd2J
Parameter
Name
Drscription
f(REF)
Reference Frequency
t(REF)
t1·
Ref Clock Period
1 +f(REF)
Input Duty Cycle
Duty' cycle for the inputs defmed as
t1+t(REF)
t2
Output Period
CPUCLK output value
t3
Output Duty Cycle
Duty cycle for the outputs defined as t3+t2
(measured at 2.5V)
Reference 9scillator nominal value
Min.
typ.
Max.
Unit
4
14.318
26
MHz
38.5
69.8
2500
ns
25%
50%
75%
10
100 MHz
544
1.84 MHz
40%
60%
ns
t4
Rise Time
Rise time for the outputs into a 25 pF load
4
ns
ts
Fall Time
Fall time for the outputs into a 25 pF load
4
ns
1(;
Three-State
Time for the outputs to go into three-state
mode after OE signal assertion
12
ns
t7
ClkValid
Time for the outputs to recover from threestate mode after OE signal goes HIGH
12
ns
tMUXREF
ClkStable
Time required for the outputs to become
valid after CO-C3 or SO-S2 select signals
change value
6.9
msec
tfreq1
freq1 Output
Old frequency output
tfreq2
freq2 Output
New frequency output
f(REF) Mux Time
Time clock output remains HIGH while
output muxes to reference frequency
t8
t9
tfreq2 Mux Time
Time clock output remains HIGH while
output muxes to new frequency value
Note:
2. Inpu! capacitance is typically 10 pF, except for the crystal pads.
10-30
3.4
t(REF)
-2tfr ,q2
"'"2
5
3 t(REF)
ns
2
3 t1"q2
2
ns
ICD2025
1£iP7cYPRESS
Test Circuit
Voo
220
161--+----,
1::. .01 J.tF 1::.
22 J.tF
131-~------~
4
OUTPUTSI---r--G
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information[3]
Ordering Code
lCD2025
Package
Name
SI
Operating
Range
Package 'JYpe
Commercial[4]
16-Pin SOIC
Note:
3.
4.
Contact your local Cypress representative.
O·C to +70·C
Example: order lCD2025SC for the lCD2025, 16-pin plastic
SOIC, commercial temperature range device.
Document #: 38-00398
10.-32
Voo
ICD2027
Q-YPRESS
. Pin Configuration
SOIC
TopVlew
32XOUT
32.768 kHz
80
81
GND
XTALIN
XTALOUT
14.318 MHz
1.843 MHz
CPUCLK
32XIN
VBATT
82
83
AVDD
VDD
OE
l"WRDWN
24.0 MHz
CPUCLK/2
ICD2027·2
Pin Summary
Name
Number
32XOUT[1]
1
Description
Oscillator output to a 32.768 kHz parallel-resonant crystal
32.768 kHz
2
32.768 kHz clock output
Input select line 0 for CPUCLK (pin has internal pull-down)
SO
3
SI
4
Input select line 1 for CPUCLK (pin has internal pull-down)
GND
5
Ground
XTALIN[1]
6
Reference Oscillator input for all internal phase-locked loops (nominally from a parallel-resonant
14.31818 MHz crystal). Optionally PC System Bus Clock.
XTALOUT[l]
7
Oscillator Output to a reference crystal.
14.318 MHz
8
14.31818 MHz clock output
1.8432 MHz
9
1.8432 MHz clock output
CPUCLK
10
CPUCLK programmable clock output (See Table 1 for values.)
CPUCLK/2
11
Half the frequency of CPUCLK. Output is phase-coherent with the CPUCLK output.
24.0 MHz
12
24.0 MHz clock output
PWRDWN
13
Puts device in Power-Down mode when signal is pulled LOW (pin has internal pull-down)
OE
14
Output Enable three-states output when signal is LOW (pin has internal pull-up)
VDD
15
+ 5V to I/O ring
AVDD
16
+5V to analog core
S3
17
Input select line 3 for CPUCLK (pin has internal pull-down)
S2
18
Input select line 2 for CPUCLK (pin has internal pull-down)
VBATI
32XIN[lj
19
+2 to +5V for battery backup operation
20
Oscillator input from 32.768 kHz crystal
Note:
1. Forbestaccuracy, use a parallel-resonant crysta!, assume CWAD = 17pR
10-34
ICD2027
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Supply Voltage to Ground Potential ......... -O.5V to +7.0V
DC Input Voltage ................... -O.5V to VDD +O.5V
Storage Thmperature ................ '. . . - 65 ° C to + 1500 C
Max soldering temperature (10 sec) ................. 260°C
Junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 125°C
Operating Range
Ambient
Thmperature
VDD& AVDD
5V±5%
O°C :s; TAMBIENT :s; 70°C
Electrical Characteristics Over the Operating Range
Parameter
Description
Thst Conditions
Min.
Max.
Unit
5.0
V
VBATT
Backup Battery Voltage
'!ypical = 3.0V
2.0
VIR
Input mGH Voltage
Except Crystal Inputs
2.0
VIL
Input LOW Voltage
Except Crystal Inputs
VOH
Output HIGH Voltage
IOH= -4.0mA
VOL
Output LOW Voltage
IOL = 4.0mA
0.4
V
IIH
Input HIGH Current
VIR = 5.25V
150
V
0.8
2.4
10
!LA
!LA
!LA
65
rnA
7.5
rnA
15
!LA
-250
IlL
Input LOW Current
VIL= OV
Ioz
Output Leakage Current
(Three-state)
IDD
Power Supply Current
Inputs @ VDD or GND
IDD-PD
Soft Power-Down Current
IBATT
Backup Battery Current
V
V
20
'!ypical = 5 !LA
Switching Characteristics[6]
Parameter
Name
Description
Min.
Max.
14.318
Unit
fREF
t(REF)
Reference Period
1 +f(REF)
t1
Duty Cycle
Duty cycle for the output clock defined as t lA + t 1B
t2
Rise Time
Rise time for the outputs into a 25-pF load
4
ns
t3
Fall Time
Fall time for the outputs into a 25-pF load
4
ns
t4
Three-state
Time for the outputs to go into three-state mode
after OE signal assertion
12
ns
t5
clk Valid
Time for the outputs to recover from three-state
mode after OE signal goes HIGH
12
ns
t6
CPUCLK/2 Skew
Skew delay between CPUCLK and CPUCLK/2
outputs
2
ns
tfreql
freq1 Output
Old frequency output
tfreq2
freq2 Output
New frequency output
t7
f(REF) Mux Time
Time clock output remains HIGH while output
muxes to reference frequency
t(REFy2
3(t(REF)f2)
ns
t8
tfreq2 Mux Time
Time clock output remains HIGH while output
muxes to new frequency value
tfre q:zf2
3/(tfreq:zf2)
ns
6.2
msec
tMUXREF
Reference input normal value
'JYp.
Reference Freqnency
MHz
69.8
Time for VCO to settle between changes
Note:
6. Input capacitance is typically 10 pF, except for the crystal pads.
10-36
40%
ns
60%
1
~YPRESS
ICD2027
Ordering Information
Ordering Code
ICD2027
Package
Name
S5
Temperature Range
CPUCLK ROM Option
C=Commercial=O·C to +70·C
1
Package 1YPe
20-PinSOIC
Example: Order ICD2027SC-1 for the ICD2027, 20-pin plastic
SOIC, commercial temperature range device which uses the
standard CPUCLK ROM Option 1 table of frequency decodes.
Custom CPUCLK ROM decodes are available by special order.
Please call your local Cypress representative.
Document #: 38-00399
10-38
~PRESS;===========================~IC~D~2~02~8
Block Diagram
:=l~r-....L.----'
VBATT
3;:~~
OSCILL6.TOR/r_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~kHZ
(INPUT FROM
32.768 kHz
CRYSTAL)
S2---"
S1----~_+---~
SO---+I
XTALIN
OSCILL6.TOR
~~.-I
XTALOUT
(INPUT FROM
14.31818 MHz
CRYSTAL)
USERCONFIGURABLE
LOGIC
DIVIDERS AND
MUXMATRIX
t t t
GND Voo
OE
AVoo
ICD2028-2
10-40
~YPRESS
ICD2028
14.31818 MHz
4.77 MHz
CPU
CPU/2
48 MHz
S 2 - - -..
S1----~t-------+_--------~--~
24 MHz
SO---~
16MHz
XTALIN
XTALOUT
9.6 MHz
12 MHz
8 MHz
3.686 MHz
1.843 MHz
1 MHz
UPLLJ4
32XOU
UPLLJ2
UPLL
3
UROMSel (UO-U2)
t
GND
Voo
AVoo
ICD2028-3
32.768 KHz
VBATT
Figure 1. Inputs
32.768 KHz
TestMode
--;::;:::===:;---
CPU
UROMSel
24MHz---------~
24.0 MHz
144 . 3~1~8~18~M~H~Z~:r============1I-i
3.686 MHz 8 MHz -------<.!
9.6 MHz - - - - - . I
12 MHz
24
=====:::l
CLKA
UPLLJ4 - - - - - . I
(TEST)
- - - - L___-J
1 MHz
8MHz
16MHz
CPU
CPU/2
UPLLJ4
(TEST)
SYSBUS
B
MUX
BMuxSel
1.843 MHz - - - - _ , - - - - - - ,
3.686 MHz - - - - - . I
4.77 MHz - - - - - . I
8 MHz ------- 50 MHz .
R post-divide = 1
post-divide ~ 2
Duty cycle of CLKOUT
measured at VDoI2 (CMOS)
post-divide - 1
threshold
Rise Time
t4
Rise time for the clock output into a 25 pF load
Note:
4.
See£xtemally Driven Crystal Oscillator Application Note. For ACcoupiing, use an input duty cycle near 50%.
10-68
TTL 0.4V to 2.4V
CMOS, 0.1 VDD to
0.9VDD
Min.
Max.
Unit
1
40
16
25
1000
MHz
ns
ns
10 (100
MHz)
11.1 (90
MHz)
45%
2560
(391 kHz)
2560
(391 kHz)
55%
ns
40%
60%
45%
55%
40%
60%
3
6
ns
ICD20S3B
Switching Waveforms (continued)
Serial Programming Timing
SCLK
-+________________________
CLKOUT __________________
-ee the
timeout interval spec in Switching Characteristics.)
When a new frequency is being set for MCLK, or if the active
VCLK register is being programmed, then a glitch-free
multiplexing to the Reference Frequency is performed. Once the
STOP bit is sent after the MCLK or active VCLK Programming
Word, the appropriate output signal will be multiplexed to the
reference signal f(REF) for an extra timeout interval (See
Switching Characteristics for further details).
Control Register Definition
The Control Register (CNTL Reg) allows the user to adjust
various internal options. Most of these options are for special
cases, and should have no applicability to standard graphics
usage. The register word is defined in Figure 1.
MUXREF-This control bit determines which clock is multiplexed to the VCLKOUT output during frequency changes.
While the VCLK VCO changes to a different frequency, a known
clock is multiplexed to the output. The default is to multiplex the
f(REF) reference frequency, but some graphics controllers cannot
run as slow as f(REF). This bit, when set, allows the MCLK to be
used as an alternative frequency.
Timeout Interval-The timeout interval is normally defined as in
the Switching Characteristics. It is derived from the MCLK VCO,
and if this VCO is programmed to certain extremes, then the
timeout may be too short. If this control bit is set, then the
timeout interval is doubled.
RAMDAC Reset-This control bit, when set, will cause the
ICD2062B to issue a RAMDAC reset sequence, which .is
C5
C4
C3
C2
required by some specific RAMDACs (such as the Bt457/458).
For more specifics on this operation, refer to the section Internal
RESET Sequence. NOTE: This operation will only take place
.
the first time this bit is set.
Duty Cycle Adjust-This control bit causes a 1 ns decrease in the
output waveform high time. The default is no adjustment. In
situations in which the capacitive load is beyond device
specifications, or where the threshold voltage VTIl is to be
changed from CMOS to TTL levels, this adjustment can
sometimes bring the output closer to 50% duty cycle.
VCLKOUT Pad-This control bit determines whether the
VCLKOUT Pad is at ECL or TTL levels. The default is ECL
levels.
When in TTL mode, the VCLKOUT Pad is
nonfunctional, and remains three-stated.
P Counter Prescale (REGO, REG 1, REG2)-These control bits
determine whether or not to prescale the P Counter value, which
allows fine tuning the output frequency of the respective register.
Prescaling is explained in more detail later in this dataSheet.
Divide Register Definition
The· output signals LDA, LDN2, LDN4, and LDC are all a
function of the VCLK VCO value divided by the division factor
stored in the Divide Register (DIVREG). The maximum WA
and WC output is 100 MHz.
Thble 4. DIVREG Division Factors
D2 D1 DO Division Clock LOW ClockIDGH Device
(cycles)
Factor
(cycles)
Version
1
A&B
0 X
1/2
1/2
+1
1
1 X
1
1
A&B
+2
0
0
0
1
2
B
+3
BI']
2
0
0
1
2
+4
0
0
1
1
0
1
+5
2
3
+8
4
4
B
B
Note:
3. Default on power-up.
C1
CO
PS2 PS1 PSO
1010101011111010101
I
Reserved (Must be set to 0)
MUXREF
0: Multiplex f(REFWO VCLKOUT---Default
1: Multiplex MCL OUT to VCLKOUT
Timeout Interval
0: Normal Timeout Interval---Default
1: Twice Normal Timeout Interval
RAMDAC Reset
0: No Reset Command---Default
1: Reset RAMDAC
Duty Cycle Adjust
0: 1 ns hig h-time decrease
1: No adju st---Default
VCLKOUT Pad
0: TTL Output Levels
1: ECL Output Levels-Default
J
P Counter Prescale (RegO)
0: Prescale=2---Default
1: Prescale=4
P Counter Prescale (Reg1)
0: Prescale=2---Default
1: Prescale=4
P Counter Prescale (Reg2)
0: Prescale=2---Default
1: Prescale=4
ICD20628-3
Figure 1. Control Register Dermition
10-88
~YPRESS
ICD2062B
Stop
Bit #
2
3
4
5
6
7
8
9
10 11
12 13
14 15 16 17 18 19 20 21
22 23 24 Bit #
VeOProg. 0'00'1 0'2 0'3 0'4 0'5 0'6 MO M1 M2 P'O P'1 P'2 P'3 P'4 P'5 P'6 10 11 12 13 AO A1
Word
CNTlReg 0 0 0 0 0 0 0 0 0 0 0 o PSO PS1 PS2 CO C1 C2 C3 C4 C5 0
DIVREG
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DO D1 D2
CNTlReg
DIVREG
0
IC020628-6
Figure 4. SeriafData Timing
The Set-Up and Hold Time requirements must be met on
both CLK edges.
4. The unlock sequence, start, and stop bits are not Manchesterencoded.
For specifics on timing, see the "Serial Programming Timing"
section in the switching waveforms..
The bits are shifted in this order: a start bit, 21 data bits, 3
address bits (which designate the desired register), and a stop bit
(which also functions as a load strobe to transfer the data from
the Serial Reg into the desired register). For the VCO registers
(REGO, REG1, REG2, MREG), the data is made up of 4fields:
D[20:17) = Index; D[16:1O)=P'; D[9:7)=Mux; D[6:0)=Q'. (See
the Programming the ICD2062B section for more details on the
VCO data word.) For the other registers with fewer than 21 bits
(DIVREG, CNTL Reg), the upper bits are used (starting with
the MSB). A total of 24 bits must always be loaded into the Serial
Data register (or an error is issued). Undefined bits should
always be set to zero to maintain software compatibility with
future enhancements.
Following the entry of the last data bit, a stop bit or Load
command is issued by bringing DATA HIGH and toggling CLK
HIGH-to-LOW and LOW-to-HIGH. The unlocking mechanism
then automatically rearms itself following the load. Only when
the watchdog timer has timed out are the SO and S1 selection pins
permitted to return to their normal register select function.
Note that the Serial Data register that receives the address and
data bits is exactly the correct length to accept the data being
sent. The stop bit is used as a load command that passes the
Serial Data Reg contents on to the register file location indicated
by the address bits. If a stop bit is not received after the Serial
Data register has been filled, but rather more valid encoded data
is received, then all of the received serial data is ignored, the
unlocking mechanism rearmed, and an error is issued. The device
counts the serial data clock edges to know exactly when the serial
buffer is full, and thus to know which bit is the stop bit. Following
the stop bit, the unlocking mechanism rearms itself. If corrupt
data is detected (i.e., incorrectly Manchester-encoded data), then
the unlocking mechanism is rearmed, the serial counter reset, all
received data ignored, and ERROUT is asserted.
ERROU'f Operation
0 veo Prog.
3.
:fA
D
DFF1
0
ERIIDDi
D
ClK
ata
ICD20626-7
Figure S. Modified Manchester Decoder Circuit
Figure 5 shows the basic mechanism used to detect erroneous
serial data. Note that the circuit must have different values on the
rising and falling edge when sampling the falling edge first. Valid
data is read on the rising edge of CLK.
The ERROUT signal is invoked for any of the following error
conditions: incorrect start bit, incorrect Manchester encoding;
incorrect length of data word; incorrect stop bit.
Note that if there is no input pin available on the target VGA
controller chip to monitor ERROUT, a software routine which
counts VSYNC pulses in order to measure output frequency may
be used as a determination of programming success.
Programming the ICD2062B
The desired output frequency is defined via a serial interface,
with a 21-bit number shifted in. The ICD2062B has two
programmable oscillators, requiring a 21-bit programming word
(W) to be loaded into each channel's respective registers
independently. This word contains 4 fields, as shown in Table 6.
The ERROUT signal is used to announce when a program error
has been detected internally by the ICD2062B. The signal
remains LOW until the next unlock sequence.
10-90
Table 6. Programming Word Bit Fields
Field
Index (I)
#of
bits
Notes
4
MSB (Most Significant Bits)
P Counter value (P')
7
Mux(M)
3
Q Counter value (Q')
7
LSB (Least Significant Bits)
~YPRESS
ICD2062B
Thble 10. P&Q Value Pairs
P
Q
f(ycO)
69
25
79.0363
460
80
29
78.9969
40
91
33
78.9669
419
(MHz)
Error (PPM)
Choose (P, 0)=(80,29) for best accuracy (40 PPM).
Therefore:
P'=P-3=80-3=77=1001101 (4dH)
0'=0-2=29-2=27=0011011 (lbH)
and the full programming word, W is obatined by concatenating:
1=0010, P'=1001101, M=ool, 0'=0011011
=001010011010010011011 (05349bH)
The programming word W is then sent as a serial bit stream, LSB
first. Appropriate start and stop bits must also be included as
defined in the Serial Programming Architecture section.
Programming Example-Prescaling=4
Assume the desired VCLKOUT frequency is 100 MHz. Table
Table 10 compares the results of using the default prescaling
value of 2 and the optional prescaling value of 4.
Thbie 11. Prescale Values
Prescale
Actual Frequency
(MHz)
P
2
99.84028
129
37
1600
4
99.99998
110
63
0
Q
Error
(PPM)
But this precision has its price, namely that the user now has to
set and reset the Prescale Bits PSO-2 (corresponding to
REGO-2), which involves loading a Control Word (taking care
to preserve the current values of the other Control Bits), before
the VCO Program Word can be loaded. Once the appropriate
Prescale Bits are set, then frequency programming can proceed as
before, unless and until it is desired to program a new frequency
without prescaling, at wbich point a new Control Word must first
be loaded with the proper bits set, and observing the precautions
noted above.
Th summarize, the sequence is:
1. Set the Prescale bits (load a Control Word)
2. Program the VCO (load'a Program Word)
Note that care must be taken not to change the Prescale Bit of
the currently active register: The results will be unpredictable at
best, and it could cause the VCO to go out of lock.
RAMDAC/VRAM Interface
Interfacing to the RAMDAC
Figure 6 shows how to interface the ICD2062B to a RAMDAC.
The part should be located as close to the RAMDAC as possible.
Thrmination resistors are needed on the VCLKOUT outputs, and
should be located as close as possible to the RAMDAC. For
specific information, please refer to the Cypress/IC Designs
application note EeL Outputs.
The ICD2062B may drive the CLOCK inputs of up to four
RAMDACs, if they are located physically adjacent to each other.
In this case, only 2 sets of termination resistors should be used,
and these should be located closest to the farthest RAMDAC
from the ICD2062B.
1Jpical ICD2062B Usage
The DIVREG register holds the divisor, which can be 1, 2, 3, 4,
5, or 8, by which the pixel clock is divided to generate the load
signals: LDA, LDN2, and LDN4.
The ENABLE input is synchronized internally to WA; it may be
used to start and stop the WC output synchronously. When
ENABLE is Law, LDC is held Ww. When ENABLE is
HIGH, then LDC will be free-running and in phase with WA.
This allows the video DRAM shift registers to be non-clocked
during the retrace intervals. Note that for fanouts greater than 4,
LDC needs to be buffered.
+5V
2200
VCLKOUT
ICD2062B
CLOCK
3300
+5V
RAMDAC
-'-
-
2200
CLOCK
VCLKOUT
14.31818 MHz -l,..
9
3300
XTALIN
-==
XTALOUT LDA
ill
ICD2062B-8
Fignre 6. ICD2062B to RAMDAC Interface Example
10-92
~YPRESS
ICD2062B
CLOCK
(free-running)
LOA/4
INTERNAL
RESET
1111111111111111111111
VCLKOUT
VCLKOOf
ICD2062B·11
Figure 9. Internal RESET TIming
Power Management Issues
Estimating Total Current Drain
Actual current drain is a function of frequency and of circuit
loading. The operating current of a given Oqtput is given by the
equation: I=C· V· f, where
I=current,
C=load capacitance (max. 25 pF),
V =output voltage (usually SV for 'ITL pads, 1.5V for EeL pads),
f=output frequency (in MHz).
'Ib calculate total operating current, sum the following:
MCLKOUT ~ C· V· f(MCLKOU1)
VCLKOUT ~ C· V • f(VCLKOUn; (ECL pad, V = 1.5V)
VCU
Valid Data Sequence (24 bits)
Stop:
Bit
ClK
DATA
IC020628-16
10-98
ICD2063
Programmable Graphics
Clock Generator
Features
• Second generation dual PLL graphics
clock generator
• Compatible with the ICD2061A
• 2 independent clock outputs:
- VCLK Output390 kHz - 135 MHz
(100 MHz at 3.3V)
- MCLK Output
3U kHz - 100 MHz
(80 MHz at 3.3V)
• Individually programmable PLLs
using a highly reliable, Manchesterencoded, 21-bit serial data word
• 2-pin serial programming interface
allows direct connection to most
graphics chip sets with no external
hardware required
• 2 advanced power-down capabilities
• Three-state oscillator control disables
outputs for test purposes
• Phase-locked loop oscillator input
derived from single 14.318 MHz
crystal
• 3.3Vand 5V operation
• Low-power, high-speed CMOS
technology
• Available in 16-pin SOIC package
configuration
Functional Description
The ICD2063 Dual Programmable
Graphics Clock Generator features a fully
programmable set of clock oscillators
which can handle all frequency requirements of most graphics systems. The
ICD2063 offers the selection ease of
ROM-based clock chips and the versatility of serially programmable frequency
synthesizers. It features both 3.3V and SV
operation with advanced power-down
capabilities, making it ideally suited for
the portable computer market.
The ICD2063 Dual Programmable
Graphics Clock Generator offers two fully
user-programmable phase-locked loops in
a single package. The outputs may be
changed "on the fly" to any desired
frequency value between limits which
depend on selected modes and operating
voltage. The ICD2063 is ideally suited for
any design where multiple or varying
frequencies are required, replacing more
expensive metal can oscillators or less
functional ROM-based clock synthesizers.
While primarily designed for the graphics
subsystem market, the programming versatility of the ICD2063 makes it ideal
wherever two variable, yet highly accurate
clock sources are required.
ICD2063 Changes from the
ICD2061A
The ICD2063 revision of the ICD2061A
is a complete mask redesign which
includes many feature enhancements.
The following major modifications have
been implemented:
• 3.3V Operation-The ICD2063
supports 3.3V operation in addition to
SV operation.
• Expanded Register Set-There are
now 4 Video registers and 2 Memory
registers. This allows better support
for Windows NT drivers.
• Expanded VCO Range-The upper
frequency limit has been increased to
13SMHz.
Pin Configuration
SOIC
Top View
PWlfDWIIJ
SO/CLK
rnTClR
Sl/DATA
AVOD
SELMJRESET
OE
GND
Von
INIT
FEATCLK
ERROIJ1'IXBUF
VCLKOUT
XTAUN
XTALOUT
MCLKOUT
IC02063-1
10-100
• No Index Field Required-The Serial
Word now treats the Index Field
(Mode Field) as a "Don't Care" bit
region, for complete software
compatibility with the ICD2061A.
• ButTered Crystal Output (Optional)XBUF Output may be specified,
replacing the ERROUT signal.
• Smooth Frequency Transition-The
two phase-locked loops now transition
smoothly from one frequency to
another.
• No MUXREF Required-The
necessity for the MUXREF procedure
has been eliminated by the smooth
frequency transition. For compatibility
with the ICD2061A, there is an option
which multiplexes a known output
during frequency transitions. New to
the ICD2063 is that the VCLK VCO is
multiplexed to the MCLK output. See
the MUXREF Option section for
details.
• Very High Frequency
Resolution-The MCLK
Phase-Locked Loop Output can be
multiplexed to the VCLK PLL
Reference Input, thus enabling very
high frequency resolution, at the
expense of slightly higher jitter. See the
Extended VCLK Frequency Precision
section.
• Reduced Register Initialization
ROM-The former INIT2 pin now
selects between the 2 memory registers
MREGO and MREGI.
• Hardware Reset (Optional)-A
hardware reset is available as an
option, replacing the memory selection
signa\.
ICD2063
Pin Summary
Name
Number
SO/CLK
1
Sl/DATA
2
AVDO
OE
GND
XTALIN[lj
3
4
5
6
XTALOUTLlj
7
Description
Bit 0 (LSB) of frequency select logic, used to select PLL frequencies. Clock Input in serial
programming mode. (Internal pull-down allows no-connect.)
Bit 1 (MSB) of frequency select logic, used to select PLL frequencies. Data Input in serial
programming mode. (Internal pull-down allows no-connect.)
+5Vor 3.3V to Analog Core
Output Enable. Three-states output when pulled LOW. (Internal pull-up allows no connect.)
Ground
Reference Oscillator input for all phase-locked loops (nominally from a parallel-resonant 14.31818
MHz crystal). Optionally PC System Bus Clock.
Oscillator Output to a reference crystal. (Pin is no-connect if external reference oscillator or PC
System Bus clock signal is used.)
Memory Clock output
MCLKOUT
8
VCLKOUT
9
ERROUT/
XBUF
FEATCLK
10
INIT
12
VOD
SELM/RESET
14
Selectable via configuration option:
SELM-Selects 1 of 2 Memory Clock Output (MCLKOUT) frequencies (see Register Selection
subsection MCLKOUT)
RESET-Hardware RESET control signal (see the Power-On Reset, RESET, and Register Initialization
section)
•
INTCLK
15
PWRDWN
16
Selects the Feature Clock external clock input as VCLkOUT output (Internal pull-up allows
no-connect.) (See Table 3.)
Power-down pin (active LOW) (Internal pull-up allows no-connect if power-down operation not
required. See Power Management Issues for specific details concerning the use of this pin.)
11
13
Video Clock output
Error Output: a LOW signals an error during serial programming OR
Buffered Crystal Reference Output (selectable via configuration option)
External clock input (Feature Clock) (Internal pull-up allows no-connect.)
Selects state of initialization ROM during power-uK' See Table 2. (This pin has no internal pull-up or
pull-down; it must be tied HIGH or LOW externa ly.)
+5V or 3.3V to I/O Ring
Register Definitions
Register File
The Register File consists of the following registers and their
respective addresses in the Serial Data register:
Thble 1. Register Addressing[2]
A2
0
0
0
Al
AO
0
0
1
0
1
0
Register
25.175 MHz
28.322 MHz
VREGO
1
1
0
MREGO
PWRDWN
Divisor for Power-Down mode
Usage
Fixed Video Clock Frequency
Fixed Video Clock Frequency
Programmable Video Clock Register 0
Programmable Memory Clock Register 0
0
1
0
1
1
0
1
1
VREGI
Programmable Video Clock Register 1
0
CNTL
1
1
1
MREGl
Control Register
Programmable Memory Clock Register 1
Noles:
1. For best accuracy, use a parallel-resonant crystal, assume CLOAD= 17 pF.
2. All register values are preserved in power-down mode.
10-102
ICD2063
QPRESS
C5
C4
C3
C2
101010101
1
C1
1
CO
PV1
PVO PM1 PMO
10101010101
L
Power-DownMode
0: Power-Down Mode 1-Default
(MCLKO UT= PWRDWN Divisor)
1: Power-Down Mode 2
(XtalOs c shutdown)
MUXREF
0: Multiplex f(RE~O VCLKOUT-Oefault
1: Multiplex MCL OUT to VCLKOUT
P Counter Prescale (MREGO)
0: Prescale=2-Default
1: Prescale=4
' - - - P Counter Prescale (MREG1)
0: Prescale=2-Default
1: Prescale=4
P Counter Prescale (VREGO)
0: Prescale=2-0efault
1: Prescale=4
Timeout Interval
0: Normal Timeout Interval-Default
1: Twice Normal Timeout Interval
P Counter Prescale (VREG1)
0: Prescale=.2-Default
1: Prescale=4
0)
Reserved (Must be set to
Split SupplyMode
0: AVoo = 3.3V; Voo = 5V
1: Both su pplies at same voltage-Default
ICD2063-3
VCLK Reference
0: f(REF)-Oefault
1: MCLKOUT
Fignre 1. Control Register Definition
Control Register Definition
The Control Register (CNTL) allows the user to adjust various
internal options. Most of these options are for special cases, and
should have no applicability to standard graphics usage. The
register word is defined in Figure 1.
VCLK Reference--This control bit determines whether the
VCLK VCO uses f(REF) or the MCLK output as a reference.
Refer to the Extended VCLK Frequency Precision section for
more details.
Split Supply Mode--This control bit allows mixing 3.3V (AVoo)
and SV (Voo) supplies. The default is for both to be the same
(SV or 3.3V) .. The alternative is AVoo = 3.3\1, Voo = SY. See
the 3.3 M:>lt and 5 Volt Issues section for more details. The
purpose is to maintain duty cycle 50%.
Timeout Interval-The timeout interval is normally defmed as in
the Switching Characteristics. It is derived from the MCLK VCO,
and if this VCO is programmed to certain extremes, then the
timeout may be too short. If this control bit is set, then the
timeout interval is doubled.
MUXREF (MUXREF Mode only)-This control bit determines
which clock is multiplexed to the VCL1{Otrf output during
frequency changes. While the VCLK VCO changes to a different
frequency, a known clock is multiplexed to the output. The
default is to multiplex the f(REF) reference frequency, but some
graphic controllers cannot run as slow as f(REF). This bit, when
set, allows the MCLK to be used as an alternative frequency.
Power-Down Mode--This control bit determines which PowerDown Mode the PWRDWN pin will implement. The default
(Power-Down Mode 1) forces the MCLKOtrf signal to be a
function of the PWRDWN register. Power-Down Mode 2 turns
off the crystal oscillator and disables all outputs. There is a more
detailed description in the section entitled Power Management
Issues.
P Counter Prescale (VREGO, VREG1, MREGO, MREG1)These control bits determine whether or not to prescale the P
Counter value, which allows fine tuning the Qutput frequency of
the respective register. Prescaling is explained in more detail in
the Prescaling section.
Serial Programming Architecture
The ICD2063 programming scheme is simple, yet impenetrable
to accidental access. Because the only common denominator
between most VGA and 8514 controllers is a few clock select
pins, these have to perform the dual functions of clock selection
and serial programming. The Serial Program Block (See
ICD2063 Logic Block Diagram) contains several components: a
Serial Unlock Decoder (containing the unlocking mechanism and
Manchester decoder), a watchdog timer, the Serial Data register
and a Demultiplexer to the Register File (see Figure 2).
Unlocking Mechanism
The Unlocking Mechanism watches for an initial break sequence,
detailed in Figure 3.
The initial unlock sequence consists of at least five LOW-toHIGH transitions of CLK with DATA HIGH, followed
immediately by a single LOW-to-HIGH transition of CLK with
DATA Law. Following this unlock sequence, the encoded serial
data is clocked into the Serial Data register.
Note that the ICD2063 may not be serially programmed when in
Power-Down Mode.
Watchdog Timer
Following any transition of CLK or DATA, the watchdog timer is
reset and begins counting. Throughout the entire programming
process, the watchdog timer ensures that there is a transition on
CLK or DATA within the timeout specification (of 2 msec-see
Switching Characteristics.) If a timeout does occur, the lock
mechanism is rearmed and the current data in the Serial Data
register is ignored.
Since the VCLK registers are selected by the SO or SI bits, and
since any change in their state may affect the resultant output
frequency, new data input on the Selection Bits is only permitted
10-104
ICD2063
c;rcYPRESS
issued). Undefined bits should always be set to zero to maintain
softwa~e compatibility with future enhancements.
Following the entry of the last data bit, a stop bit or Load
command is issued by bringing data HIGH and toggling CLK
HIGH-to-LOW and LOW-to-HIGH. The unlocking mechanism
then automatically rearms itself following the load. Only when
the watchdog timer has timed out are the SO and S1 selection pins
permitted to return to their normal register select function.
Note that the Serial Data register that receives the address and
data bits is exactly the correct length to accept the data being
sent. The stop bit is used as a load command that passes the
Serial Data register contents on to the register file location
indicated by the address bits. If a stop bit is not received after the
Serial Data register has been filled, but rather more valid
encoded data is received, then all of the received serial data is
ignored, the unlocking mechanism rearmed, and an error is
issued. The device counts the serial data clock edges to know
exactly when the serial buffer is full, and thus to know which bit is
the stop bit. Following the stop bit, the unlocking mechanism
rearms itself. If corrupt data is detected (i.e., incorrectly
Manchester-encoded data), then the unlocking mechanism is
rearmed, the serial counter reset, all received data ignored, and
ERROUT is asserted.
ERJRj'(Jf Operation
The ERROUT signal is used to report when a program error has
been detected internally by the ICD2063. The signal stays active
until the next unlock sequence.
Figure 5 shows the basic mechanism used to detect valid and
erroneous serial data. Note that the circuit must have different
values on the rising and falling edge when sampling the falling
edge first. Valid data is read on the rising edge of CLK.
The ERROUT signal is invoked for any of the following error
conditions: incorrect start bit, incorrect Manchester encoding;
incorrect length of data word; incorrect stop bit; timeout.
Note that if there is no inllUt pin available on the target VGA
controller chip to monitor ERROUT, a software routine which
counts VSYNC pulses in order to measure output frequency may
be used ·as a determination of programming accuracy.
Note also that the ERROUT signal is an order option. If the
XBUF option is chosen instead, then ERROUT is not available,
and the user may want to implement the above technique to
verify that the desired programming did indeed take place.
.0-----10
OFF3 ERRODi
o
Programming the ICD2063
The desired output frequency is defined via a serial interface,
with a 21-bit number shifted in. The ICD2063 has two
programmable oscillators, requiring a 21-bit programming word
(W) to be loaded into each channel's respective registers
independently. This word contains 4 fields:
Thble 6. Programming Word Bit Fields
#of
bits
4
Field
Mode (I)
P Counter value (1")
Post-VCO Divisor
(M)
Q Counter value (Q')
Notes
MSB (Most Significant Bits)
7
3
7
LSB (Least Significant Bits)
The frequency of the Programmable Oscillator f(veo) is
determined by these fields as follows:
P'=P-3
Q'=Q-2
f(veo) = (Prescale x f(REF) x P/Q)
where f(REF) = Reference frequency (between 1 MHz-60 MHz;
typically 14.31818 MHz) and Prescale=2 or 4 (default is 2,
defined by CNTL Reg).
Note that if a reference frequency other than 14.31818 MHz is
used, then the initially loaded ROM frequencies will .not be
correct.
Table 7 lists the various limits for f(veo).
Table 7. veo Frequency Ranges
VCLKPLL
MCLKPLL
5 Volt Operation
3.3 Volt Operation
50 MHz - 135 MHz
40 MHz - 100 MHz
50 MHz - 100 MHz
40 MHz - 80 MHz
For lower output frequencies, f(Veo) must be brought into range.
10 accomplish this, a post-VCO diVIsor is selected by setting the
values of the Post-VCO Divider fidd (M). See Table 8.
Thble 8. post-Veo Divider (M)
M
Divisor
000
001
1
2
010
4
011
8
100
16
101
110
32
64
111
128
elK
IC02063-7
Figure S. Serial Data Timing
The Mode Field (I), formerly the Index Field, is included for
historical reasons to preserve software compatibility with the
ICD2061A. In the ICD2063, it is only used for a few special
circumstances, as detailed in the following paragraphs.
10-106
~YPRESS
ICD2063
Thble 12. Effects of Prescaling
Prescale
Desired
Actual
Freq. (MHz) Freq. (MHz)
P
Q
Error
(PPM)
2
100
99.84028
129
37
1600
4
100
99.99998
110
63
0
But this precision has its price, namely that the user now has to
set and reset the Prescale Bits PSO-2 (corresponding to
REGO-2); which involves loading a Control Word (taking care
to preserve the current values of the other Control Bits), before
the VCO Program Word can be loaded. Once the appropriate
Prescale Bits are set, then frequency programming can proceed as
before. However, if it is desired to program a new frequency
without prescaling, a new Control Word must first be loaded with
the proper bits set, with the precautions noted above.
Th summarize, the sequence is:
1. Set the Prescale bits (load a Control Word)
2. Program the VCO (load a Program Word)
Note that care must be taken not to change the Prescale Bit of
the currently active register: The results will be unpredictable at
best, and it could cause the VCO to go out of lock.
Extended VCLK Frequency Precision
An optional mode set in the CNTL register allows the VCLK
PLL to use the MCLK PLL as its reference frequency instead of
f(REF). The advantage is that, by proper tuning of the input
reference, very fine frequency control is possible on the output of
VCLK.
Just about any desired value can be achieved with worst-case
precision ofless than 5 ppm.
The reference frequency oscillator is used to drive the MCLK
PLL, which is then fed internally to the VCLK PLL to generate
the desired signal. However, please note the following:
• No usable MCLK output-This method essentially uses two
PLLs to derive a single output, so that the MCLK output will
probable be meaningless. Therefore, this method is probably
not suited to normal VGA graphics applications.
• Some increased jitter-The trade-off associated with deriving
the VCLK PLL reference from another PLL is that the
MCLK + VCLK combination will tend to exhibit more jitter
than a single PLL with a crystal-controlled reference-but the
jitter should stay below 1 ns.
• More challenging programming model-Another trade-off of
having 21 bits each to define both the reference frequency and
the output is that it makes finding the optimum 2
programming words an iterative process. Th aid in these
calculations, Cypress/lC Designs strongly recommends using
BitCalc, a utility designed to help in this analysis.
Power Management Issues
Power-Down Mode 1
The ICD2063 contains a mechanism to reduce the quiescent power
when stand-bY operation is desired. In Power-Down Mode 1
(invoked bY pulling the PWRDWN signal WW and having the
proper CN1L register bit set to zero), both VCOS are shut down,
the VCLKOUT output is forced Ww, and the MCLKOUT output
is set to a user-defined low-frequency value to refresh dynamic
RAM.
The power-down MCLKOUT value is determined by the
following equation:
MCLKOUTPower-Down=f(REF)+ (PWRDWN Reg Divisor Value)
The Power-Down register divisor is determined according to the
following 4-bit word programmed into the PWRDWN register.
(See Table Table 11.)
Thble 13. PWRDWN Register Programming
PWRDWNbits
P3
P2
PI
PO
PWRDWN
Register Value (Hex)
0
0
0
0
0
N/A
0
0
0
1
1
32
447.4 kHz
0
0
1
0
2
30
477.3 kHz
0
0
1
1
3
28
511.4 kHz
0
1
0
0
4
26
550.7 kHz
0
1
0
1
5
24
596.6 kHz
0
1
1
0
6
22
650.8 kHz
0
1
1
1
7
20
715.9 kHz
1
0
0
0
8
18 (default)
795.5 kHz
1
1
0
1
9
16
894.9 kHz
0
0
1
0
A
14
1.023 MHz
1
0
1
1
B
12
1.193 MHz
1
1
0
0
C
10
1.432 MHz
1
1
0
1
D
8
1.790 MHz
1
1
1
0
E
6
2.386 MHz
1
1
1
1
F
4
3.580 MHz
Powe....Down Divisor
10-108
MCLKOUTPower_Down
(f(REF) = 14.31818 MHz)
N/A
ICD2063
Table 15. Driving other Devices with the ICD2063
fOUT
vco
B---fEJ
SettieTime
Device
Status
freq2
5V
5V
OK
3.3V
5V
OK if driving TTL inputs; if driving CMOS inputs, then ICD2063
output will appear to have a low
duty cycle.
5V
3.3V
3.3V
3.3V
Potentiallatch-ufl problems with
other devices; wi I work if other
device's input will accept
VIH=VOO+ 2Y.
OK
freql
L---r---------~~--------~ time
1C02003-9
Table Hi. Driving the ICD2063 with Other Devices
~
Device
Status
5V
5V
OK
3.3V
5V
OK
5V
3.3V
3.3V
3.3V
Figure 7. Frequency 1i:ansltionSmooth Mode: Normal Operation
fOUT
VCO
Settle lime
ftarget
TTL outputs only; input to
ICD2063 must not exceed
VOo+O.3V
OK
-
-t -
-
-
-
-
:~
-
-
-
,
,
-I -
-
-
,
-'-,
Upon changing VCLK or MCLK, either by reprogramming the
active register or by selecting a new register, the output will
transition in one of two basic ways, depending on the post-divide
values (Post-divide is used to divide down the VCO output to
frequencies below t\1e normal VCO operating range):
• Normal Operation-If the post-divide value (M) is the same
for both frequencies (original and target), then the output will
transition smoothly and linearly from the original to the target
frequency, with no oversboot (see Figure 7).
• Post-Divide Operatiol1-If the post-divide value (M) differs
between the original and target frequencies, then the output
behaves somewhat differently, but will never exceed the
greater of the original and target frequencies.
1. If the post-divide value decreases then, first, a smooth
transition occurs to an intermediate frequency (equal to
target frequency + post divider value); second, the
post-divide is changed to the new value, resulting in an
instantaneous transition to the target frequency (see
Figure 8).
- --
- ~ - - - - - - -~--;-----~I - :- - - -
flntermedlate
The ICD2063 may be configured for one of two frequency
transition options: the Smooth 1tansition Option or the
MUXREF Option (for compatibility with the ICD2061A).
Smooth 1i:ansltion Option
-
ttimeout - - . .
foriginal
Frequency Transition Options
-
ftarget/postdivide value
L..-i-,------------------....
~tvco~:
'!'
time
1C02063-10
glitch-free
Figure 8. Frequency 1i:ansltlonPost-Divide Value Decreases
fOUT
, vco
aenleTlme
foriginal
'target
----
--------.-.---,
f'ntennediate
-----------------
ftarget!postdivide value
2. If the post-divide value increases then, first, the post-divide
value is changed to the new value, resulting in an
instantaneous transition to an intermediate frequency
(equal to the target frequellCY + post divider value); second
there is a smooth transition from this frequency to the
target frequency (see Figure 9).
10-110
L-____;-,--------_----------. time
,- I v c o -'
Figure 9. Frequency 1i:ansltionPost-Divide Value Increases
1C02063-11
.~YPRESS
ICD2063
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Junction temperature ............................. 125°C
Operating Range
Supply Voltage to Ground Potential ......... -0.5V to + 7.0V
DC Input Voltage ................... -0.5V to VDD +0.5V
Storage Temperature ................... -65°C to +150°C
Max soldering temperature (10 sec) ................. 260°C
Ambient
Thmperature
O°C S TAMBIENT S 70°C
VDD& AVDD
5V:!:5%
3.3V ± 10%
Electrical Characteristics Over the Operating Rangd4]
Parameter
Description
Thst Conditions
Min.
VDD&
AVOD
Supply Voltage Relative to GND[S]
390 kHz - 100 MHz
390 kHz - 120 MHz
390 kHz - 135 MHz
VCLK specs shown
(MCLKlowend = 312kHz)
3.0
4.5
4.75
VOH
Output HIGH Voltage
IOH = -4.0mA
VOL
Output LOW Voltage
IOL= 4.0 rnA
VIH
Input HIGH Voltage
Except on Crystal Pins
VIL
Input LOW Voltage
Except on Crystal Pins
IIH
Input HIGH Current
VIH = VDD-O.5
IlL
Input LOW Current
VIL= +0.5V
typ.
Max.
Unit
V
Ioz
Output Leakage Current
(Three-state)
100
Power Supply Current
5V/3.3Y,
Inputs @ VDD or GND
IOD-TYP
Power Supply Current
5V/3.3V (60 MHz)
IADD
Analog Power Supply Current
IpOl
Power-Down Current (Mode 1)
5V/3.3V
IpDZ
Power-Down Current (Mode 2)
5V/3.3V
Notes:
4. Input capacitance is typically 10 pF, except for the crystal pins.
5. For transition between 3.3V and SV operation, refer to the3.3 Volt and
5 Volt Issues section.
10-112
3.6
5.5
5.5
VDD-0.5
V
0.4
V
2.0
VDD+O.3
V
-0.3
0.8
V
150
10
J.lA
J.lA
J.lA
65/44
rnA
80/50
rnA
10
rnA
6/4
7.5/5.0
rnA
25/20
50/35
J.lA
-250
15/10
35/24
~YPRESS
ICD2063
Switching Waveforms
Duty Cycle Timing
VDD
ICD2063-13
Rise and Fall Times
XTALIN
f(REF)
VCLKOUT
MCLKOUT
ICD2063-14
Three-State Timing
OE
VCLKOUT
MCLKOUT
THREE-STATE OUTPUT
ICD2063-15
Active MCLK and VCLK Register Programming Timing (MUXREF Mode)
I
Stop Bit
VCO Sellie Time
LJ
r--
(Internal
Timeout)
VCLKOUT
MCLKOUT
10-114
ttimeout---i
New Frequency
=z
~YPRESS
ICD2063
Switching Waveforms (continued)
Serial Programming Timing
Unlock Sequence
, Start '
Bit
,
ClK
DATA
ClK
DATA
Configuration Options
Option
Pin 10 Function
Choices
ERROUT or XBUF
-1
-2
-3
XBUF
ERROUT
ERROUT
Pin 14 Function
RESET or SELM
SELM
RESET
SELM
Frequency TIansition
Smooth or MUXREF
Smooth
MUXREF
Smooth
Ordering Information[lO]
Ordering Code
lCD2063
Package
Name
S1
Operating
Range
Package'JYpe
Commercial[ll]
16-PinSOIC
Notes:
10. Please call your local Cypress representative.
11. O·C to +70·C
Example: order lCD2063SC-1 for the ICD2063, 16-pin plastic
SOlC, commercial temperature range device with the initial
frequencies shown in Table 3.
Document #: 38-00405
Windows is a trademark of Microsoft Corporation.
10-116
Chip Options
-1, -2,-3
ICD2093
Q-YPRESS
sOle
Pin Configuration
1bpVlew
XTALOUT
XTALIN
52
50
SHUTDOWN
GND
5Y5BU5_A
5Y5BU5_B
GND
CPUA
CPUB
CPUC
CPUD
51
AVoo
16MHz
5Y5CLK
CPUH
Voo
CPUG
CPUF
CPUE
GND
'Vo o
IC02093-2
Pin Summary
Name
Number
Description
XTALOUT[lJ
1
Oscillator output to a 14.318 MHz parallel-resonant crystal
SO
2
CPU Clock ROM Select Line-Bit 0 (LSB)
SHUTDOWN 3
(OE)
When pulled LOW, shuts down oscillator, PLL, and all dynamic logic. Can be made three-state Output
Enable via configuration option. Internal pull-up allows for no-connect if shutdown operation is not
needed.
GND
4
Ground
SYSBUS_A
5
14.31818 MHz Output
SYSBUS_B
6
14.31~18
GND
7
Ground
CPUA
8
CPU Clock Output A (IX or 2X)[2J
CPUB
9
CPl1 Clock Output B (1X or 2X)[2J
CPUC
10
CPU Clock Output C (IX or 2X)[2]
CPUD
11
CPU Clock Output D (IX or 2X)[2]
Voo
12
+ 5V to I/O Ring
GND
13
Ground
CPUE
14
CPU Clock Output E (1X or 2X)[2]
CPUF
15
CPU Clock Output F (1X or 2X)12J
CPUG
16
CPU Clock Output G (1X or 2X)[2]
VOD
17
+5V to I/O Ring
CPUH
18
CPU Clock Output H (1X or 2X)[2J
SYSCLK
19
24 MHz or 32 MHz Output (factory configurable)
16 MHz
20
16 MHz Output
AVOD
21
+5V to Analog Core
S1
22
CPU Oock ROM Select Line-Bit 1
S2
23
CPU Clock ROM Select Line-Bit 2 (MSB)
XTALINLIJ
24
Oscillator input from a 14.31818 MHz crystal
MHz Output
Notes:
1. For best accuracy, use a parallel-resonant crystal, assume CLOAD = 17 pH
2. All the CPU outputs can be IX, 2X, or any mix of the two (the outputs
of each type are contiguous).
10-118
~YPRESS
ICD2093
Thrmination
The ICD2093 provides fast rise and fall times on its outputs to
drive large loads, which require the PCB designer to observe
proper transmission line techniques. There are three principal
techniques for proper termination. The optimum choice depends
on individual requirements.
J
I ..J~8~0~~_~--Z;;--1-....._
•
Zo
....~
Device
pin
Series Termination
PCB Trace
The main drawback of this technique is that CL adversely affects
rise and fall times (see Figure 1).
RT
ICL
RT=ZO
CL-Receiver
Capacitance
ICD2093 Driver
Parallel Termination
/
The main drawback of this technique is that it consumes power.
VT = VDD -;- 2 for minimum power. (Note that VT should not
equal receiver threshold. 1TL systems often set VT at 3V using
Thevenin equivalent circuit.) See example divider in Figure 2.
AC Termination
The main drawback of this technique is that it is not as good at
high frequencies (see Figure 3).
Power Calculation
Actual current drain is a function of frequency and circuit
loading. The operating current of a given output is given by the
RT=Zo-80
Device
RT
Zo
pin
PCB Trace
ICL
CL-Receiver
Capacitance
ICD2093 Driver
Figure 3. AC Thrmination
equation I = C • V • f, where I=current, C=load capacitance,
V=output voltage in Volts (usually 5V for rail-to-rail CMOS
pads) and f=output frequency in MHz.
To calculate total operating current, sum the following:
ISYSBUS A ~ C14. V • 14.318
ISYSBUS-B ~ C24. V .14.318
ICPUA - ~ CCLKA. V • fCLKA
ICPUB
~ Ccurn· V • fcurn
Icpuc
~ CCLKC· V • fCLKC
ICPUD
~ CCLKD· V • fCLKD
ICPUE
~ CCLKE· V • fCLKE
ICPUF
~ CCLKF· V • fCLKF
IcpUG
~ CCLKG. V • fCLKG
ICPUH
~ CCLKH. V • fCLKH
I(Internal) ~ .06 A (60 rnA)
This yields an approximation of the actual operating current. For
unconnected output pins, one can assume 5-10 pF loading,
depending on the package type.
Some typical values are displayed in Table 5.
Figure 1. Series Termination
Table 4. Operating Current 1YPical Values
Device
Zo
Capacitive Load
Current (in mA)
66.6 MHz
30pF
115
General Considerations
Power-Down Operation
pin
PCB Trace
Frequency
RT
RT=Zo
ICD2093 Driver
1:
SV
830
Example: SOO @ 3V
=
12S0
In the power-down state, the oscillator, PLL, and all dynamic
logic is shut down.
Note that, during shutdown, the internal PLLs are turned off.
Upon restarting, there will be a 5-msec interval during which the
VCOs stabilize. See Power-Down Timing in the Switching
Waveforms section for further timing information.
Three-State Output Operation
If the OE configuration is chosen, then the SHUTDOWN pin
becomes an OE pin, which, when pulled LOW, will three-state all
the clock output lines. This supports Wired-OR connections
between external clock lines, and allows for procedures such as
automated testing where the clock must be disabled. The OE
signal contains an internal pull-up; it can be left unconnected if
three-state operation is not required. The output pads contain
weak pull-down resistors.
Figure 2. Parallel Termination
10-120
ICD2093
Switching Characteristics[S]
Parameter
Name
Description
Min.
1YP.
Max.
Unit
f(REF)
Reference Frequency
Reference input normal value
14.318
MHz
t(REF)
Reference Clock
Period
1 + f(REF)
69.84
ns
tl
Input Duty Cycle
Duty cycle for the input oscillator dermed as
tl = tlA +t18
t2
Output Period
/
Duty cycle for the outI;lUts, measured @ CMOS
Vrn of VDD+ 2 (special screening required for
100 MHz) t3 = tlA + t18
.'
25%
50%
75%
10
100 MHz
100
10 MHz
40%
60%
ns
t3
Output Duty Cycle
4
Rise Times
Rise time of clock outputs (50-pF load @ 10 MHz)
3.5
ns
ts
Fall Times
Fall time of clock outputs (50-pF load @ 10 MHz)
4
ns
t6
Skew
Leading edge skew between 1X and 2X outputs
andCL=50pF
500
ps
ts
Skew
Leading edge skew between 1X and 1X or 2X and
2X outputs and CL =50 pF
250
ps
tveo
veo Settle Time
Time for VCO to transition smoothly and monotonically from the original to the new frequency
3
msec
tlO
Three-state Time
Time for the outputs to go into three-state mode
after OE signal goes LOW
20
ns
t11
Clock Enable Time
Time for the outputs to recover from three-state
mode after OE signal goes HIGH
20
ns
t12
SYSBUSSkew
Leading edge skew between SYSBUS outputs
500
ps
t13
SYSBUSSkew
nailing edge skew between SYSBUS outputs
500
ps
t14
Power-Down
Time to invoke power-down option
20
ns
tiS
Power-Up
Time to revoke power-down option
20
ns
Note:
5. Input capacitance is typically 10 pF, except for the crystal pads.
Switching Waveforms
Duty Cycle Timing
VOO/2
IC02093-3
10-122
~YPRESS
ICD2093
Switching Waveforms (continued)
Three-State Timing
OE
~_¥1.4V
~:10~t11
THREE-STATE OUTPUT
ALL
THREE-STATE
OUTPUTS
IC02093-7
SYSBUS Skew
___...J/
,,~---
IC02093-8
Power-Down Timing
POWER-DOWN OPTION
(SELECTED BY OE)
~
ALL OUTPUTS
1;
(forced LOW)
1002093-9
Test Circuit
DEVICE
UNDER
TEST
VDD
i
22Q
AVDD
2.2 flF
Tantalum
tb
:::r::
-
~
GND
10-124
CLKout
CLOAD
ICD2093
Configuration Options
Optio~
Option -1
Signad/Pln
CPUA
+2
+2
CPUB
+2
+2
CPUC
+2
+1
CPUD
+2
+1
CPUE
+2
+1
CPUF
+2
CPUG
+2
+1
";"1
-2
CPUH
+1
+1
Pin 3
OE
SHUTDOWN
24 MHz
24 MHz
SYSCLK
Ordering Information
Ordering Code
ICD2093
Package
Name
S13
ating
0r::nge
Package lYpe
24-PinSOIC
C=O'C to +70'C @ VDD=5V
&le: Order lCD2093SC-l for the ICD2093, 24~pin plastic
SOIC, commercial temperature range device which uses the
st&ndard configuration code -1 (SYSCLK=24 MHz, PowerDown not enabled, one +1 CPU clock &nd seven +2 CPU
clocks).
Clock Output Options
Standard Configuration -1
Custom configurations are also available. 1b order a custom
configuration, please contact your Cypress representative.
Document #: 38-00401
10-126
~YPRESS
ICD6233
Maximum Ratings
(Above whiCh the useful life may be impaired. For user guidelines,
not tested.)
Operating Range
Supply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC Input Voltage ................... -O.5V to VDD +0.5V
Storage Thmperature ................... -55°C to + 125°.C
Max soldering temperature (10 sec) ... : ............. 260°C
Junction Thmperature ........................... +125°C
Ambient
Thmperature
O°C S TAMBffiNT S 70°C
VDD
5V ± 10%
CL 25 pFmax.
Electrical Characteristics Over the Operating Range
Parameter
Description
Thst Conditions
= Max., Output <90 MHz CE = VDD
IOH = - 4.0rnA
IOL = 4.0 rnA
IDD
Supply Current
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VlH
Input HIGH Voltage
VIL
Input LOW Voltage
IlH
Input HIGH Current
VlH
IlL
Input LOW Current
VIL
Min.
VDD
Max.
Unit
55.0
rnA
0.4
V
2.4
V
2.0
V
0.8
V
100.0
-250.0
!lA
!lA
Min.
Max.
Unit
11.1
90 MHz
1066.7
937.5 kHz
ns
40
60
%
4
ns
= VDD-O.5V
= +O.5V
Switching Characteristics Over the Operating Rangel!]
Parameter
Description
Test Conditions
Output Period
5V Operation
Output Duty Cycle
Duty cycle for output pads, define as t! + t2
t3
Rise Time
Clock output rise tinIe
4
Fall Tinle
Clock output fall tinle
4
ns
t5
Power-Up
Time for output to become valid
15
msec
t6
Three-State
Time for output oscillator to enter three-state
mode after OE goes LOW
12
ns
t7
CLKValid
Time for output oscillator to enter three-state
mode after OE goes HIGH
12
ns
t!
Note:
1.
Input capacitance is typically lOpE
10-128
CY7B991
CY7B992
Programmable Skew
Clock Buffer (PSCB)
Features
• Output pair skew <100 ps typical
(2S0 max.)
• All outputs skew <2S0 ps typical
(SOO max.)
• 3.7S- to 80-MHz output operation
• User-selectable output functions
- Selectable skew to 18 ns
- Inverted and non-inverted
- Operation at 'h and \4 input
frequency
- Operation at 2x and 4x input
frequency (input as low as 3.7S
MHz)
• Zero input to output delay
• SO% duty-cycle outputs
• Outputs drive SOQ terminated lines
• Low operating current
• 32-pin PLCC/LCC package
• Jitter < 200 ps peak-to-peak
« 2SpsRMS)
• Compatible with a Pentium ~ -base4
processor
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer
user-selectable control over system clock
functions. These multiple-output clock
drivers provide the system integrator with
functions necessary to optimize the timing
of high-performance computer systems.
Eight individual drivers, arranged as four
pairs of user-controllable outputs, can
each drive terminated transmission lines
with impedances as low as 50Q while delivering minimal and specified output
skews and full-swing logic levels
(CY7B991 TTL or CY7B992 CMOS).
Each output can be hardwired to one of
nine delay or function configurations.
Delay increments of 0.7 to 1.5 ns are de-
Pentium is a trademark of Intel Corporation.
10-130
termined by the operating frequency with
outputs able to skew up to ±6 time units
from their nominal "zero" skew position.
The completely integrated PLL allows externalload and transmission line delay effects to be canceled. When this "zero
delay" capability of the PSCB is combined
with the selectable output skew functions,
the user can create output-to-output delays of up to ± 12 time units.
Divide-by-two and divide-by-four output
functions are provided for additional flexibility in designing complex clock systems.
When combined with the internal PLL,
these divide functions allow distribution
of a low-frequency clock that can be multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.
CY7B991
CY7B992
,,:rcYPRESS
ti' rtf i'
I
_0
_0
.?
(')
I
i' .?
::J
I
_0
_0
_0
-q
_0
::J
"+
::J
N
;!;;
_0
_0
+
0
+
::J
:;;:
+
_0
::J
;n
+
_0
::J
Ii5
+
_0
FB Input
REF Input
1Fx
2Fx
3Fx
4Fx
(N/A)
LM
- Stu
LL
LH
- 4tu
LM
(N/A)
- 3tu
LH
ML
- 2tu
- 1tu
ML
(N/A)
MM
MM
MH
(N/A)
+1tu
HL
MH
+ 2tu
HM
(N/A)
+ 3tu
HH
HL
HM
LL/HH
HH
+ 4tu
(N/A)
(N/A)
(N/A)
f--'
Otu
~
+ Stu
DIVIDED
INVERT
78991-3
Figure 1. 1YPical Outputs with FB Connected to a Zero-Skew Output[4]
Test Mode
Maximum Ratings
The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the
CY7B991/CY7B992 to operate as explained briefly above (for
testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a 100Q resistor.
This will allow an external tester to change the state of these
pins.)
If the TEST input is forced to its MID or HIGH state, the device
will operate with its internal phase locked loop disconnected, and
input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal
mode.
In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own function select inputs (xFO and xF1) and the waveform characteristics
of the REF input.
(Above which the useful life may be impaired. For user guidelines,
not tested.)
.
Storage Thmperature .................. -65°C to +150°C
Ambient Thmperature with
Power Applied ....................... -S5°C to +12SoC
Supply Voltage to Ground Potential ........ -O.SV to +7.0V
DC Input Voltage ....................... -O.SV to + 7.0V
Output Current into Outputs (LOW) .............. 64 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-88:~, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
Industrial
MilitaryLOJ
Notes:
4 FB connected to an output selected for "zero" skew (i.e., xFl = xFO =
MID).
5. Indicates case temperature.
10-132
Ambient
Thmperature
O°Cto +70°C
-40°C to +8SoC
-SsoC to +12SoC
Vee
SV ± 10%
SV ± 10%
SV± 10%
~
CY7B991
. , CYPRESS =============CY=7=B9=9=2
AC Test Loads and Waveforms
5V
~
I
CL
-=-
Rl
R2
-=-
3.0V
Rl = 130
R2 = 91
Cl = 60 pF (Cl = 30pF for -6 devices)
(Includes fixture and probe capacitance)
78991·4
78991-5
TTL AC Test Load (CY7B991)
TTL Input Test Waveform (CY7B991)
Vee
~
clI
-=-
-=-
Rl=100
Rl
R2 = 100
Cl = 50 pF (Cl = 30pF for -5 devices)
(Includes fixtllre and probe capacitance)
R2
78991-6
78991·7
CMOS AC Test Load (CY7B992)
CMOS Input Test Waveform (CY7B992)
Switching Characteristics Over the Operating Rangd2, 13J
CY7B991-S
Parameter
fNOM
tRPWH
tRPWL
tu
tSKEWPR
Description
FS - LOWll, "]
Operating Clock
Frequency in Mflz
FS - MIDL!,"J
FS - HIGHL!,",·]
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Outfut Matched-Pair Skew (XQO,
XQ1)[15,16
Min.
15
25
40
5.0
5.0
'lYP·
CY7B992-S
Max.
30
50
80
Min.
15
25
40
5.0
5.0
See Table 1
lYP.
Max.
30
50
801!4J
Unit
MHz
ns
ns
0.1
0.25
0.1
0.25
ns
tSKEWO
tSKEWI
Zero Output Skew (All OutputS)LD, 1IJ
Output Skew ,Rise-Rise, Fall-Fall, Same Class
Outputs)[15,1 ]
0.25
0.6
0.5
0.7
0.25
0.6
0.5
0.7
ns
ns
tSKEW2
Output Skew (Rise-F~I, Nominal-Inverted,
Divided-Divided)[15, 1 ]
O.S
l.O
0.6
1.2
ns
tSKEW3
Output Skew ~Rise-Rise, Fall-Fall, Different
Class Outputs) 15,18]
0.5
0.7
0.5
0.7
ns
tSKEW4
Output Skew (Rise-Fallj Nominal-Divided,
Divlded-Inverted)[15,18
Device-to-Device SkewI19, 251
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variationl:luJ
Output HIGH Time Deviation from 50%1'!, UJ
Output WW Time Deviation from 50%1"!, ""J
Output Rise Timel"!' :ljJ
Output Fall Timel"), .,]
PLL Lock TimeL:l4J
RMSL':>]
Cycle-to-Cycle Output
Jitter
I Peak-to-Peakl.:>J
0.5
1.0
0.6
1.3
ns
0.2
+0.5
+1.0
3.5
3.5
3.0
3.0
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
tSKEWS
tpo
toocv
tl'WH
tpWL
tORISE
tOFALL
tLOcK
tJR
-0.5
- 1.0
0.0
0.0
0.15
0.15
1.0
1.0
10-134
0.2
+0.5
+1.0
2.5
3
1.5
1.5
0.5
25
200
- 0.5
-1.0
0.0
0.0
0.5
0.5
2.0
2.0
L~
CY7B991
~, CYPRESS =============~C~Y~7~B9~92~
AC Timing Diagrams
REF
FB
Q
OTHERQ
INVERTEDQ
REF DIVIDED BY 2
REF DIVIDED BY 4
7899'·8
10-136
REF~
, , ,
,
FB
REF
FS
4FO
4F1
400
401
3FO
3F1
2FO
2F1
300
301
200
201
U1.I1..r
, , ,
1FO
1F1
100
101
lJ1.Jl.J
'
, ,
TEST
78991-11
Figure 4. Inverted Output Connections
Figure 4 shows an example of the invert function of the PSCB. In
this example the 400 output used as the FB input is programmed
for invert (4FO = 4F1 = HIGH) while the other three pairs of
outputs are programmed for zero skew. When 4FO and 4F1 are
tied high, 400 and 401 become inverted zero phase outputs. The
PLL aligns the rising edge of the FB input with the rising edge of
the REF. This causes the 10,20, and 30 outputs to become the
"inverted" outputs with respect to the REF input. By selecting
which output is connect to FB, it is possible to have 2 inverted
and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs. The correct configuration would be determined by the need
for more (or fewer) inverted outputs. 10, 20, and 30 outputs
can also be skewed to compensate for varying trace delays independent of inversion on 40.
Figure 5 illustrates the PSCB configured as a clock multiplier. The
300 output is programmed to divide by four and is fed back to
FB. This causes the PLL to increase its frequency until the 300
and 301 outputs are locked at 20 MHz while the lOx and 2Qx
outputs run at 80 MHz. The 400 and 401 outputs are programmed to divide by two, which results in a 40-MHz waveform
at these outputs. Note that the 20- and 40-MHz clocks fall simultaneously and are out of phase on their rising edge. This will al-
low the designer to use the rising edges of the 11, frequency and Y.
frequency outputs without concern for rising-edge skew. The
200,201, 100, and 101 outputs run at 80 MHz and are skewed
by programming their select inputs accordingly. Note that the FS
pin is wired for 80-MHz operation because that is the frequency
of the fastest output.
Figure 6 demonstrates the PSCB in a dock divider application.
200 is fed back to the FB input and programmed for zero skew.
30x is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of the 40x and 3Qx outputs are aligned. This allows use of the rising edges of the 11, frequency and Y. frequency without concern for skew mismatch. The
lOx outputs are programmed to zero skew and are aligned with
the 20x outputs. In this example, the FS input is grounded to
configure the device in the 15- to 30-MHz range since the highest
frequency output is running at 20 MHz.
Figure 7 shows some of the functions that are selectable on the
30x and 40x outputs. These include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output allows the system designer to clock different subsystems
on opposite edges, without suffering from the pulse asymmetry
typical of non-ideal loading. This function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be
aligned within the skew spec.
The divided outputs offer a zero-delay divider for portions of the
system that need the clock to be divided by either two or four,
and still remain within a narrow skew of the "IX" clock. Without
this feature, an external divider would need to be added, and the
propagation delay of the divider would add to the skew between
the different clock signals.
These divided outputs, coupled with the Phase Locked Loop, allow the PSCB to multiply the clock rate at the REF input by either two or four. This mode will enable the designer to distribute
a low-frequency clock between various portions of the system,
and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-skew characteristics of the
clock driver. The PSCB can perform all of the functions described above at the same time. It can multiply by two and four or
divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs.
REF
.JLh.....h..JLJ
I
REF1'L---h20 MHz
20 MHz
FB
REF
FS
4FO
4F1
3FO
3F1
2FO
2F1
1FO
1F1
TEST
400
401
300
301
200
201
100
101
FB
REF
FS
4FO
4F1
400
401
'20 MHz
3FO
3F1
2FO
2F1
300
301
1FO
1F1
TEST
100
101
~
'80 MHz
1.tnn.n.t.t.n.
,
hI1.I1.rtrLrL
,
I
I
I
, ,,
'40 MHz
~
,
I
200
201
,
010MHz
l--n--n--r
~:~
~
:
.:
I
I
:20)\1Hz
-f1..fLfLfLf1..
.[1.J1.f1.J1...
178991-12
78991·13
Figure 5. Frequency Multiplier with Skew Connections
Figure 6. Frequency Divider Connections
10-138
~
CY7B991
~~YPRESS============================CY==7B=9~~
Ordering Information
Accuracy
(ps)
Ordering Code
Package
Name
Package 'iYpe
Operating
Range
500
CY7B991-5JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
750
CY7B991-7JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7B991-7JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7B991-7LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Military
500
CY7B992-5JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
750
CY7B992-7JC
J65
32-Lead Plastic Leaded Chip Carrier
Commercial
CY7B992-7JI
J65
32-Lead Plastic Leaded Chip Carrier
Industrial
CY7B992-7LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
VOL
VIH
VIL
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VIHH
VIMM
VILL
IIH
IlL
IIHH
IIMM
IILL
ICCQ
ICCN
Switching Characteristics
Parameter
Subgroups
tNOM
tRPWH
tRPWL
tu
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
tSKEWPR
tSKEWO
tSKEWl
tSKEW2
tSKEW3
tSKEW4
tPD
tODcv
tpWH
tpWL
1,2,3
1,2,3
!aRISE
tQFALL
twcK
Document #: 38-oo188-F
10-140
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
CY7B9910
-ZZ~YPRESS=-=-=-=-=-=-=-~P~~=-L~IM~I~N~~~R~Y=-=-=-CY~7~B~9~~~O
Pin Definitions
I/O
Description
REF
I
Reference frequency input. This Input supplies the frequency and timing against which all functional
variation is measured.
FB
FSLl,4,:JJ
I
PLL feedback input (typically connected to one of the eight outputs).
I
Three-level frequency range select. See Table 1.
lEST
I
Three-level select. See Thst Mode section.
Q[0 .. 7)
0
VCCN
PWR
Power supply for output drivers.
VCCQ
GND
PWR
Power supply for internal circuitry.
PWR
Ground.
Signal Name
Clock outputs.
Maximum Ratings
(Above which the useful life maybe impaired. For user guidelines,
not tested.)
Storage Thmperature .................. -65°C to + 150°C
Ambient Thmperature with
Power Applied .................... , .. -55°C to + 125°C
Supply Voltage to Ground Potential ........ -0.5V to +7.0V
DC Input Voltage ....................... -0.5V to +7.0V
Output Current into Outputs (LOW) .............. 64 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STO-883, Method 3015)
Latch-Up Current ........................... >200 mA
Operating Range
Ambient
Temperature
O°Cto +70°C
-40°C to +85°C
Range
Commercial
Industrial
Vee
5V ± 10%
5V ± 10%
Electrical Characteristics Over the Operating Range
CY7B9910
Parameter
VOH
Description
Output HIGH Voltage
Test Conditions
Vee = Min., IOH - -16 rnA
Min.
2.4
CY7B9920
Max.
Output LOW Voltage
Max.
Unit
V
Vec = Min., IOH =-40mA
VOL
Min.
Vee- 0.75
Vee - Min., IOL - 46 rnA
0.45
V
Vee - Min., IOL -46 rnA
0.45
VIH
Input HIGH Voltage
(REF and FB inputs only)
2.0
Vee
Vee1.35
Vce
V
VIL
InEut LOW Voltage
(REF and FB inputs only)
-0.5
0.8
-0.5
1.35
V
VIHH
Three-Level I~ut HIGH
Voltage (Thst, S)[I]
Min . .s. Vee.s.Max.
Vee -1V
Vee
Vee -1V
Vce
V
VIMM
Three-Level Input MID
Voltage (Thst, FS)[I]
Min . .s. Vcc.s.Max.
Ve~250 mV
Ved2+
500mV
Ved2500mV
Vcd2+
500mV
V
VILL
Three-Level Input LOW
Voltage (Thst, FS)[I]
Min . .s. Vec.s.Max.
0.0
1.0
0.0
1.0
V
IIH
InputHIGHLeakageCurrent
(REF and FB inputs only)
Vee = Max., VIN = Max.
10
JAA
IlL
Input LOW Leakage Current
(REF and FB inputs only)
Vee - Max., VIN - O.4V
IIHH
Input HIGH Current
(Thst, FS)
VIN = Vee
IIMM
Input MID Current
(Thst, FS)
VIN- Ved2
I~ut LOW Current
VIN= GND
IILL
(
10
-500
200
-so
so
-200
st, FS)
10-142
JAA
-500
-50
200
JAA
50
JAA
-200
JAA
~
CY7B9910
_'/cYPRESS ========PRE=L;;;;;;IM=IN;;;;;;'AR=Y===CY;;;;;;7;;;;;;B;;;;;;9;;;;;;92=O
Switching Characteristics Over the Operating Range[7]
CY7B9910-S
Parameter
fNOM
tRPWH
tRPWL
tSKEW
tOEV
tpD
toocv
tORISE
tOFALL
tLOCK
tJR
Parameter
fNOM
tRPWH
tRPWL
tSKEW
tOEV
tpD
tODCV
tORISE
tOFALL
tLOCK
tJR
Description
FS - LOWL·,·]
Operating Clock
Frequency in MHz
FS - MIDL',0]
FS - HIGHL·,·,lU]
REF Pulse Width HIGH
REF Pulse Width LOW
Zero Output Skew (All OutputS)Ll<, U]
Device-to-Device SkewL","]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle VariationLloJ
Output Rise TimeLrt, I'J
Output Fall TimeLl ,1~J
PLL Lock TimeLI.J
Peak to PeaklI'J
Cycle-to-Cycle Output
Jitter
IRMSll'J
1YP.
Min.
15
25
40
5.0
5.0
REF Pulse Width HIGH
REF Pulse Width LOW
Zero Output Skew (All Outputs)II2, I3J
Device-to-Device Skewl14, 15J
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle VariationL,oJ
Output Rise TimeLlI, 10J
Output Fall TimeLI ,1OJ
PLL Lock TimeL"J
Peak to PeakL" J
Cyc1e-to-Cyc1e Output
Jitter
IRMSLl'J
0.0
0.0
1.0
1.0
- 0.7
- 1.2
0.15
0.15
Ved2.
9. The level to be set on FS is deteffilined by the "normal" operating frequency (JNOM) of the VCO (see Logic Block Diagram). Thefrequency
appearing atthe REF and FB inputswill be fNOMwhen the outputconnected to FB is undivided. The frequency of the REF and FB inputs
will be fNOMIX when the device is confignred for a frequency multiplication by using external division in the feedback path of value X.
10. When the FS pin is selected HIGH, the REF input must nottransition
upon power-up until Vce has reached 4.3V.
11 Except as noted, all CY7B9920-5 timing parameters are specified to
SO-MHz with a 30-pF load.
15
25
40
5.0
5.0
0.5
1.0
+0.5
+1.0
1.5
1.5
0.5
200
25
CY7B9910-7
Max.
'!Yp.
30
50
80
0.3
Notes:
7. Thst measurement levels for the CY7B99IO are TIL levels (1.5V to
1.5V). Thst measurement levels for the CY7B9920 are CMOS levels
(Ved2 to VccJ2). Thstconditions asume signal transition timesof2 ns
or less and output loading as shown in the AC Thst Loads and Waveforms unless otherwise specified.
S. For all three-state inputs, HIGH indicates aconneetion to Vce, WW
indicates a conoection to GND, and MID indicates an open connection. Internal teffilination circuitIy holds an unconoected input to
30
80
-0.5
-1.0
0.15
0.15
Min.
15
25
40
5.0
5.0
Min.
SO
0.25
Description
FS = LOWL-,']
Operating Clock
Frequency in MHz
FS = MIDlH,9J
FS = HIGHIH,9,IU J
CY7B9920-S
Max.
0.0
0.0
1.5
1.5
0.75
1.5
+0.7
+1.2
2.5
2.5
0.5
200
25
1YP.
Unit
30
MHz
SO
80ll lJ
0.25
- 0.5
-1.0
0.5
0.5
Min.
15
25
40
5.0
5.0
Max.
0.0
0.0
2.0
2.0
0.5
1.0
+0.5
+1.0
3.0
3.0
0.5
200
25
CY7B9920-7
Max.
'!Yp.
30
50
50
0.3
- 0.7
-1.2
0.5
0.5
0.0
0.0
3.0
3.0
0.75
1.5
+0.7
+1.2
5.0
5.0
0.5
200
25
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
12. SKEW is defined as the time between the earliest and the latest output
transition among all outputs when all are loaded with 50 pF and terminated with 50Q to 2.06V (CY7B99IO) or VccJ2 (CY7B9920).
13. tSKEW is defined as the skew between outputs.
14. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (Vee, ambient temperature, air flow, etc.).
15. Thsted initially and after any design or process changes that may affect
these parameters.
16. laDCV is the deviation of the output from a 50% duty cycle.
17. Specified with outputs loaded with 30 pF for the CY7B99XO-5 devices and 50 pF for the CY7B99XO-7 devices. Devices are terminated
through 50Q to 2.06V (CY7B9910) or Ved2 (CY7B9920).
IS. tORISE and tOFALL measured between O.SV and 2.0V for the
CY7B9910 or 0.8Vee and 0.2Vee for the CY7B9920.
19. tLOeK is the time that is required before synchronization is achieved.
This specification isvalid only after Veeis stable and within normal operating limits. This parameter is measured from the al'plication of a
new signal or frequency at REF or FB until tpD is Within specified
limits.
10-144
REF-f1..-tL.rL-~
FB
SYSTEM_-------1 REF
CLOCK
FS
I
I
I
:
,
:
,
:
I
I
I
I
•
I
,
LOAD
•
ZO-------'
'
,.------,
"'/~
~
00
01
::===LO==A=D===~
,-"
~ ~ 1L-_LO_AD---I
02
03
04
05
•
I
I
Zo
f10--------r,j'--_L_OA_D_....J
OS
07
789910-9
Figure 1. Zero-Skew and/or Zero-Delay Clock Driver
Operational Mode Descriptions
Figure 1 shows the device configured as a zero-skew clock buffer.
In this mode the 7B9910/9920 can be used as the basis for a lowskew clock distribution tree. The outputs are aligned and may
each drive a terminated transmission line to an independent load.
The FB input can be tied to any output and the operating frequency range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission
REF
lines (with impedances as low as 50 ohms), allows efficient
printed circuit board design.
Figure 2 shows the CY7B991O/9920 connected in series to
construct a zero-skew clock distribution tree between boards.
Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the PLLfilter.1t
is not recommended that more than two clock buffers be connected in series.
..JlJL.JL
, , ,
,
,
f---L--+~~,---LOA_D--,
FB
SYSTEM _ _- - - - - ! REF
FS
CLOCK
;
g~
g~
06
07
~
~
, , ,
1---...L:.f1,fl.fL
f Zo
I'--___
LOAD
..J
TEST
789910-10
Figure 2. Board-to-Board Clock Distribution
10-146
Section Contents
.;rcYPRESS
PC Chipsets
Page Number
Device
Description
CY82C597
CY82C599
386/486 Green Chipset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-1
Intelligent PCI Bus Controller ................................................ 11-61
PRELIMINARY
.;rcYPRESS
Pin Configuration
CY82C597
PQFP
i~lihUiil!ill ~~I~~il~~I~
Top View
I~
160 159158157156155164153152151150 149148147146145144143142141140139138137136135134133132131130129128127126125124123122 121
lllCSlMRI'
120
MAS
VCC
119
MA7
GNO
SDIRON4F
118
MAO
117
MAO
SDEfI
11.
SDIR1NCM
115
MAlO
DWIlOI!RI!
CAS!
B387NS4/MA11
IIIPJ'I!lY[l)
114
ClK
112
~
113
10
111
110
109
NMI
11
BSJG
E367FEl!
12
13
CPURST
14
A25!AEIW
15
HOLD
16
REIiI
Cl'OAD'I
,.
108
107
108
105
=
=
=
SI!IW.SKIIlllR
l'!ASO
R)\gf
MPO
MP1
17
104
MP2
MP3
016
Rll3BRDY
,.
103
VCC
GNO
20
21
DC/ADSTS
MJO
22
23
WI!
24
HLDA
AQ387BL
25
2.
27
ADS
1!E3
CY82C597
102
vee
96
019
97
020
••
28
017
GNO
101
100
99
01.
021
95
022
94
023
93
024
.,
025
80
89
66
87
027
m
29
I!E1
BEll
30
AS1
32
A24
A23
33
34
A22
3.
A21
66
031
38
85
coo
A20
37
84
C01
38
83
CO2
92
IJlBE
81
GNO
A19
0Q8
C09
92
31
..
40
026
028
D29
D30
~~~~~~~~~~~~~g~~~~~8~§881
~
62C5S7-1
11-2
~YPRESS
PRELIMINARY
CY82C597
the arbitration between Refresh, DMA and non-TURBO hold
request.
5. Levell Write-back CPU Support
In order to improve system performance and reduce bus
bandwidth requirements, some CPUs (from Intel, AMD, Cyrix,
etc.) implement an internal, level 1, write-back cache.
Write-back CPUs must snoop (by way of inquiry transactions)
all memory transactions. The CY82C597 will generate an
inquiry cycle by asserting EADS, which will be monitored by the
CPU, whenever there is an ISA DMNMASTER memory cycle.
During VESA master memory cycles, the VESA master must
assert EADS along with ADS. For PCI master memory cycles,
.the CY82C599 will assert EADS.
Upon seeing EA'i')S asserted, a write-back CPU will check the
status of its internal cache. If the CPU's cache contains the line
and it is marked modified (the data in the level 1 cache is more
up-to-date than the data in main memory), the cpu will assert
the HITM signal. If the CY82C597 sees HITM asserted, it will
relinquish the bus to the CPU and will not respond to the original
access until the CPU first copies the cache data back to system
memory (this is referred to as a write-back cycle). Write-backs
consist of burst write cycles (the CY82C597 will handle burst
writes to memory), The CY82C597 will wait until the CPU has
completed the write-back transaction before allowing any bus
master to access the modified memory location.
The CY82C597 has an inquiry filter to reduce the overhead of
unnecessary snoop cycles. Every time a bus master attempts to
access system memory, the CY82C597 will check to see if the
address was previously used for an inquiry cycle. If the address
was "snooped" in the previous transaction, the CY82C597 will
not generate an inquiry cycle (for ISA!DMA MASTER cycles) or
will ignore the results of the inquiry cycle (for VESA/PCI Bus
Master cycles) and will allow the transaction to pass directly to
system memory.
6. Write-back/Write-through Cache Controller
displaced data from the SRAMs is copied to the DRAMs before
the line fill. In the case of a write miss, data will only be written
to DRAM.
The CY82C597 also supports an 8-bit tag size (TAGA[7:0J)
without a DIRTY bit. All lines are considered dirty. On a cache
read miss, the line in the cache is automatically written back to
memory before the new line in memory is read. In the case of a
write miss, data will only be written to DRAM memory.
Write-back Operation
Thble 3. Thg RAM/Data RAM Requirements without a Dirty Bit
The CY82C597 implements a Burst mode, write-back cache
controller. It monitors TAGA[6:0j and compares it with the CPU
TAG address. If the cache is enabled and the Thg address
matches the CPU address, a "cache hit" is detected. During a
read hit, the CY82C597 will burst four double words to the CPU
by alternating CRDO and eRD1 (2 Banks of cache) or strobing
CRDO four times (1 Bank of cache).
In the case of a write hit, the CPU data will be written to the
cache RAMs by asserting CWEO or CWEl. DRAM data is not
updated.
During a read miss, the DIRTY bit will be checked before
reading in new data from the DRAMs. If DIRTY=1, the
Note:
1.
Write-through Operation
The· CY82C597 also supports write-through cache operation.
During a write hit, the CY82C597 writes data to both the SRAMs
and the DRAMs. Additional wait states are required especially
when a DRAM page miss occurs. For a write miss, data is written
to DRAM memory only. Only the 8-bit tag configuration is
supported in write-through mode.
The selection between write-through or write-back cache policies
is controlled by bit 6 of register 11.
DMA/lSA Master Transactions
When a DMA/MASTER memory read hit occurs, data will be
supplied from the cache SRAMs instead of the DRAMs. On a
memory read miss, data is supplied by the DRAMs. In the case
of a DMA/MASTER memory write hit cycle, data will be written
into the DRAMs and SRAMs. A DMAIMASTER write miss
cycle will only write data into the DRAMs.
Tag RAM/Data RAM Configurations
The CY82C597 supports 32KB, 64KB, 128KB, and 256KB cache
sizes for the 386, and 64KB, 128KB, 256KB, 512KB, and 1MB
cache sizes for the 486. In write-back mode, the CY82C597
combines the DIRTY RAM with the Thg RAM, thereby saving
one SRAM for cache systems. The dirty bit can be replaced by a
tag address in order to increase the cachable range. See Tables 3,
4, and 5.
Dirty bit support vs. more cachable memory is
controlled through bit 4 of control register 16.
Cache
Size
Thg RAM
ThgAddress
ThgField
Cachable
Size[l]
32KB
2Kx8
A14 -A4
A22 -A15
64KB
4Kx8
A15 -A4
A23 - A16
8MB
16MB
128KB
8Kx8
A16 -A4
A24 - A17
32MB
64MB
256KB
16Kx8
A17 -A4
A25 - A18
512KB
32Kx8
A18 -A4
A26 - A19
128 MB
1MB
64Kx8
A19 -A4
A26 - A20
128MB
128MB is the maximum DRAM size supported.
11-4
~YPRESS
PRELIMINARY
7. Page Mode DRAM ControUer
Introduction
A pure Page mode DRAM controller is used in this design. No
Interleaving is required. The CY82C597 can support mixed
DRAM sizes. The starting address of each DRAM bank is
calculated by internal hardware. The user can configure DRAM
memory from 1MB to 128MB, as long as the memory stays
CY82C597
continuous. The DRAM controller supports up to four banks of
DRAM memory. Four RAS and four CAS signals (for three and
four bank systems) or two RAS and four CAS signals (for one
and two bank systems) are the allowed options. The DRAM
controller also provides the multiplexed row and column
addresses for the DRAMs. The address split is configurable, and
the supported DRAM splits are given in the following tables.
DRAM Row/Column Address
The DRAM row address is listed as follows:
Address
Split
Row Address
Row
Col.
DRAM
1YPe
9
9
256KB
A12
A13
Al4
Al5
Al6
Al7
9
10
5l2KB
Al2
A13
A14
A15
A16
A17
10
10
1MB
Al2
A13
A14
A15
A16
A17
11
9
1MB
A12
A13
A14
A15
A16
A17
12
8
1MB
A12
A13
A14
A15
A16
MAO
MA2
MAl
MA3
MA4
MAS
MA6
MA7
MAS
MA9
MAIO
MAll
Al9
All
X
X
X
A18
A19
AZO
X
X
X
A18
A19
AZO
A2l
X
X
A18
A19
AZO
A2l
All
X
A17
A18
A19
AZO
AZ1
All
A10
Al8
11
10
2MB
AZ2
A13
A14
A15
A16
A17
Al8
A19
A20
AZl
Al2
X
12
9
2MB
AZ2
A13
A14
A15
A16
A17
A18
A19
A20
A21
A12
All
11
11
4MB
A23
A13
A14
A15·
A16
A17
A18
A19
AZO
AZ1
A22
X
12
10
4MB
A23
A13
A14
A15
A16
A17
A18
A19
A20
AZ1
A22
A12
16
6
4MB
AZ3
A13
A14
A15
A16
A17
A18
A19
AZO
AZl
A22
X
12
12
16MB
AZ3
AZ4
A14
A15
A16
A17
A18
A19
A20
AZl
AZ2
A25
The DRAM column address is listed as follows: [6)
Address
Split
Column Address
DRAM
TYPE
Row
Col.
9
9
256KB
MAO
9
10
512KB
A2
10
10
1MB
AZ
AZ
MAl
A3
MA2
MA3
MA4
MAS
MAIO
MAll
A8
1\9
AI0
X
X
X
A6
A7
AS
1\9
AIO
All
X
X
A6
A7
A8
A9
AIO
All
X
X
AS
A6
A3
M
A3
A4
M
M
MA6
MA7
MAS
MA9
A7
A4
11
9
1MB
AZ
A3
A4
AS
A6
A7
A8
A9
AI0
X
X
X
12
8
1MB
AZ
A3
A4
AS
A6
A7
A8
A9
X
X
X
X
X
11
10
2MB
A2
A3
A4
AS
A6
A7
A8
A9
AI0
All
X
12
9
2MB
AZ
A3
A4
AS
A7
A8
A9
AI0
X
X
X
11
11
4MB
AZ
A3
A4
M
M
M
M
A6
A6
A6
A6
A6
A7
AS
1\9
AIO
All
A12
X
A7
A8
All
X
X
AS
1\9
1\9
AIO
A7
AIO
All
AU
X
A7
A8
1\9
AlO
All
Al2
A13
12
10
4MB
6
4MB
A2
A2
A3
16
A3
M
M
12
12
16MB
AZ
A3
A4
Notes:
6. The column address lines are inverted from the CPU address.
11-6
~YPRESS
PRELIMINARY
16. Numerical Coprocessor Inte~ce Logic
The CY82C597 supports the Weitek 4167 Numerical
Coprocessor (486SX systems), the Weitek 3167, and the Intel 387
Numerical Coprocessor (386 systems) without any eJ[ternal logic.
For 486SX systems, INT13 will be asserted when either F'ERR or
WTINTR is activated. As soon as the F'ERR is asserted, the
interrupt service routine will handle the error and clear the
rt~rwPt by executing a dummy write to I/O port FOH. The
G E signal is also activated by writing to the I/O port FOH.
For 386 systems, BUSY386 is asserted when BUSY387 is active
to signal the 386 that the coprocessor is ERR3~' executing an
instruction. If BUSY387 is active when
is active, the
BUSY387 will be latched and IRQ will be generated. The
latched BUSY387 can be cleareq by performing a write to I/O
port FOH. If the Weitek 3167 is being used and the W~R3£t
signal (WTINTR) is active, IRQ will be asserted. The
6
signal is asserted after system reset if a 387 is present. It will stay
active until the first CPU cycle begins.
17. Keyboard Emulation Logic
I/O Port 60H and 64H are used to implement keyboard controller
emulation. The keyboard emulation is enabled by programming
register 10, bit 3 to a O. When fast GA20 is enabled, writing OlH to
Port 64H followed by DOH to Port 60H, A20 will be forced LOW
in a 386 system. For a 486 system, the ~ pin should be
connected to the 8042 and E386NGT functions as the A25 input.
If the system is designed to support 32 MB of main memory or less,
the E386NGT signal can be connected to the A20M signal on the
486 for fast GA1EA2O operation.
The CY82C597 also performs fast RESET by intercepting the
keyboljrd reset command sequence !j11d performing the reset
directly. The CY82C597 can be programmed to wait for a
HALT Instruction before asserting reset to the CPU.
18. Port B (61H), NMI, and Port 70H
When a parity error is detected by the CY82C597 , an NMI will be
generated to the CPU if NMI reporting is enabled. NMI reporting
can be enabled by setting bit 7 of Port 70H to O. The CY82C597
provides access to the Port B register defined fot a PC!AT. The
chart below illustrates the bit definition for Port B (61H):
Address Bit Access
61H
7
Read Only
Description
System memory parity check
6
Read Only I/O channel check
5
Read Only Timer 2 output
4
Read Only Refresh detection
3
ReadlWrite 0: Enable I/O channel check
1: Disable I/O channel check
2
ReadlWrite 0: Enable system memory parity
check. '
1: Disable system memory parity
check
1
ReadlWrite Speaker data
0
ReadlWrite Timer 2 gate
CY82CS97
memory mapping. All other power management functions in the
CY82C597 are disabled. For VESA/lSA-only systems, the
CY82C597 provides all of the chipset power management.
There are eleven event detectors and five user-progranunable
timers in the CY82C597 allowing it to support full hardware
power management (for CPUs that do not support SMM, System
Management Mode) and software power management (through
SMM).
Monitored Events
The CY82C597 allows the following events to be monitored:
1. VESA master request
2. Keyboard command
3. Serial Port command
4. Parallel Port command
5. Hard Disk command
6. OMA/MASTER request from the ISA bus
7. Non-motherboard memory access
8. Video memory access
9. A specific I/O address
10. A specific memory range
11. A specific I/O range
When events are detected, the CY82C597 will transition to
different power-down states.
Hardware Power Management
For hardware power management, the CY82C597 supports
Full-speed/Stand-by/Suspend!Off states. In Stand-by state, the
CY82C597 will assert the Sj:PWCLK signal that can be used by
the system to slow down the CPU's clock frwnn In the
Su~end state, the CY82C597 will assert the S OPC
signal.
STl'CLK can be used to stop the CPU's clock or turn off the
monitor and other supported peripherals.
In the Full-speed state, the CY82C597 will monitor all stand-by
events. Any monitored event will reset the stand-by timer. If no
events occur within the period specified by the stand-by timer,
the CY82C597 will enter the Stand-by state and assert the
SLOWCLK signal. Once Stand-by state has been entered, the
CY82C597 will monitor Suspend state events. If no event occurs
within the period eiecified by the suspend timer, the CY82C597
will assert STOP LK and enter the Suspend state. In the
Suspend state, the assertion of STOPCLK can be used to stop the
CPU's clock or power-down any supported peripherals. If any
monitored event is detected, the CY82C597 will return to the
Full-speed state and STOPCLK/SLOWCLK will be deasserted.
Any interrnpt will temporarily cause the STOPCLK signal (and
optionally the SLOWCLK signal) to be deasserted (allowing the
CPU to service the interrupt). If the interrupt timer expires
before a monitored event occurs, the CY82C597 will
automatically returu to the power-down state it was in prior to
the interrupt (with the appropriate signal asserted).
19. Power Management Logic
The CY82C597 implements flexible power management logic.
When used with the CY82C599 (for a full VESA/lSAlPCI
system), most ofthe power management functions are performed
by the CY82C599. The CY82C597 will only perform the SMM
11-8
PRELIMINARY
Q-YPRESS
CY82C597
CY82C597 Control Registers
The control registers for the CY82C597 are defined in this
section. The registers can be accessed through I/O Ports 22H and
23H. Th access each register, the user must first write the index
number of the register into Port 22, which forces the internal
decoding logic to point to the selected register. Data can be
accessed by then readinglwriting to/from Port 23.
Register 10: AT Bus Control, Index: 10
Bit
Function
Default
7
486 speed indicator:
0:
20/25 MHz
1:
33/40/50 MHz
0
6
Parity check disable: [7]
0:
Enable parity checking
1:
Disable parity checking
0
5
386 speed indicator:
0:
40 MHz
1:
33 MHz (or any speed below 33 MHz)
0
4
Reserved, BIOS should set to 1.
0
3
Fast Gate A20 Emulation Control (386 only):
0:
Enable
1:
Disable
0
2
Thrbo speed control:
0:
Enable turbo speed (high speed)
1:
Enable low speed
0
1:0
ATCLK control:
00
Bits
01
00:
01:
10:
11:
Bits
01
00:
01:
10:
11:
Bits
01
00:
01:
10:
11:
486 ~Ilt!ilm; (pin 4 ti!:d tQ Ycc: tl!l:QlIgl! iI 51KQ !ll~istQr)
CLK/4
CLK/6
CLK/8
CLK/5
486 ~s!!ilm; (pin 4 tied tQ Vss tl!rollgl! iI 1KQ resistQ[)
CLK/2
CLK/3
CLK/4
CLK/2.5
386 system:
CLK/4
CLK/6
CLK/8
CLK/10
Notes:
7.
If parity checking is disabled, the parity bits are used as VESA local
bus request and grant signals (see pin description). If parity is
required in the system, an external PAL must be used to control VESA
11-10
local arbitration signals (if bus mastership from the VESA slots is
allowed).
PRELIMINARY
CY82CS97
Register 13: DRAM Wait State and Cachable Range Control, Index: 13[13]
Bit
Function
Default
7:4
Bits:
1654
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
1011:
1100:
1101:
1110:
1111:
0000
Ranl:e
0-128MB
0-8MB
0-16MB
0-24MB
0-32MB
0-40MB
0-48MB
0-56MB
0-64MB
0-72MB
0-80MB
0-88MB
0-96MB
0-104MB
0-112MB
0-128MB
3
Reserved, BIOS should set to 1.
0
2
DRAM write wait states:
0:
1 wait state
1:
owait states
0
1:0
DRAM read wait states:
Bits
10
# of wait states
00:
3
01:
2
10:
1
11:
0
00
Notes:
13. The CY82C597 will take care ofthe cachable range. Bits [7:4] arefor
custom memory configurations.
11-12
PRELIMINARY
QYPRESS
Shadowing Instructions
To shadow system BIOS (Block F), you must:
1. Set register 15, bit 6 to "0" to enable ROM access.
2. Read ROM data into the CPU register.
3. Set register 15, bit 6 to "1" to enable RAM access.
4. Set register 15, bit 7 to "0" to enable RAM write.
5. Write the data stored in the CPU register to RAM.
6. Go to step 1 if not done. Else, go to step 7.
7. Set register 15, bit 7 to "1" to enable shadow RAM read
access and write protect it.
Shadowing on-board ROM is similar to shadowing system ROM.
The following example is used to shadow Block C from on-board
ROM:
1. Set register 15, bit 0 to "1" to enable ROM access.
2. Read ROM data into the CPU register.
3. Set register 15, bit 0 to "0" to enable RAM access.
4. Set register 15, bit 1 to "0" to enable RAM write.
5. Write the data stored in the CPU register to RAM.
6. Go to step 1 if not done. Else, go to step 7.
7. Set register 15, bit 1 to "1" to enable shadow RAM read
access and write protect it.
Shadowing AT bus ROM is slightly different than shadowing
on-board ROM. The following example is used to shadow Block
C from AT bus ROM:
1. Set register 15, bit 0 to 0 to disable on-board ROM
access.
2. Set register 15, bits 2, 3, 4, and 5 to 0 to disable RAM
access. All access to Block C will go to the AT bus.
3. Read AT ROM data into CPU register.
4. Set register 15, bits 2, 3, 4, and 5 to 1 to enable RAM
access.
5. Set register 15, bit 1 to 0 to enable RAM write.
6. Write the data stored in CPU register to RAM.
7. Go to step 1 if not done. Else, go to step 8.
8. Set register 15, bit 1 to 1 to enable shadow RAM read access and write protect it.
11-14
CY82C597
PRELIMINARY
QYPRESS
CY82C597
Register 19: Non·cachable Block 0 Starting Address and Size, Index: 19[18]
Bit
Function
Slow DRAM select:
Fast page mode DRAM supported.
0:
1:
Fast page mode DRAM not supported
Default
0
486 Single bank SRAM select:
0:
Support interleaved SRAMs (2 banks of SRAMs).
1:
Support 1 bank of SRAMs.
This is for 128KB cache using 32Kx8 SRAMs and 512KB cache using 128Kx8 SRAMs.
Reserved, BIOS should set to O.
0
4
Non-cachable Block 0 control:
Disable.
0:
1:
Enable.
0
3:1
Non-cachable size
Bits:
Size
321
000:
64KB
010:
128KB
100:
256KB
110:
512KB
001:
1MB
011:
2MB
000
0
Non-cachable/non-local Block 0 starting address A24.
0
7
6
5
0
Note:
18. For 64KB non-eaehable size, the starting address is bound by A24-A16 from the configuration registers.
For 128KB non-caehable size, the starting address is bound by A24-At7 from the configuration registers.
For 256KB non-cachable size, the starting address is bound by A24-AlB from the configuration registers.
For 512KB non-cachable size, the starting address is bound by A24-Al9 from the configuration registers.
For 1MB non-cachable size, the starting address is bound by A24-A20 from the configuration registers.
For 2MB non-cachable size, the starting address is bound by A24-A21 from the configuration registers.
Please note that the non-cachable size is independent of cache size. The non-cachable starting address and non-eaehable size are used to define an
address range that will not be cached.
When Register 16, bit 2 is set to I, the non-eachable block will be changed to a non-local block. All addresses within this block will not be on the
motherboard, i.e., they will go to the AT bus or VESA bus.
For 386 sYStems, 32KB/128KB cache is fixed to 1 bank of SRAMs. 64KB/256KB is fIXed to 2 banks of SRAMs. For 486 systems,
64KB/128KB/256KB/512KB/IMB can be either 1 or 2 banks of SRAMs.
11-16
PRELIMINARY
Register IC: MisceUaneous Control Register, Index: IC
Bit
Function
7
6
5
CY82C597
Default
0
Bits
0:
1:
Symmetrica14MB DRAM
Special 4MB DRAM with 16 row addresses and 6 column addresses
Bits
0:
1:
Symmetrical 4MB DRAM
Special 4MB DRAM with 12 row addresses and 10 column addresses
Bits
0:
1:
Normal mode (For 40/50 MHz systems, this bit should be set to 0)
Fast write at 25133 MHz
0
0
4
Reserved, BIOS must set to 1.
0
3
Bits
0:
1:
0
Keyboard soft reset will not generate NPRST
Keyboard soft reset will generate NPRST
2
Reserved, BIOS should be set to O.
0
1
Bits
0:
1:
0
ATCLK controlled by register 10, bit [1:0]
ATCLK fixed at 7.159 MHz
Bits
0:
1:
Normal mode (no additional IDLE AT CYCLES between AT command cycles)
Add one extra JDLE AT CYCLE between AT command cycles
0
0
Register 10: MisceUaneous Control Register, Index: ID
Bit
Function
Default
7
Bits
0:
1:
0
Normal mode (enable upper DRAM)
Upper 64KB or lKB DRAM memory will be disabled
Bits
0:
1:
Upper 64K of DRAM will be disabled if bit 7=1
Upper lK of DRAM will be disabled if bit 7=1
6
0
5
Reserved, BIOS should set to O.
0
4
Bits
0:
1:
0
Add one SYSCLK cycle of delay before AT cycle detection
Add two SYSCLK cycles of delay before AT cycle detection
3
Fast DRAM write, BIOS should set to 1.
0
2
Reserved, BIOS should be set to O.
0
1
Bits
0:
0
1:
0
AT cycle detection at end ofTI if register 11, bit 7=1 (2111 mode)
AT cycle detection at end of second T2 if register 11, bit 7=0 (3111/3222 mode)
Add extra delay on AT cycle detection, extra delay based on register ID, bit 4 setting
Reserved, BIOS should set to O.
0
11-18
PRELIMINARY
QPRESS
CY82C597
Register 60: I/O Address (for Address Detection), Index: 60
Bit
Function
7:0
Bits
7:0
Default
00000000
I/O Address to be Monitored
Register 61: I/O Address Detection and Miscellaneous Control, Index: 61
Bit
Function
Default
7
Bits
0:
1:
0
VESNAT only mode (82C597 stand-alone)
82C599 PCI bridge is present in the system
Bits
0:
1:
NMI output is non three-state
NMI output is three-state
6
0
5
Reserved
0
4
Reserved
0
3
Bits
0:
1:
0
Disable I/O address detection
Enable I/O address detection
2
Reserved, must be O.
0
1:0
I/O address (9:8).
00
Register 62: Suspend Timer and Interrupt Timer Control, Index: 62
Bit
Function
Default
7:4
Bits (Suspend Timer Period)
0000:
3.8 min.
0001:
7.5 min.
0010:
15 min.
0011:
30mins.
6Omins.
0100:
0101:
120 mins.
0110:
240mins.
0111:
480mins.
1 sec.
0000:
1001:
1.8 sec.
1010:
3.5 sec.
7 sec.
1011:
1100:
14 sec.
1101:
28 sec.
1110:
56 sec.
1111:
2 min.
0000
3:0
Bits (Interrupt Timer Period)
0000:
Reserved
0001:
Reserved
0010:
Reserved
0011:
Reserved
0100:
Reserved
0101:
54 j.tSec.
0110:
107 j.tSec.
0111:
215 j.tSec.
0000:
430 !1sec.
1001:
860 j.tSec.
1010:
1.7 msec.
1011:
3.4 msec.
1100:
7msec.
1101:
14 msec.
1110:
28 msec.
55 msec.
1111:
0000
11-20
PRELIMINARY
QYPRESS
Hardware Power-down mode allows STOPCLK and SLOWCLK
to be Controlled by the 82C597 hardware. Software Power-down
CY82C597
mode will use System Management Mode (SMM) subroutines to
implement power-down control.
Register 64: Power-Down Mode Control, Index: 64
Default
Bit
Function
7
Bits
0:
1:
Software initial SMI
0
Normal
Writing an 1 to this bit will generate an SMI to CPU. After a 1 is written, software
should write a 0 to this bit.
6
Bits
0:
1:
SMI inactive control
5
Bits
0:
1:
STOPCLK Active Control
0
Normal
Writing a 1 to this bit will assert STOPCLK. Software should subsequently write a 0
to this bit to allow STOPCLK to be deasserted.
4
Bits
0:
1:
Software STOPCLK Inactive Control
0
Normal
Writing a 1 will deassert STOPCLK. Software should subsequently write a 0 to this
bit to allow STOPCLK to be asserted.
3
Bits
0:
1:
Software SLOWCLK Active Control
Normal
Writing a 1 will assert SLOWCLK. Software should subsequently write a 0 to this
bit to allow SLOWCLK to be deasserted.
2
Bits
0:
1:
Software SLOWCLK Inactive Control
0
Normal
Writing a 1 will deassert SLOWCLK. Software should subsequently write a 0 to this
bit to allow SLOWCLK to be asserted.
1
0
Suspend Timer Control
Bits
0:
Enable suspend timer (default)
1:
Disable suspend timer
The 82C597 allows a second Suspend mode to be started after current suspend timer has
reached its terminal count (i.e. When the current suspend timer expires, it will assert SM!.)
Within the SMI subroutine, the suspend timer can be disabled and the suspend timer reenabled. After the new terminal count has been reached, the 82C597 will initiate another SM!.
0
Bits
0:
1:
0
Normal
Writing a 1 to this bit will deassert the SMI signal. This is the only way to cause the
82C597 to deassert SM!. After a 1 is written, 0 should be written to this bit.
Disable Software Reset Mask
Normal
Force 82C597 to activate pin 153.
This bit should be set to 1, then set to 0 before leaving the SMI subroutine.
0
0
Register 65: Power Management Control, Index: 65
Bit
Function
7
Bits
0:
1:
Disable SMIACT/SMADS input signal
Enable SMIACT/SMADS input signal
Bits
0:
1:
INTEL SMM mode
CyrixiAMD SMM mode
6
5
Default
0
0
Bits
0:
1:
0
Disable quick power-down mode
Enable quick power-down mode when power-down key is pushed.
4
Reserved, must be 0
0
3:0
Reserved
0000
11-22
~YPRESS
PRELIMINARY
CY82C597
Register 6A: 82CS97 Status Register, Index: 6A
Read Cycle:
SetA
SetB
Bit 7=1
SMI caused by start of stand-by mode
SMI caused by timer 5 reaching its terminal count
Bit 6=1
SM! caused by end of stand-by mode
SMI caused by timer 5 reset by"an event
Bit5=1
SM! caused by suspend timer reaching its terminal
count
82C597 is in power-down mode (stand-by or suspend
mode)
Bit 4=1
SM! caused by register 64, bit 7
82C597 is in suspend mode. Once in suspend mode,
this bit will stay 1 unless any suspend event becomes
active, or power-down mode is disabled
Bit3-1
SMI caused by timer 3 reaching its terminal count
STOPCLK pin is active
Bit 2 1
SM! caused by timer 3 reset by an event
SWWCLK pin is active
Bit 1-1
SM! caused by timer 4 reaching its terminal count
BitO=1
SM! caused by timer 4 reset by an event
Suspend timer has reached its terminal count. It will be
o if register 64, bit 1 is set to 1 later
SMI pin is active
The CY82C597 has two status registers (16 bits total) that can be
read through register 6A. Writing a 0 into bit 7 will cause A
status set to be read on a read cycle. Writing a 1 into bit 7 will
cause B status set to be read on a read cycle.
Register 68: DRAM Bank 2/3 Control, Index: 6B
Register 6A contains the source of an SMI and some internal
status. The status can be used to power-downJpower-up
individual system devices (monitor, CPU, hard disk, etc.).
Bit
Function
Default
7
Reserved
0
6:4
Bits
000:
001:
010:
011:
100:
101:
110:
111:
3
0
Bits
0:
2:0
000
Disable Bank 3
Bank 3 is 256KB
Bank 3 is 1MB
Bank 3 is 4MB
Reserved
Bank 3 is 512KB
Bank 3 is 16MB
Bank 3 is 2MB
1:
Disable Bank 2 and 3
Enable Bank 2 and 3
Bits
000:
001:
010:
011:
100:
101:
110:
111:
Disable Bank 2
Bank 2 is 256KB
Bank2is 1MB
Bank 2 is 4MB
Reserved
Bank 2 is 512KB
Bank 2 is 16MB
Bank 2 is 2MB
000
11-24
~YPRESS
PRELIMINARY
CY82CS97
Register 6E: Shadow RAM Block D, C Control, Index: 6E
Bit
Function
Default
7
Register 15, Bit 1 control (Block C RAM RJW control):
Bits
0:
Enable Register 15, Bit 1
1:
Disable Register 15, Bit 1 (Replaced by Register 6E, Bit 6)
0
6
Block C RAM enable control (see Bit 7):
Bits
0:
Read or Write
1:
Read only
0
5
Shadow RAM at DCaOOH - DFFFFH control:
Bits
0:
Disable. Will access AT Bus memory
1:
Enable.
0
4
Shadow RAM at D80aOH - DBFFFH control:
Bits
a:
Disable. Will access AT Bus memory
1:
Enable.
0
3
Shadow RAM at D4aOOH - D7FFFH control:
Bits
0:
Disable. Will access AT Bus memory
1:
Enable.
0
2
Shadow RAM at DOaOOH - D3FFFH control:
Bits
0:
Disable. Will access AT Busmemory
1:
Enable.
0
1
Block D RAM access control (DOaOOH - DFFFFH):
Bits
a:
Read or Write
1:
Read only
0
0
Block D RAMIROM control:
Bits
a:
Access RAM. For those disabled RAM, access will go to AT Bus memory.
1:
Access on board ROM.
0
11-26
PRELIMINARY
QYPRESS
CY82C597
Register 71: Timer 3 Event Detection Control, Index: 71
Bit
Function
Default
7
Bits
0:
1:
0
Disable key-board event detection
Enable key-board event detection
Bits
0:
1:
Disable serial port event detection
Enable serial port event detection
Bits
0:
1:
Disable parallel port event detection
Enable parallel port event detection
Bits
0:
1;
Disable hard disk event detection
Enable hard disk event detection
Bits
0:
1:
Disable DMAIISA master event detection
Enable DMNISA master event detection
Bits
0:
1:
Disable non-motherboard memory event detection
Enable non-motherboard memory event detection
6
5
4
3
2
1
Reserved
0
Bits
0:
1:
0
0
0
0
0
0
0
Disable video memory (Block A,B) event detection
Enable video memory (Block A,B) event detection
Register 72: Timer 3 Control, Index: 72
Bit
Function
7:4
Bits
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010
1011:
1100:
1101:
1110:
1111:
'Thrminal Time
1 sec.
1.8 sec
3.5 sec
7 sec.
14 sec.
28 sec.
56 sec.
2 min.
3.8 min.
7.5 min.
15 min.
30 min.
60 min.
120 min.
240 min.
480 min.
Bits
0:
1:
Disable timer 3
Enable timer 3
Bits
0:
1:
Disable special memory I/O event detection (please see register 66, 67, and 68)
Enable special memory I/O event detection
Bits
0:
1:
Disable I/O event detection (please see registers 60 and 61)
Enable I/O event detection
Bits
0:
1:
Disable VESA master event detection
Enable VESA master event detection
3
2
1
0
Default
0
\
0
0
0
0
11-28
PRELIMINARY
CY82C597
Register 75: Timer 5 Event Detection Control, Index: 75
Bit
Function
Default
7
Bits
0:
1:
0
Disable key-board event detection
Enable key-board event detection
Bits
0:
1:
Disable serial port event detection
Enable serial port event detection
Bits
0:
1:
Disable parallel port event detection
Enable parallel port event detection
Bits
0:
1:
Disable hard disk event detection
Enable hard disk event detection
Bits
0:
1:
Disable DMA/ISA master event detection
Enable DMA/ISA master event detection
Bits
0:
1:
Disable non-motherboard memory event detection
Enable non-motherboard memory event detection
6
5
4
3
2
1
Reserved
0
Bits
0:
1:
0
0
0
0
0
0
0
Disable video memory (Block A,B) event detection
Enable video memory (Block A,B) event detection
Register 76: Timer 5 Control, Index: 76
Bit
Function
7:4
Bits
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010
1011:
1100:
1101:
1110:
1111:
Thrminal Time
1 sec.
1.8 sec
3.5 sec
7 sec.
14 sec.
28 sec.
56 sec.
2 min.
3.8 min.
7.5 min.
15 min.
30 min.
60 min.
120 min.
240 min.
480 min.
3
Bits
0:
1:
Disable timer 5
Enable timer 5
Bits
0:
1:
Disable special memory I/O event detection (please see register 66, 67, and 68)
Enable special memory I/O event detection
Bits
0:
1:
Disable I/O event detection (Please see register 60, 61)
Enable I/O event detection
Bits
0:
1:
Disable VESA master event detection
Enable VESA master event detection
2
1
0
Default
0000
0
0
0
0
11-30
~YPRESS
PRELIMINARY
CY82CS97
Register 79: Non-Cachable Block 1 Starting Address and Size, Index: 79[24]
Bit
Function
Default
7
Non-cachable/non-local Block 1 starting address A26.
0
6
Non-cachable/non-local Block 1 starting aIi of Bank 1 cache data
SRAMs.
CWEO
0
71
Cache write enable for tbe even bank of SRAMs.
CWEI
0
72
Cache write enable for tbe odd bank of SRAMs.
TOGA2
0
73
A dual function pin. For 386 systems, it is used to toggle CPU address A2 during
cache accesses. For 486 systems with 1 bank of SRAMs, it is address 2 to bank O.
For 486 systems with 2 banks of SRAMs, it is address 3 input to bank O.
TOGA3
0
74
A dual function pin. For 386 systems, it is used to toggle CPU address A3 during
cache accesses. For 486 systems with 1 bank of SRAM, it is address 3 to bank O.
For 486 systems with 2 banks of SRAMs, it is address 3 input to bank 1.
fAGWT
0
42
Thg RAM write enable, active LOW. It is active during a cache write hit or cache
move in cycle.
TAGEN
0
41
An active LOW signal. When active, it will enable tbe CY82C597 to read/write the
ThgRAM.
XA20EA
I/O
10
This is a dual function pin. For 486 systems, it is EADS to invalidate a 486 internal
cache line. It is active during DMA/MASTER memory write hit cycles. For 386
systems, the CPU is from CYRIX, this pin is tbe EADS output to invalidate the
CPU's cache line during DMAIMASTER memory write cycles. If Intel or AMD,
this pin the SA20 output or input for DMA/MASTER cycles.
A25/AEN8
I/O
15
This is tbe CPU A25 input signal during CPU cycles and the :A'EN8 input signal
during DMA cycles.
KEN
0
17
l inactive delay
6
18
ns
T367
COMMAND active to DWIUJIViKB active delay
5
20
ns
T368
COMMAND inactive to DWROMKB inactive
5
18
ns
11-40
~YPRESS
PRELIMINARY
CY82C597
Switching Waveforms
Clock Timing
T100 - - - - - - . 1
T102
-2.0v
ClK
-1.5v
-O.Bv
T103
820597-2
T104
Reset Timing
ClK
:T1r -.. .
,
CPURST
T10S{
T108t
-I
- - - - f l ' - - - - -.......!.!.2!.
((
~(
NPRST
--t
82C597-3
AT Cycle Timing
ClK
ATClK
ALE
J
__
~
L
__.M__
~~
__
~
__
~
______
' / ',
~,
_~~--~--~--~~--~--~~--~--~~--~T~~1~1~~,~~;1-1-2~--~----I
I
I
I
82C597-4
11-42
~YPRESS
PRELIMINARY
CY82C597
Switching Waveforms (continued)
486 Cache Read Hit (2-1-1-1 Burst Mode), 2 Banks of Cache, Interleaved
TW
T1
T2
\\\
tIl
TW
TW
T1
elK
ADS
L
A[31:2]
TAGA[7:0]
TAGEI'I
GRDO
--IT321
CRITI
,
T342
TOGA2
,
t
I
Z~ZZZZi~
T323
I
TOGA3
ZZZZZZK,
T324
BRDY
T323
:xi
4
Z~
:T325
r=-:
"~
ZXxxzxt
,
1ID\ST
2
--:{:
Xh
3
151
T31,6
~
L
11-44
62C597-7
~YPRESS
PRELIMINARY
CY82C597
Switching Waveforms (continued)
Cache Write Hit Cycle (Write-Back)
elK
TAGA[7:0]
J
xxxxxxxXXX :
i
,
CWEO
CWE1
- l r.107
-lT306~
: \ -l
TAGWf
mIDJ
~
xXXxxX
r------
r -r----,.--......,
r.109
-Ir.108~
,
,
::l
-:
T31'f~
____
SRAMWITH
o WAIT STATES
---~
,
'~
,
CPlJIIDY
-+I
r.l12
,
"
~ T30:t
CWEO
CWEf
iAGWf
SRAMWITH
1 WAIT STATE
i
TAGEN
::\-
CPURDY
82C597-9
11-46
~YPRESS
PRELIMINARY
CY81C597
Switching Waveforms (continued)
Cacbe Write Miss. Page Miss Cycle
elK
\~
A[31:211
I
:
:
1331 ~
DWROMKB
133D
-..I
1337
I
I
~
I
MA[11:01
I
1335
~ __~__~__~__-r__-r__-r__-r__~__~__~__~__~'~:S:4:~~~
la14-1
J
I
82C5e7-11
11-48
.?cYPRESS
PRELIMINARY
CY82CS97
Switching Waveforms (continued)
Cache Burst Read Miss (2·1·1·1 Mode), Page Miss, Dirty = 1, DRAM RlWT Cycle (Page 2 of3)
elK
ADS
,
~
I
,
I
I
I
I
, ,
,
•
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
, ,
r.-:-\.
~~~.------------------------~--~~--~--~-----------
________-J.
,
,
MA[11:0]
,
'.
,
ROW ADDRESS
,
,
COWMN ADDRESS 1
I
I
I
I
CAS
, ,
BFID'7
, ,
CRDO
CArIT
iAGWr
DWROMKB
T331
-I
, ,
A[31:2]
'.
TAGA[7:0]
T310
xx
~
TOG~--~~~~~--~--~~--~~--~~~-r--Ti~~~~~-r~~~~~~,
TOGA3~~-,~~__~~__~__~~__~__~~__~__~~~~__~~__~~~~~~
B2C597~13
11-50
d?~
.;'CYPRESS
PRELIMINARY
CY82C597
Switching Waveforms (continued)
Cache Burst Read Miss (2·1·1·1 Mode), Page Hit, Dirty = 0, DRAM RIWT Cycle (Page 1 of2)
elK
,
MA[11:0]
, , ,
,
COLUMN ADDRESS 2
,
,
COLW;N ADDRE'S8 1
T347.
DWROMKB
A[31:2]
TAGA[7:0]
TOGA2
TOGA3
11-52
PRELIMINARY
CY82C597
Switching Waveforms (continued)
VESNPCI Master Read Memory Cycle with Inquiry Hit and Dirty (HITM=O) (Part 1 of 2)
ClK
HOLD
~I
HlDA
,MASTER
ADS
EAOS
,
CPU
~~~~:~~~~~~~:~~~~~--~~~~-
:U
FIlm
1,
BRD'i'
r-~--~--~--~--~
:L:.J
CWEO
'LJ
CWE1
rnmo
CRD1
:\
'/
,.
,
,
-,
CPU INQUIRY WRITE-BACK CYCLE.
1 WAIT STATE, BURST WRITE.
82C597-17
11-54
PRELIMINARY
.rcYPRESS
CY82CS97
Switching Waveforms (continued)
DMA/Master Read Memory Cyclu
ClK
HlDA
'(CACHE MISS)
,T371
MA[ll:0]
T361
,COLUMN ADDRESS
ROW ADDRESS
,.
T363~ t
r:
.,--_ _ _ _ _ _ _ _ _ _
T36
....
'(CACHE HIT) ,
CRUD
(A2=O)
CF!lIT (A2= 1)
82C597·19
11-56
•
~YPRESS
PRELIMINARY
CY82C597
Switching Waveforms (continued)
Numerical Coprocessor Interface TIming
_
T500
IRQ
WTINTR
CNTL
(NPRST OR lOW PORT FOH)
T505
82C597-21
11-58
~YPRESS
PRELIMINARY
CY82CS97
Switching Waveforms (continued)
Hardwllre Power-Down
elK
______________________________
'T603'~1'
~,~~:~--~-r~
NOTE30 I
~',
TOO,3
-I,
~
I
NO'rE31 '
T604
NOTE 32
,
T604
--I
B2C597-22
Ordering Information
Ordering Code
CY82C597-NC
Package
Name
N160
Operating
Range
Package'iYpe
160-Lead Plastic Quad FJatpack
Commercial
Notes:
30. The assertion of SWWCLK caused by the stand-by timer reaching its
terminal count with no detected events.
31. The assertion of STOPCLK caused by the suspend timer reaching its
terminal count with no detected events.
32. SLOWCLK and STOPCLK deassertion caused by the detection of
one of the monitored events.
Document #: 38-00411
11-60
~';;;K,
PRELIMINARY
'¥!!!IIIf' CYPRESS
CY82C599
Pin Configurations
PQFP
ThpView
~~~~~~
'"
... .,
. ~ I~ ~ I~ I~ f ~ In II~ I~ I~ I~ "'~H
~~
c'"
<
~ iii<
gj
!i!
gj
IEl
11 gJ
c
c c
z '" <
< '"
<
0
c
[:;;
S
c
< < ~
R!
c
<
~
0
§i
160 159158157156155154153152151150 149148147146145144 143142 141140 139138 137138 135134133132 131130 129128 127 126 125124 123122 121
GND
120
ADS1
CBElJ
119
REllO
AD6
118
IIEOi
AD5
117
RE02
AD4
116
AD3
115
AD2
114
llI'ITii
llIEV:
The CY82C599 will automatically de-assert LDEV if CPURDY
goes active (the transaction was claimed and completed by a
VESA device). If the target is a VESA device (in 'unknown'
space), it asserts LDEV and claims the transaction. Since LDEV
from the CY82C599 and the VESA devices are ANDed
together, the CY82C59617 will only pass the cycle to the ISA bus
if neither VESA or PCI claims the transaction. Since VESA and
PCI agents share the same priority, two memory devices (one on
VESA and the other PCI) should never share the same address
space. Doing so will cause a clash condition by having both
devices claim the same transaction.
6.2 CPU Bus Master Priority-IIO Accesses
The highest priority CPU bus master 110 transaction is
PCIJVESA space. These two types of devices 110 address spaces
are considered to have the same priority. The CY82C599 will
claim I/O transactions to PCI address space by asserting LDEY.
The transaction is allowed to proceed norm31ly, and is terminated
on the CPU bus with CPURDY from the CY82C599. If the
transaction is to VESA 110 address s~e, the VESA target will
claim the transaction by asserting LD .
The second priority CPU bus master access to 110 space is when
the target resides in ISA space. The CY82C599 will monitor, but
not participated in CPU bus master transactions to ISA space.
If the address is not mapped to PCINESA or ISA space, then it
is considered as 'unknown'. The CY82C599 will claim all 110
transactions to 'unknown' address space on the CPU bus by
asserting LDEV and will immediately initiate a PCI cycle. If the
target is a PCI device (in 'unknown' space), the transaction is
claimed by the PCI device and proceeds norma~with the
CY82C599 terminating the transaction by assertingURDY to
the CPU. If the PCI transaction goes unclaimed, the CY82C599
de-asserts r::I>EV: The CY82C599 will automatically de-assert
LDEV if CPURDY goes active (the transaction was claimed and
completed by a VESA device). If the target is a VESA device (in
'unknown' ·space), it asserts LDEV and claims the transaction.
Since LDEV from the CY82C599 and the VESA devices are
CY82C599
ANDed together, the CY82C59617 will only pass the cycle to the
ISA bus if neither VESA or PCI claims the transaction. Since
VESA and PCI agents share the same priority, two I/O devices
(one on VESA and the other PCI) should never share the same
address space. Doing so will cause a clash condition by having
both devices claim the same transaction.
6.3 PCI Master Priority-Memory Accesses
The highest priority PCI master memory transaction is an access
to Local memory. During such transactions the CY82C599 will
claim the CPU bus as quickly as possible by asserting a hold
request to the CPU. PCI bus ownership is not be granted until a
hold acknowledge is received back from the CPU. Once bus
ownership has been established, the transaction proceeds
normally with the CY82C599 as the CPU bus master.
The second priority PCI master memory transaction is to PCI
memory located on another PCI card. During these transactions
the CY82C599 monitors, but does not participate in the
transaction. In addition, the CY82C599 will hold the CPU bus
during the entire transaction.
The third priority PCI master memory transaction is to
ISANESA address space. During these types of transfers, the
CY82C599 will claim the ISANESA bus as soon as possible and
initiate an ISANESA cycle.
If the address is not mapped to PCIJVESA or lSA space, then it
is considered as 'unknown'. PCI agents are given the first
opportunity to claim PCI master accesses to 'unknown' memory
space. The CY82C599 will wait for a PCI agent to claim the
transaction by monitoring DE\1'SEL. If the transaction goes
unclaimed on the PCI bus, the CY82C599 will automatically start
a CPU bus cycle. If the transaction goes unclaimed on the CPU
bus, the 82C596/7 will automatically pass the transaction to the
ISAbus.
6.4 PCI Master Priority-IIO Accesses
The highest priority PCI master 110 access is to PCI address
space. During these transactions the CY82C599 monitors, but
does not participate in the transaction. In addition, the CPU bus
is 4eld during the entire transaction.
The second priority PCI master 110 transaction is to the ISA bus.
During such transactions, the CY82C599 will claim the
transaction by asserting DEVSEL and behave as the PCI target.
The CY82C599 will also start a CPU bus as soon as possible and
initiate an lSANESA cycle.
If the address is not mapped to PCIJVESA or ISA space, then it
is considered as 'unknown'. PCI agents are given the first
opportunity to claim PCI master accesses to 'unknown' 110 space.
The CY82C599 will wait for a PCI agent to claim the transaction
by monitoring the DEVSEL If the transaction goes unclaimed
on the PCI bus, the CY82C599 will automatically start a CPU
bus cycle. If the transaction goes unclaimed on the CPU bus, the
82C59617 will automatically pass the transaction to the ISA bus.
7.0 Levell Write-Back Cache Support
The CY82C599 also provides for chipsets that suJrtMt Level 1
protocol
write-back cache. The CY82C599 adheres to the H
required to maintain cache coherency. When HITM is asserted,
the CPU has detected a hit to a modified line in the Level 1
cache. In order to allow the CPU to write-back the modified line,
the CY82C599 de-asserts the HOLD request to the CPU. The
CPU then proceeds to write the modified line to DRAM and L2
cache (if a L2 cache hit is detected). The CY82C599
immediately requests another HOLD to the CPU so the initial
transaction can continue.
11-66
~YPRESS
PRELIMINARY
10.0 Control Registers
This section summarizes the registers in the CY82C599.
The on-chip registers are accessed via I/O sequence 22H and
23H. Each register is selected by writing a byte containing the
register address index to I/O address 22H. A subsequent byte
read/write to 110 address 23H will modify/read-out the contents
of the selected register.
The CY82C599 provides five groups of registers :
Memory address space configuration registers
(except PC/AT high memory)
110 address space configuration registers
Power down configuration registers
State machine configuration registers
PC/AT high memory address space configuration
registers
The Local DRAM Address Configuration Registers are used to
establish the boundary of the Local DRAM in the system. Index
20H and 21H are used to specify the ending address of on-board
DRAMs. Index 22H to 27H are the configuration registers for
Index20H
Bit
CY82C599
Memory Blocks 0 and 1. They contain the base address of each
memory block, the block sizes, and the mapping selection for
each block: Local DRAM region, PCI region or lSA region. It is
best to specify all Non-Local DRAM memory areas below
16Mbytes as ISA region and remap alI other Non-Local DRAM
memory areas above 2 Gbytes as the PCI region.
I/O Block Configuration Registers are used to specify the base
address, block size, and function select for the user selectable 110
blocks. The. pre-defined I/O blocks are simply enabled or
disabled.
Power Down Configuration Registers allow various hardware
events to be monitored in order to invoke or come out of power
down mode.
State Machine configuration registers control features of the PCI
and CPU bus State Machines. These features include the
number of wait states, and arbitration priority of both State
Machines.
PC/AT High Memory Address Space Configuration Registers are
used to specify the memory regions from OOOAOOOOH to
OOOFFFFFH (blocks A, B, C, D, E, and F). These bits are used
with CY82C59167 to provide shadowing in a PC/AT system.
Function
Hardware
Default
Recommended
BIOS power-on
setting
7:4
Reserved
0000
0000
3:0
Local DRAM Ending Address: lI.'Yi : A!.
:I
:I
:1
'I
(CPU MEMORY
'I
~-1-1-; MO~E)
11-110
CY82C599
~YPRESS
PRELIMINARY
CY82C599
Switching Waveforms (continued)
PCI Master Post Write to CPU, PCI Side Buffer Available
'5
10
'15
PCICLK
FIlAm:
TF!O'i'
UE\7SE[
TFIDY/STOP ,
ADDRESS=1WS,
DATA=1WS
ADDRESS=1WS
DATA=OWS
ADDRESS=OWS
DATA=1WS
,
,
ADDRESS=OWS
DATA=OWS
82C599-2-22
Note: CPU side same as 486 type CPU write cycle
11-112
~YPRESS
PRELIMINARY
CY82C599
Switching Waveforms (continued)
Switching Waveforms (continued)
Pel Master Subtractive Decode "DEVSEIl' Timing
pel Master Subtractive Decode "DEVSEIl' Timing
'5
PCICLK
~--:--~~.....,l~:--:-~:~
---'_:-+-.1:0=
(SUB-DECODE=6PCICLK)
(SUB-DECODE=5PCICLK)
82C599-2-24
82C599-2-25
Switching Waveforms (continued)
Switching Waveforms (continued)·
Pel Master Subtractive Decode "DEVSEIl' Timing
PCI Master Subtractive Decode "DEVSEIl' Timing
(SUB-DECODE=4PCICLK)
(SUB-DECODE=3PCICLK)
82C599-2-26
11-114
82C599-2-27
~YPRESS
Military Information
Military Overview.
Section Contents
Page Number
~:::!:~~::::~:~~~~~:~~~~:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: ~E~
lb~YPRESS ======M;;;;;i;;;;;li;;;;;ta;;;;;ry~P;;;;;r;;;;;o;;;;;d;;;;;u;;;;;ct;;;;;S;;;;;e;;;;;l;;;;;ec;;;;;t;;;;;or=G;;;;;u;;;;;id;;;;;e=
Static RAMs
Size
64
64
64
64
lK
1K
lK
lK
lK
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
8K
8K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
32K
32K
32K
32K
32K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
Organization
16x4-lnverting
16x4-Non-Inverting
16 x 4-lriverting
16 x 4-Non-Invetting
256 x 4-10KllOKH ECL
256x4
256x4
256x4
256x4
4Kxl-CSPower-Down
4Kx l-CSPower-Down
4Kxl-CSPower-Down
4Kxl-CSPower-Down
lKx4-10KlI0KHECL
lKx4-CSPower-Down
lKx 4-CS Power-Down
lKx4
lKx4
lKx 4-Separate I/O
lKx8-DualPort
lKx8-Dual-Port Slave
4Kx4-CSECL
2Kx 8-CS Power-Down
2Kx8-CSPower-Down
2Kx8-CSPower-Down
16Kx l-CSPower-Down
4Kx 4-CS Power-Down
4Kx4
4Kx4-0utputEnable
4Kx4-Separatel/0
4Kx4--&lparateI/0,Power-Down
2Kx8-Dual-Port
2Kx8-Dual-Port Slave
4Kx8-Dual-Port
4Kx8-Dual-Port
4Kx 8-Dual-Port Semaphores
4Kx 8-Dual-Port Semaphores
Int,Busy
4Kx 9-Dual-Port Semaphores
Int,Busy
8Kx8-CSPower-Down
8Kx8-CSPower-Down
8Kx8-CSPower-Down
8Kx 8-CS Power-Down
8Kx8-CSPower-Down
8Kx8-CSPower-Down
8Kx8-CS Power-Down
16Kx4-CS Power-Down
16Kx4-CS Power-Down
16Kx4-CSPower-Down
16Kx4-CSPower-Down
16Kx 4-0utput Enable
16Kx 4-Output Enable
16Kx 4-Separate I/O, T-write
16Kx4-Separatel/0
16Kx4-Separate I/O, T-write
16Kx4-Separatel/0
64Kx 1-CS Power-Down
8Kx 8-Dual-Port Semaphores
Int,Busy
8Kx 9-Dual-Port Semaphores
Int,Busy
Pins
(DIP)
Part Number
16
16
16
16
24
22
24S
22
22
18
18
18
18
24
18
18
18
18
24S
48
48
28
24S
24
24S
20
20
20
22S
24S
24S
48
48
48
52
52
68
CY7C189
CY7C190
CY27S03/A
CY27S07/A
CYlOE422L
CY7C122
CY7CI23
CY9122191L22
CY93422A193L422A
CY7C147
CY2147
CY7C147
CY2147
CYI0E474L
CY7C148
CY2148
CY7C149
CY2149
CY7C150
CY7C130/31
CY7C140/41
CYI0E484L
CY7CI28A
CY6116N7A
CY7C128A
CY7C167A
CY7C168A
CY7C169A
CY7C170A
CY7CI71A
CY7Cl72A
CY7C132136
CY7C142/46
CY7B134
CY7B135
CY7B1342
CY7B138
68
CY7B139
28S
28S
28S
28S
28
28
28
22S
228
22S
24S
24S
24S
28S
28S
28S
28S
22S
68
CY7C185A
CY7C185A
CY7C185A
CY7B185
CY7C186A
CY7C186A
CY7C186A
CY7CI64A
CY7CI64A
CY7BI64
CY7C166A
CY7C166A
CY7B166
CY7C161A
CY7CI62A
CY7B161
CY7B162
CY7C187A
CY7B144
68
CY7B145
JAN/SMD
Number
5962-89694
5962-88594
5962-90696
5962-88594
5962-88594
M385101289
M385101289
5962-88587
5962-88587
5962-91518
M3851O/289
M385101289
5962-88588
5962-86875
5962-86875
5962-89690
5962-89690
84036
84132
5962-86705
5962-89790
5962-90620
5962-90620
5962-93001
5962-93001
5962-38294
5962-89691
5962-85525
5962-91594
5962-38294
5962-89691
5962-85525
5962-89692
5962-86859
5962-91593
5962-89892
5962-86859
5962-91593
5962-90594
5962-89712
5962-92172
5962-86015
12-2
IccflsoflcCDR
(mA@ns)
883
Availability
tAA=25
tAA=25
tAA=25,35
tAA=25,35
tAA =5, 7
tAA=25,35
tAA = 10, 12, 15
tAA=35,45
tAA = 45,55,60,75
tAA =35,45
tAA =45,55
tAA =35,45
tAA =45,55
tAA=5,7
tAA =35,45
tAA =45,55
tAA =35,45
tAA =45,55
tAA = 12, 15,25,35
tAA = 35,45,55
tAA = 35,45,55
tAA =7,10
tAA=20,25
tAA=20,25
tAA = 35,45,55
tAA = 20,25,35,45
tAA = 20,25,35,45
tAA =20,25,35,40
tAA = 20,25,35,45
tAA = 20,25,35,45
tAA = 20,25,35,45
tAA = 35,45,55
tAA =35,45,55
tAA = 25,35
tAA = 25,35
tAA =25,35
tAA =25,35
70@25
70@25
100@35
100@25
150@5n
90@25
150@15
90@45
90@55
110/1O@35
140/25@45
110/1O@35
140!25@45
190@5n
110/10@35
140!25@45
110@35
140@45
100@15
120/40@45
120/40@45
200@10
125@20
125@20
125/40@25
70!20@25
100/?0@25
l00/20@35
120@25
l00!20@25
90@20
170/65@35
120/40@45
280@25
280@25
280@25
280@25
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
tAA = 25,35
280@25
Now
tAA = 20, 25, 35, 45
tAA = 20,25
tAA = 35,45
tAA = 10,12,15
tAA = 20,25,35,45
tAA=20,25
tAA = 35,45,55
tAA=20,25
tAA=35
tAA = 10, 12, 15
tAA=20,25
tAA=35
tAA = 10, 12, 15
tAA = 20,25,35
tAA = 20, 25, 35
tAA '" 12,15
tAA= 12,15
tAA = 20, 25, 35
tAA=25,35
125@20
125@20
100/20/1 @45
145/50@15
125@20
125@20
100/20/1 @45
90@20
70!20/1@35
135/50@15
90@20
70!20/1@35
135/50@15
70!20/1@35
70/2011@35
135/50@15
135/50@15
70/20/l@35
280@25
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
tAA = 25,35
280@25
Now
Speed (ns)
"rcYPRESS ======M;;;;;;i;;;;;;li;;;;;;t3;;;;;;ry;;;;;;;;;;;P;;;;;;r;;;;;;o;;;;;;d;;;;;;u;;;;;;ct;;;;;;S;;;;;;e;;;;;;l;;;;;;ec;;;;;;t;;;;;;or=G;;;;;;u;;;;;;id;;;;;;e=
PROMs (continued)
Organization
Size
256K
256K
256K
256K
256K
256K
256K
256K
512K
512K
512K
512K
1M
16Kx16
32KxB-C8Power-Down
32Kx B-C8 Power-Down
32Kx B-EPROM Pinout
32KxB-EPROMPinout
32Kx 8-EPROM PInout
32KxB-Registered
32KxB-Registered
64Kx B-EPROM Pinout
64KxB-EPROMPin
64KxB-Registered
64Kx B-Registered
128Kx8
Pins
Part Number
44
288
288
28
28
28
288
288
28
28
288
288
32
CY7C276
CY7C271
CY7C271
CY7C274
CY7C274
CY27C256
CY7C277
CY7C277
CY7C286
CY7C286
CY7C287
CY7C287
CY27HOIO
JAN/SMD
Numberll]*
5962-89817(W)
5962-93166(0)
5962-89817(W)
5962-93166(0)
5962-91744(W)
5962-92155(0)
5962-91637(0)
5962-92071(W)
5962-90913(W)
5962-92065(0)
Speed (ns)
tM=25,30,35
tM = 35,45,55
tM=35,45,55
tM = 35,45,55
tM = 35,45,55
tM = 45,55,70,90, 120, 150,200
tSA/CO = 40/20,50/25
tSA/co = 40/20,50/25
tM = 60,70
tM=60,70
tSA/CO = 55/20, 65/25
tSA/CO = 55/20,65/25
tM = 35,45,55,70
IccflsB
(mA@ns)
250@30
130/4O@35
130/4O@55
130/4O@35
130/4O@35
55/20
130@40
130@4O
150@60
150@60
150@65
150@65
85@35
883
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
PLDs
Organization
Pins
Part Number
JAN/SMD
Number ll]·
Speed (ns!MHz)
Icc
(mA@ns/MHz)
883
Availability
5962-92338(0)
5962-88678(W)
5962-88713(0)
5962-89839
5962-91760(0)
5962-91760(0)
5962-87539(W)
5962-87539(W)
5962-88670(0)
5962-88670(0)
M385lO/507(W)
M38510/508(0)
5962-89841(0)
5962-88637(0)
5962-90555(0)
5962-90989(W)
5962-89546(W)
5926-90802(0)
5962-90754(W)
5962-89855(0)
5962-91584(W)
5862-945lO(W)
5962-90611(W)
5962-92158(W)
5962-89468(W)
5962-92062(W)
5962-91344(W)
180@7
70@20
70@2O
130@10
190@10
190@IO
lOO@25
100@2O
100@25
120@15
120@15
120@15
130@10
80@30
100@25
lOO@25
180@40MHz
180@40MHz
2OO@2OMHz
200@20MHz
2OO@24MHz
160@66.6MHz
220@25
225@25
320@30
480@30
320@35
150@100MHz
260@83
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
5962-94688(0)
5962-94689(0)
5962-94713(0)
tpo=7,1O
tpo = 20,30,40
tpo = 20,30,40
tpOIS/CO = 10/IOn
tPOIS/CO = 10/3.6n.s
tpo/s/co = IO/3.6n.s
tpolS/CO = 25/18/15
tPOIS/CO = 20/17/15
tpOIS/CO = 25/18/15
tpOIS/CO = 15/12/10
tPOIS/CO = 15/12/10
tpo/s/co = 15/12/10
tpo/s/CO= 10/6n
tpo/s/co = 20/17/15
tpo/su/co = 20/lO/20
tpoISU/cO=2O/10/20
50, 40, 28 MHz
50, 40, 28 MHz
tpo = 25,30,40
tpo = 25,30,40
tpo = 20,25,30
lMAxs = 66.6,50,83
tpo = 12,20,25,35
tpo = 15,20,25,30,35
tpD = 15,20,25,30,35
tpo = 20,25,30,35,40
tpo = 20,25,30,35
100,83,66 MHz
fMAXltsltco=83MHz/
lO/1O
fMAXlts/tco=83MHz.1818
fMAXftsltco=83MHz.1818
fMAXftsltco=83MHz.1818
iMAx/tsltco=83MfW8/8
fMAX/tsltco=83MHz/
12/12
fMAXltsltco=83MHz/
12/12
fMAXltsltco=83MHz/
12/12
300@83
300@83
370@83
370@83
300(fBD
Now
Now
Now
Now
4Q95
300rrBD
4Q95
300(fBD
2Q95
PAl20
PALC20
PALC20
PALCE20
PLD24
PLD24
PWC24
PLD24
PWC24
PLD24
PLDC24
PLDC24
PLDC24
PWC24
PLDC24
PLDC24
PWC28
PLDC28
PWC28
PLDC28
PLDC28
PLD28
MAX28
MAX40
MAX68
MAX84
MAXlOO
PLDC28
37X-44
16L8, 16R8, 16R6, 16R4
16L8, 16R8, 16R6, 16R4
16L8, 16R8, 16R6, 16R4
16VB-Macrocell
22VIOC-MacroceU
22VIOC-MacroceU
22VIO--MacroceU
22VI0-MacroceU
22VIO--MacroceU
22VIO--MacroceU
22VIO--Macrocell
22VIO--MacroceU
22VlOD-MacroceU
20GIO--Generic
2ORA10--Asynchronous
20RAIO--Asynchronous
7C330--8tate Machine
7C330--State Machine
7C331-Asynchronous
7C331-Asynchronous
7C332-Combinatorial
7C335-8ynchronous
7C344-32 MacroceU
7C343-64 MacroceU
7C342-128 MacroceU
7C341-192 MacroceU
7C346-128 MacroceU
7C361-State Machine
7C371-32 MacroceU
20
20
20
208
248
248
248
248
248
248
248
248
248
248
248
288
288
288
288
28S
288
288
40/44
68
84
84/100
288
44
PAL16XX
PALC16XX
PALC16XX
PALCE16V8
PAL22VIOC
PAL22VPIOC
PALC22VI0
PALC22VlOB
PALC22VI0
PALC22VI0B
PALC22VlOB
PALC22VlOB
PALC22VI0D
PLDC20GlO
PW20RAI0
PW20RAlO
CY7C330
CY7C330
CY7C331
CY7C331
CY7C332
CY7C335
CY7C344/B
CY7C343/B
CY7C342/B
CY7C341/B
CY7C346/B
CY7C361
CY7C371
37X-44
37X-84
37X-84
37X-16O
FLAsH370-
7C372-64 Macrocell
7C373-64 Macrocell
7C374-128 Macrocell
7C375-128 Macrocell
7C376-192 MacroceU
44
84
84
160
160
CY7C372
CY7C373
CY7C374
CY7C375
CY7C376
7C377-192 Macrocell
240
CY7C377
7C378-256 MacroceU
160
CY7C378
24S
160
FLAsH370240
FLAsH370-
5962-94684(0)
160
12-4
.?cYPRESS
;;;;;======M=il=it=ary~P=r=o=d=uc=t=S=e=le=c=to=r=G=u=i=de=
VMEbus Interface Products
Organization
VME Interface Controller
VMEAddressController
64-BitVIC
Slave VME Interface Controller
Bus Interface LoJtic Circuit
Pins
144/160
144/160
144/160
64
64
JAN/SMD
Number
Part Number
5962-92010
5962-92009
VIC068A
VAC068A
VIC64
CY7C960
CY7C964
5962-95511
Part Number
Speed (Mbps)
Icc
(mA)
Speed (MHz)
64
50
250
150
300
64
883
Availability
Now
Now
Now
Now
Now
Communication Products
Organization
HOTLink nansmitter
HOTLinkReceiver
Pins
28
28
160-330
160-330
CY7B923
CY7B933
Icc
(mA)
95
165
Packages
883
Availability
Now
Now
L
L
Modules
Size
1M
2M
4M
4M
Organization
32Kx32SRAM
64Kx32 SRAM
128Kx32SRAM
512Kx8SRAM
Pins
66
60
66
32
Part Number
Packages
Hoo1
HD06
Hoo1
HD12
CYM1828
CYM1830
CYM1838
CYM1466
Speed (ns)
tAA=35,45,55,70
tAA = 35,45,55
tAA = 25,30,35
tAA = 35,45,55,70,85,
toO, 120
Icc
(mA@ns)
200@35
880@35
720@25
350@35
883
Availability
Now
Now
Now
Now
Notes:
The following Cypress faeilites have been granted Level Q (QML) certification by DESC:
~
~
Location
Fab
Fab2
Round Rock, TX
Fab3
Bloomington, MN
Assy/Thst
Bangkok
Bangkok, Thailand
Thst
San Jose
San Jose, CA
All of the above products are available with processing to MIL-STD-883D at a minimum. Many of these products are also available either to SMDs
(Standardized Military Drawings) or to JAN slash sheets.
The speed and power specifications listed above cover the full military temperature range.
Modules are available with MIL-STD-883D components. These modules are assembled and screened to the proposed JEDEC military processing
standard for modules.
W = Windowed Package
o = Opaque Package
HD = Hermetic DIP Module
lOOK ECL devices are available only to extended temperature range.
22S stands for 22-pin 300-mil DIP.
24S stands for 24-pin 300-mil DIP.
28S stands for 28-pin 300-mil DIP.
325 stands for 32-pin 300-mil DIP.
HOTLink is a trademark of Cypress Semiconductor.
12-6
Military Ordering Information
DESC SMD (Standardized Military Drawing) Approvals!!) (continued)
Package!3)
SMDNumber
5962-86846
5962-86846
5962-86846
5962-86846
5962-86846 '
5962-86846
5962-86859
5962-86859
5962-86859
5962-86859
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-86875
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87515
5962-87529
5962-87529
5962-87529
5962-87529
5962 87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
5962-87539
OlVX
012X
02VX
022X
03VX
032X
17LX
17XX
18LX
24YX
03XX
03ZX
04XX
04ZX
llXX
llZX
12XX
12ZX
19XX
19ZX
20XX
20ZX
05KX
05LX
053X
06KX
06LX
063X
07KX
07LX
073X
08JX
08KX
08LX
083X
09JX
09KX
09LX
093X
10JX
10KX
lOLX
103X
llJX
llKX
llLX
113X
12KX
12LX
123X
01LX
013X
02LX
023X
01LX
013X
02LX
023X
03LX
04LX
043X
Cypress(2)
Part Number
CY7C404-lODMB
CY7C404-10LMB
CY7C404-15DMB
CY7C404-15LMB
CY7C404-25DMB
CY7C404-25LMB
CY7CI66AL-35DMB
CY7C166AL-35LMB
CY7CI66A-35DMB
CY7CI64A-35DMB
CY7C130-55DMB
CY7C131-55LMB
CY7C130-45DMB
CY7C131-45LMB
CY7CI40-55DMB
CY7C141-55LMB
CY7C140-45DMB
CY7C141-45LMB
CY7C130-35DMB
CY7C131- 35LMB
CY7C140-35DMB
CY7CI41-35LMB
CY7C261-45TMB
CY7C261-45WMB
CY7C261-450MB
CY7C261-55TMB
CY7C261-55WMB
CY7C261-550MB
CY7C261-35TMB
CY7C261-35WMB
CY7C261-350MB
CY7C264-35WMB
CY7C263-35TMB
CY7C263-35WMB
CY7C263-350MB
CY7C264-45WMB
CY7C263-45TMB
CY7C263-45WMB
CY7C263-450MB
CY7C264-55WMB
CY7C263-55TMB
CY7C263-55WMB
CY7C263- 550MB
CY7C264-25WMB
CY7C263-25TMB
CY7C263-25WMB
CY7C263-250MB
CY7C261-25TMB
CY7C261-25WMB
CY7C261-250MB
CY7C245-45WMB
CY7C245-450MB
CY7C245-35WMB
CY7C245-350MB
PALC22VlO-25WMB
PALC22VlO-250MB
PALC22VlO-30WMB
PALC22VlO-300MB
PALC22VlO-40WMB
PALC22VI0B-20WMB
PALC22VlOB-200MB
Description
lYpe
18.3 DIP
20SLCC
18.3 DIP
20SLCC
18.3 DIP
20SLCC
24.3 DIP
28RTLCC
24.3 DIP
22.3 DIP
48.6 DIP
52LCC
48.6 DIP
52LCC
48.6 DIP
52LCC
48.6 DIP
52LCC
48.6 DIP
52LCC
48.6 DIP
52LCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24.6 DIP
24CP
24.3 DIP
28SLCC
24.6 DIP
24CP
24.3 DIP
28SLCC
24.6 DIP
24CP
24.3 DIP
28SLCC
24.6 DIP
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24.3 DIP
28SLCC
24.3 DIP
28 S,LCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
24.3 DIP
24.3 DIP
28SLCC
D4
L61
D4
L61
D4
L61
D14
L54
D14
DlO
D26
L69
D26
L69
D26
L69
D26
L69
D26
L69
D26
L69
T73
W14
064
T73
W14
064
T73
W14
064
W12
T73
W14
064
W12
T73
W14
064
W12
T73
W14
064
W12
T73
W14
064
T73
W14
064
W14
064
W14
064
W14
064
W14
064
W14
W14
064
12-8
Product
Description
64x5 FIFO
64x5 FIFO
64x5 FIFO
64x5 FIFO
64x5 FIFO
64x5 FIFO
16Kx4 SRAMw/OE
16K x 4 SRAM w/OE
16Kx4SRAMw/OE
16Kx4SRAM
lKx 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lKx 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lK x 8 Dual-Port SRAM
lKx 8 Dual-Port SRAM
8Kx8UVEPROM
8Kx8 UVEPROM
8Kx8UVEPROM
8Kx8UVEPROM
8Kx8UVEPROM
8Kx8 UVEPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8Kx8UVEPROM
8Kx8 UVEPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8Kx8UVEPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8Kx8UVEPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8K x 8 UV EPROM
8Kx8 UVEPROM
8Kx8UVEPROM
8Kx8UVEPROM
8Kx8UVEPROM
2K x 8 Registered UV PROM
2K x 8 Registered UV PROM
2K x 8 Registered UV PROM
2K x 8 Registered UV PROM
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
24-Pin CMOS UV EPLD
Military Ordering Information
DESC SMD (Standardized Military Drawing) Approvals!!! (continued)
Package!3]
SMDNumber
5962 88636
5962-88636
5962-88636
5962-88636
5962-88636
5962-88636
5962-88636
5962-88636
5962-88636
5962 88637
5962-88637
5962-88637
5962-88637
5962-88637
5962 88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962-88662
5962 88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88669
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
5962-88670
03KX
03LX
033X
04KX
04LX
043X
05KX
05LX
053X
OlKX
OlLX
02KX
02LX
023X
03MX
03NX
03UX
03XX
03YX
04MX
04NX
04UX
04XX
04YX
05MX
05NX
05UX
05XX
05YX
06MX
06NX
06UX
06XX
06YX
07NX
07MX
07UX
07YX
08NX
08MX
08UX
08YX
02XX
02YX
02ZX
03XX
03YX
03ZX
04XX
04YX
04ZX
05XX
05YX
05ZX
OlKX
OlLX
013X
02KX
02LX
023X
Cypress[2]
Part Number
CY7C235A-40KMB
CY7C235A -400MB
CY7C235A -40LMB
CY7C235A -30KMB
CY7C235A - 300MB
CY7C235A -30LMB
CY7C235A - 25KMB
CY7C235A-250MB
CY7C235A -25LMB
PLDC20GlO-40KMB
PLDC20GlO-400MB
PLDC20GIO-30KMB
PLDC20GlO-300MB
PLDC20GlO-30LMB
CY7C199-55KMB
CY7C199-550MB
CY7C199-55LMB
CY7C198-550MB
CY7C198-55LMB
CY7C199-45KMB
CY7C199-450MB
CY7C199-45LMB
CY7C198-450MB
CY7C198-45LMB
CY7C199-35KMB
CY7C199-350M.B
CY7C199-35LMB
CY7C198-350MB
CY7C198- 35LMB
CY7C199-25KMB
CY7C199-250MB
CY7C199-25LMB
CY7C198-250MB
CY7C198-25LMB
CY7C199-200MB
CY7C199-20KMB
CY7CI99-20LMB
CY7C198-20LMB
CY7C199-150MB
CY7C199-15KMB
CY7C199-15LMB
CY7CI98-15LMB
CY7C428 650MB
CY7C429-650MB
CY7C429-65LMB
CY7C428-500MB
CY7C429-500MB
CY7C429-50LMB
CY7C428-400MB
CY7C429-400MB
CY7C429-40LMB
CY7C428-300MB
CY7C429-300MB
CY7C429-30LMB
PALC22Vl0-25KMB
PALC22VlO-250MB
PALC22VlO-25LMB
PALC22VlO-30KMB
PALC22VIO-300MB
PALC22VlO-30LMB
Description
1Ype
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
24CP
24.3 DIP
28SLCC
28CP
28.3 DIP
28RLCC
28.6 DIP
32RLCC
28CP
28.3 DIP
28RLCC
28.6 DIP
32RLCC
28CP
28.3 DIP
28RLCC
28.6bIP
32RLCC
28CP
28.3 DIP
28RLCC
28.60IP
32RLCC
28.3 DIP
28CP
28RLCC
32RLCC
28.3 DIP
28CP
28RLCC
32RLCC
28.6 DIP
28.3 DIP
32RLCC
28.6 DIP
28.3 DIP
32RLCC
28.6 DIP
28.3 DIP
32RLCC
28.6 DIP
28.3 DIP
32RLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
K73
014
L64
K73
014
L64
K73
014
L64
K73
014
K73
014
L64
K74
022
L54
016
L55
K74
022
L54
016
L55
K74
022
L54
016
L55
K74
022
L54
016
L55
022
K74
L54
L55
022
K74
L54
L55
016
022
L55
016
022
IS5
016
022
L55
016
022
L55
K73
014
L64
K73
014
L64
12-10
Product
Description
lK x 8 Registered PROM
lK x 8 Registered PROM
lK x 8 Registered PROM
lK x 8 Registered PROM
lK x 8 Registered PROM
lK x 8 Registered PROM
lK x 8 Registered PROM
lK x 8 Registered PROM
lK x 8 Registered PROM
Generic CMOS PLO
Generic CMOS PLD
Generic CMOS PLO
Generic CMOS PLO
Generic CMOS PLO
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx 8 SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
32Kx 8 SRAM
32Kx8SRAM
32Kx8SRAM
32Kx8SRAM
2Kx9FIFO
2Kx9FIFO
2Kx9FIFO
2Kx9 FIFO
2Kx 9 FIFO
2Kx9FIFO
2Kx9FIFO
2Kx 9 FIFO
2Kx 9 FIFO
2Kx 9 FIFO
2Kx9FIFO
2Kx9FIFO
24-Pin CMOS PLD
24-Pin CMOS PLO
24-Pin CMOS PLO
24-Pin CMOS PLO
24-Pin CMOS PLO
24-Pin CMOS PLO
~YPRESS
Military Ordering Information
DESC SMD (Standardized Military Drawing) Approvals!!] (continued)
Package!3]
SMDNumber
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-88735
5962-89468
5962-89468
5962-89468
5962-89468
5962-89468
5962-89468
5962-89468
5962-89468
5962-89468
5962-89468
5962-89468
5962-89468
5962-89484
5962-89484
5962-89484
5962-89484
5962-89484
5962-89484
5962-89517
5962-89517
5962-89523
5962-89523
5962-89523
5962-89523
5926-89523
5926-89523
5926-89523
5926-89523
5962-89524
5962-89524
5962-89524
5962 89537
5962-89537
5962-89537
5962-89537
5962-89537
5962-89537
5962-89537
5962-89537
5962-89537
5962 89538
5962-89538
5962-89538
5962-89538
5962-89538
01KX
OlLX
013X
02KX
02LX
023X
03KX
03LX
033X
04KX
04LX
043X
01XX
OlYX
01ZX
02XX
02YX
02ZX
03XX
03YX
03ZX
04XX
04YX
04ZX
01MXX
01M3X
02MXX
02M3X
03MXX
03M3X
01YX
02YX
01EX
012X
02EX
022X
05EX
052X
06EX
062X
03XX
04XX
05XX
OlUX
OlYX
OlZX
02UX
02YX
02ZX
03UX
03YX
03ZX
01XX
02XX
03UX
03XX
03ZX
Cypress!2]
Part Number
CY7C245-45KMB
CY7C245 -45DMB
CY7C245-45LMB
CY7C245 - 35KMB
CY7C245-35DMB
CY7C245-35LMB
CY7C245A - 35KMB
CY7C245A - 35DMB
CY7C245A - 35LMB
CY7C245A- 2SKMB
CY7C245A-2SDMB
CY7C245A-2SLMB
CY7C342-35RMB
CY7C342-35HMB
CY7C342-35TMB
CY7C342-30RMB
CY7C342-30HMB
CY7C342-30TMB
CY7C342B-2SRMB
CY7C342B-2SHMB
CY7C342B-2STMB
CY7C342B-20RMB
CY7C342B-20HMB
CY7C342B-20TMB
CY7C265 -50WMB
CY7C265-50QMB
CY7C265 - 2SWMB
CY7C265- 2SQMB
CY7C265-15WMB
CY7C265-15QMB
CY7C9101-45LMB
CY7C9101-35LMB
CY7C403-lODMB
CY7C403-lOLMB
CY7C403-15DMB
CY7C403-15LMB
CY7C401-lODMB
CY7C401-10LMB
CY7C401-15DMB
CY7C401-15LMB
CY7C195L-45DMB
CY7C195L-35DMB
CY7C195L-25DMB
CY7C251 65QMB
CY7C2S1-65WMB
CY7C2S1-65TMB
CY7C2S1-55QMR
CY7C2S1-55WMB
CY7C2S1-55TMB
CY7C2S1-45QMB
CY7C2S1-45WMB
CY7C251-45TMB
CY7C2S4-65WMB
CY7C2S4-55WMB
CY7C254-45QMB
CY7C254-45WMB
CY7C2S4-45TMB
Description
'Jype
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
68PGA
68S0J
68QFP
68PGA
68SOJ
68QFP
68PGA
68S0J
68QFP
68PGA
68S0J
68QFP
28CP
28SLCC
28CP
28SLCC
28CP
28SLCC
68SLCC
68SLCC
16.3 DIP
20SLCC
16.3 DIP
20SLCC
16.3 DIP
20SLCC
16.3 DIP
20SLCC
28.3 DIP
28.3 DIP
28.3 DIP
32RLCC
28.3 DIP
28CP
32RLCC
28.3 DIP
28CP
32RLCC
28.3 DIP
28CP
28.6 DIP
28.6 DIP
32RLCC
28.3 DIP
28CP
K73
D14
L64
K73
D14
L64
K73
D14
L64
K73
D14
L64
R68
H81
T91
R68
H81
T91
R68
H81
T91
R68
H81
T91
W22
Q64
W22
Q64
W22
Q64
L81
12-12
LSl
D2
L61
D2
L61
D2
L61
D2
L61
D22
D22
D22
Q55
W22
T74
Q55
W22
T74
Q55
W22
T74
W16
W16
Q55
W16
T74
Product
Description
2K x 8 Registered PROM
2K x 8 Registered PROM
2K x 8 Registered PROM
2K x 8 Registered PROM
2K x 8 Registered PROM
2K x 8 Registered PROM
2K x 8 Registered PROM
2K x 8 Registered PROM
2K x 8 Registered PROM
2Kx 8 Registered PROM
2K x 8 Registered PROM
2K x 8 Registered PROM
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLD
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
16-Bit Slice
16-Bit Slice
64x 4 FIFO
64x4 FIFO
64x 4 FIFO
64x4FIFO
64x 4 FIFO
64x 4 FIFO
64x4FIFO
64x 4 FIFO
64Kx4SRAM
64Kx4SRAM
64Kx4SRAM
16K x 8 UV EPROM
16K x 8 UV EPROM
16K x 8 UV EPROM
16Kx8UVEPROM
16K x 8 UV EPROM
16K x 8 UV EPROM
16Kx8 UVEPROM
16Kx8UVEPROM
16K x 8 UV EPROM
16Kx8 UVEPROM
16K x 8 UV EPROM
16K x 8 UV EPROM
16K x 8 UV EPROM
16K x 8 UV EPROM
~YPRESS
Military Ordering Information
DESC SMD (Standardized Military Drawing) Approvais[l]
(continued)
Package!']
SMDNwnber
5962-89815
5962-89815
5962-89815
5962-89817
5962-89817
5962-89817
5962-89817
5962-89817
5962-89817
5962-89817
5962-89817
5962-89817
5962-89817
5962-89817
5962-89817
5962-89817
5962-89817
5962-89817
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89841
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-89855
5962-89863
596Z-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
5962-89863
03LX
03KX
033X
01XX
01YX
01ZX
02XX
02YX
02ZX
03XX
03YX
03ZX
04UX
04ZX
05UX
05ZX
06UX
06ZX
01KX
01LX
013X
02KX
02LX
023X
03KX
03LX
033X
04KX
04LX
043X
05KX
05LX
053X
06KX
06LX
063X
01MYX
01MZX
01M3X
02MXX
02MYX
02MZX
03MXX
03MYX
03MZX
03M3X
02XX
OZYX
02ZX
03XX
03YX
03ZX
04XX
04YX
04ZX
05XX
05YX
05ZX
06XX
06YX
06ZX
Cypress[2]
Part Number
CY7C245A-18WMB
CY7C245A -18TMB
CY7C245A-18QMB
CY7C271-55WMB
CY7C271-55TMB
CY7C271-55QMB
CY7C271-45WMB
CY7C271-45TMB
CY7C271-45QMB
CY7C271-35WMB
CY7C271-35TMB
CY7C271-35QMB
CY7C274-55WMB
CY7C274-55QMB
CY7C274-45WMB
CY7C274-45QMB
CY7C274-35WMB
CY7C274- 35QMB
pALC22VI0D-30KMB
PALC22VI0D-30DMB
PALC22V1OD-30LMB
PALC22VI0D-20KMB
PALC22VI0D-20DMB
PALC22V10D-20LMB
PALC22VlOD-15KMB
PALC22VI0D-15DMB
PALC22VlOD-15LMB
PALC22VlOD-25KMB
PALC22VI0D-25DMB
PALC22VlOD-25LMB
PALC22VlOD-15KMB
PALC22VI0D-15DMB
PALC22VI0D-15LMB
PALC22VI0D-lOKMB
PALC22V10D-10DMB
PALC22VlOD-I0LMB
CY7C331-40KMB
CY7C331-40YMB
CY7C331-40LMB
CY7C331-30DMB
CY7C331-30KMB
CY7C331-30YMB
CY7C331-25DMB
CY7C331-25KMB
CY7C331-25YMB
CY7C331-25LMB
CY7C420-65DMB
CY7C421-65DMB
CY7C421-65LMB
CY7C420-50DMB
CY7C421-50DMB
CY7C421-50LMB
CY7C420-40DMB
CY7C421-40DMB
CY7C421-40LMB
CY7C420-30DMB
CY7C421-30DMB
CY7C421-30LMB
CY7C420-25DMB
CY7C421-25DMB
CY7C421-25LMB
Description
1YJ>e
24.3 DIP
24CP
28SLCC
28.3 DIP
28CP
32RLCC
28.3 DIP
28CP
32RLCC
28.3 DIP
28CP
32RLCC
28.6 DIP
32RLCC
28.6 DIP
32RLCC
28.6 DIP
32RLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
24CP
24.3 DIP
28SLCC
28CP
28SJCQ
28SLCC
28.3 DIP
28CP
28SJCQ
28.3 DIP
28CP
28SJCQ
28SLCC
28.6 DIP
28.3 DIP
32RLCC
28.6 DIP
28.3 DIP
32RLCC
28.6 DIP
28.3 DIP
32RLCC
28.6 DIP
28.3 DIP
32RLCC
28.6 DIP
28.3 DIP
32RLCC
W14
T73
Q64
W16
T74
Q55
W16
T74
Q55
W22
T74
Q55
W16
Q55
W16
Q55
W16
Q55
K73
DI4
L64
K73
D14
L64
K73
D14
L64
K73
014
L64
K73
014
L64
K73
014
L64
K74
Y64
L64
D22
K74
Y64
D22
K74
Y64
L64
016
D22
L55
D16
D22
L55
D16
D22
L55
016
D22
L55
016
D22
L55
12-14
Product
Description
2Kx8 Registered UVEPROM
2K x 8 Registered UV EPROM
2K x 8 Registered UV EPROM
32K x 8 UV EPROM
32K x 8 UV EPROM
32K x 8 UV EPROM
32K x 8 UV EPROM
32Kx8UVEPROM
32Kx 8 UV EPROM
32Kx 8 UVEPROM
32K x 8 UV EPROM
32Kx8 UV EPROM
32K x 8 UV EPROM
32K x 8 UV EPROM
32K x 8 UV EPROM
32Kx 8 UVEPROM
32K x 8 UV EPROM
32Kx 8 UV EPROM
CMOSEEPLD
CMOSEEPLD
CMOS EE PLD
CMOS EE PLD
CMOSEEPLD
CMOS EE PLD
CMOSEEPLD
CMOSEEPLD
CMOS EE PLD
CMOS EE PLD
CMOS EE PLD
CMOS EE PLD
CMOS EE PLD
CMOSEEPLD
CMOS EE PLD
CMOS EE PLD
CMOSEEPLD
CMOS EE PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
Asynchronous PLD
512x9FIFO
512x9FIFO
512x 9 FIFO
512x 9 FIFO
512x 9 FIFO
512x9FIFO
512x9FIFO
512x9FIFO
512x9 FIFO
512x9 FIFO
512x9FIFO
512x 9 FIFO
512x 9 FIFO
512x 9 FIFO
512x 9 FIFO
Military Ordering Information
_i?cYPRESS
DESC SMD (Standardized Military Drawing) Approvais(1]
(continued)
Package!']
SMDNumber
5962-90715
5962-90715
5962-90715
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90754
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962-90803
5962 90831
5962-90831
5962-90831
5962-90831
5962 90913
5962-90913
5962-90913
5962-90913
5962-90930
5962-90930
5962-90930
5962-90930
5962-90930
5962-90930
5962-90930
5962-90930
5962-90930
5962-90989
5962-90989
5962-90989
5962-90989
5962-90989
5962-91518
5962-91518
5962-91584
5962-91584
5962-91584
5962-91584
5962-91584
06MUX
06MXX
06MZX
01MYX
01MZX
02MYX
02MZX
02M3X
03MXX
03MYX
O3MZX
03M3X
OlMLX
01M3X
02MLX
02M3X
O3MLX
O3M3X
04MLX
04M3X
05MJX
05MLX
05M3X
06MJX
06MLX
06M3X
07MJX
07MLX
07M3X
08MJX
O8MLX
08M3X
01MXX
02MXX
03MXX
04MXX
01MXX
01MYX
02MXX
02MYX
01MXX
01MYX
01M3X
02MXX
02MYX
02M3X
03MXX
03MYX
03M3X
01MLX
02MLX
02M3X
03MLX
03M3X
01MZX
02MZX
01MYX
OlMZX
02MYX
02MZX
02M3X
Cypress!l]
Part Number
CY7C433-30DMB
CY7C432-30DMB
CY7C433-30LMB
CY7C331-40TMB
CY7C331-40HMB
CY7C331-30TMB
CY7C331-30HMB
CY7C331-30QMB
CY7C331-25WMB
CY7C331-25TMB
CY7C331-25HMB
CY7C331-25QMB
CY7C261-55DMB
CY7C261-55LMB
CY7C261-45DMB
CY7C261-45LMB
CY7C261-35DMB
CY7CZ61-35LMB
CY7C261-25DMB
CY7C261-25LMB
CY7CZ64-55DMB
CY7C263-55DMB
CY7C263-55LMB
CY7C264-45DMB
CY7C263-45DMB
CY7C263-45LMB
CY7C264-35DMB
CY7C263-35DMB
CY7C263-35LMB
CY7C264-25DMB
CY7C263-25DMB
CY7C263-25LMB
CY7C269-60DMB
CY7C269-50DMB
CY7C269-25DMB
CY7C269-18DMB
CY7C287 -65WMB
CY7C287-65QMB
CY7C287 -55WMB
CY7C287-55QMB
CY7C269-50WMB
CY7C269-50TMB
CY7C269-50QMB
CY7C269-25WMB
CY7C269-25TMB
CY7C269-25QMB
CY7C269-15WMB
CY7C269-15TMB
CY7CZ69-15QMB
PLDCZORAI0-35WMB
PLDCZORAlO-25WMB
PLQC20RAlO-25QMB
PLDC20RAlO-20WMB
PLDC20RAlO-20QMB
CYI0E474L-7KMB
CYlOE474L-5KMB
CY7C332-25TMB
CY7C332-25HMB
CY7C332-2OTMB
CY7C332-20HMB
CY7C332-20QMB
Description
1Ype
Product
Description
28.3 DIP
28.6 DIP
32RLCC
28CP
28SJCQ
28CP
28SJCQ
28SLCC
28.3 DIP
28CP
28SJCQ
28SLCC
24.3 DIP
28 SLCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
24.6 DIP
24.3 DIP
28SLCC
24.6 DIP
24.3 DIP
28SLCC
24.6 DIP
24.3 DIP
28 SLCC
24.6 DIP
24.3 DIP
28SLCC
28.3 DIP
28.3 DIP
28.3 DIP
28.3 DIP
28.3 DIP
32RLCC
28.3 DIP
32RLCC
28.3 DIP
28CP
28SLCC
28.3 DIP
28CP
28SLCC
28.3 DIP
28CP
28SLCC
24.3 DIP
24.3 DIP
28SLCC
24.3 DIP
28SLCC
24CP
24.CP
28CP
28SJCQ
28CP
28SJCQ
28SLCC
D22
D16
L55
T74
H64
T74
H64
Q64
W22
T74
H64
Q64
D14
L64
D14
L64
D14
L64
D14
L64
D12
D14
L64
D12
D14
L64
D12
D14
L64
D12
D14
L64
D22
D22
D22
D22
W22
Q55
W22
Q55
W22
T74
Q64
W22
T74
Q64
W22
T74
Q64
W14
W14
Q64
W14
Q64
K63
K63
T74
H64
T74
H64
Q64
4Kx9F1FO
4Kx9F1FO
4Kx9F1FO
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
Asynchronous UV PLD
8K x 8 OTP PROM
8K x 8 OTP PROM
8K x 8 OTP PROM
8Kx 8 OTP PROM
8Kx 8 OTP PROM
8K x 8 OTP PROM
8Kx 8 OTP PROM
8K x 8 OTP PROM
8Kx80TPPROM
8K x 8 OTP PROM
8Kx8 OTP PROM
8Kx80TPPROM
8Kx80TPPROM
8Kx80TPPROM
8K x 8 OTP PROM
8Kx8 OTP PROM
8Kx80TPPROM
8K x 80TP PROM
8Kx80TPPROM
8Kx8 OTP PROM
8K x 8 REG OTP PROM
8K x 8 REG OTP PROM
8K x 8 REG OTP PROM
8K x 8 REG OTP PROM
64K x 8 Registered UV PROM
64K x 8 Registered UV PROM
64K x 8 Registered UV PROM
64K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
8K x 8 Registered UV PROM
Asynchronous CMOS UV EPLD
Asynchronous CMOS UV EPLD
Asynchronous CMOS UV EPLD
Asynchronous CMOS UV EPLD
Asynchronous CMOS UV EPLD
lK x 4 ECL SRAM
lK x 4 ECL SRAM
Registered Combinatorial UV EPLD
Registered Combinatorial UV EPLD
Registered Combinatorial UV EPLD
Registered Combinatorial UV EPLD
Re2istered Combinatorial UV EPLD
12-16
Military Ordering Information
DESC SMD (Standardized Military Drawing) Approvals!!! (continued)
Paekage!31
SMDNumber
5962-92213 03MRX
5962-92213 03M2X
5962-92213 05MRX
5962-92213 05M2X
5962-92214 01MRX
5962-92214 01M2X
5962-92214 03MRX
5962-92214 03M2X
5962-92214 05MRX
5962-92214 05M2X
5962-92215 01MRX
5962-92215 01M2X
5962-92215 03MRX
5962-92215 03M2X
5962-92215 05MRX
5962-92215 05M2X
5962-92217 01MRX
5962-92217 01M2X
5962-92217 02MRX
5962-92217 02M2X
5962-92217 03MRX
5962-92217 03M2X
5962 92218 02MRX
5962-92218 02M2X
5962-92218 .04MRX
5962-92218 04M2X
5962-92218 06MRX
5962-92218 06M2X
5962-92219 01MRX
5962-92219 01M2X
5962-92219 02MRX
5962-92219 02M2X
5962-92219 03MRX
5962-92219 03M2X
5962-92221 01MLX
5962-92221 01M3X
5962-92221 02MLX
5962-92221 02M3X
5962-92221 03MLX
5969-92221 03M3X
5962-92222 01MRX
5962-92222 01M2X
5962-92222 03MRX
5962-92222 03M2X
5962-92222 05MRX
5962-92222 05M2X
5962-92223 O1MLX
5962-92223 01M3X
5962-92223 03MLX
5962-92223 03M3X
5962-92223 05MLX
5969-92223 05M3X
5962-92230 01MLX
5962-92230 OlM3X
5962-92230 03MLX
5962-92230 03M3X
5962-92230 05MLX
5969-92230 05M3X
5962-92233 02MEX
5962-92233 02M2X
Cypress!21
Part Number
CY54FCT240ATDMB
CY54FCT240AlLMB
CY54FCf240CTDMB
CY54FCT240ClLMB
CY54FCf245TDMB
CY54FCT245TLMB
CY54FCT245ATDMB
CY54FCf245AlLMB
CY54FCT245CTDMB
CY54FCT245CTLMB
CY54FCT273TDMB
CY54FCT273lLMB
CY54FCT273ATDMB
CY54FCT273ATLMB
CY54FCT273CTDMB
CY54FCT273CTLMB
CY54FCT373TDMB
CY54FCT373lLMB
CY54FCT373ATDMB
CY54FCT373ATLMB
CY54FCT373CTDMB
CY54FCT373CTLMB
CY54FCT374TDMB
CY54FCT374lLMB
CY54FCT374ATDMB
CY54FCT374ATLMB
CY54FCT374CTDMB
CY54FCT374ClLMB
CY54FCT377TDMB
CY54FCT3771LMB
CY54FCT377ATDMB
CY54FCT377ATLMB
CY54FCT377CTDMB
CY54FCT377ClLMB
CY54FCT543TDMB
CY54FCT543lLMB
CY54FCT543ATDMB
CY54FCT543AlLMB
CY54FCT543CTDMB
CY54FCT543ClLMB
CY54FCT574TDMB
CY54FCT574lLMB
CY54FCT574ATDMB
CY54FCT574AlLMB
CY54FCT574CTDMB
CY54FCT574ClLMB
CY54FCT646TDMB
CY54FCT646lLMB
CY54FCT646ATDMB
CY54FCT646ATLMB
CY54FCT646CTDMB
CY54FCT646CTLMB
CY54FCT82SATDMB
CY54FCT82SAlLMB
CY54FCT82SBTDMB
CY54FCT82SBTLMB
CY54FCT825CTDMB
CY54FCT82SCTLMB
CY54FCT138TDMB
CY54FCT138lLMB
Description
1YJIe
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
20.3 DIP
20SLCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
24.3 DIP
28SLCC
16.3 DIP
20SLCC
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D6
L61
D14
L64
014
L41
D14
L64
D6
L61
D6
L61
D6
L61
12-18
D14
L64
014
L41
014
L64
D14
L64
D14
L41
D14
L64
D2
L61
Product
Description
Octal Buffer/Driver I
Octal Buffer/Driver I
Octal Buffer/Driver I
Octal Buffer/Driver I
Octal Thanceiver
Octal Thanceiver
Octal Thanceiver
Octal Thanceiver
Octal Thanceiver
Octal Thanceiver
Octal D Flip-Flops
Octal D Flip-Flops
Octal D Flip-Flops
Octal D Flip-Flops
Octal D Flip-Flops
Octal D Flip-Flops
Octal Transparent Latch
Octal Thansparent Latch
Octal Thansparent Latch
Octal Thansparent Latch
Octal Thansparent Latch
Octal Thansparent Latch
Octal D Flip-Flop W/OE
Octal D Flip-Flop W/OE
Octal D Flip-Flop W/OE
Octal D Flip-Flop W/OE
Octal D Flip-Flop W/OE
Octal D Flip-Flop W/OE
Octal D Flip-Flop W/CE
Octal D Flip-Flop W/CE
Octal D Flip-Flop W/CE
Octal D Flip-Flop W/CE
Octal D Flip-Flop W/CE
Octal D Flip-Flop W/CE
Octal Thanceiver/Reg
Octal Thanceiver/Reg
Octal Thanceiver/Reg
Octal Thanceiver/Reg
Octal Thanceiver/Reg
Octal Thanceiver!Reg
Octal D Register
Octal D Register
Octal D Register
Octal D Register
Octal D Register
Octal D Register
Octal Reg Thanceiver
Octal Reg Thanceiver
Octal Reg Thanceiver
Octal Reg Thanceiver
Octal Reg Thanceiver
Octal Reg Thanceiver
Octal Register W/OE
Octal Register W/OE
Octal Register W/OE
Octal Register W/OE
Octal Register W/OE
Octal Register W/OE
1-of-8 Decoder
1-of-8 Decoder
~YPRESS
Military Ordering Information
DESC SMD (Standardized Military Drawing) Approvals[l) (continued)
Package l3)
SMDNumber
5962 93112
5962-93124
5962-93124
5962-93124
5962-93124
5962-93124
5%2-93124
5962-93144
5962-93144
5962-93144
5962-93144
5962 93152
5962-93152
5962-93152
5962-93152
5962-93152
5962-93152
5962-93166
5962-93166
5962-93166
5962-93173
5962-93173
5962-93173
5962-93173
5962-93173
5962-93173
5962-93225
5962-93225
5962-93225
5962-93225
5962-93225
5962-93225
5962-93225
5962-93225
5962-94510
5962-94510
5962-94510
5962-94510
5962-94510
5962-94510
5962-94510
5962-94510
5962-94510
5962-94522
01MXX
01MXX
01MYX
02MXX
02MYX
03MXX
03MYX
01MZX
01MUX
02MZX
02MUX
01MXX
01MYX
02MXX
02MYX
03MXX
03MYX
01MXX
02MXX
03MXX
01MXX
01MYX
02MXX
02MYX
03MXX
03MYX
01MXX
01MYX
02MXX
02MYX
03MXX
03MYX
04MXX
04MYX
01MXX
01MYX
OlMZX
02MXX
02MYX
02MZX
03MXX
03MYX
03MZX
01MXX
Cypress(2)
Part Number
Description
1Ype
CY7B992-7IMB
,CY7C453-300MB
CY7C453-30IMB
CY7C453-200MB
CY7C453-20LMB
CY7C453-140MB
CY7C453-14LMB
CY7C346- 35RMB
CY7C346-35HMB
CY7C346-30RMB
CY7C346-30HMB
CY7C464-400MB
CY7C464-40LMB
CY7C464-25DMB
CY7C464-25LMB
CY7C464-20DMB
CY7C464-20LMB
CY7C271-55DMB
CY7C271-45DMB
CY7C271-35DMB
CY7C451-30DMB
CY7C451-30LMB
CY7C451-20DMB
CY7C451-20LMB
CY7C451-140MB
CY7C451-14IMB
CY7CI96-45DMB
CY7CI96-45LMB
CY7C196-350MB
CY7CI96-35LMB
CY7CI96-250MB
CY7CI96-25LMB
CY7C196-200MB
CY7CI96-20LMB
CY7C335-50WMB
CY7C335-50HMB
CY7C335-50QMB
CY7C335-66WMB
CY7C335-66HMB
CY7C335-66QMB
CY7C335 -83WMB
CY7C335-83HMB
CY7C335-83QMB
CY7B991-7LMB
32RLCC
32.3 DIP
32RLCC
32.3 DIP
32RLCC
32.3 DIP
32RLCC
l00PGA
84SJCQ
l00PGA
84SJCQ
28.6 DIP
32RLCC
28.6 DIP
32RLCC
28.6 DIP
32RLCC
28.3 DIP
28.3 DIP
28.3 DIP
32.3 DIP
32RLCC
32.3 DIP
32RLCC
32.3 DIP
32RLCC
28.3 DIP
28RLCC
28.3 DIP
28RLCC
28.3 DIP
28RLCC
28.3 DIP
28RLCC
28.3 DIP
28SJCQ
28S LCC
28.3 DIP
28SJCQ
28SLCC
28.3 DIP
28SJCQ
28SLCC
32RLCC
02
032
L55
032
L55
032
L55
Rl00
H84
Rl00
H84
TBD
L55
TBD
L55
TBD
L55
D22
022
D22
032
L55
032
L55
032
L55
022
L54
D22
L54
D22
L54
D22
L54
W22
H64
Q64
W22
H64
Q64
W22
H64
Q64
L55
Product
Description
Prog Skew Clock Buffer
2Kx 9 Clocked FIFO
2K x 9 Clocked FIFO
2K x 9 Clocked FIFO
2Kx 9 Clocked FIFO
2K x 9 Clocked FIFO
2Kx 9 Clocked FIFO
128-Macrocell UV EPLD
128-Macrocell UV EPLD
128-Macrocell UV EPLO
128-Macrocell UV EPLD
32KX 9 FIFO
32KX9F1FO
32KX 9 FIFO
32KX 9 FIFO
32KX9FIFO
32KX 9 FIFO
32Kx 8 OTP PROM
32Kx 8 OTP PROM
32K x 8 OTP PROM
512 x 9 Clocked FIFO
512 x 9 Clocked FIFO
512 x 9 Clocked FIFO
512 x 9 Clocked FIFO
512 x 9 Clocked FIFO
512 x 9 Clocked FIFO
64Kx4SRAMw/OE
64K x 4 SRAM w/OE
64Kx4SRAMw/OE
64Kx4 SRAMw/OE
64Kx4SRAMw/OE
64Kx4SRAMw/OE
64K x 4 SRAM w/OE
64Kx4SRAMw/OE
Synchronous UV EPLO
Synchronous UV EPLO
Synchronous UV EPLO
Synchronous UV EPLO
Synchronous UV EPLD
Synchronous UV EPLD
Synchronous UV EPLO
Synchronous UV EPLD
Synchronous UV EPLD
Prog Skew Clock Buffer
Notes:
1. Devices listed have been approved by OESC for the SMD
indicated as of the date of publication. Contact your local Cypress
representative, or the Cypress SMD Hotline at 408/943-2716, for
the latest update.
2. Use the SMD part number as the ordering code.
3. Package:
SMD Hotline: 408/943-2716
12-20
24.3 DIP = 24-pin 0.300" DIP;
24.6 DIP = 24-pin 0.600" DIP;
28 R LCC = 28 terminal rectan!!"lar LCC,
S = Square LCC, TLCC = Thm LCC
24 CP = 24-pin ceramic f1atpack (Configuration 1);
FP = brazed f1alpack;
PGA = Pin Grid Array.
Military Ordering Information
SMD Ordering Information
5962-XXXXX 01 -
L[L
LEAD FINISH
A
B
C
X
.
= Solder Dip
= TinPlate
= Gold
= Don't Care (The letter "X" will not be marked on the device, but will be
replaced with the actual lead finish designation.)
PACKAGE TYPE (Not a complete list)
V = 18-pin 0.300 DIP
J =
R = 20-pin 0.300 DIP
Q =
S = ZO-pin Cerpack
K =
2 =
W = 22-pin 0.400 DIP
3 =
L = 24-pin 0.300 DIP
24-pin 0.600 DIP
40-pin 0.600 DIP
24-pin Cerpack
20-pin SQ LCC
28-pin SQ LCC
X, Y,Z, U, T, M,N and 4, 5,6, 7, 8, 9 = Non-dedicatedpackage designations
and will vary per drawing.
1..-_ _ _ DEVICE CLASS DESIGNATOR
No character = Old (Pre March 1990) SMD
M
= New "One Part-One Part Number" System SMD, Class B
'-------DEVICE TYPE
'----------DRAWING NUMBER
L------------DRAWINGPREFIX
5962 = Federal Stock Class (FSC) for microcircuits. Pre-1985 drawings do
not have this prefix.
Cypress Military Marking Information
Manufacturer's identification:
Cypress Logo, CYPRESS, CYP, and CY are trademarks of Cypress Semiconductor Corporation.
Manufacturer's designating symbol or CAGE CODE:
Designating symbol = CETK or ETK
CAGE CODEIFSCM Number = 65786
Country of origin:
USA = United States of America
THA = Thailand
12-22
~
Military Ordering Information
~,CYPRESS
The codes for module products follow the the format below.
PREFIX
I CYM I
DEVICE
rt42ii1
SUFFIX
I HD -25 MB I
PROCESSING
B = MILITARY PROCESSING
= STANDARD
TEMPERATURE RANGE
M = -55°C TO 125°C
SPEED
CONFIGURATION
D = DUAL-IN-LINE
G = PIN GRID ARRAY
TYPE
H= HERMETIC
Cypress FSCM #65786
12-24
~YPRESS
Quality and Reliability
Section Contents
Quality, Reliability, and Process Flows
Page Number
Thpe and Reel Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-1
.............................................................................. 13-16
Quality, Reliability, and Process Flows
QYPRESS
'Thble 1. Cypress Commercial and Industrial Product Screening F1ows-Components
Product Thmperature Ranges
Screen
MIL-STD-883 Method
Commercial O°C to +70°C; Industrial -40°C to +8S o C
Levell
Level 2
Plastic
Hermetic
Plastic
Hermetic
Visual/Mechanical
_ Internal Visual
2010
- Hermeticity
- Fine Leak
- Gross Leak
1014, CondAorB(sample) Does Not Apply
Does Not Apply
1014, CondC
O.4%AQL
100%
O.4%AQL
100%
LTPD =5
100%
Does Not Apply
Does Not Apply
LTPD =5
100%
Does Not Apply
Does Not Apply
Does Not Apply
Does Not Apply
Does Not Apply
Does Not Apply
100%
100%[1]
100%
100%[1]
Does Not Apply
Does Not Apply
100%
5% (max)[2]
100%
5% (max)[2]
Not Performed
Not Performed
100%[1]
100%[1]
100%
100%
100%
100%
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Bum-in
- Pre-Burn-in Electrical
-Bum-in
- Post-Burn-in Electrical
• Percent Defective
Allowable (PDA)
Final Electrical
_ Static (DC), Functiollal,
andSwitching(AC) Thsts
Per Device Specification
Per Cypress Specification
Per Device Specification
Per Device Specification
1. At 25 ° C and Power
Supplies Extremes
2. At Hot Thmperature and
Power Supply Extremes
Cypress Quality
Lot Acceptance
2009
Cypress Method 17-00064
- External Visual
_ Final Electrical
Conformance
'Thble 2. Cypress Commercial and Industrial Product Screening Flows-Modules
Product Thmperature Ranges
Screen
Bum-in
- Pre-Bum-in Electrical
_Bum-in
- Post-Burn-in Electrical
- Percent Defective
Allowable (PDA)
Final Electrical
- Static (DC), Functional,
and SWltchmg (AC) Tests
MIL-STD-883 Method
Commercial O°C to +70 o C; Industrial -40°C to +8S o C
Levell
Level 2
Per Device Specification
1015
Does Not Apply
Does Not Apply
Per Device Specification
Does Not Apply
Does Not Apply
Per Device Specification
1. At 25°C and Power
Supply Extremes
2. At Hot Temperature and
Power Supply Extremes
100%
100%
100%
15%
Not Performed
100%
100%
100%
Cypress Quality
Lot Acceptance
2009
Per Cypress Module Specification Per Cypress Module Specification
- External Visual
Cypress Method 17-00064
Note 3
Note 3
- Final Electrical
Conformance
Notes:
1. Bum-in is performed as a standard for 12 hours at 150°C.
3. Lot acceptance testing is performed on evel)' lot. AOQL( the Average
Outgoing Quality Level) for 1994 was < 100 PPM.
2. Electrical Thst is performed after bum-in. Results of this are used
to determine PDA percentage.
13-2
Quality, Reliability, and Process Flows
Table 4. Group A Test Descriptions
Sub·
group
Description
Group B testing is performed for each inspection lot. An inspection lot is defined as a group of material of the same device type,
package type and lead finish built within a sixweek seal period and
submitted to Group B testing at the same time.
Sample Size/Accept No.
Components Modules[7]
1
Static Tests at 25°C
116/0
116/0
2
Static Thsts at
Maximum Rated
Operating Thmperature
116/0
116/0
3
Static Thsts at
Minimum Rated
Operating Thmperatnre
116/0
116/0
4
Dynamic Thsts at 25°C
116/0
116/0
5
Dynamic Tests at
Maximum Rated
Operating Temperature
116/0
116/0
6
Dynamic Thsts at
Minimum Rated
Operating Thmperature
116/0
116/0
Table 6. Group C Quality'Iests
Subgroup
LTPD
Description
Steady State Life Thst,
End-Point Electricals,
Method 1005, Cond D
1
7
Functional Tests at 25 ° C
116/0
116/0
Functional Thsts at
Maximum Temperature
116/0
116/0
8B
Functional Tests at
Minimum Temperature
116/0
116/0
Subgroup
1
Physical Dimensions,
Method 2016
2
Switching Thsts at 25 ° C
116/0
116/0
10
Switching Thsts at
Maximum Temperature
116/0
116/0
11
Switching Thsts at
Minimum Temperature
116/0
116/0
Table 5. Group B Quality Tests
2
3
5
Description
Resistance to Solvents,
Method 2015
Solderability,
Method 2003[8]
Bond Strengt~
Method 2011[ J
Quantity/Accept #
orLTPD
Components Modules[7]
3/0
3/0
22/0
10
15/0
NA
15/0
Table 7. Group D Quality'Iests (Package Related)
Notes:
7. Military Grade Modules are processed to proposed JEDEC srandard
flows for MIL-SID-BB3 compliant modules.
B. Sample size is based upon leads taken from a minimum of 3 devices.
9. Sample size is based upon leads taken from a minimum of 4 devices.
13-4
Description
Quantity/Accept #
orLTPD
Components Modules[7]
15/0
15/0
Lead Integrity, Seal:
Fine and Gross Leak,
Method 2004 and 1014
45/0[8]
15/0
3
Thermal Shock, Thmp
Cycling, Moisture
Resistance, Seal: Fine
and Gross Leak, Visual
Examination, EndPoint, Electricals,
Methods 1011, 1010,
1004 and 1014
15/0
15/0,
4
Mechanical Shock,
Vibration - Variable
Frequency, Constant
Acceleration, Seal:
Fine and Gross Leak,
Visual Examination,
End-Point Electricals,
Methods 2002, 2007,
2001 and 1014
15/0
15/0
Cypress uses an LTPD sampling plan that was developed by the
Military to assure product qUality. Testing is performed to the subgroups found to be appropriate for the particular device type. All
Military Grade component products have a Group A sample test
performed on each inspection lot per MIL-I-38535/MILSTD-883 and the applicable device specification.
Subgroup
45/0
Group C tests for all Military Grade products are performed on
one device type from one inspection lot representing each technology. Sample tests are performed per MIL-I-38535/MILSTD-883 from each four calendar quarters production of devices,
which is ba~ed upon the die fabrication date code.
End-point electrical tests and parameters are performed per the
applicable device specification.
8A
9
Components Modules[7]
Quality, Reliability, and Process Flows
QizrcYPRESS
Product Quality Assurance Flow--Components
..,
Process Details
Area
PROCESS
QC
INCOMING MATERIALS
INSPECTION
All incoming materials are inspected to documented procedures covering the
handling, inspection, storage, and release of raw materials used in the
manufacture of Cypress products. Materials inspected are: wafers, masks,
leadframes, ceramic packages and/or piece parts, molding compounds, gases,
chemicals, etc.
FAB
DIFFUSION/ION
IMPLANTATION
Sheet resistance, implant dose, species and CV characteristics are measured
for all critical implants on every product run. Test wafers may be used to collect
this data instead of actual production wafers. If this is done, they are processed
with the standard product prior to collecting specific data. This insures accurate
correlation between the actual product and the wafers used to monitor
implantation.
FAB
OXIDATION
Sample wafers and sample sites are inspected on each run from various
positions of the furnace load to inspect for oxide thickness. Automated
equipment is used to monitor pinhole counts for various oxidations in the
process. In addition, an appearance inspection is performed by the opeartor to
further monitor the oxidation process.
FAB
PHOTOLITHOGRAPHY
/ETCHING
Appearance of resist is checked by the operator after the spin operation. Also,
after the film is developed, both dimensions and appearance are checked by
the operator on a sample of wafers and locations upon each wafer. Final CDs
and alignment are also sample inspected on several wafers and sites on each
wafer on every product run.
FAB
METALIZATION
Film thickness is monitored on every run. Step coverage cross-sections are
performed on a periodic basis to insure coverage.
FAB
PASSIVATION
An outgoing visual inspection is performed on 100% of the wafers in a lot to
inspect for scratches, particles, bubbles, etc. Film thickness is verified on a
sample of wafers and locations within each given wafer on each run. Pinholes
are monitored on a sample basis weekly.
FAB
QC VISUAL OF
WAFERS
FAB
E-TEST
Electrical test is performed for final process electrical characteristics on every
wafer.
FAB
QC MONITOR OF
E-TEST DATA
Weekly review of all data trends; running averages, minimUmS, maximums,
etc. are reviewed with the process control manager.
TEST
WAFER PROBE/SORT
Verify functionality, electrical characteristics, stress test devices.
TEST
QC CHECK PROBING
AND ELECTRICAL
TEST RESULTS
Pass/faillot based on yield and correct probe placement.
TO ASSEMBLY
AND TEST
(continued)
13-6
6i1EYPRESS
Quality, Reliability, and Process Flows
Product Quality Assurance F1ow-Components (continued)
Commercial and Industrial Product
HERMETIC
PLASTIC
QC Visual Lot Acceptance for Die Coated Products
Mold/Encapsulate Plastic Devices
Seal Hermetic Devices
Periodic QC Monitor, Lid-Torque
Shear strength of glass-frit seal tested
to MIL-STD-883, Method 2024
Post Mold Cure
Per Cypress method for molding compound
Lead Trim/Form
Lead trim and form for plastic devices, lead
trim for hermetic devices (where applicable)
LotlD
Mark assembly lot on devices
Lead Prep/Finish (Solder Dip)
Prepare leads for solder dip, solder dip devices
and inspect for uniform solder coverage
QC Process Monitor
Verify workmanship and solder coverage
Fine and Gross Leak Test
Method 1014, Cond A or 8; fine leak (sample)
Method 1014, Cond C; gross leak (100%)
External Visual Inspection
Inspect for workmanship, construction, cracked or
broken devices, bent leads, crazing, castellation
alignment, and solder coverage.
MIL-STD-883, Method 2009
(continued)
13-8
.~YPRESS
Quality, Reliability, and Process Flows
Product Quality Assuranee F1ow-Components
Military Components
MILITARY ASSEMBLY FLOW
Wafer Prep/Mount/Saw
Inspect for accurate sawing of scribeline and 100% saw-through
Die Visual Inspection
Inspect die per MIL-STD-B83, Method 2010, condition B
QC Visual Lot Acceptance
Sample inspect die; 1.0% AQL
Die Attach
Attach per Cypress detailed specification
Die Adherence Monitor
MIL-STD-B83, Method 2019 or Method 2027
Wire Bond
Bond per Cypress detailed specification
Bond Pull Monitor
MIL-STD-B83, Method 2011
Internal Visual Inspection
Low-power and high-power inspection per
MIL-STD-BB3, Method 2010, condition B
QC Visual Lot Acceptance
Sample inspect lot per MIL-STD-B83,
Method 2010, condition B, 0.4% AQL
Die Coat
Coating applied to selected products
QC Visual Lot Acceptance for Die Coated Products
Seal
Periodic QC Monitor, Lid-Torque
Shear strength of glass
(continued)
13-10
~YPRESS
Quality, Reliability, and Process Flows
Product Quality Assurance Flow-Components (continued)
Military Components
Lead Finish - Solder Dip
Solder dip applicable devices
Fine and Gross Leak Test
Method 1014, condition A or B, fine leak; condition C, gross leak
Final Device Marking
MIL-STD-883 or applicable device specification
Group B
Method 5005
Group A
Method 5005, per applicable device specification
Group C and D
Method 5005, in accordance with
1.2.1 of MIL-STD-883; JAN devices
in accordance with MIL-I-38535
External Visual
Method 2009,100% inspection
External Visual Sample
Method 2009, 0.01 % AQL
Plant Clearance
Pack/Ship Order
Key
o
o
Test/Inspection
[Q]
Production Process and Test Inspection
<>
Production Process
QC Sample Gate and Inspection
13-12
Quality, Reliability, and Process Flows
-:jEYPRESS
Product Quality Assurance Flow-Modules (continued)
---,
OPTIONAL BURN-IN PROCESSING FOR LEVEL 2
(STANDARD FOR MIL DEVICES)
1- - -
•
o
Burn-In
Method 1015
o
o
QC Monitor - Burn-In Documents!
Results
o
o
Post-Burn-In Electricals
Per applicable device specification
o
QC Inspection
PDA verified within limits
.
- _.1
I . __
Final Electrical Test
100% test lot; DC, AC, functional, and dynamic
tests performed per applicable device specification
Final Device Marking
Final Visual Inspection
Confirm part type, count, package, check for
completeness of processing requirements, confirm
supporting documentation is sent, if required
QA electrical test
(roomtemperature)
Inspection - Pre-Shipment
Pack/Ship Order
o
o
IQ]
<>
Key
Production Process
Test/Inspection
Production Process and Test Inspection
QC Sample gate and inspection
13-14
Tape and Reel Specifications
Description
Surface-mounted devices are packaged in embossed tape and
wound onto reels for shipment in compliance with Electronics
Industries Association Standard EIA -481 Rev. A.
Specifications
Cover Tape
• The cover tape may not extend past the edge of the carrier tapes
• The cover tape shall not cover any part of any sprocket hole.
• The seal of the cover tape to the carrier tape is uniform, with the
seal extending over 100% ofthe length of each pocket, on each
side.
SOIC Devices
• The force to peel back the cover tape from the carrier tape shall
be: 20 gms mmimal, 70 gms nominal, 100 gms maximal, at a pullback speed of 300 ± 10 mm/min.
Loading the Reel
Empty pockets between the first and last filled pockets on the tape
are permitted within the following requirements:
• No two consecutive pockets may be left empty
• No more than a total often (10) empty pockets may be on a reel
The surface-mount devices are placed in the carrier tape with the
leads down, as shown in Figure 1.
TYPICAL
PLCC and LCC Devices
TYPICAL
DIRECTION OF FEED
SOJDevices
TYPICAL
DIRECTION OF FEED
[J][J][J]
..
DIRECTION OF FEED
figure 1. Part Orientation in Carrier Tape
13-16
PIN #1 TO BE ON CIRCULAR
SPROCKET-HOLE SIDE OF TAPE
Tape and Reel
QYPRESS
Thble 1. Parts Per Reel and Thpe Specifications
Package 1YJIe
Thrminals
Carrier Width (mm)
Part Pitch (mm)
PLee
20
16
12
750
28
24
16
500
SOle
SOJ
TSOP
SSOP
TSSOP
Parts Per FuU Reel
32R
24
16
500
44
32
24
400
52
32
24
400
68
84
44
250
44
32
32
20
24
12
250
1,000
24
24
12
1,000
28
24
12
1,000
20
24
3
24
24
3
1,000
1,000
28
24
3
1,000
32 (400 mil)
32
3
1,000
32
32
3
1,750
20 (150 mil)
24 (150 mil)
16
16
8
2,000
8
2,000
48 (300 mil)
32
16
1,000
56 (300 mil)
32
16
1,000
48
24
12
2,000
56
24
12
2,000
13-18
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Section Contents'
Packages
Page Number
Thermal Management and Component Reliability ".......................................................... 14-1
Package Diagrams ....................................................................................... 14-11
Module Package Diagrams ............................................................................... 14-92
Sales Representatives and Distributors
Direct Sales Offices
North American Sales Representatives
International Sales Representatives
Distributors
~YPRESS
Thermal Management
'DIble I. Failure Mechanisms and
Activation Energies in CMOS Devices
Thermal Resistance (6JA, 6Je)
Surface Charge
0.5-1.0 eV
Slow Trapping
1.0eV
Thermal resistance is a measure of the ability of a package to
transfer the heat generated by the device inside it to the ambient.
For a packaged semiconductor device, heat generated near the
junction of the powered chip causes the junction temperature to
rise above the ambient temperature. The total thermal resistance
is defined as
6 JA = TJ - TA
P
and 6JA physically represents the temperature differential between the die junction and the surrounding ambient at a power
dissipation of 1 watt.
Plastic Chemistry
1.0eV
The junction temperature is given by the equation
Polarization
1.0eV
Failure Mode
Approximate
Activation Energy (Eq)
Oxide Defects
0.3 eV
Silicon Defects
0.3 eV
Electromigration
0.6eV
0.geV
Contact Metallurgy
Microcracks
1.3 eV
Contamination
1.4eV
where
1b reduce thermally activated reliability failures, Cypress Semiconductor has optimized both their low-power-generating CMOS
device fabrication process and their high-heat-dissipation packaging capabilities. Table 2 demonstrates this optimized thermal performance by comparing bipolar, NMOS, and Cypress high-speed
lK SRAM CMOS devices in their respective plastic packaging
environments under standard operating conditions.
Bipolar
NM()S
Cypress
CMOS
6CA= Tc - TA
P
TA
=
TJ
=
=
=
TC
P
Table 2. Thermal Performance of Fast IK SRAMs
in Plastic Packages
Thchnology
and
Ambient temperature at which the device is operated;
Most common standard temperature of operation is room
temperature to 70° C.
Junction temperature of the IC chip.
Thmperature of the case (package).
Power at which the device operates.
6 JC = Junction-to-case thermal resistance. This is mainly a function of the thermal properties ofthe materials constituting
the package.
93422
9122
7C122
Speed (ns)
30
25
25
6JA = Junction-to-ambient thermal resistance. The junction-toambient environment is a still-air environment.
Icc(mA)
150
110
60
6CA
VcC i ' l
=
=
=
0000
L
[ffi[lllrnmIIIIl[][][ll]llJ[JJ[[I] OrnnnmIDIIllll iii iii iii I~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~.
.295#
.105/.115
=
J I:
--J
~.074
NOM.
1.960 NOM.
2.160 NOM.
l
1.200 MAX
~
I\..
j
PIN 1
.
4
34~
MAX •
l
'I
•
~~~~~ 6 ~~OO[JJ~,
295~:'J05
[]][][][][]['[J[][] I [lllll]][][][][][lll]]O
--I ~ 074 NOM
1960 NOM
•
2160 NOM
1
105/115
:
.-
L
.057/.067
4.130 MAX .
160-Pin Dual-Readout SIMM PM27
I.
r.265 MAX
4130 MAX - - - - - - - - I
14-106
~
PIN 1
r
220
jL
MAX
057/06 7
=:..rcYPRESS ========M~o~du;;;;;le~P;;;;;;;ac;;;;;;;ka==ge=D;;;;;;;;;ia!:gr=am~s
160·Pin Dual·Readout SIMM PM32
I'
"I
4,345 MAX
r,360 MAX
---II-- ,07 4 NOM
I:
1,960 NOM,
2,160 NOM,
PIN 1
j
l
,057/,067
4,130 MAX, - - - - - - - - - I
,105/,115
160·Pin Dual·Readout SIMM PM33
4,345 M A X - - - - - - - - - I ' I
00
00
°0
DOD DOD l
o
0 0
0
L
295~ ~~mmrrlIllmmm[]:mm~~mm[J][l] Immmmmmm[l]~mmmmmmmmm[
,105/,115
J
,074 NOM,--J
I--
1,960 NOM,
larnmmmmJI[rnIImmmmmmmurnm][mmo[l]mmmom~momomom~mmm
0=
= ~D
00
0
0
o
0 00
14-108
1,[40 MAX
:J
L
2,160 NOM,
4,130 MAX,
~O [ ]
r
A80 MAXl
0
0
PIN 1
JL
,057/,067
36·Pin SIP Module PS06
-1
~-------~-------...!·I
:===-r==:
:======;;=~I 1
-*-J~fflflHmmFJ!lK4fl.~m~d~pmn:~.125-.175
~-----3.500
f
.\
.190 MAX.
~
.755/ .040 TYP.
-l~ .020TYP.
r
(36 PINS)
36·Pin SIP Module PS08
~
I-
·1
I~=_: I!~I ; rl;/~~
1
.120 MAX.
~nll
Mil m~"-,,,
I~ I--II-II1
.100 TYP
.050 TYP.
.020 TYp..14
3.500 (36 PINS) ----~-.
40·Pin Plastic VDIP Module PV04
0.100xO.100
CHAMFER
PIN1
-110.3451
,
MAX.r-
f
l-1h
1
I I
oJ~o
~ 1.900REF.
--.L
0.540
MAX.
f
+
0.005 MIN.
I
I
---I
14-110
DIMENSIONS IN INCHES
MIN.
MAX.
Module Package Diagrams
.iI2YPRESS
64·Pin Plastic ZIP Module PZ03
Bottom View
~
_I
~
I.
1+"0.050
3.660.
,~rDDO.IDDIlIiDDIlIiDD I·J;
-I
0.350
MAX
r-
nn
''''_ffil~_~_~J~
1f
1::.'
'.'00
L ,.'"
I
II
,.'"
.I'.""L
.1 I.
I"
r..-"0.165
I i 0.025
'I TYP r'I
"""""""
""""
inn" " " " " " " " " " "
n
n
n
n
n
n
n
n
n
n
.J I ,.""
J I" TYP
TYP
n
"
n
n
n
"
n
n
n
n
n
n
n
n
n
I
( )
-I
~
0.100
TYP
n
Pin 1
DIMENSIONS IN INCHES
MIN.
MAX.
6O·Pin Plastic ZIP Module PZ04
Bottom View
-I
~
I..
~ I+" 0.050
3.460·
'~~~N~J.;
I
1.120
1.150
~
II-1 r..-
.11.
In i"
LO.135
0.165
1
n
n
inn
n
"
n
n
"
"
n
n
"
0.015
0.025
n
n
"
n
n
n
"
"
"
n
n
n
n
JO.250L
TYP I
'I
n"
n
"'
"n
n
n
n
n
I
n
"
J
n
n
"
1_0.100
TYP
i
n
n
n
n
n
n
"
n
n
n
n
n
n
-.J1_0.050
I" TYP
J
n
n
n
n
n
1
J
~
0.100
TYP
n
Pin 1
DIMENSIONS IN INCHES
MIN.
MAX.
14-112
=:'~YPRESS ===~Mod~uleP~acka~geD~iagra~ms
72·Pin Plastic ZIP Module PZ09
,350 MAXl
r
.
. .
8888
~'
J JL
.,
'-,
l_~
LJ
PIN 1
"I
3,850 MAX
1
I
,035/,065
--1
r-~
, __ J
,575 MAX
[_.
~
,125/,175
J L
,050 TYP,
•
,250
JL
I
,100 TYP,
3,750 (72 PINS)
,090/,1l0J
L
•
64·Pin Plastic ZIP Module PZIO
,050 X 45· CHAMFER
~.
"I
3,215 MAX
1
r
,350 MAX
n::==ln::==ln::==ln::==l~'
~~~~
J:J L.,"
• :-:• • • • • • •
,025/,035
~-:
• • ••
•
~-~
• • • • • • ':-.. •
J L.'""
m.
3.150 (64 PINS)
"
••
He ;
~MAX
'''t'
j
l""n.
"
PIN 1
72·Pin Plastic ZIP Module PZll
PIN 1
,090/,1l0J
,045/,055
f---------------
14-114
L
1Iz~YPRESS~;=;=;=S=al=e=S=R=e~p=r=es=e=n=ta=t=iv=e=s=a=n=d=D;=is=t=ri=b=u=to=r~s
Domestic Sales Representatives
Alabama
Giesting & Associates
4835 University Square
Suite 15
Huntsville, AL 35816
(205) 830-4554
FAX: (205) 830-4699
Arizona
Thorn Luke Sales, Inc.
9700 North 91st St., SuiteA-2OO
Scottsdale, AZ 85258
(602) 451-5400
FAX: (602) 451-0172
California
TAARCOM
451 N. Shoreline Blvd.
Mountain View, CA 94043
(415) 960-1550
FAX: (415) 960-1999
TAARCOM
735 Sunrise Ave., Suite 200-4
Roseville, CA 95661
(916) 782-1776
FAX: (916) 782-1786
Thchnology Solutions Company
5525 Oakdale Ave., Suite 275
Woodland Hills, CA 91364
(818) 704-1693
FAX: (818) 704-6165
Thchnology Solutions Company
10 Hughes, Suite A201
Irvine, CA 92718
(714) 707-4565
FAX: (714) 707-4510
Canada
bbd Electronics, Inc.
6685 -1 Millcreek Dr.
Mississauga, Ontario LSN 5M5
. (416) 821-7800
FAX: (416) 821-4541
bbd Electronics, Inc. - Vancouver
(604) 465-6892
FAX: (905) 821-4092
Western Canada
Kansas
Microwe Electronics Corporation
5330 Wallace Avenue
Delta, British Columbia V4M lAI
(604) 943-5020
FAX: (604) 943-8184
Midwest Thchnical Sales
13 Woodward Dr.
Augusta, KS 67010
(316) 775-2565
FAX: (316) 775-3577
Colorado
Midwest Thchnical Sales
15301 W. 87 Parkway, Ste. 200
Lenexa, KS 66219
(913) 888-5100
FAX: (913) 888-1103
Lange Sales
1500 W. Canal Court, Bldg. A
Suite 100
Littleton, CO 80120
(303) 795-3600
FAX: (303) 795-0373
Kentucky
Thchnology Marketing Corp.
100 Thade Street, Suite lA
Lexington, KY 40510-1007
(606) 253-1808
FAX: (606) 253-1662
Connecticut
HLM
3 Pembroke Rd.
Danbury, cr 06810
(203) 791-1878
FAX: (203) 791-1876
Massachusetts
The Nashoba Group
One Technology Park Drive
Westford, MA 01886
(508) 692-7503
FAX: (508) 692-5081
Georgia
Giesting & Associates
2434 Highway 120
Suite 108
Duluth, GA 30136
(404) 476-0025
FAX: (404) 476-2405
Michigan
Thchrep
2200 North Canton Center Rd.
Suite 110
Canton, MI 48187
(313) 981-1950
FAX: (313) 981-2006
D1inois
Micro Sales Inc.
901 W. Hawthorn Drive
Itasca,IL 60143
(708) 285 -1000
FAX: (708) 285 -1008
Minnesota
Matrix Marketing, Inc.
5001 West 80th Street, Suite 375
Bloomington, MN 55437
(612) 835-6977
FAX: (612) 835-6822
Indiana
Thchnology Mktg. corp.
1526 East Greyhound Pass
Carmel, IN 46032
(317) 844-8462
FAX: (317) 573-5472
bbd Electronics, Inc. - Calgary
(403) 225-2916
FAX: (905) 821-4092
Technology Mktg. Corp.
4630-10 W. Jefferson Blvd.
FI. Wayne, IN 46804
(219) 432-5553
FAX: (219) 432-5555
bbd Electronics, Inc. - Ottawa
(613) 564-0014
FAX: (416) 821-4092
Midwest Thchnical Sales
463 Northland Ave., N.E.
Suite 101
Cedar Rapids, IA 52402
(319) 377-1688
FAX: (319) 377-2029
bbd Electronics, Inc. - Winnipeg
(204) 942-2977
FAX: (416) 821-4092
bbd Electronics, Inc.
298 Lakeshore Rd., Ste. 203
Pointe Claire, Quebec H9S 4L3
(514) 697-0801
FAX: (514) 697-0277
bbd Electronics, Inc. - Edmonton
(403) 491-0020
FAX: (905) 821-4029
Iowa
Thchnology Marketing Corp.
1214 Appletree Lane
Kokomo, IN 46902
(317) 459-5152
FAX: (317) 457 - 3822
Missouri
Midwest Thchnical Sales
514 Earth City Expwy., #239
Earth City, MO 63045
(314) 298-8787
FAX: (314) 298-9843
Nevada
,
TAARCOM
735 Sunrise Ave.
Suite 200-4
Roseville, CA 95661
(916) 782-1776
FAX: (916)782-1786
1srcYPRESS ====S;;;;;3;;;;;le;;;;;s;;;;;R;;;;;;;ep;r;;;;;e;;;;;S;;;;;eD;;;;;t;;;;;3;;;;;t;;;;;iv;;;;;e;;;;;S;;;;;3;;;;;D;;;;;d;;;;;D=is;;;;;tr;;;;;i;;;;;h;;;;;u;;;;;to;;;;;r=s
International Direct Sales Offices
Cypress Semiconductor
International-Europe
Avenue Ernest Solvay, 7
B-13lO La Hulpe, Belgium
Tel: (32) 2-652-0270
Thlex: 64677 CYPINT B
FAX: (32) 2-652-1504
France
Cypress Semiconductor France
Miniparc B§1. no 8
Avenue des Andes, 6
Z.A. de Courtaboeuf
91952 Les Ulis Cedex, France
Tel: (33) 1-69-29-88-90
FAX: (33) 1-69-07-55-71
Germany
Cypress Semiconductor GmbH
Munchner Str. 15A
W-8011, Zorneding, Germany
Tel: (49) 81-06-2855
FAX: (49) 81-06-20087
Cypress Semiconductor GmbH
BiiroNord
Matthias-Claudius-Str. 17
W - 2359 Henstedt-Ulzburg, Germany
Thl: (49) 4193-77217
FAX: (49) 4193-78259
Italy
Cypress Semiconductor
Via Di Valle Focicchia 2
00040 Rocca Di Papa, Rome
Thl: (39) 6-949-6888
FAX: (39) 6-949-6888 (same as phone)
Cypress Semiconductor
Interporto di Torino
Proma Strada n. 5IB
10043 Orbassano, Italy
Thl: (39) 11-397-57-98
or (39) 11-397-57-57
FAX: (39) 11-397-58-10
Cypress Semiconductor
Via Gallarana 4
20052 Monza, Milano
Tel: (39) 39-202-7099
FAX: (39) 202-7101
Japan
Cypress Semiconductor Japan K.K.
Shinjuku-Marune Bldg.
1-23 -1 Shinjuku
Shinjuku-ku, Thkyo, Japan 160
Thl: (81) 3-5269-0781
FAX: (81) 3-5269-0788
Singapore
Cypress Semiconductor Singapore
583 Orchard Road, #11-03 Forum
Singapore 0923
Tel: (65) 735-0338
FAX: (65) 735-0228
Sweden
Cypress Semiconductor
Scandinavia AB
Thby Centrum, Ingang S
S-18311 Thby, Sweden
Thl: (46) 8 638 0100
FAX: (46) 8 792 1560
United Kingdom
Cypress Semiconductor U.K., Ltd.
Gate House
Fretherne Road
Welwyn Garden Cily
Herts., U.K. AL8 6NS
Tel: (44) 707-33-88-88
FAX: (44) 707-33-88-11
Cypress Semiconductor Manchester
27 Saville Rd. Cheadle
Gatley, Cheshire, UK
Thl: (44) 614-28-22-08
FAX: (44) 614-28-0746
International Sales Representatives
Australia
Braemac Pty. Ltd.
1/59-61 Burrows Road
Alexandria, Sydney 2015, Australia
Thl: (61) 2-550-6600
FAX: (61) 2-550-6377
Broemac Ply. Ltd.
6/417 Ferntree Gully Rd.
Mt. Waverly, Victoria 3149, Australia
Thl: (61) 3-540-0100
FAX: (61) 3-540-0122
Broemac Ply. Ltd.
300 Gilles Street
Adelaide, SA 5000, Australia
Thl: (61) 8-232-5550
FAX: (61) 8-232-5551
Austria
Eurodis Electronics GmbH
Lamenzanstrasse 10
A-1232 Wien
Austria
Tel: (43) 1-610-62-128
FAX: (43) 1-610-62-151
Belgium
N.V. Memec Benelux
Sint-Lambertusstraat 135
1200 Brussels, Belgium
Thl: (32) 2-772-8008
FAX: (32) 2-460-1200
SonetechlArcobel
Limburgstirum 243
B-1810 Wemmel, Belgium
Thl: (32) 2-460-0707
FAX: (32) 2-460-1200
Denmark
Thch-Partner AlS
Thmsagervej 18
DK-8230 Aabyhoj (Aarhus)
Denmark
Thl: (45) 86-25-00-55
FAX: (45) 86-25-28-55
Finland
ScandComp Finland OY
Asemakuja 2
SF-02 770 Bspoo
Finland
Thl: (358) 0 859-3099
FAX: (358) 0 859 2120
France
Arrow Electronics
73n9, Rue des Solets
Silic 585
94653 Rungis Cedex
Thl: (33) 1 49 78 49 00
FAX: (33) 1 49 78 05 99
Arrow Electronics
Les Jardins d'Entreprises
BetimentB3
213, Rue Gedand
69007 Lyon
Tel: (33) 78 72 79 42
FAX: (33) 78 72 80 24
Arrow Electronics
Centreda
Avenue Didier Daurat
31700 Blagnac
Thl: (33) 6115 75 18
FAX: (33) 61 3001 93
France (continued)
Arrow Electronics
Immeuble SI. Christophe
Rue de la Frebardiere
ZiSudEst
35135 Chantepie
Thl: (33) 99 41 7044
FAX: (33) 99 50 11 28
Newtek
Rue de CBsterel, 8, Silic 583
F - 94663 Rungis Cedex, France
Thl: (33) 1-46-87-22-00
Thlex: 263046 F
FAX: (33) 1-46-87-80-49
Newtek
Rue de ['Europe, 4
Zac Font-Ratel
F - 38640 Chrlx, France
Thl: (33) 76-98-56-01
FAX: (33) 76-98-16-04
Newtek
32, Rue Rene- Yves Cresson
4 - 35200 Rennes, France
Thl: (33) 99-50-58-58
FAX: (33) 99-50-45-42
Scaib, SA
6 Rue Ambroise Croizat
91127 Palaiseau Cedex, France
Thl: (33) 1-69-19-89-00
FAX: (33) 1-69-19-89-20
1srcYPRESS ====S;;;;;;al;;;;;;e;;;;;;s;;;;;;R;;;;;;e;;;;;;p;;;;;;r;;;;;;es;;;;;;e;;;;;;D;;;;;;ta;;;;;;t;;;;;;iv;;;;;;e;;;;;;s;;;;;;a;;;;;;D;;;;;;d;;;;;;D=is;;;;;;tr;;;;;;i;;;;;;h;;;;;;u;;;;;;to;;;;;;r=s
International Sales Representatives (continued)
Norway
ScandComp Norway NS
Aslakveien 20 F
N -0753 Oslo 7
Norway
Thl: (47) 22-50-06-50
FAX: (47) 22-50-27-77
Singapore
Electec P1E Ltd.
Block 50, Kallang Bahru
#04-21, Singapore 1233
Thl: (65) 294-8389
FAX: (65) 294-7623
South Africa
Electronic Bldg. Elements
P.O. Box 912-1222
Silverton 0127
178 Erasmus St., Meyers Park
Pretoria 0184, South Africa
Thl: (012) 803-8294
FAX: (012) 803-7680
Spain
ATD Electronica
A1basanz, 75
28037 Madrid, Spain
Thl: (34) 1-304-1534
FAX: (34) 1-327 - 2778
Sweden
ScandComp Sweden AB
Box 8303 Domnarvsgatan 33
S-163 08 Spanga
Sweden
Thl: (46) 8-761-73-00
FAX: (46) 8-760-46-69
Switzerland
Basix flir Elektronik A. G.
Hardtuimstrasse 181
CH -8010 Zurich, Switzerland
Thl: (41) 1-276-11-11
Telex: 822762 BAEZ CH
FAX: (41) 1-276-14-48
Taiwan R.O.C.
Prospect Thchnology Corp.
SF, No. 348, Section 7
Cheng-Thh Rd.
'Thipei, Thiwan
Thl: (886) 2-820-5353
Thlex: 14391 PROSTECH
FAX: (886) 2-820-5731
Thrkey
Inter Electronik Sanayi ve Ticaret A.S.
Kadlkoy Hasircibasi Caddesi no. 55
81310 Istanbul
Thrkey
Thl: (0216) 349-94-00
Thlex: 29245 Inmd tr
FAX: (0216) 349-94-30
FAX: (0216) 349-94-34
United Kingdom
2001 Electronic Components Ltd.
Stevenage Business Park
Pin Green
Stevenage, Herts
SG14SUU.K.
Arnbar Components Ltd.
17 Thame Park Road
Thame, Oxfordshire
England, OX93XD
Thl: (44) 844-26-11-44
Thlex: 837427
FAX: (44) 844-26-17-89
Arrow Electronics (UK) Ltd.
St. Martins Business Centre
Cambridge Road
Bedford MK42 OLF, u.K.
Thl: (44) 234 270272
FAX: (44) 234 214674
Pronto Electronic System Ltd.
City Gate House
Eastern Avenue, 399-425
Gants Hill, Ilfonl,
Essex, U. K. IG2 6LR
Tel: (44) 81-554-62-22
Thlex: 8954213 PRONTO G
FAX: (44) 81-518-32-22
Spectrum
The Old Waterworks
Howes Lane
Bicester
Oxon, U.K. OX6 8UA
Thl: (44) 1-869-325-174
FAX: (44) 1-869-325-175
.~YPRESS ====S;;;;;a;;;;;le;;;;;s;;;;;&;;;;;e;;;;;p;;;;;r;;;;;e;;;;;S;;;;;eD;;;;;t;;;;;a;;;;;t;;;;;iv;;;;;e;;;;;S;;;;;a;;;;;D;;;;;d;;;;;D=is;;;;;tr;;;;;i;;;;;h;;;;;u;;;;;to;;;;;r=s
Distributors (continued)
Arrow Electronics: (cont.)
Maryland
Columbia, MD 21046
(410) 596-7800
Gatbersburg, MD
(301) 596-7800
Massachusetts
Wilmington, MA 01887
(617) 658-0900
Michigan
Livonia, MI 48152
(313) 462- 2290
Minnesota
Eden Prairie, MS 55344
(612) 941-5280
Missouri
St. Louis, MO 63146
(314) 567-6888
New Jersey
Marlton, NJ 08053
(609) 596-8000
Pinebrook, NJ 07058
(201) 227-7880
New York
Oregon
Beaverton, OR 97006-7312
(503) 629-8090
Pennsylvania
Pittsburgh, PA 15238
(412) 963-6807
Texas
Austin, TX 78758
(512) 835-4180
Carrollton, TX 75006
(214) 380-6464
Houston, TX 77099
(713) 530-4700
Washington
Bellevue, WA 98007
(206) 643-9992
Wisconsin
Brookfield, WI 53045
(414) 792-0150
Bell Microproducts:
Irvine, CA 92718
(714) 470-2900
San Jose, CA 94131
(408) 451-9400
Altamonte Springs, FL 32714
(407) 682-1199
Deerfield Beach, FL 33441
(305) 429-1001
Billerica, MA 01882
(508) 667-2400
Columbia, MD 21045
(410) 720-5100
Edina, MN 55435
(612) 933-3236
Clifton, NJ 07013
(201) 777-4100
Smithtown, NY 11787
(516) 543-2000
Ambler, PA 19002
(215) 540-4148
Austin, TX 78759
(512) 258-0725
Rochester, NY 14623
(716) 427 -0300
Richardson, TX 75081
(214) 783-4191
Hauppauge, NY 11788
(516) 231-1000
Chantilly, VA 22021
(703) 803-1020
North Carolina
Raleigh, NC 27604
(919) 876-3132
Ohio
Centerville, OR 45458
(513) 435-5563
Solon, OR 44139
(216) 248-3990
Oklahoma
Tulsa, OK 74146
(918) 252-7537
Redmond, WA 98052
(206) 861-7510
=
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