1995_IDT_RISC_Data_Book 1995 IDT RISC Data Book

User Manual: 1995_IDT_RISC_Data_Book

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Integrated Device Technology, Inc.

1995
RISC MICROPROCESSORS
DATA BOOK

2975 Stender Way, Santa Clara, California 95054
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674
Printed in U.S.A.
©1995 Integrated Device Technology, Inc.

GENERAL INFORMATION

II

CONTENTS OVERVIEW

For ease of use for our customers, Integrated Device Technology provides four separate data books
- Logic, Specialized Memories and Modules, RISC and RISC SubSystems, and Static RAM.
lOT's 1995 RISC Data Book is comprised of new and revised data sheets for the RISC and RISC
Subsystems product groups. Also included is a current packaging section for the products included in this
book. This section will be updated in each subsequent data book to reflect packages offered for products
included in that book.
The 1995 RISC Data Book's Table of Contents contains a listing of the products contained in that data
book only. In the past we have included products that appeared in other lOT data books. The numbering
scheme for the book is as follows: the number in the bottom center of the page denotes the section number
and the sequence of the data sheet within that section, (i.e. 5.5 would be the fifth data sheet in the fifth
section). The number in the lower right hand corner is the page number of that particular data sheet.
Integrated Device Technology, a recognized leader in high-speed CMOS technology, produces a broad
line of products. This enables us to provide a complete CMOS solution to designers of high-performance
digital systems. Not only do our product lines include industry standard devices, they also feature products
with faster speed, lower power, and package and/or architectural benefits that allow the designer to
achieve significantly improved system performance.
To find ordering information: Ordering Information for all products in this book appears in Section
1, along with the Package Outline Index, Product Selector Guides, and Cross Reference Guides.
Reference data on our Technology Capabilities and Quality Commitments is included in separate sections
(2 and 3, respectively).
To find product data: Start with the Table of Contents, organized by product line (page 1.2), or with
the Numeric Table of Contents (page 1.4). These indexes will direct you to the page on which the complete
technical data sheet can be found. Data sheets may be of the following type:
PRODUCT BRIEF - contains initial descriptions, subject to change, for products that are in
development, also includes a features listiing.
ADVANCE INFORMATION development.

contain initial descriptions, subject to change, for products that are in

PRELIMINARY - contain descriptions for products soon to be, or recently, released to production,
including features, pinouts and block diagrams. Timing data are based on simulation or initial characterization and are subject to change upon full characterization.
FINAL - contain minimum and maximum limits specified over the complete supply and temperature
range for full production devices.
New products, product performance enhancements, additional package types and new product
families are being introduced frequently. Please contact your local lOT sales representative to determine
the latest device specifications, package types and product availability.

1.1

II

LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems
unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of lOT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support
or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Note: Integrated Oevice Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve
design or performance and to supply the best possible product. lOT does not assume any responsibility for use of any circuitry described other than the circuitry
embodied in an lOT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Oevice
Technology, Inc.
I

The lOT logo is a registered trademark, and BUSMUX, Flexi-pak, BiCEMOS, CacheRAM, CEMOS, FASTX, Flow-thruEOC, I OTic, IOT/envY, IOT/kit, IOT/sae,
IOT/sim, IOT/ux, MacStation, REAL8, RISC SubSystem, RISControlier, RISCore, RISCompiler, RISC Windows, RISChipset, SmartLogic, SyncFIFO,
TargetSystem, Orion, R36100, R3041 , R3051 , R3052, R3071, R3081 , R3710, R3715, R3720, R3721 , R3740, R4400, R4600, R4650 and R4700 are
trademarks of Integrated Oevice Technology, Inc.
MIPS and RISCross are registered trademarks of MIPS Computer Systems; Windows is a registered trademark of MicroSoft Corporation; UNIX is a registered
trademark of AT & T; Appletalk is a registered trademark of Apple Computer, Inc.; PostScript is a registered trademark of Adobe Systems; Sun-4, Sparc, and
SunOS are registered trademarks of SUN Microsystems, Inc.; IRIX 5.2 is a registered trademark of Silicon Graphics, Inc.

1.1

2

1995 RISC DATA BOOK
TABLE OF CONTENTS
PAGE

GENERAL INFORMATION
Contents Overview ................................................................................................................................................
Table of Contents .................................................................................................................................................
Numeric Table of Contents ...................................................................................................................................
Ordering Information .............................................................................................................................................
I DT Package Marking Description ........................................................................................................................
RISC Product Selector Guide ...............................................................................................................................

1.1
1.2
1.3
1.4
1.5
1.6

TECHNOLOGY AND CAPABILITIES
IDT ... Leading the CMOS Future ...........................................................................................................................
IDT Military and DESC-SMD Program ..................................................................................................................
Radiation Hardened Technology ..........................................................................................................................
IDT Leading Edge CMOS Technology .................................................................................................................
Superior Quality and Reliability .............................................................................................................................

2.1
2.2
2.3
2.4
2.5

QUALITY AND RELIABILITY
Quality, Service and Performance ........................................................................................................................
IDT Quality Conformance Program ......................................................................................................................
Radiation T olerantiEnhanced/Hardened Products for Radiation Environments .................................................. .

3.1
3.2
3.3

PACKAGE DIAGRAM OUTLINES
Thermal Performance Calculations for IDT's Packages .......................................................................................
Package Diagram Outline Index ...........................................................................................................................
Monolithic Package Diagram Outlines ..................................................................................................................

4.1
4.2
4.3

RISC PROCESSING COMPONENTS
IDT79R3000A
IDT79R3041
I DT79 R3051 /79 R3052
IDT79R3071
IDT79R3081
IDT79R36100
IDT79R4400
IDT79R4600
IDT79R4650
IDT79R4700

RISC CPU Core Processor .......................................................................................
Integrated RISControlier™ for Low-Cost Systems .................................................... ..
IDT79R3051/79R3052 RISControliers™ ................................................................... .
IDT79R3071 RISController'" ......................................................................................
IDT79R3081 RISControlier™ with FPA .................................................................... .
IDT79R361 Highly Integrated RISControlier™ .......................................................... .
Third-Generation 64-Bit Super-Pipelined RISC Microprocessor .............................. .
Fourth-Generation 64-Bit RISC Microprocessor ...................................................... ..
Embedded 64-Bit RISC Orion'· Microprocessor ...................................................... ..
Enhanced Orion'· 64-Bit RISC Microprocessor ........................................................ .

5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10

RISC SUPPORT COMPONENTS
IDT79R3715
IDT79R371 0/40
IDT79R4761
IDT79R4762

Single-Chip System Controller..................................................................................
Laser Printer Integrated System Controller for IDT R30xx RISControlier™ Family
w/Adobe'· Frame Buffer Compression ......................................................................
Orion'" Family Memory and I/O Controller ........ ...... .............. ...... .......... .............. .......
Orion'" Family PCI to Orion'" Bridge .........................................................................

1.2

6.1
6.2
6.3
6.4

II

1995 RISC DATA BOOK (Continued)
RISC DEVELOPMENT SUPPORT PRODUCTS
Third Party Development Tools and Applications Software for lOT RISC Processors .........................................
Training Class
Applications Development with lOT RISControllers'" and Orion'" Microprocessors..
IDT79S389
Laser Printer Controller-3051 Family Reference Platform for Postscript'" Level 2
Software from Adobe'" ... ........... ... .... ................. ............ ............... ......... ..... ... ....... ......
IDT79S385A
R3051'" Family Evaluation Kit ...................................................................................
lOT 79S341
R3041'" Evaluation Kit ...............................................................................................
IDT79S381
R3081'" Evaluation Kit ...............................................................................................
IDT79S460
R4600'" Evaluation and Development Platform ........................................................
IDT79S464
Orion'" 79R464 Evaluation Kit ...................................................................................
IDT7RS901
IDT/sim'" System Integration Manager ROMabie Debugging Kernel........................
IDT7RS930
IDT/c'" Multihost GNU C-Compiler System ...............................................................
IDT7RS909
lOT/kit'" Kernel Integration Toolkit .............................................................................

7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11

lOT SALES OFFICE, REPRESENTATIVE AND DISTRIBUTOR LOCATIONS

1.2

2

NUMERICAL TABLE OF CONTENTS
PART NO.

PAGE

IDT79R3000A
IDT79R3041
IDT79R3051/79R3052
IDT79R3071
IDT79R3081
IDT79R36100
IDT79R371 0/40

RISC CPU Core Processor .......................................................................................
Integrated RISControlle(" for Low-Cost Systems......................................................
IDT79R3051/79R3052 RISControllers'" ....................................................................
IDT79R3071 RISController'" ......................................................................................
IDT79R3081 RISController'" with FPA .....................................................................
IDT79R361 Highly Integrated RISController'" ...........................................................
Laser Printer Integrated System Controller for IDT R30xx RISController'" Family
w/Adobe'" Frame Buffer Compression ......................................................................
IDT79R3715
Single-Chip System Controller ..................................................................................
IDT79R4400
Third-Generation 64-Bit Super-Pipelined RISC Microprocessor ...............................
IDT79R4600
Fourth-Generation 64-Bit RISC Microprocessor ........................................................
IDT79R4650
Embedded 64-Bit RISC Orion'" Microprocessor ........................................................
IDT79R4700
Enhanced Orion'" 64-Bit RISC Microprocessor .........................................................
IDT79R4761
Orion'" Family Memory and I/O Controller .................................................................
IDT79R4762
Orion'" Family PCI to Orion'" Bridge .........................................................................
IDT79S341
R3041 '" Evaluation Kit ... .................. .... ... ....... .......... ...... ....... ...... .......... .... ...... ........ ...
IDT79S381
R3081'" Evaluation Kit ...............................................................................................
IDT79S389
Laser Printer Controller-3051 Family Reference Platform for Postscripf" Level 2
Software from Adobe'" ...............................................................................................
IDT79S385A
R3051'" Family Evaluation Kit ...................................................................................
IDT79S460
R4600'" Evaluation and Development Platform .........................................................
IDT79S464
Orion'" 79R464 Evaluation Kit ...................................................................................
IDT7RS901
IDT/sim'" System Integration Manager ROMabie Debugging Kernel........................
IDT7RS909
IDT/kif" Kernel Integration Toolkit .............................................................................
IDT7RS930
IDT/c'" Multihost GNU C-Compiler System ...............................................................
Third Party Development Tools and Applications Software for IDT RISC Processors .........................................
Training Class
Applications Development with IDT RISControllers'" and Orion'" Microprocessors ..

1.3

5.1
5.2
5.3
5.4
5.5
5.6
6.2
6.1
5.7
5.8
5.9
5.10
6.3
6.4
7.5
7.6
7.3
7.4
7.7
7.8
7.9
7.11
7.10
7.1
7.2

II

ORDERING INFORMATION
When ordering by TWX or Telex, the following format must be used:
A. Complete Bill To.
B. Complete Ship To.
C. Purchase Order Number.
D. Certificate of Conformance. Y or N.
E. Customer Source Inspection. Y or N.
F. Government Source Inspection. Y or N
G. Government Contract Number and Rating.
H. Requested Routing.
I.
IDT Part NumberEach item ordered must use the complete part number exactly as listed in the price book.
J. SCD Number - Specification Control Document (Internal Traveller).
K. Customer Part NumberlDrawing Number/Revision Level Specify whether part number is for reference only, mark only, or if extended processing to
customer specification is required.
L. Customer General Specification Numbers/Other Referenced Drawing Numbers/Revision Levels.
M. Request Date With Exact Quantity.
N.
Unit Price.
O. Special Instructions, Including Q.A. Clauses, Special Processing.
Federal Supply Code Number/Cage Number Dun & Bradstreet Number - 03-814-2600
Federal Tax I.D. - 94-2669985
TLX# - 887766
FAX# - 408-727-3468

61772

PART NUMBER DESCRIPTION
IDT

79XX
POWER

XXX

xx

DEVICE TYPE

999

'SP"E'E5'

A

A

"'PAcK'AGE

A

PROCESSI
TEMPERATURE

SPECIAL
PROCESS

y~~:NK

RADIATION TOLERANT
KNOWN GOOD DIE
COMMERCIAL - O°C to +70°C
INDUSTRIAL - _40°C to +85°C
(Consult Factory)
MILITARY - -55°C to + 125°C
(Fully compliant to MIL-STD-883.
Method5004. Cass B)

SEE PACKAGE DESCRIPTION TABLE

SPEED

GUARANTEED MINIMUM PERFORMANCE
MEASURED IN MHz

DEVICE
TYPE"

e.g. 3041

POWER
SUPPLY
VOLTAGE

R - 5.0V
RV - 3.3V

PACKAGE DESCRIPTION TABLE
J
PF

MJ
FD
G
GL
MS

84-lead PLCC
100-Iead TOFP
160-Lead POFP
208-Lead POFP
84-lead MOUAD
84-lead Cavity-down Flatpak
179-pin PGA
447-pin PGA
Extended lead 447-pin PGA
208-lead MOUAD

1.4

lOT PACKAGE MARKING DESCRIPTION
PART NUMBER DESCRIPTION

4.

lOT's part number identifies the basic product, speed,
power, package(s) available, operating temperature and
processing grade. Each data sheet has a detailed description,
using the part number, for ordering the proper product for the
user's application. The part number is comprised of a series
of alpha-numeric characters:

5.

1.
2.
3.

6.

An "lOT" corporate identifier for Integrated Device
Technology, Inc.
A basic device part number composed of alpha-numeric
characters.
A device power identifier, composed of one or two alpha
characters, is used to identify the power options. In most
cases, the following alpha characters are used:
"R" is used for 5.0V compliant products.
"RV" is used for 3.3V compliant products.

7.

A device speed identifier, when applicable, is either alpha
characters, such as "A" or "8", or numbers, such as 20 or
45. The speed units, depending on the product, are in
nanoseconds or megahertz.
A package identifier, composed of one ortwo characters.
The data sheet should be consulted to determine the
packages available and the package identifiers for that
particular product.
A temperature/process identifier. The product is available
in either the commercial or military temperature range,
processed to a commercial specification, or the product is
available in the military temperature range with full
compliance to MIL-STD-883. Many of lOT's products
have burn-in included as part of the standard commercial
process flow.
A special process identifier, composed of alpha characters,
is used for products which require radiation enhancement
(RE) or radiation tolerance (RT).

Example for Monolithic Devices:
lOT

XXX ... XXX

XX

X.. X

X... X

x

TL_:
XX

Special Process
Processrremperature*
Package*
Speed
Power
Device Type*

* Field Identifier Applicable To All Products
2507 drw 01

ASSEMBLY LOCATION DESIGNATOR

MIL-STD-883C COMPLIANT DESIGNATOR

lOT uses various locations for assembly. These are
identified by an alpha character in the last letter of the date
code marked on the package. Presently, the assembly
location alpha character is as follows:
V = Penang, hermetic
I = Anam, Korea
T = Hong Kong
A = USA
G = USA, hermetic
M = USA, plastic
P = Api, Phillipines
H = Penang, plastic

lOT ships certain military products which are compliant to
the latest revision of MIL-STD-883C. Such products are
identified by a "c" designation on the package. The location
of this designator is specified by internal documentation at
lOT.

1.5

II

HIGH-SPEED CMOS
MICROPROCESSOR FAMILY
PRODUCT SELECTOR GUIDE
Integrated Device Technology, Inc.

High-Speed CMOS Microprocessor Family
•

Broadest range of high-performance to low-cost, code-compatible RISC processors: R3000A, R4000 CPUs, R3041/51/52181
RISControliers, R4600, R4650, and R4700

•

R4400-third-generation high-performance 64-bit CPU and
FPA with on-chip cache

•

R3051/52/81/41 RISControlier Family-designed for lowercost embedded systems, all code-compatible with original
R3000

•

Support chips designed for RISC systems: R3715 System
Controller, R3740 LaserPrinterControlier, R4761 Orion Family
System Controller, and R4762 Orion Family PCI Bridge Chip

•

Low-cost Evaluation Boards available

• Applications range from real-time control to multiprocessing
systems
•

Optimizing compilers

Number

Description

Pkgs.

Avail.

Data
Book
Page

RISC CMOS MICROPROCESSORS
IDT79R4400

Very high-performance, highly integrated 64-bit CPU,
fully binary compatible with the R3000A. Combines
CPU, floating-'point and 16/32KB of cache, capable of over
50 VAX mips sustained performance

447PGA
179PGA

NOW

5.6

IDT79R3041

RISController, 2.5KB cache, R3000A core, 4-deep read/
write buffers, low-cost packaging, pin-compatible with R3051/52/81

84PLCC
100PF

NOW

5.2

IDT79R3051/52

RISControliers, 6KB or 10KB on-chip cache, R3000A
CPU core, and 4-deep read/write buffers, low-cost
84-pin packaging

84PLCC
84MJ

NOW

5.2

IDT79R3081

RISController, 20KB on-chip, R300 CPU core,
R3010A Floating Point Accelerator, 4-deep read/write
buffers, pin-compatible with R3041/51/52

84MJ
84FD
100PQFP

NOW

5.3

IDT79R4600

Very high-performance, highly integrated 64-bit CPU,
fully binary compatible with the R3000A . Combines CPU,
floating-point and 32KB of cache, capable of over 175 mips
sustained performance

NOW
179PGA
208 MQUAD

5.4

IDT79R4650

R4600 derivative capable of 66.7 Million Integer MultiplyAccumulate Operations/sec @ 133MHz and 175 mips sustained
performance. Combines CPU, floating-point and 16KB of cache.

208MQUAD

NOW

5.5

IDT79R4700

Pin-compatible with the R4600, the R4700 is an enhanced
version of the R4600. Combines CPU, floating-point and 32KB of
cache, capable of over 225 mips sustained performance

179PGA
208M QUAD

NOW

5.6

1.6

High-Speed CMOS RISC Microprocessor Family (Cont'd)

Part Number

Description

Avail.

Data
Book
Page

II

R3000 FAMILY EVALUATION KITS
IDT79S341

R3041 Family Evaluation Board. Complete, self-contained system requiring
only a power supply and simple terminal to be operational. Kit contains
R3041 CPU, 1MB of DRAM, IDT/sim monitor in EPROM, serial 1/0 ports.

NOW

7.5

IDT79S385A

R305X Family Evaluation Board~ Complete, self-contained system requiring
only a power supply and simple terminal to be operational. Kit contains
R3052E CPU, 1MB of DRAM, IDT/sim monitor in EPROM, serial 1/0 ports.
Supplied with all schematics, PAL equations and user's manual. Also includes
DOS version of the IDT/c compiler (see 7RS903) and a sample of the R3081.

NOW

7.4

IDT79S381

R3081 Family Evaluation Board. Complete, self-contained system requiring
only a power supply and simple terminal to be operational. Kit contains
R3081 CPU, 2MB of DRAM, IDT/sim monitor in EPROM, serial 1/0 ports.

NOW

7.6

IDT79S460

R4600 Family Evaluation Board. Complete, self-contained system requiring
only a power supply and simple terminal to be operational. Kit contains
R4600 CPU, 1MB of DRAM, IDT/sim monitor in EPROM, serial 1/0 ports.

NOW

7.7

R3000 FAMILY SOFTWARE DEVELOPMENT TOOLS
IDT79S901

IDT/sim System Integration Manager (see RISC SubSystems for description)

NOW

7.8

IDT79S903

IDT/c C-Compiler (see RISC SubSystems for description)

NOW

7.9

IDT79S909

IDT/kit Kernel Integration Toolkit (see RISC SubSystems for description)

NOW

7.10

Integrated RISC Design Solutions
IDT is committed to providing complete integrated RISC solutions by combining expertise in silicon process technology with leadership
products in development systems and software. Long an industry leader in producing the fastest static RAMs for cache memory and
high-speed logic for memory interface, IDT offers:
•

Dedicated RISC support chips

•

Development tools such as multi-hosted Cross Compilers

•

CPU and cache modules

•

Monitors and debuggers

RISC evaluation and prototyping vehicles

1.6

2

Rise SubSystems-Rise Without Risk ..... lOT Provides Total RiSe System Solutions!
Total Support
On-going support means on-time deliveries. IDT has on-going
vendor TOM programs with suppliers of critical components to
ensure on-time delivery of in-spec material. Our manufacturing
organization is experienced in building very high-speed boards
with tight tolerances and high-pin-count surface-mount components. And our design team is on-call to solve problems quickly if
difficulties arise during production. We provide total support-from
board design and software porting through production and testbecause our success depends on your success!

FASTER SYSTEMS: FASTER DESIGN CYCLES
Using RISC technology, you can build systems that will run rings
around an old x86 or 680xO design. IDT's RISC SubSystems
Division can help you get your design completed in record time.
IDT has proven RISC design and manufacturing experience that
you can rely on. Exploit our expertise by having IDT design AND
manufacture your board. Or integrate one of our pre-built, fullytested modules into your design.
Architectural Expertise
IDT brings together a unique combination of component knowledge, software skills, and board design experience as the foundation
for developing a board-level product that meets your needs. As
experienced system architects, we understand that component
knowledge alone is not enough-that the interface between hardware and software is critical to a successful design. We have spent
years honing our architectural expertise to include an in-depth
understanding of both the hardware and software issues so our
designs produce the performance you expect.

Modules
Our modules contain the RISC CPU, Floating Point Accelerator,
and all the cache memory. Most include clock control, interrupt and
initialization logic, and read and write buffers, as well. All the
components are surface-mounted on small, plug-in PC boards,
burned-in and tested at the rated speed. All the tricky timing, and
high-speed design is done and tested for you. The modules can be
plugged into motherboards containing main memory, 110, and the
rest of the system, all of which is relatively low-speed and is easy
to layout using conventional design techniques.

Fast Development Cycle
IDT uses the most advanced engineering tools in our hardware
development lab. We have qualified quick-turn PCB fab houses
and our own fully-equipped advanced manufacturing area, so new
fabs can be assembled and sent into debug in a matter of days. In
addition, IDT has developed the best software diagnostic tools
available for MIPS RISC debug. Spotting behavioral patterns in
malfunctioning systems and quickly identifying and fixing the
hardware or software problem is key to maintaining a time-critical
development cycle-and we want you to be first to market!

Custom Subsystems
For custom boards that meet your unique requirements, we can
develop a complete product specification, design the boards,
deliver prototypes, and provide production units in any quantities.
Many customers have found this to be a cost-effective way to
augment their own engineering resources, and to procure material
that exactly meets their needs without all the headaches of
purchasing, material control, and on-going product and manufacturing engineering.

Optimized Designs
IDT is a premier supplier of RISC assemblies. Our expertise in
handling layout, termination, and component selection issues is
unmatched, and we use the latest tools for PCB layout, routing and
design simulation. Our design team is fast and experienced,
coordinating component selection with availability of the latest
technology, and using ASICs where appropriate to improve performance and reduce space and cost. To date, we have designed and
produced more different MIPS RISC assemblies than anyone else,
optimizing every design for the highest possible performance per
dollar.

Model

Printer Controllers
IDT has designed and produced a number of printer controllers,
using both custom and standard hardware solutions. IDT's boardlevel products have been used to run Adobe PostScript PCl5
emulation, and Pipeline Associates' color PostScript emulation.
IDT is a licensee for Adobe's CPSI interpreter, and can develop a
flexible true Adobe solution in a variety of hardware and software
environments.
N

,

Description

Custom Desians
•
•
•
•

Plotter Controllers
Add-In Cards to EISNISA Bus
Add-in Cards for Macintosh
Laser Printer Controllers

•
•
•
•

Adobe CPSI PostScript Application Development
UNIXN Porting, and Driver Development
C-EXECUTIVEN Real Time OS
Interprocessor Communication between RISC Subsystem and Mac or PC

Software

1.6

TECHNOLOGY AND CAPABILITIES

fI

IDT... LEADING THE CMOS FUTURE
A major revolution is taking place in the semiconductor
industry today. A new technology is rapidly displacing older
NMOS and bipolar technologies as the workhorse of the '80s
and beyond. Thattechnology is high-speed CMOS. Integrated
Device Technology, a company totally predicated on and
dedicated to implementing high-performance CMOS products,
is on the leading edge of this dramatic change.
Beginning with the introduction of the industry's fastest
CMOS 2K x 8 Static RAM, lOT has grown into a company with
multiple divisions producing a wide range of high-speed
CMOS circuits that are, in almost every case, the fastest
available. These advanced products are produced with lOT's
proprietary CMOS technology, a twin-well, dry-etched, stepperaligned process utilizing progressively smaller dimensions.
From inception, lOT's product strategy has been to apply
the advantages of its extremely fast CMOS technology to
produce the integrated circuit elements required to implement
high-performance digital systems. lOT's goal is to provide the
circuits necessary to create systems which are far superior to
previous generations in performance, reliability, cost, weight,
and size. Many of the company's innovative product designs
offer higher levels of integration, advanced architectures,
higher density packaging and system enhancement features
that are establishing tomorrow's industry standards. The
company is committed to providing its customers with an everexpanding series ofthese high-speed, 10wer-powerlC solutions
to system design needs.
lOT's commitment, however, extends beyond state-of-theart technology and advanced products to providing the highest
level of customer service and satisfaction in the industry.

Manufacturing products to exacting quality standards that
provide excellent, long-term reliability is given the same level
of importance and priority as device performance. lOT is also
dedicated to delivering these high-quality advanced products
on time. The company would like to be known not only for its
technological capabilities, but also for providing its customers
with quick, responsive, and courteous service.
lOT's product families are available in both commercial and
military grades. As a bonus, commercial customers obtain the
benefits of military processing disciplines, established to meet
or exceed the stringent criteria of the applicable military
specifications.
lOT is the leading U.S. supplier of high-speed CMOS
circuits. The company's high-performance fast SRAM , FCT
logic, high-density modules, FIFOs, multi-port memories,
SiCMOS ECl I/O memories, RISC SubSystems, and the 32and 64-bit RISC microprocessor families complement each
other to provide high-speed CMOS solutions for a wide range
of applications and systems.
Dedicated to maintaining its leadership position as a stateof-the-art IC manufacturer, lOT will continue to focus on
maintaining its technology edge as well as developing a
broader range of innovative products. New products and
speed enhancements are continuously being added to each
ofthe existing product families, and additional productfamilies
are being introduced. Contact your lOT field representative or
factory marketing engineer for information on the most current
product offerings. If you're building state-of-the-art equipment,
lOT wants to help you solve your design problems.

2.1

fI

IDT MILITARY AND DESC-SMD PROGRAM
lOT is a leading supplier of military, high-speed CMOS
circuits. The company's high-performance Static RAMs, FCT
logic Family, Complex logic (ClP), FIFOs, Specialty
Memories (SMP), ECl 110 SiCMOS Memories, 32-bit RISC
Microprocessor, RISC Subsystems and high-density
Subsystems Modules product lines complement each other to
provide high-speed CMOS solutions to a wide range of
military applications and systems. Most of these product lines
offer Class B products which are fully compliant to the latest
revision of Mll-STO-883, Paragraph 1.2.1. In addition, lOT
offers Radiation Tolerant (RT), as well as Radiation Enhanced
(RE), products.
lOT has an active program with the Defense Electronic
Supply Center (DESC) to list all of IDT's military compliant
SMO
SRAM
84036
5962-88740
84132
5962-86015
5962-86859
5962-86705
5962-85525
5962-88552
5962-88662
5962-88611
. 5962-89891
5962-89892
5962-89690
5962-38294
5962-89692
5962-89712
5962-89790

lOT
6116
6116LA
6167
7187
6198/7198/7188
6168
7164
71256L
712568
71682L
7198
6198
6116
7164
7188
71982
71682

SMP

lOT

5962-86875
5962-87002
5962-88610
5962-88665
5962-89764
5962-91508
5962-91617
5962-91662
5962-93153

7130/7140
7132/7142
71338A171438A
7133LAl7143LA
7134
7006
7025
7024
70148

FIFO

lOT

5962-87531
5962-86846
5962-88669
5962-89568
5962-89536
5962-89863
5962-89523
5962-89666
5962-89942
5962-89943
5962-89567
5962-90715
5962-91677

7201 LA
72404L
72038
7204L
7202LA
72018A
72403L
7200L
72103L
72104L
7203L
72048
7205L

5962-93177
5962-92069
5962-92101
5962-93138
5962-92057
5962-93189
5962-91757

devices on Standard Military Drawings (SMO). The SMD
program allows standardization of militarized products and
reduction of the proliferation of non-standard source control
drawings. This program will go far toward reducing the need
for each defense contractor to make separate specification
control drawings for purchased parts. lOT plans to have
SMDs for many of its product offerings. Presently, lOT has 88
devices which are listed or pending listing. The devices are
from IDT's SRAM, FCT logic family, Complex logic (ClP),
FIFOs and Specialty Memories (SMP) product families. lOT
expects to add another 20 devices to the SMO program in the
near future. Users should contact either lOT or OESC for
current status of products in the SMO program.

SMO
7206L
72141L
72215LB
72220L
72225LB
72245LB
72200L

CLP

lOT

5962-87708
5962-88533
5962-88613
5962-88643
5962-86873
5962-87686
5962-88733
5962-92122

39C10B & C
49C460AlB/C
39C60/A
49C410
7216L
7217L
7210
49C465/A

LOGIC

lOT

5962-87630
5962-87629
5962-86862
5962-87644
5962-87628
5962-87627
5962-87654
5962-87655
5962-87656
5962-89533
5962-89506
5962-88575
5962-88608
5962-88543
5962-88640
5962-88639
5962-88656
5962-88657
5962-88674
5962-88661
5962-88736
5962-88775
5962-89508
5962-89665
5962-88651
5962-88653

54 FCT244/A
54FCT245/A
54FCT299/A
54FCT373/A
54 FCT374/A
54FCT377/A
54FCT138/A
54FCT240/A
54FCT273/A
54FCT861AlB
54FCT827 AlB
54FCT841 AlB
54FCT821 AlB
54FCT521/A
54FCT161/A
54 FCT573/A
54FCT823A1B
54FCT163/A
54FCT825A1B
54FCT863A1B
29 FCT520AlB
54FCT646/A
54FCT139/A
54FCT824A1B
54FCT533/A
54FCT645/A

2.2

5962-88654
5962-88655
5962-89767
5962-89766
5962-89733
5962-89732
5962-89652
5962-89513
5962-89731
5962-89730
5962-90901
5962-92205
5962-92157
5962-92233
5962-92208
5962-92209
5962-92210
5962-90669
5962-92213
5962-92232
5962-92203
5962-92214
5962-92211
5962-92215
5962-92216
5962-92217
5962-92218
5962-92219
5962-92212
5962-92234
5962-92236
5962-92220
5962-92237
5962-92221
5962-92238
5962-92222
5962-92244
5962-92223
5962-92246
5962-92225
5962-92229
5962-92230
5962-92247
Rise
5962-94550

SMO
54FCT640/A
54 FCT534/A
54 FCT540/A
54FCT541/A
54FCT191/A
54FCT241/A
54FCT399/A
54 FCT574/A
54FCT833A1B
54 FCT543/A
29FCT52A1B/C
29FCT520AT/BT/CT
49 FCT8051Al8061A
54FCT138T/AT/CT
54FCT157T/AT/CT
54FCT161 T/AT/CT
54FCT163T/AT/CT
54FCT193/A
54 FCT240T/AT/CT
54FCT241T/AT/CT
54FCT244T/AT/CT
54FCT245T/AT/CT
54FCT257T/AT/CT
54 FCT273T/AT/CT
54FCT299T/AT/CT
54FCT373T/AT/CT
54 FCT374T/AT/CT
54 FCT377T/AT/CT
54FCT399T/AT/CT
54FCT521T/AT/BT/CT
54FCT534T/AT/CT
54FCT540T/AT/CT
54FCT541T/AT/CT
54FCT543T/AT/CT
54FCT573T/AT/CT
54 FCT574T/AT/CT
54FCT645T/AT/CT
54FCT646T/AT/CT
54FCT652T/AT/CT
54FCT821 AT/BTICT
54FCT823AT/BT/CT
54 FCT825AT/BT/CT
54FCT827AT/BT/CT
lOT
79R3081E

· SMO
SRAM
84036
5962-88740
84132
5962-86015
5962-86859
5962-86705
5962-85525
5962-88552
5962-88662
5962-88611
5962-89891
5962-89892
5962-89690
5962-38294
5962-89692
5962-89712
5962-89790

lOT
6116
6116LA
6167
7187
61981719817188
6168
7164
71256L
712568
71682L
7198
6198
6116
7164
7188
71982
71682

SMP
5962-86875
5962-87002
5962-88610
5962-88665
5962-89764
5962-91508
5962-91617
5962-91662
5962-93153

lOT
713017140
713217142
71338A171438A
7133LAl7143LA
7134
7006
7025
7024
70148

FIFO
5962-87531
5962-86846
5962-88669
5962-89568
5962-89536
5962-89863
5962-89523
5962-89666
5962-89942
5962-89943
5962-89567
5962-90715
5962-91677
5962-93177
5962-92069
5962-92101
5962-93138
5962-92057
5962-93189
5962-91757

lOT
7201 LA
72404L
72038
7204L
7202LA
72018A
72403L
7200L
72103L
72104L
7203L
72048
7205L
7206L
72141L
72215LB
72220L
72225LB
72245LB
72200L

CLP
5962-87708
5962-88533
5962-88613
5962-88643
5962-86873
5962-87686
5962-88733
5962-92122

lOT
39C10B & C
49C460AlB/C
39C60/A
49C410
7216L
7217L
7210
49C465/A

LOGIC
5962-87630
5962-87629
5962-86862
5962-87644
5962-87628
5962-87627
5962-87654
5962-87655
5962-87656
5962-89533
5962-89506
5962-88575
5962-88608
5962-88543
5962-88640
5962-88639
5962-88656
5962-88657
5962-88674
5962-88661
5962-88736
5962-88775
5962-89508
5962-89665
5962-88651
5962-88653
5962-88654
5962-88655
5962-89767
5962-89766
5962-89733
5962-89732
5962-89652
5962-89513
5962-89731
5962-89730
5962-90901
5962-92205
5962-92157
5962-92233
5962-92208
5962-92209
5962-92210
5962-90669
5962-92213
5962-92232
5962-92203
5962-92214
5962-92211
5962-92215
5962-92216
5962-92217
5962-92218
5962-92219
5962-92212
5962-92234
5962-92236
5962-92220
5962-92237
5962-92221
5962-92238
5962-92222

lOT
54FCT244/A
54FCT245/A
54FCT299/A
54FCT373/A
54FCT374/A
54FCT377/A
54FCT138/A
54FCT240/A
54FCT273/A
54FCT861 AlB
54FCT827AlB
54FCT841 AlB
54FCT821 AlB
54FCT521/A
54FCT161/A
54FCT573/A
54FCT823A1B
54FCT163/A
54FCT825A1B
54FCT863A1B
29FCT520AlB
54FCT646/A
54FCT139/A
54FCT824A1B
54FCT533/A
54FCT645/A
54FCT640/A
54FCT534/A
54FCT540/A
54FCT541/A
54FCT191/A
54FCT241/A
54FCT399/A
54FCT574/A
54FCT833A1B
54FCT543/A
29FCT52A1B/C
29FCT520AT/BT/CT
49FCT805/A1806/A
54FCT138T/AT/CT
54FCT157T/AT/CT
54FCT161T/AT/CT
54FCT163T/AT/CT
54FCT193/A
54FCT240T/AT/CT
54 FCT241T/AT/CT
54FCT244T/AT/CT
54FCT245T/AT/CT
54FCT257T/AT/CT
54FCT273TI ATICT
54FCT299TI ATICT
54FCT373T/AT/CT
54FCT374T/AT/CT
54FCT377T/AT/CT
54FCT399T/AT/CT
54FCT521T/AT/BT/CT
54FCT534T/AT/CT
54FCT540T/AT/CT
54FCT541T/AT/CT
54FCT543T/AT/CT
54FCT573T/AT/CT
54FCT574T/AT/CT

2.2

5962-92244
5962-92223
5962-92246
5962-92225
5962-92229
5962-92230
5962-92247

54FCT645T/AT/CT
54FCT646T/AT/CT
54FCT652T/AT/CT
54FCT821 ATIBTICT
54FCT823AT/BT/CT
54FCT825ATIBTICT
54FCT827AT/BT/CT

RISC
5962-94550

lOT
79R3081E

fI

2

RADIATION HARDENED TECHNOLOGY
On an order by order basis lOT can manufacture and
supply radiation hardened products for military/aerospace
applications. Utilizing special processing and starting materials,
lOT's radiation hardened devices survive in hostile radiation
environments. In Total Dose, Dose Rate, and environments
where single event upset is of concern, lOT products are
designed to continue functioning without loss of performance.
lOT can supply most of its products on these processes. Total

Dose radiation testing is performed in-house on an ARACOR
X-Ray system. External facilities are utilized for device
research on gamma cell, LlNAC and other radiation equipment.
lOT has an on-going research and development program for
improving radiation handling capabilities (See "lOT Radiation
Tolerant/Enhanced Products for Radiation Environments" in
Section 3) of lOT products/processes.

KNOWN GOOD DIE
Emerging high performance electronic systems require
smaller and smaller form-factors. lOT is meeting these design
challenges by offering Known Good Die (KGO) in addition to
its broad array of small form-factor packages. The lOT KGO
manufacturing process enables lOT to offer die that have
received the same electrical tests, burn-in, and speed sorting
at elevated temperatures as shipped packaged products. Via
lOT KGO, users are able to manufacture cost-efficient and
reliable multi-chip modules (MCMs), hybrids, and other high-

density interconnect products. All lOT KGO, at the completion
of their test flow, receive 100% die visual inspection and are
packed within Gel-Pak™ containers. The Gel-Pak™ containers
are then placed in vacuum sealed ESO wrappers prior to
shipping. Delivered KGO products have superior yield, quality,
and reliability over standard raw die offerings. Most lOT
products can be offered as "KGO", and commercial, industrial
or military temperatures can be considered.

2.3

IDT LEADING EDGE CEMOS TECHNOLOGY
THE PRODUCTIVITY REVOLUTION
New microprocessor-based systems enhance productivity
by improving the accessibility and usability of information. By
connecting systems through a network, data can be transmitted instantly, anywhere in the world. Using affordable computing systems, information can be located, retrieved, analyzed,
and displayed as needed.
The systems that provide these capabilities are built around
the microprocessor, and lOT's products maximize the potential of these microprocessor-based systems. As sales of these
productivity-enhancing systems grow, so do the markets for
lOT products.

INNOVATIVE PRODUCTS FOR MORE PRODUCTIVE SYSTEMS
lOT markets products from four product groups: SRAMs,
Specialty Memory Products, Logic products, and RISC Microprocessors.
Our strategy is to define, develop, and manufacture products that help our customers deliver greater value to their
customers. We develop products in partnership with customers who are leaders in markets that fuel the productivity
revolution, such as high-performance desktop and server
computing, data communications and networking, and office
automation. These customers use our products to build systems that are faster, less costly, and more productive.
Our customers are also building systems that are energyefficient. Designers are developing 3.3V systems to comply
with the governmental Energy Star requirements. We have a
competitive advantage because our CMOS VII technology
was specifically designed to maintain higher speeds at this
lower voltage.
Customers using high-performance microprocessors to
build desktop computers and file servers can improve the
performance of their products by incorporating cache memory
systems. Cache memory systems are constructed with highspeed SRAMs, cache tag memories, and control logic. We are
a recognized technology leader in SRAMs and the world's
leading supplier of cache tag memories. Today, we supply
these products both as discrete components and in the form
of complete high-density cache memory modules used with
PowerPCTM, Intel 486™, Pentium™ processor, and our own
RISC microprocessors. We are working with manufacturers of
both the microprocessors and their associated chipsets to
develop new cache memory products that will maximize the
performance of future microprocessor-based systems.
Customers building digital data communications and networking equipment use FIFO and dual-port memory products
that are designed for these applications. FI FOs and dual-ports
are uniquely suited to exchanging data between systems that
operate at different speeds or use different protocols, a
R4600 and Orion are trademarks of Integrated Device Technology. Inc.
PowerPC is a trademark of Motorola
Pentium processor and i486 are trademarks of Intel Corporation
Windows NT is a trademark of Microsoft Corporation
UNIX is a registered trademark of AT&T

2.4

common requirement in communications systems. We are
the market leader in these SMP product areas, and we have
introduced the industry's largest number of product and technology innovations over the years. Development work is now
under way to design a family of products for the emerging ATM
(Asynchronous Transfer Mode) market, which is expected to
grow dramatically over the next several years.
Every high-performance system needs high-speed logic
parts to connect memories, microprocessors, communications circuits, and other system components. We have been
the performance leader in high-speed FCT logic devices since
we pioneered these products in 1985, and we currently offer
more than 150 different logic products. We have also introduced two new ultra-small packaging choices for our logic
products, ideal for use in compact desktop and portable
systems, as well as in PCMCIA cards, which are credit-card
sized modules that add functionality to personal computers.
Customers who build high-performance office automation
and communications systems are taking advantage of our
family of 32-bit and 64-bit software-compatible RISC microprocessors, based on the extendable architecture developed
by MIPS Technologies. The 20+ different microprocessors in
our RISC family offer customers a wider range of price!
performance choices than competing microprocessor families. Software compatibility allows designers to choose one
microprocessor for a particular product and then easily upgrade to a higher-performing version, in many cases simply by
removing one device and plugging in another. Our 32-bit RISC
microprocessor products are winning acceptance in a variety
of embedded applications, including laser printers, network
routers, and graphics display terminals.
In fiscal 1994, we introduced our 64-bit R4600™ Orion™
processor. This microprocessor provides leading-edge performance for embedded applications, such as laser printers
and networking systems, and is also used in file servers and
workstations that run UNIX® and Microsoft's new Windows
NTTM operating systems.

ADVANCING OUR OWN PRODUCTIVITY
We participate in the productivity revolution both as a
technology enabler and as a beneficiary. While our products
enhance the productivity of our customers' microprocessorbased systems, we improve our own internal productivity by
developing new manufacturing technologies, re-engineering
workflows, and by adopting new electronic systems.
One of the primary ways we increase internal productivity
is by developing and implementing advanced technologies.
New process technologies result in smaller die, and new
production equipment allows the use of larger wafers. The
combination of smaller die and larger wafers allows us to
generate significantly more devices per wafer. Migrating to an
advanced 0.6-micron CMOS fabrication process in fiscal
1994 not only resulted in smaller die, it also improved product
performance, increased yields, and lowered unit costs. Our
new CMOS VIII 0.5-micron process is expected to extend our

fI

process technology momentum.
Because we have our own fabrication facilities, we control
critical manufacturing operations, giving us a competitive
advantage as we continue to improve our productivity. IDT
has two sub-micron 6" wafer fabrication facilities, located in
San Jose and Salinas, California, and a high-volume assembly and test facility in Penang, Malaysia. To support future
growth, we have built a new sUb-micron 8" wafer fabrication
facility in Hillsboro, Oregon that will be fully operational in fiscal
1997, and an additional 40,000-square-foot building for test
and assembly in Penang.
Manufacturing productivity is also improved by adjusting
work schedules to increase the output from equipment already in place and improving product development cycles.
Updated computer-aided design tools shorten product design
times and improve the functionality of new product prototypes.
For example, the R4600 Orion processor was designed by
Quantum Effect Design, Inc., an IDTaffiliate operating on-site,
in just 21 months, which is a remarkably short development
cycle for such a complex product.
Improvements in quality are the direct result of improvements in productivity. Our manufacturing quality levels have

been improving for several years. In fiscal 1993, IDTwas one
of the first semiconductor companies to achieve ISO 9000
registration for wafer fabrication activities. ISO 9000 is a
worldwide quality systems standard, and certification provides an important competitive advantage in both domestic
and international markets. All of our manufacturing facilities
are now ISO 9000 certified.
Customer service and support have been directly enhanced by many of our productivity improvements. New
planning and scheduling systems allow us to improve our
efficiency and predictability for meeting delivery commitments
to customers. Expanded computer systems allow the migration of order services to field sales offices, bringing support
closer to the customer. Increased use of EDI (Electronic Data
Interchange) allows customers to directly enter orders and
check order status, resulting in more timely information with
less paperwork.
Improving productivity continues to be a key issue for
technology companies. By continuing to improve internal
productivity and manufacture quality products that support the
productivity revolution, we expect to enhance the value of our
company to our shareholders, our employees, and our customers.

2.4

2

SUPERIOR QUALITY AND RELIABILITY
Maintaining the highest standards of quality in the industry
on all products is the basis of Integrated Device Technology's
manufacturing systems and procedures. From inception,
quality and reliability are built into all of IDT's products. Quality
is "designed in" at every stage of manufacturing - as opposed
to being "tested-in" later - in order to ensure impeccable
performance.
Dedicated commitment to fine workmanship, along with
development of rigid controls throughout wafer fab, device
assembly and electrical test, create inherently reliable products.
Incoming materials are subjected to careful inspections. Quality
monitors, or inspections, are performed throughout the
manufacturing flow.
IDT military grade monolithic hermetic products are designed
to meet or exceed the demanding Class B reliability levels of
MIL-STD-883 and MIL-I-38535, as defined by Paragraph
1.2.1 of MIL-STD-883.
Product flow and test procedures for all monolithic hermetic
military grade products are in accordance with the latest
revision and notice of MIL-STD-883. State-of-the-art production
techniques and computer-based test procedures are coupled
with tight controls and inspections to ensure that products
meet the requirements for 100% screening. Routine quality
conformance lot testing is performed as defined in MIL-STD883, Methods 5004 and 5005.
For IDT module products, screening of the fully assembled
substrates is performed, in addition to the monolithic level
screening, to assure package integrity and mechanical

2.5

reliability. All modules receive 100% electrical tests (DC,
functional and dynamic switching) to ensure compliance with
the "subsystem" specifications.
By maintaining these high standards and rigid controls
throughout every step of the manufacturing process, IDT
ensures that commercial, industrial and military grade products
consistently meet customer requirements for quality, reliability
and performance.

fI
I

SPECIAL PROGRAMS

s.

Class
IDT also has manufacturing, screening and test
capabilities in-house (except X-ray and some Group D tests)
to perform Class S processing per MIL-STD-883 and has
supplied Class S products on several programs.
Radiation Hardened. IDT has developed and supplied
several levels of radiation hardened products for military/
aerospace applications to perform at various levels of dose
rate, total dose, single event upset (SEU), upset and latchup.
IDT products maintain nearly their same high-performance
levels built to these special process requirements. The
company has in-house radiation testing capability used both
in process development and testing of deliverable product.
IDT also has a separate group within the company dedicated
to supplying products for radiation hardened applications and
to continue research and development of process and products
to further improve radiation hardening capabilities.

QUALITY AND RELIABILITY

II

QSP-QUALlTY, SERVICE AND PERFORMANCE
Quality from the beginning, is the foundation for lOT's
commitment to supply consistently high-quality products to
our customers. lOT's quality commitment is embodied in its all
pervasive Total Quality Commitment (TQC) process. Everyone
who influences the quality of the product-from the designer to
the shipping clerk-is committed to constantly improving the
quality of their actions.

lOT QUALITY PHILOSOPHY
"To make quantitative constant improvement in the quality
of our actions that result in the supply of leadership products
in conformance to the requirements of our customers. "

lOTs ASSURANCE STRATEGY FOR TQC
Measurable standards are essential to the success of TQC.
All the processes contributing to the final quality of the product
need to be monitored, measured and improved upon through
the use of statistical tools.
DEVELOPMENT

Standardization
Implementing policies, procedures and measurement
techniques that are common across different operational
areas.
Documentation
Documenting and training in policies, procedures,
measurement techniques and updating through
characterization/ capability studies.
Productivity Improvement
Using constant improvement teams made up from
employees at all levels of the organization.
Leadership
Focusing on quality as a key business parameter and
strategic strength.
Total Employee Participation
Incorporating the TQC process into the lOT Corporate
Culture.

I
Customer Service
Supporting the customer, as a partner, through
performance review and pro-active problem solving.

FAB

I
PRODUCT FLOW

ASSEMBLY

I
People Excellence
Committing to growing, motivating and retaining people
through training, goal setting, performance measurement
and review.

TEST

I
SHIP
Our customers receive the benefit of our optimized systems.
Installed to enhance quality and reliability, these systems
provide accurate and timely reporting on the effectiveness of
manufacturing controls and the reliability and quality
performance of lOT products and services.
ORDER ENTRY

I
PRODUCTION CONTROL
SERVICE FLOW

I
SHIPPING

I
CUSTOMER SUPPORT
These systems and controls concentrate on TQC byfocusing
on the following key elements:
Statistical Techniques
Using statistical techniques, including Statistical Process
Control (SPC) to determine whether the product!
processes are under control.

3.1

PRODUCT FLOW
Product quality starts here. lOT has mechanisms and
procedures in place that monitor and control the quality of our
development activities. From the calibration of design capture
libraries through process technology and product
characterization that establish whether the performance,
ratings and reliability criteria have been met. This includes
failure analysis of parts that will improve the prototype product.
At the pre-production stage once again in-house qualification
tests assure the quality and reliability of the product. All
specifications and manufacturing flows are established and
personnel trained before the product is placed into production.
Manufacturing
To accomplish continuous improvement during the
manufacturing stage, control items are determined for major
manufacturing conditions. Data is gathered and statistical
techniques are used to control specific manufacturing
processes that affect the quality of the product.

II

Customer Support
I DT has a worldwide network of sales offices and Technical
Development Centers. These provide local customer support
on business transactions, and in addition, support customers
on applications information, technical services, benchmarking
of hardware solutions, and demonstration of various
Development Workstations.
The key to continuous improvement is the timely resolution
of defects and implementation of the corrective actions. This
is no more important than when product failures are found by
a customer. When failures are found atthe customer's incoming
inspection, in the production line, or the field application, the
Division Quality Assurance group is the focal point for the
investigation of the cause of failure and implementation of the
corrective action. IDT constantly improves the level of support
we give our customers by monitoring the response time to
customers that have detected a product failure. Providing the
customer with an analysis of the failure, including corrective
actions and the statistical analysis of defects, brings CQI full
circle-full support of our customers and their designs with
high-quality products.

In-process and final inspections are fed back to earlier
processes to improve product quality. All product is burnedin (where applicable) before 100% inspection of electrical
characteristics takes place.
Products which pass final inspection are then subject to
Quality Assurance and Reliability Tests. This data is used to
improve manufacturing processes and provide reliability
predictions of field applications.

Inventory and Shipping
Controls in shipping focus on ensuring parts are identified
and packaged correctly. Care is also taken to see that the
correct paperwork is present and the product being shipped
was processed correctly.

SERVICE FLOW
Quality not only applies to the product but to the quality -of
-service we give our customers. Services is also constantly
monitored for improvement.

Order Procedures
Checks are made at the order entry stage to ensure the
correct processing of the Customer's product. Afterverification
and data entry the Acknowledgements (sent to Customers)
are again checked to ensure details are correct. As part of the
TQC process, the results of these verifications are analyzed
using statistical techniques and corrective actions are taken.

SUMMARY
In 1990, IDT made the commitment to "Leadership through
Quality, Service, and Performance Products".
We believe by following that credo IDT and our cusotmers
will be successful in the coming decade. With the
implementation of the TQC strategy within the company, we
will satisfy our goal...
"Leadership through Quality, Service and Performance
Products".

Production Control
Production Control (P.C.) is responsible for the flow and
logistics of material as it moves through the manufacturing
processes. The quality of the actions taken by P.C. greatly
impinges on the quality of service the customer receives.
Because many of our customers have implemented Just-inTime (JIT) manufacturing practices, I DT as a supplier also has
to adopt these same disciplines. As a result, employees
receive extensive training and the performance level of key
actions are kept under constant review. These key actions
include:
Quotation response and accuracy.
Scheduling response and accuracy.
Response and accuracy of Expedites.
Inventory, management, and effectiveness.
On time delivery.

3.1

2

lOT QUALITY CONFORMANCE PROGRAM
A COMMITMENT TO QUALITY
Integrated Device Technology's monolithic assembly
products are designed, manufactured and tested in accordance
with the strict controls and procedures required by Military
Standards. The documentation, design and manufacturing
criteria of the Quality and Reliability Assurance Program were
developed and are being maintained to the most current
revisions of MIL-38S1 0 as defined by paragraph 1.2.1 of MILSTD-883 and MIL-STD-883 requirements.
Product flow and test procedures for all Class B monolithic
hermetic Military Grade microcircuits are in full compliance
with paragraph 1.2.1 of MIL-STD-883. State-of-the-art
production techniques and computer-based test procedures
are coupled with stringent controls and inspections to ensure
that products meet the requirements for 100% screening and
quality conformance tests as defined in MIL-STD-883, Methods
S004 and SOOS.
Product flow and test procedures for all plastic and
commercial hermetic products are in accordance with industry
practices for producing highly reliable microcircuits to ensure
that products meet the I DT requirements for 100% screening
and quality conformance tests.
By maintaining these high standards and rigid controls
throughout every step of the manufacturing process, IDT
ensures that our products consistently meet customer
requirements for quality, reliability and performance.

4.

Wire Bond Monitor: Product samples are routinely
subjected to a strength test per Method 2011, Condition
D, to ensure the integrity of the lead bond process.

5.

Pre-Cap Visual: Before the completed package is
sealed, 100% of the product is visually inspected to
Method 2010, Condition B criteria.

6.

Environmental Conditioning: 100% of the sealed
product is subjected to environmental stress tests.
These thermal and mechanical tests are designed to
eliminate units with marginal seal, die attach or lead
bond integrity.

7.

Hermetic Testing: 100% of the hermetic packages
are subjected to fine and gross leak seal tests to
eliminate marginally sealed units or units whose
seals may have become defective as a result of
environmental conditioning tests.

8.

Pre-Burn-In Electrical Test: Each product is 100%
electrically tested at an ambient temperature of +2SoC
to IDT data sheet or the customer specification.

9.

Burn-In: 100% of the Military Grade product is
burned-in under dynamic electrical conditions to the
time and temperature requirements of Method 101S,
Condition D. Except for the time, Commercial Grade
product is burned-in as applicable to the same
conditions as Military Grade devices.

10.

Post-Burn-In Electrical: After burn-in, 100% of the
Class B Military Grade product is electrically tested to
IDT data sheet or customer specifications over theSsoC to + 12SoC temperature range. Commercial
Grade products are sample tested to the applicable
temperature extremes.

11.

Mark: All product is marked with product type and lot
code identifiers. MIL-STD-883 compliant Military
Grade products are identified with the required
compliant code letter.

12.

Quality Conformance Tests: Samples ofthe Military
Grade product which have been processed to the
100% screening tests of Method S004 are routinely
subjected to the quality conformance requirements of
Method SOOS.

SUMMARY
Monolithic Hermetic Package Processing Flow(l)
Refer to the Monolithic Hermetic Package Processing Flow
diagram. All test methods refer to MIL-STO-883 unless
otherwise stated.
1.
Wafer Fabrication: Humidity, temperature and
particulate contamination levels are controlled and
maintained according to criteria patterned after Federal
Standard 209, Clean Room and Workstation
Requirements. All critical workstations are maintained
at Class 100 levels or better.
Wafers from each wafer fabrication area are subjected
to Scanning Electron Microscope analysis on a periodic
basis.
2.

Die Visuallnspection: Wafers are cut and separated
and the individual die are 100% visually inspected to
strict IDT-defined internal criteria.

3.

Die Shear Monitor: To ensure die attach integrity,
product samples are routinely subjected to a shear
strength test per Method 2019.

NOTE:
1. For quality requirements beyond Class B levels such as SEM analysis, X-Ray inspection. Particle Impact Noise Reduction (PIND) test. Class S screening
or other customer specified screening flows, please contact your Integrated Device Technology sales representative.

3.2

II

SUMMARY
Monolithic Plastic Package Processing Flow
Refer to the Monolithic Plastic Package Processing Flow
diagram. All test methods refer to MIL-STD-883 unless
otherwise stated.
1.
Wafer Fabrication: Humidity, temperature and
particulate contamination levels are controlled and
maintained according to criteria patterned after Federal
Standard 209, Clean Room and Workstation
Requirements. All critical workstations are maintained
at Class 100 levels or better.

6.

Post Mold Cure: Plastic encapsulated devices are
baked to ensure an optimum polymerization of the
epoxy mold compound so as to enhance moisture
resistance characteristics.

7.

Pre-Burn-In Electrical: Each product is 100%
electrically tested at an ambient temperature of +25°C
to lOT data sheet or the customer specification.

8.

Burn-In: Except for MSI Logic family devices where
it may be obtained as an option, all Commercial
Grade plastic package products are burned-in for 16
hours at +125°C minimum (or equivalent), utilizing
the same burn-in conditions as the Military Grade
product.

9.

Post-Burn-In Electrical: After burn-in, 100% of the
plastic product is electrically tested to lOT data sheet
or customer specifications at the maximum
temperature extreme. The minimum temperature
extreme is tested periodically on an audit basis.

10.

Mark: All product is marked with product type and lot
code identifiers. Products are identified with the
assembly and test locations.

11.

Quality Conformance Inspection: Samples of the
plastic product which have been processed to the
100% screening requirements are subjected to the
Periodic Quality Conformance Inspection Program.
Where indicated, the test methods are patterned after
MIL-STO-883 criteria.

Topside silicon nitride passivation is all applied to all
wafers for better moisture barrier characteristics.
Wafers from each wafer fabrication area are subjected
to Scanning Electron Microscope analysis on a periodic
basis.
2.

Die Visual Inspection: Wafers are 100% visually
inspected to strict lOT defined internal criteria.

3.

Die Push Test: To ensure die attach integrity,
product samples are routinely subjected to die push
tests, patterned after MIL-STO-883, Method 2019.

4.

5.

Wire Bond Monitor: Product samples are routinely
subjected to wire bond pull and ball shear tests to
ensure the integrity ofthe wire bond process, patterned
after MIL-STO-883, Method 2011, Condition O.
Pre-Cap Visual: Before encapsulation, all product
lots are visually inspected (using LTPO 5 sampling
plan) to criteria patterned after MIL-STO-883, Method
2010, Condition B.

3.2

2

TABLE 1
This table defines the device class screening procedures for lOT's high reliability products in conformance with MIL-STO-883C.

Monolithic Hermetic Package Final Processing Flow
CLASS-S
OPERATION

TEST METHOD

CLASS-C(1)

CLASS-B
ROMT

TEST METHOD

ROMT

TEST METHOD

ROMT

BURN-IN

1015 Condo 0,
240 Hrs @ 125°C or
equivalent

100%

1015 Condo 0,
160 Hrs. @ 125°C
min. or equivalent

100%

Per applicable
device specification

100%

PORT BURN-IN
ELECTRICAL:
Static (DC), Functional
and Switching (AC)

Per applicable
device specification
+25, -55 and 125°C

100%

Per applicable
device specification
+25, -55 and 125°C

100%

Per applicable (2)
device specification

100%

Group A ELECTRICAL:
Static (DC, Functional
and Switching (AC)

Per applicable
device specification
and 5005

Sample

Per applicable
device specification
and 5005

Sample

Per applicable (2)
device specification

Sample

MARK/LEAD
STRAIGHTENING

lOT Spec

100%

lOT Spec

100%

lOT Spec

100%

FINAL ELECTRICAL
TEST

Per applicable
device specification
+25°C

100%

Per applicable
device specification
+25°C

100%

Per applicable
device specification
+25°C

100%

FINAL VISUAUPACK

lOT Spec

100%

lOT Spec

100%

lOT Spec

100%

QUALITY
CONFORMANCE
INSPECTION

5005 Group B, C, 0

Sample

lOT Spec

Sample

QUALITY SHIPPING
INSPECTION
(Visual/Plant Clearance)

lOT Spec

100%

lOT Spec

100%

Sample

100%

5005 Group B, C, 0

lOT Spec

NOTES:
1. Class-C = lOT commercial spec. for hermetic and plastic packages
2. Typical O°C, 70°C, Extended -55°C +125°C

3.2

3

II

RADIATION TOLERANT/ENHANCED/HARDENED PRODUCTS FOR
RADIATION ENVIRONMENTS
INTRODUCTION

DEVICE ENHANCEMENTS

The need for high-performance CMOS integrated circuits
in military and space systems is more critical today than ever
before. The low power dissipation that is achieved using
CMOS technology, along with the high complexity and density
levels, makes CMOS the nearly ideal component for all types
of applications.
Systems designed for military or space applications are
intended for environments where high levels of radiation may
be encountered. The implication of a device failure within a
military or space system clearly is critical. IDT has made a
significant contribution toward providing reliable radiationtolerant systems by offering integrated circuits with enhanced
radiation tolerance. Radiation environments, IDT process
enhancements and device tolerance levels achieved are
described below.

Of the four radiation environments above, IDT has taken
considerable data on Total Dose Accumulation. IDT has
developed a process that significantly improves the radiation

Radiation
Category

Primary
Particle

Source

Gamma

Space or
Nuclear
Event

Permanent

Dose Rate

Photons

Nuclear
Event

Temporary
Upset of Logic
State or
Latch-up

SEU

Cosmic
Rays

Space

Temporary
Upset of
Logic State

Neutron

Neutrons

Nuclear
Event

Device Leakage
Due to Silicon
Lattice Damage

THE RADIATION ENVIRONMENT
There are four different types of radiation environments
that are of concern to builders of military and space systems.
These environments and their effects on the device operation,
summarized in Figure 1, are as follows:
Total Dose Accumulation refers to the total amount of
accumulated gamma rays experienced by the devices in the
system, and is measured in RADS (SI) for radiation units
experienced at the silicon level. The physical effect of gamma
rays on semiconductor devices is to cause threshold shifts (Vt
shifts) of both the active transistors as well as the parasitic field
transistors. Threshold voltages decrease as total dose is
accumulated; at some point, the device will begin to exhibit
parametric failures as the input/output and supply currents
increase. At higher radiation accumulation levels, functional
failures occur. In memorycircuits, however, functional failures
due to memory cell failure often occur first.
Burst Radiation or Dose Rate refers to the amount of
radiation, usually photons or electrons, experienced by the
devices in the system due to a pulse event, and is measured
in RADS (Si) per second. The effect of a high dose rate or
burst of radiation on CMOS integrated circuits is to cause
temporary upset of logic states and/or CMOS latch-Up. Latchup can cause permanent damage to the device.
Single Event Upset (SEU) is a transient logic state change
caused by high-energy ions, such as energetic cosmic rays,
striking the integrated circuits. As the ion passes through the
silicon, charge is either created through ionization or direct
nuclear collision. If collected by a circuit node, this excess
charge can cause a change in logic state of the circuit.
Dynamic nodes that are not actively held at a particular logic
state (dynamic RAM cells for example) are the most susceptible.
These upsets are transient, but can cause system failures
known as "soft errors."
Neutron Irradiation will cause structural damage to the
silicon lattice which may lead to device leakage and, ultimately,
functional failure.

Effect

Total Dose

",olU OIW U"

Figure 1.

tolerance of its devices within these environments. Prevention
of SEU failures is usually accomplished by system-level
considerations, such as Error Detection and Correction (EDC)
circuitry, since the occurrence of SEUs is not particularly
dependent on process technology. Through IDT's customer
contracts, SEU has been gathered on some devices. Little is
yet known about the effects of neutron-induced damage. For
more information on SEU testing, contact lOT's Radiation
Hardened Product Group.
Enhancements to lOT's standard process are used to
create radiation enhanced and tolerant processes. Field and
gate oxides are "hardened" to make the device less susceptible
to radiation damage by modifying the process architecture to
allow lower temperature processing. Device implants and Vts
adjustments allow more Vt margin. In addition to process
changes, lOT's radiation enhanced process utilizes epitaxial
substrate material. The use of epi substrate material provides
a lower substrate resistance environment to create latch-up
free CMOS structures.

RADIATION HARDNESS CATEGORIES
Radiation Enhanced (RE) or Radiation Tolerant ('RT)
versions of IDT products follow IDT's military product data
sheets whenever possible (consultfactory). IDT's Total Dose
Test plan exposes a sample of die on a wafer to a particular
Total Dose level via ARACOR X-Ray radiation. This Total
Dose Test plan can qualify wafers to a Total Dose level. Only
wafers with sampled die that pass Total Dose level tests are
3.3

assembled and used for orders (consult factory for more
details on Total Dose sample testing). With regard to Total
Dose testing, clarifications/exceptions to MIL-STD-883,
Methods 5005 and 1019 are required. Consult factory for
more details.
The 'RE and 'RT process enhancements enable IDT to
offer integrated circuits with varying grades of radiation
tolerance or radiation "hardness".
• Radiation Enhanced process uses Epi wafers and is able
to provide devices that can be Total Dose qualified (if
desired) to 10K RADs (Si) or greater by IDT's ARACOR xRay Total Dose sample die test plan (Total Dose levels
require negotiation, consult factory for more details).
• Radiation Tolerant product uses standard wafer/process
material that is qualified to 10K RADs (Si) Total Dose by
IDT's ARACOR X-Ray Total Dose sample die test plan.
Integrated Device Technology can provide Radiation
Tolerant/Enhanced versions of most product types (some
speed grades may not be available).

Please contact your I[)T sales representative or factory
marketing to determine availability and price of any IDT
product processed in accordance with one of these levels of
radiation hardness.

II

3.3

2

PACKAGE DIAGRAM OUTLINES

II

THERMAL PERFORMANCE CALCULATIONS FOR lOT'S PACKAGES
Since most of the electrical energy consumed by
microelectronic devices eventually appears as heat, poor
thermal performance of the device or lack of management of
this thermal energy can cause a variety of deleterious effects.
This device temperature increase can exhibit itself as one of
the key variables in establishing device performance and long
term reliability; on the other hand, effective dissipation of
internally generated thermal energy can, if properly managed,
reduce the deleterious effects and improve component
reliability .
A few key benefits of IDrs enhanced CEMOSTM process
are: low power dissipation, high speed, increased levels of
integration, wider operating temperature ranges and lower
quiescent power dissipation. Because the reliability of an
integrated circuit is largely dependent on the maximum
temperature the device attains during operation, and as the
junction stability declines with increases in junction temperature
(TJ), it becomes increasingly important to maintain a low (TJ).
CMOS devices stabilize more quickly and at greatly lower
temperature than bipolar devices under normal operation.
The accelerated aging of an integrated circuit can be expressed
as an exponential function of the junction temperature as:
tA = to exp

[

§

k

4.

Tightly controlled the assembly procedures to meet or
exceed the stringent criteria of MI L-STD-883_ to ensure
maximum heat transfer between die and packaging
materials.
The following figures graphically illustrate the thermal values
of lOT's current package families. Each envelop (shaded
area) depicts a typical spread of values due to the influence of
a number of factors which include: circuit size, package
materials and package geometry. The following range of
values are to be used as a comprehensive characterization of
the major variables rather than single point of reference.
When calculating junction temperature (TJ), it is necessary
to know the thermal resistance of the package (9JA) as
measured in "degree celsius per watt". With the accompanying
data, the following equation can be used to establish thermal
performance, enhance device reliability and ultimately provide
you, the user, with a continuing series of high-speed, lowpower CMOS solutions to your system design needs.
9JA = [TJ - TA]/P
TJ = TA + P[9JA] = TA + P[9JC + 9CA]
where

U-~\J
TJ)

,TO

9JC = TJ - Tc

9CA=Tc-TA

P

P

where
tA
lifetime at elevated junction (TJ) temperature
to
normal lifetime at normal junction (To) temperature
Ea
activation energy (ev)
k
Boltzmann's constant (8.617 x 1~ev/k)
i.e. the lifetime of a device could be decreased by a factor of
2 for every 10°C increase temperature.
To minimize the deleterious effects associated with this
potential increase, lOT has:
1. Optimized our proprietary low-power CEMOS
fabrication process to ensure the active junction
temperature rise is minimal.
2. Selected only packaging materials that optimize heat
dissipation, which encourages a cooler running device.
3. Physically designed all package components to
enhance the inherent material properties and to take
full advantage of heat transfer and radiation due to
case geometries.

Ref. MIL-STD-883C, Method 1012.1

JEDEC ENG. Bulletin No. 20, January 1975
1986 Semi. Std., Vol. 4, Test Methods G30-86, G32-86.

4.1

9
J
P
TA
TJ
Tc
9CA

9JC

9JA

=
=
=
=

Thermal resistance
Junction
Operational power of device (dissipated)
Ambient temperature in degree celsius
Temperature of the junction
Temperature of case/package
Case to Ambient, thermal resistance-usually a
measure of the heat dissipation due to natural or
forced convection, radiation and mounting
techniques.
Junction to Case, thermal resistance-usually
measured with reference to the temperature at a
specific point on the package (case) surface.
(Dependent on the package material properties
and package geometry.)
Junction to Ambient, thermal resistance-usually
measured with respect to the temperature of a
specified volume of still air. (Dependent on 9JC +
9JA which includes the influence of area and
environmental condition.)

Theta JA· Stili Air 16·20 Lead Ceramic Dips

Theta JC 22·40 Lead Ceramic Dips
20~--------------------~

110.-------------------~

18
16

105
100
95

~ :~

~ 14
~ 12
~ 10
~

r=

~

80
~ 75
r70
65
60
55

8
6
4

2

50~~~~~_.~~~~~

O+-~~~~~--~~~~~

o

o

5 10 15 20 25 30 35 40 45 50
Ole Size (1000's sq. mils)

Ole Size (1000's sq. mils)

Theta JA· Stili Air 22-40 Ceramic Dips

80
75
70
65
60
~
u
~
55
<
.., 50
•
Gi
r= 45
40
35
30

Theta JC 16·20 Lead Ceramic Dip

30

~

25

~

20

~

15

~

•

'i

r= 10
5
0

0 5 10 15 20 25 30 35 40 45 50
Ole Size (1000's sq. mils)

Thermal Resistance of Ceramic LCC's

100.--------------------,
90
80
1= 70
00( 60
~~ 50
..,00( 40
Gi
'" 30
.c
20
10
S;:
0
16 24 32 40 48 56 64

125.---~--r_~--~--~--~

100~~~~--~~---4---+--~

75~_T~~~~~~

20/24 SSOPS

~

.c~ 50t---r~9r~~~~~~~
...
: 48SS0P

...

+---~~--~--~--~1

25+---~--~~---4--~--~

+. . . . ..

···········j···········j···········t··················...

0+-~~~~~---4~-+--~

o

200 400

0 5 10 15 20 25 30 35 40 45 50
Die Size (1000's sq. mils)

Theta JA vs. Airflow
PLASTIC SSOP PACKAGES

[

5 10 15 20 25 30 35 40 45 50

LEAD COUNT

600 800 1000

AIRFLOW (LFM)

THETA JC: 20/24 PIN = 35-40 °CIW
48 PIN = 16-20 °CIW

4.1

2

~
~
~
~

r:

Theta JC Pin Grid Arrays
7~------------------~

Theta JA Ceram ic Flatpacks/Cerpacks
180
160
140
120
100
80
60
40
20

6

O~~~~~~~~~~~~~~

o

8

16 24 32 40 48 56 64
o+-----~~--~----~--~

Lead Count

o

50

100

150

200

Die Size (1000's sq. mils)

Theta JC Ceramic Flatpacks/Cerpacks
18
16
14
~ 12
~ 10

..,

~
~

PLASTIC DIPS: 16,18 &20 PINS

~
CD
0

c

~

8
6
4
2

'iii
CD

a:

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E
CD

.e

O~~~~~~~~~~~~~

o

8

I-

16 24 32 40 48 56 64

100
90
80
70
60
50
40
30
20
10

Lead Count

~W/#J/;1
~eic

~2Z?Z2ZZZZZ171

0

0 5 10 15 20 25 30 35 40 45 50
Die Size (1000's sq. mils)

PLASTIC SOICS: 24,28 & 32 PINS

~
~
CD
0

c
in

'"

'iii
CD

a:
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100
90
80
70
60
50
40
30 •

CD

.e

l-

~

~W//.@.J

~
CD
0

c
in

'"

'iii
CD

a:

ii

~eic

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~ZZ2ZZZZ722ZZ1

20
10
0

PLASTIC SOICS: 16 & 20 PINS

,-.-

CD

.e

I-

0

100
90
80
70
60
50
40
30

0

5 10 15 20 25 30 35 40 45 50
Die Size (1000'S sq. mils)

~

20
10
0

eic

22272222222224

5 10 15 20 25 30 35 40 45 50
Die Size (1000's sq. mils)

4.1

3

PLASTIC DIPS: 22,24 & 28 PINS

~
~
CD
tl

c

01

'0

lic::
iU

i

~

100
90

~

80
70

CII

~eja

60
50
40
30
20
10
0

tl

~

'0

iii

..JJz/77ZZ777J

t?zzzu-

CD

c::
iU

i

Sjc

..c

-.....;~ZZZ2ZZZZZZZZI

0

I-

PLASTIC PLCCS: 44,52,68 & 84 PINS
100
90
80
70

~

20
10
0

5 10 15 20 25 30 35 40 45 50

~ ·44.52.68 pin.

60
50
40
30

9jc - 44,52,68,84 pins

0 10 20 30 4050 60 70 8090100

Ole Size (1000's sq. mils)

Die Size (1000's sq. mils)

PLASTIC PLCCS: 28 & 32 PINS

PLASTIC DIPS: 40,48 & 64 PINS

~
CD
tl

C

01

'0

iii
CD

c::
iU

E
CII

..c

l-

100
90

~

80
70
60
50
40
30
20
10
0

eja-84 pin

ill2Z/2llZZl/J

u

I<.,.
CD
tl

c

01

'0

~eja

"=c::

~

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---~////Z2

~

9jc

I-

22227272227771

100
90
80
70

0

0 10 20 30 40 50 60 70 80 90100

~9ja
?!7TrlZTl7a

60
50
40
30
20
10

~ 9jc
--2Z7ZZZZZZZZZJ
0

5 10 15 20 25 30 35 40 45 50
Die Size (1000's sq. mils)

Die Size (1000's sq. mils)

4.1

4

28 Pin Flatpack

Alrll ••

VI.

Airflow

(mI,)

48/56 Pin Cerpack Thela JA

30 - ..••.••• _- . __ .-. :::- •. __ •..••• --

28 Pin Cerpack

Alrnow

VI.

VI.

68 Pin PGA Theta JA va. Airftow
Cavity Up without Internal heataink

Airflow

-

~ .. ···· .. ···· ..·· .. ··· .. ·· .. ·····; .. ···· .. ·· .... :::1
···;···
:

Ai,How

:

:

o~------~------~------~------~-------J
o

(mi.)

Airll •• (mi.)

144 Pin PGA Theta JA VB. Airflow
Cavity Down wilh CuW internal healBink

84 Pin PGA Theta JA vs. Airnow
Cavity Down with CuW inlernal heatsink
35 ••••••••••••••••••• "]"" ••••••••••••••••• ]"" •••••••••••••••

··T···················[····················I

30 .......................................................................................................... .

(.. . il+

, I

~

!::j. . . . . . . . . . . . . . . . . . . . .,: . . .

: :-.~

:j

;" .............._.i.
10

I

:

i

........ : ................... ~

O~------~------~------~------~------~
o

Airllo. (mi.)

Airllo. (mltl

4.1

5

179 Pin PGA Theta JA VI. Alrllow
Cavity Down with CuW Internal heatllnk

208 Pin PGA Theta JA VI. Airflow
Cavity Down wilhout Internal heatslnk

·r. . . . . . . . . ..

16 .. ·· .. ·•·· .. ·· ..

··1 .. ····· .. ·· .. ·.. ·· ..:·· .. ·.. ·.. ··· .. ·· .. ·)· .... ·· .. ·· ........1' .... .

14 ...... .. • .. ·• ....

t· . ···· ....·. · . ·1··· ......·........ ·1· ..···

. . . . . • •'• • • • • • • • • 1• • • • • • • • • •'• • • • • • • . . .1••·.........•••.

1" .. ·.... ·· .. ·.. ·· ..

!

12 .................. ; ................... ~.................... : ................... ~ .................. ..

.........

~

~I:
~

~

i

30 .................... ; ..................... ; ..................... ; ..................... ; .....................

18 • ....................; .................... ·;· .. • ................ ·; ........• .... • ......

: .........'J

1"::: .. ::.:: .. ::.::1::::.::::::::::::-:::::::::::::.:::::::::: ................ ..

.................... + ...................:...

~-..:c

............................. .

Airl1 •• (mf.)

AI,l1'.

Theta JA

447 Pin PGA Theta JA VB. Airllow
Cavity Down with internal heatsink

VS.

(mf.)

Airftow

841160/208 lead UQIAD ftatpack
28mm body

..........,......... .

~15
:..

..

• • • • • • • • • -- • • • • • • • • • . • • • • • • • • j • • • • • • • • • • • • • • • • • • •

. ..,..... .

10 ............ .

-~

·
··,,

5 ..

..

•••• J ••••••••••••••••••• J ••••••

,
,
,
,
,,

O~------~------~--------~------~------~

.,,
,
,
,
,

,,

o

Airl1 .. (mf.)

28 Pin Plastic Dip Thela JA

Alrl1 •• (of.)

VI.

28 Pin SOJ Theta JA

Airflow

VI.

Airftow

70r-------------------------------------------.

::~.~,.<,,~
. .~. . . . . . .:. . . . . . . .~. . . . . . . ,. . ·. . . ·. .

1

~

?oj .. · .... · ........ · .. ;· .... ··~~· .... ·: .... ·........ · ...... ; ...... ·.... · .... · .. ·;.... · .... ·.... · ......
~

---r------~

1

30

10t .. · .... · ........ · .. ~·· ........ · .... ·.... ·, ....·........ · ...... ! ...... ·· ........ · .. ·~ .... · .... ·· ..........1

.o~------~------~------~------~------~

o~------~------~~------~------~------~

o

AJrlJ ••

o

(mlo)

4.1

6

32 Pin SOJ Theta JA vs. Airflow

32 Pin PlCC vs. Airftow
so~----------------------------------------~

___ A:

~O{------------·------;---~:-------------:-------------------~-------·----·------~-------------------I

~

.

____ A:

0 ---------------

.~

~3Si------------------;------·--------·--~~----------------·;·-----------------;-------------------1

~3Si-----------·----···-;----------------··-·-;-·----- -~

.

~

30~-----·----------·-:--·---------------·-;-·------·-----------,f------------------·-;----=-....:·--------:

30i----------------·-l--------------------;-----·------------·l-----------··-=~

2s1-·---------------~-----------------·"-------------·------~--.---------------~----.--------.-----;

2S~---------·--------·----·--------------·--------------------·----------··------·-------------------1

II

AI,II •• (mi.)

Alii •• (mi.)

208 Pin paFP VI. Airflow

84 Pin PlCCs vs. Airflow
Normal & Enhanced

::I~'

3 5 ••••••••••••••••••• ~ ••••••••••••••••••• ~ •••••••••••••• ····T··················~···················]

'''~ ······.·!I

2Si---.---- ... ----.----~-.-----------------~...._
-.:.:.-- _
------_ !.-

---

--:

- ---- --- ___ oj

---

r----~

l

~~20f-------·------·----~-·-----··---·--·----;---------.----------~.----.-.-----------;;---------.---;
.. ----:

~::'~~~~-~---,=-L~=j
': ................................j

151-------·-·--··-·---;-·-------------·----;--·--------.. -------;--------------.----.;--------------------;

10 f ---- -----. --. ---... -~ ----.- -- ----- --. -- --;--- ------. -. ----. ---~- ----- -. --- ---. -- --.:- ---.- ---- --- -- -----,

:

Airll.w (mi.)

Ai,lIo. (mi.)

Theta JA vs. Airflow
64180/100 lead Thin Quad Flatpack
14mm body

55 •••••• .... •••••• ....

48156 Pin asoP,

VI.

Airflow

(.150· body)

T··· ....·····....···r. ·. ····. ·. . . · ·.............. j.....................j
·····~

....

·1
___ A_A_A,.

85 -

[::~~~-c=+_<

!:: · · · ' 1
30

,

--- -. -

60

25 -55 ____

0 ••• -.----

,

:
:

--

.---~

:
:.

.-----~--

,

-

-- -- -.;-:

_

..

.
.:
"'r-··---····-----··r········· ···----~·····--······-·--f--· ..........-.. .

so~----~:------~:------~:------~:------~

20~------~------~--------~------4-------~

Alrll •• (mi.)

Airllo_

4.1

(m/')

7

Theta JA

VI.

Alrnow lor 20/24 pin SSOP.
128 Pin Thin QUId F1atplck

··········~············-·--·-·.·.f,-_-_-_-_.-.·-----···----; .. --.--- ·-------·-~---·-------::_:_:::I;::.
.

. . . ... ~.

---_.-

..... -. . --:-- _... _---

::!;I·I
oL-----~!
____~:----~----~~--~
o

4.1

8

PACKAGE DIAGRAM OUTLINE INDEX
SECTION

PAGE

MONOLITHIC PACKAGE DIAGRAM OUTLINES ......................................................... 4.3
PKG.
F84-1

DESCRIPTION
84-Lead Quad Flatpack (cavity down) ......................................................................... .

G179-1
G447-1

179-Lead Pin Grid Array (cavity down) .........................................................................
447-Lead Pin Grid Array (cavity down) .........................................................................

2
3

PN100-1

100-Lead Thin Quad Flatpack ..... .............................. ....... ............ ........ ...... ..................

4

M84-1
M208-1

84-Lead MQUAD (J-bend, cavity down) .......................................................................
208-Lead MQUAD (cavity down) ..................................................................................

6
7

J84-1

84-Pin Plastic Leaded Chip Carrier (square) ................................................................

8

MODULE PACKAGE DIAGRAM OUTLINES
Module package diagrams are located at the back of each Subsystems data sheet.

4.2

MONOLITHIC PACKAGE DIAGRAMS

FLATPACKS
84 LEAD QUAD FLATPACK (CAVITY DOWN)
D1

-------1

A

D2

e

D3

1
J
E2 E1

E3

L

1I

HEAT SINK

LID

E

L

cj-

D

#

DWG #
OF LDS (N)
SYMBOL
A
A1
b

C
D/E
D1/E1
D2/E2
D3/E3

e
L
ND/NE

F84-1
84
MIN
MAX
. 135
.105
.014
.020
. 007
.011
1.940
1.960
1.140
1.160
1.000 BSC
.500 BSC
.050 BSC
.390
.410
21

NOTES:
1. ALL DIMENSIONS ARE IN INCHES,
UNLESS OTHERWISE SPECIFIED .
2.
BSC - BASIC LEAD SPACING
BETWEEN CENTERS.
3.
CROSS HATCHED AREA INDICATES
INTEGRAL METALLIC HEAT SINK .

4.3

A1

MONOLITHIC PACKAGE DIAGRAMS

PIN GRID ARRAYS
179 PIN PGA (CAVITY DOWN)
TOP VIEW

II
PIN 1 ID

SEATING PLANE

#

DWG #
OF PINS (N)
SYMBOL
A
0B
0B1
0B2
D/E
D1/E1

e
L
M
01

G179-1
179
MIN
MAX
.145
.082
.016
.020
.060
.080
.040
.060
1.840
1.880
1.700 BSC
.100 BSC
.120
.140
18
.025
.060

NOTES:
(UNLESS OTHERWISE SPECIFIED)
1. ALL DIMENSIONS ARE IN INCHES.
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE.
4. SYMBOL "N" REPRESENTS THE NUMBER OF PINS.
5. CHAMFERRED CORNERS ARE lOT'S OPTION.
[§] CROSS HATCHED AREA INDICATES INTEGRAL METALLIC
HE.AT SINK ..

4.3

2

MONOLITHIC PACKAGE DIAGRAMS

PIN GRID ARRAYS (Continued)
447 PIN PG A ( CAVITY DO WN)

BOTTOM VIEW
~-------------

0
01

I

2
1

4
3

6
5

8
7

9

TOP VIEW

·iI

10 12 14 16 18 2b 22 24 26 28 30 32 34 36 38
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

6

PIN1ID~

PIN 1 10
OPTION G447-1 ONLY

SEATING PLANE

anON G447-3 ONLY

G447-1
DWG #
447
# OF PINS (N)
SYMBOL
MIN MAX
A

¢B
(2)B1
(2)B2

D/E
D1/E1

e
L

M
01

S

G447-:3
447
MIN MAX
.070 .145
.070 . 145
.016 . 020
.016 .020
.050 .060
.050 .060
.045 .055
.045 .055
2.040 2.080 2.040 2.080
1.900 Bse 1.900 Bse
.1008se
.100 8se
.120 .140
.120 .140
39
39
.030 .045
.045 .060
.050 8se
.050 Bse

NOTES:
1. ALL DIMENSIONS ARE IN INCHES UNLESS OTHERWISE
SPECIFIED .
2. BSC - BASIC LEAD SPACING BETWEEN CENTERS.
3. SYMBOL "M" REPRESENTS THE PGA MATRIX SIZE .
4. SYMBOL "N" REPRESENTS THE NUMBER OF PINS.
5. CHAMFERRED CORNERS ARE lOT'S OPTION.
~ CROSS HATCHED AREA INDICATES INTEGRAL METALLIC
HEAT SINK ..

4.3

3

s:
o
o
r

z

=i

:I:

o

"'C

>
o
~

G')

m

c

;;:
G')

::c

~~~

~~

~J"'"

OF~

DETAIL A

~

w

GAGE PLANE
__ {

SEE DETAIL 8

DETAIL B
f-bREF1

L~WITH
&'.09/.20

PLATING

.09/.16&'

,bl

BASE METAL

DETAIL C

"'"

II

>
s:
(J)

s:

P ACKAG E DrAG RAM 0 UTLINES

o
z
o
=l

TQFP (Continued)

r
R~\1SIONS

DWG

s

y
M
B

0
L

A
Al
A2
0
01
E
El
N

e
b
b1

#

I

PN64-1

JEDEC VARIATION
BP
MIN
NOM
MAX
1.60
.05
.10
.15
1.40
1.35
1.45
16.00 BSC
14.00 BSC
16.00 BSC
14.00 BSC
64
.SO BSC
.30
.37
.45
.30
.40
.35

eee

-

-

.10

ddd

-

-

20

"'w"

DWG
N

0
T
E

4
5,2
4
5,2

7

#

I

FN80-1

JEDEC VARIATION
BO
MIN
NOM
MAX
1.60
.10
.15
.05
1.40
1.35
1.45
16.00 BSC
14.00 BSC
16.00 BSC
14.00 BSC
SO
.65 BSC
.32
.38
22
.33
.22
.30
.1e
.13

DWG
N

0
T
E

4
5,2
4
5,2

7

#

I

PN100-1

JEDEC VARIATION
BR
MAX
MIN
NOM
1.60
.15
.05
.10
1.45
1.35
1.40
16.00 BSe
14.00 BSC
16.00 BSC
14.00 BSC
100
.50 BSC
.17
.22
.27
.17
.20
.23
.OB
.08

N
0
T

E

4
5,2
4
5,2

7

DWG

#

I

REV

DESCRIPTION

DATE

APPROVED

00

INITIAL RELEASE

03/12/92

T. VU

23823

01

ADD 80 & 100 LD

02/26/93

T. VU

24911

02

ADD 120 LD

10/06/93

T. VU

27384

03

REDRAW TO JEDEe FORMAT

"/18/94

JEDEC VARIATION
BS
MIN
NOM
MAX
1.60
.05
.15
.10
1.35
1.40
1.45
16.00 BSC
14.00 BSC
16.00 BSC
14.00 BSC
120
.40 BSC
.13
.18
.23
.13
.16
.19
.OB
.07

TOP PACKAGE MAY BE SMALLER THAN BonOM PACKAGE BY .15 mm

,&

DATUMS ~ AND

,&,

DIMENSIONS D AND E ARE TO BE DETERMINED AT SEATING PLANE

&,

DIMENSIONS 01 AND El DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION IS .25 mm PER SIDE. OlAND E1 ARE MAXIMUM BODY
SIZE DIMENSIONS INCLUDING MOLD MISMATCH

&,

DETAILS OF PIN 1 IDENTIFIER IS OPTIONAL BUT MUST BE LOCATED WITHIN
THE ZONE INDICATED

&

DIMENSION b DOES NOT INCLUDE DAM BAR PROTRUSIDrJ. ALLOWABLE DAM BAR
PROTRUSION IS .OS mm IN EXCESS OF THE b DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAM BAR CANNOT BE LOCATED DrJ THE LOWER RADIUS
OR THE FOOT.

W

TO BE DETERMINED AT DATUM PLANE

EXACT SHAPE OF EACH CORNER IS OPTIONAL

&

:II

l>

I C=:::J
2 C=:::J
3 C=:::J

7

PI

P

I
P
Pl
P2
X

e
N

I

s:
en

ODDDDDO~DDDDDDDD

4
5,2
4
5,2

C=:::J
C=:::J
C=:::J
C=:::J
C=:J
C=:J

I I

~l
~J

C=:J
C=:J

+

~

0J

0000000000000000

'~L
MIN I MAX
16.S0 I 17.00
13.BO I 14.00
12.35 BSC
.30
.50
.65 BSe
SO

MIN
MAX
16.S0 17.00
13.S0 14.00
12.00 BSC
.50
.40
80 BSC
64

I

TOLERANCES
UNLESS SPECIFIED
DECIMAL
XXi
XXX±

[ill

-----1

MIN I MAX
16.S0 17.00
13.S0 I 14.00
12.00 BSC
.30
.40
.50 BSe
100

I
I

GJ

MIN
MAX
16.S0 17.00
13.S0 14.00
11.60 BSC
.20
.30
.40 BSe
120

~ Integrated Device Technology. Inc.
2975 Stender Way, Santo Cloro, CA 95054

ANGULAR

dt

±

PHONE: (40e) 727-6116
FAX; (408) 492-8574

TWX. 910-J38-2070

XXXX±

10

ALL DIMENSIONS ARE IN MILLIMETERS

APPROVALS
DRAWN

11

THIS OUTLINE CONFORMS TO JEDEC PUBLICATION 95 REGISTRATION MO-136,
VARIATION BP, BQ, BR & BS

A4

DATE

TITLE

OJ/12/92

CHECKED

SIZE

C
U1

PN PACKAGE OUTLINE
14.0 X 14.0 X 1.4 mm TQFP
1.00/.10 FORM
I DRA'MNG

No.

PSC-4036

DO NOT SCALE DRAINING
-

-

~

~
G>

E

GB

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
.10 AND .25 mm FROM THE LEAD TIP

(")

C

LAND PATTERN DIMENSIONS

N
0
T

m

&,

"'0

l>

m

ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-19B2

a,

o
G>

PN120-1

NOTES:
1

:::r:

DCN
22167

I

I

REV

03

SHEET 2 OF 2

MONOLITHIC PACKAGE DIAGRAMS

MQUADS

®

84 LEAD MQUAD (J- BEND, CAVITY DOWN)
SEA TING PLANE
PIN 1 10
h X 45'

J X 45'
3 PL

D

#

D1 - - - 8 - - - - - -

DWG #
OF LDS (N)
SYMBOL
A
A1
b
b1
C
O/E
D1/E1
02/E2
D3/.E3

e

h

J
NO/NE

M84-1
84
MIN
MAX
.165
.180
.094
.114
.026
.032
.021
.013
.008
.012
1.195
1.185
1.140
1.150
1.090
1.130
1.000 BSC
.050 BSC
. 045 REF
.015 REF
21

1
J

+

II

03
(ND)

b

NOTES:
1.

\

ALL DIMENSIONS ARE IN INCHES, UNLESS OTHERWISE
SPECIFIED.

2.

BSC -

3.

FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN .004" AT THE SEATING PLANE.

4.

D1 & E1 SHOULD BE MEASURED FROM THE BOTTOM
OF THE PACKAGE.

5.

ND & NE REPRESENT NUMBER OF LEADS IN 0 & E
DIRECTIONS RESPECTIVELY .

4.3

BASIC LEAD SPACING BETWEEN CENTERS.

6

MONOLITHIC PACKAGE DIAGRAMS

MQUADS

®

(Continued)

208 LEAD MQUAD (CAVITY DOWN)
TOP VIEW
J

X 45'
3X

o

01

h X 45'
~---------------

E1

~------------------

E

owe #
#

OF LDS (N)
SYMBOL

A
A1
A2
b
C
OlE
01/E1

e
h

J
L
ND/NE

M208-1
208
MIN
MAX
3.50
3.86
.25
.51
3.17
3.43
.22
. 35
.13
.20
30.70
30.50
27.79
27.59
.50 BSC
.89 REF
.20 REF
.40
.60

----------------~
------------------~

NOTES:
1.

ALL DIMENSIONS ARE IN MILLIMETERS, UNLESS
OTHERWISE SPECIFIED .

2.

BSC -

3.

01 & E1 SHOULD BE MEASURED FORM THE BOTTOM
OF THE PACKAGE.

BASIC LEAD SPACING BETWEEN CENTERS.

4.

NO & NE REPRESENT NUMBER OF LEADS IN 0 & E
DIRECTIONS RESPECTIVELY.

52

4.3

7

P ACKAG E DIAG RAM 0 UTLINES
PLCC

s:

o
z
o
r

::::j

REVISIONS
DESCRIPTION

DA TE

I

APPROV1"D

03/15/95

:z::

n
"tI

:t01

O

.007® H A-B® D®

m

~
G')

&&.

lr

.150 MAX
.007® H A-B® O®

007® H A-B® O®

c
l>
G')

eB6

::0

&,

:t-

s:
en

&.
&

EI

/

.,.

/

I
I

Col

\

.042

:Os6

fA

.026/.032 [ftJW!®lfp;::g~

X 45'

I

Jl
7

1

.013/.021
REF
~Ir--------ll

SEATING PlANE

LQlQQiI C

DETAIL A

013/021 [4} [007@ [C IA-B®IO@I

&,

TOLERANCES
UNLESS SPECIrIEO

.0075/.0105

~I:

~ [@

WITH PLATING

1/ I

.0075/.0125

-1

XXi

ANGULAR

±

XXXi

":1,
.013/.019

DECIMAL
XX-XXi

BASE METAl

C)
dt

I~"W'~"·I "~'" I nTLE
DRAWN

M

08/15/8'

---"..

SECTION A-A
co

1-_ _1-_1

,11;

Integrated Device Technology, Inc.
2975 Stender Way, Santo Claro, CA 95054

PHONE, ('08) 727-6'"
FAX: (408) "92-8674

SIZE I DRA'MNG No.

c

DO NOT SCALE ORA'MNG

II

TWX: 910-338-2070

PL PACKAGE OUTLINE
SQUARE PLCC
.050 PITCH

06

~

PACKAGE DIAGRAM OUTLINES
PLCC (Continued)

o
z

o

r
REVISIONS

1

I

1

::::j

I

DeN

REV

I

DESCRIPTION

27647

06

1

REDRAW TO JEDEC FORMAT

DA TE

:::t:

I APPROVED

n

1 03/15/951

"tJ
~

(")

~

G>

m

DWG

sy
M

B
0
L

A
AI
A2
0
01
D2
E
EI
E2
N

.1>0

I

#

J28-1

JEDEC VARIATION
AB
MIN
NOM
MAX
.155
.172
.IS0
.105
.115
095
.062
.OS3
.485
.490
.495
.453
.456
.450
.205
.215
.195
.485
.490
.495
.450
.453
.456
.191
.205
.219
28

DWG
N
0

T
E

3.4
5
3,4
5

#

I

J44-1

JEDEC VARIATION
AC
MAX
MIN
NOM
.165
. ~ 72 .IS0
.095
.105
.115
.062
.OS3
.685
.690
.695
.650
.653
.656
.305
.315
.295
.685
.690
.695
.650
.653
.656
.319
.291
.305
44

DWG
N
0

T
E

3,4
5
3,4
5

#

I

J52-1

JEDEC VARIATION
AD
MIN
NOM
MAX
.165
172 .ISO
.095
.105
.115
.062
.OS3
.785
.790
.795
.750
.753
.756
.345
.365
.355
.785
.790
.795
.750
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m

a,

DATUMS

TO BE DETERMINED AT DATUM PLANE

GB

11

DIMENSIONS DI AND EI ARE TO BE DETERMINED AT DATUM PLANE

[JB

&,

DIMENSIONS DI AND EI DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION IS .010 PER SIDE. 01 AND EI ARE BODY SIZE DIMENSIONS
INCLUDING MOLD MISMATCH

&.

DIMENSIONS D2 AND E2 ARE TO BE DETERfllNED AT SEATING PLANE
CONTACT POINT

&

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&

LEAD WIDTH DIMENSION DOES NOT INCLUDE DAM BAR PROTRUSION. ALLOWABLE
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II]]

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EXACT SHAPE OF EACH CORNER IS OPTIONAL

&,

THESE DIMENSIONS DETERMINE THE MAXIMUM
SOCKET APPLICATIONS

10

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ANGLE OF THE LEAD FOR

ALL DIMENSIONS ARE IN INCHES

TOLERANCES
UNLESS SPECIFIED

DECIMAL

ANGULAR

XXi

±

2975 Stender Woy, Santo Claro, CA 9SOS-4

dt

DRANNM

PHONE: (408) 727-61115

fAX: (408) "'92-8674

XXXX±
APPROVALS

THIS OUTLINE CONFORMS TO JEDEC PUBLICATION 95 REGISTRATION MS-01S,
VARIATION AB, AC, AD, AE & AF. EXCEPTIONS: JEDEC MAXIMUM BASE METAL
LEAD WIDTH IS .018

~ Integrated Device Technology. Inc.

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2975 Stender Way, Santo Cloro, CA 95054

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I06
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SHEET 3 OF 3

RISC PROCESSING COMPONENTS

II

lOT RISC PROCESSING COMPONENTS
THE COMPLETE RISC SOLUTION
Integrated Device Technology, Inc. is dedicated to providing complete RISC design solutions by combining expertise in
silicon processes with leadership products in development
systems and software. Long an industry leader in the fastest
static RAMs and high-speed logic, lOT now offers RISC
system building blocks comprised of components and boardlevel subsystems.
As a semiconductor partner with MI PS Computer Systems,
lOT has established a leadership position in the RISC marketplace by supplying the fastest CPUs at 40MHz, pioneering
RISC CPU Subsystem™ modules, and offering cost-effective
development tools and software.
The MIPS architecture has become an industry standard
and has been adopted by over 100 leading OEM manufacturers including DEC, Sony, Tandem, NEC, CDC, Adobe, Siemens, Nixdorf, Honeywell Bull and Silicon Graphics. The
MIPS ISA (Instruction Set Architecture) has been selected by
JIAWG as the 32-bit microprocessor standard for military
avionics.

RISComponenf FAMILY OVERVIEW
M

The R3000 Family consists of the R3000 RISC CPU, the
R3041, R3051/52, R3071, R3081 and R36100
n
RISControliers ,. The R3000 processor is a derivative of the
R2000A, the first commercially-available RISC processor

introduced in 1985. The R3001 RISControlier and the R3051
family, including the R3041 and R3081 , are versions of the
processor tailored for embedded control and low-cost workstations. The R3500 integrates floating-point capability onto
the R3000 pinout. The R4000 is the third generation of the
MIPS RISC architecture that sets a new performance standard for the 1990s.

THE IDT79R3000 CPU
The R3000 processor consists of two tightly-coupled processors implemented on a single chip.
The first processor is a full 32-bit Harvard Architecture CPU
consisting of 32 registers, an integer ALU, a single-cycle
shifter, and a multiplier/divider. The second processor is a
system control coprocessor containing a Translation Lookaside Buffer (TLB) and control registers to support a virtual
memory space of 4GB and separate instruction and Data
caches.
The R3000 CPU features:
• Full 32-bit operation
• Three instruction formats
• Efficient 5-stage pipeline
• On-chip cache control
• On-chip Memory Management Unit
• Multiprocessor capability

CPU

CPO
(System Control Coprocessor)
Master Pipeline/Bus Control

General Registers
(32x32)

Exception/Control
Registers
Memory
Management
Unit Re isters

ALU

Local
Control
Logic

Shifter
Multiplier/Divider

Translation
Lookaside
Buffer
(64 entries)

Address Adder
PC IncrementlMux
Virtual Page Number/
Virtual Address

Data (32+4)
ADDRESS (18)
Figure 1. IDT79R3000 Processor

5.0

2860 drw01

II

THE R3051 FAMILY OF RISControliers™

THE IDT79R4000 CPU

The IDT79R3051 Family is a derivative of the R3000,
featuring a high level of integration and targeted to highperformance but cost-sensitive embedded processing applications. The R3051 family is designed to bring the highperformance inherent in the MIPS RISC architecture into lowcost, simplified, power-sensitive applications.
Functional units were integrated onto the CPU core in order
to reduce the total system cost rather than to increase the
inherent performance of the integer engine. Thus, the R3051
family is able to offer 35 MIPS of integer performance at
40MHz without requiring external SRAM or caches.
The R3041 extends the range of price/performance achievable with the R3051 family, by dramatically lowering the cost
of using the MIPS architecture. The R3041 has been designed
to achieve minimal system and components cost, yet maintain
the high performance inherent in the MIPS architecture. The
R3041 also maintains pin and software compatibility with the
R3051 and R3081.
The R3081 extends the capabilities of the R3051 family by
integrating the additional resources into the same pinout. The
R3081 thus extends the range of applications addressed by
the R3051 family and allows designers to implement a single,
base system and software set capable of accepting a wide
variety of CPUs according to the price/performance goals of
the end system.

The R4000 is the third generation of MIPS RISC technology
and establishes a new performance standard for RISC processors for the 1990s. The R4000 extends the performance
range served by the MIPS architecture and, thereby, provides
a migration path to applications served by the. R3051
RISControlier family.
This third generation processor maintains full binary compatibility with applications executing on the R2000/R3000 and
lOT's RISControlierfamily, while achieving substantially higher
performance. The key to this performance is both the architecture/implementation of the processor and the high level of
integration achieved in a single chip. The R4000 contains the
RISC integer unit, floating-point unit, MMU, 8K of 1- and 0cache, along with multiprocessing support such as direct
control of optional secondary caches. To achieve performance levels capable of over 50 VAX MIPS sustained performance, the R4000 utilizes technology such as super-pipelining
to exploit 2-level instruction parallelism with no issue restrictions. The R4000 presents a balanced architectural approach
to achieve a wide range of price/performance goals.

5.0

2

TABLE OF CONTENTS
PAGE

Rise PROCESSING COMPONENTS
IDT79R3000A
IDT79R3041
I DT79R3051 n9R3052
IDT79R3071
IDT79R3081
IDT79R36100
IDT79R4400
IDT79R4600
IDT79R4650
IDT79R4700

RISC CPU Core Processor ................................................................... ....................
Integrated RISControlier™ for Low-Cost Systems......................................................
IDT79R3051/79R3052 RISControliers™ ....................................................................
IDT79R3071 RISController'· ......................................................................................
IDT79R3081 RISControlier™ with FPA .....................................................................
IDT79R361-- Highly Integrated RISControlier™ .........................................................
Third-Generation 64-Bit Super-Pipelined RISC Microprocessor ...............................
Fourth-Generation 64-Bit RISC Microprocessor ........................................................
Embedded 64-Bit RISC Orion Microprocessor ..........................................................
Enhanced Orion 64-Bit RISC Microprocessor ...........................................................

5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10

11

5.0

3

~

[;)

RISC CPU CORE

R3000A
Core for
RISControlier Devices

Integrated Device Technology, Inc.

FEATURES:
•

Enhanced instruction set compatible R3000A Core for
integrated RISControliers
• Integrates well with R301 OA Core Hardware Floating Point
Accelerator
• Full 32-bit Operation-Thirty-two 32-bit registers and all
instructions and addresses are 32-bit.
• Efficient Pipelining-The CPU's 5-stage pipeline design
assists in obtaining an execution rate approaching one
instruction per cycle. Pipeline stalls and exceptions are
handled precisely and efficiently.
• Integrated Cache Control for On-Chip Caches-The CPU
core contains a high-bandwidth memory interface that
handles separate Instruction and Data Caches. Both caches
are accessed during a single CPU cycle. All cache control
is integrated into the core, allowing high-speed execution.
• "E" versions feature Memory Management Unit, including
a fully-associative, 64-entryTranslation Look-aside Buffer

•
•

•
•
•
•
•
•

(TLB). This provides fast address translation forvirtual-tophysical memory mapping of the 4GB virtual address
space.
Dynamically able to switch between Big- and Little-Endian
byte ordering conventions.
Software compatible with all R3000 devices. This insures
a wide range of development support, including compilers,
operating systems, libraries, and applications software.
High-speed 0.611 CMOS technology.
50MHz clock rates yield up to 40VUPS sustained throughput.
Supports independent multi-word block refill of both the
instruction and data caches.
Supports concurrent refill and execution of instructions.
Partial word stores executed as read-modify-write operations.
6 external interrupt inputs, 2 software interrupts, with single
cycle latency to exception handler routine.

R3000A CORE BLOCK DIAGRAM
CPO
(System Control Coprocessor)

CONTROL

CPU

Local
Control
Logic

Virtual Page Number/
Virtual Address

Data
Cache Index

2860 drw 01

6:~i~~~~OC~~~~Oag~~~~S~~red trademark and Orion. R3041, R3051. R3052, R3081 , R3721 , R4600, RISCompiler, RISController, RISCore, RISC Subsystem. and RISC Windows are trademarks of Integrated

MARCH 1994
© 1995 Integrated Device Technology, Inc.

5.1

DSC-903814

1

R3000A RISC CPU PROCESSOR CORE

DESCRIPTION

decoding, thus minimizing instruction execution time. The
R3000A core initiates a new instruction on every run cycle,
and is able to complete an instruction on almost every clock
cycle. The only exceptions are the Load instructions and
Branch instructions, which each have a single cycle of latency
associated with their execution. Note, however, that in the
majority of cases the compilers are able to fill these latency
cycles with useful instructions which do not require the result
of the previous instruction. This effectively eliminates these
latency effects.
The actual instruction set of the CPU was determined after
extensive simulations to determine which instructions should
be implemented in hardware, and which operations are best
synthesized in software from other basic instructions.

The R3000A RISC Microprocessor Core consists of two
tightly-coupled processors. The first processor is a full 32-bit
CPU based on RISC (Reduced Instruction Set Computer)
principles to achieve a new standard of microprocessor price/
performance. The second processor is a system control
coprocessor, called CPO, containing an optional fully-associative 64-entry TLB (Translation Look-aside Buffer), MMU
(Memory Management Unit) and control registers, supporting
a 4G B virtual memory subsystem, and a Harvard Architecture
Cache Controller achieving a bandwidth of 400MB/second
using integrated cache memory.
This data sheet provides an overview of the features
and architecture of the R3000A core. This core is integrated into various members of the lOT RISController
family, such as the R3041, R3051, and R3081. Detail on
those specific devices is found in separate data sheets
and user's manuals.

The R3000A instruction set can be divided into the following groups:
• Load/Store instructions move data between memory and
general registers. They are all I-type instructions, since the
only addressing mode supported is base register plus 16bit, signed immediate offset.

R3000A CPU Registers
The R3000A CPU provides 32 general-purpose 32-bit
registers, a 32-bit Program Counter, and two 32-bit registers
which hold the results of integer multiply and divide operations. Only two of the 32 general registers have a special
purpose: register rO is hard-wired to the value "a", which is a
useful constant, and register r31 is used as the link register in
jump-and-link instructions (return address for subroutine calls).
The CPU registers are shown in Figure 2. Note that there
is no Program Status Word (PSW) register shown in this
figure: the functions traditionally provided by a PSW register
are instead provided in the Status and Cause registers incorporated within the System Control Coprocessor (CPO).

I-Type (Immediate)

I

r2

··
··

r29
r30

0

15

16

I

rt

I

immediate

I

25

26

0

I

op

I

target

R-Type (Register)
31

I

26
op

25

I

20

21
rs

I

16
rt

11

15

I

rd

10

6
re

0

5

I

funct

I

2860 drw 03

Figure 3. R3000A Instruction Formats

o
r1

20

I

rs

J-Type (Jump)

General Purpose Registers

rO

21

25

I

op

31

Instruction Set Overview
All R3000A instructions are 32 bits long, and there are only
three instruction formats. This approach simplifies instruction

31

26

31

Multiply/Divide Registers
31

I

0

I

HI

31

I

0

I

LO

Program Counter
31

I

0
PC

I

r31
2860 drw 02

Figure 2. R3000A CPU Registers

5.1

The Load instruction has a single cycle of latency, which
means that the data being loaded is not available to the
instruction immediately after the load instruction. The compiler will fill this delay slot with either an instruction which is
not dependent on the loaded data, or with a NOP instruction. There is no latency associated with the store instruction.
Loads and Stores can be performed on byte, half-word,
word, or non-aligned word data (32-bit data not aligned on
a modul0-4 address). The CPU cache is constructed as a
write-through cache.
• Computational instructions perform arithmetic, logical
and shift operations on values in registers. They occur in
both R-type (both operands and the result are registers)
and I-type (one operand is a 16-bit immediate) formats.
Note that computational instructions are three operand
instructions; that is, the result of the operation can be
stored into a different register than either of the two

2

11

R3000A RISC CPU PROCESSOR CORE

•

registers. Thus, net performance is increased since software does not have to perform arithmetic instructions prior
to the branch to set up the branch conditions.
• Coprocessor instructions perform operations in the
coprocessors. Coprocessor Loads and Stores are I-type.
Coprocessor computational instructions have coprocessordependent formats (see coprocessor manuals).
• Coprocessor 0 instructions perform operations on the
System Control Coprocessor (CPO) registers to manipulate the memory management and exception handling
facilities of the processor.
• Special instructions perform a variety of tasks, including
movement of data between special and general registers,
system calls, and breakpoint. They are always R-type.

operands. This means that operands need not be overwritten by arithmetic operations. This results in a more efficient
use of the large register set.
Jump and Branch instructions change the control flow of
a program. Jumps are always to a paged absolute address
formed by combining a 26-bit target with four bits of the
Program counter (J-type format, for subroutine calls), or
32-bit register byte addresses (R-type, for returns and
dispatches). Branches have 16-bit offsets relative to the
program counter (I-type). Jump and Link instructions save
a return address in Register 31. The R3000A instruction set
features a number of branch conditions. Included is the
ability to compare a register to zero and branch, and also
the ability to branch based on a comparison between two

5.1

3

R3000A RISC CPU PROCESSOR CORE

R3000A INSTRUCTION SUMMARY
OP
LB
LBU
LH
LHU
LW
LWL
LWR
SB
SH
SW
SWL
SWR

Description
Load/Store Instructions
Load Byte
Load Byte Unsigned
Load Halfword
Load Halfword Unsigned
Load Word
Load Word Left
Load Word Right
Store Byte
Store Halfword
Store Word
Store Word Left
Store Word Right

ANDI
ORI
XORI
LUI

Arithmetic Instructions
(ALU Immediate)
Add Immediate
Add Immediate Unsigned
Set on Less Than Immediate
Set on Less Than Immediate
Unsigned
AND Immediate
OR Immediate
Exclusive OR Immediate
Load Upper Immediate

ADD
ADDU
SUB
SUBU
SLT
MFCz
SLTU
AND
OR
XOR
NOR

Arithmetic Instructions
(3-operand, register-type)
Add
Add Unsigned
Subtract
Subtract Unsigned
Set on Less Than
Move From Coprocessor
Set on Less Than Unsigned
AND
OR
Exclusive OR
NOR

SLL
SRL
SRA
SLLV
SRLV
SRAV

Shift Instructions
Shift Left Logical
Shift Right Logical
Shift Right Arithmetic
Shift Left Logical Variable
Shift Right Logical Variable
Shift Right Arithmetic Variable

ADDI
ADDIU
SLTI
SLTIU

OP
MULT
MULTU
DIV
DIVU
MFHI
MTHI
MFLO
MTLO

Description
Multiply/Divide Instructions
Multiply
Multiply Unsigned
Divide
Divide Unsigned
Move From HIGH
Move To HIGH
Move From LOW
Move To LOW

SYSCALL
BREAK

Jump and Branch Instructions
Jump
Jump and Link
Jump to Register
Jump and Link Register
Branch on Equal
Branch on Not Equal
Branch on Less than or Equal to Zero
Branch on Greater Than Zero
Branch on Less Than Zero
Branch on Greater than or
Equal to Zero
Branch on Less Than Zero and Link
Branch on Greater than or Equal to
Zero and Link
Special Instructions
System Call
Break

LWCz
SWCz
MTCz

Coprocessor Instructions
Load Word from Coprocessor
Store Word to Coprocessor
Move To Coprocessor

CTCz
CFCz
COPz
BCzT
BCzF

Move Control to Coprocessor
Move Control From Coprocessor
Coprocessor Operation
Branch on Coprocessor z True
Branch on Coprocessor z False

MTCO
MFCO
TLBR
TLBWI
TLBWR
TLBP
RFE

System Control Coprocessor
(CPO) Instructions
Move To CPo
Move From CPo
Read indexed TLB entry
Write Indexed TLB entry
Write Random TLB entry
Probe TLB for matching entry
Restore From Exception

J
JAL
JR
JALR
BEQ
BNE
BLEZ
BGTZ
BLTZ
BGEZ
BLTZAL
BGEZAL

II

2860 tbl 01

5.1

4

R3000A Rise CPU PROCESSOR CORE

SYSTEM CONTROL COPROCESSOR (CPO)
REGISTERS

Table 1 lists the instruction set of the R3000A processor
core.

R3000A System Control Coprocessor (CPO)
The R3000A core can operate with up to four tightlycoupled coprocessors (designated CPO through CP3). The
System Control Coprocessor (or CPO), is incorporated on the
R3000A core and supports the virtual memory system and
exception handling functions of the processor. The virtual
memory system is implemented using a Translation Lookaside Buffer and a group of programmable registers as shown
in Figure 3.

Register

HIGH half of a TLB entry
LOW half of a TLB entry
Programmable pointer into TLB array
Pseudo-random pointer into TLB array

Status

Mode, interrupt enables, and diagnostic
status info
Indicates nature of last exception
Exception Program Counter
Pointer into kernel's virtual Page Table
Entry array
Most recent bad virtual address

Cause
EPC
Context

SYSTEM CONTROL COPROCESSOR (CPO)
REGISTERS

BadVA

The CPO registers shown in Figure 3 are used to control
the memory management and exception handling capabilities
of the R3000A. Table 2 provides a brief description of the
registers common to most devices using the core. Note,
however, that certain devices (e.g. non-E versions, the R3081 ,
and R3041) implement slightly different sets of these registers, as described in their user's manuals.

Description

EntryHIGH
EntryLOW
Index
Random

PRld

Processor revision identification (Read only)
2860 tbl 02

63

TLB

8

7

I----------i

NOT ACCESSED
BY RANDOM

a '----------'

D
D

Used with Virtual Memory System
Used with Exception Processing

2860 drw 04

Figure 4. The System Coprocessor Registers

5.1

5

R3000A RISC CPU PROCESSOR CORE

Memory Management System
The R3000A has an addressing range of 4gB. However,
since most R3000A systems implement a physical memory
smaller than 4gB, theR3000A provides for the logical expansion of memory space by translating addresses composed in
a large virtual address space into available physical memory
address. The 4gB address space is divided into 2gB which can
be accessed by both the users and the kernel, and 2gB forthe
kernel only.
The actual virtual to physical translation mechanism is
either through an on-chip translation lookaside buffer (TLB),
or through a fixed translation mechanism, depending on the
device ("E" vs. non-"E" devices). These mechanisms are
explained in the data sheets and user's manuals for those
devices.

R3000A Pipeline Architecture
The execution of a single R3000A instruction consists of
five primary steps:
- Fetch the instruction (I-Cache).
1) IF
2) RD - Read any required operands from CPU
registers while decoding the instruction.
3) ALU - Perform the required operation on
instruction operands.
4) MEM- Access memory (D-Cache).
5) we - Write back results to register file.
Each of these steps requires approximately one CPU
cycle, as shown in Figure 4 (parts of some operations overlap
into another cycle while other operations require only 1/2
cycle).
IF

I

RD

I I-CAHCE I RF

R3000A Operating Modes
TheR3000A has two operating modes: User mode and
Kernel/mode. The R3000A normally operates in the User
mode until an exception is detected forcing it into the Kernel
mode. It remains in the Kernel mode until a Restore From
Exception (RFE) instruction is executed. The manner in which
memory addresses are translated or mapped depends on the
operating mode of the R3000A, and whether the device
implements an on-chip TLB.

ALU

MEM

WB

OP

D-CACHE

WB

I

1

'--v--'
One Cycle

2860 drw 05

Figure 5. R3000A Instruction Pipeline

INSTRUCTION EXECUTION
The R3000A uses a 5-stage pipeline to achieve an instruction execution rate approaching one instruction per CPU
cycle. Thus, execution of five instructions at a time are
overlapped as shown in Figure 5.

User Mode-in this mode, a single, uniform virtual address space (kuseg) of 2gB is available. Each virtual address
is extended with a 6-bit process identifier field to form unique
virtual addresses. The actual virtual to physical address
mapping is either done via a fixed translation, or through the
TLB, depending on the device.
Kernel Mode-four separate segments are defined in
this mode:
• kuseg-when in the kernel mode, references to this segment are treated just like user mode references, thus
streamlining kernel access to user data.
• ksegO-references to this 512mB segment use cache
memory but are not mapped through the optional TLB.
Instead, they always map to the first 0.5gB of physical
address space, whether or not the device contains an onchip TLB.
• ksegl-references to this 512mB segment are not mapped
through the TLB and do not use the cache. Instead, they
are hard-mapped into the same 0.5gB segment of physical
address space as ksegO.
• kseg2-references to this 1gB segment are either mapped
through the TLB (with use of the cache determined by bit
settings within the TLB entries) orthrough a predetermined
mapping (non-E versions; all references go through the
cache).

(5-Deep)

Instruction

Flow

Current CPU
Cycle

2860 drw06

Figure 6. R3000A Execution Sequence

This pipeline operates efficiently because different CPU
resources (address and data bus accesses, ALU operations,
register accesses, and so on) are utilized on a non-interfering
basis.

5.1

6

II

R3000A RISC CPU PROCESSOR CORE

r-----

Memory System Hierarchy
A primary goal of systems employing RISC techniques is
to minimize the average number of cycles each instruction
requires for execution. In order to achieve this goal, RISC
processors incorporate a number of RISC techniques, including a compact and uniform instruction set, a deep instruction
pipeline (as described above), and utilization of optimizing
compilers.
Figure 6 illustrates a memory system that supports the
significantly greater memory bandwidth required to take full
advantage of the R3000A's performance capabilities. The key
features of this system are:
• On-chip Cache Memory-Local, high-speed memory
(called cache memory) is used to hold instructions and data
that is repetitively accessed by the CPU (for example,
within a program loop) and thus reduces the number of
references that must be made to the slower-speed main
memory.
• Separate Caches for data and Instructions-Even with
high-speed caches, memory speed can still be a limiting
factor because of the fast cycle time of a high-performance
microprocessor. The R3000A supports separate caches
for instructions and data and alternates accesses of the two
caches during each CPU cycle. Thus, the processor can
obtain data and instructions at the cycle rate of the CPU.
• Write Buffer-in orderto ensure data consistency, all data
that is written to the data cache must also be written out to
main memory. The cache write model used by the
R3000A is that of a write-through cache; that is, all data
written by the CPU is immediately written into the main
memory. To relieve the CPU of this responsibility (and the
inherent performance burden) the R3000A supports an
interface to an on-chip write buffer. Thus, the R3000A core
continues execution at high-speed, while the store data is
retired at the slower memory rate.
• Read Buffer-The IDT RISControlier family typically incorporates an on-chip read buffer. This enables the system
interface to match the speed of the high-speed execution
core with the slower speed of a low-cost memory system,
while still optimizing performance. This small on-chip FIFO
enables the CPU to refill the cache and execute instructions even while additional instructions are being read from
memory. This process is called instruction streaming.

R3000A
Core
Data

Address

Main Memory
2860 drw 07

Figure 7. An R3000A System with a High-Performance Memory
System

ADVANCED FEATURES
The R3000A offers a number of additional features such
as the ability to sWap the instruction and data caches, facilitating diagnostics and cache flushing. Another feature isolates
the caches, which forces cache hits to occur regardless of the
contents of the tag fields. The R3000A allows the processor
to execute user tasks of the opposite byte ordering (endianness)
of the operating system, and further allows parity checking to
be disabled. More details on these features can be found in the
various devices' Hardware User's Manuals.
Further features of the R3000A are configured by the user,
in a device dependentfashion. These functions include whether
byte ordering follows "Big-End ian" or "Little-End ian" protocols, particulars of the memory interface, etc.

5.1

7

~

r;J

Integrated Device Technology, Inc.

FEATURES:

•
•
•
•
•
•

• Instruction set compatible with IDT79R3000A and R3051 riot
Family MIPS RISC CPUs
• High level of integration minimizes system cost
- RISC CPU
- Multiply/divide unit
- Instruction Cache
- Data Cache
- Programmable bus interface
- Programmable port width support
• On-chip instruction and data caches
- 2KB of Instruction Cache
- 512B of Data Cache
• Flexible bus interface allows simple, low-cost designs
- Superset pin-compatible with R3051
- Adds programmable port width interface
(8-, 16-, and 32-bit memory sub-regions)
- Adds programmable bus interface timing support
(Extended address hold, Bus turn around time,
Read/write masks)
Clkln

I

IDT79R3041
IDT79RV3041

IDT79R3041™
INTEGRATED RISControlier™
FOR LOW-COST SYSTEMS

Clock

~l Generator

I

•
•
•
•
•

Single, double-frequency clock input
16.67MHz, 20M Hz, 25MHz and 33M Hz operation
20MIPS at 25MHz
Low cost 84-pin PLCC packaging
On-chip 4-deep write buffer eliminates memory write stalls
On-chip 4-word read buffer supports burst or simple block
reads
On-chip DMA arbiter
On-chip 24-bit timer
Boot from 8-bit, 16-bit, or 32-bit wide PROMs
Pin- and software-compatible family includes R3041 , R3051 ,
R3052™, and R3081™
Complete software support
- Optimizing compilers
- Real-time operating systems
- Monitors/debuggers
- Floating Point emulation software
- Page Description Languages

I Master Pipeline Control I

SBrCond(3:2)

Unit

Int(5:3), Slnt(2:0)

System Control
Coprocessor
Exception/Control
ReQisters

General Registers
(32 x 3:h-

Bus Interface
Registers

Shifter

PortSize
Reqister
Counter
Registers

Address Adder
PC Control

TC

32
,I

v

Integer
CPU Core

ALU
MultiDiv Unit

t

Virtual Address

I

Physical Address Bus

I

+

+

Data
Cache
512B

Instruction
Cache
2kB

t

Data Bus

R3051 Superset
Bus Interface Unit
~

4-deep
Write
Buffer
Data
Unpack
Unit

t

Address/
Data

4-deep
Read
Buffer
Data
Pack
Unit

DMA
Arbiter

I

32 /
,I

I

•t
BIU
Control

Timing/ Interface
Control

t _t_

DMA
Ctrl

RdlWr
Ctrl

~
SysClk

2905 drw 01

Figure 1. R3041 Block Diagram
RISControlier. R3041. R3051, R3052, R3081, IDT/sim, and lOT/kit are trademarks, and the lOT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
©1995 Integrated Device Technology, Inc.

SEPTEMBER 1995
5.2

DSC-907014

1

II

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

INTRODUCTION
The lOT R3051 family is a series of high-performance 32bit microprocessors featuring a high-level of integration, and
targeted to high-performance but cost sensitive embedded
processing applications. The R3051 family is designed to
bring the high-performance inherent in the MIPS RISC architecture into low-cost, simplified, power sensitive applications.
Thus, functional units have been integrated onto the CPU
core in order to reduce the total system cost, rather than to
increase the inherent performance of the integer engine.
Nevertheless, the R3051 family is able to offer 35MIPS of
integer performance at 40MHz without requiring external
SRAM or caches.
.
Further, the R3051 family brings dramatic power reduction
to these embedded applications, allowing the use of low-cost
packaging. Thus, the R3051 family allows customer applications to bring maximum performance at minimum cost.
The R3041 extends the range of price/performance achievable with the R3051 family, by dramatically lowering the cost

Device
Name
R3051
R3052

Instruction
Cache
4kB
8kB

Data
Cache
2kB
2kB

COMMERCIAL TEMPERATURE RANGE

of using the MIPS architecture. The R3041 is designed to
achieve minimal system and components cost, yet maintain
the high-performance inherent in the MIPS architecture. The
R3041 also maintains pin and software compatibility with the
R3051 and R3081.
The R3051 family offers a variety of price/performance
features in a pin-compatible, software compatible family.
Table 1 provides an overview of the current members of the
R3051 family. Note that the R3051 , R3052, and R3081 are
also available in pin-compatible versions that include a fullfunction memory management unit, including 64-entry TLB.
The R3051/2 and R3081 are described in separate manuals
and data sheets.
Figure 1 shows a block level representation of the functional units within the R3041. The R3041 can be viewed as the
embodiment of a discrete solution built around the R3000A.
By integrating this functionality on a single chip, dramatic cost
and power reductions are achieved.
An overview of these blocks is presented here, followed
with detailed information on each block.

Floating
Point
Software Emulation
Software Emulation

Bus
Options
Mux'ed AID
Mux'ed AID

R3071
R3081

16kB
or8kB

4kB
or8kB

On-chip Hardware

1/2 frequency bus option

R3041

2kB

512B

Software Emulation
Programmable timing support

8-, 16-, and 32-bit port width support
29051bl01

Table 1. Pin compatible R3051 Family

CPU Core
The CPU core is a full 32-bit RISC integer execution
engine, capable of sustaining close to a single cycle execution
rate. The CPU core contains a five stage pipeline, and 32
orthogonal 32-bit registers. The R3051 family implements the
MIPS-I Instruction Set Architecture (ISA). In fact, the execution engine of the R3041 is the same as the execution engine
of the R3000A. Thus, the R3041 is binary compatible with
those CPU engines, as well as compatible with other members of the R3051 family.

The execution engine of the R3051 family uses a five-stage
pipeline to achieve close to single cycle execution. A new
instruction can be started in every clock cycle; the execution
engine actually processes five instructions concurrently (in
various pipeline stages). The five parts of the pipeline are the
Instruction Fetch, Read register, ALU execution, Memory,
and Write Back stages. Figure 2 shows the concurrency
achieved by the R3051 family pipeline.

1#1

Current
CPU
Cycle

2905 drw 02

Figure 2. R3051 Family 5-Stage Pipeline

5.2

2

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

System Control Co-Processor
The R3041 also integrates on-chip a System Control Coprocessor, CPO. CPO manages the exception handling capability of the R3041 , the virtual to physical address mapping of
the R3041 , and the programmable bus interface capabilities
of the R3041. These topics are discussed in subsequent
sections.
The R3041 does not include the optional TLB found in other
members of the R3051 family, but instead performs the same
virtual to physical address mapping of the base version of the
R3051 family. These devices still support distinct kernel and
user mode operation, but do not require page management
software or an on-chip TLB, leading to a simpler software
model and a lower-cost processor.
The memory mapping used by these devices is illustrated
in Fig ure 3. Note that the reserved address spaces shown are
for compatibility with future family members; in the current
family members, references to these addresses are translated in the same fashion as their respective segments, with
no traps or exceptions taken.
When using the base versions of the architecture, the
system designer can implement a distinction between the
user tasks and the kernel tasks, without having to execute
page management software. This distinction can take the
form of physical memory protection, accomplished by ad-

dress decoding, or in other system specific forms. In systems
which do not wish to implement memory protection, and wish
to have the kernel and user tasks operate out of a single
unified memory space, upper address lines can be ignored by
the address decoder, and thus all references will be seen in
the lower gigabyte of the physical address space.
The R3041 adds additional resources into the on-chip CPO.
These resources are detailed in the R3041 User's Manual.
They allow kernel software to directly control activity of the
processor internal resources and bus interface, and include:
• Cache Configuration Register: This register controls the
data cache block size and miss refill algorithm.
• Bus Control Register: This register controls the behavior
of the various bus interface signals.
• Count and Compare Registers: Together, these two
registers implement a programmable 24-bit timer, which
can be used for DRAM refresh or as a general purpose
timer.
• Port Size Control Register: This register allows the kernel
to indicate the port width of reads and writes to various subregions of the physical address space. Thus, the R3041 can
interface directly with 8-, 16-, and 32-bit memory ports,
including a mix of sizes, for both instruction and data , .
references, without requiring additional external logic.
___

PHYSICAL

VIRTUAL

Oxffffffff

Oxffffffff

OxfffOOOOO
Oxffefffff

OxfffOOOOO
Oxffefffff
Kernel Cached
(kseg2)

OxcOOOOOOO
Oxbfffffff

OxaOOOOOOO
Ox9fffffff
Ox80000000
Ox7fffffff
Ox7ffOOOOO
Ox7fefffff

.,......._.........,....j

Kernel Uncached

Oxcooooooo
Oxbfffffff

~~~~~~~==~~~~ OxbffOOOOO

(kseg1)

Oxbfefffff

Kernel Cached
Kernel/User
Cached
Tasks

(ksegO)

2047 MB

Kernel/User
Cached

~

___________________~ Ox40000000
Ox3fffffff
Inaccessible
512 MB

(kuseg)

r---------------------~ Ox20000000

OxOOOOOOOO

Kernel Boot
and I/O

Oxlfffffff

~______~5~1~2~M~B________~

OxOOOOOOOO
2905 drw03

Figure 3. Virtual to Physical Mapping of Base Architecture Versions

5.2

3

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

Clock Generation Unit
The R3041 is driven from a single 2x frequency input clock,
capable of operating in a range of 40%-60% duty cycle. Onchip, the clock generator unit is responsible for managing the
interaction of the CPU core, caches, and bus interface. The
clock generator unit replaces the external delay line required
in R3000A based applications.

Instruction Cache
The R3041 integrates 2kB of on-chip Instruction Cache,
organized with a line size of 16 bytes (four 32-bit entries) and
is direct mapped. This relatively large cache substantially
contributes to the performance inherent in the R3041 , and
allows systems based on the R3041 to achieve high-performance even from low-cost memory systems. The cache is
implemented as a direct mapped cache, and is capable of
caching instructions from anywhere within the 4GB physical
address space. The cache is implemented using physical
addresses and physical tags (rather than virtual addresses or
tags), and thus does not require flushing on context switch.

Data Cache
The R3041 incorporates an on-chip data cache of 512B,
organized as a line size of 4 bytes (one word) and is direct
mapped. This relatively large data cache contributes substantially to the performance inherent in the R3051 family. As with
the instruction cache, the data cache is implemented as a
direct mapped physical address cache. The cache is capable
of mapping any word within the 4GB physical address space.
The data cache is implemented as a write through cache,
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance.

Bus Interface Unit
The R3051 family uses its large internal caches to provide
the majority of the bandwidth requirements of the execution
engine, and thus can utilize a simple bus interface connected
to slow memory devices.
The R3051 family bus interface utilizes a 32-bit address
and data bus multiplexed onto a single set of pins. The bus
interface unit also provides an ALE (Address Latch Enable)
output signal to de-multiplex the AID bus, and simple handshake signals to process CPU read and write requests. In
addition to the read and write interface, the R3041 incorporates a DMA arbiter, to allow an external master to control the
external bus.

COMMERCIAL TEMPERATURE RANGE

The R3041 augments the basic R3051 bus interface capability by adding the ability to directly interface with varying
memory port widths, for instructions or data. For example, the
R3041 can be used in a system with an 8-bit boot PROM, 16bit font/program cartridges, and 32-bit main memory, transparently to software, and without requiring external data
packing, rotation, and unpacking.
In addition, the R3041 incorporates the ability to change
some of the interface timing of the bus. These features can be
used to eliminate external data buffers and take advantage of
lower speed and lower cost interface components.
One of the bus interface options is the Extended Address
Hold mode which adds 1/2 clock of extra address hold time
from ALE falling. This allows easier interfacing to FPGAs and
ASICs.
The R3041 incorporates a 4-deep write buffer to decouple
the speed of the execution engine from the speed of the
memory system. The write buffers capture and FIFO processor address and data information in store operations, and
present it to the bus interface as write transactions at the rate
the memory system can accommodate. During main memory
writes, the R3041 can break a large datum (e.g. 32-bit word)
into a series of smaller transactions (e.g. bytes), according to
the width of the memory port being written. This operation is
transparent to the software which initiated the store, insuring
that the same software can run in true 32-bit memory systems.
The R3051 family read interface performs both single word
reads and quad word reads. Single word reads work with a
simple handshake, and quad word reads can either utilize the
simple handshake (in lower performance, simple systems) or
utilize a tighter timing mode when the memory system can
burst data at the processor clock rate. Thus, the system
designer can choose to use page or static column mode
DRAMs (and possibly use interleaving, if desired, in highperformance systems), or even to use simpler SRAM techniques to reduce complexity.
In order to accommodate slower quad word reads, the
R3051 family incorporates a 4-deep read buffer FIFO, so that
the external interface can queue up data within the processor
before releasing it to perform a burst fill of the internal caches.
In addition, the R3041 can perform on-chip data packing
when performing large datum reads (e.g., quad words) from
narrower memory systems (e.g., 16-bits). Once again, this
operation is transparent to the actual software, simplifying
migration of software to higher performance (true 32-bit)
systems, and simplifying field upgrades to wider memory.
Since this capability works for either instruction or data reads,
using 8-, 16-, or 32-bit boot PROMs is easily supported by the
R3041.

5.2

4

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

SYSTEM USAGE
The IDT R3051 family is specifically designed to easily
connectto low-cost memory systems. Typical low-cost memory
systems use inexpensive EPROMs, DRAMs, and application
specific peripherals.
Figure 4 shows some of the flexibility inherent in the R3041 .
I~ this example system, which is typical of a laser printer, a 32bit PROM interface is used due to the size of the PDL
interpreter. An embedded system can optionally use an 8-bit
boot PROM instead. A 16-bit font/program cartridge interface
is provided for add-in cards. A 16-bit DRAM interface is used

_

f?r a low-cost page frame buffer. In this system example, a
field or manufacturing upgrade to a 32-bit page frame buffer
is supported by the boot software and DRAM controller.
Embedded systems may optionally substitute SRAMs for the
DRAMs. Finally various 8/16/32-bit I/O ports such as RS-232/
422, SCSI, and LAN as well as the laser printer engine
interface are supported. Such a system features a very low
entry price, with a range of field upgrade options including the
ability to upgrade to a more powerful member of the R3051
family.

Clkln
IDT R3041
RISControlier

II

Control

• Addressl
Data

R3051

1

EPROM and

1

DRAM
Controller

1/0 Controller

,

1

I·········.
32-bit
EPROM

16-bit
Font
Cartridge

16-bit
DRAM

1/0

···

JL .........
I.·.·•••.•. ·.·.1\'.;Jv~"'''>.
<·DRAM····.···
••••••••••••••••••••••••••••••••

j

....
2905 drw 04

Figure 4. Typical R3041-Based Application

5.2

5

COMMERCIAL TEMPERATURE RANGE

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

DEVELOPMENT SUPPORT
The lOT R3051 family is supported by a rich set of development tools, ranging from system simulation tools through
PROM monitor and debug support, applications software and
utility libraries, logic analysis tools, and sub-system modules.
Figure 5 is an overview of the system development process
typically used when developing R3041 applications. The
R3051 family is supported in all phases of project development. These tools allow timely, parallel development of hardware and software for R3051 family based applications, and
include tools such as:
• Optimizing compilers from MIPS Technology, the acknowledged leader in optimizing compiler technology.
• Cross development tools, available in a variety of development environments.

System
Architecture
Evaluation

• The high-performance IDT floating point emUlation library
software.
• The IDT Evaluation Board, which includes RAM, EPROM,
1/0, and the IDT PROM Monitor.
• IDT Laser Printer System boards, which directly drive a lowcost print engine, and runs Adobe PostScript™ Page Description Language
• Adobe PostScript Page Description Language running on
the IDT R3051 family.
• The IDT/simTM PROM Monitor, which implements a full
PROM monitor (diagnostics, remote debug support, peek!
poke, etc.).
• IDTlkitTM (Kernel Integration Toolkit), providing library support and a frame work for the system run time environment.

System
Development
Phase

System
Integration
and Verfification

Software
DBG Debugger
PIXIE Profiler
MIPS Compiler Suite
Stand-Alone Libraries
Floating Point Library
Cross Development Tools
Adobe PostScript POL
MicroSoft Truelmage POL
PeerlessPage BIOS
lOT/kit

Hardware
Hardware Models
General CAD Tools
RISC Sub-systems
'341 Evaluation Board
Laser Printer System

2905 drw 05

Figure 5. R3041 Development Environment

5.2

6

IOTI9R30411NTEGRATEO RISController FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

PERFORMANCE OVERVIEW

SELECTABLE FEATURES

The R3051 family achieves a very high-level of performance. This performance is based on:
• An efficient execution engine: The CPU performs ALU
operations and store operations in a single cycle, and has
an effective load time of 1.3 cycles, and branch execution
rate of 1.5 cycles (based on the ability of the compilers to
avoid software interlocks). Thus, the R3041 achieves over
16 MI PS performance when operating out of cache.
• Large on-chip caches: The R3051 family contains caches
which are substantially larger than those on the majority of
embedded microprocessors. These large caches minimize
the number of bus transactions required, and allow the
R3051 family to achieve actual sustained performance very
close to its peak execution rate, even with low-cost memory
systems.
• Autonomous multiply and divide operations: The R3051
family features an on-chip integer multiplier/divide unit
which is separate from the other ALU. This allows the R3041
to perform multiply or divide operations in parallel with other
integer operations, using a single multiply or divide instruction rather than using "step" operations.
• Integrated write buffer: The R3041 features a four deep
write buffer, which captures store target addresses and data
at the processor execution rate and retires it to main
memory at the slower main memory access rate. Use of onchip write buffers eliminates the need for the processor to
stall when performing store operations.
• Burst read support: The R3041 enables the system
designer to utilize page mode, static column, or nibble mode
RAMs when performing read operations to minimize the
main memory read penalty and increase the effective cache
hit rates.

The R3051 family uses two methods to allow the system
designer to configure bus interface operation options.
The first set of options are established via the Reset
Configuration Mode inputs, sampled during the device reset.
After reset, the Reset Mode inputs become regular input or
output signals.
The second set of configuration options are contained in
the System Control Co-Processor registers. These Co-processor registers configuration options are typically initialized
with the boot PROM and can also be changed dynamically by
the kernel software.
Selectable features include:
• Big Endian vs. Little Endian operation: The part can be
configured to operate with either byte ordering convention,
and in fact may also be dynamically switched between the
two conventions. This facilitates the porting of applications
from other processor architectures, and also permits intercommunication between various types of processors and
databases.
• Data Cache Refill of one or four words: The memory
system must be capable of performing 4 word transfers to
satisfy instruction cache misses and 1 word transfers to
satisfy uncached references. The data cache refill size
option allows the system designers to choose between one
and four word refill on data cache misses, depending on the
performance each option brings to their application.
• Bus Turn Around speed: The R3041 allows the kernel to
increase the amount of time between bus transactions
when changes in direction of the AID bus occur (e.g., at the
end of reads followed by writes). This allows transceivers
and buffers to be eliminated from the system.
• Extended Address Hold Time: The R3041 allows the
system designer to increase the amount of hold time available for address latching, thus allowing slower speed (low
cost) address latches, FPGAs and ASICs to be used.
• Programmable control signals: The R3041 allows the
system designer to optimally configure various memory
control signals to be active on reads only, writes only, or on
both reads and writes. This allows the simplification of
external logic, thus reducing system cost.
• Programmable memory Port Widths: The R3041 allows
the kernel to partition the physical memory space into
various sub-regions, and to individually indicate the port
width of these sub-regions. Thus, the bus interface unit can
perform data packing and unpacking when communicating
with narrow memory sub-regions. For example, these features, can be used to allow the R3041 to interface with
narrow 8-bit boot PROMs, or to implement 16-bit only
memory systems.

The performance differences among the various R3051
family members depends on the application software and the
design of the memory system. Different family members
feature different cache sizes, and the R3081 features a
hardware floating point accelerator. Since all these devices
can be used in a pin and software compatible fashion, the
system designer has maximum freedom in trading between
performance and cost. The memory simulation tools (e.g.
Cache3041) allows the system designers to analyze and
understand the performance differences among these devices in their application.

5.2

7

II

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

THERMAL CONSIDERATIONS

NOTES ON SYSTEM DESIGN

The R3051 family utilizes special packaging techniques to
improve the thermal properties of high-speed processors.
Thus, all versions of the R3051 family are packaged in cavity
down packaging.
The lowest cost members of the family use a standard
cavity down, injection molded PLCC package (the "J" package). This package is used for all speeds of the R3041 family.
Higher speed and higher performance members of the
R3051 family utilize more advanced packaging techniques to
dissipate power while remaining both low-cost and pin- and
socket- compatible with the PLCC package. Thus, these
members of the R3051 family are available in the MOUAD
package (the "MJ" package), which is an all aluminum package with the die attached to a normal copper lead-frame
mounted to the aluminum casing. The MOUAD package is pin
and form compatible with the PLCC package. Thus, designers
can choose to utilize this package without changing their PCB.
The members of the R3051 family are guaranteed in a case
temperature range of O°C to +85°C. The type of package,
speed (power) of the device, and airflow conditions, affect the
equivalent ambient conditions which meet this specification.
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(0CA) of the given package. The following equation relates
ambient and case temperature:
TA = Tc - P * 0CA
where P is the maximum power consumption at hot temperature, calculated by using the maximum Icc specification forthe
device.
Typical values for 0CA at various airflows are shown in
Table 2 for the PLCC package.

The R3041 has been designed to simplify the task of highspeed system design .. Thus, set-up and hold-time requirements have been kept to a minimum, allowing a wide variety
of system interface strategies.
To minimize these AC parameters, the R3041 employs
feedback from its SysClk output to the internal bus interface
unit. This allows the R3041 to reference input signals to the
reference clock seen by the external system. The SysClk
output is designed to provide relatively large AC drive to
minimize skew due to slow rise or fall times. A typical part will
have less than 2ns rise orfall (10% to 90% signal times) when
driving the test load.
Therefore, the system designer should use care when
designing for direct SysClk use. Total loading (due to devices
connected on the signal net imd the routing of the net itself)
should be minimized to ensure the SysClk output has a
smooth and rapid transition. Long rise and/or fall times may
cause a degradation in the speed capability of an individual
device.
Similarly, the R3041 employs feedback on its ALE outputto
ensure adequate address hold time to ALE. The system
designer should be careful when designing the ALE net to
minimize total loading and to minimize skew between ALE and
the A/D bus, which will ensure adequate address access latch
time.
IDT's field and factory applications groups can provide the
system designer with assistance for these and other design
issues.

Airflow (ftlmin)
0CA
"J" Package
TQFP

0
29
55

200
26
40

400
21
35

600
18
33

800
16
31

1000
15
30
2905 tbl 02

Table 2. Thermal Resistance (0CA) at Various Airflows

5.2

8

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

....
C")

0'

0

~
Cl

m
~
Cl

OJ r:::-

to

0'

~
Cl

~

>

7

6

C\I

~

~

~

~

11
12

10

9

8

Vss
Vee
Clkln

CI)
CI)

e;;- N
C\I

~

~
Cl

>

~

Ii)
~
Cl

~

~

5

4

3

2

()
()

~
Cl

C\I

0'

~

N

~

()

CI)
CI)

~ >

~

84 83

0 m
.... OJ r:::- to
.... Ii)
C\I
0' 0' 0 0' 0' 0'
~ ~ 4: ~ ~ ~
T'"

0' 0'

82

81

80 79 78 77

76 75
74

Vss

13

73

Vee

14

72

A1D(14)

TriState

15

71

A1D(13)

BE16(1)

16

70

A1D(12)

BE16(O)

17

69

A1D(11)

Addr(1)

18

68

A1D(10)

Addr(O)

19

67

A1D(9)

Int(5)

20

66

Vee

Vss

21

65

Vss

Vee

22

64

A1D(8)

Int(4)

23

63

AID (7)

Int(3)

24

62

AID (6)

Slnt(2)

25

61

AID (5)

Slnt(1)

26

60

AID (4)

lOT R3041/RV3041

Slnt(O)

27

59

A1D(3)

SBrCond(3)!IOStrobe

28

58

Vss

SBrCond(2)! ExtDataEn

29

57

Vee

TC

30

56

AID (2)

Vss

31

55

A1D(1)

Vee

A1D(O)

Q)

.0
0

as

E
Q)
::2:

If I~ II
I~

IJ I~

Ii

CI)
CI)

()
()

> >

Ii

I~ I~

UJ

-I

«

I~

OJ

<1l

is

CI)
CI)

()

()

> >

g
-0
"0

«

~

-0
"0

«

tilQ)

z

~~

:J

III

2905 drw 06

84-Pin PLCCI
Top View
(Cavity Down)

5.2

9

II

COMMERCIAL TEMPERATURE RANGE

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

PIN CONFIGURATIONS

NC
NC

NC
NC
Vss
Vee

AlD(14)
AlD(13)
AlD(12)
AlD(11)
AlD(10)
AlD(9)
Vee
Vss

AlD(8)
AlD(7)
AlD(6)
AlD(5)
AlD(4)
AlD(3)

lOT R3041/RV3041
100-Pin
TQFP
(Cavity Up)
Top View

Vss
Vee

Vss
Vee
Clkln
TriState
BE16(1)
BE16(O)
Addr(1)
Addr(O)
Int(5)
Vss
Vee
Int(4)
Int(3)
Slnt(2)
Slnt(1)
Slnt(O)
SBrCond(3)/~
SBrCond(2)/ExtDataEn

TC

AlD(2)
AlD(1)
AlD(O)

Vss
Vee

NC
NC

NC
NC

2905 drw 06

5.2

10

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION
PIN NAME

110

AlD(31:0)

1/0

DESCRIPTION
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction
in one phase, and which is used to transmit data between the CPU and external memory resources during
the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:
Address(31 :4):

The high-order address for the transfer is presented on AlD(31 :4).

BE(3:0):

These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are presented on AlD(3:0). BE(3) indicates that
AlD(31 :24) will be used, and BE(O) corresponds to AlD(7:0). These
strobes are only valid for accesses to 32-bit wide memory ports. Note
that BE(3:0) can be held in-active during reads by setting the appropriate
bit of CPO; thus when latched, these signals can be directly used as Write
Enable strobes.

During the second phase, these signals are the data bus for the transaction.
Data(31 :0):

During write cycles, the bus contains the data to be stored and is driven
from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in
either a single data transaction or in a burst of four words, and places it
into the on-chip read buffer.
The byte lanes used during the transfer are a function of the datum size,
the memory port width, and the system byte-ordering.

Addr(3:0)

0

Low Address (3:0) A 4-bit bus which indicates which word/halfword/byte is currently expected by the
processor. For 32-bit port widths, only Addr(3:2) is valid during the transfer; for 16-bit port widths, only
Addr(3:1) are valid; for 8-bit port widths, all of Addr(3:0) are valid. These address lines always contain
the address ofthe current datum to be transferred. In writes and single datum reads, the addresses initially
output the specific target address, and will increment if the size of the datum is wider than the target
memory port. For quad word reads, these outputs function as a counter starting at '0000', and
incrementing according to the width of the memory port.

1(1)

During Reset, the Addr(3:0) pins act as Reset Configuration Mode bit inputs for the BootProm16,
BootProm8, ReservedHigh, and ExtAddrHold options.
The R3041 Addr(1 :0) output pins are designated as the unconnected Rsvd(1 :0) pins in the R3051 and
R3081.

Diag

0

Diagnostic Pin. This output indicates whether the current bus read transaction is due to an onchip cache miss and whether the read is an instruction or data. It is time multiplexed as described below:
Cached/Uncached:

During the phase in which the AID bus presents address information, this
pin is an active high output which indicates whether or not the current
read is a result of a cache miss. The value of this pin at this time other
than in read cycles is undefined.

110:

A high at this time indicates an instruction reference, and a low indicates
a data reference. The value of this pin at this time other than in read
cycles is undefined.

The R3041 Diag output pin is designated as the Diag(1) output pin in the R3051 and R3081.
ALE

0

Address Latch Enable: Used to indicate that the AID bus contains valid address information for
the bus transaction. This signal is used by external logic to capture the address for the transfer, typically
by using transparent latches.

DataEn

0

Data Enable: This signal indicates that the AID bus is no longer being driven by the processor
during read cycles, and thus the external memory system may enable the drivers of the memory
system onto this bus without having a bus conflict occur. During write cycles, or when no bus
transaction is occurring, this signal is negated, thus disabling the external memory drivers.

NOTE:

2905 tbl 03

1. Reset Configuration Mode bit input when Reset is asserted, normal signal
function when Reset is de-asserted.

5.2

11

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (Continued):
PIN NAME
BursV
WrNear

1/0
0

DESCRIPTION
Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current bus read
is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles
due to cache misses; it is asserted for alii-Cache miss read cycles, and for D-Cache miss read cycles
if the 4-word data block refill option is selected in the CPO Cache Config Register.
On write transactions, the WrNear output tells the external memory system that the bus interface unit
is performing back-to-back write transactions to an address within the same 256 byte page as the prior
write transaction. This signal is useful in memory systems which employ page mode or static column
DRAMs, and allows nearby writes to be retired quickly.

Rd

0

Read: An output which indicates that the current bus transaction is a read.

Wr

0

Write: An output which indicates that the current bus transaction is a write.

Ack

I

Acknowledge: An input which indicates to the device that the memory system has sufficiently
processed the bus transaction. On write transactions, this signal indicates that the CPU may either
progress to the next data item (for mini-burst writes of wide datums to narrow memories), or terminate
the write cycle. On read transactions, this signal indicates that the memory system has sufficiently
processed the read, and that the processor core may begin processing the data from this read transfer.

RdCEn

I

Read Buffer Clock Enable: An input which indicates to the device that the memory system has
placed valid data on the ND bus, and that the processor may move the data into the on-chip Read
Buffer.

SysClk

0

System Reference Clock: An output from the CPU which reflects the timing of the internal
processor "System" clock. This clock is used to control state transitions in the read buffer, write buffer,
memory controller, and bus interface unit.

BusReq

I

DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus
interface signals so that they may be driven by an external master. The negation of this input relinquishes
mastership back to the CPU.

BusGnt

0

DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has been
detected, and that the bus is relinquished to the external master.
The R3041 adds an additional DMA protocol, under the control of CPO. If the DMA Protocol is enabled,
the R3041 can request that the external master relinquish bus mastership back to the processor by
negating the BusGnt output early, and waiting for the BusReq input to be negated.

SBrCond(3)/
10Strobe

I/O

Branch Condition Port/IO Strobe: The use of this signal depends on the setting of various bits of the
CPO Bus Control register. If BrCond mode is selected, this input is logically connected to CpCond(3),
and can be used by the branch on co-processor condition instructions as an input port. The SBrCond(3)
input has special internal logic to synchronize the input, and thus may be driven by asynchronous
agents.
If this pin is selected to function as 10Strobe, it may be asserted as an output on reads, writes, or both,
as programmed into CPO. This strobe asserts in the second clock cycle of a transfer, and thus can be
used to strobe various control signals on the bus interface.

SBrCond(2)/
ExtDataEn

I/O

Branch Condition Port/Extended Data Enable: The use of this signal depends on the settings in the
CPO Bus Control register. If BrCond mode is selected, this input is logically connected to CpCond(2),
and can be used by the branch on co-processor condition instructions as an input port. The SBrCond(2)
input has special internal logic to synchronize the input, and thus may be driven by asynchronous
agents.
If this pin is selected to function as Extended Data Enable, it may be asserted as an output on reads,
writes, or both, as programmed into CPO. This strobe can be used as an extended data enable strobe,
in that it is held asserted for one-half clock cycle after the negation of Rd or Wr. This signal may typically
be used as a write enable control line for transceivers, as a write line for I/O, or as an address mux select
for DRAMs.

MemStrobe

0

Memory Strobe: This active low output pulses low for each data read or written, as configured in the
CPO Bus Control register. Thus, it can be used as a read strobe, write strobe, or both, for SRAM type
memories or for I/O devices.
The R3041 MemStrobe output pin is designated as the BrCond(O) input pin in the R3051 and R3081.
2905 tbl 04

5.2

12

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (Continued):
PIN NAME
BE16(1:0)

DESCRIPTION

1/0

0

Byte Enable Strobes for 16-bit Memory Port: These active low outputs are the byte lane strobes for
accesses to 16-bit wide memory ports; they are not necessarily valid for 8- or 32-bit wide ports. If BE16(1)
is asserted, then the most significant byte (either D(31 :24) or D(15:8), depending on system endianness)
is going to be used in this transfer. If BE16(0) is asserted, the least significant byte (D(23: 16) or D(7:0))
will be used.
BE16(1 :0) can be held inactive (masked) during read transfers, according to the programming of the CPO
Bus Control register.

1(1)

During Reset, the BE16(1 :0) act as Reset Configuration Mode bit inputs for two ReservedHigh options.
The BE16(1 :0) output pins are designated as the unconnected Rsvd(3:2) pins in the R3051 and R3081.

Last

0

Last Datum in Mini-Burst: This active low output indicates that this is the last datum transfer in a given
transaction. It is asserted after the next to last RdCEn (reads) or Ack (writes), and is negated when Rd
or Wr is negated.
The Last output pin is designated in the R3051 and R3081 as the Diag(O) output pin.

TC

0

Terminal Count: This is an active low output from the processor which indicates that the on-chip timer
has reached its terminal count. It will remain low for either 1.5 clock cycles, or until software resets the
timer, depending on the mode selected in the CPO Bus Control register. Thus, the on-chip timer can
function either as a free running timer for system functions such as DRAM refresh, or can operate as a
software controlled time-slice timer, or real-time clock.
The TC output pin is designated in the R3051 as the BrCond(1) input pin, and in the R3081 as the Run
pin output.

BusError

I

Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error.
This signal is only sampled during read and write operations. If the bus transaction is a read operation,
then the CPU will take a bus error exception.

Int(5:3)
Slnt(2:0)

I

Processor Interrupt: During normal operation, these signals are logically the same as the Int(5:0)
signals of the R3000A. During processor reset, these signals perform mode initialization of the CPU, but
in a different (simpler) fashion than the interrupt signals on the original R3000A.

1(1)

During Reset, Int(3) and Slnt(O) act as Reset Configuration Mode bit inputs for the
AddrDisplayAndForceCacheMiss and BigEndian options.
There are two types of interrupt inputs: the Sint inputs are internally synchronized by the processor,
and may be driven by an asynchronous external agent. The direct interrupt inputs are not internally
synchronized, and thus must be externally synchronized to the CPU. The direct interrupt inputs have
one cycle lower latency than the synchronized interrupts.

Clkln

I

Master Clock Input: This is a double frequency input used to control the timing of the CPU.

Reset

I

Master Processor Reset: This signal initializes the CPU. Reset initialization mode selection is
performed during the last cycle of Reset.

TriState

I

Tri-State: This input to the R3041 requests that the R3041 tri-state all of its outputs. In addition to those
outputs tri-stated during DMA, tri-state will cause SysClk, TC, and BusGnt to tri-state. This signal is
intended for use during board testing and emulation during debug and board manufacture.

Vcc

I

Power: These inputs must be supplied with the rated supply voltage (VeC). All Vcc inputs must be
connected to insure proper operation.

Vss

I

Ground: These inputs must be connected to ground (GND). All Vss inputs must be connected to insure
proper operation.

The TriState input pin is designated as the unconnected Rsvd(4)pin in the R3051 and R3081.

2905 tbl 05

NOTE:
1. Reset Configuration Mode bit input when Reset is asserted, normal signal
function when Reset is de-asserted.

5.2

13

II

IOTI9R30411NTEGRATEO RISControlier FOR LOW COST SYSTEMS

ABSOLUTE MAXIMUM RATINGS(1, 3) R3041
Symbol
VTERM
Te

Rating
Terminal Voltage with
Respect to GND
Operating Case Temperature

Commercial

Unit

-0.5 to +7.0

V

o to +85

°C

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Temperature
GND
Vee
Commercial

TSIAS

Temperature Under Bias

-55 to +125

°C

TSTG

Storage Temperature

-55 to +125

°C

Input Voltage

-0.5 to +7.0

V

VIN

COMMERCIAL TEMPERATURE RANGE

NOTES:
2905 tbt 06
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VIN minimum -3.0V for pulse width less than 15ns.
VIN should not exceed Vcc +0.5 Volts.
3. Not more than one output should be shorted at a time. Duration ofthe short
should not exceed 30 seconds.

OV

O°C to +85°C
(Case)

5.0±5%
2905 tbl 07

OUTPUT LOADING FOR AC TESTING

=

To Device
Under Test

AC TEST CONDITIONS R3041
Symbol

Parameter

Min.

VIH

Input HIGH Voltage

3.0

VIL

Input LOW Voltage

-

2905 drw07

Max.

0

Unit
V
V

VIHS

Input HIGH Voltage

3.5

-

V

VILS

Input LOW Voltage

-

0

V

Signal

Cld

All Signals

25 pF
2905 tbl 09

2905 tbl 08

DC ELECTRICAL CHARACTERISTICS R3041 -

(Te = O°C to +85°C, Vec = +5.0V ±5%)
16.67MHz

Symbol

Parameter

Test Conditions

Min.

Max.

20MHz
Min.

Max.

25MHz
Min.

Max.

33MHz
Max.

Min.

3.g"'" ........
- '''.'::''O::~

VOH

Output HIGH Voltage

Vee = Min., 10H = -4mA

VOL

Output LOW Voltage

Vee = Min., 10L = 4mA

VIH

Input HIGH Voltage(3)

VIL

Input LOW Voltage(1)

VIHS

Input HIGH Voltage(2,3)

VILS

Input LOW Voltage(1 ,2)

0.4

0.4

0.4

;;'::.:...... .0,,11-

CIN

Input Capacitance(4)

10

10

10

"ttO

COUT

Output Capacitance(4)

10

10

10

lee

Operating Current

Vee = 5V, Tc = 25°C

225

250

300

IIH

Input HIGH Leakage

VIH=VCC

100

100

1.00

IlL

Input LOW Leakage

VIL= GND

-100

loz

Output Tri-state Leakage

VOH = 2.4V, VOL = .o.5V

-1.0.0

3.5

3.5
0.4

2.0

0.4
2.0

0.8
3.0

3.0

-1.0.0

5.2

100

-1.00

V
V
V

.....

.....

--

.....

-1(jo'

V
pF
pF

370

mA

fop

~.

V

''''1'0

-100'''''
10.0

V

0.,8
3.0

-100

Unit

2.0 ::::;;\L::::~
.0.8

3.0

-100
1.00

0.4
2 ..0

0.8

NOTES:
1. VIL Min. -3.0V for pulse width less than 15ns. VIL should not fall below -0.5 volts for larger periods.
2. VIHS and VILS apply to elkin and Reset.
3. VIH should not be held above Vee + 0.5 volts.
4. Guaranteed by deSign.

=

3.5

······,\19,0

IlA
IJ.A

IlA
2905 tbll0

14

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS R3041 (1,2,3)_ (Tc =O°C to +85°C, VCC =+5.0V +5%)
-16.67MHz
Symbol
t1

Signals
BusReq, Ack, Bus Error, RdCEn

Description

Min.

Set-up to SysClk rising

8

Max.

-

20MHz
Min.
6

Max.

-

25MHz
Min.
5

33MHz

Max.

Min.

Max.

Unit

-

~A,ii::::i:,,::-

ns

J~

ns

t1a

AlD

Set-up to SysClk falling

9

-

6

-

~'

BusReq, Ack, BusError, RdCEn

Hold from SysClk rising

4

-

7

t2

3

-

2.5

-

2;5

t2a

AlD
AlD, Addr, Diag, ALE, Wr
BursVWrNear, Rd, DataEn

Hold from SysClk falling
Tri-state from SysClk rising
(after driven condition)

2

-

2

-

1.5

-

-

13

-

10

-

10

{:i~iiiiiiii:i~ ...
O
-

t4

AlD, Addr, Diag, ALE, Wr
BursVWrNear, Rd, DataEn

Driven from SysClk falling
(after tri-state condition)

-

13

-

10

-

10

-

t5

BusGnt

Asserted from SysClk rising

-

7

-sir :::m'!!

ns

Negated from SysClk falling

8

-

ns

Wr, Rd, BursVWrNear, TC

Valid from SysClk rising

5

-:fT

'4

t7a

AlD

Valid from SysClk rising

12

10

..,....

9.

ns

t7b

Last

Valid from SysClk rising

5

.4

ns

t8

ALE

Asserted from SysClk rising

4

..ii!::H:H:::':!;:is

ns

t9

ALE

Negated from SysClk falling

-

7

t7

-

8

BusGnt

-

10

t6

4

-

3

ns

t10

AlD

Hold from ALE negated

2

-

2

-

2

-

1jt:F'''''''''!'!7

ns

t11

DataEn

Asserted from SysClk

-

19

-

15

-

15

-

t12

DataEn

Asserted from AlD tri-state(4)

0

-

0

-

0

o'::'i/

0

t3

ns
ns
ns

',,'i

;'" '"

10
8
15
8
5
5

6

5
4
4

1p

.""'' ,,.

ns

ns

/!::"13

ns

t14

AlD

Driven from SysClk rising(4)

0

-

-

0

-

QW'"",;-

ns

t15

Wr, Rd, DataEn, BursVWrNear,
Last, TC

Negated from SysClk falling

-

9

-

7

-

6

-

5

ns

t16

Addr(3:0), BE 16(1 :0)

Valid from SysClk

-

8

6

-

6

-

Diag

Valid from SysClk

-

15

12

11

t18

AlD

Tri-state from SysClk

13

10

-'~2':

t19

AlD

SysClk to data out

-

13

-

",,,:' i"5
-7~' 10

ns

t17

-

12

-

t20

Clkln

Pulse Width High

12

-

10

-

8

t21

Clkln

Pulse Width Low

12

-

10

-

8

-

t22

Clkln

Clock Period

30

250

25

250

20

250

200

-

200"·

32

32

16

10

t23

Reset

Pulse Width from Vcc valid

200

-

200

t24

Reset

Minimum Pulse Width

32

-

32

-

6

2.5

-

6

-

5

-

-

ns

,:

ns

10

ns

·'10

ns

6;5:",

-

ns

15....

50

ns

-

sys

6.5:i[

ns

Ils

5,di mi:i:i>-

ns

5!

..,-

ns

215

..,..

ns

5;;:::::7-

ns

-

3

ns

-

5

t25

Reset

Set-up to SysClk falling

8

t26

Int

Mode set-up to Reset rising

8

t27

Int

Mode hold from Reset rising

2.5

t28

Slnt, SBrCond

Set-up to SysClk falling

8

-

t29

Slnt, SBrCond

Hold from SysClk falling

4

-

3

-

3

t30

Set-up to SysClk falling

8

-

6

-

5

t31

Tnt, BrCond
Tnt, BrCond

Hold from SysClk falling

4

-

3

-

3

tsys

SysClk

Pulse Width

2*t22

2*t22

2*t22

t32

SysClk

Clock High Time

t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22

-2 ::t22+2

ns

t33

SysClk

Clock Low Time

t22 - 2 t22 + 2 t22 - 2 t22+2 t22 - 2 t22 + 2 t22 - 2 t22:+ 2

ns

6

2*t22

5
5
2.5

2*t22

2*t22

3

±
-

ns
ns

...

2*122'· :2*t22

ns

2905 tbl11

5.2

15

II

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS R3041 (CO NT.)
16.67MHz
Symbol
t45

Signals
ExtDataEn

Description
Tri-state from SysClk rising
(after driven condition)

Min.

t46

ExtDataEn

Driven from SysClk falling
(after driven condition)

t47

IOStrobe

Valid from SysClk falling

t48

ExtDataEn, DataEn

Asserted from SysClk rising

t49

ExtDataEn

Negated from SysClk rising

9

t50

MemStrobe

Asserted from SysClk rising

t51

MemStrobe

Negated from SysClk falling

Max.
13

Min.

MemStrobe

Asserted from Addr(3:0) valid(4)

tderate

All outputs

Timing deration for loading
over 25pF(4, 5)

Max.

Min.

33MHz

Max.

10

10

10

10

10

8

15

12
7

6

19

15

13

19

15

13

13

t52

25MHz

20MHz

0

0

: ··········"",,,,,10

ns

7

';'::::'"::::;;;,,,..7

ns

9

""",,::::............ 9

ns

--

11
.. 11

ns
ns

~:."·"::.i\:::;:~·5

nsl

...

0

0.5

0.5

ns
0.5

25pF

NOTES:
2905 tbl12
1. All timings referenced to 1.5 Volts, with a rise and fall time of less than 2.5ns.
2. All outputs tested with 25pF loading.
3. The AC values listed here reference timing diagrams contained in the R3041 Hardware User's Manual.
4. Guaranteed by design.
5. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
6. Timings t34 - t44 are reserved for other R3051 family members.

ABSOLUTE MAXIMUM RATINGS(1, 3) RV3041
Symbol
VTERM
Tc

Rating
Terminal Voltage with
Respect to GND

Commercial
-0.5 to +7.0

Unit
V

o to +85

°C

Operating Case Temperature

TBIAS

Temperature Under Bias

-55 to +125

°C

TSTG

Storage Temperature

-55 to +125

°C

Input Voltage

-0.5 to +7.0

V

VIN

NOTES:
2905 tbl 06
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VIN minimum -3.0V for pulse width less than 15ns.
VIN should not exceed Vee +0.5 Volts.
3. Not more than one output should be shorted at a time. Duration ofthe short
should not exceed 30 seconds.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Temperature
Vee
GND
Commercial
RV3041

O°C to +85°C
(Case)

3.3±5%

OV

2905 tbl 07

OUTPUT LOADING FOR AC TESTING

=

To Device
Under Test

AC TEST CONDITIONS RV3041
Symbol

Parameter

2905 drw07

Min.

Max.

Unit

VIH

Input HIGH Voltage

3.0

-

V

VIL

Input LOW Voltage

-

0

V

VIHS

Input HIGH Voltage

3.0

-

V

VILS

Input LOW Voltage

-

0

Signal

Cld

All Signals

2SpF

,." ,. J

V
2905 tbl 08

5.2

16

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS RV3041 -

(Te

Symbol

Min.

= O°C to +85°C, Vee = +3.3V ±5%)
20MHz

16.67MHz

VOH

Parameter
Output HIGH Voltage

VOL

Output LOW Voltage

VIH

Input HIGH Voltage(3)

VIL

Input LOW Voltage(1)

Test Conditions
Vee = Min., 10H = -4mA

Max.

Min.

2.4

25MHz

Max.

Min.

2.4

2.4

0.4

Vee = Min., 10L = 4mA

0.4

2.0

33MHz

Max.

0.4

2.0

2.0

0.8

0.8

Input HIGH Voltage(2,3)
Input LOW Voltage(1,2)

0.4

0.4

0.4

CIN

Input Capacitance(4)

10

10

10

COUT

Output Capacitance(4)

lee

Operating Current

2.5

IIH

Input HIGH Leakage

VIH = VCC

IlL

Input LOW Leakage

VIL= GND

-100

loz

Output Tri-state Leakage

VOH = 2.4V, VOL = 0.5V

-100

2.5

10

10

10

150

180

100

100

-100
100

-100

-100

r"L
?;o···

V

....... ",,0..8

V

100

V

-100

~

V

10

pF

':'::':" ..10

pF

.......... 225

mA

...100

mA

-100.",/"
100

V

..... \).4
...

130
100

V

'0..4

25':::>

VIHS

Vee = 3.3V, Te = 25°C

~~4"",.·· ......

0.8

VILS

2.5

MiD~.;;,. .Max. Unit

;.....-

-106 ·····100

NOTES:
VIL Min. = -3.0V for pulse width less than 15ns. VIL should not fall below -0.5 volts for larger periods.
VIHS and VILS apply to Clkln and Reset.
VIH should not be held above Vee + 0.5 volts.
Guaranteed by design.

mA
mA
2905 tbl10

1.
2.
3.
4.

AC ELECTRICAL CHARACTERISTICS RV3041
~ymbol
tl

Signals

(1,2,3)_ (Te

16.67MHz
Min. Max.

Description

II

= ooe to +85°e, Vee = +3.3V +5%)
20MHz
Min. Max.

BusReq, Ack, BusError,
RdCEn

Set-up to SysClk rising

11

-

8

-

tla

AID

Set-up to SysClk falling

12

BusReq, Ack, BusError,
RdCEn

Hold from SysClk rising

4

-

9

t2

3

25MHz
33MHz
Min. Max. IMm. Max. Unit
5.5

-

-

7

-

2.5

ns

-

:7

ns

-

2':'5"''''''''''''''L-

ns
ns

t2a

AID

Hold from SysClk falling

2

-

AID, Addr, Diag, ALE, Wr

-

13

-

10

-

10

.. 10

ns

BurstlWrNear, Rd, DataEn

Tri-state from SysClk rising
(after driven eonditionl

t4

AID, Addr, Diag, ALE, Wr
BurstlWrNear, Rd, DataEn

Driven from SysClk falling
(after tri-state condition)

-

13

-

10

-

10

·0

ns

t5
t6

BusGnt
BusGnt

Asserted from SysClk rising
Negated from SysClk falling

-

10
10

-

8
8

7
7

ns
ns

t7

Wr, Rd, BurstlWrNear, TC

-

8

-

6

t7a

AID

Valid from SysClk rising
Valid from SysClk rising

12

Last

Valid from SysClk rising

9

-

8

-: ...;;"U,,::'18
.3L .... ) 8

t8

ALE
ALE

Asserted from SysClk rising

-

5
5

-

9

t7b

-

-

·...... ·';;""·7

-

4
4

-

4

h7.

-

4

- · .. ·"'4
i;['f:j"'''''

t9
tl0

AID

tll

DataEn

t12

DataEn
AID

t14

Negated from SysClk falling
Hold from ALE neqated

12

-

1

-

j:'..... "... ''',:
1.1 . 11. .L-

t3

2

-

5':~::n:'::"::i-

5
8

2

-

2

-

2

Asserted from SvsClk
Asserted from AID tri-state(4)
Driven from SysClk rising(4)

-

19

-

15

-

15

0
0

-

0
0

-

0
0

-

Negated from SysClk falling

-

9

-

7

-

6

-

8

-

7

12

-

11

t15

Wr, Rd, DataEn,
BurstIWrNear Last TC

t16

Addr(3:0), BE 16(1 :0)

Valid from SysClk

-

11

t17

Diag

Valid from SysClk

-

15

-

-

~:::".
::'

7
"'5

""'4

.........

... 15

b
:~.

ns
ns
ns
ns
ns
ns

.)

ns
6

ns

"''',:"... 7

ns

11

ns

-:"":':;:1:,:::::1

-

ns
ns

2905 tbl11

5.2

17

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS RV3041 (CO NT.)
16.67 MHz
Symbol

Signals

Description

Min.

Max.

20 MHz
Min.

25MHz

Max.

Tri-state from SysClk

-

13

-

10

t19

NO
NO

SysClk to data out

-

16

-

13

t20

Clkln

Pulse Width HiQh

12

10

t21

Clkln

Pulse Width Low

12

-

10

-

t22

Clkln

Clock Period

30

250

25

250

t23

Reset

Pulse Width from Vee valid

-

200

-

t18

200

32

Min.

-

33MHz

Max.

Min.

Max.

Unit

10

-

10

ns

12

-::::':".

:':1'12

ns

.......

ns

8

-

6.5

8

-

6.5"

20

250

15

200

-

ns

20'0'

;,

~b

ns

-'-

us

1

sys

.......

ns

t24

Reset

Minimum Pulse Width

32

t25

Reset

Set-up to SysClk fallinfl

8

-

6

-

5

-

5

t26

irit

Mode set-up to Reset rising

8

6

-

S

Int

Mode hold from Reset rising

2.5

2.5

2.5

Slnt, SBrCond

Set-up to SysClk falling

8

t29

Slnt, SBrCond

Hold from SysClk falling

4

-

3

-

2:5

t28
t30

Int, BrCond

Set-up to SysClk falling

8

-

6

-

5

t27

-

t31

Int, BrCond

Hold from SysClk falling

4

-

3

-

tsys

SysClk

Pulse Width

2*t22

2*t22

t32

SysClk

Clock High Time

t22 - 2

t22 + 2

t22 - 2 t22 + 2 t22 - 2 t22 +2 t22 - 2.,122:+ 2

t33

SysClk

Clock Low Time

t22 - 2

t22 + 2

t22 - 2 t22 + 2 t22 - 2 t22 + 2 t22 W,'2't22 + 2

t45

ExtDataEn

Tri-state from SysClk rising
(after driven condition)

-

13

-

10

-

10

''':''40

ns

t46

ExtDataEn

Driven from SysClk falling
(after driven condition)

-

13

-

10

-

10

~"U:!~;;;i:'jlO

ns

-

9

6

2*t22

32

250

2*t22

3
5
3
2*t22

2*t22

ns
ns

5'lj:':::nn::::L

ns

:t ............
5 ,:i::"_

ns

~::::/'

ns

2*t22

2*t22

ns
ns
ns
ns

!:'3

t47

IOStrobe

Valid from SysClk falling

-

10

-

8

t48

ExtDataEn,

Asserted from SysClk rising

15

ExtDataEn
DataEn

Negated from SysClk rising

-

12

t49

-

t50

MemStrobe

Asserted from SysClk rising

-

15

MemStrobe

Ne~ated

-

19

t51

19

-

15

t52

MemStrobe

Asserted from Addr(3:0) valid(4)

0

-

0

-

tderate

All outputs

Timing deration for loading
over 25pF(4. 5)

-

0.5

-

0.5

from SysClk fallinQ

5

~

9

7

7

-

7

ns

-:::::!H:::U'::::~

ns

6

ns

1"",,,,,,,,,,,,,,,'
15

-

15

ns

15

-

",,:::15

ns

0

-

O;:L"J -

-

0.5

-

-

''''0,5

ns
nsf
25pF

NOTES:
2905 tbl12
1. All timings referenced to 1.5 Volts, with a rise and fall time of less than 2.5ns.
2. All outputs tested with 25pF loading.
3. The AC values listed here reference timing diagrams contained in the R3041 Hardware User's Manual.
4. Guaranteed by design.
5. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
6. Timings 134 . 144 are reserved for other R3051 family members.

5.2

18

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

t22

Clkln

{

t20

t

SysClk

:f
2905 drw 08

Vcc

Clkln

t23

2905 drw 09

Figure 9. Power-On Reset Sequence

Clkln

2905 drw 10

Figure 10(a). Warm Reset Sequence

Clkln

t~----------~h~2-------------{

2905 drw 11

Figure 10(b). Warm Reset Sequence (Internal Pull-Ups Used)

-It-

-'

...,r-

t25
t26 ~

Mode Vector '(pu)s:
Slnt(2:0), Int 5:3
Mode Vector In~uts:
Addr(3:0), BE16 1:0)

~

External Device Drives Signals

.... ['"

,to.

~ t'"

..,r~t27

""

k

CPU Drives

~

2905 drw 12

Figure 11. Mode Selection and Negation of Reset

5.2

19

1DT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

Turn
Bus

Address
Memory

Sample
Data?

t14

AlD(31 :0) - - - - - I f - I E -

Addr(3:2)

ALE

Diag

____________

~-J

2905 drw 13

Figure 12(a). Start of Read Timing with Non-Extended Address Hold Option

Address
Memory

Extend
Address

Sample
Data?

t14

AlD(31:0) -----~

Addr(3:2)

ALE

DataEn

Diag

Cached?
2905 drw 14

Figure 12(b). Start of Read Timing with Extended Address Hold Option

5.2

20

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

Address

Data
Phase

Memory

End
Write?

t14

AlD(31:0) - - - - - - t - - t f --~----r--J

Addr(3:2)

Data
Out

-------------r--J

ALE

ExtDataEn
-

t7

2905 drw 15

Figure 12(c). Start of Write Timing with Non-Extended Address Hold Option

Address

Memory

Extended
Address

End
Write?

SysClk

Wr
t14
Data
Out

AlD(31:0) - - - - - - t - - t f -

Addr(3:2)

-------------r--J

ALE

ExtDataEn
_

t7

2905 drw 16

Figure 12(d). Start of Write Timing with Extended Address Hold Option

5.2

21

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

Run/
Stall

Stall

Stall

COMMERCIAL TEMPERATURE RANGE

Stall

Stall

Stall

Fixup

PhiClk

ND(31:0)

Addr(3:2) -----J-.JI"-....--_.---r---r-_ _-.-_ _ _ _---r_ _~--,_II " - -_ _ _ _ __

ALE _ _ _ _--+..J

ExtDataEn

MemStrobe

Diag _________~'I~-r----~'I~-~--~-------~----~----~I-------------Start Extended Ack/
Read Address RdCEn

?

Ack/
RdCEn

?

Ack/ Sample
RdCEn Data

End
Read
2905 dlW 17

Figure 13. Single Datum Read

5.2

22

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

Run/
Stall

Stall

Stall

COMMERCIAL TEMPERATURE RANGE

Stall

Stall

Stall

Fixup

Stall

PhiClk

SysClk

Rd

AlD(31:0)

Addr(3:0)

ALE

DataEn

ExtDataEn

Burst

Last

MemStrobe

IOStrobe

RdCEn

Ack

Diag
Start Extended RdCEn
Read Address

Sample RdCEn Sample RdCEn Sample Ackl Sample
New
Data
Data
Data RdCEn Data Transaction
2905 drw 18

Figure 14. Mini-burst read of 32-bit datum from 8-bit wide memory port

5.2

23

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

Run/
Stall

Stall

Stall

COMMERCIAL TEMPERATURE RANGE

Refill/
Fixup

Refill/
Stream/
Fixup

Refill/
Stream/
Fixup

Refill/
Stream/
Fixup

Word 0

Word 1

Word 2

Word 3

Stall

PhiClk

SysClk

Rd

ND(31:0)

Addr(3:2)

ALE

DataEn

ExtDataEn

Burst

Last

MemStrobe

IOStrobe

RdCEn

Ack

Diag
Start Extended Ack/
Read Address RdCEn

New
Sample RdCEn Sample RdCEn Sample RdCEn Sample
Data
Data
Data
Data Transaction
2905 drw 19

Figure 15. R3041 Quad Word Read

5.2

24

1DT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

Run/
Stall

Stall

Stall

COMMERCIAL TEMPERATURE RANGE

Stall

Stall

Stall

Stall

Stall

PhiClk

AlD(31:0)

Addr(3: 1) _ _ _ _--+....1 '--r-----.-,----r....J '--r------.---III '----.._ _---.--' 1~__r_---.-.I1

'--r---

ALE - - - - - 4 . . . . J 1

II

BE16(1 :0) - - - - - - t - - ' '--r----T'"'"'T--~ I '----,-----,---' I '---.---y-.I1 '--r-----,~ I '---.....,....--

DataEn

I

ExtDataEn

Last

MemStrobe

RdCEn

Ack

Diag _ _ _ _ _+_' I'--'---"T"'""'I ,-"""T"""----r----,---~--_r_--___r"--___r---r_-Start Extended RdCEn
Read Address

Sample RdCEn
Data

Sample RdCEn Sample RdCEn Sample
Data
Data
Data

RdCEn
2905 drw 20

Figure 16(a). Quad Word Read to 16-bit wide Memory Port

5.2

25

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

Stall

COMMERCIAL TEMPERATURE RANGE

Refill!
Fixup

Refill!
Stream!
Fixup

Refill!
Stream!
Fixup

Refill!
Stream!
Fixup

Word 0

Word 1

Word 2

Word 3

Stall

PhiClk

SysClk

Rd

ND(31:0)

Addr(3:1)

ALE

BE16(1 :0)

DataEn

ExtDataEn

Burst

Last

MemStrobe

IOStrobe

RdCEn

Ack

Diag
Ackl
RdCEn

Sample RdCEn Sample RdCEn Sample RdCEn Sample
New
Data
Data
Data
Data Transaction
2905 drw21

Figure 16(b). End of Quad Word read from 16-bit Wide Memory Port

5.2

26

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

SysClk

Wr

AlD(31:0)

Addr(3:2)

ALE

ExtDataEn

WrNear

II

Last

MemStrobe
t50
IOStrobe

Ack
Start Extended Data Out/
Write Address
Ack?

Ack?

Negate
New
Write Transfer

2905 drw 22

Figure 17. Basic Write to 32-bit Memory Port

5.2

27

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

NO(31:0)

Addr(3:0) -----f-..II"--r-----.r----~--_r_'I"--~-_r.....lI~"""T""--"T""""'I"---

ALE - - - - - f - . . I 1

ExtDataEn

MemStrobe

Start Extended
Write Address

Negate
New
Write Transaction
2905 drw23

Figure 18. Trl-Byte Mini-burst Write to 8-bit Port

5.2

28

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

~"

/1{'

BusReq

COMMERCIAL TEMPERATURE RANGE

~K

.Ii'

~ ~
tlt-.

I

~
t3

'\

AlD(31:0)

J

Addr(3:0)

\
J
'\

Diag

/

"
"

/
/
ALE

Last,
BE16(1:0),
MemStrobe

/

/

"

/

"

/

"'

t45

I

/

ExtDataEn

2905 drw 24

Figure 19. Request and Relinquish of R3041 Bus to External Master

5.2

29

COMMERCIAL TEMPERATURE RANGE

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

~K.

/E

--t=~

~,

/'t'

I

BusGnt

t9'
t4

<
<
-<

/

A/O(31:0)

"-

Addr(3:0)

"-

/

/

Oiag

"/

'"
'"

/

ALE

/

"/

cast.

'"

/

BE16(1 :0)
MemStrobe

/
t46

ExtDataEn

V
I

I

I

I

'"
'"
'"
2905 drw25

Figure 20. R3041 Regaining Bus Mastership

5.2

30

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

CPU Bus
Request

COMMERCIAL TEMPERATURE RANGE

---+---+--1

BusReq ___

~~

___

~

___+-____

~

____

~~'~-+-J

AlD(31:0)

BusGnt
2905 drw 26

Figure 21. R3041 DMA Pulse Protocol

Run Cycle

Exception Vector

Phi

t2B

t29

2905 drw 27

Figure 22. Synchronized Interrupt Input Timing

Run Cycle

Exception Vector

Phi

t30

2905 drw 28

t3l

Figure 23. Direct Interrupt Input Timing

Run Cycle
Phi /

V

V

~

SBrCond(n)

BCzT/F Instruction

Capture BrCond

1/

V

r

":1<-

~~

~~
t2B t29

2905 drw 29

Figure 24. Synchronized Branch Condition Input Timing

5.2

31

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

=:ft7~

SysClk
TC

'"

COMMERCIAL TEMPERATURE RANGE

J

/

:L
~/

/
t15

"--

:F

2905 drw 30

Figure 25. TC Output

84 LEAD PLCC (SQUARE)
~-----D-----~

45° x .045

-H------

+

- - - - - t - f " E1

B

SEATING PLANE
2905 drw 31

DWG#

J84-1

# of Leads

84

NOTES:

Symbol

Min.

Max.

A

165

.180

A1

.095

.115

S

.026

.032

b1

.013

.021

C

.020

.040

C1

.008

.012

0

1.185

1.195

01

1.150

1.156

D2/E2

1.090

1.
2.
3.
4.

All dimensions are in inches, unless otherwise noted.
BSC-Basic lead Spacing between Centers.
D & E do not include mold flash or protutions.
Formed leads shall be planar with respect to one another and within .004"
at the seating plane .
5. ND & NE represent the number of leads in the D & E directions respectively.
6. D1 & E1 should be measured from the bottom of the package .
7. PLCC is pin & form compatible with MQUAD; the MQUAD package is used
in other R3051 family members .

1.130
1.000 REF

03/E3
E

1.185

E1

1.150

1.195
1.156

e

.050 SSC

NO/NE

21
2905 tbl13

5.2

32

IDT79R3041 INTEGRATED RISControlier FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

10Q-PIN TQFP

100

100-Pin
TQFP

Standoff 0.05 Min

t

B~r--t

f

Max 0.102 Lead
Coplanarity

DWG#

TQFP

100

# of Leads
Symbol

Min.

Max.

A

-

1.60

A1

0.5

0.15

A2

1.35

1.45

0

15.75

16.25

01

13.95

14.05

E

15.75

16.25

E1

13.95

14.05

L

0.45

0.70
100

N

e

0.50SSe
0.17

0.27

ccc
ddd

-

0.08

-

0.08

R

0.08

R1

0.08

-

8

0

7.0
13.0

b

0.20

81

11.0

82

11.0

13.0

c

0.09

0.16
2905 tbl14

5.2

33

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
XXXXX
lOT - - Device Type

-

XX

X

X

Speed Package

Process/
Temp. Range

~

IBlank

L------------I

~--------------------------~

Commercial Temperature Range

'J'
'PF'

84-Pin PLCC
1~O-Pin TQFP

'16'
'20'
'25'

16.67MHz
20.00MHz
25.00MHz

79R3041

5.0V Integrated RISControlier
for Low-Cost Systems
3.3V Integrated RISControlier
for Low-Cost Systems

79RV3041

2905 drw 32

VALID COMBINATIONS
IDT 79R3041 79R3041 79R3041 79RV3041
79RV3041
79RV3041

16
20
25
- 16
- 20
- 25

TOFP,
TOFP,
TOFP,
TOFP,
TOFP,
TOFP,

PLCC
PLCC
PLCC
PLCC
PLCC
PLCC

Package
Package
Package
Package
Package
Package

5.2

34

I DT79R3051 n9R3052

IDT79R3051'M, 79R3051 E

RISControliers™

IDT79R3052™, 79R3052E

Integrated Device Technology. Inc.

FEATURES:
• Instruction set compatible with IDT79R3000A and
IDT79R3001 MIPS RISC CPUs
• High level of integration minimizes system cost, power
consumption
- IDT79R3000A IIDT79R3001 RISC Integer CPU
- R3051 features 4KB of Instruction Cache
- R3052 features 8KB of Instruction Cache
- All devices feature 2kB of Data Cache
- "E" Versions (Extended Architecture) feature full
function Memory Management Unit, including 64entry Translation Lookaside Buffer (TLB)
- 4-deep write buffer eliminates memory write stalls
- 4-deep read buffer supports burst refill from slow
memory devices

Clk2xln

Clock
Generator
Unit

I

•
•
•
•
•
•

- On-chip DMA arbiter
- Bus Interface minimizes design complexity
Single clock input with 40%-60% duty cycle
35 MIPS, over 64,000 Dhrystones at 40MHz
Low-cost 84-pin PLCC packaging that's pin-/packagecompatible with thermally enhanced 84-pin MQUAD.
Flexible bus interface allows simple, low-cost designs
20, 25, 33, and 40MHz operation
Complete software support
- Optimizing compilers
- Real-time operating systems
- Monitors/debuggers
- Floating Point Software
- Page Description Languages

I

Master Pipeline Control

System Control
Coprocessor

l

l

Exception/Control
Registers

BrCond(3: 0)

Integer
CPU Core

General Registers
(32 x 32)

Memory Management
Registers

ALU
Shifter

Int(5:0)

MultiDiv Unit

Translation
Lookaside Buffer
(64 entries)

Address Adder
PC Control

t

t

3~~

I

Virtual Address

Physical Address Bus

~

~
"nstruction

Data

Cache
(2kB)

Cache
(SkB/4kB)

t

y

Data Bus

t

Bus Interface Unit
4-deep
Write
Buffer

4-deep
Read
Buffer

Address/
Data

I

DMA
Arbiter

1

3~~

t

BIU
Control

t t l

DMA
Ctrl

Rd/Wr
Ctrl

SysClk
2874 drw 01

Figure 1. R3051 Family Block Diagram
The lOT logo is a registered trademark. and RISChipset, RISController. R3041, R3051. R3052. R3071. R3081, R3720, R4400 and R4600 are trademarks of Integrated Device TechnologY,lnc.

COMMERCIAL TEMPERATURE RANGE
©1995 Integrated Device Technology. Inc.

SEPTEMBER 1995
5.3

DSC-3000/S

1

IDT79R30S1n9R3052 INTEGRATED RISControliers

INTRODUCTION
The IDT IDT79R3051 family is a series of high-performance 32-bit microprocessors featuring a high level of integration which are targeted to high-performance, but costsensitive embedded processing applications. The IDT79R3051
family is designed to bring the high-performance inherent in
the MIPS RISC architecture into low-cost, simplified, powersensitive applications.
Functional units were integrated onto the CPU core in order
to reduce the total system cost, without significantly degrading
system performance. Thus, the IDT79R3051 family is able to
offer 35MIPS of integer performance at 40MHz without requiring external SRAM or caches.
Furthermore, the IDT79R3051 family brings dramatic power
reduction to these embedded applications, allowing the use of
low-cost packaging fordevices up to 25 MHz. The IDT79R3051
family allows customer applications to bring maximum performance at minimum cost.
Figure 1 shows a block-level representation of the functional units within the IDT79R3051 family. The IDT79R3051
family could be viewed as the embodiment of a discrete
solution built around the IDT79R3000A or IDT79R3001.
However, by integrating this functionality on a single chip,
dramatic cost and power reductions are achieved.
Currently, there are four members of the IDT79R3051
family. All devices are pin- and software-compatible: the
differences lie in the amount of instruction cache, and in the
memory management capabilities of the processor:
• The IDT79R3052"E" incorporates BkB of Instruction Cache,
and features a full-function Memory Management Unit
(MMU), including a 64-entry fully-associative Translation
Lookaside Buffer (TLB). This is the same MMU incorporated
into the IDT79R3000A and IDT79R3001.
• The IDT79R3052 also incorporates BkB of Instruction Cache.
However, the MMU is a much simpler subset of the capabilities of the enhanced versions of the architecture, and in fact
does not use a TLB.
• The IDT79R3051 "E" incorporates 4KB of Instruction Cache.
Additionally, this device features the same full-function
MMU (including TLB file) as the IDT79R3052"E", and
IDT79R3000A.
• The IDT79R3051 incorporates 4KB of Instruction Cache,
and uses the simpler memory management model of the
IDT79R3052.
An overview of the functional blocks incorporated in these
devices follows.

CPU Core
The CPU core is a full 32-bit RISC integer execution
engine, capable of sustaining close-to single cycle execution
rate. The CPU core contains a five stage pipeline and 32
orthogonal 32-bit registers. The IDT79R3051 family implements the MIPS ISA. In fact, the execution engine of the
IDT79R3051 family is th e same as the execution engine of the
IDT79R3000A (and IDT79R3001). Thus the IDT79R3051
family is binary-compatible with those CPU engines.

COMMERCIAL TEMPERATURE RANGE

The execution engine of the IDT79R3051 family uses a
five-stage pipeline to achieve close-to single cycle execution.
A new instruction can be started in every clock cycle; the
execution engine actually processes five instructions concurrently (in various pipeline stages). Figure 2 shows the
concurrency achieved by the IDT79R3051 family pipeline.

1#1

MEM WB
ALU

RD
IF
1#5

Current
CPU
Cycle

2874 drw02

Figure 2. R3051 Family 5-Stage Pipeline

System Control Co-Processor
The R3051 family also integrates on-chip the System
Control Co-processor, CPO. CPO manages both the exception handling capability of the IDT79R3051 family, as well as
the virtual to physical mapping of the IDT79R3051 family.
There are two versions of the IDT79R3051 family architecture: the Extended Architecture Versions (the IDT79R3051 E
and IDT79R3052E) contain a fully associative 64-entry TLB
which maps 4KB virtual pages into the physical address
space. The virtual to physical mapping thus includes kernel
segments which are hard mapped to physical addresses, and
kernel and user segments which are mapped on a page basis
by the TLB into anywhere within the 4GB physical address
space. In this TLB, B-page translations can be "locked" by the
kernel to insure deterministic response in real-time applications. These versions thus use the same MMU structure as
that found in the IDT79R3000A and IDT79R3001. Figure 3
shows the virtual-to-physical address mapping found in the
Extended Architecture versions of the processor family.
The Extended Architecture devices allow the system
designer to implement kernel software to dynamically manage
User task utilization of memory resources, and also allow the
Kernel to effectively "protect" certain resources from user
tasks. These capabilities are important in a number of
embedded applications, from process control (where resource
protection may be extremely important) to X-Window display
systems (where virtual memory management is extremely
important), and can also be used to simplify system debugging.

5.3

2

IDT79R3051179R3052 INTEGRATED RISCantraliers

COMMERCIAL TEMPERATURE RANGE

VIRTUAL

PHYSICAL

Oxffffffff

Kernel Mapped
(kseg2)

Any

OxcOOOOO 00 1 - - - - - - - - - - - 1

Kernel Uncached
(kseg1)
OxaOOOOOOO

Physical
Memory

~-------~

3548MB

Kernel Cached
(ksegO)
Ox80000000

~-------~

User Mapped
Cacheable
(kuseg)
Memory
OxOOOOOOOO

512MB
2874 drw 03

1.-_ _ _ _ _ _ _- . 1

Figure 3. Virtual-to-Physical Mapping of Extended Architecture Versions

When using the base versions of the architecture, the
system designer can implement a distinction between the
user tasks and the kernel tasks, without having to execute
page management software. This distinction can take the
form of physical memory protection, accomplished by address decoding, or in other forms. In systems which do not
wish to implement memory protection, and wish to have the
kernel and user tasks operate out of a single unified memory
space, upper address lines can be ignored by the address
decoder, and thus all references will be seen in the lower
gigabyte of the physical address space.

The base versions of the architecture (the IDT79R3051
and IDT79R3052) remove the TLB and institute a fixed
address mapping for the various segments of the virtual
address space. The base processors support distinct kernel
and user mode operation without requiring page management
software, leading to a simpler software model. The memory
mapping used by these devices is illustrated in Figure 4. Note
that the reserved address spaces shown are for compatibility
with future family members; in the current family members,
references to these addresses are translated in the same
fashion as their respective segments, with no traps or exceptions taken.

PHYSICAL

VIRTUAL
Oxffffffff

1MB Kernel Rsvd

Kernel Cached
(kseg2)

Kernel Cacheable
Tasks

1024MB

KernellUser
Cacheable
Tasks

2048MB

Inaccessible

512MB

Kernel Boot
and 1/0

512MB

OxcOOOOOOO

Kernel Uncached
(kseg1)

I---

OxaOOOOOOO

r-

Kernel Cached
(ksegO)

f-

I-- ~

Ox80000000

1MB User Rsvd
User
Cached
(kuseg)
OxOOOOOOOO

I-~

2874 drw 04

Figure 4. Virtual-to-Physical Mapping of Base Architecture Versions

5.3

3

IDT79R3051n9R3052 INTEGRATED RISControliers

Clock Generation Unit
The IDT79R3051 family is driven from a single input clock,
capable of operating in a range of 40%-60% duty cycle. On
chip, the clock generator unit is responsible for managing the
interaction of the CPU core, caches, and bus interface. The
clock generator unit replaces the external delay line required
in IDT79R3000A and IDT79R3001 based applications.
Instruction Cache
The current family includes two different instruction cache
sizes: the IDT79R3051 family (the IDT79R3051 and
IDT79R3051 E) feature 4KB of instruction cache, and the
IDT79R3052 and IDT79R3052E each incorporate 8KB of
Instruction Cache. For all four devices, the instruction cache
is organized as a line size of 16 bytes (four words). This
relatively large cache achieves a hit rate well in excess of 95%
in most applications, and substantially contributes to the
performance inherent in the IDT79R3051 family. The cache is
implemented as a direct mapped cache, and is capable of
caching instructions from anywhere within the 4GB physical
address space. The cache is implemented using physical
addresses (rather than virtual addresses), and thus does not
require flushing on context switch.

COMMERCIAL TEMPERATURE RANGE

of the memory system. The write buffers capture and FIFO
processor address and data information in store operations,
and presents it to the bus interface as write transactions at the
rate the memory system can accommodate.
The IDT79R3051/52 read interface performs both single
word reads and quad word reads. Single word reads work with
a simple handshake, and quad word reads can either utilize
the simple handshake (in lower performance, simple systems) or utilize a tighter timing mode when the memory system
can burst data at the processor clock rate. Thus, the system
designer can choose to utilize page or nibble mode DRAMs
(and possibly use interleaving), if desired, in high-performance systems, or use simpler techniques to reduce complexity.
In order to accommodate slower quad-word reads, the
IDT79R3051 family incorporates a 4-deep read buffer FIFO,
so that the external interface can queue up data within the
processor before releasing it to perform a burst fill of the
internal caches. Depending on the cost vs. performance
tradeoffs appropriate to a given application, the system design
engineer could include true burst support from the DRAM to
provide for high-performance cache miss processing, or utilize the read buffer to process quad word reads from slower
memory systems.

Data Cache

SYSTEM USAGE

All four devices incorporate an on-chip data cache of 2KB,
organized as a line size of 4 bytes (one word). This relatively
large data cache achieves hit rates well in excess of 90% in
most applications, and contributes substantially to the performance inherent in the IDT79R3051 family. As with the instruction cache, the data cache is implemented as a direct mapped
physical address cache. The cache is capable of mapping any
word within the 4GB physical address space.
The data cache is implemented as a write through cache,
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance.

The IDT79R3051 family has been specifically designed to
easily connect to low-cost memory systems. Typical low-cost
memory systems utilize slow EPROMs, DRAMs, and application-specific peripherals. These systems may also typically
contain large, slow Static RAMs, although the IDT79R3051
family has been designed to not specifically require the use of
external SRAMs.
Figure 5 shows a typical system block diagram. Transparent latches are used to de-multiplex the IDT79R3051/52
address and data busses from the AID bus. The data paths
between the memory system elements and the R3051 family
AID bus is managed by simple octal devices. A small set of
simple PALs can be used to control the various data path
elements, and to control the handshake between the memory
devices and the CPU.

Bus Interface Unit

DEVELOPMENT SUPPORT

The IDT79R3051 family uses its large internal caches to
provide the majority of the bandwidth requirements of the
execution engine, and thus can utilize a simple bus interface
connected to slow memory devices.
The IDT79R3051 family bus interface utilizes a 32-bit
address and data bus multiplexed onto a single set of pins.
The bus interface unit also provides an ALE signal to demultiplex the AID bus, and simple handshake signals to
process processor read and write requests. In addition to the
read and write interface, the IDT79R3051 family incorporates
a DMA arbiter, to allow an external master to control the
external bus.
The I DT79R3051 family incorporates a 4-deep write buffer
to decouple the speed of the execution engine from the speed

The IDT79R3051 family is supported by a rich set of
development tools, ranging from system simulation tools
through prom monitor support, logic analysis tools, and subsystem modules.
Figure 7 is an overview of the system development process
typically used when developing IDT79R3051 family-based
applications. The IDT79R3051 family is supported by powerful tools through all phases of project development. These
tools allow timely, parallel development of hardware and
software for IDT79R3051/52 based applications, and include
tools such as:
• A program, Cache-3051, which allows the performance of
an IDT79R3051 family based system to be modeled and
understood without requiring actual hardware.

5.3

4

IDT79R3051n9R3052 INTEGRATED RISControliers

COMMERCIAL TEMPERATURE RANGE

• Sable, an instruction set simulator.

• The lOT Laser Printer System board, which directly drives
a low-cost print engine, and runs Microsoft Truelmage™
Page Description Language on top of PeerlessPage™ Advanced Printer Controller BIOS.

• Optimizing compilers from MIPS, the acknowledged leader
in optimizing compiler technology.
• lOT Cross development tools, available in a variety of
development environments.

• Adobe PostScript'M Page Description Language, ported to
the R3000 instruction set, runs on the IDT79R3051 family.

• The high-performance lOT floating point library software,
which has been integrated into the compiler toolchain to
allow software floating point to replace hardware floating
point without modifying the original source code.

• The lOT Prom Monitor, which implements a full prom
monitor (diagnostics, remote debug support, peek/poke,
etc.).

• The lOT Evaluation Board, which includes RAM, EPROM,
1/0, and the lOT Prom Monitor.

• An In-Circuit Emulator, developed and sold by Embedded
Performance, Inc.

Reset
Clk2xln
Int(5:0)
~

-~

lOT R3051 Family
RISControlier

BrCond(3:0)
BusReq

AD(31:0)

l

Burst!
RdCEn WrNear

Wr

BusGnt

FCT373T

ALE

I-

Addr(3:2)

SysClk

Ack

Rd

DataEn

BErr

~

f

l rt

-

Memory and Interface
Control PALs

II Decode

Address / - -

I

l

t

DRAM Control
PALs

I

~

~

DRAM

I

PAL

,

I

t

EPROM

f---J

~

I/O Devices/
Peripherals

~

System I/O

I

FCT245T

,

2874 drw05

Figure 5. Typical R3051 Family Based System

5.3

5

IDT79R3051n9R3052 INTEGRATED RISControliers

-----I~

COMMERCIAL TEMPERATURE RANGE

Clk2xln
IDT79R3051 Family
RISContro"er

Address/
Data

Control

R3051 Family
Local Bus

DRAM
Controller

PROM

I/O

DRAM

I/O

I--

DRAM

IDT73720
Bus Exchanger

(2)

t

2874 drw 06

Figure 6. R3051 Family Chip Set Based System

5.3

6

IDT79R3051f79R3052 INTEGRATED RISControllers

System
Architecture
Evaluation

COMMERCIAL TEMPERATURE RANGE

System
Development
Phase

System
Integration
and Verification

Software
SABLE Simulator
DBG Debugger
PIXIE Profiler
MIPS Compiler Suite
Stand-Alone Libraries
Floating Point Library
Cross Development Tools
Adobe PostScript™ POL
MicroSoft Truelmage™ POL
Ada

Hardware
Cache-R305x
Hardware Models
General CAD Tools
RISC Sub-systems
Evaluation Board
Laser Printer System

Figure 7. R3051 Family Development Toolchain

5.3

7

IDT79R3051 n9R3052 INTEGRATED RISControllers

COMMERCIAL TEMPERATURE RANGE

PERFORMANCE OVERVIEW

THERMAL CONSIDERATIONS

The IDT79R3051 family achieves a very high level of
performance. This performance is based on:
• An efficient execution engine. The CPU performs ALU
operations and store operations at a single cycle rate, and
has an effective load time of 1.3 cycles, and a branch
execution rate of 1.5 cycles (based on the ability of the
compilers to avoid software interlocks). Thus, the execution
engine achieves over 35MIPS performance when operating
out of cache.

The IDT79R3051 family utilizes special packaging techniques to improve the thermal properties of high-speed processors. Thus, all versions of the IDT79R3051 family are
packaged in cavity-down packaging.
The lowest cost members of the family use a standard
cavity-down, injection molded PLCC package (the "J" package). This package, coupled with the power reduction techniques employed in the design of the IDT79R3051 family,
allows operation at speeds to 25MHz. However, at higher
speeds, additional thermal care must be taken.
For this reason, the IDT79R3051 family is also available in
the MOUAD package (the "MJ" package), which is an allaluminum package with the die attached to a normal copper
lead-frame, mounted to the aluminum casing. The MOUAD
allows for more efficient thermal transfer between the die and
the case of the part due to the heat-spreading effect of the
aluminum. The aluminum offers less internal resistance from
one end of the package to the other, which reduces the
temperature gradient across the package, and, therefore,
presents a greater area for convection and conduction to the
PCB for a given temperature. Even nominal amounts of
airflow will dramatically reduce the junction temperature of the
die, resulting in cooler operation. The MOUAD package is
available at all frequencies, and is pin- and form-compatible
with the PLCC package. Thus, designers can choose to utilize
this package without changing their PCB.
The members of the IDT79R3051 family are guaranteed in
a case temperature range of O°C to +85°C. The type of
package, speed (power) of the device, and airflow conditions
affect the equivalent ambient conditions which meet this
specification.
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(0CA) of the given package. The following equation relates
ambient and case temperature:
TA=Tc-P*0cA
where P is the maximum power consumption at hot temperature, calculated by using the maximum Icc specification for
the device.
Typical values for 0CA at various airflows are shown in
Table 1 for the various packages.

• Large on-chip caches. The IDT79R3051 family contains
caches which are substantially larger than those on the
majority of today's embedded microprocessors. These large
caches minimize the number of bus transactions required,
and allow the R3051 family to achieve actual sustained
performance, very close to its peak execution rate.
• Autonomous multiply and divide operations. The
IDT79R3051 family features an on-chip integer multiplier/
divide unit which is separate from the other ALU. This allows
the IDT79R3051 family to perform multiply or divide operations in parallel with other integer operations, using a single
multiply or divide instruction rather than "step" operations.
• Integrated write buffer. The IDT79R3051 family features a
four-deep write buffer, which captures store target addresses and data at the processor execution rate and retires
it to main memory at the slower main memory access rate.
Use of on-chip write buffers eliminates the need for the
processor to stall when performing store operations.
• Burst read support. The IDT79R3051 family enables the
system designer to utilize page mode or nibble mode RAMs
when performing read operations to minimize the main
memory read penalty and increase the effective cache hit
rates.
These techniques combine to allow the processorto achieve
35MIPS integer performance, and over 64,000 dhrystones at
40MHz without the use of external caches or zero wait-state
memory devices.

SELECTABLE FEATURES
The IDT79R3051 family allows the system designer to
configure some aspects of operation. These aspects are
established when the device is reset and include:
• Big Endian vs. Little Endian operation: The part can be
configured to operate with either byte ordering convention,
and in fact may also be dynamically switched between the
two conventions. This facilitates the porting of applications
from other processor architectures, and also permits intercommunications between various types of processors and
databases.
• Data cache refill of one or four words: The memory
system must be ca'pable of performing 4-word transfers to
satisfy cache misses. This option allows the system designer to choose between one- and four-word refill on data
cache misses, depending on the performance each option
brings to his application.

Airflow (ft/min)
"J" Package

0
29

200
26

400
21

600
18

800
16

"MJ" Package*

22

14

12

11

9

0CA

1000
15
8
2874 tbl 01

Table 1. Thermal Resistance (0CA) at Various Airflows
(*estimated: final values tbd)

5.3

8

1DT19R3051n9R3052 INTEGRATED RISControliers

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION
PIN NAME

UO

AlD(31:0)

1/0

DESCRIPTION
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction
in one phase, and which is used to transmit data between the CPU and external memory resources during
the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:
Address(31 :4):

The high-order address for the transfer is presented on AlD(31 :4).

BE(3:0):

These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are represented on AlD(3:0).

During write cycles, the bus contains the data to be stored and is driven from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in either a single data transaction
or in a burst of four words, and places it into the on-chip read buffer.
Addr(3:2)

0

Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the processor.
Specifically, this two bit bus presents either the address bits for the single word to be transferred (writes
or single datum reads) or functions as a two bit counter starting at '00' for burst read operations.

Diag(1)

0

Diagnostic Pin 1. This output indicates whether the current bus read transaction is due to an onchip cache miss, and also presents part of the miss address. The value output on this pin is time
multiplexed:

Diag(O)

0

Cached:

During the phase in which the AID bus presents address information, this
pin is an active high output which indicates whether the current read is
a result of a cache miss. The value of this pin at this time in other than
read cycles is undefined.

Miss Address (3):

During the remainder of the read operation, this output presents address
bit (3) ofthe address the processor was attempting to reference when the
cache miss occurred. Regardless of whether a cache miss is being
processed, this pin reports the transfer address during this time.

Diagnostic Pin O. This output distinguishes cache misses due to instruction references from those due
to data references, and presents the remaining bit of the miss address. The value output on this pin is
also time multiplexed:

UD:

If the "Cached" Pin indicates a cache miss, then a high on this pin at this
time indicates an instruction reference, and a low indicates a data
reference. If the read is not due to a cache miss but rather an uncached
reference, then this pin is undefined during this phase.

Miss Address (2):

During the remainderof the read operation, this output presents address
bit (2) ofthe address the processor was attempting to reference when the
cache miss occurred. Regardless of whether a cache miss is being
processed, this pin reports the transfer address during this time.

ALE

0

Address Latch Enable: Used to indicate that the AID bus contains valid address information for the bus
transaction. This signal is used by external logic to capture the address for the transfer, typically using
transparent latches.

DataEn

0

External Data Enable: This Signal indicates that the AID bus is no longer being driven by the processor
during read cycles, and thus the external memory system may enable the drivers of the memory system
onto this bus without having a bus conflict occur. During write cycles, or when no bus transaction is
occurring, this signal is negated, thus disabling the external memory drivers.
2874 Ibl 02

5.3

9

IDT79R3051n9R3052 INTEGRATED RISControliers

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (Continued):
PIN NAME
Burst!
WrNear

I/O

0

DESCRIPTION
Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current bus read
is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles
due to cache misses; it is asserted for alii-Cache miss read cycles, and for D-Cache miss read cycles
if selected at device reset time.
On write transactions, the WrNear output tells the external memory system that the bus interface unit
is performing back-to-back write transactions to an address within the same 256 word page as the prior
write transaction. This signal is useful in memory systems which employ page mode or static column
DRAMs, and allows near writes to be retired quickly.

Rd

0

Read: An output which indicates that the current bus transaction is a read.

Wr

0

Write: An output which indicates that the current bus transaction is a write.

Ack

I

Acknowledge: An input which indicates to the device that the memory system has sufficiently
processed the bus transaction, and that the CPU may either terminate the write cycle or process the read
data from this read transfer.

RdCEn

I

Read Buffer Clock Enable: An input which indicates to the device that the memory system has placed
valid data on the AID bus, and that the processor may move the data into the on-chip Read Buffer.

SysClk

0

System Reference Clock: An output from the CPU which reflects the timing of the internal processor
"Sys" clock. This clock is used to control state transitions in the read buffer, write buffer, memory
controller, and bus interface unit.

BusReq

I

DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus interface
signals so that they may be driven by an external master.

BusGnt

0

DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has been
detected, and that the bus is relinquished to the external master.

SBrCond(3:2)
BrCond(1 :0)

I

Branch Condition Port: These external signals are internally connected to the CPU signals
CpCond(3:0). These signals can be used by the branch on co-processor condition instructions as input
ports. There are two types of Branch Condition inputs: the SBrCond inputs have special internal logic
to synchronize the inputs, and thus may be driven by asynchronous agents. The direct Branch Condition
inputs must be driven synchronously.

BErr

I

Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error.
This signal is only sampled during read and write operations. If the bus transaction is a read operation,
then the CPU will take a bus error exception.

Int(5:3)
Slnt(2:0)

I

Processor Interrupt: During normal operation, these signals are logically the same as the Int(5:0)
signals of the R3000. During processor reset, these signals perform mode initialization of the CPU, but
in a different (simpler) fashion than the interrupt signals of the R3000.
There are two types of interrupt inputs: the Sint inputs are internally synchronized by the processor, and
may be driven by an asynchronous external agent. The direct interrupt inputs are not internally
synchronized, and thus must be externally synchronized to the CPU. The direct interrupt inputs have
one cycle lower latency than the synchronized interrupts.

Clk2xln

I

Master Clock Input: This is a double frequency input used to control the timing of the CPU.

Reset

I

Master Processor Reset: This signal initializes the CPU. Mode selection is performed during the last
cycle of Reset.

Rsvd(4:0)

I/O

Reserved: These five signal pins are reserved for testing and for future revisions of this device. Users
must not connect these pins.
2874 tbl 03

5.3

10

IDT79R3051n9R3052 INTEGRATED RISControliers

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS(1, 3)
Symbol

Rating

Commercial

Unit

VTERM

Terminal Voltage
with Respect
toGND

-0.5 to +7.0

V

Te

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Temperature
Vee
GND
Commercial

Operating Case
Temperature

o to +85

°C

TBIAS

Temperature
Under Bias

-55 to +125

°C

TSTG

Storage
Temperature

-55 to +125

°C

VIN

Input Voltage

-0.5 to +7.0

V

OV

O°C to +85°C
(Case)

5.0±5%
2874 tbl 06

OUTPUT LOADING FOR AC TESTING

NOTES:
2874tbl04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VIN minimum -3.0V for pulse width less than 15ns.
VIN should not exceed Vce +0.5V.
3. Not more than one output should be shorted at a time. Duration ofthe short
should not exceed 30 seconds.

VREF
+1.5V

To Device
Under Test

=

2874 drw 08

AC TEST CONDITIONS
Symbol

Parameter

Min.

Unit

Max.

VIH

Input HIGH Voltage

3.0

-

V

VIL

Input LOW Voltage

-

0

V

VIHS

Input HIGH Voltage

3.5

-

V

VILS

Input LOW Voltage

-

0

V
2874 tbl 05

DC ELECTRICAL CHARACTERISTICS (Te =O°C to +85°C, Vee =+5.0V ±5%)
25M Hz

20MHz
Min.

Max.

Min.

Vee = Min., 10H = -4mA

3.5

-

3.5

Vee = Min., 10L = 4mA

-

0.4

-

Symbol

Parameter

Test Conditions

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

33.33MHz

40MHz

Min.

Max.

Min.

-

3.5

-

3.5

-

V

0.4

-

0.4

-

0.4

V

Max.

Max.

Unit

VIH

Input HIGH Voltage(3)

-

2.0

-

2.0

-

2.0

-

2.0

-

V

VIL

Input LOW Voltage(1)

-

0.8

-

0.8

-

0.8

-

0.8

V

VIHS

Input HIGH Voltage(2,3)

-

3.0

-

3.0

-

3.0

-

3.0

-

V

VILS

Input LOW Voltage(1.2)

0.4

-

0.4

V

10

10

-

10

pF

COUT

Output Capaeitarice(4)

10

-

10

-

0.4

Input Capacitance(4)

-

0.4

CIN

-

10

10

pF

350

-

400

-

450

-

500

mA

100

-

100

-

100

~A

~A

-

10

lee

Operating Current

Vee = 5V, Te = 25°C

IIH

Input HIGH Leakage

VIH = Vee

IlL

Input LOW Leakage

VIL= GND

-100

-

-100

-

-100

-

-100

-

loz

Output Tri-state Leakage

VOH = 2.4V, VOL = 0.5V

-100

100

-100

100

-100

100

-100

100

100

NOTES:
1. VIL Min. =-3.0V for pulse width less than 15ns. VIL should not fall below -O.5V for larger periods.
2. VIHS and VILS apply to elk2xln and Reset.
3. VIH should not be held above Vee + 0.5V.
4. Guaranteed by design.

5.3

~A
2874 tbl 07

11

IDT79R3051n9R3052 INTEGRATED RISControllers

COMMER~ALTEMPERATURERANGE

AC ELECTRICAL CHARACTERISTICS (1,2,3) (Tc = O°C to +85°C , VCC = +5 OV +5%)
20MHz
Symbol

Signals

Description

Min.

Max.

25MHz
Min.

Max.

33.33MHz
Min.

Max.

40MHz
Min.

Max.

Unit

-

ns

t1

BusReq. Ack, BusError.
RdCEn,

Set-up to SysClk rising

6

-

5

-

4

-

3

t1a

AID

Set-up to SysClk falling

7

-

6

-

ns

Hold from SysClk rising

4

-

4

3

-

4.5

BusReq, Ack, BusError,

-

5

t2

3

-

ns

1

-

1

-

RdCEn,
t2a

AID

Hold from SysClk falling

2

-

2

-

t3

AID, Addr, DiaLALE, Wr
BurstlWrNear, Ad, DataEn

Tri-state from SysClk rising

-

10

-

10

-

10

-

10

ns

t4

AID, Addr, Diag, ALE, Wr
BurstIWrNear, Ad, DataEn

Driven from SysClk falling

-

10

-

10

-

10

-

10

ns

t5

BusGnt

Asserted from sysClk rising

-

7

-

5

ns

Negated from SVsClk falling

8

-

7

6

-

5

ns

t7

Wr, Rd, BurstlWrNear, AID

Valid from SysClk rising

5

-

5

4

-

3.5

ns

t8

ALE

Asserted from SVsClk rising

-

-

6

BusGnt

-

8

t6

4

-

4

3

ns

ALE

Negated from SVsClk falling

-

4

-

4

3

-

3

t9

-

3

ns

t10

AID

Hold from ALE negated

2

-

2

-

1.5

-

1.5

-

ns

t11

DataEn

Asserted from sysClk falling

-

15

-

15

-

13

-

12

ns

t12

DataEn

Asserted from AID tri-state(4)

0

0

-

ns

Driven from sysClk rising(4)

0

-

0

AID

-

0

t14

-

0

-

ns

t15

Wr, Rd, DataEn, BurstlWrNear Negated from SVsClk falling

-

7

t16

Addr(3:2)

-

6

-

Valid from sysClk

0

0

5

-

4

ns

6

-

5

-

4.5

ns

6

11

-

10

-

9

ns

10

-

9

ns

11

-

10

-

8

12

-

9

ns

10

-

8

6.5

-

8

6.5

5.6

-

ns

10

-

5.6

Pulse Width LOW

-

Clk2xln

Clock Period

25

20

250

15

250

12.5

250

Reset

Pulse Width from Vcc valid

200

-

200

t24

Reset

Minimum Pulse Width

32

-

t25

Reset

Set-up to SysClk falling

6

t26

Int

Mode set-up to Reset rising

6
2.5

t17

Diag

Valid from SVsClk

-

12

t18

AID

Tri-state from SysClk falling

10

t19

AID

sysClk falling to data out

-

t20

Clk2xln

Pulse Width HIGH

t21

Clk2xln

t22
t23

250

200

-

200

32

-

32

-

32

5

4

-

3

4

-

3

2.5

-

2.5

-

2.5

5

-

4

3

3

2

2

-

ns

5

-

-

-

4

-

3

-

ns

t27

Int

Mode hold from Reset rising

128

Slnt, SBrCond

Set-up to SVsClk falling

6

t29

Slnt, SBrCond

Hold from sysClk falling

3

t30

Set-up to SysClk falling

6

t31

int, BrCond
int, BrCond

Hold from sysClk falling

3

-

3

-

2

-

2

tsys

SysClk

Pulse Width

2*t22

2*t22

2*t22

2*t22

2*t22

2*t22

2*t22

t32

SysClk

Clock HIGH Time

t22-2 t22 +2 t22-2 t22 + 2 t22-1

t22 + 1 t22-1 t22 + 1

t33

sysClk

Clock LOW Time

t22-2 t22 +2 t22-2 t22 + 2 t22-1

t22+ 1 t22 -1 t22 + 1

tderate

All outputs

Timing deration for loading
over 25pf{4, 5)

0.5

ns

-

-

-

ns

5

-

0.5

-

0.5

-

~s

tsys
ns
ns
ns
ns

ns

2*t22

0.5

ns
ns

nsl
25pF

NOTES:
2874tbl08
1. All timings referenced to 1.5V, with a rise and fall time of less than 2.5ns.
2. All outputs tested with 25pF loading.
3. The AC values listed here reference timing diagrams contained in the R3051 Family Hardware User's Manual.
4. Guaranteed by design.
5. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.

5.3

12

IDT7SR3051nSR3052 INTEGRATED RISControllers

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS
C;;

0'
('I)

en
co
C\J
C\J

r:::C\J

0' 0' 0' 0' 0'
~

~

~

~

~

 >

C\J

~
C\J

e;;- N
N
C\J
C\J

0' 0' 0' 0' 0' 0'

~

~

~

~

~

~

t)
t)

>

C/l
C/l

>

0'
en
,....
C\J

co

~

~

r:::- 

t)
t)

>

I~ I~

UJ

--I

«

0' ,....

0;

co

(5

0;

co

(5

C/l
C/l

>

t)
t)

>

g
-0

"C

§:

(ij
Q)

-u z

"C

« «

~~

:J
Cl)

2874 drw 09

84-Pin PLCC/MQUAD
Top View

NOTE:
Reserved Pins must not be connected.

5.3

13

1DT79R3051n9R3052 INTEGRATED RISControllers

Clk2xin

SysClk

!

COMMERCIAL TEMPERATURE RANGE

t22
t20

t

~

t21

t32
2874 drw 11

Figure 8. R3051 Family Clocking

Vee
Clkln

Reset

t23

---------------------------------------;----------------~~----------~
2874 drw 12

Figure 9. Power-On Reset Sequence

SysClk

Reset

}

--;f-c-J/:..-.-----------------{

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _t_2_4

'''''M''

Figure 10. Warm Reset Sequence

~

SysClk

Reset

'7

~

~

t25

Slnt(n),

~

Int(n)

t26

*

I t27

2874 drw 14

Figure 11. Mode Selection and Negation of Reset

5.3

14

IDT79R3051n9R3052 INTEGRATED RISControliers

Run/
Fixup/
Stall

Stall

Stall

COMMERCIAL TEMPERATURE RANGE

Stall

Stall

Fixup

Stall

PhiClk

SysClk

Rd

AlD(31:0)

Addr(3:2)

ALE

DataEn

Burst

RdCEn

ACK

Diag(1)

Miss Address(3)

Diag(O)

Miss Address(2)

Start
Read

Turn
Bus

ACK?

ACK?

ACKI
RdCen

Sample
Data

End
Read

2874 drw 15

Figure 12. Single Datum Read in R3051 Family

5.3

15

IDT79R3051n9R3052 INTEGRATED RISControlJers

Run/
Fixup/
Stall

Stall

Stall

COMMERCIAL TEMPERATURE RANGE

Stall

Refill/
Stream/
Fixup

Refill/
Stream/
Fixup

Refill/
Stream/
Fixup

Refill/
Stream/
Fixup

Word 0

Word 1

Word 2

Word 3

PhiClk

SysClk

Rd

ND(31:0)

Addr(3:2)

ALE

DataEn

Burst

RdCEn

ACK

Diag(1)

Diag(O)
Sturt
Read

Turn
Bus

ACKI Sample RdCEn
RdCen
Data

Sample RdCEn Sample RdCEn Sample
New
Data
Data
Data Transaction
2874 drw 16

Figure 13. R3051 Family Burst Read

5.3

16

IDT79R30S1n9R30S21NTEGRATED RISControliers

COMMERCIAL TEMPERATURE RANGE

Stall

Stall

Stall

Stall

PhiClk

SysClk

Rd

ND(31:0)

Addr(3:2)

ALE

DataEn

Burst

RdCEn

ACK
RdCEn

Sample
Data

RdCEn

Sample
Data

RdCEn

Sample
Data

2874 drw 17

Figure 14 (a). Start of Throttled Quad Read

5.3

17

IDT79R3051 n9R3052 INTEGRATED RISControliers

Stall

COMMERCIAL TEMPERATURE RANGE

Refill/
Stream/
Fixup

Refill/
Stream/
Fixup

Refill/
Stream/
Fixup

Refill/
Stream/
Fixup

Word 0

Word 1

Word 2

Word 3

PhiClk

SysClk

Rd

ND(31:0)

Addr(3:2)

ALE

DataEn

Burst

RdCEn

ACK

ACK

RdCEn

Sample
Data

RdCEn

Sample
Data

New
Transaction

2874 drw 18

Figure 14 (b). End ofThrottled Quad Read

5.3

18

IDT79R3051n9R3052 INTEGRATED RISControllers

COMMERCIAL TEMPERATURE RANGE

Wr

AlD(31:0)

Addr(3:2) _ _ _ _--+....J ' - - . , - - , r - - - - r - - - - - - y - - - - - - - y - - - - y - - - ( ~_ _ _ _ _ __

ALE

-----t--J

Start
Write

Data
Out

ACK

New
Transfer

ACK

2874 drw 19

Figure 15. R3051 Family Write Cycle

./~

SysClk

BusReq

~
t1

~

./~

"'-

M

t5

I

t3~

BusGnt

AlD(31 :0)

"/

Addr(3:2)

"

./

"

Diag(1:0)

./

Rd

./

........

Wr

./

..........

ALE

./

Burst!
WrNear

./

...........
2874 drw 20

Figure 16. Request and Relinquish of R3051 Family Bus to External Master

5.3

19

IDT79R3051n9R3052 INTEGRATED RISControllers

~

COMMERCIAL TEMPERATURE RANGE

~

SysClk

?

BusReq

~11 ~

K

./

~

I

I

t6~

BusGnt

t4

<
<

AlD(31:0)

Addr(3:2)

.........

Diag(1:0)

<

..........

Rd

Wr

'"
'"
'"
/

ALE

BursU
WrNear

Figure 17. R3051 Family Regaining Bus Mastership

5.3

2874 drw 21

20

IDT79R3051n9R3052 INTEGRATED RISControliers

COMMERCIAL TEMPERATURE RANGE

Run Cycle

Exception Vector

Phi

t28

t29

2874 drw 22

Figure 18. Synchronized Interrupt Input Timing

Run Cycle

Exception Vector

Phi

t30

2874 drw 23

t31

Figure 19. Direct Interrupt Input Timing

Run Cycle
Phi /

V

"'-

~

BCzT/F Instruction

Capture BrCond

/

/

"'-

/

I"-

r

"-

I
c

SBrCond(n)

1-1t28 t29

2874 drw 24

Figure 20. Synchronized Branch Condition Input Timing

Run Cycle
Phi /

-----.....
BrCond(n)

V

/

/

BCzT/F Instruction

Capture BrCond

/

I"

/

r

IIX
~It30

t31

2874 drw 25

Figure 21. Direct Branch Condition Input Timing

5.3

21

IDT79R3051179R3052 INTEGRATED RISControliers

COMMERCIAL TEMPERATURE RANGE

84 LEAD PLCC/MQUAD(7) (SQUARE)
~-----D-----~

45° x .04

--++--+---t-t8

SEATING PLANE
2874 drw 27

NOTES:
1. All dimensions are in inches, unless otherwise noted.
2. BSC-Basic lead Spacing between Centers.
3. 0 & E do not include mold flash or protutions.
4. Formed leads shall be planar with respect to one another and within .004" at the seating plane.
5. NO & NE represent the number of leads in the 0 & E directions respectively.
6. 01 & E1 should be measured from the bottom of the package.
7. MQUAO is pin & form compatible with PLCC.

DWG#

J84-1

# of Leads

84

Symbol

MJ84-1
84

Min.

Max.

Min.

Max.

A

165

.180

165

.180

A1

.095

.115

.094

.114
.032

8

.026

.032

.026

b1

.013

.021

.013

.021

e

.020

.040

.020

.040

e1

.008

.012

.008

.012

D

1.185

1.195

1.185

1.195

D1

1.150

1.156

1.140

1.150

D2IE2

1.090

1.130

1.090

1.130

D3/E3

1.000 REF

1.000 REF

E

1.185

1.195

1.185

1.195

E1

1.150

1.156

1.140

1.150

e

.050 sse

.050 sse

ND/NE

21

21

5.3

22

IDT79R3051n9R3052 INTEGRATED RISControllers

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

xxxxx

IDT--Device Type

xx

x

Speed Package

x
Process/
Temp. Range

~Blank
I

L--------I

1

L -_ _ _ _ _ _ _ _ _-j

'"--------------f

Commercial Temperature Range

'J'
'MJ'

84-Pin PLCC
84-Pin MQUAD

'20'
'25'
'33'
'40'

20.0 MHz
25.0 MHz
33.33 MHz
40.0 MHz

79R3051
79R3051E
79R3052
79R3052E

4kB
4kB
8kB
8kB

Instruction Cache,
Instruction Cache,
Instruction Cache,
Instruction Cache,

No TLB
With TLB
No TLB
With TLB
2874 drw28

VALID COMBINATIONS
lOT 79R3051 - 20, 25
79R3051 E - 20, 25
79R3052 - 20, 25
79R3052E - 20, 25
79R3051 - 33, 40
79R3051 E - 33,40
79R3052 - 33,40
79R3052E - 33, 40

J
J
J
J

Packages
Packages
Packages
Packages

MJ
MJ
MJ
MJ

Only
Only
Only
Only

Packages
Packages
Packages
Packages

Only
Only
Only
Only

5.3

23

g

~

IDT79R3071
IDT79R3071 E

IDT79R3071 ™
RISControlier™

Integrated Device Technology. Inc.

FEATURES

• Large on-chip caches with user configurability
- 16kB Instruction Cache, 4kB Data Cache
- Dynamically configurable to 8kB Instruction
Cache, 8kB Data Cache
- Parity protection over data and tag fields
• Low cost 84-pin packaging
• Multiplexed bus interface with support for low-cost, lowspeed memory systems with a high-speed CPU
• On-chip 4-deep write buffer eliminates memory write
stalls
• On-chip 4-deep read buffer supports burst or simple
block reads
• On-chip DMA arbiter
• Hardware-based Cache Coherency Support
• Programmable power reduction mode
• Bus Interface operates only at half-processor frequency

• Instruction set compatible with IDT79R3000A, R3051™,
and R3500 RISC CPUs
• High level of integration minimizes system cost
- R3000A Compatible CPU
- Optional R3000A compatible MMU
- Large Instruction Cache
- Large Data Cache
- ReadlWrite Buffers
• 35VUPS at 40MHz
- 320MB/sec on-chip bandwidth
- 160MB/sec bus bandwidth
• Flexible bus interface allows simple, low-cost designs
• 1x clock input
• 33- through 50MHz operation
• 50MHz at 1x clock input and 1/2 bus frequency
• Superset pin- and software-compatible with R3041 TM,
R3051, R3052™, and R3081™

..

R3071 BLOCK DIAGRAM
Clkln

BrCond(3'2 0)

Clock
Generator
UniU
Clock Doubler

I

Master Pipeline Control

System Control
Coprocessor
(CPO)

Integer
CPU Core

Exception/Control
Reqisters
Memory Management
REiqisters

Genral Re ;sters
32 x 32
ALU

Translation
Lookaside Buffer
(64 entries)

MulUDiv Unit

Int(5:0)

t

1

Shifter
Address Adder
PC Control

Physical Address Bus
3~~

~

-

t

t
Configurable
Instruction
Cache
(16kB/8kB)

Parity
Generator
4-deep
Read
Buffer

I

Virtual Address

Configurable
Data
Cache
(4kB/8kB)
Data Bus

3~,

~

R3051 Superset Bus Interface Unit
4-deep
Write
Buffer

I
t t

DMA
Arbiter

DMA
Ctrl

Address/
Data

I

BIU
Control

Rd/Wr
Ctrl

Coherency
Logic

~

t

SysClk Invalidate
Control

3045 drw 01

The IDT logo is a registered trademark, and RISController, R3041, R3051, R3052, R3071, R3081, R4400, R4600, IDT/sim, and IDT/kit are trademarks of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
©1995 Integrated Device Technology, Inc.

SEPTEMBER 1995
5.4

DSC-9078/1

1

1DT79R3071 RISController

COMMERCIAL TEMPERATURE RANGE

INTRODUCTION

An overview of this device, and quantitative electrical
parameters and mechanical data, is found in this data sheet;
consult the R3071 Family Hardware User's Guide for a
complete description of this processor.

The lOT R3051 family is a series of high-performance 32bit microprocessors featuring a high-level of integration, which
is targeted to high-performance but cost-sensitive processing
applications. The R3051 family is designed to bring the highperformance inherent in the MIPS RISC architecture into
low-cost, simplified, power-sensitive applications.
Thus, functional units have been integrated onto the CPU
core in order to reduce the total system cost, rather than to
increase the inherent performance of the integer engine.
Nevertheless, the R3051 family is able to offer 35VUPS
performance at 40MHz without requiring external SRAM or
caches.
The R3071 extends the capabilities of the R3051 family, by
integrating additional resources into the same pin-out. The
R3071 thus extends the range of applications addressed by
the R3051 family, and allows designers to implement a single,
base system and software set capable of accepting a wide
variety of CPUs, according to the price/performance goals of
the end system.

DEVICE OVERVIEW
As part of the R3051 family, the R3071 extends the offering
of a wide range of functionality in a compatible interface. The
R3051 family allows the system designer to implement a
single base system, and utilize interface-compatible processors
of various complexity to achieve the price-performance goals
of the particular end system.
Differences among the various family members pertain to
the on-chip resources ofthe processor. Currentfamily members
are shown in Table 1, below.
Figure 1 shows a block-level representation of the functional
units within the R3071 E. The R3071 E could be viewed as the
embodiment of a discrete solution built around the R3000A
and R3010A. However, by integrating this functionality on a
single chip, dramatic cost and power reductions are achieved.

Device
Name

Instruction
Cache

Data
Cache

MMU
Option

R3041

2kB

512B

No

Software

Programmable Options
Variable Port width interface

R3051

4kB

2kB

"E" version

Software

32-bit mux'ed

R3052

8kB

2kB

"E" version

Software

32-bit mux'ed

R3071

16kB

4kB
or8kB

"E" version
or8kB

Software

1/2 frequency bus only

R3081

16kB
or8kB

4kB
or8kB

"E" version

On-chip
hardware

1/2 frequency bus

FPA

Bus
Options

3045 tbl 01

Table 1. R3051 Family Members

CPU Core
The CPU core is a full 32-bit RISC integer execution
engine, capable of sustaining close to single cycle execution.
The CPU core contains a five stage pipeline, and 32 orthogonal
32-bit registers. The R3071 uses the same basic integer
execution core as the entire R3051 family, which is the
R3000A implementation of the MIPS instruction set. Thus, the
R3071 family is binary compatible with the R3051, R3052,
R3000A, R3001, and R3500 CPUs. In addition, the R4000
and Orion represent an upwardly software compatible migration
path to still higher levels of performance.
The execution engine in the R3071 uses a five-stage
pipeline to achieve near single-cycle instruction execution
rates. A new instruction can be initiated in each clock cycle;
the execution engine actually processes five instructions
concurrently (in various pipeline stages). Figure 2 shows the
concurrency achieved in the R3071 execution pipeline.

1#1
L...-_-'--_....L-_--'-_-+.".,-~

Current CPU
Cycle

3045 drw 02

Figure 2. R3071 5-Stage Pipeline

5.4

2

IDT79R3071 RISController

COMMERCIAL TEMPERATURE RANGE

VIRTUAL

PHYSICAL

Oxffffffff

Kernel Mapped
(kseg2)

An

OxcOOOOOOO

Kernel Uncached
(kseg1 )
OxaOOOOOOO

Physical
Memory

3548 MB

Memory

512 MB

Kernel Cached
(ksegO)
Ox80000000

User Mapped
Cacheable
(kuseg)
OxOOOOOOOO

3045 drw 03

Figure 3. Virtual to Physical Mapping of Extended Architecture Versions

The Extended architecture versions of the R3051 family
(the R3051 E, R3052E, and R3071 E) allow the system designer
to implement kernel software which dynamically manages
User task utilization of system resources, and also allows the
Kernel to protect certain resources from User tasks. These
capabilities are important in general computing applications
such as ARC computers, and are also important in a variety of
embedded applications, from process control (where protection
may be important) to X-Window display systems (where
virtual memory management can be used). The MMU can
also be used to simplify system debug.
R3051 family base versions (the R3051 , R3052, and R3071)
remove the TLB and institute a fixed address mapping for the
various segments of the virtual address space. These devices
still support distinct kernel and user mode operation, but do
not require page management software, leading to a simpler
software model. The memory mapping used by these devices
is shown in Figure 4. Note that the reserved spaces are for
compatiblity with future family members, which may map on-

System Control Co-Processor
The R3071 family also integrates the System Control Coprocessor, CPO, on-chip. CPO manages both the exception
handling capability of the R3071 , as well as the virtual-tophysical address mapping.
As with the R3051 and R3052, the R3071 offers two
versions of memory management and virtual-to-physical
address mapping: the extended architecture versions, the
R3051 E, R3052E, and R3071 E, incorporate the same MMU
as the R3000A. These versions contain a fully associative 64entry TLB which maps 4kB virtual pages into the physical
address space. The virtual to physical mapping thus includes
kernel segments which are hard-mapped to physical
addresses, and kernel and user segments which are mapped
page by page by the TLB into anywhere in the 4GB physical
address space. In this TLB, 8 pages can be "locked" by the
kernel to insure deterministic response in real-time applications.
Figure 3 illustrates the virtual to physical mapping found in the
R3071E.

PHYSICAL

VIRTUAL
Oxffffffff

1MB Kernel Rsvd
Kernel Cached
(kseg2)

Kernel Cacheable
Tasks

1024 MB

Kernel/User
Cacheable
Tasks

2048 MB

Inaccessible

512 MB

Kernel Boot
and 1/0

512 MB

OxcOOOOOOO

Kernel Uncached
(kseg1 )

f---

OxaOOOOOOO

Kernel Cached
(ksegO)

f-

Ox80000000
<

<

1M.BUser Rsv~,'
User
Cached
(kuseg)

OxOOOOOOOO

r-

.'
~

L-.,

3045 drw 04

Figure 4. Virtual to Physical Mapping of Base Architecture Versions

5.4

3

IDT79R3071 RISController

chip resources to these addresses. References to these
addresses in the R3071 will be translated in the same fashion
as the rest of their respective segments, with no traps or
exceptions signalled.
When using the base versions of the architecture, the
system designer can implement a distinction between the
user tasks and the kernel tasks, without having to implement
page management software. This distinction can be
implemented by decoding the output physical address. In
systems which do not need memory protection, and wish to
have the kernel and user tasks operate out of the same
memory space, high-order address lines can be ignored by
the address decoder, and thus all references will be seen in
the lower gigabyte of the physical address space.
Clock Generator Unit
The R3071 is driven from a single input clock at the
processor rated speed. On-chip, the clock generator unit is
responsible for managing the interaction of the CPU core,
caches, and bus interface. The R3071 includes an on-chip
clock doubler to provide higher frequency signals to the
internal execution core. The clock generator unit replaces the
external delay line required in R3000A based applications.
Instruction Cache
The R3071 implements a 16kB Instruction Cache. The
system may choose to repartition the on-chip caches, so that
the instruction cache is reduced to 8kB but the data cache is
increased to 8kB. The instruction cache is organized with a
line size of 16 bytes (four entries). This large cache achieves
hit rates in excess of 98% in most applications, and substantially
contributes to the performance inherent in the R3071. The
cache is implemented as a direct mapped cache, and is
capable of caching instructions from anywhere within the 4GB
physical address space. The cache is implemented using
physical addresses (rather than virtual addresses), and thus
does not require flushing on context switch.
The instruction cache is parity protected over the instruction
word and tag fields. Parity is generated by the read buffer
during cache refill; during cache references, the parity is
checked, and in the case of a parity error, a cache miss is
processed.
Data Cache
The R3071 incorporates an on-chip data cache of 4kB,
organized as a line size of 4 bytes (one word). The R3071
allows the system to reconfigure the on-chip cache from the
default 16kB I-Cache/4kB D-Cache to 8kB of Instruction and
8kB of Data caches.
The relatively large data cache achieves hit rates in excess
of 95% in most applications, and contributes substantially to
the performance inherent in the R3071. Aswith the instruction
cache, the data cache is implemented as a direct mapped
physical address cache. The cache is capable of mapping any
word within the 4GB physical address space.
The data cache is implemented as a write-through cache,
to insure that main memory is always consistent with the

COMMERCIAL TEMPERATURE RANGE

internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance. Further, support has been provided to allow
hardware based data cache coherency in a multi-master
environment, such as one utilizing DMA from I/O to memory.
The data cache is parity protected over the data and tag
fields. Parity is generated by the read buffer during cache refill;
during cache references, the parity is checked, and in the case
of a parity error, a cache miss is processed.
Bus Interface Unit
The R3071 uses its large internal caches to provide the
majority of the bandwidth requirements of the execution
engine, and thus can utilize a simple bus interface connected
to slower memory devices. Alternately, a high-performance,
low-cost secondary cache can be implemented, allowing the
processor to increase performance in systems where bus
bandwidth is a performance limitation.
As partofthe R3051 family, the R3071 bus interface utilizes
a 32-bit address and data bus multiplexed onto a single set of
pins. The bus interface unit also provides an ALE (Address
Latch Enable) output signal to de-multiplex the AID bus, and
simple handshake signals to process CPU read and write
requests. In addition to the read and write interface, the R3051
family incorporates a DMA arbiter, to allow an external master
to control the external bus.
The R3071 also supports hardware based cache coherency
during DMA writes. The R3071 can invalidate a specified line
of data cache, or in fact can perform burst invalidations during
burst DMA writes.
The R3071 incorporates a 4-deep write buffer to decouple
the speed of the execution engine from the speed of the
memory system. The write buffers capture and FI FO processor
address and data information in store operations, and present
it to the bus interface as write transactions at the rate the
memory system can accommodate.
The R3071 read interface performs both single datum
reads and quad word reads. Single reads work with a simple
handshake, and quad word reads can either utilize the simple
handshake (in lower performance, simple systems) or utilize
a tighter timing mode when the memory system can burst data
at the processor clock rate. Thus, the system designer can
choose to utilize page or nibble mode DRAMs (and possibly
use interleaving, if desired, in high-performance systems), or
use simpler techniques to reduce complexity.
In order to accommodate slower quad word reads, the
R3071 incorporates a 4-deep read buffer FIFO, so that the
external interface can queue up data within the processor
before releasing it to perform a burst fill of the internal caches.
The R3071 is R3051 superset compatible in its bus interface.
Specifically, the R3071 has additional support to simplify the
design of very high frequency systems. This support includes
the ability to run the bus interface at one-half the processor
execution rate, as well as the ability to slow the transitions

5.4

4

IDT79R3071 RISControl/er

COMMERCIAL TEMPERATURE RANGE

between reads and writes to provide extra buffer disable time
forthe memory interface. However, it is still possible to design
a system which, with no modification to the PC Board or
software, can accept either an R3051 , R3052, or R3071.

Figure 5 shows a typical system implementation.
Transparent latches are used to de-multiplex the R3071
address and data busses from the AID bus. The data paths
between the memory system elements and the AID bus is
managed by simple octal devices. A small set of simple PALs
is used to control the various data path elements, and to
control the handshake between the memory devices and the
CPU.
Depending on the cost vs. performance tradeoffs appropriate
to a given application, the system design engineer could
include true burst support from the DRAM to provide for highperformance cache miss processing, or utilize a simpler,
lower performance memory system to reduce cost and simplify
the design. Similarly, the system designer could choose to
implement techniques, such as external secondary cache, or
DMA, to further improve system performance.

SYSTEM USAGE
The lOT R3051 family has been specifically designed to
allow a wide variety of memory systems. Low-cost systems
can use slow speed memories and simple controllers, while
other designers may choose to incorporate higher frequencies,
faster memories, and techniques such as DMA to achieve
maximum performance. The R3071 includes specific support
for high performance systems, including signals necessary to
implement external secondary caches, and the ability to
perform hardware based cache coherency in multi-master
systems.

- - - - . I Clkln

IDT R3071
RISController

Addressl
Data

Control

R3051
Local Bus

-DRAM

110 Controller

PROM

110

Controller

DRAM

110

DRAM

I

IDT73720
Bus Exchanger

t

3045 drw 05

Figure 5. R3071-Based System

5.4

5

IDT79R3071 RISController

COMMERCIAL TEMPERATURE RANGE

DEVELOPMENT SUPPORT

•
•

The lOT R3051 family is supported by a rich set of
development tools, ranging from system simulation tools
through PROM monitor and debug support, applications
software and utility libraries, logic analysis tools, sUb-system
modules, and shrink wrap operating systems. The R3071 ,
which is pin and software compatible with the R3051, can
directly utilize these existing tools to reduce time to market.
Figure 6 is an overview of the system development process
typically used when developing R3051 family applications.
The R3051 family is supported in all phases of project
development. These tools allow timely, parallel development
of hardware and software for R3051 family applications, and
include tools such as:
• A program, Cache-R3051, which allows the performance
of an R3051 family system to be modeled and understood
without requiring actual hardware.

System Architecture
Evaluation

•
•

•
•
•
•

Sable, an instruction set simulator.
Optimizing compilers from MIPS, the acknowledgedleader
in optimizing compiler technology.
Cross development tools, available in a variety of
development environments.
The high-performance lOT floating point library software,
including transcendental functions and IEEE compliant
exception handlers.
The lOT Evaluation Board, which includes RAM, EPROM,
1/0, and the lOT PROM Monitor.
Adobe PostScript'M Page Description Language, ported to
the lOT 79S389 Centaurus reference board.
IDT/sim'M, which implements a full prom monitor
(diagnostics, remote debug support, peek/poke, etc.).
IDT/kit'M, which implements a run-time support package for
R3051 family systems.

System Development
Phase

System Integration
and Verfification

Software

Cache-3051
SPP
Benchmarks
Evaluation Board
Laser Printer System
X-Terminal System

SABLE Simulator
DBG Debugger
PIXIE Profiler
MIPS Compiler Suite
Stand-Alone Libraries
Floating Point Library
Cross Development Tools
Adobe PostScript POL
MicroSoft Truelmage POL
PeerlessPage Printer as
X-Server
Hardware

Logic Analysis
Diagnostics
IDT/sim
lOT/kit
In-Circuit Emulation
Remote Debug
Real-Time as

Cache-3051
Hardware Models
General CAD Tools
Evaluation Board
Laser Printer System
X-Terminal System
Support Chips

3045 drw 06

Figure 6. R3051 Family Development Toolchain

5.4

6

IDT79R3071 RISControlier

COMMERCIAL TEMPERATURE RANGE

PERFORMANCE OVERVIEW

SELECTABLE FEATURES

The R3071 achieves a very high-level of performance. This
performance is based on:
• An efficient execution engine. The CPU performs ALU
operations and store operations in a single cycle, and has
an effective load time of 1.3 cycles, and branch execution
rate of 1.5 cycles (based on the ability of the compilers to
avoid software interlocks). Thus, the execution engine
achieves over 35VUPS performance when operating out of
cache.
• Large on-chip caches. The R3051 family contains caches
which are substantially larger than those on the majority of
today's microprocessors. These large caches minimize the
number of bus transactions required, and allow the R3051
family to achieve actual sustained performance very close
to its peak execution rate. The R3071 doubles the cache
available on the R3052.
• Autonomous multiply and divide operations. The R3051
family features an on-chip integer multiplier/divide unit
which is separate from the other ALU. This allows the CPU
to perform multiply or divide operations in parallel with other
integer operations, using a single multiply or divide
instruction rather than "step" operations.
• Integrated write buffer. The R3071 features a four-deep
write buffer, which captures store target addresses and
data at the processor execution rate and retires it to main
memory at the slower main memory access rate. Use of onchip write buffers eliminates the need for the processor to
stall when performing store operations.
• Burst read support. The R3051 family enables the system
designer to utilize page mode or nibble mode RAMs when
performing read operations to minimize the main memory
read penalty and increase the effective cache hit rates.
These techniques combine to allow the processorto achieve
over 35VUPS integer performance and 64,000 dhrystones
without the use of external caches or zero wait-state memory
devices.
The performance differences between the various family
members depends on the application software and the design
of the memory system. The impact of the various cache sizes,
and the hardware floating point, can be accurately modeled
using Cache-3051. Since the R3051, R3052, and R3071 are
all pin and software compatible, the system designer has
maximum freedom in trading between performance and cost.
A system can be designed, and later the appropriate CPU
inserted into the board, depending on the desired system
performance.

The R3071 allows the system designer to configure certain
aspects of operation. Some of these options are established
when the device is reset, while others are enabled via the
Config registers:
• BigEndian vs. LittleEndian Byte Ordering. The part can
be configured to operate with either byte ordering. ACE/
ARC systems typically use Little Endian byte ordering.
However, various embedded applications, written originally
for a Big Endian processor such as the MC6aOxO, are
easier to port to a Big Endian system.
• Data Cache Refill of one or four words. The memory
system must be capable of performing four word refills of
instruction cache misses. The R3071 allows the system
designer to enable D-Cache refill of one or four words
dynamically. Thus, specialized algorithms can choose one
refill size, while the rest of the system can operate with the
other.
• Half-frequency bus mode. The processor can be
configured such that the external bus interface is at onehalf the frequency of the processor core. This simplifies
system design; however, the large on-chip caches mitigate
the performance impact of using a slower system bus clock.
• Slow bus turn-around. The R3071 allows the system
designer to space processor operations, so that more time
is allowedfortransitions between memory and the processor
on the multiplexed address/data bus.
• Configurable cache. The R3071 allows the system
designer to use software to select either a 16kB Instruction
Cache/4kB Data Cache organization, or an akB Instruction/
akB Data Cache organization.
• Cache Coherent Interface. The R3071 has an optional
hardware based cache coherency interface intended to
support multi-master systems such as those utilizing DMA
between memory and I/O.

5.4

7

IDT79R3071 RISController

COMMERCIAL TEMPERATURE RANGE

THERMAL CONSIDERATIONS
The R3071 utilizes special packaging techniques to improve
the thermal properties of high-speed processors. Thus, the
R3071 is packaged using cavity-down packaging, utilizing
techniques to improve thermal transfer to the suurrounding
air.
The R3071 utilizes the 84-pin MOUAD package (the "MJ"
package), which is an all aluminum package with the die
attached to a normal copper lead-frame mounted to the
aluminum casing. The MOUAD package allows for an efficient
thermal transfer between the die and the case due to the heat
spreading effect of the aluminum. The aluminum offers less
internal resistance from one end of the package to the other,
reducing the temperature gradient across the package and
therefore presenting a greater area for convection and
conduction to the PCB for a given temperature. Even nominal
amounts of airflow will dramatically reduce the junction
temperature of the die, resulting in cooler operation. The
MQUAD package is available at all frequencies, and is pin and
form compatible with the PLCC used for the R3051. Thus,
designers can inter-change R3071 sand R3051 s in a particular
design, without changing their PC Board.

The R3071 is guaranteed in a case temperature range of
O°C to +85°C. The type of package, speed (power) of the
device, and airflow conditions, affect the equivalent ambient
temperature conditions which will meet this specification.
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(0CA) of the given package. The following equation relates
ambient and case temperatures:

TA = Tc - P * 0CA
where P is the maximum power consumption at hot
temperature, calculated by using the maximum Icc specification
for the device.
Typical values for 0CA at various airflows are shown in
Table 2.
Note that the R3071 allows the operational frequency to be
turned down during idle periodsto reduce powerconsumption.
This operation is described in the R3071 Hardware User's
Guide. Reducing the operation frequency dramatically reduces
power consumption.

0CA
Airflow (ftlmin)
"MJ" Package*
3045 drw02

Table 2. Thermal Resistance (0CA) at Various Airflows
(*estimated: final values tbd)

NOTES ON SYSTEM DESIGN
The R3071 has been designed to simplify the task of highspeed system design. Thus,set-up and hold-time requirements have been kept to a minimum,allowing a wide variety of
system interface strategies.
To minimize these AC parameters,the R3071 employs
feedback from its SysClk output to the internal bus interface
unit. This allows the R3071 to reference input signals to the
reference clock seen by the external system. The SysClk
output is designed to provide relatively large AC drive to
minimize skew due to slow rise or fall times. A typical part will
have less than 2ns rise or fall ( 10% to 90% signal times) when
driving the test load.
Therefore, the system designer should use care when
designing for direct SysClk use. Total loading (due to devices
connected on the signal net and the routing of the net itself)
should be minimized to ensure the SysClk output has a
smooth and rapid transition. Long rise and/or fall times may
cause a degradation in the speed capability of an individual
device.
Similarly, the R3071 employs feedback on its ALE output
to ensure adequate address hold time to ALE. The system
designer should be careful when designing the ALE net to
minimize total loading and to minimize skew between ALE and
the AID bus, which will ensure adequate address access latch
time.
lOT's field and factory applications groups can provide the
system designer with assistance for these and other design
issues.
5.4

8

IDT79R3071 RISController

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION
PIN NAME

110

AlD(31:0)

I/O

DESCRIPTION
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction
in one phase, and which is used to transmit data between the CPU and external memory resources during
the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:
Address(31 :4):

The high-order address for the transfer is presented on AlD(31 :4).

BE(3:0):

These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are presented on AlD(3:0).

During write cycles, the bus contains the data to be stored and is driven from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in either a single data
transaction or in a burst of four words, and places it into the on-chip read buffer.
During cache coherency operations, the R3071 monitors the AID bus at the start of a DMA write to capture
the write target address for potential data cache invalidates.
Addr(3:2)

liD

Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the processor.
Specifically, this two bit bus presents either the address bits for the single word to be transferred (writes
or single datum reads) or functions as a two bit counter starting at '00' for burst read operations.
During cache coherency operations, the R3071 monitors the Addr bus at the start of a DMA write to
capture the write target address for potential data cache invalidates.

Diag(1)

0

Diagnostic Pin 1. This output indicates whether the current bus read transaction is due to an onchip cache miss, and also presents part of the miss address. The value output on this pin is time
multiplexed:
Cached:

During the phase in which the AID bus presents address information, this
pin is an active high output which indicates whether the current read is
a result of a cache miss.

Miss Address (3):

During the remainder of the read operation, this output presents
address bit (3) of the address the processor was attempting to
reference when the cache miss occurred. Regardless of whether a
cache miss is being processed, this pin reports the transfer address
during this time.

On write cycles, this output signals whether the data being written as retained in the on-chip data cache.
The value of this pin is time multiplexed during writes:

Diag(O)

0

Cached:

During the address phase of write transactions, this signal is an active
high output which indicates that the store data was retained in the on-chip
data cache.

Reserved:

The value of this pin during the data phase of writes is reserved.

Diagnostic Pin O. This output distinguishes cache misses due to instruction references from those
due to data references, and presents the remaining bit of the miss address. The value output on this
pin is also time multiplexed:

110:

If the "Cached" Pin indicates a cache miss, then a high on this pin at this
time indicates an instruction reference, and a low indicates a data
reference. If the read is not due to a cache miss but rather an uncached
reference, then this pin is undefined during this phase.

Miss Address (2):

During the remainder of the read operation, this output presents
address bit (2) of the address the processor was attempting to
reference when the cache miss occurred. Regardless of whether a
cache miss is being processed, this pin reports the transfer address
during this time.

During write cycles, the value of this pin during both the address and data phases is reserved.
3045tbl03

5.4

9

IDT79R3071 RISControlier

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (Continued):
PIN NAME

1/0

DESCRIPTION

ALE

1/0

Address Latch Enable: Used to indicate that the AID bus contains valid address information for
the bus transaction. This signal is used by external logic to capture the address for the transfer, typically
using transparent latches.
During cache coherency operations, the R3071 monitors ALE at the start of a DMA write, to capture the
write target address for potential data cache invalidates.

Rd

0

Read: An output which indicates that the current bus transaction is a read.

Wr

1/0

Write: An output which indicates that the current bus transaction is a write.

DataEn

0

External Data Enable: This signal indicates that the AID bus is no longer being driven by the processor
during read cycles, and thus the external memory system may enable the drivers of the memory
system onto this bus without having a bus conflict occur. During write cycles, or when no bus
transaction is occurring, this signal is negated, thus disabling the external memory drivers

Burst!
WrNear

0

Burst TransferIWrite Near: On read transactions, the Burst signal indicates that the current bus read
is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles
due to cache misses; it is asserted for alii-Cache miss read cycles, and for D-Cache miss read cycles
if quad word refill is currently selected.

During coherent DMA, this input indicates that the current transfer is a write.

On write transactions, the WrNear output tells the external memory system that the bus interface unit
is performing back-to-back write transactions to an address within the same 512 word page as the prior
write transaction. This signal is useful in memory systems which employ page mode or static column
DRAMs, and allows near writes to be retired quickly.
Ack

I

Acknowledge: An input which indicates to the device that the memory system has sufficiently
processed the bus transaction, and that the CPU may either terminate the write cycle or
process the read data from this read transfer.
During Coherent DMA, this input indicates that the current write transfer is completed, and that the
internal invalidation address counter should be incremented.

RdCEn

I

Read Buffer Clock Enable: An input which indicates to the device that the memory system has
placed valid data on the AID bus, and that the processor may move the data into the on-chip Read
Buffer.

SysClk

0

System Reference Clock: An output from the CPU which reflects the timing of the internal
processor "Sys" clock. This clock is used to control state transitions in the read buffer, write buffer,
memory controller, and bus interface unit. This clock will either be at the same frequency as the CPU
execution rate clock, or at one-half that frequency, as selected during reset.

BusReq

I

DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus
interface signals so that they may be driven by an external master.

BusGnt

0

DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has been
detected, and that the bus is relinquished to the external master.

IvdReq

I

Invalidate Request. An input provided by an external DMA controller to request that the CPU invalidate
the Data Cache line corresponding to the current DMA write target address. This signal is the same pin
as Diag(O)

CohReq

I

Coherent DMA Request. An input used by the external DMA controller to indicate that the requested
DMA operations could involve hardware cache coherency. This signal is the Rsvd(O) of the R3051.

SBrCond(3:2)
BrCond(O)
BrCond(1)

I

Branch Condition Port: These external signals are internally connected to the CPU signals
CpCond(3:0). These signals can be used by the branch on co-processor condition instructions as input
ports. There are two types of Branch Condition inputs: the SBrCond inputs have special internal
logic to synchronize the inputs, and thus may be driven by asynchronous agents. The direct Branch
Condition inputs must be driven synchronously. Note that BrCond(1) is reserved for use by the R3081
internal FPA, and must be pulled-up externally.

BusError

I

Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error.
This signal is only sampled during read and write operations. If the bus transaction is a read operation,
then the CPU will take a bus error exception.
3045 tbl 04

5.4

10

IDT79R3071 RISController

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (Continued):
PIN NAME

1/0

DESCRIPTION

Int(5:3)
Slnt(2:0)

I

Processor Interrupt: During normal operation, these signals are logically the same as the Int(5:0)
signals of the R3000. During processor reset, these signals perform mode initialization of the CPU, but
in a different (simpler) fashion than the interrupt signals of the R3000.
There are two types of interrupt inputs: the Slnt inputs are internally synchronized by the processor,
and may be driven by an asynchronous external agent. The direct interrupt inputs are not internally
synchronized, and thus must be externally synchronized to the CPU. The direct interrupt inputs have
one cycle lower latency than the synchronized interrupts. Note that one interrupt, reserved for use by
the R3081 on-chip FPA, will not be monitored externally.

Clkln

I

Master Clock Input: This input clock is provided at the execution frequency of the CPU.

Reset

I

Master Processor Reset: This signal initializes the CPU. Mode selection is performed during
the last cycle of Reset.

Rsvd(4:1)

110

Reserved: These four signal pins are reserved for testing and for future revisions of this device.
Users must not connect these pins. Note that Rsvd(O) of the R3051 is now used for the CohReq input
pin.
3045 tbl 05

5.4

11

1DT79R3071 RISControl\er

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS(1, 3)
Symbol
VTERM

Rating
Terminal Voltage with Respect
toGND

Commercial

Unit

-0.5 to +7.0

V

o to +85

°C

-55 to +125

°C

Storage Temperature

-55 to +125

°C

Input Voltage

-0.5 to +7.0

V

Te

Operating Case Temperature

TBIAS

Temperature Under Bias

TSTG
VIN

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade

Temperature

GND

VCC

Commercial

O°C to +85°C

OV
(Case)

5.0±5%

Commercial

O°C to +85°C

OV
(Case)

3.3±5%
3U45 101 07

NOTES:
30451bl06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VIN minimum == -3.0V for pulse width less than 15ns.
VIN should not exceed Vcc +O.5V.
3. Notmorethan one output should be shorted ata time. Durationofthe short
should not exceed 30 seconds.

OUTPUT LOADING FOR AC TESTING

To Device
Under Test

AC TEST CONDITIONS-R3071
Symbol

Parameter

Min.

Max.

Unit

VIH

Input HIGH Voltage

3.0

-

V

VIL

Input LOW Voltage

-

0

V

VIHS

Input HIGH Voltage

3.5

-

V

VILS

Input LOW Voltage

-

0

V

3045 drw 07

Signal

eLD

SysClk

50 pf

All Others

25 pf
3045 Ibl 09

3045 Ibl 08

DC ELECTRICAL CHARACTERISTICS R3071- (Tc = O°C to +85°C, Vee = +5.0V ±5%)
33.33MHz
Symbol

Parameter

Test Conditions

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VIH

Input HIGH Voltage(3)

VIL

Input LOW Voltage(1)

-

VIHS

Input HIGH Voltage(2,3)

40MHz

50MHz

Min.

Max.

Min.

Vee = Min., 10H = -4mA

3.5

-

3.5

-

3.5

-

V

Vee = Min., 10L = 4mA

-

0.4

-

0.4

-

0.4

V

2.0

-

2.0

-

2.0

-

V

-

0.8

-

0.8

-

0.8

V

-

3.0

-

3.0

-

3.0

-

V

0.4

0.4

-

0.4

V

10

pF

10

-

10

pF

625

-

700

-

825

rnA

100

-

100

-

100

IlA
IlA

Max.

Min.

Max. Unit

Icc

Operating Current

Vee = 5V, Te = 25°C

-

IIH

Input HIGH Leakage

VIH= Vee

-

IlL

Input LOW Leakage

VIL= GND

-100

-

-100

-

-100

-

loz

Output Tri-state Leakage

VOH = 2.4V, VOL = 0.5V

-100

100

-100

100

-100

-100

VILS

Input LOW Voltage(1,2)

CIN

Input Capacitance(4)

-

COUT

Output Capacitance(4)

-

NOTES:
1.
2.
3.
4.

10

10
10

IlA

30451bll0

=

VIL Min. -3.0V for pulse width less than 15ns. VIL should not fall below -O.5V for larger periods.
VIHS and VILS apply to elkin and Reset.
VIH should not be held above Vcc + O.SV.
Guaranteed by design.

5.4

12

IDT79R3071 RISControlier

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS R3071

(1,2)_ (Tc = O°C to +85°C, VCC = +5.0V ±5%)
33.33MHz

Symbol
t1

Description

Signals
BusReq, Ack, BusError,
RdCEn, CohReq

Min.

40MHz

Max. Min.

Set·up to SysClk rising

4

-

3

50MHz

Max. Min.

-

5

Max. Unit

-

ns

t1a

NO

Set-up to sysClk falling

5

-

4.5

-

6

-

ns

t2

BusReq, Ack, Bus Error,
RdCEn, CohReq

Hold from SysClk rising

3

-

3

-

4

-

ns

t2a

NO
NO, Addr, Diag0LE, Wr

1

-

1

t3

-

2

-

Tri-state from SysClk rising

-

10

-

10

-

10

ns

Driven from SysClk falling

-

10

-

10

-

10

ns

6

-

5

ns

5

-

7

6

7

ns

-

5

ns

3

4

ns

3

-

4

ns

Hold from SysClk falling

BursVWrNear, Ad, DataEn
t4

NO, Addr, Diag, ALE, Wr
BursVWrNear, Ad, DataEn

t5

BusGnt

Asserted from sysClk rising

t6

BusGnt

Negated from SysClk falling

-

t7

Wr, Rd, BurstlWrNear,

Valid from sysClk rising

-

4

t8

ALE

Asserted from SysClk rising

3

t9

ALE

Negated from sysClk falling

-

3

-

t10

NO

Hold from ALE negated

1.5

-

1.5

-

1.5

-

ns

t11

DataEn

Asserted from sysClk falling

-

13

-

12

-

15

ns

t12

DataEn

Asserted from

0

-

0

Driven from SysClk rising(3)

0

-

0

-

ns

NO

-

0

t14
t15

Wr, Rd, DataEn, BursVWrNear Negated from sysClk falling

-

5

-

4

t16

Addr(3:2)

Valid from sysClk

-

5

-

4.5

t17

Diag

Valid from sysClk

-

10

-

9

-

t18

Tri-state from sysClk falling

11

-

8

SysClk falling to data out

-

9

t19

NO
NO

t20

Clkln (2x clock mode)

Pulse Width HIGH

6.5

-

5.6

NO

NO tri-state(3)

3.5

10

0

-

ns

6

ns

6

ns

11

ns

10

ns

12

ns

-

ns

t21

Clkln (2x clock mode)

Pulse Width LOW

6.5

-

5.6

-

N/A(6)

-

ns

t22

Clkln (2x clock mode)

Clock Period

15

250

12.5

250

N/A(6.7)

t23

Reset

Pulse Width from Vcc valid

200

IlS

Reset

Minimum Pulse Width

32

-

200

t24

-

-

t25

Reset

Set-up tosysClk falling

4

3

-

5

t26

Int

Mode set-up to Reset rising

8

7

-

9

t27

Int

Mode hold from Reset rising

0

0

Slnt, SBrCond

Set-up to sysClk falling

4

t29

Slnt, SBrCond

Hold from sysClk falling

2

-

0

t28

-

3

t30

Int, BrCond

Set-up to sysClk falling

4

t31

Int, BrCond

Hold from SysClk falling

2

-

3

200
32

-

3
2
3
2

N/A(6)

32

5

5

ns

tsys

-

ns

-

ns

ns
ns
ns

ns
ns

NOTES:
3045 tblll
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.
2. The AC values listed here reference timing diagrams contained in the R3081Family Hardware User's Manual.
3. Guaranteed by design.
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
5. The design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40MHz and 50MHz.
6. For the 50MHz version, 1x clock mode and half frequncy bus mode only.
7. when using the reduced frequency feature, the minimum allowed internal CPU speed is 0.5MHz.

5.4

13

IDT79R3071 RISController

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS R3071 (continued)(1, 2)_ (Tc =ooe to +85°e, VCC =+5.0V ±5%)
33.33MHz
Symbol

Signals

Description

Min.

40MHz

50MHz

Max. Min.

Max. Min.

tsys

SysClk (full frequency mode)

Pulse Width

2*t22

2*t22

2*t22

2*t22

N/A(7)

N/A(7)

t32

]YsClk (full frequency mode)

Clock HIGH time(6)

t22-1

t22+1

t22-1

t22+1

N/A(7)

N/A(7)

ns

t33

sysClk (full frequency mode)

Clock LOW time(6)

t22-1

t22+1

t22-1

t22+1

N/A(7)

N/A(7)

ns

Max. Unit
ns

tsy§/2

~sClk (half frequency mode)

Pulse Width(6)

2*t22

2*t22

2*t22

2*t22

2*t44

2*t44

ns

t34

sysClk (half frequency mode)

Clock HIGH Time(6)

t22-1

t22+1

t22-1

t22+1

t44-1

t44+1

ns

t3S

SysClk (half frequency mode)

Clock LOW Time(6)

t22-1

t22+1

t22-1

t22+1

t44-1

t44+1

ns

t36

ALE

Set-up to sysClk fallinq

7

-

6

-

8

ns

t37

ALE

Hold from SysClk falling

1

-

1

-

2

t38

Set-up to ALE fallinq

8

-

8

-

9

t39

ND
ND

Hold from ALE falling

1

-

1

-

2

t40

Wr

Set·up to sysClk rising

8

-

7

-

6

t41

Wr

Hold from SYSClk risinq

3

-

3

-

3

-

t42

Clkln (1 x clock mode)

Pulse Width HIGH(5)

13

11(5)

Clkln (1 x clock mode)

Pulse Width LOW(5)

13

11 (5)

-

16(5)

t43

-

t44

Clkln (1 x clock mode)

Clock Period(5)

30

SO

2S

SO

20

tderate

All outputs

Timing deration for loading
over CLD(3. 4)

-

1

-

1

16(5)

-

ns
ns
ns
ns
ns

-

ns

SO

ns

1

nsl
2SpF

ns

NOTES:
3045 tbl12
1. All timings referenced to 1.SV. All timings measured with respect to a 2.Sns rise and fall time.
2. The AC values listed here reference timing diagrams contained in the R3081Family Hardware User's Manual.
3. Guaranteed by design.
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 2SpF over the specified test load condition.
S. The design guarantees that the input clock rise and fall times can be as long as Sns, 3ns for 40MHz and SOMHz.
6. In 1x clock mode, 122 is replaced by t44/2.
7. For the SOMHz version, 1x clock mode and half frequency bus mode only.
8. When using the reduced frequency feature, the minimum allowed internal CPU speed is O.SMHz.

5.4

14

IDT79R3071 RISControlier

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS
C;;

0'
0>
C')

0' 0'
~

~

~

0

~

co
C\J

t::'
C\J

0' 0'
~

~

(0

en
en

C\J

t)
t)

> >

LO
C\J

~
C\J

M N
C\J
C\J

N

0' 0' 0' 0' 0' 0'
~

~

~

~

~

~

t)
t)

>

en
en

>

0' 0>
....
~

~

~

co

t::'

(0

0'

~

0' 0'

~

....

LO

~

~

84

Vss

75

Vss

12

Vee

Vee
Clkln

NO(14)

Rsvd(4)

NO(13)

Rsvd(3)

NO(12)

Rsvd(2)

NO(11)

Rsvd(1 )

NO(10)

CohReq

NO(9)

Vee

Int(5)

Vss

Vss

Vee

NO(8)

Int(4)

NO(7)

Int(3)

NO(6)

Slnt(2)

NO(5)

Slnt(1)

NO(4)

Slnt(O)

NO(3)

SBrCond(3)

Vss

SBrCond(2)

Vee

BrCond(1)

NO(2)

Vss

NO(1)

Vee

54

0'

:cc
0

'2
OJ

If I~ II II Ii Ii
I~

IJ

en
en

t)
t)

> >

/~

/If

w
-l
 >

NO(O)

§: M O>~
:g- z
-0
"C
"C
~

~

T37

~

T36

r--

I

T40

I~

iii

T41
II

I
I

K

>K

T38

T39

.> K

-f-

Internal
Invalidate
Address
3045 dlW 26

Figure 22. Beginning of Coherent DMA Write

5.4

23

1DT19R3071 RISController

COMMERCIAL TEMPERATURE RANGE

SysClk _ _ _ _. I

Ack

IvdReq

Internal
Ivd
Internal
Invalidate
Address

-----4------+------+--...
-----4------+------+--'
Figure 23. Cache Word Invalidation

3045 drw 27

SysClk

Ack
T40

Wr
T41

3045 drw 28

Figure 24. End of Coherent Write

. / rL'
./

./

.c

~

K

..?

'L'

t2

t1

~

L'
_I

ts

BusGnt

t4

AlO(31:0)

["'....

Addr(3:2)

I...........

Oiag(1:0)

I"'"

<

<
<
~
~

ALE

""Figure 25. End of Coherent DMA Request

5.4

/'
~
3045 drw 29

24

II

IDT79R3071 RISControlier

COMMERCIAL TEMPERATURE RANGE

84 LEAD MQUAD(7)

e

45°x.045

E3

~r+-----------1-------------rT

D E2

s

SEATING PLANE
3045 drw 30

NOTES:
1. All dimensions are in inches, unless otherwise noted.
2. BSC-Basic lead Spacing between Centers.
3. D & E do not include mold flash or protutions.
4. Formed leads shall be planar with respect to one another and within .004" at the seating plane.
5. ND & NE represent the number of leads in the D & E directions respectively.
6. D1 & E1 should be measured from the bottom of the package.
7. 84-pin MQUAD is pin & form compatible with 84-pin PLCC of R3051/2

MJ84-1

DWG#
# of Leads

84

Symbol

Min.

Max.

A

165

.180

A1

.094

.114

S

.026

.032

b1

.013

.021

e

.020

.040

e1

.008

.012

D

1.185

1.195

D1

1.140

1.150

D2/E2

1.090

D3/E3

1.130
1.000 REF

E

1.185

E1

1.140

1.195
1.150

e

.050 sse

ND/NE

21
3045 tbl13

5.4

25

IDT79R3071 RISControlier

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

xxxxx

IDT--Device Type

xx

x

Speed Package

I

x
Process/
Temp. Range

·~IBlank

Commercial Temperature Range

~'MJ'

84-Pin MQUAD

33

33.33MHz
40.0MHz
50.0MHz

~-------------~ 40

50

79R3071
~--------------------------~ 79R3071E

NoTLB
WithTLB

3045 drw 31

VALID COMBINATIONS
lOT 79R3071 - 33,40,50 MJ
79R3071 E - 33, 40, 50 MJ

II

MOUAD Package
MOUAD Package

5.4

26

~

r;J

lOT 79R3081 TM, 79R3081 E
lOT 79RV3081, 79RV3081 E

IDT79R3081
RISControlier™
with FPA

Integrated Device Technology, Inc.

FEATURES

• Large on-chip caches with user configurability
- 16kB Instruction Cache, 4kB Data Cache
- Dynamically configurable to BkB Instruction Cache,
BkB Data Cache
- Parity protection over data and tag fields
• Low cost B4-pin packaging
• Superset pin- and software-compatible with R3051, R3071
• Multiplexed bus interface with support for low-cost, lowspeed memory systems with a high-speed CPU
• On-chip 4-deep write buffer eliminates memory write stalls
• On-chip 4-deep read buffer supports burst or simple block
reads
• On-chip DMA arbiter
• Hardware-based Cache Coherency Support
• Programmable power reduction mode
• Bus Interface can operate at half-processor frequency

• Instruction set compatible with IDT79R3000A, R3041 ,
R3051, and R3071 RISC CPUs
• High level of integration minimizes system cost
- R3000A Compatible CPU
- R3010A Compatible Floating Point Accelerator
- Optional R3000A compatible MMU
- Large Instruction Cache
- Large Data Cache
- Read/Write Buffers
• 43VUPS at 50MHz
- 13MFlops
• Flexible bus interface allows simple, low cost designs
• Optional 1x or 2x clock input
• 20 through 50MHz operation
• "V" version operates at 3.3V
• 50MHz at 1x clock input and 1/2 bus frequency only

R3081 BLOCK DIAGRAM
Clkln

Clock Generator
Unit/Clock Doubler

-,
System Control
Coprocessor
(CPO)

Integer
CPU Core

Exception/Control
Registers

General Registers
(32 x 32)

Floating Point
Coprocessor
(CP1)
Register Unit
(16 x 64)

ALU

Exponent Unit

Memory Management
Registers

Int(5:0)

BrCond(3'2
. ,0)

,

Master Pipeline Control

Shifter

Add Unit

MultiDiv Unit

Translation
Lookaside Buffer
(64 entries)

Divide Unit

Address Adder

Multiply Unit

PC Control

t

I

Virtual Address

Exception/Control
FP Interrupt

Data Bus

Phvsical Address Bus
33~

+

t

+

Configurable
Instruction
Cache
(16kB/8kB)

•
Parity
Generator
4-deep
Read
Buffer

+

Configurable
Data
Cache
(4kB/8kB)
Data Bus

3~V'

•

R3051 Superset Bus Interface Unit
4-deep
Write
Buffer

Address/
Data

DMA
Arbiter

+

DMA
Ctrl

I

BIU
Control

-+

RdlWr
Ctrl

I

t

Coherency
Logic

SysClk

t

Invalidate
Control

2889 drw 01

The /DT logo is a registered trademark. and RISControlier, R3041, R30S1, R30S2, R3071, R3081 , R3720, R4400, R4600, IDTlkit, and /DT/sim are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1 99S Integrated Device Technology, Inc.

5.5

SEPTEMBER 1995
DSC-9064/4

1

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

•

The R3051, which incorporates 4kB of instruction cache
and 2kB of data cache, but omits the TLB, and instead uses
a simpler virtual to physical address mapping.
• The R3081 E, which incorporates a 16kB instruction cache,
a 4kB data cache, and full function memory management
unit (MMU) including 64-entry fully associative Translation
Lookaside Buffer (TLB). The cache on the R3081 E is user
configurable to an 8kB Instruction Cache and 8kB Data
Cache.
• The R3081, which incorporates a 16kB instruction cache,
a 4kB data cache, but uses the simpler memory mapping
of the R3051 /52, and thus omits the TLB. The cache on the
R3081 is user configurable to an 8kB Instruction Cache and
8kB Data Cache.
Figure 1 shows a block leve I representation of the functional
units within the R3081 E. The R3081 E could be viewed as the
embodiment of a discrete solution built around the R3000A
and R3010A. However, by integrating this functionality on a
single chip, dramatic cost and power reductions are achieved.

INTRODUCTION
The lOT R3051 family is a series of high-performance 32bit microprocessors featuring a high-level of integration, and
targeted to high-performance but cost sensitive processing
applications. The R3051 family is designed to bring the highperformance inherent in the MIPS RISC architecture into
low-cost, simplified, power sensitive applications.
Thus, functional units have been integrated onto the CPU
core in order to reduce the total system cost, rather than to
increase the inherent performance of the integer engine.
Nevertheless, the R3051 family is able to offer 43VUPS
performance at 50MHz without requiring external SRAM or
caches.
The R3081 extends the capabilities of the R3051 family, by
integrating additional resources into the same pin-out. The
R3081 thus extends the range of applications addressed by
the R3051 family, and allows designers to implement a single,
base system and software set capable of accepting a wide
variety of CPUs, according to the price/performance goals of
the end system.
In addition to the embedded applications served by the
R3051 family, the R3081 allows low-cost, entry level computer
systems to be constructed. These systems will offer many
times the performance of traditional PC systems, yet cost
approximately the same. The R3081 is able to run any
standard R3000A operation system, including ACE UNIX.
Thus, the R3081 can be used to build a low-cost ARC
compliant system, further widening the range of performance
solutions of the ACE Initiative.
An overview of this device, and quantitative electrical
parameters and mechanical data, is found in this data sheet;
consult the "R3081 Family Hardware User's Guide" for a
complete description of this processor.

DEVICE OVERVIEW
As part of the R3051 family, the R3081 extends the offering
of a wide range of functionality in a compatible interface. The
R3051 family allows the system designer to implement a
single base system, and utilize interface-compatible processors
of various complexity to achieve the price-performance goals
of the particular end system.
Differences among the various family members pertain to
the on-Chip resources ofthe processor. Currentfamily members
include:
• The R3052E, which incorporates an 8kB instruction cache,
a 2kB data cache, and full function memory management
unit (MMU) including 64-entry fully associative Translation
Lookaside Buffer (TLB).
• The R3052, which also incorporates an 8kB instruction
cache and 2kB data cache, but does not include the TLB,
and instead uses a simpler virtual to physical address
mapping.
• The R3051 E, which incorporates 4kB of instruction cache
and 2kB of data cache, along with the full function MMU/
TLB of the R3000A.

CPU Core
The CPU core is a full 32-bit RISC integer execution
engine, capable of sustaining close to single cycle execution.
The CPU core contains a five stage pipeline, and 320rthogonal
32-bit registers. The R3081 uses the same basic integer
execution core as the entire R3051 family, which is the
R3000A implementation of the MIPS instruction set. Thus, the
R3081 family is binary compatible with the R3051, R3052,
R3000A, R3001, and R3500 CPUs. In addition, the R4000
represents an upwardly software compatible migration path to
still higher levels of performance.
The execution engine in the R3081 uses a five-stage
pipeline to achieve near single-cycle instruction execution
rates. A new instruction can be initiated in each clock cycle;
the execution engine actually processes five instructions
concurrently (in various pipeline stages). Figure 2 shows the
concurrency achieved in the R3081 execution pipeline.

System Control Co-Processor
The R3081 family also integrates on-chip the System
Control Co-processor, CPO. CPO manages both the exception
handling capability of the R3081 , as well as the virtual to
physical address mapping.
As with the R3051 and R3052, the R3081 offers two
versions of memory management and virtual to physical
address mapping: the extended architecture versions, the
R3051 E, R3052E, and R3081 E, incorporate the same MMU
as the R3000A. These versions contain a fully associative 64entry TLB which maps 4kB virtual pages into the physical
address space. The virtual to physical mapping thus includes
kernel segments which are hard-mapped to physical
addresses, and kernel and user segments which are mapped
page by page by the TLB into anywhere in the 4GB physical
address space. In this TLB, 8 pages can be "locked" by the
kernel to insure deterministic response in real-time applications.
Figure 3 illustrates the virtual to physical mapping found in the
R3081E.

5.5

2

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The extended architecture versions of the R3051 family
(the R3051 E, R3052E, and R3081 E) allow the system designer
to implement kernel software which dynamically manages
user task utilization of system resources, and also allows the
Kernel to protect certain resources from user tasks. These
capabilities are important in general computing applications
such as ARC computers, and are also important in a variety of
embedded applications, from process control (where protection
may be important) to X-Window display systems (where
virtual memory management can be used). The MMU can
also be used to simplify system debug.
R3051 family baseversions (the R3051, R3052,and R3081)
remove the TLB and institute a fixed address mapping for the
various segments ofthe virtual address space. These devices
still support distinct kernel and user mode operation, but do
not require page management software, leading to a simpler
software model. The memory mapping used by these devices
is shown in Figure 4. Note that the reserved spaces are for
compatiblity with future family members, which may map onchip resources to these addresses. References to these
addresses in the R3081 will be translated in the same fashion
as the rest of their respective segments, with no traps or
exceptions signalled.
When using the base versions of the architecture, the
system designer can implement a distinction between the
user tasks and the kernel tasks, without having to implement
page management software. This distinction can be
implemented by decoding the output physical address. In
systems which do not need memory protection, and wish to
have the kernel and user tasks operate out of the same
memory space, high-order address lines can be ignored by
the address decoder, and thus all references will be seen in
the lower gigabyte of the physical address space.

1#1

Current
CPU
Cycle

2889 drw 02

Figure 2. R3081 5-Stage Pipeline

VIRTUAL

PHYSICAL

Oxffffffff

Kernel Mapped
(kseg2)
OxcOOOOOOO

Kernel Uncached
(kseg1 )
OxaOOOOOOO

Kernel Cached
(ksegO)

W
-

Physical
Memory

>- 3548MB

-4

Ox80000000
User Mapped
Cacheable
(kuseg)

t

Floating Point Co-Processor
The R3081 also integrates an R3010A compatible floating
OxOOOOOOOO
point accelerator on-chip. The FPA is a high-performance co2889 drw 03
Figure 3. Virtual to Physical Mapping of Extended Architecture
processor (co~processor 1 to the CPU) providing separate
Versions
add, multiply, and divide functional units for single and double
precision floating point arithmetic. The floating point accelerator
VIRTUAL
PHYSICAL
features low latency operations, and autonomous functional
Oxffffffff 1MB Kernel Rsvd
units which allow differing types of floating point operations to
function concurrently with integer operations. The R3010A
Kernel Cached --... Kernel Cacheable 1024 MB appears to the software programmer as a simple extension of
Tasks
(kseg2)
the integer execution unit, with 16 dedicated 64-bit floating
pOint registers (software references these as 32 32-bit registers
OxcOOOOOOO
when performing loads or stores). Figure 5 illustrates the
Kernel Uncached
(kseg1 )
functional block diagram of the on-chip FPA.
OxaOOOOOOO

Kernel Cached
(ksegO)

r

Ox80000000

Memory

>-

512MB

Kernel/User
Cacheable
Tasks

2048 MB Clock Generator Unit

Inaccessible

512 MB

Kernel Boot
and I/O

512 MB

1MB User Rsvd
User
Cached
(kuseg)
OxOOOOOOOO

~

2889 drw 04

The R3081 is driven from a single input clock which can be
either at the processor rated speed, or attwice that speed. Onchip, the clock generator unit is responsible for managing the
interaction of the CPU core, caches, and bus interface. The
R3081 includes an on-chip clock doubler to provide higher
frequency signals to the internal execution core; if 1x clock
mode is selected, the clock doubler will internally convert it to

Figure 4. Virtual to Physical Mapping of Base Architecture Versions

5.5

3

IDT79R30B1 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

a double frequency clock. The 2x clock mode is provided for
compatiblity with the R3051. The clock generator unit replaces
the external delay line required in R3000A based applications.

Instruction Cache
The R3081 implements a 16kB Instruction Cache. The
system may choose to repartition the on-chip caches, so that
the instruction cache is reduced to 8kB but the data cache is
increased to 8kB. The instruction cache is organized with a
line size of 16bytes (four entries). This large cache achieves
hit rates in excess of 98% in most applications, and substantially
contributes to the performance inherent in the R3081. The
cache is implemented as a direct mapped cache, and is
capable of caching instructions from anywhere within the 4GB
phYSical address space. The cache is implemented using
physical addresses (rather than virtual addresses), and thus
does not require flushing on context switch.
The instruction cache is parity protected over the instruction
word and tag fields. Parity is generated by the read buffer
during cache refill; during cache references, the parity is
checked, and in the case of a parity error, a cache miss is
processed.
Data Cache
The R3081 incorporates an on-chip data cache of 4kB,
organized as a line size of 4 bytes (one word). The R3081
allows the system to reconfigure the on-chip cache from the
default 16kB I-Cache/4kB D-Cache to 8kB of Instruction and
8kB of Data caches.
The relatively large data cache achieves hit rates in excess
of 95% in most applications, and contributes substantially to

Cache
Data

the performance inherent in the R3081. As with the instruction
cache, the data cache is implemented as a direct mapped
physical address cache. The cache is capable of mapping any
word within the 4GB physical address space.
The data cache is implemented as a write-through cache,
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance. Further, support has been provided to allow
hardware based data cache coherency in a multi-master
environment, such as one utilizing DMA from 110 to memory.
The data cache is parity protected over the data and tag
fields. Parity is generated by the read buffer during cache refill;
during cache references, the parity is checked, and in the case
of a parity error, a cache miss is processed.

Bus Interface Unit
The R3081 uses its large internal caches to provide the
majority of the bandwidth requirements of the execution
engine, and thus can utilize a Simple bus interface connected
to slower memory devices. Alternately, a high-performance,
low-cost secondary cache can be implemented, allowing the
processor to increase performance in systems where bus
bandwidth is a performance limitation.
As part ofthe R3051 family, the R3081 bus interface utilizes
a 32-bit address and data bus multiplexed onto a single set of
pins. The bus interface unit also provides an ALE (Address
Latch Enable) output signal to de-multiplex the AID bus, and

Data Bus

Operands
Register Unit (16 X 64)
Fraction
Condition
Codes

(11)

(11)

A
Control Unit
and Clocks

B

(53)

(53)

Result
Add Unit

Exponent
Unit
(53)

Divide Unit
(53)

Multiply Unit

2889 drw 05

Figure 5. FPA Functional Block Diagram

5.5

4

II

IDT79R3081 RISControl/er

simple handshake signals to process CPU read and write
requests. In addition to the read and write interface, the R3051
family incorporates a DMA arbiter, to allow an external master
to control the external bus.
The R3081 also supports hardware based cache coherency
during DMA writes. The R3081 can invalidate a specified line
of data cache, or in fact can perform burst invalidations during
burst DMA writes.
The R3081 incorporates a 4-deep write buffer to decouple
the speed of the execution engine from the speed of the
memory system. The write buffers capture and FIFO processor
address and data information in store operations, and present
it to the bus interface as write transactions at the rate the
memory system can accommodate.
The R3081 read interface performs both single datum
reads and quad word reads. Single reads work with a simple
handshake, and quad word reads can either utilize the simple
handshake (in lower performance, simple systems) or utilize
a tighter timing mode when the memory system can burst data
at the processor clock rate. Thus, the system designer can
choose to utilize page or nibble mode DRAMs (and possibly
use interleaving, if desired, in high-performance systems), or
use simpler techniques to reduce complexity.
In order to accommodate slower quad word reads, the
R3081 incorporates a 4-deep read buffer FIFO, so that the
external interface can queue up data within the processor
before releasing it to perform a burst fill of the internal caches.
The R3081 is R3051 superset compatible in its bus interface.
Specifically, the R3081 has additional support to simplify the
design of very high frequency systems. This support includes
the ability to run the bus interface at one-half the processor
execution rate, as well as the ability to slow the transitions
between reads and writes to provide extra buffer disable time
for the memory interface. However, it is still possible to design
a system which, with no modification to the PC Board or
software, can accept either an R3041 , R3051 , R3052, R3071 ,
or R3081.

SYSTEM USAGE
The IDT R3051 family has been specifically designed to
allow a wide variety of memory systems. Low-cost systems
can use slow speed memories and simple controllers, while
other designers may choose to incorporate higherfrequencies,
faster memories, and techniques such as DMA to achieve
maximum performance. The R3081 includes specific support
for high perfromance systems, including signals necessary to
implement external secondary caches, and the ability to
perform hardware based cache coherency in multi-master
systems.
Figure 6 shows a typical system implementation.
Transparent latches are used to de-mUltiplex the R3081
address and data busses from the AID bus. The data paths
between the memory system elements and the AID bus is
managed by simple octal devices. A small set of simple PALs
is used to control the various data path elements, and to
control the handshake between the memory devices and the
CPU.
Depending on the costvs. performance tradeoffs appropriate

MILITARY AND COMMERCIAL TEMPERATURE RANGES

to a given application, the system design engineer could
include true burst support from the DRAM to provide for highperformance cache miss processing, or utilize a simpler,
lower performance memory system to reduce cost and simplify
the design. Similarly, the system designer could choose to
implement techniques such as external secondary cache, or
DMA, to further improve system performance.

DEVELOPMENT SUPPORT

a

The IDT R3051 family is supported by
rich set of
development tools, ranging from system simulation tools
through PROM monitor and debug support, applications
software and utility libraries, logic analysis tools, SUb-system
modules, and shrink wrap operating systems. The R3081 ,
which is pin and software compatible with the R3051, can
directly utilize these existing tools to reduce time to market.
Figure 7 is an overview of the system development process
typically used when developing R3051 family applications.
The R3051 family is supported in all phases of project
development. These tools allow timely, parallel development
of hardware and software for R3051 family applications, and
include tools such as:
• Optimizing compilers from MIPS, the acknowledged leader
in optimizing compiler technology.
• Cross development tools, available in a variety of
development environments.
• The IDT Evaluation Board, which includes RAM, EPROM,
I/O, and the IDT PROM Monitor.
• IDT/sim'", which implements a full prom monitor
(diagnostics, remote debug support, peek/poke, etc.).
• IDT/kif", which implements a run-time support package for
R3051 family systems.

PERFORMANCE OVERVIEW
The R3081 achieves a very high-level of performance. This
performance is based on:
• An efficient execution engine. The CPU performs ALU
operations and store operations in a single cycle, and has
an effective load time of 1.3 cycles, and branch execution
rate of 1.5 cycles (based on the ability of the compilers to
avoid software interlocks). Thus, the execution engine
achieves over 35 VUPS performance when operating out
of cache.
• A full featured floating point accelerator/co-processor.
The R3081 incorporates an R3010A compatible floating
point accelerator on-chip, with independentALUs forfloating
point add, multiply, and divide. The floating point unit is fully
hardware interlocked, and features overlapped operation
and precise exceptions. The FPA allows floating point
adds, multiplies, and divides to occur concurrently with
each other, as well as concurrently with integer operations.
• Largeon-chipcaches. The R3051 family contains caches
which are substantially larger than those on the majority of
today's microprocessors. These large caches minimize the
number of bus transactions required, and allow the R3051
family to achieve actual sustained performance very close
to its peak execution rate. The R3081 doubles the cache
available on the R3052, making it a suitable engine for
5.5

5

IDT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Clkln
IDT R3081
RISControlier

AddresslData

Control

R3051
Local Bus

11
DRAM
Controller

1/0 Controller

1
1/0

PROM

1/0

t

DRAM

DRAM

J

t

II

IDT73720
Bus Exchanger

J
2889 drw 06

Figure 6. R3081 RISChipset Based System

System
Architecture
Evaluation

System
Development
Phase

System
Integration
and Verfification

Software
DBG Debugger
PIXIE Profiler
MIPS Compiler Suite
Stand-Alone Libraries
Floating Point Library
Cross Development Tools
Adobe PostScript PDL
MicroSoft Truelmage PDL
PeerlessPage Printer OS
X-Server

Hardware
Hardware Models
General CAD Tools
Evaluation Board
Laser Printer System
Support Chips
2889 drw 07

Figure 7. R3051 Family Development Toolchain

5.5

6

IDT79R3081 RISControl/er

many general purpose computing applications, such as
ARC compliant systems.
• Autonomous multiply and divide operations. The R3051
family features an on-chip integer multiplier/divide unit
which is separate from the other ALU. This allows the CPU
to perform multiplyordivide operations in parallel with other
integer operations, using a single multiply or divide
instruction rather than "step" operations.
• Integrated write buffer. The R30B1 features a four deep
write buffer, which captures store target addresses and
data at the processor execution rate and retires it to main
memory at the slower main memory access rate. Use of onchip write buffers eliminates the need for the processor to
stall when performing store operations.
• Burst read support. TheR3051 family enables the system
designer to utilize page mode or nibble mode RAMs when
performing read operations to minimize the main memory
read penalty and increase the effective cache hit rates.
These techniques combine to allow the processor to achieve
over 43 VUPS integer performance, 13MFIops of Linpack
performance, and 70,000 dhrystones without the use of external
caches or zero wait-state memory devices.
The performance differences between the various family
members depends on the application software and the design
of the memory system. The impact of the various cache sizes,
and the hardware floating point, can be accurately modeled
using Cache-3051. Since the R3041, R3051, R3052, R3071 ,
and R30B1 are all pin and software compatible, the system
designer has maximum freedom in trading between
performance and cost. A system can be designed, and later
the appropriate CPU inserted into the board, depending on the
desired system performance.

SELECTABLE FEATURES
The R30B1 allows the system designer to configure certain
aspects of operation. Some of these options are established
when the device is reset, while others are enabled via the
Config registers:
• BigEndian vs. LittleEndian Byte Ordering. The part can
be configured to operate with either byte ordering. ACE/
ARC systems typically use Little Endian byte ordering.
However, various embedded applications, written originally
for a Big Endian processor such as the MC6BOxO, are
easier to port to a Big Endian system.
• Data Cache Refill of one or four words. The memory
system must be capable of performing four word refills of
instruction cache misses. The R30B1 allows the system
deSigner to enable D-Cache refill of one or four words
dynamically. Thus, specialized algorithms can choose one
refill size, while the rest of the system can operate with the
other.
• Half-frequency bus mode. The processor can be
configured such that the external bus interface is at onehalf the frequency of the processor core. This simplifies
system design; however, the large on-chip caches mitigate
the performance impact of using a slower system bus clock.
• Slow bus turn-around. The R30B1 allows the system
designer to space processor operations, so that more time

MILITARY AND COMMERCIAL TEMPERATURE RANGES

is allowed fortransitions between memory and the processor
on the multiplexed address/data bus.
• Configurable cache. The R30B1 allows the system
designer to use software to select either a 16kB Instruction
Cache/4kB Data Cache organization, or an BkB Instruction/
BkB Data Cache organization.
• Cache Coherent Interface. The R30B1 has an optional
hardware based cache coherency interface intended to
support multi-master systems such as those utilizing DMA
between memory and I/O.
• Optional1x or 2x clock input. The R30B1 can be driven
with an R3051 compatible 2x clock input, or a lower
frequency 1x clock input.

THERMAL CONSIDERATIONS
The R30B1 utilizes special packaging techniques to improve
the thermal properties of high-speed processors. Thus, the
R30B1 is packaged using cavity down packaging, with an
embedded thermal slug to improve thermal transfer to the
suurrounding air.
The R30B1 utilizes the B4-pin MOUAD package (the "MJ"
package), which is an all aluminum package with the die
attached to a normal copper lead-frame mounted to the
aluminum casing. The MOUAD packageallowsforan efficient
thermal transfer between the die and the case due to the heat
spreading effect of the aluminum. The aluminum offers less
internal resistance from one end of the package to the other,
reducing the temperature gradient across the package and
therefore presenting a greater area for convection and
conduction to the PCB for a given temperature. Even nominal
amounts of airflow will dramatically reduce the junction
temperature of the die, resulting in cooler operation. The
MOUAD package is available at all frequencies, and is pin and
form compatible with the PLCC used for the R3051. Thus,
designers can inter-change R30B1 sand R3051 s in a particular
design, without changing their PC Board.
The R30B1 is guaranteed in a case temperature range of
O°C to +B5°C. The type of package, speed (power) of the
device, and airflow conditions, affect the equivalent ambient
temperature conditions which will meet this specification.
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(0CA) of the given package. The following equation relates
ambient and case temperatures:
TA =T c - P * 0CA
where P is the maximum power consumption at hot
temperature, calculated by using the maximum Icc specification
for the device.
Typical values for 0CA at various airflows are shown in
Table 1.
Note that the R30B1 allows the operational frequency to be
turned down during idle periods to reduce powerconsumption.
This operation is described in the R3081 Hardware User's
Guide. Reducing the operation frequency dramatically reduces
power consumption.

5.5

7

IDTISR3081 RISControl\er

MILITARY AND COMMERCIAL TEMPERATURE RANGES

minimize skew due to slow rise or fall times. A typical part will
have less than 2ns rise or fall (10% to 90% signal times) when
driving the test load.
Therefore, the system designer should use care when
designing for direct SysClk use. Total loading (due to devices
connected on the signal net and the routing of the net itself)
should be minimized to ensure the SysClk output has a
smooth and rapid transition. Long rise and/or fall times may
cause a degradation in the speed capability of an individual
device.
Similarly, the R3081 employs feedback on its ALE outputto
ensure adequate address hold time to ALE. The system
designer should be careful when deSigning the ALE net to
minimize total loading and to minimize skew between ALE and
the AID bus, which will ensure adequate address access latch
time.
lOT's field and factory applications groups can provide the
system designer with assistance for these and other design
issues.

0CA
Airflow (ftlmin)
"MJ" Package*
PLCC Package

0
22
29

200
14
26

400
12
21

600
11
18

800
9
16

1000
8
15
2889tbiOl

Table 1. Thermal Resistance ("CA) at Various Airflows
(*estimated: final values tbd)

NOTES ON SYSTEM DESIGN
The R3081 has been designed to simplify the task of highspeed system design. Thus, set-up and hold-time requirements
have been kept to a minimum, allowing a wide variety of
system interface strategies.
To minimize these AC parameters, the R3081 employs
feedback from its SysClk output to the internal bus interface
unit. This allows the R3081 to reference input signals to the
reference clock seen by the external system. The SysClk
output is designed to provide relatively large AC drive to

II

5.5

8

IDT79R3081 RISControl/er

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION
PIN NAME

1/0

A/D(31:0)

1/0

DESCRIPTION
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction
in one phase, and which is used to transmit data between the CPU and external memory resources during
the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:
Address(31 :4):

The high-order address for the transfer is presented on AlD(31 :4).

BE(3:0):

These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are presented on AlD(3:0).

During write cycles, the bus contains the data to be stored and is driven from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in either a single data transaction
or in a burst of four words, and places it into the on-chip read buffer.
During cache coherency operations, the R3081 monitors the AID bus at the start of a DMA write to capture
the write target address for potential data cache invalidates.
Addr(3:2)

0

Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the processor.
Specifically, this two bit bus presents either the address bits for the single word to be transferred (writes
or single datum reads) or functions as a two bit counter starting at '00' for burst read operations.
During cache coherency operations, the R3081 monitors the Addr bus at the start of a DMA write to
capture the write target address for potential data cache invalidates.

Diag(1)

0

Diagnostic Pin 1. This output indicates whether the current bus read transaction is due to an on-chip
cache miss, and also presents part of the miss address. The value output on this pin is time multiplexed:
Cached:

During the phase in which the AID bus presents address information, this
pin is an active HIGH output which indicates whether the current read is
a result of a cache miss.

Miss Address (3):

During the remainder of the read operation, this output presents address
bit (3) ofthe address the processor was attempting to reference when the
cache miss occurred. Regardless of whether a cache miss is being
processed, this pin reports the transfer address during this time.

On write cycles, this output signals whether the data being written as retained in the on-chip data cache.
The value of this pin is time multiplexed during writes:

Diag(O)

0

Cached:

During the address phase of write transactions, this signal is an active
high output which indicates that the store data was retained in the on-chip
data cache.

Reserved:

The value of this pin during the data phase of writes is reserved.

Diagnostic Pin O. This output distinguishes cache misses due to instruction references from those
due to data references, and presents the remaining bit of the miss address. The value output on this
pin is also time multiplexed:

lID:

If the "Cached" Pin indicates a cache miss, then a high on this pin at this
time indicates an instruction reference, and a low indicates a data
reference. If the read is not due to a cache miss but rather an un cached
reference, then this pin is undefined during this phase.

Miss Address (2):

During the remainder of the read operation, this output presents
address bit (2) of the address the processor was attempting to
reference when the cache miss occurred. Regardless of whether a
cache miss is being processed, this pin reports the transfer address
during this time.

During write cycles, the value of this pin during both the address and data phases is reserved.
2889 tbl02

5.5

9

IDT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION (Continued):
PIN NAME
ALE

VO

DESCRIPTION

1/0

Address Latch Enable: Used to indicate that the ND bus contains valid address information for the bus
transaction. This signal is used by external logic to capture the address for the transfer, typically using
transparent latches.
During cache coherency operations, the R3081 monitors ALE at the start of a DMA write, to capture the write
target address for potential data cache invalidates.

Rd

0

Read: An output which indicates that the current bus transaction is a read.

Wr

1/0

Write: An output which indicates that the current bus transaction is a write. During coherent DMA, this input
indicates that the current transfer is a write.

DataEn

0

External Data Enable: This signal indicates that the ND bus is no longer being driven by the processor during
read cycles, and thus the external memory system may enable the drivers of the memory system onto this bus
without having a bus conflict occur. During write cycles, or when no bus transaction is occurring, this signal is
negated, thus disabling the external memory drivers

BursV
WrNear

0

Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current bus read is
requesting a block of four contiguous words from memory. This signal is asserted only in read cycles due to
cache misses; it is asserted for alii-Cache miss read cycles, and for D-Cache miss read cycles if quad word refill
is currently selected.
On write transactions, the WrNear output tells the external memory system that the bus interface unit is
performing back-to-back write transactions to an address within the same 512 word page as the prior write
transaction. This signal is useful in memory systems which employ page mode or static column DRAMs, and
allows near writes to be retired quickly.

Ack

I

Acknowledge: An input which indicates to the device that the memory system has sufficiently processed the
bus transaction, and that the CPU may either terminate the write cycle or process the read data from this read
transfer.
During Coherent DMA, this input indicates that the current write transfer is completed, and that the internal
invalidation address counter should be incremented.

RdCEn

I

Read Buffer Clock Enable: An input which indicates to the device that the memory system has placed valid
data on the ND bus, and that the processor may move the data into the on-chip Read Buffer.

SysClk

0

System Reference Clock: An output from the CPU which reflects the timing of the internal processor "Sys"
clock. This clock is used to control state transitions in the read buffer, write buffer, memory controller, and bus
interface unit. This clock will either be at the same frequency as the CPU execution rate clock, or at one-half
that frequency, as selected during reset.

BusReq

I

DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus interface signals
so that they may be driven by an external master.

BusGnt

0

DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has been detected, and
that the bus is relinquished to the external master.

IvdReq

I

Invalidate Request. An input provided by an external DMA controller to request that the CPU invalidate the
Data Cache line corresponding to the current DMA write target address. This signal is the same pin as Diag(O)

CohReq

I

Coherent DMA Request. An input used by the external DMA controller to indicate that the requested DMA
operations could involve hardware cache coherency. This signal is the Rsvd(O) of the R3051.

SBrCond(3:2)
BrCond(O)

I

Branch Condition Port: These external signals are internally connected to the CPU signals CpCond(3:0).
These signals can be used by the branch on co-processor condition instructions as input ports. There are two
types of Branch Condition inputs: the SBrCond inputs have special internal logic to synchronize the inputs, and
thus may be driven by asynchronous agents. The direct Branch Condition inputs must be driven synchronously.
Note that BrCond(1) is used by the internal FPA, and thus is not available on an external pin.

BusError

I

Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error. This signal
is only sampled during read and write operations. If the bus transaction is a read operation, then the CPU will
take a bus error exception.
2889 tbl 03

5.5

10

II

IDT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION (Continued):
PIN NAME
Int(5:3)

1/0
I

DESCRIPTION
Processor Interrupt: During normal operation, these signals are logically the same as the Int(5:0) Slnt(2:0)
signals of the R3000. During processor reset, these signals perform mode initialization of the CPU, but in a
different (simpler) fashion than the interrupt signals of the R3000.
There are two types of interrupt inputs: the Sint inputs are internally synchronized by the processor, and may
be driven by an asynchronous external agent. The direct interrupt inputs are not internally synchronized, and
thus must be externally synchronized to the CPU. The direct interrupt inputs have one cycle lower latency than
the synchronized interrupts. Note that the interrupt used by the on-chip FPA will not be monitored externally.

Clkln

I

Master Clock Input: This input clock can be provided at the execution frequency of the CPU (1 x clock mode)
or at twice that frequency (2x clock mode), as selected at reset.

Reset

I

Master Processor Reset: This signal initializes the CPU. Mode selection is performed during the last cycle
of Reset.

Rsvd(4:1)

I/O

Reserved: These four signal pins are reserved for testing and for future revisions of this device. Users must not
connect these pins. Note that Rsvd(O) of the R3051 is now used for the CohReq input pin.
2889tbl04

ABSOLUTE MAXIMUM RATINGS(1, 3)
Symbol
VTERM

Rating
Terminal Voltage
with Respect
toGND

AC TEST CONDITIONS-R3081

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

o to +85

-55 to +125

°C

Case Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +155

°C

VIN

Input Voltage

-0.5 to +7.0

-0.5 to +7.0

V

Tc

Operating Case
Temperature

TSIAS

Symbol

Parameter

Min.

Max.

Unit

VIH

Input HIGH Voltage

3.0

-

V

VIL

Input LOW Voltage

-

0

V

VIHS

Input HIGH Voltage

3.5

-

V

VILS

Input LOW Voltage

-

0

V
2889 tbl 06

AC TEST CONDITIONS-RV3081
Symbol

2889 tbl 05

NOTES:

1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VIN minimum =-3.0V for pulse width less than 15ns.
VIN should not exceed Vce +0.5V.
3. Not more than one output should be shorted at a time. Duration of the short
should not exceed 30 seconds.

Parameter

Min.

Max.

Unit

VIH

Input HIGH Voltage

3.0

-

V

VIL

Input LOW Voltage

-

0

V

VIHS

Input HIGH Voltage

3.0

-

V

VILS

Input LOW Voltage

-

0

V
2889 tbl 06

OUTPUT LOADING FOR AC TESTING

VREF

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

To Device
Under Test

+1.5V

Grade

Temperature(Case)

GND

Vee

Military

-55°C to +125°C

OV

5.0±10%

Commercial

O°C to +85°C

OV

5.0±5%

Commercial

O°C to +85°C

OV

3.3±5%

2889 drw 08

2889 tbl 07

Signal

CLD

SysClk

50 pf

All Others

25 pf
2889tbl08

5.5

11

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS RV3081
COMMERCIAL TEMPERATURE RANGE(1, 2)_ (Tc =oDe to +85°e, VCC =+3.3V ±5%)
20MHz

25MHz

Symbol

Parameter

Test Conditions

Min.

VOH

Output HIGH Voltage

Vee = Min., IOH = -4mA

2.4

-

VOL

Output LOW Voltage

Vee = Min., IOL = 4mA

VIH

Input HIGH Voltage(3)

VIL

Input LOW Voltage(1)

VIHS

Input HIGH Voltage(2,3)

VILS

Input LOW Voltage(1,2)

CIN

Input Capaeitanee(4,5)

COUT

Output Capaeitanee(4,5)

V

0.4

-

0.4

V

-

2.0

-

V

-

0.8

-

0.8

V

-

2.8

-

2.8

-

V

-

0.4

0.4

V

10

-

10

pF

10

-

10

pF

375

-

425

mA

100

-

100

IlA

IlA
IlA

Operating Current

Vee = 3.3V, TA = 25°C

Input HIGH Leakage

VIH=VCC

-

Input LOW Leakage

VIL= GND
VOH = 2.4V, VOL

=0,5V

-100

-

-100

-

-100

100

-100

100

NOTES:
1.
2.
3.
4.
5.

Units

-

-

IIH

Output Tri-state Leakage

Max.

2.4

2.0

Icc

IlL

Min.

-

-

loz

Max.

=

VIL Min. -3.0V for pulse width less than 15ns. VIL should not fall below -0.5V for larger periods.
VIHS and VILS apply to Clkln and Reset.
VIH should not be held above Vee + 0.5V.
Guaranteed by design.
ALE is 12pF for SysClk values CIN and COUT for all speeds.

"",,0011

AC ELECTRICAL CHARACTERISTICS RV3081
COMMERCIAL TEMPERATURE RANGE (1, 2)_ (Tc =oDe to +85°e, VCC =+3.3V ±5%)
20MHz
Symbol

Signals

Description

25MHz

Min.

Max.

Min.

Max.

Unit

6

-

5

-

ns

t1

BusReq, Ack, BusError,
RdCEn, CohReq

Set-up to SysClk rising

t1a

AID

Set-up to SysClk falling

7

-

6

BusReq, Ack, BusError,
RdCEn, CohReq

Hold from SysClk rising

4

-

4

-

ns

t2
t2a

AID

Hold from sysClk falling

2

-

2

-

ns

t3

AID, Addr, Diag, ALE, Wr
BurstIWrNear, Rd, DataEn

Tri-state from SysClk rising

-

10

-

10

ns

t4

AID, Addr, Diag, ALE, Wr
BurstIWrNear, Rd, DataEn

Driven from SysClk falling

-

10

-

10

ns

t5

BusGnt

Asserted from sysClk rising

-

8

ns

BusGnt

Negated from sysClk falling

-

8

7

ns

t7

Wr, Rd, BurstM'rNear, AID

Valid fromsysClk rising

5

t8

ALE

Asserted from §YsClk rising

4

-

7

t6

ns

t9

ALE

Negated from SysClk failing

-

4

-

t10

AID

Hold from ALE negated(3)

2

-

2

-

ns

t11

DataEn

Asserted from sysClk falling

-

15

-

15

ns

t12

DataEn

Asserted from AID tri-state(3)

0

-

0

t14

AID

Driven from sysClk rising(3)

0

-

0

-

ns

t15

Wr, Rd, DataEn, BurstIWrNear Negated from SysClk falling
Valid from sysClk

6

-

6

Addr(3:2)

6

ns

t17

Diag

Valid from SysClk

-

7

t16

12

-

11

ns

5.5

5

ns

4

ns

4

ns

ns

ns

12

IDT79R3081 RISControl/er

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS RV3081 (cont.)
COMMERCIAL TEMPERATURE RANGE(1, 2)_ (Tc = aoc to +85°C, VCC = +3 3V +5%)
Symbol
t18
t19

Signals

Description

NO
NO

Tri-state from sysClk falling

Min.

SysClk falling to data valid

20MHz
Max.

25MHz
Min.
Max.

-

10
13

-

t20

Clkln (2x clock mode)

Pulse Width HIGH

10

t21

Clkln (2x clock mode)

Pulse Width LOW

10

-

Unit

10

ns

12

ns

8

-

ns

8

ns

t22

Clkln (2x clock mode)

Clock Period

25

250

20

250

ns

t23

Reset

Pulse Width from Vcc valid

200

200

-

IlS

t24

Reset

Minimum Pulse Width

32

32

-

tsys

t25

Reset

Set-up to SYSClk falling

6

5

ns

t26

Int

Mode set-up to Reset rising

10

t27

Int

Mode hold from Reset rising

0

t28

Slnt, SBrCond

Set-up to sysClk falling

6

t29

Slnt, SBrCond

Hold from SysClk falling

3

t30

Int, BrCond

Set-up to sysClk falling

6

t31

Int, BrCond

Hold from sysClk falling

3

-

3

-

tsys

sysClk (full frequency mode)

Pulse Width(5)

2*t22

2*t22

2*t22

2*t22

ns

t32

sysClk (full frequency mode)

Clock High Time(5)

t22-2

t22+2

t22-2

t22+2

ns

9
0
5
3
5

ns
ns
ns
ns
ns
ns

t33

SysClk (full frequency mode)

Clock LOW Time(5)

t22-2

t22+2

t22-2

t22+2

ns

tsys/2

sysClk (half frequency mode)

Pulse Width(5)4 *t22

4*t22

4*t22

4*t22

4*t22

ns

t34

sysClk (half frequency mode)

Clock HIGH Time(5)

2*t22-2

2*t22+2

2*t22-2

2*t22+2

ns

t35

SysClk (half frequency mode)

Clock LOW Time(5)

2*t22-2

2*t22+2

2*t22-2

2*t22+2

ns

8

ns

t36

ALESet-up to sysClk falling

9

t37

ALEHold from sysClk falling

2

t38

AlDSet-up to ALE falling

10

t39

AlDHold from ALE falling

2

-

t40

WrSet-up to SysClk rising

10

-

9

t41

WrHold fromsysClk rising

3

-

3

t42

Clkln (1 x clock mode)

20

16

t43

Clkln (1 x clock mode)

Pulse Width LOW(6)

20

-

16

-

t44

Clkln (1 x clock mode)

Clock Period(6)

50

50

40

50

ns

All outputs

Timing deration for loading

-

1

-

1

nsl

tderate

Pulse Width HIGH(6)

I ()vpr

r., n(3. 4)

2
9
2

ns
ns
ns
ns
ns
ns
ns

?5nF

NOTES:
2889tbl11
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.
3. Guaranteed by design.
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
5. In 1x clock mode, t22 is replaced by t44/2.
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns.

5.5

13

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS RV3081
COMMERCIAL TEMPERATURE RANGE(1, 2)_ (Tc = O°C to +85°C, VCC = +3.3V ±5%)
33MHz

40MHz

Symbol

Parameter

Test Conditions

Min.

VOH

Output HIGH Voltage

Vee = Min., 10H = -4rnA

2.4

-

VOL

Output LOW Voltage

Vee = Min., 10L = 4rnA

VIH

Input HIGH Voltage(3)

Max.

Min.

Max.

Units

2.4

-

V

-

0.4

-

0.4

V

2.0

-

2.0

-

V

VIL

Input LOW Voltage(1)

-

-

0.8

-

0.8

V

VIHS

Input HIGH Voltage(2,3)

-

2.8

-

2.8

-

V

VILS

Input LOW Voltage(1,2)

-

-

0.4

V

Input Capacitance(4,5)

-

10

pF

Output Capacitance(4,5)

-

10

COUT

-

0.4

CIN

10

10

pF

-

525

-

600

rnA

-

100

-

100

IlA

lee

Operating Current

IIH

Input HIGH Leakage

Vee = 3.3V, TA = 25°C
VIH =

vce

IlL

Input LOW Leakage

VIL= GND

-100

-

-100

-

IlA

loz

Output Tri-state Leakage

VOH = 2.4V, VOL = 0.5V

-100

100

-100

100

IlA

NOTES:
1.
2.
3.
4.
5.

VIL Min. = -3.0V for pulse width less than 15ns. VIL should not fall below -0.5V for larger periods.
VIHS and VILS apply to Clkln and Reset.
VIH should not be held above Vee + 0.5V.
Guaranteed by design.
ALE is 12pF for SysClk values C'N and COUT for all speeds.

AC ELECTRICAL CHARACTERISTICS RV3081
COMMERCIAL TEMPERATURE RANGE (1, 2)_ (Tc =O°C to +85°C, VCC =+3.3V ±5%)
40MHz

33MHz
Symbol
t1

Signals

Description

Min.

Max.

Min.

4

-

3

Set-up to SYSClk falling

5

-

Hold from SysClk rising

3

-

BusReq, Ack, BusError,
RdCEn, CohReq3

Set-up to SysClk rising

t1a

AID

t2

BusReq, Ack, BusError,
RdCEn, CohReq

Max.

Unit

-

ns

4.5

-

ns

3

-

ns

1

t2a

AID

Hold from sysClk falling

1

-

-

ns

t3

AID, Addr, Dia!1!'LE, Wr
BurstIWrNear, Rd, DataEn

Tri-state from SysClk rising

-

10

-

10

ns

t4

AID, Addr, Diag, ALE, Wr
BurstlWrNear, Rd, DataEn

Driven from SysClk falling

-

10

-

10

ns

-

6

5

ns

5

ns

3.5

ns

3

-

3

ns

3

-

3

ns
ns

t5

BusGnt

Asserted from SysClk rising

t6

BusGnt

Negated from sysClk falling

t7

Wr, Rd, Burst/WrNear, AID

Valid from sysClk rising

t8

ALE

Asserted from sysClk rising

t9

ALE

Negated from sysClk falling

-

t10

AID

Hold from ALE negated(3)

1.5

-

1.5

-

t11

DataEn

Asserted from sysClk falling

-

13

-

12

ns

t12

Data En

Asserted from AID tri-state(3)

0

0

AID

Driven from sysClk rising(3)

-

ns

t14

-

t15

Wr, Rd, Data En , BurstIWrNear Negated from sysClk falling

5

-

4

ns

t16

Addr(3:2)

Valid from SysClk

-

5

ns

Diag

Valid from SysClk

-

10

-

4.5

t17

9

ns

0

5.5

6
4

0

ns

14

IDT79R3081 RISContro/Jer

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS RV3081 (cont.)
COMMERCIAL TEMPERATURE RANGE(1, 2)_
Symbol
t18

Signals
AID

t19

AID

t20

Clkln (2x clock mode)

t21

(Tc

Description

=O°C to +85°C, VCC =+3.3V ±5%)
Min.

-

Pulse Width HIGH

Clkln (2x clock mode)

t22
t23

33MHz
Max.

40MHz
Min.
Max.

Unit

8

ns

11

-

10

ns

6.5

-

5.6

-

ns

Pulse Width LOW

6.5

-

5.6

-

ns

Clkln (2x clock mode)

Clock Period

15

250

12.5

250

Reset

Pulse Width from Vcc valid

200

-

200

Tri-state from sysClk falling
IsysClk falling to data valid

9

ns

t24

Reset

Minimum Pulse Width

32

-

32

t25

Reset

Set-up to SysClk falling

4

-

3

t26

Mode set-up to Reset rising

8

-

7

t27

/iii
/iii

Mode hold from Reset rising

0

-

0

t28

Slnt, SBrCond

Set-up to _sysClk falling

4

3

t29

Slnt, SBrCond

Hold from sysClk falling

2

2

-

ns

t30

Int, BrCond

Set-up to SysClk falling

4

3

-

ns

t31

Int, BrCond

Hold from sysClk falling

2

-

-

2

-

ns

tsys

SysClk (full frequency mode)

Pulse Width(5)

2*t22

2*t22

2*t22

2*t22

ns

t32

S1sClk (full frequency mode)

Clock High Time(5)

t22-1

t22+1

t22-1

t22+1

ns

t33

sysClk (full frequency mode)

Clock LOW Time(5)

t22-1

t22+1

t22-1

t22+1

ns

tsysl2

sysClk (half frequency mode)

Pulse Width(5)4*t22

4*t22

4*t22

4*t22

4*t22

ns

JI.S

tsys
ns
ns
ns
ns

t34

sysClk (half frequency mode)

Clock HIGH Time(5)

2*t22-1

2*t22+1

2*t22-1

2*t22+1

ns

t35

sysClk (half frequency mode)

Clock LOW Time(5)

2*t22-1

2*t22+1

2*t22-1

2*t22+1

ns

t36

ALESet-up to SysClk falling

7

-

6

-

ns

t37

ALEHold from sysClk falling

1

-

1

-

ns

t38

AlDSet-up to ALE falling

8

8

AlDHold from ALE falling

1

-

ns

t39

-

t40

WrSet-up to sysClk rising

8

7

WrHold from sysClk rising

3

t42

Clkln (1 x clock mode)

Pulse Width HIGH(6)

13

11(6)

-

ns

t41

-

t43

Clkln (1 x clock mode)

Pulse Width LOW(6)

13

-

11(6)

-

ns

t44

Clkln (1 x clock mode)

Clock Period(6)

30

50

25

50

ns

All outputs

Timing deration for loading

-

1

1

nsl

tderate

, "'lPr

r., ,.,(3,4)

1

3

-

ns

ns
ns

?~nF

NOTES:
2889tblll
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.
3. Guaranteed by design.
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
5. In 1x clock mode, t22 is replaced by t44/2.
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns

5.5

15

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS R3081
COMMERCIAL TEMPERATURE RANGE - (Tc =oDe to +85°C, Vcc =+5.0V ±5%)
25MHz

20MHz
Symbol

Parameter

VOH

Output HIGH Voltage

Vee = Min., 10H = -4rnA

Test Conditions

Min.

VOL

Output LOW Voltage

Vee

VIH

Input HIGH Voltage(3)

VIL

Input LOW Voltage(1)

VIHS

Input HIGH Voltage(2,3)

VILS

Input LOW Voltage(1,2)

=Min., 10L = 4rnA

-

3.5

-

Min. Max.
3.5

-

Min. Max. Units
3.5

-

V

-

0.4

-

0.4

-

0.4

-

0.4

V

-

-

2.0

-

2.0

-

2.0

-

2.0

-

V

-

0.8

-

0.8

-

0.8

-

0.8

-

0.8

V

3.0

-

3.0

-

3.0

-

3.0

-

3.0

-

V

-

0.4

0.4

V

10

pF

10

pF

625

825

rnA

100

-

100

-

0.4

100

-

0.4

525

-

0.4

475

-

100

IlA

-

IlA

Operating Current

Vee = 5V, TA = 25°C

Input HIGH Leakage

VIH = VCC

-

IlL

Input LOW Leakage

VIL= GND

loz

Min. Max.

0.4

lee

Output Capacitance(4)

-

50MHZ

-

IIH

Input Capaeitanee(4)

COUT

3.5

40MHz

2.0

-

CIN

Max. Min. Max.

3.5

33.33MHz

Output Tri-state Leakage VOH = 2.4V, VOL

10
10

-

-100

=

0.5V -100

-100

100 -100

10
10

-

-100

100

-100

NOTES:
1. VIL Min. = -3.0V for pulse width less than 15ns. VIL should not fall below -O.5V for larger periods.
2. VIHS and VILS apply to Clkln and Reset.
3. VIH should not be held above Vee + O.5V.
4. Guaranteed by design.

5.5

10
10

100

10
10
700
100

-100

-

-100

-100

100

-100 100

IlA

"",,,10'

16

iii

IDT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS R3081
COMMERCIAL TEMPERATURE RANGE (1, 2) (20, 25MHz)-(Tc =aoe to +85°e, Vcc
20MHz
Symbol

Signals

Description

t1

BusReq, Ack, BusError,

Set-up to~rising
RdCEn, CohReq

t1a

=+5.av ±5%)
25MHz

Min.

Max.

Min.

Max.

Unit

6

-

5

-

ns

6

-

ns

4

-

ns

ND

Set-up to sysClk falling

7

t2

BusReq, Ack, BusError,

Hold from SysClk rising
RdCEn, CohReq

4

-

t2a

ND

Hold from SysClk falling

2

-

2

-

ns

t3

ND, Addr, Diag, ALE, Wr

Tri-state from ~Clk rising
Burst/WrNear, Rd, DataEn

-

10

-

10

ns

t4

ND, Addr, Diag, ALE, Wr

Driven from SysClk falling
Burst/WrNear, Rd, DataEn

-

10

-

10

ns

t5

BusGnt

Asserted from sysClk rising

ns

Negated from SysClk falling

7

ns

t7

Wr,

Valid from SYSClk rising

ta

ALE

4

t9

ALE

Negated from sysClk falling

-

-

7

BusGnt

-

a

t6

4

-

4

ns

t10

AID

Hold from ALE negated

2

-

2

-

ns

t11

DataEn

Asserted from sysClk falling

-

15

-

15

ns

t12

DataEn

Asserted from AID tri-state(3)

0

0

-

ns

-

6

ns

6

ns

11

ns

10

-

10

ns

Rd, BurstlWrNear, AID

Asserted from SysClk rising

a
5

5

ns

4

ns

t14

AID

Driven from SysClk rising(3)

0

-

t15

Wr, Rd, DataEn, Burst/WrNear

Negated from _~Clk fallil1fl

-

7

t16

Addr(3:2)

Valid from§y"sClk

-

6

t17

Diag

Valid from sysClk

12

t1a

AID

Tri-state from sysClk falling

t19

AID

SysClk falling to data valid

-

13

-

12

ns

t20

Clkln (2x clock mode)

Pulse Width HIGH

10

-

a

ns

t21

Clkln (2x clock mode)

Pulse Width LOW

10

-

a

-

t22

Clkln (2x clock mode)

Clock Period

25

250

20

250

ns

t23

Reset

Pulse Width from Vee valid

200

200

t24

Reset

Minimum Pulse Width

32

-

tsys

0

ns

ns

t25

Reset

Set-up to sysClk falling

6

5

t26

Int

Mode set-up to Reset rising

10

-

-

9

-

ns

t27

Int

Mode hold from Reset rising

0

-

0

ns

t2a

Slnt, SBrCond

Set-up to sysClk falling

6

5

t29

Slnt, SBrCond

Hold from sysClk falling

3

t30

Int, BrCond

Set-up to sysClk falling

6

5

t31

Int, BrCond

Hold from SysClk falling

3

-

-

3

-

ns

tsys

sysClk (full frequency mode)

Pulse Width(5)

2*t22

2*t22

2*t22

2*t22

ns

t32

sYsClk (full frequency mode)

Clock HIGH Time(5)

t22-2

t22+2

t22-2

t22+2

ns

32

3

~s

ns

ns
ns
ns

NOTES:
2889 tbl10
1. All timings referenced to 1.5V. All timings measured with respect to a 2.Sns rise and fall time.
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.
3. Guaranteed by design.
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 2SpF over the specified test load condition.
5. In 1x clock mode, t22 is replaced by t44/2.
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40MHz and SOMHz.
7. When using the Reduced Frequency feature, the minimum allowed internal CPU speed is O.S MHz.

5.5

17

IDT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS R3081 (cant.)
COMMERCIAL TEMPERATURE RANGE(1, 2) (20, 25MHz)- (Tc =ooe to +85°e, VCC =+5.0V ±5%)
20MHz
Symbol

Signals

Description

25MHz

Min.

Max.

Min.

Max.

Unit

t22-2

t22+2

t22-2

t22+2

ns

4't22

4't22

4't22

4't22

ns

Clock HIGH Time(S)

2't22-2

2't22+2

2't22-2

2't22+2

ns

sysClk (half frequency mode)

Clock LOW Time(S)

2't22-2

2't22+2

2't22-2

2't22+2

ns

ALE

Set-up to SysClk falling

9

8

t37

ALE

Hold from sysClk falling

2

t38

AID

Set-up to ALE falling

10

t39

AID

Hold from ALE falling

2

t40

Wr

Set:up to sysClk rising

10

t41

Wr

3
16

t33

sysClk (full frequency mode)

Clock LOW Time(S)

tsys/2

sysClk (half frequency mode)

Pulse Width

t34

sysClk (half frequency mode)

t35
t36

(5)

t43

Clkln (lx clock mode)

Pulse Width LOW(6)

20

-

16

-

t44

Clkln (1 x clock mode)

Clock Period(6)

50

50

40

SO

ns

Timing deration for loading
over CLD(3, 4)

-

1

-

1

nsl
25pF

t42

tderate

Clkln (1 x clock mode)

All outputs

Hold from sysClk rising

3

-

Pulse Width HIGH(6)

20

-

2
9
2
9

ns
ns
ns
ns
ns
ns
ns
ns

NOTES:
2889 tblll
1. All timings referenced to 1.SV. All timings measured with respect to a 2.Sns rise and fall time.
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.
3. Guaranteed by design.
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
S. In lx clock mode, t22 is replaced by t44/2.
6. In lx clock mode, the design guarantees that the input clock rise and fall times can be as long as Sns, 3ns for 40MHz and SOMHz.
7. When using the Reduced Frequency feature, the minimum allowed internal CPU speed is O.S MHz.

AC ELECTRICAL CHARACTERISTICS R3081
COMMERCIAL TEMPERATURE RANGE (1, 2) (33, 40MHz)- (Tc =ooe to +85°e, VCC
33MHz

=+5.0V ±5%)
40MHz

Min.

Max.

Min.

Set-up to SysClk rising

4

-

3

-

ns

AID

Set-up to sysClk falling

S
3

3

-

ns

Hold from SysClk rising

-

4.S

BusReq, Ack, BusError,
RdCEn, CohReq

1

-

1

Symbol

Signals

tl

BusReq, Ack, BusError,
RdCEn, CohReq

tla
t2
t2a

Description

Max.

Unit

ns

AID

Hold from SysClk falling

-

ns

t3

AID, Addr, Diag, ALE, Wr
BurstlWrNear, Rd, DataEn

Tri-state from SysClk rising

-

10

-

10

ns

t4

AID, Addr, Dia(h!.LE, Wr
BurstlWrNear, Rd, DataEn

Driven from SysClk falling

-

10

-

10

ns

t5

BusGnt

Asserted from sysClk rising

S

ns

BusGnt

Negated from SysClk falling

-

6

t6

6

S

ns

t7

Wr, Rd, BurstlWrNear, AID

Valid from sysClk riSing

3.S

ns

3

ns

-

t8

ALE

Asserted from SysClk rising

-

t9

ALE

Negated from SVsClk falling

-

3

-

tl0

AID

Hold from ALE negated

1.5

-

1.S

tll

DataEn

Asserted from sysClk falling

-

13

-

12

ns

t12

DataEn

Asserted from AID tri-state(3)

0

-

0

ns

t14

AID

Driven from SysClk rising(3)

0

-

0

-

t15

1M

Rd, DataEn BurstlWrNear Neqated from SVsClk fallinq

-

S

-

4
3

3

4

ns
ns

ns
ns
2B89tblll

5.5

18

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS R3081 (cont.)
COMERCIAL TEMPERATURE RANGE (1, 2) (33, 40MHz)- (Tc =DoC to +85°C, Vcc

=+5.0V ±5%)

33MHz
Symbol

Signals

Description

40MHz

Min.

Max.
5
10

t16

Addr(3:2)

Valid from sysClk

t17

Oiag

Valid from SysClk

t18

Tri-state from sysClk falling

t19

NO
NO

-

SysClk falling to data valid

-

11

t20

Clkln (2x clock mode)

Pulse Width HIGH

6.5

t21

Clkln (2x clock mode)

Pulse Width LOW

6.5

t22

Clkln (2x clock mode)

Clock Period

t23

Reset

Pulse Width from Vee valid

t24

Reset

Minimum Pulse Width

t25

Reset

Set-up to sysClk falling

t26

Int

Mode set-up to Reset rising

8

t27

Int

Mode hold from Reset rising

t28

Slnt, SBrCond

Set-up to sysClk falling

Min.

Max.

Unit

-

4.5

ns

9

ns

-

5.6

-

ns

5.6

-

ns

15

250

12.5

250

200

-

200

32

-

32

-

4

3

0

-

4

-

3

3

9

8

ns

10

ns

ns
IlS

tsys
ns

-

ns

-

ns

ns

2

2*t22

ns
ns

7
0

t29

Slnt, SBrCond

Hold from SysClk falling

2

t30

Int, BrCond

Set-up to sysClk falling

4

t31

Int, BrCond

Hold from sysClk falling

2

-

tsys

SYsClk (full frequency mode)

Pulse Width(5)

2*t22

2*t22

2*t22

2

ns

ns

ns

t32

sysClk (full frequency mode)

Clock HIGH Time(5)

t22-1

t22+1

t22-1

t22+1

t33

SysClk (full frequency mode)

Clock LOW Time(5)

t22-1

t22+1

t22-1

t22+1

ns

tsys/2

SYsClk (half frequency mode)

Pulse Width(5)

4*t22

4*t22

4*t22

4*t22

ns

134

SysClk (half frequency mode)

Clock HIGH Time(5)

2*t22-1

2*122+1

2*t22-1

2*122+1

ns

t35

SYsClk (half frequency mode)

Clock LOW Time(5)

2*t22-1

2*t22+1

2*t22-1

2*t22+1

ns

t36

ALE

Set-up to sysClk falling

7

-

6

ns

t37

ALE

Hold from sysClk falling

1

-

1

-

t38

Set-up 10 ALE falling

8
1

t40

Wr

Set-up to ~sClk rising

8

-

ns

Hold from ALE falling

t41

Wr

Hold from sysClk rising

3

3

-

ns

t42

Clkln (1 x clock mode)

Pulse Width HIGH(6)

13

-

8

t39

NO
ND

11(6)

-

ns

11(6)

1
7

ns

ns
ns

t43

Clkln (1 x clock mode)

Pulse Width LOW(6)

13

-

-

ns

t44

Clkln (1 x clock mode)

Clock Period(6)

30

50

25

50

ns

All outputs

Timing deration for loading over CLD(3, 4)

-

1

-

1

nsf
25pF

tderate

NOTES:
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.
2889 tblll
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.
3. Guaranteed by design.
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
5. In 1x clock mode, t22 is replaced by t44/2.
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40 and 50MHz.
7. When using the Reduced Frequency feature, the minimum allowed internal CPU speed is 0.5 MHz.

5.5

19

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS R3081
COMMERCIAL TEMPERATURE RANGE (1, 2) (50MHz)- (Tc = O°C to +85°C, Vcc = +5.0V ±5%)
50MHz
Symbol

Signals

t1

BusReq, Ack, BusError,

t1a
t2

Description

Min.

Max.

Unit

Set-up to~rising
RdCEn, CohReq

5

-

ns

AID

Set-up to sysClk falling

6

-

ns

BusReq, Ack, BusError,

Hold from SysClk rising
RdCEn, CohReq

4

-

ns

2

AID

Hold from ~sClk fallirlg

-

ns

t3

AiD, Addr, Diag, ALE, Wr

Tri-state from SysClk rising
BurstlWrNear, Rd, DataEn

-

10

ns

t4

AID, Addr, Diag, ALE, Wr

Driven from SysClk falling
BurstlWrNear, Rd, DataEn

-

10

ns
ns

t2a

t5

BusGnt

Asserted from sysClk rising

-

7

t6

BusGnt

Negated from sysClk falling

7

ns

t7

Wr, Rd, Burst/WrNear, AID

Valid from SysClk rising

5

ns

t8

ALE

Asserted from sysClk rising

-

4

ns

t9

ALE

Negated from sysClk falling

-

4

ns

t10

AiD

Hold from ALE negated

1.5

-

ns

t11

DataEn

Asserted from sysClk falling

-

15

ns

t12

DataEn

Asserted from AID tri-state(3)

0

-

ns

t14

AiD

Driven from sysClk rising(3)

0

-

ns

t15

Wr, Rd, DataEn, BurstlWrNear Negated from sysClk falling

t16

Addr(3:2)

Valid from sysClk

t17

Diag

Valid from sysClk

t18

AiD

t19

AiD

Tri-state from sysClk falling

-

10

ns

sysClk falling to data valid

-

12

ns

6
6

ns

11

ns

t20

Clkln (2x clock mode)

Pulse Width HIGH

N/A(8)

t21

Clkln (2x clock mode)

Pulse Width LOW

N/A(8)

ns

t22

Clkln (2x clock mode)

Clock Period

N/A{7.8)

ns

t23

Reset

Pulse Width from Vec valid

t24

Reset

Minimum Pulse Width

200
32

II

ns

ns

-

tsys

ns

IlS

t25

Reset

Set-up to SysClk falling

5

t26

Int

Mode set-up to Reset risin[

9

-

t27

int

Mode hold from Reset rising

0

t28

Slnt, SBrCond

Set-up to sysClk falling

5

t29

Slnt, SBrCond

Hold from sysClk falling

3

t30

Set-up to SysClk falling

5

t31

int, BrCond
int, BrCond

Hold from sysClk falling

3

-

tsys

SysClk (full frequency mode)

Pulse Width(5)

N/A (8)

N/A(8)

ns

t32

SVsClk (full frequency mode)

Clock HIGH Time(5)

N/A (8)

N/A (8)

ns

ns

ns
ns
ns
ns
ns

N/A(8)
N/A(8)
Clock LOW Time(5)
t33
SVsClk (full frequency mode)
ns
~~~!ltbl
NOTES.
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.
3. Guaranteed by design.
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
5. In 1x clock mode, t22 is replaced by t44/2.
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40MHz and 50MHz.
7. When using the Reduced Frequency feature, the minimum allowed internal CPU speed is 0.5 MHz.
8. For the 50MHz version, 1x Clock Mode and half-frequency bus mode only.

5.5

20

IDT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS R3081 (cent.)
COMERCIAL TEMPERATURE RANGE (1,2) (50MHz)- (Tc =O°C to +85°C, VCC =+5.0V ±5%)
50MHz
Symbol

Signals

Description

Min.

Max.

Unit

tsys/2

SysClk (half frequency mode)

Pulse Width(5)

2't44

2't44

ns

t34

sysClk (half frequencymode)

Clock HIGH Time(5)

t44-1

t44+1

ns

t35

sysClk (half frequency mode)

Clock LOW Time(5)

t44-1

t44+1

ns
ns

t36

ALE

Set-up to sysClk falling

8

t37

ALE

Hold from sysClk falling

2

t38

AID

Set-up to ALE falling

9

t39

AID

Hold from ALE falling

2

-

t40

Vir

Set·up to sysClk rising

9

-

ns

t41

Wr

Hold from sysClk rising

ns

ns
ns
ns

t42

elkin (1 x clock mode)

Pulse Width HIGH(6)

3
16(6)

t43

elkin (1 x clock mode)

Pulse Width LOW(6)

16(6)

-

t44

elkin (1 x clock mode)

Clock Period(6)

40

50

ns

All outputs

Timing deration for loading over CLD(3, 4)

-

1

nsl

tderate

ns
ns

25pF
NOTES:
1, All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.
3. Guaranteed by design.
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
5. In 1x clock mode, t22 is replaced by t44/2.
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40MHz and 50MHz.
7. When using the Reduced Frequency feature, the minimum allowed internal CPU speed is 0.5 MHz.
8. For the 50 MHz version, 1x Clock Mode and half-frequencybus mode only.

5.5

21

IDT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS R3081
MILITARY TEMPERATURE RANGE- (Td5) =-55°C to +125°C

=

VCC +5.0V +10%)
20MHz

Symbol

Parameter

Test Conditions

Min.

VOH

Output HIGH Voltage

Vee = Min., 10H = -4mA

2.4

-

VOL

Output LOW Voltage

Vee = Min., 10l = 4mA

VIH

Input HIGH Voltage(3)

Vil

Input LOW Voltage(1)

VIHS

Input HIGH Voltage(2,3)

VllS

Input LOW Voltage(1,2)

CIN

Input Capaeitanee(4)

-

COUT

Output Capacitanee(4)

-

Max.

25MHz

Min.

Max.

Units

2.4'

-

V

-

0.4

-

0.4

V

2.0

-

2.0

-

V

-

0.8

-

0.8

V

2.8

-

2.8

-

V

-

0.4

-

0.4

V

12

-

12

pF

12

12

pF

550

-

650

mA

100

-

100

IlA

Icc

Operating Current

Vee = 5.0V, TA = 25°C

IIH

Input HIGH Leakage

VIH=VCC

-

III

Input LOW Leakage

Vll= GND

-100

-

-100

102

Output Tri-state Leakage

VOH = 2.4V, VOL = 0.5V

-100

100

-100

-

IlA

100

IlA

NOTES:
1. VIL Min. = -3.0V for pulse width less than 15ns. VIL should not fall below -0.5V for larger periods.
2. VIHS and VILS apply to Clkln and Reset.
3. VIH should not be held above Vee + 0.5V.
4. Guaranteed by design.
5. Case Temperatures are "instant on."

AC ELECTRICAL CHARACTERISTICS R3081
MILITARY TEMPERATURE RANGE (1, 2)_ (Tc(7) =-55°C to +125°C, VCC =+5.0V ±10%)
20MHz

25MHz
Max.

Unit

tl

BusReq, Ack, BusError,
RdCEn, CohReq

Set-up to SysClk rising

6

-

5

-

ns

tla

AiD

Set-up to sysClk falling

7

-

ns

BusReq, Ack, Bus Error,
RdCEn, CohReq

Hold from SysClk rising

4

-

6

t2

4

-

ns

Symbol

Signals

Description

Min.

Max.

Min.

t2a

AiD

Hold from SVsClk falling

2

-

2

-

ns

t3

AiD, Addr, Dia~LE, Wr
BurstlWrNear, Rd, DataEn

Tri-state from SysClk rising

-

10

-

10

ns

t4

AID, Addr, Dia~LE, Wr
BurstlWrNear, Rd, DataEn

Driven from SysClk falling

-

10

-

10

ns

t5

BusGnt

Asserted from SysClk rising

-

8

-

7

ns

t6

BusGnt

Negated from sYsClk falling

-

8

7

ns

t7

Wr, Rd, BurstIWrNear, AiD

Valid from SVsClk rising

5

5

ns

t8

ALE

Asserted from SVsClk rising

-

4.5

4.5

ns

t9

ALE

Negated from sYsClk falling

-

4

-

4

ns

tl0

AiD

Hold from ALE negated(3)

1.5

-

1.5

-

ns

tll

DataEn

Asserted from sysClk falling

-

15

-

15

ns

t12

DataEn

Asserted from AID tri-state(3)

0

Driven from sysClk rising(3)

0

-

ns

AiD

-

0

t14
t15

Wr, Rd, DataEn, BurstlWrNear Negated from sYsClk falling

-

7

6

ns

t16

Addr(3:2)

Valid from SysClk

6

6

ns

t17

Diag

Valid from SysClk

-

-

12

-

11

ns

5.5

0

ns

22

1DT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS R3081 (cont.)
MILITARY TEMPERATURE RANGE(1, 2)_ (Tc(7) =-55°C to +125°C , VCC =+5 OV -+10%)
20MHz
Symbol

Signals

Description

118

AID

Tri-slale from SysClk falling

t19

AID

sysClk falling to data valid

t20

Clkln (2x clock mode)

Pulse Width HIGH

10

t21

Clkln (2x clock mode)

Pulse Width LOW

10

t22

Clkln (2x clock mode)

Clock Period

25

t23

Reset

Pulse Width from Vcc valid

200
32

Min.

25MHz
Max.

Min.

Max.

-

10

10

ns

-

13

-

12

ns

-

8
8

-

ns

250

20

250

-

200

-

Ils

32

-

tsys

ns

3

-

ns

Unit

ns
ns

t24

Reset

Minimum Pulse Width

t25

Reset

Set-up 10 sysClk falling

6

126

Mode set-up to Reset rising

10

127

iiii
iiii

Mode hold from Resel rising

0

128

Slnl, SBrCond

Sel-up 10 sysClk falling

6

t29

Slnt, SBrCond

Hold from sysClk falling

3.5

t30

Int, BrCond

Set-up 10 SysClk falling

6

-

131

iiii, BrCond

Hold from sysClk falling

3.5

-

3

-

Isys

sysClk (full frequency mode)

Pulse Widlh(5)

2*122

2*122

2*122

2*122

ns

132

sysClk (full frequency mode)

Clock High Time(5)

122-2

t22+2

t22-2

122+2

ns

t22-2

t22+2

t22-2

t22+2

ns

4*122

4*122

4*t22

4*t22

ns

5

9
0
5

5

ns

ns
ns
ns

ns

t33

sysClk (full frequency mode)

Clock LOW Time(5)

tsys/2

sysClk (half frequency mode)

Pulse Widlh(5)

134

. SYsClk (halffr~uencymode)

Clock HIGH Time(5)

2*122-2

2*t22+2

2*122-2

2*122+2

ns

t35

sysClk (half frequency mode)

Clock LOW Time(5)

2*t22-2

2*t22+2

2*t22-2

2*t22+2

ns

t36

ALE

Sel-up 10 SysClk falling

9

-

8

-

ns

t37

ALE

Hold from sysClk falling

2

-

2

-

ns

138

AID

Sel-~ to ALE falling

10

-

9

-

ns

t39

AID

Hold from ALE falling

2

2

-

ns

140

1M

Set-up to sysClk rising

10

-

9

-

ns

t41

Wr

Hold from SysClk rising

3

-

3

-

ns

142

Clkln (1 x clock mode)

Pulse Width HIGH(6)

20

-

16

ns

143

Clkln (1 x clock mode)

Pulse Width LOW(6)

20

-

16

-

t44

Clkln11 x clock mode)

Clock Period(6)

50

50

40

50

ns

All outputs

Timing deration for loading
over CLD(3, 4)

-

1

-

1

nsl

Iderate

ns

25pF

NOTES:

2889 tbl11

1.
2.
3.
4.

All timings referenced 10 1.5V. All timings measured with respect to a 2.5ns rise and fall time.
The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.
Guaranteed by design.
This parameter is used to derale Ihe AC timings according 10 the loading of the system. This parameter provides a deration for loads over the specified
lest condition; that is, the deralion factor is applied for each 25pF over the specified test load condition.
5. In 1x clock mode, t22 is replaced by 144/2.
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns.
7. Case Temperatures are "instant on."

5.5

23

IDT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

00- r:::c;; a en
C\I
C\I
C\I
0' 0' 0' 0' 0'

(0

C')

~

~

~

~

~

>

0
0

>

LO
C\I

C\I

(/)
(/)

~

c;)

C\I

C\I

N

C\I

~

~

~

~

~

a en
,....

N

0' 0' 0' 0' 0' 0'
~

C\I

0
0

>

(/)
(/)

>

00,.... r:::-

(0

~

~

~

~

~

84
Vss

LO
,....

0' 0' 0' 0' 0' 0'
~

75
Vss

12

Vee

Vee
Clkln

NO(14)

Rsvd(4)

NO(13)

Rsvd(3)

NO(12)

Rsvd(2)

NO(11)

Rsvd(1)

NO(10)

CohReq

NO(9)
Vee

Int(5)
84-Pin MQUAD/PLCC

Vss

Vss

Top View

Vee

NO(8)

Int(4)

NO(7)

Int(3)

NO(6)

Slnt(2)

NO(5)

Slnt(1)

NO(4)

Slnt(O)

NO(3)

SBrCond(3)

Vss

SBrCond(2)

Vee

NC

NO(2)

Vss

NO(1)
54

Vee

a

:0c
0

()

C5

I~

If I~ II

Ij Ii Ii

(/)
(/)

>

0
0

>

Ii

I~ I~

LU

...J



0
0

>

g §:
-0

"'C

 >

ID LO

~

0-

~

~

~

C\J

~

C\J

e;;- N .C\J

0~

~

0

~

~

0

~

0;0C\J

()
()

>

(/)
(/)

>

0~

~

co

r::::- ID LO
.-

0- 0- 0- 0~

~

~

~

Vss

Vss
Vee

Vee
Clkln

AlD(14)

Rsvd(4)

AlD(13)

Rsvd(3)

AlD(12)

Rsvd(2)

AlD(11)

Rsvd(1)

AlD(10)

CohReq

AlD(9)
Vee

Int(5)
84-Pln FD

Vss

Vss

Top View
Vce

AID (8)

Int(4)

AID (7)

Int(3)

AID (6)

Slnt(2)

AlO(5)

Slnt(1)

AlD(4)

Slnt(O)

AID (3)

SBrCond(3)

Vss

SBrCond(2)

Vee

AID (2)

NC

AlO(1)

Vss
64
63

Vec

0-

:0c:
0
()

cD

If I~ II
I~

I~

I~ Ii

(/)
(/)

>

()
()

>

Ii

I~

lit

UJ

...J

oct:

If
.......

0Cl
ca
0

(/)
(/)

Cl >
ca

0

()
()

>

~

€ m

-0 "0
-0

"0

oct:

AlO(O)

oct:

(I)

Z

~~

::I

III

NOTE:
Reserved Pins must not be connected.

5.5

25

1DT79R30Bl RISController

NC
NC
Vss
Vee
AlO(14)
AlO(13)
AlO(12)
AlO(11)
AlO(10)
AlO(9)
Vee
Vss
AlO(8)
AlO(7)
AlO(6)
AlO(5)
AlO(4)
NO(3)
Vss
Vee
NO(2)
AlO(1)
NO(O)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

2524232221 20 19 18 17 16 15 14 13 12 11 10 9
26

RV3081 Y
100-Pin
TQFP
(Cavity Up)
Top View

NC
NC
Vss
Vee
Clkln
RSVO(4)
RSVO(3)
RSVO(2)
RSVO(1)
CohReQ
Int(5)
Vss
Vee
Int(4)
Int(3)
Slnt(2)
Slnt(1 )
Slnt(O)
SBrCond(3)
SBrCond(2)

NC
Vss
Vee
Vss
Vee

NC
NC

2905 drw06

5.5

26

IDT79R3081 RISController

Clkln

MILITARY AND COMMERCIAL TEMPERATURE RANGES

~-t42

_*____- t
t43

t33

SysClk

:K~--~

t32

1

tsys

2889 drw 12

Figure 8 (a). R3081 Clocking (lx clock Input mode, full frequency bus)

r -------f
"

t44

Clkln

SysClk

{~

_ _ _t_42_ _

----'1:

- Ij~

t43

------/

:K

t34

t35

tsysl2

2889 drw 13

Figure 8 (b). R3081Clocking (lx clock Input mode, half-frequency bus)

t22

Clkln

SysClk

k J
t20

-1

t21

r

/

\

\
}:

t34

/

\

t35

tsys/2
2889 drw 14

Figure 8 (c). R3081 Clocking (2x clock Input mode, half-frequency bus)

t22

Clkln

SysClk

k. . ___ --t~'j
----'1:

t21

t2_0_ _

t32

;r

----~/

"
-------f

:K
tSYS

t33

2889 drw 15

Figure 8 (d). R3081 Clocking (2x clock Input mode, full-frequency bus)

5.5

27

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Vee

Clkln ______________________________________________;1

Reset

t23

----------------------------------------------+--------------------+~-------------'
2889 drw 16

Figure 9. Power-On Reset Sequence

Clkln

Reset

'f:___________________________

)r(J~(----------------------------------~=t' ""OM"

t2_4____

Figure 10. Warm Reset Sequence

~~

SysClk

'--------------------

~cl

~L
------------------------------------------------------------'/

~

Int(n)

t26

t25

¥

...--_~I

t27

2889 drw 18

Figure 11. Mode Selection and Negation of Reset

5.5

28

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SysClk

Rd

ND(31:0)

Addr(3:2)

ALE

DataEn

Burst

RdCEn

Ack

Diag(l)

Miss Address(3)

Diag(O)

Miss Address(2)

Start
Read

Turn
Bus

Ack?

Ack?

Ack/
RdCen

Sample
Data

End
Read

2889 drw 19

Figure 12. Single Datum Read in R3081

5.5

29

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SysClk

Rd

AlD(31 :0)

Addr(3:2) - - - - - 1 - 1 1 '----,,.-.,..-.--r---~ I ' - - - - r - - - , . - ' I' '---,.---,.-' I ' - - - r - - - r - - - - r - - J

ALE _ _ _ _ _1-1

DataEn

Burst

RdCEn

Ack

Diag(1) - - - - - - t - - J

Diag(O) ----~f--'
Start
Read

Turn
Bus

AckJ
RdCen

Sample RdCEn
Data

Sample
Data

RdCEn

Sample
Data

RdCEn Sample
New
Data Transaction
2889 drw 20

Figure 13. R3081 Burst Read

5.5

30

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SysClk

Rd

ND(31:0) --------+-~

Addr(3:2)

ALE

DataEn

Burst

RdCEn

Ack
RdCEn

Sample
Data

RdCEn

Sample
Data

RdCEn

Sample
Data

2889 drw21

Figure 14 (a). Start of Throttled Quad Read

SysClk

Rd

ND(31:0)

Addr(3:2)

ALE

DataEn

Burst

RdCEn

Ack
Ack

RdCEn

Sample
Data

RdCEn

Sample
Data

New
Transaction
2889 drw 22

Figure 14 (b). End of Throttled Quad Read

5.5

31

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SysClk

Wr

AlD(31:0)

Addr(3:2)

ALE
Diag(1)

Diag(O)

II

WrNear

Ack
Start
Write

Data
Out

Ack?

Negate
Wr

Ack?

New
Transfer

2889 drw 23

Figure 15. R3081 Write Cycle

.7

SysClk

BusReq

~
I
t1

~

~

~

"'"

./

L'

I

BusGnt

t3

~

AlD(31:0)

"/

Addr(3:2)

"

Diag(1:0)

/

/

""-

Rd

/'

""""'"

Wr

/'

"

ALE

./

/

Burst!
WrNear

"
2889 drw24

Figure 16. Request and Relinquish of R3081 Bus to External Master

5.5

32

IDT79R3081 RISController

SysClk

MILITARY AND COMMERCIAL TEMPERATURE RANGES

.7 ~

~

~

;7

'L'

,
BusReq

-t' " ~

_I

ts

BusGnt

t4
ND(31:0)

1"-.....

Addr(3:2)

L
1"-.....

Diag(1:0)

<
<
<

1"-.....

Rd

Wr

ALE

/

I,

Burst/
WrNear
2889 drw 25

Figure 17. R3081 Regaining Bus Mastership

'"

SysClk

"

Slnt(n)

I"\.
t28

t29

2889 drw 26

Figure 18. Synchronized Interrupt Input Timing

SysClk

Int(n)

Figure 19. Direct Interrupt Input Timing

5.5

33

IDT79R30B1 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

t28

t29

2889 drw 28

Figure 20. Synchronized Branch Condition Input Timing

~

SysClk

BrCond(n)

k'
t30

t31

2889 drw29

Figure 21. Direct Branch Condition Input Timing

./~

SysClk

BusReq

~
t1

CohReq

"'"

~

ff

'""

~
t2

JJ

./~

~K

t3~

BusGnt

'"

ND(31:0)

/

Addr(3:2)

'"/

Diag(1 :0)

'"/

Rd

/'

Wr

/

ALE

.........

./

/

Burst/
WrNear

..........
2889 drw 30

Figure 22. Coherent DMA Request

5.5

34

IDT79R30B1 RISController

SysClk

MILITARY AND COMMERCIAL TEMPERATURE RANGES

.? ~

~

,

./~

Wr

ALE

ND
Addr

~
l) K

--="'"
T36

T37
~

~

I

T41
T40

I.

~

-,

,

K

.> f(
- --

T38

T39

:> K

Internal
Invalidate
Address

2889 drw 31

Figure 23. Beginning of Coherent DMA Write

SysClk _ _ _ _-'

Ack
IvdReq

Internal
Ivd
Internal - - - - - + - - - - - - - + - - - - - - + -....
Invalidate
Address-------+--------+---------+---'
2988 drw 32

Figure 24. Cache Word Invalidation

SysClk

Ack
T40

Wr
T41
2889 drw 33

Figure 25. End of Coherent Write

5.5

35

1DT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

.? ~

SysClk

BusReq

.7

CohReq

.?

1£
t1

~

.? ~

~

~

L'
t6

BusGnt

~
t4

AlO(31 :0)

<
<

'"""./

Addr(3:2)

'"""-

<

Oiag(1:0)
...........

Rd

~

Wr

~

ALE
...........

Burst!
WrNear

II

L
~

Figure 26. End of Coherent DMA Request

5.5

2889 drw 34

36

IDT79R3081 RISControlier

MILITARY AND COMMERCIAL TEMPERATURE RANGES

84 LEAD PLCC/MQUAD(7) (SQUARE)

J.------D------..!
45° x .04

--I-+---+-~
s

SEATING PLANE
2874 drw27

NOTES:
1. All dimensions are in inches, unless otherwise noted.
2. BSC-Basic lead Spacing between Centers.
3. D & E do not include mold flash or protutions.
4. Formed leads shall be planar with respect to one another and within .004 inches at the seating plane.
5. ND & NE represent the number of leads in the D & E directions respectively.
6. D1 & E1 should be measured from the bottom of the package.
7. MQUAD is pin & form compatible with PLCC.

DWG#

J84-1

# of Leads

84

MJ84-1
84

Symbol

Min.

Max.

Min.

Max.

A

165

.180

165

.180

A1

.095

.115

.094

.114

S

.026

.032

.026

.032

b1

.013

.021

.013

.021

e

.020

.040

.020

.040

e1

.008

.012

.008

.012

D

1.185

1.195

1.185

1.195

D1

1.150

1.156

1.140

1.150

D2/E2

1.090

1.130

1.090

1.130

D3/E3

1.000 REF

1.000 REF

E

1.185

1.195

1.185

1.195

E1

1.150

1.156

1.140

1.150

e

.050 sse

.050 sse

ND/NE

21

21

5.5

37

IDT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

xxxxx -

IDT - - - Device Type

xx

x

Speed Package

x

y

Process/
Temp.

Blank

B
M

84-Pin MQUAD
84-lead Cavity-down Flatpack with
Integral Thermal Slug
84-lead PLCC
1OO-Iead TQFP

MJ
FD

J
PF
20
25
~----------------~ 33
40
50

~

__________________________

~

Commercial Temperature Range
Compliant to MIL-STD-883, Class B
Military Temperature Range Only

20.0MHz
25.0MHz
33.33MHz
40.0MHz .
50.0MHz (fN Only)

79R3081
79R3081E
79RV3081
79RV3081 E

=
=
=
=

No TLB; VCC 5V
With TLB; Vce 5V
No TLB; Vee 3.3V
With TLB; Vee 3.3V

VALID COMBINATIONS
79RV3081 (E) - 20,25,33
79RV3081 (E) - 20,25,33,40

MJ Package
PF Package
MJ Package

79R3081 E - 20,25 (FOB/FOM)

FO Package Only

lOT 79R3081 (E) - 20,25,33,40,50

5.5

38

~~

Integrated Device Technology. Inc.

IDT79R36100™
Advanced
Information

IDT79R36100™
HIGHLY INTEGRATED
RISController™

FEATURES
• Instruction set compatible with the lOT RISControlier
Family MIPS RISC CPUs
• System-level integration minimizes system cost
- 32-bit RISC CPU
- 4KB instruction cache on-chip
- 1KB data cache on-chip
- Memory, DMA and I/O controllers
- System peripherals
• 24 MIPS/ 42K Dhrystone-2.1 at 25 MHz
• Improved cache control and cache locking
• Flexible bus interface allows simple, low cost designs
- De-multiplexed address bus and data bus
- On-chip 4-deep ReadlWrite buffer
- Programmable bus width (8-,16-, and 32-bit)
• On-chip DRAM controller with Address Multiplexer
- Supports optional interleaved DRAMs

• On-chip memory and I/O controller
- Chip selects, wait-state generator
- Supports optional interleaved ROMs
- Supports PCMCIA Master protocol
• On-chip DMA controller
- 4 internal channels, 2 external channels
• On-chip bi-directionallEEE 1284 Centronics™ Parallel Port interface
• On-chip laser printer video raster engine interface
• Built-in debug/emulator support
• 3.3V and 5V versions, MQUAD-208 packaging
• Supports interrupt steering to internal DMA
• On-chip dual-channel serial communications controller
• On-chip timers and interrupt controller

BLOCK DIAGRAM
BrCond.lnt

Timers
Diag Bus

TImer
Control
Serial Port
Control
PIOmultipurpose
1/0 pins

Bi-directional
Parallel Port
Control

Bus
Interface

Laser Printer
Control

4-deep
Write
Buffer

Addr/Data

Path

The lOT logo is a registered trademark and Orion.R36100. R4600.R4650.R4700. R3041.R3051. R3052.R3081.RISControlier. and RISCore are trademarks of Integrated Device Technology. Inc.

SEPTEMBER 1995

Commercial Temperature Range
© 1995 Integrated Device Technology. Inc.

5.6

IDT79R36100

DESCRIPTION
The IDT79R36100 is a highly integrated member of the
lOT RISController family. The R36100 implements a
"system on a chip" including the CPU core, cache
memory, system logic functions and application specific
peripherals. The 36100 is well-suited to a wide variety of
very cost sensitive and board space constrained
embedded applications. The high level of integration also
greatly reduces the system design challenge, substantially reducing design risk and time to market.
The R36100 RISController is based upon the general
purpose R3000A MIPS RISC CPU core and integrates
substantial amounts of on-chip instruction cache and data
cache memory. In addition to the CPU core and cache
memory, the R36100 integrates all necessary system
logic functions on-chip, including DRAM, ROM, I/O and
DMA controllers; counter/timers; interrupt controllers;
general purpose parallel I/O and debug support circuitry.
The R36100 also integrates printer and data communication peripherals including an IEEE 1284 parallel port,
laser printer video rasterizer, and two serial communications ports.
The R36100 RISController is software compatible with
all members of the lOT RISController family, including the
family of low-cost 32-bit R30xx RISControllers and the
Orion family of high-performance 64-bit embedded
controllers. The common instruction set architecture
(ISA) enables the same applications software to be used
across a wide variety of price/performance points.
The R36100 RISController has four on-Chip bus
controllers allowing seamless interfaces with a wide
variety of standard memories and peripherals, including:
• Standard page mode DRAMs
• EPROMs, FLASH, SRAM, Dual-Port SRAM
• FIFOs, SCSI, A/D, and other I/O peripherals
• Ethernet, data compression, and other coprocessors
The R36100 RISController integrates an IEEE 1284
parallel port, RS-232C and Local Talk serial ports, and a
laser printer video rasterizer to serve printer system applications, including:
• monochrome laser and ink-jet printers
• host-based printer cards
• multi-function laser/fax printer systems
In addition, the R36100 RISController integrates
asynchronous and synchronous serial controller channels
and multiple timers to serve data communications applications, such as:
• Local Area Network (LAN) interface cards
• CSU/DSU SDLC/HDLC line driver cards
• Router, switcher, and data compression cards

Device Overview
The R36100 RISController shown in the figure on page
1 is a block level representation of the functional units.
The R36100 can be viewed as a "system on a chip"-the

COMMERCIAL TEMPERATURE RANGE

embodiment of a discrete system built around the
R3000A CPU. By integrating the system functionality
onto a single chip, dramatic cost, size, and power reductions are achieved. Thus the overall system complexity is
reduced and system development time is minimized.
CPU Core
The R36100 RISController is based on the R3000A
CPU core. The R3000A is a full 32-bit RISC integer
execution engine, capable of sustaining a peak single
cycle execution rate by using its five-stage pipeline. The
CPU core contains an integer ALU unit and bit shifter with
a separate integer multiplier/divider unit, address adder
and program counter generator, and 32 orthogonal 32-bit
registers. The R36100 execution core implements the
MIPS-I instruction set architecture (ISA). Thus, the
R36100 is binary compatible with all other MIPS CPU
engines, including the low-cost R30xx family and the
high-speed R4600 Orion family.
System Control Co-Processor
The R36100 RISController also integrates a System
Control Co-processor (CPO) on chip. CPO manages the
exception handling capability of the R36100, the virtual to
physical address memory mapping of the R36100, and
the various programmable bus-to-cache interface
capabilities of the R36100. These topics are discussed in
the Hardware User's Manual.
The R36100 does not include the optional TLB found in
other members of the lOT RISController family, but
instead performs the same virtual to physical address
mapping of the Base Versions of the R30xx family. These
Base Version devices still support distinct kernel and LlSer
mode operation, but do not require page management
software or an on-chip TLB, leading to a simpler operating
system software model and a lower cost processor.
Clock Generator Unit
The R36100 RISController is driven from a single,
double frequency input clock. An on-Chip clock generator
unit is responsible for managing the interaction of the
CPU core, caches, and bus interface. The clock
generator unit replaces the external delay line that was
required in discrete R3000A based systems.
Instruction Cache
The R36100 RISController integrates 4kB of on-chip
instruction cache, which is organized with a line size of 16
bytes (four 32-bit entries). This relatively large cache
substantially contributes to the high performance inherent
in the R36100, and allows systems based on the R36100
to achieve high performance even from low-cost memory
systems. The cache is implemented as a direct mapped
cache, and is capable of caching instructions from
anywhere within the 4GB physical address space. The

5.6

2

II

IDT79R36100

cache is implemented using physical addresses and
physical tags (rather than virtual addresses or tags), and
thus does not require flushing on context switches.
The R36100 instruction cache supports a cache locking
mechanism to improve real-time performance. Each
cache can be split into two halves or four quarters, each
half or quarter servicing a different area of the large
address space. This enables the system software to
"lock" time-critical code (e.g., router address hash-table
lookup algorithms and interrupt service routines), into one
of the halves or quarters, and allow other tasks to utilize
the other half or quarters without disrupting the lockedtime critical code. This technique allows software to
perform instruction cache locking, which ensures deterministic response.

COMMERCIAL TEMPERATURE RANGE

bus interface that connects to slow memory devices
without sacrificing performance.
The R36100 bus interface utilizes a de-multiplexed
address and data bus. This interface readily connects to
memory subsystems that are 8-, 16-, or 32-bits wide,
and/or interleaved.
The R36100 incorporates a 4-deep write buffer to
decouple the speed of the execution engine from the
speed of the memory system. The write buffers capture
the processor's address and data information during
internal store operations and process as FIFO at a rate of
up to one per clock. The write buffer then presents the
bus interface write transactions at the rate the memory
system can accommodate.
During main memory writes, the R36100 can break a
large datum (e.g. 32-bit word) into a series of smaller
transactions (e.g. bytes), according to the width of the
memory port being written. This operation is transparent
to the software that initiated the store. This insures that
the same software can run across multiple platfoms
having differing memory system configurations.
The R36100 read interface performs both single datum
reads and quad word reads. In order to accommodate
slower reads, the R36100 incorporates a 4-deep read
buffer FIFO, so that the external interface can queue data
within the processor before releasing it to perform a burst
fill of the internal caches.
In addition, the R36100 can perform on-chip data
packing when performing large datum reads (e.g., quad
words) from narrower memory systems (e.g., 16-bits).
Once again, this operation is transparent to the actual
software, which simplifies migration of software to higher
performance (true 32-bit) systems, and simplifying field
upgrades to wider memory. Since this capability works
for either instruction or data reads, the R36100 easily
supports the use of 8-, 16-, 32-bit, or interleaved boot
PROMs.

Data Cache
The R36100 RISController incorporates an on-chip
data cache of 1kB, which is organized as a line size of 4
bytes (one word). This relatively large data cache
contributes substantially to the high performance inherent
in the R36100. As with the instruction cache, the data
cache is implemented as a direct mapped physical
address cache. The cache is capable of mapping any
word within the 4GB physical address space.
The data cache is implemented as a write through
cache to insure that main memory is always consistent
and coherent with the internal cache. In order to minimize
processor stalls due to data write operations, the bus
interface unit incorporates a 4-deep write buffer that
captures address and data at the processor execution
rate. This allows the data to be retired to main memory at
a much slower rate without impacting the performance of
the internal CPU pipeline.
The R36100 supports data cache locking with the same
mechanism as the instruction cache. The 36100 allows
the data cache to be split into two halves or quarters,
each half or quarter servicing a different area of the large
address space. This enables the system software to Memory Controller
"lock" time-critical data (e.g., routing address information
The R36100 RISController uses the on-chip memory
tables and the interrupt stack) into one of the halves or controller to gluelessly attach external ROM (including
quarters, and allows other tasks to utilize the other half or FLASH) and/or SRAM, in a number of system configuraquarter without disrupting the critical data. This technique tions. For example, the memory controller supports
allows software to perform data cache locking without interleaved ROM and/or SRAM, 8-bit boot ROM, 32-bit
burst ROMs, as well as a simple 32-bit wide EPROM
requiring memory management support.
array. The memory controller integrates all of the control
signals as well as managing the access timing and waitBus Interface Unit
The R36100 R ISController uses its large internal state generation for multiple banks, all under the control
caches to provide the majority of its memory bandwidth of boot software.
requirements to/from the execution engine. The execution
engine pipeline can access both one instruction and one
data load/store per clock cycle. Only on the relatively rare
cache miss or on writes does the R361 00 require access
to main memory. Thus, the R36100 can utilize a simple

5.6

3

IDT79R36100

COMMERCIAL TEMPERATURE RANGE

DRAM Controller
The R36100 RISController integrates an on-chip
DRAM controller. The DRAM controller directly controls
up to four banks of standard page mode DRAMs in a
number of configurations, including systems with varying
densities of DRAM, 32-bit wide, interleaved DRAM, and
16-bit wide DRAM subsystems.

customize the R36100 resources according to their
needs.
Thus, designs needing a special purpose
controller--such as the laser printer video controller--can
allocate the laser printer video pins for that purpose.
Other applications, such as Datacom, which do not need
the laser printer video, can use those pins for general
purpose inputs or outputs.

I/O Controller
The R36100 RISController has an on-chip 1/0
controller that performs all necessary address decoding
and wait-state generation for external 1/0 devices. In
addition, the on-chip 1/0 controller readily interfaces as a
master to PCMCIA, including support of the large address
space required and the PCMCIA chip-select protocol and
timing.

Serial Communications Controller
The R36100 RISController integrates a dual channel
serial port. This peripheral controller can perform a
variety of synchronous and asynchronous protocols,
including RS-232C, LocalTalk, SDLC, and HDLC. To
maximize throughput, the on-chip serial port is optionally
serviced by the auto-initiated on-chip DMA controller
which can automatically block move data to and from the
port.

DMA Control
The R36100 RISController provides on-chip DMA
control for internal peripherals, external peripherals, and
external memory. Multiple internal channels allow block
moves of data between any combination of memory and
1/0. Each channel can also be interrupt controlled, which
allows an 1/0 rileripherallike the serial port to regulate the
individual transactions of a block move.
The R36100 RISController also supports external
DMA masters, which take over the external system bus
via a bus request and grant handshake.· Once in control
of the system bus, the external DMA master can read and
write to memory, 1/0, and internal peripherals via the
R361 ~O's bus controllers.

Interrupt Controller
The R36100 RISController integrates an on-Chip
interrupt controller to manage both external interrupts and
interrupts signaled from the on-chip peripherals. The
interrupt controller improves internal interrupt servicing
speed and assists in interrupt prioritization and nesting,
as well as interfacing with the auto-initiated DMA.
IEEE 1284 Bi-directional Parallel Port
The R36100 RISController includes an internal
IEEE1284 parallel port peripheral, which implements a
true bi-directional port. Features include:
• 8-bit input Target Compatible protocol (for backward
compatibility with legacy PCs)
• nibble and byte mode output protocol (for backward
compatibility with most PCs)
• ECP protocol (for the emerging Laser Printer PC standard)
• EPP protocol (for datacom applications)
• External transceiver interface control pins
• Auto-initiated DMA via internal interrupts

Counter/Timers
The R36100 RISController contains 3 general purpose
timers. Each timer consists of a 16-bit count register as
well as a 16-bit compare register. The count register
resets to 0 and then counts upward until it equals the
compare register. When the count register equals the
compare register, the TCN output is asserted and the
count is reset back to O. In order to support intervals
Laser Printer Video Interface
longer than 2 16 ticks, the timers use a common 16-bit
The R36100 RISController integrates an on-chip laser
prescaler counter. Each timer is programmable to select
printer videolcontrol interface. This peripheral provides
a power-of-2 divisor of the prescaler. Using these
support for the following:
features, each timer can be used as a general purpose
1-bit serial stream laser printer or raster engine inter•
real-time clock, bus timeout timer, watch dog timer,
face
PWMlsquare wavelbaud rate generator or gated clock
• On-Chip FIFO
external event counter.
• Programmable margin widths and page lengths
• Auto-initiated DMA via internal interrupts
PIO Interface
The R36100 RISController has a Parallel
Input/Output (PIO) interface for controlling multi-purpose
utility pins. The PIO pins can be programmed to act as
general purpose inputs or outputs. Each PIO pin is also
multiplexed with other controllers' inputs or outputs. This
flexible arrangement allows system designers to

5.6

4

IDT79R36100

COMMERCIAL TEMPERATURE RANGE

Performance Overview

Development Support

The R36100 RISControlier achieves a very high-level of
performance. This performance is due to the following
features:
• An efficient execution engine. The CPU performs ALU
operations and store operations in a single cycle, has
an effective load time of 1.3 cycles and branch execution rate of 1 .5 cycles based on the ability of the compilers to avoid software interlocks. Thus, the R36100
achieves over 24 dhrystone MIPS performance at
25M Hz.
• Large on-chip caches. The R361 00 contains caches
that are substantially larger than most embedded
microprocessors. These large caches minimize the
number of bus transactions required, and allow the
R36100 to achieve actual sustained performance that
is very close to its peak execution rate, even with low
cost memory systems.
• Autonomous multiply and divide operations. The
R361 00 features an on-chip integer multiplier/divide
unit that is separate from the other ALU. This allows
the R36100 to perform multiply or divide operations in
parallel with other integer operations by using a single
multiply or divide instruction rather than "step" operations.
• Integrated write buffer. The R36100 features a four
deep write buffer, which captures store target
addresses and data at the processor execution rate
and retires them to main memory at the slower main
memory access rate. Use of on-chip write buffers eliminates the need for the processor to stall when performing store operations.
• Burst read support. The R36100 enables the system
designer to utilize page, static, or nibble mode RAMs
when performing read operations. This minimizes the
main memory read penalty and increase the effective
cache hit rates.
• Tightly coupled memory system. System resources
can be accessed and managed efficiently for the
needs of the execution core when memory controllers
are integrated on-chip.

The R36100 is supported by a rich set of development
tools, ranging from system simulation tools through
PROM monitor and debug support, applications software
and utility libraries, logic analysis and emulator tools, and
SUb-system modules.
Figure 1 is an overview of the system development
process typically used when developing R36100 applications. The R36100 family is supported in all phases of
project development. These tools allow timely, parallel
development of hardware and software for R361 00 based
applications, and include tools such as the following:
• IDT/c compiler, based on the GCC/GNU tool chain.
• Cross development tools, available for a variety of
development environments.
• High-performance lOT floating point emulation library
software.
• lOT Evaluation Boards, which include RAM, EPROM,
I/O, and the lOT PROM Monitor.
• lOT laser printer system boards, which directly drive a
low-cost print engine.
• Adobe PostScript Page Description Language running
on the lOT R3051 family.
• IDT/sim PROM Monitor, which implements a full PROM
monitor, including diagnostics, remote debug support,
and peek/poke.
• IDT/kitTM (Kernel Integration Toolkit), which provides
library support and a framework for the system runtime environment.
• Logic analyzer and in-circuit emulator support for fast
debugging and hardware/software integration.

System
Architecture
Evaluation

System
Development
Phase

System
Integration
and
Verfification

Software
Stand-Alone Libraries

Selectable Features

~~;~~~~~~~~~~~~~
Tools

Boot-time selectable features are:8/16 or 32-bit
PROM support and Big/Little Endian selection. Other
selectable, register-configurable features are:
• Number of wait states for different memory and I/O
controllers
• Memory and I/O map configuration
• 16 or 32-bit DRAM and 8/16 or 32-bit memory and I/O
• Interleaved or non interleaved memory/DRAM
• Programmable control signals timing for all controllers
• Selectable PIO
• Selectable transceivers type for all controllers (FCT
260/FCT245/FCT543)
• Selectable 110 style (Motorolallntel/PCMCIA)

Adobe PostScript POL
IDTlsim device drivers
IDTlkit
IDTlc Compiler
Hardware
Hardware Models
Evaluation Board
Laser Printer System
General CAD Tools

Figure 1. Development Support

5.6

5

IDT79R36100

COMMERCIAL TEMPERATURE RANGE

System Usage
The IDT R36100 RISControlier is specifically designed
to easily implement low-cost memory systems. Typical lowcost memory systems use EPROMs, DRAMs, as well as
application specific peripherals. Some embedded systems
also optionally contain or substitute DRAM with static
RAMs.
Figure 2 demonstrates the low-system cost inherent in
the R36100. In this example system, which is typical of a
low-cost laser printer, a 32-bit PROM interface is used due
to the size of the PDL interpreter. Other embedded systems
could optionally use an 8-bit or a 16-bit PROM, or even an
interleaved 64-bit interface. A 16-bit font cartridge interface
is provided through PCMCIA for add-in cards and a 32-bit
page buffer DRAM is used for high-resolution.
In this example, a field or manufacturing upgrade to a
larger page buffer is supported by the boot software and
DRAM controller. Such a system features a very low entry
price, with a range of field upgrade options. Note that the
performance of the R36100 allows software frame buffer
compression to be effective in reducing system DRAM while
maintaining expected performance.

LAN
cartridge

16-bit
FONTRO
cartridge

FONT
Hard Disk
cartridge

add-in
cartridges

printer controller card

Font
Rasterization
Co-processor

LAN
add-in card
slot

FAX
add-in card
slot

SCSI
add-in card
slot

add-in card

Figure 2. R361 ~O-based Printer System

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COMMERCIAL TEMPERATURE RANGE

IDT79R36100

Pin Description
The following is a list of interface, interrupt, and miscellaneous pins available on the R36100. Pins marked with one
asterisk are active when low.

Pin Name

Type

Description

System Bus Interface:
SysAddr(25:0)

Output

System Address Bus.
Also serves as the DramAddr(13:2) Bus.

SysData(31 :0)

InputiOutput

System Data Bus.

SysClklnlnput

Input

System Clock Input.
Twice (2x) the internal CPU frequency.

SysClk

Output

System Clock Output.
All other outputs are referenced to this system clock.

SysReset

Input

System Reset.
Initializes entire chip, except for JTAG circuitry.

SysWait

Input

System Way.
Extends current bus transaction.

SysBusError

Input

System Bus Error.
Terminates current bus transaction.

SysALEn

Outputllnput(DMA)

System Address Latch Enable.
Indicates valid address at the beginning of a bus transaction.

SysBurstFrame

Outputllnput(DMA)

System Burst Frame.
First indicates the beginning of a bus transaction. Then indicates if the bus transaction is
a burst and if the next datum is the last datum.

SysData Rdy

Output

System Data Ready.
Indicates valid data during each datum of a bus transaction (except when SysWait is
asserted).

SysRd

Outputllnput(DMA)

System Read.
Indicates current bus transaction is a read.

SysWr

Outputllnput(DMA)

System Write.
Indicates current bus transaction is a write.

DRAM Controller Pins
DramRAS(3:0)

Output

DRAM Row Address Strobe.

DramCAS(3:0)

Output

DRAM Column Address Strobe.

DramRDEnEven

Output

DRAM Read Enable for Even FCT245/543 Type Banks. On FCT260 type banks, it is the
read enable for both.

DramRdEnOdd

Output

DRAM Read Enable for Odd FCT245/543 Type Banks. On FCT260 Type Banks, it is
the path select.

DramWrEnEven

Output

DRAM Write Enable for Even Banks.

DramWrEnOdd

Output

DRAM Write Enable for Odd Banks.

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COMMERCIAL TEMPERATURE RANGE

IDT79R36100
Pin Name

Type

Description

Memory Controller:
MemCS/loCS(7:0)

Output

Memory or I/O Chip Selects.
MemCS(O) and optionally MemCS(1) are reserved for the Boot PROM. loCS(6) and/or
loCS(7) are optionally reserved for the Centronics Port if used.

MemRdEnEven

Output

Memory Read Enable for Even FCT245/543 Type Banks.
On FCT260 Type banks, it is the read enable for both even and odd banks.

MemRdEnOdd

Output

Memory Read Enable for Even FCT245/543 Type Banks.

MemWrEn(3:0)

Output

Memory Write Enable for each byte lane.

10RdEn/DStrobe

Output

I/O Read Enable or I/O Data Strobe.

10WrEn/RdWr

Output

I/O Write Enable or I/O Read/Write.

DmaBusGnt(1 :0)

Output

DMA Bus Grant

DmaBusReq(1 :0)

Input

DMA Bus Request.

On FCT260 Type Banks, it is the path select.

DMA Controller:

Indicates that the CPU has tri-stated the bus and other DMA related signals.

Indicates that external DMA agent would like control of the bus and other DMA related
signals.
Input/Output

DMA transaction done

SerialPClkln(1 :0)

Input

Optional Prim ary Serial Clock Input.

SerialSClk(1 :0)

Input/Output

Optional Secondary Serial Clock Input or Output.

SerialRxData(1 :0)

Input

Serial Receiver Data Stream.

SerialTxData(1 :0)

Output

Serial Transmitter Data Stream.

Seria1CTS(1 :0)

Input

Serial Clear To Send.

Seria1RTS(1 :0)

Output

Serial Request To Send.

Serial Sync(1 :0)

Input/Output

Serial Frame Sync.

Serial DCD(1 :0)

Input

Serial Data Carrier Detect.

Seria1DTR(1 :0)

Output

Serial Data Terminal Ready.

Input/Output

Timer Terminal count output or Timer Count Gate Enable input.

DmaDone

Serial Port Pins:

Timer:
TimerTC(2:0)
ITimerGate(2:0)

Terminal count asserts when Timer Count equals O. Timer Gate enables counter to
count upward or to stop.

PIO:
P10(31 :0)

Input/Output

Parallel inputs or Parallel Outputs.
Parallel inputs and parallel outputs are multiplexed with various peripheral inputs and
peripheral outputs. If the peripheral is unused, the input or output pin can be reconfigured to be a general purpose input or output, respectively.

5.6

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IDT79R36100
Pin Name

Type

Description

Bi-Directional Centronics Interface:
CentStrobe

Input

Centronics Strobe.
In compatible mode, strobes data into the printer. Has other uses for other modes.

CentAck

Output

Centronics Acknowledge.
In compatible mode, acknowledges a strobe. Has other uses for other modes.

CentBusy

Output

Centronics Busy.
In compatible mode, delays the host from sending more data. Has other uses for other
modes.

CentPaperError

Output

Centronics Paper Out/Jam Error.
In Compatible mode, indicates that the printer has a paper error when asserted with
CentFault. Has other uses for other modes.

CentSelect

Output

Centronics Select.
In Compatible mode, used to indicate that this printer is on-line. Has other uses for
other modes.

CentAutoFeed

Input

Centronics Auto Page Feed.
In compatible mode, sends a paper feed to the printer. Has other uses for other modes.

Centlnit

Input

Centronics Initialization/Reset.
In Compatible mode, resets the printer. Has other uses for other modes.

CentFault

Output

Centronics Fault.
In Compatible mode, indicates that the printer has a problem. Has other uses for other
modes.

CentSelectln

Input

Centronics Select In.
In Compatible mode, indicates that the Host wants to select this printer on a shared
cable. Has other uses for other modes

CentHostStrobe

Output

Centronics Host Strobe.
Used to latch Host data on the external FCT952/374 data transceiver during a Host
write.

CentHostOEn

Output

Centronics Host Output Enable.
Used to enable the external FCT952/374 data transceiver during a Host read.

Laser Engine Interface:
LaserVideoData

Output

LaserVideoClkln

Input

Laser Video Data Stream.
Laser Video Clock Input.
Accepts either the (1 x) Video Data Stream frequency or 8 times (8x) the PLL frequency.

LaserLineSync

Input

Laser Line Sync.
Indicates that the laser drum is ready to start accepting data for a new line.

LaserPageSync

Input

Laser Page Sync.
Indicates that the laser drum is ready to start a new page.

Debug/Emulator Interface:
JtagClkln

Input

JTAG Clock Input (TCK).
Test mode serial boundary scan input clock.

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COMMERCIAL TEMPERATURE RANGE

IDT79R36100
Pin Name

Type

Description

Debug/Emulator Interface:
JtagModeSelect

Input

JTAG Mode Select (TSEL).
Test mode serial boundary scan command data. In normal operating mode, JtagModeSelect should be left unasserted high.

JtagDataln

Input

JTAG Data In (TDI). Test mode serial boundary scan register data input.

JtagDataOut

Output

JTAG Data Out (TDO).
Test mode serial boundary scan register data output.

JtagReset

Input

TAG Reset (TRES*).
Resets the JTAG test circuitry. Does not reset any other chip functions.ln normal operating mode, JtagReset should be left asserted low.

Diagnostic Pins
DiagC/UnC

Output

Diagnostic Cached versus Uncached.
On read bus transactions indicates whether the read is cached or uncached.

DiaglnstiData

Output

Diagnostic Instruction versus Data.
On read bus transactions indicates whether the read is for instructions or data.

DiagRun

Output

Diagnostic Run.
Indicates an internal pipeline run cycle. This pin has iso-synchronous timing.

DiagBranchTaken

Output

DiagBranchTaken
Indicates that a branch, jump, or exception has been taken. This pin has asynchronous
timing.

DiagJRorExe

Output

Diagnostic Jump Register or Exception occurring.
Indicates that a jump register or exception is executing. This pin has asynchronous timing.

DiaglnternalWr

Output

Diagnostic Internal Write.
Indicates that a MTCO to CPO register $3 is occurring.

DiaglnstCacheWrDis

Output

DiagTriState

Input

Diagnostic Cache Write Disable.
Disables writes to the instruction and data cache. This pin has iso-synchronous timing
and is not recommended for functional use.
Diagnostic Tri-State all outputs.
All outputs are tri-stated including SysClk. This pin is asynchronous such that tri-stating
asserts or de-asserts output enables immediately.

DiagFCM

Input

Diagnostic Force Cache Miss.
This pin has iso-synchronous timing. If used for functional board tests, it is recommended that it be (de-)asserted statically at reset time and left (de-)asserted.

DiaglntDis

Input

DiagNoCS

Output

Diagnostic Interrupt Disable.
Diagnostic No Chip Select.
No internal or external chip select has occurred for the current bus transaction, therefore
an external state machine should handle the bus transaction.

DiaglnternalDMA

Output

Diagnostic Internal DMA.
Asserts whenever any of the Internal DMA channels is generating the current bus transaction.

5.6

10

COMMERCIAL TEMPERATURE RANGE

IDT79R36100
Pin Name

Type

Description

Exception Handling:
ExcSlnt(2:0)

Input

Exception Synchronized Interrupts.
Also used as the reset initialization vector for 2:Boot16, 1:Boot8, and O:BigEndian
modes.

Exclnt(4:3)

Input

Exception Interrupts.

ExcSBrCond(3:2)

Input

Exception Synchronized Branch Condition inputs.

Power/Ground:
Vcc

Input

Power pin.
All power pins must be connected. 5V or 3.3V depending on part type.

Gnd

Input

Ground pin (VSS).
All ground pins must be connected.

5.6

av.

11

COMMERCIAL TEMPERATURE RANGE

IDT79R36100

Physical Specifications

MD208
Top View

5.6

12

COMMERCIAL TEMPERATURE RANGE

IDT79R36100

36100 Advance Pin-Out
Pin

Function

Pin

Function

Pin

Function

Pin

Function

JtagDataOut
SysData(O)
SysData(1)
SysData(2)
SysData(3)
vee

105

N/C

157

SeriaITxData(O)

106
107
108

DramRASN(2)
DramRASN(3)
DramCASN(O)
DramCASN(1 )
vee
vss

158
159
160
161
162
163

SeriaICTSN(O)
SeriaIRTSN(O)
SeriaITxClkN(O)
SeriaISyenN(O)
vee
vss

164
165
166

SeriaIDTRN(O)
SeriaIDCDN(O)
SerialClklnN(1 )

115

DramCASN(2)
DramCASN(3)
DramRdEnEvenN
DramRdEnOddN_TrN

116
117

MemCSN_loCSN(O)
MemCSN_loCSN(1 )

118
119
120
121
122
123
124

MemCSN_loCSN(2)
MemCSN_loCSN(3)
vee
vss
MemCSN_loCSN(4)

167
168
169
170
171
172
173
174
175
176

SerialTxClkN(1 )
SerialSyneN(1 )
SerialRxData(1 )
SerialTxData(1 )
SeriaICTSN(1 )
vee
vss
SeriaIRTSN(1 )
SeriaIDCDN(1 )
SeriaIDTRN(1 )

1

Test1N

53

2

SysAddr(O)
SysAddr(1)
DiagC_UnCN
SysAddr(2)
vee
vss

54
55
56
57
58
59

vss

8
9
10

SysAddr(3)
SysAddr(4)
DiagRunN

60
61
62

112
113
114

11
12
13
14

DiagBranehTakenN
DiagJRorExeN
DiaglnternalWrN

63
64
65

SysData(4)
SysData(5)
SysData(6)
SysData(7)
SysData(8)
SysData(9)

SysAddr(5)
SysAddr(6)
vee

66
67
68

vss
SysAddr(7)
SysAddr(8)
DiaglnstCaeheWrDisN

69
70
71

SysData(10)
SysData(11 )
vee
vss
SysData(12)
SysData(13)
SysData(14)

3
4
5
6
7

15
16
17
18
19
20

72

109
110
111

MemCSN_loCSN(5)
MemCSN_loCSN(6)

21

DiagTriStateN

73

SysData(15)

125

MemCSN_loCSN(7)

22
23
24
25
26
27
28
29
30
31
32
33

DiagFCMN
DiaglntDisN
SysAddr(9)
SysAddr(10)
vee
vss

74
75
76

SysData(16)
SysData(17)
SysData(18)
SysData(19)
vee
vss

126
127
128
129
130
131
132
133
134
135

MemRdEnEvenN
MemRdEnOddN
MemWrEnN(O)
MemWrEnN(1 )
vee

136
137

N/C
N/C

179
180
181
182
183
184
185
186
187
188
189

138
139
140
141
142

LaserVideoData
LaserVideoClk
vee
vss
LaserLineSyneN
LaserPageSyneN

190
191
192
193
194
195

CentSeleetinN
CentHostStrobeN
vee
vss
CentHostOEnN
DmaBusGntN(O)

ExeSintN(O)
ExeSintN(1 )
ExeSintN(2)
ExelntN(3)
ExelntN(4)
DiaglntDmaN
vee
vss
SysWaitN
SysBusErrorN
SysClkN
SeriaIClklnN(O)
SeriaIRxData(O)

196
197
198
199
200
201

DmaBusGntN(1 )
DmaBusReqN(O)
DmaBusReqN(1 )

202
203
204
205
206
207
208

vee
vss
SysRdN
SysWrN
SysBurstFrameN
ExeSBrCond(2)
ExeSBrCond(3)

34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

SysAddr(11 )
SysAddr(12)
DiagNoCSN
Diaginst_DataN
SysAddr(13)
SysAddr(14)
SysAddr(15)
SysAddr(16)
vee
vss
SysAddr(17)
SysAddr(18)
SysAddr(19)
SysAddr(20)
SysAddr(21 )
SysAddr(22)
SysAddr(23)
SysAddr(24)
vee
vss
SysAddr(25)
JtagModeSeleet
JtagResetN
JtagClkln
JtagDataln

77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104

SysData(20)
SysData(21 )
SysData(22)
SysData(23)
SysData(24)
SysData(25)
SysData(26)
SysData(27)
vee
vss
SysData(28)
SysData(29)
SysData(30)
SysData(31 )

143
144
145

SysClkln
SysResetN
DramWrEvenN

N/C

146
147
148
149

vee
vss
DramWrOddN

150
151
152

N/C

153
154
155
156

DramRASN(O)
DramRASN(1 )
TestON

5.6

vss
MemWrEnN(2)
MemWrEnN(3)
loRdEnN_DStrobeN
loWrEnN_RdWrN

177
178

TimerTCN(O)
TimerTCN(1 )
TimerTCN(2)
CentStrobeN
CentAekN
vee
vss
Cent Busy
CentPaperError
CentSeleet
CentAutoFeedN
CentinitN
CentFaultN

DmaDoneN
SysAleN
SysDataRdyN

13

COMMERCIAL TEMPERATURE RANGE

IDT79R36100

SysAddr(25:0)

...

SysData(31 :0)

~

ge:

3f>'

III!
III!

3~
7

SysClkln

0

u

SysClk

CI)

:J

"C

e:
CII

0

SysBusError

~

:s

SysALEn

III!

CII

SysBurstFrameSys

III!

>-

DataRdy

III!

E

en

e'E

<:

~

•

u

0

OmaBusGnt(1:O) "

•

DmaDone

J

CD

.2

a.w

w

r

0

ExcSlnt(2:0)
Exclnt(5:3)

0

~

w

E

ExcSBrCond(3:2)

x

1

w

w

[

0

~

1

•

3.:;::.
/'
III!

R36100
Logic
Symbol

I

7

2.:::::

2.:;::
/'
2.:::::

III!

7

.

DiagC/UnC

III!

OlaglnstIData

•

2.c::.

+--f4

•

JtagReset

2.:;::
/'
2.c::.

7

DiagRun

•
•

u

~

DiagJRorExe

w

E
~0

e:
01
ro

(5

III!

•

Diag InternalWr

l

•

•

Diag InstCacheWrDis

•
•
•

DiagTriState
DlagFCM
DiaglntDis

-.:"0
we:
~J

oe

[

•
•
•

~

7

PIO

1

III!

3*,

/'

o

14

g

~

I DT79R4400™
IDT79RV4400

THIRD GENERATION
64-BIT SUPER-PIPELINED
RISC MICROPROCESSOR

Integrated Device Technology, Inc.

FEATURES:

• Standard operating system support includes:
- Microsoft Windows™ NT
- UNISOFT UNIX™ System V.4
• Fully software compatible with R3000A 32-bit RISe
Processor Family
• 50, 67, 75, 88 and 1OOMHz clock frequencies
• 64GB physical address space
• Processor family for a wide variety of applications
- Desktop workstations
- Deskside or departmental servers
- High-performance embedded applications
- Tightly coupled multi-processing systems
- Fault tolerant systems
• R4400 for 5V operation and RV4400 for 3.3V operation

• True 64-bit microprocessor
- 64-bit integer operations
- 64-bit floating-point operations
- 64-bit registers
- 64-bit virtual address space
• High-performance microprocessor
- Super-pipelined architecture supports 200MIPS at
100MHz
- No issue restrictions for dual instruction issue
• High level of integration
- 64-bit integer CPU
- 64-bit floating-point accelerator
- 16KB instruction; 16KB data cache
- Flexible MMU with large TLB

BLOCK DIAGRAM
Q)

Q)

"0

Data
Cache

0

u

Q)

0

0)

C\l

C\l

I

0

u

Q)

0

I-

l-

I

"0

Instruction
Cache

0)

Store Buffer/Aligner

18us

h

1

Write Buffer

~r SysAD

l

SCData
SCTag
SCAddr

DBus

t
FP Register File
FP Pipeline/Bypass
FP Status Register
FP Multiply

FP Divide

~

rl

PCache
Control

H

System,
Scache
Control

~

Pipeline
Control

System
Control

I

CPO Roqisters
ITLB
JTLB
DVA

IVA

I

Address Unit

I

PC Incrementer

+

I
Reqister File

ALU
Load Aligner/
Store Drive
Integer Multiply/
Divide MDHI, MDLO

~

FP Add, Convert,
Square Root

2884 drw 01

The IDT logo is a registered trademark and R3041. R3051. R3052, R3071, R3081, R3721 , R4400, R4600, RISControlier, and RISC Subsystem are trademarks of Integrated Device Technology, Inc.
MIPS is a registered trademark of MIPS Computer Systems, Inc.; Windows is a registered trademark of MicroSoft Corporation; UNIX is a registered trademark of AT & T

COMMERCIAL TEMPERATURE RANGE
©1995 Integrated Device Technology, Inc.

JULY 1995
5.7

DSC·9053/6

1

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

DESCRIPTION:
The IDT79R4400 family supports a wide variety of processor-based applications, from 32-bit ARC compliant desktop
systems through high-performance, 64-bit OLTP systems
manipulating large data bases in a multi-processor-based
system. The IDT79R4400 products offer a broad range of
price-performance options for high-performance systems,
allowing the system architect unprecedented degrees of freedom in making price-performance tradeoffs.
The IDT R4400 products provide complete upward application-software compatibility with the IDT79R3000 family of
microprocessors, including the IDT79R3000A and the IDT
n
RISControlier • family (IDT79R3051 ™ family). Microsoft Windows NT and UNISOFT UNIX VA operating systems insure
the availability of thousands of applications programs, geared
to provide a complete solution to a large number of processing
needs. An array of development tools facilitates the rapid
development of R4400-based systems, enabling a wide variety of customers to take advantage of the MIPS Open Architecture philosophy.
The R4400 family achieves a unique balance between
high-integer and high-floating-point performance. The key to
this balance is the super-pipelined architecture of the processor, which brings performance gains to both integer and
floating-point intensive programs without requiring
recompilation to take advantage of the architectural advancement. The execution engine is assured of a rapid and continual supply of instructions and data through the use of large
on-chip caches, and a high-performance on-chip TLB.
The R4400 family also provides a compatible, timely, and
necessary evolution path from 32-bitto true, 64-bit computing.
The original design objectives of the R4400 clearly mandated
this evolution path; the result is a true 64-bit processor fully
compatible with 32-bit operating systems and applications.
The 64-bit computing and addressing capability of the
R4400 enables a wide variety of capabilities previously limited
by a smaller address space. For example, the large address
space allows operating systems with extensive file mapping;
direct access to large files can occur without explicit I/O calls.
Applications such as large CAD databases, multi-media, and
high-quality image storage and retrieval all directly benefit
from the enlarged address space.
This data sheet provides an overview of the features and
architecture of the IDT79R4400 CPU family. A more detailed
description of the processor is available in the "R4400 Hardware User's Manual". Further information on development
support, applications notes, and complementary products are
also available from your 10caiiDT sales representative.

PC CONFIGURATION
The I DT79R4400PC is available in a 179-pin Pin Grid Array
(PGA). This configuration does not support secondary cache
or cache COherency, and is ideal for applications such as highperformance embedded control and low-cost desktop systems, where the on-chip caches provide enough performance
and where cost, power, and board space must be kept to a
minimum. By eliminating a secondary cache, a system can be
designed with fewer parts and lower power consumption.
SC CONFIGURATION
The 79R4400SC is available in a 447-pin Pin Grid Array
(PGA). This processor supports a secondary cache interface
and is ideal in systems where high performance is desired.
This component supports a 128kB to 4mB secondary cache
made from standard SRAMs. This flexibility allows system
designers to make price/performance tradeoffs in cache subsystem designs.
MC CONFIGURATION
The IDT79R4400MC is also available in the 447-pin Pin
Grid Array (PGA). This processor supports a secondary cache
and configurable multiprocessor cache coherency protocols.
Like the "SC" configuration, this processor also supports a
128kB to 4mB secondary cache made from standard SRAMs.
The IDT79R4400MC is well suited for a range of designs from
high performance desktop systems to fault tolerant multiprocessor servers.

HARDWARE OVERVIEW
The I DT R4400 processor brings a high-level of integration
designed for high-performance computing. The key elements
of the IDT R4400 are briefly described below. A more detailed
description of each of these subsystems is available in other
literature.
Superpipelined Implementation
In orderto achieve the high-performance desired fortoday's
applications and user's interfaces, the R4400 exploits instruction level parallelism using a superpipelined microarchitecture.
The R4400 uses an 8-stage superpipeline which places no
issue restrictions on instruction issue. Thus, any two instructions can be issued each master clock cycle under normal
circumstances, leading to 200MI PS performance at 100MHz.
One key advantage of this architecture is that all existing
applications can gain from the architectural advancement
represented by the R4400, without requiring recompilation to
reorder the software.
In order to support dual instruction issue, the internal
pipeline of the R4400 operates at twice the external clock
frequency. Instruction execution stages such as cache accesses are pipelined (thus the chip itself is super-pipelined)
to eliminate bottlenecks associated with long-latency functional units. Other stages, such as the ALU stage, completely
process one operation per pipeline clock cycle, allowing the
results of one operation to be immediately used by the
instruction which follows, with no pipeline interlocks.

IDT79R4400 FAMILY MEMBERS
The IDT79R4400 processor is available in three different
configurations: the IDT79R4400MC and IDT79R4400SC,
which include a 128-bit wide secondary cache bus; and the
IDT79R4400PC, with no secondary cache interface. All references to R4400 apply to R4400 (5V) and RV4400 (3.3V)
operation.

5.7

2

•

IDT79R4400 Family

I

I

Master Clock
Cycle
IF

I
I

IS
IF

COMMERCIAL TEMPERATURE RANGE

I

I

PCycle

I

RF

I

I

IS

1

RF

I

IF

I
I

IS

EX

IF

I
I
I
I
I
I

(8-Deep)
DF

I

DS

I

TC

r--WB

EX

1

DF

J

DS

TC

WB

RF

I
I
I
I

EX

I
I
I
I
I

DF

DS

TC

EX

DF

DS

RF

EX

DF

IS

RF

EX

IF

IS

RF

IF

IS

IS
IF

RF
IS
IF

J
I
I
I
I
I

I
I
I
I
I

WB
TC
DS
DF
EX

1

I

RF

TC

I
I

WB

DS

I

TC

DF

I

DS

EX

J

DF

WB

I
I
I

WB

I

DS

TC

I
I

I

WB

I

TC

I

WB

I

'----

Current CPU
Cycle

2884 drw02

Figure 1. R4400 a-Stage Super-Pipeline

clock

2

phase
cycle:
IFetch

IF

l

I

IC1
ITLB1

2

2
IS

I
I

EX

RF

IC2
ITLB2

2

2

2

DF

I

2

DS

TC

2

WB

ITC
IDEC
RF

ALU
Ld/St

ALU
DVA

I
I

Branch

IVA

I
I

IC1
IC2
ITLB1
ITLB2
ITC
IDEC
RF
ALU
DVA
DC1
DC2
LSA
JTLB1
JTLB2
DTC
IVA
WB

DC1
JTLB1

I
I
I

DC2
LSA
JTLB2

I
I
I

DTC

I

WB

I

I

WB

J

2884 drw 03

Instruction cache access stage 1
Instruction cache access stage 2
Instruction address translation stage 1
Instruction address translation stage 2
Instruction tag check
Instruction decode
Register operand fetch
Operation
Data virtual address calculation
Data cache access stage 1
Data cache access stage 2
Data load or store align
Data/Instruction address translation stage 1
Data/Instruction address translation stage 2
Data tag check
Instruction virtual address calculation
Write-back to register file

Figure 2. Pipeline Activities

5.7

3

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

High clock frequency results from careful construction of
the various resources of the processor: pipelining cache
accesses, shortening register access times, implementing
virtually indexed primary caches, and allowing the latency of
functional units to span multiple pipeline stages.
After extensive simulation of many methods of exploiting
instruction level parallelism, superpipelining was chosen because it improves integer performance commensurate with
floating-point performance. Thus, the R4400 provides performance benefits both to technical computing applications, and
also to a wide variety of commercial applications as well. In
today's technology, superpipelining results in less complex
logic, faster cycle times, quicker design cycles, and lower
cost. The pipeline of the IDT79R4400 is illustrated in Figure 1.

THE R4400 PIPELINE
The R4400 processor has an eight-stage execution pipeline. That is, each instruction takes eight Pclock (Pipeline
clocks, at twice the frequency of the input clock) cycles to
execute, but a new instruction is started on each Pclock cycle.
Anotherway of viewing the process is that, at any point in time,
eightseparate instructions are being executed at once. Figure
1 shows the R4400 pipeline in both views: a horizontal slice
shows the execution process of individual instructions, and a
vertical slice shows the processing of eight instructions at
once.
Each box shown in Figure 1 corresponds to a part of the
execution process.
Figure 2 illustrates the activities occuring within each
pipestage as a function of the instruction type. First, in the IF
stage, an instruction address is selected by the program
counter logic and the first half of both the instruction cache
fetch (IC1) and the instruction virtual to physical address
translation (ITLB1) is performed. The instruction address
translation is done through a two entry subset of the main or
joint translation lookaside buffer (JTLB) called the ITLB.
In the IS stage, the second half of both the instruction cache
fetch (IC2) and instruction translation (ITLB2) are done.
During the RF stage, three activities occur in parallel. The
instruction decoder (IDEC) decodes the instruction and

checks for interlock conditions. Meanwhile, the instruction tag
check (ITC) is performed between the instruction cache tag
and the page frame number (PFN) from the ITLB's translation.
In parallel with both of the above, the operands are fetched
from the register file (RF).
In the EX stage, if the instruction is a register-to-register
operation, the arithmetic or logical operation is performed
(ALU). If the instruction is a load/store, a data virtual address
is calculated (OVA). If the instruction is a branch, a virtual
branch target address is calculated (IVA).
For load/stores, the OF stage is used to do the first half of
both the data cache fetch (DC1) and the data virtual to
physical address translation (JTLB1). Similarly, the OS stage
does the second half of both the data fetch (DC2) and the data
translation (JTLB2) as well as the load align or store align
(LSA), as appropriate. If the instruction is a branch, the JTLB
is used during OF and OS to translate the branch address and
refill the ITLB if necessary.
The TC stage is used to perform the tag check for load/
stores. During the WB stage the instruction result is written to
the register file.
Smooth pipeline flow is interrupted when cache accesses
miss, data dependencies are detected, or when exceptions
occur. Interruptions that are handled by hardware, such as
cache misses, are referred to as interlocks, while those that
are handled using software are exceptions. Collectively, the
cases of all interlock and exception conditions are referred to
as faults.
Interlocks come in two varieties. Those interlocks which are
resolved by simply stopping the pipeline are referred to as
stalls, while those which require part of the pipeline to advance while holding up another part are slips.
At each cycle, exception and interlock conditions are
checked for all active instructions. The conditions can be
referred back to particular instructions, as each exception or
interlock condition corresponds to a particular pipeline stage.
When an exception condition occurs, the relevant instruction and all that follow it in the pipeline are cancelled. Accordingly, any stall conditions and any later exception conditions
that are referenced to the same instruction are inhibited; there
is no value in servicing stalls for a cancelled instruction. A new

General Purpose Registers

o

63

Multiply/Divide Registers

0

0

63

r1

HI

r2

63

•
•
•
•

0

LO

Program Counter
63

r29

r30

0

PC

r31
2884 drw04

Figure 3. CPU Registers

5.7

4

&I

1DT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

instruction stream is begun, starting execution at a predefined
exception vector. System control coprocessor registers are
loaded with information that will identify the type of exception
and any necessary auxiliary information, such as the virtual
address at which translation exceptions occur.
When a stall condition is detected, all eight instructions,
each in a different stage of the pipeline, are frozen at once.
Often, the stall condition is only detected after parts of the
pipeline have advanced using incorrect data; this occurrence
is referred to as pipeline overrun. When in the stalled state,
parts of the pipeline that are immune to overrun are frozen and
the remainder is permitted to continue clocking. Just before
resuming execution, the pipeline overrun is reversed by
inserting corrected information into the pipeline.
When a slip condition is detected, the pipeline stages which
must advance in order to resolve the dependency continue to
be retired while the dependent stages are held until the
necessary data is available.
Another class of interlocks exists which, since they originate external to the processor, are not referenced to a particular pipeline stage. These interlocks are referred to as external
stalls and are unaffected by the occurrence of exceptions.

Integer Execution Engine
The R4400 implements the extended MIPS Instruction Set
architecture, and thus is fully upwards compatible with applications running on the earlier generation parts. The R4400

includes additions to the instruction set, targeted at improving
performance and capability while maintaining binary compatibility with earlier processors. The extensions result in better
code density, greater multi-processing support, improved
performance for commonly used code sequences in operating system kernels, as well as faster execution of floatingpoint intensive applications. All resource dependencies are
made transparentto the programmer, insuring transportability
amongst implementations of the MIPS instruction set architecture.
In addition to the instruction extensions detailed above,
new instructions have been defined to take advantage of the
64-bit architecture of the processor. When operating as a 32bit processor, the R4400 will take an exception on these new
instructions.
The MIPS integer unit implements a load/store architecture
with single cycle ALU operations (logical, shift, add, sub) and
autonomous multiply/divide unit. The programmer model for
the R4400 includes the register set illustrated in Figure 3. The
register resources include: 32 general purpose orthogonal
integer registers, the HI/La result registers for the intger
multiply/divide unit, and the program counter. In addition, the
on-chip floating-point co-processor adds 32 floating-point
registers, and a floating-point control/status register.

CPO and the TLB
EntryloO
2*

EntryHi
10*

I

Page Mask
5*

Entrylo1
3*

Index
0*

47

Random
1*

TlB

Wired
6*

("Safe" entries)
(See Random Register,
contents of TlB Wired)

o

o

127

X Context
20*

* Register number

ECC
26*

o

Count
9*

ErrorEPC
30*

=Used with Memory Management System.

0

Status
12*

Cause
13*

Context
4*

EPC
14*

BadVAddr
8*

PR Id
15*

Compare
11*

Config
16*

lLAddr
17*

Watchlo
18*

CacheErr
27*

Watch Hi
19*

TagHi
29*

Taglo
28*

=Used with Exception Processing and
diagnostics.

2884 drw 05

Figure 4. The R4400 CPO Registers

5.7

5

IDT79R4400 Family

System Control Co-processor (CPO)
The system control co-processor in the MIPS architecture
is responsible for the virtual memory subsystem, the exception control system, and the diagnostics capability of the
processor. In the MIPS architecture, the system control coprocessor (and thus the kernel software) is implementation
dependent. The R4400 CPO is a superset extension of the
MMU found in the R3000A.
The Memory management unit controls the virtual memory
system page mapping. It consists of an instruction translation
buffer (the ITLB), a Joint TLB (the JTLB), and co-processor
registers used for the virtual memory mapping sub-system.
System Control Co-Processor Registers
The R4400 incorporates all system control co-processor
(CPO) registers on-chip. These registers provide the path
through which the virtual memory system's page mapping is
examined, changed (the operating modes, kernel vs. user
mode, interrupts enabled or disabled, cache features) and
controlled. Also, these registers control exception handling. In
addition, the R4400 includes registers to implement a realtime cycle counting facility, to address reference traps for
debugging, to aid in cache diagnostic testing, and to assist in
data error detection and correction.
Figure 4 illustrates the System Control Co-Processor registers.

COMMERCIAL TEMPERATURE RANGE

Two mechanisms are provided to assist in controlling the
amount of mapped space, and the replacement characteristics of various memory regions. First, the page size can be
configured, on a per-entry basis, to map a page size of 4KB to
16MB (in multiples of 4). A CPO register is loaded with the page
size of a mapping, and that size is entered into the TLB when
a new entry is written. Thus, operating systems can treat
various regions of memory distinctly from applications programs and data files. For example, a typical frame buffer can
be memory mapped using only one TLB entry.
The second mechanism controls the replacement algorithm when a TLB miss occurs. The R4400 uses a Random
Replacement algorithm to select a TLB entry to be written with
a new mapping; however, the processor provides a mechanism whereby a system specific number of mappings can be
locked into the TLB, and thus avoid being randomly replaced.
This facilitates the design of real-time systems, by allowing
deterministic access to critical software.
The joint TLB also contains information to control the cache
coherency protocol for each page. Specifically, each page has
attribute bits to determine whetherthe coherency algorithm is:
uncached, noncoherent, sharable, exclusive, or update. The
use of these attributes, coupled with state information in the
processor caches, enables a wide variety of multiprocessing
strategies to be easily implemented.
Figure 6 shows the format of the TLB entry and registers
used to control the TLB.

Virtual to Physical Address Mapping
The R4400 provides three modes of virtual addressing:
• user mode
• kernel mode
• supervisor mode
This mechanism is available to system software to provide
a secure environment for user processes. Bits in a status
register determine which virtual addressing mode is used. In
the user mode, the R4400 provides a single, uniform virtual
address space of 2GB.
When operating in the kernel mode, four distinct virtual
address spaces, totalling 4GB, are simultaneously available
and are differentiated by the high-order bits of the virtual
address.
The R4400 processor also support a supervisor mode in
which the virtual address space is 2.5GB, divided into two
regions based on the high-order bits of the virtual address.
The three different modes of virtual addressing are shown in
Figure 5. When the R4400 is configured as a 64-bit microprocessor, the virtual address space layout is a compatible
extension of the 32-bit virtual address space layout.

OxFFFFFFFF
OxEOOOOOOO
OxDFFFFFFF
OxCOOOOOOO
OxBFFFFFFF

OxAOOOOOOO
Ox9FFFFFFF

Ox80000000
Ox7FFFFFFF

Kernel virtual address space (kseg3)
Mapped, 0.5g8
Supervisor Virtual address space
(ksseg) Mapped, 0.5g8

Uncached kernel physical address space
(kseg1)
Unmapped, 0.5g8
Cached kernel physical address space
(ksegO)
Unmapped, 0.5g8

~ace (kseg~
apped,2g

JointTLB
For fast virtual-to-physical address decoding, the R4400
uses a large, fully associative TLB which maps 96 virtual
pages to their corresponding physical addresses. The TLB is
organized as 48 pairs of even-odd entries, and maps a virtual
address and address space identifier into the large, 64gB
physical address space.

OxOOOOOOOO
2884 drw 06

Figure 5. Kernel Mode Virtual Addressing (32-bit mode)

5.7

6

II

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

Instruction TLB
The R4400 also incorporates a 2-entry instruction TLB.
Each entry maps a 4KB page. The instruction TLB improves
performance by allowing instruction address translation to
occur in parallel with data address translation. When a miss
occurs on an instruction address translation, the ITLB is filled
from the JTLB. The operation of thE? ITLB is invisible to the
user.
Register File
The R4400 has thirty-two general purpose registers. These
registers are used for scalar integer operations and address
calculation. The registerfile consists of two read ports and one
write port, and uses bypassing to enable the reading and
writing of the same register twice per cycle as well as to
minimize the operation latency in the pipeline.

31

I

0

7

The R4400 ALU consists of the integer adder and logic unit.
The adder performs address calculations in addition to arithmetic operations, and the logic unit performs all shift operations. Each of these units is highly optimized and can perform
an operation in a single superpipeline cycle.
Integer Multiplier/Divider
The R4400 integer multplier and divider units perform
signed and unsigned multiply and divide operations and
execute instructions in parallel with the ALU. The results of the
operation are placed in the MOHI and MOLO registers. The
values can then be transferred to the general purpose register
file using the MFHI/MFLO instructions. The following table
shows the number of processor internal cycles required
between a 32-bit integer multiply or divide and a subsequent
MFHI or MFLO operation, in order that no interlock or stall

PageMask Register 13 12

24

25

ALU

I

0

MASK

0

12

13

MASK = Page comparison mask
Reserved. Must be written as zero; returns zero when read.
0=

EntryHi Register

31

I

13 12

I

VPN2
19

8 7
0

0
ASIO

I

5

I

8

VPN2 = Virtual Page Number divided by two (maps to two pages)
AS/D = Address Space 10 field. An 8-bit field which lets multiple processes share the TLB while each process has a
distinct mapping of otherwise identical virtual page numbers. This is the same ASIO described at the
beginning of this chapter.
0=
Reserved. Must be written as zero; returns zero when read.

30 29

63

64~11

0

PFN

2

24

6

3

5

C

I

2

1

0

10lVIGI

3

30 29

63

64~11

EntryLoO & EntryLo1

6

5

3

0

PFN

C

2

24

3

2

1

0

10lVIGI

PFN = Page Frame Number. Upper bits of the physical address.
C=
Specifies the cache algorithm to be used.
0=
~irty. If this bit is set, the page is marked as dirty and, therefore, writable. This bit is actually a write-protect bit
that software can use to prevent alteration of data.
V=
Valid. If this bit is set, it indicates that the TLB entry is valid; otherwise, a TLBL or TLBS Miss occurs.
G=
Global. If this bit is set in both LaO and Lo1, then ignore the ASIO.
0=
Reserved. Must be written as zero; returns zero when read.
2884 drw07

Figure 6. Fields of an R4400 TLB Entry

5.7

7

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

occurs ..
Operation

Single Word

Double Word

MULT

10

20

DIV

69

133

Floating-Point General Register File
The floating-point register file is made up of sixteen 64-bit
registers which can also be viewed as thirty-two 32-bit floating-point registers. The MI PS architecture supports a
coprocessor load and store double so, when configured as 64bit registers, the floating-point unit can take advantage of the
64-bit wide data cache and issue a co-processor load or store
a doubleword instruction in every cycle.

FLOATING-POINT UNIT
The R4400 incorporates an entire floating-point unit on
chip, including a floating-point register file and execution unit.
The floating-point unit forms a "seamless" interface with the
integer unit, decoding and executing instructions in parallel
with the integer unit.

Floating-Point Control Register File
The floating-point control registers contain a register for
determining configuration and revision information for the
coprocessor and control and status information. These are
primarily involved with diagnostic software, exception handling, state saving and restoring, and control of rounding
modes.

Floating-point Co-Processor
The R4400 floating-point execution unit supports single
and double precision arithmetic, as specified in the IEEE
Standard 754. The execution unit is broken into separate
multiply, divide, and add/convert/square root units, which
allow for overlapped operations. The multiplier is pipelined,
allowing a new multiply to begin every 4 cycles.
As in the IDT79R301 0, the R4400 maintains fully precise
floating-point exceptions while allowing both overlapped and
pipelined operations. Precise exceptions are extremely important in mission-critical environments, such as ADA, and
highly desirable for debugging in any environment.
The floating-point unit's operation set includes floatingpoint add, subtract, multiply, divide, square root, conversion
between fixed-point and floating-point format, conversion
among floating-point formats, and floating-point compare.
Thes operations comply with the IEEE Standard 754.
The following table gives the latencies of some of the
floating-point instructions in internal processor cycles.

Operation

Single
Precision

CACHE MEMORY
In order to keep the high-performance superpipeline full
and operating efficiently, the R4400 incorporates on-chip
instruction and data caches. Each cache has its own 64-bit
data path that can be accessed twice a cycle, so the instruction and data caches can be accessed in parallel with full
pipelining. Combining this feature with a pipelined, single
master clock cycle access of each cache, the cache subsystem provides the integer and floating-point units with an
aggregate bandwidth of 2GB per second at a system clock
frequency of 75MHz.

Instruction Cache
The IDT79R4400 incorporates a direct-mapped on-chip
instruction cache. This virtually indexed, physically tagged
cache is 16KB in size and is protected with byte parity.
Because the cache is virtually indexed, the virtual-tophysical address translation occurs in parallel with the cache
access, thus further increasing performance by allowing these
two operations to occur simultaneously. The tag holds a 24bit physical address and valid bit, and is parity protected.
The instruction cache is 64-bits wide, and can be refilled or
accessed twice per master clock cycle, although the current
IDT79R4400 CPU fetches on 32-bit unit/master cycle for a
peak instruction bandwidth of 400MB/sec. The line size can
be configured as four or eight words to allow different applications to have a line size that delivers optimum performance.

Double
Precision

ADD

4

4

SUB

4

4

MUL

7

8

DIV

23

36

SQRT

54

112

CMP

3

3

FIX

4

4

ROUND

4

4

TRUNC

4

4

FLOAT

5

5

ABS

2

2

MOV

1

1

NEG

2

2

LWC1,LDC1

3

3

SWC1 SDC1

1

1

2884 tbl 0

Data Cache
For fast, single cycle data access, the IDT79R4400 includes an 16KB on-chip data cache.
The data cache is protected with byte parity and its tag is
protected with a single parity bit. It is virtually indexed and
physically tagged to allow simultaneous address translation
and data cache access.
The Data Cache is direct mapped, and its line size can be
configured as four or eight words. The write policy is writeback,
which means that a store to a cache line does not immediately
cause memory to be updated. This increases system performance by reducing bus traffic and eliminating the bottleneck
5.7

8

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

of waiting for each store operation to finish before issuing a
subsequent memory operation.
Associated with the Data Cache is the store buffer. When
the R4400 executes a store instruction, this 2-entry buffer gets
written with the store data while the tag comparison is performed. If the tag matches, then the data gets written into the
Data Cache in the next cycle that the Data Cache is not
accessed. The store buffer allows the R4400 to execute two
stores per master cycle and to perform back-to-back stores
without penalty. Likewise, the R4400 can perform two loads or
a load and store per master cycle without penalty, yielding
1.2GB/sec bandwidth without restrictions on instruction combinations.
When the Data Cache line does need to be written back to
slower memory (either secondary cache or main memory), the
processor writes the data to an internal write buffer which can
hold a line (4 or 8 words) of data. By writing the data to the fast
write buffer, the processor can continue executing instructions without having to wait until the write completes to the
slower memory.
The IDT79R4400 caches are designed for easy and flexible integration in many types of multiprocessor systems. The
Data Cache contains all the necessary state bits to allow the
R4400 to maintain cache coherency across all R4400 processors in a system.

SECONDARY CACHE INTERFACE
The R4400SC and R4400MC support a secondary cache
that can range in size from 128KBs to 4MBs. The cache can
be configured as a unified cache or split into an instruction
cache and a data cache, and it can be designed using industry
standard SRAMs. The lOT R4400 provides all of the secondary cache control circuitry on chip, including ECC.
The secondary cache interface consists of a 128-bit data
bus, a 25-bit tag bus, and 18-bit address bus, and SRAM
control signals. The wide data bus improves performance by
providing a high bandwidth data path to fill the primary
caches. ECC check bits are added to both the data and tag
buses to improve data integrity. All double-bit errors can be
detected and all single bit-errors can be detected and all single
bit-errors can be corrected on both buses.

The secondary cache access time is configurable, providing system designers with the flexibility to tailor the cache
design to specific applications. The line size of the secondary
cache is also configurable and can be 4-,8-, 16-, or 32-words.
The line size of the primary cache must always be less than or
equal to the line size of the secondary cache.
The secondary cache is physically tagged and physically
indexed. The physical cache prevents problems that could
arise due to virtual address aliasing. Also, a physical cache
makes multiprocessing cache coherency protocols easier to
implement. The R4400MC provides a set of cache states and
a mechanism for manipulating the contents and state of the
cache, which are sufficient to implement a variety of cache
coherency protocols, using either bus snooping or directory
based schemes.

SYSTEM INTERFACE
The R4400 supports a 64-bit system interface that can be
used to construct systems as simple as a uniprocessor with a
direct DRAM interface and no secondary cache or as
sopisticated as a fully cache coherent multiprocessor. The
interface consists of a 64-bit Address/Data bus with 8 check
bits and a 9-bit command bus protected with parity. In addition, there are 8 handshake signals. The interface has a
simple timing specification and is capable of transferring data
between the processor and memory at a peak rate of 600MB/
sec at 75MHz.
Figure 7 shows a typical desktop system using the R4400PC.
Similarly, a high-performance desktop workstation/server system can be built using the IDT79R4400SC and adding a
secondary cache.
The system interface allows the processor to access external resources in order to satisfy cache misses and uncached
operations. The IDT79R4400MC, in addition to handling simple
memory and 110 transactions, supports a number of cache
coherency transactions of sufficient generality to support a
variety of cache coherent multiprocessing models. In particular, the interface is designed to support both bus snooping and
directory based multiprocessor models and supports both
write-update and write-invalidate coherency protocols.

Address
DRAM

DRAM
Control

SCSI

R4400PC

Address Data

ENET

Memory liD
Controller

2884 drw08

Figure 7. TYPical Desktop System Block Diagram

5.7

9

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

doubleword, and block transfers on the SysAD bus. In the
case of a sub-doubleword transfer, the low-order 3 address
bits gives the byte address of the transfer, and the SysCmd
bus indicates the number of bytes being transferred.

Figure 8 shows a typical multiprocessor system using the
IDT79R4400MC, an interiace agent, and a secondary cache.

System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to
transfer addresses and data between the R4400 and the rest
of the system. It is protected with an 8-bit check bus, SysADC.
The check bits can be configured as either parity or ECC, for
flexibility in interiacing to either parity or ECC memory systems.
The system interiace is configurable to allow easier interfacing to memory and I/O systems of varying frequencies. The
data rate and the bus frequency at which the R4400 transmits
data to the system interiace are programmable via boot time
mode control bits. Also, the rate at which the processor
receives data is fully controlled by the external device. Therefore, either a low cost interiace requiring no write buffering or
a fast, high performance interiace can be designed to communicate with the R4400. Again, the system designer has the
flexibility to make these price/periomance tradeoffs.
System Command Bus
The R4400 interface has a 9-bit System Command
(SysCmd) bus. The command bus indicates whether the
SysAD bus carries an address or data. If the SysAD carries an
address, then the SysCmd bus also indicates what type of
transaction is to take place (for example, a read orwrite).lfthe
SysAD carries data, then the SysCmd bus also gives information about the data (for example, this is the last data word
transmitted, or the cache state of this line of data is clean
exclusive). The SysCmd bus is bidirectional to support both
processor requests and external requests to the R4400.
Processor requests are initiated by the R4400 and responded
to by an external device. External requests are issued by an
external device and require the R4400 to respond.
The R4400 supports byte, halfword, tribyte, word,

f64

Coherent
Bus

Interface
Agent

! ,. 64
/

•••
., 64 !
/

R4400 MC

R4400 MC

f128

f128

Handshake Signals
There are eight handshake signals on the system interiace.
Two of these, RdRdy and WrRdy are used by an external
device to indicate to the IDT79R4400 whether it can accept a
new read or write transaction. The IDT79R4400 samples
these signals before deasserting the address on read and
write requests.
ExtRqst and Release are used to transfer control of the
SysAD and SysCmd buses between the processor and an
external device. When an external device needs to control the
interiace, it asserts ExtRqst. The IDT79R4400 responds by
asserting Release to release the system interiace to slave
state.
ValidOut and Validln are used by the IDT79R4400 and the
external device respectively to indicate that there is a valid
command or data on the SysAD and SysCmd buses. The
R4400 asserts ValidOut when it is driving these buses with a
valid command or data, and the external device drives Valid In
when it has control of the buses and is driving a valid command
or data.
Finally, there are two signals that are available on the MC
version only and are used in multiprocessing systems. They
are IvdAck and IvdErr, and they are driven by an external
device to indicate the completion status of the current processor invalidate or update request.
R4400 Requests
The R4400 is capable of issuing requests to a memory and
I/O subsystem. The system interiace supports two modes of
operation:
• Secondary Cache mode
• No Secondary Cache mode

{64
Interface
Agent

f64
Interface
Agent

•••

)"128

Memory

, 11'64

.... 1.'64

...--L..-

r--'---

I/O
ctrl

I/O
ctrl

L--.--

o....-r--

I/O Bus
2nd Cache

•••

I/O Bus

2nd Cache
2884 drw 09

Figure 8. Multiprocessor System Using the R4400 MC

5.7

10

•

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

No Secondary Cache Mode
The R4400 without a secondary cache requires a nonoverlapping system interface. This means that only one processor request may be outstanding at a time and that the
request must be serviced by an external device before the
R4400 issues another request. The R4400PC can issue read
and write requests to an external device, and an external
device can issue read and write requests to the R4400.
Figure 9 shows a processor read request. The R4400
asserts Valid Out and simultaneously drives the address and
read command on the SysAD and SysCmd buses. If the
system interface has RdRdy asserted, then the processor
tristates its drivers and releases the system interface to slave
state by asserting Release. The external device can then
begin sending the data to the IDT79R4400.
Secondary Cache Mode
The R4400 with a secondary cache operates in an overlapping bus transfer mode in which multiple system interface
transactions may be issued in parallel. The processor may
issue a combination of read request, an update or invalidate
request, and a write request. For instance, when a dirty cache
line needs to be replaced, the processor issues a read request
immediately followed by a write request, without waiting for
the read data to return. This has the advantage of "hiding" the
write transaction between the read request and read response, thus increasing overall system performance. This
mode of operation is not necessary or useful in R4400

systems without secondary cache since the processor contains a write buffer capable of accepting an entire primary
cache line of data. Overlapping is a superset of non-overlapping system operation.
Figure 10 illustrates a processor request in overlap mode.
This request is made up of a read, invalidate, and write
request. Note that the protocol forthe read, the invalidate, and
the write are all similar to each other, with the exception that
the processor also sends out valid data during the write
request. In Figure 10 the processor write transaction not only
occurs before the read response from the external device, but
it also illustrates how an external device can hold off a write
request through the de assertion of WrRdy.
External Requests
The R4400 responds to requests issued by an external
device. The requests can take several forms. An external
device may need to supply data in response to an R4400 read
request or it may need to gain control over the system
interface bus to access other resources which may be on that
bus. It also may issue cache coherency requests to the
processor, such as a request for the R4400 to update, invalidate, or snoop upon its caches, or to supply a cache line of
data. Additionally, an external device may need to write to the
R4400 interrupt register.
The following is a list of the supported external requests:
• Read
• Write
• Invalidate

TClock

RClock

SysAD

~

(

SysADC

~

(

ValidOut

LJ

Valid In

RdRdy

WrRdy

Release
2884 drw 10

Figure 9. Processor Read Request

5.7

11

1DT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

•
•
•
•

Update
Snoop
Intervention
Null
Figure 11 shows an example of an external snoop request.
The process by which the external device issues the request
is very similar to the way the R4400 issues a request. The
external device first gains ownership of the system interface
by asserting ExtRqst and waiting for the R4400 to assert
Release. The external device then sends in a valid command
by asserting Validln and driving the SysCmd and SysAD
buses with the snoop command and address. The R4400
responds to the request by asserting Valid Out and driving the
SysCmd bus with the cache state of the snooped upon line.

Depending upon the amount and type of data sharing in an
application, the operating system can choose the most appropriate caching strategy.
Support for processor synchronization is provided by the
Load Linked and Store Conditional instructions. The Load
Linked and Store Conditional instructions:
1. Provide a simple mechanism for generating all of the
common synchronization primitives including test-andset, bit-level locks, semaphores, counters, sequencers,
etc. with no additional hardware overhead.
2. Operate in such a fashion that bus traffic is only generated when the state of the cache line changes.
3. Need not lock a system bus-a very important feature
for larger systems.

CACHE COHERENCY CAPABILITY

ADVANCED FEATURES

With the IDT79R4400MC, cache coherence is maintained
in hardware. The system control coprocessor permits the
specification of different caching protocols on a per-page
basis. A page may be:
• uncached
• cached but non-coherent
• cached and coherent exclusive (only one processor
cache contains the data on loads and stores).
• cached and coherent exclusive on writes (write invalidate
scheme-only one processor cache contains the data
when that datum is written to).
• cached and coherent with updates on writes (writeupdate scheme).

The R4400 supports a number of other capabilities in
addition to the standard processor model described above.
Many of these capabilities are selected by the system designer during the processor reset sequence, via the boot time
mode control interface. Features are included to support fault
tolerance, system test, or other system environments.

Boot Time Options
Fundamental operational modes for the processor are
initialized by the boot-time mode control interface. The boottime mode control interface is a serial interface operating at a
very low frequency (Master clock divided by 256). The low

TClock

RClock

SysAD Bus

Addr

Data3

SysCmd Bus

Write

CData

ValidOut

\

Validln

RdRdy

WrRdy

\'--------'/
Release

2884 drw 11

Figure 10. Processor Read, Invalidate, Write Request

5.7

12

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

frequency operation allows the initialization information to be
kept in a low cost EPROM.
Immediately after the VCCOk Signal is asserted, the processor reads a serial bit stream of 256 bits to initialize all
fundamental operational modes. After initialization is complete, the processor continues to drive the serial clock output,
but no further initialization bits are read.

plicit fault-tolerant modes of operation, the design of internal
processor operation is such to support processor synchronization; for example, both the TLB random replacement algorithm, and the on-chip timer, can be forced to known states via
software. Thus, the IDT R4400 family can be used to build
"non-stop" machines across a number of different system
models.

JTAGINTERFACE
The JTAG boundary scan mechanism provides a capability for testing the interconnect between the IDT79R4400
processor, the printed circuit board to which it is attached, and
the other components on the board. In addition the JTAG
boundary scan mechanism provides a rudimentary capability
for low-speed logical testing of the secondary cache RAMs.
The JTAG boundary scan mechanism does not provide any
capability for testing the R4400 processor itself.
In accordance with the JTAG specification the R4400
processor contains a TAP controller, JTAG instruction register, JTAG boundary scan register, JTAG identification register, and JTAG bypass register. However, the R4400 JTAG
implementation provides only the external test functionality of
the boundary scan register.

FAULT TOLERANT SUPPORT
The R4400 has been designed to support varying models
of fault tolerance. These modes include: master/checker
operation and triple-modular redundancy. In addition to ex-

TClock

RClock

SysADBus ____________________________________~~~______~~~______
SysCmdBus ______________________________________~~______~~~______

ValidOut

Validln

ExtRqst

\'-----_----1/

Release
2884 drw 12

Figure 11. External Snoop Request

5.7

13

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

BOOT-TIME MODES
Serial Bit

Value

Mode Setting

0
1

BlkOrder: Block read response ordering.
Sequential ordering.
Sub-block ordering.

0
1

EIBParMode: System interface check bus checking.
SECDED error checking and correcting mode.
Byte parity.

0
1

EndBlt: Byte ordering.
Little Endian.
Big Endian.

0
1

DShMdDis: Dirty shared mode, enables transition to dirty shared state on processor update
successful.
Dirty Shared Enabled.
Dirty Shared Disabled.

0
1

NoSCMode: Specifies presence of secondary cache.
Present.
Not Present.

0
1-3

SysPort: System Interface port width (Bit 6 Most Significant).
64 bits.
Reserved(1)

0
1

SC64BitMd: Secondary cache interface port width.
128 bits.
Reserved(l) ,

0
1

EISpltMd: Secondary cache organization
Unified
Reserved(1)

0
1
2
3

SCBlkSz: Secondary cache line size (Bit 10 Most Significant).
4 words.
8 words.
16 words.
32 words.

0
1
2
3
4
5
6
7
8
9-15

XmitDatPat: System Interface Data Rate (Bit 14 Most Significant).
D
DDx
DDxx
DxDx
DDxxx
DDxxxx
DxxDxx
DDxxxxxx
DxxxDxxx
Reserved(1)

0
1
2
3
4
5-7

SysCkRatio: PC lock to SClock divisor: frequency relationship between SClock, RClock, and
TClock and PClock (Bit 17 MostSignificant).
Divide by 2
Divide by 3
Divide by4
Divide by 6
Divide by 8
Reserved(l)

0

1

2

3

4

5:6

7

8

9:10

11 :14

15:17

18

0

Reserved (Required value)

0
1

TimlntDis: Timer Interrupt enable allows timer interrupts, otherwise the interrupt used by the
timer becomes a general-purpose interrupt.
Enabled
Disabled

19

20

PotUpdDis: Potential invalidate enable (allows potential invalidates to be issued. Otherwise
only normal invalidates are issued).
2884tbl03

5.7

14

IDT79R4400 Family

Serial Bit

COMMERCIAL TEMPERATURE RANGE

Value

Mode Setting

0
1

Enabled
Disabled

0-2
3-15

TWrSUp: Secondary cache write de assertion delay, TWrsup in PCycles (Bit 24 Most Signifi
cant).
Undefined
Number of PCLK cycles (Min 3; Max 15)

0
1-3

TWr2Dly: .Secondary cache write assertion delay 2, TWr2Dly in PCycles (Bit 26 Most Signifi
cant).
Undefined
Number of PCLK cycles (Min 1; Max 3)

0
1-3

TWr1 Diy: Secondary cache write assertion delay 1, TWr1 Diy in PCycles (Bit 28 Most Signifi
cant).
Undefined
Number of PCLK cycles (Min 1; Max 3)

0
1

TWrRc: Secondary cache write recovery time, TWrRc in PCycles either 0 or 1 cycles.
ocycle
1 cycle

0
1

TDis: Secondary cache disable time, TDis in PCycles (Bit 32 Most Significant).
Undefined
Number of PCLK cycles (Min 2; Max 7)

0-2
3-15

TRd2Cyc: Secondary cache read cycle time 2, TRdCyc2 in PCycles (Bit 36 Most Significant).
Undefined
Number of PCLK cycles (Min 3; Max 15)

0-3
4-15

TRd2Cyc: Secondary cache read cycle time 1, TRdCyc1 in PCycles, (Bit 40 Most Significant).
Undefined
Number of PCLK cycles (Min 4; Max 15)

21:24

25:26

27:28

29

30:32

33:36

37:40

41
0
1
42
SCMasterMd
0
1
1
0
43:45(2)

NoMPmode: Secondary cache line is not invalidated
NoMPmode off: after a secondary cache miss, the existing valid caceline is invalidated
(following writeback if necessary)
NoMPmode on: after a secondary cache miss, the existing valid cache line is not invali
dated. Available on the R4400SC to improve performance.
SCM aster Md: selects the type of Master/Checker mode (also see description of mode bit 18).
'SIMasterMd (Bit 18)
Complete Master (required for single-chip operation)
0
Complete Listener (paired with Complete Master)
1
System Interface Master (SIMaster)
0
Secondary Cache Master (SCMaster, paired with SIMaster)
1

0

Reserved.

0
1

Pkg179: R4400 type.
Large (447 pin). SC/MC
Small (179). PC

0
1
2
3
4-7

CycDivisor: This mode determines the clock divisior for the reduced power mode. When the
RP bit in the Status Register is set to one, the pipeline clock is divided by one of the following
values (Bit 49 is Most Significant).
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Reserved(1)

0-1
2-3
4-7

DrvO_50, DrvO_75, Drv1_00: Drive theoutputs in N x MasterClock period (Bit 52 Most
Significant) .
Drive at 0.5 x MasterClockperiod.
Drive at 0.75 x MasterClock period.
Drive at 1.0 x MasterClock period.

46

47:49

50:52

2884 tbl04

5.7

15

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

53:56
0
1-14
15

InitP: Initial values for the state bits that determine the pull-down dildt and switching speed
of the output buffers (Bit 53 Most Significant).
Fastest pull-down rate.
Intermediate pull-down rate.
Slowest pull-down rate.

0
1-14
15

InitN: Initial values for the state bits that determine the pull-up di/dt and switching speed
of the output buffers (Bit 57 Most Significant).
Slowest pull-up rate.
Intermediate pull-up rates.
Fastest pull-up rate.

0
1

EnbIDPLLR: Enables the negative feedback loop that determines the di/dt and switching
speed of the output buffers only during ColdReset.
Disable dildt control mechanism.
Enable di/dt control mechanism.

57:60

61

Serial Bit

Value

Mode Setting

0
1

EnbIDPLL: Enables the negative feedback loop that determines the di/dt and switching
speed of the output buffers during Cold Reset and during normal operation.
Disable dildt control mechanism.
Enable di/dt control mechanism.

0
1

DsbIDPLL: Enables PLLs that match Masterln and produce RClock, TClock, SClock and the
internal clocks.
Enable PLLs.
Disable PLLs.

62

63

SRTristate: Controls when output-only pins are trestated
Only whe ColdReset is asserted.
When Reset or Cold Reset are asserted

64

65-255

0
1
0(2)

Reserved (must be scanned in as zeros).
2884 tbl 05

NOTES:
1. Selecting a Reserved value results in undefined processor behavior.
2. O's must be presented for these reserved values.

PIN DESCRIPTION
The following is a list of interface, interrupt and maintenance pins available on the different package configurations.
Pin Name

Type

Description

Secondary cache interface pins available only on the SC and MC configuration:
SCAddr( 17: 1)

Output

Secondary cache address bus
A 17-bit address bus for the secondary cache.

SCAddrO(W:Z)

Output

Secondary cache address Isb
To minimize loading effect, there are 4 identical copies of this signal.

SCAPar(2:0)

Output

Secondary cache address parity bus
A 3-bit bus that carries the parity of the SCAddr bus and the cache control lines SCOE, SCWR,
SCDCS and SCTCS.

SCData(127:0)

InpuVOutput

Secondary cache data bus
A 128-bit bus used to read or write cache data from/to the secondary cache.

SCDChk(15:0)

InpuVOutput

Secondary cache data ECC bus
A 16-bit bus that carries two 8-bit ECC fields that covers the 128 bits of the SCData from/to
the secondary cache. SCDChk(15:8) corresponds to SCData(127:64) and SCDChk(7:0)
corresponds to SCData(63:0).

SCDCS

Output

Secondary cache data chip select
Chip select enable signal for the secondary cache Ram associated with SCData and SCDChk.

SCOE

Output

Secondary cache output enable
Output enable for the secondary cache RAM.

SCTag(24:0)

InpuVOutput

Secondary cache tag bus
A 25-bit bus used to read or write cache tags from/to the secondary cache.

SCTChk(6:0)

InpuVOutput

Secondary cache tag ECC bus
A 7-bit bus that carries an ECC field covering the SCTag from/to the secondary cache.

5.7

16

II

1DT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (Cont.)
Pin Name

Type

Description

SCTCS

Output

Secondary cache tag chip select
Chip select enable signal for the secondary cache tag RAM associated with SCTag and
SCTChk.

SCWr(W:Z)

Output

Secondary Cache write enable
Write enable for the secondary cache RAM.

System interface pins available on all parts:
ExtRqst

Input

Release

Output

RdRdy

Input

External request
Signals that the system interface needs to submit an external request.
Release interface
Signals that the processor is releasing the system interface to slave state
Read Ready
Signals that an external agent can now accept a processor read, invalidate, or update request
in both secondary cache and no secondary cache mode or can accept a read followed by a
write request in secondary cache mode.

SysAD(63:0)

InpuVOutput

System address/data bus
A 64-bit address and data bus for communication between the processor and an external
agent.

SysADC(7:0)

InpuVOutput

System address/data check bus
An 8-bit bus containing check bits for the SysAD bus.

SysCmd(8:0)

InpuVOutput

System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an
external agent.

SysCmdP

InpuVOutput

System command/data identifier bus parity
A single, even-parity bit for the SysCmd bus.

Validln

ValidOut

WrRdy

Input

Output

Input

Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a
valid command or data identifier on the SysCmd bus.
Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid
command or data identifier on the SysCmd bus.
Write Ready
Signals that an external agent can now accept a processor write request in both non-overlap
and overlap mode.

System interface pins available only on the MC configuration.
IvdAck

Input

Invalidate acknowledge
Signals successful completion of a processor invalidate or update request.

IvdErr

Input

Invalidate error
Signals unsuccessful completion of a processor invalidate or update request.

Interrupt pins available only on the PC configuration:
Int(5:1)

Input

Interrupt
Five of six general processor interrupts, bit-wise ORed with bits 5:1 of the interrupt register.

Interrupt pin available on all devices:
Int(O)

Input

Interrupt
One of six general processor interrupts, bit-wise ORed with bit 0 of the interrupt register.

Non-maskable interrupt pin available on all devices:
NMI

Input

Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.
2884 tbl 06

5.7

17

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (Cant.)
Pin Name

Type

Description

Boot-time mode control interface pins available on all devices:
ModeClock

Modeln

Output

Input

Boot mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred and
fifty six.
Boot mode data in
Serial boot-mode data input.

JTAG interface pins available on all devices:
JTDI

Input

JTAG data in
JTAG serial data in.

JTCK

Input

JTAG clock input
JTAG serial clock input.

JTDO

Output

JTMS

Input

JTAG data out
JTAG serial data out.
JTAG command
JTAG command signal, signals that the incoming serial data is command data.

Maintenance pins available on all devices:
100ut

Output

1/0 output
Output slew rate control feedback loop output. Must be connected to lOin through a delay loop
that models the 10 path from the R4000 to an external agent.

lOin

Input

1/0 input
Output slew rate control feedback loop input (see 100ut).

MasterClock

Input

Master clock
Master clock input at the processor operating frequency.

MasterOut

Output

Master clock out
Master clock output aligned with MasterClock.

RClock(1 :0)

Output

Receive clocks
Two identical receive clocks at the system interface frequency.

SyncOut

Output

Synchronization clock out
Synchronization clock output. Must be connected to Syncln through an interconnect that
models the interconnect between MasterOut, TClock, RClock, and the external agent.

Syncln
TClock(1 :0)

Input
Output

Synchronization clock in
Synchronization clock input. See SyncOut.
Transmit clocks
Two identical transmit clocks at the system interface frequency.

VCCOk

Input

VCC isOK
When asserted, this signal indicates to the R4000 that the +5 volt power supply has been
above 4.75 volts for more than 100 milliseconds and will remain stable. The assertion of
VCCOk initiates the reading of the boot-time mode control serial stream.

Cold Reset

Input

Cold reset
This signal must be asserted for a power on reset or a cold reset. The clocks SClock, TClock,
and RClock begin to cycle and are synchronized with the de-assertion edge of Cold Reset.
Cold Reset must be de-asserted synchronously with MasterOut.

Reset

Input

Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously or
asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be deasserted synchronously with MasterOut.

Fault

Output

VccP

Input

Fault
Mismatch output of boundary comparators.
Quiet VCC for PLL
Quiet Vce for the internal phase locked loop.
5.7

18

II

1DT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (Cont.)
VssP

Input

I

I

Quiet VSS for PLL
Quiet Vss for the internal phase locked loop.

Maintenance pins available only on the SC and MC configurations:
Status(7:0)

Status

I

I

Output
An 8-bit bus that indicates the current operation status of the processor.
2884 tbl 07

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

VTERM

Terminal Voltage with
Respect to GND

Tc

Operating Temperature

Commercial

Unit

-0.5 to +7.0

V

o to +85

°C

RECOMMENDED OPERATION
TEMPERATURE AND SUPPLY VOLTAGE

(Case)
TSTG

Storage Temperature

lOUT

DC Output Current

Grade

Temperature

GND

Vee

R4400 Com.

O°C to +85°C (Case)

OV

5.0±5%

RV4400Com.

O°C to +85°C (Case)

OV

3.3±5%
2884 tbll0

-55 to +125

°C

50

mA

NOTES:
2884 tbl09
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VIN minimum =-3.0V for pulse width less than 15ns. VIN should not exceed
Vcc +0.5 Volts.
3. Not more than one output should be shorted at a time. Duration ofthe short
should not exceed 30 seconds.

DC ELECTRICAL CHARACTERISTICS-R4400 COMMERCIAL TEMPERATURE RANGE
(Vr,r, - fl.O\

+ fl%'

TC':::J!'>e - ODC tn +RflDC)
67MHz

50MHz
Symbol

Parameter

Conditions

Min.

Max.

Min.

VOH

Output HIGH Voltage

IOH = -4mA

3.5

-

3.5

VOHC

Output HIGH Voltage
(MasterOut, TClock,
RClock, SyncOut)(3)

IOH =-4mA

4.0

-

4.0

IOL= 4mA

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

VIL

-

-

75MHz
Max.

-

Min.
3.5
4.0

-

Max.

Units

-

V

V

0.4

V

Vcc+ .5

2.0

Vcc+ .5

V

-0.5(1)

0.8

-0.5(1)

0.8

V

Vcc+ .5

0.8 Vcc

Vcc+ .5

0.8 Vcc

Vcc+ .5

V

-0.5(1)

0.2 Vcc

-0.5(1)

0.2 Vcc

-0.5(1)

0.2 Vcc

V
pF

0.4

2.0

Vcc+ .5

2.0

Input LOW Voltage(1 ,2)

-0.5(1)

0.8

VIHC

Input HIGH Voltage
(MasterClock, Syncln)

0.8 Vcc

VILC

Input LOW Voltage
(MasterClock, Syncln)

0.4

Cln

Input Capacitance

-

10

-

10

-

10

COut

Output Capacitance

-

10

-

10

-

10

pF

ILeak

Input Leakage

-

10

-

10

-

10

JlA

-

20

-

20

-

20

JlA

-

2.8

-

3.2

-

3.6

A

IOLeak

Input/Output Leakage

Icc

Operating Current

Vcc = 5V, Tc=25°C

2884tblll

NOTES:
1. VIL (min.) = -3.0V for pulse width less than 15ns.
2. Except for MasterClock input.
3. Applies to TClock, RClock, MasterOut, and ModeClock outputs.

5.7

19

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS-R4400 COMMERCIAL TEMPERATURE RANGE
(Vcc=5.0V ± 5%; Tcase = ODC to +85 DC) MasterClock and Clock Parameters(2)
50MHz
Symbol

Parameter

Conditions

TMCkHigh

MasterClock High

(3)

TMCkLow

MasterClock Low

(3)

Min.

67MHz

Max.

Min.

75MHz

Max.

Min.

Max.

Units

4

-

3

-

3

4

-

3

-

MasterClock Freq(1)

25

50

25

TMCP

MasterClock Period

20

40

ns

TMCJitter

Clock Jitter
(on RClock, TClock,
MasterOut, SyncOut)

-

±500

-

±500

-

±500

ps

TMCRise

MasterClock Rise Time

-

5

ns

-

5

-

3.5

MasterClock Fall Time

-

4

TMCFall

3.5

ns

TModeCKP

ModeClock Period

-

256*TMCP

-

256*TMCP

-

256*TMCP

ns

TJTAGCKP

JTAG Clock Period

40

-

4*TMCP

15

ns

3

-

67

25

75

MHz

40

13.3

4

-

4*TMCP

-

4*TMCP

NOTES:
1. Operation of the R4400 is only guaranteed with the phase lock loop enabled.
2. Capacitive load for all output timings is SOpF. Deration is per CLD specification.
3. Transition:S; Sns for SO, 67MHz; transition :s; 3.Sns for 7SMHz.

ns

ns
2884 tbl12

EI

SYSTEM INTERFACE PARAMETERS-R4400
50MHz
Symbol
T 00 1,2,3

Parameter
Data Output

Conditions
Max Slew Rate
Modebits[53:56] =0
Modebits[57:60] = 15
Min Slew Rate
Modebits[53:56]
Modebits[57:60]

= 15
=0

75MHz

67MHz

Min.

Max.

Min.

Max.

Min.

Max.

3.5

10

2

7

2

7

ns

6

16

6

12

6

12

ns

-

3.5

-

ns

1

-

ns

Tos

Data Setup

5

-

5

TOH

Data Hold

1.5

-

1.5

Units

NOTES:
2884tbl13a
1. When the dynamic output slew rate control Modebits [61] or [62] are enabled, the initial values for the pull-up and pull-down rates should be set to
the slowest value, Modebits [S3:S6]=1S, Modebits[S7:60]=O.
2. Timings are measured from 1.SV of the clock to 1.SV of signal.
3. Capacitive load for all output timings is SOpF. Deration is per CLD specification.
4. Data Output, Data Setup and Data Hold apply to all logic signals driven out of or driven into the R4000 on the system interface. Secondary cache
signals are specified separately.

BOOT MODE INTERFACE PARAMETERS-R4400
50MHz
Symbol

Parameter

Conditions

Min.

TMOS

Mode Data Setup

3

TMOH

Mode Data Hold

0

67MHz

Max.

-

Min.
3

0

75MHz

Max.

-

Min.

Max.

Units

3

-

MCLKcycles

0

-

MCLKcycles
2884tbl13b

5.7

20

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

SECONDARY CACHE INTERFACE PARAMETERS-R4400
50MHz
Symbol
TSC0 1•2.3

Parameter
PClock to Output

Conditions

Min.

67MHz

75MHz

Max.

Min.

Max.

Min.

Max.

Units

Max Slew Rate
Modebits[53:56] =0
Modebits[57:60] =15

2

10

2

7

2

7

ns

Min Slew Rate
Modebits[53:56] =15
Modebits[57:60] =0

6

16

6

12

6

12

ns

-

-

ns

1
4

15

TSCDS

Data Setup

5

-

5

TSCDH

Data Hold

2

-

1.5

TRd1Cyc4

Cycle length of 4 word Rd

4

15

4

TDis4

Cycles between Rd & Wr

2

7

2

7

2

7

Pcycles

TRd2Cyc 4

Cycle length of 8 word Rd

3

15

3

15

3

15

Pcycles

TWr1Dly4

Cycles bet. Addr & SCWr

1

3

1

3

1

3

Pcycles

TWrRc4

Cycles bet. deassertion of
SCWr to start of next cycle

0

1

0

1

0

1

Pcycles

TWrSUp4

Cycles from second
doubleword to SCWr

2

15

2

15

3

15

Pcycles

TWr2Dly4

Cycles between1st & 2nd
word in 8-word write

1

3

1

3

1

3

Pcycles

15

3.5

ns
Pcycles

2884 tbl14

NOTES:
1. When the dynamic output slew rate control Mode bits [61] or [62] are enabled, the initial values for the pull-up and pull-down rates should be set to
the slowest value, Modebits [53:56]=15, Modebits[57:60]=O.
2. Timings are measured from 1.5V of the Pclock to 1.5V of signal.
3. Capacitive load for all output timings is 50pF. Deration is per CLD specification.
4. Number of cycles is configured through the boot time mode control.

CAPACITIVE LOAD DERATION
50MHz
Symbol
CLD

Parameter
Load Derate

Min.

-

I

I

67MHz

Max.

Min.

2

-

I

I

75MHz

Max.
2

Min.

-

I

I

Max.

Units

2

ns/25pF
2884 tbl15

5.7

21

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS-RV4400 COMMERCIAL TEMPERATURE RANGE

=3.3V ± 5%; Tease =O°C to +85°C)

(VCC

50MHz
Symbol

Parameter

Conditions

Min.

67MHz

Max.

Min.

75MHz

Max.

Min.

2.7

-

2.4

-

0.4

Vcc+ .5

2.0

0.8

-0.5(1)

0.8 Vcc

Vcc+ .5

-0.5(1)

0.2 Vcc

Max.

Units

2.7

-

V

-

0.4

V

Vcc+ .5

2.0

Vcc+ .5

V

0.8

-0.5(1)

0.8

V

0.8 Vcc

Vcc+ .5

0.8 Vcc

Vcc+ .5

V

-0.5(1)

0.2 Vcc

-0.5(1)

0.2 Vcc

V

VOH

Output HIGH Voltage

IOH =-4mA

2.4

-

2.4

VOHC

Output HIGH Voltage
(MasterOut, TClock,
RClock, SyncOut)(3)

IOH = -4mA

2.7

-

VOL

Output LOW Voltage

IOL= 4mA

-

0.4

VIH

Input HIGH Voltage

2.0

VIL

Input LOW Voltage(1 ,2)

-0.5(1)

VIHC

Input HIGH Voltage
(MasterClock, Syncln)

VILC

Input LOW Voltage
(MasterClock, Syncln)

V

Cln

Input Capacitance

-

10

-

10

pF

Output Capacitance

10

-

10

10

pF

ILeak

Input Leakage

-

-

10

COut

10

-

10

-

10

IlA

IOLeak

Input/Output Leakage

20

-

20

-

20

IlA

Icc

Operating Current

-

2.0

-

2.4

-

2.8

A

Vcc = 3.3V, Tc=25°C

2884 tbl11

NOTES.

1. VIL (min.) = -3.0V for pulse width less than 15ns.
2. Except for MasterClock input.
3. Applies to TClock, RClock, MasterOut, and ModeClock outputs.

DC ELECTRICAL CHARACTERISTICS-RV4400 COMMERCIAL TEMPERATURE RANGE
(VCC

=3.3V ± 5%; Tcase =O°C to +85°C)
88MHz

Symbol

Parameter

Conditions

VOH

Output HIGH Voltage

IOH =-4mA

VOHC

Output HIGH Voltage
(MasterOut, TClock,
RClock, SyncOut)(3)

IOH =-4mA

VOL

Output LOW Voltage

IOL = 4mA

VIH

Input HIGH Voltage

VIL

Input LOW Voltage(1 ,2)

VIHC

Input HIGH Voltage
(MasterClock, Syncln)

VILC

Input LOW Voltage
(MasterClock, Syncln)

~m.

100MHz

Max.

-9;5~]1i,;O,2}.tcc
~!
_

v

r-.;1m.

Max.

-¢5\1l:: UtZt~cc

Units

V

-'\

Cln

Input Capacitance

COut

Output Capacitance

pF

ILeak

Input Leakage

IlA

IOLeak

Input/Output Leakage

Icc

Operating Current

pF

IlA
Vcc = 3.3V, Tc=25°C

NOTES:

A
2884tbl11

1. VIL (min.) = -3.0V for pulse width less than 15ns.
2. Except for MasterClock input.
3. Applies to TClock, RClock, MasterOut, and ModeClock outputs.

5.7

22

II

IDT79R4400 Family

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS-RV4400 COMMERCIAL TEMPERATURE RANGE
(Vcc=3.3V ± 5%; Tcase =

aoc to +85°C) MasterClock and Clock Parameters(2)
50MHz

Symbol

Parameter

Conditions

Min.

67MHz

Max.

Min.

75MHz

Max.

Min.

TMCkHigh

MasterClock High

(3)

4

-

3

-

3

TMCkLow

MasterClock Low

(3)

4

-

3

-

3

Max.

-

Units
ns
ns

MasterClock Freq(1)

25

50

25

67

25

75

MHz

TMCP

MasterClock Period

20

40

15

40

13.3

40

ns

TMCJitter

Clock Jitter
(on RClock, TClock,
MasterOut, SyncOut)

-

±500

-

±500

-

±500

ps

TMCRise

MasterClock Rise Time

-

3.5

ns

5

-

4

MasterClock Fall Time

-

5

TMCFall

4

-

3.5

ns

TModeCKP

ModeClock Period

-

256*TMCP

-

256*TMCP

-

256*TMCP

ns

TJTAGCKP

JTAG Clock Period

4*TMCP

-

4*TMCP

-

-

4*TMCP

NOTES:
1. Operation of the R4400 is only guaranteed with the phase lock loop enabled.
2. Capacitive load for all output timings is SOpF. Deration is per CLD specification.
3. Transition::; Sns for 50, 67MHz; transition $ 3.5ns for 7SMHz.

ns
2884tbl12

AC ELECTRICAL CHARACTERISTICS-RV4400 COMMERCIAL TEMPERATURE RANGE
(Vcc=3.3V ± 5%; Tcase =

aoc to +85°C) MasterClock and Clock Parameters(2)
88MHz

100MHz

~JI~~z w.:::!,Max.

Symbol

Parameter

Conds.

~~ :;r;;;;;:.Max.

TMCkHigh

MasterClock High

(3)

?:S:JZt:.'1 I~:::,.~

TMCkLow

MasterClock Low

(3)

2.5,,_:~ :z;pdr

."

25-::::;: ~~8

MasterClock Freq(1)
TMCP

MasterClock Period

TMCJitter

Clock Jitter
(on RClock, TClock,
MasterOut, SyncOut)
MasterClock Rise Time

~- >~Vl.

TMCFall

MasterClock Fall Time

TModeCKP

ModeClock Period

~-:;,~ r;;-:a.5
~ ~@!TMCP

TJTAGCKP

JTAG Clock Period

T"MCRise

3

~.

4*1~'dP~;

NOTES:
1. Operation of the R4400 is only guaranteed with the phase lock loop enabled.
2. Capacitive load for all output timings is 50pF. Deration is per CLD specification.
3. Transition::; 2.SnsS.

5.7

.. 4

1~::j·5

~--4-

:;Qi5~1t >;:::;t:~
2.5

-

.,»>,~1 -

~~ ;!100

..

ns
ns
MHz

.• 40

ns

~500

ps

:s-

I,"""", 2.5
:~
r::=-"""'V" h 2.5
~~

t:=:~t!:

Units

~2'56*TMCP
~,..,..".,>,i

4~~~~L 1~41-

ns
ns
ns
ns
2884tbl12

23

COMMERCIAL TEMPERATURE RANGE

IDT79R4400 Family

SYSTEM INTERFACE PARAMETERS-RV4400
50MHz
Symbol
T 00 1,2,3

Data Output

67MHz

75MHz

Min.

Max.

Min.

Max.

Min.

Max.

Max Slew Rate
Modebits[53:56] = 0
Modebits[57:60] = 15

3.5

10

2

7

2

7

ns

Min Slew Rate
Modebits[53:56] = 15
Modebits[57:60] = 0

6

16

6

12

6

12

ns

-

5

-

-

ns

Parameter

Conditions

Tos

Data Setup

5

TOH

Data Hold

1.5

1.5

3.5
1

Units

ns

NOTES:
2884tb113a
1. When the dynamic output slew rate control Modebits [61) or [62) are enabled, the initial values for the pull-up and pull-down rates should be set to
the slowest value, Modebits [53:56]=15, Modebits[57:60)=0.
2. Timings are measured from 1.5V of the clock to 1.5V of signal.
3. Capacitive load for all output timings is 50pF. Deration is per CLD specification.
4. Data Output, Data Setup and Data Hold apply to all logic signals driven out of or driven into the R4000 on the system interface. Secondary cache
signals are specified separately.

SYSTEM INTERFACE PARAMETERS-RV4400
Symbol

Parameter

Conditions

Units

T 00 1,2,3

Data Output

Max Slew Rate
Modebits[53:56] = 0
Modebits[57:60] = 15

ns

Min Slew Rate
Modebits[53:56] = 15
Modebits[57:60] = 0

ns

Tos

Data Setup

ns

TOH

Data Hold

ns

NOTES:
2884tb113a
1. When the dynamic output slew rate control Modebits [61) or [62) are enabled, the initial values for the pull-up and pull-down rates should be set to
the slowest value, Modebits [53:56] = 15, Modebits [57:60) = O.
2. Timings are measured from 1.5V of the clock to 1.5V of signal.
3. Capacitive load for all output timings is 50pF. Deration is per CLD specification.
4. Data Output, Data Setup and Data Hold apply to all logic signals driven out of or driven into the R4000 on the system interface. Secondary cache
signals are specified separately.

BOOT MODE INTERFACE PARAMETERS-RV4400
50MHz
Symbol

Parameter

Conditions

TMOS

Mode Data Setup

3

TMOH

Mode Data Hold

0

67MHz

Max.

Min.

Min.

-

75MHz

Max.

Min.

3

-

3

0

-

0

Max.

-

Units
MCLKcycies
MCLKcycies
2884tb113b

BOOT MODE INTERFACE PARAMETERS-R4400
88MHz
Symbol

Paramete

TMOS

Mode Data Setup

TMOH

Mode Data Hold

Min.

Max.

100MHz
Min.

, rT~T
Illd'1£ 11\,,-1

]lt~1l1 1"0 Jr-T"fR rfTl~T

1
..h.. 1}.\1 '1; It.l.~ 1. •

Max.

Units
MCLKcycies
MCLKcycles
2884tb113b

5.7

24

COMMERCIAL TEMPERATURE RANGE

IDT79R4400 Family

SECONDARY CACHE INTERFACE PARAMETERS-RV4400
67MHz

50MHz
Symbol
TSC0 1,2,3

Parameter
PC lock to Output

Conditions

Min.

Max Slew Rate
Modebits[53:56]
Modebits[57:60]

=0
=15

Min Slew Rate
Modebits[53:56]
Modebits[57:60]

=15
=0

75MHz

Max.

Min.

Max.

Min.

Max.

Units

2

10

2

7

2

7

ns

6

16

6

12

6

12

ns

-

3.5

-

ns

1

-

TSCDS

Data Setup

5

-

5

TSCDH

Data Hold

2

-

1.5

TRdlCyc4

Cycle length of 4 word Rd

4

15

4

15

4

15

Pcycles

TDis4

ns

Cycles between Rd & Wr

2

7

2

7

2

7

Pcycles

TRd2Cyc 4

Cycle length of B word Rd

3

15

3

15

3

15

Pcycles

TWr1Dly4

Cycles bet. Addr & SCWr

1

3

1

3

1

3

Pcycles

TWrRc4

Cycles bet. deassertion of
SCWr to start of next cycle

0

1

0

1

0

1

Pcycles

TWrSUp4

Cycles from second
doubleword to SCWr

2

15

2

15

3

15

Pcycles

Cycles between1 st & 2nd
word in B-word write

1

3

1

3

1

3

Pcycles

TWr2Dly4

2884tbl14

SECONDARY CACHE INTERFACE PARAMETERS-RV4400
100MHz

BBMHz
Symbol

Parameter

Conditions

Min.

TSC0 1,2,3

PC lock to Output

Max Slew Rate
Modebits[53:56]
Modebits[57:60]
Min Slew Rate
Modebits[53:56]
Modebits[57:60]

TSCDS

=0
=15

.~~ l~.

~

,-~J.

.

.

~-

=15
=0

"90SPECfp92 (exact figures
are system-dependent).
The R4600 provides complete upward application-software compatibility with the IOT79R3000™ family of microprocessors, including the lOT RISControlier™79R30sfM I
R30S2TM/R3041TM/R3071TM/R3081TM as well as the
IOT79R4000 family of microprocessors. Microsoft Windows
NT and UNISOFT Unix VA operating systems insure the
availability of thousands of applications programs, geared
to provide a complete solution to a large number of processing needs. An array of development tools facilitates
the rapid development of R4600-based systems, enabling
a wide variety of customers to take advantage of the MIPS
Open Architecture philosophy.
Together with the R4000 family, the R4600 provides a
compatible, timely, and necessary evolution path from 32bit to true, 64-bit computing. The original design objectives
of the R4000 clearly mandated this evolution path; the
result is a true 64-bit processor fully compatible with 32-bit

HARDWARE OVERVIEW
The R4600 family brings a high-level of integration
designed for high-performance computing. The key elements of the R4600 are briefly described below. A more
detailed description of each of these subsystems is available in the User's Manual.
Pipeline
The R4600 uses a S-stage pipeline similar to the
IOT79R3000. The simplicity of this pipeline allows the
R4600 to be lower cost and lower power than super-scalar
or super-pipelined processors. Unlike the R3000, the
R4600 does virtual-to-physical translation in parallel with
cache access. This allows the R4600 to operate at twice
the frequency of the R3000 and to support a larger TLB for
address translation.
Compared to the 8-stage R4000 pipeline, the R4600 is
more efficient (requires fewer stalls).
Figure 2 shows the R4600 pipeline.

Figure 1. CPU Registers

General Purpose Registers

o

63

Multiply/Divide Registers

0

o

63

r1

HIGH

o

63

r2

·
·
·
·

LOW

Program Counter

o

63

r29

PC

r30
r31

5.8

2

IDT79R4600

COMMERCIAL TEMPERATURE RANGE
Figure 2. R4600 Pipeline

11

10

21

11

1R

2R

1A

2A

10

20

1W

2W

11

21

1R

2R

1A

2A

10

20

1W

2W

11

21

1R

2R

1A

2A·

10

20

1W

11

21

1R

2R

1A

2A

10

11

21

1R

2R

1A

12
13
14

one cycle

11-1 R
21
2A-20
10
10-20
2R
2R
2R
2R
1A
1A-2A
1A
2A
1A
2W

Instruction cache access
Instruction virtual to physical address translation in ITLB
Data cache access and load align
Data virtual to physical address translation in OTLB
Virtual to physical address translation in JTLB
Register file read
Bypass calculation
Instruction decode
Branch address calculation
Issue or slip decision
Integer add, logical, shift
Data virtual address calculation
Store align
Branch decision
Register file write

point registers, and a floating-point control/status register.

Integer Execution Engine
The R4600 implements the MIPS Instruction Set architecture, and thus is fully upward compatible with applications running on the earlier generation parts. The R4600
includes the same additions to the instruction set as found
in the R4000 family of microprocessors, targeted at improving performance and capability while maintaining binary
compatibility with earlier processors. The extensions result
in better code density, greater multi-processing support,
improved performance for commonly used code
sequences in operating system kernels, and faster execution of floating-point intensive applications. All resource
dependencies are made transparent to the programmer,
insuring transportability among implementations of the
MIPS instruction set architecture.
In addition to the instruction extensions detailed above,
new instructions have been defined to take advantage of
the 64-bit architecture of the processor. When operating as
a 32-bit processor, the R4600 will take an exception on
these new instructions.
The MIPS integer unit implements a load/store architecture with single cycle ALU operations (logical, shift, add,
sub) and autonomous multiply/divide unit. The register
resources include: 32 general-purpose orthogonal integer
registers, the HIGH/LOW result registers for the integer
multiply/divide unit, and the program counter. In addition,
the on-chip floating-point co-processor adds 32 floating-

Register File
The R4600 has thirty-two general-purpose registers.
These registers are used for scalar integer operations and
address calculation. The register file consists of two read
ports and one write port, and is fully bypassed to minimize
operation latency in the pipeline.

ALU
The R4600 ALU consists of the integer adder and logic
unit. The adder performs address calculations in addition to
arithmetic operations, and the logic unit performs all logical
and shift operations. Each of these units is highly optimized
and can perform an operation in a single pipeline cycle.
Integer Multiply/Divide
The R4600 uses the floating-point unit to perform integer
multiply and divide. The results of the operation are placed
in the HIGH and LOW registers. The values can then be
transferred to the general purpose register file using the
MFHIIMFLO instructions. Table 1 below shows the number
of processor internal cycles required between an integer
multiply or divide and a subsequent MFHI or MFLO operation, in order that no interlock or stall occurs.

5.8

3

IDT79R4600

COMMERCIAL TEMPERATURE RANGE

Table 2: Floating-Point Cycles
Table 1: Integer multiply/divide cycles

MULT
DIV

32-bit

64-bit

8 or 11

10 or 13

42

74

Floating-Point Co-Processor
The R4600 incorporates an entire floating-point co-processor on chip, including a floating-point register file and
execution units. The floating-point co-processor forms a
"seamless" interface with the integer unit, decoding and
executing instructions in parallel with the integer unit.

Double
Precision

ADD

4

4

SUB

4

4

MUL

8

8

DIV

32

61

SQRT

31

60

CMP

3

3

FIX

4

4

FLOAT

6

6

ABS

1

1

MOV

1

1

NEG

1

1

LWC1, LDC1

2

2

SWC1, SDC1

1

1

System Control Co-processor (CPO)
The system control co-processor in the MIPS architecture is responsible for the virtual memory sub-system, the
exception control system, and the diagnostics capability of
the processor. In the MIPS architecture, the system control
co-processor (and thus the kernel software) is implementation dependent. The R4600 CPO is essentially identical to
that of the R4000PC, except that the WatchLo and WatchHi
registers are no longer present and the Index CACHE ops
use an extra address bit to select one of the two sets (the
R4000 caches are direct mapped, instead of two-way set
associative).
The Memory management unit controls the virtual memory system page mapping. It consists of an instruction
address translation buffer (the ITLB), a data address translation buffer (the DTLB), a Joint TLB (the JTLB), and coprocessor registers used for the virtual memory mapping
sub-system.

Table 2: Floating-Point Cycles
Single
Precision

Double
Precision

Floating-Point General Register File
The floating-point register file is made up of thirty-two 64bit registers. With the LDC1 and SDC1 instructions the
floating-point unit can take advantage of the 64-bit wide
data cache and issue a co-processor load or store doubleword instruction in every cycle.
The floating-point control register space contains two
registers; one for determining configuration and revision
information for the coprocessor and one for control and status information. These are primarily involved with diagnostic software, exception handling, state saving and restoring,
and control of rounding modes.

Floating-Point Units
The R4600 floating-point execution units supports single
and double precision arithmetic, as specified in the IEEE
Standard 754. The execution unit is broken into a separate
multiply unit and a combined add/convertJdivide/square
root unit. Overlap of multiplies and add/subtract is supported. The multiplier is partially pipelined, allowing a new
multiply to begin every 6 cycles.
As in the IDT79R3010A and IDT79R4000, the R4600
maintains fully precise floating-point exceptions while
allowing both overlapped and pipe lined operations. Precise
exceptions are extremely important in mission-critical environments, such as ADA, and highly desirable for debugging in any environment.
The floating-point unit's operation set includes floatingpoint add, subtract, multiply, divide, square root, conversion between fixed-point and floating-point format, conversion among floating-point formats, and floating-point
compare. These operations comply with the IEEE Standard
754.
Table 2 below gives the latencies of some of the floatingpoint instructions in internal processor cycles.

Operation

Single
Precision

Operation

System Control Co-Processor Registers
The R4600 incorporates all system control co-processor
(CPO) registers on-chip. These registers provide the path
through which the virtual memory system's page mapping
is examined and changed, exceptions are handled, and
operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition,
the R4600 includes registers to implement a real-time cycle
counting facility, to aid in cache diagnostic testing, and to
assist in data error detection.
Figure 3 shows the CPO registers.

5.8

4

EI

IDT79R4600

COMMERCIAL TEMPERATURE RANGE

Virtual to Physical Address Mapping
The R4600 provides three modes of virtual addressing:
• user mode
• supervisor mode
• kernel mode
This mechanism is available to system software to provide a secure environment for user processes. Bits in a status register determine which virtual addressing mode is
used. In the user mode, the R4600 provides a single, uniform virtual address space of 256GB (2GB for 32-bit
mode).
When operating in the kernel mode, four distinct virtual
address spaces, totalling 1024GB (4GB in 32-bit mode),
are simultaneously available and are differentiated by the
high-order bits of the virtual address.
The R4600 processors also support a supervisor mode in
which the virtual address space is 256.5GB (2.5GB in 32bit mode), divided into three regions based on the highorder bits of the virtual address.
Figure 4 shows the address space layout for 32-bit operation.
When the R4600 is configured as a 64-bit microprocessor, the virtual address space layout is an upward compatible extension of the 32-bit virtual address space layout.

amount of mapped space, and the replacement characteristics of various memory regions. First, the page size can
be configured, on a per-entry basis, to map a page size of
4KB to 16MB (in multiples of 4). A CPO register is loaded
with the page size of a mapping, and that size is entered
into the TLB when a new entry is written. Thus, operating
systems can provide special purpose maps; for example, a
typical frame buffer can be memory mapped using only one
TLB entry.
The second mechanism controls the replacement algorithm when a TLB miss occurs. The R4600 provides a random replacement algorithm to select a TLB entry to be
written with a new mapping; however, the processor provides a mechanism whereby a system specific number of
mappings can be locked into the TLB, and thus avoid being
randomly replaced. This facilitates the design of real-time
systems, by allowing deterministic access to critical software.
The joint TLB also contains information to control the
cache coherency protocol for each page. Specifically, each
page has attribute bits to determine whether the coherency
algorithm is: uncached, non-coherent write-back, noncoherent write-through write-allocate, non-coherent writethrough no write-allocate. Non-coherent write-back is typically used for both code and data on the R4600; the writethrough modes support more efficient frame buffer
accesses than the R4000 family, cache coherency is not
supported, however.

JointTLB
For fast virtual-to-physical address decoding, the R4600
uses a large, fully associative TLB which maps 96 Virtual
pages to their corresponding physical addresses. The TLB
is organized as 48 pairs of even-odd entries, and maps a
virtual address and address space identifier into the large,
64GB physical address space.
Two mechanisms are provided to assist in controlling the

Instruction TLB
The R4600 also incorporates a 2-entry instruction TLB.
Each entry maps a 4KB page. The instruction TLB
improves performance by allowing instruction address

Figure 3. The R4600 CPO Registers
Count
g*
PageMask
5*

EntryloO
2*

EntryHi
10*

Entrylo1
3*

41

Index
0*
TlB
Random
1*

I
(entries protected
from TlBWR)

I

Wired
6*

* Register number

5.8

I

Status
12*

I

EPC
14*

I I
I I
I

Compare
11*

"
II

Cause
13*

I

Context
4*

II

XContext
20*

BadVAddr
8*

II

lLAddr
17*

I

PRld
15*

II

Config
16·

I
I

TagHi
2g·
ECC
26*

II
I

Taglo
28*

5

IDT79R4600

COMMERCIAL TEMPERATURE RANGE

Cache Memory
In order to keep the R4600's high-performance pipeline
full and operating efficiently, the R4600 incorporates onchip instruction and data caches that can be accessed in a
single processor cycle. Each cache has its own 64-bit data
path and can be accessed in parallel. The cache subsystem provides the integer and floating-point units with an
aggregate bandwidth of 2.4GB per second at a pipelineclock frequency of 150M Hz.

translation to occur in parallel with data address translation.
When a miss occurs on an instruction address translation,
the least-recently used ITLB entry is filled from the JTLB.
The operation of the ITLB is invisible to the user.

DataTLB
The R4600 also incorporates a 4-entry data TLB. Each
entry maps a 4KB page. The data TLB improves performance by allowing data address translation to occur in parallel with data address translation. When a miss occurs on
an data address translation, the DTLB is filled from the
JTLB. The DTLB refill is pseudo-LRU: the least recently
used entry of the least recently used half is filled. The operation of the DTLB is invisible to the user.
Furthermore, the large 2-way set-associative caches
increase emulation performance of DOS and Windows 3.1
applications when running under Windows NT.

Instruction Cache
The R4600 incorporates a two-way set associative onchip instruction cache. This virtually indexed, physically
tagged cache is 16KB in size and is protected with word
parity.
Because the cache is virtually indexed, the virtual-tophysical address translation occurs in parallel with the
cache access, thus further increasing performance by
allowing these two operations to occur simultaneously. The
tag holds a 24-bit physical address and valid bit, and is parity protected.
The instruction cache is 64-bits wide, and can be refilled
or accessed in a single processor cycle. Instruction fetches
require only 32 bits per cycle, for a peak instruction bandwidth of 600MB/sec at 150MHz. Sequential accesses take
advantage of the 64-bit fetch to reduce power dissipation,
and cache miss refill writes 64 bits-per-cycle to minimize
the cache miss penalty. The line size is eight instructions
(32 bytes) to maximize performance.

Figure 4. Kernel Mode Virtual Addressing (32-bit mode)

OxFFFFFFFF

Kernel virtual address space
(kseg3)
Mapped, O.5GB

OxEOOOOOOO
OxDFFFFFFF

OxCOOOOOOO
OxBFFFFFFF

Supervisor virtual address space
(sseg)
Mapped, O.5GB

Data Cache
For fast, single cycle data access, the R4600 includes a
16KB on-chip data cache that is two-way set associative
with a fixed 32-byte (eight words) line size.
The data cache is protected with byte parity and its tag is
protected with a single parity bit. It is virtually indexed and
physically tagged to allow simultaneous address translation
and data cache access
The normal write policy is write back, which means that a
store to a cache line does not immediately cause memory
to be updated. This increases system performance by
reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. Software can however select
write-through on a per-page basis when it is appropriate,
such as for frame buffers.
Associated with the Data Cache is the store buffer. When
the R4600 executes a Store instruction, this single-entry
buffer gets written with the store data while the tag comparison is performed. If the tag matches, then the data is written into the Data Cache in the next cycle that the Data
Cache is not accessed (the next non-load cycle). The store
buffer allows the R4600 to execute a store every processor
cycle and to perform back-to-back stores without penalty.

Uncached kernel physical address space
(kseg1)
Unmapped, O.5GB

OxAOOOOOOO
Ox9FFFFFFF

Cached kernel physical address space
(ksegO)
Unmapped, O.5GB

Ox80000000
Ox7FFFFFFF

User virtual address space
(useg)
Mapped, 2.0GB

Write buffer
Writes to external memory, whether cache miss writebacks or stores to uncached or write-through addresses,

OxOOOOOOOO

5.8

6

II

IDT79R4600

COMMERCIAL TEMPERATURE RANGE

use the on-chip write buffer. The write buffer holds up to
four 64-bit address and data pairs. The entire buffer is used
for a data cache write back and allows the processor to proceed in parallel with memory update. For uncached and
write-through stores, the write buffer significantly increases
performance over the R4000 family of processors.

System Command Bus
The R4600 interface has a 9-bit System Command
(SysCmd) bus. The command bus indicates whether the
SysAD bus carries an address or data. If the SysAD carries
an address, then the SysCmd bus also indicates what type
of transaction is to take place (for example, a read or write).
If the SysAD carries data, then the SysCmd bus also gives
information about the data (for example, this is the last data
word transmitted, or the cache state of this data line is
clean exclusive). The SysCmd bus is bidirectional to support both processor requests and external requests to the
R4600. Processor requests are initiated by the R4600 and
responded to by an external device. External requests are
issued by an external device and require the R4600 to
respond.
The R4600 supports one to eight byte and block transfers on the SysAD bus. In the case of a sub-doubleword
transfer, the low-order 3 address bits gives the byte
address of the transfer, and the SysCmd bus indicates the
number of bytes being transferred.

System Interface
The R4600 supports a 64-bit system interface that is
compatible with the R4000PC system interface. This interface operates from two clocks provided by the R4600,
TClock[1 :OJ and RClock[1 :0], at some division of the internal clock.
The interface consists of a 64-bit Address/Data bus with
8 check bits and a 9-bit command bus protected with parity.
In addition, there are 8 handshake signals and 6 interrupt
inputs. The interface has a simple timing specification and
is capable of transferring data between the processor and
memory at a peak rate of 600MS/sec at 150M Hz.
Figure 5 on page 7 shows a typical system using the
R4600. In this example two banks of DRAMs are used to
supply and accept data with a DDxxDD data pattern.

Handshake Signals
There are six handshake signals on the system interface.
Two of these, Rd Rdy and WrRdy are used by an external
device to indicate to the R4600 whether it can accept a new
read or write transaction. The R4600 samples these signals before deasserting the address on read and write
requests.
ExtRqst and Release are used to transfer control of the
SysAD and SysCmd buses between the processor and an
external device. When an external device needs to control
the interface, it asserts ExtRqst. The R4600 responds by
asserting Release to release the system interface to slave
state.
ValidOut and Validln are used by the R4600 and the
external device respectively to indicate that there is a valid
command or data on the SysAD and SysCmd buses. The
R4600 asserts Valid Out when it is driving these buses with
a valid command or data, and the external device drives

System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to
transfer addresses and data between the R4600 and the
rest of the system. It is protected with an 8-bit parity check
bus, SysADC.
The system interface is configurable to allow easier interfacing to memory and I/O systems of varying frequencies.
The data rate and the bus frequency at which the R4600
transmits data to the system interface are programmable
via boot time mode control bits. Also, the rate at which the
processor receives data is fully controlled by the external
device. Therefore, either a low cost interface requiring no
read or write buffering or a faster, high performance interface can be designed to communicate with the R4600.
Again, the system designer has the flexibility to make these
price/performance trade-offs.

Figure 5. Typical Desktop System Block Diagram

Address

Control
SCSI

NE

32

emory 1/
Controller.....~------~
R4600

9
2

11

5.8

7

IDTI9R4600

COMMERCIAL TEMPERATURE RANGE

Validln when it has control of the buses and is driving a
valid command or data.

• Null
Boot Time Options
Fundamental operational modes for the processor are
initialized by the boot-time mode control interface. The
boot-time mode control interface is a serial interface operating at a very low frequency (MasterClock divided by 256).
The low-frequency operation allows the initialization information to be kept in a low-cost EPROM; alternatively the
twenty-or-so bits could be generated by the system interface ASIC or a simple PAL.
Immediately after the VCCOK Signal is asserted, the processor reads a serial bit stream of 256 bits to initialize all
fundamental operational modes. After initialization is complete, the processor continues to drive the serial clock output, but no further initialization bits are read.

Non-overlapping System Interface
The R4600 requires a non-overlapping system interface,
compatible with the R4000PC. This means that only one
processor request may be outstanding at a time and that
the request must be serviced by an external device before
the R4600 issues another request. The R4600 can issue
read and write requests to an external device, and an
external device can issue read and write requests to the
R4600.
The R4600 asserts Valid Out and simultaneously drives
the address and read command on the SysAD and
SysCmd buses. If the system interface has RdRdy
asserted, then the processor tristates its drivers and
releases the system interface to slave state by asserting
Release. The external device can then begin sending the
data to the R4600.
Figure 6 on page 8 shows a processor block read
request and the external agent read response. The read
latency is 4 cycles (ValidOut to Validln), and the response
data pattern is DDxxDD. Figure 6 on page 8 shows a processor block write.

JTAG Interface
For compatibility with the R4000PC, the R4600 supports
the JTAG interface pins, with the serial input connected to
serial output. Boundary scan is not supported.
Boot-Time Modes
The boot-time serial mode stream is defined in Table 3
below. Bit 0 is the bit presented to the processor when
VCCOK is asserted; bit 255 is the last.

External Requests
The R4600 responds to requests issued by an external
device. The requests can take several forms. An external
device may need to supply data in response to an R4600
read request or it may need to gain control over the system
interface bus to access other resources which may be on
that bus. It also may issue requests to the processor, such
as a request for the R4600 to write to the R4600 interrupt
register.
The following is a list of the supported external requests:
• Write

Power Management
CPO is also used to control the power management for
the R4600. This is the standby mode and it can be used to
reduce the power consumption of the internal core of the
CPU. The standby mode is entered by executing the WAIT
instruction with the SysAD bus idle and is exited by any
interrupt.

Figure 6. Processor Block Read
TClock

SysAD

SySCm_d______

~~~________~~_________~

\'---~/
RdRdy

\'---_/

------------------------------------------------------------------------------

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IDT79R4600

COMMERCIAL TEMPERATURE RANGE

Table 3: Boot time mode stream
Table 3: Boot time mode stream
Mode bit
0
4 .. 1

Mode bit
11

Description
reserved (must be zero)

1

Write back data rate

12

O~D.

14.. 13

Clock divisor

2~4.

Output driver strength
10 ~ 100% strength (fastest).
11 ~ 83% strength.
00 ~ 67% strength.
01 ~ 50% strength (slowest)

o -> TClock[O] enabled

bit 16"

o -> TClock[1] enabled
1 -> TClock[1] disabled

bit 17"

5~7.

o -> RClock[O] enabled
1 -> RClock[O] disabled

6~8.

7 reserved

10 .. 9

reserved (must be zero)

bit 15"

3~5.

4~6.

bit 18"

o ~ Little endian.
~

Disabled

1 -> TClock[O] disabled

1 ~3.

1

~

Reserved

0~2.

8

Disable the timer interrupt on Int[5].

o ~ Enabled

1 ~ DDx.
2 ~ DDxx.
3 ~ DxDx.
4 ~ DDxxx.
5 ~ DDxxxx.
6 ~ DxxDxx.
7 ~ DDxxxxxx.
8 ~ DxxxDxxx.
9-15 reserved·
7 .. 5

Description

o -> RClock[1] enabled
1 -> RClock[1] disabled

Big endian

00 ~ R4000 compatible.
01 ~ reserved.
10 ~ pipelined writes.
11 ~ write re-issue

255 .. 19

must be zero
valid for rev 2.0 only. otherwise must be zero

Figure 7. Processor Block Write

SYSAD _________~~_________
syscm_d________~~_________~L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

\'--_ _ _1
RdRdy
WrRdy

\'---~/

------------------------------------------------------------------------------------------------------------------------------------------------5.8

9

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COMMERCIAL TEMPERATURE RANGE

Comparison of R4600/R4700 and R4400
This section compares features of the R4600/R4700 to the earlier R4400 PC. Table 1.20 to Table 1.26 highlight some of
the differences between the R4600/R4700 and the R4400 PC. This list is not exhaustive.

Table 4: System interface comparison between R4400PC and R4600
Item

R4400 PC

R4600/R4700

I/O

R4400: TIL compatible
RV4400: LV CMOS

R4600/R4700: TIL-compatible (5V ±O.5%)
RV4600/RV4700: LVCMOS (3.3V±O.3V)

Package

179-pin ceramic PGA

179-pin PGA and 208-pin MQUAD

JTAG

yes

no (serial out connected directly to serial in)

Block transfer sizes

16B or 32B

32B

Sclock divisor

2,3,4,6,8

2,3,4,5,6, 7, 8

Non-block writes

max throughput of 4 sclock cycles

two new system interface protocol options that
support 2 sclock cycle throughput (remains 4 in
compatibility mode)

Serial configuration

as described in R4000 User's Guide

different, as described in Table 9.2 on page 9-7

Address bits 63 .. 56 on reads and
writes

zero

bits 19 .. 12 of virtual address

Uncached and write-through stores

uncached stores are buffered in 1-entry
uncached store buffer (write through not
possible)

uncached and write-though stores buffered in 4entry write buffer

SysADC

parity only

same

SysADC for non-data cycles

parity

zero

SysCmdP

parity

zero

Parity error during write back

use Cache Error exception

output bad parity

Error bit in data identifier of read
responses

Bus Error if error bit set for any doubleword

only check error bit of first doubleword; all other
error bits ignored

Parity error on read data

Bus Error if parity error in any doubleword

bad parity written to cache; take Cache Error
exception if bad parity occurs on doublewords
that the processor is waiting for

Block writes

1-2 null cycles between address and
data

o cycles between address and data

Release after Read Request

variable latency

o latency

SysAD value for x cycles of writeback data pattern

data bus undefined

data bus maintains last D cycle value

SysAD bus use after last D cycle of
write back

data bus undefined

trailing x cycles (e.g. DDxxDDxx, not DDxxDD)
follow rule in entry immediately preceding

Output slew rate

dynamic feedback control

simple CMOS output buffers with 2-bit static
strength control

100ut output

output slew rate control feedback loop
output

driven HIGH, do not connect
(reserved for future output)

lOin input

output slew rate control input

should be driven high
(reserved for future input)

GrpRunB output

do not connect

same
(reserved for future output)

GrpStaliB input

should be connected to VCC

same
(reserved for future input)

FaultB output pin

indicates compare mismatch

driven HIGH, do not connect
(reserved for future output)

5.8

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10

IDT79R4600

COMMERCIAL TEMPERATURE RANGE

Table 5: Cache comparison between R4400PC and R4600
Item

R4400 PC

R4600/R4700

Cache Sizes

16KB Instruction cache, 16KB Data cache

16KB Instruction cache, 16KB Data cache

Cache Line Sizes

software selectable between 16B and 32B

fixed at 32B

Cache Index

vAddr13 .. 0

vAddr12..o

Cache Tag

p Addr35 .. 12

same

Cache Organization

direct mapped

2-way set associative

Data cache write policy

write-allocate and write-back

write-allocate or not based on TLB entry,
write-through or not based on TLB entry

Data cache miss

stall, output address, copy dirty data to
writeback buffer, refill cache, output writeback data

same, with FIFO to select the set to refill

Data order for block reads

sub-block ordering

same

Data order for block writes

sequential

same

Instruction cache miss
restart

restart after all data received and written to
cache

same

Data cache miss restart

restart after all data received and written to
cache

restart on first doubleword, send subsequent doublewords to response buffer

Instruction Tag

2-bit cache state

1-bit cache state

Cache miss overhead

5-8 cycles

3 cycles

Instruction cache parity

1 parity bit per 8 data bits

1 parity bit per 32 data bits

Data cache parity

1 parity bit per 8 data bits

same

Table 6: TLB comparison between R4400PC and R4600
Item

R4400 PC

R4600/R4700

Instruction virtual
address translation

2-entry ITLB

same

ITLB miss

1 cycle penalty, refilled from JTLB, LRU
replacement

1 cycle on branch, jump, and ERET, 2
cycles otherwise, refilled from JTLB, LRU
replacement

Data virtual address
translation

done directly in JTLB

4-entry DTLB

DTLB miss

n.a.

1 cycle penalty, refilled from JTLB, pseudoLRU replacement

JTLB

48 entries of even/odd page pairs, fully
associative

same

Page size

4KB, 16KB, ... , 16MB

same

Multiple entry match in
JTLB

sets TS in Status and disables TLB until
Reset to prevent damage

no damage for multiple match; no detection or shutdown implemented

Virtual address size

VSIZE = 40

same

Physical address size

PSIZE = 36

same

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IDT79R4600

COMMERCIAL TEMPERATURE RANGE

Table 7: Pipeline comparison between R4400PC and R4600
Item

R4400 PC

ALU latency

1 cycle

1 cycle

Load latency

3 cycles

2 cycles

Branch latency

4 cycles (2 cycle penalty for taken
branches)

2 cycles (no penalty for taken branches)

Store buffer (not write
buffer)

2 doublewords

1 doubleword

Integer multiply

integer multiply hardware, 1 cycle to issue

done in floating-point multiplier, 4 cycles to
issue

Integer divide

done in integer datapath adder, slips until
done

done in floating-point adder, 4 cycles to
issue

Integer multiply

HIGH and LOW available at the same time

LOW available one cycle before HIGH

Integer divide

HIGH and LOW available at the same time

HIGH available one cycle before LOW

HIGH and LOW hazards

yes, HIGH and LOW written early in pipeline

no, HIGH and LOW written after W
2 cycles

R4600/R4700

MFHI/MFLO latency

1 cycle

SLLV, SRLV, SRAV

2 cycles to issue

1 cycle to issue

DSLL, DSRL, DSRA,
DSLL32, DSRL32,
DSRA32, DSLLV, DSRLV,
DSRAV

2 cycles to issue

1 cycle to issue

Table 8: Coprocessor 0 comparison between R4400PC and R4600
Item

R4400 PC

R4600/R4700

WatchLo, WatchHi

implemented

unimplemented (no watch registers)

Config

as described in R4000 User's Guide

subset

Status

as described in R4000 User's Guide, but
RP not functional

no TS or RP

Low-power standby mode

no

WAIT instruction disables internal clock,
freezing pipeline and other state; resume
on interrupt

MFCO/MTCO hazard

only hazardous for certain cpO register
combinations

always hazardous -- detected and 1-cycle
slip inserted

EntryLoO, EntryL01

as described in R4000 User's Guide

two new cache algorithms added to C field
for non-coherent write-through

TagLo, TagHi, ECC,
Cache Err

R4400SC bits implemented but meaningless

Only bits meaningful on R4400 PC imp lemented

TagLo

as described in R4000 User's Guide

bits 5 .. 3 read/writeable but otherwise
unused, bit 2 used for F bit

Exceptions

as described in R4000 User's Guide (VCEI
and VCED not possible)

VCEI, VCED, and WATCH exceptions not
implemented

Index CACHE ops
I Fill CACHE op

use vAddr13.A to select line

use vAddr13 to select set, vAddr12 .. 5 to
select line of set

Index Store Tag CACHE
op

Status.CE ignored

TagLo.P stored if Status.CE set

PRld

Imp = Ox04

R4600: Imp = Ox20
R4700: Imp = Ox21

S.B

12

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COMMERCIAL TEMPERATURE RANGE

Table 9: Coprocessor 1 comparison between R4400PC and R4600
Item

R4400 PC

R4600/R4700

Possible exception stall

only for operands that can cause exceptions

some simplifications in detection hardware

Floating-point divide

separate divide unit

done in floating-paint adder

Floating-paint square root

done in floating-point adder

same

Converts to/from 64-bit
integer

uses unimplemented for integer operands/
results with more than 53 bits of precision

handles full 64-bit operands and results

Floating-point registers

Status.FR enables all 32 floating point registers

same

FCRO

Imp

= Ox05

R4600: Imp
R4700: Imp

5.8

= Ox20
= Ox21

13

IDT79R4600

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION
The following is a list of interface, interrupt, and miscellaneous pins available on the R4600.
Pin Name

Type

Description

System interface:
ExtRqst*

Input

External request
Signals that the system interface needs to submit an external request.

Release*

Output

Release interface
Signals that the processor is releasing the system interface to slave state

RdRdy*

Input

Read Ready
Signals that an external agent can now accept a processor read.

WrRdy*

Input

Write Ready
Signals that an external agent can now accept a processor write request.

Validln*

Input

Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus
and a valid command or data identifier on the SysCmd bus.

ValidOut*

Output

Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and
a valid command or data identifier on the SysCmd bus.

SysAD(63:0)

Input/Output

System address/data bus
A 64-bit address and data bus for communication between the processor and an externalagent.

SysADC(7:0)

Input/Output

System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.

SysCmd(8:0)

Input/Output

System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an
external agent.

SysCmdP

Input/Output

Reserved system command/data identifier bus parity
for the R4600 unused on input and zero on output.

Clock/control interface:
MasterClock

Input

Master clock
Master clock input at one half the processor operating frequency.

MasterOut

Output

Master clock out
Master clock output aligned with MasterClock.

RClock(1 :0)

Output

Receive clocks
Two identical receive clocks at the system interface frequency.

TClock(1 :0)

Output

Transmit clocks
Two identical transmit clocks at the system interface frequency.

100ut

Output

Reserved for future output
Always HIGH.

lOin

Input

Reserved for future input
Should be driven HIGH.

SyncOut

Output

Synchronization clock out
Synchronization clock output. Must be connected to Syncln through an interconnect that
models the interconnect between MasterOut, TClock, RClock, and the external agent.

Syncln

Input

Synchronization clock in
Synchronization clock input. See SyncOut.

5.8

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IDT79R4600

COMMERCIAL TEMPERATURE RANGE

Pin Name

Type

Description

Fault*

Output

Fault
Always HIGH.

VeeP

Input

Quiet Vee for PLL
Quiet Vee for the internal phase locked loop.

VssP

Input

Quiet Vss for PLL
Quiet Vss for the internal phase locked loop.

Int*(5:0)

Input

Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.

NMI*

Input

Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.

Interrupt interface:

Initialization interface:
Veeok

Input

Vee is OK
When asserted, this signal indicates to the R4600 that the 3.3V (5.0V) power supply has
been above 3.0V (4.5V) for more than 100 milliseconds and will remain stable. The
assertion of Veeok initiates the reading of the boot-time mode control serial stream.

ColdReset*

Input

Cold reset
This signal must be asserted for a power on reset or a cold reset. The clocks SClock,
TClock, and RClock begin to cycle and are synchronized with the de-assertion edge of
Cold Reset. ColdReset must be de-asserted synchronously with MasterOut.

Reset*

Input

Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously
or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset
must be de-asserted synchronously with MasterOut.

ModeClock

Output

Boot mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six.

Modeln

Input

Boot mode data in
Serial boot-mode data input.

5.8

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IDT79R4600

COMMERCIAL TEMPERATURE RANGE

Standby Mode Operations
The R4600 provides a means to reduce the amount of power consumed by the internal core when the CPU would otherwise not be performing any useful operations. This is known as "Standby Mode" .

Entering Standby Mode
Executing the WAIT iunstruction enables interrupts and enters Standby mode. When the WAIT instruction finishes the W
pipe-stage, if the SysAd bus is currently idle, the internal clocks will shut down, thus freezing the pipeline. The PLL, internal
timer, some of the input pin clocks (Int[5:0]*, NMI*, ExtRqst*, Reset*, and ColdReset*) and the output clocks (TClock[1 :0],
RClock[1 :0], SyncOut, Modeclock and MasterOut) will continue to run. If the conditions are not correct when the WAIT
instruction finishes the W pipe-stage (i.e. the SysAd bus is not idle), the WAIT is treated as a NOP.
Once the CPU is in Standby Mode, any interrupt, including the internally generated timer interrupt or ExtRqst*, will cause
the CPU to exit Standby Mode.

ABSOLUTE MAXIMUM RATINGS(1)

Symbol

Rating

RV4600
3.3V±5%

R4600
5.0V±5%

Commercial

Commercial

Unit

VTERM

Terminal Voltage with
respect to GND

-0.5(2) to +4.6

-0.5(2) to +7.0

V

Tc

Operating Temperature
(case)

o to +85

o to +85

°C

T SIAS

Case Temperature
Under Bias

-55 to +125

-55 to +125

°C

TSTG

Storage Temperature

-55 to +125

-55 to +125

°C

liN

DC Input Current

20(3)

20(3)

mA

lOUT

DC Output Current

50

50

mA

II

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VIN minimum =-2.0V for pulse width less than 15ns. VIN should not exceed Vee +0.5 Volts.
3. When VIN < OV or VIN > Vee
4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.

RECOMMENDED OPERATION TEMPERATURE AND SUPPLY VOLTAGE
Vee

Grade

Commercial

Temperature

O°C to +85°C (Case)

GND

OV

RV4600

R4600

3.3V±5%

5.0V±5%

5.B

16

IDT79R4600

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS D
(Vee = 3.3±5%, TCASE = ODC to +85 C)
RV4600
100MHz

Parameter

Minimum

VOH

RV4600
133MHz

Maximum

-

VOL

Minimum

-

-

Conditions

Maximum

-

O.1V

Vee O.1V

VOL

COMMERICAL TEMPERATURE RANGE RV4600

O.1V

-

O.4V

-

IIOUTI= 20uA

-

VeeO.1V

O.4V
lIoUTI=4mA

-

VOH

2.4V

V IL

-O.5V

O. 2Vee

-O.5V

O. 2Vee

-

V IH

O. 7V ee

V ee +
O.5V

O. 7Vee

Vee +
O.5V

-

2.4V

VoHe

-

-

-

-

-

VILe

-

-

-

-

-

-

-

-

-

V IHe

-

CIN

-

10pF

-

10pF

-

COUT

-

10pF

-

10pF

-

I/OLEAK

-

20uA

-

20uA

InpuVOutput Leakage

RV4600
100MHz

Parameter

Typical(12)
System Condition:

Maximum

RV4600
133MHz
Typical(12)

100/50MHz

-

125mA

-

175mA

133/44MHz

-

-

175mA

C L = OpF(11)

-

225mA

C L = 50pF

standby

Icc

Conditions

Maximum

575mA

875mA

775mA

1150mA

C L = OpF, No SysAd
activity(11)

650mA

1100mA

850mA

1375mA

C L = 50pF R4xOO compatible writes
Te = 25°C

650mA

1275mA

850mA

1525mA

C L = 50pF Pipelined
writes or Write re-issue,
Te = 25°C

active

5.8

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IOTI9R4600

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (Vcc=3.3V ± 5%; T CASE = ooe to +85°C)

COMMERICAL TEMPERATURE RANGE RV4600

Clock Parameters

Parameter

Symbol

RV4600
100MHz

Test Conditions

Min
MasterClock HIGH
MasterClock LOW

RV4600
133MHz

Max

Min

Units

Max

tMCHIGH

Transition

~

5ns

4

-

3

-

ns

tMCLOW

Transition

~

5ns

4

-

3

-

ns

-

-

25

50

25

67

MHz

MasterClock Period

t MCP

-

20

40

15

40

ns

MasterClock Frequency(5)

Clock Jitter for MasterClock

tJitterln(11)

-

-

±250

-

±250

ps

Clock Jitter for MasterOut,
SyncOut, TClock, RClock

tJitterOut (11)

-

-

±500

-

±500

ps

MasterClock Rise Time

tMCRise (11)

-

-

5

-

4

ns

MasterClock Fall Time

tMcFall(11)

-

-

5

-

4

ns

ModeClock Period

tModeCKP

-

-

256*
tMCP

-

256*
tMcp

ns

II

NOTES:

5. Operation of the R4600 is only guaranteed with the Phase Lock Loop enabled.

System Interface Parameters(6)

Parameter

Data Output(7)

Symbol

t OM = Min
too Max

=

Data Setup

tos

Data Hold

tOH

RV4600
100MHz
(Vee= 3.3±5%)

Test Conditions

mode14 .. 13

trise = 5ns
tfall = 5ns

Units

Min

Max

Min

Max

1.0

9

1.0

9

ns

2.0

15

2.0

12

ns

3.5

-

3.5

-

ns

1.5

-

1.5

-

ns

=10 (fastest)

mode14 .. 13 = 01 (slowest)

RV4600
133MHz
(Vee= 3.3±5%)

Boot Time Interface Parameters
Parameter

Symbol

Test Conditions

RV4600
100MHz
Min

Max

RV4600
133MHz
Min

Units

Max

Mode Data Setup

tos

-

3

-

3

-

Master Clock Cycle

Mode Data Hold

tOH

-

0

-

0

-

Master Clock Cycle

5.8

18

IDT79R4600

COMMERC~LTEMPERATURERANGE

Capacitive Load Deration
RV4600100MHz
Parameter

Units
Min

Load Derate

RV4600133MHz

Symbol
Max

-

C LD

Min

-

2

DC ELECTRICAL CHARACTERISTICS D
(V cc= 5.0±5%, TCASE =oDe to +85 C)
R4600100MHz

Max
2

ns/25pF

COMMERICAL TEMPERATURE RANGE R4600

R4600 133MHz

Parameter

Conditions
Minimum

Maximum

-

VOL

O.1V

VOH

Vee0.1V

VOL

-

-

Minimum

Maximum

-

O.1V

O.4V

-

IloUTI= 20uA

-

Ve e 0.1V

-

O.4V
"ouTI= 4mA

-

VOH

3.5V

VIL

-0.5V

0.8V

-0.5V

0.8V

-

V IH

2.0V

Vee +
0.5V

2.0V

Vee +
0.5V

-

3.5V

liN

-

±10uA

-

±10uA

CIN

-

10pF

-

10pF

-

COUT

-

10pF

-

10pF

-

I/OLEAK

-

±20uA

-

±20uA

Input/Output Leakage

R4600 100MHz

o ~VIN ~Vee

R4600 133MHz

Parameter

Conditions

Typical(12)
System Condition:
standby

Icc

Maximum

Typical(12)

100/50MHz

Maximum

133/44MHz

-

-

175mA

-

225mA

C L = OpF(ll)

-

250mA

-

325mA

C L = 50pF

875mA

1000mA

1175mA

1300mA

C L = OpF, No SysAd
activity(ll)

975mA

1200mA

1275mA

1510mA

CL = 50pF R4xOO compatible writes
Te = 25°C

1100mA

1400mA

1300mA

1675mA

CL = 50pF Pipe lined
writes or Write re-issue,
Te = 25°C

active

S.B

19

IDT79R4600

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS -

COMMERICAL TEMPERATURE RANGE R4600

(Vcc=5.0V ± 5%; T CASE = O°C to +85°C)

Clock Parameters
100MHz
Symbol

Parameter

Units
Min

MasterClock HIGH
MasterClock LOW

133MHz

Test Conditions

tMCHIGH

Transition::; 5ns

tMCLOW

Transition::; 5ns

Max

4

-

4

-

Min

Max

3

-

3

-

ns
ns

-

-

25

50

25

67

MHz

tMcp

-

20

40

15

40

ns

Clock Jitter for MasterClock

tJitterln(11)

-

-

±250

ps

Clock Jitter for MasterOut,
SyncOut, TClock, RClock

-

-

±500

-

±250

tJitte rOut(11)

±500

ps

MasterClock Rise Time

tMCRise

(11)

-

-

5

-

4

ns

MasterClock Fall Time

tMcFall(11)

-

-

5

-

4

ns

ModeClock Period

tModeCKP

-

-

256*
tMCP

-

256*
t MCP

ns

JTAG Clock Period

tJTAGCKP

-

-

4*
tMCP

-

4*
tMCP

ns

MasterClock Frequency(5)
MasterClock Period

II

NOTES:

6. Operation of the R4600 is only guaranteed with the Phase Lock Loop enabled.

AC ELECTRICAL CHARACTERISTICS -

COMMERICAL TEMPERATURE RANGE R4600

(Vcc = 5.0V ± 5%; T CASE = O°C to +85°C)

System Interface Parameters(6)

Parameter

Symbol

R4600
100MHz

Test Conditions

Min

Data Output(7)

Data Setup
Data Hold

R4600
133MHz

Max

Min

mode14 .. 13 = 10 (fastest)

1.0

9

1.0

9

ns

mode14 .. 13 = 11

1.3

11

1.3

10

ns

mode14 .. 13 = 00

1.6

13

1.6

11

ns

mode14 .. 13 = 01 (slowest)

2.0

15

2.0

12

ns

3.5

-

3.5

-

ns

1.5

-

1.5

-

ns

too

tos
tOH

Units

Max

trise = 5ns
tfall = 5ns

NOTES:

7. Timings are measured from 1.5V of the clock to 1.5V of the signal.
8. Capacitive load for all output timings is 50pF.
9. Timings are measured from 1.5V of the clock to 1.5V of the signal.
10.Capacitive load for all output timings is 50pF.
11.Guaranteed by Design.
12.Typical integer instruction mix and cache miss rates.

5.8

20

IDT79R4600

COMMERCIAL TEMPERATURE RANGE

Boot Time Interface Parameters

Parameter

Symbol

Test Conditions

R4600
100MHz
Min

R4600
133MHz

Max

Min

Units

Max

Mode Data Setup

tos

-

3

-

3

-

MasterClock cycles

Mode Data Hold

tOH

-

0

-

0

-

MasterClock cycles

CAPACITIVE LOAD DERATION
R4600 100MHz
Parameter

Units
Min

Load Derate

R4600133MHz

Symbol
CLD

-

Max

2

Min

-

Max
2

5.8

ns/25pF

21

IOTI9R4600

PHYSICAL SPECIFICATIONS -

COMMERCIAL TEMPERATURE RANGE

MQUAD

MS208
Top View

5.8

II

22

IDT79R4600

COMMERCIAL TEMPERATURE RANGE

RV4600 MQUAD package pin-out
Pin
1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

Function

Pin

Function

Pin

Function

Pin

Function

N.C;.

53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104

N.C.

105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156

N.C;.

l~{

N.C;.

N.C.
N.C.
N.C.
Vee
Vss
SysAD21
SysAD53
RdRdyB
Modeln
SysAD22
SysAD54
Vee
Vss
ReleaseB
SysAD23
SysAD55
NMIB
Vee
Vss
SysADC2
SysADC6
Vee
SysAD24
Vee
Vss
SysAD56
N.C.
SysAD25
SysAD57
Vee
Vss
IOOut
SysAD26
SysAD58
lOin
Vee
Vss
SysAD27
SysAD59
ColdResetB
SysAD28
Vee
Vss
SysAD60
ResetB
SysAD29
SysAD61
Vee
Vss
N.C.
N.C.

158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

N.C.
RClockO
RClock1
SyncOut
SysAD30
Vee
Vss
SysAD62
MasterOut
SysAD31
SysAD63
Vee
Vss
VeeOK
SysADC3
SysADC7
Vee
vss
N.C.
N.C.
N.C.
N.C.
N.C.
VeeP
VssP
N.C.
N.C.
MasterClock
Vee
Vss
Syncln
Vee
Vss
N.C.
SysADC5
SysADC1
N.C.
Vee
Vss
SysAD47
SysAD15
N.C.
SysAD46
Vee
Vss
SysAD14
N.C.
TClock1
TClockO
N.C.
N.C.

N.C.
Vss
Vee
SysAD45
SysAD13
FaultB
SysAD44
Vss
Vee
SysAD12
SysCmdP
SysAD43
SysAD11
Vss
Vee
SysCmd8
SysAD42
SysAD10
SysCmd7
Vss
Vee
SysAD41
SysAD9
SysCmd6
SysAD40
N.C.
N.C.
Vss
Vee
SysAD8
SysCmd5
SysADC4
SysADCO
Vss
Vee
SysCmd4
SysAD39
SysAD7
SysCMD3
Vss
Vee
SysAD38
SysAD6
ModeClock
WrRdyB
SysAD37
SysAD5
Vss
Vee
N.C.
N.C.

N.C.
SysCmd2
SysAD36
SysAD4
SysCmd1
Vss
Vee
SysAD35
SysAD3
SysCmdO
SysAD34
Vss
Vee
N.C.
N.C.
SysAD2
IntB5
SysAD33
SysAD1
Vss
Vee
IntB4
SysAD32
SysADO
IntB3
Vss
Vee
IntB2
SysAD16
SysAD48
IntB1
Vss
Vee
SysAD17
SysAD49
IntBO
SysAD18
Vss
Vee
SysAD50
ValidlnB
SysAD19
SysAD51
Vss
Vee
ValidOutB
SysAD20
SysAD52
ExtRqstB
N.C.
N.C.

N.C. pins should be left floating for maximum flexibility and compatibility with future designs.
5.8

23

IDTI9R4600

COMMERCIAL TEMPERATURE RANGE

R4600/RV4600 PGA Pin-out
Function

Pin

Cold Reset

T14

ExtRqst

U2

Fault

816

Reserved

a (NC)

U10

Reserved I (Vcc)

T9

lOin

T13

100ut

U12

Into

N2

Int1

L3

Int2

K3

Int3

J3

Int4

H3

Int5

F2

JTCK

H17

JTDI

G16

JTDO

F16

JTMS

E16

MasterClock

J17

MasterOut

P17

ModeClock

84

Modeln

U4

NMI

U7

RClockO

T17

RClock1

R16

RdRdy

T5

Release

V5

Reset

U16

Syncln

J16

SyncOut

P16

SysADO

J2

SysAD1

G2

SysAD2

E1

SysAD3

E3

SysAD4

C2

Function

Pin

Function

Pin

SysAD5

C4

SysAD40

C10

SysAD6

85

SysAD41

C11

SysAD7

86

SysAD42

813

SysAD8

89

SysAD43

A15

SysAD9

811

SysAD44

C15

SysAD10

C12

SysAD45

817

SysAD11

814

SysAD46

E17

SysAD12

815

SysAD47

F17

SysAD13

C16

SysAD48

L2

SysAD14

D17

SysA049

M3

SysAD15

E18

SysAD50

N3

SysAD16

K2

SysAD51

R2

SysAD17

M2

SysAD52

T3

SysAD18

P1

SysAD53

U3

SysAD19

P3

SysA054

T6

SysAD20

T2

SysAD55

TI

SysAD21

T4

SysAD56

T10

SysAD22

U5

SysAD57

T11

SysAD23

U6

SysAD58

U13

SysAD24

U9

SysAD59

V15

SysAD25

U11

SysAD60

T15

SysAD26

T12

SysAD61

U17

SysAD27

U14

SysAD62

N16

SysAD28

U15

SysAD63

N17

SysAD29

T16

SysADCO

C8

SysAD30

R17

SysADC1

G17

SysAD31

M16

SysADC2

T8

SysAD32

H2

SysADC3

L16

SysAD33

G3

SysADC4

88

SysAD34

F3

SysADC5

H16

SysAD35

D2

SysADC6

U8

SysAD36

C3

SysADC7

L17

SysAD37

83

SysCmdO

E2

SysAD38

C6

SysCmd1

03

SysAD39

C7

SysCmd2

82

5.8

II

24

IDT79R4600

COMMERCIAL TEMPERATURE RANGE

Function

Pin

Function

Pin

Function

Pin

SysCmd3

A5

Vee

U1

Vss

V9

SysCmd4

87

Vee

V3

Vss

V11

SysCmd5

C9

Vee

V6

Vss

V13

SysCmd6

810

Vee

V8

Vss

V16

SysCmd7

812

Vee

V10

Vss

V18

SysCmd8

C13

Vee

V12

JTCK

H17

SysCmdP

C14

Vee

V14

JTOI

G16

TClockO

C17

Vee

V17

JTOO

F16

TClock1

016

Vss

A3

JTMS

E16

VCCOk

M17

Vss

A6

Validln

P2

Vss

A8

ValidOut

R3

Vss

A10

WrRdy

C5

Vss

A12

VeeP

K17

Vss

A14

VssP

K16

Vss

A17

Vee

A2

Vss

A18

Vee

A4

Vss

81

Reserved I (NC)

A7

Vss

C18

Vee

A9

Vss

01

Vee

A11

Vss

F18

Vee

A13

Vss

G1

Vee

A16

Vss

H18

Vee

818

Vss

J1

Vee

C1

Vss

K18

Vee

018

Vss

L1

Vee

F1

Vss

M18

Vee

G18

Vss

N1

Vee

H1

Vss

P18

Vee

J18

Vss

R18

Vee

K1

Vss

T1

Vee

L18

Vss

U18

Vee

M1

Vss

V1

Vee

N18

Vss

V2

Vee

R1

Vss

V4

Vee

T18

Vss

V7

5.8

25

IDTI9R4600

COMMERCIAL TEMPERATURE RANGE

2 3 4 5 6 7 8 9 1011 1213 1415 1617 18

G

•
•
•
•
•
•
•
•
•
•
•
•

F

•

V
U

T
R
P
N
M
L
K

J
H

E
D
C

B
A

•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
•
•
•
•
•
•
•
•
R4600/RV4600
•
•

•
•

•

Pinout
Bottom

•
•

•
•
•
• • • • • • • • • • • • •
• • • • • • • • • • • • •
• • • • • • • • • • • • • •
2

•
•
•
•

• •
• •

•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•

•
•
•

•

• • •

•
•
•
•

•
•
•
•

•
•
•
•

V
U

T
R
P
N
M
L
K

J
H

G
F

E
D
C

B
A

II

3 4 5 6 7 8 9 1011 1213 1415 1617 18
2884 drw 12

IDT79YY

XXXX

Configuration

Device
Type

999
---Speed

A

A
Package

Process/
Temperature
Range

~

Blank

Commercial (O°C to +85°C, Case)

G
MS

PGA 179
MQUAD 208

100
133

100MHz
133MHz

4600

16KB Each of 1-, D-Cache

R
RV

5V
3.3V

VALID COMBINATIONS

lOT

79R4600 - 100, 133
79RV4600 - 100, 133

G, MS Packages
G, MS Packages

5.8

26

ORtoN

EMBEDDED
64-BIT RISC ORION
MICROPROCESSOR

Integrated DeviceTechnology,lnc.

FEATURES:

IDT79R4650™

Preliminary

• Low-power operation
- Less than 3W peak internal power at 100MHz
- Active power management powers-down inactive units
- Standby mode power consumption <200mW
• Upward software compatible with IDT RISControlier Family
• Large, efficient on-chip caches
- Separate 8kB Instruction and 8kB Data caches
- Over 1500MB/sec bandwidth from internal caches
- 2-set associative
- Write-back and write-through support
- Cache locking to facilitate deterministic response
• Bus compatible with R4600/0rion family
- System interfaces to 67 MHz, provides bandwidth up to
533 MB/S
- Direct interface to 32-bit wide or 64-bit wide systems
- Synchronized to external reference clock for mUlti-master
operation
• Improved real-time support
- Fast interrupt decode
- Optional cache locking

• High-performance embedded 64-bit microprocessor
- 64-bit integer operations
- 64-bit registers
- 80M Hz, 100MHz, 133MHz operation frequency
• High-performance DSP capability
- 66.7 Million Integer Multiply-Accumulate Operations/
sec @ 133 MHz
- 44 MFlops floating point operations @ 133MHz
• High-performance microprocessor
- 133 MIPS at 133MHz
- 66.7 M Mul-Add/second at 133MHz
- 44 MFLOP/s at 133MHz
- >300,000 dhrystone (2.1)/sec capability at 133MHz
(175 dhrystone MIPS)
• High level of integration
- 64-bit, 133 MIPS integer CPU
- 44MFIops Single precision floating-point unit
- 8KB instruction cache; 8KB data cache
- Integer multiply unit with 66.7M Mul-Add/sec

BLOCK DIAGRAM:
133 MIPS 64-bit Orion CPU

System Control Coprocessor

44MFLOPS Single-Precision FPA

Address Translationl
Cache Attribute Control

64-bit register file

FP register file

64-bit adder

E
0

Exception Management
Functions

E
0

CJ

CJ
G>

.=G>

.~

Store Aligner

FP AddlSub/CvtI
Div/Sqrt

Co

G>

a::

J~

Co

a::

Logic Unit

PacklUnpack

E

E

Load aligner

High-Performance
Integer MuHiply

ill

FP Multiply

ill

t

.~

1

Control Bus

~

1

Instruction Cache
SetA
(Lockable)

.-

.....

Jil

-

.....

Instruction Cache
Set B

J

1

ill

11r

Data Bus

Instruction Bus

+

ill

~

~

1.

Data Cache
SetA
(Lockable)

32-/64-bH
Synchronized
System Interface

Data Cache
Set B

r

The lOT logo is a registered trademark and Orion, R4650, R4650, R4600, R308t, R3052, R305t, R3041, RISController, and RISCore are trademarks of Intergrated Device Technology,lnc.

SEPTEMBER 1995

COMMERCIAL TEMPERATURE RANGE
© 1995 Integrated Device Technology, Inc.

5.9

DSC9084/1

1

IDT79R4650

COMMERCIAL TEMPERATURE RANGE

troller™79R3051 ™/R3052™ /R3041 ™ /R3071 ™ /R3081 ™ as
well as the IOT79R4600 family of microprocessors. An
array of development tools facilitates the rapid development of R4650-based systems, enabling a wide variety
of customers to take advantage of the high-performance
capabilities of the processor while maintaining short time to
market goals.
The 64-bit computing capability of the R4650 enables a
wide variety of capabilities previously limited by the lower
bandwidth and bit-manipulation rates inherent in 32-bit
architectures. For example, the R4650 can perform loads
and stores from cached memory at the rates of 8-bytes
every clock cycle, doubling the bandwidth of an equivalent
32-bit processor. This capability, coupled with the high
clock rate for the R4650 pipeline, enables new levels of
performance to be obtained from embedded systems.
This data sheet provides an overview of the features and
architecture of the R4650 CPU. A more detailed description
of the processor is available in the IDT79R4650 Processor
Hardware User's Manual, available from lOT. Further information on development support, applications notes, and
complementary products are also available from your local
lOT sales representative.

DESCRIPTION:
The IOT79R4650 is a low-cost member of the lOT Orion
family, targeted to a variety of performance hungry
embedded applications. The R4650 continues the Orion
tradition of high-performance through high-speed pipelines,
high-bandwidth caches and bus interface, 64-bit architecture, and careful attention to efficient control. The R4650
reduces the cost of this performance relative to the R4600,
by removing functional units that are frequently unneeded
for many embedded applications, such as double-precision
floating point arithmetic and a TLB.
The R4650 adds features relative to the R4600, reflective
of its target applications. These features enable system
cost reduction (e.g. optional 32-bit system interface) as well
as higher performance for certain types of systems (e.g.
cache locking, improved real-time support, integer OSP
capability).
The R4650 supports a wide variety of embedded
processor-based applications, such as consumer game
systems, multi-media functions, internetworking
equipment, switching equipment, and printing systems.
Upwardly software-compatible with the RISControlier
family, and bus- and upwardly software-compatible with the
lOT Orion family, the R4650 will serve in many of the same
applications, but, in addition supports other applications
such as those requiring integer OSP functions.
The R4650 brings Orion performance levels to lower cost
systems. Orion performance is preserved by retaining large
on-chip caches that are two-way set associative, a streamlined high-speed pipeline, high-bandwidth, 64-bit
execution, and facilities such as early restart for data cache
misses. These techniques combine to allow the system
designer over 2GB/sec aggregate internal bandwidth, 533
MB/sec bus bandwidth, 175 VAX MIPS, 44MFlops, and
66.7 M Multiply-add/second.
The R4650 provides complete upward applicationsoftware compatibility with the IOT79R3000™ family of
microprocessors, including the lOT RISCon-

HARDWARE OVERVIEW
The R4650 family brings a high-level of integration
designed for high-performance computing. The key
elements of the R4650 are briefly described below. A more
detailed description of each of these subsystems is
available in the User's Manual.

Pipeline
The R4650 uses a 5-stage pipeline similar to the
IDT79R3000 and the IDT79R4600. The simplicity of this
pipeline allows the R4650 to be lower cost and lower power
than super-scalar or super-pipelined processors. Unlike
superscalar processors, applications that have large data
dependencies or that require a great deal of load/stores

General Purpose Registers

o

63

Multiply/Divide Registers

63

0

0
HI (Accumulate HI)

r1

63

r2

·
·
·
·

0
LO (Accumulate LO)

Program Counter

63

31

0

PC

r29
Figure 1: CPU Registers

5.9

2

II

IDT79R4650

I

10

COMMERCIAL TEMPERATURE RANGE

11

I

21

11

I

1R

I

2R

I

1A

I

2A

I

10

I

2D

I

1W

I

2W

I

I

11

I

21

I
I

1R

I
I

2R

I
I
I

1A

I
I
I

2A

I
I
I
I

10

I
I
I
I

2D

I
I

1W

2W

10

2D

1W

I

2R

I

1A

2A

1D

I

21

I
I

1R

2R

1A

I

12

11

21

13

1R
11

14

2R
21

I
11-1R

Instruction cache access

21
2A-2D

Instruction virtual to physical address translation
Data cache access and load align

1D
1D-2D

1R
11

2A

one cycle

...
...
...

Data virtual to physical address translation
Virtual to physical address translation

2R

Register file read

2R

Bypass calculation

2R
2R

Instruction decode
Branch address calculation

1A

Issue or slip decision

1A-2A

1A

Integer add, logical, shift

1A

Data virtual address calculation

2A

Store align

1A

Branch decision

2W

Register file write
Figure 2: R4650 Plpelme

Technologies for this purpose, are supported by a wide
variety of development tools.
The MIPS integer unit implements a load/store architecture with single cycle ALU operations (logical, shift, add,
sub) and autonomous multiply/divide unit. The 64-bit
register resources include: 32 general-purpose orthogonal
integer registers, the HIILO result registers for the integer
multiply/divide unit, and the program counter. In addition,
the on-chip floating-point co-processor adds 32 floatingpoint registers, and a floating-point control/status register.

can still achieve performance close to the peak
performance of the processor. Figure 2 shows the R4650
pipeline.
Integer Execution Engine
The R4650 implements the MIPS-III Instruction Set
Architecture, and thus is fully upward compatible with applications running on the earlier generation parts. The R4650
includes the same additions to the instruction set found in
the R4600 family of microprocessors, targeted at improving
performance and capability while maintaining binary
compatibility with earlier R30xx processors. The extensions
result in better code density, greater multi-processing
support, improved performance for commonly used code
sequences in operating system kernels, and faster
execution of floating-point intensive applications. All
resource dependencies are made transparent to the
programmer, insuring transportability among implementations of the MIPS instruction set architecture. In addition,
MIPS-III specifies new instructions defined to take
advantage of the 64-bit architecture of the processor.
Finally, the R4650 also implements additional instructions, which are considered extensions to the MIPS-"I
architecture. These instructions improve the multiply and
multiply-add throughput of the CPU, making it well suited to
a wide variety of imaging and DSP applications. These
extensions, which use opcodes allocated by MIPS

Register File
The R4650 has thirty-two general-purpose 64-bit
registers. These registers are used for scalar integer
operations and address calculation. The register file
consists of two read ports and one write port, and is fully
bypassed to minimize operation latency in the pipeline.
Figure 1 illustrates the R4650 Register File.

ALU
The R4650 ALU consists of the integer adder and logic
unit. The adder performs address calculations in addition to
arithmetic operations, and the logic unit performs all logical
and shift operations. Each of these units is highly optimized
and can perform an operation in a single pipeline cycle.

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Integer Multiply/Divide
The R4650 uses a dedicated integer multiply!divide unit,
optimized for high-speed multiply and multiply-accumulate
operation. Table 1 shows the performance, expressed in
terms of pipeline clocks, achieved by the R4650 integer
multiply unit.
Opcode
MULT/U,
MAD/U
MUL

Operand
Size

Latency

Repeat

Stall

16 bit

3

2

0

32 bit

4

3

0

16 bit

3

2

1

32 bit

4

3

2

DMUL T,
DMULTU

any

6

5

0

DIV,DIVU

any

36

36

0

DDIV,
DDIVU

any

68

68

0

unit, decoding and executing instructions in parallel with
the integer unit.
The floating-point unit of the R4650 directly implements
single-precision floating point operations. This enables the
R4650 to perform functions such as graphics rendering,
without requiring extensive die area or power consumption.
The single-precision unit of the R4650 is directly
compatible with the single-precision operation of the
R4600, and features the same latencies and repeat rates.
The R4650 does not directly implement the doubleprecision operations found in the R4600. However, to
maintain software compatibility, the R4650 will signal a trap
when a double-precision operation is initiated, allowing the
requested function to be emulated in software. Alternatively, the system architect could use a software library
emulation of double-precision functions, selected at
compile time, to eliminate the overhead associated with
trap and emulation.
Floating-Point Units
The R4650 floating-point execution units perform single
precision arithmetic, as specified in the IEEE Standard 754.
The execution unit is broken into a separate multiply unit
and a combined add/convertldivide!square root unit.
Overlap of multiplies and add/subtract is supported. The
multiplier is partially pipe lined, allowing a new multiply to
begin every 6 cycles.
As in the IDT79R4600, the R4650 maintains fully precise
floating-point exceptions while allowing both overlapped
and pipe lined operations. Precise exceptions are extremely
important in mission-critical environments, such as ADA,
and highly desirable for debugging in any environment.
The floating-point unit's operation set includes floatingpoint add, subtract, multiply, divide, square root,
conversion between fixed-point and floating-point format,
conversion among floating-point formats, and floating-point
compare. These operations comply with IEEE Standard
754. Double precision operations are not directly
supported; attempts to execute double-precision floating
point operations, or refer directly to double-precision
registers, result in the R4650 signalling a "trap" to the CPU,
enabling emulation of the requested function.

Table 1: R4650 Integer Multiply Operation

The MIPS-III architecture defines that the results of a
multiply or divide operation are placed in the HI and LO
registers. The values can then be transferred to the general
purpose register file using the MFHI!MFLO instructions.
The R4650 adds a new multiply instruction, "MUL", which
can specify that the multiply results bypass the "Lo" register
and are placed immediately in the primary register file. By
avoiding the explicit "Move-from-Lo" instruction required
when using "Lo" , throughput of multiply-intensive operations is increased.
An additional enhancement offered by the R4650 is an
atomic "multiply-add" operation, MAD, used to perform
multiply-accumulate operations. This instruction multiplies
two numbers and adds the product to the current contents
of the HI and LO registers. This operation is used in
numerous DSP algorithms, and allows the R4650 to cost
reduce systems requiring a mix of DSP and control
functions.
Finally, aggressive implementation techniques feature
low latency for these operations along with pipelining to
allow new operations to be issued before a previous one
has fully completed. Table 1 also shows the repeat rate
(peak issue rate), latency, and number of processor stalls
required for the various operations. The R4650 performs
automatic operand size detection to determine the size of
the operand, and implements hardware interlocks to
prevent overrun, allowing this high-performance to be
achieved with simple programming.
Floating-Point Co-Processor
The R4650 incorporates an entire single-precision
floating-point co-processor on chip, including a floatingpoint register file and execution units. The floating-point coprocessor forms a "seamless" interface with the integer
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COMMERCIAL TEMPERATURE RANGE

Table 2 gives the latencies of some of the floating-point
instructions in internal processor cycles.

Operation

through which the virtual memory system's address translation is controlled, exceptions are handled, and operating
modes are controlled (kernel vs. user mode, interrupts
enabled or disabled, cache features). In addition, the
R4650 includes registers to implement a real-time cycle
counting facility, which aids in cache diagnostic testing,
assists in data error detection, and facilitates software
debug. Alternatively, this timer can be used as the
operating system reference timer, and can signal a periodic
interrupt.
Table 3 shows the CPO registers of the R4650.

Instruction
Latency

ADD

4

SUB

4

MUl

8

DIV

32

SQRT

31

CMP

3

FIX

4

FLOAT

6

ABS

Number Name

u

IIljaSe

Function I Changes
(relative to R4600 boards)
Instruction address space base (new In
R4650)

1

1B0und

Instruction address space bound (new
in R4650)

1

2

DBase

Data address space base (new in
R4650)

MOV

1

3

DBound

NEG

1

Data address space bound (new in
R4650)

lWC1

2

SWC1

1

4-7,10,
20-25,
29,31

not used

8

BadVAddr

Virtual address on address exceptions
- changed to 32 bits

Table 2: Floating-Point Operation
Floating-Point General Register File

The floating-point register file is made up of thirty-two 32bit registers. These registers are used as source or target
registers for the single-precision operations.
References to these registers as 64-bit registers (as
supported in the R4600) will cause a trap to be signalled to
the integer unit.
The floating-point control register space contains two
registers; one for determining configuration and revision
information for the coprocessor and one for control and
status information. These are primarily involved with
diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.

9

Count

Counts every other cycle -

11

Compare

Generate interrupt when Count =
Compare - no change

no change

12

Status

Miscellaneous control/status -

delete

KX, SX, and KSU low bit, add cache lock-

ing bits

System Control Co-processor (CPO)

The system control co-processor in the MIPS architecture is responsible for the virtual to physical address
translation and cache protocols, the exception control
system, and the diagnostics capability of the processor. In
the MIPS architecture, the system control co-processor
(and thus the kernel software) is implementation
dependent.
In the R4650, significant changes in CPO relative to the
R4600 have been implemented. These changes are
designed to simplify memory management, facilitate
debug, and speed real-time processing.
System Control Co-Processor Registers

13

Cause

Exception/Interrupt information bits for watch exceptions

add

14

EPC

Exception PC -

15

PRld

Processor 10 -Imp changed to Ox22

16

Config

Cache size fields changed to reflect
R4650 cache sizes. KO field deleted,
since function is now in CAlg.

17

CAlg

Cache attributes for the 8512MB
regions of the virtual address space new register

18

IWatch

Instruction breakpoint virtual address
- new register

19

DWatch

Data breakpoint virtual address
- new register

changed to 32 bits

26

ECC

no change

27

CacheErr

no change

28

Taglo

no change

30

ErrorEPC

CacheError exception PC to 32 bits

changed

Table 3: R4650 CPO Registers

The R4650 incorporates all system control co-processor
(CPO) registers on-chip. These registers provide the path
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COMMERCIAL TEMPERATURE RANGE

Operation modes
The R4650 supports two modes of operation: user mode
and kernel mode.
Kernel mode operation is typically used for exception
handling and operating system kernel functions, including
CPO management and access to 10 devices. In kernel
mode, software has access to the entire address space
and all of the co-processor a registers, and can select
whether to enable co-processor 1 accesses. The processor
enters kernel.mode at reset, and whenever an exception is
recognized.
User mode is typically used for applications programs.
User mode accesses are limited to a subset of the virtual
address space, and can be inhibited from accessing CPO
functions.

the value of the corresponding "base" register is added to
the virtual address to form the physical address for that
reference. If the address is not within bounds, an exception
is signalled.
This facility enables multiple user processes in a single
physical memory without the use of a TLB. This type of
operation is further supported by a number of development
tools for the R4650, including real-time operating systems
and "position independent code".
Kernel mode addresses do not use the base-bounds
registers, but rather undergo a fixed virtual to physical
address translation.

Debug Support
To facilitate software debug, the R4650 adds a pair of
"watch" registers to CPO. When enabled, these registers
will cause the CPU to take an exception when a "watched"
address is appropriately accessed.

OxFFFFFFFF
Kernel virtual address space
(kseg2)
Unmapped, 1.0 GB

Interrupt Vector
The R4650 also adds the capability to speed interrupt
exception decoding. Unlike the R4600, which utilizes a
single common exception vector for all exception types
(including interrupts), the R4650 allows kernel software to
enable a separate interrupt exception vector. When
enabled, this vector location speeds interrupt processing by
allowing software to avoid decoding interrupts from general
purpose exceptions.

OxCOOOOOOO
OxBFFFFFFF
Uncached kernel physical address space
(kseg1 )
Unmapped, 0.5GB

OxAOOOOOOO
Ox9FFFFFFF

Cache Memory
In order to keep the R4650's high-performance pipeline
full and operating efficiently, the R4650 incorporates onchip instruction and data caches that can each be
accessed in a single processor cycle. Each cache has its
own 64-bit data path and can be accessed in parallel. The
cache subsystem provides the integer and floating-point
units with an aggregate bandwidth of over 1500 MB per
second at a pipelineclock frequency of 133M Hz. The cache
subsystem is similar in construction to that found in the
R4600, although some changes have been implemented.
Table 6is an overview of the caches found on the R4650.

Cached kernel physical address space
(ksegO)
Unmapped,0.5GB

OxBOOOOOOO
Ox7FFFFFF

User virtual address space
(useg)
Mapped,2.0GB

OxOOOOOOOO

Instruction Cache
The R4650 incorporates a two-way set associative onchip instruction cache. This virtually indexed, physically
tagged cache is 8KB in size and is parity protected.
Because the cache is virtually indexed, the virtual-tophysical address translation occurs in parallel with the
cache access, thus further increasing performance by
allowing these two operations to occur simultaneously. The
tag holds a 20-bit physical address and valid bit, and is
parity protected.
The instruction cache is 64-bits wide, and can be refilled
or accessed in a single processor cycle. Instruction fetches
require only 32 bits per cycle, for a peak instruction
bandwidth of 533MB/sec at 133M Hz. Sequential accesses
take advantage of the 64-bit fetch to reduce power dissipation, and cache miss refill, can write 64 bits-per-cycle to

Figure 3: Mode Virtual Addressing (32-bit mode)

Virtual to Physical Address Mapping
The 4GB virtual address space of the R4650 is shown in
figure 3. The 4 GB address space is divided into addresses
accessible in either kernel or user mode (kuseg), and
addresses only accessible in kernel mode (kseg2:0).
The R4650 supports the use of multiple user tasks
sharing common virtual addresses, but mapped to
separate physical addresses. This facility is implemented
via the "base-bounds" registers contained in CPO.
When a user virtual address is asserted (load, store, or
instruction fetch), the R4650 compares the virtual address
with the contents of the appropriate "bounds" register
(instruction or data). If the virtual address is "in bounds",

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COMMERCIAL TEMPERATURE RANGE

minimize the cache miss penalty. The line size is eight
instructions (32 bytes) to maximize performance.
In addition, the contents of one set of the instruction
cache (set "A") can be "locked" by setting a bit in a CPO
register. Locking the set prevents its contents from being
overwritten by a subsequent cache miss; refill occurs then
only into "set B".
This operation effectively "locks" time critical code into
one 4kB set, while allowing the other set to service other
instruction streams in a normal fashion. Thus, the benefits
of cached performance are achieved, while deterministic
real-time response is preserved.

The data cache is protected with byte parity and its tag is
protected with a single parity bit. It is virtually indexed and
physically tagged to allow simultaneous address translation
and data cache access
The normal write policy is write back, which means that a
store to a cache line does not immediately cause memory
to be updated. This increases system performance by
reducing bus traffic and eliminating the bottleneck of
waiting for each store operation to finish before issuing a
subsequent memory operation. Software can however
select write-through for certain address ranges, using the
CAlg register in CPO. Cache protocols supported for the
data cache are:
• Uncached. Addresses in a memory area indicated as
uncached will not be read from the cache. Stores to such
addresses will be written directly to main memory, without changing cache contents.
• Writeback. Loads and instruction fetches will first search
the cache, reading main memory only if the desired data
is not cache resident. On data store operations, the
cache is first searched to see if the target address is
cache resident. If it is resident, the cache contents will be
updated, and the cache line marked for later writeback. If
the cache lookup misses, the target line is first brought
into the cache before the cache is updated.
• Write-through with write allocate. Loads and instruction fetches will first search the cache, reading main
memory only if the desired data is not cache resident. On
data store operations, the cache is first searched to see if
the target address is cache resident. If it is resident, the
cache contents will be updated and main memory will
also be written; the state of the "writeback" bit of the
cache line will be unchanged. If the cache lookup misses,
the target line is first brought into the cache before the
cache is updated.
• Write-through without write-allocate. Loads and
instruction fetches will first search the cache, reading
main memory only if the desired data is not cache resident. On data store operations, the cache is first

Data Cache
For fast, single cycle data access, the R4650 includes an
8KB on-chip data cache that is two-way set associative
with a fixed 32-byte (eight words) line size. Table 4 lists the
R4650 cache attributes.
Characteristics

Instruction

Data

Size

8K8

8K8

Line size

2-way set associative
328

2-way set associative
328

Index

vAddr ll .. 0

vAddr ll .. 0

Tag

pAddr 31 .. 12

pAddr 31 .. 12

Write policy

n.a.

writeback Iwritethru

Line transfer order

read sub-block
order
write sequential

read sub-block
order
write sequential

Miss restart after
transfer of

entire line

first word

Parity

per-word

per-byte

Cache locking

set A

set A

Organization

Table 4: R4650 Cache Attributes

..---~

DRAM
(80ns)

Boot
ROM

Control

~

+-~
j--

T...

SCSI
J~

~~32 or64

.

... Memory 1/0

lit

.....

-

~

32or64

,...

~

R4650

-

Address

Controller

-

lr

ENET
h

"

.

~

...

9

~

2

.....

11

Figure 4: Typical R4650 System Architecture
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IOTI9R4650

COMMERCIAL TEMPERATURE RANGE

searched to see if the target address is cache resident. If
it is resident, the cache contents will be updated, and the
cache line marked for later writeback. If the cache lookup
misses, then only main memory is written.
Associated with the Data Cache is the store buffer. When
the R4650 executes a Store instruction, this single-entry
buffer gets written with the store data while the tag
comparison is performed. If the tag matches, then the data
is written into the Data Cache in the next cycle that the
Data Cache is not accessed (the next non-load cycle). The
store buffer allows the R4650 to execute a store every
processor cycle and to perform back-to-back stores without
penalty.

Figure 4 shows a typical system using the R4650. In this
example two banks of DRAMs are used to supply and
accept data with a DDxxDD data pattern
The R4650 clocking interface allows the CPU to be easily
mated with external reference clocks. The CPU input clock
is the bus reference clock, and can be between 25 and
67MHz (somewhat dependent on maximum pipeline speed
for the CPU).
An on-chip phase-locked-loop generates the pipeline
clock from the system interface clock by multiplying it up an
amount selected at system reset. Supported multipliers are
values 2 through 8 inclusive, allowing systems to
implement pipeline clocks at significantly higher frequency
than the system interface clock.

Write buffer
Writes to external memory, whether cache miss writebacks or stores to uncached or write-through addresses,
use the on-chip write bufter. The write buffer holds up to
four address and data pairs. The entire buffer is used for a
data cache write back and allows the processor to proceed
in parallel with memory update. For uncached and writethrough stores, the write buffer significantly increases
performance over the R4000 family of processors.

System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to
transfer addresses and data between the R4650 and the
rest of the system. It is protected with an 8-bit parity check
bus, SysADC. When initialized for 32-bit operation, SysAD
can be viewed as a 32-bit multiplexed bus, with 4 parity
check bits.
The system interface is configurable to allow easier interfacing to memory and I/O systems of varying frequencies.
The bus frequency and reference timing of the R4650 are
taken from the input clock. The rate at which the CPU
transmits data to the system interface is programmable via
boot time mode control bits. The rate at which the
processor receives data is fully controlled by the external
device. Therefore, either a low cost interface requiring no
read or write buffering or a faster, high performance
interface can be designed to communicate with the R4650.
Again, the system designer has the flexibility to make these
price/performance trade-ofts.

System Interface
The R4650 supports a 64-bit system interface that is bus
compatible with the R4600 system interface. In addition,
the R4650 supports a 32-bit system interface mode,
allowing the CPU to interface directly with a lower cost
memory system.
The interface consists of a 64-bit Address/Data bus with
8 check bits and a 9-bit command bus protected with parity.
In addition, there are 8 handshake signals and 6 interrupt
inputs. The interface has a simple timing specification and
is capable of transferring data between the processor and
memory at a peak rate of 533MB/sec at 133M Hz.

SYSAD ________
SYSCm_d______

~~~______~~________~~~--~~

~~

~

~

\'----->/

\'--------'/

~

Figure 5: R4650 Block Read Request (64-bit interface option)

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COMMERCIAL TEMPERATURE RANGE

System Command Bus
The R4650 interface has a 9-bit System Command
(SysCmd) bus. The command bus indicates whether the
SysAD bus carries an address or data. If the SysAD carries
an address, then the SysCmd bus also indicates what type
of transaction is to take place (for example, a read or write).
If the SysAD carries data, then the SysCmd bus also gives
information about the data (for example, this is the last data
word transmitted, or the cache state of this data line is
clean exclusive). The SysCmd bus is bidirectional to
support both processor requests and external requests to
the R4650. Processor requests are initiated by the R4650
and responded to by an external device. External requests
are issued by an external device and require the R4650 to
respond.
The R4650 supports single datum (one to eight byte) and
a-word block transfers on the SysAD bus. In the case of a
single-datum transfer, the low-order 3 address bits gives
the byte address of the transfer, and the SysCmd bus
indicates the number of bytes being transferred. The
choice of 32- or 64-bit wide system interface dictates
whether a cache line block transaction requires 4 double
word data cycles or a single word cycles, and whether a
single datum transfer larger than 4 bytes needs to be
broken into two smaller transfers.

the interface, it asserts ExtRqst. The R4650 responds by
asserting Release to release the system interface to slave
state.
ValidOut and Validln are used by the R4650 and the
external device respectively to indicate that there is a valid
command or data on the SysAD and SysCmd buses. The
R4650 asserts Valid Out when it is driving these buses with
a valid command or data, and the external device drives
Validln when it has control of the buses and is driving a
valid command or data.

Non-overlapping System Interface
The R4650 requires a non-overlapping system interface,
compatible with the R4600. This means that only one
processor request may be outstanding at a time and that
the request must be serviced by an external device before
the R4650 issues another request. The R4650 can issue
read and write requests to an external device, and an
external device can issue read and write requests to the
R4650.
The R4650 asserts Valid Out and simultaneously drives
the address and read command on the SysAD and
SysCmd buses. If the system interface has Rd Rdy or Read
transactions asserted, then the processor tristates its
drivers and releases the system interface to slave state by
asserting Release. The external device can then begin
sending the data to the R4650.
Figure 5 shows a processor block read request and the
external agent read response. The read latency is 4 cycles
(ValidOut to Valid In), and the response data pattern is
DDxxDD. Figure 6 shows a processor block write.

Handshake Signals
There are six handshake signals on the system interface.
Two of these, RdRdy and WrRdy are used by an external
device to indicate to the R4650 whether it can accept a new
read or write transaction. The R4650 samples these
signals before deasserting the address on read and write
requests.
ExtRqst and Release are used to transfer control of the
SysAD and SysCmd buses between the processor and an
external device. When an external device needs to control

Write Reissue and Pipeline Write

The R4600 and the R4650 implement additional write
protocols designed to improve performance. This implementation doubles the effective write bandwidth. The write
re-issue has a high repeat rate of 2 cycles per write. A write

SYSAD ________~~~________~~~___________________________
SYSCm_d______~~

\~--_/
RdRdy
WrRdy

~~___________________________

\'---------'/

-------------------------------------------------------------------------------------------------------------------------------------------------------------Figure 6: R4650 Block Write Request (64-bit system interface)
5.9

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IDT79R4650

issues if WrRdy is asserted 2 cycles earlier and is still
asserted at the issue cycle. If it is not still asserted, the last
write re-issues again. Pipelined writes have the same
2-cycle per write repeat rate, but can issue one more write
after WrRdy de-asserts. They still follow the issue rule as
R4xOO mode for other writes.
External Requests
The R4650 responds to requests issued by an external
device. The requests can take several forms. An external
device may need to supply data in response to an R4650
read request or it may need to gain control over the system
interface bus to access other resources which may be on
that bus.
The following is a list of the supported external requests:
• Read Response
• Null

COMMERCIAL TEMPERATURE RANGE

The PLL, internal timer, and some of the input pins (Int[5:0]*,
NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run.
If the conditions are not correct when the WAIT instruction
finishes the W pipe-stage (Le. the SysAd bus is not idle), the
WAIT is treated as a NOP.
Once the CPU is in Standby Mode, any interrupt, including
the internally generated timer interrupt, will cause the CPU to
exit Standby Mode.
Mode bit
0
4 .. 1

Description
Reserved (must be zero)
Writeback data rate
64-bit
0-7 D,
1 -7 DDx,
2 -7 DDxx,
3 -7 DxDx,
4 -7 DDxxx,
5 -7 DDxxxx,
6 -7 DxxDxx,
7 -7 DDxxxxxx,
8 -7 DxxxDxxx,
9-15 reserved

BootTime Options
Fundamental operational modes for the processor are
initialized by the boot-time mode control interface. The
boot-time mode control interface is a serial interface
operating at a very low frequency (MasterClock divided by
256). The low-frequency operation allows the initialization
information to be kept in a low-cost EPROM; alternatively
the twenty-or-so bits could be generated by the system
interface ASIC or a simple PAL.
Immediately after the VCCOK Signal is asserted, the
processor reads a serial bit stream of 256 bits to initialize
all fundamental operational modes. After initialization is
complete, the processor continues to drive the serial clock
output, but no further initialization bits are read.

7 .. 5

32-bit
0-7W,
1 -7WWX,
2 -7WWXX,
3 -7WxWX,
4-7WWxxx,
5 -7WWXXXX,
6 -7WxxWXX,
7 -7 WWxxxxxx,
8 -7 WxxxWxxx,
9-15 reserved

Clock multiplier
0-72,
1 -73,
2 -74,
3 -75,
4 -7 6,
5 -77,
6 -7 8,
7 reserved

Boot-Time Modes
The boot-time serial mode stream is defined in Table 5.
Bit 0 is the bit presented to the processor when VCCOK is
asserted; bit 255 is the last.

8

o -7 Little end ian,
1 -7 Big end ian

10.. 9

Power Management
CPO is also used to control the power management for
the R4650. This is the standby mode and it can be used to
reduce the power consumption of the internal core of the
CPU. The standby mode is entered by executing the WAIT
instruction with the SysAD bus idle and is exited by any
interrupt.

00
01
10
11

-7
-7
-7
-7

R4000 compatible,
reserved,
pipelined writes,
write re-issue

11

Disable the timer interrupt on Int[5].

12

o -7 64-bit system interface
1 -7 32-bit system interface

14.. 13

Standby Mode Operation
The R4650 provides a means to reduce the amount of
power consumed by the internal core when the CPU would
otherwise not be performing any useful operations. This is
known as "Standby Mode".

255 .. 15

Output driver strength
10 -7 100% strength (fastest),
11 -7 83% strength,
00 -7 67% strength,
01 -7 50% strength (slowest)
must be zero

Table 5: Boot time mode stream

Entering Standby Mode
Executing the WAIT instruction enables interrupts and
enters Standby mode. When the WAIT instruction finishes
the W pipe-stage, if the SysAd bus is currently idle, the
internal clocks will shut down, thus freezing the pipeline.
5.9

10

IDT79R4650

COMMERCIAL TEMPERATURE RANGE

Thermal Considerations
The R4650 utilizes special packaging techniques to
improve the thermal properties of high-speed processors.
The R4650 is packaged using cavity down packaging in a
208-pin MQUAD.
The R4650 utilizes the MQUAD package (the "MS"
package), which is an all-aluminum package with the die
attached to a normal copper lead frame mounted to the
aluminum casing. Due to the heat-spreading effect of the
aluminum, the MQUAD package allows for an efficient
thermal transfer between the die and the case. The
aluminum offers less internal resistance from one end of
the package to the other, reducing the temperature
gradient across the package and therefore presenting a
greater area for convection and conduction to the PCB for
a given temperature. Even nominal amounts of airflow will
dramatically reduce the junction temperature of the die,
resulting in cooler operation.
The R4650 is guaranteed in a case temperature range of
0 0 to +85 0 C. The type of package, speed (power) of the
device, and airflow conditions affect the equivalent ambient
temperature conditions that will meet this specification.
The equivalent allowable ambient temperature, TA, can
be calculated using the thermal resistance from case to
ambient (0CA) of the given package. The following
equation relates ambient and case temperatures:
TA=Tc-P*0cA
where P is the maximum power consumption at hot
temperature, calculated by using the maximum Icc specification for the device.
Typical values for 0CA at various airflows are shown in
Table 6.
0CA
Airflow (fUmin)
208 MQUAD

0

21

200

400

600

800

1000

13

10

9

8

7

Table 6: Thermal Resistance (0CA) at Various Airflows

Note that the R4650 implements advanced power
management to substantially reduce the average power
dissipation of the device. This operation is described in the
IDT79R4650 Hardware User's Manual.

5.9

11

IDT79R4650

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION
The following is a list of interface, interrupt, and miscellaneous pins available on the R4650. Pins marked with one
asterisk are active when low.
Pin Name

Type

Description

System interface:
ExtRqst*

Input

External request
Signals that the system interface needs to submit an external request.

Release*

Output

Release interface
Signals that the processor is releasing the system interface to slave state

RdRdy*

Input

Read Ready
Signals that an external agent can now accept a processor read.

WrRdy*

Input

Write Ready
Signals that an external agent can now accept a processor write request.

Validln*

Input

Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus
and a valid command or data identifier on the SysCmd bus.

ValidOut*

Output

Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and
a valid command or data identifier on the SysCmd bus.

SysAD(63:0)

Input/Output

System address/data bus
A 64-bit address and data bus for communication between the processor and an externalagent.

SysADC(7:0)

Input/Output

System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.

SysCmd(8:0)

Input/Output

System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an
external agent.

SysCmdP

Input/Output

Reserved system command/data identifier bus parity
For the R4650 this signal is unused on input and zero on output.

Clock/control interface:
MasterClock

Input

Master clock
Master clock input used as the system interface reference clock. All output timings are
relative to this input clock. Pipeline operation frequency is derived by multiplying this
clock up by the factor selected during boot initialization.

VeeP

Input

Quiet Vce for PLL
Quiet Vce for the internal phase locked loop.

VssP

Input

Quiet Vss for PLL
Quiet Vss for the internal phase locked loop.

Int*(5:0)

Input

Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.

NMI*

Input

Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.

Interrupt interface:

5.9

12

II

IDT79R4650

COMMERCIAL TEMPERATURE RANGE

Pin Name

Type

Description

Initialization interface:
Veeok

Input

Vee is OK
When asserted, this signal indicates to the R46S0 that the 3.3V (S.OV) power supply has
been above 3.0V (4.SV) for more than 100 milfiseconds and wilf remain stable. The
assertion of Veeok initiates the reading of the boot-time mode control serial stream.

ColdReset*

Input

Cold reset
This signal must be asserted for a power on reset or a cold reset. Cold Reset must be
de-asserted synchronously with MasterClock.

Reset*

Input

Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously
or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset
must be de-asserted synchronously with MasterClock.

ModeClock

Output

Boot mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six.

Modeln

Input

Boot mode data in
Serial boot-mode data input.

5.9

13

IDT79R4650

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS(1)

Symbol

R4650
5.0V±5%

RV4650
3.3V±5%

Commercial

Commercial

Rating

Unit

VTERM

Terminal Voltage with
respect to GND

-0.5(2) to +7.0

-0.5(2) to +4.6

V

Tc

Operating Temperature
(case)

o to +85

o to +85

°C

T SIAS

Case Temperature
Under Bias

-55 to +125

-55 to +125

°C

T STG

Storage Temperature

-55 to +125

-55 to +125

°C

liN

DC Input Current

20(3)

20(3)

mA

lOUT

DC Output Current

50(4)

50(4)

mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V 1N minimum -2.0V for pulse width less than 15ns. V 1N should not exceed Vee +0.5 Volts.
3. When V 1N < OV or V 1N > Vee
4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.

=

RECOMMENDED OPERATION TEMPERATURE AND SUPPLY VOLTAGE

Grade

Commercial

Temperature

R4650

RV4650

Vee

Vee

5.0V±5%

3.3V±5%

GND

aoc to +85°C (Case)

av

5.9

14

III

IDT79R4650

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS (V cc

COMMERCIAL TEMPERATURE RANGE-R4650

=5.0±5%, T CASE =O°C to +85°C)
R465080MHz

R4650 100MHz

R4650 133MHz

Parameter

Conditions
Minimum

-

VOL
VOH

Maximum
0.1V

-

Vee- 0 . 1V

VOL

-

O.4V

-

3.5V

VIL

-0.5V

0.8V

VIH

2.0V

Vee + 0.5V

CIN
COUT
I/OLEAK

Maximum

-

0.1V

Vee - 0.1V

VOH

liN

Minimum

-

O.4V

±10uA

-

10pF

10pF

20uA

-

Maximum
0.1V

Ve e - 0.1V

-

IIOUTI= 20uA

O.4V

"o

UTI=4mA

-

2.4V

-0.5V

0. 2V ee

-0.5V

0. 2V ee

-

2.0V

Vee + 0.5V

2.0V

Vee + 0.5V

o :::;VIN :::;Vee

2.4V

-

-

Minimum

-

-

±10uA

-

±10uA

10pF

-

10pF

-

10pF

-

10pF

-

20uA

InpuVOutput Leakage

20uA

POWER CONSUMPTION-R4650
R465080MHz

R4650100MHz

R4650 133MHz

Parameter

Conditions
Typical(9)

System Condition:
standby

Max

Typical(9)

80/40MHz

Max

Typical(9)

100/50MHz

Max

-

133/44MHz

=OpF(8)

-

50mA

-

75mA

-

100mA

CL

-

125 mA

-

150 mA

-

200mA

CL = 50pF

575 mA

800mA

700 mA

1200 mA

950mA

1350 mA

C L = OpF
No SysAd activity(8)

675 mA

1200 mA

800 mA

1400 mA

1050 mA

1750 mA

CL = 50pF
R4xOO compatible writes,
Te 25°C

active,
64-bit bus
option

=

675 mA

1400 mA

800 mA

1675 mA

1050 mA

2000 mA

Icc

C L = 50pF
Pipelined writes or write
re-issue,
Te 250 C(8)

=

active,
32-bit bus
option

575 mA

800mA

700 mA

1000 mA

950 mA

1350 mA

C L = OpF
No SysAd activity(8)

625 mA

1000 mA

750 mA

1200 mA

1000 mA

1550 mA

C L = 50pF
R4xOO compatible writes,
Te = 25°C

625mA

1100 mA

750 mA

1350 mA

1000 mA

1650 mA

C L = 50pF
Pipelined writes or write
re-issue,
Te = 25 OC(8)

5.9

15

IDT79R4650

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (V cc=5.0V

COMMERCIAL TEMPERATURE RANGE-R4650

± 5%; T CASE = O°C to +85°C)

Clock Parameters-R4650
Parameter

Symbol

R4650
80MHz

Test Conditions

R4650
100MHz

R4650
133MHz

Units

Min

Max

Min

Max

Min

Max

50

80

50

100

50

133

MHz

Pipeline clock frequency

PClk

MasterClock HIGH

tMCHIGH

Transition ~ 5ns

6

-

4

-

3

-

ns

MasterClock LOW

tMCLOW

Transition ~ 5ns

6

-

4

-

3

-

ns

20

40

25

50

25

67

MHz

25

40

20

40

15

40

ns

±250

ps

4

ns

4

ns

-

MasterClock Frequency(5)
MasterClock Period

tMCP

Clock Jitter for MasterClock

tJitterln(8)

-

(8)

-

±250

-

±250

-

5

-

5

-

5

-

5

-

-

256'
tMCP

-

MasterClock Rise Time

tMCRise

MasterClock Fall Time

tMCFall(8)

-

-

ModeClock Period

tModeCKP

-

-

256'
tMCP

256'
tMcp

II

ns

NOTES:
5. Operation of the R4650 is only guaranteed with the Phase Lock Loop enabled.
6. Timings are measured from f.5V of the clock to 1.5V of the signal.
7. Capacitive load for all output timings is 50pF.
8. Guaranteed by Design.
9. Typical integer instruction mix and cache miss rates.

System Interface Parameters-R4650(6)
Parameter

Data Output(7)

Symbol

=
=

to M Min
too Max

Data Output Hold

tOOH

Data Setup

tos

Data Hold

tOH

,

R4650
80MHz

Test Conditions

=10 (fastest)
mode14 .. 13 =01 (slowest)
mode14 .. 13 =10 (fastest)
mode14 .. 13

=
=

trise 5ns
tfall 5ns

R4650
133MHz

R4650
100MHz

Units

Min

Max

Min

Max

Min

Max

1.0

11

1.0

9

1.0

9

ns

2.0

15

2.0

12

2.0

12

ns

1.0

-

1.0

-

1.0

-

ns

5

-

3.5

-

3.5

-

ns

2.5

-

1.5

-

1.5

-

ns

, 25pf loading on external putput signals, fastest settings

Boot Time Interface Parameters-R4650
Parameter

Symbol

Test Conditions

R4650
80MHz
Min

Mode Data Setup

tos

Mode Data Hold

tOH

-

Max

R4650
100MHz
Min

3

-

3

0

-

0

5.9

Max

-

R4650
133MHz
Min
3
0

Units

Max

-

Master Clock Cycle
Master Clock Cycle
16

IDT79R4650

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS - COMMERCIAL TEMPERATURE RANGE RV4650
(V cc = 3.3±5%, T CASE

=O°C to +85°C)
RV4650 80MHz

RV4650100MHz

RV4650133MHz
Conditions

Parameter
Maximum

Minimum

-

VOL
VOH

-

-

VOH

2.4V

VIL

-0.5V

VIH

0. 7Vee

Maximum

-

O.lV

V ee O.lV

VOL

Minimum

Minimum

-

O.lV

-

V ee O.lV

O.4V

-

-

2.4V
-0.5V

Vee +
0.5V

0. 7Vee

O.lV
IloUTI= 20uA

-

Vee O.lV

-

O.4V

0. 2V ee

Maximum

O.4V
IloUTI= 4mA

2.4V

-

0. 2Vee

-0.5V

0. 2Vee

-

Vee +
0.5V

0. 7Vee

Vee +
0.5V

-

-

VoHe

-

-

-

-

-

-

-

VILe

-

-

-

-

-

-

-

VIHe

-

-

-

-

-

-

-

CIN

-

COUT
I/OLEAK

10pF

-

-

10pF

-

20uA

-

10pF

-

10pF

-

10pF

-

10pF

-

-

20uA

-

20uA

Input/Output Leakage

POWER CONSUMPTION-RV4650
RV4650133MHz

RV4650100MHz

RV4650 80MHz

Conditions

Parameter
Typical(9)

80/40MHz

System Condition:

Icc

standby

active,
64-bit bus
option

active,
32-bit bus
option

Typical(9)

Maximum

Typical(9)

Maximum

Maximum

-

133/44MHz

100/50MHz

-

40mA

50mA
100 mA

-

60mA

90 mA

-

CL = OpF(8)

110 mA

C L = 50pF

375 mA

575 mA

475mA

700mA

625mA

925 mA

CL = OpF, No SysAd
activity(8)

450mA

800mA

550 mA

925 mA

700mA

1150 mA

C L = 50pF R4xOO
Icompatible writes
Te = 25°C

450 mA

950mA

550 mA

925mA

700 mA

1300 mA

C L = 50pF Pipelined
writes or Write re-issue,
Te = 25 OC(8)

375mA

575 mA

475 mA

700mA

625mA

925mA

C L = OpF, No SysAd
activity(8)

400mA

700mA

525 mA

825 mA

650mA

1050 mA

C L 50pF R4xOO compatible writes
Te 25°C

400 mA

775 mA

525 mA

825 mA

5.9

650 mA

1125 mA

=

=
C L =50pF Pipelined
writes or Write re-issue,
Te =25 OC(8)

17

IDT79R4650

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS - COMMERCIAL TEMPERATURE RANGE-RV4650
(V cc=3.3V ± 5%; T CASE = O°C to +85°C)

Clock Parameters-RV4650

Parameter

Symbol

RV4650
80MHz

Test Conditions

RV4650
100MHz

RV4650
133MHz

Units

Min

Max

Min

Max

Min

Max

50

80

50

100

50

133

MHz

Pipeline clock frequency

PClk

MasterClock HIGH

tMCHIGH

Transition

5ns

6

-

4

-

3

-

ns

MasterClock LOW

tMCLOW

Transition ~ 5ns

6

-

4

-

3

-

ns

~

-

-

20

40

25

50

25

67

MHz

MasterClock Period

tMcp

-

25

40

20

40

15

40

ns

Clock Jitter for MasterClock

tJitterln(8)

-

-

±250

-

±250

-

±250

ps

-

-

5

-

5

-

4

ns

5

-

5

-

4

ns

MasterClock Frequency(5)

(8)

MasterClock Rise Time

tMCRise

MasterClock Fall Time

tMcFall(8)

-

-

ModeClock Period

tModeCKP

-

-

-

256*

256*

tMCP

-

256*

ns

tMCP

tMCP

NOTES.

i0.0peration of the RV4650 is only guaranteed with the Phase Lock Loop enabled.

System Interface Parameters-RV4650(6)

Parameter

Data Output(7)

Symbol

=
=

t oM Min
too Max

Data Output Hold

tOOH *

Data Setup

tos

Data Hold

tOH

RV4650
80MHz

Test Conditions

modei4 .. i3

RV4650
133MHz

RV4650
100MHz

Units

Min

Max

Min

Max

Min

Max

1.0

11

1.0

9

1.0

9

ns

2.0

15

2.0

12

2.0

12

ns

1.0

-

1.0

-

1.0

-

5

-

3.5

-

3.5

-

ns

2.5

-

1.5

-

1.5

-

ns

= 10 (fastest)

=01 (slowest)
modei4 .. i3 =10 (fastest)

modei4 .. i3

trise = 5ns
tlall = 5ns

ns

* 25pf loading on external putput signals, fastest settings

BootTime Interface Parameters-RV4650

Parameter

Symbol

Test Conditions

RV4650
80MHz
Min

Max

RV4650
100MHz
Min

Max

RV4650
133MHz
Min

Units

Max

Mode Data Setup

tos

-

3

-

3

-

3

-

Master Clock Cycle

Mode Data Hold

tDH

-

0

-

0

-

0

-

Master Clock Cycle

5.9

18

IDT79R4650

PHYSICAL SPECIFICATIONS -

COMMERCIAL TEMPERATURE RANGE

208-PIN MQUAD

MS208
Top View

5.9

19

IDT79R4650

COMMERCIAL TEMPERATURE RANGE

R4650 MQUAD PACKAGE PIN-OUT*
Pin Function
Pin Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
SysAD11
Vss
Vee
SysCmd8
SysAD42
SysAD10
SysCmd7
Vss
Vee
SysAD41
SysAD9
SysCmd6
SysAD40
Vss
Vee
SysAD8
SysCmd5
SysADC4
SysADCO
Vss
Vee
SysCmd4
SysAD39
SysAD7
SysCmd3
Vss
Vee
SysAD38
SysAD6
ModeClock
WrRdy*
SysAD37
SysAD5
Vss
Vee
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.

o::i

54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104

Pin

Function

Pin

Function

N.L,;.

1UO

N.l,;.

157

N.C.
N.C.
N.C.
SysCmd2
SysAD36
SysAD4
SysCmd1
Vss
Vee
SysAD35
SysAD3
SysCmdO
SysAD34
Vss
Vee
SysAD2
Int5*
SysAD33
SysAD1
Vss
Vee
Int4*
SysAD32
SysADO
Int3*
Vss
Vee
Int2*
SysAD16
SysAD48
Int1*
Vss
Vee
SysAD17
SysAD49
IntO*
SysAD18
Vss
Vee
SysAD50
Validln*
SysAD19
SysAD51
Vss
Vee
ValidOut*
SysAD20
N.C.
N.C.
N.C.
N.C.

106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156

N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
SysAD52
ExtRqst*
Vee
Vss
SysAD21
SysAD53
RdRdy*
Modein
SysAD22
SysAD54
Vee
Vss
Release*
SysAD23
SysAD55
NMI*
Vee
Vss
SysADC2
SysADC6
SysAD24
Vee
Vss
SysAD56
SysAD25
SysAD57
Vee
Vss
IOOut
SysAD26
SysAD58
lOin
Vee
Vss
SysAD27
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.

158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

N.C.
N.C.
SysAD59
ColdReset*
SysAD28
Vee
Vss
SysAD60
Reset*
SysAD29
SysAD61
SysAD30
Vee
Vss
SysAD62
SysAD31
SysAD63
Vee
Vss
VeeOK
SysADC3
SysADC7
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VeeP
VssP
MasterClock
Vee
Vss
SysADC5
SysADC1
Vee
Vss
SysAD47
SysAD15
SysAD46
Vee
Vss
SysAD14
SysAD45
SysAD13
SysAD44
Vss
Vee
SysAD12
SysCmdP
SysAD43
N.C.

*N.C. pins should be left floating for maximum flexibility and eompatibility with future designs.
5.9

20

IDT79R4650

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

IDT79

yy

xxxx

999

Operating
Voltage

Device
Type

Speed

A

A

Package Temp rangel
Process

~
1.----------1

Blank

Commercial
(O°C to +S5°C Case)

MS

20S-Pin MQUAD

SO
100
133

SOMHzPClk
100 MHz PClk
133 MHz PClk

L - - - - - - - - - - - - - - t 4650

L-_______________

~

R
RV

Orion Processor for
Embedded Systems

5.0+1-5%
3.3+1-5%

Valid Combinations:
IDT 79R4650 - 80, 100,133

MQUAD package

5.9

21

ontoN™

ENHANCED ORION
64-BIT RISC
MICROPROCESSOR

IDT79R4700™
PRELIMINARY

Integrated Device Technology, Inc.

FEATURES:

• Low-power operation
- 3.3V power supply
- 24mW/MHZ typical internal power dissipation
(2.4W @ 100MHz, 3.3V)
- Standby mode reduces internal power
• Standard operating system support includes:
- Microsoft Windows ™ NT
- UNISOFT Unix™ System VA
• Fully software and pin-compatible with R4600 ORION
Processor Family
• Available in R4600 pin-compatible 179-pin PGA or 208pin MQUAD
• 100-175MHz with mode bit dependent output clock frequencies
• 64GB physical address space
• Processor family for a wide variety of applications
- Desktop workstations and pes
- Deskside or departmental servers
- High-performance embedded applications (e.g. color
printers, multi-media and internetworking.)

• True 64-bit microprocessor
- 64-bit integer operations
- 64-bit floating-point operations
- 64-bit registers
- 64-bit virtual address space
• High-performance microprocessor
- 175 peak MIPS at 175MHz
- 87 peak MFLOP/s at 175MHz
- 132 SPECint92 at 175MHz
- Two-way set associative caches
• Improved FPA multiply performance
- 1 mul, 1 add every 4 clock cycles
• High level of integration
- 64-bit integer CPU
- 64-bit floating-point unit
- 16KB instruction cache; 16KB data cache
Flexible MMU with large TLB

BLOCK DIAGRAM:
Data Tag A
Instruction Set A

Data Set A

t

I~

j\

Istore Buffer
11'
r-

11J

II

DTLB Physical
[\

DataTag B

""

SysAD

TT

J

~,r

I
1

Instruction Select

Write Buffer

Address Buffer

Read Buffer

nstruction Tag

Instruction Registe

A

1

\11

ITLB Physical
Instruction Set B

Data Set B
,nstruction Tag B

Control

r
l7

\11

DB us

~

Floating-point
Register File
Unpacker/Packer

f

IBus

I

I

I

TaCl

~

AuxTaCl ];

I

ec

JointTLB

I
I

0

u
Floating-point
AddlSub/CvtlDiv/Sqrt
Integer Divide

c:
'0

Coprocessor 0

nDVA

\~

~

Integer Register File

120 SPECint92 and >90 SPECfp92 (exact
figures are system-dependent).
The R4700 provides complete upward application-software compatibility with the IOT79R3000™ family of microprocessors, including the lOT RISController™79R3051TM/
R3052™ /R3041"M /R3071 ™/R3081 TM as well as the
IOT79R4000 family of microprocessors. Microsoft Windows

NT and UNISOFT Unix V.4 operating systems insure the
availability of thousands of applications programs, geared
to provide a complete solution to a large number of processing needs. An array of development tools facilitates
the rapid development of R4700-based systems, enabling
a wide variety of customers to take advantage of the MIPS
Open Architecture philosophy.
The 64-bit computing and addressing capability of the
R4700 enables a wide variety of capabilities previously limited by a smaller address space. For example, the large
address space allows operating systems with extensive file
mapping; direct access to large files can occur without
explicit I/O calls. Applications such as large CAD databases, multi-media, and high-quality image storage and
retrieval all directly benefit from the enlarged address
space.
This data sheet provides an overview of the features and
architecture of the R4700 CPU. A more detailed description
of the processor appears in the IDT79R4600 and
IDT79R4700 RiSe Processor Hardware User's Manual,
available from lOT. Further information on development
support, applications notes, and complementary products
are also available from your local lOT sales representative.

HARDWARE OVERVIEW
The R4700 family brings a high-level of integration
designed for high-performance computing. The key elements of the R4700 are briefly described below. A more
detailed description of each of these subsystems is available in the User's Manual.
Pipeline

The R4700 uses a 5-stage pipeline similar to the
IOT79R3000. The simplicity of this pipeline allows the
R4700 to be lower cost and lower power than super-scalar

General Purpose Registers

o

63

Multiply/Divide Registers

o

63

0

HI

r1

o

63

r2

·
·
·
·

LO

Program Counter

o

63
PC

r29
r30
r31
Figure 1: CPU Registers

5.10

2

IDT79R4700

I

10

COMMERCIAL TEMPERATURE RANGE

11

I

21

11

I

1R

I

2R

I

1A

I

2A

J

10

I

20

I

1W

I

2W

I

I

11

I

21

I
I

1R

I
I

2R

I
I
I

1A

I
I

2A

I
I
I
I

10

I
I
I
I

20

I
I
I
I

12

11

21

13

1R

I

11

14

2R
21

I
11-1 R
21
2A-20

10
10-20

1R
11

2A
2R
21

one cycle

10
1A
1R

I
I
I
I

2W
20
2A
2R

I
I
I
I

1W
10
1A

I
I
I

...
...
...

I

Instruction cache access
Instruction virtual to physical address translation in ITLB
Data cache access and load align
Data virtual to physical address translation in OTLB
Virtual to physical address translation in JTLB

2R

Register file read

2R

Bypass calculation

2R

Instruction decode

2R

Branch address calculation

1A

Issue or slip decision

1A-2A

1A

1W

•

Integer add, logical, shift

1A

Oata virtual address calculation

2A

Store align

1A

Branch decision

2W

Register file write
Figure 2: R4700 Pipeline

or super-pipelined processors. Unlike the R3000, the
R4700 does virtual-to-physical translation in parallel with
cache access. This allows the R4700 to operate at over
three times the frequency of the R3000 and to support a
larger TLB for address translation.
Compared to the 8-stage R4000 pipeline, the R4700 is
more efficient (requires fewer stalls).
Figure 2 shows the R4700 pipeline.
Integer Execution Engine
The R4700 implements the MIPS Instruction Set architecture, and thus is fully upward compatible with applications running on the earlier generation parts. The R4700
includes the same additions to the instruction set as found
in the R4000 family of microprocessors, targeted at improving performance and capability while maintaining binary
compatibility with earlier processors. The extensions result
in better code density, greater multi-processing support,
improved performance for commonly used code
sequences in operating system kernels, and faster execution of floating-point intensive applications. All resource
dependencies are made transparent to the programmer,
insuring transportability among implementations of the
MIPS instruction set architecture.
In addition to the instruction extensions detailed above,
new instructions defined in the R4600 that take advantage

of the 64-bit architecture of the processor are also incorporated into the R4700. The R4700 is fully softwarecompatible with the R4600. When operating as a 32-bit
processor, the R4700 will take an exception on these new
instructions.
The MIPS integer unit implements a load/store architecture with single cycle ALU operations (logical, shift, add,
sub) and autonomous multiply/divide unit. The register
resources include: 32 general-purpose orthogonal integer
registers, the HI/LO result registers for the integer multiply/
divide unit, and the program counter. In addition, the onchip floating-point co-processor adds 32 floating-point registers, and a floating-point control/status register.
Register File
The R4700 has thirty-two general-purpose registers.
These registers are used for scalar integer operations and
address calculation. The register file consists of two read
ports and one write port, and is fully bypassed to minimize
operation latency in the pipeline.

ALU
The R4700 ALU consists of the integer adder and logic
unit. The adder performs address calculations in addition to
arithmetic operations, and the logic unit performs all logical
and shift operations. Each of these units is highly optimized
5.10

3

IDT79R4700

COMMER~ALTEMPERATURERANGE

and can perform an operation in a single pipeline cycle.

Integer Multiply/Divide
The R4700 uses the floating-point unit to perform integer
multiply and divide. The results of the operation are placed
in the HI and LO registers. The values can then be transferred to the general purpose register file using the MFHI/
MFLO instructions. Table 1 below shows the number of
processor internal cycles required between an integer multiply or divide and a subsequent MFHI or MFLO operation,
in order that no interlock or stall occurs. The R4700 performs an integer multiply faster than the R4600 by 2 clock
cycles. However, it takes the same number of clock cycles
for integer division.

MULT
DIV

32-bit

64-bit

6-9

7 - 10

42

74

instructions in internal processor cycles. Note that multiplies are pipelined, so that a new multiply can be initiated
every 4 pipeline cycles

Floating-Point General Register File
The floating-point register file is made up of thirty-two 64bit registers. With the LDC1 and SDC1 instructions the
floating-point unit can take advantage of the 64-bit wide
data cache and issue a co-processor load or store doubleword instruction in every cycle.
The floating-point control register space contains two
registers; one for determining configuration and revision
information for the coprocessor and one for control and status information. These are primarily involved with
diagnostic software, exception handling; state saving and
restoring, and control of rounding modes.

Operation

Single
Precision

Double
Precision

ADD

4

4

Table 1: Integer multiply/divide cycles

SUB

4

4

Floating-Point Co-Processor
The R4700 incorporates an entire floating-point co-processor on chip, including a floating-point register file and
execution units. The floating-point co-processor forms a
"seamless" interface with the integer unit, decoding and
executing instructions in parallel with the integer unit. The
floating point coprocessor of the R4700 has improved the
floating multiply operations compared to the R4600. This
improves the peak MFLOPS to be equal to half of the pipeline clock rate.

MUL

4

5

DIV

32

61

SORT

31

60

Floating-Point Units
The R4700 floating-point execution units supports single
and double precision arithmetic, as specified in the IEEE
Standard 754. The execution unit is broken into a separate
multiply unit and a combined add/convert/divide/square
root unit. Overlap of multiplies and add/subtract is supported. The multiplier is partially pipelined, allowing a new
multiply to begin every 4 cycles.
As in the IDT79R3010A and IDT79R4000, the R4700
maintains fully precise floating-paint exceptions while
allowing both overlapped and pipelined operations. Precise
exceptions are extremely important in mission-critical environments and highly desirable for debugging in any environment.
The floating-pOint unit's operation set includes floatingpoint add, subtract, multiply, divide, square root, conversion between fixed-point and floating-pOint format, conversion among floating-point formats, and floating-point
compare. These operations comply with the IEEE Standard
754. The floating point unit improves the multiply compared
to the R4600 by performing a single precision multiply in 4
clock cycles and a double precision multiply in 5 clock
cycles.
Table 2 gives the latencies of some of the floating-point

CMP

3

3

FIX

4

4

FLOAT

6

6

ABS

1

1

MOV

1

1

NEG

1

1

LWC1, LDC1

2

2

SWC1, SDC1

1

1

Table 2: Floating-Point Cycles

System Control Co-processor (CPO)
The system control co-processor in the MIPS architecture is responsible for the virtual memory SUb-system, the
exception control system, and the diagnostics capability of
the processor. In the MIPS architecture, the system control
co-processor (and thus the kernel software) is implementation dependent. The R4700 CPO is identical to that of the
R4600.
The Memory management unit controls the virtual memory system page mapping. It consists of an instruction
address translation buffer (the ITLB), a data address translation buffer (the DTLB), a Joint TLB (the JTLB), and coprocessor registers used for the virtual memory mapping
sub-system.

5.10

4

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

System Control Co-Processor Registers
The R4700 incorporates all system control co-processor
(CPO) registers on-chip. These registers provide the path
through which the virtual memory system's page mapping
is examined and changed, exceptions are handled, and
operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition,
the R4700 includes registers to implement a real-time cycle
counting facility, to aid in cache diagnostic testing, and to
assist in data error detection. Figure 3 shows the CPO
registers.

5-

EntryloO
2-

EntryHi
10-

Entrylo1
3-

PageMask

32-bit address mode), divided into three regions based on
the high-order bits of the virtual address.
Figure 4 shows the address space layout for 32-bit virtual
address operation.When the R4700 is configured for 64-bit
virtual addressing, the virtual address space layout is an
upward compatible extension of the 32-bit virtual address
space layout.

Count
g-

I

Status
12-

I

EPC
14-

I
Index
0-

I

TlB
Random
1-

I"",

(entries protected
from TlBWR)
(L-________________~

r

I

Wired
6-

I
I

Context
4-

I
I

BadVAddr
8-

PRld

I
I

- Register number

I

15-

TagHi
29-

ECC
26-

II
II
II

II
II

II
II
II

Compare
11-

Cause
13-

ErrorEPC
30-

&I

XContext
20-

llAddr
17-

Config
16-

Taglo
28-

CacheErr
27-

Figure 3: The R4700 CPO Registers

Virtual to Physical Address Mapping
The R4700 provides three modes of virtual addressing:
• user mode
• supervisor mode
• kernel mode
This mechanism is available to system software to provide a secure environment for user processes. Bits in a status register determine which virtual addressing mode is
used. In the user mode, the R4700 provides a single, uniform virtual address space of 256GB (2GB for 32-bit
address mode).
When operating in the kernel mode, four distinct virtual
address spaces, totalling 1024GB (4GB in 32-bit address
mode), are simultaneously available and are differentiated
by the high-order bits of the virtual address.
The R4700 processor also supports a supervisor mode in
which the virtual address space is 256.5GB (2.5GB in

JointTLB
For fast virtual-to-physical address decoding, the R4700
uses a large, fully associative TLB which maps 96 Virtual
pages to their corresponding physical addresses. The TLB
is organized as 48 pairs of even-odd entries, and maps a
virtual address and address space identifier into the large,
64GB physical address space.
Two mechanisms are provided to assist in controlling the
amount of mapped space, and the replacement characteristics of various memory regions. First, the page size canbe
configured, on a per-entry basis, to map a page size of 4KB
to 16MB (in multiples of 4). A CPO register is loaded with
the page size of a mapping, and that size is entered into
the TLB when a new entry is written. Thus, operating systems can provide special purpose maps; for example, a
typical frame buffer can be memory mapped using only one
TLB entry.
The second mechanism controls the replacement
5.10

5

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

algorithm when a TLB miss occurs. The R4700 provides a
random replacement algorithm to select a TLB entry to be
written with a new mapping; however, the processor provides a mechanism whereby a system specific number of
mappings can be locked into the TLB, and thus avoid being
randomly replaced. This facilitates the design of real-time
systems, by allowing deterministic access to critical software.
The joint TLB also contains information to control the
cache coherency protocol for each page. Specifically, each
page has attribute bits to determine whether the coherency
algorithm is: uncached, non-coherent write-back, noncoherent write-through write-allocate, non-coherent writethrough no write-allocate. Non-coherent write-back is typically used for both code and data on the R4700; the writethrough modes support more efficient frame buffer
accesses than the R4000 family; cache coherency is not
supported,howeve~

OxliE liE Eli liE
OxEOOOOOOO

Kernel virtual address space
(kseg3)
Mapped, O.5GB

OxDFFFFFFF

OxCOOOOOOO
OxBFFFFFFF

OxAOOOOOOO

Supervisor virtual address space
(sseg)
Mapped,O.5GB
Uncached kernel physical address space
(kseg1 )
Unmapped, O.5GB

Ox9FFFFFFF

Cached kernel physical address space
(ksegO)
Unmapped, O.5GB

Ox80000000
Ox7FFFFFF

User virtual address space
(useg)
Mapped, 2.0GB

OxOOOOOOOO
Figure 4: Kernel Mode Virtual Addressing (32-bit Mode)

Instruction TLB
The R4700 also incorporates a 2-entry instruction TLB.
Each entry maps a 4KB page. The instruction TLB
improves performance by allowing instruction address
translation to occur in parallel with data address translation.
When a miss occurs on an instruction address translation,
the least-recently used ITLB entry is filled from the JTLB.
The operation of the ITLB is invisible to the user.
DataTLB
The R4700 also incorporates a 4-entry data TLB. Each

entry maps a 4KB page. The data TLB improves performance by allowing data address translation to occur in parallel with data address translation. When a miss occurs on
an data address translation, the DTLB is filled from the
JTLB. The DTLB refill is pseudo-LRU: the least recently
used entry of the least recently used half is filled. The operation of the DTLB is invisible to the user.
Furthermore, the large 2-way set-associative caches
increase emulation performance of DOS and Windows 3.1
applications when running under Windows NT.
Cache Memory
In order to keep the R4700's high-performance pipeline
full and operating efficiently, the R4700 incorporates onchip instruction and data caches that can be accessed in a
single processor cycle. Each cache has its own 64-bit data
path and can be accessed in parallel. The cache subsystem provides the integer and floating-point units with an
aggregate bandwidth of 2.4GB per second at a pipeline
clock frequency of 150MHz. The cache subsystem is the
same as for the R4600.
Instruction Cache
The R4700 incorporates a two-way set associative onchip instruction cache. This virtually indexed, physically
tagged cache is 16KB in size and is protected with word
parity.
Because the cache is virtually indexed, the virtual-tophysical address translation occurs in parallel with the
cache access, thus further increasing performance by
allowing these two operations to occur simultaneously. The
tag holds a 24-bit physical address and valid bit, and is parity protected.
The instruction cache is 64-bits wide, and can be refilled
or accessed in a single processor cycle. Instruction fetches
require only 32 bits per cycle, for a peak instruction bandwidth of 700MB/sec at 175MHz. Sequential accesses take
advantage of the 64-bit fetch to reduce power dissipation,
and cache miss refill writes 64 bits-per-cycle to minimize
the cache miss penalty. The line size is eight instructions
(32 bytes) to maximize performance.
Data Cache
For fast, single cycle data access, the R4700 includes a
16KB on-chip data cache that is two-way set associative
with a fixed 32-byte (eight words) line size.
The data cache is protected with byte parity and its tag is
protected with a single parity bit. It is virtually indexed and
physically tagged to allow simultaneous address translation
and data cache access
The normal write policy is writeback, which means that a
store to a cache line does not immediately cause memory
to be updated. This increases system performance by
reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. Software can however select
write-through on a per-page basis when it is appropriate,
such as for frame buffers.
5.10

6

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

Associated with the Data Cache is the store buffer. When
the R4700 executes a Store instruction, this single-entry
buffer gets written with the store data while the tag comparison is performed. If the tag matches, then the data is written into the Data Cache in the next cycle that the Data
Cache is not accessed (the next non-load cycle). The store
buffer allows the R4700 to execute a store every processor
cycle and to perform back-to-back stores without penalty.

rest of the system. It is protected with an a-bit parity check
bus, SysADC.
The system interface is configurable to allow easier interfacing to memory and I/O systems of varying frequencies.
The data rate and the bus frequency at which the R4700
transmits data to the system interface are programmable
via boot time mode control bits. Also, the rate at which the
processor receives data is fully controlled by the external
device. Therefore, either a low cost interface requiring no
read or write buffering or a faster, high performance interface can be designed to communicate with the R4700.
Again, the system designer has the flexibility to make these
price/performance trade-offs.

Write buffer
Writes to external memory, whether cache miss writebacks or stores to uncached or write-through addresses,
use the on-chip write buffer. The write buffer holds up to
four 64-bit address and 64-bit data pairs. The entire buffer
is used for a data cache write back and allows the processor to proceed in parallel with memory update. For
uncached and write-through stores, the write buffer significantly increases performance over the R4000 family of processors.

System Command Bus
The R4700 interface has a 9-bit System Command
(SysCmd) bus. The command bus indicates whether the
SysAD bus carries an address or data. If the SysAD carries
an address, then the SysCmd bus also indicates what type
of transaction is to take place (for example, a read or write).
If the SysAD carries data, then the SysCmd bus also gives
information about the data (for example, this is the last data
word transmitted, or the cache state of this data line is
clean exclusive). The SysCmd bus is bidirectional to support both processor requests and external requests to the
R4700. Processor requests are initiated by the R4700 and
responded to by an external device. External requests are
issued by an external device and require the R4700 to
respond.
The R4700 supports one to eight byte and block transfers on the SysAD bus. In the case of a sub-doubleword
transfer, the low-order 3 address bits gives the byte
address of the transfer, and the SysCmd bus indicates the
number of bytes being transferred.

System Interface
The R4700 supports a 64-bit system interface that is
compatible with the R4000PC system interface. This interface operates from two clocks provided by the R4700,
TClock[1 :0] and RClock[1 :0], at some division of the internal clock.
The interface consists of a 64-bit Address/Data bus with
8 check bits and a 9-bit command bus protected with parity.
In addition, there are 8 handshake signals and 6 interrupt
inputs. The interface has a simple timing specification and
is capable of transferring data between the processor and
memory at a peak rate of 700MB/sec at 17SMHz.
Figure 5 shows a typical system using the R4700. In this
example two banks of DRAMs are used to supply and
accept data with a DDxxDD data pattern.

Handshake Signals
There are six handshake signals on the system interface.
Two of these, RdRdy and WrRdy are used by an external
device to indicate to the R4700 whether it can accept a new

System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to
transfer addresses and data between the R4700 and the

Address
L2
Cache
Control
SCSI

NE

32

emory 1/

Controller-,....I--+----+--~

R4700

9

2
11

Figure 5: Typical Desktop System Block Diagram

5.10

7

IDT79R4700

read or write transaction. The R4700 samples these signals before deasserting the address on read and write
requests.
ExtRqst and Release are used to transfer control of the
SysAD and SysCmd buses between the processor and an
external device. When an external device needs to control
the interface, it asserts ExtRqst. The R4700 responds by
asserting Release to release the system interface to slave
state.
ValidOut and Validln are used by the R4700 and the
external device respectively to indicate that there is a valid
command or data on the SysAD and SysCmd buses. The
R4700 asserts Valid Out when it is driving these buses with
a valid command or data, and the external device drives
Valid In when it has control of the buses and is driving a
valid command or data.
Non-overlapping System Interface
The R4700 uses a non-overlapping system interface,
compatible with the R4600. This means that only one processor request may be outstanding at a time and that the
request must be serviced by an external device before the
R4700 issues another request. The R4700 can issue read
and write requests to an external device, and an external
device can issue read and write requests to the R4700.
For processor read transaction the R4700 asserts ValidOut and simultaneously drives the address and read command on the SysAD and SysCmd buses. If the system
interface has Rd Rdy asserted, then the processor tristates
its drivers and releases the system interface to slave state
by asserting Release. The external device can then begin
sending the data.
Figure 6 shows a processor block read request and the
external agent read response. The read latency is4 cycles
(ValidOut to Valid In), and the response data pattern is
DDxxDD. Figure 7 shows a processor block write.

COMMERCIAL TEMPERATURE RANGE

External Requests
The R4700 responds to requests issued by an external
device. The requests can take several forms. An external
device may need to supply data in response to an R4700
read request or it may need to gain control over the system
interface bus to access other resources which may be on
that bus. It also may issue requests to the processor, such
as a request for the R4700 to write to the R4700 interrupt
register.
The following is a list of the supported external requests:
• Write
• Null
• Read Response
Boot Time Options
Fundamental operational modes for the processor are
initialized by the boot-time mode control interface. The
boot-time mode control interface is a serial interface operating at a very low frequency (MasterClock divided by 256).
The low-frequency operation allows the initialization information to be kept in a low-cost seriel EEPROM; alternatively the twenty-or-so bits could be generated by the
system interface ASIC or a simple PAL.
Immediately after the VCCOK Signal is asserted, the processor reads a serial bit stream of 256 bits to initialize all
fundamental operational modes. After initialization is complete, the processor continues to drive the serial clock output, but no further initialization bits are read.
JTAG Interface
For compatibility with the R4000PC, the R4700 supports
the JTAG interface pins, with the serial input connected to
serial output. Boundary scan is not supported.

Write Reissue and Pipeline Write

The R4600 and the R4700 implement additional write
protocols designed to improve performance. This implementation doubles the effective write bandwidth. The write
re-issue has a high repeat rate of 2 cycles per write. A write
issues if WrRdy is asserted 2 cycles earlier and is still
asserted at the issue cycle. If it is not still asserted, the last
write re-issues again. Pipe lined writes have the same 2cycle per write repeat rate, but can issue one more write
after WrRdy de-asserts. They still follow the issue rule as
R4xOO mode for other writes.

5.10

8

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

SysAD

~

SysCmd

8---\

ValidOut

~

~----------~~

X X X----------~~
CData

\

Validln

CData

/

\~_/

RdRdy

WrRdy

~

Release

SySAD________

SySCm_d______

Figure 6: Processor Block Read

~~~________~~~______________________________

~~

~~______________________________

\'---~/

\~--l/

Figure 7: Processor Block Write

5.10

9

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

Boot-Time Modes
The boot-time serial mode stream is defined in Table 3.
Bit a is the bit presented to the processor when VCCOK is
asserted; bit 255 is the last.

Mode bit
0

4 .. 1

Power Management
CPO is also used to control the power management for
the R4700. This is the standby mode and it can be used to
reduce the power consumption of the internal core of the
CPU. The standby mode is entered by executing the WAIT
instruction with the SysAD bus idle and is exited by an
interrupt.

Description

Mode
bit

reserved (must be zero)

14.. 13

Output driver strength
10 ~ 100% strength (fastest),
11 ~ 83% strength,
00 ~ 67% strength,
01 ~ 50% strength (slowest)

Write back data rate

bit 15

o -> TClock[O] enabled

O~D,

1 -> TClock[O] disabled

1 ~ DDx,
2 ~ DDxx,
3 ~ DxDx,
4 ~ DDxxx,
5 ~ DDxxxx,
6 ~ DxxDxx,
7 ~ DDxxxxxx,
8 ~ DxxxDxxx,
9-15 reserved
7 .. 5

Clock divisor

bit 16

o -> TClock[1] enabled
1 -> TClock[1] disabled

0~2,

1

Description

~3,

2~4,
3~5,
4~6,
5~7,

6~8,

7 reserved
8

o ~ Little endian,
1

10 .. 9

11

~

00
01
10
11

bit 17

Big endian

~
~
~
~

o -> RClock[O] enabled
1 -> RClock[O] disabled

bit 18

R4000 compatible,
reserved,
pipelined writes,
write re-issue

o -> RClock[1] enabled
1 -> RClock[1] disabled

Disable the timer interrupt on Int[5].

255 .. 19

Reserved (must be zero)

o ~ Enabled
1
12

~

Disabled

reserved (must be zero)
Table 3: Boot time mode stream

5.10

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IDT79R4700

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION
The following is a list of interface, interrupt, and miscellaneous pins available on the R4700. Signals marked with one
asterisk are active when low.
Pin Name

Type

Description

System interface:
ExtRqst*

Input

External request
Signals that the system interlace needs to submit an external request.

Release*

Output

Release interlace
Signals that the processor is releasing the system interlace to slave state

RdRdy*

Input

Read Ready
Signals that an external agent can now accept a processor read.

WrRdy*

Input

Write Ready
Signals that an external agent can now accept a processor write request.

Validln*

Input

Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus
and a valid command or data identifier on the SysCmd bus.

ValidOut*

Output

Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and
a valid command or data identifier on the SysCmd bus.

SysAD(63:0)

Input/Output

System address/data bus
A 64-bit address and data bus for communication between the processor and an externalagent.

SysADC(7:0)

Input/Output

System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.

SysCmd(8:0)

Input/Output

System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an
external agent.

SysCmdP

Input/Output

Reserved system command/data identifier bus parity
for the R4700 unused on input and zero on output.

Clock/control interface:
MasterClock

Input

Master clock
Master clock input at one half the processor operating frequency.

MasterOut

Output

Master clock out
Master clock output aligned with MasterClock.

RClock(1 :0)

Output

Receive clocks
Two identical receive clocks at the system interlace frequency.

TClock(1 :0)

Output

Transmit clocks
Two identical transmit clocks at the system interlace frequency.

IOOut

Output

Reserved for future output
Always HIGH.

lOin

Input

Reserved for future input
Should be driven HIGH.

SyncOut

Output

Synchronization clock out
Synchronization clock output. Must be connected to Syncln through an interconnect that
models the interconnect between MasterOut, TClock, RClock, and the external agent.

5.10

11

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

Pin Name

Type

Description

Syncln

Input

Synchronization clock in
Synchronization clock input. See SyncOut.

Fault·

Output

Fault
Always HIGH.

VeeP

Input

Quiet Vee for PLL
Quiet Vee for the internal phase locked loop.

VssP

Input

Quiet Vss for PLL
Quiet Vss for the internal phase locked loop.

Int*(5:0)

Input

Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.

NMI*

Input

Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.

Interrupt interface:

Initialization interface:
Vccok

Input

Vee is OK
When asserted, this signal indicates to the R4700 that the 3.3V (5.0V) power supply has
been above 3.0V (4.5V) for more than 100 milliseconds and will remain stable. The
assertion of Vccok initiates the reading of the boot-time mode control serial stream.

ColdReset*

Input

Cold reset
This signal must be asserted for a power on reset or a cold reset. The clocks SClock,
TClock, and RClock begin to cycle and are synchronized with the de-assertion edge of
Cold Reset. ColdReset must be de-asserted synchronously with MasterOut.

Reset*

Input

Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously
or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset
must be de-asserted synchronously with MasterOut.

ModeClock

Output

Boot mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six.

Modeln

Input

Boot mode data in
Serial boot-mode data input.

** For compatibility with the R4600, the R4650 supports the JTAG interface pins, with the serial input connected
to serial output. Boundary scan is not supported.

5.10

12

IDT79R4700

Standby Mode Operations

COMMERCIAL TEMPERATURE RANGE

Table 5.

The R4700 provides a means to reduce the amount of
power consumed by the internal core when the CPU would
otherwise not be performing any useful operations. This is
known as "Standby Mode" .
Entering Standby Mode
Executing the WAIT iunstruction enables interrupts and
enters Standby mode. When the WAIT instruction finishes
the W pipe-stage, if the SysAd bus is currently idle, the
internal clocks will shut down, thus freezing the pipeline.
The PLL, internal timer, some of the input pin clocks
(Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) and the
output clocks (TClock[1 :0], RClock[1 :0], SyncOut, Modeclock and MasterOut) will continue to run. If the conditions
are not correct when the WAIT instruction finishes the W
pipe-stage (i.e. the SysAd bus is not idle), the WAIT is
treated as a NOP.
Once the CPU is in Standby Mode, any interrupt, including the internally generated timer interrupt, will cause the
CPU to exit Standby Mode.

0CA
Airflow (fUmin)

0

200

400

600

800

1000

PGA

16

7

5

3

2.5

2

MQUAD

20

12

9

8

7

6

Table 5: Thermal Resistance (0CA) at Various Airflows

Note that the R4700 implements advanced power management to substantially reduce the average power dissipation of the device. This operation is described in the
IDT79R4600lR4700 Hardware User's Manual.

Thermal Considerations
The R4700 utilizes special packaging techniques to
improve the thermal properties of high-speed processors.
The R4700 is packaged using cavity down packaging in a
179-pin PGA package with integral thermal slug, and a
208-lead MOUAD OFP package. These packages effectively dissipate the power of the CPU, increasing device
reliability.
The R47000 utilizes the MOUAD package (the "MS"
package), which is an all-aluminum package with the die
attached to a normal copper lead frame mounted to the
aluminum casing. Due to the heat-spreading effect of the
aluminum, the package allows for an efficient thermal
transfer between the die and the case. The aluminum
offers less internal resistance from one end of the package
to the other, reducing the temperature gradient across the
package and therefore presenting a greater area for
convection and conduction to the PCB for a given temperature. Even nominal amounts of airflow will dramatically
reduce the junction temperature of the die, resulting in
cooler operation.
The R4700 is guaranteed in a case temperature range of
00 to +85 0 C. The type of package, speed (power) of the
device, and airflow conditions affect the equivalent ambient
temperature conditions that will meet this specification.
The equivalent allowable ambient temperature, TA, can
be calculated using the thermal resistance from case to
ambient (0CA) of the given package. The following equation relates ambient and case temperatures:
TA = Tc - P * 0CA
where P is the maximum power consumption at hot temperature, calculated by using the maximum Icc specification for the device.
Typical values for 0CA at various airflows are shown in
5.10

13

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS(1)

Symbol

Rating

RV4700
3.3V±5%

R4700
5.0V±5%

Commercial

Commercial

Unit

VTERM

Terminal Voltage with
respect to GND

-0.5(2) to +4.6

-0.5(2) to +7.0

V

Tc

Operating Temperature
(case)

o to +85

o to +85

°C

T SIAS

Case Temperature
Under Bias

-55 to +125

-55 to + 125

°C

T STG

Storage Temperature

-55 to +125

-55 to +125

°C

liN

DC Input Current

20(3)

20(3)

mA

lOUT

DC Output Current

50

50(4)

mA

NOTES.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VIN minimum = -2.0V for pulse width less than 15ns. VIN should not exceed Vee +0.5 Volts.
3. When VIN < OV or VIN > Vee
4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.

RECOMMENDED OPERATION TEMPERATURE AND SUPPLY VOLTAGE

Grade

Commercial

Temperature

O°C to +85°C (Case)

RV4700

R4700

Vee

Vee

3.3V±5%

5.0V±5%

GND

OV

5.10

14

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS -

COMMERCIAL TEMPERATURE RANGE-R4700

(Vee = 5.0±5%, T CASE = O°C to +85°C)

Parameter

R4700 100MHz
Minimum

-

VOL
VOH

O.1V

-

Vee O.1V

-

VOL

Maximum

O.4V

-

R4700 133MHz
Minimum

-

R4700 150MHz

Maximum

Minimum

-

VeeO.1V

-

O.1V

-

-

1I0UTI= 20uA

-

V ee 0.1V

O.4V

3.5V

Maximum

-

O.1V

Conditions

O.4V

1I0UTI= 4mA

-

VOH

3.5V

3.5V

VIL

-O.5V

O.8V

-O.5V

O.8V

-O.5V

O.8V

-

V IH

2.0V

Vee +
O.5V

2.0V

Vee +
O.5V

2.0V

Vee +
O.5V

O~VIN ~Vce

lIN

-

±10uA

-

±10uA

-

±10uA

CIN

-

10pF

-

10pF

-

10pF

-

COUT

-

10pF

-

10pF

-

10pF

-

I/OLEAK

-

20uA

-

20uA

-

20uA

Input/Output
Leakage

Power Consumption-R4700
R4700100MHz

R4700133MHz

R4700 150MHz
Conditions

Parameter
Typical(9)
System
Condition:
standby

Max

Typical(9)

Max

Typical(9)

133/33MHz

100/25MHz

Max

150/38MHz

-

-

175mA

-

225mA

-

260mA

CL = OpF(B)

-

250mA

-

325mA

-

370mA

C L = 50pF

875mA

1000mA

1175mA

1300mA

1325mA

1500mA

CL = OpF
No SysAd activity(B)

975mA

1200mA

1275mA

1500mA

1450mA

1700mA

CL = 50pF
R4xOO compatible
writes
Te = 25°C

975mA

1400mA

1275mA

1675mA

1450mA

1900mA

CL = 50pF
Pipelined writes or
write re-issue
Te = 25OC(8)

Icc
active

5.10

15

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS -

COMMERCIAL TEMPERATURE RANGE-R4700

(V cc=5.0V ± 5%; T CASE = O°C to +85°C)

Clock Parameters-R4700
Parameter

Symbol

R4700
100MHz

Test Conditions

Min
MasterClock HIGH

tMCHIGH

Transition ~ 5ns

MasterClock LOW

tMCLOW

Transition

~

5ns

4
4

Max

R4700
133MHz
Min

Max

R4700
150MHz
Min

Units

Max

-

3

-

3

-

ns

-

3

-

3

-

ns

25

67

25

75

MHz

15

40

13.3

40

ns

-

-

25

MasterClock Period

tMcp

-

20

Clock Jitter for MasterClock

tJitterln(8)

-

-

±250

-

±250

-

±250

ps

Clock Jitter for MasterOut,
SyncOut, TClock, RClock

tJitterOut(8)

-

-

±500

-

±500

-

±500

ps

MasterClock Rise Time

tMCRise

(8)

-

-

5

-

4

-

3.5

ns

MasterClock Fall Time

tMCFa,,(8)

-

-

5

-

4

-

3.5

ns

ModeClock Period

tModeCKP

-

-

256*t

-

256*t

-

256*t

ns

MasterClock Frequency(5)

50
40

MCP
JTAG Clock Period

tJTAGCKP

-

-

4*t
MCP

MCP

-

4*t
MCP

MCP

-

4*t

ns

MCP

NOTES:

5. Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled.
6. Timings are measured from 1.5V of the clock to 1.5V of the signal.
7. Capacitive load for all output timings is 50pF.
8. Guaranteed by Design.
9. Typical integer instruction mix and cache miss rates.

5.10

16

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

System Interface Parameters-R4700(6)
Parameter

Data Output(7)

Symbol

too

Data Setup

tos

Data Hold

tOH

R4700
100MHz

Test Conditions

R4700
133MHz

R4700
150MHz

Units

Min

Max

Min

Max

Min

Max

mode14 .. 13 = 10 (fastest)

1.0

9

1.0

9

1.0

8

ns

mode14 .. 13 = 11

1.3

11

1.3

10

1.3

9.3

ns

mode14 .. 13 =00

1.6

13

1.6

11

1.6

10.6

ns

mode14 .. 13 =01 (slowest)

2.0

15

2.0

12

2.0

12

ns

trise =5ns
tfall =5ns

3.5

-

3.5

3.5

-

1.5

-

ns

1.5

-

1.5

ns

Boot Time Interface Parameters-R4700

Parameter

Symbol

Min

Max

R4700
150MHz

R4700
133MHz

R4700
100MHz

Test
Conditions

Min

Max

Min

Units

Max

Mode Data Setup

tos

-

3

-

3

-

3

-

Master Clock Cycle

Mode Data Hold

tOH

-

0

-

0

-

0

-

Master Clock Cycle

Capacitive Load Deration-R4700
Parameter

Load Derate

R4700100MHz

R4700 133MHz

R4700150MHz

Min

Max

Min

Min

-

2

Units

Symbol

CLD

Max

-

2

5.10

-

Max
2

ns/25pF

17

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS (Vcc = 3.3±5%, T CASE =

COMMERCIAL TEMPERATURE RANGE-RV4700

aoc to +85°C)

RV4700100MHz

RV4700133MHz

RV4700150MHz

RV4700175MHz

Min

Max

Min

Max

Min

Max

Min

Max

O.1V

-

O.1V

-

O.1V

-

O.1V

Parameter

Conditions

-

VOL
VOH

Vee
- O.1V

VOL

-

VOH

2.4V

V IL

-O.5V

V IH

O. 7Vee

-

-

Vee
- O.1V

-

Vee
- O.1V

-

OAV

-

2.4V

-

2.4V

O. 2Vee

-Q.5V

O. 2Vee

-Q.5V

Vee
+O.5V

O. 7Vee

Vee
+O.5V

O. 7Vee

O.4V

-

-

O.4V

IIOUTI= 20uA

-

Vee
- O.1V

O.4V
IIOUTI=4mA

2.4V

-

O. 2Vee

-Q.5V

O. 2Vee

-

Vee
+O.5V

O. 7Vee

Vee
+ O.5V

-

-

-

-

-

-

-

-

-

-

-

-

-

VoHe

-

-

-

-

VILe

-

-

-

VIHe

-

-

-

CIN

-

10pF

-

10pF

-

10pF

-

10pF

-

COUT

-

10pF

-

10pF

-

10pF

-

10pF

-

I/OLEAK

-

20uA

-

20uA

-

20uA

-

20uA

-

Input/Output
Leakage

Power Consumption-RV4700
RV4700100MHz
Parameter

Typical

Max

standby

Typical

Max

(9)

(9)

System
Condition:

RV4700133MHz

100/25MHz

RV4700150MHz
Typical

Max

(9)

133/33MHz

RV4700 175MHz
Typical

Max

Conditions

(9)

150/38MHz

-

175/44MHz

-

125mA

-

175mA

-

200mA

-

200mA

C L = OpF(B)

-

175mA

-

225mA

-

250mA

-

250mA

C L = 50pF

575mA

875mA

775mA

1150mA

875mA

1300mA

1025mA

1500mA

CL = OpF, No SysAd
activity(B)

650mA

1100mA

850mA

1375mA

950mA

1550mA

1200mA

1800mA

C L 50pF
R4xOO compatible
writes
Te 25°C

Icc
active

=

=

650mA

1275mA

850mA

1525mA

950mA

5.10

1725mA

1200mA

2000mA

CL = 50pF
Pipelined writes or
write re-issue,
Te = 25 OC(B)

18

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS - COMMERCIAL TEMPERATURE RANGE-RV4700
(V cc=3.3V ± 5%; T CASE = O°C to +85°C)

Clock Parameters-RV4700
Parameter

Symbol

RV4700
100MHz

Test Conditions

RV4700
133MHz
Max

Min

Units

Min

Max

MasterClock HIGH

tMCHIGH

Transition::; 5ns

4

-

3

-

ns

MasterClock LOW

tMCLOW

Transition::; 5ns

4

-

3

-

ns

-

-

25

50

25

67

MHz

t MCP

-

20

40

15

40

ns

MasterClock Frequency(5)
MasterClock Period
Clock Jitter for MasterClock

tJitterln(8)

-

-

±250

ps

t Jitte rOut(8)

-

-

±500

-

±250

Clock Jitter for MasterOut,
SyncOut, TClock, RClock

±500

ps

MasterClock Rise Time

tMCRise

(8)

-

-

5

-

4

ns

MasterClock Fall Time

tMcFall(8)

5

-

4

ns

ModeClock Period

tModeCKP

-

-

Parameter

Symbol

-

MasterClock LOW

-

Test Conditions

256"
tMCP
RV4700
175MHz

RV4700
150MHz
Min

MasterClock HIGH

256"
tMcp

Max

Min

ns

Units
Max

tMCH1GH

Transition::; 5ns

3

-

3

-

ns

tMCLOW

Transition::; 5ns

3

-

3

-

ns

-

25

75

25

87.5

13.3

40

11.4

40

ns

MasterClock Frequency(10)

MHz

MasterClock Period

tMCP

-

Clock Jitter for MasterClock

tJitterln (8)

-

-

±250

-

±250

ps

Clock Jitter for MasterOut,
SyncOut, TClock, RClock

tJitterOut(8)

-

-

±500

-

±500

ps

MasterClock Rise Time

tMCRise

(8)

-

-

3.5

3.5

ns

MasterClock Fall Time

tMCFall(8)

-

-

3.5

-

3.5

ns

ModeClock Period

tModeCKP

-

-

256"
tMCP

-

256"
tMcp

ns

NOTE:
10.0peration of the RV4700 is only guaranteed with the Phase Lock Loop enabled.

5.10

19

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

System Interface Parameters-RV4700(6)

Parameter

Data Output(7)

Symbol

t OM = Min
too = Max

Data Setup

tos

Data Hold

tOH

RV4700
100MHz

Test Conditions

RV4700
133MHz

RV4700
175MHz

RV4700
150MHz

Units

Min

Max

Min

Max

Min

Max

Min

Max

mode14 .. 13 = 10 (fastest)

1.0

9

1.0

9

1.0

8

1.0

8

ns

mode14 .. 13 = 01 (slowest)

2.0

15

2.0

12

2.0

12

2.0

12

ns

3.5

-

3.5

-

3.5

-

3.5

-

ns

1.5

-

1.5

-

1.5

-

1.5

-

ns

trise = 5ns
tfall = 5ns

Boot Time Interface Parameters-RV4700

Parameter

Symbol

RV4700
100MHz

Test
Conditions

Min

Max

RV4700
150MHz

RV4700
133MHz
Min

Max

Min

Max

RV4700
175MHz
Min

Units

Max

Mode Data Setup

tos

-

3

-

3

-

3

-

3

-

Master Clock Cycle

Mode Data Hold

tOH

-

0

-

0

-

0

-

0

-

Master Clock Cycle

Capacitive Load Deration-RV4700
RV4700100MHz
Parameter

RV4700 150MHz

RV4700 175MHz
Units

Min
Load Derate

RV4700133MHz

Symbol

C LO

-

Max
2

Min

Max

-

2

5.10

Min

-

Max
2

Min

-

Max
2

ns/25pF

20

IDT79R4700

PHYSICAL SPECIFICATIONS -

COMMERCIAL TEMPERATURE RANGE

208-PIN MQUAD

MS208
Top View

5.10

21

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

PHYSICAL SPECIFICATIONS -

1 2

V
U

T
R
P
N
M
L

K
J
H
G
F
E

0
C
B

A

3 4

PGA

5 6

7 8

9 10 11 12 13 14 15 16 17 18

• • • • • • • • • • • • • • • • • •
• • • • • • • • • • • • • • • • • •

V
U

• • • • • • • • • • • • • • • • • •
• • •

• • •

T
R
P

• • •

• • •

• • •

• • •
•
•
•
•

•
•
•
•

•
•
•
•

R4700

Pinout
Bottom

• • •

• • •
• • •
• • •
• • •

• • •
• • •

• • •

• • •

• • •

N
M
L

K
J
H

G
F

• • •

E

• • • • • • • • • • • • • • • • • •

0
C

• • •

• • •

• • •

• • • • • • • • • • • • • • • • • •
• • • • • • • • • • • • • • • • •
1 2

3 4

5 6

7 8

B

A

9 10 11 12 13 14 15 16 17 18
2884 drw 12

5.10

22

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

R4700 MQUAD PACKAGE PIN-OUT*
Pin Function
Pin Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

N.C.
N.C.
Vss
Vee
SysAD45
SysAD13
Fault*
SysAD44
Vss
Vee
SysAD12
SysCmdP
SysAD43
SysAD11
Vss
Vee
SysCmd8
SysAD42
SysAD10
SysCmd7
Vss
Vee
SysAD41
SysAD9
SysCmd6
SysAD40
N.C.
N.C.
Vss
Vee
SysAD8
SysCmd5
SysADC4
SysADCO
Vss
Vee
SysCmd4
SysAD39
SysAD7
SysCMD3
Vss
Vee
SysAD38
SysAD6
ModeClock
WrRdy*
SysAD37
SysAD5
Vss
Vee
N.C.
N.C.

53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104

N.C.
N.C.
SysCmd2
SysAD36
SysAD4
SysCmd1
Vss
Vee
SysAD35
SysAD3
SysCmdO
SysAD34
Vss
Vee
N.C.
N.C.
SysAD2
Int5*
SysAD33
SysAD1
Vss
Vee
Int4*
SysAD32
SysADO
Int3*
Vss
Vee
Int2*
SysAD16
SysAD48
Int1*
Vss
Vee
SysAD17
SysAD49
IntO·
SysAD18
Vss
Vee
SysAD50
Validln*
SysAD19
SysAD51
Vss
Vee
ValidOut*
SysAD20
SysAD52
ExtRqst*
N.C.
N.C.

Pin

Function

Pin

Function

105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156

N.C.
N.C.
N.C.
N.C.
Vee
Vss
SysAD21
SysAD53
RdRdy*
Modeln
SysAD22
SysAD54
Vee
Vss
Release*
SysAD23
SysAD55
NMI*
Vee
vss
SysADC2
SysADC6
Vee
SysAD24
Vee
Vss
SysAD56
N.C.
SysAD25
SysAD57
Vee
Vss
100ut
SysAD26
SysAD58
lOin
Vee
Vss
SysAD27
SysAD59
ColdReset*
SysAD28
Vee
Vss
SysAD60
Reset*
SysAD29
SysAD61
Vee
Vss
N.C.
N.C.

lof

N.l,;.

158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

N.C.
RClockO
RClock1
SyncOut
SysAD30
Vee
Vss
SysAD62
MasterOut
SysAD31
SysAD63
Vee
Vss
VeeOK
SysADC3
SysADC7
Vee
Vss
N.C.
N.C.
N.C.
N.C.
N.C.
VeeP
VSSP
N.C.
N.C.
MasterClock
Vee
Vss
Syncln
Vee
Vss
N.C.
SysADC5
SysADC1
N.C.
Vee
Vss
SysAD47
SysAD15
N.C.
SysAD46
Vee
Vss
SysAD14
N.C.
TClock1
TClockO
N.C.
N.C.

*N.C. pins should be left floating for maximum flexibility and eompatibility with future designs.
5.10

23

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

R4700 PGA Pin-out
Function

Function
Pin

Cold Reset

T14

ExtRqst

U2

Fault

816

Reserved 0 (NC)

U10

Reserved I (Vee)

T9

lOin

T13

100ut

U12

IntO

N2

Int1

L3

Int2

K3

Int3

J3

Int4

H3

Int5

F2

MasterClock

J17

MasterOut

P17

ModeCloek

84

Modeln

U4

NMI

U7

RCloekO

T17

RCloek1

R16

RdRdy

T5

Release

V5

Reset

U16

Syneln

J16

SyncOut

P16

SysADO

J2

SysAD1

G2

SysAD2

E1

SysAD3

E3

SysAD4

C2

SysAD5

C4

SysAD6

85

SysAD7

86

SysAD8

89

Pin

Function

Pin

SysAD9

811

SysAD44

C15

SysAD10

C12

SysAD45

817

SysAD11

814

SysAD46

E17

SysAD12

815

SysAD47

F17

SysAD13

C16

SysAD4S

L2

SysAD14

D17

SysAD49

M3

SysAD15

E18

SysAD50

N3

SysAD16

K2

SysAD51

R2

SysAD17

M2

SysAD52

T3

SysAD18

P1

SysAD53

U3

SysAD19

P3

SysAD54

T6

SysAD20

T2

SysAD55

T7

SysAD21

T4

SysAD56

T10

SysAD22

U5

SysAD57

T11

SysAD23

U6

SysAD58

U13

SysAD24

U9

SysAD59

V15

SysAD25

U11

SysAD60

T15

SysAD26

T12

SysAD61

U17

SysAD27

U14

SysAD62

N16

SysAD28

U15

SysAD63

N17

SysAD29

T16

SysADCO

CS

SysAD30

R17

SysADC1

G17

SysAD31

M16

SysADC2

TS

SysAD32

H2

SysADC3

L16

SysAD33

G3

SysADC4

88

SysAD34

F3

SysADC5

H16

SysAD35

D2

SysADC6

US

SysAD36

C3

SysADC7

L17

SysAD37

83

SysCmdO

E2

SysAD38

C6

SysCmd1

D3

SysAD39

C7

SysCmd2

82

SysAD40

C10

SysCmd3

A5

SysAD41

C11

SysCmd4

87

SysAD42

813

SysCmd5

C9

SysAD43

A15

SysCmd6

810

5.10

24

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

Function
SysCmd7

Pin
B12

Function

Pin

Vee

Function

Pin

V10

Vss

Vee

V12

JTMS

E16

Vee

V14

JTOO

F16

Vee

V17

JTOI

G16

016

Vss

A3

JTCK

H17

VeeOk

M17

Vss

A6

Vss

A8

SysCmd8

C13

SysCmdP

C14

TClockO

C17

TClock1

Valid In

P2

ValidOut

R3

Vss

A10

WrRdy

C5

Vss

A12

VeeP

K17

Vss

A14

VssP

K16

Vss

A17

Vee

A2

Vss

A18

Vee

A4

Vss

B1

Reserved I (Vee)

A7

Vss

C18

Vee

A9

Vss

01

Vee

A11

Vss

F18

Vee

A13

Vss

G1

Vee

A16

Vss

H18

Vee

B18

Vss

J1

Vee

C1

Vss

K18

Vee

018

Vss

L1

Vee

F1

Vss

M18

Vee

G18

Vss

N1

Vee

H1

Vss

P18

Vee

J18

Vss

R18

Vee

K1

Vss

T1

Vee

L18

Vss

U18

Vee

M1

Vss

V1

Vee

N18

Vss

V2

Vee

R1

Vss

V4

Vee

T18

Vss

V7

Vee

U1

Vss

V9

Vee

V3

Vss

V11

Vee

V6

Vss

V13

Vee

V8

Vss

V16

5.10

V18

25

IDT79R4700

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
IDT79

YY

Configuration

xxxx

999

A

A

Device
Type

Speed

Package

Process/
Temperature
Range
Blank

Commercial (O°C to +85°C (Case))

G
MS

PGA 179
208-Pin MQUAD

100
133
150
175

100MHz
133MHz
150MHz
175MHz

4700

Enhanced Orion CPU

RV
R

3.3V±S%
5.0V±S%

Valid Combinations:
lOT 79R4700 - 100,133,150
79RV4700 -100,133,150,175

PGA, MQUAO Package
PGA, MQUAO Package

5.10

26

RISC SUPPORT COMPONENTS

II

RISC SUPPORT COMPONENTS
A Rise microprocessor is an important, but not selfsufficient, element of a high-performance general or embedded computing system. Equally important is the memory
system (both cache and main memory) and the I/O interface
to the execution core.
By providing these system solutions as building blocks, lOT
allows its customers the maximum flexibility in achieving their

price/performance goals while minimizing time-to-market, real
estate and complexity of the end system.
This section of the data book contains some selected
devices which have either been specifically designed for
particular RiSe processors or found to be exceptionally useful in these high-performance systems.

6.0

TABLE OF CONTENTS
PAGE

RISC SUPPORT COMPONENTS
IOT79R3715
IOT79R371 0/40
IOT79R4761
IOT79R4762

Single-Chip System Controller ..... ... .......... ....... ........ ........... .... .... ........ ........ .... ..........
Laser Printer Integrated System Controller for lOT R30xx RISController Family
w/Adobe Frame Buffer Compression ........................................................................
Orion Family Memory and 1/0 Controller ..... ..............................................................
Orion Family PCI to Orion Bridge ........ ..... ........... ...... .... ... .................... .... ... .......... ...

6.0

6.1
6.2
6.3
6.4

2

~g

SINGLE-CHIP SYSTEM
CONTROLLER

IDT79R3715
ADVANCE
INFORMATION

Integrated Device Technology, Inc.

FEATURES
• System Controller for the pin-compatible lOT R30xx
family of processors
• DRAM Controller
- 1 - 40 MB directly, 1 - 3 banks directly
- Device depth supported: 256K - 4M
- Non-interleave
• ROM Controller
- 1 - 20MB, Address-space support bank size: 1- 8MB
- Support for standard and burst ROMs
- Support for interleave or non-interleave
• Direct Interface to external DMA master
• I/O Bus follows 8/16-bit Intel 80186 style
• I/O Controller
- Two 8-bit and two 16-bit external channels
DMA and non-DMA access for the 8-bit channels
8-32 packing, 32-8 unpacking logic for DMA access
16-32 packing, 32-16 unpacking for CPU/
external DMA master coprocessor accesses
- Round robin arbitration
- Programmable timing for I/O and control signals
Big and Little Endian support

• PCMCIA Support
- Through 16-bit I/O bus, using simple glue logic
- 16-bit to 32-bit packing and 32-bit to 16-bit
unpacking
- Big and Little Endian support
256MB address space dedicated to 2 PCMCIA
slots
• 24-bit Timer/Counter, In-Circuit testing capability
• Centronics Interface
- Bi-directional Centronics, compliant with IEEE1284
Supports DMA and CPU controlled transfers
- Supports the following modes:
Compatible; Nibble; Byte; ECP; EPP
• Interrupt Controller
- 6 external level interrupts (through the PIO pins)
14 internal interrupts
- Individual interrupt mask capability, enabling polling
or interrupt-driven systems
• General Purpose I/O
- Six programmable Input (interrupts) or Output pins

DRAM
General
Purpose I/O

I,

ROM
Serial

lOT
R3041 ,
R3051 ,
R3052,
R3071 ,
or R3081
RISController

External DMA
Master

IDT79R3715 System Organization

3715·20

The lOT logo is a registered trademark and R3715 is a trademark of Integrated Device Technology, Inc.

April 1995

COMMERCIAL TEMPERATURE RANGE
© 1995 Integrated Device Technology, Inc.

6.1

MC- 9089/1

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

ADVANCE INFORMATION

Some of the architectural characteristics that result
in very high performance include:
• incorporating a tightly coupled interface to any of
the R30xx RISC CPUs
minimizing latency to critical resources
partitioning the system in a balanced way to attain
efficient use of shared resources
enabling several simultaneous operations in the
system
The R3715 is ideal for modular design of laser
printers because it allows a high level of programmability and incorporates the control logic for an industry
standard interface to peripherals. This gives OEMs the
ability to offer several products from the same basic
design, as well as the ability to upgrade systems in the
field. The block diagram that follows shows the R3715
configuration.

OVERVIEW
The IDT79R3715 is a single-chip System Controller
designed to complement IDT's R30xx family of 32-bit
embedded processors. It has all of the features necessary to maximize the performance of a RISC-based
system and reduce the overall system chip count.
The R3715 can move large amounts of data quickly
without the need for processor intervention. It also
achieves a significant reduction in system cost by its high
level of integration. Additional savings come from the
architecture of the I/O controller, which allows for the utilization of low cost peripheral components (disk controller,
network controller, etc.), while attaining the higher level of
performance only associated with costlier components.

Memory
System

Modes:
Compatible
Nibble
Byte

CPU

ECP
EPP

e.g.
Serial
Network

3715·21

IDT79R3715 Block Diagram

6.1

2

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

ADVANCE INFORMATION

FUNCTIONAL DESCRIPTION

External DMA Master Interface

Processor Interface
The R3715 has a glueless interface to the IDT
R3041/51/52171/81 family of RISC processors. It
supports these devices in both slave and master modes
of operation. As slave, they support CPU access to
memory and I/O devices, and as master, handle
accesses on the AID bus.
As slave the R3715 supports processor single
transfer read or write, as well as burst read access. Each
supports processor access to the ROM, DRAM, devices
on the 1/0 bus, and the R3715 internal registers. Burst
read is supported only for DRAM or ROM read access.
ACK* and RDCEN* timing is fixed for the R3715 registers. DRAM access can be extended by one clock, and
access timing for ROM and 1/0 are programmable.
As master the R3715 will request the bus by
asserting BUSREQ* when a DMA source (internal or
external) needs to transfer data to or from the DRAM I
ROM I I/O Channel.
The priority between the DMA sources is in the
following descending order:
Access in process
1/0 DMA
External DMA master
The CPU will get ownership of the AID bus for at
least one cycle after four DMA accesses. This assumes
that each external DMA master (external agent) bus
possession is counted as one, regardless of the number
of transfers it executes on the bus. In the default state,
when there is no DMA request, the bus is owned by the
CPU.
Figure 2.1 shows the CPU-to-R3715 interface.

The R3715 has a simple interface to the external
DMA master coprocessor. It supports the external DMA
master operation in its slave and master modes. As slave
it supports the processor read and write accesses to the
external DMA master, and as master it enables access
to the DRAM, ROM, and 16 bit I/O bus (for font
cartridges). The R3715 directly controls the data buffers
and the address buffer needed to isolate the external
DMA master from the A/D bus.
The R3715 decodes CPU access to the external
DMA master and asserts ECS*, EAS*, and EDS*. The
address is latched into an external transparent latch
(373-type) when the processor asserts ALE and is driven
into the multiplexed bus (DAL[31 :0]) by EATOE*. Data is
driven to or from the external DMA master by transceivers controlled by EADDIR* and EADOE*. To end an
external DMA master cycle the R3715 asserts RDCEN*
and ACK* to the CPU when the external DMA master
asserts EDTACK*.
In external DMA master mode, the external DMA
master requests the bus by asserting EBREQ*. The
R3715 will grant the bus by asserting EBGNT* (provided
no other DMA device has requested the bus and
provided also that it was granted by the CPU to the
R3715). The external DMA master will assert EAS* first,
and then EDS*, to initiate an access to a system
resource (e.g. DRAM). The R3715 will assert EADOE*
and EADDIR* to drive the external DMA master address,
and ALE to latch it. In the data phase it will assert
EADDIR* and EADOE* according to the access direction
(Read or Write).
To end the cycle the R3715 will assert EDTACK* to
the external DMA master. When it does not require the
bus any longer the external DMA master will release it by
deasserting EBREQ*
External access to the DRAM takes 5 clocks from
EAS* to EDTACK*. Frequencies above 25 MHz may
need an additional clock cycle. One clock can be added
to this interval by using the ExtCas bit in the DRAM
control register.
Figure 2.2 on the following page shows a typical
implementation of an external DMA master interface.

AD(31:0)

R3041 ,
R3051,
R3052,
R3071 ,
or
R3081

Addr(3:2)
Burst'
ALE
SysClk'
Rd*
Wr*
Ack'
- RdCEn*
~ BusReq*
~usGnt

Int*
- DataEn*

\32

2

,
.....

.

-"

--.

---'"

IDT79R3715
~

3715 drw 03.1

Figure 2.1 RISController to R3715 Interface

6.1

3

til

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

ADVANCE INFORMATION

Address/Data Bus

ALE

--------1
C.

EATOE

BCAdr
BCData
BCRW

External DMA
Master Interface

BReq

eq

BGnt

EBGnt

OS

EDS

c

c
ECS

CS
AAck

c

IReq
RESET
RESET ______~----------------------~~~~
SYSClk ____....._ _ _ _ _ _ _ _ _ _ _ _S_Y_S_C_lk-tl~

IDT79R3715
3715 drw 10.1

Figure 2.2 External DMA Master Coprocessor Implementation

ROM
The ROM controller supports up to 20 Mbyte of
memory with several device types and system configurations. To support these system and device options, the
assertion time of RDCEN* and ACK* by the R3715 can
be programmed, thus accommodating different types of
memory architectures, including standard ROMs, interleaved ROMs, and burst ROMs.
There are three CS signals to support up to three
banks of ROM. Each ROM bank can be either non-interleaved or interleaved (composed of 2 leaves of ROM
differentiated by ADDR[2]). ROMCS[2]* controls the boot
bank and has a fixed address space of 4 Mbyte. Address
space for ROMCS[1]* and ROMCS[O]* is programmable
to 1, 2, 4, or 8 Mbyte.
The R3715 puts the 3 ROM bank address ranges in
a contiguous address space. In other words, the start
address of the next ROMCS[x]* will follow the last
address of the previous ROMCS[x-1]*. For interleaved
support, ROMOE* is provided to control the OE of the
interleave multiplexer. The R3715 also supports burst

ROM, and can be made to write to the ROM space (for
flash or debug) with additional glue logic.
After reset, the R3715 is configured with the
maximum number of wait states between each data
transfer (16 clocks between each RDCEN*) and 64
clocks between ROMCS[x]* to ACK*. The initial (reset)
space size for ROMCS[1]* and ROMCS[O]* is 1 Mbyte,
and 4Mbytes for ROMCS[2]*.
Figure 2.3 on the following page shows the configuration of the ROM/DRAM memory system.

6.1

4

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

ADVANCE INFORMATION

IDT79R3715
EPROM/ROM
rJl
rJl
Q)

-0
"C

«

EPROM/ROM

DWr
CAS(3:0)
ROMCS(2:0)
ROMOE
ALE

Figure 2.3 R3715 ROM/DRAM Memory System

3715 drw04.1

DRAM

Interrupt Controller

The DRAM controller supports directly 1 to 40 Mbytes
of DRAM, with up to three non-interleaved banks. The
address space starts at physical address o. The DRAM
device types supported have the following attributes:
page mode, early write, and "CAS before RAS" refresh.
The DRAM controller supports single transfer reads
and writes and burst reads. Various DRAM device depths
are supported and the address space is continuous for
the selected configuration. The DRAM controller can be
configured to support different device depth for the base
bank (RAS[O]*) and the extension banks (RAS[1]* and
RAS[2]*).
For systems running at high frequency there is an
option to extend the CAS* signals by an additional cycle.
An external DMA master may sample data on the rising
edge of SYSCLK*, and the CPU on the falling edge. It is
possible to extend the CAS* by one cycle for external
DMA master accesses. To minimize the refresh penalty
IDT recommends that you program the refresh frequency
according to the value of SYSCLK*.
The initial values of the R3715 control registers at
reset are shown in the tables in Section 3.

Each interrupt source on the R3715 is maskable.
The Cause register bit will reflect the cause of the interrupt, and writing a '0' into it will acknowledge the
internal interrupt. For example - if the "Bandlnt" bit was
active, the CPU should write 'fffB' into the Cause
register, in order to reset the interrupt flag.
The external interrupts, PI0[5:0], are acknowledged at the source of the interrupt (the interrupt flag is
deasserted when PIO is inactive), the corresponding
bits in the Interrupt Cause register are read only.
At reset, all interrupts are masked in the mask
register.
DMA-Based Serial Interface

One of the DMA-supported I/O channels can be
used to support protocols such as AppleTalk directly,
with only the addition of an external communication
controller, such as the 85C30 or 85C230, and the I/O
interface devices it requires. The R3715 I/O FIFO and
Burst DMA capabilities aid in separating the real-time
demands of protocols such as AppleTalk from the realtime demands of the engine interface, but without the
cost implications of external buffering.

PIO Port

Each of the PI0[5:0] pins can be individually
programmed to be an output or input pin by writing to the
PIO Control register. When programmed as an input pin it
can be used as a level (active LOW) interrupt. The PIO
pins are synchronized and pulled up internally. At reset,
all PIOs are initialized as inputs.
6.1

5

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

(

lORd

~79R3715

6)

IOData(7:0)

.0

....•.... ; .y'y: tL

IOWr
IOCS(O)
IODReq(O)

ADVANCE INFORMATION

85C30
or
85230

B~
~G!

IOCS(1:0)
10DReq(1 :0)
10DAck(1 :0)
10Wait
lOBED
10BEl
IOGPCS(1:0)

3715 drw 07.1

Figure 2.4 DMA-Supported AppleTalk I/O Port

10Al

Programmable TimerlCounter
The general purpose timer/counter can be
programmed to function as a timer or as a counter. As a
counter, it will cause an interrupt and stop counting when
it reaches terminal count. Writing a new value to the
counter will start the counter if the Enable bit is active. As
a timer on terminal count, it will cause an interrupt, reload
with the value stored in the Timer/Counter Value register
and continue to count.
The Timer/Counter counting is enabled or disabled
by the enable bit. The value n should be written to the
Counter in order to count to n clocks. At reset, the
counter is disabled.

1/0 Bus
The R3715 supports two 8-bit (IOCS[1 :0]*) and two
16-bit (IOGP/-lCS[1 :0]*) external I/O channels that share
the IODATA[15:0] pins. The two 8-bit I/O channels and
the first 16-bit I/O channel (IOGPCS[O]*) each has a 16
Mbyte address space. The second 16 bit I/O channel
(I0GPCS[1 ]*) has a 256 Mbyte address space.
Timing of the control signals to an I/O channel is
programmable. The user can specify the length of 10RD*
and 10WR* signals. The IOCS[1 :0]*, IOGPCS[1 :0]* or
DMAACK[1 :0]* are asserted one cycle before the 10RD*
or 10WR* signals become active, and remain active for
one cycle after 10RD* or 10WR* are dasserted. RDCEN*
and ACK* will be asserted by the R3715 to end a
processor (or EDTACK* to end an external DMA master)
110 cycle.

I/O
Device

3715 drw 06.1

Figure 2.5 General Purpose I/O Device Interface

a-bit I/O Channels
The R3715 supports processor byte accesses (reads
and writes) to devices located on the two 8 bit I/O channels. These accesses can be made using any of the four
bytes on the 32 bit data bus. The R3715 will transfer the
correct byte (according to the 4 Byte Enables) to the 8 bit
I/O bus (IODATA[7:0]).
The I/O channel unit on the R3715 operates as a
DMA controller with the two 8 bit I/O channels. DMA
operations between I/O devices and the DRAM are
supported. Eight bit data is packed or unpacked during
DMA access into a 32 bit register for I/O DMA read or
write respectively.
DMA Operations
Processor requests have priority over DMA
requests. The priority for DMA operations is round robin
for the Centronics and the two external 8-bit DMA
engines. DMAREQ[1 :0]* can be masked by writing '0' to
the enable bit of the channel. A channel will not participate in the arbitration if the channel is disabled or if the
I/O BIU (Bus Interface Unit) is owned by another channel.
The I/O BIU is emptied into memory in a DMA read
access under the following conditions: 1) if the I/O BIU is
full, or 2) if there is no DMA request (DMAREQ[1 :0]) from
the channel which owns the I/O BIU for a time out period,
or 3) the byte count reaches zero.
In the write direction if the DMAREQ* from the
channel that owns the I/O BIU is not active for a time out
period, and the I/O BIU is not empty, arbitration will
resume on the I/O bus. The time out period is set to 32
clocks. The clock period value cannot be changed, only
enabled or disabled.

6.1

6

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

ADVANCE INFORMATION

16-bit 110 Channels
The R3715 supports processor and external OMA
master accesses (reads and writes) to devices located
on the two 16-bit I/O channels.
For 16-bit devices, the CPU can read or write to any
byte or half word. Processor or external OMA master
access to the 16-bit I/O channels with any combination of
byte enables active, will be performed in two consecutive
I/O cycles in case of 3 or 4 byte accesses. In the two
cycles, data will be packed or unpacked from a 32-bit
register for an I/O read or write respectively. Conversion
between big and little end ian is supported for 16-bit
devices.

IOOata(7:0)

""','1\

rrt21-+1J
\
\

CAS*

OEMAD*

r--

I

L.-.t7 \

ext ( AS·

L-t22+/
1/;:.>,/

I
/

-t6-/
\
>
\

ACK* / RDCEN*

DRAM Read (Programmable)

6.1

36

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

SYSCLK

J

AlD[31:0]

DADR[10:0]

II

\

ALE

I(

ADVANCE INFORMATION

II

\

I

\
addr

\

Ir-

I

Ir' ::trlrll

data

~"

~1a---1

f----t19----j

{

I.BD(

If

\

rowadc less

J. Icolumn_addtess

X.

~t2o--

RAS*

~

\

-t214

CAS*

\

f-t2c-J

\

/'/

I--t20--1

DWR*

if

\ ":\

'--t7-

OEMAD*

\

L-t7/

'

"i

,i,,~

.'

-16--/

ACK*

\

'

'-,,-\

[/

DRAM Write

SYSCLK

' L '\...... rL rL ' L

n-n- rL rL "--n-n-' \

ALE

no '

AlD[31:0]
BURST*
DADR[10:0]
RAS*

r-

\

RDCEN*

O(~

~olt

rn\M irlrlr

J:~

(11

X.

h~

I

IX

,--

1\

CAS*
OEMAD*

,~

n::>

111

1\

frl.

r

r~

\

'-- V-- I~

1'---

r r -

L-

ACK*

DRAM Burst Read

6.1

37

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

SYSCLK
ALE

A/O[31 :0]
AOOR[3:2]

--1l~

__________________________________________________

=x_____
~o

ADVANCE INFORMATION

X_F...;..FF_F..;...OO_10_ _ _ _ _ _ _ _ _---JX'-.:....:.FF..:..:FF:...:..F.:...;FF...;..F_ _ _ _ _ _ _ __

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

ACK*
ROCEN*
IOGPCS*
IORO*
IOWAIT*

U
____________

----------------------------------,L-J~----_~3_~X~2~

_____________

XJCX~2

''-_ _. .;:d;:,:;:e. :,.:vt.:.:. :.im.:.,:;:e_ _----I!

--------..'-1

~

\'-____d~e::..!.vt!.!!.im:..:.::e::....__---J!

'-'

IOOATA[15:0]

-=zz:;;;:z=-z_ _ _-'X~F:...:..F.:...;FF_ _ _ _ _ _ _--IX'l..:;z:;;;:zz:;;;,Z_ _--JX,-F-FF-F--------,X'-=z;:::zzz=--_ _

IOBE[1:0]*

~.::..o-------------------------_

IOA1

- - - - - - - - - - - - - -_ _----_~I

'--

I/O Read 16-Bit

SYSCLK

IOGPCS*

IOWR*

IOA1

IOBE*

~~~_'-_~_~d~atwa_ _ _ _ _~'_______ '-___~d~at~a_ _ _ _ _ _~~

1/0 Write 24-Bit

6.1

38

ADVANCE INFORMATION

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

SYSCLK
IOGPCS*

~ t26
IOWAIT*

•

--------~------------~

IOWR*
25

-.j

IOOATA[15:0]

1/0 Write (With Wait State)

SYSCLK
OMAREQ
t16
OMAACK*I--------r----+----n~

IORO*I--------+----+---~-----n~

IOOATA[7:0]

1-----1---.f.---f----{,
~~"+'

1/0 Bus DMA Read

6.1

39

ADVANCE INFORMATION

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

SYSCLK:

ALE; _ _ _ _ _---.1

ADDR[3:2]

AlD[31 :0]

.iift=~~~==~

EBREQ*

EBGNT*

EAS*

EAACK*

EDS*

EDTACK*

EADDIR*

IODATA[15:0]

IORD*

'LJj
External DMA Master- Master 1/0 Read

6.1

40

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

129~OOfO

I

I

I

I

I

ADVANCE INFORMATION

I

I

129~OOrO I

I II I
I

SYSCLK

I

130~OrO~

Id

I

ALE

I

r-r-

AD[31:0]
ADDR[3:2]

13~50rOOI

I I I
-lI1JlJUlIlllIUlUUUlf

I

a

.::=::::x

_n

~
~

~2

3

n

L-

RD*
WR*
BURSr

-1-1

~U

H-

H

U

U

ACK*

U

RDCEN*
BUSREQ*

~I

I
1--

BUSGNT*

I

I
L-J
H

EADOE*
EADDIR*
EDTACK*

Ut-r--I~r-

1-1

EDS*

I

EBREQ*

I
M

1

EBGNT*

I-IL-J

EAS*

til

ECS*

U

EAACK*
EATOE*
RAS[2:0]*

~7

CAS[3:0]*

J-YF

DADR[10:0]
DWR*

X-

x:

OF

=X:CO:=J° 1F

X::x:X

X000

U
External DMA Master- Master Read

6.1

41

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

3090000

ADVANCE INFORMATION

13100000

13110000

13120000

13130000

13140000

III 1 1111111111111111111111/111111111111111/1 IIIIllllfl

I

3150000

1I1111111~11

I

SYSCLK
AD[31:0j
ADDR[3:2j
ALE

OQooFEAO

______________________
3

~X_2

_______________________

y_X~o

~I_______________________

l

_______

,n___

I

RD*
WR*

t--n

BURSr

LJ

ACK*
RDCEN*
BUSREO*

~

I---.J

BUSGNr
EADOE*
EADDIR*
EDTACK*
EDS*
EBREO*

----~HI--~====~UIr====~==~I~-----

-1-1
-,

....-------------.LJ

H

--1-/

H

EBGNr
EAS*
ECS*

u

EAACK*
EATOE*
RAS[2:0)*
CAS[3:0)*
DADR[10:0j

""""D.
r
y
X
~~~~====~====~~~
_F
_ _ _ _~X_O__ X\-F_ _ _ _ _ _ _ _ _ _ _~O
f=t_O ____ ~_F_ _ _ _ _ __
6

01F

7

X,AB

X01F

5

7

X.;;..;26~8_ _ _ _ _ _~~..;;.;26..;..8_ _ _ _ _ _ _~X'_4.....;;02_ _ __ _

L.-J

DWR*

External DMA Master- Master Write

6.1

42

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

2560000

ADVANCE INFORMATION

12570000

12580000

12590000

12600000

12610000

111111111111111111111111111111111111111111111111111
1

SYSCLK
AD[31:0]
ADDR[3:2]

~ _ _~ 1COOOOOO

~O

3

r

Il

ALE
RD*
WR*

1-

BURSr
ACK*

~I

U

1_'

RDCEN*
BUSREQ*
BUSGNr
EADOE*
EADDIR*

L-I

EDTACK*

I

EDS*

•

EBREQ*
EBGNr

LJ

EAS*
ECS*
EAACK*
EATOE*

~7

RAS[2:0]*

6

CAS[3:0]*

T..~..:..F

DADR[10:0]
DWR*

_________________________

"L-J~~X~7=======================
6

External DMA Master- Slave Read

6.1

43

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

2580000
1

SYSCLK

12585000

12590000

12595000

1 2600000

1 2605000

I

2610000

"111111, JlII,11I1 JlJldd, JI,ldll, "IIJI,I, 1111,1,1, dll,I,I,

1

n--.ILn~_n~_ILrLJ---uL..-I---uL..-IL

AD[31 :0] ~y
ADDR[3:2]

ADVANCE INFORMATION

3

X1COOOOOO

00000000

~======================~==~

l_O_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

ALE ____ Il~

___________________r-l~--

RD*
WR*~-I~_ _ _ _ _ _ _ _ _ _ _ _ _~

BURST*

_I

ACK*Jr-------------------,~

RDCEN*
BUSREQ*
BUSGNT*
EADOE*

---------------------------

==============================______~=========

EADDIR*
EDTACK*
EDS*

------------------.--~

L

-------------------

EBREQ*
EBGNT*
EAS*
ECS*
EAACK*

-----,

---------------------------------L

EATOE*
RAS[2:0]*

6

X_7________________--=-_ _ _ _ _ _ _ _ _ _ __

CAS[3:0]* ~ ____________________________________
DADR[10:0]
DWR*

IU1F

X,-OO_U_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

J
External DMA Master- Slave Write

6.1

44

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

SYSCLK

ADVANCE INFORMATION

n-n-n-n-n- ~n-n-n-n-r---L r\.
h6+j

BUSREQ*
BUSGNT*
OEMAD*

1\

\
\

I

\

RAS*

r-tg..j

1-18-+1

A/D[31:0]
DADR[10:0]

II

1\

DWR*

.;

rc:

IJ

(

dFita wor

1:(

,'.,' .>

r.oll Imn

1\

CAS*

1\

AID Bus DMA Write

6.1

45

ADVANCE INFORMATION

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

105090

111POPO

1115q09

11200~0

11250~0

11300~0

1135000

,111111 1qlllllill qlllllrl, qlrlllill qlrllllil qlrllllil ql,llllll qlllll,
SYSC LK mnlJlJ.JJlJIJ.JJ1llll111ll111Jl1.ll)TJIU)mIDlJI1JIl)iTfll)1JJ1Ullllll11l1ll1ll1lllJIlJlTllllJlJ.JJlJIJ.JJ1llll11JJ1UllJl
AD[31:0)~-X-(X

,[~~~(~YJ

ADDR[3:2)"c=J1.~~YXrI..~~(x;;:O=====
ALE --.I __JL-IL-I-IL-n
I
I
I
I
0_
RD'
WR'

-U-LJ-U-I--1-U-U-I--1-I--1-U-UI~-U-

J
~

BUSREQ'
BUSGNT'

L-I-

DATAEN'

-U-I-.J-I-.J-U-·1-.J-I-.J-I-.J-I_I-I-.J-Ln-IHLf

OEMAD

L-j-

eseleetin'
eautofd'

~1========================================:1

L-I

\__r--

I_I

1_ _1

estrobe'

I

ebusy _ _ _ _ _ _~
eaek'

L-I

eroe'

U

1

L-.J
II

ewoe'
erstrobe _ _ _ _

___'I--I ____~1-'I----_ _ _--~I--~

ewstrobe
dmareq[1 :0)
RAS[2:0)*
CAS[3:0)*
DADR[10:0)
IOWR'
lORD'
IODATA[15:0)

n

II

==============================================-::;X;::DC.~7
=
=F==1i::::=:==;-;:::;;.======================================::rj~=F
=.
.

~.r=x ...l;:g_o_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

-U

---------,

=x__;'-zz_______~-'F'---------'n. .;z-z---------.
Centronics Compatible DMA-Standard
(Application=OO)

6.1

46

ADVANCE INFORMATION

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

150000q

11520000

11540000

11560000

11600000

1158000q

I l i l l l l l l 1l l l l l l l l l l 1111111111 11111111111111111111 111111111111111
SYSCLK
AD[31 :0)
ADDR[3:2)

lJUUUUUUUUIJUUUlJUUUU1J1JUlMJUlJUUUUUUUUUUUUUUlMJUlJUlJUUUl1U1JlJUL

c:)

0
X---x=
E),J O]~_O___Em,-O______
n
n
nL--________

00080000
0

ALE

~

00080000

00080000

00080000

0

RD*~

~I

WR*

1

BUSREQ*
BUSGNT*

'---_ _ _ _ _

------------------------------------------------.1_________
U

DATAEN*

~I

LI

I-

OEMAD _________________________________________~======_r
eseleetin*
eautofd*
estrobe*l"-_ _
ebusy

'_ _I

,.----------------,_________

eaek*

u

LI

eroe*
ewoe*
erstrobe

--.J

"-_____________

r----,I~

_________________

ewstrobe
dmareq[1 :0)
RAS[2:0)*
CAS[3:0)*
DADR[10:0)

===========,------,
____~========~===.;====::.["I--~==========::;;::====::::=
~~ 7

7

Y6

[

==============~
~============~EJ..:.F
~Q F

o.=DI

000

IOWR*
IORD*
IODATA[15:0)

LI
U
_zz_zz____________(~-zzz-z--------------c=lr=zz=zz:-----------ECP Forward Transfer

6.1

47

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

II I I I
SYSCLK

196000
101 1 1

ADVANCE INFORMATION

1198000

1200000

1202000

1 1 I 1 1 I I 01 1 1 1 1 I 1 1 I I 01 1 1 1 1 I 1 1 I I 01 I I I I

I

1204000

I I I I 01

JlJ1IUl

AD[31 :0] ]~OOO~8~OOOO----"'"

~OOO80000

ADDR[3:2]_o_ _ _---::--_ _ _ _ _ _ _ _ _ _ tJ~~_o_=-----~
ALE _______
~n~

n______________________

RD" ___I

__________

1_ _1

WR"
BUSREQ"l _ _ _ _ _ _ _~

-'1

BUSGNr ----1 ______

r-n,__--,

DATAEN*_Il-n
OEMAD

u

-------------------

eseleetin"
eautofd" _ _ _ _ _ _ _ _ _ _ _ _ _

~

estrabe"
ebusy _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
eaek"
erae'

I

----------=====----------------~-

ewoe"
erstrobe

I'. ._____________

-------------------------------'n___

ewstrabe _ _ _ _ _ _ _ _ _ _

II

dmareq[1 :0]

r-II

====:=:l=7======:::;::;========================

RAS[2:0]*:::::7======:::::l=6
CAS[3:0]* F
DADR[10:0]

Orm

000

IOWR"

~

F

EXJ~)rm

U~================~U~

lORD'

_______l'_U~9D

IODATA[15:0] ~u~u

___________~~=

_ _ _---Il~z=

ECP Reverse Transfer

6.1

48

79R3715 SINGLE-CHIP SYSTEM CONTROLLER

ADVANCE INFORMATION

PACKAGE
160-Pin Quad Flat Package (QFP, EIAJ)
31.2 ±0.4

28.0 ± 0.1

'-

r
[C ~;~
1=1= 125

~

[[
:-

126
127
IJ ..J 128
C.1=t=1129
I.T....L1 130
131

,OJ

~~~ ~~~

iT

:I
l-

.134
135
136

:~_

137
138
139
IJ- 140
C '141
142
~~=d 143
144
145

'.I

:_

IJJ

ern

,rq

~d ~:~

~

'._

r~
~-

[cd

148
149
150
151

']152
153
154
'J:I1155

U

iT

~r:=q 156
'-.r:::[1 157

:,.1:::"0 158

:1=I~ 159

i~lJ1160

•
Figure 10.1 160-Pin Quad Flat Package

3134 drw 03

6.1

49

79R3715 SINGLE·CHIP SYSTEM CONTROLLER

ADVANCE INFORMATION

160 - Pin Quad Flat Package-Expanded View (QFP, EIAJ)
31.2 ± 0.4

3.33

+0.551
-0.102

t L
0.1

Seating Plane

3134 drw04

Figure 10.2 Expanded View of Figure 10.1 Detail

VALID COMBINATIONS
79R3715PF

160-pin PQFP

6.1

50

G

Integrated Device Technology. Inc.

LASER PRINTER
INTEGRATED SYSTEM
CONTROLLER

IDT79R3710
IDT79R3740
ADVANCE
INFORMATION

FEATURES
• Pin-Compatible System Controller with Laser Printerspecific features for the lOT R30xx family of processors
• DRAM Controller
- 1 - 40 MB directly, 1 - 3 banks directly
- Device depth supported: 256K - 4M
- Non-interleave
• ROM Controller
- 1 - 20MB, Address-space support bank size: 1- 8MB
- Support for standard and burst ROMs
- Support for interleave or non-interleave
• Direct Interface to Adobe Typhoon rasterizer coprocessor
• I/O Bus follows 8/16-bit Intel 80186 style
• I/O Controller
Two 8-bit and two 16-bit external channels
- DMA and non-DMA access for the 8-bit channels
- 8-32 packing, 32-8 unpacking logic for DMA access
- 16-32 packing, 32-16 unpacking for CPU/ Typhoon
coprocessor accesses
- Round robin arbitration
- Programmable timing for I/O and control signals
- Big and little end ian support
• PCMCIA Support
- Through 16-bit I/O bus, using simple glue logic
- 16-bit to 32-bit packing and 32-bit to 16-bit unpacking
- Big and little endian support
- 256MB address space dedicated to 2 PCMCIA slots
• Engine Control
- Supports control and status lines to the engine
- Horizontal and vertical margin counters
• 24-bit Timer/Counter, In-Circuit testing capability
• High-performance CMOS technology

• Video Controller
- Four-entry (32-bit wide) FIFO with data serializer
Video data Phase Lock Loop (PLL)
- DMA support (with chaining)
- Full duplex printing support
- Inverse video
- 1OMHz with PLL, 28MHz with external clock
• Centronics Interface
- Bi-directional Centronics, compliant with IEEE1284
- Supports DMA and CPU controlled transfers
- Supports the following modes:
- Compatible; Nibble; Byte; ECP; EPP
• Interrupt Controller
- 6 external level interrupts (through the PIO pins)
- 14 internal interrupts
- Individual interrupt mask capability, enabling polling
or interrupt-driven systems
• General Purpose I/O
- Six programmable Input (interrupts) or Output pins
SpeciallDT79R3740-only features
• UART on-chip, 16550-style
• Incorporates Adobe Memory Booster Technology
- Achieves greater than 4:1 lossless compression for
most pages
- Reduced DRAM requirements up to 4 MB for 600
dpi letter-size; with higher resolutions, achieves
even greater DRAM savings
- Supports monochrome and bi-Ievel color devices
- Always prints the page with minimum memory cost
- Supports printer page rates up to 20 ppm

DRAM/ROM
Control

G.P.I/O

Adobe
Frame Buffer
Compression
and

lOT
R3041,
R3051,
R3052,
R3071 ,
or R3081
RISControl\er

AppleTalk

D(~~T8~~y~on
Bidirectional
Centronics

~~~f~Jlf:r~~~
Coprocessor

Bus Master
DMA Interface

UART
(3740 only)

1DT79R3710 and 1DT79R3740

IDT79R3710 and IDT79R3740 System Organization

3710·20

The lOT logo is a registered trademark. and R3710 and R3740 are trademarks of Integrated Device Technology. Inc. All others are trademarks of their respective companies.

COMMERCIAL TEMPERATURE RANGE
© 1995 Integrated Device Technology, Inc.

MAY 1995
6.2

DSC 9092/-

1

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

ADVANCE INFORMATION

OVERVIEW
Adobe Memory Booster Technology
(For the R3740 only)

The IDT79R3710 and IDT79R3740 are single chip
CMOS System Controllers designed to complement lOT's
R30xx family of 32-bit embedded processors. They have
all of the features necessary to implement a high-performance, high-quality, feature-rich laser printer, at a similar
or lower cost than that of low-end laser printers.
For instance, both the R3710 and R3740 facilitate the
implementation of high-quality Multi-Function imaging
products (printers that include functions such as fax,
copier, or scanner). In addition, the R3740 includes stateof-the-art Adobe Memory Booster (AMB) technology. The
R3710 and R3740 can be interchanged in a single
design, allowing multiple end products from a single
design effort.
The R3710 and R3740 support high resolution
printers, since they can move large amounts of data
quickly without the need for processor intervention. They
also achieve a significant reduction in system cost by their
high level of integration, and for the R3740, from the AMB
circuitry on-board. Additional savings come from the
architecture of the I/O controller, which allows for the utilization of low cost peripheral components (disk controller,
network controller, etc.), while attaining the higher level of
performance only associated with costlier components.
Some of the architectural characteristics that result in
very high performance include:
incorporating a tightly coupled interface to the
R30xx RISC CPU;
minimizing latency to critical resources;
partitioning the system in a balanced way to
attain efficient use of shared resources;
enabling several simultaneous operations in the
system.
The R371 0 and R3740 are ideal for modular design of
laser printers because they allow a high level of programmability, and because they incorporate the control logic
for an industry standard interface to peripherals. This
gives OEMs the ability to offer several products from the
same basic design, as well as the ability to upgrade
systems in the field.
Block diagrams on the following page show R3710
and R3740 configuration.

In the R3740 Controller Adobe and lOT provide a
comprehensive solution for memory cost reduction that
supports a complex set of system goals. Two underlying printer implementation strategies are supported.
First, the compression scheme must consistently
provide greater than four-to-one compression for most
of the pages printed, across a wide range of page
styles, using a loss less compression algorithm to maintain high page quality, regardless of data type (fonts,
graphics or scanned halftone images). This affords the
opportunity to significantly lower memory cost.
Secondly, Adobe memory booster always prints
the page, avoiding the all-or-nothing extreme of full
compression or the "page not printed because" error
message. To implement this strategy, Adobe Memory
Booster utilizes a two-step process, beginning with a
lossless compression algorithm to provide full
compression in a minimum memory system. If this
cannot be achieved in the available memory space, a
new data compression technology from Adobe
provides a price/quality trade-off by achieving a higher
compression ratio.
Both the loss less and the alternative compression
technologies used by Adobe Memory Booster are
implemented in the R3740, providing full support of this
cost- saving strategy.

6.2

2

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

ADVANCE INFORMATION

IDT79R3710
Printer
Engine
Memory
System

DRAM
Control

Modes:
Compatible
Nibble

8,tte

CPU

ECP

EPP

Coprocessor

3710-21

IDT79R3710 Block Diagram

Memory
System
Adobe
Frame Buffer
Compression &
Decompression

Engine
Interface

CPU
10 Ports

Centronics
Interface

Coprocessor

Serial
Interface

3710-22

IDT79R3740 Block Diagram

6.2

3

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

FUNCTIONAL DESCRIPTION

Co-Processor (Typhoon) Interface

Processor Interface

The R3710 and R3740 have simple interfaces to the
Typhoon coprocessor. They support the Typhoon in its
slave and master modes of operation. As slaves they
support the processor read and write accesses to the
Typhoon, and as masters they enable Typhoon access to
the DRAM, ROM, and 16 bit 110 bus (for font cartridges).
The R3710 and R3740 directly control the data buffers
and the address buffer needed to isolate the Typhoon
from the AID bus.
The R3710 and R3740 decode CPU access to the
Typhoon and assert TCS*, TAS*, and TDS*. The address
is latched into an external transparent latch (373-type)
when the processor asserts ALE and is driven into the
Typhoon multiplexed bus (DAL[31 :0]) by TATOE*. Data is
driven to or from the Typhoon by transceivers controlled
by TADDIR* and TADOE*. To end a Typhoon cycle both
the R3710 and R3740 assert RDCEN* and ACK* to the
CPU when the Typhoon asserts TDTACK*.
In Typhoon master mode, the Typhoon requests the
bus by asserting TBREQ*. The R3710 or R3740 will
grant the bus by asserting TBGNT* (provided no other
DMA device has requested the bus and provided also
that it was granted by the CPU to the R3710 or R3740).
The Typhoon will assert TAS* first, and then TDS*, to
initiate an access to a system resource (e.g. DRAM). The
R3710 or R3740 will assert TADOE* and TADDIR* to
drive the Typhoon address, and ALE to latch it. In the
data phase it will assert TADDIR* and TADOE* according
to the access direction (Read or Write).
To end the cycle the R3710 or R3740 will assert
TDTACK* to the Typhoon. When it does not require the
bus any longer the Typhoon will release it by deasserting
TBREQ*
Typhoon access to the DRAM takes 5 clocks from
TAS* to TDTACK*. Frequencies above 25 MHz may need
an additional clock cycle. One clock can be added to this
interval by using the TypExtCas bit in the DRAM control
register.
Figure 2.2 shows the implementation of the Adobe
Typhoon Coprocessor interface.

The R3710 and R3740 have a glueless interface to
the IDT R3041/51/52171/81 family of RISC processors.
They operate either as a slave, supporting CPU access
to memory and 110 devices, or as a master, handling
accesses on the AID bus.
As slave the R3710 or R3740 supports processor
single transfer read or write, as well as burst read
access. Each supports processor access to the ROM,
DRAM, devices on the I/O bus, the Typhoon coprocessor
and the R3710 or R3740 internal registers. Burst read is
supported only for DRAM or ROM read access. ACK*
and RDCEN* timing is fixed for both the R3710 and
R3740 registers. DRAM access can be extended by one
clock, and access timing for ROM and I/O are programmable.
As master the R3710 or R3740 will request the bus
by asserting BUSREQ* when a DMA source (internal or
external) needs to transfer data to or from the DRAM I
ROM I 1/0 Channel.
The priority between the DMA sources is in the
following descending order:
Access in process
Video out
Decompression and compression
(for the R3740 only)
I/O DMA
Typhoon.
The CPU will get ownership of the AID bus for at
least one cycle after four DMA accesses. This assumes
that each Typhoon (external agent) bus possession is
counted as one, regardless of the number of transfers it
executes on the bus. In the default state, when there is
no DMA request, the bus is owned by the CPU.
Figure 2.1 shows the CPU-to-R3710/R3740 interface.

AD(31:0)

R3041
R3051
R3052
or
R3081

Addr(3:2)
Burst*
ALE
SysClk*
Rd*
Wr*
Ack*
RdCEn*
BusReq*
~ BusGnt*
Int*
- DataEn*

\32

2

ADVANCE INFORMATION

'

IDT79R3710
IDT79R3740
3085 drw 03.1

Figure 2.1: RISControlier to R3710/R3740 Interface

6.2

4

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

Address/Data Bus

" :,';"r;;'c'
"

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<

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,.' ,,',,'","',:
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TADOE
TADDir

FCT162373X2j~!,i

1

[;',),

TATOE

BCAdr
(jj

ADVANCE INFORMATION

BCData

~~

.c.::x:

BCRW

On:

:.:.cn
u
C1l
CO

Adobe
Typhoon
Font
Rasterizer

BReq

TBReq

BGnt

TBGnt
TAS

AS

TDS

BCOE

OS

BCCS

DTAck

TCS

CS
WRCPUIReq

-.
RESET

AAck

!

TDTAck

TAAck

RESET
SYSClk

SYSClk

IDT79R3710
IDT79R3740
30B5 drw 10,1

Figure 2,2: Adobe Typhoon Coprocessor Implementation

support burst ROMs, and can be made to write to the
ROM space (for Flash or debug) with additional glue
logic.
After reset, the R3710 or R3740 is configured with
the maximum number of wait states between each data
transfer (16 clocks between each RDCEN*) and 64
clocks between ROMCS[x]* to ACK*. The initial (reset)
space size for ROMCS[1]* and ROMCS[O]* is 1 Mbyte,
and 4Mbytes for ROMCS[2]*.
Figure 2.3 shows the configuration of the
ROM/DRAM memory system.

ROM
The ROM controller supports up to 20 Mbyte of
memory with several device types and system configurations. To support these system and device options, the
assertion time of RDCEN* and ACK* by the R3710 and
R3740 can be programmed, thus accommodating
different types of memory architectures, including standard ROMs, interleaved ROMs, and burst ROMs.
There are three CS signals to support up to three
banks of ROM. Each ROM bank can be either non-interleaved or interleaved (composed of 2 leaves of ROM
differentiated by ADDR[2]). ROMCS[2]* controls the boot
bank and has a fixed address space of 4 Mbyte. Address
space for ROMCS[1]* and ROMCS[O]* is programmable
to 1, 2, 4, or 8 Mbyte.
The R3710 or R3740 puts the 3 ROM bank address
ranges in a contiguous address space. In other words,
the start address of the next ROMCS[x]* will follow the
last address of the previous ROMCS[x-1 ]*. For interleaved support, ROMOE* is provided to control the OE of
the interleave multiplexer. The R3710 and R3740 also

6.2

5

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

ADVANCE INFORMATION

IDT79R3710
IDT79R3740

- - EPROMiROM - Addr(10:0)

- - EPROMiROM - -

ALE

3085 drw 04.1

Figure 2.3: R3710/R3740 ROM/DRAM Memory System

DRAM

ered in a 4-deep, 32-bit-wide video FIFO and serialized
for output to the print engine video input. A video PLL is
provided for synchronization of the video to LineSync.
A PLL bypass option is provided for systems with an
already-synchronized video clock.
The Serializer can shift video data in either direction to support duplex printing. Also, horizontal and
vertical margin counters are provided and appropriately synchronized to PageSync and LineSync.
Figure 2.5 shows the R3710/R3740 engine interface.

. The DRAM controller supports directly 1 to 40 Mbytes
of DRAM, with up to three non-interleaved banks. The
address space starts at physical address O. The DRAM
device types supported have the following attributes:
page mode, early write, and "CAS before RAS" refresh.
The DRAM controller supports single transfer reads
and writes and burst reads. Various DRAM device depths
are supported and the address space is continuous for
the selected configuration. The DRAM controller can be
configured to support different device depth for the base
bank (RAS[O]*) and the extension banks (RAS[1]* and
RAS[2]*).
For systems running at high frequency there is an
option to extend the CAS* signals by an additional cycle.
Since the Typhoon samples data on the rising edge of
SYSCLK*, and the CPU on the falling edge, for systems
above 25MHz it may be necessary to extend the CAS* by
one cycle for Typhoon accesses. To minimize the refresh
penalty lOT recommends you program the refresh
frequency according to the value of SYSCLK*.
The initial values of the R3710 and R3740 control
registers at reset are shown in section 3.13.

~D179f~37'IO~~~--------------~VDO
~~~~--------------~BD
~~~~--~~~----~VSREQ
~____--1 SBS,(

~

~~
'I;rz--;tm~~{~~::=j-lPPRDY
ROY
STS

I----""-JcPRDY
I-----IVSYNC
I------t~ PRNT

Q)

"6,
I1j

I--_--I~CBS'(

CCLK

Programmable Engine Interface

I-----II~CMD

The R3710 and R3740 move data from the page
buffer memory (for the R3740, compressed data in
DRAM) to the print engine by DMA in two ways: 1) For the
R3740, through the decompression logic for compressed
bands, or 2) for the R3710, directly. 32-bit words are buff-

L-__1-----~PCLK
3085 drw 05.1

Figure 2.5: R3710/R3740 Engine Interface

6.2

6

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

PIO Port

port.

Each of the PI0[5:0] pins can be individually
programmed to be an output or input pin by writing to the
PIO Control register. When programmed as an· input pin it
can be used as a level (active LOW) interrupt. The PIO
pins are synchronized and pulled up internally. At reset,
all PIOs are initialized as inputs.
For the R3740 only, the PI0(4) and PI0(5) pins are
shared with the UART pins RI and DCD, respectively.
Their functionality (PIO or UART) is determined by bit 6
in the PIO control register.

(
~fR3710

Interrupt Controller
Each interrupt source on the R3710 and R3740 is
maskable. The Cause register bit will reflect the cause of
the interrupt, and writing a '0' into it will acknowledge the
internal interrupt. For example - if the "Sandlnt" bit was
active, the CPU should write 'fffB' into the Cause register,
in order to reset the interrupt flag.
The external interrupts, PI0[5:0], are acknowledged
at the source of the interrupt (the interrupt flag is deasserted when PIO is inactive), the corresponding bits in
the Interrupt Cause register are read only.
At reset, all interrupts are masked in the mask
register.

DMA AppleTalk
One of the DMA-supported I/O channels can be used to
support AppleTalk directly, with only the addition of an
external communication controller, such as the 85C30 or
85C230, and the I/O interface devices it requires. The
R3710 and R3740's 110 FIFO and Surst DMA capabilities
aid in the separation of the real-time demands of the
AppleTalk protocol from the real-time demands of the
engine interface, but without the system cost implications
of "buffered" AppleTalk.
Figure 2.8 shows the configuration of an AppleTalk I/O

ADVANCE INFORMATION

6)
..

IOData(7:0)
:'1,

lORd
IOWr
IOCS{O)

85C30
or
85230

IODReq{O)

IDT79R3740

B~
mGi
3085 drw 07.1

Figure 2.8: DMA-Supported AppleTalk I/O Port

Programmable Timer/Counter
The general purpose timer/counter can be
programmed to function as a timer or as a counter. As a
counter, it will cause an interrupt and stop counting when
it reaches terminal count. Writing a new value to the
counter will start the counter if the Enable bit is active. As
a timer on terminal count, it will cause an interrupt, reload
with the value stored in the Timer/Counter Value register
and continue to count.
The Timer/Counter counting is enabled or disabled
by the enable bit. The value n should be written to the
Counter in order to count to n clocks. At reset, the
counter is disabled.

I/O Bus
The R3710 and R3740 support two 8-bit (IOCS[1 :O]*)
and two 16-bit (IOGPIlCS[1 :0]*) external I/O channels
that share the IODATA[15:0] pins. The two 8-bit I/O channels and the first 16-bit I/O channel (IOGPCS[O]*) each
has a 16 Mbyte address space. The second 16 bit I/O
channel (IOGPCS[1]*) has a 256 Mbyte address space.
Timing of the control Signals to an I/O channel is
programmable. The user can specify the length of 10RD*
and 10WR* signals. The IOCS[1 :0]*, IOGPCS[1 :0]* or
DMAACK[1 :0]* are asserted one cycle before the 10RD*
or 10WR* signals become active, and remain active for
one cycle after 10RD* or 10WR* are dasserted. RDCEN*
and ACK* will be asserted by the R3710 or R3740 to end
a processor (or TDTACK* to end a Typhoon) I/O cycle.
Figure 2.10 shows the configuration of the general
purpose I/O device interface.

6.2

7

tI

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

1/0
Device

ADVANCE INFORMATION

The R3710 and R3740 support processor and
Typhoon accesses (reads and writes) to devices located
on the two 16-bit 110 channels.
For 16-bit devices, the CPU can read or write to any
byte or half word. Processor or Typhoon access to the
16-bit I/O channels with any combination of byte enables
active, will be performed in two consecutive I/O cycles in
case of 3 or 4 byte accesses. In the two cycles, data will
be packed or unpacked from a 32-bit register for an I/O
read or write respectively. Conversion between big and
little endian is supported for 16-bit devices.
The following signals support Canon type engines: a)
Engine Strobe (ESTROBE*) - Clocks data into the engine
control register from IODATA[15:0] to be driven to the
engine and b) Engine Output Enable (EOE*) - drives the
engine status to the IODATA[15:0].

3085 drw 06.1

Figure 2.10: General Purpose I/O Device Interface

8-bit 110 Channels
The R3710 and R3740 support processor byte
accesses (reads and writes) to devices located on the
two a bit 110 channels. These accesses can be made
using any of the four bytes on the 32 bit data bus. The
R3710 or R3740 will transfer the correct byte (according
to the 4 Byte Enables) to the a bit 110 bus (/ODATA[7:0]).
The I/O channel unit on the R3710 and R3740 operates as a DMA controller with the two a bit I/O channels.
DMA operations between 110 devices and the DRAM are
supported. Eight bit data is packed or unpacked during
DMA access into a 32 bit register for I/O DMA read or
write respectively.
DMA Operations
Processor requests have priority over DMA
requests. The priority for DMA operations is round robin
for the Centronics and the two external a-bit DMA
engines. DMAREQ[1 :0]* can be masked by writing '0' to
the enable bit of the channel. A channel will not participate in the arbitration if the channel is disabled or if the
I/O BIU (Bus Interface Unit) is owned by another channel.
The I/O BIU is emptied into memory in a DMA read
access under the following conditions: 1) if the I/O BIU is
full, or 2) if there is no DMA request (DMAREQ[1 :0]) from
the channel which owns the I/O BIU for a time out period,
or 3) the byte count reaches zero.
In the write direction if the DMAREQ* from the
channel that owns the I/O BIU is not active for a time out
period, and the 110 BIU is not empty, arbitration will
resume on the I/O bus. The time out period is set to 32
clocks. The clock period value cannot be changed, only
enabled or disabled.
16-bit 110 Channels

6.2

8

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

Centronics IEEE 1284 Communication

3) Pagelnt - active when PAGESYNC* is active.

lOT's Centronics implementation meets the IEEE
1284 definition of a compliant device. It supports the
following modes: Compatible, Nibble, Byte,. ECP and
EPP, as well as the negotiation necessary for transition
between different modes. Support for the Compatible
mode includes the following three variations: Standard,
IBM Epson, and Classic.
NOTE: This data sheet does not include a complete
discussion of the IEEE 1284 bi-directional Centronics
standard. lOT urges designers to review the IEEE1284
Rev. 2 specification.
There are two ways to handle the Centronics
protocol. In the first option, data is transferred in DMA
fashion and is only applicable in the Compatible, ECP,
and EPP modes. The second option is interrupt driven,
and applies to all modes. That is, Byte and Nibble modes
are only interrupt driven.
There is support for special character detection in the
Centronics incoming data. Control data characters like I\C
or I\T can be detected and the CPU will be interrupted.
Figure 2.11 shows the configuration of the IEEE
P1284 bidirectional centronics I/O port.

<0
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address

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RAS*

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r-t2o--j

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\

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'--t7I

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ACK*

\

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DRAM Write

SYSCLK

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n- n- ' L' L' L' L' L ~ rL n

ALE
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A/D[31 :0]
BURST*
DADR[10:0]
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RDCEN*

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DRAM Burst Read

6.2

64

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

SYSCLK
ALE

A/D[31 :0]
ADDR[3:2]

--1l~

_________________________________________________

=x____
..!!O~

ADVANCE INFORMATION

X.....;F_F;...;.FF"'-'OO_10_ _ _ _ _ _ _ _ _---..IX'-.;...;FF...;,..FF;..;..F.;...;FF..;..F_ _ _ _ _ _ _ ___

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IODATA[15:0]
IOBE[1:0]*
IOA1

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X_2_________________

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___________

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- - - - - - - - - - -_ _----_~I

1/0 Read 16-8it

SYSCLK

IOGPCS*

IOWR*

IOA1

IOBE*

_______ '-__~_~d~atwa_______x,~

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c'-_ _~da~t~a_ _ _ _ _ _ _~~

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I/O Write 24-8 it

6.2

65

ADVANCE INFORMATION

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

SYSCLK:
ALE ; _ _ _ _ _..J

ADOR[3:2] li;:.:..;.~~~;.;.;;t\,----,!lllillJ.L-+-_-I-_~_ _~_-+-_-+

__+-_-+-_......J
.

,

A/O[31 :0] F~;J..--aqctras.~~-¥~*~~~~I;..--~-~--~-~-~
TBREQ*

TBGNT*

TA8*

TAACK*

T08*

TDTACK*

TAOOIR*

t14~

IOOATA[15:0]
IORO*

~~~~~~~~~~~m=t=r~~~Ii~

''--JJ
Typhoon Master 110 Read

6.2

66

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

ADVANCE INFORMATION

SYSCLK
AO[31:0]
AOOR[3:2]
ALE

Y2
h
~--~~--------~----------------------------------~~
0

n~----------------------------~~

~

L-

RO*
WR*
BURSr
ACK*
ROCEN*

~

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BUSREO*

Jl

BUSGNr

~
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TAOOE*

H

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TOS*

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TAS*
TCS*
TAACK*

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RAS[2:0]*

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1000

u
Typhoon Master Read-R3710

6.2

67

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

2900000

1

, I,

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I, I I I, I rO,OOIOO,O I " , I,

12950000

I I I,

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ADVANCE INFORMATION

13050000

,I,

I I
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SYSCLK
AO[31:0)
AOOR[3:2)
ALE
RO"

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BURST*

______________________________

~~3_ _ _ _ _ _ _ _1~2

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1000

u

Typhoon Master Read--R3740

6.2

68

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

3090000

13100000

13110000

ADVANCE INFORMATION

13120000

13130000

13140000

III 1 1111111111 111111111111111111111111111111 1111111111

I

3150000

111111111 I I I

SYSCLK
AD[31:0]
ADDR[3:2]
ALE

OOOOFEAO

12

3

n

l

~

____________________

______

I

RD'
WR*

r-n

H

BURST'

LJ
LJ

ACK'
RDCEN*
BUSREO'

~n~

~

BUSGNr
TADOE'
TADDIR*

H

TDTACK'
TDS'
TBREO'

-r-i
-,

U

LJ

H

TBGNr
TAS'

~

H

L-'

TCS'

U

TAACK'
TATOE'
RAS[2:0]*
CAS[3:0]*
DADR[10:0]

17

"7"")6
F
o1F

~O
~'AB

Is

r===f
~o

IF

X olF

~26B

X268

1402

L-.-J

DWR*

Typhoon Master Write-R3710

6.2

69

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

ADVANCE INFORMATION

SYSCLK

~

____~~

rl~

______________~

IH
~~r-l~----------~H~~~

--------~-~~LI------------~~~=====~

U

------~ur--------------------------------

----~==~--------------~~~======
I
----------~I

I

1

I
U~

1-1

H~~--~~~------~H
r---~~---------

I

~

I

H

u
16

17
15
LJo
~~~~~~~~~~:;t=l=-=:;.~=======::;r=n;::::::;;;:FO

IF

~----~~~~1~~~~~~~~='~~;~6==~;g1~~~~6==~====~~r~~o~=======

====~~====~~U~===============
Typhoon Master Write--R3740

6.2

70

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

2560000

12570000

12580000

ADVANCE INFORMATION

12590000

11111i1l11l
1
111111111111111111111111111111

12600000

12610000

IIl1illlll

SYSCLK
AD[31:0)
AODR[3:2)
ALE

A8000018

3

______

1

0

~n~

__________________________________

~r

RD*
WR*
BURST*
ACK*

u

-U

L

u

RDCEN*
BUSREO*
BUSGNT*
TADOE*
TADOIR*

L.--J

TDTACK*

I

TOS*
TBREO*
TBGNT*

LJ

TAS*
TCS*
TAACK*
TATOE*

Xl

RAS[2:0)*

6

CAS[3:0)*

~_F_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

DADR[10:0)
OWR*

Yl
~~-----------------------------------------------

Typhoon Slave Read--R3710

6.2

71

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

2560000

12570000

12580000

ADVANCE INFORMATION

12590000

12600000

12610000

1
11111111111111111111111111111111111111111111
1111111111111

SYSCLK
AD[31:0]
ADDR[3:2]
ALE
RD*

~~==~========~~~======~~~
_3_ _ _ _--Alo__________________. . .~

n'--_________---;;::::=========~IL

========;1---1

I
I

WR*
BURSr
ACK*

'-

U

~

LJ~---------

RDCEN*
BUSREO*
BUSGNr
TADOE*
TADDIR*

L-J
I

TDTACK*
TDS*
TBREO*
TBGNT*

U

TAS*
TCS*
TAACK*
TATOE*
RAS[2:0]* ~ 6

X7

CAS[3:0]* ~F

'E:

DADR[10:0] ~ooo
DWR*

~~~========================~~

Typhoon Slave Read-R3740

6.2

72

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

I

2580000
1

2585pOO

r590000

111111111111111111

12595000

ADVANCE INFORMATION

I

2600000

I

2605000

I

2610000

IIdddl dllddl dllllill IIdlllll ddllill

I

SYSCLK

XlCOOOOOO
ADDR[3:2]

3

Xo

ALE~~________________________________~r-l~

____

RD*
WR*
BURST*

~~

____________________________~

-.-J

ACK* Jr----------------------------------~~
RDCEN*
BUSREQ*

BUSGNT*
TADOE*

--------------------------------------------------------

================================____________~==========
L

TADDIR*
TDTACK*
TDS*
TBREQ*
TBGNT*
TAS*
TCS·
TAACK*

L

TATOE*

RAS[2:0]*
CAS[3:0]*
DADR[10:0]
DWR*

~~7=========================

Q_F___________________________________________________

r::=J. . .

OOO
_ _________________________________________________

J

Typhoon Slave Write--R3710

6.2

73

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

2580000

12585000

12590000

12595000

ADVANCE INFORMATION

12600000

12605000

1

2610000

1111 1 dd""1 IIddIlI ddlldl ddl/III dd""1 d"ddl ddddl
SYSCLK ULSl-.J

12615000

I

AD[31:0]-,-r=_1_ _D~ooooo
ADDR[3:2]

_3_ _ _..X,_O_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

ALE _ _ _~r_l~

_________________________________~rl~_____

RD*
WR*

rl~

_______________________________

~

BURST*

ACK*-~~==~---------------~~~------RDCEN*
BUSREQ*
BUSGNT*

n

TADOE*
TADDIR*
TDTACK*

n

TDS*

L

TBREQ*
TBGNT*
TAS*

~

TCS*

TAACK*------------~==========~----------------------====
TATOE*
RAS[2:0]*

-r=-=y7

CAS[3:0]*

~r;:-F------------------------

DADR[10:0]
DWR*

---'r==Jgo
----1

Typhoon Slave Write--R3740

6.2

74

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

ADVANCE INFORMATION

SYSCLK
IOGPCS*

~ t26 ~
IOWAIT*

--------~--------------

IOWR*

/

\~--------------------~
25~

I/O Write (With Wait State)

SYSCLK
DMAREQ

DMAACK*

t16
I-----+----~----~~

IORD*I-----+----+---~~--~~

IODATA[7:0] I----+----+---~----_f

r--....I..I..O""-t'

1/0 Bus DMA Read

6.2

75

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

SYSCLK

'L

n-

~' L

ADVANCE INFORMATION

n- ' L n- ~ ' LrL rL n.

H6+/
BUSREQ*
BUSGNT*
OEMAD*

1\

\

1/

\

I

\
1\

DWR*

-tS..j

A/D[31 :0]
DADR[10:0]
RAS*

/

-t9-.J

{

d8ta war

IX

m

r.oll Imn

\

CAS*

1\

I

AID Bus DMA Write

6.2

76

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

ADVANCE INFORMATION

SYSCLK
AD[31 :0]
ADDR[3:2]

;;:=~~~~:;-;;;:;;;::'~;;;¢=.:;;;;~::::;;~~~~~-;;:~~~==;;;~~::::u:r,;::=====
_0_--I..A.I\I\III.-..-1UUIM._JIU1~--IlIUILI\..---1h'\-M~-M...MA...--AII..N\JL--AIII..MA_.JlAJlIILA-_M...._ __

ALE __~-~l~-~L--I~-~~-~~--~--+--~-~L-_ _ _~L_
RD'

UL.Jl.JU--u-LJLJ

WR*

J

BUSREQ*

- - - - - - - - - - - - - - - - - - - - - - - - - - -L s -----------------------------------------Ls-

OEMAD

cselectin*
cautofd*

~l======================~1L-J
~

cstrobe*
cbusy _ _ _ _ _ _ _ _...J.

~r----~

LJ

cack*

________

croe*
cwoe*

- - .I~______________ r
crstrobe _ _ _ _ _ _ _ _~,r -I~
__ _.
_.
__
~I
l - - JL - - - cwstrobe

n

dmareq[1 :0]

n

=

=========--==============--=============~E::XC;::V:;:7
CAS[3:0]* ~F==========================::;~
RAS[2:0]*

DADR[10:0]
IOWR*

==~~~================================~==
==ro
go

11

IORD*---------~U~-------~Urr-----------------------

______---,O,-,f_2_______n,-,~,-2Z_____________

IODATA[15:0] ==X~~,,-2Z

Centronics Compatible DMA-Standard
(Application=OO)

6.2

77

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

'500000

1'520000

1'540000

ADVANCE INFORMATION

1'560000

1'580000

1'600000

111111111 / 1111111111 1111111111 1111111111 ,,"111111""1"111""1
SYSCLK
AD[31 ;0]
ADDA[3:2]

_00_08_000_0_ _

= ' - 0_____'[JJJ'-0_________

AD*
WA*

n

n

ALE

nL..._ _ _ _ _ _ __

L--J

---------------------------------------------

-JI

BUSAEQ*

L...-_ _ _

BUSGNT*

U

U

DATAEN*

I-

======-,

OEMAD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

cselectin*
cautofd*
cstrobe*

IL.__--J

cbusy

r - - - - - - - - - , L . -_ _ _---'

cack*

u

croe*

u

cwoe*
crstrobe

-----1

cwstrobe

.;::=========,--,
__-=========~==::;;::===lI-~==========:;;:===;ii=
7
El7
~
==============~
~==========~~
CAS[3:0]* F
ElF
~

dmareq[1 :0]
AAS[2:0]*

DADA[10:0]

rr=DI

000

IOWA*
IOAD*
IODATA[15:0]

U

U

_=_z_ _ _ _ _ _ _Dl....J\,z_=________c=Jr.:::z==---------

ECP Forward Transfer

6.2

78

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

ADVANCE INFORMATION

196000
1198000
~ooooo
1202000
1204000
I 1 1 1 1 101 1 1 1 1 I 1 1 1 1 01 1 1 1 1 I 1 1 1 1 r 1 1 1 1 1 I 1 1 1 1 01 1 1 1 1 I 1 1 1 1 01
SYSCLK

ITfIo

F

__~~====~__~======~n~__~==
u

L
L

II

~-------------------~
r---LL

I

u

IOWR'
lORD'

I_

IOOATA[1S:01_zzz_z_ _ _ _ _ _ _.a.zz_9D_ _ _ _.AI_zz_zz_ _ _ _ _ _ _ _---,,-p_6_D_L--

ECP Reverse Transfer

6.2

79

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

ADVANCE INFORMATION

PACKAGE
160-Pin Quad Flat Package (QFP, EIAJ)
31.2±0.4

28.0±0.1

LL

121
122
123
LL; 124
I_Tl 125
TTl 126
r:r: 127
[:L, 128
129
L[J 130
[JJ 131
TTj 132
IT': 133
1=1,134
JT: 135
TT] 136
J]j 137
138
TJ:1139
:-CI: 140
,_r11141
[IJ 142
IT! 143
,IT: 144
, LIJ 145
:1:::Lj 146
~I=r: 147
Ll~ 148
149
: r~IJ 150
JTJ151
152
J::::[~ 153
~TLi 154
155
1':"1=' 156
157
l]J 158
lT~ 159
r"[ 160

. IT;

-u;

IX

'l:n

TC

U--::tJ

:rn
'-[:r:::

•

Figure 10.1: 160-Pin Quad Flat Package

3134 drw 03

6.2

80

79R3710 and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

ADVANCE INFORMATION

160 - Pin Quad Flat Package-Expanded View (QFP, EIAJ)
31.2±OA

+0.551

3.33 -0.102

t0.1 L

Seating Plane

3134 drw 04

Figure 10.2: Expanded View

6.2

81

79R3710.and 79R3740 LASER PRINTER INTEGRATED SYSTEM CONTROLLER

ADVANCE INFORMATION

ORDERING INFORMATION
IDT79

yy

xxxx

Operating
Voltage

Device
Type

999
A
A
Speed Package Temp Rangel
Process

I .. ~Blaok

LIP
~

____________~25
33

I -__________________

~

R3710

Commercial
(O°C to +85°C Case)

160-Pin PQFP

25 MHz R3710
33 MHz R3740

Laser Printer Controllers

R3740

R

5.0+1-5%
3710-27

Figure 11.1: Ordering Information

6.2

82

R4761 ORION
Family Memory
and 1/0 Controller

ORtoN
IDT79R4761™

Product Brief

Integrated Device Technology. Inc.

FEATURES:
• Direct interface to IDT ORION R4600/R4700/R4650 RiSe
processors
- 64-Bit interface support for R4600/R4700/R4650
- 32-Bit interface support for R4650
• 50 MHz bus frequency
• 1 Gbyte address space
- Flexible DRAM interface
- Direct interface to 512 Mbytes
- Available two-way interleaving
- Transparent refresh
- Supports 16 Mbit DRAMs
- Individually programmable timing parameters,bank sizes
• RS-232 serial port (16450 UART)
• Flexible ROM/SRAM interface
- Direct interface to 64 Mbytes
- Available two-way interleaving
- Each bank can be ROM, SRAM, or Flash ROM
- Individually programmable timing parameters and bank sizes

• Serial EEPROM interface
- Reads 256 configuration bits at power-on
- Reads 8- and 16-bit random values
• Peripheral interface
- Four ports total
- Three ports configurable as DMA
- "Smart" DMA support
- External intelligent agent (e.g. R4762)
interface support
- Single and demand DMA protocol
- Two "queued" DMA channels
- Programmable timing parameters
• Memory-to-memory DMA channel
• Interrupt controller/prioritizer
- Eight interrupt levels
- Fixed or rotating prioritization
• Packaged in 208 PQFP

DRAM
Memory
Interface

R47001

ROM
SRAM
FLASH ROM

CPU

ORION
R46001

Interface

R4650

Interrupt
Prioritizer

SERIAL EEPROM

Address
Map
Control

DMA
Peripheral
Interface

Control

R4762
"SMART" DMA
GENERIC DMA
USER 1/0

FIGURE 1: 4761 BLOCK DIAGRAM

The IDT logo is a registered trademark and Orion, R4650, R4600, R4700,R3081, R3052, R3051, R3041, RISControlier, and RISCore are trademarksof Integrated Device Technology, Inc

SEPTEMBER 1995

COMMERCIAL TEMPERATURE RANGE

DSC·9093/·
© 1995 Integrated Device Technology. Inc.

6.3

1

IDT79R4761

COMMERaALTEMPERATURERANGE

DESCRIPTION:
The IDT79R4761 is a high performance memory/peripheral
controller for the IDT R4600, R4700, and R4650 RISC microprocessors. The on-chip functions include: an OrionlR4650 interface,
an R4762 interface, a serial EEPROM controller, a DRAM
controller, a ROM/SRAM controller, a peripheral interface with
DMA capability, an interrupt controller/prioritizer, and a serial
interface (UART).

DRAM or ROM/SRAM at the full memory transfer rate (one
doubleword per clock for interleaved configurations), and can be
selected for single-transfer or demand-transfer mode. Two of the
DMA channels have an alternate address pOinter, allowing
queued buffer applications. The R4761 performs DMA arbitration
using fixed or rotating priority.
Serial Interface
A serial interface compatible with a 16450 UART is included.
The baud rate input clock can be selectively prescaled by 16,
allowing flexibility in fine-tuning the exact frequencies desired.
Baud rates from 50 to 38.5K bits per second are possible.

CPU Interface
The CPU interface connects directly to the Orion R4600/R4700
and R4650 processors. The 32-bit bus mode of the R4650 is
supported. R4000 compatible write mode and write re-issue
modes are supported. All bus arbitration functions for the system
are managed by R4761, including those involving the SX-12
device. A single interrupt to the CPU is provided from the interrupt
prioritizer. Boot-mode initialization from the EEPROM is handled
totally by R4761 , in conjunction with an external low-cost PAL,
and can be expanded for future CPU versions.

Interrupt Controller
An eight-level interrupt controller is also contained in the
R4761. Each of the four peripheral ports, plus the memory-tomemory DMA channel, UART, and internal R4761 exceptions
make up the eight levels. Two prioritization methods are available:
fixed and rotating. A single interrupt signal is provided to the
CPU.

R4762 Interface
The R4762 interface connects directly to the R4762 PCI Bridge
device. CPU access of R4762/PCI address space and R4762
access of system DRAM are supported. R4762 DMA transfers to
DRAM up to 64 bytes are supported.
Serial EEPROM Interface
The serial EEPROM interface reads the 256-bit initialization
stream from a standard 2K-byte serial EEPROM at system poweron and cold resets. An external PAL assists in the sequence,
allowing the R4761 to buffer only the first 16 bits. Once initialization is complete, the CPU can read 8- or 16-bit values from the
EEPROM.
Memory Controllers
The memory controllers in the R4761 are flexible and efficient.
The DRAM controller directly interfaces to four noninterleaved
banks or two interleaved banks, up to a maximum of 512 MBytes.
DRAM word depths up to 16M are supported, and each bank can
have a different word depth. Programmable timing parameters
control the RAS-CAS and refresh timing. Both concurrent and
staggered CAS-before-RAS refresh are supported. Sustained
zero-wait state transfers are possible with interleaving, while
non interleaved configurations use at least 1 wait state.
ROM/SRAM Controller
The ROM/SRAM controller also controls four non interleaved
banks or two interleaved banks, up to a maximum of 64 MBytes.
Word depths from 16K to 2M are allowed. Each bank can be
read-only ROM, Flash ROM, or SRAM, and each has its own
word depth and timing parameters. Interleaved banks can be
intermixed with noninterleaved banks. Interleaving allows zerowait state sustained transfers.
Peripheral Interface
A flexible peripheral interface provides four mUlti-function ports
for external devices using synchronous signal protocols. All ports
can be configured as user I/O, with edge- or level-sensitive
interrupt capability on inputs. PortO can support the R4762 device.
Three of the ports can be configured for direct memory access
(DMA), including one "smart" peripheral that can use either Intel
and Motorola bus arbitration. An internal memory-to-memory
DMA channel is also included. DMA devices can transfer to/from

6.3

2

~

r;J

Pel-to-Orion Bus Bridge

ORtoN
IDT79R4762
Product Brief

Integrated Device Technology. Inc.

FEATURES
•
•
•
•

Interrupt generation capability
On-chip DMA controller
Programmable memory mapping
Host arbiter functions on chip:
- 5 master arbitration
- Programmable fixed or round-robin priority scheme
- Host bridge parking, when there is no bus owner
- Configuration support
- Moves data between PCI and local memory
- Supports both chaining and non-chaining operation
- Scatter-gather support
• Optional byte-swap per function between PCI and local
bus
• Packaged in 208-pin QFP

• Glue-less bridge between Orion family, including
R4600, R4700, R4650, and 32-bit PCI
• Extensive use of internal buffering de-couples PCI and
local-bus latencies
- 64-byte CPU write to PCI FIFO
- 32-byte CPU read from PCI FIFO
- 128-byte local memory access FIFO
- 32-byte DMA FIFO
• Simple interface to external Orion family local-bus
memory controller
• Supports 32-bit (e.g. R4650) or 64-bit CPU bus modes
to 50MHz
• Supports 32-bit PCI to 33 MHz
• Functions for host or adapter-card PCI bridges

CPU SysAd. SysCMD, ctrl

Orion Family
CPU Interface
32· or 64·bit

DMA
Channel

CPU
Transmit
FIFO
(64 bytes)

DMA request/acknowledge
Transfer request/acknowledge

Local Bus
Controller
Interface

CPU
Receive
FIFO
(32 bytes)

PCI
Receive
FIFO
(64 bytes)

PCI
Transmit
FIFO
(64 bytes)

Configuration
Registers

Byte Swapper

PCI
Address/Data

Mailbox
Registers

PCI
Control

Functions

Config. clrl,
Bus Arbiter

FIGURE 1: R4762 BLOCK DIAGRAM

The IDT logo is a registered trademark and Orion, R4600. R4650, R4700.R3081,R3052,R3051.R3041.RISController, and RISCore are trademarks oflntegrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
© 1995 Integrated Dovico Technology. Inc.

SEPTEMBER 1995
6.4

DSC.90~5/.

JDT79R4762

PCI-TO-ORION BUS BRIDGE

DESCRIPTION:

If the local bus address maps to the PCI I/O space, as
a PCI master, the R4762 generates a PCI I/O cycle. Similarly, accesses mapped to the PCI bus configuration
space will generate configuration cycles.

The IDT79R4762 is designed to provide a simple lowcost bridge between an Orion family CPU, its local memory resources, and the PCI bus. The R4762 can be used
in systems implementing an Orion family CPU on a PCI
add-in adapter card, or in systems implementing an
Orion CPU as the host off a PC I-based system.
The R4762 is designed to mate the PCI bus effectively
with an Orion family CPU. Although PCI offers high bandwidth and relatively low latency, the Orion family offers
significantly higher bandwidth. The R4762 has been
designed to de-couple the speeds of the two buses and
incorporates a significant amount of FIFO logic to mate
the bandwidth and latency requirements of the two busses.
This product brief is intended to provide an overview of
capabilities on the R4762 PCI bridge. A block diagram of
the R4762 is included on page 1.

PCI Target Mode Operation
As a PCI target, the R4762 allows access to its internal
registers and to the Orion local bus, with the following
commands: I/O read, I/O write, memory read, memory
write, memory read multiple, memory read line, memory
write, and invalidate. The R4762 supports read or write
access of byte, word, or long-word size. Using an
address generated from an internal I/O base register, for
PCI I/O accesses, the R4762 will generate local bus
memory cycles. The R4762 can also perform target initiated terminations such as retry, disconnects, and targetabort.
PCI Configuration Support

PCllnterface Features

The R4762 includes an internal configuration space,
which meets the requirements for a host bridge. In "host
mode," the R4762 is configurable by the Orion-family
processor. In addition, the R4762 can generate configuration cycles; it supports both "type 0" and "type 1" configuration cycles, using mechanism #1. In "target mode,"
the R4762 is configurable from the PCI bus.

The R4762 is a fairly high-performance PCI interface
chip, consistent with the class of CPU being bridged to
PCI. It also supports the generation of back-to-back
cycles, to maximize PCI bandwidth. The R4762 does not
perform "address stepping" as a bus master, but the
R4762 does respond to PCI bus requests with "medium
speed DEVSEL" timing.
The R4762 PCI interface implements a pair of "mail
box" registers: one for local bus to PCI and the other for
PCI to local bus, when an agent on one side writes to the
appropriate mail box and interrupt is signalled to the
other side.
In addition, the R4762 implements a "latency timer" for
the PCI bus. If the transaction is not completed within
the time-out period, the R4762 will signal a PCI disconnect, causing the transaction to be re-tried later. After an
appropriate number of re-tries has been attempted and
the transaction remains uncompleted, an error condition
is signalled and the transaction aborted.
Since the MIPS architecture is purely memory based
(rather than memory and I/O spaces), the R4762 divides
a portion of the memory address space into the following
SUb-sections: PCI-memory, PCI-I/O, PCI-configuration,
and Internal R4762 register space. Burst accesses are
supported only to memory.

Local Bus Writes to PCI
The master transmit buffer provides a write buffer for
host writes to the CPU. This allows the CPU to issue the
write command, address, and data at maximum speed,
even though the PCI latency can be longer. The transmit
buffer is 2 cache lines deep; therefore, up to two CPU
write commands can be buffered without incurring CPU
stalls. Errors that may occur during PCI writes are
reported back to the CPU using a general interrupt.
Local Bus Reads from PCI
The R4762 implements a number of features to insure
memory coherency and to avoid deadlocks on the PCI
bus. To insure memory coherency, the R4762 processes
all pending PCI writes before processing a host read to
the PCI bus. To avoid deadlocks, if the CPU is awaiting a
read transaction across the PCI bus, the R4762 signals a
RETRY back to other PCI masters attempting to read the
CPU local memory.

PCI Master Mode Operation
As a PCI master, the R4762 can generate memory,I/O,
or configuration cycles for direct local to PCI bus
accesses. Memory read, memory write, memory read
multiple, and memory read line cycles are supported.

6.4

2

IDT79R4762

pel-TO-ORION BUS BRIDGE

Various factors dictate the architecture of the master
receive FIFO buffer of the R4762:
• The Orion family processes cache misses using subblock (burst order), while not all memory systems support
this sequence. Thus, the R4762 processes cache fill
requests as a sequential read of 8 words and picks the
data out in the correct order to return it to the CPU.
• Since the PCI bus allows mUlti-word transfers to be
broken off by the target, the R4762 implements a local
memory bi-directional FIFO capable of buffering an entire
cache line. Thus, a processor request such as a burst read
can be processed as multiple PCI reads.

The R4762 is programmed with the command location in
memory. When DMA is started, the R4762 DMAs the control block from memory, which causes the appropriate
transfers to begin. When this control block is processed,
the R4762 will DMA the next control block from memory
(the location of this next control block is a parameter in the
first block). This will continue until it completes a control
block with an "end-of-chain" flag set. The DMA controller
has its own FIFO.
To share the local and PCI bus resources with the rest of
the system, the R4762 implements a set of rules to allow
other agents to access these busses during DMA transfer.

PCI Write to Local Bus

Local Bus Controller Interface

The R4762 target write buffer is designed to buffer more
than one PCI write transaction, allowing the bus to be freed
while the actual write occurs on the CPU local bus.
To insure memory coherency, target writes are completed before PCI reads of the local bus are processed. To
insure bus efficiency, a retry is signaled to the PCI bus, in
this case, to allow the bus to be freed for other uses until
the target writes are retired.

The R4762 uses a simple interface to the Orion local bus
memory controller. Figure 1 shows a typical system implementation of an R4762-based adapter card. For a hostbased application, the processor sub-system would look
similar.

PCI Read from Local Bus
If the local bus is free, the R4762 will pre-fetch up to one
cache line from the local bus memory and save this data in
the local memory FIFO. This data is immediately provided
to the PCI bus; meanwhile, the R4762 will pre-fetch an
additional cache line and save this in the FIFO. Thus, burst
transfers larger than the cache line size (e.g. ATM cells of
48 bytes) can occur at true PCI speeds. If the read terminates before the data in the FIFO is exhausted, the data is
flushed from the FIFO.
Note that the R4762 assumes that the local bus memory
will process DMA requests using a sequential data ordering
algorithm. Although the R4762 will issue the same cache
line read command as an Orion CPU will for a cache line,
the R4762 expects data to be returned starting with the
word requested and then sequentially until the end of the
line. This is done to minimize PCI latency. Sub-block ordering would cause the R4762 to await data from the local
memory controller which the PCI bus can never use.

IDT Orion

Family
CPU
(R4600, R4700,
R4650)

IDT R4762
PCI Bridge

Local Bus
Memory
Controller
(e.g.IDTR4761)

DMA Controller

Figure 2:

PCI Adapter Card built with R4762

In addition to providing data buffering between the local
bus and the PCI bus, the R4762 includes an on-chip DMA
controller to facilitate data movement between the buses.
The R4762 DMA controller is a single-channel controller
that can perform chaining or non-chaining. Scatter-gather
capability is supported.

6.4

3

Rise DEVELOPMENT SUPPORT
PRODUCTS

II

~

g

RISC DEVELOPMENT
SUPPORT PRODUCTS

Integrated Device Technology. Inc.

INTRODUCTION

PROTOTYPING SYSTEMS

For engineers developing software and hardware products
around the IDT79R3000 and IDT79R4000 Instruction Set
Architecture (ISA), which includes the IDT79R30xx families of
RISControliers and the R4000 Orion Family. IDT offers three
software products and several prototyping and evaluation
systems. This catalog primarily focuses on products
manufactured and sold directly by Integrated Device
Technology.

Completely assembled and tested hardware systems are
available for prototyping and initial software porting. All systems include a CPU, serial 110, EPROM containing the IDTI
sim monitor, and some amount of RAM. These systems have
provision for simple addition of user-defined hardware. Units
are available which support the I DT79R30xx and I DT79 R4xxx
families.
For laser printer controllers, the IDT79S389A Reference
Platform provides a ready prototyping target for R30xx Family
laser printer controllers using PostScript Level 2 software from
Adobe.

SOFTWARE PRODUCTS
IOT/c-IDT's optimizing ANSI C-compiler. This compiler,
which uses the GNU C front end, includes full ANSI C
compatibility and highly efficient floating point emulation libraries for IDT79R30xx-based systems (without hardware
floating point) and IDT79R4650-based systems. A unique
debug control scripting language makes it easy to locate
hardware problems that occur only under rare conditions. IDTI
c includes the compiler, optimizer, assembler, linker, librarian,
C libraries, Floating Point Libraries, and symbolic debugger.
IOT/sim-IDT/sim is IDT's System Integration Manager,
used to bring up new hardware and to support the symbolic
debug in both the MIPS and IDT C compilers. IDT/sim is a
ROMabie debug kernal with extensive diagnostics built-in. It
is supplied in EPROM on all IDT prototyping boards, and is
available in source code for use with either the MIPS or IDT C
Compilers.
IOT/kit-IDT/kit, the Kernel Integration ToolKit, contains
source code and compiled versions of a complete set of
routines for initializing systems, servicing interrupts, handling
floating point exceptions, and so forth. Also included is source
code for ANSI libraries, for the Floating Point Emulation
Libraries and for transcendental functions.

7.0

THIRD PARTY DEVELOPMENT TOOLS
The increasing popularity of IDT's RISC microprocessors
has resulted in a dramatic increase in the number of third party
tools available. For information on these products, contact
your 10caiiDT sales representative.
• Real-Time Operating Systems from Lynx, Wind River,
Accelerated Technology and Integrated Systems, Inc.
• Compilers from MIPS, Green Hills, BSO Tasking, Cygnus
Support and Embedded Performance, Inc.
• VME Boards from CES, RISQ Modular Systems,
Omnibyte, Densan, Heurikon
• Device Simulation Models from Zycad, HDL, CAE
Technology and Synopsys
• Peripheral Support Circuits from Chrysalis Research,
DeskStation Technology, Galileo Technology, and
Mentor ARC, Inc.
• Page Description Language interpreters from Adobe
Systems, PCPI, Phoenix Technology, Inc. Pipeline
Associates, Inc and Rastek, Inc.
• In-Circuit Emulators from Embedded Performance, Inc.
and Topmax, Inc.
• Logic Analyzer support from Hewlett-Packard and
Tektronix

•

I

7.0

2

TABLE OF CONTENTS
PAGE
Rise DEVELOPMENT SUPPORT PRODUCTS
Third Party Development Tools and Applications Software for lOT RISC Processors .........................................
Training Class
Applications Development with lOT RISControllers and Orion Microprocessors ......
IDT79S389
Laser Printer Controller-3051 Family Reference Platform for Postscript Level 2
Software from Adobe ....................... ..................... .... ................. ......... ....... .... ............
IDT79S385A
R3051 Family Evaluation Kit .....................................................................................
lOT 79S341
R3041 Evaluation Kit .................................................................................................
IDT79S381
R3081 Evaluation Kit .................................................................................................
IDT79S460
R4600 Evaluation and Development Platform ...........................................................
IDT79S464
Orion 79R464 Evaluation Kit .....................................................................................
IDT7RS901
IDT/sim System Integration Manager ROMabie Debugging Kernel..........................
IDT7RS930
IDT/c Multihost GNU C-Compiler System .................................................................
IDT7RS909
lOT/kit Kernel Integration Toolkit ...............................................................................

7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11

II

7.0

3

~

g

THIRD-PARTY DEVELOPMENT TOOLS AND
APPLICATIONS SOFTWARE FOR IDT Rise
PROCESSORS

Integrated Device Technology. Inc.

OVERVIEW

As the MIPS architecture is increasingly popular and successful, many new tools are constantly being announced. IDT
encourages our customers to work closely with their local
sales representative for a current list of third party support.
This listing is current as of the date of this document.

The MIPS/IDT RISC Microprocessorfamily is supported by
a wide variety of third-party development tools and applications software. Many of these tools are software products,
useful across the entire line of processors; others of these are
hardware development tools, appropriate for one or two
members of the family.

Product Name
Software Development Tools
Nucleus:DBUG/DBUG+, PC
XoftWare-System Software
SDE-MIPS
R3000 Cross-Development Package
UDB-Universal Source DB
Compilers, Cross Development Sys.
Model CCE3K-SW Tools
Compilers, Development SW
IDT/c, IDT/sim
R3000/R4000 Compilers
StethoScoEe, WINDVIEW
Software Libraries
Nucleus FILE, Nucleus Net
lOT/kit (IDT79S909)
VDS Kit-Video Library
USFiles, USNet
Ada Development Tools
DACS MIPS Ada CC System
ADA Compiler
VADS-Ada System
RISCADA Development System
Real-Time Operating Systems
Nucleus Plus, Nucleus RTX
QUITOS
CHORUS CLASSIX
MULTI Debug Servers
pSOSystem/MIPS
C-Executive, PSX
AMX3000
LynxOS
MultiTask
UniPlus +
VxWorks 5.1 RTOS

Vendor

Phone
334-661-5770
619-755-1000
011-44-171-700-3301
617-320-9400
408-685-0336

FAX

Accelerated Technology
AGE Logic, Inc.
Algorithmics, Ltd.
BSO/Tasking, Inc.
CaseTools, Inc.
Cygnus Support
Embedded Performance
Green Hills Software, Inc.
lOT
MIPS Technologies, Inc.
Wind River S~stems, Inc.

408-434-2210
617-862-2002
408-492-8208
415-390-4170
510-748-4100

334-661-5788
619-755-3998
011-44-171-700-3400
617-320-9212
408-685-0312
415-903-0122
408-435-7800
617-862-2427
408-492-8469
415-390-6170
510-814-2011

Accelerated Technology
IDT
Performance Computing, Inc.
U.S. Software

334-661-5770
408-492-8208
503-641-1221
503-641-8446

334-661-5788
408-492-8469
503-641-3344
503-644-2413

DOC-I
Green Hills Software
Rational Corporation
Thompson Software Prod.

602-275-7172
617-862-2002
408-496-3600
619-457-2700

602-275-7502
617-862-2427
408-496-3636
619-452-2117

Accelerated Technology
Advanced Real Time Systems
Chorus Systems
Green Hills Software, Inc.
Integrated Systems, Inc.-lSI
JMI Software System, Inc.
Kadak Products Ltd.
Lynx Real-Time Systems
U.S. Software
Unisoft Corp.
Wind River Systems, Inc.

334-661-5770
011-33-1-64589090
408-879-4100
617-862-2002
408-980-1500
215-628-0840
604-734-2796
408-354-7770
503-641-8446
415-794-2666
510-748-4100

334-661-5788
011-33-1-64589149
408-879-4102
617-862-2427
408-980-0400
215-628-0353
604-734-8114
408-354-7085
503-644-2413
415-794-2668
510-814-2011

415~903-1400

SEPTEMBER 1995
©1995 Integrated Device Technology, Inc.

7.1

THIRD PARTY DEVELOPMENT TOOLS AND APPLICATIONS SOFTWARE

Product Name

Vendor

Phone

FAX

Logic Analyzers
ML-4400 Logic Analyzer
CLAS 4000 Logic Analyzer
PIXXXX Logic Analyzer PP
HP-16500 Logic Analysis System
DAS9200, Model 32GPX

American Arium
Biomation
Corelis
Hewlett-Packard Co.
Tektronix, Inc.

714-731-1661
408-434-2210
31 0-926-6727
800-452-4844
800-426-2200

714-731-6344
408-435-7970
31 0-404-6196

Embedded Performance, Inc.
Topmax
XLNT Designs, Inc.

408-434-2210
602-730-2530
619-487-9320

408-435-7970
602-730-2550
619-487-9768

Algorithmics Ltd.
Cogent Engineering
Creative Electronics (CES)
IDT
Integrated Real-Time Systems
Omnibyte Corporation
RISO Modular Systems
ShaBLAMM! Computer, Inc.
Siemens Nixdorf (SNI)
Vigilant Technologies, Inc.

011-44-71-700-3301
508-632-2020
011-41-022-7925745
408-492-8208
408-241-4950
708-231-6880
510-490-0732
408-730-9696
011-33-1-34819227
305-680-6759

011-44-71-700-3400
508-632-1211
011-41-022-7925748
408-492-8469
708-231-7042
510-490-7225
408-730-4940
011-33-1-34819667
305-434-9048

CAE Technology, Inc.
Chrysalis Research Corp.
HDL Systems Corp.
Synopsys Logic Modeling
Z;tcad Coreoration

408-526-9207
617-371-9115
408-522-2600
503-690-6900
201-347-7900

408-526-9308
617-371-9175
408-522-2626
503-690-6906
201-347-8525

IDT
Chrysalis
DeskStation Technology
Galileo Technology, Inc.
Mentor ARC, Inc.

800-345-7015
617-271-0943
913-599-1900
408-451-1400
510-656-0100

408-492-8674
617-275-4461
913-599-4024
408-451-1404
510-656-3246

Chrysalis Research Corp.
Embedded Performance, Inc.
IDT
IDT RISC Subsystems Div.
RISO Modular Systems, Inc.
Topmax

508-371-9115
408-434-2210
408-492-8208
408-492-5668
510-490-0732
602-730-2530

508-371-9175
408-435-7970
408-492-8469
408-988-5600
510-490-7225
602-730-2550

Adobe Systems, Inc.
lOT
PCPI
Peerless Systems Corp.
Phoenix Technologies, Ltd.
Pipeline Associates
Rastek Corporation

415-961-4400
408-492-8208
619-485-8411
310-536-0908
617-551-5030
201-267 -3840
205-882-0882

415-961-3769
408-492-8469
619-487 -5809
310-297 -3264
617-661-4802
201-267-3715
205-882-0238

413-448-8003

In-Circuit Emulators
ICEMAN 3041, SYS-R3051
TMax 5501-30xx Emulator
NetROM ROM Emulator

Evaluation Boards
P-4000i
CMA Universal Development Systems
VME Boards
Evaluation Kits
Prometheus 4600
PULSAR 3000 VME board
RISOengine Computer Boards
Nitro-VLB Booster
RISC 4XOO CPU Boards
SLOTSAVER 3000

Simulation Tools/Models
Verilog Models for R4XXX
VHDL models for R30XX
SOFT-RISC Verilog Models
Logic Modeling
Model Bank

II

Support Components
IDT R3715, R3740
RXI--RXD Chipset
LogiCore Chipset
Galileo-2, Galileo-3, ...
WINset-PCI RxOO, VL R4xOO

Consulting/Design Services
Design Services
Software Development Class
Training Class
Design, Development Mfg.
Hardware/Software Design
Consulting/Design Services

Page Description Languages
Adobe Postscript Software
IDT79S389 Reference PIt.
Postscript Porting Services
Peerless Page
Phoenix Page
PowerPage Level 2, PCL 5x
Mirroc5E-PCL Emulation

7.1

2

~

g

Integrated Device Technology. Inc.

TRAINING CLASSApplications Development with the IDT R3041 , R3051, R3052,
R3071, R3081 RISControliers and R4600, R4700 and R4650
Orion Family

OVERVIEW
lOT ofters a training class intended to provide in-depth
knowledge on the use and capabilities of the 32-bit R30xx
RISControliers and the 64-bit R4xxx Processors. The class
is intended to provide an accurate basis fordevice evaluation,
as well as to provide a design engineer with the ability to
rapidly bring an application based on lOT parts to production.
The class is intended for engineers who are designing with
the lOT processor family, and who wish to minimize time to
market. It is also appropriate for customers performing a
detailed processor survey priorto device selection. The class
covers both hardware as well as software issues.

COURSE CONTENTS
The course provides a detailed discussion, including handson workshops, on both the hardware and software considerations appropriate to applications which are either new development projects or porting projects from another architecture
to lOT's RISC architecture. While the course does assume
basic familiarity with hardware and software development,
the course does not assume previous RISC training or
experience.

The course prepares the participant to create designs around
a RISControlier from the R30xx family as well as around the
R4xxx (Orion) family, through detailed lectures and hands-on
workshops and laboratory sessions. The programming environment is reviewed, as are various hardware price-performance trade-ofts.
Major topics covered are CPU overview, pipeline scheduling,
co-processor overview, floating point accelerator overvie~,
64-bit vs. 32-bit considerations, error checking, cache architecture, memory management unit, exception processing,
compatibility issues, timing, IOTic compiler tool-chain, source
level debugger and utilities.

COURSE LOCATION AND SCHEDULE
The course is held on three consecutive days at the lOT facility
in Santa Clara, California. Directions, accommodations, and
schedule information is available from your local sales representative.

SEPTEMBER 1995
©1995 Integrated Device Technology, Inc.

7.2

TRAINING CLASS

DAY 1
MIPS Architecture Overview

DAY 2
R30xx System Interface

•
•
•
•
•
•

•
•
•
•

CPU Integer Unit
Floating Point Accelerator
System Control Co-Processor
On-chip Caches
System Interface
Lab

Operations Priority
Read Interface
Write Interface
DMA Interface

Cache Architecture

System Design Topics

•
•
•
•
•

•
•
•
•
•

Cache Architecture
Operation
Flushing
Performance
Lab

Input Clock Considerations
System Clock State Machines
Bus Turn Around
Using Ack and RdCEn
Lab

Memory Management

R4xxx System Interface

•
•
•
•

•
•
•
•
•
•

Overview
Virtual to Physical Address Translation
TLB Operation
Lab

Clock Generation
Read Interface
Write Interface
DMA Interface
System Design Topics
Lab

Exception Handling
•
•
•
•
•

Precise Exception Model
Exception Processing
Software Techniques
Exception Latency
Special Techniques

DAY 3
IDT Tool Chains
•
•
•
•
•
•
•

fI

lOT Compiler & Libraries
Important Compiler Options & Utilities
High Level Language to Assembly Interface
Getting a Prototype Running
lOT Startup Module
How to Service External Interrupt
Floating Point Emulation

Software Lab
•
•
•
•
•
•

Real/Emulation mode Floating Point
Cached/Uncached Execution
Debugging Exercises
Unaligned Data Handling Exercises
Inlining Assembly in C program
Using Cache Ops to Speed Up Program

7.2

2

g

~

Integrated Device Technology. Inc.

CENTAURUS
IDT79S389
LASER PRINTER CONTROLLER
R3051'" FAMILY REFERENCE PLATFORM FOR
PostScript" Level 2 SOFTWARE FROM ADOBE®

FEATURES

• Programmable DUART (85C30) with RS232C and AppleTalk® ports
• SCSI Controller (53C80) with one SCSI port (2 connector
locations)
• Centronics parallel input port
• Adobe reference front panel interface (based on Canon
LBP-8 MARKIIIR 6-button/LCD/LED front panel)
IDT FIFO-based Canon video interface to LBP-SXlRX
engines
• Clock, reset and interrupt generation logic
• Expansion bus connector for:
- Custom engine interfaces (600dpi, color, etc.)
- Additional I/O (Ethernet, Adobe FAX, etc.)
- Additional font ROM space
• Shipped with IDT/simTM initializatior. and monitor debug
software (PostScript EPROMs available from Adobe)
• Executes various Adobe software (provided only under
license from Adobe Systems Incorporated), including:
- Adobe's high-level and low-level monitors
- Adobe Print Architecture
- Adobe's PostScript Level 2 Interpreter

• Software-ready laser printer controller suitable for Adobe
OEMs developing PostScript Level 2 products
• IDT/Adobe demonstration platform for PostScript Level 2
software running on IDT's R3051 RISController™ family
I DT/OEM R3041 ™/R3051 /R3081 ™ based prototyping
target and reference design (25M Hz)
• Uses IDT79R3721 DRAM Controller and IDT73720 Bus
Exchangers
• Options for two-way interleaved or non-interleaved
(jumpers) DRAM memory system
Up to 16MB DRAM (four 72-pin sockets; 1MB or 4MB
SIMMs)
- 4 non-interleaved banks or 2 two-way interleaved
banks
• Options for two-way interleaved or non-interleaved
EPROM/ROM memory system
- Up to 4MB ROM (8 32-pin sockets; 1, 2 or 4Mb
EPROM/ROMs)
2 non-interleaved banks or 1 two-way interleaved
bank
• 512 bytes serial EEROM

SCSI
Parallel
Interface

R3041
R3051/52

or
R3081

.....--

-

..

Appletalk
Serial
Interface

I---

Centronics
Parallel
Interface

I--

I

I

f-

..

RS232C
Serial
Interface

•
.

.

2MB
TO
4MB
ROMI
EPROM

Video Output
to
LBP-RX
Print
Engine

Adobe
Front
Panel
Interface

2MB
TO
16MB
DRAM
(SIMMs)

I---

I
Figure 1. IOT79S389 Block Diagram

Expansion Connector
290B

drw01

~:~~~:;~;~i~n~er;r~:~~r~~~;~~~~~~~~,~~~~,~~, IDT/sim. Orion. REALB. R3041. R3051. R3052. R30Bl. R3721. R4600. RISCompiler. RISConlrolier. RISCore. RiSe Subsyslem. and RiSe Windows are
AppleTalk is a reqislered trademark of Apple Computer. Inc.; PostScript is a registered trademark of Adobe Systems

MARCH 1994
©1995 Integrated Device Technology. Inc.

7.3

DSC-9073/1

1

IOT79S389 R3051 Family Laser Printer Controller Reference Platform

INTRODUCTION

The IDT79S389 Reference Platform is designed around
the R3051 RISControlier family, including the IDT79R3081
and the R3041. All devices in the R3051 family are pin- and
software-compatible. As a consequence, R3041 , R3051 E,
R3052, R3052E, R3081 and R3081 E can be substituted for
the R3051 throughout this manual. For details on the R3051
family refer to the data sheets and hardware user manuals.

The IDT79S389 provides an R3051 family laser printer
controller reference platform for rapid adaptation into OEM
differentiated products using PostScript Level 2 software from
Adobe. "Reference platform" means that IDT and Adobe
engineers have jointly developed both hardware and software
modules for the specified configuration. This provides a
baseline hardware and software design to accelerate time-tomarket where changes can be limited to one or two areas
(form factor, engine interlace or I/O options), without having to
start at the beginning.
Since the IDT R3051 family includes pin-compatible members with and without floating point accelerator hardware on
chip, Adobe software licensees will be able to obtain "core
PostScript" binaries in two versions: one compiled with the
MIPS C-compiler assuming the presence of the FPA (for
IDT79R3081), and another version based on IDT's floating
point emulation libraries (for IDT79R3041 , R3051 and R3052).
The IDT79S389 is completely self contained, and is intended
for use either on the desktop, or installed inside a variety of
Canon print engines; e.g. Canon OEM engines LBP-SX and
LBP-RX, Canon LBP-8 MARKIlIR and HP LaserJet III. The
IDT79S389 fits into any of the above engine mounting locations, including the standard power supply and video interlace
connections. For evaluation on the desktop, a PC-style 4-pin
power supply connector is also provided. Figure 1 illustrates
the simplified block diagram of the IDT79S389 Reference
Platform.

SYSTEM OVERVIEW
Figure 2 illustrates a high-level schematic of the data paths
and various subsystems of the board. The user's manual that
ships with the board provides extensive detail on the board,
including complete schematics, PAL equations, and theory of
operation.

Address and Data Path
The R3051 family uses a time multiplexed address and
data bus. The IDT79S389 demultiplexes this bus into an
address bus and two data buses. The use of two data buses
both minimizes the loading of the buses, and allows either or
both of the EPROM and DRAM subsystems to be interleaved.
The address path is constructed using IDT 74FCT162373
16-bit wide transparent latches, and is de-multiplexed off the
ND bus using the processor supplied ALE output signal.
The data paths are provided by a pair of IDT 73720 Bus
Exchangers. The 73720 in general is a 3-port, 16-bit wide
transceiver, used to multiplex a common CPU port between
two data ports (typically found in two way interleaved sys-

R3041
R3051/52

or
R3081

fI

CPU AID BUS

X PORT
BUS EXCHANGER
ZPORT

YPORT

VIDEO FIFO
AND
VIDEO INTERFACE

EVEN DATA BUS

DRAM
BANKSO&2

2908 dwg 02

Figure 2. 10T79S389 High Level Schematics

7.3

2

IDT795389 R3051 Family Laser Printer Controller Reference Platform

1MB SIMM
non-interleaved

1MB SIMM
interleaved

4MB SIMM
non-interleaved

4MB SIMM
interleaved

Bank 0

OX0080_0000->
Ox008F FFFF

Ox0080_0000->
Ox009F FFFF (even)

OX0080_0000->
OxOOBF FFFF

OX0080_0000 ->
OxOOFF FFFF (even)

Bank 1

Ox0090_0000->
Ox009F FFFF

Ox0080_0000 ->
Ox009F FFFF(odd)

OXOOCO_OOOO ->
OxOOFF FFFF

Ox0080_0000->
OxOOFF FFFF (odd)

Bank 2

OxOOAO_OOOO->
OxOOAF FFFF

OxOOAO_OOOO ->
OxOOAF FFFF (even)

Ox0100_0000->
Ox013F FFFF

Ox0100_0000->
Ox017F FFFF (even)

Bank 3

OxOOBO_OOOO ->
OxOOBF FFFF

OxOOAO_OOOO->
OxOOAF FFFF (odd)

Ox0140_0000->
Ox017F FFFF

Ox0100_0000->
Ox017F FFFF (odd)

Table 1. DRAM Memory Map

tems). The control of the 73720 Bus Exchangers is performed
by a dedicated PAL, which directs transfers between the CPU
and the appropriate data bus, and insures that bus conflicts
are avoided.
State Machines
The IDT79S389 uses a distributed state machine structure
to implement control of the various peripheral subsystems. In
this structure, each peripheral subsystem has dedicated control
PALs associated with it. These PALs monitor the start of a
transaction, and either ignore the transaction (if intended for
other subsystems), or provide the appropriate control
responses back to the processor at the appropriate times,
according to the latency of the targeted subsystem. A master
PAL generates a common "Cycle End" indicator to all state
machines, indicating that they can await another transaction.
The advantage of this distributed state machine structure is
that memory subsystems can be independently added,
removed, ormodified, without impacting the rest of the system.
This simplifies end user customizing and system debug.
The disadvantage of this structure is that the number of
PALs required is larger than if the state machines were
centralized. It is expected that customers using this as a
reference design would customize and/or cost reduce the
state machines and I/O subsystems, using interface ASICs,
ASSPs, or condensed PALs.
In addition to the distributed state machines, the IDT79S389
contains a number of PALs providing common functions to all
state machines. These functions include address decoding,
Cycle End generation, data path steering logic, bus timeout,
and CPU inpu~response synchronization.

DRAM Subsystem
The DRAM subsystem of the IDT79S389 board supports
the use of 256K x 32 or 1M x 32 72-pin SIMM memories. Up
to 4 SIMMs may be used, for a maximum of 16MB of DRAM
memory. The memory can be interleaved or non-interleaved,
according to a set of DIP switches.
The DRAM system is controlled by the IDT79R3721 DRAM
controller. This device features an R3051 family bus interface,
and implements direct control of the DRAM devices. The
timing and configuration of the DRAMs is programmable in the
R3721 , according to the settings of an internal mode register.
To maximize user flexibility without requiring PROM
changes, the IDT79S389 memory maps a set of DIP switches,
called the MSEL switches. At system startup, the value of
these switches is read by the CPU and then written to the
IDT79R3721 DRAM controller, to configure the system timing
model. Thus, in order to change the memory configuration or
timing, the user merely needs to set the DIP switches and
reset the board.
The DRAM memory is memory mapped to the address
space Ox0080_0000 to Ox017F_FFFF, depending on the size
of SIMM, number of SIMMs, and interleaving chosen. Table
1 illustrates the address map, depending on configuration.
Table 2 illustrates the read and write latency (measured in
clock cycles) of the various memory configurations, assuming
80ns SIMMs and a 25M Hz system.

First Word of Read
Adjacent words

CPU Subsystem
The IDT79S389 board incorporates the standard R3051
family PLCC footprint. It is targeted to run at 25MHz, although
its frequency may be scaled up or down, as appropriate. Note
that when scaling frequency, the user should reprogram the
wait states associated with the various memory and peripheral
subsystems, and may need or choose to use faster or slower
control and memory devices. The board and software do not
require the use of a TLB.

Non-page Write
Page Write

Interleaved

Non-Interleaved

5
1
4
3

5
2
4
3

Table 2. Number of Clock Cycles for Various DRAM Transfers

The IDT79S389 board is shipped with two 1 MB 80ns
SIMMs in a non-interleaved configuration. Additional SIMMs
can be added by the user, and interleaving can easily be
selected.

7.3

3

IDT79S389 R3051 Family Laser Printer Controller Reference Platform

1Mb EPROM
BankO

Ox1 FCO_OOOO ->

(non-Interleaved)
Bank 1

2Mb EPROM

4Mb EPROM

Ox1 FCO_OOOO ->

Ox1 FCO_OOOO ->

Ox1 FC7_FFFF

Ox1 FCF_FFFF

Ox1 FDF_FFFF

Ox1 FC8_0000 ->

ox1 FDO_OOOO ->

Ox1 FEO_OOOO ->

(non-interleaved)

Ox1 FCF_FFFF

Ox1 FDF _FFFF

Ox1 FFF_FFFF

Bank
(Interleaved)

Ox1 FCO_OOOO ->

Ox1 FCO_OOOO ->

Ox1 FCO_OOOO ->

Ox1 FCF FFFF (even)

Ox1 FDF FFFF (even)

Ox1 FFF FFFF (even)

Bank 1

Ox1 FCO_OOOO ->

Ox1 FCO_OOOO ->

Ox1 FCO_OOOO ->

(interleaved)

Ox1 FCF FFFF (odd)

Ox1FDF FFFF (odd)

Ox1FFF FFFF(odd)

°

Table 3. EPROM Address Map

EPROM Subsystem
The EPROM subsystem contains 8 sockets, capable of
accepting 1Mb, 2Mb, or 4Mb devices. The sockets accept 8bit wide EPROMs in the OIP package.
The board can be used with either 4 or 8 EPROM devices;
if 8 devices are used, Interleaved or non-interleaved operation
can be selected. The density of EPROM, and the interleaving
factor, are selected via jumpers and PALs for the board. The
board ships with 512KB of 120ns EPROM installed in a single
bank; the EPROMs contain the IDT/sim monitor program
ported to this board.
The EPROMs reside in the physical address range
Ox1 FCO_OOOO through Ox1 FFF_FFFF. This address space
includes the system exception vectors, as well as the bootup
code, and can be accessed either through or around the onchip processor cache, according to the virtual address used.
Table 3 shows the physical address map for the EPROMs.
Table 4 shows the memory latency of the EPROM subsystem,
for 120ns EPROMs and a 25M Hz system.

The serial channels are implemented using a single 85C30
SCC serial controller. The address space forthe serial controller is Ox0073_0000 through OX0073_FFFF.
EEROM Interface
The 10T79S389 board includes a 512B EEROM to store
various configuration data. The EEROM is accessed by the
65C22 VIA device, which is memory mapped to Ox0071_0000
through Ox0071_FFFF.
Centronics Interface
The board also includes a unidirectional Centronics port.
Centronics data is read from address space Ox0075_0000
through Ox0075_FFFF; Centronics status is written in the
address space Ox0076_0000 through OX0076_FFFF.
Front Panel Interface
The front panel interface corresponds to a Canon LBP-8
Mark IIIR, and uses a series of switches, LEOs, and LCOs to
implement front panel control. Front panel is accessed by the
65C22 VIA device, which is memory mapped to Ox0071_0000
through Ox0071_FFFF.

SCSI Subsystem
The IOT79S389 board contains a single SCSI channel,
implemented using the 53C80 SCSI controller. Although there
is only one channel, there are two SCSI connectors on the
board,' to support the differences in the form factor of the
various laser engines supported.
The SCSI device resides in the address range Ox0074_0000
through Ox0074_FFFF.

Video Interface
The video interface corresponds to the interface requires
for the Canon LBP-8 Mark IIIR, based on the Canon LBP-RX
print engine. The video interface is implemented using discrete
logic, with status taken from the 65C22.
Video data is sent to the video interface by performing an
aliased read of the ORAM memory. If a processor read of the
16MB region starting at Ox0880_0000 is detected, the access
will be processed as a ORAM read. However, the read data
returned from the ORAM will be captured by the video interface,
and later shifted out to the print engine. This technique
eliminates overhead by not requiring the processor to explicitly
write the data to the video channel.

Serial Channels Subsystem
The IOT79S389 board implements two serial channels.
One is a traditional RS-232 channel, and is accessed by a OB25 connector. The other channel supports AppleTalk, and
uses the standard AppleTalk connector. The board includes
voltage translators and transceivers to implement the electrical protocols required by these standards.

Interleaved

User Expansion Area
In addition to the memory systems described above, the
IOT79S389 board contains a user expansion connector. The
user expansion connector allows users to add custom features
to the board for software development. Features which could
be added might include an Ethernet channel, additional font
ROM, or a different engine and front panel interface.
The I0T79S389 board provides a User Chip Select, mapped
to address Ox0078_0000 through OX0078_FFFF, for use with
the expansion connector.

Non-Interleaved

First Word of Read

5

5

Adjacent words

4

1.6 (1-3-1)

Table 4. Number of Clock Cycles for Various EPROM Transfers

7.3

4

fI

I

10T79S389 R3051 F=amlly Laser Printer Controller Reference Platform

Board Form Factor
The form factor and hole placement of the board allows.it
to be directly mounted into either a Canon LBP-8 Mark IIIR
laser printer, the HP LaserJet III, or the Canon OEM print
engines LBP-SX or LBP-RX engines. The placement of the
video, front panel, and power connectors, are compatible with
these form factors.
In addition, the board can be run on a benchtop using a
standard PC compatible power supply. If the board is used in
this fashion to drive an engine, it is recommended that a
common ground between the board and the engine be provided.

SPECIFICATION SUMMARY
Order Number:

Maximum on board memory capacity:
DRAM
Four 72-pin SIMM sockets for
256K x 32 or 1M x 32 (1 to 16MB)
EPROM
Eight 32-pin sockets for 128K x 8
to 512K x 8 (to 4MB)
Serial EEROM
One 8-pin socket for serial
EEROM (512bytes)
Debug Monitor EPROM:
IDT/sim Version 4.0 ported to
IDT79S389

Summary: Address Map and Interrupt Assignment
Table 5 is a summary of the address map of the I DT79S389
board. Table 6 shows the interrupt assignments of the CPU.

Memory Subsystem

Start Address

End Address

VIA

OX0071_0000

Ox0071_FFFF

SCC

Ox0073 0000

Ox0073_FFFF

SCSI

OX0074_0000

Ox0074_FFFF

Centronics Data

Ox0075 0000

Ox0075_FFFF

Centronics Status

Ox0076_0000

Ox0076_FFFF

User Chip Select

Ox0078 0000

Ox0078_FFFF

MSEL Switches

OX0079_0000

Ox0079_FFFF

R3721 Mode Register

Ox007A 0000

Ox007A_FFFF

DRAM

OX0080_0000

Ox017F_FFFF

Aliased Video DRAM

Ox0880 0000

Ox097F_FFFF

EPROM

Ox1 FCO_OOOO

Ox1 FFF_FFFF

Serial Ports:
Serial

Appletalk

Parallel port:
Centronics

Table 5. 10T79S389 Memory Map Summary

Device

IDT79S389

Controlled by 85C30 DUART.
CRT terminal connector or for
downloading J3 (25-pin AMP
748133-1 ,DB25S, right angle
female).
AppleTalk connector J2 (8-pin
AMP 749179-1, D8 8, right angle
female).
36-pin, female, right angle,
standard Centronics para"el
connector (R.Nugent RPMC36SB-SR-TG).

SCSI port:

Controlled by 53C80 SCSI
controller. SCSI connector J5 or
J10 (50-pin, female, right angle,
(R.Nugent RPM-C50SB-SR-TG).

Video:

Standard 20-pin, male Canon
LBP-RX video interface
connector (HIROSE PCN-10-20P
2.54DSA).

Front Panel:

J7, 34-pin male, right angle
connector (AMP 1-103149-7).

Expansion:

Four 40-pin male, four wall
headers, J11-14
(MOLEX 39-26-7404).

Physical:

Compatible with Canon RX, SX
engine form factors.

Operating Temp:

Q-50Q C.

Power Supply:

5.0V ± 5%,3 Amps typical
(estimate).

CPU Interrupt

Reserved

Int(O)

R3081 Floating Point

Int(1)

VIA

Int(2)

HFullNideo Reset

Int(3)

SCSI

Int(4)

SCC

Int(5)

Table 6. 10T79S389 Interrupt Assignment

U

5

1DT795389 R3051 Family Laser Printer Controller Reference Platform

PHYSICAL LAYOUT

3.

Advanced hardware starting point for rapid evaluation,
cost-performance point analysis and development of
OEM finished products.

4.

Advanced software-ready controller, suitable for
immediate development with PostScript Level 2
software from Adobe, and adaptation to other print
engines and communications ports (Adobe software
available only under license from Adobe Systems
Incorporated).

The physical layout of the IDT79S389 Reference Platform
reflects the board's primary objectives:
1.

Software delivery vehicle for PostScript Level 2
software from Adobe
- Memory space appropriate for PostScript Level 2
software typical implementations,
- Various memory configurations (interleaved
vs non-interleaved, code running out of DRAM or
out of ROM) to easily evaluate cost and performance
alternatives.

2.

Cost-Effective design model for IDT79R3051
RISController family
- NO zero-wait-state memory,
- Minimum complexity board configuration (6 layers),
- Fits industry standard Canon LBP-RX print engine.

SCSI Connector Locations

>0.

0..
:J

CfJ

iii

:::

II

o

0...

o

0...

Front Panel Interface

Canon RX Engine Interface

Appletalk
2908 dwg 03

Figure 3. IDT795389 Board Layout

7.3

6

IDT79S389 R3051 Family Laser Printer Controller Reference Platform

ORDERING INFORMATION
Each unit is shipped with complete schematics and PAL equations. A user's guide includes instructions on downloading
code, operating the Software Integration Manager, and providing the correct timing interfaces to additional hardware. Boards
are shipped with the R3081 CPU plugged in, but samples of the R3052 and R3041 are provided. The R3051 can also be ordered
to allow user upgrades.

Evaluation Boards
R3041
R3051
R3081
R4600

Evaluation
Evaluation
Evaluation
Evaluation

Kit
Kit
Kit
Kit

20
25
33
50

MHz
MHz
MHz
MHz

System Board ............................................................................... .
System Board ............................................................................... .
System Board with Ethernet.. ....................................................... .
to 75 MHz System Board with Ethernet ....................................... .

7.3

79S341
79S385A
79S381
79S460

7

G®

R3051™ FAMILY
EVALUATION KIT

IDT79S385A

Integrated Device Technology, Inc.

FEATURES:
• Complete 25MHz RISC System Board
- Requires only 5V supply and terminal to operate
- Supports R3041 1M, R3051, R3052™, R3071 'M or
R3081™ highly integrated RISC CPUs
- Board contains an IDT79R3052E
- 1MB of non-interleaved DRAM, expandable to 4MB
- 128KB of EPROM, expandable to 2MB
- Serial and Parallel Ports
- Connectors provided for easy connection to HP Logic
Analyzer
- Wire-wrap area on the board
• IDT/c™ for IBM PC compatibles included in kit
- Hardware or software floating point
- Remote symbolic debug
• lOT's System Integration Manager (IDT/simTM) included in
EPROM
- High capability debug monitor
- Simplifies software development

• Complete set of documentation included
- Supplied with complete set of board schematics
PAL equations supplied on IBM PC 3.5" disks
- User's manuals for R3051 family, IDT/sim, and IDT/c
• Utility programs also included
- Program utility disk
- HP16500A Logic Analyzer disassembly software
• R3081 sample also included for board upgrade

DESCRIPTION:
The IDT79S385A Evaluation Kit is a complete kit for
evaluating the R3051 hardware and software environment.
The kit contains a working system, including all schematics
and theory of operation, an R3081 sample to allow the user
to upgrade the system capabilities, and a complete software
development environment, including debug monitor and "G"
compiler/assembler toolchain. Finally, the kit is complemented by documentation, logic analyzer software, and
utility programs.

II

IDT79S385 Rise System Board. Actual Size 8.5" x 11"
The lOT logo Is a registered trademark and R3051. R3041. and R30Bl are trademarks of Integrated Device Technology. Inc.

SEPTEMBER 1995
©1995 Integrated Dovice Technology, Inc.

7.4

DSC-9063/S

1

IDT79S385A
RISC EVALUATION KIT FOR R3051 FAMILY

PRODUCT BRIEF

COMPLETE SINGLE BOARD COMPUTER

load of software. A set of expansion connectors permits
external hardware to be connected to the board, and a wirewrap area on the board can be used to build additional
hardware without using a second board.
The board is designed to be placed on a flat table-top
surface. Standoffs are provided for physical support.
The 3051 Bus, along with other control signals, is connected to a set of pins in the center of the board next to the
wire wrap area. These signals can be used to connect
additional hardware on either the wire-wrap area or on
another board via a ribbon cable. OMA control is provided.
Table 1 shows the signal description for the expansion
connector.

The 79S385 board is a complete working RISC system
intended as a complete design example using the R3051
family of highly integrated RISC CPUs. The board requires
only a simple CRT terminal and a 5V power supply for
operation. Figure 2 shows a block diagram of the79S385
board.
The board is designed around lOT's R3051 family of
highly integrated RISC CPUs. An R3052E CPU chip (8KB 1cache and 2KB O-cache, with on-chip TLB) is included in a
socket, but any member of the family can be substituted.
The 79S385A kit includes a sample of a 25MHz R3081 in a
PGA pinout, to allow the user to upgrade the system. A large
wire-wrap area is available on the board for adding additional hardware. All the schematics and details of the designs are supplied with the board, including all PAL equations on an IBM format 3.5" disk.
The 79S385 board is supplied with 1MB of DRAM in
socketed 256K x 4 ZIPs; the ZIPs can be replaced with 4MB
devices to obtain 4MB of DRAM on the board (an applications brief on upgrading memory is included in the kit). Other
hardware on board includes a 2681 OUART and an 8254
counter/timer; both these devices are supported with drivers
in IOT/sim. A parallel Centronics port is available for higher
speed download of code into the board.
The board contains 128KB of EPROM expandable to
2MB by replacing the EPROMs with higher density devices.
The EPROMs contain lOT's powerful System Integration
Manager (IOT/sim), a debugging monitor that supports
download of code from host systems, execution control
commands, memory probing, and 1/0.
There are two serial ports, a free-running programmable
timer, and a parallel Centronics port for high-speed downSignal Name

IOT/SIM DEBUG MONITOR SOFTWARE
lOT's System Integration Manager (IOT/sim) is included
in EPROMs on the board. This software permits downloading of code from a host system, execution control with
breakpoints, in-line assembly and disassembly, and a variety of commands to control main memory, cache memory,
and the internal TLB. It provides all the resources needed to
bring up new hardware and software.
The evaluation kit also includes a complete set of user
documentation for the IOTlsim software too/. The capabilities of IOTlsim are described in a separate data sheet.

IOT/C IIC II COMPILER FOR IBM PC COMPATIBLES
In addition, the evaluation kit contains a complete copy of
the IOTlc software development toolchain, hosted on IBM
PC compatible computers. I OTic, described in a separate
data sheet, includes:
• The ability to generate big- or little-endian code

Description

10rO

EAOO-EA31

I/O

32-bit buffered address bus

EDOO-ED31

I/O

32-bit buffered data bus

SYSOUT

0

Buffered SYSCLK Clock from CPU; used to synchronize data transfers

MRES#

0

Copy of the Reset signal to the CPU

MREQ

0

Memory Request output (handshaking signal for data transfers)

EXACK#

I

Acknowledge input (handshaking for data transfers)

IP4-IP5

I

Auxiliary input pin to the 2681 UART

WEA-WED

0

Write Enables for the four bytes of the data word

UCS

0

Chip select signal decoded from the high order address bits for external hardware

INTO:INT5

I

Interrupt inputs to the R3052

RD#

0

Memory Read output signal from the 3052

WR#

0

Memory Write output signal from the 3052

BREQ#

I

Bus Request input to the 3052

BUSGNT#

0

Bus Grant output from the 3052
Table 1. Signals Supplied on Expansion Connector

7.4

2885 tbl 01

2

IDT79S385A
RISC EVALUATION KIT FOR R3051 FAMILY

PRODUCT BRIEF

End·lanness

INT[5:0]

......

Reset
Control
Logic

/

Tristate

~

Data_Blk_Refill_Size

-

BR·
BG·

..
..
..

Read
Write

Read
Write
Control
Logic

Ack

""-

RCEN

~
ALE

four To
50-pin {
Connectors

Control
Address
Data

.....
....
....

I

--.

~

4

1

I

32
Address

Address
Latch

Data
Buffer

..

..

CS_device

Serial
Ports

2681
UART

r-...

...

....V21
32

~~
CJ)
a:

'J

r-...
C\J

C')

C\J

~~

-

'J

Centronics
Input
Port

32
I ..

Address
Decoder

...
.....

~
.....

~

1
I

Data

8254

..
--

21
I

I

..

8

~ Timer

... Centronics_lnt

Timing
Control
Logic

LE

Control··

... UART_lnt.

Interrupt
Control
Logic

DACKI EXACK

R3051

-

TimeUnt

~

BE[3:0]

AD[31:0]

+
Sv

~

rL~
~

EPROM

19

Parallel
Port

1

I
32

--

Row/
.... Column
Addr
Mux

..

po

....

po

.......

I~

DRAM
2885 drw 01

II

•• These control signals include R3051 and the on-board control logic signals as well.

Figure 2. IDTI9S385 Board Block Diagram

KIT CONTENTS

Hardware or software floating point support
"C" library support, including source libraries
Remote symbolic debug

LOGIC ANALYZER INTERFACE
The 79S385A evaluation kit also includes the ability to
simply use an HP16500A logic analyzer for execution trace
and software debug. The board includes a set of connectors
to easily allow connection of the logic analyzer to the board.
Also included is a disk for the HP16500 containing disassembly software, allowing the analyzer to display a disassembled listing of the software executing on the system.

KIT SUMMARY
The IDT 79S385A evaluation kit is a complete low-cost
package for evaluation of the R3051 family, especially its
software environment. The kit allows the user to develop
and execute high-level language programs, to look at a
software development toolchain for the IDT R3051 family,
and to evaluate a hardware design around the R3051 family.

7.4

IDT79S385 RISC Evaluation Board
IDT/c Multi-Host compiler toolchain
IDT/sim debug monitor included in board EPROMs.
User's Manuals for:
• IDT79S385 board
• R3051
• R3081
• IDT/sim
• IDT/c
Applications Guide for R3051 family
Program Utility Disk
Disassembler for HP16500 Logic Analyzer
PAL Equations on IBM PC compatible 3.5" disk format

3

IDT79S385A
RISC EVALUATION KIT FOR R3051 FAMILY

PRODUCT BRIEF

Interrupts
6 User Interrupts, three synchronized with SYSCLK

BOARD SPECIFICATIONS
CPU
25MHz R3052E on board
25MHz R3081 sample included

1/0 characteristics
TTL levels from FCT logic devices, PALs and R3052

Cache Ram
8KB I-cache, 2KB D-cache (in 3052 chip)
16KB I-Cache, 4KB D-Cache configurable to
8KB I-Cache, 8KB-DCache (in R3081 chip)

Power Supply
2 amps (typical) at 5V, 25°C, at rated speed
Environmental Conditions
Ambient temperature O°C to +50°C
Relative Humidity 5% to 95%

Cacheable Address Space
4GB

Clock Frequency
25MHz

DMA Support
Bi-directional tri-stateable buffers can be used to
write to DRAM from external logic

Interconnection
Five 50-pin connectors, containing Address, Data, and
Control signals and R3052 signals
Five 20-pin plugs for use with HP logic analyzer
Two RS-232 serial ports on DB-25 connectors
One parallel Centronics port for input

Block Refill
4 word instruction block size
1 or 4 word data block size programmable via jumper
Endianness (Byte Ordering)
User programmable via jumper

User Selectable Options
Endianness, data block refill size
Tri-State mode of 3052

ReadlWrite Buffers
Both are 4 words deep (inside R3052 chip)

ORDERING INFORMATION
Each unit is shipped with complete schematics and PAL equations. A user's manual includes instructions on
downloading code, operating the Software Integration Manager, and providing the correct timing interfaces to additional
hardware. Boards are shipped with the R3052E CPU plugged in, but any member of the 3051 family can be used. An
additional sample of the R3081 is included to allow user upgrades.

Evaluation Boards
R3051 Family Evaluation Kit ......................................................................................................................795385A

EPROM Upgrades
The following part numbers update the evaluation board hardware to the latest version of the IDT/sim
monitor.
Evaluation boards ...............................................................................................................................7R5901 BGP
Use with 79S385 only

7.4

4

(;)

R3041™ EVALUATION KIT

IDT79S341

Integrated Device Technology, Inc.

FEATURES:
- Complete low-cost 20MHz RISC system
- Plug-in AT-style card or stand alone mode
- Supports the R3041 'M highly-integrated, low-cost
RISController'M CPU
- DRAM/memory controller logic implemented with a
single low-cost PLA chip
- Capability to test different hardware wait-state and
clocking options
-128KBytes of boot EPROM expandable to 512KB
- 1MByte DRAM expandable to 4MB
- 8/16/32-bit wide DRAM array
- Two Serial Ports
- 16-bit external Counter/Timer
- PC ISA interface logic
- Connector provided for easy connection to a logic
analyzer

- lOT's System Integration Manager (IDT/simTM) included in
EPROM
- On-board debug monitor
- Simplifies software development
-lOT's PCI016 Terminal Emulation Program (IDT/pci016™)
included in kit
- Allows communication and downloading between the
board and PC
- Complete set of documentation included
- User's Manual for R3041 Evaluation board
- Installation and operation guide for standalone
and PC configurations
- DeSign and theory of operation documentation
- Includes complete set of board schematics and PLA
equations
- User's Manual for R3041 , IDT/c, and IDT/sim
- Application Guide for the R3051 Family

- IDT/c™ for PC included in kit:
- Software floating point emulation
- Remote symbolic debug

FUNCTIONAL BLOCK DIAGRAM

I

II

Figure 1. R3041 System Evaluation Board. Actual Size 4.2" x 10.0"
The IDT logo is a registered trademark and IDT/c,lDTenvY,lDT/sae,lDT/sim,lDT/ux, R3041, R3051, R3052, R3081, R3721, R4600, RISCompiler, RISControlier, RISCore, RISC Subsystem, and
RISC Windows aro Irademarks of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
©1995lnlegraled Dovlco Technology, Inc.

SEPTEMBER 1995
7.5

DSC-907611

1

IDT79S34FM EVALUATION KIT

DESCRIPTION
The I DT79S341 Evaluation Kit is a complete kit for evaluating the R3041 hardware and software environment. The kit
contains a working system, including a User's Manual with
installation guide, schematics, PLA equations, theory of operation, and design notes. A complete software development
environment, including debug monitor and "C" compiler/assembler toolchain for the PC is included. The kit also includes
the R3041 User's Manual and the R3051 Family Applications
Guide.

COMPLETE SINGLE BOARD COMPUTER
The 79S341 Evaluation Board is an example of a complete
working MIPS R3000-based RISC System. The board is a
low-cost and parts-count design example using the highly
integrated R3041 RISControlier CPU. Primary uses of the
board include:
1. Evaluating the R3041 architecture.
2. Prototyping and running software.
The board is highly configurable and contains hardware
options for state machine experiments as well as for setting
different DRAM sizes, speeds and 32/16/8-bit memory widths.
The 79S341 Evaluation Board is designed around the
IDi79R3041 RISControlier. The R3041 is a highly integrated
low-cost version of the R3051 family of RISControliers and
includes 2KB of on chip instruction and 512B of on chip data
cache. The R3041 also contains memory controller support
circuitry including programmable bus width, a refresh timer,
read and write strobes, and address multiplexer controls.
Thus on the S341 board, the DRAM controller, memory
controller, and I/O controller are implemented externally within
a single low-cost 24-pin PLA.
Although the R3041 can run in an R3051 family buscompatible mode, on the 79S341 Evaluation Board, specific
superset bus features of the R3041 are taken advantage of;
for instance the 8-bit boot PROM capability, to reduce chip
count and cost. Other boards, such as the IDT79S385A
R3051 evaluation board kit, as described in a separate data
sheet, can be used to demonstrate the R3041 using its R3051
bus-compatible mode.
The 79S341 Evaluation Board can be operated in one of
two ways. In the default configuration as a standalone board,
the 79S341 board requires only a standard RS232-C CRT
video terminal and a 5V power supply for operation. The board
can be placed on a flat table-top surface by using the remov-

COMMERCIAL TEMPERATURE RANGES

able standoffs which are provided for physical support. The
standoffs can be removed for the alternate configuration as a
PC/AT ISA backplane add-in board. In this second configuration, the 79S341 Board only requires a PC/AT compatible
personal computer. Using the IDT/pci016 PC/AT software
program included in the kit provides a terminal emulator and
downloader directly over the PC/AT backplane.
The 79S341 board contains a single 128K x 8 EPROM and
can be upgraded to a user supplied 256K x 8 or 512K x 8
EPROM. Main memory consists of eight 256K x 4 (1 Mb)
DRAM ZIPs. There are two serial ports, one external timer in
addition to the internal timer on the R3041 , and a PC/AT
backplane 16-bit I/O interface for downloading software. A
logic analyzer connector permits external observation and
evaluation of key CPU signals.
The boot EPROM contains IDT's System Integration Manager (IDT/sim), a debug monitor kernel that supports download of code from host systems, remote debug interface,
execution control commands including single stepping and
instruction tracing, memory probing, register probing, linebased assembly, and disassembly of code.
The board supports the use of 32/16/8-bitwide DRAM array
configurations through the use of hardware jumper options.
The board can be populated with either the default 1Mb DRAM
ZIPs or with user supplied 4Mb DRAM ZIPs. Thus the board
supports anywhere from 256KB to 4MB of main memory.
An IDT MacStation, SPARCstation, (or PC/AT) can be
connected to the 79S341 via one of the serial ports and user
developed code (generated using a cross-compiler such -as
GNU-C, MIPS-C, or the IDT/c compiler) can be downloaded
to the board. In the add-in board mode, the 79S341 can be
installed on the backplane of a PC/AT personal computer.
Development can done completely from the PC/AT or downloads can be transferred from a workstation to the PC (via user
supplied ethernet) and then through the PC/AT backplane of
the 79S341. When used on the PC/AT backplane, additional
server software which runs under MS-DOS is included, which
allows CRT video emUlation and program downloading via the
PC/AT ISA backplane.
In addition, a logic analyzer connector is provided allowing
additional hardware observability.
The 79S341 is constructed using through-hole devices on
a 4-layer 4.2" x 10.0" PC/AT form factor compatible epoxy
laminate board with standoffs and is intended either as a
standalone bench top device or as a backplane add-in card.

7.5

2

IDT79S341'M EVALUATION KIT

COMMERCIAL TEMPERATURE RANGES

AID Bus, Byte Enables OutpuVWrite Enables

1

1
R3041
RISControlier

I

R3041
IAcknowledae

IRESETI INITIALIZATION
PULLUPS
139.5,7705
I
CLOCK OSC and
BUFFER OSC,240

I

DRAM ADDRESS
MULTIPLEXER AND
MEMORY LATCHES

DUARTI
LEVEL SHIFTERI
RS232 CONNECTORS

I-.t-

1M X 32 DRAM
BANK

3 x 841
ADDRESS

T

DECODER5~1t

139.5
I
~
MEMORY
CONTROLLER 20R8

XSTAL,2681 ,235

128K X 8 EPROM

8x514256
Latched AddresslBus
RAS, CAS
I

PC/AT INTERFACE
CONTROLLER 521,
20R4

PC/AT REGISTERS

1--1

27C010
I

2X65J-

Figure 2. 795341 Board Block Diagram

KIT SUMMARY

IDTIC MULTI-HOSTED C-COMPILER

The IOT79S341 evaluation kit is a complete, low-cost
package for evaluation of the R3041 RISController and its
software environment. The kit allows users to develop and
execute high-level language "G" programs, to look at a software development toolchain forthe lOT R3051 family, and to
evaluate a low-cost hardware design using the R3041
RISController.

The evaluation kit contains a complete copy of the 10T/c
software development toolchain, hosted on IBM PC-386/486
compatible computers and SUN SparcStation. IOTic, described in a separate data sheet, includes:
• ANSI-C optimizing compiler, assembler, linker, and
librarian
• ANSI-C library support (source libraries available
separately)
• Supports multiple memory segments for embedded
system code
• Software floating pOint support
• Remote symbolic debug

KIT CONTENTS

IDTISIM DEBUG MONITOR SOFTWARE
lOT's System Integration Manager (IOT/sim) is included in
an EPROM on the board. This software permits downloading
of code from a host system, execution control with breakpoints,
in-line assembly and disassembly, and a variety of commands
to control registers, cache memory, and main memory. lOTI
sim provides all the resources needed to bring up new
hardware and software.
The evaluation kit also includes a complete set of user
documentation forthe 10T/sim software tool. The capabilities
of 10T/sim are described in a separate data sheet.

• 79S341 RISC Evaluation Board
• 10T/c Multi-Host compiler toolchain (IBM PC-compatible
version)
• 10T/sim debug monitor included in board EPROM User's
Manuals for:
- 79S341 board
- R3041

-

10T/c

- 10T/sim
- Applications Guide for R3051 family
• IOT/pci016 software on IBM PC compatible 3.5" disk
format
• 6' cable for serial port from board for connection with 9pin male or 25-pin male connector

BOARD SPECIFICATIONS

IDT/PCI016 TERMINAL EMULATION AND
DOWNLOAD UTILITY SOFTWARE
lOT's PC 16-bit 1/0 Terminal Emulation and Oownload
Utility Software (lOT/pci016) is included on an IBM PC compatible disk for use with an IBM PC AT-Bus compatible (ISA)
machine. IDT/pci016 allows the evaluation board to be operated from the PCIAT ISA backplane. The PCIAT acts as a
video screen and keyboard terminal for the board by communicating through the backplane. IOT/pci016 also includes
download utilities to move s-record files from the PCIAT to the
evaluation board.

7.5

3

fI

IDT79S34FM EVALUATION KIT

CPU
On-chip

COMMERCIAL TEMPERATURE RANGES

20MHZ R3041
2KB I-cache, 512B D-cache

On-Board Memory Capacity:
As shipped (Minimum): DRAM - 256K x 32 (1 MB)
EPROM - 128K x 8 (128KB)
Maximum:
DRAM - 1M x 32 (4MB)
EPROM - 512K x 8 (512KB)
Debug Monitor EPROM: 128K x 8 (128KB) containing
IDT/sim.
Controlled by SCN2681 DUART.
Serial Ports:
CRT Terminal connects to J3.
Software configurable features.
9600 Baud, 8 bits, no parity,
Default state:
1 stop bit.
AUX Download port connects to J4.
Software configurable features:
Default state:
9600 Baud,8 bits, no parity,
1 stop bit.
Serial Port Connectors: Two DTE DB9s (right angle
female) connectors.
Timers:

1. Programmable counter/timer
16-bit timer on 2681 DUART.
2. On-chip R3041 24-bittimer used
for DRAM refresh timer.

Interrupts:

3 synch ronized, 3 unsynchronized
(4 used on-board with 2 spares).

Expansion Connector:

One 96-pin Right angle (male)
DIN compatible. Connects with
96-pin reverse DIN (female). Contains R3052 AID bus, control sig
nals, and Bufferred SysClk.

User Selectable Options:
Standalone vs. PC/AT ISA configuration, PC/AT ISA I/O
address, interrupt number, DRAM size, 32/16/8 DRAM width,
Boot PROM size, Endianess, cache vs. debug mode, Data
Block Refill size
Physical Dimensions:
PC/AT ISA Form Factor compatible: 4.2" x 10.0".
Operating Temperature: ODC to 50 DC
Relative Humidity:
5% - 95%
Power Supply:
5.0V ± 5%, 0.75Amps typical
Power Supply Connection (if used):
One 4-pin power supply
connector (4p-pin PC disk drive)
PC/AT Compatibility (if used): PC/AT 8.33MHz ISA Bus
backplane slot
PC/AT System Requirements (if used):
DOS 3.0 or higher, 640K memory,
3.5" floppy disk drive

ORDERING INFORMATION
Each kit is shipped with an evaluation board, complete
schematics and PLA equations, as well as a complete software development toolchain for "C" language programming.
User's Manuals include instructions on compiling "C" programs, downloading code, and operating the Software Integration Manager.
Evaluation Board
R3041 Evaluation Kit ........................................... 79S341

7.5

4

G

R3081™ EVALUATION KIT

IDT79S381

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• Complete 33MHz RISC System Board
• Supports R3081"', R3052"', R3051"', R3041'" CPUs
• Includes:
- R3081 CPU, with R3041, R3051 and R3071 samples
- 2MB interleaved DRAM, expandable to 4MB, 8MB,
or 16MB
- 256KB zero-wait-state SRAM
- 512KB of EPROM expandable to 1MB or 2MB
- 1024-bit serial EEPROM
- 2 serial ports
- IEEE 802.3 Ethernet subsystem with 8KB dual-port
SRAM expandable to 16KB
- Expansion connector

lOT's R3081 Evaluation Kit is a complete evaluation and
development kit for lOT's R3051 family of RISControllers"'.
Designed to demonstrate the optimal performance of these
RISControllers, zero-wait state memories allow one to see the
true performance of lOT's R3041 , R3051/2, and R3081 devices. For those developing large segments of code, the IEEE
ethernet interface allows for quick downloading of large code
blocks. The system supports up to 16MBytes of DRAM. On top
of the system board with an on-board monitor, lOT's System
Integration Manager (I DT/sim"') , the complete package includes lOT's IDTlc compiler (IDT/c"'), samples of our R3041 ,
R3051 and R3071 devices, and a complete documentation
package including a user's guide, board schematics, and PAL
equations.

FUNCTIONAL BLOCK DIAGRAM

33MHz

m
I\)

JLr

o

R3081E
RISControlier

-0

JJ

Dual
RS232
Serial
Ports

s:

256Kbytes

owait state
SRAM

2M bytes
EPROM

II

OJ

r-------~----------~--~--------~--~------~~
CD
en

V3 DRAM
Controller

OJ ...._ _ _......J
So

~

CJ)

----J

' -_ _ _ _ _ _ _ _

IEEE 803.2

Ethernet

3041 drw 01

The lOT logo Is a roglslored trademark and R3041. R3051 , R3052, R3071 , R3081, R4400, R4600, lOT/kit, IDT/slm, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
©1995 Integrated Device TechnOlogy, Inc.

SEPTEMBER 1995
7.6

DSC-90n/1

1

R3081 EVALUATION KIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
Each kit is shipped with an evaluation board, complete
schematics and PLA equations, as well as a complete software
development toolchain for "G" language programming, downloading code, and operating the Software Integration Manager.
Evaluation Board
R3081 Evaluation Kit. .................................. 79S381

7.6

2

G

Orion™ R4600™ EVALUATION and
DEVELOPMENT PLATFORM

Preliminary

795460

Integrated Device Technology, Inc.

FEATURES:
• Shipped with IDTlsim™ (System Integration Manager) in
EPROM
- High capability debug monitor
- Simplifies software development
• Complete set of documentation included
- Complete set of board schematics
- Complete PAL sources
- Board specifications manual
- Design manual with the theory of operations
- User's manual for IDT/sim

• Complete RISC System Development Board
- Supports R4600 at speeds of 100, 133 or 150 MHz
• Uses a12 pin PC-style power connector with +12V, -12V
and +5V
• System interface and memory system runs at 50MHz
• 2MB minimum of non-interleaved DRAM, expandable to
96MB in 4 SIMMs
- 2 SIMMs for base memory and 2 SIMMs for expansion memory
- Tuned for 60ns DRAMs but can use 70 or 80ns
DRAMs
• 256KB of EPROM, expandable to 1MB
• Ethernet connection (thick net) via the DP83932 SONIC
Controller
• Dual serial ports through NEC 72001 DUART
• Daughter board expansion area
• Provides for logic analyzer connection

DESCRIPTION:
The 79S460 Evaluation Board is a complete design for
evaluating the R4600 hardware and software environment.
The package contains a working system, including schematics and theory of operations, complete documentation, and a
debug monitor for software development.

FUNCTIONAL BLOCK DIAGRAM

CPU R4000PC
or R4400PC
or R4600

Memory Controller
and On-board Memory

fI
EPROM

Expansion
Connector

1/0 Bus Interface

Local 110
(serial. NVRAM. etc.)

Ethernet

3035 drw 01

The IDT logo is

a reg,stered trademark and R4600, R4400, Orion, RISController, and IDT/sim are trademarks 01 Integrated Device Technology, Inc.

SEPTEMBER 1995
©1995 Integrated Device Technology, Inc.

7.7

DSC·907411

PRELIMINARY IDT79S460
Orion™ R4600™ EVALUATION and DEVELOPMENT PLATFORM

COMPLETE SINGLE BOARD COMPUTER
The79S460 is a complete working RISC system intended
as a design example using the R4600 highly integrated CPU.
The board requires only a simple CRT terminal and a PC-style
power supply for operations. While intended to use the R4600,
the board also supports the pin compatible R4400"'PC.
The R4600 Evaluation Board is supplied with 2MB of
DRAM in the base memory SIMM sockets. This can be
upgraded to 32MB for base memory (4Mx36 SIMMs). The
expansion memory SIMMs can provide an additional 64MB of
DRAM. Other hardware on the board includes a NEC 72001
DUART and a DP83932 SONIC Ethernet Controller; both
devices are supported with drivers in IDT/sim. The Ethernet
connection is provided for higher speed download of code to
the board.

The board contains 256KB of EPROM expandable to 1MB
by replacing the given EPROM with a higher density device
and adding the second EPROM. The enclosed EPROM
contains lOT's powerful System Integration Manager (lOTI
sim), a debugging monitor that supports download of code
from host systems, execution control commands, memory
probing and 1/0. The capabilities of IDTlsim are described in
a separate data sheet.
The R4600 Evaluation Board also contains a daughterboard expansion bus. This is controlled by logic similar to a
simplified i486 local bus but is expanded to 64-bits and
operates at 33MHz. Daughter-boards provide slave memory
or registers accessible to the R4600 CPU and can also be
DMA masters capable of reading and writing to memory.

ORDERING INFORMATION
Each unit!s shipped with complete. schematics and PAL ~quations. A user's manual includes instructions on downloading
code, ?peratl~g the Software Integration Manager, and proViding the correct timing interfaces to additional hardware. Boards
are shipped with the R4600 CPU plugged-in, but the R4400PC can also be used. The R4400PC can also be ordered to allow
user upgrades.

EVALUATION BOARD
R4600 Evaluation Kit. ................................................................................................................................................79S460

7.7

2

(;)®

ORION TM79S464 EVALUATION KIT

IDT79S464

Integrated Device Technology. Inc.

FEATURES:

DESCRIPTION:

The major features of the 79S464 R ISController Evaluation
Board include:
• Complete 50MHz RISC system
• Default standalone board configuration for use with
external terminal
• Supports the R4600/R4700/R4650 highly integrated
RISController CPUs
• 4, 16, or 64MByte DRAM, interleaved, 60nsec for 50MHz
bus
• 4MBytes of EPROM, non-interleaved, non-cacheable
• lOT's System Integration Manager (IDT/sim) included in
EPROM
• Two serial RS232 channels (in Cirrus CL-CD1284)
• Intel 82C54 timer for OS interrupt (UNIX, CExec, NT,
etc.)
• Clock, reset, and interrupt generation logic
• P1284 bidirectional interface using the Cirrus CL-CD1284;
supports all 5 modes

The 79S464 Evaluation Board is an example of a complete
working MIPS R4600 RISC System. The board is a low cost
and parts count design example using the highly integrated
R4600 RISController CPU. Primary uses of the board
include:
1. Evaluating the R4600/R4700/R4650 architecture.
2. Prototyping and running software.
The board is highly configurable and contains hardware
options for setting different DRAM sizes and bus speed.
Figure 1 shows a block diagram ofthe 79S464 RiSe evaluation
board.

II

The lOT logo is n fOgictored trademark, and IDTlc, IDTlsim, R3041 , R3051, R3052, R3081, R4400, R4600 RISControlier and RISCore are trademarks of Integrated Device Technology, Inc.

©1995 Integrated Dcvlco IllCllnOlogy

7.8

IDT 795464

EVALUATION BOARD DESCRIPTION

SYSAD ADDRESS
BUFFERS

SYSADDATA
BUFFERS

PROM DATA
BUFFERS

PROM ADDRESS

PROM SIMMs
Bank 1: Hi
Bank 1: La

16260 x 4

DRAM SIMMs (32 bit data)

DRAM DATA
BUFFERS

64

RAS/CAS
Address Muxes

2 x 16501
A

B

PA[31:0]

PERIPHERAL
ADDRESS
BUFFERS

82C54 Timer

64/32
BUS
EXCHANGE

Command/Status Registers

Figure 1 795464 R4600 Evaluation Board Block Diagram

7.8

2

IDT79S464

EVALUATION BOARD DESCRIPTIONS

EXPLANATION OF FEATURES
The 79S464 Evaluation Board is configured as astandalone
board, and requires only a standard RS232-C CRT video
terminal and a 5 volt power supply for operation. The board
can be placed on a flattabletop surface by using the removable
standoffs which are provided for physical support.
The 79S464 board contains two 512Kx32 PROM SIMMs.
Main memory consists of 4, 16, or 64 MBytes, using 256Kx32,
1Mx32, or 4Mx32 DRAM SIMMs. There are two serial ports
and one external timer in addition to the internal timer on the
R4600.
The boot EPROM contains lOT's System Integration
Manager (IDT/sim), a debug monitor kernel that supports
download of code from host systems, remote debug interface,
execution control commands including single stepping and
instruction tracing, memory probing, register probing, linebased assembly, and disassembly of code.
The board supports the use of 32-bit wide DRAM SIMMs
through the use of hardware jumper options. The board can
be populated with up to 4 SIMMs: 256Kx32, 1Mx32, or 4Mx32
DRAM SIMMs. Thus, the board supports from 4 to 64MBytes
of main memory.
A MIPS workstation, SPARCstation, or PC/AT can be

connected to the 79S464 via one of the serial ports and user
developed code (generated using a cross-compiler such as
GNUlGCC++, MIPS/C, or the IDT/c compiler) can be
downloaded to the board.
The 79S464 is designed around the IDT79R4600
RISControlier. The R4600 is a highly integrated version of the
Orion family of RISControliers and includes 16KBytes of on
chip instruction and 16KBytes of on chip data cache. For
further details on the R4600 RISController, please refer to the
R4600lR4700 Hardware User's Manual and the R4600 data
sheet.
The 79S464 can be used to evaluate the performance of the
R4600 orthe R4700. In addition, the 79S461 , when populated
with the R4650, can be plugged into the R4600 CPU socket.
This allows the R4650's performance in the system to be
evaluated as well.
The 79S464 is constructed using both through-hole devices
and surface mount on a 13" x 10" PCB rectangular form factor
laminate board with standoffs, and is intended for use as a
standalone bench top device.

II

Ordering Information:
Each kit is shipped with an evaluation board, complete schematics, and PAL equations, A user's manual includes instructions
on downloading code, operating the Software Integration Manager, and providing the corrent timing interfaces to additional
hardware. Boards are shipped with the R4600 CPU plugged-in.

Evaulation Board
R4600 Evaluation Kit ..... ..... ...... ............ ....... ..... ............................ ................................................... .........

7.8

79S464

3

(;)

IDT79S901

IDTlsim™
SYSTEM INTEGRATION MANAGER
ROMABLE DEBUGGING KERNEL

Integrated Device Technology, Inc.

FEATURES
• Complete source code provided
• Robust debug monitor
• Supports remote source-level debug
GOB-IDT/c tool chain
DBX-MIPS tool chain
• Remote file access-connects target to remote host file
system
• Ethernet and Centronics support for fast download
• Diagnostic tests for memory, cache, MMU, FPA, and
system
• Adaptable to systems with or without hardware floating
point accelerator
• Includes a variety of device drivers
• Easy to add new user interface commands and I/O device
drivers

Powerful Tool for Integration of RISControlier
Based systems
The IOT79S901 System Integration Manager (IOT/sim) is a
ROM able debug monitor product that permits convenient
control and debug of RISC systems built around lOT's R30xx
RISController™, R4400™, R4600™, R4700™ and R4650™
CPUs. Facilities are included to operate the CPU under
controlled conditions: examining and altering the contents of
memory, manipulating and controlling R30xx, R4xxx resources
(such as cache, TLB and coprocessors), loading programs
from host machines, and controlling the path of execution of
loaded programs.
IOT/sim source code includes lOT's MicroMonitor, a very
simple monitor which requires only a UART and ROM to be
functional for performing the initial debugging and integration
of new hardware.

RS232C CABLE
(DOWNLOAD & REMOTE DEBUG)

SYSTEM UNDER
DEVELOPMENT

HOST SYSTEM
( Sun 4, PC-DOS, or MIPS RISC/os)

TARGET WITH IDT/sim in EPROMs
System Integration Manager

2867 drw 01

The IDT logo is a registered trademark. and IDT/c. IDT/sim. R3041. R3051. R3052. R3081. R4400. R4600, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.

SEPTEMBER 1995
©1995 Integrated Device Technology, Inc.

7.9

DSC'904414

1

IDT79S901
IDT/sim SYSTEM INTEGRATION MANAGER

PRODUCT BRIEF

IDT/sim Features

(source-level debug with gdb on and IDT/c Host or dbx on a
MIPS RISC/os system; and Communications (remote file
access, terminal emulator and set baud rate).

IDT/sim is a software tool to help system designers debug
hardware designs and port software to systems based on one
of the R3000 ISA CPUs, R4400, R4600, R4700 and R4650.
The software is supplied in EPROMs on most IDT RISC
Development products, and may be purchased in sourcecode form so it can be modified, compiled and installed on
your system.
IDT/sim provides all the basic functions needed to get a new
hardware design debugged and to port and debug software on
it. Typically, the monitor is compiled and burned into EPROMs
that are plugged into the target system. Approximately 115KB
of EPROM is needed for the binary code, and 71 KB of RAM
is needed for storing variables. Once installed, the designer
communicates with the monitor via a simple terminal connected to an RS-232 port on the target system. Source code
is included to support a variety of UARTs forthis port. On startup, the monitor will determine the cache and main memory
sizes automatically.

Run-Time Support
IDT/sim includes over 50 functions that can be called by user's
programs to perform common I/O and R30xx, R4xxx control
operations. A complete list of commands is listed later in this
document.

Feature Set
R4650 Orion Support: IDT/sim has been upgraded to support the latest 64-bit RISController family member, the
79R4650. This support has been implemented as a series of
"IFDEF" options to the base 32-bit source tree. This approach
allows a common set of features across 32 and 64-bit targets
with a single development environment.
R3710/15 Support: IDT/sim now supports IDT79R371 0/15
Laser printer integrated system controller for IDT R30xx
RISController family. Features supported are: ROM controller, DRAM controller, Centronics, Timer, Printer interface
diagnostics.

Diagnostics
The monitor includes a set of diagnostic routines for testing the
integrity of the hardware. The diagnostic suite includes: main
memory tests which exercise all address and data paths; a
cache memory test which runs memory tests on both caches,
checks tag memory, and verifies that instructions can be
executed from cache; a system test which checks the ability
to read and write full words, half-words, and bytes and checks
the cache operation for valid, hit/miss, and invalidation; a
MMU test which checks the operation of the TLB inside the
CPU; and a Floating Point test which tests the functionality of
the on-chip FPA, including exception interrupts.

Download Support
Object code created on a software development system can
be downloaded in either ASCII S-records or binary formats to
the target system's memory. The code can be produced with
IDT/c, the MIPS RISCross Compiler tools, or several third
party compiler toolchains.
The IDT/sim console may also be used as a terminal to a
software development system accessed through a second
serial port. On targets which implement ethernet, utilities are
also available to support ethernet downloads, and remote file
access.

Debug Commands
A variety of commands are included in IDT/sim to support
software/hardware debug. IDT/sim commands can be grouped
into several categories, including: Execution Control
(breakpoint, call, continue, go, gotill, next, step, unbreak);
Memory Commands (assemble, cache flush, compare, disassemble, dump, dump cache, dump registers, fill, fill registers,
move read/write cache, search and substitute); TLB Commands (dump, flush, map, pid and probe); Remote Debug

lOT MicroMonitor: IDT/sim includes IDT's MicroMonitor, a
very simple monitor for performing the initial debugging of new
hardware.
Source-level Debug: Fully integrated with IDT's new compiler toolchain (IDT/c Version 5.1) which supports sourcelevel debug using gdb. IDT/sim supports gdb as a front end
(with full access to /sim's commands) or use of an ASCII
terminal in a stand-alone mode.
Remote File Access: IDT/sim has implemented features to
allow connection of the target with a remote host file system
allowing file transfer between target and host at run time. As
an example, this can be useful for accessing large data
images residing on a host without linking them with the
application. Ethernet support is also included.
Trace Facility: Traces the memory accesses of a user
program. Provides for tracing the path of execution, readsfrom memory, or writes-to memory. Trace qualifiers allow the
tracing of a specific instruction or class of instructions or
references to particular memory ranges. The user may stop
tracing on the following conditions: trace buffer full, hitting a
breakpoint, executing a specific instruction, or accessing a
specific memory range. The trace buffer contents may be
displayed using standard R30xx, and R4xxx family mnemonics.

7.9

2

II

IDT79S901
IDT/sim SYSTEM INTEGRATION MANAGER

PRODUCT BRIEF

KSEG 1
Unmapped,
Uncached

Physical Address
Ifffffff.---------------------------------~

Virtual Address
bfffffff

lfclffff

bfclffff

IfcOOOOO

bfcOOOOO

USER

CODE
SPACE

.;

aOOl1400

.;
.;
aOOl1400 .,

00011400

aOOOf400

IDT/sim

aOOO0100

RAM

SPACE
00000000

aOOOOOOO

..... .....

..... aOOOOOOO
2867 drw 02

Figure 2 IDT/sim Memory Map

space, and is normally placed in 128KB of EPROM. IDT/sim
uses main memory to store interrupt vectors, variables, and a
stack. Approximately 71 KB of RAM space is reserved for this
data.

Figure 2 shows the memory utilized by IDT/sim. The
EPROM space starts at virtual address bfcOOOOO, which is the
R3000's start-up address. The compiled version of IDT/sim
with all features included occupies about 115KB of EPROM

7.9

3

IDT79S901
IDT/sim SYSTEM INTEGRATION MANAGER

PRODUCT BRIEF

IDT/sim COMMANDS
loadll [options] DEV
Download code to target
movelm [-wl-bl-h]  
Move the block of memory specified by RANGE to
the address specified by destination
nextln [count]
Step over subroutine calls
rad [-ol-dl-h]
Set the default radix to the requested base.
rc [-i] <-wl-bl-h] 
Isolate and read from cache
regsellrs [-cl-h]
Select either the compiler names or the hardware
names for registers
searchlsr [-wl-bl-h]   [mask]
Search area of memory for value.
seg [-OI-11-21-u]
Set the default segment to the requested k-segment.
setbaudlsb DEV
Set the baud rate on a serial channel
stepls []
Single step count times
sub [-wl-hl-bl-II-r] 

Examine and change memory interactively.
t {-a/-ol-el-dl-r RANGEI-w RANGEI-c RANGE/-i INSI-m
MSK}
Trace command
te [-e BPNUM] [-d BPNUM]
Trace conditionally command
te [DEV]
Connects the console port straight though to a
second serial port
tex[RANGE]
Exclude tracing calls to RANGE
tlbdumpltd [RANGE]
Dumps the contents of the TLB
tlbflushltf [RANGE]
Displays the current process identifier ( pid )
tlbmapltm [-i index] [-ndgv]  
Virtual-to-physical mapping of the TLB
tlbpidlti [pid]
Set/display TLB PID
tlbptovltpltm 
Probe the TLB
ts [-bl-fl-ol-r RANGEI-w RANGEI-i INS/-m MSK]
Stop trace command
unbrklub 
Clear breakpoints
we [-i] [-w/-b/-h]  [value_list]
Isolate and write to I or D cache
wtfile  [value_list]
Write file to remote host file system

asm  examine and change memory interactively
using standard assembler mnemonics
benchmarklbm
Facilitates benchmarking
brklb [addresslist]
Set/display breakpoints
cacheflushlcf [-il-d]
Flush the I-cache and/or the D-cache
call1ca 
 [arg1 arg2 ... arg8}
Call subroutine with up-to 8 arguments
checksumlcs
Display the checksums for an address range
comparelcp [-wl-bl-h]  
Compare the block of memory specified by RANGE
to the block of memory that starts at destination
con tIc
Continues execution of the client process from
where it last halted execution.
dbgint/di [<-el-d DEV>]
Debug interrupt enable/disable - allows 'break key'
to generate external interrupt
debugldb [DEV]
Enter remote debug mode
dis 
Disassemble target memory specified by RANGE
disptagldt [-i] RANGE
Displays the instruction or data cache tag values and
data contents
dr [reg#lname\reg_group]
Print out the current contents of register(s)
dt
Dump the trace buffer
dumpld [-wl-h] 
Dump the memory specified by RANGE to the
display
enable DEVICE
Connect to remote hosfor file access
fillIf [-wl-hl-bl-II-r]  [value_list.]
Fills memory specified by range with value_list
fr [-sl-d]  
Fill  with 
golg [-n] 

Start execution at address 

gotilllgt 

Continue execution until address 

helpl? [commandlist]
This command will print out a list of the commands
available in the monitor. If a command list is supplied, only the syntax for the commands in the list is
displayed
historylh
Displays the last 16 commands entered
idb [DEVICE] Connect to remote host source level
debugger.initli
Initialize prom monitor (warm reset)

7.9

4

II

IDT79S901
IDTIsim SYSTEM INTEGRATION MANAGER

PRODUCT BRIEF

RUN TIME SUPPORT ENTRY POINTS
exit
atob
clear_cache
cli
close
exc_ utlb_ code
flush_cache
geCmem_conf
geCrange
getchar
gets
instalL command
insta/Ummediate_int
insta/Lnew_ dev
insta/LnormaLint
ioctl
longjmp
open
printf
putchar
puts
rclose
read
reinit
reset
restart
rfileinit
rgets
rlseek
ropen
rprintf
rread
rwrite
seCmem-conf
setjmp
showcar
sprintf
strcat
strcmp
strcpy
strlen
tokenize
timecstart
timer_stop
write

DEVICE DRIVERS (INCLUDED IN SOURCE
CODE)
68681/2681 DUART
8530 SCC
SCSI
Centronics Parallel
8254 Timer/Counter
8251 UART

7.9

5

IDT79S901
IDTisim SYSTEM INTEGRATION MANAGER

PRODUCT BRIEF

ORDERING INFORMATION
To order an lOT board-level product, see EPROM order codes below. To order 10Tlsim in source code, order the Internal
Use License AND order the software on the appropriate source media. You may also order binary distribution rights for the
run-time version of the monitor. Ask your lOT sales office for information.

LICENSES
Internal Source License .....................................................................................................................................................79S901SL
Permits purchase of up to six copies of source code (any media combination) and use of source code to develop run-time
binaries on up to six machines at a time, but does not permit inclusion of the run time code in an end product. Also purchase
one or more of the Source Media listed below.

Limited Binary Distribution Rights .............................................................................................................................79S901 BDR-L
Extension to Internal Source License to permit inclusion of binary code into end product. Internal Source License must be
referenced on order or ordered simultaneously. This license permits up to 100 copies to be distributed royalty-free. For
additional copies, purchase Unlimited Binary Distribution Rights.

SOURCE MEDIA
10Tlsim source code can be compiled with either the MIPS C-compiler, or with IDT/c version 4.1 or later. Earlier versions
of IDT/c cannot compile this code. The products listed below are media only and must be purchased with license 79S901 SL,
listed above.
Source for 386/486PC, MS-DOS ....................................................................................................................................79S901 DOS
Compile with IDTIc C-Compiler. Shipped with 1.44MB 3.5" diskettes.
Source SUN Machines ...................................................................................................................................................79S901 SUN
Use with MIPS C-Compiler or with fOTIc. Developmental Use License number must be referenced on order, or must be
ordered simultaneously.

II

I

7.9

6

tQ

IOT/e™
Multi-Host GNU C-Compiler System

IOT7S930

Integrated Device Technology. Inc.

OPTIMIZING C·COMPILER SYSTEM:

FEATURES:

IOT/c is a C-compiler system for the lOT RISController'"
• ANSI C-Compliant GNU Compiler, Assembler, Linker, Lifamily of embedded microprocessors, It supports developbrarian, and ANSI Libraries
• Full Oevelopment Environment Including start-up code, ment for any of the MIPS R3000 and R4000 family of
microprocessors and their derivatives, including the lOT
cache management routines, etc.
• Efficient Software Floating Point Emulation Library for sys- Orion Family.
The toolchain has been specifically designed for developtems without hardware FPU. Includes Transcendentals
• GOB Provides full source and assembly level debug through ing and debugging code that runs on a remote target. The
compiler system includes the GNU C-compiler, assembler,
IOT/sim'" interface
T
T
• Sun 4 (Sparc "), PC-OOS ", and SGllrix 5.2T" Host Platforms linker, librarian, and source level debugger. The full GNU
• Fully object code compatible with MIPS RISCross Compil- suite of libraries is included and it is supplemented by the
ersT"
lOT/kif" libraries in binary form.
lOT/kit is a complete set of architecture-specific code
• Supports entire lOT family of MIPS ISA Processors (R3000/
T
T
R3500 T", R3041'", R3051 T", R3052 ., R3071'", R3081 ", (including start-up code, cache and exception management
code, etc.) optimized for RISControlier family development.
R4400T", R4600 T", R4650 T", and R4 700T")
A complete assembly language floating point emulation
library is also included for use in systems without a hardware
FPU. lOT/kit is also available in source form.
IOT/c is available for execution on SunOS™, and SGllrix
5.2 workstations as well as PC-OOS hosts. Other host ports
are available from 3rd parties.
New features in release 5.1/6.1 of IOT/c include an
upgrade to the current release of the GNU compiler suite,
full implementation of gdb support and an improved floating
point emulation library.

Host
DevelopmentSystems
SUNSPARC
MIPS RISC/os
386/486 PC-DOS

The IOTlc Tool Chain

 x, double
rintO----------------------nearest x in dir of round
fmodO -------------------fp remof x/y, sign of x
atanO --------------------tan -1 (x)
cosO ---------------------cos of x
expO --------------------- exponential function el\x
logO ----------------------naturallogarithm In(x), x>o
log100 ------------------base 10 logarithm, x>o
sinO ----------------------sine of x
sqrtO ---------------------square root of x, x>= 0
tanO ----------------------tan of x
xtoiO --------------------- raises x to integer power, i
sim_fpintO -------------simulate IEEE standard trap
sim unint ---------------sim FP Unimplemented Op
log() ----------------------naturallogarithm In(x), x>O
log100 ------------------base 10 logarithm, x>O
log1 pO ------------------Iog (1 + x)
log_LO-----------------og(1 + x) -2s/s
powO -------------------- xl\y
cosO ---------------------cos of x
sinO ----------------------sine of x
sinhO -------------------- hyperbolic sine of x
copysignO -------------- returns x with sign of y
dremO -------------------x - n*y, integer nearest n
finiteO -------------------1 = real x; 0 = INF or NAN x
10gbO --------------------exponent of xl\n
scalbO -------------------x * (2**n) computed for n
sqrtO ---------------------square root of x, x>= 0
tanO ----------------------tan of x
expm1 0 ----------------- exponent (x - 1)
tanhO -------------------- hyperbolic tangent of x
fabsO --------------------absolute value of number
frexpO ------------------- returns mantissa;exp in *ptr
isnanO ------------------tests for floating point NaN
IdexpO ------------------ returns quantity *2l\exp
powO -------------------- xl\y

ANSI STANDARD C LIBRARY

absO --------------------- absolute value of integer
atofO ---------------------fp value of an Ascii string
atoiO --------------------- integer value of Ascii str
atolO ---------------------Iong value of Ascii str
bsearchO ---------------binary search of a array
divO ---------------------- rem & quot of int division
ferrorO ------------------error during a file operation?
atexitO ------------------ routines called at exit time
exitO --------------------- Terminate with status
fopenO ------------------open file/ret file stream ptr.
fcioseO ------------------close a file
fdopenO ---------------- open stream
labsO --------------------absolute value of long arg
IdivO --------------------- rem & quotient of division
freeO --------------------- free allocated memory
maliocO -----------------memory allocation
reallocO ----------------- reallocation of memory
fscanfO ------------------ read data from a file
printfO -------------------display data on the std I/O
qsortO -------------------quick sort routine
randO --------------------generates random number
srandO ------------------seed for random num genr
sbrkO -------------------- mem allocation bp routine
scanfO ------------------read data from standard input
sprintfO -----------------output data into a string
sscanfO -----------------read data from a string
memcmpO -------------compare two memory arrays
memcpyO -------------- memory array copy
memmove() ------------ memory array move
memchrO ---------------ret ptr to first matched char
memsetO ---------------place a char in memory array
strlenO ------------------ return string length
strcmpO ----------------- strings are identical?
strcpyO ------------------copy string
strncpyO ----------------copy n characters of a string
strchrO ------------------ret ptr to first match of a char
strchrO ------------------ret ptr to last match of a char
strcatO ------------------concatenate a strings
strncatO -----------------concatenate strings

7.11

5

IDT79S909
lOT/kit Kernel Integration Toolkit

PRODUCT BRIEF

ORDERING INFORMATION
To order the IDT/kit Developer's Package, order the Internal Source License and order the software on the appropriate
source media. The License Agreement is available from your local IDT sales office and is also published in IDT's
development tools catalog.

LICENSES
Internal Source License ......................................................................................................... 79S909SL
Permits purchase of up to six copies of source code (any media combination) and use of source code
to develop run-time binaries on up to six machines at a time, but does not permit inclusion of the run
time code in an end product.
Limited Binary Distribution Rights ................................................................................. 79S909BDR-L
Extension to Internal Source License to permit inclusion of binary code into end product. Source
License must be referenced on order or ordered simultaneously. This license permits up to 100 copies
to be distributed royalty-free. Additional copies are subject to the royalty.

SOURCE MEDIA
IDT/kit source code can be compiled with either the MIPS C compiler or with IDT/c version 3.5 or later.
Earlier versions of IDT/c cannot compile this code. The products listed below are media only and
must be purchased with license 79S909SL above.
Source for 386, MS-DOS .....................................................................................................79S909DOS
Compile with !OTic C-Compiler. Shipped with 1.44 MB 3.5" diskettes.
Source for SPARe machine ............................................................................................... 79S909SUN
Compile with !OTic C-Compiler. Shipped with 1.44 MB 3.5" diskettes.

7.11

6

I

I
I

One 800# does it all!
Dial 1-800-345-7015 to contact either your local sales office or corporate headquarters.
Dial the 800 number above, then dial "1" for corporate headquarters where an operator will
assist you in contacting technical support or customer service OR dial "2" to be routed to
your local sales office.

DOMESTIC SALES REPRESENTATIVES
ALABAMA
lOT
555 Sparkman Or.,# 1238

Dynasty Components
1 Terrence Matthews
Cresent
Kanata, Ontario K2M 2G3

lOT
18167 U.S. 19 North
Suite 455
Clearwater, FL 34624

Dynasty Components
1870 Sources Boulevard
Suite 202
Pointe Claire, Quebec
Canada H9R 5N4

lOT
1500 N. W. 49th St. # 500
Ft. Lauderdale, FL 33309

Huntsville, AL 35816

ALASKA
Thorson Co. Northwest
12340 NE 8th St., #201
Bellevue, WA 98005

ARIZONA
Western High Tech Mktg.
9414 E. San Salvador, #102
Scottsdale, AZ 85258

ARKANSAS
lOT
(S. Cen. Regional Office)
14285 Midway Rd.,Ste.100
Dallas, TX 75244

CALIFORNIA
lOT
(Corporate Headquarters)
2975 Stender Way
P.O. Box 58015
Santa Clara, CA 95052
lOT
(Western Headquarters)
2590 North First Street
San Jose, CA 95131
lOT
(SW Regional Office)
6 Jenner Dr., Suite 100
Irvine, CA 92718
lOT
(SW Regional Office)
17609 Ventura Blvd., # 100
Encino, CA 91316
Quest-Rep
6494 Weathers PI.,Ste. 200
San Diego, CA 92121

CANADA (EAST.)
Dynasty Components
1140 Morrison Dr., Unit 110
Ottawa, Ontario
Canada K2H 8S9
Dynasty Components
2339 Otani Trail
Mississauga, Ontario
Canada L5H 3N2

CANADA (WEST)
Dynasty Components
2 Mountain River Estates
RP #2, P.O. Box 14, #17
Calgary, Alberta
Canada T2P 2G5

GEORGIA
lOT
(SE Regional Office)
3091 Governors Lake Dr.
Building 100, Suite 500
Norcross, GA 30071

HAWAII

Thorson Pacific
4170 Still Creek Dr. # 200
Burnaby, British Columbia
Canada V5C 6C6

lOT
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052

COLORADO

IDAHO
(NORTHERN)

lOT
(NW Regional Office)
5299 OTC Blvd., Ste. 350
Englewood, CO 80111

Anderson Associates
270 S. Main st. Ste. 108
Bountiful, UT 84010

S-J Mid Atlantic, Inc.
131-0 Gaither Drive
Mt. Laurel, NJ 08054

FLORIDA
lOT
(SE Headquarters)
1413 S. Patrick Dr., Ste.10
Indian Harbor Beach, FL
32937

KENTUCKY
Norm Case Associates
303 Uhl Road
Melbourne, KY 41059

OHMS Technology Inc.
5780 Lincoln Dr. # 400
Edina, MN 55436

MISSISSIPPI
lOT
555 Sparkman Dr. # 1238
Huntsville, AL 35816

LOUISIANA
lOT
(S. Cen. Regional Office)
14285 Midway Rd., #100
Dallas, TX 75244

MISSOURI
Rush & West Associates
2170 Mason Road
St. Louis, MO 63131

MAINE

MONTANA

lOT
(NE Headquarters)
#2 Westboro Business Pk.
200 Friberg PkWay,
Suite 4002
Westboro, MA 01581

Thorson Rocky Mountain
7108 "0" S. Alton Wy, # A
Englewood, CO 80112

NEBRASKA

Thorson Rocky Mountain
1831 E. Fort Union Blvd.
Suite 103
Salt Lake City, UT 84121

lOT
(SE Regional Office)
Horn Point Harbor
105 Eastern Ave., # 201
Annapolis, MO 21403

NEVADA
(NORTHERN)

ILLINOIS

MASSACHUSETTS

lOT
(Central Regional Office)
1375 E. Woodfield Road.
Suite 380
Schaurnburg,IL 60173

lOT
(NE Headquarters)
#2 Westboro Business Pk.
200 Friberg PkWay,
Suite 4002
Westboro, MA 01581

CONNECTICUT

lOT
(SE Regional Office)
Horn Point Harbor
105 Eastern Ave., # 201
Annapolis, MO 21403

Rush & West Associates
333 E. Poplar Street
Olathe, KS 66061

lOT
(N. Cen. Regional Office)
1650 W. 82nd St. #1040
Minneapolis, MN 55431

MARYLAND

IDAHO
(SOUTHERN)

DELAWARE

KANSAS

MINNESOTA

Rush & West Associates
333 E. Poplar St., Ste.C-3
Olathe, KS 66061

Thorson Rocky Mountain
7108 "0" S. Alton Way, #A
Englewood, CO 80112

SJ New England
10 Copper Ridge Circle
Guilford, CT 06437

Rush & West Associates
4537 Brady Street
Davenport, IA 52807

Teq Sales
820 Davis Road, Ste. 304
Elgin, IL 60123

SJ New England
11 Waterman Street
Worchester, MA 01603

INDIANA
Arete Sales
2250 Lake Ave. Suite 255
Ft. Wayne, IN 46805

IOWA
Rep Associates
4905 Lakeside Dr. N.E.
Suite 107
Cedar Rapids, IA 52402

MICHIGAN
Bergin-Milan Group, Ltd.
33900 W. Eight Mile Rd.
Suite 181
Farmington Hills, MI
48335

lOT
(Western Headquarters)
2975 Stender Way
Santa Clara, CA 95052

NEVADA
(SOUTHERN)
Western High Tech Mktg.
9414 E. San Salvador
Suite 206
Scottsdale, AZ 85258

NEW HAMPSHIRE
lOT
(NE Headquarters)
#2 Westboro Business Pk.
200 Friberg PkWay,
Suite 4002
Westboro, .MA 01581

NEW JERSEY
/DT
(SE Regional Office)
One Greentree Centre,
Suite 202
Marlton, NJ 08053
SJ Mid-Atlantic, Inc.
131-D Gaither Drive
Mt. Laurel, NJ 08054

NEW JERSEY
(NORTHERN)
SJ Associates
265 Sunrise HWay, #20
Rockville Centre, NY
11570

Quality Components
500 Helendale Road
Suite 125
Rochester, NY 14609
SJ Associates
265 Sunrise HWay, #20
Rockville Centre, NY
11570

NORTH CAROLINA
lOT
(SE Area Sales)
213 Townsend Court
Cary, NC 27511
/DT
6001 Rambling Hills Drive
Morrisville, NC 27560

NEW MEXICO
Western High Tech Mktg.
9414 E. San Salvador
SUite 206
Scottsdale, AZ 85258

NEW YORK
/DT
(NE Regional Office)
1160 Pittsford Victor Rd.
Bldg. E
Pittsford, NY 14534
Quality Components
3343 Harlem Road
Buffalo, NY 14225

Tingen Technical Sales
304A W. Millbrook Road
Raleigh, NC 27609

NORTH DAKOTA
OHMS Technology Inc.
5780 Lincoln Drive
Suite 400
Edina, MN 55436

OHIO
Norm Case Associates
21010 Center Ridge Road
Rocky River, OH 44116

OKLAHOMA

SOUTH CAROLINA

VERMONT

lOT
(S. Cen. Regional Office)
14285 Midway Road
Suite 100
Dallas, TX 75244

Tingen Technical Sales
304A W. Millbrook Road
Raleigh, NC 27609

/DT
(NE Headquarters)
#2 Westboro Business Pk.
200 Friberg PkWay,
Suite 4002
Westboro, MA 01581

OREGON
lOT
(NW RegionalOffice)
15455 NW Greenbriar
PkWay
Suite 210
Beaverton, OR 97006
Thorson Pacific
9600 S.w. Oak Street
Suite 320
Portland, OR 97223

PENNSYLVANIA
(WESTERN)
Norm Case Associates
21010 Center Ridge Road
Rocky River, OH 44116

PENNSYLVANIA
(EASTERN)
S-J Mid-Atlantic
131-D Gaither Drive
Mt. Laurel, NJ 08054

RHODE ISLAND
lOT
(NE Headquarters)
#2 Westboro Business Pk.
200 Friberg PkWay,
Suite 4002
Westboro, MA 01581

Quality Components
116 E. Fayette Street
Manlius, NY 13104

SOUTH DAKOTA
OHMS Technology Inc.
5780 Lincoln Drive
Suite 400
Edina, MN 55436

TENNESSEE
/DT
555 Sparkman Drive
Suite 1200-0
Huntsville, AL 35816

VIRGINIA
/DT
(SE Regional Office)
Horn Point Harbor
105 Eastern Avenue
Suite201
Annapolis, MD 21403

WASHINGTON
TEXAS
lOT
(S. Cen. Regional Office)
15851 Dallas Parkway
Suite 1100
Dallas, TX 75248
lOT
9430 Research Blvd.
Ste 0400, Echelon IV
Austin, TX 78759

UTAH
Anderson Associates
270 S. Main Street
Suite 108
Bountiful, UT 84010
Thorson Rocky Mountain
5505 South 900 East
Suite 140
Salt Lake City, UT 84117

Thorson Pacific, Inc.
14575 Bel-Red Road
Suite 102
Bellevue, WA 98007

WEST VIRGINIA
Norm Case Associates
21010 Center Ridge Road
Rocky River, OH 44116

WISCONSIN
TEQ Sales
20720 W. Watertown
Road, Suite 201
Waukesha, WI 53186

WYOMING
Thorson Rocky Mountain
7108 "D" S. Alton Way
Suite A
Englewood, CO 80112

INTERNATIONAL SALES REPRESENTATIVES
AVNET Nortec NS
Herlev, Denmark
Tel.: 45-44-92-15-52

AFRICA

CHINA

Prime Source (PTY) Ltd.
Johanesburg, So. Africa
Tel.: 444-7237

Lestina International, Ltd.
Beijing, China, P.R.C.
Tel.: 8610-849-9430

AUSTRALIA

Lestina International, Ltd.
Guangzhou, China, P.R.C
Tel.: 8620-380-7307

AVNET Nortec OY
Helsinki, Finland
Tel.: 358-068-21819

Lestina International, Ltd.
Nanjing, China, P.R.C.
Tel.: 8625-449-1384

FRANCE

GEC Electronics Division
Rydalmere, NSW
Australia
Tel.: 612-638-1999/1888

AUSTRIA
Elbatex GmbH
Vienna, Austria
Tel.: 43-186-32110

BELGIUM
ACALN.V.
Betea Components
Zaventem, Belgium
Tel.: 322-725-1080

Lestina International, Ltd.
Chongqing, China, P.R.C.
Tel.: 8681-531-5258

DENMARK
ARROW-EXACTEC
Skovlunde, Denmark
Tel.: 45-44-927-000

FINLAND

lOT
(So. Europe Reg. Office)
15 Rue du Buisson aux
Fraises
91300 Massy, France
Tel.: 33-1-69-30-89-00
A2M
Bron, France
Tel.: 33-1-72-37-0414

2

A2M
Buc, France
Tel.: 33-1-39-56-8181
A2M
Cesson-Sevigne, France
Tel.: 33-1-99-63-3232

AVNET EMG
Chantillon, France
Tel.: 33-149-652-2750
AVNETEMG
Rognes, France
Tel.: 33-42-50-1805

A2M
Cedex, France
Tel.: 33-1-46-23-79-50

AVNETEMG
Saint-Etienne, France
Tel.: 33-77-79-7970

A2M
Merignac, France
Tel.: 33-1-56-34-1 097

AVNETEMG
Schweiller, France
Tel.: 33-88-82-5514

COMPRESS
Rungis Cedex, France
Tel.: 331-4687-8020
AVNETEMG
Cesson-Sevigne, France
Tel.: 33-99-83-9898

GERMANY
/DT
(Cen. Europe Reg. Office)
Gottfried- Von-CrammStr. 1, 85375 Neufahrn,
Germany
Tel.: 49-8165-5024

lOT
c/o Kornblumenstr. 6
74232 Abstatt, Germany
Tel.: 49·7062·90620
lOT
Eggeweg 128
33617 Bielefeld, Germany
Tel.: 49·521·914110

Scantec GmbH
Kirchheim·Teck, Germany
Tel.: 49·70·215·4027

AVNET de Mico
Torino, Italy
Tel.: 31·81·481
AVNET de Mico
Roma, Italy
Tel.: 6·33·32·283

Topas Electronic GmbH
Hannover, Germany
Tel.: 49·51·113·1217

AVNET E2000
Berlin, Germany
Tel.: 30·2110761

AVNET de Mico
Bologna, Italy
Tel.: 51·55·56·14

Topas Electronic GmbH
Quickborn, Germany
Tel.: 49·4106·73097

AVNET E2000
Erkath Dusseldorf,
Germany
Tel.: 211·92003·0

AVNET de Mico
Rubano·Padova, Italy
Tel.: 49·63·35·55

GREECE

AVNET de Mico
Campi Bisenzio, Italy
Tel.: 55·89·41·05

Digital Electronics
Athens, Greece
Tel.: 30·1·576·5754

AVNET E2000
Frankfurt, Germany
Tel.: 69·973804·0

Lasi Electronica
Bologna, Italy
Tel.: (3951) 353815/
374556

HONG KONG

AVNET E2000
Hamburg, Germany
Tel.: 40·645570

AVNET E2000
Gerlingen, Germany
Tel.: 71·56·356·0

AVNET de Mico
Milano, Italy
Tel.: 2·95·34·36·00

Scantec GmbH
Ruckersdorf, Germany
Tel.: 49·91·157·9529

AVNET E2000
Munchen, Germany
Tel.: 89·45110·01

AVNET E2000
Nurnberg, Germany
Tel.: 911·995161·0

Scantec GmbH
Planegg, Germany
Tel.: 49·859·8021

lOT ASIA L TO.
Unit 1003
China Hong Kong City
Tower 6, 33 Canton Road
Hong Kong
Tel.: 852·2736·0122

Lasi Electronica
Firenze, Italy
Tel.: (3955) 582627
Lasi Electronica
Milano, Italy
Tel.: (39) 266·101370

Lestina International Ltd.
Kowloon, Hong Kong
Tel.: 852·2735·1736

Lasi Electronica
Roma, Italy
Tel.: (19396) 5405301/
5409614

INDIA
Jermyn GmbH
Limburg, Germany
Tel.: 49·6431/508·0
Jermyn GmbH
Pinneberg, Germany
Tel.: 49·40/5282041
Jermyn GmbH
Hermsdorf, Germany
Tel.: 49·3660142374
Jermyn GmbH
Berlin, Germany
Tel.: 49·30/2142056
Jermyn GmbH
Dusseldorf, Germany
Tel.: 49·211/25001·0
Jermyn GmbH
Heimstetten, Germany
49·89/909903·0
Jermyn GmbH
Herrenberg, Germany
Tel.: 49·7032/203·01

Techno Trends
San Jose, CA
Tel.: (408) 294·2833

Lasi Electronica
Torino, Italy
Tel.: (3911) 328588/
359277

Sritech Information
Technology, Inc
Javanagar, Bangalore
0812·643608

JAPAN
10TKK
(Japan Headquarters)
Sumitomo Fudosan
Sanbacho Bldg.
6·26 Sanbacho
Chiyoda·Ku
Tokyo 102, Japan
Tel.: 813·3221·9821

ISRAEL
Vectronics, Ltd.
Herzlia, Israel
Tel.: 972·9·55·60·70

ITALY
lOT
(lOT Italia S.r.L.)
Central Oirezionale
Colleoni
Palazzo Astrolabio
Via Cardano 2
20041 Agrate Brianza,ltaly

Dia Semicon Systems
Yokohama, Japan
Tel.: 045·476·7410

Tachibana Tectron Co.,
Ltd.
Tokyo, Japan
Tel.: 813·3793·1171

KOREA

SWITZERLAND
ElbatexAG
Wettingen, Switzerland
Tel.: 011·41·56275·777

TAIWAN

Uniquest
Seoul, Korea
Tel.: 822·562·8805

NETHERLANDS
ACAL Auriema
Eindhoven, Netherlands
Tel.: 040·502·602

NO. IRELAND
Bloomer Electronics, Ltd.
Craigavon, Co. Armagh, N.
Ireland
Tel.: 762·339818

IDT, Asia
1OF·1, 508, Sect. 5
Chung·Hsaio E. Road
Taipei, Taiwan, R.O.C.
Tel.: 8862·726·7255
Johnson Trading Co.
Taipei, Taiwan
Tel.: 886·273·31211
World Peace Industrial
Co., Ltd.
Nankang, Taipei, Taiwan
Tel: 886·2788·5200

TURKEY
Elektro
Istanbul, Turkey

NORWAY
AVNET Nortec AS
Hvalstad, Norway
Tel.: 47·66·84·62·10

UNITED KINGDOM
lOT
(European Headquarters/
No. Europe Reg. Office)
Prime House
Barnett Wood Lane
Leatherhead
Surrey, UK KT22 70G
Tel.: 44·1372·363339

PORTUGAL
ANATRONIC, SA
Odivelas, Portugal
Tel.: 351·19376267

SINGAPOREI
FAR EAST
Serial System PTE LTD
11 Jalan Mesin 06·00
Singapore 1336
Tel.: 65·280·0200

Avnet Access, Ltd.
Letchworth, Herfordshire,
UK
Tel.: 0462·480888
MicroCall, Ltd.
Thame Oxon, UK
Tel.: 44·844·261·939

SPAIN
Anatronic, SA
Madrid, Spain
Tel.: 34·1·542·5566

M.M.D. Ltd.
Reading, Berkshire, UK
Tel.: 44·734·313232

SWEDEN
lOT
(lOT AB)
Veddestavagen 13
S·175 62 Jarfalla, Sweden
Tel. :468·761-1130

AVNET Nortec AB
Solna, Sweden
Tel.: 468·705·1800

AUTHORIZED DISTRIBUTORS (U.S. and Canada)
Future
Electronics

Hamilton Hallmark

Insight
Electronics

Contact your local office.

Port
Electronics

Wyle
Elecrtonics



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